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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN3/MIMX8MN3_cm7.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN3/MIMX8MN3_cm7.h
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1/*
2** ###################################################################
3** Processors: MIMX8MN3CVTIZ
4** MIMX8MN3DVTJZ
5**
6** Compilers: GNU C Compiler
7** IAR ANSI C/C++ Compiler for ARM
8** Keil ARM C/C++ Compiler
9**
10** Reference manual: MX8MNRM, Rev.A, 04/2019
11** Version: rev. 2.0, 2019-09-23
12** Build: b190830
13**
14** Abstract:
15** CMSIS Peripheral Access Layer for MIMX8MN3_cm7
16**
17** Copyright 1997-2016 Freescale Semiconductor, Inc.
18** Copyright 2016-2019 NXP
19** All rights reserved.
20**
21** SPDX-License-Identifier: BSD-3-Clause
22**
23** http: www.nxp.com
24** mail: [email protected]
25**
26** Revisions:
27** - rev. 1.0 (2019-04-22)
28** Initial version.
29** - rev. 2.0 (2019-09-23)
30** Rev.B Header RFP
31**
32** ###################################################################
33*/
34
35/*!
36 * @file MIMX8MN3_cm7.h
37 * @version 2.0
38 * @date 2019-09-23
39 * @brief CMSIS Peripheral Access Layer for MIMX8MN3_cm7
40 *
41 * CMSIS Peripheral Access Layer for MIMX8MN3_cm7
42 */
43
44#ifndef _MIMX8MN3_CM7_H_
45#define _MIMX8MN3_CM7_H_ /**< Symbol preventing repeated inclusion */
46
47/** Memory map major version (memory maps with equal major version number are
48 * compatible) */
49#define MCU_MEM_MAP_VERSION 0x0200U
50/** Memory map minor version */
51#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
52
53/* ----------------------------------------------------------------------------
54 -- Interrupt vector numbers
55 ---------------------------------------------------------------------------- */
56
57/*!
58 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
59 * @{
60 */
61
62/** Interrupt Number Definitions */
63#define NUMBER_OF_INT_VECTORS 144 /**< Number of interrupts in the Vector table */
64
65typedef enum IRQn
66{
67 /* Auxiliary constants */
68 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
69
70 /* Core interrupts */
71 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
72 HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */
73 MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */
74 BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */
75 UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */
76 SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */
77 DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */
78 PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */
79 SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */
80
81 /* Device specific interrupts */
82 GPR_IRQ_IRQn = 0, /**< GPR Interrupt. Used to notify cores on exception condition while boot. */
83 DAP_IRQn = 1, /**< DAP Interrupt */
84 SDMA1_IRQn = 2, /**< AND of all 48 SDMA1 interrupts (events) from all the channels */
85 GPU3D_IRQn = 3, /**< GPU3D Interrupt */
86 SNVS_IRQn = 4, /**< ON-OFF button press shorter than 5 seconds (pulse event) */
87 LCDIF_IRQn = 5, /**< LCDIF Interrupt */
88 SPDIF1_IRQn = 6, /**< SPDIF1 RZX/TX Interrupt */
89 Reserved23_IRQn = 7, /**< Reserved Interrupt */
90 Reserved24_IRQn = 8, /**< Reserved Interrupt */
91 QOS_IRQn = 9, /**< QOS interrupt */
92 WDOG3_IRQn = 10, /**< Watchdog Timer reset */
93 HS_CP1_IRQn = 11, /**< HS Interrupt Request */
94 APBHDMA_IRQn = 12, /**< GPMI operation channel 0-3 description complete interrupt */
95 Reserved29_IRQn = 13, /**< Reserved */
96 BCH_IRQn = 14, /**< BCH operation complete interrupt */
97 GPMI_IRQn = 15, /**< GPMI operation TIMEOUT ERROR interrupt */
98 ISI_CH0_IRQn = 16, /**< ISI Camera Channel 0 Interrupt */
99 MIPI_CSI1_IRQn = 17, /**< MIPI CSI Interrupt */
100 MIPI_DSI_IRQn = 18, /**< MIPI DSI Interrupt */
101 SNVS_Consolidated_IRQn = 19, /**< SRTC Consolidated Interrupt. Non TZ. */
102 SNVS_Security_IRQn = 20, /**< SRTC Security Interrupt. TZ. */
103 CSU_IRQn =
104 21, /**< CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted. */
105 USDHC1_IRQn = 22, /**< uSDHC1 Enhanced SDHC Interrupt Request */
106 USDHC2_IRQn = 23, /**< uSDHC2 Enhanced SDHC Interrupt Request */
107 USDHC3_IRQn = 24, /**< uSDHC3 Enhanced SDHC Interrupt Request */
108 Reserved41_IRQn = 25, /**< Reserved Interrupt */
109 UART1_IRQn = 26, /**< UART-1 ORed interrupt */
110 UART2_IRQn = 27, /**< UART-2 ORed interrupt */
111 UART3_IRQn = 28, /**< UART-3 ORed interrupt */
112 UART4_IRQn = 29, /**< UART-4 ORed interrupt */
113 Reserved46_IRQn = 30, /**< Reserved Interrupt */
114 ECSPI1_IRQn = 31, /**< ECSPI1 interrupt request line to the core. */
115 ECSPI2_IRQn = 32, /**< ECSPI2 interrupt request line to the core. */
116 ECSPI3_IRQn = 33, /**< ECSPI3 interrupt request line to the core. */
117 SDMA3_IRQn = 34, /**< AND of all 48 SDMA3 interrupts (events) from all the channels */
118 I2C1_IRQn = 35, /**< I2C-1 Interrupt */
119 I2C2_IRQn = 36, /**< I2C-2 Interrupt */
120 I2C3_IRQn = 37, /**< I2C-3 Interrupt */
121 I2C4_IRQn = 38, /**< I2C-4 Interrupt */
122 RDC_IRQn = 39, /**< RDC interrupt */
123 USB1_IRQn = 40, /**< USB1 Interrupt */
124 Reserved57_IRQn = 41, /**< Reserved Interrupt */
125 ISI_CH1_IRQn = 42, /**< ISI Camera Channel 1 Interrupt */
126 ISI_CH2_IRQn = 43, /**< ISI Camera Channel 2 Interrupt */
127 PDM_HWVAD_EVENT_IRQn = 44, /**< Digital Microphone interface voice activity detector event interrupt */
128 PDM_HWVAD_ERROR_IRQn = 45, /**< Digital Microphone interface voice activity detector error interrupt */
129 GPT6_IRQn = 46, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3
130 Interrupt lines */
131 SCTR_IRQ0_IRQn = 47, /**< System Counter Interrupt 0 */
132 SCTR_IRQ1_IRQn = 48, /**< System Counter Interrupt 1 */
133 TEMPMON_LOW_IRQn = 49, /**< TempSensor (Temperature low alarm). */
134 I2S3_IRQn = 50, /**< SAI3 Receive / Transmit Interrupt */
135 GPT5_IRQn = 51, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3
136 Interrupt lines */
137 GPT4_IRQn = 52, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3
138 Interrupt lines */
139 GPT3_IRQn = 53, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3
140 Interrupt lines */
141 GPT2_IRQn = 54, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3
142 Interrupt lines */
143 GPT1_IRQn = 55, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3
144 Interrupt lines */
145 GPIO1_INT7_IRQn = 56, /**< Active HIGH Interrupt from INT7 from GPIO */
146 GPIO1_INT6_IRQn = 57, /**< Active HIGH Interrupt from INT6 from GPIO */
147 GPIO1_INT5_IRQn = 58, /**< Active HIGH Interrupt from INT5 from GPIO */
148 GPIO1_INT4_IRQn = 59, /**< Active HIGH Interrupt from INT4 from GPIO */
149 GPIO1_INT3_IRQn = 60, /**< Active HIGH Interrupt from INT3 from GPIO */
150 GPIO1_INT2_IRQn = 61, /**< Active HIGH Interrupt from INT2 from GPIO */
151 GPIO1_INT1_IRQn = 62, /**< Active HIGH Interrupt from INT1 from GPIO */
152 GPIO1_INT0_IRQn = 63, /**< Active HIGH Interrupt from INT0 from GPIO */
153 GPIO1_Combined_0_15_IRQn = 64, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
154 GPIO1_Combined_16_31_IRQn = 65, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
155 GPIO2_Combined_0_15_IRQn = 66, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
156 GPIO2_Combined_16_31_IRQn = 67, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */
157 GPIO3_Combined_0_15_IRQn = 68, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */
158 GPIO3_Combined_16_31_IRQn = 69, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */
159 GPIO4_Combined_0_15_IRQn = 70, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */
160 GPIO4_Combined_16_31_IRQn = 71, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */
161 GPIO5_Combined_0_15_IRQn = 72, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
162 GPIO5_Combined_16_31_IRQn = 73, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */
163 Reserved90_IRQn = 74, /**< Reserved interrupt */
164 Reserved91_IRQn = 75, /**< Reserved interrupt */
165 Reserved92_IRQn = 76, /**< Reserved interrupt */
166 Reserved93_IRQn = 77, /**< Reserved interrupt */
167 WDOG1_IRQn = 78, /**< Watchdog Timer reset */
168 WDOG2_IRQn = 79, /**< Watchdog Timer reset */
169 Reserved96_IRQn = 80, /**< Reserved interrupt */
170 PWM1_IRQn = 81, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO
171 Waterlevel crossing interrupt line. */
172 PWM2_IRQn = 82, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO
173 Waterlevel crossing interrupt line. */
174 PWM3_IRQn = 83, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO
175 Waterlevel crossing interrupt line. */
176 PWM4_IRQn = 84, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO
177 Waterlevel crossing interrupt line. */
178 CCM_IRQ1_IRQn = 85, /**< CCM Interrupt Request 1 */
179 CCM_IRQ2_IRQn = 86, /**< CCM Interrupt Request 2 */
180 GPC_IRQn = 87, /**< GPC Interrupt Request 1 */
181 MU_A53_IRQn = 88, /**< Interrupt to A53 */
182 SRC_IRQn = 89, /**< SRC interrupt request */
183 I2S56_IRQn = 90, /**< SAI5/6 Receive / Transmit Interrupt */
184 RTIC_IRQn = 91, /**< RTIC Interrupt */
185 CPU_PerformanceUnit_IRQn = 92, /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[n] */
186 CPU_CTI_Trigger_IRQn = 93, /**< CTI trigger outputs (internal: nCTIIRQ[n] */
187 SRC_Combined_IRQn = 94, /**< Combined CPU wdog interrupts (4x) out of SRC. */
188 Reserved111_IRQn = 95, /**< Reserved Interrupt */
189 I2S2_IRQn = 96, /**< SAI2 Receive / Transmit Interrupt */
190 MU_M7_IRQn = 97, /**< Interrupt to M7 */
191 DDR_PerformanceMonitor_IRQn = 98, /**< ddr Interrupt for performance monitor */
192 DDR_IRQn = 99, /**< ddr Interrupt */
193 Reserved116_IRQn = 100, /**< Reserved interrupt */
194 CPU_Error_AXI_IRQn = 101, /**< CPU Error indicator for AXI transaction with a write response error condition */
195 CPU_Error_L2RAM_IRQn = 102, /**< CPU Error indicator for L2 RAM double-bit ECC error */
196 SDMA2_IRQn = 103, /**< AND of all 48 SDMA2 interrupts (events) from all the channels */
197 SJC_IRQn = 104, /**< Interrupt triggered by SJC register */
198 CAAM_IRQ0_IRQn = 105, /**< CAAM interrupt queue for JQ */
199 CAAM_IRQ1_IRQn = 106, /**< CAAM interrupt queue for JQ */
200 QSPI_IRQn = 107, /**< QSPI Interrupt */
201 TZASC_IRQn = 108, /**< TZASC (PL380) interrupt */
202 PDM_EVENT_IRQn = 109, /**< Digital Microphone interface interrupt */
203 PDM_ERROR_IRQn = 110, /**< Digital Microphone interface error interrupt */
204 I2S7_IRQn = 111, /**< SAI7 Receive / Transmit Interrupt */
205 PERFMON1_IRQn = 112, /**< General Interrupt */
206 PERFMON2_IRQn = 113, /**< General Interrupt */
207 CAAM_IRQ2_IRQn = 114, /**< CAAM interrupt queue for JQ */
208 CAAM_ERROR_IRQn = 115, /**< Recoverable error interrupt */
209 HS_CP0_IRQn = 116, /**< HS Interrupt Request */
210 CM7_CTI_IRQn = 117, /**< CTI trigger outputs from CM7 platform */
211 ENET_MAC0_Rx_Tx_Done1_IRQn = 118, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */
212 ENET_MAC0_Rx_Tx_Done2_IRQn = 119, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */
213 ENET_IRQn = 120, /**< MAC 0 IRQ */
214 ENET_1588_IRQn = 121, /**< MAC 0 1588 Timer Interrupt - synchronous */
215 ASRC_IRQn = 122, /**< ASRC Interrupt */
216 Reserved139_IRQn = 123, /**< Reserved Interrupt */
217 Reserved140_IRQn = 124, /**< Reserved Interrupt */
218 Reserved141_IRQn = 125, /**< Reserved Interrupt */
219 ISI_CH3_IRQn = 126, /**< ISI Camera Channel 3 Interrupt */
220 Reserved143_IRQn = 127 /**< Reserved Interrupt */
221} IRQn_Type;
222
223/*!
224 * @}
225 */ /* end of group Interrupt_vector_numbers */
226
227/* ----------------------------------------------------------------------------
228 -- Cortex M7 Core Configuration
229 ---------------------------------------------------------------------------- */
230
231/*!
232 * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration
233 * @{
234 */
235
236#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
237#define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */
238#define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */
239#define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */
240#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
241#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
242#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
243
244#include "core_cm7.h" /* Core Peripheral Access Layer */
245#include "system_MIMX8MN3_cm7.h" /* Device specific configuration file */
246
247/*!
248 * @}
249 */ /* end of group Cortex_Core_Configuration */
250
251/* ----------------------------------------------------------------------------
252 -- Mapping Information
253 ---------------------------------------------------------------------------- */
254
255/*!
256 * @addtogroup Mapping_Information Mapping Information
257 * @{
258 */
259
260/** Mapping Information */
261/*!
262 * @addtogroup iomuxc_pads
263 * @{ */
264
265/*******************************************************************************
266 * Definitions
267 *******************************************************************************/
268
269/*!
270 * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
271 *
272 * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
273 */
274typedef enum _iomuxc_sw_mux_ctl_pad
275{
276 kIOMUXC_SW_MUX_CTL_PAD_BOOT_MODE2 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
277 kIOMUXC_SW_MUX_CTL_PAD_BOOT_MODE3 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
278 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
279 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
280 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
281 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
282 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */
283 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */
284 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */
285 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */
286 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */
287 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */
288 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
289 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
290 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
291 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
292 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */
293 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */
294 kIOMUXC_SW_MUX_CTL_PAD_ENET_MDC = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */
295 kIOMUXC_SW_MUX_CTL_PAD_ENET_MDIO = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */
296 kIOMUXC_SW_MUX_CTL_PAD_ENET_TD3 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */
297 kIOMUXC_SW_MUX_CTL_PAD_ENET_TD2 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */
298 kIOMUXC_SW_MUX_CTL_PAD_ENET_TD1 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */
299 kIOMUXC_SW_MUX_CTL_PAD_ENET_TD0 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */
300 kIOMUXC_SW_MUX_CTL_PAD_ENET_TX_CTL = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */
301 kIOMUXC_SW_MUX_CTL_PAD_ENET_TXC = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */
302 kIOMUXC_SW_MUX_CTL_PAD_ENET_RX_CTL = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */
303 kIOMUXC_SW_MUX_CTL_PAD_ENET_RXC = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */
304 kIOMUXC_SW_MUX_CTL_PAD_ENET_RD0 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */
305 kIOMUXC_SW_MUX_CTL_PAD_ENET_RD1 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */
306 kIOMUXC_SW_MUX_CTL_PAD_ENET_RD2 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */
307 kIOMUXC_SW_MUX_CTL_PAD_ENET_RD3 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */
308 kIOMUXC_SW_MUX_CTL_PAD_SD1_CLK = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */
309 kIOMUXC_SW_MUX_CTL_PAD_SD1_CMD = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */
310 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */
311 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */
312 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */
313 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */
314 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA4 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */
315 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA5 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */
316 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA6 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */
317 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA7 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */
318 kIOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */
319 kIOMUXC_SW_MUX_CTL_PAD_SD1_STROBE = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */
320 kIOMUXC_SW_MUX_CTL_PAD_SD2_CD_B = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */
321 kIOMUXC_SW_MUX_CTL_PAD_SD2_CLK = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */
322 kIOMUXC_SW_MUX_CTL_PAD_SD2_CMD = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */
323 kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */
324 kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */
325 kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */
326 kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */
327 kIOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */
328 kIOMUXC_SW_MUX_CTL_PAD_SD2_WP = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */
329 kIOMUXC_SW_MUX_CTL_PAD_NAND_ALE = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */
330 kIOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */
331 kIOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */
332 kIOMUXC_SW_MUX_CTL_PAD_NAND_CE2_B = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */
333 kIOMUXC_SW_MUX_CTL_PAD_NAND_CE3_B = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */
334 kIOMUXC_SW_MUX_CTL_PAD_NAND_CLE = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */
335 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */
336 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */
337 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */
338 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */
339 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */
340 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */
341 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */
342 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */
343 kIOMUXC_SW_MUX_CTL_PAD_NAND_DQS = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */
344 kIOMUXC_SW_MUX_CTL_PAD_NAND_RE_B = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */
345 kIOMUXC_SW_MUX_CTL_PAD_NAND_READY_B = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */
346 kIOMUXC_SW_MUX_CTL_PAD_NAND_WE_B = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */
347 kIOMUXC_SW_MUX_CTL_PAD_NAND_WP_B = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */
348 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */
349 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXC = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */
350 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD0 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */
351 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD1 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */
352 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD2 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */
353 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD3 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */
354 kIOMUXC_SW_MUX_CTL_PAD_SAI5_MCLK = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */
355 kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */
356 kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXC = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */
357 kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXD0 = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */
358 kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXFS = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */
359 kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXC = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */
360 kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXD0 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */
361 kIOMUXC_SW_MUX_CTL_PAD_SAI2_MCLK = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */
362 kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXFS = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */
363 kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXC = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */
364 kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXD = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */
365 kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */
366 kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXC = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */
367 kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXD = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */
368 kIOMUXC_SW_MUX_CTL_PAD_SAI3_MCLK = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */
369 kIOMUXC_SW_MUX_CTL_PAD_SPDIF_TX = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */
370 kIOMUXC_SW_MUX_CTL_PAD_SPDIF_RX = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */
371 kIOMUXC_SW_MUX_CTL_PAD_SPDIF_EXT_CLK = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */
372 kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */
373 kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */
374 kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */
375 kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */
376 kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */
377 kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */
378 kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */
379 kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 = 124U, /**< IOMUXC SW_MUX_CTL_PAD index */
380 kIOMUXC_SW_MUX_CTL_PAD_I2C1_SCL = 125U, /**< IOMUXC SW_MUX_CTL_PAD index */
381 kIOMUXC_SW_MUX_CTL_PAD_I2C1_SDA = 126U, /**< IOMUXC SW_MUX_CTL_PAD index */
382 kIOMUXC_SW_MUX_CTL_PAD_I2C2_SCL = 127U, /**< IOMUXC SW_MUX_CTL_PAD index */
383 kIOMUXC_SW_MUX_CTL_PAD_I2C2_SDA = 128U, /**< IOMUXC SW_MUX_CTL_PAD index */
384 kIOMUXC_SW_MUX_CTL_PAD_I2C3_SCL = 129U, /**< IOMUXC SW_MUX_CTL_PAD index */
385 kIOMUXC_SW_MUX_CTL_PAD_I2C3_SDA = 130U, /**< IOMUXC SW_MUX_CTL_PAD index */
386 kIOMUXC_SW_MUX_CTL_PAD_I2C4_SCL = 131U, /**< IOMUXC SW_MUX_CTL_PAD index */
387 kIOMUXC_SW_MUX_CTL_PAD_I2C4_SDA = 132U, /**< IOMUXC SW_MUX_CTL_PAD index */
388 kIOMUXC_SW_MUX_CTL_PAD_UART1_RXD = 133U, /**< IOMUXC SW_MUX_CTL_PAD index */
389 kIOMUXC_SW_MUX_CTL_PAD_UART1_TXD = 134U, /**< IOMUXC SW_MUX_CTL_PAD index */
390 kIOMUXC_SW_MUX_CTL_PAD_UART2_RXD = 135U, /**< IOMUXC SW_MUX_CTL_PAD index */
391 kIOMUXC_SW_MUX_CTL_PAD_UART2_TXD = 136U, /**< IOMUXC SW_MUX_CTL_PAD index */
392 kIOMUXC_SW_MUX_CTL_PAD_UART3_RXD = 137U, /**< IOMUXC SW_MUX_CTL_PAD index */
393 kIOMUXC_SW_MUX_CTL_PAD_UART3_TXD = 138U, /**< IOMUXC SW_MUX_CTL_PAD index */
394 kIOMUXC_SW_MUX_CTL_PAD_UART4_RXD = 139U, /**< IOMUXC SW_MUX_CTL_PAD index */
395 kIOMUXC_SW_MUX_CTL_PAD_UART4_TXD = 140U, /**< IOMUXC SW_MUX_CTL_PAD index */
396} iomuxc_sw_mux_ctl_pad_t;
397
398/*!
399 * @addtogroup iomuxc_pads
400 * @{ */
401
402/*******************************************************************************
403 * Definitions
404 *******************************************************************************/
405
406/*!
407 * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
408 *
409 * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
410 */
411typedef enum _iomuxc_sw_pad_ctl_pad
412{
413 kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */
414 kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */
415 kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE2 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */
416 kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE3 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */
417 kIOMUXC_SW_PAD_CTL_PAD_JTAG_MOD = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */
418 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDI = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */
419 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TMS = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */
420 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TCK = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */
421 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDO = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */
422 kIOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */
423 kIOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */
424 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */
425 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */
426 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */
427 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */
428 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */
429 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */
430 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */
431 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */
432 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */
433 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */
434 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */
435 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */
436 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */
437 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */
438 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */
439 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */
440 kIOMUXC_SW_PAD_CTL_PAD_ENET_MDC = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */
441 kIOMUXC_SW_PAD_CTL_PAD_ENET_MDIO = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */
442 kIOMUXC_SW_PAD_CTL_PAD_ENET_TD3 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */
443 kIOMUXC_SW_PAD_CTL_PAD_ENET_TD2 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */
444 kIOMUXC_SW_PAD_CTL_PAD_ENET_TD1 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */
445 kIOMUXC_SW_PAD_CTL_PAD_ENET_TD0 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */
446 kIOMUXC_SW_PAD_CTL_PAD_ENET_TX_CTL = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */
447 kIOMUXC_SW_PAD_CTL_PAD_ENET_TXC = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */
448 kIOMUXC_SW_PAD_CTL_PAD_ENET_RX_CTL = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */
449 kIOMUXC_SW_PAD_CTL_PAD_ENET_RXC = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */
450 kIOMUXC_SW_PAD_CTL_PAD_ENET_RD0 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */
451 kIOMUXC_SW_PAD_CTL_PAD_ENET_RD1 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */
452 kIOMUXC_SW_PAD_CTL_PAD_ENET_RD2 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */
453 kIOMUXC_SW_PAD_CTL_PAD_ENET_RD3 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */
454 kIOMUXC_SW_PAD_CTL_PAD_SD1_CLK = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */
455 kIOMUXC_SW_PAD_CTL_PAD_SD1_CMD = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */
456 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */
457 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */
458 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */
459 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */
460 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA4 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */
461 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA5 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */
462 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA6 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */
463 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA7 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */
464 kIOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */
465 kIOMUXC_SW_PAD_CTL_PAD_SD1_STROBE = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */
466 kIOMUXC_SW_PAD_CTL_PAD_SD2_CD_B = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */
467 kIOMUXC_SW_PAD_CTL_PAD_SD2_CLK = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */
468 kIOMUXC_SW_PAD_CTL_PAD_SD2_CMD = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */
469 kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */
470 kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */
471 kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */
472 kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */
473 kIOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */
474 kIOMUXC_SW_PAD_CTL_PAD_SD2_WP = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */
475 kIOMUXC_SW_PAD_CTL_PAD_NAND_ALE = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */
476 kIOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */
477 kIOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */
478 kIOMUXC_SW_PAD_CTL_PAD_NAND_CE2_B = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */
479 kIOMUXC_SW_PAD_CTL_PAD_NAND_CE3_B = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */
480 kIOMUXC_SW_PAD_CTL_PAD_NAND_CLE = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */
481 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */
482 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */
483 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */
484 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */
485 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */
486 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */
487 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */
488 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */
489 kIOMUXC_SW_PAD_CTL_PAD_NAND_DQS = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */
490 kIOMUXC_SW_PAD_CTL_PAD_NAND_RE_B = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */
491 kIOMUXC_SW_PAD_CTL_PAD_NAND_READY_B = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */
492 kIOMUXC_SW_PAD_CTL_PAD_NAND_WE_B = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */
493 kIOMUXC_SW_PAD_CTL_PAD_NAND_WP_B = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */
494 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXFS = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */
495 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXC = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */
496 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD0 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */
497 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD1 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */
498 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD2 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */
499 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD3 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */
500 kIOMUXC_SW_PAD_CTL_PAD_SAI5_MCLK = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */
501 kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXFS = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */
502 kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXC = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */
503 kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXD0 = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */
504 kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXFS = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */
505 kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXC = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */
506 kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXD0 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */
507 kIOMUXC_SW_PAD_CTL_PAD_SAI2_MCLK = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */
508 kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXFS = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */
509 kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXC = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */
510 kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXD = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */
511 kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXFS = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */
512 kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXC = 124U, /**< IOMUXC SW_PAD_CTL_PAD index */
513 kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXD = 125U, /**< IOMUXC SW_PAD_CTL_PAD index */
514 kIOMUXC_SW_PAD_CTL_PAD_SAI3_MCLK = 126U, /**< IOMUXC SW_PAD_CTL_PAD index */
515 kIOMUXC_SW_PAD_CTL_PAD_SPDIF_TX = 127U, /**< IOMUXC SW_PAD_CTL_PAD index */
516 kIOMUXC_SW_PAD_CTL_PAD_SPDIF_RX = 128U, /**< IOMUXC SW_PAD_CTL_PAD index */
517 kIOMUXC_SW_PAD_CTL_PAD_SPDIF_EXT_CLK = 129U, /**< IOMUXC SW_PAD_CTL_PAD index */
518 kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK = 130U, /**< IOMUXC SW_PAD_CTL_PAD index */
519 kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI = 131U, /**< IOMUXC SW_PAD_CTL_PAD index */
520 kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO = 132U, /**< IOMUXC SW_PAD_CTL_PAD index */
521 kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0 = 133U, /**< IOMUXC SW_PAD_CTL_PAD index */
522 kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK = 134U, /**< IOMUXC SW_PAD_CTL_PAD index */
523 kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI = 135U, /**< IOMUXC SW_PAD_CTL_PAD index */
524 kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO = 136U, /**< IOMUXC SW_PAD_CTL_PAD index */
525 kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0 = 137U, /**< IOMUXC SW_PAD_CTL_PAD index */
526 kIOMUXC_SW_PAD_CTL_PAD_I2C1_SCL = 138U, /**< IOMUXC SW_PAD_CTL_PAD index */
527 kIOMUXC_SW_PAD_CTL_PAD_I2C1_SDA = 139U, /**< IOMUXC SW_PAD_CTL_PAD index */
528 kIOMUXC_SW_PAD_CTL_PAD_I2C2_SCL = 140U, /**< IOMUXC SW_PAD_CTL_PAD index */
529 kIOMUXC_SW_PAD_CTL_PAD_I2C2_SDA = 141U, /**< IOMUXC SW_PAD_CTL_PAD index */
530 kIOMUXC_SW_PAD_CTL_PAD_I2C3_SCL = 142U, /**< IOMUXC SW_PAD_CTL_PAD index */
531 kIOMUXC_SW_PAD_CTL_PAD_I2C3_SDA = 143U, /**< IOMUXC SW_PAD_CTL_PAD index */
532 kIOMUXC_SW_PAD_CTL_PAD_I2C4_SCL = 144U, /**< IOMUXC SW_PAD_CTL_PAD index */
533 kIOMUXC_SW_PAD_CTL_PAD_I2C4_SDA = 145U, /**< IOMUXC SW_PAD_CTL_PAD index */
534 kIOMUXC_SW_PAD_CTL_PAD_UART1_RXD = 146U, /**< IOMUXC SW_PAD_CTL_PAD index */
535 kIOMUXC_SW_PAD_CTL_PAD_UART1_TXD = 147U, /**< IOMUXC SW_PAD_CTL_PAD index */
536 kIOMUXC_SW_PAD_CTL_PAD_UART2_RXD = 148U, /**< IOMUXC SW_PAD_CTL_PAD index */
537 kIOMUXC_SW_PAD_CTL_PAD_UART2_TXD = 149U, /**< IOMUXC SW_PAD_CTL_PAD index */
538 kIOMUXC_SW_PAD_CTL_PAD_UART3_RXD = 150U, /**< IOMUXC SW_PAD_CTL_PAD index */
539 kIOMUXC_SW_PAD_CTL_PAD_UART3_TXD = 151U, /**< IOMUXC SW_PAD_CTL_PAD index */
540 kIOMUXC_SW_PAD_CTL_PAD_UART4_RXD = 152U, /**< IOMUXC SW_PAD_CTL_PAD index */
541 kIOMUXC_SW_PAD_CTL_PAD_UART4_TXD = 153U, /**< IOMUXC SW_PAD_CTL_PAD index */
542} iomuxc_sw_pad_ctl_pad_t;
543
544/* @} */
545
546/*!
547 * @brief Enumeration for the IOMUXC select input
548 *
549 * Defines the enumeration for the IOMUXC select input collections.
550 */
551typedef enum _iomuxc_select_input
552{
553 kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 0U, /**< IOMUXC select input index */
554 kIOMUXC_ENET1_MDIO_SELECT_INPUT = 1U, /**< IOMUXC select input index */
555 kIOMUXC_SAI5_RX_BCLK_SELECT_INPUT = 5U, /**< IOMUXC select input index */
556 kIOMUXC_SAI5_RX_DATA0_SELECT_INPUT = 6U, /**< IOMUXC select input index */
557 kIOMUXC_SAI5_RX_DATA1_SELECT_INPUT = 7U, /**< IOMUXC select input index */
558 kIOMUXC_SAI5_RX_DATA2_SELECT_INPUT = 8U, /**< IOMUXC select input index */
559 kIOMUXC_SAI5_RX_DATA3_SELECT_INPUT = 9U, /**< IOMUXC select input index */
560 kIOMUXC_SAI5_RX_SYNC_SELECT_INPUT = 10U, /**< IOMUXC select input index */
561 kIOMUXC_SAI5_TX_BCLK_SELECT_INPUT = 11U, /**< IOMUXC select input index */
562 kIOMUXC_SAI5_TX_SYNC_SELECT_INPUT = 12U, /**< IOMUXC select input index */
563 kIOMUXC_UART1_RTS_B_SELECT_INPUT = 13U, /**< IOMUXC select input index */
564 kIOMUXC_UART1_RX_SELECT_INPUT = 14U, /**< IOMUXC select input index */
565 kIOMUXC_UART2_RTS_B_SELECT_INPUT = 15U, /**< IOMUXC select input index */
566 kIOMUXC_UART2_RX_SELECT_INPUT = 16U, /**< IOMUXC select input index */
567 kIOMUXC_UART3_RTS_B_SELECT_INPUT = 17U, /**< IOMUXC select input index */
568 kIOMUXC_UART3_RX_SELECT_INPUT = 18U, /**< IOMUXC select input index */
569 kIOMUXC_UART4_RTS_B_SELECT_INPUT = 19U, /**< IOMUXC select input index */
570 kIOMUXC_UART4_RX_SELECT_INPUT = 20U, /**< IOMUXC select input index */
571 kIOMUXC_PDM_BIT_STREAM0_SELECT_INPUT = 30U, /**< IOMUXC select input index */
572 kIOMUXC_PDM_BIT_STREAM1_SELECT_INPUT = 31U, /**< IOMUXC select input index */
573 kIOMUXC_PDM_BIT_STREAM2_SELECT_INPUT = 32U, /**< IOMUXC select input index */
574 kIOMUXC_PDM_BIT_STREAM3_SELECT_INPUT = 33U, /**< IOMUXC select input index */
575 kIOMUXC_USDHC3_DATA7_SELECT_INPUT = 36U, /**< IOMUXC select input index */
576 kIOMUXC_USDHC3_DATA5_SELECT_INPUT = 37U, /**< IOMUXC select input index */
577 kIOMUXC_ENET1_RGMII_RD1_SELECT_INPUT = 38U, /**< IOMUXC select input index */
578 kIOMUXC_USDHC3_DATA4_SELECT_INPUT = 39U, /**< IOMUXC select input index */
579 kIOMUXC_I2C1_SCL_SELECT_INPUT = 40U, /**< IOMUXC select input index */
580 kIOMUXC_I2C2_SDA_SELECT_INPUT = 41U, /**< IOMUXC select input index */
581 kIOMUXC_ECSPI1_SS0_SELECT_INPUT = 42U, /**< IOMUXC select input index */
582 kIOMUXC_SPDIF1_EXT_CLK_SELECT_INPUT = 43U, /**< IOMUXC select input index */
583 kIOMUXC_I2C1_SDA_SELECT_INPUT = 44U, /**< IOMUXC select input index */
584 kIOMUXC_ECSPI2_SS0_SELECT_INPUT = 45U, /**< IOMUXC select input index */
585 kIOMUXC_ENET1_RGMII_RX_CTL_SELECT_INPUT = 46U, /**< IOMUXC select input index */
586 kIOMUXC_ECSPI2_MISO_SELECT_INPUT = 47U, /**< IOMUXC select input index */
587 kIOMUXC_ENET1_RGMII_RD0_SELECT_INPUT = 48U, /**< IOMUXC select input index */
588 kIOMUXC_ECSPI2_SCLK_SELECT_INPUT = 49U, /**< IOMUXC select input index */
589 kIOMUXC_USDHC3_DATA6_SELECT_INPUT = 50U, /**< IOMUXC select input index */
590 kIOMUXC_I2C3_SCL_SELECT_INPUT = 51U, /**< IOMUXC select input index */
591 kIOMUXC_I2C4_SDA_SELECT_INPUT = 52U, /**< IOMUXC select input index */
592 kIOMUXC_ECSPI2_MOSI_SELECT_INPUT = 53U, /**< IOMUXC select input index */
593 kIOMUXC_SAI5_MCLK_SELECT_INPUT = 54U, /**< IOMUXC select input index */
594 kIOMUXC_USDHC3_CD_B_SELECT_INPUT = 55U, /**< IOMUXC select input index */
595 kIOMUXC_USDHC3_STROBE_SELECT_INPUT = 56U, /**< IOMUXC select input index */
596 kIOMUXC_USDHC3_CLK_SELECT_INPUT = 57U, /**< IOMUXC select input index */
597 kIOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT = 58U, /**< IOMUXC select input index */
598 kIOMUXC_ECSPI1_MOSI_SELECT_INPUT = 59U, /**< IOMUXC select input index */
599 kIOMUXC_SAI2_RX_DATA1_SELECT_INPUT = 60U, /**< IOMUXC select input index */
600 kIOMUXC_USDHC3_DATA1_SELECT_INPUT = 61U, /**< IOMUXC select input index */
601 kIOMUXC_USDHC3_DATA0_SELECT_INPUT = 62U, /**< IOMUXC select input index */
602 kIOMUXC_USDHC3_WP_SELECT_INPUT = 63U, /**< IOMUXC select input index */
603 kIOMUXC_I2C3_SDA_SELECT_INPUT = 64U, /**< IOMUXC select input index */
604 kIOMUXC_SAI3_MCLK_SELECT_INPUT = 65U, /**< IOMUXC select input index */
605 kIOMUXC_ECSPI1_MISO_SELECT_INPUT = 66U, /**< IOMUXC select input index */
606 kIOMUXC_ENET1_RX_ER_SELECT_INPUT = 67U, /**< IOMUXC select input index */
607 kIOMUXC_SPDIF1_IN_SELECT_INPUT = 68U, /**< IOMUXC select input index */
608 kIOMUXC_I2C2_SCL_SELECT_INPUT = 69U, /**< IOMUXC select input index */
609 kIOMUXC_I2C4_SCL_SELECT_INPUT = 70U, /**< IOMUXC select input index */
610 kIOMUXC_ECSPI1_SCLK_SELECT_INPUT = 71U, /**< IOMUXC select input index */
611 kIOMUXC_USDHC3_CMD_SELECT_INPUT = 72U, /**< IOMUXC select input index */
612 kIOMUXC_USDHC3_DATA3_SELECT_INPUT = 73U, /**< IOMUXC select input index */
613 kIOMUXC_USDHC3_DATA2_SELECT_INPUT = 74U, /**< IOMUXC select input index */
614 kIOMUXC_GPT1_CLK_SELECT_INPUT = 75U, /**< IOMUXC select input index */
615 kIOMUXC_GPT1_CAPTURE2_SELECT_INPUT = 76U, /**< IOMUXC select input index */
616 kIOMUXC_GPT1_CAPTURE1_SELECT_INPUT = 77U, /**< IOMUXC select input index */
617} iomuxc_select_input_t;
618
619/*!
620 * @addtogroup rdc_mapping
621 * @{
622 */
623
624/*******************************************************************************
625 * Definitions
626 ******************************************************************************/
627
628/*!
629 * @brief Structure for the RDC mapping
630 *
631 * Defines the structure for the RDC resource collections.
632 */
633
634typedef enum _rdc_master
635{
636 kRDC_Master_A53 = 0U, /**< ARM Cortex-A53 RDC Master */
637 kRDC_Master_M7 = 1U, /**< ARM Cortex-M7 RDC Master */
638 kRDC_Reserved0 = 2U, /**< Reserved */
639 kRDC_Master_SDMA3_PERIPH = 3U, /**< SDMA3 PERIPHERAL RDC Master */
640 kRDC_Reserved1 = 4U, /**< Reserved */
641 kRDC_Master_LCDIF = 5U, /**< LCDIF RDC Master */
642 kRDC_Master_ISI = 6U, /**< ISI PORT RDC Master */
643 kRDC_Master_SDMA3_BURST = 7U, /**< SDMA3 BURST RDC Master */
644 kRDC_Master_Coresight = 8U, /**< CORESIGHT RDC Master */
645 kRDC_Master_DAP = 9U, /**< DAP RDC Master */
646 kRDC_Master_CAAM = 10U, /**< CAAM RDC Master */
647 kRDC_Master_SDMA1_PERIPH = 11U, /**< SDMA1 PERIPHERAL RDC Master */
648 kRDC_Master_SDMA1_BURST = 12U, /**< SDMA1 BURST RDC Master */
649 kRDC_Master_APBHDMA = 13U, /**< APBH DMA RDC Master */
650 kRDC_Master_RAWNAND = 14U, /**< RAW NAND RDC Master */
651 kRDC_Master_USDHC1 = 15U, /**< USDHC1 RDC Master */
652 kRDC_Master_USDHC2 = 16U, /**< USDHC2 RDC Master */
653 kRDC_Master_USDHC3 = 17U, /**< USDHC3 RDC Master */
654 kRDC_Master_GPU = 18U, /**< GPU RDC Master */
655 kRDC_Master_USB1 = 19U, /**< USB1 RDC Master */
656 kRDC_Reserved2 = 20U, /**< Reserved */
657 kRDC_Master_TESTPORT = 21U, /**< TESTPORT RDC Master */
658 kRDC_Master_ENET1TX = 22U, /**< ENET1 TX RDC Master */
659 kRDC_Master_ENET1RX = 23U, /**< ENET1 RX RDC Master */
660 kRDC_Master_SDMA2_PERIPH = 24U, /**< SDMA2 PERIPH RDC Master */
661 kRDC_Master_SDMA2_BURST = 24U, /**< SDMA2 BURST RDC Master */
662 kRDC_Master_SDMA2_SPBA2 = 24U, /**< SDMA2 to SPBA2 RDC Master */
663 kRDC_Master_SDMA3_SPBA2 = 25U, /**< SDMA3 to SPBA2 RDC Master */
664 kRDC_Master_SDMA1_SPBA1 = 26U, /**< SDMA1 to SPBA1 RDC Master */
665} rdc_master_t;
666
667typedef enum _rdc_mem
668{
669 kRDC_Mem_MRC0_0 = 0U, /**< DRAM. Region resolution 4KB. */
670 kRDC_Mem_MRC0_1 = 1U,
671 kRDC_Mem_MRC0_2 = 2U,
672 kRDC_Mem_MRC0_3 = 3U,
673 kRDC_Mem_MRC0_4 = 4U,
674 kRDC_Mem_MRC0_5 = 5U,
675 kRDC_Mem_MRC0_6 = 6U,
676 kRDC_Mem_MRC0_7 = 7U,
677 kRDC_Mem_MRC1_0 = 8U, /**< QSPI. Region resolution 4KB. */
678 kRDC_Mem_MRC1_1 = 9U,
679 kRDC_Mem_MRC1_2 = 10U,
680 kRDC_Mem_MRC1_3 = 11U,
681 kRDC_Mem_MRC1_4 = 12U,
682 kRDC_Mem_MRC1_5 = 13U,
683 kRDC_Mem_MRC1_6 = 14U,
684 kRDC_Mem_MRC1_7 = 15U,
685 kRDC_Mem_MRC2_0 = 16U, /**< OCRAM. Region resolution 128B. */
686 kRDC_Mem_MRC2_1 = 17U,
687 kRDC_Mem_MRC2_2 = 18U,
688 kRDC_Mem_MRC2_3 = 19U,
689 kRDC_Mem_MRC2_4 = 20U,
690 kRDC_Mem_MRC3_0 = 21U, /**< OCRAM_S. Region resolution 128B. */
691 kRDC_Mem_MRC3_1 = 22U,
692 kRDC_Mem_MRC3_2 = 23U,
693 kRDC_Mem_MRC3_3 = 24U,
694 kRDC_Mem_MRC3_4 = 25U,
695 kRDC_Mem_MRC4_0 = 26U, /**< TCM. Region resolution 128B. */
696 kRDC_Mem_MRC4_1 = 27U,
697 kRDC_Mem_MRC4_2 = 28U,
698 kRDC_Mem_MRC4_3 = 29U,
699 kRDC_Mem_MRC4_4 = 30U,
700 kRDC_Mem_MRC5_0 = 31U, /**< GIC. Region resolution 4KB. */
701 kRDC_Mem_MRC5_1 = 32U,
702 kRDC_Mem_MRC5_2 = 33U,
703 kRDC_Mem_MRC5_3 = 34U,
704 kRDC_Mem_MRC6_0 = 35U, /**< GPU. Region resolution 4KB. */
705 kRDC_Mem_MRC6_1 = 36U,
706 kRDC_Mem_MRC6_2 = 37U,
707 kRDC_Mem_MRC6_3 = 38U,
708 kRDC_Mem_MRC6_4 = 39U,
709 kRDC_Mem_MRC6_5 = 40U,
710 kRDC_Mem_MRC6_6 = 41U,
711 kRDC_Mem_MRC6_7 = 42U,
712 kRDC_Mem_MRC7_0 = 43U, /**< DEBUG(DAP). Region resolution 4KB. */
713 kRDC_Mem_MRC7_1 = 44U,
714 kRDC_Mem_MRC7_2 = 45U,
715 kRDC_Mem_MRC7_3 = 46U,
716 kRDC_Mem_MRC8_0 = 47U, /**< DDRC(REG). Region resolution 4KB. */
717 kRDC_Mem_MRC8_1 = 48U,
718 kRDC_Mem_MRC8_2 = 49U,
719 kRDC_Mem_MRC8_3 = 50U,
720 kRDC_Mem_MRC8_4 = 51U,
721} rdc_mem_t;
722
723typedef enum _rdc_periph
724{
725 kRDC_Periph_GPIO1 = 0U, /**< GPIO1 RDC Peripheral */
726 kRDC_Periph_GPIO2 = 1U, /**< GPIO2 RDC Peripheral */
727 kRDC_Periph_GPIO3 = 2U, /**< GPIO3 RDC Peripheral */
728 kRDC_Periph_GPIO4 = 3U, /**< GPIO4 RDC Peripheral */
729 kRDC_Periph_GPIO5 = 4U, /**< GPIO5 RDC Peripheral */
730 kRDC_Periph_ANA_TSENSOR = 6U, /**< ANA_TSENSOR RDC Peripheral */
731 kRDC_Periph_ANA_OSC = 7U, /**< ANA_OSC RDC Peripheral */
732 kRDC_Periph_WDOG1 = 8U, /**< WDOG1 RDC Peripheral */
733 kRDC_Periph_WDOG2 = 9U, /**< WDOG2 RDC Peripheral */
734 kRDC_Periph_WDOG3 = 10U, /**< WDOG3 RDC Peripheral */
735 kRDC_Periph_SDMA3 = 11U, /**< SDMA3 RDC Peripheral */
736 kRDC_Periph_SDMA2 = 12U, /**< SDMA2 RDC Peripheral */
737 kRDC_Periph_GPT1 = 13U, /**< GPT1 RDC Peripheral */
738 kRDC_Periph_GPT2 = 14U, /**< GPT2 RDC Peripheral */
739 kRDC_Periph_GPT3 = 15U, /**< GPT3 RDC Peripheral */
740 kRDC_Periph_ROMCP = 17U, /**< ROMCP RDC Peripheral */
741 kRDC_Periph_IOMUXC = 19U, /**< IOMUXC RDC Peripheral */
742 kRDC_Periph_IOMUXC_GPR = 20U, /**< IOMUXC_GPR RDC Peripheral */
743 kRDC_Periph_OCOTP_CTRL = 21U, /**< OCOTP_CTRL RDC Peripheral */
744 kRDC_Periph_ANA_PLL = 22U, /**< ANA_PLL RDC Peripheral */
745 kRDC_Periph_SNVS_HP = 23U, /**< SNVS_HP GPR RDC Peripheral */
746 kRDC_Periph_CCM = 24U, /**< CCM RDC Peripheral */
747 kRDC_Periph_SRC = 25U, /**< SRC RDC Peripheral */
748 kRDC_Periph_GPC = 26U, /**< GPC RDC Peripheral */
749 kRDC_Periph_SEMAPHORE1 = 27U, /**< SEMAPHORE1 RDC Peripheral */
750 kRDC_Periph_SEMAPHORE2 = 28U, /**< SEMAPHORE2 RDC Peripheral */
751 kRDC_Periph_RDC = 29U, /**< RDC RDC Peripheral */
752 kRDC_Periph_CSU = 30U, /**< CSU RDC Peripheral */
753 kRDC_Periph_LCDIF = 32U, /**< LCDIF RDC Peripheral */
754 kRDC_Periph_MIPI_DSI = 33U, /**< MIPI_DSI RDC Peripheral */
755 kRDC_Periph_ISI = 34U, /**< ISI RDC Peripheral */
756 kRDC_Periph_MIPI_CSI = 35U, /**< MIPI_CSI RDC Peripheral */
757 kRDC_Periph_USB1 = 36U, /**< USB1 RDC Peripheral */
758 kRDC_Periph_PWM1 = 38U, /**< PWM1 RDC Peripheral */
759 kRDC_Periph_PWM2 = 39U, /**< PWM2 RDC Peripheral */
760 kRDC_Periph_PWM3 = 40U, /**< PWM3 RDC Peripheral */
761 kRDC_Periph_PWM4 = 41U, /**< PWM4 RDC Peripheral */
762 kRDC_Periph_SYS_COUNTER_RD = 42U, /**< System counter read RDC Peripheral */
763 kRDC_Periph_SYS_COUNTER_CMP = 43U, /**< System counter compare RDC Peripheral */
764 kRDC_Periph_SYS_COUNTER_CTRL = 44U, /**< System counter control RDC Peripheral */
765 kRDC_Periph_GPT6 = 46U, /**< GPT6 RDC Peripheral */
766 kRDC_Periph_GPT5 = 47U, /**< GPT5 RDC Peripheral */
767 kRDC_Periph_GPT4 = 48U, /**< GPT4 RDC Peripheral */
768 kRDC_Periph_TZASC = 56U, /**< TZASC RDC Peripheral */
769 kRDC_Periph_PERFMON1 = 60U, /**< PERFMON1 RDC Peripheral */
770 kRDC_Periph_PERFMON2 = 61U, /**< PERFMON2 RDC Peripheral */
771 kRDC_Periph_PLATFORM_CTRL = 62U, /**< PLATFORM_CTRL RDC Peripheral */
772 kRDC_Periph_QOSC = 63U, /**< QOSC RDC Peripheral */
773 kRDC_Periph_I2C1 = 66U, /**< I2C1 RDC Peripheral */
774 kRDC_Periph_I2C2 = 67U, /**< I2C2 RDC Peripheral */
775 kRDC_Periph_I2C3 = 68U, /**< I2C3 RDC Peripheral */
776 kRDC_Periph_I2C4 = 69U, /**< I2C4 RDC Peripheral */
777 kRDC_Periph_UART4 = 70U, /**< UART4 RDC Peripheral */
778 kRDC_Periph_MU_A = 74U, /**< MU_A RDC Peripheral */
779 kRDC_Periph_MU_B = 75U, /**< MU_B RDC Peripheral */
780 kRDC_Periph_SEMAPHORE_HS = 76U, /**< SEMAPHORE_HS RDC Peripheral */
781 kRDC_Periph_SAI2 = 79U, /**< SAI2 RDC Peripheral */
782 kRDC_Periph_SAI3 = 80U, /**< SAI3 RDC Peripheral */
783 kRDC_Periph_SAI5 = 82U, /**< SAI5 RDC Peripheral */
784 kRDC_Periph_SAI6 = 83U, /**< SAI6 RDC Peripheral */
785 kRDC_Periph_USDHC1 = 84U, /**< USDHC1 RDC Peripheral */
786 kRDC_Periph_USDHC2 = 85U, /**< USDHC2 RDC Peripheral */
787 kRDC_Periph_USDHC3 = 86U, /**< USDHC3 RDC Peripheral */
788 kRDC_Periph_SAI7 = 87U, /**< SAI7 RDC Peripheral */
789 kRDC_Periph_SPBA2 = 90U, /**< SPBA2 RDC Peripheral */
790 kRDC_Periph_QSPI = 91U, /**< QSPI RDC Peripheral */
791 kRDC_Periph_SDMA1 = 93U, /**< SDMA1 RDC Peripheral */
792 kRDC_Periph_ENET1 = 94U, /**< ENET1 RDC Peripheral */
793 kRDC_Periph_SPDIF1 = 97U, /**< SPDIF1 RDC Peripheral */
794 kRDC_Periph_ECSPI1 = 98U, /**< ECSPI1 RDC Peripheral */
795 kRDC_Periph_ECSPI2 = 99U, /**< ECSPI2 RDC Peripheral */
796 kRDC_Periph_ECSPI3 = 100U, /**< ECSPI3 RDC Peripheral */
797 kRDC_Periph_MICFIL = 101U, /**< MICFIL RDC Peripheral */
798 kRDC_Periph_UART1 = 102U, /**< UART1 RDC Peripheral */
799 kRDC_Periph_UART3 = 104U, /**< UART3 RDC Peripheral */
800 kRDC_Periph_UART2 = 105U, /**< UART2 RDC Peripheral */
801 kRDC_Periph_ASRC = 107U, /**< ASRC RDC Peripheral */
802 kRDC_Periph_SPBA1 = 111U, /**< SPBA1 RDC Peripheral */
803 kRDC_Periph_CAAM = 114U, /**< CAAM RDC Peripheral */
804} rdc_periph_t;
805
806/* @} */
807
808/*!
809 * @}
810 */ /* end of group Mapping_Information */
811
812/* ----------------------------------------------------------------------------
813 -- Device Peripheral Access Layer
814 ---------------------------------------------------------------------------- */
815
816/*!
817 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
818 * @{
819 */
820
821/*
822** Start of section using anonymous unions
823*/
824
825#if defined(__ARMCC_VERSION)
826#if (__ARMCC_VERSION >= 6010050)
827#pragma clang diagnostic push
828#else
829#pragma push
830#pragma anon_unions
831#endif
832#elif defined(__GNUC__)
833/* anonymous unions are enabled by default */
834#elif defined(__IAR_SYSTEMS_ICC__)
835#pragma language = extended
836#else
837#error Not supported compiler type
838#endif
839
840/* ----------------------------------------------------------------------------
841 -- AIPSTZ Peripheral Access Layer
842 ---------------------------------------------------------------------------- */
843
844/*!
845 * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer
846 * @{
847 */
848
849/** AIPSTZ - Register Layout Typedef */
850typedef struct
851{
852 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */
853 uint8_t RESERVED_0[60];
854 __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */
855 __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */
856 __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */
857 __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */
858 __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */
859} AIPSTZ_Type;
860
861/* ----------------------------------------------------------------------------
862 -- AIPSTZ Register Masks
863 ---------------------------------------------------------------------------- */
864
865/*!
866 * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks
867 * @{
868 */
869
870/*! @name MPR - Master Priviledge Registers */
871/*! @{ */
872#define AIPSTZ_MPR_MPROT5_MASK (0xF00U)
873#define AIPSTZ_MPR_MPROT5_SHIFT (8U)
874/*! MPROT5
875 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of
876 * the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access
877 * attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses.
878 * 0bxx1x..This master is trusted for write accesses.
879 * 0bx0xx..This master is not trusted for read accesses.
880 * 0bx1xx..This master is trusted for read accesses.
881 * 0b1xxx..Write accesses from this master are allowed to be buffered
882 */
883#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
884#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
885#define AIPSTZ_MPR_MPROT3_SHIFT (16U)
886/*! MPROT3
887 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of
888 * the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access
889 * attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses.
890 * 0bxx1x..This master is trusted for write accesses.
891 * 0bx0xx..This master is not trusted for read accesses.
892 * 0bx1xx..This master is trusted for read accesses.
893 * 0b1xxx..Write accesses from this master are allowed to be buffered
894 */
895#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
896#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
897#define AIPSTZ_MPR_MPROT2_SHIFT (20U)
898/*! MPROT2
899 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of
900 * the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access
901 * attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses.
902 * 0bxx1x..This master is trusted for write accesses.
903 * 0bx0xx..This master is not trusted for read accesses.
904 * 0bx1xx..This master is trusted for read accesses.
905 * 0b1xxx..Write accesses from this master are allowed to be buffered
906 */
907#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
908#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
909#define AIPSTZ_MPR_MPROT1_SHIFT (24U)
910/*! MPROT1
911 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of
912 * the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access
913 * attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses.
914 * 0bxx1x..This master is trusted for write accesses.
915 * 0bx0xx..This master is not trusted for read accesses.
916 * 0bx1xx..This master is trusted for read accesses.
917 * 0b1xxx..Write accesses from this master are allowed to be buffered
918 */
919#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
920#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
921#define AIPSTZ_MPR_MPROT0_SHIFT (28U)
922/*! MPROT0
923 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of
924 * the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access
925 * attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses.
926 * 0bxx1x..This master is trusted for write accesses.
927 * 0bx0xx..This master is not trusted for read accesses.
928 * 0bx1xx..This master is trusted for read accesses.
929 * 0b1xxx..Write accesses from this master are allowed to be buffered
930 */
931#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
932/*! @} */
933
934/*! @name OPACR - Off-Platform Peripheral Access Control Registers */
935/*! @{ */
936#define AIPSTZ_OPACR_OPAC7_MASK (0xFU)
937#define AIPSTZ_OPACR_OPAC7_SHIFT (0U)
938/*! OPAC7
939 * 0bxxx0..Accesses from an untrusted master are allowed.
940 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
941 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
942 * 0bxx0x..This peripheral allows write accesses.
943 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
944 * error response and no peripheral access is initiated on the IPS bus.
945 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
946 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
947 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
948 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
949 * on the IPS bus.
950 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
951 */
952#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
953#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
954#define AIPSTZ_OPACR_OPAC6_SHIFT (4U)
955/*! OPAC6
956 * 0bxxx0..Accesses from an untrusted master are allowed.
957 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
958 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
959 * 0bxx0x..This peripheral allows write accesses.
960 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
961 * error response and no peripheral access is initiated on the IPS bus.
962 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
963 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
964 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
965 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
966 * on the IPS bus.
967 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
968 */
969#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
970#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
971#define AIPSTZ_OPACR_OPAC5_SHIFT (8U)
972/*! OPAC5
973 * 0bxxx0..Accesses from an untrusted master are allowed.
974 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
975 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
976 * 0bxx0x..This peripheral allows write accesses.
977 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
978 * error response and no peripheral access is initiated on the IPS bus.
979 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
980 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
981 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
982 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
983 * on the IPS bus.
984 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
985 */
986#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
987#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
988#define AIPSTZ_OPACR_OPAC4_SHIFT (12U)
989/*! OPAC4
990 * 0bxxx0..Accesses from an untrusted master are allowed.
991 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
992 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
993 * 0bxx0x..This peripheral allows write accesses.
994 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
995 * error response and no peripheral access is initiated on the IPS bus.
996 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
997 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
998 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
999 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1000 * on the IPS bus.
1001 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1002 */
1003#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
1004#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
1005#define AIPSTZ_OPACR_OPAC3_SHIFT (16U)
1006/*! OPAC3
1007 * 0bxxx0..Accesses from an untrusted master are allowed.
1008 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1009 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1010 * 0bxx0x..This peripheral allows write accesses.
1011 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1012 * error response and no peripheral access is initiated on the IPS bus.
1013 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1014 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1015 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1016 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1017 * on the IPS bus.
1018 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1019 */
1020#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
1021#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
1022#define AIPSTZ_OPACR_OPAC2_SHIFT (20U)
1023/*! OPAC2
1024 * 0bxxx0..Accesses from an untrusted master are allowed.
1025 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1026 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1027 * 0bxx0x..This peripheral allows write accesses.
1028 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1029 * error response and no peripheral access is initiated on the IPS bus.
1030 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1031 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1032 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1033 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1034 * on the IPS bus.
1035 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1036 */
1037#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
1038#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
1039#define AIPSTZ_OPACR_OPAC1_SHIFT (24U)
1040/*! OPAC1
1041 * 0bxxx0..Accesses from an untrusted master are allowed.
1042 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1043 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1044 * 0bxx0x..This peripheral allows write accesses.
1045 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1046 * error response and no peripheral access is initiated on the IPS bus.
1047 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1048 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1049 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1050 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1051 * on the IPS bus.
1052 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1053 */
1054#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
1055#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
1056#define AIPSTZ_OPACR_OPAC0_SHIFT (28U)
1057/*! OPAC0
1058 * 0bxxx0..Accesses from an untrusted master are allowed.
1059 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1060 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1061 * 0bxx0x..This peripheral allows write accesses.
1062 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1063 * error response and no peripheral access is initiated on the IPS bus.
1064 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1065 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1066 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1067 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1068 * on the IPS bus.
1069 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1070 */
1071#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
1072/*! @} */
1073
1074/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */
1075/*! @{ */
1076#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
1077#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
1078/*! OPAC15
1079 * 0bxxx0..Accesses from an untrusted master are allowed.
1080 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1081 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1082 * 0bxx0x..This peripheral allows write accesses.
1083 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1084 * error response and no peripheral access is initiated on the IPS bus.
1085 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1086 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1087 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1088 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1089 * on the IPS bus.
1090 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1091 */
1092#define AIPSTZ_OPACR1_OPAC15(x) \
1093 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
1094#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
1095#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
1096/*! OPAC14
1097 * 0bxxx0..Accesses from an untrusted master are allowed.
1098 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1099 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1100 * 0bxx0x..This peripheral allows write accesses.
1101 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1102 * error response and no peripheral access is initiated on the IPS bus.
1103 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1104 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1105 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1106 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1107 * on the IPS bus.
1108 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1109 */
1110#define AIPSTZ_OPACR1_OPAC14(x) \
1111 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
1112#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
1113#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
1114/*! OPAC13
1115 * 0bxxx0..Accesses from an untrusted master are allowed.
1116 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1117 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1118 * 0bxx0x..This peripheral allows write accesses.
1119 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1120 * error response and no peripheral access is initiated on the IPS bus.
1121 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1122 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1123 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1124 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1125 * on the IPS bus.
1126 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1127 */
1128#define AIPSTZ_OPACR1_OPAC13(x) \
1129 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
1130#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
1131#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
1132/*! OPAC12
1133 * 0bxxx0..Accesses from an untrusted master are allowed.
1134 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1135 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1136 * 0bxx0x..This peripheral allows write accesses.
1137 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1138 * error response and no peripheral access is initiated on the IPS bus.
1139 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1140 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1141 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1142 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1143 * on the IPS bus.
1144 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1145 */
1146#define AIPSTZ_OPACR1_OPAC12(x) \
1147 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
1148#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
1149#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
1150/*! OPAC11
1151 * 0bxxx0..Accesses from an untrusted master are allowed.
1152 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1153 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1154 * 0bxx0x..This peripheral allows write accesses.
1155 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1156 * error response and no peripheral access is initiated on the IPS bus.
1157 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1158 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1159 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1160 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1161 * on the IPS bus.
1162 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1163 */
1164#define AIPSTZ_OPACR1_OPAC11(x) \
1165 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
1166#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
1167#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
1168/*! OPAC10
1169 * 0bxxx0..Accesses from an untrusted master are allowed.
1170 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1171 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1172 * 0bxx0x..This peripheral allows write accesses.
1173 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1174 * error response and no peripheral access is initiated on the IPS bus.
1175 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1176 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1177 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1178 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1179 * on the IPS bus.
1180 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1181 */
1182#define AIPSTZ_OPACR1_OPAC10(x) \
1183 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
1184#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
1185#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
1186/*! OPAC9
1187 * 0bxxx0..Accesses from an untrusted master are allowed.
1188 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1189 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1190 * 0bxx0x..This peripheral allows write accesses.
1191 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1192 * error response and no peripheral access is initiated on the IPS bus.
1193 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1194 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1195 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1196 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1197 * on the IPS bus.
1198 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1199 */
1200#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
1201#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
1202#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
1203/*! OPAC8
1204 * 0bxxx0..Accesses from an untrusted master are allowed.
1205 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1206 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1207 * 0bxx0x..This peripheral allows write accesses.
1208 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1209 * error response and no peripheral access is initiated on the IPS bus.
1210 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1211 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1212 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1213 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1214 * on the IPS bus.
1215 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1216 */
1217#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
1218/*! @} */
1219
1220/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */
1221/*! @{ */
1222#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
1223#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
1224/*! OPAC23
1225 * 0bxxx0..Accesses from an untrusted master are allowed.
1226 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1227 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1228 * 0bxx0x..This peripheral allows write accesses.
1229 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1230 * error response and no peripheral access is initiated on the IPS bus.
1231 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1232 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1233 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1234 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1235 * on the IPS bus.
1236 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1237 */
1238#define AIPSTZ_OPACR2_OPAC23(x) \
1239 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
1240#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
1241#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
1242/*! OPAC22
1243 * 0bxxx0..Accesses from an untrusted master are allowed.
1244 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1245 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1246 * 0bxx0x..This peripheral allows write accesses.
1247 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1248 * error response and no peripheral access is initiated on the IPS bus.
1249 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1250 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1251 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1252 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1253 * on the IPS bus.
1254 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1255 */
1256#define AIPSTZ_OPACR2_OPAC22(x) \
1257 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
1258#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
1259#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
1260/*! OPAC21
1261 * 0bxxx0..Accesses from an untrusted master are allowed.
1262 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1263 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1264 * 0bxx0x..This peripheral allows write accesses.
1265 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1266 * error response and no peripheral access is initiated on the IPS bus.
1267 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1268 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1269 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1270 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1271 * on the IPS bus.
1272 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1273 */
1274#define AIPSTZ_OPACR2_OPAC21(x) \
1275 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
1276#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
1277#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
1278/*! OPAC20
1279 * 0bxxx0..Accesses from an untrusted master are allowed.
1280 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1281 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1282 * 0bxx0x..This peripheral allows write accesses.
1283 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1284 * error response and no peripheral access is initiated on the IPS bus.
1285 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1286 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1287 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1288 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1289 * on the IPS bus.
1290 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1291 */
1292#define AIPSTZ_OPACR2_OPAC20(x) \
1293 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
1294#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
1295#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
1296/*! OPAC19
1297 * 0bxxx0..Accesses from an untrusted master are allowed.
1298 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1299 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1300 * 0bxx0x..This peripheral allows write accesses.
1301 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1302 * error response and no peripheral access is initiated on the IPS bus.
1303 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1304 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1305 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1306 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1307 * on the IPS bus.
1308 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1309 */
1310#define AIPSTZ_OPACR2_OPAC19(x) \
1311 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
1312#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
1313#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
1314/*! OPAC18
1315 * 0bxxx0..Accesses from an untrusted master are allowed.
1316 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1317 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1318 * 0bxx0x..This peripheral allows write accesses.
1319 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1320 * error response and no peripheral access is initiated on the IPS bus.
1321 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1322 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1323 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1324 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1325 * on the IPS bus.
1326 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1327 */
1328#define AIPSTZ_OPACR2_OPAC18(x) \
1329 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
1330#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
1331#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
1332/*! OPAC17
1333 * 0bxxx0..Accesses from an untrusted master are allowed.
1334 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1335 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1336 * 0bxx0x..This peripheral allows write accesses.
1337 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1338 * error response and no peripheral access is initiated on the IPS bus.
1339 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1340 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1341 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1342 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1343 * on the IPS bus.
1344 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1345 */
1346#define AIPSTZ_OPACR2_OPAC17(x) \
1347 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
1348#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
1349#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
1350/*! OPAC16
1351 * 0bxxx0..Accesses from an untrusted master are allowed.
1352 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1353 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1354 * 0bxx0x..This peripheral allows write accesses.
1355 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1356 * error response and no peripheral access is initiated on the IPS bus.
1357 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1358 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1359 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1360 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1361 * on the IPS bus.
1362 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1363 */
1364#define AIPSTZ_OPACR2_OPAC16(x) \
1365 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
1366/*! @} */
1367
1368/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */
1369/*! @{ */
1370#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
1371#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
1372/*! OPAC31
1373 * 0bxxx0..Accesses from an untrusted master are allowed.
1374 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1375 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1376 * 0bxx0x..This peripheral allows write accesses.
1377 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1378 * error response and no peripheral access is initiated on the IPS bus.
1379 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1380 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1381 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1382 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1383 * on the IPS bus.
1384 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1385 */
1386#define AIPSTZ_OPACR3_OPAC31(x) \
1387 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
1388#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
1389#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
1390/*! OPAC30
1391 * 0bxxx0..Accesses from an untrusted master are allowed.
1392 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1393 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1394 * 0bxx0x..This peripheral allows write accesses.
1395 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1396 * error response and no peripheral access is initiated on the IPS bus.
1397 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1398 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1399 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1400 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1401 * on the IPS bus.
1402 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1403 */
1404#define AIPSTZ_OPACR3_OPAC30(x) \
1405 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
1406#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
1407#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
1408/*! OPAC29
1409 * 0bxxx0..Accesses from an untrusted master are allowed.
1410 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1411 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1412 * 0bxx0x..This peripheral allows write accesses.
1413 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1414 * error response and no peripheral access is initiated on the IPS bus.
1415 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1416 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1417 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1418 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1419 * on the IPS bus.
1420 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1421 */
1422#define AIPSTZ_OPACR3_OPAC29(x) \
1423 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
1424#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
1425#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
1426/*! OPAC28
1427 * 0bxxx0..Accesses from an untrusted master are allowed.
1428 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1429 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1430 * 0bxx0x..This peripheral allows write accesses.
1431 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1432 * error response and no peripheral access is initiated on the IPS bus.
1433 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1434 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1435 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1436 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1437 * on the IPS bus.
1438 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1439 */
1440#define AIPSTZ_OPACR3_OPAC28(x) \
1441 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
1442#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
1443#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
1444/*! OPAC27
1445 * 0bxxx0..Accesses from an untrusted master are allowed.
1446 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1447 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1448 * 0bxx0x..This peripheral allows write accesses.
1449 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1450 * error response and no peripheral access is initiated on the IPS bus.
1451 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1452 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1453 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1454 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1455 * on the IPS bus.
1456 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1457 */
1458#define AIPSTZ_OPACR3_OPAC27(x) \
1459 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
1460#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
1461#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
1462/*! OPAC26
1463 * 0bxxx0..Accesses from an untrusted master are allowed.
1464 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1465 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1466 * 0bxx0x..This peripheral allows write accesses.
1467 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1468 * error response and no peripheral access is initiated on the IPS bus.
1469 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1470 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1471 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1472 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1473 * on the IPS bus.
1474 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1475 */
1476#define AIPSTZ_OPACR3_OPAC26(x) \
1477 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
1478#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
1479#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
1480/*! OPAC25
1481 * 0bxxx0..Accesses from an untrusted master are allowed.
1482 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1483 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1484 * 0bxx0x..This peripheral allows write accesses.
1485 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1486 * error response and no peripheral access is initiated on the IPS bus.
1487 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1488 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1489 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1490 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1491 * on the IPS bus.
1492 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1493 */
1494#define AIPSTZ_OPACR3_OPAC25(x) \
1495 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
1496#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
1497#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
1498/*! OPAC24
1499 * 0bxxx0..Accesses from an untrusted master are allowed.
1500 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1501 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1502 * 0bxx0x..This peripheral allows write accesses.
1503 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1504 * error response and no peripheral access is initiated on the IPS bus.
1505 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1506 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1507 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1508 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1509 * on the IPS bus.
1510 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1511 */
1512#define AIPSTZ_OPACR3_OPAC24(x) \
1513 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
1514/*! @} */
1515
1516/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */
1517/*! @{ */
1518#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
1519#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
1520/*! OPAC33
1521 * 0bxxx0..Accesses from an untrusted master are allowed.
1522 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1523 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1524 * 0bxx0x..This peripheral allows write accesses.
1525 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1526 * error response and no peripheral access is initiated on the IPS bus.
1527 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1528 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1529 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1530 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1531 * on the IPS bus.
1532 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1533 */
1534#define AIPSTZ_OPACR4_OPAC33(x) \
1535 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
1536#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
1537#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
1538/*! OPAC32
1539 * 0bxxx0..Accesses from an untrusted master are allowed.
1540 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1541 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1542 * 0bxx0x..This peripheral allows write accesses.
1543 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1544 * error response and no peripheral access is initiated on the IPS bus.
1545 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1546 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1547 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1548 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1549 * on the IPS bus.
1550 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1551 */
1552#define AIPSTZ_OPACR4_OPAC32(x) \
1553 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
1554/*! @} */
1555
1556/*!
1557 * @}
1558 */ /* end of group AIPSTZ_Register_Masks */
1559
1560/* AIPSTZ - Peripheral instance base addresses */
1561/** Peripheral AIPSTZ base address */
1562#define AIPSTZ_BASE (0x301F0000u)
1563/** Peripheral AIPSTZ base pointer */
1564#define AIPSTZ ((AIPSTZ_Type *)AIPSTZ_BASE)
1565/** Array initializer of AIPSTZ peripheral base addresses */
1566#define AIPSTZ_BASE_ADDRS \
1567 { \
1568 AIPSTZ_BASE \
1569 }
1570/** Array initializer of AIPSTZ peripheral base pointers */
1571#define AIPSTZ_BASE_PTRS \
1572 { \
1573 AIPSTZ \
1574 }
1575
1576/*!
1577 * @}
1578 */ /* end of group AIPSTZ_Peripheral_Access_Layer */
1579
1580/* ----------------------------------------------------------------------------
1581 -- APBH Peripheral Access Layer
1582 ---------------------------------------------------------------------------- */
1583
1584/*!
1585 * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer
1586 * @{
1587 */
1588
1589/** APBH - Register Layout Typedef */
1590typedef struct
1591{
1592 __IO uint32_t CTRL0; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */
1593 __IO uint32_t CTRL0_SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */
1594 __IO uint32_t CTRL0_CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */
1595 __IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */
1596 __IO uint32_t CTRL1; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */
1597 __IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */
1598 __IO uint32_t CTRL1_CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */
1599 __IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */
1600 __IO uint32_t CTRL2; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */
1601 __IO uint32_t CTRL2_SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */
1602 __IO uint32_t CTRL2_CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */
1603 __IO uint32_t CTRL2_TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */
1604 __IO uint32_t CHANNEL_CTRL; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */
1605 __IO uint32_t CHANNEL_CTRL_SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */
1606 __IO uint32_t CHANNEL_CTRL_CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */
1607 __IO uint32_t CHANNEL_CTRL_TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */
1608 __I uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */
1609 uint8_t RESERVED_0[12];
1610 __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */
1611 uint8_t RESERVED_1[12];
1612 __IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60 */
1613 uint8_t RESERVED_2[156];
1614 struct
1615 { /* offset: 0x100, array step: 0x70 */
1616 __I uint32_t CH_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, array offset: 0x100, array
1617 step: 0x70 */
1618 uint8_t RESERVED_0[12];
1619 __IO uint32_t
1620 CH_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, array offset: 0x110, array step: 0x70 */
1621 uint8_t RESERVED_1[12];
1622 __I uint32_t CH_CMD; /**< APBH DMA Channel n Command Register, array offset: 0x120, array step: 0x70 */
1623 uint8_t RESERVED_2[12];
1624 __I uint32_t CH_BAR; /**< APBH DMA Channel n Buffer Address Register, array offset: 0x130, array step: 0x70 */
1625 uint8_t RESERVED_3[12];
1626 __IO uint32_t CH_SEMA; /**< APBH DMA Channel n Semaphore Register, array offset: 0x140, array step: 0x70 */
1627 uint8_t RESERVED_4[12];
1628 __I uint32_t
1629 CH_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x150, array step: 0x70 */
1630 uint8_t RESERVED_5[12];
1631 __I uint32_t
1632 CH_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x160, array step: 0x70 */
1633 uint8_t RESERVED_6[12];
1634 } CH_CFGn[16];
1635 __I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */
1636} APBH_Type;
1637
1638/* ----------------------------------------------------------------------------
1639 -- APBH Register Masks
1640 ---------------------------------------------------------------------------- */
1641
1642/*!
1643 * @addtogroup APBH_Register_Masks APBH Register Masks
1644 * @{
1645 */
1646
1647/*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */
1648/*! @{ */
1649#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU)
1650#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U)
1651/*! CLKGATE_CHANNEL
1652 * 0b0000000000000001..NAND0
1653 * 0b0000000000000010..NAND1
1654 * 0b0000000000000100..NAND2
1655 * 0b0000000000001000..NAND3
1656 * 0b0000000000010000..NAND4
1657 * 0b0000000000100000..NAND5
1658 * 0b0000000001000000..NAND6
1659 * 0b0000000010000000..NAND7
1660 * 0b0000000100000000..SSP
1661 */
1662#define APBH_CTRL0_CLKGATE_CHANNEL(x) \
1663 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK)
1664#define APBH_CTRL0_RSVD0_MASK (0xFFF0000U)
1665#define APBH_CTRL0_RSVD0_SHIFT (16U)
1666#define APBH_CTRL0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_RSVD0_SHIFT)) & APBH_CTRL0_RSVD0_MASK)
1667#define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U)
1668#define APBH_CTRL0_APB_BURST_EN_SHIFT (28U)
1669#define APBH_CTRL0_APB_BURST_EN(x) \
1670 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK)
1671#define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U)
1672#define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U)
1673#define APBH_CTRL0_AHB_BURST8_EN(x) \
1674 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK)
1675#define APBH_CTRL0_CLKGATE_MASK (0x40000000U)
1676#define APBH_CTRL0_CLKGATE_SHIFT (30U)
1677#define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK)
1678#define APBH_CTRL0_SFTRST_MASK (0x80000000U)
1679#define APBH_CTRL0_SFTRST_SHIFT (31U)
1680#define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK)
1681/*! @} */
1682
1683/*! @name CTRL0_SET - AHB to APBH Bridge Control and Status Register 0 */
1684/*! @{ */
1685#define APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK (0xFFFFU)
1686#define APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT (0U)
1687/*! CLKGATE_CHANNEL
1688 * 0b0000000000000001..NAND0
1689 * 0b0000000000000010..NAND1
1690 * 0b0000000000000100..NAND2
1691 * 0b0000000000001000..NAND3
1692 * 0b0000000000010000..NAND4
1693 * 0b0000000000100000..NAND5
1694 * 0b0000000001000000..NAND6
1695 * 0b0000000010000000..NAND7
1696 * 0b0000000100000000..SSP
1697 */
1698#define APBH_CTRL0_SET_CLKGATE_CHANNEL(x) \
1699 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK)
1700#define APBH_CTRL0_SET_RSVD0_MASK (0xFFF0000U)
1701#define APBH_CTRL0_SET_RSVD0_SHIFT (16U)
1702#define APBH_CTRL0_SET_RSVD0(x) \
1703 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_RSVD0_SHIFT)) & APBH_CTRL0_SET_RSVD0_MASK)
1704#define APBH_CTRL0_SET_APB_BURST_EN_MASK (0x10000000U)
1705#define APBH_CTRL0_SET_APB_BURST_EN_SHIFT (28U)
1706#define APBH_CTRL0_SET_APB_BURST_EN(x) \
1707 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_APB_BURST_EN_SHIFT)) & APBH_CTRL0_SET_APB_BURST_EN_MASK)
1708#define APBH_CTRL0_SET_AHB_BURST8_EN_MASK (0x20000000U)
1709#define APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT (29U)
1710#define APBH_CTRL0_SET_AHB_BURST8_EN(x) \
1711 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_SET_AHB_BURST8_EN_MASK)
1712#define APBH_CTRL0_SET_CLKGATE_MASK (0x40000000U)
1713#define APBH_CTRL0_SET_CLKGATE_SHIFT (30U)
1714#define APBH_CTRL0_SET_CLKGATE(x) \
1715 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_SHIFT)) & APBH_CTRL0_SET_CLKGATE_MASK)
1716#define APBH_CTRL0_SET_SFTRST_MASK (0x80000000U)
1717#define APBH_CTRL0_SET_SFTRST_SHIFT (31U)
1718#define APBH_CTRL0_SET_SFTRST(x) \
1719 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_SFTRST_SHIFT)) & APBH_CTRL0_SET_SFTRST_MASK)
1720/*! @} */
1721
1722/*! @name CTRL0_CLR - AHB to APBH Bridge Control and Status Register 0 */
1723/*! @{ */
1724#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK (0xFFFFU)
1725#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT (0U)
1726/*! CLKGATE_CHANNEL
1727 * 0b0000000000000001..NAND0
1728 * 0b0000000000000010..NAND1
1729 * 0b0000000000000100..NAND2
1730 * 0b0000000000001000..NAND3
1731 * 0b0000000000010000..NAND4
1732 * 0b0000000000100000..NAND5
1733 * 0b0000000001000000..NAND6
1734 * 0b0000000010000000..NAND7
1735 * 0b0000000100000000..SSP
1736 */
1737#define APBH_CTRL0_CLR_CLKGATE_CHANNEL(x) \
1738 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK)
1739#define APBH_CTRL0_CLR_RSVD0_MASK (0xFFF0000U)
1740#define APBH_CTRL0_CLR_RSVD0_SHIFT (16U)
1741#define APBH_CTRL0_CLR_RSVD0(x) \
1742 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_RSVD0_SHIFT)) & APBH_CTRL0_CLR_RSVD0_MASK)
1743#define APBH_CTRL0_CLR_APB_BURST_EN_MASK (0x10000000U)
1744#define APBH_CTRL0_CLR_APB_BURST_EN_SHIFT (28U)
1745#define APBH_CTRL0_CLR_APB_BURST_EN(x) \
1746 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_APB_BURST_EN_SHIFT)) & APBH_CTRL0_CLR_APB_BURST_EN_MASK)
1747#define APBH_CTRL0_CLR_AHB_BURST8_EN_MASK (0x20000000U)
1748#define APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT (29U)
1749#define APBH_CTRL0_CLR_AHB_BURST8_EN(x) \
1750 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_CLR_AHB_BURST8_EN_MASK)
1751#define APBH_CTRL0_CLR_CLKGATE_MASK (0x40000000U)
1752#define APBH_CTRL0_CLR_CLKGATE_SHIFT (30U)
1753#define APBH_CTRL0_CLR_CLKGATE(x) \
1754 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_MASK)
1755#define APBH_CTRL0_CLR_SFTRST_MASK (0x80000000U)
1756#define APBH_CTRL0_CLR_SFTRST_SHIFT (31U)
1757#define APBH_CTRL0_CLR_SFTRST(x) \
1758 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_SFTRST_SHIFT)) & APBH_CTRL0_CLR_SFTRST_MASK)
1759/*! @} */
1760
1761/*! @name CTRL0_TOG - AHB to APBH Bridge Control and Status Register 0 */
1762/*! @{ */
1763#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK (0xFFFFU)
1764#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT (0U)
1765/*! CLKGATE_CHANNEL
1766 * 0b0000000000000001..NAND0
1767 * 0b0000000000000010..NAND1
1768 * 0b0000000000000100..NAND2
1769 * 0b0000000000001000..NAND3
1770 * 0b0000000000010000..NAND4
1771 * 0b0000000000100000..NAND5
1772 * 0b0000000001000000..NAND6
1773 * 0b0000000010000000..NAND7
1774 * 0b0000000100000000..SSP
1775 */
1776#define APBH_CTRL0_TOG_CLKGATE_CHANNEL(x) \
1777 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK)
1778#define APBH_CTRL0_TOG_RSVD0_MASK (0xFFF0000U)
1779#define APBH_CTRL0_TOG_RSVD0_SHIFT (16U)
1780#define APBH_CTRL0_TOG_RSVD0(x) \
1781 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_RSVD0_SHIFT)) & APBH_CTRL0_TOG_RSVD0_MASK)
1782#define APBH_CTRL0_TOG_APB_BURST_EN_MASK (0x10000000U)
1783#define APBH_CTRL0_TOG_APB_BURST_EN_SHIFT (28U)
1784#define APBH_CTRL0_TOG_APB_BURST_EN(x) \
1785 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_APB_BURST_EN_SHIFT)) & APBH_CTRL0_TOG_APB_BURST_EN_MASK)
1786#define APBH_CTRL0_TOG_AHB_BURST8_EN_MASK (0x20000000U)
1787#define APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT (29U)
1788#define APBH_CTRL0_TOG_AHB_BURST8_EN(x) \
1789 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_TOG_AHB_BURST8_EN_MASK)
1790#define APBH_CTRL0_TOG_CLKGATE_MASK (0x40000000U)
1791#define APBH_CTRL0_TOG_CLKGATE_SHIFT (30U)
1792#define APBH_CTRL0_TOG_CLKGATE(x) \
1793 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_MASK)
1794#define APBH_CTRL0_TOG_SFTRST_MASK (0x80000000U)
1795#define APBH_CTRL0_TOG_SFTRST_SHIFT (31U)
1796#define APBH_CTRL0_TOG_SFTRST(x) \
1797 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_SFTRST_SHIFT)) & APBH_CTRL0_TOG_SFTRST_MASK)
1798/*! @} */
1799
1800/*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */
1801/*! @{ */
1802#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U)
1803#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U)
1804#define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) \
1805 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK)
1806#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U)
1807#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U)
1808#define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) \
1809 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK)
1810#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U)
1811#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U)
1812#define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) \
1813 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK)
1814#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U)
1815#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U)
1816#define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) \
1817 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK)
1818#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U)
1819#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U)
1820#define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) \
1821 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK)
1822#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U)
1823#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U)
1824#define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) \
1825 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK)
1826#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U)
1827#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U)
1828#define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) \
1829 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK)
1830#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U)
1831#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U)
1832#define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) \
1833 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK)
1834#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U)
1835#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U)
1836#define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) \
1837 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK)
1838#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U)
1839#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U)
1840#define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) \
1841 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK)
1842#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U)
1843#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U)
1844#define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) \
1845 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK)
1846#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U)
1847#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U)
1848#define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) \
1849 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK)
1850#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
1851#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U)
1852#define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) \
1853 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK)
1854#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
1855#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U)
1856#define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) \
1857 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK)
1858#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
1859#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U)
1860#define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) \
1861 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK)
1862#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
1863#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U)
1864#define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) \
1865 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK)
1866#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
1867#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
1868#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) \
1869 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK)
1870#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
1871#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
1872#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) \
1873 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK)
1874#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
1875#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
1876#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) \
1877 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK)
1878#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
1879#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
1880#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) \
1881 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK)
1882#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
1883#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
1884#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) \
1885 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK)
1886#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
1887#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
1888#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) \
1889 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK)
1890#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
1891#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
1892#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) \
1893 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK)
1894#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
1895#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
1896#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) \
1897 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK)
1898#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
1899#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
1900#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) \
1901 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK)
1902#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
1903#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
1904#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) \
1905 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK)
1906#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
1907#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
1908#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) \
1909 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
1910#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
1911#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
1912#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) \
1913 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK)
1914#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
1915#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
1916#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) \
1917 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK)
1918#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
1919#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
1920#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) \
1921 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK)
1922#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
1923#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
1924#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) \
1925 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK)
1926#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
1927#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
1928#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) \
1929 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK)
1930/*! @} */
1931
1932/*! @name CTRL1_SET - AHB to APBH Bridge Control and Status Register 1 */
1933/*! @{ */
1934#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK (0x1U)
1935#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT (0U)
1936#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ(x) \
1937 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK)
1938#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK (0x2U)
1939#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT (1U)
1940#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ(x) \
1941 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK)
1942#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK (0x4U)
1943#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT (2U)
1944#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ(x) \
1945 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK)
1946#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK (0x8U)
1947#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT (3U)
1948#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ(x) \
1949 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK)
1950#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK (0x10U)
1951#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT (4U)
1952#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ(x) \
1953 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK)
1954#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK (0x20U)
1955#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT (5U)
1956#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ(x) \
1957 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK)
1958#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK (0x40U)
1959#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT (6U)
1960#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ(x) \
1961 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK)
1962#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK (0x80U)
1963#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT (7U)
1964#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ(x) \
1965 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK)
1966#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK (0x100U)
1967#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT (8U)
1968#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ(x) \
1969 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK)
1970#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK (0x200U)
1971#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT (9U)
1972#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ(x) \
1973 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK)
1974#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK (0x400U)
1975#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT (10U)
1976#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ(x) \
1977 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK)
1978#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK (0x800U)
1979#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT (11U)
1980#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ(x) \
1981 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK)
1982#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
1983#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT (12U)
1984#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ(x) \
1985 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK)
1986#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
1987#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT (13U)
1988#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ(x) \
1989 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK)
1990#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
1991#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT (14U)
1992#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ(x) \
1993 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK)
1994#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
1995#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT (15U)
1996#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ(x) \
1997 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK)
1998#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
1999#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
2000#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN(x) \
2001 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & \
2002 APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK)
2003#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
2004#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
2005#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN(x) \
2006 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & \
2007 APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK)
2008#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
2009#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
2010#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN(x) \
2011 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & \
2012 APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK)
2013#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
2014#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
2015#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN(x) \
2016 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & \
2017 APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK)
2018#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
2019#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
2020#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN(x) \
2021 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & \
2022 APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK)
2023#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
2024#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
2025#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN(x) \
2026 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & \
2027 APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK)
2028#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
2029#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
2030#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN(x) \
2031 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & \
2032 APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK)
2033#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
2034#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
2035#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN(x) \
2036 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & \
2037 APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK)
2038#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
2039#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
2040#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN(x) \
2041 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & \
2042 APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK)
2043#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
2044#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
2045#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN(x) \
2046 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & \
2047 APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK)
2048#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
2049#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
2050#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN(x) \
2051 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & \
2052 APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK)
2053#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
2054#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
2055#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN(x) \
2056 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & \
2057 APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK)
2058#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
2059#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
2060#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN(x) \
2061 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & \
2062 APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK)
2063#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
2064#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
2065#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN(x) \
2066 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & \
2067 APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK)
2068#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
2069#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
2070#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN(x) \
2071 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & \
2072 APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK)
2073#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
2074#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
2075#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN(x) \
2076 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & \
2077 APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK)
2078/*! @} */
2079
2080/*! @name CTRL1_CLR - AHB to APBH Bridge Control and Status Register 1 */
2081/*! @{ */
2082#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK (0x1U)
2083#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT (0U)
2084#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ(x) \
2085 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK)
2086#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK (0x2U)
2087#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT (1U)
2088#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ(x) \
2089 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK)
2090#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK (0x4U)
2091#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT (2U)
2092#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ(x) \
2093 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK)
2094#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK (0x8U)
2095#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT (3U)
2096#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ(x) \
2097 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK)
2098#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK (0x10U)
2099#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT (4U)
2100#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ(x) \
2101 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK)
2102#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK (0x20U)
2103#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT (5U)
2104#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ(x) \
2105 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK)
2106#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK (0x40U)
2107#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT (6U)
2108#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ(x) \
2109 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK)
2110#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK (0x80U)
2111#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT (7U)
2112#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ(x) \
2113 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK)
2114#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK (0x100U)
2115#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT (8U)
2116#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ(x) \
2117 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK)
2118#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK (0x200U)
2119#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT (9U)
2120#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ(x) \
2121 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK)
2122#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK (0x400U)
2123#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT (10U)
2124#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ(x) \
2125 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK)
2126#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK (0x800U)
2127#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT (11U)
2128#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ(x) \
2129 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK)
2130#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
2131#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT (12U)
2132#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ(x) \
2133 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK)
2134#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
2135#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT (13U)
2136#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ(x) \
2137 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK)
2138#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
2139#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT (14U)
2140#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ(x) \
2141 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK)
2142#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
2143#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT (15U)
2144#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ(x) \
2145 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK)
2146#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
2147#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
2148#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN(x) \
2149 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & \
2150 APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK)
2151#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
2152#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
2153#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN(x) \
2154 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & \
2155 APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK)
2156#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
2157#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
2158#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN(x) \
2159 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & \
2160 APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK)
2161#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
2162#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
2163#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN(x) \
2164 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & \
2165 APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK)
2166#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
2167#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
2168#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN(x) \
2169 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & \
2170 APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK)
2171#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
2172#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
2173#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN(x) \
2174 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & \
2175 APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK)
2176#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
2177#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
2178#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN(x) \
2179 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & \
2180 APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK)
2181#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
2182#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
2183#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN(x) \
2184 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & \
2185 APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK)
2186#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
2187#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
2188#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN(x) \
2189 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & \
2190 APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK)
2191#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
2192#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
2193#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN(x) \
2194 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & \
2195 APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK)
2196#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
2197#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
2198#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN(x) \
2199 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & \
2200 APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK)
2201#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
2202#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
2203#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN(x) \
2204 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & \
2205 APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK)
2206#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
2207#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
2208#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN(x) \
2209 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & \
2210 APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK)
2211#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
2212#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
2213#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN(x) \
2214 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & \
2215 APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK)
2216#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
2217#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
2218#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN(x) \
2219 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & \
2220 APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK)
2221#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
2222#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
2223#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN(x) \
2224 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & \
2225 APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK)
2226/*! @} */
2227
2228/*! @name CTRL1_TOG - AHB to APBH Bridge Control and Status Register 1 */
2229/*! @{ */
2230#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK (0x1U)
2231#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT (0U)
2232#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ(x) \
2233 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK)
2234#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK (0x2U)
2235#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT (1U)
2236#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ(x) \
2237 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK)
2238#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK (0x4U)
2239#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT (2U)
2240#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ(x) \
2241 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK)
2242#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK (0x8U)
2243#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT (3U)
2244#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ(x) \
2245 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK)
2246#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK (0x10U)
2247#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT (4U)
2248#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ(x) \
2249 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK)
2250#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK (0x20U)
2251#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT (5U)
2252#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ(x) \
2253 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK)
2254#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK (0x40U)
2255#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT (6U)
2256#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ(x) \
2257 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK)
2258#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK (0x80U)
2259#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT (7U)
2260#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ(x) \
2261 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK)
2262#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK (0x100U)
2263#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT (8U)
2264#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ(x) \
2265 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK)
2266#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK (0x200U)
2267#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT (9U)
2268#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ(x) \
2269 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK)
2270#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK (0x400U)
2271#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT (10U)
2272#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ(x) \
2273 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK)
2274#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK (0x800U)
2275#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT (11U)
2276#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ(x) \
2277 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK)
2278#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
2279#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT (12U)
2280#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ(x) \
2281 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK)
2282#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
2283#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT (13U)
2284#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ(x) \
2285 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK)
2286#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
2287#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT (14U)
2288#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ(x) \
2289 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK)
2290#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
2291#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT (15U)
2292#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ(x) \
2293 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK)
2294#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
2295#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
2296#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN(x) \
2297 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & \
2298 APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK)
2299#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
2300#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
2301#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN(x) \
2302 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & \
2303 APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK)
2304#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
2305#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
2306#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN(x) \
2307 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & \
2308 APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK)
2309#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
2310#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
2311#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN(x) \
2312 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & \
2313 APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK)
2314#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
2315#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
2316#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN(x) \
2317 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & \
2318 APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK)
2319#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
2320#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
2321#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN(x) \
2322 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & \
2323 APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK)
2324#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
2325#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
2326#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN(x) \
2327 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & \
2328 APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK)
2329#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
2330#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
2331#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN(x) \
2332 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & \
2333 APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK)
2334#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
2335#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
2336#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN(x) \
2337 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & \
2338 APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK)
2339#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
2340#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
2341#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN(x) \
2342 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & \
2343 APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK)
2344#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
2345#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
2346#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN(x) \
2347 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & \
2348 APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK)
2349#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
2350#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
2351#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN(x) \
2352 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & \
2353 APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK)
2354#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
2355#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
2356#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN(x) \
2357 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & \
2358 APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK)
2359#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
2360#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
2361#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN(x) \
2362 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & \
2363 APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK)
2364#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
2365#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
2366#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN(x) \
2367 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & \
2368 APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK)
2369#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
2370#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
2371#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN(x) \
2372 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & \
2373 APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK)
2374/*! @} */
2375
2376/*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */
2377/*! @{ */
2378#define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U)
2379#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U)
2380#define APBH_CTRL2_CH0_ERROR_IRQ(x) \
2381 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK)
2382#define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U)
2383#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U)
2384#define APBH_CTRL2_CH1_ERROR_IRQ(x) \
2385 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK)
2386#define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U)
2387#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U)
2388#define APBH_CTRL2_CH2_ERROR_IRQ(x) \
2389 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK)
2390#define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U)
2391#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U)
2392#define APBH_CTRL2_CH3_ERROR_IRQ(x) \
2393 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK)
2394#define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U)
2395#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U)
2396#define APBH_CTRL2_CH4_ERROR_IRQ(x) \
2397 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK)
2398#define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U)
2399#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U)
2400#define APBH_CTRL2_CH5_ERROR_IRQ(x) \
2401 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK)
2402#define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U)
2403#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U)
2404#define APBH_CTRL2_CH6_ERROR_IRQ(x) \
2405 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK)
2406#define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U)
2407#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U)
2408#define APBH_CTRL2_CH7_ERROR_IRQ(x) \
2409 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK)
2410#define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U)
2411#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U)
2412#define APBH_CTRL2_CH8_ERROR_IRQ(x) \
2413 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK)
2414#define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U)
2415#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U)
2416#define APBH_CTRL2_CH9_ERROR_IRQ(x) \
2417 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK)
2418#define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U)
2419#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U)
2420#define APBH_CTRL2_CH10_ERROR_IRQ(x) \
2421 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK)
2422#define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U)
2423#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U)
2424#define APBH_CTRL2_CH11_ERROR_IRQ(x) \
2425 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK)
2426#define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U)
2427#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U)
2428#define APBH_CTRL2_CH12_ERROR_IRQ(x) \
2429 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK)
2430#define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U)
2431#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U)
2432#define APBH_CTRL2_CH13_ERROR_IRQ(x) \
2433 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK)
2434#define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U)
2435#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U)
2436#define APBH_CTRL2_CH14_ERROR_IRQ(x) \
2437 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK)
2438#define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U)
2439#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U)
2440#define APBH_CTRL2_CH15_ERROR_IRQ(x) \
2441 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK)
2442#define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U)
2443#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U)
2444/*! CH0_ERROR_STATUS
2445 * 0b0..An early termination from the device causes error IRQ.
2446 * 0b1..An AHB bus error causes error IRQ.
2447 */
2448#define APBH_CTRL2_CH0_ERROR_STATUS(x) \
2449 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK)
2450#define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U)
2451#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U)
2452/*! CH1_ERROR_STATUS
2453 * 0b0..An early termination from the device causes error IRQ.
2454 * 0b1..An AHB bus error causes error IRQ.
2455 */
2456#define APBH_CTRL2_CH1_ERROR_STATUS(x) \
2457 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK)
2458#define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U)
2459#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U)
2460/*! CH2_ERROR_STATUS
2461 * 0b0..An early termination from the device causes error IRQ.
2462 * 0b1..An AHB bus error causes error IRQ.
2463 */
2464#define APBH_CTRL2_CH2_ERROR_STATUS(x) \
2465 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK)
2466#define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U)
2467#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U)
2468/*! CH3_ERROR_STATUS
2469 * 0b0..An early termination from the device causes error IRQ.
2470 * 0b1..An AHB bus error causes error IRQ.
2471 */
2472#define APBH_CTRL2_CH3_ERROR_STATUS(x) \
2473 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK)
2474#define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U)
2475#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U)
2476/*! CH4_ERROR_STATUS
2477 * 0b0..An early termination from the device causes error IRQ.
2478 * 0b1..An AHB bus error causes error IRQ.
2479 */
2480#define APBH_CTRL2_CH4_ERROR_STATUS(x) \
2481 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK)
2482#define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U)
2483#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U)
2484/*! CH5_ERROR_STATUS
2485 * 0b0..An early termination from the device causes error IRQ.
2486 * 0b1..An AHB bus error causes error IRQ.
2487 */
2488#define APBH_CTRL2_CH5_ERROR_STATUS(x) \
2489 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK)
2490#define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U)
2491#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U)
2492/*! CH6_ERROR_STATUS
2493 * 0b0..An early termination from the device causes error IRQ.
2494 * 0b1..An AHB bus error causes error IRQ.
2495 */
2496#define APBH_CTRL2_CH6_ERROR_STATUS(x) \
2497 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK)
2498#define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U)
2499#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U)
2500/*! CH7_ERROR_STATUS
2501 * 0b0..An early termination from the device causes error IRQ.
2502 * 0b1..An AHB bus error causes error IRQ.
2503 */
2504#define APBH_CTRL2_CH7_ERROR_STATUS(x) \
2505 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK)
2506#define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U)
2507#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U)
2508/*! CH8_ERROR_STATUS
2509 * 0b0..An early termination from the device causes error IRQ.
2510 * 0b1..An AHB bus error causes error IRQ.
2511 */
2512#define APBH_CTRL2_CH8_ERROR_STATUS(x) \
2513 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK)
2514#define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U)
2515#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U)
2516/*! CH9_ERROR_STATUS
2517 * 0b0..An early termination from the device causes error IRQ.
2518 * 0b1..An AHB bus error causes error IRQ.
2519 */
2520#define APBH_CTRL2_CH9_ERROR_STATUS(x) \
2521 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK)
2522#define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U)
2523#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U)
2524/*! CH10_ERROR_STATUS
2525 * 0b0..An early termination from the device causes error IRQ.
2526 * 0b1..An AHB bus error causes error IRQ.
2527 */
2528#define APBH_CTRL2_CH10_ERROR_STATUS(x) \
2529 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK)
2530#define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U)
2531#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U)
2532/*! CH11_ERROR_STATUS
2533 * 0b0..An early termination from the device causes error IRQ.
2534 * 0b1..An AHB bus error causes error IRQ.
2535 */
2536#define APBH_CTRL2_CH11_ERROR_STATUS(x) \
2537 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK)
2538#define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U)
2539#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U)
2540/*! CH12_ERROR_STATUS
2541 * 0b0..An early termination from the device causes error IRQ.
2542 * 0b1..An AHB bus error causes error IRQ.
2543 */
2544#define APBH_CTRL2_CH12_ERROR_STATUS(x) \
2545 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK)
2546#define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U)
2547#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U)
2548/*! CH13_ERROR_STATUS
2549 * 0b0..An early termination from the device causes error IRQ.
2550 * 0b1..An AHB bus error causes error IRQ.
2551 */
2552#define APBH_CTRL2_CH13_ERROR_STATUS(x) \
2553 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK)
2554#define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U)
2555#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U)
2556/*! CH14_ERROR_STATUS
2557 * 0b0..An early termination from the device causes error IRQ.
2558 * 0b1..An AHB bus error causes error IRQ.
2559 */
2560#define APBH_CTRL2_CH14_ERROR_STATUS(x) \
2561 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK)
2562#define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U)
2563#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U)
2564/*! CH15_ERROR_STATUS
2565 * 0b0..An early termination from the device causes error IRQ.
2566 * 0b1..An AHB bus error causes error IRQ.
2567 */
2568#define APBH_CTRL2_CH15_ERROR_STATUS(x) \
2569 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK)
2570/*! @} */
2571
2572/*! @name CTRL2_SET - AHB to APBH Bridge Control and Status Register 2 */
2573/*! @{ */
2574#define APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK (0x1U)
2575#define APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT (0U)
2576#define APBH_CTRL2_SET_CH0_ERROR_IRQ(x) \
2577 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK)
2578#define APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK (0x2U)
2579#define APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT (1U)
2580#define APBH_CTRL2_SET_CH1_ERROR_IRQ(x) \
2581 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK)
2582#define APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK (0x4U)
2583#define APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT (2U)
2584#define APBH_CTRL2_SET_CH2_ERROR_IRQ(x) \
2585 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK)
2586#define APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK (0x8U)
2587#define APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT (3U)
2588#define APBH_CTRL2_SET_CH3_ERROR_IRQ(x) \
2589 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK)
2590#define APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK (0x10U)
2591#define APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT (4U)
2592#define APBH_CTRL2_SET_CH4_ERROR_IRQ(x) \
2593 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK)
2594#define APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK (0x20U)
2595#define APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT (5U)
2596#define APBH_CTRL2_SET_CH5_ERROR_IRQ(x) \
2597 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK)
2598#define APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK (0x40U)
2599#define APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT (6U)
2600#define APBH_CTRL2_SET_CH6_ERROR_IRQ(x) \
2601 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK)
2602#define APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK (0x80U)
2603#define APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT (7U)
2604#define APBH_CTRL2_SET_CH7_ERROR_IRQ(x) \
2605 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK)
2606#define APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK (0x100U)
2607#define APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT (8U)
2608#define APBH_CTRL2_SET_CH8_ERROR_IRQ(x) \
2609 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK)
2610#define APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK (0x200U)
2611#define APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT (9U)
2612#define APBH_CTRL2_SET_CH9_ERROR_IRQ(x) \
2613 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK)
2614#define APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK (0x400U)
2615#define APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT (10U)
2616#define APBH_CTRL2_SET_CH10_ERROR_IRQ(x) \
2617 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK)
2618#define APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK (0x800U)
2619#define APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT (11U)
2620#define APBH_CTRL2_SET_CH11_ERROR_IRQ(x) \
2621 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK)
2622#define APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK (0x1000U)
2623#define APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT (12U)
2624#define APBH_CTRL2_SET_CH12_ERROR_IRQ(x) \
2625 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK)
2626#define APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK (0x2000U)
2627#define APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT (13U)
2628#define APBH_CTRL2_SET_CH13_ERROR_IRQ(x) \
2629 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK)
2630#define APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK (0x4000U)
2631#define APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT (14U)
2632#define APBH_CTRL2_SET_CH14_ERROR_IRQ(x) \
2633 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK)
2634#define APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK (0x8000U)
2635#define APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT (15U)
2636#define APBH_CTRL2_SET_CH15_ERROR_IRQ(x) \
2637 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK)
2638#define APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK (0x10000U)
2639#define APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT (16U)
2640/*! CH0_ERROR_STATUS
2641 * 0b0..An early termination from the device causes error IRQ.
2642 * 0b1..An AHB bus error causes error IRQ.
2643 */
2644#define APBH_CTRL2_SET_CH0_ERROR_STATUS(x) \
2645 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK)
2646#define APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK (0x20000U)
2647#define APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT (17U)
2648/*! CH1_ERROR_STATUS
2649 * 0b0..An early termination from the device causes error IRQ.
2650 * 0b1..An AHB bus error causes error IRQ.
2651 */
2652#define APBH_CTRL2_SET_CH1_ERROR_STATUS(x) \
2653 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK)
2654#define APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK (0x40000U)
2655#define APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT (18U)
2656/*! CH2_ERROR_STATUS
2657 * 0b0..An early termination from the device causes error IRQ.
2658 * 0b1..An AHB bus error causes error IRQ.
2659 */
2660#define APBH_CTRL2_SET_CH2_ERROR_STATUS(x) \
2661 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK)
2662#define APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK (0x80000U)
2663#define APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT (19U)
2664/*! CH3_ERROR_STATUS
2665 * 0b0..An early termination from the device causes error IRQ.
2666 * 0b1..An AHB bus error causes error IRQ.
2667 */
2668#define APBH_CTRL2_SET_CH3_ERROR_STATUS(x) \
2669 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK)
2670#define APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK (0x100000U)
2671#define APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT (20U)
2672/*! CH4_ERROR_STATUS
2673 * 0b0..An early termination from the device causes error IRQ.
2674 * 0b1..An AHB bus error causes error IRQ.
2675 */
2676#define APBH_CTRL2_SET_CH4_ERROR_STATUS(x) \
2677 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK)
2678#define APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK (0x200000U)
2679#define APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT (21U)
2680/*! CH5_ERROR_STATUS
2681 * 0b0..An early termination from the device causes error IRQ.
2682 * 0b1..An AHB bus error causes error IRQ.
2683 */
2684#define APBH_CTRL2_SET_CH5_ERROR_STATUS(x) \
2685 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK)
2686#define APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK (0x400000U)
2687#define APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT (22U)
2688/*! CH6_ERROR_STATUS
2689 * 0b0..An early termination from the device causes error IRQ.
2690 * 0b1..An AHB bus error causes error IRQ.
2691 */
2692#define APBH_CTRL2_SET_CH6_ERROR_STATUS(x) \
2693 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK)
2694#define APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK (0x800000U)
2695#define APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT (23U)
2696/*! CH7_ERROR_STATUS
2697 * 0b0..An early termination from the device causes error IRQ.
2698 * 0b1..An AHB bus error causes error IRQ.
2699 */
2700#define APBH_CTRL2_SET_CH7_ERROR_STATUS(x) \
2701 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK)
2702#define APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK (0x1000000U)
2703#define APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT (24U)
2704/*! CH8_ERROR_STATUS
2705 * 0b0..An early termination from the device causes error IRQ.
2706 * 0b1..An AHB bus error causes error IRQ.
2707 */
2708#define APBH_CTRL2_SET_CH8_ERROR_STATUS(x) \
2709 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK)
2710#define APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK (0x2000000U)
2711#define APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT (25U)
2712/*! CH9_ERROR_STATUS
2713 * 0b0..An early termination from the device causes error IRQ.
2714 * 0b1..An AHB bus error causes error IRQ.
2715 */
2716#define APBH_CTRL2_SET_CH9_ERROR_STATUS(x) \
2717 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK)
2718#define APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK (0x4000000U)
2719#define APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT (26U)
2720/*! CH10_ERROR_STATUS
2721 * 0b0..An early termination from the device causes error IRQ.
2722 * 0b1..An AHB bus error causes error IRQ.
2723 */
2724#define APBH_CTRL2_SET_CH10_ERROR_STATUS(x) \
2725 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK)
2726#define APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK (0x8000000U)
2727#define APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT (27U)
2728/*! CH11_ERROR_STATUS
2729 * 0b0..An early termination from the device causes error IRQ.
2730 * 0b1..An AHB bus error causes error IRQ.
2731 */
2732#define APBH_CTRL2_SET_CH11_ERROR_STATUS(x) \
2733 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK)
2734#define APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK (0x10000000U)
2735#define APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT (28U)
2736/*! CH12_ERROR_STATUS
2737 * 0b0..An early termination from the device causes error IRQ.
2738 * 0b1..An AHB bus error causes error IRQ.
2739 */
2740#define APBH_CTRL2_SET_CH12_ERROR_STATUS(x) \
2741 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK)
2742#define APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK (0x20000000U)
2743#define APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT (29U)
2744/*! CH13_ERROR_STATUS
2745 * 0b0..An early termination from the device causes error IRQ.
2746 * 0b1..An AHB bus error causes error IRQ.
2747 */
2748#define APBH_CTRL2_SET_CH13_ERROR_STATUS(x) \
2749 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK)
2750#define APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK (0x40000000U)
2751#define APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT (30U)
2752/*! CH14_ERROR_STATUS
2753 * 0b0..An early termination from the device causes error IRQ.
2754 * 0b1..An AHB bus error causes error IRQ.
2755 */
2756#define APBH_CTRL2_SET_CH14_ERROR_STATUS(x) \
2757 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK)
2758#define APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK (0x80000000U)
2759#define APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT (31U)
2760/*! CH15_ERROR_STATUS
2761 * 0b0..An early termination from the device causes error IRQ.
2762 * 0b1..An AHB bus error causes error IRQ.
2763 */
2764#define APBH_CTRL2_SET_CH15_ERROR_STATUS(x) \
2765 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK)
2766/*! @} */
2767
2768/*! @name CTRL2_CLR - AHB to APBH Bridge Control and Status Register 2 */
2769/*! @{ */
2770#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK (0x1U)
2771#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT (0U)
2772#define APBH_CTRL2_CLR_CH0_ERROR_IRQ(x) \
2773 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK)
2774#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK (0x2U)
2775#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT (1U)
2776#define APBH_CTRL2_CLR_CH1_ERROR_IRQ(x) \
2777 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK)
2778#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK (0x4U)
2779#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT (2U)
2780#define APBH_CTRL2_CLR_CH2_ERROR_IRQ(x) \
2781 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK)
2782#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK (0x8U)
2783#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT (3U)
2784#define APBH_CTRL2_CLR_CH3_ERROR_IRQ(x) \
2785 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK)
2786#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK (0x10U)
2787#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT (4U)
2788#define APBH_CTRL2_CLR_CH4_ERROR_IRQ(x) \
2789 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK)
2790#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK (0x20U)
2791#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT (5U)
2792#define APBH_CTRL2_CLR_CH5_ERROR_IRQ(x) \
2793 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK)
2794#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK (0x40U)
2795#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT (6U)
2796#define APBH_CTRL2_CLR_CH6_ERROR_IRQ(x) \
2797 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK)
2798#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK (0x80U)
2799#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT (7U)
2800#define APBH_CTRL2_CLR_CH7_ERROR_IRQ(x) \
2801 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK)
2802#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK (0x100U)
2803#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT (8U)
2804#define APBH_CTRL2_CLR_CH8_ERROR_IRQ(x) \
2805 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK)
2806#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK (0x200U)
2807#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT (9U)
2808#define APBH_CTRL2_CLR_CH9_ERROR_IRQ(x) \
2809 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK)
2810#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK (0x400U)
2811#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT (10U)
2812#define APBH_CTRL2_CLR_CH10_ERROR_IRQ(x) \
2813 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK)
2814#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK (0x800U)
2815#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT (11U)
2816#define APBH_CTRL2_CLR_CH11_ERROR_IRQ(x) \
2817 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK)
2818#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK (0x1000U)
2819#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT (12U)
2820#define APBH_CTRL2_CLR_CH12_ERROR_IRQ(x) \
2821 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK)
2822#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK (0x2000U)
2823#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT (13U)
2824#define APBH_CTRL2_CLR_CH13_ERROR_IRQ(x) \
2825 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK)
2826#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK (0x4000U)
2827#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT (14U)
2828#define APBH_CTRL2_CLR_CH14_ERROR_IRQ(x) \
2829 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK)
2830#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK (0x8000U)
2831#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT (15U)
2832#define APBH_CTRL2_CLR_CH15_ERROR_IRQ(x) \
2833 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK)
2834#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK (0x10000U)
2835#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT (16U)
2836/*! CH0_ERROR_STATUS
2837 * 0b0..An early termination from the device causes error IRQ.
2838 * 0b1..An AHB bus error causes error IRQ.
2839 */
2840#define APBH_CTRL2_CLR_CH0_ERROR_STATUS(x) \
2841 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK)
2842#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK (0x20000U)
2843#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT (17U)
2844/*! CH1_ERROR_STATUS
2845 * 0b0..An early termination from the device causes error IRQ.
2846 * 0b1..An AHB bus error causes error IRQ.
2847 */
2848#define APBH_CTRL2_CLR_CH1_ERROR_STATUS(x) \
2849 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK)
2850#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK (0x40000U)
2851#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT (18U)
2852/*! CH2_ERROR_STATUS
2853 * 0b0..An early termination from the device causes error IRQ.
2854 * 0b1..An AHB bus error causes error IRQ.
2855 */
2856#define APBH_CTRL2_CLR_CH2_ERROR_STATUS(x) \
2857 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK)
2858#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK (0x80000U)
2859#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT (19U)
2860/*! CH3_ERROR_STATUS
2861 * 0b0..An early termination from the device causes error IRQ.
2862 * 0b1..An AHB bus error causes error IRQ.
2863 */
2864#define APBH_CTRL2_CLR_CH3_ERROR_STATUS(x) \
2865 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK)
2866#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK (0x100000U)
2867#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT (20U)
2868/*! CH4_ERROR_STATUS
2869 * 0b0..An early termination from the device causes error IRQ.
2870 * 0b1..An AHB bus error causes error IRQ.
2871 */
2872#define APBH_CTRL2_CLR_CH4_ERROR_STATUS(x) \
2873 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK)
2874#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK (0x200000U)
2875#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT (21U)
2876/*! CH5_ERROR_STATUS
2877 * 0b0..An early termination from the device causes error IRQ.
2878 * 0b1..An AHB bus error causes error IRQ.
2879 */
2880#define APBH_CTRL2_CLR_CH5_ERROR_STATUS(x) \
2881 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK)
2882#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK (0x400000U)
2883#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT (22U)
2884/*! CH6_ERROR_STATUS
2885 * 0b0..An early termination from the device causes error IRQ.
2886 * 0b1..An AHB bus error causes error IRQ.
2887 */
2888#define APBH_CTRL2_CLR_CH6_ERROR_STATUS(x) \
2889 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK)
2890#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK (0x800000U)
2891#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT (23U)
2892/*! CH7_ERROR_STATUS
2893 * 0b0..An early termination from the device causes error IRQ.
2894 * 0b1..An AHB bus error causes error IRQ.
2895 */
2896#define APBH_CTRL2_CLR_CH7_ERROR_STATUS(x) \
2897 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK)
2898#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK (0x1000000U)
2899#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT (24U)
2900/*! CH8_ERROR_STATUS
2901 * 0b0..An early termination from the device causes error IRQ.
2902 * 0b1..An AHB bus error causes error IRQ.
2903 */
2904#define APBH_CTRL2_CLR_CH8_ERROR_STATUS(x) \
2905 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK)
2906#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK (0x2000000U)
2907#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT (25U)
2908/*! CH9_ERROR_STATUS
2909 * 0b0..An early termination from the device causes error IRQ.
2910 * 0b1..An AHB bus error causes error IRQ.
2911 */
2912#define APBH_CTRL2_CLR_CH9_ERROR_STATUS(x) \
2913 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK)
2914#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK (0x4000000U)
2915#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT (26U)
2916/*! CH10_ERROR_STATUS
2917 * 0b0..An early termination from the device causes error IRQ.
2918 * 0b1..An AHB bus error causes error IRQ.
2919 */
2920#define APBH_CTRL2_CLR_CH10_ERROR_STATUS(x) \
2921 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK)
2922#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK (0x8000000U)
2923#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT (27U)
2924/*! CH11_ERROR_STATUS
2925 * 0b0..An early termination from the device causes error IRQ.
2926 * 0b1..An AHB bus error causes error IRQ.
2927 */
2928#define APBH_CTRL2_CLR_CH11_ERROR_STATUS(x) \
2929 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK)
2930#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK (0x10000000U)
2931#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT (28U)
2932/*! CH12_ERROR_STATUS
2933 * 0b0..An early termination from the device causes error IRQ.
2934 * 0b1..An AHB bus error causes error IRQ.
2935 */
2936#define APBH_CTRL2_CLR_CH12_ERROR_STATUS(x) \
2937 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK)
2938#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK (0x20000000U)
2939#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT (29U)
2940/*! CH13_ERROR_STATUS
2941 * 0b0..An early termination from the device causes error IRQ.
2942 * 0b1..An AHB bus error causes error IRQ.
2943 */
2944#define APBH_CTRL2_CLR_CH13_ERROR_STATUS(x) \
2945 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK)
2946#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK (0x40000000U)
2947#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT (30U)
2948/*! CH14_ERROR_STATUS
2949 * 0b0..An early termination from the device causes error IRQ.
2950 * 0b1..An AHB bus error causes error IRQ.
2951 */
2952#define APBH_CTRL2_CLR_CH14_ERROR_STATUS(x) \
2953 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK)
2954#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK (0x80000000U)
2955#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT (31U)
2956/*! CH15_ERROR_STATUS
2957 * 0b0..An early termination from the device causes error IRQ.
2958 * 0b1..An AHB bus error causes error IRQ.
2959 */
2960#define APBH_CTRL2_CLR_CH15_ERROR_STATUS(x) \
2961 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK)
2962/*! @} */
2963
2964/*! @name CTRL2_TOG - AHB to APBH Bridge Control and Status Register 2 */
2965/*! @{ */
2966#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK (0x1U)
2967#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT (0U)
2968#define APBH_CTRL2_TOG_CH0_ERROR_IRQ(x) \
2969 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK)
2970#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK (0x2U)
2971#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT (1U)
2972#define APBH_CTRL2_TOG_CH1_ERROR_IRQ(x) \
2973 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK)
2974#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK (0x4U)
2975#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT (2U)
2976#define APBH_CTRL2_TOG_CH2_ERROR_IRQ(x) \
2977 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK)
2978#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK (0x8U)
2979#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT (3U)
2980#define APBH_CTRL2_TOG_CH3_ERROR_IRQ(x) \
2981 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK)
2982#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK (0x10U)
2983#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT (4U)
2984#define APBH_CTRL2_TOG_CH4_ERROR_IRQ(x) \
2985 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK)
2986#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK (0x20U)
2987#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT (5U)
2988#define APBH_CTRL2_TOG_CH5_ERROR_IRQ(x) \
2989 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK)
2990#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK (0x40U)
2991#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT (6U)
2992#define APBH_CTRL2_TOG_CH6_ERROR_IRQ(x) \
2993 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK)
2994#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK (0x80U)
2995#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT (7U)
2996#define APBH_CTRL2_TOG_CH7_ERROR_IRQ(x) \
2997 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK)
2998#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK (0x100U)
2999#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT (8U)
3000#define APBH_CTRL2_TOG_CH8_ERROR_IRQ(x) \
3001 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK)
3002#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK (0x200U)
3003#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT (9U)
3004#define APBH_CTRL2_TOG_CH9_ERROR_IRQ(x) \
3005 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK)
3006#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK (0x400U)
3007#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT (10U)
3008#define APBH_CTRL2_TOG_CH10_ERROR_IRQ(x) \
3009 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK)
3010#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK (0x800U)
3011#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT (11U)
3012#define APBH_CTRL2_TOG_CH11_ERROR_IRQ(x) \
3013 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK)
3014#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK (0x1000U)
3015#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT (12U)
3016#define APBH_CTRL2_TOG_CH12_ERROR_IRQ(x) \
3017 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK)
3018#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK (0x2000U)
3019#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT (13U)
3020#define APBH_CTRL2_TOG_CH13_ERROR_IRQ(x) \
3021 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK)
3022#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK (0x4000U)
3023#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT (14U)
3024#define APBH_CTRL2_TOG_CH14_ERROR_IRQ(x) \
3025 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK)
3026#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK (0x8000U)
3027#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT (15U)
3028#define APBH_CTRL2_TOG_CH15_ERROR_IRQ(x) \
3029 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK)
3030#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK (0x10000U)
3031#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT (16U)
3032/*! CH0_ERROR_STATUS
3033 * 0b0..An early termination from the device causes error IRQ.
3034 * 0b1..An AHB bus error causes error IRQ.
3035 */
3036#define APBH_CTRL2_TOG_CH0_ERROR_STATUS(x) \
3037 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK)
3038#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK (0x20000U)
3039#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT (17U)
3040/*! CH1_ERROR_STATUS
3041 * 0b0..An early termination from the device causes error IRQ.
3042 * 0b1..An AHB bus error causes error IRQ.
3043 */
3044#define APBH_CTRL2_TOG_CH1_ERROR_STATUS(x) \
3045 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK)
3046#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK (0x40000U)
3047#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT (18U)
3048/*! CH2_ERROR_STATUS
3049 * 0b0..An early termination from the device causes error IRQ.
3050 * 0b1..An AHB bus error causes error IRQ.
3051 */
3052#define APBH_CTRL2_TOG_CH2_ERROR_STATUS(x) \
3053 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK)
3054#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK (0x80000U)
3055#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT (19U)
3056/*! CH3_ERROR_STATUS
3057 * 0b0..An early termination from the device causes error IRQ.
3058 * 0b1..An AHB bus error causes error IRQ.
3059 */
3060#define APBH_CTRL2_TOG_CH3_ERROR_STATUS(x) \
3061 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK)
3062#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK (0x100000U)
3063#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT (20U)
3064/*! CH4_ERROR_STATUS
3065 * 0b0..An early termination from the device causes error IRQ.
3066 * 0b1..An AHB bus error causes error IRQ.
3067 */
3068#define APBH_CTRL2_TOG_CH4_ERROR_STATUS(x) \
3069 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK)
3070#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK (0x200000U)
3071#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT (21U)
3072/*! CH5_ERROR_STATUS
3073 * 0b0..An early termination from the device causes error IRQ.
3074 * 0b1..An AHB bus error causes error IRQ.
3075 */
3076#define APBH_CTRL2_TOG_CH5_ERROR_STATUS(x) \
3077 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK)
3078#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK (0x400000U)
3079#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT (22U)
3080/*! CH6_ERROR_STATUS
3081 * 0b0..An early termination from the device causes error IRQ.
3082 * 0b1..An AHB bus error causes error IRQ.
3083 */
3084#define APBH_CTRL2_TOG_CH6_ERROR_STATUS(x) \
3085 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK)
3086#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK (0x800000U)
3087#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT (23U)
3088/*! CH7_ERROR_STATUS
3089 * 0b0..An early termination from the device causes error IRQ.
3090 * 0b1..An AHB bus error causes error IRQ.
3091 */
3092#define APBH_CTRL2_TOG_CH7_ERROR_STATUS(x) \
3093 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK)
3094#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK (0x1000000U)
3095#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT (24U)
3096/*! CH8_ERROR_STATUS
3097 * 0b0..An early termination from the device causes error IRQ.
3098 * 0b1..An AHB bus error causes error IRQ.
3099 */
3100#define APBH_CTRL2_TOG_CH8_ERROR_STATUS(x) \
3101 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK)
3102#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK (0x2000000U)
3103#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT (25U)
3104/*! CH9_ERROR_STATUS
3105 * 0b0..An early termination from the device causes error IRQ.
3106 * 0b1..An AHB bus error causes error IRQ.
3107 */
3108#define APBH_CTRL2_TOG_CH9_ERROR_STATUS(x) \
3109 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK)
3110#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK (0x4000000U)
3111#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT (26U)
3112/*! CH10_ERROR_STATUS
3113 * 0b0..An early termination from the device causes error IRQ.
3114 * 0b1..An AHB bus error causes error IRQ.
3115 */
3116#define APBH_CTRL2_TOG_CH10_ERROR_STATUS(x) \
3117 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK)
3118#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK (0x8000000U)
3119#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT (27U)
3120/*! CH11_ERROR_STATUS
3121 * 0b0..An early termination from the device causes error IRQ.
3122 * 0b1..An AHB bus error causes error IRQ.
3123 */
3124#define APBH_CTRL2_TOG_CH11_ERROR_STATUS(x) \
3125 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK)
3126#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK (0x10000000U)
3127#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT (28U)
3128/*! CH12_ERROR_STATUS
3129 * 0b0..An early termination from the device causes error IRQ.
3130 * 0b1..An AHB bus error causes error IRQ.
3131 */
3132#define APBH_CTRL2_TOG_CH12_ERROR_STATUS(x) \
3133 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK)
3134#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK (0x20000000U)
3135#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT (29U)
3136/*! CH13_ERROR_STATUS
3137 * 0b0..An early termination from the device causes error IRQ.
3138 * 0b1..An AHB bus error causes error IRQ.
3139 */
3140#define APBH_CTRL2_TOG_CH13_ERROR_STATUS(x) \
3141 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK)
3142#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK (0x40000000U)
3143#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT (30U)
3144/*! CH14_ERROR_STATUS
3145 * 0b0..An early termination from the device causes error IRQ.
3146 * 0b1..An AHB bus error causes error IRQ.
3147 */
3148#define APBH_CTRL2_TOG_CH14_ERROR_STATUS(x) \
3149 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK)
3150#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK (0x80000000U)
3151#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT (31U)
3152/*! CH15_ERROR_STATUS
3153 * 0b0..An early termination from the device causes error IRQ.
3154 * 0b1..An AHB bus error causes error IRQ.
3155 */
3156#define APBH_CTRL2_TOG_CH15_ERROR_STATUS(x) \
3157 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK)
3158/*! @} */
3159
3160/*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */
3161/*! @{ */
3162#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU)
3163#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U)
3164/*! FREEZE_CHANNEL
3165 * 0b0000000000000001..NAND0
3166 * 0b0000000000000010..NAND1
3167 * 0b0000000000000100..NAND2
3168 * 0b0000000000001000..NAND3
3169 * 0b0000000000010000..NAND4
3170 * 0b0000000000100000..NAND5
3171 * 0b0000000001000000..NAND6
3172 * 0b0000000010000000..NAND7
3173 * 0b0000000100000000..SSP
3174 */
3175#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) \
3176 (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK)
3177#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U)
3178#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U)
3179/*! RESET_CHANNEL
3180 * 0b0000000000000001..NAND0
3181 * 0b0000000000000010..NAND1
3182 * 0b0000000000000100..NAND2
3183 * 0b0000000000001000..NAND3
3184 * 0b0000000000010000..NAND4
3185 * 0b0000000000100000..NAND5
3186 * 0b0000000001000000..NAND6
3187 * 0b0000000010000000..NAND7
3188 * 0b0000000100000000..SSP
3189 */
3190#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) \
3191 (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK)
3192/*! @} */
3193
3194/*! @name CHANNEL_CTRL_SET - AHB to APBH Bridge Channel Register */
3195/*! @{ */
3196#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK (0xFFFFU)
3197#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT (0U)
3198/*! FREEZE_CHANNEL
3199 * 0b0000000000000001..NAND0
3200 * 0b0000000000000010..NAND1
3201 * 0b0000000000000100..NAND2
3202 * 0b0000000000001000..NAND3
3203 * 0b0000000000010000..NAND4
3204 * 0b0000000000100000..NAND5
3205 * 0b0000000001000000..NAND6
3206 * 0b0000000010000000..NAND7
3207 * 0b0000000100000000..SSP
3208 */
3209#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL(x) \
3210 (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT)) & \
3211 APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK)
3212#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK (0xFFFF0000U)
3213#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT (16U)
3214/*! RESET_CHANNEL
3215 * 0b0000000000000001..NAND0
3216 * 0b0000000000000010..NAND1
3217 * 0b0000000000000100..NAND2
3218 * 0b0000000000001000..NAND3
3219 * 0b0000000000010000..NAND4
3220 * 0b0000000000100000..NAND5
3221 * 0b0000000001000000..NAND6
3222 * 0b0000000010000000..NAND7
3223 * 0b0000000100000000..SSP
3224 */
3225#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL(x) \
3226 (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT)) & \
3227 APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK)
3228/*! @} */
3229
3230/*! @name CHANNEL_CTRL_CLR - AHB to APBH Bridge Channel Register */
3231/*! @{ */
3232#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK (0xFFFFU)
3233#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT (0U)
3234/*! FREEZE_CHANNEL
3235 * 0b0000000000000001..NAND0
3236 * 0b0000000000000010..NAND1
3237 * 0b0000000000000100..NAND2
3238 * 0b0000000000001000..NAND3
3239 * 0b0000000000010000..NAND4
3240 * 0b0000000000100000..NAND5
3241 * 0b0000000001000000..NAND6
3242 * 0b0000000010000000..NAND7
3243 * 0b0000000100000000..SSP
3244 */
3245#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL(x) \
3246 (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT)) & \
3247 APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK)
3248#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK (0xFFFF0000U)
3249#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT (16U)
3250/*! RESET_CHANNEL
3251 * 0b0000000000000001..NAND0
3252 * 0b0000000000000010..NAND1
3253 * 0b0000000000000100..NAND2
3254 * 0b0000000000001000..NAND3
3255 * 0b0000000000010000..NAND4
3256 * 0b0000000000100000..NAND5
3257 * 0b0000000001000000..NAND6
3258 * 0b0000000010000000..NAND7
3259 * 0b0000000100000000..SSP
3260 */
3261#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL(x) \
3262 (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT)) & \
3263 APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK)
3264/*! @} */
3265
3266/*! @name CHANNEL_CTRL_TOG - AHB to APBH Bridge Channel Register */
3267/*! @{ */
3268#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK (0xFFFFU)
3269#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT (0U)
3270/*! FREEZE_CHANNEL
3271 * 0b0000000000000001..NAND0
3272 * 0b0000000000000010..NAND1
3273 * 0b0000000000000100..NAND2
3274 * 0b0000000000001000..NAND3
3275 * 0b0000000000010000..NAND4
3276 * 0b0000000000100000..NAND5
3277 * 0b0000000001000000..NAND6
3278 * 0b0000000010000000..NAND7
3279 * 0b0000000100000000..SSP
3280 */
3281#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL(x) \
3282 (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT)) & \
3283 APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK)
3284#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK (0xFFFF0000U)
3285#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT (16U)
3286/*! RESET_CHANNEL
3287 * 0b0000000000000001..NAND0
3288 * 0b0000000000000010..NAND1
3289 * 0b0000000000000100..NAND2
3290 * 0b0000000000001000..NAND3
3291 * 0b0000000000010000..NAND4
3292 * 0b0000000000100000..NAND5
3293 * 0b0000000001000000..NAND6
3294 * 0b0000000010000000..NAND7
3295 * 0b0000000100000000..SSP
3296 */
3297#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL(x) \
3298 (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT)) & \
3299 APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK)
3300/*! @} */
3301
3302/*! @name DEVSEL - AHB to APBH DMA Device Assignment Register */
3303/*! @{ */
3304#define APBH_DEVSEL_CH0_MASK (0x3U)
3305#define APBH_DEVSEL_CH0_SHIFT (0U)
3306#define APBH_DEVSEL_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH0_SHIFT)) & APBH_DEVSEL_CH0_MASK)
3307#define APBH_DEVSEL_CH1_MASK (0xCU)
3308#define APBH_DEVSEL_CH1_SHIFT (2U)
3309#define APBH_DEVSEL_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH1_SHIFT)) & APBH_DEVSEL_CH1_MASK)
3310#define APBH_DEVSEL_CH2_MASK (0x30U)
3311#define APBH_DEVSEL_CH2_SHIFT (4U)
3312#define APBH_DEVSEL_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH2_SHIFT)) & APBH_DEVSEL_CH2_MASK)
3313#define APBH_DEVSEL_CH3_MASK (0xC0U)
3314#define APBH_DEVSEL_CH3_SHIFT (6U)
3315#define APBH_DEVSEL_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH3_SHIFT)) & APBH_DEVSEL_CH3_MASK)
3316#define APBH_DEVSEL_CH4_MASK (0x300U)
3317#define APBH_DEVSEL_CH4_SHIFT (8U)
3318#define APBH_DEVSEL_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH4_SHIFT)) & APBH_DEVSEL_CH4_MASK)
3319#define APBH_DEVSEL_CH5_MASK (0xC00U)
3320#define APBH_DEVSEL_CH5_SHIFT (10U)
3321#define APBH_DEVSEL_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH5_SHIFT)) & APBH_DEVSEL_CH5_MASK)
3322#define APBH_DEVSEL_CH6_MASK (0x3000U)
3323#define APBH_DEVSEL_CH6_SHIFT (12U)
3324#define APBH_DEVSEL_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH6_SHIFT)) & APBH_DEVSEL_CH6_MASK)
3325#define APBH_DEVSEL_CH7_MASK (0xC000U)
3326#define APBH_DEVSEL_CH7_SHIFT (14U)
3327#define APBH_DEVSEL_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH7_SHIFT)) & APBH_DEVSEL_CH7_MASK)
3328#define APBH_DEVSEL_CH8_MASK (0x30000U)
3329#define APBH_DEVSEL_CH8_SHIFT (16U)
3330#define APBH_DEVSEL_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH8_SHIFT)) & APBH_DEVSEL_CH8_MASK)
3331#define APBH_DEVSEL_CH9_MASK (0xC0000U)
3332#define APBH_DEVSEL_CH9_SHIFT (18U)
3333#define APBH_DEVSEL_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH9_SHIFT)) & APBH_DEVSEL_CH9_MASK)
3334#define APBH_DEVSEL_CH10_MASK (0x300000U)
3335#define APBH_DEVSEL_CH10_SHIFT (20U)
3336#define APBH_DEVSEL_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH10_SHIFT)) & APBH_DEVSEL_CH10_MASK)
3337#define APBH_DEVSEL_CH11_MASK (0xC00000U)
3338#define APBH_DEVSEL_CH11_SHIFT (22U)
3339#define APBH_DEVSEL_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH11_SHIFT)) & APBH_DEVSEL_CH11_MASK)
3340#define APBH_DEVSEL_CH12_MASK (0x3000000U)
3341#define APBH_DEVSEL_CH12_SHIFT (24U)
3342#define APBH_DEVSEL_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH12_SHIFT)) & APBH_DEVSEL_CH12_MASK)
3343#define APBH_DEVSEL_CH13_MASK (0xC000000U)
3344#define APBH_DEVSEL_CH13_SHIFT (26U)
3345#define APBH_DEVSEL_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH13_SHIFT)) & APBH_DEVSEL_CH13_MASK)
3346#define APBH_DEVSEL_CH14_MASK (0x30000000U)
3347#define APBH_DEVSEL_CH14_SHIFT (28U)
3348#define APBH_DEVSEL_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH14_SHIFT)) & APBH_DEVSEL_CH14_MASK)
3349#define APBH_DEVSEL_CH15_MASK (0xC0000000U)
3350#define APBH_DEVSEL_CH15_SHIFT (30U)
3351#define APBH_DEVSEL_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH15_SHIFT)) & APBH_DEVSEL_CH15_MASK)
3352/*! @} */
3353
3354/*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */
3355/*! @{ */
3356#define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U)
3357#define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U)
3358#define APBH_DMA_BURST_SIZE_CH0(x) \
3359 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK)
3360#define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU)
3361#define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U)
3362#define APBH_DMA_BURST_SIZE_CH1(x) \
3363 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK)
3364#define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U)
3365#define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U)
3366#define APBH_DMA_BURST_SIZE_CH2(x) \
3367 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK)
3368#define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U)
3369#define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U)
3370#define APBH_DMA_BURST_SIZE_CH3(x) \
3371 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK)
3372#define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U)
3373#define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U)
3374#define APBH_DMA_BURST_SIZE_CH4(x) \
3375 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK)
3376#define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U)
3377#define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U)
3378#define APBH_DMA_BURST_SIZE_CH5(x) \
3379 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK)
3380#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U)
3381#define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U)
3382#define APBH_DMA_BURST_SIZE_CH6(x) \
3383 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK)
3384#define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U)
3385#define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U)
3386#define APBH_DMA_BURST_SIZE_CH7(x) \
3387 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK)
3388#define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U)
3389#define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U)
3390/*! CH8
3391 * 0b00..BURST0
3392 * 0b01..BURST4
3393 * 0b10..BURST8
3394 */
3395#define APBH_DMA_BURST_SIZE_CH8(x) \
3396 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK)
3397#define APBH_DMA_BURST_SIZE_CH9_MASK (0xC0000U)
3398#define APBH_DMA_BURST_SIZE_CH9_SHIFT (18U)
3399#define APBH_DMA_BURST_SIZE_CH9(x) \
3400 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH9_SHIFT)) & APBH_DMA_BURST_SIZE_CH9_MASK)
3401#define APBH_DMA_BURST_SIZE_CH10_MASK (0x300000U)
3402#define APBH_DMA_BURST_SIZE_CH10_SHIFT (20U)
3403#define APBH_DMA_BURST_SIZE_CH10(x) \
3404 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH10_SHIFT)) & APBH_DMA_BURST_SIZE_CH10_MASK)
3405#define APBH_DMA_BURST_SIZE_CH11_MASK (0xC00000U)
3406#define APBH_DMA_BURST_SIZE_CH11_SHIFT (22U)
3407#define APBH_DMA_BURST_SIZE_CH11(x) \
3408 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH11_SHIFT)) & APBH_DMA_BURST_SIZE_CH11_MASK)
3409#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3000000U)
3410#define APBH_DMA_BURST_SIZE_CH12_SHIFT (24U)
3411#define APBH_DMA_BURST_SIZE_CH12(x) \
3412 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH12_SHIFT)) & APBH_DMA_BURST_SIZE_CH12_MASK)
3413#define APBH_DMA_BURST_SIZE_CH13_MASK (0xC000000U)
3414#define APBH_DMA_BURST_SIZE_CH13_SHIFT (26U)
3415#define APBH_DMA_BURST_SIZE_CH13(x) \
3416 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH13_SHIFT)) & APBH_DMA_BURST_SIZE_CH13_MASK)
3417#define APBH_DMA_BURST_SIZE_CH14_MASK (0x30000000U)
3418#define APBH_DMA_BURST_SIZE_CH14_SHIFT (28U)
3419#define APBH_DMA_BURST_SIZE_CH14(x) \
3420 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH14_SHIFT)) & APBH_DMA_BURST_SIZE_CH14_MASK)
3421#define APBH_DMA_BURST_SIZE_CH15_MASK (0xC0000000U)
3422#define APBH_DMA_BURST_SIZE_CH15_SHIFT (30U)
3423#define APBH_DMA_BURST_SIZE_CH15(x) \
3424 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH15_SHIFT)) & APBH_DMA_BURST_SIZE_CH15_MASK)
3425/*! @} */
3426
3427/*! @name DEBUG - AHB to APBH DMA Debug Register */
3428/*! @{ */
3429#define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U)
3430#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U)
3431#define APBH_DEBUG_GPMI_ONE_FIFO(x) \
3432 (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK)
3433/*! @} */
3434
3435/*! @name CH_CURCMDAR - APBH DMA Channel n Current Command Address Register */
3436/*! @{ */
3437#define APBH_CH_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3438#define APBH_CH_CURCMDAR_CMD_ADDR_SHIFT (0U)
3439#define APBH_CH_CURCMDAR_CMD_ADDR(x) \
3440 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_CURCMDAR_CMD_ADDR_MASK)
3441/*! @} */
3442
3443/* The count of APBH_CH_CURCMDAR */
3444#define APBH_CH_CURCMDAR_COUNT (16U)
3445
3446/*! @name CH_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
3447/*! @{ */
3448#define APBH_CH_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3449#define APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT (0U)
3450#define APBH_CH_NXTCMDAR_CMD_ADDR(x) \
3451 (((uint32_t)(((uint32_t)(x)) << APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_NXTCMDAR_CMD_ADDR_MASK)
3452/*! @} */
3453
3454/* The count of APBH_CH_NXTCMDAR */
3455#define APBH_CH_NXTCMDAR_COUNT (16U)
3456
3457/*! @name CH_CMD - APBH DMA Channel n Command Register */
3458/*! @{ */
3459#define APBH_CH_CMD_COMMAND_MASK (0x3U)
3460#define APBH_CH_CMD_COMMAND_SHIFT (0U)
3461/*! COMMAND
3462 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
3463 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified
3464 * number of bytes. 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for
3465 * the specified number of bytes. 0b11..Perform any requested PIO word transfers and then perform a conditional branch
3466 * to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS
3467 * as a chain pointer if the peripheral sense line is false.
3468 */
3469#define APBH_CH_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_COMMAND_SHIFT)) & APBH_CH_CMD_COMMAND_MASK)
3470#define APBH_CH_CMD_CHAIN_MASK (0x4U)
3471#define APBH_CH_CMD_CHAIN_SHIFT (2U)
3472#define APBH_CH_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CHAIN_SHIFT)) & APBH_CH_CMD_CHAIN_MASK)
3473#define APBH_CH_CMD_IRQONCMPLT_MASK (0x8U)
3474#define APBH_CH_CMD_IRQONCMPLT_SHIFT (3U)
3475#define APBH_CH_CMD_IRQONCMPLT(x) \
3476 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_IRQONCMPLT_SHIFT)) & APBH_CH_CMD_IRQONCMPLT_MASK)
3477#define APBH_CH_CMD_NANDLOCK_MASK (0x10U)
3478#define APBH_CH_CMD_NANDLOCK_SHIFT (4U)
3479#define APBH_CH_CMD_NANDLOCK(x) \
3480 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDLOCK_SHIFT)) & APBH_CH_CMD_NANDLOCK_MASK)
3481#define APBH_CH_CMD_NANDWAIT4READY_MASK (0x20U)
3482#define APBH_CH_CMD_NANDWAIT4READY_SHIFT (5U)
3483#define APBH_CH_CMD_NANDWAIT4READY(x) \
3484 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH_CMD_NANDWAIT4READY_MASK)
3485#define APBH_CH_CMD_SEMAPHORE_MASK (0x40U)
3486#define APBH_CH_CMD_SEMAPHORE_SHIFT (6U)
3487#define APBH_CH_CMD_SEMAPHORE(x) \
3488 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_SEMAPHORE_SHIFT)) & APBH_CH_CMD_SEMAPHORE_MASK)
3489#define APBH_CH_CMD_WAIT4ENDCMD_MASK (0x80U)
3490#define APBH_CH_CMD_WAIT4ENDCMD_SHIFT (7U)
3491#define APBH_CH_CMD_WAIT4ENDCMD(x) \
3492 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH_CMD_WAIT4ENDCMD_MASK)
3493#define APBH_CH_CMD_HALTONTERMINATE_MASK (0x100U)
3494#define APBH_CH_CMD_HALTONTERMINATE_SHIFT (8U)
3495#define APBH_CH_CMD_HALTONTERMINATE(x) \
3496 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH_CMD_HALTONTERMINATE_MASK)
3497#define APBH_CH_CMD_CMDWORDS_MASK (0xF000U)
3498#define APBH_CH_CMD_CMDWORDS_SHIFT (12U)
3499#define APBH_CH_CMD_CMDWORDS(x) \
3500 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CMDWORDS_SHIFT)) & APBH_CH_CMD_CMDWORDS_MASK)
3501#define APBH_CH_CMD_XFER_COUNT_MASK (0xFFFF0000U)
3502#define APBH_CH_CMD_XFER_COUNT_SHIFT (16U)
3503#define APBH_CH_CMD_XFER_COUNT(x) \
3504 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_XFER_COUNT_SHIFT)) & APBH_CH_CMD_XFER_COUNT_MASK)
3505/*! @} */
3506
3507/* The count of APBH_CH_CMD */
3508#define APBH_CH_CMD_COUNT (16U)
3509
3510/*! @name CH_BAR - APBH DMA Channel n Buffer Address Register */
3511/*! @{ */
3512#define APBH_CH_BAR_ADDRESS_MASK (0xFFFFFFFFU)
3513#define APBH_CH_BAR_ADDRESS_SHIFT (0U)
3514#define APBH_CH_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_BAR_ADDRESS_SHIFT)) & APBH_CH_BAR_ADDRESS_MASK)
3515/*! @} */
3516
3517/* The count of APBH_CH_BAR */
3518#define APBH_CH_BAR_COUNT (16U)
3519
3520/*! @name CH_SEMA - APBH DMA Channel n Semaphore Register */
3521/*! @{ */
3522#define APBH_CH_SEMA_INCREMENT_SEMA_MASK (0xFFU)
3523#define APBH_CH_SEMA_INCREMENT_SEMA_SHIFT (0U)
3524#define APBH_CH_SEMA_INCREMENT_SEMA(x) \
3525 (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH_SEMA_INCREMENT_SEMA_MASK)
3526#define APBH_CH_SEMA_PHORE_MASK (0xFF0000U)
3527#define APBH_CH_SEMA_PHORE_SHIFT (16U)
3528#define APBH_CH_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_PHORE_SHIFT)) & APBH_CH_SEMA_PHORE_MASK)
3529/*! @} */
3530
3531/* The count of APBH_CH_SEMA */
3532#define APBH_CH_SEMA_COUNT (16U)
3533
3534/*! @name CH_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
3535/*! @{ */
3536#define APBH_CH_DEBUG1_STATEMACHINE_MASK (0x1FU)
3537#define APBH_CH_DEBUG1_STATEMACHINE_SHIFT (0U)
3538/*! STATEMACHINE
3539 * 0b00000..This is the idle state of the DMA state machine.
3540 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
3541 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
3542 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
3543 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
3544 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
3545 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the
3546 * PIO words when PIO count is greater than 1.
3547 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
3548 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on
3549 * the APB. 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to
3550 * complete. 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter
3551 * accepts the request from this channel. 0b01101..During DMA Read transfers, the state machine waits in this state
3552 * until the AHB master arbiter accepts the request from this channel. 0b01110..Upon completion of the DMA transfers,
3553 * this state checks the value of the Chain bit and branches accordingly. 0b01111..The state machine goes to this state
3554 * after the DMA transfers are complete, and determines what step to take next. 0b10100..When a terminate signal is set,
3555 * the state machine enters this state until the current AHB transfer is completed. 0b10101..When the Wait for Command
3556 * End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
3557 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write
3558 * to the AHB memory space. 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters
3559 * this state and effectively halts. A channel reset is required to exit this state 0b11110..If the Chain bit is a 0,
3560 * the state machine enters this state and effectively halts. 0b11111..When the NAND Wait for Ready bit is set, the
3561 * state machine enters this state until the GPMI device indicates that the external device is ready.
3562 */
3563#define APBH_CH_DEBUG1_STATEMACHINE(x) \
3564 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH_DEBUG1_STATEMACHINE_MASK)
3565#define APBH_CH_DEBUG1_RSVD1_MASK (0xFFFE0U)
3566#define APBH_CH_DEBUG1_RSVD1_SHIFT (5U)
3567#define APBH_CH_DEBUG1_RSVD1(x) \
3568 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RSVD1_SHIFT)) & APBH_CH_DEBUG1_RSVD1_MASK)
3569#define APBH_CH_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
3570#define APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
3571#define APBH_CH_DEBUG1_WR_FIFO_FULL(x) \
3572 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_FULL_MASK)
3573#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
3574#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
3575#define APBH_CH_DEBUG1_WR_FIFO_EMPTY(x) \
3576 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK)
3577#define APBH_CH_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
3578#define APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
3579#define APBH_CH_DEBUG1_RD_FIFO_FULL(x) \
3580 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_FULL_MASK)
3581#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
3582#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
3583#define APBH_CH_DEBUG1_RD_FIFO_EMPTY(x) \
3584 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK)
3585#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
3586#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
3587#define APBH_CH_DEBUG1_NEXTCMDADDRVALID(x) \
3588 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK)
3589#define APBH_CH_DEBUG1_LOCK_MASK (0x2000000U)
3590#define APBH_CH_DEBUG1_LOCK_SHIFT (25U)
3591#define APBH_CH_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_LOCK_SHIFT)) & APBH_CH_DEBUG1_LOCK_MASK)
3592#define APBH_CH_DEBUG1_READY_MASK (0x4000000U)
3593#define APBH_CH_DEBUG1_READY_SHIFT (26U)
3594#define APBH_CH_DEBUG1_READY(x) \
3595 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_READY_SHIFT)) & APBH_CH_DEBUG1_READY_MASK)
3596#define APBH_CH_DEBUG1_SENSE_MASK (0x8000000U)
3597#define APBH_CH_DEBUG1_SENSE_SHIFT (27U)
3598#define APBH_CH_DEBUG1_SENSE(x) \
3599 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_SENSE_SHIFT)) & APBH_CH_DEBUG1_SENSE_MASK)
3600#define APBH_CH_DEBUG1_END_MASK (0x10000000U)
3601#define APBH_CH_DEBUG1_END_SHIFT (28U)
3602#define APBH_CH_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_END_SHIFT)) & APBH_CH_DEBUG1_END_MASK)
3603#define APBH_CH_DEBUG1_KICK_MASK (0x20000000U)
3604#define APBH_CH_DEBUG1_KICK_SHIFT (29U)
3605#define APBH_CH_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_KICK_SHIFT)) & APBH_CH_DEBUG1_KICK_MASK)
3606#define APBH_CH_DEBUG1_BURST_MASK (0x40000000U)
3607#define APBH_CH_DEBUG1_BURST_SHIFT (30U)
3608#define APBH_CH_DEBUG1_BURST(x) \
3609 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_BURST_SHIFT)) & APBH_CH_DEBUG1_BURST_MASK)
3610#define APBH_CH_DEBUG1_REQ_MASK (0x80000000U)
3611#define APBH_CH_DEBUG1_REQ_SHIFT (31U)
3612#define APBH_CH_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_REQ_SHIFT)) & APBH_CH_DEBUG1_REQ_MASK)
3613/*! @} */
3614
3615/* The count of APBH_CH_DEBUG1 */
3616#define APBH_CH_DEBUG1_COUNT (16U)
3617
3618/*! @name CH_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
3619/*! @{ */
3620#define APBH_CH_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
3621#define APBH_CH_DEBUG2_AHB_BYTES_SHIFT (0U)
3622#define APBH_CH_DEBUG2_AHB_BYTES(x) \
3623 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH_DEBUG2_AHB_BYTES_MASK)
3624#define APBH_CH_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
3625#define APBH_CH_DEBUG2_APB_BYTES_SHIFT (16U)
3626#define APBH_CH_DEBUG2_APB_BYTES(x) \
3627 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH_DEBUG2_APB_BYTES_MASK)
3628/*! @} */
3629
3630/* The count of APBH_CH_DEBUG2 */
3631#define APBH_CH_DEBUG2_COUNT (16U)
3632
3633/*! @name VERSION - APBH Bridge Version Register */
3634/*! @{ */
3635#define APBH_VERSION_STEP_MASK (0xFFFFU)
3636#define APBH_VERSION_STEP_SHIFT (0U)
3637#define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK)
3638#define APBH_VERSION_MINOR_MASK (0xFF0000U)
3639#define APBH_VERSION_MINOR_SHIFT (16U)
3640#define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK)
3641#define APBH_VERSION_MAJOR_MASK (0xFF000000U)
3642#define APBH_VERSION_MAJOR_SHIFT (24U)
3643#define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK)
3644/*! @} */
3645
3646/*!
3647 * @}
3648 */ /* end of group APBH_Register_Masks */
3649
3650/* APBH - Peripheral instance base addresses */
3651/** Peripheral APBH base address */
3652#define APBH_BASE (0x33000000u)
3653/** Peripheral APBH base pointer */
3654#define APBH ((APBH_Type *)APBH_BASE)
3655/** Array initializer of APBH peripheral base addresses */
3656#define APBH_BASE_ADDRS \
3657 { \
3658 APBH_BASE \
3659 }
3660/** Array initializer of APBH peripheral base pointers */
3661#define APBH_BASE_PTRS \
3662 { \
3663 APBH \
3664 }
3665/** Interrupt vectors for the APBH peripheral type */
3666#define APBH_IRQS \
3667 { \
3668 APBHDMA_IRQn \
3669 }
3670
3671/*!
3672 * @}
3673 */ /* end of group APBH_Peripheral_Access_Layer */
3674
3675/* ----------------------------------------------------------------------------
3676 -- ASRC Peripheral Access Layer
3677 ---------------------------------------------------------------------------- */
3678
3679/*!
3680 * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer
3681 * @{
3682 */
3683
3684/** ASRC - Register Layout Typedef */
3685typedef struct
3686{
3687 __O uint32_t WRFIFO[4]; /**< ASRC Input Write FIFO, array offset: 0x0, array step: 0x4 */
3688 __I uint32_t RDFIFO[4]; /**< ASRC Output Read FIFO, array offset: 0x10, array step: 0x4 */
3689 __IO uint32_t CTX_CTRL[4]; /**< ASRC Context Control, array offset: 0x20, array step: 0x4 */
3690 __IO uint32_t CTX_CTRL_EXT1[4]; /**< ASRC Context Control Extended 1, array offset: 0x30, array step: 0x4 */
3691 __IO uint32_t CTX_CTRL_EXT2[4]; /**< ASRC Context Control Extended 2, array offset: 0x40, array step: 0x4 */
3692 __IO uint32_t CTRL_IN_ACCESS[4]; /**< ASRC Control Input Access, array offset: 0x50, array step: 0x4 */
3693 __IO uint32_t PROC_CTRL_SLOT0_R0[4]; /**< ASRC Datapath Processor Control Slot0 Register0, array offset: 0x60, array
3694 step: 0x4 */
3695 __IO uint32_t PROC_CTRL_SLOT0_R1[4]; /**< ASRC Datapath Processor Control Slot0 Register1, array offset: 0x70, array
3696 step: 0x4 */
3697 __IO uint32_t PROC_CTRL_SLOT0_R2[4]; /**< ASRC Datapath Processor Control Slot0 Register2, array offset: 0x80, array
3698 step: 0x4 */
3699 __IO uint32_t PROC_CTRL_SLOT0_R3[4]; /**< ASRC Datapath Processor Control Slot0 Register3, array offset: 0x90, array
3700 step: 0x4 */
3701 __IO uint32_t PROC_CTRL_SLOT1_R0[4]; /**< ASRC Datapath Processor Control Slot1 Register0, array offset: 0xA0, array
3702 step: 0x4 */
3703 __IO uint32_t PROC_CTRL_SLOT1_R1[4]; /**< ASRC Datapath Processor Control SLOT1 Register1, array offset: 0xB0, array
3704 step: 0x4 */
3705 __IO uint32_t PROC_CTRL_SLOT1_R2[4]; /**< ASRC Datapath Processor Control SLOT1 Register2, array offset: 0xC0, array
3706 step: 0x4 */
3707 __IO uint32_t PROC_CTRL_SLOT1_R3[4]; /**< ASRC Datapath Processor Control SLOT1 Register3, array offset: 0xD0, array
3708 step: 0x4 */
3709 __IO uint32_t CTX_OUT_CTRL[4]; /**< ASRC Context Output Control, array offset: 0xE0, array step: 0x4 */
3710 __IO uint32_t CTRL_OUT_ACCESS[4]; /**< ASRC Control Output Access, array offset: 0xF0, array step: 0x4 */
3711 __I uint32_t SAMPLE_FIFO_STATUS[4]; /**< ASRC Sample FIFO Status, array offset: 0x100, array step: 0x4 */
3712 struct
3713 { /* offset: 0x110, array step: 0x8 */
3714 __IO uint32_t RS_RATIO_LOW; /**< ASRC Resampling Ratio Low, array offset: 0x110, array step: 0x8 */
3715 __IO uint32_t RS_RATIO_HIGH; /**< ASRC Resampling Ratio High, array offset: 0x114, array step: 0x8 */
3716 } RS_RATIO_LOW[4];
3717 __IO uint32_t RS_UPDATE_CTRL[4]; /**< ASRC Resampling Ratio Update Control, array offset: 0x130, array step: 0x4 */
3718 __IO uint32_t RS_UPDATE_RATE[4]; /**< ASRC Resampling Ratio Update Rate, array offset: 0x140, array step: 0x4 */
3719 __IO uint32_t RS_CT_LOW; /**< ASRC Resampling Center Tap Coefficient Low, offset: 0x150 */
3720 __IO uint32_t RS_CT_HIGH; /**< ASRC Resampling Center Tap Coefficient High, offset: 0x154 */
3721 uint8_t RESERVED_0[8];
3722 __IO uint32_t PRE_COEFF_FIFO[4]; /**< ASRC Prefilter Coefficient FIFO, array offset: 0x160, array step: 0x4 */
3723 __O uint32_t CTX_RS_COEFF_MEM; /**< ASRC Context Resampling Coefficient Memory, offset: 0x170 */
3724 __IO uint32_t CTX_RS_COEFF_CTRL; /**< ASRC Context Resampling Coefficient Control, offset: 0x174 */
3725 __IO uint32_t IRQ_CTRL; /**< ASRC Interrupt Control, offset: 0x178 */
3726 __IO uint32_t IRQ_FLAGS; /**< ASRC Interrupt Status Flags, offset: 0x17C */
3727 __IO uint32_t CHANNEL_STATUS_0[4]; /**< ASRC Channel Status 0, array offset: 0x180, array step: 0x4 */
3728 __IO uint32_t CHANNEL_STATUS_1[4]; /**< ASRC Channel Status 1, array offset: 0x190, array step: 0x4 */
3729 __IO uint32_t CHANNEL_STATUS_2[4]; /**< ASRC Channel Status 2, array offset: 0x1A0, array step: 0x4 */
3730 __IO uint32_t CHANNEL_STATUS_3[4]; /**< ASRC Channel Status 3, array offset: 0x1B0, array step: 0x4 */
3731 __IO uint32_t CHANNEL_STATUS_4[4]; /**< ASRC Channel Status 4, array offset: 0x1C0, array step: 0x4 */
3732 __IO uint32_t CHANNEL_STATUS_5[4]; /**< ASRC Channel Status 5, array offset: 0x1D0, array step: 0x4 */
3733} ASRC_Type;
3734
3735/* ----------------------------------------------------------------------------
3736 -- ASRC Register Masks
3737 ---------------------------------------------------------------------------- */
3738
3739/*!
3740 * @addtogroup ASRC_Register_Masks ASRC Register Masks
3741 * @{
3742 */
3743
3744/*! @name WRFIFO - ASRC Input Write FIFO */
3745/*! @{ */
3746#define ASRC_WRFIFO_CTX_WR_DATA_MASK (0xFFFFFFFFU)
3747#define ASRC_WRFIFO_CTX_WR_DATA_SHIFT (0U)
3748#define ASRC_WRFIFO_CTX_WR_DATA(x) \
3749 (((uint32_t)(((uint32_t)(x)) << ASRC_WRFIFO_CTX_WR_DATA_SHIFT)) & ASRC_WRFIFO_CTX_WR_DATA_MASK)
3750/*! @} */
3751
3752/* The count of ASRC_WRFIFO */
3753#define ASRC_WRFIFO_COUNT (4U)
3754
3755/*! @name RDFIFO - ASRC Output Read FIFO */
3756/*! @{ */
3757#define ASRC_RDFIFO_CTX_RD_DATA_MASK (0xFFFFFFFFU)
3758#define ASRC_RDFIFO_CTX_RD_DATA_SHIFT (0U)
3759#define ASRC_RDFIFO_CTX_RD_DATA(x) \
3760 (((uint32_t)(((uint32_t)(x)) << ASRC_RDFIFO_CTX_RD_DATA_SHIFT)) & ASRC_RDFIFO_CTX_RD_DATA_MASK)
3761/*! @} */
3762
3763/* The count of ASRC_RDFIFO */
3764#define ASRC_RDFIFO_COUNT (4U)
3765
3766/*! @name CTX_CTRL - ASRC Context Control */
3767/*! @{ */
3768#define ASRC_CTX_CTRL_NUM_CH_EN_MASK (0x1FU)
3769#define ASRC_CTX_CTRL_NUM_CH_EN_SHIFT (0U)
3770#define ASRC_CTX_CTRL_NUM_CH_EN(x) \
3771 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_NUM_CH_EN_SHIFT)) & ASRC_CTX_CTRL_NUM_CH_EN_MASK)
3772#define ASRC_CTX_CTRL_SIGN_IN_MASK (0x40U)
3773#define ASRC_CTX_CTRL_SIGN_IN_SHIFT (6U)
3774/*! SIGN_IN - Input Data Sign
3775 * 0b0..Signed Format
3776 * 0b1..Unsigned Format
3777 */
3778#define ASRC_CTX_CTRL_SIGN_IN(x) \
3779 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_SIGN_IN_SHIFT)) & ASRC_CTX_CTRL_SIGN_IN_MASK)
3780#define ASRC_CTX_CTRL_FLOAT_FMT_MASK (0x80U)
3781#define ASRC_CTX_CTRL_FLOAT_FMT_SHIFT (7U)
3782/*! FLOAT_FMT - Context Input Floating Point Format
3783 * 0b0..Integer Format
3784 * 0b1..Single Precision Floating Point Format
3785 */
3786#define ASRC_CTX_CTRL_FLOAT_FMT(x) \
3787 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_FLOAT_FMT_SHIFT)) & ASRC_CTX_CTRL_FLOAT_FMT_MASK)
3788#define ASRC_CTX_CTRL_BITS_PER_SAMPLE_MASK (0x300U)
3789#define ASRC_CTX_CTRL_BITS_PER_SAMPLE_SHIFT (8U)
3790/*! BITS_PER_SAMPLE - Number of Bits Per Audio Sample
3791 * 0b00..16-bits Per Sample
3792 * 0b01..20-bits Per Sample
3793 * 0b10..24-bits Per Sample
3794 * 0b11..32-bits Per Sample
3795 */
3796#define ASRC_CTX_CTRL_BITS_PER_SAMPLE(x) \
3797 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_BITS_PER_SAMPLE_SHIFT)) & ASRC_CTX_CTRL_BITS_PER_SAMPLE_MASK)
3798#define ASRC_CTX_CTRL_BIT_REV_MASK (0x400U)
3799#define ASRC_CTX_CTRL_BIT_REV_SHIFT (10U)
3800/*! BIT_REV - Sample Bit Reversal
3801 * 0b0..Keep Input Ordering
3802 * 0b1..Reverse Bit Ordering
3803 */
3804#define ASRC_CTX_CTRL_BIT_REV(x) \
3805 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_BIT_REV_SHIFT)) & ASRC_CTX_CTRL_BIT_REV_MASK)
3806#define ASRC_CTX_CTRL_SAMPLE_POSITION_MASK (0xF800U)
3807#define ASRC_CTX_CTRL_SAMPLE_POSITION_SHIFT (11U)
3808#define ASRC_CTX_CTRL_SAMPLE_POSITION(x) \
3809 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_SAMPLE_POSITION_SHIFT)) & ASRC_CTX_CTRL_SAMPLE_POSITION_MASK)
3810#define ASRC_CTX_CTRL_FIFO_WTMK_MASK (0x7F0000U)
3811#define ASRC_CTX_CTRL_FIFO_WTMK_SHIFT (16U)
3812#define ASRC_CTX_CTRL_FIFO_WTMK(x) \
3813 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_FIFO_WTMK_SHIFT)) & ASRC_CTX_CTRL_FIFO_WTMK_MASK)
3814#define ASRC_CTX_CTRL_FWMDE_MASK (0x10000000U)
3815#define ASRC_CTX_CTRL_FWMDE_SHIFT (28U)
3816/*! FWMDE - FIFO Watermark DMA Enable
3817 * 0b0..Input DMA Requests Not Enabled for This Context
3818 * 0b1..Input DMA Requests Enabled for This Context
3819 */
3820#define ASRC_CTX_CTRL_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_FWMDE_SHIFT)) & ASRC_CTX_CTRL_FWMDE_MASK)
3821#define ASRC_CTX_CTRL_RUN_STOP_MASK (0x20000000U)
3822#define ASRC_CTX_CTRL_RUN_STOP_SHIFT (29U)
3823#define ASRC_CTX_CTRL_RUN_STOP(x) \
3824 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_RUN_STOP_SHIFT)) & ASRC_CTX_CTRL_RUN_STOP_MASK)
3825#define ASRC_CTX_CTRL_RUN_EN_MASK (0x80000000U)
3826#define ASRC_CTX_CTRL_RUN_EN_SHIFT (31U)
3827#define ASRC_CTX_CTRL_RUN_EN(x) \
3828 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_RUN_EN_SHIFT)) & ASRC_CTX_CTRL_RUN_EN_MASK)
3829/*! @} */
3830
3831/* The count of ASRC_CTX_CTRL */
3832#define ASRC_CTX_CTRL_COUNT (4U)
3833
3834/*! @name CTX_CTRL_EXT1 - ASRC Context Control Extended 1 */
3835/*! @{ */
3836#define ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_MASK (0x3U)
3837#define ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_SHIFT (0U)
3838/*! PF_INIT_MODE - Prefilter Initialization Mode
3839 * 0b00..Do not pre-fill any prefilter taps. The first sample written to the ASRC corresponds to the highest index
3840 * prefilter filter tap. 0b01..Replicate the first sample to fill the right half of the prefilter. 0b10..Zero fill the
3841 * right half of the prefilter. 0b11..N/A
3842 */
3843#define ASRC_CTX_CTRL_EXT1_PF_INIT_MODE(x) \
3844 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_MASK)
3845#define ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_MASK (0xCU)
3846#define ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_SHIFT (2U)
3847/*! RS_INIT_MODE - Resampler Initialization Mode
3848 * 0b00..Do not pre-fill any resampler taps. The first sample output from the prefilter corresponds to the highest
3849 * index resampling filter tap. 0b01..Replicate the first prefilter output sample to fill the right half of the
3850 * resampler. 0b10..Fill the right half of the re-sampler with zeros. 0b11..N/A
3851 */
3852#define ASRC_CTX_CTRL_EXT1_RS_INIT_MODE(x) \
3853 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_MASK)
3854#define ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_MASK (0x10U)
3855#define ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_SHIFT (4U)
3856/*! PF_STOP_MODE - Pre-Filter Stop Mode
3857 * 0b0..Replicate the last sample input to the ASRC_WRFIFO for the left-half of the pre-filter on RUN_STOP.
3858 * 0b1..Zero-Fill the left-half of the pre-filter on RUN_STOP.
3859 */
3860#define ASRC_CTX_CTRL_EXT1_PF_STOP_MODE(x) \
3861 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_MASK)
3862#define ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_MASK (0x20U)
3863#define ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_SHIFT (5U)
3864/*! RS_STOP_MODE - Resampler Stop Mode
3865 * 0b0..Replicate the final prefilter output for the left-half of the resampler on RUN_STOP.
3866 * 0b1..Zero-Fill the left-half of the resampler on RUN_STOP.
3867 */
3868#define ASRC_CTX_CTRL_EXT1_RS_STOP_MODE(x) \
3869 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_MASK)
3870#define ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_MASK (0x40U)
3871#define ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_SHIFT (6U)
3872/*! PF_BYPASS_MODE - Prefilter Bypass Mode
3873 * 0b0..Run the prefilter in normal operation.
3874 * 0b1..Run the prefilter in bypass mode.
3875 */
3876#define ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE(x) \
3877 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_MASK)
3878#define ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_MASK (0x80U)
3879#define ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_SHIFT (7U)
3880/*! RS_BYPASS_MODE - Resampler Bypass Mode
3881 * 0b0..Run the resampler in normal operation.
3882 * 0b1..Run the resampler in bypass mode.
3883 */
3884#define ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE(x) \
3885 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_MASK)
3886#define ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_MASK (0x100U)
3887#define ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_SHIFT (8U)
3888/*! PF_TWO_STAGE_EN - Prefilter Two-Stage Enable
3889 * 0b0..The pre-filter will run in single stage mode (ST1 only)
3890 * 0b1..The pre-filter will run in two stage mode (ST1 and ST2)
3891 */
3892#define ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN(x) \
3893 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_SHIFT)) & \
3894 ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_MASK)
3895#define ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_MASK (0x200U)
3896#define ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_SHIFT (9U)
3897/*! PF_ST1_WB_FLOAT - Prefilter Stage1 Writeback Floating Point
3898 * 0b0..The pre-filter stage1 results are stored in 32-bit integer format.
3899 * 0b1..The pre-filter stage1 results are stored in 32-bit floating point format.
3900 */
3901#define ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT(x) \
3902 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_SHIFT)) & \
3903 ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_MASK)
3904#define ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_MASK (0xFF0000U)
3905#define ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_SHIFT (16U)
3906#define ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR(x) \
3907 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_SHIFT)) & \
3908 ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_MASK)
3909#define ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_MASK (0x1000000U)
3910#define ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_SHIFT (24U)
3911#define ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST(x) \
3912 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_SHIFT)) & \
3913 ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_MASK)
3914#define ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_MASK (0x2000000U)
3915#define ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_SHIFT (25U)
3916#define ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR(x) \
3917 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_SHIFT)) & \
3918 ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_MASK)
3919/*! @} */
3920
3921/* The count of ASRC_CTX_CTRL_EXT1 */
3922#define ASRC_CTX_CTRL_EXT1_COUNT (4U)
3923
3924/*! @name CTX_CTRL_EXT2 - ASRC Context Control Extended 2 */
3925/*! @{ */
3926#define ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_MASK (0x1FFU)
3927#define ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_SHIFT (0U)
3928#define ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS(x) \
3929 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_SHIFT)) & ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_MASK)
3930#define ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_MASK (0x1FF0000U)
3931#define ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_SHIFT (16U)
3932#define ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS(x) \
3933 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_SHIFT)) & ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_MASK)
3934/*! @} */
3935
3936/* The count of ASRC_CTX_CTRL_EXT2 */
3937#define ASRC_CTX_CTRL_EXT2_COUNT (4U)
3938
3939/*! @name CTRL_IN_ACCESS - ASRC Control Input Access */
3940/*! @{ */
3941#define ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_MASK (0x3FU)
3942#define ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_SHIFT (0U)
3943#define ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH(x) \
3944 (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_SHIFT)) & ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_MASK)
3945#define ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_MASK (0x3F00U)
3946#define ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_SHIFT (8U)
3947#define ASRC_CTRL_IN_ACCESS_GROUP_LENGTH(x) \
3948 (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_SHIFT)) & ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_MASK)
3949#define ASRC_CTRL_IN_ACCESS_ITERATIONS_MASK (0x3F0000U)
3950#define ASRC_CTRL_IN_ACCESS_ITERATIONS_SHIFT (16U)
3951#define ASRC_CTRL_IN_ACCESS_ITERATIONS(x) \
3952 (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_IN_ACCESS_ITERATIONS_SHIFT)) & ASRC_CTRL_IN_ACCESS_ITERATIONS_MASK)
3953/*! @} */
3954
3955/* The count of ASRC_CTRL_IN_ACCESS */
3956#define ASRC_CTRL_IN_ACCESS_COUNT (4U)
3957
3958/*! @name PROC_CTRL_SLOT0_R0 - ASRC Datapath Processor Control Slot0 Register0 */
3959/*! @{ */
3960#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_MASK (0x1U)
3961#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_SHIFT (0U)
3962/*! SLOT0_EN - SLOT0 Enable
3963 * 0b0..Context SLOT0 is disabled
3964 * 0b1..Context SLOT0 is enabled
3965 */
3966#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN(x) \
3967 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_MASK)
3968#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_MASK (0x6U)
3969#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_SHIFT (1U)
3970#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM(x) \
3971 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_SHIFT)) & \
3972 ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_MASK)
3973#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_MASK (0x1F00U)
3974#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_SHIFT (8U)
3975/*! SLOT0_NUM_CH - SLOT0 Number of Channels
3976 * 0b00000..Context SLOT0 owns 1 of 8 channels
3977 * 0b00001..Context SLOT0 owns 2 of 8 channels
3978 * 0b00010..Context SLOT0 owns 3 of 8 channels
3979 * 0b00011-0b00111..Context SLOT0 owns N of 8 channels
3980 */
3981#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH(x) \
3982 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_SHIFT)) & \
3983 ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_MASK)
3984#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_MASK (0x1F0000U)
3985#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_SHIFT (16U)
3986#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH(x) \
3987 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_SHIFT)) & \
3988 ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_MASK)
3989#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_MASK (0x1F000000U)
3990#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_SHIFT (24U)
3991#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH(x) \
3992 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_SHIFT)) & \
3993 ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_MASK)
3994/*! @} */
3995
3996/* The count of ASRC_PROC_CTRL_SLOT0_R0 */
3997#define ASRC_PROC_CTRL_SLOT0_R0_COUNT (4U)
3998
3999/*! @name PROC_CTRL_SLOT0_R1 - ASRC Datapath Processor Control Slot0 Register1 */
4000/*! @{ */
4001#define ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_MASK (0x1FFFU)
4002#define ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_SHIFT (0U)
4003#define ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP(x) \
4004 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_SHIFT)) & \
4005 ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_MASK)
4006/*! @} */
4007
4008/* The count of ASRC_PROC_CTRL_SLOT0_R1 */
4009#define ASRC_PROC_CTRL_SLOT0_R1_COUNT (4U)
4010
4011/*! @name PROC_CTRL_SLOT0_R2 - ASRC Datapath Processor Control Slot0 Register2 */
4012/*! @{ */
4013#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_MASK (0x1FFFU)
4014#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_SHIFT (0U)
4015#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR(x) \
4016 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_SHIFT)) & \
4017 ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_MASK)
4018#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_MASK (0x1FFF0000U)
4019#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_SHIFT (16U)
4020#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC(x) \
4021 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_SHIFT)) & \
4022 ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_MASK)
4023/*! @} */
4024
4025/* The count of ASRC_PROC_CTRL_SLOT0_R2 */
4026#define ASRC_PROC_CTRL_SLOT0_R2_COUNT (4U)
4027
4028/*! @name PROC_CTRL_SLOT0_R3 - ASRC Datapath Processor Control Slot0 Register3 */
4029/*! @{ */
4030#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_MASK (0x1FFFU)
4031#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_SHIFT (0U)
4032#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR(x) \
4033 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_SHIFT)) & \
4034 ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_MASK)
4035#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_MASK (0x1FFF0000U)
4036#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_SHIFT (16U)
4037#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC(x) \
4038 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_SHIFT)) & \
4039 ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_MASK)
4040/*! @} */
4041
4042/* The count of ASRC_PROC_CTRL_SLOT0_R3 */
4043#define ASRC_PROC_CTRL_SLOT0_R3_COUNT (4U)
4044
4045/*! @name PROC_CTRL_SLOT1_R0 - ASRC Datapath Processor Control Slot1 Register0 */
4046/*! @{ */
4047#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_MASK (0x1U)
4048#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_SHIFT (0U)
4049/*! SLOT1_EN - SLOT1 Enable
4050 * 0b0..Context SLOT1 is disabled
4051 * 0b1..Context SLOT1 is enabled
4052 */
4053#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN(x) \
4054 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_MASK)
4055#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_MASK (0x6U)
4056#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_SHIFT (1U)
4057#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM(x) \
4058 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_SHIFT)) & \
4059 ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_MASK)
4060#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_MASK (0x1F00U)
4061#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_SHIFT (8U)
4062/*! SLOT1_NUM_CH - SLOT1 Number of Channels
4063 * 0b00000..Context SLOT1 owns 1 of 8 channels
4064 * 0b00001..Context SLOT1 owns 2 of 8 channels
4065 * 0b00010..Context SLOT1 owns 3 of 8 channels
4066 * 0b00011-0b00111..Context SLOT1 owns N of 8 channels
4067 */
4068#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH(x) \
4069 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_SHIFT)) & \
4070 ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_MASK)
4071#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_MASK (0x1F0000U)
4072#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_SHIFT (16U)
4073#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH(x) \
4074 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_SHIFT)) & \
4075 ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_MASK)
4076#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_MASK (0x1F000000U)
4077#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_SHIFT (24U)
4078#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH(x) \
4079 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_SHIFT)) & \
4080 ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_MASK)
4081/*! @} */
4082
4083/* The count of ASRC_PROC_CTRL_SLOT1_R0 */
4084#define ASRC_PROC_CTRL_SLOT1_R0_COUNT (4U)
4085
4086/*! @name PROC_CTRL_SLOT1_R1 - ASRC Datapath Processor Control SLOT1 Register1 */
4087/*! @{ */
4088#define ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_MASK (0x1FFFU)
4089#define ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_SHIFT (0U)
4090#define ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP(x) \
4091 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_SHIFT)) & \
4092 ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_MASK)
4093/*! @} */
4094
4095/* The count of ASRC_PROC_CTRL_SLOT1_R1 */
4096#define ASRC_PROC_CTRL_SLOT1_R1_COUNT (4U)
4097
4098/*! @name PROC_CTRL_SLOT1_R2 - ASRC Datapath Processor Control SLOT1 Register2 */
4099/*! @{ */
4100#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_MASK (0x1FFFU)
4101#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_SHIFT (0U)
4102#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR(x) \
4103 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_SHIFT)) & \
4104 ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_MASK)
4105#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_MASK (0x1FFF0000U)
4106#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_SHIFT (16U)
4107#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC(x) \
4108 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_SHIFT)) & \
4109 ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_MASK)
4110/*! @} */
4111
4112/* The count of ASRC_PROC_CTRL_SLOT1_R2 */
4113#define ASRC_PROC_CTRL_SLOT1_R2_COUNT (4U)
4114
4115/*! @name PROC_CTRL_SLOT1_R3 - ASRC Datapath Processor Control SLOT1 Register3 */
4116/*! @{ */
4117#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_MASK (0x1FFFU)
4118#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_SHIFT (0U)
4119#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR(x) \
4120 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_SHIFT)) & \
4121 ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_MASK)
4122#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_MASK (0x1FFF0000U)
4123#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_SHIFT (16U)
4124#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC(x) \
4125 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_SHIFT)) & \
4126 ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_MASK)
4127/*! @} */
4128
4129/* The count of ASRC_PROC_CTRL_SLOT1_R3 */
4130#define ASRC_PROC_CTRL_SLOT1_R3_COUNT (4U)
4131
4132/*! @name CTX_OUT_CTRL - ASRC Context Output Control */
4133/*! @{ */
4134#define ASRC_CTX_OUT_CTRL_DITHER_EN_MASK (0x1U)
4135#define ASRC_CTX_OUT_CTRL_DITHER_EN_SHIFT (0U)
4136#define ASRC_CTX_OUT_CTRL_DITHER_EN(x) \
4137 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_DITHER_EN_SHIFT)) & ASRC_CTX_OUT_CTRL_DITHER_EN_MASK)
4138#define ASRC_CTX_OUT_CTRL_IEC_EN_MASK (0x2U)
4139#define ASRC_CTX_OUT_CTRL_IEC_EN_SHIFT (1U)
4140/*! IEC_EN - IEC60958 Bit-Field Insertion Enable
4141 * 0b0..No Data Insertion Enabled.
4142 * 0b1..IEC60958 Bit-Field Insertion Enabled.
4143 */
4144#define ASRC_CTX_OUT_CTRL_IEC_EN(x) \
4145 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_IEC_EN_SHIFT)) & ASRC_CTX_OUT_CTRL_IEC_EN_MASK)
4146#define ASRC_CTX_OUT_CTRL_IEC_V_DATA_MASK (0x4U)
4147#define ASRC_CTX_OUT_CTRL_IEC_V_DATA_SHIFT (2U)
4148#define ASRC_CTX_OUT_CTRL_IEC_V_DATA(x) \
4149 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_IEC_V_DATA_SHIFT)) & ASRC_CTX_OUT_CTRL_IEC_V_DATA_MASK)
4150#define ASRC_CTX_OUT_CTRL_SIGN_OUT_MASK (0x40U)
4151#define ASRC_CTX_OUT_CTRL_SIGN_OUT_SHIFT (6U)
4152/*! SIGN_OUT - Output Data Sign
4153 * 0b0..Signed Format
4154 * 0b1..Convert to Unsigned
4155 */
4156#define ASRC_CTX_OUT_CTRL_SIGN_OUT(x) \
4157 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_SIGN_OUT_SHIFT)) & ASRC_CTX_OUT_CTRL_SIGN_OUT_MASK)
4158#define ASRC_CTX_OUT_CTRL_FLOAT_FMT_MASK (0x80U)
4159#define ASRC_CTX_OUT_CTRL_FLOAT_FMT_SHIFT (7U)
4160/*! FLOAT_FMT - Context Output Floating Point Format
4161 * 0b0..Integer Format
4162 * 0b1..Single Precision Floating Point Format
4163 */
4164#define ASRC_CTX_OUT_CTRL_FLOAT_FMT(x) \
4165 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_FLOAT_FMT_SHIFT)) & ASRC_CTX_OUT_CTRL_FLOAT_FMT_MASK)
4166#define ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_MASK (0x300U)
4167#define ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_SHIFT (8U)
4168/*! BITS_PER_SAMPLE - Number of Bits Per Audio Sample
4169 * 0b00..16-bits Per Sample
4170 * 0b01..20-bits Per Sample
4171 * 0b10..24-bits Per Sample
4172 * 0b11..32-bits Per Sample
4173 */
4174#define ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE(x) \
4175 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_SHIFT)) & ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_MASK)
4176#define ASRC_CTX_OUT_CTRL_BIT_REV_MASK (0x400U)
4177#define ASRC_CTX_OUT_CTRL_BIT_REV_SHIFT (10U)
4178/*! BIT_REV - Sample Bit-Reversal
4179 * 0b0..No change.
4180 * 0b1..Bit-reverse sample data.
4181 */
4182#define ASRC_CTX_OUT_CTRL_BIT_REV(x) \
4183 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_BIT_REV_SHIFT)) & ASRC_CTX_OUT_CTRL_BIT_REV_MASK)
4184#define ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_MASK (0xF800U)
4185#define ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_SHIFT (11U)
4186#define ASRC_CTX_OUT_CTRL_SAMPLE_POSITION(x) \
4187 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_SHIFT)) & ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_MASK)
4188#define ASRC_CTX_OUT_CTRL_FIFO_WTMK_MASK (0x7F0000U)
4189#define ASRC_CTX_OUT_CTRL_FIFO_WTMK_SHIFT (16U)
4190#define ASRC_CTX_OUT_CTRL_FIFO_WTMK(x) \
4191 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_FIFO_WTMK_SHIFT)) & ASRC_CTX_OUT_CTRL_FIFO_WTMK_MASK)
4192#define ASRC_CTX_OUT_CTRL_FWMDE_MASK (0x10000000U)
4193#define ASRC_CTX_OUT_CTRL_FWMDE_SHIFT (28U)
4194/*! FWMDE - Output FIFO Watermark DMA Enable
4195 * 0b0..Output DMA Requests Not Enabled for This Context
4196 * 0b1..Output DMA Requests Enabled for This Context
4197 */
4198#define ASRC_CTX_OUT_CTRL_FWMDE(x) \
4199 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_FWMDE_SHIFT)) & ASRC_CTX_OUT_CTRL_FWMDE_MASK)
4200/*! @} */
4201
4202/* The count of ASRC_CTX_OUT_CTRL */
4203#define ASRC_CTX_OUT_CTRL_COUNT (4U)
4204
4205/*! @name CTRL_OUT_ACCESS - ASRC Control Output Access */
4206/*! @{ */
4207#define ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_MASK (0x3FU)
4208#define ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_SHIFT (0U)
4209#define ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH(x) \
4210 (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_SHIFT)) & \
4211 ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_MASK)
4212#define ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_MASK (0x3F00U)
4213#define ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_SHIFT (8U)
4214#define ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH(x) \
4215 (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_SHIFT)) & ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_MASK)
4216#define ASRC_CTRL_OUT_ACCESS_ITERATIONS_MASK (0x3F0000U)
4217#define ASRC_CTRL_OUT_ACCESS_ITERATIONS_SHIFT (16U)
4218#define ASRC_CTRL_OUT_ACCESS_ITERATIONS(x) \
4219 (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_OUT_ACCESS_ITERATIONS_SHIFT)) & ASRC_CTRL_OUT_ACCESS_ITERATIONS_MASK)
4220/*! @} */
4221
4222/* The count of ASRC_CTRL_OUT_ACCESS */
4223#define ASRC_CTRL_OUT_ACCESS_COUNT (4U)
4224
4225/*! @name SAMPLE_FIFO_STATUS - ASRC Sample FIFO Status */
4226/*! @{ */
4227#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_MASK (0x7FU)
4228#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_SHIFT (0U)
4229#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT(x) \
4230 (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_SHIFT)) & \
4231 ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_MASK)
4232#define ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_MASK (0x80U)
4233#define ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_SHIFT (7U)
4234#define ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK(x) \
4235 (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_SHIFT)) & \
4236 ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_MASK)
4237#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_MASK (0x7F0000U)
4238#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_SHIFT (16U)
4239#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN(x) \
4240 (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_SHIFT)) & \
4241 ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_MASK)
4242#define ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_MASK (0x800000U)
4243#define ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_SHIFT (23U)
4244#define ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK(x) \
4245 (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_SHIFT)) & \
4246 ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_MASK)
4247/*! @} */
4248
4249/* The count of ASRC_SAMPLE_FIFO_STATUS */
4250#define ASRC_SAMPLE_FIFO_STATUS_COUNT (4U)
4251
4252/*! @name RS_RATIO_LOW - ASRC Resampling Ratio Low */
4253/*! @{ */
4254#define ASRC_RS_RATIO_LOW_RS_RATIO_LOW_MASK (0xFFFFFFFFU)
4255#define ASRC_RS_RATIO_LOW_RS_RATIO_LOW_SHIFT (0U)
4256#define ASRC_RS_RATIO_LOW_RS_RATIO_LOW(x) \
4257 (((uint32_t)(((uint32_t)(x)) << ASRC_RS_RATIO_LOW_RS_RATIO_LOW_SHIFT)) & ASRC_RS_RATIO_LOW_RS_RATIO_LOW_MASK)
4258/*! @} */
4259
4260/* The count of ASRC_RS_RATIO_LOW */
4261#define ASRC_RS_RATIO_LOW_COUNT (4U)
4262
4263/*! @name RS_RATIO_HIGH - ASRC Resampling Ratio High */
4264/*! @{ */
4265#define ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_MASK (0xFFFU)
4266#define ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_SHIFT (0U)
4267#define ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH(x) \
4268 (((uint32_t)(((uint32_t)(x)) << ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_SHIFT)) & ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_MASK)
4269#define ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_MASK (0x80000000U)
4270#define ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_SHIFT (31U)
4271#define ASRC_RS_RATIO_HIGH_RS_RATIO_VLD(x) \
4272 (((uint32_t)(((uint32_t)(x)) << ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_SHIFT)) & ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_MASK)
4273/*! @} */
4274
4275/* The count of ASRC_RS_RATIO_HIGH */
4276#define ASRC_RS_RATIO_HIGH_COUNT (4U)
4277
4278/*! @name RS_UPDATE_CTRL - ASRC Resampling Ratio Update Control */
4279/*! @{ */
4280#define ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_MASK (0xFFFFFFFFU)
4281#define ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_SHIFT (0U)
4282#define ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD(x) \
4283 (((uint32_t)(((uint32_t)(x)) << ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_SHIFT)) & ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_MASK)
4284/*! @} */
4285
4286/* The count of ASRC_RS_UPDATE_CTRL */
4287#define ASRC_RS_UPDATE_CTRL_COUNT (4U)
4288
4289/*! @name RS_UPDATE_RATE - ASRC Resampling Ratio Update Rate */
4290/*! @{ */
4291#define ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_MASK (0x7FFFFFFFU)
4292#define ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_SHIFT (0U)
4293#define ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE(x) \
4294 (((uint32_t)(((uint32_t)(x)) << ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_SHIFT)) & \
4295 ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_MASK)
4296/*! @} */
4297
4298/* The count of ASRC_RS_UPDATE_RATE */
4299#define ASRC_RS_UPDATE_RATE_COUNT (4U)
4300
4301/*! @name RS_CT_LOW - ASRC Resampling Center Tap Coefficient Low */
4302/*! @{ */
4303#define ASRC_RS_CT_LOW_RS_CT_LOW_MASK (0xFFFFFFFFU)
4304#define ASRC_RS_CT_LOW_RS_CT_LOW_SHIFT (0U)
4305#define ASRC_RS_CT_LOW_RS_CT_LOW(x) \
4306 (((uint32_t)(((uint32_t)(x)) << ASRC_RS_CT_LOW_RS_CT_LOW_SHIFT)) & ASRC_RS_CT_LOW_RS_CT_LOW_MASK)
4307/*! @} */
4308
4309/*! @name RS_CT_HIGH - ASRC Resampling Center Tap Coefficient High */
4310/*! @{ */
4311#define ASRC_RS_CT_HIGH_RS_CT_HIGH_MASK (0xFFFFFFFFU)
4312#define ASRC_RS_CT_HIGH_RS_CT_HIGH_SHIFT (0U)
4313#define ASRC_RS_CT_HIGH_RS_CT_HIGH(x) \
4314 (((uint32_t)(((uint32_t)(x)) << ASRC_RS_CT_HIGH_RS_CT_HIGH_SHIFT)) & ASRC_RS_CT_HIGH_RS_CT_HIGH_MASK)
4315/*! @} */
4316
4317/*! @name PRE_COEFF_FIFO - ASRC Prefilter Coefficient FIFO */
4318/*! @{ */
4319#define ASRC_PRE_COEFF_FIFO_COEFF_DATA_MASK (0xFFFFFFFFU)
4320#define ASRC_PRE_COEFF_FIFO_COEFF_DATA_SHIFT (0U)
4321#define ASRC_PRE_COEFF_FIFO_COEFF_DATA(x) \
4322 (((uint32_t)(((uint32_t)(x)) << ASRC_PRE_COEFF_FIFO_COEFF_DATA_SHIFT)) & ASRC_PRE_COEFF_FIFO_COEFF_DATA_MASK)
4323/*! @} */
4324
4325/* The count of ASRC_PRE_COEFF_FIFO */
4326#define ASRC_PRE_COEFF_FIFO_COUNT (4U)
4327
4328/*! @name CTX_RS_COEFF_MEM - ASRC Context Resampling Coefficient Memory */
4329/*! @{ */
4330#define ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_MASK (0xFFFFFFFFU)
4331#define ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_SHIFT (0U)
4332#define ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA(x) \
4333 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_SHIFT)) & \
4334 ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_MASK)
4335/*! @} */
4336
4337/*! @name CTX_RS_COEFF_CTRL - ASRC Context Resampling Coefficient Control */
4338/*! @{ */
4339#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_MASK (0x1U)
4340#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_SHIFT (0U)
4341#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST(x) \
4342 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_SHIFT)) & \
4343 ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_MASK)
4344#define ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_MASK (0x6U)
4345#define ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_SHIFT (1U)
4346/*! NUM_RES_TAPS - Number of Resampling Coefficient Taps
4347 * 0b00..32-Tap Resampling Filter
4348 * 0b01..64-Tap Resampling Filter
4349 * 0b10..128-Tap Resampling Filter
4350 * 0b11..N/A
4351 */
4352#define ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS(x) \
4353 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_SHIFT)) & \
4354 ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_MASK)
4355#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_MASK (0x7FF0000U)
4356#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_SHIFT (16U)
4357#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR(x) \
4358 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_SHIFT)) & \
4359 ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_MASK)
4360/*! @} */
4361
4362/*! @name IRQ_CTRL - ASRC Interrupt Control */
4363/*! @{ */
4364#define ASRC_IRQ_CTRL_INFIFO_OVF_MASK_MASK (0xFU)
4365#define ASRC_IRQ_CTRL_INFIFO_OVF_MASK_SHIFT (0U)
4366/*! INFIFO_OVF_MASK - ASRC Input FIFO Overflow Mask
4367 * 0b0000..The INFIFO_OVF interrupt is enabled for Context 0 to 3.
4368 * 0b0001..The INFIFO_OVF interrupt is disabled for Context 0 and enabled for Context 1 to 3.
4369 * 0b0010..The INFIFO_OVF interrupt is disabled for Context 1 and enabled for Context 0, 2, and 3.
4370 * 0b0011-0b1110..The INFIFO_OVF interrupt is enabled for any context with a 1'b0 bit field.
4371 * 0b1111..The INFIFO_OVF interrupt is disabled for Context 0 to 3.
4372 */
4373#define ASRC_IRQ_CTRL_INFIFO_OVF_MASK(x) \
4374 (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_CTRL_INFIFO_OVF_MASK_SHIFT)) & ASRC_IRQ_CTRL_INFIFO_OVF_MASK_MASK)
4375#define ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_MASK (0xF0U)
4376#define ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_SHIFT (4U)
4377/*! OUTFIFO_EMPTY_RD_MASK - ASRC Output FIFO Empty Read Mask
4378 * 0b0000..The OUTFIFO_EMPTY_RD interrupt is enabled for Context 0 to 3.
4379 * 0b0001..The OUTFIFO_EMPTY_RD interrupt is disabled for Context 0 and enabled for Context 1 to 3.
4380 * 0b0010..The OUTFIFO_EMPTY_RD interrupt is disabled for Context 1 and enabled for Context 0, 2, and 3.
4381 * 0b0011-0b1110..The OUTFIFO_EMPTY_RD interrupt is enabled for any context with a 1'b0 bit field.
4382 * 0b1111..The OUTFIFO_EMPTY_RD interrupt is disabled for Context 0 to 3.
4383 */
4384#define ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK(x) \
4385 (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_SHIFT)) & \
4386 ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_MASK)
4387#define ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_MASK (0xF00U)
4388#define ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_SHIFT (8U)
4389/*! RUN_STOP_DONE_MASK - ASRC RUN STOP DONE MASK
4390 * 0b0000..The RUN_STOP_DONE interrupt is enabled for Context 0 to 3.
4391 * 0b0001..The RUN_STOP_DONE interrupt is disabled for Context 0 and enabled for Context 1 to 3.
4392 * 0b0010..The RUN_STOP_DONE interrupt is disabled for Context 1 and enabled for Context 0, 2, and 3.
4393 * 0b0011-0b1110..The RUN_STOP_DONE interrupt is enabled for any context with a 1'b0 bit field.
4394 * 0b1111..The RUN_STOP_DONE interrupt is disabled for Context 0 to 3.
4395 */
4396#define ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK(x) \
4397 (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_SHIFT)) & ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_MASK)
4398/*! @} */
4399
4400/*! @name IRQ_FLAGS - ASRC Interrupt Status Flags */
4401/*! @{ */
4402#define ASRC_IRQ_FLAGS_INFIFO_OVF_MASK (0xFU)
4403#define ASRC_IRQ_FLAGS_INFIFO_OVF_SHIFT (0U)
4404/*! INFIFO_OVF - ASRC Input FIFO Overflow Flag
4405 * 0b0000..No INFIFO_OVF errors have been recorded.
4406 * 0b0001..The ASRC_WRFIFO0 has overflown.
4407 * 0b0010..The ASRC_WRFIFO1 has overflown.
4408 * 0b0011-0b1110..The ASRC_WRFIFOn has overflown. Where n = any bit position set to 0b1.
4409 * 0b1111..ASRC_WRFIFO0, ASRC_WRFIFO1, ASRC_WRFIFO2, and ASRC_WRFIFO3 have overflown.
4410 */
4411#define ASRC_IRQ_FLAGS_INFIFO_OVF(x) \
4412 (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_FLAGS_INFIFO_OVF_SHIFT)) & ASRC_IRQ_FLAGS_INFIFO_OVF_MASK)
4413#define ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD_MASK (0xF0U)
4414#define ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD_SHIFT (4U)
4415/*! OUTFIFO_EMPTY_RD - ASRC Output FIFO Empty Read Flag
4416 * 0b0000..No reads have been requested from an empty ASRC_RDFIFO.
4417 * 0b0001..A read has been requested from ASRC_RDFIFO0 when it was empty.
4418 * 0b0010..A read has been requested from ASRC_RDFIFO1 when it was empty.
4419 * 0b0011-0b1110..A read has been requested from ASRC_RDFIFOn when it was empty. n = any bit position with a 0b1.
4420 * 0b1111..A read has been requested from ASRC_RDFIFO0, ASRC_RDFIFO1, ASRC_RDFIFO2, and ASRC_RDFIFO3 while empty.
4421 */
4422#define ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD(x) \
4423 (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD_SHIFT)) & ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD_MASK)
4424#define ASRC_IRQ_FLAGS_RUN_STOP_DONE_MASK (0xF00U)
4425#define ASRC_IRQ_FLAGS_RUN_STOP_DONE_SHIFT (8U)
4426/*! RUN_STOP_DONE - ASRC RUN STOP DONE FLAG
4427 * 0b0000..No RUN_STOP operations have been completed.
4428 * 0b0001..The RUN_STOP operation for Context 0 has completed.
4429 * 0b0010..The RUN_STOP operation for Context 1 has completed.
4430 * 0b0011-0b1110..The RUN_STOP operation has completed for any context with a 1'b1 bit field.
4431 * 0b1111..The RUN_STOP operation has completed for Context 0 to 3.
4432 */
4433#define ASRC_IRQ_FLAGS_RUN_STOP_DONE(x) \
4434 (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_FLAGS_RUN_STOP_DONE_SHIFT)) & ASRC_IRQ_FLAGS_RUN_STOP_DONE_MASK)
4435/*! @} */
4436
4437/*! @name CHANNEL_STATUS_0 - ASRC Channel Status 0 */
4438/*! @{ */
4439#define ASRC_CHANNEL_STATUS_0_CHN_STAT_MASK (0xFFFFFFFFU)
4440#define ASRC_CHANNEL_STATUS_0_CHN_STAT_SHIFT (0U)
4441#define ASRC_CHANNEL_STATUS_0_CHN_STAT(x) \
4442 (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_0_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_0_CHN_STAT_MASK)
4443/*! @} */
4444
4445/* The count of ASRC_CHANNEL_STATUS_0 */
4446#define ASRC_CHANNEL_STATUS_0_COUNT (4U)
4447
4448/*! @name CHANNEL_STATUS_1 - ASRC Channel Status 1 */
4449/*! @{ */
4450#define ASRC_CHANNEL_STATUS_1_CHN_STAT_MASK (0xFFFFFFFFU)
4451#define ASRC_CHANNEL_STATUS_1_CHN_STAT_SHIFT (0U)
4452#define ASRC_CHANNEL_STATUS_1_CHN_STAT(x) \
4453 (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_1_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_1_CHN_STAT_MASK)
4454/*! @} */
4455
4456/* The count of ASRC_CHANNEL_STATUS_1 */
4457#define ASRC_CHANNEL_STATUS_1_COUNT (4U)
4458
4459/*! @name CHANNEL_STATUS_2 - ASRC Channel Status 2 */
4460/*! @{ */
4461#define ASRC_CHANNEL_STATUS_2_CHN_STAT_MASK (0xFFFFFFFFU)
4462#define ASRC_CHANNEL_STATUS_2_CHN_STAT_SHIFT (0U)
4463#define ASRC_CHANNEL_STATUS_2_CHN_STAT(x) \
4464 (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_2_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_2_CHN_STAT_MASK)
4465/*! @} */
4466
4467/* The count of ASRC_CHANNEL_STATUS_2 */
4468#define ASRC_CHANNEL_STATUS_2_COUNT (4U)
4469
4470/*! @name CHANNEL_STATUS_3 - ASRC Channel Status 3 */
4471/*! @{ */
4472#define ASRC_CHANNEL_STATUS_3_CHN_STAT_MASK (0xFFFFFFFFU)
4473#define ASRC_CHANNEL_STATUS_3_CHN_STAT_SHIFT (0U)
4474#define ASRC_CHANNEL_STATUS_3_CHN_STAT(x) \
4475 (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_3_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_3_CHN_STAT_MASK)
4476/*! @} */
4477
4478/* The count of ASRC_CHANNEL_STATUS_3 */
4479#define ASRC_CHANNEL_STATUS_3_COUNT (4U)
4480
4481/*! @name CHANNEL_STATUS_4 - ASRC Channel Status 4 */
4482/*! @{ */
4483#define ASRC_CHANNEL_STATUS_4_CHN_STAT_MASK (0xFFFFFFFFU)
4484#define ASRC_CHANNEL_STATUS_4_CHN_STAT_SHIFT (0U)
4485#define ASRC_CHANNEL_STATUS_4_CHN_STAT(x) \
4486 (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_4_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_4_CHN_STAT_MASK)
4487/*! @} */
4488
4489/* The count of ASRC_CHANNEL_STATUS_4 */
4490#define ASRC_CHANNEL_STATUS_4_COUNT (4U)
4491
4492/*! @name CHANNEL_STATUS_5 - ASRC Channel Status 5 */
4493/*! @{ */
4494#define ASRC_CHANNEL_STATUS_5_CHN_STAT_MASK (0xFFFFFFFFU)
4495#define ASRC_CHANNEL_STATUS_5_CHN_STAT_SHIFT (0U)
4496#define ASRC_CHANNEL_STATUS_5_CHN_STAT(x) \
4497 (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_5_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_5_CHN_STAT_MASK)
4498/*! @} */
4499
4500/* The count of ASRC_CHANNEL_STATUS_5 */
4501#define ASRC_CHANNEL_STATUS_5_COUNT (4U)
4502
4503/*!
4504 * @}
4505 */ /* end of group ASRC_Register_Masks */
4506
4507/* ASRC - Peripheral instance base addresses */
4508/** Peripheral ASRC base address */
4509#define ASRC_BASE (0x300C0000u)
4510/** Peripheral ASRC base pointer */
4511#define ASRC ((ASRC_Type *)ASRC_BASE)
4512/** Array initializer of ASRC peripheral base addresses */
4513#define ASRC_BASE_ADDRS \
4514 { \
4515 ASRC_BASE \
4516 }
4517/** Array initializer of ASRC peripheral base pointers */
4518#define ASRC_BASE_PTRS \
4519 { \
4520 ASRC \
4521 }
4522
4523/*!
4524 * @}
4525 */ /* end of group ASRC_Peripheral_Access_Layer */
4526
4527/* ----------------------------------------------------------------------------
4528 -- BCH Peripheral Access Layer
4529 ---------------------------------------------------------------------------- */
4530
4531/*!
4532 * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer
4533 * @{
4534 */
4535
4536/** BCH - Register Layout Typedef */
4537typedef struct
4538{
4539 __IO uint32_t CTRL; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */
4540 __IO uint32_t CTRL_SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */
4541 __IO uint32_t CTRL_CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */
4542 __IO uint32_t CTRL_TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */
4543 __I uint32_t STATUS0; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */
4544 uint8_t RESERVED_0[12];
4545 __IO uint32_t MODE; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */
4546 uint8_t RESERVED_1[12];
4547 __IO uint32_t ENCODEPTR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */
4548 uint8_t RESERVED_2[12];
4549 __IO uint32_t DATAPTR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */
4550 uint8_t RESERVED_3[12];
4551 __IO uint32_t METAPTR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */
4552 uint8_t RESERVED_4[28];
4553 __IO uint32_t LAYOUTSELECT; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */
4554 uint8_t RESERVED_5[12];
4555 __IO uint32_t FLASH0LAYOUT0; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */
4556 uint8_t RESERVED_6[12];
4557 __IO uint32_t FLASH0LAYOUT1; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */
4558 uint8_t RESERVED_7[12];
4559 __IO uint32_t FLASH1LAYOUT0; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */
4560 uint8_t RESERVED_8[12];
4561 __IO uint32_t FLASH1LAYOUT1; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */
4562 uint8_t RESERVED_9[12];
4563 __IO uint32_t FLASH2LAYOUT0; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */
4564 uint8_t RESERVED_10[12];
4565 __IO uint32_t FLASH2LAYOUT1; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */
4566 uint8_t RESERVED_11[12];
4567 __IO uint32_t FLASH3LAYOUT0; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */
4568 uint8_t RESERVED_12[12];
4569 __IO uint32_t FLASH3LAYOUT1; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */
4570 uint8_t RESERVED_13[12];
4571 __IO uint32_t DEBUG0; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */
4572 __IO uint32_t DEBUG0_SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */
4573 __IO uint32_t DEBUG0_CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */
4574 __IO uint32_t DEBUG0_TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */
4575 __I uint32_t DBGKESREAD; /**< KES Debug Read Register, offset: 0x110 */
4576 uint8_t RESERVED_14[12];
4577 __I uint32_t DBGCSFEREAD; /**< Chien Search Debug Read Register, offset: 0x120 */
4578 uint8_t RESERVED_15[12];
4579 __I uint32_t DBGSYNDGENREAD; /**< Syndrome Generator Debug Read Register, offset: 0x130 */
4580 uint8_t RESERVED_16[12];
4581 __I uint32_t DBGAHBMREAD; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */
4582 uint8_t RESERVED_17[12];
4583 __I uint32_t BLOCKNAME; /**< Block Name Register, offset: 0x150 */
4584 uint8_t RESERVED_18[12];
4585 __I uint32_t VERSION; /**< BCH Version Register, offset: 0x160 */
4586 uint8_t RESERVED_19[12];
4587 __IO uint32_t DEBUG1; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */
4588} BCH_Type;
4589
4590/* ----------------------------------------------------------------------------
4591 -- BCH Register Masks
4592 ---------------------------------------------------------------------------- */
4593
4594/*!
4595 * @addtogroup BCH_Register_Masks BCH Register Masks
4596 * @{
4597 */
4598
4599/*! @name CTRL - Hardware BCH ECC Accelerator Control Register */
4600/*! @{ */
4601#define BCH_CTRL_COMPLETE_IRQ_MASK (0x1U)
4602#define BCH_CTRL_COMPLETE_IRQ_SHIFT (0U)
4603#define BCH_CTRL_COMPLETE_IRQ(x) \
4604 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK)
4605#define BCH_CTRL_RSVD0_MASK (0x2U)
4606#define BCH_CTRL_RSVD0_SHIFT (1U)
4607#define BCH_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK)
4608#define BCH_CTRL_DEBUG_STALL_IRQ_MASK (0x4U)
4609#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT (2U)
4610#define BCH_CTRL_DEBUG_STALL_IRQ(x) \
4611 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK)
4612#define BCH_CTRL_BM_ERROR_IRQ_MASK (0x8U)
4613#define BCH_CTRL_BM_ERROR_IRQ_SHIFT (3U)
4614#define BCH_CTRL_BM_ERROR_IRQ(x) \
4615 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK)
4616#define BCH_CTRL_RSVD1_MASK (0xF0U)
4617#define BCH_CTRL_RSVD1_SHIFT (4U)
4618#define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK)
4619#define BCH_CTRL_COMPLETE_IRQ_EN_MASK (0x100U)
4620#define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT (8U)
4621#define BCH_CTRL_COMPLETE_IRQ_EN(x) \
4622 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK)
4623#define BCH_CTRL_RSVD2_MASK (0x200U)
4624#define BCH_CTRL_RSVD2_SHIFT (9U)
4625#define BCH_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK)
4626#define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK (0x400U)
4627#define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT (10U)
4628#define BCH_CTRL_DEBUG_STALL_IRQ_EN(x) \
4629 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK)
4630#define BCH_CTRL_RSVD3_MASK (0xF800U)
4631#define BCH_CTRL_RSVD3_SHIFT (11U)
4632#define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK)
4633#define BCH_CTRL_M2M_ENABLE_MASK (0x10000U)
4634#define BCH_CTRL_M2M_ENABLE_SHIFT (16U)
4635#define BCH_CTRL_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK)
4636#define BCH_CTRL_M2M_ENCODE_MASK (0x20000U)
4637#define BCH_CTRL_M2M_ENCODE_SHIFT (17U)
4638#define BCH_CTRL_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK)
4639#define BCH_CTRL_M2M_LAYOUT_MASK (0xC0000U)
4640#define BCH_CTRL_M2M_LAYOUT_SHIFT (18U)
4641#define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK)
4642#define BCH_CTRL_RSVD4_MASK (0x300000U)
4643#define BCH_CTRL_RSVD4_SHIFT (20U)
4644#define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK)
4645#define BCH_CTRL_DEBUGSYNDROME_MASK (0x400000U)
4646#define BCH_CTRL_DEBUGSYNDROME_SHIFT (22U)
4647#define BCH_CTRL_DEBUGSYNDROME(x) \
4648 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK)
4649#define BCH_CTRL_RSVD5_MASK (0x3F800000U)
4650#define BCH_CTRL_RSVD5_SHIFT (23U)
4651#define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK)
4652#define BCH_CTRL_CLKGATE_MASK (0x40000000U)
4653#define BCH_CTRL_CLKGATE_SHIFT (30U)
4654/*! CLKGATE
4655 * 0b0..Allow BCH to operate normally.
4656 * 0b1..Do not clock BCH gates in order to minimize power consumption.
4657 */
4658#define BCH_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK)
4659#define BCH_CTRL_SFTRST_MASK (0x80000000U)
4660#define BCH_CTRL_SFTRST_SHIFT (31U)
4661/*! SFTRST
4662 * 0b0..Allow BCH to operate normally.
4663 * 0b1..Hold BCH in reset.
4664 */
4665#define BCH_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK)
4666/*! @} */
4667
4668/*! @name CTRL_SET - Hardware BCH ECC Accelerator Control Register */
4669/*! @{ */
4670#define BCH_CTRL_SET_COMPLETE_IRQ_MASK (0x1U)
4671#define BCH_CTRL_SET_COMPLETE_IRQ_SHIFT (0U)
4672#define BCH_CTRL_SET_COMPLETE_IRQ(x) \
4673 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_MASK)
4674#define BCH_CTRL_SET_RSVD0_MASK (0x2U)
4675#define BCH_CTRL_SET_RSVD0_SHIFT (1U)
4676#define BCH_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD0_SHIFT)) & BCH_CTRL_SET_RSVD0_MASK)
4677#define BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK (0x4U)
4678#define BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT (2U)
4679#define BCH_CTRL_SET_DEBUG_STALL_IRQ(x) \
4680 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK)
4681#define BCH_CTRL_SET_BM_ERROR_IRQ_MASK (0x8U)
4682#define BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT (3U)
4683#define BCH_CTRL_SET_BM_ERROR_IRQ(x) \
4684 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_SET_BM_ERROR_IRQ_MASK)
4685#define BCH_CTRL_SET_RSVD1_MASK (0xF0U)
4686#define BCH_CTRL_SET_RSVD1_SHIFT (4U)
4687#define BCH_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD1_SHIFT)) & BCH_CTRL_SET_RSVD1_MASK)
4688#define BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK (0x100U)
4689#define BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT (8U)
4690#define BCH_CTRL_SET_COMPLETE_IRQ_EN(x) \
4691 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK)
4692#define BCH_CTRL_SET_RSVD2_MASK (0x200U)
4693#define BCH_CTRL_SET_RSVD2_SHIFT (9U)
4694#define BCH_CTRL_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD2_SHIFT)) & BCH_CTRL_SET_RSVD2_MASK)
4695#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK (0x400U)
4696#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT (10U)
4697#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN(x) \
4698 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK)
4699#define BCH_CTRL_SET_RSVD3_MASK (0xF800U)
4700#define BCH_CTRL_SET_RSVD3_SHIFT (11U)
4701#define BCH_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD3_SHIFT)) & BCH_CTRL_SET_RSVD3_MASK)
4702#define BCH_CTRL_SET_M2M_ENABLE_MASK (0x10000U)
4703#define BCH_CTRL_SET_M2M_ENABLE_SHIFT (16U)
4704#define BCH_CTRL_SET_M2M_ENABLE(x) \
4705 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENABLE_SHIFT)) & BCH_CTRL_SET_M2M_ENABLE_MASK)
4706#define BCH_CTRL_SET_M2M_ENCODE_MASK (0x20000U)
4707#define BCH_CTRL_SET_M2M_ENCODE_SHIFT (17U)
4708#define BCH_CTRL_SET_M2M_ENCODE(x) \
4709 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENCODE_SHIFT)) & BCH_CTRL_SET_M2M_ENCODE_MASK)
4710#define BCH_CTRL_SET_M2M_LAYOUT_MASK (0xC0000U)
4711#define BCH_CTRL_SET_M2M_LAYOUT_SHIFT (18U)
4712#define BCH_CTRL_SET_M2M_LAYOUT(x) \
4713 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_LAYOUT_SHIFT)) & BCH_CTRL_SET_M2M_LAYOUT_MASK)
4714#define BCH_CTRL_SET_RSVD4_MASK (0x300000U)
4715#define BCH_CTRL_SET_RSVD4_SHIFT (20U)
4716#define BCH_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD4_SHIFT)) & BCH_CTRL_SET_RSVD4_MASK)
4717#define BCH_CTRL_SET_DEBUGSYNDROME_MASK (0x400000U)
4718#define BCH_CTRL_SET_DEBUGSYNDROME_SHIFT (22U)
4719#define BCH_CTRL_SET_DEBUGSYNDROME(x) \
4720 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_SET_DEBUGSYNDROME_MASK)
4721#define BCH_CTRL_SET_RSVD5_MASK (0x3F800000U)
4722#define BCH_CTRL_SET_RSVD5_SHIFT (23U)
4723#define BCH_CTRL_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD5_SHIFT)) & BCH_CTRL_SET_RSVD5_MASK)
4724#define BCH_CTRL_SET_CLKGATE_MASK (0x40000000U)
4725#define BCH_CTRL_SET_CLKGATE_SHIFT (30U)
4726/*! CLKGATE
4727 * 0b0..Allow BCH to operate normally.
4728 * 0b1..Do not clock BCH gates in order to minimize power consumption.
4729 */
4730#define BCH_CTRL_SET_CLKGATE(x) \
4731 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_CLKGATE_SHIFT)) & BCH_CTRL_SET_CLKGATE_MASK)
4732#define BCH_CTRL_SET_SFTRST_MASK (0x80000000U)
4733#define BCH_CTRL_SET_SFTRST_SHIFT (31U)
4734/*! SFTRST
4735 * 0b0..Allow BCH to operate normally.
4736 * 0b1..Hold BCH in reset.
4737 */
4738#define BCH_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_SFTRST_SHIFT)) & BCH_CTRL_SET_SFTRST_MASK)
4739/*! @} */
4740
4741/*! @name CTRL_CLR - Hardware BCH ECC Accelerator Control Register */
4742/*! @{ */
4743#define BCH_CTRL_CLR_COMPLETE_IRQ_MASK (0x1U)
4744#define BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT (0U)
4745#define BCH_CTRL_CLR_COMPLETE_IRQ(x) \
4746 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_MASK)
4747#define BCH_CTRL_CLR_RSVD0_MASK (0x2U)
4748#define BCH_CTRL_CLR_RSVD0_SHIFT (1U)
4749#define BCH_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD0_SHIFT)) & BCH_CTRL_CLR_RSVD0_MASK)
4750#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK (0x4U)
4751#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT (2U)
4752#define BCH_CTRL_CLR_DEBUG_STALL_IRQ(x) \
4753 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK)
4754#define BCH_CTRL_CLR_BM_ERROR_IRQ_MASK (0x8U)
4755#define BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT (3U)
4756#define BCH_CTRL_CLR_BM_ERROR_IRQ(x) \
4757 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_CLR_BM_ERROR_IRQ_MASK)
4758#define BCH_CTRL_CLR_RSVD1_MASK (0xF0U)
4759#define BCH_CTRL_CLR_RSVD1_SHIFT (4U)
4760#define BCH_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD1_SHIFT)) & BCH_CTRL_CLR_RSVD1_MASK)
4761#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK (0x100U)
4762#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT (8U)
4763#define BCH_CTRL_CLR_COMPLETE_IRQ_EN(x) \
4764 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK)
4765#define BCH_CTRL_CLR_RSVD2_MASK (0x200U)
4766#define BCH_CTRL_CLR_RSVD2_SHIFT (9U)
4767#define BCH_CTRL_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD2_SHIFT)) & BCH_CTRL_CLR_RSVD2_MASK)
4768#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK (0x400U)
4769#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT (10U)
4770#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN(x) \
4771 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK)
4772#define BCH_CTRL_CLR_RSVD3_MASK (0xF800U)
4773#define BCH_CTRL_CLR_RSVD3_SHIFT (11U)
4774#define BCH_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD3_SHIFT)) & BCH_CTRL_CLR_RSVD3_MASK)
4775#define BCH_CTRL_CLR_M2M_ENABLE_MASK (0x10000U)
4776#define BCH_CTRL_CLR_M2M_ENABLE_SHIFT (16U)
4777#define BCH_CTRL_CLR_M2M_ENABLE(x) \
4778 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENABLE_SHIFT)) & BCH_CTRL_CLR_M2M_ENABLE_MASK)
4779#define BCH_CTRL_CLR_M2M_ENCODE_MASK (0x20000U)
4780#define BCH_CTRL_CLR_M2M_ENCODE_SHIFT (17U)
4781#define BCH_CTRL_CLR_M2M_ENCODE(x) \
4782 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENCODE_SHIFT)) & BCH_CTRL_CLR_M2M_ENCODE_MASK)
4783#define BCH_CTRL_CLR_M2M_LAYOUT_MASK (0xC0000U)
4784#define BCH_CTRL_CLR_M2M_LAYOUT_SHIFT (18U)
4785#define BCH_CTRL_CLR_M2M_LAYOUT(x) \
4786 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_LAYOUT_SHIFT)) & BCH_CTRL_CLR_M2M_LAYOUT_MASK)
4787#define BCH_CTRL_CLR_RSVD4_MASK (0x300000U)
4788#define BCH_CTRL_CLR_RSVD4_SHIFT (20U)
4789#define BCH_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD4_SHIFT)) & BCH_CTRL_CLR_RSVD4_MASK)
4790#define BCH_CTRL_CLR_DEBUGSYNDROME_MASK (0x400000U)
4791#define BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT (22U)
4792#define BCH_CTRL_CLR_DEBUGSYNDROME(x) \
4793 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_CLR_DEBUGSYNDROME_MASK)
4794#define BCH_CTRL_CLR_RSVD5_MASK (0x3F800000U)
4795#define BCH_CTRL_CLR_RSVD5_SHIFT (23U)
4796#define BCH_CTRL_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD5_SHIFT)) & BCH_CTRL_CLR_RSVD5_MASK)
4797#define BCH_CTRL_CLR_CLKGATE_MASK (0x40000000U)
4798#define BCH_CTRL_CLR_CLKGATE_SHIFT (30U)
4799/*! CLKGATE
4800 * 0b0..Allow BCH to operate normally.
4801 * 0b1..Do not clock BCH gates in order to minimize power consumption.
4802 */
4803#define BCH_CTRL_CLR_CLKGATE(x) \
4804 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_CLKGATE_SHIFT)) & BCH_CTRL_CLR_CLKGATE_MASK)
4805#define BCH_CTRL_CLR_SFTRST_MASK (0x80000000U)
4806#define BCH_CTRL_CLR_SFTRST_SHIFT (31U)
4807/*! SFTRST
4808 * 0b0..Allow BCH to operate normally.
4809 * 0b1..Hold BCH in reset.
4810 */
4811#define BCH_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_SFTRST_SHIFT)) & BCH_CTRL_CLR_SFTRST_MASK)
4812/*! @} */
4813
4814/*! @name CTRL_TOG - Hardware BCH ECC Accelerator Control Register */
4815/*! @{ */
4816#define BCH_CTRL_TOG_COMPLETE_IRQ_MASK (0x1U)
4817#define BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT (0U)
4818#define BCH_CTRL_TOG_COMPLETE_IRQ(x) \
4819 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_MASK)
4820#define BCH_CTRL_TOG_RSVD0_MASK (0x2U)
4821#define BCH_CTRL_TOG_RSVD0_SHIFT (1U)
4822#define BCH_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD0_SHIFT)) & BCH_CTRL_TOG_RSVD0_MASK)
4823#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK (0x4U)
4824#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT (2U)
4825#define BCH_CTRL_TOG_DEBUG_STALL_IRQ(x) \
4826 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK)
4827#define BCH_CTRL_TOG_BM_ERROR_IRQ_MASK (0x8U)
4828#define BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT (3U)
4829#define BCH_CTRL_TOG_BM_ERROR_IRQ(x) \
4830 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_TOG_BM_ERROR_IRQ_MASK)
4831#define BCH_CTRL_TOG_RSVD1_MASK (0xF0U)
4832#define BCH_CTRL_TOG_RSVD1_SHIFT (4U)
4833#define BCH_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD1_SHIFT)) & BCH_CTRL_TOG_RSVD1_MASK)
4834#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK (0x100U)
4835#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT (8U)
4836#define BCH_CTRL_TOG_COMPLETE_IRQ_EN(x) \
4837 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK)
4838#define BCH_CTRL_TOG_RSVD2_MASK (0x200U)
4839#define BCH_CTRL_TOG_RSVD2_SHIFT (9U)
4840#define BCH_CTRL_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD2_SHIFT)) & BCH_CTRL_TOG_RSVD2_MASK)
4841#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK (0x400U)
4842#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT (10U)
4843#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN(x) \
4844 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK)
4845#define BCH_CTRL_TOG_RSVD3_MASK (0xF800U)
4846#define BCH_CTRL_TOG_RSVD3_SHIFT (11U)
4847#define BCH_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD3_SHIFT)) & BCH_CTRL_TOG_RSVD3_MASK)
4848#define BCH_CTRL_TOG_M2M_ENABLE_MASK (0x10000U)
4849#define BCH_CTRL_TOG_M2M_ENABLE_SHIFT (16U)
4850#define BCH_CTRL_TOG_M2M_ENABLE(x) \
4851 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENABLE_SHIFT)) & BCH_CTRL_TOG_M2M_ENABLE_MASK)
4852#define BCH_CTRL_TOG_M2M_ENCODE_MASK (0x20000U)
4853#define BCH_CTRL_TOG_M2M_ENCODE_SHIFT (17U)
4854#define BCH_CTRL_TOG_M2M_ENCODE(x) \
4855 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENCODE_SHIFT)) & BCH_CTRL_TOG_M2M_ENCODE_MASK)
4856#define BCH_CTRL_TOG_M2M_LAYOUT_MASK (0xC0000U)
4857#define BCH_CTRL_TOG_M2M_LAYOUT_SHIFT (18U)
4858#define BCH_CTRL_TOG_M2M_LAYOUT(x) \
4859 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_LAYOUT_SHIFT)) & BCH_CTRL_TOG_M2M_LAYOUT_MASK)
4860#define BCH_CTRL_TOG_RSVD4_MASK (0x300000U)
4861#define BCH_CTRL_TOG_RSVD4_SHIFT (20U)
4862#define BCH_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD4_SHIFT)) & BCH_CTRL_TOG_RSVD4_MASK)
4863#define BCH_CTRL_TOG_DEBUGSYNDROME_MASK (0x400000U)
4864#define BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT (22U)
4865#define BCH_CTRL_TOG_DEBUGSYNDROME(x) \
4866 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_TOG_DEBUGSYNDROME_MASK)
4867#define BCH_CTRL_TOG_RSVD5_MASK (0x3F800000U)
4868#define BCH_CTRL_TOG_RSVD5_SHIFT (23U)
4869#define BCH_CTRL_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD5_SHIFT)) & BCH_CTRL_TOG_RSVD5_MASK)
4870#define BCH_CTRL_TOG_CLKGATE_MASK (0x40000000U)
4871#define BCH_CTRL_TOG_CLKGATE_SHIFT (30U)
4872/*! CLKGATE
4873 * 0b0..Allow BCH to operate normally.
4874 * 0b1..Do not clock BCH gates in order to minimize power consumption.
4875 */
4876#define BCH_CTRL_TOG_CLKGATE(x) \
4877 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_CLKGATE_SHIFT)) & BCH_CTRL_TOG_CLKGATE_MASK)
4878#define BCH_CTRL_TOG_SFTRST_MASK (0x80000000U)
4879#define BCH_CTRL_TOG_SFTRST_SHIFT (31U)
4880/*! SFTRST
4881 * 0b0..Allow BCH to operate normally.
4882 * 0b1..Hold BCH in reset.
4883 */
4884#define BCH_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_SFTRST_SHIFT)) & BCH_CTRL_TOG_SFTRST_MASK)
4885/*! @} */
4886
4887/*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */
4888/*! @{ */
4889#define BCH_STATUS0_RSVD0_MASK (0x3U)
4890#define BCH_STATUS0_RSVD0_SHIFT (0U)
4891#define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK)
4892#define BCH_STATUS0_UNCORRECTABLE_MASK (0x4U)
4893#define BCH_STATUS0_UNCORRECTABLE_SHIFT (2U)
4894#define BCH_STATUS0_UNCORRECTABLE(x) \
4895 (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK)
4896#define BCH_STATUS0_CORRECTED_MASK (0x8U)
4897#define BCH_STATUS0_CORRECTED_SHIFT (3U)
4898#define BCH_STATUS0_CORRECTED(x) \
4899 (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK)
4900#define BCH_STATUS0_ALLONES_MASK (0x10U)
4901#define BCH_STATUS0_ALLONES_SHIFT (4U)
4902#define BCH_STATUS0_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK)
4903#define BCH_STATUS0_RSVD1_MASK (0xE0U)
4904#define BCH_STATUS0_RSVD1_SHIFT (5U)
4905#define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK)
4906#define BCH_STATUS0_STATUS_BLK0_MASK (0xFF00U)
4907#define BCH_STATUS0_STATUS_BLK0_SHIFT (8U)
4908/*! STATUS_BLK0
4909 * 0b00000000..No errors found on block.
4910 * 0b00000001..One error found on block.
4911 * 0b00000010..One errors found on block.
4912 * 0b00000011..One errors found on block.
4913 * 0b00000100..One errors found on block.
4914 * 0b11111110..Block exhibited uncorrectable errors.
4915 * 0b11111111..Page is erased.
4916 */
4917#define BCH_STATUS0_STATUS_BLK0(x) \
4918 (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK)
4919#define BCH_STATUS0_COMPLETED_CE_MASK (0xF0000U)
4920#define BCH_STATUS0_COMPLETED_CE_SHIFT (16U)
4921#define BCH_STATUS0_COMPLETED_CE(x) \
4922 (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK)
4923#define BCH_STATUS0_HANDLE_MASK (0xFFF00000U)
4924#define BCH_STATUS0_HANDLE_SHIFT (20U)
4925#define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK)
4926/*! @} */
4927
4928/*! @name MODE - Hardware ECC Accelerator Mode Register */
4929/*! @{ */
4930#define BCH_MODE_ERASE_THRESHOLD_MASK (0xFFU)
4931#define BCH_MODE_ERASE_THRESHOLD_SHIFT (0U)
4932#define BCH_MODE_ERASE_THRESHOLD(x) \
4933 (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK)
4934#define BCH_MODE_RSVD_MASK (0xFFFFFF00U)
4935#define BCH_MODE_RSVD_SHIFT (8U)
4936#define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK)
4937/*! @} */
4938
4939/*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */
4940/*! @{ */
4941#define BCH_ENCODEPTR_ADDR_MASK (0xFFFFFFFFU)
4942#define BCH_ENCODEPTR_ADDR_SHIFT (0U)
4943#define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK)
4944/*! @} */
4945
4946/*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */
4947/*! @{ */
4948#define BCH_DATAPTR_ADDR_MASK (0xFFFFFFFFU)
4949#define BCH_DATAPTR_ADDR_SHIFT (0U)
4950#define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK)
4951/*! @} */
4952
4953/*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */
4954/*! @{ */
4955#define BCH_METAPTR_ADDR_MASK (0xFFFFFFFFU)
4956#define BCH_METAPTR_ADDR_SHIFT (0U)
4957#define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK)
4958/*! @} */
4959
4960/*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */
4961/*! @{ */
4962#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3U)
4963#define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT (0U)
4964#define BCH_LAYOUTSELECT_CS0_SELECT(x) \
4965 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK)
4966#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0xCU)
4967#define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT (2U)
4968#define BCH_LAYOUTSELECT_CS1_SELECT(x) \
4969 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK)
4970#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x30U)
4971#define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT (4U)
4972#define BCH_LAYOUTSELECT_CS2_SELECT(x) \
4973 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK)
4974#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0xC0U)
4975#define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT (6U)
4976#define BCH_LAYOUTSELECT_CS3_SELECT(x) \
4977 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK)
4978#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x300U)
4979#define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT (8U)
4980#define BCH_LAYOUTSELECT_CS4_SELECT(x) \
4981 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK)
4982#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0xC00U)
4983#define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT (10U)
4984#define BCH_LAYOUTSELECT_CS5_SELECT(x) \
4985 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK)
4986#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3000U)
4987#define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT (12U)
4988#define BCH_LAYOUTSELECT_CS6_SELECT(x) \
4989 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK)
4990#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0xC000U)
4991#define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT (14U)
4992#define BCH_LAYOUTSELECT_CS7_SELECT(x) \
4993 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK)
4994#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x30000U)
4995#define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT (16U)
4996#define BCH_LAYOUTSELECT_CS8_SELECT(x) \
4997 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK)
4998#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0xC0000U)
4999#define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT (18U)
5000#define BCH_LAYOUTSELECT_CS9_SELECT(x) \
5001 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK)
5002#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x300000U)
5003#define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT (20U)
5004#define BCH_LAYOUTSELECT_CS10_SELECT(x) \
5005 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK)
5006#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0xC00000U)
5007#define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT (22U)
5008#define BCH_LAYOUTSELECT_CS11_SELECT(x) \
5009 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK)
5010#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3000000U)
5011#define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT (24U)
5012#define BCH_LAYOUTSELECT_CS12_SELECT(x) \
5013 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK)
5014#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0xC000000U)
5015#define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT (26U)
5016#define BCH_LAYOUTSELECT_CS13_SELECT(x) \
5017 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK)
5018#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x30000000U)
5019#define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT (28U)
5020#define BCH_LAYOUTSELECT_CS14_SELECT(x) \
5021 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK)
5022#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0xC0000000U)
5023#define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT (30U)
5024#define BCH_LAYOUTSELECT_CS15_SELECT(x) \
5025 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK)
5026/*! @} */
5027
5028/*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */
5029/*! @{ */
5030#define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
5031#define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT (0U)
5032#define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) \
5033 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK)
5034#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
5035#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
5036#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x) \
5037 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK)
5038#define BCH_FLASH0LAYOUT0_ECC0_MASK (0xF800U)
5039#define BCH_FLASH0LAYOUT0_ECC0_SHIFT (11U)
5040/*! ECC0
5041 * 0b00000..No ECC to be performed
5042 * 0b00001..ECC 2 to be performed
5043 * 0b00010..ECC 4 to be performed
5044 * 0b11110..ECC 60 to be performed
5045 * 0b11111..ECC 62 to be performed
5046 */
5047#define BCH_FLASH0LAYOUT0_ECC0(x) \
5048 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK)
5049#define BCH_FLASH0LAYOUT0_META_SIZE_MASK (0xFF0000U)
5050#define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT (16U)
5051#define BCH_FLASH0LAYOUT0_META_SIZE(x) \
5052 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK)
5053#define BCH_FLASH0LAYOUT0_NBLOCKS_MASK (0xFF000000U)
5054#define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT (24U)
5055#define BCH_FLASH0LAYOUT0_NBLOCKS(x) \
5056 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK)
5057/*! @} */
5058
5059/*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */
5060/*! @{ */
5061#define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
5062#define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT (0U)
5063#define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) \
5064 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK)
5065#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
5066#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
5067#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x) \
5068 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK)
5069#define BCH_FLASH0LAYOUT1_ECCN_MASK (0xF800U)
5070#define BCH_FLASH0LAYOUT1_ECCN_SHIFT (11U)
5071/*! ECCN
5072 * 0b00000..No ECC to be performed
5073 * 0b00001..ECC 2 to be performed
5074 * 0b00010..ECC 4 to be performed
5075 * 0b11110..ECC 60 to be performed
5076 * 0b11111..ECC 62 to be performed
5077 */
5078#define BCH_FLASH0LAYOUT1_ECCN(x) \
5079 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK)
5080#define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
5081#define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT (16U)
5082#define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) \
5083 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK)
5084/*! @} */
5085
5086/*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */
5087/*! @{ */
5088#define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
5089#define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT (0U)
5090#define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) \
5091 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK)
5092#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
5093#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
5094#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x) \
5095 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK)
5096#define BCH_FLASH1LAYOUT0_ECC0_MASK (0xF800U)
5097#define BCH_FLASH1LAYOUT0_ECC0_SHIFT (11U)
5098/*! ECC0
5099 * 0b00000..No ECC to be performed
5100 * 0b00001..ECC 2 to be performed
5101 * 0b00010..ECC 4 to be performed
5102 * 0b11110..ECC 60 to be performed
5103 * 0b11111..ECC 62 to be performed
5104 */
5105#define BCH_FLASH1LAYOUT0_ECC0(x) \
5106 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK)
5107#define BCH_FLASH1LAYOUT0_META_SIZE_MASK (0xFF0000U)
5108#define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT (16U)
5109#define BCH_FLASH1LAYOUT0_META_SIZE(x) \
5110 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK)
5111#define BCH_FLASH1LAYOUT0_NBLOCKS_MASK (0xFF000000U)
5112#define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT (24U)
5113#define BCH_FLASH1LAYOUT0_NBLOCKS(x) \
5114 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK)
5115/*! @} */
5116
5117/*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */
5118/*! @{ */
5119#define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
5120#define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT (0U)
5121#define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) \
5122 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK)
5123#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
5124#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
5125#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x) \
5126 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK)
5127#define BCH_FLASH1LAYOUT1_ECCN_MASK (0xF800U)
5128#define BCH_FLASH1LAYOUT1_ECCN_SHIFT (11U)
5129/*! ECCN
5130 * 0b00000..No ECC to be performed
5131 * 0b00001..ECC 2 to be performed
5132 * 0b00010..ECC 4 to be performed
5133 * 0b11110..ECC 60 to be performed
5134 * 0b11111..ECC 62 to be performed
5135 */
5136#define BCH_FLASH1LAYOUT1_ECCN(x) \
5137 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK)
5138#define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
5139#define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT (16U)
5140#define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) \
5141 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK)
5142/*! @} */
5143
5144/*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */
5145/*! @{ */
5146#define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
5147#define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT (0U)
5148#define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) \
5149 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK)
5150#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
5151#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
5152#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x) \
5153 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK)
5154#define BCH_FLASH2LAYOUT0_ECC0_MASK (0xF800U)
5155#define BCH_FLASH2LAYOUT0_ECC0_SHIFT (11U)
5156/*! ECC0
5157 * 0b00000..No ECC to be performed
5158 * 0b00001..ECC 2 to be performed
5159 * 0b00010..ECC 4 to be performed
5160 * 0b11110..ECC 60 to be performed
5161 * 0b11111..ECC 62 to be performed
5162 */
5163#define BCH_FLASH2LAYOUT0_ECC0(x) \
5164 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK)
5165#define BCH_FLASH2LAYOUT0_META_SIZE_MASK (0xFF0000U)
5166#define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT (16U)
5167#define BCH_FLASH2LAYOUT0_META_SIZE(x) \
5168 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK)
5169#define BCH_FLASH2LAYOUT0_NBLOCKS_MASK (0xFF000000U)
5170#define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT (24U)
5171#define BCH_FLASH2LAYOUT0_NBLOCKS(x) \
5172 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK)
5173/*! @} */
5174
5175/*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */
5176/*! @{ */
5177#define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
5178#define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT (0U)
5179#define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) \
5180 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK)
5181#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
5182#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
5183#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x) \
5184 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK)
5185#define BCH_FLASH2LAYOUT1_ECCN_MASK (0xF800U)
5186#define BCH_FLASH2LAYOUT1_ECCN_SHIFT (11U)
5187/*! ECCN
5188 * 0b00000..No ECC to be performed
5189 * 0b00001..ECC 2 to be performed
5190 * 0b00010..ECC 4 to be performed
5191 * 0b11110..ECC 60 to be performed
5192 * 0b11111..ECC 62 to be performed
5193 */
5194#define BCH_FLASH2LAYOUT1_ECCN(x) \
5195 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK)
5196#define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
5197#define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT (16U)
5198#define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) \
5199 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK)
5200/*! @} */
5201
5202/*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */
5203/*! @{ */
5204#define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
5205#define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT (0U)
5206#define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) \
5207 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK)
5208#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
5209#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
5210#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x) \
5211 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK)
5212#define BCH_FLASH3LAYOUT0_ECC0_MASK (0xF800U)
5213#define BCH_FLASH3LAYOUT0_ECC0_SHIFT (11U)
5214/*! ECC0
5215 * 0b00000..No ECC to be performed
5216 * 0b00001..ECC 2 to be performed
5217 * 0b00010..ECC 4 to be performed
5218 * 0b11110..ECC 60 to be performed
5219 * 0b11111..ECC 62 to be performed
5220 */
5221#define BCH_FLASH3LAYOUT0_ECC0(x) \
5222 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK)
5223#define BCH_FLASH3LAYOUT0_META_SIZE_MASK (0xFF0000U)
5224#define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT (16U)
5225#define BCH_FLASH3LAYOUT0_META_SIZE(x) \
5226 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK)
5227#define BCH_FLASH3LAYOUT0_NBLOCKS_MASK (0xFF000000U)
5228#define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT (24U)
5229#define BCH_FLASH3LAYOUT0_NBLOCKS(x) \
5230 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK)
5231/*! @} */
5232
5233/*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */
5234/*! @{ */
5235#define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
5236#define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT (0U)
5237#define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) \
5238 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK)
5239#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
5240#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
5241#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x) \
5242 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK)
5243#define BCH_FLASH3LAYOUT1_ECCN_MASK (0xF800U)
5244#define BCH_FLASH3LAYOUT1_ECCN_SHIFT (11U)
5245/*! ECCN
5246 * 0b00000..No ECC to be performed
5247 * 0b00001..ECC 2 to be performed
5248 * 0b00010..ECC 4 to be performed
5249 * 0b11110..ECC 60 to be performed
5250 * 0b11111..ECC 62 to be performed
5251 */
5252#define BCH_FLASH3LAYOUT1_ECCN(x) \
5253 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK)
5254#define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
5255#define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT (16U)
5256#define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) \
5257 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK)
5258/*! @} */
5259
5260/*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */
5261/*! @{ */
5262#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK (0x3FU)
5263#define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT (0U)
5264#define BCH_DEBUG0_DEBUG_REG_SELECT(x) \
5265 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK)
5266#define BCH_DEBUG0_RSVD0_MASK (0xC0U)
5267#define BCH_DEBUG0_RSVD0_SHIFT (6U)
5268#define BCH_DEBUG0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK)
5269#define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK (0x100U)
5270#define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT (8U)
5271/*! BM_KES_TEST_BYPASS
5272 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
5273 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
5274 */
5275#define BCH_DEBUG0_BM_KES_TEST_BYPASS(x) \
5276 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK)
5277#define BCH_DEBUG0_KES_DEBUG_STALL_MASK (0x200U)
5278#define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT (9U)
5279/*! KES_DEBUG_STALL
5280 * 0b0..KES FSM proceeds to next block supplied by bus master.
5281 * 0b1..KES FSM waits after current equations are solved and the search engine is started.
5282 */
5283#define BCH_DEBUG0_KES_DEBUG_STALL(x) \
5284 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK)
5285#define BCH_DEBUG0_KES_DEBUG_STEP_MASK (0x400U)
5286#define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT (10U)
5287#define BCH_DEBUG0_KES_DEBUG_STEP(x) \
5288 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK)
5289#define BCH_DEBUG0_KES_STANDALONE_MASK (0x800U)
5290#define BCH_DEBUG0_KES_STANDALONE_SHIFT (11U)
5291/*! KES_STANDALONE
5292 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
5293 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
5294 */
5295#define BCH_DEBUG0_KES_STANDALONE(x) \
5296 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK)
5297#define BCH_DEBUG0_KES_DEBUG_KICK_MASK (0x1000U)
5298#define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT (12U)
5299#define BCH_DEBUG0_KES_DEBUG_KICK(x) \
5300 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK)
5301#define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK (0x2000U)
5302#define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT (13U)
5303/*! KES_DEBUG_MODE4K
5304 * 0b1..Mode is set for 4K NAND pages.
5305 * 0b1..Mode is set for 2K NAND pages.
5306 */
5307#define BCH_DEBUG0_KES_DEBUG_MODE4K(x) \
5308 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK)
5309#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
5310#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
5311/*! KES_DEBUG_PAYLOAD_FLAG
5312 * 0b1..Payload is set for 512 bytes data block.
5313 * 0b1..Payload is set for 65 or 19 bytes auxiliary block.
5314 */
5315#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x) \
5316 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK)
5317#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
5318#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
5319#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x) \
5320 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK)
5321#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
5322#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
5323/*! KES_DEBUG_SYNDROME_SYMBOL
5324 * 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
5325 * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
5326 */
5327#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x) \
5328 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & \
5329 BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK)
5330#define BCH_DEBUG0_RSVD1_MASK (0xFE000000U)
5331#define BCH_DEBUG0_RSVD1_SHIFT (25U)
5332#define BCH_DEBUG0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK)
5333/*! @} */
5334
5335/*! @name DEBUG0_SET - Hardware BCH ECC Debug Register0 */
5336/*! @{ */
5337#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK (0x3FU)
5338#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT (0U)
5339#define BCH_DEBUG0_SET_DEBUG_REG_SELECT(x) \
5340 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK)
5341#define BCH_DEBUG0_SET_RSVD0_MASK (0xC0U)
5342#define BCH_DEBUG0_SET_RSVD0_SHIFT (6U)
5343#define BCH_DEBUG0_SET_RSVD0(x) \
5344 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD0_SHIFT)) & BCH_DEBUG0_SET_RSVD0_MASK)
5345#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK (0x100U)
5346#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT (8U)
5347/*! BM_KES_TEST_BYPASS
5348 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
5349 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
5350 */
5351#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS(x) \
5352 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK)
5353#define BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK (0x200U)
5354#define BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT (9U)
5355/*! KES_DEBUG_STALL
5356 * 0b0..KES FSM proceeds to next block supplied by bus master.
5357 * 0b1..KES FSM waits after current equations are solved and the search engine is started.
5358 */
5359#define BCH_DEBUG0_SET_KES_DEBUG_STALL(x) \
5360 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK)
5361#define BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK (0x400U)
5362#define BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT (10U)
5363#define BCH_DEBUG0_SET_KES_DEBUG_STEP(x) \
5364 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK)
5365#define BCH_DEBUG0_SET_KES_STANDALONE_MASK (0x800U)
5366#define BCH_DEBUG0_SET_KES_STANDALONE_SHIFT (11U)
5367/*! KES_STANDALONE
5368 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
5369 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
5370 */
5371#define BCH_DEBUG0_SET_KES_STANDALONE(x) \
5372 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_SET_KES_STANDALONE_MASK)
5373#define BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK (0x1000U)
5374#define BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT (12U)
5375#define BCH_DEBUG0_SET_KES_DEBUG_KICK(x) \
5376 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK)
5377#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK (0x2000U)
5378#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT (13U)
5379/*! KES_DEBUG_MODE4K
5380 * 0b1..Mode is set for 4K NAND pages.
5381 * 0b1..Mode is set for 2K NAND pages.
5382 */
5383#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K(x) \
5384 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK)
5385#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
5386#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
5387/*! KES_DEBUG_PAYLOAD_FLAG
5388 * 0b1..Payload is set for 512 bytes data block.
5389 * 0b1..Payload is set for 65 or 19 bytes auxiliary block.
5390 */
5391#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG(x) \
5392 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & \
5393 BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK)
5394#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
5395#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
5396#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND(x) \
5397 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT)) & \
5398 BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK)
5399#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
5400#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
5401/*! KES_DEBUG_SYNDROME_SYMBOL
5402 * 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
5403 * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
5404 */
5405#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL(x) \
5406 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & \
5407 BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK)
5408#define BCH_DEBUG0_SET_RSVD1_MASK (0xFE000000U)
5409#define BCH_DEBUG0_SET_RSVD1_SHIFT (25U)
5410#define BCH_DEBUG0_SET_RSVD1(x) \
5411 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD1_SHIFT)) & BCH_DEBUG0_SET_RSVD1_MASK)
5412/*! @} */
5413
5414/*! @name DEBUG0_CLR - Hardware BCH ECC Debug Register0 */
5415/*! @{ */
5416#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK (0x3FU)
5417#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT (0U)
5418#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT(x) \
5419 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK)
5420#define BCH_DEBUG0_CLR_RSVD0_MASK (0xC0U)
5421#define BCH_DEBUG0_CLR_RSVD0_SHIFT (6U)
5422#define BCH_DEBUG0_CLR_RSVD0(x) \
5423 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD0_SHIFT)) & BCH_DEBUG0_CLR_RSVD0_MASK)
5424#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK (0x100U)
5425#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT (8U)
5426/*! BM_KES_TEST_BYPASS
5427 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
5428 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
5429 */
5430#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS(x) \
5431 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK)
5432#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK (0x200U)
5433#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT (9U)
5434/*! KES_DEBUG_STALL
5435 * 0b0..KES FSM proceeds to next block supplied by bus master.
5436 * 0b1..KES FSM waits after current equations are solved and the search engine is started.
5437 */
5438#define BCH_DEBUG0_CLR_KES_DEBUG_STALL(x) \
5439 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK)
5440#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK (0x400U)
5441#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT (10U)
5442#define BCH_DEBUG0_CLR_KES_DEBUG_STEP(x) \
5443 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK)
5444#define BCH_DEBUG0_CLR_KES_STANDALONE_MASK (0x800U)
5445#define BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT (11U)
5446/*! KES_STANDALONE
5447 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
5448 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
5449 */
5450#define BCH_DEBUG0_CLR_KES_STANDALONE(x) \
5451 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_CLR_KES_STANDALONE_MASK)
5452#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK (0x1000U)
5453#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT (12U)
5454#define BCH_DEBUG0_CLR_KES_DEBUG_KICK(x) \
5455 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK)
5456#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK (0x2000U)
5457#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT (13U)
5458/*! KES_DEBUG_MODE4K
5459 * 0b1..Mode is set for 4K NAND pages.
5460 * 0b1..Mode is set for 2K NAND pages.
5461 */
5462#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K(x) \
5463 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK)
5464#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
5465#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
5466/*! KES_DEBUG_PAYLOAD_FLAG
5467 * 0b1..Payload is set for 512 bytes data block.
5468 * 0b1..Payload is set for 65 or 19 bytes auxiliary block.
5469 */
5470#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG(x) \
5471 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & \
5472 BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK)
5473#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
5474#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
5475#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND(x) \
5476 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT)) & \
5477 BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK)
5478#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
5479#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
5480/*! KES_DEBUG_SYNDROME_SYMBOL
5481 * 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
5482 * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
5483 */
5484#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL(x) \
5485 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & \
5486 BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK)
5487#define BCH_DEBUG0_CLR_RSVD1_MASK (0xFE000000U)
5488#define BCH_DEBUG0_CLR_RSVD1_SHIFT (25U)
5489#define BCH_DEBUG0_CLR_RSVD1(x) \
5490 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD1_SHIFT)) & BCH_DEBUG0_CLR_RSVD1_MASK)
5491/*! @} */
5492
5493/*! @name DEBUG0_TOG - Hardware BCH ECC Debug Register0 */
5494/*! @{ */
5495#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK (0x3FU)
5496#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT (0U)
5497#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT(x) \
5498 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK)
5499#define BCH_DEBUG0_TOG_RSVD0_MASK (0xC0U)
5500#define BCH_DEBUG0_TOG_RSVD0_SHIFT (6U)
5501#define BCH_DEBUG0_TOG_RSVD0(x) \
5502 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD0_SHIFT)) & BCH_DEBUG0_TOG_RSVD0_MASK)
5503#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK (0x100U)
5504#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT (8U)
5505/*! BM_KES_TEST_BYPASS
5506 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
5507 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
5508 */
5509#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS(x) \
5510 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK)
5511#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK (0x200U)
5512#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT (9U)
5513/*! KES_DEBUG_STALL
5514 * 0b0..KES FSM proceeds to next block supplied by bus master.
5515 * 0b1..KES FSM waits after current equations are solved and the search engine is started.
5516 */
5517#define BCH_DEBUG0_TOG_KES_DEBUG_STALL(x) \
5518 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK)
5519#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK (0x400U)
5520#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT (10U)
5521#define BCH_DEBUG0_TOG_KES_DEBUG_STEP(x) \
5522 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK)
5523#define BCH_DEBUG0_TOG_KES_STANDALONE_MASK (0x800U)
5524#define BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT (11U)
5525/*! KES_STANDALONE
5526 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
5527 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
5528 */
5529#define BCH_DEBUG0_TOG_KES_STANDALONE(x) \
5530 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_TOG_KES_STANDALONE_MASK)
5531#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK (0x1000U)
5532#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT (12U)
5533#define BCH_DEBUG0_TOG_KES_DEBUG_KICK(x) \
5534 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK)
5535#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK (0x2000U)
5536#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT (13U)
5537/*! KES_DEBUG_MODE4K
5538 * 0b1..Mode is set for 4K NAND pages.
5539 * 0b1..Mode is set for 2K NAND pages.
5540 */
5541#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K(x) \
5542 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK)
5543#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
5544#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
5545/*! KES_DEBUG_PAYLOAD_FLAG
5546 * 0b1..Payload is set for 512 bytes data block.
5547 * 0b1..Payload is set for 65 or 19 bytes auxiliary block.
5548 */
5549#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG(x) \
5550 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & \
5551 BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK)
5552#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
5553#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
5554#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND(x) \
5555 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT)) & \
5556 BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK)
5557#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
5558#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
5559/*! KES_DEBUG_SYNDROME_SYMBOL
5560 * 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
5561 * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
5562 */
5563#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL(x) \
5564 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & \
5565 BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK)
5566#define BCH_DEBUG0_TOG_RSVD1_MASK (0xFE000000U)
5567#define BCH_DEBUG0_TOG_RSVD1_SHIFT (25U)
5568#define BCH_DEBUG0_TOG_RSVD1(x) \
5569 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD1_SHIFT)) & BCH_DEBUG0_TOG_RSVD1_MASK)
5570/*! @} */
5571
5572/*! @name DBGKESREAD - KES Debug Read Register */
5573/*! @{ */
5574#define BCH_DBGKESREAD_VALUES_MASK (0xFFFFFFFFU)
5575#define BCH_DBGKESREAD_VALUES_SHIFT (0U)
5576#define BCH_DBGKESREAD_VALUES(x) \
5577 (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK)
5578/*! @} */
5579
5580/*! @name DBGCSFEREAD - Chien Search Debug Read Register */
5581/*! @{ */
5582#define BCH_DBGCSFEREAD_VALUES_MASK (0xFFFFFFFFU)
5583#define BCH_DBGCSFEREAD_VALUES_SHIFT (0U)
5584#define BCH_DBGCSFEREAD_VALUES(x) \
5585 (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK)
5586/*! @} */
5587
5588/*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */
5589/*! @{ */
5590#define BCH_DBGSYNDGENREAD_VALUES_MASK (0xFFFFFFFFU)
5591#define BCH_DBGSYNDGENREAD_VALUES_SHIFT (0U)
5592#define BCH_DBGSYNDGENREAD_VALUES(x) \
5593 (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK)
5594/*! @} */
5595
5596/*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */
5597/*! @{ */
5598#define BCH_DBGAHBMREAD_VALUES_MASK (0xFFFFFFFFU)
5599#define BCH_DBGAHBMREAD_VALUES_SHIFT (0U)
5600#define BCH_DBGAHBMREAD_VALUES(x) \
5601 (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK)
5602/*! @} */
5603
5604/*! @name BLOCKNAME - Block Name Register */
5605/*! @{ */
5606#define BCH_BLOCKNAME_NAME_MASK (0xFFFFFFFFU)
5607#define BCH_BLOCKNAME_NAME_SHIFT (0U)
5608#define BCH_BLOCKNAME_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK)
5609/*! @} */
5610
5611/*! @name VERSION - BCH Version Register */
5612/*! @{ */
5613#define BCH_VERSION_STEP_MASK (0xFFFFU)
5614#define BCH_VERSION_STEP_SHIFT (0U)
5615#define BCH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK)
5616#define BCH_VERSION_MINOR_MASK (0xFF0000U)
5617#define BCH_VERSION_MINOR_SHIFT (16U)
5618#define BCH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK)
5619#define BCH_VERSION_MAJOR_MASK (0xFF000000U)
5620#define BCH_VERSION_MAJOR_SHIFT (24U)
5621#define BCH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK)
5622/*! @} */
5623
5624/*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */
5625/*! @{ */
5626#define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK (0x1FFU)
5627#define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT (0U)
5628#define BCH_DEBUG1_ERASED_ZERO_COUNT(x) \
5629 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK)
5630#define BCH_DEBUG1_RSVD_MASK (0x7FFFFE00U)
5631#define BCH_DEBUG1_RSVD_SHIFT (9U)
5632#define BCH_DEBUG1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK)
5633#define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK (0x80000000U)
5634#define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT (31U)
5635/*! DEBUG1_PREERASECHK
5636 * 0b0..Turn off pre-erase check
5637 * 0b1..Turn on pre-erase check
5638 */
5639#define BCH_DEBUG1_DEBUG1_PREERASECHK(x) \
5640 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK)
5641/*! @} */
5642
5643/*!
5644 * @}
5645 */ /* end of group BCH_Register_Masks */
5646
5647/* BCH - Peripheral instance base addresses */
5648/** Peripheral BCH base address */
5649#define BCH_BASE (0x33004000u)
5650/** Peripheral BCH base pointer */
5651#define BCH ((BCH_Type *)BCH_BASE)
5652/** Array initializer of BCH peripheral base addresses */
5653#define BCH_BASE_ADDRS \
5654 { \
5655 BCH_BASE \
5656 }
5657/** Array initializer of BCH peripheral base pointers */
5658#define BCH_BASE_PTRS \
5659 { \
5660 BCH \
5661 }
5662/** Interrupt vectors for the BCH peripheral type */
5663#define BCH_IRQS \
5664 { \
5665 BCH_IRQn \
5666 }
5667
5668/*!
5669 * @}
5670 */ /* end of group BCH_Peripheral_Access_Layer */
5671
5672/* ----------------------------------------------------------------------------
5673 -- CCM Peripheral Access Layer
5674 ---------------------------------------------------------------------------- */
5675
5676/*!
5677 * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
5678 * @{
5679 */
5680
5681/** CCM - Register Layout Typedef */
5682typedef struct
5683{
5684 __IO uint32_t GPR0; /**< General Purpose Register, offset: 0x0 */
5685 __IO uint32_t GPR0_SET; /**< General Purpose Register, offset: 0x4 */
5686 __IO uint32_t GPR0_CLR; /**< General Purpose Register, offset: 0x8 */
5687 __IO uint32_t GPR0_TOG; /**< General Purpose Register, offset: 0xC */
5688 uint8_t RESERVED_0[2032];
5689 struct
5690 { /* offset: 0x800, array step: 0x10 */
5691 __IO uint32_t PLL_CTRL; /**< CCM PLL Control Register, array offset: 0x800, array step: 0x10 */
5692 __IO uint32_t PLL_CTRL_SET; /**< CCM PLL Control Register, array offset: 0x804, array step: 0x10 */
5693 __IO uint32_t PLL_CTRL_CLR; /**< CCM PLL Control Register, array offset: 0x808, array step: 0x10 */
5694 __IO uint32_t PLL_CTRL_TOG; /**< CCM PLL Control Register, array offset: 0x80C, array step: 0x10 */
5695 } PLL_CTRL[39];
5696 uint8_t RESERVED_1[13712];
5697 struct
5698 { /* offset: 0x4000, array step: 0x10 */
5699 __IO uint32_t CCGR; /**< CCM Clock Gating Register, array offset: 0x4000, array step: 0x10 */
5700 __IO uint32_t CCGR_SET; /**< CCM Clock Gating Register, array offset: 0x4004, array step: 0x10 */
5701 __IO uint32_t CCGR_CLR; /**< CCM Clock Gating Register, array offset: 0x4008, array step: 0x10 */
5702 __IO uint32_t CCGR_TOG; /**< CCM Clock Gating Register, array offset: 0x400C, array step: 0x10 */
5703 } CCGR[103];
5704 uint8_t RESERVED_2[14736];
5705 struct
5706 { /* offset: 0x8000, array step: 0x80 */
5707 __IO uint32_t TARGET_ROOT; /**< Target Register, array offset: 0x8000, array step: 0x80 */
5708 __IO uint32_t TARGET_ROOT_SET; /**< Target Register, array offset: 0x8004, array step: 0x80 */
5709 __IO uint32_t TARGET_ROOT_CLR; /**< Target Register, array offset: 0x8008, array step: 0x80 */
5710 __IO uint32_t TARGET_ROOT_TOG; /**< Target Register, array offset: 0x800C, array step: 0x80 */
5711 __IO uint32_t MISC; /**< Miscellaneous Register, array offset: 0x8010, array step: 0x80 */
5712 __IO uint32_t MISC_ROOT_SET; /**< Miscellaneous Register, array offset: 0x8014, array step: 0x80 */
5713 __IO uint32_t MISC_ROOT_CLR; /**< Miscellaneous Register, array offset: 0x8018, array step: 0x80 */
5714 __IO uint32_t MISC_ROOT_TOG; /**< Miscellaneous Register, array offset: 0x801C, array step: 0x80 */
5715 __IO uint32_t POST; /**< Post Divider Register, array offset: 0x8020, array step: 0x80 */
5716 __IO uint32_t POST_ROOT_SET; /**< Post Divider Register, array offset: 0x8024, array step: 0x80 */
5717 __IO uint32_t POST_ROOT_CLR; /**< Post Divider Register, array offset: 0x8028, array step: 0x80 */
5718 __IO uint32_t POST_ROOT_TOG; /**< Post Divider Register, array offset: 0x802C, array step: 0x80 */
5719 __IO uint32_t PRE; /**< Pre Divider Register, array offset: 0x8030, array step: 0x80 */
5720 __IO uint32_t PRE_ROOT_SET; /**< Pre Divider Register, array offset: 0x8034, array step: 0x80 */
5721 __IO uint32_t PRE_ROOT_CLR; /**< Pre Divider Register, array offset: 0x8038, array step: 0x80 */
5722 __IO uint32_t PRE_ROOT_TOG; /**< Pre Divider Register, array offset: 0x803C, array step: 0x80 */
5723 uint8_t RESERVED_0[48];
5724 __IO uint32_t ACCESS_CTRL; /**< Access Control Register, array offset: 0x8070, array step: 0x80 */
5725 __IO uint32_t ACCESS_CTRL_ROOT_SET; /**< Access Control Register, array offset: 0x8074, array step: 0x80 */
5726 __IO uint32_t ACCESS_CTRL_ROOT_CLR; /**< Access Control Register, array offset: 0x8078, array step: 0x80 */
5727 __IO uint32_t ACCESS_CTRL_ROOT_TOG; /**< Access Control Register, array offset: 0x807C, array step: 0x80 */
5728 } ROOT[135];
5729} CCM_Type;
5730
5731/* ----------------------------------------------------------------------------
5732 -- CCM Register Masks
5733 ---------------------------------------------------------------------------- */
5734
5735/*!
5736 * @addtogroup CCM_Register_Masks CCM Register Masks
5737 * @{
5738 */
5739
5740/*! @name GPR0 - General Purpose Register */
5741/*! @{ */
5742#define CCM_GPR0_GP0_MASK (0xFFFFFFFFU)
5743#define CCM_GPR0_GP0_SHIFT (0U)
5744#define CCM_GPR0_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_GP0_SHIFT)) & CCM_GPR0_GP0_MASK)
5745/*! @} */
5746
5747/*! @name GPR0_SET - General Purpose Register */
5748/*! @{ */
5749#define CCM_GPR0_SET_GP0_MASK (0xFFFFFFFFU)
5750#define CCM_GPR0_SET_GP0_SHIFT (0U)
5751#define CCM_GPR0_SET_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_SET_GP0_SHIFT)) & CCM_GPR0_SET_GP0_MASK)
5752/*! @} */
5753
5754/*! @name GPR0_CLR - General Purpose Register */
5755/*! @{ */
5756#define CCM_GPR0_CLR_GP0_MASK (0xFFFFFFFFU)
5757#define CCM_GPR0_CLR_GP0_SHIFT (0U)
5758#define CCM_GPR0_CLR_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_CLR_GP0_SHIFT)) & CCM_GPR0_CLR_GP0_MASK)
5759/*! @} */
5760
5761/*! @name GPR0_TOG - General Purpose Register */
5762/*! @{ */
5763#define CCM_GPR0_TOG_GP0_MASK (0xFFFFFFFFU)
5764#define CCM_GPR0_TOG_GP0_SHIFT (0U)
5765#define CCM_GPR0_TOG_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_TOG_GP0_SHIFT)) & CCM_GPR0_TOG_GP0_MASK)
5766/*! @} */
5767
5768/*! @name PLL_CTRL - CCM PLL Control Register */
5769/*! @{ */
5770#define CCM_PLL_CTRL_SETTING0_MASK (0x3U)
5771#define CCM_PLL_CTRL_SETTING0_SHIFT (0U)
5772/*! SETTING0
5773 * 0b00..Domain clocks not needed
5774 * 0b01..Domain clocks needed when in RUN
5775 * 0b10..Domain clocks needed when in RUN and WAIT
5776 * 0b11..Domain clocks needed all the time
5777 */
5778#define CCM_PLL_CTRL_SETTING0(x) \
5779 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING0_SHIFT)) & CCM_PLL_CTRL_SETTING0_MASK)
5780#define CCM_PLL_CTRL_SETTING1_MASK (0x30U)
5781#define CCM_PLL_CTRL_SETTING1_SHIFT (4U)
5782/*! SETTING1
5783 * 0b00..Domain clocks not needed
5784 * 0b01..Domain clocks needed when in RUN
5785 * 0b10..Domain clocks needed when in RUN and WAIT
5786 * 0b11..Domain clocks needed all the time
5787 */
5788#define CCM_PLL_CTRL_SETTING1(x) \
5789 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING1_SHIFT)) & CCM_PLL_CTRL_SETTING1_MASK)
5790#define CCM_PLL_CTRL_SETTING2_MASK (0x300U)
5791#define CCM_PLL_CTRL_SETTING2_SHIFT (8U)
5792/*! SETTING2
5793 * 0b00..Domain clocks not needed
5794 * 0b01..Domain clocks needed when in RUN
5795 * 0b10..Domain clocks needed when in RUN and WAIT
5796 * 0b11..Domain clocks needed all the time
5797 */
5798#define CCM_PLL_CTRL_SETTING2(x) \
5799 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING2_SHIFT)) & CCM_PLL_CTRL_SETTING2_MASK)
5800#define CCM_PLL_CTRL_SETTING3_MASK (0x3000U)
5801#define CCM_PLL_CTRL_SETTING3_SHIFT (12U)
5802/*! SETTING3
5803 * 0b00..Domain clocks not needed
5804 * 0b01..Domain clocks needed when in RUN
5805 * 0b10..Domain clocks needed when in RUN and WAIT
5806 * 0b11..Domain clocks needed all the time
5807 */
5808#define CCM_PLL_CTRL_SETTING3(x) \
5809 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING3_SHIFT)) & CCM_PLL_CTRL_SETTING3_MASK)
5810/*! @} */
5811
5812/* The count of CCM_PLL_CTRL */
5813#define CCM_PLL_CTRL_COUNT (39U)
5814
5815/*! @name PLL_CTRL_SET - CCM PLL Control Register */
5816/*! @{ */
5817#define CCM_PLL_CTRL_SET_SETTING0_MASK (0x3U)
5818#define CCM_PLL_CTRL_SET_SETTING0_SHIFT (0U)
5819/*! SETTING0
5820 * 0b00..Domain clocks not needed
5821 * 0b01..Domain clocks needed when in RUN
5822 * 0b10..Domain clocks needed when in RUN and WAIT
5823 * 0b11..Domain clocks needed all the time
5824 */
5825#define CCM_PLL_CTRL_SET_SETTING0(x) \
5826 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING0_SHIFT)) & CCM_PLL_CTRL_SET_SETTING0_MASK)
5827#define CCM_PLL_CTRL_SET_SETTING1_MASK (0x30U)
5828#define CCM_PLL_CTRL_SET_SETTING1_SHIFT (4U)
5829/*! SETTING1
5830 * 0b00..Domain clocks not needed
5831 * 0b01..Domain clocks needed when in RUN
5832 * 0b10..Domain clocks needed when in RUN and WAIT
5833 * 0b11..Domain clocks needed all the time
5834 */
5835#define CCM_PLL_CTRL_SET_SETTING1(x) \
5836 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING1_SHIFT)) & CCM_PLL_CTRL_SET_SETTING1_MASK)
5837#define CCM_PLL_CTRL_SET_SETTING2_MASK (0x300U)
5838#define CCM_PLL_CTRL_SET_SETTING2_SHIFT (8U)
5839/*! SETTING2
5840 * 0b00..Domain clocks not needed
5841 * 0b01..Domain clocks needed when in RUN
5842 * 0b10..Domain clocks needed when in RUN and WAIT
5843 * 0b11..Domain clocks needed all the time
5844 */
5845#define CCM_PLL_CTRL_SET_SETTING2(x) \
5846 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING2_SHIFT)) & CCM_PLL_CTRL_SET_SETTING2_MASK)
5847#define CCM_PLL_CTRL_SET_SETTING3_MASK (0x3000U)
5848#define CCM_PLL_CTRL_SET_SETTING3_SHIFT (12U)
5849/*! SETTING3
5850 * 0b00..Domain clocks not needed
5851 * 0b01..Domain clocks needed when in RUN
5852 * 0b10..Domain clocks needed when in RUN and WAIT
5853 * 0b11..Domain clocks needed all the time
5854 */
5855#define CCM_PLL_CTRL_SET_SETTING3(x) \
5856 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING3_SHIFT)) & CCM_PLL_CTRL_SET_SETTING3_MASK)
5857/*! @} */
5858
5859/* The count of CCM_PLL_CTRL_SET */
5860#define CCM_PLL_CTRL_SET_COUNT (39U)
5861
5862/*! @name PLL_CTRL_CLR - CCM PLL Control Register */
5863/*! @{ */
5864#define CCM_PLL_CTRL_CLR_SETTING0_MASK (0x3U)
5865#define CCM_PLL_CTRL_CLR_SETTING0_SHIFT (0U)
5866/*! SETTING0
5867 * 0b00..Domain clocks not needed
5868 * 0b01..Domain clocks needed when in RUN
5869 * 0b10..Domain clocks needed when in RUN and WAIT
5870 * 0b11..Domain clocks needed all the time
5871 */
5872#define CCM_PLL_CTRL_CLR_SETTING0(x) \
5873 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING0_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING0_MASK)
5874#define CCM_PLL_CTRL_CLR_SETTING1_MASK (0x30U)
5875#define CCM_PLL_CTRL_CLR_SETTING1_SHIFT (4U)
5876/*! SETTING1
5877 * 0b00..Domain clocks not needed
5878 * 0b01..Domain clocks needed when in RUN
5879 * 0b10..Domain clocks needed when in RUN and WAIT
5880 * 0b11..Domain clocks needed all the time
5881 */
5882#define CCM_PLL_CTRL_CLR_SETTING1(x) \
5883 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING1_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING1_MASK)
5884#define CCM_PLL_CTRL_CLR_SETTING2_MASK (0x300U)
5885#define CCM_PLL_CTRL_CLR_SETTING2_SHIFT (8U)
5886/*! SETTING2
5887 * 0b00..Domain clocks not needed
5888 * 0b01..Domain clocks needed when in RUN
5889 * 0b10..Domain clocks needed when in RUN and WAIT
5890 * 0b11..Domain clocks needed all the time
5891 */
5892#define CCM_PLL_CTRL_CLR_SETTING2(x) \
5893 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING2_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING2_MASK)
5894#define CCM_PLL_CTRL_CLR_SETTING3_MASK (0x3000U)
5895#define CCM_PLL_CTRL_CLR_SETTING3_SHIFT (12U)
5896/*! SETTING3
5897 * 0b00..Domain clocks not needed
5898 * 0b01..Domain clocks needed when in RUN
5899 * 0b10..Domain clocks needed when in RUN and WAIT
5900 * 0b11..Domain clocks needed all the time
5901 */
5902#define CCM_PLL_CTRL_CLR_SETTING3(x) \
5903 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING3_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING3_MASK)
5904/*! @} */
5905
5906/* The count of CCM_PLL_CTRL_CLR */
5907#define CCM_PLL_CTRL_CLR_COUNT (39U)
5908
5909/*! @name PLL_CTRL_TOG - CCM PLL Control Register */
5910/*! @{ */
5911#define CCM_PLL_CTRL_TOG_SETTING0_MASK (0x3U)
5912#define CCM_PLL_CTRL_TOG_SETTING0_SHIFT (0U)
5913/*! SETTING0
5914 * 0b00..Domain clocks not needed
5915 * 0b01..Domain clocks needed when in RUN
5916 * 0b10..Domain clocks needed when in RUN and WAIT
5917 * 0b11..Domain clocks needed all the time
5918 */
5919#define CCM_PLL_CTRL_TOG_SETTING0(x) \
5920 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING0_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING0_MASK)
5921#define CCM_PLL_CTRL_TOG_SETTING1_MASK (0x30U)
5922#define CCM_PLL_CTRL_TOG_SETTING1_SHIFT (4U)
5923/*! SETTING1
5924 * 0b00..Domain clocks not needed
5925 * 0b01..Domain clocks needed when in RUN
5926 * 0b10..Domain clocks needed when in RUN and WAIT
5927 * 0b11..Domain clocks needed all the time
5928 */
5929#define CCM_PLL_CTRL_TOG_SETTING1(x) \
5930 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING1_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING1_MASK)
5931#define CCM_PLL_CTRL_TOG_SETTING2_MASK (0x300U)
5932#define CCM_PLL_CTRL_TOG_SETTING2_SHIFT (8U)
5933/*! SETTING2
5934 * 0b00..Domain clocks not needed
5935 * 0b01..Domain clocks needed when in RUN
5936 * 0b10..Domain clocks needed when in RUN and WAIT
5937 * 0b11..Domain clocks needed all the time
5938 */
5939#define CCM_PLL_CTRL_TOG_SETTING2(x) \
5940 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING2_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING2_MASK)
5941#define CCM_PLL_CTRL_TOG_SETTING3_MASK (0x3000U)
5942#define CCM_PLL_CTRL_TOG_SETTING3_SHIFT (12U)
5943/*! SETTING3
5944 * 0b00..Domain clocks not needed
5945 * 0b01..Domain clocks needed when in RUN
5946 * 0b10..Domain clocks needed when in RUN and WAIT
5947 * 0b11..Domain clocks needed all the time
5948 */
5949#define CCM_PLL_CTRL_TOG_SETTING3(x) \
5950 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING3_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING3_MASK)
5951/*! @} */
5952
5953/* The count of CCM_PLL_CTRL_TOG */
5954#define CCM_PLL_CTRL_TOG_COUNT (39U)
5955
5956/*! @name CCGR - CCM Clock Gating Register */
5957/*! @{ */
5958#define CCM_CCGR_SETTING0_MASK (0x3U)
5959#define CCM_CCGR_SETTING0_SHIFT (0U)
5960/*! SETTING0
5961 * 0b00..Domain clocks not needed
5962 * 0b01..Domain clocks needed when in RUN
5963 * 0b10..Domain clocks needed when in RUN and WAIT
5964 * 0b11..Domain clocks needed all the time
5965 */
5966#define CCM_CCGR_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING0_SHIFT)) & CCM_CCGR_SETTING0_MASK)
5967#define CCM_CCGR_SETTING1_MASK (0x30U)
5968#define CCM_CCGR_SETTING1_SHIFT (4U)
5969/*! SETTING1
5970 * 0b00..Domain clocks not needed
5971 * 0b01..Domain clocks needed when in RUN
5972 * 0b10..Domain clocks needed when in RUN and WAIT
5973 * 0b11..Domain clocks needed all the time
5974 */
5975#define CCM_CCGR_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING1_SHIFT)) & CCM_CCGR_SETTING1_MASK)
5976#define CCM_CCGR_SETTING2_MASK (0x300U)
5977#define CCM_CCGR_SETTING2_SHIFT (8U)
5978/*! SETTING2
5979 * 0b00..Domain clocks not needed
5980 * 0b01..Domain clocks needed when in RUN
5981 * 0b10..Domain clocks needed when in RUN and WAIT
5982 * 0b11..Domain clocks needed all the time
5983 */
5984#define CCM_CCGR_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING2_SHIFT)) & CCM_CCGR_SETTING2_MASK)
5985#define CCM_CCGR_SETTING3_MASK (0x3000U)
5986#define CCM_CCGR_SETTING3_SHIFT (12U)
5987/*! SETTING3
5988 * 0b00..Domain clocks not needed
5989 * 0b01..Domain clocks needed when in RUN
5990 * 0b10..Domain clocks needed when in RUN and WAIT
5991 * 0b11..Domain clocks needed all the time
5992 */
5993#define CCM_CCGR_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING3_SHIFT)) & CCM_CCGR_SETTING3_MASK)
5994/*! @} */
5995
5996/* The count of CCM_CCGR */
5997#define CCM_CCGR_COUNT (103U)
5998
5999/*! @name CCGR_SET - CCM Clock Gating Register */
6000/*! @{ */
6001#define CCM_CCGR_SET_SETTING0_MASK (0x3U)
6002#define CCM_CCGR_SET_SETTING0_SHIFT (0U)
6003/*! SETTING0
6004 * 0b00..Domain clocks not needed
6005 * 0b01..Domain clocks needed when in RUN
6006 * 0b10..Domain clocks needed when in RUN and WAIT
6007 * 0b11..Domain clocks needed all the time
6008 */
6009#define CCM_CCGR_SET_SETTING0(x) \
6010 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING0_SHIFT)) & CCM_CCGR_SET_SETTING0_MASK)
6011#define CCM_CCGR_SET_SETTING1_MASK (0x30U)
6012#define CCM_CCGR_SET_SETTING1_SHIFT (4U)
6013/*! SETTING1
6014 * 0b00..Domain clocks not needed
6015 * 0b01..Domain clocks needed when in RUN
6016 * 0b10..Domain clocks needed when in RUN and WAIT
6017 * 0b11..Domain clocks needed all the time
6018 */
6019#define CCM_CCGR_SET_SETTING1(x) \
6020 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING1_SHIFT)) & CCM_CCGR_SET_SETTING1_MASK)
6021#define CCM_CCGR_SET_SETTING2_MASK (0x300U)
6022#define CCM_CCGR_SET_SETTING2_SHIFT (8U)
6023/*! SETTING2
6024 * 0b00..Domain clocks not needed
6025 * 0b01..Domain clocks needed when in RUN
6026 * 0b10..Domain clocks needed when in RUN and WAIT
6027 * 0b11..Domain clocks needed all the time
6028 */
6029#define CCM_CCGR_SET_SETTING2(x) \
6030 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING2_SHIFT)) & CCM_CCGR_SET_SETTING2_MASK)
6031#define CCM_CCGR_SET_SETTING3_MASK (0x3000U)
6032#define CCM_CCGR_SET_SETTING3_SHIFT (12U)
6033/*! SETTING3
6034 * 0b00..Domain clocks not needed
6035 * 0b01..Domain clocks needed when in RUN
6036 * 0b10..Domain clocks needed when in RUN and WAIT
6037 * 0b11..Domain clocks needed all the time
6038 */
6039#define CCM_CCGR_SET_SETTING3(x) \
6040 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING3_SHIFT)) & CCM_CCGR_SET_SETTING3_MASK)
6041/*! @} */
6042
6043/* The count of CCM_CCGR_SET */
6044#define CCM_CCGR_SET_COUNT (103U)
6045
6046/*! @name CCGR_CLR - CCM Clock Gating Register */
6047/*! @{ */
6048#define CCM_CCGR_CLR_SETTING0_MASK (0x3U)
6049#define CCM_CCGR_CLR_SETTING0_SHIFT (0U)
6050/*! SETTING0
6051 * 0b00..Domain clocks not needed
6052 * 0b01..Domain clocks needed when in RUN
6053 * 0b10..Domain clocks needed when in RUN and WAIT
6054 * 0b11..Domain clocks needed all the time
6055 */
6056#define CCM_CCGR_CLR_SETTING0(x) \
6057 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING0_SHIFT)) & CCM_CCGR_CLR_SETTING0_MASK)
6058#define CCM_CCGR_CLR_SETTING1_MASK (0x30U)
6059#define CCM_CCGR_CLR_SETTING1_SHIFT (4U)
6060/*! SETTING1
6061 * 0b00..Domain clocks not needed
6062 * 0b01..Domain clocks needed when in RUN
6063 * 0b10..Domain clocks needed when in RUN and WAIT
6064 * 0b11..Domain clocks needed all the time
6065 */
6066#define CCM_CCGR_CLR_SETTING1(x) \
6067 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING1_SHIFT)) & CCM_CCGR_CLR_SETTING1_MASK)
6068#define CCM_CCGR_CLR_SETTING2_MASK (0x300U)
6069#define CCM_CCGR_CLR_SETTING2_SHIFT (8U)
6070/*! SETTING2
6071 * 0b00..Domain clocks not needed
6072 * 0b01..Domain clocks needed when in RUN
6073 * 0b10..Domain clocks needed when in RUN and WAIT
6074 * 0b11..Domain clocks needed all the time
6075 */
6076#define CCM_CCGR_CLR_SETTING2(x) \
6077 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING2_SHIFT)) & CCM_CCGR_CLR_SETTING2_MASK)
6078#define CCM_CCGR_CLR_SETTING3_MASK (0x3000U)
6079#define CCM_CCGR_CLR_SETTING3_SHIFT (12U)
6080/*! SETTING3
6081 * 0b00..Domain clocks not needed
6082 * 0b01..Domain clocks needed when in RUN
6083 * 0b10..Domain clocks needed when in RUN and WAIT
6084 * 0b11..Domain clocks needed all the time
6085 */
6086#define CCM_CCGR_CLR_SETTING3(x) \
6087 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING3_SHIFT)) & CCM_CCGR_CLR_SETTING3_MASK)
6088/*! @} */
6089
6090/* The count of CCM_CCGR_CLR */
6091#define CCM_CCGR_CLR_COUNT (103U)
6092
6093/*! @name CCGR_TOG - CCM Clock Gating Register */
6094/*! @{ */
6095#define CCM_CCGR_TOG_SETTING0_MASK (0x3U)
6096#define CCM_CCGR_TOG_SETTING0_SHIFT (0U)
6097/*! SETTING0
6098 * 0b00..Domain clocks not needed
6099 * 0b01..Domain clocks needed when in RUN
6100 * 0b10..Domain clocks needed when in RUN and WAIT
6101 * 0b11..Domain clocks needed all the time
6102 */
6103#define CCM_CCGR_TOG_SETTING0(x) \
6104 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING0_SHIFT)) & CCM_CCGR_TOG_SETTING0_MASK)
6105#define CCM_CCGR_TOG_SETTING1_MASK (0x30U)
6106#define CCM_CCGR_TOG_SETTING1_SHIFT (4U)
6107/*! SETTING1
6108 * 0b00..Domain clocks not needed
6109 * 0b01..Domain clocks needed when in RUN
6110 * 0b10..Domain clocks needed when in RUN and WAIT
6111 * 0b11..Domain clocks needed all the time
6112 */
6113#define CCM_CCGR_TOG_SETTING1(x) \
6114 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING1_SHIFT)) & CCM_CCGR_TOG_SETTING1_MASK)
6115#define CCM_CCGR_TOG_SETTING2_MASK (0x300U)
6116#define CCM_CCGR_TOG_SETTING2_SHIFT (8U)
6117/*! SETTING2
6118 * 0b00..Domain clocks not needed
6119 * 0b01..Domain clocks needed when in RUN
6120 * 0b10..Domain clocks needed when in RUN and WAIT
6121 * 0b11..Domain clocks needed all the time
6122 */
6123#define CCM_CCGR_TOG_SETTING2(x) \
6124 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING2_SHIFT)) & CCM_CCGR_TOG_SETTING2_MASK)
6125#define CCM_CCGR_TOG_SETTING3_MASK (0x3000U)
6126#define CCM_CCGR_TOG_SETTING3_SHIFT (12U)
6127/*! SETTING3
6128 * 0b00..Domain clocks not needed
6129 * 0b01..Domain clocks needed when in RUN
6130 * 0b10..Domain clocks needed when in RUN and WAIT
6131 * 0b11..Domain clocks needed all the time
6132 */
6133#define CCM_CCGR_TOG_SETTING3(x) \
6134 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING3_SHIFT)) & CCM_CCGR_TOG_SETTING3_MASK)
6135/*! @} */
6136
6137/* The count of CCM_CCGR_TOG */
6138#define CCM_CCGR_TOG_COUNT (103U)
6139
6140/*! @name TARGET_ROOT - Target Register */
6141/*! @{ */
6142#define CCM_TARGET_ROOT_POST_PODF_MASK (0x3FU)
6143#define CCM_TARGET_ROOT_POST_PODF_SHIFT (0U)
6144/*! POST_PODF
6145 * 0b000000..Divide by 1
6146 * 0b000001..Divide by 2
6147 * 0b000010..Divide by 3
6148 * 0b000011..Divide by 4
6149 * 0b000100..Divide by 5
6150 * 0b000101..Divide by 6
6151 * 0b111111..Divide by 64
6152 */
6153#define CCM_TARGET_ROOT_POST_PODF(x) \
6154 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_POST_PODF_MASK)
6155#define CCM_TARGET_ROOT_PRE_PODF_MASK (0x70000U)
6156#define CCM_TARGET_ROOT_PRE_PODF_SHIFT (16U)
6157/*! PRE_PODF
6158 * 0b000..Divide by 1
6159 * 0b001..Divide by 2
6160 * 0b010..Divide by 3
6161 * 0b011..Divide by 4
6162 * 0b100..Divide by 5
6163 * 0b101..Divide by 6
6164 * 0b110..Divide by 7
6165 * 0b111..Divide by 8
6166 */
6167#define CCM_TARGET_ROOT_PRE_PODF(x) \
6168 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_PRE_PODF_MASK)
6169#define CCM_TARGET_ROOT_MUX_MASK (0x7000000U)
6170#define CCM_TARGET_ROOT_MUX_SHIFT (24U)
6171#define CCM_TARGET_ROOT_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_MUX_SHIFT)) & CCM_TARGET_ROOT_MUX_MASK)
6172#define CCM_TARGET_ROOT_ENABLE_MASK (0x10000000U)
6173#define CCM_TARGET_ROOT_ENABLE_SHIFT (28U)
6174/*! ENABLE
6175 * 0b0..clock root is OFF
6176 * 0b1..clock root is ON
6177 */
6178#define CCM_TARGET_ROOT_ENABLE(x) \
6179 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_ENABLE_SHIFT)) & CCM_TARGET_ROOT_ENABLE_MASK)
6180/*! @} */
6181
6182/* The count of CCM_TARGET_ROOT */
6183#define CCM_TARGET_ROOT_COUNT (135U)
6184
6185/*! @name TARGET_ROOT_SET - Target Register */
6186/*! @{ */
6187#define CCM_TARGET_ROOT_SET_POST_PODF_MASK (0x3FU)
6188#define CCM_TARGET_ROOT_SET_POST_PODF_SHIFT (0U)
6189/*! POST_PODF
6190 * 0b000000..Divide by 1
6191 * 0b000001..Divide by 2
6192 * 0b000010..Divide by 3
6193 * 0b000011..Divide by 4
6194 * 0b000100..Divide by 5
6195 * 0b000101..Divide by 6
6196 * 0b111111..Divide by 64
6197 */
6198#define CCM_TARGET_ROOT_SET_POST_PODF(x) \
6199 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_SET_POST_PODF_MASK)
6200#define CCM_TARGET_ROOT_SET_PRE_PODF_MASK (0x70000U)
6201#define CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT (16U)
6202/*! PRE_PODF
6203 * 0b000..Divide by 1
6204 * 0b001..Divide by 2
6205 * 0b010..Divide by 3
6206 * 0b011..Divide by 4
6207 * 0b100..Divide by 5
6208 * 0b101..Divide by 6
6209 * 0b110..Divide by 7
6210 * 0b111..Divide by 8
6211 */
6212#define CCM_TARGET_ROOT_SET_PRE_PODF(x) \
6213 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_SET_PRE_PODF_MASK)
6214#define CCM_TARGET_ROOT_SET_MUX_MASK (0x7000000U)
6215#define CCM_TARGET_ROOT_SET_MUX_SHIFT (24U)
6216#define CCM_TARGET_ROOT_SET_MUX(x) \
6217 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_MUX_SHIFT)) & CCM_TARGET_ROOT_SET_MUX_MASK)
6218#define CCM_TARGET_ROOT_SET_ENABLE_MASK (0x10000000U)
6219#define CCM_TARGET_ROOT_SET_ENABLE_SHIFT (28U)
6220/*! ENABLE
6221 * 0b0..clock root is OFF
6222 * 0b1..clock root is ON
6223 */
6224#define CCM_TARGET_ROOT_SET_ENABLE(x) \
6225 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_ENABLE_SHIFT)) & CCM_TARGET_ROOT_SET_ENABLE_MASK)
6226/*! @} */
6227
6228/* The count of CCM_TARGET_ROOT_SET */
6229#define CCM_TARGET_ROOT_SET_COUNT (135U)
6230
6231/*! @name TARGET_ROOT_CLR - Target Register */
6232/*! @{ */
6233#define CCM_TARGET_ROOT_CLR_POST_PODF_MASK (0x3FU)
6234#define CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT (0U)
6235/*! POST_PODF
6236 * 0b000000..Divide by 1
6237 * 0b000001..Divide by 2
6238 * 0b000010..Divide by 3
6239 * 0b000011..Divide by 4
6240 * 0b000100..Divide by 5
6241 * 0b000101..Divide by 6
6242 * 0b111111..Divide by 64
6243 */
6244#define CCM_TARGET_ROOT_CLR_POST_PODF(x) \
6245 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_CLR_POST_PODF_MASK)
6246#define CCM_TARGET_ROOT_CLR_PRE_PODF_MASK (0x70000U)
6247#define CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT (16U)
6248/*! PRE_PODF
6249 * 0b000..Divide by 1
6250 * 0b001..Divide by 2
6251 * 0b010..Divide by 3
6252 * 0b011..Divide by 4
6253 * 0b100..Divide by 5
6254 * 0b101..Divide by 6
6255 * 0b110..Divide by 7
6256 * 0b111..Divide by 8
6257 */
6258#define CCM_TARGET_ROOT_CLR_PRE_PODF(x) \
6259 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_CLR_PRE_PODF_MASK)
6260#define CCM_TARGET_ROOT_CLR_MUX_MASK (0x7000000U)
6261#define CCM_TARGET_ROOT_CLR_MUX_SHIFT (24U)
6262#define CCM_TARGET_ROOT_CLR_MUX(x) \
6263 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_MUX_SHIFT)) & CCM_TARGET_ROOT_CLR_MUX_MASK)
6264#define CCM_TARGET_ROOT_CLR_ENABLE_MASK (0x10000000U)
6265#define CCM_TARGET_ROOT_CLR_ENABLE_SHIFT (28U)
6266/*! ENABLE
6267 * 0b0..clock root is OFF
6268 * 0b1..clock root is ON
6269 */
6270#define CCM_TARGET_ROOT_CLR_ENABLE(x) \
6271 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_ENABLE_SHIFT)) & CCM_TARGET_ROOT_CLR_ENABLE_MASK)
6272/*! @} */
6273
6274/* The count of CCM_TARGET_ROOT_CLR */
6275#define CCM_TARGET_ROOT_CLR_COUNT (135U)
6276
6277/*! @name TARGET_ROOT_TOG - Target Register */
6278/*! @{ */
6279#define CCM_TARGET_ROOT_TOG_POST_PODF_MASK (0x3FU)
6280#define CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT (0U)
6281/*! POST_PODF
6282 * 0b000000..Divide by 1
6283 * 0b000001..Divide by 2
6284 * 0b000010..Divide by 3
6285 * 0b000011..Divide by 4
6286 * 0b000100..Divide by 5
6287 * 0b000101..Divide by 6
6288 * 0b111111..Divide by 64
6289 */
6290#define CCM_TARGET_ROOT_TOG_POST_PODF(x) \
6291 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_TOG_POST_PODF_MASK)
6292#define CCM_TARGET_ROOT_TOG_PRE_PODF_MASK (0x70000U)
6293#define CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT (16U)
6294/*! PRE_PODF
6295 * 0b000..Divide by 1
6296 * 0b001..Divide by 2
6297 * 0b010..Divide by 3
6298 * 0b011..Divide by 4
6299 * 0b100..Divide by 5
6300 * 0b101..Divide by 6
6301 * 0b110..Divide by 7
6302 * 0b111..Divide by 8
6303 */
6304#define CCM_TARGET_ROOT_TOG_PRE_PODF(x) \
6305 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_TOG_PRE_PODF_MASK)
6306#define CCM_TARGET_ROOT_TOG_MUX_MASK (0x7000000U)
6307#define CCM_TARGET_ROOT_TOG_MUX_SHIFT (24U)
6308#define CCM_TARGET_ROOT_TOG_MUX(x) \
6309 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_MUX_SHIFT)) & CCM_TARGET_ROOT_TOG_MUX_MASK)
6310#define CCM_TARGET_ROOT_TOG_ENABLE_MASK (0x10000000U)
6311#define CCM_TARGET_ROOT_TOG_ENABLE_SHIFT (28U)
6312/*! ENABLE
6313 * 0b0..clock root is OFF
6314 * 0b1..clock root is ON
6315 */
6316#define CCM_TARGET_ROOT_TOG_ENABLE(x) \
6317 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_ENABLE_SHIFT)) & CCM_TARGET_ROOT_TOG_ENABLE_MASK)
6318/*! @} */
6319
6320/* The count of CCM_TARGET_ROOT_TOG */
6321#define CCM_TARGET_ROOT_TOG_COUNT (135U)
6322
6323/*! @name MISC - Miscellaneous Register */
6324/*! @{ */
6325#define CCM_MISC_AUTHEN_FAIL_MASK (0x1U)
6326#define CCM_MISC_AUTHEN_FAIL_SHIFT (0U)
6327#define CCM_MISC_AUTHEN_FAIL(x) \
6328 (((uint32_t)(((uint32_t)(x)) << CCM_MISC_AUTHEN_FAIL_SHIFT)) & CCM_MISC_AUTHEN_FAIL_MASK)
6329#define CCM_MISC_TIMEOUT_MASK (0x10U)
6330#define CCM_MISC_TIMEOUT_SHIFT (4U)
6331#define CCM_MISC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_TIMEOUT_SHIFT)) & CCM_MISC_TIMEOUT_MASK)
6332#define CCM_MISC_VIOLATE_MASK (0x100U)
6333#define CCM_MISC_VIOLATE_SHIFT (8U)
6334#define CCM_MISC_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_VIOLATE_SHIFT)) & CCM_MISC_VIOLATE_MASK)
6335/*! @} */
6336
6337/* The count of CCM_MISC */
6338#define CCM_MISC_COUNT (135U)
6339
6340/*! @name MISC_ROOT_SET - Miscellaneous Register */
6341/*! @{ */
6342#define CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK (0x1U)
6343#define CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT (0U)
6344#define CCM_MISC_ROOT_SET_AUTHEN_FAIL(x) \
6345 (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK)
6346#define CCM_MISC_ROOT_SET_TIMEOUT_MASK (0x10U)
6347#define CCM_MISC_ROOT_SET_TIMEOUT_SHIFT (4U)
6348#define CCM_MISC_ROOT_SET_TIMEOUT(x) \
6349 (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_SET_TIMEOUT_MASK)
6350#define CCM_MISC_ROOT_SET_VIOLATE_MASK (0x100U)
6351#define CCM_MISC_ROOT_SET_VIOLATE_SHIFT (8U)
6352#define CCM_MISC_ROOT_SET_VIOLATE(x) \
6353 (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_VIOLATE_SHIFT)) & CCM_MISC_ROOT_SET_VIOLATE_MASK)
6354/*! @} */
6355
6356/* The count of CCM_MISC_ROOT_SET */
6357#define CCM_MISC_ROOT_SET_COUNT (135U)
6358
6359/*! @name MISC_ROOT_CLR - Miscellaneous Register */
6360/*! @{ */
6361#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK (0x1U)
6362#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT (0U)
6363#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL(x) \
6364 (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK)
6365#define CCM_MISC_ROOT_CLR_TIMEOUT_MASK (0x10U)
6366#define CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT (4U)
6367#define CCM_MISC_ROOT_CLR_TIMEOUT(x) \
6368 (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_CLR_TIMEOUT_MASK)
6369#define CCM_MISC_ROOT_CLR_VIOLATE_MASK (0x100U)
6370#define CCM_MISC_ROOT_CLR_VIOLATE_SHIFT (8U)
6371#define CCM_MISC_ROOT_CLR_VIOLATE(x) \
6372 (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_VIOLATE_SHIFT)) & CCM_MISC_ROOT_CLR_VIOLATE_MASK)
6373/*! @} */
6374
6375/* The count of CCM_MISC_ROOT_CLR */
6376#define CCM_MISC_ROOT_CLR_COUNT (135U)
6377
6378/*! @name MISC_ROOT_TOG - Miscellaneous Register */
6379/*! @{ */
6380#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK (0x1U)
6381#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT (0U)
6382#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL(x) \
6383 (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK)
6384#define CCM_MISC_ROOT_TOG_TIMEOUT_MASK (0x10U)
6385#define CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT (4U)
6386#define CCM_MISC_ROOT_TOG_TIMEOUT(x) \
6387 (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_TOG_TIMEOUT_MASK)
6388#define CCM_MISC_ROOT_TOG_VIOLATE_MASK (0x100U)
6389#define CCM_MISC_ROOT_TOG_VIOLATE_SHIFT (8U)
6390#define CCM_MISC_ROOT_TOG_VIOLATE(x) \
6391 (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_VIOLATE_SHIFT)) & CCM_MISC_ROOT_TOG_VIOLATE_MASK)
6392/*! @} */
6393
6394/* The count of CCM_MISC_ROOT_TOG */
6395#define CCM_MISC_ROOT_TOG_COUNT (135U)
6396
6397/*! @name POST - Post Divider Register */
6398/*! @{ */
6399#define CCM_POST_POST_PODF_MASK (0x3FU)
6400#define CCM_POST_POST_PODF_SHIFT (0U)
6401/*! POST_PODF
6402 * 0b000000..Divide by 1
6403 * 0b000001..Divide by 2
6404 * 0b000010..Divide by 3
6405 * 0b000011..Divide by 4
6406 * 0b000100..Divide by 5
6407 * 0b000101..Divide by 6
6408 * 0b111111..Divide by 64
6409 */
6410#define CCM_POST_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_POST_PODF_SHIFT)) & CCM_POST_POST_PODF_MASK)
6411#define CCM_POST_BUSY1_MASK (0x80U)
6412#define CCM_POST_BUSY1_SHIFT (7U)
6413#define CCM_POST_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_BUSY1_SHIFT)) & CCM_POST_BUSY1_MASK)
6414#define CCM_POST_SELECT_MASK (0x10000000U)
6415#define CCM_POST_SELECT_SHIFT (28U)
6416/*! SELECT
6417 * 0b0..select branch A
6418 * 0b1..select branch B
6419 */
6420#define CCM_POST_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_SELECT_SHIFT)) & CCM_POST_SELECT_MASK)
6421#define CCM_POST_BUSY2_MASK (0x80000000U)
6422#define CCM_POST_BUSY2_SHIFT (31U)
6423#define CCM_POST_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_BUSY2_SHIFT)) & CCM_POST_BUSY2_MASK)
6424/*! @} */
6425
6426/* The count of CCM_POST */
6427#define CCM_POST_COUNT (135U)
6428
6429/*! @name POST_ROOT_SET - Post Divider Register */
6430/*! @{ */
6431#define CCM_POST_ROOT_SET_POST_PODF_MASK (0x3FU)
6432#define CCM_POST_ROOT_SET_POST_PODF_SHIFT (0U)
6433/*! POST_PODF
6434 * 0b000000..Divide by 1
6435 * 0b000001..Divide by 2
6436 * 0b000010..Divide by 3
6437 * 0b000011..Divide by 4
6438 * 0b000100..Divide by 5
6439 * 0b000101..Divide by 6
6440 * 0b111111..Divide by 64
6441 */
6442#define CCM_POST_ROOT_SET_POST_PODF(x) \
6443 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_POST_PODF_SHIFT)) & CCM_POST_ROOT_SET_POST_PODF_MASK)
6444#define CCM_POST_ROOT_SET_BUSY1_MASK (0x80U)
6445#define CCM_POST_ROOT_SET_BUSY1_SHIFT (7U)
6446#define CCM_POST_ROOT_SET_BUSY1(x) \
6447 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_BUSY1_SHIFT)) & CCM_POST_ROOT_SET_BUSY1_MASK)
6448#define CCM_POST_ROOT_SET_SELECT_MASK (0x10000000U)
6449#define CCM_POST_ROOT_SET_SELECT_SHIFT (28U)
6450/*! SELECT
6451 * 0b0..select branch A
6452 * 0b1..select branch B
6453 */
6454#define CCM_POST_ROOT_SET_SELECT(x) \
6455 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_SELECT_SHIFT)) & CCM_POST_ROOT_SET_SELECT_MASK)
6456#define CCM_POST_ROOT_SET_BUSY2_MASK (0x80000000U)
6457#define CCM_POST_ROOT_SET_BUSY2_SHIFT (31U)
6458#define CCM_POST_ROOT_SET_BUSY2(x) \
6459 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_BUSY2_SHIFT)) & CCM_POST_ROOT_SET_BUSY2_MASK)
6460/*! @} */
6461
6462/* The count of CCM_POST_ROOT_SET */
6463#define CCM_POST_ROOT_SET_COUNT (135U)
6464
6465/*! @name POST_ROOT_CLR - Post Divider Register */
6466/*! @{ */
6467#define CCM_POST_ROOT_CLR_POST_PODF_MASK (0x3FU)
6468#define CCM_POST_ROOT_CLR_POST_PODF_SHIFT (0U)
6469/*! POST_PODF
6470 * 0b000000..Divide by 1
6471 * 0b000001..Divide by 2
6472 * 0b000010..Divide by 3
6473 * 0b000011..Divide by 4
6474 * 0b000100..Divide by 5
6475 * 0b000101..Divide by 6
6476 * 0b111111..Divide by 64
6477 */
6478#define CCM_POST_ROOT_CLR_POST_PODF(x) \
6479 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_POST_PODF_SHIFT)) & CCM_POST_ROOT_CLR_POST_PODF_MASK)
6480#define CCM_POST_ROOT_CLR_BUSY1_MASK (0x80U)
6481#define CCM_POST_ROOT_CLR_BUSY1_SHIFT (7U)
6482#define CCM_POST_ROOT_CLR_BUSY1(x) \
6483 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_BUSY1_SHIFT)) & CCM_POST_ROOT_CLR_BUSY1_MASK)
6484#define CCM_POST_ROOT_CLR_SELECT_MASK (0x10000000U)
6485#define CCM_POST_ROOT_CLR_SELECT_SHIFT (28U)
6486/*! SELECT
6487 * 0b0..select branch A
6488 * 0b1..select branch B
6489 */
6490#define CCM_POST_ROOT_CLR_SELECT(x) \
6491 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_SELECT_SHIFT)) & CCM_POST_ROOT_CLR_SELECT_MASK)
6492#define CCM_POST_ROOT_CLR_BUSY2_MASK (0x80000000U)
6493#define CCM_POST_ROOT_CLR_BUSY2_SHIFT (31U)
6494#define CCM_POST_ROOT_CLR_BUSY2(x) \
6495 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_BUSY2_SHIFT)) & CCM_POST_ROOT_CLR_BUSY2_MASK)
6496/*! @} */
6497
6498/* The count of CCM_POST_ROOT_CLR */
6499#define CCM_POST_ROOT_CLR_COUNT (135U)
6500
6501/*! @name POST_ROOT_TOG - Post Divider Register */
6502/*! @{ */
6503#define CCM_POST_ROOT_TOG_POST_PODF_MASK (0x3FU)
6504#define CCM_POST_ROOT_TOG_POST_PODF_SHIFT (0U)
6505/*! POST_PODF
6506 * 0b000000..Divide by 1
6507 * 0b000001..Divide by 2
6508 * 0b000010..Divide by 3
6509 * 0b000011..Divide by 4
6510 * 0b000100..Divide by 5
6511 * 0b000101..Divide by 6
6512 * 0b111111..Divide by 64
6513 */
6514#define CCM_POST_ROOT_TOG_POST_PODF(x) \
6515 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_POST_PODF_SHIFT)) & CCM_POST_ROOT_TOG_POST_PODF_MASK)
6516#define CCM_POST_ROOT_TOG_BUSY1_MASK (0x80U)
6517#define CCM_POST_ROOT_TOG_BUSY1_SHIFT (7U)
6518#define CCM_POST_ROOT_TOG_BUSY1(x) \
6519 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_BUSY1_SHIFT)) & CCM_POST_ROOT_TOG_BUSY1_MASK)
6520#define CCM_POST_ROOT_TOG_SELECT_MASK (0x10000000U)
6521#define CCM_POST_ROOT_TOG_SELECT_SHIFT (28U)
6522/*! SELECT
6523 * 0b0..select branch A
6524 * 0b1..select branch B
6525 */
6526#define CCM_POST_ROOT_TOG_SELECT(x) \
6527 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_SELECT_SHIFT)) & CCM_POST_ROOT_TOG_SELECT_MASK)
6528#define CCM_POST_ROOT_TOG_BUSY2_MASK (0x80000000U)
6529#define CCM_POST_ROOT_TOG_BUSY2_SHIFT (31U)
6530#define CCM_POST_ROOT_TOG_BUSY2(x) \
6531 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_BUSY2_SHIFT)) & CCM_POST_ROOT_TOG_BUSY2_MASK)
6532/*! @} */
6533
6534/* The count of CCM_POST_ROOT_TOG */
6535#define CCM_POST_ROOT_TOG_COUNT (135U)
6536
6537/*! @name PRE - Pre Divider Register */
6538/*! @{ */
6539#define CCM_PRE_PRE_PODF_B_MASK (0x7U)
6540#define CCM_PRE_PRE_PODF_B_SHIFT (0U)
6541/*! PRE_PODF_B
6542 * 0b000..Divide by 1
6543 * 0b001..Divide by 2
6544 * 0b010..Divide by 3
6545 * 0b011..Divide by 4
6546 * 0b100..Divide by 5
6547 * 0b101..Divide by 6
6548 * 0b110..Divide by 7
6549 * 0b111..Divide by 8
6550 */
6551#define CCM_PRE_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_PRE_PODF_B_SHIFT)) & CCM_PRE_PRE_PODF_B_MASK)
6552#define CCM_PRE_BUSY0_MASK (0x8U)
6553#define CCM_PRE_BUSY0_SHIFT (3U)
6554#define CCM_PRE_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY0_SHIFT)) & CCM_PRE_BUSY0_MASK)
6555#define CCM_PRE_MUX_B_MASK (0x700U)
6556#define CCM_PRE_MUX_B_SHIFT (8U)
6557#define CCM_PRE_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_MUX_B_SHIFT)) & CCM_PRE_MUX_B_MASK)
6558#define CCM_PRE_EN_B_MASK (0x1000U)
6559#define CCM_PRE_EN_B_SHIFT (12U)
6560/*! EN_B
6561 * 0b0..Clock shutdown
6562 * 0b1..Clock ON
6563 */
6564#define CCM_PRE_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_EN_B_SHIFT)) & CCM_PRE_EN_B_MASK)
6565#define CCM_PRE_BUSY1_MASK (0x8000U)
6566#define CCM_PRE_BUSY1_SHIFT (15U)
6567#define CCM_PRE_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY1_SHIFT)) & CCM_PRE_BUSY1_MASK)
6568#define CCM_PRE_PRE_PODF_A_MASK (0x70000U)
6569#define CCM_PRE_PRE_PODF_A_SHIFT (16U)
6570/*! PRE_PODF_A
6571 * 0b000..Divide by 1
6572 * 0b001..Divide by 2
6573 * 0b010..Divide by 3
6574 * 0b011..Divide by 4
6575 * 0b100..Divide by 5
6576 * 0b101..Divide by 6
6577 * 0b110..Divide by 7
6578 * 0b111..Divide by 8
6579 */
6580#define CCM_PRE_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_PRE_PODF_A_SHIFT)) & CCM_PRE_PRE_PODF_A_MASK)
6581#define CCM_PRE_BUSY3_MASK (0x80000U)
6582#define CCM_PRE_BUSY3_SHIFT (19U)
6583#define CCM_PRE_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY3_SHIFT)) & CCM_PRE_BUSY3_MASK)
6584#define CCM_PRE_MUX_A_MASK (0x7000000U)
6585#define CCM_PRE_MUX_A_SHIFT (24U)
6586#define CCM_PRE_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_MUX_A_SHIFT)) & CCM_PRE_MUX_A_MASK)
6587#define CCM_PRE_EN_A_MASK (0x10000000U)
6588#define CCM_PRE_EN_A_SHIFT (28U)
6589/*! EN_A
6590 * 0b0..Clock shutdown
6591 * 0b1..clock ON
6592 */
6593#define CCM_PRE_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_EN_A_SHIFT)) & CCM_PRE_EN_A_MASK)
6594#define CCM_PRE_BUSY4_MASK (0x80000000U)
6595#define CCM_PRE_BUSY4_SHIFT (31U)
6596#define CCM_PRE_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY4_SHIFT)) & CCM_PRE_BUSY4_MASK)
6597/*! @} */
6598
6599/* The count of CCM_PRE */
6600#define CCM_PRE_COUNT (135U)
6601
6602/*! @name PRE_ROOT_SET - Pre Divider Register */
6603/*! @{ */
6604#define CCM_PRE_ROOT_SET_PRE_PODF_B_MASK (0x7U)
6605#define CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT (0U)
6606/*! PRE_PODF_B
6607 * 0b000..Divide by 1
6608 * 0b001..Divide by 2
6609 * 0b010..Divide by 3
6610 * 0b011..Divide by 4
6611 * 0b100..Divide by 5
6612 * 0b101..Divide by 6
6613 * 0b110..Divide by 7
6614 * 0b111..Divide by 8
6615 */
6616#define CCM_PRE_ROOT_SET_PRE_PODF_B(x) \
6617 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_SET_PRE_PODF_B_MASK)
6618#define CCM_PRE_ROOT_SET_BUSY0_MASK (0x8U)
6619#define CCM_PRE_ROOT_SET_BUSY0_SHIFT (3U)
6620#define CCM_PRE_ROOT_SET_BUSY0(x) \
6621 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY0_SHIFT)) & CCM_PRE_ROOT_SET_BUSY0_MASK)
6622#define CCM_PRE_ROOT_SET_MUX_B_MASK (0x700U)
6623#define CCM_PRE_ROOT_SET_MUX_B_SHIFT (8U)
6624#define CCM_PRE_ROOT_SET_MUX_B(x) \
6625 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_MUX_B_SHIFT)) & CCM_PRE_ROOT_SET_MUX_B_MASK)
6626#define CCM_PRE_ROOT_SET_EN_B_MASK (0x1000U)
6627#define CCM_PRE_ROOT_SET_EN_B_SHIFT (12U)
6628/*! EN_B
6629 * 0b0..Clock shutdown
6630 * 0b1..Clock ON
6631 */
6632#define CCM_PRE_ROOT_SET_EN_B(x) \
6633 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_EN_B_SHIFT)) & CCM_PRE_ROOT_SET_EN_B_MASK)
6634#define CCM_PRE_ROOT_SET_BUSY1_MASK (0x8000U)
6635#define CCM_PRE_ROOT_SET_BUSY1_SHIFT (15U)
6636#define CCM_PRE_ROOT_SET_BUSY1(x) \
6637 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY1_SHIFT)) & CCM_PRE_ROOT_SET_BUSY1_MASK)
6638#define CCM_PRE_ROOT_SET_PRE_PODF_A_MASK (0x70000U)
6639#define CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT (16U)
6640/*! PRE_PODF_A
6641 * 0b000..Divide by 1
6642 * 0b001..Divide by 2
6643 * 0b010..Divide by 3
6644 * 0b011..Divide by 4
6645 * 0b100..Divide by 5
6646 * 0b101..Divide by 6
6647 * 0b110..Divide by 7
6648 * 0b111..Divide by 8
6649 */
6650#define CCM_PRE_ROOT_SET_PRE_PODF_A(x) \
6651 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_SET_PRE_PODF_A_MASK)
6652#define CCM_PRE_ROOT_SET_BUSY3_MASK (0x80000U)
6653#define CCM_PRE_ROOT_SET_BUSY3_SHIFT (19U)
6654#define CCM_PRE_ROOT_SET_BUSY3(x) \
6655 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY3_SHIFT)) & CCM_PRE_ROOT_SET_BUSY3_MASK)
6656#define CCM_PRE_ROOT_SET_MUX_A_MASK (0x7000000U)
6657#define CCM_PRE_ROOT_SET_MUX_A_SHIFT (24U)
6658#define CCM_PRE_ROOT_SET_MUX_A(x) \
6659 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_MUX_A_SHIFT)) & CCM_PRE_ROOT_SET_MUX_A_MASK)
6660#define CCM_PRE_ROOT_SET_EN_A_MASK (0x10000000U)
6661#define CCM_PRE_ROOT_SET_EN_A_SHIFT (28U)
6662/*! EN_A
6663 * 0b0..Clock shutdown
6664 * 0b1..clock ON
6665 */
6666#define CCM_PRE_ROOT_SET_EN_A(x) \
6667 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_EN_A_SHIFT)) & CCM_PRE_ROOT_SET_EN_A_MASK)
6668#define CCM_PRE_ROOT_SET_BUSY4_MASK (0x80000000U)
6669#define CCM_PRE_ROOT_SET_BUSY4_SHIFT (31U)
6670#define CCM_PRE_ROOT_SET_BUSY4(x) \
6671 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY4_SHIFT)) & CCM_PRE_ROOT_SET_BUSY4_MASK)
6672/*! @} */
6673
6674/* The count of CCM_PRE_ROOT_SET */
6675#define CCM_PRE_ROOT_SET_COUNT (135U)
6676
6677/*! @name PRE_ROOT_CLR - Pre Divider Register */
6678/*! @{ */
6679#define CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK (0x7U)
6680#define CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT (0U)
6681/*! PRE_PODF_B
6682 * 0b000..Divide by 1
6683 * 0b001..Divide by 2
6684 * 0b010..Divide by 3
6685 * 0b011..Divide by 4
6686 * 0b100..Divide by 5
6687 * 0b101..Divide by 6
6688 * 0b110..Divide by 7
6689 * 0b111..Divide by 8
6690 */
6691#define CCM_PRE_ROOT_CLR_PRE_PODF_B(x) \
6692 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK)
6693#define CCM_PRE_ROOT_CLR_BUSY0_MASK (0x8U)
6694#define CCM_PRE_ROOT_CLR_BUSY0_SHIFT (3U)
6695#define CCM_PRE_ROOT_CLR_BUSY0(x) \
6696 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY0_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY0_MASK)
6697#define CCM_PRE_ROOT_CLR_MUX_B_MASK (0x700U)
6698#define CCM_PRE_ROOT_CLR_MUX_B_SHIFT (8U)
6699#define CCM_PRE_ROOT_CLR_MUX_B(x) \
6700 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_MUX_B_SHIFT)) & CCM_PRE_ROOT_CLR_MUX_B_MASK)
6701#define CCM_PRE_ROOT_CLR_EN_B_MASK (0x1000U)
6702#define CCM_PRE_ROOT_CLR_EN_B_SHIFT (12U)
6703/*! EN_B
6704 * 0b0..Clock shutdown
6705 * 0b1..Clock ON
6706 */
6707#define CCM_PRE_ROOT_CLR_EN_B(x) \
6708 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_EN_B_SHIFT)) & CCM_PRE_ROOT_CLR_EN_B_MASK)
6709#define CCM_PRE_ROOT_CLR_BUSY1_MASK (0x8000U)
6710#define CCM_PRE_ROOT_CLR_BUSY1_SHIFT (15U)
6711#define CCM_PRE_ROOT_CLR_BUSY1(x) \
6712 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY1_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY1_MASK)
6713#define CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK (0x70000U)
6714#define CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT (16U)
6715/*! PRE_PODF_A
6716 * 0b000..Divide by 1
6717 * 0b001..Divide by 2
6718 * 0b010..Divide by 3
6719 * 0b011..Divide by 4
6720 * 0b100..Divide by 5
6721 * 0b101..Divide by 6
6722 * 0b110..Divide by 7
6723 * 0b111..Divide by 8
6724 */
6725#define CCM_PRE_ROOT_CLR_PRE_PODF_A(x) \
6726 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK)
6727#define CCM_PRE_ROOT_CLR_BUSY3_MASK (0x80000U)
6728#define CCM_PRE_ROOT_CLR_BUSY3_SHIFT (19U)
6729#define CCM_PRE_ROOT_CLR_BUSY3(x) \
6730 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY3_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY3_MASK)
6731#define CCM_PRE_ROOT_CLR_MUX_A_MASK (0x7000000U)
6732#define CCM_PRE_ROOT_CLR_MUX_A_SHIFT (24U)
6733#define CCM_PRE_ROOT_CLR_MUX_A(x) \
6734 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_MUX_A_SHIFT)) & CCM_PRE_ROOT_CLR_MUX_A_MASK)
6735#define CCM_PRE_ROOT_CLR_EN_A_MASK (0x10000000U)
6736#define CCM_PRE_ROOT_CLR_EN_A_SHIFT (28U)
6737/*! EN_A
6738 * 0b0..Clock shutdown
6739 * 0b1..clock ON
6740 */
6741#define CCM_PRE_ROOT_CLR_EN_A(x) \
6742 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_EN_A_SHIFT)) & CCM_PRE_ROOT_CLR_EN_A_MASK)
6743#define CCM_PRE_ROOT_CLR_BUSY4_MASK (0x80000000U)
6744#define CCM_PRE_ROOT_CLR_BUSY4_SHIFT (31U)
6745#define CCM_PRE_ROOT_CLR_BUSY4(x) \
6746 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY4_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY4_MASK)
6747/*! @} */
6748
6749/* The count of CCM_PRE_ROOT_CLR */
6750#define CCM_PRE_ROOT_CLR_COUNT (135U)
6751
6752/*! @name PRE_ROOT_TOG - Pre Divider Register */
6753/*! @{ */
6754#define CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK (0x7U)
6755#define CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT (0U)
6756/*! PRE_PODF_B
6757 * 0b000..Divide by 1
6758 * 0b001..Divide by 2
6759 * 0b010..Divide by 3
6760 * 0b011..Divide by 4
6761 * 0b100..Divide by 5
6762 * 0b101..Divide by 6
6763 * 0b110..Divide by 7
6764 * 0b111..Divide by 8
6765 */
6766#define CCM_PRE_ROOT_TOG_PRE_PODF_B(x) \
6767 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK)
6768#define CCM_PRE_ROOT_TOG_BUSY0_MASK (0x8U)
6769#define CCM_PRE_ROOT_TOG_BUSY0_SHIFT (3U)
6770#define CCM_PRE_ROOT_TOG_BUSY0(x) \
6771 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY0_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY0_MASK)
6772#define CCM_PRE_ROOT_TOG_MUX_B_MASK (0x700U)
6773#define CCM_PRE_ROOT_TOG_MUX_B_SHIFT (8U)
6774#define CCM_PRE_ROOT_TOG_MUX_B(x) \
6775 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_MUX_B_SHIFT)) & CCM_PRE_ROOT_TOG_MUX_B_MASK)
6776#define CCM_PRE_ROOT_TOG_EN_B_MASK (0x1000U)
6777#define CCM_PRE_ROOT_TOG_EN_B_SHIFT (12U)
6778/*! EN_B
6779 * 0b0..Clock shutdown
6780 * 0b1..Clock ON
6781 */
6782#define CCM_PRE_ROOT_TOG_EN_B(x) \
6783 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_EN_B_SHIFT)) & CCM_PRE_ROOT_TOG_EN_B_MASK)
6784#define CCM_PRE_ROOT_TOG_BUSY1_MASK (0x8000U)
6785#define CCM_PRE_ROOT_TOG_BUSY1_SHIFT (15U)
6786#define CCM_PRE_ROOT_TOG_BUSY1(x) \
6787 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY1_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY1_MASK)
6788#define CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK (0x70000U)
6789#define CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT (16U)
6790/*! PRE_PODF_A
6791 * 0b000..Divide by 1
6792 * 0b001..Divide by 2
6793 * 0b010..Divide by 3
6794 * 0b011..Divide by 4
6795 * 0b100..Divide by 5
6796 * 0b101..Divide by 6
6797 * 0b110..Divide by 7
6798 * 0b111..Divide by 8
6799 */
6800#define CCM_PRE_ROOT_TOG_PRE_PODF_A(x) \
6801 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK)
6802#define CCM_PRE_ROOT_TOG_BUSY3_MASK (0x80000U)
6803#define CCM_PRE_ROOT_TOG_BUSY3_SHIFT (19U)
6804#define CCM_PRE_ROOT_TOG_BUSY3(x) \
6805 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY3_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY3_MASK)
6806#define CCM_PRE_ROOT_TOG_MUX_A_MASK (0x7000000U)
6807#define CCM_PRE_ROOT_TOG_MUX_A_SHIFT (24U)
6808#define CCM_PRE_ROOT_TOG_MUX_A(x) \
6809 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_MUX_A_SHIFT)) & CCM_PRE_ROOT_TOG_MUX_A_MASK)
6810#define CCM_PRE_ROOT_TOG_EN_A_MASK (0x10000000U)
6811#define CCM_PRE_ROOT_TOG_EN_A_SHIFT (28U)
6812/*! EN_A
6813 * 0b0..Clock shutdown
6814 * 0b1..clock ON
6815 */
6816#define CCM_PRE_ROOT_TOG_EN_A(x) \
6817 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_EN_A_SHIFT)) & CCM_PRE_ROOT_TOG_EN_A_MASK)
6818#define CCM_PRE_ROOT_TOG_BUSY4_MASK (0x80000000U)
6819#define CCM_PRE_ROOT_TOG_BUSY4_SHIFT (31U)
6820#define CCM_PRE_ROOT_TOG_BUSY4(x) \
6821 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY4_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY4_MASK)
6822/*! @} */
6823
6824/* The count of CCM_PRE_ROOT_TOG */
6825#define CCM_PRE_ROOT_TOG_COUNT (135U)
6826
6827/*! @name ACCESS_CTRL - Access Control Register */
6828/*! @{ */
6829#define CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK (0xFU)
6830#define CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT (0U)
6831#define CCM_ACCESS_CTRL_DOMAIN0_INFO(x) \
6832 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK)
6833#define CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK (0xF0U)
6834#define CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT (4U)
6835#define CCM_ACCESS_CTRL_DOMAIN1_INFO(x) \
6836 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK)
6837#define CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK (0xF00U)
6838#define CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT (8U)
6839#define CCM_ACCESS_CTRL_DOMAIN2_INFO(x) \
6840 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK)
6841#define CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK (0xF000U)
6842#define CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT (12U)
6843#define CCM_ACCESS_CTRL_DOMAIN3_INFO(x) \
6844 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK)
6845#define CCM_ACCESS_CTRL_OWNER_ID_MASK (0x30000U)
6846#define CCM_ACCESS_CTRL_OWNER_ID_SHIFT (16U)
6847/*! OWNER_ID
6848 * 0b00..domaino
6849 * 0b01..domain1
6850 * 0b10..domain2
6851 * 0b11..domain3
6852 */
6853#define CCM_ACCESS_CTRL_OWNER_ID(x) \
6854 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_OWNER_ID_MASK)
6855#define CCM_ACCESS_CTRL_MUTEX_MASK (0x100000U)
6856#define CCM_ACCESS_CTRL_MUTEX_SHIFT (20U)
6857/*! MUTEX
6858 * 0b0..Semaphore is free to take
6859 * 0b1..Semaphore is taken
6860 */
6861#define CCM_ACCESS_CTRL_MUTEX(x) \
6862 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_MUTEX_MASK)
6863#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK (0x1000000U)
6864#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT (24U)
6865/*! DOMAIN0_WHITELIST
6866 * 0b0..Domain cannot change the setting
6867 * 0b1..Domain can change the setting
6868 */
6869#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST(x) \
6870 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK)
6871#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK (0x2000000U)
6872#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT (25U)
6873/*! DOMAIN1_WHITELIST
6874 * 0b0..Domain cannot change the setting
6875 * 0b1..Domain can change the setting
6876 */
6877#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST(x) \
6878 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK)
6879#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK (0x4000000U)
6880#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT (26U)
6881/*! DOMAIN2_WHITELIST
6882 * 0b0..Domain cannot change the setting
6883 * 0b1..Domain can change the setting
6884 */
6885#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST(x) \
6886 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK)
6887#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK (0x8000000U)
6888#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT (27U)
6889/*! DOMAIN3_WHITELIST
6890 * 0b0..Domain cannot change the setting
6891 * 0b1..Domain can change the setting
6892 */
6893#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST(x) \
6894 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK)
6895#define CCM_ACCESS_CTRL_SEMA_EN_MASK (0x10000000U)
6896#define CCM_ACCESS_CTRL_SEMA_EN_SHIFT (28U)
6897/*! SEMA_EN
6898 * 0b0..Disable
6899 * 0b1..Enable
6900 */
6901#define CCM_ACCESS_CTRL_SEMA_EN(x) \
6902 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_SEMA_EN_MASK)
6903#define CCM_ACCESS_CTRL_LOCK_MASK (0x80000000U)
6904#define CCM_ACCESS_CTRL_LOCK_SHIFT (31U)
6905/*! LOCK
6906 * 0b0..Access control inactive
6907 * 0b1..Access control active
6908 */
6909#define CCM_ACCESS_CTRL_LOCK(x) \
6910 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_LOCK_SHIFT)) & CCM_ACCESS_CTRL_LOCK_MASK)
6911/*! @} */
6912
6913/* The count of CCM_ACCESS_CTRL */
6914#define CCM_ACCESS_CTRL_COUNT (135U)
6915
6916/*! @name ACCESS_CTRL_ROOT_SET - Access Control Register */
6917/*! @{ */
6918#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK (0xFU)
6919#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT (0U)
6920#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO(x) \
6921 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT)) & \
6922 CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK)
6923#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK (0xF0U)
6924#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT (4U)
6925#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO(x) \
6926 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT)) & \
6927 CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK)
6928#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK (0xF00U)
6929#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT (8U)
6930#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO(x) \
6931 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT)) & \
6932 CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK)
6933#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK (0xF000U)
6934#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT (12U)
6935#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO(x) \
6936 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT)) & \
6937 CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK)
6938#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK (0x30000U)
6939#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT (16U)
6940/*! OWNER_ID
6941 * 0b00..domaino
6942 * 0b01..domain1
6943 * 0b10..domain2
6944 * 0b11..domain3
6945 */
6946#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID(x) \
6947 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK)
6948#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK (0x100000U)
6949#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT (20U)
6950/*! MUTEX
6951 * 0b0..Semaphore is free to take
6952 * 0b1..Semaphore is taken
6953 */
6954#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX(x) \
6955 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK)
6956#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK (0x1000000U)
6957#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT (24U)
6958/*! DOMAIN0_WHITELIST
6959 * 0b0..Domain cannot change the setting
6960 * 0b1..Domain can change the setting
6961 */
6962#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST(x) \
6963 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT)) & \
6964 CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK)
6965#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK (0x2000000U)
6966#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT (25U)
6967/*! DOMAIN1_WHITELIST
6968 * 0b0..Domain cannot change the setting
6969 * 0b1..Domain can change the setting
6970 */
6971#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST(x) \
6972 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT)) & \
6973 CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK)
6974#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK (0x4000000U)
6975#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT (26U)
6976/*! DOMAIN2_WHITELIST
6977 * 0b0..Domain cannot change the setting
6978 * 0b1..Domain can change the setting
6979 */
6980#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST(x) \
6981 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT)) & \
6982 CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK)
6983#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK (0x8000000U)
6984#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT (27U)
6985/*! DOMAIN3_WHITELIST
6986 * 0b0..Domain cannot change the setting
6987 * 0b1..Domain can change the setting
6988 */
6989#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST(x) \
6990 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT)) & \
6991 CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK)
6992#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK (0x10000000U)
6993#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT (28U)
6994/*! SEMA_EN
6995 * 0b0..Disable
6996 * 0b1..Enable
6997 */
6998#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN(x) \
6999 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK)
7000#define CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK (0x80000000U)
7001#define CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT (31U)
7002/*! LOCK
7003 * 0b0..Access control inactive
7004 * 0b1..Access control active
7005 */
7006#define CCM_ACCESS_CTRL_ROOT_SET_LOCK(x) \
7007 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK)
7008/*! @} */
7009
7010/* The count of CCM_ACCESS_CTRL_ROOT_SET */
7011#define CCM_ACCESS_CTRL_ROOT_SET_COUNT (135U)
7012
7013/*! @name ACCESS_CTRL_ROOT_CLR - Access Control Register */
7014/*! @{ */
7015#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK (0xFU)
7016#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT (0U)
7017#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO(x) \
7018 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT)) & \
7019 CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK)
7020#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK (0xF0U)
7021#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT (4U)
7022#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO(x) \
7023 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT)) & \
7024 CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK)
7025#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK (0xF00U)
7026#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT (8U)
7027#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO(x) \
7028 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT)) & \
7029 CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK)
7030#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK (0xF000U)
7031#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT (12U)
7032#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO(x) \
7033 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT)) & \
7034 CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK)
7035#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK (0x30000U)
7036#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT (16U)
7037/*! OWNER_ID
7038 * 0b00..domaino
7039 * 0b01..domain1
7040 * 0b10..domain2
7041 * 0b11..domain3
7042 */
7043#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID(x) \
7044 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK)
7045#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK (0x100000U)
7046#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT (20U)
7047/*! MUTEX
7048 * 0b0..Semaphore is free to take
7049 * 0b1..Semaphore is taken
7050 */
7051#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX(x) \
7052 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK)
7053#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK (0x1000000U)
7054#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT (24U)
7055/*! DOMAIN0_WHITELIST
7056 * 0b0..Domain cannot change the setting
7057 * 0b1..Domain can change the setting
7058 */
7059#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST(x) \
7060 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT)) & \
7061 CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK)
7062#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK (0x2000000U)
7063#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT (25U)
7064/*! DOMAIN1_WHITELIST
7065 * 0b0..Domain cannot change the setting
7066 * 0b1..Domain can change the setting
7067 */
7068#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST(x) \
7069 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT)) & \
7070 CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK)
7071#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK (0x4000000U)
7072#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT (26U)
7073/*! DOMAIN2_WHITELIST
7074 * 0b0..Domain cannot change the setting
7075 * 0b1..Domain can change the setting
7076 */
7077#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST(x) \
7078 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT)) & \
7079 CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK)
7080#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK (0x8000000U)
7081#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT (27U)
7082/*! DOMAIN3_WHITELIST
7083 * 0b0..Domain cannot change the setting
7084 * 0b1..Domain can change the setting
7085 */
7086#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST(x) \
7087 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT)) & \
7088 CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK)
7089#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK (0x10000000U)
7090#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT (28U)
7091/*! SEMA_EN
7092 * 0b0..Disable
7093 * 0b1..Enable
7094 */
7095#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN(x) \
7096 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK)
7097#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK (0x80000000U)
7098#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT (31U)
7099/*! LOCK
7100 * 0b0..Access control inactive
7101 * 0b1..Access control active
7102 */
7103#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK(x) \
7104 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK)
7105/*! @} */
7106
7107/* The count of CCM_ACCESS_CTRL_ROOT_CLR */
7108#define CCM_ACCESS_CTRL_ROOT_CLR_COUNT (135U)
7109
7110/*! @name ACCESS_CTRL_ROOT_TOG - Access Control Register */
7111/*! @{ */
7112#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK (0xFU)
7113#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT (0U)
7114#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO(x) \
7115 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT)) & \
7116 CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK)
7117#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK (0xF0U)
7118#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT (4U)
7119#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO(x) \
7120 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT)) & \
7121 CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK)
7122#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK (0xF00U)
7123#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT (8U)
7124#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO(x) \
7125 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT)) & \
7126 CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK)
7127#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK (0xF000U)
7128#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT (12U)
7129#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO(x) \
7130 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT)) & \
7131 CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK)
7132#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK (0x30000U)
7133#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT (16U)
7134/*! OWNER_ID
7135 * 0b00..domaino
7136 * 0b01..domain1
7137 * 0b10..domain2
7138 * 0b11..domain3
7139 */
7140#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID(x) \
7141 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK)
7142#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK (0x100000U)
7143#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT (20U)
7144/*! MUTEX
7145 * 0b0..Semaphore is free to take
7146 * 0b1..Semaphore is taken
7147 */
7148#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX(x) \
7149 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK)
7150#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK (0x1000000U)
7151#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT (24U)
7152/*! DOMAIN0_WHITELIST
7153 * 0b0..Domain cannot change the setting
7154 * 0b1..Domain can change the setting
7155 */
7156#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST(x) \
7157 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT)) & \
7158 CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK)
7159#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK (0x2000000U)
7160#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT (25U)
7161/*! DOMAIN1_WHITELIST
7162 * 0b0..Domain cannot change the setting
7163 * 0b1..Domain can change the setting
7164 */
7165#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST(x) \
7166 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT)) & \
7167 CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK)
7168#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK (0x4000000U)
7169#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT (26U)
7170/*! DOMAIN2_WHITELIST
7171 * 0b0..Domain cannot change the setting
7172 * 0b1..Domain can change the setting
7173 */
7174#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST(x) \
7175 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT)) & \
7176 CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK)
7177#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK (0x8000000U)
7178#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT (27U)
7179/*! DOMAIN3_WHITELIST
7180 * 0b0..Domain cannot change the setting
7181 * 0b1..Domain can change the setting
7182 */
7183#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST(x) \
7184 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT)) & \
7185 CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK)
7186#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK (0x10000000U)
7187#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT (28U)
7188/*! SEMA_EN
7189 * 0b0..Disable
7190 * 0b1..Enable
7191 */
7192#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN(x) \
7193 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK)
7194#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK (0x80000000U)
7195#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT (31U)
7196/*! LOCK
7197 * 0b0..Access control inactive
7198 * 0b1..Access control active
7199 */
7200#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK(x) \
7201 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK)
7202/*! @} */
7203
7204/* The count of CCM_ACCESS_CTRL_ROOT_TOG */
7205#define CCM_ACCESS_CTRL_ROOT_TOG_COUNT (135U)
7206
7207/*!
7208 * @}
7209 */ /* end of group CCM_Register_Masks */
7210
7211/* CCM - Peripheral instance base addresses */
7212/** Peripheral CCM base address */
7213#define CCM_BASE (0x30380000u)
7214/** Peripheral CCM base pointer */
7215#define CCM ((CCM_Type *)CCM_BASE)
7216/** Array initializer of CCM peripheral base addresses */
7217#define CCM_BASE_ADDRS \
7218 { \
7219 CCM_BASE \
7220 }
7221/** Array initializer of CCM peripheral base pointers */
7222#define CCM_BASE_PTRS \
7223 { \
7224 CCM \
7225 }
7226/** Interrupt vectors for the CCM peripheral type */
7227#define CCM_IRQS \
7228 { \
7229 CCM_IRQ1_IRQn, CCM_IRQ2_IRQn \
7230 }
7231
7232/*!
7233 * @}
7234 */ /* end of group CCM_Peripheral_Access_Layer */
7235
7236/* ----------------------------------------------------------------------------
7237 -- CCM_ANALOG Peripheral Access Layer
7238 ---------------------------------------------------------------------------- */
7239
7240/*!
7241 * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer
7242 * @{
7243 */
7244
7245/** CCM_ANALOG - Register Layout Typedef */
7246typedef struct
7247{
7248 __IO uint32_t AUDIO_PLL1_GEN_CTRL; /**< AUDIO PLL1 General Function Control Register, offset: 0x0 */
7249 __IO uint32_t AUDIO_PLL1_FDIV_CTL0; /**< AUDIO PLL1 Divide and Fraction Data Control 0 Register, offset: 0x4 */
7250 __IO uint32_t AUDIO_PLL1_FDIV_CTL1; /**< AUDIO PLL1 Divide and Fraction Data Control 1 Register, offset: 0x8 */
7251 __IO uint32_t AUDIO_PLL1_SSCG_CTRL; /**< AUDIO PLL1 PLL SSCG Control Register, offset: 0xC */
7252 __IO uint32_t AUDIO_PLL1_MNIT_CTRL; /**< AUDIO PLL1 PLL Monitoring Control Register, offset: 0x10 */
7253 __IO uint32_t AUDIO_PLL2_GEN_CTRL; /**< AUDIO PLL2 General Function Control Register, offset: 0x14 */
7254 __IO uint32_t AUDIO_PLL2_FDIV_CTL0; /**< AUDIO PLL2 Divide and Fraction Data Control 0 Register, offset: 0x18 */
7255 __IO uint32_t AUDIO_PLL2_FDIV_CTL1; /**< AUDIO PLL2 Divide and Fraction Data Control 1 Register, offset: 0x1C */
7256 __IO uint32_t AUDIO_PLL2_SSCG_CTRL; /**< AUDIO PLL2 PLL SSCG Control Register, offset: 0x20 */
7257 __IO uint32_t AUDIO_PLL2_MNIT_CTRL; /**< AUDIO PLL2 PLL Monitoring Control Register, offset: 0x24 */
7258 __IO uint32_t VIDEO_PLL1_GEN_CTRL; /**< VIDEO PLL1 General Function Control Register, offset: 0x28 */
7259 __IO uint32_t VIDEO_PLL1_FDIV_CTL0; /**< VIDEO PLL1 Divide and Fraction Data Control 0 Register, offset: 0x2C */
7260 __IO uint32_t VIDEO_PLL1_FDIV_CTL1; /**< VIDEO PLL1 Divide and Fraction Data Control 1 Register, offset: 0x30 */
7261 __IO uint32_t VIDEO_PLL1_SSCG_CTRL; /**< VIDEO PLL1 PLL SSCG Control Register, offset: 0x34 */
7262 __IO uint32_t VIDEO_PLL1_MNIT_CTRL; /**< VIDEO PLL1 PLL Monitoring Control Register, offset: 0x38 */
7263 uint8_t RESERVED_0[20];
7264 __IO uint32_t DRAM_PLL_GEN_CTRL; /**< DRAM PLL General Function Control Register, offset: 0x50 */
7265 __IO uint32_t DRAM_PLL_FDIV_CTL0; /**< DRAM PLL Divide and Fraction Data Control 0 Register, offset: 0x54 */
7266 __IO uint32_t DRAM_PLL_FDIV_CTL1; /**< DRAM PLL Divide and Fraction Data Control 1 Register, offset: 0x58 */
7267 __IO uint32_t DRAM_PLL_SSCG_CTRL; /**< DRAM PLL PLL SSCG Control Register, offset: 0x5C */
7268 __IO uint32_t DRAM_PLL_MNIT_CTRL; /**< DRAM PLL PLL Monitoring Control Register, offset: 0x60 */
7269 __IO uint32_t GPU_PLL_GEN_CTRL; /**< GPU PLL General Function Control Register, offset: 0x64 */
7270 __IO uint32_t GPU_PLL_FDIV_CTL0; /**< GPU PLL Divide and Fraction Data Control 0 Register, offset: 0x68 */
7271 __IO uint32_t GPU_PLL_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x6C */
7272 __IO uint32_t GPU_PLL_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x70 */
7273 __IO uint32_t M7_ALT_PLL_GEN_CTRL; /**< M7 Alternate PLL General Function Control Register, offset: 0x74 */
7274 __IO uint32_t
7275 M7_ALT_PLL_FDIV_CTL0; /**< M7 Alternate PLL Divide and Fraction Data Control 0 Register, offset: 0x78 */
7276 __IO uint32_t M7_ALT_PLL_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x7C */
7277 __IO uint32_t M7_ALT_PLL_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x80 */
7278 __IO uint32_t ARM_PLL_GEN_CTRL; /**< ARM PLL General Function Control Register, offset: 0x84 */
7279 __IO uint32_t ARM_PLL_FDIV_CTL0; /**< ARM PLL Divide and Fraction Data Control 0 Register, offset: 0x88 */
7280 __IO uint32_t ARM_PLL_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x8C */
7281 __IO uint32_t ARM_PLL_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x90 */
7282 __IO uint32_t SYS_PLL1_GEN_CTRL; /**< SYS PLL1 General Function Control Register, offset: 0x94 */
7283 __IO uint32_t SYS_PLL1_FDIV_CTL0; /**< SYS PLL1 Divide and Fraction Data Control 0 Register, offset: 0x98 */
7284 __IO uint32_t SYS_PLL1_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x9C */
7285 uint8_t RESERVED_1[96];
7286 __IO uint32_t SYS_PLL1_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x100 */
7287 __IO uint32_t SYS_PLL2_GEN_CTRL; /**< SYS PLL2 General Function Control Register, offset: 0x104 */
7288 __IO uint32_t SYS_PLL2_FDIV_CTL0; /**< SYS PLL2 Divide and Fraction Data Control 0 Register, offset: 0x108 */
7289 __IO uint32_t SYS_PLL2_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x10C */
7290 __IO uint32_t SYS_PLL2_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x110 */
7291 __IO uint32_t SYS_PLL3_GEN_CTRL; /**< SYS PLL3 General Function Control Register, offset: 0x114 */
7292 __IO uint32_t SYS_PLL3_FDIV_CTL0; /**< SYS PLL3 Divide and Fraction Data Control 0 Register, offset: 0x118 */
7293 __IO uint32_t SYS_PLL3_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x11C */
7294 __IO uint32_t SYS_PLL3_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x120 */
7295 __IO uint32_t OSC_MISC_CFG; /**< Osc Misc Configuration Register, offset: 0x124 */
7296 __IO uint32_t ANAMIX_PLL_MNIT_CTL; /**< PLL Clock Output for Test Enable and Select Register, offset: 0x128 */
7297 uint8_t RESERVED_2[1748];
7298 __I uint32_t DIGPROG; /**< DIGPROG Register, offset: 0x800 */
7299} CCM_ANALOG_Type;
7300
7301/* ----------------------------------------------------------------------------
7302 -- CCM_ANALOG Register Masks
7303 ---------------------------------------------------------------------------- */
7304
7305/*!
7306 * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks
7307 * @{
7308 */
7309
7310/*! @name AUDIO_PLL1_GEN_CTRL - AUDIO PLL1 General Function Control Register */
7311/*! @{ */
7312#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
7313#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
7314/*! PLL_REF_CLK_SEL
7315 * 0b00..SYS_XTAL
7316 * 0b01..PAD_CLK
7317 * 0b10..Reserved
7318 * 0b11..Reserved
7319 */
7320#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) \
7321 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \
7322 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
7323#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
7324#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
7325/*! PAD_CLK_SEL
7326 * 0b00..CLKIN1 XOR CLKIN2
7327 * 0b01..CLKIN2
7328 * 0b10..CLKIN1
7329 * 0b11..Reserved
7330 */
7331#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL(x) \
7332 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \
7333 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK)
7334#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
7335#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
7336#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS(x) \
7337 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & \
7338 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_MASK)
7339#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
7340#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
7341#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) \
7342 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \
7343 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
7344#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U)
7345#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U)
7346#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST(x) \
7347 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & \
7348 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_MASK)
7349#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
7350#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
7351#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \
7352 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \
7353 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
7354#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
7355#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (13U)
7356#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE(x) \
7357 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & \
7358 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_MASK)
7359#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
7360#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
7361#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) \
7362 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \
7363 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK)
7364#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
7365#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U)
7366#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK(x) \
7367 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & \
7368 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_MASK)
7369/*! @} */
7370
7371/*! @name AUDIO_PLL1_FDIV_CTL0 - AUDIO PLL1 Divide and Fraction Data Control 0 Register */
7372/*! @{ */
7373#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
7374#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
7375#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV(x) \
7376 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \
7377 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK)
7378#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
7379#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
7380#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) \
7381 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \
7382 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK)
7383#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
7384#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
7385#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) \
7386 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \
7387 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK)
7388/*! @} */
7389
7390/*! @name AUDIO_PLL1_FDIV_CTL1 - AUDIO PLL1 Divide and Fraction Data Control 1 Register */
7391/*! @{ */
7392#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
7393#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT (0U)
7394#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM(x) \
7395 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT)) & \
7396 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_MASK)
7397/*! @} */
7398
7399/*! @name AUDIO_PLL1_SSCG_CTRL - AUDIO PLL1 PLL SSCG Control Register */
7400/*! @{ */
7401#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_MASK (0x3U)
7402#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_SHIFT (0U)
7403/*! SEL_PF
7404 * 0b00..Down spread
7405 * 0b01..Up spread
7406 * 0b1x..Center spread
7407 */
7408#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF(x) \
7409 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_SHIFT)) & \
7410 CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_MASK)
7411#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
7412#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
7413#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL(x) \
7414 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & \
7415 CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK)
7416#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
7417#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
7418#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL(x) \
7419 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & \
7420 CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
7421#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
7422#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT (31U)
7423#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN(x) \
7424 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT)) & \
7425 CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_MASK)
7426/*! @} */
7427
7428/*! @name AUDIO_PLL1_MNIT_CTRL - AUDIO PLL1 PLL Monitoring Control Register */
7429/*! @{ */
7430#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_MASK (0x7U)
7431#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_SHIFT (0U)
7432#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP(x) \
7433 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_SHIFT)) & \
7434 CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_MASK)
7435#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_MASK (0x8U)
7436#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_SHIFT (3U)
7437#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN(x) \
7438 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & \
7439 CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_MASK)
7440#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
7441#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_SHIFT (4U)
7442#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC(x) \
7443 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & \
7444 CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_MASK)
7445#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_MASK (0x4000U)
7446#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_SHIFT (14U)
7447#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN(x) \
7448 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & \
7449 CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_MASK)
7450#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_MASK (0x8000U)
7451#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_SHIFT (15U)
7452/*! FSEL
7453 * 0b0..FEED_OUT = FREF
7454 * 0b1..FEED_OUT = FEED
7455 */
7456#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL(x) \
7457 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_SHIFT)) & \
7458 CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_MASK)
7459#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
7460#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
7461/*! AFCINIT_SEL
7462 * 0b0..nominal delay
7463 * 0b1..nominal delay * 2
7464 */
7465#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL(x) \
7466 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \
7467 CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK)
7468#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
7469#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
7470#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) \
7471 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \
7472 CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
7473#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
7474#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
7475/*! PBIAS_CTRL
7476 * 0b0..0.50*VDD
7477 * 0b1..0.67*VDD
7478 */
7479#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL(x) \
7480 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \
7481 CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK)
7482#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
7483#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (20U)
7484#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL(x) \
7485 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & \
7486 CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_MASK)
7487/*! @} */
7488
7489/*! @name AUDIO_PLL2_GEN_CTRL - AUDIO PLL2 General Function Control Register */
7490/*! @{ */
7491#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
7492#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
7493/*! PLL_REF_CLK_SEL
7494 * 0b00..SYS_XTAL
7495 * 0b01..PAD_CLK
7496 * 0b10..Reserved
7497 * 0b11..Reserved
7498 */
7499#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL(x) \
7500 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \
7501 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
7502#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
7503#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
7504/*! PAD_CLK_SEL
7505 * 0b00..CLKIN1 XOR CLKIN2
7506 * 0b01..CLKIN2
7507 * 0b10..CLKIN1
7508 * 0b11..Reserved
7509 */
7510#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL(x) \
7511 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \
7512 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK)
7513#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
7514#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
7515#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS(x) \
7516 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT)) & \
7517 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_MASK)
7518#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
7519#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
7520#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE(x) \
7521 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \
7522 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
7523#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_MASK (0x200U)
7524#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_SHIFT (9U)
7525#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST(x) \
7526 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_SHIFT)) & \
7527 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_MASK)
7528#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
7529#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
7530#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \
7531 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \
7532 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
7533#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
7534#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_SHIFT (13U)
7535#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE(x) \
7536 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_SHIFT)) & \
7537 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_MASK)
7538#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
7539#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
7540#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS(x) \
7541 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \
7542 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK)
7543#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
7544#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_SHIFT (31U)
7545#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK(x) \
7546 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_SHIFT)) & \
7547 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_MASK)
7548/*! @} */
7549
7550/*! @name AUDIO_PLL2_FDIV_CTL0 - AUDIO PLL2 Divide and Fraction Data Control 0 Register */
7551/*! @{ */
7552#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
7553#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
7554#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV(x) \
7555 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \
7556 CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK)
7557#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
7558#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
7559#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV(x) \
7560 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \
7561 CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK)
7562#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
7563#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
7564#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV(x) \
7565 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \
7566 CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK)
7567/*! @} */
7568
7569/*! @name AUDIO_PLL2_FDIV_CTL1 - AUDIO PLL2 Divide and Fraction Data Control 1 Register */
7570/*! @{ */
7571#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
7572#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_SHIFT (0U)
7573#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM(x) \
7574 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_SHIFT)) & \
7575 CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_MASK)
7576/*! @} */
7577
7578/*! @name AUDIO_PLL2_SSCG_CTRL - AUDIO PLL2 PLL SSCG Control Register */
7579/*! @{ */
7580#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_MASK (0x3U)
7581#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_SHIFT (0U)
7582/*! SEL_PF
7583 * 0b00..Down spread
7584 * 0b01..Up spread
7585 * 0b1x..Center spread
7586 */
7587#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF(x) \
7588 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_SHIFT)) & \
7589 CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_MASK)
7590#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
7591#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
7592#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL(x) \
7593 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & \
7594 CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_MASK)
7595#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
7596#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
7597#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL(x) \
7598 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & \
7599 CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
7600#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
7601#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_SHIFT (31U)
7602#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN(x) \
7603 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_SHIFT)) & \
7604 CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_MASK)
7605/*! @} */
7606
7607/*! @name AUDIO_PLL2_MNIT_CTRL - AUDIO PLL2 PLL Monitoring Control Register */
7608/*! @{ */
7609#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_MASK (0x7U)
7610#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_SHIFT (0U)
7611#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP(x) \
7612 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_SHIFT)) & \
7613 CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_MASK)
7614#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_MASK (0x8U)
7615#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_SHIFT (3U)
7616#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN(x) \
7617 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_SHIFT)) & \
7618 CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_MASK)
7619#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
7620#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_SHIFT (4U)
7621#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC(x) \
7622 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_SHIFT)) & \
7623 CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_MASK)
7624#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_MASK (0x4000U)
7625#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_SHIFT (14U)
7626#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN(x) \
7627 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_SHIFT)) & \
7628 CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_MASK)
7629#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_MASK (0x8000U)
7630#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_SHIFT (15U)
7631/*! FSEL
7632 * 0b0..FEED_OUT = FREF
7633 * 0b1..FEED_OUT = FEED
7634 */
7635#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL(x) \
7636 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_SHIFT)) & \
7637 CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_MASK)
7638#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
7639#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
7640/*! AFCINIT_SEL
7641 * 0b0..nominal delay
7642 * 0b1..nominal delay * 2
7643 */
7644#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL(x) \
7645 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \
7646 CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK)
7647#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
7648#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
7649#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN(x) \
7650 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \
7651 CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
7652#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
7653#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
7654/*! PBIAS_CTRL
7655 * 0b0..0.50*VDD
7656 * 0b1..0.67*VDD
7657 */
7658#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL(x) \
7659 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \
7660 CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK)
7661#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
7662#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_SHIFT (20U)
7663#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL(x) \
7664 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_SHIFT)) & \
7665 CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_MASK)
7666/*! @} */
7667
7668/*! @name VIDEO_PLL1_GEN_CTRL - VIDEO PLL1 General Function Control Register */
7669/*! @{ */
7670#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
7671#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
7672/*! PLL_REF_CLK_SEL
7673 * 0b00..SYS_XTAL
7674 * 0b01..PAD_CLK
7675 * 0b10..Reserved
7676 * 0b11..Reserved
7677 */
7678#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) \
7679 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \
7680 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
7681#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
7682#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
7683/*! PAD_CLK_SEL
7684 * 0b00..CLKIN1 XOR CLKIN2
7685 * 0b01..CLKIN2
7686 * 0b10..CLKIN1
7687 * 0b11..Reserved
7688 */
7689#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL(x) \
7690 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \
7691 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK)
7692#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
7693#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
7694#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS(x) \
7695 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & \
7696 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_MASK)
7697#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
7698#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
7699#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) \
7700 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \
7701 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
7702#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U)
7703#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U)
7704#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST(x) \
7705 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & \
7706 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_MASK)
7707#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
7708#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
7709#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \
7710 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \
7711 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
7712#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
7713#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (13U)
7714#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE(x) \
7715 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & \
7716 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_MASK)
7717#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
7718#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
7719#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) \
7720 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \
7721 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK)
7722#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
7723#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U)
7724#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK(x) \
7725 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & \
7726 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_MASK)
7727/*! @} */
7728
7729/*! @name VIDEO_PLL1_FDIV_CTL0 - VIDEO PLL1 Divide and Fraction Data Control 0 Register */
7730/*! @{ */
7731#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
7732#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
7733#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV(x) \
7734 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \
7735 CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK)
7736#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
7737#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
7738#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) \
7739 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \
7740 CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK)
7741#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
7742#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
7743#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) \
7744 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \
7745 CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK)
7746/*! @} */
7747
7748/*! @name VIDEO_PLL1_FDIV_CTL1 - VIDEO PLL1 Divide and Fraction Data Control 1 Register */
7749/*! @{ */
7750#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
7751#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT (0U)
7752#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM(x) \
7753 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT)) & \
7754 CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_MASK)
7755/*! @} */
7756
7757/*! @name VIDEO_PLL1_SSCG_CTRL - VIDEO PLL1 PLL SSCG Control Register */
7758/*! @{ */
7759#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_MASK (0x3U)
7760#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_SHIFT (0U)
7761/*! SEL_PF
7762 * 0b00..Down spread
7763 * 0b01..Up spread
7764 * 0b1x..Center spread
7765 */
7766#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF(x) \
7767 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_SHIFT)) & \
7768 CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_MASK)
7769#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
7770#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
7771#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL(x) \
7772 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & \
7773 CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK)
7774#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
7775#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
7776#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL(x) \
7777 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & \
7778 CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
7779#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
7780#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT (31U)
7781#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN(x) \
7782 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT)) & \
7783 CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_MASK)
7784/*! @} */
7785
7786/*! @name VIDEO_PLL1_MNIT_CTRL - VIDEO PLL1 PLL Monitoring Control Register */
7787/*! @{ */
7788#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_MASK (0x7U)
7789#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_SHIFT (0U)
7790#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP(x) \
7791 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_SHIFT)) & \
7792 CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_MASK)
7793#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_MASK (0x8U)
7794#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_SHIFT (3U)
7795#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN(x) \
7796 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & \
7797 CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_MASK)
7798#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
7799#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_SHIFT (4U)
7800#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC(x) \
7801 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & \
7802 CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_MASK)
7803#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_MASK (0x4000U)
7804#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_SHIFT (14U)
7805#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN(x) \
7806 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & \
7807 CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_MASK)
7808#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_MASK (0x8000U)
7809#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_SHIFT (15U)
7810/*! FSEL
7811 * 0b0..FEED_OUT = FREF
7812 * 0b1..FEED_OUT = FEED
7813 */
7814#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL(x) \
7815 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_SHIFT)) & \
7816 CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_MASK)
7817#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
7818#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
7819/*! AFCINIT_SEL
7820 * 0b0..nominal delay
7821 * 0b1..nominal delay * 2
7822 */
7823#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL(x) \
7824 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \
7825 CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK)
7826#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
7827#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
7828#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) \
7829 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \
7830 CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
7831#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
7832#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
7833/*! PBIAS_CTRL
7834 * 0b0..0.50*VDD
7835 * 0b1..0.67*VDD
7836 */
7837#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL(x) \
7838 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \
7839 CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK)
7840#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
7841#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (20U)
7842#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL(x) \
7843 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & \
7844 CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_MASK)
7845/*! @} */
7846
7847/*! @name DRAM_PLL_GEN_CTRL - DRAM PLL General Function Control Register */
7848/*! @{ */
7849#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
7850#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
7851/*! PLL_REF_CLK_SEL
7852 * 0b00..SYS_XTAL
7853 * 0b01..PAD_CLK
7854 * 0b10..Reserved
7855 * 0b11..Reserved
7856 */
7857#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) \
7858 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \
7859 CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
7860#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
7861#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
7862/*! PAD_CLK_SEL
7863 * 0b00..CLKIN1 XOR CLKIN2
7864 * 0b01..CLKIN2
7865 * 0b10..CLKIN1
7866 * 0b11..Reserved
7867 */
7868#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL(x) \
7869 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \
7870 CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
7871#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
7872#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
7873#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS(x) \
7874 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & \
7875 CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_MASK)
7876#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
7877#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
7878#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) \
7879 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \
7880 CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
7881#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
7882#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
7883#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST(x) \
7884 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_SHIFT)) & \
7885 CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_MASK)
7886#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
7887#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
7888#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \
7889 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \
7890 CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
7891#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
7892#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_SHIFT (13U)
7893#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE(x) \
7894 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & \
7895 CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_MASK)
7896#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
7897#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
7898#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) \
7899 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \
7900 CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
7901#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
7902#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
7903#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK(x) \
7904 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & \
7905 CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_MASK)
7906/*! @} */
7907
7908/*! @name DRAM_PLL_FDIV_CTL0 - DRAM PLL Divide and Fraction Data Control 0 Register */
7909/*! @{ */
7910#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
7911#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
7912#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV(x) \
7913 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \
7914 CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
7915#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
7916#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
7917#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV(x) \
7918 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \
7919 CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
7920#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
7921#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
7922#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) \
7923 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \
7924 CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
7925/*! @} */
7926
7927/*! @name DRAM_PLL_FDIV_CTL1 - DRAM PLL Divide and Fraction Data Control 1 Register */
7928/*! @{ */
7929#define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
7930#define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_SHIFT (0U)
7931#define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM(x) \
7932 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_SHIFT)) & \
7933 CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_MASK)
7934/*! @} */
7935
7936/*! @name DRAM_PLL_SSCG_CTRL - DRAM PLL PLL SSCG Control Register */
7937/*! @{ */
7938#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_MASK (0x3U)
7939#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_SHIFT (0U)
7940/*! SEL_PF
7941 * 0b00..Down spread
7942 * 0b01..Up spread
7943 * 0b1x..Center spread
7944 */
7945#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF(x) \
7946 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_SHIFT)) & \
7947 CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_MASK)
7948#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
7949#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
7950#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL(x) \
7951 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & \
7952 CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_MASK)
7953#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
7954#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
7955#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL(x) \
7956 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & \
7957 CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
7958#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
7959#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_SHIFT (31U)
7960#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN(x) \
7961 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_SHIFT)) & \
7962 CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_MASK)
7963/*! @} */
7964
7965/*! @name DRAM_PLL_MNIT_CTRL - DRAM PLL PLL Monitoring Control Register */
7966/*! @{ */
7967#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_MASK (0x7U)
7968#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_SHIFT (0U)
7969#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP(x) \
7970 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_MASK)
7971#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_MASK (0x8U)
7972#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_SHIFT (3U)
7973#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN(x) \
7974 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & \
7975 CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_MASK)
7976#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
7977#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_SHIFT (4U)
7978#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC(x) \
7979 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & \
7980 CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_MASK)
7981#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_MASK (0x4000U)
7982#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_SHIFT (14U)
7983#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN(x) \
7984 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & \
7985 CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_MASK)
7986#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_MASK (0x8000U)
7987#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_SHIFT (15U)
7988/*! FSEL
7989 * 0b0..FEED_OUT = FREF
7990 * 0b1..FEED_OUT = FEED
7991 */
7992#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL(x) \
7993 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_SHIFT)) & \
7994 CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_MASK)
7995#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
7996#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
7997/*! AFCINIT_SEL
7998 * 0b0..nominal delay
7999 * 0b1..nominal delay * 2
8000 */
8001#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL(x) \
8002 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \
8003 CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
8004#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
8005#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
8006#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) \
8007 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \
8008 CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
8009#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
8010#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
8011/*! PBIAS_CTRL
8012 * 0b0..0.50*VDD
8013 * 0b1..0.67*VDD
8014 */
8015#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL(x) \
8016 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \
8017 CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
8018#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
8019#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_SHIFT (20U)
8020#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL(x) \
8021 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & \
8022 CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_MASK)
8023/*! @} */
8024
8025/*! @name GPU_PLL_GEN_CTRL - GPU PLL General Function Control Register */
8026/*! @{ */
8027#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
8028#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
8029/*! PLL_REF_CLK_SEL
8030 * 0b00..SYS_XTAL
8031 * 0b01..PAD_CLK
8032 * 0b10..Reserved
8033 * 0b11..Reserved
8034 */
8035#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) \
8036 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \
8037 CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
8038#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
8039#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
8040/*! PAD_CLK_SEL
8041 * 0b00..CLKIN1 XOR CLKIN2
8042 * 0b01..CLKIN2
8043 * 0b10..CLKIN1
8044 * 0b11..Reserved
8045 */
8046#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL(x) \
8047 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \
8048 CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
8049#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
8050#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
8051#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS(x) \
8052 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & \
8053 CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_MASK)
8054#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
8055#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
8056#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) \
8057 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \
8058 CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
8059#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
8060#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
8061#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST(x) \
8062 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_SHIFT)) & \
8063 CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_MASK)
8064#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
8065#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
8066#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \
8067 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \
8068 CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
8069#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U)
8070#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U)
8071#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE(x) \
8072 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & \
8073 CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_MASK)
8074#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
8075#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
8076#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) \
8077 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \
8078 CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
8079#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
8080#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
8081/*! PLL_LOCK_SEL
8082 * 0b0..Using PLL maximum lock time
8083 * 0b1..Using PLL output lock
8084 */
8085#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL(x) \
8086 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & \
8087 CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK)
8088#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
8089#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
8090#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK(x) \
8091 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & \
8092 CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_MASK)
8093/*! @} */
8094
8095/*! @name GPU_PLL_FDIV_CTL0 - GPU PLL Divide and Fraction Data Control 0 Register */
8096/*! @{ */
8097#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
8098#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
8099#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV(x) \
8100 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \
8101 CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
8102#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
8103#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
8104#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV(x) \
8105 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \
8106 CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
8107#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
8108#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
8109#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) \
8110 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \
8111 CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
8112/*! @} */
8113
8114/*! @name GPU_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
8115/*! @{ */
8116#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
8117#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
8118#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN(x) \
8119 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & \
8120 CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK)
8121#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
8122#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
8123#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) \
8124 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & \
8125 CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK)
8126#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
8127#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
8128#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) \
8129 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & \
8130 CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK)
8131/*! @} */
8132
8133/*! @name GPU_PLL_MNIT_CTRL - PLL Monitoring Control Register */
8134/*! @{ */
8135#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_MASK (0x3U)
8136#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_SHIFT (0U)
8137#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP(x) \
8138 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_MASK)
8139#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U)
8140#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U)
8141#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN(x) \
8142 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & \
8143 CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_MASK)
8144#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U)
8145#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U)
8146#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC(x) \
8147 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & \
8148 CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_MASK)
8149#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U)
8150#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U)
8151#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN(x) \
8152 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & \
8153 CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_MASK)
8154#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_MASK (0x4000U)
8155#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_SHIFT (14U)
8156/*! FSEL
8157 * 0b0..FEED_OUT = FREF
8158 * 0b1..FEED_OUT = FEED
8159 */
8160#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL(x) \
8161 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_MASK)
8162#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
8163#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
8164/*! AFCINIT_SEL
8165 * 0b0..nominal delay
8166 * 0b1..nominal delay * 2
8167 */
8168#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL(x) \
8169 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \
8170 CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
8171#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
8172#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
8173#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) \
8174 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \
8175 CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
8176#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
8177#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
8178/*! PBIAS_CTRL
8179 * 0b0..0.50*VDD
8180 * 0b1..0.67*VDD
8181 */
8182#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL(x) \
8183 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \
8184 CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
8185#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
8186#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U)
8187#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL(x) \
8188 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & \
8189 CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_MASK)
8190#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
8191#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
8192#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK(x) \
8193 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & \
8194 CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_MASK)
8195#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U)
8196#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U)
8197#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN(x) \
8198 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & \
8199 CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_MASK)
8200/*! @} */
8201
8202/*! @name M7_ALT_PLL_GEN_CTRL - M7 Alternate PLL General Function Control Register */
8203/*! @{ */
8204#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
8205#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
8206/*! PLL_REF_CLK_SEL
8207 * 0b00..SYS_XTAL
8208 * 0b01..PAD_CLK
8209 * 0b10..Reserved
8210 * 0b11..Reserved
8211 */
8212#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) \
8213 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \
8214 CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
8215#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
8216#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
8217/*! PAD_CLK_SEL
8218 * 0b00..CLKIN1 XOR CLKIN2
8219 * 0b01..CLKIN2
8220 * 0b10..CLKIN1
8221 * 0b11..Reserved
8222 */
8223#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PAD_CLK_SEL(x) \
8224 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \
8225 CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
8226#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
8227#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
8228#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_BYPASS(x) \
8229 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & \
8230 CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_BYPASS_MASK)
8231#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
8232#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
8233#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) \
8234 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \
8235 CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
8236#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
8237#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
8238#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST(x) \
8239 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_SHIFT)) & \
8240 CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_MASK)
8241#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
8242#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
8243#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \
8244 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \
8245 CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
8246#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U)
8247#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U)
8248#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE(x) \
8249 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & \
8250 CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_MASK)
8251#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
8252#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
8253#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) \
8254 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \
8255 CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
8256#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
8257#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
8258/*! PLL_LOCK_SEL
8259 * 0b0..Using PLL maximum lock time
8260 * 0b1..Using PLL output lock
8261 */
8262#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SEL(x) \
8263 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & \
8264 CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK)
8265#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
8266#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
8267#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK(x) \
8268 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & \
8269 CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_MASK)
8270/*! @} */
8271
8272/*! @name M7_ALT_PLL_FDIV_CTL0 - M7 Alternate PLL Divide and Fraction Data Control 0 Register */
8273/*! @{ */
8274#define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
8275#define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
8276#define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_POST_DIV(x) \
8277 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \
8278 CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
8279#define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
8280#define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
8281#define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_PRE_DIV(x) \
8282 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \
8283 CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
8284#define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
8285#define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
8286#define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) \
8287 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \
8288 CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
8289/*! @} */
8290
8291/*! @name M7_ALT_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
8292/*! @{ */
8293#define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
8294#define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
8295#define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_IN(x) \
8296 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & \
8297 CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK)
8298#define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
8299#define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
8300#define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) \
8301 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & \
8302 CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK)
8303#define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
8304#define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
8305#define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) \
8306 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & \
8307 CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK)
8308/*! @} */
8309
8310/*! @name M7_ALT_PLL_MNIT_CTRL - PLL Monitoring Control Register */
8311/*! @{ */
8312#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_ICP_MASK (0x3U)
8313#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_ICP_SHIFT (0U)
8314#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_ICP(x) \
8315 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_ICP_SHIFT)) & \
8316 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_ICP_MASK)
8317#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U)
8318#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U)
8319#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_EN(x) \
8320 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & \
8321 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_EN_MASK)
8322#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U)
8323#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U)
8324#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_EXTAFC(x) \
8325 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & \
8326 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_EXTAFC_MASK)
8327#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U)
8328#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U)
8329#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FEED_EN(x) \
8330 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & \
8331 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FEED_EN_MASK)
8332#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FSEL_MASK (0x4000U)
8333#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FSEL_SHIFT (14U)
8334/*! FSEL
8335 * 0b0..FEED_OUT = FREF
8336 * 0b1..FEED_OUT = FEED
8337 */
8338#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FSEL(x) \
8339 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FSEL_SHIFT)) & \
8340 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FSEL_MASK)
8341#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
8342#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
8343/*! AFCINIT_SEL
8344 * 0b0..nominal delay
8345 * 0b1..nominal delay * 2
8346 */
8347#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFCINIT_SEL(x) \
8348 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \
8349 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
8350#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
8351#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
8352#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) \
8353 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \
8354 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
8355#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
8356#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
8357/*! PBIAS_CTRL
8358 * 0b0..0.50*VDD
8359 * 0b1..0.67*VDD
8360 */
8361#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL(x) \
8362 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \
8363 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
8364#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
8365#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U)
8366#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_SEL(x) \
8367 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & \
8368 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_SEL_MASK)
8369#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
8370#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
8371#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FOUT_MASK(x) \
8372 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & \
8373 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FOUT_MASK_MASK)
8374#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U)
8375#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U)
8376#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_LRD_EN(x) \
8377 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & \
8378 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_LRD_EN_MASK)
8379/*! @} */
8380
8381/*! @name ARM_PLL_GEN_CTRL - ARM PLL General Function Control Register */
8382/*! @{ */
8383#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
8384#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
8385/*! PLL_REF_CLK_SEL
8386 * 0b00..SYS_XTAL
8387 * 0b01..PAD_CLK
8388 * 0b10..Reserved
8389 * 0b11..Reserved
8390 */
8391#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) \
8392 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \
8393 CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
8394#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
8395#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
8396/*! PAD_CLK_SEL
8397 * 0b00..CLKIN1 XOR CLKIN2
8398 * 0b01..CLKIN2
8399 * 0b10..CLKIN1
8400 * 0b11..Reserved
8401 */
8402#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL(x) \
8403 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \
8404 CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
8405#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
8406#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
8407#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS(x) \
8408 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & \
8409 CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_MASK)
8410#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
8411#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
8412#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) \
8413 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \
8414 CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
8415#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
8416#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
8417#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST(x) \
8418 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_SHIFT)) & \
8419 CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_MASK)
8420#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
8421#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
8422#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \
8423 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \
8424 CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
8425#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U)
8426#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U)
8427#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE(x) \
8428 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & \
8429 CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_MASK)
8430#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
8431#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
8432#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) \
8433 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \
8434 CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
8435#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
8436#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
8437/*! PLL_LOCK_SEL
8438 * 0b0..Using PLL maximum lock time
8439 * 0b1..Using PLL output lock
8440 */
8441#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL(x) \
8442 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & \
8443 CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK)
8444#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
8445#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
8446#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK(x) \
8447 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & \
8448 CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_MASK)
8449/*! @} */
8450
8451/*! @name ARM_PLL_FDIV_CTL0 - ARM PLL Divide and Fraction Data Control 0 Register */
8452/*! @{ */
8453#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
8454#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
8455#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV(x) \
8456 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \
8457 CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
8458#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
8459#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
8460#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV(x) \
8461 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \
8462 CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
8463#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
8464#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
8465#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) \
8466 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \
8467 CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
8468/*! @} */
8469
8470/*! @name ARM_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
8471/*! @{ */
8472#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
8473#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
8474#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN(x) \
8475 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & \
8476 CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK)
8477#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
8478#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
8479#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) \
8480 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & \
8481 CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK)
8482#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
8483#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
8484#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) \
8485 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & \
8486 CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK)
8487/*! @} */
8488
8489/*! @name ARM_PLL_MNIT_CTRL - PLL Monitoring Control Register */
8490/*! @{ */
8491#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_MASK (0x3U)
8492#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_SHIFT (0U)
8493#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP(x) \
8494 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_MASK)
8495#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U)
8496#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U)
8497#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN(x) \
8498 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & \
8499 CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_MASK)
8500#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U)
8501#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U)
8502#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC(x) \
8503 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & \
8504 CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_MASK)
8505#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U)
8506#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U)
8507#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN(x) \
8508 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & \
8509 CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_MASK)
8510#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_MASK (0x4000U)
8511#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_SHIFT (14U)
8512/*! FSEL
8513 * 0b0..FEED_OUT = FREF
8514 * 0b1..FEED_OUT = FEED
8515 */
8516#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL(x) \
8517 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_MASK)
8518#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
8519#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
8520/*! AFCINIT_SEL
8521 * 0b0..nominal delay
8522 * 0b1..nominal delay * 2
8523 */
8524#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL(x) \
8525 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \
8526 CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
8527#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
8528#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
8529#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) \
8530 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \
8531 CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
8532#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
8533#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
8534/*! PBIAS_CTRL
8535 * 0b0..0.50*VDD
8536 * 0b1..0.67*VDD
8537 */
8538#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL(x) \
8539 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \
8540 CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
8541#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
8542#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U)
8543#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL(x) \
8544 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & \
8545 CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_MASK)
8546#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
8547#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
8548#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK(x) \
8549 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & \
8550 CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_MASK)
8551#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U)
8552#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U)
8553#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN(x) \
8554 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & \
8555 CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_MASK)
8556/*! @} */
8557
8558/*! @name SYS_PLL1_GEN_CTRL - SYS PLL1 General Function Control Register */
8559/*! @{ */
8560#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
8561#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
8562/*! PLL_REF_CLK_SEL
8563 * 0b00..SYS_XTAL
8564 * 0b01..PAD_CLK
8565 * 0b10..Reserved
8566 * 0b11..Reserved
8567 */
8568#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) \
8569 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \
8570 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
8571#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
8572#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
8573/*! PAD_CLK_SEL
8574 * 0b00..CLKIN1 XOR CLKIN2
8575 * 0b01..CLKIN2
8576 * 0b10..CLKIN1
8577 * 0b11..Reserved
8578 */
8579#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL(x) \
8580 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \
8581 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK)
8582#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
8583#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
8584#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS(x) \
8585 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & \
8586 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_MASK)
8587#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
8588#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
8589#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) \
8590 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \
8591 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
8592#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U)
8593#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U)
8594#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST(x) \
8595 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & \
8596 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_MASK)
8597#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
8598#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
8599#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \
8600 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \
8601 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
8602#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x800U)
8603#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (11U)
8604#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE(x) \
8605 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & \
8606 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_MASK)
8607#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK (0x1000U)
8608#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT (12U)
8609#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE(x) \
8610 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT)) & \
8611 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK)
8612#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_MASK (0x2000U)
8613#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_SHIFT (13U)
8614#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE(x) \
8615 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_SHIFT)) & \
8616 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_MASK)
8617#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK (0x4000U)
8618#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT (14U)
8619#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE(x) \
8620 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT)) & \
8621 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK)
8622#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_MASK (0x8000U)
8623#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_SHIFT (15U)
8624#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE(x) \
8625 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_SHIFT)) & \
8626 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_MASK)
8627#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK (0x10000U)
8628#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT (16U)
8629#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE(x) \
8630 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT)) & \
8631 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK)
8632#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_MASK (0x20000U)
8633#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_SHIFT (17U)
8634#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE(x) \
8635 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_SHIFT)) & \
8636 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_MASK)
8637#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK (0x40000U)
8638#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT (18U)
8639#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE(x) \
8640 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT)) & \
8641 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK)
8642#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_MASK (0x80000U)
8643#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_SHIFT (19U)
8644#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE(x) \
8645 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_SHIFT)) & \
8646 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_MASK)
8647#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK (0x100000U)
8648#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT (20U)
8649#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE(x) \
8650 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT)) & \
8651 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK)
8652#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_MASK (0x200000U)
8653#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_SHIFT (21U)
8654#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE(x) \
8655 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_SHIFT)) & \
8656 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_MASK)
8657#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK (0x400000U)
8658#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT (22U)
8659#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE(x) \
8660 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT)) & \
8661 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK)
8662#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_MASK (0x800000U)
8663#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_SHIFT (23U)
8664#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE(x) \
8665 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_SHIFT)) & \
8666 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_MASK)
8667#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK (0x1000000U)
8668#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT (24U)
8669#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE(x) \
8670 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT)) & \
8671 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK)
8672#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_MASK (0x2000000U)
8673#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_SHIFT (25U)
8674#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE(x) \
8675 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_SHIFT)) & \
8676 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_MASK)
8677#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK (0x4000000U)
8678#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT (26U)
8679#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE(x) \
8680 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT)) & \
8681 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK)
8682#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_MASK (0x8000000U)
8683#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_SHIFT (27U)
8684#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE(x) \
8685 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_SHIFT)) & \
8686 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_MASK)
8687#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
8688#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
8689#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) \
8690 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \
8691 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK)
8692#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
8693#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
8694/*! PLL_LOCK_SEL
8695 * 0b0..Using PLL maximum lock time
8696 * 0b1..Using PLL output lock
8697 */
8698#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL(x) \
8699 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & \
8700 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_MASK)
8701#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
8702#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U)
8703#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK(x) \
8704 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & \
8705 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_MASK)
8706/*! @} */
8707
8708/*! @name SYS_PLL1_FDIV_CTL0 - SYS PLL1 Divide and Fraction Data Control 0 Register */
8709/*! @{ */
8710#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
8711#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
8712#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV(x) \
8713 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \
8714 CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK)
8715#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
8716#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
8717#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) \
8718 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \
8719 CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK)
8720#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
8721#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
8722#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) \
8723 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \
8724 CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK)
8725/*! @} */
8726
8727/*! @name SYS_PLL1_LOCKD_CTRL - PLL Lock Detector Control Register */
8728/*! @{ */
8729#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
8730#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
8731#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN(x) \
8732 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & \
8733 CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_MASK)
8734#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
8735#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
8736#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT(x) \
8737 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & \
8738 CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_MASK)
8739#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
8740#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
8741#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY(x) \
8742 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & \
8743 CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_MASK)
8744/*! @} */
8745
8746/*! @name SYS_PLL1_MNIT_CTRL - PLL Monitoring Control Register */
8747/*! @{ */
8748#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_MASK (0x3U)
8749#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_SHIFT (0U)
8750#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP(x) \
8751 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_MASK)
8752#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_MASK (0x4U)
8753#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_SHIFT (2U)
8754#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN(x) \
8755 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & \
8756 CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_MASK)
8757#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_MASK (0xF8U)
8758#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_SHIFT (3U)
8759#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC(x) \
8760 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & \
8761 CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_MASK)
8762#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_MASK (0x2000U)
8763#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_SHIFT (13U)
8764#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN(x) \
8765 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & \
8766 CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_MASK)
8767#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_MASK (0x4000U)
8768#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_SHIFT (14U)
8769/*! FSEL
8770 * 0b0..FEED_OUT = FREF
8771 * 0b1..FEED_OUT = FEED
8772 */
8773#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL(x) \
8774 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_SHIFT)) & \
8775 CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_MASK)
8776#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
8777#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
8778/*! AFCINIT_SEL
8779 * 0b0..nominal delay
8780 * 0b1..nominal delay * 2
8781 */
8782#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL(x) \
8783 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \
8784 CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK)
8785#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
8786#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
8787#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) \
8788 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \
8789 CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
8790#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
8791#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
8792/*! PBIAS_CTRL
8793 * 0b0..0.50*VDD
8794 * 0b1..0.67*VDD
8795 */
8796#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL(x) \
8797 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \
8798 CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK)
8799#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
8800#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (19U)
8801#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL(x) \
8802 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & \
8803 CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_MASK)
8804#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
8805#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
8806#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK(x) \
8807 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_SHIFT)) & \
8808 CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_MASK)
8809#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_MASK (0x200000U)
8810#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_SHIFT (21U)
8811#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN(x) \
8812 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_SHIFT)) & \
8813 CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_MASK)
8814/*! @} */
8815
8816/*! @name SYS_PLL2_GEN_CTRL - SYS PLL2 General Function Control Register */
8817/*! @{ */
8818#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
8819#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
8820/*! PLL_REF_CLK_SEL
8821 * 0b00..SYS_XTAL
8822 * 0b01..PAD_CLK
8823 * 0b10..Reserved
8824 * 0b11..Reserved
8825 */
8826#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL(x) \
8827 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \
8828 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
8829#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
8830#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
8831/*! PAD_CLK_SEL
8832 * 0b00..CLKIN1 XOR CLKIN2
8833 * 0b01..CLKIN2
8834 * 0b10..CLKIN1
8835 * 0b11..Reserved
8836 */
8837#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL(x) \
8838 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \
8839 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK)
8840#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
8841#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
8842#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS(x) \
8843 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT)) & \
8844 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_MASK)
8845#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
8846#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
8847#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE(x) \
8848 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \
8849 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
8850#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_MASK (0x200U)
8851#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_SHIFT (9U)
8852#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST(x) \
8853 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_SHIFT)) & \
8854 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_MASK)
8855#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
8856#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
8857#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \
8858 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \
8859 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
8860#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_MASK (0x800U)
8861#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_SHIFT (11U)
8862#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE(x) \
8863 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_SHIFT)) & \
8864 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_MASK)
8865#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK (0x1000U)
8866#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT (12U)
8867#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE(x) \
8868 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT)) & \
8869 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK)
8870#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_MASK (0x2000U)
8871#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_SHIFT (13U)
8872#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE(x) \
8873 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_SHIFT)) & \
8874 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_MASK)
8875#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK (0x4000U)
8876#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT (14U)
8877#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE(x) \
8878 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT)) & \
8879 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK)
8880#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_MASK (0x8000U)
8881#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_SHIFT (15U)
8882#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE(x) \
8883 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_SHIFT)) & \
8884 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_MASK)
8885#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK (0x10000U)
8886#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT (16U)
8887#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE(x) \
8888 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT)) & \
8889 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK)
8890#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_MASK (0x20000U)
8891#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_SHIFT (17U)
8892#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE(x) \
8893 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_SHIFT)) & \
8894 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_MASK)
8895#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK (0x40000U)
8896#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT (18U)
8897#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE(x) \
8898 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT)) & \
8899 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK)
8900#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_MASK (0x80000U)
8901#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_SHIFT (19U)
8902#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE(x) \
8903 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_SHIFT)) & \
8904 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_MASK)
8905#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK (0x100000U)
8906#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT (20U)
8907#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE(x) \
8908 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT)) & \
8909 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK)
8910#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_MASK (0x200000U)
8911#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_SHIFT (21U)
8912#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE(x) \
8913 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_SHIFT)) & \
8914 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_MASK)
8915#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK (0x400000U)
8916#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT (22U)
8917#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE(x) \
8918 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT)) & \
8919 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK)
8920#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_MASK (0x800000U)
8921#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_SHIFT (23U)
8922#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE(x) \
8923 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_SHIFT)) & \
8924 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_MASK)
8925#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK (0x1000000U)
8926#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT (24U)
8927#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE(x) \
8928 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT)) & \
8929 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK)
8930#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_MASK (0x2000000U)
8931#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_SHIFT (25U)
8932#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE(x) \
8933 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_SHIFT)) & \
8934 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_MASK)
8935#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK (0x4000000U)
8936#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT (26U)
8937#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE(x) \
8938 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT)) & \
8939 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK)
8940#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_MASK (0x8000000U)
8941#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_SHIFT (27U)
8942#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE(x) \
8943 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_SHIFT)) & \
8944 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_MASK)
8945#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
8946#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
8947#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS(x) \
8948 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \
8949 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK)
8950#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
8951#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
8952/*! PLL_LOCK_SEL
8953 * 0b0..Using PLL maximum lock time
8954 * 0b1..Using PLL output lock
8955 */
8956#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL(x) \
8957 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & \
8958 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_MASK)
8959#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
8960#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SHIFT (31U)
8961#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK(x) \
8962 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SHIFT)) & \
8963 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_MASK)
8964/*! @} */
8965
8966/*! @name SYS_PLL2_FDIV_CTL0 - SYS PLL2 Divide and Fraction Data Control 0 Register */
8967/*! @{ */
8968#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
8969#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
8970#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV(x) \
8971 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \
8972 CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK)
8973#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
8974#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
8975#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV(x) \
8976 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \
8977 CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK)
8978#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
8979#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
8980#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV(x) \
8981 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \
8982 CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK)
8983/*! @} */
8984
8985/*! @name SYS_PLL2_LOCKD_CTRL - PLL Lock Detector Control Register */
8986/*! @{ */
8987#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
8988#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
8989#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN(x) \
8990 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & \
8991 CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_MASK)
8992#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
8993#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
8994#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT(x) \
8995 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & \
8996 CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_MASK)
8997#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
8998#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
8999#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY(x) \
9000 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & \
9001 CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_MASK)
9002/*! @} */
9003
9004/*! @name SYS_PLL2_MNIT_CTRL - PLL Monitoring Control Register */
9005/*! @{ */
9006#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_MASK (0x3U)
9007#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_SHIFT (0U)
9008#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP(x) \
9009 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_MASK)
9010#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_MASK (0x4U)
9011#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_SHIFT (2U)
9012#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN(x) \
9013 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_SHIFT)) & \
9014 CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_MASK)
9015#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_MASK (0xF8U)
9016#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_SHIFT (3U)
9017#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC(x) \
9018 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_SHIFT)) & \
9019 CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_MASK)
9020#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_MASK (0x2000U)
9021#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_SHIFT (13U)
9022#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN(x) \
9023 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_SHIFT)) & \
9024 CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_MASK)
9025#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_MASK (0x4000U)
9026#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_SHIFT (14U)
9027/*! FSEL
9028 * 0b0..FEED_OUT = FREF
9029 * 0b1..FEED_OUT = FEED
9030 */
9031#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL(x) \
9032 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_SHIFT)) & \
9033 CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_MASK)
9034#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
9035#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
9036/*! AFCINIT_SEL
9037 * 0b0..nominal delay
9038 * 0b1..nominal delay * 2
9039 */
9040#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL(x) \
9041 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \
9042 CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK)
9043#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
9044#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
9045#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN(x) \
9046 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \
9047 CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
9048#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
9049#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
9050/*! PBIAS_CTRL
9051 * 0b0..0.50*VDD
9052 * 0b1..0.67*VDD
9053 */
9054#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL(x) \
9055 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \
9056 CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK)
9057#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
9058#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_SHIFT (19U)
9059#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL(x) \
9060 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_SHIFT)) & \
9061 CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_MASK)
9062#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
9063#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
9064#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK(x) \
9065 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_SHIFT)) & \
9066 CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_MASK)
9067#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_MASK (0x200000U)
9068#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_SHIFT (21U)
9069#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN(x) \
9070 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_SHIFT)) & \
9071 CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_MASK)
9072/*! @} */
9073
9074/*! @name SYS_PLL3_GEN_CTRL - SYS PLL3 General Function Control Register */
9075/*! @{ */
9076#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
9077#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
9078/*! PLL_REF_CLK_SEL
9079 * 0b00..SYS_XTAL
9080 * 0b01..PAD_CLK
9081 * 0b10..Reserved
9082 * 0b11..Reserved
9083 */
9084#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL(x) \
9085 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \
9086 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
9087#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
9088#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
9089/*! PAD_CLK_SEL
9090 * 0b00..CLKIN1 XOR CLKIN2
9091 * 0b01..CLKIN2
9092 * 0b10..CLKIN1
9093 * 0b11..Reserved
9094 */
9095#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL(x) \
9096 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \
9097 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_MASK)
9098#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
9099#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
9100#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS(x) \
9101 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_SHIFT)) & \
9102 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_MASK)
9103#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
9104#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
9105#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE(x) \
9106 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \
9107 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
9108#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_MASK (0x200U)
9109#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_SHIFT (9U)
9110#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST(x) \
9111 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_SHIFT)) & \
9112 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_MASK)
9113#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
9114#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
9115#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \
9116 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \
9117 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
9118#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_MASK (0x800U)
9119#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_SHIFT (11U)
9120#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE(x) \
9121 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_SHIFT)) & \
9122 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_MASK)
9123#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
9124#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
9125#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS(x) \
9126 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \
9127 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_MASK)
9128#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
9129#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
9130/*! PLL_LOCK_SEL
9131 * 0b0..Using PLL maximum lock time
9132 * 0b1..Using PLL output lock
9133 */
9134#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL(x) \
9135 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & \
9136 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_MASK)
9137#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
9138#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SHIFT (31U)
9139#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK(x) \
9140 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SHIFT)) & \
9141 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_MASK)
9142/*! @} */
9143
9144/*! @name SYS_PLL3_FDIV_CTL0 - SYS PLL3 Divide and Fraction Data Control 0 Register */
9145/*! @{ */
9146#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
9147#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
9148#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV(x) \
9149 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \
9150 CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_MASK)
9151#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
9152#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
9153#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV(x) \
9154 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \
9155 CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_MASK)
9156#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
9157#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
9158#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV(x) \
9159 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \
9160 CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_MASK)
9161/*! @} */
9162
9163/*! @name SYS_PLL3_LOCKD_CTRL - PLL Lock Detector Control Register */
9164/*! @{ */
9165#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
9166#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
9167#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN(x) \
9168 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & \
9169 CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_MASK)
9170#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
9171#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
9172#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT(x) \
9173 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & \
9174 CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_MASK)
9175#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
9176#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
9177#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY(x) \
9178 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & \
9179 CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_MASK)
9180/*! @} */
9181
9182/*! @name SYS_PLL3_MNIT_CTRL - PLL Monitoring Control Register */
9183/*! @{ */
9184#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_MASK (0x3U)
9185#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_SHIFT (0U)
9186#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP(x) \
9187 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_MASK)
9188#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_MASK (0x4U)
9189#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_SHIFT (2U)
9190#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN(x) \
9191 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_SHIFT)) & \
9192 CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_MASK)
9193#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_MASK (0xF8U)
9194#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_SHIFT (3U)
9195#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC(x) \
9196 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_SHIFT)) & \
9197 CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_MASK)
9198#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_MASK (0x2000U)
9199#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_SHIFT (13U)
9200#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN(x) \
9201 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_SHIFT)) & \
9202 CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_MASK)
9203#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_MASK (0x4000U)
9204#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_SHIFT (14U)
9205/*! FSEL
9206 * 0b0..FEED_OUT = FREF
9207 * 0b1..FEED_OUT = FEED
9208 */
9209#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL(x) \
9210 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_SHIFT)) & \
9211 CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_MASK)
9212#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
9213#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
9214/*! AFCINIT_SEL
9215 * 0b0..nominal delay
9216 * 0b1..nominal delay * 2
9217 */
9218#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL(x) \
9219 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \
9220 CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_MASK)
9221#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
9222#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
9223#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN(x) \
9224 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \
9225 CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
9226#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
9227#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
9228/*! PBIAS_CTRL
9229 * 0b0..0.50*VDD
9230 * 0b1..0.67*VDD
9231 */
9232#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL(x) \
9233 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \
9234 CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_MASK)
9235#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
9236#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_SHIFT (19U)
9237#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL(x) \
9238 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_SHIFT)) & \
9239 CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_SEL_MASK)
9240#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
9241#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
9242#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK(x) \
9243 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_SHIFT)) & \
9244 CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FOUT_MASK_MASK)
9245#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_MASK (0x200000U)
9246#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_SHIFT (21U)
9247#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN(x) \
9248 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_SHIFT)) & \
9249 CCM_ANALOG_SYS_PLL3_MNIT_CTRL_LRD_EN_MASK)
9250/*! @} */
9251
9252/*! @name OSC_MISC_CFG - Osc Misc Configuration Register */
9253/*! @{ */
9254#define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK (0x1U)
9255#define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_SHIFT (0U)
9256/*! OSC_32K_SEL
9257 * 0b0..Divided by 24M clock
9258 * 0b1..32K Oscillator
9259 */
9260#define CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL(x) \
9261 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_SHIFT)) & \
9262 CCM_ANALOG_OSC_MISC_CFG_OSC_32K_SEL_MASK)
9263/*! @} */
9264
9265/*! @name ANAMIX_PLL_MNIT_CTL - PLL Clock Output for Test Enable and Select Register */
9266/*! @{ */
9267#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_MASK (0xFU)
9268#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_SHIFT (0U)
9269#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL(x) \
9270 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_SHIFT)) & \
9271 CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_DIV_VAL_MASK)
9272#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_MASK (0xF0U)
9273#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_SHIFT (4U)
9274#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL(x) \
9275 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_SHIFT)) & \
9276 CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_SEL_MASK)
9277#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_MASK (0x100U)
9278#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_SHIFT (8U)
9279#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE(x) \
9280 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_SHIFT)) & \
9281 CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT1_OUTPUT_CKE_MASK)
9282#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_MASK (0xF0000U)
9283#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_SHIFT (16U)
9284#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL(x) \
9285 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_SHIFT)) & \
9286 CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_DIV_VAL_MASK)
9287#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_MASK (0xF00000U)
9288#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_SHIFT (20U)
9289#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL(x) \
9290 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_SHIFT)) & \
9291 CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_SEL_MASK)
9292#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_MASK (0x1000000U)
9293#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_SHIFT (24U)
9294#define CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE(x) \
9295 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_SHIFT)) & \
9296 CCM_ANALOG_ANAMIX_PLL_MNIT_CTL_CLKOUT2_OUTPUT_CKE_MASK)
9297/*! @} */
9298
9299/*! @name DIGPROG - DIGPROG Register */
9300/*! @{ */
9301#define CCM_ANALOG_DIGPROG_DIGPROG_MINOR_MASK (0xFFU)
9302#define CCM_ANALOG_DIGPROG_DIGPROG_MINOR_SHIFT (0U)
9303#define CCM_ANALOG_DIGPROG_DIGPROG_MINOR(x) \
9304 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MINOR_SHIFT)) & CCM_ANALOG_DIGPROG_DIGPROG_MINOR_MASK)
9305#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_MASK (0xFF00U)
9306#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_SHIFT (8U)
9307#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER(x) \
9308 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_SHIFT)) & \
9309 CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_LOWER_MASK)
9310#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_MASK (0xFF0000U)
9311#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_SHIFT (16U)
9312#define CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER(x) \
9313 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_SHIFT)) & \
9314 CCM_ANALOG_DIGPROG_DIGPROG_MAJOR_UPPER_MASK)
9315/*! @} */
9316
9317/*!
9318 * @}
9319 */ /* end of group CCM_ANALOG_Register_Masks */
9320
9321/* CCM_ANALOG - Peripheral instance base addresses */
9322/** Peripheral CCM_ANALOG base address */
9323#define CCM_ANALOG_BASE (0x30360000u)
9324/** Peripheral CCM_ANALOG base pointer */
9325#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
9326/** Array initializer of CCM_ANALOG peripheral base addresses */
9327#define CCM_ANALOG_BASE_ADDRS \
9328 { \
9329 CCM_ANALOG_BASE \
9330 }
9331/** Array initializer of CCM_ANALOG peripheral base pointers */
9332#define CCM_ANALOG_BASE_PTRS \
9333 { \
9334 CCM_ANALOG \
9335 }
9336
9337/*!
9338 * @}
9339 */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */
9340
9341/* ----------------------------------------------------------------------------
9342 -- DDRC Peripheral Access Layer
9343 ---------------------------------------------------------------------------- */
9344
9345/*!
9346 * @addtogroup DDRC_Peripheral_Access_Layer DDRC Peripheral Access Layer
9347 * @{
9348 */
9349
9350/** DDRC - Register Layout Typedef */
9351typedef struct
9352{
9353 __IO uint32_t MSTR; /**< Master Register0, offset: 0x0 */
9354 __I uint32_t STAT; /**< Operating Mode Status Register, offset: 0x4 */
9355 __IO uint32_t MSTR1; /**< Operating Mode Status Register, offset: 0x8 */
9356 __IO uint32_t MRCTRL3; /**< Operating Mode Status Register, offset: 0xC */
9357 __IO uint32_t MRCTRL0; /**< Mode Register Read/Write Control Register 0., offset: 0x10 */
9358 __IO uint32_t MRCTRL1; /**< Mode Register Read/Write Control Register 1, offset: 0x14 */
9359 __I uint32_t MRSTAT; /**< Mode Register Read/Write Status Register, offset: 0x18 */
9360 __IO uint32_t MRCTRL2; /**< Mode Register Read/Write Control Register 2, offset: 0x1C */
9361 __IO uint32_t DERATEEN; /**< Temperature Derate Enable Register, offset: 0x20 */
9362 __IO uint32_t DERATEINT; /**< Temperature Derate Interval Register, offset: 0x24 */
9363 uint8_t RESERVED_0[8];
9364 __IO uint32_t PWRCTL; /**< Low Power Control Register, offset: 0x30 */
9365 __IO uint32_t PWRTMG; /**< Low Power Timing Register, offset: 0x34 */
9366 __IO uint32_t HWLPCTL; /**< Hardware Low Power Control Register, offset: 0x38 */
9367 uint8_t RESERVED_1[20];
9368 __IO uint32_t RFSHCTL0; /**< Refresh Control Register 0, offset: 0x50 */
9369 __IO uint32_t RFSHCTL1; /**< Refresh Control Register 1, offset: 0x54 */
9370 uint8_t RESERVED_2[8];
9371 __IO uint32_t RFSHCTL3; /**< Refresh Control Register 3, offset: 0x60 */
9372 __IO uint32_t RFSHTMG; /**< Refresh Timing Register, offset: 0x64 */
9373 uint8_t RESERVED_3[104];
9374 __IO uint32_t INIT0; /**< SDRAM Initialization Register 0, offset: 0xD0 */
9375 __IO uint32_t INIT1; /**< SDRAM Initialization Register 1, offset: 0xD4 */
9376 __IO uint32_t INIT2; /**< SDRAM Initialization Register 2, offset: 0xD8 */
9377 __IO uint32_t INIT3; /**< SDRAM Initialization Register 3, offset: 0xDC */
9378 __IO uint32_t INIT4; /**< SDRAM Initialization Register 4, offset: 0xE0 */
9379 __IO uint32_t INIT5; /**< SDRAM Initialization Register 5, offset: 0xE4 */
9380 __IO uint32_t INIT6; /**< SDRAM Initialization Register 6, offset: 0xE8 */
9381 __IO uint32_t INIT7; /**< SDRAM Initialization Register 7, offset: 0xEC */
9382 __IO uint32_t DIMMCTL; /**< DIMM Control Register, offset: 0xF0 */
9383 __IO uint32_t RANKCTL; /**< Rank Control Register, offset: 0xF4 */
9384 uint8_t RESERVED_4[8];
9385 __IO uint32_t DRAMTMG0; /**< SDRAM Timing Register 0, offset: 0x100 */
9386 __IO uint32_t DRAMTMG1; /**< SDRAM Timing Register 1, offset: 0x104 */
9387 __IO uint32_t DRAMTMG2; /**< SDRAM Timing Register 2, offset: 0x108 */
9388 __IO uint32_t DRAMTMG3; /**< SDRAM Timing Register 3, offset: 0x10C */
9389 __IO uint32_t DRAMTMG4; /**< SDRAM Timing Register 4, offset: 0x110 */
9390 __IO uint32_t DRAMTMG5; /**< SDRAM Timing Register 5, offset: 0x114 */
9391 __IO uint32_t DRAMTMG6; /**< SDRAM Timing Register 6, offset: 0x118 */
9392 __IO uint32_t DRAMTMG7; /**< SDRAM Timing Register 7, offset: 0x11C */
9393 __IO uint32_t DRAMTMG8; /**< SDRAM Timing Register 8, offset: 0x120 */
9394 __IO uint32_t DRAMTMG9; /**< SDRAM Timing Register 9, offset: 0x124 */
9395 __IO uint32_t DRAMTMG10; /**< SDRAM Timing Register 10, offset: 0x128 */
9396 __IO uint32_t DRAMTMG11; /**< SDRAM Timing Register 11, offset: 0x12C */
9397 __IO uint32_t DRAMTMG12; /**< SDRAM Timing Register 12, offset: 0x130 */
9398 __IO uint32_t DRAMTMG13; /**< SDRAM Timing Register 13, offset: 0x134 */
9399 __IO uint32_t DRAMTMG14; /**< SDRAM Timing Register 14, offset: 0x138 */
9400 __IO uint32_t DRAMTMG15; /**< SDRAM Timing Register 15, offset: 0x13C */
9401 uint8_t RESERVED_5[64];
9402 __IO uint32_t ZQCTL0; /**< ZQ Control Register 0, offset: 0x180 */
9403 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */
9404 __IO uint32_t ZQCTL2; /**< ZQ Control Register 2, offset: 0x188 */
9405 __I uint32_t ZQSTAT; /**< ZQ Status Register, offset: 0x18C */
9406 __IO uint32_t DFITMG0; /**< DFI Timing Register 0, offset: 0x190 */
9407 __IO uint32_t DFITMG1; /**< DFI Timing Register 1, offset: 0x194 */
9408 __IO uint32_t DFILPCFG0; /**< DFI Low Power Configuration Register 0, offset: 0x198 */
9409 __IO uint32_t DFILPCFG1; /**< DFI Low Power Configuration Register 1, offset: 0x19C */
9410 __IO uint32_t DFIUPD0; /**< DFI Update Register 0, offset: 0x1A0 */
9411 __IO uint32_t DFIUPD1; /**< DFI Update Register 1, offset: 0x1A4 */
9412 __IO uint32_t DFIUPD2; /**< DFI Update Register 2, offset: 0x1A8 */
9413 uint8_t RESERVED_6[4];
9414 __IO uint32_t DFIMISC; /**< DFI Miscellaneous Control Register, offset: 0x1B0 */
9415 __IO uint32_t DFITMG2; /**< DFI Timing Register 2, offset: 0x1B4 */
9416 __IO uint32_t DFITMG3; /**< DFI Timing Register 3, offset: 0x1B8 */
9417 __I uint32_t DFISTAT; /**< DFI Status Register, offset: 0x1BC */
9418 __IO uint32_t DBICTL; /**< DM/DBI Control Register, offset: 0x1C0 */
9419 uint8_t RESERVED_7[60];
9420 __IO uint32_t ADDRMAP0; /**< Address Map Register 0, offset: 0x200 */
9421 __IO uint32_t ADDRMAP1; /**< Address Map Register 1, offset: 0x204 */
9422 __IO uint32_t ADDRMAP2; /**< Address Map Register 2, offset: 0x208 */
9423 __IO uint32_t ADDRMAP3; /**< Address Map Register 3, offset: 0x20C */
9424 __IO uint32_t ADDRMAP4; /**< Address Map Register 4, offset: 0x210 */
9425 __IO uint32_t ADDRMAP5; /**< Address Map Register 5, offset: 0x214 */
9426 __IO uint32_t ADDRMAP6; /**< Address Map Register 6, offset: 0x218 */
9427 __IO uint32_t ADDRMAP7; /**< Address Map Register 7, offset: 0x21C */
9428 __IO uint32_t ADDRMAP8; /**< Address Map Register 8, offset: 0x220 */
9429 __IO uint32_t ADDRMAP9; /**< Address Map Register 9, offset: 0x224 */
9430 __IO uint32_t ADDRMAP10; /**< Address Map Register 10, offset: 0x228 */
9431 __IO uint32_t ADDRMAP11; /**< Address Map Register 11, offset: 0x22C */
9432 uint8_t RESERVED_8[16];
9433 __IO uint32_t ODTCFG; /**< ODT Configuration Register, offset: 0x240 */
9434 __IO uint32_t ODTMAP; /**< ODT/Rank Map Register, offset: 0x244 */
9435 uint8_t RESERVED_9[8];
9436 __IO uint32_t SCHED; /**< Scheduler Control Register, offset: 0x250 */
9437 __IO uint32_t SCHED1; /**< Scheduler Control Register 1, offset: 0x254 */
9438 uint8_t RESERVED_10[4];
9439 __IO uint32_t PERFHPR1; /**< High Priority Read CAM Register 1, offset: 0x25C */
9440 uint8_t RESERVED_11[4];
9441 __IO uint32_t PERFLPR1; /**< Low Priority Read CAM Register 1, offset: 0x264 */
9442 uint8_t RESERVED_12[4];
9443 __IO uint32_t PERFWR1; /**< Write CAM Register 1, offset: 0x26C */
9444 uint8_t RESERVED_13[144];
9445 __IO uint32_t DBG0; /**< Debug Register 0, offset: 0x300 */
9446 __IO uint32_t DBG1; /**< Debug Register 1, offset: 0x304 */
9447 __I uint32_t DBGCAM; /**< CAM Debug Register, offset: 0x308 */
9448 __IO uint32_t DBGCMD; /**< Command Debug Register, offset: 0x30C */
9449 __I uint32_t DBGSTAT; /**< Status Debug Register, offset: 0x310 */
9450 uint8_t RESERVED_14[12];
9451 __IO uint32_t SWCTL; /**< Software Register Programming Control Enable, offset: 0x320 */
9452 __I uint32_t SWSTAT; /**< Software Register Programming Control Status, offset: 0x324 */
9453 uint8_t RESERVED_15[68];
9454 __IO uint32_t POISONCFG; /**< AXI Poison Configuration Register., offset: 0x36C */
9455 __I uint32_t POISONSTAT; /**< AXI Poison Status Register, offset: 0x370 */
9456 uint8_t RESERVED_16[136];
9457 __I uint32_t PSTAT; /**< Port Status Register, offset: 0x3FC */
9458 __IO uint32_t PCCFG; /**< Port Common Configuration Register, offset: 0x400 */
9459 __IO uint32_t PCFGR_0; /**< Port n Configuration Read Register, offset: 0x404 */
9460 __IO uint32_t PCFGW_0; /**< Port n Configuration Write Register, offset: 0x408 */
9461 uint8_t RESERVED_17[132];
9462 __IO uint32_t PCTRL_0; /**< Port n Control Register, offset: 0x490 */
9463 __IO uint32_t PCFGQOS0_0; /**< Port n Read QoS Configuration Register 0, offset: 0x494 */
9464 __IO uint32_t PCFGQOS1_0; /**< Port n Read QoS Configuration Register 1, offset: 0x498 */
9465 __IO uint32_t PCFGWQOS0_0; /**< Port n Write QoS Configuration Register 0, offset: 0x49C */
9466 __IO uint32_t PCFGWQOS1_0; /**< Port n Write QoS Configuration Register 1, offset: 0x4A0 */
9467 uint8_t RESERVED_18[7036];
9468 __IO uint32_t DERATEEN_SHADOW; /**< [SHADOW] Temperature Derate Enable Register, offset: 0x2020 */
9469 __IO uint32_t DERATEINT_SHADOW; /**< [SHADOW] Temperature Derate Interval Register, offset: 0x2024 */
9470 uint8_t RESERVED_19[40];
9471 __IO uint32_t RFSHCTL0_SHADOW; /**< [SHADOW] Refresh Control Register 0, offset: 0x2050 */
9472 uint8_t RESERVED_20[16];
9473 __IO uint32_t RFSHTMG_SHADOW; /**< [SHADOW] Refresh Timing Register, offset: 0x2064 */
9474 uint8_t RESERVED_21[116];
9475 __IO uint32_t INIT3_SHADOW; /**< [SHADOW] SDRAM Initialization Register 3, offset: 0x20DC */
9476 __IO uint32_t INIT4_SHADOW; /**< [SHADOW] SDRAM Initialization Register 4, offset: 0x20E0 */
9477 uint8_t RESERVED_22[4];
9478 __IO uint32_t INIT6_SHADOW; /**< [SHADOW] SDRAM Initialization Register 6, offset: 0x20E8 */
9479 __IO uint32_t INIT7_SHADOW; /**< [SHADOW] SDRAM Initialization Register 7, offset: 0x20EC */
9480 uint8_t RESERVED_23[16];
9481 __IO uint32_t DRAMTMG0_SHADOW; /**< [SHADOW] SDRAM Timing Register 0, offset: 0x2100 */
9482 __IO uint32_t DRAMTMG1_SHADOW; /**< [SHADOW] SDRAM Timing Register 1, offset: 0x2104 */
9483 __IO uint32_t DRAMTMG2_SHADOW; /**< [SHADOW] SDRAM Timing Register 2, offset: 0x2108 */
9484 __IO uint32_t DRAMTMG3_SHADOW; /**< [SHADOW] SDRAM Timing Register 3, offset: 0x210C */
9485 __IO uint32_t DRAMTMG4_SHADOW; /**< [SHADOW] SDRAM Timing Register 4, offset: 0x2110 */
9486 __IO uint32_t DRAMTMG5_SHADOW; /**< [SHADOW] SDRAM Timing Register 5, offset: 0x2114 */
9487 __IO uint32_t DRAMTMG6_SHADOW; /**< [SHADOW] SDRAM Timing Register 6, offset: 0x2118 */
9488 __IO uint32_t DRAMTMG7_SHADOW; /**< [SHADOW] SDRAM Timing Register 7, offset: 0x211C */
9489 __IO uint32_t DRAMTMG8_SHADOW; /**< [SHADOW] SDRAM Timing Register 8, offset: 0x2120 */
9490 __IO uint32_t DRAMTMG9_SHADOW; /**< [SHADOW] SDRAM Timing Register 9, offset: 0x2124 */
9491 __IO uint32_t DRAMTMG10_SHADOW; /**< [SHADOW] SDRAM Timing Register 10, offset: 0x2128 */
9492 __IO uint32_t DRAMTMG11_SHADOW; /**< [SHADOW] SDRAM Timing Register 11, offset: 0x212C */
9493 __IO uint32_t DRAMTMG12_SHADOW; /**< [SHADOW] SDRAM Timing Register 12, offset: 0x2130 */
9494 __IO uint32_t DRAMTMG13_SHADOW; /**< [SHADOW] SDRAM Timing Register 13, offset: 0x2134 */
9495 __IO uint32_t DRAMTMG14_SHADOW; /**< [SHADOW] SDRAM Timing Register 14, offset: 0x2138 */
9496 __IO uint32_t DRAMTMG15_SHADOW; /**< [SHADOW] SDRAM Timing Register 15, offset: 0x213C */
9497 uint8_t RESERVED_24[64];
9498 __IO uint32_t ZQCTL0_SHADOW; /**< [SHADOW] ZQ Control Register 0, offset: 0x2180 */
9499 uint8_t RESERVED_25[12];
9500 __IO uint32_t DFITMG0_SHADOW; /**< [SHADOW] DFI Timing Register 0, offset: 0x2190 */
9501 __IO uint32_t DFITMG1_SHADOW; /**< [SHADOW] DFI Timing Register 1, offset: 0x2194 */
9502 uint8_t RESERVED_26[28];
9503 __IO uint32_t DFITMG2_SHADOW; /**< [SHADOW] DFI Timing Register 2, offset: 0x21B4 */
9504 __IO uint32_t DFITMG3_SHADOW; /**< [SHADOW] DFI Timing Register 3, offset: 0x21B8 */
9505 uint8_t RESERVED_27[132];
9506 __IO uint32_t ODTCFG_SHADOW; /**< [SHADOW] ODT Configuration Register, offset: 0x2240 */
9507} DDRC_Type;
9508
9509/* ----------------------------------------------------------------------------
9510 -- DDRC Register Masks
9511 ---------------------------------------------------------------------------- */
9512
9513/*!
9514 * @addtogroup DDRC_Register_Masks DDRC Register Masks
9515 * @{
9516 */
9517
9518/*! @name MSTR - Master Register0 */
9519/*! @{ */
9520#define DDRC_MSTR_ddr3_MASK (0x1U)
9521#define DDRC_MSTR_ddr3_SHIFT (0U)
9522#define DDRC_MSTR_ddr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_ddr3_SHIFT)) & DDRC_MSTR_ddr3_MASK)
9523#define DDRC_MSTR_lpddr2_MASK (0x4U)
9524#define DDRC_MSTR_lpddr2_SHIFT (2U)
9525#define DDRC_MSTR_lpddr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr2_SHIFT)) & DDRC_MSTR_lpddr2_MASK)
9526#define DDRC_MSTR_lpddr3_MASK (0x8U)
9527#define DDRC_MSTR_lpddr3_SHIFT (3U)
9528#define DDRC_MSTR_lpddr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr3_SHIFT)) & DDRC_MSTR_lpddr3_MASK)
9529#define DDRC_MSTR_ddr4_MASK (0x10U)
9530#define DDRC_MSTR_ddr4_SHIFT (4U)
9531#define DDRC_MSTR_ddr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_ddr4_SHIFT)) & DDRC_MSTR_ddr4_MASK)
9532#define DDRC_MSTR_lpddr4_MASK (0x20U)
9533#define DDRC_MSTR_lpddr4_SHIFT (5U)
9534#define DDRC_MSTR_lpddr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr4_SHIFT)) & DDRC_MSTR_lpddr4_MASK)
9535#define DDRC_MSTR_burstchop_MASK (0x200U)
9536#define DDRC_MSTR_burstchop_SHIFT (9U)
9537#define DDRC_MSTR_burstchop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_burstchop_SHIFT)) & DDRC_MSTR_burstchop_MASK)
9538#define DDRC_MSTR_en_2t_timing_mode_MASK (0x400U)
9539#define DDRC_MSTR_en_2t_timing_mode_SHIFT (10U)
9540#define DDRC_MSTR_en_2t_timing_mode(x) \
9541 (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_en_2t_timing_mode_SHIFT)) & DDRC_MSTR_en_2t_timing_mode_MASK)
9542#define DDRC_MSTR_geardown_mode_MASK (0x800U)
9543#define DDRC_MSTR_geardown_mode_SHIFT (11U)
9544#define DDRC_MSTR_geardown_mode(x) \
9545 (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_geardown_mode_SHIFT)) & DDRC_MSTR_geardown_mode_MASK)
9546#define DDRC_MSTR_data_bus_width_MASK (0x3000U)
9547#define DDRC_MSTR_data_bus_width_SHIFT (12U)
9548#define DDRC_MSTR_data_bus_width(x) \
9549 (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_data_bus_width_SHIFT)) & DDRC_MSTR_data_bus_width_MASK)
9550#define DDRC_MSTR_dll_off_mode_MASK (0x8000U)
9551#define DDRC_MSTR_dll_off_mode_SHIFT (15U)
9552#define DDRC_MSTR_dll_off_mode(x) \
9553 (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_dll_off_mode_SHIFT)) & DDRC_MSTR_dll_off_mode_MASK)
9554#define DDRC_MSTR_burst_rdwr_MASK (0xF0000U)
9555#define DDRC_MSTR_burst_rdwr_SHIFT (16U)
9556/*! burst_rdwr - SDRAM burst length used
9557 * 0b0001..Burst length of 2 (only supported for mDDR)
9558 * 0b0010..Burst length of 4
9559 * 0b0100..Burst length of 8
9560 * 0b1000..Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4)
9561 */
9562#define DDRC_MSTR_burst_rdwr(x) \
9563 (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_burst_rdwr_SHIFT)) & DDRC_MSTR_burst_rdwr_MASK)
9564#define DDRC_MSTR_frequency_ratio_MASK (0x400000U)
9565#define DDRC_MSTR_frequency_ratio_SHIFT (22U)
9566/*! frequency_ratio - Selects the Frequency Ratio
9567 * 0b0..1:2 Mode
9568 * 0b1..1:1 Mode
9569 */
9570#define DDRC_MSTR_frequency_ratio(x) \
9571 (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_frequency_ratio_SHIFT)) & DDRC_MSTR_frequency_ratio_MASK)
9572#define DDRC_MSTR_active_ranks_MASK (0x3000000U)
9573#define DDRC_MSTR_active_ranks_SHIFT (24U)
9574#define DDRC_MSTR_active_ranks(x) \
9575 (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_active_ranks_SHIFT)) & DDRC_MSTR_active_ranks_MASK)
9576#define DDRC_MSTR_frequency_mode_MASK (0x20000000U)
9577#define DDRC_MSTR_frequency_mode_SHIFT (29U)
9578/*! frequency_mode - Choose which registers are used.
9579 * 0b0..Original Registers
9580 * 0b1..Shadow Registers
9581 */
9582#define DDRC_MSTR_frequency_mode(x) \
9583 (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_frequency_mode_SHIFT)) & DDRC_MSTR_frequency_mode_MASK)
9584#define DDRC_MSTR_device_config_MASK (0xC0000000U)
9585#define DDRC_MSTR_device_config_SHIFT (30U)
9586/*! device_config - Indicates the configuration of the device used in the system.
9587 * 0b00..x4 device
9588 * 0b01..x8 device
9589 * 0b10..x16 device
9590 * 0b11..x32 device
9591 */
9592#define DDRC_MSTR_device_config(x) \
9593 (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_device_config_SHIFT)) & DDRC_MSTR_device_config_MASK)
9594/*! @} */
9595
9596/*! @name STAT - Operating Mode Status Register */
9597/*! @{ */
9598#define DDRC_STAT_operating_mode_MASK (0x7U)
9599#define DDRC_STAT_operating_mode_SHIFT (0U)
9600#define DDRC_STAT_operating_mode(x) \
9601 (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_operating_mode_SHIFT)) & DDRC_STAT_operating_mode_MASK)
9602#define DDRC_STAT_selfref_type_MASK (0x30U)
9603#define DDRC_STAT_selfref_type_SHIFT (4U)
9604/*! selfref_type - Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if
9605 * it was under Automatic Self Refresh control only or not.
9606 * 0b00..SDRAM is not in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by
9607 * CRCPARCTRL1.crc_parity_retry_enable, this also indicates SRE command is still in parity error window or retry
9608 * is in-progress. 0b11..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was caused by
9609 * Automatic Self Refresh only. If retry is enabled, this guarantees SRE command is executed correctly without parity
9610 * error. 0b10..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was not caused solely under
9611 * Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software
9612 * (reg_ddrc_selfref_sw). If retry is enabled, this guarantees SRE command is executed correctly without parity
9613 */
9614#define DDRC_STAT_selfref_type(x) \
9615 (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_selfref_type_SHIFT)) & DDRC_STAT_selfref_type_MASK)
9616#define DDRC_STAT_selfref_state_MASK (0x300U)
9617#define DDRC_STAT_selfref_state_SHIFT (8U)
9618/*! selfref_state - Self refresh state. This indicates self refresh or self refresh power down state
9619 * for LPDDR4. This register is used for frequency change and MRR/MRW access during self refresh.
9620 * 0b00..SDRAM is not in Self Refresh.
9621 * 0b01..Self refresh 1
9622 * 0b10..Self refresh power down
9623 * 0b11..Self refresh
9624 */
9625#define DDRC_STAT_selfref_state(x) \
9626 (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_selfref_state_SHIFT)) & DDRC_STAT_selfref_state_MASK)
9627/*! @} */
9628
9629/*! @name MSTR1 - Operating Mode Status Register */
9630/*! @{ */
9631#define DDRC_MSTR1_rank_tmgreg_sel_MASK (0x3U)
9632#define DDRC_MSTR1_rank_tmgreg_sel_SHIFT (0U)
9633/*! rank_tmgreg_sel - rank_tmgreg_sel
9634 * 0b00..USE DRAMTMGx registers for the rank
9635 * 0b01..USE MRAMTMGx registers for the rank
9636 */
9637#define DDRC_MSTR1_rank_tmgreg_sel(x) \
9638 (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR1_rank_tmgreg_sel_SHIFT)) & DDRC_MSTR1_rank_tmgreg_sel_MASK)
9639#define DDRC_MSTR1_alt_addrmap_en_MASK (0x10000U)
9640#define DDRC_MSTR1_alt_addrmap_en_SHIFT (16U)
9641/*! alt_addrmap_en - Enable Alternative Address Map
9642 * 0b0..Disable Alternative Address Map
9643 * 0b1..Enable Alternative Address Map
9644 */
9645#define DDRC_MSTR1_alt_addrmap_en(x) \
9646 (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR1_alt_addrmap_en_SHIFT)) & DDRC_MSTR1_alt_addrmap_en_MASK)
9647/*! @} */
9648
9649/*! @name MRCTRL3 - Operating Mode Status Register */
9650/*! @{ */
9651#define DDRC_MRCTRL3_mr_rank_sel_MASK (0x3U)
9652#define DDRC_MRCTRL3_mr_rank_sel_SHIFT (0U)
9653#define DDRC_MRCTRL3_mr_rank_sel(x) \
9654 (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL3_mr_rank_sel_SHIFT)) & DDRC_MRCTRL3_mr_rank_sel_MASK)
9655/*! @} */
9656
9657/*! @name MRCTRL0 - Mode Register Read/Write Control Register 0. */
9658/*! @{ */
9659#define DDRC_MRCTRL0_mr_type_MASK (0x1U)
9660#define DDRC_MRCTRL0_mr_type_SHIFT (0U)
9661/*! mr_type - Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4.
9662 * 0b0..Write
9663 * 0b1..Read
9664 */
9665#define DDRC_MRCTRL0_mr_type(x) \
9666 (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_type_SHIFT)) & DDRC_MRCTRL0_mr_type_MASK)
9667#define DDRC_MRCTRL0_mpr_en_MASK (0x2U)
9668#define DDRC_MRCTRL0_mpr_en_SHIFT (1U)
9669/*! mpr_en - Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4).
9670 * 0b0..MRS
9671 * 0b1..WR/RD for MPR
9672 */
9673#define DDRC_MRCTRL0_mpr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mpr_en_SHIFT)) & DDRC_MRCTRL0_mpr_en_MASK)
9674#define DDRC_MRCTRL0_pda_en_MASK (0x4U)
9675#define DDRC_MRCTRL0_pda_en_SHIFT (2U)
9676/*! pda_en - Indicates whether the mode register operation is MRS in PDA mode or not. Note that when
9677 * pba_mode=1, PBA access is initiated instead of PDA access.
9678 * 0b0..MRS
9679 * 0b1..MRS in Per DRAM Addressability
9680 */
9681#define DDRC_MRCTRL0_pda_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_pda_en_SHIFT)) & DDRC_MRCTRL0_pda_en_MASK)
9682#define DDRC_MRCTRL0_sw_init_int_MASK (0x8U)
9683#define DDRC_MRCTRL0_sw_init_int_SHIFT (3U)
9684/*! sw_init_int - Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before
9685 * automatic SDRAM initialization routine or not. For DDR4, this bit can be used to initialize the
9686 * DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit can be used to
9687 * program additional mode registers before automatic SDRAM initialization if necessary. In LPDDR4
9688 * independent channel mode, note that this must be programmed to both channels beforehand. Note that
9689 * this must be cleared to 0 after completing Software operation. Otherwise, SDRAM
9690 * initialization routine will not re-start.
9691 * 0b0..Software intervention is not allowed
9692 * 0b1..Software intervention is allowed
9693 */
9694#define DDRC_MRCTRL0_sw_init_int(x) \
9695 (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_sw_init_int_SHIFT)) & DDRC_MRCTRL0_sw_init_int_MASK)
9696#define DDRC_MRCTRL0_mr_rank_MASK (0x30U)
9697#define DDRC_MRCTRL0_mr_rank_SHIFT (4U)
9698#define DDRC_MRCTRL0_mr_rank(x) \
9699 (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_rank_SHIFT)) & DDRC_MRCTRL0_mr_rank_MASK)
9700#define DDRC_MRCTRL0_mr_addr_MASK (0xF000U)
9701#define DDRC_MRCTRL0_mr_addr_SHIFT (12U)
9702/*! mr_addr - Address of the mode register that is to be written to.
9703 * 0b0000..MR0
9704 * 0b0001..MR1
9705 * 0b0010..MR2
9706 * 0b0011..MR3
9707 * 0b0100..MR4
9708 * 0b0101..MR5
9709 * 0b0110..MR6
9710 * 0b0111..MR7
9711 */
9712#define DDRC_MRCTRL0_mr_addr(x) \
9713 (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_addr_SHIFT)) & DDRC_MRCTRL0_mr_addr_MASK)
9714#define DDRC_MRCTRL0_pba_mode_MASK (0x40000000U)
9715#define DDRC_MRCTRL0_pba_mode_SHIFT (30U)
9716#define DDRC_MRCTRL0_pba_mode(x) \
9717 (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_pba_mode_SHIFT)) & DDRC_MRCTRL0_pba_mode_MASK)
9718#define DDRC_MRCTRL0_mr_wr_MASK (0x80000000U)
9719#define DDRC_MRCTRL0_mr_wr_SHIFT (31U)
9720#define DDRC_MRCTRL0_mr_wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_wr_SHIFT)) & DDRC_MRCTRL0_mr_wr_MASK)
9721/*! @} */
9722
9723/*! @name MRCTRL1 - Mode Register Read/Write Control Register 1 */
9724/*! @{ */
9725#define DDRC_MRCTRL1_mr_data_MASK (0x3FFFFU)
9726#define DDRC_MRCTRL1_mr_data_SHIFT (0U)
9727#define DDRC_MRCTRL1_mr_data(x) \
9728 (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL1_mr_data_SHIFT)) & DDRC_MRCTRL1_mr_data_MASK)
9729/*! @} */
9730
9731/*! @name MRSTAT - Mode Register Read/Write Status Register */
9732/*! @{ */
9733#define DDRC_MRSTAT_mr_wr_busy_MASK (0x1U)
9734#define DDRC_MRSTAT_mr_wr_busy_SHIFT (0U)
9735/*! mr_wr_busy - The SoC core may initiate a MR write operation only if this signal is low. This
9736 * signal goes high in the clock after the DDRC accepts the MRW/MRR request. It goes low when the
9737 * MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when
9738 * 'MRSTAT.mr_wr_busy' is high.
9739 * 0b0..Indicates that the SoC core can initiate a mode register write operation
9740 * 0b1..Indicates that mode register write operation is in progress
9741 */
9742#define DDRC_MRSTAT_mr_wr_busy(x) \
9743 (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_mr_wr_busy_SHIFT)) & DDRC_MRSTAT_mr_wr_busy_MASK)
9744#define DDRC_MRSTAT_pda_done_MASK (0x100U)
9745#define DDRC_MRSTAT_pda_done_SHIFT (8U)
9746/*! pda_done - The SoC core may initiate a MR write operation in PDA/PBA mode only if this signal is
9747 * low. This signal goes high when three consecutive MRS commands related to the PDA/PBA mode
9748 * are issued to the SDRAM. This signal goes low when MRCTRL0.pda_en becomes 0. Therefore, it is
9749 * recommended to write MRCTRL0.pda_en to 0 after this signal goes high in order to prepare to
9750 * perform PDA operation next time
9751 * 0b0..Indicates that mode register write operation related to PDA/PBA is in progress or has not started yet.
9752 * 0b1..Indicates that mode register write operation related to PDA/PBA has competed.
9753 */
9754#define DDRC_MRSTAT_pda_done(x) \
9755 (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_pda_done_SHIFT)) & DDRC_MRSTAT_pda_done_MASK)
9756/*! @} */
9757
9758/*! @name MRCTRL2 - Mode Register Read/Write Control Register 2 */
9759/*! @{ */
9760#define DDRC_MRCTRL2_mr_device_sel_MASK (0xFFFFFFFFU)
9761#define DDRC_MRCTRL2_mr_device_sel_SHIFT (0U)
9762#define DDRC_MRCTRL2_mr_device_sel(x) \
9763 (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL2_mr_device_sel_SHIFT)) & DDRC_MRCTRL2_mr_device_sel_MASK)
9764/*! @} */
9765
9766/*! @name DERATEEN - Temperature Derate Enable Register */
9767/*! @{ */
9768#define DDRC_DERATEEN_derate_enable_MASK (0x1U)
9769#define DDRC_DERATEEN_derate_enable_SHIFT (0U)
9770/*! derate_enable - Enables derating. Present only in designs configured to support
9771 * LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
9772 * 0b0..Timing parameter derating is disabled
9773 * 0b1..Timing parameter derating is enabled using MR4 read value.
9774 */
9775#define DDRC_DERATEEN_derate_enable(x) \
9776 (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_enable_SHIFT)) & DDRC_DERATEEN_derate_enable_MASK)
9777#define DDRC_DERATEEN_derate_value_MASK (0x2U)
9778#define DDRC_DERATEEN_derate_value_SHIFT (1U)
9779/*! derate_value - Derate value. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
9780 * Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a
9781 * core_ddrc_core_clk period. For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this
9782 * register field should be set to 1; otherwise it should be set to 0.
9783 * 0b0..Derating uses +1
9784 * 0b1..Derating uses +2
9785 */
9786#define DDRC_DERATEEN_derate_value(x) \
9787 (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_value_SHIFT)) & DDRC_DERATEEN_derate_value_MASK)
9788#define DDRC_DERATEEN_derate_byte_MASK (0xF0U)
9789#define DDRC_DERATEEN_derate_byte_SHIFT (4U)
9790#define DDRC_DERATEEN_derate_byte(x) \
9791 (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_byte_SHIFT)) & DDRC_DERATEEN_derate_byte_MASK)
9792#define DDRC_DERATEEN_rc_derate_value_MASK (0x300U)
9793#define DDRC_DERATEEN_rc_derate_value_SHIFT (8U)
9794/*! rc_derate_value - Derate value of tRC for LPDDR4. Present only in designs configured to support
9795 * LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by the
9796 * core_ddrc_core_clk period, and rounding up the next integer.
9797 * 0b00..Derating uses +1
9798 * 0b01..Derating uses +2
9799 * 0b10..Derating uses +3
9800 * 0b11..Derating uses +4
9801 */
9802#define DDRC_DERATEEN_rc_derate_value(x) \
9803 (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_rc_derate_value_SHIFT)) & DDRC_DERATEEN_rc_derate_value_MASK)
9804/*! @} */
9805
9806/*! @name DERATEINT - Temperature Derate Interval Register */
9807/*! @{ */
9808#define DDRC_DERATEINT_mr4_read_interval_MASK (0xFFFFFFFFU)
9809#define DDRC_DERATEINT_mr4_read_interval_SHIFT (0U)
9810#define DDRC_DERATEINT_mr4_read_interval(x) \
9811 (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEINT_mr4_read_interval_SHIFT)) & DDRC_DERATEINT_mr4_read_interval_MASK)
9812/*! @} */
9813
9814/*! @name PWRCTL - Low Power Control Register */
9815/*! @{ */
9816#define DDRC_PWRCTL_selfref_en_MASK (0x1U)
9817#define DDRC_PWRCTL_selfref_en_SHIFT (0U)
9818#define DDRC_PWRCTL_selfref_en(x) \
9819 (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_selfref_en_SHIFT)) & DDRC_PWRCTL_selfref_en_MASK)
9820#define DDRC_PWRCTL_powerdown_en_MASK (0x2U)
9821#define DDRC_PWRCTL_powerdown_en_SHIFT (1U)
9822#define DDRC_PWRCTL_powerdown_en(x) \
9823 (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_powerdown_en_SHIFT)) & DDRC_PWRCTL_powerdown_en_MASK)
9824#define DDRC_PWRCTL_deeppowerdown_en_MASK (0x4U)
9825#define DDRC_PWRCTL_deeppowerdown_en_SHIFT (2U)
9826#define DDRC_PWRCTL_deeppowerdown_en(x) \
9827 (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_deeppowerdown_en_SHIFT)) & DDRC_PWRCTL_deeppowerdown_en_MASK)
9828#define DDRC_PWRCTL_en_dfi_dram_clk_disable_MASK (0x8U)
9829#define DDRC_PWRCTL_en_dfi_dram_clk_disable_SHIFT (3U)
9830#define DDRC_PWRCTL_en_dfi_dram_clk_disable(x) \
9831 (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_en_dfi_dram_clk_disable_SHIFT)) & \
9832 DDRC_PWRCTL_en_dfi_dram_clk_disable_MASK)
9833#define DDRC_PWRCTL_mpsm_en_MASK (0x10U)
9834#define DDRC_PWRCTL_mpsm_en_SHIFT (4U)
9835#define DDRC_PWRCTL_mpsm_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_mpsm_en_SHIFT)) & DDRC_PWRCTL_mpsm_en_MASK)
9836#define DDRC_PWRCTL_selfref_sw_MASK (0x20U)
9837#define DDRC_PWRCTL_selfref_sw_SHIFT (5U)
9838/*! selfref_sw - A value of 1 to this register causes system to move to Self Refresh state
9839 * immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software
9840 * Entry/Exit to Self Refresh.
9841 * 0b0..Software Exit from Self Refresh
9842 * 0b1..Software Entry to Self Refresh
9843 */
9844#define DDRC_PWRCTL_selfref_sw(x) \
9845 (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_selfref_sw_SHIFT)) & DDRC_PWRCTL_selfref_sw_MASK)
9846#define DDRC_PWRCTL_stay_in_selfref_MASK (0x40U)
9847#define DDRC_PWRCTL_stay_in_selfref_SHIFT (6U)
9848/*! stay_in_selfref - Self refresh state is an intermediate state to enter to Self refresh power
9849 * down state or exit Self refresh power down state for LPDDR4. This register controls transition
9850 * from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 0 - Allow
9851 * transition from Self refresh state
9852 * 0b0..
9853 * 0b1..
9854 */
9855#define DDRC_PWRCTL_stay_in_selfref(x) \
9856 (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_stay_in_selfref_SHIFT)) & DDRC_PWRCTL_stay_in_selfref_MASK)
9857/*! @} */
9858
9859/*! @name PWRTMG - Low Power Timing Register */
9860/*! @{ */
9861#define DDRC_PWRTMG_powerdown_to_x32_MASK (0x1FU)
9862#define DDRC_PWRTMG_powerdown_to_x32_SHIFT (0U)
9863#define DDRC_PWRTMG_powerdown_to_x32(x) \
9864 (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_powerdown_to_x32_SHIFT)) & DDRC_PWRTMG_powerdown_to_x32_MASK)
9865#define DDRC_PWRTMG_t_dpd_x4096_MASK (0xFF00U)
9866#define DDRC_PWRTMG_t_dpd_x4096_SHIFT (8U)
9867#define DDRC_PWRTMG_t_dpd_x4096(x) \
9868 (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_t_dpd_x4096_SHIFT)) & DDRC_PWRTMG_t_dpd_x4096_MASK)
9869#define DDRC_PWRTMG_selfref_to_x32_MASK (0xFF0000U)
9870#define DDRC_PWRTMG_selfref_to_x32_SHIFT (16U)
9871#define DDRC_PWRTMG_selfref_to_x32(x) \
9872 (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_selfref_to_x32_SHIFT)) & DDRC_PWRTMG_selfref_to_x32_MASK)
9873/*! @} */
9874
9875/*! @name HWLPCTL - Hardware Low Power Control Register */
9876/*! @{ */
9877#define DDRC_HWLPCTL_hw_lp_en_MASK (0x1U)
9878#define DDRC_HWLPCTL_hw_lp_en_SHIFT (0U)
9879#define DDRC_HWLPCTL_hw_lp_en(x) \
9880 (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_en_SHIFT)) & DDRC_HWLPCTL_hw_lp_en_MASK)
9881#define DDRC_HWLPCTL_hw_lp_exit_idle_en_MASK (0x2U)
9882#define DDRC_HWLPCTL_hw_lp_exit_idle_en_SHIFT (1U)
9883#define DDRC_HWLPCTL_hw_lp_exit_idle_en(x) \
9884 (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_exit_idle_en_SHIFT)) & DDRC_HWLPCTL_hw_lp_exit_idle_en_MASK)
9885#define DDRC_HWLPCTL_hw_lp_idle_x32_MASK (0xFFF0000U)
9886#define DDRC_HWLPCTL_hw_lp_idle_x32_SHIFT (16U)
9887#define DDRC_HWLPCTL_hw_lp_idle_x32(x) \
9888 (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_idle_x32_SHIFT)) & DDRC_HWLPCTL_hw_lp_idle_x32_MASK)
9889/*! @} */
9890
9891/*! @name RFSHCTL0 - Refresh Control Register 0 */
9892/*! @{ */
9893#define DDRC_RFSHCTL0_per_bank_refresh_MASK (0x4U)
9894#define DDRC_RFSHCTL0_per_bank_refresh_SHIFT (2U)
9895/*! per_bank_refresh - Per bank refresh allows traffic to flow to other banks. Per bank refresh is
9896 * not supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices.
9897 * Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
9898 * 0b1..Per bank refresh
9899 * 0b0..All bank refresh
9900 */
9901#define DDRC_RFSHCTL0_per_bank_refresh(x) \
9902 (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_per_bank_refresh_SHIFT)) & DDRC_RFSHCTL0_per_bank_refresh_MASK)
9903#define DDRC_RFSHCTL0_refresh_burst_MASK (0x1F0U)
9904#define DDRC_RFSHCTL0_refresh_burst_SHIFT (4U)
9905#define DDRC_RFSHCTL0_refresh_burst(x) \
9906 (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_burst_SHIFT)) & DDRC_RFSHCTL0_refresh_burst_MASK)
9907#define DDRC_RFSHCTL0_refresh_to_x32_MASK (0x1F000U)
9908#define DDRC_RFSHCTL0_refresh_to_x32_SHIFT (12U)
9909#define DDRC_RFSHCTL0_refresh_to_x32(x) \
9910 (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_to_x32_SHIFT)) & DDRC_RFSHCTL0_refresh_to_x32_MASK)
9911#define DDRC_RFSHCTL0_refresh_margin_MASK (0xF00000U)
9912#define DDRC_RFSHCTL0_refresh_margin_SHIFT (20U)
9913#define DDRC_RFSHCTL0_refresh_margin(x) \
9914 (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_margin_SHIFT)) & DDRC_RFSHCTL0_refresh_margin_MASK)
9915/*! @} */
9916
9917/*! @name RFSHCTL1 - Refresh Control Register 1 */
9918/*! @{ */
9919#define DDRC_RFSHCTL1_refresh_timer0_start_value_x32_MASK (0xFFFU)
9920#define DDRC_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT (0U)
9921#define DDRC_RFSHCTL1_refresh_timer0_start_value_x32(x) \
9922 (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT)) & \
9923 DDRC_RFSHCTL1_refresh_timer0_start_value_x32_MASK)
9924#define DDRC_RFSHCTL1_refresh_timer1_start_value_x32_MASK (0xFFF0000U)
9925#define DDRC_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT (16U)
9926#define DDRC_RFSHCTL1_refresh_timer1_start_value_x32(x) \
9927 (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT)) & \
9928 DDRC_RFSHCTL1_refresh_timer1_start_value_x32_MASK)
9929/*! @} */
9930
9931/*! @name RFSHCTL3 - Refresh Control Register 3 */
9932/*! @{ */
9933#define DDRC_RFSHCTL3_dis_auto_refresh_MASK (0x1U)
9934#define DDRC_RFSHCTL3_dis_auto_refresh_SHIFT (0U)
9935#define DDRC_RFSHCTL3_dis_auto_refresh(x) \
9936 (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_dis_auto_refresh_SHIFT)) & DDRC_RFSHCTL3_dis_auto_refresh_MASK)
9937#define DDRC_RFSHCTL3_refresh_update_level_MASK (0x2U)
9938#define DDRC_RFSHCTL3_refresh_update_level_SHIFT (1U)
9939#define DDRC_RFSHCTL3_refresh_update_level(x) \
9940 (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_refresh_update_level_SHIFT)) & \
9941 DDRC_RFSHCTL3_refresh_update_level_MASK)
9942#define DDRC_RFSHCTL3_refresh_mode_MASK (0x70U)
9943#define DDRC_RFSHCTL3_refresh_mode_SHIFT (4U)
9944#define DDRC_RFSHCTL3_refresh_mode(x) \
9945 (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_refresh_mode_SHIFT)) & DDRC_RFSHCTL3_refresh_mode_MASK)
9946/*! @} */
9947
9948/*! @name RFSHTMG - Refresh Timing Register */
9949/*! @{ */
9950#define DDRC_RFSHTMG_t_rfc_min_MASK (0x3FFU)
9951#define DDRC_RFSHTMG_t_rfc_min_SHIFT (0U)
9952#define DDRC_RFSHTMG_t_rfc_min(x) \
9953 (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_t_rfc_min_SHIFT)) & DDRC_RFSHTMG_t_rfc_min_MASK)
9954#define DDRC_RFSHTMG_lpddr3_trefbw_en_MASK (0x8000U)
9955#define DDRC_RFSHTMG_lpddr3_trefbw_en_SHIFT (15U)
9956#define DDRC_RFSHTMG_lpddr3_trefbw_en(x) \
9957 (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_lpddr3_trefbw_en_SHIFT)) & DDRC_RFSHTMG_lpddr3_trefbw_en_MASK)
9958#define DDRC_RFSHTMG_t_rfc_nom_x32_MASK (0xFFF0000U)
9959#define DDRC_RFSHTMG_t_rfc_nom_x32_SHIFT (16U)
9960#define DDRC_RFSHTMG_t_rfc_nom_x32(x) \
9961 (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_t_rfc_nom_x32_SHIFT)) & DDRC_RFSHTMG_t_rfc_nom_x32_MASK)
9962/*! @} */
9963
9964/*! @name INIT0 - SDRAM Initialization Register 0 */
9965/*! @{ */
9966#define DDRC_INIT0_pre_cke_x1024_MASK (0xFFFU)
9967#define DDRC_INIT0_pre_cke_x1024_SHIFT (0U)
9968#define DDRC_INIT0_pre_cke_x1024(x) \
9969 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_pre_cke_x1024_SHIFT)) & DDRC_INIT0_pre_cke_x1024_MASK)
9970#define DDRC_INIT0_post_cke_x1024_MASK (0x3FF0000U)
9971#define DDRC_INIT0_post_cke_x1024_SHIFT (16U)
9972#define DDRC_INIT0_post_cke_x1024(x) \
9973 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_post_cke_x1024_SHIFT)) & DDRC_INIT0_post_cke_x1024_MASK)
9974#define DDRC_INIT0_skip_dram_init_MASK (0xC0000000U)
9975#define DDRC_INIT0_skip_dram_init_SHIFT (30U)
9976/*! skip_dram_init - If lower bit is enabled the SDRAM initialization routine is skipped. The upper
9977 * bit decides what state the controller starts up in when reset is removed - 00 - SDRAM
9978 * Intialization routine is run after power-up - 01 - SDRAM Initialization routine is skipped after
9979 * power-up. Controller starts up in Normal Mode - 11 - SDRAM Initialization routine is skipped after
9980 * power-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Initialization routine is run
9981 * after power-up.
9982 * 0b00..SDRAM Initialization routine is run after power-up
9983 * 0b01..SDRAM Initialization routine is skipped after power-up
9984 * 0b10..SDRAM Initialization routine is run after power-up
9985 * 0b11..SDRAM Initialization routine is skipped after power-up
9986 */
9987#define DDRC_INIT0_skip_dram_init(x) \
9988 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_skip_dram_init_SHIFT)) & DDRC_INIT0_skip_dram_init_MASK)
9989/*! @} */
9990
9991/*! @name INIT1 - SDRAM Initialization Register 1 */
9992/*! @{ */
9993#define DDRC_INIT1_pre_ocd_x32_MASK (0xFU)
9994#define DDRC_INIT1_pre_ocd_x32_SHIFT (0U)
9995#define DDRC_INIT1_pre_ocd_x32(x) \
9996 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_pre_ocd_x32_SHIFT)) & DDRC_INIT1_pre_ocd_x32_MASK)
9997#define DDRC_INIT1_dram_rstn_x1024_MASK (0x1FF0000U)
9998#define DDRC_INIT1_dram_rstn_x1024_SHIFT (16U)
9999#define DDRC_INIT1_dram_rstn_x1024(x) \
10000 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_dram_rstn_x1024_SHIFT)) & DDRC_INIT1_dram_rstn_x1024_MASK)
10001/*! @} */
10002
10003/*! @name INIT2 - SDRAM Initialization Register 2 */
10004/*! @{ */
10005#define DDRC_INIT2_min_stable_clock_x1_MASK (0xFU)
10006#define DDRC_INIT2_min_stable_clock_x1_SHIFT (0U)
10007#define DDRC_INIT2_min_stable_clock_x1(x) \
10008 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_min_stable_clock_x1_SHIFT)) & DDRC_INIT2_min_stable_clock_x1_MASK)
10009#define DDRC_INIT2_idle_after_reset_x32_MASK (0xFF00U)
10010#define DDRC_INIT2_idle_after_reset_x32_SHIFT (8U)
10011#define DDRC_INIT2_idle_after_reset_x32(x) \
10012 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_idle_after_reset_x32_SHIFT)) & DDRC_INIT2_idle_after_reset_x32_MASK)
10013/*! @} */
10014
10015/*! @name INIT3 - SDRAM Initialization Register 3 */
10016/*! @{ */
10017#define DDRC_INIT3_emr_MASK (0xFFFFU)
10018#define DDRC_INIT3_emr_SHIFT (0U)
10019#define DDRC_INIT3_emr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_emr_SHIFT)) & DDRC_INIT3_emr_MASK)
10020#define DDRC_INIT3_mr_MASK (0xFFFF0000U)
10021#define DDRC_INIT3_mr_SHIFT (16U)
10022#define DDRC_INIT3_mr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_mr_SHIFT)) & DDRC_INIT3_mr_MASK)
10023/*! @} */
10024
10025/*! @name INIT4 - SDRAM Initialization Register 4 */
10026/*! @{ */
10027#define DDRC_INIT4_emr3_MASK (0xFFFFU)
10028#define DDRC_INIT4_emr3_SHIFT (0U)
10029#define DDRC_INIT4_emr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_emr3_SHIFT)) & DDRC_INIT4_emr3_MASK)
10030#define DDRC_INIT4_emr2_MASK (0xFFFF0000U)
10031#define DDRC_INIT4_emr2_SHIFT (16U)
10032#define DDRC_INIT4_emr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_emr2_SHIFT)) & DDRC_INIT4_emr2_MASK)
10033/*! @} */
10034
10035/*! @name INIT5 - SDRAM Initialization Register 5 */
10036/*! @{ */
10037#define DDRC_INIT5_max_auto_init_x1024_MASK (0x3FFU)
10038#define DDRC_INIT5_max_auto_init_x1024_SHIFT (0U)
10039#define DDRC_INIT5_max_auto_init_x1024(x) \
10040 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_max_auto_init_x1024_SHIFT)) & DDRC_INIT5_max_auto_init_x1024_MASK)
10041#define DDRC_INIT5_dev_zqinit_x32_MASK (0xFF0000U)
10042#define DDRC_INIT5_dev_zqinit_x32_SHIFT (16U)
10043#define DDRC_INIT5_dev_zqinit_x32(x) \
10044 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_dev_zqinit_x32_SHIFT)) & DDRC_INIT5_dev_zqinit_x32_MASK)
10045/*! @} */
10046
10047/*! @name INIT6 - SDRAM Initialization Register 6 */
10048/*! @{ */
10049#define DDRC_INIT6_mr5_MASK (0xFFFFU)
10050#define DDRC_INIT6_mr5_SHIFT (0U)
10051#define DDRC_INIT6_mr5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_mr5_SHIFT)) & DDRC_INIT6_mr5_MASK)
10052#define DDRC_INIT6_mr4_MASK (0xFFFF0000U)
10053#define DDRC_INIT6_mr4_SHIFT (16U)
10054#define DDRC_INIT6_mr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_mr4_SHIFT)) & DDRC_INIT6_mr4_MASK)
10055/*! @} */
10056
10057/*! @name INIT7 - SDRAM Initialization Register 7 */
10058/*! @{ */
10059#define DDRC_INIT7_mr6_MASK (0xFFFF0000U)
10060#define DDRC_INIT7_mr6_SHIFT (16U)
10061#define DDRC_INIT7_mr6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT7_mr6_SHIFT)) & DDRC_INIT7_mr6_MASK)
10062/*! @} */
10063
10064/*! @name DIMMCTL - DIMM Control Register */
10065/*! @{ */
10066#define DDRC_DIMMCTL_dimm_stagger_cs_en_MASK (0x1U)
10067#define DDRC_DIMMCTL_dimm_stagger_cs_en_SHIFT (0U)
10068/*! dimm_stagger_cs_en - Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and
10069 * LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs.
10070 * Even if this bit is set it does not take care of software driven MR commands (via
10071 * MRCTRL0/MRCTRL1), where software is responsible to send them to separate ranks as appropriate.
10072 * 0b0..Do not stagger accesses
10073 * 0b1..For(non-DDR4) Send all commands to even and odd ranks separately;For(DDR4) Send MRS commands to each ranks
10074 * separately
10075 */
10076#define DDRC_DIMMCTL_dimm_stagger_cs_en(x) \
10077 (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_stagger_cs_en_SHIFT)) & DDRC_DIMMCTL_dimm_stagger_cs_en_MASK)
10078#define DDRC_DIMMCTL_dimm_addr_mirr_en_MASK (0x2U)
10079#define DDRC_DIMMCTL_dimm_addr_mirr_en_SHIFT (1U)
10080/*! dimm_addr_mirr_en - Address Mirroring Enable (for multi-rank UDIMM implementations and
10081 * multi-rank DDR4 RDIMM/LRDIMM implementations). Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address
10082 * mirroring for odd ranks, which means that the following address, bank address and bank group
10083 * bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for
10084 * the DDR4. Setting this bit ensures that, for mode register accesses during the automatic
10085 * initialization routine, these bits are swapped within the DDRC to compensate for this
10086 * UDIMM/RDIMM/LRDIMM swapping. In addition to the automatic initialization routine, in case of DDR4
10087 * UDIMM/RDIMM/LRDIMM, they are swapped during the automatic MRS access to enable/disable of a particular
10088 * DDR4 feature. Note: This has no effect on the address of any other memory accesses, or of
10089 * software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4
10090 * SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0
10091 * because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1.
10092 * 0b0..Do not implement address mirroring
10093 * 0b1..For odd ranks, implement address mirroring for MRS commands to during initialization and for any
10094 * automatic DDR4 MRS commands (to be used if UDIMM/RDIMM/LRDIMM implements address mirroring)
10095 */
10096#define DDRC_DIMMCTL_dimm_addr_mirr_en(x) \
10097 (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_addr_mirr_en_SHIFT)) & DDRC_DIMMCTL_dimm_addr_mirr_en_MASK)
10098#define DDRC_DIMMCTL_dimm_output_inv_en_MASK (0x4U)
10099#define DDRC_DIMMCTL_dimm_output_inv_en_SHIFT (2U)
10100/*! dimm_output_inv_en - Output Inversion Enable (for DDR4 RDIMM/LRDIMM implementations only). DDR4
10101 * RDIMM/LRDIMM implements the Output Inversion feature by default, which means that the
10102 * following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13,
10103 * A17, BA0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the
10104 * DDRC during the automatic initialization routine and enabling of a particular DDR4 feature,
10105 * separate A-side and B-side mode register accesses are generated. For B-side mode register
10106 * accesses, these bits are inverted within the DDRC to compensate for this RDIMM/LRDIMM inversion. It
10107 * is recommended to set this bit always, if using DDR4 RDIMMs/LRDIMMs. Note: This has no effect
10108 * on the address of any other memory accesses, or of software-driven mode register accesses.
10109 * 0b0..Do not implement output inversion for B-side DRAMs.
10110 * 0b1..Implement output inversion for B-side DRAMs.
10111 */
10112#define DDRC_DIMMCTL_dimm_output_inv_en(x) \
10113 (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_output_inv_en_SHIFT)) & DDRC_DIMMCTL_dimm_output_inv_en_MASK)
10114#define DDRC_DIMMCTL_mrs_a17_en_MASK (0x8U)
10115#define DDRC_DIMMCTL_mrs_a17_en_SHIFT (3U)
10116/*! mrs_a17_en - Enable for A17 bit of MRS command. A17 bit of the mode register address is
10117 * specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs
10118 * which do not have A17 are attached and the Output Inversion are enabled, this must be set to
10119 * 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on
10120 * the address of any other memory accesses, or of software-driven mode register accesses.
10121 * 0b0..Disabled
10122 * 0b1..Enabled
10123 */
10124#define DDRC_DIMMCTL_mrs_a17_en(x) \
10125 (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_mrs_a17_en_SHIFT)) & DDRC_DIMMCTL_mrs_a17_en_MASK)
10126#define DDRC_DIMMCTL_mrs_bg1_en_MASK (0x10U)
10127#define DDRC_DIMMCTL_mrs_bg1_en_SHIFT (4U)
10128/*! mrs_bg1_en - Enable for BG1 bit of MRS command. BG1 bit of the mode register address is
10129 * specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs
10130 * which do not have BG1 are attached and both the CA parity and the Output Inversion are
10131 * enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note:
10132 * This has no effect on the address of any other memory accesses, or of software-driven mode
10133 * register accesses. If address mirroring is enabled, this is applied to BG1 of even ranks and BG0
10134 * of odd ranks.
10135 * 0b0..Disabled
10136 * 0b1..Enabled
10137 */
10138#define DDRC_DIMMCTL_mrs_bg1_en(x) \
10139 (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_mrs_bg1_en_SHIFT)) & DDRC_DIMMCTL_mrs_bg1_en_MASK)
10140#define DDRC_DIMMCTL_dimm_dis_bg_mirroring_MASK (0x20U)
10141#define DDRC_DIMMCTL_dimm_dis_bg_mirroring_SHIFT (5U)
10142/*! dimm_dis_bg_mirroring - Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and
10143 * BG1 are NOT swapped even if Address Mirroring is enabled. This will be required for DDR4 DIMMs
10144 * with x16 devices.
10145 * 0b0..BG0 and BG1 are swapped if address mirroring is enabled.
10146 * 0b1..BG0 and BG1 are NOT swapped.
10147 */
10148#define DDRC_DIMMCTL_dimm_dis_bg_mirroring(x) \
10149 (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_dis_bg_mirroring_SHIFT)) & \
10150 DDRC_DIMMCTL_dimm_dis_bg_mirroring_MASK)
10151#define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_MASK (0x40U)
10152#define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT (6U)
10153#define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot(x) \
10154 (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT)) & DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_MASK)
10155/*! @} */
10156
10157/*! @name RANKCTL - Rank Control Register */
10158/*! @{ */
10159#define DDRC_RANKCTL_max_rank_rd_MASK (0xFU)
10160#define DDRC_RANKCTL_max_rank_rd_SHIFT (0U)
10161#define DDRC_RANKCTL_max_rank_rd(x) \
10162 (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_max_rank_rd_SHIFT)) & DDRC_RANKCTL_max_rank_rd_MASK)
10163#define DDRC_RANKCTL_diff_rank_rd_gap_MASK (0xF0U)
10164#define DDRC_RANKCTL_diff_rank_rd_gap_SHIFT (4U)
10165#define DDRC_RANKCTL_diff_rank_rd_gap(x) \
10166 (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_diff_rank_rd_gap_SHIFT)) & DDRC_RANKCTL_diff_rank_rd_gap_MASK)
10167#define DDRC_RANKCTL_diff_rank_wr_gap_MASK (0xF00U)
10168#define DDRC_RANKCTL_diff_rank_wr_gap_SHIFT (8U)
10169#define DDRC_RANKCTL_diff_rank_wr_gap(x) \
10170 (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_diff_rank_wr_gap_SHIFT)) & DDRC_RANKCTL_diff_rank_wr_gap_MASK)
10171/*! @} */
10172
10173/*! @name DRAMTMG0 - SDRAM Timing Register 0 */
10174/*! @{ */
10175#define DDRC_DRAMTMG0_t_ras_min_MASK (0x3FU)
10176#define DDRC_DRAMTMG0_t_ras_min_SHIFT (0U)
10177#define DDRC_DRAMTMG0_t_ras_min(x) \
10178 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_ras_min_SHIFT)) & DDRC_DRAMTMG0_t_ras_min_MASK)
10179#define DDRC_DRAMTMG0_t_ras_max_MASK (0x7F00U)
10180#define DDRC_DRAMTMG0_t_ras_max_SHIFT (8U)
10181#define DDRC_DRAMTMG0_t_ras_max(x) \
10182 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_ras_max_SHIFT)) & DDRC_DRAMTMG0_t_ras_max_MASK)
10183#define DDRC_DRAMTMG0_t_faw_MASK (0x3F0000U)
10184#define DDRC_DRAMTMG0_t_faw_SHIFT (16U)
10185#define DDRC_DRAMTMG0_t_faw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_faw_SHIFT)) & DDRC_DRAMTMG0_t_faw_MASK)
10186#define DDRC_DRAMTMG0_wr2pre_MASK (0x7F000000U)
10187#define DDRC_DRAMTMG0_wr2pre_SHIFT (24U)
10188#define DDRC_DRAMTMG0_wr2pre(x) \
10189 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_wr2pre_SHIFT)) & DDRC_DRAMTMG0_wr2pre_MASK)
10190/*! @} */
10191
10192/*! @name DRAMTMG1 - SDRAM Timing Register 1 */
10193/*! @{ */
10194#define DDRC_DRAMTMG1_t_rc_MASK (0x7FU)
10195#define DDRC_DRAMTMG1_t_rc_SHIFT (0U)
10196#define DDRC_DRAMTMG1_t_rc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_t_rc_SHIFT)) & DDRC_DRAMTMG1_t_rc_MASK)
10197#define DDRC_DRAMTMG1_rd2pre_MASK (0x3F00U)
10198#define DDRC_DRAMTMG1_rd2pre_SHIFT (8U)
10199#define DDRC_DRAMTMG1_rd2pre(x) \
10200 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_rd2pre_SHIFT)) & DDRC_DRAMTMG1_rd2pre_MASK)
10201#define DDRC_DRAMTMG1_t_xp_MASK (0x1F0000U)
10202#define DDRC_DRAMTMG1_t_xp_SHIFT (16U)
10203#define DDRC_DRAMTMG1_t_xp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_t_xp_SHIFT)) & DDRC_DRAMTMG1_t_xp_MASK)
10204/*! @} */
10205
10206/*! @name DRAMTMG2 - SDRAM Timing Register 2 */
10207/*! @{ */
10208#define DDRC_DRAMTMG2_wr2rd_MASK (0x3FU)
10209#define DDRC_DRAMTMG2_wr2rd_SHIFT (0U)
10210#define DDRC_DRAMTMG2_wr2rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_wr2rd_SHIFT)) & DDRC_DRAMTMG2_wr2rd_MASK)
10211#define DDRC_DRAMTMG2_rd2wr_MASK (0x3F00U)
10212#define DDRC_DRAMTMG2_rd2wr_SHIFT (8U)
10213#define DDRC_DRAMTMG2_rd2wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_rd2wr_SHIFT)) & DDRC_DRAMTMG2_rd2wr_MASK)
10214#define DDRC_DRAMTMG2_read_latency_MASK (0x3F0000U)
10215#define DDRC_DRAMTMG2_read_latency_SHIFT (16U)
10216#define DDRC_DRAMTMG2_read_latency(x) \
10217 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_read_latency_SHIFT)) & DDRC_DRAMTMG2_read_latency_MASK)
10218#define DDRC_DRAMTMG2_write_latency_MASK (0x3F000000U)
10219#define DDRC_DRAMTMG2_write_latency_SHIFT (24U)
10220#define DDRC_DRAMTMG2_write_latency(x) \
10221 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_write_latency_SHIFT)) & DDRC_DRAMTMG2_write_latency_MASK)
10222/*! @} */
10223
10224/*! @name DRAMTMG3 - SDRAM Timing Register 3 */
10225/*! @{ */
10226#define DDRC_DRAMTMG3_t_mod_MASK (0x3FFU)
10227#define DDRC_DRAMTMG3_t_mod_SHIFT (0U)
10228#define DDRC_DRAMTMG3_t_mod(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mod_SHIFT)) & DDRC_DRAMTMG3_t_mod_MASK)
10229#define DDRC_DRAMTMG3_t_mrd_MASK (0x3F000U)
10230#define DDRC_DRAMTMG3_t_mrd_SHIFT (12U)
10231#define DDRC_DRAMTMG3_t_mrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mrd_SHIFT)) & DDRC_DRAMTMG3_t_mrd_MASK)
10232#define DDRC_DRAMTMG3_t_mrw_MASK (0x3FF00000U)
10233#define DDRC_DRAMTMG3_t_mrw_SHIFT (20U)
10234#define DDRC_DRAMTMG3_t_mrw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mrw_SHIFT)) & DDRC_DRAMTMG3_t_mrw_MASK)
10235/*! @} */
10236
10237/*! @name DRAMTMG4 - SDRAM Timing Register 4 */
10238/*! @{ */
10239#define DDRC_DRAMTMG4_t_rp_MASK (0x1FU)
10240#define DDRC_DRAMTMG4_t_rp_SHIFT (0U)
10241#define DDRC_DRAMTMG4_t_rp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rp_SHIFT)) & DDRC_DRAMTMG4_t_rp_MASK)
10242#define DDRC_DRAMTMG4_t_rrd_MASK (0xF00U)
10243#define DDRC_DRAMTMG4_t_rrd_SHIFT (8U)
10244#define DDRC_DRAMTMG4_t_rrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rrd_SHIFT)) & DDRC_DRAMTMG4_t_rrd_MASK)
10245#define DDRC_DRAMTMG4_t_ccd_MASK (0xF0000U)
10246#define DDRC_DRAMTMG4_t_ccd_SHIFT (16U)
10247#define DDRC_DRAMTMG4_t_ccd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_ccd_SHIFT)) & DDRC_DRAMTMG4_t_ccd_MASK)
10248#define DDRC_DRAMTMG4_t_rcd_MASK (0x1F000000U)
10249#define DDRC_DRAMTMG4_t_rcd_SHIFT (24U)
10250#define DDRC_DRAMTMG4_t_rcd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rcd_SHIFT)) & DDRC_DRAMTMG4_t_rcd_MASK)
10251/*! @} */
10252
10253/*! @name DRAMTMG5 - SDRAM Timing Register 5 */
10254/*! @{ */
10255#define DDRC_DRAMTMG5_t_cke_MASK (0x1FU)
10256#define DDRC_DRAMTMG5_t_cke_SHIFT (0U)
10257#define DDRC_DRAMTMG5_t_cke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cke_SHIFT)) & DDRC_DRAMTMG5_t_cke_MASK)
10258#define DDRC_DRAMTMG5_t_ckesr_MASK (0x3F00U)
10259#define DDRC_DRAMTMG5_t_ckesr_SHIFT (8U)
10260#define DDRC_DRAMTMG5_t_ckesr(x) \
10261 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_ckesr_SHIFT)) & DDRC_DRAMTMG5_t_ckesr_MASK)
10262#define DDRC_DRAMTMG5_t_cksre_MASK (0xF0000U)
10263#define DDRC_DRAMTMG5_t_cksre_SHIFT (16U)
10264#define DDRC_DRAMTMG5_t_cksre(x) \
10265 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cksre_SHIFT)) & DDRC_DRAMTMG5_t_cksre_MASK)
10266#define DDRC_DRAMTMG5_t_cksrx_MASK (0xF000000U)
10267#define DDRC_DRAMTMG5_t_cksrx_SHIFT (24U)
10268#define DDRC_DRAMTMG5_t_cksrx(x) \
10269 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cksrx_SHIFT)) & DDRC_DRAMTMG5_t_cksrx_MASK)
10270/*! @} */
10271
10272/*! @name DRAMTMG6 - SDRAM Timing Register 6 */
10273/*! @{ */
10274#define DDRC_DRAMTMG6_t_ckcsx_MASK (0xFU)
10275#define DDRC_DRAMTMG6_t_ckcsx_SHIFT (0U)
10276#define DDRC_DRAMTMG6_t_ckcsx(x) \
10277 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckcsx_SHIFT)) & DDRC_DRAMTMG6_t_ckcsx_MASK)
10278#define DDRC_DRAMTMG6_t_ckdpdx_MASK (0xF0000U)
10279#define DDRC_DRAMTMG6_t_ckdpdx_SHIFT (16U)
10280#define DDRC_DRAMTMG6_t_ckdpdx(x) \
10281 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckdpdx_SHIFT)) & DDRC_DRAMTMG6_t_ckdpdx_MASK)
10282#define DDRC_DRAMTMG6_t_ckdpde_MASK (0xF000000U)
10283#define DDRC_DRAMTMG6_t_ckdpde_SHIFT (24U)
10284#define DDRC_DRAMTMG6_t_ckdpde(x) \
10285 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckdpde_SHIFT)) & DDRC_DRAMTMG6_t_ckdpde_MASK)
10286/*! @} */
10287
10288/*! @name DRAMTMG7 - SDRAM Timing Register 7 */
10289/*! @{ */
10290#define DDRC_DRAMTMG7_t_ckpdx_MASK (0xFU)
10291#define DDRC_DRAMTMG7_t_ckpdx_SHIFT (0U)
10292#define DDRC_DRAMTMG7_t_ckpdx(x) \
10293 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_t_ckpdx_SHIFT)) & DDRC_DRAMTMG7_t_ckpdx_MASK)
10294#define DDRC_DRAMTMG7_t_ckpde_MASK (0xF00U)
10295#define DDRC_DRAMTMG7_t_ckpde_SHIFT (8U)
10296#define DDRC_DRAMTMG7_t_ckpde(x) \
10297 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_t_ckpde_SHIFT)) & DDRC_DRAMTMG7_t_ckpde_MASK)
10298/*! @} */
10299
10300/*! @name DRAMTMG8 - SDRAM Timing Register 8 */
10301/*! @{ */
10302#define DDRC_DRAMTMG8_t_xs_x32_MASK (0x7FU)
10303#define DDRC_DRAMTMG8_t_xs_x32_SHIFT (0U)
10304#define DDRC_DRAMTMG8_t_xs_x32(x) \
10305 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_x32_MASK)
10306#define DDRC_DRAMTMG8_t_xs_dll_x32_MASK (0x7F00U)
10307#define DDRC_DRAMTMG8_t_xs_dll_x32_SHIFT (8U)
10308#define DDRC_DRAMTMG8_t_xs_dll_x32(x) \
10309 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_dll_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_dll_x32_MASK)
10310#define DDRC_DRAMTMG8_t_xs_abort_x32_MASK (0x7F0000U)
10311#define DDRC_DRAMTMG8_t_xs_abort_x32_SHIFT (16U)
10312#define DDRC_DRAMTMG8_t_xs_abort_x32(x) \
10313 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_abort_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_abort_x32_MASK)
10314#define DDRC_DRAMTMG8_t_xs_fast_x32_MASK (0x7F000000U)
10315#define DDRC_DRAMTMG8_t_xs_fast_x32_SHIFT (24U)
10316#define DDRC_DRAMTMG8_t_xs_fast_x32(x) \
10317 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_fast_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_fast_x32_MASK)
10318/*! @} */
10319
10320/*! @name DRAMTMG9 - SDRAM Timing Register 9 */
10321/*! @{ */
10322#define DDRC_DRAMTMG9_wr2rd_s_MASK (0x3FU)
10323#define DDRC_DRAMTMG9_wr2rd_s_SHIFT (0U)
10324#define DDRC_DRAMTMG9_wr2rd_s(x) \
10325 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_wr2rd_s_SHIFT)) & DDRC_DRAMTMG9_wr2rd_s_MASK)
10326#define DDRC_DRAMTMG9_t_rrd_s_MASK (0xF00U)
10327#define DDRC_DRAMTMG9_t_rrd_s_SHIFT (8U)
10328#define DDRC_DRAMTMG9_t_rrd_s(x) \
10329 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_t_rrd_s_SHIFT)) & DDRC_DRAMTMG9_t_rrd_s_MASK)
10330#define DDRC_DRAMTMG9_t_ccd_s_MASK (0x70000U)
10331#define DDRC_DRAMTMG9_t_ccd_s_SHIFT (16U)
10332#define DDRC_DRAMTMG9_t_ccd_s(x) \
10333 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_t_ccd_s_SHIFT)) & DDRC_DRAMTMG9_t_ccd_s_MASK)
10334#define DDRC_DRAMTMG9_ddr4_wr_preamble_MASK (0x40000000U)
10335#define DDRC_DRAMTMG9_ddr4_wr_preamble_SHIFT (30U)
10336#define DDRC_DRAMTMG9_ddr4_wr_preamble(x) \
10337 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_ddr4_wr_preamble_SHIFT)) & DDRC_DRAMTMG9_ddr4_wr_preamble_MASK)
10338/*! @} */
10339
10340/*! @name DRAMTMG10 - SDRAM Timing Register 10 */
10341/*! @{ */
10342#define DDRC_DRAMTMG10_t_gear_hold_MASK (0x3U)
10343#define DDRC_DRAMTMG10_t_gear_hold_SHIFT (0U)
10344#define DDRC_DRAMTMG10_t_gear_hold(x) \
10345 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_gear_hold_SHIFT)) & DDRC_DRAMTMG10_t_gear_hold_MASK)
10346#define DDRC_DRAMTMG10_t_gear_setup_MASK (0xCU)
10347#define DDRC_DRAMTMG10_t_gear_setup_SHIFT (2U)
10348#define DDRC_DRAMTMG10_t_gear_setup(x) \
10349 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_gear_setup_SHIFT)) & DDRC_DRAMTMG10_t_gear_setup_MASK)
10350#define DDRC_DRAMTMG10_t_cmd_gear_MASK (0x1F00U)
10351#define DDRC_DRAMTMG10_t_cmd_gear_SHIFT (8U)
10352#define DDRC_DRAMTMG10_t_cmd_gear(x) \
10353 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_cmd_gear_SHIFT)) & DDRC_DRAMTMG10_t_cmd_gear_MASK)
10354#define DDRC_DRAMTMG10_t_sync_gear_MASK (0x1F0000U)
10355#define DDRC_DRAMTMG10_t_sync_gear_SHIFT (16U)
10356#define DDRC_DRAMTMG10_t_sync_gear(x) \
10357 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_sync_gear_SHIFT)) & DDRC_DRAMTMG10_t_sync_gear_MASK)
10358/*! @} */
10359
10360/*! @name DRAMTMG11 - SDRAM Timing Register 11 */
10361/*! @{ */
10362#define DDRC_DRAMTMG11_t_ckmpe_MASK (0x1FU)
10363#define DDRC_DRAMTMG11_t_ckmpe_SHIFT (0U)
10364#define DDRC_DRAMTMG11_t_ckmpe(x) \
10365 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_ckmpe_SHIFT)) & DDRC_DRAMTMG11_t_ckmpe_MASK)
10366#define DDRC_DRAMTMG11_t_mpx_s_MASK (0x300U)
10367#define DDRC_DRAMTMG11_t_mpx_s_SHIFT (8U)
10368#define DDRC_DRAMTMG11_t_mpx_s(x) \
10369 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_mpx_s_SHIFT)) & DDRC_DRAMTMG11_t_mpx_s_MASK)
10370#define DDRC_DRAMTMG11_t_mpx_lh_MASK (0x1F0000U)
10371#define DDRC_DRAMTMG11_t_mpx_lh_SHIFT (16U)
10372#define DDRC_DRAMTMG11_t_mpx_lh(x) \
10373 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_mpx_lh_SHIFT)) & DDRC_DRAMTMG11_t_mpx_lh_MASK)
10374#define DDRC_DRAMTMG11_post_mpsm_gap_x32_MASK (0x7F000000U)
10375#define DDRC_DRAMTMG11_post_mpsm_gap_x32_SHIFT (24U)
10376#define DDRC_DRAMTMG11_post_mpsm_gap_x32(x) \
10377 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_post_mpsm_gap_x32_SHIFT)) & DDRC_DRAMTMG11_post_mpsm_gap_x32_MASK)
10378/*! @} */
10379
10380/*! @name DRAMTMG12 - SDRAM Timing Register 12 */
10381/*! @{ */
10382#define DDRC_DRAMTMG12_t_mrd_pda_MASK (0x1FU)
10383#define DDRC_DRAMTMG12_t_mrd_pda_SHIFT (0U)
10384#define DDRC_DRAMTMG12_t_mrd_pda(x) \
10385 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_mrd_pda_SHIFT)) & DDRC_DRAMTMG12_t_mrd_pda_MASK)
10386#define DDRC_DRAMTMG12_t_ckehcmd_MASK (0xF00U)
10387#define DDRC_DRAMTMG12_t_ckehcmd_SHIFT (8U)
10388#define DDRC_DRAMTMG12_t_ckehcmd(x) \
10389 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_ckehcmd_SHIFT)) & DDRC_DRAMTMG12_t_ckehcmd_MASK)
10390#define DDRC_DRAMTMG12_t_cmdcke_MASK (0x30000U)
10391#define DDRC_DRAMTMG12_t_cmdcke_SHIFT (16U)
10392#define DDRC_DRAMTMG12_t_cmdcke(x) \
10393 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_cmdcke_SHIFT)) & DDRC_DRAMTMG12_t_cmdcke_MASK)
10394/*! @} */
10395
10396/*! @name DRAMTMG13 - SDRAM Timing Register 13 */
10397/*! @{ */
10398#define DDRC_DRAMTMG13_t_ppd_MASK (0x7U)
10399#define DDRC_DRAMTMG13_t_ppd_SHIFT (0U)
10400#define DDRC_DRAMTMG13_t_ppd(x) \
10401 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_t_ppd_SHIFT)) & DDRC_DRAMTMG13_t_ppd_MASK)
10402#define DDRC_DRAMTMG13_t_ccd_mw_MASK (0x3F0000U)
10403#define DDRC_DRAMTMG13_t_ccd_mw_SHIFT (16U)
10404#define DDRC_DRAMTMG13_t_ccd_mw(x) \
10405 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_t_ccd_mw_SHIFT)) & DDRC_DRAMTMG13_t_ccd_mw_MASK)
10406#define DDRC_DRAMTMG13_odtloff_MASK (0x7F000000U)
10407#define DDRC_DRAMTMG13_odtloff_SHIFT (24U)
10408#define DDRC_DRAMTMG13_odtloff(x) \
10409 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_odtloff_SHIFT)) & DDRC_DRAMTMG13_odtloff_MASK)
10410/*! @} */
10411
10412/*! @name DRAMTMG14 - SDRAM Timing Register 14 */
10413/*! @{ */
10414#define DDRC_DRAMTMG14_t_xsr_MASK (0xFFFU)
10415#define DDRC_DRAMTMG14_t_xsr_SHIFT (0U)
10416#define DDRC_DRAMTMG14_t_xsr(x) \
10417 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG14_t_xsr_SHIFT)) & DDRC_DRAMTMG14_t_xsr_MASK)
10418/*! @} */
10419
10420/*! @name DRAMTMG15 - SDRAM Timing Register 15 */
10421/*! @{ */
10422#define DDRC_DRAMTMG15_t_stab_x32_MASK (0xFFU)
10423#define DDRC_DRAMTMG15_t_stab_x32_SHIFT (0U)
10424#define DDRC_DRAMTMG15_t_stab_x32(x) \
10425 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_t_stab_x32_SHIFT)) & DDRC_DRAMTMG15_t_stab_x32_MASK)
10426#define DDRC_DRAMTMG15_en_dfi_lp_t_stab_MASK (0x80000000U)
10427#define DDRC_DRAMTMG15_en_dfi_lp_t_stab_SHIFT (31U)
10428/*! en_dfi_lp_t_stab - Enable DFI tSTAB
10429 * 0b0..Disable using tSTAB when exiting DFI LP
10430 * 0b1..Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to
10431 * save maximum power.
10432 */
10433#define DDRC_DRAMTMG15_en_dfi_lp_t_stab(x) \
10434 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_en_dfi_lp_t_stab_SHIFT)) & DDRC_DRAMTMG15_en_dfi_lp_t_stab_MASK)
10435/*! @} */
10436
10437/*! @name ZQCTL0 - ZQ Control Register 0 */
10438/*! @{ */
10439#define DDRC_ZQCTL0_t_zq_short_nop_MASK (0x3FFU)
10440#define DDRC_ZQCTL0_t_zq_short_nop_SHIFT (0U)
10441#define DDRC_ZQCTL0_t_zq_short_nop(x) \
10442 (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_t_zq_short_nop_SHIFT)) & DDRC_ZQCTL0_t_zq_short_nop_MASK)
10443#define DDRC_ZQCTL0_t_zq_long_nop_MASK (0x7FF0000U)
10444#define DDRC_ZQCTL0_t_zq_long_nop_SHIFT (16U)
10445#define DDRC_ZQCTL0_t_zq_long_nop(x) \
10446 (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_t_zq_long_nop_SHIFT)) & DDRC_ZQCTL0_t_zq_long_nop_MASK)
10447#define DDRC_ZQCTL0_dis_mpsmx_zqcl_MASK (0x10000000U)
10448#define DDRC_ZQCTL0_dis_mpsmx_zqcl_SHIFT (28U)
10449/*! dis_mpsmx_zqcl - Do not issue ZQCL command at Maximum Power Save Mode exit if the DDRC_SHARED_AC
10450 * configuration parameter is set. Program it to 1'b1. The software can send ZQCS after exiting
10451 * MPSM mode.
10452 * 0b0..Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode.
10453 * This is only present for designs supporting DDR4 devices.
10454 * 0b1..Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode.
10455 */
10456#define DDRC_ZQCTL0_dis_mpsmx_zqcl(x) \
10457 (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_mpsmx_zqcl_SHIFT)) & DDRC_ZQCTL0_dis_mpsmx_zqcl_MASK)
10458#define DDRC_ZQCTL0_zq_resistor_shared_MASK (0x20000000U)
10459#define DDRC_ZQCTL0_zq_resistor_shared_SHIFT (29U)
10460/*! zq_resistor_shared - ZQ resistor sharing
10461 * 0b0..ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4
10462 * devices. 0b1..Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands
10463 * are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to
10464 * different ranks do not overlap.
10465 */
10466#define DDRC_ZQCTL0_zq_resistor_shared(x) \
10467 (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_zq_resistor_shared_SHIFT)) & DDRC_ZQCTL0_zq_resistor_shared_MASK)
10468#define DDRC_ZQCTL0_dis_srx_zqcl_MASK (0x40000000U)
10469#define DDRC_ZQCTL0_dis_srx_zqcl_SHIFT (30U)
10470/*! dis_srx_zqcl - Disable ZQCL/MPC
10471 * 0b0..Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable
10472 * when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs supporting
10473 * DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
10474 * 0b1..Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable
10475 * when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode.
10476 */
10477#define DDRC_ZQCTL0_dis_srx_zqcl(x) \
10478 (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_srx_zqcl_SHIFT)) & DDRC_ZQCTL0_dis_srx_zqcl_MASK)
10479#define DDRC_ZQCTL0_dis_auto_zq_MASK (0x80000000U)
10480#define DDRC_ZQCTL0_dis_auto_zq_SHIFT (31U)
10481/*! dis_auto_zq - Disable Auto ZQCS/MPC
10482 * 0b0..Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024.
10483 * 0b1..Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used
10484 * instead to issue ZQ calibration request from APB module.
10485 */
10486#define DDRC_ZQCTL0_dis_auto_zq(x) \
10487 (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_auto_zq_SHIFT)) & DDRC_ZQCTL0_dis_auto_zq_MASK)
10488/*! @} */
10489
10490/*! @name ZQCTL1 - ZQ Control Register 1 */
10491/*! @{ */
10492#define DDRC_ZQCTL1_t_zq_short_interval_x1024_MASK (0xFFFFFU)
10493#define DDRC_ZQCTL1_t_zq_short_interval_x1024_SHIFT (0U)
10494#define DDRC_ZQCTL1_t_zq_short_interval_x1024(x) \
10495 (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_t_zq_short_interval_x1024_SHIFT)) & \
10496 DDRC_ZQCTL1_t_zq_short_interval_x1024_MASK)
10497#define DDRC_ZQCTL1_t_zq_reset_nop_MASK (0x3FF00000U)
10498#define DDRC_ZQCTL1_t_zq_reset_nop_SHIFT (20U)
10499#define DDRC_ZQCTL1_t_zq_reset_nop(x) \
10500 (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_t_zq_reset_nop_SHIFT)) & DDRC_ZQCTL1_t_zq_reset_nop_MASK)
10501/*! @} */
10502
10503/*! @name ZQCTL2 - ZQ Control Register 2 */
10504/*! @{ */
10505#define DDRC_ZQCTL2_zq_reset_MASK (0x1U)
10506#define DDRC_ZQCTL2_zq_reset_SHIFT (0U)
10507#define DDRC_ZQCTL2_zq_reset(x) \
10508 (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL2_zq_reset_SHIFT)) & DDRC_ZQCTL2_zq_reset_MASK)
10509/*! @} */
10510
10511/*! @name ZQSTAT - ZQ Status Register */
10512/*! @{ */
10513#define DDRC_ZQSTAT_zq_reset_busy_MASK (0x1U)
10514#define DDRC_ZQSTAT_zq_reset_busy_SHIFT (0U)
10515/*! zq_reset_busy - SoC core may initiate a ZQ Reset operation only if this signal is low. This
10516 * signal goes high in the clock after the DDRC accepts the ZQ Reset request. It goes low when the ZQ
10517 * Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended
10518 * not to perform ZQ Reset commands when this signal is high.
10519 * 0b0..Indicates that the SoC core can initiate a ZQ Reset operation
10520 * 0b1..Indicates that ZQ Reset operation is in progress
10521 */
10522#define DDRC_ZQSTAT_zq_reset_busy(x) \
10523 (((uint32_t)(((uint32_t)(x)) << DDRC_ZQSTAT_zq_reset_busy_SHIFT)) & DDRC_ZQSTAT_zq_reset_busy_MASK)
10524/*! @} */
10525
10526/*! @name DFITMG0 - DFI Timing Register 0 */
10527/*! @{ */
10528#define DDRC_DFITMG0_dfi_tphy_wrlat_MASK (0x3FU)
10529#define DDRC_DFITMG0_dfi_tphy_wrlat_SHIFT (0U)
10530#define DDRC_DFITMG0_dfi_tphy_wrlat(x) \
10531 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_tphy_wrlat_SHIFT)) & DDRC_DFITMG0_dfi_tphy_wrlat_MASK)
10532#define DDRC_DFITMG0_dfi_tphy_wrdata_MASK (0x3F00U)
10533#define DDRC_DFITMG0_dfi_tphy_wrdata_SHIFT (8U)
10534#define DDRC_DFITMG0_dfi_tphy_wrdata(x) \
10535 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_tphy_wrdata_SHIFT)) & DDRC_DFITMG0_dfi_tphy_wrdata_MASK)
10536#define DDRC_DFITMG0_dfi_wrdata_use_sdr_MASK (0x8000U)
10537#define DDRC_DFITMG0_dfi_wrdata_use_sdr_SHIFT (15U)
10538#define DDRC_DFITMG0_dfi_wrdata_use_sdr(x) \
10539 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_wrdata_use_sdr_SHIFT)) & DDRC_DFITMG0_dfi_wrdata_use_sdr_MASK)
10540#define DDRC_DFITMG0_dfi_t_rddata_en_MASK (0x7F0000U)
10541#define DDRC_DFITMG0_dfi_t_rddata_en_SHIFT (16U)
10542#define DDRC_DFITMG0_dfi_t_rddata_en(x) \
10543 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_t_rddata_en_SHIFT)) & DDRC_DFITMG0_dfi_t_rddata_en_MASK)
10544#define DDRC_DFITMG0_dfi_rddata_use_sdr_MASK (0x800000U)
10545#define DDRC_DFITMG0_dfi_rddata_use_sdr_SHIFT (23U)
10546#define DDRC_DFITMG0_dfi_rddata_use_sdr(x) \
10547 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_rddata_use_sdr_SHIFT)) & DDRC_DFITMG0_dfi_rddata_use_sdr_MASK)
10548#define DDRC_DFITMG0_dfi_t_ctrl_delay_MASK (0x1F000000U)
10549#define DDRC_DFITMG0_dfi_t_ctrl_delay_SHIFT (24U)
10550#define DDRC_DFITMG0_dfi_t_ctrl_delay(x) \
10551 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_t_ctrl_delay_SHIFT)) & DDRC_DFITMG0_dfi_t_ctrl_delay_MASK)
10552/*! @} */
10553
10554/*! @name DFITMG1 - DFI Timing Register 1 */
10555/*! @{ */
10556#define DDRC_DFITMG1_dfi_t_dram_clk_enable_MASK (0x1FU)
10557#define DDRC_DFITMG1_dfi_t_dram_clk_enable_SHIFT (0U)
10558#define DDRC_DFITMG1_dfi_t_dram_clk_enable(x) \
10559 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_dram_clk_enable_SHIFT)) & \
10560 DDRC_DFITMG1_dfi_t_dram_clk_enable_MASK)
10561#define DDRC_DFITMG1_dfi_t_dram_clk_disable_MASK (0x1F00U)
10562#define DDRC_DFITMG1_dfi_t_dram_clk_disable_SHIFT (8U)
10563#define DDRC_DFITMG1_dfi_t_dram_clk_disable(x) \
10564 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_dram_clk_disable_SHIFT)) & \
10565 DDRC_DFITMG1_dfi_t_dram_clk_disable_MASK)
10566#define DDRC_DFITMG1_dfi_t_wrdata_delay_MASK (0x1F0000U)
10567#define DDRC_DFITMG1_dfi_t_wrdata_delay_SHIFT (16U)
10568#define DDRC_DFITMG1_dfi_t_wrdata_delay(x) \
10569 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_wrdata_delay_SHIFT)) & DDRC_DFITMG1_dfi_t_wrdata_delay_MASK)
10570#define DDRC_DFITMG1_dfi_t_parin_lat_MASK (0x3000000U)
10571#define DDRC_DFITMG1_dfi_t_parin_lat_SHIFT (24U)
10572#define DDRC_DFITMG1_dfi_t_parin_lat(x) \
10573 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_parin_lat_SHIFT)) & DDRC_DFITMG1_dfi_t_parin_lat_MASK)
10574#define DDRC_DFITMG1_dfi_t_cmd_lat_MASK (0xF0000000U)
10575#define DDRC_DFITMG1_dfi_t_cmd_lat_SHIFT (28U)
10576#define DDRC_DFITMG1_dfi_t_cmd_lat(x) \
10577 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_cmd_lat_SHIFT)) & DDRC_DFITMG1_dfi_t_cmd_lat_MASK)
10578/*! @} */
10579
10580/*! @name DFILPCFG0 - DFI Low Power Configuration Register 0 */
10581/*! @{ */
10582#define DDRC_DFILPCFG0_dfi_lp_en_pd_MASK (0x1U)
10583#define DDRC_DFILPCFG0_dfi_lp_en_pd_SHIFT (0U)
10584#define DDRC_DFILPCFG0_dfi_lp_en_pd(x) \
10585 (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_pd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_pd_MASK)
10586#define DDRC_DFILPCFG0_dfi_lp_wakeup_pd_MASK (0xF0U)
10587#define DDRC_DFILPCFG0_dfi_lp_wakeup_pd_SHIFT (4U)
10588/*! dfi_lp_wakeup_pd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down
10589 * mode is entered. Determines the DFI's tlp_wakeup time:
10590 * 0b0000..16 cycles
10591 * 0b0001..32 cycles
10592 * 0b0010..64 cycles
10593 * 0b0011..128 cycles
10594 * 0b0100..256 cycles
10595 * 0b0101..512 cycles
10596 * 0b0110..1024 cycles
10597 * 0b0111..2048 cycles
10598 * 0b1000..4096 cycles
10599 * 0b1001..8192 cycles
10600 * 0b1010..16384 cycles
10601 * 0b1011..32768 cycles
10602 * 0b1100..65536 cycles
10603 * 0b1101..131072 cycles
10604 * 0b1110..262144 cycles
10605 * 0b1111..Unlimited cycles
10606 */
10607#define DDRC_DFILPCFG0_dfi_lp_wakeup_pd(x) \
10608 (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_pd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_pd_MASK)
10609#define DDRC_DFILPCFG0_dfi_lp_en_sr_MASK (0x100U)
10610#define DDRC_DFILPCFG0_dfi_lp_en_sr_SHIFT (8U)
10611/*! dfi_lp_en_sr - Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 -
10612 * Enabled 0b0..Disabled 0b1..Enabled
10613 */
10614#define DDRC_DFILPCFG0_dfi_lp_en_sr(x) \
10615 (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_sr_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_sr_MASK)
10616#define DDRC_DFILPCFG0_dfi_lp_wakeup_sr_MASK (0xF000U)
10617#define DDRC_DFILPCFG0_dfi_lp_wakeup_sr_SHIFT (12U)
10618/*! dfi_lp_wakeup_sr - Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh
10619 * mode is entered. Determines the DFI's tlp_wakeup time:
10620 * 0b0000..16 cycles
10621 * 0b0001..32 cycles
10622 * 0b0010..64 cycles
10623 * 0b0011..128 cycles
10624 * 0b0100..256 cycles
10625 * 0b0101..512 cycles
10626 * 0b0110..1024 cycles
10627 * 0b0111..2048 cycles
10628 * 0b1000..4096 cycles
10629 * 0b1001..8192 cycles
10630 * 0b1010..16384 cycles
10631 * 0b1011..32768 cycles
10632 * 0b1100..65536 cycles
10633 * 0b1101..131072 cycles
10634 * 0b1110..262144 cycles
10635 * 0b1111..Unlimited cycles
10636 */
10637#define DDRC_DFILPCFG0_dfi_lp_wakeup_sr(x) \
10638 (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_sr_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_sr_MASK)
10639#define DDRC_DFILPCFG0_dfi_lp_en_dpd_MASK (0x10000U)
10640#define DDRC_DFILPCFG0_dfi_lp_en_dpd_SHIFT (16U)
10641#define DDRC_DFILPCFG0_dfi_lp_en_dpd(x) \
10642 (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_dpd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_dpd_MASK)
10643#define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_MASK (0xF00000U)
10644#define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_SHIFT (20U)
10645/*! dfi_lp_wakeup_dpd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power
10646 * Down mode is entered. Determines the DFI's tlp_wakeup time: This is only present for designs
10647 * supporting mDDR or LPDDR2/LPDDR3 devices.
10648 * 0b0000..16 cycles
10649 * 0b0001..32 cycles
10650 * 0b0010..64 cycles
10651 * 0b0011..128 cycles
10652 * 0b0100..256 cycles
10653 * 0b0101..512 cycles
10654 * 0b0110..1024 cycles
10655 * 0b0111..2048 cycles
10656 * 0b1000..4096 cycles
10657 * 0b1001..8192 cycles
10658 * 0b1010..16384 cycles
10659 * 0b1011..32768 cycles
10660 * 0b1100..65536 cycles
10661 * 0b1101..131072 cycles
10662 * 0b1110..262144 cycles
10663 * 0b1111..Unlimited cycles
10664 */
10665#define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd(x) \
10666 (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_MASK)
10667#define DDRC_DFILPCFG0_dfi_tlp_resp_MASK (0x1F000000U)
10668#define DDRC_DFILPCFG0_dfi_tlp_resp_SHIFT (24U)
10669#define DDRC_DFILPCFG0_dfi_tlp_resp(x) \
10670 (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_tlp_resp_SHIFT)) & DDRC_DFILPCFG0_dfi_tlp_resp_MASK)
10671/*! @} */
10672
10673/*! @name DFILPCFG1 - DFI Low Power Configuration Register 1 */
10674/*! @{ */
10675#define DDRC_DFILPCFG1_dfi_lp_en_mpsm_MASK (0x1U)
10676#define DDRC_DFILPCFG1_dfi_lp_en_mpsm_SHIFT (0U)
10677#define DDRC_DFILPCFG1_dfi_lp_en_mpsm(x) \
10678 (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG1_dfi_lp_en_mpsm_SHIFT)) & DDRC_DFILPCFG1_dfi_lp_en_mpsm_MASK)
10679#define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_MASK (0xF0U)
10680#define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_SHIFT (4U)
10681/*! dfi_lp_wakeup_mpsm - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum
10682 * Power Saving Mode is entered. Determines the DFI's tlp_wakeup time:
10683 * 0b0000..16 cycles
10684 * 0b0001..32 cycles
10685 * 0b0010..64 cycles
10686 * 0b0011..128 cycles
10687 * 0b0100..256 cycles
10688 * 0b0101..512 cycles
10689 * 0b0110..1024 cycles
10690 * 0b0111..2048 cycles
10691 * 0b1000..4096 cycles
10692 * 0b1001..8192 cycles
10693 * 0b1010..16384 cycles
10694 * 0b1011..32768 cycles
10695 * 0b1100..65536 cycles
10696 * 0b1101..131072 cycles
10697 * 0b1110..262144 cycles
10698 * 0b1111..Unlimited cycles
10699 */
10700#define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm(x) \
10701 (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_SHIFT)) & DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_MASK)
10702/*! @} */
10703
10704/*! @name DFIUPD0 - DFI Update Register 0 */
10705/*! @{ */
10706#define DDRC_DFIUPD0_dfi_t_ctrlup_min_MASK (0x3FFU)
10707#define DDRC_DFIUPD0_dfi_t_ctrlup_min_SHIFT (0U)
10708#define DDRC_DFIUPD0_dfi_t_ctrlup_min(x) \
10709 (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dfi_t_ctrlup_min_SHIFT)) & DDRC_DFIUPD0_dfi_t_ctrlup_min_MASK)
10710#define DDRC_DFIUPD0_dfi_t_ctrlup_max_MASK (0x3FF0000U)
10711#define DDRC_DFIUPD0_dfi_t_ctrlup_max_SHIFT (16U)
10712#define DDRC_DFIUPD0_dfi_t_ctrlup_max(x) \
10713 (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dfi_t_ctrlup_max_SHIFT)) & DDRC_DFIUPD0_dfi_t_ctrlup_max_MASK)
10714#define DDRC_DFIUPD0_ctrlupd_pre_srx_MASK (0x20000000U)
10715#define DDRC_DFIUPD0_ctrlupd_pre_srx_SHIFT (29U)
10716/*! ctrlupd_pre_srx - Selects dfi_ctrlupd_req requirements at SRX: - 0 : send ctrlupd after SRX - 1
10717 * : send ctrlupd before SRX If DFIUPD0.dis_auto_ctrlupd_srx=1, this register has no impact,
10718 * because no dfi_ctrlupd_req will be issued when SRX.
10719 * 0b0..send ctrlupd after SRX
10720 * 0b1..send ctrlupd before SRX
10721 */
10722#define DDRC_DFIUPD0_ctrlupd_pre_srx(x) \
10723 (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_ctrlupd_pre_srx_SHIFT)) & DDRC_DFIUPD0_ctrlupd_pre_srx_MASK)
10724#define DDRC_DFIUPD0_dis_auto_ctrlupd_srx_MASK (0x40000000U)
10725#define DDRC_DFIUPD0_dis_auto_ctrlupd_srx_SHIFT (30U)
10726/*! dis_auto_ctrlupd_srx - Auto ctrlupd request generation
10727 * 0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC at self-refresh exit.
10728 * 0b0..DDRC issues a dfi_ctrlupd_req before or after exiting self-refresh, depending on DFIUPD0.ctrlupd_pre_srx.
10729 */
10730#define DDRC_DFIUPD0_dis_auto_ctrlupd_srx(x) \
10731 (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dis_auto_ctrlupd_srx_SHIFT)) & DDRC_DFIUPD0_dis_auto_ctrlupd_srx_MASK)
10732#define DDRC_DFIUPD0_dis_auto_ctrlupd_MASK (0x80000000U)
10733#define DDRC_DFIUPD0_dis_auto_ctrlupd_SHIFT (31U)
10734/*! dis_auto_ctrlupd - automatic dfi_ctrlupd_req generation by the DDRC
10735 * 0b0..DDRC issues dfi_ctrlupd_req periodically.
10736 * 0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC. The core must issue the dfi_ctrlupd_req
10737 * signal using register reg_ddrc_ctrlupd.
10738 */
10739#define DDRC_DFIUPD0_dis_auto_ctrlupd(x) \
10740 (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dis_auto_ctrlupd_SHIFT)) & DDRC_DFIUPD0_dis_auto_ctrlupd_MASK)
10741/*! @} */
10742
10743/*! @name DFIUPD1 - DFI Update Register 1 */
10744/*! @{ */
10745#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_MASK (0xFFU)
10746#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_SHIFT (0U)
10747#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024(x) \
10748 (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_SHIFT)) & \
10749 DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_MASK)
10750#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_MASK (0xFF0000U)
10751#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_SHIFT (16U)
10752#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024(x) \
10753 (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_SHIFT)) & \
10754 DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_MASK)
10755/*! @} */
10756
10757/*! @name DFIUPD2 - DFI Update Register 2 */
10758/*! @{ */
10759#define DDRC_DFIUPD2_dfi_phyupd_en_MASK (0x80000000U)
10760#define DDRC_DFIUPD2_dfi_phyupd_en_SHIFT (31U)
10761/*! dfi_phyupd_en - Enables the support for acknowledging PHY-initiated updates:
10762 * 0b0..Disabled
10763 * 0b1..Enabled
10764 */
10765#define DDRC_DFIUPD2_dfi_phyupd_en(x) \
10766 (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD2_dfi_phyupd_en_SHIFT)) & DDRC_DFIUPD2_dfi_phyupd_en_MASK)
10767/*! @} */
10768
10769/*! @name DFIMISC - DFI Miscellaneous Control Register */
10770/*! @{ */
10771#define DDRC_DFIMISC_dfi_init_complete_en_MASK (0x1U)
10772#define DDRC_DFIMISC_dfi_init_complete_en_SHIFT (0U)
10773#define DDRC_DFIMISC_dfi_init_complete_en(x) \
10774 (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_init_complete_en_SHIFT)) & DDRC_DFIMISC_dfi_init_complete_en_MASK)
10775#define DDRC_DFIMISC_phy_dbi_mode_MASK (0x2U)
10776#define DDRC_DFIMISC_phy_dbi_mode_SHIFT (1U)
10777/*! phy_dbi_mode - DBI implemented in DDRC or PHY. Present only in designs configured to support DDR4 and LPDDR4.
10778 * 0b0..DDRC implements DBI functionality.
10779 * 0b1..PHY implements DBI functionality.
10780 */
10781#define DDRC_DFIMISC_phy_dbi_mode(x) \
10782 (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_phy_dbi_mode_SHIFT)) & DDRC_DFIMISC_phy_dbi_mode_MASK)
10783#define DDRC_DFIMISC_dfi_data_cs_polarity_MASK (0x4U)
10784#define DDRC_DFIMISC_dfi_data_cs_polarity_SHIFT (2U)
10785/*! dfi_data_cs_polarity - Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals.
10786 * 0b0..Signals are active low
10787 * 0b1..Signals are active high
10788 */
10789#define DDRC_DFIMISC_dfi_data_cs_polarity(x) \
10790 (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_data_cs_polarity_SHIFT)) & DDRC_DFIMISC_dfi_data_cs_polarity_MASK)
10791#define DDRC_DFIMISC_ctl_idle_en_MASK (0x10U)
10792#define DDRC_DFIMISC_ctl_idle_en_SHIFT (4U)
10793#define DDRC_DFIMISC_ctl_idle_en(x) \
10794 (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_ctl_idle_en_SHIFT)) & DDRC_DFIMISC_ctl_idle_en_MASK)
10795#define DDRC_DFIMISC_dfi_init_start_MASK (0x20U)
10796#define DDRC_DFIMISC_dfi_init_start_SHIFT (5U)
10797#define DDRC_DFIMISC_dfi_init_start(x) \
10798 (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_init_start_SHIFT)) & DDRC_DFIMISC_dfi_init_start_MASK)
10799#define DDRC_DFIMISC_dfi_frequency_MASK (0x1F00U)
10800#define DDRC_DFIMISC_dfi_frequency_SHIFT (8U)
10801#define DDRC_DFIMISC_dfi_frequency(x) \
10802 (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_frequency_SHIFT)) & DDRC_DFIMISC_dfi_frequency_MASK)
10803/*! @} */
10804
10805/*! @name DFITMG2 - DFI Timing Register 2 */
10806/*! @{ */
10807#define DDRC_DFITMG2_dfi_tphy_wrcslat_MASK (0x3FU)
10808#define DDRC_DFITMG2_dfi_tphy_wrcslat_SHIFT (0U)
10809#define DDRC_DFITMG2_dfi_tphy_wrcslat(x) \
10810 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_dfi_tphy_wrcslat_SHIFT)) & DDRC_DFITMG2_dfi_tphy_wrcslat_MASK)
10811#define DDRC_DFITMG2_dfi_tphy_rdcslat_MASK (0x7F00U)
10812#define DDRC_DFITMG2_dfi_tphy_rdcslat_SHIFT (8U)
10813#define DDRC_DFITMG2_dfi_tphy_rdcslat(x) \
10814 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_dfi_tphy_rdcslat_SHIFT)) & DDRC_DFITMG2_dfi_tphy_rdcslat_MASK)
10815/*! @} */
10816
10817/*! @name DFITMG3 - DFI Timing Register 3 */
10818/*! @{ */
10819#define DDRC_DFITMG3_dfi_t_geardown_delay_MASK (0x1FU)
10820#define DDRC_DFITMG3_dfi_t_geardown_delay_SHIFT (0U)
10821#define DDRC_DFITMG3_dfi_t_geardown_delay(x) \
10822 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG3_dfi_t_geardown_delay_SHIFT)) & DDRC_DFITMG3_dfi_t_geardown_delay_MASK)
10823/*! @} */
10824
10825/*! @name DFISTAT - DFI Status Register */
10826/*! @{ */
10827#define DDRC_DFISTAT_dfi_init_complete_MASK (0x1U)
10828#define DDRC_DFISTAT_dfi_init_complete_SHIFT (0U)
10829#define DDRC_DFISTAT_dfi_init_complete(x) \
10830 (((uint32_t)(((uint32_t)(x)) << DDRC_DFISTAT_dfi_init_complete_SHIFT)) & DDRC_DFISTAT_dfi_init_complete_MASK)
10831#define DDRC_DFISTAT_dfi_lp_ack_MASK (0x2U)
10832#define DDRC_DFISTAT_dfi_lp_ack_SHIFT (1U)
10833#define DDRC_DFISTAT_dfi_lp_ack(x) \
10834 (((uint32_t)(((uint32_t)(x)) << DDRC_DFISTAT_dfi_lp_ack_SHIFT)) & DDRC_DFISTAT_dfi_lp_ack_MASK)
10835/*! @} */
10836
10837/*! @name DBICTL - DM/DBI Control Register */
10838/*! @{ */
10839#define DDRC_DBICTL_dm_en_MASK (0x1U)
10840#define DDRC_DBICTL_dm_en_SHIFT (0U)
10841/*! dm_en - DM enable signal in DDRC. This signal must be set the same logical value as DRAM's mode
10842 * register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal
10843 * must be set to 0. - LPDDR4: Set this to inverted value of MR13[5] which is opposite polarity
10844 * from this signal
10845 * 0b0..DM is disabled
10846 * 0b1..DM is enabled
10847 */
10848#define DDRC_DBICTL_dm_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_dm_en_SHIFT)) & DDRC_DBICTL_dm_en_MASK)
10849#define DDRC_DBICTL_wr_dbi_en_MASK (0x2U)
10850#define DDRC_DBICTL_wr_dbi_en_SHIFT (1U)
10851/*! wr_dbi_en - This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A11.
10852 * When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]
10853 * 0b0..Write DBI is disabled
10854 * 0b1..Write DBI is enabled.
10855 */
10856#define DDRC_DBICTL_wr_dbi_en(x) \
10857 (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_wr_dbi_en_SHIFT)) & DDRC_DBICTL_wr_dbi_en_MASK)
10858#define DDRC_DBICTL_rd_dbi_en_MASK (0x4U)
10859#define DDRC_DBICTL_rd_dbi_en_SHIFT (2U)
10860#define DDRC_DBICTL_rd_dbi_en(x) \
10861 (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_rd_dbi_en_SHIFT)) & DDRC_DBICTL_rd_dbi_en_MASK)
10862/*! @} */
10863
10864/*! @name ADDRMAP0 - Address Map Register 0 */
10865/*! @{ */
10866#define DDRC_ADDRMAP0_addrmap_cs_bit0_MASK (0x1FU)
10867#define DDRC_ADDRMAP0_addrmap_cs_bit0_SHIFT (0U)
10868#define DDRC_ADDRMAP0_addrmap_cs_bit0(x) \
10869 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP0_addrmap_cs_bit0_SHIFT)) & DDRC_ADDRMAP0_addrmap_cs_bit0_MASK)
10870/*! @} */
10871
10872/*! @name ADDRMAP1 - Address Map Register 1 */
10873/*! @{ */
10874#define DDRC_ADDRMAP1_addrmap_bank_b0_MASK (0x1FU)
10875#define DDRC_ADDRMAP1_addrmap_bank_b0_SHIFT (0U)
10876#define DDRC_ADDRMAP1_addrmap_bank_b0(x) \
10877 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b0_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b0_MASK)
10878#define DDRC_ADDRMAP1_addrmap_bank_b1_MASK (0x1F00U)
10879#define DDRC_ADDRMAP1_addrmap_bank_b1_SHIFT (8U)
10880#define DDRC_ADDRMAP1_addrmap_bank_b1(x) \
10881 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b1_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b1_MASK)
10882#define DDRC_ADDRMAP1_addrmap_bank_b2_MASK (0x1F0000U)
10883#define DDRC_ADDRMAP1_addrmap_bank_b2_SHIFT (16U)
10884#define DDRC_ADDRMAP1_addrmap_bank_b2(x) \
10885 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b2_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b2_MASK)
10886/*! @} */
10887
10888/*! @name ADDRMAP2 - Address Map Register 2 */
10889/*! @{ */
10890#define DDRC_ADDRMAP2_addrmap_col_b2_MASK (0xFU)
10891#define DDRC_ADDRMAP2_addrmap_col_b2_SHIFT (0U)
10892#define DDRC_ADDRMAP2_addrmap_col_b2(x) \
10893 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b2_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b2_MASK)
10894#define DDRC_ADDRMAP2_addrmap_col_b3_MASK (0xF00U)
10895#define DDRC_ADDRMAP2_addrmap_col_b3_SHIFT (8U)
10896#define DDRC_ADDRMAP2_addrmap_col_b3(x) \
10897 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b3_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b3_MASK)
10898#define DDRC_ADDRMAP2_addrmap_col_b4_MASK (0xF0000U)
10899#define DDRC_ADDRMAP2_addrmap_col_b4_SHIFT (16U)
10900#define DDRC_ADDRMAP2_addrmap_col_b4(x) \
10901 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b4_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b4_MASK)
10902#define DDRC_ADDRMAP2_addrmap_col_b5_MASK (0xF000000U)
10903#define DDRC_ADDRMAP2_addrmap_col_b5_SHIFT (24U)
10904#define DDRC_ADDRMAP2_addrmap_col_b5(x) \
10905 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b5_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b5_MASK)
10906/*! @} */
10907
10908/*! @name ADDRMAP3 - Address Map Register 3 */
10909/*! @{ */
10910#define DDRC_ADDRMAP3_addrmap_col_b6_MASK (0xFU)
10911#define DDRC_ADDRMAP3_addrmap_col_b6_SHIFT (0U)
10912#define DDRC_ADDRMAP3_addrmap_col_b6(x) \
10913 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b6_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b6_MASK)
10914#define DDRC_ADDRMAP3_addrmap_col_b7_MASK (0xF00U)
10915#define DDRC_ADDRMAP3_addrmap_col_b7_SHIFT (8U)
10916#define DDRC_ADDRMAP3_addrmap_col_b7(x) \
10917 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b7_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b7_MASK)
10918#define DDRC_ADDRMAP3_addrmap_col_b8_MASK (0xF0000U)
10919#define DDRC_ADDRMAP3_addrmap_col_b8_SHIFT (16U)
10920#define DDRC_ADDRMAP3_addrmap_col_b8(x) \
10921 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b8_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b8_MASK)
10922#define DDRC_ADDRMAP3_addrmap_col_b9_MASK (0xF000000U)
10923#define DDRC_ADDRMAP3_addrmap_col_b9_SHIFT (24U)
10924#define DDRC_ADDRMAP3_addrmap_col_b9(x) \
10925 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b9_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b9_MASK)
10926/*! @} */
10927
10928/*! @name ADDRMAP4 - Address Map Register 4 */
10929/*! @{ */
10930#define DDRC_ADDRMAP4_addrmap_col_b10_MASK (0xFU)
10931#define DDRC_ADDRMAP4_addrmap_col_b10_SHIFT (0U)
10932#define DDRC_ADDRMAP4_addrmap_col_b10(x) \
10933 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP4_addrmap_col_b10_SHIFT)) & DDRC_ADDRMAP4_addrmap_col_b10_MASK)
10934#define DDRC_ADDRMAP4_addrmap_col_b11_MASK (0xF00U)
10935#define DDRC_ADDRMAP4_addrmap_col_b11_SHIFT (8U)
10936#define DDRC_ADDRMAP4_addrmap_col_b11(x) \
10937 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP4_addrmap_col_b11_SHIFT)) & DDRC_ADDRMAP4_addrmap_col_b11_MASK)
10938/*! @} */
10939
10940/*! @name ADDRMAP5 - Address Map Register 5 */
10941/*! @{ */
10942#define DDRC_ADDRMAP5_addrmap_row_b0_MASK (0xFU)
10943#define DDRC_ADDRMAP5_addrmap_row_b0_SHIFT (0U)
10944#define DDRC_ADDRMAP5_addrmap_row_b0(x) \
10945 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b0_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b0_MASK)
10946#define DDRC_ADDRMAP5_addrmap_row_b1_MASK (0xF00U)
10947#define DDRC_ADDRMAP5_addrmap_row_b1_SHIFT (8U)
10948#define DDRC_ADDRMAP5_addrmap_row_b1(x) \
10949 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b1_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b1_MASK)
10950#define DDRC_ADDRMAP5_addrmap_row_b2_10_MASK (0xF0000U)
10951#define DDRC_ADDRMAP5_addrmap_row_b2_10_SHIFT (16U)
10952#define DDRC_ADDRMAP5_addrmap_row_b2_10(x) \
10953 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b2_10_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b2_10_MASK)
10954#define DDRC_ADDRMAP5_addrmap_row_b11_MASK (0xF000000U)
10955#define DDRC_ADDRMAP5_addrmap_row_b11_SHIFT (24U)
10956#define DDRC_ADDRMAP5_addrmap_row_b11(x) \
10957 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b11_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b11_MASK)
10958/*! @} */
10959
10960/*! @name ADDRMAP6 - Address Map Register 6 */
10961/*! @{ */
10962#define DDRC_ADDRMAP6_addrmap_row_b12_MASK (0xFU)
10963#define DDRC_ADDRMAP6_addrmap_row_b12_SHIFT (0U)
10964#define DDRC_ADDRMAP6_addrmap_row_b12(x) \
10965 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b12_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b12_MASK)
10966#define DDRC_ADDRMAP6_addrmap_row_b13_MASK (0xF00U)
10967#define DDRC_ADDRMAP6_addrmap_row_b13_SHIFT (8U)
10968#define DDRC_ADDRMAP6_addrmap_row_b13(x) \
10969 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b13_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b13_MASK)
10970#define DDRC_ADDRMAP6_addrmap_row_b14_MASK (0xF0000U)
10971#define DDRC_ADDRMAP6_addrmap_row_b14_SHIFT (16U)
10972#define DDRC_ADDRMAP6_addrmap_row_b14(x) \
10973 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b14_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b14_MASK)
10974#define DDRC_ADDRMAP6_addrmap_row_b15_MASK (0xF000000U)
10975#define DDRC_ADDRMAP6_addrmap_row_b15_SHIFT (24U)
10976#define DDRC_ADDRMAP6_addrmap_row_b15(x) \
10977 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b15_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b15_MASK)
10978#define DDRC_ADDRMAP6_lpddr3_6gb_12gb_MASK (0x80000000U)
10979#define DDRC_ADDRMAP6_lpddr3_6gb_12gb_SHIFT (31U)
10980#define DDRC_ADDRMAP6_lpddr3_6gb_12gb(x) \
10981 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_lpddr3_6gb_12gb_SHIFT)) & DDRC_ADDRMAP6_lpddr3_6gb_12gb_MASK)
10982/*! @} */
10983
10984/*! @name ADDRMAP7 - Address Map Register 7 */
10985/*! @{ */
10986#define DDRC_ADDRMAP7_addrmap_row_b16_MASK (0xFU)
10987#define DDRC_ADDRMAP7_addrmap_row_b16_SHIFT (0U)
10988#define DDRC_ADDRMAP7_addrmap_row_b16(x) \
10989 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP7_addrmap_row_b16_SHIFT)) & DDRC_ADDRMAP7_addrmap_row_b16_MASK)
10990#define DDRC_ADDRMAP7_addrmap_row_b17_MASK (0xF00U)
10991#define DDRC_ADDRMAP7_addrmap_row_b17_SHIFT (8U)
10992#define DDRC_ADDRMAP7_addrmap_row_b17(x) \
10993 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP7_addrmap_row_b17_SHIFT)) & DDRC_ADDRMAP7_addrmap_row_b17_MASK)
10994/*! @} */
10995
10996/*! @name ADDRMAP8 - Address Map Register 8 */
10997/*! @{ */
10998#define DDRC_ADDRMAP8_addrmap_bg_b0_MASK (0x1FU)
10999#define DDRC_ADDRMAP8_addrmap_bg_b0_SHIFT (0U)
11000#define DDRC_ADDRMAP8_addrmap_bg_b0(x) \
11001 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP8_addrmap_bg_b0_SHIFT)) & DDRC_ADDRMAP8_addrmap_bg_b0_MASK)
11002#define DDRC_ADDRMAP8_addrmap_bg_b1_MASK (0x3F00U)
11003#define DDRC_ADDRMAP8_addrmap_bg_b1_SHIFT (8U)
11004#define DDRC_ADDRMAP8_addrmap_bg_b1(x) \
11005 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP8_addrmap_bg_b1_SHIFT)) & DDRC_ADDRMAP8_addrmap_bg_b1_MASK)
11006/*! @} */
11007
11008/*! @name ADDRMAP9 - Address Map Register 9 */
11009/*! @{ */
11010#define DDRC_ADDRMAP9_addrmap_row_b2_MASK (0xFU)
11011#define DDRC_ADDRMAP9_addrmap_row_b2_SHIFT (0U)
11012#define DDRC_ADDRMAP9_addrmap_row_b2(x) \
11013 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b2_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b2_MASK)
11014#define DDRC_ADDRMAP9_addrmap_row_b3_MASK (0xF00U)
11015#define DDRC_ADDRMAP9_addrmap_row_b3_SHIFT (8U)
11016#define DDRC_ADDRMAP9_addrmap_row_b3(x) \
11017 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b3_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b3_MASK)
11018#define DDRC_ADDRMAP9_addrmap_row_b4_MASK (0xF0000U)
11019#define DDRC_ADDRMAP9_addrmap_row_b4_SHIFT (16U)
11020#define DDRC_ADDRMAP9_addrmap_row_b4(x) \
11021 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b4_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b4_MASK)
11022#define DDRC_ADDRMAP9_addrmap_row_b5_MASK (0xF000000U)
11023#define DDRC_ADDRMAP9_addrmap_row_b5_SHIFT (24U)
11024#define DDRC_ADDRMAP9_addrmap_row_b5(x) \
11025 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b5_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b5_MASK)
11026/*! @} */
11027
11028/*! @name ADDRMAP10 - Address Map Register 10 */
11029/*! @{ */
11030#define DDRC_ADDRMAP10_addrmap_row_b6_MASK (0xFU)
11031#define DDRC_ADDRMAP10_addrmap_row_b6_SHIFT (0U)
11032#define DDRC_ADDRMAP10_addrmap_row_b6(x) \
11033 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b6_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b6_MASK)
11034#define DDRC_ADDRMAP10_addrmap_row_b7_MASK (0xF00U)
11035#define DDRC_ADDRMAP10_addrmap_row_b7_SHIFT (8U)
11036#define DDRC_ADDRMAP10_addrmap_row_b7(x) \
11037 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b7_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b7_MASK)
11038#define DDRC_ADDRMAP10_addrmap_row_b8_MASK (0xF0000U)
11039#define DDRC_ADDRMAP10_addrmap_row_b8_SHIFT (16U)
11040#define DDRC_ADDRMAP10_addrmap_row_b8(x) \
11041 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b8_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b8_MASK)
11042#define DDRC_ADDRMAP10_addrmap_row_b9_MASK (0xF000000U)
11043#define DDRC_ADDRMAP10_addrmap_row_b9_SHIFT (24U)
11044#define DDRC_ADDRMAP10_addrmap_row_b9(x) \
11045 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b9_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b9_MASK)
11046/*! @} */
11047
11048/*! @name ADDRMAP11 - Address Map Register 11 */
11049/*! @{ */
11050#define DDRC_ADDRMAP11_addrmap_row_b10_MASK (0xFU)
11051#define DDRC_ADDRMAP11_addrmap_row_b10_SHIFT (0U)
11052#define DDRC_ADDRMAP11_addrmap_row_b10(x) \
11053 (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP11_addrmap_row_b10_SHIFT)) & DDRC_ADDRMAP11_addrmap_row_b10_MASK)
11054/*! @} */
11055
11056/*! @name ODTCFG - ODT Configuration Register */
11057/*! @{ */
11058#define DDRC_ODTCFG_rd_odt_delay_MASK (0x7CU)
11059#define DDRC_ODTCFG_rd_odt_delay_SHIFT (2U)
11060#define DDRC_ODTCFG_rd_odt_delay(x) \
11061 (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_rd_odt_delay_SHIFT)) & DDRC_ODTCFG_rd_odt_delay_MASK)
11062#define DDRC_ODTCFG_rd_odt_hold_MASK (0xF00U)
11063#define DDRC_ODTCFG_rd_odt_hold_SHIFT (8U)
11064#define DDRC_ODTCFG_rd_odt_hold(x) \
11065 (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_rd_odt_hold_SHIFT)) & DDRC_ODTCFG_rd_odt_hold_MASK)
11066#define DDRC_ODTCFG_wr_odt_delay_MASK (0x1F0000U)
11067#define DDRC_ODTCFG_wr_odt_delay_SHIFT (16U)
11068#define DDRC_ODTCFG_wr_odt_delay(x) \
11069 (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_wr_odt_delay_SHIFT)) & DDRC_ODTCFG_wr_odt_delay_MASK)
11070#define DDRC_ODTCFG_wr_odt_hold_MASK (0xF000000U)
11071#define DDRC_ODTCFG_wr_odt_hold_SHIFT (24U)
11072#define DDRC_ODTCFG_wr_odt_hold(x) \
11073 (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_wr_odt_hold_SHIFT)) & DDRC_ODTCFG_wr_odt_hold_MASK)
11074/*! @} */
11075
11076/*! @name ODTMAP - ODT/Rank Map Register */
11077/*! @{ */
11078#define DDRC_ODTMAP_rank0_wr_odt_MASK (0x3U)
11079#define DDRC_ODTMAP_rank0_wr_odt_SHIFT (0U)
11080#define DDRC_ODTMAP_rank0_wr_odt(x) \
11081 (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank0_wr_odt_SHIFT)) & DDRC_ODTMAP_rank0_wr_odt_MASK)
11082#define DDRC_ODTMAP_rank0_rd_odt_MASK (0x30U)
11083#define DDRC_ODTMAP_rank0_rd_odt_SHIFT (4U)
11084#define DDRC_ODTMAP_rank0_rd_odt(x) \
11085 (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank0_rd_odt_SHIFT)) & DDRC_ODTMAP_rank0_rd_odt_MASK)
11086#define DDRC_ODTMAP_rank1_wr_odt_MASK (0x300U)
11087#define DDRC_ODTMAP_rank1_wr_odt_SHIFT (8U)
11088#define DDRC_ODTMAP_rank1_wr_odt(x) \
11089 (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank1_wr_odt_SHIFT)) & DDRC_ODTMAP_rank1_wr_odt_MASK)
11090#define DDRC_ODTMAP_rank1_rd_odt_MASK (0x3000U)
11091#define DDRC_ODTMAP_rank1_rd_odt_SHIFT (12U)
11092#define DDRC_ODTMAP_rank1_rd_odt(x) \
11093 (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank1_rd_odt_SHIFT)) & DDRC_ODTMAP_rank1_rd_odt_MASK)
11094/*! @} */
11095
11096/*! @name SCHED - Scheduler Control Register */
11097/*! @{ */
11098#define DDRC_SCHED_force_low_pri_n_MASK (0x1U)
11099#define DDRC_SCHED_force_low_pri_n_SHIFT (0U)
11100#define DDRC_SCHED_force_low_pri_n(x) \
11101 (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_force_low_pri_n_SHIFT)) & DDRC_SCHED_force_low_pri_n_MASK)
11102#define DDRC_SCHED_prefer_write_MASK (0x2U)
11103#define DDRC_SCHED_prefer_write_SHIFT (1U)
11104#define DDRC_SCHED_prefer_write(x) \
11105 (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_prefer_write_SHIFT)) & DDRC_SCHED_prefer_write_MASK)
11106#define DDRC_SCHED_pageclose_MASK (0x4U)
11107#define DDRC_SCHED_pageclose_SHIFT (2U)
11108#define DDRC_SCHED_pageclose(x) \
11109 (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_pageclose_SHIFT)) & DDRC_SCHED_pageclose_MASK)
11110#define DDRC_SCHED_lpr_num_entries_MASK (0x1F00U)
11111#define DDRC_SCHED_lpr_num_entries_SHIFT (8U)
11112#define DDRC_SCHED_lpr_num_entries(x) \
11113 (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_lpr_num_entries_SHIFT)) & DDRC_SCHED_lpr_num_entries_MASK)
11114#define DDRC_SCHED_go2critical_hysteresis_MASK (0xFF0000U)
11115#define DDRC_SCHED_go2critical_hysteresis_SHIFT (16U)
11116#define DDRC_SCHED_go2critical_hysteresis(x) \
11117 (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_go2critical_hysteresis_SHIFT)) & DDRC_SCHED_go2critical_hysteresis_MASK)
11118#define DDRC_SCHED_rdwr_idle_gap_MASK (0x7F000000U)
11119#define DDRC_SCHED_rdwr_idle_gap_SHIFT (24U)
11120#define DDRC_SCHED_rdwr_idle_gap(x) \
11121 (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_rdwr_idle_gap_SHIFT)) & DDRC_SCHED_rdwr_idle_gap_MASK)
11122/*! @} */
11123
11124/*! @name SCHED1 - Scheduler Control Register 1 */
11125/*! @{ */
11126#define DDRC_SCHED1_pageclose_timer_MASK (0xFFU)
11127#define DDRC_SCHED1_pageclose_timer_SHIFT (0U)
11128#define DDRC_SCHED1_pageclose_timer(x) \
11129 (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED1_pageclose_timer_SHIFT)) & DDRC_SCHED1_pageclose_timer_MASK)
11130/*! @} */
11131
11132/*! @name PERFHPR1 - High Priority Read CAM Register 1 */
11133/*! @{ */
11134#define DDRC_PERFHPR1_hpr_max_starve_MASK (0xFFFFU)
11135#define DDRC_PERFHPR1_hpr_max_starve_SHIFT (0U)
11136#define DDRC_PERFHPR1_hpr_max_starve(x) \
11137 (((uint32_t)(((uint32_t)(x)) << DDRC_PERFHPR1_hpr_max_starve_SHIFT)) & DDRC_PERFHPR1_hpr_max_starve_MASK)
11138#define DDRC_PERFHPR1_hpr_xact_run_length_MASK (0xFF000000U)
11139#define DDRC_PERFHPR1_hpr_xact_run_length_SHIFT (24U)
11140#define DDRC_PERFHPR1_hpr_xact_run_length(x) \
11141 (((uint32_t)(((uint32_t)(x)) << DDRC_PERFHPR1_hpr_xact_run_length_SHIFT)) & DDRC_PERFHPR1_hpr_xact_run_length_MASK)
11142/*! @} */
11143
11144/*! @name PERFLPR1 - Low Priority Read CAM Register 1 */
11145/*! @{ */
11146#define DDRC_PERFLPR1_lpr_max_starve_MASK (0xFFFFU)
11147#define DDRC_PERFLPR1_lpr_max_starve_SHIFT (0U)
11148#define DDRC_PERFLPR1_lpr_max_starve(x) \
11149 (((uint32_t)(((uint32_t)(x)) << DDRC_PERFLPR1_lpr_max_starve_SHIFT)) & DDRC_PERFLPR1_lpr_max_starve_MASK)
11150#define DDRC_PERFLPR1_lpr_xact_run_length_MASK (0xFF000000U)
11151#define DDRC_PERFLPR1_lpr_xact_run_length_SHIFT (24U)
11152#define DDRC_PERFLPR1_lpr_xact_run_length(x) \
11153 (((uint32_t)(((uint32_t)(x)) << DDRC_PERFLPR1_lpr_xact_run_length_SHIFT)) & DDRC_PERFLPR1_lpr_xact_run_length_MASK)
11154/*! @} */
11155
11156/*! @name PERFWR1 - Write CAM Register 1 */
11157/*! @{ */
11158#define DDRC_PERFWR1_w_max_starve_MASK (0xFFFFU)
11159#define DDRC_PERFWR1_w_max_starve_SHIFT (0U)
11160#define DDRC_PERFWR1_w_max_starve(x) \
11161 (((uint32_t)(((uint32_t)(x)) << DDRC_PERFWR1_w_max_starve_SHIFT)) & DDRC_PERFWR1_w_max_starve_MASK)
11162#define DDRC_PERFWR1_w_xact_run_length_MASK (0xFF000000U)
11163#define DDRC_PERFWR1_w_xact_run_length_SHIFT (24U)
11164#define DDRC_PERFWR1_w_xact_run_length(x) \
11165 (((uint32_t)(((uint32_t)(x)) << DDRC_PERFWR1_w_xact_run_length_SHIFT)) & DDRC_PERFWR1_w_xact_run_length_MASK)
11166/*! @} */
11167
11168/*! @name DBG0 - Debug Register 0 */
11169/*! @{ */
11170#define DDRC_DBG0_dis_wc_MASK (0x1U)
11171#define DDRC_DBG0_dis_wc_SHIFT (0U)
11172#define DDRC_DBG0_dis_wc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_wc_SHIFT)) & DDRC_DBG0_dis_wc_MASK)
11173#define DDRC_DBG0_dis_rd_bypass_MASK (0x2U)
11174#define DDRC_DBG0_dis_rd_bypass_SHIFT (1U)
11175#define DDRC_DBG0_dis_rd_bypass(x) \
11176 (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_rd_bypass_SHIFT)) & DDRC_DBG0_dis_rd_bypass_MASK)
11177#define DDRC_DBG0_dis_act_bypass_MASK (0x4U)
11178#define DDRC_DBG0_dis_act_bypass_SHIFT (2U)
11179#define DDRC_DBG0_dis_act_bypass(x) \
11180 (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_act_bypass_SHIFT)) & DDRC_DBG0_dis_act_bypass_MASK)
11181#define DDRC_DBG0_dis_collision_page_opt_MASK (0x10U)
11182#define DDRC_DBG0_dis_collision_page_opt_SHIFT (4U)
11183#define DDRC_DBG0_dis_collision_page_opt(x) \
11184 (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_collision_page_opt_SHIFT)) & DDRC_DBG0_dis_collision_page_opt_MASK)
11185/*! @} */
11186
11187/*! @name DBG1 - Debug Register 1 */
11188/*! @{ */
11189#define DDRC_DBG1_dis_dq_MASK (0x1U)
11190#define DDRC_DBG1_dis_dq_SHIFT (0U)
11191#define DDRC_DBG1_dis_dq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG1_dis_dq_SHIFT)) & DDRC_DBG1_dis_dq_MASK)
11192#define DDRC_DBG1_dis_hif_MASK (0x2U)
11193#define DDRC_DBG1_dis_hif_SHIFT (1U)
11194#define DDRC_DBG1_dis_hif(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG1_dis_hif_SHIFT)) & DDRC_DBG1_dis_hif_MASK)
11195/*! @} */
11196
11197/*! @name DBGCAM - CAM Debug Register */
11198/*! @{ */
11199#define DDRC_DBGCAM_dbg_hpr_q_depth_MASK (0x3FU)
11200#define DDRC_DBGCAM_dbg_hpr_q_depth_SHIFT (0U)
11201#define DDRC_DBGCAM_dbg_hpr_q_depth(x) \
11202 (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_hpr_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_hpr_q_depth_MASK)
11203#define DDRC_DBGCAM_dbg_lpr_q_depth_MASK (0x3F00U)
11204#define DDRC_DBGCAM_dbg_lpr_q_depth_SHIFT (8U)
11205#define DDRC_DBGCAM_dbg_lpr_q_depth(x) \
11206 (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_lpr_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_lpr_q_depth_MASK)
11207#define DDRC_DBGCAM_dbg_w_q_depth_MASK (0x3F0000U)
11208#define DDRC_DBGCAM_dbg_w_q_depth_SHIFT (16U)
11209#define DDRC_DBGCAM_dbg_w_q_depth(x) \
11210 (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_w_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_w_q_depth_MASK)
11211#define DDRC_DBGCAM_dbg_stall_MASK (0x1000000U)
11212#define DDRC_DBGCAM_dbg_stall_SHIFT (24U)
11213#define DDRC_DBGCAM_dbg_stall(x) \
11214 (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_SHIFT)) & DDRC_DBGCAM_dbg_stall_MASK)
11215#define DDRC_DBGCAM_dbg_rd_q_empty_MASK (0x2000000U)
11216#define DDRC_DBGCAM_dbg_rd_q_empty_SHIFT (25U)
11217#define DDRC_DBGCAM_dbg_rd_q_empty(x) \
11218 (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_rd_q_empty_SHIFT)) & DDRC_DBGCAM_dbg_rd_q_empty_MASK)
11219#define DDRC_DBGCAM_dbg_wr_q_empty_MASK (0x4000000U)
11220#define DDRC_DBGCAM_dbg_wr_q_empty_SHIFT (26U)
11221#define DDRC_DBGCAM_dbg_wr_q_empty(x) \
11222 (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_wr_q_empty_SHIFT)) & DDRC_DBGCAM_dbg_wr_q_empty_MASK)
11223#define DDRC_DBGCAM_rd_data_pipeline_empty_MASK (0x10000000U)
11224#define DDRC_DBGCAM_rd_data_pipeline_empty_SHIFT (28U)
11225#define DDRC_DBGCAM_rd_data_pipeline_empty(x) \
11226 (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_rd_data_pipeline_empty_SHIFT)) & \
11227 DDRC_DBGCAM_rd_data_pipeline_empty_MASK)
11228#define DDRC_DBGCAM_wr_data_pipeline_empty_MASK (0x20000000U)
11229#define DDRC_DBGCAM_wr_data_pipeline_empty_SHIFT (29U)
11230#define DDRC_DBGCAM_wr_data_pipeline_empty(x) \
11231 (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_wr_data_pipeline_empty_SHIFT)) & \
11232 DDRC_DBGCAM_wr_data_pipeline_empty_MASK)
11233#define DDRC_DBGCAM_dbg_stall_wr_MASK (0x40000000U)
11234#define DDRC_DBGCAM_dbg_stall_wr_SHIFT (30U)
11235#define DDRC_DBGCAM_dbg_stall_wr(x) \
11236 (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_wr_SHIFT)) & DDRC_DBGCAM_dbg_stall_wr_MASK)
11237#define DDRC_DBGCAM_dbg_stall_rd_MASK (0x80000000U)
11238#define DDRC_DBGCAM_dbg_stall_rd_SHIFT (31U)
11239#define DDRC_DBGCAM_dbg_stall_rd(x) \
11240 (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_rd_SHIFT)) & DDRC_DBGCAM_dbg_stall_rd_MASK)
11241/*! @} */
11242
11243/*! @name DBGCMD - Command Debug Register */
11244/*! @{ */
11245#define DDRC_DBGCMD_rank0_refresh_MASK (0x1U)
11246#define DDRC_DBGCMD_rank0_refresh_SHIFT (0U)
11247#define DDRC_DBGCMD_rank0_refresh(x) \
11248 (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_rank0_refresh_SHIFT)) & DDRC_DBGCMD_rank0_refresh_MASK)
11249#define DDRC_DBGCMD_rank1_refresh_MASK (0x2U)
11250#define DDRC_DBGCMD_rank1_refresh_SHIFT (1U)
11251#define DDRC_DBGCMD_rank1_refresh(x) \
11252 (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_rank1_refresh_SHIFT)) & DDRC_DBGCMD_rank1_refresh_MASK)
11253#define DDRC_DBGCMD_zq_calib_short_MASK (0x10U)
11254#define DDRC_DBGCMD_zq_calib_short_SHIFT (4U)
11255#define DDRC_DBGCMD_zq_calib_short(x) \
11256 (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_zq_calib_short_SHIFT)) & DDRC_DBGCMD_zq_calib_short_MASK)
11257#define DDRC_DBGCMD_ctrlupd_MASK (0x20U)
11258#define DDRC_DBGCMD_ctrlupd_SHIFT (5U)
11259#define DDRC_DBGCMD_ctrlupd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_ctrlupd_SHIFT)) & DDRC_DBGCMD_ctrlupd_MASK)
11260/*! @} */
11261
11262/*! @name DBGSTAT - Status Debug Register */
11263/*! @{ */
11264#define DDRC_DBGSTAT_rank0_refresh_busy_MASK (0x1U)
11265#define DDRC_DBGSTAT_rank0_refresh_busy_SHIFT (0U)
11266#define DDRC_DBGSTAT_rank0_refresh_busy(x) \
11267 (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_rank0_refresh_busy_SHIFT)) & DDRC_DBGSTAT_rank0_refresh_busy_MASK)
11268#define DDRC_DBGSTAT_rank1_refresh_busy_MASK (0x2U)
11269#define DDRC_DBGSTAT_rank1_refresh_busy_SHIFT (1U)
11270#define DDRC_DBGSTAT_rank1_refresh_busy(x) \
11271 (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_rank1_refresh_busy_SHIFT)) & DDRC_DBGSTAT_rank1_refresh_busy_MASK)
11272#define DDRC_DBGSTAT_zq_calib_short_busy_MASK (0x10U)
11273#define DDRC_DBGSTAT_zq_calib_short_busy_SHIFT (4U)
11274#define DDRC_DBGSTAT_zq_calib_short_busy(x) \
11275 (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_zq_calib_short_busy_SHIFT)) & DDRC_DBGSTAT_zq_calib_short_busy_MASK)
11276#define DDRC_DBGSTAT_ctrlupd_busy_MASK (0x20U)
11277#define DDRC_DBGSTAT_ctrlupd_busy_SHIFT (5U)
11278#define DDRC_DBGSTAT_ctrlupd_busy(x) \
11279 (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_ctrlupd_busy_SHIFT)) & DDRC_DBGSTAT_ctrlupd_busy_MASK)
11280/*! @} */
11281
11282/*! @name SWCTL - Software Register Programming Control Enable */
11283/*! @{ */
11284#define DDRC_SWCTL_sw_done_MASK (0x1U)
11285#define DDRC_SWCTL_sw_done_SHIFT (0U)
11286#define DDRC_SWCTL_sw_done(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SWCTL_sw_done_SHIFT)) & DDRC_SWCTL_sw_done_MASK)
11287/*! @} */
11288
11289/*! @name SWSTAT - Software Register Programming Control Status */
11290/*! @{ */
11291#define DDRC_SWSTAT_sw_done_ack_MASK (0x1U)
11292#define DDRC_SWSTAT_sw_done_ack_SHIFT (0U)
11293#define DDRC_SWSTAT_sw_done_ack(x) \
11294 (((uint32_t)(((uint32_t)(x)) << DDRC_SWSTAT_sw_done_ack_SHIFT)) & DDRC_SWSTAT_sw_done_ack_MASK)
11295/*! @} */
11296
11297/*! @name POISONCFG - AXI Poison Configuration Register. */
11298/*! @{ */
11299#define DDRC_POISONCFG_wr_poison_slverr_en_MASK (0x1U)
11300#define DDRC_POISONCFG_wr_poison_slverr_en_SHIFT (0U)
11301#define DDRC_POISONCFG_wr_poison_slverr_en(x) \
11302 (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_slverr_en_SHIFT)) & \
11303 DDRC_POISONCFG_wr_poison_slverr_en_MASK)
11304#define DDRC_POISONCFG_wr_poison_intr_en_MASK (0x10U)
11305#define DDRC_POISONCFG_wr_poison_intr_en_SHIFT (4U)
11306#define DDRC_POISONCFG_wr_poison_intr_en(x) \
11307 (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_intr_en_SHIFT)) & DDRC_POISONCFG_wr_poison_intr_en_MASK)
11308#define DDRC_POISONCFG_wr_poison_intr_clr_MASK (0x100U)
11309#define DDRC_POISONCFG_wr_poison_intr_clr_SHIFT (8U)
11310#define DDRC_POISONCFG_wr_poison_intr_clr(x) \
11311 (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_intr_clr_SHIFT)) & DDRC_POISONCFG_wr_poison_intr_clr_MASK)
11312#define DDRC_POISONCFG_rd_poison_slverr_en_MASK (0x10000U)
11313#define DDRC_POISONCFG_rd_poison_slverr_en_SHIFT (16U)
11314#define DDRC_POISONCFG_rd_poison_slverr_en(x) \
11315 (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_slverr_en_SHIFT)) & \
11316 DDRC_POISONCFG_rd_poison_slverr_en_MASK)
11317#define DDRC_POISONCFG_rd_poison_intr_en_MASK (0x100000U)
11318#define DDRC_POISONCFG_rd_poison_intr_en_SHIFT (20U)
11319#define DDRC_POISONCFG_rd_poison_intr_en(x) \
11320 (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_intr_en_SHIFT)) & DDRC_POISONCFG_rd_poison_intr_en_MASK)
11321#define DDRC_POISONCFG_rd_poison_intr_clr_MASK (0x1000000U)
11322#define DDRC_POISONCFG_rd_poison_intr_clr_SHIFT (24U)
11323#define DDRC_POISONCFG_rd_poison_intr_clr(x) \
11324 (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_intr_clr_SHIFT)) & DDRC_POISONCFG_rd_poison_intr_clr_MASK)
11325/*! @} */
11326
11327/*! @name POISONSTAT - AXI Poison Status Register */
11328/*! @{ */
11329#define DDRC_POISONSTAT_wr_poison_intr_0_MASK (0x1U)
11330#define DDRC_POISONSTAT_wr_poison_intr_0_SHIFT (0U)
11331#define DDRC_POISONSTAT_wr_poison_intr_0(x) \
11332 (((uint32_t)(((uint32_t)(x)) << DDRC_POISONSTAT_wr_poison_intr_0_SHIFT)) & DDRC_POISONSTAT_wr_poison_intr_0_MASK)
11333#define DDRC_POISONSTAT_rd_poison_intr_0_MASK (0x10000U)
11334#define DDRC_POISONSTAT_rd_poison_intr_0_SHIFT (16U)
11335#define DDRC_POISONSTAT_rd_poison_intr_0(x) \
11336 (((uint32_t)(((uint32_t)(x)) << DDRC_POISONSTAT_rd_poison_intr_0_SHIFT)) & DDRC_POISONSTAT_rd_poison_intr_0_MASK)
11337/*! @} */
11338
11339/*! @name PSTAT - Port Status Register */
11340/*! @{ */
11341#define DDRC_PSTAT_rd_port_busy_0_MASK (0x1U)
11342#define DDRC_PSTAT_rd_port_busy_0_SHIFT (0U)
11343#define DDRC_PSTAT_rd_port_busy_0(x) \
11344 (((uint32_t)(((uint32_t)(x)) << DDRC_PSTAT_rd_port_busy_0_SHIFT)) & DDRC_PSTAT_rd_port_busy_0_MASK)
11345#define DDRC_PSTAT_wr_port_busy_0_MASK (0x10000U)
11346#define DDRC_PSTAT_wr_port_busy_0_SHIFT (16U)
11347#define DDRC_PSTAT_wr_port_busy_0(x) \
11348 (((uint32_t)(((uint32_t)(x)) << DDRC_PSTAT_wr_port_busy_0_SHIFT)) & DDRC_PSTAT_wr_port_busy_0_MASK)
11349/*! @} */
11350
11351/*! @name PCCFG - Port Common Configuration Register */
11352/*! @{ */
11353#define DDRC_PCCFG_go2critical_en_MASK (0x1U)
11354#define DDRC_PCCFG_go2critical_en_SHIFT (0U)
11355#define DDRC_PCCFG_go2critical_en(x) \
11356 (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_go2critical_en_SHIFT)) & DDRC_PCCFG_go2critical_en_MASK)
11357#define DDRC_PCCFG_pagematch_limit_MASK (0x10U)
11358#define DDRC_PCCFG_pagematch_limit_SHIFT (4U)
11359#define DDRC_PCCFG_pagematch_limit(x) \
11360 (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_pagematch_limit_SHIFT)) & DDRC_PCCFG_pagematch_limit_MASK)
11361#define DDRC_PCCFG_bl_exp_mode_MASK (0x100U)
11362#define DDRC_PCCFG_bl_exp_mode_SHIFT (8U)
11363#define DDRC_PCCFG_bl_exp_mode(x) \
11364 (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_bl_exp_mode_SHIFT)) & DDRC_PCCFG_bl_exp_mode_MASK)
11365/*! @} */
11366
11367/*! @name PCFGR_0 - Port n Configuration Read Register */
11368/*! @{ */
11369#define DDRC_PCFGR_0_rd_port_priority_MASK (0x3FFU)
11370#define DDRC_PCFGR_0_rd_port_priority_SHIFT (0U)
11371#define DDRC_PCFGR_0_rd_port_priority(x) \
11372 (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_priority_SHIFT)) & DDRC_PCFGR_0_rd_port_priority_MASK)
11373#define DDRC_PCFGR_0_rd_port_aging_en_MASK (0x1000U)
11374#define DDRC_PCFGR_0_rd_port_aging_en_SHIFT (12U)
11375#define DDRC_PCFGR_0_rd_port_aging_en(x) \
11376 (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_aging_en_SHIFT)) & DDRC_PCFGR_0_rd_port_aging_en_MASK)
11377#define DDRC_PCFGR_0_rd_port_urgent_en_MASK (0x2000U)
11378#define DDRC_PCFGR_0_rd_port_urgent_en_SHIFT (13U)
11379#define DDRC_PCFGR_0_rd_port_urgent_en(x) \
11380 (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_urgent_en_SHIFT)) & DDRC_PCFGR_0_rd_port_urgent_en_MASK)
11381#define DDRC_PCFGR_0_rd_port_pagematch_en_MASK (0x4000U)
11382#define DDRC_PCFGR_0_rd_port_pagematch_en_SHIFT (14U)
11383#define DDRC_PCFGR_0_rd_port_pagematch_en(x) \
11384 (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_pagematch_en_SHIFT)) & DDRC_PCFGR_0_rd_port_pagematch_en_MASK)
11385#define DDRC_PCFGR_0_rdwr_ordered_en_MASK (0x10000U)
11386#define DDRC_PCFGR_0_rdwr_ordered_en_SHIFT (16U)
11387#define DDRC_PCFGR_0_rdwr_ordered_en(x) \
11388 (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rdwr_ordered_en_SHIFT)) & DDRC_PCFGR_0_rdwr_ordered_en_MASK)
11389/*! @} */
11390
11391/*! @name PCFGW_0 - Port n Configuration Write Register */
11392/*! @{ */
11393#define DDRC_PCFGW_0_wr_port_priority_MASK (0x3FFU)
11394#define DDRC_PCFGW_0_wr_port_priority_SHIFT (0U)
11395#define DDRC_PCFGW_0_wr_port_priority(x) \
11396 (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_priority_SHIFT)) & DDRC_PCFGW_0_wr_port_priority_MASK)
11397#define DDRC_PCFGW_0_wr_port_aging_en_MASK (0x1000U)
11398#define DDRC_PCFGW_0_wr_port_aging_en_SHIFT (12U)
11399#define DDRC_PCFGW_0_wr_port_aging_en(x) \
11400 (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_aging_en_SHIFT)) & DDRC_PCFGW_0_wr_port_aging_en_MASK)
11401#define DDRC_PCFGW_0_wr_port_urgent_en_MASK (0x2000U)
11402#define DDRC_PCFGW_0_wr_port_urgent_en_SHIFT (13U)
11403#define DDRC_PCFGW_0_wr_port_urgent_en(x) \
11404 (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_urgent_en_SHIFT)) & DDRC_PCFGW_0_wr_port_urgent_en_MASK)
11405#define DDRC_PCFGW_0_wr_port_pagematch_en_MASK (0x4000U)
11406#define DDRC_PCFGW_0_wr_port_pagematch_en_SHIFT (14U)
11407#define DDRC_PCFGW_0_wr_port_pagematch_en(x) \
11408 (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_pagematch_en_SHIFT)) & DDRC_PCFGW_0_wr_port_pagematch_en_MASK)
11409/*! @} */
11410
11411/*! @name PCTRL_0 - Port n Control Register */
11412/*! @{ */
11413#define DDRC_PCTRL_0_port_en_MASK (0x1U)
11414#define DDRC_PCTRL_0_port_en_SHIFT (0U)
11415#define DDRC_PCTRL_0_port_en(x) \
11416 (((uint32_t)(((uint32_t)(x)) << DDRC_PCTRL_0_port_en_SHIFT)) & DDRC_PCTRL_0_port_en_MASK)
11417/*! @} */
11418
11419/*! @name PCFGQOS0_0 - Port n Read QoS Configuration Register 0 */
11420/*! @{ */
11421#define DDRC_PCFGQOS0_0_rqos_map_level1_MASK (0xFU)
11422#define DDRC_PCFGQOS0_0_rqos_map_level1_SHIFT (0U)
11423#define DDRC_PCFGQOS0_0_rqos_map_level1(x) \
11424 (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_level1_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_level1_MASK)
11425#define DDRC_PCFGQOS0_0_rqos_map_region0_MASK (0x30000U)
11426#define DDRC_PCFGQOS0_0_rqos_map_region0_SHIFT (16U)
11427#define DDRC_PCFGQOS0_0_rqos_map_region0(x) \
11428 (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_region0_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_region0_MASK)
11429#define DDRC_PCFGQOS0_0_rqos_map_region1_MASK (0x300000U)
11430#define DDRC_PCFGQOS0_0_rqos_map_region1_SHIFT (20U)
11431#define DDRC_PCFGQOS0_0_rqos_map_region1(x) \
11432 (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_region1_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_region1_MASK)
11433/*! @} */
11434
11435/*! @name PCFGQOS1_0 - Port n Read QoS Configuration Register 1 */
11436/*! @{ */
11437#define DDRC_PCFGQOS1_0_rqos_map_timeoutb_MASK (0x7FFU)
11438#define DDRC_PCFGQOS1_0_rqos_map_timeoutb_SHIFT (0U)
11439#define DDRC_PCFGQOS1_0_rqos_map_timeoutb(x) \
11440 (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS1_0_rqos_map_timeoutb_SHIFT)) & DDRC_PCFGQOS1_0_rqos_map_timeoutb_MASK)
11441#define DDRC_PCFGQOS1_0_rqos_map_timeoutr_MASK (0x7FF0000U)
11442#define DDRC_PCFGQOS1_0_rqos_map_timeoutr_SHIFT (16U)
11443#define DDRC_PCFGQOS1_0_rqos_map_timeoutr(x) \
11444 (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS1_0_rqos_map_timeoutr_SHIFT)) & DDRC_PCFGQOS1_0_rqos_map_timeoutr_MASK)
11445/*! @} */
11446
11447/*! @name PCFGWQOS0_0 - Port n Write QoS Configuration Register 0 */
11448/*! @{ */
11449#define DDRC_PCFGWQOS0_0_wqos_map_level_MASK (0xFU)
11450#define DDRC_PCFGWQOS0_0_wqos_map_level_SHIFT (0U)
11451#define DDRC_PCFGWQOS0_0_wqos_map_level(x) \
11452 (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_level_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_level_MASK)
11453#define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U)
11454#define DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT (16U)
11455#define DDRC_PCFGWQOS0_0_wqos_map_region0(x) \
11456 (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
11457#define DDRC_PCFGWQOS0_0_wqos_map_region1_MASK (0x300000U)
11458#define DDRC_PCFGWQOS0_0_wqos_map_region1_SHIFT (20U)
11459#define DDRC_PCFGWQOS0_0_wqos_map_region1(x) \
11460 (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region1_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region1_MASK)
11461/*! @} */
11462
11463/*! @name PCFGWQOS1_0 - Port n Write QoS Configuration Register 1 */
11464/*! @{ */
11465#define DDRC_PCFGWQOS1_0_wqos_map_timeout_MASK (0x7FFU)
11466#define DDRC_PCFGWQOS1_0_wqos_map_timeout_SHIFT (0U)
11467#define DDRC_PCFGWQOS1_0_wqos_map_timeout(x) \
11468 (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS1_0_wqos_map_timeout_SHIFT)) & DDRC_PCFGWQOS1_0_wqos_map_timeout_MASK)
11469/*! @} */
11470
11471/*! @name DERATEEN_SHADOW - [SHADOW] Temperature Derate Enable Register */
11472/*! @{ */
11473#define DDRC_DERATEEN_SHADOW_derate_enable_MASK (0x1U)
11474#define DDRC_DERATEEN_SHADOW_derate_enable_SHIFT (0U)
11475#define DDRC_DERATEEN_SHADOW_derate_enable(x) \
11476 (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_enable_SHIFT)) & \
11477 DDRC_DERATEEN_SHADOW_derate_enable_MASK)
11478#define DDRC_DERATEEN_SHADOW_derate_value_MASK (0x2U)
11479#define DDRC_DERATEEN_SHADOW_derate_value_SHIFT (1U)
11480#define DDRC_DERATEEN_SHADOW_derate_value(x) \
11481 (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_value_SHIFT)) & DDRC_DERATEEN_SHADOW_derate_value_MASK)
11482#define DDRC_DERATEEN_SHADOW_derate_byte_MASK (0xF0U)
11483#define DDRC_DERATEEN_SHADOW_derate_byte_SHIFT (4U)
11484#define DDRC_DERATEEN_SHADOW_derate_byte(x) \
11485 (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_byte_SHIFT)) & DDRC_DERATEEN_SHADOW_derate_byte_MASK)
11486#define DDRC_DERATEEN_SHADOW_rc_derate_value_MASK (0x300U)
11487#define DDRC_DERATEEN_SHADOW_rc_derate_value_SHIFT (8U)
11488#define DDRC_DERATEEN_SHADOW_rc_derate_value(x) \
11489 (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_rc_derate_value_SHIFT)) & \
11490 DDRC_DERATEEN_SHADOW_rc_derate_value_MASK)
11491/*! @} */
11492
11493/*! @name DERATEINT_SHADOW - [SHADOW] Temperature Derate Interval Register */
11494/*! @{ */
11495#define DDRC_DERATEINT_SHADOW_mr4_read_interval_MASK (0xFFFFFFFFU)
11496#define DDRC_DERATEINT_SHADOW_mr4_read_interval_SHIFT (0U)
11497#define DDRC_DERATEINT_SHADOW_mr4_read_interval(x) \
11498 (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEINT_SHADOW_mr4_read_interval_SHIFT)) & \
11499 DDRC_DERATEINT_SHADOW_mr4_read_interval_MASK)
11500/*! @} */
11501
11502/*! @name RFSHCTL0_SHADOW - [SHADOW] Refresh Control Register 0 */
11503/*! @{ */
11504#define DDRC_RFSHCTL0_SHADOW_per_bank_refresh_MASK (0x4U)
11505#define DDRC_RFSHCTL0_SHADOW_per_bank_refresh_SHIFT (2U)
11506#define DDRC_RFSHCTL0_SHADOW_per_bank_refresh(x) \
11507 (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_per_bank_refresh_SHIFT)) & \
11508 DDRC_RFSHCTL0_SHADOW_per_bank_refresh_MASK)
11509#define DDRC_RFSHCTL0_SHADOW_refresh_burst_MASK (0x1F0U)
11510#define DDRC_RFSHCTL0_SHADOW_refresh_burst_SHIFT (4U)
11511#define DDRC_RFSHCTL0_SHADOW_refresh_burst(x) \
11512 (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_burst_SHIFT)) & \
11513 DDRC_RFSHCTL0_SHADOW_refresh_burst_MASK)
11514#define DDRC_RFSHCTL0_SHADOW_refresh_to_x32_MASK (0x1F000U)
11515#define DDRC_RFSHCTL0_SHADOW_refresh_to_x32_SHIFT (12U)
11516#define DDRC_RFSHCTL0_SHADOW_refresh_to_x32(x) \
11517 (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_to_x32_SHIFT)) & \
11518 DDRC_RFSHCTL0_SHADOW_refresh_to_x32_MASK)
11519#define DDRC_RFSHCTL0_SHADOW_refresh_margin_MASK (0xF00000U)
11520#define DDRC_RFSHCTL0_SHADOW_refresh_margin_SHIFT (20U)
11521#define DDRC_RFSHCTL0_SHADOW_refresh_margin(x) \
11522 (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_margin_SHIFT)) & \
11523 DDRC_RFSHCTL0_SHADOW_refresh_margin_MASK)
11524/*! @} */
11525
11526/*! @name RFSHTMG_SHADOW - [SHADOW] Refresh Timing Register */
11527/*! @{ */
11528#define DDRC_RFSHTMG_SHADOW_t_rfc_min_MASK (0x3FFU)
11529#define DDRC_RFSHTMG_SHADOW_t_rfc_min_SHIFT (0U)
11530#define DDRC_RFSHTMG_SHADOW_t_rfc_min(x) \
11531 (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_t_rfc_min_SHIFT)) & DDRC_RFSHTMG_SHADOW_t_rfc_min_MASK)
11532#define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_MASK (0x8000U)
11533#define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_SHIFT (15U)
11534#define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en(x) \
11535 (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_SHIFT)) & \
11536 DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_MASK)
11537#define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_MASK (0xFFF0000U)
11538#define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_SHIFT (16U)
11539#define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32(x) \
11540 (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_SHIFT)) & DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_MASK)
11541/*! @} */
11542
11543/*! @name INIT3_SHADOW - [SHADOW] SDRAM Initialization Register 3 */
11544/*! @{ */
11545#define DDRC_INIT3_SHADOW_emr_MASK (0xFFFFU)
11546#define DDRC_INIT3_SHADOW_emr_SHIFT (0U)
11547#define DDRC_INIT3_SHADOW_emr(x) \
11548 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_SHADOW_emr_SHIFT)) & DDRC_INIT3_SHADOW_emr_MASK)
11549#define DDRC_INIT3_SHADOW_mr_MASK (0xFFFF0000U)
11550#define DDRC_INIT3_SHADOW_mr_SHIFT (16U)
11551#define DDRC_INIT3_SHADOW_mr(x) \
11552 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_SHADOW_mr_SHIFT)) & DDRC_INIT3_SHADOW_mr_MASK)
11553/*! @} */
11554
11555/*! @name INIT4_SHADOW - [SHADOW] SDRAM Initialization Register 4 */
11556/*! @{ */
11557#define DDRC_INIT4_SHADOW_emr3_MASK (0xFFFFU)
11558#define DDRC_INIT4_SHADOW_emr3_SHIFT (0U)
11559#define DDRC_INIT4_SHADOW_emr3(x) \
11560 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_SHADOW_emr3_SHIFT)) & DDRC_INIT4_SHADOW_emr3_MASK)
11561#define DDRC_INIT4_SHADOW_emr2_MASK (0xFFFF0000U)
11562#define DDRC_INIT4_SHADOW_emr2_SHIFT (16U)
11563#define DDRC_INIT4_SHADOW_emr2(x) \
11564 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_SHADOW_emr2_SHIFT)) & DDRC_INIT4_SHADOW_emr2_MASK)
11565/*! @} */
11566
11567/*! @name INIT6_SHADOW - [SHADOW] SDRAM Initialization Register 6 */
11568/*! @{ */
11569#define DDRC_INIT6_SHADOW_mr5_MASK (0xFFFFU)
11570#define DDRC_INIT6_SHADOW_mr5_SHIFT (0U)
11571#define DDRC_INIT6_SHADOW_mr5(x) \
11572 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_SHADOW_mr5_SHIFT)) & DDRC_INIT6_SHADOW_mr5_MASK)
11573#define DDRC_INIT6_SHADOW_mr4_MASK (0xFFFF0000U)
11574#define DDRC_INIT6_SHADOW_mr4_SHIFT (16U)
11575#define DDRC_INIT6_SHADOW_mr4(x) \
11576 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_SHADOW_mr4_SHIFT)) & DDRC_INIT6_SHADOW_mr4_MASK)
11577/*! @} */
11578
11579/*! @name INIT7_SHADOW - [SHADOW] SDRAM Initialization Register 7 */
11580/*! @{ */
11581#define DDRC_INIT7_SHADOW_mr6_MASK (0xFFFF0000U)
11582#define DDRC_INIT7_SHADOW_mr6_SHIFT (16U)
11583#define DDRC_INIT7_SHADOW_mr6(x) \
11584 (((uint32_t)(((uint32_t)(x)) << DDRC_INIT7_SHADOW_mr6_SHIFT)) & DDRC_INIT7_SHADOW_mr6_MASK)
11585/*! @} */
11586
11587/*! @name DRAMTMG0_SHADOW - [SHADOW] SDRAM Timing Register 0 */
11588/*! @{ */
11589#define DDRC_DRAMTMG0_SHADOW_t_ras_min_MASK (0x3FU)
11590#define DDRC_DRAMTMG0_SHADOW_t_ras_min_SHIFT (0U)
11591#define DDRC_DRAMTMG0_SHADOW_t_ras_min(x) \
11592 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_ras_min_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_ras_min_MASK)
11593#define DDRC_DRAMTMG0_SHADOW_t_ras_max_MASK (0x7F00U)
11594#define DDRC_DRAMTMG0_SHADOW_t_ras_max_SHIFT (8U)
11595#define DDRC_DRAMTMG0_SHADOW_t_ras_max(x) \
11596 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_ras_max_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_ras_max_MASK)
11597#define DDRC_DRAMTMG0_SHADOW_t_faw_MASK (0x3F0000U)
11598#define DDRC_DRAMTMG0_SHADOW_t_faw_SHIFT (16U)
11599#define DDRC_DRAMTMG0_SHADOW_t_faw(x) \
11600 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_faw_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_faw_MASK)
11601#define DDRC_DRAMTMG0_SHADOW_wr2pre_MASK (0x7F000000U)
11602#define DDRC_DRAMTMG0_SHADOW_wr2pre_SHIFT (24U)
11603#define DDRC_DRAMTMG0_SHADOW_wr2pre(x) \
11604 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_wr2pre_SHIFT)) & DDRC_DRAMTMG0_SHADOW_wr2pre_MASK)
11605/*! @} */
11606
11607/*! @name DRAMTMG1_SHADOW - [SHADOW] SDRAM Timing Register 1 */
11608/*! @{ */
11609#define DDRC_DRAMTMG1_SHADOW_t_rc_MASK (0x7FU)
11610#define DDRC_DRAMTMG1_SHADOW_t_rc_SHIFT (0U)
11611#define DDRC_DRAMTMG1_SHADOW_t_rc(x) \
11612 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_t_rc_SHIFT)) & DDRC_DRAMTMG1_SHADOW_t_rc_MASK)
11613#define DDRC_DRAMTMG1_SHADOW_rd2pre_MASK (0x3F00U)
11614#define DDRC_DRAMTMG1_SHADOW_rd2pre_SHIFT (8U)
11615#define DDRC_DRAMTMG1_SHADOW_rd2pre(x) \
11616 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_rd2pre_SHIFT)) & DDRC_DRAMTMG1_SHADOW_rd2pre_MASK)
11617#define DDRC_DRAMTMG1_SHADOW_t_xp_MASK (0x1F0000U)
11618#define DDRC_DRAMTMG1_SHADOW_t_xp_SHIFT (16U)
11619#define DDRC_DRAMTMG1_SHADOW_t_xp(x) \
11620 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_t_xp_SHIFT)) & DDRC_DRAMTMG1_SHADOW_t_xp_MASK)
11621/*! @} */
11622
11623/*! @name DRAMTMG2_SHADOW - [SHADOW] SDRAM Timing Register 2 */
11624/*! @{ */
11625#define DDRC_DRAMTMG2_SHADOW_wr2rd_MASK (0x3FU)
11626#define DDRC_DRAMTMG2_SHADOW_wr2rd_SHIFT (0U)
11627#define DDRC_DRAMTMG2_SHADOW_wr2rd(x) \
11628 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_wr2rd_SHIFT)) & DDRC_DRAMTMG2_SHADOW_wr2rd_MASK)
11629#define DDRC_DRAMTMG2_SHADOW_rd2wr_MASK (0x3F00U)
11630#define DDRC_DRAMTMG2_SHADOW_rd2wr_SHIFT (8U)
11631#define DDRC_DRAMTMG2_SHADOW_rd2wr(x) \
11632 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_rd2wr_SHIFT)) & DDRC_DRAMTMG2_SHADOW_rd2wr_MASK)
11633#define DDRC_DRAMTMG2_SHADOW_read_latency_MASK (0x3F0000U)
11634#define DDRC_DRAMTMG2_SHADOW_read_latency_SHIFT (16U)
11635#define DDRC_DRAMTMG2_SHADOW_read_latency(x) \
11636 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_read_latency_SHIFT)) & DDRC_DRAMTMG2_SHADOW_read_latency_MASK)
11637#define DDRC_DRAMTMG2_SHADOW_write_latency_MASK (0x3F000000U)
11638#define DDRC_DRAMTMG2_SHADOW_write_latency_SHIFT (24U)
11639#define DDRC_DRAMTMG2_SHADOW_write_latency(x) \
11640 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_write_latency_SHIFT)) & \
11641 DDRC_DRAMTMG2_SHADOW_write_latency_MASK)
11642/*! @} */
11643
11644/*! @name DRAMTMG3_SHADOW - [SHADOW] SDRAM Timing Register 3 */
11645/*! @{ */
11646#define DDRC_DRAMTMG3_SHADOW_t_mod_MASK (0x3FFU)
11647#define DDRC_DRAMTMG3_SHADOW_t_mod_SHIFT (0U)
11648#define DDRC_DRAMTMG3_SHADOW_t_mod(x) \
11649 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mod_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mod_MASK)
11650#define DDRC_DRAMTMG3_SHADOW_t_mrd_MASK (0x3F000U)
11651#define DDRC_DRAMTMG3_SHADOW_t_mrd_SHIFT (12U)
11652#define DDRC_DRAMTMG3_SHADOW_t_mrd(x) \
11653 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mrd_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mrd_MASK)
11654#define DDRC_DRAMTMG3_SHADOW_t_mrw_MASK (0x3FF00000U)
11655#define DDRC_DRAMTMG3_SHADOW_t_mrw_SHIFT (20U)
11656#define DDRC_DRAMTMG3_SHADOW_t_mrw(x) \
11657 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mrw_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mrw_MASK)
11658/*! @} */
11659
11660/*! @name DRAMTMG4_SHADOW - [SHADOW] SDRAM Timing Register 4 */
11661/*! @{ */
11662#define DDRC_DRAMTMG4_SHADOW_t_rp_MASK (0x1FU)
11663#define DDRC_DRAMTMG4_SHADOW_t_rp_SHIFT (0U)
11664#define DDRC_DRAMTMG4_SHADOW_t_rp(x) \
11665 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rp_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rp_MASK)
11666#define DDRC_DRAMTMG4_SHADOW_t_rrd_MASK (0xF00U)
11667#define DDRC_DRAMTMG4_SHADOW_t_rrd_SHIFT (8U)
11668#define DDRC_DRAMTMG4_SHADOW_t_rrd(x) \
11669 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rrd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rrd_MASK)
11670#define DDRC_DRAMTMG4_SHADOW_t_ccd_MASK (0xF0000U)
11671#define DDRC_DRAMTMG4_SHADOW_t_ccd_SHIFT (16U)
11672#define DDRC_DRAMTMG4_SHADOW_t_ccd(x) \
11673 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_ccd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_ccd_MASK)
11674#define DDRC_DRAMTMG4_SHADOW_t_rcd_MASK (0x1F000000U)
11675#define DDRC_DRAMTMG4_SHADOW_t_rcd_SHIFT (24U)
11676#define DDRC_DRAMTMG4_SHADOW_t_rcd(x) \
11677 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rcd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rcd_MASK)
11678/*! @} */
11679
11680/*! @name DRAMTMG5_SHADOW - [SHADOW] SDRAM Timing Register 5 */
11681/*! @{ */
11682#define DDRC_DRAMTMG5_SHADOW_t_cke_MASK (0x1FU)
11683#define DDRC_DRAMTMG5_SHADOW_t_cke_SHIFT (0U)
11684#define DDRC_DRAMTMG5_SHADOW_t_cke(x) \
11685 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cke_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cke_MASK)
11686#define DDRC_DRAMTMG5_SHADOW_t_ckesr_MASK (0x3F00U)
11687#define DDRC_DRAMTMG5_SHADOW_t_ckesr_SHIFT (8U)
11688#define DDRC_DRAMTMG5_SHADOW_t_ckesr(x) \
11689 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_ckesr_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_ckesr_MASK)
11690#define DDRC_DRAMTMG5_SHADOW_t_cksre_MASK (0xF0000U)
11691#define DDRC_DRAMTMG5_SHADOW_t_cksre_SHIFT (16U)
11692#define DDRC_DRAMTMG5_SHADOW_t_cksre(x) \
11693 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cksre_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cksre_MASK)
11694#define DDRC_DRAMTMG5_SHADOW_t_cksrx_MASK (0xF000000U)
11695#define DDRC_DRAMTMG5_SHADOW_t_cksrx_SHIFT (24U)
11696#define DDRC_DRAMTMG5_SHADOW_t_cksrx(x) \
11697 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cksrx_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cksrx_MASK)
11698/*! @} */
11699
11700/*! @name DRAMTMG6_SHADOW - [SHADOW] SDRAM Timing Register 6 */
11701/*! @{ */
11702#define DDRC_DRAMTMG6_SHADOW_t_ckcsx_MASK (0xFU)
11703#define DDRC_DRAMTMG6_SHADOW_t_ckcsx_SHIFT (0U)
11704#define DDRC_DRAMTMG6_SHADOW_t_ckcsx(x) \
11705 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckcsx_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckcsx_MASK)
11706#define DDRC_DRAMTMG6_SHADOW_t_ckdpdx_MASK (0xF0000U)
11707#define DDRC_DRAMTMG6_SHADOW_t_ckdpdx_SHIFT (16U)
11708#define DDRC_DRAMTMG6_SHADOW_t_ckdpdx(x) \
11709 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckdpdx_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckdpdx_MASK)
11710#define DDRC_DRAMTMG6_SHADOW_t_ckdpde_MASK (0xF000000U)
11711#define DDRC_DRAMTMG6_SHADOW_t_ckdpde_SHIFT (24U)
11712#define DDRC_DRAMTMG6_SHADOW_t_ckdpde(x) \
11713 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckdpde_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckdpde_MASK)
11714/*! @} */
11715
11716/*! @name DRAMTMG7_SHADOW - [SHADOW] SDRAM Timing Register 7 */
11717/*! @{ */
11718#define DDRC_DRAMTMG7_SHADOW_t_ckpdx_MASK (0xFU)
11719#define DDRC_DRAMTMG7_SHADOW_t_ckpdx_SHIFT (0U)
11720#define DDRC_DRAMTMG7_SHADOW_t_ckpdx(x) \
11721 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_SHADOW_t_ckpdx_SHIFT)) & DDRC_DRAMTMG7_SHADOW_t_ckpdx_MASK)
11722#define DDRC_DRAMTMG7_SHADOW_t_ckpde_MASK (0xF00U)
11723#define DDRC_DRAMTMG7_SHADOW_t_ckpde_SHIFT (8U)
11724#define DDRC_DRAMTMG7_SHADOW_t_ckpde(x) \
11725 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_SHADOW_t_ckpde_SHIFT)) & DDRC_DRAMTMG7_SHADOW_t_ckpde_MASK)
11726/*! @} */
11727
11728/*! @name DRAMTMG8_SHADOW - [SHADOW] SDRAM Timing Register 8 */
11729/*! @{ */
11730#define DDRC_DRAMTMG8_SHADOW_t_xs_x32_MASK (0x7FU)
11731#define DDRC_DRAMTMG8_SHADOW_t_xs_x32_SHIFT (0U)
11732#define DDRC_DRAMTMG8_SHADOW_t_xs_x32(x) \
11733 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_x32_MASK)
11734#define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_MASK (0x7F00U)
11735#define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_SHIFT (8U)
11736#define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32(x) \
11737 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_MASK)
11738#define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_MASK (0x7F0000U)
11739#define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_SHIFT (16U)
11740#define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32(x) \
11741 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_SHIFT)) & \
11742 DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_MASK)
11743#define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_MASK (0x7F000000U)
11744#define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_SHIFT (24U)
11745#define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32(x) \
11746 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_SHIFT)) & \
11747 DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_MASK)
11748/*! @} */
11749
11750/*! @name DRAMTMG9_SHADOW - [SHADOW] SDRAM Timing Register 9 */
11751/*! @{ */
11752#define DDRC_DRAMTMG9_SHADOW_wr2rd_s_MASK (0x3FU)
11753#define DDRC_DRAMTMG9_SHADOW_wr2rd_s_SHIFT (0U)
11754#define DDRC_DRAMTMG9_SHADOW_wr2rd_s(x) \
11755 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_wr2rd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_wr2rd_s_MASK)
11756#define DDRC_DRAMTMG9_SHADOW_t_rrd_s_MASK (0xF00U)
11757#define DDRC_DRAMTMG9_SHADOW_t_rrd_s_SHIFT (8U)
11758#define DDRC_DRAMTMG9_SHADOW_t_rrd_s(x) \
11759 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_t_rrd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_t_rrd_s_MASK)
11760#define DDRC_DRAMTMG9_SHADOW_t_ccd_s_MASK (0x70000U)
11761#define DDRC_DRAMTMG9_SHADOW_t_ccd_s_SHIFT (16U)
11762#define DDRC_DRAMTMG9_SHADOW_t_ccd_s(x) \
11763 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_t_ccd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_t_ccd_s_MASK)
11764#define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_MASK (0x40000000U)
11765#define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_SHIFT (30U)
11766#define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble(x) \
11767 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_SHIFT)) & \
11768 DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_MASK)
11769/*! @} */
11770
11771/*! @name DRAMTMG10_SHADOW - [SHADOW] SDRAM Timing Register 10 */
11772/*! @{ */
11773#define DDRC_DRAMTMG10_SHADOW_t_gear_hold_MASK (0x3U)
11774#define DDRC_DRAMTMG10_SHADOW_t_gear_hold_SHIFT (0U)
11775#define DDRC_DRAMTMG10_SHADOW_t_gear_hold(x) \
11776 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_gear_hold_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_gear_hold_MASK)
11777#define DDRC_DRAMTMG10_SHADOW_t_gear_setup_MASK (0xCU)
11778#define DDRC_DRAMTMG10_SHADOW_t_gear_setup_SHIFT (2U)
11779#define DDRC_DRAMTMG10_SHADOW_t_gear_setup(x) \
11780 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_gear_setup_SHIFT)) & \
11781 DDRC_DRAMTMG10_SHADOW_t_gear_setup_MASK)
11782#define DDRC_DRAMTMG10_SHADOW_t_cmd_gear_MASK (0x1F00U)
11783#define DDRC_DRAMTMG10_SHADOW_t_cmd_gear_SHIFT (8U)
11784#define DDRC_DRAMTMG10_SHADOW_t_cmd_gear(x) \
11785 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_cmd_gear_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_cmd_gear_MASK)
11786#define DDRC_DRAMTMG10_SHADOW_t_sync_gear_MASK (0x1F0000U)
11787#define DDRC_DRAMTMG10_SHADOW_t_sync_gear_SHIFT (16U)
11788#define DDRC_DRAMTMG10_SHADOW_t_sync_gear(x) \
11789 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_sync_gear_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_sync_gear_MASK)
11790/*! @} */
11791
11792/*! @name DRAMTMG11_SHADOW - [SHADOW] SDRAM Timing Register 11 */
11793/*! @{ */
11794#define DDRC_DRAMTMG11_SHADOW_t_ckmpe_MASK (0x1FU)
11795#define DDRC_DRAMTMG11_SHADOW_t_ckmpe_SHIFT (0U)
11796#define DDRC_DRAMTMG11_SHADOW_t_ckmpe(x) \
11797 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_ckmpe_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_ckmpe_MASK)
11798#define DDRC_DRAMTMG11_SHADOW_t_mpx_s_MASK (0x300U)
11799#define DDRC_DRAMTMG11_SHADOW_t_mpx_s_SHIFT (8U)
11800#define DDRC_DRAMTMG11_SHADOW_t_mpx_s(x) \
11801 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_mpx_s_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_mpx_s_MASK)
11802#define DDRC_DRAMTMG11_SHADOW_t_mpx_lh_MASK (0x1F0000U)
11803#define DDRC_DRAMTMG11_SHADOW_t_mpx_lh_SHIFT (16U)
11804#define DDRC_DRAMTMG11_SHADOW_t_mpx_lh(x) \
11805 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_mpx_lh_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_mpx_lh_MASK)
11806#define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_MASK (0x7F000000U)
11807#define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_SHIFT (24U)
11808#define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32(x) \
11809 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_SHIFT)) & \
11810 DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_MASK)
11811/*! @} */
11812
11813/*! @name DRAMTMG12_SHADOW - [SHADOW] SDRAM Timing Register 12 */
11814/*! @{ */
11815#define DDRC_DRAMTMG12_SHADOW_t_mrd_pda_MASK (0x1FU)
11816#define DDRC_DRAMTMG12_SHADOW_t_mrd_pda_SHIFT (0U)
11817#define DDRC_DRAMTMG12_SHADOW_t_mrd_pda(x) \
11818 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_mrd_pda_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_mrd_pda_MASK)
11819#define DDRC_DRAMTMG12_SHADOW_t_ckehcmd_MASK (0xF00U)
11820#define DDRC_DRAMTMG12_SHADOW_t_ckehcmd_SHIFT (8U)
11821#define DDRC_DRAMTMG12_SHADOW_t_ckehcmd(x) \
11822 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_ckehcmd_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_ckehcmd_MASK)
11823#define DDRC_DRAMTMG12_SHADOW_t_cmdcke_MASK (0x30000U)
11824#define DDRC_DRAMTMG12_SHADOW_t_cmdcke_SHIFT (16U)
11825#define DDRC_DRAMTMG12_SHADOW_t_cmdcke(x) \
11826 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_cmdcke_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_cmdcke_MASK)
11827/*! @} */
11828
11829/*! @name DRAMTMG13_SHADOW - [SHADOW] SDRAM Timing Register 13 */
11830/*! @{ */
11831#define DDRC_DRAMTMG13_SHADOW_t_ppd_MASK (0x7U)
11832#define DDRC_DRAMTMG13_SHADOW_t_ppd_SHIFT (0U)
11833#define DDRC_DRAMTMG13_SHADOW_t_ppd(x) \
11834 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_t_ppd_SHIFT)) & DDRC_DRAMTMG13_SHADOW_t_ppd_MASK)
11835#define DDRC_DRAMTMG13_SHADOW_t_ccd_mw_MASK (0x3F0000U)
11836#define DDRC_DRAMTMG13_SHADOW_t_ccd_mw_SHIFT (16U)
11837#define DDRC_DRAMTMG13_SHADOW_t_ccd_mw(x) \
11838 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_t_ccd_mw_SHIFT)) & DDRC_DRAMTMG13_SHADOW_t_ccd_mw_MASK)
11839#define DDRC_DRAMTMG13_SHADOW_odtloff_MASK (0x7F000000U)
11840#define DDRC_DRAMTMG13_SHADOW_odtloff_SHIFT (24U)
11841#define DDRC_DRAMTMG13_SHADOW_odtloff(x) \
11842 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_odtloff_SHIFT)) & DDRC_DRAMTMG13_SHADOW_odtloff_MASK)
11843/*! @} */
11844
11845/*! @name DRAMTMG14_SHADOW - [SHADOW] SDRAM Timing Register 14 */
11846/*! @{ */
11847#define DDRC_DRAMTMG14_SHADOW_t_xsr_MASK (0xFFFU)
11848#define DDRC_DRAMTMG14_SHADOW_t_xsr_SHIFT (0U)
11849#define DDRC_DRAMTMG14_SHADOW_t_xsr(x) \
11850 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG14_SHADOW_t_xsr_SHIFT)) & DDRC_DRAMTMG14_SHADOW_t_xsr_MASK)
11851/*! @} */
11852
11853/*! @name DRAMTMG15_SHADOW - [SHADOW] SDRAM Timing Register 15 */
11854/*! @{ */
11855#define DDRC_DRAMTMG15_SHADOW_t_stab_x32_MASK (0xFFU)
11856#define DDRC_DRAMTMG15_SHADOW_t_stab_x32_SHIFT (0U)
11857#define DDRC_DRAMTMG15_SHADOW_t_stab_x32(x) \
11858 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_SHADOW_t_stab_x32_SHIFT)) & DDRC_DRAMTMG15_SHADOW_t_stab_x32_MASK)
11859#define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_MASK (0x80000000U)
11860#define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_SHIFT (31U)
11861#define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab(x) \
11862 (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_SHIFT)) & \
11863 DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_MASK)
11864/*! @} */
11865
11866/*! @name ZQCTL0_SHADOW - [SHADOW] ZQ Control Register 0 */
11867/*! @{ */
11868#define DDRC_ZQCTL0_SHADOW_t_zq_short_nop_MASK (0x3FFU)
11869#define DDRC_ZQCTL0_SHADOW_t_zq_short_nop_SHIFT (0U)
11870#define DDRC_ZQCTL0_SHADOW_t_zq_short_nop(x) \
11871 (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_t_zq_short_nop_SHIFT)) & DDRC_ZQCTL0_SHADOW_t_zq_short_nop_MASK)
11872#define DDRC_ZQCTL0_SHADOW_t_zq_long_nop_MASK (0x7FF0000U)
11873#define DDRC_ZQCTL0_SHADOW_t_zq_long_nop_SHIFT (16U)
11874#define DDRC_ZQCTL0_SHADOW_t_zq_long_nop(x) \
11875 (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_t_zq_long_nop_SHIFT)) & DDRC_ZQCTL0_SHADOW_t_zq_long_nop_MASK)
11876#define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_MASK (0x10000000U)
11877#define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_SHIFT (28U)
11878#define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl(x) \
11879 (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_MASK)
11880#define DDRC_ZQCTL0_SHADOW_zq_resistor_shared_MASK (0x20000000U)
11881#define DDRC_ZQCTL0_SHADOW_zq_resistor_shared_SHIFT (29U)
11882#define DDRC_ZQCTL0_SHADOW_zq_resistor_shared(x) \
11883 (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_zq_resistor_shared_SHIFT)) & \
11884 DDRC_ZQCTL0_SHADOW_zq_resistor_shared_MASK)
11885#define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_MASK (0x40000000U)
11886#define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_SHIFT (30U)
11887#define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl(x) \
11888 (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_MASK)
11889#define DDRC_ZQCTL0_SHADOW_dis_auto_zq_MASK (0x80000000U)
11890#define DDRC_ZQCTL0_SHADOW_dis_auto_zq_SHIFT (31U)
11891#define DDRC_ZQCTL0_SHADOW_dis_auto_zq(x) \
11892 (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_auto_zq_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_auto_zq_MASK)
11893/*! @} */
11894
11895/*! @name DFITMG0_SHADOW - [SHADOW] DFI Timing Register 0 */
11896/*! @{ */
11897#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_MASK (0x3FU)
11898#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_SHIFT (0U)
11899#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat(x) \
11900 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_SHIFT)) & \
11901 DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_MASK)
11902#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_MASK (0x3F00U)
11903#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_SHIFT (8U)
11904#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata(x) \
11905 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_SHIFT)) & \
11906 DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_MASK)
11907#define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_MASK (0x8000U)
11908#define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_SHIFT (15U)
11909#define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr(x) \
11910 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_SHIFT)) & \
11911 DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_MASK)
11912#define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_MASK (0x7F0000U)
11913#define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_SHIFT (16U)
11914#define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en(x) \
11915 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_SHIFT)) & \
11916 DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_MASK)
11917#define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_MASK (0x800000U)
11918#define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_SHIFT (23U)
11919#define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr(x) \
11920 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_SHIFT)) & \
11921 DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_MASK)
11922#define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_MASK (0x1F000000U)
11923#define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_SHIFT (24U)
11924#define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay(x) \
11925 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_SHIFT)) & \
11926 DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_MASK)
11927/*! @} */
11928
11929/*! @name DFITMG1_SHADOW - [SHADOW] DFI Timing Register 1 */
11930/*! @{ */
11931#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_MASK (0x1FU)
11932#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_SHIFT (0U)
11933#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable(x) \
11934 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_SHIFT)) & \
11935 DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_MASK)
11936#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_MASK (0x1F00U)
11937#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_SHIFT (8U)
11938#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable(x) \
11939 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_SHIFT)) & \
11940 DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_MASK)
11941#define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_MASK (0x1F0000U)
11942#define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_SHIFT (16U)
11943#define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay(x) \
11944 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_SHIFT)) & \
11945 DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_MASK)
11946#define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_MASK (0x3000000U)
11947#define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_SHIFT (24U)
11948#define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat(x) \
11949 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_SHIFT)) & \
11950 DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_MASK)
11951#define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_MASK (0xF0000000U)
11952#define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_SHIFT (28U)
11953#define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat(x) \
11954 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_MASK)
11955/*! @} */
11956
11957/*! @name DFITMG2_SHADOW - [SHADOW] DFI Timing Register 2 */
11958/*! @{ */
11959#define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_MASK (0x3FU)
11960#define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_SHIFT (0U)
11961#define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat(x) \
11962 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_SHIFT)) & \
11963 DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_MASK)
11964#define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_MASK (0x7F00U)
11965#define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_SHIFT (8U)
11966#define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat(x) \
11967 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_SHIFT)) & \
11968 DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_MASK)
11969/*! @} */
11970
11971/*! @name DFITMG3_SHADOW - [SHADOW] DFI Timing Register 3 */
11972/*! @{ */
11973#define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_MASK (0x1FU)
11974#define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_SHIFT (0U)
11975#define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay(x) \
11976 (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_SHIFT)) & \
11977 DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_MASK)
11978/*! @} */
11979
11980/*! @name ODTCFG_SHADOW - [SHADOW] ODT Configuration Register */
11981/*! @{ */
11982#define DDRC_ODTCFG_SHADOW_rd_odt_delay_MASK (0x7CU)
11983#define DDRC_ODTCFG_SHADOW_rd_odt_delay_SHIFT (2U)
11984#define DDRC_ODTCFG_SHADOW_rd_odt_delay(x) \
11985 (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_rd_odt_delay_SHIFT)) & DDRC_ODTCFG_SHADOW_rd_odt_delay_MASK)
11986#define DDRC_ODTCFG_SHADOW_rd_odt_hold_MASK (0xF00U)
11987#define DDRC_ODTCFG_SHADOW_rd_odt_hold_SHIFT (8U)
11988#define DDRC_ODTCFG_SHADOW_rd_odt_hold(x) \
11989 (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_rd_odt_hold_SHIFT)) & DDRC_ODTCFG_SHADOW_rd_odt_hold_MASK)
11990#define DDRC_ODTCFG_SHADOW_wr_odt_delay_MASK (0x1F0000U)
11991#define DDRC_ODTCFG_SHADOW_wr_odt_delay_SHIFT (16U)
11992#define DDRC_ODTCFG_SHADOW_wr_odt_delay(x) \
11993 (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_wr_odt_delay_SHIFT)) & DDRC_ODTCFG_SHADOW_wr_odt_delay_MASK)
11994#define DDRC_ODTCFG_SHADOW_wr_odt_hold_MASK (0xF000000U)
11995#define DDRC_ODTCFG_SHADOW_wr_odt_hold_SHIFT (24U)
11996#define DDRC_ODTCFG_SHADOW_wr_odt_hold(x) \
11997 (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_wr_odt_hold_SHIFT)) & DDRC_ODTCFG_SHADOW_wr_odt_hold_MASK)
11998/*! @} */
11999
12000/*!
12001 * @}
12002 */ /* end of group DDRC_Register_Masks */
12003
12004/* DDRC - Peripheral instance base addresses */
12005/** Peripheral DDRC base address */
12006#define DDRC_BASE (0x3D400000u)
12007/** Peripheral DDRC base pointer */
12008#define DDRC ((DDRC_Type *)DDRC_BASE)
12009/** Array initializer of DDRC peripheral base addresses */
12010#define DDRC_BASE_ADDRS \
12011 { \
12012 DDRC_BASE \
12013 }
12014/** Array initializer of DDRC peripheral base pointers */
12015#define DDRC_BASE_PTRS \
12016 { \
12017 DDRC \
12018 }
12019
12020/*!
12021 * @}
12022 */ /* end of group DDRC_Peripheral_Access_Layer */
12023
12024/* ----------------------------------------------------------------------------
12025 -- DWC_DDRPHYA_ANIB Peripheral Access Layer
12026 ---------------------------------------------------------------------------- */
12027
12028/*!
12029 * @addtogroup DWC_DDRPHYA_ANIB_Peripheral_Access_Layer DWC_DDRPHYA_ANIB Peripheral Access Layer
12030 * @{
12031 */
12032
12033/** DWC_DDRPHYA_ANIB - Register Layout Typedef */
12034typedef struct
12035{
12036 uint8_t RESERVED_0[52];
12037 __IO uint16_t MTESTMUXSEL; /**< Digital Observation Pin control, offset: 0x34 */
12038 uint8_t RESERVED_1[24];
12039 __IO uint16_t AFORCEDRVCONT; /**< Force Address/Command Driven (Lanes A3-A0), offset: 0x4E */
12040 __IO uint16_t AFORCETRICONT; /**< Force Address/Command Tristate (Lanes A3-A0), offset: 0x50 */
12041 uint8_t RESERVED_2[52];
12042 __IO uint16_t ATXIMPEDANCE; /**< Address TX impedance controls, offset: 0x86 */
12043 uint8_t RESERVED_3[30];
12044 __I uint16_t ATESTPRBSERR; /**< Address Loopback PRBS Error status for an entire ACX4 block, offset: 0xA6 */
12045 uint8_t RESERVED_4[2];
12046 __IO uint16_t ATXSLEWRATE; /**< Address TX slew rate and predriver controls, offset: 0xAA */
12047 __I uint16_t ATESTPRBSERRCNT; /**< Address Loopback Test Result register, offset: 0xAC */
12048 uint8_t RESERVED_5[82];
12049 __IO uint16_t ATXDLY_P0; /**< Address/Command Delay, per pstate., offset: 0x100 */
12050 uint8_t RESERVED_6[2097150];
12051 __IO uint16_t ATXDLY_P1; /**< Address/Command Delay, per pstate., offset: 0x200100 */
12052 uint8_t RESERVED_7[2097150];
12053 __IO uint16_t ATXDLY_P2; /**< Address/Command Delay, per pstate., offset: 0x400100 */
12054 uint8_t RESERVED_8[2097150];
12055 __IO uint16_t ATXDLY_P3; /**< Address/Command Delay, per pstate., offset: 0x600100 */
12056} DWC_DDRPHYA_ANIB_Type;
12057
12058/* ----------------------------------------------------------------------------
12059 -- DWC_DDRPHYA_ANIB Register Masks
12060 ---------------------------------------------------------------------------- */
12061
12062/*!
12063 * @addtogroup DWC_DDRPHYA_ANIB_Register_Masks DWC_DDRPHYA_ANIB Register Masks
12064 * @{
12065 */
12066
12067/*! @name MTESTMUXSEL - Digital Observation Pin control */
12068/*! @{ */
12069#define DWC_DDRPHYA_ANIB_MTESTMUXSEL_MtestMuxSel_MASK (0x3FU)
12070#define DWC_DDRPHYA_ANIB_MTESTMUXSEL_MtestMuxSel_SHIFT (0U)
12071#define DWC_DDRPHYA_ANIB_MTESTMUXSEL_MtestMuxSel(x) \
12072 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_MTESTMUXSEL_MtestMuxSel_SHIFT)) & \
12073 DWC_DDRPHYA_ANIB_MTESTMUXSEL_MtestMuxSel_MASK)
12074/*! @} */
12075
12076/*! @name AFORCEDRVCONT - Force Address/Command Driven (Lanes A3-A0) */
12077/*! @{ */
12078#define DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AForceDrvCont_MASK (0xFU)
12079#define DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AForceDrvCont_SHIFT (0U)
12080#define DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AForceDrvCont(x) \
12081 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AForceDrvCont_SHIFT)) & \
12082 DWC_DDRPHYA_ANIB_AFORCEDRVCONT_AForceDrvCont_MASK)
12083/*! @} */
12084
12085/*! @name AFORCETRICONT - Force Address/Command Tristate (Lanes A3-A0) */
12086/*! @{ */
12087#define DWC_DDRPHYA_ANIB_AFORCETRICONT_AForceTriCont_MASK (0xFU)
12088#define DWC_DDRPHYA_ANIB_AFORCETRICONT_AForceTriCont_SHIFT (0U)
12089#define DWC_DDRPHYA_ANIB_AFORCETRICONT_AForceTriCont(x) \
12090 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_AFORCETRICONT_AForceTriCont_SHIFT)) & \
12091 DWC_DDRPHYA_ANIB_AFORCETRICONT_AForceTriCont_MASK)
12092/*! @} */
12093
12094/*! @name ATXIMPEDANCE - Address TX impedance controls */
12095/*! @{ */
12096#define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenP_MASK (0x1FU)
12097#define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenP_SHIFT (0U)
12098#define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenP(x) \
12099 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenP_SHIFT)) & \
12100 DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenP_MASK)
12101#define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenN_MASK (0x3E0U)
12102#define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenN_SHIFT (5U)
12103#define DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenN(x) \
12104 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenN_SHIFT)) & \
12105 DWC_DDRPHYA_ANIB_ATXIMPEDANCE_ADrvStrenN_MASK)
12106/*! @} */
12107
12108/*! @name ATESTPRBSERR - Address Loopback PRBS Error status for an entire ACX4 block */
12109/*! @{ */
12110#define DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATestPrbsErr_MASK (0xFU)
12111#define DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATestPrbsErr_SHIFT (0U)
12112#define DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATestPrbsErr(x) \
12113 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATestPrbsErr_SHIFT)) & \
12114 DWC_DDRPHYA_ANIB_ATESTPRBSERR_ATestPrbsErr_MASK)
12115/*! @} */
12116
12117/*! @name ATXSLEWRATE - Address TX slew rate and predriver controls */
12118/*! @{ */
12119#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreP_MASK (0xFU)
12120#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreP_SHIFT (0U)
12121#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreP(x) \
12122 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreP_SHIFT)) & \
12123 DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreP_MASK)
12124#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreN_MASK (0xF0U)
12125#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreN_SHIFT (4U)
12126#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreN(x) \
12127 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreN_SHIFT)) & \
12128 DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreN_MASK)
12129#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreDrvMode_MASK (0x700U)
12130#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreDrvMode_SHIFT (8U)
12131#define DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreDrvMode(x) \
12132 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreDrvMode_SHIFT)) & \
12133 DWC_DDRPHYA_ANIB_ATXSLEWRATE_ATxPreDrvMode_MASK)
12134/*! @} */
12135
12136/*! @name ATESTPRBSERRCNT - Address Loopback Test Result register */
12137/*! @{ */
12138#define DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATestPrbsErrCnt_MASK (0xFFFFU)
12139#define DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATestPrbsErrCnt_SHIFT (0U)
12140#define DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATestPrbsErrCnt(x) \
12141 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATestPrbsErrCnt_SHIFT)) & \
12142 DWC_DDRPHYA_ANIB_ATESTPRBSERRCNT_ATestPrbsErrCnt_MASK)
12143/*! @} */
12144
12145/*! @name ATXDLY_P0 - Address/Command Delay, per pstate. */
12146/*! @{ */
12147#define DWC_DDRPHYA_ANIB_ATXDLY_P0_ATxDly_p0_MASK (0x7FU)
12148#define DWC_DDRPHYA_ANIB_ATXDLY_P0_ATxDly_p0_SHIFT (0U)
12149#define DWC_DDRPHYA_ANIB_ATXDLY_P0_ATxDly_p0(x) \
12150 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXDLY_P0_ATxDly_p0_SHIFT)) & \
12151 DWC_DDRPHYA_ANIB_ATXDLY_P0_ATxDly_p0_MASK)
12152/*! @} */
12153
12154/*! @name ATXDLY_P1 - Address/Command Delay, per pstate. */
12155/*! @{ */
12156#define DWC_DDRPHYA_ANIB_ATXDLY_P1_ATxDly_p1_MASK (0x7FU)
12157#define DWC_DDRPHYA_ANIB_ATXDLY_P1_ATxDly_p1_SHIFT (0U)
12158#define DWC_DDRPHYA_ANIB_ATXDLY_P1_ATxDly_p1(x) \
12159 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXDLY_P1_ATxDly_p1_SHIFT)) & \
12160 DWC_DDRPHYA_ANIB_ATXDLY_P1_ATxDly_p1_MASK)
12161/*! @} */
12162
12163/*! @name ATXDLY_P2 - Address/Command Delay, per pstate. */
12164/*! @{ */
12165#define DWC_DDRPHYA_ANIB_ATXDLY_P2_ATxDly_p2_MASK (0x7FU)
12166#define DWC_DDRPHYA_ANIB_ATXDLY_P2_ATxDly_p2_SHIFT (0U)
12167#define DWC_DDRPHYA_ANIB_ATXDLY_P2_ATxDly_p2(x) \
12168 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXDLY_P2_ATxDly_p2_SHIFT)) & \
12169 DWC_DDRPHYA_ANIB_ATXDLY_P2_ATxDly_p2_MASK)
12170/*! @} */
12171
12172/*! @name ATXDLY_P3 - Address/Command Delay, per pstate. */
12173/*! @{ */
12174#define DWC_DDRPHYA_ANIB_ATXDLY_P3_ATxDly_p3_MASK (0x7FU)
12175#define DWC_DDRPHYA_ANIB_ATXDLY_P3_ATxDly_p3_SHIFT (0U)
12176#define DWC_DDRPHYA_ANIB_ATXDLY_P3_ATxDly_p3(x) \
12177 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_ANIB_ATXDLY_P3_ATxDly_p3_SHIFT)) & \
12178 DWC_DDRPHYA_ANIB_ATXDLY_P3_ATxDly_p3_MASK)
12179/*! @} */
12180
12181/*!
12182 * @}
12183 */ /* end of group DWC_DDRPHYA_ANIB_Register_Masks */
12184
12185/* DWC_DDRPHYA_ANIB - Peripheral instance base addresses */
12186/** Peripheral DWC_DDRPHYA_ANIB0 base address */
12187#define DWC_DDRPHYA_ANIB0_BASE (0x3C000000u)
12188/** Peripheral DWC_DDRPHYA_ANIB0 base pointer */
12189#define DWC_DDRPHYA_ANIB0 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB0_BASE)
12190/** Peripheral DWC_DDRPHYA_ANIB1 base address */
12191#define DWC_DDRPHYA_ANIB1_BASE (0x3C001000u)
12192/** Peripheral DWC_DDRPHYA_ANIB1 base pointer */
12193#define DWC_DDRPHYA_ANIB1 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB1_BASE)
12194/** Peripheral DWC_DDRPHYA_ANIB2 base address */
12195#define DWC_DDRPHYA_ANIB2_BASE (0x3C002000u)
12196/** Peripheral DWC_DDRPHYA_ANIB2 base pointer */
12197#define DWC_DDRPHYA_ANIB2 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB2_BASE)
12198/** Peripheral DWC_DDRPHYA_ANIB3 base address */
12199#define DWC_DDRPHYA_ANIB3_BASE (0x3C003000u)
12200/** Peripheral DWC_DDRPHYA_ANIB3 base pointer */
12201#define DWC_DDRPHYA_ANIB3 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB3_BASE)
12202/** Peripheral DWC_DDRPHYA_ANIB4 base address */
12203#define DWC_DDRPHYA_ANIB4_BASE (0x3C004000u)
12204/** Peripheral DWC_DDRPHYA_ANIB4 base pointer */
12205#define DWC_DDRPHYA_ANIB4 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB4_BASE)
12206/** Peripheral DWC_DDRPHYA_ANIB5 base address */
12207#define DWC_DDRPHYA_ANIB5_BASE (0x3C005000u)
12208/** Peripheral DWC_DDRPHYA_ANIB5 base pointer */
12209#define DWC_DDRPHYA_ANIB5 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB5_BASE)
12210/** Peripheral DWC_DDRPHYA_ANIB6 base address */
12211#define DWC_DDRPHYA_ANIB6_BASE (0x3C006000u)
12212/** Peripheral DWC_DDRPHYA_ANIB6 base pointer */
12213#define DWC_DDRPHYA_ANIB6 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB6_BASE)
12214/** Peripheral DWC_DDRPHYA_ANIB7 base address */
12215#define DWC_DDRPHYA_ANIB7_BASE (0x3C007000u)
12216/** Peripheral DWC_DDRPHYA_ANIB7 base pointer */
12217#define DWC_DDRPHYA_ANIB7 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB7_BASE)
12218/** Peripheral DWC_DDRPHYA_ANIB8 base address */
12219#define DWC_DDRPHYA_ANIB8_BASE (0x3C008000u)
12220/** Peripheral DWC_DDRPHYA_ANIB8 base pointer */
12221#define DWC_DDRPHYA_ANIB8 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB8_BASE)
12222/** Peripheral DWC_DDRPHYA_ANIB9 base address */
12223#define DWC_DDRPHYA_ANIB9_BASE (0x3C009000u)
12224/** Peripheral DWC_DDRPHYA_ANIB9 base pointer */
12225#define DWC_DDRPHYA_ANIB9 ((DWC_DDRPHYA_ANIB_Type *)DWC_DDRPHYA_ANIB9_BASE)
12226/** Array initializer of DWC_DDRPHYA_ANIB peripheral base addresses */
12227#define DWC_DDRPHYA_ANIB_BASE_ADDRS \
12228 { \
12229 DWC_DDRPHYA_ANIB0_BASE, DWC_DDRPHYA_ANIB1_BASE, DWC_DDRPHYA_ANIB2_BASE, DWC_DDRPHYA_ANIB3_BASE, \
12230 DWC_DDRPHYA_ANIB4_BASE, DWC_DDRPHYA_ANIB5_BASE, DWC_DDRPHYA_ANIB6_BASE, DWC_DDRPHYA_ANIB7_BASE, \
12231 DWC_DDRPHYA_ANIB8_BASE, DWC_DDRPHYA_ANIB9_BASE \
12232 }
12233/** Array initializer of DWC_DDRPHYA_ANIB peripheral base pointers */
12234#define DWC_DDRPHYA_ANIB_BASE_PTRS \
12235 { \
12236 DWC_DDRPHYA_ANIB0, DWC_DDRPHYA_ANIB1, DWC_DDRPHYA_ANIB2, DWC_DDRPHYA_ANIB3, DWC_DDRPHYA_ANIB4, \
12237 DWC_DDRPHYA_ANIB5, DWC_DDRPHYA_ANIB6, DWC_DDRPHYA_ANIB7, DWC_DDRPHYA_ANIB8, DWC_DDRPHYA_ANIB9 \
12238 }
12239
12240/*!
12241 * @}
12242 */ /* end of group DWC_DDRPHYA_ANIB_Peripheral_Access_Layer */
12243
12244/* ----------------------------------------------------------------------------
12245 -- DWC_DDRPHYA_APBONLY Peripheral Access Layer
12246 ---------------------------------------------------------------------------- */
12247
12248/*!
12249 * @addtogroup DWC_DDRPHYA_APBONLY_Peripheral_Access_Layer DWC_DDRPHYA_APBONLY Peripheral Access Layer
12250 * @{
12251 */
12252
12253/** DWC_DDRPHYA_APBONLY - Register Layout Typedef */
12254typedef struct
12255{
12256 __IO uint16_t MICROCONTMUXSEL; /**< PMU Config Mux Select, offset: 0x0 */
12257 uint8_t RESERVED_0[6];
12258 __I uint16_t UCTSHADOWREGS; /**< PMU/Controller Protocol - Controller Read-only Shadow, offset: 0x8 */
12259 uint8_t RESERVED_1[86];
12260 __IO uint16_t DCTWRITEONLY; /**< Reserved for future use., offset: 0x60 */
12261 __IO uint16_t DCTWRITEPROT; /**< DCT downstream mailbox protocol CSR., offset: 0x62 */
12262 __I uint16_t UCTWRITEONLYSHADOW; /**< Read-only view of the csr UctDatWriteOnly, offset: 0x64 */
12263 uint8_t RESERVED_2[2];
12264 __I uint16_t UCTDATWRITEONLYSHADOW; /**< Read-only view of the csr UctDatWriteOnly, offset: 0x68 */
12265 uint8_t RESERVED_3[4];
12266 __IO uint16_t DFICFGRDDATAVALIDTICKS; /**< Number of DfiClk ticks required for valid csr Rd Data., offset: 0x6E */
12267 uint8_t RESERVED_4[194];
12268 __IO uint16_t MICRORESET; /**< Controls reset and clock shutdown on the local microcontroller, offset: 0x132 */
12269 uint8_t RESERVED_5[192];
12270 __I uint16_t DFIINITCOMPLETESHADOW; /**< dfi_init_complete - Controller Read-only Shadow, offset: 0x1F4 */
12271} DWC_DDRPHYA_APBONLY_Type;
12272
12273/* ----------------------------------------------------------------------------
12274 -- DWC_DDRPHYA_APBONLY Register Masks
12275 ---------------------------------------------------------------------------- */
12276
12277/*!
12278 * @addtogroup DWC_DDRPHYA_APBONLY_Register_Masks DWC_DDRPHYA_APBONLY Register Masks
12279 * @{
12280 */
12281
12282/*! @name MICROCONTMUXSEL - PMU Config Mux Select */
12283/*! @{ */
12284#define DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MicroContMuxSel_MASK (0x1U)
12285#define DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MicroContMuxSel_SHIFT (0U)
12286#define DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MicroContMuxSel(x) \
12287 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MicroContMuxSel_SHIFT)) & \
12288 DWC_DDRPHYA_APBONLY_MICROCONTMUXSEL_MicroContMuxSel_MASK)
12289/*! @} */
12290
12291/*! @name UCTSHADOWREGS - PMU/Controller Protocol - Controller Read-only Shadow */
12292/*! @{ */
12293#define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctWriteProtShadow_MASK (0x1U)
12294#define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctWriteProtShadow_SHIFT (0U)
12295#define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctWriteProtShadow(x) \
12296 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctWriteProtShadow_SHIFT)) & \
12297 DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctWriteProtShadow_MASK)
12298#define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctDatWriteProtShadow_MASK (0x2U)
12299#define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctDatWriteProtShadow_SHIFT (1U)
12300#define DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctDatWriteProtShadow(x) \
12301 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctDatWriteProtShadow_SHIFT)) & \
12302 DWC_DDRPHYA_APBONLY_UCTSHADOWREGS_UctDatWriteProtShadow_MASK)
12303/*! @} */
12304
12305/*! @name DCTWRITEONLY - Reserved for future use. */
12306/*! @{ */
12307#define DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DctWriteOnly_MASK (0xFFFFU)
12308#define DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DctWriteOnly_SHIFT (0U)
12309#define DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DctWriteOnly(x) \
12310 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DctWriteOnly_SHIFT)) & \
12311 DWC_DDRPHYA_APBONLY_DCTWRITEONLY_DctWriteOnly_MASK)
12312/*! @} */
12313
12314/*! @name DCTWRITEPROT - DCT downstream mailbox protocol CSR. */
12315/*! @{ */
12316#define DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DctWriteProt_MASK (0x1U)
12317#define DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DctWriteProt_SHIFT (0U)
12318#define DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DctWriteProt(x) \
12319 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DctWriteProt_SHIFT)) & \
12320 DWC_DDRPHYA_APBONLY_DCTWRITEPROT_DctWriteProt_MASK)
12321/*! @} */
12322
12323/*! @name UCTWRITEONLYSHADOW - Read-only view of the csr UctDatWriteOnly */
12324/*! @{ */
12325#define DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UctWriteOnlyShadow_MASK (0xFFFFU)
12326#define DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UctWriteOnlyShadow_SHIFT (0U)
12327#define DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UctWriteOnlyShadow(x) \
12328 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UctWriteOnlyShadow_SHIFT)) & \
12329 DWC_DDRPHYA_APBONLY_UCTWRITEONLYSHADOW_UctWriteOnlyShadow_MASK)
12330/*! @} */
12331
12332/*! @name UCTDATWRITEONLYSHADOW - Read-only view of the csr UctDatWriteOnly */
12333/*! @{ */
12334#define DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UctDatWriteOnlyShadow_MASK (0xFFFFU)
12335#define DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UctDatWriteOnlyShadow_SHIFT (0U)
12336#define DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UctDatWriteOnlyShadow(x) \
12337 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UctDatWriteOnlyShadow_SHIFT)) & \
12338 DWC_DDRPHYA_APBONLY_UCTDATWRITEONLYSHADOW_UctDatWriteOnlyShadow_MASK)
12339/*! @} */
12340
12341/*! @name DFICFGRDDATAVALIDTICKS - Number of DfiClk ticks required for valid csr Rd Data. */
12342/*! @{ */
12343#define DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DfiCfgRdDataValidTicks_MASK (0x3FU)
12344#define DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DfiCfgRdDataValidTicks_SHIFT (0U)
12345#define DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DfiCfgRdDataValidTicks(x) \
12346 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DfiCfgRdDataValidTicks_SHIFT)) & \
12347 DWC_DDRPHYA_APBONLY_DFICFGRDDATAVALIDTICKS_DfiCfgRdDataValidTicks_MASK)
12348/*! @} */
12349
12350/*! @name MICRORESET - Controls reset and clock shutdown on the local microcontroller */
12351/*! @{ */
12352#define DWC_DDRPHYA_APBONLY_MICRORESET_StallToMicro_MASK (0x1U)
12353#define DWC_DDRPHYA_APBONLY_MICRORESET_StallToMicro_SHIFT (0U)
12354#define DWC_DDRPHYA_APBONLY_MICRORESET_StallToMicro(x) \
12355 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICRORESET_StallToMicro_SHIFT)) & \
12356 DWC_DDRPHYA_APBONLY_MICRORESET_StallToMicro_MASK)
12357#define DWC_DDRPHYA_APBONLY_MICRORESET_TestWakeup_MASK (0x2U)
12358#define DWC_DDRPHYA_APBONLY_MICRORESET_TestWakeup_SHIFT (1U)
12359#define DWC_DDRPHYA_APBONLY_MICRORESET_TestWakeup(x) \
12360 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICRORESET_TestWakeup_SHIFT)) & \
12361 DWC_DDRPHYA_APBONLY_MICRORESET_TestWakeup_MASK)
12362#define DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMicro_MASK (0x4U)
12363#define DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMicro_SHIFT (2U)
12364#define DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMicro(x) \
12365 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMicro_SHIFT)) & \
12366 DWC_DDRPHYA_APBONLY_MICRORESET_RSVDMicro_MASK)
12367#define DWC_DDRPHYA_APBONLY_MICRORESET_ResetToMicro_MASK (0x8U)
12368#define DWC_DDRPHYA_APBONLY_MICRORESET_ResetToMicro_SHIFT (3U)
12369#define DWC_DDRPHYA_APBONLY_MICRORESET_ResetToMicro(x) \
12370 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_MICRORESET_ResetToMicro_SHIFT)) & \
12371 DWC_DDRPHYA_APBONLY_MICRORESET_ResetToMicro_MASK)
12372/*! @} */
12373
12374/*! @name DFIINITCOMPLETESHADOW - dfi_init_complete - Controller Read-only Shadow */
12375/*! @{ */
12376#define DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DfiInitCompleteShadow_MASK (0x1U)
12377#define DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DfiInitCompleteShadow_SHIFT (0U)
12378#define DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DfiInitCompleteShadow(x) \
12379 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DfiInitCompleteShadow_SHIFT)) & \
12380 DWC_DDRPHYA_APBONLY_DFIINITCOMPLETESHADOW_DfiInitCompleteShadow_MASK)
12381/*! @} */
12382
12383/*!
12384 * @}
12385 */ /* end of group DWC_DDRPHYA_APBONLY_Register_Masks */
12386
12387/* DWC_DDRPHYA_APBONLY - Peripheral instance base addresses */
12388/** Peripheral DWC_DDRPHYA_APBONLY0 base address */
12389#define DWC_DDRPHYA_APBONLY0_BASE (0x3C0D0000u)
12390/** Peripheral DWC_DDRPHYA_APBONLY0 base pointer */
12391#define DWC_DDRPHYA_APBONLY0 ((DWC_DDRPHYA_APBONLY_Type *)DWC_DDRPHYA_APBONLY0_BASE)
12392/** Array initializer of DWC_DDRPHYA_APBONLY peripheral base addresses */
12393#define DWC_DDRPHYA_APBONLY_BASE_ADDRS \
12394 { \
12395 DWC_DDRPHYA_APBONLY0_BASE \
12396 }
12397/** Array initializer of DWC_DDRPHYA_APBONLY peripheral base pointers */
12398#define DWC_DDRPHYA_APBONLY_BASE_PTRS \
12399 { \
12400 DWC_DDRPHYA_APBONLY0 \
12401 }
12402
12403/*!
12404 * @}
12405 */ /* end of group DWC_DDRPHYA_APBONLY_Peripheral_Access_Layer */
12406
12407/* ----------------------------------------------------------------------------
12408 -- DWC_DDRPHYA_DBYTE Peripheral Access Layer
12409 ---------------------------------------------------------------------------- */
12410
12411/*!
12412 * @addtogroup DWC_DDRPHYA_DBYTE_Peripheral_Access_Layer DWC_DDRPHYA_DBYTE Peripheral Access Layer
12413 * @{
12414 */
12415
12416/** DWC_DDRPHYA_DBYTE - Register Layout Typedef */
12417typedef struct
12418{
12419 __IO uint16_t DBYTEMISCMODE; /**< DBYTE Module Disable, offset: 0x0 */
12420 uint8_t RESERVED_0[50];
12421 __IO uint16_t MTESTMUXSEL; /**< Digital Observation Pin control, offset: 0x34 */
12422 uint8_t RESERVED_1[10];
12423 __IO uint16_t DFIMRL_P0; /**< DFI MaxReadLatency, offset: 0x40 */
12424 uint8_t RESERVED_2[30];
12425 __IO uint16_t
12426 VREFDAC1_R0; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x60 */
12427 uint8_t RESERVED_3[30];
12428 __IO uint16_t VREFDAC0_R0; /**< VrefDAC0 control for DQ Receiver, offset: 0x80 */
12429 __IO uint16_t TXIMPEDANCECTRL0_B0_P0; /**< Data TX impedance controls, offset: 0x82 */
12430 uint8_t RESERVED_4[2];
12431 __IO uint16_t DQDQSRCVCNTRL_B0_P0; /**< Dq/Dqs receiver control, offset: 0x86 */
12432 uint8_t RESERVED_5[8];
12433 __IO uint16_t TXEQUALIZATIONMODE_P0; /**< Tx dq driver equalization mode controls., offset: 0x90 */
12434 __IO uint16_t TXIMPEDANCECTRL1_B0_P0; /**< TX impedance controls, offset: 0x92 */
12435 __IO uint16_t DQDQSRCVCNTRL1; /**< Dq/Dqs receiver control, offset: 0x94 */
12436 __IO uint16_t TXIMPEDANCECTRL2_B0_P0; /**< TX equalization impedance controls, offset: 0x96 */
12437 __IO uint16_t DQDQSRCVCNTRL2_P0; /**< Dq/Dqs receiver control, offset: 0x98 */
12438 __IO uint16_t TXODTDRVSTREN_B0_P0; /**< TX ODT driver strength control, offset: 0x9A */
12439 uint8_t RESERVED_6[16];
12440 __I uint16_t RXFIFOCHECKSTATUS; /**< Status of RX FIFO Consistency Checks, offset: 0xAC */
12441 __I uint16_t RXFIFOCHECKERRVALUES; /**< Contains the captured values associated with an RxFifo consistency error,
12442 offset: 0xAE */
12443 __I uint16_t RXFIFOINFO; /**< Data Receive FIFO Pointer Values, offset: 0xB0 */
12444 __IO uint16_t RXFIFOVISIBILITY; /**< RX FIFO visibility, offset: 0xB2 */
12445 __I uint16_t RXFIFOCONTENTSDQ3210; /**< RX FIFO contents, lane[3:0], offset: 0xB4 */
12446 __I uint16_t RXFIFOCONTENTSDQ7654; /**< RX FIFO contents, lane[7:4], offset: 0xB6 */
12447 __I uint16_t RXFIFOCONTENTSDBI; /**< RX FIFO contents, dbi, offset: 0xB8 */
12448 uint8_t RESERVED_7[4];
12449 __IO uint16_t TXSLEWRATE_B0_P0; /**< TX slew rate controls, offset: 0xBE */
12450 uint8_t RESERVED_8[16];
12451 __IO uint16_t RXPBDLYTG0_R0; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0xD0 */
12452 __IO uint16_t RXPBDLYTG1_R0; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0xD2 */
12453 __IO uint16_t RXPBDLYTG2_R0; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0xD4 */
12454 __IO uint16_t RXPBDLYTG3_R0; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0xD6 */
12455 uint8_t RESERVED_9[40];
12456 __IO uint16_t RXENDLYTG0_U0_P0; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x100 */
12457 __IO uint16_t RXENDLYTG1_U0_P0; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x102 */
12458 __IO uint16_t RXENDLYTG2_U0_P0; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x104 */
12459 __IO uint16_t RXENDLYTG3_U0_P0; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x106 */
12460 uint8_t RESERVED_10[16];
12461 __IO uint16_t RXCLKDLYTG0_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x118 */
12462 __IO uint16_t RXCLKDLYTG1_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x11A */
12463 __IO uint16_t RXCLKDLYTG2_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x11C */
12464 __IO uint16_t RXCLKDLYTG3_U0_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x11E */
12465 __IO uint16_t RXCLKCDLYTG0_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x120 */
12466 __IO uint16_t RXCLKCDLYTG1_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x122 */
12467 __IO uint16_t RXCLKCDLYTG2_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x124 */
12468 uint8_t RESERVED_11[2];
12469 __IO uint16_t RXCLKCDLYTG3_U0_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x128 */
12470 uint8_t RESERVED_12[22];
12471 __IO uint16_t DQLNSEL[8]; /**< Maps Phy DQ lane to memory DQ0, array offset: 0x140, array step: 0x2 */
12472 uint8_t RESERVED_13[48];
12473 __IO uint16_t TXDQDLYTG0_R0_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x180 */
12474 __IO uint16_t TXDQDLYTG1_R0_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x182 */
12475 __IO uint16_t TXDQDLYTG2_R0_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x184 */
12476 __IO uint16_t TXDQDLYTG3_R0_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x186 */
12477 uint8_t RESERVED_14[24];
12478 __IO uint16_t TXDQSDLYTG0_U0_P0; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x1A0 */
12479 __IO uint16_t TXDQSDLYTG1_U0_P0; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x1A2 */
12480 __IO uint16_t TXDQSDLYTG2_U0_P0; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x1A4 */
12481 __IO uint16_t TXDQSDLYTG3_U0_P0; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x1A6 */
12482 uint8_t RESERVED_15[32];
12483 __I uint16_t DXLCDLSTATUS; /**< Debug status of the DBYTE LCDL, offset: 0x1C8 */
12484 uint8_t RESERVED_16[150];
12485 __IO uint16_t
12486 VREFDAC1_R1; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x260 */
12487 uint8_t RESERVED_17[30];
12488 __IO uint16_t VREFDAC0_R1; /**< VrefDAC0 control for DQ Receiver, offset: 0x280 */
12489 __IO uint16_t TXIMPEDANCECTRL0_B1_P0; /**< Data TX impedance controls, offset: 0x282 */
12490 uint8_t RESERVED_18[2];
12491 __IO uint16_t DQDQSRCVCNTRL_B1_P0; /**< Dq/Dqs receiver control, offset: 0x286 */
12492 uint8_t RESERVED_19[10];
12493 __IO uint16_t TXIMPEDANCECTRL1_B1_P0; /**< TX impedance controls, offset: 0x292 */
12494 uint8_t RESERVED_20[2];
12495 __IO uint16_t TXIMPEDANCECTRL2_B1_P0; /**< TX equalization impedance controls, offset: 0x296 */
12496 uint8_t RESERVED_21[2];
12497 __IO uint16_t TXODTDRVSTREN_B1_P0; /**< TX ODT driver strength control, offset: 0x29A */
12498 uint8_t RESERVED_22[34];
12499 __IO uint16_t TXSLEWRATE_B1_P0; /**< TX slew rate controls, offset: 0x2BE */
12500 uint8_t RESERVED_23[16];
12501 __IO uint16_t RXPBDLYTG0_R1; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x2D0 */
12502 __IO uint16_t RXPBDLYTG1_R1; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x2D2 */
12503 __IO uint16_t RXPBDLYTG2_R1; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x2D4 */
12504 __IO uint16_t RXPBDLYTG3_R1; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x2D6 */
12505 uint8_t RESERVED_24[40];
12506 __IO uint16_t RXENDLYTG0_U1_P0; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x300 */
12507 __IO uint16_t RXENDLYTG1_U1_P0; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x302 */
12508 __IO uint16_t RXENDLYTG2_U1_P0; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x304 */
12509 __IO uint16_t RXENDLYTG3_U1_P0; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x306 */
12510 uint8_t RESERVED_25[16];
12511 __IO uint16_t RXCLKDLYTG0_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x318 */
12512 __IO uint16_t RXCLKDLYTG1_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x31A */
12513 __IO uint16_t RXCLKDLYTG2_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x31C */
12514 __IO uint16_t RXCLKDLYTG3_U1_P0; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x31E */
12515 __IO uint16_t RXCLKCDLYTG0_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x320 */
12516 __IO uint16_t RXCLKCDLYTG1_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x322 */
12517 __IO uint16_t RXCLKCDLYTG2_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x324 */
12518 uint8_t RESERVED_26[2];
12519 __IO uint16_t RXCLKCDLYTG3_U1_P0; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x328 */
12520 uint8_t RESERVED_27[86];
12521 __IO uint16_t TXDQDLYTG0_R1_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x380 */
12522 __IO uint16_t TXDQDLYTG1_R1_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x382 */
12523 __IO uint16_t TXDQDLYTG2_R1_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x384 */
12524 __IO uint16_t TXDQDLYTG3_R1_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x386 */
12525 uint8_t RESERVED_28[24];
12526 __IO uint16_t TXDQSDLYTG0_U1_P0; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x3A0 */
12527 __IO uint16_t TXDQSDLYTG1_U1_P0; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x3A2 */
12528 __IO uint16_t TXDQSDLYTG2_U1_P0; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x3A4 */
12529 __IO uint16_t TXDQSDLYTG3_U1_P0; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x3A6 */
12530 uint8_t RESERVED_29[184];
12531 __IO uint16_t
12532 VREFDAC1_R2; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x460 */
12533 uint8_t RESERVED_30[30];
12534 __IO uint16_t VREFDAC0_R2; /**< VrefDAC0 control for DQ Receiver, offset: 0x480 */
12535 uint8_t RESERVED_31[78];
12536 __IO uint16_t RXPBDLYTG0_R2; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x4D0 */
12537 __IO uint16_t RXPBDLYTG1_R2; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x4D2 */
12538 __IO uint16_t RXPBDLYTG2_R2; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x4D4 */
12539 __IO uint16_t RXPBDLYTG3_R2; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x4D6 */
12540 uint8_t RESERVED_32[168];
12541 __IO uint16_t TXDQDLYTG0_R2_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x580 */
12542 __IO uint16_t TXDQDLYTG1_R2_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x582 */
12543 __IO uint16_t TXDQDLYTG2_R2_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x584 */
12544 __IO uint16_t TXDQDLYTG3_R2_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x586 */
12545 uint8_t RESERVED_33[216];
12546 __IO uint16_t
12547 VREFDAC1_R3; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x660 */
12548 uint8_t RESERVED_34[30];
12549 __IO uint16_t VREFDAC0_R3; /**< VrefDAC0 control for DQ Receiver, offset: 0x680 */
12550 uint8_t RESERVED_35[78];
12551 __IO uint16_t RXPBDLYTG0_R3; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x6D0 */
12552 __IO uint16_t RXPBDLYTG1_R3; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x6D2 */
12553 __IO uint16_t RXPBDLYTG2_R3; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x6D4 */
12554 __IO uint16_t RXPBDLYTG3_R3; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x6D6 */
12555 uint8_t RESERVED_36[168];
12556 __IO uint16_t TXDQDLYTG0_R3_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x780 */
12557 __IO uint16_t TXDQDLYTG1_R3_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x782 */
12558 __IO uint16_t TXDQDLYTG2_R3_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x784 */
12559 __IO uint16_t TXDQDLYTG3_R3_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x786 */
12560 uint8_t RESERVED_37[216];
12561 __IO uint16_t
12562 VREFDAC1_R4; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x860 */
12563 uint8_t RESERVED_38[30];
12564 __IO uint16_t VREFDAC0_R4; /**< VrefDAC0 control for DQ Receiver, offset: 0x880 */
12565 uint8_t RESERVED_39[78];
12566 __IO uint16_t RXPBDLYTG0_R4; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x8D0 */
12567 __IO uint16_t RXPBDLYTG1_R4; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x8D2 */
12568 __IO uint16_t RXPBDLYTG2_R4; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x8D4 */
12569 __IO uint16_t RXPBDLYTG3_R4; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x8D6 */
12570 uint8_t RESERVED_40[168];
12571 __IO uint16_t TXDQDLYTG0_R4_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x980 */
12572 __IO uint16_t TXDQDLYTG1_R4_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x982 */
12573 __IO uint16_t TXDQDLYTG2_R4_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x984 */
12574 __IO uint16_t TXDQDLYTG3_R4_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x986 */
12575 uint8_t RESERVED_41[216];
12576 __IO uint16_t
12577 VREFDAC1_R5; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0xA60 */
12578 uint8_t RESERVED_42[30];
12579 __IO uint16_t VREFDAC0_R5; /**< VrefDAC0 control for DQ Receiver, offset: 0xA80 */
12580 uint8_t RESERVED_43[78];
12581 __IO uint16_t RXPBDLYTG0_R5; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0xAD0 */
12582 __IO uint16_t RXPBDLYTG1_R5; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0xAD2 */
12583 __IO uint16_t RXPBDLYTG2_R5; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0xAD4 */
12584 __IO uint16_t RXPBDLYTG3_R5; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0xAD6 */
12585 uint8_t RESERVED_44[168];
12586 __IO uint16_t TXDQDLYTG0_R5_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0xB80 */
12587 __IO uint16_t TXDQDLYTG1_R5_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0xB82 */
12588 __IO uint16_t TXDQDLYTG2_R5_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0xB84 */
12589 __IO uint16_t TXDQDLYTG3_R5_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0xB86 */
12590 uint8_t RESERVED_45[216];
12591 __IO uint16_t
12592 VREFDAC1_R6; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0xC60 */
12593 uint8_t RESERVED_46[30];
12594 __IO uint16_t VREFDAC0_R6; /**< VrefDAC0 control for DQ Receiver, offset: 0xC80 */
12595 uint8_t RESERVED_47[78];
12596 __IO uint16_t RXPBDLYTG0_R6; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0xCD0 */
12597 __IO uint16_t RXPBDLYTG1_R6; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0xCD2 */
12598 __IO uint16_t RXPBDLYTG2_R6; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0xCD4 */
12599 __IO uint16_t RXPBDLYTG3_R6; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0xCD6 */
12600 uint8_t RESERVED_48[168];
12601 __IO uint16_t TXDQDLYTG0_R6_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0xD80 */
12602 __IO uint16_t TXDQDLYTG1_R6_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0xD82 */
12603 __IO uint16_t TXDQDLYTG2_R6_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0xD84 */
12604 __IO uint16_t TXDQDLYTG3_R6_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0xD86 */
12605 uint8_t RESERVED_49[216];
12606 __IO uint16_t
12607 VREFDAC1_R7; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0xE60 */
12608 uint8_t RESERVED_50[30];
12609 __IO uint16_t VREFDAC0_R7; /**< VrefDAC0 control for DQ Receiver, offset: 0xE80 */
12610 uint8_t RESERVED_51[78];
12611 __IO uint16_t RXPBDLYTG0_R7; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0xED0 */
12612 __IO uint16_t RXPBDLYTG1_R7; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0xED2 */
12613 __IO uint16_t RXPBDLYTG2_R7; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0xED4 */
12614 __IO uint16_t RXPBDLYTG3_R7; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0xED6 */
12615 uint8_t RESERVED_52[168];
12616 __IO uint16_t TXDQDLYTG0_R7_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0xF80 */
12617 __IO uint16_t TXDQDLYTG1_R7_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0xF82 */
12618 __IO uint16_t TXDQDLYTG2_R7_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0xF84 */
12619 __IO uint16_t TXDQDLYTG3_R7_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0xF86 */
12620 uint8_t RESERVED_53[216];
12621 __IO uint16_t
12622 VREFDAC1_R8; /**< VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4), offset: 0x1060 */
12623 uint8_t RESERVED_54[30];
12624 __IO uint16_t VREFDAC0_R8; /**< VrefDAC0 control for DQ Receiver, offset: 0x1080 */
12625 uint8_t RESERVED_55[78];
12626 __IO uint16_t RXPBDLYTG0_R8; /**< Read DQ per-bit BDL delay (Timing Group 0)., offset: 0x10D0 */
12627 __IO uint16_t RXPBDLYTG1_R8; /**< Read DQ per-bit BDL delay (Timing Group 1)., offset: 0x10D2 */
12628 __IO uint16_t RXPBDLYTG2_R8; /**< Read DQ per-bit BDL delay (Timing Group 2)., offset: 0x10D4 */
12629 __IO uint16_t RXPBDLYTG3_R8; /**< Read DQ per-bit BDL delay (Timing Group 3)., offset: 0x10D6 */
12630 uint8_t RESERVED_56[168];
12631 __IO uint16_t TXDQDLYTG0_R8_P0; /**< Write DQ Delay (Timing Group 0)., offset: 0x1180 */
12632 __IO uint16_t TXDQDLYTG1_R8_P0; /**< Write DQ Delay (Timing Group 1)., offset: 0x1182 */
12633 __IO uint16_t TXDQDLYTG2_R8_P0; /**< Write DQ Delay (Timing Group 2)., offset: 0x1184 */
12634 __IO uint16_t TXDQDLYTG3_R8_P0; /**< Write DQ Delay (Timing Group 3)., offset: 0x1186 */
12635 uint8_t RESERVED_57[2092728];
12636 __IO uint16_t DFIMRL_P1; /**< DFI MaxReadLatency, offset: 0x200040 */
12637 uint8_t RESERVED_58[64];
12638 __IO uint16_t TXIMPEDANCECTRL0_B0_P1; /**< Data TX impedance controls, offset: 0x200082 */
12639 uint8_t RESERVED_59[2];
12640 __IO uint16_t DQDQSRCVCNTRL_B0_P1; /**< Dq/Dqs receiver control, offset: 0x200086 */
12641 uint8_t RESERVED_60[8];
12642 __IO uint16_t TXEQUALIZATIONMODE_P1; /**< Tx dq driver equalization mode controls., offset: 0x200090 */
12643 __IO uint16_t TXIMPEDANCECTRL1_B0_P1; /**< TX impedance controls, offset: 0x200092 */
12644 uint8_t RESERVED_61[2];
12645 __IO uint16_t TXIMPEDANCECTRL2_B0_P1; /**< TX equalization impedance controls, offset: 0x200096 */
12646 __IO uint16_t DQDQSRCVCNTRL2_P1; /**< Dq/Dqs receiver control, offset: 0x200098 */
12647 __IO uint16_t TXODTDRVSTREN_B0_P1; /**< TX ODT driver strength control, offset: 0x20009A */
12648 uint8_t RESERVED_62[34];
12649 __IO uint16_t TXSLEWRATE_B0_P1; /**< TX slew rate controls, offset: 0x2000BE */
12650 uint8_t RESERVED_63[64];
12651 __IO uint16_t RXENDLYTG0_U0_P1; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x200100 */
12652 __IO uint16_t RXENDLYTG1_U0_P1; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x200102 */
12653 __IO uint16_t RXENDLYTG2_U0_P1; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x200104 */
12654 __IO uint16_t RXENDLYTG3_U0_P1; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x200106 */
12655 uint8_t RESERVED_64[16];
12656 __IO uint16_t RXCLKDLYTG0_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x200118 */
12657 __IO uint16_t RXCLKDLYTG1_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x20011A */
12658 __IO uint16_t RXCLKDLYTG2_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x20011C */
12659 __IO uint16_t RXCLKDLYTG3_U0_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x20011E */
12660 __IO uint16_t
12661 RXCLKCDLYTG0_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x200120 */
12662 __IO uint16_t
12663 RXCLKCDLYTG1_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x200122 */
12664 __IO uint16_t
12665 RXCLKCDLYTG2_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x200124 */
12666 uint8_t RESERVED_65[2];
12667 __IO uint16_t
12668 RXCLKCDLYTG3_U0_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x200128 */
12669 uint8_t RESERVED_66[86];
12670 __IO uint16_t TXDQDLYTG0_R0_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200180 */
12671 __IO uint16_t TXDQDLYTG1_R0_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200182 */
12672 __IO uint16_t TXDQDLYTG2_R0_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200184 */
12673 __IO uint16_t TXDQDLYTG3_R0_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200186 */
12674 uint8_t RESERVED_67[24];
12675 __IO uint16_t TXDQSDLYTG0_U0_P1; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x2001A0 */
12676 __IO uint16_t TXDQSDLYTG1_U0_P1; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x2001A2 */
12677 __IO uint16_t TXDQSDLYTG2_U0_P1; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x2001A4 */
12678 __IO uint16_t TXDQSDLYTG3_U0_P1; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x2001A6 */
12679 uint8_t RESERVED_68[218];
12680 __IO uint16_t TXIMPEDANCECTRL0_B1_P1; /**< Data TX impedance controls, offset: 0x200282 */
12681 uint8_t RESERVED_69[2];
12682 __IO uint16_t DQDQSRCVCNTRL_B1_P1; /**< Dq/Dqs receiver control, offset: 0x200286 */
12683 uint8_t RESERVED_70[10];
12684 __IO uint16_t TXIMPEDANCECTRL1_B1_P1; /**< TX impedance controls, offset: 0x200292 */
12685 uint8_t RESERVED_71[2];
12686 __IO uint16_t TXIMPEDANCECTRL2_B1_P1; /**< TX equalization impedance controls, offset: 0x200296 */
12687 uint8_t RESERVED_72[2];
12688 __IO uint16_t TXODTDRVSTREN_B1_P1; /**< TX ODT driver strength control, offset: 0x20029A */
12689 uint8_t RESERVED_73[34];
12690 __IO uint16_t TXSLEWRATE_B1_P1; /**< TX slew rate controls, offset: 0x2002BE */
12691 uint8_t RESERVED_74[64];
12692 __IO uint16_t RXENDLYTG0_U1_P1; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x200300 */
12693 __IO uint16_t RXENDLYTG1_U1_P1; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x200302 */
12694 __IO uint16_t RXENDLYTG2_U1_P1; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x200304 */
12695 __IO uint16_t RXENDLYTG3_U1_P1; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x200306 */
12696 uint8_t RESERVED_75[16];
12697 __IO uint16_t RXCLKDLYTG0_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x200318 */
12698 __IO uint16_t RXCLKDLYTG1_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x20031A */
12699 __IO uint16_t RXCLKDLYTG2_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x20031C */
12700 __IO uint16_t RXCLKDLYTG3_U1_P1; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x20031E */
12701 __IO uint16_t
12702 RXCLKCDLYTG0_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x200320 */
12703 __IO uint16_t
12704 RXCLKCDLYTG1_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x200322 */
12705 __IO uint16_t
12706 RXCLKCDLYTG2_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x200324 */
12707 uint8_t RESERVED_76[2];
12708 __IO uint16_t
12709 RXCLKCDLYTG3_U1_P1; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x200328 */
12710 uint8_t RESERVED_77[86];
12711 __IO uint16_t TXDQDLYTG0_R1_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200380 */
12712 __IO uint16_t TXDQDLYTG1_R1_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200382 */
12713 __IO uint16_t TXDQDLYTG2_R1_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200384 */
12714 __IO uint16_t TXDQDLYTG3_R1_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200386 */
12715 uint8_t RESERVED_78[24];
12716 __IO uint16_t TXDQSDLYTG0_U1_P1; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x2003A0 */
12717 __IO uint16_t TXDQSDLYTG1_U1_P1; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x2003A2 */
12718 __IO uint16_t TXDQSDLYTG2_U1_P1; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x2003A4 */
12719 __IO uint16_t TXDQSDLYTG3_U1_P1; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x2003A6 */
12720 uint8_t RESERVED_79[472];
12721 __IO uint16_t TXDQDLYTG0_R2_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200580 */
12722 __IO uint16_t TXDQDLYTG1_R2_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200582 */
12723 __IO uint16_t TXDQDLYTG2_R2_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200584 */
12724 __IO uint16_t TXDQDLYTG3_R2_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200586 */
12725 uint8_t RESERVED_80[504];
12726 __IO uint16_t TXDQDLYTG0_R3_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200780 */
12727 __IO uint16_t TXDQDLYTG1_R3_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200782 */
12728 __IO uint16_t TXDQDLYTG2_R3_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200784 */
12729 __IO uint16_t TXDQDLYTG3_R3_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200786 */
12730 uint8_t RESERVED_81[504];
12731 __IO uint16_t TXDQDLYTG0_R4_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200980 */
12732 __IO uint16_t TXDQDLYTG1_R4_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200982 */
12733 __IO uint16_t TXDQDLYTG2_R4_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200984 */
12734 __IO uint16_t TXDQDLYTG3_R4_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200986 */
12735 uint8_t RESERVED_82[504];
12736 __IO uint16_t TXDQDLYTG0_R5_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200B80 */
12737 __IO uint16_t TXDQDLYTG1_R5_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200B82 */
12738 __IO uint16_t TXDQDLYTG2_R5_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200B84 */
12739 __IO uint16_t TXDQDLYTG3_R5_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200B86 */
12740 uint8_t RESERVED_83[504];
12741 __IO uint16_t TXDQDLYTG0_R6_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200D80 */
12742 __IO uint16_t TXDQDLYTG1_R6_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200D82 */
12743 __IO uint16_t TXDQDLYTG2_R6_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200D84 */
12744 __IO uint16_t TXDQDLYTG3_R6_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200D86 */
12745 uint8_t RESERVED_84[504];
12746 __IO uint16_t TXDQDLYTG0_R7_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x200F80 */
12747 __IO uint16_t TXDQDLYTG1_R7_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x200F82 */
12748 __IO uint16_t TXDQDLYTG2_R7_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x200F84 */
12749 __IO uint16_t TXDQDLYTG3_R7_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x200F86 */
12750 uint8_t RESERVED_85[504];
12751 __IO uint16_t TXDQDLYTG0_R8_P1; /**< Write DQ Delay (Timing Group 0)., offset: 0x201180 */
12752 __IO uint16_t TXDQDLYTG1_R8_P1; /**< Write DQ Delay (Timing Group 1)., offset: 0x201182 */
12753 __IO uint16_t TXDQDLYTG2_R8_P1; /**< Write DQ Delay (Timing Group 2)., offset: 0x201184 */
12754 __IO uint16_t TXDQDLYTG3_R8_P1; /**< Write DQ Delay (Timing Group 3)., offset: 0x201186 */
12755 uint8_t RESERVED_86[2092728];
12756 __IO uint16_t DFIMRL_P2; /**< DFI MaxReadLatency, offset: 0x400040 */
12757 uint8_t RESERVED_87[64];
12758 __IO uint16_t TXIMPEDANCECTRL0_B0_P2; /**< Data TX impedance controls, offset: 0x400082 */
12759 uint8_t RESERVED_88[2];
12760 __IO uint16_t DQDQSRCVCNTRL_B0_P2; /**< Dq/Dqs receiver control, offset: 0x400086 */
12761 uint8_t RESERVED_89[8];
12762 __IO uint16_t TXEQUALIZATIONMODE_P2; /**< Tx dq driver equalization mode controls., offset: 0x400090 */
12763 __IO uint16_t TXIMPEDANCECTRL1_B0_P2; /**< TX impedance controls, offset: 0x400092 */
12764 uint8_t RESERVED_90[2];
12765 __IO uint16_t TXIMPEDANCECTRL2_B0_P2; /**< TX equalization impedance controls, offset: 0x400096 */
12766 __IO uint16_t DQDQSRCVCNTRL2_P2; /**< Dq/Dqs receiver control, offset: 0x400098 */
12767 __IO uint16_t TXODTDRVSTREN_B0_P2; /**< TX ODT driver strength control, offset: 0x40009A */
12768 uint8_t RESERVED_91[34];
12769 __IO uint16_t TXSLEWRATE_B0_P2; /**< TX slew rate controls, offset: 0x4000BE */
12770 uint8_t RESERVED_92[64];
12771 __IO uint16_t RXENDLYTG0_U0_P2; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x400100 */
12772 __IO uint16_t RXENDLYTG1_U0_P2; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x400102 */
12773 __IO uint16_t RXENDLYTG2_U0_P2; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x400104 */
12774 __IO uint16_t RXENDLYTG3_U0_P2; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x400106 */
12775 uint8_t RESERVED_93[16];
12776 __IO uint16_t RXCLKDLYTG0_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x400118 */
12777 __IO uint16_t RXCLKDLYTG1_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x40011A */
12778 __IO uint16_t RXCLKDLYTG2_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x40011C */
12779 __IO uint16_t RXCLKDLYTG3_U0_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x40011E */
12780 __IO uint16_t
12781 RXCLKCDLYTG0_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x400120 */
12782 __IO uint16_t
12783 RXCLKCDLYTG1_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x400122 */
12784 __IO uint16_t
12785 RXCLKCDLYTG2_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x400124 */
12786 uint8_t RESERVED_94[2];
12787 __IO uint16_t
12788 RXCLKCDLYTG3_U0_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x400128 */
12789 uint8_t RESERVED_95[50];
12790 __IO uint16_t PPTDQSCNTINVTRNTG0_P2; /**< DQS Oscillator Count inverse at time of training in LPDDR4 drift
12791 compensation, offset: 0x40015C */
12792 __IO uint16_t PPTDQSCNTINVTRNTG1_P2; /**< DQS Oscillator Count inverse at time of training in LPDDR4 drift
12793 compensation, offset: 0x40015E */
12794 uint8_t RESERVED_96[32];
12795 __IO uint16_t TXDQDLYTG0_R0_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400180 */
12796 __IO uint16_t TXDQDLYTG1_R0_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400182 */
12797 __IO uint16_t TXDQDLYTG2_R0_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400184 */
12798 __IO uint16_t TXDQDLYTG3_R0_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400186 */
12799 uint8_t RESERVED_97[24];
12800 __IO uint16_t TXDQSDLYTG0_U0_P2; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x4001A0 */
12801 __IO uint16_t TXDQSDLYTG1_U0_P2; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x4001A2 */
12802 __IO uint16_t TXDQSDLYTG2_U0_P2; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x4001A4 */
12803 __IO uint16_t TXDQSDLYTG3_U0_P2; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x4001A6 */
12804 uint8_t RESERVED_98[218];
12805 __IO uint16_t TXIMPEDANCECTRL0_B1_P2; /**< Data TX impedance controls, offset: 0x400282 */
12806 uint8_t RESERVED_99[2];
12807 __IO uint16_t DQDQSRCVCNTRL_B1_P2; /**< Dq/Dqs receiver control, offset: 0x400286 */
12808 uint8_t RESERVED_100[10];
12809 __IO uint16_t TXIMPEDANCECTRL1_B1_P2; /**< TX impedance controls, offset: 0x400292 */
12810 uint8_t RESERVED_101[2];
12811 __IO uint16_t TXIMPEDANCECTRL2_B1_P2; /**< TX equalization impedance controls, offset: 0x400296 */
12812 uint8_t RESERVED_102[2];
12813 __IO uint16_t TXODTDRVSTREN_B1_P2; /**< TX ODT driver strength control, offset: 0x40029A */
12814 uint8_t RESERVED_103[34];
12815 __IO uint16_t TXSLEWRATE_B1_P2; /**< TX slew rate controls, offset: 0x4002BE */
12816 uint8_t RESERVED_104[64];
12817 __IO uint16_t RXENDLYTG0_U1_P2; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x400300 */
12818 __IO uint16_t RXENDLYTG1_U1_P2; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x400302 */
12819 __IO uint16_t RXENDLYTG2_U1_P2; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x400304 */
12820 __IO uint16_t RXENDLYTG3_U1_P2; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x400306 */
12821 uint8_t RESERVED_105[16];
12822 __IO uint16_t RXCLKDLYTG0_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x400318 */
12823 __IO uint16_t RXCLKDLYTG1_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x40031A */
12824 __IO uint16_t RXCLKDLYTG2_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x40031C */
12825 __IO uint16_t RXCLKDLYTG3_U1_P2; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x40031E */
12826 __IO uint16_t
12827 RXCLKCDLYTG0_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x400320 */
12828 __IO uint16_t
12829 RXCLKCDLYTG1_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x400322 */
12830 __IO uint16_t
12831 RXCLKCDLYTG2_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x400324 */
12832 uint8_t RESERVED_106[2];
12833 __IO uint16_t
12834 RXCLKCDLYTG3_U1_P2; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x400328 */
12835 uint8_t RESERVED_107[86];
12836 __IO uint16_t TXDQDLYTG0_R1_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400380 */
12837 __IO uint16_t TXDQDLYTG1_R1_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400382 */
12838 __IO uint16_t TXDQDLYTG2_R1_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400384 */
12839 __IO uint16_t TXDQDLYTG3_R1_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400386 */
12840 uint8_t RESERVED_108[24];
12841 __IO uint16_t TXDQSDLYTG0_U1_P2; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x4003A0 */
12842 __IO uint16_t TXDQSDLYTG1_U1_P2; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x4003A2 */
12843 __IO uint16_t TXDQSDLYTG2_U1_P2; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x4003A4 */
12844 __IO uint16_t TXDQSDLYTG3_U1_P2; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x4003A6 */
12845 uint8_t RESERVED_109[472];
12846 __IO uint16_t TXDQDLYTG0_R2_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400580 */
12847 __IO uint16_t TXDQDLYTG1_R2_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400582 */
12848 __IO uint16_t TXDQDLYTG2_R2_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400584 */
12849 __IO uint16_t TXDQDLYTG3_R2_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400586 */
12850 uint8_t RESERVED_110[504];
12851 __IO uint16_t TXDQDLYTG0_R3_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400780 */
12852 __IO uint16_t TXDQDLYTG1_R3_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400782 */
12853 __IO uint16_t TXDQDLYTG2_R3_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400784 */
12854 __IO uint16_t TXDQDLYTG3_R3_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400786 */
12855 uint8_t RESERVED_111[504];
12856 __IO uint16_t TXDQDLYTG0_R4_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400980 */
12857 __IO uint16_t TXDQDLYTG1_R4_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400982 */
12858 __IO uint16_t TXDQDLYTG2_R4_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400984 */
12859 __IO uint16_t TXDQDLYTG3_R4_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400986 */
12860 uint8_t RESERVED_112[504];
12861 __IO uint16_t TXDQDLYTG0_R5_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400B80 */
12862 __IO uint16_t TXDQDLYTG1_R5_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400B82 */
12863 __IO uint16_t TXDQDLYTG2_R5_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400B84 */
12864 __IO uint16_t TXDQDLYTG3_R5_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400B86 */
12865 uint8_t RESERVED_113[504];
12866 __IO uint16_t TXDQDLYTG0_R6_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400D80 */
12867 __IO uint16_t TXDQDLYTG1_R6_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400D82 */
12868 __IO uint16_t TXDQDLYTG2_R6_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400D84 */
12869 __IO uint16_t TXDQDLYTG3_R6_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400D86 */
12870 uint8_t RESERVED_114[504];
12871 __IO uint16_t TXDQDLYTG0_R7_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x400F80 */
12872 __IO uint16_t TXDQDLYTG1_R7_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x400F82 */
12873 __IO uint16_t TXDQDLYTG2_R7_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x400F84 */
12874 __IO uint16_t TXDQDLYTG3_R7_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x400F86 */
12875 uint8_t RESERVED_115[504];
12876 __IO uint16_t TXDQDLYTG0_R8_P2; /**< Write DQ Delay (Timing Group 0)., offset: 0x401180 */
12877 __IO uint16_t TXDQDLYTG1_R8_P2; /**< Write DQ Delay (Timing Group 1)., offset: 0x401182 */
12878 __IO uint16_t TXDQDLYTG2_R8_P2; /**< Write DQ Delay (Timing Group 2)., offset: 0x401184 */
12879 __IO uint16_t TXDQDLYTG3_R8_P2; /**< Write DQ Delay (Timing Group 3)., offset: 0x401186 */
12880 uint8_t RESERVED_116[2092728];
12881 __IO uint16_t DFIMRL_P3; /**< DFI MaxReadLatency, offset: 0x600040 */
12882 uint8_t RESERVED_117[64];
12883 __IO uint16_t TXIMPEDANCECTRL0_B0_P3; /**< Data TX impedance controls, offset: 0x600082 */
12884 uint8_t RESERVED_118[2];
12885 __IO uint16_t DQDQSRCVCNTRL_B0_P3; /**< Dq/Dqs receiver control, offset: 0x600086 */
12886 uint8_t RESERVED_119[8];
12887 __IO uint16_t TXEQUALIZATIONMODE_P3; /**< Tx dq driver equalization mode controls., offset: 0x600090 */
12888 __IO uint16_t TXIMPEDANCECTRL1_B0_P3; /**< TX impedance controls, offset: 0x600092 */
12889 uint8_t RESERVED_120[2];
12890 __IO uint16_t TXIMPEDANCECTRL2_B0_P3; /**< TX equalization impedance controls, offset: 0x600096 */
12891 __IO uint16_t DQDQSRCVCNTRL2_P3; /**< Dq/Dqs receiver control, offset: 0x600098 */
12892 __IO uint16_t TXODTDRVSTREN_B0_P3; /**< TX ODT driver strength control, offset: 0x60009A */
12893 uint8_t RESERVED_121[34];
12894 __IO uint16_t TXSLEWRATE_B0_P3; /**< TX slew rate controls, offset: 0x6000BE */
12895 uint8_t RESERVED_122[64];
12896 __IO uint16_t RXENDLYTG0_U0_P3; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x600100 */
12897 __IO uint16_t RXENDLYTG1_U0_P3; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x600102 */
12898 __IO uint16_t RXENDLYTG2_U0_P3; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x600104 */
12899 __IO uint16_t RXENDLYTG3_U0_P3; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x600106 */
12900 uint8_t RESERVED_123[16];
12901 __IO uint16_t RXCLKDLYTG0_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x600118 */
12902 __IO uint16_t RXCLKDLYTG1_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x60011A */
12903 __IO uint16_t RXCLKDLYTG2_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x60011C */
12904 __IO uint16_t RXCLKDLYTG3_U0_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x60011E */
12905 __IO uint16_t
12906 RXCLKCDLYTG0_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x600120 */
12907 __IO uint16_t
12908 RXCLKCDLYTG1_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x600122 */
12909 __IO uint16_t
12910 RXCLKCDLYTG2_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x600124 */
12911 uint8_t RESERVED_124[2];
12912 __IO uint16_t
12913 RXCLKCDLYTG3_U0_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x600128 */
12914 uint8_t RESERVED_125[50];
12915 __IO uint16_t PPTDQSCNTINVTRNTG0_P3; /**< DQS Oscillator Count inverse at time of training in LPDDR4 drift
12916 compensation, offset: 0x60015C */
12917 __IO uint16_t PPTDQSCNTINVTRNTG1_P3; /**< DQS Oscillator Count inverse at time of training in LPDDR4 drift
12918 compensation, offset: 0x60015E */
12919 uint8_t RESERVED_126[32];
12920 __IO uint16_t TXDQDLYTG0_R0_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600180 */
12921 __IO uint16_t TXDQDLYTG1_R0_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600182 */
12922 __IO uint16_t TXDQDLYTG2_R0_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600184 */
12923 __IO uint16_t TXDQDLYTG3_R0_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600186 */
12924 uint8_t RESERVED_127[24];
12925 __IO uint16_t TXDQSDLYTG0_U0_P3; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x6001A0 */
12926 __IO uint16_t TXDQSDLYTG1_U0_P3; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x6001A2 */
12927 __IO uint16_t TXDQSDLYTG2_U0_P3; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x6001A4 */
12928 __IO uint16_t TXDQSDLYTG3_U0_P3; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x6001A6 */
12929 uint8_t RESERVED_128[218];
12930 __IO uint16_t TXIMPEDANCECTRL0_B1_P3; /**< Data TX impedance controls, offset: 0x600282 */
12931 uint8_t RESERVED_129[2];
12932 __IO uint16_t DQDQSRCVCNTRL_B1_P3; /**< Dq/Dqs receiver control, offset: 0x600286 */
12933 uint8_t RESERVED_130[10];
12934 __IO uint16_t TXIMPEDANCECTRL1_B1_P3; /**< TX impedance controls, offset: 0x600292 */
12935 uint8_t RESERVED_131[2];
12936 __IO uint16_t TXIMPEDANCECTRL2_B1_P3; /**< TX equalization impedance controls, offset: 0x600296 */
12937 uint8_t RESERVED_132[2];
12938 __IO uint16_t TXODTDRVSTREN_B1_P3; /**< TX ODT driver strength control, offset: 0x60029A */
12939 uint8_t RESERVED_133[34];
12940 __IO uint16_t TXSLEWRATE_B1_P3; /**< TX slew rate controls, offset: 0x6002BE */
12941 uint8_t RESERVED_134[64];
12942 __IO uint16_t RXENDLYTG0_U1_P3; /**< Trained Receive Enable Delay (For Timing Group 0), offset: 0x600300 */
12943 __IO uint16_t RXENDLYTG1_U1_P3; /**< Trained Receive Enable Delay (For Timing Group 1), offset: 0x600302 */
12944 __IO uint16_t RXENDLYTG2_U1_P3; /**< Trained Receive Enable Delay (For Timing Group 2), offset: 0x600304 */
12945 __IO uint16_t RXENDLYTG3_U1_P3; /**< Trained Receive Enable Delay (For Timing Group 3), offset: 0x600306 */
12946 uint8_t RESERVED_135[16];
12947 __IO uint16_t RXCLKDLYTG0_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=0)., offset: 0x600318 */
12948 __IO uint16_t RXCLKDLYTG1_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=1)., offset: 0x60031A */
12949 __IO uint16_t RXCLKDLYTG2_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=2)., offset: 0x60031C */
12950 __IO uint16_t RXCLKDLYTG3_U1_P3; /**< Trained Read DQS to RxClk Delay (Timing Group DEST=3)., offset: 0x60031E */
12951 __IO uint16_t
12952 RXCLKCDLYTG0_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x600320 */
12953 __IO uint16_t
12954 RXCLKCDLYTG1_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0)., offset: 0x600322 */
12955 __IO uint16_t
12956 RXCLKCDLYTG2_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2)., offset: 0x600324 */
12957 uint8_t RESERVED_136[2];
12958 __IO uint16_t
12959 RXCLKCDLYTG3_U1_P3; /**< Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3)., offset: 0x600328 */
12960 uint8_t RESERVED_137[86];
12961 __IO uint16_t TXDQDLYTG0_R1_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600380 */
12962 __IO uint16_t TXDQDLYTG1_R1_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600382 */
12963 __IO uint16_t TXDQDLYTG2_R1_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600384 */
12964 __IO uint16_t TXDQDLYTG3_R1_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600386 */
12965 uint8_t RESERVED_138[24];
12966 __IO uint16_t TXDQSDLYTG0_U1_P3; /**< Write DQS Delay (Timing Group DEST=0)., offset: 0x6003A0 */
12967 __IO uint16_t TXDQSDLYTG1_U1_P3; /**< Write DQS Delay (Timing Group DEST=1)., offset: 0x6003A2 */
12968 __IO uint16_t TXDQSDLYTG2_U1_P3; /**< Write DQS Delay (Timing Group DEST=2)., offset: 0x6003A4 */
12969 __IO uint16_t TXDQSDLYTG3_U1_P3; /**< Write DQS Delay (Timing Group DEST=3)., offset: 0x6003A6 */
12970 uint8_t RESERVED_139[472];
12971 __IO uint16_t TXDQDLYTG0_R2_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600580 */
12972 __IO uint16_t TXDQDLYTG1_R2_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600582 */
12973 __IO uint16_t TXDQDLYTG2_R2_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600584 */
12974 __IO uint16_t TXDQDLYTG3_R2_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600586 */
12975 uint8_t RESERVED_140[504];
12976 __IO uint16_t TXDQDLYTG0_R3_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600780 */
12977 __IO uint16_t TXDQDLYTG1_R3_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600782 */
12978 __IO uint16_t TXDQDLYTG2_R3_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600784 */
12979 __IO uint16_t TXDQDLYTG3_R3_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600786 */
12980 uint8_t RESERVED_141[504];
12981 __IO uint16_t TXDQDLYTG0_R4_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600980 */
12982 __IO uint16_t TXDQDLYTG1_R4_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600982 */
12983 __IO uint16_t TXDQDLYTG2_R4_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600984 */
12984 __IO uint16_t TXDQDLYTG3_R4_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600986 */
12985 uint8_t RESERVED_142[504];
12986 __IO uint16_t TXDQDLYTG0_R5_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600B80 */
12987 __IO uint16_t TXDQDLYTG1_R5_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600B82 */
12988 __IO uint16_t TXDQDLYTG2_R5_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600B84 */
12989 __IO uint16_t TXDQDLYTG3_R5_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600B86 */
12990 uint8_t RESERVED_143[504];
12991 __IO uint16_t TXDQDLYTG0_R6_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600D80 */
12992 __IO uint16_t TXDQDLYTG1_R6_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600D82 */
12993 __IO uint16_t TXDQDLYTG2_R6_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600D84 */
12994 __IO uint16_t TXDQDLYTG3_R6_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600D86 */
12995 uint8_t RESERVED_144[504];
12996 __IO uint16_t TXDQDLYTG0_R7_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x600F80 */
12997 __IO uint16_t TXDQDLYTG1_R7_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x600F82 */
12998 __IO uint16_t TXDQDLYTG2_R7_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x600F84 */
12999 __IO uint16_t TXDQDLYTG3_R7_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x600F86 */
13000 uint8_t RESERVED_145[504];
13001 __IO uint16_t TXDQDLYTG0_R8_P3; /**< Write DQ Delay (Timing Group 0)., offset: 0x601180 */
13002 __IO uint16_t TXDQDLYTG1_R8_P3; /**< Write DQ Delay (Timing Group 1)., offset: 0x601182 */
13003 __IO uint16_t TXDQDLYTG2_R8_P3; /**< Write DQ Delay (Timing Group 2)., offset: 0x601184 */
13004 __IO uint16_t TXDQDLYTG3_R8_P3; /**< Write DQ Delay (Timing Group 3)., offset: 0x601186 */
13005} DWC_DDRPHYA_DBYTE_Type;
13006
13007/* ----------------------------------------------------------------------------
13008 -- DWC_DDRPHYA_DBYTE Register Masks
13009 ---------------------------------------------------------------------------- */
13010
13011/*!
13012 * @addtogroup DWC_DDRPHYA_DBYTE_Register_Masks DWC_DDRPHYA_DBYTE Register Masks
13013 * @{
13014 */
13015
13016/*! @name DBYTEMISCMODE - DBYTE Module Disable */
13017/*! @{ */
13018#define DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DByteDisable_MASK (0x4U)
13019#define DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DByteDisable_SHIFT (2U)
13020#define DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DByteDisable(x) \
13021 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DByteDisable_SHIFT)) & \
13022 DWC_DDRPHYA_DBYTE_DBYTEMISCMODE_DByteDisable_MASK)
13023/*! @} */
13024
13025/*! @name MTESTMUXSEL - Digital Observation Pin control */
13026/*! @{ */
13027#define DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MtestMuxSel_MASK (0x3FU)
13028#define DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MtestMuxSel_SHIFT (0U)
13029#define DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MtestMuxSel(x) \
13030 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MtestMuxSel_SHIFT)) & \
13031 DWC_DDRPHYA_DBYTE_MTESTMUXSEL_MtestMuxSel_MASK)
13032/*! @} */
13033
13034/*! @name DFIMRL_P0 - DFI MaxReadLatency */
13035/*! @{ */
13036#define DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_p0_MASK (0x1FU)
13037#define DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_p0_SHIFT (0U)
13038#define DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_p0(x) \
13039 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_p0_SHIFT)) & \
13040 DWC_DDRPHYA_DBYTE_DFIMRL_P0_DFIMRL_p0_MASK)
13041/*! @} */
13042
13043/*! @name VREFDAC1_R0 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
13044/*! @{ */
13045#define DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VrefDAC1_rx_MASK (0x7FU)
13046#define DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VrefDAC1_rx_SHIFT (0U)
13047#define DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VrefDAC1_rx(x) \
13048 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VrefDAC1_rx_SHIFT)) & \
13049 DWC_DDRPHYA_DBYTE_VREFDAC1_R0_VrefDAC1_rx_MASK)
13050/*! @} */
13051
13052/*! @name VREFDAC0_R0 - VrefDAC0 control for DQ Receiver */
13053/*! @{ */
13054#define DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VrefDAC0_rx_MASK (0x7FU)
13055#define DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VrefDAC0_rx_SHIFT (0U)
13056#define DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VrefDAC0_rx(x) \
13057 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VrefDAC0_rx_SHIFT)) & \
13058 DWC_DDRPHYA_DBYTE_VREFDAC0_R0_VrefDAC0_rx_MASK)
13059/*! @} */
13060
13061/*! @name TXIMPEDANCECTRL0_B0_P0 - Data TX impedance controls */
13062/*! @{ */
13063#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqP_MASK (0x3FU)
13064#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqP_SHIFT (0U)
13065#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqP(x) \
13066 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqP_SHIFT)) & \
13067 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqP_MASK)
13068#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqN_MASK (0xFC0U)
13069#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqN_SHIFT (6U)
13070#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqN(x) \
13071 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqN_SHIFT)) & \
13072 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P0_DrvStrenDqN_MASK)
13073/*! @} */
13074
13075/*! @name DQDQSRCVCNTRL_B0_P0 - Dq/Dqs receiver control */
13076/*! @{ */
13077#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SelAnalogVref_MASK (0x1U)
13078#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SelAnalogVref_SHIFT (0U)
13079#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SelAnalogVref(x) \
13080 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SelAnalogVref_SHIFT)) & \
13081 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_SelAnalogVref_MASK)
13082#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_ExtVrefRange_MASK (0x2U)
13083#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_ExtVrefRange_SHIFT (1U)
13084#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_ExtVrefRange(x) \
13085 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_ExtVrefRange_SHIFT)) & \
13086 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_ExtVrefRange_MASK)
13087#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DfeCtrl_MASK (0xCU)
13088#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DfeCtrl_SHIFT (2U)
13089#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DfeCtrl(x) \
13090 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DfeCtrl_SHIFT)) & \
13091 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_DfeCtrl_MASK)
13092#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MajorModeDbyte_MASK (0x70U)
13093#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MajorModeDbyte_SHIFT (4U)
13094#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MajorModeDbyte(x) \
13095 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MajorModeDbyte_SHIFT)) & \
13096 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_MajorModeDbyte_MASK)
13097#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GainCurrAdj_MASK (0xF80U)
13098#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GainCurrAdj_SHIFT (7U)
13099#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GainCurrAdj(x) \
13100 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GainCurrAdj_SHIFT)) & \
13101 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P0_GainCurrAdj_MASK)
13102/*! @} */
13103
13104/*! @name TXEQUALIZATIONMODE_P0 - Tx dq driver equalization mode controls. */
13105/*! @{ */
13106#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TxEqMode_MASK (0x3U)
13107#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TxEqMode_SHIFT (0U)
13108#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TxEqMode(x) \
13109 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TxEqMode_SHIFT)) & \
13110 DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P0_TxEqMode_MASK)
13111/*! @} */
13112
13113/*! @name TXIMPEDANCECTRL1_B0_P0 - TX impedance controls */
13114/*! @{ */
13115#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqP_MASK (0x3FU)
13116#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqP_SHIFT (0U)
13117#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqP(x) \
13118 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqP_SHIFT)) & \
13119 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqP_MASK)
13120#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqN_MASK (0xFC0U)
13121#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqN_SHIFT (6U)
13122#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqN(x) \
13123 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqN_SHIFT)) & \
13124 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P0_DrvStrenFSDqN_MASK)
13125/*! @} */
13126
13127/*! @name DQDQSRCVCNTRL1 - Dq/Dqs receiver control */
13128/*! @{ */
13129#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvr_MASK (0x1FFU)
13130#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvr_SHIFT (0U)
13131#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvr(x) \
13132 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvr_SHIFT)) & \
13133 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvr_MASK)
13134#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvrDqs_MASK (0x200U)
13135#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvrDqs_SHIFT (9U)
13136#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvrDqs(x) \
13137 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvrDqs_SHIFT)) & \
13138 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_PowerDownRcvrDqs_MASK)
13139#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RxPadStandbyEn_MASK (0x400U)
13140#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RxPadStandbyEn_SHIFT (10U)
13141#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RxPadStandbyEn(x) \
13142 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RxPadStandbyEn_SHIFT)) & \
13143 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_RxPadStandbyEn_MASK)
13144#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_EnLPReqPDR_MASK (0x800U)
13145#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_EnLPReqPDR_SHIFT (11U)
13146#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_EnLPReqPDR(x) \
13147 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_EnLPReqPDR_SHIFT)) & \
13148 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL1_EnLPReqPDR_MASK)
13149/*! @} */
13150
13151/*! @name TXIMPEDANCECTRL2_B0_P0 - TX equalization impedance controls */
13152/*! @{ */
13153#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQHiDqP_MASK (0x3FU)
13154#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQHiDqP_SHIFT (0U)
13155#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQHiDqP(x) \
13156 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQHiDqP_SHIFT)) & \
13157 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQHiDqP_MASK)
13158#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQLoDqN_MASK (0xFC0U)
13159#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQLoDqN_SHIFT (6U)
13160#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQLoDqN(x) \
13161 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQLoDqN_SHIFT)) & \
13162 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P0_DrvStrenEQLoDqN_MASK)
13163/*! @} */
13164
13165/*! @name DQDQSRCVCNTRL2_P0 - Dq/Dqs receiver control */
13166/*! @{ */
13167#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_EnRxAgressivePDR_MASK (0x1U)
13168#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_EnRxAgressivePDR_SHIFT (0U)
13169#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_EnRxAgressivePDR(x) \
13170 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_EnRxAgressivePDR_SHIFT)) & \
13171 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P0_EnRxAgressivePDR_MASK)
13172/*! @} */
13173
13174/*! @name TXODTDRVSTREN_B0_P0 - TX ODT driver strength control */
13175/*! @{ */
13176#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenP_MASK (0x3FU)
13177#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenP_SHIFT (0U)
13178#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenP(x) \
13179 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenP_SHIFT)) & \
13180 DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenP_MASK)
13181#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenN_MASK (0xFC0U)
13182#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenN_SHIFT (6U)
13183#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenN(x) \
13184 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenN_SHIFT)) & \
13185 DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P0_ODTStrenN_MASK)
13186/*! @} */
13187
13188/*! @name RXFIFOCHECKSTATUS - Status of RX FIFO Consistency Checks */
13189/*! @{ */
13190#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocErr_MASK (0x1U)
13191#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocErr_SHIFT (0U)
13192#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocErr(x) \
13193 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocErr_SHIFT)) & \
13194 DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocErr_MASK)
13195#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocErr_MASK (0x2U)
13196#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocErr_SHIFT (1U)
13197#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocErr(x) \
13198 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocErr_SHIFT)) & \
13199 DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocErr_MASK)
13200#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocUErr_MASK (0x4U)
13201#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocUErr_SHIFT (2U)
13202#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocUErr(x) \
13203 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocUErr_SHIFT)) & \
13204 DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoRdLocUErr_MASK)
13205#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocUErr_MASK (0x8U)
13206#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocUErr_SHIFT (3U)
13207#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocUErr(x) \
13208 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocUErr_SHIFT)) & \
13209 DWC_DDRPHYA_DBYTE_RXFIFOCHECKSTATUS_RxFifoWrLocUErr_MASK)
13210/*! @} */
13211
13212/*! @name RXFIFOCHECKERRVALUES - Contains the captured values associated with an RxFifo consistency error */
13213/*! @{ */
13214#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocErrValue_MASK (0xFU)
13215#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocErrValue_SHIFT (0U)
13216#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocErrValue(x) \
13217 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocErrValue_SHIFT)) & \
13218 DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocErrValue_MASK)
13219#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocErrValue_MASK (0xF0U)
13220#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocErrValue_SHIFT (4U)
13221#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocErrValue(x) \
13222 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocErrValue_SHIFT)) & \
13223 DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocErrValue_MASK)
13224#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocUErrValue_MASK (0xF00U)
13225#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocUErrValue_SHIFT (8U)
13226#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocUErrValue(x) \
13227 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocUErrValue_SHIFT)) & \
13228 DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoRdLocUErrValue_MASK)
13229#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocUErrValue_MASK (0xF000U)
13230#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocUErrValue_SHIFT (12U)
13231#define DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocUErrValue(x) \
13232 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocUErrValue_SHIFT)) & \
13233 DWC_DDRPHYA_DBYTE_RXFIFOCHECKERRVALUES_RxFifoWrLocUErrValue_MASK)
13234/*! @} */
13235
13236/*! @name RXFIFOINFO - Data Receive FIFO Pointer Values */
13237/*! @{ */
13238#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLoc_MASK (0xFU)
13239#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLoc_SHIFT (0U)
13240#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLoc(x) \
13241 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLoc_SHIFT)) & \
13242 DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLoc_MASK)
13243#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLoc_MASK (0xF0U)
13244#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLoc_SHIFT (4U)
13245#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLoc(x) \
13246 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLoc_SHIFT)) & \
13247 DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLoc_MASK)
13248#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLocU_MASK (0xF00U)
13249#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLocU_SHIFT (8U)
13250#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLocU(x) \
13251 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLocU_SHIFT)) & \
13252 DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoRdLocU_MASK)
13253#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLocU_MASK (0xF000U)
13254#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLocU_SHIFT (12U)
13255#define DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLocU(x) \
13256 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLocU_SHIFT)) & \
13257 DWC_DDRPHYA_DBYTE_RXFIFOINFO_RxFifoWrLocU_MASK)
13258/*! @} */
13259
13260/*! @name RXFIFOVISIBILITY - RX FIFO visibility */
13261/*! @{ */
13262#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtr_MASK (0x7U)
13263#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtr_SHIFT (0U)
13264#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtr(x) \
13265 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtr_SHIFT)) & \
13266 DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtr_MASK)
13267#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtrOvr_MASK (0x8U)
13268#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtrOvr_SHIFT (3U)
13269#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtrOvr(x) \
13270 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtrOvr_SHIFT)) & \
13271 DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdPtrOvr_MASK)
13272#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdEn_MASK (0x10U)
13273#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdEn_SHIFT (4U)
13274#define DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdEn(x) \
13275 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdEn_SHIFT)) & \
13276 DWC_DDRPHYA_DBYTE_RXFIFOVISIBILITY_RxFifoRdEn_MASK)
13277/*! @} */
13278
13279/*! @name RXFIFOCONTENTSDQ3210 - RX FIFO contents, lane[3:0] */
13280/*! @{ */
13281#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RxFifoContentsDQ3210_MASK (0xFFFFU)
13282#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RxFifoContentsDQ3210_SHIFT (0U)
13283#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RxFifoContentsDQ3210(x) \
13284 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RxFifoContentsDQ3210_SHIFT)) & \
13285 DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ3210_RxFifoContentsDQ3210_MASK)
13286/*! @} */
13287
13288/*! @name RXFIFOCONTENTSDQ7654 - RX FIFO contents, lane[7:4] */
13289/*! @{ */
13290#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RxFifoContentsDQ7654_MASK (0xFFFFU)
13291#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RxFifoContentsDQ7654_SHIFT (0U)
13292#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RxFifoContentsDQ7654(x) \
13293 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RxFifoContentsDQ7654_SHIFT)) & \
13294 DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDQ7654_RxFifoContentsDQ7654_MASK)
13295/*! @} */
13296
13297/*! @name RXFIFOCONTENTSDBI - RX FIFO contents, dbi */
13298/*! @{ */
13299#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RxFifoContentsDBI_MASK (0xFU)
13300#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RxFifoContentsDBI_SHIFT (0U)
13301#define DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RxFifoContentsDBI(x) \
13302 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RxFifoContentsDBI_SHIFT)) & \
13303 DWC_DDRPHYA_DBYTE_RXFIFOCONTENTSDBI_RxFifoContentsDBI_MASK)
13304/*! @} */
13305
13306/*! @name TXSLEWRATE_B0_P0 - TX slew rate controls */
13307/*! @{ */
13308#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreP_MASK (0xFU)
13309#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreP_SHIFT (0U)
13310#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreP(x) \
13311 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreP_SHIFT)) & \
13312 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreP_MASK)
13313#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreN_MASK (0xF0U)
13314#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreN_SHIFT (4U)
13315#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreN(x) \
13316 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreN_SHIFT)) & \
13317 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreN_MASK)
13318#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreDrvMode_MASK (0x700U)
13319#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreDrvMode_SHIFT (8U)
13320#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreDrvMode(x) \
13321 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreDrvMode_SHIFT)) & \
13322 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P0_TxPreDrvMode_MASK)
13323/*! @} */
13324
13325/*! @name RXPBDLYTG0_R0 - Read DQ per-bit BDL delay (Timing Group 0). */
13326/*! @{ */
13327#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RxPBDlyTg0_rx_MASK (0x7FU)
13328#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RxPBDlyTg0_rx_SHIFT (0U)
13329#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RxPBDlyTg0_rx(x) \
13330 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RxPBDlyTg0_rx_SHIFT)) & \
13331 DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R0_RxPBDlyTg0_rx_MASK)
13332/*! @} */
13333
13334/*! @name RXPBDLYTG1_R0 - Read DQ per-bit BDL delay (Timing Group 1). */
13335/*! @{ */
13336#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RxPBDlyTg1_rx_MASK (0x7FU)
13337#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RxPBDlyTg1_rx_SHIFT (0U)
13338#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RxPBDlyTg1_rx(x) \
13339 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RxPBDlyTg1_rx_SHIFT)) & \
13340 DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R0_RxPBDlyTg1_rx_MASK)
13341/*! @} */
13342
13343/*! @name RXPBDLYTG2_R0 - Read DQ per-bit BDL delay (Timing Group 2). */
13344/*! @{ */
13345#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RxPBDlyTg2_rx_MASK (0x7FU)
13346#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RxPBDlyTg2_rx_SHIFT (0U)
13347#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RxPBDlyTg2_rx(x) \
13348 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RxPBDlyTg2_rx_SHIFT)) & \
13349 DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R0_RxPBDlyTg2_rx_MASK)
13350/*! @} */
13351
13352/*! @name RXPBDLYTG3_R0 - Read DQ per-bit BDL delay (Timing Group 3). */
13353/*! @{ */
13354#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RxPBDlyTg3_rx_MASK (0x7FU)
13355#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RxPBDlyTg3_rx_SHIFT (0U)
13356#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RxPBDlyTg3_rx(x) \
13357 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RxPBDlyTg3_rx_SHIFT)) & \
13358 DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R0_RxPBDlyTg3_rx_MASK)
13359/*! @} */
13360
13361/*! @name RXENDLYTG0_U0_P0 - Trained Receive Enable Delay (For Timing Group 0) */
13362/*! @{ */
13363#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RxEnDlyTg0_un_px_MASK (0x7FFU)
13364#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RxEnDlyTg0_un_px_SHIFT (0U)
13365#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RxEnDlyTg0_un_px(x) \
13366 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RxEnDlyTg0_un_px_SHIFT)) & \
13367 DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P0_RxEnDlyTg0_un_px_MASK)
13368/*! @} */
13369
13370/*! @name RXENDLYTG1_U0_P0 - Trained Receive Enable Delay (For Timing Group 1) */
13371/*! @{ */
13372#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RxEnDlyTg1_un_px_MASK (0x7FFU)
13373#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RxEnDlyTg1_un_px_SHIFT (0U)
13374#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RxEnDlyTg1_un_px(x) \
13375 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RxEnDlyTg1_un_px_SHIFT)) & \
13376 DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P0_RxEnDlyTg1_un_px_MASK)
13377/*! @} */
13378
13379/*! @name RXENDLYTG2_U0_P0 - Trained Receive Enable Delay (For Timing Group 2) */
13380/*! @{ */
13381#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RxEnDlyTg2_un_px_MASK (0x7FFU)
13382#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RxEnDlyTg2_un_px_SHIFT (0U)
13383#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RxEnDlyTg2_un_px(x) \
13384 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RxEnDlyTg2_un_px_SHIFT)) & \
13385 DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P0_RxEnDlyTg2_un_px_MASK)
13386/*! @} */
13387
13388/*! @name RXENDLYTG3_U0_P0 - Trained Receive Enable Delay (For Timing Group 3) */
13389/*! @{ */
13390#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RxEnDlyTg3_un_px_MASK (0x7FFU)
13391#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RxEnDlyTg3_un_px_SHIFT (0U)
13392#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RxEnDlyTg3_un_px(x) \
13393 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RxEnDlyTg3_un_px_SHIFT)) & \
13394 DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P0_RxEnDlyTg3_un_px_MASK)
13395/*! @} */
13396
13397/*! @name RXCLKDLYTG0_U0_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
13398/*! @{ */
13399#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RxClkDlyTg0_un_px_MASK (0x3FU)
13400#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RxClkDlyTg0_un_px_SHIFT (0U)
13401#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RxClkDlyTg0_un_px(x) \
13402 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RxClkDlyTg0_un_px_SHIFT)) & \
13403 DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P0_RxClkDlyTg0_un_px_MASK)
13404/*! @} */
13405
13406/*! @name RXCLKDLYTG1_U0_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
13407/*! @{ */
13408#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RxClkDlyTg1_un_px_MASK (0x3FU)
13409#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RxClkDlyTg1_un_px_SHIFT (0U)
13410#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RxClkDlyTg1_un_px(x) \
13411 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RxClkDlyTg1_un_px_SHIFT)) & \
13412 DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P0_RxClkDlyTg1_un_px_MASK)
13413/*! @} */
13414
13415/*! @name RXCLKDLYTG2_U0_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
13416/*! @{ */
13417#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RxClkDlyTg2_un_px_MASK (0x3FU)
13418#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RxClkDlyTg2_un_px_SHIFT (0U)
13419#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RxClkDlyTg2_un_px(x) \
13420 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RxClkDlyTg2_un_px_SHIFT)) & \
13421 DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P0_RxClkDlyTg2_un_px_MASK)
13422/*! @} */
13423
13424/*! @name RXCLKDLYTG3_U0_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
13425/*! @{ */
13426#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RxClkDlyTg3_un_px_MASK (0x3FU)
13427#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RxClkDlyTg3_un_px_SHIFT (0U)
13428#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RxClkDlyTg3_un_px(x) \
13429 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RxClkDlyTg3_un_px_SHIFT)) & \
13430 DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P0_RxClkDlyTg3_un_px_MASK)
13431/*! @} */
13432
13433/*! @name RXCLKCDLYTG0_U0_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
13434/*! @{ */
13435#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RxClkcDlyTg0_un_px_MASK (0x3FU)
13436#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RxClkcDlyTg0_un_px_SHIFT (0U)
13437#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RxClkcDlyTg0_un_px(x) \
13438 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RxClkcDlyTg0_un_px_SHIFT)) & \
13439 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P0_RxClkcDlyTg0_un_px_MASK)
13440/*! @} */
13441
13442/*! @name RXCLKCDLYTG1_U0_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
13443/*! @{ */
13444#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RxClkcDlyTg1_un_px_MASK (0x3FU)
13445#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RxClkcDlyTg1_un_px_SHIFT (0U)
13446#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RxClkcDlyTg1_un_px(x) \
13447 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RxClkcDlyTg1_un_px_SHIFT)) & \
13448 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P0_RxClkcDlyTg1_un_px_MASK)
13449/*! @} */
13450
13451/*! @name RXCLKCDLYTG2_U0_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
13452/*! @{ */
13453#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RxClkcDlyTg2_un_px_MASK (0x3FU)
13454#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RxClkcDlyTg2_un_px_SHIFT (0U)
13455#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RxClkcDlyTg2_un_px(x) \
13456 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RxClkcDlyTg2_un_px_SHIFT)) & \
13457 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P0_RxClkcDlyTg2_un_px_MASK)
13458/*! @} */
13459
13460/*! @name RXCLKCDLYTG3_U0_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
13461/*! @{ */
13462#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RxClkcDlyTg3_un_px_MASK (0x3FU)
13463#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RxClkcDlyTg3_un_px_SHIFT (0U)
13464#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RxClkcDlyTg3_un_px(x) \
13465 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RxClkcDlyTg3_un_px_SHIFT)) & \
13466 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P0_RxClkcDlyTg3_un_px_MASK)
13467/*! @} */
13468
13469/*! @name DQLNSEL - Maps Phy DQ lane to memory DQ0 */
13470/*! @{ */
13471#define DWC_DDRPHYA_DBYTE_DQLNSEL_DqLnSel_MASK (0x7U)
13472#define DWC_DDRPHYA_DBYTE_DQLNSEL_DqLnSel_SHIFT (0U)
13473#define DWC_DDRPHYA_DBYTE_DQLNSEL_DqLnSel(x) \
13474 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQLNSEL_DqLnSel_SHIFT)) & DWC_DDRPHYA_DBYTE_DQLNSEL_DqLnSel_MASK)
13475/*! @} */
13476
13477/* The count of DWC_DDRPHYA_DBYTE_DQLNSEL */
13478#define DWC_DDRPHYA_DBYTE_DQLNSEL_COUNT (8U)
13479
13480/*! @name TXDQDLYTG0_R0_P0 - Write DQ Delay (Timing Group 0). */
13481/*! @{ */
13482#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU)
13483#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TxDqDlyTg0_rn_px_SHIFT (0U)
13484#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TxDqDlyTg0_rn_px(x) \
13485 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TxDqDlyTg0_rn_px_SHIFT)) & \
13486 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P0_TxDqDlyTg0_rn_px_MASK)
13487/*! @} */
13488
13489/*! @name TXDQDLYTG1_R0_P0 - Write DQ Delay (Timing Group 1). */
13490/*! @{ */
13491#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU)
13492#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TxDqDlyTg1_rn_px_SHIFT (0U)
13493#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TxDqDlyTg1_rn_px(x) \
13494 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TxDqDlyTg1_rn_px_SHIFT)) & \
13495 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P0_TxDqDlyTg1_rn_px_MASK)
13496/*! @} */
13497
13498/*! @name TXDQDLYTG2_R0_P0 - Write DQ Delay (Timing Group 2). */
13499/*! @{ */
13500#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU)
13501#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TxDqDlyTg2_rn_px_SHIFT (0U)
13502#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TxDqDlyTg2_rn_px(x) \
13503 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TxDqDlyTg2_rn_px_SHIFT)) & \
13504 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P0_TxDqDlyTg2_rn_px_MASK)
13505/*! @} */
13506
13507/*! @name TXDQDLYTG3_R0_P0 - Write DQ Delay (Timing Group 3). */
13508/*! @{ */
13509#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU)
13510#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TxDqDlyTg3_rn_px_SHIFT (0U)
13511#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TxDqDlyTg3_rn_px(x) \
13512 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TxDqDlyTg3_rn_px_SHIFT)) & \
13513 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P0_TxDqDlyTg3_rn_px_MASK)
13514/*! @} */
13515
13516/*! @name TXDQSDLYTG0_U0_P0 - Write DQS Delay (Timing Group DEST=0). */
13517/*! @{ */
13518#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TxDqsDlyTg0_un_px_MASK (0x3FFU)
13519#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TxDqsDlyTg0_un_px_SHIFT (0U)
13520#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TxDqsDlyTg0_un_px(x) \
13521 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TxDqsDlyTg0_un_px_SHIFT)) & \
13522 DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P0_TxDqsDlyTg0_un_px_MASK)
13523/*! @} */
13524
13525/*! @name TXDQSDLYTG1_U0_P0 - Write DQS Delay (Timing Group DEST=1). */
13526/*! @{ */
13527#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TxDqsDlyTg1_un_px_MASK (0x3FFU)
13528#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TxDqsDlyTg1_un_px_SHIFT (0U)
13529#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TxDqsDlyTg1_un_px(x) \
13530 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TxDqsDlyTg1_un_px_SHIFT)) & \
13531 DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P0_TxDqsDlyTg1_un_px_MASK)
13532/*! @} */
13533
13534/*! @name TXDQSDLYTG2_U0_P0 - Write DQS Delay (Timing Group DEST=2). */
13535/*! @{ */
13536#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TxDqsDlyTg2_un_px_MASK (0x3FFU)
13537#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TxDqsDlyTg2_un_px_SHIFT (0U)
13538#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TxDqsDlyTg2_un_px(x) \
13539 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TxDqsDlyTg2_un_px_SHIFT)) & \
13540 DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P0_TxDqsDlyTg2_un_px_MASK)
13541/*! @} */
13542
13543/*! @name TXDQSDLYTG3_U0_P0 - Write DQS Delay (Timing Group DEST=3). */
13544/*! @{ */
13545#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TxDqsDlyTg3_un_px_MASK (0x3FFU)
13546#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TxDqsDlyTg3_un_px_SHIFT (0U)
13547#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TxDqsDlyTg3_un_px(x) \
13548 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TxDqsDlyTg3_un_px_SHIFT)) & \
13549 DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P0_TxDqsDlyTg3_un_px_MASK)
13550/*! @} */
13551
13552/*! @name DXLCDLSTATUS - Debug status of the DBYTE LCDL */
13553/*! @{ */
13554#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlFineSnapVal_MASK (0x3FFU)
13555#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlFineSnapVal_SHIFT (0U)
13556#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlFineSnapVal(x) \
13557 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlFineSnapVal_SHIFT)) & \
13558 DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlFineSnapVal_MASK)
13559#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlPhdSnapVal_MASK (0x400U)
13560#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlPhdSnapVal_SHIFT (10U)
13561#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlPhdSnapVal(x) \
13562 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlPhdSnapVal_SHIFT)) & \
13563 DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlPhdSnapVal_MASK)
13564#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyLock_MASK (0x800U)
13565#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyLock_SHIFT (11U)
13566#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyLock(x) \
13567 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyLock_SHIFT)) & \
13568 DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyLock_MASK)
13569#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyUnlock_MASK (0x1000U)
13570#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyUnlock_SHIFT (12U)
13571#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyUnlock(x) \
13572 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyUnlock_SHIFT)) & \
13573 DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlStickyUnlock_MASK)
13574#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlLiveLock_MASK (0x2000U)
13575#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlLiveLock_SHIFT (13U)
13576#define DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlLiveLock(x) \
13577 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlLiveLock_SHIFT)) & \
13578 DWC_DDRPHYA_DBYTE_DXLCDLSTATUS_DxLcdlLiveLock_MASK)
13579/*! @} */
13580
13581/*! @name VREFDAC1_R1 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
13582/*! @{ */
13583#define DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VrefDAC1_rx_MASK (0x7FU)
13584#define DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VrefDAC1_rx_SHIFT (0U)
13585#define DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VrefDAC1_rx(x) \
13586 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VrefDAC1_rx_SHIFT)) & \
13587 DWC_DDRPHYA_DBYTE_VREFDAC1_R1_VrefDAC1_rx_MASK)
13588/*! @} */
13589
13590/*! @name VREFDAC0_R1 - VrefDAC0 control for DQ Receiver */
13591/*! @{ */
13592#define DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VrefDAC0_rx_MASK (0x7FU)
13593#define DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VrefDAC0_rx_SHIFT (0U)
13594#define DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VrefDAC0_rx(x) \
13595 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VrefDAC0_rx_SHIFT)) & \
13596 DWC_DDRPHYA_DBYTE_VREFDAC0_R1_VrefDAC0_rx_MASK)
13597/*! @} */
13598
13599/*! @name TXIMPEDANCECTRL0_B1_P0 - Data TX impedance controls */
13600/*! @{ */
13601#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqP_MASK (0x3FU)
13602#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqP_SHIFT (0U)
13603#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqP(x) \
13604 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqP_SHIFT)) & \
13605 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqP_MASK)
13606#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqN_MASK (0xFC0U)
13607#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqN_SHIFT (6U)
13608#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqN(x) \
13609 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqN_SHIFT)) & \
13610 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P0_DrvStrenDqN_MASK)
13611/*! @} */
13612
13613/*! @name DQDQSRCVCNTRL_B1_P0 - Dq/Dqs receiver control */
13614/*! @{ */
13615#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SelAnalogVref_MASK (0x1U)
13616#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SelAnalogVref_SHIFT (0U)
13617#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SelAnalogVref(x) \
13618 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SelAnalogVref_SHIFT)) & \
13619 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_SelAnalogVref_MASK)
13620#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_ExtVrefRange_MASK (0x2U)
13621#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_ExtVrefRange_SHIFT (1U)
13622#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_ExtVrefRange(x) \
13623 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_ExtVrefRange_SHIFT)) & \
13624 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_ExtVrefRange_MASK)
13625#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DfeCtrl_MASK (0xCU)
13626#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DfeCtrl_SHIFT (2U)
13627#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DfeCtrl(x) \
13628 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DfeCtrl_SHIFT)) & \
13629 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_DfeCtrl_MASK)
13630#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MajorModeDbyte_MASK (0x70U)
13631#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MajorModeDbyte_SHIFT (4U)
13632#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MajorModeDbyte(x) \
13633 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MajorModeDbyte_SHIFT)) & \
13634 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_MajorModeDbyte_MASK)
13635#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GainCurrAdj_MASK (0xF80U)
13636#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GainCurrAdj_SHIFT (7U)
13637#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GainCurrAdj(x) \
13638 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GainCurrAdj_SHIFT)) & \
13639 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P0_GainCurrAdj_MASK)
13640/*! @} */
13641
13642/*! @name TXIMPEDANCECTRL1_B1_P0 - TX impedance controls */
13643/*! @{ */
13644#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqP_MASK (0x3FU)
13645#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqP_SHIFT (0U)
13646#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqP(x) \
13647 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqP_SHIFT)) & \
13648 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqP_MASK)
13649#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqN_MASK (0xFC0U)
13650#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqN_SHIFT (6U)
13651#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqN(x) \
13652 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqN_SHIFT)) & \
13653 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P0_DrvStrenFSDqN_MASK)
13654/*! @} */
13655
13656/*! @name TXIMPEDANCECTRL2_B1_P0 - TX equalization impedance controls */
13657/*! @{ */
13658#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQHiDqP_MASK (0x3FU)
13659#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQHiDqP_SHIFT (0U)
13660#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQHiDqP(x) \
13661 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQHiDqP_SHIFT)) & \
13662 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQHiDqP_MASK)
13663#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQLoDqN_MASK (0xFC0U)
13664#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQLoDqN_SHIFT (6U)
13665#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQLoDqN(x) \
13666 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQLoDqN_SHIFT)) & \
13667 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P0_DrvStrenEQLoDqN_MASK)
13668/*! @} */
13669
13670/*! @name TXODTDRVSTREN_B1_P0 - TX ODT driver strength control */
13671/*! @{ */
13672#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenP_MASK (0x3FU)
13673#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenP_SHIFT (0U)
13674#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenP(x) \
13675 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenP_SHIFT)) & \
13676 DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenP_MASK)
13677#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenN_MASK (0xFC0U)
13678#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenN_SHIFT (6U)
13679#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenN(x) \
13680 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenN_SHIFT)) & \
13681 DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P0_ODTStrenN_MASK)
13682/*! @} */
13683
13684/*! @name TXSLEWRATE_B1_P0 - TX slew rate controls */
13685/*! @{ */
13686#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreP_MASK (0xFU)
13687#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreP_SHIFT (0U)
13688#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreP(x) \
13689 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreP_SHIFT)) & \
13690 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreP_MASK)
13691#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreN_MASK (0xF0U)
13692#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreN_SHIFT (4U)
13693#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreN(x) \
13694 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreN_SHIFT)) & \
13695 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreN_MASK)
13696#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreDrvMode_MASK (0x700U)
13697#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreDrvMode_SHIFT (8U)
13698#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreDrvMode(x) \
13699 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreDrvMode_SHIFT)) & \
13700 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P0_TxPreDrvMode_MASK)
13701/*! @} */
13702
13703/*! @name RXPBDLYTG0_R1 - Read DQ per-bit BDL delay (Timing Group 0). */
13704/*! @{ */
13705#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RxPBDlyTg0_rx_MASK (0x7FU)
13706#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RxPBDlyTg0_rx_SHIFT (0U)
13707#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RxPBDlyTg0_rx(x) \
13708 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RxPBDlyTg0_rx_SHIFT)) & \
13709 DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R1_RxPBDlyTg0_rx_MASK)
13710/*! @} */
13711
13712/*! @name RXPBDLYTG1_R1 - Read DQ per-bit BDL delay (Timing Group 1). */
13713/*! @{ */
13714#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RxPBDlyTg1_rx_MASK (0x7FU)
13715#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RxPBDlyTg1_rx_SHIFT (0U)
13716#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RxPBDlyTg1_rx(x) \
13717 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RxPBDlyTg1_rx_SHIFT)) & \
13718 DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R1_RxPBDlyTg1_rx_MASK)
13719/*! @} */
13720
13721/*! @name RXPBDLYTG2_R1 - Read DQ per-bit BDL delay (Timing Group 2). */
13722/*! @{ */
13723#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RxPBDlyTg2_rx_MASK (0x7FU)
13724#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RxPBDlyTg2_rx_SHIFT (0U)
13725#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RxPBDlyTg2_rx(x) \
13726 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RxPBDlyTg2_rx_SHIFT)) & \
13727 DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R1_RxPBDlyTg2_rx_MASK)
13728/*! @} */
13729
13730/*! @name RXPBDLYTG3_R1 - Read DQ per-bit BDL delay (Timing Group 3). */
13731/*! @{ */
13732#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RxPBDlyTg3_rx_MASK (0x7FU)
13733#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RxPBDlyTg3_rx_SHIFT (0U)
13734#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RxPBDlyTg3_rx(x) \
13735 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RxPBDlyTg3_rx_SHIFT)) & \
13736 DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R1_RxPBDlyTg3_rx_MASK)
13737/*! @} */
13738
13739/*! @name RXENDLYTG0_U1_P0 - Trained Receive Enable Delay (For Timing Group 0) */
13740/*! @{ */
13741#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RxEnDlyTg0_un_px_MASK (0x7FFU)
13742#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RxEnDlyTg0_un_px_SHIFT (0U)
13743#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RxEnDlyTg0_un_px(x) \
13744 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RxEnDlyTg0_un_px_SHIFT)) & \
13745 DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P0_RxEnDlyTg0_un_px_MASK)
13746/*! @} */
13747
13748/*! @name RXENDLYTG1_U1_P0 - Trained Receive Enable Delay (For Timing Group 1) */
13749/*! @{ */
13750#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RxEnDlyTg1_un_px_MASK (0x7FFU)
13751#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RxEnDlyTg1_un_px_SHIFT (0U)
13752#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RxEnDlyTg1_un_px(x) \
13753 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RxEnDlyTg1_un_px_SHIFT)) & \
13754 DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P0_RxEnDlyTg1_un_px_MASK)
13755/*! @} */
13756
13757/*! @name RXENDLYTG2_U1_P0 - Trained Receive Enable Delay (For Timing Group 2) */
13758/*! @{ */
13759#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RxEnDlyTg2_un_px_MASK (0x7FFU)
13760#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RxEnDlyTg2_un_px_SHIFT (0U)
13761#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RxEnDlyTg2_un_px(x) \
13762 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RxEnDlyTg2_un_px_SHIFT)) & \
13763 DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P0_RxEnDlyTg2_un_px_MASK)
13764/*! @} */
13765
13766/*! @name RXENDLYTG3_U1_P0 - Trained Receive Enable Delay (For Timing Group 3) */
13767/*! @{ */
13768#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RxEnDlyTg3_un_px_MASK (0x7FFU)
13769#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RxEnDlyTg3_un_px_SHIFT (0U)
13770#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RxEnDlyTg3_un_px(x) \
13771 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RxEnDlyTg3_un_px_SHIFT)) & \
13772 DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P0_RxEnDlyTg3_un_px_MASK)
13773/*! @} */
13774
13775/*! @name RXCLKDLYTG0_U1_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
13776/*! @{ */
13777#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RxClkDlyTg0_un_px_MASK (0x3FU)
13778#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RxClkDlyTg0_un_px_SHIFT (0U)
13779#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RxClkDlyTg0_un_px(x) \
13780 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RxClkDlyTg0_un_px_SHIFT)) & \
13781 DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P0_RxClkDlyTg0_un_px_MASK)
13782/*! @} */
13783
13784/*! @name RXCLKDLYTG1_U1_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
13785/*! @{ */
13786#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RxClkDlyTg1_un_px_MASK (0x3FU)
13787#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RxClkDlyTg1_un_px_SHIFT (0U)
13788#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RxClkDlyTg1_un_px(x) \
13789 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RxClkDlyTg1_un_px_SHIFT)) & \
13790 DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P0_RxClkDlyTg1_un_px_MASK)
13791/*! @} */
13792
13793/*! @name RXCLKDLYTG2_U1_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
13794/*! @{ */
13795#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RxClkDlyTg2_un_px_MASK (0x3FU)
13796#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RxClkDlyTg2_un_px_SHIFT (0U)
13797#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RxClkDlyTg2_un_px(x) \
13798 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RxClkDlyTg2_un_px_SHIFT)) & \
13799 DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P0_RxClkDlyTg2_un_px_MASK)
13800/*! @} */
13801
13802/*! @name RXCLKDLYTG3_U1_P0 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
13803/*! @{ */
13804#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RxClkDlyTg3_un_px_MASK (0x3FU)
13805#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RxClkDlyTg3_un_px_SHIFT (0U)
13806#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RxClkDlyTg3_un_px(x) \
13807 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RxClkDlyTg3_un_px_SHIFT)) & \
13808 DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P0_RxClkDlyTg3_un_px_MASK)
13809/*! @} */
13810
13811/*! @name RXCLKCDLYTG0_U1_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
13812/*! @{ */
13813#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RxClkcDlyTg0_un_px_MASK (0x3FU)
13814#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RxClkcDlyTg0_un_px_SHIFT (0U)
13815#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RxClkcDlyTg0_un_px(x) \
13816 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RxClkcDlyTg0_un_px_SHIFT)) & \
13817 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P0_RxClkcDlyTg0_un_px_MASK)
13818/*! @} */
13819
13820/*! @name RXCLKCDLYTG1_U1_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
13821/*! @{ */
13822#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RxClkcDlyTg1_un_px_MASK (0x3FU)
13823#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RxClkcDlyTg1_un_px_SHIFT (0U)
13824#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RxClkcDlyTg1_un_px(x) \
13825 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RxClkcDlyTg1_un_px_SHIFT)) & \
13826 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P0_RxClkcDlyTg1_un_px_MASK)
13827/*! @} */
13828
13829/*! @name RXCLKCDLYTG2_U1_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
13830/*! @{ */
13831#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RxClkcDlyTg2_un_px_MASK (0x3FU)
13832#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RxClkcDlyTg2_un_px_SHIFT (0U)
13833#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RxClkcDlyTg2_un_px(x) \
13834 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RxClkcDlyTg2_un_px_SHIFT)) & \
13835 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P0_RxClkcDlyTg2_un_px_MASK)
13836/*! @} */
13837
13838/*! @name RXCLKCDLYTG3_U1_P0 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
13839/*! @{ */
13840#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RxClkcDlyTg3_un_px_MASK (0x3FU)
13841#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RxClkcDlyTg3_un_px_SHIFT (0U)
13842#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RxClkcDlyTg3_un_px(x) \
13843 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RxClkcDlyTg3_un_px_SHIFT)) & \
13844 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P0_RxClkcDlyTg3_un_px_MASK)
13845/*! @} */
13846
13847/*! @name TXDQDLYTG0_R1_P0 - Write DQ Delay (Timing Group 0). */
13848/*! @{ */
13849#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU)
13850#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TxDqDlyTg0_rn_px_SHIFT (0U)
13851#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TxDqDlyTg0_rn_px(x) \
13852 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TxDqDlyTg0_rn_px_SHIFT)) & \
13853 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P0_TxDqDlyTg0_rn_px_MASK)
13854/*! @} */
13855
13856/*! @name TXDQDLYTG1_R1_P0 - Write DQ Delay (Timing Group 1). */
13857/*! @{ */
13858#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU)
13859#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TxDqDlyTg1_rn_px_SHIFT (0U)
13860#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TxDqDlyTg1_rn_px(x) \
13861 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TxDqDlyTg1_rn_px_SHIFT)) & \
13862 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P0_TxDqDlyTg1_rn_px_MASK)
13863/*! @} */
13864
13865/*! @name TXDQDLYTG2_R1_P0 - Write DQ Delay (Timing Group 2). */
13866/*! @{ */
13867#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU)
13868#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TxDqDlyTg2_rn_px_SHIFT (0U)
13869#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TxDqDlyTg2_rn_px(x) \
13870 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TxDqDlyTg2_rn_px_SHIFT)) & \
13871 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P0_TxDqDlyTg2_rn_px_MASK)
13872/*! @} */
13873
13874/*! @name TXDQDLYTG3_R1_P0 - Write DQ Delay (Timing Group 3). */
13875/*! @{ */
13876#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU)
13877#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TxDqDlyTg3_rn_px_SHIFT (0U)
13878#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TxDqDlyTg3_rn_px(x) \
13879 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TxDqDlyTg3_rn_px_SHIFT)) & \
13880 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P0_TxDqDlyTg3_rn_px_MASK)
13881/*! @} */
13882
13883/*! @name TXDQSDLYTG0_U1_P0 - Write DQS Delay (Timing Group DEST=0). */
13884/*! @{ */
13885#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TxDqsDlyTg0_un_px_MASK (0x3FFU)
13886#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TxDqsDlyTg0_un_px_SHIFT (0U)
13887#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TxDqsDlyTg0_un_px(x) \
13888 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TxDqsDlyTg0_un_px_SHIFT)) & \
13889 DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P0_TxDqsDlyTg0_un_px_MASK)
13890/*! @} */
13891
13892/*! @name TXDQSDLYTG1_U1_P0 - Write DQS Delay (Timing Group DEST=1). */
13893/*! @{ */
13894#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TxDqsDlyTg1_un_px_MASK (0x3FFU)
13895#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TxDqsDlyTg1_un_px_SHIFT (0U)
13896#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TxDqsDlyTg1_un_px(x) \
13897 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TxDqsDlyTg1_un_px_SHIFT)) & \
13898 DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P0_TxDqsDlyTg1_un_px_MASK)
13899/*! @} */
13900
13901/*! @name TXDQSDLYTG2_U1_P0 - Write DQS Delay (Timing Group DEST=2). */
13902/*! @{ */
13903#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TxDqsDlyTg2_un_px_MASK (0x3FFU)
13904#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TxDqsDlyTg2_un_px_SHIFT (0U)
13905#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TxDqsDlyTg2_un_px(x) \
13906 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TxDqsDlyTg2_un_px_SHIFT)) & \
13907 DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P0_TxDqsDlyTg2_un_px_MASK)
13908/*! @} */
13909
13910/*! @name TXDQSDLYTG3_U1_P0 - Write DQS Delay (Timing Group DEST=3). */
13911/*! @{ */
13912#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TxDqsDlyTg3_un_px_MASK (0x3FFU)
13913#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TxDqsDlyTg3_un_px_SHIFT (0U)
13914#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TxDqsDlyTg3_un_px(x) \
13915 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TxDqsDlyTg3_un_px_SHIFT)) & \
13916 DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P0_TxDqsDlyTg3_un_px_MASK)
13917/*! @} */
13918
13919/*! @name VREFDAC1_R2 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
13920/*! @{ */
13921#define DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VrefDAC1_rx_MASK (0x7FU)
13922#define DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VrefDAC1_rx_SHIFT (0U)
13923#define DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VrefDAC1_rx(x) \
13924 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VrefDAC1_rx_SHIFT)) & \
13925 DWC_DDRPHYA_DBYTE_VREFDAC1_R2_VrefDAC1_rx_MASK)
13926/*! @} */
13927
13928/*! @name VREFDAC0_R2 - VrefDAC0 control for DQ Receiver */
13929/*! @{ */
13930#define DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VrefDAC0_rx_MASK (0x7FU)
13931#define DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VrefDAC0_rx_SHIFT (0U)
13932#define DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VrefDAC0_rx(x) \
13933 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VrefDAC0_rx_SHIFT)) & \
13934 DWC_DDRPHYA_DBYTE_VREFDAC0_R2_VrefDAC0_rx_MASK)
13935/*! @} */
13936
13937/*! @name RXPBDLYTG0_R2 - Read DQ per-bit BDL delay (Timing Group 0). */
13938/*! @{ */
13939#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RxPBDlyTg0_rx_MASK (0x7FU)
13940#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RxPBDlyTg0_rx_SHIFT (0U)
13941#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RxPBDlyTg0_rx(x) \
13942 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RxPBDlyTg0_rx_SHIFT)) & \
13943 DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R2_RxPBDlyTg0_rx_MASK)
13944/*! @} */
13945
13946/*! @name RXPBDLYTG1_R2 - Read DQ per-bit BDL delay (Timing Group 1). */
13947/*! @{ */
13948#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RxPBDlyTg1_rx_MASK (0x7FU)
13949#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RxPBDlyTg1_rx_SHIFT (0U)
13950#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RxPBDlyTg1_rx(x) \
13951 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RxPBDlyTg1_rx_SHIFT)) & \
13952 DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R2_RxPBDlyTg1_rx_MASK)
13953/*! @} */
13954
13955/*! @name RXPBDLYTG2_R2 - Read DQ per-bit BDL delay (Timing Group 2). */
13956/*! @{ */
13957#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RxPBDlyTg2_rx_MASK (0x7FU)
13958#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RxPBDlyTg2_rx_SHIFT (0U)
13959#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RxPBDlyTg2_rx(x) \
13960 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RxPBDlyTg2_rx_SHIFT)) & \
13961 DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R2_RxPBDlyTg2_rx_MASK)
13962/*! @} */
13963
13964/*! @name RXPBDLYTG3_R2 - Read DQ per-bit BDL delay (Timing Group 3). */
13965/*! @{ */
13966#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RxPBDlyTg3_rx_MASK (0x7FU)
13967#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RxPBDlyTg3_rx_SHIFT (0U)
13968#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RxPBDlyTg3_rx(x) \
13969 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RxPBDlyTg3_rx_SHIFT)) & \
13970 DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R2_RxPBDlyTg3_rx_MASK)
13971/*! @} */
13972
13973/*! @name TXDQDLYTG0_R2_P0 - Write DQ Delay (Timing Group 0). */
13974/*! @{ */
13975#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU)
13976#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TxDqDlyTg0_rn_px_SHIFT (0U)
13977#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TxDqDlyTg0_rn_px(x) \
13978 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TxDqDlyTg0_rn_px_SHIFT)) & \
13979 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P0_TxDqDlyTg0_rn_px_MASK)
13980/*! @} */
13981
13982/*! @name TXDQDLYTG1_R2_P0 - Write DQ Delay (Timing Group 1). */
13983/*! @{ */
13984#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU)
13985#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TxDqDlyTg1_rn_px_SHIFT (0U)
13986#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TxDqDlyTg1_rn_px(x) \
13987 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TxDqDlyTg1_rn_px_SHIFT)) & \
13988 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P0_TxDqDlyTg1_rn_px_MASK)
13989/*! @} */
13990
13991/*! @name TXDQDLYTG2_R2_P0 - Write DQ Delay (Timing Group 2). */
13992/*! @{ */
13993#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU)
13994#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TxDqDlyTg2_rn_px_SHIFT (0U)
13995#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TxDqDlyTg2_rn_px(x) \
13996 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TxDqDlyTg2_rn_px_SHIFT)) & \
13997 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P0_TxDqDlyTg2_rn_px_MASK)
13998/*! @} */
13999
14000/*! @name TXDQDLYTG3_R2_P0 - Write DQ Delay (Timing Group 3). */
14001/*! @{ */
14002#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU)
14003#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TxDqDlyTg3_rn_px_SHIFT (0U)
14004#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TxDqDlyTg3_rn_px(x) \
14005 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TxDqDlyTg3_rn_px_SHIFT)) & \
14006 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P0_TxDqDlyTg3_rn_px_MASK)
14007/*! @} */
14008
14009/*! @name VREFDAC1_R3 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
14010/*! @{ */
14011#define DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VrefDAC1_rx_MASK (0x7FU)
14012#define DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VrefDAC1_rx_SHIFT (0U)
14013#define DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VrefDAC1_rx(x) \
14014 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VrefDAC1_rx_SHIFT)) & \
14015 DWC_DDRPHYA_DBYTE_VREFDAC1_R3_VrefDAC1_rx_MASK)
14016/*! @} */
14017
14018/*! @name VREFDAC0_R3 - VrefDAC0 control for DQ Receiver */
14019/*! @{ */
14020#define DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VrefDAC0_rx_MASK (0x7FU)
14021#define DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VrefDAC0_rx_SHIFT (0U)
14022#define DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VrefDAC0_rx(x) \
14023 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VrefDAC0_rx_SHIFT)) & \
14024 DWC_DDRPHYA_DBYTE_VREFDAC0_R3_VrefDAC0_rx_MASK)
14025/*! @} */
14026
14027/*! @name RXPBDLYTG0_R3 - Read DQ per-bit BDL delay (Timing Group 0). */
14028/*! @{ */
14029#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RxPBDlyTg0_rx_MASK (0x7FU)
14030#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RxPBDlyTg0_rx_SHIFT (0U)
14031#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RxPBDlyTg0_rx(x) \
14032 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RxPBDlyTg0_rx_SHIFT)) & \
14033 DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R3_RxPBDlyTg0_rx_MASK)
14034/*! @} */
14035
14036/*! @name RXPBDLYTG1_R3 - Read DQ per-bit BDL delay (Timing Group 1). */
14037/*! @{ */
14038#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RxPBDlyTg1_rx_MASK (0x7FU)
14039#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RxPBDlyTg1_rx_SHIFT (0U)
14040#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RxPBDlyTg1_rx(x) \
14041 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RxPBDlyTg1_rx_SHIFT)) & \
14042 DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R3_RxPBDlyTg1_rx_MASK)
14043/*! @} */
14044
14045/*! @name RXPBDLYTG2_R3 - Read DQ per-bit BDL delay (Timing Group 2). */
14046/*! @{ */
14047#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RxPBDlyTg2_rx_MASK (0x7FU)
14048#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RxPBDlyTg2_rx_SHIFT (0U)
14049#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RxPBDlyTg2_rx(x) \
14050 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RxPBDlyTg2_rx_SHIFT)) & \
14051 DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R3_RxPBDlyTg2_rx_MASK)
14052/*! @} */
14053
14054/*! @name RXPBDLYTG3_R3 - Read DQ per-bit BDL delay (Timing Group 3). */
14055/*! @{ */
14056#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RxPBDlyTg3_rx_MASK (0x7FU)
14057#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RxPBDlyTg3_rx_SHIFT (0U)
14058#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RxPBDlyTg3_rx(x) \
14059 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RxPBDlyTg3_rx_SHIFT)) & \
14060 DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R3_RxPBDlyTg3_rx_MASK)
14061/*! @} */
14062
14063/*! @name TXDQDLYTG0_R3_P0 - Write DQ Delay (Timing Group 0). */
14064/*! @{ */
14065#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU)
14066#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TxDqDlyTg0_rn_px_SHIFT (0U)
14067#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TxDqDlyTg0_rn_px(x) \
14068 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TxDqDlyTg0_rn_px_SHIFT)) & \
14069 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P0_TxDqDlyTg0_rn_px_MASK)
14070/*! @} */
14071
14072/*! @name TXDQDLYTG1_R3_P0 - Write DQ Delay (Timing Group 1). */
14073/*! @{ */
14074#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU)
14075#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TxDqDlyTg1_rn_px_SHIFT (0U)
14076#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TxDqDlyTg1_rn_px(x) \
14077 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TxDqDlyTg1_rn_px_SHIFT)) & \
14078 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P0_TxDqDlyTg1_rn_px_MASK)
14079/*! @} */
14080
14081/*! @name TXDQDLYTG2_R3_P0 - Write DQ Delay (Timing Group 2). */
14082/*! @{ */
14083#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU)
14084#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TxDqDlyTg2_rn_px_SHIFT (0U)
14085#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TxDqDlyTg2_rn_px(x) \
14086 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TxDqDlyTg2_rn_px_SHIFT)) & \
14087 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P0_TxDqDlyTg2_rn_px_MASK)
14088/*! @} */
14089
14090/*! @name TXDQDLYTG3_R3_P0 - Write DQ Delay (Timing Group 3). */
14091/*! @{ */
14092#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU)
14093#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TxDqDlyTg3_rn_px_SHIFT (0U)
14094#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TxDqDlyTg3_rn_px(x) \
14095 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TxDqDlyTg3_rn_px_SHIFT)) & \
14096 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P0_TxDqDlyTg3_rn_px_MASK)
14097/*! @} */
14098
14099/*! @name VREFDAC1_R4 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
14100/*! @{ */
14101#define DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VrefDAC1_rx_MASK (0x7FU)
14102#define DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VrefDAC1_rx_SHIFT (0U)
14103#define DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VrefDAC1_rx(x) \
14104 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VrefDAC1_rx_SHIFT)) & \
14105 DWC_DDRPHYA_DBYTE_VREFDAC1_R4_VrefDAC1_rx_MASK)
14106/*! @} */
14107
14108/*! @name VREFDAC0_R4 - VrefDAC0 control for DQ Receiver */
14109/*! @{ */
14110#define DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VrefDAC0_rx_MASK (0x7FU)
14111#define DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VrefDAC0_rx_SHIFT (0U)
14112#define DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VrefDAC0_rx(x) \
14113 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VrefDAC0_rx_SHIFT)) & \
14114 DWC_DDRPHYA_DBYTE_VREFDAC0_R4_VrefDAC0_rx_MASK)
14115/*! @} */
14116
14117/*! @name RXPBDLYTG0_R4 - Read DQ per-bit BDL delay (Timing Group 0). */
14118/*! @{ */
14119#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RxPBDlyTg0_rx_MASK (0x7FU)
14120#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RxPBDlyTg0_rx_SHIFT (0U)
14121#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RxPBDlyTg0_rx(x) \
14122 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RxPBDlyTg0_rx_SHIFT)) & \
14123 DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R4_RxPBDlyTg0_rx_MASK)
14124/*! @} */
14125
14126/*! @name RXPBDLYTG1_R4 - Read DQ per-bit BDL delay (Timing Group 1). */
14127/*! @{ */
14128#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RxPBDlyTg1_rx_MASK (0x7FU)
14129#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RxPBDlyTg1_rx_SHIFT (0U)
14130#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RxPBDlyTg1_rx(x) \
14131 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RxPBDlyTg1_rx_SHIFT)) & \
14132 DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R4_RxPBDlyTg1_rx_MASK)
14133/*! @} */
14134
14135/*! @name RXPBDLYTG2_R4 - Read DQ per-bit BDL delay (Timing Group 2). */
14136/*! @{ */
14137#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RxPBDlyTg2_rx_MASK (0x7FU)
14138#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RxPBDlyTg2_rx_SHIFT (0U)
14139#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RxPBDlyTg2_rx(x) \
14140 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RxPBDlyTg2_rx_SHIFT)) & \
14141 DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R4_RxPBDlyTg2_rx_MASK)
14142/*! @} */
14143
14144/*! @name RXPBDLYTG3_R4 - Read DQ per-bit BDL delay (Timing Group 3). */
14145/*! @{ */
14146#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RxPBDlyTg3_rx_MASK (0x7FU)
14147#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RxPBDlyTg3_rx_SHIFT (0U)
14148#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RxPBDlyTg3_rx(x) \
14149 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RxPBDlyTg3_rx_SHIFT)) & \
14150 DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R4_RxPBDlyTg3_rx_MASK)
14151/*! @} */
14152
14153/*! @name TXDQDLYTG0_R4_P0 - Write DQ Delay (Timing Group 0). */
14154/*! @{ */
14155#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU)
14156#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TxDqDlyTg0_rn_px_SHIFT (0U)
14157#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TxDqDlyTg0_rn_px(x) \
14158 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TxDqDlyTg0_rn_px_SHIFT)) & \
14159 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P0_TxDqDlyTg0_rn_px_MASK)
14160/*! @} */
14161
14162/*! @name TXDQDLYTG1_R4_P0 - Write DQ Delay (Timing Group 1). */
14163/*! @{ */
14164#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU)
14165#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TxDqDlyTg1_rn_px_SHIFT (0U)
14166#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TxDqDlyTg1_rn_px(x) \
14167 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TxDqDlyTg1_rn_px_SHIFT)) & \
14168 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P0_TxDqDlyTg1_rn_px_MASK)
14169/*! @} */
14170
14171/*! @name TXDQDLYTG2_R4_P0 - Write DQ Delay (Timing Group 2). */
14172/*! @{ */
14173#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU)
14174#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TxDqDlyTg2_rn_px_SHIFT (0U)
14175#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TxDqDlyTg2_rn_px(x) \
14176 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TxDqDlyTg2_rn_px_SHIFT)) & \
14177 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P0_TxDqDlyTg2_rn_px_MASK)
14178/*! @} */
14179
14180/*! @name TXDQDLYTG3_R4_P0 - Write DQ Delay (Timing Group 3). */
14181/*! @{ */
14182#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU)
14183#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TxDqDlyTg3_rn_px_SHIFT (0U)
14184#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TxDqDlyTg3_rn_px(x) \
14185 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TxDqDlyTg3_rn_px_SHIFT)) & \
14186 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P0_TxDqDlyTg3_rn_px_MASK)
14187/*! @} */
14188
14189/*! @name VREFDAC1_R5 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
14190/*! @{ */
14191#define DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VrefDAC1_rx_MASK (0x7FU)
14192#define DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VrefDAC1_rx_SHIFT (0U)
14193#define DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VrefDAC1_rx(x) \
14194 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VrefDAC1_rx_SHIFT)) & \
14195 DWC_DDRPHYA_DBYTE_VREFDAC1_R5_VrefDAC1_rx_MASK)
14196/*! @} */
14197
14198/*! @name VREFDAC0_R5 - VrefDAC0 control for DQ Receiver */
14199/*! @{ */
14200#define DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VrefDAC0_rx_MASK (0x7FU)
14201#define DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VrefDAC0_rx_SHIFT (0U)
14202#define DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VrefDAC0_rx(x) \
14203 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VrefDAC0_rx_SHIFT)) & \
14204 DWC_DDRPHYA_DBYTE_VREFDAC0_R5_VrefDAC0_rx_MASK)
14205/*! @} */
14206
14207/*! @name RXPBDLYTG0_R5 - Read DQ per-bit BDL delay (Timing Group 0). */
14208/*! @{ */
14209#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RxPBDlyTg0_rx_MASK (0x7FU)
14210#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RxPBDlyTg0_rx_SHIFT (0U)
14211#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RxPBDlyTg0_rx(x) \
14212 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RxPBDlyTg0_rx_SHIFT)) & \
14213 DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R5_RxPBDlyTg0_rx_MASK)
14214/*! @} */
14215
14216/*! @name RXPBDLYTG1_R5 - Read DQ per-bit BDL delay (Timing Group 1). */
14217/*! @{ */
14218#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RxPBDlyTg1_rx_MASK (0x7FU)
14219#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RxPBDlyTg1_rx_SHIFT (0U)
14220#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RxPBDlyTg1_rx(x) \
14221 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RxPBDlyTg1_rx_SHIFT)) & \
14222 DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R5_RxPBDlyTg1_rx_MASK)
14223/*! @} */
14224
14225/*! @name RXPBDLYTG2_R5 - Read DQ per-bit BDL delay (Timing Group 2). */
14226/*! @{ */
14227#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RxPBDlyTg2_rx_MASK (0x7FU)
14228#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RxPBDlyTg2_rx_SHIFT (0U)
14229#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RxPBDlyTg2_rx(x) \
14230 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RxPBDlyTg2_rx_SHIFT)) & \
14231 DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R5_RxPBDlyTg2_rx_MASK)
14232/*! @} */
14233
14234/*! @name RXPBDLYTG3_R5 - Read DQ per-bit BDL delay (Timing Group 3). */
14235/*! @{ */
14236#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RxPBDlyTg3_rx_MASK (0x7FU)
14237#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RxPBDlyTg3_rx_SHIFT (0U)
14238#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RxPBDlyTg3_rx(x) \
14239 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RxPBDlyTg3_rx_SHIFT)) & \
14240 DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R5_RxPBDlyTg3_rx_MASK)
14241/*! @} */
14242
14243/*! @name TXDQDLYTG0_R5_P0 - Write DQ Delay (Timing Group 0). */
14244/*! @{ */
14245#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU)
14246#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TxDqDlyTg0_rn_px_SHIFT (0U)
14247#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TxDqDlyTg0_rn_px(x) \
14248 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TxDqDlyTg0_rn_px_SHIFT)) & \
14249 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P0_TxDqDlyTg0_rn_px_MASK)
14250/*! @} */
14251
14252/*! @name TXDQDLYTG1_R5_P0 - Write DQ Delay (Timing Group 1). */
14253/*! @{ */
14254#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU)
14255#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TxDqDlyTg1_rn_px_SHIFT (0U)
14256#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TxDqDlyTg1_rn_px(x) \
14257 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TxDqDlyTg1_rn_px_SHIFT)) & \
14258 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P0_TxDqDlyTg1_rn_px_MASK)
14259/*! @} */
14260
14261/*! @name TXDQDLYTG2_R5_P0 - Write DQ Delay (Timing Group 2). */
14262/*! @{ */
14263#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU)
14264#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TxDqDlyTg2_rn_px_SHIFT (0U)
14265#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TxDqDlyTg2_rn_px(x) \
14266 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TxDqDlyTg2_rn_px_SHIFT)) & \
14267 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P0_TxDqDlyTg2_rn_px_MASK)
14268/*! @} */
14269
14270/*! @name TXDQDLYTG3_R5_P0 - Write DQ Delay (Timing Group 3). */
14271/*! @{ */
14272#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU)
14273#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TxDqDlyTg3_rn_px_SHIFT (0U)
14274#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TxDqDlyTg3_rn_px(x) \
14275 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TxDqDlyTg3_rn_px_SHIFT)) & \
14276 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P0_TxDqDlyTg3_rn_px_MASK)
14277/*! @} */
14278
14279/*! @name VREFDAC1_R6 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
14280/*! @{ */
14281#define DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VrefDAC1_rx_MASK (0x7FU)
14282#define DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VrefDAC1_rx_SHIFT (0U)
14283#define DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VrefDAC1_rx(x) \
14284 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VrefDAC1_rx_SHIFT)) & \
14285 DWC_DDRPHYA_DBYTE_VREFDAC1_R6_VrefDAC1_rx_MASK)
14286/*! @} */
14287
14288/*! @name VREFDAC0_R6 - VrefDAC0 control for DQ Receiver */
14289/*! @{ */
14290#define DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VrefDAC0_rx_MASK (0x7FU)
14291#define DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VrefDAC0_rx_SHIFT (0U)
14292#define DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VrefDAC0_rx(x) \
14293 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VrefDAC0_rx_SHIFT)) & \
14294 DWC_DDRPHYA_DBYTE_VREFDAC0_R6_VrefDAC0_rx_MASK)
14295/*! @} */
14296
14297/*! @name RXPBDLYTG0_R6 - Read DQ per-bit BDL delay (Timing Group 0). */
14298/*! @{ */
14299#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RxPBDlyTg0_rx_MASK (0x7FU)
14300#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RxPBDlyTg0_rx_SHIFT (0U)
14301#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RxPBDlyTg0_rx(x) \
14302 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RxPBDlyTg0_rx_SHIFT)) & \
14303 DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R6_RxPBDlyTg0_rx_MASK)
14304/*! @} */
14305
14306/*! @name RXPBDLYTG1_R6 - Read DQ per-bit BDL delay (Timing Group 1). */
14307/*! @{ */
14308#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RxPBDlyTg1_rx_MASK (0x7FU)
14309#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RxPBDlyTg1_rx_SHIFT (0U)
14310#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RxPBDlyTg1_rx(x) \
14311 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RxPBDlyTg1_rx_SHIFT)) & \
14312 DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R6_RxPBDlyTg1_rx_MASK)
14313/*! @} */
14314
14315/*! @name RXPBDLYTG2_R6 - Read DQ per-bit BDL delay (Timing Group 2). */
14316/*! @{ */
14317#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RxPBDlyTg2_rx_MASK (0x7FU)
14318#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RxPBDlyTg2_rx_SHIFT (0U)
14319#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RxPBDlyTg2_rx(x) \
14320 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RxPBDlyTg2_rx_SHIFT)) & \
14321 DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R6_RxPBDlyTg2_rx_MASK)
14322/*! @} */
14323
14324/*! @name RXPBDLYTG3_R6 - Read DQ per-bit BDL delay (Timing Group 3). */
14325/*! @{ */
14326#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RxPBDlyTg3_rx_MASK (0x7FU)
14327#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RxPBDlyTg3_rx_SHIFT (0U)
14328#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RxPBDlyTg3_rx(x) \
14329 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RxPBDlyTg3_rx_SHIFT)) & \
14330 DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R6_RxPBDlyTg3_rx_MASK)
14331/*! @} */
14332
14333/*! @name TXDQDLYTG0_R6_P0 - Write DQ Delay (Timing Group 0). */
14334/*! @{ */
14335#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU)
14336#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TxDqDlyTg0_rn_px_SHIFT (0U)
14337#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TxDqDlyTg0_rn_px(x) \
14338 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TxDqDlyTg0_rn_px_SHIFT)) & \
14339 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P0_TxDqDlyTg0_rn_px_MASK)
14340/*! @} */
14341
14342/*! @name TXDQDLYTG1_R6_P0 - Write DQ Delay (Timing Group 1). */
14343/*! @{ */
14344#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU)
14345#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TxDqDlyTg1_rn_px_SHIFT (0U)
14346#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TxDqDlyTg1_rn_px(x) \
14347 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TxDqDlyTg1_rn_px_SHIFT)) & \
14348 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P0_TxDqDlyTg1_rn_px_MASK)
14349/*! @} */
14350
14351/*! @name TXDQDLYTG2_R6_P0 - Write DQ Delay (Timing Group 2). */
14352/*! @{ */
14353#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU)
14354#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TxDqDlyTg2_rn_px_SHIFT (0U)
14355#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TxDqDlyTg2_rn_px(x) \
14356 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TxDqDlyTg2_rn_px_SHIFT)) & \
14357 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P0_TxDqDlyTg2_rn_px_MASK)
14358/*! @} */
14359
14360/*! @name TXDQDLYTG3_R6_P0 - Write DQ Delay (Timing Group 3). */
14361/*! @{ */
14362#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU)
14363#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TxDqDlyTg3_rn_px_SHIFT (0U)
14364#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TxDqDlyTg3_rn_px(x) \
14365 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TxDqDlyTg3_rn_px_SHIFT)) & \
14366 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P0_TxDqDlyTg3_rn_px_MASK)
14367/*! @} */
14368
14369/*! @name VREFDAC1_R7 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
14370/*! @{ */
14371#define DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VrefDAC1_rx_MASK (0x7FU)
14372#define DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VrefDAC1_rx_SHIFT (0U)
14373#define DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VrefDAC1_rx(x) \
14374 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VrefDAC1_rx_SHIFT)) & \
14375 DWC_DDRPHYA_DBYTE_VREFDAC1_R7_VrefDAC1_rx_MASK)
14376/*! @} */
14377
14378/*! @name VREFDAC0_R7 - VrefDAC0 control for DQ Receiver */
14379/*! @{ */
14380#define DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VrefDAC0_rx_MASK (0x7FU)
14381#define DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VrefDAC0_rx_SHIFT (0U)
14382#define DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VrefDAC0_rx(x) \
14383 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VrefDAC0_rx_SHIFT)) & \
14384 DWC_DDRPHYA_DBYTE_VREFDAC0_R7_VrefDAC0_rx_MASK)
14385/*! @} */
14386
14387/*! @name RXPBDLYTG0_R7 - Read DQ per-bit BDL delay (Timing Group 0). */
14388/*! @{ */
14389#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RxPBDlyTg0_rx_MASK (0x7FU)
14390#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RxPBDlyTg0_rx_SHIFT (0U)
14391#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RxPBDlyTg0_rx(x) \
14392 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RxPBDlyTg0_rx_SHIFT)) & \
14393 DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R7_RxPBDlyTg0_rx_MASK)
14394/*! @} */
14395
14396/*! @name RXPBDLYTG1_R7 - Read DQ per-bit BDL delay (Timing Group 1). */
14397/*! @{ */
14398#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RxPBDlyTg1_rx_MASK (0x7FU)
14399#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RxPBDlyTg1_rx_SHIFT (0U)
14400#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RxPBDlyTg1_rx(x) \
14401 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RxPBDlyTg1_rx_SHIFT)) & \
14402 DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R7_RxPBDlyTg1_rx_MASK)
14403/*! @} */
14404
14405/*! @name RXPBDLYTG2_R7 - Read DQ per-bit BDL delay (Timing Group 2). */
14406/*! @{ */
14407#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RxPBDlyTg2_rx_MASK (0x7FU)
14408#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RxPBDlyTg2_rx_SHIFT (0U)
14409#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RxPBDlyTg2_rx(x) \
14410 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RxPBDlyTg2_rx_SHIFT)) & \
14411 DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R7_RxPBDlyTg2_rx_MASK)
14412/*! @} */
14413
14414/*! @name RXPBDLYTG3_R7 - Read DQ per-bit BDL delay (Timing Group 3). */
14415/*! @{ */
14416#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RxPBDlyTg3_rx_MASK (0x7FU)
14417#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RxPBDlyTg3_rx_SHIFT (0U)
14418#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RxPBDlyTg3_rx(x) \
14419 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RxPBDlyTg3_rx_SHIFT)) & \
14420 DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R7_RxPBDlyTg3_rx_MASK)
14421/*! @} */
14422
14423/*! @name TXDQDLYTG0_R7_P0 - Write DQ Delay (Timing Group 0). */
14424/*! @{ */
14425#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU)
14426#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TxDqDlyTg0_rn_px_SHIFT (0U)
14427#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TxDqDlyTg0_rn_px(x) \
14428 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TxDqDlyTg0_rn_px_SHIFT)) & \
14429 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P0_TxDqDlyTg0_rn_px_MASK)
14430/*! @} */
14431
14432/*! @name TXDQDLYTG1_R7_P0 - Write DQ Delay (Timing Group 1). */
14433/*! @{ */
14434#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU)
14435#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TxDqDlyTg1_rn_px_SHIFT (0U)
14436#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TxDqDlyTg1_rn_px(x) \
14437 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TxDqDlyTg1_rn_px_SHIFT)) & \
14438 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P0_TxDqDlyTg1_rn_px_MASK)
14439/*! @} */
14440
14441/*! @name TXDQDLYTG2_R7_P0 - Write DQ Delay (Timing Group 2). */
14442/*! @{ */
14443#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU)
14444#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TxDqDlyTg2_rn_px_SHIFT (0U)
14445#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TxDqDlyTg2_rn_px(x) \
14446 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TxDqDlyTg2_rn_px_SHIFT)) & \
14447 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P0_TxDqDlyTg2_rn_px_MASK)
14448/*! @} */
14449
14450/*! @name TXDQDLYTG3_R7_P0 - Write DQ Delay (Timing Group 3). */
14451/*! @{ */
14452#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU)
14453#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TxDqDlyTg3_rn_px_SHIFT (0U)
14454#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TxDqDlyTg3_rn_px(x) \
14455 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TxDqDlyTg3_rn_px_SHIFT)) & \
14456 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P0_TxDqDlyTg3_rn_px_MASK)
14457/*! @} */
14458
14459/*! @name VREFDAC1_R8 - VrefDAC1 control for DQ Receiver (used only when DFE is enabled in DDR4) */
14460/*! @{ */
14461#define DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VrefDAC1_rx_MASK (0x7FU)
14462#define DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VrefDAC1_rx_SHIFT (0U)
14463#define DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VrefDAC1_rx(x) \
14464 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VrefDAC1_rx_SHIFT)) & \
14465 DWC_DDRPHYA_DBYTE_VREFDAC1_R8_VrefDAC1_rx_MASK)
14466/*! @} */
14467
14468/*! @name VREFDAC0_R8 - VrefDAC0 control for DQ Receiver */
14469/*! @{ */
14470#define DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VrefDAC0_rx_MASK (0x7FU)
14471#define DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VrefDAC0_rx_SHIFT (0U)
14472#define DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VrefDAC0_rx(x) \
14473 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VrefDAC0_rx_SHIFT)) & \
14474 DWC_DDRPHYA_DBYTE_VREFDAC0_R8_VrefDAC0_rx_MASK)
14475/*! @} */
14476
14477/*! @name RXPBDLYTG0_R8 - Read DQ per-bit BDL delay (Timing Group 0). */
14478/*! @{ */
14479#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RxPBDlyTg0_rx_MASK (0x7FU)
14480#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RxPBDlyTg0_rx_SHIFT (0U)
14481#define DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RxPBDlyTg0_rx(x) \
14482 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RxPBDlyTg0_rx_SHIFT)) & \
14483 DWC_DDRPHYA_DBYTE_RXPBDLYTG0_R8_RxPBDlyTg0_rx_MASK)
14484/*! @} */
14485
14486/*! @name RXPBDLYTG1_R8 - Read DQ per-bit BDL delay (Timing Group 1). */
14487/*! @{ */
14488#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RxPBDlyTg1_rx_MASK (0x7FU)
14489#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RxPBDlyTg1_rx_SHIFT (0U)
14490#define DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RxPBDlyTg1_rx(x) \
14491 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RxPBDlyTg1_rx_SHIFT)) & \
14492 DWC_DDRPHYA_DBYTE_RXPBDLYTG1_R8_RxPBDlyTg1_rx_MASK)
14493/*! @} */
14494
14495/*! @name RXPBDLYTG2_R8 - Read DQ per-bit BDL delay (Timing Group 2). */
14496/*! @{ */
14497#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RxPBDlyTg2_rx_MASK (0x7FU)
14498#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RxPBDlyTg2_rx_SHIFT (0U)
14499#define DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RxPBDlyTg2_rx(x) \
14500 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RxPBDlyTg2_rx_SHIFT)) & \
14501 DWC_DDRPHYA_DBYTE_RXPBDLYTG2_R8_RxPBDlyTg2_rx_MASK)
14502/*! @} */
14503
14504/*! @name RXPBDLYTG3_R8 - Read DQ per-bit BDL delay (Timing Group 3). */
14505/*! @{ */
14506#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RxPBDlyTg3_rx_MASK (0x7FU)
14507#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RxPBDlyTg3_rx_SHIFT (0U)
14508#define DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RxPBDlyTg3_rx(x) \
14509 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RxPBDlyTg3_rx_SHIFT)) & \
14510 DWC_DDRPHYA_DBYTE_RXPBDLYTG3_R8_RxPBDlyTg3_rx_MASK)
14511/*! @} */
14512
14513/*! @name TXDQDLYTG0_R8_P0 - Write DQ Delay (Timing Group 0). */
14514/*! @{ */
14515#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TxDqDlyTg0_rn_px_MASK (0x1FFU)
14516#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TxDqDlyTg0_rn_px_SHIFT (0U)
14517#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TxDqDlyTg0_rn_px(x) \
14518 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TxDqDlyTg0_rn_px_SHIFT)) & \
14519 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P0_TxDqDlyTg0_rn_px_MASK)
14520/*! @} */
14521
14522/*! @name TXDQDLYTG1_R8_P0 - Write DQ Delay (Timing Group 1). */
14523/*! @{ */
14524#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TxDqDlyTg1_rn_px_MASK (0x1FFU)
14525#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TxDqDlyTg1_rn_px_SHIFT (0U)
14526#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TxDqDlyTg1_rn_px(x) \
14527 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TxDqDlyTg1_rn_px_SHIFT)) & \
14528 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P0_TxDqDlyTg1_rn_px_MASK)
14529/*! @} */
14530
14531/*! @name TXDQDLYTG2_R8_P0 - Write DQ Delay (Timing Group 2). */
14532/*! @{ */
14533#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TxDqDlyTg2_rn_px_MASK (0x1FFU)
14534#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TxDqDlyTg2_rn_px_SHIFT (0U)
14535#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TxDqDlyTg2_rn_px(x) \
14536 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TxDqDlyTg2_rn_px_SHIFT)) & \
14537 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P0_TxDqDlyTg2_rn_px_MASK)
14538/*! @} */
14539
14540/*! @name TXDQDLYTG3_R8_P0 - Write DQ Delay (Timing Group 3). */
14541/*! @{ */
14542#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TxDqDlyTg3_rn_px_MASK (0x1FFU)
14543#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TxDqDlyTg3_rn_px_SHIFT (0U)
14544#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TxDqDlyTg3_rn_px(x) \
14545 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TxDqDlyTg3_rn_px_SHIFT)) & \
14546 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P0_TxDqDlyTg3_rn_px_MASK)
14547/*! @} */
14548
14549/*! @name DFIMRL_P1 - DFI MaxReadLatency */
14550/*! @{ */
14551#define DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_p1_MASK (0x1FU)
14552#define DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_p1_SHIFT (0U)
14553#define DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_p1(x) \
14554 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_p1_SHIFT)) & \
14555 DWC_DDRPHYA_DBYTE_DFIMRL_P1_DFIMRL_p1_MASK)
14556/*! @} */
14557
14558/*! @name TXIMPEDANCECTRL0_B0_P1 - Data TX impedance controls */
14559/*! @{ */
14560#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqP_MASK (0x3FU)
14561#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqP_SHIFT (0U)
14562#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqP(x) \
14563 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqP_SHIFT)) & \
14564 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqP_MASK)
14565#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqN_MASK (0xFC0U)
14566#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqN_SHIFT (6U)
14567#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqN(x) \
14568 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqN_SHIFT)) & \
14569 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P1_DrvStrenDqN_MASK)
14570/*! @} */
14571
14572/*! @name DQDQSRCVCNTRL_B0_P1 - Dq/Dqs receiver control */
14573/*! @{ */
14574#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SelAnalogVref_MASK (0x1U)
14575#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SelAnalogVref_SHIFT (0U)
14576#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SelAnalogVref(x) \
14577 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SelAnalogVref_SHIFT)) & \
14578 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_SelAnalogVref_MASK)
14579#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_ExtVrefRange_MASK (0x2U)
14580#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_ExtVrefRange_SHIFT (1U)
14581#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_ExtVrefRange(x) \
14582 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_ExtVrefRange_SHIFT)) & \
14583 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_ExtVrefRange_MASK)
14584#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DfeCtrl_MASK (0xCU)
14585#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DfeCtrl_SHIFT (2U)
14586#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DfeCtrl(x) \
14587 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DfeCtrl_SHIFT)) & \
14588 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_DfeCtrl_MASK)
14589#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MajorModeDbyte_MASK (0x70U)
14590#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MajorModeDbyte_SHIFT (4U)
14591#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MajorModeDbyte(x) \
14592 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MajorModeDbyte_SHIFT)) & \
14593 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_MajorModeDbyte_MASK)
14594#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GainCurrAdj_MASK (0xF80U)
14595#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GainCurrAdj_SHIFT (7U)
14596#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GainCurrAdj(x) \
14597 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GainCurrAdj_SHIFT)) & \
14598 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P1_GainCurrAdj_MASK)
14599/*! @} */
14600
14601/*! @name TXEQUALIZATIONMODE_P1 - Tx dq driver equalization mode controls. */
14602/*! @{ */
14603#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TxEqMode_MASK (0x3U)
14604#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TxEqMode_SHIFT (0U)
14605#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TxEqMode(x) \
14606 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TxEqMode_SHIFT)) & \
14607 DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P1_TxEqMode_MASK)
14608/*! @} */
14609
14610/*! @name TXIMPEDANCECTRL1_B0_P1 - TX impedance controls */
14611/*! @{ */
14612#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqP_MASK (0x3FU)
14613#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqP_SHIFT (0U)
14614#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqP(x) \
14615 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqP_SHIFT)) & \
14616 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqP_MASK)
14617#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqN_MASK (0xFC0U)
14618#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqN_SHIFT (6U)
14619#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqN(x) \
14620 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqN_SHIFT)) & \
14621 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P1_DrvStrenFSDqN_MASK)
14622/*! @} */
14623
14624/*! @name TXIMPEDANCECTRL2_B0_P1 - TX equalization impedance controls */
14625/*! @{ */
14626#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQHiDqP_MASK (0x3FU)
14627#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQHiDqP_SHIFT (0U)
14628#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQHiDqP(x) \
14629 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQHiDqP_SHIFT)) & \
14630 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQHiDqP_MASK)
14631#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQLoDqN_MASK (0xFC0U)
14632#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQLoDqN_SHIFT (6U)
14633#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQLoDqN(x) \
14634 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQLoDqN_SHIFT)) & \
14635 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P1_DrvStrenEQLoDqN_MASK)
14636/*! @} */
14637
14638/*! @name DQDQSRCVCNTRL2_P1 - Dq/Dqs receiver control */
14639/*! @{ */
14640#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_EnRxAgressivePDR_MASK (0x1U)
14641#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_EnRxAgressivePDR_SHIFT (0U)
14642#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_EnRxAgressivePDR(x) \
14643 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_EnRxAgressivePDR_SHIFT)) & \
14644 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P1_EnRxAgressivePDR_MASK)
14645/*! @} */
14646
14647/*! @name TXODTDRVSTREN_B0_P1 - TX ODT driver strength control */
14648/*! @{ */
14649#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenP_MASK (0x3FU)
14650#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenP_SHIFT (0U)
14651#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenP(x) \
14652 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenP_SHIFT)) & \
14653 DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenP_MASK)
14654#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenN_MASK (0xFC0U)
14655#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenN_SHIFT (6U)
14656#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenN(x) \
14657 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenN_SHIFT)) & \
14658 DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P1_ODTStrenN_MASK)
14659/*! @} */
14660
14661/*! @name TXSLEWRATE_B0_P1 - TX slew rate controls */
14662/*! @{ */
14663#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreP_MASK (0xFU)
14664#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreP_SHIFT (0U)
14665#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreP(x) \
14666 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreP_SHIFT)) & \
14667 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreP_MASK)
14668#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreN_MASK (0xF0U)
14669#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreN_SHIFT (4U)
14670#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreN(x) \
14671 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreN_SHIFT)) & \
14672 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreN_MASK)
14673#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreDrvMode_MASK (0x700U)
14674#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreDrvMode_SHIFT (8U)
14675#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreDrvMode(x) \
14676 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreDrvMode_SHIFT)) & \
14677 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P1_TxPreDrvMode_MASK)
14678/*! @} */
14679
14680/*! @name RXENDLYTG0_U0_P1 - Trained Receive Enable Delay (For Timing Group 0) */
14681/*! @{ */
14682#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RxEnDlyTg0_un_px_MASK (0x7FFU)
14683#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RxEnDlyTg0_un_px_SHIFT (0U)
14684#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RxEnDlyTg0_un_px(x) \
14685 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RxEnDlyTg0_un_px_SHIFT)) & \
14686 DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P1_RxEnDlyTg0_un_px_MASK)
14687/*! @} */
14688
14689/*! @name RXENDLYTG1_U0_P1 - Trained Receive Enable Delay (For Timing Group 1) */
14690/*! @{ */
14691#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RxEnDlyTg1_un_px_MASK (0x7FFU)
14692#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RxEnDlyTg1_un_px_SHIFT (0U)
14693#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RxEnDlyTg1_un_px(x) \
14694 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RxEnDlyTg1_un_px_SHIFT)) & \
14695 DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P1_RxEnDlyTg1_un_px_MASK)
14696/*! @} */
14697
14698/*! @name RXENDLYTG2_U0_P1 - Trained Receive Enable Delay (For Timing Group 2) */
14699/*! @{ */
14700#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RxEnDlyTg2_un_px_MASK (0x7FFU)
14701#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RxEnDlyTg2_un_px_SHIFT (0U)
14702#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RxEnDlyTg2_un_px(x) \
14703 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RxEnDlyTg2_un_px_SHIFT)) & \
14704 DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P1_RxEnDlyTg2_un_px_MASK)
14705/*! @} */
14706
14707/*! @name RXENDLYTG3_U0_P1 - Trained Receive Enable Delay (For Timing Group 3) */
14708/*! @{ */
14709#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RxEnDlyTg3_un_px_MASK (0x7FFU)
14710#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RxEnDlyTg3_un_px_SHIFT (0U)
14711#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RxEnDlyTg3_un_px(x) \
14712 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RxEnDlyTg3_un_px_SHIFT)) & \
14713 DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P1_RxEnDlyTg3_un_px_MASK)
14714/*! @} */
14715
14716/*! @name RXCLKDLYTG0_U0_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
14717/*! @{ */
14718#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RxClkDlyTg0_un_px_MASK (0x3FU)
14719#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RxClkDlyTg0_un_px_SHIFT (0U)
14720#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RxClkDlyTg0_un_px(x) \
14721 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RxClkDlyTg0_un_px_SHIFT)) & \
14722 DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P1_RxClkDlyTg0_un_px_MASK)
14723/*! @} */
14724
14725/*! @name RXCLKDLYTG1_U0_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
14726/*! @{ */
14727#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RxClkDlyTg1_un_px_MASK (0x3FU)
14728#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RxClkDlyTg1_un_px_SHIFT (0U)
14729#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RxClkDlyTg1_un_px(x) \
14730 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RxClkDlyTg1_un_px_SHIFT)) & \
14731 DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P1_RxClkDlyTg1_un_px_MASK)
14732/*! @} */
14733
14734/*! @name RXCLKDLYTG2_U0_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
14735/*! @{ */
14736#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RxClkDlyTg2_un_px_MASK (0x3FU)
14737#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RxClkDlyTg2_un_px_SHIFT (0U)
14738#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RxClkDlyTg2_un_px(x) \
14739 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RxClkDlyTg2_un_px_SHIFT)) & \
14740 DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P1_RxClkDlyTg2_un_px_MASK)
14741/*! @} */
14742
14743/*! @name RXCLKDLYTG3_U0_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
14744/*! @{ */
14745#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RxClkDlyTg3_un_px_MASK (0x3FU)
14746#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RxClkDlyTg3_un_px_SHIFT (0U)
14747#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RxClkDlyTg3_un_px(x) \
14748 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RxClkDlyTg3_un_px_SHIFT)) & \
14749 DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P1_RxClkDlyTg3_un_px_MASK)
14750/*! @} */
14751
14752/*! @name RXCLKCDLYTG0_U0_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
14753/*! @{ */
14754#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RxClkcDlyTg0_un_px_MASK (0x3FU)
14755#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RxClkcDlyTg0_un_px_SHIFT (0U)
14756#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RxClkcDlyTg0_un_px(x) \
14757 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RxClkcDlyTg0_un_px_SHIFT)) & \
14758 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P1_RxClkcDlyTg0_un_px_MASK)
14759/*! @} */
14760
14761/*! @name RXCLKCDLYTG1_U0_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
14762/*! @{ */
14763#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RxClkcDlyTg1_un_px_MASK (0x3FU)
14764#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RxClkcDlyTg1_un_px_SHIFT (0U)
14765#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RxClkcDlyTg1_un_px(x) \
14766 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RxClkcDlyTg1_un_px_SHIFT)) & \
14767 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P1_RxClkcDlyTg1_un_px_MASK)
14768/*! @} */
14769
14770/*! @name RXCLKCDLYTG2_U0_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
14771/*! @{ */
14772#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RxClkcDlyTg2_un_px_MASK (0x3FU)
14773#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RxClkcDlyTg2_un_px_SHIFT (0U)
14774#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RxClkcDlyTg2_un_px(x) \
14775 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RxClkcDlyTg2_un_px_SHIFT)) & \
14776 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P1_RxClkcDlyTg2_un_px_MASK)
14777/*! @} */
14778
14779/*! @name RXCLKCDLYTG3_U0_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
14780/*! @{ */
14781#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RxClkcDlyTg3_un_px_MASK (0x3FU)
14782#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RxClkcDlyTg3_un_px_SHIFT (0U)
14783#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RxClkcDlyTg3_un_px(x) \
14784 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RxClkcDlyTg3_un_px_SHIFT)) & \
14785 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P1_RxClkcDlyTg3_un_px_MASK)
14786/*! @} */
14787
14788/*! @name TXDQDLYTG0_R0_P1 - Write DQ Delay (Timing Group 0). */
14789/*! @{ */
14790#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU)
14791#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TxDqDlyTg0_rn_px_SHIFT (0U)
14792#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TxDqDlyTg0_rn_px(x) \
14793 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TxDqDlyTg0_rn_px_SHIFT)) & \
14794 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P1_TxDqDlyTg0_rn_px_MASK)
14795/*! @} */
14796
14797/*! @name TXDQDLYTG1_R0_P1 - Write DQ Delay (Timing Group 1). */
14798/*! @{ */
14799#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU)
14800#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TxDqDlyTg1_rn_px_SHIFT (0U)
14801#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TxDqDlyTg1_rn_px(x) \
14802 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TxDqDlyTg1_rn_px_SHIFT)) & \
14803 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P1_TxDqDlyTg1_rn_px_MASK)
14804/*! @} */
14805
14806/*! @name TXDQDLYTG2_R0_P1 - Write DQ Delay (Timing Group 2). */
14807/*! @{ */
14808#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU)
14809#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TxDqDlyTg2_rn_px_SHIFT (0U)
14810#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TxDqDlyTg2_rn_px(x) \
14811 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TxDqDlyTg2_rn_px_SHIFT)) & \
14812 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P1_TxDqDlyTg2_rn_px_MASK)
14813/*! @} */
14814
14815/*! @name TXDQDLYTG3_R0_P1 - Write DQ Delay (Timing Group 3). */
14816/*! @{ */
14817#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU)
14818#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TxDqDlyTg3_rn_px_SHIFT (0U)
14819#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TxDqDlyTg3_rn_px(x) \
14820 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TxDqDlyTg3_rn_px_SHIFT)) & \
14821 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P1_TxDqDlyTg3_rn_px_MASK)
14822/*! @} */
14823
14824/*! @name TXDQSDLYTG0_U0_P1 - Write DQS Delay (Timing Group DEST=0). */
14825/*! @{ */
14826#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TxDqsDlyTg0_un_px_MASK (0x3FFU)
14827#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TxDqsDlyTg0_un_px_SHIFT (0U)
14828#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TxDqsDlyTg0_un_px(x) \
14829 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TxDqsDlyTg0_un_px_SHIFT)) & \
14830 DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P1_TxDqsDlyTg0_un_px_MASK)
14831/*! @} */
14832
14833/*! @name TXDQSDLYTG1_U0_P1 - Write DQS Delay (Timing Group DEST=1). */
14834/*! @{ */
14835#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TxDqsDlyTg1_un_px_MASK (0x3FFU)
14836#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TxDqsDlyTg1_un_px_SHIFT (0U)
14837#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TxDqsDlyTg1_un_px(x) \
14838 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TxDqsDlyTg1_un_px_SHIFT)) & \
14839 DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P1_TxDqsDlyTg1_un_px_MASK)
14840/*! @} */
14841
14842/*! @name TXDQSDLYTG2_U0_P1 - Write DQS Delay (Timing Group DEST=2). */
14843/*! @{ */
14844#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TxDqsDlyTg2_un_px_MASK (0x3FFU)
14845#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TxDqsDlyTg2_un_px_SHIFT (0U)
14846#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TxDqsDlyTg2_un_px(x) \
14847 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TxDqsDlyTg2_un_px_SHIFT)) & \
14848 DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P1_TxDqsDlyTg2_un_px_MASK)
14849/*! @} */
14850
14851/*! @name TXDQSDLYTG3_U0_P1 - Write DQS Delay (Timing Group DEST=3). */
14852/*! @{ */
14853#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TxDqsDlyTg3_un_px_MASK (0x3FFU)
14854#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TxDqsDlyTg3_un_px_SHIFT (0U)
14855#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TxDqsDlyTg3_un_px(x) \
14856 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TxDqsDlyTg3_un_px_SHIFT)) & \
14857 DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P1_TxDqsDlyTg3_un_px_MASK)
14858/*! @} */
14859
14860/*! @name TXIMPEDANCECTRL0_B1_P1 - Data TX impedance controls */
14861/*! @{ */
14862#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqP_MASK (0x3FU)
14863#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqP_SHIFT (0U)
14864#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqP(x) \
14865 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqP_SHIFT)) & \
14866 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqP_MASK)
14867#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqN_MASK (0xFC0U)
14868#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqN_SHIFT (6U)
14869#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqN(x) \
14870 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqN_SHIFT)) & \
14871 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P1_DrvStrenDqN_MASK)
14872/*! @} */
14873
14874/*! @name DQDQSRCVCNTRL_B1_P1 - Dq/Dqs receiver control */
14875/*! @{ */
14876#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SelAnalogVref_MASK (0x1U)
14877#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SelAnalogVref_SHIFT (0U)
14878#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SelAnalogVref(x) \
14879 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SelAnalogVref_SHIFT)) & \
14880 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_SelAnalogVref_MASK)
14881#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_ExtVrefRange_MASK (0x2U)
14882#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_ExtVrefRange_SHIFT (1U)
14883#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_ExtVrefRange(x) \
14884 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_ExtVrefRange_SHIFT)) & \
14885 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_ExtVrefRange_MASK)
14886#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DfeCtrl_MASK (0xCU)
14887#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DfeCtrl_SHIFT (2U)
14888#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DfeCtrl(x) \
14889 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DfeCtrl_SHIFT)) & \
14890 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_DfeCtrl_MASK)
14891#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MajorModeDbyte_MASK (0x70U)
14892#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MajorModeDbyte_SHIFT (4U)
14893#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MajorModeDbyte(x) \
14894 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MajorModeDbyte_SHIFT)) & \
14895 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_MajorModeDbyte_MASK)
14896#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GainCurrAdj_MASK (0xF80U)
14897#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GainCurrAdj_SHIFT (7U)
14898#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GainCurrAdj(x) \
14899 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GainCurrAdj_SHIFT)) & \
14900 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P1_GainCurrAdj_MASK)
14901/*! @} */
14902
14903/*! @name TXIMPEDANCECTRL1_B1_P1 - TX impedance controls */
14904/*! @{ */
14905#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqP_MASK (0x3FU)
14906#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqP_SHIFT (0U)
14907#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqP(x) \
14908 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqP_SHIFT)) & \
14909 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqP_MASK)
14910#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqN_MASK (0xFC0U)
14911#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqN_SHIFT (6U)
14912#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqN(x) \
14913 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqN_SHIFT)) & \
14914 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P1_DrvStrenFSDqN_MASK)
14915/*! @} */
14916
14917/*! @name TXIMPEDANCECTRL2_B1_P1 - TX equalization impedance controls */
14918/*! @{ */
14919#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQHiDqP_MASK (0x3FU)
14920#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQHiDqP_SHIFT (0U)
14921#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQHiDqP(x) \
14922 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQHiDqP_SHIFT)) & \
14923 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQHiDqP_MASK)
14924#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQLoDqN_MASK (0xFC0U)
14925#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQLoDqN_SHIFT (6U)
14926#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQLoDqN(x) \
14927 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQLoDqN_SHIFT)) & \
14928 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P1_DrvStrenEQLoDqN_MASK)
14929/*! @} */
14930
14931/*! @name TXODTDRVSTREN_B1_P1 - TX ODT driver strength control */
14932/*! @{ */
14933#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenP_MASK (0x3FU)
14934#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenP_SHIFT (0U)
14935#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenP(x) \
14936 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenP_SHIFT)) & \
14937 DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenP_MASK)
14938#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenN_MASK (0xFC0U)
14939#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenN_SHIFT (6U)
14940#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenN(x) \
14941 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenN_SHIFT)) & \
14942 DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P1_ODTStrenN_MASK)
14943/*! @} */
14944
14945/*! @name TXSLEWRATE_B1_P1 - TX slew rate controls */
14946/*! @{ */
14947#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreP_MASK (0xFU)
14948#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreP_SHIFT (0U)
14949#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreP(x) \
14950 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreP_SHIFT)) & \
14951 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreP_MASK)
14952#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreN_MASK (0xF0U)
14953#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreN_SHIFT (4U)
14954#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreN(x) \
14955 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreN_SHIFT)) & \
14956 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreN_MASK)
14957#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreDrvMode_MASK (0x700U)
14958#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreDrvMode_SHIFT (8U)
14959#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreDrvMode(x) \
14960 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreDrvMode_SHIFT)) & \
14961 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P1_TxPreDrvMode_MASK)
14962/*! @} */
14963
14964/*! @name RXENDLYTG0_U1_P1 - Trained Receive Enable Delay (For Timing Group 0) */
14965/*! @{ */
14966#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RxEnDlyTg0_un_px_MASK (0x7FFU)
14967#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RxEnDlyTg0_un_px_SHIFT (0U)
14968#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RxEnDlyTg0_un_px(x) \
14969 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RxEnDlyTg0_un_px_SHIFT)) & \
14970 DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P1_RxEnDlyTg0_un_px_MASK)
14971/*! @} */
14972
14973/*! @name RXENDLYTG1_U1_P1 - Trained Receive Enable Delay (For Timing Group 1) */
14974/*! @{ */
14975#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RxEnDlyTg1_un_px_MASK (0x7FFU)
14976#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RxEnDlyTg1_un_px_SHIFT (0U)
14977#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RxEnDlyTg1_un_px(x) \
14978 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RxEnDlyTg1_un_px_SHIFT)) & \
14979 DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P1_RxEnDlyTg1_un_px_MASK)
14980/*! @} */
14981
14982/*! @name RXENDLYTG2_U1_P1 - Trained Receive Enable Delay (For Timing Group 2) */
14983/*! @{ */
14984#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RxEnDlyTg2_un_px_MASK (0x7FFU)
14985#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RxEnDlyTg2_un_px_SHIFT (0U)
14986#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RxEnDlyTg2_un_px(x) \
14987 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RxEnDlyTg2_un_px_SHIFT)) & \
14988 DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P1_RxEnDlyTg2_un_px_MASK)
14989/*! @} */
14990
14991/*! @name RXENDLYTG3_U1_P1 - Trained Receive Enable Delay (For Timing Group 3) */
14992/*! @{ */
14993#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RxEnDlyTg3_un_px_MASK (0x7FFU)
14994#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RxEnDlyTg3_un_px_SHIFT (0U)
14995#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RxEnDlyTg3_un_px(x) \
14996 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RxEnDlyTg3_un_px_SHIFT)) & \
14997 DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P1_RxEnDlyTg3_un_px_MASK)
14998/*! @} */
14999
15000/*! @name RXCLKDLYTG0_U1_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
15001/*! @{ */
15002#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RxClkDlyTg0_un_px_MASK (0x3FU)
15003#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RxClkDlyTg0_un_px_SHIFT (0U)
15004#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RxClkDlyTg0_un_px(x) \
15005 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RxClkDlyTg0_un_px_SHIFT)) & \
15006 DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P1_RxClkDlyTg0_un_px_MASK)
15007/*! @} */
15008
15009/*! @name RXCLKDLYTG1_U1_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
15010/*! @{ */
15011#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RxClkDlyTg1_un_px_MASK (0x3FU)
15012#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RxClkDlyTg1_un_px_SHIFT (0U)
15013#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RxClkDlyTg1_un_px(x) \
15014 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RxClkDlyTg1_un_px_SHIFT)) & \
15015 DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P1_RxClkDlyTg1_un_px_MASK)
15016/*! @} */
15017
15018/*! @name RXCLKDLYTG2_U1_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
15019/*! @{ */
15020#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RxClkDlyTg2_un_px_MASK (0x3FU)
15021#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RxClkDlyTg2_un_px_SHIFT (0U)
15022#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RxClkDlyTg2_un_px(x) \
15023 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RxClkDlyTg2_un_px_SHIFT)) & \
15024 DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P1_RxClkDlyTg2_un_px_MASK)
15025/*! @} */
15026
15027/*! @name RXCLKDLYTG3_U1_P1 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
15028/*! @{ */
15029#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RxClkDlyTg3_un_px_MASK (0x3FU)
15030#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RxClkDlyTg3_un_px_SHIFT (0U)
15031#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RxClkDlyTg3_un_px(x) \
15032 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RxClkDlyTg3_un_px_SHIFT)) & \
15033 DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P1_RxClkDlyTg3_un_px_MASK)
15034/*! @} */
15035
15036/*! @name RXCLKCDLYTG0_U1_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
15037/*! @{ */
15038#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RxClkcDlyTg0_un_px_MASK (0x3FU)
15039#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RxClkcDlyTg0_un_px_SHIFT (0U)
15040#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RxClkcDlyTg0_un_px(x) \
15041 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RxClkcDlyTg0_un_px_SHIFT)) & \
15042 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P1_RxClkcDlyTg0_un_px_MASK)
15043/*! @} */
15044
15045/*! @name RXCLKCDLYTG1_U1_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
15046/*! @{ */
15047#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RxClkcDlyTg1_un_px_MASK (0x3FU)
15048#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RxClkcDlyTg1_un_px_SHIFT (0U)
15049#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RxClkcDlyTg1_un_px(x) \
15050 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RxClkcDlyTg1_un_px_SHIFT)) & \
15051 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P1_RxClkcDlyTg1_un_px_MASK)
15052/*! @} */
15053
15054/*! @name RXCLKCDLYTG2_U1_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
15055/*! @{ */
15056#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RxClkcDlyTg2_un_px_MASK (0x3FU)
15057#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RxClkcDlyTg2_un_px_SHIFT (0U)
15058#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RxClkcDlyTg2_un_px(x) \
15059 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RxClkcDlyTg2_un_px_SHIFT)) & \
15060 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P1_RxClkcDlyTg2_un_px_MASK)
15061/*! @} */
15062
15063/*! @name RXCLKCDLYTG3_U1_P1 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
15064/*! @{ */
15065#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RxClkcDlyTg3_un_px_MASK (0x3FU)
15066#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RxClkcDlyTg3_un_px_SHIFT (0U)
15067#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RxClkcDlyTg3_un_px(x) \
15068 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RxClkcDlyTg3_un_px_SHIFT)) & \
15069 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P1_RxClkcDlyTg3_un_px_MASK)
15070/*! @} */
15071
15072/*! @name TXDQDLYTG0_R1_P1 - Write DQ Delay (Timing Group 0). */
15073/*! @{ */
15074#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU)
15075#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TxDqDlyTg0_rn_px_SHIFT (0U)
15076#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TxDqDlyTg0_rn_px(x) \
15077 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TxDqDlyTg0_rn_px_SHIFT)) & \
15078 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P1_TxDqDlyTg0_rn_px_MASK)
15079/*! @} */
15080
15081/*! @name TXDQDLYTG1_R1_P1 - Write DQ Delay (Timing Group 1). */
15082/*! @{ */
15083#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU)
15084#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TxDqDlyTg1_rn_px_SHIFT (0U)
15085#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TxDqDlyTg1_rn_px(x) \
15086 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TxDqDlyTg1_rn_px_SHIFT)) & \
15087 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P1_TxDqDlyTg1_rn_px_MASK)
15088/*! @} */
15089
15090/*! @name TXDQDLYTG2_R1_P1 - Write DQ Delay (Timing Group 2). */
15091/*! @{ */
15092#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU)
15093#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TxDqDlyTg2_rn_px_SHIFT (0U)
15094#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TxDqDlyTg2_rn_px(x) \
15095 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TxDqDlyTg2_rn_px_SHIFT)) & \
15096 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P1_TxDqDlyTg2_rn_px_MASK)
15097/*! @} */
15098
15099/*! @name TXDQDLYTG3_R1_P1 - Write DQ Delay (Timing Group 3). */
15100/*! @{ */
15101#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU)
15102#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TxDqDlyTg3_rn_px_SHIFT (0U)
15103#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TxDqDlyTg3_rn_px(x) \
15104 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TxDqDlyTg3_rn_px_SHIFT)) & \
15105 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P1_TxDqDlyTg3_rn_px_MASK)
15106/*! @} */
15107
15108/*! @name TXDQSDLYTG0_U1_P1 - Write DQS Delay (Timing Group DEST=0). */
15109/*! @{ */
15110#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TxDqsDlyTg0_un_px_MASK (0x3FFU)
15111#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TxDqsDlyTg0_un_px_SHIFT (0U)
15112#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TxDqsDlyTg0_un_px(x) \
15113 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TxDqsDlyTg0_un_px_SHIFT)) & \
15114 DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P1_TxDqsDlyTg0_un_px_MASK)
15115/*! @} */
15116
15117/*! @name TXDQSDLYTG1_U1_P1 - Write DQS Delay (Timing Group DEST=1). */
15118/*! @{ */
15119#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TxDqsDlyTg1_un_px_MASK (0x3FFU)
15120#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TxDqsDlyTg1_un_px_SHIFT (0U)
15121#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TxDqsDlyTg1_un_px(x) \
15122 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TxDqsDlyTg1_un_px_SHIFT)) & \
15123 DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P1_TxDqsDlyTg1_un_px_MASK)
15124/*! @} */
15125
15126/*! @name TXDQSDLYTG2_U1_P1 - Write DQS Delay (Timing Group DEST=2). */
15127/*! @{ */
15128#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TxDqsDlyTg2_un_px_MASK (0x3FFU)
15129#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TxDqsDlyTg2_un_px_SHIFT (0U)
15130#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TxDqsDlyTg2_un_px(x) \
15131 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TxDqsDlyTg2_un_px_SHIFT)) & \
15132 DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P1_TxDqsDlyTg2_un_px_MASK)
15133/*! @} */
15134
15135/*! @name TXDQSDLYTG3_U1_P1 - Write DQS Delay (Timing Group DEST=3). */
15136/*! @{ */
15137#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TxDqsDlyTg3_un_px_MASK (0x3FFU)
15138#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TxDqsDlyTg3_un_px_SHIFT (0U)
15139#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TxDqsDlyTg3_un_px(x) \
15140 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TxDqsDlyTg3_un_px_SHIFT)) & \
15141 DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P1_TxDqsDlyTg3_un_px_MASK)
15142/*! @} */
15143
15144/*! @name TXDQDLYTG0_R2_P1 - Write DQ Delay (Timing Group 0). */
15145/*! @{ */
15146#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU)
15147#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TxDqDlyTg0_rn_px_SHIFT (0U)
15148#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TxDqDlyTg0_rn_px(x) \
15149 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TxDqDlyTg0_rn_px_SHIFT)) & \
15150 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P1_TxDqDlyTg0_rn_px_MASK)
15151/*! @} */
15152
15153/*! @name TXDQDLYTG1_R2_P1 - Write DQ Delay (Timing Group 1). */
15154/*! @{ */
15155#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU)
15156#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TxDqDlyTg1_rn_px_SHIFT (0U)
15157#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TxDqDlyTg1_rn_px(x) \
15158 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TxDqDlyTg1_rn_px_SHIFT)) & \
15159 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P1_TxDqDlyTg1_rn_px_MASK)
15160/*! @} */
15161
15162/*! @name TXDQDLYTG2_R2_P1 - Write DQ Delay (Timing Group 2). */
15163/*! @{ */
15164#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU)
15165#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TxDqDlyTg2_rn_px_SHIFT (0U)
15166#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TxDqDlyTg2_rn_px(x) \
15167 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TxDqDlyTg2_rn_px_SHIFT)) & \
15168 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P1_TxDqDlyTg2_rn_px_MASK)
15169/*! @} */
15170
15171/*! @name TXDQDLYTG3_R2_P1 - Write DQ Delay (Timing Group 3). */
15172/*! @{ */
15173#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU)
15174#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TxDqDlyTg3_rn_px_SHIFT (0U)
15175#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TxDqDlyTg3_rn_px(x) \
15176 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TxDqDlyTg3_rn_px_SHIFT)) & \
15177 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P1_TxDqDlyTg3_rn_px_MASK)
15178/*! @} */
15179
15180/*! @name TXDQDLYTG0_R3_P1 - Write DQ Delay (Timing Group 0). */
15181/*! @{ */
15182#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU)
15183#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TxDqDlyTg0_rn_px_SHIFT (0U)
15184#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TxDqDlyTg0_rn_px(x) \
15185 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TxDqDlyTg0_rn_px_SHIFT)) & \
15186 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P1_TxDqDlyTg0_rn_px_MASK)
15187/*! @} */
15188
15189/*! @name TXDQDLYTG1_R3_P1 - Write DQ Delay (Timing Group 1). */
15190/*! @{ */
15191#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU)
15192#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TxDqDlyTg1_rn_px_SHIFT (0U)
15193#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TxDqDlyTg1_rn_px(x) \
15194 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TxDqDlyTg1_rn_px_SHIFT)) & \
15195 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P1_TxDqDlyTg1_rn_px_MASK)
15196/*! @} */
15197
15198/*! @name TXDQDLYTG2_R3_P1 - Write DQ Delay (Timing Group 2). */
15199/*! @{ */
15200#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU)
15201#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TxDqDlyTg2_rn_px_SHIFT (0U)
15202#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TxDqDlyTg2_rn_px(x) \
15203 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TxDqDlyTg2_rn_px_SHIFT)) & \
15204 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P1_TxDqDlyTg2_rn_px_MASK)
15205/*! @} */
15206
15207/*! @name TXDQDLYTG3_R3_P1 - Write DQ Delay (Timing Group 3). */
15208/*! @{ */
15209#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU)
15210#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TxDqDlyTg3_rn_px_SHIFT (0U)
15211#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TxDqDlyTg3_rn_px(x) \
15212 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TxDqDlyTg3_rn_px_SHIFT)) & \
15213 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P1_TxDqDlyTg3_rn_px_MASK)
15214/*! @} */
15215
15216/*! @name TXDQDLYTG0_R4_P1 - Write DQ Delay (Timing Group 0). */
15217/*! @{ */
15218#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU)
15219#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TxDqDlyTg0_rn_px_SHIFT (0U)
15220#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TxDqDlyTg0_rn_px(x) \
15221 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TxDqDlyTg0_rn_px_SHIFT)) & \
15222 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P1_TxDqDlyTg0_rn_px_MASK)
15223/*! @} */
15224
15225/*! @name TXDQDLYTG1_R4_P1 - Write DQ Delay (Timing Group 1). */
15226/*! @{ */
15227#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU)
15228#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TxDqDlyTg1_rn_px_SHIFT (0U)
15229#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TxDqDlyTg1_rn_px(x) \
15230 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TxDqDlyTg1_rn_px_SHIFT)) & \
15231 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P1_TxDqDlyTg1_rn_px_MASK)
15232/*! @} */
15233
15234/*! @name TXDQDLYTG2_R4_P1 - Write DQ Delay (Timing Group 2). */
15235/*! @{ */
15236#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU)
15237#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TxDqDlyTg2_rn_px_SHIFT (0U)
15238#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TxDqDlyTg2_rn_px(x) \
15239 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TxDqDlyTg2_rn_px_SHIFT)) & \
15240 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P1_TxDqDlyTg2_rn_px_MASK)
15241/*! @} */
15242
15243/*! @name TXDQDLYTG3_R4_P1 - Write DQ Delay (Timing Group 3). */
15244/*! @{ */
15245#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU)
15246#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TxDqDlyTg3_rn_px_SHIFT (0U)
15247#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TxDqDlyTg3_rn_px(x) \
15248 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TxDqDlyTg3_rn_px_SHIFT)) & \
15249 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P1_TxDqDlyTg3_rn_px_MASK)
15250/*! @} */
15251
15252/*! @name TXDQDLYTG0_R5_P1 - Write DQ Delay (Timing Group 0). */
15253/*! @{ */
15254#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU)
15255#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TxDqDlyTg0_rn_px_SHIFT (0U)
15256#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TxDqDlyTg0_rn_px(x) \
15257 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TxDqDlyTg0_rn_px_SHIFT)) & \
15258 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P1_TxDqDlyTg0_rn_px_MASK)
15259/*! @} */
15260
15261/*! @name TXDQDLYTG1_R5_P1 - Write DQ Delay (Timing Group 1). */
15262/*! @{ */
15263#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU)
15264#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TxDqDlyTg1_rn_px_SHIFT (0U)
15265#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TxDqDlyTg1_rn_px(x) \
15266 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TxDqDlyTg1_rn_px_SHIFT)) & \
15267 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P1_TxDqDlyTg1_rn_px_MASK)
15268/*! @} */
15269
15270/*! @name TXDQDLYTG2_R5_P1 - Write DQ Delay (Timing Group 2). */
15271/*! @{ */
15272#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU)
15273#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TxDqDlyTg2_rn_px_SHIFT (0U)
15274#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TxDqDlyTg2_rn_px(x) \
15275 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TxDqDlyTg2_rn_px_SHIFT)) & \
15276 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P1_TxDqDlyTg2_rn_px_MASK)
15277/*! @} */
15278
15279/*! @name TXDQDLYTG3_R5_P1 - Write DQ Delay (Timing Group 3). */
15280/*! @{ */
15281#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU)
15282#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TxDqDlyTg3_rn_px_SHIFT (0U)
15283#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TxDqDlyTg3_rn_px(x) \
15284 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TxDqDlyTg3_rn_px_SHIFT)) & \
15285 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P1_TxDqDlyTg3_rn_px_MASK)
15286/*! @} */
15287
15288/*! @name TXDQDLYTG0_R6_P1 - Write DQ Delay (Timing Group 0). */
15289/*! @{ */
15290#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU)
15291#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TxDqDlyTg0_rn_px_SHIFT (0U)
15292#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TxDqDlyTg0_rn_px(x) \
15293 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TxDqDlyTg0_rn_px_SHIFT)) & \
15294 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P1_TxDqDlyTg0_rn_px_MASK)
15295/*! @} */
15296
15297/*! @name TXDQDLYTG1_R6_P1 - Write DQ Delay (Timing Group 1). */
15298/*! @{ */
15299#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU)
15300#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TxDqDlyTg1_rn_px_SHIFT (0U)
15301#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TxDqDlyTg1_rn_px(x) \
15302 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TxDqDlyTg1_rn_px_SHIFT)) & \
15303 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P1_TxDqDlyTg1_rn_px_MASK)
15304/*! @} */
15305
15306/*! @name TXDQDLYTG2_R6_P1 - Write DQ Delay (Timing Group 2). */
15307/*! @{ */
15308#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU)
15309#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TxDqDlyTg2_rn_px_SHIFT (0U)
15310#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TxDqDlyTg2_rn_px(x) \
15311 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TxDqDlyTg2_rn_px_SHIFT)) & \
15312 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P1_TxDqDlyTg2_rn_px_MASK)
15313/*! @} */
15314
15315/*! @name TXDQDLYTG3_R6_P1 - Write DQ Delay (Timing Group 3). */
15316/*! @{ */
15317#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU)
15318#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TxDqDlyTg3_rn_px_SHIFT (0U)
15319#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TxDqDlyTg3_rn_px(x) \
15320 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TxDqDlyTg3_rn_px_SHIFT)) & \
15321 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P1_TxDqDlyTg3_rn_px_MASK)
15322/*! @} */
15323
15324/*! @name TXDQDLYTG0_R7_P1 - Write DQ Delay (Timing Group 0). */
15325/*! @{ */
15326#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU)
15327#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TxDqDlyTg0_rn_px_SHIFT (0U)
15328#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TxDqDlyTg0_rn_px(x) \
15329 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TxDqDlyTg0_rn_px_SHIFT)) & \
15330 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P1_TxDqDlyTg0_rn_px_MASK)
15331/*! @} */
15332
15333/*! @name TXDQDLYTG1_R7_P1 - Write DQ Delay (Timing Group 1). */
15334/*! @{ */
15335#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU)
15336#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TxDqDlyTg1_rn_px_SHIFT (0U)
15337#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TxDqDlyTg1_rn_px(x) \
15338 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TxDqDlyTg1_rn_px_SHIFT)) & \
15339 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P1_TxDqDlyTg1_rn_px_MASK)
15340/*! @} */
15341
15342/*! @name TXDQDLYTG2_R7_P1 - Write DQ Delay (Timing Group 2). */
15343/*! @{ */
15344#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU)
15345#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TxDqDlyTg2_rn_px_SHIFT (0U)
15346#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TxDqDlyTg2_rn_px(x) \
15347 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TxDqDlyTg2_rn_px_SHIFT)) & \
15348 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P1_TxDqDlyTg2_rn_px_MASK)
15349/*! @} */
15350
15351/*! @name TXDQDLYTG3_R7_P1 - Write DQ Delay (Timing Group 3). */
15352/*! @{ */
15353#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU)
15354#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TxDqDlyTg3_rn_px_SHIFT (0U)
15355#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TxDqDlyTg3_rn_px(x) \
15356 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TxDqDlyTg3_rn_px_SHIFT)) & \
15357 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P1_TxDqDlyTg3_rn_px_MASK)
15358/*! @} */
15359
15360/*! @name TXDQDLYTG0_R8_P1 - Write DQ Delay (Timing Group 0). */
15361/*! @{ */
15362#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TxDqDlyTg0_rn_px_MASK (0x1FFU)
15363#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TxDqDlyTg0_rn_px_SHIFT (0U)
15364#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TxDqDlyTg0_rn_px(x) \
15365 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TxDqDlyTg0_rn_px_SHIFT)) & \
15366 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P1_TxDqDlyTg0_rn_px_MASK)
15367/*! @} */
15368
15369/*! @name TXDQDLYTG1_R8_P1 - Write DQ Delay (Timing Group 1). */
15370/*! @{ */
15371#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TxDqDlyTg1_rn_px_MASK (0x1FFU)
15372#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TxDqDlyTg1_rn_px_SHIFT (0U)
15373#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TxDqDlyTg1_rn_px(x) \
15374 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TxDqDlyTg1_rn_px_SHIFT)) & \
15375 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P1_TxDqDlyTg1_rn_px_MASK)
15376/*! @} */
15377
15378/*! @name TXDQDLYTG2_R8_P1 - Write DQ Delay (Timing Group 2). */
15379/*! @{ */
15380#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TxDqDlyTg2_rn_px_MASK (0x1FFU)
15381#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TxDqDlyTg2_rn_px_SHIFT (0U)
15382#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TxDqDlyTg2_rn_px(x) \
15383 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TxDqDlyTg2_rn_px_SHIFT)) & \
15384 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P1_TxDqDlyTg2_rn_px_MASK)
15385/*! @} */
15386
15387/*! @name TXDQDLYTG3_R8_P1 - Write DQ Delay (Timing Group 3). */
15388/*! @{ */
15389#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TxDqDlyTg3_rn_px_MASK (0x1FFU)
15390#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TxDqDlyTg3_rn_px_SHIFT (0U)
15391#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TxDqDlyTg3_rn_px(x) \
15392 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TxDqDlyTg3_rn_px_SHIFT)) & \
15393 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P1_TxDqDlyTg3_rn_px_MASK)
15394/*! @} */
15395
15396/*! @name DFIMRL_P2 - DFI MaxReadLatency */
15397/*! @{ */
15398#define DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_p2_MASK (0x1FU)
15399#define DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_p2_SHIFT (0U)
15400#define DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_p2(x) \
15401 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_p2_SHIFT)) & \
15402 DWC_DDRPHYA_DBYTE_DFIMRL_P2_DFIMRL_p2_MASK)
15403/*! @} */
15404
15405/*! @name TXIMPEDANCECTRL0_B0_P2 - Data TX impedance controls */
15406/*! @{ */
15407#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqP_MASK (0x3FU)
15408#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqP_SHIFT (0U)
15409#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqP(x) \
15410 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqP_SHIFT)) & \
15411 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqP_MASK)
15412#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqN_MASK (0xFC0U)
15413#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqN_SHIFT (6U)
15414#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqN(x) \
15415 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqN_SHIFT)) & \
15416 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P2_DrvStrenDqN_MASK)
15417/*! @} */
15418
15419/*! @name DQDQSRCVCNTRL_B0_P2 - Dq/Dqs receiver control */
15420/*! @{ */
15421#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SelAnalogVref_MASK (0x1U)
15422#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SelAnalogVref_SHIFT (0U)
15423#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SelAnalogVref(x) \
15424 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SelAnalogVref_SHIFT)) & \
15425 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_SelAnalogVref_MASK)
15426#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_ExtVrefRange_MASK (0x2U)
15427#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_ExtVrefRange_SHIFT (1U)
15428#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_ExtVrefRange(x) \
15429 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_ExtVrefRange_SHIFT)) & \
15430 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_ExtVrefRange_MASK)
15431#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DfeCtrl_MASK (0xCU)
15432#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DfeCtrl_SHIFT (2U)
15433#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DfeCtrl(x) \
15434 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DfeCtrl_SHIFT)) & \
15435 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_DfeCtrl_MASK)
15436#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MajorModeDbyte_MASK (0x70U)
15437#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MajorModeDbyte_SHIFT (4U)
15438#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MajorModeDbyte(x) \
15439 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MajorModeDbyte_SHIFT)) & \
15440 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_MajorModeDbyte_MASK)
15441#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GainCurrAdj_MASK (0xF80U)
15442#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GainCurrAdj_SHIFT (7U)
15443#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GainCurrAdj(x) \
15444 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GainCurrAdj_SHIFT)) & \
15445 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P2_GainCurrAdj_MASK)
15446/*! @} */
15447
15448/*! @name TXEQUALIZATIONMODE_P2 - Tx dq driver equalization mode controls. */
15449/*! @{ */
15450#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TxEqMode_MASK (0x3U)
15451#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TxEqMode_SHIFT (0U)
15452#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TxEqMode(x) \
15453 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TxEqMode_SHIFT)) & \
15454 DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P2_TxEqMode_MASK)
15455/*! @} */
15456
15457/*! @name TXIMPEDANCECTRL1_B0_P2 - TX impedance controls */
15458/*! @{ */
15459#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqP_MASK (0x3FU)
15460#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqP_SHIFT (0U)
15461#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqP(x) \
15462 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqP_SHIFT)) & \
15463 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqP_MASK)
15464#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqN_MASK (0xFC0U)
15465#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqN_SHIFT (6U)
15466#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqN(x) \
15467 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqN_SHIFT)) & \
15468 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P2_DrvStrenFSDqN_MASK)
15469/*! @} */
15470
15471/*! @name TXIMPEDANCECTRL2_B0_P2 - TX equalization impedance controls */
15472/*! @{ */
15473#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQHiDqP_MASK (0x3FU)
15474#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQHiDqP_SHIFT (0U)
15475#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQHiDqP(x) \
15476 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQHiDqP_SHIFT)) & \
15477 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQHiDqP_MASK)
15478#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQLoDqN_MASK (0xFC0U)
15479#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQLoDqN_SHIFT (6U)
15480#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQLoDqN(x) \
15481 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQLoDqN_SHIFT)) & \
15482 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P2_DrvStrenEQLoDqN_MASK)
15483/*! @} */
15484
15485/*! @name DQDQSRCVCNTRL2_P2 - Dq/Dqs receiver control */
15486/*! @{ */
15487#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_EnRxAgressivePDR_MASK (0x1U)
15488#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_EnRxAgressivePDR_SHIFT (0U)
15489#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_EnRxAgressivePDR(x) \
15490 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_EnRxAgressivePDR_SHIFT)) & \
15491 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P2_EnRxAgressivePDR_MASK)
15492/*! @} */
15493
15494/*! @name TXODTDRVSTREN_B0_P2 - TX ODT driver strength control */
15495/*! @{ */
15496#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenP_MASK (0x3FU)
15497#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenP_SHIFT (0U)
15498#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenP(x) \
15499 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenP_SHIFT)) & \
15500 DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenP_MASK)
15501#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenN_MASK (0xFC0U)
15502#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenN_SHIFT (6U)
15503#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenN(x) \
15504 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenN_SHIFT)) & \
15505 DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P2_ODTStrenN_MASK)
15506/*! @} */
15507
15508/*! @name TXSLEWRATE_B0_P2 - TX slew rate controls */
15509/*! @{ */
15510#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreP_MASK (0xFU)
15511#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreP_SHIFT (0U)
15512#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreP(x) \
15513 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreP_SHIFT)) & \
15514 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreP_MASK)
15515#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreN_MASK (0xF0U)
15516#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreN_SHIFT (4U)
15517#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreN(x) \
15518 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreN_SHIFT)) & \
15519 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreN_MASK)
15520#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreDrvMode_MASK (0x700U)
15521#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreDrvMode_SHIFT (8U)
15522#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreDrvMode(x) \
15523 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreDrvMode_SHIFT)) & \
15524 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P2_TxPreDrvMode_MASK)
15525/*! @} */
15526
15527/*! @name RXENDLYTG0_U0_P2 - Trained Receive Enable Delay (For Timing Group 0) */
15528/*! @{ */
15529#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RxEnDlyTg0_un_px_MASK (0x7FFU)
15530#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RxEnDlyTg0_un_px_SHIFT (0U)
15531#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RxEnDlyTg0_un_px(x) \
15532 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RxEnDlyTg0_un_px_SHIFT)) & \
15533 DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P2_RxEnDlyTg0_un_px_MASK)
15534/*! @} */
15535
15536/*! @name RXENDLYTG1_U0_P2 - Trained Receive Enable Delay (For Timing Group 1) */
15537/*! @{ */
15538#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RxEnDlyTg1_un_px_MASK (0x7FFU)
15539#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RxEnDlyTg1_un_px_SHIFT (0U)
15540#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RxEnDlyTg1_un_px(x) \
15541 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RxEnDlyTg1_un_px_SHIFT)) & \
15542 DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P2_RxEnDlyTg1_un_px_MASK)
15543/*! @} */
15544
15545/*! @name RXENDLYTG2_U0_P2 - Trained Receive Enable Delay (For Timing Group 2) */
15546/*! @{ */
15547#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RxEnDlyTg2_un_px_MASK (0x7FFU)
15548#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RxEnDlyTg2_un_px_SHIFT (0U)
15549#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RxEnDlyTg2_un_px(x) \
15550 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RxEnDlyTg2_un_px_SHIFT)) & \
15551 DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P2_RxEnDlyTg2_un_px_MASK)
15552/*! @} */
15553
15554/*! @name RXENDLYTG3_U0_P2 - Trained Receive Enable Delay (For Timing Group 3) */
15555/*! @{ */
15556#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RxEnDlyTg3_un_px_MASK (0x7FFU)
15557#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RxEnDlyTg3_un_px_SHIFT (0U)
15558#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RxEnDlyTg3_un_px(x) \
15559 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RxEnDlyTg3_un_px_SHIFT)) & \
15560 DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P2_RxEnDlyTg3_un_px_MASK)
15561/*! @} */
15562
15563/*! @name RXCLKDLYTG0_U0_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
15564/*! @{ */
15565#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RxClkDlyTg0_un_px_MASK (0x3FU)
15566#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RxClkDlyTg0_un_px_SHIFT (0U)
15567#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RxClkDlyTg0_un_px(x) \
15568 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RxClkDlyTg0_un_px_SHIFT)) & \
15569 DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P2_RxClkDlyTg0_un_px_MASK)
15570/*! @} */
15571
15572/*! @name RXCLKDLYTG1_U0_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
15573/*! @{ */
15574#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RxClkDlyTg1_un_px_MASK (0x3FU)
15575#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RxClkDlyTg1_un_px_SHIFT (0U)
15576#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RxClkDlyTg1_un_px(x) \
15577 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RxClkDlyTg1_un_px_SHIFT)) & \
15578 DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P2_RxClkDlyTg1_un_px_MASK)
15579/*! @} */
15580
15581/*! @name RXCLKDLYTG2_U0_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
15582/*! @{ */
15583#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RxClkDlyTg2_un_px_MASK (0x3FU)
15584#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RxClkDlyTg2_un_px_SHIFT (0U)
15585#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RxClkDlyTg2_un_px(x) \
15586 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RxClkDlyTg2_un_px_SHIFT)) & \
15587 DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P2_RxClkDlyTg2_un_px_MASK)
15588/*! @} */
15589
15590/*! @name RXCLKDLYTG3_U0_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
15591/*! @{ */
15592#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RxClkDlyTg3_un_px_MASK (0x3FU)
15593#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RxClkDlyTg3_un_px_SHIFT (0U)
15594#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RxClkDlyTg3_un_px(x) \
15595 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RxClkDlyTg3_un_px_SHIFT)) & \
15596 DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P2_RxClkDlyTg3_un_px_MASK)
15597/*! @} */
15598
15599/*! @name RXCLKCDLYTG0_U0_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
15600/*! @{ */
15601#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RxClkcDlyTg0_un_px_MASK (0x3FU)
15602#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RxClkcDlyTg0_un_px_SHIFT (0U)
15603#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RxClkcDlyTg0_un_px(x) \
15604 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RxClkcDlyTg0_un_px_SHIFT)) & \
15605 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P2_RxClkcDlyTg0_un_px_MASK)
15606/*! @} */
15607
15608/*! @name RXCLKCDLYTG1_U0_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
15609/*! @{ */
15610#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RxClkcDlyTg1_un_px_MASK (0x3FU)
15611#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RxClkcDlyTg1_un_px_SHIFT (0U)
15612#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RxClkcDlyTg1_un_px(x) \
15613 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RxClkcDlyTg1_un_px_SHIFT)) & \
15614 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P2_RxClkcDlyTg1_un_px_MASK)
15615/*! @} */
15616
15617/*! @name RXCLKCDLYTG2_U0_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
15618/*! @{ */
15619#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RxClkcDlyTg2_un_px_MASK (0x3FU)
15620#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RxClkcDlyTg2_un_px_SHIFT (0U)
15621#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RxClkcDlyTg2_un_px(x) \
15622 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RxClkcDlyTg2_un_px_SHIFT)) & \
15623 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P2_RxClkcDlyTg2_un_px_MASK)
15624/*! @} */
15625
15626/*! @name RXCLKCDLYTG3_U0_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
15627/*! @{ */
15628#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RxClkcDlyTg3_un_px_MASK (0x3FU)
15629#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RxClkcDlyTg3_un_px_SHIFT (0U)
15630#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RxClkcDlyTg3_un_px(x) \
15631 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RxClkcDlyTg3_un_px_SHIFT)) & \
15632 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P2_RxClkcDlyTg3_un_px_MASK)
15633/*! @} */
15634
15635/*! @name PPTDQSCNTINVTRNTG0_P2 - DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation */
15636/*! @{ */
15637#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PptDqsCntInvTrnTg0_p2_MASK (0xFFFFU)
15638#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PptDqsCntInvTrnTg0_p2_SHIFT (0U)
15639#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PptDqsCntInvTrnTg0_p2(x) \
15640 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PptDqsCntInvTrnTg0_p2_SHIFT)) & \
15641 DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P2_PptDqsCntInvTrnTg0_p2_MASK)
15642/*! @} */
15643
15644/*! @name PPTDQSCNTINVTRNTG1_P2 - DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation */
15645/*! @{ */
15646#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PptDqsCntInvTrnTg1_p2_MASK (0xFFFFU)
15647#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PptDqsCntInvTrnTg1_p2_SHIFT (0U)
15648#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PptDqsCntInvTrnTg1_p2(x) \
15649 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PptDqsCntInvTrnTg1_p2_SHIFT)) & \
15650 DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P2_PptDqsCntInvTrnTg1_p2_MASK)
15651/*! @} */
15652
15653/*! @name TXDQDLYTG0_R0_P2 - Write DQ Delay (Timing Group 0). */
15654/*! @{ */
15655#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU)
15656#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TxDqDlyTg0_rn_px_SHIFT (0U)
15657#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TxDqDlyTg0_rn_px(x) \
15658 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TxDqDlyTg0_rn_px_SHIFT)) & \
15659 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P2_TxDqDlyTg0_rn_px_MASK)
15660/*! @} */
15661
15662/*! @name TXDQDLYTG1_R0_P2 - Write DQ Delay (Timing Group 1). */
15663/*! @{ */
15664#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU)
15665#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TxDqDlyTg1_rn_px_SHIFT (0U)
15666#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TxDqDlyTg1_rn_px(x) \
15667 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TxDqDlyTg1_rn_px_SHIFT)) & \
15668 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P2_TxDqDlyTg1_rn_px_MASK)
15669/*! @} */
15670
15671/*! @name TXDQDLYTG2_R0_P2 - Write DQ Delay (Timing Group 2). */
15672/*! @{ */
15673#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU)
15674#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TxDqDlyTg2_rn_px_SHIFT (0U)
15675#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TxDqDlyTg2_rn_px(x) \
15676 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TxDqDlyTg2_rn_px_SHIFT)) & \
15677 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P2_TxDqDlyTg2_rn_px_MASK)
15678/*! @} */
15679
15680/*! @name TXDQDLYTG3_R0_P2 - Write DQ Delay (Timing Group 3). */
15681/*! @{ */
15682#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU)
15683#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TxDqDlyTg3_rn_px_SHIFT (0U)
15684#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TxDqDlyTg3_rn_px(x) \
15685 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TxDqDlyTg3_rn_px_SHIFT)) & \
15686 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P2_TxDqDlyTg3_rn_px_MASK)
15687/*! @} */
15688
15689/*! @name TXDQSDLYTG0_U0_P2 - Write DQS Delay (Timing Group DEST=0). */
15690/*! @{ */
15691#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TxDqsDlyTg0_un_px_MASK (0x3FFU)
15692#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TxDqsDlyTg0_un_px_SHIFT (0U)
15693#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TxDqsDlyTg0_un_px(x) \
15694 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TxDqsDlyTg0_un_px_SHIFT)) & \
15695 DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P2_TxDqsDlyTg0_un_px_MASK)
15696/*! @} */
15697
15698/*! @name TXDQSDLYTG1_U0_P2 - Write DQS Delay (Timing Group DEST=1). */
15699/*! @{ */
15700#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TxDqsDlyTg1_un_px_MASK (0x3FFU)
15701#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TxDqsDlyTg1_un_px_SHIFT (0U)
15702#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TxDqsDlyTg1_un_px(x) \
15703 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TxDqsDlyTg1_un_px_SHIFT)) & \
15704 DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P2_TxDqsDlyTg1_un_px_MASK)
15705/*! @} */
15706
15707/*! @name TXDQSDLYTG2_U0_P2 - Write DQS Delay (Timing Group DEST=2). */
15708/*! @{ */
15709#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TxDqsDlyTg2_un_px_MASK (0x3FFU)
15710#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TxDqsDlyTg2_un_px_SHIFT (0U)
15711#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TxDqsDlyTg2_un_px(x) \
15712 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TxDqsDlyTg2_un_px_SHIFT)) & \
15713 DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P2_TxDqsDlyTg2_un_px_MASK)
15714/*! @} */
15715
15716/*! @name TXDQSDLYTG3_U0_P2 - Write DQS Delay (Timing Group DEST=3). */
15717/*! @{ */
15718#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TxDqsDlyTg3_un_px_MASK (0x3FFU)
15719#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TxDqsDlyTg3_un_px_SHIFT (0U)
15720#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TxDqsDlyTg3_un_px(x) \
15721 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TxDqsDlyTg3_un_px_SHIFT)) & \
15722 DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P2_TxDqsDlyTg3_un_px_MASK)
15723/*! @} */
15724
15725/*! @name TXIMPEDANCECTRL0_B1_P2 - Data TX impedance controls */
15726/*! @{ */
15727#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqP_MASK (0x3FU)
15728#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqP_SHIFT (0U)
15729#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqP(x) \
15730 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqP_SHIFT)) & \
15731 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqP_MASK)
15732#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqN_MASK (0xFC0U)
15733#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqN_SHIFT (6U)
15734#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqN(x) \
15735 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqN_SHIFT)) & \
15736 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P2_DrvStrenDqN_MASK)
15737/*! @} */
15738
15739/*! @name DQDQSRCVCNTRL_B1_P2 - Dq/Dqs receiver control */
15740/*! @{ */
15741#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SelAnalogVref_MASK (0x1U)
15742#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SelAnalogVref_SHIFT (0U)
15743#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SelAnalogVref(x) \
15744 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SelAnalogVref_SHIFT)) & \
15745 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_SelAnalogVref_MASK)
15746#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_ExtVrefRange_MASK (0x2U)
15747#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_ExtVrefRange_SHIFT (1U)
15748#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_ExtVrefRange(x) \
15749 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_ExtVrefRange_SHIFT)) & \
15750 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_ExtVrefRange_MASK)
15751#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DfeCtrl_MASK (0xCU)
15752#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DfeCtrl_SHIFT (2U)
15753#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DfeCtrl(x) \
15754 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DfeCtrl_SHIFT)) & \
15755 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_DfeCtrl_MASK)
15756#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MajorModeDbyte_MASK (0x70U)
15757#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MajorModeDbyte_SHIFT (4U)
15758#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MajorModeDbyte(x) \
15759 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MajorModeDbyte_SHIFT)) & \
15760 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_MajorModeDbyte_MASK)
15761#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GainCurrAdj_MASK (0xF80U)
15762#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GainCurrAdj_SHIFT (7U)
15763#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GainCurrAdj(x) \
15764 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GainCurrAdj_SHIFT)) & \
15765 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P2_GainCurrAdj_MASK)
15766/*! @} */
15767
15768/*! @name TXIMPEDANCECTRL1_B1_P2 - TX impedance controls */
15769/*! @{ */
15770#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqP_MASK (0x3FU)
15771#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqP_SHIFT (0U)
15772#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqP(x) \
15773 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqP_SHIFT)) & \
15774 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqP_MASK)
15775#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqN_MASK (0xFC0U)
15776#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqN_SHIFT (6U)
15777#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqN(x) \
15778 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqN_SHIFT)) & \
15779 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P2_DrvStrenFSDqN_MASK)
15780/*! @} */
15781
15782/*! @name TXIMPEDANCECTRL2_B1_P2 - TX equalization impedance controls */
15783/*! @{ */
15784#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQHiDqP_MASK (0x3FU)
15785#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQHiDqP_SHIFT (0U)
15786#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQHiDqP(x) \
15787 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQHiDqP_SHIFT)) & \
15788 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQHiDqP_MASK)
15789#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQLoDqN_MASK (0xFC0U)
15790#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQLoDqN_SHIFT (6U)
15791#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQLoDqN(x) \
15792 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQLoDqN_SHIFT)) & \
15793 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P2_DrvStrenEQLoDqN_MASK)
15794/*! @} */
15795
15796/*! @name TXODTDRVSTREN_B1_P2 - TX ODT driver strength control */
15797/*! @{ */
15798#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenP_MASK (0x3FU)
15799#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenP_SHIFT (0U)
15800#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenP(x) \
15801 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenP_SHIFT)) & \
15802 DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenP_MASK)
15803#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenN_MASK (0xFC0U)
15804#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenN_SHIFT (6U)
15805#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenN(x) \
15806 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenN_SHIFT)) & \
15807 DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P2_ODTStrenN_MASK)
15808/*! @} */
15809
15810/*! @name TXSLEWRATE_B1_P2 - TX slew rate controls */
15811/*! @{ */
15812#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreP_MASK (0xFU)
15813#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreP_SHIFT (0U)
15814#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreP(x) \
15815 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreP_SHIFT)) & \
15816 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreP_MASK)
15817#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreN_MASK (0xF0U)
15818#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreN_SHIFT (4U)
15819#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreN(x) \
15820 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreN_SHIFT)) & \
15821 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreN_MASK)
15822#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreDrvMode_MASK (0x700U)
15823#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreDrvMode_SHIFT (8U)
15824#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreDrvMode(x) \
15825 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreDrvMode_SHIFT)) & \
15826 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P2_TxPreDrvMode_MASK)
15827/*! @} */
15828
15829/*! @name RXENDLYTG0_U1_P2 - Trained Receive Enable Delay (For Timing Group 0) */
15830/*! @{ */
15831#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RxEnDlyTg0_un_px_MASK (0x7FFU)
15832#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RxEnDlyTg0_un_px_SHIFT (0U)
15833#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RxEnDlyTg0_un_px(x) \
15834 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RxEnDlyTg0_un_px_SHIFT)) & \
15835 DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P2_RxEnDlyTg0_un_px_MASK)
15836/*! @} */
15837
15838/*! @name RXENDLYTG1_U1_P2 - Trained Receive Enable Delay (For Timing Group 1) */
15839/*! @{ */
15840#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RxEnDlyTg1_un_px_MASK (0x7FFU)
15841#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RxEnDlyTg1_un_px_SHIFT (0U)
15842#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RxEnDlyTg1_un_px(x) \
15843 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RxEnDlyTg1_un_px_SHIFT)) & \
15844 DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P2_RxEnDlyTg1_un_px_MASK)
15845/*! @} */
15846
15847/*! @name RXENDLYTG2_U1_P2 - Trained Receive Enable Delay (For Timing Group 2) */
15848/*! @{ */
15849#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RxEnDlyTg2_un_px_MASK (0x7FFU)
15850#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RxEnDlyTg2_un_px_SHIFT (0U)
15851#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RxEnDlyTg2_un_px(x) \
15852 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RxEnDlyTg2_un_px_SHIFT)) & \
15853 DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P2_RxEnDlyTg2_un_px_MASK)
15854/*! @} */
15855
15856/*! @name RXENDLYTG3_U1_P2 - Trained Receive Enable Delay (For Timing Group 3) */
15857/*! @{ */
15858#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RxEnDlyTg3_un_px_MASK (0x7FFU)
15859#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RxEnDlyTg3_un_px_SHIFT (0U)
15860#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RxEnDlyTg3_un_px(x) \
15861 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RxEnDlyTg3_un_px_SHIFT)) & \
15862 DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P2_RxEnDlyTg3_un_px_MASK)
15863/*! @} */
15864
15865/*! @name RXCLKDLYTG0_U1_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
15866/*! @{ */
15867#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RxClkDlyTg0_un_px_MASK (0x3FU)
15868#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RxClkDlyTg0_un_px_SHIFT (0U)
15869#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RxClkDlyTg0_un_px(x) \
15870 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RxClkDlyTg0_un_px_SHIFT)) & \
15871 DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P2_RxClkDlyTg0_un_px_MASK)
15872/*! @} */
15873
15874/*! @name RXCLKDLYTG1_U1_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
15875/*! @{ */
15876#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RxClkDlyTg1_un_px_MASK (0x3FU)
15877#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RxClkDlyTg1_un_px_SHIFT (0U)
15878#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RxClkDlyTg1_un_px(x) \
15879 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RxClkDlyTg1_un_px_SHIFT)) & \
15880 DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P2_RxClkDlyTg1_un_px_MASK)
15881/*! @} */
15882
15883/*! @name RXCLKDLYTG2_U1_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
15884/*! @{ */
15885#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RxClkDlyTg2_un_px_MASK (0x3FU)
15886#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RxClkDlyTg2_un_px_SHIFT (0U)
15887#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RxClkDlyTg2_un_px(x) \
15888 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RxClkDlyTg2_un_px_SHIFT)) & \
15889 DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P2_RxClkDlyTg2_un_px_MASK)
15890/*! @} */
15891
15892/*! @name RXCLKDLYTG3_U1_P2 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
15893/*! @{ */
15894#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RxClkDlyTg3_un_px_MASK (0x3FU)
15895#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RxClkDlyTg3_un_px_SHIFT (0U)
15896#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RxClkDlyTg3_un_px(x) \
15897 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RxClkDlyTg3_un_px_SHIFT)) & \
15898 DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P2_RxClkDlyTg3_un_px_MASK)
15899/*! @} */
15900
15901/*! @name RXCLKCDLYTG0_U1_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
15902/*! @{ */
15903#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RxClkcDlyTg0_un_px_MASK (0x3FU)
15904#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RxClkcDlyTg0_un_px_SHIFT (0U)
15905#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RxClkcDlyTg0_un_px(x) \
15906 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RxClkcDlyTg0_un_px_SHIFT)) & \
15907 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P2_RxClkcDlyTg0_un_px_MASK)
15908/*! @} */
15909
15910/*! @name RXCLKCDLYTG1_U1_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
15911/*! @{ */
15912#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RxClkcDlyTg1_un_px_MASK (0x3FU)
15913#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RxClkcDlyTg1_un_px_SHIFT (0U)
15914#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RxClkcDlyTg1_un_px(x) \
15915 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RxClkcDlyTg1_un_px_SHIFT)) & \
15916 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P2_RxClkcDlyTg1_un_px_MASK)
15917/*! @} */
15918
15919/*! @name RXCLKCDLYTG2_U1_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
15920/*! @{ */
15921#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RxClkcDlyTg2_un_px_MASK (0x3FU)
15922#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RxClkcDlyTg2_un_px_SHIFT (0U)
15923#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RxClkcDlyTg2_un_px(x) \
15924 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RxClkcDlyTg2_un_px_SHIFT)) & \
15925 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P2_RxClkcDlyTg2_un_px_MASK)
15926/*! @} */
15927
15928/*! @name RXCLKCDLYTG3_U1_P2 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
15929/*! @{ */
15930#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RxClkcDlyTg3_un_px_MASK (0x3FU)
15931#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RxClkcDlyTg3_un_px_SHIFT (0U)
15932#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RxClkcDlyTg3_un_px(x) \
15933 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RxClkcDlyTg3_un_px_SHIFT)) & \
15934 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P2_RxClkcDlyTg3_un_px_MASK)
15935/*! @} */
15936
15937/*! @name TXDQDLYTG0_R1_P2 - Write DQ Delay (Timing Group 0). */
15938/*! @{ */
15939#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU)
15940#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TxDqDlyTg0_rn_px_SHIFT (0U)
15941#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TxDqDlyTg0_rn_px(x) \
15942 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TxDqDlyTg0_rn_px_SHIFT)) & \
15943 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P2_TxDqDlyTg0_rn_px_MASK)
15944/*! @} */
15945
15946/*! @name TXDQDLYTG1_R1_P2 - Write DQ Delay (Timing Group 1). */
15947/*! @{ */
15948#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU)
15949#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TxDqDlyTg1_rn_px_SHIFT (0U)
15950#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TxDqDlyTg1_rn_px(x) \
15951 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TxDqDlyTg1_rn_px_SHIFT)) & \
15952 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P2_TxDqDlyTg1_rn_px_MASK)
15953/*! @} */
15954
15955/*! @name TXDQDLYTG2_R1_P2 - Write DQ Delay (Timing Group 2). */
15956/*! @{ */
15957#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU)
15958#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TxDqDlyTg2_rn_px_SHIFT (0U)
15959#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TxDqDlyTg2_rn_px(x) \
15960 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TxDqDlyTg2_rn_px_SHIFT)) & \
15961 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P2_TxDqDlyTg2_rn_px_MASK)
15962/*! @} */
15963
15964/*! @name TXDQDLYTG3_R1_P2 - Write DQ Delay (Timing Group 3). */
15965/*! @{ */
15966#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU)
15967#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TxDqDlyTg3_rn_px_SHIFT (0U)
15968#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TxDqDlyTg3_rn_px(x) \
15969 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TxDqDlyTg3_rn_px_SHIFT)) & \
15970 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P2_TxDqDlyTg3_rn_px_MASK)
15971/*! @} */
15972
15973/*! @name TXDQSDLYTG0_U1_P2 - Write DQS Delay (Timing Group DEST=0). */
15974/*! @{ */
15975#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TxDqsDlyTg0_un_px_MASK (0x3FFU)
15976#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TxDqsDlyTg0_un_px_SHIFT (0U)
15977#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TxDqsDlyTg0_un_px(x) \
15978 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TxDqsDlyTg0_un_px_SHIFT)) & \
15979 DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P2_TxDqsDlyTg0_un_px_MASK)
15980/*! @} */
15981
15982/*! @name TXDQSDLYTG1_U1_P2 - Write DQS Delay (Timing Group DEST=1). */
15983/*! @{ */
15984#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TxDqsDlyTg1_un_px_MASK (0x3FFU)
15985#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TxDqsDlyTg1_un_px_SHIFT (0U)
15986#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TxDqsDlyTg1_un_px(x) \
15987 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TxDqsDlyTg1_un_px_SHIFT)) & \
15988 DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P2_TxDqsDlyTg1_un_px_MASK)
15989/*! @} */
15990
15991/*! @name TXDQSDLYTG2_U1_P2 - Write DQS Delay (Timing Group DEST=2). */
15992/*! @{ */
15993#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TxDqsDlyTg2_un_px_MASK (0x3FFU)
15994#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TxDqsDlyTg2_un_px_SHIFT (0U)
15995#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TxDqsDlyTg2_un_px(x) \
15996 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TxDqsDlyTg2_un_px_SHIFT)) & \
15997 DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P2_TxDqsDlyTg2_un_px_MASK)
15998/*! @} */
15999
16000/*! @name TXDQSDLYTG3_U1_P2 - Write DQS Delay (Timing Group DEST=3). */
16001/*! @{ */
16002#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TxDqsDlyTg3_un_px_MASK (0x3FFU)
16003#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TxDqsDlyTg3_un_px_SHIFT (0U)
16004#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TxDqsDlyTg3_un_px(x) \
16005 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TxDqsDlyTg3_un_px_SHIFT)) & \
16006 DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P2_TxDqsDlyTg3_un_px_MASK)
16007/*! @} */
16008
16009/*! @name TXDQDLYTG0_R2_P2 - Write DQ Delay (Timing Group 0). */
16010/*! @{ */
16011#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU)
16012#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TxDqDlyTg0_rn_px_SHIFT (0U)
16013#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TxDqDlyTg0_rn_px(x) \
16014 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TxDqDlyTg0_rn_px_SHIFT)) & \
16015 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P2_TxDqDlyTg0_rn_px_MASK)
16016/*! @} */
16017
16018/*! @name TXDQDLYTG1_R2_P2 - Write DQ Delay (Timing Group 1). */
16019/*! @{ */
16020#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU)
16021#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TxDqDlyTg1_rn_px_SHIFT (0U)
16022#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TxDqDlyTg1_rn_px(x) \
16023 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TxDqDlyTg1_rn_px_SHIFT)) & \
16024 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P2_TxDqDlyTg1_rn_px_MASK)
16025/*! @} */
16026
16027/*! @name TXDQDLYTG2_R2_P2 - Write DQ Delay (Timing Group 2). */
16028/*! @{ */
16029#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU)
16030#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TxDqDlyTg2_rn_px_SHIFT (0U)
16031#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TxDqDlyTg2_rn_px(x) \
16032 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TxDqDlyTg2_rn_px_SHIFT)) & \
16033 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P2_TxDqDlyTg2_rn_px_MASK)
16034/*! @} */
16035
16036/*! @name TXDQDLYTG3_R2_P2 - Write DQ Delay (Timing Group 3). */
16037/*! @{ */
16038#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU)
16039#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TxDqDlyTg3_rn_px_SHIFT (0U)
16040#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TxDqDlyTg3_rn_px(x) \
16041 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TxDqDlyTg3_rn_px_SHIFT)) & \
16042 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P2_TxDqDlyTg3_rn_px_MASK)
16043/*! @} */
16044
16045/*! @name TXDQDLYTG0_R3_P2 - Write DQ Delay (Timing Group 0). */
16046/*! @{ */
16047#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU)
16048#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TxDqDlyTg0_rn_px_SHIFT (0U)
16049#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TxDqDlyTg0_rn_px(x) \
16050 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TxDqDlyTg0_rn_px_SHIFT)) & \
16051 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P2_TxDqDlyTg0_rn_px_MASK)
16052/*! @} */
16053
16054/*! @name TXDQDLYTG1_R3_P2 - Write DQ Delay (Timing Group 1). */
16055/*! @{ */
16056#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU)
16057#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TxDqDlyTg1_rn_px_SHIFT (0U)
16058#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TxDqDlyTg1_rn_px(x) \
16059 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TxDqDlyTg1_rn_px_SHIFT)) & \
16060 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P2_TxDqDlyTg1_rn_px_MASK)
16061/*! @} */
16062
16063/*! @name TXDQDLYTG2_R3_P2 - Write DQ Delay (Timing Group 2). */
16064/*! @{ */
16065#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU)
16066#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TxDqDlyTg2_rn_px_SHIFT (0U)
16067#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TxDqDlyTg2_rn_px(x) \
16068 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TxDqDlyTg2_rn_px_SHIFT)) & \
16069 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P2_TxDqDlyTg2_rn_px_MASK)
16070/*! @} */
16071
16072/*! @name TXDQDLYTG3_R3_P2 - Write DQ Delay (Timing Group 3). */
16073/*! @{ */
16074#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU)
16075#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TxDqDlyTg3_rn_px_SHIFT (0U)
16076#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TxDqDlyTg3_rn_px(x) \
16077 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TxDqDlyTg3_rn_px_SHIFT)) & \
16078 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P2_TxDqDlyTg3_rn_px_MASK)
16079/*! @} */
16080
16081/*! @name TXDQDLYTG0_R4_P2 - Write DQ Delay (Timing Group 0). */
16082/*! @{ */
16083#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU)
16084#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TxDqDlyTg0_rn_px_SHIFT (0U)
16085#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TxDqDlyTg0_rn_px(x) \
16086 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TxDqDlyTg0_rn_px_SHIFT)) & \
16087 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P2_TxDqDlyTg0_rn_px_MASK)
16088/*! @} */
16089
16090/*! @name TXDQDLYTG1_R4_P2 - Write DQ Delay (Timing Group 1). */
16091/*! @{ */
16092#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU)
16093#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TxDqDlyTg1_rn_px_SHIFT (0U)
16094#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TxDqDlyTg1_rn_px(x) \
16095 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TxDqDlyTg1_rn_px_SHIFT)) & \
16096 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P2_TxDqDlyTg1_rn_px_MASK)
16097/*! @} */
16098
16099/*! @name TXDQDLYTG2_R4_P2 - Write DQ Delay (Timing Group 2). */
16100/*! @{ */
16101#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU)
16102#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TxDqDlyTg2_rn_px_SHIFT (0U)
16103#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TxDqDlyTg2_rn_px(x) \
16104 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TxDqDlyTg2_rn_px_SHIFT)) & \
16105 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P2_TxDqDlyTg2_rn_px_MASK)
16106/*! @} */
16107
16108/*! @name TXDQDLYTG3_R4_P2 - Write DQ Delay (Timing Group 3). */
16109/*! @{ */
16110#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU)
16111#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TxDqDlyTg3_rn_px_SHIFT (0U)
16112#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TxDqDlyTg3_rn_px(x) \
16113 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TxDqDlyTg3_rn_px_SHIFT)) & \
16114 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P2_TxDqDlyTg3_rn_px_MASK)
16115/*! @} */
16116
16117/*! @name TXDQDLYTG0_R5_P2 - Write DQ Delay (Timing Group 0). */
16118/*! @{ */
16119#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU)
16120#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TxDqDlyTg0_rn_px_SHIFT (0U)
16121#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TxDqDlyTg0_rn_px(x) \
16122 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TxDqDlyTg0_rn_px_SHIFT)) & \
16123 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P2_TxDqDlyTg0_rn_px_MASK)
16124/*! @} */
16125
16126/*! @name TXDQDLYTG1_R5_P2 - Write DQ Delay (Timing Group 1). */
16127/*! @{ */
16128#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU)
16129#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TxDqDlyTg1_rn_px_SHIFT (0U)
16130#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TxDqDlyTg1_rn_px(x) \
16131 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TxDqDlyTg1_rn_px_SHIFT)) & \
16132 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P2_TxDqDlyTg1_rn_px_MASK)
16133/*! @} */
16134
16135/*! @name TXDQDLYTG2_R5_P2 - Write DQ Delay (Timing Group 2). */
16136/*! @{ */
16137#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU)
16138#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TxDqDlyTg2_rn_px_SHIFT (0U)
16139#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TxDqDlyTg2_rn_px(x) \
16140 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TxDqDlyTg2_rn_px_SHIFT)) & \
16141 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P2_TxDqDlyTg2_rn_px_MASK)
16142/*! @} */
16143
16144/*! @name TXDQDLYTG3_R5_P2 - Write DQ Delay (Timing Group 3). */
16145/*! @{ */
16146#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU)
16147#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TxDqDlyTg3_rn_px_SHIFT (0U)
16148#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TxDqDlyTg3_rn_px(x) \
16149 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TxDqDlyTg3_rn_px_SHIFT)) & \
16150 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P2_TxDqDlyTg3_rn_px_MASK)
16151/*! @} */
16152
16153/*! @name TXDQDLYTG0_R6_P2 - Write DQ Delay (Timing Group 0). */
16154/*! @{ */
16155#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU)
16156#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TxDqDlyTg0_rn_px_SHIFT (0U)
16157#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TxDqDlyTg0_rn_px(x) \
16158 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TxDqDlyTg0_rn_px_SHIFT)) & \
16159 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P2_TxDqDlyTg0_rn_px_MASK)
16160/*! @} */
16161
16162/*! @name TXDQDLYTG1_R6_P2 - Write DQ Delay (Timing Group 1). */
16163/*! @{ */
16164#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU)
16165#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TxDqDlyTg1_rn_px_SHIFT (0U)
16166#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TxDqDlyTg1_rn_px(x) \
16167 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TxDqDlyTg1_rn_px_SHIFT)) & \
16168 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P2_TxDqDlyTg1_rn_px_MASK)
16169/*! @} */
16170
16171/*! @name TXDQDLYTG2_R6_P2 - Write DQ Delay (Timing Group 2). */
16172/*! @{ */
16173#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU)
16174#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TxDqDlyTg2_rn_px_SHIFT (0U)
16175#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TxDqDlyTg2_rn_px(x) \
16176 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TxDqDlyTg2_rn_px_SHIFT)) & \
16177 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P2_TxDqDlyTg2_rn_px_MASK)
16178/*! @} */
16179
16180/*! @name TXDQDLYTG3_R6_P2 - Write DQ Delay (Timing Group 3). */
16181/*! @{ */
16182#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU)
16183#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TxDqDlyTg3_rn_px_SHIFT (0U)
16184#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TxDqDlyTg3_rn_px(x) \
16185 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TxDqDlyTg3_rn_px_SHIFT)) & \
16186 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P2_TxDqDlyTg3_rn_px_MASK)
16187/*! @} */
16188
16189/*! @name TXDQDLYTG0_R7_P2 - Write DQ Delay (Timing Group 0). */
16190/*! @{ */
16191#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU)
16192#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TxDqDlyTg0_rn_px_SHIFT (0U)
16193#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TxDqDlyTg0_rn_px(x) \
16194 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TxDqDlyTg0_rn_px_SHIFT)) & \
16195 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P2_TxDqDlyTg0_rn_px_MASK)
16196/*! @} */
16197
16198/*! @name TXDQDLYTG1_R7_P2 - Write DQ Delay (Timing Group 1). */
16199/*! @{ */
16200#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU)
16201#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TxDqDlyTg1_rn_px_SHIFT (0U)
16202#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TxDqDlyTg1_rn_px(x) \
16203 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TxDqDlyTg1_rn_px_SHIFT)) & \
16204 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P2_TxDqDlyTg1_rn_px_MASK)
16205/*! @} */
16206
16207/*! @name TXDQDLYTG2_R7_P2 - Write DQ Delay (Timing Group 2). */
16208/*! @{ */
16209#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU)
16210#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TxDqDlyTg2_rn_px_SHIFT (0U)
16211#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TxDqDlyTg2_rn_px(x) \
16212 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TxDqDlyTg2_rn_px_SHIFT)) & \
16213 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P2_TxDqDlyTg2_rn_px_MASK)
16214/*! @} */
16215
16216/*! @name TXDQDLYTG3_R7_P2 - Write DQ Delay (Timing Group 3). */
16217/*! @{ */
16218#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU)
16219#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TxDqDlyTg3_rn_px_SHIFT (0U)
16220#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TxDqDlyTg3_rn_px(x) \
16221 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TxDqDlyTg3_rn_px_SHIFT)) & \
16222 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P2_TxDqDlyTg3_rn_px_MASK)
16223/*! @} */
16224
16225/*! @name TXDQDLYTG0_R8_P2 - Write DQ Delay (Timing Group 0). */
16226/*! @{ */
16227#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TxDqDlyTg0_rn_px_MASK (0x1FFU)
16228#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TxDqDlyTg0_rn_px_SHIFT (0U)
16229#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TxDqDlyTg0_rn_px(x) \
16230 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TxDqDlyTg0_rn_px_SHIFT)) & \
16231 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P2_TxDqDlyTg0_rn_px_MASK)
16232/*! @} */
16233
16234/*! @name TXDQDLYTG1_R8_P2 - Write DQ Delay (Timing Group 1). */
16235/*! @{ */
16236#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TxDqDlyTg1_rn_px_MASK (0x1FFU)
16237#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TxDqDlyTg1_rn_px_SHIFT (0U)
16238#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TxDqDlyTg1_rn_px(x) \
16239 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TxDqDlyTg1_rn_px_SHIFT)) & \
16240 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P2_TxDqDlyTg1_rn_px_MASK)
16241/*! @} */
16242
16243/*! @name TXDQDLYTG2_R8_P2 - Write DQ Delay (Timing Group 2). */
16244/*! @{ */
16245#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TxDqDlyTg2_rn_px_MASK (0x1FFU)
16246#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TxDqDlyTg2_rn_px_SHIFT (0U)
16247#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TxDqDlyTg2_rn_px(x) \
16248 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TxDqDlyTg2_rn_px_SHIFT)) & \
16249 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P2_TxDqDlyTg2_rn_px_MASK)
16250/*! @} */
16251
16252/*! @name TXDQDLYTG3_R8_P2 - Write DQ Delay (Timing Group 3). */
16253/*! @{ */
16254#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TxDqDlyTg3_rn_px_MASK (0x1FFU)
16255#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TxDqDlyTg3_rn_px_SHIFT (0U)
16256#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TxDqDlyTg3_rn_px(x) \
16257 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TxDqDlyTg3_rn_px_SHIFT)) & \
16258 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P2_TxDqDlyTg3_rn_px_MASK)
16259/*! @} */
16260
16261/*! @name DFIMRL_P3 - DFI MaxReadLatency */
16262/*! @{ */
16263#define DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_p3_MASK (0x1FU)
16264#define DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_p3_SHIFT (0U)
16265#define DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_p3(x) \
16266 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_p3_SHIFT)) & \
16267 DWC_DDRPHYA_DBYTE_DFIMRL_P3_DFIMRL_p3_MASK)
16268/*! @} */
16269
16270/*! @name TXIMPEDANCECTRL0_B0_P3 - Data TX impedance controls */
16271/*! @{ */
16272#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqP_MASK (0x3FU)
16273#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqP_SHIFT (0U)
16274#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqP(x) \
16275 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqP_SHIFT)) & \
16276 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqP_MASK)
16277#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqN_MASK (0xFC0U)
16278#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqN_SHIFT (6U)
16279#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqN(x) \
16280 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqN_SHIFT)) & \
16281 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B0_P3_DrvStrenDqN_MASK)
16282/*! @} */
16283
16284/*! @name DQDQSRCVCNTRL_B0_P3 - Dq/Dqs receiver control */
16285/*! @{ */
16286#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SelAnalogVref_MASK (0x1U)
16287#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SelAnalogVref_SHIFT (0U)
16288#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SelAnalogVref(x) \
16289 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SelAnalogVref_SHIFT)) & \
16290 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_SelAnalogVref_MASK)
16291#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_ExtVrefRange_MASK (0x2U)
16292#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_ExtVrefRange_SHIFT (1U)
16293#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_ExtVrefRange(x) \
16294 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_ExtVrefRange_SHIFT)) & \
16295 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_ExtVrefRange_MASK)
16296#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DfeCtrl_MASK (0xCU)
16297#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DfeCtrl_SHIFT (2U)
16298#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DfeCtrl(x) \
16299 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DfeCtrl_SHIFT)) & \
16300 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_DfeCtrl_MASK)
16301#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MajorModeDbyte_MASK (0x70U)
16302#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MajorModeDbyte_SHIFT (4U)
16303#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MajorModeDbyte(x) \
16304 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MajorModeDbyte_SHIFT)) & \
16305 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_MajorModeDbyte_MASK)
16306#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GainCurrAdj_MASK (0xF80U)
16307#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GainCurrAdj_SHIFT (7U)
16308#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GainCurrAdj(x) \
16309 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GainCurrAdj_SHIFT)) & \
16310 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B0_P3_GainCurrAdj_MASK)
16311/*! @} */
16312
16313/*! @name TXEQUALIZATIONMODE_P3 - Tx dq driver equalization mode controls. */
16314/*! @{ */
16315#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TxEqMode_MASK (0x3U)
16316#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TxEqMode_SHIFT (0U)
16317#define DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TxEqMode(x) \
16318 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TxEqMode_SHIFT)) & \
16319 DWC_DDRPHYA_DBYTE_TXEQUALIZATIONMODE_P3_TxEqMode_MASK)
16320/*! @} */
16321
16322/*! @name TXIMPEDANCECTRL1_B0_P3 - TX impedance controls */
16323/*! @{ */
16324#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqP_MASK (0x3FU)
16325#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqP_SHIFT (0U)
16326#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqP(x) \
16327 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqP_SHIFT)) & \
16328 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqP_MASK)
16329#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqN_MASK (0xFC0U)
16330#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqN_SHIFT (6U)
16331#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqN(x) \
16332 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqN_SHIFT)) & \
16333 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B0_P3_DrvStrenFSDqN_MASK)
16334/*! @} */
16335
16336/*! @name TXIMPEDANCECTRL2_B0_P3 - TX equalization impedance controls */
16337/*! @{ */
16338#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQHiDqP_MASK (0x3FU)
16339#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQHiDqP_SHIFT (0U)
16340#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQHiDqP(x) \
16341 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQHiDqP_SHIFT)) & \
16342 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQHiDqP_MASK)
16343#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQLoDqN_MASK (0xFC0U)
16344#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQLoDqN_SHIFT (6U)
16345#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQLoDqN(x) \
16346 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQLoDqN_SHIFT)) & \
16347 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B0_P3_DrvStrenEQLoDqN_MASK)
16348/*! @} */
16349
16350/*! @name DQDQSRCVCNTRL2_P3 - Dq/Dqs receiver control */
16351/*! @{ */
16352#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_EnRxAgressivePDR_MASK (0x1U)
16353#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_EnRxAgressivePDR_SHIFT (0U)
16354#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_EnRxAgressivePDR(x) \
16355 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_EnRxAgressivePDR_SHIFT)) & \
16356 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL2_P3_EnRxAgressivePDR_MASK)
16357/*! @} */
16358
16359/*! @name TXODTDRVSTREN_B0_P3 - TX ODT driver strength control */
16360/*! @{ */
16361#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenP_MASK (0x3FU)
16362#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenP_SHIFT (0U)
16363#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenP(x) \
16364 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenP_SHIFT)) & \
16365 DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenP_MASK)
16366#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenN_MASK (0xFC0U)
16367#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenN_SHIFT (6U)
16368#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenN(x) \
16369 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenN_SHIFT)) & \
16370 DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B0_P3_ODTStrenN_MASK)
16371/*! @} */
16372
16373/*! @name TXSLEWRATE_B0_P3 - TX slew rate controls */
16374/*! @{ */
16375#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreP_MASK (0xFU)
16376#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreP_SHIFT (0U)
16377#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreP(x) \
16378 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreP_SHIFT)) & \
16379 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreP_MASK)
16380#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreN_MASK (0xF0U)
16381#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreN_SHIFT (4U)
16382#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreN(x) \
16383 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreN_SHIFT)) & \
16384 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreN_MASK)
16385#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreDrvMode_MASK (0x700U)
16386#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreDrvMode_SHIFT (8U)
16387#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreDrvMode(x) \
16388 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreDrvMode_SHIFT)) & \
16389 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B0_P3_TxPreDrvMode_MASK)
16390/*! @} */
16391
16392/*! @name RXENDLYTG0_U0_P3 - Trained Receive Enable Delay (For Timing Group 0) */
16393/*! @{ */
16394#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RxEnDlyTg0_un_px_MASK (0x7FFU)
16395#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RxEnDlyTg0_un_px_SHIFT (0U)
16396#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RxEnDlyTg0_un_px(x) \
16397 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RxEnDlyTg0_un_px_SHIFT)) & \
16398 DWC_DDRPHYA_DBYTE_RXENDLYTG0_U0_P3_RxEnDlyTg0_un_px_MASK)
16399/*! @} */
16400
16401/*! @name RXENDLYTG1_U0_P3 - Trained Receive Enable Delay (For Timing Group 1) */
16402/*! @{ */
16403#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RxEnDlyTg1_un_px_MASK (0x7FFU)
16404#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RxEnDlyTg1_un_px_SHIFT (0U)
16405#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RxEnDlyTg1_un_px(x) \
16406 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RxEnDlyTg1_un_px_SHIFT)) & \
16407 DWC_DDRPHYA_DBYTE_RXENDLYTG1_U0_P3_RxEnDlyTg1_un_px_MASK)
16408/*! @} */
16409
16410/*! @name RXENDLYTG2_U0_P3 - Trained Receive Enable Delay (For Timing Group 2) */
16411/*! @{ */
16412#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RxEnDlyTg2_un_px_MASK (0x7FFU)
16413#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RxEnDlyTg2_un_px_SHIFT (0U)
16414#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RxEnDlyTg2_un_px(x) \
16415 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RxEnDlyTg2_un_px_SHIFT)) & \
16416 DWC_DDRPHYA_DBYTE_RXENDLYTG2_U0_P3_RxEnDlyTg2_un_px_MASK)
16417/*! @} */
16418
16419/*! @name RXENDLYTG3_U0_P3 - Trained Receive Enable Delay (For Timing Group 3) */
16420/*! @{ */
16421#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RxEnDlyTg3_un_px_MASK (0x7FFU)
16422#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RxEnDlyTg3_un_px_SHIFT (0U)
16423#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RxEnDlyTg3_un_px(x) \
16424 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RxEnDlyTg3_un_px_SHIFT)) & \
16425 DWC_DDRPHYA_DBYTE_RXENDLYTG3_U0_P3_RxEnDlyTg3_un_px_MASK)
16426/*! @} */
16427
16428/*! @name RXCLKDLYTG0_U0_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
16429/*! @{ */
16430#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RxClkDlyTg0_un_px_MASK (0x3FU)
16431#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RxClkDlyTg0_un_px_SHIFT (0U)
16432#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RxClkDlyTg0_un_px(x) \
16433 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RxClkDlyTg0_un_px_SHIFT)) & \
16434 DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U0_P3_RxClkDlyTg0_un_px_MASK)
16435/*! @} */
16436
16437/*! @name RXCLKDLYTG1_U0_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
16438/*! @{ */
16439#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RxClkDlyTg1_un_px_MASK (0x3FU)
16440#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RxClkDlyTg1_un_px_SHIFT (0U)
16441#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RxClkDlyTg1_un_px(x) \
16442 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RxClkDlyTg1_un_px_SHIFT)) & \
16443 DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U0_P3_RxClkDlyTg1_un_px_MASK)
16444/*! @} */
16445
16446/*! @name RXCLKDLYTG2_U0_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
16447/*! @{ */
16448#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RxClkDlyTg2_un_px_MASK (0x3FU)
16449#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RxClkDlyTg2_un_px_SHIFT (0U)
16450#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RxClkDlyTg2_un_px(x) \
16451 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RxClkDlyTg2_un_px_SHIFT)) & \
16452 DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U0_P3_RxClkDlyTg2_un_px_MASK)
16453/*! @} */
16454
16455/*! @name RXCLKDLYTG3_U0_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
16456/*! @{ */
16457#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RxClkDlyTg3_un_px_MASK (0x3FU)
16458#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RxClkDlyTg3_un_px_SHIFT (0U)
16459#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RxClkDlyTg3_un_px(x) \
16460 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RxClkDlyTg3_un_px_SHIFT)) & \
16461 DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U0_P3_RxClkDlyTg3_un_px_MASK)
16462/*! @} */
16463
16464/*! @name RXCLKCDLYTG0_U0_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
16465/*! @{ */
16466#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RxClkcDlyTg0_un_px_MASK (0x3FU)
16467#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RxClkcDlyTg0_un_px_SHIFT (0U)
16468#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RxClkcDlyTg0_un_px(x) \
16469 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RxClkcDlyTg0_un_px_SHIFT)) & \
16470 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U0_P3_RxClkcDlyTg0_un_px_MASK)
16471/*! @} */
16472
16473/*! @name RXCLKCDLYTG1_U0_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
16474/*! @{ */
16475#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RxClkcDlyTg1_un_px_MASK (0x3FU)
16476#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RxClkcDlyTg1_un_px_SHIFT (0U)
16477#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RxClkcDlyTg1_un_px(x) \
16478 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RxClkcDlyTg1_un_px_SHIFT)) & \
16479 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U0_P3_RxClkcDlyTg1_un_px_MASK)
16480/*! @} */
16481
16482/*! @name RXCLKCDLYTG2_U0_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
16483/*! @{ */
16484#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RxClkcDlyTg2_un_px_MASK (0x3FU)
16485#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RxClkcDlyTg2_un_px_SHIFT (0U)
16486#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RxClkcDlyTg2_un_px(x) \
16487 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RxClkcDlyTg2_un_px_SHIFT)) & \
16488 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U0_P3_RxClkcDlyTg2_un_px_MASK)
16489/*! @} */
16490
16491/*! @name RXCLKCDLYTG3_U0_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
16492/*! @{ */
16493#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RxClkcDlyTg3_un_px_MASK (0x3FU)
16494#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RxClkcDlyTg3_un_px_SHIFT (0U)
16495#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RxClkcDlyTg3_un_px(x) \
16496 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RxClkcDlyTg3_un_px_SHIFT)) & \
16497 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U0_P3_RxClkcDlyTg3_un_px_MASK)
16498/*! @} */
16499
16500/*! @name PPTDQSCNTINVTRNTG0_P3 - DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation */
16501/*! @{ */
16502#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PptDqsCntInvTrnTg0_p3_MASK (0xFFFFU)
16503#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PptDqsCntInvTrnTg0_p3_SHIFT (0U)
16504#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PptDqsCntInvTrnTg0_p3(x) \
16505 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PptDqsCntInvTrnTg0_p3_SHIFT)) & \
16506 DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG0_P3_PptDqsCntInvTrnTg0_p3_MASK)
16507/*! @} */
16508
16509/*! @name PPTDQSCNTINVTRNTG1_P3 - DQS Oscillator Count inverse at time of training in LPDDR4 drift compensation */
16510/*! @{ */
16511#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PptDqsCntInvTrnTg1_p3_MASK (0xFFFFU)
16512#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PptDqsCntInvTrnTg1_p3_SHIFT (0U)
16513#define DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PptDqsCntInvTrnTg1_p3(x) \
16514 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PptDqsCntInvTrnTg1_p3_SHIFT)) & \
16515 DWC_DDRPHYA_DBYTE_PPTDQSCNTINVTRNTG1_P3_PptDqsCntInvTrnTg1_p3_MASK)
16516/*! @} */
16517
16518/*! @name TXDQDLYTG0_R0_P3 - Write DQ Delay (Timing Group 0). */
16519/*! @{ */
16520#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU)
16521#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TxDqDlyTg0_rn_px_SHIFT (0U)
16522#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TxDqDlyTg0_rn_px(x) \
16523 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TxDqDlyTg0_rn_px_SHIFT)) & \
16524 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R0_P3_TxDqDlyTg0_rn_px_MASK)
16525/*! @} */
16526
16527/*! @name TXDQDLYTG1_R0_P3 - Write DQ Delay (Timing Group 1). */
16528/*! @{ */
16529#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU)
16530#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TxDqDlyTg1_rn_px_SHIFT (0U)
16531#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TxDqDlyTg1_rn_px(x) \
16532 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TxDqDlyTg1_rn_px_SHIFT)) & \
16533 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R0_P3_TxDqDlyTg1_rn_px_MASK)
16534/*! @} */
16535
16536/*! @name TXDQDLYTG2_R0_P3 - Write DQ Delay (Timing Group 2). */
16537/*! @{ */
16538#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU)
16539#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TxDqDlyTg2_rn_px_SHIFT (0U)
16540#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TxDqDlyTg2_rn_px(x) \
16541 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TxDqDlyTg2_rn_px_SHIFT)) & \
16542 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R0_P3_TxDqDlyTg2_rn_px_MASK)
16543/*! @} */
16544
16545/*! @name TXDQDLYTG3_R0_P3 - Write DQ Delay (Timing Group 3). */
16546/*! @{ */
16547#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU)
16548#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TxDqDlyTg3_rn_px_SHIFT (0U)
16549#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TxDqDlyTg3_rn_px(x) \
16550 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TxDqDlyTg3_rn_px_SHIFT)) & \
16551 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R0_P3_TxDqDlyTg3_rn_px_MASK)
16552/*! @} */
16553
16554/*! @name TXDQSDLYTG0_U0_P3 - Write DQS Delay (Timing Group DEST=0). */
16555/*! @{ */
16556#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TxDqsDlyTg0_un_px_MASK (0x3FFU)
16557#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TxDqsDlyTg0_un_px_SHIFT (0U)
16558#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TxDqsDlyTg0_un_px(x) \
16559 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TxDqsDlyTg0_un_px_SHIFT)) & \
16560 DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U0_P3_TxDqsDlyTg0_un_px_MASK)
16561/*! @} */
16562
16563/*! @name TXDQSDLYTG1_U0_P3 - Write DQS Delay (Timing Group DEST=1). */
16564/*! @{ */
16565#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TxDqsDlyTg1_un_px_MASK (0x3FFU)
16566#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TxDqsDlyTg1_un_px_SHIFT (0U)
16567#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TxDqsDlyTg1_un_px(x) \
16568 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TxDqsDlyTg1_un_px_SHIFT)) & \
16569 DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U0_P3_TxDqsDlyTg1_un_px_MASK)
16570/*! @} */
16571
16572/*! @name TXDQSDLYTG2_U0_P3 - Write DQS Delay (Timing Group DEST=2). */
16573/*! @{ */
16574#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TxDqsDlyTg2_un_px_MASK (0x3FFU)
16575#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TxDqsDlyTg2_un_px_SHIFT (0U)
16576#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TxDqsDlyTg2_un_px(x) \
16577 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TxDqsDlyTg2_un_px_SHIFT)) & \
16578 DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U0_P3_TxDqsDlyTg2_un_px_MASK)
16579/*! @} */
16580
16581/*! @name TXDQSDLYTG3_U0_P3 - Write DQS Delay (Timing Group DEST=3). */
16582/*! @{ */
16583#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TxDqsDlyTg3_un_px_MASK (0x3FFU)
16584#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TxDqsDlyTg3_un_px_SHIFT (0U)
16585#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TxDqsDlyTg3_un_px(x) \
16586 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TxDqsDlyTg3_un_px_SHIFT)) & \
16587 DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U0_P3_TxDqsDlyTg3_un_px_MASK)
16588/*! @} */
16589
16590/*! @name TXIMPEDANCECTRL0_B1_P3 - Data TX impedance controls */
16591/*! @{ */
16592#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqP_MASK (0x3FU)
16593#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqP_SHIFT (0U)
16594#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqP(x) \
16595 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqP_SHIFT)) & \
16596 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqP_MASK)
16597#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqN_MASK (0xFC0U)
16598#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqN_SHIFT (6U)
16599#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqN(x) \
16600 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqN_SHIFT)) & \
16601 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL0_B1_P3_DrvStrenDqN_MASK)
16602/*! @} */
16603
16604/*! @name DQDQSRCVCNTRL_B1_P3 - Dq/Dqs receiver control */
16605/*! @{ */
16606#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SelAnalogVref_MASK (0x1U)
16607#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SelAnalogVref_SHIFT (0U)
16608#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SelAnalogVref(x) \
16609 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SelAnalogVref_SHIFT)) & \
16610 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_SelAnalogVref_MASK)
16611#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_ExtVrefRange_MASK (0x2U)
16612#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_ExtVrefRange_SHIFT (1U)
16613#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_ExtVrefRange(x) \
16614 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_ExtVrefRange_SHIFT)) & \
16615 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_ExtVrefRange_MASK)
16616#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DfeCtrl_MASK (0xCU)
16617#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DfeCtrl_SHIFT (2U)
16618#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DfeCtrl(x) \
16619 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DfeCtrl_SHIFT)) & \
16620 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_DfeCtrl_MASK)
16621#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MajorModeDbyte_MASK (0x70U)
16622#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MajorModeDbyte_SHIFT (4U)
16623#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MajorModeDbyte(x) \
16624 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MajorModeDbyte_SHIFT)) & \
16625 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_MajorModeDbyte_MASK)
16626#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GainCurrAdj_MASK (0xF80U)
16627#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GainCurrAdj_SHIFT (7U)
16628#define DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GainCurrAdj(x) \
16629 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GainCurrAdj_SHIFT)) & \
16630 DWC_DDRPHYA_DBYTE_DQDQSRCVCNTRL_B1_P3_GainCurrAdj_MASK)
16631/*! @} */
16632
16633/*! @name TXIMPEDANCECTRL1_B1_P3 - TX impedance controls */
16634/*! @{ */
16635#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqP_MASK (0x3FU)
16636#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqP_SHIFT (0U)
16637#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqP(x) \
16638 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqP_SHIFT)) & \
16639 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqP_MASK)
16640#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqN_MASK (0xFC0U)
16641#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqN_SHIFT (6U)
16642#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqN(x) \
16643 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqN_SHIFT)) & \
16644 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL1_B1_P3_DrvStrenFSDqN_MASK)
16645/*! @} */
16646
16647/*! @name TXIMPEDANCECTRL2_B1_P3 - TX equalization impedance controls */
16648/*! @{ */
16649#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQHiDqP_MASK (0x3FU)
16650#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQHiDqP_SHIFT (0U)
16651#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQHiDqP(x) \
16652 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQHiDqP_SHIFT)) & \
16653 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQHiDqP_MASK)
16654#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQLoDqN_MASK (0xFC0U)
16655#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQLoDqN_SHIFT (6U)
16656#define DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQLoDqN(x) \
16657 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQLoDqN_SHIFT)) & \
16658 DWC_DDRPHYA_DBYTE_TXIMPEDANCECTRL2_B1_P3_DrvStrenEQLoDqN_MASK)
16659/*! @} */
16660
16661/*! @name TXODTDRVSTREN_B1_P3 - TX ODT driver strength control */
16662/*! @{ */
16663#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenP_MASK (0x3FU)
16664#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenP_SHIFT (0U)
16665#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenP(x) \
16666 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenP_SHIFT)) & \
16667 DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenP_MASK)
16668#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenN_MASK (0xFC0U)
16669#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenN_SHIFT (6U)
16670#define DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenN(x) \
16671 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenN_SHIFT)) & \
16672 DWC_DDRPHYA_DBYTE_TXODTDRVSTREN_B1_P3_ODTStrenN_MASK)
16673/*! @} */
16674
16675/*! @name TXSLEWRATE_B1_P3 - TX slew rate controls */
16676/*! @{ */
16677#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreP_MASK (0xFU)
16678#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreP_SHIFT (0U)
16679#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreP(x) \
16680 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreP_SHIFT)) & \
16681 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreP_MASK)
16682#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreN_MASK (0xF0U)
16683#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreN_SHIFT (4U)
16684#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreN(x) \
16685 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreN_SHIFT)) & \
16686 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreN_MASK)
16687#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreDrvMode_MASK (0x700U)
16688#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreDrvMode_SHIFT (8U)
16689#define DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreDrvMode(x) \
16690 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreDrvMode_SHIFT)) & \
16691 DWC_DDRPHYA_DBYTE_TXSLEWRATE_B1_P3_TxPreDrvMode_MASK)
16692/*! @} */
16693
16694/*! @name RXENDLYTG0_U1_P3 - Trained Receive Enable Delay (For Timing Group 0) */
16695/*! @{ */
16696#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RxEnDlyTg0_un_px_MASK (0x7FFU)
16697#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RxEnDlyTg0_un_px_SHIFT (0U)
16698#define DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RxEnDlyTg0_un_px(x) \
16699 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RxEnDlyTg0_un_px_SHIFT)) & \
16700 DWC_DDRPHYA_DBYTE_RXENDLYTG0_U1_P3_RxEnDlyTg0_un_px_MASK)
16701/*! @} */
16702
16703/*! @name RXENDLYTG1_U1_P3 - Trained Receive Enable Delay (For Timing Group 1) */
16704/*! @{ */
16705#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RxEnDlyTg1_un_px_MASK (0x7FFU)
16706#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RxEnDlyTg1_un_px_SHIFT (0U)
16707#define DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RxEnDlyTg1_un_px(x) \
16708 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RxEnDlyTg1_un_px_SHIFT)) & \
16709 DWC_DDRPHYA_DBYTE_RXENDLYTG1_U1_P3_RxEnDlyTg1_un_px_MASK)
16710/*! @} */
16711
16712/*! @name RXENDLYTG2_U1_P3 - Trained Receive Enable Delay (For Timing Group 2) */
16713/*! @{ */
16714#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RxEnDlyTg2_un_px_MASK (0x7FFU)
16715#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RxEnDlyTg2_un_px_SHIFT (0U)
16716#define DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RxEnDlyTg2_un_px(x) \
16717 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RxEnDlyTg2_un_px_SHIFT)) & \
16718 DWC_DDRPHYA_DBYTE_RXENDLYTG2_U1_P3_RxEnDlyTg2_un_px_MASK)
16719/*! @} */
16720
16721/*! @name RXENDLYTG3_U1_P3 - Trained Receive Enable Delay (For Timing Group 3) */
16722/*! @{ */
16723#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RxEnDlyTg3_un_px_MASK (0x7FFU)
16724#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RxEnDlyTg3_un_px_SHIFT (0U)
16725#define DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RxEnDlyTg3_un_px(x) \
16726 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RxEnDlyTg3_un_px_SHIFT)) & \
16727 DWC_DDRPHYA_DBYTE_RXENDLYTG3_U1_P3_RxEnDlyTg3_un_px_MASK)
16728/*! @} */
16729
16730/*! @name RXCLKDLYTG0_U1_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=0). */
16731/*! @{ */
16732#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RxClkDlyTg0_un_px_MASK (0x3FU)
16733#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RxClkDlyTg0_un_px_SHIFT (0U)
16734#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RxClkDlyTg0_un_px(x) \
16735 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RxClkDlyTg0_un_px_SHIFT)) & \
16736 DWC_DDRPHYA_DBYTE_RXCLKDLYTG0_U1_P3_RxClkDlyTg0_un_px_MASK)
16737/*! @} */
16738
16739/*! @name RXCLKDLYTG1_U1_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=1). */
16740/*! @{ */
16741#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RxClkDlyTg1_un_px_MASK (0x3FU)
16742#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RxClkDlyTg1_un_px_SHIFT (0U)
16743#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RxClkDlyTg1_un_px(x) \
16744 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RxClkDlyTg1_un_px_SHIFT)) & \
16745 DWC_DDRPHYA_DBYTE_RXCLKDLYTG1_U1_P3_RxClkDlyTg1_un_px_MASK)
16746/*! @} */
16747
16748/*! @name RXCLKDLYTG2_U1_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=2). */
16749/*! @{ */
16750#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RxClkDlyTg2_un_px_MASK (0x3FU)
16751#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RxClkDlyTg2_un_px_SHIFT (0U)
16752#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RxClkDlyTg2_un_px(x) \
16753 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RxClkDlyTg2_un_px_SHIFT)) & \
16754 DWC_DDRPHYA_DBYTE_RXCLKDLYTG2_U1_P3_RxClkDlyTg2_un_px_MASK)
16755/*! @} */
16756
16757/*! @name RXCLKDLYTG3_U1_P3 - Trained Read DQS to RxClk Delay (Timing Group DEST=3). */
16758/*! @{ */
16759#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RxClkDlyTg3_un_px_MASK (0x3FU)
16760#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RxClkDlyTg3_un_px_SHIFT (0U)
16761#define DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RxClkDlyTg3_un_px(x) \
16762 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RxClkDlyTg3_un_px_SHIFT)) & \
16763 DWC_DDRPHYA_DBYTE_RXCLKDLYTG3_U1_P3_RxClkDlyTg3_un_px_MASK)
16764/*! @} */
16765
16766/*! @name RXCLKCDLYTG0_U1_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
16767/*! @{ */
16768#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RxClkcDlyTg0_un_px_MASK (0x3FU)
16769#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RxClkcDlyTg0_un_px_SHIFT (0U)
16770#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RxClkcDlyTg0_un_px(x) \
16771 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RxClkcDlyTg0_un_px_SHIFT)) & \
16772 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG0_U1_P3_RxClkcDlyTg0_un_px_MASK)
16773/*! @} */
16774
16775/*! @name RXCLKCDLYTG1_U1_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=0). */
16776/*! @{ */
16777#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RxClkcDlyTg1_un_px_MASK (0x3FU)
16778#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RxClkcDlyTg1_un_px_SHIFT (0U)
16779#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RxClkcDlyTg1_un_px(x) \
16780 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RxClkcDlyTg1_un_px_SHIFT)) & \
16781 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG1_U1_P3_RxClkcDlyTg1_un_px_MASK)
16782/*! @} */
16783
16784/*! @name RXCLKCDLYTG2_U1_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=2). */
16785/*! @{ */
16786#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RxClkcDlyTg2_un_px_MASK (0x3FU)
16787#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RxClkcDlyTg2_un_px_SHIFT (0U)
16788#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RxClkcDlyTg2_un_px(x) \
16789 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RxClkcDlyTg2_un_px_SHIFT)) & \
16790 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG2_U1_P3_RxClkcDlyTg2_un_px_MASK)
16791/*! @} */
16792
16793/*! @name RXCLKCDLYTG3_U1_P3 - Trained Read DQS_c to RxClkc Delay (Timing Group DEST=3). */
16794/*! @{ */
16795#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RxClkcDlyTg3_un_px_MASK (0x3FU)
16796#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RxClkcDlyTg3_un_px_SHIFT (0U)
16797#define DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RxClkcDlyTg3_un_px(x) \
16798 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RxClkcDlyTg3_un_px_SHIFT)) & \
16799 DWC_DDRPHYA_DBYTE_RXCLKCDLYTG3_U1_P3_RxClkcDlyTg3_un_px_MASK)
16800/*! @} */
16801
16802/*! @name TXDQDLYTG0_R1_P3 - Write DQ Delay (Timing Group 0). */
16803/*! @{ */
16804#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU)
16805#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TxDqDlyTg0_rn_px_SHIFT (0U)
16806#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TxDqDlyTg0_rn_px(x) \
16807 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TxDqDlyTg0_rn_px_SHIFT)) & \
16808 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R1_P3_TxDqDlyTg0_rn_px_MASK)
16809/*! @} */
16810
16811/*! @name TXDQDLYTG1_R1_P3 - Write DQ Delay (Timing Group 1). */
16812/*! @{ */
16813#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU)
16814#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TxDqDlyTg1_rn_px_SHIFT (0U)
16815#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TxDqDlyTg1_rn_px(x) \
16816 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TxDqDlyTg1_rn_px_SHIFT)) & \
16817 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R1_P3_TxDqDlyTg1_rn_px_MASK)
16818/*! @} */
16819
16820/*! @name TXDQDLYTG2_R1_P3 - Write DQ Delay (Timing Group 2). */
16821/*! @{ */
16822#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU)
16823#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TxDqDlyTg2_rn_px_SHIFT (0U)
16824#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TxDqDlyTg2_rn_px(x) \
16825 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TxDqDlyTg2_rn_px_SHIFT)) & \
16826 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R1_P3_TxDqDlyTg2_rn_px_MASK)
16827/*! @} */
16828
16829/*! @name TXDQDLYTG3_R1_P3 - Write DQ Delay (Timing Group 3). */
16830/*! @{ */
16831#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU)
16832#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TxDqDlyTg3_rn_px_SHIFT (0U)
16833#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TxDqDlyTg3_rn_px(x) \
16834 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TxDqDlyTg3_rn_px_SHIFT)) & \
16835 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R1_P3_TxDqDlyTg3_rn_px_MASK)
16836/*! @} */
16837
16838/*! @name TXDQSDLYTG0_U1_P3 - Write DQS Delay (Timing Group DEST=0). */
16839/*! @{ */
16840#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TxDqsDlyTg0_un_px_MASK (0x3FFU)
16841#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TxDqsDlyTg0_un_px_SHIFT (0U)
16842#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TxDqsDlyTg0_un_px(x) \
16843 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TxDqsDlyTg0_un_px_SHIFT)) & \
16844 DWC_DDRPHYA_DBYTE_TXDQSDLYTG0_U1_P3_TxDqsDlyTg0_un_px_MASK)
16845/*! @} */
16846
16847/*! @name TXDQSDLYTG1_U1_P3 - Write DQS Delay (Timing Group DEST=1). */
16848/*! @{ */
16849#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TxDqsDlyTg1_un_px_MASK (0x3FFU)
16850#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TxDqsDlyTg1_un_px_SHIFT (0U)
16851#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TxDqsDlyTg1_un_px(x) \
16852 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TxDqsDlyTg1_un_px_SHIFT)) & \
16853 DWC_DDRPHYA_DBYTE_TXDQSDLYTG1_U1_P3_TxDqsDlyTg1_un_px_MASK)
16854/*! @} */
16855
16856/*! @name TXDQSDLYTG2_U1_P3 - Write DQS Delay (Timing Group DEST=2). */
16857/*! @{ */
16858#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TxDqsDlyTg2_un_px_MASK (0x3FFU)
16859#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TxDqsDlyTg2_un_px_SHIFT (0U)
16860#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TxDqsDlyTg2_un_px(x) \
16861 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TxDqsDlyTg2_un_px_SHIFT)) & \
16862 DWC_DDRPHYA_DBYTE_TXDQSDLYTG2_U1_P3_TxDqsDlyTg2_un_px_MASK)
16863/*! @} */
16864
16865/*! @name TXDQSDLYTG3_U1_P3 - Write DQS Delay (Timing Group DEST=3). */
16866/*! @{ */
16867#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TxDqsDlyTg3_un_px_MASK (0x3FFU)
16868#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TxDqsDlyTg3_un_px_SHIFT (0U)
16869#define DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TxDqsDlyTg3_un_px(x) \
16870 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TxDqsDlyTg3_un_px_SHIFT)) & \
16871 DWC_DDRPHYA_DBYTE_TXDQSDLYTG3_U1_P3_TxDqsDlyTg3_un_px_MASK)
16872/*! @} */
16873
16874/*! @name TXDQDLYTG0_R2_P3 - Write DQ Delay (Timing Group 0). */
16875/*! @{ */
16876#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU)
16877#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TxDqDlyTg0_rn_px_SHIFT (0U)
16878#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TxDqDlyTg0_rn_px(x) \
16879 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TxDqDlyTg0_rn_px_SHIFT)) & \
16880 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R2_P3_TxDqDlyTg0_rn_px_MASK)
16881/*! @} */
16882
16883/*! @name TXDQDLYTG1_R2_P3 - Write DQ Delay (Timing Group 1). */
16884/*! @{ */
16885#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU)
16886#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TxDqDlyTg1_rn_px_SHIFT (0U)
16887#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TxDqDlyTg1_rn_px(x) \
16888 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TxDqDlyTg1_rn_px_SHIFT)) & \
16889 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R2_P3_TxDqDlyTg1_rn_px_MASK)
16890/*! @} */
16891
16892/*! @name TXDQDLYTG2_R2_P3 - Write DQ Delay (Timing Group 2). */
16893/*! @{ */
16894#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU)
16895#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TxDqDlyTg2_rn_px_SHIFT (0U)
16896#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TxDqDlyTg2_rn_px(x) \
16897 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TxDqDlyTg2_rn_px_SHIFT)) & \
16898 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R2_P3_TxDqDlyTg2_rn_px_MASK)
16899/*! @} */
16900
16901/*! @name TXDQDLYTG3_R2_P3 - Write DQ Delay (Timing Group 3). */
16902/*! @{ */
16903#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU)
16904#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TxDqDlyTg3_rn_px_SHIFT (0U)
16905#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TxDqDlyTg3_rn_px(x) \
16906 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TxDqDlyTg3_rn_px_SHIFT)) & \
16907 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R2_P3_TxDqDlyTg3_rn_px_MASK)
16908/*! @} */
16909
16910/*! @name TXDQDLYTG0_R3_P3 - Write DQ Delay (Timing Group 0). */
16911/*! @{ */
16912#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU)
16913#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TxDqDlyTg0_rn_px_SHIFT (0U)
16914#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TxDqDlyTg0_rn_px(x) \
16915 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TxDqDlyTg0_rn_px_SHIFT)) & \
16916 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R3_P3_TxDqDlyTg0_rn_px_MASK)
16917/*! @} */
16918
16919/*! @name TXDQDLYTG1_R3_P3 - Write DQ Delay (Timing Group 1). */
16920/*! @{ */
16921#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU)
16922#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TxDqDlyTg1_rn_px_SHIFT (0U)
16923#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TxDqDlyTg1_rn_px(x) \
16924 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TxDqDlyTg1_rn_px_SHIFT)) & \
16925 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R3_P3_TxDqDlyTg1_rn_px_MASK)
16926/*! @} */
16927
16928/*! @name TXDQDLYTG2_R3_P3 - Write DQ Delay (Timing Group 2). */
16929/*! @{ */
16930#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU)
16931#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TxDqDlyTg2_rn_px_SHIFT (0U)
16932#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TxDqDlyTg2_rn_px(x) \
16933 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TxDqDlyTg2_rn_px_SHIFT)) & \
16934 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R3_P3_TxDqDlyTg2_rn_px_MASK)
16935/*! @} */
16936
16937/*! @name TXDQDLYTG3_R3_P3 - Write DQ Delay (Timing Group 3). */
16938/*! @{ */
16939#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU)
16940#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TxDqDlyTg3_rn_px_SHIFT (0U)
16941#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TxDqDlyTg3_rn_px(x) \
16942 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TxDqDlyTg3_rn_px_SHIFT)) & \
16943 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R3_P3_TxDqDlyTg3_rn_px_MASK)
16944/*! @} */
16945
16946/*! @name TXDQDLYTG0_R4_P3 - Write DQ Delay (Timing Group 0). */
16947/*! @{ */
16948#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU)
16949#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TxDqDlyTg0_rn_px_SHIFT (0U)
16950#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TxDqDlyTg0_rn_px(x) \
16951 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TxDqDlyTg0_rn_px_SHIFT)) & \
16952 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R4_P3_TxDqDlyTg0_rn_px_MASK)
16953/*! @} */
16954
16955/*! @name TXDQDLYTG1_R4_P3 - Write DQ Delay (Timing Group 1). */
16956/*! @{ */
16957#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU)
16958#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TxDqDlyTg1_rn_px_SHIFT (0U)
16959#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TxDqDlyTg1_rn_px(x) \
16960 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TxDqDlyTg1_rn_px_SHIFT)) & \
16961 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R4_P3_TxDqDlyTg1_rn_px_MASK)
16962/*! @} */
16963
16964/*! @name TXDQDLYTG2_R4_P3 - Write DQ Delay (Timing Group 2). */
16965/*! @{ */
16966#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU)
16967#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TxDqDlyTg2_rn_px_SHIFT (0U)
16968#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TxDqDlyTg2_rn_px(x) \
16969 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TxDqDlyTg2_rn_px_SHIFT)) & \
16970 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R4_P3_TxDqDlyTg2_rn_px_MASK)
16971/*! @} */
16972
16973/*! @name TXDQDLYTG3_R4_P3 - Write DQ Delay (Timing Group 3). */
16974/*! @{ */
16975#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU)
16976#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TxDqDlyTg3_rn_px_SHIFT (0U)
16977#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TxDqDlyTg3_rn_px(x) \
16978 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TxDqDlyTg3_rn_px_SHIFT)) & \
16979 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R4_P3_TxDqDlyTg3_rn_px_MASK)
16980/*! @} */
16981
16982/*! @name TXDQDLYTG0_R5_P3 - Write DQ Delay (Timing Group 0). */
16983/*! @{ */
16984#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU)
16985#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TxDqDlyTg0_rn_px_SHIFT (0U)
16986#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TxDqDlyTg0_rn_px(x) \
16987 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TxDqDlyTg0_rn_px_SHIFT)) & \
16988 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R5_P3_TxDqDlyTg0_rn_px_MASK)
16989/*! @} */
16990
16991/*! @name TXDQDLYTG1_R5_P3 - Write DQ Delay (Timing Group 1). */
16992/*! @{ */
16993#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU)
16994#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TxDqDlyTg1_rn_px_SHIFT (0U)
16995#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TxDqDlyTg1_rn_px(x) \
16996 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TxDqDlyTg1_rn_px_SHIFT)) & \
16997 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R5_P3_TxDqDlyTg1_rn_px_MASK)
16998/*! @} */
16999
17000/*! @name TXDQDLYTG2_R5_P3 - Write DQ Delay (Timing Group 2). */
17001/*! @{ */
17002#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU)
17003#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TxDqDlyTg2_rn_px_SHIFT (0U)
17004#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TxDqDlyTg2_rn_px(x) \
17005 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TxDqDlyTg2_rn_px_SHIFT)) & \
17006 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R5_P3_TxDqDlyTg2_rn_px_MASK)
17007/*! @} */
17008
17009/*! @name TXDQDLYTG3_R5_P3 - Write DQ Delay (Timing Group 3). */
17010/*! @{ */
17011#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU)
17012#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TxDqDlyTg3_rn_px_SHIFT (0U)
17013#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TxDqDlyTg3_rn_px(x) \
17014 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TxDqDlyTg3_rn_px_SHIFT)) & \
17015 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R5_P3_TxDqDlyTg3_rn_px_MASK)
17016/*! @} */
17017
17018/*! @name TXDQDLYTG0_R6_P3 - Write DQ Delay (Timing Group 0). */
17019/*! @{ */
17020#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU)
17021#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TxDqDlyTg0_rn_px_SHIFT (0U)
17022#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TxDqDlyTg0_rn_px(x) \
17023 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TxDqDlyTg0_rn_px_SHIFT)) & \
17024 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R6_P3_TxDqDlyTg0_rn_px_MASK)
17025/*! @} */
17026
17027/*! @name TXDQDLYTG1_R6_P3 - Write DQ Delay (Timing Group 1). */
17028/*! @{ */
17029#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU)
17030#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TxDqDlyTg1_rn_px_SHIFT (0U)
17031#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TxDqDlyTg1_rn_px(x) \
17032 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TxDqDlyTg1_rn_px_SHIFT)) & \
17033 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R6_P3_TxDqDlyTg1_rn_px_MASK)
17034/*! @} */
17035
17036/*! @name TXDQDLYTG2_R6_P3 - Write DQ Delay (Timing Group 2). */
17037/*! @{ */
17038#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU)
17039#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TxDqDlyTg2_rn_px_SHIFT (0U)
17040#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TxDqDlyTg2_rn_px(x) \
17041 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TxDqDlyTg2_rn_px_SHIFT)) & \
17042 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R6_P3_TxDqDlyTg2_rn_px_MASK)
17043/*! @} */
17044
17045/*! @name TXDQDLYTG3_R6_P3 - Write DQ Delay (Timing Group 3). */
17046/*! @{ */
17047#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU)
17048#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TxDqDlyTg3_rn_px_SHIFT (0U)
17049#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TxDqDlyTg3_rn_px(x) \
17050 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TxDqDlyTg3_rn_px_SHIFT)) & \
17051 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R6_P3_TxDqDlyTg3_rn_px_MASK)
17052/*! @} */
17053
17054/*! @name TXDQDLYTG0_R7_P3 - Write DQ Delay (Timing Group 0). */
17055/*! @{ */
17056#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU)
17057#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TxDqDlyTg0_rn_px_SHIFT (0U)
17058#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TxDqDlyTg0_rn_px(x) \
17059 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TxDqDlyTg0_rn_px_SHIFT)) & \
17060 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R7_P3_TxDqDlyTg0_rn_px_MASK)
17061/*! @} */
17062
17063/*! @name TXDQDLYTG1_R7_P3 - Write DQ Delay (Timing Group 1). */
17064/*! @{ */
17065#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU)
17066#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TxDqDlyTg1_rn_px_SHIFT (0U)
17067#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TxDqDlyTg1_rn_px(x) \
17068 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TxDqDlyTg1_rn_px_SHIFT)) & \
17069 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R7_P3_TxDqDlyTg1_rn_px_MASK)
17070/*! @} */
17071
17072/*! @name TXDQDLYTG2_R7_P3 - Write DQ Delay (Timing Group 2). */
17073/*! @{ */
17074#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU)
17075#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TxDqDlyTg2_rn_px_SHIFT (0U)
17076#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TxDqDlyTg2_rn_px(x) \
17077 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TxDqDlyTg2_rn_px_SHIFT)) & \
17078 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R7_P3_TxDqDlyTg2_rn_px_MASK)
17079/*! @} */
17080
17081/*! @name TXDQDLYTG3_R7_P3 - Write DQ Delay (Timing Group 3). */
17082/*! @{ */
17083#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU)
17084#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TxDqDlyTg3_rn_px_SHIFT (0U)
17085#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TxDqDlyTg3_rn_px(x) \
17086 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TxDqDlyTg3_rn_px_SHIFT)) & \
17087 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R7_P3_TxDqDlyTg3_rn_px_MASK)
17088/*! @} */
17089
17090/*! @name TXDQDLYTG0_R8_P3 - Write DQ Delay (Timing Group 0). */
17091/*! @{ */
17092#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TxDqDlyTg0_rn_px_MASK (0x1FFU)
17093#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TxDqDlyTg0_rn_px_SHIFT (0U)
17094#define DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TxDqDlyTg0_rn_px(x) \
17095 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TxDqDlyTg0_rn_px_SHIFT)) & \
17096 DWC_DDRPHYA_DBYTE_TXDQDLYTG0_R8_P3_TxDqDlyTg0_rn_px_MASK)
17097/*! @} */
17098
17099/*! @name TXDQDLYTG1_R8_P3 - Write DQ Delay (Timing Group 1). */
17100/*! @{ */
17101#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TxDqDlyTg1_rn_px_MASK (0x1FFU)
17102#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TxDqDlyTg1_rn_px_SHIFT (0U)
17103#define DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TxDqDlyTg1_rn_px(x) \
17104 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TxDqDlyTg1_rn_px_SHIFT)) & \
17105 DWC_DDRPHYA_DBYTE_TXDQDLYTG1_R8_P3_TxDqDlyTg1_rn_px_MASK)
17106/*! @} */
17107
17108/*! @name TXDQDLYTG2_R8_P3 - Write DQ Delay (Timing Group 2). */
17109/*! @{ */
17110#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TxDqDlyTg2_rn_px_MASK (0x1FFU)
17111#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TxDqDlyTg2_rn_px_SHIFT (0U)
17112#define DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TxDqDlyTg2_rn_px(x) \
17113 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TxDqDlyTg2_rn_px_SHIFT)) & \
17114 DWC_DDRPHYA_DBYTE_TXDQDLYTG2_R8_P3_TxDqDlyTg2_rn_px_MASK)
17115/*! @} */
17116
17117/*! @name TXDQDLYTG3_R8_P3 - Write DQ Delay (Timing Group 3). */
17118/*! @{ */
17119#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TxDqDlyTg3_rn_px_MASK (0x1FFU)
17120#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TxDqDlyTg3_rn_px_SHIFT (0U)
17121#define DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TxDqDlyTg3_rn_px(x) \
17122 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TxDqDlyTg3_rn_px_SHIFT)) & \
17123 DWC_DDRPHYA_DBYTE_TXDQDLYTG3_R8_P3_TxDqDlyTg3_rn_px_MASK)
17124/*! @} */
17125
17126/*!
17127 * @}
17128 */ /* end of group DWC_DDRPHYA_DBYTE_Register_Masks */
17129
17130/* DWC_DDRPHYA_DBYTE - Peripheral instance base addresses */
17131/** Peripheral DWC_DDRPHYA_DBYTE0 base address */
17132#define DWC_DDRPHYA_DBYTE0_BASE (0x3C010000u)
17133/** Peripheral DWC_DDRPHYA_DBYTE0 base pointer */
17134#define DWC_DDRPHYA_DBYTE0 ((DWC_DDRPHYA_DBYTE_Type *)DWC_DDRPHYA_DBYTE0_BASE)
17135/** Peripheral DWC_DDRPHYA_DBYTE1 base address */
17136#define DWC_DDRPHYA_DBYTE1_BASE (0x3C011000u)
17137/** Peripheral DWC_DDRPHYA_DBYTE1 base pointer */
17138#define DWC_DDRPHYA_DBYTE1 ((DWC_DDRPHYA_DBYTE_Type *)DWC_DDRPHYA_DBYTE1_BASE)
17139/** Peripheral DWC_DDRPHYA_DBYTE2 base address */
17140#define DWC_DDRPHYA_DBYTE2_BASE (0x3C012000u)
17141/** Peripheral DWC_DDRPHYA_DBYTE2 base pointer */
17142#define DWC_DDRPHYA_DBYTE2 ((DWC_DDRPHYA_DBYTE_Type *)DWC_DDRPHYA_DBYTE2_BASE)
17143/** Peripheral DWC_DDRPHYA_DBYTE3 base address */
17144#define DWC_DDRPHYA_DBYTE3_BASE (0x3C013000u)
17145/** Peripheral DWC_DDRPHYA_DBYTE3 base pointer */
17146#define DWC_DDRPHYA_DBYTE3 ((DWC_DDRPHYA_DBYTE_Type *)DWC_DDRPHYA_DBYTE3_BASE)
17147/** Array initializer of DWC_DDRPHYA_DBYTE peripheral base addresses */
17148#define DWC_DDRPHYA_DBYTE_BASE_ADDRS \
17149 { \
17150 DWC_DDRPHYA_DBYTE0_BASE, DWC_DDRPHYA_DBYTE1_BASE, DWC_DDRPHYA_DBYTE2_BASE, DWC_DDRPHYA_DBYTE3_BASE \
17151 }
17152/** Array initializer of DWC_DDRPHYA_DBYTE peripheral base pointers */
17153#define DWC_DDRPHYA_DBYTE_BASE_PTRS \
17154 { \
17155 DWC_DDRPHYA_DBYTE0, DWC_DDRPHYA_DBYTE1, DWC_DDRPHYA_DBYTE2, DWC_DDRPHYA_DBYTE3 \
17156 }
17157
17158/*!
17159 * @}
17160 */ /* end of group DWC_DDRPHYA_DBYTE_Peripheral_Access_Layer */
17161
17162/* ----------------------------------------------------------------------------
17163 -- DWC_DDRPHYA_DRTUB Peripheral Access Layer
17164 ---------------------------------------------------------------------------- */
17165
17166/*!
17167 * @addtogroup DWC_DDRPHYA_DRTUB_Peripheral_Access_Layer DWC_DDRPHYA_DRTUB Peripheral Access Layer
17168 * @{
17169 */
17170
17171/** DWC_DDRPHYA_DRTUB - Register Layout Typedef */
17172typedef struct
17173{
17174 uint8_t RESERVED_0[256];
17175 __IO uint16_t UCCLKHCLKENABLES; /**< Ucclk and Hclk enables, offset: 0x100 */
17176 __IO uint16_t CURPSTATE0B; /**< PIE current Pstate value, offset: 0x102 */
17177 uint8_t RESERVED_1[214];
17178 __I uint16_t CUSTPUBREV; /**< Customer settable by the customer, offset: 0x1DA */
17179 __I uint16_t PUBREV; /**< The hardware version of this PUB, excluding the PHY, offset: 0x1DC */
17180} DWC_DDRPHYA_DRTUB_Type;
17181
17182/* ----------------------------------------------------------------------------
17183 -- DWC_DDRPHYA_DRTUB Register Masks
17184 ---------------------------------------------------------------------------- */
17185
17186/*!
17187 * @addtogroup DWC_DDRPHYA_DRTUB_Register_Masks DWC_DDRPHYA_DRTUB Register Masks
17188 * @{
17189 */
17190
17191/*! @name UCCLKHCLKENABLES - Ucclk and Hclk enables */
17192/*! @{ */
17193#define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UcclkEn_MASK (0x1U)
17194#define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UcclkEn_SHIFT (0U)
17195#define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UcclkEn(x) \
17196 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UcclkEn_SHIFT)) & \
17197 DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_UcclkEn_MASK)
17198#define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HclkEn_MASK (0x2U)
17199#define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HclkEn_SHIFT (1U)
17200#define DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HclkEn(x) \
17201 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HclkEn_SHIFT)) & \
17202 DWC_DDRPHYA_DRTUB_UCCLKHCLKENABLES_HclkEn_MASK)
17203/*! @} */
17204
17205/*! @name CURPSTATE0B - PIE current Pstate value */
17206/*! @{ */
17207#define DWC_DDRPHYA_DRTUB_CURPSTATE0B_CurPstate0b_MASK (0xFU)
17208#define DWC_DDRPHYA_DRTUB_CURPSTATE0B_CurPstate0b_SHIFT (0U)
17209#define DWC_DDRPHYA_DRTUB_CURPSTATE0B_CurPstate0b(x) \
17210 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_CURPSTATE0B_CurPstate0b_SHIFT)) & \
17211 DWC_DDRPHYA_DRTUB_CURPSTATE0B_CurPstate0b_MASK)
17212/*! @} */
17213
17214/*! @name CUSTPUBREV - Customer settable by the customer */
17215/*! @{ */
17216#define DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV_MASK (0x3FU)
17217#define DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV_SHIFT (0U)
17218#define DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV(x) \
17219 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV_SHIFT)) & \
17220 DWC_DDRPHYA_DRTUB_CUSTPUBREV_CUSTPUBREV_MASK)
17221/*! @} */
17222
17223/*! @name PUBREV - The hardware version of this PUB, excluding the PHY */
17224/*! @{ */
17225#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR_MASK (0xFU)
17226#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR_SHIFT (0U)
17227#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR(x) \
17228 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR_SHIFT)) & DWC_DDRPHYA_DRTUB_PUBREV_PUBMNR_MASK)
17229#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR_MASK (0xF0U)
17230#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR_SHIFT (4U)
17231#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR(x) \
17232 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR_SHIFT)) & DWC_DDRPHYA_DRTUB_PUBREV_PUBMDR_MASK)
17233#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR_MASK (0xFF00U)
17234#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR_SHIFT (8U)
17235#define DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR(x) \
17236 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR_SHIFT)) & DWC_DDRPHYA_DRTUB_PUBREV_PUBMJR_MASK)
17237/*! @} */
17238
17239/*!
17240 * @}
17241 */ /* end of group DWC_DDRPHYA_DRTUB_Register_Masks */
17242
17243/* DWC_DDRPHYA_DRTUB - Peripheral instance base addresses */
17244/** Peripheral DWC_DDRPHYA_DRTUB0 base address */
17245#define DWC_DDRPHYA_DRTUB0_BASE (0x3C0C0000u)
17246/** Peripheral DWC_DDRPHYA_DRTUB0 base pointer */
17247#define DWC_DDRPHYA_DRTUB0 ((DWC_DDRPHYA_DRTUB_Type *)DWC_DDRPHYA_DRTUB0_BASE)
17248/** Array initializer of DWC_DDRPHYA_DRTUB peripheral base addresses */
17249#define DWC_DDRPHYA_DRTUB_BASE_ADDRS \
17250 { \
17251 DWC_DDRPHYA_DRTUB0_BASE \
17252 }
17253/** Array initializer of DWC_DDRPHYA_DRTUB peripheral base pointers */
17254#define DWC_DDRPHYA_DRTUB_BASE_PTRS \
17255 { \
17256 DWC_DDRPHYA_DRTUB0 \
17257 }
17258
17259/*!
17260 * @}
17261 */ /* end of group DWC_DDRPHYA_DRTUB_Peripheral_Access_Layer */
17262
17263/* ----------------------------------------------------------------------------
17264 -- DWC_DDRPHYA_INITENG Peripheral Access Layer
17265 ---------------------------------------------------------------------------- */
17266
17267/*!
17268 * @addtogroup DWC_DDRPHYA_INITENG_Peripheral_Access_Layer DWC_DDRPHYA_INITENG Peripheral Access Layer
17269 * @{
17270 */
17271
17272/** DWC_DDRPHYA_INITENG - Register Layout Typedef */
17273typedef struct
17274{
17275 uint8_t RESERVED_0[80];
17276 __IO uint16_t PHYINLP3; /**< Indicator for PIE Lower Power 3 (LP3) Status, offset: 0x50 */
17277} DWC_DDRPHYA_INITENG_Type;
17278
17279/* ----------------------------------------------------------------------------
17280 -- DWC_DDRPHYA_INITENG Register Masks
17281 ---------------------------------------------------------------------------- */
17282
17283/*!
17284 * @addtogroup DWC_DDRPHYA_INITENG_Register_Masks DWC_DDRPHYA_INITENG Register Masks
17285 * @{
17286 */
17287
17288/*! @name PHYINLP3 - Indicator for PIE Lower Power 3 (LP3) Status */
17289/*! @{ */
17290#define DWC_DDRPHYA_INITENG_PHYINLP3_PhyInLP3_MASK (0x1U)
17291#define DWC_DDRPHYA_INITENG_PHYINLP3_PhyInLP3_SHIFT (0U)
17292#define DWC_DDRPHYA_INITENG_PHYINLP3_PhyInLP3(x) \
17293 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_INITENG_PHYINLP3_PhyInLP3_SHIFT)) & \
17294 DWC_DDRPHYA_INITENG_PHYINLP3_PhyInLP3_MASK)
17295/*! @} */
17296
17297/*!
17298 * @}
17299 */ /* end of group DWC_DDRPHYA_INITENG_Register_Masks */
17300
17301/* DWC_DDRPHYA_INITENG - Peripheral instance base addresses */
17302/** Peripheral DWC_DDRPHYA_INITENG0 base address */
17303#define DWC_DDRPHYA_INITENG0_BASE (0x3C090000u)
17304/** Peripheral DWC_DDRPHYA_INITENG0 base pointer */
17305#define DWC_DDRPHYA_INITENG0 ((DWC_DDRPHYA_INITENG_Type *)DWC_DDRPHYA_INITENG0_BASE)
17306/** Array initializer of DWC_DDRPHYA_INITENG peripheral base addresses */
17307#define DWC_DDRPHYA_INITENG_BASE_ADDRS \
17308 { \
17309 DWC_DDRPHYA_INITENG0_BASE \
17310 }
17311/** Array initializer of DWC_DDRPHYA_INITENG peripheral base pointers */
17312#define DWC_DDRPHYA_INITENG_BASE_PTRS \
17313 { \
17314 DWC_DDRPHYA_INITENG0 \
17315 }
17316
17317/*!
17318 * @}
17319 */ /* end of group DWC_DDRPHYA_INITENG_Peripheral_Access_Layer */
17320
17321/* ----------------------------------------------------------------------------
17322 -- DWC_DDRPHYA_MASTER Peripheral Access Layer
17323 ---------------------------------------------------------------------------- */
17324
17325/*!
17326 * @addtogroup DWC_DDRPHYA_MASTER_Peripheral_Access_Layer DWC_DDRPHYA_MASTER Peripheral Access Layer
17327 * @{
17328 */
17329
17330/** DWC_DDRPHYA_MASTER - Register Layout Typedef */
17331typedef struct
17332{
17333 __IO uint16_t RXFIFOINIT; /**< Rx FIFO pointer initialization control, offset: 0x0 */
17334 __IO uint16_t FORCECLKDISABLE; /**< Clock gating control, offset: 0x2 */
17335 uint8_t RESERVED_0[2];
17336 __IO uint16_t FORCEINTERNALUPDATE; /**< This Register used by Training Firmware to force an internal PHY Update
17337 Event., offset: 0x6 */
17338 __I uint16_t PHYCONFIG; /**< Read Only displays PHY Configuration., offset: 0x8 */
17339 __IO uint16_t PGCR; /**< PHY General Configuration Register(PGCR)., offset: 0xA */
17340 uint8_t RESERVED_1[2];
17341 __IO uint16_t TESTBUMPCNTRL1; /**< Test Bump Control1, offset: 0xE */
17342 __IO uint16_t CALUCLKINFO_P0; /**< Impedance Calibration Clock Ratio, offset: 0x10 */
17343 uint8_t RESERVED_2[2];
17344 __IO uint16_t TESTBUMPCNTRL; /**< Test Bump Control, offset: 0x14 */
17345 __IO uint16_t SEQ0BDLY0_P0; /**< PHY Initialization Engine (PIE) Delay Register 0, offset: 0x16 */
17346 __IO uint16_t SEQ0BDLY1_P0; /**< PHY Initialization Engine (PIE) Delay Register 1, offset: 0x18 */
17347 __IO uint16_t SEQ0BDLY2_P0; /**< PHY Initialization Engine (PIE) Delay Register 2, offset: 0x1A */
17348 __IO uint16_t SEQ0BDLY3_P0; /**< PHY Initialization Engine (PIE) Delay Register 3, offset: 0x1C */
17349 __I uint16_t PHYALERTSTATUS; /**< PHY Alert status bit, offset: 0x1E */
17350 __IO uint16_t PPTTRAINSETUP_P0; /**< Setup Intervals for DFI PHY Master operations, offset: 0x20 */
17351 uint8_t RESERVED_3[2];
17352 __IO uint16_t ATESTMODE; /**< ATestMode control, offset: 0x24 */
17353 uint8_t RESERVED_4[2];
17354 __I uint16_t TXCALBINP; /**< TX P Impedance Calibration observation, offset: 0x28 */
17355 __I uint16_t TXCALBINN; /**< TX N Impedance Calibration observation, offset: 0x2A */
17356 __IO uint16_t TXCALPOVR; /**< TX P Impedance Calibration override, offset: 0x2C */
17357 __IO uint16_t TXCALNOVR; /**< TX N Impedance Calibration override, offset: 0x2E */
17358 __IO uint16_t DFIMODE; /**< Enables for update and low-power interfaces for DFI0 and DFI1, offset: 0x30 */
17359 __IO uint16_t TRISTATEMODECA_P0; /**< Mode select register for MEMCLK/Address/Command Tristates, offset: 0x32 */
17360 __IO uint16_t MTESTMUXSEL; /**< Digital Observation Pin control, offset: 0x34 */
17361 __IO uint16_t MTESTPGMINFO; /**< Digital Observation Pin program info for debug, offset: 0x36 */
17362 __IO uint16_t DYNPWRDNUP; /**< Dynaimc Power Up/Down control, offset: 0x38 */
17363 uint8_t RESERVED_5[2];
17364 __IO uint16_t PHYTID; /**< PHY Technology ID Register, offset: 0x3C */
17365 uint8_t RESERVED_6[2];
17366 __IO uint16_t HWTMRL_P0; /**< HWT MaxReadLatency., offset: 0x40 */
17367 __IO uint16_t DFIPHYUPD; /**< DFI PhyUpdate Request time counter (in MEMCLKs), offset: 0x42 */
17368 __IO uint16_t PDAMRSWRITEMODE; /**< Controls the write DQ generation for Per-Dram-Addressing of MRS, offset: 0x44 */
17369 __IO uint16_t
17370 DFIGEARDOWNCTL; /**< Controls whether dfi_geardown_en will cause CS and CKE timing to change., offset: 0x46 */
17371 __IO uint16_t
17372 DQSPREAMBLECONTROL_P0; /**< Control the PHY logic related to the read and write DQS preamble, offset: 0x48 */
17373 __IO uint16_t MASTERX4CONFIG; /**< DBYTE module controls to select X4 Dram device mode, offset: 0x4A */
17374 __IO uint16_t WRLEVBITS; /**< Write level feedback DQ observability select., offset: 0x4C */
17375 __IO uint16_t ENABLECSMULTICAST; /**< In DDR4 Mode , this controls whether CS_N[3:2] should be multicast on
17376 CID[1:0], offset: 0x4E */
17377 __IO uint16_t HWTLPCSMULTICAST; /**< Drives cs_n[0] onto cs_n[1] during training, offset: 0x50 */
17378 uint8_t RESERVED_7[6];
17379 __IO uint16_t ACX4ANIBDIS; /**< Disable for unused ACX Nibbles, offset: 0x58 */
17380 __IO uint16_t
17381 DMIPINPRESENT_P0; /**< This Register is used to enable the Read-DBI function in each DBYTE, offset: 0x5A */
17382 __IO uint16_t ARDPTRINITVAL_P0; /**< Address/Command FIFO ReadPointer Initial Value, offset: 0x5C */
17383 uint8_t RESERVED_8[22];
17384 __IO uint16_t DBYTEDLLMODECNTRL; /**< DLL Mode control CSR for DBYTEs, offset: 0x74 */
17385 uint8_t RESERVED_9[20];
17386 __IO uint16_t CALOFFSETS; /**< Impedance Calibration offsets control, offset: 0x8A */
17387 uint8_t RESERVED_10[2];
17388 __IO uint16_t SARINITVALS; /**< Sar Init Vals, offset: 0x8E */
17389 uint8_t RESERVED_11[2];
17390 __IO uint16_t CALPEXTOVR; /**< Impedance Calibration PExt Override control, offset: 0x92 */
17391 __IO uint16_t CALCMPR5OVR; /**< Impedance Calibration Cmpr 50 control, offset: 0x94 */
17392 __IO uint16_t CALNINTOVR; /**< Impedance Calibration NInt Override control, offset: 0x96 */
17393 uint8_t RESERVED_12[8];
17394 __IO uint16_t CALDRVSTR0; /**< Impedance Calibration driver strength control, offset: 0xA0 */
17395 uint8_t RESERVED_13[10];
17396 __IO uint16_t PROCODTTIMECTL_P0; /**< READ DATA On-Die Termination Timing Control (by PHY), offset: 0xAC */
17397 uint8_t RESERVED_14[8];
17398 __IO uint16_t MEMALERTCONTROL; /**< This Register is used to configure the MemAlert Receiver, offset: 0xB6 */
17399 __IO uint16_t MEMALERTCONTROL2; /**< This Register is used to configure the MemAlert Receiver, offset: 0xB8 */
17400 uint8_t RESERVED_15[6];
17401 __IO uint16_t MEMRESETL; /**< Protection and control of BP_MemReset_L, offset: 0xC0 */
17402 uint8_t RESERVED_16[24];
17403 __IO uint16_t DRIVECSLOWONTOHIGH; /**< Drive CS_N 3:0 onto CS_N 7:4, offset: 0xDA */
17404 __IO uint16_t PUBMODE; /**< PUBMODE - HWT Mux Select, offset: 0xDC */
17405 __I uint16_t MISCPHYSTATUS; /**< Misc PHY status bits, offset: 0xDE */
17406 __IO uint16_t CORELOOPBACKSEL; /**< Controls whether the loopback path bypasses the final PAD node., offset: 0xE0 */
17407 __IO uint16_t DLLTRAINPARAM; /**< DLL Various Training Parameters, offset: 0xE2 */
17408 uint8_t RESERVED_17[4];
17409 __IO uint16_t HWTLPCSENBYPASS; /**< CSn Disable Bypass for LPDDR3/4, offset: 0xE8 */
17410 __IO uint16_t DFICAMODE; /**< Dfi Command/Address Mode, offset: 0xEA */
17411 uint8_t RESERVED_18[4];
17412 __IO uint16_t DLLCONTROL; /**< DLL Lock State machine control register, offset: 0xF0 */
17413 __IO uint16_t PULSEDLLUPDATEPHASE; /**< DLL update phase control, offset: 0xF2 */
17414 uint8_t RESERVED_19[4];
17415 __IO uint16_t DLLGAINCTL_P0; /**< DLL gain control, offset: 0xF8 */
17416 uint8_t RESERVED_20[22];
17417 __IO uint16_t CALRATE; /**< Impedance Calibration Control, offset: 0x110 */
17418 __IO uint16_t CALZAP; /**< Impedance Calibration Zap/Reset, offset: 0x112 */
17419 uint8_t RESERVED_21[2];
17420 __IO uint16_t PSTATE; /**< PSTATE Selection, offset: 0x116 */
17421 uint8_t RESERVED_22[2];
17422 __IO uint16_t PLLOUTGATECONTROL; /**< PLL Output Control, offset: 0x11A */
17423 uint8_t RESERVED_23[4];
17424 __IO uint16_t PORCONTROL; /**< PMU Power-on Reset Control (PLL/DLL Lock Done), offset: 0x120 */
17425 uint8_t RESERVED_24[12];
17426 __I uint16_t CALBUSY; /**< Impedance Calibration Busy Status, offset: 0x12E */
17427 __IO uint16_t CALMISC2; /**< Miscellaneous impedance calibration controls., offset: 0x130 */
17428 uint8_t RESERVED_25[2];
17429 __IO uint16_t CALMISC; /**< Controls for disabling the impedance calibration of certain targets., offset: 0x134 */
17430 __I uint16_t CALVREFS; /**< , offset: 0x136 */
17431 __I uint16_t CALCMPR5; /**< Impedance Calibration Cmpr control, offset: 0x138 */
17432 __I uint16_t CALNINT; /**< Impedance Calibration NInt control, offset: 0x13A */
17433 __I uint16_t CALPEXT; /**< Impedance Calibration PExt control, offset: 0x13C */
17434 uint8_t RESERVED_26[18];
17435 __IO uint16_t CALCMPINVERT; /**< Impedance Calibration Cmp Invert control, offset: 0x150 */
17436 uint8_t RESERVED_27[10];
17437 __IO uint16_t CALCMPANACNTRL; /**< Impedance Calibration Cmpana control, offset: 0x15C */
17438 uint8_t RESERVED_28[2];
17439 __IO uint16_t DFIRDDATACSDESTMAP_P0; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4
17440 LRDIMM, offset: 0x160 */
17441 uint8_t RESERVED_29[2];
17442 __IO uint16_t VREFINGLOBAL_P0; /**< PHY Global Vref Controls, offset: 0x164 */
17443 uint8_t RESERVED_30[2];
17444 __IO uint16_t DFIWRDATACSDESTMAP_P0; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4
17445 LRDIMM, offset: 0x168 */
17446 __I uint16_t MASUPDGOODCTR; /**< Counts successful PHY Master Interface Updates (PPTs), offset: 0x16A */
17447 __I uint16_t PHYUPD0GOODCTR; /**< Counts successful PHY-initiated DFI0 Interface Updates, offset: 0x16C */
17448 __I uint16_t PHYUPD1GOODCTR; /**< Counts successful PHY-initiated DFI1 Interface Updates, offset: 0x16E */
17449 __I uint16_t CTLUPD0GOODCTR; /**< Counts successful Memory Controller DFI0 Interface Updates, offset: 0x170 */
17450 __I uint16_t CTLUPD1GOODCTR; /**< Counts successful Memory Controller DFI1 Interface Updates, offset: 0x172 */
17451 __I uint16_t MASUPDFAILCTR; /**< Counts unsuccessful PHY Master Interface Updates, offset: 0x174 */
17452 __I uint16_t PHYUPD0FAILCTR; /**< Counts unsuccessful PHY-initiated DFI0 Interface Updates, offset: 0x176 */
17453 __I uint16_t PHYUPD1FAILCTR; /**< Counts unsuccessful PHY-initiated DFI1 Interface Updates, offset: 0x178 */
17454 __IO uint16_t PHYPERFCTRENABLE; /**< Enables for Performance Counters, offset: 0x17A */
17455 uint8_t RESERVED_31[10];
17456 __IO uint16_t PLLPWRDN; /**< PLL Power Down, offset: 0x186 */
17457 __IO uint16_t PLLRESET; /**< PLL Reset, offset: 0x188 */
17458 __IO uint16_t PLLCTRL2_P0; /**< PState dependent PLL Control Register 2, offset: 0x18A */
17459 __IO uint16_t PLLCTRL0; /**< PLL Control Register 0, offset: 0x18C */
17460 __IO uint16_t PLLCTRL1_P0; /**< PState dependent PLL Control Register 1, offset: 0x18E */
17461 __IO uint16_t PLLTST; /**< PLL Testing Control Register, offset: 0x190 */
17462 __I uint16_t PLLLOCKSTATUS; /**< PLL's pll_lock pin output, offset: 0x192 */
17463 __IO uint16_t PLLTESTMODE_P0; /**< Additional controls for PLL CP/VCO modes of operation, offset: 0x194 */
17464 __IO uint16_t PLLCTRL3; /**< PLL Control Register 3, offset: 0x196 */
17465 __IO uint16_t PLLCTRL4_P0; /**< PState dependent PLL Control Register 4, offset: 0x198 */
17466 __I uint16_t PLLENDOFCAL; /**< PLL's eoc (end of calibration) output, offset: 0x19A */
17467 __I uint16_t PLLSTANDBYEFF; /**< PLL's standby_eff (effective standby) output, offset: 0x19C */
17468 __I uint16_t PLLDACVALOUT; /**< PLL's Dacval_out output, offset: 0x19E */
17469 uint8_t RESERVED_32[38];
17470 __IO uint16_t LCDLDBGCNTL; /**< Controls for use in observing and testing the LCDLs., offset: 0x1C6 */
17471 __I uint16_t ACLCDLSTATUS; /**< Debug status of the DBYTE LCDL, offset: 0x1C8 */
17472 uint8_t RESERVED_33[16];
17473 __I uint16_t CUSTPHYREV; /**< Customer settable by the customer, offset: 0x1DA */
17474 __I uint16_t PHYREV; /**< The hardware version of this PHY, excluding the PUB, offset: 0x1DC */
17475 __IO uint16_t
17476 LP3EXITSEQ0BSTARTVECTOR; /**< Start vector value to be used for LP3-exit or Init PIE Sequence, offset: 0x1DE */
17477 __IO uint16_t DFIFREQXLAT0; /**< DFI Frequency Translation Register 0, offset: 0x1E0 */
17478 __IO uint16_t DFIFREQXLAT1; /**< DFI Frequency Translation Register 1, offset: 0x1E2 */
17479 __IO uint16_t DFIFREQXLAT2; /**< DFI Frequency Translation Register 2, offset: 0x1E4 */
17480 __IO uint16_t DFIFREQXLAT3; /**< DFI Frequency Translation Register 3, offset: 0x1E6 */
17481 __IO uint16_t DFIFREQXLAT4; /**< DFI Frequency Translation Register 4, offset: 0x1E8 */
17482 __IO uint16_t DFIFREQXLAT5; /**< DFI Frequency Translation Register 5, offset: 0x1EA */
17483 __IO uint16_t DFIFREQXLAT6; /**< DFI Frequency Translation Register 6, offset: 0x1EC */
17484 __IO uint16_t DFIFREQXLAT7; /**< DFI Frequency Translation Register 7, offset: 0x1EE */
17485 __IO uint16_t TXRDPTRINIT; /**< TxRdPtrInit control register, offset: 0x1F0 */
17486 __IO uint16_t DFIINITCOMPLETE; /**< DFI Init Complete control, offset: 0x1F2 */
17487 __IO uint16_t DFIFREQRATIO_P0; /**< DFI Frequency Ratio, offset: 0x1F4 */
17488 __IO uint16_t RXFIFOCHECKS; /**< Enable more frequent consistency checks of the RX FIFOs, offset: 0x1F6 */
17489 uint8_t RESERVED_34[6];
17490 __IO uint16_t MTESTDTOCTRL; /**< , offset: 0x1FE */
17491 __IO uint16_t
17492 MAPCAA0TODFI; /**< Maps PHY CAA lane 0 from dfi0_address of the index of the register contents, offset: 0x200 */
17493 __IO uint16_t
17494 MAPCAA1TODFI; /**< Maps PHY CAA lane 1 from dfi0_address of the index of the register contents, offset: 0x202 */
17495 __IO uint16_t
17496 MAPCAA2TODFI; /**< Maps PHY CAA lane 2 from dfi0_address of the index of the register contents, offset: 0x204 */
17497 __IO uint16_t
17498 MAPCAA3TODFI; /**< Maps PHY CAA lane 3 from dfi0_address of the index of the register contents, offset: 0x206 */
17499 __IO uint16_t
17500 MAPCAA4TODFI; /**< Maps PHY CAA lane 4 from dfi0_address of the index of the register contents, offset: 0x208 */
17501 __IO uint16_t
17502 MAPCAA5TODFI; /**< Maps PHY CAA lane 5 from dfi0_address of the index of the register contents, offset: 0x20A */
17503 __IO uint16_t
17504 MAPCAA6TODFI; /**< Maps PHY CAA lane 6 from dfi0_address of the index of the register contents, offset: 0x20C */
17505 __IO uint16_t
17506 MAPCAA7TODFI; /**< Maps PHY CAA lane 7 from dfi0_address of the index of the register contents, offset: 0x20E */
17507 __IO uint16_t
17508 MAPCAA8TODFI; /**< Maps PHY CAA lane 8 from dfi0_address of the index of the register contents, offset: 0x210 */
17509 __IO uint16_t
17510 MAPCAA9TODFI; /**< Maps PHY CAA lane 9 from dfi0_address of the index of the register contents, offset: 0x212 */
17511 uint8_t RESERVED_35[12];
17512 __IO uint16_t
17513 MAPCAB0TODFI; /**< Maps PHY CAB lane 0 from dfi1_address of the index of the register contents, offset: 0x220 */
17514 __IO uint16_t
17515 MAPCAB1TODFI; /**< Maps PHY CAB lane 1 from dfi1_address of the index of the register contents, offset: 0x222 */
17516 __IO uint16_t
17517 MAPCAB2TODFI; /**< Maps PHY CAB lane 2 from dfi1_address of the index of the register contents, offset: 0x224 */
17518 __IO uint16_t
17519 MAPCAB3TODFI; /**< Maps PHY CAB lane 3 from dfi1_address of the index of the register contents, offset: 0x226 */
17520 __IO uint16_t
17521 MAPCAB4TODFI; /**< Maps PHY CAB lane 4 from dfi1_address of the index of the register contents, offset: 0x228 */
17522 __IO uint16_t
17523 MAPCAB5TODFI; /**< Maps PHY CAB lane 5 from dfi1_address of the index of the register contents, offset: 0x22A */
17524 __IO uint16_t
17525 MAPCAB6TODFI; /**< Maps PHY CAB lane 6 from dfi1_address of the index of the register contents, offset: 0x22C */
17526 __IO uint16_t
17527 MAPCAB7TODFI; /**< Maps PHY CAB lane 7 from dfi1_address of the index of the register contents, offset: 0x22E */
17528 __IO uint16_t
17529 MAPCAB8TODFI; /**< Maps PHY CAB lane 8 from dfi1_address of the index of the register contents, offset: 0x230 */
17530 __IO uint16_t
17531 MAPCAB9TODFI; /**< Maps PHY CAB lane 9 from dfi1_address of the index of the register contents, offset: 0x232 */
17532 uint8_t RESERVED_36[2];
17533 __IO uint16_t PHYINTERRUPTENABLE; /**< Interrupt Enable Bits, offset: 0x236 */
17534 __IO uint16_t PHYINTERRUPTFWCONTROL; /**< Interrupt Firmware Control Bits, offset: 0x238 */
17535 __IO uint16_t PHYINTERRUPTMASK; /**< Interrupt Mask Bits, offset: 0x23A */
17536 __IO uint16_t PHYINTERRUPTCLEAR; /**< Interrupt Clear Bits, offset: 0x23C */
17537 __I uint16_t PHYINTERRUPTSTATUS; /**< Interrupt Status Bits, offset: 0x23E */
17538 __IO uint16_t HWTSWIZZLEHWTADDRESS0; /**< Signal swizzle selection for HWT swizzle, offset: 0x240 */
17539 __IO uint16_t HWTSWIZZLEHWTADDRESS1; /**< Signal swizzle selection for HWT swizzle, offset: 0x242 */
17540 __IO uint16_t HWTSWIZZLEHWTADDRESS2; /**< Signal swizzle selection for HWT swizzle, offset: 0x244 */
17541 __IO uint16_t HWTSWIZZLEHWTADDRESS3; /**< Signal swizzle selection for HWT swizzle, offset: 0x246 */
17542 __IO uint16_t HWTSWIZZLEHWTADDRESS4; /**< Signal swizzle selection for HWT swizzle, offset: 0x248 */
17543 __IO uint16_t HWTSWIZZLEHWTADDRESS5; /**< Signal swizzle selection for HWT swizzle, offset: 0x24A */
17544 __IO uint16_t HWTSWIZZLEHWTADDRESS6; /**< Signal swizzle selection for HWT swizzle, offset: 0x24C */
17545 __IO uint16_t HWTSWIZZLEHWTADDRESS7; /**< Signal swizzle selection for HWT swizzle, offset: 0x24E */
17546 __IO uint16_t HWTSWIZZLEHWTADDRESS8; /**< Signal swizzle selection for HWT swizzle, offset: 0x250 */
17547 __IO uint16_t HWTSWIZZLEHWTADDRESS9; /**< Signal swizzle selection for HWT swizzle, offset: 0x252 */
17548 __IO uint16_t HWTSWIZZLEHWTADDRESS10; /**< Signal swizzle selection for HWT swizzle, offset: 0x254 */
17549 __IO uint16_t HWTSWIZZLEHWTADDRESS11; /**< Signal swizzle selection for HWT swizzle, offset: 0x256 */
17550 __IO uint16_t HWTSWIZZLEHWTADDRESS12; /**< Signal swizzle selection for HWT swizzle, offset: 0x258 */
17551 __IO uint16_t HWTSWIZZLEHWTADDRESS13; /**< Signal swizzle selection for HWT swizzle, offset: 0x25A */
17552 __IO uint16_t HWTSWIZZLEHWTADDRESS14; /**< Signal swizzle selection for HWT swizzle, offset: 0x25C */
17553 __IO uint16_t HWTSWIZZLEHWTADDRESS15; /**< Signal swizzle selection for HWT swizzle, offset: 0x25E */
17554 __IO uint16_t HWTSWIZZLEHWTADDRESS17; /**< Signal swizzle selection for HWT swizzle, offset: 0x260 */
17555 __IO uint16_t HWTSWIZZLEHWTACTN; /**< Signal swizzle selection for HWT swizzle, offset: 0x262 */
17556 __IO uint16_t HWTSWIZZLEHWTBANK0; /**< Signal swizzle selection for HWT swizzle, offset: 0x264 */
17557 __IO uint16_t HWTSWIZZLEHWTBANK1; /**< Signal swizzle selection for HWT swizzle, offset: 0x266 */
17558 __IO uint16_t HWTSWIZZLEHWTBANK2; /**< Signal swizzle selection for HWT swizzle, offset: 0x268 */
17559 __IO uint16_t HWTSWIZZLEHWTBG0; /**< Signal swizzle selection for HWT swizzle, offset: 0x26A */
17560 __IO uint16_t HWTSWIZZLEHWTBG1; /**< Signal swizzle selection for HWT swizzle, offset: 0x26C */
17561 __IO uint16_t HWTSWIZZLEHWTCASN; /**< Signal swizzle selection for HWT swizzle, offset: 0x26E */
17562 __IO uint16_t HWTSWIZZLEHWTRASN; /**< Signal swizzle selection for HWT swizzle, offset: 0x270 */
17563 __IO uint16_t HWTSWIZZLEHWTWEN; /**< Signal swizzle selection for HWT swizzle, offset: 0x272 */
17564 __IO uint16_t HWTSWIZZLEHWTPARITYIN; /**< Signal swizzle selection for HWT swizzle, offset: 0x274 */
17565 uint8_t RESERVED_37[2];
17566 __IO uint16_t DFIHANDSHAKEDELAYS0; /**< Add assertion/deassertion delays on handshake signals Logic assumes that dfi
17567 signal assertions exceed the programmed delays, offset: 0x278 */
17568 __IO uint16_t DFIHANDSHAKEDELAYS1; /**< Add assertion/deassertion delays on handshake signals Logic assumes that dfi
17569 signal assertions exceed the programmed delays, offset: 0x27A */
17570 uint8_t RESERVED_38[2096532];
17571 __IO uint16_t CALUCLKINFO_P1; /**< Impedance Calibration Clock Ratio, offset: 0x200010 */
17572 uint8_t RESERVED_39[4];
17573 __IO uint16_t SEQ0BDLY0_P1; /**< PHY Initialization Engine (PIE) Delay Register 0, offset: 0x200016 */
17574 __IO uint16_t SEQ0BDLY1_P1; /**< PHY Initialization Engine (PIE) Delay Register 1, offset: 0x200018 */
17575 __IO uint16_t SEQ0BDLY2_P1; /**< PHY Initialization Engine (PIE) Delay Register 2, offset: 0x20001A */
17576 __IO uint16_t SEQ0BDLY3_P1; /**< PHY Initialization Engine (PIE) Delay Register 3, offset: 0x20001C */
17577 uint8_t RESERVED_40[2];
17578 __IO uint16_t PPTTRAINSETUP_P1; /**< Setup Intervals for DFI PHY Master operations, offset: 0x200020 */
17579 uint8_t RESERVED_41[16];
17580 __IO uint16_t TRISTATEMODECA_P1; /**< Mode select register for MEMCLK/Address/Command Tristates, offset: 0x200032 */
17581 uint8_t RESERVED_42[12];
17582 __IO uint16_t HWTMRL_P1; /**< HWT MaxReadLatency., offset: 0x200040 */
17583 uint8_t RESERVED_43[6];
17584 __IO uint16_t DQSPREAMBLECONTROL_P1; /**< Control the PHY logic related to the read and write DQS preamble, offset:
17585 0x200048 */
17586 uint8_t RESERVED_44[16];
17587 __IO uint16_t
17588 DMIPINPRESENT_P1; /**< This Register is used to enable the Read-DBI function in each DBYTE, offset: 0x20005A */
17589 __IO uint16_t ARDPTRINITVAL_P1; /**< Address/Command FIFO ReadPointer Initial Value, offset: 0x20005C */
17590 uint8_t RESERVED_45[78];
17591 __IO uint16_t PROCODTTIMECTL_P1; /**< READ DATA On-Die Termination Timing Control (by PHY), offset: 0x2000AC */
17592 uint8_t RESERVED_46[74];
17593 __IO uint16_t DLLGAINCTL_P1; /**< DLL gain control, offset: 0x2000F8 */
17594 uint8_t RESERVED_47[102];
17595 __IO uint16_t DFIRDDATACSDESTMAP_P1; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4
17596 LRDIMM, offset: 0x200160 */
17597 uint8_t RESERVED_48[2];
17598 __IO uint16_t VREFINGLOBAL_P1; /**< PHY Global Vref Controls, offset: 0x200164 */
17599 uint8_t RESERVED_49[2];
17600 __IO uint16_t DFIWRDATACSDESTMAP_P1; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4
17601 LRDIMM, offset: 0x200168 */
17602 uint8_t RESERVED_50[32];
17603 __IO uint16_t PLLCTRL2_P1; /**< PState dependent PLL Control Register 2, offset: 0x20018A */
17604 uint8_t RESERVED_51[2];
17605 __IO uint16_t PLLCTRL1_P1; /**< PState dependent PLL Control Register 1, offset: 0x20018E */
17606 uint8_t RESERVED_52[4];
17607 __IO uint16_t PLLTESTMODE_P1; /**< Additional controls for PLL CP/VCO modes of operation, offset: 0x200194 */
17608 uint8_t RESERVED_53[2];
17609 __IO uint16_t PLLCTRL4_P1; /**< PState dependent PLL Control Register 4, offset: 0x200198 */
17610 uint8_t RESERVED_54[90];
17611 __IO uint16_t DFIFREQRATIO_P1; /**< DFI Frequency Ratio, offset: 0x2001F4 */
17612 uint8_t RESERVED_55[2096666];
17613 __IO uint16_t CALUCLKINFO_P2; /**< Impedance Calibration Clock Ratio, offset: 0x400010 */
17614 uint8_t RESERVED_56[4];
17615 __IO uint16_t SEQ0BDLY0_P2; /**< PHY Initialization Engine (PIE) Delay Register 0, offset: 0x400016 */
17616 __IO uint16_t SEQ0BDLY1_P2; /**< PHY Initialization Engine (PIE) Delay Register 1, offset: 0x400018 */
17617 __IO uint16_t SEQ0BDLY2_P2; /**< PHY Initialization Engine (PIE) Delay Register 2, offset: 0x40001A */
17618 __IO uint16_t SEQ0BDLY3_P2; /**< PHY Initialization Engine (PIE) Delay Register 3, offset: 0x40001C */
17619 uint8_t RESERVED_57[2];
17620 __IO uint16_t PPTTRAINSETUP_P2; /**< Setup Intervals for DFI PHY Master operations, offset: 0x400020 */
17621 uint8_t RESERVED_58[16];
17622 __IO uint16_t TRISTATEMODECA_P2; /**< Mode select register for MEMCLK/Address/Command Tristates, offset: 0x400032 */
17623 uint8_t RESERVED_59[12];
17624 __IO uint16_t HWTMRL_P2; /**< HWT MaxReadLatency., offset: 0x400040 */
17625 uint8_t RESERVED_60[6];
17626 __IO uint16_t DQSPREAMBLECONTROL_P2; /**< Control the PHY logic related to the read and write DQS preamble, offset:
17627 0x400048 */
17628 uint8_t RESERVED_61[16];
17629 __IO uint16_t
17630 DMIPINPRESENT_P2; /**< This Register is used to enable the Read-DBI function in each DBYTE, offset: 0x40005A */
17631 __IO uint16_t ARDPTRINITVAL_P2; /**< Address/Command FIFO ReadPointer Initial Value, offset: 0x40005C */
17632 uint8_t RESERVED_62[78];
17633 __IO uint16_t PROCODTTIMECTL_P2; /**< READ DATA On-Die Termination Timing Control (by PHY), offset: 0x4000AC */
17634 uint8_t RESERVED_63[74];
17635 __IO uint16_t DLLGAINCTL_P2; /**< DLL gain control, offset: 0x4000F8 */
17636 uint8_t RESERVED_64[102];
17637 __IO uint16_t DFIRDDATACSDESTMAP_P2; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4
17638 LRDIMM, offset: 0x400160 */
17639 uint8_t RESERVED_65[2];
17640 __IO uint16_t VREFINGLOBAL_P2; /**< PHY Global Vref Controls, offset: 0x400164 */
17641 uint8_t RESERVED_66[2];
17642 __IO uint16_t DFIWRDATACSDESTMAP_P2; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4
17643 LRDIMM, offset: 0x400168 */
17644 uint8_t RESERVED_67[32];
17645 __IO uint16_t PLLCTRL2_P2; /**< PState dependent PLL Control Register 2, offset: 0x40018A */
17646 uint8_t RESERVED_68[2];
17647 __IO uint16_t PLLCTRL1_P2; /**< PState dependent PLL Control Register 1, offset: 0x40018E */
17648 uint8_t RESERVED_69[4];
17649 __IO uint16_t PLLTESTMODE_P2; /**< Additional controls for PLL CP/VCO modes of operation, offset: 0x400194 */
17650 uint8_t RESERVED_70[2];
17651 __IO uint16_t PLLCTRL4_P2; /**< PState dependent PLL Control Register 4, offset: 0x400198 */
17652 uint8_t RESERVED_71[90];
17653 __IO uint16_t DFIFREQRATIO_P2; /**< DFI Frequency Ratio, offset: 0x4001F4 */
17654 uint8_t RESERVED_72[2096666];
17655 __IO uint16_t CALUCLKINFO_P3; /**< Impedance Calibration Clock Ratio, offset: 0x600010 */
17656 uint8_t RESERVED_73[4];
17657 __IO uint16_t SEQ0BDLY0_P3; /**< PHY Initialization Engine (PIE) Delay Register 0, offset: 0x600016 */
17658 __IO uint16_t SEQ0BDLY1_P3; /**< PHY Initialization Engine (PIE) Delay Register 1, offset: 0x600018 */
17659 __IO uint16_t SEQ0BDLY2_P3; /**< PHY Initialization Engine (PIE) Delay Register 2, offset: 0x60001A */
17660 __IO uint16_t SEQ0BDLY3_P3; /**< PHY Initialization Engine (PIE) Delay Register 3, offset: 0x60001C */
17661 uint8_t RESERVED_74[2];
17662 __IO uint16_t PPTTRAINSETUP_P3; /**< Setup Intervals for DFI PHY Master operations, offset: 0x600020 */
17663 uint8_t RESERVED_75[16];
17664 __IO uint16_t TRISTATEMODECA_P3; /**< Mode select register for MEMCLK/Address/Command Tristates, offset: 0x600032 */
17665 uint8_t RESERVED_76[12];
17666 __IO uint16_t HWTMRL_P3; /**< HWT MaxReadLatency., offset: 0x600040 */
17667 uint8_t RESERVED_77[6];
17668 __IO uint16_t DQSPREAMBLECONTROL_P3; /**< Control the PHY logic related to the read and write DQS preamble, offset:
17669 0x600048 */
17670 uint8_t RESERVED_78[16];
17671 __IO uint16_t
17672 DMIPINPRESENT_P3; /**< This Register is used to enable the Read-DBI function in each DBYTE, offset: 0x60005A */
17673 __IO uint16_t ARDPTRINITVAL_P3; /**< Address/Command FIFO ReadPointer Initial Value, offset: 0x60005C */
17674 uint8_t RESERVED_79[78];
17675 __IO uint16_t PROCODTTIMECTL_P3; /**< READ DATA On-Die Termination Timing Control (by PHY), offset: 0x6000AC */
17676 uint8_t RESERVED_80[74];
17677 __IO uint16_t DLLGAINCTL_P3; /**< DLL gain control, offset: 0x6000F8 */
17678 uint8_t RESERVED_81[102];
17679 __IO uint16_t DFIRDDATACSDESTMAP_P3; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4
17680 LRDIMM, offset: 0x600160 */
17681 uint8_t RESERVED_82[2];
17682 __IO uint16_t VREFINGLOBAL_P3; /**< PHY Global Vref Controls, offset: 0x600164 */
17683 uint8_t RESERVED_83[2];
17684 __IO uint16_t DFIWRDATACSDESTMAP_P3; /**< Maps dfi_rddata_cs_n to destination dimm timing group for use with D4
17685 LRDIMM, offset: 0x600168 */
17686 uint8_t RESERVED_84[32];
17687 __IO uint16_t PLLCTRL2_P3; /**< PState dependent PLL Control Register 2, offset: 0x60018A */
17688 uint8_t RESERVED_85[2];
17689 __IO uint16_t PLLCTRL1_P3; /**< PState dependent PLL Control Register 1, offset: 0x60018E */
17690 uint8_t RESERVED_86[4];
17691 __IO uint16_t PLLTESTMODE_P3; /**< Additional controls for PLL CP/VCO modes of operation, offset: 0x600194 */
17692 uint8_t RESERVED_87[2];
17693 __IO uint16_t PLLCTRL4_P3; /**< PState dependent PLL Control Register 4, offset: 0x600198 */
17694 uint8_t RESERVED_88[90];
17695 __IO uint16_t DFIFREQRATIO_P3; /**< DFI Frequency Ratio, offset: 0x6001F4 */
17696} DWC_DDRPHYA_MASTER_Type;
17697
17698/* ----------------------------------------------------------------------------
17699 -- DWC_DDRPHYA_MASTER Register Masks
17700 ---------------------------------------------------------------------------- */
17701
17702/*!
17703 * @addtogroup DWC_DDRPHYA_MASTER_Register_Masks DWC_DDRPHYA_MASTER Register Masks
17704 * @{
17705 */
17706
17707/*! @name RXFIFOINIT - Rx FIFO pointer initialization control */
17708/*! @{ */
17709#define DWC_DDRPHYA_MASTER_RXFIFOINIT_RxFifoInitPtr_MASK (0x1U)
17710#define DWC_DDRPHYA_MASTER_RXFIFOINIT_RxFifoInitPtr_SHIFT (0U)
17711#define DWC_DDRPHYA_MASTER_RXFIFOINIT_RxFifoInitPtr(x) \
17712 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_RXFIFOINIT_RxFifoInitPtr_SHIFT)) & \
17713 DWC_DDRPHYA_MASTER_RXFIFOINIT_RxFifoInitPtr_MASK)
17714#define DWC_DDRPHYA_MASTER_RXFIFOINIT_InhibitRxFifoRd_MASK (0x2U)
17715#define DWC_DDRPHYA_MASTER_RXFIFOINIT_InhibitRxFifoRd_SHIFT (1U)
17716#define DWC_DDRPHYA_MASTER_RXFIFOINIT_InhibitRxFifoRd(x) \
17717 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_RXFIFOINIT_InhibitRxFifoRd_SHIFT)) & \
17718 DWC_DDRPHYA_MASTER_RXFIFOINIT_InhibitRxFifoRd_MASK)
17719/*! @} */
17720
17721/*! @name FORCECLKDISABLE - Clock gating control */
17722/*! @{ */
17723#define DWC_DDRPHYA_MASTER_FORCECLKDISABLE_ForceClkDisable_MASK (0xFU)
17724#define DWC_DDRPHYA_MASTER_FORCECLKDISABLE_ForceClkDisable_SHIFT (0U)
17725#define DWC_DDRPHYA_MASTER_FORCECLKDISABLE_ForceClkDisable(x) \
17726 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_FORCECLKDISABLE_ForceClkDisable_SHIFT)) & \
17727 DWC_DDRPHYA_MASTER_FORCECLKDISABLE_ForceClkDisable_MASK)
17728/*! @} */
17729
17730/*! @name FORCEINTERNALUPDATE - This Register used by Training Firmware to force an internal PHY Update Event. */
17731/*! @{ */
17732#define DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_ForceInternalUpdate_MASK (0x1U)
17733#define DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_ForceInternalUpdate_SHIFT (0U)
17734#define DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_ForceInternalUpdate(x) \
17735 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_ForceInternalUpdate_SHIFT)) & \
17736 DWC_DDRPHYA_MASTER_FORCEINTERNALUPDATE_ForceInternalUpdate_MASK)
17737/*! @} */
17738
17739/*! @name PHYCONFIG - Read Only displays PHY Configuration. */
17740/*! @{ */
17741#define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigAnibs_MASK (0xFU)
17742#define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigAnibs_SHIFT (0U)
17743#define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigAnibs(x) \
17744 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigAnibs_SHIFT)) & \
17745 DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigAnibs_MASK)
17746#define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDbytes_MASK (0xF0U)
17747#define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDbytes_SHIFT (4U)
17748#define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDbytes(x) \
17749 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDbytes_SHIFT)) & \
17750 DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDbytes_MASK)
17751#define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDfi_MASK (0x300U)
17752#define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDfi_SHIFT (8U)
17753#define DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDfi(x) \
17754 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDfi_SHIFT)) & \
17755 DWC_DDRPHYA_MASTER_PHYCONFIG_PhyConfigDfi_MASK)
17756/*! @} */
17757
17758/*! @name PGCR - PHY General Configuration Register(PGCR). */
17759/*! @{ */
17760#define DWC_DDRPHYA_MASTER_PGCR_RxClkRiseFallMode_MASK (0x1U)
17761#define DWC_DDRPHYA_MASTER_PGCR_RxClkRiseFallMode_SHIFT (0U)
17762#define DWC_DDRPHYA_MASTER_PGCR_RxClkRiseFallMode(x) \
17763 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PGCR_RxClkRiseFallMode_SHIFT)) & \
17764 DWC_DDRPHYA_MASTER_PGCR_RxClkRiseFallMode_MASK)
17765/*! @} */
17766
17767/*! @name TESTBUMPCNTRL1 - Test Bump Control1 */
17768/*! @{ */
17769#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestMajorMode_MASK (0x7U)
17770#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestMajorMode_SHIFT (0U)
17771#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestMajorMode(x) \
17772 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestMajorMode_SHIFT)) & \
17773 DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestMajorMode_MASK)
17774#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestBiasBypassEn_MASK (0x8U)
17775#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestBiasBypassEn_SHIFT (3U)
17776#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestBiasBypassEn(x) \
17777 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestBiasBypassEn_SHIFT)) & \
17778 DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestBiasBypassEn_MASK)
17779#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestAnalogOutCtrl_MASK (0xF0U)
17780#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestAnalogOutCtrl_SHIFT (4U)
17781#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestAnalogOutCtrl(x) \
17782 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestAnalogOutCtrl_SHIFT)) & \
17783 DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestAnalogOutCtrl_MASK)
17784#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestGainCurrAdj_MASK (0x1F00U)
17785#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestGainCurrAdj_SHIFT (8U)
17786#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestGainCurrAdj(x) \
17787 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestGainCurrAdj_SHIFT)) & \
17788 DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestGainCurrAdj_MASK)
17789#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestSelExternalVref_MASK (0x2000U)
17790#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestSelExternalVref_SHIFT (13U)
17791#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestSelExternalVref(x) \
17792 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestSelExternalVref_SHIFT)) & \
17793 DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestSelExternalVref_MASK)
17794#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestExtVrefRange_MASK (0x4000U)
17795#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestExtVrefRange_SHIFT (14U)
17796#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestExtVrefRange(x) \
17797 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestExtVrefRange_SHIFT)) & \
17798 DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestExtVrefRange_MASK)
17799#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestPowerGateEn_MASK (0x8000U)
17800#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestPowerGateEn_SHIFT (15U)
17801#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestPowerGateEn(x) \
17802 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestPowerGateEn_SHIFT)) & \
17803 DWC_DDRPHYA_MASTER_TESTBUMPCNTRL1_TestPowerGateEn_MASK)
17804/*! @} */
17805
17806/*! @name CALUCLKINFO_P0 - Impedance Calibration Clock Ratio */
17807/*! @{ */
17808#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CalUClkTicksPer1uS_MASK (0x3FFU)
17809#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CalUClkTicksPer1uS_SHIFT (0U)
17810#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CalUClkTicksPer1uS(x) \
17811 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CalUClkTicksPer1uS_SHIFT)) & \
17812 DWC_DDRPHYA_MASTER_CALUCLKINFO_P0_CalUClkTicksPer1uS_MASK)
17813/*! @} */
17814
17815/*! @name TESTBUMPCNTRL - Test Bump Control */
17816/*! @{ */
17817#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpEn_MASK (0x3U)
17818#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpEn_SHIFT (0U)
17819#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpEn(x) \
17820 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpEn_SHIFT)) & \
17821 DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpEn_MASK)
17822#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpToggle_MASK (0x4U)
17823#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpToggle_SHIFT (2U)
17824#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpToggle(x) \
17825 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpToggle_SHIFT)) & \
17826 DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpToggle_MASK)
17827#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpDataSel_MASK (0x1F8U)
17828#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpDataSel_SHIFT (3U)
17829#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpDataSel(x) \
17830 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpDataSel_SHIFT)) & \
17831 DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_TestBumpDataSel_MASK)
17832#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_ForceMtestOnAlert_MASK (0x200U)
17833#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_ForceMtestOnAlert_SHIFT (9U)
17834#define DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_ForceMtestOnAlert(x) \
17835 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_ForceMtestOnAlert_SHIFT)) & \
17836 DWC_DDRPHYA_MASTER_TESTBUMPCNTRL_ForceMtestOnAlert_MASK)
17837/*! @} */
17838
17839/*! @name SEQ0BDLY0_P0 - PHY Initialization Engine (PIE) Delay Register 0 */
17840/*! @{ */
17841#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_Seq0BDLY0_p0_MASK (0xFFFFU)
17842#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_Seq0BDLY0_p0_SHIFT (0U)
17843#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_Seq0BDLY0_p0(x) \
17844 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_Seq0BDLY0_p0_SHIFT)) & \
17845 DWC_DDRPHYA_MASTER_SEQ0BDLY0_P0_Seq0BDLY0_p0_MASK)
17846/*! @} */
17847
17848/*! @name SEQ0BDLY1_P0 - PHY Initialization Engine (PIE) Delay Register 1 */
17849/*! @{ */
17850#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_Seq0BDLY1_p0_MASK (0xFFFFU)
17851#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_Seq0BDLY1_p0_SHIFT (0U)
17852#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_Seq0BDLY1_p0(x) \
17853 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_Seq0BDLY1_p0_SHIFT)) & \
17854 DWC_DDRPHYA_MASTER_SEQ0BDLY1_P0_Seq0BDLY1_p0_MASK)
17855/*! @} */
17856
17857/*! @name SEQ0BDLY2_P0 - PHY Initialization Engine (PIE) Delay Register 2 */
17858/*! @{ */
17859#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_Seq0BDLY2_p0_MASK (0xFFFFU)
17860#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_Seq0BDLY2_p0_SHIFT (0U)
17861#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_Seq0BDLY2_p0(x) \
17862 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_Seq0BDLY2_p0_SHIFT)) & \
17863 DWC_DDRPHYA_MASTER_SEQ0BDLY2_P0_Seq0BDLY2_p0_MASK)
17864/*! @} */
17865
17866/*! @name SEQ0BDLY3_P0 - PHY Initialization Engine (PIE) Delay Register 3 */
17867/*! @{ */
17868#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_Seq0BDLY3_p0_MASK (0xFFFFU)
17869#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_Seq0BDLY3_p0_SHIFT (0U)
17870#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_Seq0BDLY3_p0(x) \
17871 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_Seq0BDLY3_p0_SHIFT)) & \
17872 DWC_DDRPHYA_MASTER_SEQ0BDLY3_P0_Seq0BDLY3_p0_MASK)
17873/*! @} */
17874
17875/*! @name PHYALERTSTATUS - PHY Alert status bit */
17876/*! @{ */
17877#define DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PhyAlert_MASK (0x1U)
17878#define DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PhyAlert_SHIFT (0U)
17879#define DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PhyAlert(x) \
17880 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PhyAlert_SHIFT)) & \
17881 DWC_DDRPHYA_MASTER_PHYALERTSTATUS_PhyAlert_MASK)
17882/*! @} */
17883
17884/*! @name PPTTRAINSETUP_P0 - Setup Intervals for DFI PHY Master operations */
17885/*! @{ */
17886#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrTrainInterval_MASK (0xFU)
17887#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrTrainInterval_SHIFT (0U)
17888#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrTrainInterval(x) \
17889 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrTrainInterval_SHIFT)) & \
17890 DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrTrainInterval_MASK)
17891#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrMaxReqToAck_MASK (0x70U)
17892#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrMaxReqToAck_SHIFT (4U)
17893#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrMaxReqToAck(x) \
17894 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrMaxReqToAck_SHIFT)) & \
17895 DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P0_PhyMstrMaxReqToAck_MASK)
17896/*! @} */
17897
17898/*! @name ATESTMODE - ATestMode control */
17899/*! @{ */
17900#define DWC_DDRPHYA_MASTER_ATESTMODE_ATestPrbsEn_MASK (0x1U)
17901#define DWC_DDRPHYA_MASTER_ATESTMODE_ATestPrbsEn_SHIFT (0U)
17902#define DWC_DDRPHYA_MASTER_ATESTMODE_ATestPrbsEn(x) \
17903 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ATESTMODE_ATestPrbsEn_SHIFT)) & \
17904 DWC_DDRPHYA_MASTER_ATESTMODE_ATestPrbsEn_MASK)
17905#define DWC_DDRPHYA_MASTER_ATESTMODE_ATestClkEn_MASK (0x2U)
17906#define DWC_DDRPHYA_MASTER_ATESTMODE_ATestClkEn_SHIFT (1U)
17907#define DWC_DDRPHYA_MASTER_ATESTMODE_ATestClkEn(x) \
17908 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ATESTMODE_ATestClkEn_SHIFT)) & \
17909 DWC_DDRPHYA_MASTER_ATESTMODE_ATestClkEn_MASK)
17910#define DWC_DDRPHYA_MASTER_ATESTMODE_ATestModeSel_MASK (0x1CU)
17911#define DWC_DDRPHYA_MASTER_ATESTMODE_ATestModeSel_SHIFT (2U)
17912#define DWC_DDRPHYA_MASTER_ATESTMODE_ATestModeSel(x) \
17913 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ATESTMODE_ATestModeSel_SHIFT)) & \
17914 DWC_DDRPHYA_MASTER_ATESTMODE_ATestModeSel_MASK)
17915/*! @} */
17916
17917/*! @name TXCALBINP - TX P Impedance Calibration observation */
17918/*! @{ */
17919#define DWC_DDRPHYA_MASTER_TXCALBINP_TxCalBinP_MASK (0x1FU)
17920#define DWC_DDRPHYA_MASTER_TXCALBINP_TxCalBinP_SHIFT (0U)
17921#define DWC_DDRPHYA_MASTER_TXCALBINP_TxCalBinP(x) \
17922 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALBINP_TxCalBinP_SHIFT)) & \
17923 DWC_DDRPHYA_MASTER_TXCALBINP_TxCalBinP_MASK)
17924/*! @} */
17925
17926/*! @name TXCALBINN - TX N Impedance Calibration observation */
17927/*! @{ */
17928#define DWC_DDRPHYA_MASTER_TXCALBINN_TxCalBinN_MASK (0x1FU)
17929#define DWC_DDRPHYA_MASTER_TXCALBINN_TxCalBinN_SHIFT (0U)
17930#define DWC_DDRPHYA_MASTER_TXCALBINN_TxCalBinN(x) \
17931 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALBINN_TxCalBinN_SHIFT)) & \
17932 DWC_DDRPHYA_MASTER_TXCALBINN_TxCalBinN_MASK)
17933/*! @} */
17934
17935/*! @name TXCALPOVR - TX P Impedance Calibration override */
17936/*! @{ */
17937#define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrVal_MASK (0x1FU)
17938#define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrVal_SHIFT (0U)
17939#define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrVal(x) \
17940 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrVal_SHIFT)) & \
17941 DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrVal_MASK)
17942#define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrEn_MASK (0x20U)
17943#define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrEn_SHIFT (5U)
17944#define DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrEn(x) \
17945 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrEn_SHIFT)) & \
17946 DWC_DDRPHYA_MASTER_TXCALPOVR_TxCalBinPOvrEn_MASK)
17947/*! @} */
17948
17949/*! @name TXCALNOVR - TX N Impedance Calibration override */
17950/*! @{ */
17951#define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrVal_MASK (0x1FU)
17952#define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrVal_SHIFT (0U)
17953#define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrVal(x) \
17954 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrVal_SHIFT)) & \
17955 DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrVal_MASK)
17956#define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrEn_MASK (0x20U)
17957#define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrEn_SHIFT (5U)
17958#define DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrEn(x) \
17959 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrEn_SHIFT)) & \
17960 DWC_DDRPHYA_MASTER_TXCALNOVR_TxCalBinNOvrEn_MASK)
17961/*! @} */
17962
17963/*! @name DFIMODE - Enables for update and low-power interfaces for DFI0 and DFI1 */
17964/*! @{ */
17965#define DWC_DDRPHYA_MASTER_DFIMODE_Dfi0Enable_MASK (0x1U)
17966#define DWC_DDRPHYA_MASTER_DFIMODE_Dfi0Enable_SHIFT (0U)
17967#define DWC_DDRPHYA_MASTER_DFIMODE_Dfi0Enable(x) \
17968 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIMODE_Dfi0Enable_SHIFT)) & \
17969 DWC_DDRPHYA_MASTER_DFIMODE_Dfi0Enable_MASK)
17970#define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Enable_MASK (0x2U)
17971#define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Enable_SHIFT (1U)
17972#define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Enable(x) \
17973 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Enable_SHIFT)) & \
17974 DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Enable_MASK)
17975#define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Override_MASK (0x4U)
17976#define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Override_SHIFT (2U)
17977#define DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Override(x) \
17978 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Override_SHIFT)) & \
17979 DWC_DDRPHYA_MASTER_DFIMODE_Dfi1Override_MASK)
17980/*! @} */
17981
17982/*! @name TRISTATEMODECA_P0 - Mode select register for MEMCLK/Address/Command Tristates */
17983/*! @{ */
17984#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DisDynAdrTri_MASK (0x1U)
17985#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DisDynAdrTri_SHIFT (0U)
17986#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DisDynAdrTri(x) \
17987 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DisDynAdrTri_SHIFT)) & \
17988 DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DisDynAdrTri_MASK)
17989#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMode_MASK (0x2U)
17990#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMode_SHIFT (1U)
17991#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMode(x) \
17992 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMode_SHIFT)) & \
17993 DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_DDR2TMode_MASK)
17994#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CkDisVal_MASK (0xCU)
17995#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CkDisVal_SHIFT (2U)
17996#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CkDisVal(x) \
17997 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CkDisVal_SHIFT)) & \
17998 DWC_DDRPHYA_MASTER_TRISTATEMODECA_P0_CkDisVal_MASK)
17999/*! @} */
18000
18001/*! @name MTESTMUXSEL - Digital Observation Pin control */
18002/*! @{ */
18003#define DWC_DDRPHYA_MASTER_MTESTMUXSEL_MtestMuxSel_MASK (0x3FU)
18004#define DWC_DDRPHYA_MASTER_MTESTMUXSEL_MtestMuxSel_SHIFT (0U)
18005#define DWC_DDRPHYA_MASTER_MTESTMUXSEL_MtestMuxSel(x) \
18006 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MTESTMUXSEL_MtestMuxSel_SHIFT)) & \
18007 DWC_DDRPHYA_MASTER_MTESTMUXSEL_MtestMuxSel_MASK)
18008/*! @} */
18009
18010/*! @name MTESTPGMINFO - Digital Observation Pin program info for debug */
18011/*! @{ */
18012#define DWC_DDRPHYA_MASTER_MTESTPGMINFO_MtestPgmInfo_MASK (0x1U)
18013#define DWC_DDRPHYA_MASTER_MTESTPGMINFO_MtestPgmInfo_SHIFT (0U)
18014#define DWC_DDRPHYA_MASTER_MTESTPGMINFO_MtestPgmInfo(x) \
18015 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MTESTPGMINFO_MtestPgmInfo_SHIFT)) & \
18016 DWC_DDRPHYA_MASTER_MTESTPGMINFO_MtestPgmInfo_MASK)
18017/*! @} */
18018
18019/*! @name DYNPWRDNUP - Dynaimc Power Up/Down control */
18020/*! @{ */
18021#define DWC_DDRPHYA_MASTER_DYNPWRDNUP_DynPowerDown_MASK (0x1U)
18022#define DWC_DDRPHYA_MASTER_DYNPWRDNUP_DynPowerDown_SHIFT (0U)
18023#define DWC_DDRPHYA_MASTER_DYNPWRDNUP_DynPowerDown(x) \
18024 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DYNPWRDNUP_DynPowerDown_SHIFT)) & \
18025 DWC_DDRPHYA_MASTER_DYNPWRDNUP_DynPowerDown_MASK)
18026/*! @} */
18027
18028/*! @name PHYTID - PHY Technology ID Register */
18029/*! @{ */
18030#define DWC_DDRPHYA_MASTER_PHYTID_PhyTID_MASK (0xFFFFU)
18031#define DWC_DDRPHYA_MASTER_PHYTID_PhyTID_SHIFT (0U)
18032#define DWC_DDRPHYA_MASTER_PHYTID_PhyTID(x) \
18033 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYTID_PhyTID_SHIFT)) & DWC_DDRPHYA_MASTER_PHYTID_PhyTID_MASK)
18034/*! @} */
18035
18036/*! @name HWTMRL_P0 - HWT MaxReadLatency. */
18037/*! @{ */
18038#define DWC_DDRPHYA_MASTER_HWTMRL_P0_HwtMRL_p0_MASK (0x1FU)
18039#define DWC_DDRPHYA_MASTER_HWTMRL_P0_HwtMRL_p0_SHIFT (0U)
18040#define DWC_DDRPHYA_MASTER_HWTMRL_P0_HwtMRL_p0(x) \
18041 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTMRL_P0_HwtMRL_p0_SHIFT)) & \
18042 DWC_DDRPHYA_MASTER_HWTMRL_P0_HwtMRL_p0_MASK)
18043/*! @} */
18044
18045/*! @name DFIPHYUPD - DFI PhyUpdate Request time counter (in MEMCLKs) */
18046/*! @{ */
18047#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT_MASK (0xFU)
18048#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT_SHIFT (0U)
18049#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT(x) \
18050 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT_SHIFT)) & \
18051 DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDCNT_MASK)
18052#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP_MASK (0x70U)
18053#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP_SHIFT (4U)
18054#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP(x) \
18055 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP_SHIFT)) & \
18056 DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDRESP_MASK)
18057#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE_MASK (0x80U)
18058#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE_SHIFT (7U)
18059#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE(x) \
18060 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE_SHIFT)) & \
18061 DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDMODE_MASK)
18062#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD_MASK (0xF00U)
18063#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD_SHIFT (8U)
18064#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD(x) \
18065 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD_SHIFT)) & \
18066 DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDTHRESHOLD_MASK)
18067#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD_MASK (0xF000U)
18068#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD_SHIFT (12U)
18069#define DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD(x) \
18070 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD_SHIFT)) & \
18071 DWC_DDRPHYA_MASTER_DFIPHYUPD_DFIPHYUPDINTTHRESHOLD_MASK)
18072/*! @} */
18073
18074/*! @name PDAMRSWRITEMODE - Controls the write DQ generation for Per-Dram-Addressing of MRS */
18075/*! @{ */
18076#define DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PdaMrsWriteMode_MASK (0x1U)
18077#define DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PdaMrsWriteMode_SHIFT (0U)
18078#define DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PdaMrsWriteMode(x) \
18079 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PdaMrsWriteMode_SHIFT)) & \
18080 DWC_DDRPHYA_MASTER_PDAMRSWRITEMODE_PdaMrsWriteMode_MASK)
18081/*! @} */
18082
18083/*! @name DFIGEARDOWNCTL - Controls whether dfi_geardown_en will cause CS and CKE timing to change. */
18084/*! @{ */
18085#define DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL_MASK (0x3U)
18086#define DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL_SHIFT (0U)
18087#define DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL(x) \
18088 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL_SHIFT)) & \
18089 DWC_DDRPHYA_MASTER_DFIGEARDOWNCTL_DFIGEARDOWNCTL_MASK)
18090/*! @} */
18091
18092/*! @name DQSPREAMBLECONTROL_P0 - Control the PHY logic related to the read and write DQS preamble */
18093/*! @{ */
18094#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckRxDqsPre_MASK (0x1U)
18095#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckRxDqsPre_SHIFT (0U)
18096#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckRxDqsPre(x) \
18097 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckRxDqsPre_SHIFT)) & \
18098 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckRxDqsPre_MASK)
18099#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckTxDqsPre_MASK (0x2U)
18100#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckTxDqsPre_SHIFT (1U)
18101#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckTxDqsPre(x) \
18102 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckTxDqsPre_SHIFT)) & \
18103 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_TwoTckTxDqsPre_MASK)
18104#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_PositionDfeInit_MASK (0x1CU)
18105#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_PositionDfeInit_SHIFT (2U)
18106#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_PositionDfeInit(x) \
18107 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_PositionDfeInit_SHIFT)) & \
18108 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_PositionDfeInit_MASK)
18109#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TglTwoTckTxDqsPre_MASK (0x20U)
18110#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TglTwoTckTxDqsPre_SHIFT (5U)
18111#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TglTwoTckTxDqsPre(x) \
18112 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TglTwoTckTxDqsPre_SHIFT)) & \
18113 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4TglTwoTckTxDqsPre_MASK)
18114#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4PostambleExt_MASK (0x40U)
18115#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4PostambleExt_SHIFT (6U)
18116#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4PostambleExt(x) \
18117 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4PostambleExt_SHIFT)) & \
18118 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4PostambleExt_MASK)
18119#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4SttcPreBridgeRxEn_MASK (0x80U)
18120#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4SttcPreBridgeRxEn_SHIFT (7U)
18121#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4SttcPreBridgeRxEn(x) \
18122 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4SttcPreBridgeRxEn_SHIFT)) & \
18123 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_LP4SttcPreBridgeRxEn_MASK)
18124#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION_MASK (0x100U)
18125#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION_SHIFT (8U)
18126#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION(x) \
18127 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION_SHIFT)) & \
18128 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P0_WDQSEXTENSION_MASK)
18129/*! @} */
18130
18131/*! @name MASTERX4CONFIG - DBYTE module controls to select X4 Dram device mode */
18132/*! @{ */
18133#define DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG_MASK (0xFU)
18134#define DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG_SHIFT (0U)
18135#define DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG(x) \
18136 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG_SHIFT)) & \
18137 DWC_DDRPHYA_MASTER_MASTERX4CONFIG_X4TG_MASK)
18138/*! @} */
18139
18140/*! @name WRLEVBITS - Write level feedback DQ observability select. */
18141/*! @{ */
18142#define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSL_MASK (0xFU)
18143#define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSL_SHIFT (0U)
18144#define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSL(x) \
18145 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSL_SHIFT)) & \
18146 DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSL_MASK)
18147#define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSU_MASK (0xF0U)
18148#define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSU_SHIFT (4U)
18149#define DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSU(x) \
18150 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSU_SHIFT)) & \
18151 DWC_DDRPHYA_MASTER_WRLEVBITS_WrLevForDQSU_MASK)
18152/*! @} */
18153
18154/*! @name ENABLECSMULTICAST - In DDR4 Mode , this controls whether CS_N[3:2] should be multicast on CID[1:0] */
18155/*! @{ */
18156#define DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_EnableCsMulticast_MASK (0x1U)
18157#define DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_EnableCsMulticast_SHIFT (0U)
18158#define DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_EnableCsMulticast(x) \
18159 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_EnableCsMulticast_SHIFT)) & \
18160 DWC_DDRPHYA_MASTER_ENABLECSMULTICAST_EnableCsMulticast_MASK)
18161/*! @} */
18162
18163/*! @name HWTLPCSMULTICAST - Drives cs_n[0] onto cs_n[1] during training */
18164/*! @{ */
18165#define DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HwtLpCsMultiCast_MASK (0x1U)
18166#define DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HwtLpCsMultiCast_SHIFT (0U)
18167#define DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HwtLpCsMultiCast(x) \
18168 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HwtLpCsMultiCast_SHIFT)) & \
18169 DWC_DDRPHYA_MASTER_HWTLPCSMULTICAST_HwtLpCsMultiCast_MASK)
18170/*! @} */
18171
18172/*! @name ACX4ANIBDIS - Disable for unused ACX Nibbles */
18173/*! @{ */
18174#define DWC_DDRPHYA_MASTER_ACX4ANIBDIS_Acx4AnibDis_MASK (0xFFFU)
18175#define DWC_DDRPHYA_MASTER_ACX4ANIBDIS_Acx4AnibDis_SHIFT (0U)
18176#define DWC_DDRPHYA_MASTER_ACX4ANIBDIS_Acx4AnibDis(x) \
18177 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACX4ANIBDIS_Acx4AnibDis_SHIFT)) & \
18178 DWC_DDRPHYA_MASTER_ACX4ANIBDIS_Acx4AnibDis_MASK)
18179/*! @} */
18180
18181/*! @name DMIPINPRESENT_P0 - This Register is used to enable the Read-DBI function in each DBYTE */
18182/*! @{ */
18183#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RdDbiEnabled_MASK (0x1U)
18184#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RdDbiEnabled_SHIFT (0U)
18185#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RdDbiEnabled(x) \
18186 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RdDbiEnabled_SHIFT)) & \
18187 DWC_DDRPHYA_MASTER_DMIPINPRESENT_P0_RdDbiEnabled_MASK)
18188/*! @} */
18189
18190/*! @name ARDPTRINITVAL_P0 - Address/Command FIFO ReadPointer Initial Value */
18191/*! @{ */
18192#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARdPtrInitVal_p0_MASK (0xFU)
18193#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARdPtrInitVal_p0_SHIFT (0U)
18194#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARdPtrInitVal_p0(x) \
18195 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARdPtrInitVal_p0_SHIFT)) & \
18196 DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P0_ARdPtrInitVal_p0_MASK)
18197/*! @} */
18198
18199/*! @name DBYTEDLLMODECNTRL - DLL Mode control CSR for DBYTEs */
18200/*! @{ */
18201#define DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DllRxPreambleMode_MASK (0x2U)
18202#define DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DllRxPreambleMode_SHIFT (1U)
18203#define DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DllRxPreambleMode(x) \
18204 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DllRxPreambleMode_SHIFT)) & \
18205 DWC_DDRPHYA_MASTER_DBYTEDLLMODECNTRL_DllRxPreambleMode_MASK)
18206/*! @} */
18207
18208/*! @name CALOFFSETS - Impedance Calibration offsets control */
18209/*! @{ */
18210#define DWC_DDRPHYA_MASTER_CALOFFSETS_CalCmpr5Offset_MASK (0x3FU)
18211#define DWC_DDRPHYA_MASTER_CALOFFSETS_CalCmpr5Offset_SHIFT (0U)
18212#define DWC_DDRPHYA_MASTER_CALOFFSETS_CalCmpr5Offset(x) \
18213 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALOFFSETS_CalCmpr5Offset_SHIFT)) & \
18214 DWC_DDRPHYA_MASTER_CALOFFSETS_CalCmpr5Offset_MASK)
18215#define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPdThOffset_MASK (0x3C0U)
18216#define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPdThOffset_SHIFT (6U)
18217#define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPdThOffset(x) \
18218 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPdThOffset_SHIFT)) & \
18219 DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPdThOffset_MASK)
18220#define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPuThOffset_MASK (0x3C00U)
18221#define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPuThOffset_SHIFT (10U)
18222#define DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPuThOffset(x) \
18223 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPuThOffset_SHIFT)) & \
18224 DWC_DDRPHYA_MASTER_CALOFFSETS_CalDrvPuThOffset_MASK)
18225/*! @} */
18226
18227/*! @name SARINITVALS - Sar Init Vals */
18228/*! @{ */
18229#define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitOFFSET05_MASK (0x7U)
18230#define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitOFFSET05_SHIFT (0U)
18231#define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitOFFSET05(x) \
18232 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SARINITVALS_SarInitOFFSET05_SHIFT)) & \
18233 DWC_DDRPHYA_MASTER_SARINITVALS_SarInitOFFSET05_MASK)
18234#define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitNINT_MASK (0x38U)
18235#define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitNINT_SHIFT (3U)
18236#define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitNINT(x) \
18237 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SARINITVALS_SarInitNINT_SHIFT)) & \
18238 DWC_DDRPHYA_MASTER_SARINITVALS_SarInitNINT_MASK)
18239#define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitPEXT_MASK (0x1C0U)
18240#define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitPEXT_SHIFT (6U)
18241#define DWC_DDRPHYA_MASTER_SARINITVALS_SarInitPEXT(x) \
18242 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SARINITVALS_SarInitPEXT_SHIFT)) & \
18243 DWC_DDRPHYA_MASTER_SARINITVALS_SarInitPEXT_MASK)
18244/*! @} */
18245
18246/*! @name CALPEXTOVR - Impedance Calibration PExt Override control */
18247/*! @{ */
18248#define DWC_DDRPHYA_MASTER_CALPEXTOVR_CalPExtOvr_MASK (0x1FU)
18249#define DWC_DDRPHYA_MASTER_CALPEXTOVR_CalPExtOvr_SHIFT (0U)
18250#define DWC_DDRPHYA_MASTER_CALPEXTOVR_CalPExtOvr(x) \
18251 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALPEXTOVR_CalPExtOvr_SHIFT)) & \
18252 DWC_DDRPHYA_MASTER_CALPEXTOVR_CalPExtOvr_MASK)
18253/*! @} */
18254
18255/*! @name CALCMPR5OVR - Impedance Calibration Cmpr 50 control */
18256/*! @{ */
18257#define DWC_DDRPHYA_MASTER_CALCMPR5OVR_CalCmpr5Ovr_MASK (0xFFU)
18258#define DWC_DDRPHYA_MASTER_CALCMPR5OVR_CalCmpr5Ovr_SHIFT (0U)
18259#define DWC_DDRPHYA_MASTER_CALCMPR5OVR_CalCmpr5Ovr(x) \
18260 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPR5OVR_CalCmpr5Ovr_SHIFT)) & \
18261 DWC_DDRPHYA_MASTER_CALCMPR5OVR_CalCmpr5Ovr_MASK)
18262/*! @} */
18263
18264/*! @name CALNINTOVR - Impedance Calibration NInt Override control */
18265/*! @{ */
18266#define DWC_DDRPHYA_MASTER_CALNINTOVR_CalNIntOvr_MASK (0x1FU)
18267#define DWC_DDRPHYA_MASTER_CALNINTOVR_CalNIntOvr_SHIFT (0U)
18268#define DWC_DDRPHYA_MASTER_CALNINTOVR_CalNIntOvr(x) \
18269 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALNINTOVR_CalNIntOvr_SHIFT)) & \
18270 DWC_DDRPHYA_MASTER_CALNINTOVR_CalNIntOvr_MASK)
18271/*! @} */
18272
18273/*! @name CALDRVSTR0 - Impedance Calibration driver strength control */
18274/*! @{ */
18275#define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPd50_MASK (0xFU)
18276#define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPd50_SHIFT (0U)
18277#define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPd50(x) \
18278 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPd50_SHIFT)) & \
18279 DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPd50_MASK)
18280#define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPu50_MASK (0xF0U)
18281#define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPu50_SHIFT (4U)
18282#define DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPu50(x) \
18283 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPu50_SHIFT)) & \
18284 DWC_DDRPHYA_MASTER_CALDRVSTR0_CalDrvStrPu50_MASK)
18285/*! @} */
18286
18287/*! @name PROCODTTIMECTL_P0 - READ DATA On-Die Termination Timing Control (by PHY) */
18288/*! @{ */
18289#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtTailWidth_MASK (0x3U)
18290#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtTailWidth_SHIFT (0U)
18291#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtTailWidth(x) \
18292 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtTailWidth_SHIFT)) & \
18293 DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtTailWidth_MASK)
18294#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtStartDelay_MASK (0xCU)
18295#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtStartDelay_SHIFT (2U)
18296#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtStartDelay(x) \
18297 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtStartDelay_SHIFT)) & \
18298 DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P0_POdtStartDelay_MASK)
18299/*! @} */
18300
18301/*! @name MEMALERTCONTROL - This Register is used to configure the MemAlert Receiver */
18302/*! @{ */
18303#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefLevel_MASK (0x7FU)
18304#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefLevel_SHIFT (0U)
18305#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefLevel(x) \
18306 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefLevel_SHIFT)) & \
18307 DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefLevel_MASK)
18308#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefExtEn_MASK (0x80U)
18309#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefExtEn_SHIFT (7U)
18310#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefExtEn(x) \
18311 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefExtEn_SHIFT)) & \
18312 DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTVrefExtEn_MASK)
18313#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuStren_MASK (0xF00U)
18314#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuStren_SHIFT (8U)
18315#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuStren(x) \
18316 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuStren_SHIFT)) & \
18317 DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuStren_MASK)
18318#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuEn_MASK (0x1000U)
18319#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuEn_SHIFT (12U)
18320#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuEn(x) \
18321 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuEn_SHIFT)) & \
18322 DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTPuEn_MASK)
18323#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRxEn_MASK (0x2000U)
18324#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRxEn_SHIFT (13U)
18325#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRxEn(x) \
18326 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRxEn_SHIFT)) & \
18327 DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTRxEn_MASK)
18328#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDisableVal_MASK (0x4000U)
18329#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDisableVal_SHIFT (14U)
18330#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDisableVal(x) \
18331 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDisableVal_SHIFT)) & \
18332 DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTDisableVal_MASK)
18333#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTForceError_MASK (0x8000U)
18334#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTForceError_SHIFT (15U)
18335#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTForceError(x) \
18336 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTForceError_SHIFT)) & \
18337 DWC_DDRPHYA_MASTER_MEMALERTCONTROL_MALERTForceError_MASK)
18338/*! @} */
18339
18340/*! @name MEMALERTCONTROL2 - This Register is used to configure the MemAlert Receiver */
18341/*! @{ */
18342#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSyncBypass_MASK (0x1U)
18343#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSyncBypass_SHIFT (0U)
18344#define DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSyncBypass(x) \
18345 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSyncBypass_SHIFT)) & \
18346 DWC_DDRPHYA_MASTER_MEMALERTCONTROL2_MALERTSyncBypass_MASK)
18347/*! @} */
18348
18349/*! @name MEMRESETL - Protection and control of BP_MemReset_L */
18350/*! @{ */
18351#define DWC_DDRPHYA_MASTER_MEMRESETL_MemResetLValue_MASK (0x1U)
18352#define DWC_DDRPHYA_MASTER_MEMRESETL_MemResetLValue_SHIFT (0U)
18353#define DWC_DDRPHYA_MASTER_MEMRESETL_MemResetLValue(x) \
18354 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMRESETL_MemResetLValue_SHIFT)) & \
18355 DWC_DDRPHYA_MASTER_MEMRESETL_MemResetLValue_MASK)
18356#define DWC_DDRPHYA_MASTER_MEMRESETL_ProtectMemReset_MASK (0x2U)
18357#define DWC_DDRPHYA_MASTER_MEMRESETL_ProtectMemReset_SHIFT (1U)
18358#define DWC_DDRPHYA_MASTER_MEMRESETL_ProtectMemReset(x) \
18359 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MEMRESETL_ProtectMemReset_SHIFT)) & \
18360 DWC_DDRPHYA_MASTER_MEMRESETL_ProtectMemReset_MASK)
18361/*! @} */
18362
18363/*! @name DRIVECSLOWONTOHIGH - Drive CS_N 3:0 onto CS_N 7:4 */
18364/*! @{ */
18365#define DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CsLowOntoHigh_MASK (0x1U)
18366#define DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CsLowOntoHigh_SHIFT (0U)
18367#define DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CsLowOntoHigh(x) \
18368 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CsLowOntoHigh_SHIFT)) & \
18369 DWC_DDRPHYA_MASTER_DRIVECSLOWONTOHIGH_CsLowOntoHigh_MASK)
18370/*! @} */
18371
18372/*! @name PUBMODE - PUBMODE - HWT Mux Select */
18373/*! @{ */
18374#define DWC_DDRPHYA_MASTER_PUBMODE_HwtMemSrc_MASK (0x1U)
18375#define DWC_DDRPHYA_MASTER_PUBMODE_HwtMemSrc_SHIFT (0U)
18376#define DWC_DDRPHYA_MASTER_PUBMODE_HwtMemSrc(x) \
18377 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PUBMODE_HwtMemSrc_SHIFT)) & \
18378 DWC_DDRPHYA_MASTER_PUBMODE_HwtMemSrc_MASK)
18379/*! @} */
18380
18381/*! @name MISCPHYSTATUS - Misc PHY status bits */
18382/*! @{ */
18383#define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DctSane_MASK (0x1U)
18384#define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DctSane_SHIFT (0U)
18385#define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DctSane(x) \
18386 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DctSane_SHIFT)) & \
18387 DWC_DDRPHYA_MASTER_MISCPHYSTATUS_DctSane_MASK)
18388#define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMemReset_MASK (0x2U)
18389#define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMemReset_SHIFT (1U)
18390#define DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMemReset(x) \
18391 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMemReset_SHIFT)) & \
18392 DWC_DDRPHYA_MASTER_MISCPHYSTATUS_PORMemReset_MASK)
18393/*! @} */
18394
18395/*! @name CORELOOPBACKSEL - Controls whether the loopback path bypasses the final PAD node. */
18396/*! @{ */
18397#define DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CoreLoopbackSel_MASK (0x1U)
18398#define DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CoreLoopbackSel_SHIFT (0U)
18399#define DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CoreLoopbackSel(x) \
18400 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CoreLoopbackSel_SHIFT)) & \
18401 DWC_DDRPHYA_MASTER_CORELOOPBACKSEL_CoreLoopbackSel_MASK)
18402/*! @} */
18403
18404/*! @name DLLTRAINPARAM - DLL Various Training Parameters */
18405/*! @{ */
18406#define DWC_DDRPHYA_MASTER_DLLTRAINPARAM_ExtendPhdTime_MASK (0x3U)
18407#define DWC_DDRPHYA_MASTER_DLLTRAINPARAM_ExtendPhdTime_SHIFT (0U)
18408#define DWC_DDRPHYA_MASTER_DLLTRAINPARAM_ExtendPhdTime(x) \
18409 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLTRAINPARAM_ExtendPhdTime_SHIFT)) & \
18410 DWC_DDRPHYA_MASTER_DLLTRAINPARAM_ExtendPhdTime_MASK)
18411/*! @} */
18412
18413/*! @name HWTLPCSENBYPASS - CSn Disable Bypass for LPDDR3/4 */
18414/*! @{ */
18415#define DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HwtLpCsEnBypass_MASK (0x1U)
18416#define DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HwtLpCsEnBypass_SHIFT (0U)
18417#define DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HwtLpCsEnBypass(x) \
18418 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HwtLpCsEnBypass_SHIFT)) & \
18419 DWC_DDRPHYA_MASTER_HWTLPCSENBYPASS_HwtLpCsEnBypass_MASK)
18420/*! @} */
18421
18422/*! @name DFICAMODE - Dfi Command/Address Mode */
18423/*! @{ */
18424#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp3CAMode_MASK (0x1U)
18425#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp3CAMode_SHIFT (0U)
18426#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp3CAMode(x) \
18427 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp3CAMode_SHIFT)) & \
18428 DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp3CAMode_MASK)
18429#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4CAMode_MASK (0x2U)
18430#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4CAMode_SHIFT (1U)
18431#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4CAMode(x) \
18432 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4CAMode_SHIFT)) & \
18433 DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4CAMode_MASK)
18434#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp4CAMode_MASK (0x4U)
18435#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp4CAMode_SHIFT (2U)
18436#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp4CAMode(x) \
18437 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp4CAMode_SHIFT)) & \
18438 DWC_DDRPHYA_MASTER_DFICAMODE_DfiLp4CAMode_MASK)
18439#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4AltCAMode_MASK (0x8U)
18440#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4AltCAMode_SHIFT (3U)
18441#define DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4AltCAMode(x) \
18442 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4AltCAMode_SHIFT)) & \
18443 DWC_DDRPHYA_MASTER_DFICAMODE_DfiD4AltCAMode_MASK)
18444/*! @} */
18445
18446/*! @name DLLCONTROL - DLL Lock State machine control register */
18447/*! @{ */
18448#define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRelock_MASK (0x1U)
18449#define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRelock_SHIFT (0U)
18450#define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRelock(x) \
18451 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRelock_SHIFT)) & \
18452 DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRelock_MASK)
18453#define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetSlave_MASK (0x2U)
18454#define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetSlave_SHIFT (1U)
18455#define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetSlave(x) \
18456 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetSlave_SHIFT)) & \
18457 DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetSlave_MASK)
18458#define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRSVD_MASK (0x4U)
18459#define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRSVD_SHIFT (2U)
18460#define DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRSVD(x) \
18461 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRSVD_SHIFT)) & \
18462 DWC_DDRPHYA_MASTER_DLLCONTROL_DllResetRSVD_MASK)
18463/*! @} */
18464
18465/*! @name PULSEDLLUPDATEPHASE - DLL update phase control */
18466/*! @{ */
18467#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseDbyteDllUpdatePhase_MASK (0x1U)
18468#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseDbyteDllUpdatePhase_SHIFT (0U)
18469#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseDbyteDllUpdatePhase(x) \
18470 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseDbyteDllUpdatePhase_SHIFT)) & \
18471 DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseDbyteDllUpdatePhase_MASK)
18472#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACkDllUpdatePhase_MASK (0x2U)
18473#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACkDllUpdatePhase_SHIFT (1U)
18474#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACkDllUpdatePhase(x) \
18475 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACkDllUpdatePhase_SHIFT)) & \
18476 DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACkDllUpdatePhase_MASK)
18477#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACaDllUpdatePhase_MASK (0x4U)
18478#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACaDllUpdatePhase_SHIFT (2U)
18479#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACaDllUpdatePhase(x) \
18480 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACaDllUpdatePhase_SHIFT)) & \
18481 DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_PulseACaDllUpdatePhase_MASK)
18482#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UpdatePhaseDestReserved_MASK (0x38U)
18483#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UpdatePhaseDestReserved_SHIFT (3U)
18484#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UpdatePhaseDestReserved(x) \
18485 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UpdatePhaseDestReserved_SHIFT)) & \
18486 DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_UpdatePhaseDestReserved_MASK)
18487#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TrainUpdatePhaseOnLongBubble_MASK (0x40U)
18488#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TrainUpdatePhaseOnLongBubble_SHIFT (6U)
18489#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TrainUpdatePhaseOnLongBubble(x) \
18490 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TrainUpdatePhaseOnLongBubble_SHIFT)) & \
18491 DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_TrainUpdatePhaseOnLongBubble_MASK)
18492#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_AlwaysUpdateLcdlPhase_MASK (0x80U)
18493#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_AlwaysUpdateLcdlPhase_SHIFT (7U)
18494#define DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_AlwaysUpdateLcdlPhase(x) \
18495 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_AlwaysUpdateLcdlPhase_SHIFT)) & \
18496 DWC_DDRPHYA_MASTER_PULSEDLLUPDATEPHASE_AlwaysUpdateLcdlPhase_MASK)
18497/*! @} */
18498
18499/*! @name DLLGAINCTL_P0 - DLL gain control */
18500/*! @{ */
18501#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainIV_MASK (0xFU)
18502#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainIV_SHIFT (0U)
18503#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainIV(x) \
18504 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainIV_SHIFT)) & \
18505 DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainIV_MASK)
18506#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainTV_MASK (0xF0U)
18507#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainTV_SHIFT (4U)
18508#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainTV(x) \
18509 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainTV_SHIFT)) & \
18510 DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllGainTV_MASK)
18511#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllSeedSel_MASK (0xF00U)
18512#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllSeedSel_SHIFT (8U)
18513#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllSeedSel(x) \
18514 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllSeedSel_SHIFT)) & \
18515 DWC_DDRPHYA_MASTER_DLLGAINCTL_P0_DllSeedSel_MASK)
18516/*! @} */
18517
18518/*! @name CALRATE - Impedance Calibration Control */
18519/*! @{ */
18520#define DWC_DDRPHYA_MASTER_CALRATE_CalInterval_MASK (0xFU)
18521#define DWC_DDRPHYA_MASTER_CALRATE_CalInterval_SHIFT (0U)
18522#define DWC_DDRPHYA_MASTER_CALRATE_CalInterval(x) \
18523 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALRATE_CalInterval_SHIFT)) & \
18524 DWC_DDRPHYA_MASTER_CALRATE_CalInterval_MASK)
18525#define DWC_DDRPHYA_MASTER_CALRATE_CalRun_MASK (0x10U)
18526#define DWC_DDRPHYA_MASTER_CALRATE_CalRun_SHIFT (4U)
18527#define DWC_DDRPHYA_MASTER_CALRATE_CalRun(x) \
18528 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALRATE_CalRun_SHIFT)) & DWC_DDRPHYA_MASTER_CALRATE_CalRun_MASK)
18529#define DWC_DDRPHYA_MASTER_CALRATE_CalOnce_MASK (0x20U)
18530#define DWC_DDRPHYA_MASTER_CALRATE_CalOnce_SHIFT (5U)
18531#define DWC_DDRPHYA_MASTER_CALRATE_CalOnce(x) \
18532 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALRATE_CalOnce_SHIFT)) & \
18533 DWC_DDRPHYA_MASTER_CALRATE_CalOnce_MASK)
18534#define DWC_DDRPHYA_MASTER_CALRATE_DisableBackgroundZQUpdates_MASK (0x40U)
18535#define DWC_DDRPHYA_MASTER_CALRATE_DisableBackgroundZQUpdates_SHIFT (6U)
18536#define DWC_DDRPHYA_MASTER_CALRATE_DisableBackgroundZQUpdates(x) \
18537 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALRATE_DisableBackgroundZQUpdates_SHIFT)) & \
18538 DWC_DDRPHYA_MASTER_CALRATE_DisableBackgroundZQUpdates_MASK)
18539/*! @} */
18540
18541/*! @name CALZAP - Impedance Calibration Zap/Reset */
18542/*! @{ */
18543#define DWC_DDRPHYA_MASTER_CALZAP_CalZap_MASK (0x1U)
18544#define DWC_DDRPHYA_MASTER_CALZAP_CalZap_SHIFT (0U)
18545#define DWC_DDRPHYA_MASTER_CALZAP_CalZap(x) \
18546 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALZAP_CalZap_SHIFT)) & DWC_DDRPHYA_MASTER_CALZAP_CalZap_MASK)
18547/*! @} */
18548
18549/*! @name PSTATE - PSTATE Selection */
18550/*! @{ */
18551#define DWC_DDRPHYA_MASTER_PSTATE_PState_MASK (0xFU)
18552#define DWC_DDRPHYA_MASTER_PSTATE_PState_SHIFT (0U)
18553#define DWC_DDRPHYA_MASTER_PSTATE_PState(x) \
18554 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PSTATE_PState_SHIFT)) & DWC_DDRPHYA_MASTER_PSTATE_PState_MASK)
18555/*! @} */
18556
18557/*! @name PLLOUTGATECONTROL - PLL Output Control */
18558/*! @{ */
18559#define DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PclkGateEn_MASK (0x1U)
18560#define DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PclkGateEn_SHIFT (0U)
18561#define DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PclkGateEn(x) \
18562 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PclkGateEn_SHIFT)) & \
18563 DWC_DDRPHYA_MASTER_PLLOUTGATECONTROL_PclkGateEn_MASK)
18564/*! @} */
18565
18566/*! @name PORCONTROL - PMU Power-on Reset Control (PLL/DLL Lock Done) */
18567/*! @{ */
18568#define DWC_DDRPHYA_MASTER_PORCONTROL_PllDllLockDone_MASK (0x1U)
18569#define DWC_DDRPHYA_MASTER_PORCONTROL_PllDllLockDone_SHIFT (0U)
18570#define DWC_DDRPHYA_MASTER_PORCONTROL_PllDllLockDone(x) \
18571 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PORCONTROL_PllDllLockDone_SHIFT)) & \
18572 DWC_DDRPHYA_MASTER_PORCONTROL_PllDllLockDone_MASK)
18573/*! @} */
18574
18575/*! @name CALBUSY - Impedance Calibration Busy Status */
18576/*! @{ */
18577#define DWC_DDRPHYA_MASTER_CALBUSY_CalBusy_MASK (0x1U)
18578#define DWC_DDRPHYA_MASTER_CALBUSY_CalBusy_SHIFT (0U)
18579#define DWC_DDRPHYA_MASTER_CALBUSY_CalBusy(x) \
18580 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALBUSY_CalBusy_SHIFT)) & \
18581 DWC_DDRPHYA_MASTER_CALBUSY_CalBusy_MASK)
18582/*! @} */
18583
18584/*! @name CALMISC2 - Miscellaneous impedance calibration controls. */
18585/*! @{ */
18586#define DWC_DDRPHYA_MASTER_CALMISC2_CalNumVotes_MASK (0x7U)
18587#define DWC_DDRPHYA_MASTER_CALMISC2_CalNumVotes_SHIFT (0U)
18588#define DWC_DDRPHYA_MASTER_CALMISC2_CalNumVotes(x) \
18589 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC2_CalNumVotes_SHIFT)) & \
18590 DWC_DDRPHYA_MASTER_CALMISC2_CalNumVotes_MASK)
18591#define DWC_DDRPHYA_MASTER_CALMISC2_CalCmptrResTrim_MASK (0x1000U)
18592#define DWC_DDRPHYA_MASTER_CALMISC2_CalCmptrResTrim_SHIFT (12U)
18593#define DWC_DDRPHYA_MASTER_CALMISC2_CalCmptrResTrim(x) \
18594 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC2_CalCmptrResTrim_SHIFT)) & \
18595 DWC_DDRPHYA_MASTER_CALMISC2_CalCmptrResTrim_MASK)
18596#define DWC_DDRPHYA_MASTER_CALMISC2_CalCancelRoundErrDis_MASK (0x2000U)
18597#define DWC_DDRPHYA_MASTER_CALMISC2_CalCancelRoundErrDis_SHIFT (13U)
18598#define DWC_DDRPHYA_MASTER_CALMISC2_CalCancelRoundErrDis(x) \
18599 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC2_CalCancelRoundErrDis_SHIFT)) & \
18600 DWC_DDRPHYA_MASTER_CALMISC2_CalCancelRoundErrDis_MASK)
18601#define DWC_DDRPHYA_MASTER_CALMISC2_CalSlowCmpana_MASK (0x4000U)
18602#define DWC_DDRPHYA_MASTER_CALMISC2_CalSlowCmpana_SHIFT (14U)
18603#define DWC_DDRPHYA_MASTER_CALMISC2_CalSlowCmpana(x) \
18604 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC2_CalSlowCmpana_SHIFT)) & \
18605 DWC_DDRPHYA_MASTER_CALMISC2_CalSlowCmpana_MASK)
18606/*! @} */
18607
18608/*! @name CALMISC - Controls for disabling the impedance calibration of certain targets. */
18609/*! @{ */
18610#define DWC_DDRPHYA_MASTER_CALMISC_CalCmpr5Dis_MASK (0x1U)
18611#define DWC_DDRPHYA_MASTER_CALMISC_CalCmpr5Dis_SHIFT (0U)
18612#define DWC_DDRPHYA_MASTER_CALMISC_CalCmpr5Dis(x) \
18613 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC_CalCmpr5Dis_SHIFT)) & \
18614 DWC_DDRPHYA_MASTER_CALMISC_CalCmpr5Dis_MASK)
18615#define DWC_DDRPHYA_MASTER_CALMISC_CalNIntDis_MASK (0x2U)
18616#define DWC_DDRPHYA_MASTER_CALMISC_CalNIntDis_SHIFT (1U)
18617#define DWC_DDRPHYA_MASTER_CALMISC_CalNIntDis(x) \
18618 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC_CalNIntDis_SHIFT)) & \
18619 DWC_DDRPHYA_MASTER_CALMISC_CalNIntDis_MASK)
18620#define DWC_DDRPHYA_MASTER_CALMISC_CalPExtDis_MASK (0x4U)
18621#define DWC_DDRPHYA_MASTER_CALMISC_CalPExtDis_SHIFT (2U)
18622#define DWC_DDRPHYA_MASTER_CALMISC_CalPExtDis(x) \
18623 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALMISC_CalPExtDis_SHIFT)) & \
18624 DWC_DDRPHYA_MASTER_CALMISC_CalPExtDis_MASK)
18625/*! @} */
18626
18627/*! @name CALVREFS - */
18628/*! @{ */
18629#define DWC_DDRPHYA_MASTER_CALVREFS_CalVRefs_MASK (0x3U)
18630#define DWC_DDRPHYA_MASTER_CALVREFS_CalVRefs_SHIFT (0U)
18631#define DWC_DDRPHYA_MASTER_CALVREFS_CalVRefs(x) \
18632 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALVREFS_CalVRefs_SHIFT)) & \
18633 DWC_DDRPHYA_MASTER_CALVREFS_CalVRefs_MASK)
18634/*! @} */
18635
18636/*! @name CALCMPR5 - Impedance Calibration Cmpr control */
18637/*! @{ */
18638#define DWC_DDRPHYA_MASTER_CALCMPR5_CalCmpr5_MASK (0xFFU)
18639#define DWC_DDRPHYA_MASTER_CALCMPR5_CalCmpr5_SHIFT (0U)
18640#define DWC_DDRPHYA_MASTER_CALCMPR5_CalCmpr5(x) \
18641 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPR5_CalCmpr5_SHIFT)) & \
18642 DWC_DDRPHYA_MASTER_CALCMPR5_CalCmpr5_MASK)
18643/*! @} */
18644
18645/*! @name CALNINT - Impedance Calibration NInt control */
18646/*! @{ */
18647#define DWC_DDRPHYA_MASTER_CALNINT_CalNIntThB_MASK (0x1FU)
18648#define DWC_DDRPHYA_MASTER_CALNINT_CalNIntThB_SHIFT (0U)
18649#define DWC_DDRPHYA_MASTER_CALNINT_CalNIntThB(x) \
18650 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALNINT_CalNIntThB_SHIFT)) & \
18651 DWC_DDRPHYA_MASTER_CALNINT_CalNIntThB_MASK)
18652/*! @} */
18653
18654/*! @name CALPEXT - Impedance Calibration PExt control */
18655/*! @{ */
18656#define DWC_DDRPHYA_MASTER_CALPEXT_CalPExtThB_MASK (0x1FU)
18657#define DWC_DDRPHYA_MASTER_CALPEXT_CalPExtThB_SHIFT (0U)
18658#define DWC_DDRPHYA_MASTER_CALPEXT_CalPExtThB(x) \
18659 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALPEXT_CalPExtThB_SHIFT)) & \
18660 DWC_DDRPHYA_MASTER_CALPEXT_CalPExtThB_MASK)
18661/*! @} */
18662
18663/*! @name CALCMPINVERT - Impedance Calibration Cmp Invert control */
18664/*! @{ */
18665#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDac50_MASK (0x1U)
18666#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDac50_SHIFT (0U)
18667#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDac50(x) \
18668 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDac50_SHIFT)) & \
18669 DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDac50_MASK)
18670#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPd50_MASK (0x2U)
18671#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPd50_SHIFT (1U)
18672#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPd50(x) \
18673 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPd50_SHIFT)) & \
18674 DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPd50_MASK)
18675#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPu50_MASK (0x4U)
18676#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPu50_SHIFT (2U)
18677#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPu50(x) \
18678 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPu50_SHIFT)) & \
18679 DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalDrvPu50_MASK)
18680#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPd_MASK (0x8U)
18681#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPd_SHIFT (3U)
18682#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPd(x) \
18683 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPd_SHIFT)) & \
18684 DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPd_MASK)
18685#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPu_MASK (0x10U)
18686#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPu_SHIFT (4U)
18687#define DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPu(x) \
18688 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPu_SHIFT)) & \
18689 DWC_DDRPHYA_MASTER_CALCMPINVERT_CmpInvertCalOdtPu_MASK)
18690/*! @} */
18691
18692/*! @name CALCMPANACNTRL - Impedance Calibration Cmpana control */
18693/*! @{ */
18694#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainCurrAdj_MASK (0xFFU)
18695#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainCurrAdj_SHIFT (0U)
18696#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainCurrAdj(x) \
18697 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainCurrAdj_SHIFT)) & \
18698 DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainCurrAdj_MASK)
18699#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainResAdj_MASK (0x100U)
18700#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainResAdj_SHIFT (8U)
18701#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainResAdj(x) \
18702 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainResAdj_SHIFT)) & \
18703 DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprGainResAdj_MASK)
18704#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprBiasBypassEn_MASK (0x200U)
18705#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprBiasBypassEn_SHIFT (9U)
18706#define DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprBiasBypassEn(x) \
18707 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprBiasBypassEn_SHIFT)) & \
18708 DWC_DDRPHYA_MASTER_CALCMPANACNTRL_CmprBiasBypassEn_MASK)
18709/*! @} */
18710
18711/*! @name DFIRDDATACSDESTMAP_P0 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
18712/*! @{ */
18713#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm0_MASK (0x3U)
18714#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm0_SHIFT (0U)
18715#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm0(x) \
18716 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm0_SHIFT)) & \
18717 DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm0_MASK)
18718#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm1_MASK (0xCU)
18719#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm1_SHIFT (2U)
18720#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm1(x) \
18721 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm1_SHIFT)) & \
18722 DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm1_MASK)
18723#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm2_MASK (0x30U)
18724#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm2_SHIFT (4U)
18725#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm2(x) \
18726 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm2_SHIFT)) & \
18727 DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm2_MASK)
18728#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm3_MASK (0xC0U)
18729#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm3_SHIFT (6U)
18730#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm3(x) \
18731 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm3_SHIFT)) & \
18732 DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P0_DfiRdDestm3_MASK)
18733/*! @} */
18734
18735/*! @name VREFINGLOBAL_P0 - PHY Global Vref Controls */
18736/*! @{ */
18737#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInSel_MASK (0x7U)
18738#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInSel_SHIFT (0U)
18739#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInSel(x) \
18740 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInSel_SHIFT)) & \
18741 DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInSel_MASK)
18742#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInDAC_MASK (0x3F8U)
18743#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInDAC_SHIFT (3U)
18744#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInDAC(x) \
18745 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInDAC_SHIFT)) & \
18746 DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInDAC_MASK)
18747#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInTrim_MASK (0x3C00U)
18748#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInTrim_SHIFT (10U)
18749#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInTrim(x) \
18750 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInTrim_SHIFT)) & \
18751 DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInTrim_MASK)
18752#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInMode_MASK (0x4000U)
18753#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInMode_SHIFT (14U)
18754#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInMode(x) \
18755 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInMode_SHIFT)) & \
18756 DWC_DDRPHYA_MASTER_VREFINGLOBAL_P0_GlobalVrefInMode_MASK)
18757/*! @} */
18758
18759/*! @name DFIWRDATACSDESTMAP_P0 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
18760/*! @{ */
18761#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm0_MASK (0x3U)
18762#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm0_SHIFT (0U)
18763#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm0(x) \
18764 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm0_SHIFT)) & \
18765 DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm0_MASK)
18766#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm1_MASK (0xCU)
18767#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm1_SHIFT (2U)
18768#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm1(x) \
18769 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm1_SHIFT)) & \
18770 DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm1_MASK)
18771#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm2_MASK (0x30U)
18772#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm2_SHIFT (4U)
18773#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm2(x) \
18774 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm2_SHIFT)) & \
18775 DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm2_MASK)
18776#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm3_MASK (0xC0U)
18777#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm3_SHIFT (6U)
18778#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm3(x) \
18779 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm3_SHIFT)) & \
18780 DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P0_DfiWrDestm3_MASK)
18781/*! @} */
18782
18783/*! @name MASUPDGOODCTR - Counts successful PHY Master Interface Updates (PPTs) */
18784/*! @{ */
18785#define DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MasUpdGoodCtr_MASK (0xFFFFU)
18786#define DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MasUpdGoodCtr_SHIFT (0U)
18787#define DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MasUpdGoodCtr(x) \
18788 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MasUpdGoodCtr_SHIFT)) & \
18789 DWC_DDRPHYA_MASTER_MASUPDGOODCTR_MasUpdGoodCtr_MASK)
18790/*! @} */
18791
18792/*! @name PHYUPD0GOODCTR - Counts successful PHY-initiated DFI0 Interface Updates */
18793/*! @{ */
18794#define DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PhyUpd0GoodCtr_MASK (0xFFFFU)
18795#define DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PhyUpd0GoodCtr_SHIFT (0U)
18796#define DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PhyUpd0GoodCtr(x) \
18797 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PhyUpd0GoodCtr_SHIFT)) & \
18798 DWC_DDRPHYA_MASTER_PHYUPD0GOODCTR_PhyUpd0GoodCtr_MASK)
18799/*! @} */
18800
18801/*! @name PHYUPD1GOODCTR - Counts successful PHY-initiated DFI1 Interface Updates */
18802/*! @{ */
18803#define DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PhyUpd1GoodCtr_MASK (0xFFFFU)
18804#define DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PhyUpd1GoodCtr_SHIFT (0U)
18805#define DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PhyUpd1GoodCtr(x) \
18806 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PhyUpd1GoodCtr_SHIFT)) & \
18807 DWC_DDRPHYA_MASTER_PHYUPD1GOODCTR_PhyUpd1GoodCtr_MASK)
18808/*! @} */
18809
18810/*! @name CTLUPD0GOODCTR - Counts successful Memory Controller DFI0 Interface Updates */
18811/*! @{ */
18812#define DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CtlUpd0GoodCtr_MASK (0xFFFFU)
18813#define DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CtlUpd0GoodCtr_SHIFT (0U)
18814#define DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CtlUpd0GoodCtr(x) \
18815 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CtlUpd0GoodCtr_SHIFT)) & \
18816 DWC_DDRPHYA_MASTER_CTLUPD0GOODCTR_CtlUpd0GoodCtr_MASK)
18817/*! @} */
18818
18819/*! @name CTLUPD1GOODCTR - Counts successful Memory Controller DFI1 Interface Updates */
18820/*! @{ */
18821#define DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CtlUpd1GoodCtr_MASK (0xFFFFU)
18822#define DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CtlUpd1GoodCtr_SHIFT (0U)
18823#define DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CtlUpd1GoodCtr(x) \
18824 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CtlUpd1GoodCtr_SHIFT)) & \
18825 DWC_DDRPHYA_MASTER_CTLUPD1GOODCTR_CtlUpd1GoodCtr_MASK)
18826/*! @} */
18827
18828/*! @name MASUPDFAILCTR - Counts unsuccessful PHY Master Interface Updates */
18829/*! @{ */
18830#define DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MasUpdFailCtr_MASK (0xFFFFU)
18831#define DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MasUpdFailCtr_SHIFT (0U)
18832#define DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MasUpdFailCtr(x) \
18833 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MasUpdFailCtr_SHIFT)) & \
18834 DWC_DDRPHYA_MASTER_MASUPDFAILCTR_MasUpdFailCtr_MASK)
18835/*! @} */
18836
18837/*! @name PHYUPD0FAILCTR - Counts unsuccessful PHY-initiated DFI0 Interface Updates */
18838/*! @{ */
18839#define DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PhyUpd0FailCtr_MASK (0xFFFFU)
18840#define DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PhyUpd0FailCtr_SHIFT (0U)
18841#define DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PhyUpd0FailCtr(x) \
18842 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PhyUpd0FailCtr_SHIFT)) & \
18843 DWC_DDRPHYA_MASTER_PHYUPD0FAILCTR_PhyUpd0FailCtr_MASK)
18844/*! @} */
18845
18846/*! @name PHYUPD1FAILCTR - Counts unsuccessful PHY-initiated DFI1 Interface Updates */
18847/*! @{ */
18848#define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PhyUpd1FailCtr_MASK (0xFFFFU)
18849#define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PhyUpd1FailCtr_SHIFT (0U)
18850#define DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PhyUpd1FailCtr(x) \
18851 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PhyUpd1FailCtr_SHIFT)) & \
18852 DWC_DDRPHYA_MASTER_PHYUPD1FAILCTR_PhyUpd1FailCtr_MASK)
18853/*! @} */
18854
18855/*! @name PHYPERFCTRENABLE - Enables for Performance Counters */
18856/*! @{ */
18857#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdGoodCtl_MASK (0x1U)
18858#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdGoodCtl_SHIFT (0U)
18859#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdGoodCtl(x) \
18860 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdGoodCtl_SHIFT)) & \
18861 DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdGoodCtl_MASK)
18862#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0GoodCtl_MASK (0x2U)
18863#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0GoodCtl_SHIFT (1U)
18864#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0GoodCtl(x) \
18865 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0GoodCtl_SHIFT)) & \
18866 DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0GoodCtl_MASK)
18867#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1GoodCtl_MASK (0x4U)
18868#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1GoodCtl_SHIFT (2U)
18869#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1GoodCtl(x) \
18870 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1GoodCtl_SHIFT)) & \
18871 DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1GoodCtl_MASK)
18872#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd0GoodCtl_MASK (0x8U)
18873#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd0GoodCtl_SHIFT (3U)
18874#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd0GoodCtl(x) \
18875 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd0GoodCtl_SHIFT)) & \
18876 DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd0GoodCtl_MASK)
18877#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd1GoodCtl_MASK (0x10U)
18878#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd1GoodCtl_SHIFT (4U)
18879#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd1GoodCtl(x) \
18880 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd1GoodCtl_SHIFT)) & \
18881 DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_CtlUpd1GoodCtl_MASK)
18882#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdFailCtl_MASK (0x20U)
18883#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdFailCtl_SHIFT (5U)
18884#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdFailCtl(x) \
18885 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdFailCtl_SHIFT)) & \
18886 DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_MasUpdFailCtl_MASK)
18887#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0FailCtl_MASK (0x40U)
18888#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0FailCtl_SHIFT (6U)
18889#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0FailCtl(x) \
18890 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0FailCtl_SHIFT)) & \
18891 DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd0FailCtl_MASK)
18892#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1FailCtl_MASK (0x80U)
18893#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1FailCtl_SHIFT (7U)
18894#define DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1FailCtl(x) \
18895 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1FailCtl_SHIFT)) & \
18896 DWC_DDRPHYA_MASTER_PHYPERFCTRENABLE_PhyUpd1FailCtl_MASK)
18897/*! @} */
18898
18899/*! @name PLLPWRDN - PLL Power Down */
18900/*! @{ */
18901#define DWC_DDRPHYA_MASTER_PLLPWRDN_PllPwrDn_MASK (0x1U)
18902#define DWC_DDRPHYA_MASTER_PLLPWRDN_PllPwrDn_SHIFT (0U)
18903#define DWC_DDRPHYA_MASTER_PLLPWRDN_PllPwrDn(x) \
18904 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLPWRDN_PllPwrDn_SHIFT)) & \
18905 DWC_DDRPHYA_MASTER_PLLPWRDN_PllPwrDn_MASK)
18906/*! @} */
18907
18908/*! @name PLLRESET - PLL Reset */
18909/*! @{ */
18910#define DWC_DDRPHYA_MASTER_PLLRESET_PllReset_MASK (0x1U)
18911#define DWC_DDRPHYA_MASTER_PLLRESET_PllReset_SHIFT (0U)
18912#define DWC_DDRPHYA_MASTER_PLLRESET_PllReset(x) \
18913 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLRESET_PllReset_SHIFT)) & \
18914 DWC_DDRPHYA_MASTER_PLLRESET_PllReset_MASK)
18915/*! @} */
18916
18917/*! @name PLLCTRL2_P0 - PState dependent PLL Control Register 2 */
18918/*! @{ */
18919#define DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PllFreqSel_MASK (0x1FU)
18920#define DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PllFreqSel_SHIFT (0U)
18921#define DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PllFreqSel(x) \
18922 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PllFreqSel_SHIFT)) & \
18923 DWC_DDRPHYA_MASTER_PLLCTRL2_P0_PllFreqSel_MASK)
18924/*! @} */
18925
18926/*! @name PLLCTRL0 - PLL Control Register 0 */
18927/*! @{ */
18928#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllStandby_MASK (0x1U)
18929#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllStandby_SHIFT (0U)
18930#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllStandby(x) \
18931 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllStandby_SHIFT)) & \
18932 DWC_DDRPHYA_MASTER_PLLCTRL0_PllStandby_MASK)
18933#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypSel_MASK (0x2U)
18934#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypSel_SHIFT (1U)
18935#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypSel(x) \
18936 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypSel_SHIFT)) & \
18937 DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypSel_MASK)
18938#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllX2Mode_MASK (0x4U)
18939#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllX2Mode_SHIFT (2U)
18940#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllX2Mode(x) \
18941 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllX2Mode_SHIFT)) & \
18942 DWC_DDRPHYA_MASTER_PLLCTRL0_PllX2Mode_MASK)
18943#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllOutBypEn_MASK (0x8U)
18944#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllOutBypEn_SHIFT (3U)
18945#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllOutBypEn(x) \
18946 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllOutBypEn_SHIFT)) & \
18947 DWC_DDRPHYA_MASTER_PLLCTRL0_PllOutBypEn_MASK)
18948#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllPreset_MASK (0x10U)
18949#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllPreset_SHIFT (4U)
18950#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllPreset(x) \
18951 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllPreset_SHIFT)) & \
18952 DWC_DDRPHYA_MASTER_PLLCTRL0_PllPreset_MASK)
18953#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypassMode_MASK (0x20U)
18954#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypassMode_SHIFT (5U)
18955#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypassMode(x) \
18956 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypassMode_SHIFT)) & \
18957 DWC_DDRPHYA_MASTER_PLLCTRL0_PllBypassMode_MASK)
18958#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSelDfiFreqRatio_MASK (0x40U)
18959#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSelDfiFreqRatio_SHIFT (6U)
18960#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSelDfiFreqRatio(x) \
18961 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllSelDfiFreqRatio_SHIFT)) & \
18962 DWC_DDRPHYA_MASTER_PLLCTRL0_PllSelDfiFreqRatio_MASK)
18963#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusFlush_MASK (0x80U)
18964#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusFlush_SHIFT (7U)
18965#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusFlush(x) \
18966 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusFlush_SHIFT)) & \
18967 DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusFlush_MASK)
18968#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusByp_MASK (0x100U)
18969#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusByp_SHIFT (8U)
18970#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusByp(x) \
18971 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusByp_SHIFT)) & \
18972 DWC_DDRPHYA_MASTER_PLLCTRL0_PllSyncBusByp_MASK)
18973#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllReserved10x9_MASK (0x600U)
18974#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllReserved10x9_SHIFT (9U)
18975#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllReserved10x9(x) \
18976 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllReserved10x9_SHIFT)) & \
18977 DWC_DDRPHYA_MASTER_PLLCTRL0_PllReserved10x9_MASK)
18978#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllGearShift_MASK (0x800U)
18979#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllGearShift_SHIFT (11U)
18980#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllGearShift(x) \
18981 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllGearShift_SHIFT)) & \
18982 DWC_DDRPHYA_MASTER_PLLCTRL0_PllGearShift_MASK)
18983#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockCntSel_MASK (0x1000U)
18984#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockCntSel_SHIFT (12U)
18985#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockCntSel(x) \
18986 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockCntSel_SHIFT)) & \
18987 DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockCntSel_MASK)
18988#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockPhSel_MASK (0x6000U)
18989#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockPhSel_SHIFT (13U)
18990#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockPhSel(x) \
18991 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockPhSel_SHIFT)) & \
18992 DWC_DDRPHYA_MASTER_PLLCTRL0_PllLockPhSel_MASK)
18993#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSpareCtrl0_MASK (0x8000U)
18994#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSpareCtrl0_SHIFT (15U)
18995#define DWC_DDRPHYA_MASTER_PLLCTRL0_PllSpareCtrl0(x) \
18996 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL0_PllSpareCtrl0_SHIFT)) & \
18997 DWC_DDRPHYA_MASTER_PLLCTRL0_PllSpareCtrl0_MASK)
18998/*! @} */
18999
19000/*! @name PLLCTRL1_P0 - PState dependent PLL Control Register 1 */
19001/*! @{ */
19002#define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpIntCtrl_MASK (0x1FU)
19003#define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpIntCtrl_SHIFT (0U)
19004#define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpIntCtrl(x) \
19005 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpIntCtrl_SHIFT)) & \
19006 DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpIntCtrl_MASK)
19007#define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpPropCtrl_MASK (0x1E0U)
19008#define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpPropCtrl_SHIFT (5U)
19009#define DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpPropCtrl(x) \
19010 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpPropCtrl_SHIFT)) & \
19011 DWC_DDRPHYA_MASTER_PLLCTRL1_P0_PllCpPropCtrl_MASK)
19012/*! @} */
19013
19014/*! @name PLLTST - PLL Testing Control Register */
19015/*! @{ */
19016#define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstEn_MASK (0x1U)
19017#define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstEn_SHIFT (0U)
19018#define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstEn(x) \
19019 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstEn_SHIFT)) & \
19020 DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstEn_MASK)
19021#define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstSel_MASK (0x1EU)
19022#define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstSel_SHIFT (1U)
19023#define DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstSel(x) \
19024 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstSel_SHIFT)) & \
19025 DWC_DDRPHYA_MASTER_PLLTST_PllAnaTstSel_MASK)
19026#define DWC_DDRPHYA_MASTER_PLLTST_PllDigTstSel_MASK (0x1E0U)
19027#define DWC_DDRPHYA_MASTER_PLLTST_PllDigTstSel_SHIFT (5U)
19028#define DWC_DDRPHYA_MASTER_PLLTST_PllDigTstSel(x) \
19029 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTST_PllDigTstSel_SHIFT)) & \
19030 DWC_DDRPHYA_MASTER_PLLTST_PllDigTstSel_MASK)
19031/*! @} */
19032
19033/*! @name PLLLOCKSTATUS - PLL's pll_lock pin output */
19034/*! @{ */
19035#define DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PllLockStatus_MASK (0x1U)
19036#define DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PllLockStatus_SHIFT (0U)
19037#define DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PllLockStatus(x) \
19038 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PllLockStatus_SHIFT)) & \
19039 DWC_DDRPHYA_MASTER_PLLLOCKSTATUS_PllLockStatus_MASK)
19040/*! @} */
19041
19042/*! @name PLLTESTMODE_P0 - Additional controls for PLL CP/VCO modes of operation */
19043/*! @{ */
19044#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PllTestMode_p0_MASK (0xFFFFU)
19045#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PllTestMode_p0_SHIFT (0U)
19046#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PllTestMode_p0(x) \
19047 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PllTestMode_p0_SHIFT)) & \
19048 DWC_DDRPHYA_MASTER_PLLTESTMODE_P0_PllTestMode_p0_MASK)
19049/*! @} */
19050
19051/*! @name PLLCTRL3 - PLL Control Register 3 */
19052/*! @{ */
19053#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllSpare_MASK (0xFU)
19054#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllSpare_SHIFT (0U)
19055#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllSpare(x) \
19056 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PllSpare_SHIFT)) & \
19057 DWC_DDRPHYA_MASTER_PLLCTRL3_PllSpare_MASK)
19058#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllMaxRange_MASK (0x1F0U)
19059#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllMaxRange_SHIFT (4U)
19060#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllMaxRange(x) \
19061 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PllMaxRange_SHIFT)) & \
19062 DWC_DDRPHYA_MASTER_PLLCTRL3_PllMaxRange_MASK)
19063#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllDacValIn_MASK (0x3E00U)
19064#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllDacValIn_SHIFT (9U)
19065#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllDacValIn(x) \
19066 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PllDacValIn_SHIFT)) & \
19067 DWC_DDRPHYA_MASTER_PLLCTRL3_PllDacValIn_MASK)
19068#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllForceCal_MASK (0x4000U)
19069#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllForceCal_SHIFT (14U)
19070#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllForceCal(x) \
19071 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PllForceCal_SHIFT)) & \
19072 DWC_DDRPHYA_MASTER_PLLCTRL3_PllForceCal_MASK)
19073#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllEnCal_MASK (0x8000U)
19074#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllEnCal_SHIFT (15U)
19075#define DWC_DDRPHYA_MASTER_PLLCTRL3_PllEnCal(x) \
19076 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL3_PllEnCal_SHIFT)) & \
19077 DWC_DDRPHYA_MASTER_PLLCTRL3_PllEnCal_MASK)
19078/*! @} */
19079
19080/*! @name PLLCTRL4_P0 - PState dependent PLL Control Register 4 */
19081/*! @{ */
19082#define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpIntGsCtrl_MASK (0x1FU)
19083#define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpIntGsCtrl_SHIFT (0U)
19084#define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpIntGsCtrl(x) \
19085 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpIntGsCtrl_SHIFT)) & \
19086 DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpIntGsCtrl_MASK)
19087#define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpPropGsCtrl_MASK (0x1E0U)
19088#define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpPropGsCtrl_SHIFT (5U)
19089#define DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpPropGsCtrl(x) \
19090 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpPropGsCtrl_SHIFT)) & \
19091 DWC_DDRPHYA_MASTER_PLLCTRL4_P0_PllCpPropGsCtrl_MASK)
19092/*! @} */
19093
19094/*! @name PLLENDOFCAL - PLL's eoc (end of calibration) output */
19095/*! @{ */
19096#define DWC_DDRPHYA_MASTER_PLLENDOFCAL_PllEndofCal_MASK (0x1U)
19097#define DWC_DDRPHYA_MASTER_PLLENDOFCAL_PllEndofCal_SHIFT (0U)
19098#define DWC_DDRPHYA_MASTER_PLLENDOFCAL_PllEndofCal(x) \
19099 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLENDOFCAL_PllEndofCal_SHIFT)) & \
19100 DWC_DDRPHYA_MASTER_PLLENDOFCAL_PllEndofCal_MASK)
19101/*! @} */
19102
19103/*! @name PLLSTANDBYEFF - PLL's standby_eff (effective standby) output */
19104/*! @{ */
19105#define DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PllStandbyEff_MASK (0x1U)
19106#define DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PllStandbyEff_SHIFT (0U)
19107#define DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PllStandbyEff(x) \
19108 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PllStandbyEff_SHIFT)) & \
19109 DWC_DDRPHYA_MASTER_PLLSTANDBYEFF_PllStandbyEff_MASK)
19110/*! @} */
19111
19112/*! @name PLLDACVALOUT - PLL's Dacval_out output */
19113/*! @{ */
19114#define DWC_DDRPHYA_MASTER_PLLDACVALOUT_PllDacValOut_MASK (0x1FU)
19115#define DWC_DDRPHYA_MASTER_PLLDACVALOUT_PllDacValOut_SHIFT (0U)
19116#define DWC_DDRPHYA_MASTER_PLLDACVALOUT_PllDacValOut(x) \
19117 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLDACVALOUT_PllDacValOut_SHIFT)) & \
19118 DWC_DDRPHYA_MASTER_PLLDACVALOUT_PllDacValOut_MASK)
19119/*! @} */
19120
19121/*! @name LCDLDBGCNTL - Controls for use in observing and testing the LCDLs. */
19122/*! @{ */
19123#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvrVal_MASK (0x1FFU)
19124#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvrVal_SHIFT (0U)
19125#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvrVal(x) \
19126 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvrVal_SHIFT)) & \
19127 DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvrVal_MASK)
19128#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvr_MASK (0x200U)
19129#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvr_SHIFT (9U)
19130#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvr(x) \
19131 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvr_SHIFT)) & \
19132 DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineOvr_MASK)
19133#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineSnap_MASK (0x400U)
19134#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineSnap_SHIFT (10U)
19135#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineSnap(x) \
19136 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineSnap_SHIFT)) & \
19137 DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlFineSnap_MASK)
19138#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlTstEnable_MASK (0x800U)
19139#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlTstEnable_SHIFT (11U)
19140#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlTstEnable(x) \
19141 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlTstEnable_SHIFT)) & \
19142 DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlTstEnable_MASK)
19143#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlStatusSel_MASK (0xF000U)
19144#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlStatusSel_SHIFT (12U)
19145#define DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlStatusSel(x) \
19146 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlStatusSel_SHIFT)) & \
19147 DWC_DDRPHYA_MASTER_LCDLDBGCNTL_LcdlStatusSel_MASK)
19148/*! @} */
19149
19150/*! @name ACLCDLSTATUS - Debug status of the DBYTE LCDL */
19151/*! @{ */
19152#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlFineSnapVal_MASK (0x3FFU)
19153#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlFineSnapVal_SHIFT (0U)
19154#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlFineSnapVal(x) \
19155 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlFineSnapVal_SHIFT)) & \
19156 DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlFineSnapVal_MASK)
19157#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlPhdSnapVal_MASK (0x400U)
19158#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlPhdSnapVal_SHIFT (10U)
19159#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlPhdSnapVal(x) \
19160 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlPhdSnapVal_SHIFT)) & \
19161 DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlPhdSnapVal_MASK)
19162#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyLock_MASK (0x800U)
19163#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyLock_SHIFT (11U)
19164#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyLock(x) \
19165 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyLock_SHIFT)) & \
19166 DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyLock_MASK)
19167#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyUnlock_MASK (0x1000U)
19168#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyUnlock_SHIFT (12U)
19169#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyUnlock(x) \
19170 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyUnlock_SHIFT)) & \
19171 DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlStickyUnlock_MASK)
19172#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlLiveLock_MASK (0x2000U)
19173#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlLiveLock_SHIFT (13U)
19174#define DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlLiveLock(x) \
19175 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlLiveLock_SHIFT)) & \
19176 DWC_DDRPHYA_MASTER_ACLCDLSTATUS_AcLcdlLiveLock_MASK)
19177/*! @} */
19178
19179/*! @name CUSTPHYREV - Customer settable by the customer */
19180/*! @{ */
19181#define DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV_MASK (0x3FU)
19182#define DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV_SHIFT (0U)
19183#define DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV(x) \
19184 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV_SHIFT)) & \
19185 DWC_DDRPHYA_MASTER_CUSTPHYREV_CUSTPHYREV_MASK)
19186/*! @} */
19187
19188/*! @name PHYREV - The hardware version of this PHY, excluding the PUB */
19189/*! @{ */
19190#define DWC_DDRPHYA_MASTER_PHYREV_PHYMNR_MASK (0xFU)
19191#define DWC_DDRPHYA_MASTER_PHYREV_PHYMNR_SHIFT (0U)
19192#define DWC_DDRPHYA_MASTER_PHYREV_PHYMNR(x) \
19193 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYREV_PHYMNR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYREV_PHYMNR_MASK)
19194#define DWC_DDRPHYA_MASTER_PHYREV_PHYMDR_MASK (0xF0U)
19195#define DWC_DDRPHYA_MASTER_PHYREV_PHYMDR_SHIFT (4U)
19196#define DWC_DDRPHYA_MASTER_PHYREV_PHYMDR(x) \
19197 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYREV_PHYMDR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYREV_PHYMDR_MASK)
19198#define DWC_DDRPHYA_MASTER_PHYREV_PHYMJR_MASK (0xFF00U)
19199#define DWC_DDRPHYA_MASTER_PHYREV_PHYMJR_SHIFT (8U)
19200#define DWC_DDRPHYA_MASTER_PHYREV_PHYMJR(x) \
19201 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYREV_PHYMJR_SHIFT)) & DWC_DDRPHYA_MASTER_PHYREV_PHYMJR_MASK)
19202/*! @} */
19203
19204/*! @name LP3EXITSEQ0BSTARTVECTOR - Start vector value to be used for LP3-exit or Init PIE Sequence */
19205/*! @{ */
19206#define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllEnabled_MASK (0xFU)
19207#define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllEnabled_SHIFT (0U)
19208#define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllEnabled(x) \
19209 (((uint16_t)( \
19210 ((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllEnabled_SHIFT)) & \
19211 DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllEnabled_MASK)
19212#define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllBypassed_MASK (0xF0U)
19213#define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllBypassed_SHIFT (4U)
19214#define DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllBypassed(x) \
19215 (((uint16_t)( \
19216 ((uint16_t)(x)) << DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllBypassed_SHIFT)) & \
19217 DWC_DDRPHYA_MASTER_LP3EXITSEQ0BSTARTVECTOR_LP3ExitSeq0BStartVecPllBypassed_MASK)
19218/*! @} */
19219
19220/*! @name DFIFREQXLAT0 - DFI Frequency Translation Register 0 */
19221/*! @{ */
19222#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal0_MASK (0xFU)
19223#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal0_SHIFT (0U)
19224#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal0(x) \
19225 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal0_SHIFT)) & \
19226 DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal0_MASK)
19227#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal1_MASK (0xF0U)
19228#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal1_SHIFT (4U)
19229#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal1(x) \
19230 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal1_SHIFT)) & \
19231 DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal1_MASK)
19232#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal2_MASK (0xF00U)
19233#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal2_SHIFT (8U)
19234#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal2(x) \
19235 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal2_SHIFT)) & \
19236 DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal2_MASK)
19237#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal3_MASK (0xF000U)
19238#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal3_SHIFT (12U)
19239#define DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal3(x) \
19240 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal3_SHIFT)) & \
19241 DWC_DDRPHYA_MASTER_DFIFREQXLAT0_DfiFreqXlatVal3_MASK)
19242/*! @} */
19243
19244/*! @name DFIFREQXLAT1 - DFI Frequency Translation Register 1 */
19245/*! @{ */
19246#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal4_MASK (0xFU)
19247#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal4_SHIFT (0U)
19248#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal4(x) \
19249 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal4_SHIFT)) & \
19250 DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal4_MASK)
19251#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal5_MASK (0xF0U)
19252#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal5_SHIFT (4U)
19253#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal5(x) \
19254 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal5_SHIFT)) & \
19255 DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal5_MASK)
19256#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal6_MASK (0xF00U)
19257#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal6_SHIFT (8U)
19258#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal6(x) \
19259 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal6_SHIFT)) & \
19260 DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal6_MASK)
19261#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal7_MASK (0xF000U)
19262#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal7_SHIFT (12U)
19263#define DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal7(x) \
19264 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal7_SHIFT)) & \
19265 DWC_DDRPHYA_MASTER_DFIFREQXLAT1_DfiFreqXlatVal7_MASK)
19266/*! @} */
19267
19268/*! @name DFIFREQXLAT2 - DFI Frequency Translation Register 2 */
19269/*! @{ */
19270#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal8_MASK (0xFU)
19271#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal8_SHIFT (0U)
19272#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal8(x) \
19273 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal8_SHIFT)) & \
19274 DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal8_MASK)
19275#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal9_MASK (0xF0U)
19276#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal9_SHIFT (4U)
19277#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal9(x) \
19278 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal9_SHIFT)) & \
19279 DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal9_MASK)
19280#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal10_MASK (0xF00U)
19281#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal10_SHIFT (8U)
19282#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal10(x) \
19283 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal10_SHIFT)) & \
19284 DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal10_MASK)
19285#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal11_MASK (0xF000U)
19286#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal11_SHIFT (12U)
19287#define DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal11(x) \
19288 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal11_SHIFT)) & \
19289 DWC_DDRPHYA_MASTER_DFIFREQXLAT2_DfiFreqXlatVal11_MASK)
19290/*! @} */
19291
19292/*! @name DFIFREQXLAT3 - DFI Frequency Translation Register 3 */
19293/*! @{ */
19294#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal12_MASK (0xFU)
19295#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal12_SHIFT (0U)
19296#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal12(x) \
19297 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal12_SHIFT)) & \
19298 DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal12_MASK)
19299#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal13_MASK (0xF0U)
19300#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal13_SHIFT (4U)
19301#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal13(x) \
19302 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal13_SHIFT)) & \
19303 DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal13_MASK)
19304#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal14_MASK (0xF00U)
19305#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal14_SHIFT (8U)
19306#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal14(x) \
19307 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal14_SHIFT)) & \
19308 DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal14_MASK)
19309#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal15_MASK (0xF000U)
19310#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal15_SHIFT (12U)
19311#define DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal15(x) \
19312 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal15_SHIFT)) & \
19313 DWC_DDRPHYA_MASTER_DFIFREQXLAT3_DfiFreqXlatVal15_MASK)
19314/*! @} */
19315
19316/*! @name DFIFREQXLAT4 - DFI Frequency Translation Register 4 */
19317/*! @{ */
19318#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal16_MASK (0xFU)
19319#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal16_SHIFT (0U)
19320#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal16(x) \
19321 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal16_SHIFT)) & \
19322 DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal16_MASK)
19323#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal17_MASK (0xF0U)
19324#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal17_SHIFT (4U)
19325#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal17(x) \
19326 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal17_SHIFT)) & \
19327 DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal17_MASK)
19328#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal18_MASK (0xF00U)
19329#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal18_SHIFT (8U)
19330#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal18(x) \
19331 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal18_SHIFT)) & \
19332 DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal18_MASK)
19333#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal19_MASK (0xF000U)
19334#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal19_SHIFT (12U)
19335#define DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal19(x) \
19336 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal19_SHIFT)) & \
19337 DWC_DDRPHYA_MASTER_DFIFREQXLAT4_DfiFreqXlatVal19_MASK)
19338/*! @} */
19339
19340/*! @name DFIFREQXLAT5 - DFI Frequency Translation Register 5 */
19341/*! @{ */
19342#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal20_MASK (0xFU)
19343#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal20_SHIFT (0U)
19344#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal20(x) \
19345 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal20_SHIFT)) & \
19346 DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal20_MASK)
19347#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal21_MASK (0xF0U)
19348#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal21_SHIFT (4U)
19349#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal21(x) \
19350 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal21_SHIFT)) & \
19351 DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal21_MASK)
19352#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal22_MASK (0xF00U)
19353#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal22_SHIFT (8U)
19354#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal22(x) \
19355 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal22_SHIFT)) & \
19356 DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal22_MASK)
19357#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal23_MASK (0xF000U)
19358#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal23_SHIFT (12U)
19359#define DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal23(x) \
19360 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal23_SHIFT)) & \
19361 DWC_DDRPHYA_MASTER_DFIFREQXLAT5_DfiFreqXlatVal23_MASK)
19362/*! @} */
19363
19364/*! @name DFIFREQXLAT6 - DFI Frequency Translation Register 6 */
19365/*! @{ */
19366#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal24_MASK (0xFU)
19367#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal24_SHIFT (0U)
19368#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal24(x) \
19369 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal24_SHIFT)) & \
19370 DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal24_MASK)
19371#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal25_MASK (0xF0U)
19372#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal25_SHIFT (4U)
19373#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal25(x) \
19374 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal25_SHIFT)) & \
19375 DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal25_MASK)
19376#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal26_MASK (0xF00U)
19377#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal26_SHIFT (8U)
19378#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal26(x) \
19379 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal26_SHIFT)) & \
19380 DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal26_MASK)
19381#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal27_MASK (0xF000U)
19382#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal27_SHIFT (12U)
19383#define DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal27(x) \
19384 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal27_SHIFT)) & \
19385 DWC_DDRPHYA_MASTER_DFIFREQXLAT6_DfiFreqXlatVal27_MASK)
19386/*! @} */
19387
19388/*! @name DFIFREQXLAT7 - DFI Frequency Translation Register 7 */
19389/*! @{ */
19390#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal28_MASK (0xFU)
19391#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal28_SHIFT (0U)
19392#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal28(x) \
19393 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal28_SHIFT)) & \
19394 DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal28_MASK)
19395#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal29_MASK (0xF0U)
19396#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal29_SHIFT (4U)
19397#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal29(x) \
19398 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal29_SHIFT)) & \
19399 DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal29_MASK)
19400#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal30_MASK (0xF00U)
19401#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal30_SHIFT (8U)
19402#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal30(x) \
19403 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal30_SHIFT)) & \
19404 DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal30_MASK)
19405#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal31_MASK (0xF000U)
19406#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal31_SHIFT (12U)
19407#define DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal31(x) \
19408 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal31_SHIFT)) & \
19409 DWC_DDRPHYA_MASTER_DFIFREQXLAT7_DfiFreqXlatVal31_MASK)
19410/*! @} */
19411
19412/*! @name TXRDPTRINIT - TxRdPtrInit control register */
19413/*! @{ */
19414#define DWC_DDRPHYA_MASTER_TXRDPTRINIT_TxRdPtrInit_MASK (0x1U)
19415#define DWC_DDRPHYA_MASTER_TXRDPTRINIT_TxRdPtrInit_SHIFT (0U)
19416#define DWC_DDRPHYA_MASTER_TXRDPTRINIT_TxRdPtrInit(x) \
19417 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TXRDPTRINIT_TxRdPtrInit_SHIFT)) & \
19418 DWC_DDRPHYA_MASTER_TXRDPTRINIT_TxRdPtrInit_MASK)
19419/*! @} */
19420
19421/*! @name DFIINITCOMPLETE - DFI Init Complete control */
19422/*! @{ */
19423#define DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DfiInitComplete_MASK (0x1U)
19424#define DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DfiInitComplete_SHIFT (0U)
19425#define DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DfiInitComplete(x) \
19426 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DfiInitComplete_SHIFT)) & \
19427 DWC_DDRPHYA_MASTER_DFIINITCOMPLETE_DfiInitComplete_MASK)
19428/*! @} */
19429
19430/*! @name DFIFREQRATIO_P0 - DFI Frequency Ratio */
19431/*! @{ */
19432#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DfiFreqRatio_p0_MASK (0x3U)
19433#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DfiFreqRatio_p0_SHIFT (0U)
19434#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DfiFreqRatio_p0(x) \
19435 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DfiFreqRatio_p0_SHIFT)) & \
19436 DWC_DDRPHYA_MASTER_DFIFREQRATIO_P0_DfiFreqRatio_p0_MASK)
19437/*! @} */
19438
19439/*! @name RXFIFOCHECKS - Enable more frequent consistency checks of the RX FIFOs */
19440/*! @{ */
19441#define DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DoFrequentRxFifoChecks_MASK (0x1U)
19442#define DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DoFrequentRxFifoChecks_SHIFT (0U)
19443#define DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DoFrequentRxFifoChecks(x) \
19444 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DoFrequentRxFifoChecks_SHIFT)) & \
19445 DWC_DDRPHYA_MASTER_RXFIFOCHECKS_DoFrequentRxFifoChecks_MASK)
19446/*! @} */
19447
19448/*! @name MTESTDTOCTRL - */
19449/*! @{ */
19450#define DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTestDtoCtrl_MASK (0x1U)
19451#define DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTestDtoCtrl_SHIFT (0U)
19452#define DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTestDtoCtrl(x) \
19453 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTestDtoCtrl_SHIFT)) & \
19454 DWC_DDRPHYA_MASTER_MTESTDTOCTRL_MTestDtoCtrl_MASK)
19455/*! @} */
19456
19457/*! @name MAPCAA0TODFI - Maps PHY CAA lane 0 from dfi0_address of the index of the register contents */
19458/*! @{ */
19459#define DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MapCAA0toDfi_MASK (0xFU)
19460#define DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MapCAA0toDfi_SHIFT (0U)
19461#define DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MapCAA0toDfi(x) \
19462 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MapCAA0toDfi_SHIFT)) & \
19463 DWC_DDRPHYA_MASTER_MAPCAA0TODFI_MapCAA0toDfi_MASK)
19464/*! @} */
19465
19466/*! @name MAPCAA1TODFI - Maps PHY CAA lane 1 from dfi0_address of the index of the register contents */
19467/*! @{ */
19468#define DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MapCAA1toDfi_MASK (0xFU)
19469#define DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MapCAA1toDfi_SHIFT (0U)
19470#define DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MapCAA1toDfi(x) \
19471 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MapCAA1toDfi_SHIFT)) & \
19472 DWC_DDRPHYA_MASTER_MAPCAA1TODFI_MapCAA1toDfi_MASK)
19473/*! @} */
19474
19475/*! @name MAPCAA2TODFI - Maps PHY CAA lane 2 from dfi0_address of the index of the register contents */
19476/*! @{ */
19477#define DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MapCAA2toDfi_MASK (0xFU)
19478#define DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MapCAA2toDfi_SHIFT (0U)
19479#define DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MapCAA2toDfi(x) \
19480 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MapCAA2toDfi_SHIFT)) & \
19481 DWC_DDRPHYA_MASTER_MAPCAA2TODFI_MapCAA2toDfi_MASK)
19482/*! @} */
19483
19484/*! @name MAPCAA3TODFI - Maps PHY CAA lane 3 from dfi0_address of the index of the register contents */
19485/*! @{ */
19486#define DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MapCAA3toDfi_MASK (0xFU)
19487#define DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MapCAA3toDfi_SHIFT (0U)
19488#define DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MapCAA3toDfi(x) \
19489 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MapCAA3toDfi_SHIFT)) & \
19490 DWC_DDRPHYA_MASTER_MAPCAA3TODFI_MapCAA3toDfi_MASK)
19491/*! @} */
19492
19493/*! @name MAPCAA4TODFI - Maps PHY CAA lane 4 from dfi0_address of the index of the register contents */
19494/*! @{ */
19495#define DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MapCAA4toDfi_MASK (0xFU)
19496#define DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MapCAA4toDfi_SHIFT (0U)
19497#define DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MapCAA4toDfi(x) \
19498 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MapCAA4toDfi_SHIFT)) & \
19499 DWC_DDRPHYA_MASTER_MAPCAA4TODFI_MapCAA4toDfi_MASK)
19500/*! @} */
19501
19502/*! @name MAPCAA5TODFI - Maps PHY CAA lane 5 from dfi0_address of the index of the register contents */
19503/*! @{ */
19504#define DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MapCAA5toDfi_MASK (0xFU)
19505#define DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MapCAA5toDfi_SHIFT (0U)
19506#define DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MapCAA5toDfi(x) \
19507 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MapCAA5toDfi_SHIFT)) & \
19508 DWC_DDRPHYA_MASTER_MAPCAA5TODFI_MapCAA5toDfi_MASK)
19509/*! @} */
19510
19511/*! @name MAPCAA6TODFI - Maps PHY CAA lane 6 from dfi0_address of the index of the register contents */
19512/*! @{ */
19513#define DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MapCAA6toDfi_MASK (0xFU)
19514#define DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MapCAA6toDfi_SHIFT (0U)
19515#define DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MapCAA6toDfi(x) \
19516 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MapCAA6toDfi_SHIFT)) & \
19517 DWC_DDRPHYA_MASTER_MAPCAA6TODFI_MapCAA6toDfi_MASK)
19518/*! @} */
19519
19520/*! @name MAPCAA7TODFI - Maps PHY CAA lane 7 from dfi0_address of the index of the register contents */
19521/*! @{ */
19522#define DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MapCAA7toDfi_MASK (0xFU)
19523#define DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MapCAA7toDfi_SHIFT (0U)
19524#define DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MapCAA7toDfi(x) \
19525 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MapCAA7toDfi_SHIFT)) & \
19526 DWC_DDRPHYA_MASTER_MAPCAA7TODFI_MapCAA7toDfi_MASK)
19527/*! @} */
19528
19529/*! @name MAPCAA8TODFI - Maps PHY CAA lane 8 from dfi0_address of the index of the register contents */
19530/*! @{ */
19531#define DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MapCAA8toDfi_MASK (0xFU)
19532#define DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MapCAA8toDfi_SHIFT (0U)
19533#define DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MapCAA8toDfi(x) \
19534 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MapCAA8toDfi_SHIFT)) & \
19535 DWC_DDRPHYA_MASTER_MAPCAA8TODFI_MapCAA8toDfi_MASK)
19536/*! @} */
19537
19538/*! @name MAPCAA9TODFI - Maps PHY CAA lane 9 from dfi0_address of the index of the register contents */
19539/*! @{ */
19540#define DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MapCAA9toDfi_MASK (0xFU)
19541#define DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MapCAA9toDfi_SHIFT (0U)
19542#define DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MapCAA9toDfi(x) \
19543 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MapCAA9toDfi_SHIFT)) & \
19544 DWC_DDRPHYA_MASTER_MAPCAA9TODFI_MapCAA9toDfi_MASK)
19545/*! @} */
19546
19547/*! @name MAPCAB0TODFI - Maps PHY CAB lane 0 from dfi1_address of the index of the register contents */
19548/*! @{ */
19549#define DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MapCAB0toDfi_MASK (0xFU)
19550#define DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MapCAB0toDfi_SHIFT (0U)
19551#define DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MapCAB0toDfi(x) \
19552 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MapCAB0toDfi_SHIFT)) & \
19553 DWC_DDRPHYA_MASTER_MAPCAB0TODFI_MapCAB0toDfi_MASK)
19554/*! @} */
19555
19556/*! @name MAPCAB1TODFI - Maps PHY CAB lane 1 from dfi1_address of the index of the register contents */
19557/*! @{ */
19558#define DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MapCAB1toDfi_MASK (0xFU)
19559#define DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MapCAB1toDfi_SHIFT (0U)
19560#define DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MapCAB1toDfi(x) \
19561 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MapCAB1toDfi_SHIFT)) & \
19562 DWC_DDRPHYA_MASTER_MAPCAB1TODFI_MapCAB1toDfi_MASK)
19563/*! @} */
19564
19565/*! @name MAPCAB2TODFI - Maps PHY CAB lane 2 from dfi1_address of the index of the register contents */
19566/*! @{ */
19567#define DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MapCAB2toDfi_MASK (0xFU)
19568#define DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MapCAB2toDfi_SHIFT (0U)
19569#define DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MapCAB2toDfi(x) \
19570 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MapCAB2toDfi_SHIFT)) & \
19571 DWC_DDRPHYA_MASTER_MAPCAB2TODFI_MapCAB2toDfi_MASK)
19572/*! @} */
19573
19574/*! @name MAPCAB3TODFI - Maps PHY CAB lane 3 from dfi1_address of the index of the register contents */
19575/*! @{ */
19576#define DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MapCAB3toDfi_MASK (0xFU)
19577#define DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MapCAB3toDfi_SHIFT (0U)
19578#define DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MapCAB3toDfi(x) \
19579 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MapCAB3toDfi_SHIFT)) & \
19580 DWC_DDRPHYA_MASTER_MAPCAB3TODFI_MapCAB3toDfi_MASK)
19581/*! @} */
19582
19583/*! @name MAPCAB4TODFI - Maps PHY CAB lane 4 from dfi1_address of the index of the register contents */
19584/*! @{ */
19585#define DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MapCAB4toDfi_MASK (0xFU)
19586#define DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MapCAB4toDfi_SHIFT (0U)
19587#define DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MapCAB4toDfi(x) \
19588 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MapCAB4toDfi_SHIFT)) & \
19589 DWC_DDRPHYA_MASTER_MAPCAB4TODFI_MapCAB4toDfi_MASK)
19590/*! @} */
19591
19592/*! @name MAPCAB5TODFI - Maps PHY CAB lane 5 from dfi1_address of the index of the register contents */
19593/*! @{ */
19594#define DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MapCAB5toDfi_MASK (0xFU)
19595#define DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MapCAB5toDfi_SHIFT (0U)
19596#define DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MapCAB5toDfi(x) \
19597 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MapCAB5toDfi_SHIFT)) & \
19598 DWC_DDRPHYA_MASTER_MAPCAB5TODFI_MapCAB5toDfi_MASK)
19599/*! @} */
19600
19601/*! @name MAPCAB6TODFI - Maps PHY CAB lane 6 from dfi1_address of the index of the register contents */
19602/*! @{ */
19603#define DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MapCAB6toDfi_MASK (0xFU)
19604#define DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MapCAB6toDfi_SHIFT (0U)
19605#define DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MapCAB6toDfi(x) \
19606 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MapCAB6toDfi_SHIFT)) & \
19607 DWC_DDRPHYA_MASTER_MAPCAB6TODFI_MapCAB6toDfi_MASK)
19608/*! @} */
19609
19610/*! @name MAPCAB7TODFI - Maps PHY CAB lane 7 from dfi1_address of the index of the register contents */
19611/*! @{ */
19612#define DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MapCAB7toDfi_MASK (0xFU)
19613#define DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MapCAB7toDfi_SHIFT (0U)
19614#define DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MapCAB7toDfi(x) \
19615 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MapCAB7toDfi_SHIFT)) & \
19616 DWC_DDRPHYA_MASTER_MAPCAB7TODFI_MapCAB7toDfi_MASK)
19617/*! @} */
19618
19619/*! @name MAPCAB8TODFI - Maps PHY CAB lane 8 from dfi1_address of the index of the register contents */
19620/*! @{ */
19621#define DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MapCAB8toDfi_MASK (0xFU)
19622#define DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MapCAB8toDfi_SHIFT (0U)
19623#define DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MapCAB8toDfi(x) \
19624 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MapCAB8toDfi_SHIFT)) & \
19625 DWC_DDRPHYA_MASTER_MAPCAB8TODFI_MapCAB8toDfi_MASK)
19626/*! @} */
19627
19628/*! @name MAPCAB9TODFI - Maps PHY CAB lane 9 from dfi1_address of the index of the register contents */
19629/*! @{ */
19630#define DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MapCAB9toDfi_MASK (0xFU)
19631#define DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MapCAB9toDfi_SHIFT (0U)
19632#define DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MapCAB9toDfi(x) \
19633 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MapCAB9toDfi_SHIFT)) & \
19634 DWC_DDRPHYA_MASTER_MAPCAB9TODFI_MapCAB9toDfi_MASK)
19635/*! @} */
19636
19637/*! @name PHYINTERRUPTENABLE - Interrupt Enable Bits */
19638/*! @{ */
19639#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngCmpltEn_MASK (0x1U)
19640#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngCmpltEn_SHIFT (0U)
19641#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngCmpltEn(x) \
19642 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngCmpltEn_SHIFT)) & \
19643 DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngCmpltEn_MASK)
19644#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyInitCmpltEn_MASK (0x2U)
19645#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyInitCmpltEn_SHIFT (1U)
19646#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyInitCmpltEn(x) \
19647 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyInitCmpltEn_SHIFT)) & \
19648 DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyInitCmpltEn_MASK)
19649#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngFailEn_MASK (0x4U)
19650#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngFailEn_SHIFT (2U)
19651#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngFailEn(x) \
19652 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngFailEn_SHIFT)) & \
19653 DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyTrngFailEn_MASK)
19654#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyFWReservedEn_MASK (0xF8U)
19655#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyFWReservedEn_SHIFT (3U)
19656#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyFWReservedEn(x) \
19657 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyFWReservedEn_SHIFT)) & \
19658 DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyFWReservedEn_MASK)
19659#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyVTDriftAlarmEn_MASK (0x300U)
19660#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyVTDriftAlarmEn_SHIFT (8U)
19661#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyVTDriftAlarmEn(x) \
19662 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyVTDriftAlarmEn_SHIFT)) & \
19663 DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyVTDriftAlarmEn_MASK)
19664#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyRxFifoCheckEn_MASK (0x400U)
19665#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyRxFifoCheckEn_SHIFT (10U)
19666#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyRxFifoCheckEn(x) \
19667 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyRxFifoCheckEn_SHIFT)) & \
19668 DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyRxFifoCheckEn_MASK)
19669#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyHWReservedEn_MASK (0xF800U)
19670#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyHWReservedEn_SHIFT (11U)
19671#define DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyHWReservedEn(x) \
19672 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyHWReservedEn_SHIFT)) & \
19673 DWC_DDRPHYA_MASTER_PHYINTERRUPTENABLE_PhyHWReservedEn_MASK)
19674/*! @} */
19675
19676/*! @name PHYINTERRUPTFWCONTROL - Interrupt Firmware Control Bits */
19677/*! @{ */
19678#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngCmpltFW_MASK (0x1U)
19679#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngCmpltFW_SHIFT (0U)
19680#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngCmpltFW(x) \
19681 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngCmpltFW_SHIFT)) & \
19682 DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngCmpltFW_MASK)
19683#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyInitCmpltFW_MASK (0x2U)
19684#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyInitCmpltFW_SHIFT (1U)
19685#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyInitCmpltFW(x) \
19686 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyInitCmpltFW_SHIFT)) & \
19687 DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyInitCmpltFW_MASK)
19688#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngFailFW_MASK (0x4U)
19689#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngFailFW_SHIFT (2U)
19690#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngFailFW(x) \
19691 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngFailFW_SHIFT)) & \
19692 DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyTrngFailFW_MASK)
19693#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyFWReservedFW_MASK (0xF8U)
19694#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyFWReservedFW_SHIFT (3U)
19695#define DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyFWReservedFW(x) \
19696 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyFWReservedFW_SHIFT)) & \
19697 DWC_DDRPHYA_MASTER_PHYINTERRUPTFWCONTROL_PhyFWReservedFW_MASK)
19698/*! @} */
19699
19700/*! @name PHYINTERRUPTMASK - Interrupt Mask Bits */
19701/*! @{ */
19702#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngCmpltMsk_MASK (0x1U)
19703#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngCmpltMsk_SHIFT (0U)
19704#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngCmpltMsk(x) \
19705 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngCmpltMsk_SHIFT)) & \
19706 DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngCmpltMsk_MASK)
19707#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyInitCmpltMsk_MASK (0x2U)
19708#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyInitCmpltMsk_SHIFT (1U)
19709#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyInitCmpltMsk(x) \
19710 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyInitCmpltMsk_SHIFT)) & \
19711 DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyInitCmpltMsk_MASK)
19712#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngFailMsk_MASK (0x4U)
19713#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngFailMsk_SHIFT (2U)
19714#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngFailMsk(x) \
19715 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngFailMsk_SHIFT)) & \
19716 DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyTrngFailMsk_MASK)
19717#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyFWReservedMsk_MASK (0xF8U)
19718#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyFWReservedMsk_SHIFT (3U)
19719#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyFWReservedMsk(x) \
19720 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyFWReservedMsk_SHIFT)) & \
19721 DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyFWReservedMsk_MASK)
19722#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyVTDriftAlarmMsk_MASK (0x300U)
19723#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyVTDriftAlarmMsk_SHIFT (8U)
19724#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyVTDriftAlarmMsk(x) \
19725 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyVTDriftAlarmMsk_SHIFT)) & \
19726 DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyVTDriftAlarmMsk_MASK)
19727#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyRxFifoCheckMsk_MASK (0x400U)
19728#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyRxFifoCheckMsk_SHIFT (10U)
19729#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyRxFifoCheckMsk(x) \
19730 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyRxFifoCheckMsk_SHIFT)) & \
19731 DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyRxFifoCheckMsk_MASK)
19732#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyHWReservedMsk_MASK (0xF800U)
19733#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyHWReservedMsk_SHIFT (11U)
19734#define DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyHWReservedMsk(x) \
19735 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyHWReservedMsk_SHIFT)) & \
19736 DWC_DDRPHYA_MASTER_PHYINTERRUPTMASK_PhyHWReservedMsk_MASK)
19737/*! @} */
19738
19739/*! @name PHYINTERRUPTCLEAR - Interrupt Clear Bits */
19740/*! @{ */
19741#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngCmpltClr_MASK (0x1U)
19742#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngCmpltClr_SHIFT (0U)
19743#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngCmpltClr(x) \
19744 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngCmpltClr_SHIFT)) & \
19745 DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngCmpltClr_MASK)
19746#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyInitCmpltClr_MASK (0x2U)
19747#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyInitCmpltClr_SHIFT (1U)
19748#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyInitCmpltClr(x) \
19749 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyInitCmpltClr_SHIFT)) & \
19750 DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyInitCmpltClr_MASK)
19751#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngFailClr_MASK (0x4U)
19752#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngFailClr_SHIFT (2U)
19753#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngFailClr(x) \
19754 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngFailClr_SHIFT)) & \
19755 DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyTrngFailClr_MASK)
19756#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyFWReservedClr_MASK (0xF8U)
19757#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyFWReservedClr_SHIFT (3U)
19758#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyFWReservedClr(x) \
19759 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyFWReservedClr_SHIFT)) & \
19760 DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyFWReservedClr_MASK)
19761#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyVTDriftAlarmClr_MASK (0x300U)
19762#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyVTDriftAlarmClr_SHIFT (8U)
19763#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyVTDriftAlarmClr(x) \
19764 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyVTDriftAlarmClr_SHIFT)) & \
19765 DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyVTDriftAlarmClr_MASK)
19766#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyRxFifoCheckClr_MASK (0x400U)
19767#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyRxFifoCheckClr_SHIFT (10U)
19768#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyRxFifoCheckClr(x) \
19769 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyRxFifoCheckClr_SHIFT)) & \
19770 DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyRxFifoCheckClr_MASK)
19771#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyHWReservedClr_MASK (0xF800U)
19772#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyHWReservedClr_SHIFT (11U)
19773#define DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyHWReservedClr(x) \
19774 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyHWReservedClr_SHIFT)) & \
19775 DWC_DDRPHYA_MASTER_PHYINTERRUPTCLEAR_PhyHWReservedClr_MASK)
19776/*! @} */
19777
19778/*! @name PHYINTERRUPTSTATUS - Interrupt Status Bits */
19779/*! @{ */
19780#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngCmplt_MASK (0x1U)
19781#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngCmplt_SHIFT (0U)
19782#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngCmplt(x) \
19783 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngCmplt_SHIFT)) & \
19784 DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngCmplt_MASK)
19785#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyInitCmplt_MASK (0x2U)
19786#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyInitCmplt_SHIFT (1U)
19787#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyInitCmplt(x) \
19788 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyInitCmplt_SHIFT)) & \
19789 DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyInitCmplt_MASK)
19790#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngFail_MASK (0x4U)
19791#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngFail_SHIFT (2U)
19792#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngFail(x) \
19793 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngFail_SHIFT)) & \
19794 DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyTrngFail_MASK)
19795#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyFWReserved_MASK (0xF8U)
19796#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyFWReserved_SHIFT (3U)
19797#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyFWReserved(x) \
19798 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyFWReserved_SHIFT)) & \
19799 DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyFWReserved_MASK)
19800#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDriftAlarm_MASK (0x300U)
19801#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDriftAlarm_SHIFT (8U)
19802#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDriftAlarm(x) \
19803 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDriftAlarm_SHIFT)) & \
19804 DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_VTDriftAlarm_MASK)
19805#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyRxFifoCheck_MASK (0x400U)
19806#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyRxFifoCheck_SHIFT (10U)
19807#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyRxFifoCheck(x) \
19808 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyRxFifoCheck_SHIFT)) & \
19809 DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyRxFifoCheck_MASK)
19810#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyHWReserved_MASK (0xF800U)
19811#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyHWReserved_SHIFT (11U)
19812#define DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyHWReserved(x) \
19813 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyHWReserved_SHIFT)) & \
19814 DWC_DDRPHYA_MASTER_PHYINTERRUPTSTATUS_PhyHWReserved_MASK)
19815/*! @} */
19816
19817/*! @name HWTSWIZZLEHWTADDRESS0 - Signal swizzle selection for HWT swizzle */
19818/*! @{ */
19819#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HwtSwizzleHwtAddress0_MASK (0x1FU)
19820#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HwtSwizzleHwtAddress0_SHIFT (0U)
19821#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HwtSwizzleHwtAddress0(x) \
19822 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HwtSwizzleHwtAddress0_SHIFT)) & \
19823 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS0_HwtSwizzleHwtAddress0_MASK)
19824/*! @} */
19825
19826/*! @name HWTSWIZZLEHWTADDRESS1 - Signal swizzle selection for HWT swizzle */
19827/*! @{ */
19828#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HwtSwizzleHwtAddress1_MASK (0x1FU)
19829#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HwtSwizzleHwtAddress1_SHIFT (0U)
19830#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HwtSwizzleHwtAddress1(x) \
19831 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HwtSwizzleHwtAddress1_SHIFT)) & \
19832 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS1_HwtSwizzleHwtAddress1_MASK)
19833/*! @} */
19834
19835/*! @name HWTSWIZZLEHWTADDRESS2 - Signal swizzle selection for HWT swizzle */
19836/*! @{ */
19837#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HwtSwizzleHwtAddress2_MASK (0x1FU)
19838#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HwtSwizzleHwtAddress2_SHIFT (0U)
19839#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HwtSwizzleHwtAddress2(x) \
19840 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HwtSwizzleHwtAddress2_SHIFT)) & \
19841 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS2_HwtSwizzleHwtAddress2_MASK)
19842/*! @} */
19843
19844/*! @name HWTSWIZZLEHWTADDRESS3 - Signal swizzle selection for HWT swizzle */
19845/*! @{ */
19846#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HwtSwizzleHwtAddress3_MASK (0x1FU)
19847#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HwtSwizzleHwtAddress3_SHIFT (0U)
19848#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HwtSwizzleHwtAddress3(x) \
19849 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HwtSwizzleHwtAddress3_SHIFT)) & \
19850 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS3_HwtSwizzleHwtAddress3_MASK)
19851/*! @} */
19852
19853/*! @name HWTSWIZZLEHWTADDRESS4 - Signal swizzle selection for HWT swizzle */
19854/*! @{ */
19855#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HwtSwizzleHwtAddress4_MASK (0x1FU)
19856#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HwtSwizzleHwtAddress4_SHIFT (0U)
19857#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HwtSwizzleHwtAddress4(x) \
19858 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HwtSwizzleHwtAddress4_SHIFT)) & \
19859 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS4_HwtSwizzleHwtAddress4_MASK)
19860/*! @} */
19861
19862/*! @name HWTSWIZZLEHWTADDRESS5 - Signal swizzle selection for HWT swizzle */
19863/*! @{ */
19864#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HwtSwizzleHwtAddress5_MASK (0x1FU)
19865#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HwtSwizzleHwtAddress5_SHIFT (0U)
19866#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HwtSwizzleHwtAddress5(x) \
19867 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HwtSwizzleHwtAddress5_SHIFT)) & \
19868 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS5_HwtSwizzleHwtAddress5_MASK)
19869/*! @} */
19870
19871/*! @name HWTSWIZZLEHWTADDRESS6 - Signal swizzle selection for HWT swizzle */
19872/*! @{ */
19873#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HwtSwizzleHwtAddress6_MASK (0x1FU)
19874#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HwtSwizzleHwtAddress6_SHIFT (0U)
19875#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HwtSwizzleHwtAddress6(x) \
19876 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HwtSwizzleHwtAddress6_SHIFT)) & \
19877 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS6_HwtSwizzleHwtAddress6_MASK)
19878/*! @} */
19879
19880/*! @name HWTSWIZZLEHWTADDRESS7 - Signal swizzle selection for HWT swizzle */
19881/*! @{ */
19882#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HwtSwizzleHwtAddress7_MASK (0x1FU)
19883#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HwtSwizzleHwtAddress7_SHIFT (0U)
19884#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HwtSwizzleHwtAddress7(x) \
19885 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HwtSwizzleHwtAddress7_SHIFT)) & \
19886 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS7_HwtSwizzleHwtAddress7_MASK)
19887/*! @} */
19888
19889/*! @name HWTSWIZZLEHWTADDRESS8 - Signal swizzle selection for HWT swizzle */
19890/*! @{ */
19891#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HwtSwizzleHwtAddress8_MASK (0x1FU)
19892#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HwtSwizzleHwtAddress8_SHIFT (0U)
19893#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HwtSwizzleHwtAddress8(x) \
19894 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HwtSwizzleHwtAddress8_SHIFT)) & \
19895 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS8_HwtSwizzleHwtAddress8_MASK)
19896/*! @} */
19897
19898/*! @name HWTSWIZZLEHWTADDRESS9 - Signal swizzle selection for HWT swizzle */
19899/*! @{ */
19900#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HwtSwizzleHwtAddress9_MASK (0x1FU)
19901#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HwtSwizzleHwtAddress9_SHIFT (0U)
19902#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HwtSwizzleHwtAddress9(x) \
19903 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HwtSwizzleHwtAddress9_SHIFT)) & \
19904 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS9_HwtSwizzleHwtAddress9_MASK)
19905/*! @} */
19906
19907/*! @name HWTSWIZZLEHWTADDRESS10 - Signal swizzle selection for HWT swizzle */
19908/*! @{ */
19909#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HwtSwizzleHwtAddress10_MASK (0x1FU)
19910#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HwtSwizzleHwtAddress10_SHIFT (0U)
19911#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HwtSwizzleHwtAddress10(x) \
19912 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HwtSwizzleHwtAddress10_SHIFT)) & \
19913 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS10_HwtSwizzleHwtAddress10_MASK)
19914/*! @} */
19915
19916/*! @name HWTSWIZZLEHWTADDRESS11 - Signal swizzle selection for HWT swizzle */
19917/*! @{ */
19918#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HwtSwizzleHwtAddress11_MASK (0x1FU)
19919#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HwtSwizzleHwtAddress11_SHIFT (0U)
19920#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HwtSwizzleHwtAddress11(x) \
19921 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HwtSwizzleHwtAddress11_SHIFT)) & \
19922 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS11_HwtSwizzleHwtAddress11_MASK)
19923/*! @} */
19924
19925/*! @name HWTSWIZZLEHWTADDRESS12 - Signal swizzle selection for HWT swizzle */
19926/*! @{ */
19927#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HwtSwizzleHwtAddress12_MASK (0x1FU)
19928#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HwtSwizzleHwtAddress12_SHIFT (0U)
19929#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HwtSwizzleHwtAddress12(x) \
19930 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HwtSwizzleHwtAddress12_SHIFT)) & \
19931 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS12_HwtSwizzleHwtAddress12_MASK)
19932/*! @} */
19933
19934/*! @name HWTSWIZZLEHWTADDRESS13 - Signal swizzle selection for HWT swizzle */
19935/*! @{ */
19936#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HwtSwizzleHwtAddress13_MASK (0x1FU)
19937#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HwtSwizzleHwtAddress13_SHIFT (0U)
19938#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HwtSwizzleHwtAddress13(x) \
19939 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HwtSwizzleHwtAddress13_SHIFT)) & \
19940 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS13_HwtSwizzleHwtAddress13_MASK)
19941/*! @} */
19942
19943/*! @name HWTSWIZZLEHWTADDRESS14 - Signal swizzle selection for HWT swizzle */
19944/*! @{ */
19945#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HwtSwizzleHwtAddress14_MASK (0x1FU)
19946#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HwtSwizzleHwtAddress14_SHIFT (0U)
19947#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HwtSwizzleHwtAddress14(x) \
19948 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HwtSwizzleHwtAddress14_SHIFT)) & \
19949 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS14_HwtSwizzleHwtAddress14_MASK)
19950/*! @} */
19951
19952/*! @name HWTSWIZZLEHWTADDRESS15 - Signal swizzle selection for HWT swizzle */
19953/*! @{ */
19954#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HwtSwizzleHwtAddress15_MASK (0x1FU)
19955#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HwtSwizzleHwtAddress15_SHIFT (0U)
19956#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HwtSwizzleHwtAddress15(x) \
19957 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HwtSwizzleHwtAddress15_SHIFT)) & \
19958 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS15_HwtSwizzleHwtAddress15_MASK)
19959/*! @} */
19960
19961/*! @name HWTSWIZZLEHWTADDRESS17 - Signal swizzle selection for HWT swizzle */
19962/*! @{ */
19963#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HwtSwizzleHwtAddress17_MASK (0x1FU)
19964#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HwtSwizzleHwtAddress17_SHIFT (0U)
19965#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HwtSwizzleHwtAddress17(x) \
19966 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HwtSwizzleHwtAddress17_SHIFT)) & \
19967 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTADDRESS17_HwtSwizzleHwtAddress17_MASK)
19968/*! @} */
19969
19970/*! @name HWTSWIZZLEHWTACTN - Signal swizzle selection for HWT swizzle */
19971/*! @{ */
19972#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HwtSwizzleHwtActN_MASK (0x1FU)
19973#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HwtSwizzleHwtActN_SHIFT (0U)
19974#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HwtSwizzleHwtActN(x) \
19975 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HwtSwizzleHwtActN_SHIFT)) & \
19976 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTACTN_HwtSwizzleHwtActN_MASK)
19977/*! @} */
19978
19979/*! @name HWTSWIZZLEHWTBANK0 - Signal swizzle selection for HWT swizzle */
19980/*! @{ */
19981#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HwtSwizzleHwtBank0_MASK (0x1FU)
19982#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HwtSwizzleHwtBank0_SHIFT (0U)
19983#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HwtSwizzleHwtBank0(x) \
19984 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HwtSwizzleHwtBank0_SHIFT)) & \
19985 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK0_HwtSwizzleHwtBank0_MASK)
19986/*! @} */
19987
19988/*! @name HWTSWIZZLEHWTBANK1 - Signal swizzle selection for HWT swizzle */
19989/*! @{ */
19990#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HwtSwizzleHwtBank1_MASK (0x1FU)
19991#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HwtSwizzleHwtBank1_SHIFT (0U)
19992#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HwtSwizzleHwtBank1(x) \
19993 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HwtSwizzleHwtBank1_SHIFT)) & \
19994 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK1_HwtSwizzleHwtBank1_MASK)
19995/*! @} */
19996
19997/*! @name HWTSWIZZLEHWTBANK2 - Signal swizzle selection for HWT swizzle */
19998/*! @{ */
19999#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HwtSwizzleHwtBank2_MASK (0x1FU)
20000#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HwtSwizzleHwtBank2_SHIFT (0U)
20001#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HwtSwizzleHwtBank2(x) \
20002 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HwtSwizzleHwtBank2_SHIFT)) & \
20003 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBANK2_HwtSwizzleHwtBank2_MASK)
20004/*! @} */
20005
20006/*! @name HWTSWIZZLEHWTBG0 - Signal swizzle selection for HWT swizzle */
20007/*! @{ */
20008#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HwtSwizzleHwtBg0_MASK (0x1FU)
20009#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HwtSwizzleHwtBg0_SHIFT (0U)
20010#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HwtSwizzleHwtBg0(x) \
20011 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HwtSwizzleHwtBg0_SHIFT)) & \
20012 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG0_HwtSwizzleHwtBg0_MASK)
20013/*! @} */
20014
20015/*! @name HWTSWIZZLEHWTBG1 - Signal swizzle selection for HWT swizzle */
20016/*! @{ */
20017#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HwtSwizzleHwtBg1_MASK (0x1FU)
20018#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HwtSwizzleHwtBg1_SHIFT (0U)
20019#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HwtSwizzleHwtBg1(x) \
20020 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HwtSwizzleHwtBg1_SHIFT)) & \
20021 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTBG1_HwtSwizzleHwtBg1_MASK)
20022/*! @} */
20023
20024/*! @name HWTSWIZZLEHWTCASN - Signal swizzle selection for HWT swizzle */
20025/*! @{ */
20026#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HwtSwizzleHwtCasN_MASK (0x1FU)
20027#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HwtSwizzleHwtCasN_SHIFT (0U)
20028#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HwtSwizzleHwtCasN(x) \
20029 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HwtSwizzleHwtCasN_SHIFT)) & \
20030 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTCASN_HwtSwizzleHwtCasN_MASK)
20031/*! @} */
20032
20033/*! @name HWTSWIZZLEHWTRASN - Signal swizzle selection for HWT swizzle */
20034/*! @{ */
20035#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HwtSwizzleHwtRasN_MASK (0x1FU)
20036#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HwtSwizzleHwtRasN_SHIFT (0U)
20037#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HwtSwizzleHwtRasN(x) \
20038 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HwtSwizzleHwtRasN_SHIFT)) & \
20039 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTRASN_HwtSwizzleHwtRasN_MASK)
20040/*! @} */
20041
20042/*! @name HWTSWIZZLEHWTWEN - Signal swizzle selection for HWT swizzle */
20043/*! @{ */
20044#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HwtSwizzleHwtWeN_MASK (0x1FU)
20045#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HwtSwizzleHwtWeN_SHIFT (0U)
20046#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HwtSwizzleHwtWeN(x) \
20047 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HwtSwizzleHwtWeN_SHIFT)) & \
20048 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTWEN_HwtSwizzleHwtWeN_MASK)
20049/*! @} */
20050
20051/*! @name HWTSWIZZLEHWTPARITYIN - Signal swizzle selection for HWT swizzle */
20052/*! @{ */
20053#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HwtSwizzleHwtParityIn_MASK (0x1FU)
20054#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HwtSwizzleHwtParityIn_SHIFT (0U)
20055#define DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HwtSwizzleHwtParityIn(x) \
20056 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HwtSwizzleHwtParityIn_SHIFT)) & \
20057 DWC_DDRPHYA_MASTER_HWTSWIZZLEHWTPARITYIN_HwtSwizzleHwtParityIn_MASK)
20058/*! @} */
20059
20060/*! @name DFIHANDSHAKEDELAYS0 - Add assertion/deassertion delays on handshake signals Logic assumes that dfi signal
20061 * assertions exceed the programmed delays */
20062/*! @{ */
20063#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdAckDelay0_MASK (0xFU)
20064#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdAckDelay0_SHIFT (0U)
20065#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdAckDelay0(x) \
20066 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdAckDelay0_SHIFT)) & \
20067 DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdAckDelay0_MASK)
20068#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdReqDelay0_MASK (0xF0U)
20069#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdReqDelay0_SHIFT (4U)
20070#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdReqDelay0(x) \
20071 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdReqDelay0_SHIFT)) & \
20072 DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_PhyUpdReqDelay0_MASK)
20073#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdAckDelay0_MASK (0xF00U)
20074#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdAckDelay0_SHIFT (8U)
20075#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdAckDelay0(x) \
20076 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdAckDelay0_SHIFT)) & \
20077 DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdAckDelay0_MASK)
20078#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdReqDelay0_MASK (0xF000U)
20079#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdReqDelay0_SHIFT (12U)
20080#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdReqDelay0(x) \
20081 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdReqDelay0_SHIFT)) & \
20082 DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS0_CtrlUpdReqDelay0_MASK)
20083/*! @} */
20084
20085/*! @name DFIHANDSHAKEDELAYS1 - Add assertion/deassertion delays on handshake signals Logic assumes that dfi signal
20086 * assertions exceed the programmed delays */
20087/*! @{ */
20088#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdAckDelay1_MASK (0xFU)
20089#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdAckDelay1_SHIFT (0U)
20090#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdAckDelay1(x) \
20091 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdAckDelay1_SHIFT)) & \
20092 DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdAckDelay1_MASK)
20093#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdReqDelay1_MASK (0xF0U)
20094#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdReqDelay1_SHIFT (4U)
20095#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdReqDelay1(x) \
20096 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdReqDelay1_SHIFT)) & \
20097 DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_PhyUpdReqDelay1_MASK)
20098#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdAckDelay1_MASK (0xF00U)
20099#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdAckDelay1_SHIFT (8U)
20100#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdAckDelay1(x) \
20101 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdAckDelay1_SHIFT)) & \
20102 DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdAckDelay1_MASK)
20103#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdReqDelay1_MASK (0xF000U)
20104#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdReqDelay1_SHIFT (12U)
20105#define DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdReqDelay1(x) \
20106 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdReqDelay1_SHIFT)) & \
20107 DWC_DDRPHYA_MASTER_DFIHANDSHAKEDELAYS1_CtrlUpdReqDelay1_MASK)
20108/*! @} */
20109
20110/*! @name CALUCLKINFO_P1 - Impedance Calibration Clock Ratio */
20111/*! @{ */
20112#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CalUClkTicksPer1uS_MASK (0x3FFU)
20113#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CalUClkTicksPer1uS_SHIFT (0U)
20114#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CalUClkTicksPer1uS(x) \
20115 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CalUClkTicksPer1uS_SHIFT)) & \
20116 DWC_DDRPHYA_MASTER_CALUCLKINFO_P1_CalUClkTicksPer1uS_MASK)
20117/*! @} */
20118
20119/*! @name SEQ0BDLY0_P1 - PHY Initialization Engine (PIE) Delay Register 0 */
20120/*! @{ */
20121#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_Seq0BDLY0_p1_MASK (0xFFFFU)
20122#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_Seq0BDLY0_p1_SHIFT (0U)
20123#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_Seq0BDLY0_p1(x) \
20124 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_Seq0BDLY0_p1_SHIFT)) & \
20125 DWC_DDRPHYA_MASTER_SEQ0BDLY0_P1_Seq0BDLY0_p1_MASK)
20126/*! @} */
20127
20128/*! @name SEQ0BDLY1_P1 - PHY Initialization Engine (PIE) Delay Register 1 */
20129/*! @{ */
20130#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_Seq0BDLY1_p1_MASK (0xFFFFU)
20131#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_Seq0BDLY1_p1_SHIFT (0U)
20132#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_Seq0BDLY1_p1(x) \
20133 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_Seq0BDLY1_p1_SHIFT)) & \
20134 DWC_DDRPHYA_MASTER_SEQ0BDLY1_P1_Seq0BDLY1_p1_MASK)
20135/*! @} */
20136
20137/*! @name SEQ0BDLY2_P1 - PHY Initialization Engine (PIE) Delay Register 2 */
20138/*! @{ */
20139#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_Seq0BDLY2_p1_MASK (0xFFFFU)
20140#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_Seq0BDLY2_p1_SHIFT (0U)
20141#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_Seq0BDLY2_p1(x) \
20142 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_Seq0BDLY2_p1_SHIFT)) & \
20143 DWC_DDRPHYA_MASTER_SEQ0BDLY2_P1_Seq0BDLY2_p1_MASK)
20144/*! @} */
20145
20146/*! @name SEQ0BDLY3_P1 - PHY Initialization Engine (PIE) Delay Register 3 */
20147/*! @{ */
20148#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_Seq0BDLY3_p1_MASK (0xFFFFU)
20149#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_Seq0BDLY3_p1_SHIFT (0U)
20150#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_Seq0BDLY3_p1(x) \
20151 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_Seq0BDLY3_p1_SHIFT)) & \
20152 DWC_DDRPHYA_MASTER_SEQ0BDLY3_P1_Seq0BDLY3_p1_MASK)
20153/*! @} */
20154
20155/*! @name PPTTRAINSETUP_P1 - Setup Intervals for DFI PHY Master operations */
20156/*! @{ */
20157#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrTrainInterval_MASK (0xFU)
20158#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrTrainInterval_SHIFT (0U)
20159#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrTrainInterval(x) \
20160 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrTrainInterval_SHIFT)) & \
20161 DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrTrainInterval_MASK)
20162#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrMaxReqToAck_MASK (0x70U)
20163#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrMaxReqToAck_SHIFT (4U)
20164#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrMaxReqToAck(x) \
20165 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrMaxReqToAck_SHIFT)) & \
20166 DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P1_PhyMstrMaxReqToAck_MASK)
20167/*! @} */
20168
20169/*! @name TRISTATEMODECA_P1 - Mode select register for MEMCLK/Address/Command Tristates */
20170/*! @{ */
20171#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DisDynAdrTri_MASK (0x1U)
20172#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DisDynAdrTri_SHIFT (0U)
20173#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DisDynAdrTri(x) \
20174 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DisDynAdrTri_SHIFT)) & \
20175 DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DisDynAdrTri_MASK)
20176#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMode_MASK (0x2U)
20177#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMode_SHIFT (1U)
20178#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMode(x) \
20179 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMode_SHIFT)) & \
20180 DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_DDR2TMode_MASK)
20181#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CkDisVal_MASK (0xCU)
20182#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CkDisVal_SHIFT (2U)
20183#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CkDisVal(x) \
20184 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CkDisVal_SHIFT)) & \
20185 DWC_DDRPHYA_MASTER_TRISTATEMODECA_P1_CkDisVal_MASK)
20186/*! @} */
20187
20188/*! @name HWTMRL_P1 - HWT MaxReadLatency. */
20189/*! @{ */
20190#define DWC_DDRPHYA_MASTER_HWTMRL_P1_HwtMRL_p1_MASK (0x1FU)
20191#define DWC_DDRPHYA_MASTER_HWTMRL_P1_HwtMRL_p1_SHIFT (0U)
20192#define DWC_DDRPHYA_MASTER_HWTMRL_P1_HwtMRL_p1(x) \
20193 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTMRL_P1_HwtMRL_p1_SHIFT)) & \
20194 DWC_DDRPHYA_MASTER_HWTMRL_P1_HwtMRL_p1_MASK)
20195/*! @} */
20196
20197/*! @name DQSPREAMBLECONTROL_P1 - Control the PHY logic related to the read and write DQS preamble */
20198/*! @{ */
20199#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckRxDqsPre_MASK (0x1U)
20200#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckRxDqsPre_SHIFT (0U)
20201#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckRxDqsPre(x) \
20202 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckRxDqsPre_SHIFT)) & \
20203 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckRxDqsPre_MASK)
20204#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckTxDqsPre_MASK (0x2U)
20205#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckTxDqsPre_SHIFT (1U)
20206#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckTxDqsPre(x) \
20207 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckTxDqsPre_SHIFT)) & \
20208 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_TwoTckTxDqsPre_MASK)
20209#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_PositionDfeInit_MASK (0x1CU)
20210#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_PositionDfeInit_SHIFT (2U)
20211#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_PositionDfeInit(x) \
20212 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_PositionDfeInit_SHIFT)) & \
20213 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_PositionDfeInit_MASK)
20214#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TglTwoTckTxDqsPre_MASK (0x20U)
20215#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TglTwoTckTxDqsPre_SHIFT (5U)
20216#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TglTwoTckTxDqsPre(x) \
20217 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TglTwoTckTxDqsPre_SHIFT)) & \
20218 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4TglTwoTckTxDqsPre_MASK)
20219#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4PostambleExt_MASK (0x40U)
20220#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4PostambleExt_SHIFT (6U)
20221#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4PostambleExt(x) \
20222 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4PostambleExt_SHIFT)) & \
20223 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4PostambleExt_MASK)
20224#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4SttcPreBridgeRxEn_MASK (0x80U)
20225#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4SttcPreBridgeRxEn_SHIFT (7U)
20226#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4SttcPreBridgeRxEn(x) \
20227 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4SttcPreBridgeRxEn_SHIFT)) & \
20228 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_LP4SttcPreBridgeRxEn_MASK)
20229#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION_MASK (0x100U)
20230#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION_SHIFT (8U)
20231#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION(x) \
20232 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION_SHIFT)) & \
20233 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P1_WDQSEXTENSION_MASK)
20234/*! @} */
20235
20236/*! @name DMIPINPRESENT_P1 - This Register is used to enable the Read-DBI function in each DBYTE */
20237/*! @{ */
20238#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RdDbiEnabled_MASK (0x1U)
20239#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RdDbiEnabled_SHIFT (0U)
20240#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RdDbiEnabled(x) \
20241 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RdDbiEnabled_SHIFT)) & \
20242 DWC_DDRPHYA_MASTER_DMIPINPRESENT_P1_RdDbiEnabled_MASK)
20243/*! @} */
20244
20245/*! @name ARDPTRINITVAL_P1 - Address/Command FIFO ReadPointer Initial Value */
20246/*! @{ */
20247#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARdPtrInitVal_p1_MASK (0xFU)
20248#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARdPtrInitVal_p1_SHIFT (0U)
20249#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARdPtrInitVal_p1(x) \
20250 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARdPtrInitVal_p1_SHIFT)) & \
20251 DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P1_ARdPtrInitVal_p1_MASK)
20252/*! @} */
20253
20254/*! @name PROCODTTIMECTL_P1 - READ DATA On-Die Termination Timing Control (by PHY) */
20255/*! @{ */
20256#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtTailWidth_MASK (0x3U)
20257#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtTailWidth_SHIFT (0U)
20258#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtTailWidth(x) \
20259 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtTailWidth_SHIFT)) & \
20260 DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtTailWidth_MASK)
20261#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtStartDelay_MASK (0xCU)
20262#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtStartDelay_SHIFT (2U)
20263#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtStartDelay(x) \
20264 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtStartDelay_SHIFT)) & \
20265 DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P1_POdtStartDelay_MASK)
20266/*! @} */
20267
20268/*! @name DLLGAINCTL_P1 - DLL gain control */
20269/*! @{ */
20270#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainIV_MASK (0xFU)
20271#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainIV_SHIFT (0U)
20272#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainIV(x) \
20273 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainIV_SHIFT)) & \
20274 DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainIV_MASK)
20275#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainTV_MASK (0xF0U)
20276#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainTV_SHIFT (4U)
20277#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainTV(x) \
20278 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainTV_SHIFT)) & \
20279 DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllGainTV_MASK)
20280#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllSeedSel_MASK (0xF00U)
20281#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllSeedSel_SHIFT (8U)
20282#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllSeedSel(x) \
20283 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllSeedSel_SHIFT)) & \
20284 DWC_DDRPHYA_MASTER_DLLGAINCTL_P1_DllSeedSel_MASK)
20285/*! @} */
20286
20287/*! @name DFIRDDATACSDESTMAP_P1 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
20288/*! @{ */
20289#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm0_MASK (0x3U)
20290#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm0_SHIFT (0U)
20291#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm0(x) \
20292 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm0_SHIFT)) & \
20293 DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm0_MASK)
20294#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm1_MASK (0xCU)
20295#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm1_SHIFT (2U)
20296#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm1(x) \
20297 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm1_SHIFT)) & \
20298 DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm1_MASK)
20299#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm2_MASK (0x30U)
20300#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm2_SHIFT (4U)
20301#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm2(x) \
20302 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm2_SHIFT)) & \
20303 DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm2_MASK)
20304#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm3_MASK (0xC0U)
20305#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm3_SHIFT (6U)
20306#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm3(x) \
20307 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm3_SHIFT)) & \
20308 DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P1_DfiRdDestm3_MASK)
20309/*! @} */
20310
20311/*! @name VREFINGLOBAL_P1 - PHY Global Vref Controls */
20312/*! @{ */
20313#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInSel_MASK (0x7U)
20314#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInSel_SHIFT (0U)
20315#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInSel(x) \
20316 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInSel_SHIFT)) & \
20317 DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInSel_MASK)
20318#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInDAC_MASK (0x3F8U)
20319#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInDAC_SHIFT (3U)
20320#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInDAC(x) \
20321 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInDAC_SHIFT)) & \
20322 DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInDAC_MASK)
20323#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInTrim_MASK (0x3C00U)
20324#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInTrim_SHIFT (10U)
20325#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInTrim(x) \
20326 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInTrim_SHIFT)) & \
20327 DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInTrim_MASK)
20328#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInMode_MASK (0x4000U)
20329#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInMode_SHIFT (14U)
20330#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInMode(x) \
20331 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInMode_SHIFT)) & \
20332 DWC_DDRPHYA_MASTER_VREFINGLOBAL_P1_GlobalVrefInMode_MASK)
20333/*! @} */
20334
20335/*! @name DFIWRDATACSDESTMAP_P1 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
20336/*! @{ */
20337#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm0_MASK (0x3U)
20338#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm0_SHIFT (0U)
20339#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm0(x) \
20340 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm0_SHIFT)) & \
20341 DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm0_MASK)
20342#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm1_MASK (0xCU)
20343#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm1_SHIFT (2U)
20344#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm1(x) \
20345 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm1_SHIFT)) & \
20346 DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm1_MASK)
20347#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm2_MASK (0x30U)
20348#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm2_SHIFT (4U)
20349#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm2(x) \
20350 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm2_SHIFT)) & \
20351 DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm2_MASK)
20352#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm3_MASK (0xC0U)
20353#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm3_SHIFT (6U)
20354#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm3(x) \
20355 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm3_SHIFT)) & \
20356 DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P1_DfiWrDestm3_MASK)
20357/*! @} */
20358
20359/*! @name PLLCTRL2_P1 - PState dependent PLL Control Register 2 */
20360/*! @{ */
20361#define DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PllFreqSel_MASK (0x1FU)
20362#define DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PllFreqSel_SHIFT (0U)
20363#define DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PllFreqSel(x) \
20364 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PllFreqSel_SHIFT)) & \
20365 DWC_DDRPHYA_MASTER_PLLCTRL2_P1_PllFreqSel_MASK)
20366/*! @} */
20367
20368/*! @name PLLCTRL1_P1 - PState dependent PLL Control Register 1 */
20369/*! @{ */
20370#define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpIntCtrl_MASK (0x1FU)
20371#define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpIntCtrl_SHIFT (0U)
20372#define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpIntCtrl(x) \
20373 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpIntCtrl_SHIFT)) & \
20374 DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpIntCtrl_MASK)
20375#define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpPropCtrl_MASK (0x1E0U)
20376#define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpPropCtrl_SHIFT (5U)
20377#define DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpPropCtrl(x) \
20378 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpPropCtrl_SHIFT)) & \
20379 DWC_DDRPHYA_MASTER_PLLCTRL1_P1_PllCpPropCtrl_MASK)
20380/*! @} */
20381
20382/*! @name PLLTESTMODE_P1 - Additional controls for PLL CP/VCO modes of operation */
20383/*! @{ */
20384#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PllTestMode_p1_MASK (0xFFFFU)
20385#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PllTestMode_p1_SHIFT (0U)
20386#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PllTestMode_p1(x) \
20387 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PllTestMode_p1_SHIFT)) & \
20388 DWC_DDRPHYA_MASTER_PLLTESTMODE_P1_PllTestMode_p1_MASK)
20389/*! @} */
20390
20391/*! @name PLLCTRL4_P1 - PState dependent PLL Control Register 4 */
20392/*! @{ */
20393#define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpIntGsCtrl_MASK (0x1FU)
20394#define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpIntGsCtrl_SHIFT (0U)
20395#define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpIntGsCtrl(x) \
20396 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpIntGsCtrl_SHIFT)) & \
20397 DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpIntGsCtrl_MASK)
20398#define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpPropGsCtrl_MASK (0x1E0U)
20399#define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpPropGsCtrl_SHIFT (5U)
20400#define DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpPropGsCtrl(x) \
20401 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpPropGsCtrl_SHIFT)) & \
20402 DWC_DDRPHYA_MASTER_PLLCTRL4_P1_PllCpPropGsCtrl_MASK)
20403/*! @} */
20404
20405/*! @name DFIFREQRATIO_P1 - DFI Frequency Ratio */
20406/*! @{ */
20407#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DfiFreqRatio_p1_MASK (0x3U)
20408#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DfiFreqRatio_p1_SHIFT (0U)
20409#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DfiFreqRatio_p1(x) \
20410 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DfiFreqRatio_p1_SHIFT)) & \
20411 DWC_DDRPHYA_MASTER_DFIFREQRATIO_P1_DfiFreqRatio_p1_MASK)
20412/*! @} */
20413
20414/*! @name CALUCLKINFO_P2 - Impedance Calibration Clock Ratio */
20415/*! @{ */
20416#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CalUClkTicksPer1uS_MASK (0x3FFU)
20417#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CalUClkTicksPer1uS_SHIFT (0U)
20418#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CalUClkTicksPer1uS(x) \
20419 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CalUClkTicksPer1uS_SHIFT)) & \
20420 DWC_DDRPHYA_MASTER_CALUCLKINFO_P2_CalUClkTicksPer1uS_MASK)
20421/*! @} */
20422
20423/*! @name SEQ0BDLY0_P2 - PHY Initialization Engine (PIE) Delay Register 0 */
20424/*! @{ */
20425#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_Seq0BDLY0_p2_MASK (0xFFFFU)
20426#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_Seq0BDLY0_p2_SHIFT (0U)
20427#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_Seq0BDLY0_p2(x) \
20428 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_Seq0BDLY0_p2_SHIFT)) & \
20429 DWC_DDRPHYA_MASTER_SEQ0BDLY0_P2_Seq0BDLY0_p2_MASK)
20430/*! @} */
20431
20432/*! @name SEQ0BDLY1_P2 - PHY Initialization Engine (PIE) Delay Register 1 */
20433/*! @{ */
20434#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_Seq0BDLY1_p2_MASK (0xFFFFU)
20435#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_Seq0BDLY1_p2_SHIFT (0U)
20436#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_Seq0BDLY1_p2(x) \
20437 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_Seq0BDLY1_p2_SHIFT)) & \
20438 DWC_DDRPHYA_MASTER_SEQ0BDLY1_P2_Seq0BDLY1_p2_MASK)
20439/*! @} */
20440
20441/*! @name SEQ0BDLY2_P2 - PHY Initialization Engine (PIE) Delay Register 2 */
20442/*! @{ */
20443#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_Seq0BDLY2_p2_MASK (0xFFFFU)
20444#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_Seq0BDLY2_p2_SHIFT (0U)
20445#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_Seq0BDLY2_p2(x) \
20446 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_Seq0BDLY2_p2_SHIFT)) & \
20447 DWC_DDRPHYA_MASTER_SEQ0BDLY2_P2_Seq0BDLY2_p2_MASK)
20448/*! @} */
20449
20450/*! @name SEQ0BDLY3_P2 - PHY Initialization Engine (PIE) Delay Register 3 */
20451/*! @{ */
20452#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_Seq0BDLY3_p2_MASK (0xFFFFU)
20453#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_Seq0BDLY3_p2_SHIFT (0U)
20454#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_Seq0BDLY3_p2(x) \
20455 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_Seq0BDLY3_p2_SHIFT)) & \
20456 DWC_DDRPHYA_MASTER_SEQ0BDLY3_P2_Seq0BDLY3_p2_MASK)
20457/*! @} */
20458
20459/*! @name PPTTRAINSETUP_P2 - Setup Intervals for DFI PHY Master operations */
20460/*! @{ */
20461#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrTrainInterval_MASK (0xFU)
20462#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrTrainInterval_SHIFT (0U)
20463#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrTrainInterval(x) \
20464 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrTrainInterval_SHIFT)) & \
20465 DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrTrainInterval_MASK)
20466#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrMaxReqToAck_MASK (0x70U)
20467#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrMaxReqToAck_SHIFT (4U)
20468#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrMaxReqToAck(x) \
20469 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrMaxReqToAck_SHIFT)) & \
20470 DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P2_PhyMstrMaxReqToAck_MASK)
20471/*! @} */
20472
20473/*! @name TRISTATEMODECA_P2 - Mode select register for MEMCLK/Address/Command Tristates */
20474/*! @{ */
20475#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DisDynAdrTri_MASK (0x1U)
20476#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DisDynAdrTri_SHIFT (0U)
20477#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DisDynAdrTri(x) \
20478 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DisDynAdrTri_SHIFT)) & \
20479 DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DisDynAdrTri_MASK)
20480#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMode_MASK (0x2U)
20481#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMode_SHIFT (1U)
20482#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMode(x) \
20483 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMode_SHIFT)) & \
20484 DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_DDR2TMode_MASK)
20485#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CkDisVal_MASK (0xCU)
20486#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CkDisVal_SHIFT (2U)
20487#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CkDisVal(x) \
20488 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CkDisVal_SHIFT)) & \
20489 DWC_DDRPHYA_MASTER_TRISTATEMODECA_P2_CkDisVal_MASK)
20490/*! @} */
20491
20492/*! @name HWTMRL_P2 - HWT MaxReadLatency. */
20493/*! @{ */
20494#define DWC_DDRPHYA_MASTER_HWTMRL_P2_HwtMRL_p2_MASK (0x1FU)
20495#define DWC_DDRPHYA_MASTER_HWTMRL_P2_HwtMRL_p2_SHIFT (0U)
20496#define DWC_DDRPHYA_MASTER_HWTMRL_P2_HwtMRL_p2(x) \
20497 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTMRL_P2_HwtMRL_p2_SHIFT)) & \
20498 DWC_DDRPHYA_MASTER_HWTMRL_P2_HwtMRL_p2_MASK)
20499/*! @} */
20500
20501/*! @name DQSPREAMBLECONTROL_P2 - Control the PHY logic related to the read and write DQS preamble */
20502/*! @{ */
20503#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckRxDqsPre_MASK (0x1U)
20504#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckRxDqsPre_SHIFT (0U)
20505#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckRxDqsPre(x) \
20506 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckRxDqsPre_SHIFT)) & \
20507 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckRxDqsPre_MASK)
20508#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckTxDqsPre_MASK (0x2U)
20509#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckTxDqsPre_SHIFT (1U)
20510#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckTxDqsPre(x) \
20511 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckTxDqsPre_SHIFT)) & \
20512 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_TwoTckTxDqsPre_MASK)
20513#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_PositionDfeInit_MASK (0x1CU)
20514#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_PositionDfeInit_SHIFT (2U)
20515#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_PositionDfeInit(x) \
20516 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_PositionDfeInit_SHIFT)) & \
20517 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_PositionDfeInit_MASK)
20518#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TglTwoTckTxDqsPre_MASK (0x20U)
20519#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TglTwoTckTxDqsPre_SHIFT (5U)
20520#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TglTwoTckTxDqsPre(x) \
20521 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TglTwoTckTxDqsPre_SHIFT)) & \
20522 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4TglTwoTckTxDqsPre_MASK)
20523#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4PostambleExt_MASK (0x40U)
20524#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4PostambleExt_SHIFT (6U)
20525#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4PostambleExt(x) \
20526 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4PostambleExt_SHIFT)) & \
20527 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4PostambleExt_MASK)
20528#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4SttcPreBridgeRxEn_MASK (0x80U)
20529#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4SttcPreBridgeRxEn_SHIFT (7U)
20530#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4SttcPreBridgeRxEn(x) \
20531 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4SttcPreBridgeRxEn_SHIFT)) & \
20532 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_LP4SttcPreBridgeRxEn_MASK)
20533#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION_MASK (0x100U)
20534#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION_SHIFT (8U)
20535#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION(x) \
20536 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION_SHIFT)) & \
20537 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P2_WDQSEXTENSION_MASK)
20538/*! @} */
20539
20540/*! @name DMIPINPRESENT_P2 - This Register is used to enable the Read-DBI function in each DBYTE */
20541/*! @{ */
20542#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RdDbiEnabled_MASK (0x1U)
20543#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RdDbiEnabled_SHIFT (0U)
20544#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RdDbiEnabled(x) \
20545 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RdDbiEnabled_SHIFT)) & \
20546 DWC_DDRPHYA_MASTER_DMIPINPRESENT_P2_RdDbiEnabled_MASK)
20547/*! @} */
20548
20549/*! @name ARDPTRINITVAL_P2 - Address/Command FIFO ReadPointer Initial Value */
20550/*! @{ */
20551#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARdPtrInitVal_p2_MASK (0xFU)
20552#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARdPtrInitVal_p2_SHIFT (0U)
20553#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARdPtrInitVal_p2(x) \
20554 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARdPtrInitVal_p2_SHIFT)) & \
20555 DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P2_ARdPtrInitVal_p2_MASK)
20556/*! @} */
20557
20558/*! @name PROCODTTIMECTL_P2 - READ DATA On-Die Termination Timing Control (by PHY) */
20559/*! @{ */
20560#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtTailWidth_MASK (0x3U)
20561#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtTailWidth_SHIFT (0U)
20562#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtTailWidth(x) \
20563 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtTailWidth_SHIFT)) & \
20564 DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtTailWidth_MASK)
20565#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtStartDelay_MASK (0xCU)
20566#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtStartDelay_SHIFT (2U)
20567#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtStartDelay(x) \
20568 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtStartDelay_SHIFT)) & \
20569 DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P2_POdtStartDelay_MASK)
20570/*! @} */
20571
20572/*! @name DLLGAINCTL_P2 - DLL gain control */
20573/*! @{ */
20574#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainIV_MASK (0xFU)
20575#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainIV_SHIFT (0U)
20576#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainIV(x) \
20577 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainIV_SHIFT)) & \
20578 DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainIV_MASK)
20579#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainTV_MASK (0xF0U)
20580#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainTV_SHIFT (4U)
20581#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainTV(x) \
20582 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainTV_SHIFT)) & \
20583 DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllGainTV_MASK)
20584#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllSeedSel_MASK (0xF00U)
20585#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllSeedSel_SHIFT (8U)
20586#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllSeedSel(x) \
20587 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllSeedSel_SHIFT)) & \
20588 DWC_DDRPHYA_MASTER_DLLGAINCTL_P2_DllSeedSel_MASK)
20589/*! @} */
20590
20591/*! @name DFIRDDATACSDESTMAP_P2 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
20592/*! @{ */
20593#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm0_MASK (0x3U)
20594#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm0_SHIFT (0U)
20595#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm0(x) \
20596 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm0_SHIFT)) & \
20597 DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm0_MASK)
20598#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm1_MASK (0xCU)
20599#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm1_SHIFT (2U)
20600#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm1(x) \
20601 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm1_SHIFT)) & \
20602 DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm1_MASK)
20603#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm2_MASK (0x30U)
20604#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm2_SHIFT (4U)
20605#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm2(x) \
20606 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm2_SHIFT)) & \
20607 DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm2_MASK)
20608#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm3_MASK (0xC0U)
20609#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm3_SHIFT (6U)
20610#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm3(x) \
20611 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm3_SHIFT)) & \
20612 DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P2_DfiRdDestm3_MASK)
20613/*! @} */
20614
20615/*! @name VREFINGLOBAL_P2 - PHY Global Vref Controls */
20616/*! @{ */
20617#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInSel_MASK (0x7U)
20618#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInSel_SHIFT (0U)
20619#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInSel(x) \
20620 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInSel_SHIFT)) & \
20621 DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInSel_MASK)
20622#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInDAC_MASK (0x3F8U)
20623#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInDAC_SHIFT (3U)
20624#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInDAC(x) \
20625 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInDAC_SHIFT)) & \
20626 DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInDAC_MASK)
20627#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInTrim_MASK (0x3C00U)
20628#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInTrim_SHIFT (10U)
20629#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInTrim(x) \
20630 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInTrim_SHIFT)) & \
20631 DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInTrim_MASK)
20632#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInMode_MASK (0x4000U)
20633#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInMode_SHIFT (14U)
20634#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInMode(x) \
20635 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInMode_SHIFT)) & \
20636 DWC_DDRPHYA_MASTER_VREFINGLOBAL_P2_GlobalVrefInMode_MASK)
20637/*! @} */
20638
20639/*! @name DFIWRDATACSDESTMAP_P2 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
20640/*! @{ */
20641#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm0_MASK (0x3U)
20642#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm0_SHIFT (0U)
20643#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm0(x) \
20644 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm0_SHIFT)) & \
20645 DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm0_MASK)
20646#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm1_MASK (0xCU)
20647#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm1_SHIFT (2U)
20648#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm1(x) \
20649 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm1_SHIFT)) & \
20650 DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm1_MASK)
20651#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm2_MASK (0x30U)
20652#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm2_SHIFT (4U)
20653#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm2(x) \
20654 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm2_SHIFT)) & \
20655 DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm2_MASK)
20656#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm3_MASK (0xC0U)
20657#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm3_SHIFT (6U)
20658#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm3(x) \
20659 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm3_SHIFT)) & \
20660 DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P2_DfiWrDestm3_MASK)
20661/*! @} */
20662
20663/*! @name PLLCTRL2_P2 - PState dependent PLL Control Register 2 */
20664/*! @{ */
20665#define DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PllFreqSel_MASK (0x1FU)
20666#define DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PllFreqSel_SHIFT (0U)
20667#define DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PllFreqSel(x) \
20668 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PllFreqSel_SHIFT)) & \
20669 DWC_DDRPHYA_MASTER_PLLCTRL2_P2_PllFreqSel_MASK)
20670/*! @} */
20671
20672/*! @name PLLCTRL1_P2 - PState dependent PLL Control Register 1 */
20673/*! @{ */
20674#define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpIntCtrl_MASK (0x1FU)
20675#define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpIntCtrl_SHIFT (0U)
20676#define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpIntCtrl(x) \
20677 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpIntCtrl_SHIFT)) & \
20678 DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpIntCtrl_MASK)
20679#define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpPropCtrl_MASK (0x1E0U)
20680#define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpPropCtrl_SHIFT (5U)
20681#define DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpPropCtrl(x) \
20682 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpPropCtrl_SHIFT)) & \
20683 DWC_DDRPHYA_MASTER_PLLCTRL1_P2_PllCpPropCtrl_MASK)
20684/*! @} */
20685
20686/*! @name PLLTESTMODE_P2 - Additional controls for PLL CP/VCO modes of operation */
20687/*! @{ */
20688#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PllTestMode_p2_MASK (0xFFFFU)
20689#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PllTestMode_p2_SHIFT (0U)
20690#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PllTestMode_p2(x) \
20691 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PllTestMode_p2_SHIFT)) & \
20692 DWC_DDRPHYA_MASTER_PLLTESTMODE_P2_PllTestMode_p2_MASK)
20693/*! @} */
20694
20695/*! @name PLLCTRL4_P2 - PState dependent PLL Control Register 4 */
20696/*! @{ */
20697#define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpIntGsCtrl_MASK (0x1FU)
20698#define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpIntGsCtrl_SHIFT (0U)
20699#define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpIntGsCtrl(x) \
20700 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpIntGsCtrl_SHIFT)) & \
20701 DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpIntGsCtrl_MASK)
20702#define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpPropGsCtrl_MASK (0x1E0U)
20703#define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpPropGsCtrl_SHIFT (5U)
20704#define DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpPropGsCtrl(x) \
20705 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpPropGsCtrl_SHIFT)) & \
20706 DWC_DDRPHYA_MASTER_PLLCTRL4_P2_PllCpPropGsCtrl_MASK)
20707/*! @} */
20708
20709/*! @name DFIFREQRATIO_P2 - DFI Frequency Ratio */
20710/*! @{ */
20711#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DfiFreqRatio_p2_MASK (0x3U)
20712#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DfiFreqRatio_p2_SHIFT (0U)
20713#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DfiFreqRatio_p2(x) \
20714 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DfiFreqRatio_p2_SHIFT)) & \
20715 DWC_DDRPHYA_MASTER_DFIFREQRATIO_P2_DfiFreqRatio_p2_MASK)
20716/*! @} */
20717
20718/*! @name CALUCLKINFO_P3 - Impedance Calibration Clock Ratio */
20719/*! @{ */
20720#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CalUClkTicksPer1uS_MASK (0x3FFU)
20721#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CalUClkTicksPer1uS_SHIFT (0U)
20722#define DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CalUClkTicksPer1uS(x) \
20723 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CalUClkTicksPer1uS_SHIFT)) & \
20724 DWC_DDRPHYA_MASTER_CALUCLKINFO_P3_CalUClkTicksPer1uS_MASK)
20725/*! @} */
20726
20727/*! @name SEQ0BDLY0_P3 - PHY Initialization Engine (PIE) Delay Register 0 */
20728/*! @{ */
20729#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_Seq0BDLY0_p3_MASK (0xFFFFU)
20730#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_Seq0BDLY0_p3_SHIFT (0U)
20731#define DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_Seq0BDLY0_p3(x) \
20732 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_Seq0BDLY0_p3_SHIFT)) & \
20733 DWC_DDRPHYA_MASTER_SEQ0BDLY0_P3_Seq0BDLY0_p3_MASK)
20734/*! @} */
20735
20736/*! @name SEQ0BDLY1_P3 - PHY Initialization Engine (PIE) Delay Register 1 */
20737/*! @{ */
20738#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_Seq0BDLY1_p3_MASK (0xFFFFU)
20739#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_Seq0BDLY1_p3_SHIFT (0U)
20740#define DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_Seq0BDLY1_p3(x) \
20741 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_Seq0BDLY1_p3_SHIFT)) & \
20742 DWC_DDRPHYA_MASTER_SEQ0BDLY1_P3_Seq0BDLY1_p3_MASK)
20743/*! @} */
20744
20745/*! @name SEQ0BDLY2_P3 - PHY Initialization Engine (PIE) Delay Register 2 */
20746/*! @{ */
20747#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_Seq0BDLY2_p3_MASK (0xFFFFU)
20748#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_Seq0BDLY2_p3_SHIFT (0U)
20749#define DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_Seq0BDLY2_p3(x) \
20750 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_Seq0BDLY2_p3_SHIFT)) & \
20751 DWC_DDRPHYA_MASTER_SEQ0BDLY2_P3_Seq0BDLY2_p3_MASK)
20752/*! @} */
20753
20754/*! @name SEQ0BDLY3_P3 - PHY Initialization Engine (PIE) Delay Register 3 */
20755/*! @{ */
20756#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_Seq0BDLY3_p3_MASK (0xFFFFU)
20757#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_Seq0BDLY3_p3_SHIFT (0U)
20758#define DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_Seq0BDLY3_p3(x) \
20759 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_Seq0BDLY3_p3_SHIFT)) & \
20760 DWC_DDRPHYA_MASTER_SEQ0BDLY3_P3_Seq0BDLY3_p3_MASK)
20761/*! @} */
20762
20763/*! @name PPTTRAINSETUP_P3 - Setup Intervals for DFI PHY Master operations */
20764/*! @{ */
20765#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrTrainInterval_MASK (0xFU)
20766#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrTrainInterval_SHIFT (0U)
20767#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrTrainInterval(x) \
20768 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrTrainInterval_SHIFT)) & \
20769 DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrTrainInterval_MASK)
20770#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrMaxReqToAck_MASK (0x70U)
20771#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrMaxReqToAck_SHIFT (4U)
20772#define DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrMaxReqToAck(x) \
20773 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrMaxReqToAck_SHIFT)) & \
20774 DWC_DDRPHYA_MASTER_PPTTRAINSETUP_P3_PhyMstrMaxReqToAck_MASK)
20775/*! @} */
20776
20777/*! @name TRISTATEMODECA_P3 - Mode select register for MEMCLK/Address/Command Tristates */
20778/*! @{ */
20779#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DisDynAdrTri_MASK (0x1U)
20780#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DisDynAdrTri_SHIFT (0U)
20781#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DisDynAdrTri(x) \
20782 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DisDynAdrTri_SHIFT)) & \
20783 DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DisDynAdrTri_MASK)
20784#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMode_MASK (0x2U)
20785#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMode_SHIFT (1U)
20786#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMode(x) \
20787 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMode_SHIFT)) & \
20788 DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_DDR2TMode_MASK)
20789#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CkDisVal_MASK (0xCU)
20790#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CkDisVal_SHIFT (2U)
20791#define DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CkDisVal(x) \
20792 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CkDisVal_SHIFT)) & \
20793 DWC_DDRPHYA_MASTER_TRISTATEMODECA_P3_CkDisVal_MASK)
20794/*! @} */
20795
20796/*! @name HWTMRL_P3 - HWT MaxReadLatency. */
20797/*! @{ */
20798#define DWC_DDRPHYA_MASTER_HWTMRL_P3_HwtMRL_p3_MASK (0x1FU)
20799#define DWC_DDRPHYA_MASTER_HWTMRL_P3_HwtMRL_p3_SHIFT (0U)
20800#define DWC_DDRPHYA_MASTER_HWTMRL_P3_HwtMRL_p3(x) \
20801 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_HWTMRL_P3_HwtMRL_p3_SHIFT)) & \
20802 DWC_DDRPHYA_MASTER_HWTMRL_P3_HwtMRL_p3_MASK)
20803/*! @} */
20804
20805/*! @name DQSPREAMBLECONTROL_P3 - Control the PHY logic related to the read and write DQS preamble */
20806/*! @{ */
20807#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckRxDqsPre_MASK (0x1U)
20808#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckRxDqsPre_SHIFT (0U)
20809#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckRxDqsPre(x) \
20810 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckRxDqsPre_SHIFT)) & \
20811 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckRxDqsPre_MASK)
20812#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckTxDqsPre_MASK (0x2U)
20813#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckTxDqsPre_SHIFT (1U)
20814#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckTxDqsPre(x) \
20815 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckTxDqsPre_SHIFT)) & \
20816 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_TwoTckTxDqsPre_MASK)
20817#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_PositionDfeInit_MASK (0x1CU)
20818#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_PositionDfeInit_SHIFT (2U)
20819#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_PositionDfeInit(x) \
20820 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_PositionDfeInit_SHIFT)) & \
20821 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_PositionDfeInit_MASK)
20822#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TglTwoTckTxDqsPre_MASK (0x20U)
20823#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TglTwoTckTxDqsPre_SHIFT (5U)
20824#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TglTwoTckTxDqsPre(x) \
20825 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TglTwoTckTxDqsPre_SHIFT)) & \
20826 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4TglTwoTckTxDqsPre_MASK)
20827#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4PostambleExt_MASK (0x40U)
20828#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4PostambleExt_SHIFT (6U)
20829#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4PostambleExt(x) \
20830 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4PostambleExt_SHIFT)) & \
20831 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4PostambleExt_MASK)
20832#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4SttcPreBridgeRxEn_MASK (0x80U)
20833#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4SttcPreBridgeRxEn_SHIFT (7U)
20834#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4SttcPreBridgeRxEn(x) \
20835 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4SttcPreBridgeRxEn_SHIFT)) & \
20836 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_LP4SttcPreBridgeRxEn_MASK)
20837#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION_MASK (0x100U)
20838#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION_SHIFT (8U)
20839#define DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION(x) \
20840 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION_SHIFT)) & \
20841 DWC_DDRPHYA_MASTER_DQSPREAMBLECONTROL_P3_WDQSEXTENSION_MASK)
20842/*! @} */
20843
20844/*! @name DMIPINPRESENT_P3 - This Register is used to enable the Read-DBI function in each DBYTE */
20845/*! @{ */
20846#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RdDbiEnabled_MASK (0x1U)
20847#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RdDbiEnabled_SHIFT (0U)
20848#define DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RdDbiEnabled(x) \
20849 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RdDbiEnabled_SHIFT)) & \
20850 DWC_DDRPHYA_MASTER_DMIPINPRESENT_P3_RdDbiEnabled_MASK)
20851/*! @} */
20852
20853/*! @name ARDPTRINITVAL_P3 - Address/Command FIFO ReadPointer Initial Value */
20854/*! @{ */
20855#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARdPtrInitVal_p3_MASK (0xFU)
20856#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARdPtrInitVal_p3_SHIFT (0U)
20857#define DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARdPtrInitVal_p3(x) \
20858 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARdPtrInitVal_p3_SHIFT)) & \
20859 DWC_DDRPHYA_MASTER_ARDPTRINITVAL_P3_ARdPtrInitVal_p3_MASK)
20860/*! @} */
20861
20862/*! @name PROCODTTIMECTL_P3 - READ DATA On-Die Termination Timing Control (by PHY) */
20863/*! @{ */
20864#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtTailWidth_MASK (0x3U)
20865#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtTailWidth_SHIFT (0U)
20866#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtTailWidth(x) \
20867 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtTailWidth_SHIFT)) & \
20868 DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtTailWidth_MASK)
20869#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtStartDelay_MASK (0xCU)
20870#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtStartDelay_SHIFT (2U)
20871#define DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtStartDelay(x) \
20872 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtStartDelay_SHIFT)) & \
20873 DWC_DDRPHYA_MASTER_PROCODTTIMECTL_P3_POdtStartDelay_MASK)
20874/*! @} */
20875
20876/*! @name DLLGAINCTL_P3 - DLL gain control */
20877/*! @{ */
20878#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainIV_MASK (0xFU)
20879#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainIV_SHIFT (0U)
20880#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainIV(x) \
20881 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainIV_SHIFT)) & \
20882 DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainIV_MASK)
20883#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainTV_MASK (0xF0U)
20884#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainTV_SHIFT (4U)
20885#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainTV(x) \
20886 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainTV_SHIFT)) & \
20887 DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllGainTV_MASK)
20888#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllSeedSel_MASK (0xF00U)
20889#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllSeedSel_SHIFT (8U)
20890#define DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllSeedSel(x) \
20891 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllSeedSel_SHIFT)) & \
20892 DWC_DDRPHYA_MASTER_DLLGAINCTL_P3_DllSeedSel_MASK)
20893/*! @} */
20894
20895/*! @name DFIRDDATACSDESTMAP_P3 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
20896/*! @{ */
20897#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm0_MASK (0x3U)
20898#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm0_SHIFT (0U)
20899#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm0(x) \
20900 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm0_SHIFT)) & \
20901 DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm0_MASK)
20902#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm1_MASK (0xCU)
20903#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm1_SHIFT (2U)
20904#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm1(x) \
20905 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm1_SHIFT)) & \
20906 DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm1_MASK)
20907#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm2_MASK (0x30U)
20908#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm2_SHIFT (4U)
20909#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm2(x) \
20910 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm2_SHIFT)) & \
20911 DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm2_MASK)
20912#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm3_MASK (0xC0U)
20913#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm3_SHIFT (6U)
20914#define DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm3(x) \
20915 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm3_SHIFT)) & \
20916 DWC_DDRPHYA_MASTER_DFIRDDATACSDESTMAP_P3_DfiRdDestm3_MASK)
20917/*! @} */
20918
20919/*! @name VREFINGLOBAL_P3 - PHY Global Vref Controls */
20920/*! @{ */
20921#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInSel_MASK (0x7U)
20922#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInSel_SHIFT (0U)
20923#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInSel(x) \
20924 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInSel_SHIFT)) & \
20925 DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInSel_MASK)
20926#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInDAC_MASK (0x3F8U)
20927#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInDAC_SHIFT (3U)
20928#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInDAC(x) \
20929 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInDAC_SHIFT)) & \
20930 DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInDAC_MASK)
20931#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInTrim_MASK (0x3C00U)
20932#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInTrim_SHIFT (10U)
20933#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInTrim(x) \
20934 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInTrim_SHIFT)) & \
20935 DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInTrim_MASK)
20936#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInMode_MASK (0x4000U)
20937#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInMode_SHIFT (14U)
20938#define DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInMode(x) \
20939 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInMode_SHIFT)) & \
20940 DWC_DDRPHYA_MASTER_VREFINGLOBAL_P3_GlobalVrefInMode_MASK)
20941/*! @} */
20942
20943/*! @name DFIWRDATACSDESTMAP_P3 - Maps dfi_rddata_cs_n to destination dimm timing group for use with D4 LRDIMM */
20944/*! @{ */
20945#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm0_MASK (0x3U)
20946#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm0_SHIFT (0U)
20947#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm0(x) \
20948 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm0_SHIFT)) & \
20949 DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm0_MASK)
20950#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm1_MASK (0xCU)
20951#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm1_SHIFT (2U)
20952#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm1(x) \
20953 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm1_SHIFT)) & \
20954 DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm1_MASK)
20955#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm2_MASK (0x30U)
20956#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm2_SHIFT (4U)
20957#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm2(x) \
20958 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm2_SHIFT)) & \
20959 DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm2_MASK)
20960#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm3_MASK (0xC0U)
20961#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm3_SHIFT (6U)
20962#define DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm3(x) \
20963 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm3_SHIFT)) & \
20964 DWC_DDRPHYA_MASTER_DFIWRDATACSDESTMAP_P3_DfiWrDestm3_MASK)
20965/*! @} */
20966
20967/*! @name PLLCTRL2_P3 - PState dependent PLL Control Register 2 */
20968/*! @{ */
20969#define DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PllFreqSel_MASK (0x1FU)
20970#define DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PllFreqSel_SHIFT (0U)
20971#define DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PllFreqSel(x) \
20972 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PllFreqSel_SHIFT)) & \
20973 DWC_DDRPHYA_MASTER_PLLCTRL2_P3_PllFreqSel_MASK)
20974/*! @} */
20975
20976/*! @name PLLCTRL1_P3 - PState dependent PLL Control Register 1 */
20977/*! @{ */
20978#define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpIntCtrl_MASK (0x1FU)
20979#define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpIntCtrl_SHIFT (0U)
20980#define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpIntCtrl(x) \
20981 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpIntCtrl_SHIFT)) & \
20982 DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpIntCtrl_MASK)
20983#define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpPropCtrl_MASK (0x1E0U)
20984#define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpPropCtrl_SHIFT (5U)
20985#define DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpPropCtrl(x) \
20986 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpPropCtrl_SHIFT)) & \
20987 DWC_DDRPHYA_MASTER_PLLCTRL1_P3_PllCpPropCtrl_MASK)
20988/*! @} */
20989
20990/*! @name PLLTESTMODE_P3 - Additional controls for PLL CP/VCO modes of operation */
20991/*! @{ */
20992#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PllTestMode_p3_MASK (0xFFFFU)
20993#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PllTestMode_p3_SHIFT (0U)
20994#define DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PllTestMode_p3(x) \
20995 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PllTestMode_p3_SHIFT)) & \
20996 DWC_DDRPHYA_MASTER_PLLTESTMODE_P3_PllTestMode_p3_MASK)
20997/*! @} */
20998
20999/*! @name PLLCTRL4_P3 - PState dependent PLL Control Register 4 */
21000/*! @{ */
21001#define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpIntGsCtrl_MASK (0x1FU)
21002#define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpIntGsCtrl_SHIFT (0U)
21003#define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpIntGsCtrl(x) \
21004 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpIntGsCtrl_SHIFT)) & \
21005 DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpIntGsCtrl_MASK)
21006#define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpPropGsCtrl_MASK (0x1E0U)
21007#define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpPropGsCtrl_SHIFT (5U)
21008#define DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpPropGsCtrl(x) \
21009 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpPropGsCtrl_SHIFT)) & \
21010 DWC_DDRPHYA_MASTER_PLLCTRL4_P3_PllCpPropGsCtrl_MASK)
21011/*! @} */
21012
21013/*! @name DFIFREQRATIO_P3 - DFI Frequency Ratio */
21014/*! @{ */
21015#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DfiFreqRatio_p3_MASK (0x3U)
21016#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DfiFreqRatio_p3_SHIFT (0U)
21017#define DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DfiFreqRatio_p3(x) \
21018 (((uint16_t)(((uint16_t)(x)) << DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DfiFreqRatio_p3_SHIFT)) & \
21019 DWC_DDRPHYA_MASTER_DFIFREQRATIO_P3_DfiFreqRatio_p3_MASK)
21020/*! @} */
21021
21022/*!
21023 * @}
21024 */ /* end of group DWC_DDRPHYA_MASTER_Register_Masks */
21025
21026/* DWC_DDRPHYA_MASTER - Peripheral instance base addresses */
21027/** Peripheral DWC_DDRPHYA_MASTER0 base address */
21028#define DWC_DDRPHYA_MASTER0_BASE (0x3C020000u)
21029/** Peripheral DWC_DDRPHYA_MASTER0 base pointer */
21030#define DWC_DDRPHYA_MASTER0 ((DWC_DDRPHYA_MASTER_Type *)DWC_DDRPHYA_MASTER0_BASE)
21031/** Array initializer of DWC_DDRPHYA_MASTER peripheral base addresses */
21032#define DWC_DDRPHYA_MASTER_BASE_ADDRS \
21033 { \
21034 DWC_DDRPHYA_MASTER0_BASE \
21035 }
21036/** Array initializer of DWC_DDRPHYA_MASTER peripheral base pointers */
21037#define DWC_DDRPHYA_MASTER_BASE_PTRS \
21038 { \
21039 DWC_DDRPHYA_MASTER0 \
21040 }
21041
21042/*!
21043 * @}
21044 */ /* end of group DWC_DDRPHYA_MASTER_Peripheral_Access_Layer */
21045
21046/* ----------------------------------------------------------------------------
21047 -- ECSPI Peripheral Access Layer
21048 ---------------------------------------------------------------------------- */
21049
21050/*!
21051 * @addtogroup ECSPI_Peripheral_Access_Layer ECSPI Peripheral Access Layer
21052 * @{
21053 */
21054
21055/** ECSPI - Register Layout Typedef */
21056typedef struct
21057{
21058 __I uint32_t RXDATA; /**< Receive Data Register, offset: 0x0 */
21059 __O uint32_t TXDATA; /**< Transmit Data Register, offset: 0x4 */
21060 __IO uint32_t CONREG; /**< Control Register, offset: 0x8 */
21061 __IO uint32_t CONFIGREG; /**< Config Register, offset: 0xC */
21062 __IO uint32_t INTREG; /**< Interrupt Control Register, offset: 0x10 */
21063 __IO uint32_t DMAREG; /**< DMA Control Register, offset: 0x14 */
21064 __IO uint32_t STATREG; /**< Status Register, offset: 0x18 */
21065 __IO uint32_t PERIODREG; /**< Sample Period Control Register, offset: 0x1C */
21066 __IO uint32_t TESTREG; /**< Test Control Register, offset: 0x20 */
21067 uint8_t RESERVED_0[28];
21068 __O uint32_t MSGDATA; /**< Message Data Register, offset: 0x40 */
21069} ECSPI_Type;
21070
21071/* ----------------------------------------------------------------------------
21072 -- ECSPI Register Masks
21073 ---------------------------------------------------------------------------- */
21074
21075/*!
21076 * @addtogroup ECSPI_Register_Masks ECSPI Register Masks
21077 * @{
21078 */
21079
21080/*! @name RXDATA - Receive Data Register */
21081/*! @{ */
21082#define ECSPI_RXDATA_ECSPI_RXDATA_MASK (0xFFFFFFFFU)
21083#define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT (0U)
21084#define ECSPI_RXDATA_ECSPI_RXDATA(x) \
21085 (((uint32_t)(((uint32_t)(x)) << ECSPI_RXDATA_ECSPI_RXDATA_SHIFT)) & ECSPI_RXDATA_ECSPI_RXDATA_MASK)
21086/*! @} */
21087
21088/*! @name TXDATA - Transmit Data Register */
21089/*! @{ */
21090#define ECSPI_TXDATA_ECSPI_TXDATA_MASK (0xFFFFFFFFU)
21091#define ECSPI_TXDATA_ECSPI_TXDATA_SHIFT (0U)
21092#define ECSPI_TXDATA_ECSPI_TXDATA(x) \
21093 (((uint32_t)(((uint32_t)(x)) << ECSPI_TXDATA_ECSPI_TXDATA_SHIFT)) & ECSPI_TXDATA_ECSPI_TXDATA_MASK)
21094/*! @} */
21095
21096/*! @name CONREG - Control Register */
21097/*! @{ */
21098#define ECSPI_CONREG_EN_MASK (0x1U)
21099#define ECSPI_CONREG_EN_SHIFT (0U)
21100/*! EN
21101 * 0b0..Disable the block.
21102 * 0b1..Enable the block.
21103 */
21104#define ECSPI_CONREG_EN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_EN_SHIFT)) & ECSPI_CONREG_EN_MASK)
21105#define ECSPI_CONREG_HT_MASK (0x2U)
21106#define ECSPI_CONREG_HT_SHIFT (1U)
21107/*! HT
21108 * 0b0..Disable HT mode.
21109 * 0b1..Enable HT mode.
21110 */
21111#define ECSPI_CONREG_HT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_HT_SHIFT)) & ECSPI_CONREG_HT_MASK)
21112#define ECSPI_CONREG_XCH_MASK (0x4U)
21113#define ECSPI_CONREG_XCH_SHIFT (2U)
21114/*! XCH
21115 * 0b0..Idle.
21116 * 0b1..Initiates exchange (write) or busy (read).
21117 */
21118#define ECSPI_CONREG_XCH(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_XCH_SHIFT)) & ECSPI_CONREG_XCH_MASK)
21119#define ECSPI_CONREG_SMC_MASK (0x8U)
21120#define ECSPI_CONREG_SMC_SHIFT (3U)
21121/*! SMC
21122 * 0b0..SPI Exchange Bit (XCH) controls when a SPI burst can start. Setting the XCH bit will start a SPI burst or
21123 * multiple bursts. This is controlled by the SPI SS Wave Form Select (SS_CTL). Refer to XCH and SS_CTL
21124 * descriptions.
21125 * 0b1..Immediately starts a SPI burst when data is written in TXFIFO.
21126 */
21127#define ECSPI_CONREG_SMC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_SMC_SHIFT)) & ECSPI_CONREG_SMC_MASK)
21128#define ECSPI_CONREG_CHANNEL_MODE_MASK (0xF0U)
21129#define ECSPI_CONREG_CHANNEL_MODE_SHIFT (4U)
21130/*! CHANNEL_MODE
21131 * 0b0000..Slave mode.
21132 * 0b0001..Master mode.
21133 */
21134#define ECSPI_CONREG_CHANNEL_MODE(x) \
21135 (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_MODE_SHIFT)) & ECSPI_CONREG_CHANNEL_MODE_MASK)
21136#define ECSPI_CONREG_POST_DIVIDER_MASK (0xF00U)
21137#define ECSPI_CONREG_POST_DIVIDER_SHIFT (8U)
21138/*! POST_DIVIDER
21139 * 0b0000..Divide by 1.
21140 * 0b0001..Divide by 2.
21141 * 0b0010..Divide by 4.
21142 * 0b1110..Divide by 2 14 .
21143 * 0b1111..Divide by 2 15 .
21144 */
21145#define ECSPI_CONREG_POST_DIVIDER(x) \
21146 (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_POST_DIVIDER_SHIFT)) & ECSPI_CONREG_POST_DIVIDER_MASK)
21147#define ECSPI_CONREG_PRE_DIVIDER_MASK (0xF000U)
21148#define ECSPI_CONREG_PRE_DIVIDER_SHIFT (12U)
21149/*! PRE_DIVIDER
21150 * 0b0000..Divide by 1.
21151 * 0b0001..Divide by 2.
21152 * 0b0010..Divide by 3.
21153 * 0b1101..Divide by 14.
21154 * 0b1110..Divide by 15.
21155 * 0b1111..Divide by 16.
21156 */
21157#define ECSPI_CONREG_PRE_DIVIDER(x) \
21158 (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_PRE_DIVIDER_SHIFT)) & ECSPI_CONREG_PRE_DIVIDER_MASK)
21159#define ECSPI_CONREG_DRCTL_MASK (0x30000U)
21160#define ECSPI_CONREG_DRCTL_SHIFT (16U)
21161/*! DRCTL
21162 * 0b00..The SPI_RDY signal is a don't care.
21163 * 0b01..Burst will be triggered by the falling edge of the SPI_RDY signal (edge-triggered).
21164 * 0b10..Burst will be triggered by a low level of the SPI_RDY signal (level-triggered).
21165 * 0b11..Reserved.
21166 */
21167#define ECSPI_CONREG_DRCTL(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_DRCTL_SHIFT)) & ECSPI_CONREG_DRCTL_MASK)
21168#define ECSPI_CONREG_CHANNEL_SELECT_MASK (0xC0000U)
21169#define ECSPI_CONREG_CHANNEL_SELECT_SHIFT (18U)
21170/*! CHANNEL_SELECT
21171 * 0b00..Channel 0 is selected. Chip Select 0 (SS0) will be asserted.
21172 * 0b01..Channel 1 is selected. Chip Select 1 (SS1) will be asserted.
21173 * 0b10..Channel 2 is selected. Chip Select 2 (SS2) will be asserted.
21174 * 0b11..Channel 3 is selected. Chip Select 3 (SS3) will be asserted.
21175 */
21176#define ECSPI_CONREG_CHANNEL_SELECT(x) \
21177 (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_CHANNEL_SELECT_SHIFT)) & ECSPI_CONREG_CHANNEL_SELECT_MASK)
21178#define ECSPI_CONREG_BURST_LENGTH_MASK (0xFFF00000U)
21179#define ECSPI_CONREG_BURST_LENGTH_SHIFT (20U)
21180/*! BURST_LENGTH
21181 * 0b000000000000..A SPI burst contains the 1 LSB in a word.
21182 * 0b000000000001..A SPI burst contains the 2 LSB in a word.
21183 * 0b000000000010..A SPI burst contains the 3 LSB in a word.
21184 * 0b000000011111..A SPI burst contains all 32 bits in a word.
21185 * 0b000000100000..A SPI burst contains the 1 LSB in first word and all 32 bits in second word.
21186 * 0b000000100001..A SPI burst contains the 2 LSB in first word and all 32 bits in second word.
21187 * 0b111111111110..A SPI burst contains the 31 LSB in first word and 2^7 -1 words.
21188 * 0b111111111111..A SPI burst contains 2^7 words.
21189 */
21190#define ECSPI_CONREG_BURST_LENGTH(x) \
21191 (((uint32_t)(((uint32_t)(x)) << ECSPI_CONREG_BURST_LENGTH_SHIFT)) & ECSPI_CONREG_BURST_LENGTH_MASK)
21192/*! @} */
21193
21194/*! @name CONFIGREG - Config Register */
21195/*! @{ */
21196#define ECSPI_CONFIGREG_SCLK_PHA_MASK (0xFU)
21197#define ECSPI_CONFIGREG_SCLK_PHA_SHIFT (0U)
21198/*! SCLK_PHA
21199 * 0b0000..Phase 0 operation.
21200 * 0b0001..Phase 1 operation.
21201 */
21202#define ECSPI_CONFIGREG_SCLK_PHA(x) \
21203 (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_PHA_SHIFT)) & ECSPI_CONFIGREG_SCLK_PHA_MASK)
21204#define ECSPI_CONFIGREG_SCLK_POL_MASK (0xF0U)
21205#define ECSPI_CONFIGREG_SCLK_POL_SHIFT (4U)
21206/*! SCLK_POL
21207 * 0b0000..Active high polarity (0 = Idle).
21208 * 0b0001..Active low polarity (1 = Idle).
21209 */
21210#define ECSPI_CONFIGREG_SCLK_POL(x) \
21211 (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_POL_SHIFT)) & ECSPI_CONFIGREG_SCLK_POL_MASK)
21212#define ECSPI_CONFIGREG_SS_CTL_MASK (0xF00U)
21213#define ECSPI_CONFIGREG_SS_CTL_SHIFT (8U)
21214/*! SS_CTL
21215 * 0b0000..In master mode - only one SPI burst will be transmitted.
21216 * 0b0001..In master mode - Negate Chip Select (SS) signal between SPI bursts. Multiple SPI bursts will be
21217 * transmitted. The SPI transfer will automatically stop when the TXFIFO is empty.
21218 * 0b0000..In slave mode - an SPI burst is completed when the number of bits received in the shift register is
21219 * equal to (BURST LENGTH + 1). Only the n least-significant bits (n = BURST LENGTH[4:0] + 1) of the first
21220 * received word are valid. All bits subsequent to the first received word in RXFIFO are valid.
21221 * 0b0001..Reserved
21222 */
21223#define ECSPI_CONFIGREG_SS_CTL(x) \
21224 (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_CTL_SHIFT)) & ECSPI_CONFIGREG_SS_CTL_MASK)
21225#define ECSPI_CONFIGREG_SS_POL_MASK (0xF000U)
21226#define ECSPI_CONFIGREG_SS_POL_SHIFT (12U)
21227/*! SS_POL
21228 * 0b0000..Active low.
21229 * 0b0001..Active high.
21230 */
21231#define ECSPI_CONFIGREG_SS_POL(x) \
21232 (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SS_POL_SHIFT)) & ECSPI_CONFIGREG_SS_POL_MASK)
21233#define ECSPI_CONFIGREG_DATA_CTL_MASK (0xF0000U)
21234#define ECSPI_CONFIGREG_DATA_CTL_SHIFT (16U)
21235/*! DATA_CTL
21236 * 0b0000..Stay high.
21237 * 0b0001..Stay low.
21238 */
21239#define ECSPI_CONFIGREG_DATA_CTL(x) \
21240 (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_DATA_CTL_SHIFT)) & ECSPI_CONFIGREG_DATA_CTL_MASK)
21241#define ECSPI_CONFIGREG_SCLK_CTL_MASK (0xF00000U)
21242#define ECSPI_CONFIGREG_SCLK_CTL_SHIFT (20U)
21243/*! SCLK_CTL
21244 * 0b0000..Stay low.
21245 * 0b0001..Stay high.
21246 */
21247#define ECSPI_CONFIGREG_SCLK_CTL(x) \
21248 (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_SCLK_CTL_SHIFT)) & ECSPI_CONFIGREG_SCLK_CTL_MASK)
21249#define ECSPI_CONFIGREG_HT_LENGTH_MASK (0x1F000000U)
21250#define ECSPI_CONFIGREG_HT_LENGTH_SHIFT (24U)
21251#define ECSPI_CONFIGREG_HT_LENGTH(x) \
21252 (((uint32_t)(((uint32_t)(x)) << ECSPI_CONFIGREG_HT_LENGTH_SHIFT)) & ECSPI_CONFIGREG_HT_LENGTH_MASK)
21253/*! @} */
21254
21255/*! @name INTREG - Interrupt Control Register */
21256/*! @{ */
21257#define ECSPI_INTREG_TEEN_MASK (0x1U)
21258#define ECSPI_INTREG_TEEN_SHIFT (0U)
21259/*! TEEN
21260 * 0b0..Disable
21261 * 0b1..Enable
21262 */
21263#define ECSPI_INTREG_TEEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TEEN_SHIFT)) & ECSPI_INTREG_TEEN_MASK)
21264#define ECSPI_INTREG_TDREN_MASK (0x2U)
21265#define ECSPI_INTREG_TDREN_SHIFT (1U)
21266/*! TDREN
21267 * 0b0..Disable
21268 * 0b1..Enable
21269 */
21270#define ECSPI_INTREG_TDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TDREN_SHIFT)) & ECSPI_INTREG_TDREN_MASK)
21271#define ECSPI_INTREG_TFEN_MASK (0x4U)
21272#define ECSPI_INTREG_TFEN_SHIFT (2U)
21273/*! TFEN
21274 * 0b0..Disable
21275 * 0b1..Enable
21276 */
21277#define ECSPI_INTREG_TFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TFEN_SHIFT)) & ECSPI_INTREG_TFEN_MASK)
21278#define ECSPI_INTREG_RREN_MASK (0x8U)
21279#define ECSPI_INTREG_RREN_SHIFT (3U)
21280/*! RREN
21281 * 0b0..Disable
21282 * 0b1..Enable
21283 */
21284#define ECSPI_INTREG_RREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RREN_SHIFT)) & ECSPI_INTREG_RREN_MASK)
21285#define ECSPI_INTREG_RDREN_MASK (0x10U)
21286#define ECSPI_INTREG_RDREN_SHIFT (4U)
21287/*! RDREN
21288 * 0b0..Disable
21289 * 0b1..Enable
21290 */
21291#define ECSPI_INTREG_RDREN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RDREN_SHIFT)) & ECSPI_INTREG_RDREN_MASK)
21292#define ECSPI_INTREG_RFEN_MASK (0x20U)
21293#define ECSPI_INTREG_RFEN_SHIFT (5U)
21294/*! RFEN
21295 * 0b0..Disable
21296 * 0b1..Enable
21297 */
21298#define ECSPI_INTREG_RFEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_RFEN_SHIFT)) & ECSPI_INTREG_RFEN_MASK)
21299#define ECSPI_INTREG_ROEN_MASK (0x40U)
21300#define ECSPI_INTREG_ROEN_SHIFT (6U)
21301/*! ROEN
21302 * 0b0..Disable
21303 * 0b1..Enable
21304 */
21305#define ECSPI_INTREG_ROEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_ROEN_SHIFT)) & ECSPI_INTREG_ROEN_MASK)
21306#define ECSPI_INTREG_TCEN_MASK (0x80U)
21307#define ECSPI_INTREG_TCEN_SHIFT (7U)
21308/*! TCEN
21309 * 0b0..Disable
21310 * 0b1..Enable
21311 */
21312#define ECSPI_INTREG_TCEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_INTREG_TCEN_SHIFT)) & ECSPI_INTREG_TCEN_MASK)
21313/*! @} */
21314
21315/*! @name DMAREG - DMA Control Register */
21316/*! @{ */
21317#define ECSPI_DMAREG_TX_THRESHOLD_MASK (0x3FU)
21318#define ECSPI_DMAREG_TX_THRESHOLD_SHIFT (0U)
21319#define ECSPI_DMAREG_TX_THRESHOLD(x) \
21320 (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_TX_THRESHOLD_MASK)
21321#define ECSPI_DMAREG_TEDEN_MASK (0x80U)
21322#define ECSPI_DMAREG_TEDEN_SHIFT (7U)
21323/*! TEDEN
21324 * 0b0..Disable
21325 * 0b1..Enable
21326 */
21327#define ECSPI_DMAREG_TEDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_TEDEN_SHIFT)) & ECSPI_DMAREG_TEDEN_MASK)
21328#define ECSPI_DMAREG_RX_THRESHOLD_MASK (0x3F0000U)
21329#define ECSPI_DMAREG_RX_THRESHOLD_SHIFT (16U)
21330#define ECSPI_DMAREG_RX_THRESHOLD(x) \
21331 (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_THRESHOLD_SHIFT)) & ECSPI_DMAREG_RX_THRESHOLD_MASK)
21332#define ECSPI_DMAREG_RXDEN_MASK (0x800000U)
21333#define ECSPI_DMAREG_RXDEN_SHIFT (23U)
21334/*! RXDEN
21335 * 0b0..Disable
21336 * 0b1..Enable
21337 */
21338#define ECSPI_DMAREG_RXDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXDEN_SHIFT)) & ECSPI_DMAREG_RXDEN_MASK)
21339#define ECSPI_DMAREG_RX_DMA_LENGTH_MASK (0x3F000000U)
21340#define ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT (24U)
21341#define ECSPI_DMAREG_RX_DMA_LENGTH(x) \
21342 (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RX_DMA_LENGTH_SHIFT)) & ECSPI_DMAREG_RX_DMA_LENGTH_MASK)
21343#define ECSPI_DMAREG_RXTDEN_MASK (0x80000000U)
21344#define ECSPI_DMAREG_RXTDEN_SHIFT (31U)
21345/*! RXTDEN
21346 * 0b0..Disable
21347 * 0b1..Enable
21348 */
21349#define ECSPI_DMAREG_RXTDEN(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_DMAREG_RXTDEN_SHIFT)) & ECSPI_DMAREG_RXTDEN_MASK)
21350/*! @} */
21351
21352/*! @name STATREG - Status Register */
21353/*! @{ */
21354#define ECSPI_STATREG_TE_MASK (0x1U)
21355#define ECSPI_STATREG_TE_SHIFT (0U)
21356/*! TE
21357 * 0b0..TXFIFO contains one or more words.
21358 * 0b1..TXFIFO is empty.
21359 */
21360#define ECSPI_STATREG_TE(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TE_SHIFT)) & ECSPI_STATREG_TE_MASK)
21361#define ECSPI_STATREG_TDR_MASK (0x2U)
21362#define ECSPI_STATREG_TDR_SHIFT (1U)
21363/*! TDR
21364 * 0b0..Number of valid data slots in TXFIFO is greater than TX_THRESHOLD.
21365 * 0b1..Number of valid data slots in TXFIFO is not greater than TX_THRESHOLD.
21366 */
21367#define ECSPI_STATREG_TDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TDR_SHIFT)) & ECSPI_STATREG_TDR_MASK)
21368#define ECSPI_STATREG_TF_MASK (0x4U)
21369#define ECSPI_STATREG_TF_SHIFT (2U)
21370/*! TF
21371 * 0b0..TXFIFO is not Full.
21372 * 0b1..TXFIFO is Full.
21373 */
21374#define ECSPI_STATREG_TF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TF_SHIFT)) & ECSPI_STATREG_TF_MASK)
21375#define ECSPI_STATREG_RR_MASK (0x8U)
21376#define ECSPI_STATREG_RR_SHIFT (3U)
21377/*! RR
21378 * 0b0..No valid data in RXFIFO.
21379 * 0b1..More than 1 word in RXFIFO.
21380 */
21381#define ECSPI_STATREG_RR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RR_SHIFT)) & ECSPI_STATREG_RR_MASK)
21382#define ECSPI_STATREG_RDR_MASK (0x10U)
21383#define ECSPI_STATREG_RDR_SHIFT (4U)
21384/*! RDR
21385 * 0b0..When RXTDE is set - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD.
21386 * 0b1..When RXTDE is set - Number of data entries in the RXFIFO is greater than RX_THRESHOLD or a DMA TAIL DMA
21387 * condition exists. 0b0..When RXTDE is clear - Number of data entries in the RXFIFO is not greater than RX_THRESHOLD.
21388 * 0b1..When RXTDE is clear - Number of data entries in the RXFIFO is greater than RX_THRESHOLD.
21389 */
21390#define ECSPI_STATREG_RDR(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RDR_SHIFT)) & ECSPI_STATREG_RDR_MASK)
21391#define ECSPI_STATREG_RF_MASK (0x20U)
21392#define ECSPI_STATREG_RF_SHIFT (5U)
21393/*! RF
21394 * 0b0..Not Full.
21395 * 0b1..Full.
21396 */
21397#define ECSPI_STATREG_RF(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RF_SHIFT)) & ECSPI_STATREG_RF_MASK)
21398#define ECSPI_STATREG_RO_MASK (0x40U)
21399#define ECSPI_STATREG_RO_SHIFT (6U)
21400/*! RO
21401 * 0b0..RXFIFO has no overflow.
21402 * 0b1..RXFIFO has overflowed.
21403 */
21404#define ECSPI_STATREG_RO(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_RO_SHIFT)) & ECSPI_STATREG_RO_MASK)
21405#define ECSPI_STATREG_TC_MASK (0x80U)
21406#define ECSPI_STATREG_TC_SHIFT (7U)
21407/*! TC
21408 * 0b0..Transfer in progress.
21409 * 0b1..Transfer completed.
21410 */
21411#define ECSPI_STATREG_TC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_STATREG_TC_SHIFT)) & ECSPI_STATREG_TC_MASK)
21412/*! @} */
21413
21414/*! @name PERIODREG - Sample Period Control Register */
21415/*! @{ */
21416#define ECSPI_PERIODREG_SAMPLE_PERIOD_MASK (0x7FFFU)
21417#define ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT (0U)
21418/*! SAMPLE_PERIOD
21419 * 0b000000000000000..0 wait states inserted
21420 * 0b000000000000001..1 wait state inserted
21421 * 0b111111111111110..32766 wait states inserted
21422 * 0b111111111111111..32767 wait states inserted
21423 */
21424#define ECSPI_PERIODREG_SAMPLE_PERIOD(x) \
21425 (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_SAMPLE_PERIOD_SHIFT)) & ECSPI_PERIODREG_SAMPLE_PERIOD_MASK)
21426#define ECSPI_PERIODREG_CSRC_MASK (0x8000U)
21427#define ECSPI_PERIODREG_CSRC_SHIFT (15U)
21428/*! CSRC
21429 * 0b0..SPI Clock (SCLK)
21430 * 0b1..Low-Frequency Reference Clock (32.768 KHz)
21431 */
21432#define ECSPI_PERIODREG_CSRC(x) \
21433 (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSRC_SHIFT)) & ECSPI_PERIODREG_CSRC_MASK)
21434#define ECSPI_PERIODREG_CSD_CTL_MASK (0x3F0000U)
21435#define ECSPI_PERIODREG_CSD_CTL_SHIFT (16U)
21436#define ECSPI_PERIODREG_CSD_CTL(x) \
21437 (((uint32_t)(((uint32_t)(x)) << ECSPI_PERIODREG_CSD_CTL_SHIFT)) & ECSPI_PERIODREG_CSD_CTL_MASK)
21438/*! @} */
21439
21440/*! @name TESTREG - Test Control Register */
21441/*! @{ */
21442#define ECSPI_TESTREG_TXCNT_MASK (0x7FU)
21443#define ECSPI_TESTREG_TXCNT_SHIFT (0U)
21444#define ECSPI_TESTREG_TXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_TXCNT_SHIFT)) & ECSPI_TESTREG_TXCNT_MASK)
21445#define ECSPI_TESTREG_RXCNT_MASK (0x7F00U)
21446#define ECSPI_TESTREG_RXCNT_SHIFT (8U)
21447#define ECSPI_TESTREG_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_RXCNT_SHIFT)) & ECSPI_TESTREG_RXCNT_MASK)
21448#define ECSPI_TESTREG_LBC_MASK (0x80000000U)
21449#define ECSPI_TESTREG_LBC_SHIFT (31U)
21450/*! LBC
21451 * 0b0..Not connected.
21452 * 0b1..Transmitter and receiver sections internally connected for Loopback.
21453 */
21454#define ECSPI_TESTREG_LBC(x) (((uint32_t)(((uint32_t)(x)) << ECSPI_TESTREG_LBC_SHIFT)) & ECSPI_TESTREG_LBC_MASK)
21455/*! @} */
21456
21457/*! @name MSGDATA - Message Data Register */
21458/*! @{ */
21459#define ECSPI_MSGDATA_ECSPI_MSGDATA_MASK (0xFFFFFFFFU)
21460#define ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT (0U)
21461#define ECSPI_MSGDATA_ECSPI_MSGDATA(x) \
21462 (((uint32_t)(((uint32_t)(x)) << ECSPI_MSGDATA_ECSPI_MSGDATA_SHIFT)) & ECSPI_MSGDATA_ECSPI_MSGDATA_MASK)
21463/*! @} */
21464
21465/*!
21466 * @}
21467 */ /* end of group ECSPI_Register_Masks */
21468
21469/* ECSPI - Peripheral instance base addresses */
21470/** Peripheral ECSPI1 base address */
21471#define ECSPI1_BASE (0x30820000u)
21472/** Peripheral ECSPI1 base pointer */
21473#define ECSPI1 ((ECSPI_Type *)ECSPI1_BASE)
21474/** Peripheral ECSPI2 base address */
21475#define ECSPI2_BASE (0x30830000u)
21476/** Peripheral ECSPI2 base pointer */
21477#define ECSPI2 ((ECSPI_Type *)ECSPI2_BASE)
21478/** Peripheral ECSPI3 base address */
21479#define ECSPI3_BASE (0x30840000u)
21480/** Peripheral ECSPI3 base pointer */
21481#define ECSPI3 ((ECSPI_Type *)ECSPI3_BASE)
21482/** Array initializer of ECSPI peripheral base addresses */
21483#define ECSPI_BASE_ADDRS \
21484 { \
21485 0u, ECSPI1_BASE, ECSPI2_BASE, ECSPI3_BASE \
21486 }
21487/** Array initializer of ECSPI peripheral base pointers */
21488#define ECSPI_BASE_PTRS \
21489 { \
21490 (ECSPI_Type *)0u, ECSPI1, ECSPI2, ECSPI3 \
21491 }
21492/** Interrupt vectors for the ECSPI peripheral type */
21493#define ECSPI_IRQS \
21494 { \
21495 NotAvail_IRQn, ECSPI1_IRQn, ECSPI2_IRQn, ECSPI3_IRQn \
21496 }
21497
21498/*!
21499 * @}
21500 */ /* end of group ECSPI_Peripheral_Access_Layer */
21501
21502/* ----------------------------------------------------------------------------
21503 -- ENET Peripheral Access Layer
21504 ---------------------------------------------------------------------------- */
21505
21506/*!
21507 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
21508 * @{
21509 */
21510
21511/** ENET - Register Layout Typedef */
21512typedef struct
21513{
21514 uint8_t RESERVED_0[4];
21515 __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
21516 __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
21517 uint8_t RESERVED_1[4];
21518 __IO uint32_t RDAR; /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */
21519 __IO uint32_t TDAR; /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */
21520 uint8_t RESERVED_2[12];
21521 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
21522 uint8_t RESERVED_3[24];
21523 __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
21524 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
21525 uint8_t RESERVED_4[28];
21526 __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
21527 uint8_t RESERVED_5[28];
21528 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
21529 uint8_t RESERVED_6[60];
21530 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
21531 uint8_t RESERVED_7[28];
21532 __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
21533 __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
21534 __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
21535 __IO uint32_t TXIC[3]; /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */
21536 uint8_t RESERVED_8[4];
21537 __IO uint32_t RXIC[3]; /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */
21538 uint8_t RESERVED_9[12];
21539 __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
21540 __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
21541 __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
21542 __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
21543 uint8_t RESERVED_10[28];
21544 __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
21545 uint8_t RESERVED_11[24];
21546 __IO uint32_t RDSR1; /**< Receive Descriptor Ring 1 Start Register, offset: 0x160 */
21547 __IO uint32_t TDSR1; /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164 */
21548 __IO uint32_t MRBR1; /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168 */
21549 __IO uint32_t RDSR2; /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C */
21550 __IO uint32_t TDSR2; /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */
21551 __IO uint32_t MRBR2; /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */
21552 uint8_t RESERVED_12[8];
21553 __IO uint32_t RDSR; /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */
21554 __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */
21555 __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */
21556 uint8_t RESERVED_13[4];
21557 __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
21558 __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
21559 __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
21560 __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
21561 __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
21562 __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
21563 __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
21564 __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
21565 __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
21566 uint8_t RESERVED_14[12];
21567 __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
21568 __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
21569 __IO uint32_t
21570 RCMR[2]; /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4 */
21571 uint8_t RESERVED_15[8];
21572 __IO uint32_t DMACFG[2]; /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4 */
21573 __IO uint32_t RDAR1; /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0 */
21574 __IO uint32_t TDAR1; /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4 */
21575 __IO uint32_t RDAR2; /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */
21576 __IO uint32_t TDAR2; /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */
21577 __IO uint32_t QOS; /**< QOS Scheme, offset: 0x1F0 */
21578 uint8_t RESERVED_16[12];
21579 uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */
21580 __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
21581 __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
21582 __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
21583 __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
21584 __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
21585 __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
21586 __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
21587 __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
21588 __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
21589 __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
21590 __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
21591 __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
21592 __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
21593 __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
21594 __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
21595 __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
21596 __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
21597 uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */
21598 __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
21599 __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
21600 __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
21601 __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
21602 __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
21603 __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
21604 __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
21605 __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
21606 __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */
21607 __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
21608 __I uint32_t
21609 IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
21610 uint8_t RESERVED_17[12];
21611 __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
21612 __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
21613 __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
21614 __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
21615 __I uint32_t
21616 RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
21617 __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
21618 __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
21619 __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
21620 uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */
21621 __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
21622 __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
21623 __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
21624 __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
21625 __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
21626 __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
21627 __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
21628 __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
21629 __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
21630 __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
21631 __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
21632 __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
21633 __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
21634 __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
21635 __I uint32_t
21636 IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
21637 uint8_t RESERVED_18[284];
21638 __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
21639 __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
21640 __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
21641 __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
21642 __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
21643 __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
21644 __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
21645 uint8_t RESERVED_19[488];
21646 __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
21647 struct
21648 { /* offset: 0x608, array step: 0x8 */
21649 __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
21650 __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
21651 } CHANNEL[4];
21652} ENET_Type;
21653
21654/* ----------------------------------------------------------------------------
21655 -- ENET Register Masks
21656 ---------------------------------------------------------------------------- */
21657
21658/*!
21659 * @addtogroup ENET_Register_Masks ENET Register Masks
21660 * @{
21661 */
21662
21663/*! @name EIR - Interrupt Event Register */
21664/*! @{ */
21665#define ENET_EIR_RXB1_MASK (0x1U)
21666#define ENET_EIR_RXB1_SHIFT (0U)
21667#define ENET_EIR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK)
21668#define ENET_EIR_RXF1_MASK (0x2U)
21669#define ENET_EIR_RXF1_SHIFT (1U)
21670#define ENET_EIR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK)
21671#define ENET_EIR_TXB1_MASK (0x4U)
21672#define ENET_EIR_TXB1_SHIFT (2U)
21673#define ENET_EIR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK)
21674#define ENET_EIR_TXF1_MASK (0x8U)
21675#define ENET_EIR_TXF1_SHIFT (3U)
21676#define ENET_EIR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK)
21677#define ENET_EIR_RXB2_MASK (0x10U)
21678#define ENET_EIR_RXB2_SHIFT (4U)
21679#define ENET_EIR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK)
21680#define ENET_EIR_RXF2_MASK (0x20U)
21681#define ENET_EIR_RXF2_SHIFT (5U)
21682#define ENET_EIR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK)
21683#define ENET_EIR_TXB2_MASK (0x40U)
21684#define ENET_EIR_TXB2_SHIFT (6U)
21685#define ENET_EIR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK)
21686#define ENET_EIR_TXF2_MASK (0x80U)
21687#define ENET_EIR_TXF2_SHIFT (7U)
21688#define ENET_EIR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK)
21689#define ENET_EIR_RXFLUSH_0_MASK (0x1000U)
21690#define ENET_EIR_RXFLUSH_0_SHIFT (12U)
21691#define ENET_EIR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK)
21692#define ENET_EIR_RXFLUSH_1_MASK (0x2000U)
21693#define ENET_EIR_RXFLUSH_1_SHIFT (13U)
21694#define ENET_EIR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK)
21695#define ENET_EIR_RXFLUSH_2_MASK (0x4000U)
21696#define ENET_EIR_RXFLUSH_2_SHIFT (14U)
21697#define ENET_EIR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK)
21698#define ENET_EIR_TS_TIMER_MASK (0x8000U)
21699#define ENET_EIR_TS_TIMER_SHIFT (15U)
21700#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
21701#define ENET_EIR_TS_AVAIL_MASK (0x10000U)
21702#define ENET_EIR_TS_AVAIL_SHIFT (16U)
21703#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
21704#define ENET_EIR_WAKEUP_MASK (0x20000U)
21705#define ENET_EIR_WAKEUP_SHIFT (17U)
21706#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
21707#define ENET_EIR_PLR_MASK (0x40000U)
21708#define ENET_EIR_PLR_SHIFT (18U)
21709#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
21710#define ENET_EIR_UN_MASK (0x80000U)
21711#define ENET_EIR_UN_SHIFT (19U)
21712#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
21713#define ENET_EIR_RL_MASK (0x100000U)
21714#define ENET_EIR_RL_SHIFT (20U)
21715#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
21716#define ENET_EIR_LC_MASK (0x200000U)
21717#define ENET_EIR_LC_SHIFT (21U)
21718#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
21719#define ENET_EIR_EBERR_MASK (0x400000U)
21720#define ENET_EIR_EBERR_SHIFT (22U)
21721#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
21722#define ENET_EIR_MII_MASK (0x800000U)
21723#define ENET_EIR_MII_SHIFT (23U)
21724#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
21725#define ENET_EIR_RXB_MASK (0x1000000U)
21726#define ENET_EIR_RXB_SHIFT (24U)
21727#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
21728#define ENET_EIR_RXF_MASK (0x2000000U)
21729#define ENET_EIR_RXF_SHIFT (25U)
21730#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
21731#define ENET_EIR_TXB_MASK (0x4000000U)
21732#define ENET_EIR_TXB_SHIFT (26U)
21733#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
21734#define ENET_EIR_TXF_MASK (0x8000000U)
21735#define ENET_EIR_TXF_SHIFT (27U)
21736#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
21737#define ENET_EIR_GRA_MASK (0x10000000U)
21738#define ENET_EIR_GRA_SHIFT (28U)
21739#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
21740#define ENET_EIR_BABT_MASK (0x20000000U)
21741#define ENET_EIR_BABT_SHIFT (29U)
21742#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
21743#define ENET_EIR_BABR_MASK (0x40000000U)
21744#define ENET_EIR_BABR_SHIFT (30U)
21745#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
21746/*! @} */
21747
21748/*! @name EIMR - Interrupt Mask Register */
21749/*! @{ */
21750#define ENET_EIMR_RXB1_MASK (0x1U)
21751#define ENET_EIMR_RXB1_SHIFT (0U)
21752#define ENET_EIMR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK)
21753#define ENET_EIMR_RXF1_MASK (0x2U)
21754#define ENET_EIMR_RXF1_SHIFT (1U)
21755#define ENET_EIMR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK)
21756#define ENET_EIMR_TXB1_MASK (0x4U)
21757#define ENET_EIMR_TXB1_SHIFT (2U)
21758#define ENET_EIMR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK)
21759#define ENET_EIMR_TXF1_MASK (0x8U)
21760#define ENET_EIMR_TXF1_SHIFT (3U)
21761#define ENET_EIMR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK)
21762#define ENET_EIMR_RXB2_MASK (0x10U)
21763#define ENET_EIMR_RXB2_SHIFT (4U)
21764#define ENET_EIMR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK)
21765#define ENET_EIMR_RXF2_MASK (0x20U)
21766#define ENET_EIMR_RXF2_SHIFT (5U)
21767#define ENET_EIMR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK)
21768#define ENET_EIMR_TXB2_MASK (0x40U)
21769#define ENET_EIMR_TXB2_SHIFT (6U)
21770#define ENET_EIMR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK)
21771#define ENET_EIMR_TXF2_MASK (0x80U)
21772#define ENET_EIMR_TXF2_SHIFT (7U)
21773#define ENET_EIMR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK)
21774#define ENET_EIMR_RXFLUSH_0_MASK (0x1000U)
21775#define ENET_EIMR_RXFLUSH_0_SHIFT (12U)
21776#define ENET_EIMR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK)
21777#define ENET_EIMR_RXFLUSH_1_MASK (0x2000U)
21778#define ENET_EIMR_RXFLUSH_1_SHIFT (13U)
21779#define ENET_EIMR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK)
21780#define ENET_EIMR_RXFLUSH_2_MASK (0x4000U)
21781#define ENET_EIMR_RXFLUSH_2_SHIFT (14U)
21782#define ENET_EIMR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK)
21783#define ENET_EIMR_TS_TIMER_MASK (0x8000U)
21784#define ENET_EIMR_TS_TIMER_SHIFT (15U)
21785#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
21786#define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
21787#define ENET_EIMR_TS_AVAIL_SHIFT (16U)
21788#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
21789#define ENET_EIMR_WAKEUP_MASK (0x20000U)
21790#define ENET_EIMR_WAKEUP_SHIFT (17U)
21791#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
21792#define ENET_EIMR_PLR_MASK (0x40000U)
21793#define ENET_EIMR_PLR_SHIFT (18U)
21794#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
21795#define ENET_EIMR_UN_MASK (0x80000U)
21796#define ENET_EIMR_UN_SHIFT (19U)
21797#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
21798#define ENET_EIMR_RL_MASK (0x100000U)
21799#define ENET_EIMR_RL_SHIFT (20U)
21800#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
21801#define ENET_EIMR_LC_MASK (0x200000U)
21802#define ENET_EIMR_LC_SHIFT (21U)
21803#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
21804#define ENET_EIMR_EBERR_MASK (0x400000U)
21805#define ENET_EIMR_EBERR_SHIFT (22U)
21806#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
21807#define ENET_EIMR_MII_MASK (0x800000U)
21808#define ENET_EIMR_MII_SHIFT (23U)
21809#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
21810#define ENET_EIMR_RXB_MASK (0x1000000U)
21811#define ENET_EIMR_RXB_SHIFT (24U)
21812#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
21813#define ENET_EIMR_RXF_MASK (0x2000000U)
21814#define ENET_EIMR_RXF_SHIFT (25U)
21815#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
21816#define ENET_EIMR_TXB_MASK (0x4000000U)
21817#define ENET_EIMR_TXB_SHIFT (26U)
21818/*! TXB - TXB Interrupt Mask
21819 * 0b0..The corresponding interrupt source is masked.
21820 * 0b1..The corresponding interrupt source is not masked.
21821 */
21822#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
21823#define ENET_EIMR_TXF_MASK (0x8000000U)
21824#define ENET_EIMR_TXF_SHIFT (27U)
21825/*! TXF - TXF Interrupt Mask
21826 * 0b0..The corresponding interrupt source is masked.
21827 * 0b1..The corresponding interrupt source is not masked.
21828 */
21829#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
21830#define ENET_EIMR_GRA_MASK (0x10000000U)
21831#define ENET_EIMR_GRA_SHIFT (28U)
21832/*! GRA - GRA Interrupt Mask
21833 * 0b0..The corresponding interrupt source is masked.
21834 * 0b1..The corresponding interrupt source is not masked.
21835 */
21836#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
21837#define ENET_EIMR_BABT_MASK (0x20000000U)
21838#define ENET_EIMR_BABT_SHIFT (29U)
21839/*! BABT - BABT Interrupt Mask
21840 * 0b0..The corresponding interrupt source is masked.
21841 * 0b1..The corresponding interrupt source is not masked.
21842 */
21843#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
21844#define ENET_EIMR_BABR_MASK (0x40000000U)
21845#define ENET_EIMR_BABR_SHIFT (30U)
21846/*! BABR - BABR Interrupt Mask
21847 * 0b0..The corresponding interrupt source is masked.
21848 * 0b1..The corresponding interrupt source is not masked.
21849 */
21850#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
21851/*! @} */
21852
21853/*! @name RDAR - Receive Descriptor Active Register - Ring 0 */
21854/*! @{ */
21855#define ENET_RDAR_RDAR_MASK (0x1000000U)
21856#define ENET_RDAR_RDAR_SHIFT (24U)
21857#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
21858/*! @} */
21859
21860/*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */
21861/*! @{ */
21862#define ENET_TDAR_TDAR_MASK (0x1000000U)
21863#define ENET_TDAR_TDAR_SHIFT (24U)
21864#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
21865/*! @} */
21866
21867/*! @name ECR - Ethernet Control Register */
21868/*! @{ */
21869#define ENET_ECR_RESET_MASK (0x1U)
21870#define ENET_ECR_RESET_SHIFT (0U)
21871#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
21872#define ENET_ECR_ETHEREN_MASK (0x2U)
21873#define ENET_ECR_ETHEREN_SHIFT (1U)
21874/*! ETHEREN - Ethernet Enable
21875 * 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted
21876 * frame. 0b1..MAC is enabled, and reception and transmission are possible.
21877 */
21878#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
21879#define ENET_ECR_MAGICEN_MASK (0x4U)
21880#define ENET_ECR_MAGICEN_SHIFT (2U)
21881/*! MAGICEN - Magic Packet Detection Enable
21882 * 0b0..Magic detection logic disabled.
21883 * 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
21884 */
21885#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
21886#define ENET_ECR_SLEEP_MASK (0x8U)
21887#define ENET_ECR_SLEEP_SHIFT (3U)
21888/*! SLEEP - Sleep Mode Enable
21889 * 0b0..Normal operating mode.
21890 * 0b1..Sleep mode.
21891 */
21892#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
21893#define ENET_ECR_EN1588_MASK (0x10U)
21894#define ENET_ECR_EN1588_SHIFT (4U)
21895/*! EN1588 - EN1588 Enable
21896 * 0b0..Legacy FEC buffer descriptors and functions enabled.
21897 * 0b1..Enhanced frame time-stamping functions enabled.
21898 */
21899#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
21900#define ENET_ECR_SPEED_MASK (0x20U)
21901#define ENET_ECR_SPEED_SHIFT (5U)
21902/*! SPEED
21903 * 0b0..10/100-Mbit/s mode
21904 * 0b1..1000-Mbit/s mode
21905 */
21906#define ENET_ECR_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK)
21907#define ENET_ECR_DBGEN_MASK (0x40U)
21908#define ENET_ECR_DBGEN_SHIFT (6U)
21909/*! DBGEN - Debug Enable
21910 * 0b0..MAC continues operation in debug mode.
21911 * 0b1..MAC enters hardware freeze mode when the processor is in debug mode.
21912 */
21913#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
21914#define ENET_ECR_DBSWP_MASK (0x100U)
21915#define ENET_ECR_DBSWP_SHIFT (8U)
21916/*! DBSWP - Descriptor Byte Swapping Enable
21917 * 0b0..The buffer descriptor bytes are not swapped to support big-endian devices.
21918 * 0b1..The buffer descriptor bytes are swapped to support little-endian devices.
21919 */
21920#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
21921#define ENET_ECR_SVLANEN_MASK (0x200U)
21922#define ENET_ECR_SVLANEN_SHIFT (9U)
21923/*! SVLANEN - S-VLAN enable
21924 * 0b0..Only the EtherType 0x8100 will be considered for VLAN detection.
21925 * 0b1..The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in
21926 * receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the
21927 * classification match comparators, RCMRn.
21928 */
21929#define ENET_ECR_SVLANEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK)
21930#define ENET_ECR_VLANUSE2ND_MASK (0x400U)
21931#define ENET_ECR_VLANUSE2ND_SHIFT (10U)
21932/*! VLANUSE2ND - VLAN use second tag
21933 * 0b0..Always extract data from the first VLAN tag if it exists.
21934 * 0b1..When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A
21935 * double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The
21936 * second tag must be a C-VLAN
21937 */
21938#define ENET_ECR_VLANUSE2ND(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK)
21939#define ENET_ECR_SVLANDBL_MASK (0x800U)
21940#define ENET_ECR_SVLANDBL_SHIFT (11U)
21941#define ENET_ECR_SVLANDBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK)
21942/*! @} */
21943
21944/*! @name MMFR - MII Management Frame Register */
21945/*! @{ */
21946#define ENET_MMFR_DATA_MASK (0xFFFFU)
21947#define ENET_MMFR_DATA_SHIFT (0U)
21948#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
21949#define ENET_MMFR_TA_MASK (0x30000U)
21950#define ENET_MMFR_TA_SHIFT (16U)
21951#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
21952#define ENET_MMFR_RA_MASK (0x7C0000U)
21953#define ENET_MMFR_RA_SHIFT (18U)
21954#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
21955#define ENET_MMFR_PA_MASK (0xF800000U)
21956#define ENET_MMFR_PA_SHIFT (23U)
21957#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
21958#define ENET_MMFR_OP_MASK (0x30000000U)
21959#define ENET_MMFR_OP_SHIFT (28U)
21960#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
21961#define ENET_MMFR_ST_MASK (0xC0000000U)
21962#define ENET_MMFR_ST_SHIFT (30U)
21963#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
21964/*! @} */
21965
21966/*! @name MSCR - MII Speed Control Register */
21967/*! @{ */
21968#define ENET_MSCR_MII_SPEED_MASK (0x7EU)
21969#define ENET_MSCR_MII_SPEED_SHIFT (1U)
21970#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
21971#define ENET_MSCR_DIS_PRE_MASK (0x80U)
21972#define ENET_MSCR_DIS_PRE_SHIFT (7U)
21973/*! DIS_PRE - Disable Preamble
21974 * 0b0..Preamble enabled.
21975 * 0b1..Preamble (32 ones) is not prepended to the MII management frame.
21976 */
21977#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
21978#define ENET_MSCR_HOLDTIME_MASK (0x700U)
21979#define ENET_MSCR_HOLDTIME_SHIFT (8U)
21980/*! HOLDTIME - Hold time On MDIO Output
21981 * 0b000..1 internal module clock cycle
21982 * 0b001..2 internal module clock cycles
21983 * 0b010..3 internal module clock cycles
21984 * 0b111..8 internal module clock cycles
21985 */
21986#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
21987/*! @} */
21988
21989/*! @name MIBC - MIB Control Register */
21990/*! @{ */
21991#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
21992#define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
21993/*! MIB_CLEAR - MIB Clear
21994 * 0b0..See note above.
21995 * 0b1..All statistics counters are reset to 0.
21996 */
21997#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
21998#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
21999#define ENET_MIBC_MIB_IDLE_SHIFT (30U)
22000/*! MIB_IDLE - MIB Idle
22001 * 0b0..The MIB block is updating MIB counters.
22002 * 0b1..The MIB block is not currently updating any MIB counters.
22003 */
22004#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
22005#define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
22006#define ENET_MIBC_MIB_DIS_SHIFT (31U)
22007/*! MIB_DIS - Disable MIB Logic
22008 * 0b0..MIB logic is enabled.
22009 * 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
22010 */
22011#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
22012/*! @} */
22013
22014/*! @name RCR - Receive Control Register */
22015/*! @{ */
22016#define ENET_RCR_LOOP_MASK (0x1U)
22017#define ENET_RCR_LOOP_SHIFT (0U)
22018/*! LOOP - Internal Loopback
22019 * 0b0..Loopback disabled.
22020 * 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT
22021 * must be cleared.
22022 */
22023#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
22024#define ENET_RCR_DRT_MASK (0x2U)
22025#define ENET_RCR_DRT_SHIFT (1U)
22026/*! DRT - Disable Receive On Transmit
22027 * 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit
22028 * activity in half-duplex mode. 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex
22029 * mode.)
22030 */
22031#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
22032#define ENET_RCR_MII_MODE_MASK (0x4U)
22033#define ENET_RCR_MII_MODE_SHIFT (2U)
22034/*! MII_MODE - Media Independent Interface Mode
22035 * 0b0..Reserved.
22036 * 0b1..MII or RMII mode, as indicated by the RMII_MODE field.
22037 */
22038#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
22039#define ENET_RCR_PROM_MASK (0x8U)
22040#define ENET_RCR_PROM_SHIFT (3U)
22041/*! PROM - Promiscuous Mode
22042 * 0b0..Disabled.
22043 * 0b1..Enabled.
22044 */
22045#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
22046#define ENET_RCR_BC_REJ_MASK (0x10U)
22047#define ENET_RCR_BC_REJ_SHIFT (4U)
22048#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
22049#define ENET_RCR_FCE_MASK (0x20U)
22050#define ENET_RCR_FCE_SHIFT (5U)
22051#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
22052#define ENET_RCR_RGMII_EN_MASK (0x40U)
22053#define ENET_RCR_RGMII_EN_SHIFT (6U)
22054/*! RGMII_EN - RGMII Mode Enable
22055 * 0b0..MAC configured for non-RGMII operation
22056 * 0b1..MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If
22057 * ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode.
22058 */
22059#define ENET_RCR_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK)
22060#define ENET_RCR_RMII_MODE_MASK (0x100U)
22061#define ENET_RCR_RMII_MODE_SHIFT (8U)
22062/*! RMII_MODE - RMII Mode Enable
22063 * 0b0..MAC configured for MII mode.
22064 * 0b1..MAC configured for RMII operation.
22065 */
22066#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
22067#define ENET_RCR_RMII_10T_MASK (0x200U)
22068#define ENET_RCR_RMII_10T_SHIFT (9U)
22069/*! RMII_10T
22070 * 0b0..100-Mbit/s operation.
22071 * 0b1..10-Mbit/s operation.
22072 */
22073#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
22074#define ENET_RCR_PADEN_MASK (0x1000U)
22075#define ENET_RCR_PADEN_SHIFT (12U)
22076/*! PADEN - Enable Frame Padding Remove On Receive
22077 * 0b0..No padding is removed on receive by the MAC.
22078 * 0b1..Padding is removed from received frames.
22079 */
22080#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
22081#define ENET_RCR_PAUFWD_MASK (0x2000U)
22082#define ENET_RCR_PAUFWD_SHIFT (13U)
22083/*! PAUFWD - Terminate/Forward Pause Frames
22084 * 0b0..Pause frames are terminated and discarded in the MAC.
22085 * 0b1..Pause frames are forwarded to the user application.
22086 */
22087#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
22088#define ENET_RCR_CRCFWD_MASK (0x4000U)
22089#define ENET_RCR_CRCFWD_SHIFT (14U)
22090/*! CRCFWD - Terminate/Forward Received CRC
22091 * 0b0..The CRC field of received frames is transmitted to the user application.
22092 * 0b1..The CRC field is stripped from the frame.
22093 */
22094#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
22095#define ENET_RCR_CFEN_MASK (0x8000U)
22096#define ENET_RCR_CFEN_SHIFT (15U)
22097/*! CFEN - MAC Control Frame Enable
22098 * 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client
22099 * interface. 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
22100 */
22101#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
22102#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
22103#define ENET_RCR_MAX_FL_SHIFT (16U)
22104#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
22105#define ENET_RCR_NLC_MASK (0x40000000U)
22106#define ENET_RCR_NLC_SHIFT (30U)
22107/*! NLC - Payload Length Check Disable
22108 * 0b0..The payload length check is disabled.
22109 * 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the
22110 * EIR[PLR] field.
22111 */
22112#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
22113#define ENET_RCR_GRS_MASK (0x80000000U)
22114#define ENET_RCR_GRS_SHIFT (31U)
22115#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
22116/*! @} */
22117
22118/*! @name TCR - Transmit Control Register */
22119/*! @{ */
22120#define ENET_TCR_GTS_MASK (0x1U)
22121#define ENET_TCR_GTS_SHIFT (0U)
22122#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
22123#define ENET_TCR_FDEN_MASK (0x4U)
22124#define ENET_TCR_FDEN_SHIFT (2U)
22125#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
22126#define ENET_TCR_TFC_PAUSE_MASK (0x8U)
22127#define ENET_TCR_TFC_PAUSE_SHIFT (3U)
22128/*! TFC_PAUSE - Transmit Frame Control Pause
22129 * 0b0..No PAUSE frame transmitted.
22130 * 0b1..The MAC stops transmission of data frames after the current transmission is complete.
22131 */
22132#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
22133#define ENET_TCR_RFC_PAUSE_MASK (0x10U)
22134#define ENET_TCR_RFC_PAUSE_SHIFT (4U)
22135#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
22136#define ENET_TCR_ADDSEL_MASK (0xE0U)
22137#define ENET_TCR_ADDSEL_SHIFT (5U)
22138/*! ADDSEL - Source MAC Address Select On Transmit
22139 * 0b000..Node MAC address programmed on PADDR1/2 registers.
22140 * 0b100..Reserved.
22141 * 0b101..Reserved.
22142 * 0b110..Reserved.
22143 */
22144#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
22145#define ENET_TCR_ADDINS_MASK (0x100U)
22146#define ENET_TCR_ADDINS_SHIFT (8U)
22147/*! ADDINS - Set MAC Address On Transmit
22148 * 0b0..The source MAC address is not modified by the MAC.
22149 * 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
22150 */
22151#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
22152#define ENET_TCR_CRCFWD_MASK (0x200U)
22153#define ENET_TCR_CRCFWD_SHIFT (9U)
22154/*! CRCFWD - Forward Frame From Application With CRC
22155 * 0b0..TxBD[TC] controls whether the frame has a CRC from the application.
22156 * 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the
22157 * application.
22158 */
22159#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
22160/*! @} */
22161
22162/*! @name PALR - Physical Address Lower Register */
22163/*! @{ */
22164#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
22165#define ENET_PALR_PADDR1_SHIFT (0U)
22166#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
22167/*! @} */
22168
22169/*! @name PAUR - Physical Address Upper Register */
22170/*! @{ */
22171#define ENET_PAUR_TYPE_MASK (0xFFFFU)
22172#define ENET_PAUR_TYPE_SHIFT (0U)
22173#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
22174#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
22175#define ENET_PAUR_PADDR2_SHIFT (16U)
22176#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
22177/*! @} */
22178
22179/*! @name OPD - Opcode/Pause Duration Register */
22180/*! @{ */
22181#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
22182#define ENET_OPD_PAUSE_DUR_SHIFT (0U)
22183#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
22184#define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
22185#define ENET_OPD_OPCODE_SHIFT (16U)
22186#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
22187/*! @} */
22188
22189/*! @name TXIC - Transmit Interrupt Coalescing Register */
22190/*! @{ */
22191#define ENET_TXIC_ICTT_MASK (0xFFFFU)
22192#define ENET_TXIC_ICTT_SHIFT (0U)
22193#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
22194#define ENET_TXIC_ICFT_MASK (0xFF00000U)
22195#define ENET_TXIC_ICFT_SHIFT (20U)
22196#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
22197#define ENET_TXIC_ICCS_MASK (0x40000000U)
22198#define ENET_TXIC_ICCS_SHIFT (30U)
22199/*! ICCS - Interrupt Coalescing Timer Clock Source Select
22200 * 0b0..Use MII/GMII TX clocks.
22201 * 0b1..Use ENET system clock.
22202 */
22203#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
22204#define ENET_TXIC_ICEN_MASK (0x80000000U)
22205#define ENET_TXIC_ICEN_SHIFT (31U)
22206/*! ICEN - Interrupt Coalescing Enable
22207 * 0b0..Disable Interrupt coalescing.
22208 * 0b1..Enable Interrupt coalescing.
22209 */
22210#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
22211/*! @} */
22212
22213/* The count of ENET_TXIC */
22214#define ENET_TXIC_COUNT (3U)
22215
22216/*! @name RXIC - Receive Interrupt Coalescing Register */
22217/*! @{ */
22218#define ENET_RXIC_ICTT_MASK (0xFFFFU)
22219#define ENET_RXIC_ICTT_SHIFT (0U)
22220#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
22221#define ENET_RXIC_ICFT_MASK (0xFF00000U)
22222#define ENET_RXIC_ICFT_SHIFT (20U)
22223#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
22224#define ENET_RXIC_ICCS_MASK (0x40000000U)
22225#define ENET_RXIC_ICCS_SHIFT (30U)
22226/*! ICCS - Interrupt Coalescing Timer Clock Source Select
22227 * 0b0..Use MII/GMII TX clocks.
22228 * 0b1..Use ENET system clock.
22229 */
22230#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
22231#define ENET_RXIC_ICEN_MASK (0x80000000U)
22232#define ENET_RXIC_ICEN_SHIFT (31U)
22233/*! ICEN - Interrupt Coalescing Enable
22234 * 0b0..Disable Interrupt coalescing.
22235 * 0b1..Enable Interrupt coalescing.
22236 */
22237#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
22238/*! @} */
22239
22240/* The count of ENET_RXIC */
22241#define ENET_RXIC_COUNT (3U)
22242
22243/*! @name IAUR - Descriptor Individual Upper Address Register */
22244/*! @{ */
22245#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
22246#define ENET_IAUR_IADDR1_SHIFT (0U)
22247#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
22248/*! @} */
22249
22250/*! @name IALR - Descriptor Individual Lower Address Register */
22251/*! @{ */
22252#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
22253#define ENET_IALR_IADDR2_SHIFT (0U)
22254#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
22255/*! @} */
22256
22257/*! @name GAUR - Descriptor Group Upper Address Register */
22258/*! @{ */
22259#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
22260#define ENET_GAUR_GADDR1_SHIFT (0U)
22261#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
22262/*! @} */
22263
22264/*! @name GALR - Descriptor Group Lower Address Register */
22265/*! @{ */
22266#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
22267#define ENET_GALR_GADDR2_SHIFT (0U)
22268#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
22269/*! @} */
22270
22271/*! @name TFWR - Transmit FIFO Watermark Register */
22272/*! @{ */
22273#define ENET_TFWR_TFWR_MASK (0x3FU)
22274#define ENET_TFWR_TFWR_SHIFT (0U)
22275/*! TFWR - Transmit FIFO Write
22276 * 0b000000..64 bytes written.
22277 * 0b000001..64 bytes written.
22278 * 0b000010..128 bytes written.
22279 * 0b000011..192 bytes written.
22280 * 0b111111..4032 bytes written.
22281 */
22282#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
22283#define ENET_TFWR_STRFWD_MASK (0x100U)
22284#define ENET_TFWR_STRFWD_SHIFT (8U)
22285/*! STRFWD - Store And Forward Enable
22286 * 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR].
22287 * 0b1..Enabled.
22288 */
22289#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
22290/*! @} */
22291
22292/*! @name RDSR1 - Receive Descriptor Ring 1 Start Register */
22293/*! @{ */
22294#define ENET_RDSR1_R_DES_START_MASK (0xFFFFFFF8U)
22295#define ENET_RDSR1_R_DES_START_SHIFT (3U)
22296#define ENET_RDSR1_R_DES_START(x) \
22297 (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK)
22298/*! @} */
22299
22300/*! @name TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register */
22301/*! @{ */
22302#define ENET_TDSR1_X_DES_START_MASK (0xFFFFFFF8U)
22303#define ENET_TDSR1_X_DES_START_SHIFT (3U)
22304#define ENET_TDSR1_X_DES_START(x) \
22305 (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK)
22306/*! @} */
22307
22308/*! @name MRBR1 - Maximum Receive Buffer Size Register - Ring 1 */
22309/*! @{ */
22310#define ENET_MRBR1_R_BUF_SIZE_MASK (0x7F0U)
22311#define ENET_MRBR1_R_BUF_SIZE_SHIFT (4U)
22312#define ENET_MRBR1_R_BUF_SIZE(x) \
22313 (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK)
22314/*! @} */
22315
22316/*! @name RDSR2 - Receive Descriptor Ring 2 Start Register */
22317/*! @{ */
22318#define ENET_RDSR2_R_DES_START_MASK (0xFFFFFFF8U)
22319#define ENET_RDSR2_R_DES_START_SHIFT (3U)
22320#define ENET_RDSR2_R_DES_START(x) \
22321 (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK)
22322/*! @} */
22323
22324/*! @name TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register */
22325/*! @{ */
22326#define ENET_TDSR2_X_DES_START_MASK (0xFFFFFFF8U)
22327#define ENET_TDSR2_X_DES_START_SHIFT (3U)
22328#define ENET_TDSR2_X_DES_START(x) \
22329 (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK)
22330/*! @} */
22331
22332/*! @name MRBR2 - Maximum Receive Buffer Size Register - Ring 2 */
22333/*! @{ */
22334#define ENET_MRBR2_R_BUF_SIZE_MASK (0x7F0U)
22335#define ENET_MRBR2_R_BUF_SIZE_SHIFT (4U)
22336#define ENET_MRBR2_R_BUF_SIZE(x) \
22337 (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK)
22338/*! @} */
22339
22340/*! @name RDSR - Receive Descriptor Ring 0 Start Register */
22341/*! @{ */
22342#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
22343#define ENET_RDSR_R_DES_START_SHIFT (3U)
22344#define ENET_RDSR_R_DES_START(x) \
22345 (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
22346/*! @} */
22347
22348/*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */
22349/*! @{ */
22350#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
22351#define ENET_TDSR_X_DES_START_SHIFT (3U)
22352#define ENET_TDSR_X_DES_START(x) \
22353 (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
22354/*! @} */
22355
22356/*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */
22357/*! @{ */
22358#define ENET_MRBR_R_BUF_SIZE_MASK (0x7F0U)
22359#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
22360#define ENET_MRBR_R_BUF_SIZE(x) \
22361 (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
22362/*! @} */
22363
22364/*! @name RSFL - Receive FIFO Section Full Threshold */
22365/*! @{ */
22366#define ENET_RSFL_RX_SECTION_FULL_MASK (0x3FFU)
22367#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
22368#define ENET_RSFL_RX_SECTION_FULL(x) \
22369 (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
22370/*! @} */
22371
22372/*! @name RSEM - Receive FIFO Section Empty Threshold */
22373/*! @{ */
22374#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0x3FFU)
22375#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
22376#define ENET_RSEM_RX_SECTION_EMPTY(x) \
22377 (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
22378#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
22379#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
22380#define ENET_RSEM_STAT_SECTION_EMPTY(x) \
22381 (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
22382/*! @} */
22383
22384/*! @name RAEM - Receive FIFO Almost Empty Threshold */
22385/*! @{ */
22386#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0x3FFU)
22387#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
22388#define ENET_RAEM_RX_ALMOST_EMPTY(x) \
22389 (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
22390/*! @} */
22391
22392/*! @name RAFL - Receive FIFO Almost Full Threshold */
22393/*! @{ */
22394#define ENET_RAFL_RX_ALMOST_FULL_MASK (0x3FFU)
22395#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
22396#define ENET_RAFL_RX_ALMOST_FULL(x) \
22397 (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
22398/*! @} */
22399
22400/*! @name TSEM - Transmit FIFO Section Empty Threshold */
22401/*! @{ */
22402#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0x3FFU)
22403#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
22404#define ENET_TSEM_TX_SECTION_EMPTY(x) \
22405 (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
22406/*! @} */
22407
22408/*! @name TAEM - Transmit FIFO Almost Empty Threshold */
22409/*! @{ */
22410#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0x3FFU)
22411#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
22412#define ENET_TAEM_TX_ALMOST_EMPTY(x) \
22413 (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
22414/*! @} */
22415
22416/*! @name TAFL - Transmit FIFO Almost Full Threshold */
22417/*! @{ */
22418#define ENET_TAFL_TX_ALMOST_FULL_MASK (0x3FFU)
22419#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
22420#define ENET_TAFL_TX_ALMOST_FULL(x) \
22421 (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
22422/*! @} */
22423
22424/*! @name TIPG - Transmit Inter-Packet Gap */
22425/*! @{ */
22426#define ENET_TIPG_IPG_MASK (0x1FU)
22427#define ENET_TIPG_IPG_SHIFT (0U)
22428#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
22429/*! @} */
22430
22431/*! @name FTRL - Frame Truncation Length */
22432/*! @{ */
22433#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
22434#define ENET_FTRL_TRUNC_FL_SHIFT (0U)
22435#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
22436/*! @} */
22437
22438/*! @name TACC - Transmit Accelerator Function Configuration */
22439/*! @{ */
22440#define ENET_TACC_SHIFT16_MASK (0x1U)
22441#define ENET_TACC_SHIFT16_SHIFT (0U)
22442/*! SHIFT16 - TX FIFO Shift-16
22443 * 0b0..Disabled.
22444 * 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the
22445 * frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This
22446 * function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is
22447 * extended to a 16-byte header.
22448 */
22449#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
22450#define ENET_TACC_IPCHK_MASK (0x8U)
22451#define ENET_TACC_IPCHK_SHIFT (3U)
22452/*! IPCHK
22453 * 0b0..Checksum is not inserted.
22454 * 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must
22455 * be cleared. If a non-IP frame is transmitted the frame is not modified.
22456 */
22457#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
22458#define ENET_TACC_PROCHK_MASK (0x10U)
22459#define ENET_TACC_PROCHK_SHIFT (4U)
22460/*! PROCHK
22461 * 0b0..Checksum not inserted.
22462 * 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the
22463 * frame. The checksum field must be cleared. The other frames are not modified.
22464 */
22465#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
22466/*! @} */
22467
22468/*! @name RACC - Receive Accelerator Function Configuration */
22469/*! @{ */
22470#define ENET_RACC_PADREM_MASK (0x1U)
22471#define ENET_RACC_PADREM_SHIFT (0U)
22472/*! PADREM - Enable Padding Removal For Short IP Frames
22473 * 0b0..Padding not removed.
22474 * 0b1..Any bytes following the IP payload section of the frame are removed from the frame.
22475 */
22476#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
22477#define ENET_RACC_IPDIS_MASK (0x2U)
22478#define ENET_RACC_IPDIS_SHIFT (1U)
22479/*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum
22480 * 0b0..Frames with wrong IPv4 header checksum are not discarded.
22481 * 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no
22482 * header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in
22483 * store and forward mode (RSFL cleared).
22484 */
22485#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
22486#define ENET_RACC_PRODIS_MASK (0x4U)
22487#define ENET_RACC_PRODIS_SHIFT (2U)
22488/*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum
22489 * 0b0..Frames with wrong checksum are not discarded.
22490 * 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame
22491 * is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL
22492 * cleared).
22493 */
22494#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
22495#define ENET_RACC_LINEDIS_MASK (0x40U)
22496#define ENET_RACC_LINEDIS_SHIFT (6U)
22497/*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors
22498 * 0b0..Frames with errors are not discarded.
22499 * 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user
22500 * application interface.
22501 */
22502#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
22503#define ENET_RACC_SHIFT16_MASK (0x80U)
22504#define ENET_RACC_SHIFT16_SHIFT (7U)
22505/*! SHIFT16 - RX FIFO Shift-16
22506 * 0b0..Disabled.
22507 * 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
22508 */
22509#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
22510/*! @} */
22511
22512/*! @name RCMR - Receive Classification Match Register for Class n */
22513/*! @{ */
22514#define ENET_RCMR_CMP0_MASK (0x7U)
22515#define ENET_RCMR_CMP0_SHIFT (0U)
22516#define ENET_RCMR_CMP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK)
22517#define ENET_RCMR_CMP1_MASK (0x70U)
22518#define ENET_RCMR_CMP1_SHIFT (4U)
22519#define ENET_RCMR_CMP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK)
22520#define ENET_RCMR_CMP2_MASK (0x700U)
22521#define ENET_RCMR_CMP2_SHIFT (8U)
22522#define ENET_RCMR_CMP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK)
22523#define ENET_RCMR_CMP3_MASK (0x7000U)
22524#define ENET_RCMR_CMP3_SHIFT (12U)
22525#define ENET_RCMR_CMP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK)
22526#define ENET_RCMR_MATCHEN_MASK (0x10000U)
22527#define ENET_RCMR_MATCHEN_SHIFT (16U)
22528/*! MATCHEN - Match Enable
22529 * 0b0..Disabled (default): no compares will occur and the classification indicator for this class will never assert.
22530 * 0b1..The register contents are valid and a comparison with all compare values is done when a VLAN frame is received.
22531 */
22532#define ENET_RCMR_MATCHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK)
22533/*! @} */
22534
22535/* The count of ENET_RCMR */
22536#define ENET_RCMR_COUNT (2U)
22537
22538/*! @name DMACFG - DMA Class Based Configuration */
22539/*! @{ */
22540#define ENET_DMACFG_IDLE_SLOPE_MASK (0xFFFFU)
22541#define ENET_DMACFG_IDLE_SLOPE_SHIFT (0U)
22542#define ENET_DMACFG_IDLE_SLOPE(x) \
22543 (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK)
22544#define ENET_DMACFG_DMA_CLASS_EN_MASK (0x10000U)
22545#define ENET_DMACFG_DMA_CLASS_EN_SHIFT (16U)
22546/*! DMA_CLASS_EN - DMA class enable
22547 * 0b0..The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also
22548 * requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2
22549 * queues are disabled then their frames will be placed in queue 0.
22550 * 0b1..Enable the DMA controller to support the corresponding descriptor ring for this class of traffic.
22551 */
22552#define ENET_DMACFG_DMA_CLASS_EN(x) \
22553 (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK)
22554#define ENET_DMACFG_CALC_NOIPG_MASK (0x20000U)
22555#define ENET_DMACFG_CALC_NOIPG_SHIFT (17U)
22556/*! CALC_NOIPG - Calculate no IPG
22557 * 0b0..The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred
22558 * for a frame when doing bandwidth calculations. This is the default.
22559 * 0b1..Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping,
22560 * when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every
22561 * frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames
22562 * will become more bandwidth than large frames due to the relation of data to IPG overhead).
22563 */
22564#define ENET_DMACFG_CALC_NOIPG(x) \
22565 (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK)
22566/*! @} */
22567
22568/* The count of ENET_DMACFG */
22569#define ENET_DMACFG_COUNT (2U)
22570
22571/*! @name RDAR1 - Receive Descriptor Active Register - Ring 1 */
22572/*! @{ */
22573#define ENET_RDAR1_RDAR_MASK (0x1000000U)
22574#define ENET_RDAR1_RDAR_SHIFT (24U)
22575#define ENET_RDAR1_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK)
22576/*! @} */
22577
22578/*! @name TDAR1 - Transmit Descriptor Active Register - Ring 1 */
22579/*! @{ */
22580#define ENET_TDAR1_TDAR_MASK (0x1000000U)
22581#define ENET_TDAR1_TDAR_SHIFT (24U)
22582#define ENET_TDAR1_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK)
22583/*! @} */
22584
22585/*! @name RDAR2 - Receive Descriptor Active Register - Ring 2 */
22586/*! @{ */
22587#define ENET_RDAR2_RDAR_MASK (0x1000000U)
22588#define ENET_RDAR2_RDAR_SHIFT (24U)
22589#define ENET_RDAR2_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK)
22590/*! @} */
22591
22592/*! @name TDAR2 - Transmit Descriptor Active Register - Ring 2 */
22593/*! @{ */
22594#define ENET_TDAR2_TDAR_MASK (0x1000000U)
22595#define ENET_TDAR2_TDAR_SHIFT (24U)
22596#define ENET_TDAR2_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK)
22597/*! @} */
22598
22599/*! @name QOS - QOS Scheme */
22600/*! @{ */
22601#define ENET_QOS_TX_SCHEME_MASK (0x7U)
22602#define ENET_QOS_TX_SCHEME_SHIFT (0U)
22603/*! TX_SCHEME - TX scheme configuration
22604 * 0b000..Credit-based scheme
22605 * 0b001..Round-robin scheme
22606 */
22607#define ENET_QOS_TX_SCHEME(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK)
22608#define ENET_QOS_RX_FLUSH0_MASK (0x8U)
22609#define ENET_QOS_RX_FLUSH0_SHIFT (3U)
22610/*! RX_FLUSH0 - RX Flush Ring 0
22611 * 0b0..Disable
22612 * 0b1..Enable
22613 */
22614#define ENET_QOS_RX_FLUSH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK)
22615#define ENET_QOS_RX_FLUSH1_MASK (0x10U)
22616#define ENET_QOS_RX_FLUSH1_SHIFT (4U)
22617/*! RX_FLUSH1 - RX Flush Ring 1
22618 * 0b0..Disable
22619 * 0b1..Enable
22620 */
22621#define ENET_QOS_RX_FLUSH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK)
22622#define ENET_QOS_RX_FLUSH2_MASK (0x20U)
22623#define ENET_QOS_RX_FLUSH2_SHIFT (5U)
22624/*! RX_FLUSH2 - RX Flush Ring 2
22625 * 0b0..Disable
22626 * 0b1..Enable
22627 */
22628#define ENET_QOS_RX_FLUSH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK)
22629/*! @} */
22630
22631/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
22632/*! @{ */
22633#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
22634#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
22635#define ENET_RMON_T_PACKETS_TXPKTS(x) \
22636 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
22637/*! @} */
22638
22639/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
22640/*! @{ */
22641#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
22642#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
22643#define ENET_RMON_T_BC_PKT_TXPKTS(x) \
22644 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
22645/*! @} */
22646
22647/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
22648/*! @{ */
22649#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
22650#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
22651#define ENET_RMON_T_MC_PKT_TXPKTS(x) \
22652 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
22653/*! @} */
22654
22655/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
22656/*! @{ */
22657#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
22658#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
22659#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) \
22660 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
22661/*! @} */
22662
22663/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
22664/*! @{ */
22665#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
22666#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
22667#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) \
22668 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
22669/*! @} */
22670
22671/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
22672/*! @{ */
22673#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
22674#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
22675#define ENET_RMON_T_OVERSIZE_TXPKTS(x) \
22676 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
22677/*! @} */
22678
22679/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
22680/*! @{ */
22681#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
22682#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
22683#define ENET_RMON_T_FRAG_TXPKTS(x) \
22684 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
22685/*! @} */
22686
22687/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
22688/*! @{ */
22689#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
22690#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
22691#define ENET_RMON_T_JAB_TXPKTS(x) \
22692 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
22693/*! @} */
22694
22695/*! @name RMON_T_COL - Tx Collision Count Statistic Register */
22696/*! @{ */
22697#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
22698#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
22699#define ENET_RMON_T_COL_TXPKTS(x) \
22700 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
22701/*! @} */
22702
22703/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
22704/*! @{ */
22705#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
22706#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
22707#define ENET_RMON_T_P64_TXPKTS(x) \
22708 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
22709/*! @} */
22710
22711/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
22712/*! @{ */
22713#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
22714#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
22715#define ENET_RMON_T_P65TO127_TXPKTS(x) \
22716 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
22717/*! @} */
22718
22719/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
22720/*! @{ */
22721#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
22722#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
22723#define ENET_RMON_T_P128TO255_TXPKTS(x) \
22724 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
22725/*! @} */
22726
22727/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
22728/*! @{ */
22729#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
22730#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
22731#define ENET_RMON_T_P256TO511_TXPKTS(x) \
22732 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
22733/*! @} */
22734
22735/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
22736/*! @{ */
22737#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
22738#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
22739#define ENET_RMON_T_P512TO1023_TXPKTS(x) \
22740 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
22741/*! @} */
22742
22743/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
22744/*! @{ */
22745#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
22746#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
22747#define ENET_RMON_T_P1024TO2047_TXPKTS(x) \
22748 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
22749/*! @} */
22750
22751/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
22752/*! @{ */
22753#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
22754#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
22755#define ENET_RMON_T_P_GTE2048_TXPKTS(x) \
22756 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
22757/*! @} */
22758
22759/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
22760/*! @{ */
22761#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
22762#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
22763#define ENET_RMON_T_OCTETS_TXOCTS(x) \
22764 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
22765/*! @} */
22766
22767/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
22768/*! @{ */
22769#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
22770#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
22771#define ENET_IEEE_T_FRAME_OK_COUNT(x) \
22772 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
22773/*! @} */
22774
22775/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
22776/*! @{ */
22777#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
22778#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
22779#define ENET_IEEE_T_1COL_COUNT(x) \
22780 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
22781/*! @} */
22782
22783/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
22784/*! @{ */
22785#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
22786#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
22787#define ENET_IEEE_T_MCOL_COUNT(x) \
22788 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
22789/*! @} */
22790
22791/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
22792/*! @{ */
22793#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
22794#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
22795#define ENET_IEEE_T_DEF_COUNT(x) \
22796 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
22797/*! @} */
22798
22799/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
22800/*! @{ */
22801#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
22802#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
22803#define ENET_IEEE_T_LCOL_COUNT(x) \
22804 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
22805/*! @} */
22806
22807/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
22808/*! @{ */
22809#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
22810#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
22811#define ENET_IEEE_T_EXCOL_COUNT(x) \
22812 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
22813/*! @} */
22814
22815/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
22816/*! @{ */
22817#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
22818#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
22819#define ENET_IEEE_T_MACERR_COUNT(x) \
22820 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
22821/*! @} */
22822
22823/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
22824/*! @{ */
22825#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
22826#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
22827#define ENET_IEEE_T_CSERR_COUNT(x) \
22828 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
22829/*! @} */
22830
22831/*! @name IEEE_T_SQE - Reserved Statistic Register */
22832/*! @{ */
22833#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)
22834#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U)
22835#define ENET_IEEE_T_SQE_COUNT(x) \
22836 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
22837/*! @} */
22838
22839/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
22840/*! @{ */
22841#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
22842#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
22843#define ENET_IEEE_T_FDXFC_COUNT(x) \
22844 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
22845/*! @} */
22846
22847/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
22848/*! @{ */
22849#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
22850#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
22851#define ENET_IEEE_T_OCTETS_OK_COUNT(x) \
22852 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
22853/*! @} */
22854
22855/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
22856/*! @{ */
22857#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
22858#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
22859#define ENET_RMON_R_PACKETS_COUNT(x) \
22860 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
22861/*! @} */
22862
22863/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
22864/*! @{ */
22865#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
22866#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
22867#define ENET_RMON_R_BC_PKT_COUNT(x) \
22868 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
22869/*! @} */
22870
22871/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
22872/*! @{ */
22873#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
22874#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
22875#define ENET_RMON_R_MC_PKT_COUNT(x) \
22876 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
22877/*! @} */
22878
22879/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
22880/*! @{ */
22881#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
22882#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
22883#define ENET_RMON_R_CRC_ALIGN_COUNT(x) \
22884 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
22885/*! @} */
22886
22887/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
22888/*! @{ */
22889#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
22890#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
22891#define ENET_RMON_R_UNDERSIZE_COUNT(x) \
22892 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
22893/*! @} */
22894
22895/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
22896/*! @{ */
22897#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
22898#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
22899#define ENET_RMON_R_OVERSIZE_COUNT(x) \
22900 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
22901/*! @} */
22902
22903/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
22904/*! @{ */
22905#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
22906#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
22907#define ENET_RMON_R_FRAG_COUNT(x) \
22908 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
22909/*! @} */
22910
22911/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
22912/*! @{ */
22913#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
22914#define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
22915#define ENET_RMON_R_JAB_COUNT(x) \
22916 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
22917/*! @} */
22918
22919/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
22920/*! @{ */
22921#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
22922#define ENET_RMON_R_P64_COUNT_SHIFT (0U)
22923#define ENET_RMON_R_P64_COUNT(x) \
22924 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
22925/*! @} */
22926
22927/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
22928/*! @{ */
22929#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
22930#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
22931#define ENET_RMON_R_P65TO127_COUNT(x) \
22932 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
22933/*! @} */
22934
22935/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
22936/*! @{ */
22937#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
22938#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
22939#define ENET_RMON_R_P128TO255_COUNT(x) \
22940 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
22941/*! @} */
22942
22943/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
22944/*! @{ */
22945#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
22946#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
22947#define ENET_RMON_R_P256TO511_COUNT(x) \
22948 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
22949/*! @} */
22950
22951/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
22952/*! @{ */
22953#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
22954#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
22955#define ENET_RMON_R_P512TO1023_COUNT(x) \
22956 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
22957/*! @} */
22958
22959/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
22960/*! @{ */
22961#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
22962#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
22963#define ENET_RMON_R_P1024TO2047_COUNT(x) \
22964 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
22965/*! @} */
22966
22967/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
22968/*! @{ */
22969#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
22970#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
22971#define ENET_RMON_R_P_GTE2048_COUNT(x) \
22972 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
22973/*! @} */
22974
22975/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
22976/*! @{ */
22977#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
22978#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
22979#define ENET_RMON_R_OCTETS_COUNT(x) \
22980 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
22981/*! @} */
22982
22983/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
22984/*! @{ */
22985#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
22986#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
22987#define ENET_IEEE_R_DROP_COUNT(x) \
22988 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
22989/*! @} */
22990
22991/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
22992/*! @{ */
22993#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
22994#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
22995#define ENET_IEEE_R_FRAME_OK_COUNT(x) \
22996 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
22997/*! @} */
22998
22999/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
23000/*! @{ */
23001#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
23002#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
23003#define ENET_IEEE_R_CRC_COUNT(x) \
23004 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
23005/*! @} */
23006
23007/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
23008/*! @{ */
23009#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
23010#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
23011#define ENET_IEEE_R_ALIGN_COUNT(x) \
23012 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
23013/*! @} */
23014
23015/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
23016/*! @{ */
23017#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
23018#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
23019#define ENET_IEEE_R_MACERR_COUNT(x) \
23020 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
23021/*! @} */
23022
23023/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
23024/*! @{ */
23025#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
23026#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
23027#define ENET_IEEE_R_FDXFC_COUNT(x) \
23028 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
23029/*! @} */
23030
23031/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
23032/*! @{ */
23033#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
23034#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
23035#define ENET_IEEE_R_OCTETS_OK_COUNT(x) \
23036 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
23037/*! @} */
23038
23039/*! @name ATCR - Adjustable Timer Control Register */
23040/*! @{ */
23041#define ENET_ATCR_EN_MASK (0x1U)
23042#define ENET_ATCR_EN_SHIFT (0U)
23043/*! EN - Enable Timer
23044 * 0b0..The timer stops at the current value.
23045 * 0b1..The timer starts incrementing.
23046 */
23047#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
23048#define ENET_ATCR_OFFEN_MASK (0x4U)
23049#define ENET_ATCR_OFFEN_SHIFT (2U)
23050/*! OFFEN - Enable One-Shot Offset Event
23051 * 0b0..Disable.
23052 * 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared
23053 * when the offset event is reached, so no further event occurs until the field is set again. The timer
23054 * offset value must be set before setting this field.
23055 */
23056#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
23057#define ENET_ATCR_OFFRST_MASK (0x8U)
23058#define ENET_ATCR_OFFRST_SHIFT (3U)
23059/*! OFFRST - Reset Timer On Offset Event
23060 * 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached.
23061 * 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a
23062 * timer interrupt.
23063 */
23064#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
23065#define ENET_ATCR_PEREN_MASK (0x10U)
23066#define ENET_ATCR_PEREN_SHIFT (4U)
23067/*! PEREN - Enable Periodical Event
23068 * 0b0..Disable.
23069 * 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when
23070 * the timer wraps around according to the periodic setting ATPER. The timer period value must be set before
23071 * setting this bit. Not all devices contain the event signal output. See the chip configuration details.
23072 */
23073#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
23074#define ENET_ATCR_PINPER_MASK (0x80U)
23075#define ENET_ATCR_PINPER_SHIFT (7U)
23076/*! PINPER
23077 * 0b0..Disable.
23078 * 0b1..Enable.
23079 */
23080#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
23081#define ENET_ATCR_RESTART_MASK (0x200U)
23082#define ENET_ATCR_RESTART_SHIFT (9U)
23083#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
23084#define ENET_ATCR_CAPTURE_MASK (0x800U)
23085#define ENET_ATCR_CAPTURE_SHIFT (11U)
23086/*! CAPTURE - Capture Timer Value
23087 * 0b0..No effect.
23088 * 0b1..The current time is captured and can be read from the ATVR register.
23089 */
23090#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
23091#define ENET_ATCR_SLAVE_MASK (0x2000U)
23092#define ENET_ATCR_SLAVE_SHIFT (13U)
23093/*! SLAVE - Enable Timer Slave Mode
23094 * 0b0..The timer is active and all configuration fields in this register are relevant.
23095 * 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except
23096 * CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
23097 */
23098#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
23099/*! @} */
23100
23101/*! @name ATVR - Timer Value Register */
23102/*! @{ */
23103#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
23104#define ENET_ATVR_ATIME_SHIFT (0U)
23105#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
23106/*! @} */
23107
23108/*! @name ATOFF - Timer Offset Register */
23109/*! @{ */
23110#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
23111#define ENET_ATOFF_OFFSET_SHIFT (0U)
23112#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
23113/*! @} */
23114
23115/*! @name ATPER - Timer Period Register */
23116/*! @{ */
23117#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
23118#define ENET_ATPER_PERIOD_SHIFT (0U)
23119#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
23120/*! @} */
23121
23122/*! @name ATCOR - Timer Correction Register */
23123/*! @{ */
23124#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
23125#define ENET_ATCOR_COR_SHIFT (0U)
23126#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
23127/*! @} */
23128
23129/*! @name ATINC - Time-Stamping Clock Period Register */
23130/*! @{ */
23131#define ENET_ATINC_INC_MASK (0x7FU)
23132#define ENET_ATINC_INC_SHIFT (0U)
23133#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
23134#define ENET_ATINC_INC_CORR_MASK (0x7F00U)
23135#define ENET_ATINC_INC_CORR_SHIFT (8U)
23136#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
23137/*! @} */
23138
23139/*! @name ATSTMP - Timestamp of Last Transmitted Frame */
23140/*! @{ */
23141#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
23142#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
23143#define ENET_ATSTMP_TIMESTAMP(x) \
23144 (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
23145/*! @} */
23146
23147/*! @name TGSR - Timer Global Status Register */
23148/*! @{ */
23149#define ENET_TGSR_TF0_MASK (0x1U)
23150#define ENET_TGSR_TF0_SHIFT (0U)
23151/*! TF0 - Copy Of Timer Flag For Channel 0
23152 * 0b0..Timer Flag for Channel 0 is clear
23153 * 0b1..Timer Flag for Channel 0 is set
23154 */
23155#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
23156#define ENET_TGSR_TF1_MASK (0x2U)
23157#define ENET_TGSR_TF1_SHIFT (1U)
23158/*! TF1 - Copy Of Timer Flag For Channel 1
23159 * 0b0..Timer Flag for Channel 1 is clear
23160 * 0b1..Timer Flag for Channel 1 is set
23161 */
23162#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
23163#define ENET_TGSR_TF2_MASK (0x4U)
23164#define ENET_TGSR_TF2_SHIFT (2U)
23165/*! TF2 - Copy Of Timer Flag For Channel 2
23166 * 0b0..Timer Flag for Channel 2 is clear
23167 * 0b1..Timer Flag for Channel 2 is set
23168 */
23169#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
23170#define ENET_TGSR_TF3_MASK (0x8U)
23171#define ENET_TGSR_TF3_SHIFT (3U)
23172/*! TF3 - Copy Of Timer Flag For Channel 3
23173 * 0b0..Timer Flag for Channel 3 is clear
23174 * 0b1..Timer Flag for Channel 3 is set
23175 */
23176#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
23177/*! @} */
23178
23179/*! @name TCSR - Timer Control Status Register */
23180/*! @{ */
23181#define ENET_TCSR_TDRE_MASK (0x1U)
23182#define ENET_TCSR_TDRE_SHIFT (0U)
23183/*! TDRE - Timer DMA Request Enable
23184 * 0b0..DMA request is disabled
23185 * 0b1..DMA request is enabled
23186 */
23187#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
23188#define ENET_TCSR_TMODE_MASK (0x3CU)
23189#define ENET_TCSR_TMODE_SHIFT (2U)
23190/*! TMODE - Timer Mode
23191 * 0b0000..Timer Channel is disabled.
23192 * 0b0001..Timer Channel is configured for Input Capture on rising edge.
23193 * 0b0010..Timer Channel is configured for Input Capture on falling edge.
23194 * 0b0011..Timer Channel is configured for Input Capture on both edges.
23195 * 0b0100..Timer Channel is configured for Output Compare - software only.
23196 * 0b0101..Timer Channel is configured for Output Compare - toggle output on compare.
23197 * 0b0110..Timer Channel is configured for Output Compare - clear output on compare.
23198 * 0b0111..Timer Channel is configured for Output Compare - set output on compare.
23199 * 0b1000..Reserved
23200 * 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
23201 * 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
23202 * 0b110x..Reserved
23203 * 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for one 1588-clock cycle.
23204 * 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for one 1588-clock cycle.
23205 */
23206#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
23207#define ENET_TCSR_TIE_MASK (0x40U)
23208#define ENET_TCSR_TIE_SHIFT (6U)
23209/*! TIE - Timer Interrupt Enable
23210 * 0b0..Interrupt is disabled
23211 * 0b1..Interrupt is enabled
23212 */
23213#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
23214#define ENET_TCSR_TF_MASK (0x80U)
23215#define ENET_TCSR_TF_SHIFT (7U)
23216/*! TF - Timer Flag
23217 * 0b0..Input Capture or Output Compare has not occurred.
23218 * 0b1..Input Capture or Output Compare has occurred.
23219 */
23220#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
23221/*! @} */
23222
23223/* The count of ENET_TCSR */
23224#define ENET_TCSR_COUNT (4U)
23225
23226/*! @name TCCR - Timer Compare Capture Register */
23227/*! @{ */
23228#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
23229#define ENET_TCCR_TCC_SHIFT (0U)
23230#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
23231/*! @} */
23232
23233/* The count of ENET_TCCR */
23234#define ENET_TCCR_COUNT (4U)
23235
23236/*!
23237 * @}
23238 */ /* end of group ENET_Register_Masks */
23239
23240/* ENET - Peripheral instance base addresses */
23241/** Peripheral ENET base address */
23242#define ENET_BASE (0x30BE0000u)
23243/** Peripheral ENET base pointer */
23244#define ENET ((ENET_Type *)ENET_BASE)
23245/** Array initializer of ENET peripheral base addresses */
23246#define ENET_BASE_ADDRS \
23247 { \
23248 ENET_BASE \
23249 }
23250/** Array initializer of ENET peripheral base pointers */
23251#define ENET_BASE_PTRS \
23252 { \
23253 ENET \
23254 }
23255/** Interrupt vectors for the ENET peripheral type */
23256#define ENET_Transmit_IRQS \
23257 { \
23258 ENET_IRQn \
23259 }
23260#define ENET_Receive_IRQS \
23261 { \
23262 ENET_IRQn \
23263 }
23264#define ENET_Error_IRQS \
23265 { \
23266 ENET_IRQn \
23267 }
23268#define ENET_1588_Timer_IRQS \
23269 { \
23270 ENET_IRQn \
23271 }
23272/* ENET Buffer Descriptor and Buffer Address Alignment. */
23273#define ENET_BUFF_ALIGNMENT (64U)
23274
23275/*!
23276 * @}
23277 */ /* end of group ENET_Peripheral_Access_Layer */
23278
23279/* ----------------------------------------------------------------------------
23280 -- FlexSPI Peripheral Access Layer
23281 ---------------------------------------------------------------------------- */
23282
23283/*!
23284 * @addtogroup FlexSPI_Peripheral_Access_Layer FlexSPI Peripheral Access Layer
23285 * @{
23286 */
23287
23288/** FlexSPI - Register Layout Typedef */
23289typedef struct
23290{
23291 __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */
23292 __IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */
23293 __IO uint32_t MCR2; /**< Module Control Register 2, offset: 0x8 */
23294 __IO uint32_t AHBCR; /**< AHB Bus Control Register, offset: 0xC */
23295 __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x10 */
23296 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */
23297 __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */
23298 __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */
23299 __IO uint32_t AHBRXBUFCR0[8]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array
23300 offset: 0x20, array step: 0x4 */
23301 uint8_t RESERVED_0[32];
23302 __IO uint32_t FLSHCR0[4]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */
23303 __IO uint32_t FLSHCR1[4]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */
23304 __IO uint32_t FLSHCR2[4]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */
23305 uint8_t RESERVED_1[4];
23306 __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */
23307 uint8_t RESERVED_2[8];
23308 __IO uint32_t IPCR0; /**< IP Control Register 0, offset: 0xA0 */
23309 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */
23310 uint8_t RESERVED_3[8];
23311 __IO uint32_t IPCMD; /**< IP Command Register, offset: 0xB0 */
23312 __IO uint32_t DLPR; /**< Data Learn Pattern Register, offset: 0xB4 */
23313 __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */
23314 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */
23315 __IO uint32_t DLLCR[2]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */
23316 uint8_t RESERVED_4[24];
23317 __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */
23318 __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */
23319 __I uint32_t STS2; /**< Status Register 2, offset: 0xE8 */
23320 __I uint32_t AHBSPNDSTS; /**< AHB Suspend Status Register, offset: 0xEC */
23321 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */
23322 __I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */
23323 uint8_t RESERVED_5[8];
23324 __I uint32_t
23325 RFDR[32]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */
23326 __O uint32_t
23327 TFDR[32]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */
23328 __IO uint32_t LUT[128]; /**< LUT 0..LUT 127, array offset: 0x200, array step: 0x4 */
23329} FlexSPI_Type;
23330
23331/* ----------------------------------------------------------------------------
23332 -- FlexSPI Register Masks
23333 ---------------------------------------------------------------------------- */
23334
23335/*!
23336 * @addtogroup FlexSPI_Register_Masks FlexSPI Register Masks
23337 * @{
23338 */
23339
23340/*! @name MCR0 - Module Control Register 0 */
23341/*! @{ */
23342#define FlexSPI_MCR0_SWRESET_MASK (0x1U)
23343#define FlexSPI_MCR0_SWRESET_SHIFT (0U)
23344#define FlexSPI_MCR0_SWRESET(x) \
23345 (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_SWRESET_SHIFT)) & FlexSPI_MCR0_SWRESET_MASK)
23346#define FlexSPI_MCR0_MDIS_MASK (0x2U)
23347#define FlexSPI_MCR0_MDIS_SHIFT (1U)
23348#define FlexSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_MDIS_SHIFT)) & FlexSPI_MCR0_MDIS_MASK)
23349#define FlexSPI_MCR0_RXCLKSRC_MASK (0x30U)
23350#define FlexSPI_MCR0_RXCLKSRC_SHIFT (4U)
23351/*! RXCLKSRC - Sample Clock source selection for Flash Reading
23352 * 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally.
23353 * 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
23354 * 0b10..Reserved
23355 * 0b11..Flash provided Read strobe and input from DQS pad
23356 */
23357#define FlexSPI_MCR0_RXCLKSRC(x) \
23358 (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_RXCLKSRC_SHIFT)) & FlexSPI_MCR0_RXCLKSRC_MASK)
23359#define FlexSPI_MCR0_ARDFEN_MASK (0x40U)
23360#define FlexSPI_MCR0_ARDFEN_SHIFT (6U)
23361/*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO.
23362 * 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error
23363 * response. 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return
23364 * data zero but no bus error response.
23365 */
23366#define FlexSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_ARDFEN_SHIFT)) & FlexSPI_MCR0_ARDFEN_MASK)
23367#define FlexSPI_MCR0_ATDFEN_MASK (0x80U)
23368#define FlexSPI_MCR0_ATDFEN_SHIFT (7U)
23369/*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO.
23370 * 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error
23371 * response. 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be
23372 * ignored but no bus error response.
23373 */
23374#define FlexSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_ATDFEN_SHIFT)) & FlexSPI_MCR0_ATDFEN_MASK)
23375#define FlexSPI_MCR0_SERCLKDIV_MASK (0x700U)
23376#define FlexSPI_MCR0_SERCLKDIV_SHIFT (8U)
23377/*! SERCLKDIV - The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on
23378 * clocking. 0b000..Divided by 1 0b001..Divided by 2 0b010..Divided by 3 0b011..Divided by 4 0b100..Divided by 5
23379 * 0b101..Divided by 6
23380 * 0b110..Divided by 7
23381 * 0b111..Divided by 8
23382 */
23383#define FlexSPI_MCR0_SERCLKDIV(x) \
23384 (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_SERCLKDIV_SHIFT)) & FlexSPI_MCR0_SERCLKDIV_MASK)
23385#define FlexSPI_MCR0_HSEN_MASK (0x800U)
23386#define FlexSPI_MCR0_HSEN_SHIFT (11U)
23387/*! HSEN - Half Speed Serial Flash access Enable.
23388 * 0b0..Disable divide by 2 of serial flash clock for half speed commands.
23389 * 0b1..Enable divide by 2 of serial flash clock for half speed commands.
23390 */
23391#define FlexSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_HSEN_SHIFT)) & FlexSPI_MCR0_HSEN_MASK)
23392#define FlexSPI_MCR0_DOZEEN_MASK (0x1000U)
23393#define FlexSPI_MCR0_DOZEEN_SHIFT (12U)
23394/*! DOZEEN - Doze mode enable bit
23395 * 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request
23396 * from system. 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode
23397 * request from system.
23398 */
23399#define FlexSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_DOZEEN_SHIFT)) & FlexSPI_MCR0_DOZEEN_MASK)
23400#define FlexSPI_MCR0_COMBINATIONEN_MASK (0x2000U)
23401#define FlexSPI_MCR0_COMBINATIONEN_SHIFT (13U)
23402/*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and
23403 * B_DATA[3:0]). 0b0..Disable. 0b1..Enable.
23404 */
23405#define FlexSPI_MCR0_COMBINATIONEN(x) \
23406 (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_COMBINATIONEN_SHIFT)) & FlexSPI_MCR0_COMBINATIONEN_MASK)
23407#define FlexSPI_MCR0_SCKFREERUNEN_MASK (0x4000U)
23408#define FlexSPI_MCR0_SCKFREERUNEN_SHIFT (14U)
23409/*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications,
23410 * external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is
23411 * enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2).
23412 * 0b0..Disable.
23413 * 0b1..Enable.
23414 */
23415#define FlexSPI_MCR0_SCKFREERUNEN(x) \
23416 (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_SCKFREERUNEN_SHIFT)) & FlexSPI_MCR0_SCKFREERUNEN_MASK)
23417#define FlexSPI_MCR0_LEARNEN_MASK (0x8000U)
23418#define FlexSPI_MCR0_LEARNEN_SHIFT (15U)
23419/*! LEARNEN - This bit is used to enable/disable data learning feature. When data learning is
23420 * disabled, the sampling clock phase 0 is always used for RX data sampling even if LEARN instruction
23421 * is correctly executed.
23422 * 0b0..Disable.
23423 * 0b1..Enable.
23424 */
23425#define FlexSPI_MCR0_LEARNEN(x) \
23426 (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_LEARNEN_SHIFT)) & FlexSPI_MCR0_LEARNEN_MASK)
23427#define FlexSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U)
23428#define FlexSPI_MCR0_IPGRANTWAIT_SHIFT (16U)
23429#define FlexSPI_MCR0_IPGRANTWAIT(x) \
23430 (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_IPGRANTWAIT_SHIFT)) & FlexSPI_MCR0_IPGRANTWAIT_MASK)
23431#define FlexSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U)
23432#define FlexSPI_MCR0_AHBGRANTWAIT_SHIFT (24U)
23433#define FlexSPI_MCR0_AHBGRANTWAIT(x) \
23434 (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FlexSPI_MCR0_AHBGRANTWAIT_MASK)
23435/*! @} */
23436
23437/*! @name MCR1 - Module Control Register 1 */
23438/*! @{ */
23439#define FlexSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU)
23440#define FlexSPI_MCR1_AHBBUSWAIT_SHIFT (0U)
23441#define FlexSPI_MCR1_AHBBUSWAIT(x) \
23442 (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR1_AHBBUSWAIT_SHIFT)) & FlexSPI_MCR1_AHBBUSWAIT_MASK)
23443#define FlexSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U)
23444#define FlexSPI_MCR1_SEQWAIT_SHIFT (16U)
23445#define FlexSPI_MCR1_SEQWAIT(x) \
23446 (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR1_SEQWAIT_SHIFT)) & FlexSPI_MCR1_SEQWAIT_MASK)
23447/*! @} */
23448
23449/*! @name MCR2 - Module Control Register 2 */
23450/*! @{ */
23451#define FlexSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U)
23452#define FlexSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U)
23453/*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned
23454 * automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or
23455 * AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP
23456 * mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.
23457 * 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.
23458 * 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
23459 */
23460#define FlexSPI_MCR2_CLRAHBBUFOPT(x) \
23461 (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FlexSPI_MCR2_CLRAHBBUFOPT_MASK)
23462#define FlexSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U)
23463#define FlexSPI_MCR2_CLRLEARNPHASE_SHIFT (14U)
23464#define FlexSPI_MCR2_CLRLEARNPHASE(x) \
23465 (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FlexSPI_MCR2_CLRLEARNPHASE_MASK)
23466#define FlexSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U)
23467#define FlexSPI_MCR2_SAMEDEVICEEN_SHIFT (15U)
23468/*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2.
23469 * 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash
23470 * A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1,
23471 * FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be
23472 * ignored.
23473 * 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2.
23474 * FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
23475 */
23476#define FlexSPI_MCR2_SAMEDEVICEEN(x) \
23477 (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FlexSPI_MCR2_SAMEDEVICEEN_MASK)
23478#define FlexSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U)
23479#define FlexSPI_MCR2_SCKBDIFFOPT_SHIFT (19U)
23480/*! SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to
23481 * A_SCLK). In this case, port B flash access is not available. After changing the value of this
23482 * field, MCR0[SWRESET] should be set.
23483 * 0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is
23484 * not available. 0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available.
23485 */
23486#define FlexSPI_MCR2_SCKBDIFFOPT(x) \
23487 (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FlexSPI_MCR2_SCKBDIFFOPT_MASK)
23488#define FlexSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U)
23489#define FlexSPI_MCR2_RESUMEWAIT_SHIFT (24U)
23490#define FlexSPI_MCR2_RESUMEWAIT(x) \
23491 (((uint32_t)(((uint32_t)(x)) << FlexSPI_MCR2_RESUMEWAIT_SHIFT)) & FlexSPI_MCR2_RESUMEWAIT_MASK)
23492/*! @} */
23493
23494/*! @name AHBCR - AHB Bus Control Register */
23495/*! @{ */
23496#define FlexSPI_AHBCR_APAREN_MASK (0x1U)
23497#define FlexSPI_AHBCR_APAREN_SHIFT (0U)
23498/*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) .
23499 * 0b0..Flash will be accessed in Individual mode.
23500 * 0b1..Flash will be accessed in Parallel mode.
23501 */
23502#define FlexSPI_AHBCR_APAREN(x) \
23503 (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBCR_APAREN_SHIFT)) & FlexSPI_AHBCR_APAREN_MASK)
23504#define FlexSPI_AHBCR_CACHABLEEN_MASK (0x8U)
23505#define FlexSPI_AHBCR_CACHABLEEN_SHIFT (3U)
23506/*! CACHABLEEN - Enable AHB bus cachable read access support.
23507 * 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.
23508 * 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
23509 */
23510#define FlexSPI_AHBCR_CACHABLEEN(x) \
23511 (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBCR_CACHABLEEN_SHIFT)) & FlexSPI_AHBCR_CACHABLEEN_MASK)
23512#define FlexSPI_AHBCR_BUFFERABLEEN_MASK (0x10U)
23513#define FlexSPI_AHBCR_BUFFERABLEEN_SHIFT (4U)
23514/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat
23515 * of AHB write access, refer for more details about AHB bufferable write.
23516 * 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus
23517 * ready after all data is transmitted to External device and AHB command finished.
23518 * 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is
23519 * granted by arbitrator and will not wait for AHB command finished.
23520 */
23521#define FlexSPI_AHBCR_BUFFERABLEEN(x) \
23522 (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FlexSPI_AHBCR_BUFFERABLEEN_MASK)
23523#define FlexSPI_AHBCR_PREFETCHEN_MASK (0x20U)
23524#define FlexSPI_AHBCR_PREFETCHEN_SHIFT (5U)
23525#define FlexSPI_AHBCR_PREFETCHEN(x) \
23526 (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBCR_PREFETCHEN_SHIFT)) & FlexSPI_AHBCR_PREFETCHEN_MASK)
23527#define FlexSPI_AHBCR_READADDROPT_MASK (0x40U)
23528#define FlexSPI_AHBCR_READADDROPT_SHIFT (6U)
23529/*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment
23530 * limitation. 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode
23531 * or flash is wordaddressable. 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch
23532 * more data than AHB burst required to meet the alignment requirement.
23533 */
23534#define FlexSPI_AHBCR_READADDROPT(x) \
23535 (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBCR_READADDROPT_SHIFT)) & FlexSPI_AHBCR_READADDROPT_MASK)
23536/*! @} */
23537
23538/*! @name INTEN - Interrupt Enable Register */
23539/*! @{ */
23540#define FlexSPI_INTEN_IPCMDDONEEN_MASK (0x1U)
23541#define FlexSPI_INTEN_IPCMDDONEEN_SHIFT (0U)
23542#define FlexSPI_INTEN_IPCMDDONEEN(x) \
23543 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_IPCMDDONEEN_SHIFT)) & FlexSPI_INTEN_IPCMDDONEEN_MASK)
23544#define FlexSPI_INTEN_IPCMDGEEN_MASK (0x2U)
23545#define FlexSPI_INTEN_IPCMDGEEN_SHIFT (1U)
23546#define FlexSPI_INTEN_IPCMDGEEN(x) \
23547 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_IPCMDGEEN_SHIFT)) & FlexSPI_INTEN_IPCMDGEEN_MASK)
23548#define FlexSPI_INTEN_AHBCMDGEEN_MASK (0x4U)
23549#define FlexSPI_INTEN_AHBCMDGEEN_SHIFT (2U)
23550#define FlexSPI_INTEN_AHBCMDGEEN(x) \
23551 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_AHBCMDGEEN_SHIFT)) & FlexSPI_INTEN_AHBCMDGEEN_MASK)
23552#define FlexSPI_INTEN_IPCMDERREN_MASK (0x8U)
23553#define FlexSPI_INTEN_IPCMDERREN_SHIFT (3U)
23554#define FlexSPI_INTEN_IPCMDERREN(x) \
23555 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_IPCMDERREN_SHIFT)) & FlexSPI_INTEN_IPCMDERREN_MASK)
23556#define FlexSPI_INTEN_AHBCMDERREN_MASK (0x10U)
23557#define FlexSPI_INTEN_AHBCMDERREN_SHIFT (4U)
23558#define FlexSPI_INTEN_AHBCMDERREN(x) \
23559 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_AHBCMDERREN_SHIFT)) & FlexSPI_INTEN_AHBCMDERREN_MASK)
23560#define FlexSPI_INTEN_IPRXWAEN_MASK (0x20U)
23561#define FlexSPI_INTEN_IPRXWAEN_SHIFT (5U)
23562#define FlexSPI_INTEN_IPRXWAEN(x) \
23563 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_IPRXWAEN_SHIFT)) & FlexSPI_INTEN_IPRXWAEN_MASK)
23564#define FlexSPI_INTEN_IPTXWEEN_MASK (0x40U)
23565#define FlexSPI_INTEN_IPTXWEEN_SHIFT (6U)
23566#define FlexSPI_INTEN_IPTXWEEN(x) \
23567 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_IPTXWEEN_SHIFT)) & FlexSPI_INTEN_IPTXWEEN_MASK)
23568#define FlexSPI_INTEN_DATALEARNFAILEN_MASK (0x80U)
23569#define FlexSPI_INTEN_DATALEARNFAILEN_SHIFT (7U)
23570#define FlexSPI_INTEN_DATALEARNFAILEN(x) \
23571 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FlexSPI_INTEN_DATALEARNFAILEN_MASK)
23572#define FlexSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U)
23573#define FlexSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U)
23574#define FlexSPI_INTEN_SCKSTOPBYRDEN(x) \
23575 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FlexSPI_INTEN_SCKSTOPBYRDEN_MASK)
23576#define FlexSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U)
23577#define FlexSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U)
23578#define FlexSPI_INTEN_SCKSTOPBYWREN(x) \
23579 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FlexSPI_INTEN_SCKSTOPBYWREN_MASK)
23580#define FlexSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U)
23581#define FlexSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U)
23582#define FlexSPI_INTEN_AHBBUSTIMEOUTEN(x) \
23583 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FlexSPI_INTEN_AHBBUSTIMEOUTEN_MASK)
23584#define FlexSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U)
23585#define FlexSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U)
23586#define FlexSPI_INTEN_SEQTIMEOUTEN(x) \
23587 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FlexSPI_INTEN_SEQTIMEOUTEN_MASK)
23588/*! @} */
23589
23590/*! @name INTR - Interrupt Register */
23591/*! @{ */
23592#define FlexSPI_INTR_IPCMDDONE_MASK (0x1U)
23593#define FlexSPI_INTR_IPCMDDONE_SHIFT (0U)
23594#define FlexSPI_INTR_IPCMDDONE(x) \
23595 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_IPCMDDONE_SHIFT)) & FlexSPI_INTR_IPCMDDONE_MASK)
23596#define FlexSPI_INTR_IPCMDGE_MASK (0x2U)
23597#define FlexSPI_INTR_IPCMDGE_SHIFT (1U)
23598#define FlexSPI_INTR_IPCMDGE(x) \
23599 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_IPCMDGE_SHIFT)) & FlexSPI_INTR_IPCMDGE_MASK)
23600#define FlexSPI_INTR_AHBCMDGE_MASK (0x4U)
23601#define FlexSPI_INTR_AHBCMDGE_SHIFT (2U)
23602#define FlexSPI_INTR_AHBCMDGE(x) \
23603 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_AHBCMDGE_SHIFT)) & FlexSPI_INTR_AHBCMDGE_MASK)
23604#define FlexSPI_INTR_IPCMDERR_MASK (0x8U)
23605#define FlexSPI_INTR_IPCMDERR_SHIFT (3U)
23606#define FlexSPI_INTR_IPCMDERR(x) \
23607 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_IPCMDERR_SHIFT)) & FlexSPI_INTR_IPCMDERR_MASK)
23608#define FlexSPI_INTR_AHBCMDERR_MASK (0x10U)
23609#define FlexSPI_INTR_AHBCMDERR_SHIFT (4U)
23610#define FlexSPI_INTR_AHBCMDERR(x) \
23611 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_AHBCMDERR_SHIFT)) & FlexSPI_INTR_AHBCMDERR_MASK)
23612#define FlexSPI_INTR_IPRXWA_MASK (0x20U)
23613#define FlexSPI_INTR_IPRXWA_SHIFT (5U)
23614#define FlexSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_IPRXWA_SHIFT)) & FlexSPI_INTR_IPRXWA_MASK)
23615#define FlexSPI_INTR_IPTXWE_MASK (0x40U)
23616#define FlexSPI_INTR_IPTXWE_SHIFT (6U)
23617#define FlexSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_IPTXWE_SHIFT)) & FlexSPI_INTR_IPTXWE_MASK)
23618#define FlexSPI_INTR_DATALEARNFAIL_MASK (0x80U)
23619#define FlexSPI_INTR_DATALEARNFAIL_SHIFT (7U)
23620#define FlexSPI_INTR_DATALEARNFAIL(x) \
23621 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_DATALEARNFAIL_SHIFT)) & FlexSPI_INTR_DATALEARNFAIL_MASK)
23622#define FlexSPI_INTR_SCKSTOPBYRD_MASK (0x100U)
23623#define FlexSPI_INTR_SCKSTOPBYRD_SHIFT (8U)
23624#define FlexSPI_INTR_SCKSTOPBYRD(x) \
23625 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_SCKSTOPBYRD_SHIFT)) & FlexSPI_INTR_SCKSTOPBYRD_MASK)
23626#define FlexSPI_INTR_SCKSTOPBYWR_MASK (0x200U)
23627#define FlexSPI_INTR_SCKSTOPBYWR_SHIFT (9U)
23628#define FlexSPI_INTR_SCKSTOPBYWR(x) \
23629 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_SCKSTOPBYWR_SHIFT)) & FlexSPI_INTR_SCKSTOPBYWR_MASK)
23630#define FlexSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U)
23631#define FlexSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U)
23632#define FlexSPI_INTR_AHBBUSTIMEOUT(x) \
23633 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FlexSPI_INTR_AHBBUSTIMEOUT_MASK)
23634#define FlexSPI_INTR_SEQTIMEOUT_MASK (0x800U)
23635#define FlexSPI_INTR_SEQTIMEOUT_SHIFT (11U)
23636#define FlexSPI_INTR_SEQTIMEOUT(x) \
23637 (((uint32_t)(((uint32_t)(x)) << FlexSPI_INTR_SEQTIMEOUT_SHIFT)) & FlexSPI_INTR_SEQTIMEOUT_MASK)
23638/*! @} */
23639
23640/*! @name LUTKEY - LUT Key Register */
23641/*! @{ */
23642#define FlexSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)
23643#define FlexSPI_LUTKEY_KEY_SHIFT (0U)
23644#define FlexSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUTKEY_KEY_SHIFT)) & FlexSPI_LUTKEY_KEY_MASK)
23645/*! @} */
23646
23647/*! @name LUTCR - LUT Control Register */
23648/*! @{ */
23649#define FlexSPI_LUTCR_LOCK_MASK (0x1U)
23650#define FlexSPI_LUTCR_LOCK_SHIFT (0U)
23651#define FlexSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUTCR_LOCK_SHIFT)) & FlexSPI_LUTCR_LOCK_MASK)
23652#define FlexSPI_LUTCR_UNLOCK_MASK (0x2U)
23653#define FlexSPI_LUTCR_UNLOCK_SHIFT (1U)
23654#define FlexSPI_LUTCR_UNLOCK(x) \
23655 (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUTCR_UNLOCK_SHIFT)) & FlexSPI_LUTCR_UNLOCK_MASK)
23656/*! @} */
23657
23658/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */
23659/*! @{ */
23660#define FlexSPI_AHBRXBUFCR0_BUFSZ_MASK (0x1FFU)
23661#define FlexSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U)
23662#define FlexSPI_AHBRXBUFCR0_BUFSZ(x) \
23663 (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FlexSPI_AHBRXBUFCR0_BUFSZ_MASK)
23664#define FlexSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U)
23665#define FlexSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U)
23666#define FlexSPI_AHBRXBUFCR0_MSTRID(x) \
23667 (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FlexSPI_AHBRXBUFCR0_MSTRID_MASK)
23668#define FlexSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U)
23669#define FlexSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U)
23670#define FlexSPI_AHBRXBUFCR0_PRIORITY(x) \
23671 (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FlexSPI_AHBRXBUFCR0_PRIORITY_MASK)
23672#define FlexSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U)
23673#define FlexSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U)
23674#define FlexSPI_AHBRXBUFCR0_PREFETCHEN(x) \
23675 (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FlexSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
23676/*! @} */
23677
23678/* The count of FlexSPI_AHBRXBUFCR0 */
23679#define FlexSPI_AHBRXBUFCR0_COUNT (8U)
23680
23681/*! @name FLSHCR0 - Flash Control Register 0 */
23682/*! @{ */
23683#define FlexSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU)
23684#define FlexSPI_FLSHCR0_FLSHSZ_SHIFT (0U)
23685#define FlexSPI_FLSHCR0_FLSHSZ(x) \
23686 (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR0_FLSHSZ_SHIFT)) & FlexSPI_FLSHCR0_FLSHSZ_MASK)
23687/*! @} */
23688
23689/* The count of FlexSPI_FLSHCR0 */
23690#define FlexSPI_FLSHCR0_COUNT (4U)
23691
23692/*! @name FLSHCR1 - Flash Control Register 1 */
23693/*! @{ */
23694#define FlexSPI_FLSHCR1_TCSS_MASK (0x1FU)
23695#define FlexSPI_FLSHCR1_TCSS_SHIFT (0U)
23696#define FlexSPI_FLSHCR1_TCSS(x) \
23697 (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_TCSS_SHIFT)) & FlexSPI_FLSHCR1_TCSS_MASK)
23698#define FlexSPI_FLSHCR1_TCSH_MASK (0x3E0U)
23699#define FlexSPI_FLSHCR1_TCSH_SHIFT (5U)
23700#define FlexSPI_FLSHCR1_TCSH(x) \
23701 (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_TCSH_SHIFT)) & FlexSPI_FLSHCR1_TCSH_MASK)
23702#define FlexSPI_FLSHCR1_WA_MASK (0x400U)
23703#define FlexSPI_FLSHCR1_WA_SHIFT (10U)
23704#define FlexSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_WA_SHIFT)) & FlexSPI_FLSHCR1_WA_MASK)
23705#define FlexSPI_FLSHCR1_CAS_MASK (0x7800U)
23706#define FlexSPI_FLSHCR1_CAS_SHIFT (11U)
23707#define FlexSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_CAS_SHIFT)) & FlexSPI_FLSHCR1_CAS_MASK)
23708#define FlexSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U)
23709#define FlexSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U)
23710/*! CSINTERVALUNIT - CS interval unit
23711 * 0b0..The CS interval unit is 1 serial clock cycle
23712 * 0b1..The CS interval unit is 256 serial clock cycle
23713 */
23714#define FlexSPI_FLSHCR1_CSINTERVALUNIT(x) \
23715 (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FlexSPI_FLSHCR1_CSINTERVALUNIT_MASK)
23716#define FlexSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U)
23717#define FlexSPI_FLSHCR1_CSINTERVAL_SHIFT (16U)
23718#define FlexSPI_FLSHCR1_CSINTERVAL(x) \
23719 (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FlexSPI_FLSHCR1_CSINTERVAL_MASK)
23720/*! @} */
23721
23722/* The count of FlexSPI_FLSHCR1 */
23723#define FlexSPI_FLSHCR1_COUNT (4U)
23724
23725/*! @name FLSHCR2 - Flash Control Register 2 */
23726/*! @{ */
23727#define FlexSPI_FLSHCR2_ARDSEQID_MASK (0x1FU)
23728#define FlexSPI_FLSHCR2_ARDSEQID_SHIFT (0U)
23729#define FlexSPI_FLSHCR2_ARDSEQID(x) \
23730 (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_ARDSEQID_SHIFT)) & FlexSPI_FLSHCR2_ARDSEQID_MASK)
23731#define FlexSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U)
23732#define FlexSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U)
23733#define FlexSPI_FLSHCR2_ARDSEQNUM(x) \
23734 (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FlexSPI_FLSHCR2_ARDSEQNUM_MASK)
23735#define FlexSPI_FLSHCR2_AWRSEQID_MASK (0x1F00U)
23736#define FlexSPI_FLSHCR2_AWRSEQID_SHIFT (8U)
23737#define FlexSPI_FLSHCR2_AWRSEQID(x) \
23738 (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_AWRSEQID_SHIFT)) & FlexSPI_FLSHCR2_AWRSEQID_MASK)
23739#define FlexSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U)
23740#define FlexSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U)
23741#define FlexSPI_FLSHCR2_AWRSEQNUM(x) \
23742 (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FlexSPI_FLSHCR2_AWRSEQNUM_MASK)
23743#define FlexSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U)
23744#define FlexSPI_FLSHCR2_AWRWAIT_SHIFT (16U)
23745#define FlexSPI_FLSHCR2_AWRWAIT(x) \
23746 (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_AWRWAIT_SHIFT)) & FlexSPI_FLSHCR2_AWRWAIT_MASK)
23747#define FlexSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U)
23748#define FlexSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U)
23749/*! AWRWAITUNIT - AWRWAIT unit
23750 * 0b000..The AWRWAIT unit is 2 ahb clock cycle
23751 * 0b001..The AWRWAIT unit is 8 ahb clock cycle
23752 * 0b010..The AWRWAIT unit is 32 ahb clock cycle
23753 * 0b011..The AWRWAIT unit is 128 ahb clock cycle
23754 * 0b100..The AWRWAIT unit is 512 ahb clock cycle
23755 * 0b101..The AWRWAIT unit is 2048 ahb clock cycle
23756 * 0b110..The AWRWAIT unit is 8192 ahb clock cycle
23757 * 0b111..The AWRWAIT unit is 32768 ahb clock cycle
23758 */
23759#define FlexSPI_FLSHCR2_AWRWAITUNIT(x) \
23760 (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FlexSPI_FLSHCR2_AWRWAITUNIT_MASK)
23761#define FlexSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U)
23762#define FlexSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U)
23763#define FlexSPI_FLSHCR2_CLRINSTRPTR(x) \
23764 (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FlexSPI_FLSHCR2_CLRINSTRPTR_MASK)
23765/*! @} */
23766
23767/* The count of FlexSPI_FLSHCR2 */
23768#define FlexSPI_FLSHCR2_COUNT (4U)
23769
23770/*! @name FLSHCR4 - Flash Control Register 4 */
23771/*! @{ */
23772#define FlexSPI_FLSHCR4_WMOPT1_MASK (0x1U)
23773#define FlexSPI_FLSHCR4_WMOPT1_SHIFT (0U)
23774/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment
23775 * limitation. 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB
23776 * write burst start address alignment when flash is accessed in individual mode. 0b1..DQS pin will not be used as Write
23777 * Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is
23778 * accessed in individual mode.
23779 */
23780#define FlexSPI_FLSHCR4_WMOPT1(x) \
23781 (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR4_WMOPT1_SHIFT)) & FlexSPI_FLSHCR4_WMOPT1_MASK)
23782#define FlexSPI_FLSHCR4_WMENA_MASK (0x4U)
23783#define FlexSPI_FLSHCR4_WMENA_SHIFT (2U)
23784/*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for
23785 * memory device on port A, this bit must be set.
23786 * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
23787 * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external
23788 * device.
23789 */
23790#define FlexSPI_FLSHCR4_WMENA(x) \
23791 (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR4_WMENA_SHIFT)) & FlexSPI_FLSHCR4_WMENA_MASK)
23792#define FlexSPI_FLSHCR4_WMENB_MASK (0x8U)
23793#define FlexSPI_FLSHCR4_WMENB_SHIFT (3U)
23794/*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for
23795 * memory device on port B, this bit must be set.
23796 * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
23797 * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external
23798 * device.
23799 */
23800#define FlexSPI_FLSHCR4_WMENB(x) \
23801 (((uint32_t)(((uint32_t)(x)) << FlexSPI_FLSHCR4_WMENB_SHIFT)) & FlexSPI_FLSHCR4_WMENB_MASK)
23802/*! @} */
23803
23804/*! @name IPCR0 - IP Control Register 0 */
23805/*! @{ */
23806#define FlexSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU)
23807#define FlexSPI_IPCR0_SFAR_SHIFT (0U)
23808#define FlexSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCR0_SFAR_SHIFT)) & FlexSPI_IPCR0_SFAR_MASK)
23809/*! @} */
23810
23811/*! @name IPCR1 - IP Control Register 1 */
23812/*! @{ */
23813#define FlexSPI_IPCR1_IDATSZ_MASK (0xFFFFU)
23814#define FlexSPI_IPCR1_IDATSZ_SHIFT (0U)
23815#define FlexSPI_IPCR1_IDATSZ(x) \
23816 (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCR1_IDATSZ_SHIFT)) & FlexSPI_IPCR1_IDATSZ_MASK)
23817#define FlexSPI_IPCR1_ISEQID_MASK (0x1F0000U)
23818#define FlexSPI_IPCR1_ISEQID_SHIFT (16U)
23819#define FlexSPI_IPCR1_ISEQID(x) \
23820 (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCR1_ISEQID_SHIFT)) & FlexSPI_IPCR1_ISEQID_MASK)
23821#define FlexSPI_IPCR1_ISEQNUM_MASK (0x7000000U)
23822#define FlexSPI_IPCR1_ISEQNUM_SHIFT (24U)
23823#define FlexSPI_IPCR1_ISEQNUM(x) \
23824 (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCR1_ISEQNUM_SHIFT)) & FlexSPI_IPCR1_ISEQNUM_MASK)
23825#define FlexSPI_IPCR1_IPAREN_MASK (0x80000000U)
23826#define FlexSPI_IPCR1_IPAREN_SHIFT (31U)
23827/*! IPAREN - Parallel mode Enabled for IP command.
23828 * 0b0..Flash will be accessed in Individual mode.
23829 * 0b1..Flash will be accessed in Parallel mode.
23830 */
23831#define FlexSPI_IPCR1_IPAREN(x) \
23832 (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCR1_IPAREN_SHIFT)) & FlexSPI_IPCR1_IPAREN_MASK)
23833/*! @} */
23834
23835/*! @name IPCMD - IP Command Register */
23836/*! @{ */
23837#define FlexSPI_IPCMD_TRG_MASK (0x1U)
23838#define FlexSPI_IPCMD_TRG_SHIFT (0U)
23839#define FlexSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPCMD_TRG_SHIFT)) & FlexSPI_IPCMD_TRG_MASK)
23840/*! @} */
23841
23842/*! @name DLPR - Data Learn Pattern Register */
23843/*! @{ */
23844#define FlexSPI_DLPR_DLP_MASK (0xFFFFFFFFU)
23845#define FlexSPI_DLPR_DLP_SHIFT (0U)
23846#define FlexSPI_DLPR_DLP(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLPR_DLP_SHIFT)) & FlexSPI_DLPR_DLP_MASK)
23847/*! @} */
23848
23849/*! @name IPRXFCR - IP RX FIFO Control Register */
23850/*! @{ */
23851#define FlexSPI_IPRXFCR_CLRIPRXF_MASK (0x1U)
23852#define FlexSPI_IPRXFCR_CLRIPRXF_SHIFT (0U)
23853#define FlexSPI_IPRXFCR_CLRIPRXF(x) \
23854 (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FlexSPI_IPRXFCR_CLRIPRXF_MASK)
23855#define FlexSPI_IPRXFCR_RXDMAEN_MASK (0x2U)
23856#define FlexSPI_IPRXFCR_RXDMAEN_SHIFT (1U)
23857/*! RXDMAEN - IP RX FIFO reading by DMA enabled.
23858 * 0b0..IP RX FIFO would be read by processor.
23859 * 0b1..IP RX FIFO would be read by DMA.
23860 */
23861#define FlexSPI_IPRXFCR_RXDMAEN(x) \
23862 (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPRXFCR_RXDMAEN_SHIFT)) & FlexSPI_IPRXFCR_RXDMAEN_MASK)
23863#define FlexSPI_IPRXFCR_RXWMRK_MASK (0xFCU)
23864#define FlexSPI_IPRXFCR_RXWMRK_SHIFT (2U)
23865#define FlexSPI_IPRXFCR_RXWMRK(x) \
23866 (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPRXFCR_RXWMRK_SHIFT)) & FlexSPI_IPRXFCR_RXWMRK_MASK)
23867/*! @} */
23868
23869/*! @name IPTXFCR - IP TX FIFO Control Register */
23870/*! @{ */
23871#define FlexSPI_IPTXFCR_CLRIPTXF_MASK (0x1U)
23872#define FlexSPI_IPTXFCR_CLRIPTXF_SHIFT (0U)
23873#define FlexSPI_IPTXFCR_CLRIPTXF(x) \
23874 (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FlexSPI_IPTXFCR_CLRIPTXF_MASK)
23875#define FlexSPI_IPTXFCR_TXDMAEN_MASK (0x2U)
23876#define FlexSPI_IPTXFCR_TXDMAEN_SHIFT (1U)
23877/*! TXDMAEN - IP TX FIFO filling by DMA enabled.
23878 * 0b0..IP TX FIFO would be filled by processor.
23879 * 0b1..IP TX FIFO would be filled by DMA.
23880 */
23881#define FlexSPI_IPTXFCR_TXDMAEN(x) \
23882 (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPTXFCR_TXDMAEN_SHIFT)) & FlexSPI_IPTXFCR_TXDMAEN_MASK)
23883#define FlexSPI_IPTXFCR_TXWMRK_MASK (0x1FCU)
23884#define FlexSPI_IPTXFCR_TXWMRK_SHIFT (2U)
23885#define FlexSPI_IPTXFCR_TXWMRK(x) \
23886 (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPTXFCR_TXWMRK_SHIFT)) & FlexSPI_IPTXFCR_TXWMRK_MASK)
23887/*! @} */
23888
23889/*! @name DLLCR - DLL Control Register 0 */
23890/*! @{ */
23891#define FlexSPI_DLLCR_DLLEN_MASK (0x1U)
23892#define FlexSPI_DLLCR_DLLEN_SHIFT (0U)
23893#define FlexSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLLCR_DLLEN_SHIFT)) & FlexSPI_DLLCR_DLLEN_MASK)
23894#define FlexSPI_DLLCR_DLLRESET_MASK (0x2U)
23895#define FlexSPI_DLLCR_DLLRESET_SHIFT (1U)
23896#define FlexSPI_DLLCR_DLLRESET(x) \
23897 (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLLCR_DLLRESET_SHIFT)) & FlexSPI_DLLCR_DLLRESET_MASK)
23898#define FlexSPI_DLLCR_SLVDLYTARGET_MASK (0x78U)
23899#define FlexSPI_DLLCR_SLVDLYTARGET_SHIFT (3U)
23900#define FlexSPI_DLLCR_SLVDLYTARGET(x) \
23901 (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FlexSPI_DLLCR_SLVDLYTARGET_MASK)
23902#define FlexSPI_DLLCR_OVRDEN_MASK (0x100U)
23903#define FlexSPI_DLLCR_OVRDEN_SHIFT (8U)
23904#define FlexSPI_DLLCR_OVRDEN(x) \
23905 (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLLCR_OVRDEN_SHIFT)) & FlexSPI_DLLCR_OVRDEN_MASK)
23906#define FlexSPI_DLLCR_OVRDVAL_MASK (0x7E00U)
23907#define FlexSPI_DLLCR_OVRDVAL_SHIFT (9U)
23908#define FlexSPI_DLLCR_OVRDVAL(x) \
23909 (((uint32_t)(((uint32_t)(x)) << FlexSPI_DLLCR_OVRDVAL_SHIFT)) & FlexSPI_DLLCR_OVRDVAL_MASK)
23910/*! @} */
23911
23912/* The count of FlexSPI_DLLCR */
23913#define FlexSPI_DLLCR_COUNT (2U)
23914
23915/*! @name STS0 - Status Register 0 */
23916/*! @{ */
23917#define FlexSPI_STS0_SEQIDLE_MASK (0x1U)
23918#define FlexSPI_STS0_SEQIDLE_SHIFT (0U)
23919#define FlexSPI_STS0_SEQIDLE(x) \
23920 (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS0_SEQIDLE_SHIFT)) & FlexSPI_STS0_SEQIDLE_MASK)
23921#define FlexSPI_STS0_ARBIDLE_MASK (0x2U)
23922#define FlexSPI_STS0_ARBIDLE_SHIFT (1U)
23923#define FlexSPI_STS0_ARBIDLE(x) \
23924 (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS0_ARBIDLE_SHIFT)) & FlexSPI_STS0_ARBIDLE_MASK)
23925#define FlexSPI_STS0_ARBCMDSRC_MASK (0xCU)
23926#define FlexSPI_STS0_ARBCMDSRC_SHIFT (2U)
23927/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted
23928 * by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).
23929 * 0b00..Triggered by AHB read command (triggered by AHB read).
23930 * 0b01..Triggered by AHB write command (triggered by AHB Write).
23931 * 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG).
23932 * 0b11..Triggered by suspended command (resumed).
23933 */
23934#define FlexSPI_STS0_ARBCMDSRC(x) \
23935 (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS0_ARBCMDSRC_SHIFT)) & FlexSPI_STS0_ARBCMDSRC_MASK)
23936#define FlexSPI_STS0_DATALEARNPHASEA_MASK (0xF0U)
23937#define FlexSPI_STS0_DATALEARNPHASEA_SHIFT (4U)
23938#define FlexSPI_STS0_DATALEARNPHASEA(x) \
23939 (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS0_DATALEARNPHASEA_SHIFT)) & FlexSPI_STS0_DATALEARNPHASEA_MASK)
23940#define FlexSPI_STS0_DATALEARNPHASEB_MASK (0xF00U)
23941#define FlexSPI_STS0_DATALEARNPHASEB_SHIFT (8U)
23942#define FlexSPI_STS0_DATALEARNPHASEB(x) \
23943 (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS0_DATALEARNPHASEB_SHIFT)) & FlexSPI_STS0_DATALEARNPHASEB_MASK)
23944/*! @} */
23945
23946/*! @name STS1 - Status Register 1 */
23947/*! @{ */
23948#define FlexSPI_STS1_AHBCMDERRID_MASK (0x1FU)
23949#define FlexSPI_STS1_AHBCMDERRID_SHIFT (0U)
23950#define FlexSPI_STS1_AHBCMDERRID(x) \
23951 (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS1_AHBCMDERRID_SHIFT)) & FlexSPI_STS1_AHBCMDERRID_MASK)
23952#define FlexSPI_STS1_AHBCMDERRCODE_MASK (0xF00U)
23953#define FlexSPI_STS1_AHBCMDERRCODE_SHIFT (8U)
23954/*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be
23955 * cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
23956 * 0b0000..No error.
23957 * 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence.
23958 * 0b0011..There is unknown instruction opcode in the sequence.
23959 * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
23960 * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
23961 * 0b1110..Sequence execution timeout.
23962 */
23963#define FlexSPI_STS1_AHBCMDERRCODE(x) \
23964 (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS1_AHBCMDERRCODE_SHIFT)) & FlexSPI_STS1_AHBCMDERRCODE_MASK)
23965#define FlexSPI_STS1_IPCMDERRID_MASK (0x1F0000U)
23966#define FlexSPI_STS1_IPCMDERRID_SHIFT (16U)
23967#define FlexSPI_STS1_IPCMDERRID(x) \
23968 (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS1_IPCMDERRID_SHIFT)) & FlexSPI_STS1_IPCMDERRID_MASK)
23969#define FlexSPI_STS1_IPCMDERRCODE_MASK (0xF000000U)
23970#define FlexSPI_STS1_IPCMDERRCODE_SHIFT (24U)
23971/*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be
23972 * cleared when INTR[IPCMDERR] is write-1-clear(w1c).
23973 * 0b0000..No error.
23974 * 0b0010..IP command with JMP_ON_CS instruction used in the sequence.
23975 * 0b0011..There is unknown instruction opcode in the sequence.
23976 * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
23977 * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
23978 * 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2).
23979 * 0b1110..Sequence execution timeout.
23980 * 0b1111..Flash boundary crossed.
23981 */
23982#define FlexSPI_STS1_IPCMDERRCODE(x) \
23983 (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS1_IPCMDERRCODE_SHIFT)) & FlexSPI_STS1_IPCMDERRCODE_MASK)
23984/*! @} */
23985
23986/*! @name STS2 - Status Register 2 */
23987/*! @{ */
23988#define FlexSPI_STS2_ASLVLOCK_MASK (0x1U)
23989#define FlexSPI_STS2_ASLVLOCK_SHIFT (0U)
23990#define FlexSPI_STS2_ASLVLOCK(x) \
23991 (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_ASLVLOCK_SHIFT)) & FlexSPI_STS2_ASLVLOCK_MASK)
23992#define FlexSPI_STS2_AREFLOCK_MASK (0x2U)
23993#define FlexSPI_STS2_AREFLOCK_SHIFT (1U)
23994#define FlexSPI_STS2_AREFLOCK(x) \
23995 (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_AREFLOCK_SHIFT)) & FlexSPI_STS2_AREFLOCK_MASK)
23996#define FlexSPI_STS2_ASLVSEL_MASK (0xFCU)
23997#define FlexSPI_STS2_ASLVSEL_SHIFT (2U)
23998#define FlexSPI_STS2_ASLVSEL(x) \
23999 (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_ASLVSEL_SHIFT)) & FlexSPI_STS2_ASLVSEL_MASK)
24000#define FlexSPI_STS2_AREFSEL_MASK (0x3F00U)
24001#define FlexSPI_STS2_AREFSEL_SHIFT (8U)
24002#define FlexSPI_STS2_AREFSEL(x) \
24003 (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_AREFSEL_SHIFT)) & FlexSPI_STS2_AREFSEL_MASK)
24004#define FlexSPI_STS2_BSLVLOCK_MASK (0x10000U)
24005#define FlexSPI_STS2_BSLVLOCK_SHIFT (16U)
24006#define FlexSPI_STS2_BSLVLOCK(x) \
24007 (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_BSLVLOCK_SHIFT)) & FlexSPI_STS2_BSLVLOCK_MASK)
24008#define FlexSPI_STS2_BREFLOCK_MASK (0x20000U)
24009#define FlexSPI_STS2_BREFLOCK_SHIFT (17U)
24010#define FlexSPI_STS2_BREFLOCK(x) \
24011 (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_BREFLOCK_SHIFT)) & FlexSPI_STS2_BREFLOCK_MASK)
24012#define FlexSPI_STS2_BSLVSEL_MASK (0xFC0000U)
24013#define FlexSPI_STS2_BSLVSEL_SHIFT (18U)
24014#define FlexSPI_STS2_BSLVSEL(x) \
24015 (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_BSLVSEL_SHIFT)) & FlexSPI_STS2_BSLVSEL_MASK)
24016#define FlexSPI_STS2_BREFSEL_MASK (0x3F000000U)
24017#define FlexSPI_STS2_BREFSEL_SHIFT (24U)
24018#define FlexSPI_STS2_BREFSEL(x) \
24019 (((uint32_t)(((uint32_t)(x)) << FlexSPI_STS2_BREFSEL_SHIFT)) & FlexSPI_STS2_BREFSEL_MASK)
24020/*! @} */
24021
24022/*! @name AHBSPNDSTS - AHB Suspend Status Register */
24023/*! @{ */
24024#define FlexSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U)
24025#define FlexSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U)
24026#define FlexSPI_AHBSPNDSTS_ACTIVE(x) \
24027 (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FlexSPI_AHBSPNDSTS_ACTIVE_MASK)
24028#define FlexSPI_AHBSPNDSTS_BUFID_MASK (0xEU)
24029#define FlexSPI_AHBSPNDSTS_BUFID_SHIFT (1U)
24030#define FlexSPI_AHBSPNDSTS_BUFID(x) \
24031 (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBSPNDSTS_BUFID_SHIFT)) & FlexSPI_AHBSPNDSTS_BUFID_MASK)
24032#define FlexSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U)
24033#define FlexSPI_AHBSPNDSTS_DATLFT_SHIFT (16U)
24034#define FlexSPI_AHBSPNDSTS_DATLFT(x) \
24035 (((uint32_t)(((uint32_t)(x)) << FlexSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FlexSPI_AHBSPNDSTS_DATLFT_MASK)
24036/*! @} */
24037
24038/*! @name IPRXFSTS - IP RX FIFO Status Register */
24039/*! @{ */
24040#define FlexSPI_IPRXFSTS_FILL_MASK (0xFFU)
24041#define FlexSPI_IPRXFSTS_FILL_SHIFT (0U)
24042#define FlexSPI_IPRXFSTS_FILL(x) \
24043 (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPRXFSTS_FILL_SHIFT)) & FlexSPI_IPRXFSTS_FILL_MASK)
24044#define FlexSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U)
24045#define FlexSPI_IPRXFSTS_RDCNTR_SHIFT (16U)
24046#define FlexSPI_IPRXFSTS_RDCNTR(x) \
24047 (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPRXFSTS_RDCNTR_SHIFT)) & FlexSPI_IPRXFSTS_RDCNTR_MASK)
24048/*! @} */
24049
24050/*! @name IPTXFSTS - IP TX FIFO Status Register */
24051/*! @{ */
24052#define FlexSPI_IPTXFSTS_FILL_MASK (0xFFU)
24053#define FlexSPI_IPTXFSTS_FILL_SHIFT (0U)
24054#define FlexSPI_IPTXFSTS_FILL(x) \
24055 (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPTXFSTS_FILL_SHIFT)) & FlexSPI_IPTXFSTS_FILL_MASK)
24056#define FlexSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U)
24057#define FlexSPI_IPTXFSTS_WRCNTR_SHIFT (16U)
24058#define FlexSPI_IPTXFSTS_WRCNTR(x) \
24059 (((uint32_t)(((uint32_t)(x)) << FlexSPI_IPTXFSTS_WRCNTR_SHIFT)) & FlexSPI_IPTXFSTS_WRCNTR_MASK)
24060/*! @} */
24061
24062/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */
24063/*! @{ */
24064#define FlexSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU)
24065#define FlexSPI_RFDR_RXDATA_SHIFT (0U)
24066#define FlexSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_RFDR_RXDATA_SHIFT)) & FlexSPI_RFDR_RXDATA_MASK)
24067/*! @} */
24068
24069/* The count of FlexSPI_RFDR */
24070#define FlexSPI_RFDR_COUNT (32U)
24071
24072/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */
24073/*! @{ */
24074#define FlexSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU)
24075#define FlexSPI_TFDR_TXDATA_SHIFT (0U)
24076#define FlexSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_TFDR_TXDATA_SHIFT)) & FlexSPI_TFDR_TXDATA_MASK)
24077/*! @} */
24078
24079/* The count of FlexSPI_TFDR */
24080#define FlexSPI_TFDR_COUNT (32U)
24081
24082/*! @name LUT - LUT 0..LUT 127 */
24083/*! @{ */
24084#define FlexSPI_LUT_OPERAND0_MASK (0xFFU)
24085#define FlexSPI_LUT_OPERAND0_SHIFT (0U)
24086#define FlexSPI_LUT_OPERAND0(x) \
24087 (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_OPERAND0_SHIFT)) & FlexSPI_LUT_OPERAND0_MASK)
24088#define FlexSPI_LUT_NUM_PADS0_MASK (0x300U)
24089#define FlexSPI_LUT_NUM_PADS0_SHIFT (8U)
24090#define FlexSPI_LUT_NUM_PADS0(x) \
24091 (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_NUM_PADS0_SHIFT)) & FlexSPI_LUT_NUM_PADS0_MASK)
24092#define FlexSPI_LUT_OPCODE0_MASK (0xFC00U)
24093#define FlexSPI_LUT_OPCODE0_SHIFT (10U)
24094#define FlexSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_OPCODE0_SHIFT)) & FlexSPI_LUT_OPCODE0_MASK)
24095#define FlexSPI_LUT_OPERAND1_MASK (0xFF0000U)
24096#define FlexSPI_LUT_OPERAND1_SHIFT (16U)
24097#define FlexSPI_LUT_OPERAND1(x) \
24098 (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_OPERAND1_SHIFT)) & FlexSPI_LUT_OPERAND1_MASK)
24099#define FlexSPI_LUT_NUM_PADS1_MASK (0x3000000U)
24100#define FlexSPI_LUT_NUM_PADS1_SHIFT (24U)
24101#define FlexSPI_LUT_NUM_PADS1(x) \
24102 (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_NUM_PADS1_SHIFT)) & FlexSPI_LUT_NUM_PADS1_MASK)
24103#define FlexSPI_LUT_OPCODE1_MASK (0xFC000000U)
24104#define FlexSPI_LUT_OPCODE1_SHIFT (26U)
24105#define FlexSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FlexSPI_LUT_OPCODE1_SHIFT)) & FlexSPI_LUT_OPCODE1_MASK)
24106/*! @} */
24107
24108/* The count of FlexSPI_LUT */
24109#define FlexSPI_LUT_COUNT (128U)
24110
24111/*!
24112 * @}
24113 */ /* end of group FlexSPI_Register_Masks */
24114
24115/* FlexSPI - Peripheral instance base addresses */
24116/** Peripheral FLEXSPI base address */
24117#define FLEXSPI_BASE (0x30BB0000u)
24118/** Peripheral FLEXSPI base pointer */
24119#define FLEXSPI ((FlexSPI_Type *)FLEXSPI_BASE)
24120/** Array initializer of FlexSPI peripheral base addresses */
24121#define FlexSPI_BASE_ADDRS \
24122 { \
24123 FLEXSPI_BASE \
24124 }
24125/** Array initializer of FlexSPI peripheral base pointers */
24126#define FlexSPI_BASE_PTRS \
24127 { \
24128 FLEXSPI \
24129 }
24130
24131/*!
24132 * @}
24133 */ /* end of group FlexSPI_Peripheral_Access_Layer */
24134
24135/* ----------------------------------------------------------------------------
24136 -- GPC Peripheral Access Layer
24137 ---------------------------------------------------------------------------- */
24138
24139/*!
24140 * @addtogroup GPC_Peripheral_Access_Layer GPC Peripheral Access Layer
24141 * @{
24142 */
24143
24144/** GPC - Register Layout Typedef */
24145typedef struct
24146{
24147 __IO uint32_t LPCR_A53_BSC; /**< Basic Low power control register of A53 platform, offset: 0x0 */
24148 __IO uint32_t LPCR_A53_AD; /**< Advanced Low power control register of A53 platform, offset: 0x4 */
24149 __IO uint32_t LPCR_M7; /**< Low power control register of CPU1, offset: 0x8 */
24150 uint8_t RESERVED_0[8];
24151 __IO uint32_t SLPCR; /**< System low power control register, offset: 0x14 */
24152 __IO uint32_t MST_CPU_MAPPING; /**< MASTER LPM Handshake, offset: 0x18 */
24153 uint8_t RESERVED_1[4];
24154 __IO uint32_t MLPCR; /**< Memory low power control register, offset: 0x20 */
24155 __IO uint32_t PGC_ACK_SEL_A53; /**< PGC acknowledge signal selection of A53 platform, offset: 0x24 */
24156 __IO uint32_t PGC_ACK_SEL_M7; /**< PGC acknowledge signal selection of M7 platform, offset: 0x28 */
24157 __IO uint32_t MISC; /**< GPC Miscellaneous register, offset: 0x2C */
24158 __IO uint32_t IMR_CORE0_A53[4]; /**< IRQ masking register 1 of A53 core0..IRQ masking register 4 of A53 core0, array
24159 offset: 0x30, array step: 0x4 */
24160 __IO uint32_t IMR_CORE1_A53[4]; /**< IRQ masking register 1 of A53 core1..IRQ masking register 4 of A53 core1, array
24161 offset: 0x40, array step: 0x4 */
24162 __IO uint32_t IMR_M7[4]; /**< IRQ masking register 1 of M7..IRQ masking register 4 of M7, array offset: 0x50, array
24163 step: 0x4 */
24164 uint8_t RESERVED_2[16];
24165 __I uint32_t ISR_A53[4]; /**< IRQ status register 1 of A53..IRQ status register 4 of A53, array offset: 0x70, array
24166 step: 0x4 */
24167 __I uint32_t
24168 ISR_M7[4]; /**< IRQ status register 1 of M7..IRQ status register 4 of M7, array offset: 0x80, array step: 0x4 */
24169 uint8_t RESERVED_3[32];
24170 __IO uint32_t SLT0_CFG; /**< Slot configure register for CPUs, offset: 0xB0 */
24171 __IO uint32_t SLT1_CFG; /**< Slot configure register for CPUs, offset: 0xB4 */
24172 __IO uint32_t SLT2_CFG; /**< Slot configure register for CPUs, offset: 0xB8 */
24173 __IO uint32_t SLT3_CFG; /**< Slot configure register for CPUs, offset: 0xBC */
24174 __IO uint32_t SLT4_CFG; /**< Slot configure register for CPUs, offset: 0xC0 */
24175 __IO uint32_t SLT5_CFG; /**< Slot configure register for CPUs, offset: 0xC4 */
24176 __IO uint32_t SLT6_CFG; /**< Slot configure register for CPUs, offset: 0xC8 */
24177 __IO uint32_t SLT7_CFG; /**< Slot configure register for CPUs, offset: 0xCC */
24178 __IO uint32_t SLT8_CFG; /**< Slot configure register for CPUs, offset: 0xD0 */
24179 __IO uint32_t SLT9_CFG; /**< Slot configure register for CPUs, offset: 0xD4 */
24180 __IO uint32_t SLT10_CFG; /**< Slot configure register for CPUs, offset: 0xD8 */
24181 __IO uint32_t SLT11_CFG; /**< Slot configure register for CPUs, offset: 0xDC */
24182 __IO uint32_t SLT12_CFG; /**< Slot configure register for CPUs, offset: 0xE0 */
24183 __IO uint32_t SLT13_CFG; /**< Slot configure register for CPUs, offset: 0xE4 */
24184 __IO uint32_t SLT14_CFG; /**< Slot configure register for CPUs, offset: 0xE8 */
24185 __IO uint32_t PGC_CPU_0_1_MAPPING; /**< PGC CPU mapping, offset: 0xEC */
24186 __IO uint32_t CPU_PGC_SW_PUP_REQ; /**< CPU PGC software power up trigger, offset: 0xF0 */
24187 __IO uint32_t MIX_PGC_SW_PUP_REQ; /**< MIX PGC software power up trigger, offset: 0xF4 */
24188 __IO uint32_t PU_PGC_SW_PUP_REQ; /**< PU PGC software up trigger, offset: 0xF8 */
24189 __IO uint32_t CPU_PGC_SW_PDN_REQ; /**< CPU PGC software down trigger, offset: 0xFC */
24190 __IO uint32_t MIX_PGC_SW_PDN_REQ; /**< MIX PGC software power down trigger, offset: 0x100 */
24191 __IO uint32_t PU_PGC_SW_PDN_REQ; /**< PU PGC software down trigger, offset: 0x104 */
24192 __IO uint32_t LPCR_A53_BSC2; /**< Basic Low power control register of A53 platform, offset: 0x108 */
24193 uint8_t RESERVED_4[36];
24194 __I uint32_t CPU_PGC_PUP_STATUS1; /**< CPU PGC software up trigger status1, offset: 0x130 */
24195 __I uint32_t A53_MIX_PGC_PUP_STATUS[3]; /**< A53 MIX software up trigger status register, array offset: 0x134, array
24196 step: 0x4 */
24197 __I uint32_t M7_MIX_PGC_PUP_STATUS[3]; /**< M7 MIX PGC software up trigger status register, array offset: 0x140,
24198 array step: 0x4 */
24199 __I uint32_t A53_PU_PGC_PUP_STATUS[3]; /**< A53 PU software up trigger status register, array offset: 0x14C, array
24200 step: 0x4 */
24201 __I uint32_t M7_PU_PGC_PUP_STATUS[3]; /**< M7 PU PGC software up trigger status register, array offset: 0x158, array
24202 step: 0x4 */
24203 uint8_t RESERVED_5[12];
24204 __I uint32_t CPU_PGC_PDN_STATUS1; /**< CPU PGC software dn trigger status1, offset: 0x170 */
24205 __I uint32_t A53_MIX_PGC_PDN_STATUS[3]; /**< A53 MIX software down trigger status register, array offset: 0x174,
24206 array step: 0x4 */
24207 __I uint32_t M7_MIX_PGC_PDN_STATUS[3]; /**< M7 MIX PGC software power down trigger status register, array offset:
24208 0x180, array step: 0x4 */
24209 __I uint32_t
24210 A53_PU_PGC_PDN_STATUS[3]; /**< A53 PU PGC software down trigger status, array offset: 0x18C, array step: 0x4 */
24211 __I uint32_t
24212 M7_PU_PGC_PDN_STATUS[3]; /**< M7 PU PGC software down trigger status, array offset: 0x198, array step: 0x4 */
24213 uint8_t RESERVED_6[12];
24214 __IO uint32_t A53_MIX_PDN_FLG; /**< A53 MIX PDN FLG, offset: 0x1B0 */
24215 __IO uint32_t A53_PU_PDN_FLG; /**< A53 PU PDN FLG, offset: 0x1B4 */
24216 __IO uint32_t M7_MIX_PDN_FLG; /**< M7 MIX PDN FLG, offset: 0x1B8 */
24217 __IO uint32_t M7_PU_PDN_FLG; /**< M7 PU PDN FLG, offset: 0x1BC */
24218 __IO uint32_t IMR_CORE2_A53[4]; /**< IRQ masking register 1 of A53 core2..IRQ masking register 4 of A53 core2, array
24219 offset: 0x1C0, array step: 0x4 */
24220 __IO uint32_t IMR_CORE3_A53[4]; /**< IRQ masking register 1 of A53 core3..IRQ masking register 4 of A53 core3, array
24221 offset: 0x1D0, array step: 0x4 */
24222 __IO uint32_t ACK_SEL_A53_PU; /**< PGC acknowledge signal selection of A53 platform for PUs, offset: 0x1E0 */
24223 __IO uint32_t ACK_SEL_M7_PU; /**< PGC acknowledge signal selection of M7 platform for PUs, offset: 0x1E4 */
24224 __IO uint32_t SLT15_CFG; /**< Slot configure register for PGC CPUs, offset: 0x1E8 */
24225 __IO uint32_t SLT16_CFG; /**< Slot configure register for PGC CPUs, offset: 0x1EC */
24226 __IO uint32_t SLT17_CFG; /**< Slot configure register for PGC CPUs, offset: 0x1F0 */
24227 __IO uint32_t SLT18_CFG; /**< Slot configure register for PGC CPUs, offset: 0x1F4 */
24228 __IO uint32_t SLT19_CFG; /**< Slot configure register for PGC CPUs, offset: 0x1F8 */
24229 __IO uint32_t PU_PWRHSK; /**< Power handshake register, offset: 0x1FC */
24230 __IO uint32_t SLT_CFG_PU[20]; /**< Slot configure register for PGC PUs, array offset: 0x200, array step: 0x4 */
24231} GPC_Type;
24232
24233/* ----------------------------------------------------------------------------
24234 -- GPC Register Masks
24235 ---------------------------------------------------------------------------- */
24236
24237/*!
24238 * @addtogroup GPC_Register_Masks GPC Register Masks
24239 * @{
24240 */
24241
24242/*! @name LPCR_A53_BSC - Basic Low power control register of A53 platform */
24243/*! @{ */
24244#define GPC_LPCR_A53_BSC_LPM0_MASK (0x3U)
24245#define GPC_LPCR_A53_BSC_LPM0_SHIFT (0U)
24246/*! LPM0
24247 * 0b00..Remain in RUN mode
24248 * 0b01..Transfer to WAIT mode
24249 * 0b10..Transfer to STOP mode
24250 * 0b11..Reserved
24251 */
24252#define GPC_LPCR_A53_BSC_LPM0(x) \
24253 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_LPM0_SHIFT)) & GPC_LPCR_A53_BSC_LPM0_MASK)
24254#define GPC_LPCR_A53_BSC_LPM1_MASK (0xCU)
24255#define GPC_LPCR_A53_BSC_LPM1_SHIFT (2U)
24256/*! LPM1
24257 * 0b00..Remain in RUN mode
24258 * 0b01..Transfer to WAIT mode
24259 * 0b10..Transfer to STOP mode
24260 * 0b11..Reserved
24261 */
24262#define GPC_LPCR_A53_BSC_LPM1(x) \
24263 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_LPM1_SHIFT)) & GPC_LPCR_A53_BSC_LPM1_MASK)
24264#define GPC_LPCR_A53_BSC_MST0_LPM_HSK_MASK_MASK (0x40U)
24265#define GPC_LPCR_A53_BSC_MST0_LPM_HSK_MASK_SHIFT (6U)
24266/*! MST0_LPM_HSK_MASK - MASTER0 LPM handshake mask
24267 * 0b0..enable MASTER0 LPM handshake, wait ACK from MASTER0
24268 * 0b1..disable MASTER0 LPM handshake, mask ACK from MASTER0
24269 */
24270#define GPC_LPCR_A53_BSC_MST0_LPM_HSK_MASK(x) \
24271 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MST0_LPM_HSK_MASK_SHIFT)) & \
24272 GPC_LPCR_A53_BSC_MST0_LPM_HSK_MASK_MASK)
24273#define GPC_LPCR_A53_BSC_MST1_LPM_HSK_MASK_MASK (0x80U)
24274#define GPC_LPCR_A53_BSC_MST1_LPM_HSK_MASK_SHIFT (7U)
24275/*! MST1_LPM_HSK_MASK - MASTER1 LPM handshake mask
24276 * 0b0..enable MASTER1 LPM handshake, wait ACK from MASTER1
24277 * 0b1..disable MASTER1 LPM handshake, mask ACK from MASTER1
24278 */
24279#define GPC_LPCR_A53_BSC_MST1_LPM_HSK_MASK(x) \
24280 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MST1_LPM_HSK_MASK_SHIFT)) & \
24281 GPC_LPCR_A53_BSC_MST1_LPM_HSK_MASK_MASK)
24282#define GPC_LPCR_A53_BSC_MST2_LPM_HSK_MASK_MASK (0x100U)
24283#define GPC_LPCR_A53_BSC_MST2_LPM_HSK_MASK_SHIFT (8U)
24284/*! MST2_LPM_HSK_MASK - MASTER2 LPM handshake mask
24285 * 0b0..enable MASTER2 LPM handshake, wait ACK from MASTER2
24286 * 0b1..disable MASTER2 LPM handshake, mask ACK from MASTER2
24287 */
24288#define GPC_LPCR_A53_BSC_MST2_LPM_HSK_MASK(x) \
24289 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MST2_LPM_HSK_MASK_SHIFT)) & \
24290 GPC_LPCR_A53_BSC_MST2_LPM_HSK_MASK_MASK)
24291#define GPC_LPCR_A53_BSC_MST3_LPM_HSK_MASK_MASK (0x200U)
24292#define GPC_LPCR_A53_BSC_MST3_LPM_HSK_MASK_SHIFT (9U)
24293/*! MST3_LPM_HSK_MASK - MASTER3 LPM handshake mask
24294 * 0b0..enable MASTER3 LPM handshake, wait ACK from MASTER3
24295 * 0b1..disable MASTER3 LPM handshake, mask ACK from MASTER3
24296 */
24297#define GPC_LPCR_A53_BSC_MST3_LPM_HSK_MASK(x) \
24298 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MST3_LPM_HSK_MASK_SHIFT)) & \
24299 GPC_LPCR_A53_BSC_MST3_LPM_HSK_MASK_MASK)
24300#define GPC_LPCR_A53_BSC_MST4_LPM_HSK_MASK_MASK (0x400U)
24301#define GPC_LPCR_A53_BSC_MST4_LPM_HSK_MASK_SHIFT (10U)
24302/*! MST4_LPM_HSK_MASK - MASTER4 LPM handshake mask
24303 * 0b0..enable MASTER4 LPM handshake, wait ACK from MASTER4
24304 * 0b1..disable MASTER4 LPM handshake, mask ACK from MASTER4
24305 */
24306#define GPC_LPCR_A53_BSC_MST4_LPM_HSK_MASK(x) \
24307 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MST4_LPM_HSK_MASK_SHIFT)) & \
24308 GPC_LPCR_A53_BSC_MST4_LPM_HSK_MASK_MASK)
24309#define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_MASK (0x4000U)
24310#define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_SHIFT (14U)
24311/*! CPU_CLK_ON_LPM
24312 * 0b0..A53 clock disabled on wait/stop mode
24313 * 0b1..A53 clock enabled on wait/stop mode
24314 */
24315#define GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM(x) \
24316 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_SHIFT)) & GPC_LPCR_A53_BSC_CPU_CLK_ON_LPM_MASK)
24317#define GPC_LPCR_A53_BSC_MASK_CORE0_WFI_MASK (0x10000U)
24318#define GPC_LPCR_A53_BSC_MASK_CORE0_WFI_SHIFT (16U)
24319/*! MASK_CORE0_WFI
24320 * 0b0..WFI for CORE0 is not masked
24321 * 0b1..WFI for CORE0 is masked
24322 */
24323#define GPC_LPCR_A53_BSC_MASK_CORE0_WFI(x) \
24324 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE0_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE0_WFI_MASK)
24325#define GPC_LPCR_A53_BSC_MASK_CORE1_WFI_MASK (0x20000U)
24326#define GPC_LPCR_A53_BSC_MASK_CORE1_WFI_SHIFT (17U)
24327/*! MASK_CORE1_WFI
24328 * 0b0..WFI for CORE1 is not masked
24329 * 0b1..WFI for CORE1 is masked
24330 */
24331#define GPC_LPCR_A53_BSC_MASK_CORE1_WFI(x) \
24332 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE1_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE1_WFI_MASK)
24333#define GPC_LPCR_A53_BSC_MASK_CORE2_WFI_MASK (0x40000U)
24334#define GPC_LPCR_A53_BSC_MASK_CORE2_WFI_SHIFT (18U)
24335/*! MASK_CORE2_WFI
24336 * 0b0..WFI for CORE2 is not masked
24337 * 0b1..WFI for CORE2 is masked
24338 */
24339#define GPC_LPCR_A53_BSC_MASK_CORE2_WFI(x) \
24340 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE2_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE2_WFI_MASK)
24341#define GPC_LPCR_A53_BSC_MASK_CORE3_WFI_MASK (0x80000U)
24342#define GPC_LPCR_A53_BSC_MASK_CORE3_WFI_SHIFT (19U)
24343/*! MASK_CORE3_WFI
24344 * 0b0..WFI for CORE3 is not masked
24345 * 0b1..WFI for CORE3 is masked
24346 */
24347#define GPC_LPCR_A53_BSC_MASK_CORE3_WFI(x) \
24348 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_CORE3_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_CORE3_WFI_MASK)
24349#define GPC_LPCR_A53_BSC_IRQ_SRC_C2_MASK (0x400000U)
24350#define GPC_LPCR_A53_BSC_IRQ_SRC_C2_SHIFT (22U)
24351/*! IRQ_SRC_C2
24352 * 0b0..core2 wakeup source from external INT[127:0], masked by IMR1. See Power Up Process for A53 Platform for more
24353 * specific information. 0b1..core2 wakeup source from external GIC(nFIQ[1]/nIRQ[1]), SCU should not be powered down
24354 * during low power mode when this bit is set to 1'b1.
24355 */
24356#define GPC_LPCR_A53_BSC_IRQ_SRC_C2(x) \
24357 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C2_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C2_MASK)
24358#define GPC_LPCR_A53_BSC_IRQ_SRC_C3_MASK (0x800000U)
24359#define GPC_LPCR_A53_BSC_IRQ_SRC_C3_SHIFT (23U)
24360/*! IRQ_SRC_C3
24361 * 0b0..core3 wakeup source from external INT[127:0], masked by IMR1. See Power Up Process for A53 Platform for more
24362 * specific information. 0b1..core3 wakeup source from external GIC(nFIQ[1]/nIRQ[1]), SCU should not be powered down
24363 * during low power mode when this bit is set to 1'b1.
24364 */
24365#define GPC_LPCR_A53_BSC_IRQ_SRC_C3(x) \
24366 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C3_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C3_MASK)
24367#define GPC_LPCR_A53_BSC_MASK_SCU_WFI_MASK (0x1000000U)
24368#define GPC_LPCR_A53_BSC_MASK_SCU_WFI_SHIFT (24U)
24369/*! MASK_SCU_WFI
24370 * 0b0..WFI for SCU is not masked
24371 * 0b1..WFI for SCU is masked
24372 */
24373#define GPC_LPCR_A53_BSC_MASK_SCU_WFI(x) \
24374 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_SCU_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_SCU_WFI_MASK)
24375#define GPC_LPCR_A53_BSC_MASK_L2CC_WFI_MASK (0x4000000U)
24376#define GPC_LPCR_A53_BSC_MASK_L2CC_WFI_SHIFT (26U)
24377/*! MASK_L2CC_WFI
24378 * 0b0..WFI for L2 cache controller is not masked
24379 * 0b1..WFI for L2 cache controller is masked
24380 */
24381#define GPC_LPCR_A53_BSC_MASK_L2CC_WFI(x) \
24382 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_L2CC_WFI_SHIFT)) & GPC_LPCR_A53_BSC_MASK_L2CC_WFI_MASK)
24383#define GPC_LPCR_A53_BSC_IRQ_SRC_C0_MASK (0x10000000U)
24384#define GPC_LPCR_A53_BSC_IRQ_SRC_C0_SHIFT (28U)
24385/*! IRQ_SRC_C0
24386 * 0b0..core0 wakeup source from external INT[127:0], masked by IMR0 refer to "Power up process for A53 platform" for
24387 * more specific information 0b1..core0 wakeup source from GIC(nFIQ[0]/nIRQ[0] ), SCU should not be power down during
24388 * low power mode when this bit is set to 1'b1
24389 */
24390#define GPC_LPCR_A53_BSC_IRQ_SRC_C0(x) \
24391 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C0_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C0_MASK)
24392#define GPC_LPCR_A53_BSC_IRQ_SRC_C1_MASK (0x20000000U)
24393#define GPC_LPCR_A53_BSC_IRQ_SRC_C1_SHIFT (29U)
24394/*! IRQ_SRC_C1
24395 * 0b0..core1 wakeup source from external INT[127:0], masked by IMR1 refer to "Power up process for A53 platform" for
24396 * more specific information 0b1..core1 wakeup source from GIC(nFIQ[1]/nIRQ[1] ), SCU should not be power down during
24397 * low power mode when this bit is set to 1'b1
24398 */
24399#define GPC_LPCR_A53_BSC_IRQ_SRC_C1(x) \
24400 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_C1_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_C1_MASK)
24401#define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_MASK (0x40000000U)
24402#define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_SHIFT (30U)
24403/*! IRQ_SRC_A53_WUP
24404 * 0b0..LPM wakeup source be "OR" result of
24405 * LPCR_A53_BSC[IRQ_SRC_C0]/LPCR_A53_BSC[IRQ_SRC_C1]/LPCR_A53_BSC[IRQ_SRC_C2]/LPCR_A53_BSC[IRQ_SRC_C3] setting
24406 * 0b1..LPM wakeup source from external INT[127:0], masked by IMR0
24407 */
24408#define GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP(x) \
24409 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_SHIFT)) & GPC_LPCR_A53_BSC_IRQ_SRC_A53_WUP_MASK)
24410#define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_MASK (0x80000000U)
24411#define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_SHIFT (31U)
24412/*! MASK_DSM_TRIGGER
24413 * 0b0..DSM trigger of A53 platform will not be masked
24414 * 0b1..DSM trigger of A53 platform will be masked
24415 */
24416#define GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER(x) \
24417 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_SHIFT)) & GPC_LPCR_A53_BSC_MASK_DSM_TRIGGER_MASK)
24418/*! @} */
24419
24420/*! @name LPCR_A53_AD - Advanced Low power control register of A53 platform */
24421/*! @{ */
24422#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_MASK (0x1U)
24423#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_SHIFT (0U)
24424/*! EN_C0_WFI_PDN
24425 * 0b0..CORE0 will not be power down with WFI request
24426 * 0b1..CORE0 will be power down with WFI request
24427 */
24428#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN(x) \
24429 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_WFI_PDN_MASK)
24430#define GPC_LPCR_A53_AD_EN_C0_PDN_MASK (0x2U)
24431#define GPC_LPCR_A53_AD_EN_C0_PDN_SHIFT (1U)
24432/*! EN_C0_PDN
24433 * 0b0..CORE0 will not be power down with low power mode request
24434 * 0b1..CORE0 will be power down with low power mode request
24435 */
24436#define GPC_LPCR_A53_AD_EN_C0_PDN(x) \
24437 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_PDN_MASK)
24438#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_MASK (0x4U)
24439#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_SHIFT (2U)
24440/*! EN_C1_WFI_PDN
24441 * 0b0..CORE1 will not be power down with WFI request
24442 * 0b1..CORE1 will be power down with WFI request
24443 */
24444#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN(x) \
24445 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_WFI_PDN_MASK)
24446#define GPC_LPCR_A53_AD_EN_C1_PDN_MASK (0x8U)
24447#define GPC_LPCR_A53_AD_EN_C1_PDN_SHIFT (3U)
24448/*! EN_C1_PDN
24449 * 0b0..CORE1 will not be power down with low power mode request
24450 * 0b1..CORE1 will be power down with low power mode request
24451 */
24452#define GPC_LPCR_A53_AD_EN_C1_PDN(x) \
24453 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_PDN_MASK)
24454#define GPC_LPCR_A53_AD_EN_PLAT_PDN_MASK (0x10U)
24455#define GPC_LPCR_A53_AD_EN_PLAT_PDN_SHIFT (4U)
24456/*! EN_PLAT_PDN
24457 * 0b0..SCU and L2 cache RAM will not be power down with low power mode request
24458 * 0b1..SCU and L2 cache RAM will be power down with low power mode request
24459 */
24460#define GPC_LPCR_A53_AD_EN_PLAT_PDN(x) \
24461 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_PLAT_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_PLAT_PDN_MASK)
24462#define GPC_LPCR_A53_AD_EN_L2_WFI_PDN_MASK (0x20U)
24463#define GPC_LPCR_A53_AD_EN_L2_WFI_PDN_SHIFT (5U)
24464/*! EN_L2_WFI_PDN
24465 * 0b0..SCU and L2 will not be power down with WFI request
24466 * 0b1..SCU and L2 will be power down with WFI request (default)
24467 */
24468#define GPC_LPCR_A53_AD_EN_L2_WFI_PDN(x) \
24469 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_L2_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_L2_WFI_PDN_MASK)
24470#define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_MASK (0x100U)
24471#define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_SHIFT (8U)
24472/*! EN_C0_IRQ_PUP
24473 * 0b0..CORE0 will not power up with IRQ request
24474 * 0b1..CORE0 will power up with IRQ request
24475 */
24476#define GPC_LPCR_A53_AD_EN_C0_IRQ_PUP(x) \
24477 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_IRQ_PUP_MASK)
24478#define GPC_LPCR_A53_AD_EN_C0_PUP_MASK (0x200U)
24479#define GPC_LPCR_A53_AD_EN_C0_PUP_SHIFT (9U)
24480/*! EN_C0_PUP
24481 * 0b0..CORE0 will not power up with low power mode request
24482 * 0b1..CORE0 will power up with low power mode request
24483 */
24484#define GPC_LPCR_A53_AD_EN_C0_PUP(x) \
24485 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_PUP_MASK)
24486#define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_MASK (0x400U)
24487#define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_SHIFT (10U)
24488/*! EN_C1_IRQ_PUP
24489 * 0b0..CORE1 will not power up with IRQ request
24490 * 0b1..CORE1 will power up with IRQ request
24491 */
24492#define GPC_LPCR_A53_AD_EN_C1_IRQ_PUP(x) \
24493 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_IRQ_PUP_MASK)
24494#define GPC_LPCR_A53_AD_EN_C1_PUP_MASK (0x800U)
24495#define GPC_LPCR_A53_AD_EN_C1_PUP_SHIFT (11U)
24496/*! EN_C1_PUP
24497 * 0b0..CORE1 will not power up with low power mode request (only used wake up from CPU01_OFF mode)
24498 * 0b1..CORE1 will power up with low power mode request
24499 */
24500#define GPC_LPCR_A53_AD_EN_C1_PUP(x) \
24501 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_PUP_MASK)
24502#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_MASK (0x10000U)
24503#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_SHIFT (16U)
24504/*! EN_C2_WFI_PDN
24505 * 0b0..CORE2 will not be power down with WFI request
24506 * 0b1..CORE2 will be power down with WFI request
24507 */
24508#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN(x) \
24509 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_WFI_PDN_MASK)
24510#define GPC_LPCR_A53_AD_EN_C2_PDN_MASK (0x20000U)
24511#define GPC_LPCR_A53_AD_EN_C2_PDN_SHIFT (17U)
24512/*! EN_C2_PDN
24513 * 0b0..CORE2 will not be power down with low power mode request
24514 * 0b1..CORE2 will be power down with low power mode request
24515 */
24516#define GPC_LPCR_A53_AD_EN_C2_PDN(x) \
24517 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_PDN_MASK)
24518#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_MASK (0x40000U)
24519#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_SHIFT (18U)
24520/*! EN_C3_WFI_PDN
24521 * 0b0..CORE3 will not be power down with WFI request
24522 * 0b1..CORE3 will be power down with WFI request
24523 */
24524#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN(x) \
24525 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_WFI_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_WFI_PDN_MASK)
24526#define GPC_LPCR_A53_AD_EN_C3_PDN_MASK (0x80000U)
24527#define GPC_LPCR_A53_AD_EN_C3_PDN_SHIFT (19U)
24528/*! EN_C3_PDN
24529 * 0b0..CORE3 will not be power down with low power mode request
24530 * 0b1..CORE3 will be power down with low power mode request
24531 */
24532#define GPC_LPCR_A53_AD_EN_C3_PDN(x) \
24533 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_PDN_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_PDN_MASK)
24534#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS_MASK (0x100000U)
24535#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS_SHIFT (20U)
24536/*! EN_C0_WFI_PDN_DIS
24537 * 0b0..Disable WIFI power down core0
24538 * 0b1..Enable WIFI power down core0
24539 */
24540#define GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS(x) \
24541 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS_SHIFT)) & GPC_LPCR_A53_AD_EN_C0_WFI_PDN_DIS_MASK)
24542#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS_MASK (0x200000U)
24543#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS_SHIFT (21U)
24544/*! EN_C1_WFI_PDN_DIS
24545 * 0b0..Disable WIFI power down core1
24546 * 0b1..Enable WIFI power down core1
24547 */
24548#define GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS(x) \
24549 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS_SHIFT)) & GPC_LPCR_A53_AD_EN_C1_WFI_PDN_DIS_MASK)
24550#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS_MASK (0x400000U)
24551#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS_SHIFT (22U)
24552/*! EN_C2_WFI_PDN_DIS
24553 * 0b0..Disable WIFI power down core2
24554 * 0b1..Enable WIFI power down core2
24555 */
24556#define GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS(x) \
24557 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_WFI_PDN_DIS_MASK)
24558#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS_MASK (0x800000U)
24559#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS_SHIFT (23U)
24560/*! EN_C3_WFI_PDN_DIS
24561 * 0b0..Disable WFI power down core3
24562 * 0b1..Enable WFI power down core3
24563 */
24564#define GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS(x) \
24565 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_WFI_PDN_DIS_MASK)
24566#define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_MASK (0x1000000U)
24567#define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_SHIFT (24U)
24568/*! EN_C2_IRQ_PUP
24569 * 0b0..CORE2 will not power up with IRQ request
24570 * 0b1..CORE2 will power up with IRQ request
24571 */
24572#define GPC_LPCR_A53_AD_EN_C2_IRQ_PUP(x) \
24573 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_IRQ_PUP_MASK)
24574#define GPC_LPCR_A53_AD_EN_C2_PUP_MASK (0x2000000U)
24575#define GPC_LPCR_A53_AD_EN_C2_PUP_SHIFT (25U)
24576/*! EN_C2_PUP
24577 * 0b0..CORE2 will not power up with lower power mode request
24578 * 0b1..CORE2 will power up with low power mode request (only used wake up from CPU_OFF)
24579 */
24580#define GPC_LPCR_A53_AD_EN_C2_PUP(x) \
24581 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C2_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C2_PUP_MASK)
24582#define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_MASK (0x4000000U)
24583#define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_SHIFT (26U)
24584/*! EN_C3_IRQ_PUP
24585 * 0b0..CORE3 will not power up with IRQ request
24586 * 0b1..CORE3 will power up with IRQ request
24587 */
24588#define GPC_LPCR_A53_AD_EN_C3_IRQ_PUP(x) \
24589 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_IRQ_PUP_MASK)
24590#define GPC_LPCR_A53_AD_EN_C3_PUP_MASK (0x8000000U)
24591#define GPC_LPCR_A53_AD_EN_C3_PUP_SHIFT (27U)
24592/*! EN_C3_PUP
24593 * 0b0..CORE3 will not power up with lower power mode request
24594 * 0b1..CORE3 will power up with low power mode request (only used wake up from CPU_OFF)
24595 */
24596#define GPC_LPCR_A53_AD_EN_C3_PUP(x) \
24597 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_EN_C3_PUP_SHIFT)) & GPC_LPCR_A53_AD_EN_C3_PUP_MASK)
24598#define GPC_LPCR_A53_AD_L2PGE_MASK (0x80000000U)
24599#define GPC_LPCR_A53_AD_L2PGE_SHIFT (31U)
24600/*! L2PGE
24601 * 0b0..L2 cache RAM will power down with SCU power domain in A53 platform (used for ALL_OFF mode)
24602 * 0b1..L2 cache RAM will not power down with SCU power domain in A53 platform (used for ALL_OFF mode)
24603 */
24604#define GPC_LPCR_A53_AD_L2PGE(x) \
24605 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_AD_L2PGE_SHIFT)) & GPC_LPCR_A53_AD_L2PGE_MASK)
24606/*! @} */
24607
24608/*! @name LPCR_M7 - Low power control register of CPU1 */
24609/*! @{ */
24610#define GPC_LPCR_M7_LPM0_MASK (0x3U)
24611#define GPC_LPCR_M7_LPM0_SHIFT (0U)
24612/*! LPM0
24613 * 0b00..Remain in RUN mode
24614 * 0b01..Transfer to WAIT mode
24615 * 0b10..Transfer to STOP mode
24616 * 0b11..Reserved
24617 */
24618#define GPC_LPCR_M7_LPM0(x) (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_LPM0_SHIFT)) & GPC_LPCR_M7_LPM0_MASK)
24619#define GPC_LPCR_M7_EN_M7_PDN_MASK (0x4U)
24620#define GPC_LPCR_M7_EN_M7_PDN_SHIFT (2U)
24621#define GPC_LPCR_M7_EN_M7_PDN(x) \
24622 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_EN_M7_PDN_SHIFT)) & GPC_LPCR_M7_EN_M7_PDN_MASK)
24623#define GPC_LPCR_M7_EN_M7_PUP_MASK (0x8U)
24624#define GPC_LPCR_M7_EN_M7_PUP_SHIFT (3U)
24625#define GPC_LPCR_M7_EN_M7_PUP(x) \
24626 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_EN_M7_PUP_SHIFT)) & GPC_LPCR_M7_EN_M7_PUP_MASK)
24627#define GPC_LPCR_M7_CPU_CLK_ON_LPM_MASK (0x4000U)
24628#define GPC_LPCR_M7_CPU_CLK_ON_LPM_SHIFT (14U)
24629/*! CPU_CLK_ON_LPM
24630 * 0b0..M7 clock disabled on wait/stop mode.
24631 * 0b1..M7 clock enabled on wait/stop mode.
24632 */
24633#define GPC_LPCR_M7_CPU_CLK_ON_LPM(x) \
24634 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_CPU_CLK_ON_LPM_SHIFT)) & GPC_LPCR_M7_CPU_CLK_ON_LPM_MASK)
24635#define GPC_LPCR_M7_MASK_M7_WFI_MASK (0x10000U)
24636#define GPC_LPCR_M7_MASK_M7_WFI_SHIFT (16U)
24637/*! MASK_M7_WFI
24638 * 0b0..WFI for M7 is not masked
24639 * 0b1..WFI for M7 is masked
24640 */
24641#define GPC_LPCR_M7_MASK_M7_WFI(x) \
24642 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_MASK_M7_WFI_SHIFT)) & GPC_LPCR_M7_MASK_M7_WFI_MASK)
24643#define GPC_LPCR_M7_MASK_DSM_TRIGGER_MASK (0x80000000U)
24644#define GPC_LPCR_M7_MASK_DSM_TRIGGER_SHIFT (31U)
24645/*! MASK_DSM_TRIGGER
24646 * 0b0..DSM trigger of M7 platform will not be masked
24647 * 0b1..DSM trigger of M7 platform will be masked
24648 */
24649#define GPC_LPCR_M7_MASK_DSM_TRIGGER(x) \
24650 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_M7_MASK_DSM_TRIGGER_SHIFT)) & GPC_LPCR_M7_MASK_DSM_TRIGGER_MASK)
24651/*! @} */
24652
24653/*! @name SLPCR - System low power control register */
24654/*! @{ */
24655#define GPC_SLPCR_BYPASS_PMIC_READY_MASK (0x1U)
24656#define GPC_SLPCR_BYPASS_PMIC_READY_SHIFT (0U)
24657/*! BYPASS_PMIC_READY
24658 * 0b0..Don't bypass the PMIC_READY signal - GPC will wait for its assertion during exit of low power mode if standby
24659 * voltage was enabled 0b1..Bypass the PMIC_READY signal - GPC will not wait for its assertion during exit of low power
24660 * mode if standby voltage was enabled
24661 */
24662#define GPC_SLPCR_BYPASS_PMIC_READY(x) \
24663 (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_BYPASS_PMIC_READY_SHIFT)) & GPC_SLPCR_BYPASS_PMIC_READY_MASK)
24664#define GPC_SLPCR_SBYOS_MASK (0x2U)
24665#define GPC_SLPCR_SBYOS_SHIFT (1U)
24666/*! SBYOS
24667 * 0b0..On chip oscillator will not be powered down, after next entrance to DSM.
24668 * 0b1..On chip oscillator will be powered down, after next entrance to DSM. When returning from DSM, external
24669 * oscillator will be enabled again, on chip oscillator will return to oscillator mode , and after oscnt count
24670 * GPC will continue with the exit from DSM process.
24671 */
24672#define GPC_SLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_SBYOS_SHIFT)) & GPC_SLPCR_SBYOS_MASK)
24673#define GPC_SLPCR_VSTBY_MASK (0x4U)
24674#define GPC_SLPCR_VSTBY_SHIFT (2U)
24675/*! VSTBY
24676 * 0b0..Voltage will not be changed to standby voltage after next entrance to stop mode. (PMIC_STBY_REQ will remain
24677 * negated - '0') 0b1..Voltage will be changed to standby voltage after next entrance to stop mode.
24678 */
24679#define GPC_SLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_VSTBY_SHIFT)) & GPC_SLPCR_VSTBY_MASK)
24680#define GPC_SLPCR_STBY_COUNT_MASK (0x38U)
24681#define GPC_SLPCR_STBY_COUNT_SHIFT (3U)
24682/*! STBY_COUNT
24683 * 0b000..GPC will wait 4 ckil clock cycles
24684 * 0b001..GPC will wait 8 ckil clock cycles
24685 * 0b010..GPC will wait 16 ckil clock cycles
24686 * 0b011..GPC will wait 32 ckil clock cycles
24687 * 0b100..GPC will wait 64 ckil clock cycles
24688 * 0b101..GPC will wait 128 ckil clock cycles
24689 * 0b110..GPC will wait 256 ckil clock cycles
24690 * 0b111..GPC will wait 512 ckil clock cycles
24691 */
24692#define GPC_SLPCR_STBY_COUNT(x) \
24693 (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_STBY_COUNT_SHIFT)) & GPC_SLPCR_STBY_COUNT_MASK)
24694#define GPC_SLPCR_COSC_PWRDOWN_MASK (0x40U)
24695#define GPC_SLPCR_COSC_PWRDOWN_SHIFT (6U)
24696/*! COSC_PWRDOWN
24697 * 0b0..On-chip oscillator will not be powered down, i.e. cosc_pwrdown = 0
24698 * 0b1..On-chip oscillator will be powered down, i.e. cosc_pwrdown = 1
24699 */
24700#define GPC_SLPCR_COSC_PWRDOWN(x) \
24701 (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_COSC_PWRDOWN_SHIFT)) & GPC_SLPCR_COSC_PWRDOWN_MASK)
24702#define GPC_SLPCR_COSC_EN_MASK (0x80U)
24703#define GPC_SLPCR_COSC_EN_SHIFT (7U)
24704/*! COSC_EN
24705 * 0b0..Disable on-chip oscillator
24706 * 0b1..Enable on-chip oscillator
24707 */
24708#define GPC_SLPCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_COSC_EN_SHIFT)) & GPC_SLPCR_COSC_EN_MASK)
24709#define GPC_SLPCR_OSCCNT_MASK (0xFF00U)
24710#define GPC_SLPCR_OSCCNT_SHIFT (8U)
24711/*! OSCCNT
24712 * 0b00000000..count 1 ckil
24713 * 0b11111111..count 256 ckils
24714 */
24715#define GPC_SLPCR_OSCCNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_OSCCNT_SHIFT)) & GPC_SLPCR_OSCCNT_MASK)
24716#define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_MASK (0x10000U)
24717#define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_SHIFT (16U)
24718#define GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE(x) \
24719 (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_SHIFT)) & \
24720 GPC_SLPCR_EN_A53_FASTWUP_WAIT_MODE_MASK)
24721#define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_MASK (0x20000U)
24722#define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_SHIFT (17U)
24723#define GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE(x) \
24724 (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_SHIFT)) & \
24725 GPC_SLPCR_EN_A53_FASTWUP_STOP_MODE_MASK)
24726#define GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE_MASK (0x40000U)
24727#define GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE_SHIFT (18U)
24728#define GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE(x) \
24729 (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE_SHIFT)) & GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE_MASK)
24730#define GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE_MASK (0x80000U)
24731#define GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE_SHIFT (19U)
24732#define GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE(x) \
24733 (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE_SHIFT)) & GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE_MASK)
24734#define GPC_SLPCR_DISABLE_A53_IS_DSM_MASK (0x800000U)
24735#define GPC_SLPCR_DISABLE_A53_IS_DSM_SHIFT (23U)
24736/*! DISABLE_A53_IS_DSM
24737 * 0b0..Enable A53 isolation signal in DSM
24738 * 0b1..Disable A53 isolation signal in DSM
24739 */
24740#define GPC_SLPCR_DISABLE_A53_IS_DSM(x) \
24741 (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_DISABLE_A53_IS_DSM_SHIFT)) & GPC_SLPCR_DISABLE_A53_IS_DSM_MASK)
24742#define GPC_SLPCR_REG_BYPASS_COUNT_MASK (0x3F000000U)
24743#define GPC_SLPCR_REG_BYPASS_COUNT_SHIFT (24U)
24744/*! REG_BYPASS_COUNT
24745 * 0b000000..no delay
24746 * 0b000001..1 CKIL clock period delay
24747 * 0b111111..63 CKIL clock period delay
24748 */
24749#define GPC_SLPCR_REG_BYPASS_COUNT(x) \
24750 (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_REG_BYPASS_COUNT_SHIFT)) & GPC_SLPCR_REG_BYPASS_COUNT_MASK)
24751#define GPC_SLPCR_RBC_EN_MASK (0x40000000U)
24752#define GPC_SLPCR_RBC_EN_SHIFT (30U)
24753/*! RBC_EN
24754 * 0b0..REG_BYPASS_COUNTER disabled
24755 * 0b1..REG_BYPASS_COUNTER enabled
24756 */
24757#define GPC_SLPCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_RBC_EN_SHIFT)) & GPC_SLPCR_RBC_EN_MASK)
24758#define GPC_SLPCR_EN_DSM_MASK (0x80000000U)
24759#define GPC_SLPCR_EN_DSM_SHIFT (31U)
24760/*! EN_DSM
24761 * 0b0..DSM disabled
24762 * 0b1..DSM enabled
24763 */
24764#define GPC_SLPCR_EN_DSM(x) (((uint32_t)(((uint32_t)(x)) << GPC_SLPCR_EN_DSM_SHIFT)) & GPC_SLPCR_EN_DSM_MASK)
24765/*! @} */
24766
24767/*! @name MST_CPU_MAPPING - MASTER LPM Handshake */
24768/*! @{ */
24769#define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_MASK (0x1U)
24770#define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_SHIFT (0U)
24771/*! MST0_CPU_MAPPING - MASTER0 CPU Mapping
24772 * 0b0..GPC will not send out power off requirement
24773 * 0b1..GPC will send out power off requirement
24774 */
24775#define GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING(x) \
24776 (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_SHIFT)) & \
24777 GPC_MST_CPU_MAPPING_MST0_CPU_MAPPING_MASK)
24778#define GPC_MST_CPU_MAPPING_MST1_CPU_MAPPING_MASK (0x2U)
24779#define GPC_MST_CPU_MAPPING_MST1_CPU_MAPPING_SHIFT (1U)
24780/*! MST1_CPU_MAPPING - MASTER0 CPU Mapping
24781 * 0b0..GPC will not send out power off requirement
24782 * 0b1..GPC will send out power off requirement
24783 */
24784#define GPC_MST_CPU_MAPPING_MST1_CPU_MAPPING(x) \
24785 (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MST1_CPU_MAPPING_SHIFT)) & \
24786 GPC_MST_CPU_MAPPING_MST1_CPU_MAPPING_MASK)
24787#define GPC_MST_CPU_MAPPING_MST2_CPU_MAPPING_MASK (0x4U)
24788#define GPC_MST_CPU_MAPPING_MST2_CPU_MAPPING_SHIFT (2U)
24789/*! MST2_CPU_MAPPING - MASTER2 CPU Mapping
24790 * 0b0..GPC will not send out power off requirement
24791 * 0b1..GPC will send out power off requirement
24792 */
24793#define GPC_MST_CPU_MAPPING_MST2_CPU_MAPPING(x) \
24794 (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MST2_CPU_MAPPING_SHIFT)) & \
24795 GPC_MST_CPU_MAPPING_MST2_CPU_MAPPING_MASK)
24796#define GPC_MST_CPU_MAPPING_MST3_CPU_MAPPING_MASK (0x8U)
24797#define GPC_MST_CPU_MAPPING_MST3_CPU_MAPPING_SHIFT (3U)
24798/*! MST3_CPU_MAPPING - MASTER3 CPU Mapping
24799 * 0b0..GPC will not send out power off requirement
24800 * 0b1..GPC will send out power off requirement
24801 */
24802#define GPC_MST_CPU_MAPPING_MST3_CPU_MAPPING(x) \
24803 (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MST3_CPU_MAPPING_SHIFT)) & \
24804 GPC_MST_CPU_MAPPING_MST3_CPU_MAPPING_MASK)
24805#define GPC_MST_CPU_MAPPING_MST4_CPU_MAPPING_MASK (0x10U)
24806#define GPC_MST_CPU_MAPPING_MST4_CPU_MAPPING_SHIFT (4U)
24807/*! MST4_CPU_MAPPING - MASTER4 CPU Mapping
24808 * 0b0..GPC will not send out power off requirement
24809 * 0b1..GPC will send out power off requirement
24810 */
24811#define GPC_MST_CPU_MAPPING_MST4_CPU_MAPPING(x) \
24812 (((uint32_t)(((uint32_t)(x)) << GPC_MST_CPU_MAPPING_MST4_CPU_MAPPING_SHIFT)) & \
24813 GPC_MST_CPU_MAPPING_MST4_CPU_MAPPING_MASK)
24814/*! @} */
24815
24816/*! @name MLPCR - Memory low power control register */
24817/*! @{ */
24818#define GPC_MLPCR_MEMLP_CTL_DIS_MASK (0x1U)
24819#define GPC_MLPCR_MEMLP_CTL_DIS_SHIFT (0U)
24820/*! MEMLP_CTL_DIS
24821 * 0b0..Enable RAM low power control
24822 * 0b1..Disable RAM low power control
24823 */
24824#define GPC_MLPCR_MEMLP_CTL_DIS(x) \
24825 (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_CTL_DIS_SHIFT)) & GPC_MLPCR_MEMLP_CTL_DIS_MASK)
24826#define GPC_MLPCR_MEMLP_RET_SEL_MASK (0x2U)
24827#define GPC_MLPCR_MEMLP_RET_SEL_SHIFT (1U)
24828/*! MEMLP_RET_SEL
24829 * 0b0..retention mode 2
24830 * 0b1..retention mode 1
24831 */
24832#define GPC_MLPCR_MEMLP_RET_SEL(x) \
24833 (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_RET_SEL_SHIFT)) & GPC_MLPCR_MEMLP_RET_SEL_MASK)
24834#define GPC_MLPCR_ROMLP_PDN_DIS_MASK (0x4U)
24835#define GPC_MLPCR_ROMLP_PDN_DIS_SHIFT (2U)
24836/*! ROMLP_PDN_DIS
24837 * 0b0..Enable ROM shut down control(should also enable RAM low power control);
24838 * 0b1..Disable ROM shut down control
24839 */
24840#define GPC_MLPCR_ROMLP_PDN_DIS(x) \
24841 (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_ROMLP_PDN_DIS_SHIFT)) & GPC_MLPCR_ROMLP_PDN_DIS_MASK)
24842#define GPC_MLPCR_MEMLP_ENT_CNT_MASK (0xFF00U)
24843#define GPC_MLPCR_MEMLP_ENT_CNT_SHIFT (8U)
24844#define GPC_MLPCR_MEMLP_ENT_CNT(x) \
24845 (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_ENT_CNT_SHIFT)) & GPC_MLPCR_MEMLP_ENT_CNT_MASK)
24846#define GPC_MLPCR_MEM_EXT_CNT_MASK (0xFF0000U)
24847#define GPC_MLPCR_MEM_EXT_CNT_SHIFT (16U)
24848#define GPC_MLPCR_MEM_EXT_CNT(x) \
24849 (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEM_EXT_CNT_SHIFT)) & GPC_MLPCR_MEM_EXT_CNT_MASK)
24850#define GPC_MLPCR_MEMLP_RET_PGEN_MASK (0xFF000000U)
24851#define GPC_MLPCR_MEMLP_RET_PGEN_SHIFT (24U)
24852#define GPC_MLPCR_MEMLP_RET_PGEN(x) \
24853 (((uint32_t)(((uint32_t)(x)) << GPC_MLPCR_MEMLP_RET_PGEN_SHIFT)) & GPC_MLPCR_MEMLP_RET_PGEN_MASK)
24854/*! @} */
24855
24856/*! @name PGC_ACK_SEL_A53 - PGC acknowledge signal selection of A53 platform */
24857/*! @{ */
24858#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_MASK (0x1U)
24859#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_SHIFT (0U)
24860#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK(x) \
24861 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_SHIFT)) & \
24862 GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PDN_ACK_MASK)
24863#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_MASK (0x2U)
24864#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_SHIFT (1U)
24865#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK(x) \
24866 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_SHIFT)) & \
24867 GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PDN_ACK_MASK)
24868#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_MASK (0x4U)
24869#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_SHIFT (2U)
24870#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK(x) \
24871 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_SHIFT)) & \
24872 GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PDN_ACK_MASK)
24873#define GPC_PGC_ACK_SEL_A53_NOC_PGC_PDN_ACK_MASK (0x8U)
24874#define GPC_PGC_ACK_SEL_A53_NOC_PGC_PDN_ACK_SHIFT (3U)
24875#define GPC_PGC_ACK_SEL_A53_NOC_PGC_PDN_ACK(x) \
24876 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_NOC_PGC_PDN_ACK_SHIFT)) & \
24877 GPC_PGC_ACK_SEL_A53_NOC_PGC_PDN_ACK_MASK)
24878#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_MASK (0x2000U)
24879#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_SHIFT (13U)
24880#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK(x) \
24881 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_SHIFT)) & \
24882 GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PDN_ACK_MASK)
24883#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_MASK (0x4000U)
24884#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_SHIFT (14U)
24885#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK(x) \
24886 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_SHIFT)) & \
24887 GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PDN_ACK_MASK)
24888#define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_MASK (0x8000U)
24889#define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_SHIFT (15U)
24890#define GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK(x) \
24891 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_SHIFT)) & \
24892 GPC_PGC_ACK_SEL_A53_A53_PGC_PDN_ACK_MASK)
24893#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_MASK (0x10000U)
24894#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_SHIFT (16U)
24895#define GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK(x) \
24896 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_SHIFT)) & \
24897 GPC_PGC_ACK_SEL_A53_A53_C0_PGC_PUP_ACK_MASK)
24898#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_MASK (0x20000U)
24899#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_SHIFT (17U)
24900#define GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK(x) \
24901 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_SHIFT)) & \
24902 GPC_PGC_ACK_SEL_A53_A53_C1_PGC_PUP_ACK_MASK)
24903#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_MASK (0x40000U)
24904#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_SHIFT (18U)
24905#define GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK(x) \
24906 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_SHIFT)) & \
24907 GPC_PGC_ACK_SEL_A53_A53_PLAT_PGC_PUP_ACK_MASK)
24908#define GPC_PGC_ACK_SEL_A53_NOC_PGC_PUP_ACK_MASK (0x80000U)
24909#define GPC_PGC_ACK_SEL_A53_NOC_PGC_PUP_ACK_SHIFT (19U)
24910#define GPC_PGC_ACK_SEL_A53_NOC_PGC_PUP_ACK(x) \
24911 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_NOC_PGC_PUP_ACK_SHIFT)) & \
24912 GPC_PGC_ACK_SEL_A53_NOC_PGC_PUP_ACK_MASK)
24913#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_MASK (0x20000000U)
24914#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_SHIFT (29U)
24915#define GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK(x) \
24916 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_SHIFT)) & \
24917 GPC_PGC_ACK_SEL_A53_A53_C2_PGC_PUP_ACK_MASK)
24918#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_MASK (0x40000000U)
24919#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_SHIFT (30U)
24920#define GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK(x) \
24921 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_SHIFT)) & \
24922 GPC_PGC_ACK_SEL_A53_A53_C3_PGC_PUP_ACK_MASK)
24923#define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_MASK (0x80000000U)
24924#define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_SHIFT (31U)
24925#define GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK(x) \
24926 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_SHIFT)) & \
24927 GPC_PGC_ACK_SEL_A53_A53_PGC_PUP_ACK_MASK)
24928/*! @} */
24929
24930/*! @name PGC_ACK_SEL_M7 - PGC acknowledge signal selection of M7 platform */
24931/*! @{ */
24932#define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK_MASK (0x1U)
24933#define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK_SHIFT (0U)
24934#define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK(x) \
24935 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK_SHIFT)) & \
24936 GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK_MASK)
24937#define GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK_MASK (0x2U)
24938#define GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK_SHIFT (1U)
24939#define GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK(x) \
24940 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK_SHIFT)) & \
24941 GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK_MASK)
24942#define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK_MASK (0x8000U)
24943#define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK_SHIFT (15U)
24944#define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK(x) \
24945 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK_SHIFT)) & \
24946 GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK_MASK)
24947#define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK_MASK (0x10000U)
24948#define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK_SHIFT (16U)
24949#define GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK(x) \
24950 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK_SHIFT)) & \
24951 GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK_MASK)
24952#define GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK_MASK (0x20000U)
24953#define GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK_SHIFT (17U)
24954#define GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK(x) \
24955 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK_SHIFT)) & \
24956 GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK_MASK)
24957#define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK_MASK (0x80000000U)
24958#define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK_SHIFT (31U)
24959#define GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK(x) \
24960 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK_SHIFT)) & \
24961 GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK_MASK)
24962/*! @} */
24963
24964/*! @name MISC - GPC Miscellaneous register */
24965/*! @{ */
24966#define GPC_MISC_M7_SLEEP_HOLD_REQ_B_MASK (0x1U)
24967#define GPC_MISC_M7_SLEEP_HOLD_REQ_B_SHIFT (0U)
24968/*! M7_SLEEP_HOLD_REQ_B
24969 * 0b0..Hold M7 platform in sleep mode. This bit is a software control bit to M7 platform.
24970 * 0b1..Don't hold M7 platform in sleep mode.
24971 */
24972#define GPC_MISC_M7_SLEEP_HOLD_REQ_B(x) \
24973 (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M7_SLEEP_HOLD_REQ_B_SHIFT)) & GPC_MISC_M7_SLEEP_HOLD_REQ_B_MASK)
24974#define GPC_MISC_A53_SLEEP_HOLD_REQ_B_MASK (0x2U)
24975#define GPC_MISC_A53_SLEEP_HOLD_REQ_B_SHIFT (1U)
24976/*! A53_SLEEP_HOLD_REQ_B
24977 * 0b0..Hold A53 platform in sleep mode. This bit is a software control bit to A53 platform.
24978 * 0b1..Don't hold A53 platform in sleep mode.
24979 */
24980#define GPC_MISC_A53_SLEEP_HOLD_REQ_B(x) \
24981 (((uint32_t)(((uint32_t)(x)) << GPC_MISC_A53_SLEEP_HOLD_REQ_B_SHIFT)) & GPC_MISC_A53_SLEEP_HOLD_REQ_B_MASK)
24982#define GPC_MISC_GPC_IRQ_MASK_MASK (0x20U)
24983#define GPC_MISC_GPC_IRQ_MASK_SHIFT (5U)
24984/*! GPC_IRQ_MASK
24985 * 0b0..Not masked
24986 * 0b1..Interrupt / event is masked
24987 */
24988#define GPC_MISC_GPC_IRQ_MASK(x) \
24989 (((uint32_t)(((uint32_t)(x)) << GPC_MISC_GPC_IRQ_MASK_SHIFT)) & GPC_MISC_GPC_IRQ_MASK_MASK)
24990#define GPC_MISC_M7_PDN_REQ_MASK_MASK (0x100U)
24991#define GPC_MISC_M7_PDN_REQ_MASK_SHIFT (8U)
24992/*! M7_PDN_REQ_MASK
24993 * 0b0..M7 power down request to virtual M7 PGC will be masked.
24994 * 0b1..M7 power down request to virtual M7 PGC will not be masked. Set this bit to 1'b1 when M7 virtual PGC is used.
24995 */
24996#define GPC_MISC_M7_PDN_REQ_MASK(x) \
24997 (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M7_PDN_REQ_MASK_SHIFT)) & GPC_MISC_M7_PDN_REQ_MASK_MASK)
24998#define GPC_MISC_A53_BYPASS_PUP_MASK_MASK (0x1000000U)
24999#define GPC_MISC_A53_BYPASS_PUP_MASK_SHIFT (24U)
25000#define GPC_MISC_A53_BYPASS_PUP_MASK(x) \
25001 (((uint32_t)(((uint32_t)(x)) << GPC_MISC_A53_BYPASS_PUP_MASK_SHIFT)) & GPC_MISC_A53_BYPASS_PUP_MASK_MASK)
25002#define GPC_MISC_M7_BYPASS_PUP_MASK_MASK (0x2000000U)
25003#define GPC_MISC_M7_BYPASS_PUP_MASK_SHIFT (25U)
25004#define GPC_MISC_M7_BYPASS_PUP_MASK(x) \
25005 (((uint32_t)(((uint32_t)(x)) << GPC_MISC_M7_BYPASS_PUP_MASK_SHIFT)) & GPC_MISC_M7_BYPASS_PUP_MASK_MASK)
25006/*! @} */
25007
25008/*! @name IMR_CORE0_A53 - IRQ masking register 1 of A53 core0..IRQ masking register 4 of A53 core0 */
25009/*! @{ */
25010#define GPC_IMR_CORE0_A53_IMR1_CORE0_A53_MASK (0xFFFFFFFFU)
25011#define GPC_IMR_CORE0_A53_IMR1_CORE0_A53_SHIFT (0U)
25012/*! IMR1_CORE0_A53
25013 * 0b00000000000000000000000000000000..IRQ not masked
25014 * 0b00000000000000000000000000000001..IRQ masked
25015 */
25016#define GPC_IMR_CORE0_A53_IMR1_CORE0_A53(x) \
25017 (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR1_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR1_CORE0_A53_MASK)
25018#define GPC_IMR_CORE0_A53_IMR2_CORE0_A53_MASK (0xFFFFFFFFU)
25019#define GPC_IMR_CORE0_A53_IMR2_CORE0_A53_SHIFT (0U)
25020/*! IMR2_CORE0_A53
25021 * 0b00000000000000000000000000000000..IRQ not masked
25022 * 0b00000000000000000000000000000001..IRQ masked
25023 */
25024#define GPC_IMR_CORE0_A53_IMR2_CORE0_A53(x) \
25025 (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR2_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR2_CORE0_A53_MASK)
25026#define GPC_IMR_CORE0_A53_IMR3_CORE0_A53_MASK (0xFFFFFFFFU)
25027#define GPC_IMR_CORE0_A53_IMR3_CORE0_A53_SHIFT (0U)
25028/*! IMR3_CORE0_A53
25029 * 0b00000000000000000000000000000000..IRQ not masked
25030 * 0b00000000000000000000000000000001..IRQ masked
25031 */
25032#define GPC_IMR_CORE0_A53_IMR3_CORE0_A53(x) \
25033 (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR3_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR3_CORE0_A53_MASK)
25034#define GPC_IMR_CORE0_A53_IMR4_CORE0_A53_MASK (0xFFFFFFFFU)
25035#define GPC_IMR_CORE0_A53_IMR4_CORE0_A53_SHIFT (0U)
25036/*! IMR4_CORE0_A53
25037 * 0b00000000000000000000000000000000..IRQ not masked
25038 * 0b00000000000000000000000000000001..IRQ masked
25039 */
25040#define GPC_IMR_CORE0_A53_IMR4_CORE0_A53(x) \
25041 (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE0_A53_IMR4_CORE0_A53_SHIFT)) & GPC_IMR_CORE0_A53_IMR4_CORE0_A53_MASK)
25042/*! @} */
25043
25044/* The count of GPC_IMR_CORE0_A53 */
25045#define GPC_IMR_CORE0_A53_COUNT (4U)
25046
25047/*! @name IMR_CORE1_A53 - IRQ masking register 1 of A53 core1..IRQ masking register 4 of A53 core1 */
25048/*! @{ */
25049#define GPC_IMR_CORE1_A53_IMR1_CORE1_A53_MASK (0xFFFFFFFFU)
25050#define GPC_IMR_CORE1_A53_IMR1_CORE1_A53_SHIFT (0U)
25051/*! IMR1_CORE1_A53
25052 * 0b00000000000000000000000000000000..IRQ not masked
25053 * 0b00000000000000000000000000000001..IRQ masked
25054 */
25055#define GPC_IMR_CORE1_A53_IMR1_CORE1_A53(x) \
25056 (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR1_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR1_CORE1_A53_MASK)
25057#define GPC_IMR_CORE1_A53_IMR2_CORE1_A53_MASK (0xFFFFFFFFU)
25058#define GPC_IMR_CORE1_A53_IMR2_CORE1_A53_SHIFT (0U)
25059/*! IMR2_CORE1_A53
25060 * 0b00000000000000000000000000000000..IRQ not masked
25061 * 0b00000000000000000000000000000001..IRQ masked
25062 */
25063#define GPC_IMR_CORE1_A53_IMR2_CORE1_A53(x) \
25064 (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR2_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR2_CORE1_A53_MASK)
25065#define GPC_IMR_CORE1_A53_IMR3_CORE1_A53_MASK (0xFFFFFFFFU)
25066#define GPC_IMR_CORE1_A53_IMR3_CORE1_A53_SHIFT (0U)
25067/*! IMR3_CORE1_A53
25068 * 0b00000000000000000000000000000000..IRQ not masked
25069 * 0b00000000000000000000000000000001..IRQ masked
25070 */
25071#define GPC_IMR_CORE1_A53_IMR3_CORE1_A53(x) \
25072 (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR3_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR3_CORE1_A53_MASK)
25073#define GPC_IMR_CORE1_A53_IMR4_CORE1_A53_MASK (0xFFFFFFFFU)
25074#define GPC_IMR_CORE1_A53_IMR4_CORE1_A53_SHIFT (0U)
25075/*! IMR4_CORE1_A53
25076 * 0b00000000000000000000000000000000..IRQ not masked
25077 * 0b00000000000000000000000000000001..IRQ masked
25078 */
25079#define GPC_IMR_CORE1_A53_IMR4_CORE1_A53(x) \
25080 (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE1_A53_IMR4_CORE1_A53_SHIFT)) & GPC_IMR_CORE1_A53_IMR4_CORE1_A53_MASK)
25081/*! @} */
25082
25083/* The count of GPC_IMR_CORE1_A53 */
25084#define GPC_IMR_CORE1_A53_COUNT (4U)
25085
25086/*! @name IMR_M7 - IRQ masking register 1 of M7..IRQ masking register 4 of M7 */
25087/*! @{ */
25088#define GPC_IMR_M7_IMR1_M7_MASK (0xFFFFFFFFU)
25089#define GPC_IMR_M7_IMR1_M7_SHIFT (0U)
25090/*! IMR1_M7
25091 * 0b00000000000000000000000000000000..IRQ not masked
25092 * 0b00000000000000000000000000000001..IRQ masked
25093 */
25094#define GPC_IMR_M7_IMR1_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M7_IMR1_M7_SHIFT)) & GPC_IMR_M7_IMR1_M7_MASK)
25095#define GPC_IMR_M7_IMR2_M7_MASK (0xFFFFFFFFU)
25096#define GPC_IMR_M7_IMR2_M7_SHIFT (0U)
25097/*! IMR2_M7
25098 * 0b00000000000000000000000000000000..IRQ not masked
25099 * 0b00000000000000000000000000000001..IRQ masked
25100 */
25101#define GPC_IMR_M7_IMR2_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M7_IMR2_M7_SHIFT)) & GPC_IMR_M7_IMR2_M7_MASK)
25102#define GPC_IMR_M7_IMR3_M7_MASK (0xFFFFFFFFU)
25103#define GPC_IMR_M7_IMR3_M7_SHIFT (0U)
25104/*! IMR3_M7
25105 * 0b00000000000000000000000000000000..IRQ not masked
25106 * 0b00000000000000000000000000000001..IRQ masked
25107 */
25108#define GPC_IMR_M7_IMR3_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M7_IMR3_M7_SHIFT)) & GPC_IMR_M7_IMR3_M7_MASK)
25109#define GPC_IMR_M7_IMR4_M7_MASK (0xFFFFFFFFU)
25110#define GPC_IMR_M7_IMR4_M7_SHIFT (0U)
25111/*! IMR4_M7
25112 * 0b00000000000000000000000000000000..IRQ not masked
25113 * 0b00000000000000000000000000000001..IRQ masked
25114 */
25115#define GPC_IMR_M7_IMR4_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_IMR_M7_IMR4_M7_SHIFT)) & GPC_IMR_M7_IMR4_M7_MASK)
25116/*! @} */
25117
25118/* The count of GPC_IMR_M7 */
25119#define GPC_IMR_M7_COUNT (4U)
25120
25121/*! @name ISR_A53 - IRQ status register 1 of A53..IRQ status register 4 of A53 */
25122/*! @{ */
25123#define GPC_ISR_A53_ISR1_A53_MASK (0xFFFFFFFFU)
25124#define GPC_ISR_A53_ISR1_A53_SHIFT (0U)
25125#define GPC_ISR_A53_ISR1_A53(x) \
25126 (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR1_A53_SHIFT)) & GPC_ISR_A53_ISR1_A53_MASK)
25127#define GPC_ISR_A53_ISR2_A53_MASK (0xFFFFFFFFU)
25128#define GPC_ISR_A53_ISR2_A53_SHIFT (0U)
25129#define GPC_ISR_A53_ISR2_A53(x) \
25130 (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR2_A53_SHIFT)) & GPC_ISR_A53_ISR2_A53_MASK)
25131#define GPC_ISR_A53_ISR3_A53_MASK (0xFFFFFFFFU)
25132#define GPC_ISR_A53_ISR3_A53_SHIFT (0U)
25133#define GPC_ISR_A53_ISR3_A53(x) \
25134 (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR3_A53_SHIFT)) & GPC_ISR_A53_ISR3_A53_MASK)
25135#define GPC_ISR_A53_ISR4_A53_MASK (0xFFFFFFFFU)
25136#define GPC_ISR_A53_ISR4_A53_SHIFT (0U)
25137#define GPC_ISR_A53_ISR4_A53(x) \
25138 (((uint32_t)(((uint32_t)(x)) << GPC_ISR_A53_ISR4_A53_SHIFT)) & GPC_ISR_A53_ISR4_A53_MASK)
25139/*! @} */
25140
25141/* The count of GPC_ISR_A53 */
25142#define GPC_ISR_A53_COUNT (4U)
25143
25144/*! @name ISR_M7 - IRQ status register 1 of M7..IRQ status register 4 of M7 */
25145/*! @{ */
25146#define GPC_ISR_M7_ISR1_M7_MASK (0xFFFFFFFFU)
25147#define GPC_ISR_M7_ISR1_M7_SHIFT (0U)
25148#define GPC_ISR_M7_ISR1_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M7_ISR1_M7_SHIFT)) & GPC_ISR_M7_ISR1_M7_MASK)
25149#define GPC_ISR_M7_ISR2_M7_MASK (0xFFFFFFFFU)
25150#define GPC_ISR_M7_ISR2_M7_SHIFT (0U)
25151#define GPC_ISR_M7_ISR2_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M7_ISR2_M7_SHIFT)) & GPC_ISR_M7_ISR2_M7_MASK)
25152#define GPC_ISR_M7_ISR3_M7_MASK (0xFFFFFFFFU)
25153#define GPC_ISR_M7_ISR3_M7_SHIFT (0U)
25154#define GPC_ISR_M7_ISR3_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M7_ISR3_M7_SHIFT)) & GPC_ISR_M7_ISR3_M7_MASK)
25155#define GPC_ISR_M7_ISR4_M7_MASK (0xFFFFFFFFU)
25156#define GPC_ISR_M7_ISR4_M7_SHIFT (0U)
25157#define GPC_ISR_M7_ISR4_M7(x) (((uint32_t)(((uint32_t)(x)) << GPC_ISR_M7_ISR4_M7_SHIFT)) & GPC_ISR_M7_ISR4_M7_MASK)
25158/*! @} */
25159
25160/* The count of GPC_ISR_M7 */
25161#define GPC_ISR_M7_COUNT (4U)
25162
25163/*! @name SLT0_CFG - Slot configure register for CPUs */
25164/*! @{ */
25165#define GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
25166#define GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
25167#define GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \
25168 (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25169 GPC_SLT0_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
25170#define GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
25171#define GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
25172#define GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \
25173 (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25174 GPC_SLT0_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
25175#define GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
25176#define GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
25177#define GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \
25178 (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25179 GPC_SLT0_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
25180#define GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
25181#define GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
25182#define GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \
25183 (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25184 GPC_SLT0_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
25185#define GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
25186#define GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
25187#define GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \
25188 (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25189 GPC_SLT0_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
25190#define GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
25191#define GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
25192#define GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \
25193 (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25194 GPC_SLT0_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
25195#define GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
25196#define GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
25197#define GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \
25198 (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25199 GPC_SLT0_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
25200#define GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
25201#define GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
25202#define GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \
25203 (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25204 GPC_SLT0_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
25205#define GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
25206#define GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
25207#define GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL(x) \
25208 (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_SCU_PDN_SLOT_CONTROL_MASK)
25209#define GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
25210#define GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
25211#define GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL(x) \
25212 (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_SCU_PUP_SLOT_CONTROL_MASK)
25213#define GPC_SLT0_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U)
25214#define GPC_SLT0_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U)
25215#define GPC_SLT0_CFG_NOC_PDN_SLOT_CONTROL(x) \
25216 (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_NOC_PDN_SLOT_CONTROL_MASK)
25217#define GPC_SLT0_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U)
25218#define GPC_SLT0_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U)
25219#define GPC_SLT0_CFG_NOC_PUP_SLOT_CONTROL(x) \
25220 (((uint32_t)(((uint32_t)(x)) << GPC_SLT0_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT0_CFG_NOC_PUP_SLOT_CONTROL_MASK)
25221/*! @} */
25222
25223/*! @name SLT1_CFG - Slot configure register for CPUs */
25224/*! @{ */
25225#define GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
25226#define GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
25227#define GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \
25228 (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25229 GPC_SLT1_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
25230#define GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
25231#define GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
25232#define GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \
25233 (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25234 GPC_SLT1_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
25235#define GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
25236#define GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
25237#define GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \
25238 (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25239 GPC_SLT1_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
25240#define GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
25241#define GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
25242#define GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \
25243 (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25244 GPC_SLT1_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
25245#define GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
25246#define GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
25247#define GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \
25248 (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25249 GPC_SLT1_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
25250#define GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
25251#define GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
25252#define GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \
25253 (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25254 GPC_SLT1_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
25255#define GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
25256#define GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
25257#define GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \
25258 (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25259 GPC_SLT1_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
25260#define GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
25261#define GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
25262#define GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \
25263 (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25264 GPC_SLT1_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
25265#define GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
25266#define GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
25267#define GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL(x) \
25268 (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_SCU_PDN_SLOT_CONTROL_MASK)
25269#define GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
25270#define GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
25271#define GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL(x) \
25272 (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_SCU_PUP_SLOT_CONTROL_MASK)
25273#define GPC_SLT1_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U)
25274#define GPC_SLT1_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U)
25275#define GPC_SLT1_CFG_NOC_PDN_SLOT_CONTROL(x) \
25276 (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_NOC_PDN_SLOT_CONTROL_MASK)
25277#define GPC_SLT1_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U)
25278#define GPC_SLT1_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U)
25279#define GPC_SLT1_CFG_NOC_PUP_SLOT_CONTROL(x) \
25280 (((uint32_t)(((uint32_t)(x)) << GPC_SLT1_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT1_CFG_NOC_PUP_SLOT_CONTROL_MASK)
25281/*! @} */
25282
25283/*! @name SLT2_CFG - Slot configure register for CPUs */
25284/*! @{ */
25285#define GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
25286#define GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
25287#define GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \
25288 (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25289 GPC_SLT2_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
25290#define GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
25291#define GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
25292#define GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \
25293 (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25294 GPC_SLT2_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
25295#define GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
25296#define GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
25297#define GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \
25298 (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25299 GPC_SLT2_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
25300#define GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
25301#define GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
25302#define GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \
25303 (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25304 GPC_SLT2_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
25305#define GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
25306#define GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
25307#define GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \
25308 (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25309 GPC_SLT2_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
25310#define GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
25311#define GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
25312#define GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \
25313 (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25314 GPC_SLT2_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
25315#define GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
25316#define GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
25317#define GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \
25318 (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25319 GPC_SLT2_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
25320#define GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
25321#define GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
25322#define GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \
25323 (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25324 GPC_SLT2_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
25325#define GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
25326#define GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
25327#define GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL(x) \
25328 (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_SCU_PDN_SLOT_CONTROL_MASK)
25329#define GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
25330#define GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
25331#define GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL(x) \
25332 (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_SCU_PUP_SLOT_CONTROL_MASK)
25333#define GPC_SLT2_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U)
25334#define GPC_SLT2_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U)
25335#define GPC_SLT2_CFG_NOC_PDN_SLOT_CONTROL(x) \
25336 (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_NOC_PDN_SLOT_CONTROL_MASK)
25337#define GPC_SLT2_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U)
25338#define GPC_SLT2_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U)
25339#define GPC_SLT2_CFG_NOC_PUP_SLOT_CONTROL(x) \
25340 (((uint32_t)(((uint32_t)(x)) << GPC_SLT2_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT2_CFG_NOC_PUP_SLOT_CONTROL_MASK)
25341/*! @} */
25342
25343/*! @name SLT3_CFG - Slot configure register for CPUs */
25344/*! @{ */
25345#define GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
25346#define GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
25347#define GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \
25348 (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25349 GPC_SLT3_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
25350#define GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
25351#define GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
25352#define GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \
25353 (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25354 GPC_SLT3_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
25355#define GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
25356#define GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
25357#define GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \
25358 (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25359 GPC_SLT3_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
25360#define GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
25361#define GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
25362#define GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \
25363 (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25364 GPC_SLT3_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
25365#define GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
25366#define GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
25367#define GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \
25368 (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25369 GPC_SLT3_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
25370#define GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
25371#define GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
25372#define GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \
25373 (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25374 GPC_SLT3_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
25375#define GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
25376#define GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
25377#define GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \
25378 (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25379 GPC_SLT3_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
25380#define GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
25381#define GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
25382#define GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \
25383 (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25384 GPC_SLT3_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
25385#define GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
25386#define GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
25387#define GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL(x) \
25388 (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_SCU_PDN_SLOT_CONTROL_MASK)
25389#define GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
25390#define GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
25391#define GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL(x) \
25392 (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_SCU_PUP_SLOT_CONTROL_MASK)
25393#define GPC_SLT3_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U)
25394#define GPC_SLT3_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U)
25395#define GPC_SLT3_CFG_NOC_PDN_SLOT_CONTROL(x) \
25396 (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_NOC_PDN_SLOT_CONTROL_MASK)
25397#define GPC_SLT3_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U)
25398#define GPC_SLT3_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U)
25399#define GPC_SLT3_CFG_NOC_PUP_SLOT_CONTROL(x) \
25400 (((uint32_t)(((uint32_t)(x)) << GPC_SLT3_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT3_CFG_NOC_PUP_SLOT_CONTROL_MASK)
25401/*! @} */
25402
25403/*! @name SLT4_CFG - Slot configure register for CPUs */
25404/*! @{ */
25405#define GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
25406#define GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
25407#define GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \
25408 (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25409 GPC_SLT4_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
25410#define GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
25411#define GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
25412#define GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \
25413 (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25414 GPC_SLT4_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
25415#define GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
25416#define GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
25417#define GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \
25418 (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25419 GPC_SLT4_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
25420#define GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
25421#define GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
25422#define GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \
25423 (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25424 GPC_SLT4_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
25425#define GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
25426#define GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
25427#define GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \
25428 (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25429 GPC_SLT4_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
25430#define GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
25431#define GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
25432#define GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \
25433 (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25434 GPC_SLT4_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
25435#define GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
25436#define GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
25437#define GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \
25438 (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25439 GPC_SLT4_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
25440#define GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
25441#define GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
25442#define GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \
25443 (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25444 GPC_SLT4_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
25445#define GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
25446#define GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
25447#define GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL(x) \
25448 (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_SCU_PDN_SLOT_CONTROL_MASK)
25449#define GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
25450#define GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
25451#define GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL(x) \
25452 (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_SCU_PUP_SLOT_CONTROL_MASK)
25453#define GPC_SLT4_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U)
25454#define GPC_SLT4_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U)
25455#define GPC_SLT4_CFG_NOC_PDN_SLOT_CONTROL(x) \
25456 (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_NOC_PDN_SLOT_CONTROL_MASK)
25457#define GPC_SLT4_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U)
25458#define GPC_SLT4_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U)
25459#define GPC_SLT4_CFG_NOC_PUP_SLOT_CONTROL(x) \
25460 (((uint32_t)(((uint32_t)(x)) << GPC_SLT4_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT4_CFG_NOC_PUP_SLOT_CONTROL_MASK)
25461/*! @} */
25462
25463/*! @name SLT5_CFG - Slot configure register for CPUs */
25464/*! @{ */
25465#define GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
25466#define GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
25467#define GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \
25468 (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25469 GPC_SLT5_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
25470#define GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
25471#define GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
25472#define GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \
25473 (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25474 GPC_SLT5_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
25475#define GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
25476#define GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
25477#define GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \
25478 (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25479 GPC_SLT5_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
25480#define GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
25481#define GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
25482#define GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \
25483 (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25484 GPC_SLT5_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
25485#define GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
25486#define GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
25487#define GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \
25488 (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25489 GPC_SLT5_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
25490#define GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
25491#define GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
25492#define GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \
25493 (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25494 GPC_SLT5_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
25495#define GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
25496#define GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
25497#define GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \
25498 (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25499 GPC_SLT5_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
25500#define GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
25501#define GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
25502#define GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \
25503 (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25504 GPC_SLT5_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
25505#define GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
25506#define GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
25507#define GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL(x) \
25508 (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_SCU_PDN_SLOT_CONTROL_MASK)
25509#define GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
25510#define GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
25511#define GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL(x) \
25512 (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_SCU_PUP_SLOT_CONTROL_MASK)
25513#define GPC_SLT5_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U)
25514#define GPC_SLT5_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U)
25515#define GPC_SLT5_CFG_NOC_PDN_SLOT_CONTROL(x) \
25516 (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_NOC_PDN_SLOT_CONTROL_MASK)
25517#define GPC_SLT5_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U)
25518#define GPC_SLT5_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U)
25519#define GPC_SLT5_CFG_NOC_PUP_SLOT_CONTROL(x) \
25520 (((uint32_t)(((uint32_t)(x)) << GPC_SLT5_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT5_CFG_NOC_PUP_SLOT_CONTROL_MASK)
25521/*! @} */
25522
25523/*! @name SLT6_CFG - Slot configure register for CPUs */
25524/*! @{ */
25525#define GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
25526#define GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
25527#define GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \
25528 (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25529 GPC_SLT6_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
25530#define GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
25531#define GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
25532#define GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \
25533 (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25534 GPC_SLT6_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
25535#define GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
25536#define GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
25537#define GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \
25538 (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25539 GPC_SLT6_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
25540#define GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
25541#define GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
25542#define GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \
25543 (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25544 GPC_SLT6_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
25545#define GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
25546#define GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
25547#define GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \
25548 (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25549 GPC_SLT6_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
25550#define GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
25551#define GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
25552#define GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \
25553 (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25554 GPC_SLT6_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
25555#define GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
25556#define GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
25557#define GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \
25558 (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25559 GPC_SLT6_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
25560#define GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
25561#define GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
25562#define GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \
25563 (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25564 GPC_SLT6_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
25565#define GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
25566#define GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
25567#define GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL(x) \
25568 (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_SCU_PDN_SLOT_CONTROL_MASK)
25569#define GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
25570#define GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
25571#define GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL(x) \
25572 (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_SCU_PUP_SLOT_CONTROL_MASK)
25573#define GPC_SLT6_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U)
25574#define GPC_SLT6_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U)
25575#define GPC_SLT6_CFG_NOC_PDN_SLOT_CONTROL(x) \
25576 (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_NOC_PDN_SLOT_CONTROL_MASK)
25577#define GPC_SLT6_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U)
25578#define GPC_SLT6_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U)
25579#define GPC_SLT6_CFG_NOC_PUP_SLOT_CONTROL(x) \
25580 (((uint32_t)(((uint32_t)(x)) << GPC_SLT6_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT6_CFG_NOC_PUP_SLOT_CONTROL_MASK)
25581/*! @} */
25582
25583/*! @name SLT7_CFG - Slot configure register for CPUs */
25584/*! @{ */
25585#define GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
25586#define GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
25587#define GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \
25588 (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25589 GPC_SLT7_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
25590#define GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
25591#define GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
25592#define GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \
25593 (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25594 GPC_SLT7_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
25595#define GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
25596#define GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
25597#define GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \
25598 (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25599 GPC_SLT7_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
25600#define GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
25601#define GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
25602#define GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \
25603 (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25604 GPC_SLT7_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
25605#define GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
25606#define GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
25607#define GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \
25608 (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25609 GPC_SLT7_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
25610#define GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
25611#define GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
25612#define GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \
25613 (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25614 GPC_SLT7_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
25615#define GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
25616#define GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
25617#define GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \
25618 (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25619 GPC_SLT7_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
25620#define GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
25621#define GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
25622#define GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \
25623 (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25624 GPC_SLT7_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
25625#define GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
25626#define GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
25627#define GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL(x) \
25628 (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_SCU_PDN_SLOT_CONTROL_MASK)
25629#define GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
25630#define GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
25631#define GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL(x) \
25632 (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_SCU_PUP_SLOT_CONTROL_MASK)
25633#define GPC_SLT7_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U)
25634#define GPC_SLT7_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U)
25635#define GPC_SLT7_CFG_NOC_PDN_SLOT_CONTROL(x) \
25636 (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_NOC_PDN_SLOT_CONTROL_MASK)
25637#define GPC_SLT7_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U)
25638#define GPC_SLT7_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U)
25639#define GPC_SLT7_CFG_NOC_PUP_SLOT_CONTROL(x) \
25640 (((uint32_t)(((uint32_t)(x)) << GPC_SLT7_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT7_CFG_NOC_PUP_SLOT_CONTROL_MASK)
25641/*! @} */
25642
25643/*! @name SLT8_CFG - Slot configure register for CPUs */
25644/*! @{ */
25645#define GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
25646#define GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
25647#define GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \
25648 (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25649 GPC_SLT8_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
25650#define GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
25651#define GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
25652#define GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \
25653 (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25654 GPC_SLT8_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
25655#define GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
25656#define GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
25657#define GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \
25658 (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25659 GPC_SLT8_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
25660#define GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
25661#define GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
25662#define GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \
25663 (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25664 GPC_SLT8_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
25665#define GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
25666#define GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
25667#define GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \
25668 (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25669 GPC_SLT8_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
25670#define GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
25671#define GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
25672#define GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \
25673 (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25674 GPC_SLT8_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
25675#define GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
25676#define GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
25677#define GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \
25678 (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25679 GPC_SLT8_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
25680#define GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
25681#define GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
25682#define GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \
25683 (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25684 GPC_SLT8_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
25685#define GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
25686#define GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
25687#define GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL(x) \
25688 (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_SCU_PDN_SLOT_CONTROL_MASK)
25689#define GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
25690#define GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
25691#define GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL(x) \
25692 (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_SCU_PUP_SLOT_CONTROL_MASK)
25693#define GPC_SLT8_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U)
25694#define GPC_SLT8_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U)
25695#define GPC_SLT8_CFG_NOC_PDN_SLOT_CONTROL(x) \
25696 (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_NOC_PDN_SLOT_CONTROL_MASK)
25697#define GPC_SLT8_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U)
25698#define GPC_SLT8_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U)
25699#define GPC_SLT8_CFG_NOC_PUP_SLOT_CONTROL(x) \
25700 (((uint32_t)(((uint32_t)(x)) << GPC_SLT8_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT8_CFG_NOC_PUP_SLOT_CONTROL_MASK)
25701/*! @} */
25702
25703/*! @name SLT9_CFG - Slot configure register for CPUs */
25704/*! @{ */
25705#define GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
25706#define GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
25707#define GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \
25708 (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25709 GPC_SLT9_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
25710#define GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
25711#define GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
25712#define GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \
25713 (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25714 GPC_SLT9_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
25715#define GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
25716#define GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
25717#define GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \
25718 (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25719 GPC_SLT9_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
25720#define GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
25721#define GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
25722#define GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \
25723 (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25724 GPC_SLT9_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
25725#define GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
25726#define GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
25727#define GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \
25728 (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25729 GPC_SLT9_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
25730#define GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
25731#define GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
25732#define GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \
25733 (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25734 GPC_SLT9_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
25735#define GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
25736#define GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
25737#define GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \
25738 (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25739 GPC_SLT9_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
25740#define GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
25741#define GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
25742#define GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \
25743 (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25744 GPC_SLT9_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
25745#define GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
25746#define GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
25747#define GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL(x) \
25748 (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_SCU_PDN_SLOT_CONTROL_MASK)
25749#define GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
25750#define GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
25751#define GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL(x) \
25752 (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_SCU_PUP_SLOT_CONTROL_MASK)
25753#define GPC_SLT9_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U)
25754#define GPC_SLT9_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U)
25755#define GPC_SLT9_CFG_NOC_PDN_SLOT_CONTROL(x) \
25756 (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_NOC_PDN_SLOT_CONTROL_MASK)
25757#define GPC_SLT9_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U)
25758#define GPC_SLT9_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U)
25759#define GPC_SLT9_CFG_NOC_PUP_SLOT_CONTROL(x) \
25760 (((uint32_t)(((uint32_t)(x)) << GPC_SLT9_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & GPC_SLT9_CFG_NOC_PUP_SLOT_CONTROL_MASK)
25761/*! @} */
25762
25763/*! @name SLT10_CFG - Slot configure register for CPUs */
25764/*! @{ */
25765#define GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
25766#define GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
25767#define GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \
25768 (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25769 GPC_SLT10_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
25770#define GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
25771#define GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
25772#define GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \
25773 (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25774 GPC_SLT10_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
25775#define GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
25776#define GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
25777#define GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \
25778 (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25779 GPC_SLT10_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
25780#define GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
25781#define GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
25782#define GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \
25783 (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25784 GPC_SLT10_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
25785#define GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
25786#define GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
25787#define GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \
25788 (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25789 GPC_SLT10_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
25790#define GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
25791#define GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
25792#define GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \
25793 (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25794 GPC_SLT10_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
25795#define GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
25796#define GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
25797#define GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \
25798 (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25799 GPC_SLT10_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
25800#define GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
25801#define GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
25802#define GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \
25803 (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25804 GPC_SLT10_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
25805#define GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
25806#define GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
25807#define GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL(x) \
25808 (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & \
25809 GPC_SLT10_CFG_SCU_PDN_SLOT_CONTROL_MASK)
25810#define GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
25811#define GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
25812#define GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL(x) \
25813 (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & \
25814 GPC_SLT10_CFG_SCU_PUP_SLOT_CONTROL_MASK)
25815#define GPC_SLT10_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U)
25816#define GPC_SLT10_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U)
25817#define GPC_SLT10_CFG_NOC_PDN_SLOT_CONTROL(x) \
25818 (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & \
25819 GPC_SLT10_CFG_NOC_PDN_SLOT_CONTROL_MASK)
25820#define GPC_SLT10_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U)
25821#define GPC_SLT10_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U)
25822#define GPC_SLT10_CFG_NOC_PUP_SLOT_CONTROL(x) \
25823 (((uint32_t)(((uint32_t)(x)) << GPC_SLT10_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & \
25824 GPC_SLT10_CFG_NOC_PUP_SLOT_CONTROL_MASK)
25825/*! @} */
25826
25827/*! @name SLT11_CFG - Slot configure register for CPUs */
25828/*! @{ */
25829#define GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
25830#define GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
25831#define GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \
25832 (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25833 GPC_SLT11_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
25834#define GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
25835#define GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
25836#define GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \
25837 (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25838 GPC_SLT11_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
25839#define GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
25840#define GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
25841#define GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \
25842 (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25843 GPC_SLT11_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
25844#define GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
25845#define GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
25846#define GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \
25847 (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25848 GPC_SLT11_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
25849#define GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
25850#define GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
25851#define GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \
25852 (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25853 GPC_SLT11_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
25854#define GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
25855#define GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
25856#define GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \
25857 (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25858 GPC_SLT11_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
25859#define GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
25860#define GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
25861#define GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \
25862 (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25863 GPC_SLT11_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
25864#define GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
25865#define GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
25866#define GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \
25867 (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25868 GPC_SLT11_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
25869#define GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
25870#define GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
25871#define GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL(x) \
25872 (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & \
25873 GPC_SLT11_CFG_SCU_PDN_SLOT_CONTROL_MASK)
25874#define GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
25875#define GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
25876#define GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL(x) \
25877 (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & \
25878 GPC_SLT11_CFG_SCU_PUP_SLOT_CONTROL_MASK)
25879#define GPC_SLT11_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U)
25880#define GPC_SLT11_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U)
25881#define GPC_SLT11_CFG_NOC_PDN_SLOT_CONTROL(x) \
25882 (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & \
25883 GPC_SLT11_CFG_NOC_PDN_SLOT_CONTROL_MASK)
25884#define GPC_SLT11_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U)
25885#define GPC_SLT11_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U)
25886#define GPC_SLT11_CFG_NOC_PUP_SLOT_CONTROL(x) \
25887 (((uint32_t)(((uint32_t)(x)) << GPC_SLT11_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & \
25888 GPC_SLT11_CFG_NOC_PUP_SLOT_CONTROL_MASK)
25889/*! @} */
25890
25891/*! @name SLT12_CFG - Slot configure register for CPUs */
25892/*! @{ */
25893#define GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
25894#define GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
25895#define GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \
25896 (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25897 GPC_SLT12_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
25898#define GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
25899#define GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
25900#define GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \
25901 (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25902 GPC_SLT12_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
25903#define GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
25904#define GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
25905#define GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \
25906 (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25907 GPC_SLT12_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
25908#define GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
25909#define GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
25910#define GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \
25911 (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25912 GPC_SLT12_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
25913#define GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
25914#define GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
25915#define GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \
25916 (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25917 GPC_SLT12_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
25918#define GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
25919#define GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
25920#define GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \
25921 (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25922 GPC_SLT12_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
25923#define GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
25924#define GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
25925#define GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \
25926 (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25927 GPC_SLT12_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
25928#define GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
25929#define GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
25930#define GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \
25931 (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25932 GPC_SLT12_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
25933#define GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
25934#define GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
25935#define GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL(x) \
25936 (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & \
25937 GPC_SLT12_CFG_SCU_PDN_SLOT_CONTROL_MASK)
25938#define GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
25939#define GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
25940#define GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL(x) \
25941 (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & \
25942 GPC_SLT12_CFG_SCU_PUP_SLOT_CONTROL_MASK)
25943#define GPC_SLT12_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U)
25944#define GPC_SLT12_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U)
25945#define GPC_SLT12_CFG_NOC_PDN_SLOT_CONTROL(x) \
25946 (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & \
25947 GPC_SLT12_CFG_NOC_PDN_SLOT_CONTROL_MASK)
25948#define GPC_SLT12_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U)
25949#define GPC_SLT12_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U)
25950#define GPC_SLT12_CFG_NOC_PUP_SLOT_CONTROL(x) \
25951 (((uint32_t)(((uint32_t)(x)) << GPC_SLT12_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & \
25952 GPC_SLT12_CFG_NOC_PUP_SLOT_CONTROL_MASK)
25953/*! @} */
25954
25955/*! @name SLT13_CFG - Slot configure register for CPUs */
25956/*! @{ */
25957#define GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
25958#define GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
25959#define GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \
25960 (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25961 GPC_SLT13_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
25962#define GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
25963#define GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
25964#define GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \
25965 (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25966 GPC_SLT13_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
25967#define GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
25968#define GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
25969#define GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \
25970 (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25971 GPC_SLT13_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
25972#define GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
25973#define GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
25974#define GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \
25975 (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25976 GPC_SLT13_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
25977#define GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
25978#define GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
25979#define GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \
25980 (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25981 GPC_SLT13_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
25982#define GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
25983#define GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
25984#define GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \
25985 (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25986 GPC_SLT13_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
25987#define GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
25988#define GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
25989#define GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \
25990 (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \
25991 GPC_SLT13_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
25992#define GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
25993#define GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
25994#define GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \
25995 (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \
25996 GPC_SLT13_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
25997#define GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
25998#define GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
25999#define GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL(x) \
26000 (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & \
26001 GPC_SLT13_CFG_SCU_PDN_SLOT_CONTROL_MASK)
26002#define GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
26003#define GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
26004#define GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL(x) \
26005 (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & \
26006 GPC_SLT13_CFG_SCU_PUP_SLOT_CONTROL_MASK)
26007#define GPC_SLT13_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U)
26008#define GPC_SLT13_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U)
26009#define GPC_SLT13_CFG_NOC_PDN_SLOT_CONTROL(x) \
26010 (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & \
26011 GPC_SLT13_CFG_NOC_PDN_SLOT_CONTROL_MASK)
26012#define GPC_SLT13_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U)
26013#define GPC_SLT13_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U)
26014#define GPC_SLT13_CFG_NOC_PUP_SLOT_CONTROL(x) \
26015 (((uint32_t)(((uint32_t)(x)) << GPC_SLT13_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & \
26016 GPC_SLT13_CFG_NOC_PUP_SLOT_CONTROL_MASK)
26017/*! @} */
26018
26019/*! @name SLT14_CFG - Slot configure register for CPUs */
26020/*! @{ */
26021#define GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
26022#define GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
26023#define GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \
26024 (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \
26025 GPC_SLT14_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
26026#define GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
26027#define GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
26028#define GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \
26029 (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \
26030 GPC_SLT14_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
26031#define GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
26032#define GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
26033#define GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \
26034 (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \
26035 GPC_SLT14_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
26036#define GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
26037#define GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
26038#define GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \
26039 (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \
26040 GPC_SLT14_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
26041#define GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
26042#define GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
26043#define GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \
26044 (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \
26045 GPC_SLT14_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
26046#define GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
26047#define GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
26048#define GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \
26049 (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \
26050 GPC_SLT14_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
26051#define GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
26052#define GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
26053#define GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \
26054 (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \
26055 GPC_SLT14_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
26056#define GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
26057#define GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
26058#define GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \
26059 (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \
26060 GPC_SLT14_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
26061#define GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
26062#define GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
26063#define GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL(x) \
26064 (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & \
26065 GPC_SLT14_CFG_SCU_PDN_SLOT_CONTROL_MASK)
26066#define GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
26067#define GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
26068#define GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL(x) \
26069 (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & \
26070 GPC_SLT14_CFG_SCU_PUP_SLOT_CONTROL_MASK)
26071#define GPC_SLT14_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U)
26072#define GPC_SLT14_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U)
26073#define GPC_SLT14_CFG_NOC_PDN_SLOT_CONTROL(x) \
26074 (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & \
26075 GPC_SLT14_CFG_NOC_PDN_SLOT_CONTROL_MASK)
26076#define GPC_SLT14_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U)
26077#define GPC_SLT14_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U)
26078#define GPC_SLT14_CFG_NOC_PUP_SLOT_CONTROL(x) \
26079 (((uint32_t)(((uint32_t)(x)) << GPC_SLT14_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & \
26080 GPC_SLT14_CFG_NOC_PUP_SLOT_CONTROL_MASK)
26081/*! @} */
26082
26083/*! @name PGC_CPU_0_1_MAPPING - PGC CPU mapping */
26084/*! @{ */
26085#define GPC_PGC_CPU_0_1_MAPPING_NOC_A53_DOMAIN_MASK (0x2U)
26086#define GPC_PGC_CPU_0_1_MAPPING_NOC_A53_DOMAIN_SHIFT (1U)
26087#define GPC_PGC_CPU_0_1_MAPPING_NOC_A53_DOMAIN(x) \
26088 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_NOC_A53_DOMAIN_SHIFT)) & \
26089 GPC_PGC_CPU_0_1_MAPPING_NOC_A53_DOMAIN_MASK)
26090#define GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN_MASK (0x4U)
26091#define GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN_SHIFT (2U)
26092#define GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN(x) \
26093 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN_SHIFT)) & \
26094 GPC_PGC_CPU_0_1_MAPPING_MIPI_A53_DOMAIN_MASK)
26095#define GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN_MASK (0x10U)
26096#define GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN_SHIFT (4U)
26097#define GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN(x) \
26098 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN_SHIFT)) & \
26099 GPC_PGC_CPU_0_1_MAPPING_OTG1_A53_DOMAIN_MASK)
26100#define GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN_MASK (0x80U)
26101#define GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN_SHIFT (7U)
26102#define GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN(x) \
26103 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN_SHIFT)) & \
26104 GPC_PGC_CPU_0_1_MAPPING_DDR1_A53_DOMAIN_MASK)
26105#define GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN_MASK (0x200U)
26106#define GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN_SHIFT (9U)
26107#define GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN(x) \
26108 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN_SHIFT)) & \
26109 GPC_PGC_CPU_0_1_MAPPING_GPU_A53_DOMAIN_MASK)
26110#define GPC_PGC_CPU_0_1_MAPPING_DISPMIX_A53_DOMAIN_MASK (0x1000U)
26111#define GPC_PGC_CPU_0_1_MAPPING_DISPMIX_A53_DOMAIN_SHIFT (12U)
26112#define GPC_PGC_CPU_0_1_MAPPING_DISPMIX_A53_DOMAIN(x) \
26113 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DISPMIX_A53_DOMAIN_SHIFT)) & \
26114 GPC_PGC_CPU_0_1_MAPPING_DISPMIX_A53_DOMAIN_MASK)
26115#define GPC_PGC_CPU_0_1_MAPPING_NOC_M7_DOMAIN_MASK (0x20000U)
26116#define GPC_PGC_CPU_0_1_MAPPING_NOC_M7_DOMAIN_SHIFT (17U)
26117#define GPC_PGC_CPU_0_1_MAPPING_NOC_M7_DOMAIN(x) \
26118 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_NOC_M7_DOMAIN_SHIFT)) & \
26119 GPC_PGC_CPU_0_1_MAPPING_NOC_M7_DOMAIN_MASK)
26120#define GPC_PGC_CPU_0_1_MAPPING_MIPI_M7_DOMAIN_MASK (0x40000U)
26121#define GPC_PGC_CPU_0_1_MAPPING_MIPI_M7_DOMAIN_SHIFT (18U)
26122#define GPC_PGC_CPU_0_1_MAPPING_MIPI_M7_DOMAIN(x) \
26123 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_MIPI_M7_DOMAIN_SHIFT)) & \
26124 GPC_PGC_CPU_0_1_MAPPING_MIPI_M7_DOMAIN_MASK)
26125#define GPC_PGC_CPU_0_1_MAPPING_OTG1_M7_DOMAIN_MASK (0x100000U)
26126#define GPC_PGC_CPU_0_1_MAPPING_OTG1_M7_DOMAIN_SHIFT (20U)
26127#define GPC_PGC_CPU_0_1_MAPPING_OTG1_M7_DOMAIN(x) \
26128 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_OTG1_M7_DOMAIN_SHIFT)) & \
26129 GPC_PGC_CPU_0_1_MAPPING_OTG1_M7_DOMAIN_MASK)
26130#define GPC_PGC_CPU_0_1_MAPPING_DDR1_M7_DOMAIN_MASK (0x800000U)
26131#define GPC_PGC_CPU_0_1_MAPPING_DDR1_M7_DOMAIN_SHIFT (23U)
26132#define GPC_PGC_CPU_0_1_MAPPING_DDR1_M7_DOMAIN(x) \
26133 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DDR1_M7_DOMAIN_SHIFT)) & \
26134 GPC_PGC_CPU_0_1_MAPPING_DDR1_M7_DOMAIN_MASK)
26135#define GPC_PGC_CPU_0_1_MAPPING_GPUMIX_M7_DOMAIN_MASK (0x2000000U)
26136#define GPC_PGC_CPU_0_1_MAPPING_GPUMIX_M7_DOMAIN_SHIFT (25U)
26137#define GPC_PGC_CPU_0_1_MAPPING_GPUMIX_M7_DOMAIN(x) \
26138 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_GPUMIX_M7_DOMAIN_SHIFT)) & \
26139 GPC_PGC_CPU_0_1_MAPPING_GPUMIX_M7_DOMAIN_MASK)
26140#define GPC_PGC_CPU_0_1_MAPPING_DISPMIX_M7_DOMAIN_MASK (0x10000000U)
26141#define GPC_PGC_CPU_0_1_MAPPING_DISPMIX_M7_DOMAIN_SHIFT (28U)
26142#define GPC_PGC_CPU_0_1_MAPPING_DISPMIX_M7_DOMAIN(x) \
26143 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_CPU_0_1_MAPPING_DISPMIX_M7_DOMAIN_SHIFT)) & \
26144 GPC_PGC_CPU_0_1_MAPPING_DISPMIX_M7_DOMAIN_MASK)
26145/*! @} */
26146
26147/*! @name CPU_PGC_SW_PUP_REQ - CPU PGC software power up trigger */
26148/*! @{ */
26149#define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_MASK (0x1U)
26150#define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_SHIFT (0U)
26151#define GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ(x) \
26152 (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_SHIFT)) & \
26153 GPC_CPU_PGC_SW_PUP_REQ_CORE0_A53_SW_PUP_REQ_MASK)
26154#define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_MASK (0x2U)
26155#define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_SHIFT (1U)
26156#define GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ(x) \
26157 (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_SHIFT)) & \
26158 GPC_CPU_PGC_SW_PUP_REQ_CORE1_A53_SW_PUP_REQ_MASK)
26159#define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_MASK (0x4U)
26160#define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_SHIFT (2U)
26161#define GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ(x) \
26162 (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_SHIFT)) & \
26163 GPC_CPU_PGC_SW_PUP_REQ_CORE2_A53_SW_PUP_REQ_MASK)
26164#define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_MASK (0x8U)
26165#define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_SHIFT (3U)
26166#define GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ(x) \
26167 (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_SHIFT)) & \
26168 GPC_CPU_PGC_SW_PUP_REQ_CORE3_A53_SW_PUP_REQ_MASK)
26169#define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_MASK (0x10U)
26170#define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_SHIFT (4U)
26171#define GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ(x) \
26172 (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_SHIFT)) & \
26173 GPC_CPU_PGC_SW_PUP_REQ_SCU_A53_SW_PUP_REQ_MASK)
26174/*! @} */
26175
26176/*! @name MIX_PGC_SW_PUP_REQ - MIX PGC software power up trigger */
26177/*! @{ */
26178#define GPC_MIX_PGC_SW_PUP_REQ_NOC_SW_PUP_REQ_MASK (0x2U)
26179#define GPC_MIX_PGC_SW_PUP_REQ_NOC_SW_PUP_REQ_SHIFT (1U)
26180#define GPC_MIX_PGC_SW_PUP_REQ_NOC_SW_PUP_REQ(x) \
26181 (((uint32_t)(((uint32_t)(x)) << GPC_MIX_PGC_SW_PUP_REQ_NOC_SW_PUP_REQ_SHIFT)) & \
26182 GPC_MIX_PGC_SW_PUP_REQ_NOC_SW_PUP_REQ_MASK)
26183/*! @} */
26184
26185/*! @name PU_PGC_SW_PUP_REQ - PU PGC software up trigger */
26186/*! @{ */
26187#define GPC_PU_PGC_SW_PUP_REQ_MIPI_DSI_SW_PUP_REQ_MASK (0x1U)
26188#define GPC_PU_PGC_SW_PUP_REQ_MIPI_DSI_SW_PUP_REQ_SHIFT (0U)
26189#define GPC_PU_PGC_SW_PUP_REQ_MIPI_DSI_SW_PUP_REQ(x) \
26190 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_MIPI_DSI_SW_PUP_REQ_SHIFT)) & \
26191 GPC_PU_PGC_SW_PUP_REQ_MIPI_DSI_SW_PUP_REQ_MASK)
26192#define GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ_MASK (0x4U)
26193#define GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ_SHIFT (2U)
26194#define GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ(x) \
26195 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ_SHIFT)) & \
26196 GPC_PU_PGC_SW_PUP_REQ_USB_OTG1_SW_PUP_REQ_MASK)
26197#define GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_MASK (0x20U)
26198#define GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_SHIFT (5U)
26199#define GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ(x) \
26200 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_SHIFT)) & \
26201 GPC_PU_PGC_SW_PUP_REQ_DDR1_SW_PUP_REQ_MASK)
26202#define GPC_PU_PGC_SW_PUP_REQ_GPUMIX_SW_PUP_REQ_MASK (0x80U)
26203#define GPC_PU_PGC_SW_PUP_REQ_GPUMIX_SW_PUP_REQ_SHIFT (7U)
26204#define GPC_PU_PGC_SW_PUP_REQ_GPUMIX_SW_PUP_REQ(x) \
26205 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_GPUMIX_SW_PUP_REQ_SHIFT)) & \
26206 GPC_PU_PGC_SW_PUP_REQ_GPUMIX_SW_PUP_REQ_MASK)
26207#define GPC_PU_PGC_SW_PUP_REQ_DISPMIX_SW_PUP_REQ_MASK (0x400U)
26208#define GPC_PU_PGC_SW_PUP_REQ_DISPMIX_SW_PUP_REQ_SHIFT (10U)
26209#define GPC_PU_PGC_SW_PUP_REQ_DISPMIX_SW_PUP_REQ(x) \
26210 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PUP_REQ_DISPMIX_SW_PUP_REQ_SHIFT)) & \
26211 GPC_PU_PGC_SW_PUP_REQ_DISPMIX_SW_PUP_REQ_MASK)
26212/*! @} */
26213
26214/*! @name CPU_PGC_SW_PDN_REQ - CPU PGC software down trigger */
26215/*! @{ */
26216#define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_MASK (0x1U)
26217#define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_SHIFT (0U)
26218#define GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ(x) \
26219 (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_SHIFT)) & \
26220 GPC_CPU_PGC_SW_PDN_REQ_CORE0_A53_SW_PDN_REQ_MASK)
26221#define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_MASK (0x2U)
26222#define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_SHIFT (1U)
26223#define GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ(x) \
26224 (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_SHIFT)) & \
26225 GPC_CPU_PGC_SW_PDN_REQ_CORE1_A53_SW_PDN_REQ_MASK)
26226#define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PDN_REQ_MASK (0x4U)
26227#define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PDN_REQ_SHIFT (2U)
26228#define GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PDN_REQ(x) \
26229 (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PDN_REQ_SHIFT)) & \
26230 GPC_CPU_PGC_SW_PDN_REQ_CORE2_A53_SW_PDN_REQ_MASK)
26231#define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_MASK (0x8U)
26232#define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_SHIFT (3U)
26233#define GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ(x) \
26234 (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_SHIFT)) & \
26235 GPC_CPU_PGC_SW_PDN_REQ_CORE3_A53_SW_PUP_REQ_MASK)
26236#define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PUP_REQ_MASK (0x10U)
26237#define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PUP_REQ_SHIFT (4U)
26238#define GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PUP_REQ(x) \
26239 (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PUP_REQ_SHIFT)) & \
26240 GPC_CPU_PGC_SW_PDN_REQ_SCU_A53_SW_PUP_REQ_MASK)
26241/*! @} */
26242
26243/*! @name MIX_PGC_SW_PDN_REQ - MIX PGC software power down trigger */
26244/*! @{ */
26245#define GPC_MIX_PGC_SW_PDN_REQ_NOC_SW_PDN_REQ_MASK (0x2U)
26246#define GPC_MIX_PGC_SW_PDN_REQ_NOC_SW_PDN_REQ_SHIFT (1U)
26247#define GPC_MIX_PGC_SW_PDN_REQ_NOC_SW_PDN_REQ(x) \
26248 (((uint32_t)(((uint32_t)(x)) << GPC_MIX_PGC_SW_PDN_REQ_NOC_SW_PDN_REQ_SHIFT)) & \
26249 GPC_MIX_PGC_SW_PDN_REQ_NOC_SW_PDN_REQ_MASK)
26250/*! @} */
26251
26252/*! @name PU_PGC_SW_PDN_REQ - PU PGC software down trigger */
26253/*! @{ */
26254#define GPC_PU_PGC_SW_PDN_REQ_MIPI_DSI_SW_PDN_REQ_MASK (0x1U)
26255#define GPC_PU_PGC_SW_PDN_REQ_MIPI_DSI_SW_PDN_REQ_SHIFT (0U)
26256#define GPC_PU_PGC_SW_PDN_REQ_MIPI_DSI_SW_PDN_REQ(x) \
26257 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_MIPI_DSI_SW_PDN_REQ_SHIFT)) & \
26258 GPC_PU_PGC_SW_PDN_REQ_MIPI_DSI_SW_PDN_REQ_MASK)
26259#define GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ_MASK (0x4U)
26260#define GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ_SHIFT (2U)
26261#define GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ(x) \
26262 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ_SHIFT)) & \
26263 GPC_PU_PGC_SW_PDN_REQ_USB_OTG1_SW_PDN_REQ_MASK)
26264#define GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ_MASK (0x20U)
26265#define GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ_SHIFT (5U)
26266#define GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ(x) \
26267 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ_SHIFT)) & \
26268 GPC_PU_PGC_SW_PDN_REQ_DDR1_SW_PDN_REQ_MASK)
26269#define GPC_PU_PGC_SW_PDN_REQ_GPUMIX_SW_PDN_REQ_MASK (0x80U)
26270#define GPC_PU_PGC_SW_PDN_REQ_GPUMIX_SW_PDN_REQ_SHIFT (7U)
26271#define GPC_PU_PGC_SW_PDN_REQ_GPUMIX_SW_PDN_REQ(x) \
26272 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_GPUMIX_SW_PDN_REQ_SHIFT)) & \
26273 GPC_PU_PGC_SW_PDN_REQ_GPUMIX_SW_PDN_REQ_MASK)
26274#define GPC_PU_PGC_SW_PDN_REQ_DISPMIX_SW_PDN_REQ_MASK (0x400U)
26275#define GPC_PU_PGC_SW_PDN_REQ_DISPMIX_SW_PDN_REQ_SHIFT (10U)
26276#define GPC_PU_PGC_SW_PDN_REQ_DISPMIX_SW_PDN_REQ(x) \
26277 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PGC_SW_PDN_REQ_DISPMIX_SW_PDN_REQ_SHIFT)) & \
26278 GPC_PU_PGC_SW_PDN_REQ_DISPMIX_SW_PDN_REQ_MASK)
26279/*! @} */
26280
26281/*! @name LPCR_A53_BSC2 - Basic Low power control register of A53 platform */
26282/*! @{ */
26283#define GPC_LPCR_A53_BSC2_LPM2_MASK (0x3U)
26284#define GPC_LPCR_A53_BSC2_LPM2_SHIFT (0U)
26285/*! LPM2
26286 * 0b00..Remain in RUN mode
26287 * 0b01..Transfer to WAIT mode
26288 * 0b10..Transfer to STOP mode
26289 * 0b11..Reserved
26290 */
26291#define GPC_LPCR_A53_BSC2_LPM2(x) \
26292 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC2_LPM2_SHIFT)) & GPC_LPCR_A53_BSC2_LPM2_MASK)
26293#define GPC_LPCR_A53_BSC2_LPM3_MASK (0xCU)
26294#define GPC_LPCR_A53_BSC2_LPM3_SHIFT (2U)
26295/*! LPM3
26296 * 0b00..Remain in RUN mode
26297 * 0b01..Transfer to WAIT mode
26298 * 0b10..Transfer to STOP mode
26299 * 0b11..Reserved
26300 */
26301#define GPC_LPCR_A53_BSC2_LPM3(x) \
26302 (((uint32_t)(((uint32_t)(x)) << GPC_LPCR_A53_BSC2_LPM3_SHIFT)) & GPC_LPCR_A53_BSC2_LPM3_MASK)
26303/*! @} */
26304
26305/*! @name CPU_PGC_PUP_STATUS1 - CPU PGC software up trigger status1 */
26306/*! @{ */
26307#define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_MASK (0x1U)
26308#define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_SHIFT (0U)
26309#define GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS(x) \
26310 (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_SHIFT)) & \
26311 GPC_CPU_PGC_PUP_STATUS1_CORE0_A53_PUP_STATUS_MASK)
26312#define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_MASK (0x2U)
26313#define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_SHIFT (1U)
26314#define GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS(x) \
26315 (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_SHIFT)) & \
26316 GPC_CPU_PGC_PUP_STATUS1_CORE1_A53_PUP_STATUS_MASK)
26317#define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_MASK (0x4U)
26318#define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_SHIFT (2U)
26319#define GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS(x) \
26320 (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_SHIFT)) & \
26321 GPC_CPU_PGC_PUP_STATUS1_CORE2_A53_PUP_STATUS_MASK)
26322#define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_STATUS_MASK (0x8U)
26323#define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_STATUS_SHIFT (3U)
26324#define GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_STATUS(x) \
26325 (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_STATUS_SHIFT)) & \
26326 GPC_CPU_PGC_PUP_STATUS1_CORE3_A53_PUP_STATUS_MASK)
26327#define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_REQ_MASK (0x10U)
26328#define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_REQ_SHIFT (4U)
26329#define GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_REQ(x) \
26330 (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_REQ_SHIFT)) & \
26331 GPC_CPU_PGC_PUP_STATUS1_SCU_A53_PUP_REQ_MASK)
26332/*! @} */
26333
26334/*! @name A53_MIX_PGC_PUP_STATUS - A53 MIX software up trigger status register */
26335/*! @{ */
26336#define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_MASK (0x1U)
26337#define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_SHIFT (0U)
26338#define GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS(x) \
26339 (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_SHIFT)) & \
26340 GPC_A53_MIX_PGC_PUP_STATUS_A53_MIX_PGC_PUP_STATUS_MASK)
26341/*! @} */
26342
26343/* The count of GPC_A53_MIX_PGC_PUP_STATUS */
26344#define GPC_A53_MIX_PGC_PUP_STATUS_COUNT (3U)
26345
26346/*! @name M7_MIX_PGC_PUP_STATUS - M7 MIX PGC software up trigger status register */
26347/*! @{ */
26348#define GPC_M7_MIX_PGC_PUP_STATUS_M7_MIX_PGC_PUP_STATUS_MASK (0x1U)
26349#define GPC_M7_MIX_PGC_PUP_STATUS_M7_MIX_PGC_PUP_STATUS_SHIFT (0U)
26350#define GPC_M7_MIX_PGC_PUP_STATUS_M7_MIX_PGC_PUP_STATUS(x) \
26351 (((uint32_t)(((uint32_t)(x)) << GPC_M7_MIX_PGC_PUP_STATUS_M7_MIX_PGC_PUP_STATUS_SHIFT)) & \
26352 GPC_M7_MIX_PGC_PUP_STATUS_M7_MIX_PGC_PUP_STATUS_MASK)
26353/*! @} */
26354
26355/* The count of GPC_M7_MIX_PGC_PUP_STATUS */
26356#define GPC_M7_MIX_PGC_PUP_STATUS_COUNT (3U)
26357
26358/*! @name A53_PU_PGC_PUP_STATUS - A53 PU software up trigger status register */
26359/*! @{ */
26360#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY_PUP_STATUS_MASK (0x1U)
26361#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY_PUP_STATUS_SHIFT (0U)
26362#define GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY_PUP_STATUS(x) \
26363 (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY_PUP_STATUS_SHIFT)) & \
26364 GPC_A53_PU_PGC_PUP_STATUS_A53_MIPI_PHY_PUP_STATUS_MASK)
26365#define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS_MASK (0x4U)
26366#define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS_SHIFT (2U)
26367#define GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS(x) \
26368 (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS_SHIFT)) & \
26369 GPC_A53_PU_PGC_PUP_STATUS_A53_OTG1_PUP_STATUS_MASK)
26370#define GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS_MASK (0x20U)
26371#define GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS_SHIFT (5U)
26372#define GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS(x) \
26373 (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS_SHIFT)) & \
26374 GPC_A53_PU_PGC_PUP_STATUS_A53_DDR1_PUP_STATUS_MASK)
26375#define GPC_A53_PU_PGC_PUP_STATUS_A53_GPUMIX_PUP_STATUS_MASK (0x80U)
26376#define GPC_A53_PU_PGC_PUP_STATUS_A53_GPUMIX_PUP_STATUS_SHIFT (7U)
26377#define GPC_A53_PU_PGC_PUP_STATUS_A53_GPUMIX_PUP_STATUS(x) \
26378 (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_GPUMIX_PUP_STATUS_SHIFT)) & \
26379 GPC_A53_PU_PGC_PUP_STATUS_A53_GPUMIX_PUP_STATUS_MASK)
26380#define GPC_A53_PU_PGC_PUP_STATUS_A53_DISPMIX_PUP_STATUS_MASK (0x400U)
26381#define GPC_A53_PU_PGC_PUP_STATUS_A53_DISPMIX_PUP_STATUS_SHIFT (10U)
26382#define GPC_A53_PU_PGC_PUP_STATUS_A53_DISPMIX_PUP_STATUS(x) \
26383 (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PUP_STATUS_A53_DISPMIX_PUP_STATUS_SHIFT)) & \
26384 GPC_A53_PU_PGC_PUP_STATUS_A53_DISPMIX_PUP_STATUS_MASK)
26385/*! @} */
26386
26387/* The count of GPC_A53_PU_PGC_PUP_STATUS */
26388#define GPC_A53_PU_PGC_PUP_STATUS_COUNT (3U)
26389
26390/*! @name M7_PU_PGC_PUP_STATUS - M7 PU PGC software up trigger status register */
26391/*! @{ */
26392#define GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY_PUP_STATUS_MASK (0x1U)
26393#define GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY_PUP_STATUS_SHIFT (0U)
26394#define GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY_PUP_STATUS(x) \
26395 (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY_PUP_STATUS_SHIFT)) & \
26396 GPC_M7_PU_PGC_PUP_STATUS_M7_MIPI_PHY_PUP_STATUS_MASK)
26397#define GPC_M7_PU_PGC_PUP_STATUS_M7_OTG1_PUP_STATUS_MASK (0x4U)
26398#define GPC_M7_PU_PGC_PUP_STATUS_M7_OTG1_PUP_STATUS_SHIFT (2U)
26399#define GPC_M7_PU_PGC_PUP_STATUS_M7_OTG1_PUP_STATUS(x) \
26400 (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_OTG1_PUP_STATUS_SHIFT)) & \
26401 GPC_M7_PU_PGC_PUP_STATUS_M7_OTG1_PUP_STATUS_MASK)
26402#define GPC_M7_PU_PGC_PUP_STATUS_M7_DDR1_PUP_STATUS_MASK (0x20U)
26403#define GPC_M7_PU_PGC_PUP_STATUS_M7_DDR1_PUP_STATUS_SHIFT (5U)
26404#define GPC_M7_PU_PGC_PUP_STATUS_M7_DDR1_PUP_STATUS(x) \
26405 (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_DDR1_PUP_STATUS_SHIFT)) & \
26406 GPC_M7_PU_PGC_PUP_STATUS_M7_DDR1_PUP_STATUS_MASK)
26407#define GPC_M7_PU_PGC_PUP_STATUS_M7_GPUMIX_PUP_STATUS_MASK (0x80U)
26408#define GPC_M7_PU_PGC_PUP_STATUS_M7_GPUMIX_PUP_STATUS_SHIFT (7U)
26409#define GPC_M7_PU_PGC_PUP_STATUS_M7_GPUMIX_PUP_STATUS(x) \
26410 (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_GPUMIX_PUP_STATUS_SHIFT)) & \
26411 GPC_M7_PU_PGC_PUP_STATUS_M7_GPUMIX_PUP_STATUS_MASK)
26412#define GPC_M7_PU_PGC_PUP_STATUS_M7_DISPMIX_PUP_STATUS_MASK (0x400U)
26413#define GPC_M7_PU_PGC_PUP_STATUS_M7_DISPMIX_PUP_STATUS_SHIFT (10U)
26414#define GPC_M7_PU_PGC_PUP_STATUS_M7_DISPMIX_PUP_STATUS(x) \
26415 (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PUP_STATUS_M7_DISPMIX_PUP_STATUS_SHIFT)) & \
26416 GPC_M7_PU_PGC_PUP_STATUS_M7_DISPMIX_PUP_STATUS_MASK)
26417/*! @} */
26418
26419/* The count of GPC_M7_PU_PGC_PUP_STATUS */
26420#define GPC_M7_PU_PGC_PUP_STATUS_COUNT (3U)
26421
26422/*! @name CPU_PGC_PDN_STATUS1 - CPU PGC software dn trigger status1 */
26423/*! @{ */
26424#define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_MASK (0x1U)
26425#define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_SHIFT (0U)
26426#define GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS(x) \
26427 (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_SHIFT)) & \
26428 GPC_CPU_PGC_PDN_STATUS1_CORE0_A53_PDN_STATUS_MASK)
26429#define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_MASK (0x2U)
26430#define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_SHIFT (1U)
26431#define GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS(x) \
26432 (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_SHIFT)) & \
26433 GPC_CPU_PGC_PDN_STATUS1_CORE1_A53_PDN_STATUS_MASK)
26434#define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_MASK (0x4U)
26435#define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_SHIFT (2U)
26436#define GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS(x) \
26437 (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_SHIFT)) & \
26438 GPC_CPU_PGC_PDN_STATUS1_CORE2_A53_PDN_STATUS_MASK)
26439#define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_STATUS_MASK (0x8U)
26440#define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_STATUS_SHIFT (3U)
26441#define GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_STATUS(x) \
26442 (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_STATUS_SHIFT)) & \
26443 GPC_CPU_PGC_PDN_STATUS1_CORE3_A53_PDN_STATUS_MASK)
26444#define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_REQ_MASK (0x10U)
26445#define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_REQ_SHIFT (4U)
26446#define GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_REQ(x) \
26447 (((uint32_t)(((uint32_t)(x)) << GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_REQ_SHIFT)) & \
26448 GPC_CPU_PGC_PDN_STATUS1_SCU_A53_PDN_REQ_MASK)
26449/*! @} */
26450
26451/*! @name A53_MIX_PGC_PDN_STATUS - A53 MIX software down trigger status register */
26452/*! @{ */
26453#define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_MASK (0x1U)
26454#define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_SHIFT (0U)
26455#define GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS(x) \
26456 (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_SHIFT)) & \
26457 GPC_A53_MIX_PGC_PDN_STATUS_A53_MIX_PGC_PDN_STATUS_MASK)
26458/*! @} */
26459
26460/* The count of GPC_A53_MIX_PGC_PDN_STATUS */
26461#define GPC_A53_MIX_PGC_PDN_STATUS_COUNT (3U)
26462
26463/*! @name M7_MIX_PGC_PDN_STATUS - M7 MIX PGC software power down trigger status register */
26464/*! @{ */
26465#define GPC_M7_MIX_PGC_PDN_STATUS_M7_MIX_PGC_PDN_STATUS_MASK (0x1U)
26466#define GPC_M7_MIX_PGC_PDN_STATUS_M7_MIX_PGC_PDN_STATUS_SHIFT (0U)
26467#define GPC_M7_MIX_PGC_PDN_STATUS_M7_MIX_PGC_PDN_STATUS(x) \
26468 (((uint32_t)(((uint32_t)(x)) << GPC_M7_MIX_PGC_PDN_STATUS_M7_MIX_PGC_PDN_STATUS_SHIFT)) & \
26469 GPC_M7_MIX_PGC_PDN_STATUS_M7_MIX_PGC_PDN_STATUS_MASK)
26470/*! @} */
26471
26472/* The count of GPC_M7_MIX_PGC_PDN_STATUS */
26473#define GPC_M7_MIX_PGC_PDN_STATUS_COUNT (3U)
26474
26475/*! @name A53_PU_PGC_PDN_STATUS - A53 PU PGC software down trigger status */
26476/*! @{ */
26477#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY_PDN_STATUS_MASK (0x1U)
26478#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY_PDN_STATUS_SHIFT (0U)
26479#define GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY_PDN_STATUS(x) \
26480 (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY_PDN_STATUS_SHIFT)) & \
26481 GPC_A53_PU_PGC_PDN_STATUS_A53_MIPI_PHY_PDN_STATUS_MASK)
26482#define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS_MASK (0x4U)
26483#define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS_SHIFT (2U)
26484#define GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS(x) \
26485 (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS_SHIFT)) & \
26486 GPC_A53_PU_PGC_PDN_STATUS_A53_OTG1_PDN_STATUS_MASK)
26487#define GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS_MASK (0x20U)
26488#define GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS_SHIFT (5U)
26489#define GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS(x) \
26490 (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS_SHIFT)) & \
26491 GPC_A53_PU_PGC_PDN_STATUS_A53_DDR1_PDN_STATUS_MASK)
26492#define GPC_A53_PU_PGC_PDN_STATUS_A53_GPUMIX_PDN_STATUS_MASK (0x80U)
26493#define GPC_A53_PU_PGC_PDN_STATUS_A53_GPUMIX_PDN_STATUS_SHIFT (7U)
26494#define GPC_A53_PU_PGC_PDN_STATUS_A53_GPUMIX_PDN_STATUS(x) \
26495 (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_GPUMIX_PDN_STATUS_SHIFT)) & \
26496 GPC_A53_PU_PGC_PDN_STATUS_A53_GPUMIX_PDN_STATUS_MASK)
26497#define GPC_A53_PU_PGC_PDN_STATUS_A53_DISPMIX_PDN_STATUS_MASK (0x400U)
26498#define GPC_A53_PU_PGC_PDN_STATUS_A53_DISPMIX_PDN_STATUS_SHIFT (10U)
26499#define GPC_A53_PU_PGC_PDN_STATUS_A53_DISPMIX_PDN_STATUS(x) \
26500 (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PGC_PDN_STATUS_A53_DISPMIX_PDN_STATUS_SHIFT)) & \
26501 GPC_A53_PU_PGC_PDN_STATUS_A53_DISPMIX_PDN_STATUS_MASK)
26502/*! @} */
26503
26504/* The count of GPC_A53_PU_PGC_PDN_STATUS */
26505#define GPC_A53_PU_PGC_PDN_STATUS_COUNT (3U)
26506
26507/*! @name M7_PU_PGC_PDN_STATUS - M7 PU PGC software down trigger status */
26508/*! @{ */
26509#define GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY_PDN_STATUS_MASK (0x1U)
26510#define GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY_PDN_STATUS_SHIFT (0U)
26511#define GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY_PDN_STATUS(x) \
26512 (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY_PDN_STATUS_SHIFT)) & \
26513 GPC_M7_PU_PGC_PDN_STATUS_M7_MIPI_PHY_PDN_STATUS_MASK)
26514#define GPC_M7_PU_PGC_PDN_STATUS_M7_OTG1_PDN_STATUS_MASK (0x4U)
26515#define GPC_M7_PU_PGC_PDN_STATUS_M7_OTG1_PDN_STATUS_SHIFT (2U)
26516#define GPC_M7_PU_PGC_PDN_STATUS_M7_OTG1_PDN_STATUS(x) \
26517 (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_OTG1_PDN_STATUS_SHIFT)) & \
26518 GPC_M7_PU_PGC_PDN_STATUS_M7_OTG1_PDN_STATUS_MASK)
26519#define GPC_M7_PU_PGC_PDN_STATUS_M7_DDR1_PDN_STATUS_MASK (0x20U)
26520#define GPC_M7_PU_PGC_PDN_STATUS_M7_DDR1_PDN_STATUS_SHIFT (5U)
26521#define GPC_M7_PU_PGC_PDN_STATUS_M7_DDR1_PDN_STATUS(x) \
26522 (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_DDR1_PDN_STATUS_SHIFT)) & \
26523 GPC_M7_PU_PGC_PDN_STATUS_M7_DDR1_PDN_STATUS_MASK)
26524#define GPC_M7_PU_PGC_PDN_STATUS_M7_GPUMIX_PDN_STATUS_MASK (0x80U)
26525#define GPC_M7_PU_PGC_PDN_STATUS_M7_GPUMIX_PDN_STATUS_SHIFT (7U)
26526#define GPC_M7_PU_PGC_PDN_STATUS_M7_GPUMIX_PDN_STATUS(x) \
26527 (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_GPUMIX_PDN_STATUS_SHIFT)) & \
26528 GPC_M7_PU_PGC_PDN_STATUS_M7_GPUMIX_PDN_STATUS_MASK)
26529#define GPC_M7_PU_PGC_PDN_STATUS_M7_DISPMIX_PDN_STATUS_MASK (0x400U)
26530#define GPC_M7_PU_PGC_PDN_STATUS_M7_DISPMIX_PDN_STATUS_SHIFT (10U)
26531#define GPC_M7_PU_PGC_PDN_STATUS_M7_DISPMIX_PDN_STATUS(x) \
26532 (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PGC_PDN_STATUS_M7_DISPMIX_PDN_STATUS_SHIFT)) & \
26533 GPC_M7_PU_PGC_PDN_STATUS_M7_DISPMIX_PDN_STATUS_MASK)
26534/*! @} */
26535
26536/* The count of GPC_M7_PU_PGC_PDN_STATUS */
26537#define GPC_M7_PU_PGC_PDN_STATUS_COUNT (3U)
26538
26539/*! @name A53_MIX_PDN_FLG - A53 MIX PDN FLG */
26540/*! @{ */
26541#define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_MASK (0x1U)
26542#define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_SHIFT (0U)
26543#define GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG(x) \
26544 (((uint32_t)(((uint32_t)(x)) << GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_SHIFT)) & \
26545 GPC_A53_MIX_PDN_FLG_A53_MIX_PDN_FLAG_MASK)
26546/*! @} */
26547
26548/*! @name A53_PU_PDN_FLG - A53 PU PDN FLG */
26549/*! @{ */
26550#define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_MASK (0x3FFFU)
26551#define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_SHIFT (0U)
26552#define GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG(x) \
26553 (((uint32_t)(((uint32_t)(x)) << GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_SHIFT)) & GPC_A53_PU_PDN_FLG_A53_PU_PDN_FLG_MASK)
26554/*! @} */
26555
26556/*! @name M7_MIX_PDN_FLG - M7 MIX PDN FLG */
26557/*! @{ */
26558#define GPC_M7_MIX_PDN_FLG_M7_MIX_PDN_FLAG_MASK (0x1U)
26559#define GPC_M7_MIX_PDN_FLG_M7_MIX_PDN_FLAG_SHIFT (0U)
26560#define GPC_M7_MIX_PDN_FLG_M7_MIX_PDN_FLAG(x) \
26561 (((uint32_t)(((uint32_t)(x)) << GPC_M7_MIX_PDN_FLG_M7_MIX_PDN_FLAG_SHIFT)) & \
26562 GPC_M7_MIX_PDN_FLG_M7_MIX_PDN_FLAG_MASK)
26563/*! @} */
26564
26565/*! @name M7_PU_PDN_FLG - M7 PU PDN FLG */
26566/*! @{ */
26567#define GPC_M7_PU_PDN_FLG_M7_PU_PDN_FLG_MASK (0x3FFFU)
26568#define GPC_M7_PU_PDN_FLG_M7_PU_PDN_FLG_SHIFT (0U)
26569#define GPC_M7_PU_PDN_FLG_M7_PU_PDN_FLG(x) \
26570 (((uint32_t)(((uint32_t)(x)) << GPC_M7_PU_PDN_FLG_M7_PU_PDN_FLG_SHIFT)) & GPC_M7_PU_PDN_FLG_M7_PU_PDN_FLG_MASK)
26571/*! @} */
26572
26573/*! @name IMR_CORE2_A53 - IRQ masking register 1 of A53 core2..IRQ masking register 4 of A53 core2 */
26574/*! @{ */
26575#define GPC_IMR_CORE2_A53_IMR1_CORE2_A53_MASK (0xFFFFFFFFU)
26576#define GPC_IMR_CORE2_A53_IMR1_CORE2_A53_SHIFT (0U)
26577/*! IMR1_CORE2_A53
26578 * 0b00000000000000000000000000000000..IRQ not masked
26579 * 0b00000000000000000000000000000001..IRQ masked
26580 */
26581#define GPC_IMR_CORE2_A53_IMR1_CORE2_A53(x) \
26582 (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR1_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR1_CORE2_A53_MASK)
26583#define GPC_IMR_CORE2_A53_IMR2_CORE2_A53_MASK (0xFFFFFFFFU)
26584#define GPC_IMR_CORE2_A53_IMR2_CORE2_A53_SHIFT (0U)
26585/*! IMR2_CORE2_A53
26586 * 0b00000000000000000000000000000000..IRQ not masked
26587 * 0b00000000000000000000000000000001..IRQ masked
26588 */
26589#define GPC_IMR_CORE2_A53_IMR2_CORE2_A53(x) \
26590 (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR2_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR2_CORE2_A53_MASK)
26591#define GPC_IMR_CORE2_A53_IMR3_CORE2_A53_MASK (0xFFFFFFFFU)
26592#define GPC_IMR_CORE2_A53_IMR3_CORE2_A53_SHIFT (0U)
26593/*! IMR3_CORE2_A53
26594 * 0b00000000000000000000000000000000..IRQ not masked
26595 * 0b00000000000000000000000000000001..IRQ masked
26596 */
26597#define GPC_IMR_CORE2_A53_IMR3_CORE2_A53(x) \
26598 (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR3_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR3_CORE2_A53_MASK)
26599#define GPC_IMR_CORE2_A53_IMR4_CORE2_A53_MASK (0xFFFFFFFFU)
26600#define GPC_IMR_CORE2_A53_IMR4_CORE2_A53_SHIFT (0U)
26601/*! IMR4_CORE2_A53
26602 * 0b00000000000000000000000000000000..IRQ not masked
26603 * 0b00000000000000000000000000000001..IRQ masked
26604 */
26605#define GPC_IMR_CORE2_A53_IMR4_CORE2_A53(x) \
26606 (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE2_A53_IMR4_CORE2_A53_SHIFT)) & GPC_IMR_CORE2_A53_IMR4_CORE2_A53_MASK)
26607/*! @} */
26608
26609/* The count of GPC_IMR_CORE2_A53 */
26610#define GPC_IMR_CORE2_A53_COUNT (4U)
26611
26612/*! @name IMR_CORE3_A53 - IRQ masking register 1 of A53 core3..IRQ masking register 4 of A53 core3 */
26613/*! @{ */
26614#define GPC_IMR_CORE3_A53_IMR1_CORE3_A53_MASK (0xFFFFFFFFU)
26615#define GPC_IMR_CORE3_A53_IMR1_CORE3_A53_SHIFT (0U)
26616/*! IMR1_CORE3_A53
26617 * 0b00000000000000000000000000000000..IRQ not masked
26618 * 0b00000000000000000000000000000001..IRQ masked
26619 */
26620#define GPC_IMR_CORE3_A53_IMR1_CORE3_A53(x) \
26621 (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR1_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR1_CORE3_A53_MASK)
26622#define GPC_IMR_CORE3_A53_IMR2_CORE3_A53_MASK (0xFFFFFFFFU)
26623#define GPC_IMR_CORE3_A53_IMR2_CORE3_A53_SHIFT (0U)
26624/*! IMR2_CORE3_A53
26625 * 0b00000000000000000000000000000000..IRQ not masked
26626 * 0b00000000000000000000000000000001..IRQ masked
26627 */
26628#define GPC_IMR_CORE3_A53_IMR2_CORE3_A53(x) \
26629 (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR2_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR2_CORE3_A53_MASK)
26630#define GPC_IMR_CORE3_A53_IMR3_CORE3_A53_MASK (0xFFFFFFFFU)
26631#define GPC_IMR_CORE3_A53_IMR3_CORE3_A53_SHIFT (0U)
26632/*! IMR3_CORE3_A53
26633 * 0b00000000000000000000000000000000..IRQ not masked
26634 * 0b00000000000000000000000000000001..IRQ masked
26635 */
26636#define GPC_IMR_CORE3_A53_IMR3_CORE3_A53(x) \
26637 (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR3_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR3_CORE3_A53_MASK)
26638#define GPC_IMR_CORE3_A53_IMR4_CORE3_A53_MASK (0xFFFFFFFFU)
26639#define GPC_IMR_CORE3_A53_IMR4_CORE3_A53_SHIFT (0U)
26640/*! IMR4_CORE3_A53
26641 * 0b00000000000000000000000000000000..IRQ not masked
26642 * 0b00000000000000000000000000000001..IRQ masked
26643 */
26644#define GPC_IMR_CORE3_A53_IMR4_CORE3_A53(x) \
26645 (((uint32_t)(((uint32_t)(x)) << GPC_IMR_CORE3_A53_IMR4_CORE3_A53_SHIFT)) & GPC_IMR_CORE3_A53_IMR4_CORE3_A53_MASK)
26646/*! @} */
26647
26648/* The count of GPC_IMR_CORE3_A53 */
26649#define GPC_IMR_CORE3_A53_COUNT (4U)
26650
26651/*! @name ACK_SEL_A53_PU - PGC acknowledge signal selection of A53 platform for PUs */
26652/*! @{ */
26653#define GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK_MASK (0x4U)
26654#define GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK_SHIFT (2U)
26655#define GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK(x) \
26656 (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK_SHIFT)) & \
26657 GPC_ACK_SEL_A53_PU_MIPI_PGC_PDN_ACK_MASK)
26658#define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK_MASK (0x10U)
26659#define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK_SHIFT (4U)
26660#define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK(x) \
26661 (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK_SHIFT)) & \
26662 GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PDN_ACK_MASK)
26663#define GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK_MASK (0x80U)
26664#define GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK_SHIFT (7U)
26665#define GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK(x) \
26666 (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK_SHIFT)) & \
26667 GPC_ACK_SEL_A53_PU_DDR1_PGC_PDN_ACK_MASK)
26668#define GPC_ACK_SEL_A53_PU_GPUMIX_PGC_PDN_ACK_MASK (0x200U)
26669#define GPC_ACK_SEL_A53_PU_GPUMIX_PGC_PDN_ACK_SHIFT (9U)
26670#define GPC_ACK_SEL_A53_PU_GPUMIX_PGC_PDN_ACK(x) \
26671 (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPUMIX_PGC_PDN_ACK_SHIFT)) & \
26672 GPC_ACK_SEL_A53_PU_GPUMIX_PGC_PDN_ACK_MASK)
26673#define GPC_ACK_SEL_A53_PU_DISPMIX_PGC_PDN_ACK_MASK (0x1000U)
26674#define GPC_ACK_SEL_A53_PU_DISPMIX_PGC_PDN_ACK_SHIFT (12U)
26675#define GPC_ACK_SEL_A53_PU_DISPMIX_PGC_PDN_ACK(x) \
26676 (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DISPMIX_PGC_PDN_ACK_SHIFT)) & \
26677 GPC_ACK_SEL_A53_PU_DISPMIX_PGC_PDN_ACK_MASK)
26678#define GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK_MASK (0x40000U)
26679#define GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK_SHIFT (18U)
26680#define GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK(x) \
26681 (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK_SHIFT)) & \
26682 GPC_ACK_SEL_A53_PU_MIPI_PGC_PUP_ACK_MASK)
26683#define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK_MASK (0x100000U)
26684#define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK_SHIFT (20U)
26685#define GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK(x) \
26686 (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK_SHIFT)) & \
26687 GPC_ACK_SEL_A53_PU_USB_OTG1_PGC_PUP_ACK_MASK)
26688#define GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK_MASK (0x800000U)
26689#define GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK_SHIFT (23U)
26690#define GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK(x) \
26691 (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK_SHIFT)) & \
26692 GPC_ACK_SEL_A53_PU_DDR1_PGC_PUP_ACK_MASK)
26693#define GPC_ACK_SEL_A53_PU_GPUMIX_PGC_PUP_ACK_MASK (0x2000000U)
26694#define GPC_ACK_SEL_A53_PU_GPUMIX_PGC_PUP_ACK_SHIFT (25U)
26695#define GPC_ACK_SEL_A53_PU_GPUMIX_PGC_PUP_ACK(x) \
26696 (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_GPUMIX_PGC_PUP_ACK_SHIFT)) & \
26697 GPC_ACK_SEL_A53_PU_GPUMIX_PGC_PUP_ACK_MASK)
26698#define GPC_ACK_SEL_A53_PU_DISPMIX_PGC_PUP_ACK_MASK (0x10000000U)
26699#define GPC_ACK_SEL_A53_PU_DISPMIX_PGC_PUP_ACK_SHIFT (28U)
26700#define GPC_ACK_SEL_A53_PU_DISPMIX_PGC_PUP_ACK(x) \
26701 (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_A53_PU_DISPMIX_PGC_PUP_ACK_SHIFT)) & \
26702 GPC_ACK_SEL_A53_PU_DISPMIX_PGC_PUP_ACK_MASK)
26703/*! @} */
26704
26705/*! @name ACK_SEL_M7_PU - PGC acknowledge signal selection of M7 platform for PUs */
26706/*! @{ */
26707#define GPC_ACK_SEL_M7_PU_MIPI_PGC_PDN_ACK_MASK (0x4U)
26708#define GPC_ACK_SEL_M7_PU_MIPI_PGC_PDN_ACK_SHIFT (2U)
26709#define GPC_ACK_SEL_M7_PU_MIPI_PGC_PDN_ACK(x) \
26710 (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_MIPI_PGC_PDN_ACK_SHIFT)) & \
26711 GPC_ACK_SEL_M7_PU_MIPI_PGC_PDN_ACK_MASK)
26712#define GPC_ACK_SEL_M7_PU_USB_OTG1_PGC_PDN_ACK_MASK (0x10U)
26713#define GPC_ACK_SEL_M7_PU_USB_OTG1_PGC_PDN_ACK_SHIFT (4U)
26714#define GPC_ACK_SEL_M7_PU_USB_OTG1_PGC_PDN_ACK(x) \
26715 (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_USB_OTG1_PGC_PDN_ACK_SHIFT)) & \
26716 GPC_ACK_SEL_M7_PU_USB_OTG1_PGC_PDN_ACK_MASK)
26717#define GPC_ACK_SEL_M7_PU_DDR1_PGC_PDN_ACK_MASK (0x80U)
26718#define GPC_ACK_SEL_M7_PU_DDR1_PGC_PDN_ACK_SHIFT (7U)
26719#define GPC_ACK_SEL_M7_PU_DDR1_PGC_PDN_ACK(x) \
26720 (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_DDR1_PGC_PDN_ACK_SHIFT)) & \
26721 GPC_ACK_SEL_M7_PU_DDR1_PGC_PDN_ACK_MASK)
26722#define GPC_ACK_SEL_M7_PU_GPUMIX_PGC_PDN_ACK_MASK (0x200U)
26723#define GPC_ACK_SEL_M7_PU_GPUMIX_PGC_PDN_ACK_SHIFT (9U)
26724#define GPC_ACK_SEL_M7_PU_GPUMIX_PGC_PDN_ACK(x) \
26725 (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_GPUMIX_PGC_PDN_ACK_SHIFT)) & \
26726 GPC_ACK_SEL_M7_PU_GPUMIX_PGC_PDN_ACK_MASK)
26727#define GPC_ACK_SEL_M7_PU_DISPMIX_PGC_PDN_ACK_MASK (0x1000U)
26728#define GPC_ACK_SEL_M7_PU_DISPMIX_PGC_PDN_ACK_SHIFT (12U)
26729#define GPC_ACK_SEL_M7_PU_DISPMIX_PGC_PDN_ACK(x) \
26730 (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_DISPMIX_PGC_PDN_ACK_SHIFT)) & \
26731 GPC_ACK_SEL_M7_PU_DISPMIX_PGC_PDN_ACK_MASK)
26732#define GPC_ACK_SEL_M7_PU_MIPI_PGC_PUP_ACK_MASK (0x40000U)
26733#define GPC_ACK_SEL_M7_PU_MIPI_PGC_PUP_ACK_SHIFT (18U)
26734#define GPC_ACK_SEL_M7_PU_MIPI_PGC_PUP_ACK(x) \
26735 (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_MIPI_PGC_PUP_ACK_SHIFT)) & \
26736 GPC_ACK_SEL_M7_PU_MIPI_PGC_PUP_ACK_MASK)
26737#define GPC_ACK_SEL_M7_PU_USB_OTG1_PGC_PUP_ACK_MASK (0x100000U)
26738#define GPC_ACK_SEL_M7_PU_USB_OTG1_PGC_PUP_ACK_SHIFT (20U)
26739#define GPC_ACK_SEL_M7_PU_USB_OTG1_PGC_PUP_ACK(x) \
26740 (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_USB_OTG1_PGC_PUP_ACK_SHIFT)) & \
26741 GPC_ACK_SEL_M7_PU_USB_OTG1_PGC_PUP_ACK_MASK)
26742#define GPC_ACK_SEL_M7_PU_DDR1_PGC_PUP_ACK_MASK (0x800000U)
26743#define GPC_ACK_SEL_M7_PU_DDR1_PGC_PUP_ACK_SHIFT (23U)
26744#define GPC_ACK_SEL_M7_PU_DDR1_PGC_PUP_ACK(x) \
26745 (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_DDR1_PGC_PUP_ACK_SHIFT)) & \
26746 GPC_ACK_SEL_M7_PU_DDR1_PGC_PUP_ACK_MASK)
26747#define GPC_ACK_SEL_M7_PU_GPUMIX_PGC_PUP_ACK_MASK (0x2000000U)
26748#define GPC_ACK_SEL_M7_PU_GPUMIX_PGC_PUP_ACK_SHIFT (25U)
26749#define GPC_ACK_SEL_M7_PU_GPUMIX_PGC_PUP_ACK(x) \
26750 (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_GPUMIX_PGC_PUP_ACK_SHIFT)) & \
26751 GPC_ACK_SEL_M7_PU_GPUMIX_PGC_PUP_ACK_MASK)
26752#define GPC_ACK_SEL_M7_PU_DISPMIX_PGC_PUP_ACK_MASK (0x10000000U)
26753#define GPC_ACK_SEL_M7_PU_DISPMIX_PGC_PUP_ACK_SHIFT (28U)
26754#define GPC_ACK_SEL_M7_PU_DISPMIX_PGC_PUP_ACK(x) \
26755 (((uint32_t)(((uint32_t)(x)) << GPC_ACK_SEL_M7_PU_DISPMIX_PGC_PUP_ACK_SHIFT)) & \
26756 GPC_ACK_SEL_M7_PU_DISPMIX_PGC_PUP_ACK_MASK)
26757/*! @} */
26758
26759/*! @name SLT15_CFG - Slot configure register for PGC CPUs */
26760/*! @{ */
26761#define GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
26762#define GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
26763#define GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \
26764 (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \
26765 GPC_SLT15_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
26766#define GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
26767#define GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
26768#define GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \
26769 (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \
26770 GPC_SLT15_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
26771#define GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
26772#define GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
26773#define GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \
26774 (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \
26775 GPC_SLT15_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
26776#define GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
26777#define GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
26778#define GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \
26779 (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \
26780 GPC_SLT15_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
26781#define GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
26782#define GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
26783#define GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \
26784 (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \
26785 GPC_SLT15_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
26786#define GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
26787#define GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
26788#define GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \
26789 (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \
26790 GPC_SLT15_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
26791#define GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
26792#define GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
26793#define GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \
26794 (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \
26795 GPC_SLT15_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
26796#define GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
26797#define GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
26798#define GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \
26799 (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \
26800 GPC_SLT15_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
26801#define GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
26802#define GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
26803#define GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL(x) \
26804 (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & \
26805 GPC_SLT15_CFG_SCU_PDN_SLOT_CONTROL_MASK)
26806#define GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
26807#define GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
26808#define GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL(x) \
26809 (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & \
26810 GPC_SLT15_CFG_SCU_PUP_SLOT_CONTROL_MASK)
26811#define GPC_SLT15_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U)
26812#define GPC_SLT15_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U)
26813#define GPC_SLT15_CFG_NOC_PDN_SLOT_CONTROL(x) \
26814 (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & \
26815 GPC_SLT15_CFG_NOC_PDN_SLOT_CONTROL_MASK)
26816#define GPC_SLT15_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U)
26817#define GPC_SLT15_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U)
26818#define GPC_SLT15_CFG_NOC_PUP_SLOT_CONTROL(x) \
26819 (((uint32_t)(((uint32_t)(x)) << GPC_SLT15_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & \
26820 GPC_SLT15_CFG_NOC_PUP_SLOT_CONTROL_MASK)
26821/*! @} */
26822
26823/*! @name SLT16_CFG - Slot configure register for PGC CPUs */
26824/*! @{ */
26825#define GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
26826#define GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
26827#define GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \
26828 (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \
26829 GPC_SLT16_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
26830#define GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
26831#define GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
26832#define GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \
26833 (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \
26834 GPC_SLT16_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
26835#define GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
26836#define GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
26837#define GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \
26838 (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \
26839 GPC_SLT16_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
26840#define GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
26841#define GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
26842#define GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \
26843 (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \
26844 GPC_SLT16_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
26845#define GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
26846#define GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
26847#define GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \
26848 (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \
26849 GPC_SLT16_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
26850#define GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
26851#define GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
26852#define GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \
26853 (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \
26854 GPC_SLT16_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
26855#define GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
26856#define GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
26857#define GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \
26858 (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \
26859 GPC_SLT16_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
26860#define GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
26861#define GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
26862#define GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \
26863 (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \
26864 GPC_SLT16_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
26865#define GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
26866#define GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
26867#define GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL(x) \
26868 (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & \
26869 GPC_SLT16_CFG_SCU_PDN_SLOT_CONTROL_MASK)
26870#define GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
26871#define GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
26872#define GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL(x) \
26873 (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & \
26874 GPC_SLT16_CFG_SCU_PUP_SLOT_CONTROL_MASK)
26875#define GPC_SLT16_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U)
26876#define GPC_SLT16_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U)
26877#define GPC_SLT16_CFG_NOC_PDN_SLOT_CONTROL(x) \
26878 (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & \
26879 GPC_SLT16_CFG_NOC_PDN_SLOT_CONTROL_MASK)
26880#define GPC_SLT16_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U)
26881#define GPC_SLT16_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U)
26882#define GPC_SLT16_CFG_NOC_PUP_SLOT_CONTROL(x) \
26883 (((uint32_t)(((uint32_t)(x)) << GPC_SLT16_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & \
26884 GPC_SLT16_CFG_NOC_PUP_SLOT_CONTROL_MASK)
26885/*! @} */
26886
26887/*! @name SLT17_CFG - Slot configure register for PGC CPUs */
26888/*! @{ */
26889#define GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
26890#define GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
26891#define GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \
26892 (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \
26893 GPC_SLT17_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
26894#define GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
26895#define GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
26896#define GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \
26897 (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \
26898 GPC_SLT17_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
26899#define GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
26900#define GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
26901#define GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \
26902 (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \
26903 GPC_SLT17_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
26904#define GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
26905#define GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
26906#define GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \
26907 (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \
26908 GPC_SLT17_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
26909#define GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
26910#define GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
26911#define GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \
26912 (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \
26913 GPC_SLT17_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
26914#define GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
26915#define GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
26916#define GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \
26917 (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \
26918 GPC_SLT17_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
26919#define GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
26920#define GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
26921#define GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \
26922 (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \
26923 GPC_SLT17_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
26924#define GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
26925#define GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
26926#define GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \
26927 (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \
26928 GPC_SLT17_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
26929#define GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
26930#define GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
26931#define GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL(x) \
26932 (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & \
26933 GPC_SLT17_CFG_SCU_PDN_SLOT_CONTROL_MASK)
26934#define GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
26935#define GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
26936#define GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL(x) \
26937 (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & \
26938 GPC_SLT17_CFG_SCU_PUP_SLOT_CONTROL_MASK)
26939#define GPC_SLT17_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U)
26940#define GPC_SLT17_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U)
26941#define GPC_SLT17_CFG_NOC_PDN_SLOT_CONTROL(x) \
26942 (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & \
26943 GPC_SLT17_CFG_NOC_PDN_SLOT_CONTROL_MASK)
26944#define GPC_SLT17_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U)
26945#define GPC_SLT17_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U)
26946#define GPC_SLT17_CFG_NOC_PUP_SLOT_CONTROL(x) \
26947 (((uint32_t)(((uint32_t)(x)) << GPC_SLT17_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & \
26948 GPC_SLT17_CFG_NOC_PUP_SLOT_CONTROL_MASK)
26949/*! @} */
26950
26951/*! @name SLT18_CFG - Slot configure register for PGC CPUs */
26952/*! @{ */
26953#define GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
26954#define GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
26955#define GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \
26956 (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \
26957 GPC_SLT18_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
26958#define GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
26959#define GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
26960#define GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \
26961 (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \
26962 GPC_SLT18_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
26963#define GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
26964#define GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
26965#define GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \
26966 (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \
26967 GPC_SLT18_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
26968#define GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
26969#define GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
26970#define GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \
26971 (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \
26972 GPC_SLT18_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
26973#define GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
26974#define GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
26975#define GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \
26976 (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \
26977 GPC_SLT18_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
26978#define GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
26979#define GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
26980#define GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \
26981 (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \
26982 GPC_SLT18_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
26983#define GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
26984#define GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
26985#define GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \
26986 (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \
26987 GPC_SLT18_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
26988#define GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
26989#define GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
26990#define GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \
26991 (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \
26992 GPC_SLT18_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
26993#define GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
26994#define GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
26995#define GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL(x) \
26996 (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & \
26997 GPC_SLT18_CFG_SCU_PDN_SLOT_CONTROL_MASK)
26998#define GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
26999#define GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
27000#define GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL(x) \
27001 (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & \
27002 GPC_SLT18_CFG_SCU_PUP_SLOT_CONTROL_MASK)
27003#define GPC_SLT18_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U)
27004#define GPC_SLT18_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U)
27005#define GPC_SLT18_CFG_NOC_PDN_SLOT_CONTROL(x) \
27006 (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & \
27007 GPC_SLT18_CFG_NOC_PDN_SLOT_CONTROL_MASK)
27008#define GPC_SLT18_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U)
27009#define GPC_SLT18_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U)
27010#define GPC_SLT18_CFG_NOC_PUP_SLOT_CONTROL(x) \
27011 (((uint32_t)(((uint32_t)(x)) << GPC_SLT18_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & \
27012 GPC_SLT18_CFG_NOC_PUP_SLOT_CONTROL_MASK)
27013/*! @} */
27014
27015/*! @name SLT19_CFG - Slot configure register for PGC CPUs */
27016/*! @{ */
27017#define GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK (0x1U)
27018#define GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT (0U)
27019#define GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL(x) \
27020 (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL_SHIFT)) & \
27021 GPC_SLT19_CFG_CORE0_A53_PDN_SLOT_CONTROL_MASK)
27022#define GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK (0x2U)
27023#define GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT (1U)
27024#define GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL(x) \
27025 (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL_SHIFT)) & \
27026 GPC_SLT19_CFG_CORE0_A53_PUP_SLOT_CONTROL_MASK)
27027#define GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK (0x4U)
27028#define GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT (2U)
27029#define GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL(x) \
27030 (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL_SHIFT)) & \
27031 GPC_SLT19_CFG_CORE1_A53_PDN_SLOT_CONTROL_MASK)
27032#define GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK (0x8U)
27033#define GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT (3U)
27034#define GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL(x) \
27035 (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL_SHIFT)) & \
27036 GPC_SLT19_CFG_CORE1_A53_PUP_SLOT_CONTROL_MASK)
27037#define GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK (0x10U)
27038#define GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT (4U)
27039#define GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL(x) \
27040 (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL_SHIFT)) & \
27041 GPC_SLT19_CFG_CORE2_A53_PDN_SLOT_CONTROL_MASK)
27042#define GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK (0x20U)
27043#define GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT (5U)
27044#define GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL(x) \
27045 (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL_SHIFT)) & \
27046 GPC_SLT19_CFG_CORE2_A53_PUP_SLOT_CONTROL_MASK)
27047#define GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK (0x40U)
27048#define GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT (6U)
27049#define GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL(x) \
27050 (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL_SHIFT)) & \
27051 GPC_SLT19_CFG_CORE3_A53_PDN_SLOT_CONTROL_MASK)
27052#define GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK (0x80U)
27053#define GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT (7U)
27054#define GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL(x) \
27055 (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL_SHIFT)) & \
27056 GPC_SLT19_CFG_CORE3_A53_PUP_SLOT_CONTROL_MASK)
27057#define GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL_MASK (0x100U)
27058#define GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL_SHIFT (8U)
27059#define GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL(x) \
27060 (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL_SHIFT)) & \
27061 GPC_SLT19_CFG_SCU_PDN_SLOT_CONTROL_MASK)
27062#define GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL_MASK (0x200U)
27063#define GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL_SHIFT (9U)
27064#define GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL(x) \
27065 (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL_SHIFT)) & \
27066 GPC_SLT19_CFG_SCU_PUP_SLOT_CONTROL_MASK)
27067#define GPC_SLT19_CFG_NOC_PDN_SLOT_CONTROL_MASK (0x400U)
27068#define GPC_SLT19_CFG_NOC_PDN_SLOT_CONTROL_SHIFT (10U)
27069#define GPC_SLT19_CFG_NOC_PDN_SLOT_CONTROL(x) \
27070 (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_NOC_PDN_SLOT_CONTROL_SHIFT)) & \
27071 GPC_SLT19_CFG_NOC_PDN_SLOT_CONTROL_MASK)
27072#define GPC_SLT19_CFG_NOC_PUP_SLOT_CONTROL_MASK (0x800U)
27073#define GPC_SLT19_CFG_NOC_PUP_SLOT_CONTROL_SHIFT (11U)
27074#define GPC_SLT19_CFG_NOC_PUP_SLOT_CONTROL(x) \
27075 (((uint32_t)(((uint32_t)(x)) << GPC_SLT19_CFG_NOC_PUP_SLOT_CONTROL_SHIFT)) & \
27076 GPC_SLT19_CFG_NOC_PUP_SLOT_CONTROL_MASK)
27077/*! @} */
27078
27079/*! @name PU_PWRHSK - Power handshake register */
27080/*! @{ */
27081#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_MASK (0x1U)
27082#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_SHIFT (0U)
27083#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ(x) \
27084 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_SHIFT)) & \
27085 GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSREQ_MASK)
27086#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_MASK (0x2U)
27087#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_SHIFT (1U)
27088#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ(x) \
27089 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_SHIFT)) & \
27090 GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSREQ_MASK)
27091#define GPC_PU_PWRHSK_GPC_NOC2DDR_PWRDNREQN_MASK (0x4U)
27092#define GPC_PU_PWRHSK_GPC_NOC2DDR_PWRDNREQN_SHIFT (2U)
27093#define GPC_PU_PWRHSK_GPC_NOC2DDR_PWRDNREQN(x) \
27094 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2DDR_PWRDNREQN_SHIFT)) & \
27095 GPC_PU_PWRHSK_GPC_NOC2DDR_PWRDNREQN_MASK)
27096#define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNREQN_MASK (0x8U)
27097#define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNREQN_SHIFT (3U)
27098#define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNREQN(x) \
27099 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNREQN_SHIFT)) & \
27100 GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNREQN_MASK)
27101#define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNREQN_MASK (0x10U)
27102#define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNREQN_SHIFT (4U)
27103#define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNREQN(x) \
27104 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNREQN_SHIFT)) & \
27105 GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNREQN_MASK)
27106#define GPC_PU_PWRHSK_GPC_HSIOMIX2NOC_PWRDNREQN_MASK (0x20U)
27107#define GPC_PU_PWRHSK_GPC_HSIOMIX2NOC_PWRDNREQN_SHIFT (5U)
27108#define GPC_PU_PWRHSK_GPC_HSIOMIX2NOC_PWRDNREQN(x) \
27109 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_HSIOMIX2NOC_PWRDNREQN_SHIFT)) & \
27110 GPC_PU_PWRHSK_GPC_HSIOMIX2NOC_PWRDNREQN_MASK)
27111#define GPC_PU_PWRHSK_GPC_DISPMIX2NOC_PWRDNREQN_MASK (0x80U)
27112#define GPC_PU_PWRHSK_GPC_DISPMIX2NOC_PWRDNREQN_SHIFT (7U)
27113#define GPC_PU_PWRHSK_GPC_DISPMIX2NOC_PWRDNREQN(x) \
27114 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DISPMIX2NOC_PWRDNREQN_SHIFT)) & \
27115 GPC_PU_PWRHSK_GPC_DISPMIX2NOC_PWRDNREQN_MASK)
27116#define GPC_PU_PWRHSK_GPC_GPUPMIX2NOC_PWRDNREQN_MASK (0x200U)
27117#define GPC_PU_PWRHSK_GPC_GPUPMIX2NOC_PWRDNREQN_SHIFT (9U)
27118#define GPC_PU_PWRHSK_GPC_GPUPMIX2NOC_PWRDNREQN(x) \
27119 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_GPUPMIX2NOC_PWRDNREQN_SHIFT)) & \
27120 GPC_PU_PWRHSK_GPC_GPUPMIX2NOC_PWRDNREQN_MASK)
27121#define GPC_PU_PWRHSK_GPC_NOC2GPUPMIX_PWRDNREQN_MASK (0x800U)
27122#define GPC_PU_PWRHSK_GPC_NOC2GPUPMIX_PWRDNREQN_SHIFT (11U)
27123#define GPC_PU_PWRHSK_GPC_NOC2GPUPMIX_PWRDNREQN(x) \
27124 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2GPUPMIX_PWRDNREQN_SHIFT)) & \
27125 GPC_PU_PWRHSK_GPC_NOC2GPUPMIX_PWRDNREQN_MASK)
27126#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK_MASK (0x10000U)
27127#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK_SHIFT (16U)
27128#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK(x) \
27129 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK_SHIFT)) & \
27130 GPC_PU_PWRHSK_GPC_DDR1_CORE_CSYSACK_MASK)
27131#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE_MASK (0x20000U)
27132#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE_SHIFT (17U)
27133#define GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE(x) \
27134 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE_SHIFT)) & \
27135 GPC_PU_PWRHSK_GPC_DDR1_CORE_CACTIVE_MASK)
27136#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK_MASK (0x40000U)
27137#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK_SHIFT (18U)
27138#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK(x) \
27139 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK_SHIFT)) & \
27140 GPC_PU_PWRHSK_GPC_DDR1_AXI_CSYSACK_MASK)
27141#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE_MASK (0x80000U)
27142#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE_SHIFT (19U)
27143#define GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE(x) \
27144 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE_SHIFT)) & \
27145 GPC_PU_PWRHSK_GPC_DDR1_AXI_CACTIVE_MASK)
27146#define GPC_PU_PWRHSK_GPC_NOC2DDR1_PWRDNACKN_MASK (0x100000U)
27147#define GPC_PU_PWRHSK_GPC_NOC2DDR1_PWRDNACKN_SHIFT (20U)
27148#define GPC_PU_PWRHSK_GPC_NOC2DDR1_PWRDNACKN(x) \
27149 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2DDR1_PWRDNACKN_SHIFT)) & \
27150 GPC_PU_PWRHSK_GPC_NOC2DDR1_PWRDNACKN_MASK)
27151#define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNACKN_MASK (0x200000U)
27152#define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNACKN_SHIFT (21U)
27153#define GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNACKN(x) \
27154 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNACKN_SHIFT)) & \
27155 GPC_PU_PWRHSK_GPC_SUPERMIX2NOC_PWRDNACKN_MASK)
27156#define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNACKN_MASK (0x400000U)
27157#define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNACKN_SHIFT (22U)
27158#define GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNACKN(x) \
27159 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNACKN_SHIFT)) & \
27160 GPC_PU_PWRHSK_GPC_NOC2SUPERMIX_PWRDNACKN_MASK)
27161#define GPC_PU_PWRHSK_GPC_HSIOMIX2NOC_PWRDNACKN_MASK (0x800000U)
27162#define GPC_PU_PWRHSK_GPC_HSIOMIX2NOC_PWRDNACKN_SHIFT (23U)
27163#define GPC_PU_PWRHSK_GPC_HSIOMIX2NOC_PWRDNACKN(x) \
27164 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_HSIOMIX2NOC_PWRDNACKN_SHIFT)) & \
27165 GPC_PU_PWRHSK_GPC_HSIOMIX2NOC_PWRDNACKN_MASK)
27166#define GPC_PU_PWRHSK_GPC_DISPMIX2NOC_PWRDNACKN_MASK (0x2000000U)
27167#define GPC_PU_PWRHSK_GPC_DISPMIX2NOC_PWRDNACKN_SHIFT (25U)
27168#define GPC_PU_PWRHSK_GPC_DISPMIX2NOC_PWRDNACKN(x) \
27169 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_DISPMIX2NOC_PWRDNACKN_SHIFT)) & \
27170 GPC_PU_PWRHSK_GPC_DISPMIX2NOC_PWRDNACKN_MASK)
27171#define GPC_PU_PWRHSK_GPC_GPUMIX2NOC_PWRDNACKN_MASK (0x8000000U)
27172#define GPC_PU_PWRHSK_GPC_GPUMIX2NOC_PWRDNACKN_SHIFT (27U)
27173#define GPC_PU_PWRHSK_GPC_GPUMIX2NOC_PWRDNACKN(x) \
27174 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_GPUMIX2NOC_PWRDNACKN_SHIFT)) & \
27175 GPC_PU_PWRHSK_GPC_GPUMIX2NOC_PWRDNACKN_MASK)
27176#define GPC_PU_PWRHSK_GPC_NOC2GPUMIX_PWRDNACKN_MASK (0x20000000U)
27177#define GPC_PU_PWRHSK_GPC_NOC2GPUMIX_PWRDNACKN_SHIFT (29U)
27178#define GPC_PU_PWRHSK_GPC_NOC2GPUMIX_PWRDNACKN(x) \
27179 (((uint32_t)(((uint32_t)(x)) << GPC_PU_PWRHSK_GPC_NOC2GPUMIX_PWRDNACKN_SHIFT)) & \
27180 GPC_PU_PWRHSK_GPC_NOC2GPUMIX_PWRDNACKN_MASK)
27181/*! @} */
27182
27183/*! @name SLT_CFG_PU - Slot configure register for PGC PUs */
27184/*! @{ */
27185#define GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL_MASK (0x4U)
27186#define GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL_SHIFT (2U)
27187#define GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL(x) \
27188 (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL_SHIFT)) & \
27189 GPC_SLT_CFG_PU_MIPI_PDN_SLOT_CONTROL_MASK)
27190#define GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL_MASK (0x8U)
27191#define GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL_SHIFT (3U)
27192#define GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL(x) \
27193 (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL_SHIFT)) & \
27194 GPC_SLT_CFG_PU_MIPI_PUP_SLOT_CONTROL_MASK)
27195#define GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL_MASK (0x40U)
27196#define GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL_SHIFT (6U)
27197#define GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL(x) \
27198 (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL_SHIFT)) & \
27199 GPC_SLT_CFG_PU_OTG1_PDN_SLOT_CONTROL_MASK)
27200#define GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL_MASK (0x80U)
27201#define GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL_SHIFT (7U)
27202#define GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL(x) \
27203 (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL_SHIFT)) & \
27204 GPC_SLT_CFG_PU_OTG1_PUP_SLOT_CONTROL_MASK)
27205#define GPC_SLT_CFG_PU_M7_PDN_SLOT_CONTROL_MASK (0x1000U)
27206#define GPC_SLT_CFG_PU_M7_PDN_SLOT_CONTROL_SHIFT (12U)
27207#define GPC_SLT_CFG_PU_M7_PDN_SLOT_CONTROL(x) \
27208 (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_M7_PDN_SLOT_CONTROL_SHIFT)) & \
27209 GPC_SLT_CFG_PU_M7_PDN_SLOT_CONTROL_MASK)
27210#define GPC_SLT_CFG_PU_M7_PUP_SLOT_CONTROL_MASK (0x2000U)
27211#define GPC_SLT_CFG_PU_M7_PUP_SLOT_CONTROL_SHIFT (13U)
27212#define GPC_SLT_CFG_PU_M7_PUP_SLOT_CONTROL(x) \
27213 (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_M7_PUP_SLOT_CONTROL_SHIFT)) & \
27214 GPC_SLT_CFG_PU_M7_PUP_SLOT_CONTROL_MASK)
27215#define GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL_MASK (0x4000U)
27216#define GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL_SHIFT (14U)
27217#define GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL(x) \
27218 (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL_SHIFT)) & \
27219 GPC_SLT_CFG_PU_DDR1_PDN_SLOT_CONTROL_MASK)
27220#define GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL_MASK (0x8000U)
27221#define GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL_SHIFT (15U)
27222#define GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL(x) \
27223 (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL_SHIFT)) & \
27224 GPC_SLT_CFG_PU_DDR1_PUP_SLOT_CONTROL_MASK)
27225#define GPC_SLT_CFG_PU_GPUMIX_PDN_SLOT_CONTROL_MASK (0x40000U)
27226#define GPC_SLT_CFG_PU_GPUMIX_PDN_SLOT_CONTROL_SHIFT (18U)
27227#define GPC_SLT_CFG_PU_GPUMIX_PDN_SLOT_CONTROL(x) \
27228 (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPUMIX_PDN_SLOT_CONTROL_SHIFT)) & \
27229 GPC_SLT_CFG_PU_GPUMIX_PDN_SLOT_CONTROL_MASK)
27230#define GPC_SLT_CFG_PU_GPUMIX_PUP_SLOT_CONTROL_MASK (0x80000U)
27231#define GPC_SLT_CFG_PU_GPUMIX_PUP_SLOT_CONTROL_SHIFT (19U)
27232#define GPC_SLT_CFG_PU_GPUMIX_PUP_SLOT_CONTROL(x) \
27233 (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_GPUMIX_PUP_SLOT_CONTROL_SHIFT)) & \
27234 GPC_SLT_CFG_PU_GPUMIX_PUP_SLOT_CONTROL_MASK)
27235#define GPC_SLT_CFG_PU_DISPMIX_PDN_SLOT_CONTROL_MASK (0x1000000U)
27236#define GPC_SLT_CFG_PU_DISPMIX_PDN_SLOT_CONTROL_SHIFT (24U)
27237#define GPC_SLT_CFG_PU_DISPMIX_PDN_SLOT_CONTROL(x) \
27238 (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DISPMIX_PDN_SLOT_CONTROL_SHIFT)) & \
27239 GPC_SLT_CFG_PU_DISPMIX_PDN_SLOT_CONTROL_MASK)
27240#define GPC_SLT_CFG_PU_DISPMIX_PUP_SLOT_CONTROL_MASK (0x2000000U)
27241#define GPC_SLT_CFG_PU_DISPMIX_PUP_SLOT_CONTROL_SHIFT (25U)
27242#define GPC_SLT_CFG_PU_DISPMIX_PUP_SLOT_CONTROL(x) \
27243 (((uint32_t)(((uint32_t)(x)) << GPC_SLT_CFG_PU_DISPMIX_PUP_SLOT_CONTROL_SHIFT)) & \
27244 GPC_SLT_CFG_PU_DISPMIX_PUP_SLOT_CONTROL_MASK)
27245/*! @} */
27246
27247/* The count of GPC_SLT_CFG_PU */
27248#define GPC_SLT_CFG_PU_COUNT (20U)
27249
27250/*!
27251 * @}
27252 */ /* end of group GPC_Register_Masks */
27253
27254/* GPC - Peripheral instance base addresses */
27255/** Peripheral GPC base address */
27256#define GPC_BASE (0x303A0000u)
27257/** Peripheral GPC base pointer */
27258#define GPC ((GPC_Type *)GPC_BASE)
27259/** Array initializer of GPC peripheral base addresses */
27260#define GPC_BASE_ADDRS \
27261 { \
27262 GPC_BASE \
27263 }
27264/** Array initializer of GPC peripheral base pointers */
27265#define GPC_BASE_PTRS \
27266 { \
27267 GPC \
27268 }
27269/** Interrupt vectors for the GPC peripheral type */
27270#define GPC_IRQS \
27271 { \
27272 GPC_IRQn \
27273 }
27274
27275/*!
27276 * @}
27277 */ /* end of group GPC_Peripheral_Access_Layer */
27278
27279/* ----------------------------------------------------------------------------
27280 -- GPC_PGC Peripheral Access Layer
27281 ---------------------------------------------------------------------------- */
27282
27283/*!
27284 * @addtogroup GPC_PGC_Peripheral_Access_Layer GPC_PGC Peripheral Access Layer
27285 * @{
27286 */
27287
27288/** GPC_PGC - Register Layout Typedef */
27289typedef struct
27290{
27291 uint8_t RESERVED_0[2048];
27292 struct
27293 { /* offset: 0x800, array step: 0x40 */
27294 __IO uint32_t PGC_CTRL; /**< GPC PGC Control Register for PGC CPUs, array offset: 0x800, array step: 0x40 */
27295 __IO uint32_t PGC_PUPSCR; /**< GPC PGC Up Sequence Control Register, array offset: 0x804, array step: 0x40 */
27296 __IO uint32_t PGC_PDNSCR; /**< GPC PGC Down Sequence Control Register, array offset: 0x808, array step: 0x40 */
27297 __IO uint32_t PGC_SR; /**< GPC PGC Status Register, array offset: 0x80C, array step: 0x40 */
27298 uint8_t RESERVED_0[48];
27299 } GPC_PGC_A53COREnCTRL[4];
27300 __IO uint32_t A53SCU_CTRL; /**< GPC PGC Control Register for PGC CPUs, offset: 0x900 */
27301 __IO uint32_t A53SCU_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0x904 */
27302 __IO uint32_t A53SCU_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0x908 */
27303 __IO uint32_t A53SCU_SR; /**< GPC PGC Status Register, offset: 0x90C */
27304 __IO uint32_t A53SCU_AUXSW; /**< GPC PGC Auxiliary Power Switch Control Register, offset: 0x910 */
27305 uint8_t RESERVED_1[300];
27306 __IO uint32_t NOC_MIX_CTRL; /**< GPC PGC Control Register for PGC MIX., offset: 0xA40 */
27307 __IO uint32_t NOC_MIX_PUPSCR; /**< GPC PGC Up Sequence Control Register, offset: 0xA44 */
27308 __IO uint32_t NOC_MIX_PDNSCR; /**< GPC PGC Down Sequence Control Register, offset: 0xA48 */
27309 __IO uint32_t NOC_MIX_SR; /**< GPC PGC Status Register, offset: 0xA4C */
27310 uint8_t RESERVED_2[432];
27311 struct
27312 { /* offset: 0xC00, array step: 0x40 */
27313 __IO uint32_t PU_CTRL; /**< GPC PGC Control Register for PGC PUs, array offset: 0xC00, array step: 0x40 */
27314 __IO uint32_t PU_PUPSCR; /**< GPC PGC Up Sequence Control Register, array offset: 0xC04, array step: 0x40 */
27315 __IO uint32_t PU_PDNSCR; /**< GPC PGC Down Sequence Control Register, array offset: 0xC08, array step: 0x40 */
27316 __IO uint32_t PU_SR; /**< GPC PGC Status Register, array offset: 0xC0C, array step: 0x40 */
27317 uint8_t RESERVED_0[48];
27318 } GPC_PGC_CTRL[14];
27319} GPC_PGC_Type;
27320
27321/* ----------------------------------------------------------------------------
27322 -- GPC_PGC Register Masks
27323 ---------------------------------------------------------------------------- */
27324
27325/*!
27326 * @addtogroup GPC_PGC_Register_Masks GPC_PGC Register Masks
27327 * @{
27328 */
27329
27330/*! @name PGC_CTRL - GPC PGC Control Register for PGC CPUs */
27331/*! @{ */
27332#define GPC_PGC_PGC_CTRL_PCR_MASK (0x1U)
27333#define GPC_PGC_PGC_CTRL_PCR_SHIFT (0U)
27334/*! PCR
27335 * 0b0..Do not switch off power even if pdn_req is asserted.
27336 * 0b1..Switch off power when pdn_req is asserted.
27337 */
27338#define GPC_PGC_PGC_CTRL_PCR(x) \
27339 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_CTRL_PCR_SHIFT)) & GPC_PGC_PGC_CTRL_PCR_MASK)
27340#define GPC_PGC_PGC_CTRL_L2RSTDIS_MASK (0x7EU)
27341#define GPC_PGC_PGC_CTRL_L2RSTDIS_SHIFT (1U)
27342#define GPC_PGC_PGC_CTRL_L2RSTDIS(x) \
27343 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PGC_CTRL_L2RSTDIS_MASK)
27344#define GPC_PGC_PGC_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
27345#define GPC_PGC_PGC_CTRL_DFTRAM_TCD1_SHIFT (8U)
27346#define GPC_PGC_PGC_CTRL_DFTRAM_TCD1(x) \
27347 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PGC_CTRL_DFTRAM_TCD1_MASK)
27348#define GPC_PGC_PGC_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
27349#define GPC_PGC_PGC_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
27350#define GPC_PGC_PGC_CTRL_L2RETN_TCD1_TDR(x) \
27351 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PGC_CTRL_L2RETN_TCD1_TDR_MASK)
27352#define GPC_PGC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
27353#define GPC_PGC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
27354#define GPC_PGC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM(x) \
27355 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & \
27356 GPC_PGC_PGC_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
27357/*! @} */
27358
27359/* The count of GPC_PGC_PGC_CTRL */
27360#define GPC_PGC_PGC_CTRL_COUNT (4U)
27361
27362/*! @name PGC_PUPSCR - GPC PGC Up Sequence Control Register */
27363/*! @{ */
27364#define GPC_PGC_PGC_PUPSCR_SW_MASK (0x3FU)
27365#define GPC_PGC_PGC_PUPSCR_SW_SHIFT (0U)
27366#define GPC_PGC_PGC_PUPSCR_SW(x) \
27367 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_PUPSCR_SW_SHIFT)) & GPC_PGC_PGC_PUPSCR_SW_MASK)
27368#define GPC_PGC_PGC_PUPSCR_SW2ISO_MASK (0x7FFF80U)
27369#define GPC_PGC_PGC_PUPSCR_SW2ISO_SHIFT (7U)
27370#define GPC_PGC_PGC_PUPSCR_SW2ISO(x) \
27371 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PGC_PUPSCR_SW2ISO_MASK)
27372/*! @} */
27373
27374/* The count of GPC_PGC_PGC_PUPSCR */
27375#define GPC_PGC_PGC_PUPSCR_COUNT (4U)
27376
27377/*! @name PGC_PDNSCR - GPC PGC Down Sequence Control Register */
27378/*! @{ */
27379#define GPC_PGC_PGC_PDNSCR_ISO_MASK (0x3FU)
27380#define GPC_PGC_PGC_PDNSCR_ISO_SHIFT (0U)
27381#define GPC_PGC_PGC_PDNSCR_ISO(x) \
27382 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_PDNSCR_ISO_SHIFT)) & GPC_PGC_PGC_PDNSCR_ISO_MASK)
27383#define GPC_PGC_PGC_PDNSCR_ISO2SW_MASK (0x3F00U)
27384#define GPC_PGC_PGC_PDNSCR_ISO2SW_SHIFT (8U)
27385#define GPC_PGC_PGC_PDNSCR_ISO2SW(x) \
27386 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PGC_PDNSCR_ISO2SW_MASK)
27387/*! @} */
27388
27389/* The count of GPC_PGC_PGC_PDNSCR */
27390#define GPC_PGC_PGC_PDNSCR_COUNT (4U)
27391
27392/*! @name PGC_SR - GPC PGC Status Register */
27393/*! @{ */
27394#define GPC_PGC_PGC_SR_PSR_MASK (0x1U)
27395#define GPC_PGC_PGC_SR_PSR_SHIFT (0U)
27396/*! PSR
27397 * 0b0..The target subsystem was not powered down for the previous power-down request.
27398 * 0b1..The target subsystem was powered down for the previous power-down request.
27399 */
27400#define GPC_PGC_PGC_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_SR_PSR_SHIFT)) & GPC_PGC_PGC_SR_PSR_MASK)
27401#define GPC_PGC_PGC_SR_L2RETN_FLAG_MASK (0x2U)
27402#define GPC_PGC_PGC_SR_L2RETN_FLAG_SHIFT (1U)
27403/*! L2RETN_FLAG
27404 * 0b0..A53 is not wakeup from L2 retention mode.
27405 * 0b1..A53 is wakeup from L2 retention mode.
27406 */
27407#define GPC_PGC_PGC_SR_L2RETN_FLAG(x) \
27408 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PGC_SR_L2RETN_FLAG_MASK)
27409#define GPC_PGC_PGC_SR_ALLOFF_FLAG_MASK (0x4U)
27410#define GPC_PGC_PGC_SR_ALLOFF_FLAG_SHIFT (2U)
27411/*! ALLOFF_FLAG
27412 * 0b0..A53 is not wakeup from ALL_OFF mode.
27413 * 0b1..A53 is wakeup from ALL_OFF mode.
27414 */
27415#define GPC_PGC_PGC_SR_ALLOFF_FLAG(x) \
27416 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PGC_SR_ALLOFF_FLAG_MASK)
27417#define GPC_PGC_PGC_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
27418#define GPC_PGC_PGC_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
27419/*! PUP_CLK_DIV_SEL
27420 * 0b0000..1
27421 * 0b0001..1/2 count_clk
27422 * 0b0010..1/4 count_clk
27423 * 0b0011..1/8 count_clk
27424 * 0b0100..1/16 count_clk
27425 * 0b0101..1/32 count_clk
27426 * 0b0110..1/64 count_clk
27427 * 0b0111..1/128 count_clk
27428 * 0b1000..1/256 count_clk
27429 * 0b1001..1/512 count_clk
27430 * 0b1010..1/1024 count_clk
27431 * 0b1011..1/2056 count_clk
27432 * 0b1100..1/4096 count_clk
27433 * 0b1101..1/8192 count_clk
27434 * 0b1110..1/16384 count_clk
27435 * 0b1111..1/32768 count_clk
27436 */
27437#define GPC_PGC_PGC_SR_PUP_CLK_DIV_SEL(x) \
27438 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PGC_SR_PUP_CLK_DIV_SEL_MASK)
27439#define GPC_PGC_PGC_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
27440#define GPC_PGC_PGC_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
27441#define GPC_PGC_PGC_SR_L2RSTDIS_DEASSERT_CNT(x) \
27442 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PGC_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & \
27443 GPC_PGC_PGC_SR_L2RSTDIS_DEASSERT_CNT_MASK)
27444/*! @} */
27445
27446/* The count of GPC_PGC_PGC_SR */
27447#define GPC_PGC_PGC_SR_COUNT (4U)
27448
27449/*! @name A53SCU_CTRL - GPC PGC Control Register for PGC CPUs */
27450/*! @{ */
27451#define GPC_PGC_A53SCU_CTRL_PCR_MASK (0x1U)
27452#define GPC_PGC_A53SCU_CTRL_PCR_SHIFT (0U)
27453/*! PCR
27454 * 0b0..Do not switch off power even if pdn_req is asserted.
27455 * 0b1..Switch off power when pdn_req is asserted.
27456 */
27457#define GPC_PGC_A53SCU_CTRL_PCR(x) \
27458 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_PCR_SHIFT)) & GPC_PGC_A53SCU_CTRL_PCR_MASK)
27459#define GPC_PGC_A53SCU_CTRL_L2RSTDIS_MASK (0x7EU)
27460#define GPC_PGC_A53SCU_CTRL_L2RSTDIS_SHIFT (1U)
27461#define GPC_PGC_A53SCU_CTRL_L2RSTDIS(x) \
27462 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_A53SCU_CTRL_L2RSTDIS_MASK)
27463#define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
27464#define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_SHIFT (8U)
27465#define GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1(x) \
27466 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_A53SCU_CTRL_DFTRAM_TCD1_MASK)
27467#define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
27468#define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
27469#define GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR(x) \
27470 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_SHIFT)) & \
27471 GPC_PGC_A53SCU_CTRL_L2RETN_TCD1_TDR_MASK)
27472#define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
27473#define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
27474#define GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM(x) \
27475 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & \
27476 GPC_PGC_A53SCU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
27477/*! @} */
27478
27479/*! @name A53SCU_PUPSCR - GPC PGC Up Sequence Control Register */
27480/*! @{ */
27481#define GPC_PGC_A53SCU_PUPSCR_SW_MASK (0x3FU)
27482#define GPC_PGC_A53SCU_PUPSCR_SW_SHIFT (0U)
27483#define GPC_PGC_A53SCU_PUPSCR_SW(x) \
27484 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PUPSCR_SW_SHIFT)) & GPC_PGC_A53SCU_PUPSCR_SW_MASK)
27485#define GPC_PGC_A53SCU_PUPSCR_SW2ISO_MASK (0x7FFF80U)
27486#define GPC_PGC_A53SCU_PUPSCR_SW2ISO_SHIFT (7U)
27487#define GPC_PGC_A53SCU_PUPSCR_SW2ISO(x) \
27488 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_A53SCU_PUPSCR_SW2ISO_MASK)
27489/*! @} */
27490
27491/*! @name A53SCU_PDNSCR - GPC PGC Down Sequence Control Register */
27492/*! @{ */
27493#define GPC_PGC_A53SCU_PDNSCR_ISO_MASK (0x3FU)
27494#define GPC_PGC_A53SCU_PDNSCR_ISO_SHIFT (0U)
27495#define GPC_PGC_A53SCU_PDNSCR_ISO(x) \
27496 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_ISO_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_ISO_MASK)
27497#define GPC_PGC_A53SCU_PDNSCR_ISO2SW_MASK (0x3F00U)
27498#define GPC_PGC_A53SCU_PDNSCR_ISO2SW_SHIFT (8U)
27499#define GPC_PGC_A53SCU_PDNSCR_ISO2SW(x) \
27500 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_A53SCU_PDNSCR_ISO2SW_MASK)
27501/*! @} */
27502
27503/*! @name A53SCU_SR - GPC PGC Status Register */
27504/*! @{ */
27505#define GPC_PGC_A53SCU_SR_PSR_MASK (0x1U)
27506#define GPC_PGC_A53SCU_SR_PSR_SHIFT (0U)
27507/*! PSR
27508 * 0b0..The target subsystem was not powered down for the previous power-down request.
27509 * 0b1..The target subsystem was powered down for the previous power-down request.
27510 */
27511#define GPC_PGC_A53SCU_SR_PSR(x) \
27512 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_PSR_SHIFT)) & GPC_PGC_A53SCU_SR_PSR_MASK)
27513#define GPC_PGC_A53SCU_SR_L2RETN_FLAG_MASK (0x2U)
27514#define GPC_PGC_A53SCU_SR_L2RETN_FLAG_SHIFT (1U)
27515/*! L2RETN_FLAG
27516 * 0b0..A53 is not wakeup from L2 retention mode.
27517 * 0b1..A53 is wakeup from L2 retention mode.
27518 */
27519#define GPC_PGC_A53SCU_SR_L2RETN_FLAG(x) \
27520 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_A53SCU_SR_L2RETN_FLAG_MASK)
27521#define GPC_PGC_A53SCU_SR_ALLOFF_FLAG_MASK (0x4U)
27522#define GPC_PGC_A53SCU_SR_ALLOFF_FLAG_SHIFT (2U)
27523/*! ALLOFF_FLAG
27524 * 0b0..A53 is not wakeup from ALL_OFF mode.
27525 * 0b1..A53 is wakeup from ALL_OFF mode.
27526 */
27527#define GPC_PGC_A53SCU_SR_ALLOFF_FLAG(x) \
27528 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_A53SCU_SR_ALLOFF_FLAG_MASK)
27529#define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
27530#define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
27531/*! PUP_CLK_DIV_SEL
27532 * 0b0000..1
27533 * 0b0001..1/2 count_clk
27534 * 0b0010..1/4 count_clk
27535 * 0b0011..1/8 count_clk
27536 * 0b0100..1/16 count_clk
27537 * 0b0101..1/32 count_clk
27538 * 0b0110..1/64 count_clk
27539 * 0b0111..1/128 count_clk
27540 * 0b1000..1/256 count_clk
27541 * 0b1001..1/512 count_clk
27542 * 0b1010..1/1024 count_clk
27543 * 0b1011..1/2056 count_clk
27544 * 0b1100..1/4096 count_clk
27545 * 0b1101..1/8192 count_clk
27546 * 0b1110..1/16384 count_clk
27547 * 0b1111..1/32768 count_clk
27548 */
27549#define GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL(x) \
27550 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_A53SCU_SR_PUP_CLK_DIV_SEL_MASK)
27551#define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
27552#define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
27553#define GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT(x) \
27554 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & \
27555 GPC_PGC_A53SCU_SR_L2RSTDIS_DEASSERT_CNT_MASK)
27556/*! @} */
27557
27558/*! @name A53SCU_AUXSW - GPC PGC Auxiliary Power Switch Control Register */
27559/*! @{ */
27560#define GPC_PGC_A53SCU_AUXSW_DFTRAM_TRC1_TMC_TMR_TCD2_MASK (0x3FFU)
27561#define GPC_PGC_A53SCU_AUXSW_DFTRAM_TRC1_TMC_TMR_TCD2_SHIFT (0U)
27562#define GPC_PGC_A53SCU_AUXSW_DFTRAM_TRC1_TMC_TMR_TCD2(x) \
27563 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_AUXSW_DFTRAM_TRC1_TMC_TMR_TCD2_SHIFT)) & \
27564 GPC_PGC_A53SCU_AUXSW_DFTRAM_TRC1_TMC_TMR_TCD2_MASK)
27565#define GPC_PGC_A53SCU_AUXSW_L2RETN_RTC1_TMC_TMR_MASK (0xFFC00U)
27566#define GPC_PGC_A53SCU_AUXSW_L2RETN_RTC1_TMC_TMR_SHIFT (10U)
27567#define GPC_PGC_A53SCU_AUXSW_L2RETN_RTC1_TMC_TMR(x) \
27568 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_AUXSW_L2RETN_RTC1_TMC_TMR_SHIFT)) & \
27569 GPC_PGC_A53SCU_AUXSW_L2RETN_RTC1_TMC_TMR_MASK)
27570#define GPC_PGC_A53SCU_AUXSW_MEMPWR_TRC1_TMC_MASK (0x3FF00000U)
27571#define GPC_PGC_A53SCU_AUXSW_MEMPWR_TRC1_TMC_SHIFT (20U)
27572#define GPC_PGC_A53SCU_AUXSW_MEMPWR_TRC1_TMC(x) \
27573 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_A53SCU_AUXSW_MEMPWR_TRC1_TMC_SHIFT)) & \
27574 GPC_PGC_A53SCU_AUXSW_MEMPWR_TRC1_TMC_MASK)
27575/*! @} */
27576
27577/*! @name NOC_MIX_CTRL - GPC PGC Control Register for PGC MIX. */
27578/*! @{ */
27579#define GPC_PGC_NOC_MIX_CTRL_MIX_PCR_MASK (0x1U)
27580#define GPC_PGC_NOC_MIX_CTRL_MIX_PCR_SHIFT (0U)
27581/*! MIX_PCR
27582 * 0b0..Do not switch off power even if pdn_req is asserted.
27583 * 0b1..Switch off power when pdn_req is asserted.
27584 */
27585#define GPC_PGC_NOC_MIX_CTRL_MIX_PCR(x) \
27586 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_CTRL_MIX_PCR_SHIFT)) & GPC_PGC_NOC_MIX_CTRL_MIX_PCR_MASK)
27587#define GPC_PGC_NOC_MIX_CTRL_L2RSTDIS_MASK (0x7EU)
27588#define GPC_PGC_NOC_MIX_CTRL_L2RSTDIS_SHIFT (1U)
27589#define GPC_PGC_NOC_MIX_CTRL_L2RSTDIS(x) \
27590 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_NOC_MIX_CTRL_L2RSTDIS_MASK)
27591#define GPC_PGC_NOC_MIX_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
27592#define GPC_PGC_NOC_MIX_CTRL_DFTRAM_TCD1_SHIFT (8U)
27593#define GPC_PGC_NOC_MIX_CTRL_DFTRAM_TCD1(x) \
27594 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_NOC_MIX_CTRL_DFTRAM_TCD1_MASK)
27595#define GPC_PGC_NOC_MIX_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
27596#define GPC_PGC_NOC_MIX_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
27597#define GPC_PGC_NOC_MIX_CTRL_L2RETN_TCD1_TDR(x) \
27598 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_CTRL_L2RETN_TCD1_TDR_SHIFT)) & \
27599 GPC_PGC_NOC_MIX_CTRL_L2RETN_TCD1_TDR_MASK)
27600#define GPC_PGC_NOC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
27601#define GPC_PGC_NOC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
27602#define GPC_PGC_NOC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM(x) \
27603 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & \
27604 GPC_PGC_NOC_MIX_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
27605/*! @} */
27606
27607/*! @name NOC_MIX_PUPSCR - GPC PGC Up Sequence Control Register */
27608/*! @{ */
27609#define GPC_PGC_NOC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_MASK (0x40U)
27610#define GPC_PGC_NOC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT (6U)
27611#define GPC_PGC_NOC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT(x) \
27612 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_SHIFT)) & \
27613 GPC_PGC_NOC_MIX_PUPSCR_PUP_WAIT_SCALL_OUT_MASK)
27614#define GPC_PGC_NOC_MIX_PUPSCR_SW2ISO_MASK (0x7FFF80U)
27615#define GPC_PGC_NOC_MIX_PUPSCR_SW2ISO_SHIFT (7U)
27616#define GPC_PGC_NOC_MIX_PUPSCR_SW2ISO(x) \
27617 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_NOC_MIX_PUPSCR_SW2ISO_MASK)
27618/*! @} */
27619
27620/*! @name NOC_MIX_PDNSCR - GPC PGC Down Sequence Control Register */
27621/*! @{ */
27622#define GPC_PGC_NOC_MIX_PDNSCR_ISO_MASK (0x3FU)
27623#define GPC_PGC_NOC_MIX_PDNSCR_ISO_SHIFT (0U)
27624#define GPC_PGC_NOC_MIX_PDNSCR_ISO(x) \
27625 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_PDNSCR_ISO_SHIFT)) & GPC_PGC_NOC_MIX_PDNSCR_ISO_MASK)
27626#define GPC_PGC_NOC_MIX_PDNSCR_ISO2SW_MASK (0x3F00U)
27627#define GPC_PGC_NOC_MIX_PDNSCR_ISO2SW_SHIFT (8U)
27628#define GPC_PGC_NOC_MIX_PDNSCR_ISO2SW(x) \
27629 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_NOC_MIX_PDNSCR_ISO2SW_MASK)
27630/*! @} */
27631
27632/*! @name NOC_MIX_SR - GPC PGC Status Register */
27633/*! @{ */
27634#define GPC_PGC_NOC_MIX_SR_PSR_MASK (0x1U)
27635#define GPC_PGC_NOC_MIX_SR_PSR_SHIFT (0U)
27636/*! PSR
27637 * 0b0..The target subsystem was not powered down for the previous power-down request.
27638 * 0b1..The target subsystem was powered down for the previous power-down request.
27639 */
27640#define GPC_PGC_NOC_MIX_SR_PSR(x) \
27641 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_SR_PSR_SHIFT)) & GPC_PGC_NOC_MIX_SR_PSR_MASK)
27642#define GPC_PGC_NOC_MIX_SR_L2RETN_FLAG_MASK (0x2U)
27643#define GPC_PGC_NOC_MIX_SR_L2RETN_FLAG_SHIFT (1U)
27644/*! L2RETN_FLAG
27645 * 0b0..A53 is not wakeup from L2 retention mode.
27646 * 0b1..A53 is wakeup from L2 retention mode.
27647 */
27648#define GPC_PGC_NOC_MIX_SR_L2RETN_FLAG(x) \
27649 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_NOC_MIX_SR_L2RETN_FLAG_MASK)
27650#define GPC_PGC_NOC_MIX_SR_ALLOFF_FLAG_MASK (0x4U)
27651#define GPC_PGC_NOC_MIX_SR_ALLOFF_FLAG_SHIFT (2U)
27652/*! ALLOFF_FLAG
27653 * 0b0..A53 is not wakeup from ALL_OFF mode.
27654 * 0b1..A53 is wakeup from ALL_OFF mode.
27655 */
27656#define GPC_PGC_NOC_MIX_SR_ALLOFF_FLAG(x) \
27657 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_NOC_MIX_SR_ALLOFF_FLAG_MASK)
27658#define GPC_PGC_NOC_MIX_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
27659#define GPC_PGC_NOC_MIX_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
27660/*! PUP_CLK_DIV_SEL
27661 * 0b0000..1
27662 * 0b0001..1/2 count_clk
27663 * 0b0010..1/4 count_clk
27664 * 0b0011..1/8 count_clk
27665 * 0b0100..1/16 count_clk
27666 * 0b0101..1/32 count_clk
27667 * 0b0110..1/64 count_clk
27668 * 0b0111..1/128 count_clk
27669 * 0b1000..1/256 count_clk
27670 * 0b1001..1/512 count_clk
27671 * 0b1010..1/1024 count_clk
27672 * 0b1011..1/2056 count_clk
27673 * 0b1100..1/4096 count_clk
27674 * 0b1101..1/8192 count_clk
27675 * 0b1110..1/16384 count_clk
27676 * 0b1111..1/32768 count_clk
27677 */
27678#define GPC_PGC_NOC_MIX_SR_PUP_CLK_DIV_SEL(x) \
27679 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_SR_PUP_CLK_DIV_SEL_SHIFT)) & \
27680 GPC_PGC_NOC_MIX_SR_PUP_CLK_DIV_SEL_MASK)
27681#define GPC_PGC_NOC_MIX_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
27682#define GPC_PGC_NOC_MIX_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
27683#define GPC_PGC_NOC_MIX_SR_L2RSTDIS_DEASSERT_CNT(x) \
27684 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_NOC_MIX_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & \
27685 GPC_PGC_NOC_MIX_SR_L2RSTDIS_DEASSERT_CNT_MASK)
27686/*! @} */
27687
27688/*! @name PU_CTRL - GPC PGC Control Register for PGC PUs */
27689/*! @{ */
27690#define GPC_PGC_PU_CTRL_PCR_MASK (0x1U)
27691#define GPC_PGC_PU_CTRL_PCR_SHIFT (0U)
27692/*! PCR
27693 * 0b0..Do not switch off power even if pdn_req is asserted.
27694 * 0b1..Switch off power when pdn_req is asserted.
27695 */
27696#define GPC_PGC_PU_CTRL_PCR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_CTRL_PCR_SHIFT)) & GPC_PGC_PU_CTRL_PCR_MASK)
27697#define GPC_PGC_PU_CTRL_L2RSTDIS_MASK (0x7EU)
27698#define GPC_PGC_PU_CTRL_L2RSTDIS_SHIFT (1U)
27699#define GPC_PGC_PU_CTRL_L2RSTDIS(x) \
27700 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_CTRL_L2RSTDIS_SHIFT)) & GPC_PGC_PU_CTRL_L2RSTDIS_MASK)
27701#define GPC_PGC_PU_CTRL_DFTRAM_TCD1_MASK (0x3F00U)
27702#define GPC_PGC_PU_CTRL_DFTRAM_TCD1_SHIFT (8U)
27703#define GPC_PGC_PU_CTRL_DFTRAM_TCD1(x) \
27704 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_CTRL_DFTRAM_TCD1_SHIFT)) & GPC_PGC_PU_CTRL_DFTRAM_TCD1_MASK)
27705#define GPC_PGC_PU_CTRL_L2RETN_TCD1_TDR_MASK (0x3F0000U)
27706#define GPC_PGC_PU_CTRL_L2RETN_TCD1_TDR_SHIFT (16U)
27707#define GPC_PGC_PU_CTRL_L2RETN_TCD1_TDR(x) \
27708 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_CTRL_L2RETN_TCD1_TDR_SHIFT)) & GPC_PGC_PU_CTRL_L2RETN_TCD1_TDR_MASK)
27709#define GPC_PGC_PU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK (0x3F000000U)
27710#define GPC_PGC_PU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT (24U)
27711#define GPC_PGC_PU_CTRL_MEMPWR_TCD1_TDR_TRM(x) \
27712 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_CTRL_MEMPWR_TCD1_TDR_TRM_SHIFT)) & \
27713 GPC_PGC_PU_CTRL_MEMPWR_TCD1_TDR_TRM_MASK)
27714/*! @} */
27715
27716/* The count of GPC_PGC_PU_CTRL */
27717#define GPC_PGC_PU_CTRL_COUNT (14U)
27718
27719/*! @name PU_PUPSCR - GPC PGC Up Sequence Control Register */
27720/*! @{ */
27721#define GPC_PGC_PU_PUPSCR_SW_MASK (0x3FU)
27722#define GPC_PGC_PU_PUPSCR_SW_SHIFT (0U)
27723#define GPC_PGC_PU_PUPSCR_SW(x) \
27724 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_PUPSCR_SW_SHIFT)) & GPC_PGC_PU_PUPSCR_SW_MASK)
27725#define GPC_PGC_PU_PUPSCR_SW2ISO_MASK (0x7FFF80U)
27726#define GPC_PGC_PU_PUPSCR_SW2ISO_SHIFT (7U)
27727#define GPC_PGC_PU_PUPSCR_SW2ISO(x) \
27728 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_PUPSCR_SW2ISO_SHIFT)) & GPC_PGC_PU_PUPSCR_SW2ISO_MASK)
27729/*! @} */
27730
27731/* The count of GPC_PGC_PU_PUPSCR */
27732#define GPC_PGC_PU_PUPSCR_COUNT (14U)
27733
27734/*! @name PU_PDNSCR - GPC PGC Down Sequence Control Register */
27735/*! @{ */
27736#define GPC_PGC_PU_PDNSCR_ISO_MASK (0x3FU)
27737#define GPC_PGC_PU_PDNSCR_ISO_SHIFT (0U)
27738#define GPC_PGC_PU_PDNSCR_ISO(x) \
27739 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_PDNSCR_ISO_SHIFT)) & GPC_PGC_PU_PDNSCR_ISO_MASK)
27740#define GPC_PGC_PU_PDNSCR_ISO2SW_MASK (0x3F00U)
27741#define GPC_PGC_PU_PDNSCR_ISO2SW_SHIFT (8U)
27742#define GPC_PGC_PU_PDNSCR_ISO2SW(x) \
27743 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_PDNSCR_ISO2SW_SHIFT)) & GPC_PGC_PU_PDNSCR_ISO2SW_MASK)
27744/*! @} */
27745
27746/* The count of GPC_PGC_PU_PDNSCR */
27747#define GPC_PGC_PU_PDNSCR_COUNT (14U)
27748
27749/*! @name PU_SR - GPC PGC Status Register */
27750/*! @{ */
27751#define GPC_PGC_PU_SR_PSR_MASK (0x1U)
27752#define GPC_PGC_PU_SR_PSR_SHIFT (0U)
27753/*! PSR
27754 * 0b0..The target subsystem was not powered down for the previous power-down request.
27755 * 0b1..The target subsystem was powered down for the previous power-down request.
27756 */
27757#define GPC_PGC_PU_SR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_SR_PSR_SHIFT)) & GPC_PGC_PU_SR_PSR_MASK)
27758#define GPC_PGC_PU_SR_L2RETN_FLAG_MASK (0x2U)
27759#define GPC_PGC_PU_SR_L2RETN_FLAG_SHIFT (1U)
27760/*! L2RETN_FLAG
27761 * 0b0..A53 is not wakeup from L2 retention mode.
27762 * 0b1..A53 is wakeup from L2 retention mode.
27763 */
27764#define GPC_PGC_PU_SR_L2RETN_FLAG(x) \
27765 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_SR_L2RETN_FLAG_SHIFT)) & GPC_PGC_PU_SR_L2RETN_FLAG_MASK)
27766#define GPC_PGC_PU_SR_ALLOFF_FLAG_MASK (0x4U)
27767#define GPC_PGC_PU_SR_ALLOFF_FLAG_SHIFT (2U)
27768/*! ALLOFF_FLAG
27769 * 0b0..A53 is not wakeup from ALL_OFF mode.
27770 * 0b1..A53 is wakeup from ALL_OFF mode.
27771 */
27772#define GPC_PGC_PU_SR_ALLOFF_FLAG(x) \
27773 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_SR_ALLOFF_FLAG_SHIFT)) & GPC_PGC_PU_SR_ALLOFF_FLAG_MASK)
27774#define GPC_PGC_PU_SR_PUP_CLK_DIV_SEL_MASK (0x78U)
27775#define GPC_PGC_PU_SR_PUP_CLK_DIV_SEL_SHIFT (3U)
27776/*! PUP_CLK_DIV_SEL
27777 * 0b0000..1
27778 * 0b0001..1/2 count_clk
27779 * 0b0010..1/4 count_clk
27780 * 0b0011..1/8 count_clk
27781 * 0b0100..1/16 count_clk
27782 * 0b0101..1/32 count_clk
27783 * 0b0110..1/64 count_clk
27784 * 0b0111..1/128 count_clk
27785 * 0b1000..1/256 count_clk
27786 * 0b1001..1/512 count_clk
27787 * 0b1010..1/1024 count_clk
27788 * 0b1011..1/2056 count_clk
27789 * 0b1100..1/4096 count_clk
27790 * 0b1101..1/8192 count_clk
27791 * 0b1110..1/16384 count_clk
27792 * 0b1111..1/32768 count_clk
27793 */
27794#define GPC_PGC_PU_SR_PUP_CLK_DIV_SEL(x) \
27795 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_SR_PUP_CLK_DIV_SEL_SHIFT)) & GPC_PGC_PU_SR_PUP_CLK_DIV_SEL_MASK)
27796#define GPC_PGC_PU_SR_L2RSTDIS_DEASSERT_CNT_MASK (0x3FF00U)
27797#define GPC_PGC_PU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT (8U)
27798#define GPC_PGC_PU_SR_L2RSTDIS_DEASSERT_CNT(x) \
27799 (((uint32_t)(((uint32_t)(x)) << GPC_PGC_PU_SR_L2RSTDIS_DEASSERT_CNT_SHIFT)) & \
27800 GPC_PGC_PU_SR_L2RSTDIS_DEASSERT_CNT_MASK)
27801/*! @} */
27802
27803/* The count of GPC_PGC_PU_SR */
27804#define GPC_PGC_PU_SR_COUNT (14U)
27805
27806/*!
27807 * @}
27808 */ /* end of group GPC_PGC_Register_Masks */
27809
27810/* GPC_PGC - Peripheral instance base addresses */
27811/** Peripheral GPC_PGC base address */
27812#define GPC_PGC_BASE (0x303A0000u)
27813/** Peripheral GPC_PGC base pointer */
27814#define GPC_PGC ((GPC_PGC_Type *)GPC_PGC_BASE)
27815/** Array initializer of GPC_PGC peripheral base addresses */
27816#define GPC_PGC_BASE_ADDRS \
27817 { \
27818 GPC_PGC_BASE \
27819 }
27820/** Array initializer of GPC_PGC peripheral base pointers */
27821#define GPC_PGC_BASE_PTRS \
27822 { \
27823 GPC_PGC \
27824 }
27825
27826/*!
27827 * @}
27828 */ /* end of group GPC_PGC_Peripheral_Access_Layer */
27829
27830/* ----------------------------------------------------------------------------
27831 -- GPIO Peripheral Access Layer
27832 ---------------------------------------------------------------------------- */
27833
27834/*!
27835 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
27836 * @{
27837 */
27838
27839/** GPIO - Register Layout Typedef */
27840typedef struct
27841{
27842 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */
27843 __IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */
27844 __I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */
27845 __IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */
27846 __IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */
27847 __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */
27848 __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */
27849 __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */
27850} GPIO_Type;
27851
27852/* ----------------------------------------------------------------------------
27853 -- GPIO Register Masks
27854 ---------------------------------------------------------------------------- */
27855
27856/*!
27857 * @addtogroup GPIO_Register_Masks GPIO Register Masks
27858 * @{
27859 */
27860
27861/*! @name DR - GPIO data register */
27862/*! @{ */
27863#define GPIO_DR_DR_MASK (0xFFFFFFFFU)
27864#define GPIO_DR_DR_SHIFT (0U)
27865#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
27866/*! @} */
27867
27868/*! @name GDIR - GPIO direction register */
27869/*! @{ */
27870#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU)
27871#define GPIO_GDIR_GDIR_SHIFT (0U)
27872/*! GDIR
27873 * 0b00000000000000000000000000000000..GPIO is configured as input.
27874 * 0b00000000000000000000000000000001..GPIO is configured as output.
27875 */
27876#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
27877/*! @} */
27878
27879/*! @name PSR - GPIO pad status register */
27880/*! @{ */
27881#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU)
27882#define GPIO_PSR_PSR_SHIFT (0U)
27883#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
27884/*! @} */
27885
27886/*! @name ICR1 - GPIO interrupt configuration register1 */
27887/*! @{ */
27888#define GPIO_ICR1_ICR0_MASK (0x3U)
27889#define GPIO_ICR1_ICR0_SHIFT (0U)
27890/*! ICR0
27891 * 0b00..Interrupt n is low-level sensitive.
27892 * 0b01..Interrupt n is high-level sensitive.
27893 * 0b10..Interrupt n is rising-edge sensitive.
27894 * 0b11..Interrupt n is falling-edge sensitive.
27895 */
27896#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
27897#define GPIO_ICR1_ICR1_MASK (0xCU)
27898#define GPIO_ICR1_ICR1_SHIFT (2U)
27899/*! ICR1
27900 * 0b00..Interrupt n is low-level sensitive.
27901 * 0b01..Interrupt n is high-level sensitive.
27902 * 0b10..Interrupt n is rising-edge sensitive.
27903 * 0b11..Interrupt n is falling-edge sensitive.
27904 */
27905#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
27906#define GPIO_ICR1_ICR2_MASK (0x30U)
27907#define GPIO_ICR1_ICR2_SHIFT (4U)
27908/*! ICR2
27909 * 0b00..Interrupt n is low-level sensitive.
27910 * 0b01..Interrupt n is high-level sensitive.
27911 * 0b10..Interrupt n is rising-edge sensitive.
27912 * 0b11..Interrupt n is falling-edge sensitive.
27913 */
27914#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
27915#define GPIO_ICR1_ICR3_MASK (0xC0U)
27916#define GPIO_ICR1_ICR3_SHIFT (6U)
27917/*! ICR3
27918 * 0b00..Interrupt n is low-level sensitive.
27919 * 0b01..Interrupt n is high-level sensitive.
27920 * 0b10..Interrupt n is rising-edge sensitive.
27921 * 0b11..Interrupt n is falling-edge sensitive.
27922 */
27923#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
27924#define GPIO_ICR1_ICR4_MASK (0x300U)
27925#define GPIO_ICR1_ICR4_SHIFT (8U)
27926/*! ICR4
27927 * 0b00..Interrupt n is low-level sensitive.
27928 * 0b01..Interrupt n is high-level sensitive.
27929 * 0b10..Interrupt n is rising-edge sensitive.
27930 * 0b11..Interrupt n is falling-edge sensitive.
27931 */
27932#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
27933#define GPIO_ICR1_ICR5_MASK (0xC00U)
27934#define GPIO_ICR1_ICR5_SHIFT (10U)
27935/*! ICR5
27936 * 0b00..Interrupt n is low-level sensitive.
27937 * 0b01..Interrupt n is high-level sensitive.
27938 * 0b10..Interrupt n is rising-edge sensitive.
27939 * 0b11..Interrupt n is falling-edge sensitive.
27940 */
27941#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
27942#define GPIO_ICR1_ICR6_MASK (0x3000U)
27943#define GPIO_ICR1_ICR6_SHIFT (12U)
27944/*! ICR6
27945 * 0b00..Interrupt n is low-level sensitive.
27946 * 0b01..Interrupt n is high-level sensitive.
27947 * 0b10..Interrupt n is rising-edge sensitive.
27948 * 0b11..Interrupt n is falling-edge sensitive.
27949 */
27950#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
27951#define GPIO_ICR1_ICR7_MASK (0xC000U)
27952#define GPIO_ICR1_ICR7_SHIFT (14U)
27953/*! ICR7
27954 * 0b00..Interrupt n is low-level sensitive.
27955 * 0b01..Interrupt n is high-level sensitive.
27956 * 0b10..Interrupt n is rising-edge sensitive.
27957 * 0b11..Interrupt n is falling-edge sensitive.
27958 */
27959#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
27960#define GPIO_ICR1_ICR8_MASK (0x30000U)
27961#define GPIO_ICR1_ICR8_SHIFT (16U)
27962/*! ICR8
27963 * 0b00..Interrupt n is low-level sensitive.
27964 * 0b01..Interrupt n is high-level sensitive.
27965 * 0b10..Interrupt n is rising-edge sensitive.
27966 * 0b11..Interrupt n is falling-edge sensitive.
27967 */
27968#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
27969#define GPIO_ICR1_ICR9_MASK (0xC0000U)
27970#define GPIO_ICR1_ICR9_SHIFT (18U)
27971/*! ICR9
27972 * 0b00..Interrupt n is low-level sensitive.
27973 * 0b01..Interrupt n is high-level sensitive.
27974 * 0b10..Interrupt n is rising-edge sensitive.
27975 * 0b11..Interrupt n is falling-edge sensitive.
27976 */
27977#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
27978#define GPIO_ICR1_ICR10_MASK (0x300000U)
27979#define GPIO_ICR1_ICR10_SHIFT (20U)
27980/*! ICR10
27981 * 0b00..Interrupt n is low-level sensitive.
27982 * 0b01..Interrupt n is high-level sensitive.
27983 * 0b10..Interrupt n is rising-edge sensitive.
27984 * 0b11..Interrupt n is falling-edge sensitive.
27985 */
27986#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
27987#define GPIO_ICR1_ICR11_MASK (0xC00000U)
27988#define GPIO_ICR1_ICR11_SHIFT (22U)
27989/*! ICR11
27990 * 0b00..Interrupt n is low-level sensitive.
27991 * 0b01..Interrupt n is high-level sensitive.
27992 * 0b10..Interrupt n is rising-edge sensitive.
27993 * 0b11..Interrupt n is falling-edge sensitive.
27994 */
27995#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
27996#define GPIO_ICR1_ICR12_MASK (0x3000000U)
27997#define GPIO_ICR1_ICR12_SHIFT (24U)
27998/*! ICR12
27999 * 0b00..Interrupt n is low-level sensitive.
28000 * 0b01..Interrupt n is high-level sensitive.
28001 * 0b10..Interrupt n is rising-edge sensitive.
28002 * 0b11..Interrupt n is falling-edge sensitive.
28003 */
28004#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
28005#define GPIO_ICR1_ICR13_MASK (0xC000000U)
28006#define GPIO_ICR1_ICR13_SHIFT (26U)
28007/*! ICR13
28008 * 0b00..Interrupt n is low-level sensitive.
28009 * 0b01..Interrupt n is high-level sensitive.
28010 * 0b10..Interrupt n is rising-edge sensitive.
28011 * 0b11..Interrupt n is falling-edge sensitive.
28012 */
28013#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
28014#define GPIO_ICR1_ICR14_MASK (0x30000000U)
28015#define GPIO_ICR1_ICR14_SHIFT (28U)
28016/*! ICR14
28017 * 0b00..Interrupt n is low-level sensitive.
28018 * 0b01..Interrupt n is high-level sensitive.
28019 * 0b10..Interrupt n is rising-edge sensitive.
28020 * 0b11..Interrupt n is falling-edge sensitive.
28021 */
28022#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
28023#define GPIO_ICR1_ICR15_MASK (0xC0000000U)
28024#define GPIO_ICR1_ICR15_SHIFT (30U)
28025/*! ICR15
28026 * 0b00..Interrupt n is low-level sensitive.
28027 * 0b01..Interrupt n is high-level sensitive.
28028 * 0b10..Interrupt n is rising-edge sensitive.
28029 * 0b11..Interrupt n is falling-edge sensitive.
28030 */
28031#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
28032/*! @} */
28033
28034/*! @name ICR2 - GPIO interrupt configuration register2 */
28035/*! @{ */
28036#define GPIO_ICR2_ICR16_MASK (0x3U)
28037#define GPIO_ICR2_ICR16_SHIFT (0U)
28038/*! ICR16
28039 * 0b00..Interrupt n is low-level sensitive.
28040 * 0b01..Interrupt n is high-level sensitive.
28041 * 0b10..Interrupt n is rising-edge sensitive.
28042 * 0b11..Interrupt n is falling-edge sensitive.
28043 */
28044#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
28045#define GPIO_ICR2_ICR17_MASK (0xCU)
28046#define GPIO_ICR2_ICR17_SHIFT (2U)
28047/*! ICR17
28048 * 0b00..Interrupt n is low-level sensitive.
28049 * 0b01..Interrupt n is high-level sensitive.
28050 * 0b10..Interrupt n is rising-edge sensitive.
28051 * 0b11..Interrupt n is falling-edge sensitive.
28052 */
28053#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
28054#define GPIO_ICR2_ICR18_MASK (0x30U)
28055#define GPIO_ICR2_ICR18_SHIFT (4U)
28056/*! ICR18
28057 * 0b00..Interrupt n is low-level sensitive.
28058 * 0b01..Interrupt n is high-level sensitive.
28059 * 0b10..Interrupt n is rising-edge sensitive.
28060 * 0b11..Interrupt n is falling-edge sensitive.
28061 */
28062#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
28063#define GPIO_ICR2_ICR19_MASK (0xC0U)
28064#define GPIO_ICR2_ICR19_SHIFT (6U)
28065/*! ICR19
28066 * 0b00..Interrupt n is low-level sensitive.
28067 * 0b01..Interrupt n is high-level sensitive.
28068 * 0b10..Interrupt n is rising-edge sensitive.
28069 * 0b11..Interrupt n is falling-edge sensitive.
28070 */
28071#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
28072#define GPIO_ICR2_ICR20_MASK (0x300U)
28073#define GPIO_ICR2_ICR20_SHIFT (8U)
28074/*! ICR20
28075 * 0b00..Interrupt n is low-level sensitive.
28076 * 0b01..Interrupt n is high-level sensitive.
28077 * 0b10..Interrupt n is rising-edge sensitive.
28078 * 0b11..Interrupt n is falling-edge sensitive.
28079 */
28080#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
28081#define GPIO_ICR2_ICR21_MASK (0xC00U)
28082#define GPIO_ICR2_ICR21_SHIFT (10U)
28083/*! ICR21
28084 * 0b00..Interrupt n is low-level sensitive.
28085 * 0b01..Interrupt n is high-level sensitive.
28086 * 0b10..Interrupt n is rising-edge sensitive.
28087 * 0b11..Interrupt n is falling-edge sensitive.
28088 */
28089#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
28090#define GPIO_ICR2_ICR22_MASK (0x3000U)
28091#define GPIO_ICR2_ICR22_SHIFT (12U)
28092/*! ICR22
28093 * 0b00..Interrupt n is low-level sensitive.
28094 * 0b01..Interrupt n is high-level sensitive.
28095 * 0b10..Interrupt n is rising-edge sensitive.
28096 * 0b11..Interrupt n is falling-edge sensitive.
28097 */
28098#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
28099#define GPIO_ICR2_ICR23_MASK (0xC000U)
28100#define GPIO_ICR2_ICR23_SHIFT (14U)
28101/*! ICR23
28102 * 0b00..Interrupt n is low-level sensitive.
28103 * 0b01..Interrupt n is high-level sensitive.
28104 * 0b10..Interrupt n is rising-edge sensitive.
28105 * 0b11..Interrupt n is falling-edge sensitive.
28106 */
28107#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
28108#define GPIO_ICR2_ICR24_MASK (0x30000U)
28109#define GPIO_ICR2_ICR24_SHIFT (16U)
28110/*! ICR24
28111 * 0b00..Interrupt n is low-level sensitive.
28112 * 0b01..Interrupt n is high-level sensitive.
28113 * 0b10..Interrupt n is rising-edge sensitive.
28114 * 0b11..Interrupt n is falling-edge sensitive.
28115 */
28116#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
28117#define GPIO_ICR2_ICR25_MASK (0xC0000U)
28118#define GPIO_ICR2_ICR25_SHIFT (18U)
28119/*! ICR25
28120 * 0b00..Interrupt n is low-level sensitive.
28121 * 0b01..Interrupt n is high-level sensitive.
28122 * 0b10..Interrupt n is rising-edge sensitive.
28123 * 0b11..Interrupt n is falling-edge sensitive.
28124 */
28125#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
28126#define GPIO_ICR2_ICR26_MASK (0x300000U)
28127#define GPIO_ICR2_ICR26_SHIFT (20U)
28128/*! ICR26
28129 * 0b00..Interrupt n is low-level sensitive.
28130 * 0b01..Interrupt n is high-level sensitive.
28131 * 0b10..Interrupt n is rising-edge sensitive.
28132 * 0b11..Interrupt n is falling-edge sensitive.
28133 */
28134#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
28135#define GPIO_ICR2_ICR27_MASK (0xC00000U)
28136#define GPIO_ICR2_ICR27_SHIFT (22U)
28137/*! ICR27
28138 * 0b00..Interrupt n is low-level sensitive.
28139 * 0b01..Interrupt n is high-level sensitive.
28140 * 0b10..Interrupt n is rising-edge sensitive.
28141 * 0b11..Interrupt n is falling-edge sensitive.
28142 */
28143#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
28144#define GPIO_ICR2_ICR28_MASK (0x3000000U)
28145#define GPIO_ICR2_ICR28_SHIFT (24U)
28146/*! ICR28
28147 * 0b00..Interrupt n is low-level sensitive.
28148 * 0b01..Interrupt n is high-level sensitive.
28149 * 0b10..Interrupt n is rising-edge sensitive.
28150 * 0b11..Interrupt n is falling-edge sensitive.
28151 */
28152#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
28153#define GPIO_ICR2_ICR29_MASK (0xC000000U)
28154#define GPIO_ICR2_ICR29_SHIFT (26U)
28155/*! ICR29
28156 * 0b00..Interrupt n is low-level sensitive.
28157 * 0b01..Interrupt n is high-level sensitive.
28158 * 0b10..Interrupt n is rising-edge sensitive.
28159 * 0b11..Interrupt n is falling-edge sensitive.
28160 */
28161#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
28162#define GPIO_ICR2_ICR30_MASK (0x30000000U)
28163#define GPIO_ICR2_ICR30_SHIFT (28U)
28164/*! ICR30
28165 * 0b00..Interrupt n is low-level sensitive.
28166 * 0b01..Interrupt n is high-level sensitive.
28167 * 0b10..Interrupt n is rising-edge sensitive.
28168 * 0b11..Interrupt n is falling-edge sensitive.
28169 */
28170#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
28171#define GPIO_ICR2_ICR31_MASK (0xC0000000U)
28172#define GPIO_ICR2_ICR31_SHIFT (30U)
28173/*! ICR31
28174 * 0b00..Interrupt n is low-level sensitive.
28175 * 0b01..Interrupt n is high-level sensitive.
28176 * 0b10..Interrupt n is rising-edge sensitive.
28177 * 0b11..Interrupt n is falling-edge sensitive.
28178 */
28179#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
28180/*! @} */
28181
28182/*! @name IMR - GPIO interrupt mask register */
28183/*! @{ */
28184#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU)
28185#define GPIO_IMR_IMR_SHIFT (0U)
28186/*! IMR
28187 * 0b00000000000000000000000000000000..Interrupt n is disabled.
28188 * 0b00000000000000000000000000000001..Interrupt n is enabled.
28189 */
28190#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
28191/*! @} */
28192
28193/*! @name ISR - GPIO interrupt status register */
28194/*! @{ */
28195#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU)
28196#define GPIO_ISR_ISR_SHIFT (0U)
28197#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
28198/*! @} */
28199
28200/*! @name EDGE_SEL - GPIO edge select register */
28201/*! @{ */
28202#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU)
28203#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U)
28204#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) \
28205 (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
28206/*! @} */
28207
28208/*!
28209 * @}
28210 */ /* end of group GPIO_Register_Masks */
28211
28212/* GPIO - Peripheral instance base addresses */
28213/** Peripheral GPIO1 base address */
28214#define GPIO1_BASE (0x30200000u)
28215/** Peripheral GPIO1 base pointer */
28216#define GPIO1 ((GPIO_Type *)GPIO1_BASE)
28217/** Peripheral GPIO2 base address */
28218#define GPIO2_BASE (0x30210000u)
28219/** Peripheral GPIO2 base pointer */
28220#define GPIO2 ((GPIO_Type *)GPIO2_BASE)
28221/** Peripheral GPIO3 base address */
28222#define GPIO3_BASE (0x30220000u)
28223/** Peripheral GPIO3 base pointer */
28224#define GPIO3 ((GPIO_Type *)GPIO3_BASE)
28225/** Peripheral GPIO4 base address */
28226#define GPIO4_BASE (0x30230000u)
28227/** Peripheral GPIO4 base pointer */
28228#define GPIO4 ((GPIO_Type *)GPIO4_BASE)
28229/** Peripheral GPIO5 base address */
28230#define GPIO5_BASE (0x30240000u)
28231/** Peripheral GPIO5 base pointer */
28232#define GPIO5 ((GPIO_Type *)GPIO5_BASE)
28233/** Array initializer of GPIO peripheral base addresses */
28234#define GPIO_BASE_ADDRS \
28235 { \
28236 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE \
28237 }
28238/** Array initializer of GPIO peripheral base pointers */
28239#define GPIO_BASE_PTRS \
28240 { \
28241 (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5 \
28242 }
28243/** Interrupt vectors for the GPIO peripheral type */
28244#define GPIO_IRQS \
28245 { \
28246 NotAvail_IRQn, GPIO1_INT0_IRQn, GPIO1_INT1_IRQn, GPIO1_INT2_IRQn, GPIO1_INT3_IRQn, GPIO1_INT4_IRQn, \
28247 GPIO1_INT5_IRQn, GPIO1_INT6_IRQn, GPIO1_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, \
28248 NotAvail_IRQn \
28249 }
28250#define GPIO_COMBINED_LOW_IRQS \
28251 { \
28252 NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, \
28253 GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn \
28254 }
28255#define GPIO_COMBINED_HIGH_IRQS \
28256 { \
28257 NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, \
28258 GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn \
28259 }
28260
28261/*!
28262 * @}
28263 */ /* end of group GPIO_Peripheral_Access_Layer */
28264
28265/* ----------------------------------------------------------------------------
28266 -- GPMI Peripheral Access Layer
28267 ---------------------------------------------------------------------------- */
28268
28269/*!
28270 * @addtogroup GPMI_Peripheral_Access_Layer GPMI Peripheral Access Layer
28271 * @{
28272 */
28273
28274/** GPMI - Register Layout Typedef */
28275typedef struct
28276{
28277 __IO uint32_t CTRL0; /**< GPMI Control Register 0 Description, offset: 0x0 */
28278 __IO uint32_t CTRL0_SET; /**< GPMI Control Register 0 Description, offset: 0x4 */
28279 __IO uint32_t CTRL0_CLR; /**< GPMI Control Register 0 Description, offset: 0x8 */
28280 __IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset: 0xC */
28281 __IO uint32_t COMPARE; /**< GPMI Compare Register Description, offset: 0x10 */
28282 uint8_t RESERVED_0[12];
28283 __IO uint32_t ECCCTRL; /**< GPMI Integrated ECC Control Register Description, offset: 0x20 */
28284 __IO uint32_t ECCCTRL_SET; /**< GPMI Integrated ECC Control Register Description, offset: 0x24 */
28285 __IO uint32_t ECCCTRL_CLR; /**< GPMI Integrated ECC Control Register Description, offset: 0x28 */
28286 __IO uint32_t ECCCTRL_TOG; /**< GPMI Integrated ECC Control Register Description, offset: 0x2C */
28287 __IO uint32_t ECCCOUNT; /**< GPMI Integrated ECC Transfer Count Register Description, offset: 0x30 */
28288 uint8_t RESERVED_1[12];
28289 __IO uint32_t PAYLOAD; /**< GPMI Payload Address Register Description, offset: 0x40 */
28290 uint8_t RESERVED_2[12];
28291 __IO uint32_t AUXILIARY; /**< GPMI Auxiliary Address Register Description, offset: 0x50 */
28292 uint8_t RESERVED_3[12];
28293 __IO uint32_t CTRL1; /**< GPMI Control Register 1 Description, offset: 0x60 */
28294 __IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset: 0x64 */
28295 __IO uint32_t CTRL1_CLR; /**< GPMI Control Register 1 Description, offset: 0x68 */
28296 __IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset: 0x6C */
28297 __IO uint32_t TIMING0; /**< GPMI Timing Register 0 Description, offset: 0x70 */
28298 uint8_t RESERVED_4[12];
28299 __IO uint32_t TIMING1; /**< GPMI Timing Register 1 Description, offset: 0x80 */
28300 uint8_t RESERVED_5[12];
28301 __IO uint32_t TIMING2; /**< GPMI Timing Register 2 Description, offset: 0x90 */
28302 uint8_t RESERVED_6[12];
28303 __IO uint32_t DATA; /**< GPMI DMA Data Transfer Register Description, offset: 0xA0 */
28304 uint8_t RESERVED_7[12];
28305 __I uint32_t STAT; /**< GPMI Status Register Description, offset: 0xB0 */
28306 uint8_t RESERVED_8[12];
28307 __I uint32_t DEBUGr; /**< GPMI Debug Information Register Description, offset: 0xC0 */
28308 uint8_t RESERVED_9[12];
28309 __I uint32_t VERSION; /**< GPMI Version Register Description, offset: 0xD0 */
28310 uint8_t RESERVED_10[12];
28311 __IO uint32_t DEBUG2; /**< GPMI Debug2 Information Register Description, offset: 0xE0 */
28312 uint8_t RESERVED_11[12];
28313 __I uint32_t DEBUG3; /**< GPMI Debug3 Information Register Description, offset: 0xF0 */
28314 uint8_t RESERVED_12[12];
28315 __IO uint32_t READ_DDR_DLL_CTRL; /**< GPMI Double Rate Read DLL Control Register Description, offset: 0x100 */
28316 uint8_t RESERVED_13[12];
28317 __IO uint32_t WRITE_DDR_DLL_CTRL; /**< GPMI Double Rate Write DLL Control Register Description, offset: 0x110 */
28318 uint8_t RESERVED_14[12];
28319 __I uint32_t READ_DDR_DLL_STS; /**< GPMI Double Rate Read DLL Status Register Description, offset: 0x120 */
28320 uint8_t RESERVED_15[12];
28321 __I uint32_t WRITE_DDR_DLL_STS; /**< GPMI Double Rate Write DLL Status Register Description, offset: 0x130 */
28322} GPMI_Type;
28323
28324/* ----------------------------------------------------------------------------
28325 -- GPMI Register Masks
28326 ---------------------------------------------------------------------------- */
28327
28328/*!
28329 * @addtogroup GPMI_Register_Masks GPMI Register Masks
28330 * @{
28331 */
28332
28333/*! @name CTRL0 - GPMI Control Register 0 Description */
28334/*! @{ */
28335#define GPMI_CTRL0_XFER_COUNT_MASK (0xFFFFU)
28336#define GPMI_CTRL0_XFER_COUNT_SHIFT (0U)
28337#define GPMI_CTRL0_XFER_COUNT(x) \
28338 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_XFER_COUNT_SHIFT)) & GPMI_CTRL0_XFER_COUNT_MASK)
28339#define GPMI_CTRL0_ADDRESS_INCREMENT_MASK (0x10000U)
28340#define GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT (16U)
28341/*! ADDRESS_INCREMENT
28342 * 0b0..Address does not increment.
28343 * 0b1..Increment address.
28344 */
28345#define GPMI_CTRL0_ADDRESS_INCREMENT(x) \
28346 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_ADDRESS_INCREMENT_MASK)
28347#define GPMI_CTRL0_ADDRESS_MASK (0xE0000U)
28348#define GPMI_CTRL0_ADDRESS_SHIFT (17U)
28349#define GPMI_CTRL0_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_SHIFT)) & GPMI_CTRL0_ADDRESS_MASK)
28350#define GPMI_CTRL0_CS_MASK (0x700000U)
28351#define GPMI_CTRL0_CS_SHIFT (20U)
28352#define GPMI_CTRL0_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CS_SHIFT)) & GPMI_CTRL0_CS_MASK)
28353#define GPMI_CTRL0_WORD_LENGTH_MASK (0x800000U)
28354#define GPMI_CTRL0_WORD_LENGTH_SHIFT (23U)
28355/*! WORD_LENGTH
28356 * 0b0..Reserved.
28357 * 0b1..8-bit Data Bus mode.
28358 */
28359#define GPMI_CTRL0_WORD_LENGTH(x) \
28360 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_WORD_LENGTH_MASK)
28361#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3000000U)
28362#define GPMI_CTRL0_COMMAND_MODE_SHIFT (24U)
28363/*! COMMAND_MODE
28364 * 0b00..Write mode.
28365 * 0b01..Read Mode.
28366 * 0b10..Read and Compare Mode (setting sense flop).
28367 * 0b11..Wait for Ready.
28368 */
28369#define GPMI_CTRL0_COMMAND_MODE(x) \
28370 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_COMMAND_MODE_MASK)
28371#define GPMI_CTRL0_UDMA_MASK (0x4000000U)
28372#define GPMI_CTRL0_UDMA_SHIFT (26U)
28373/*! UDMA
28374 * 0b0..Use ATA-PIO mode on the external bus.
28375 * 0b1..Use ATA-Ultra DMA mode on the external bus.
28376 */
28377#define GPMI_CTRL0_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_UDMA_SHIFT)) & GPMI_CTRL0_UDMA_MASK)
28378#define GPMI_CTRL0_LOCK_CS_MASK (0x8000000U)
28379#define GPMI_CTRL0_LOCK_CS_SHIFT (27U)
28380#define GPMI_CTRL0_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_LOCK_CS_SHIFT)) & GPMI_CTRL0_LOCK_CS_MASK)
28381#define GPMI_CTRL0_DEV_IRQ_EN_MASK (0x10000000U)
28382#define GPMI_CTRL0_DEV_IRQ_EN_SHIFT (28U)
28383#define GPMI_CTRL0_DEV_IRQ_EN(x) \
28384 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_DEV_IRQ_EN_MASK)
28385#define GPMI_CTRL0_RUN_MASK (0x20000000U)
28386#define GPMI_CTRL0_RUN_SHIFT (29U)
28387#define GPMI_CTRL0_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_RUN_SHIFT)) & GPMI_CTRL0_RUN_MASK)
28388#define GPMI_CTRL0_CLKGATE_MASK (0x40000000U)
28389#define GPMI_CTRL0_CLKGATE_SHIFT (30U)
28390#define GPMI_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLKGATE_SHIFT)) & GPMI_CTRL0_CLKGATE_MASK)
28391#define GPMI_CTRL0_SFTRST_MASK (0x80000000U)
28392#define GPMI_CTRL0_SFTRST_SHIFT (31U)
28393#define GPMI_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SFTRST_SHIFT)) & GPMI_CTRL0_SFTRST_MASK)
28394/*! @} */
28395
28396/*! @name CTRL0_SET - GPMI Control Register 0 Description */
28397/*! @{ */
28398#define GPMI_CTRL0_SET_XFER_COUNT_MASK (0xFFFFU)
28399#define GPMI_CTRL0_SET_XFER_COUNT_SHIFT (0U)
28400#define GPMI_CTRL0_SET_XFER_COUNT(x) \
28401 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_XFER_COUNT_SHIFT)) & GPMI_CTRL0_SET_XFER_COUNT_MASK)
28402#define GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK (0x10000U)
28403#define GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT (16U)
28404/*! ADDRESS_INCREMENT
28405 * 0b0..Address does not increment.
28406 * 0b1..Increment address.
28407 */
28408#define GPMI_CTRL0_SET_ADDRESS_INCREMENT(x) \
28409 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_INCREMENT_MASK)
28410#define GPMI_CTRL0_SET_ADDRESS_MASK (0xE0000U)
28411#define GPMI_CTRL0_SET_ADDRESS_SHIFT (17U)
28412#define GPMI_CTRL0_SET_ADDRESS(x) \
28413 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_ADDRESS_SHIFT)) & GPMI_CTRL0_SET_ADDRESS_MASK)
28414#define GPMI_CTRL0_SET_CS_MASK (0x700000U)
28415#define GPMI_CTRL0_SET_CS_SHIFT (20U)
28416#define GPMI_CTRL0_SET_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CS_SHIFT)) & GPMI_CTRL0_SET_CS_MASK)
28417#define GPMI_CTRL0_SET_WORD_LENGTH_MASK (0x800000U)
28418#define GPMI_CTRL0_SET_WORD_LENGTH_SHIFT (23U)
28419/*! WORD_LENGTH
28420 * 0b0..Reserved.
28421 * 0b1..8-bit Data Bus mode.
28422 */
28423#define GPMI_CTRL0_SET_WORD_LENGTH(x) \
28424 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_SET_WORD_LENGTH_MASK)
28425#define GPMI_CTRL0_SET_COMMAND_MODE_MASK (0x3000000U)
28426#define GPMI_CTRL0_SET_COMMAND_MODE_SHIFT (24U)
28427/*! COMMAND_MODE
28428 * 0b00..Write mode.
28429 * 0b01..Read Mode.
28430 * 0b10..Read and Compare Mode (setting sense flop).
28431 * 0b11..Wait for Ready.
28432 */
28433#define GPMI_CTRL0_SET_COMMAND_MODE(x) \
28434 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_SET_COMMAND_MODE_MASK)
28435#define GPMI_CTRL0_SET_UDMA_MASK (0x4000000U)
28436#define GPMI_CTRL0_SET_UDMA_SHIFT (26U)
28437/*! UDMA
28438 * 0b0..Use ATA-PIO mode on the external bus.
28439 * 0b1..Use ATA-Ultra DMA mode on the external bus.
28440 */
28441#define GPMI_CTRL0_SET_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_UDMA_SHIFT)) & GPMI_CTRL0_SET_UDMA_MASK)
28442#define GPMI_CTRL0_SET_LOCK_CS_MASK (0x8000000U)
28443#define GPMI_CTRL0_SET_LOCK_CS_SHIFT (27U)
28444#define GPMI_CTRL0_SET_LOCK_CS(x) \
28445 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_LOCK_CS_SHIFT)) & GPMI_CTRL0_SET_LOCK_CS_MASK)
28446#define GPMI_CTRL0_SET_DEV_IRQ_EN_MASK (0x10000000U)
28447#define GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT (28U)
28448#define GPMI_CTRL0_SET_DEV_IRQ_EN(x) \
28449 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_SET_DEV_IRQ_EN_MASK)
28450#define GPMI_CTRL0_SET_RUN_MASK (0x20000000U)
28451#define GPMI_CTRL0_SET_RUN_SHIFT (29U)
28452#define GPMI_CTRL0_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_RUN_SHIFT)) & GPMI_CTRL0_SET_RUN_MASK)
28453#define GPMI_CTRL0_SET_CLKGATE_MASK (0x40000000U)
28454#define GPMI_CTRL0_SET_CLKGATE_SHIFT (30U)
28455#define GPMI_CTRL0_SET_CLKGATE(x) \
28456 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_CLKGATE_SHIFT)) & GPMI_CTRL0_SET_CLKGATE_MASK)
28457#define GPMI_CTRL0_SET_SFTRST_MASK (0x80000000U)
28458#define GPMI_CTRL0_SET_SFTRST_SHIFT (31U)
28459#define GPMI_CTRL0_SET_SFTRST(x) \
28460 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SET_SFTRST_SHIFT)) & GPMI_CTRL0_SET_SFTRST_MASK)
28461/*! @} */
28462
28463/*! @name CTRL0_CLR - GPMI Control Register 0 Description */
28464/*! @{ */
28465#define GPMI_CTRL0_CLR_XFER_COUNT_MASK (0xFFFFU)
28466#define GPMI_CTRL0_CLR_XFER_COUNT_SHIFT (0U)
28467#define GPMI_CTRL0_CLR_XFER_COUNT(x) \
28468 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_XFER_COUNT_SHIFT)) & GPMI_CTRL0_CLR_XFER_COUNT_MASK)
28469#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK (0x10000U)
28470#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT (16U)
28471/*! ADDRESS_INCREMENT
28472 * 0b0..Address does not increment.
28473 * 0b1..Increment address.
28474 */
28475#define GPMI_CTRL0_CLR_ADDRESS_INCREMENT(x) \
28476 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_INCREMENT_MASK)
28477#define GPMI_CTRL0_CLR_ADDRESS_MASK (0xE0000U)
28478#define GPMI_CTRL0_CLR_ADDRESS_SHIFT (17U)
28479#define GPMI_CTRL0_CLR_ADDRESS(x) \
28480 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_ADDRESS_SHIFT)) & GPMI_CTRL0_CLR_ADDRESS_MASK)
28481#define GPMI_CTRL0_CLR_CS_MASK (0x700000U)
28482#define GPMI_CTRL0_CLR_CS_SHIFT (20U)
28483#define GPMI_CTRL0_CLR_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CS_SHIFT)) & GPMI_CTRL0_CLR_CS_MASK)
28484#define GPMI_CTRL0_CLR_WORD_LENGTH_MASK (0x800000U)
28485#define GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT (23U)
28486/*! WORD_LENGTH
28487 * 0b0..Reserved.
28488 * 0b1..8-bit Data Bus mode.
28489 */
28490#define GPMI_CTRL0_CLR_WORD_LENGTH(x) \
28491 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_CLR_WORD_LENGTH_MASK)
28492#define GPMI_CTRL0_CLR_COMMAND_MODE_MASK (0x3000000U)
28493#define GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT (24U)
28494/*! COMMAND_MODE
28495 * 0b00..Write mode.
28496 * 0b01..Read Mode.
28497 * 0b10..Read and Compare Mode (setting sense flop).
28498 * 0b11..Wait for Ready.
28499 */
28500#define GPMI_CTRL0_CLR_COMMAND_MODE(x) \
28501 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_CLR_COMMAND_MODE_MASK)
28502#define GPMI_CTRL0_CLR_UDMA_MASK (0x4000000U)
28503#define GPMI_CTRL0_CLR_UDMA_SHIFT (26U)
28504/*! UDMA
28505 * 0b0..Use ATA-PIO mode on the external bus.
28506 * 0b1..Use ATA-Ultra DMA mode on the external bus.
28507 */
28508#define GPMI_CTRL0_CLR_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_UDMA_SHIFT)) & GPMI_CTRL0_CLR_UDMA_MASK)
28509#define GPMI_CTRL0_CLR_LOCK_CS_MASK (0x8000000U)
28510#define GPMI_CTRL0_CLR_LOCK_CS_SHIFT (27U)
28511#define GPMI_CTRL0_CLR_LOCK_CS(x) \
28512 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_LOCK_CS_SHIFT)) & GPMI_CTRL0_CLR_LOCK_CS_MASK)
28513#define GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK (0x10000000U)
28514#define GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT (28U)
28515#define GPMI_CTRL0_CLR_DEV_IRQ_EN(x) \
28516 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_CLR_DEV_IRQ_EN_MASK)
28517#define GPMI_CTRL0_CLR_RUN_MASK (0x20000000U)
28518#define GPMI_CTRL0_CLR_RUN_SHIFT (29U)
28519#define GPMI_CTRL0_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_RUN_SHIFT)) & GPMI_CTRL0_CLR_RUN_MASK)
28520#define GPMI_CTRL0_CLR_CLKGATE_MASK (0x40000000U)
28521#define GPMI_CTRL0_CLR_CLKGATE_SHIFT (30U)
28522#define GPMI_CTRL0_CLR_CLKGATE(x) \
28523 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_CLKGATE_SHIFT)) & GPMI_CTRL0_CLR_CLKGATE_MASK)
28524#define GPMI_CTRL0_CLR_SFTRST_MASK (0x80000000U)
28525#define GPMI_CTRL0_CLR_SFTRST_SHIFT (31U)
28526#define GPMI_CTRL0_CLR_SFTRST(x) \
28527 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLR_SFTRST_SHIFT)) & GPMI_CTRL0_CLR_SFTRST_MASK)
28528/*! @} */
28529
28530/*! @name CTRL0_TOG - GPMI Control Register 0 Description */
28531/*! @{ */
28532#define GPMI_CTRL0_TOG_XFER_COUNT_MASK (0xFFFFU)
28533#define GPMI_CTRL0_TOG_XFER_COUNT_SHIFT (0U)
28534#define GPMI_CTRL0_TOG_XFER_COUNT(x) \
28535 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_XFER_COUNT_SHIFT)) & GPMI_CTRL0_TOG_XFER_COUNT_MASK)
28536#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK (0x10000U)
28537#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT (16U)
28538/*! ADDRESS_INCREMENT
28539 * 0b0..Address does not increment.
28540 * 0b1..Increment address.
28541 */
28542#define GPMI_CTRL0_TOG_ADDRESS_INCREMENT(x) \
28543 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_INCREMENT_MASK)
28544#define GPMI_CTRL0_TOG_ADDRESS_MASK (0xE0000U)
28545#define GPMI_CTRL0_TOG_ADDRESS_SHIFT (17U)
28546#define GPMI_CTRL0_TOG_ADDRESS(x) \
28547 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_ADDRESS_SHIFT)) & GPMI_CTRL0_TOG_ADDRESS_MASK)
28548#define GPMI_CTRL0_TOG_CS_MASK (0x700000U)
28549#define GPMI_CTRL0_TOG_CS_SHIFT (20U)
28550#define GPMI_CTRL0_TOG_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CS_SHIFT)) & GPMI_CTRL0_TOG_CS_MASK)
28551#define GPMI_CTRL0_TOG_WORD_LENGTH_MASK (0x800000U)
28552#define GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT (23U)
28553/*! WORD_LENGTH
28554 * 0b0..Reserved.
28555 * 0b1..8-bit Data Bus mode.
28556 */
28557#define GPMI_CTRL0_TOG_WORD_LENGTH(x) \
28558 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_TOG_WORD_LENGTH_MASK)
28559#define GPMI_CTRL0_TOG_COMMAND_MODE_MASK (0x3000000U)
28560#define GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT (24U)
28561/*! COMMAND_MODE
28562 * 0b00..Write mode.
28563 * 0b01..Read Mode.
28564 * 0b10..Read and Compare Mode (setting sense flop).
28565 * 0b11..Wait for Ready.
28566 */
28567#define GPMI_CTRL0_TOG_COMMAND_MODE(x) \
28568 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_TOG_COMMAND_MODE_MASK)
28569#define GPMI_CTRL0_TOG_UDMA_MASK (0x4000000U)
28570#define GPMI_CTRL0_TOG_UDMA_SHIFT (26U)
28571/*! UDMA
28572 * 0b0..Use ATA-PIO mode on the external bus.
28573 * 0b1..Use ATA-Ultra DMA mode on the external bus.
28574 */
28575#define GPMI_CTRL0_TOG_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_UDMA_SHIFT)) & GPMI_CTRL0_TOG_UDMA_MASK)
28576#define GPMI_CTRL0_TOG_LOCK_CS_MASK (0x8000000U)
28577#define GPMI_CTRL0_TOG_LOCK_CS_SHIFT (27U)
28578#define GPMI_CTRL0_TOG_LOCK_CS(x) \
28579 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_LOCK_CS_SHIFT)) & GPMI_CTRL0_TOG_LOCK_CS_MASK)
28580#define GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK (0x10000000U)
28581#define GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT (28U)
28582#define GPMI_CTRL0_TOG_DEV_IRQ_EN(x) \
28583 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_DEV_IRQ_EN_SHIFT)) & GPMI_CTRL0_TOG_DEV_IRQ_EN_MASK)
28584#define GPMI_CTRL0_TOG_RUN_MASK (0x20000000U)
28585#define GPMI_CTRL0_TOG_RUN_SHIFT (29U)
28586#define GPMI_CTRL0_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_RUN_SHIFT)) & GPMI_CTRL0_TOG_RUN_MASK)
28587#define GPMI_CTRL0_TOG_CLKGATE_MASK (0x40000000U)
28588#define GPMI_CTRL0_TOG_CLKGATE_SHIFT (30U)
28589#define GPMI_CTRL0_TOG_CLKGATE(x) \
28590 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_CLKGATE_SHIFT)) & GPMI_CTRL0_TOG_CLKGATE_MASK)
28591#define GPMI_CTRL0_TOG_SFTRST_MASK (0x80000000U)
28592#define GPMI_CTRL0_TOG_SFTRST_SHIFT (31U)
28593#define GPMI_CTRL0_TOG_SFTRST(x) \
28594 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_TOG_SFTRST_SHIFT)) & GPMI_CTRL0_TOG_SFTRST_MASK)
28595/*! @} */
28596
28597/*! @name COMPARE - GPMI Compare Register Description */
28598/*! @{ */
28599#define GPMI_COMPARE_REFERENCE_MASK (0xFFFFU)
28600#define GPMI_COMPARE_REFERENCE_SHIFT (0U)
28601#define GPMI_COMPARE_REFERENCE(x) \
28602 (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_REFERENCE_SHIFT)) & GPMI_COMPARE_REFERENCE_MASK)
28603#define GPMI_COMPARE_MASK_MASK (0xFFFF0000U)
28604#define GPMI_COMPARE_MASK_SHIFT (16U)
28605#define GPMI_COMPARE_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_MASK_SHIFT)) & GPMI_COMPARE_MASK_MASK)
28606/*! @} */
28607
28608/*! @name ECCCTRL - GPMI Integrated ECC Control Register Description */
28609/*! @{ */
28610#define GPMI_ECCCTRL_BUFFER_MASK_MASK (0x1FFU)
28611#define GPMI_ECCCTRL_BUFFER_MASK_SHIFT (0U)
28612#define GPMI_ECCCTRL_BUFFER_MASK(x) \
28613 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_BUFFER_MASK_MASK)
28614#define GPMI_ECCCTRL_RANDOMIZER_TYPE_MASK (0x600U)
28615#define GPMI_ECCCTRL_RANDOMIZER_TYPE_SHIFT (9U)
28616/*! RANDOMIZER_TYPE
28617 * 0b00..Type 0
28618 * 0b01..Type 1
28619 */
28620#define GPMI_ECCCTRL_RANDOMIZER_TYPE(x) \
28621 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_RANDOMIZER_TYPE_MASK)
28622#define GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK (0x800U)
28623#define GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT (11U)
28624/*! RANDOMIZER_ENABLE
28625 * 0b0..disable
28626 * 0b1..enable
28627 */
28628#define GPMI_ECCCTRL_RANDOMIZER_ENABLE(x) \
28629 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK)
28630#define GPMI_ECCCTRL_ENABLE_ECC_MASK (0x1000U)
28631#define GPMI_ECCCTRL_ENABLE_ECC_SHIFT (12U)
28632#define GPMI_ECCCTRL_ENABLE_ECC(x) \
28633 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_ENABLE_ECC_MASK)
28634#define GPMI_ECCCTRL_ECC_CMD_MASK (0x6000U)
28635#define GPMI_ECCCTRL_ECC_CMD_SHIFT (13U)
28636#define GPMI_ECCCTRL_ECC_CMD(x) \
28637 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_ECC_CMD_MASK)
28638#define GPMI_ECCCTRL_RSVD2_MASK (0x8000U)
28639#define GPMI_ECCCTRL_RSVD2_SHIFT (15U)
28640#define GPMI_ECCCTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RSVD2_SHIFT)) & GPMI_ECCCTRL_RSVD2_MASK)
28641#define GPMI_ECCCTRL_HANDLE_MASK (0xFFFF0000U)
28642#define GPMI_ECCCTRL_HANDLE_SHIFT (16U)
28643#define GPMI_ECCCTRL_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_HANDLE_SHIFT)) & GPMI_ECCCTRL_HANDLE_MASK)
28644/*! @} */
28645
28646/*! @name ECCCTRL_SET - GPMI Integrated ECC Control Register Description */
28647/*! @{ */
28648#define GPMI_ECCCTRL_SET_BUFFER_MASK_MASK (0x1FFU)
28649#define GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT (0U)
28650#define GPMI_ECCCTRL_SET_BUFFER_MASK(x) \
28651 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_SET_BUFFER_MASK_MASK)
28652#define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_MASK (0x600U)
28653#define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_SHIFT (9U)
28654/*! RANDOMIZER_TYPE
28655 * 0b00..Type 0
28656 * 0b01..Type 1
28657 */
28658#define GPMI_ECCCTRL_SET_RANDOMIZER_TYPE(x) \
28659 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_SET_RANDOMIZER_TYPE_MASK)
28660#define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_MASK (0x800U)
28661#define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_SHIFT (11U)
28662/*! RANDOMIZER_ENABLE
28663 * 0b0..disable
28664 * 0b1..enable
28665 */
28666#define GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE(x) \
28667 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_SHIFT)) & \
28668 GPMI_ECCCTRL_SET_RANDOMIZER_ENABLE_MASK)
28669#define GPMI_ECCCTRL_SET_ENABLE_ECC_MASK (0x1000U)
28670#define GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT (12U)
28671#define GPMI_ECCCTRL_SET_ENABLE_ECC(x) \
28672 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_SET_ENABLE_ECC_MASK)
28673#define GPMI_ECCCTRL_SET_ECC_CMD_MASK (0x6000U)
28674#define GPMI_ECCCTRL_SET_ECC_CMD_SHIFT (13U)
28675#define GPMI_ECCCTRL_SET_ECC_CMD(x) \
28676 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_SET_ECC_CMD_MASK)
28677#define GPMI_ECCCTRL_SET_RSVD2_MASK (0x8000U)
28678#define GPMI_ECCCTRL_SET_RSVD2_SHIFT (15U)
28679#define GPMI_ECCCTRL_SET_RSVD2(x) \
28680 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_RSVD2_SHIFT)) & GPMI_ECCCTRL_SET_RSVD2_MASK)
28681#define GPMI_ECCCTRL_SET_HANDLE_MASK (0xFFFF0000U)
28682#define GPMI_ECCCTRL_SET_HANDLE_SHIFT (16U)
28683#define GPMI_ECCCTRL_SET_HANDLE(x) \
28684 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_SET_HANDLE_SHIFT)) & GPMI_ECCCTRL_SET_HANDLE_MASK)
28685/*! @} */
28686
28687/*! @name ECCCTRL_CLR - GPMI Integrated ECC Control Register Description */
28688/*! @{ */
28689#define GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK (0x1FFU)
28690#define GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT (0U)
28691#define GPMI_ECCCTRL_CLR_BUFFER_MASK(x) \
28692 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_CLR_BUFFER_MASK_MASK)
28693#define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_MASK (0x600U)
28694#define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_SHIFT (9U)
28695/*! RANDOMIZER_TYPE
28696 * 0b00..Type 0
28697 * 0b01..Type 1
28698 */
28699#define GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE(x) \
28700 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_CLR_RANDOMIZER_TYPE_MASK)
28701#define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_MASK (0x800U)
28702#define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_SHIFT (11U)
28703/*! RANDOMIZER_ENABLE
28704 * 0b0..disable
28705 * 0b1..enable
28706 */
28707#define GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE(x) \
28708 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_SHIFT)) & \
28709 GPMI_ECCCTRL_CLR_RANDOMIZER_ENABLE_MASK)
28710#define GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK (0x1000U)
28711#define GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT (12U)
28712#define GPMI_ECCCTRL_CLR_ENABLE_ECC(x) \
28713 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_CLR_ENABLE_ECC_MASK)
28714#define GPMI_ECCCTRL_CLR_ECC_CMD_MASK (0x6000U)
28715#define GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT (13U)
28716#define GPMI_ECCCTRL_CLR_ECC_CMD(x) \
28717 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_CLR_ECC_CMD_MASK)
28718#define GPMI_ECCCTRL_CLR_RSVD2_MASK (0x8000U)
28719#define GPMI_ECCCTRL_CLR_RSVD2_SHIFT (15U)
28720#define GPMI_ECCCTRL_CLR_RSVD2(x) \
28721 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_RSVD2_SHIFT)) & GPMI_ECCCTRL_CLR_RSVD2_MASK)
28722#define GPMI_ECCCTRL_CLR_HANDLE_MASK (0xFFFF0000U)
28723#define GPMI_ECCCTRL_CLR_HANDLE_SHIFT (16U)
28724#define GPMI_ECCCTRL_CLR_HANDLE(x) \
28725 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_CLR_HANDLE_SHIFT)) & GPMI_ECCCTRL_CLR_HANDLE_MASK)
28726/*! @} */
28727
28728/*! @name ECCCTRL_TOG - GPMI Integrated ECC Control Register Description */
28729/*! @{ */
28730#define GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK (0x1FFU)
28731#define GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT (0U)
28732#define GPMI_ECCCTRL_TOG_BUFFER_MASK(x) \
28733 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_TOG_BUFFER_MASK_MASK)
28734#define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_MASK (0x600U)
28735#define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_SHIFT (9U)
28736/*! RANDOMIZER_TYPE
28737 * 0b00..Type 0
28738 * 0b01..Type 1
28739 */
28740#define GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE(x) \
28741 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_TOG_RANDOMIZER_TYPE_MASK)
28742#define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_MASK (0x800U)
28743#define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_SHIFT (11U)
28744/*! RANDOMIZER_ENABLE
28745 * 0b0..disable
28746 * 0b1..enable
28747 */
28748#define GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE(x) \
28749 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_SHIFT)) & \
28750 GPMI_ECCCTRL_TOG_RANDOMIZER_ENABLE_MASK)
28751#define GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK (0x1000U)
28752#define GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT (12U)
28753#define GPMI_ECCCTRL_TOG_ENABLE_ECC(x) \
28754 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_TOG_ENABLE_ECC_MASK)
28755#define GPMI_ECCCTRL_TOG_ECC_CMD_MASK (0x6000U)
28756#define GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT (13U)
28757#define GPMI_ECCCTRL_TOG_ECC_CMD(x) \
28758 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_TOG_ECC_CMD_MASK)
28759#define GPMI_ECCCTRL_TOG_RSVD2_MASK (0x8000U)
28760#define GPMI_ECCCTRL_TOG_RSVD2_SHIFT (15U)
28761#define GPMI_ECCCTRL_TOG_RSVD2(x) \
28762 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_RSVD2_SHIFT)) & GPMI_ECCCTRL_TOG_RSVD2_MASK)
28763#define GPMI_ECCCTRL_TOG_HANDLE_MASK (0xFFFF0000U)
28764#define GPMI_ECCCTRL_TOG_HANDLE_SHIFT (16U)
28765#define GPMI_ECCCTRL_TOG_HANDLE(x) \
28766 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_TOG_HANDLE_SHIFT)) & GPMI_ECCCTRL_TOG_HANDLE_MASK)
28767/*! @} */
28768
28769/*! @name ECCCOUNT - GPMI Integrated ECC Transfer Count Register Description */
28770/*! @{ */
28771#define GPMI_ECCCOUNT_COUNT_MASK (0xFFFFU)
28772#define GPMI_ECCCOUNT_COUNT_SHIFT (0U)
28773#define GPMI_ECCCOUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_COUNT_SHIFT)) & GPMI_ECCCOUNT_COUNT_MASK)
28774#define GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK (0xFF0000U)
28775#define GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT (16U)
28776#define GPMI_ECCCOUNT_RANDOMIZER_PAGE(x) \
28777 (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT)) & GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK)
28778/*! @} */
28779
28780/*! @name PAYLOAD - GPMI Payload Address Register Description */
28781/*! @{ */
28782#define GPMI_PAYLOAD_RSVD0_MASK (0x3U)
28783#define GPMI_PAYLOAD_RSVD0_SHIFT (0U)
28784#define GPMI_PAYLOAD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_RSVD0_SHIFT)) & GPMI_PAYLOAD_RSVD0_MASK)
28785#define GPMI_PAYLOAD_ADDRESS_MASK (0xFFFFFFFCU)
28786#define GPMI_PAYLOAD_ADDRESS_SHIFT (2U)
28787#define GPMI_PAYLOAD_ADDRESS(x) \
28788 (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_ADDRESS_SHIFT)) & GPMI_PAYLOAD_ADDRESS_MASK)
28789/*! @} */
28790
28791/*! @name AUXILIARY - GPMI Auxiliary Address Register Description */
28792/*! @{ */
28793#define GPMI_AUXILIARY_RSVD0_MASK (0x3U)
28794#define GPMI_AUXILIARY_RSVD0_SHIFT (0U)
28795#define GPMI_AUXILIARY_RSVD0(x) \
28796 (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_RSVD0_SHIFT)) & GPMI_AUXILIARY_RSVD0_MASK)
28797#define GPMI_AUXILIARY_ADDRESS_MASK (0xFFFFFFFCU)
28798#define GPMI_AUXILIARY_ADDRESS_SHIFT (2U)
28799#define GPMI_AUXILIARY_ADDRESS(x) \
28800 (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_ADDRESS_SHIFT)) & GPMI_AUXILIARY_ADDRESS_MASK)
28801/*! @} */
28802
28803/*! @name CTRL1 - GPMI Control Register 1 Description */
28804/*! @{ */
28805#define GPMI_CTRL1_GPMI_MODE_MASK (0x1U)
28806#define GPMI_CTRL1_GPMI_MODE_SHIFT (0U)
28807/*! GPMI_MODE
28808 * 0b0..NAND mode.
28809 * 0b1..ATA mode.
28810 */
28811#define GPMI_CTRL1_GPMI_MODE(x) \
28812 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_MODE_SHIFT)) & GPMI_CTRL1_GPMI_MODE_MASK)
28813#define GPMI_CTRL1_CAMERA_MODE_MASK (0x2U)
28814#define GPMI_CTRL1_CAMERA_MODE_SHIFT (1U)
28815#define GPMI_CTRL1_CAMERA_MODE(x) \
28816 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CAMERA_MODE_MASK)
28817#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK (0x4U)
28818#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT (2U)
28819/*! ATA_IRQRDY_POLARITY
28820 * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
28821 * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
28822 */
28823#define GPMI_CTRL1_ATA_IRQRDY_POLARITY(x) \
28824 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK)
28825#define GPMI_CTRL1_DEV_RESET_MASK (0x8U)
28826#define GPMI_CTRL1_DEV_RESET_SHIFT (3U)
28827/*! DEV_RESET
28828 * 0b0..NANDF_WP_B pin is held low (asserted).
28829 * 0b1..NANDF_WP_B pin is held high (de-asserted).
28830 */
28831#define GPMI_CTRL1_DEV_RESET(x) \
28832 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_RESET_SHIFT)) & GPMI_CTRL1_DEV_RESET_MASK)
28833#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U)
28834#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U)
28835#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(x) \
28836 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & \
28837 GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
28838#define GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK (0x80U)
28839#define GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT (7U)
28840#define GPMI_CTRL1_ABORT_WAIT_REQUEST(x) \
28841 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK)
28842#define GPMI_CTRL1_BURST_EN_MASK (0x100U)
28843#define GPMI_CTRL1_BURST_EN_SHIFT (8U)
28844#define GPMI_CTRL1_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BURST_EN_SHIFT)) & GPMI_CTRL1_BURST_EN_MASK)
28845#define GPMI_CTRL1_TIMEOUT_IRQ_MASK (0x200U)
28846#define GPMI_CTRL1_TIMEOUT_IRQ_SHIFT (9U)
28847#define GPMI_CTRL1_TIMEOUT_IRQ(x) \
28848 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_MASK)
28849#define GPMI_CTRL1_DEV_IRQ_MASK (0x400U)
28850#define GPMI_CTRL1_DEV_IRQ_SHIFT (10U)
28851#define GPMI_CTRL1_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_IRQ_SHIFT)) & GPMI_CTRL1_DEV_IRQ_MASK)
28852#define GPMI_CTRL1_DMA2ECC_MODE_MASK (0x800U)
28853#define GPMI_CTRL1_DMA2ECC_MODE_SHIFT (11U)
28854#define GPMI_CTRL1_DMA2ECC_MODE(x) \
28855 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_DMA2ECC_MODE_MASK)
28856#define GPMI_CTRL1_RDN_DELAY_MASK (0xF000U)
28857#define GPMI_CTRL1_RDN_DELAY_SHIFT (12U)
28858#define GPMI_CTRL1_RDN_DELAY(x) \
28859 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_RDN_DELAY_SHIFT)) & GPMI_CTRL1_RDN_DELAY_MASK)
28860#define GPMI_CTRL1_HALF_PERIOD_MASK (0x10000U)
28861#define GPMI_CTRL1_HALF_PERIOD_SHIFT (16U)
28862#define GPMI_CTRL1_HALF_PERIOD(x) \
28863 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_HALF_PERIOD_MASK)
28864#define GPMI_CTRL1_DLL_ENABLE_MASK (0x20000U)
28865#define GPMI_CTRL1_DLL_ENABLE_SHIFT (17U)
28866#define GPMI_CTRL1_DLL_ENABLE(x) \
28867 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_DLL_ENABLE_MASK)
28868#define GPMI_CTRL1_BCH_MODE_MASK (0x40000U)
28869#define GPMI_CTRL1_BCH_MODE_SHIFT (18U)
28870#define GPMI_CTRL1_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BCH_MODE_SHIFT)) & GPMI_CTRL1_BCH_MODE_MASK)
28871#define GPMI_CTRL1_GANGED_RDYBUSY_MASK (0x80000U)
28872#define GPMI_CTRL1_GANGED_RDYBUSY_SHIFT (19U)
28873#define GPMI_CTRL1_GANGED_RDYBUSY(x) \
28874 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_GANGED_RDYBUSY_MASK)
28875#define GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK (0x100000U)
28876#define GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT (20U)
28877#define GPMI_CTRL1_TIMEOUT_IRQ_EN(x) \
28878 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK)
28879#define GPMI_CTRL1_TEST_TRIGGER_MASK (0x200000U)
28880#define GPMI_CTRL1_TEST_TRIGGER_SHIFT (21U)
28881/*! TEST_TRIGGER
28882 * 0b0..Disable
28883 * 0b1..Enable
28884 */
28885#define GPMI_CTRL1_TEST_TRIGGER(x) \
28886 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TEST_TRIGGER_MASK)
28887#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0xC00000U)
28888#define GPMI_CTRL1_WRN_DLY_SEL_SHIFT (22U)
28889#define GPMI_CTRL1_WRN_DLY_SEL(x) \
28890 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_WRN_DLY_SEL_MASK)
28891#define GPMI_CTRL1_DECOUPLE_CS_MASK (0x1000000U)
28892#define GPMI_CTRL1_DECOUPLE_CS_SHIFT (24U)
28893#define GPMI_CTRL1_DECOUPLE_CS(x) \
28894 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_DECOUPLE_CS_MASK)
28895#define GPMI_CTRL1_SSYNCMODE_MASK (0x2000000U)
28896#define GPMI_CTRL1_SSYNCMODE_SHIFT (25U)
28897#define GPMI_CTRL1_SSYNCMODE(x) \
28898 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SSYNCMODE_MASK)
28899#define GPMI_CTRL1_UPDATE_CS_MASK (0x4000000U)
28900#define GPMI_CTRL1_UPDATE_CS_SHIFT (26U)
28901#define GPMI_CTRL1_UPDATE_CS(x) \
28902 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_UPDATE_CS_SHIFT)) & GPMI_CTRL1_UPDATE_CS_MASK)
28903#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK (0x8000000U)
28904#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT (27U)
28905/*! GPMI_CLK_DIV2_EN
28906 * 0b0..internal factor-2 clock divider is disabled
28907 * 0b1..internal factor-2 clock divider is enabled.
28908 */
28909#define GPMI_CTRL1_GPMI_CLK_DIV2_EN(x) \
28910 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK)
28911#define GPMI_CTRL1_TOGGLE_MODE_MASK (0x10000000U)
28912#define GPMI_CTRL1_TOGGLE_MODE_SHIFT (28U)
28913#define GPMI_CTRL1_TOGGLE_MODE(x) \
28914 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOGGLE_MODE_MASK)
28915#define GPMI_CTRL1_WRITE_CLK_STOP_MASK (0x20000000U)
28916#define GPMI_CTRL1_WRITE_CLK_STOP_SHIFT (29U)
28917#define GPMI_CTRL1_WRITE_CLK_STOP(x) \
28918 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_WRITE_CLK_STOP_MASK)
28919#define GPMI_CTRL1_SSYNC_CLK_STOP_MASK (0x40000000U)
28920#define GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT (30U)
28921#define GPMI_CTRL1_SSYNC_CLK_STOP(x) \
28922 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SSYNC_CLK_STOP_MASK)
28923#define GPMI_CTRL1_DEV_CLK_STOP_MASK (0x80000000U)
28924#define GPMI_CTRL1_DEV_CLK_STOP_SHIFT (31U)
28925#define GPMI_CTRL1_DEV_CLK_STOP(x) \
28926 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_DEV_CLK_STOP_MASK)
28927/*! @} */
28928
28929/*! @name CTRL1_SET - GPMI Control Register 1 Description */
28930/*! @{ */
28931#define GPMI_CTRL1_SET_GPMI_MODE_MASK (0x1U)
28932#define GPMI_CTRL1_SET_GPMI_MODE_SHIFT (0U)
28933/*! GPMI_MODE
28934 * 0b0..NAND mode.
28935 * 0b1..ATA mode.
28936 */
28937#define GPMI_CTRL1_SET_GPMI_MODE(x) \
28938 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_MODE_SHIFT)) & GPMI_CTRL1_SET_GPMI_MODE_MASK)
28939#define GPMI_CTRL1_SET_CAMERA_MODE_MASK (0x2U)
28940#define GPMI_CTRL1_SET_CAMERA_MODE_SHIFT (1U)
28941#define GPMI_CTRL1_SET_CAMERA_MODE(x) \
28942 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_SET_CAMERA_MODE_MASK)
28943#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK (0x4U)
28944#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT (2U)
28945/*! ATA_IRQRDY_POLARITY
28946 * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
28947 * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
28948 */
28949#define GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY(x) \
28950 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_SHIFT)) & \
28951 GPMI_CTRL1_SET_ATA_IRQRDY_POLARITY_MASK)
28952#define GPMI_CTRL1_SET_DEV_RESET_MASK (0x8U)
28953#define GPMI_CTRL1_SET_DEV_RESET_SHIFT (3U)
28954/*! DEV_RESET
28955 * 0b0..NANDF_WP_B pin is held low (asserted).
28956 * 0b1..NANDF_WP_B pin is held high (de-asserted).
28957 */
28958#define GPMI_CTRL1_SET_DEV_RESET(x) \
28959 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_RESET_SHIFT)) & GPMI_CTRL1_SET_DEV_RESET_MASK)
28960#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U)
28961#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U)
28962#define GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL(x) \
28963 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & \
28964 GPMI_CTRL1_SET_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
28965#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK (0x80U)
28966#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT (7U)
28967#define GPMI_CTRL1_SET_ABORT_WAIT_REQUEST(x) \
28968 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_SET_ABORT_WAIT_REQUEST_MASK)
28969#define GPMI_CTRL1_SET_BURST_EN_MASK (0x100U)
28970#define GPMI_CTRL1_SET_BURST_EN_SHIFT (8U)
28971#define GPMI_CTRL1_SET_BURST_EN(x) \
28972 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BURST_EN_SHIFT)) & GPMI_CTRL1_SET_BURST_EN_MASK)
28973#define GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK (0x200U)
28974#define GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT (9U)
28975#define GPMI_CTRL1_SET_TIMEOUT_IRQ(x) \
28976 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_MASK)
28977#define GPMI_CTRL1_SET_DEV_IRQ_MASK (0x400U)
28978#define GPMI_CTRL1_SET_DEV_IRQ_SHIFT (10U)
28979#define GPMI_CTRL1_SET_DEV_IRQ(x) \
28980 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_IRQ_SHIFT)) & GPMI_CTRL1_SET_DEV_IRQ_MASK)
28981#define GPMI_CTRL1_SET_DMA2ECC_MODE_MASK (0x800U)
28982#define GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT (11U)
28983#define GPMI_CTRL1_SET_DMA2ECC_MODE(x) \
28984 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_SET_DMA2ECC_MODE_MASK)
28985#define GPMI_CTRL1_SET_RDN_DELAY_MASK (0xF000U)
28986#define GPMI_CTRL1_SET_RDN_DELAY_SHIFT (12U)
28987#define GPMI_CTRL1_SET_RDN_DELAY(x) \
28988 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_RDN_DELAY_SHIFT)) & GPMI_CTRL1_SET_RDN_DELAY_MASK)
28989#define GPMI_CTRL1_SET_HALF_PERIOD_MASK (0x10000U)
28990#define GPMI_CTRL1_SET_HALF_PERIOD_SHIFT (16U)
28991#define GPMI_CTRL1_SET_HALF_PERIOD(x) \
28992 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_SET_HALF_PERIOD_MASK)
28993#define GPMI_CTRL1_SET_DLL_ENABLE_MASK (0x20000U)
28994#define GPMI_CTRL1_SET_DLL_ENABLE_SHIFT (17U)
28995#define GPMI_CTRL1_SET_DLL_ENABLE(x) \
28996 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_SET_DLL_ENABLE_MASK)
28997#define GPMI_CTRL1_SET_BCH_MODE_MASK (0x40000U)
28998#define GPMI_CTRL1_SET_BCH_MODE_SHIFT (18U)
28999#define GPMI_CTRL1_SET_BCH_MODE(x) \
29000 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_BCH_MODE_SHIFT)) & GPMI_CTRL1_SET_BCH_MODE_MASK)
29001#define GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK (0x80000U)
29002#define GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT (19U)
29003#define GPMI_CTRL1_SET_GANGED_RDYBUSY(x) \
29004 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_SET_GANGED_RDYBUSY_MASK)
29005#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK (0x100000U)
29006#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT (20U)
29007#define GPMI_CTRL1_SET_TIMEOUT_IRQ_EN(x) \
29008 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_SET_TIMEOUT_IRQ_EN_MASK)
29009#define GPMI_CTRL1_SET_TEST_TRIGGER_MASK (0x200000U)
29010#define GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT (21U)
29011/*! TEST_TRIGGER
29012 * 0b0..Disable
29013 * 0b1..Enable
29014 */
29015#define GPMI_CTRL1_SET_TEST_TRIGGER(x) \
29016 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_SET_TEST_TRIGGER_MASK)
29017#define GPMI_CTRL1_SET_WRN_DLY_SEL_MASK (0xC00000U)
29018#define GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT (22U)
29019#define GPMI_CTRL1_SET_WRN_DLY_SEL(x) \
29020 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_SET_WRN_DLY_SEL_MASK)
29021#define GPMI_CTRL1_SET_DECOUPLE_CS_MASK (0x1000000U)
29022#define GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT (24U)
29023#define GPMI_CTRL1_SET_DECOUPLE_CS(x) \
29024 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_SET_DECOUPLE_CS_MASK)
29025#define GPMI_CTRL1_SET_SSYNCMODE_MASK (0x2000000U)
29026#define GPMI_CTRL1_SET_SSYNCMODE_SHIFT (25U)
29027#define GPMI_CTRL1_SET_SSYNCMODE(x) \
29028 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SET_SSYNCMODE_MASK)
29029#define GPMI_CTRL1_SET_UPDATE_CS_MASK (0x4000000U)
29030#define GPMI_CTRL1_SET_UPDATE_CS_SHIFT (26U)
29031#define GPMI_CTRL1_SET_UPDATE_CS(x) \
29032 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_UPDATE_CS_SHIFT)) & GPMI_CTRL1_SET_UPDATE_CS_MASK)
29033#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK (0x8000000U)
29034#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT (27U)
29035/*! GPMI_CLK_DIV2_EN
29036 * 0b0..internal factor-2 clock divider is disabled
29037 * 0b1..internal factor-2 clock divider is enabled.
29038 */
29039#define GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN(x) \
29040 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_SET_GPMI_CLK_DIV2_EN_MASK)
29041#define GPMI_CTRL1_SET_TOGGLE_MODE_MASK (0x10000000U)
29042#define GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT (28U)
29043#define GPMI_CTRL1_SET_TOGGLE_MODE(x) \
29044 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_SET_TOGGLE_MODE_MASK)
29045#define GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK (0x20000000U)
29046#define GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT (29U)
29047#define GPMI_CTRL1_SET_WRITE_CLK_STOP(x) \
29048 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_WRITE_CLK_STOP_MASK)
29049#define GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK (0x40000000U)
29050#define GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT (30U)
29051#define GPMI_CTRL1_SET_SSYNC_CLK_STOP(x) \
29052 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_SSYNC_CLK_STOP_MASK)
29053#define GPMI_CTRL1_SET_DEV_CLK_STOP_MASK (0x80000000U)
29054#define GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT (31U)
29055#define GPMI_CTRL1_SET_DEV_CLK_STOP(x) \
29056 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SET_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_SET_DEV_CLK_STOP_MASK)
29057/*! @} */
29058
29059/*! @name CTRL1_CLR - GPMI Control Register 1 Description */
29060/*! @{ */
29061#define GPMI_CTRL1_CLR_GPMI_MODE_MASK (0x1U)
29062#define GPMI_CTRL1_CLR_GPMI_MODE_SHIFT (0U)
29063/*! GPMI_MODE
29064 * 0b0..NAND mode.
29065 * 0b1..ATA mode.
29066 */
29067#define GPMI_CTRL1_CLR_GPMI_MODE(x) \
29068 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_MODE_SHIFT)) & GPMI_CTRL1_CLR_GPMI_MODE_MASK)
29069#define GPMI_CTRL1_CLR_CAMERA_MODE_MASK (0x2U)
29070#define GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT (1U)
29071#define GPMI_CTRL1_CLR_CAMERA_MODE(x) \
29072 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CLR_CAMERA_MODE_MASK)
29073#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK (0x4U)
29074#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT (2U)
29075/*! ATA_IRQRDY_POLARITY
29076 * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
29077 * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
29078 */
29079#define GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY(x) \
29080 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_SHIFT)) & \
29081 GPMI_CTRL1_CLR_ATA_IRQRDY_POLARITY_MASK)
29082#define GPMI_CTRL1_CLR_DEV_RESET_MASK (0x8U)
29083#define GPMI_CTRL1_CLR_DEV_RESET_SHIFT (3U)
29084/*! DEV_RESET
29085 * 0b0..NANDF_WP_B pin is held low (asserted).
29086 * 0b1..NANDF_WP_B pin is held high (de-asserted).
29087 */
29088#define GPMI_CTRL1_CLR_DEV_RESET(x) \
29089 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_RESET_SHIFT)) & GPMI_CTRL1_CLR_DEV_RESET_MASK)
29090#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U)
29091#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U)
29092#define GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL(x) \
29093 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & \
29094 GPMI_CTRL1_CLR_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
29095#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK (0x80U)
29096#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT (7U)
29097#define GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST(x) \
29098 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_CLR_ABORT_WAIT_REQUEST_MASK)
29099#define GPMI_CTRL1_CLR_BURST_EN_MASK (0x100U)
29100#define GPMI_CTRL1_CLR_BURST_EN_SHIFT (8U)
29101#define GPMI_CTRL1_CLR_BURST_EN(x) \
29102 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BURST_EN_SHIFT)) & GPMI_CTRL1_CLR_BURST_EN_MASK)
29103#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK (0x200U)
29104#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT (9U)
29105#define GPMI_CTRL1_CLR_TIMEOUT_IRQ(x) \
29106 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_MASK)
29107#define GPMI_CTRL1_CLR_DEV_IRQ_MASK (0x400U)
29108#define GPMI_CTRL1_CLR_DEV_IRQ_SHIFT (10U)
29109#define GPMI_CTRL1_CLR_DEV_IRQ(x) \
29110 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_IRQ_SHIFT)) & GPMI_CTRL1_CLR_DEV_IRQ_MASK)
29111#define GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK (0x800U)
29112#define GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT (11U)
29113#define GPMI_CTRL1_CLR_DMA2ECC_MODE(x) \
29114 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_CLR_DMA2ECC_MODE_MASK)
29115#define GPMI_CTRL1_CLR_RDN_DELAY_MASK (0xF000U)
29116#define GPMI_CTRL1_CLR_RDN_DELAY_SHIFT (12U)
29117#define GPMI_CTRL1_CLR_RDN_DELAY(x) \
29118 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_RDN_DELAY_SHIFT)) & GPMI_CTRL1_CLR_RDN_DELAY_MASK)
29119#define GPMI_CTRL1_CLR_HALF_PERIOD_MASK (0x10000U)
29120#define GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT (16U)
29121#define GPMI_CTRL1_CLR_HALF_PERIOD(x) \
29122 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_CLR_HALF_PERIOD_MASK)
29123#define GPMI_CTRL1_CLR_DLL_ENABLE_MASK (0x20000U)
29124#define GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT (17U)
29125#define GPMI_CTRL1_CLR_DLL_ENABLE(x) \
29126 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_CLR_DLL_ENABLE_MASK)
29127#define GPMI_CTRL1_CLR_BCH_MODE_MASK (0x40000U)
29128#define GPMI_CTRL1_CLR_BCH_MODE_SHIFT (18U)
29129#define GPMI_CTRL1_CLR_BCH_MODE(x) \
29130 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_BCH_MODE_SHIFT)) & GPMI_CTRL1_CLR_BCH_MODE_MASK)
29131#define GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK (0x80000U)
29132#define GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT (19U)
29133#define GPMI_CTRL1_CLR_GANGED_RDYBUSY(x) \
29134 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_CLR_GANGED_RDYBUSY_MASK)
29135#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK (0x100000U)
29136#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT (20U)
29137#define GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN(x) \
29138 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_CLR_TIMEOUT_IRQ_EN_MASK)
29139#define GPMI_CTRL1_CLR_TEST_TRIGGER_MASK (0x200000U)
29140#define GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT (21U)
29141/*! TEST_TRIGGER
29142 * 0b0..Disable
29143 * 0b1..Enable
29144 */
29145#define GPMI_CTRL1_CLR_TEST_TRIGGER(x) \
29146 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_CLR_TEST_TRIGGER_MASK)
29147#define GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK (0xC00000U)
29148#define GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT (22U)
29149#define GPMI_CTRL1_CLR_WRN_DLY_SEL(x) \
29150 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_CLR_WRN_DLY_SEL_MASK)
29151#define GPMI_CTRL1_CLR_DECOUPLE_CS_MASK (0x1000000U)
29152#define GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT (24U)
29153#define GPMI_CTRL1_CLR_DECOUPLE_CS(x) \
29154 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_CLR_DECOUPLE_CS_MASK)
29155#define GPMI_CTRL1_CLR_SSYNCMODE_MASK (0x2000000U)
29156#define GPMI_CTRL1_CLR_SSYNCMODE_SHIFT (25U)
29157#define GPMI_CTRL1_CLR_SSYNCMODE(x) \
29158 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNCMODE_SHIFT)) & GPMI_CTRL1_CLR_SSYNCMODE_MASK)
29159#define GPMI_CTRL1_CLR_UPDATE_CS_MASK (0x4000000U)
29160#define GPMI_CTRL1_CLR_UPDATE_CS_SHIFT (26U)
29161#define GPMI_CTRL1_CLR_UPDATE_CS(x) \
29162 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_UPDATE_CS_SHIFT)) & GPMI_CTRL1_CLR_UPDATE_CS_MASK)
29163#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK (0x8000000U)
29164#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT (27U)
29165/*! GPMI_CLK_DIV2_EN
29166 * 0b0..internal factor-2 clock divider is disabled
29167 * 0b1..internal factor-2 clock divider is enabled.
29168 */
29169#define GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN(x) \
29170 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_CLR_GPMI_CLK_DIV2_EN_MASK)
29171#define GPMI_CTRL1_CLR_TOGGLE_MODE_MASK (0x10000000U)
29172#define GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT (28U)
29173#define GPMI_CTRL1_CLR_TOGGLE_MODE(x) \
29174 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_CLR_TOGGLE_MODE_MASK)
29175#define GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK (0x20000000U)
29176#define GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT (29U)
29177#define GPMI_CTRL1_CLR_WRITE_CLK_STOP(x) \
29178 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_WRITE_CLK_STOP_MASK)
29179#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK (0x40000000U)
29180#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT (30U)
29181#define GPMI_CTRL1_CLR_SSYNC_CLK_STOP(x) \
29182 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_SSYNC_CLK_STOP_MASK)
29183#define GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK (0x80000000U)
29184#define GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT (31U)
29185#define GPMI_CTRL1_CLR_DEV_CLK_STOP(x) \
29186 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CLR_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_CLR_DEV_CLK_STOP_MASK)
29187/*! @} */
29188
29189/*! @name CTRL1_TOG - GPMI Control Register 1 Description */
29190/*! @{ */
29191#define GPMI_CTRL1_TOG_GPMI_MODE_MASK (0x1U)
29192#define GPMI_CTRL1_TOG_GPMI_MODE_SHIFT (0U)
29193/*! GPMI_MODE
29194 * 0b0..NAND mode.
29195 * 0b1..ATA mode.
29196 */
29197#define GPMI_CTRL1_TOG_GPMI_MODE(x) \
29198 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_MODE_SHIFT)) & GPMI_CTRL1_TOG_GPMI_MODE_MASK)
29199#define GPMI_CTRL1_TOG_CAMERA_MODE_MASK (0x2U)
29200#define GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT (1U)
29201#define GPMI_CTRL1_TOG_CAMERA_MODE(x) \
29202 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_TOG_CAMERA_MODE_MASK)
29203#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK (0x4U)
29204#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT (2U)
29205/*! ATA_IRQRDY_POLARITY
29206 * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
29207 * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
29208 */
29209#define GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY(x) \
29210 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_SHIFT)) & \
29211 GPMI_CTRL1_TOG_ATA_IRQRDY_POLARITY_MASK)
29212#define GPMI_CTRL1_TOG_DEV_RESET_MASK (0x8U)
29213#define GPMI_CTRL1_TOG_DEV_RESET_SHIFT (3U)
29214/*! DEV_RESET
29215 * 0b0..NANDF_WP_B pin is held low (asserted).
29216 * 0b1..NANDF_WP_B pin is held high (de-asserted).
29217 */
29218#define GPMI_CTRL1_TOG_DEV_RESET(x) \
29219 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_RESET_SHIFT)) & GPMI_CTRL1_TOG_DEV_RESET_MASK)
29220#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U)
29221#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U)
29222#define GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL(x) \
29223 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & \
29224 GPMI_CTRL1_TOG_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
29225#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK (0x80U)
29226#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT (7U)
29227#define GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST(x) \
29228 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_TOG_ABORT_WAIT_REQUEST_MASK)
29229#define GPMI_CTRL1_TOG_BURST_EN_MASK (0x100U)
29230#define GPMI_CTRL1_TOG_BURST_EN_SHIFT (8U)
29231#define GPMI_CTRL1_TOG_BURST_EN(x) \
29232 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BURST_EN_SHIFT)) & GPMI_CTRL1_TOG_BURST_EN_MASK)
29233#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK (0x200U)
29234#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT (9U)
29235#define GPMI_CTRL1_TOG_TIMEOUT_IRQ(x) \
29236 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_MASK)
29237#define GPMI_CTRL1_TOG_DEV_IRQ_MASK (0x400U)
29238#define GPMI_CTRL1_TOG_DEV_IRQ_SHIFT (10U)
29239#define GPMI_CTRL1_TOG_DEV_IRQ(x) \
29240 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_IRQ_SHIFT)) & GPMI_CTRL1_TOG_DEV_IRQ_MASK)
29241#define GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK (0x800U)
29242#define GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT (11U)
29243#define GPMI_CTRL1_TOG_DMA2ECC_MODE(x) \
29244 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_TOG_DMA2ECC_MODE_MASK)
29245#define GPMI_CTRL1_TOG_RDN_DELAY_MASK (0xF000U)
29246#define GPMI_CTRL1_TOG_RDN_DELAY_SHIFT (12U)
29247#define GPMI_CTRL1_TOG_RDN_DELAY(x) \
29248 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_RDN_DELAY_SHIFT)) & GPMI_CTRL1_TOG_RDN_DELAY_MASK)
29249#define GPMI_CTRL1_TOG_HALF_PERIOD_MASK (0x10000U)
29250#define GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT (16U)
29251#define GPMI_CTRL1_TOG_HALF_PERIOD(x) \
29252 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_TOG_HALF_PERIOD_MASK)
29253#define GPMI_CTRL1_TOG_DLL_ENABLE_MASK (0x20000U)
29254#define GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT (17U)
29255#define GPMI_CTRL1_TOG_DLL_ENABLE(x) \
29256 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_TOG_DLL_ENABLE_MASK)
29257#define GPMI_CTRL1_TOG_BCH_MODE_MASK (0x40000U)
29258#define GPMI_CTRL1_TOG_BCH_MODE_SHIFT (18U)
29259#define GPMI_CTRL1_TOG_BCH_MODE(x) \
29260 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_BCH_MODE_SHIFT)) & GPMI_CTRL1_TOG_BCH_MODE_MASK)
29261#define GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK (0x80000U)
29262#define GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT (19U)
29263#define GPMI_CTRL1_TOG_GANGED_RDYBUSY(x) \
29264 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_TOG_GANGED_RDYBUSY_MASK)
29265#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK (0x100000U)
29266#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT (20U)
29267#define GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN(x) \
29268 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TOG_TIMEOUT_IRQ_EN_MASK)
29269#define GPMI_CTRL1_TOG_TEST_TRIGGER_MASK (0x200000U)
29270#define GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT (21U)
29271/*! TEST_TRIGGER
29272 * 0b0..Disable
29273 * 0b1..Enable
29274 */
29275#define GPMI_CTRL1_TOG_TEST_TRIGGER(x) \
29276 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TEST_TRIGGER_SHIFT)) & GPMI_CTRL1_TOG_TEST_TRIGGER_MASK)
29277#define GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK (0xC00000U)
29278#define GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT (22U)
29279#define GPMI_CTRL1_TOG_WRN_DLY_SEL(x) \
29280 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_TOG_WRN_DLY_SEL_MASK)
29281#define GPMI_CTRL1_TOG_DECOUPLE_CS_MASK (0x1000000U)
29282#define GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT (24U)
29283#define GPMI_CTRL1_TOG_DECOUPLE_CS(x) \
29284 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_TOG_DECOUPLE_CS_MASK)
29285#define GPMI_CTRL1_TOG_SSYNCMODE_MASK (0x2000000U)
29286#define GPMI_CTRL1_TOG_SSYNCMODE_SHIFT (25U)
29287#define GPMI_CTRL1_TOG_SSYNCMODE(x) \
29288 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNCMODE_SHIFT)) & GPMI_CTRL1_TOG_SSYNCMODE_MASK)
29289#define GPMI_CTRL1_TOG_UPDATE_CS_MASK (0x4000000U)
29290#define GPMI_CTRL1_TOG_UPDATE_CS_SHIFT (26U)
29291#define GPMI_CTRL1_TOG_UPDATE_CS(x) \
29292 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_UPDATE_CS_SHIFT)) & GPMI_CTRL1_TOG_UPDATE_CS_MASK)
29293#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK (0x8000000U)
29294#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT (27U)
29295/*! GPMI_CLK_DIV2_EN
29296 * 0b0..internal factor-2 clock divider is disabled
29297 * 0b1..internal factor-2 clock divider is enabled.
29298 */
29299#define GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN(x) \
29300 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_TOG_GPMI_CLK_DIV2_EN_MASK)
29301#define GPMI_CTRL1_TOG_TOGGLE_MODE_MASK (0x10000000U)
29302#define GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT (28U)
29303#define GPMI_CTRL1_TOG_TOGGLE_MODE(x) \
29304 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOG_TOGGLE_MODE_MASK)
29305#define GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK (0x20000000U)
29306#define GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT (29U)
29307#define GPMI_CTRL1_TOG_WRITE_CLK_STOP(x) \
29308 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_WRITE_CLK_STOP_MASK)
29309#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK (0x40000000U)
29310#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT (30U)
29311#define GPMI_CTRL1_TOG_SSYNC_CLK_STOP(x) \
29312 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_SSYNC_CLK_STOP_MASK)
29313#define GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK (0x80000000U)
29314#define GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT (31U)
29315#define GPMI_CTRL1_TOG_DEV_CLK_STOP(x) \
29316 (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOG_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_TOG_DEV_CLK_STOP_MASK)
29317/*! @} */
29318
29319/*! @name TIMING0 - GPMI Timing Register 0 Description */
29320/*! @{ */
29321#define GPMI_TIMING0_DATA_SETUP_MASK (0xFFU)
29322#define GPMI_TIMING0_DATA_SETUP_SHIFT (0U)
29323#define GPMI_TIMING0_DATA_SETUP(x) \
29324 (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_SETUP_SHIFT)) & GPMI_TIMING0_DATA_SETUP_MASK)
29325#define GPMI_TIMING0_DATA_HOLD_MASK (0xFF00U)
29326#define GPMI_TIMING0_DATA_HOLD_SHIFT (8U)
29327#define GPMI_TIMING0_DATA_HOLD(x) \
29328 (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_HOLD_SHIFT)) & GPMI_TIMING0_DATA_HOLD_MASK)
29329#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xFF0000U)
29330#define GPMI_TIMING0_ADDRESS_SETUP_SHIFT (16U)
29331#define GPMI_TIMING0_ADDRESS_SETUP(x) \
29332 (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_ADDRESS_SETUP_SHIFT)) & GPMI_TIMING0_ADDRESS_SETUP_MASK)
29333#define GPMI_TIMING0_RSVD1_MASK (0xFF000000U)
29334#define GPMI_TIMING0_RSVD1_SHIFT (24U)
29335#define GPMI_TIMING0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_RSVD1_SHIFT)) & GPMI_TIMING0_RSVD1_MASK)
29336/*! @} */
29337
29338/*! @name TIMING1 - GPMI Timing Register 1 Description */
29339/*! @{ */
29340#define GPMI_TIMING1_RSVD1_MASK (0xFFFFU)
29341#define GPMI_TIMING1_RSVD1_SHIFT (0U)
29342#define GPMI_TIMING1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_RSVD1_SHIFT)) & GPMI_TIMING1_RSVD1_MASK)
29343#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xFFFF0000U)
29344#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT (16U)
29345#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(x) \
29346 (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT)) & GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK)
29347/*! @} */
29348
29349/*! @name TIMING2 - GPMI Timing Register 2 Description */
29350/*! @{ */
29351#define GPMI_TIMING2_DATA_PAUSE_MASK (0xFU)
29352#define GPMI_TIMING2_DATA_PAUSE_SHIFT (0U)
29353#define GPMI_TIMING2_DATA_PAUSE(x) \
29354 (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_DATA_PAUSE_SHIFT)) & GPMI_TIMING2_DATA_PAUSE_MASK)
29355#define GPMI_TIMING2_CMDADD_PAUSE_MASK (0xF0U)
29356#define GPMI_TIMING2_CMDADD_PAUSE_SHIFT (4U)
29357#define GPMI_TIMING2_CMDADD_PAUSE(x) \
29358 (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CMDADD_PAUSE_SHIFT)) & GPMI_TIMING2_CMDADD_PAUSE_MASK)
29359#define GPMI_TIMING2_POSTAMBLE_DELAY_MASK (0xF00U)
29360#define GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT (8U)
29361#define GPMI_TIMING2_POSTAMBLE_DELAY(x) \
29362 (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_POSTAMBLE_DELAY_MASK)
29363#define GPMI_TIMING2_PREAMBLE_DELAY_MASK (0xF000U)
29364#define GPMI_TIMING2_PREAMBLE_DELAY_SHIFT (12U)
29365#define GPMI_TIMING2_PREAMBLE_DELAY(x) \
29366 (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_PREAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_PREAMBLE_DELAY_MASK)
29367#define GPMI_TIMING2_CE_DELAY_MASK (0x1F0000U)
29368#define GPMI_TIMING2_CE_DELAY_SHIFT (16U)
29369#define GPMI_TIMING2_CE_DELAY(x) \
29370 (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CE_DELAY_SHIFT)) & GPMI_TIMING2_CE_DELAY_MASK)
29371#define GPMI_TIMING2_RSVD0_MASK (0xE00000U)
29372#define GPMI_TIMING2_RSVD0_SHIFT (21U)
29373#define GPMI_TIMING2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_RSVD0_SHIFT)) & GPMI_TIMING2_RSVD0_MASK)
29374#define GPMI_TIMING2_READ_LATENCY_MASK (0x7000000U)
29375#define GPMI_TIMING2_READ_LATENCY_SHIFT (24U)
29376/*! READ_LATENCY
29377 * 0b000..READ LATENCY is 0
29378 * 0b001..READ LATENCY is 1
29379 * 0b010..READ LATENCY is 2
29380 * 0b011..READ LATENCY is 3
29381 * 0b100..READ LATENCY is 4
29382 * 0b101..READ LATENCY is 5
29383 */
29384#define GPMI_TIMING2_READ_LATENCY(x) \
29385 (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_READ_LATENCY_SHIFT)) & GPMI_TIMING2_READ_LATENCY_MASK)
29386#define GPMI_TIMING2_TCR_MASK (0x18000000U)
29387#define GPMI_TIMING2_TCR_SHIFT (27U)
29388#define GPMI_TIMING2_TCR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TCR_SHIFT)) & GPMI_TIMING2_TCR_MASK)
29389#define GPMI_TIMING2_TRPSTH_MASK (0xE0000000U)
29390#define GPMI_TIMING2_TRPSTH_SHIFT (29U)
29391#define GPMI_TIMING2_TRPSTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TRPSTH_SHIFT)) & GPMI_TIMING2_TRPSTH_MASK)
29392/*! @} */
29393
29394/*! @name DATA - GPMI DMA Data Transfer Register Description */
29395/*! @{ */
29396#define GPMI_DATA_DATA_MASK (0xFFFFFFFFU)
29397#define GPMI_DATA_DATA_SHIFT (0U)
29398#define GPMI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DATA_DATA_SHIFT)) & GPMI_DATA_DATA_MASK)
29399/*! @} */
29400
29401/*! @name STAT - GPMI Status Register Description */
29402/*! @{ */
29403#define GPMI_STAT_PRESENT_MASK (0x1U)
29404#define GPMI_STAT_PRESENT_SHIFT (0U)
29405/*! PRESENT
29406 * 0b0..GPMI is not present in this product.
29407 * 0b1..GPMI is present is in this product.
29408 */
29409#define GPMI_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_PRESENT_SHIFT)) & GPMI_STAT_PRESENT_MASK)
29410#define GPMI_STAT_FIFO_FULL_MASK (0x2U)
29411#define GPMI_STAT_FIFO_FULL_SHIFT (1U)
29412/*! FIFO_FULL
29413 * 0b0..FIFO is not full.
29414 * 0b1..FIFO is full.
29415 */
29416#define GPMI_STAT_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_FULL_SHIFT)) & GPMI_STAT_FIFO_FULL_MASK)
29417#define GPMI_STAT_FIFO_EMPTY_MASK (0x4U)
29418#define GPMI_STAT_FIFO_EMPTY_SHIFT (2U)
29419/*! FIFO_EMPTY
29420 * 0b0..FIFO is not empty.
29421 * 0b1..FIFO is empty.
29422 */
29423#define GPMI_STAT_FIFO_EMPTY(x) \
29424 (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_EMPTY_SHIFT)) & GPMI_STAT_FIFO_EMPTY_MASK)
29425#define GPMI_STAT_INVALID_BUFFER_MASK_MASK (0x8U)
29426#define GPMI_STAT_INVALID_BUFFER_MASK_SHIFT (3U)
29427/*! INVALID_BUFFER_MASK
29428 * 0b0..ECC Buffer Mask is not invalid.
29429 * 0b1..ECC Buffer Mask is invalid.
29430 */
29431#define GPMI_STAT_INVALID_BUFFER_MASK(x) \
29432 (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_INVALID_BUFFER_MASK_SHIFT)) & GPMI_STAT_INVALID_BUFFER_MASK_MASK)
29433#define GPMI_STAT_ATA_IRQ_MASK (0x10U)
29434#define GPMI_STAT_ATA_IRQ_SHIFT (4U)
29435#define GPMI_STAT_ATA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_ATA_IRQ_SHIFT)) & GPMI_STAT_ATA_IRQ_MASK)
29436#define GPMI_STAT_RSVD1_MASK (0xE0U)
29437#define GPMI_STAT_RSVD1_SHIFT (5U)
29438#define GPMI_STAT_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RSVD1_SHIFT)) & GPMI_STAT_RSVD1_MASK)
29439#define GPMI_STAT_DEV0_ERROR_MASK (0x100U)
29440#define GPMI_STAT_DEV0_ERROR_SHIFT (8U)
29441/*! DEV0_ERROR
29442 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 0.
29443 * 0b1..An Error has occurred on ATA/NAND Device accessed by
29444 */
29445#define GPMI_STAT_DEV0_ERROR(x) \
29446 (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV0_ERROR_SHIFT)) & GPMI_STAT_DEV0_ERROR_MASK)
29447#define GPMI_STAT_DEV1_ERROR_MASK (0x200U)
29448#define GPMI_STAT_DEV1_ERROR_SHIFT (9U)
29449/*! DEV1_ERROR
29450 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 1.
29451 * 0b1..An Error has occurred on ATA/NAND Device accessed by
29452 */
29453#define GPMI_STAT_DEV1_ERROR(x) \
29454 (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV1_ERROR_SHIFT)) & GPMI_STAT_DEV1_ERROR_MASK)
29455#define GPMI_STAT_DEV2_ERROR_MASK (0x400U)
29456#define GPMI_STAT_DEV2_ERROR_SHIFT (10U)
29457/*! DEV2_ERROR
29458 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 2.
29459 * 0b1..An Error has occurred on ATA/NAND Device accessed by
29460 */
29461#define GPMI_STAT_DEV2_ERROR(x) \
29462 (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV2_ERROR_SHIFT)) & GPMI_STAT_DEV2_ERROR_MASK)
29463#define GPMI_STAT_DEV3_ERROR_MASK (0x800U)
29464#define GPMI_STAT_DEV3_ERROR_SHIFT (11U)
29465/*! DEV3_ERROR
29466 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 3.
29467 * 0b1..An Error has occurred on ATA/NAND Device accessed by
29468 */
29469#define GPMI_STAT_DEV3_ERROR(x) \
29470 (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV3_ERROR_SHIFT)) & GPMI_STAT_DEV3_ERROR_MASK)
29471#define GPMI_STAT_DEV4_ERROR_MASK (0x1000U)
29472#define GPMI_STAT_DEV4_ERROR_SHIFT (12U)
29473/*! DEV4_ERROR
29474 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 4.
29475 * 0b1..An Error has occurred on ATA/NAND Device accessed by
29476 */
29477#define GPMI_STAT_DEV4_ERROR(x) \
29478 (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV4_ERROR_SHIFT)) & GPMI_STAT_DEV4_ERROR_MASK)
29479#define GPMI_STAT_DEV5_ERROR_MASK (0x2000U)
29480#define GPMI_STAT_DEV5_ERROR_SHIFT (13U)
29481/*! DEV5_ERROR
29482 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 5.
29483 * 0b1..An Error has occurred on ATA/NAND Device accessed by
29484 */
29485#define GPMI_STAT_DEV5_ERROR(x) \
29486 (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV5_ERROR_SHIFT)) & GPMI_STAT_DEV5_ERROR_MASK)
29487#define GPMI_STAT_DEV6_ERROR_MASK (0x4000U)
29488#define GPMI_STAT_DEV6_ERROR_SHIFT (14U)
29489/*! DEV6_ERROR
29490 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 6.
29491 * 0b1..An Error has occurred on ATA/NAND Device accessed by
29492 */
29493#define GPMI_STAT_DEV6_ERROR(x) \
29494 (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV6_ERROR_SHIFT)) & GPMI_STAT_DEV6_ERROR_MASK)
29495#define GPMI_STAT_DEV7_ERROR_MASK (0x8000U)
29496#define GPMI_STAT_DEV7_ERROR_SHIFT (15U)
29497/*! DEV7_ERROR
29498 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 7.
29499 * 0b1..An Error has occurred on ATA/NAND Device accessed by
29500 */
29501#define GPMI_STAT_DEV7_ERROR(x) \
29502 (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV7_ERROR_SHIFT)) & GPMI_STAT_DEV7_ERROR_MASK)
29503#define GPMI_STAT_RDY_TIMEOUT_MASK (0xFF0000U)
29504#define GPMI_STAT_RDY_TIMEOUT_SHIFT (16U)
29505#define GPMI_STAT_RDY_TIMEOUT(x) \
29506 (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RDY_TIMEOUT_SHIFT)) & GPMI_STAT_RDY_TIMEOUT_MASK)
29507#define GPMI_STAT_READY_BUSY_MASK (0xFF000000U)
29508#define GPMI_STAT_READY_BUSY_SHIFT (24U)
29509#define GPMI_STAT_READY_BUSY(x) \
29510 (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_READY_BUSY_SHIFT)) & GPMI_STAT_READY_BUSY_MASK)
29511/*! @} */
29512
29513/*! @name DEBUG - GPMI Debug Information Register Description */
29514/*! @{ */
29515#define GPMI_DEBUG_CMD_END_MASK (0xFFU)
29516#define GPMI_DEBUG_CMD_END_SHIFT (0U)
29517#define GPMI_DEBUG_CMD_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_CMD_END_SHIFT)) & GPMI_DEBUG_CMD_END_MASK)
29518#define GPMI_DEBUG_DMAREQ_MASK (0xFF00U)
29519#define GPMI_DEBUG_DMAREQ_SHIFT (8U)
29520#define GPMI_DEBUG_DMAREQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMAREQ_SHIFT)) & GPMI_DEBUG_DMAREQ_MASK)
29521#define GPMI_DEBUG_DMA_SENSE_MASK (0xFF0000U)
29522#define GPMI_DEBUG_DMA_SENSE_SHIFT (16U)
29523#define GPMI_DEBUG_DMA_SENSE(x) \
29524 (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMA_SENSE_SHIFT)) & GPMI_DEBUG_DMA_SENSE_MASK)
29525#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xFF000000U)
29526#define GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT (24U)
29527#define GPMI_DEBUG_WAIT_FOR_READY_END(x) \
29528 (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT)) & GPMI_DEBUG_WAIT_FOR_READY_END_MASK)
29529/*! @} */
29530
29531/*! @name VERSION - GPMI Version Register Description */
29532/*! @{ */
29533#define GPMI_VERSION_STEP_MASK (0xFFFFU)
29534#define GPMI_VERSION_STEP_SHIFT (0U)
29535#define GPMI_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_STEP_SHIFT)) & GPMI_VERSION_STEP_MASK)
29536#define GPMI_VERSION_MINOR_MASK (0xFF0000U)
29537#define GPMI_VERSION_MINOR_SHIFT (16U)
29538#define GPMI_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MINOR_SHIFT)) & GPMI_VERSION_MINOR_MASK)
29539#define GPMI_VERSION_MAJOR_MASK (0xFF000000U)
29540#define GPMI_VERSION_MAJOR_SHIFT (24U)
29541#define GPMI_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MAJOR_SHIFT)) & GPMI_VERSION_MAJOR_MASK)
29542/*! @} */
29543
29544/*! @name DEBUG2 - GPMI Debug2 Information Register Description */
29545/*! @{ */
29546#define GPMI_DEBUG2_RDN_TAP_MASK (0x3FU)
29547#define GPMI_DEBUG2_RDN_TAP_SHIFT (0U)
29548#define GPMI_DEBUG2_RDN_TAP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RDN_TAP_SHIFT)) & GPMI_DEBUG2_RDN_TAP_MASK)
29549#define GPMI_DEBUG2_UPDATE_WINDOW_MASK (0x40U)
29550#define GPMI_DEBUG2_UPDATE_WINDOW_SHIFT (6U)
29551#define GPMI_DEBUG2_UPDATE_WINDOW(x) \
29552 (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UPDATE_WINDOW_SHIFT)) & GPMI_DEBUG2_UPDATE_WINDOW_MASK)
29553#define GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK (0x80U)
29554#define GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT (7U)
29555#define GPMI_DEBUG2_VIEW_DELAYED_RDN(x) \
29556 (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT)) & GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK)
29557#define GPMI_DEBUG2_SYND2GPMI_READY_MASK (0x100U)
29558#define GPMI_DEBUG2_SYND2GPMI_READY_SHIFT (8U)
29559#define GPMI_DEBUG2_SYND2GPMI_READY(x) \
29560 (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_READY_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_READY_MASK)
29561#define GPMI_DEBUG2_SYND2GPMI_VALID_MASK (0x200U)
29562#define GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT (9U)
29563#define GPMI_DEBUG2_SYND2GPMI_VALID(x) \
29564 (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_VALID_MASK)
29565#define GPMI_DEBUG2_GPMI2SYND_READY_MASK (0x400U)
29566#define GPMI_DEBUG2_GPMI2SYND_READY_SHIFT (10U)
29567#define GPMI_DEBUG2_GPMI2SYND_READY(x) \
29568 (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_READY_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_READY_MASK)
29569#define GPMI_DEBUG2_GPMI2SYND_VALID_MASK (0x800U)
29570#define GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT (11U)
29571#define GPMI_DEBUG2_GPMI2SYND_VALID(x) \
29572 (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_VALID_MASK)
29573#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xF000U)
29574#define GPMI_DEBUG2_SYND2GPMI_BE_SHIFT (12U)
29575#define GPMI_DEBUG2_SYND2GPMI_BE(x) \
29576 (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_BE_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_BE_MASK)
29577#define GPMI_DEBUG2_MAIN_STATE_MASK (0xF0000U)
29578#define GPMI_DEBUG2_MAIN_STATE_SHIFT (16U)
29579#define GPMI_DEBUG2_MAIN_STATE(x) \
29580 (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_MAIN_STATE_SHIFT)) & GPMI_DEBUG2_MAIN_STATE_MASK)
29581#define GPMI_DEBUG2_PIN_STATE_MASK (0x700000U)
29582#define GPMI_DEBUG2_PIN_STATE_SHIFT (20U)
29583#define GPMI_DEBUG2_PIN_STATE(x) \
29584 (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_PIN_STATE_SHIFT)) & GPMI_DEBUG2_PIN_STATE_MASK)
29585#define GPMI_DEBUG2_BUSY_MASK (0x800000U)
29586#define GPMI_DEBUG2_BUSY_SHIFT (23U)
29587#define GPMI_DEBUG2_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_BUSY_SHIFT)) & GPMI_DEBUG2_BUSY_MASK)
29588#define GPMI_DEBUG2_UDMA_STATE_MASK (0xF000000U)
29589#define GPMI_DEBUG2_UDMA_STATE_SHIFT (24U)
29590#define GPMI_DEBUG2_UDMA_STATE(x) \
29591 (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UDMA_STATE_SHIFT)) & GPMI_DEBUG2_UDMA_STATE_MASK)
29592#define GPMI_DEBUG2_RSVD1_MASK (0xF0000000U)
29593#define GPMI_DEBUG2_RSVD1_SHIFT (28U)
29594#define GPMI_DEBUG2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RSVD1_SHIFT)) & GPMI_DEBUG2_RSVD1_MASK)
29595/*! @} */
29596
29597/*! @name DEBUG3 - GPMI Debug3 Information Register Description */
29598/*! @{ */
29599#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK (0xFFFFU)
29600#define GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT (0U)
29601#define GPMI_DEBUG3_DEV_WORD_CNTR(x) \
29602 (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_DEV_WORD_CNTR_MASK)
29603#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xFFFF0000U)
29604#define GPMI_DEBUG3_APB_WORD_CNTR_SHIFT (16U)
29605#define GPMI_DEBUG3_APB_WORD_CNTR(x) \
29606 (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_APB_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_APB_WORD_CNTR_MASK)
29607/*! @} */
29608
29609/*! @name READ_DDR_DLL_CTRL - GPMI Double Rate Read DLL Control Register Description */
29610/*! @{ */
29611#define GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK (0x1U)
29612#define GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT (0U)
29613#define GPMI_READ_DDR_DLL_CTRL_ENABLE(x) \
29614 (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK)
29615#define GPMI_READ_DDR_DLL_CTRL_RESET_MASK (0x2U)
29616#define GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT (1U)
29617#define GPMI_READ_DDR_DLL_CTRL_RESET(x) \
29618 (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RESET_MASK)
29619#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
29620#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
29621#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD(x) \
29622 (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & \
29623 GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK)
29624#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
29625#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
29626#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(x) \
29627 (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & \
29628 GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK)
29629#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
29630#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
29631#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE(x) \
29632 (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & \
29633 GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK)
29634#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U)
29635#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U)
29636#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON(x) \
29637 (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK)
29638#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U)
29639#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U)
29640#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE(x) \
29641 (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & \
29642 GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK)
29643#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U)
29644#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U)
29645#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) \
29646 (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & \
29647 GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
29648#define GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U)
29649#define GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT (18U)
29650#define GPMI_READ_DDR_DLL_CTRL_RSVD1(x) \
29651 (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK)
29652#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
29653#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
29654#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(x) \
29655 (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & \
29656 GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK)
29657#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
29658#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
29659#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(x) \
29660 (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & \
29661 GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK)
29662/*! @} */
29663
29664/*! @name WRITE_DDR_DLL_CTRL - GPMI Double Rate Write DLL Control Register Description */
29665/*! @{ */
29666#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK (0x1U)
29667#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT (0U)
29668#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE(x) \
29669 (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK)
29670#define GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK (0x2U)
29671#define GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT (1U)
29672#define GPMI_WRITE_DDR_DLL_CTRL_RESET(x) \
29673 (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK)
29674#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
29675#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
29676#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD(x) \
29677 (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & \
29678 GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK)
29679#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
29680#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
29681#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(x) \
29682 (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & \
29683 GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK)
29684#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
29685#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
29686#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE(x) \
29687 (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & \
29688 GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK)
29689#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U)
29690#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U)
29691#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON(x) \
29692 (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK)
29693#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U)
29694#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U)
29695#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE(x) \
29696 (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & \
29697 GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK)
29698#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U)
29699#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U)
29700#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) \
29701 (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & \
29702 GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
29703#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U)
29704#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT (18U)
29705#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1(x) \
29706 (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK)
29707#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
29708#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
29709#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(x) \
29710 (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & \
29711 GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK)
29712#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
29713#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
29714#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(x) \
29715 (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & \
29716 GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK)
29717/*! @} */
29718
29719/*! @name READ_DDR_DLL_STS - GPMI Double Rate Read DLL Status Register Description */
29720/*! @{ */
29721#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK (0x1U)
29722#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT (0U)
29723#define GPMI_READ_DDR_DLL_STS_SLV_LOCK(x) \
29724 (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK)
29725#define GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU)
29726#define GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT (1U)
29727#define GPMI_READ_DDR_DLL_STS_SLV_SEL(x) \
29728 (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK)
29729#define GPMI_READ_DDR_DLL_STS_RSVD0_MASK (0xFE00U)
29730#define GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT (9U)
29731#define GPMI_READ_DDR_DLL_STS_RSVD0(x) \
29732 (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD0_MASK)
29733#define GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK (0x10000U)
29734#define GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT (16U)
29735#define GPMI_READ_DDR_DLL_STS_REF_LOCK(x) \
29736 (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK)
29737#define GPMI_READ_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U)
29738#define GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT (17U)
29739#define GPMI_READ_DDR_DLL_STS_REF_SEL(x) \
29740 (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_SEL_MASK)
29741#define GPMI_READ_DDR_DLL_STS_RSVD1_MASK (0xFE000000U)
29742#define GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT (25U)
29743#define GPMI_READ_DDR_DLL_STS_RSVD1(x) \
29744 (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD1_MASK)
29745/*! @} */
29746
29747/*! @name WRITE_DDR_DLL_STS - GPMI Double Rate Write DLL Status Register Description */
29748/*! @{ */
29749#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK (0x1U)
29750#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT (0U)
29751#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK(x) \
29752 (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK)
29753#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU)
29754#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT (1U)
29755#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL(x) \
29756 (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK)
29757#define GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK (0xFE00U)
29758#define GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT (9U)
29759#define GPMI_WRITE_DDR_DLL_STS_RSVD0(x) \
29760 (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK)
29761#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK (0x10000U)
29762#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT (16U)
29763#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK(x) \
29764 (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK)
29765#define GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U)
29766#define GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT (17U)
29767#define GPMI_WRITE_DDR_DLL_STS_REF_SEL(x) \
29768 (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK)
29769#define GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK (0xFE000000U)
29770#define GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT (25U)
29771#define GPMI_WRITE_DDR_DLL_STS_RSVD1(x) \
29772 (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK)
29773/*! @} */
29774
29775/*!
29776 * @}
29777 */ /* end of group GPMI_Register_Masks */
29778
29779/* GPMI - Peripheral instance base addresses */
29780/** Peripheral GPMI base address */
29781#define GPMI_BASE (0x33002000u)
29782/** Peripheral GPMI base pointer */
29783#define GPMI ((GPMI_Type *)GPMI_BASE)
29784/** Array initializer of GPMI peripheral base addresses */
29785#define GPMI_BASE_ADDRS \
29786 { \
29787 GPMI_BASE \
29788 }
29789/** Array initializer of GPMI peripheral base pointers */
29790#define GPMI_BASE_PTRS \
29791 { \
29792 GPMI \
29793 }
29794
29795/*!
29796 * @}
29797 */ /* end of group GPMI_Peripheral_Access_Layer */
29798
29799/* ----------------------------------------------------------------------------
29800 -- GPT Peripheral Access Layer
29801 ---------------------------------------------------------------------------- */
29802
29803/*!
29804 * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer
29805 * @{
29806 */
29807
29808/** GPT - Register Layout Typedef */
29809typedef struct
29810{
29811 __IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */
29812 __IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */
29813 __IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */
29814 __IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */
29815 __IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array
29816 step: 0x4 */
29817 __I uint32_t
29818 ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */
29819 __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */
29820} GPT_Type;
29821
29822/* ----------------------------------------------------------------------------
29823 -- GPT Register Masks
29824 ---------------------------------------------------------------------------- */
29825
29826/*!
29827 * @addtogroup GPT_Register_Masks GPT Register Masks
29828 * @{
29829 */
29830
29831/*! @name CR - GPT Control Register */
29832/*! @{ */
29833#define GPT_CR_EN_MASK (0x1U)
29834#define GPT_CR_EN_SHIFT (0U)
29835/*! EN
29836 * 0b0..GPT is disabled.
29837 * 0b1..GPT is enabled.
29838 */
29839#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
29840#define GPT_CR_ENMOD_MASK (0x2U)
29841#define GPT_CR_ENMOD_SHIFT (1U)
29842/*! ENMOD
29843 * 0b0..GPT counter will retain its value when it is disabled.
29844 * 0b1..GPT counter value is reset to 0 when it is disabled.
29845 */
29846#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
29847#define GPT_CR_DBGEN_MASK (0x4U)
29848#define GPT_CR_DBGEN_SHIFT (2U)
29849/*! DBGEN
29850 * 0b0..GPT is disabled in debug mode.
29851 * 0b1..GPT is enabled in debug mode.
29852 */
29853#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
29854#define GPT_CR_WAITEN_MASK (0x8U)
29855#define GPT_CR_WAITEN_SHIFT (3U)
29856/*! WAITEN
29857 * 0b0..GPT is disabled in wait mode.
29858 * 0b1..GPT is enabled in wait mode.
29859 */
29860#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
29861#define GPT_CR_DOZEEN_MASK (0x10U)
29862#define GPT_CR_DOZEEN_SHIFT (4U)
29863/*! DOZEEN
29864 * 0b0..GPT is disabled in doze mode.
29865 * 0b1..GPT is enabled in doze mode.
29866 */
29867#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
29868#define GPT_CR_STOPEN_MASK (0x20U)
29869#define GPT_CR_STOPEN_SHIFT (5U)
29870/*! STOPEN
29871 * 0b0..GPT is disabled in Stop mode.
29872 * 0b1..GPT is enabled in Stop mode.
29873 */
29874#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
29875#define GPT_CR_CLKSRC_MASK (0x1C0U)
29876#define GPT_CR_CLKSRC_SHIFT (6U)
29877/*! CLKSRC
29878 * 0b000..No clock
29879 * 0b001..Peripheral Clock (ipg_clk)
29880 * 0b010..High Frequency Reference Clock (ipg_clk_highfreq)
29881 * 0b011..External Clock
29882 * 0b100..Low Frequency Reference Clock (ipg_clk_32k)
29883 * 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M)
29884 */
29885#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
29886#define GPT_CR_FRR_MASK (0x200U)
29887#define GPT_CR_FRR_SHIFT (9U)
29888/*! FRR
29889 * 0b0..Restart mode
29890 * 0b1..Free-Run mode
29891 */
29892#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
29893#define GPT_CR_EN_24M_MASK (0x400U)
29894#define GPT_CR_EN_24M_SHIFT (10U)
29895/*! EN_24M
29896 * 0b0..24M clock disabled
29897 * 0b1..24M clock enabled
29898 */
29899#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
29900#define GPT_CR_SWR_MASK (0x8000U)
29901#define GPT_CR_SWR_SHIFT (15U)
29902/*! SWR
29903 * 0b0..GPT is not in reset state
29904 * 0b1..GPT is in reset state
29905 */
29906#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
29907#define GPT_CR_IM1_MASK (0x30000U)
29908#define GPT_CR_IM1_SHIFT (16U)
29909#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
29910#define GPT_CR_IM2_MASK (0xC0000U)
29911#define GPT_CR_IM2_SHIFT (18U)
29912/*! IM2
29913 * 0b00..capture disabled
29914 * 0b01..capture on rising edge only
29915 * 0b10..capture on falling edge only
29916 * 0b11..capture on both edges
29917 */
29918#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
29919#define GPT_CR_OM1_MASK (0x700000U)
29920#define GPT_CR_OM1_SHIFT (20U)
29921#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
29922#define GPT_CR_OM2_MASK (0x3800000U)
29923#define GPT_CR_OM2_SHIFT (23U)
29924#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
29925#define GPT_CR_OM3_MASK (0x1C000000U)
29926#define GPT_CR_OM3_SHIFT (26U)
29927/*! OM3
29928 * 0b000..Output disconnected. No response on pin.
29929 * 0b001..Toggle output pin
29930 * 0b010..Clear output pin
29931 * 0b011..Set output pin
29932 * 0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin.
29933 */
29934#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
29935#define GPT_CR_FO1_MASK (0x20000000U)
29936#define GPT_CR_FO1_SHIFT (29U)
29937#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
29938#define GPT_CR_FO2_MASK (0x40000000U)
29939#define GPT_CR_FO2_SHIFT (30U)
29940#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
29941#define GPT_CR_FO3_MASK (0x80000000U)
29942#define GPT_CR_FO3_SHIFT (31U)
29943/*! FO3
29944 * 0b0..Writing a 0 has no effect.
29945 * 0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set.
29946 */
29947#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
29948/*! @} */
29949
29950/*! @name PR - GPT Prescaler Register */
29951/*! @{ */
29952#define GPT_PR_PRESCALER_MASK (0xFFFU)
29953#define GPT_PR_PRESCALER_SHIFT (0U)
29954/*! PRESCALER
29955 * 0b000000000000..Divide by 1
29956 * 0b000000000001..Divide by 2
29957 * 0b111111111111..Divide by 4096
29958 */
29959#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
29960#define GPT_PR_PRESCALER24M_MASK (0xF000U)
29961#define GPT_PR_PRESCALER24M_SHIFT (12U)
29962/*! PRESCALER24M
29963 * 0b0000..Divide by 1
29964 * 0b0001..Divide by 2
29965 * 0b1111..Divide by 16
29966 */
29967#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
29968/*! @} */
29969
29970/*! @name SR - GPT Status Register */
29971/*! @{ */
29972#define GPT_SR_OF1_MASK (0x1U)
29973#define GPT_SR_OF1_SHIFT (0U)
29974#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
29975#define GPT_SR_OF2_MASK (0x2U)
29976#define GPT_SR_OF2_SHIFT (1U)
29977#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
29978#define GPT_SR_OF3_MASK (0x4U)
29979#define GPT_SR_OF3_SHIFT (2U)
29980/*! OF3
29981 * 0b0..Compare event has not occurred.
29982 * 0b1..Compare event has occurred.
29983 */
29984#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
29985#define GPT_SR_IF1_MASK (0x8U)
29986#define GPT_SR_IF1_SHIFT (3U)
29987#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
29988#define GPT_SR_IF2_MASK (0x10U)
29989#define GPT_SR_IF2_SHIFT (4U)
29990/*! IF2
29991 * 0b0..Capture event has not occurred.
29992 * 0b1..Capture event has occurred.
29993 */
29994#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
29995#define GPT_SR_ROV_MASK (0x20U)
29996#define GPT_SR_ROV_SHIFT (5U)
29997/*! ROV
29998 * 0b0..Rollover has not occurred.
29999 * 0b1..Rollover has occurred.
30000 */
30001#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
30002/*! @} */
30003
30004/*! @name IR - GPT Interrupt Register */
30005/*! @{ */
30006#define GPT_IR_OF1IE_MASK (0x1U)
30007#define GPT_IR_OF1IE_SHIFT (0U)
30008#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
30009#define GPT_IR_OF2IE_MASK (0x2U)
30010#define GPT_IR_OF2IE_SHIFT (1U)
30011#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
30012#define GPT_IR_OF3IE_MASK (0x4U)
30013#define GPT_IR_OF3IE_SHIFT (2U)
30014/*! OF3IE
30015 * 0b0..Output Compare Channel n interrupt is disabled.
30016 * 0b1..Output Compare Channel n interrupt is enabled.
30017 */
30018#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
30019#define GPT_IR_IF1IE_MASK (0x8U)
30020#define GPT_IR_IF1IE_SHIFT (3U)
30021#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
30022#define GPT_IR_IF2IE_MASK (0x10U)
30023#define GPT_IR_IF2IE_SHIFT (4U)
30024/*! IF2IE
30025 * 0b0..IF2IE Input Capture n Interrupt Enable is disabled.
30026 * 0b1..IF2IE Input Capture n Interrupt Enable is enabled.
30027 */
30028#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
30029#define GPT_IR_ROVIE_MASK (0x20U)
30030#define GPT_IR_ROVIE_SHIFT (5U)
30031/*! ROVIE
30032 * 0b0..Rollover interrupt is disabled.
30033 * 0b1..Rollover interrupt enabled.
30034 */
30035#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
30036/*! @} */
30037
30038/*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */
30039/*! @{ */
30040#define GPT_OCR_COMP_MASK (0xFFFFFFFFU)
30041#define GPT_OCR_COMP_SHIFT (0U)
30042#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
30043/*! @} */
30044
30045/* The count of GPT_OCR */
30046#define GPT_OCR_COUNT (3U)
30047
30048/*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */
30049/*! @{ */
30050#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU)
30051#define GPT_ICR_CAPT_SHIFT (0U)
30052#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
30053/*! @} */
30054
30055/* The count of GPT_ICR */
30056#define GPT_ICR_COUNT (2U)
30057
30058/*! @name CNT - GPT Counter Register */
30059/*! @{ */
30060#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU)
30061#define GPT_CNT_COUNT_SHIFT (0U)
30062#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)
30063/*! @} */
30064
30065/*!
30066 * @}
30067 */ /* end of group GPT_Register_Masks */
30068
30069/* GPT - Peripheral instance base addresses */
30070/** Peripheral GPT1 base address */
30071#define GPT1_BASE (0x302D0000u)
30072/** Peripheral GPT1 base pointer */
30073#define GPT1 ((GPT_Type *)GPT1_BASE)
30074/** Peripheral GPT2 base address */
30075#define GPT2_BASE (0x302E0000u)
30076/** Peripheral GPT2 base pointer */
30077#define GPT2 ((GPT_Type *)GPT2_BASE)
30078/** Peripheral GPT3 base address */
30079#define GPT3_BASE (0x302F0000u)
30080/** Peripheral GPT3 base pointer */
30081#define GPT3 ((GPT_Type *)GPT3_BASE)
30082/** Peripheral GPT4 base address */
30083#define GPT4_BASE (0x30700000u)
30084/** Peripheral GPT4 base pointer */
30085#define GPT4 ((GPT_Type *)GPT4_BASE)
30086/** Peripheral GPT5 base address */
30087#define GPT5_BASE (0x306F0000u)
30088/** Peripheral GPT5 base pointer */
30089#define GPT5 ((GPT_Type *)GPT5_BASE)
30090/** Peripheral GPT6 base address */
30091#define GPT6_BASE (0x306E0000u)
30092/** Peripheral GPT6 base pointer */
30093#define GPT6 ((GPT_Type *)GPT6_BASE)
30094/** Array initializer of GPT peripheral base addresses */
30095#define GPT_BASE_ADDRS \
30096 { \
30097 0u, GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE, GPT5_BASE, GPT6_BASE \
30098 }
30099/** Array initializer of GPT peripheral base pointers */
30100#define GPT_BASE_PTRS \
30101 { \
30102 (GPT_Type *)0u, GPT1, GPT2, GPT3, GPT4, GPT5, GPT6 \
30103 }
30104/** Interrupt vectors for the GPT peripheral type */
30105#define GPT_IRQS \
30106 { \
30107 NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn, GPT3_IRQn, GPT4_IRQn, GPT5_IRQn, GPT6_IRQn \
30108 }
30109
30110/*!
30111 * @}
30112 */ /* end of group GPT_Peripheral_Access_Layer */
30113
30114/* ----------------------------------------------------------------------------
30115 -- I2C Peripheral Access Layer
30116 ---------------------------------------------------------------------------- */
30117
30118/*!
30119 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
30120 * @{
30121 */
30122
30123/** I2C - Register Layout Typedef */
30124typedef struct
30125{
30126 __IO uint16_t IADR; /**< I2C Address Register, offset: 0x0 */
30127 uint8_t RESERVED_0[2];
30128 __IO uint16_t IFDR; /**< I2C Frequency Divider Register, offset: 0x4 */
30129 uint8_t RESERVED_1[2];
30130 __IO uint16_t I2CR; /**< I2C Control Register, offset: 0x8 */
30131 uint8_t RESERVED_2[2];
30132 __IO uint16_t I2SR; /**< I2C Status Register, offset: 0xC */
30133 uint8_t RESERVED_3[2];
30134 __IO uint16_t I2DR; /**< I2C Data I/O Register, offset: 0x10 */
30135} I2C_Type;
30136
30137/* ----------------------------------------------------------------------------
30138 -- I2C Register Masks
30139 ---------------------------------------------------------------------------- */
30140
30141/*!
30142 * @addtogroup I2C_Register_Masks I2C Register Masks
30143 * @{
30144 */
30145
30146/*! @name IADR - I2C Address Register */
30147/*! @{ */
30148#define I2C_IADR_ADR_MASK (0xFEU)
30149#define I2C_IADR_ADR_SHIFT (1U)
30150#define I2C_IADR_ADR(x) (((uint16_t)(((uint16_t)(x)) << I2C_IADR_ADR_SHIFT)) & I2C_IADR_ADR_MASK)
30151/*! @} */
30152
30153/*! @name IFDR - I2C Frequency Divider Register */
30154/*! @{ */
30155#define I2C_IFDR_IC_MASK (0x3FU)
30156#define I2C_IFDR_IC_SHIFT (0U)
30157#define I2C_IFDR_IC(x) (((uint16_t)(((uint16_t)(x)) << I2C_IFDR_IC_SHIFT)) & I2C_IFDR_IC_MASK)
30158/*! @} */
30159
30160/*! @name I2CR - I2C Control Register */
30161/*! @{ */
30162#define I2C_I2CR_RSTA_MASK (0x4U)
30163#define I2C_I2CR_RSTA_SHIFT (2U)
30164/*! RSTA
30165 * 0b0..No repeat start
30166 * 0b1..Generates a Repeated Start condition
30167 */
30168#define I2C_I2CR_RSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_RSTA_SHIFT)) & I2C_I2CR_RSTA_MASK)
30169#define I2C_I2CR_TXAK_MASK (0x8U)
30170#define I2C_I2CR_TXAK_SHIFT (3U)
30171/*! TXAK
30172 * 0b0..An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data.
30173 * 0b1..No acknowledge signal response is sent (that is, the acknowledge bit = 1).
30174 */
30175#define I2C_I2CR_TXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_TXAK_SHIFT)) & I2C_I2CR_TXAK_MASK)
30176#define I2C_I2CR_MTX_MASK (0x10U)
30177#define I2C_I2CR_MTX_SHIFT (4U)
30178/*! MTX
30179 * 0b0..Receive.When a slave is addressed, the software should set MTX according to the slave read/write bit in
30180 * the I2C status register (I2C_I2SR[SRW]).
30181 * 0b1..Transmit.In Master mode, MTX should be set according to the type of transfer required. Therefore, for address
30182 * cycles, MTX is always 1.
30183 */
30184#define I2C_I2CR_MTX(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MTX_SHIFT)) & I2C_I2CR_MTX_MASK)
30185#define I2C_I2CR_MSTA_MASK (0x20U)
30186#define I2C_I2CR_MSTA_SHIFT (5U)
30187/*! MSTA
30188 * 0b0..Slave mode. Changing MSTA from 1 to 0 generates a Stop and selects Slave mode.
30189 * 0b1..Master mode. Changing MSTA from 0 to 1 signals a Start on the bus and selects Master mode.
30190 */
30191#define I2C_I2CR_MSTA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_MSTA_SHIFT)) & I2C_I2CR_MSTA_MASK)
30192#define I2C_I2CR_IIEN_MASK (0x40U)
30193#define I2C_I2CR_IIEN_SHIFT (6U)
30194/*! IIEN
30195 * 0b0..I2C interrupts are disabled, but the status flag I2C_I2SR[IIF] continues to be set when an Interrupt condition
30196 * occurs. 0b1..I2C interrupts are enabled. An I2C interrupt occurs if I2C_I2SR[IIF] is also set.
30197 */
30198#define I2C_I2CR_IIEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IIEN_SHIFT)) & I2C_I2CR_IIEN_MASK)
30199#define I2C_I2CR_IEN_MASK (0x80U)
30200#define I2C_I2CR_IEN_SHIFT (7U)
30201/*! IEN
30202 * 0b0..The block is disabled, but registers can still be accessed.
30203 * 0b1..The I2C is enabled. This bit must be set before any other I2C_I2CR bits have an effect.
30204 */
30205#define I2C_I2CR_IEN(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2CR_IEN_SHIFT)) & I2C_I2CR_IEN_MASK)
30206/*! @} */
30207
30208/*! @name I2SR - I2C Status Register */
30209/*! @{ */
30210#define I2C_I2SR_RXAK_MASK (0x1U)
30211#define I2C_I2SR_RXAK_SHIFT (0U)
30212/*! RXAK
30213 * 0b0..An "acknowledge" signal was received after the completion of an 8-bit data transmission on the bus.
30214 * 0b1..A "No acknowledge" signal was detected at the ninth clock.
30215 */
30216#define I2C_I2SR_RXAK(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_RXAK_SHIFT)) & I2C_I2SR_RXAK_MASK)
30217#define I2C_I2SR_IIF_MASK (0x2U)
30218#define I2C_I2SR_IIF_SHIFT (1U)
30219/*! IIF
30220 * 0b0..No I2C interrupt pending.
30221 * 0b1..An interrupt is pending.This causes a processor interrupt request (if the interrupt enable is asserted
30222 * [IIEN = 1]). The interrupt is set when one of the following occurs: One byte transfer is completed (the
30223 * interrupt is set at the falling edge of the ninth clock). An address is received that matches its own specific
30224 * address in Slave Receive mode. Arbitration is lost.
30225 */
30226#define I2C_I2SR_IIF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IIF_SHIFT)) & I2C_I2SR_IIF_MASK)
30227#define I2C_I2SR_SRW_MASK (0x4U)
30228#define I2C_I2SR_SRW_SHIFT (2U)
30229/*! SRW
30230 * 0b0..Slave receive, master writing to slave
30231 * 0b1..Slave transmit, master reading from slave
30232 */
30233#define I2C_I2SR_SRW(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_SRW_SHIFT)) & I2C_I2SR_SRW_MASK)
30234#define I2C_I2SR_IAL_MASK (0x10U)
30235#define I2C_I2SR_IAL_SHIFT (4U)
30236/*! IAL
30237 * 0b0..No arbitration lost.
30238 * 0b1..Arbitration is lost.
30239 */
30240#define I2C_I2SR_IAL(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAL_SHIFT)) & I2C_I2SR_IAL_MASK)
30241#define I2C_I2SR_IBB_MASK (0x20U)
30242#define I2C_I2SR_IBB_SHIFT (5U)
30243/*! IBB
30244 * 0b0..Bus is idle. If a Stop signal is detected, IBB is cleared.
30245 * 0b1..Bus is busy. When Start is detected, IBB is set.
30246 */
30247#define I2C_I2SR_IBB(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IBB_SHIFT)) & I2C_I2SR_IBB_MASK)
30248#define I2C_I2SR_IAAS_MASK (0x40U)
30249#define I2C_I2SR_IAAS_SHIFT (6U)
30250/*! IAAS
30251 * 0b0..Not addressed
30252 * 0b1..Addressed as a slave. Set when its own address (I2C_IADR) matches the calling address.
30253 */
30254#define I2C_I2SR_IAAS(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_IAAS_SHIFT)) & I2C_I2SR_IAAS_MASK)
30255#define I2C_I2SR_ICF_MASK (0x80U)
30256#define I2C_I2SR_ICF_SHIFT (7U)
30257/*! ICF
30258 * 0b0..Transfer is in progress.
30259 * 0b1..Transfer is complete. This bit is set by the falling edge of the ninth clock of the last byte transfer.
30260 */
30261#define I2C_I2SR_ICF(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2SR_ICF_SHIFT)) & I2C_I2SR_ICF_MASK)
30262/*! @} */
30263
30264/*! @name I2DR - I2C Data I/O Register */
30265/*! @{ */
30266#define I2C_I2DR_DATA_MASK (0xFFU)
30267#define I2C_I2DR_DATA_SHIFT (0U)
30268#define I2C_I2DR_DATA(x) (((uint16_t)(((uint16_t)(x)) << I2C_I2DR_DATA_SHIFT)) & I2C_I2DR_DATA_MASK)
30269/*! @} */
30270
30271/*!
30272 * @}
30273 */ /* end of group I2C_Register_Masks */
30274
30275/* I2C - Peripheral instance base addresses */
30276/** Peripheral I2C1 base address */
30277#define I2C1_BASE (0x30A20000u)
30278/** Peripheral I2C1 base pointer */
30279#define I2C1 ((I2C_Type *)I2C1_BASE)
30280/** Peripheral I2C2 base address */
30281#define I2C2_BASE (0x30A30000u)
30282/** Peripheral I2C2 base pointer */
30283#define I2C2 ((I2C_Type *)I2C2_BASE)
30284/** Peripheral I2C3 base address */
30285#define I2C3_BASE (0x30A40000u)
30286/** Peripheral I2C3 base pointer */
30287#define I2C3 ((I2C_Type *)I2C3_BASE)
30288/** Peripheral I2C4 base address */
30289#define I2C4_BASE (0x30A50000u)
30290/** Peripheral I2C4 base pointer */
30291#define I2C4 ((I2C_Type *)I2C4_BASE)
30292/** Array initializer of I2C peripheral base addresses */
30293#define I2C_BASE_ADDRS \
30294 { \
30295 0u, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE \
30296 }
30297/** Array initializer of I2C peripheral base pointers */
30298#define I2C_BASE_PTRS \
30299 { \
30300 (I2C_Type *)0u, I2C1, I2C2, I2C3, I2C4 \
30301 }
30302/** Interrupt vectors for the I2C peripheral type */
30303#define I2C_IRQS \
30304 { \
30305 NotAvail_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn, I2C4_IRQn \
30306 }
30307
30308/*!
30309 * @}
30310 */ /* end of group I2C_Peripheral_Access_Layer */
30311
30312/* ----------------------------------------------------------------------------
30313 -- I2S Peripheral Access Layer
30314 ---------------------------------------------------------------------------- */
30315
30316/*!
30317 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
30318 * @{
30319 */
30320
30321/** I2S - Register Layout Typedef */
30322typedef struct
30323{
30324 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
30325 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
30326 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x8 */
30327 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0xC */
30328 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x10 */
30329 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0x14 */
30330 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x18 */
30331 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x1C */
30332 __O uint32_t TDR[8]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
30333 __I uint32_t TFR[8]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
30334 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
30335 uint8_t RESERVED_0[12];
30336 __IO uint32_t TTCR; /**< SAI Transmit Timestamp Control Register, offset: 0x70 */
30337 __I uint32_t TTSR; /**< SAI Transmit Timestamp Register, offset: 0x74 */
30338 __I uint32_t TBCR; /**< SAI Transmit Bit Count Register, offset: 0x78 */
30339 __I uint32_t TBCTR; /**< SAI Transmit Bit Count Timestamp Register, offset: 0x7C */
30340 uint8_t RESERVED_1[8];
30341 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x88 */
30342 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x8C */
30343 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x90 */
30344 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x94 */
30345 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x98 */
30346 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x9C */
30347 __I uint32_t RDR[8]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
30348 __I uint32_t RFR[8]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
30349 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
30350 uint8_t RESERVED_2[12];
30351 __IO uint32_t RTCR; /**< SAI Receive Timestamp Control Register, offset: 0xF0 */
30352 __I uint32_t RTSR; /**< SAI Receive Timestamp Register, offset: 0xF4 */
30353 __I uint32_t RBCR; /**< SAI Receive Bit Count Register, offset: 0xF8 */
30354 __I uint32_t RBCTR; /**< SAI Receive Bit Count Timestamp Register, offset: 0xFC */
30355 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
30356} I2S_Type;
30357
30358/* ----------------------------------------------------------------------------
30359 -- I2S Register Masks
30360 ---------------------------------------------------------------------------- */
30361
30362/*!
30363 * @addtogroup I2S_Register_Masks I2S Register Masks
30364 * @{
30365 */
30366
30367/*! @name VERID - Version ID Register */
30368/*! @{ */
30369#define I2S_VERID_FEATURE_MASK (0xFFFFU)
30370#define I2S_VERID_FEATURE_SHIFT (0U)
30371/*! FEATURE - Feature Specification Number
30372 * 0b0000000000000000..Standard feature set.
30373 * 0b0000000000000010..Standard feature set with Timestamp Registers.
30374 */
30375#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
30376#define I2S_VERID_MINOR_MASK (0xFF0000U)
30377#define I2S_VERID_MINOR_SHIFT (16U)
30378#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
30379#define I2S_VERID_MAJOR_MASK (0xFF000000U)
30380#define I2S_VERID_MAJOR_SHIFT (24U)
30381#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
30382/*! @} */
30383
30384/*! @name PARAM - Parameter Register */
30385/*! @{ */
30386#define I2S_PARAM_DATALINE_MASK (0xFU)
30387#define I2S_PARAM_DATALINE_SHIFT (0U)
30388#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
30389#define I2S_PARAM_FIFO_MASK (0xF00U)
30390#define I2S_PARAM_FIFO_SHIFT (8U)
30391#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
30392#define I2S_PARAM_FRAME_MASK (0xF0000U)
30393#define I2S_PARAM_FRAME_SHIFT (16U)
30394#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
30395/*! @} */
30396
30397/*! @name TCSR - SAI Transmit Control Register */
30398/*! @{ */
30399#define I2S_TCSR_FRDE_MASK (0x1U)
30400#define I2S_TCSR_FRDE_SHIFT (0U)
30401/*! FRDE - FIFO Request DMA Enable
30402 * 0b0..Disables the DMA request.
30403 * 0b1..Enables the DMA request.
30404 */
30405#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
30406#define I2S_TCSR_FWDE_MASK (0x2U)
30407#define I2S_TCSR_FWDE_SHIFT (1U)
30408/*! FWDE - FIFO Warning DMA Enable
30409 * 0b0..Disables the DMA request.
30410 * 0b1..Enables the DMA request.
30411 */
30412#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
30413#define I2S_TCSR_FRIE_MASK (0x100U)
30414#define I2S_TCSR_FRIE_SHIFT (8U)
30415/*! FRIE - FIFO Request Interrupt Enable
30416 * 0b0..Disables the interrupt.
30417 * 0b1..Enables the interrupt.
30418 */
30419#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
30420#define I2S_TCSR_FWIE_MASK (0x200U)
30421#define I2S_TCSR_FWIE_SHIFT (9U)
30422/*! FWIE - FIFO Warning Interrupt Enable
30423 * 0b0..Disables the interrupt.
30424 * 0b1..Enables the interrupt.
30425 */
30426#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
30427#define I2S_TCSR_FEIE_MASK (0x400U)
30428#define I2S_TCSR_FEIE_SHIFT (10U)
30429/*! FEIE - FIFO Error Interrupt Enable
30430 * 0b0..Disables the interrupt.
30431 * 0b1..Enables the interrupt.
30432 */
30433#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
30434#define I2S_TCSR_SEIE_MASK (0x800U)
30435#define I2S_TCSR_SEIE_SHIFT (11U)
30436/*! SEIE - Sync Error Interrupt Enable
30437 * 0b0..Disables interrupt.
30438 * 0b1..Enables interrupt.
30439 */
30440#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
30441#define I2S_TCSR_WSIE_MASK (0x1000U)
30442#define I2S_TCSR_WSIE_SHIFT (12U)
30443/*! WSIE - Word Start Interrupt Enable
30444 * 0b0..Disables interrupt.
30445 * 0b1..Enables interrupt.
30446 */
30447#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
30448#define I2S_TCSR_FRF_MASK (0x10000U)
30449#define I2S_TCSR_FRF_SHIFT (16U)
30450/*! FRF - FIFO Request Flag
30451 * 0b0..Transmit FIFO watermark has not been reached.
30452 * 0b1..Transmit FIFO watermark has been reached.
30453 */
30454#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
30455#define I2S_TCSR_FWF_MASK (0x20000U)
30456#define I2S_TCSR_FWF_SHIFT (17U)
30457/*! FWF - FIFO Warning Flag
30458 * 0b0..No enabled transmit FIFO is empty.
30459 * 0b1..Enabled transmit FIFO is empty.
30460 */
30461#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
30462#define I2S_TCSR_FEF_MASK (0x40000U)
30463#define I2S_TCSR_FEF_SHIFT (18U)
30464/*! FEF - FIFO Error Flag
30465 * 0b0..Transmit underrun not detected.
30466 * 0b1..Transmit underrun detected.
30467 */
30468#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
30469#define I2S_TCSR_SEF_MASK (0x80000U)
30470#define I2S_TCSR_SEF_SHIFT (19U)
30471/*! SEF - Sync Error Flag
30472 * 0b0..Sync error not detected.
30473 * 0b1..Frame sync error detected.
30474 */
30475#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
30476#define I2S_TCSR_WSF_MASK (0x100000U)
30477#define I2S_TCSR_WSF_SHIFT (20U)
30478/*! WSF - Word Start Flag
30479 * 0b0..Start of word not detected.
30480 * 0b1..Start of word detected.
30481 */
30482#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
30483#define I2S_TCSR_SR_MASK (0x1000000U)
30484#define I2S_TCSR_SR_SHIFT (24U)
30485/*! SR - Software Reset
30486 * 0b0..No effect.
30487 * 0b1..Software reset.
30488 */
30489#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
30490#define I2S_TCSR_FR_MASK (0x2000000U)
30491#define I2S_TCSR_FR_SHIFT (25U)
30492/*! FR - FIFO Reset
30493 * 0b0..No effect.
30494 * 0b1..FIFO reset.
30495 */
30496#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
30497#define I2S_TCSR_BCE_MASK (0x10000000U)
30498#define I2S_TCSR_BCE_SHIFT (28U)
30499/*! BCE - Bit Clock Enable
30500 * 0b0..Transmit bit clock is disabled.
30501 * 0b1..Transmit bit clock is enabled.
30502 */
30503#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
30504#define I2S_TCSR_DBGE_MASK (0x20000000U)
30505#define I2S_TCSR_DBGE_SHIFT (29U)
30506/*! DBGE - Debug Enable
30507 * 0b0..Transmitter is disabled in Debug mode, after completing the current frame.
30508 * 0b1..Transmitter is enabled in Debug mode.
30509 */
30510#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
30511#define I2S_TCSR_TE_MASK (0x80000000U)
30512#define I2S_TCSR_TE_SHIFT (31U)
30513/*! TE - Transmitter Enable
30514 * 0b0..Transmitter is disabled.
30515 * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
30516 */
30517#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
30518/*! @} */
30519
30520/*! @name TCR1 - SAI Transmit Configuration 1 Register */
30521/*! @{ */
30522#define I2S_TCR1_TFW_MASK (0x7FU)
30523#define I2S_TCR1_TFW_SHIFT (0U)
30524#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
30525/*! @} */
30526
30527/*! @name TCR2 - SAI Transmit Configuration 2 Register */
30528/*! @{ */
30529#define I2S_TCR2_DIV_MASK (0xFFU)
30530#define I2S_TCR2_DIV_SHIFT (0U)
30531#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
30532#define I2S_TCR2_BYP_MASK (0x800000U)
30533#define I2S_TCR2_BYP_SHIFT (23U)
30534/*! BYP - Bit Clock Bypass
30535 * 0b0..Internal bit clock is generated from bit clock divider.
30536 * 0b1..Internal bit clock is divide by one of the audio master clock.
30537 */
30538#define I2S_TCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK)
30539#define I2S_TCR2_BCD_MASK (0x1000000U)
30540#define I2S_TCR2_BCD_SHIFT (24U)
30541/*! BCD - Bit Clock Direction
30542 * 0b0..Bit clock is generated externally in Slave mode.
30543 * 0b1..Bit clock is generated internally in Master mode.
30544 */
30545#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
30546#define I2S_TCR2_BCP_MASK (0x2000000U)
30547#define I2S_TCR2_BCP_SHIFT (25U)
30548/*! BCP - Bit Clock Polarity
30549 * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
30550 * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
30551 */
30552#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
30553#define I2S_TCR2_MSEL_MASK (0xC000000U)
30554#define I2S_TCR2_MSEL_SHIFT (26U)
30555/*! MSEL - MCLK Select
30556 * 0b00..Bus Clock selected.
30557 * 0b01..Master Clock (MCLK) 1 option selected.
30558 * 0b10..Master Clock (MCLK) 2 option selected.
30559 * 0b11..Master Clock (MCLK) 3 option selected.
30560 */
30561#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
30562#define I2S_TCR2_BCI_MASK (0x10000000U)
30563#define I2S_TCR2_BCI_SHIFT (28U)
30564/*! BCI - Bit Clock Input
30565 * 0b0..No effect.
30566 * 0b1..Internal logic is clocked as if bit clock was externally generated.
30567 */
30568#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
30569#define I2S_TCR2_BCS_MASK (0x20000000U)
30570#define I2S_TCR2_BCS_SHIFT (29U)
30571/*! BCS - Bit Clock Swap
30572 * 0b0..Use the normal bit clock source.
30573 * 0b1..Swap the bit clock source.
30574 */
30575#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
30576#define I2S_TCR2_SYNC_MASK (0xC0000000U)
30577#define I2S_TCR2_SYNC_SHIFT (30U)
30578/*! SYNC - Synchronous Mode
30579 * 0b00..Asynchronous mode.
30580 * 0b01..Synchronous with receiver.
30581 * 0b10..Reserved.
30582 * 0b11..Reserved.
30583 */
30584#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
30585/*! @} */
30586
30587/*! @name TCR3 - SAI Transmit Configuration 3 Register */
30588/*! @{ */
30589#define I2S_TCR3_WDFL_MASK (0x1FU)
30590#define I2S_TCR3_WDFL_SHIFT (0U)
30591#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
30592#define I2S_TCR3_TCE_MASK (0xFF0000U)
30593#define I2S_TCR3_TCE_SHIFT (16U)
30594#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
30595#define I2S_TCR3_CFR_MASK (0xFF000000U)
30596#define I2S_TCR3_CFR_SHIFT (24U)
30597#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
30598/*! @} */
30599
30600/*! @name TCR4 - SAI Transmit Configuration 4 Register */
30601/*! @{ */
30602#define I2S_TCR4_FSD_MASK (0x1U)
30603#define I2S_TCR4_FSD_SHIFT (0U)
30604/*! FSD - Frame Sync Direction
30605 * 0b0..Frame sync is generated externally in Slave mode.
30606 * 0b1..Frame sync is generated internally in Master mode.
30607 */
30608#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
30609#define I2S_TCR4_FSP_MASK (0x2U)
30610#define I2S_TCR4_FSP_SHIFT (1U)
30611/*! FSP - Frame Sync Polarity
30612 * 0b0..Frame sync is active high.
30613 * 0b1..Frame sync is active low.
30614 */
30615#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
30616#define I2S_TCR4_ONDEM_MASK (0x4U)
30617#define I2S_TCR4_ONDEM_SHIFT (2U)
30618/*! ONDEM - On Demand Mode
30619 * 0b0..Internal frame sync is generated continuously.
30620 * 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
30621 */
30622#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
30623#define I2S_TCR4_FSE_MASK (0x8U)
30624#define I2S_TCR4_FSE_SHIFT (3U)
30625/*! FSE - Frame Sync Early
30626 * 0b0..Frame sync asserts with the first bit of the frame.
30627 * 0b1..Frame sync asserts one bit before the first bit of the frame.
30628 */
30629#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
30630#define I2S_TCR4_MF_MASK (0x10U)
30631#define I2S_TCR4_MF_SHIFT (4U)
30632/*! MF - MSB First
30633 * 0b0..LSB is transmitted first.
30634 * 0b1..MSB is transmitted first.
30635 */
30636#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
30637#define I2S_TCR4_CHMOD_MASK (0x20U)
30638#define I2S_TCR4_CHMOD_SHIFT (5U)
30639/*! CHMOD - Channel Mode
30640 * 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled.
30641 * 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are
30642 * disabled.
30643 */
30644#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
30645#define I2S_TCR4_SYWD_MASK (0x1F00U)
30646#define I2S_TCR4_SYWD_SHIFT (8U)
30647#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
30648#define I2S_TCR4_FRSZ_MASK (0x1F0000U)
30649#define I2S_TCR4_FRSZ_SHIFT (16U)
30650#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
30651#define I2S_TCR4_FPACK_MASK (0x3000000U)
30652#define I2S_TCR4_FPACK_SHIFT (24U)
30653/*! FPACK - FIFO Packing Mode
30654 * 0b00..FIFO packing is disabled
30655 * 0b01..Reserved
30656 * 0b10..8-bit FIFO packing is enabled
30657 * 0b11..16-bit FIFO packing is enabled
30658 */
30659#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
30660#define I2S_TCR4_FCOMB_MASK (0xC000000U)
30661#define I2S_TCR4_FCOMB_SHIFT (26U)
30662/*! FCOMB - FIFO Combine Mode
30663 * 0b00..FIFO combine mode disabled.
30664 * 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers).
30665 * 0b10..FIFO combine mode enabled on FIFO writes (by software).
30666 * 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
30667 */
30668#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
30669#define I2S_TCR4_FCONT_MASK (0x10000000U)
30670#define I2S_TCR4_FCONT_SHIFT (28U)
30671/*! FCONT - FIFO Continue on Error
30672 * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been
30673 * cleared. 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the
30674 * FIFO warning flag has been cleared.
30675 */
30676#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
30677/*! @} */
30678
30679/*! @name TCR5 - SAI Transmit Configuration 5 Register */
30680/*! @{ */
30681#define I2S_TCR5_FBT_MASK (0x1F00U)
30682#define I2S_TCR5_FBT_SHIFT (8U)
30683#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
30684#define I2S_TCR5_W0W_MASK (0x1F0000U)
30685#define I2S_TCR5_W0W_SHIFT (16U)
30686#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
30687#define I2S_TCR5_WNW_MASK (0x1F000000U)
30688#define I2S_TCR5_WNW_SHIFT (24U)
30689#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
30690/*! @} */
30691
30692/*! @name TDR - SAI Transmit Data Register */
30693/*! @{ */
30694#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
30695#define I2S_TDR_TDR_SHIFT (0U)
30696#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
30697/*! @} */
30698
30699/* The count of I2S_TDR */
30700#define I2S_TDR_COUNT (8U)
30701
30702/*! @name TFR - SAI Transmit FIFO Register */
30703/*! @{ */
30704#define I2S_TFR_RFP_MASK (0xFFU)
30705#define I2S_TFR_RFP_SHIFT (0U)
30706#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
30707#define I2S_TFR_WFP_MASK (0xFF0000U)
30708#define I2S_TFR_WFP_SHIFT (16U)
30709#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
30710#define I2S_TFR_WCP_MASK (0x80000000U)
30711#define I2S_TFR_WCP_SHIFT (31U)
30712/*! WCP - Write Channel Pointer
30713 * 0b0..No effect.
30714 * 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
30715 */
30716#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
30717/*! @} */
30718
30719/* The count of I2S_TFR */
30720#define I2S_TFR_COUNT (8U)
30721
30722/*! @name TMR - SAI Transmit Mask Register */
30723/*! @{ */
30724#define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
30725#define I2S_TMR_TWM_SHIFT (0U)
30726/*! TWM - Transmit Word Mask
30727 * 0b00000000000000000000000000000000..Word N is enabled.
30728 * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when
30729 * masked.
30730 */
30731#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
30732/*! @} */
30733
30734/*! @name TTCR - SAI Transmit Timestamp Control Register */
30735/*! @{ */
30736#define I2S_TTCR_TSEN_MASK (0x1U)
30737#define I2S_TTCR_TSEN_SHIFT (0U)
30738/*! TSEN - Timestamp Enable
30739 * 0b0..Timestamp counter is disabled.
30740 * 0b1..Timestamp counter is enabled.
30741 */
30742#define I2S_TTCR_TSEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSEN_SHIFT)) & I2S_TTCR_TSEN_MASK)
30743#define I2S_TTCR_TSINC_MASK (0x2U)
30744#define I2S_TTCR_TSINC_SHIFT (1U)
30745/*! TSINC - Timestamp Increment
30746 * 0b0..Timestamp counter starts to increment when enabled and the bit counter has incremented.
30747 * 0b1..Timestamp counter starts to increment when enabled.
30748 */
30749#define I2S_TTCR_TSINC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_TSINC_SHIFT)) & I2S_TTCR_TSINC_MASK)
30750#define I2S_TTCR_RTSC_MASK (0x100U)
30751#define I2S_TTCR_RTSC_SHIFT (8U)
30752/*! RTSC - Reset Timestamp Counter
30753 * 0b0..Timestamp counter is not reset.
30754 * 0b1..Timestamp counter is reset.
30755 */
30756#define I2S_TTCR_RTSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_RTSC_SHIFT)) & I2S_TTCR_RTSC_MASK)
30757#define I2S_TTCR_RBC_MASK (0x200U)
30758#define I2S_TTCR_RBC_SHIFT (9U)
30759/*! RBC - Reset Bit Counter
30760 * 0b0..Bit counter is not reset.
30761 * 0b1..Bit counter is reset.
30762 */
30763#define I2S_TTCR_RBC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTCR_RBC_SHIFT)) & I2S_TTCR_RBC_MASK)
30764/*! @} */
30765
30766/*! @name TTSR - SAI Transmit Timestamp Register */
30767/*! @{ */
30768#define I2S_TTSR_TSC_MASK (0xFFFFFFFFU)
30769#define I2S_TTSR_TSC_SHIFT (0U)
30770#define I2S_TTSR_TSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TTSR_TSC_SHIFT)) & I2S_TTSR_TSC_MASK)
30771/*! @} */
30772
30773/*! @name TBCR - SAI Transmit Bit Count Register */
30774/*! @{ */
30775#define I2S_TBCR_BCNT_MASK (0xFFFFFFFFU)
30776#define I2S_TBCR_BCNT_SHIFT (0U)
30777#define I2S_TBCR_BCNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TBCR_BCNT_SHIFT)) & I2S_TBCR_BCNT_MASK)
30778/*! @} */
30779
30780/*! @name TBCTR - SAI Transmit Bit Count Timestamp Register */
30781/*! @{ */
30782#define I2S_TBCTR_BCTS_MASK (0xFFFFFFFFU)
30783#define I2S_TBCTR_BCTS_SHIFT (0U)
30784#define I2S_TBCTR_BCTS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TBCTR_BCTS_SHIFT)) & I2S_TBCTR_BCTS_MASK)
30785/*! @} */
30786
30787/*! @name RCSR - SAI Receive Control Register */
30788/*! @{ */
30789#define I2S_RCSR_FRDE_MASK (0x1U)
30790#define I2S_RCSR_FRDE_SHIFT (0U)
30791/*! FRDE - FIFO Request DMA Enable
30792 * 0b0..Disables the DMA request.
30793 * 0b1..Enables the DMA request.
30794 */
30795#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
30796#define I2S_RCSR_FWDE_MASK (0x2U)
30797#define I2S_RCSR_FWDE_SHIFT (1U)
30798/*! FWDE - FIFO Warning DMA Enable
30799 * 0b0..Disables the DMA request.
30800 * 0b1..Enables the DMA request.
30801 */
30802#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
30803#define I2S_RCSR_FRIE_MASK (0x100U)
30804#define I2S_RCSR_FRIE_SHIFT (8U)
30805/*! FRIE - FIFO Request Interrupt Enable
30806 * 0b0..Disables the interrupt.
30807 * 0b1..Enables the interrupt.
30808 */
30809#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
30810#define I2S_RCSR_FWIE_MASK (0x200U)
30811#define I2S_RCSR_FWIE_SHIFT (9U)
30812/*! FWIE - FIFO Warning Interrupt Enable
30813 * 0b0..Disables the interrupt.
30814 * 0b1..Enables the interrupt.
30815 */
30816#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
30817#define I2S_RCSR_FEIE_MASK (0x400U)
30818#define I2S_RCSR_FEIE_SHIFT (10U)
30819/*! FEIE - FIFO Error Interrupt Enable
30820 * 0b0..Disables the interrupt.
30821 * 0b1..Enables the interrupt.
30822 */
30823#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
30824#define I2S_RCSR_SEIE_MASK (0x800U)
30825#define I2S_RCSR_SEIE_SHIFT (11U)
30826/*! SEIE - Sync Error Interrupt Enable
30827 * 0b0..Disables interrupt.
30828 * 0b1..Enables interrupt.
30829 */
30830#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
30831#define I2S_RCSR_WSIE_MASK (0x1000U)
30832#define I2S_RCSR_WSIE_SHIFT (12U)
30833/*! WSIE - Word Start Interrupt Enable
30834 * 0b0..Disables interrupt.
30835 * 0b1..Enables interrupt.
30836 */
30837#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
30838#define I2S_RCSR_FRF_MASK (0x10000U)
30839#define I2S_RCSR_FRF_SHIFT (16U)
30840/*! FRF - FIFO Request Flag
30841 * 0b0..Receive FIFO watermark not reached.
30842 * 0b1..Receive FIFO watermark has been reached.
30843 */
30844#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
30845#define I2S_RCSR_FWF_MASK (0x20000U)
30846#define I2S_RCSR_FWF_SHIFT (17U)
30847/*! FWF - FIFO Warning Flag
30848 * 0b0..No enabled receive FIFO is full.
30849 * 0b1..Enabled receive FIFO is full.
30850 */
30851#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
30852#define I2S_RCSR_FEF_MASK (0x40000U)
30853#define I2S_RCSR_FEF_SHIFT (18U)
30854/*! FEF - FIFO Error Flag
30855 * 0b0..Receive overflow not detected.
30856 * 0b1..Receive overflow detected.
30857 */
30858#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
30859#define I2S_RCSR_SEF_MASK (0x80000U)
30860#define I2S_RCSR_SEF_SHIFT (19U)
30861/*! SEF - Sync Error Flag
30862 * 0b0..Sync error not detected.
30863 * 0b1..Frame sync error detected.
30864 */
30865#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
30866#define I2S_RCSR_WSF_MASK (0x100000U)
30867#define I2S_RCSR_WSF_SHIFT (20U)
30868/*! WSF - Word Start Flag
30869 * 0b0..Start of word not detected.
30870 * 0b1..Start of word detected.
30871 */
30872#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
30873#define I2S_RCSR_SR_MASK (0x1000000U)
30874#define I2S_RCSR_SR_SHIFT (24U)
30875/*! SR - Software Reset
30876 * 0b0..No effect.
30877 * 0b1..Software reset.
30878 */
30879#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
30880#define I2S_RCSR_FR_MASK (0x2000000U)
30881#define I2S_RCSR_FR_SHIFT (25U)
30882/*! FR - FIFO Reset
30883 * 0b0..No effect.
30884 * 0b1..FIFO reset.
30885 */
30886#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
30887#define I2S_RCSR_BCE_MASK (0x10000000U)
30888#define I2S_RCSR_BCE_SHIFT (28U)
30889/*! BCE - Bit Clock Enable
30890 * 0b0..Receive bit clock is disabled.
30891 * 0b1..Receive bit clock is enabled.
30892 */
30893#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
30894#define I2S_RCSR_DBGE_MASK (0x20000000U)
30895#define I2S_RCSR_DBGE_SHIFT (29U)
30896/*! DBGE - Debug Enable
30897 * 0b0..Receiver is disabled in Debug mode, after completing the current frame.
30898 * 0b1..Receiver is enabled in Debug mode.
30899 */
30900#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
30901#define I2S_RCSR_RE_MASK (0x80000000U)
30902#define I2S_RCSR_RE_SHIFT (31U)
30903/*! RE - Receiver Enable
30904 * 0b0..Receiver is disabled.
30905 * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
30906 */
30907#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
30908/*! @} */
30909
30910/*! @name RCR1 - SAI Receive Configuration 1 Register */
30911/*! @{ */
30912#define I2S_RCR1_RFW_MASK (0x7FU)
30913#define I2S_RCR1_RFW_SHIFT (0U)
30914#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
30915/*! @} */
30916
30917/*! @name RCR2 - SAI Receive Configuration 2 Register */
30918/*! @{ */
30919#define I2S_RCR2_DIV_MASK (0xFFU)
30920#define I2S_RCR2_DIV_SHIFT (0U)
30921#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
30922#define I2S_RCR2_BYP_MASK (0x800000U)
30923#define I2S_RCR2_BYP_SHIFT (23U)
30924/*! BYP - Bit Clock Bypass
30925 * 0b0..Internal bit clock is generated from bit clock divider.
30926 * 0b1..Internal bit clock is divide by one of the audio master clock.
30927 */
30928#define I2S_RCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK)
30929#define I2S_RCR2_BCD_MASK (0x1000000U)
30930#define I2S_RCR2_BCD_SHIFT (24U)
30931/*! BCD - Bit Clock Direction
30932 * 0b0..Bit clock is generated externally in Slave mode.
30933 * 0b1..Bit clock is generated internally in Master mode.
30934 */
30935#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
30936#define I2S_RCR2_BCP_MASK (0x2000000U)
30937#define I2S_RCR2_BCP_SHIFT (25U)
30938/*! BCP - Bit Clock Polarity
30939 * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
30940 * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
30941 */
30942#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
30943#define I2S_RCR2_MSEL_MASK (0xC000000U)
30944#define I2S_RCR2_MSEL_SHIFT (26U)
30945/*! MSEL - MCLK Select
30946 * 0b00..Bus Clock selected.
30947 * 0b01..Master Clock (MCLK) 1 option selected.
30948 * 0b10..Master Clock (MCLK) 2 option selected.
30949 * 0b11..Master Clock (MCLK) 3 option selected.
30950 */
30951#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
30952#define I2S_RCR2_BCI_MASK (0x10000000U)
30953#define I2S_RCR2_BCI_SHIFT (28U)
30954/*! BCI - Bit Clock Input
30955 * 0b0..No effect.
30956 * 0b1..Internal logic is clocked as if bit clock was externally generated.
30957 */
30958#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
30959#define I2S_RCR2_BCS_MASK (0x20000000U)
30960#define I2S_RCR2_BCS_SHIFT (29U)
30961/*! BCS - Bit Clock Swap
30962 * 0b0..Use the normal bit clock source.
30963 * 0b1..Swap the bit clock source.
30964 */
30965#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
30966#define I2S_RCR2_SYNC_MASK (0xC0000000U)
30967#define I2S_RCR2_SYNC_SHIFT (30U)
30968/*! SYNC - Synchronous Mode
30969 * 0b00..Asynchronous mode.
30970 * 0b01..Synchronous with transmitter.
30971 * 0b10..Reserved.
30972 * 0b11..Reserved.
30973 */
30974#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
30975/*! @} */
30976
30977/*! @name RCR3 - SAI Receive Configuration 3 Register */
30978/*! @{ */
30979#define I2S_RCR3_WDFL_MASK (0x1FU)
30980#define I2S_RCR3_WDFL_SHIFT (0U)
30981#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
30982#define I2S_RCR3_RCE_MASK (0xFF0000U)
30983#define I2S_RCR3_RCE_SHIFT (16U)
30984#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
30985#define I2S_RCR3_CFR_MASK (0xFF000000U)
30986#define I2S_RCR3_CFR_SHIFT (24U)
30987#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
30988/*! @} */
30989
30990/*! @name RCR4 - SAI Receive Configuration 4 Register */
30991/*! @{ */
30992#define I2S_RCR4_FSD_MASK (0x1U)
30993#define I2S_RCR4_FSD_SHIFT (0U)
30994/*! FSD - Frame Sync Direction
30995 * 0b0..Frame Sync is generated externally in Slave mode.
30996 * 0b1..Frame Sync is generated internally in Master mode.
30997 */
30998#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
30999#define I2S_RCR4_FSP_MASK (0x2U)
31000#define I2S_RCR4_FSP_SHIFT (1U)
31001/*! FSP - Frame Sync Polarity
31002 * 0b0..Frame sync is active high.
31003 * 0b1..Frame sync is active low.
31004 */
31005#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
31006#define I2S_RCR4_ONDEM_MASK (0x4U)
31007#define I2S_RCR4_ONDEM_SHIFT (2U)
31008/*! ONDEM - On Demand Mode
31009 * 0b0..Internal frame sync is generated continuously.
31010 * 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
31011 */
31012#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
31013#define I2S_RCR4_FSE_MASK (0x8U)
31014#define I2S_RCR4_FSE_SHIFT (3U)
31015/*! FSE - Frame Sync Early
31016 * 0b0..Frame sync asserts with the first bit of the frame.
31017 * 0b1..Frame sync asserts one bit before the first bit of the frame.
31018 */
31019#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
31020#define I2S_RCR4_MF_MASK (0x10U)
31021#define I2S_RCR4_MF_SHIFT (4U)
31022/*! MF - MSB First
31023 * 0b0..LSB is received first.
31024 * 0b1..MSB is received first.
31025 */
31026#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
31027#define I2S_RCR4_SYWD_MASK (0x1F00U)
31028#define I2S_RCR4_SYWD_SHIFT (8U)
31029#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
31030#define I2S_RCR4_FRSZ_MASK (0x1F0000U)
31031#define I2S_RCR4_FRSZ_SHIFT (16U)
31032#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
31033#define I2S_RCR4_FPACK_MASK (0x3000000U)
31034#define I2S_RCR4_FPACK_SHIFT (24U)
31035/*! FPACK - FIFO Packing Mode
31036 * 0b00..FIFO packing is disabled
31037 * 0b01..Reserved.
31038 * 0b10..8-bit FIFO packing is enabled
31039 * 0b11..16-bit FIFO packing is enabled
31040 */
31041#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
31042#define I2S_RCR4_FCOMB_MASK (0xC000000U)
31043#define I2S_RCR4_FCOMB_SHIFT (26U)
31044/*! FCOMB - FIFO Combine Mode
31045 * 0b00..FIFO combine mode disabled.
31046 * 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers).
31047 * 0b10..FIFO combine mode enabled on FIFO reads (by software).
31048 * 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
31049 */
31050#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
31051#define I2S_RCR4_FCONT_MASK (0x10000000U)
31052#define I2S_RCR4_FCONT_SHIFT (28U)
31053/*! FCONT - FIFO Continue on Error
31054 * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been
31055 * cleared. 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the
31056 * FIFO warning flag has been cleared.
31057 */
31058#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
31059/*! @} */
31060
31061/*! @name RCR5 - SAI Receive Configuration 5 Register */
31062/*! @{ */
31063#define I2S_RCR5_FBT_MASK (0x1F00U)
31064#define I2S_RCR5_FBT_SHIFT (8U)
31065#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
31066#define I2S_RCR5_W0W_MASK (0x1F0000U)
31067#define I2S_RCR5_W0W_SHIFT (16U)
31068#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
31069#define I2S_RCR5_WNW_MASK (0x1F000000U)
31070#define I2S_RCR5_WNW_SHIFT (24U)
31071#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
31072/*! @} */
31073
31074/*! @name RDR - SAI Receive Data Register */
31075/*! @{ */
31076#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
31077#define I2S_RDR_RDR_SHIFT (0U)
31078#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
31079/*! @} */
31080
31081/* The count of I2S_RDR */
31082#define I2S_RDR_COUNT (8U)
31083
31084/*! @name RFR - SAI Receive FIFO Register */
31085/*! @{ */
31086#define I2S_RFR_RFP_MASK (0xFFU)
31087#define I2S_RFR_RFP_SHIFT (0U)
31088#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
31089#define I2S_RFR_RCP_MASK (0x8000U)
31090#define I2S_RFR_RCP_SHIFT (15U)
31091/*! RCP - Receive Channel Pointer
31092 * 0b0..No effect.
31093 * 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
31094 */
31095#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
31096#define I2S_RFR_WFP_MASK (0xFF0000U)
31097#define I2S_RFR_WFP_SHIFT (16U)
31098#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
31099/*! @} */
31100
31101/* The count of I2S_RFR */
31102#define I2S_RFR_COUNT (8U)
31103
31104/*! @name RMR - SAI Receive Mask Register */
31105/*! @{ */
31106#define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
31107#define I2S_RMR_RWM_SHIFT (0U)
31108/*! RWM - Receive Word Mask
31109 * 0b00000000000000000000000000000000..Word N is enabled.
31110 * 0b00000000000000000000000000000001..Word N is masked.
31111 */
31112#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
31113/*! @} */
31114
31115/*! @name RTCR - SAI Receive Timestamp Control Register */
31116/*! @{ */
31117#define I2S_RTCR_TSEN_MASK (0x1U)
31118#define I2S_RTCR_TSEN_SHIFT (0U)
31119/*! TSEN - Timestamp Enable
31120 * 0b0..Timestamp counter is disabled.
31121 * 0b1..Timestamp counter is enabled.
31122 */
31123#define I2S_RTCR_TSEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSEN_SHIFT)) & I2S_RTCR_TSEN_MASK)
31124#define I2S_RTCR_TSINC_MASK (0x2U)
31125#define I2S_RTCR_TSINC_SHIFT (1U)
31126/*! TSINC - Timestamp Increment
31127 * 0b0..Timestamp counter starts to increment when enabled and the bit counter has incremented.
31128 * 0b1..Timestamp counter starts to increment when enabled.
31129 */
31130#define I2S_RTCR_TSINC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_TSINC_SHIFT)) & I2S_RTCR_TSINC_MASK)
31131#define I2S_RTCR_RTSC_MASK (0x100U)
31132#define I2S_RTCR_RTSC_SHIFT (8U)
31133/*! RTSC - Reset Timestamp Counter
31134 * 0b0..Timestamp counter is not reset.
31135 * 0b1..Timestamp counter is reset.
31136 */
31137#define I2S_RTCR_RTSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_RTSC_SHIFT)) & I2S_RTCR_RTSC_MASK)
31138#define I2S_RTCR_RBC_MASK (0x200U)
31139#define I2S_RTCR_RBC_SHIFT (9U)
31140/*! RBC - Reset Bit Counter
31141 * 0b0..Bit counter is not reset.
31142 * 0b1..Bit counter is reset.
31143 */
31144#define I2S_RTCR_RBC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTCR_RBC_SHIFT)) & I2S_RTCR_RBC_MASK)
31145/*! @} */
31146
31147/*! @name RTSR - SAI Receive Timestamp Register */
31148/*! @{ */
31149#define I2S_RTSR_TSC_MASK (0xFFFFFFFFU)
31150#define I2S_RTSR_TSC_SHIFT (0U)
31151#define I2S_RTSR_TSC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RTSR_TSC_SHIFT)) & I2S_RTSR_TSC_MASK)
31152/*! @} */
31153
31154/*! @name RBCR - SAI Receive Bit Count Register */
31155/*! @{ */
31156#define I2S_RBCR_BCNT_MASK (0xFFFFFFFFU)
31157#define I2S_RBCR_BCNT_SHIFT (0U)
31158#define I2S_RBCR_BCNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RBCR_BCNT_SHIFT)) & I2S_RBCR_BCNT_MASK)
31159/*! @} */
31160
31161/*! @name RBCTR - SAI Receive Bit Count Timestamp Register */
31162/*! @{ */
31163#define I2S_RBCTR_BCTS_MASK (0xFFFFFFFFU)
31164#define I2S_RBCTR_BCTS_SHIFT (0U)
31165#define I2S_RBCTR_BCTS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RBCTR_BCTS_SHIFT)) & I2S_RBCTR_BCTS_MASK)
31166/*! @} */
31167
31168/*! @name MCR - SAI MCLK Control Register */
31169/*! @{ */
31170#define I2S_MCR_DIV_MASK (0xFFU)
31171#define I2S_MCR_DIV_SHIFT (0U)
31172#define I2S_MCR_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIV_SHIFT)) & I2S_MCR_DIV_MASK)
31173#define I2S_MCR_DIVEN_MASK (0x800000U)
31174#define I2S_MCR_DIVEN_SHIFT (23U)
31175/*! DIVEN - MCLK Post Divide Enable
31176 * 0b0..Output on MCLK signal pin is the audio master clock.
31177 * 0b1..Output on MCLK signal pin is a post-divided version of audio master clock.
31178 */
31179#define I2S_MCR_DIVEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DIVEN_SHIFT)) & I2S_MCR_DIVEN_MASK)
31180#define I2S_MCR_MOE_MASK (0x40000000U)
31181#define I2S_MCR_MOE_SHIFT (30U)
31182/*! MOE - MCLK Output Enable
31183 * 0b0..MCLK signal pin is an input.
31184 * 0b1..MCLK signal pin is an output.
31185 */
31186#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
31187/*! @} */
31188
31189/*!
31190 * @}
31191 */ /* end of group I2S_Register_Masks */
31192
31193/* I2S - Peripheral instance base addresses */
31194/** Peripheral I2S2 base address */
31195#define I2S2_BASE (0x30020000u)
31196/** Peripheral I2S2 base pointer */
31197#define I2S2 ((I2S_Type *)I2S2_BASE)
31198/** Peripheral I2S3 base address */
31199#define I2S3_BASE (0x30030000u)
31200/** Peripheral I2S3 base pointer */
31201#define I2S3 ((I2S_Type *)I2S3_BASE)
31202/** Peripheral I2S5 base address */
31203#define I2S5_BASE (0x30050000u)
31204/** Peripheral I2S5 base pointer */
31205#define I2S5 ((I2S_Type *)I2S5_BASE)
31206/** Peripheral I2S6 base address */
31207#define I2S6_BASE (0x30060000u)
31208/** Peripheral I2S6 base pointer */
31209#define I2S6 ((I2S_Type *)I2S6_BASE)
31210/** Peripheral I2S7 base address */
31211#define I2S7_BASE (0x300B0000u)
31212/** Peripheral I2S7 base pointer */
31213#define I2S7 ((I2S_Type *)I2S7_BASE)
31214/** Array initializer of I2S peripheral base addresses */
31215#define I2S_BASE_ADDRS \
31216 { \
31217 0u, 0u, I2S2_BASE, I2S3_BASE, 0u, I2S5_BASE, I2S6_BASE, I2S7_BASE \
31218 }
31219/** Array initializer of I2S peripheral base pointers */
31220#define I2S_BASE_PTRS \
31221 { \
31222 (I2S_Type *)0u, (I2S_Type *)0u, I2S2, I2S3, (I2S_Type *)0u, I2S5, I2S6, I2S7 \
31223 }
31224/** Interrupt vectors for the I2S peripheral type */
31225#define I2S_RX_IRQS \
31226 { \
31227 NotAvail_IRQn, NotAvail_IRQn, I2S2_IRQn, I2S3_IRQn, NotAvail_IRQn, I2S56_IRQn, I2S56_IRQn, I2S7_IRQn \
31228 }
31229#define I2S_TX_IRQS \
31230 { \
31231 NotAvail_IRQn, NotAvail_IRQn, I2S2_IRQn, I2S3_IRQn, NotAvail_IRQn, I2S56_IRQn, I2S56_IRQn, I2S7_IRQn \
31232 }
31233
31234/*!
31235 * @}
31236 */ /* end of group I2S_Peripheral_Access_Layer */
31237
31238/* ----------------------------------------------------------------------------
31239 -- IOMUXC Peripheral Access Layer
31240 ---------------------------------------------------------------------------- */
31241
31242/*!
31243 * @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer
31244 * @{
31245 */
31246
31247/** IOMUXC - Register Layout Typedef */
31248typedef struct
31249{
31250 uint8_t RESERVED_0[32];
31251 __IO uint32_t SW_MUX_CTL_PAD[141]; /**< Pad Mux Register, array offset: 0x20, array step: 0x4 */
31252 __IO uint32_t SW_PAD_CTL_PAD[154]; /**< Pad Control Register, array offset: 0x254, array step: 0x4 */
31253 __IO uint32_t SELECT_INPUT[78]; /**< Select Input Register, array offset: 0x4BC, array step: 0x4 */
31254} IOMUXC_Type;
31255
31256/* ----------------------------------------------------------------------------
31257 -- IOMUXC Register Masks
31258 ---------------------------------------------------------------------------- */
31259
31260/*!
31261 * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks
31262 * @{
31263 */
31264
31265/*! @name SW_MUX_CTL_PAD - Pad Mux Register */
31266/*! @{ */
31267#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0x7U)
31268#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)
31269/*! MUX_MODE
31270 * 0b000..Select signal SRC_BOOT_MODE2
31271 * 0b001..Select signal I2C1_SCL- Configure register IOMUXC_I2C1_SCL_SELECT_INPUTSelect Input Register for mode ALT1.
31272 */
31273#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) \
31274 (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)
31275#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U)
31276#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U)
31277/*! SION
31278 * 0b1..Force input path of pad BOOT_MODE2
31279 * 0b0..Input Path is determined by functionality of the selected mux mode (regular).
31280 */
31281#define IOMUXC_SW_MUX_CTL_PAD_SION(x) \
31282 (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
31283/*! @} */
31284
31285/* The count of IOMUXC_SW_MUX_CTL_PAD */
31286#define IOMUXC_SW_MUX_CTL_PAD_COUNT (141U)
31287
31288/*! @name SW_PAD_CTL_PAD - Pad Control Register */
31289/*! @{ */
31290#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x7U)
31291#define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (0U)
31292/*! DSE - Drive Strength Field
31293 * 0b00x..Drive strength X1
31294 * 0b01x..Drive strength X4
31295 * 0b10x..Drive strength X2
31296 * 0b11x..Drive strength X6
31297 */
31298#define IOMUXC_SW_PAD_CTL_PAD_DSE(x) \
31299 (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
31300#define IOMUXC_SW_PAD_CTL_PAD_FSEL_MASK (0x18U)
31301#define IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT (3U)
31302/*! FSEL - Slew Rate Field
31303 * 0b0x..Select slow slew rate (IO.SR = 1)
31304 * 0b1x..Select fast slew rate (IO.SR = 0)
31305 */
31306#define IOMUXC_SW_PAD_CTL_PAD_FSEL(x) \
31307 (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_FSEL_MASK)
31308#define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x20U)
31309#define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (5U)
31310/*! ODE - Open Drain Enable Field
31311 * 0b0..Disable open-drain mode
31312 * 0b1..Enable open-drain mode
31313 */
31314#define IOMUXC_SW_PAD_CTL_PAD_ODE(x) \
31315 (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
31316#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x40U)
31317#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (6U)
31318/*! PUE
31319 * 0b0..Select pull-down resistor, the resistor is enabled when IO.PE=1
31320 * 0b1..Select pull-up resistor, the resistor is enabled when IO.PE=1
31321 */
31322#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) \
31323 (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
31324#define IOMUXC_SW_PAD_CTL_PAD_HYS_MASK (0x80U)
31325#define IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT (7U)
31326/*! HYS - Hysteresis Enable Field
31327 * 0b0..Select CMOS input, IO.IS=0
31328 * 0b1..Select schmitt input, IO.IS=1
31329 */
31330#define IOMUXC_SW_PAD_CTL_PAD_HYS(x) \
31331 (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_HYS_MASK)
31332#define IOMUXC_SW_PAD_CTL_PAD_PE_MASK (0x100U)
31333#define IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT (8U)
31334/*! PE - Pull Resistors Enable Field
31335 * 0b0..Disable pull resistor, IO.PE=0
31336 * 0b1..Enable pull resistor, IO.PE=1
31337 */
31338#define IOMUXC_SW_PAD_CTL_PAD_PE(x) \
31339 (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PE_MASK)
31340/*! @} */
31341
31342/* The count of IOMUXC_SW_PAD_CTL_PAD */
31343#define IOMUXC_SW_PAD_CTL_PAD_COUNT (154U)
31344
31345/*! @name SELECT_INPUT - Select Input Register */
31346/*! @{ */
31347#define IOMUXC_SELECT_INPUT_DAISY_MASK \
31348 (0xFU) /* Merged from fields with different position or width, of widths (1, 2, 3, 4), largest definition used */
31349#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U)
31350/*! DAISY - Input Select (DAISY) Field
31351 * 0b0..Selecting ALT5 mode of pad GPIO1_IO05 for CCM_PMIC_READY.
31352 * 0b1..Selecting ALT5 mode of pad GPIO1_IO11 for CCM_PMIC_READY.
31353 */
31354#define IOMUXC_SELECT_INPUT_DAISY(x) \
31355 (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & \
31356 IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2, 3, 4), \
31357 largest definition used */
31358/*! @} */
31359
31360/* The count of IOMUXC_SELECT_INPUT */
31361#define IOMUXC_SELECT_INPUT_COUNT (78U)
31362
31363/*!
31364 * @}
31365 */ /* end of group IOMUXC_Register_Masks */
31366
31367/* IOMUXC - Peripheral instance base addresses */
31368/** Peripheral IOMUXC base address */
31369#define IOMUXC_BASE (0x30330000u)
31370/** Peripheral IOMUXC base pointer */
31371#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE)
31372/** Array initializer of IOMUXC peripheral base addresses */
31373#define IOMUXC_BASE_ADDRS \
31374 { \
31375 IOMUXC_BASE \
31376 }
31377/** Array initializer of IOMUXC peripheral base pointers */
31378#define IOMUXC_BASE_PTRS \
31379 { \
31380 IOMUXC \
31381 }
31382
31383/*!
31384 * @}
31385 */ /* end of group IOMUXC_Peripheral_Access_Layer */
31386
31387/* ----------------------------------------------------------------------------
31388 -- IOMUXC_GPR Peripheral Access Layer
31389 ---------------------------------------------------------------------------- */
31390
31391/*!
31392 * @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer
31393 * @{
31394 */
31395
31396/** IOMUXC_GPR - Register Layout Typedef */
31397typedef struct
31398{
31399 uint32_t GPR0; /**< General Purpose Register 0, offset: 0x0 */
31400 __IO uint32_t GPR1; /**< General Purpose Register 1, offset: 0x4 */
31401 __IO uint32_t GPR2; /**< General Purpose Register 2, offset: 0x8 */
31402 __IO uint32_t GPR3; /**< General Purpose Register 3, offset: 0xC */
31403 __IO uint32_t GPR4; /**< General Purpose Register 4, offset: 0x10 */
31404 __IO uint32_t GPR5; /**< General Purpose Register 5, offset: 0x14 */
31405 __IO uint32_t GPR6; /**< General Purpose Register 6, offset: 0x18 */
31406 __IO uint32_t GPR7; /**< General Purpose Register 7, offset: 0x1C */
31407 __IO uint32_t GPR8; /**< General Purpose Register 8, offset: 0x20 */
31408 uint32_t GPR9; /**< General Purpose Register 9, offset: 0x24 */
31409 __IO uint32_t GPR10; /**< General Purpose Register 10, offset: 0x28 */
31410 __IO uint32_t GPR11; /**< General Purpose Register 11, offset: 0x2C */
31411 uint32_t GPR12; /**< General Purpose Register 12, offset: 0x30 */
31412 __IO uint32_t GPR13; /**< General Purpose Register 13, offset: 0x34 */
31413 uint32_t GPR14; /**< General Purpose Register 14, offset: 0x38 */
31414 uint32_t GPR15; /**< General Purpose Register 15, offset: 0x3C */
31415 uint32_t GPR16; /**< General Purpose Register 16, offset: 0x40 */
31416 uint32_t GPR17; /**< General Purpose Register 17, offset: 0x44 */
31417 uint32_t GPR18; /**< General Purpose Register 18, offset: 0x48 */
31418 uint32_t GPR19; /**< General Purpose Register 19, offset: 0x4C */
31419 __IO uint32_t GPR20; /**< General Purpose Register 20, offset: 0x50 */
31420 __IO uint32_t GPR21; /**< General Purpose Register 21, offset: 0x54 */
31421 __IO uint32_t GPR22; /**< General Purpose Register 22, offset: 0x58 */
31422 uint32_t GPR[25]; /**< General Purpose Register, array offset: 0x5C, array step: 0x4 */
31423} IOMUXC_GPR_Type;
31424
31425/* ----------------------------------------------------------------------------
31426 -- IOMUXC_GPR Register Masks
31427 ---------------------------------------------------------------------------- */
31428
31429/*!
31430 * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks
31431 * @{
31432 */
31433
31434/*! @name GPR1 - General Purpose Register 1 */
31435/*! @{ */
31436#define IOMUXC_GPR_GPR1_GPR_IRQ_MASK (0x1000U)
31437#define IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT (12U)
31438#define IOMUXC_GPR_GPR1_GPR_IRQ(x) \
31439 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT)) & IOMUXC_GPR_GPR1_GPR_IRQ_MASK)
31440#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK (0x2000U)
31441#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT (13U)
31442/*! GPR_ENET1_TX_CLK_SEL
31443 * 0b0..ENET_TD2.ALT1 is input, input data is used as ENET1_IPG_CLK_RMII.
31444 * 0b1..ENET_TD2.ALT1 is output, output data comes from CCM_ENET_REF_CLK_ROOT.
31445 */
31446#define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL(x) \
31447 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT)) & \
31448 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK)
31449#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK (0x800000U)
31450#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT (23U)
31451#define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK(x) \
31452 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT)) & \
31453 IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK)
31454#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK (0xF0000000U)
31455#define IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT (28U)
31456#define IOMUXC_GPR_GPR1_GPR_DBG_ACK(x) \
31457 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT)) & IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK)
31458/*! @} */
31459
31460/*! @name GPR2 - General Purpose Register 2 */
31461/*! @{ */
31462#define IOMUXC_GPR_GPR2_GPR_SAI2_EXT_MCLK_EN_MASK (0x2U)
31463#define IOMUXC_GPR_GPR2_GPR_SAI2_EXT_MCLK_EN_SHIFT (1U)
31464/*! GPR_SAI2_EXT_MCLK_EN
31465 * 0b1..the corresponding pads are input.
31466 * 0b0..the corresponding pads are output.
31467 */
31468#define IOMUXC_GPR_GPR2_GPR_SAI2_EXT_MCLK_EN(x) \
31469 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_GPR_SAI2_EXT_MCLK_EN_SHIFT)) & \
31470 IOMUXC_GPR_GPR2_GPR_SAI2_EXT_MCLK_EN_MASK)
31471#define IOMUXC_GPR_GPR2_GPR_SAI3_EXT_MCLK_EN_MASK (0x4U)
31472#define IOMUXC_GPR_GPR2_GPR_SAI3_EXT_MCLK_EN_SHIFT (2U)
31473/*! GPR_SAI3_EXT_MCLK_EN
31474 * 0b1..the corresponding pads are input.
31475 * 0b0..the corresponding pads are output.
31476 */
31477#define IOMUXC_GPR_GPR2_GPR_SAI3_EXT_MCLK_EN(x) \
31478 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_GPR_SAI3_EXT_MCLK_EN_SHIFT)) & \
31479 IOMUXC_GPR_GPR2_GPR_SAI3_EXT_MCLK_EN_MASK)
31480#define IOMUXC_GPR_GPR2_GPR_SAI5_EXT_MCLK_EN_MASK (0x10U)
31481#define IOMUXC_GPR_GPR2_GPR_SAI5_EXT_MCLK_EN_SHIFT (4U)
31482/*! GPR_SAI5_EXT_MCLK_EN
31483 * 0b1..the corresponding pads are input.
31484 * 0b0..the corresponding pads are output.
31485 */
31486#define IOMUXC_GPR_GPR2_GPR_SAI5_EXT_MCLK_EN(x) \
31487 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_GPR_SAI5_EXT_MCLK_EN_SHIFT)) & \
31488 IOMUXC_GPR_GPR2_GPR_SAI5_EXT_MCLK_EN_MASK)
31489#define IOMUXC_GPR_GPR2_GPR_SAI6_EXT_MCLK_EN_MASK (0x20U)
31490#define IOMUXC_GPR_GPR2_GPR_SAI6_EXT_MCLK_EN_SHIFT (5U)
31491/*! GPR_SAI6_EXT_MCLK_EN
31492 * 0b1..the corresponding pads are input.
31493 * 0b0..the corresponding pads are output.
31494 */
31495#define IOMUXC_GPR_GPR2_GPR_SAI6_EXT_MCLK_EN(x) \
31496 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_GPR_SAI6_EXT_MCLK_EN_SHIFT)) & \
31497 IOMUXC_GPR_GPR2_GPR_SAI6_EXT_MCLK_EN_MASK)
31498#define IOMUXC_GPR_GPR2_GPR_SAI7_EXT_MCLK_EN_MASK (0x40U)
31499#define IOMUXC_GPR_GPR2_GPR_SAI7_EXT_MCLK_EN_SHIFT (6U)
31500/*! GPR_SAI7_EXT_MCLK_EN
31501 * 0b1..the corresponding pads are input.
31502 * 0b0..the corresponding pads are output.
31503 */
31504#define IOMUXC_GPR_GPR2_GPR_SAI7_EXT_MCLK_EN(x) \
31505 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_GPR_SAI7_EXT_MCLK_EN_SHIFT)) & \
31506 IOMUXC_GPR_GPR2_GPR_SAI7_EXT_MCLK_EN_MASK)
31507#define IOMUXC_GPR_GPR2_GPR_GPT4_EXT_CLK_SEL_MASK (0xF00U)
31508#define IOMUXC_GPR_GPR2_GPR_GPT4_EXT_CLK_SEL_SHIFT (8U)
31509/*! GPR_GPT4_EXT_CLK_SEL
31510 * 0b0000..SAI7_TX_SYNC
31511 * 0b0001..SAI2_TX_SYNC
31512 * 0b0010..SAI3_TX_SYNC
31513 * 0b0011..Reserved
31514 * 0b0100..SAI5_TX_SYNC
31515 * 0b0101..SAI6_TX_SYNC
31516 * 0b0110..SAI7_RX_SYNC
31517 * 0b0111..SAI2_RX_SYNC
31518 * 0b1000..SAI3_RX_SYNC
31519 * 0b1001..Reserved
31520 * 0b1010..SAI5_RX_SYNC
31521 */
31522#define IOMUXC_GPR_GPR2_GPR_GPT4_EXT_CLK_SEL(x) \
31523 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_GPR_GPT4_EXT_CLK_SEL_SHIFT)) & \
31524 IOMUXC_GPR_GPR2_GPR_GPT4_EXT_CLK_SEL_MASK)
31525#define IOMUXC_GPR_GPR2_GPR_GPT5_EXT_CLK_SEL_MASK (0xF000U)
31526#define IOMUXC_GPR_GPR2_GPR_GPT5_EXT_CLK_SEL_SHIFT (12U)
31527/*! GPR_GPT5_EXT_CLK_SEL
31528 * 0b0000..SAI7_TX_SYNC
31529 * 0b0001..SAI2_TX_SYNC
31530 * 0b0010..SAI3_TX_SYNC
31531 * 0b0011..Reserved
31532 * 0b0100..SAI5_TX_SYNC
31533 * 0b0101..SAI6_TX_SYNC
31534 * 0b0110..SAI7_RX_SYNC
31535 * 0b0111..SAI2_RX_SYNC
31536 * 0b1000..SAI3_RX_SYNC
31537 * 0b1001..Reserved
31538 * 0b1010..SAI5_RX_SYNC
31539 */
31540#define IOMUXC_GPR_GPR2_GPR_GPT5_EXT_CLK_SEL(x) \
31541 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_GPR_GPT5_EXT_CLK_SEL_SHIFT)) & \
31542 IOMUXC_GPR_GPR2_GPR_GPT5_EXT_CLK_SEL_MASK)
31543#define IOMUXC_GPR_GPR2_GPR_GPT6_EXT_CLK_SEL_MASK (0xF0000U)
31544#define IOMUXC_GPR_GPR2_GPR_GPT6_EXT_CLK_SEL_SHIFT (16U)
31545/*! GPR_GPT6_EXT_CLK_SEL
31546 * 0b0000..SAI7_TX_SYNC
31547 * 0b0001..SAI2_TX_SYNC
31548 * 0b0010..SAI3_TX_SYNC
31549 * 0b0011..Reserved
31550 * 0b0100..SAI5_TX_SYNC
31551 * 0b0101..SAI6_TX_SYNC
31552 * 0b0110..SAI7_RX_SYNC
31553 * 0b0111..SAI2_RX_SYNC
31554 * 0b1000..SAI3_RX_SYNC
31555 * 0b1001..Reserved
31556 * 0b1010..SAI5_RX_SYNC
31557 */
31558#define IOMUXC_GPR_GPR2_GPR_GPT6_EXT_CLK_SEL(x) \
31559 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_GPR_GPT6_EXT_CLK_SEL_SHIFT)) & \
31560 IOMUXC_GPR_GPR2_GPR_GPT6_EXT_CLK_SEL_MASK)
31561/*! @} */
31562
31563/*! @name GPR3 - General Purpose Register 3 */
31564/*! @{ */
31565#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_MASK (0x1U)
31566#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_SHIFT (0U)
31567#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en(x) \
31568 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_SHIFT)) & \
31569 IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_MASK)
31570#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_MASK (0x2U)
31571#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_SHIFT (1U)
31572#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en(x) \
31573 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_SHIFT)) & \
31574 IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_MASK)
31575#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_MASK (0x4U)
31576#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_SHIFT (2U)
31577#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en(x) \
31578 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_SHIFT)) & \
31579 IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_MASK)
31580#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_MASK (0x8U)
31581#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_SHIFT (3U)
31582#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en(x) \
31583 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_SHIFT)) & \
31584 IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_MASK)
31585#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_MASK (0x10U)
31586#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_SHIFT (4U)
31587#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en(x) \
31588 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_SHIFT)) & \
31589 IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_MASK)
31590#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_MASK (0x20U)
31591#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_SHIFT (5U)
31592#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en(x) \
31593 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_SHIFT)) & \
31594 IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_MASK)
31595#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_MASK (0x40U)
31596#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_SHIFT (6U)
31597#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en(x) \
31598 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_SHIFT)) & \
31599 IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_MASK)
31600#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_MASK (0x80U)
31601#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_SHIFT (7U)
31602#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en(x) \
31603 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_SHIFT)) & \
31604 IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_MASK)
31605#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_pndg_MASK (0x10000U)
31606#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_pndg_SHIFT (16U)
31607#define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_pndg(x) \
31608 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_pndg_SHIFT)) & \
31609 IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_pndg_MASK)
31610#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_pndg_MASK (0x20000U)
31611#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_pndg_SHIFT (17U)
31612#define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_pndg(x) \
31613 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_pndg_SHIFT)) & \
31614 IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_pndg_MASK)
31615#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_pndg_MASK (0x40000U)
31616#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_pndg_SHIFT (18U)
31617#define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_pndg(x) \
31618 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_pndg_SHIFT)) & \
31619 IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_pndg_MASK)
31620#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_pndg_MASK (0x80000U)
31621#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_pndg_SHIFT (19U)
31622#define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_pndg(x) \
31623 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_pndg_SHIFT)) & \
31624 IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_pndg_MASK)
31625#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_pndg_MASK (0x100000U)
31626#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_pndg_SHIFT (20U)
31627#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_pndg(x) \
31628 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_pndg_SHIFT)) & \
31629 IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_pndg_MASK)
31630#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_pndg_MASK (0x200000U)
31631#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_pndg_SHIFT (21U)
31632#define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_pndg(x) \
31633 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_pndg_SHIFT)) & \
31634 IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_pndg_MASK)
31635#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_pndg_MASK (0x400000U)
31636#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_pndg_SHIFT (22U)
31637#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_pndg(x) \
31638 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_pndg_SHIFT)) & \
31639 IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_pndg_MASK)
31640#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_pndg_MASK (0x800000U)
31641#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_pndg_SHIFT (23U)
31642#define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_pndg(x) \
31643 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_pndg_SHIFT)) & \
31644 IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_pndg_MASK)
31645/*! @} */
31646
31647/*! @name GPR4 - General Purpose Register 4 */
31648/*! @{ */
31649#define IOMUXC_GPR_GPR4_GPR_SDMA1_IPG_STOP_MASK (0x1U)
31650#define IOMUXC_GPR_GPR4_GPR_SDMA1_IPG_STOP_SHIFT (0U)
31651#define IOMUXC_GPR_GPR4_GPR_SDMA1_IPG_STOP(x) \
31652 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_SDMA1_IPG_STOP_SHIFT)) & \
31653 IOMUXC_GPR_GPR4_GPR_SDMA1_IPG_STOP_MASK)
31654#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK (0x8U)
31655#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT (3U)
31656#define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP(x) \
31657 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT)) & \
31658 IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK)
31659#define IOMUXC_GPR_GPR4_GPR_SDMA2_IPG_STOP_MASK (0x10U)
31660#define IOMUXC_GPR_GPR4_GPR_SDMA2_IPG_STOP_SHIFT (4U)
31661#define IOMUXC_GPR_GPR4_GPR_SDMA2_IPG_STOP(x) \
31662 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_SDMA2_IPG_STOP_SHIFT)) & \
31663 IOMUXC_GPR_GPR4_GPR_SDMA2_IPG_STOP_MASK)
31664#define IOMUXC_GPR_GPR4_GPR_SDMA3_IPG_STOP_MASK (0x1000U)
31665#define IOMUXC_GPR_GPR4_GPR_SDMA3_IPG_STOP_SHIFT (12U)
31666#define IOMUXC_GPR_GPR4_GPR_SDMA3_IPG_STOP(x) \
31667 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_GPR_SDMA3_IPG_STOP_SHIFT)) & \
31668 IOMUXC_GPR_GPR4_GPR_SDMA3_IPG_STOP_MASK)
31669#define IOMUXC_GPR_GPR4_SDMA1_IPG_STOP_ACK_MASK (0x10000U)
31670#define IOMUXC_GPR_GPR4_SDMA1_IPG_STOP_ACK_SHIFT (16U)
31671#define IOMUXC_GPR_GPR4_SDMA1_IPG_STOP_ACK(x) \
31672 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SDMA1_IPG_STOP_ACK_SHIFT)) & \
31673 IOMUXC_GPR_GPR4_SDMA1_IPG_STOP_ACK_MASK)
31674#define IOMUXC_GPR_GPR4_SDMA3_IPG_STOP_ACK_MASK (0x40000U)
31675#define IOMUXC_GPR_GPR4_SDMA3_IPG_STOP_ACK_SHIFT (18U)
31676#define IOMUXC_GPR_GPR4_SDMA3_IPG_STOP_ACK(x) \
31677 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SDMA3_IPG_STOP_ACK_SHIFT)) & \
31678 IOMUXC_GPR_GPR4_SDMA3_IPG_STOP_ACK_MASK)
31679#define IOMUXC_GPR_GPR4_ENET1_IPG_STOP_ACK_MASK (0x80000U)
31680#define IOMUXC_GPR_GPR4_ENET1_IPG_STOP_ACK_SHIFT (19U)
31681#define IOMUXC_GPR_GPR4_ENET1_IPG_STOP_ACK(x) \
31682 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET1_IPG_STOP_ACK_SHIFT)) & \
31683 IOMUXC_GPR_GPR4_ENET1_IPG_STOP_ACK_MASK)
31684#define IOMUXC_GPR_GPR4_SDMA2_IPG_STOP_ACK_MASK (0x100000U)
31685#define IOMUXC_GPR_GPR4_SDMA2_IPG_STOP_ACK_SHIFT (20U)
31686#define IOMUXC_GPR_GPR4_SDMA2_IPG_STOP_ACK(x) \
31687 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SDMA2_IPG_STOP_ACK_SHIFT)) & \
31688 IOMUXC_GPR_GPR4_SDMA2_IPG_STOP_ACK_MASK)
31689#define IOMUXC_GPR_GPR4_SAI7_IPG_STOP_ACK_MASK (0x200000U)
31690#define IOMUXC_GPR_GPR4_SAI7_IPG_STOP_ACK_SHIFT (21U)
31691#define IOMUXC_GPR_GPR4_SAI7_IPG_STOP_ACK(x) \
31692 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI7_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI7_IPG_STOP_ACK_MASK)
31693#define IOMUXC_GPR_GPR4_SAI2_IPG_STOP_ACK_MASK (0x400000U)
31694#define IOMUXC_GPR_GPR4_SAI2_IPG_STOP_ACK_SHIFT (22U)
31695#define IOMUXC_GPR_GPR4_SAI2_IPG_STOP_ACK(x) \
31696 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI2_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI2_IPG_STOP_ACK_MASK)
31697#define IOMUXC_GPR_GPR4_SAI3_IPG_STOP_ACK_MASK (0x800000U)
31698#define IOMUXC_GPR_GPR4_SAI3_IPG_STOP_ACK_SHIFT (23U)
31699#define IOMUXC_GPR_GPR4_SAI3_IPG_STOP_ACK(x) \
31700 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI3_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI3_IPG_STOP_ACK_MASK)
31701#define IOMUXC_GPR_GPR4_SAI5_IPG_STOP_ACK_MASK (0x2000000U)
31702#define IOMUXC_GPR_GPR4_SAI5_IPG_STOP_ACK_SHIFT (25U)
31703#define IOMUXC_GPR_GPR4_SAI5_IPG_STOP_ACK(x) \
31704 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI5_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI5_IPG_STOP_ACK_MASK)
31705#define IOMUXC_GPR_GPR4_SAI6_IPG_STOP_ACK_MASK (0x4000000U)
31706#define IOMUXC_GPR_GPR4_SAI6_IPG_STOP_ACK_SHIFT (26U)
31707#define IOMUXC_GPR_GPR4_SAI6_IPG_STOP_ACK(x) \
31708 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_SAI6_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_SAI6_IPG_STOP_ACK_MASK)
31709#define IOMUXC_GPR_GPR4_PDM_IPG_STOP_ACK_MASK (0x8000000U)
31710#define IOMUXC_GPR_GPR4_PDM_IPG_STOP_ACK_SHIFT (27U)
31711#define IOMUXC_GPR_GPR4_PDM_IPG_STOP_ACK(x) \
31712 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_PDM_IPG_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR4_PDM_IPG_STOP_ACK_MASK)
31713/*! @} */
31714
31715/*! @name GPR5 - General Purpose Register 5 */
31716/*! @{ */
31717#define IOMUXC_GPR_GPR5_GPR_PDM_CLK_SEL_MASK (0xFU)
31718#define IOMUXC_GPR_GPR5_GPR_PDM_CLK_SEL_SHIFT (0U)
31719/*! GPR_PDM_CLK_SEL
31720 * 0b0000..normal clock.
31721 * 0b0001..32K clock.
31722 */
31723#define IOMUXC_GPR_GPR5_GPR_PDM_CLK_SEL(x) \
31724 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPR_PDM_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR5_GPR_PDM_CLK_SEL_MASK)
31725#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK (0x40U)
31726#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT (6U)
31727/*! GPR_WDOG1_MASK
31728 * 0b0..WDOG1 low will make the GPIO1_IO02.ALT5_OUT low.
31729 * 0b1..WDOG1 low will NOT impact the GPIO1_IO02.ALT5_OUT.
31730 */
31731#define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK(x) \
31732 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK)
31733#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK (0x80U)
31734#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT (7U)
31735/*! GPR_WDOG2_MASK
31736 * 0b0..WDOG2 low will make the GPIO1_IO02.ALT5_OUT low.
31737 * 0b1..WDOG2 low will NOT impact the GPIO1_IO02.ALT5_OUT.
31738 */
31739#define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK(x) \
31740 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK)
31741#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK (0x100000U)
31742#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT (20U)
31743/*! GPR_WDOG3_MASK
31744 * 0b0..WDOG3 low will make the GPIO1_IO02.ALT5_OUT low.
31745 * 0b1..WDOG3 low will NOT impact the GPIO1_IO02.ALT5_OUT.
31746 */
31747#define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK(x) \
31748 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT)) & IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK)
31749/*! @} */
31750
31751/*! @name GPR6 - General Purpose Register 6 */
31752/*! @{ */
31753#define IOMUXC_GPR_GPR6_GPR_SAI7_SEL3_MASK (0x1FU)
31754#define IOMUXC_GPR_GPR6_GPR_SAI7_SEL3_SHIFT (0U)
31755#define IOMUXC_GPR_GPR6_GPR_SAI7_SEL3(x) \
31756 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_GPR_SAI7_SEL3_SHIFT)) & IOMUXC_GPR_GPR6_GPR_SAI7_SEL3_MASK)
31757#define IOMUXC_GPR_GPR6_GPR_SAI7_SEL1_MASK (0x20U)
31758#define IOMUXC_GPR_GPR6_GPR_SAI7_SEL1_SHIFT (5U)
31759#define IOMUXC_GPR_GPR6_GPR_SAI7_SEL1(x) \
31760 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_GPR_SAI7_SEL1_SHIFT)) & IOMUXC_GPR_GPR6_GPR_SAI7_SEL1_MASK)
31761#define IOMUXC_GPR_GPR6_GPR_SAI7_SEL2_MASK (0x1F00U)
31762#define IOMUXC_GPR_GPR6_GPR_SAI7_SEL2_SHIFT (8U)
31763#define IOMUXC_GPR_GPR6_GPR_SAI7_SEL2(x) \
31764 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_GPR_SAI7_SEL2_SHIFT)) & IOMUXC_GPR_GPR6_GPR_SAI7_SEL2_MASK)
31765#define IOMUXC_GPR_GPR6_GPR_SAI7_MCLK_OUT_SEL_MASK (0x2000U)
31766#define IOMUXC_GPR_GPR6_GPR_SAI7_MCLK_OUT_SEL_SHIFT (13U)
31767#define IOMUXC_GPR_GPR6_GPR_SAI7_MCLK_OUT_SEL(x) \
31768 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_GPR_SAI7_MCLK_OUT_SEL_SHIFT)) & \
31769 IOMUXC_GPR_GPR6_GPR_SAI7_MCLK_OUT_SEL_MASK)
31770#define IOMUXC_GPR_GPR6_GPR_SAI2_SEL3_MASK (0x1F0000U)
31771#define IOMUXC_GPR_GPR6_GPR_SAI2_SEL3_SHIFT (16U)
31772/*! GPR_SAI2_SEL3
31773 * 0b00000..SAI1_CLK_ROOT
31774 * 0b00001..SAI2_CLK_ROOT
31775 * 0b00010..SAI3_CLK_ROOT
31776 * 0b00011..SAI4_CLK_ROOT
31777 * 0b00100..SAI5_CLK_ROOT
31778 * 0b00101..SAI6_CLK_ROOT
31779 * 0b00110..SAI7_CLK_ROOT
31780 * 0b00111..Reserved
31781 * 0b01000..SAI2_MCLK
31782 * 0b01001..SAI3_MCLK
31783 * 0b01010..Reserved
31784 * 0b01011..SAI5_MCLK
31785 * 0b01100..SAI6_MCLK
31786 * 0b01101..SAI7_MCLK
31787 * 0b01110..SPDIF1_CLK_ROOT
31788 * 0b01111..Reserved
31789 * 0b10000..SPDIF1_EXTCLK
31790 * 0b10001..SPDIF1_SRCCLK
31791 * 0b10010..SPDIF1_OUTCLK
31792 * 0b10011..Reserved
31793 */
31794#define IOMUXC_GPR_GPR6_GPR_SAI2_SEL3(x) \
31795 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_GPR_SAI2_SEL3_SHIFT)) & IOMUXC_GPR_GPR6_GPR_SAI2_SEL3_MASK)
31796#define IOMUXC_GPR_GPR6_GPR_SAI2_SEL1_MASK (0x200000U)
31797#define IOMUXC_GPR_GPR6_GPR_SAI2_SEL1_SHIFT (21U)
31798#define IOMUXC_GPR_GPR6_GPR_SAI2_SEL1(x) \
31799 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_GPR_SAI2_SEL1_SHIFT)) & IOMUXC_GPR_GPR6_GPR_SAI2_SEL1_MASK)
31800#define IOMUXC_GPR_GPR6_GPR_SAI2_SEL2_MASK (0x1F000000U)
31801#define IOMUXC_GPR_GPR6_GPR_SAI2_SEL2_SHIFT (24U)
31802/*! GPR_SAI2_SEL2
31803 * 0b00000..SAI1_CLK_ROOT
31804 * 0b00001..SAI2_CLK_ROOT
31805 * 0b00010..SAI3_CLK_ROOT
31806 * 0b00011..SAI4_CLK_ROOT
31807 * 0b00100..SAI5_CLK_ROOT
31808 * 0b00101..SAI6_CLK_ROOT
31809 * 0b00110..SAI7_CLK_ROOT
31810 * 0b00111..Reserved
31811 * 0b01000..SAI2_MCLK
31812 * 0b01001..SAI3_MCLK
31813 * 0b01010..Reserved
31814 * 0b01011..SAI5_MCLK
31815 * 0b01100..SAI6_MCLK
31816 * 0b01101..SAI7_MCLK
31817 * 0b01110..SPDIF1_CLK_ROOT
31818 * 0b01111..Reserved
31819 * 0b10000..SPDIF1_EXTCLK
31820 * 0b10001..SPDIF1_SRCCLK
31821 * 0b10010..SPDIF1_OUTCLK
31822 * 0b10011..Reserved
31823 */
31824#define IOMUXC_GPR_GPR6_GPR_SAI2_SEL2(x) \
31825 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_GPR_SAI2_SEL2_SHIFT)) & IOMUXC_GPR_GPR6_GPR_SAI2_SEL2_MASK)
31826#define IOMUXC_GPR_GPR6_GPR_SAI2_MCLK_OUT_SEL_MASK (0x20000000U)
31827#define IOMUXC_GPR_GPR6_GPR_SAI2_MCLK_OUT_SEL_SHIFT (29U)
31828#define IOMUXC_GPR_GPR6_GPR_SAI2_MCLK_OUT_SEL(x) \
31829 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_GPR_SAI2_MCLK_OUT_SEL_SHIFT)) & \
31830 IOMUXC_GPR_GPR6_GPR_SAI2_MCLK_OUT_SEL_MASK)
31831/*! @} */
31832
31833/*! @name GPR7 - General Purpose Register 7 */
31834/*! @{ */
31835#define IOMUXC_GPR_GPR7_GPR_SAI3_SEL3_MASK (0x1FU)
31836#define IOMUXC_GPR_GPR7_GPR_SAI3_SEL3_SHIFT (0U)
31837#define IOMUXC_GPR_GPR7_GPR_SAI3_SEL3(x) \
31838 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_GPR_SAI3_SEL3_SHIFT)) & IOMUXC_GPR_GPR7_GPR_SAI3_SEL3_MASK)
31839#define IOMUXC_GPR_GPR7_GPR_SAI3_SEL1_MASK (0x20U)
31840#define IOMUXC_GPR_GPR7_GPR_SAI3_SEL1_SHIFT (5U)
31841#define IOMUXC_GPR_GPR7_GPR_SAI3_SEL1(x) \
31842 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_GPR_SAI3_SEL1_SHIFT)) & IOMUXC_GPR_GPR7_GPR_SAI3_SEL1_MASK)
31843#define IOMUXC_GPR_GPR7_GPR_SAI3_SEL2_MASK (0x1F00U)
31844#define IOMUXC_GPR_GPR7_GPR_SAI3_SEL2_SHIFT (8U)
31845#define IOMUXC_GPR_GPR7_GPR_SAI3_SEL2(x) \
31846 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_GPR_SAI3_SEL2_SHIFT)) & IOMUXC_GPR_GPR7_GPR_SAI3_SEL2_MASK)
31847#define IOMUXC_GPR_GPR7_GPR_SAI3_MCLK_OUT_SEL_MASK (0x2000U)
31848#define IOMUXC_GPR_GPR7_GPR_SAI3_MCLK_OUT_SEL_SHIFT (13U)
31849#define IOMUXC_GPR_GPR7_GPR_SAI3_MCLK_OUT_SEL(x) \
31850 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_GPR_SAI3_MCLK_OUT_SEL_SHIFT)) & \
31851 IOMUXC_GPR_GPR7_GPR_SAI3_MCLK_OUT_SEL_MASK)
31852/*! @} */
31853
31854/*! @name GPR8 - General Purpose Register 8 */
31855/*! @{ */
31856#define IOMUXC_GPR_GPR8_GPR_SAI5_SEL3_MASK (0x1FU)
31857#define IOMUXC_GPR_GPR8_GPR_SAI5_SEL3_SHIFT (0U)
31858#define IOMUXC_GPR_GPR8_GPR_SAI5_SEL3(x) \
31859 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_GPR_SAI5_SEL3_SHIFT)) & IOMUXC_GPR_GPR8_GPR_SAI5_SEL3_MASK)
31860#define IOMUXC_GPR_GPR8_GPR_SAI5_SEL1_MASK (0x20U)
31861#define IOMUXC_GPR_GPR8_GPR_SAI5_SEL1_SHIFT (5U)
31862#define IOMUXC_GPR_GPR8_GPR_SAI5_SEL1(x) \
31863 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_GPR_SAI5_SEL1_SHIFT)) & IOMUXC_GPR_GPR8_GPR_SAI5_SEL1_MASK)
31864#define IOMUXC_GPR_GPR8_GPR_SAI5_SEL2_MASK (0x1F00U)
31865#define IOMUXC_GPR_GPR8_GPR_SAI5_SEL2_SHIFT (8U)
31866#define IOMUXC_GPR_GPR8_GPR_SAI5_SEL2(x) \
31867 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_GPR_SAI5_SEL2_SHIFT)) & IOMUXC_GPR_GPR8_GPR_SAI5_SEL2_MASK)
31868#define IOMUXC_GPR_GPR8_GPR_SAI5_MCLK_OUT_SEL_MASK (0x2000U)
31869#define IOMUXC_GPR_GPR8_GPR_SAI5_MCLK_OUT_SEL_SHIFT (13U)
31870#define IOMUXC_GPR_GPR8_GPR_SAI5_MCLK_OUT_SEL(x) \
31871 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_GPR_SAI5_MCLK_OUT_SEL_SHIFT)) & \
31872 IOMUXC_GPR_GPR8_GPR_SAI5_MCLK_OUT_SEL_MASK)
31873#define IOMUXC_GPR_GPR8_GPR_SAI6_SEL3_MASK (0x1F0000U)
31874#define IOMUXC_GPR_GPR8_GPR_SAI6_SEL3_SHIFT (16U)
31875#define IOMUXC_GPR_GPR8_GPR_SAI6_SEL3(x) \
31876 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_GPR_SAI6_SEL3_SHIFT)) & IOMUXC_GPR_GPR8_GPR_SAI6_SEL3_MASK)
31877#define IOMUXC_GPR_GPR8_GPR_SAI6_SEL1_MASK (0x200000U)
31878#define IOMUXC_GPR_GPR8_GPR_SAI6_SEL1_SHIFT (21U)
31879#define IOMUXC_GPR_GPR8_GPR_SAI6_SEL1(x) \
31880 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_GPR_SAI6_SEL1_SHIFT)) & IOMUXC_GPR_GPR8_GPR_SAI6_SEL1_MASK)
31881#define IOMUXC_GPR_GPR8_GPR_SAI6_SEL2_MASK (0x1F000000U)
31882#define IOMUXC_GPR_GPR8_GPR_SAI6_SEL2_SHIFT (24U)
31883#define IOMUXC_GPR_GPR8_GPR_SAI6_SEL2(x) \
31884 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_GPR_SAI6_SEL2_SHIFT)) & IOMUXC_GPR_GPR8_GPR_SAI6_SEL2_MASK)
31885#define IOMUXC_GPR_GPR8_GPR_SAI6_MCLK_OUT_SEL_MASK (0x20000000U)
31886#define IOMUXC_GPR_GPR8_GPR_SAI6_MCLK_OUT_SEL_SHIFT (29U)
31887#define IOMUXC_GPR_GPR8_GPR_SAI6_MCLK_OUT_SEL(x) \
31888 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_GPR_SAI6_MCLK_OUT_SEL_SHIFT)) & \
31889 IOMUXC_GPR_GPR8_GPR_SAI6_MCLK_OUT_SEL_MASK)
31890/*! @} */
31891
31892/*! @name GPR10 - General Purpose Register 10 */
31893/*! @{ */
31894#define IOMUXC_GPR_GPR10_GPR_TZASC_EN_MASK (0x1U)
31895#define IOMUXC_GPR_GPR10_GPR_TZASC_EN_SHIFT (0U)
31896#define IOMUXC_GPR_GPR10_GPR_TZASC_EN(x) \
31897 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_GPR_TZASC_EN_SHIFT)) & IOMUXC_GPR_GPR10_GPR_TZASC_EN_MASK)
31898#define IOMUXC_GPR_GPR10_GPR_TZASC_ID_SWAP_BYPASS_MASK (0x2U)
31899#define IOMUXC_GPR_GPR10_GPR_TZASC_ID_SWAP_BYPASS_SHIFT (1U)
31900#define IOMUXC_GPR_GPR10_GPR_TZASC_ID_SWAP_BYPASS(x) \
31901 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_GPR_TZASC_ID_SWAP_BYPASS_SHIFT)) & \
31902 IOMUXC_GPR_GPR10_GPR_TZASC_ID_SWAP_BYPASS_MASK)
31903#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK (0x4U)
31904#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT (2U)
31905#define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN(x) \
31906 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT)) & \
31907 IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK)
31908#define IOMUXC_GPR_GPR10_GPR_EXC_ERR_RESP_EN_MASK (0x8U)
31909#define IOMUXC_GPR_GPR10_GPR_EXC_ERR_RESP_EN_SHIFT (3U)
31910#define IOMUXC_GPR_GPR10_GPR_EXC_ERR_RESP_EN(x) \
31911 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_GPR_EXC_ERR_RESP_EN_SHIFT)) & \
31912 IOMUXC_GPR_GPR10_GPR_EXC_ERR_RESP_EN_MASK)
31913#define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_EN_MASK (0x10000U)
31914#define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_EN_SHIFT (16U)
31915#define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_EN(x) \
31916 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_EN_SHIFT)) & \
31917 IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_EN_MASK)
31918#define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_ID_SWAP_BYPASS_MASK (0x20000U)
31919#define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_ID_SWAP_BYPASS_SHIFT (17U)
31920#define IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_ID_SWAP_BYPASS(x) \
31921 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_ID_SWAP_BYPASS_SHIFT)) & \
31922 IOMUXC_GPR_GPR10_LOCK_GPR_TZASC_ID_SWAP_BYPASS_MASK)
31923#define IOMUXC_GPR_GPR10_LOCK_GPR_SEC_ERR_RESP_EN_MASK (0x40000U)
31924#define IOMUXC_GPR_GPR10_LOCK_GPR_SEC_ERR_RESP_EN_SHIFT (18U)
31925#define IOMUXC_GPR_GPR10_LOCK_GPR_SEC_ERR_RESP_EN(x) \
31926 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_GPR_SEC_ERR_RESP_EN_SHIFT)) & \
31927 IOMUXC_GPR_GPR10_LOCK_GPR_SEC_ERR_RESP_EN_MASK)
31928#define IOMUXC_GPR_GPR10_LOCK_GPR_EXC_ERR_RESP_EN_MASK (0x80000U)
31929#define IOMUXC_GPR_GPR10_LOCK_GPR_EXC_ERR_RESP_EN_SHIFT (19U)
31930#define IOMUXC_GPR_GPR10_LOCK_GPR_EXC_ERR_RESP_EN(x) \
31931 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_LOCK_GPR_EXC_ERR_RESP_EN_SHIFT)) & \
31932 IOMUXC_GPR_GPR10_LOCK_GPR_EXC_ERR_RESP_EN_MASK)
31933/*! @} */
31934
31935/*! @name GPR11 - General Purpose Register 11 */
31936/*! @{ */
31937#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK (0x1U)
31938#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT (0U)
31939#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0(x) \
31940 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT)) & \
31941 IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK)
31942#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK (0xFEU)
31943#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT (1U)
31944#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1(x) \
31945 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT)) & \
31946 IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK)
31947#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK (0x400U)
31948#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT (10U)
31949#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0(x) \
31950 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT)) & \
31951 IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK)
31952#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK (0x3800U)
31953#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT (11U)
31954#define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1(x) \
31955 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT)) & \
31956 IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK)
31957#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK (0x10000U)
31958#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT (16U)
31959#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0(x) \
31960 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT)) & \
31961 IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK)
31962#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK (0xFE0000U)
31963#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT (17U)
31964#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1(x) \
31965 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT)) & \
31966 IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK)
31967#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK (0x4000000U)
31968#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT (26U)
31969#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0(x) \
31970 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT)) & \
31971 IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK)
31972#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK (0x38000000U)
31973#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT (27U)
31974#define IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1(x) \
31975 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT)) & \
31976 IOMUXC_GPR_GPR11_LOCK_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK)
31977/*! @} */
31978
31979/*! @name GPR13 - General Purpose Register 13 */
31980/*! @{ */
31981#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK (0x1U)
31982#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT (0U)
31983#define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC(x) \
31984 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT)) & \
31985 IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK)
31986#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK (0x2U)
31987#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT (1U)
31988#define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC(x) \
31989 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT)) & \
31990 IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK)
31991/*! @} */
31992
31993/*! @name GPR20 - General Purpose Register 20 */
31994/*! @{ */
31995#define IOMUXC_GPR_GPR20_SRAM_HSD_RAWLM_MASK (0x3U)
31996#define IOMUXC_GPR_GPR20_SRAM_HSD_RAWLM_SHIFT (0U)
31997/*! SRAM_HSD_RAWLM
31998 * 0b00..when supermix operates on 0.8V (default)
31999 * 0b00..when supermix operates on 0.9V
32000 */
32001#define IOMUXC_GPR_GPR20_SRAM_HSD_RAWLM(x) \
32002 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_SRAM_HSD_RAWLM_SHIFT)) & IOMUXC_GPR_GPR20_SRAM_HSD_RAWLM_MASK)
32003#define IOMUXC_GPR_GPR20_SRAM_HSD_RAWL_MASK (0x4U)
32004#define IOMUXC_GPR_GPR20_SRAM_HSD_RAWL_SHIFT (2U)
32005/*! SRAM_HSD_RAWL
32006 * 0b1..when supermix operates on 0.8V (default)
32007 * 0b0..when supermix operates on 0.9V
32008 */
32009#define IOMUXC_GPR_GPR20_SRAM_HSD_RAWL(x) \
32010 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_SRAM_HSD_RAWL_SHIFT)) & IOMUXC_GPR_GPR20_SRAM_HSD_RAWL_MASK)
32011#define IOMUXC_GPR_GPR20_SRAM_HSD_WABLM_MASK (0x18U)
32012#define IOMUXC_GPR_GPR20_SRAM_HSD_WABLM_SHIFT (3U)
32013/*! SRAM_HSD_WABLM
32014 * 0b01..when supermix operates on 0.8V (default)
32015 * 0b00..when supermix operates on 0.9V
32016 */
32017#define IOMUXC_GPR_GPR20_SRAM_HSD_WABLM(x) \
32018 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_SRAM_HSD_WABLM_SHIFT)) & IOMUXC_GPR_GPR20_SRAM_HSD_WABLM_MASK)
32019#define IOMUXC_GPR_GPR20_SRAM_HSD_WABL_MASK (0x20U)
32020#define IOMUXC_GPR_GPR20_SRAM_HSD_WABL_SHIFT (5U)
32021/*! SRAM_HSD_WABL
32022 * 0b1..when supermix operates on 0.8V (default)
32023 * 0b1..when supermix operates on 0.9V
32024 */
32025#define IOMUXC_GPR_GPR20_SRAM_HSD_WABL(x) \
32026 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_SRAM_HSD_WABL_SHIFT)) & IOMUXC_GPR_GPR20_SRAM_HSD_WABL_MASK)
32027/*! @} */
32028
32029/*! @name GPR21 - General Purpose Register 21 */
32030/*! @{ */
32031#define IOMUXC_GPR_GPR21_CM7_INIT_VTOR_MASK (0xFFFFFF80U)
32032#define IOMUXC_GPR_GPR21_CM7_INIT_VTOR_SHIFT (7U)
32033#define IOMUXC_GPR_GPR21_CM7_INIT_VTOR(x) \
32034 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_CM7_INIT_VTOR_SHIFT)) & IOMUXC_GPR_GPR21_CM7_INIT_VTOR_MASK)
32035/*! @} */
32036
32037/*! @name GPR22 - General Purpose Register 22 */
32038/*! @{ */
32039#define IOMUXC_GPR_GPR22_CM7_CPUWAIT_MASK (0x1U)
32040#define IOMUXC_GPR_GPR22_CM7_CPUWAIT_SHIFT (0U)
32041#define IOMUXC_GPR_GPR22_CM7_CPUWAIT(x) \
32042 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_CM7_CPUWAIT_SHIFT)) & IOMUXC_GPR_GPR22_CM7_CPUWAIT_MASK)
32043#define IOMUXC_GPR_GPR22_CM7_HCLK_AUTO_GATE_EN_MASK (0x4U)
32044#define IOMUXC_GPR_GPR22_CM7_HCLK_AUTO_GATE_EN_SHIFT (2U)
32045/*! CM7_HCLK_AUTO_GATE_EN
32046 * 0b0..Disable.
32047 * 0b1..Enable.
32048 */
32049#define IOMUXC_GPR_GPR22_CM7_HCLK_AUTO_GATE_EN(x) \
32050 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_CM7_HCLK_AUTO_GATE_EN_SHIFT)) & \
32051 IOMUXC_GPR_GPR22_CM7_HCLK_AUTO_GATE_EN_MASK)
32052#define IOMUXC_GPR_GPR22_CM7_HCLK_GATE_EN_MASK (0x8U)
32053#define IOMUXC_GPR_GPR22_CM7_HCLK_GATE_EN_SHIFT (3U)
32054/*! CM7_HCLK_GATE_EN
32055 * 0b0..Not Gated.
32056 * 0b1..Gated.
32057 */
32058#define IOMUXC_GPR_GPR22_CM7_HCLK_GATE_EN(x) \
32059 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_CM7_HCLK_GATE_EN_SHIFT)) & IOMUXC_GPR_GPR22_CM7_HCLK_GATE_EN_MASK)
32060#define IOMUXC_GPR_GPR22_CPU_STANDBYWFI_MASK (0xF0000U)
32061#define IOMUXC_GPR_GPR22_CPU_STANDBYWFI_SHIFT (16U)
32062#define IOMUXC_GPR_GPR22_CPU_STANDBYWFI(x) \
32063 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_CPU_STANDBYWFI_SHIFT)) & IOMUXC_GPR_GPR22_CPU_STANDBYWFI_MASK)
32064#define IOMUXC_GPR_GPR22_CPU_STANDBYWFE_MASK (0xF00000U)
32065#define IOMUXC_GPR_GPR22_CPU_STANDBYWFE_SHIFT (20U)
32066#define IOMUXC_GPR_GPR22_CPU_STANDBYWFE(x) \
32067 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_CPU_STANDBYWFE_SHIFT)) & IOMUXC_GPR_GPR22_CPU_STANDBYWFE_MASK)
32068#define IOMUXC_GPR_GPR22_CM7_AHBSRDY_MASK (0x40000000U)
32069#define IOMUXC_GPR_GPR22_CM7_AHBSRDY_SHIFT (30U)
32070/*! CM7_AHBSRDY
32071 * 0b0..AHBS is ready.
32072 * 0b1..AHBS is not ready.
32073 */
32074#define IOMUXC_GPR_GPR22_CM7_AHBSRDY(x) \
32075 (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_CM7_AHBSRDY_SHIFT)) & IOMUXC_GPR_GPR22_CM7_AHBSRDY_MASK)
32076/*! @} */
32077
32078/* The count of IOMUXC_GPR_GPR */
32079#define IOMUXC_GPR_GPR_COUNT (25U)
32080
32081/*!
32082 * @}
32083 */ /* end of group IOMUXC_GPR_Register_Masks */
32084
32085/* IOMUXC_GPR - Peripheral instance base addresses */
32086/** Peripheral IOMUXC_GPR base address */
32087#define IOMUXC_GPR_BASE (0x30340000u)
32088/** Peripheral IOMUXC_GPR base pointer */
32089#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
32090/** Array initializer of IOMUXC_GPR peripheral base addresses */
32091#define IOMUXC_GPR_BASE_ADDRS \
32092 { \
32093 IOMUXC_GPR_BASE \
32094 }
32095/** Array initializer of IOMUXC_GPR peripheral base pointers */
32096#define IOMUXC_GPR_BASE_PTRS \
32097 { \
32098 IOMUXC_GPR \
32099 }
32100
32101/*!
32102 * @}
32103 */ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */
32104
32105/* ----------------------------------------------------------------------------
32106 -- ISI Peripheral Access Layer
32107 ---------------------------------------------------------------------------- */
32108
32109/*!
32110 * @addtogroup ISI_Peripheral_Access_Layer ISI Peripheral Access Layer
32111 * @{
32112 */
32113
32114/** ISI - Register Layout Typedef */
32115typedef struct
32116{
32117 __IO uint32_t CHNL_CTRL; /**< Channel Control Register, offset: 0x0 */
32118 __IO uint32_t CHNL_IMG_CTRL; /**< Channel Image Control Register, offset: 0x4 */
32119 __IO uint32_t CHNL_OUT_BUF_CTRL; /**< Channel Output Buffer Control Register, offset: 0x8 */
32120 __IO uint32_t CHNL_IMG_CFG; /**< Channel Image Configuration, offset: 0xC */
32121 __IO uint32_t CHNL_IER; /**< Channel Interrupt Enable Register, offset: 0x10 */
32122 __IO uint32_t CHNL_STS; /**< Channel Status Register, offset: 0x14 */
32123 __IO uint32_t CHNL_SCALE_FACTOR; /**< Channel Scale Factor Register, offset: 0x18 */
32124 __IO uint32_t CHNL_SCALE_OFFSET; /**< Channel Scale Offset Register, offset: 0x1C */
32125 __IO uint32_t CHNL_CROP_ULC; /**< Channel Crop Upper Left Corner Coordinate Register, offset: 0x20 */
32126 __IO uint32_t CHNL_CROP_LRC; /**< Channel Crop Lower Right Corner Coordinate Register, offset: 0x24 */
32127 __IO uint32_t CHNL_CSC_COEFF0; /**< Channel Color Space Conversion Coefficient Register 0, offset: 0x28 */
32128 __IO uint32_t CHNL_CSC_COEFF1; /**< Channel Color Space Conversion Coefficient Register 1, offset: 0x2C */
32129 __IO uint32_t CHNL_CSC_COEFF2; /**< Channel Color Space Conversion Coefficient Register 2, offset: 0x30 */
32130 __IO uint32_t CHNL_CSC_COEFF3; /**< Channel Color Space Conversion Coefficient Register 3, offset: 0x34 */
32131 __IO uint32_t CHNL_CSC_COEFF4; /**< Channel Color Space Conversion Coefficient Register 4, offset: 0x38 */
32132 __IO uint32_t CHNL_CSC_COEFF5; /**< Channel Color Space Conversion Coefficient Register 5, offset: 0x3C */
32133 __IO uint32_t CHNL_ROI_0_ALPHA; /**< Channel Alpha Value Register for Region of Interest 0, offset: 0x40 */
32134 __IO uint32_t CHNL_ROI_0_ULC; /**< Channel Upper Left Coordinate Register for Region of Interest 0, offset: 0x44 */
32135 __IO uint32_t CHNL_ROI_0_LRC; /**< Channel Lower Right Coordinate Register for Region of Interest 0, offset: 0x48 */
32136 __IO uint32_t CHNL_ROI_1_ALPHA; /**< Channel Alpha Value Register for Region of Interest 1, offset: 0x4C */
32137 __IO uint32_t CHNL_ROI_1_ULC; /**< Channel Upper Left Coordinate Register for Region of Interest 1, offset: 0x50 */
32138 __IO uint32_t CHNL_ROI_1_LRC; /**< Channel Lower Right Coordinate Register for Region of Interest 1, offset: 0x54 */
32139 __IO uint32_t CHNL_ROI_2_ALPHA; /**< Channel Alpha Value Register for Region of Interest 2, offset: 0x58 */
32140 __IO uint32_t CHNL_ROI_2_ULC; /**< Channel Upper Left Coordinate Register for Region of Interest 2, offset: 0x5C */
32141 __IO uint32_t CHNL_ROI_2_LRC; /**< Channel Lower Right Coordinate Register for Region of Interest 2, offset: 0x60 */
32142 __IO uint32_t CHNL_ROI_3_ALPHA; /**< Channel Alpha Value Register for Region of Interest 3, offset: 0x64 */
32143 __IO uint32_t CHNL_ROI_3_ULC; /**< Channel Upper Left Coordinate Register for Region of Interest 3, offset: 0x68 */
32144 __IO uint32_t CHNL_ROI_3_LRC; /**< Channel Lower Right Coordinate Register for Region of Interest 3, offset: 0x6C */
32145 __IO uint32_t CHNL_OUT_BUF1_ADDR_Y; /**< Channel RGB or Luma (Y) Output Buffer 1 Address, offset: 0x70 */
32146 __IO uint32_t CHNL_OUT_BUF1_ADDR_U; /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address, offset: 0x74 */
32147 __IO uint32_t CHNL_OUT_BUF1_ADDR_V; /**< Channel Chroma (V/Cr) Output Buffer 1 Address, offset: 0x78 */
32148 __IO uint32_t CHNL_OUT_BUF_PITCH; /**< Channel Output Buffer Pitch, offset: 0x7C */
32149 __IO uint32_t CHNL_IN_BUF_ADDR; /**< Channel Input Buffer Address, offset: 0x80 */
32150 __IO uint32_t CHNL_IN_BUF_PITCH; /**< Channel Input Buffer Pitch, offset: 0x84 */
32151 __IO uint32_t CHNL_MEM_RD_CTRL; /**< Channel Memory Read Control, offset: 0x88 */
32152 __IO uint32_t CHNL_OUT_BUF2_ADDR_Y; /**< Channel RGB or Luma (Y) Output Buffer 2 Address, offset: 0x8C */
32153 __IO uint32_t CHNL_OUT_BUF2_ADDR_U; /**< Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address, offset: 0x90 */
32154 __IO uint32_t CHNL_OUT_BUF2_ADDR_V; /**< Channel Chroma (V/Cr) Output Buffer 2 Address, offset: 0x94 */
32155 __IO uint32_t CHNL_SCL_IMG_CFG; /**< Channel Scaled Image Configuration, offset: 0x98 */
32156 __IO uint32_t CHNL_FLOW_CTRL; /**< Channel Flow Control Register, offset: 0x9C */
32157} ISI_Type;
32158
32159/* ----------------------------------------------------------------------------
32160 -- ISI Register Masks
32161 ---------------------------------------------------------------------------- */
32162
32163/*!
32164 * @addtogroup ISI_Register_Masks ISI Register Masks
32165 * @{
32166 */
32167
32168/*! @name CHNL_CTRL - Channel Control Register */
32169/*! @{ */
32170#define ISI_CHNL_CTRL_SRC_MASK (0x7U)
32171#define ISI_CHNL_CTRL_SRC_SHIFT (0U)
32172/*! SRC - Input image source port selection
32173 * 0b000..Image will be sourced from input port 0 of the Pixel Link Crossbar
32174 * 0b001..Image will be sourced from input port 1 of the Pixel Link Crossbar
32175 * 0b010..Image will be sourced from input port 2 of the Pixel Link Crossbar
32176 * 0b011..Image will be sourced from input port 3 of the Pixel Link Crossbar
32177 * 0b100..Image will be sourced from input port 4 of the Pixel Link Crossbar
32178 * 0b101..Image will be sourced from input port 5 of the Pixel Link Crossbar (Input port 5 connected to AXI read)
32179 * 0b110..Reserved
32180 * 0b111..Reserved
32181 */
32182#define ISI_CHNL_CTRL_SRC(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_SHIFT)) & ISI_CHNL_CTRL_SRC_MASK)
32183#define ISI_CHNL_CTRL_SRC_TYPE_MASK (0x10U)
32184#define ISI_CHNL_CTRL_SRC_TYPE_SHIFT (4U)
32185/*! SRC_TYPE - Type of selected input image source
32186 * 0b0..Image input source is Pixel Link
32187 * 0b1..Image input source is Memory
32188 */
32189#define ISI_CHNL_CTRL_SRC_TYPE(x) \
32190 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SRC_TYPE_SHIFT)) & ISI_CHNL_CTRL_SRC_TYPE_MASK)
32191#define ISI_CHNL_CTRL_VC_ID_MASK (0xC0U)
32192#define ISI_CHNL_CTRL_VC_ID_SHIFT (6U)
32193/*! VC_ID - Virtual channel ID
32194 * 0b00..Virtual Channel 0 selected or no virtual channel used
32195 * 0b01..Virtual Channel 1 selected
32196 * 0b10..Virtual Channel 2 selected
32197 * 0b11..Virtual Channel 3 selected
32198 */
32199#define ISI_CHNL_CTRL_VC_ID(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_VC_ID_SHIFT)) & ISI_CHNL_CTRL_VC_ID_MASK)
32200#define ISI_CHNL_CTRL_SEC_LB_SRC_MASK (0x700U)
32201#define ISI_CHNL_CTRL_SEC_LB_SRC_SHIFT (8U)
32202#define ISI_CHNL_CTRL_SEC_LB_SRC(x) \
32203 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SEC_LB_SRC_SHIFT)) & ISI_CHNL_CTRL_SEC_LB_SRC_MASK)
32204#define ISI_CHNL_CTRL_SW_RST_MASK (0x1000000U)
32205#define ISI_CHNL_CTRL_SW_RST_SHIFT (24U)
32206/*! SW_RST - Software reset bit
32207 * 0b0..No Reset
32208 * 0b1..Channel pipeline is under software reset
32209 */
32210#define ISI_CHNL_CTRL_SW_RST(x) \
32211 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_SW_RST_SHIFT)) & ISI_CHNL_CTRL_SW_RST_MASK)
32212#define ISI_CHNL_CTRL_CHAIN_BUF_MASK (0x6000000U)
32213#define ISI_CHNL_CTRL_CHAIN_BUF_SHIFT (25U)
32214/*! CHAIN_BUF - Chain line buffer control
32215 * 0b00..No line buffers chained (supports 2048 or less horizontal resolution)
32216 * 0b01..2 line buffers chained (supports 4096 horizontal resolution). Line buffers of channels 'n' and 'n+1' are
32217 * chained. 0b10..4 line buffers chained (supports 8192 horizontal resolution). Line buffers of channels 'n', 'n+1',
32218 * 'n+2' and 'n+3' are chained. 0b11..Reserved for future use
32219 */
32220#define ISI_CHNL_CTRL_CHAIN_BUF(x) \
32221 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHAIN_BUF_SHIFT)) & ISI_CHNL_CTRL_CHAIN_BUF_MASK)
32222#define ISI_CHNL_CTRL_CHNL_BYPASS_MASK (0x20000000U)
32223#define ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT (29U)
32224/*! CHNL_BYPASS - Channel bypass enable
32225 * 0b0..Channel is not bypassed
32226 * 0b1..Channel is bypassed
32227 */
32228#define ISI_CHNL_CTRL_CHNL_BYPASS(x) \
32229 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_BYPASS_SHIFT)) & ISI_CHNL_CTRL_CHNL_BYPASS_MASK)
32230#define ISI_CHNL_CTRL_CLK_EN_MASK (0x40000000U)
32231#define ISI_CHNL_CTRL_CLK_EN_SHIFT (30U)
32232/*! CLK_EN - Channel clock enable
32233 * 0b0..Channel processing clock is disabled
32234 * 0b1..Channel processing clock is enabled
32235 */
32236#define ISI_CHNL_CTRL_CLK_EN(x) \
32237 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CLK_EN_SHIFT)) & ISI_CHNL_CTRL_CLK_EN_MASK)
32238#define ISI_CHNL_CTRL_CHNL_EN_MASK (0x80000000U)
32239#define ISI_CHNL_CTRL_CHNL_EN_SHIFT (31U)
32240/*! CHNL_EN - Enable channel processing
32241 * 0b0..Processing channel is disabled
32242 * 0b1..Processing channel is enabled
32243 */
32244#define ISI_CHNL_CTRL_CHNL_EN(x) \
32245 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CTRL_CHNL_EN_SHIFT)) & ISI_CHNL_CTRL_CHNL_EN_MASK)
32246/*! @} */
32247
32248/*! @name CHNL_IMG_CTRL - Channel Image Control Register */
32249/*! @{ */
32250#define ISI_CHNL_IMG_CTRL_CSC_BYP_MASK (0x1U)
32251#define ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT (0U)
32252/*! CSC_BYP - Color Space Conversion bypass control
32253 * 0b0..CSC is operational
32254 * 0b1..CSC is bypassed
32255 */
32256#define ISI_CHNL_IMG_CTRL_CSC_BYP(x) \
32257 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_BYP_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_BYP_MASK)
32258#define ISI_CHNL_IMG_CTRL_CSC_MODE_MASK (0x6U)
32259#define ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT (1U)
32260/*! CSC_MODE - Color Space Conversion operating mode
32261 * 0b00..Convert from YUV to RGB
32262 * 0b01..Convert from YCbCr to RGB
32263 * 0b10..Convert from RGB to YUV
32264 * 0b11..Convert from RGB to YCbCr
32265 */
32266#define ISI_CHNL_IMG_CTRL_CSC_MODE(x) \
32267 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CSC_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_CSC_MODE_MASK)
32268#define ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK (0x8U)
32269#define ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT (3U)
32270/*! YCBCR_MODE - YCbCr Mode
32271 * 0b0..YCbCr mode is disabled
32272 * 0b1..YCbCr mode is enabled
32273 */
32274#define ISI_CHNL_IMG_CTRL_YCBCR_MODE(x) \
32275 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_YCBCR_MODE_SHIFT)) & ISI_CHNL_IMG_CTRL_YCBCR_MODE_MASK)
32276#define ISI_CHNL_IMG_CTRL_RSVD2_MASK (0x10U)
32277#define ISI_CHNL_IMG_CTRL_RSVD2_SHIFT (4U)
32278#define ISI_CHNL_IMG_CTRL_RSVD2(x) \
32279 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_RSVD2_SHIFT)) & ISI_CHNL_IMG_CTRL_RSVD2_MASK)
32280#define ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK (0x20U)
32281#define ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT (5U)
32282/*! HFLIP_EN - Horizontal flip control
32283 * 0b0..Horizantal image flip disabled
32284 * 0b1..Horizontal image flip enabled
32285 */
32286#define ISI_CHNL_IMG_CTRL_HFLIP_EN(x) \
32287 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_HFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_HFLIP_EN_MASK)
32288#define ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK (0x40U)
32289#define ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT (6U)
32290/*! VFLIP_EN - Veritical flip control
32291 * 0b0..Vertical image flip disabled
32292 * 0b1..Vertical image flip enabled
32293 */
32294#define ISI_CHNL_IMG_CTRL_VFLIP_EN(x) \
32295 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_VFLIP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_VFLIP_EN_MASK)
32296#define ISI_CHNL_IMG_CTRL_CROP_EN_MASK (0x80U)
32297#define ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT (7U)
32298/*! CROP_EN - Output image cropping enable
32299 * 0b0..Image cropping is disabled
32300 * 0b1..Image cropping is enabled
32301 */
32302#define ISI_CHNL_IMG_CTRL_CROP_EN(x) \
32303 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_CROP_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_CROP_EN_MASK)
32304#define ISI_CHNL_IMG_CTRL_DEC_Y_MASK (0x300U)
32305#define ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT (8U)
32306/*! DEC_Y - Vertical pre-decimation control
32307 * 0b00..Pre-decimation filter is disabled. Bilinear scaling filter is still operational.
32308 * 0b01..Decimate by 2
32309 * 0b10..Decimate by 4
32310 * 0b11..Decimate by 8
32311 */
32312#define ISI_CHNL_IMG_CTRL_DEC_Y(x) \
32313 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_Y_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_Y_MASK)
32314#define ISI_CHNL_IMG_CTRL_DEC_X_MASK (0xC00U)
32315#define ISI_CHNL_IMG_CTRL_DEC_X_SHIFT (10U)
32316/*! DEC_X - Horizontal pre-decimation control
32317 * 0b00..Pre-decimation filter is disabled. Bilinear scaling filter is still operational.
32318 * 0b01..Decimate by 2
32319 * 0b10..Decimate by 4
32320 * 0b11..Decimate by 8
32321 */
32322#define ISI_CHNL_IMG_CTRL_DEC_X(x) \
32323 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEC_X_SHIFT)) & ISI_CHNL_IMG_CTRL_DEC_X_MASK)
32324#define ISI_CHNL_IMG_CTRL_DEINT_MASK (0x7000U)
32325#define ISI_CHNL_IMG_CTRL_DEINT_SHIFT (12U)
32326/*! DEINT - De-interlace control
32327 * 0b000, 0b001..No de-interlacing done
32328 * 0b010..Weave de-interlacing (Odd, Even) method used
32329 * 0b011..Weave de-interlacing (Even, Odd) method used
32330 * 0b100..Blending or linear interpolation (Odd + Even) de-interlacing method used
32331 * 0b101..Blending or linear interpolation (Even + Odd) de-interlacing method used
32332 * 0b110, 0b111..Line doubling de-interlacing method used. Both Odd and Even fields are doubled.
32333 */
32334#define ISI_CHNL_IMG_CTRL_DEINT(x) \
32335 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_DEINT_SHIFT)) & ISI_CHNL_IMG_CTRL_DEINT_MASK)
32336#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK (0x8000U)
32337#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT (15U)
32338/*! GBL_ALPHA_EN - Global alpha value insertion enable
32339 * 0b0..Global Alpha value insertion is disabled
32340 * 0b1..Global Alpha value insertion is enabled
32341 */
32342#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN(x) \
32343 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_EN_MASK)
32344#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK (0xFF0000U)
32345#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT (16U)
32346/*! GBL_ALPHA_VAL - Global alpha value
32347 * 0b00000000-0b11111111..Alpha value to be inserted with all RGB pixels
32348 */
32349#define ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL(x) \
32350 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_SHIFT)) & ISI_CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK)
32351#define ISI_CHNL_IMG_CTRL_FORMAT_MASK (0x3F000000U)
32352#define ISI_CHNL_IMG_CTRL_FORMAT_SHIFT (24U)
32353/*! FORMAT - Output image format
32354 * 0b000000..RGBA8888 - RGB format with alpha in LSB; 8-bits per component. 'A' indicates alpha value.
32355 * 0b000001..ABGR8888 - BGR format with alpha in MSB; 8-bits per component. 'A' indicates alpha value.
32356 * 0b000010..ARGB8888 - RGB format with alpha in MSB; 8-bits per component. 'A' indicates alpha value.
32357 * 0b000011..RGBX888 - RGB format with 8-bits per color component (unpacked and MSB-alinged in 32-bit DWORD). 'X'
32358 * indicates the waste bits. 0b000100..XBGR888 - BGR format with 8-bits per color component (unpacked and LSB aligned in
32359 * 32-bit DWORD). 'X' indicates the waste bits. 0b000101..XRGB888 - RGB format with 8-bits per color component (unpacked
32360 * and LSB aligned in 32-bit DWORD). 'X' indicates the waste bits. 0b000110..RGB888P - RGB format with 8-bits per color
32361 * component (packed into 24-bits). No waste bits. 0b000111..BGR888P - BGR format with 8-bits per color component
32362 * (packed into 24-bits). No waste bits. 0b001000..A2BGR10 - BGR format with 2-bits alpha in MSB; 10-bits per color
32363 * component. 'A' indicates alpha value. 0b001001..A2RGB10 - RGB format with 2-bits alpha in MSB; 10-bits per color
32364 * component. 'A' indicates alpha value. 0b001010..RGB565 - RGB format with 5-bits of R, B; 6-bits of G (packed into
32365 * 16-bits WORD). No waste bits. 0b001011..RAW8 - 8-bit RAW data packed into 32-bit DWORD 0b001100..RAW10 - 10-bit RAW
32366 * data packed into 16-bit WORD with 6 LSBs waste bits 0b001101..RAW10P - 10-bit RAW data packed into 32-bit DWORD
32367 * 0b001110..RAW12 - 12-bit RAW data packed into 16-bit DWORD with 4 LSBs waste bits
32368 * 0b001111..RAW16 - 16-bit RAW data packed into 32-bit DWORD
32369 * 0b010000..YUV444_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes
32370 * 0b010001..YUV444_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes
32371 * 0b010010..YUV444_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes
32372 * 0b010011..YUV444_1P8 with 8-bits per color component; 1-plane YUV interleaved unpacked bytes (8 MSBs waste bits in
32373 * 32-bit DWORD) 0b010100..YUV444_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs
32374 * waste bits in 16-bit WORD) 0b010101..YUV444_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked
32375 * bytes (6 LSBs waste bits in 16-bit WORD) 0b010110..YUV444_3P10 with 10-bits per color component; 3-plane,
32376 * non-interleaved unpacked bytes (6 LSBs waste bits in 16-bit WORD) 0b010111..Reserved for future use
32377 * 0b011000..YUV444_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in
32378 * 32-bit DWORD) 0b011001..YUV444_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs
32379 * waste bits in 32-bit DWORD) 0b011010..YUV444_3P10P with 10-bits per color component; 3-plane, non-interleaved packed
32380 * bytes (2 MSBs waste bits in 32-bit DWORD) 0b011011..Reserved for future use 0b011100..YUV444_1P12 with 12-bits per
32381 * color component; 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD) 0b011101..YUV444_2P12
32382 * with 12-bits per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
32383 * 0b011110..YUV444_3P12 with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits
32384 * in 16-bit WORD) 0b011111..Reserved for future use 0b100000..YUV422_1P8P with 8-bits per color component; 1-plane, YUV
32385 * interleaved packed bytes 0b100001..YUV422_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes
32386 * 0b100010..YUV422_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes
32387 * 0b100011..Reserved for future use
32388 * 0b100100..YUV422_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits
32389 * in 16-bit WORD) 0b100101..YUV422_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6
32390 * LSBs waste bits in 16-bit WORD) 0b100110..YUV422_3P10 with 10-bits per color component; 3-plane, non-interleaved
32391 * unpacked bytes (6 LSBs waste bits in 16-bit WORD) 0b100111..Reserved for future use 0b101000..YUV422_1P10P with
32392 * 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
32393 * 0b101001..YUV422_2P10P with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in
32394 * 32-bit DWORD) 0b101010..YUV422_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs
32395 * waste bits in 32-bit DWORD) 0b101011..Reserved for future use 0b101100..YUV422_1P12 with 12-bits per color component;
32396 * 1-plane, YUV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD) 0b101101..YUV422_2P12 with 12-bits per
32397 * color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD) 0b101110..YUV422_3P12 with
32398 * 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
32399 * 0b101111..Reserved for future use
32400 * 0b110000..Reserved for future use
32401 * 0b110001..YUV420_2P8P with 8-bits per color component; 2-plane, UV interleaved packed bytes
32402 * 0b110010..YUV420_3P8P with 8-bits per color component; 3-plane, non-interleaved packed bytes
32403 * 0b110011..Reserved for future use
32404 * 0b110100..Reserved for future use
32405 * 0b110101..YUV420_2P10 with 10-bits per color component; 2-plane, UV interleaved unpacked bytes (6 LSBs waste bits in
32406 * 16-bit WORD) 0b110110..YUV420_3P10 with 10-bits per color component; 3-plane, non-interleaved unpacked bytes (6 LSBs
32407 * waste bits in 16-bit WORD) 0b110111..Reserved for future use 0b111000..Reserved for future use 0b111001..YUV420_2P10P
32408 * with 10-bits per color component; 2-plane, UV interleaved packed bytes (2 MSBs waste bits in 32-bit DWORD)
32409 * 0b111010..YUV420_3P10P with 10-bits per color component; 3-plane, non-interleaved packed bytes (2 MSBs waste bits in
32410 * 32-bit DWORD) 0b111011..Reserved for future use 0b111100..Reserved for future use 0b111101..YUV420_2P12 with 12-bits
32411 * per color component; 2-plane, UV interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD) 0b111110..YUV420_3P12
32412 * with 12-bits per color component; 3-plane, non-interleaved unpacked bytes (4 LSBs waste bits in 16-bit WORD)
32413 * 0b111111..Reserved for future use
32414 */
32415#define ISI_CHNL_IMG_CTRL_FORMAT(x) \
32416 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_FORMAT_SHIFT)) & ISI_CHNL_IMG_CTRL_FORMAT_MASK)
32417#define ISI_CHNL_IMG_CTRL_RSVD0_MASK (0xC0000000U)
32418#define ISI_CHNL_IMG_CTRL_RSVD0_SHIFT (30U)
32419#define ISI_CHNL_IMG_CTRL_RSVD0(x) \
32420 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CTRL_RSVD0_SHIFT)) & ISI_CHNL_IMG_CTRL_RSVD0_MASK)
32421/*! @} */
32422
32423/*! @name CHNL_OUT_BUF_CTRL - Channel Output Buffer Control Register */
32424/*! @{ */
32425#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_MASK (0xFU)
32426#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_SHIFT (0U)
32427/*! PANIC_SET_THD_Y - Overflow panic set threshold value for Y/RGB output buffer
32428 * 0b0000..No panic alert will be asserted
32429 * 0b0001-0b1111..Panic will assert when buffer is n * 6.25% full, where n = 1 to 15
32430 */
32431#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y(x) \
32432 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_SHIFT)) & \
32433 ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_Y_MASK)
32434#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_MASK (0xF00U)
32435#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_SHIFT (8U)
32436/*! PANIC_SET_THD_U - Overflow panic set threshold value for U output buffer
32437 * 0b0000..No panic alert will be asserted
32438 * 0b0001-0b1111..Panic will assert when buffer is n * 6.25% full, where n = 1 to 15
32439 */
32440#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U(x) \
32441 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_SHIFT)) & \
32442 ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_U_MASK)
32443#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK (0x4000U)
32444#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT (14U)
32445#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR(x) \
32446 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_SHIFT)) & \
32447 ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR_MASK)
32448#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK (0x8000U)
32449#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT (15U)
32450#define ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR(x) \
32451 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_SHIFT)) & \
32452 ISI_CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR_MASK)
32453#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_MASK (0xF0000U)
32454#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_SHIFT (16U)
32455/*! PANIC_SET_THD_V - Overflow panic set threshold value for V output buffer
32456 * 0b0000..No panic alert will be asserted
32457 * 0b0001-0b1111..Panic will assert when buffer is n * 6.25% full, where n = 1 to 15
32458 */
32459#define ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V(x) \
32460 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_SHIFT)) & \
32461 ISI_CHNL_OUT_BUF_CTRL_PANIC_SET_THD_V_MASK)
32462#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_MASK (0x40000000U)
32463#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_SHIFT (30U)
32464/*! MAX_WR_BEATS_UV - Maximum AXI write beats for U and V-buffers
32465 * 0b0..Maximum write beats per write request are 8 (i.e. 128 bytes)
32466 * 0b1..Maximum write beats per write request are 16 (i.e. 256 bytes)
32467 */
32468#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV(x) \
32469 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_SHIFT)) & \
32470 ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_UV_MASK)
32471#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_MASK (0x80000000U)
32472#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_SHIFT (31U)
32473/*! MAX_WR_BEATS_Y - Maximum AXI write beats for Y-buffer
32474 * 0b0..Maximum write beats per write request are 8 (i.e. 128 bytes)
32475 * 0b1..Maximum write beats per write request are 16 (i.e. 256 bytes)
32476 */
32477#define ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y(x) \
32478 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_SHIFT)) & \
32479 ISI_CHNL_OUT_BUF_CTRL_MAX_WR_BEATS_Y_MASK)
32480/*! @} */
32481
32482/*! @name CHNL_IMG_CFG - Channel Image Configuration */
32483/*! @{ */
32484#define ISI_CHNL_IMG_CFG_WIDTH_MASK (0x1FFFU)
32485#define ISI_CHNL_IMG_CFG_WIDTH_SHIFT (0U)
32486#define ISI_CHNL_IMG_CFG_WIDTH(x) \
32487 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_IMG_CFG_WIDTH_MASK)
32488#define ISI_CHNL_IMG_CFG_RSVD0_MASK (0xE000U)
32489#define ISI_CHNL_IMG_CFG_RSVD0_SHIFT (13U)
32490#define ISI_CHNL_IMG_CFG_RSVD0(x) \
32491 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_RSVD0_SHIFT)) & ISI_CHNL_IMG_CFG_RSVD0_MASK)
32492#define ISI_CHNL_IMG_CFG_HEIGHT_MASK (0x1FFF0000U)
32493#define ISI_CHNL_IMG_CFG_HEIGHT_SHIFT (16U)
32494#define ISI_CHNL_IMG_CFG_HEIGHT(x) \
32495 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_IMG_CFG_HEIGHT_MASK)
32496#define ISI_CHNL_IMG_CFG_RSVD1_MASK (0xE0000000U)
32497#define ISI_CHNL_IMG_CFG_RSVD1_SHIFT (29U)
32498#define ISI_CHNL_IMG_CFG_RSVD1(x) \
32499 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IMG_CFG_RSVD1_SHIFT)) & ISI_CHNL_IMG_CFG_RSVD1_MASK)
32500/*! @} */
32501
32502/*! @name CHNL_IER - Channel Interrupt Enable Register */
32503/*! @{ */
32504#define ISI_CHNL_IER_RSVD0_MASK (0xFFFFU)
32505#define ISI_CHNL_IER_RSVD0_SHIFT (0U)
32506#define ISI_CHNL_IER_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_RSVD0_SHIFT)) & ISI_CHNL_IER_RSVD0_MASK)
32507#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK (0x10000U)
32508#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT (16U)
32509/*! LATE_VSYNC_ERR_EN - VSYNC timing (Late) error interrupt enable bit
32510 * 0b0..Interrupt is disabled
32511 * 0b1..Interrupt is enabled
32512 */
32513#define ISI_CHNL_IER_LATE_VSYNC_ERR_EN(x) \
32514 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LATE_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_LATE_VSYNC_ERR_EN_MASK)
32515#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK (0x20000U)
32516#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT (17U)
32517/*! EARLY_VSYNC_ERR_EN - VSYNC timing (Early) error interrupt enable bit
32518 * 0b0..Interrupt is disabled
32519 * 0b1..Interrupt is enabled
32520 */
32521#define ISI_CHNL_IER_EARLY_VSYNC_ERR_EN(x) \
32522 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_SHIFT)) & ISI_CHNL_IER_EARLY_VSYNC_ERR_EN_MASK)
32523#define ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK (0x80000U)
32524#define ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT (19U)
32525/*! OFLW_Y_BUF_EN - Y output buffer overflow interrupt enable bit
32526 * 0b0..Interrupt is disabled
32527 * 0b1..Interrupt is enabled
32528 */
32529#define ISI_CHNL_IER_OFLW_Y_BUF_EN(x) \
32530 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_Y_BUF_EN_MASK)
32531#define ISI_CHNL_IER_PANIC_Y_BUF_EN_MASK (0x100000U)
32532#define ISI_CHNL_IER_PANIC_Y_BUF_EN_SHIFT (20U)
32533/*! PANIC_Y_BUF_EN - Y output buffer potential overflow panic interrupt enable bit
32534 * 0b0..Interrupt is disabled
32535 * 0b1..Interrupt is enabled
32536 */
32537#define ISI_CHNL_IER_PANIC_Y_BUF_EN(x) \
32538 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_Y_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_Y_BUF_EN_MASK)
32539#define ISI_CHNL_IER_OFLW_U_BUF_EN_MASK (0x200000U)
32540#define ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT (21U)
32541/*! OFLW_U_BUF_EN - U output buffer overflow interrupt enable bit
32542 * 0b0..Interrupt is disabled
32543 * 0b1..Interrupt is enabled
32544 */
32545#define ISI_CHNL_IER_OFLW_U_BUF_EN(x) \
32546 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_U_BUF_EN_MASK)
32547#define ISI_CHNL_IER_PANIC_U_BUF_EN_MASK (0x400000U)
32548#define ISI_CHNL_IER_PANIC_U_BUF_EN_SHIFT (22U)
32549/*! PANIC_U_BUF_EN - U output buffer potential overflow panic interrupt enable bit
32550 * 0b0..Interrupt is disabled
32551 * 0b1..Interrupt is enabled
32552 */
32553#define ISI_CHNL_IER_PANIC_U_BUF_EN(x) \
32554 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_U_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_U_BUF_EN_MASK)
32555#define ISI_CHNL_IER_OFLW_V_BUF_EN_MASK (0x800000U)
32556#define ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT (23U)
32557/*! OFLW_V_BUF_EN - V output buffer overflow interrupt enable bit
32558 * 0b0..Interrupt is disabled
32559 * 0b1..Interrupt is enabled
32560 */
32561#define ISI_CHNL_IER_OFLW_V_BUF_EN(x) \
32562 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_OFLW_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_OFLW_V_BUF_EN_MASK)
32563#define ISI_CHNL_IER_PANIC_V_BUF_EN_MASK (0x1000000U)
32564#define ISI_CHNL_IER_PANIC_V_BUF_EN_SHIFT (24U)
32565/*! PANIC_V_BUF_EN - V output buffer potential overflow panic interrupt enable bit
32566 * 0b0..Interrupt is disabled
32567 * 0b1..Interrupt is enabled
32568 */
32569#define ISI_CHNL_IER_PANIC_V_BUF_EN(x) \
32570 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_PANIC_V_BUF_EN_SHIFT)) & ISI_CHNL_IER_PANIC_V_BUF_EN_MASK)
32571#define ISI_CHNL_IER_AXI_RD_ERR_EN_MASK (0x2000000U)
32572#define ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT (25U)
32573/*! AXI_RD_ERR_EN - AXI bus read error interrupt enable bit
32574 * 0b0..Interrupt is disabled
32575 * 0b1..Interrupt is enabled
32576 */
32577#define ISI_CHNL_IER_AXI_RD_ERR_EN(x) \
32578 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_RD_ERR_EN_SHIFT)) & ISI_CHNL_IER_AXI_RD_ERR_EN_MASK)
32579#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK (0x4000000U)
32580#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT (26U)
32581/*! AXI_WR_ERR_Y_EN - AXI bus read error interrupt enable bit for Y/RGB data buffer
32582 * 0b0..Interrupt is disabled
32583 * 0b1..Interrupt is enabled
32584 */
32585#define ISI_CHNL_IER_AXI_WR_ERR_Y_EN(x) \
32586 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_Y_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_Y_EN_MASK)
32587#define ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK (0x8000000U)
32588#define ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT (27U)
32589/*! AXI_WR_ERR_U_EN - AXI bus read error interrupt enable bit for U data buffer
32590 * 0b0..Interrupt is disabled
32591 * 0b1..Interrupt is enabled
32592 */
32593#define ISI_CHNL_IER_AXI_WR_ERR_U_EN(x) \
32594 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_U_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_U_EN_MASK)
32595#define ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK (0x10000000U)
32596#define ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT (28U)
32597/*! AXI_WR_ERR_V_EN - AXI bus read error interrupt enable bit for V data buffer
32598 * 0b0..Interrupt is disabled
32599 * 0b1..Interrupt is enabled
32600 */
32601#define ISI_CHNL_IER_AXI_WR_ERR_V_EN(x) \
32602 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_AXI_WR_ERR_V_EN_SHIFT)) & ISI_CHNL_IER_AXI_WR_ERR_V_EN_MASK)
32603#define ISI_CHNL_IER_FRM_RCVD_EN_MASK (0x20000000U)
32604#define ISI_CHNL_IER_FRM_RCVD_EN_SHIFT (29U)
32605/*! FRM_RCVD_EN - Frame received interrupt enable bit
32606 * 0b0..Interrupt is disabled
32607 * 0b1..Interrupt is enabled
32608 */
32609#define ISI_CHNL_IER_FRM_RCVD_EN(x) \
32610 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_FRM_RCVD_EN_SHIFT)) & ISI_CHNL_IER_FRM_RCVD_EN_MASK)
32611#define ISI_CHNL_IER_LINE_RCVD_EN_MASK (0x40000000U)
32612#define ISI_CHNL_IER_LINE_RCVD_EN_SHIFT (30U)
32613/*! LINE_RCVD_EN - Line received interrupt enable bit
32614 * 0b0..Interrupt is disabled
32615 * 0b1..Interrupt is enabled
32616 */
32617#define ISI_CHNL_IER_LINE_RCVD_EN(x) \
32618 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_LINE_RCVD_EN_SHIFT)) & ISI_CHNL_IER_LINE_RCVD_EN_MASK)
32619#define ISI_CHNL_IER_MEM_RD_DONE_EN_MASK (0x80000000U)
32620#define ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT (31U)
32621/*! MEM_RD_DONE_EN - Memory read complete interrupt enable bit
32622 * 0b0..Interrupt is disabled
32623 * 0b1..Interrupt is enabled
32624 */
32625#define ISI_CHNL_IER_MEM_RD_DONE_EN(x) \
32626 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IER_MEM_RD_DONE_EN_SHIFT)) & ISI_CHNL_IER_MEM_RD_DONE_EN_MASK)
32627/*! @} */
32628
32629/*! @name CHNL_STS - Channel Status Register */
32630/*! @{ */
32631#define ISI_CHNL_STS_BUF1_ACTIVE_MASK (0x100U)
32632#define ISI_CHNL_STS_BUF1_ACTIVE_SHIFT (8U)
32633/*! BUF1_ACTIVE - Current frame being stored in Buffer 1 Address
32634 * 0b0..Buffer 1 Address inactive
32635 * 0b1..Buffer 1 Address in use
32636 */
32637#define ISI_CHNL_STS_BUF1_ACTIVE(x) \
32638 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF1_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF1_ACTIVE_MASK)
32639#define ISI_CHNL_STS_BUF2_ACTIVE_MASK (0x200U)
32640#define ISI_CHNL_STS_BUF2_ACTIVE_SHIFT (9U)
32641/*! BUF2_ACTIVE - Current frame being stored in Buffer 2 Address
32642 * 0b0..Buffer 2 Address inactive
32643 * 0b1..Buffer 2 Address in use
32644 */
32645#define ISI_CHNL_STS_BUF2_ACTIVE(x) \
32646 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_BUF2_ACTIVE_SHIFT)) & ISI_CHNL_STS_BUF2_ACTIVE_MASK)
32647#define ISI_CHNL_STS_MEM_RD_OFLOW_MASK (0x400U)
32648#define ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT (10U)
32649/*! MEM_RD_OFLOW - Memory read FIFO overflow error status
32650 * 0b0..No overflow occurred during memory read
32651 * 0b1..FIFO overflow occurred during memory read
32652 */
32653#define ISI_CHNL_STS_MEM_RD_OFLOW(x) \
32654 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_OFLOW_SHIFT)) & ISI_CHNL_STS_MEM_RD_OFLOW_MASK)
32655#define ISI_CHNL_STS_RSVD1_MASK (0xF800U)
32656#define ISI_CHNL_STS_RSVD1_SHIFT (11U)
32657#define ISI_CHNL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_RSVD1_SHIFT)) & ISI_CHNL_STS_RSVD1_MASK)
32658#define ISI_CHNL_STS_LATE_VSYNC_ERR_MASK (0x10000U)
32659#define ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT (16U)
32660/*! LATE_VSYNC_ERR - VSYNC timing (Late) error interrupt flag
32661 * 0b0..No error
32662 * 0b1..VSYNC detected later than expected
32663 */
32664#define ISI_CHNL_STS_LATE_VSYNC_ERR(x) \
32665 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LATE_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_LATE_VSYNC_ERR_MASK)
32666#define ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK (0x20000U)
32667#define ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT (17U)
32668/*! EARLY_VSYNC_ERR - VSYNC timing (Early) error interrupt flag
32669 * 0b0..No error
32670 * 0b1..VSYNC detected earlier than expected
32671 */
32672#define ISI_CHNL_STS_EARLY_VSYNC_ERR(x) \
32673 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_EARLY_VSYNC_ERR_SHIFT)) & ISI_CHNL_STS_EARLY_VSYNC_ERR_MASK)
32674#define ISI_CHNL_STS_OFLW_Y_BUF_MASK (0x40000U)
32675#define ISI_CHNL_STS_OFLW_Y_BUF_SHIFT (18U)
32676/*! OFLW_Y_BUF - Overflow in Y/RGB output buffer interrupt flag
32677 * 0b0..No overflow
32678 * 0b1..Overflow has occured in the channel
32679 */
32680#define ISI_CHNL_STS_OFLW_Y_BUF(x) \
32681 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_Y_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_Y_BUF_MASK)
32682#define ISI_CHNL_STS_PANIC_Y_BUF_MASK (0x80000U)
32683#define ISI_CHNL_STS_PANIC_Y_BUF_SHIFT (19U)
32684/*! PANIC_Y_BUF - Y/RGB output buffer potential overflow panic alert interrupt flag
32685 * 0b0..Buffer has not crossed the panic threshold limit
32686 * 0b1..Panic threshold limit crossed. Software must take action.
32687 */
32688#define ISI_CHNL_STS_PANIC_Y_BUF(x) \
32689 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_Y_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_Y_BUF_MASK)
32690#define ISI_CHNL_STS_OFLW_U_BUF_MASK (0x100000U)
32691#define ISI_CHNL_STS_OFLW_U_BUF_SHIFT (20U)
32692/*! OFLW_U_BUF - Overflow in U output buffer interrupt flag
32693 * 0b0..No overflow
32694 * 0b1..Overflow has occured in the channel
32695 */
32696#define ISI_CHNL_STS_OFLW_U_BUF(x) \
32697 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_U_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_U_BUF_MASK)
32698#define ISI_CHNL_STS_PANIC_U_BUF_MASK (0x200000U)
32699#define ISI_CHNL_STS_PANIC_U_BUF_SHIFT (21U)
32700/*! PANIC_U_BUF - U output buffer potential overflow panic alert interrupt flag
32701 * 0b0..Buffer has not crossed the panic threshold limit
32702 * 0b1..Panic threshold limit crossed. Software must take action.
32703 */
32704#define ISI_CHNL_STS_PANIC_U_BUF(x) \
32705 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_U_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_U_BUF_MASK)
32706#define ISI_CHNL_STS_OFLW_V_BUF_MASK (0x400000U)
32707#define ISI_CHNL_STS_OFLW_V_BUF_SHIFT (22U)
32708/*! OFLW_V_BUF - Overflow in U output buffer interrupt flag
32709 * 0b0..No overflow
32710 * 0b1..Overflow has occured in the channel
32711 */
32712#define ISI_CHNL_STS_OFLW_V_BUF(x) \
32713 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_OFLW_V_BUF_SHIFT)) & ISI_CHNL_STS_OFLW_V_BUF_MASK)
32714#define ISI_CHNL_STS_PANIC_V_BUF_MASK (0x800000U)
32715#define ISI_CHNL_STS_PANIC_V_BUF_SHIFT (23U)
32716/*! PANIC_V_BUF - V output buffer potential overflow panic alert interrupt flag
32717 * 0b0..Buffer has not crossed the panic threshold limit
32718 * 0b1..Panic threshold limit crossed. Software must take action.
32719 */
32720#define ISI_CHNL_STS_PANIC_V_BUF(x) \
32721 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_PANIC_V_BUF_SHIFT)) & ISI_CHNL_STS_PANIC_V_BUF_MASK)
32722#define ISI_CHNL_STS_AXI_RD_ERR_MASK (0x2000000U)
32723#define ISI_CHNL_STS_AXI_RD_ERR_SHIFT (25U)
32724/*! AXI_RD_ERR - AXI Bus read error interrupt flag
32725 * 0b0..No error
32726 * 0b1..Error occured during read
32727 */
32728#define ISI_CHNL_STS_AXI_RD_ERR(x) \
32729 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_RD_ERR_SHIFT)) & ISI_CHNL_STS_AXI_RD_ERR_MASK)
32730#define ISI_CHNL_STS_AXI_WR_ERR_Y_MASK (0x4000000U)
32731#define ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT (26U)
32732/*! AXI_WR_ERR_Y - AXI Bus write error interrupt flag for Y/RGB data buffer
32733 * 0b0..No error
32734 * 0b1..Error occured during write
32735 */
32736#define ISI_CHNL_STS_AXI_WR_ERR_Y(x) \
32737 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_Y_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_Y_MASK)
32738#define ISI_CHNL_STS_AXI_WR_ERR_U_MASK (0x8000000U)
32739#define ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT (27U)
32740/*! AXI_WR_ERR_U - AXI Bus write error interrupt flag for U data buffer
32741 * 0b0..No error
32742 * 0b1..Error occured during write
32743 */
32744#define ISI_CHNL_STS_AXI_WR_ERR_U(x) \
32745 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_U_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_U_MASK)
32746#define ISI_CHNL_STS_AXI_WR_ERR_V_MASK (0x10000000U)
32747#define ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT (28U)
32748/*! AXI_WR_ERR_V - AXI Bus write error interrupt flag for V data buffer
32749 * 0b0..No error
32750 * 0b1..Error occured during write
32751 */
32752#define ISI_CHNL_STS_AXI_WR_ERR_V(x) \
32753 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_AXI_WR_ERR_V_SHIFT)) & ISI_CHNL_STS_AXI_WR_ERR_V_MASK)
32754#define ISI_CHNL_STS_FRM_STRD_MASK (0x20000000U)
32755#define ISI_CHNL_STS_FRM_STRD_SHIFT (29U)
32756/*! FRM_STRD - Frame stored successfully interrupt flag
32757 * 0b0..No frame being received or in progress
32758 * 0b1..One full frame has been received and stored in memory
32759 */
32760#define ISI_CHNL_STS_FRM_STRD(x) \
32761 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_FRM_STRD_SHIFT)) & ISI_CHNL_STS_FRM_STRD_MASK)
32762#define ISI_CHNL_STS_LINE_STRD_MASK (0x40000000U)
32763#define ISI_CHNL_STS_LINE_STRD_SHIFT (30U)
32764/*! LINE_STRD - Line received and stored interrupt flag
32765 * 0b0..No new line received
32766 * 0b1..New line received and stored into memory
32767 */
32768#define ISI_CHNL_STS_LINE_STRD(x) \
32769 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_LINE_STRD_SHIFT)) & ISI_CHNL_STS_LINE_STRD_MASK)
32770#define ISI_CHNL_STS_MEM_RD_DONE_MASK (0x80000000U)
32771#define ISI_CHNL_STS_MEM_RD_DONE_SHIFT (31U)
32772/*! MEM_RD_DONE - Memory read complete interrupt flag
32773 * 0b0..Image read from memory not complete or not started
32774 * 0b1..Image read from memory completed
32775 */
32776#define ISI_CHNL_STS_MEM_RD_DONE(x) \
32777 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_STS_MEM_RD_DONE_SHIFT)) & ISI_CHNL_STS_MEM_RD_DONE_MASK)
32778/*! @} */
32779
32780/*! @name CHNL_SCALE_FACTOR - Channel Scale Factor Register */
32781/*! @{ */
32782#define ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK (0x3FFFU)
32783#define ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT (0U)
32784#define ISI_CHNL_SCALE_FACTOR_X_SCALE(x) \
32785 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_X_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_X_SCALE_MASK)
32786#define ISI_CHNL_SCALE_FACTOR_RSVD1_MASK (0xC000U)
32787#define ISI_CHNL_SCALE_FACTOR_RSVD1_SHIFT (14U)
32788#define ISI_CHNL_SCALE_FACTOR_RSVD1(x) \
32789 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_RSVD1_SHIFT)) & ISI_CHNL_SCALE_FACTOR_RSVD1_MASK)
32790#define ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK (0x3FFF0000U)
32791#define ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT (16U)
32792#define ISI_CHNL_SCALE_FACTOR_Y_SCALE(x) \
32793 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_Y_SCALE_SHIFT)) & ISI_CHNL_SCALE_FACTOR_Y_SCALE_MASK)
32794#define ISI_CHNL_SCALE_FACTOR_RSVD0_MASK (0xC0000000U)
32795#define ISI_CHNL_SCALE_FACTOR_RSVD0_SHIFT (30U)
32796#define ISI_CHNL_SCALE_FACTOR_RSVD0(x) \
32797 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_FACTOR_RSVD0_SHIFT)) & ISI_CHNL_SCALE_FACTOR_RSVD0_MASK)
32798/*! @} */
32799
32800/*! @name CHNL_SCALE_OFFSET - Channel Scale Offset Register */
32801/*! @{ */
32802#define ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK (0xFFFU)
32803#define ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT (0U)
32804#define ISI_CHNL_SCALE_OFFSET_X_OFFSET(x) \
32805 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_X_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_X_OFFSET_MASK)
32806#define ISI_CHNL_SCALE_OFFSET_RSVD1_MASK (0xF000U)
32807#define ISI_CHNL_SCALE_OFFSET_RSVD1_SHIFT (12U)
32808#define ISI_CHNL_SCALE_OFFSET_RSVD1(x) \
32809 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_RSVD1_SHIFT)) & ISI_CHNL_SCALE_OFFSET_RSVD1_MASK)
32810#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK (0xFFF0000U)
32811#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT (16U)
32812#define ISI_CHNL_SCALE_OFFSET_Y_OFFSET(x) \
32813 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_Y_OFFSET_SHIFT)) & ISI_CHNL_SCALE_OFFSET_Y_OFFSET_MASK)
32814#define ISI_CHNL_SCALE_OFFSET_RSVD0_MASK (0xF0000000U)
32815#define ISI_CHNL_SCALE_OFFSET_RSVD0_SHIFT (28U)
32816#define ISI_CHNL_SCALE_OFFSET_RSVD0(x) \
32817 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCALE_OFFSET_RSVD0_SHIFT)) & ISI_CHNL_SCALE_OFFSET_RSVD0_MASK)
32818/*! @} */
32819
32820/*! @name CHNL_CROP_ULC - Channel Crop Upper Left Corner Coordinate Register */
32821/*! @{ */
32822#define ISI_CHNL_CROP_ULC_Y_MASK (0xFFFU)
32823#define ISI_CHNL_CROP_ULC_Y_SHIFT (0U)
32824#define ISI_CHNL_CROP_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_Y_SHIFT)) & ISI_CHNL_CROP_ULC_Y_MASK)
32825#define ISI_CHNL_CROP_ULC_RSVD1_MASK (0xF000U)
32826#define ISI_CHNL_CROP_ULC_RSVD1_SHIFT (12U)
32827#define ISI_CHNL_CROP_ULC_RSVD1(x) \
32828 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_RSVD1_SHIFT)) & ISI_CHNL_CROP_ULC_RSVD1_MASK)
32829#define ISI_CHNL_CROP_ULC_X_MASK (0xFFF0000U)
32830#define ISI_CHNL_CROP_ULC_X_SHIFT (16U)
32831#define ISI_CHNL_CROP_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_X_SHIFT)) & ISI_CHNL_CROP_ULC_X_MASK)
32832#define ISI_CHNL_CROP_ULC_RSVD0_MASK (0xF0000000U)
32833#define ISI_CHNL_CROP_ULC_RSVD0_SHIFT (28U)
32834#define ISI_CHNL_CROP_ULC_RSVD0(x) \
32835 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_ULC_RSVD0_SHIFT)) & ISI_CHNL_CROP_ULC_RSVD0_MASK)
32836/*! @} */
32837
32838/*! @name CHNL_CROP_LRC - Channel Crop Lower Right Corner Coordinate Register */
32839/*! @{ */
32840#define ISI_CHNL_CROP_LRC_Y_MASK (0xFFFU)
32841#define ISI_CHNL_CROP_LRC_Y_SHIFT (0U)
32842#define ISI_CHNL_CROP_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_Y_SHIFT)) & ISI_CHNL_CROP_LRC_Y_MASK)
32843#define ISI_CHNL_CROP_LRC_RSVD1_MASK (0xF000U)
32844#define ISI_CHNL_CROP_LRC_RSVD1_SHIFT (12U)
32845#define ISI_CHNL_CROP_LRC_RSVD1(x) \
32846 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_RSVD1_SHIFT)) & ISI_CHNL_CROP_LRC_RSVD1_MASK)
32847#define ISI_CHNL_CROP_LRC_X_MASK (0xFFF0000U)
32848#define ISI_CHNL_CROP_LRC_X_SHIFT (16U)
32849#define ISI_CHNL_CROP_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_X_SHIFT)) & ISI_CHNL_CROP_LRC_X_MASK)
32850#define ISI_CHNL_CROP_LRC_RSVD0_MASK (0xF0000000U)
32851#define ISI_CHNL_CROP_LRC_RSVD0_SHIFT (28U)
32852#define ISI_CHNL_CROP_LRC_RSVD0(x) \
32853 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CROP_LRC_RSVD0_SHIFT)) & ISI_CHNL_CROP_LRC_RSVD0_MASK)
32854/*! @} */
32855
32856/*! @name CHNL_CSC_COEFF0 - Channel Color Space Conversion Coefficient Register 0 */
32857/*! @{ */
32858#define ISI_CHNL_CSC_COEFF0_A1_MASK (0x7FFU)
32859#define ISI_CHNL_CSC_COEFF0_A1_SHIFT (0U)
32860#define ISI_CHNL_CSC_COEFF0_A1(x) \
32861 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A1_SHIFT)) & ISI_CHNL_CSC_COEFF0_A1_MASK)
32862#define ISI_CHNL_CSC_COEFF0_RSVD1_MASK (0xF800U)
32863#define ISI_CHNL_CSC_COEFF0_RSVD1_SHIFT (11U)
32864#define ISI_CHNL_CSC_COEFF0_RSVD1(x) \
32865 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF0_RSVD1_MASK)
32866#define ISI_CHNL_CSC_COEFF0_A2_MASK (0x7FF0000U)
32867#define ISI_CHNL_CSC_COEFF0_A2_SHIFT (16U)
32868#define ISI_CHNL_CSC_COEFF0_A2(x) \
32869 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_A2_SHIFT)) & ISI_CHNL_CSC_COEFF0_A2_MASK)
32870#define ISI_CHNL_CSC_COEFF0_RSVD0_MASK (0xF8000000U)
32871#define ISI_CHNL_CSC_COEFF0_RSVD0_SHIFT (27U)
32872#define ISI_CHNL_CSC_COEFF0_RSVD0(x) \
32873 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF0_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF0_RSVD0_MASK)
32874/*! @} */
32875
32876/*! @name CHNL_CSC_COEFF1 - Channel Color Space Conversion Coefficient Register 1 */
32877/*! @{ */
32878#define ISI_CHNL_CSC_COEFF1_A3_MASK (0x7FFU)
32879#define ISI_CHNL_CSC_COEFF1_A3_SHIFT (0U)
32880#define ISI_CHNL_CSC_COEFF1_A3(x) \
32881 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_A3_SHIFT)) & ISI_CHNL_CSC_COEFF1_A3_MASK)
32882#define ISI_CHNL_CSC_COEFF1_RSVD1_MASK (0xF800U)
32883#define ISI_CHNL_CSC_COEFF1_RSVD1_SHIFT (11U)
32884#define ISI_CHNL_CSC_COEFF1_RSVD1(x) \
32885 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF1_RSVD1_MASK)
32886#define ISI_CHNL_CSC_COEFF1_B1_MASK (0x7FF0000U)
32887#define ISI_CHNL_CSC_COEFF1_B1_SHIFT (16U)
32888#define ISI_CHNL_CSC_COEFF1_B1(x) \
32889 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_B1_SHIFT)) & ISI_CHNL_CSC_COEFF1_B1_MASK)
32890#define ISI_CHNL_CSC_COEFF1_RSVD0_MASK (0xF8000000U)
32891#define ISI_CHNL_CSC_COEFF1_RSVD0_SHIFT (27U)
32892#define ISI_CHNL_CSC_COEFF1_RSVD0(x) \
32893 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF1_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF1_RSVD0_MASK)
32894/*! @} */
32895
32896/*! @name CHNL_CSC_COEFF2 - Channel Color Space Conversion Coefficient Register 2 */
32897/*! @{ */
32898#define ISI_CHNL_CSC_COEFF2_B2_MASK (0x7FFU)
32899#define ISI_CHNL_CSC_COEFF2_B2_SHIFT (0U)
32900#define ISI_CHNL_CSC_COEFF2_B2(x) \
32901 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B2_SHIFT)) & ISI_CHNL_CSC_COEFF2_B2_MASK)
32902#define ISI_CHNL_CSC_COEFF2_RSVD1_MASK (0xF800U)
32903#define ISI_CHNL_CSC_COEFF2_RSVD1_SHIFT (11U)
32904#define ISI_CHNL_CSC_COEFF2_RSVD1(x) \
32905 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF2_RSVD1_MASK)
32906#define ISI_CHNL_CSC_COEFF2_B3_MASK (0x7FF0000U)
32907#define ISI_CHNL_CSC_COEFF2_B3_SHIFT (16U)
32908#define ISI_CHNL_CSC_COEFF2_B3(x) \
32909 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_B3_SHIFT)) & ISI_CHNL_CSC_COEFF2_B3_MASK)
32910#define ISI_CHNL_CSC_COEFF2_RSVD0_MASK (0xF8000000U)
32911#define ISI_CHNL_CSC_COEFF2_RSVD0_SHIFT (27U)
32912#define ISI_CHNL_CSC_COEFF2_RSVD0(x) \
32913 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF2_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF2_RSVD0_MASK)
32914/*! @} */
32915
32916/*! @name CHNL_CSC_COEFF3 - Channel Color Space Conversion Coefficient Register 3 */
32917/*! @{ */
32918#define ISI_CHNL_CSC_COEFF3_C1_MASK (0x7FFU)
32919#define ISI_CHNL_CSC_COEFF3_C1_SHIFT (0U)
32920#define ISI_CHNL_CSC_COEFF3_C1(x) \
32921 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C1_SHIFT)) & ISI_CHNL_CSC_COEFF3_C1_MASK)
32922#define ISI_CHNL_CSC_COEFF3_RSVD1_MASK (0xF800U)
32923#define ISI_CHNL_CSC_COEFF3_RSVD1_SHIFT (11U)
32924#define ISI_CHNL_CSC_COEFF3_RSVD1(x) \
32925 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF3_RSVD1_MASK)
32926#define ISI_CHNL_CSC_COEFF3_C2_MASK (0x7FF0000U)
32927#define ISI_CHNL_CSC_COEFF3_C2_SHIFT (16U)
32928#define ISI_CHNL_CSC_COEFF3_C2(x) \
32929 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_C2_SHIFT)) & ISI_CHNL_CSC_COEFF3_C2_MASK)
32930#define ISI_CHNL_CSC_COEFF3_RSVD0_MASK (0xF8000000U)
32931#define ISI_CHNL_CSC_COEFF3_RSVD0_SHIFT (27U)
32932#define ISI_CHNL_CSC_COEFF3_RSVD0(x) \
32933 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF3_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF3_RSVD0_MASK)
32934/*! @} */
32935
32936/*! @name CHNL_CSC_COEFF4 - Channel Color Space Conversion Coefficient Register 4 */
32937/*! @{ */
32938#define ISI_CHNL_CSC_COEFF4_C3_MASK (0x7FFU)
32939#define ISI_CHNL_CSC_COEFF4_C3_SHIFT (0U)
32940#define ISI_CHNL_CSC_COEFF4_C3(x) \
32941 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_C3_SHIFT)) & ISI_CHNL_CSC_COEFF4_C3_MASK)
32942#define ISI_CHNL_CSC_COEFF4_RSVD1_MASK (0xF800U)
32943#define ISI_CHNL_CSC_COEFF4_RSVD1_SHIFT (11U)
32944#define ISI_CHNL_CSC_COEFF4_RSVD1(x) \
32945 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF4_RSVD1_MASK)
32946#define ISI_CHNL_CSC_COEFF4_D1_MASK (0x1FF0000U)
32947#define ISI_CHNL_CSC_COEFF4_D1_SHIFT (16U)
32948#define ISI_CHNL_CSC_COEFF4_D1(x) \
32949 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_D1_SHIFT)) & ISI_CHNL_CSC_COEFF4_D1_MASK)
32950#define ISI_CHNL_CSC_COEFF4_RSVD0_MASK (0xFE000000U)
32951#define ISI_CHNL_CSC_COEFF4_RSVD0_SHIFT (25U)
32952#define ISI_CHNL_CSC_COEFF4_RSVD0(x) \
32953 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF4_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF4_RSVD0_MASK)
32954/*! @} */
32955
32956/*! @name CHNL_CSC_COEFF5 - Channel Color Space Conversion Coefficient Register 5 */
32957/*! @{ */
32958#define ISI_CHNL_CSC_COEFF5_D2_MASK (0x1FFU)
32959#define ISI_CHNL_CSC_COEFF5_D2_SHIFT (0U)
32960#define ISI_CHNL_CSC_COEFF5_D2(x) \
32961 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D2_SHIFT)) & ISI_CHNL_CSC_COEFF5_D2_MASK)
32962#define ISI_CHNL_CSC_COEFF5_RSVD1_MASK (0xFE00U)
32963#define ISI_CHNL_CSC_COEFF5_RSVD1_SHIFT (9U)
32964#define ISI_CHNL_CSC_COEFF5_RSVD1(x) \
32965 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_RSVD1_SHIFT)) & ISI_CHNL_CSC_COEFF5_RSVD1_MASK)
32966#define ISI_CHNL_CSC_COEFF5_D3_MASK (0x1FF0000U)
32967#define ISI_CHNL_CSC_COEFF5_D3_SHIFT (16U)
32968#define ISI_CHNL_CSC_COEFF5_D3(x) \
32969 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_D3_SHIFT)) & ISI_CHNL_CSC_COEFF5_D3_MASK)
32970#define ISI_CHNL_CSC_COEFF5_RSVD0_MASK (0xFE000000U)
32971#define ISI_CHNL_CSC_COEFF5_RSVD0_SHIFT (25U)
32972#define ISI_CHNL_CSC_COEFF5_RSVD0(x) \
32973 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_CSC_COEFF5_RSVD0_SHIFT)) & ISI_CHNL_CSC_COEFF5_RSVD0_MASK)
32974/*! @} */
32975
32976/*! @name CHNL_ROI_0_ALPHA - Channel Alpha Value Register for Region of Interest 0 */
32977/*! @{ */
32978#define ISI_CHNL_ROI_0_ALPHA_RSVD1_MASK (0xFFFFU)
32979#define ISI_CHNL_ROI_0_ALPHA_RSVD1_SHIFT (0U)
32980#define ISI_CHNL_ROI_0_ALPHA_RSVD1(x) \
32981 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ALPHA_RSVD1_SHIFT)) & ISI_CHNL_ROI_0_ALPHA_RSVD1_MASK)
32982#define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_MASK (0x10000U)
32983#define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_SHIFT (16U)
32984/*! ALPHA_EN - Alpha value insertion enable
32985 * 0b0..Alpha value insertion is disabled
32986 * 0b1..Alpha value insertion is enabled
32987 */
32988#define ISI_CHNL_ROI_0_ALPHA_ALPHA_EN(x) \
32989 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_0_ALPHA_ALPHA_EN_MASK)
32990#define ISI_CHNL_ROI_0_ALPHA_RSVD0_MASK (0xFE0000U)
32991#define ISI_CHNL_ROI_0_ALPHA_RSVD0_SHIFT (17U)
32992#define ISI_CHNL_ROI_0_ALPHA_RSVD0(x) \
32993 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ALPHA_RSVD0_SHIFT)) & ISI_CHNL_ROI_0_ALPHA_RSVD0_MASK)
32994#define ISI_CHNL_ROI_0_ALPHA_ALPHA_MASK (0xFF000000U)
32995#define ISI_CHNL_ROI_0_ALPHA_ALPHA_SHIFT (24U)
32996#define ISI_CHNL_ROI_0_ALPHA_ALPHA(x) \
32997 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_0_ALPHA_ALPHA_MASK)
32998/*! @} */
32999
33000/*! @name CHNL_ROI_0_ULC - Channel Upper Left Coordinate Register for Region of Interest 0 */
33001/*! @{ */
33002#define ISI_CHNL_ROI_0_ULC_Y_MASK (0xFFFU)
33003#define ISI_CHNL_ROI_0_ULC_Y_SHIFT (0U)
33004#define ISI_CHNL_ROI_0_ULC_Y(x) \
33005 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ULC_Y_SHIFT)) & ISI_CHNL_ROI_0_ULC_Y_MASK)
33006#define ISI_CHNL_ROI_0_ULC_RSVD1_MASK (0xF000U)
33007#define ISI_CHNL_ROI_0_ULC_RSVD1_SHIFT (12U)
33008#define ISI_CHNL_ROI_0_ULC_RSVD1(x) \
33009 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ULC_RSVD1_SHIFT)) & ISI_CHNL_ROI_0_ULC_RSVD1_MASK)
33010#define ISI_CHNL_ROI_0_ULC_X_MASK (0xFFF0000U)
33011#define ISI_CHNL_ROI_0_ULC_X_SHIFT (16U)
33012#define ISI_CHNL_ROI_0_ULC_X(x) \
33013 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ULC_X_SHIFT)) & ISI_CHNL_ROI_0_ULC_X_MASK)
33014#define ISI_CHNL_ROI_0_ULC_RSVD0_MASK (0xF0000000U)
33015#define ISI_CHNL_ROI_0_ULC_RSVD0_SHIFT (28U)
33016#define ISI_CHNL_ROI_0_ULC_RSVD0(x) \
33017 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_ULC_RSVD0_SHIFT)) & ISI_CHNL_ROI_0_ULC_RSVD0_MASK)
33018/*! @} */
33019
33020/*! @name CHNL_ROI_0_LRC - Channel Lower Right Coordinate Register for Region of Interest 0 */
33021/*! @{ */
33022#define ISI_CHNL_ROI_0_LRC_Y_MASK (0xFFFU)
33023#define ISI_CHNL_ROI_0_LRC_Y_SHIFT (0U)
33024#define ISI_CHNL_ROI_0_LRC_Y(x) \
33025 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_LRC_Y_SHIFT)) & ISI_CHNL_ROI_0_LRC_Y_MASK)
33026#define ISI_CHNL_ROI_0_LRC_RSVD1_MASK (0xF000U)
33027#define ISI_CHNL_ROI_0_LRC_RSVD1_SHIFT (12U)
33028#define ISI_CHNL_ROI_0_LRC_RSVD1(x) \
33029 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_LRC_RSVD1_SHIFT)) & ISI_CHNL_ROI_0_LRC_RSVD1_MASK)
33030#define ISI_CHNL_ROI_0_LRC_X_MASK (0xFFF0000U)
33031#define ISI_CHNL_ROI_0_LRC_X_SHIFT (16U)
33032#define ISI_CHNL_ROI_0_LRC_X(x) \
33033 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_LRC_X_SHIFT)) & ISI_CHNL_ROI_0_LRC_X_MASK)
33034#define ISI_CHNL_ROI_0_LRC_RSVD0_MASK (0xF0000000U)
33035#define ISI_CHNL_ROI_0_LRC_RSVD0_SHIFT (28U)
33036#define ISI_CHNL_ROI_0_LRC_RSVD0(x) \
33037 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_0_LRC_RSVD0_SHIFT)) & ISI_CHNL_ROI_0_LRC_RSVD0_MASK)
33038/*! @} */
33039
33040/*! @name CHNL_ROI_1_ALPHA - Channel Alpha Value Register for Region of Interest 1 */
33041/*! @{ */
33042#define ISI_CHNL_ROI_1_ALPHA_RSVD1_MASK (0xFFFFU)
33043#define ISI_CHNL_ROI_1_ALPHA_RSVD1_SHIFT (0U)
33044#define ISI_CHNL_ROI_1_ALPHA_RSVD1(x) \
33045 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ALPHA_RSVD1_SHIFT)) & ISI_CHNL_ROI_1_ALPHA_RSVD1_MASK)
33046#define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_MASK (0x10000U)
33047#define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_SHIFT (16U)
33048/*! ALPHA_EN - Alpha value insertion enable
33049 * 0b0..Alpha value insertion is disabled
33050 * 0b1..Alpha value insertion is enabled
33051 */
33052#define ISI_CHNL_ROI_1_ALPHA_ALPHA_EN(x) \
33053 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_1_ALPHA_ALPHA_EN_MASK)
33054#define ISI_CHNL_ROI_1_ALPHA_RSVD0_MASK (0xFE0000U)
33055#define ISI_CHNL_ROI_1_ALPHA_RSVD0_SHIFT (17U)
33056#define ISI_CHNL_ROI_1_ALPHA_RSVD0(x) \
33057 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ALPHA_RSVD0_SHIFT)) & ISI_CHNL_ROI_1_ALPHA_RSVD0_MASK)
33058#define ISI_CHNL_ROI_1_ALPHA_ALPHA_MASK (0xFF000000U)
33059#define ISI_CHNL_ROI_1_ALPHA_ALPHA_SHIFT (24U)
33060#define ISI_CHNL_ROI_1_ALPHA_ALPHA(x) \
33061 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_1_ALPHA_ALPHA_MASK)
33062/*! @} */
33063
33064/*! @name CHNL_ROI_1_ULC - Channel Upper Left Coordinate Register for Region of Interest 1 */
33065/*! @{ */
33066#define ISI_CHNL_ROI_1_ULC_Y_MASK (0xFFFU)
33067#define ISI_CHNL_ROI_1_ULC_Y_SHIFT (0U)
33068#define ISI_CHNL_ROI_1_ULC_Y(x) \
33069 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ULC_Y_SHIFT)) & ISI_CHNL_ROI_1_ULC_Y_MASK)
33070#define ISI_CHNL_ROI_1_ULC_RSVD1_MASK (0xF000U)
33071#define ISI_CHNL_ROI_1_ULC_RSVD1_SHIFT (12U)
33072#define ISI_CHNL_ROI_1_ULC_RSVD1(x) \
33073 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ULC_RSVD1_SHIFT)) & ISI_CHNL_ROI_1_ULC_RSVD1_MASK)
33074#define ISI_CHNL_ROI_1_ULC_X_MASK (0xFFF0000U)
33075#define ISI_CHNL_ROI_1_ULC_X_SHIFT (16U)
33076#define ISI_CHNL_ROI_1_ULC_X(x) \
33077 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ULC_X_SHIFT)) & ISI_CHNL_ROI_1_ULC_X_MASK)
33078#define ISI_CHNL_ROI_1_ULC_RSVD0_MASK (0xF0000000U)
33079#define ISI_CHNL_ROI_1_ULC_RSVD0_SHIFT (28U)
33080#define ISI_CHNL_ROI_1_ULC_RSVD0(x) \
33081 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_ULC_RSVD0_SHIFT)) & ISI_CHNL_ROI_1_ULC_RSVD0_MASK)
33082/*! @} */
33083
33084/*! @name CHNL_ROI_1_LRC - Channel Lower Right Coordinate Register for Region of Interest 1 */
33085/*! @{ */
33086#define ISI_CHNL_ROI_1_LRC_Y_MASK (0xFFFU)
33087#define ISI_CHNL_ROI_1_LRC_Y_SHIFT (0U)
33088#define ISI_CHNL_ROI_1_LRC_Y(x) \
33089 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_LRC_Y_SHIFT)) & ISI_CHNL_ROI_1_LRC_Y_MASK)
33090#define ISI_CHNL_ROI_1_LRC_RSVD1_MASK (0xF000U)
33091#define ISI_CHNL_ROI_1_LRC_RSVD1_SHIFT (12U)
33092#define ISI_CHNL_ROI_1_LRC_RSVD1(x) \
33093 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_LRC_RSVD1_SHIFT)) & ISI_CHNL_ROI_1_LRC_RSVD1_MASK)
33094#define ISI_CHNL_ROI_1_LRC_X_MASK (0xFFF0000U)
33095#define ISI_CHNL_ROI_1_LRC_X_SHIFT (16U)
33096#define ISI_CHNL_ROI_1_LRC_X(x) \
33097 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_LRC_X_SHIFT)) & ISI_CHNL_ROI_1_LRC_X_MASK)
33098#define ISI_CHNL_ROI_1_LRC_RSVD0_MASK (0xF0000000U)
33099#define ISI_CHNL_ROI_1_LRC_RSVD0_SHIFT (28U)
33100#define ISI_CHNL_ROI_1_LRC_RSVD0(x) \
33101 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_1_LRC_RSVD0_SHIFT)) & ISI_CHNL_ROI_1_LRC_RSVD0_MASK)
33102/*! @} */
33103
33104/*! @name CHNL_ROI_2_ALPHA - Channel Alpha Value Register for Region of Interest 2 */
33105/*! @{ */
33106#define ISI_CHNL_ROI_2_ALPHA_RSVD1_MASK (0xFFFFU)
33107#define ISI_CHNL_ROI_2_ALPHA_RSVD1_SHIFT (0U)
33108#define ISI_CHNL_ROI_2_ALPHA_RSVD1(x) \
33109 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ALPHA_RSVD1_SHIFT)) & ISI_CHNL_ROI_2_ALPHA_RSVD1_MASK)
33110#define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_MASK (0x10000U)
33111#define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_SHIFT (16U)
33112/*! ALPHA_EN - Alpha value insertion enable
33113 * 0b0..Alpha value insertion is disabled
33114 * 0b1..Alpha value insertion is enabled
33115 */
33116#define ISI_CHNL_ROI_2_ALPHA_ALPHA_EN(x) \
33117 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_2_ALPHA_ALPHA_EN_MASK)
33118#define ISI_CHNL_ROI_2_ALPHA_RSVD0_MASK (0xFE0000U)
33119#define ISI_CHNL_ROI_2_ALPHA_RSVD0_SHIFT (17U)
33120#define ISI_CHNL_ROI_2_ALPHA_RSVD0(x) \
33121 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ALPHA_RSVD0_SHIFT)) & ISI_CHNL_ROI_2_ALPHA_RSVD0_MASK)
33122#define ISI_CHNL_ROI_2_ALPHA_ALPHA_MASK (0xFF000000U)
33123#define ISI_CHNL_ROI_2_ALPHA_ALPHA_SHIFT (24U)
33124#define ISI_CHNL_ROI_2_ALPHA_ALPHA(x) \
33125 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_2_ALPHA_ALPHA_MASK)
33126/*! @} */
33127
33128/*! @name CHNL_ROI_2_ULC - Channel Upper Left Coordinate Register for Region of Interest 2 */
33129/*! @{ */
33130#define ISI_CHNL_ROI_2_ULC_Y_MASK (0xFFFU)
33131#define ISI_CHNL_ROI_2_ULC_Y_SHIFT (0U)
33132#define ISI_CHNL_ROI_2_ULC_Y(x) \
33133 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ULC_Y_SHIFT)) & ISI_CHNL_ROI_2_ULC_Y_MASK)
33134#define ISI_CHNL_ROI_2_ULC_RSVD1_MASK (0xF000U)
33135#define ISI_CHNL_ROI_2_ULC_RSVD1_SHIFT (12U)
33136#define ISI_CHNL_ROI_2_ULC_RSVD1(x) \
33137 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ULC_RSVD1_SHIFT)) & ISI_CHNL_ROI_2_ULC_RSVD1_MASK)
33138#define ISI_CHNL_ROI_2_ULC_X_MASK (0xFFF0000U)
33139#define ISI_CHNL_ROI_2_ULC_X_SHIFT (16U)
33140#define ISI_CHNL_ROI_2_ULC_X(x) \
33141 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ULC_X_SHIFT)) & ISI_CHNL_ROI_2_ULC_X_MASK)
33142#define ISI_CHNL_ROI_2_ULC_RSVD0_MASK (0xF0000000U)
33143#define ISI_CHNL_ROI_2_ULC_RSVD0_SHIFT (28U)
33144#define ISI_CHNL_ROI_2_ULC_RSVD0(x) \
33145 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_ULC_RSVD0_SHIFT)) & ISI_CHNL_ROI_2_ULC_RSVD0_MASK)
33146/*! @} */
33147
33148/*! @name CHNL_ROI_2_LRC - Channel Lower Right Coordinate Register for Region of Interest 2 */
33149/*! @{ */
33150#define ISI_CHNL_ROI_2_LRC_Y_MASK (0xFFFU)
33151#define ISI_CHNL_ROI_2_LRC_Y_SHIFT (0U)
33152#define ISI_CHNL_ROI_2_LRC_Y(x) \
33153 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_LRC_Y_SHIFT)) & ISI_CHNL_ROI_2_LRC_Y_MASK)
33154#define ISI_CHNL_ROI_2_LRC_RSVD1_MASK (0xF000U)
33155#define ISI_CHNL_ROI_2_LRC_RSVD1_SHIFT (12U)
33156#define ISI_CHNL_ROI_2_LRC_RSVD1(x) \
33157 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_LRC_RSVD1_SHIFT)) & ISI_CHNL_ROI_2_LRC_RSVD1_MASK)
33158#define ISI_CHNL_ROI_2_LRC_X_MASK (0xFFF0000U)
33159#define ISI_CHNL_ROI_2_LRC_X_SHIFT (16U)
33160#define ISI_CHNL_ROI_2_LRC_X(x) \
33161 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_LRC_X_SHIFT)) & ISI_CHNL_ROI_2_LRC_X_MASK)
33162#define ISI_CHNL_ROI_2_LRC_RSVD0_MASK (0xF0000000U)
33163#define ISI_CHNL_ROI_2_LRC_RSVD0_SHIFT (28U)
33164#define ISI_CHNL_ROI_2_LRC_RSVD0(x) \
33165 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_2_LRC_RSVD0_SHIFT)) & ISI_CHNL_ROI_2_LRC_RSVD0_MASK)
33166/*! @} */
33167
33168/*! @name CHNL_ROI_3_ALPHA - Channel Alpha Value Register for Region of Interest 3 */
33169/*! @{ */
33170#define ISI_CHNL_ROI_3_ALPHA_RSVD1_MASK (0xFFFFU)
33171#define ISI_CHNL_ROI_3_ALPHA_RSVD1_SHIFT (0U)
33172#define ISI_CHNL_ROI_3_ALPHA_RSVD1(x) \
33173 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ALPHA_RSVD1_SHIFT)) & ISI_CHNL_ROI_3_ALPHA_RSVD1_MASK)
33174#define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_MASK (0x10000U)
33175#define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_SHIFT (16U)
33176/*! ALPHA_EN - Alpha value insertion enable
33177 * 0b0..Alpha value insertion is disabled
33178 * 0b1..Alpha value insertion is enabled
33179 */
33180#define ISI_CHNL_ROI_3_ALPHA_ALPHA_EN(x) \
33181 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_SHIFT)) & ISI_CHNL_ROI_3_ALPHA_ALPHA_EN_MASK)
33182#define ISI_CHNL_ROI_3_ALPHA_RSVD0_MASK (0xFE0000U)
33183#define ISI_CHNL_ROI_3_ALPHA_RSVD0_SHIFT (17U)
33184#define ISI_CHNL_ROI_3_ALPHA_RSVD0(x) \
33185 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ALPHA_RSVD0_SHIFT)) & ISI_CHNL_ROI_3_ALPHA_RSVD0_MASK)
33186#define ISI_CHNL_ROI_3_ALPHA_ALPHA_MASK (0xFF000000U)
33187#define ISI_CHNL_ROI_3_ALPHA_ALPHA_SHIFT (24U)
33188#define ISI_CHNL_ROI_3_ALPHA_ALPHA(x) \
33189 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ALPHA_ALPHA_SHIFT)) & ISI_CHNL_ROI_3_ALPHA_ALPHA_MASK)
33190/*! @} */
33191
33192/*! @name CHNL_ROI_3_ULC - Channel Upper Left Coordinate Register for Region of Interest 3 */
33193/*! @{ */
33194#define ISI_CHNL_ROI_3_ULC_Y_MASK (0xFFFU)
33195#define ISI_CHNL_ROI_3_ULC_Y_SHIFT (0U)
33196#define ISI_CHNL_ROI_3_ULC_Y(x) \
33197 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ULC_Y_SHIFT)) & ISI_CHNL_ROI_3_ULC_Y_MASK)
33198#define ISI_CHNL_ROI_3_ULC_RSVD1_MASK (0xF000U)
33199#define ISI_CHNL_ROI_3_ULC_RSVD1_SHIFT (12U)
33200#define ISI_CHNL_ROI_3_ULC_RSVD1(x) \
33201 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ULC_RSVD1_SHIFT)) & ISI_CHNL_ROI_3_ULC_RSVD1_MASK)
33202#define ISI_CHNL_ROI_3_ULC_X_MASK (0xFFF0000U)
33203#define ISI_CHNL_ROI_3_ULC_X_SHIFT (16U)
33204#define ISI_CHNL_ROI_3_ULC_X(x) \
33205 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ULC_X_SHIFT)) & ISI_CHNL_ROI_3_ULC_X_MASK)
33206#define ISI_CHNL_ROI_3_ULC_RSVD0_MASK (0xF0000000U)
33207#define ISI_CHNL_ROI_3_ULC_RSVD0_SHIFT (28U)
33208#define ISI_CHNL_ROI_3_ULC_RSVD0(x) \
33209 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_ULC_RSVD0_SHIFT)) & ISI_CHNL_ROI_3_ULC_RSVD0_MASK)
33210/*! @} */
33211
33212/*! @name CHNL_ROI_3_LRC - Channel Lower Right Coordinate Register for Region of Interest 3 */
33213/*! @{ */
33214#define ISI_CHNL_ROI_3_LRC_Y_MASK (0xFFFU)
33215#define ISI_CHNL_ROI_3_LRC_Y_SHIFT (0U)
33216#define ISI_CHNL_ROI_3_LRC_Y(x) \
33217 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_LRC_Y_SHIFT)) & ISI_CHNL_ROI_3_LRC_Y_MASK)
33218#define ISI_CHNL_ROI_3_LRC_RSVD1_MASK (0xF000U)
33219#define ISI_CHNL_ROI_3_LRC_RSVD1_SHIFT (12U)
33220#define ISI_CHNL_ROI_3_LRC_RSVD1(x) \
33221 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_LRC_RSVD1_SHIFT)) & ISI_CHNL_ROI_3_LRC_RSVD1_MASK)
33222#define ISI_CHNL_ROI_3_LRC_X_MASK (0xFFF0000U)
33223#define ISI_CHNL_ROI_3_LRC_X_SHIFT (16U)
33224#define ISI_CHNL_ROI_3_LRC_X(x) \
33225 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_LRC_X_SHIFT)) & ISI_CHNL_ROI_3_LRC_X_MASK)
33226#define ISI_CHNL_ROI_3_LRC_RSVD0_MASK (0xF0000000U)
33227#define ISI_CHNL_ROI_3_LRC_RSVD0_SHIFT (28U)
33228#define ISI_CHNL_ROI_3_LRC_RSVD0(x) \
33229 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_ROI_3_LRC_RSVD0_SHIFT)) & ISI_CHNL_ROI_3_LRC_RSVD0_MASK)
33230/*! @} */
33231
33232/*! @name CHNL_OUT_BUF1_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 1 Address */
33233/*! @{ */
33234#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK (0xFFFFFFFFU)
33235#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT (0U)
33236#define ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR(x) \
33237 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_Y_ADDR_MASK)
33238/*! @} */
33239
33240/*! @name CHNL_OUT_BUF1_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address */
33241/*! @{ */
33242#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK (0xFFFFFFFFU)
33243#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT (0U)
33244#define ISI_CHNL_OUT_BUF1_ADDR_U_ADDR(x) \
33245 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_U_ADDR_MASK)
33246/*! @} */
33247
33248/*! @name CHNL_OUT_BUF1_ADDR_V - Channel Chroma (V/Cr) Output Buffer 1 Address */
33249/*! @{ */
33250#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK (0xFFFFFFFFU)
33251#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT (0U)
33252#define ISI_CHNL_OUT_BUF1_ADDR_V_ADDR(x) \
33253 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF1_ADDR_V_ADDR_MASK)
33254/*! @} */
33255
33256/*! @name CHNL_OUT_BUF_PITCH - Channel Output Buffer Pitch */
33257/*! @{ */
33258#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK (0xFFFFU)
33259#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT (0U)
33260#define ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH(x) \
33261 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK)
33262/*! @} */
33263
33264/*! @name CHNL_IN_BUF_ADDR - Channel Input Buffer Address */
33265/*! @{ */
33266#define ISI_CHNL_IN_BUF_ADDR_ADDR_MASK (0xFFFFFFFFU)
33267#define ISI_CHNL_IN_BUF_ADDR_ADDR_SHIFT (0U)
33268#define ISI_CHNL_IN_BUF_ADDR_ADDR(x) \
33269 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_ADDR_ADDR_SHIFT)) & ISI_CHNL_IN_BUF_ADDR_ADDR_MASK)
33270/*! @} */
33271
33272/*! @name CHNL_IN_BUF_PITCH - Channel Input Buffer Pitch */
33273/*! @{ */
33274#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK (0xFFFFU)
33275#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT (0U)
33276#define ISI_CHNL_IN_BUF_PITCH_LINE_PITCH(x) \
33277 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_LINE_PITCH_MASK)
33278#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK (0xFFFF0000U)
33279#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT (16U)
33280#define ISI_CHNL_IN_BUF_PITCH_FRM_PITCH(x) \
33281 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_SHIFT)) & ISI_CHNL_IN_BUF_PITCH_FRM_PITCH_MASK)
33282/*! @} */
33283
33284/*! @name CHNL_MEM_RD_CTRL - Channel Memory Read Control */
33285/*! @{ */
33286#define ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK (0x1U)
33287#define ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT (0U)
33288/*! READ_MEM - Initiate read from memory
33289 * 0b0..No reads from memory done
33290 * 0b1..Reads from memory initiated
33291 */
33292#define ISI_CHNL_MEM_RD_CTRL_READ_MEM(x) \
33293 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_READ_MEM_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_READ_MEM_MASK)
33294#define ISI_CHNL_MEM_RD_CTRL_RSVD0_MASK (0xFFFFFFEU)
33295#define ISI_CHNL_MEM_RD_CTRL_RSVD0_SHIFT (1U)
33296#define ISI_CHNL_MEM_RD_CTRL_RSVD0(x) \
33297 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_RSVD0_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_RSVD0_MASK)
33298#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK (0xF0000000U)
33299#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT (28U)
33300/*! IMG_TYPE - Input image format
33301 * 0b0000..BGR8P - BGR format with 8-bits per color component (packed into 32-bit DWORD)
33302 * 0b0001..RGB8P - RGB format with 8-bits per color component (packed into 32-bit DWORD)
33303 * 0b0010..XRGB8 - RGB format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD)
33304 * 0b0011..RGBX8 - RGB format with 8-bits per color component (unpacked and MSBalinged in 32-bit DWORD)
33305 * 0b0100..XBGR8 - BGR format with 8-bits per color component (unpacked and LSB aligned in 32-bit DWORD)
33306 * 0b0101..RGB565 - RGB format with 5-bits of R, B; 6-bits of G (packed into 32-bit DWORD)
33307 * 0b0110..A2BGR10 - BGR format with 2-bits alpha in MSB; 10-bits per color component
33308 * 0b0111..A2RGB10 - RGB format with 2-bits alpha in MSB; 10-bits per color component
33309 * 0b1000..YUV444_1P8P with 8-bits per color component; 1-plane, YUV interleaved packed bytes
33310 * 0b1001..YUV444_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked bytes (6 LSBs waste bits in
33311 * 16-bit WORD) 0b1010..YUV444_1P10P with 10-bits per color component; 1-plane, YUV interleaved packed bytes (2 MSBs
33312 * waste bits in 32-bit WORD) 0b1011..YUV444_1P12 with 12-bits per color component; 1-plane, YUV interleaved unpacked
33313 * bytes (4 LSBs waste bits in 16-bit WORD) 0b1100..YUV444_1P8 with 8-bits per color component; 1-plane YUV interleaved
33314 * unpacked bytes (8 MSBs waste bits in 32-bit DWORD) 0b1101..YUV422_1P8P with 8-bits per color component; 1-plane YUV
33315 * interleaved packed bytes 0b1110..YUV422_1P10 with 10-bits per color component; 1-plane, YUV interleaved unpacked
33316 * bytes (6 LSBs waste bits in 16-bit WORD) 0b1111..YUV422_1P12 with 12-bits per color component; 1-plane, YUV
33317 * interleaved packed bytes (4 MSBs waste bits in 16-bit WORD)
33318 */
33319#define ISI_CHNL_MEM_RD_CTRL_IMG_TYPE(x) \
33320 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_SHIFT)) & ISI_CHNL_MEM_RD_CTRL_IMG_TYPE_MASK)
33321/*! @} */
33322
33323/*! @name CHNL_OUT_BUF2_ADDR_Y - Channel RGB or Luma (Y) Output Buffer 2 Address */
33324/*! @{ */
33325#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK (0xFFFFFFFFU)
33326#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT (0U)
33327#define ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR(x) \
33328 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_Y_ADDR_MASK)
33329/*! @} */
33330
33331/*! @name CHNL_OUT_BUF2_ADDR_U - Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address */
33332/*! @{ */
33333#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK (0xFFFFFFFFU)
33334#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT (0U)
33335#define ISI_CHNL_OUT_BUF2_ADDR_U_ADDR(x) \
33336 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_U_ADDR_MASK)
33337/*! @} */
33338
33339/*! @name CHNL_OUT_BUF2_ADDR_V - Channel Chroma (V/Cr) Output Buffer 2 Address */
33340/*! @{ */
33341#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK (0xFFFFFFFFU)
33342#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT (0U)
33343#define ISI_CHNL_OUT_BUF2_ADDR_V_ADDR(x) \
33344 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_SHIFT)) & ISI_CHNL_OUT_BUF2_ADDR_V_ADDR_MASK)
33345/*! @} */
33346
33347/*! @name CHNL_SCL_IMG_CFG - Channel Scaled Image Configuration */
33348/*! @{ */
33349#define ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK (0x1FFFU)
33350#define ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT (0U)
33351#define ISI_CHNL_SCL_IMG_CFG_WIDTH(x) \
33352 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_WIDTH_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_WIDTH_MASK)
33353#define ISI_CHNL_SCL_IMG_CFG_RSVD0_MASK (0xE000U)
33354#define ISI_CHNL_SCL_IMG_CFG_RSVD0_SHIFT (13U)
33355#define ISI_CHNL_SCL_IMG_CFG_RSVD0(x) \
33356 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_RSVD0_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_RSVD0_MASK)
33357#define ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK (0x1FFF0000U)
33358#define ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT (16U)
33359#define ISI_CHNL_SCL_IMG_CFG_HEIGHT(x) \
33360 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_HEIGHT_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_HEIGHT_MASK)
33361#define ISI_CHNL_SCL_IMG_CFG_RSVD1_MASK (0xE0000000U)
33362#define ISI_CHNL_SCL_IMG_CFG_RSVD1_SHIFT (29U)
33363#define ISI_CHNL_SCL_IMG_CFG_RSVD1(x) \
33364 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_SCL_IMG_CFG_RSVD1_SHIFT)) & ISI_CHNL_SCL_IMG_CFG_RSVD1_MASK)
33365/*! @} */
33366
33367/*! @name CHNL_FLOW_CTRL - Channel Flow Control Register */
33368/*! @{ */
33369#define ISI_CHNL_FLOW_CTRL_FC_DENOM_MASK (0xFFU)
33370#define ISI_CHNL_FLOW_CTRL_FC_DENOM_SHIFT (0U)
33371/*! FC_DENOM - Denominator value of fraction of usable bandwidth
33372 * 0b00000000..Invalid value. Flow control will be disabled.
33373 */
33374#define ISI_CHNL_FLOW_CTRL_FC_DENOM(x) \
33375 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_FLOW_CTRL_FC_DENOM_SHIFT)) & ISI_CHNL_FLOW_CTRL_FC_DENOM_MASK)
33376#define ISI_CHNL_FLOW_CTRL_FC_NUMER_MASK (0xFF0000U)
33377#define ISI_CHNL_FLOW_CTRL_FC_NUMER_SHIFT (16U)
33378/*! FC_NUMER - Numertor value of fraction of usable bandwidth
33379 * 0b00000000..Flow control is disabled.
33380 */
33381#define ISI_CHNL_FLOW_CTRL_FC_NUMER(x) \
33382 (((uint32_t)(((uint32_t)(x)) << ISI_CHNL_FLOW_CTRL_FC_NUMER_SHIFT)) & ISI_CHNL_FLOW_CTRL_FC_NUMER_MASK)
33383/*! @} */
33384
33385/*!
33386 * @}
33387 */ /* end of group ISI_Register_Masks */
33388
33389/* ISI - Peripheral instance base addresses */
33390/** Peripheral ISI base address */
33391#define ISI_BASE (0x32E20000u)
33392/** Peripheral ISI base pointer */
33393#define ISI ((ISI_Type *)ISI_BASE)
33394/** Array initializer of ISI peripheral base addresses */
33395#define ISI_BASE_ADDRS \
33396 { \
33397 ISI_BASE \
33398 }
33399/** Array initializer of ISI peripheral base pointers */
33400#define ISI_BASE_PTRS \
33401 { \
33402 ISI \
33403 }
33404
33405/*!
33406 * @}
33407 */ /* end of group ISI_Peripheral_Access_Layer */
33408
33409/* ----------------------------------------------------------------------------
33410 -- LCDIF Peripheral Access Layer
33411 ---------------------------------------------------------------------------- */
33412
33413/*!
33414 * @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer
33415 * @{
33416 */
33417
33418/** LCDIF - Register Layout Typedef */
33419typedef struct
33420{
33421 __IO uint32_t CTRL; /**< LCDIF General Control Register, offset: 0x0 */
33422 __IO uint32_t CTRL_SET; /**< LCDIF General Control Register, offset: 0x4 */
33423 __IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 */
33424 __IO uint32_t CTRL_TOG; /**< LCDIF General Control Register, offset: 0xC */
33425 __IO uint32_t CTRL1; /**< LCDIF General Control1 Register, offset: 0x10 */
33426 __IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x14 */
33427 __IO uint32_t CTRL1_CLR; /**< LCDIF General Control1 Register, offset: 0x18 */
33428 __IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1C */
33429 __IO uint32_t CTRL2; /**< LCDIF General Control2 Register, offset: 0x20 */
33430 __IO uint32_t CTRL2_SET; /**< LCDIF General Control2 Register, offset: 0x24 */
33431 __IO uint32_t CTRL2_CLR; /**< LCDIF General Control2 Register, offset: 0x28 */
33432 __IO uint32_t CTRL2_TOG; /**< LCDIF General Control2 Register, offset: 0x2C */
33433 __IO uint32_t TRANSFER_COUNT; /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */
33434 uint8_t RESERVED_0[12];
33435 __IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */
33436 uint8_t RESERVED_1[12];
33437 __IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */
33438 uint8_t RESERVED_2[12];
33439 __IO uint32_t TIMING; /**< LCD Interface Timing Register, offset: 0x60 */
33440 uint8_t RESERVED_3[12];
33441 __IO uint32_t VDCTRL0; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */
33442 __IO uint32_t VDCTRL0_SET; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */
33443 __IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */
33444 __IO uint32_t VDCTRL0_TOG; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */
33445 __IO uint32_t VDCTRL1; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */
33446 uint8_t RESERVED_4[12];
33447 __IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */
33448 uint8_t RESERVED_5[12];
33449 __IO uint32_t VDCTRL3; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */
33450 uint8_t RESERVED_6[12];
33451 __IO uint32_t VDCTRL4; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */
33452 uint8_t RESERVED_7[12];
33453 __IO uint32_t DVICTRL0; /**< Digital Video Interface Control0 Register, offset: 0xC0 */
33454 uint8_t RESERVED_8[12];
33455 __IO uint32_t DVICTRL1; /**< Digital Video Interface Control1 Register, offset: 0xD0 */
33456 uint8_t RESERVED_9[12];
33457 __IO uint32_t DVICTRL2; /**< Digital Video Interface Control2 Register, offset: 0xE0 */
33458 uint8_t RESERVED_10[12];
33459 __IO uint32_t DVICTRL3; /**< Digital Video Interface Control3 Register, offset: 0xF0 */
33460 uint8_t RESERVED_11[12];
33461 __IO uint32_t DVICTRL4; /**< Digital Video Interface Control4 Register, offset: 0x100 */
33462 uint8_t RESERVED_12[12];
33463 __IO uint32_t CSC_COEFF0; /**< RGB to YCbCr 4:2:2 CSC Coefficient0 Register, offset: 0x110 */
33464 uint8_t RESERVED_13[12];
33465 __IO uint32_t CSC_COEFF1; /**< RGB to YCbCr 4:2:2 CSC Coefficient1 Register, offset: 0x120 */
33466 uint8_t RESERVED_14[12];
33467 __IO uint32_t CSC_COEFF2; /**< RGB to YCbCr 4:2:2 CSC Coefficent2 Register, offset: 0x130 */
33468 uint8_t RESERVED_15[12];
33469 __IO uint32_t CSC_COEFF3; /**< RGB to YCbCr 4:2:2 CSC Coefficient3 Register, offset: 0x140 */
33470 uint8_t RESERVED_16[12];
33471 __IO uint32_t CSC_COEFF4; /**< RGB to YCbCr 4:2:2 CSC Coefficient4 Register, offset: 0x150 */
33472 uint8_t RESERVED_17[12];
33473 __IO uint32_t CSC_OFFSET; /**< RGB to YCbCr 4:2:2 CSC Offset Register, offset: 0x160 */
33474 uint8_t RESERVED_18[12];
33475 __IO uint32_t CSC_LIMIT; /**< RGB to YCbCr 4:2:2 CSC Limit Register, offset: 0x170 */
33476 uint8_t RESERVED_19[12];
33477 __IO uint32_t DATA; /**< LCD Interface Data Register, offset: 0x180 */
33478 uint8_t RESERVED_20[12];
33479 __IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */
33480 uint8_t RESERVED_21[12];
33481 __IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */
33482 uint8_t RESERVED_22[12];
33483 __I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */
33484 uint8_t RESERVED_23[76];
33485 __IO uint32_t THRES; /**< LCDIF Threshold Register, offset: 0x200 */
33486 uint8_t RESERVED_24[12];
33487 __IO uint32_t AS_CTRL; /**< LCDIF AS Buffer Control Register, offset: 0x210 */
33488 uint8_t RESERVED_25[12];
33489 __IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x220 */
33490 uint8_t RESERVED_26[12];
33491 __IO uint32_t AS_NEXT_BUF; /**< , offset: 0x230 */
33492 uint8_t RESERVED_27[12];
33493 __IO uint32_t AS_CLRKEYLOW; /**< LCDIF Overlay Color Key Low, offset: 0x240 */
33494 uint8_t RESERVED_28[12];
33495 __IO uint32_t AS_CLRKEYHIGH; /**< LCDIF Overlay Color Key High, offset: 0x250 */
33496 uint8_t RESERVED_29[12];
33497 __IO uint32_t SYNC_DELAY; /**< LCD working insync mode with CSI for VSYNC delay, offset: 0x260 */
33498 uint8_t RESERVED_30[284];
33499 __IO uint32_t PIGEONCTRL0; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x380 */
33500 __IO uint32_t PIGEONCTRL0_SET; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x384 */
33501 __IO uint32_t PIGEONCTRL0_CLR; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x388 */
33502 __IO uint32_t PIGEONCTRL0_TOG; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x38C */
33503 __IO uint32_t PIGEONCTRL1; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x390 */
33504 __IO uint32_t PIGEONCTRL1_SET; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x394 */
33505 __IO uint32_t PIGEONCTRL1_CLR; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x398 */
33506 __IO uint32_t PIGEONCTRL1_TOG; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x39C */
33507 __IO uint32_t PIGEONCTRL2; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A0 */
33508 __IO uint32_t PIGEONCTRL2_SET; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A4 */
33509 __IO uint32_t PIGEONCTRL2_CLR; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A8 */
33510 __IO uint32_t PIGEONCTRL2_TOG; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3AC */
33511 uint8_t RESERVED_31[1104];
33512 struct
33513 { /* offset: 0x800, array step: 0x40 */
33514 __IO uint32_t
33515 PIGEON_n_0; /**< Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40 */
33516 uint8_t RESERVED_0[12];
33517 __IO uint32_t
33518 PIGEON_n_1; /**< Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40 */
33519 uint8_t RESERVED_1[12];
33520 __IO uint32_t
33521 PIGEON_n_2; /**< Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40 */
33522 uint8_t RESERVED_2[28];
33523 } PIGEON_n[12];
33524} LCDIF_Type;
33525
33526/* ----------------------------------------------------------------------------
33527 -- LCDIF Register Masks
33528 ---------------------------------------------------------------------------- */
33529
33530/*!
33531 * @addtogroup LCDIF_Register_Masks LCDIF Register Masks
33532 * @{
33533 */
33534
33535/*! @name CTRL - LCDIF General Control Register */
33536/*! @{ */
33537#define LCDIF_CTRL_RUN_MASK (0x1U)
33538#define LCDIF_CTRL_RUN_SHIFT (0U)
33539#define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)
33540#define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U)
33541#define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U)
33542/*! DATA_FORMAT_24_BIT
33543 * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
33544 * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
33545 * each byte do not contain any useful data, and should be dropped.
33546 */
33547#define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) \
33548 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)
33549#define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U)
33550#define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U)
33551/*! DATA_FORMAT_18_BIT
33552 * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not
33553 * contain any useful data. 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666
33554 * and lower 14 bits do not contain any useful data.
33555 */
33556#define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) \
33557 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)
33558#define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U)
33559#define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U)
33560#define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) \
33561 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)
33562#define LCDIF_CTRL_RSRVD0_MASK (0x10U)
33563#define LCDIF_CTRL_RSRVD0_SHIFT (4U)
33564#define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK)
33565#define LCDIF_CTRL_MASTER_MASK (0x20U)
33566#define LCDIF_CTRL_MASTER_SHIFT (5U)
33567#define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK)
33568#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
33569#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
33570#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) \
33571 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK)
33572#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK (0x80U)
33573#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT (7U)
33574#define LCDIF_CTRL_RGB_TO_YCBCR422_CSC(x) \
33575 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RGB_TO_YCBCR422_CSC_SHIFT)) & LCDIF_CTRL_RGB_TO_YCBCR422_CSC_MASK)
33576#define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U)
33577#define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U)
33578/*! WORD_LENGTH
33579 * 0b00..Input data is 16 bits per pixel.
33580 * 0b01..Input data is 8 bits wide.
33581 * 0b10..Input data is 18 bits per pixel.
33582 * 0b11..Input data is 24 bits per pixel.
33583 */
33584#define LCDIF_CTRL_WORD_LENGTH(x) \
33585 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)
33586#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U)
33587#define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U)
33588/*! LCD_DATABUS_WIDTH
33589 * 0b00..16-bit data bus mode.
33590 * 0b01..8-bit data bus mode.
33591 * 0b10..18-bit data bus mode.
33592 * 0b11..24-bit data bus mode.
33593 */
33594#define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) \
33595 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)
33596#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U)
33597#define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U)
33598/*! CSC_DATA_SWIZZLE
33599 * 0b00..No byte swapping.(Little endian)
33600 * 0b00..Little Endian byte ordering (same as NO_SWAP).
33601 * 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
33602 * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
33603 * 0b10..Swap half-words.
33604 * 0b11..Swap bytes within each half-word.
33605 */
33606#define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) \
33607 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)
33608#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U)
33609#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U)
33610/*! INPUT_DATA_SWIZZLE
33611 * 0b00..No byte swapping.(Little endian)
33612 * 0b00..Little Endian byte ordering (same as NO_SWAP).
33613 * 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
33614 * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
33615 * 0b10..Swap half-words.
33616 * 0b11..Swap bytes within each half-word.
33617 */
33618#define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) \
33619 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)
33620#define LCDIF_CTRL_DATA_SELECT_MASK (0x10000U)
33621#define LCDIF_CTRL_DATA_SELECT_SHIFT (16U)
33622/*! DATA_SELECT
33623 * 0b0..Command Mode. LCD_RS signal is Low.
33624 * 0b1..Data Mode. LCD_RS signal is High.
33625 */
33626#define LCDIF_CTRL_DATA_SELECT(x) \
33627 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SELECT_SHIFT)) & LCDIF_CTRL_DATA_SELECT_MASK)
33628#define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U)
33629#define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U)
33630#define LCDIF_CTRL_DOTCLK_MODE(x) \
33631 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK)
33632#define LCDIF_CTRL_VSYNC_MODE_MASK (0x40000U)
33633#define LCDIF_CTRL_VSYNC_MODE_SHIFT (18U)
33634#define LCDIF_CTRL_VSYNC_MODE(x) \
33635 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_VSYNC_MODE_MASK)
33636#define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U)
33637#define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U)
33638#define LCDIF_CTRL_BYPASS_COUNT(x) \
33639 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK)
33640#define LCDIF_CTRL_DVI_MODE_MASK (0x100000U)
33641#define LCDIF_CTRL_DVI_MODE_SHIFT (20U)
33642#define LCDIF_CTRL_DVI_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DVI_MODE_SHIFT)) & LCDIF_CTRL_DVI_MODE_MASK)
33643#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U)
33644#define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U)
33645#define LCDIF_CTRL_SHIFT_NUM_BITS(x) \
33646 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)
33647#define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U)
33648#define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U)
33649/*! DATA_SHIFT_DIR
33650 * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
33651 * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
33652 */
33653#define LCDIF_CTRL_DATA_SHIFT_DIR(x) \
33654 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)
33655#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U)
33656#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT (27U)
33657#define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE(x) \
33658 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_SHIFT)) & LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE_MASK)
33659#define LCDIF_CTRL_READ_WRITEB_MASK (0x10000000U)
33660#define LCDIF_CTRL_READ_WRITEB_SHIFT (28U)
33661#define LCDIF_CTRL_READ_WRITEB(x) \
33662 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_READ_WRITEB_SHIFT)) & LCDIF_CTRL_READ_WRITEB_MASK)
33663#define LCDIF_CTRL_YCBCR422_INPUT_MASK (0x20000000U)
33664#define LCDIF_CTRL_YCBCR422_INPUT_SHIFT (29U)
33665#define LCDIF_CTRL_YCBCR422_INPUT(x) \
33666 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_YCBCR422_INPUT_MASK)
33667#define LCDIF_CTRL_CLKGATE_MASK (0x40000000U)
33668#define LCDIF_CTRL_CLKGATE_SHIFT (30U)
33669#define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK)
33670#define LCDIF_CTRL_SFTRST_MASK (0x80000000U)
33671#define LCDIF_CTRL_SFTRST_SHIFT (31U)
33672#define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK)
33673/*! @} */
33674
33675/*! @name CTRL_SET - LCDIF General Control Register */
33676/*! @{ */
33677#define LCDIF_CTRL_SET_RUN_MASK (0x1U)
33678#define LCDIF_CTRL_SET_RUN_SHIFT (0U)
33679#define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)
33680#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U)
33681#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U)
33682/*! DATA_FORMAT_24_BIT
33683 * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
33684 * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
33685 * each byte do not contain any useful data, and should be dropped.
33686 */
33687#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) \
33688 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)
33689#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U)
33690#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U)
33691/*! DATA_FORMAT_18_BIT
33692 * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not
33693 * contain any useful data. 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666
33694 * and lower 14 bits do not contain any useful data.
33695 */
33696#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) \
33697 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)
33698#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U)
33699#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U)
33700#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) \
33701 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK)
33702#define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U)
33703#define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U)
33704#define LCDIF_CTRL_SET_RSRVD0(x) \
33705 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK)
33706#define LCDIF_CTRL_SET_MASTER_MASK (0x20U)
33707#define LCDIF_CTRL_SET_MASTER_SHIFT (5U)
33708#define LCDIF_CTRL_SET_MASTER(x) \
33709 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK)
33710#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
33711#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
33712#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) \
33713 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & \
33714 LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK)
33715#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK (0x80U)
33716#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT (7U)
33717#define LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC(x) \
33718 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_SHIFT)) & \
33719 LCDIF_CTRL_SET_RGB_TO_YCBCR422_CSC_MASK)
33720#define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U)
33721#define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U)
33722/*! WORD_LENGTH
33723 * 0b00..Input data is 16 bits per pixel.
33724 * 0b01..Input data is 8 bits wide.
33725 * 0b10..Input data is 18 bits per pixel.
33726 * 0b11..Input data is 24 bits per pixel.
33727 */
33728#define LCDIF_CTRL_SET_WORD_LENGTH(x) \
33729 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)
33730#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U)
33731#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U)
33732/*! LCD_DATABUS_WIDTH
33733 * 0b00..16-bit data bus mode.
33734 * 0b01..8-bit data bus mode.
33735 * 0b10..18-bit data bus mode.
33736 * 0b11..24-bit data bus mode.
33737 */
33738#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) \
33739 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)
33740#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U)
33741#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U)
33742/*! CSC_DATA_SWIZZLE
33743 * 0b00..No byte swapping.(Little endian)
33744 * 0b00..Little Endian byte ordering (same as NO_SWAP).
33745 * 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
33746 * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
33747 * 0b10..Swap half-words.
33748 * 0b11..Swap bytes within each half-word.
33749 */
33750#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) \
33751 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)
33752#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U)
33753#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U)
33754/*! INPUT_DATA_SWIZZLE
33755 * 0b00..No byte swapping.(Little endian)
33756 * 0b00..Little Endian byte ordering (same as NO_SWAP).
33757 * 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
33758 * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
33759 * 0b10..Swap half-words.
33760 * 0b11..Swap bytes within each half-word.
33761 */
33762#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) \
33763 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)
33764#define LCDIF_CTRL_SET_DATA_SELECT_MASK (0x10000U)
33765#define LCDIF_CTRL_SET_DATA_SELECT_SHIFT (16U)
33766/*! DATA_SELECT
33767 * 0b0..Command Mode. LCD_RS signal is Low.
33768 * 0b1..Data Mode. LCD_RS signal is High.
33769 */
33770#define LCDIF_CTRL_SET_DATA_SELECT(x) \
33771 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SELECT_SHIFT)) & LCDIF_CTRL_SET_DATA_SELECT_MASK)
33772#define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U)
33773#define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U)
33774#define LCDIF_CTRL_SET_DOTCLK_MODE(x) \
33775 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK)
33776#define LCDIF_CTRL_SET_VSYNC_MODE_MASK (0x40000U)
33777#define LCDIF_CTRL_SET_VSYNC_MODE_SHIFT (18U)
33778#define LCDIF_CTRL_SET_VSYNC_MODE(x) \
33779 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_SET_VSYNC_MODE_MASK)
33780#define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U)
33781#define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U)
33782#define LCDIF_CTRL_SET_BYPASS_COUNT(x) \
33783 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK)
33784#define LCDIF_CTRL_SET_DVI_MODE_MASK (0x100000U)
33785#define LCDIF_CTRL_SET_DVI_MODE_SHIFT (20U)
33786#define LCDIF_CTRL_SET_DVI_MODE(x) \
33787 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DVI_MODE_SHIFT)) & LCDIF_CTRL_SET_DVI_MODE_MASK)
33788#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U)
33789#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U)
33790#define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) \
33791 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)
33792#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U)
33793#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U)
33794/*! DATA_SHIFT_DIR
33795 * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
33796 * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
33797 */
33798#define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) \
33799 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)
33800#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U)
33801#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT (27U)
33802#define LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE(x) \
33803 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_SHIFT)) & \
33804 LCDIF_CTRL_SET_WAIT_FOR_VSYNC_EDGE_MASK)
33805#define LCDIF_CTRL_SET_READ_WRITEB_MASK (0x10000000U)
33806#define LCDIF_CTRL_SET_READ_WRITEB_SHIFT (28U)
33807#define LCDIF_CTRL_SET_READ_WRITEB(x) \
33808 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_READ_WRITEB_SHIFT)) & LCDIF_CTRL_SET_READ_WRITEB_MASK)
33809#define LCDIF_CTRL_SET_YCBCR422_INPUT_MASK (0x20000000U)
33810#define LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT (29U)
33811#define LCDIF_CTRL_SET_YCBCR422_INPUT(x) \
33812 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_SET_YCBCR422_INPUT_MASK)
33813#define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U)
33814#define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U)
33815#define LCDIF_CTRL_SET_CLKGATE(x) \
33816 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK)
33817#define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U)
33818#define LCDIF_CTRL_SET_SFTRST_SHIFT (31U)
33819#define LCDIF_CTRL_SET_SFTRST(x) \
33820 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK)
33821/*! @} */
33822
33823/*! @name CTRL_CLR - LCDIF General Control Register */
33824/*! @{ */
33825#define LCDIF_CTRL_CLR_RUN_MASK (0x1U)
33826#define LCDIF_CTRL_CLR_RUN_SHIFT (0U)
33827#define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)
33828#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U)
33829#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U)
33830/*! DATA_FORMAT_24_BIT
33831 * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
33832 * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
33833 * each byte do not contain any useful data, and should be dropped.
33834 */
33835#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) \
33836 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)
33837#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U)
33838#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U)
33839/*! DATA_FORMAT_18_BIT
33840 * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not
33841 * contain any useful data. 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666
33842 * and lower 14 bits do not contain any useful data.
33843 */
33844#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) \
33845 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)
33846#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U)
33847#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U)
33848#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) \
33849 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK)
33850#define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U)
33851#define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U)
33852#define LCDIF_CTRL_CLR_RSRVD0(x) \
33853 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK)
33854#define LCDIF_CTRL_CLR_MASTER_MASK (0x20U)
33855#define LCDIF_CTRL_CLR_MASTER_SHIFT (5U)
33856#define LCDIF_CTRL_CLR_MASTER(x) \
33857 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK)
33858#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
33859#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
33860#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) \
33861 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & \
33862 LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK)
33863#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK (0x80U)
33864#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT (7U)
33865#define LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC(x) \
33866 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_SHIFT)) & \
33867 LCDIF_CTRL_CLR_RGB_TO_YCBCR422_CSC_MASK)
33868#define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U)
33869#define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U)
33870/*! WORD_LENGTH
33871 * 0b00..Input data is 16 bits per pixel.
33872 * 0b01..Input data is 8 bits wide.
33873 * 0b10..Input data is 18 bits per pixel.
33874 * 0b11..Input data is 24 bits per pixel.
33875 */
33876#define LCDIF_CTRL_CLR_WORD_LENGTH(x) \
33877 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)
33878#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U)
33879#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U)
33880/*! LCD_DATABUS_WIDTH
33881 * 0b00..16-bit data bus mode.
33882 * 0b01..8-bit data bus mode.
33883 * 0b10..18-bit data bus mode.
33884 * 0b11..24-bit data bus mode.
33885 */
33886#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) \
33887 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)
33888#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U)
33889#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U)
33890/*! CSC_DATA_SWIZZLE
33891 * 0b00..No byte swapping.(Little endian)
33892 * 0b00..Little Endian byte ordering (same as NO_SWAP).
33893 * 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
33894 * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
33895 * 0b10..Swap half-words.
33896 * 0b11..Swap bytes within each half-word.
33897 */
33898#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) \
33899 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)
33900#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U)
33901#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U)
33902/*! INPUT_DATA_SWIZZLE
33903 * 0b00..No byte swapping.(Little endian)
33904 * 0b00..Little Endian byte ordering (same as NO_SWAP).
33905 * 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
33906 * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
33907 * 0b10..Swap half-words.
33908 * 0b11..Swap bytes within each half-word.
33909 */
33910#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) \
33911 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)
33912#define LCDIF_CTRL_CLR_DATA_SELECT_MASK (0x10000U)
33913#define LCDIF_CTRL_CLR_DATA_SELECT_SHIFT (16U)
33914/*! DATA_SELECT
33915 * 0b0..Command Mode. LCD_RS signal is Low.
33916 * 0b1..Data Mode. LCD_RS signal is High.
33917 */
33918#define LCDIF_CTRL_CLR_DATA_SELECT(x) \
33919 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SELECT_SHIFT)) & LCDIF_CTRL_CLR_DATA_SELECT_MASK)
33920#define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U)
33921#define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U)
33922#define LCDIF_CTRL_CLR_DOTCLK_MODE(x) \
33923 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK)
33924#define LCDIF_CTRL_CLR_VSYNC_MODE_MASK (0x40000U)
33925#define LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT (18U)
33926#define LCDIF_CTRL_CLR_VSYNC_MODE(x) \
33927 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_CLR_VSYNC_MODE_MASK)
33928#define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U)
33929#define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U)
33930#define LCDIF_CTRL_CLR_BYPASS_COUNT(x) \
33931 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK)
33932#define LCDIF_CTRL_CLR_DVI_MODE_MASK (0x100000U)
33933#define LCDIF_CTRL_CLR_DVI_MODE_SHIFT (20U)
33934#define LCDIF_CTRL_CLR_DVI_MODE(x) \
33935 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DVI_MODE_SHIFT)) & LCDIF_CTRL_CLR_DVI_MODE_MASK)
33936#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U)
33937#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U)
33938#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) \
33939 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)
33940#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U)
33941#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U)
33942/*! DATA_SHIFT_DIR
33943 * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
33944 * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
33945 */
33946#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) \
33947 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)
33948#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U)
33949#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT (27U)
33950#define LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE(x) \
33951 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_SHIFT)) & \
33952 LCDIF_CTRL_CLR_WAIT_FOR_VSYNC_EDGE_MASK)
33953#define LCDIF_CTRL_CLR_READ_WRITEB_MASK (0x10000000U)
33954#define LCDIF_CTRL_CLR_READ_WRITEB_SHIFT (28U)
33955#define LCDIF_CTRL_CLR_READ_WRITEB(x) \
33956 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_READ_WRITEB_SHIFT)) & LCDIF_CTRL_CLR_READ_WRITEB_MASK)
33957#define LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK (0x20000000U)
33958#define LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT (29U)
33959#define LCDIF_CTRL_CLR_YCBCR422_INPUT(x) \
33960 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_CLR_YCBCR422_INPUT_MASK)
33961#define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U)
33962#define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U)
33963#define LCDIF_CTRL_CLR_CLKGATE(x) \
33964 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK)
33965#define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U)
33966#define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U)
33967#define LCDIF_CTRL_CLR_SFTRST(x) \
33968 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK)
33969/*! @} */
33970
33971/*! @name CTRL_TOG - LCDIF General Control Register */
33972/*! @{ */
33973#define LCDIF_CTRL_TOG_RUN_MASK (0x1U)
33974#define LCDIF_CTRL_TOG_RUN_SHIFT (0U)
33975#define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)
33976#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U)
33977#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U)
33978/*! DATA_FORMAT_24_BIT
33979 * 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
33980 * 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
33981 * each byte do not contain any useful data, and should be dropped.
33982 */
33983#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) \
33984 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)
33985#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U)
33986#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U)
33987/*! DATA_FORMAT_18_BIT
33988 * 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not
33989 * contain any useful data. 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666
33990 * and lower 14 bits do not contain any useful data.
33991 */
33992#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) \
33993 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)
33994#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U)
33995#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U)
33996#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) \
33997 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK)
33998#define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U)
33999#define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U)
34000#define LCDIF_CTRL_TOG_RSRVD0(x) \
34001 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK)
34002#define LCDIF_CTRL_TOG_MASTER_MASK (0x20U)
34003#define LCDIF_CTRL_TOG_MASTER_SHIFT (5U)
34004#define LCDIF_CTRL_TOG_MASTER(x) \
34005 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK)
34006#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
34007#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
34008#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) \
34009 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & \
34010 LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK)
34011#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK (0x80U)
34012#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT (7U)
34013#define LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC(x) \
34014 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_SHIFT)) & \
34015 LCDIF_CTRL_TOG_RGB_TO_YCBCR422_CSC_MASK)
34016#define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U)
34017#define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U)
34018/*! WORD_LENGTH
34019 * 0b00..Input data is 16 bits per pixel.
34020 * 0b01..Input data is 8 bits wide.
34021 * 0b10..Input data is 18 bits per pixel.
34022 * 0b11..Input data is 24 bits per pixel.
34023 */
34024#define LCDIF_CTRL_TOG_WORD_LENGTH(x) \
34025 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)
34026#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U)
34027#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U)
34028/*! LCD_DATABUS_WIDTH
34029 * 0b00..16-bit data bus mode.
34030 * 0b01..8-bit data bus mode.
34031 * 0b10..18-bit data bus mode.
34032 * 0b11..24-bit data bus mode.
34033 */
34034#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) \
34035 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)
34036#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U)
34037#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U)
34038/*! CSC_DATA_SWIZZLE
34039 * 0b00..No byte swapping.(Little endian)
34040 * 0b00..Little Endian byte ordering (same as NO_SWAP).
34041 * 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
34042 * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
34043 * 0b10..Swap half-words.
34044 * 0b11..Swap bytes within each half-word.
34045 */
34046#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) \
34047 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)
34048#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U)
34049#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U)
34050/*! INPUT_DATA_SWIZZLE
34051 * 0b00..No byte swapping.(Little endian)
34052 * 0b00..Little Endian byte ordering (same as NO_SWAP).
34053 * 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
34054 * 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
34055 * 0b10..Swap half-words.
34056 * 0b11..Swap bytes within each half-word.
34057 */
34058#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) \
34059 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)
34060#define LCDIF_CTRL_TOG_DATA_SELECT_MASK (0x10000U)
34061#define LCDIF_CTRL_TOG_DATA_SELECT_SHIFT (16U)
34062/*! DATA_SELECT
34063 * 0b0..Command Mode. LCD_RS signal is Low.
34064 * 0b1..Data Mode. LCD_RS signal is High.
34065 */
34066#define LCDIF_CTRL_TOG_DATA_SELECT(x) \
34067 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SELECT_SHIFT)) & LCDIF_CTRL_TOG_DATA_SELECT_MASK)
34068#define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U)
34069#define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U)
34070#define LCDIF_CTRL_TOG_DOTCLK_MODE(x) \
34071 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK)
34072#define LCDIF_CTRL_TOG_VSYNC_MODE_MASK (0x40000U)
34073#define LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT (18U)
34074#define LCDIF_CTRL_TOG_VSYNC_MODE(x) \
34075 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_VSYNC_MODE_SHIFT)) & LCDIF_CTRL_TOG_VSYNC_MODE_MASK)
34076#define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U)
34077#define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U)
34078#define LCDIF_CTRL_TOG_BYPASS_COUNT(x) \
34079 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK)
34080#define LCDIF_CTRL_TOG_DVI_MODE_MASK (0x100000U)
34081#define LCDIF_CTRL_TOG_DVI_MODE_SHIFT (20U)
34082#define LCDIF_CTRL_TOG_DVI_MODE(x) \
34083 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DVI_MODE_SHIFT)) & LCDIF_CTRL_TOG_DVI_MODE_MASK)
34084#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U)
34085#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U)
34086#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) \
34087 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)
34088#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U)
34089#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U)
34090/*! DATA_SHIFT_DIR
34091 * 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
34092 * 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
34093 */
34094#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) \
34095 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)
34096#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK (0x8000000U)
34097#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT (27U)
34098#define LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE(x) \
34099 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_SHIFT)) & \
34100 LCDIF_CTRL_TOG_WAIT_FOR_VSYNC_EDGE_MASK)
34101#define LCDIF_CTRL_TOG_READ_WRITEB_MASK (0x10000000U)
34102#define LCDIF_CTRL_TOG_READ_WRITEB_SHIFT (28U)
34103#define LCDIF_CTRL_TOG_READ_WRITEB(x) \
34104 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_READ_WRITEB_SHIFT)) & LCDIF_CTRL_TOG_READ_WRITEB_MASK)
34105#define LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK (0x20000000U)
34106#define LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT (29U)
34107#define LCDIF_CTRL_TOG_YCBCR422_INPUT(x) \
34108 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_YCBCR422_INPUT_SHIFT)) & LCDIF_CTRL_TOG_YCBCR422_INPUT_MASK)
34109#define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U)
34110#define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U)
34111#define LCDIF_CTRL_TOG_CLKGATE(x) \
34112 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK)
34113#define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U)
34114#define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U)
34115#define LCDIF_CTRL_TOG_SFTRST(x) \
34116 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK)
34117/*! @} */
34118
34119/*! @name CTRL1 - LCDIF General Control1 Register */
34120/*! @{ */
34121#define LCDIF_CTRL1_RESET_MASK (0x1U)
34122#define LCDIF_CTRL1_RESET_SHIFT (0U)
34123/*! RESET
34124 * 0b0..LCD_RESET output signal is low.
34125 * 0b1..LCD_RESET output signal is high.
34126 */
34127#define LCDIF_CTRL1_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RESET_SHIFT)) & LCDIF_CTRL1_RESET_MASK)
34128#define LCDIF_CTRL1_MODE86_MASK (0x2U)
34129#define LCDIF_CTRL1_MODE86_SHIFT (1U)
34130/*! MODE86
34131 * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively.
34132 * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively.
34133 */
34134#define LCDIF_CTRL1_MODE86(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_MODE86_SHIFT)) & LCDIF_CTRL1_MODE86_MASK)
34135#define LCDIF_CTRL1_BUSY_ENABLE_MASK (0x4U)
34136#define LCDIF_CTRL1_BUSY_ENABLE_SHIFT (2U)
34137/*! BUSY_ENABLE
34138 * 0b0..The busy signal from the LCD controller will be ignored.
34139 * 0b1..Enable the use of the busy signal from the LCD controller.
34140 */
34141#define LCDIF_CTRL1_BUSY_ENABLE(x) \
34142 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_BUSY_ENABLE_MASK)
34143#define LCDIF_CTRL1_RSRVD0_MASK (0xF8U)
34144#define LCDIF_CTRL1_RSRVD0_SHIFT (3U)
34145#define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)
34146#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U)
34147#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U)
34148/*! VSYNC_EDGE_IRQ
34149 * 0b0..No Interrupt Request Pending.
34150 * 0b1..Interrupt Request Pending.
34151 */
34152#define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) \
34153 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)
34154#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U)
34155#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U)
34156/*! CUR_FRAME_DONE_IRQ
34157 * 0b0..No Interrupt Request Pending.
34158 * 0b1..Interrupt Request Pending.
34159 */
34160#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) \
34161 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)
34162#define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U)
34163#define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U)
34164/*! UNDERFLOW_IRQ
34165 * 0b0..No Interrupt Request Pending.
34166 * 0b1..Interrupt Request Pending.
34167 */
34168#define LCDIF_CTRL1_UNDERFLOW_IRQ(x) \
34169 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)
34170#define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U)
34171#define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U)
34172/*! OVERFLOW_IRQ
34173 * 0b0..No Interrupt Request Pending.
34174 * 0b1..Interrupt Request Pending.
34175 */
34176#define LCDIF_CTRL1_OVERFLOW_IRQ(x) \
34177 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)
34178#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
34179#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
34180#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) \
34181 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)
34182#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
34183#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
34184#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) \
34185 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK)
34186#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U)
34187#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U)
34188#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) \
34189 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK)
34190#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U)
34191#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U)
34192#define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) \
34193 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK)
34194#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U)
34195#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U)
34196#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) \
34197 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
34198#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
34199#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
34200#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) \
34201 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & \
34202 LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK)
34203#define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U)
34204#define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U)
34205#define LCDIF_CTRL1_FIFO_CLEAR(x) \
34206 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK)
34207#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
34208#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
34209#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) \
34210 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & \
34211 LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK)
34212#define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U)
34213#define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U)
34214#define LCDIF_CTRL1_INTERLACE_FIELDS(x) \
34215 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK)
34216#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
34217#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U)
34218#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) \
34219 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)
34220#define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U)
34221#define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U)
34222/*! BM_ERROR_IRQ
34223 * 0b0..No Interrupt Request Pending.
34224 * 0b1..Interrupt Request Pending.
34225 */
34226#define LCDIF_CTRL1_BM_ERROR_IRQ(x) \
34227 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)
34228#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U)
34229#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U)
34230#define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) \
34231 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK)
34232#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK (0x8000000U)
34233#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT (27U)
34234#define LCDIF_CTRL1_COMBINE_MPU_WR_STRB(x) \
34235 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_COMBINE_MPU_WR_STRB_SHIFT)) & LCDIF_CTRL1_COMBINE_MPU_WR_STRB_MASK)
34236/*! @} */
34237
34238/*! @name CTRL1_SET - LCDIF General Control1 Register */
34239/*! @{ */
34240#define LCDIF_CTRL1_SET_RESET_MASK (0x1U)
34241#define LCDIF_CTRL1_SET_RESET_SHIFT (0U)
34242/*! RESET
34243 * 0b0..LCD_RESET output signal is low.
34244 * 0b1..LCD_RESET output signal is high.
34245 */
34246#define LCDIF_CTRL1_SET_RESET(x) \
34247 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RESET_SHIFT)) & LCDIF_CTRL1_SET_RESET_MASK)
34248#define LCDIF_CTRL1_SET_MODE86_MASK (0x2U)
34249#define LCDIF_CTRL1_SET_MODE86_SHIFT (1U)
34250/*! MODE86
34251 * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively.
34252 * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively.
34253 */
34254#define LCDIF_CTRL1_SET_MODE86(x) \
34255 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_MODE86_SHIFT)) & LCDIF_CTRL1_SET_MODE86_MASK)
34256#define LCDIF_CTRL1_SET_BUSY_ENABLE_MASK (0x4U)
34257#define LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT (2U)
34258/*! BUSY_ENABLE
34259 * 0b0..The busy signal from the LCD controller will be ignored.
34260 * 0b1..Enable the use of the busy signal from the LCD controller.
34261 */
34262#define LCDIF_CTRL1_SET_BUSY_ENABLE(x) \
34263 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_SET_BUSY_ENABLE_MASK)
34264#define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U)
34265#define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U)
34266#define LCDIF_CTRL1_SET_RSRVD0(x) \
34267 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)
34268#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U)
34269#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U)
34270/*! VSYNC_EDGE_IRQ
34271 * 0b0..No Interrupt Request Pending.
34272 * 0b1..Interrupt Request Pending.
34273 */
34274#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) \
34275 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)
34276#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U)
34277#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)
34278/*! CUR_FRAME_DONE_IRQ
34279 * 0b0..No Interrupt Request Pending.
34280 * 0b1..Interrupt Request Pending.
34281 */
34282#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) \
34283 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & \
34284 LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)
34285#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U)
34286#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U)
34287/*! UNDERFLOW_IRQ
34288 * 0b0..No Interrupt Request Pending.
34289 * 0b1..Interrupt Request Pending.
34290 */
34291#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) \
34292 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)
34293#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U)
34294#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U)
34295/*! OVERFLOW_IRQ
34296 * 0b0..No Interrupt Request Pending.
34297 * 0b1..Interrupt Request Pending.
34298 */
34299#define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) \
34300 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)
34301#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
34302#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
34303#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) \
34304 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK)
34305#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
34306#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
34307#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) \
34308 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & \
34309 LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK)
34310#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U)
34311#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U)
34312#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) \
34313 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK)
34314#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U)
34315#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U)
34316#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) \
34317 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK)
34318#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U)
34319#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U)
34320#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) \
34321 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & \
34322 LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)
34323#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
34324#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
34325#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) \
34326 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & \
34327 LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK)
34328#define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U)
34329#define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U)
34330#define LCDIF_CTRL1_SET_FIFO_CLEAR(x) \
34331 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK)
34332#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
34333#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
34334#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) \
34335 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & \
34336 LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK)
34337#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U)
34338#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U)
34339#define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) \
34340 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK)
34341#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
34342#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U)
34343#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) \
34344 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & \
34345 LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)
34346#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U)
34347#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U)
34348/*! BM_ERROR_IRQ
34349 * 0b0..No Interrupt Request Pending.
34350 * 0b1..Interrupt Request Pending.
34351 */
34352#define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) \
34353 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)
34354#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U)
34355#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U)
34356#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) \
34357 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK)
34358#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK (0x8000000U)
34359#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT (27U)
34360#define LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB(x) \
34361 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_SHIFT)) & \
34362 LCDIF_CTRL1_SET_COMBINE_MPU_WR_STRB_MASK)
34363/*! @} */
34364
34365/*! @name CTRL1_CLR - LCDIF General Control1 Register */
34366/*! @{ */
34367#define LCDIF_CTRL1_CLR_RESET_MASK (0x1U)
34368#define LCDIF_CTRL1_CLR_RESET_SHIFT (0U)
34369/*! RESET
34370 * 0b0..LCD_RESET output signal is low.
34371 * 0b1..LCD_RESET output signal is high.
34372 */
34373#define LCDIF_CTRL1_CLR_RESET(x) \
34374 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RESET_SHIFT)) & LCDIF_CTRL1_CLR_RESET_MASK)
34375#define LCDIF_CTRL1_CLR_MODE86_MASK (0x2U)
34376#define LCDIF_CTRL1_CLR_MODE86_SHIFT (1U)
34377/*! MODE86
34378 * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively.
34379 * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively.
34380 */
34381#define LCDIF_CTRL1_CLR_MODE86(x) \
34382 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_MODE86_SHIFT)) & LCDIF_CTRL1_CLR_MODE86_MASK)
34383#define LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK (0x4U)
34384#define LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT (2U)
34385/*! BUSY_ENABLE
34386 * 0b0..The busy signal from the LCD controller will be ignored.
34387 * 0b1..Enable the use of the busy signal from the LCD controller.
34388 */
34389#define LCDIF_CTRL1_CLR_BUSY_ENABLE(x) \
34390 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_CLR_BUSY_ENABLE_MASK)
34391#define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U)
34392#define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U)
34393#define LCDIF_CTRL1_CLR_RSRVD0(x) \
34394 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
34395#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U)
34396#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U)
34397/*! VSYNC_EDGE_IRQ
34398 * 0b0..No Interrupt Request Pending.
34399 * 0b1..Interrupt Request Pending.
34400 */
34401#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) \
34402 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)
34403#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U)
34404#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)
34405/*! CUR_FRAME_DONE_IRQ
34406 * 0b0..No Interrupt Request Pending.
34407 * 0b1..Interrupt Request Pending.
34408 */
34409#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) \
34410 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & \
34411 LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)
34412#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U)
34413#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U)
34414/*! UNDERFLOW_IRQ
34415 * 0b0..No Interrupt Request Pending.
34416 * 0b1..Interrupt Request Pending.
34417 */
34418#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) \
34419 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)
34420#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U)
34421#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U)
34422/*! OVERFLOW_IRQ
34423 * 0b0..No Interrupt Request Pending.
34424 * 0b1..Interrupt Request Pending.
34425 */
34426#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) \
34427 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)
34428#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
34429#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
34430#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) \
34431 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK)
34432#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
34433#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
34434#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) \
34435 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & \
34436 LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK)
34437#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U)
34438#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U)
34439#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) \
34440 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK)
34441#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U)
34442#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U)
34443#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) \
34444 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK)
34445#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U)
34446#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U)
34447#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) \
34448 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & \
34449 LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)
34450#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
34451#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
34452#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) \
34453 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & \
34454 LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK)
34455#define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U)
34456#define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U)
34457#define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) \
34458 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK)
34459#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
34460#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
34461#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) \
34462 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & \
34463 LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK)
34464#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U)
34465#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U)
34466#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) \
34467 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK)
34468#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
34469#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U)
34470#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) \
34471 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & \
34472 LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)
34473#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U)
34474#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U)
34475/*! BM_ERROR_IRQ
34476 * 0b0..No Interrupt Request Pending.
34477 * 0b1..Interrupt Request Pending.
34478 */
34479#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) \
34480 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)
34481#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U)
34482#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U)
34483#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) \
34484 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK)
34485#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK (0x8000000U)
34486#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT (27U)
34487#define LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB(x) \
34488 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_SHIFT)) & \
34489 LCDIF_CTRL1_CLR_COMBINE_MPU_WR_STRB_MASK)
34490/*! @} */
34491
34492/*! @name CTRL1_TOG - LCDIF General Control1 Register */
34493/*! @{ */
34494#define LCDIF_CTRL1_TOG_RESET_MASK (0x1U)
34495#define LCDIF_CTRL1_TOG_RESET_SHIFT (0U)
34496/*! RESET
34497 * 0b0..LCD_RESET output signal is low.
34498 * 0b1..LCD_RESET output signal is high.
34499 */
34500#define LCDIF_CTRL1_TOG_RESET(x) \
34501 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RESET_SHIFT)) & LCDIF_CTRL1_TOG_RESET_MASK)
34502#define LCDIF_CTRL1_TOG_MODE86_MASK (0x2U)
34503#define LCDIF_CTRL1_TOG_MODE86_SHIFT (1U)
34504/*! MODE86
34505 * 0b0..Pins LCD_WR_RWn and LCD_RD_E function as active low WR and active low RD signals respectively.
34506 * 0b1..Pins LCD_WR_RWn and LCD_RD_E function as Read/Write and active high Enable signals respectively.
34507 */
34508#define LCDIF_CTRL1_TOG_MODE86(x) \
34509 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_MODE86_SHIFT)) & LCDIF_CTRL1_TOG_MODE86_MASK)
34510#define LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK (0x4U)
34511#define LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT (2U)
34512/*! BUSY_ENABLE
34513 * 0b0..The busy signal from the LCD controller will be ignored.
34514 * 0b1..Enable the use of the busy signal from the LCD controller.
34515 */
34516#define LCDIF_CTRL1_TOG_BUSY_ENABLE(x) \
34517 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BUSY_ENABLE_SHIFT)) & LCDIF_CTRL1_TOG_BUSY_ENABLE_MASK)
34518#define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U)
34519#define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U)
34520#define LCDIF_CTRL1_TOG_RSRVD0(x) \
34521 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)
34522#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U)
34523#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U)
34524/*! VSYNC_EDGE_IRQ
34525 * 0b0..No Interrupt Request Pending.
34526 * 0b1..Interrupt Request Pending.
34527 */
34528#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) \
34529 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)
34530#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U)
34531#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)
34532/*! CUR_FRAME_DONE_IRQ
34533 * 0b0..No Interrupt Request Pending.
34534 * 0b1..Interrupt Request Pending.
34535 */
34536#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) \
34537 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & \
34538 LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)
34539#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U)
34540#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U)
34541/*! UNDERFLOW_IRQ
34542 * 0b0..No Interrupt Request Pending.
34543 * 0b1..Interrupt Request Pending.
34544 */
34545#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) \
34546 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)
34547#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U)
34548#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U)
34549/*! OVERFLOW_IRQ
34550 * 0b0..No Interrupt Request Pending.
34551 * 0b1..Interrupt Request Pending.
34552 */
34553#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) \
34554 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)
34555#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
34556#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
34557#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) \
34558 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK)
34559#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
34560#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
34561#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) \
34562 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & \
34563 LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK)
34564#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U)
34565#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U)
34566#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) \
34567 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK)
34568#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U)
34569#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U)
34570#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) \
34571 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK)
34572#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U)
34573#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U)
34574#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) \
34575 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & \
34576 LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)
34577#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
34578#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
34579#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) \
34580 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & \
34581 LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK)
34582#define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U)
34583#define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U)
34584#define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) \
34585 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK)
34586#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
34587#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
34588#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) \
34589 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & \
34590 LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK)
34591#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U)
34592#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U)
34593#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) \
34594 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK)
34595#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
34596#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U)
34597#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) \
34598 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & \
34599 LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)
34600#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U)
34601#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U)
34602/*! BM_ERROR_IRQ
34603 * 0b0..No Interrupt Request Pending.
34604 * 0b1..Interrupt Request Pending.
34605 */
34606#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) \
34607 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)
34608#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U)
34609#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U)
34610#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) \
34611 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK)
34612#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK (0x8000000U)
34613#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT (27U)
34614#define LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB(x) \
34615 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_SHIFT)) & \
34616 LCDIF_CTRL1_TOG_COMBINE_MPU_WR_STRB_MASK)
34617/*! @} */
34618
34619/*! @name CTRL2 - LCDIF General Control2 Register */
34620/*! @{ */
34621#define LCDIF_CTRL2_RSRVD0_MASK (0x1U)
34622#define LCDIF_CTRL2_RSRVD0_SHIFT (0U)
34623#define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)
34624#define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0xEU)
34625#define LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT (1U)
34626#define LCDIF_CTRL2_INITIAL_DUMMY_READ(x) \
34627 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_INITIAL_DUMMY_READ_SHIFT)) & LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK)
34628#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U)
34629#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U)
34630#define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS(x) \
34631 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & \
34632 LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK)
34633#define LCDIF_CTRL2_RSRVD1_MASK (0x80U)
34634#define LCDIF_CTRL2_RSRVD1_SHIFT (7U)
34635#define LCDIF_CTRL2_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD1_SHIFT)) & LCDIF_CTRL2_RSRVD1_MASK)
34636#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK (0x100U)
34637#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT (8U)
34638#define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT(x) \
34639 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_SHIFT)) & LCDIF_CTRL2_READ_MODE_6_BIT_INPUT_MASK)
34640#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U)
34641#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U)
34642#define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) \
34643 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & \
34644 LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK)
34645#define LCDIF_CTRL2_READ_PACK_DIR_MASK (0x400U)
34646#define LCDIF_CTRL2_READ_PACK_DIR_SHIFT (10U)
34647#define LCDIF_CTRL2_READ_PACK_DIR(x) \
34648 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_READ_PACK_DIR_MASK)
34649#define LCDIF_CTRL2_RSRVD2_MASK (0x800U)
34650#define LCDIF_CTRL2_RSRVD2_SHIFT (11U)
34651#define LCDIF_CTRL2_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD2_SHIFT)) & LCDIF_CTRL2_RSRVD2_MASK)
34652#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U)
34653#define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U)
34654/*! EVEN_LINE_PATTERN
34655 * 0b000..RGB
34656 * 0b001..RBG
34657 * 0b010..GBR
34658 * 0b011..GRB
34659 * 0b100..BRG
34660 * 0b101..BGR
34661 */
34662#define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) \
34663 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)
34664#define LCDIF_CTRL2_RSRVD3_MASK (0x8000U)
34665#define LCDIF_CTRL2_RSRVD3_SHIFT (15U)
34666#define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)
34667#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U)
34668#define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U)
34669/*! ODD_LINE_PATTERN
34670 * 0b000..RGB
34671 * 0b001..RBG
34672 * 0b010..GBR
34673 * 0b011..GRB
34674 * 0b100..BRG
34675 * 0b101..BGR
34676 */
34677#define LCDIF_CTRL2_ODD_LINE_PATTERN(x) \
34678 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)
34679#define LCDIF_CTRL2_RSRVD4_MASK (0x80000U)
34680#define LCDIF_CTRL2_RSRVD4_SHIFT (19U)
34681#define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK)
34682#define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U)
34683#define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U)
34684#define LCDIF_CTRL2_BURST_LEN_8(x) \
34685 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)
34686#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U)
34687#define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U)
34688/*! OUTSTANDING_REQS
34689 * 0b000..REQ_1
34690 * 0b001..REQ_2
34691 * 0b010..REQ_4
34692 * 0b011..REQ_8
34693 * 0b100..REQ_16
34694 */
34695#define LCDIF_CTRL2_OUTSTANDING_REQS(x) \
34696 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)
34697#define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U)
34698#define LCDIF_CTRL2_RSRVD5_SHIFT (24U)
34699#define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK)
34700/*! @} */
34701
34702/*! @name CTRL2_SET - LCDIF General Control2 Register */
34703/*! @{ */
34704#define LCDIF_CTRL2_SET_RSRVD0_MASK (0x1U)
34705#define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U)
34706#define LCDIF_CTRL2_SET_RSRVD0(x) \
34707 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)
34708#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK (0xEU)
34709#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT (1U)
34710#define LCDIF_CTRL2_SET_INITIAL_DUMMY_READ(x) \
34711 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_SHIFT)) & \
34712 LCDIF_CTRL2_SET_INITIAL_DUMMY_READ_MASK)
34713#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U)
34714#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U)
34715#define LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS(x) \
34716 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & \
34717 LCDIF_CTRL2_SET_READ_MODE_NUM_PACKED_SUBWORDS_MASK)
34718#define LCDIF_CTRL2_SET_RSRVD1_MASK (0x80U)
34719#define LCDIF_CTRL2_SET_RSRVD1_SHIFT (7U)
34720#define LCDIF_CTRL2_SET_RSRVD1(x) \
34721 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD1_SHIFT)) & LCDIF_CTRL2_SET_RSRVD1_MASK)
34722#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK (0x100U)
34723#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT (8U)
34724#define LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT(x) \
34725 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_SHIFT)) & \
34726 LCDIF_CTRL2_SET_READ_MODE_6_BIT_INPUT_MASK)
34727#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U)
34728#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U)
34729#define LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) \
34730 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & \
34731 LCDIF_CTRL2_SET_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK)
34732#define LCDIF_CTRL2_SET_READ_PACK_DIR_MASK (0x400U)
34733#define LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT (10U)
34734#define LCDIF_CTRL2_SET_READ_PACK_DIR(x) \
34735 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_SET_READ_PACK_DIR_MASK)
34736#define LCDIF_CTRL2_SET_RSRVD2_MASK (0x800U)
34737#define LCDIF_CTRL2_SET_RSRVD2_SHIFT (11U)
34738#define LCDIF_CTRL2_SET_RSRVD2(x) \
34739 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD2_SHIFT)) & LCDIF_CTRL2_SET_RSRVD2_MASK)
34740#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U)
34741#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U)
34742/*! EVEN_LINE_PATTERN
34743 * 0b000..RGB
34744 * 0b001..RBG
34745 * 0b010..GBR
34746 * 0b011..GRB
34747 * 0b100..BRG
34748 * 0b101..BGR
34749 */
34750#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) \
34751 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)
34752#define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U)
34753#define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U)
34754#define LCDIF_CTRL2_SET_RSRVD3(x) \
34755 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)
34756#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U)
34757#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U)
34758/*! ODD_LINE_PATTERN
34759 * 0b000..RGB
34760 * 0b001..RBG
34761 * 0b010..GBR
34762 * 0b011..GRB
34763 * 0b100..BRG
34764 * 0b101..BGR
34765 */
34766#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) \
34767 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)
34768#define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U)
34769#define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U)
34770#define LCDIF_CTRL2_SET_RSRVD4(x) \
34771 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK)
34772#define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U)
34773#define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U)
34774#define LCDIF_CTRL2_SET_BURST_LEN_8(x) \
34775 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)
34776#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U)
34777#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U)
34778/*! OUTSTANDING_REQS
34779 * 0b000..REQ_1
34780 * 0b001..REQ_2
34781 * 0b010..REQ_4
34782 * 0b011..REQ_8
34783 * 0b100..REQ_16
34784 */
34785#define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) \
34786 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)
34787#define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U)
34788#define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U)
34789#define LCDIF_CTRL2_SET_RSRVD5(x) \
34790 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK)
34791/*! @} */
34792
34793/*! @name CTRL2_CLR - LCDIF General Control2 Register */
34794/*! @{ */
34795#define LCDIF_CTRL2_CLR_RSRVD0_MASK (0x1U)
34796#define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U)
34797#define LCDIF_CTRL2_CLR_RSRVD0(x) \
34798 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)
34799#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK (0xEU)
34800#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT (1U)
34801#define LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ(x) \
34802 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_SHIFT)) & \
34803 LCDIF_CTRL2_CLR_INITIAL_DUMMY_READ_MASK)
34804#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U)
34805#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U)
34806#define LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS(x) \
34807 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & \
34808 LCDIF_CTRL2_CLR_READ_MODE_NUM_PACKED_SUBWORDS_MASK)
34809#define LCDIF_CTRL2_CLR_RSRVD1_MASK (0x80U)
34810#define LCDIF_CTRL2_CLR_RSRVD1_SHIFT (7U)
34811#define LCDIF_CTRL2_CLR_RSRVD1(x) \
34812 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD1_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD1_MASK)
34813#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK (0x100U)
34814#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT (8U)
34815#define LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT(x) \
34816 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_SHIFT)) & \
34817 LCDIF_CTRL2_CLR_READ_MODE_6_BIT_INPUT_MASK)
34818#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U)
34819#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U)
34820#define LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) \
34821 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & \
34822 LCDIF_CTRL2_CLR_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK)
34823#define LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK (0x400U)
34824#define LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT (10U)
34825#define LCDIF_CTRL2_CLR_READ_PACK_DIR(x) \
34826 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_CLR_READ_PACK_DIR_MASK)
34827#define LCDIF_CTRL2_CLR_RSRVD2_MASK (0x800U)
34828#define LCDIF_CTRL2_CLR_RSRVD2_SHIFT (11U)
34829#define LCDIF_CTRL2_CLR_RSRVD2(x) \
34830 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD2_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD2_MASK)
34831#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U)
34832#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U)
34833/*! EVEN_LINE_PATTERN
34834 * 0b000..RGB
34835 * 0b001..RBG
34836 * 0b010..GBR
34837 * 0b011..GRB
34838 * 0b100..BRG
34839 * 0b101..BGR
34840 */
34841#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) \
34842 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)
34843#define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U)
34844#define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U)
34845#define LCDIF_CTRL2_CLR_RSRVD3(x) \
34846 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)
34847#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U)
34848#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U)
34849/*! ODD_LINE_PATTERN
34850 * 0b000..RGB
34851 * 0b001..RBG
34852 * 0b010..GBR
34853 * 0b011..GRB
34854 * 0b100..BRG
34855 * 0b101..BGR
34856 */
34857#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) \
34858 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)
34859#define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U)
34860#define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U)
34861#define LCDIF_CTRL2_CLR_RSRVD4(x) \
34862 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK)
34863#define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U)
34864#define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U)
34865#define LCDIF_CTRL2_CLR_BURST_LEN_8(x) \
34866 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)
34867#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U)
34868#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U)
34869/*! OUTSTANDING_REQS
34870 * 0b000..REQ_1
34871 * 0b001..REQ_2
34872 * 0b010..REQ_4
34873 * 0b011..REQ_8
34874 * 0b100..REQ_16
34875 */
34876#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) \
34877 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)
34878#define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U)
34879#define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U)
34880#define LCDIF_CTRL2_CLR_RSRVD5(x) \
34881 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK)
34882/*! @} */
34883
34884/*! @name CTRL2_TOG - LCDIF General Control2 Register */
34885/*! @{ */
34886#define LCDIF_CTRL2_TOG_RSRVD0_MASK (0x1U)
34887#define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U)
34888#define LCDIF_CTRL2_TOG_RSRVD0(x) \
34889 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)
34890#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK (0xEU)
34891#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT (1U)
34892#define LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ(x) \
34893 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_SHIFT)) & \
34894 LCDIF_CTRL2_TOG_INITIAL_DUMMY_READ_MASK)
34895#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x70U)
34896#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT (4U)
34897#define LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS(x) \
34898 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_SHIFT)) & \
34899 LCDIF_CTRL2_TOG_READ_MODE_NUM_PACKED_SUBWORDS_MASK)
34900#define LCDIF_CTRL2_TOG_RSRVD1_MASK (0x80U)
34901#define LCDIF_CTRL2_TOG_RSRVD1_SHIFT (7U)
34902#define LCDIF_CTRL2_TOG_RSRVD1(x) \
34903 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD1_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD1_MASK)
34904#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK (0x100U)
34905#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT (8U)
34906#define LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT(x) \
34907 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_SHIFT)) & \
34908 LCDIF_CTRL2_TOG_READ_MODE_6_BIT_INPUT_MASK)
34909#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK (0x200U)
34910#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT (9U)
34911#define LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT(x) \
34912 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_SHIFT)) & \
34913 LCDIF_CTRL2_TOG_READ_MODE_OUTPUT_IN_RGB_FORMAT_MASK)
34914#define LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK (0x400U)
34915#define LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT (10U)
34916#define LCDIF_CTRL2_TOG_READ_PACK_DIR(x) \
34917 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_READ_PACK_DIR_SHIFT)) & LCDIF_CTRL2_TOG_READ_PACK_DIR_MASK)
34918#define LCDIF_CTRL2_TOG_RSRVD2_MASK (0x800U)
34919#define LCDIF_CTRL2_TOG_RSRVD2_SHIFT (11U)
34920#define LCDIF_CTRL2_TOG_RSRVD2(x) \
34921 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD2_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD2_MASK)
34922#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U)
34923#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U)
34924/*! EVEN_LINE_PATTERN
34925 * 0b000..RGB
34926 * 0b001..RBG
34927 * 0b010..GBR
34928 * 0b011..GRB
34929 * 0b100..BRG
34930 * 0b101..BGR
34931 */
34932#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) \
34933 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)
34934#define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U)
34935#define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U)
34936#define LCDIF_CTRL2_TOG_RSRVD3(x) \
34937 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)
34938#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U)
34939#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U)
34940/*! ODD_LINE_PATTERN
34941 * 0b000..RGB
34942 * 0b001..RBG
34943 * 0b010..GBR
34944 * 0b011..GRB
34945 * 0b100..BRG
34946 * 0b101..BGR
34947 */
34948#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) \
34949 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)
34950#define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U)
34951#define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U)
34952#define LCDIF_CTRL2_TOG_RSRVD4(x) \
34953 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK)
34954#define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U)
34955#define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U)
34956#define LCDIF_CTRL2_TOG_BURST_LEN_8(x) \
34957 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)
34958#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U)
34959#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U)
34960/*! OUTSTANDING_REQS
34961 * 0b000..REQ_1
34962 * 0b001..REQ_2
34963 * 0b010..REQ_4
34964 * 0b011..REQ_8
34965 * 0b100..REQ_16
34966 */
34967#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) \
34968 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)
34969#define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U)
34970#define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U)
34971#define LCDIF_CTRL2_TOG_RSRVD5(x) \
34972 (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
34973/*! @} */
34974
34975/*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */
34976/*! @{ */
34977#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU)
34978#define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U)
34979#define LCDIF_TRANSFER_COUNT_H_COUNT(x) \
34980 (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
34981#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U)
34982#define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U)
34983#define LCDIF_TRANSFER_COUNT_V_COUNT(x) \
34984 (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
34985/*! @} */
34986
34987/*! @name CUR_BUF - LCD Interface Current Buffer Address Register */
34988/*! @{ */
34989#define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU)
34990#define LCDIF_CUR_BUF_ADDR_SHIFT (0U)
34991#define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK)
34992/*! @} */
34993
34994/*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */
34995/*! @{ */
34996#define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU)
34997#define LCDIF_NEXT_BUF_ADDR_SHIFT (0U)
34998#define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK)
34999/*! @} */
35000
35001/*! @name TIMING - LCD Interface Timing Register */
35002/*! @{ */
35003#define LCDIF_TIMING_DATA_SETUP_MASK (0xFFU)
35004#define LCDIF_TIMING_DATA_SETUP_SHIFT (0U)
35005#define LCDIF_TIMING_DATA_SETUP(x) \
35006 (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_SETUP_SHIFT)) & LCDIF_TIMING_DATA_SETUP_MASK)
35007#define LCDIF_TIMING_DATA_HOLD_MASK (0xFF00U)
35008#define LCDIF_TIMING_DATA_HOLD_SHIFT (8U)
35009#define LCDIF_TIMING_DATA_HOLD(x) \
35010 (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_DATA_HOLD_SHIFT)) & LCDIF_TIMING_DATA_HOLD_MASK)
35011#define LCDIF_TIMING_CMD_SETUP_MASK (0xFF0000U)
35012#define LCDIF_TIMING_CMD_SETUP_SHIFT (16U)
35013#define LCDIF_TIMING_CMD_SETUP(x) \
35014 (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_SETUP_SHIFT)) & LCDIF_TIMING_CMD_SETUP_MASK)
35015#define LCDIF_TIMING_CMD_HOLD_MASK (0xFF000000U)
35016#define LCDIF_TIMING_CMD_HOLD_SHIFT (24U)
35017#define LCDIF_TIMING_CMD_HOLD(x) \
35018 (((uint32_t)(((uint32_t)(x)) << LCDIF_TIMING_CMD_HOLD_SHIFT)) & LCDIF_TIMING_CMD_HOLD_MASK)
35019/*! @} */
35020
35021/*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
35022/*! @{ */
35023#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
35024#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U)
35025#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) \
35026 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
35027#define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U)
35028#define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U)
35029#define LCDIF_VDCTRL0_HALF_LINE_MODE(x) \
35030 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK)
35031#define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U)
35032#define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U)
35033#define LCDIF_VDCTRL0_HALF_LINE(x) \
35034 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK)
35035#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
35036#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
35037#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) \
35038 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & \
35039 LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK)
35040#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U)
35041#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U)
35042#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) \
35043 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK)
35044#define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U)
35045#define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U)
35046#define LCDIF_VDCTRL0_RSRVD1(x) \
35047 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK)
35048#define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U)
35049#define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U)
35050#define LCDIF_VDCTRL0_ENABLE_POL(x) \
35051 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK)
35052#define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U)
35053#define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U)
35054#define LCDIF_VDCTRL0_DOTCLK_POL(x) \
35055 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK)
35056#define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U)
35057#define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U)
35058#define LCDIF_VDCTRL0_HSYNC_POL(x) \
35059 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK)
35060#define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U)
35061#define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U)
35062#define LCDIF_VDCTRL0_VSYNC_POL(x) \
35063 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK)
35064#define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U)
35065#define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U)
35066#define LCDIF_VDCTRL0_ENABLE_PRESENT(x) \
35067 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK)
35068#define LCDIF_VDCTRL0_VSYNC_OEB_MASK (0x20000000U)
35069#define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT (29U)
35070/*! VSYNC_OEB
35071 * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
35072 * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
35073 */
35074#define LCDIF_VDCTRL0_VSYNC_OEB(x) \
35075 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK)
35076#define LCDIF_VDCTRL0_RSRVD2_MASK (0xC0000000U)
35077#define LCDIF_VDCTRL0_RSRVD2_SHIFT (30U)
35078#define LCDIF_VDCTRL0_RSRVD2(x) \
35079 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK)
35080/*! @} */
35081
35082/*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
35083/*! @{ */
35084#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
35085#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U)
35086#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) \
35087 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & \
35088 LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)
35089#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U)
35090#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U)
35091#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) \
35092 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK)
35093#define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U)
35094#define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U)
35095#define LCDIF_VDCTRL0_SET_HALF_LINE(x) \
35096 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK)
35097#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
35098#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
35099#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) \
35100 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & \
35101 LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK)
35102#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U)
35103#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U)
35104#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) \
35105 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & \
35106 LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK)
35107#define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U)
35108#define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U)
35109#define LCDIF_VDCTRL0_SET_RSRVD1(x) \
35110 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK)
35111#define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U)
35112#define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U)
35113#define LCDIF_VDCTRL0_SET_ENABLE_POL(x) \
35114 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK)
35115#define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U)
35116#define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U)
35117#define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) \
35118 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK)
35119#define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U)
35120#define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U)
35121#define LCDIF_VDCTRL0_SET_HSYNC_POL(x) \
35122 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK)
35123#define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U)
35124#define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U)
35125#define LCDIF_VDCTRL0_SET_VSYNC_POL(x) \
35126 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK)
35127#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U)
35128#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U)
35129#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) \
35130 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK)
35131#define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK (0x20000000U)
35132#define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT (29U)
35133/*! VSYNC_OEB
35134 * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
35135 * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
35136 */
35137#define LCDIF_VDCTRL0_SET_VSYNC_OEB(x) \
35138 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK)
35139#define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xC0000000U)
35140#define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (30U)
35141#define LCDIF_VDCTRL0_SET_RSRVD2(x) \
35142 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK)
35143/*! @} */
35144
35145/*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
35146/*! @{ */
35147#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
35148#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U)
35149#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) \
35150 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & \
35151 LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)
35152#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U)
35153#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U)
35154#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) \
35155 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK)
35156#define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U)
35157#define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U)
35158#define LCDIF_VDCTRL0_CLR_HALF_LINE(x) \
35159 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK)
35160#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
35161#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
35162#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) \
35163 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & \
35164 LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK)
35165#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U)
35166#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U)
35167#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) \
35168 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & \
35169 LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK)
35170#define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U)
35171#define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U)
35172#define LCDIF_VDCTRL0_CLR_RSRVD1(x) \
35173 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK)
35174#define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U)
35175#define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U)
35176#define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) \
35177 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK)
35178#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U)
35179#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U)
35180#define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) \
35181 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK)
35182#define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U)
35183#define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U)
35184#define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) \
35185 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK)
35186#define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U)
35187#define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U)
35188#define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) \
35189 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK)
35190#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U)
35191#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U)
35192#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) \
35193 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK)
35194#define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK (0x20000000U)
35195#define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT (29U)
35196/*! VSYNC_OEB
35197 * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
35198 * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
35199 */
35200#define LCDIF_VDCTRL0_CLR_VSYNC_OEB(x) \
35201 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK)
35202#define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xC0000000U)
35203#define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (30U)
35204#define LCDIF_VDCTRL0_CLR_RSRVD2(x) \
35205 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK)
35206/*! @} */
35207
35208/*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
35209/*! @{ */
35210#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
35211#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U)
35212#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) \
35213 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & \
35214 LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)
35215#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U)
35216#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U)
35217#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) \
35218 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK)
35219#define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U)
35220#define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U)
35221#define LCDIF_VDCTRL0_TOG_HALF_LINE(x) \
35222 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK)
35223#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
35224#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
35225#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) \
35226 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & \
35227 LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK)
35228#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U)
35229#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U)
35230#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) \
35231 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & \
35232 LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK)
35233#define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U)
35234#define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U)
35235#define LCDIF_VDCTRL0_TOG_RSRVD1(x) \
35236 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK)
35237#define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U)
35238#define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U)
35239#define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) \
35240 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK)
35241#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U)
35242#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U)
35243#define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) \
35244 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK)
35245#define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U)
35246#define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U)
35247#define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) \
35248 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK)
35249#define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U)
35250#define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U)
35251#define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) \
35252 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK)
35253#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U)
35254#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U)
35255#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) \
35256 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK)
35257#define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK (0x20000000U)
35258#define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT (29U)
35259/*! VSYNC_OEB
35260 * 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
35261 * 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
35262 */
35263#define LCDIF_VDCTRL0_TOG_VSYNC_OEB(x) \
35264 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK)
35265#define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xC0000000U)
35266#define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (30U)
35267#define LCDIF_VDCTRL0_TOG_RSRVD2(x) \
35268 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK)
35269/*! @} */
35270
35271/*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */
35272/*! @{ */
35273#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU)
35274#define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U)
35275#define LCDIF_VDCTRL1_VSYNC_PERIOD(x) \
35276 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
35277/*! @} */
35278
35279/*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */
35280/*! @{ */
35281#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU)
35282#define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U)
35283#define LCDIF_VDCTRL2_HSYNC_PERIOD(x) \
35284 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
35285#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U)
35286#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U)
35287#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) \
35288 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
35289/*! @} */
35290
35291/*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */
35292/*! @{ */
35293#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU)
35294#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U)
35295#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) \
35296 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
35297#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U)
35298#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U)
35299#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) \
35300 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
35301#define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U)
35302#define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U)
35303#define LCDIF_VDCTRL3_VSYNC_ONLY(x) \
35304 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK)
35305#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U)
35306#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U)
35307#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) \
35308 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK)
35309#define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U)
35310#define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U)
35311#define LCDIF_VDCTRL3_RSRVD0(x) \
35312 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
35313/*! @} */
35314
35315/*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */
35316/*! @{ */
35317#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU)
35318#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U)
35319#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) \
35320 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & \
35321 LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
35322#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U)
35323#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U)
35324#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) \
35325 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK)
35326#define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U)
35327#define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U)
35328#define LCDIF_VDCTRL4_RSRVD0(x) \
35329 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK)
35330#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U)
35331#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U)
35332#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) \
35333 (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
35334/*! @} */
35335
35336/*! @name DVICTRL0 - Digital Video Interface Control0 Register */
35337/*! @{ */
35338#define LCDIF_DVICTRL0_H_BLANKING_CNT_MASK (0xFFFU)
35339#define LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT (0U)
35340#define LCDIF_DVICTRL0_H_BLANKING_CNT(x) \
35341 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_BLANKING_CNT_SHIFT)) & LCDIF_DVICTRL0_H_BLANKING_CNT_MASK)
35342#define LCDIF_DVICTRL0_RSRVD0_MASK (0xF000U)
35343#define LCDIF_DVICTRL0_RSRVD0_SHIFT (12U)
35344#define LCDIF_DVICTRL0_RSRVD0(x) \
35345 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD0_SHIFT)) & LCDIF_DVICTRL0_RSRVD0_MASK)
35346#define LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK (0xFFF0000U)
35347#define LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT (16U)
35348#define LCDIF_DVICTRL0_H_ACTIVE_CNT(x) \
35349 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_H_ACTIVE_CNT_SHIFT)) & LCDIF_DVICTRL0_H_ACTIVE_CNT_MASK)
35350#define LCDIF_DVICTRL0_RSRVD1_MASK (0xF0000000U)
35351#define LCDIF_DVICTRL0_RSRVD1_SHIFT (28U)
35352#define LCDIF_DVICTRL0_RSRVD1(x) \
35353 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL0_RSRVD1_SHIFT)) & LCDIF_DVICTRL0_RSRVD1_MASK)
35354/*! @} */
35355
35356/*! @name DVICTRL1 - Digital Video Interface Control1 Register */
35357/*! @{ */
35358#define LCDIF_DVICTRL1_F2_START_LINE_MASK (0x3FFU)
35359#define LCDIF_DVICTRL1_F2_START_LINE_SHIFT (0U)
35360#define LCDIF_DVICTRL1_F2_START_LINE(x) \
35361 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F2_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F2_START_LINE_MASK)
35362#define LCDIF_DVICTRL1_F1_END_LINE_MASK (0xFFC00U)
35363#define LCDIF_DVICTRL1_F1_END_LINE_SHIFT (10U)
35364#define LCDIF_DVICTRL1_F1_END_LINE(x) \
35365 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_END_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_END_LINE_MASK)
35366#define LCDIF_DVICTRL1_F1_START_LINE_MASK (0x3FF00000U)
35367#define LCDIF_DVICTRL1_F1_START_LINE_SHIFT (20U)
35368#define LCDIF_DVICTRL1_F1_START_LINE(x) \
35369 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_F1_START_LINE_SHIFT)) & LCDIF_DVICTRL1_F1_START_LINE_MASK)
35370#define LCDIF_DVICTRL1_RSRVD0_MASK (0xC0000000U)
35371#define LCDIF_DVICTRL1_RSRVD0_SHIFT (30U)
35372#define LCDIF_DVICTRL1_RSRVD0(x) \
35373 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL1_RSRVD0_SHIFT)) & LCDIF_DVICTRL1_RSRVD0_MASK)
35374/*! @} */
35375
35376/*! @name DVICTRL2 - Digital Video Interface Control2 Register */
35377/*! @{ */
35378#define LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK (0x3FFU)
35379#define LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT (0U)
35380#define LCDIF_DVICTRL2_V1_BLANK_END_LINE(x) \
35381 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL2_V1_BLANK_END_LINE_MASK)
35382#define LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK (0xFFC00U)
35383#define LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT (10U)
35384#define LCDIF_DVICTRL2_V1_BLANK_START_LINE(x) \
35385 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_V1_BLANK_START_LINE_SHIFT)) & \
35386 LCDIF_DVICTRL2_V1_BLANK_START_LINE_MASK)
35387#define LCDIF_DVICTRL2_F2_END_LINE_MASK (0x3FF00000U)
35388#define LCDIF_DVICTRL2_F2_END_LINE_SHIFT (20U)
35389#define LCDIF_DVICTRL2_F2_END_LINE(x) \
35390 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_F2_END_LINE_SHIFT)) & LCDIF_DVICTRL2_F2_END_LINE_MASK)
35391#define LCDIF_DVICTRL2_RSRVD0_MASK (0xC0000000U)
35392#define LCDIF_DVICTRL2_RSRVD0_SHIFT (30U)
35393#define LCDIF_DVICTRL2_RSRVD0(x) \
35394 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL2_RSRVD0_SHIFT)) & LCDIF_DVICTRL2_RSRVD0_MASK)
35395/*! @} */
35396
35397/*! @name DVICTRL3 - Digital Video Interface Control3 Register */
35398/*! @{ */
35399#define LCDIF_DVICTRL3_V_LINES_CNT_MASK (0x3FFU)
35400#define LCDIF_DVICTRL3_V_LINES_CNT_SHIFT (0U)
35401#define LCDIF_DVICTRL3_V_LINES_CNT(x) \
35402 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V_LINES_CNT_SHIFT)) & LCDIF_DVICTRL3_V_LINES_CNT_MASK)
35403#define LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK (0xFFC00U)
35404#define LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT (10U)
35405#define LCDIF_DVICTRL3_V2_BLANK_END_LINE(x) \
35406 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_END_LINE_SHIFT)) & LCDIF_DVICTRL3_V2_BLANK_END_LINE_MASK)
35407#define LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK (0x3FF00000U)
35408#define LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT (20U)
35409#define LCDIF_DVICTRL3_V2_BLANK_START_LINE(x) \
35410 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_V2_BLANK_START_LINE_SHIFT)) & \
35411 LCDIF_DVICTRL3_V2_BLANK_START_LINE_MASK)
35412#define LCDIF_DVICTRL3_RSRVD0_MASK (0xC0000000U)
35413#define LCDIF_DVICTRL3_RSRVD0_SHIFT (30U)
35414#define LCDIF_DVICTRL3_RSRVD0(x) \
35415 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL3_RSRVD0_SHIFT)) & LCDIF_DVICTRL3_RSRVD0_MASK)
35416/*! @} */
35417
35418/*! @name DVICTRL4 - Digital Video Interface Control4 Register */
35419/*! @{ */
35420#define LCDIF_DVICTRL4_H_FILL_CNT_MASK (0xFFU)
35421#define LCDIF_DVICTRL4_H_FILL_CNT_SHIFT (0U)
35422#define LCDIF_DVICTRL4_H_FILL_CNT(x) \
35423 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_H_FILL_CNT_SHIFT)) & LCDIF_DVICTRL4_H_FILL_CNT_MASK)
35424#define LCDIF_DVICTRL4_CR_FILL_VALUE_MASK (0xFF00U)
35425#define LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT (8U)
35426#define LCDIF_DVICTRL4_CR_FILL_VALUE(x) \
35427 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CR_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CR_FILL_VALUE_MASK)
35428#define LCDIF_DVICTRL4_CB_FILL_VALUE_MASK (0xFF0000U)
35429#define LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT (16U)
35430#define LCDIF_DVICTRL4_CB_FILL_VALUE(x) \
35431 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_CB_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_CB_FILL_VALUE_MASK)
35432#define LCDIF_DVICTRL4_Y_FILL_VALUE_MASK (0xFF000000U)
35433#define LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT (24U)
35434#define LCDIF_DVICTRL4_Y_FILL_VALUE(x) \
35435 (((uint32_t)(((uint32_t)(x)) << LCDIF_DVICTRL4_Y_FILL_VALUE_SHIFT)) & LCDIF_DVICTRL4_Y_FILL_VALUE_MASK)
35436/*! @} */
35437
35438/*! @name CSC_COEFF0 - RGB to YCbCr 4:2:2 CSC Coefficient0 Register */
35439/*! @{ */
35440#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK (0x3U)
35441#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT (0U)
35442/*! CSC_SUBSAMPLE_FILTER
35443 * 0b00..No filtering, simply keep every chroma value for samples numbered 2n and discard chroma values associated with
35444 * all samples numbered 2n+1. 0b01..Reserved 0b10..Chroma samples numbered 2n and 2n+1 are averaged (weights 1/2, 1/2)
35445 * and that chroma value replaces the two chroma values at 2n and 2n+1. This chroma now exists horizontally halfway
35446 * between the two luma samples. 0b11..Chroma samples numbered 2n-1, 2n, and 2n+1 are averaged (weights 1/4, 1/2, 1/4)
35447 * and that chroma value exists at the same site as the luma sample numbered 2n and the chroma samples at 2n+1 are
35448 * discarded.
35449 */
35450#define LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(x) \
35451 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_SHIFT)) & \
35452 LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER_MASK)
35453#define LCDIF_CSC_COEFF0_RSRVD0_MASK (0xFFFCU)
35454#define LCDIF_CSC_COEFF0_RSRVD0_SHIFT (2U)
35455#define LCDIF_CSC_COEFF0_RSRVD0(x) \
35456 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD0_MASK)
35457#define LCDIF_CSC_COEFF0_C0_MASK (0x3FF0000U)
35458#define LCDIF_CSC_COEFF0_C0_SHIFT (16U)
35459#define LCDIF_CSC_COEFF0_C0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_C0_SHIFT)) & LCDIF_CSC_COEFF0_C0_MASK)
35460#define LCDIF_CSC_COEFF0_RSRVD1_MASK (0xFC000000U)
35461#define LCDIF_CSC_COEFF0_RSRVD1_SHIFT (26U)
35462#define LCDIF_CSC_COEFF0_RSRVD1(x) \
35463 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF0_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF0_RSRVD1_MASK)
35464/*! @} */
35465
35466/*! @name CSC_COEFF1 - RGB to YCbCr 4:2:2 CSC Coefficient1 Register */
35467/*! @{ */
35468#define LCDIF_CSC_COEFF1_C1_MASK (0x3FFU)
35469#define LCDIF_CSC_COEFF1_C1_SHIFT (0U)
35470#define LCDIF_CSC_COEFF1_C1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C1_SHIFT)) & LCDIF_CSC_COEFF1_C1_MASK)
35471#define LCDIF_CSC_COEFF1_RSRVD0_MASK (0xFC00U)
35472#define LCDIF_CSC_COEFF1_RSRVD0_SHIFT (10U)
35473#define LCDIF_CSC_COEFF1_RSRVD0(x) \
35474 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD0_MASK)
35475#define LCDIF_CSC_COEFF1_C2_MASK (0x3FF0000U)
35476#define LCDIF_CSC_COEFF1_C2_SHIFT (16U)
35477#define LCDIF_CSC_COEFF1_C2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_C2_SHIFT)) & LCDIF_CSC_COEFF1_C2_MASK)
35478#define LCDIF_CSC_COEFF1_RSRVD1_MASK (0xFC000000U)
35479#define LCDIF_CSC_COEFF1_RSRVD1_SHIFT (26U)
35480#define LCDIF_CSC_COEFF1_RSRVD1(x) \
35481 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF1_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF1_RSRVD1_MASK)
35482/*! @} */
35483
35484/*! @name CSC_COEFF2 - RGB to YCbCr 4:2:2 CSC Coefficent2 Register */
35485/*! @{ */
35486#define LCDIF_CSC_COEFF2_C3_MASK (0x3FFU)
35487#define LCDIF_CSC_COEFF2_C3_SHIFT (0U)
35488#define LCDIF_CSC_COEFF2_C3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C3_SHIFT)) & LCDIF_CSC_COEFF2_C3_MASK)
35489#define LCDIF_CSC_COEFF2_RSRVD0_MASK (0xFC00U)
35490#define LCDIF_CSC_COEFF2_RSRVD0_SHIFT (10U)
35491#define LCDIF_CSC_COEFF2_RSRVD0(x) \
35492 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD0_MASK)
35493#define LCDIF_CSC_COEFF2_C4_MASK (0x3FF0000U)
35494#define LCDIF_CSC_COEFF2_C4_SHIFT (16U)
35495#define LCDIF_CSC_COEFF2_C4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_C4_SHIFT)) & LCDIF_CSC_COEFF2_C4_MASK)
35496#define LCDIF_CSC_COEFF2_RSRVD1_MASK (0xFC000000U)
35497#define LCDIF_CSC_COEFF2_RSRVD1_SHIFT (26U)
35498#define LCDIF_CSC_COEFF2_RSRVD1(x) \
35499 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF2_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF2_RSRVD1_MASK)
35500/*! @} */
35501
35502/*! @name CSC_COEFF3 - RGB to YCbCr 4:2:2 CSC Coefficient3 Register */
35503/*! @{ */
35504#define LCDIF_CSC_COEFF3_C5_MASK (0x3FFU)
35505#define LCDIF_CSC_COEFF3_C5_SHIFT (0U)
35506#define LCDIF_CSC_COEFF3_C5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C5_SHIFT)) & LCDIF_CSC_COEFF3_C5_MASK)
35507#define LCDIF_CSC_COEFF3_RSRVD0_MASK (0xFC00U)
35508#define LCDIF_CSC_COEFF3_RSRVD0_SHIFT (10U)
35509#define LCDIF_CSC_COEFF3_RSRVD0(x) \
35510 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD0_MASK)
35511#define LCDIF_CSC_COEFF3_C6_MASK (0x3FF0000U)
35512#define LCDIF_CSC_COEFF3_C6_SHIFT (16U)
35513#define LCDIF_CSC_COEFF3_C6(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_C6_SHIFT)) & LCDIF_CSC_COEFF3_C6_MASK)
35514#define LCDIF_CSC_COEFF3_RSRVD1_MASK (0xFC000000U)
35515#define LCDIF_CSC_COEFF3_RSRVD1_SHIFT (26U)
35516#define LCDIF_CSC_COEFF3_RSRVD1(x) \
35517 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF3_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF3_RSRVD1_MASK)
35518/*! @} */
35519
35520/*! @name CSC_COEFF4 - RGB to YCbCr 4:2:2 CSC Coefficient4 Register */
35521/*! @{ */
35522#define LCDIF_CSC_COEFF4_C7_MASK (0x3FFU)
35523#define LCDIF_CSC_COEFF4_C7_SHIFT (0U)
35524#define LCDIF_CSC_COEFF4_C7(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C7_SHIFT)) & LCDIF_CSC_COEFF4_C7_MASK)
35525#define LCDIF_CSC_COEFF4_RSRVD0_MASK (0xFC00U)
35526#define LCDIF_CSC_COEFF4_RSRVD0_SHIFT (10U)
35527#define LCDIF_CSC_COEFF4_RSRVD0(x) \
35528 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD0_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD0_MASK)
35529#define LCDIF_CSC_COEFF4_C8_MASK (0x3FF0000U)
35530#define LCDIF_CSC_COEFF4_C8_SHIFT (16U)
35531#define LCDIF_CSC_COEFF4_C8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_C8_SHIFT)) & LCDIF_CSC_COEFF4_C8_MASK)
35532#define LCDIF_CSC_COEFF4_RSRVD1_MASK (0xFC000000U)
35533#define LCDIF_CSC_COEFF4_RSRVD1_SHIFT (26U)
35534#define LCDIF_CSC_COEFF4_RSRVD1(x) \
35535 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_COEFF4_RSRVD1_SHIFT)) & LCDIF_CSC_COEFF4_RSRVD1_MASK)
35536/*! @} */
35537
35538/*! @name CSC_OFFSET - RGB to YCbCr 4:2:2 CSC Offset Register */
35539/*! @{ */
35540#define LCDIF_CSC_OFFSET_Y_OFFSET_MASK (0x1FFU)
35541#define LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT (0U)
35542#define LCDIF_CSC_OFFSET_Y_OFFSET(x) \
35543 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_Y_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_Y_OFFSET_MASK)
35544#define LCDIF_CSC_OFFSET_RSRVD0_MASK (0xFE00U)
35545#define LCDIF_CSC_OFFSET_RSRVD0_SHIFT (9U)
35546#define LCDIF_CSC_OFFSET_RSRVD0(x) \
35547 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD0_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD0_MASK)
35548#define LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK (0x1FF0000U)
35549#define LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT (16U)
35550#define LCDIF_CSC_OFFSET_CBCR_OFFSET(x) \
35551 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_CBCR_OFFSET_SHIFT)) & LCDIF_CSC_OFFSET_CBCR_OFFSET_MASK)
35552#define LCDIF_CSC_OFFSET_RSRVD1_MASK (0xFE000000U)
35553#define LCDIF_CSC_OFFSET_RSRVD1_SHIFT (25U)
35554#define LCDIF_CSC_OFFSET_RSRVD1(x) \
35555 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_OFFSET_RSRVD1_SHIFT)) & LCDIF_CSC_OFFSET_RSRVD1_MASK)
35556/*! @} */
35557
35558/*! @name CSC_LIMIT - RGB to YCbCr 4:2:2 CSC Limit Register */
35559/*! @{ */
35560#define LCDIF_CSC_LIMIT_Y_MAX_MASK (0xFFU)
35561#define LCDIF_CSC_LIMIT_Y_MAX_SHIFT (0U)
35562#define LCDIF_CSC_LIMIT_Y_MAX(x) \
35563 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MAX_SHIFT)) & LCDIF_CSC_LIMIT_Y_MAX_MASK)
35564#define LCDIF_CSC_LIMIT_Y_MIN_MASK (0xFF00U)
35565#define LCDIF_CSC_LIMIT_Y_MIN_SHIFT (8U)
35566#define LCDIF_CSC_LIMIT_Y_MIN(x) \
35567 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_Y_MIN_SHIFT)) & LCDIF_CSC_LIMIT_Y_MIN_MASK)
35568#define LCDIF_CSC_LIMIT_CBCR_MAX_MASK (0xFF0000U)
35569#define LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT (16U)
35570#define LCDIF_CSC_LIMIT_CBCR_MAX(x) \
35571 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MAX_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MAX_MASK)
35572#define LCDIF_CSC_LIMIT_CBCR_MIN_MASK (0xFF000000U)
35573#define LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT (24U)
35574#define LCDIF_CSC_LIMIT_CBCR_MIN(x) \
35575 (((uint32_t)(((uint32_t)(x)) << LCDIF_CSC_LIMIT_CBCR_MIN_SHIFT)) & LCDIF_CSC_LIMIT_CBCR_MIN_MASK)
35576/*! @} */
35577
35578/*! @name DATA - LCD Interface Data Register */
35579/*! @{ */
35580#define LCDIF_DATA_DATA_ZERO_MASK (0xFFU)
35581#define LCDIF_DATA_DATA_ZERO_SHIFT (0U)
35582#define LCDIF_DATA_DATA_ZERO(x) \
35583 (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ZERO_SHIFT)) & LCDIF_DATA_DATA_ZERO_MASK)
35584#define LCDIF_DATA_DATA_ONE_MASK (0xFF00U)
35585#define LCDIF_DATA_DATA_ONE_SHIFT (8U)
35586#define LCDIF_DATA_DATA_ONE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_ONE_SHIFT)) & LCDIF_DATA_DATA_ONE_MASK)
35587#define LCDIF_DATA_DATA_TWO_MASK (0xFF0000U)
35588#define LCDIF_DATA_DATA_TWO_SHIFT (16U)
35589#define LCDIF_DATA_DATA_TWO(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_TWO_SHIFT)) & LCDIF_DATA_DATA_TWO_MASK)
35590#define LCDIF_DATA_DATA_THREE_MASK (0xFF000000U)
35591#define LCDIF_DATA_DATA_THREE_SHIFT (24U)
35592#define LCDIF_DATA_DATA_THREE(x) \
35593 (((uint32_t)(((uint32_t)(x)) << LCDIF_DATA_DATA_THREE_SHIFT)) & LCDIF_DATA_DATA_THREE_MASK)
35594/*! @} */
35595
35596/*! @name BM_ERROR_STAT - Bus Master Error Status Register */
35597/*! @{ */
35598#define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU)
35599#define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U)
35600#define LCDIF_BM_ERROR_STAT_ADDR(x) \
35601 (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK)
35602/*! @} */
35603
35604/*! @name CRC_STAT - CRC Status Register */
35605/*! @{ */
35606#define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU)
35607#define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U)
35608#define LCDIF_CRC_STAT_CRC_VALUE(x) \
35609 (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK)
35610/*! @} */
35611
35612/*! @name STAT - LCD Interface Status Register */
35613/*! @{ */
35614#define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU)
35615#define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U)
35616#define LCDIF_STAT_LFIFO_COUNT(x) \
35617 (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK)
35618#define LCDIF_STAT_RSRVD0_MASK (0xFFFE00U)
35619#define LCDIF_STAT_RSRVD0_SHIFT (9U)
35620#define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK)
35621#define LCDIF_STAT_DVI_CURRENT_FIELD_MASK (0x1000000U)
35622#define LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT (24U)
35623#define LCDIF_STAT_DVI_CURRENT_FIELD(x) \
35624 (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DVI_CURRENT_FIELD_SHIFT)) & LCDIF_STAT_DVI_CURRENT_FIELD_MASK)
35625#define LCDIF_STAT_BUSY_MASK (0x2000000U)
35626#define LCDIF_STAT_BUSY_SHIFT (25U)
35627#define LCDIF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_BUSY_SHIFT)) & LCDIF_STAT_BUSY_MASK)
35628#define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U)
35629#define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U)
35630#define LCDIF_STAT_TXFIFO_EMPTY(x) \
35631 (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK)
35632#define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U)
35633#define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U)
35634#define LCDIF_STAT_TXFIFO_FULL(x) \
35635 (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK)
35636#define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U)
35637#define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U)
35638#define LCDIF_STAT_LFIFO_EMPTY(x) \
35639 (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK)
35640#define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U)
35641#define LCDIF_STAT_LFIFO_FULL_SHIFT (29U)
35642#define LCDIF_STAT_LFIFO_FULL(x) \
35643 (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK)
35644#define LCDIF_STAT_PRESENT_MASK (0x80000000U)
35645#define LCDIF_STAT_PRESENT_SHIFT (31U)
35646#define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK)
35647/*! @} */
35648
35649/*! @name THRES - LCDIF Threshold Register */
35650/*! @{ */
35651#define LCDIF_THRES_PANIC_MASK (0x1FFU)
35652#define LCDIF_THRES_PANIC_SHIFT (0U)
35653#define LCDIF_THRES_PANIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_PANIC_SHIFT)) & LCDIF_THRES_PANIC_MASK)
35654#define LCDIF_THRES_RSRVD1_MASK (0xFE00U)
35655#define LCDIF_THRES_RSRVD1_SHIFT (9U)
35656#define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK)
35657#define LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U)
35658#define LCDIF_THRES_FASTCLOCK_SHIFT (16U)
35659#define LCDIF_THRES_FASTCLOCK(x) \
35660 (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK)
35661#define LCDIF_THRES_RSRVD2_MASK (0xFE000000U)
35662#define LCDIF_THRES_RSRVD2_SHIFT (25U)
35663#define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK)
35664/*! @} */
35665
35666/*! @name AS_CTRL - LCDIF AS Buffer Control Register */
35667/*! @{ */
35668#define LCDIF_AS_CTRL_AS_ENABLE_MASK (0x1U)
35669#define LCDIF_AS_CTRL_AS_ENABLE_SHIFT (0U)
35670#define LCDIF_AS_CTRL_AS_ENABLE(x) \
35671 (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_AS_ENABLE_SHIFT)) & LCDIF_AS_CTRL_AS_ENABLE_MASK)
35672#define LCDIF_AS_CTRL_ALPHA_CTRL_MASK (0x6U)
35673#define LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT (1U)
35674#define LCDIF_AS_CTRL_ALPHA_CTRL(x) \
35675 (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_CTRL_SHIFT)) & LCDIF_AS_CTRL_ALPHA_CTRL_MASK)
35676#define LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U)
35677#define LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U)
35678#define LCDIF_AS_CTRL_ENABLE_COLORKEY(x) \
35679 (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & LCDIF_AS_CTRL_ENABLE_COLORKEY_MASK)
35680#define LCDIF_AS_CTRL_FORMAT_MASK (0xF0U)
35681#define LCDIF_AS_CTRL_FORMAT_SHIFT (4U)
35682#define LCDIF_AS_CTRL_FORMAT(x) \
35683 (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_FORMAT_SHIFT)) & LCDIF_AS_CTRL_FORMAT_MASK)
35684#define LCDIF_AS_CTRL_ALPHA_MASK (0xFF00U)
35685#define LCDIF_AS_CTRL_ALPHA_SHIFT (8U)
35686#define LCDIF_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_SHIFT)) & LCDIF_AS_CTRL_ALPHA_MASK)
35687#define LCDIF_AS_CTRL_ROP_MASK (0xF0000U)
35688#define LCDIF_AS_CTRL_ROP_SHIFT (16U)
35689#define LCDIF_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ROP_SHIFT)) & LCDIF_AS_CTRL_ROP_MASK)
35690#define LCDIF_AS_CTRL_ALPHA_INVERT_MASK (0x100000U)
35691#define LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT (20U)
35692#define LCDIF_AS_CTRL_ALPHA_INVERT(x) \
35693 (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_ALPHA_INVERT_SHIFT)) & LCDIF_AS_CTRL_ALPHA_INVERT_MASK)
35694#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK (0x600000U)
35695#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT (21U)
35696#define LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE(x) \
35697 (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_AS_CTRL_INPUT_DATA_SWIZZLE_MASK)
35698#define LCDIF_AS_CTRL_PS_DISABLE_MASK (0x800000U)
35699#define LCDIF_AS_CTRL_PS_DISABLE_SHIFT (23U)
35700#define LCDIF_AS_CTRL_PS_DISABLE(x) \
35701 (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_PS_DISABLE_SHIFT)) & LCDIF_AS_CTRL_PS_DISABLE_MASK)
35702#define LCDIF_AS_CTRL_RVDS1_MASK (0x7000000U)
35703#define LCDIF_AS_CTRL_RVDS1_SHIFT (24U)
35704#define LCDIF_AS_CTRL_RVDS1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_RVDS1_SHIFT)) & LCDIF_AS_CTRL_RVDS1_MASK)
35705#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK (0x8000000U)
35706#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT (27U)
35707#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ(x) \
35708 (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_MASK)
35709#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK (0x10000000U)
35710#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT (28U)
35711#define LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN(x) \
35712 (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_SHIFT)) & LCDIF_AS_CTRL_CSI_SYNC_ON_IRQ_EN_MASK)
35713#define LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK (0x20000000U)
35714#define LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT (29U)
35715#define LCDIF_AS_CTRL_CSI_VSYNC_MODE(x) \
35716 (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_MODE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_MODE_MASK)
35717#define LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK (0x40000000U)
35718#define LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT (30U)
35719#define LCDIF_AS_CTRL_CSI_VSYNC_POL(x) \
35720 (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_POL_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_POL_MASK)
35721#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK (0x80000000U)
35722#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT (31U)
35723#define LCDIF_AS_CTRL_CSI_VSYNC_ENABLE(x) \
35724 (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_SHIFT)) & LCDIF_AS_CTRL_CSI_VSYNC_ENABLE_MASK)
35725/*! @} */
35726
35727/*! @name AS_BUF - Alpha Surface Buffer Pointer */
35728/*! @{ */
35729#define LCDIF_AS_BUF_ADDR_MASK (0xFFFFFFFFU)
35730#define LCDIF_AS_BUF_ADDR_SHIFT (0U)
35731#define LCDIF_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_BUF_ADDR_SHIFT)) & LCDIF_AS_BUF_ADDR_MASK)
35732/*! @} */
35733
35734/*! @name AS_NEXT_BUF - */
35735/*! @{ */
35736#define LCDIF_AS_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU)
35737#define LCDIF_AS_NEXT_BUF_ADDR_SHIFT (0U)
35738#define LCDIF_AS_NEXT_BUF_ADDR(x) \
35739 (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_NEXT_BUF_ADDR_SHIFT)) & LCDIF_AS_NEXT_BUF_ADDR_MASK)
35740/*! @} */
35741
35742/*! @name AS_CLRKEYLOW - LCDIF Overlay Color Key Low */
35743/*! @{ */
35744#define LCDIF_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)
35745#define LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT (0U)
35746#define LCDIF_AS_CLRKEYLOW_PIXEL(x) \
35747 (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYLOW_PIXEL_MASK)
35748#define LCDIF_AS_CLRKEYLOW_RSVD1_MASK (0xFF000000U)
35749#define LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT (24U)
35750#define LCDIF_AS_CLRKEYLOW_RSVD1(x) \
35751 (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYLOW_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYLOW_RSVD1_MASK)
35752/*! @} */
35753
35754/*! @name AS_CLRKEYHIGH - LCDIF Overlay Color Key High */
35755/*! @{ */
35756#define LCDIF_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)
35757#define LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT (0U)
35758#define LCDIF_AS_CLRKEYHIGH_PIXEL(x) \
35759 (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_PIXEL_SHIFT)) & LCDIF_AS_CLRKEYHIGH_PIXEL_MASK)
35760#define LCDIF_AS_CLRKEYHIGH_RSVD1_MASK (0xFF000000U)
35761#define LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT (24U)
35762#define LCDIF_AS_CLRKEYHIGH_RSVD1(x) \
35763 (((uint32_t)(((uint32_t)(x)) << LCDIF_AS_CLRKEYHIGH_RSVD1_SHIFT)) & LCDIF_AS_CLRKEYHIGH_RSVD1_MASK)
35764/*! @} */
35765
35766/*! @name SYNC_DELAY - LCD working insync mode with CSI for VSYNC delay */
35767/*! @{ */
35768#define LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK (0xFFFFU)
35769#define LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT (0U)
35770#define LCDIF_SYNC_DELAY_H_COUNT_DELAY(x) \
35771 (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_H_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_H_COUNT_DELAY_MASK)
35772#define LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK (0xFFFF0000U)
35773#define LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT (16U)
35774#define LCDIF_SYNC_DELAY_V_COUNT_DELAY(x) \
35775 (((uint32_t)(((uint32_t)(x)) << LCDIF_SYNC_DELAY_V_COUNT_DELAY_SHIFT)) & LCDIF_SYNC_DELAY_V_COUNT_DELAY_MASK)
35776/*! @} */
35777
35778/*! @name PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register */
35779/*! @{ */
35780#define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU)
35781#define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U)
35782#define LCDIF_PIGEONCTRL0_FD_PERIOD(x) \
35783 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK)
35784#define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U)
35785#define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U)
35786#define LCDIF_PIGEONCTRL0_LD_PERIOD(x) \
35787 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK)
35788/*! @} */
35789
35790/*! @name PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register */
35791/*! @{ */
35792#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU)
35793#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U)
35794#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) \
35795 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK)
35796#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U)
35797#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U)
35798#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) \
35799 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK)
35800/*! @} */
35801
35802/*! @name PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register */
35803/*! @{ */
35804#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU)
35805#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U)
35806#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) \
35807 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK)
35808#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U)
35809#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U)
35810#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) \
35811 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK)
35812/*! @} */
35813
35814/*! @name PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register */
35815/*! @{ */
35816#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU)
35817#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U)
35818#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) \
35819 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK)
35820#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U)
35821#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U)
35822#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) \
35823 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK)
35824/*! @} */
35825
35826/*! @name PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register */
35827/*! @{ */
35828#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU)
35829#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U)
35830#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) \
35831 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & \
35832 LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK)
35833#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
35834#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U)
35835#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) \
35836 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & \
35837 LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK)
35838/*! @} */
35839
35840/*! @name PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register */
35841/*! @{ */
35842#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU)
35843#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U)
35844#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) \
35845 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & \
35846 LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK)
35847#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
35848#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U)
35849#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) \
35850 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & \
35851 LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK)
35852/*! @} */
35853
35854/*! @name PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register */
35855/*! @{ */
35856#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU)
35857#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U)
35858#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) \
35859 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & \
35860 LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK)
35861#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
35862#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U)
35863#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) \
35864 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & \
35865 LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK)
35866/*! @} */
35867
35868/*! @name PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register */
35869/*! @{ */
35870#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU)
35871#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U)
35872#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) \
35873 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & \
35874 LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK)
35875#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
35876#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U)
35877#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) \
35878 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & \
35879 LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK)
35880/*! @} */
35881
35882/*! @name PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register */
35883/*! @{ */
35884#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U)
35885#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U)
35886#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) \
35887 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK)
35888#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U)
35889#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U)
35890#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) \
35891 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK)
35892/*! @} */
35893
35894/*! @name PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register */
35895/*! @{ */
35896#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U)
35897#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U)
35898#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) \
35899 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & \
35900 LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK)
35901#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U)
35902#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U)
35903#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) \
35904 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & \
35905 LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK)
35906/*! @} */
35907
35908/*! @name PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register */
35909/*! @{ */
35910#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U)
35911#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U)
35912#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) \
35913 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & \
35914 LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK)
35915#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U)
35916#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U)
35917#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) \
35918 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & \
35919 LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK)
35920/*! @} */
35921
35922/*! @name PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register */
35923/*! @{ */
35924#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U)
35925#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U)
35926#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) \
35927 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & \
35928 LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK)
35929#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U)
35930#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U)
35931#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) \
35932 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & \
35933 LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK)
35934/*! @} */
35935
35936/*! @name PIGEON_n_0 - Panel Interface Signal Generator Register */
35937/*! @{ */
35938#define LCDIF_PIGEON_n_0_EN_MASK (0x1U)
35939#define LCDIF_PIGEON_n_0_EN_SHIFT (0U)
35940#define LCDIF_PIGEON_n_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_0_EN_SHIFT)) & LCDIF_PIGEON_n_0_EN_MASK)
35941#define LCDIF_PIGEON_n_0_POL_MASK (0x2U)
35942#define LCDIF_PIGEON_n_0_POL_SHIFT (1U)
35943/*! POL
35944 * 0b0..Normal Signal (Active high)
35945 * 0b1..Inverted signal (Active low)
35946 */
35947#define LCDIF_PIGEON_n_0_POL(x) \
35948 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_0_POL_SHIFT)) & LCDIF_PIGEON_n_0_POL_MASK)
35949#define LCDIF_PIGEON_n_0_INC_SEL_MASK (0xCU)
35950#define LCDIF_PIGEON_n_0_INC_SEL_SHIFT (2U)
35951/*! INC_SEL
35952 * 0b00..pclk
35953 * 0b01..Line start pulse
35954 * 0b10..Frame start pulse
35955 * 0b11..Use another signal as tick event
35956 */
35957#define LCDIF_PIGEON_n_0_INC_SEL(x) \
35958 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_n_0_INC_SEL_MASK)
35959#define LCDIF_PIGEON_n_0_OFFSET_MASK (0xF0U)
35960#define LCDIF_PIGEON_n_0_OFFSET_SHIFT (4U)
35961#define LCDIF_PIGEON_n_0_OFFSET(x) \
35962 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_0_OFFSET_SHIFT)) & LCDIF_PIGEON_n_0_OFFSET_MASK)
35963#define LCDIF_PIGEON_n_0_MASK_CNT_SEL_MASK (0xF00U)
35964#define LCDIF_PIGEON_n_0_MASK_CNT_SEL_SHIFT (8U)
35965/*! MASK_CNT_SEL
35966 * 0b0000..pclk counter within one hscan state
35967 * 0b0001..pclk cycle within one hscan state
35968 * 0b0010..line counter within one vscan state
35969 * 0b0011..line cycle within one vscan state
35970 * 0b0100..frame counter
35971 * 0b0101..frame cycle
35972 * 0b0110..horizontal counter (pclk counter within one line )
35973 * 0b0111..vertical counter (line counter within one frame)
35974 */
35975#define LCDIF_PIGEON_n_0_MASK_CNT_SEL(x) \
35976 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_n_0_MASK_CNT_SEL_MASK)
35977#define LCDIF_PIGEON_n_0_MASK_CNT_MASK (0xFFF000U)
35978#define LCDIF_PIGEON_n_0_MASK_CNT_SHIFT (12U)
35979#define LCDIF_PIGEON_n_0_MASK_CNT(x) \
35980 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_n_0_MASK_CNT_MASK)
35981#define LCDIF_PIGEON_n_0_STATE_MASK_MASK (0xFF000000U)
35982#define LCDIF_PIGEON_n_0_STATE_MASK_SHIFT (24U)
35983/*! STATE_MASK
35984 * 0b00000001..FRAME SYNC
35985 * 0b00000010..FRAME BEGIN
35986 * 0b00000100..FRAME DATA
35987 * 0b00001000..FRAME END
35988 * 0b00010000..LINE SYNC
35989 * 0b00100000..LINE BEGIN
35990 * 0b01000000..LINE DATA
35991 * 0b10000000..LINE END
35992 */
35993#define LCDIF_PIGEON_n_0_STATE_MASK(x) \
35994 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_n_0_STATE_MASK_MASK)
35995/*! @} */
35996
35997/* The count of LCDIF_PIGEON_n_0 */
35998#define LCDIF_PIGEON_n_0_COUNT (12U)
35999
36000/*! @name PIGEON_n_1 - Panel Interface Signal Generator Register */
36001/*! @{ */
36002#define LCDIF_PIGEON_n_1_SET_CNT_MASK (0xFFFFU)
36003#define LCDIF_PIGEON_n_1_SET_CNT_SHIFT (0U)
36004/*! SET_CNT
36005 * 0b0000000000000000..Start as active
36006 */
36007#define LCDIF_PIGEON_n_1_SET_CNT(x) \
36008 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_n_1_SET_CNT_MASK)
36009#define LCDIF_PIGEON_n_1_CLR_CNT_MASK (0xFFFF0000U)
36010#define LCDIF_PIGEON_n_1_CLR_CNT_SHIFT (16U)
36011/*! CLR_CNT
36012 * 0b0000000000000000..Keep active until mask off
36013 */
36014#define LCDIF_PIGEON_n_1_CLR_CNT(x) \
36015 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_n_1_CLR_CNT_MASK)
36016/*! @} */
36017
36018/* The count of LCDIF_PIGEON_n_1 */
36019#define LCDIF_PIGEON_n_1_COUNT (12U)
36020
36021/*! @name PIGEON_n_2 - Panel Interface Signal Generator Register */
36022/*! @{ */
36023#define LCDIF_PIGEON_n_2_SIG_LOGIC_MASK (0xFU)
36024#define LCDIF_PIGEON_n_2_SIG_LOGIC_SHIFT (0U)
36025/*! SIG_LOGIC
36026 * 0b0000..No logic operation
36027 * 0b0001..sigout = sig_another AND this_sig
36028 * 0b0010..sigout = sig_another OR this_sig
36029 * 0b0011..mask = sig_another AND other_masks
36030 */
36031#define LCDIF_PIGEON_n_2_SIG_LOGIC(x) \
36032 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_n_2_SIG_LOGIC_MASK)
36033#define LCDIF_PIGEON_n_2_SIG_ANOTHER_MASK (0x1F0U)
36034#define LCDIF_PIGEON_n_2_SIG_ANOTHER_SHIFT (4U)
36035/*! SIG_ANOTHER
36036 * 0b00000..Keep active until mask off
36037 */
36038#define LCDIF_PIGEON_n_2_SIG_ANOTHER(x) \
36039 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_n_2_SIG_ANOTHER_MASK)
36040#define LCDIF_PIGEON_n_2_RSVD_MASK (0xFFFFFE00U)
36041#define LCDIF_PIGEON_n_2_RSVD_SHIFT (9U)
36042#define LCDIF_PIGEON_n_2_RSVD(x) \
36043 (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_n_2_RSVD_SHIFT)) & LCDIF_PIGEON_n_2_RSVD_MASK)
36044/*! @} */
36045
36046/* The count of LCDIF_PIGEON_n_2 */
36047#define LCDIF_PIGEON_n_2_COUNT (12U)
36048
36049/*!
36050 * @}
36051 */ /* end of group LCDIF_Register_Masks */
36052
36053/* LCDIF - Peripheral instance base addresses */
36054/** Peripheral LCDIF base address */
36055#define LCDIF_BASE (0x32E00000u)
36056/** Peripheral LCDIF base pointer */
36057#define LCDIF ((LCDIF_Type *)LCDIF_BASE)
36058/** Array initializer of LCDIF peripheral base addresses */
36059#define LCDIF_BASE_ADDRS \
36060 { \
36061 LCDIF_BASE \
36062 }
36063/** Array initializer of LCDIF peripheral base pointers */
36064#define LCDIF_BASE_PTRS \
36065 { \
36066 LCDIF \
36067 }
36068
36069/*!
36070 * @}
36071 */ /* end of group LCDIF_Peripheral_Access_Layer */
36072
36073/* ----------------------------------------------------------------------------
36074 -- MIPI_CSI Peripheral Access Layer
36075 ---------------------------------------------------------------------------- */
36076
36077/*!
36078 * @addtogroup MIPI_CSI_Peripheral_Access_Layer MIPI_CSI Peripheral Access Layer
36079 * @{
36080 */
36081
36082/** MIPI_CSI - Register Layout Typedef */
36083typedef struct
36084{
36085 uint8_t RESERVED_0[4];
36086 __IO uint32_t CSIS_COMMON_CTRL; /**< CSIS Common Control Register, offset: 0x4 */
36087 __IO uint32_t CSIS_CLOCK_CTRL; /**< CSIS Clock Control Register, offset: 0x8 */
36088 uint8_t RESERVED_1[4];
36089 __IO uint32_t INTERRUPT_MASK_0; /**< Interrupt mask register 0, offset: 0x10 */
36090 __IO uint32_t INTERRUPT_SOURCE_0; /**< Interrupt source register 0, offset: 0x14 */
36091 __IO uint32_t INTERRUPT_MASK_1; /**< Interrupt mask register 1, offset: 0x18 */
36092 __IO uint32_t INTERRUPT_SOURCE_1; /**< Interrupt source register 1, offset: 0x1C */
36093 __IO uint32_t DPHY_STATUS; /**< D-PHY status register, offset: 0x20 */
36094 __IO uint32_t DPHY_COMMON_CTRL; /**< D-PHY common control register, offset: 0x24 */
36095 uint8_t RESERVED_2[8];
36096 __IO uint32_t DPHY_MASTER_SLAVE_CTRL_LOW; /**< D-PHY Master and Slave Control register Low, offset: 0x30 */
36097 __IO uint32_t DPHY_MASTER_SLAVE_CTRL_HIGH; /**< D-PHY Master and Slave Control register HIGH, offset: 0x34 */
36098 __IO uint32_t DPHY_SLAVE_CTRL_LOW; /**< D-PHY Slave Control register Low, offset: 0x38 */
36099 __IO uint32_t DPHY_SLAVE_CTRL_HIGH; /**< D-PHY Slave Control register HIGH, offset: 0x3C */
36100 struct
36101 { /* offset: 0x40, array step: 0x10 */
36102 __IO uint32_t ISP_CONFIG; /**< ISP Configuration Register, array offset: 0x40, array step: 0x10 */
36103 __IO uint32_t ISP_RESOLUTION; /**< ISP Resolution Register, array offset: 0x44, array step: 0x10 */
36104 __IO uint32_t ISP_SYNC; /**< ISP SYNC Register, array offset: 0x48, array step: 0x10 */
36105 uint8_t RESERVED_0[4];
36106 } ISP_CONFIGn[4];
36107 struct
36108 { /* offset: 0x80, array step: 0x10 */
36109 __I uint32_t SHADOW_CONFIG; /**< Shadow Configuration Register, array offset: 0x80, array step: 0x10 */
36110 __I uint32_t SHADOW_RESOLUTION; /**< Shadow Resolution Register, array offset: 0x84, array step: 0x10 */
36111 __I uint32_t SHADOW_SYNC; /**< Shadow SYNC Register, array offset: 0x88, array step: 0x10 */
36112 uint8_t RESERVED_0[4];
36113 } SHADOW_CONFIGn[4];
36114 uint8_t RESERVED_3[64];
36115 __IO uint32_t FRAME_COUNTER[4]; /**< Frame Counter, array offset: 0x100, array step: 0x4 */
36116 __IO uint32_t LINE_INTERRUPT_RATIO[4]; /**< Line Interrupt Ratio, array offset: 0x110, array step: 0x4 */
36117} MIPI_CSI_Type;
36118
36119/* ----------------------------------------------------------------------------
36120 -- MIPI_CSI Register Masks
36121 ---------------------------------------------------------------------------- */
36122
36123/*!
36124 * @addtogroup MIPI_CSI_Register_Masks MIPI_CSI Register Masks
36125 * @{
36126 */
36127
36128/*! @name CSIS_COMMON_CTRL - CSIS Common Control Register */
36129/*! @{ */
36130#define MIPI_CSI_CSIS_COMMON_CTRL_CSI_EN_MASK (0x1U)
36131#define MIPI_CSI_CSIS_COMMON_CTRL_CSI_EN_SHIFT (0U)
36132/*! CSI_EN
36133 * 0b0..Disable
36134 * 0b1..Enable
36135 */
36136#define MIPI_CSI_CSIS_COMMON_CTRL_CSI_EN(x) \
36137 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_COMMON_CTRL_CSI_EN_SHIFT)) & MIPI_CSI_CSIS_COMMON_CTRL_CSI_EN_MASK)
36138#define MIPI_CSI_CSIS_COMMON_CTRL_SW_RESET_MASK (0x2U)
36139#define MIPI_CSI_CSIS_COMMON_CTRL_SW_RESET_SHIFT (1U)
36140/*! SW_RESET - Software reset
36141 * 0b0..Ready
36142 * 0b1..Reset
36143 */
36144#define MIPI_CSI_CSIS_COMMON_CTRL_SW_RESET(x) \
36145 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_COMMON_CTRL_SW_RESET_SHIFT)) & \
36146 MIPI_CSI_CSIS_COMMON_CTRL_SW_RESET_MASK)
36147#define MIPI_CSI_CSIS_COMMON_CTRL_LANE_NUMBER_MASK (0x300U)
36148#define MIPI_CSI_CSIS_COMMON_CTRL_LANE_NUMBER_SHIFT (8U)
36149/*! LANE_NUMBER
36150 * 0b00..1 data lane
36151 * 0b01..2 data lane
36152 * 0b10..3 data lane
36153 * 0b11..4 data lane
36154 */
36155#define MIPI_CSI_CSIS_COMMON_CTRL_LANE_NUMBER(x) \
36156 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_COMMON_CTRL_LANE_NUMBER_SHIFT)) & \
36157 MIPI_CSI_CSIS_COMMON_CTRL_LANE_NUMBER_MASK)
36158#define MIPI_CSI_CSIS_COMMON_CTRL_UPDATE_SHADOW_MASK (0xF0000U)
36159#define MIPI_CSI_CSIS_COMMON_CTRL_UPDATE_SHADOW_SHIFT (16U)
36160#define MIPI_CSI_CSIS_COMMON_CTRL_UPDATE_SHADOW(x) \
36161 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_COMMON_CTRL_UPDATE_SHADOW_SHIFT)) & \
36162 MIPI_CSI_CSIS_COMMON_CTRL_UPDATE_SHADOW_MASK)
36163/*! @} */
36164
36165/*! @name CSIS_CLOCK_CTRL - CSIS Clock Control Register */
36166/*! @{ */
36167#define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_EN_MASK (0xF0U)
36168#define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_EN_SHIFT (4U)
36169/*! CLKGATE_EN
36170 * 0b0000..Pixel clock is always alive
36171 * 0b0001..Pixel clock is alive during the interval of frame [7] CH3 [6] CH2 [5] CH1 [4] CH0 (Refer 2.9)
36172 */
36173#define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_EN(x) \
36174 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_EN_SHIFT)) & \
36175 MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_EN_MASK)
36176#define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_TRAIL_MASK (0xFFFF0000U)
36177#define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_TRAIL_SHIFT (16U)
36178#define MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_TRAIL(x) \
36179 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_TRAIL_SHIFT)) & \
36180 MIPI_CSI_CSIS_CLOCK_CTRL_CLKGATE_TRAIL_MASK)
36181/*! @} */
36182
36183/*! @name INTERRUPT_MASK_0 - Interrupt mask register 0 */
36184/*! @{ */
36185#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ID_MASK (0x1U)
36186#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ID_SHIFT (0U)
36187/*! MSK_ERR_ID - Unknown ID error
36188 * 0b0..Disable (masked)
36189 * 0b1..Enable (unmasked)
36190 */
36191#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ID(x) \
36192 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ID_SHIFT)) & \
36193 MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ID_MASK)
36194#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_CRC_MASK (0x2U)
36195#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_CRC_SHIFT (1U)
36196/*! MSK_ERR_CRC - CRC error
36197 * 0b0..Disable (masked)
36198 * 0b1..Enable (unmasked)
36199 */
36200#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_CRC(x) \
36201 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_CRC_SHIFT)) & \
36202 MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_CRC_MASK)
36203#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ECC_MASK (0x4U)
36204#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ECC_SHIFT (2U)
36205/*! MSK_ERR_ECC - ECC error
36206 * 0b0..Disable (masked)
36207 * 0b1..Enable (unmasked)
36208 */
36209#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ECC(x) \
36210 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ECC_SHIFT)) & \
36211 MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_ECC_MASK)
36212#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_WRONG_CFG_MASK (0x8U)
36213#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_WRONG_CFG_SHIFT (3U)
36214/*! MSK_ERR_WRONG_CFG - Wrong configuration
36215 * 0b0..Disable (masked)
36216 * 0b1..Enable (unmasked)
36217 */
36218#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_WRONG_CFG(x) \
36219 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_WRONG_CFG_SHIFT)) & \
36220 MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_WRONG_CFG_MASK)
36221#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_OVER_MASK (0x10U)
36222#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_OVER_SHIFT (4U)
36223/*! MSK_ERR_OVER - Image FIFO overflow interrupt
36224 * 0b0..Disable (masked)
36225 * 0b1..Enable (unmasked)
36226 */
36227#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_OVER(x) \
36228 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_OVER_SHIFT)) & \
36229 MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_OVER_MASK)
36230#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FE_MASK (0xF00U)
36231#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FE_SHIFT (8U)
36232/*! MSK_ERR_LOST_FE - Lost of Frame End packet, [CH3,CH2,CH1,CH0]
36233 * 0b0000..Disable (masked)
36234 * 0b0001..Enable (unmasked)
36235 */
36236#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FE(x) \
36237 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FE_SHIFT)) & \
36238 MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FE_MASK)
36239#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FS_MASK (0xF000U)
36240#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FS_SHIFT (12U)
36241/*! MSK_ERR_LOST_FS - Lost of Frame Start packet, [CH3,CH2,CH1,CH0]
36242 * 0b0000..Disable (masked)
36243 * 0b0001..Enable (unmasked)
36244 */
36245#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FS(x) \
36246 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FS_SHIFT)) & \
36247 MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_LOST_FS_MASK)
36248#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_SOT_HS_MASK (0xF0000U)
36249#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_SOT_HS_SHIFT (16U)
36250/*! MSK_ERR_SOT_HS - Start of transmission error [Lane3, Lane2, Lane1, Lane0]
36251 * 0b0000..Disable (masked)
36252 * 0b0001..Enable (unmasked)
36253 */
36254#define MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_SOT_HS(x) \
36255 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_SOT_HS_SHIFT)) & \
36256 MIPI_CSI_INTERRUPT_MASK_0_MSK_ERR_SOT_HS_MASK)
36257#define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMEEND_MASK (0xF00000U)
36258#define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMEEND_SHIFT (20U)
36259/*! MSK_FRAMEEND - FE packet is received, [CH3,CH2,CH1,CH0]
36260 * 0b0000..Disable (masked)
36261 * 0b0001..Enable (unmasked)
36262 */
36263#define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMEEND(x) \
36264 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMEEND_SHIFT)) & \
36265 MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMEEND_MASK)
36266#define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMESTART_MASK (0xF000000U)
36267#define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMESTART_SHIFT (24U)
36268/*! MSK_FRAMESTART - FS packet is received, [CH3,CH2,CH1,CH0]
36269 * 0b0000..Disable (masked)
36270 * 0b0001..Enable (unmasked)
36271 */
36272#define MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMESTART(x) \
36273 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMESTART_SHIFT)) & \
36274 MIPI_CSI_INTERRUPT_MASK_0_MSK_FRAMESTART_MASK)
36275/*! @} */
36276
36277/*! @name INTERRUPT_SOURCE_0 - Interrupt source register 0 */
36278/*! @{ */
36279#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ID_MASK (0x1U)
36280#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ID_SHIFT (0U)
36281#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ID(x) \
36282 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ID_SHIFT)) & \
36283 MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ID_MASK)
36284#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_CRC_MASK (0x2U)
36285#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_CRC_SHIFT (1U)
36286#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_CRC(x) \
36287 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_CRC_SHIFT)) & \
36288 MIPI_CSI_INTERRUPT_SOURCE_0_ERR_CRC_MASK)
36289#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ECC_MASK (0x4U)
36290#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ECC_SHIFT (2U)
36291#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ECC(x) \
36292 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ECC_SHIFT)) & \
36293 MIPI_CSI_INTERRUPT_SOURCE_0_ERR_ECC_MASK)
36294#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_WRONG_CFG_MASK (0x8U)
36295#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_WRONG_CFG_SHIFT (3U)
36296#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_WRONG_CFG(x) \
36297 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_WRONG_CFG_SHIFT)) & \
36298 MIPI_CSI_INTERRUPT_SOURCE_0_ERR_WRONG_CFG_MASK)
36299#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_OVER_MASK (0x10U)
36300#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_OVER_SHIFT (4U)
36301#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_OVER(x) \
36302 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_OVER_SHIFT)) & \
36303 MIPI_CSI_INTERRUPT_SOURCE_0_ERR_OVER_MASK)
36304#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FE_MASK (0xF00U)
36305#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FE_SHIFT (8U)
36306#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FE(x) \
36307 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FE_SHIFT)) & \
36308 MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FE_MASK)
36309#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FS_MASK (0xF000U)
36310#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FS_SHIFT (12U)
36311#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FS(x) \
36312 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FS_SHIFT)) & \
36313 MIPI_CSI_INTERRUPT_SOURCE_0_ERR_LOST_FS_MASK)
36314#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_SOT_HS_MASK (0xF0000U)
36315#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_SOT_HS_SHIFT (16U)
36316#define MIPI_CSI_INTERRUPT_SOURCE_0_ERR_SOT_HS(x) \
36317 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_ERR_SOT_HS_SHIFT)) & \
36318 MIPI_CSI_INTERRUPT_SOURCE_0_ERR_SOT_HS_MASK)
36319#define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_END_MASK (0xF00000U)
36320#define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_END_SHIFT (20U)
36321#define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_END(x) \
36322 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_END_SHIFT)) & \
36323 MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_END_MASK)
36324#define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_START_MASK (0xF000000U)
36325#define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_START_SHIFT (24U)
36326#define MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_START(x) \
36327 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_START_SHIFT)) & \
36328 MIPI_CSI_INTERRUPT_SOURCE_0_FRAME_START_MASK)
36329/*! @} */
36330
36331/*! @name INTERRUPT_MASK_1 - Interrupt mask register 1 */
36332/*! @{ */
36333#define MIPI_CSI_INTERRUPT_MASK_1_MSK_LINE_END_MASK (0xFU)
36334#define MIPI_CSI_INTERRUPT_MASK_1_MSK_LINE_END_SHIFT (0U)
36335#define MIPI_CSI_INTERRUPT_MASK_1_MSK_LINE_END(x) \
36336 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_MASK_1_MSK_LINE_END_SHIFT)) & \
36337 MIPI_CSI_INTERRUPT_MASK_1_MSK_LINE_END_MASK)
36338/*! @} */
36339
36340/*! @name INTERRUPT_SOURCE_1 - Interrupt source register 1 */
36341/*! @{ */
36342#define MIPI_CSI_INTERRUPT_SOURCE_1_LINE_END_MASK (0xFU)
36343#define MIPI_CSI_INTERRUPT_SOURCE_1_LINE_END_SHIFT (0U)
36344#define MIPI_CSI_INTERRUPT_SOURCE_1_LINE_END(x) \
36345 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_INTERRUPT_SOURCE_1_LINE_END_SHIFT)) & \
36346 MIPI_CSI_INTERRUPT_SOURCE_1_LINE_END_MASK)
36347/*! @} */
36348
36349/*! @name DPHY_STATUS - D-PHY status register */
36350/*! @{ */
36351#define MIPI_CSI_DPHY_STATUS_STOPSTATECLK_MASK (0x1U)
36352#define MIPI_CSI_DPHY_STATUS_STOPSTATECLK_SHIFT (0U)
36353/*! STOPSTATECLK
36354 * 0b0..Not Stop state
36355 * 0b1..Stop state
36356 */
36357#define MIPI_CSI_DPHY_STATUS_STOPSTATECLK(x) \
36358 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_STATUS_STOPSTATECLK_SHIFT)) & MIPI_CSI_DPHY_STATUS_STOPSTATECLK_MASK)
36359#define MIPI_CSI_DPHY_STATUS_ULPSCLK_MASK (0x2U)
36360#define MIPI_CSI_DPHY_STATUS_ULPSCLK_SHIFT (1U)
36361/*! ULPSCLK
36362 * 0b0..Not ULPS
36363 * 0b1..ULPS
36364 */
36365#define MIPI_CSI_DPHY_STATUS_ULPSCLK(x) \
36366 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_STATUS_ULPSCLK_SHIFT)) & MIPI_CSI_DPHY_STATUS_ULPSCLK_MASK)
36367#define MIPI_CSI_DPHY_STATUS_STOPSTATEDAT_MASK (0xF0U)
36368#define MIPI_CSI_DPHY_STATUS_STOPSTATEDAT_SHIFT (4U)
36369/*! STOPSTATEDAT - Data lane [3:0] is in Stop State
36370 * 0b0000..Not Stop state
36371 * 0b0001..Stop state
36372 */
36373#define MIPI_CSI_DPHY_STATUS_STOPSTATEDAT(x) \
36374 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_STATUS_STOPSTATEDAT_SHIFT)) & MIPI_CSI_DPHY_STATUS_STOPSTATEDAT_MASK)
36375#define MIPI_CSI_DPHY_STATUS_ULPSDAT_MASK (0xF00U)
36376#define MIPI_CSI_DPHY_STATUS_ULPSDAT_SHIFT (8U)
36377/*! ULPSDAT - Data lane [3:0] is in ULPS
36378 * 0b0000..Not ULPS
36379 * 0b0001..ULPS
36380 */
36381#define MIPI_CSI_DPHY_STATUS_ULPSDAT(x) \
36382 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_STATUS_ULPSDAT_SHIFT)) & MIPI_CSI_DPHY_STATUS_ULPSDAT_MASK)
36383/*! @} */
36384
36385/*! @name DPHY_COMMON_CTRL - D-PHY common control register */
36386/*! @{ */
36387#define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_CLK_MASK (0x1U)
36388#define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_CLK_SHIFT (0U)
36389/*! ENABLE_CLK
36390 * 0b0..Disable
36391 * 0b1..Enable
36392 */
36393#define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_CLK(x) \
36394 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_CLK_SHIFT)) & \
36395 MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_CLK_MASK)
36396#define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_DAT_MASK (0x1EU)
36397#define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_DAT_SHIFT (1U)
36398/*! ENABLE_DAT - D-PHY enable
36399 * 0b0000..Disable
36400 * 0b0001..Enable
36401 */
36402#define MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_DAT(x) \
36403 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_DAT_SHIFT)) & \
36404 MIPI_CSI_DPHY_COMMON_CTRL_ENABLE_DAT_MASK)
36405#define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_DAT_MASK (0x20U)
36406#define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_DAT_SHIFT (5U)
36407/*! S_DPDN_SWAP_DAT - Swapping Dp and Dn channel of data lanes.
36408 * 0b0..Default
36409 * 0b1..Swapped
36410 */
36411#define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_DAT(x) \
36412 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_DAT_SHIFT)) & \
36413 MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_DAT_MASK)
36414#define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_CLK_MASK (0x40U)
36415#define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_CLK_SHIFT (6U)
36416/*! S_DPDN_SWAP_CLK
36417 * 0b0..Default
36418 * 0b1..Swapped
36419 */
36420#define MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_CLK(x) \
36421 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_CLK_SHIFT)) & \
36422 MIPI_CSI_DPHY_COMMON_CTRL_S_DPDN_SWAP_CLK_MASK)
36423#define MIPI_CSI_DPHY_COMMON_CTRL_S_CLKSETTLECTL_MASK (0xC00000U)
36424#define MIPI_CSI_DPHY_COMMON_CTRL_S_CLKSETTLECTL_SHIFT (22U)
36425#define MIPI_CSI_DPHY_COMMON_CTRL_S_CLKSETTLECTL(x) \
36426 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_S_CLKSETTLECTL_SHIFT)) & \
36427 MIPI_CSI_DPHY_COMMON_CTRL_S_CLKSETTLECTL_MASK)
36428#define MIPI_CSI_DPHY_COMMON_CTRL_HSSETTLE_MASK (0xFF000000U)
36429#define MIPI_CSI_DPHY_COMMON_CTRL_HSSETTLE_SHIFT (24U)
36430#define MIPI_CSI_DPHY_COMMON_CTRL_HSSETTLE(x) \
36431 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_COMMON_CTRL_HSSETTLE_SHIFT)) & \
36432 MIPI_CSI_DPHY_COMMON_CTRL_HSSETTLE_MASK)
36433/*! @} */
36434
36435/*! @name DPHY_MASTER_SLAVE_CTRL_LOW - D-PHY Master and Slave Control register Low */
36436/*! @{ */
36437#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_B_DPHYCTRL_MASK (0xFFFFFFFFU)
36438#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_B_DPHYCTRL_SHIFT (0U)
36439#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_B_DPHYCTRL(x) \
36440 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_B_DPHYCTRL_SHIFT)) & \
36441 MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_LOW_B_DPHYCTRL_MASK)
36442/*! @} */
36443
36444/*! @name DPHY_MASTER_SLAVE_CTRL_HIGH - D-PHY Master and Slave Control register HIGH */
36445/*! @{ */
36446#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_B_DPHYCTRL_MASK (0xFFFFFFFFU)
36447#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_B_DPHYCTRL_SHIFT (0U)
36448#define MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_B_DPHYCTRL(x) \
36449 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_B_DPHYCTRL_SHIFT)) & \
36450 MIPI_CSI_DPHY_MASTER_SLAVE_CTRL_HIGH_B_DPHYCTRL_MASK)
36451/*! @} */
36452
36453/*! @name DPHY_SLAVE_CTRL_LOW - D-PHY Slave Control register Low */
36454/*! @{ */
36455#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_S_DPHYCTRL_MASK (0xFFFFFFFFU)
36456#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_S_DPHYCTRL_SHIFT (0U)
36457#define MIPI_CSI_DPHY_SLAVE_CTRL_LOW_S_DPHYCTRL(x) \
36458 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_LOW_S_DPHYCTRL_SHIFT)) & \
36459 MIPI_CSI_DPHY_SLAVE_CTRL_LOW_S_DPHYCTRL_MASK)
36460/*! @} */
36461
36462/*! @name DPHY_SLAVE_CTRL_HIGH - D-PHY Slave Control register HIGH */
36463/*! @{ */
36464#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_S_DPHYCTRL_MASK (0xFFFFFFFFU)
36465#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_S_DPHYCTRL_SHIFT (0U)
36466#define MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_S_DPHYCTRL(x) \
36467 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_S_DPHYCTRL_SHIFT)) & \
36468 MIPI_CSI_DPHY_SLAVE_CTRL_HIGH_S_DPHYCTRL_MASK)
36469/*! @} */
36470
36471/*! @name ISP_CONFIG - ISP Configuration Register */
36472/*! @{ */
36473#define MIPI_CSI_ISP_CONFIG_DATAFORMAT_MASK (0xFCU)
36474#define MIPI_CSI_ISP_CONFIG_DATAFORMAT_SHIFT (2U)
36475#define MIPI_CSI_ISP_CONFIG_DATAFORMAT(x) \
36476 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_CONFIG_DATAFORMAT_SHIFT)) & MIPI_CSI_ISP_CONFIG_DATAFORMAT_MASK)
36477#define MIPI_CSI_ISP_CONFIG_RGB_SWAP_MASK (0x400U)
36478#define MIPI_CSI_ISP_CONFIG_RGB_SWAP_SHIFT (10U)
36479/*! RGB_SWAP
36480 * 0b0..MSB is R and LSB is B
36481 * 0b1..MSB is B and LSB is R (swapped)
36482 */
36483#define MIPI_CSI_ISP_CONFIG_RGB_SWAP(x) \
36484 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_CONFIG_RGB_SWAP_SHIFT)) & MIPI_CSI_ISP_CONFIG_RGB_SWAP_MASK)
36485#define MIPI_CSI_ISP_CONFIG_PARALLEL_MASK (0x800U)
36486#define MIPI_CSI_ISP_CONFIG_PARALLEL_SHIFT (11U)
36487/*! PARALLEL - Output bus width of CH0 is 32 bits.
36488 * 0b0..Normal output
36489 * 0b1..32bit data alignment
36490 */
36491#define MIPI_CSI_ISP_CONFIG_PARALLEL(x) \
36492 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_CONFIG_PARALLEL_SHIFT)) & MIPI_CSI_ISP_CONFIG_PARALLEL_MASK)
36493#define MIPI_CSI_ISP_CONFIG_PIXEL_MODE_MASK (0x3000U)
36494#define MIPI_CSI_ISP_CONFIG_PIXEL_MODE_SHIFT (12U)
36495#define MIPI_CSI_ISP_CONFIG_PIXEL_MODE(x) \
36496 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_CONFIG_PIXEL_MODE_SHIFT)) & MIPI_CSI_ISP_CONFIG_PIXEL_MODE_MASK)
36497/*! @} */
36498
36499/* The count of MIPI_CSI_ISP_CONFIG */
36500#define MIPI_CSI_ISP_CONFIG_COUNT (4U)
36501
36502/*! @name ISP_RESOLUTION - ISP Resolution Register */
36503/*! @{ */
36504#define MIPI_CSI_ISP_RESOLUTION_HRESOL_MASK (0xFFFFU)
36505#define MIPI_CSI_ISP_RESOLUTION_HRESOL_SHIFT (0U)
36506#define MIPI_CSI_ISP_RESOLUTION_HRESOL(x) \
36507 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_RESOLUTION_HRESOL_SHIFT)) & MIPI_CSI_ISP_RESOLUTION_HRESOL_MASK)
36508#define MIPI_CSI_ISP_RESOLUTION_VRESOL_MASK (0xFFFF0000U)
36509#define MIPI_CSI_ISP_RESOLUTION_VRESOL_SHIFT (16U)
36510#define MIPI_CSI_ISP_RESOLUTION_VRESOL(x) \
36511 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_RESOLUTION_VRESOL_SHIFT)) & MIPI_CSI_ISP_RESOLUTION_VRESOL_MASK)
36512/*! @} */
36513
36514/* The count of MIPI_CSI_ISP_RESOLUTION */
36515#define MIPI_CSI_ISP_RESOLUTION_COUNT (4U)
36516
36517/*! @name ISP_SYNC - ISP SYNC Register */
36518/*! @{ */
36519#define MIPI_CSI_ISP_SYNC_HSYNC_LINTV_MASK (0xFC0000U)
36520#define MIPI_CSI_ISP_SYNC_HSYNC_LINTV_SHIFT (18U)
36521#define MIPI_CSI_ISP_SYNC_HSYNC_LINTV(x) \
36522 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_ISP_SYNC_HSYNC_LINTV_SHIFT)) & MIPI_CSI_ISP_SYNC_HSYNC_LINTV_MASK)
36523/*! @} */
36524
36525/* The count of MIPI_CSI_ISP_SYNC */
36526#define MIPI_CSI_ISP_SYNC_COUNT (4U)
36527
36528/*! @name SHADOW_CONFIG - Shadow Configuration Register */
36529/*! @{ */
36530#define MIPI_CSI_SHADOW_CONFIG_VIRTUAL_CHANNEL_MASK (0x3U)
36531#define MIPI_CSI_SHADOW_CONFIG_VIRTUAL_CHANNEL_SHIFT (0U)
36532#define MIPI_CSI_SHADOW_CONFIG_VIRTUAL_CHANNEL(x) \
36533 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_CONFIG_VIRTUAL_CHANNEL_SHIFT)) & \
36534 MIPI_CSI_SHADOW_CONFIG_VIRTUAL_CHANNEL_MASK)
36535#define MIPI_CSI_SHADOW_CONFIG_DATAFORMAT_MASK (0xFCU)
36536#define MIPI_CSI_SHADOW_CONFIG_DATAFORMAT_SHIFT (2U)
36537#define MIPI_CSI_SHADOW_CONFIG_DATAFORMAT(x) \
36538 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_CONFIG_DATAFORMAT_SHIFT)) & MIPI_CSI_SHADOW_CONFIG_DATAFORMAT_MASK)
36539#define MIPI_CSI_SHADOW_CONFIG_RGB_SWAP_SDW_MASK (0x400U)
36540#define MIPI_CSI_SHADOW_CONFIG_RGB_SWAP_SDW_SHIFT (10U)
36541#define MIPI_CSI_SHADOW_CONFIG_RGB_SWAP_SDW(x) \
36542 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_CONFIG_RGB_SWAP_SDW_SHIFT)) & \
36543 MIPI_CSI_SHADOW_CONFIG_RGB_SWAP_SDW_MASK)
36544#define MIPI_CSI_SHADOW_CONFIG_PARALLEL_SDW_MASK (0x800U)
36545#define MIPI_CSI_SHADOW_CONFIG_PARALLEL_SDW_SHIFT (11U)
36546#define MIPI_CSI_SHADOW_CONFIG_PARALLEL_SDW(x) \
36547 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_CONFIG_PARALLEL_SDW_SHIFT)) & \
36548 MIPI_CSI_SHADOW_CONFIG_PARALLEL_SDW_MASK)
36549#define MIPI_CSI_SHADOW_CONFIG_PIXEL_MODE_MASK (0x3000U)
36550#define MIPI_CSI_SHADOW_CONFIG_PIXEL_MODE_SHIFT (12U)
36551#define MIPI_CSI_SHADOW_CONFIG_PIXEL_MODE(x) \
36552 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_CONFIG_PIXEL_MODE_SHIFT)) & MIPI_CSI_SHADOW_CONFIG_PIXEL_MODE_MASK)
36553/*! @} */
36554
36555/* The count of MIPI_CSI_SHADOW_CONFIG */
36556#define MIPI_CSI_SHADOW_CONFIG_COUNT (4U)
36557
36558/*! @name SHADOW_RESOLUTION - Shadow Resolution Register */
36559/*! @{ */
36560#define MIPI_CSI_SHADOW_RESOLUTION_HRESOL_SDW_MASK (0xFFFFU)
36561#define MIPI_CSI_SHADOW_RESOLUTION_HRESOL_SDW_SHIFT (0U)
36562#define MIPI_CSI_SHADOW_RESOLUTION_HRESOL_SDW(x) \
36563 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_RESOLUTION_HRESOL_SDW_SHIFT)) & \
36564 MIPI_CSI_SHADOW_RESOLUTION_HRESOL_SDW_MASK)
36565#define MIPI_CSI_SHADOW_RESOLUTION_VRESOL_SDW_MASK (0xFFFF0000U)
36566#define MIPI_CSI_SHADOW_RESOLUTION_VRESOL_SDW_SHIFT (16U)
36567#define MIPI_CSI_SHADOW_RESOLUTION_VRESOL_SDW(x) \
36568 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_RESOLUTION_VRESOL_SDW_SHIFT)) & \
36569 MIPI_CSI_SHADOW_RESOLUTION_VRESOL_SDW_MASK)
36570/*! @} */
36571
36572/* The count of MIPI_CSI_SHADOW_RESOLUTION */
36573#define MIPI_CSI_SHADOW_RESOLUTION_COUNT (4U)
36574
36575/*! @name SHADOW_SYNC - Shadow SYNC Register */
36576/*! @{ */
36577#define MIPI_CSI_SHADOW_SYNC_HSYNC_LINTV_SDW_MASK (0xFC0000U)
36578#define MIPI_CSI_SHADOW_SYNC_HSYNC_LINTV_SDW_SHIFT (18U)
36579#define MIPI_CSI_SHADOW_SYNC_HSYNC_LINTV_SDW(x) \
36580 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_SHADOW_SYNC_HSYNC_LINTV_SDW_SHIFT)) & \
36581 MIPI_CSI_SHADOW_SYNC_HSYNC_LINTV_SDW_MASK)
36582/*! @} */
36583
36584/* The count of MIPI_CSI_SHADOW_SYNC */
36585#define MIPI_CSI_SHADOW_SYNC_COUNT (4U)
36586
36587/*! @name FRAME_COUNTER - Frame Counter */
36588/*! @{ */
36589#define MIPI_CSI_FRAME_COUNTER_FRM_CNT_MASK (0xFFFFFFFFU)
36590#define MIPI_CSI_FRAME_COUNTER_FRM_CNT_SHIFT (0U)
36591#define MIPI_CSI_FRAME_COUNTER_FRM_CNT(x) \
36592 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_FRAME_COUNTER_FRM_CNT_SHIFT)) & MIPI_CSI_FRAME_COUNTER_FRM_CNT_MASK)
36593/*! @} */
36594
36595/* The count of MIPI_CSI_FRAME_COUNTER */
36596#define MIPI_CSI_FRAME_COUNTER_COUNT (4U)
36597
36598/*! @name LINE_INTERRUPT_RATIO - Line Interrupt Ratio */
36599/*! @{ */
36600#define MIPI_CSI_LINE_INTERRUPT_RATIO_LINE_INTR_MASK (0xFFFFFFFFU)
36601#define MIPI_CSI_LINE_INTERRUPT_RATIO_LINE_INTR_SHIFT (0U)
36602#define MIPI_CSI_LINE_INTERRUPT_RATIO_LINE_INTR(x) \
36603 (((uint32_t)(((uint32_t)(x)) << MIPI_CSI_LINE_INTERRUPT_RATIO_LINE_INTR_SHIFT)) & \
36604 MIPI_CSI_LINE_INTERRUPT_RATIO_LINE_INTR_MASK)
36605/*! @} */
36606
36607/* The count of MIPI_CSI_LINE_INTERRUPT_RATIO */
36608#define MIPI_CSI_LINE_INTERRUPT_RATIO_COUNT (4U)
36609
36610/*!
36611 * @}
36612 */ /* end of group MIPI_CSI_Register_Masks */
36613
36614/* MIPI_CSI - Peripheral instance base addresses */
36615/** Peripheral MIPI_CSI base address */
36616#define MIPI_CSI_BASE (0x32E30000u)
36617/** Peripheral MIPI_CSI base pointer */
36618#define MIPI_CSI ((MIPI_CSI_Type *)MIPI_CSI_BASE)
36619/** Array initializer of MIPI_CSI peripheral base addresses */
36620#define MIPI_CSI_BASE_ADDRS \
36621 { \
36622 MIPI_CSI_BASE \
36623 }
36624/** Array initializer of MIPI_CSI peripheral base pointers */
36625#define MIPI_CSI_BASE_PTRS \
36626 { \
36627 MIPI_CSI \
36628 }
36629
36630/*!
36631 * @}
36632 */ /* end of group MIPI_CSI_Peripheral_Access_Layer */
36633
36634/* ----------------------------------------------------------------------------
36635 -- MIPI_DSI Peripheral Access Layer
36636 ---------------------------------------------------------------------------- */
36637
36638/*!
36639 * @addtogroup MIPI_DSI_Peripheral_Access_Layer MIPI_DSI Peripheral Access Layer
36640 * @{
36641 */
36642
36643/** MIPI_DSI - Register Layout Typedef */
36644typedef struct
36645{
36646 __I uint32_t DSI_VERSION; /**< Specifies the DSI version register., offset: 0x0 */
36647 __I uint32_t DSI_STATUS; /**< Specifies the status register., offset: 0x4 */
36648 __I uint32_t DSI_RGB_STATUS; /**< Specifies the RGB FSM status register., offset: 0x8 */
36649 __IO uint32_t DSI_SWRST; /**< Specifies the software reset register., offset: 0xC */
36650 __IO uint32_t DSI_CLKCTRL; /**< Specifies the clock control register., offset: 0x10 */
36651 __IO uint32_t DSI_TIMEOUT; /**< Specifies the time out register., offset: 0x14 */
36652 __IO uint32_t DSI_CONFIG; /**< Specifies the configuration register., offset: 0x18 */
36653 __IO uint32_t DSI_ESCMODE; /**< Specifies the escape mode register., offset: 0x1C */
36654 __IO uint32_t DSI_MDRESOL; /**< Specifies the main display image resolution register., offset: 0x20 */
36655 __IO uint32_t DSI_MVPORCH; /**< Specifies the main display Vporch register., offset: 0x24 */
36656 __IO uint32_t DSI_MHPORCH; /**< Specifies the main display Hporch register., offset: 0x28 */
36657 __IO uint32_t DSI_MSYNC; /**< Specifies the main display Sync Area register., offset: 0x2C */
36658 __IO uint32_t DSI_SDRESOL; /**< Specifies the sub display image resolution register., offset: 0x30 */
36659 __IO uint32_t DSI_INTSRC; /**< Specifies the interrupt source register., offset: 0x34 */
36660 __IO uint32_t DSI_INTMSK; /**< Specifies the interrupt mask register., offset: 0x38 */
36661 __O uint32_t DSI_PKTHDR; /**< Specifies the packet header FIFO register., offset: 0x3C */
36662 __O uint32_t DSI_PAYLOAD; /**< Specifies the payload FIFO register., offset: 0x40 */
36663 __I uint32_t DSI_RXFIFO; /**< Specifies the read FIFO register., offset: 0x44 */
36664 __IO uint32_t DSI_FIFOTHLD; /**< Specifies the FIFO threshold level register., offset: 0x48 */
36665 __IO uint32_t DSI_FIFOCTRL; /**< Specifies the FIFO status and control register., offset: 0x4C */
36666 __IO uint32_t DSI_MEMACCHR; /**< Specifies the FIFO memory AC characteristic register., offset: 0x50 */
36667 uint8_t RESERVED_0[36];
36668 __IO uint32_t DSI_MULTI_PKT; /**< Specifies the Multi Packet, Packet Go register., offset: 0x78 */
36669 uint8_t RESERVED_1[20];
36670 __IO uint32_t DSI_PLLCTRL_1G; /**< Specifies the 1Gbps D-PHY PLL control register., offset: 0x90 */
36671 __IO uint32_t DSI_PLLCTRL; /**< Specifies the PLL control register., offset: 0x94 */
36672 __IO uint32_t DSI_PLLCTRL1; /**< Specifies the PLL control register 1., offset: 0x98 */
36673 __IO uint32_t DSI_PLLCTRL2; /**< Specifies the PLL control register 2., offset: 0x9C */
36674 __IO uint32_t DSI_PLLTMR; /**< Specifies the PLL timer register., offset: 0xA0 */
36675 __IO uint32_t DSI_PHYCTRL_B1; /**< Specifies the D-PHY control register 1., offset: 0xA4 */
36676 __IO uint32_t DSI_PHYCTRL_B2; /**< Specifies the D-PHY control register 2., offset: 0xA8 */
36677 __IO uint32_t DSI_PHYCTRL_M1; /**< Specifies the D-PHY control register 1., offset: 0xAC */
36678 __IO uint32_t DSI_PHYCTRL_M2; /**< Specifies the D-PHY control register 2., offset: 0xB0 */
36679 __IO uint32_t DSI_PHYTIMING; /**< Specifies the D-PHY timing register., offset: 0xB4 */
36680 __IO uint32_t DSI_PHYTIMING1; /**< Specifies the D-PHY timing register 1., offset: 0xB8 */
36681 __IO uint32_t DSI_PHYTIMING2; /**< Specifies the D-PHY timing register 2., offset: 0xBC */
36682} MIPI_DSI_Type;
36683
36684/* ----------------------------------------------------------------------------
36685 -- MIPI_DSI Register Masks
36686 ---------------------------------------------------------------------------- */
36687
36688/*!
36689 * @addtogroup MIPI_DSI_Register_Masks MIPI_DSI Register Masks
36690 * @{
36691 */
36692
36693/*! @name DSI_VERSION - Specifies the DSI version register. */
36694/*! @{ */
36695#define MIPI_DSI_DSI_VERSION_Version_MASK (0xFFFFFFFFU)
36696#define MIPI_DSI_DSI_VERSION_Version_SHIFT (0U)
36697#define MIPI_DSI_DSI_VERSION_Version(x) \
36698 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_VERSION_Version_SHIFT)) & MIPI_DSI_DSI_VERSION_Version_MASK)
36699/*! @} */
36700
36701/*! @name DSI_STATUS - Specifies the status register. */
36702/*! @{ */
36703#define MIPI_DSI_DSI_STATUS_StopstateDat_MASK (0xFU)
36704#define MIPI_DSI_DSI_STATUS_StopstateDat_SHIFT (0U)
36705#define MIPI_DSI_DSI_STATUS_StopstateDat(x) \
36706 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_StopstateDat_SHIFT)) & MIPI_DSI_DSI_STATUS_StopstateDat_MASK)
36707#define MIPI_DSI_DSI_STATUS_UlpsDat_MASK (0xF0U)
36708#define MIPI_DSI_DSI_STATUS_UlpsDat_SHIFT (4U)
36709#define MIPI_DSI_DSI_STATUS_UlpsDat(x) \
36710 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_UlpsDat_SHIFT)) & MIPI_DSI_DSI_STATUS_UlpsDat_MASK)
36711#define MIPI_DSI_DSI_STATUS_StopstateClk_MASK (0x100U)
36712#define MIPI_DSI_DSI_STATUS_StopstateClk_SHIFT (8U)
36713#define MIPI_DSI_DSI_STATUS_StopstateClk(x) \
36714 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_StopstateClk_SHIFT)) & MIPI_DSI_DSI_STATUS_StopstateClk_MASK)
36715#define MIPI_DSI_DSI_STATUS_UlpsClk_MASK (0x200U)
36716#define MIPI_DSI_DSI_STATUS_UlpsClk_SHIFT (9U)
36717#define MIPI_DSI_DSI_STATUS_UlpsClk(x) \
36718 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_UlpsClk_SHIFT)) & MIPI_DSI_DSI_STATUS_UlpsClk_MASK)
36719#define MIPI_DSI_DSI_STATUS_TxReadyHsClk_MASK (0x400U)
36720#define MIPI_DSI_DSI_STATUS_TxReadyHsClk_SHIFT (10U)
36721#define MIPI_DSI_DSI_STATUS_TxReadyHsClk(x) \
36722 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_TxReadyHsClk_SHIFT)) & MIPI_DSI_DSI_STATUS_TxReadyHsClk_MASK)
36723#define MIPI_DSI_DSI_STATUS_Direction_MASK (0x10000U)
36724#define MIPI_DSI_DSI_STATUS_Direction_SHIFT (16U)
36725#define MIPI_DSI_DSI_STATUS_Direction(x) \
36726 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_Direction_SHIFT)) & MIPI_DSI_DSI_STATUS_Direction_MASK)
36727#define MIPI_DSI_DSI_STATUS_SwRstRls_MASK (0x100000U)
36728#define MIPI_DSI_DSI_STATUS_SwRstRls_SHIFT (20U)
36729#define MIPI_DSI_DSI_STATUS_SwRstRls(x) \
36730 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_SwRstRls_SHIFT)) & MIPI_DSI_DSI_STATUS_SwRstRls_MASK)
36731#define MIPI_DSI_DSI_STATUS_PllStable_MASK (0x80000000U)
36732#define MIPI_DSI_DSI_STATUS_PllStable_SHIFT (31U)
36733#define MIPI_DSI_DSI_STATUS_PllStable(x) \
36734 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_STATUS_PllStable_SHIFT)) & MIPI_DSI_DSI_STATUS_PllStable_MASK)
36735/*! @} */
36736
36737/*! @name DSI_RGB_STATUS - Specifies the RGB FSM status register. */
36738/*! @{ */
36739#define MIPI_DSI_DSI_RGB_STATUS_RGBstate_MASK (0x1FFFU)
36740#define MIPI_DSI_DSI_RGB_STATUS_RGBstate_SHIFT (0U)
36741#define MIPI_DSI_DSI_RGB_STATUS_RGBstate(x) \
36742 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_RGB_STATUS_RGBstate_SHIFT)) & MIPI_DSI_DSI_RGB_STATUS_RGBstate_MASK)
36743#define MIPI_DSI_DSI_RGB_STATUS_CmdMode_InSel_MASK (0x80000000U)
36744#define MIPI_DSI_DSI_RGB_STATUS_CmdMode_InSel_SHIFT (31U)
36745#define MIPI_DSI_DSI_RGB_STATUS_CmdMode_InSel(x) \
36746 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_RGB_STATUS_CmdMode_InSel_SHIFT)) & \
36747 MIPI_DSI_DSI_RGB_STATUS_CmdMode_InSel_MASK)
36748/*! @} */
36749
36750/*! @name DSI_SWRST - Specifies the software reset register. */
36751/*! @{ */
36752#define MIPI_DSI_DSI_SWRST_SwRst_MASK (0x1U)
36753#define MIPI_DSI_DSI_SWRST_SwRst_SHIFT (0U)
36754#define MIPI_DSI_DSI_SWRST_SwRst(x) \
36755 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_SWRST_SwRst_SHIFT)) & MIPI_DSI_DSI_SWRST_SwRst_MASK)
36756#define MIPI_DSI_DSI_SWRST_FuncRst_MASK (0x10000U)
36757#define MIPI_DSI_DSI_SWRST_FuncRst_SHIFT (16U)
36758#define MIPI_DSI_DSI_SWRST_FuncRst(x) \
36759 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_SWRST_FuncRst_SHIFT)) & MIPI_DSI_DSI_SWRST_FuncRst_MASK)
36760/*! @} */
36761
36762/*! @name DSI_CLKCTRL - Specifies the clock control register. */
36763/*! @{ */
36764#define MIPI_DSI_DSI_CLKCTRL_EscPrescaler_MASK (0xFFFFU)
36765#define MIPI_DSI_DSI_CLKCTRL_EscPrescaler_SHIFT (0U)
36766#define MIPI_DSI_DSI_CLKCTRL_EscPrescaler(x) \
36767 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_EscPrescaler_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_EscPrescaler_MASK)
36768#define MIPI_DSI_DSI_CLKCTRL_LaneEscClkEn_MASK (0xF80000U)
36769#define MIPI_DSI_DSI_CLKCTRL_LaneEscClkEn_SHIFT (19U)
36770#define MIPI_DSI_DSI_CLKCTRL_LaneEscClkEn(x) \
36771 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_LaneEscClkEn_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_LaneEscClkEn_MASK)
36772#define MIPI_DSI_DSI_CLKCTRL_ByteClkEn_MASK (0x1000000U)
36773#define MIPI_DSI_DSI_CLKCTRL_ByteClkEn_SHIFT (24U)
36774#define MIPI_DSI_DSI_CLKCTRL_ByteClkEn(x) \
36775 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_ByteClkEn_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_ByteClkEn_MASK)
36776#define MIPI_DSI_DSI_CLKCTRL_ByteClkSrc_MASK (0x6000000U)
36777#define MIPI_DSI_DSI_CLKCTRL_ByteClkSrc_SHIFT (25U)
36778#define MIPI_DSI_DSI_CLKCTRL_ByteClkSrc(x) \
36779 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_ByteClkSrc_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_ByteClkSrc_MASK)
36780#define MIPI_DSI_DSI_CLKCTRL_PLLBypass_MASK (0x8000000U)
36781#define MIPI_DSI_DSI_CLKCTRL_PLLBypass_SHIFT (27U)
36782#define MIPI_DSI_DSI_CLKCTRL_PLLBypass(x) \
36783 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_PLLBypass_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_PLLBypass_MASK)
36784#define MIPI_DSI_DSI_CLKCTRL_EscClkEn_MASK (0x10000000U)
36785#define MIPI_DSI_DSI_CLKCTRL_EscClkEn_SHIFT (28U)
36786#define MIPI_DSI_DSI_CLKCTRL_EscClkEn(x) \
36787 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_EscClkEn_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_EscClkEn_MASK)
36788#define MIPI_DSI_DSI_CLKCTRL_Dphy_sel_MASK (0x20000000U)
36789#define MIPI_DSI_DSI_CLKCTRL_Dphy_sel_SHIFT (29U)
36790#define MIPI_DSI_DSI_CLKCTRL_Dphy_sel(x) \
36791 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_Dphy_sel_SHIFT)) & MIPI_DSI_DSI_CLKCTRL_Dphy_sel_MASK)
36792#define MIPI_DSI_DSI_CLKCTRL_TxRequestHsClk_MASK (0x80000000U)
36793#define MIPI_DSI_DSI_CLKCTRL_TxRequestHsClk_SHIFT (31U)
36794#define MIPI_DSI_DSI_CLKCTRL_TxRequestHsClk(x) \
36795 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CLKCTRL_TxRequestHsClk_SHIFT)) & \
36796 MIPI_DSI_DSI_CLKCTRL_TxRequestHsClk_MASK)
36797/*! @} */
36798
36799/*! @name DSI_TIMEOUT - Specifies the time out register. */
36800/*! @{ */
36801#define MIPI_DSI_DSI_TIMEOUT_LpdrTout_MASK (0xFFFFU)
36802#define MIPI_DSI_DSI_TIMEOUT_LpdrTout_SHIFT (0U)
36803#define MIPI_DSI_DSI_TIMEOUT_LpdrTout(x) \
36804 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_TIMEOUT_LpdrTout_SHIFT)) & MIPI_DSI_DSI_TIMEOUT_LpdrTout_MASK)
36805#define MIPI_DSI_DSI_TIMEOUT_BtaTout_MASK (0xFF0000U)
36806#define MIPI_DSI_DSI_TIMEOUT_BtaTout_SHIFT (16U)
36807#define MIPI_DSI_DSI_TIMEOUT_BtaTout(x) \
36808 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_TIMEOUT_BtaTout_SHIFT)) & MIPI_DSI_DSI_TIMEOUT_BtaTout_MASK)
36809/*! @} */
36810
36811/*! @name DSI_CONFIG - Specifies the configuration register. */
36812/*! @{ */
36813#define MIPI_DSI_DSI_CONFIG_LaneEn_MASK (0x1FU)
36814#define MIPI_DSI_DSI_CONFIG_LaneEn_SHIFT (0U)
36815#define MIPI_DSI_DSI_CONFIG_LaneEn(x) \
36816 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_LaneEn_SHIFT)) & MIPI_DSI_DSI_CONFIG_LaneEn_MASK)
36817#define MIPI_DSI_DSI_CONFIG_NumOfDatLane_MASK (0x60U)
36818#define MIPI_DSI_DSI_CONFIG_NumOfDatLane_SHIFT (5U)
36819#define MIPI_DSI_DSI_CONFIG_NumOfDatLane(x) \
36820 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_NumOfDatLane_SHIFT)) & MIPI_DSI_DSI_CONFIG_NumOfDatLane_MASK)
36821#define MIPI_DSI_DSI_CONFIG_SubPixFormat_MASK (0x700U)
36822#define MIPI_DSI_DSI_CONFIG_SubPixFormat_SHIFT (8U)
36823#define MIPI_DSI_DSI_CONFIG_SubPixFormat(x) \
36824 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_SubPixFormat_SHIFT)) & MIPI_DSI_DSI_CONFIG_SubPixFormat_MASK)
36825#define MIPI_DSI_DSI_CONFIG_MainPixFormat_MASK (0x7000U)
36826#define MIPI_DSI_DSI_CONFIG_MainPixFormat_SHIFT (12U)
36827#define MIPI_DSI_DSI_CONFIG_MainPixFormat(x) \
36828 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_MainPixFormat_SHIFT)) & MIPI_DSI_DSI_CONFIG_MainPixFormat_MASK)
36829#define MIPI_DSI_DSI_CONFIG_SubVc_MASK (0x30000U)
36830#define MIPI_DSI_DSI_CONFIG_SubVc_SHIFT (16U)
36831#define MIPI_DSI_DSI_CONFIG_SubVc(x) \
36832 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_SubVc_SHIFT)) & MIPI_DSI_DSI_CONFIG_SubVc_MASK)
36833#define MIPI_DSI_DSI_CONFIG_MainVc_MASK (0xC0000U)
36834#define MIPI_DSI_DSI_CONFIG_MainVc_SHIFT (18U)
36835#define MIPI_DSI_DSI_CONFIG_MainVc(x) \
36836 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_MainVc_SHIFT)) & MIPI_DSI_DSI_CONFIG_MainVc_MASK)
36837#define MIPI_DSI_DSI_CONFIG_HsaDisableMode_MASK (0x100000U)
36838#define MIPI_DSI_DSI_CONFIG_HsaDisableMode_SHIFT (20U)
36839#define MIPI_DSI_DSI_CONFIG_HsaDisableMode(x) \
36840 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_HsaDisableMode_SHIFT)) & \
36841 MIPI_DSI_DSI_CONFIG_HsaDisableMode_MASK)
36842#define MIPI_DSI_DSI_CONFIG_HbpDisableMode_MASK (0x200000U)
36843#define MIPI_DSI_DSI_CONFIG_HbpDisableMode_SHIFT (21U)
36844#define MIPI_DSI_DSI_CONFIG_HbpDisableMode(x) \
36845 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_HbpDisableMode_SHIFT)) & \
36846 MIPI_DSI_DSI_CONFIG_HbpDisableMode_MASK)
36847#define MIPI_DSI_DSI_CONFIG_HfpDisableMode_MASK (0x400000U)
36848#define MIPI_DSI_DSI_CONFIG_HfpDisableMode_SHIFT (22U)
36849#define MIPI_DSI_DSI_CONFIG_HfpDisableMode(x) \
36850 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_HfpDisableMode_SHIFT)) & \
36851 MIPI_DSI_DSI_CONFIG_HfpDisableMode_MASK)
36852#define MIPI_DSI_DSI_CONFIG_HseDisableMode_MASK (0x800000U)
36853#define MIPI_DSI_DSI_CONFIG_HseDisableMode_SHIFT (23U)
36854#define MIPI_DSI_DSI_CONFIG_HseDisableMode(x) \
36855 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_HseDisableMode_SHIFT)) & \
36856 MIPI_DSI_DSI_CONFIG_HseDisableMode_MASK)
36857#define MIPI_DSI_DSI_CONFIG_AutoMode_MASK (0x1000000U)
36858#define MIPI_DSI_DSI_CONFIG_AutoMode_SHIFT (24U)
36859#define MIPI_DSI_DSI_CONFIG_AutoMode(x) \
36860 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_AutoMode_SHIFT)) & MIPI_DSI_DSI_CONFIG_AutoMode_MASK)
36861#define MIPI_DSI_DSI_CONFIG_VideoMode_MASK (0x2000000U)
36862#define MIPI_DSI_DSI_CONFIG_VideoMode_SHIFT (25U)
36863#define MIPI_DSI_DSI_CONFIG_VideoMode(x) \
36864 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_VideoMode_SHIFT)) & MIPI_DSI_DSI_CONFIG_VideoMode_MASK)
36865#define MIPI_DSI_DSI_CONFIG_BurstMode_MASK (0x4000000U)
36866#define MIPI_DSI_DSI_CONFIG_BurstMode_SHIFT (26U)
36867#define MIPI_DSI_DSI_CONFIG_BurstMode(x) \
36868 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_BurstMode_SHIFT)) & MIPI_DSI_DSI_CONFIG_BurstMode_MASK)
36869#define MIPI_DSI_DSI_CONFIG_SyncInform_MASK (0x8000000U)
36870#define MIPI_DSI_DSI_CONFIG_SyncInform_SHIFT (27U)
36871#define MIPI_DSI_DSI_CONFIG_SyncInform(x) \
36872 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_SyncInform_SHIFT)) & MIPI_DSI_DSI_CONFIG_SyncInform_MASK)
36873#define MIPI_DSI_DSI_CONFIG_EoT_r03_MASK (0x10000000U)
36874#define MIPI_DSI_DSI_CONFIG_EoT_r03_SHIFT (28U)
36875#define MIPI_DSI_DSI_CONFIG_EoT_r03(x) \
36876 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_EoT_r03_SHIFT)) & MIPI_DSI_DSI_CONFIG_EoT_r03_MASK)
36877#define MIPI_DSI_DSI_CONFIG_Mflush_VS_MASK (0x20000000U)
36878#define MIPI_DSI_DSI_CONFIG_Mflush_VS_SHIFT (29U)
36879#define MIPI_DSI_DSI_CONFIG_Mflush_VS(x) \
36880 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_Mflush_VS_SHIFT)) & MIPI_DSI_DSI_CONFIG_Mflush_VS_MASK)
36881#define MIPI_DSI_DSI_CONFIG_Clklane_Stop_Start_MASK (0x40000000U)
36882#define MIPI_DSI_DSI_CONFIG_Clklane_Stop_Start_SHIFT (30U)
36883#define MIPI_DSI_DSI_CONFIG_Clklane_Stop_Start(x) \
36884 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_Clklane_Stop_Start_SHIFT)) & \
36885 MIPI_DSI_DSI_CONFIG_Clklane_Stop_Start_MASK)
36886#define MIPI_DSI_DSI_CONFIG_Non_Continuous_clock_lane_MASK (0x80000000U)
36887#define MIPI_DSI_DSI_CONFIG_Non_Continuous_clock_lane_SHIFT (31U)
36888#define MIPI_DSI_DSI_CONFIG_Non_Continuous_clock_lane(x) \
36889 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_CONFIG_Non_Continuous_clock_lane_SHIFT)) & \
36890 MIPI_DSI_DSI_CONFIG_Non_Continuous_clock_lane_MASK)
36891/*! @} */
36892
36893/*! @name DSI_ESCMODE - Specifies the escape mode register. */
36894/*! @{ */
36895#define MIPI_DSI_DSI_ESCMODE_TxUlpsClkExit_MASK (0x1U)
36896#define MIPI_DSI_DSI_ESCMODE_TxUlpsClkExit_SHIFT (0U)
36897#define MIPI_DSI_DSI_ESCMODE_TxUlpsClkExit(x) \
36898 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TxUlpsClkExit_SHIFT)) & \
36899 MIPI_DSI_DSI_ESCMODE_TxUlpsClkExit_MASK)
36900#define MIPI_DSI_DSI_ESCMODE_TxUlpsClk_MASK (0x2U)
36901#define MIPI_DSI_DSI_ESCMODE_TxUlpsClk_SHIFT (1U)
36902#define MIPI_DSI_DSI_ESCMODE_TxUlpsClk(x) \
36903 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TxUlpsClk_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TxUlpsClk_MASK)
36904#define MIPI_DSI_DSI_ESCMODE_TxUlpsExit_MASK (0x4U)
36905#define MIPI_DSI_DSI_ESCMODE_TxUlpsExit_SHIFT (2U)
36906#define MIPI_DSI_DSI_ESCMODE_TxUlpsExit(x) \
36907 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TxUlpsExit_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TxUlpsExit_MASK)
36908#define MIPI_DSI_DSI_ESCMODE_TxUlpsDat_MASK (0x8U)
36909#define MIPI_DSI_DSI_ESCMODE_TxUlpsDat_SHIFT (3U)
36910#define MIPI_DSI_DSI_ESCMODE_TxUlpsDat(x) \
36911 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TxUlpsDat_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TxUlpsDat_MASK)
36912#define MIPI_DSI_DSI_ESCMODE_TxTriggerRst_MASK (0x10U)
36913#define MIPI_DSI_DSI_ESCMODE_TxTriggerRst_SHIFT (4U)
36914#define MIPI_DSI_DSI_ESCMODE_TxTriggerRst(x) \
36915 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TxTriggerRst_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TxTriggerRst_MASK)
36916#define MIPI_DSI_DSI_ESCMODE_TxLpdt_MASK (0x40U)
36917#define MIPI_DSI_DSI_ESCMODE_TxLpdt_SHIFT (6U)
36918#define MIPI_DSI_DSI_ESCMODE_TxLpdt(x) \
36919 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_TxLpdt_SHIFT)) & MIPI_DSI_DSI_ESCMODE_TxLpdt_MASK)
36920#define MIPI_DSI_DSI_ESCMODE_CmdLpdt_MASK (0x80U)
36921#define MIPI_DSI_DSI_ESCMODE_CmdLpdt_SHIFT (7U)
36922#define MIPI_DSI_DSI_ESCMODE_CmdLpdt(x) \
36923 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_CmdLpdt_SHIFT)) & MIPI_DSI_DSI_ESCMODE_CmdLpdt_MASK)
36924#define MIPI_DSI_DSI_ESCMODE_ForceBta_MASK (0x10000U)
36925#define MIPI_DSI_DSI_ESCMODE_ForceBta_SHIFT (16U)
36926#define MIPI_DSI_DSI_ESCMODE_ForceBta(x) \
36927 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_ForceBta_SHIFT)) & MIPI_DSI_DSI_ESCMODE_ForceBta_MASK)
36928#define MIPI_DSI_DSI_ESCMODE_ForceStopstate__MASK (0x100000U)
36929#define MIPI_DSI_DSI_ESCMODE_ForceStopstate__SHIFT (20U)
36930#define MIPI_DSI_DSI_ESCMODE_ForceStopstate_(x) \
36931 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_ForceStopstate__SHIFT)) & \
36932 MIPI_DSI_DSI_ESCMODE_ForceStopstate__MASK)
36933#define MIPI_DSI_DSI_ESCMODE_STOPstate_Cnt_MASK (0xFFE00000U)
36934#define MIPI_DSI_DSI_ESCMODE_STOPstate_Cnt_SHIFT (21U)
36935#define MIPI_DSI_DSI_ESCMODE_STOPstate_Cnt(x) \
36936 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_ESCMODE_STOPstate_Cnt_SHIFT)) & \
36937 MIPI_DSI_DSI_ESCMODE_STOPstate_Cnt_MASK)
36938/*! @} */
36939
36940/*! @name DSI_MDRESOL - Specifies the main display image resolution register. */
36941/*! @{ */
36942#define MIPI_DSI_DSI_MDRESOL_MainHResol_MASK (0xFFFU)
36943#define MIPI_DSI_DSI_MDRESOL_MainHResol_SHIFT (0U)
36944#define MIPI_DSI_DSI_MDRESOL_MainHResol(x) \
36945 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MDRESOL_MainHResol_SHIFT)) & MIPI_DSI_DSI_MDRESOL_MainHResol_MASK)
36946#define MIPI_DSI_DSI_MDRESOL_MainVResol_MASK (0xFFF0000U)
36947#define MIPI_DSI_DSI_MDRESOL_MainVResol_SHIFT (16U)
36948#define MIPI_DSI_DSI_MDRESOL_MainVResol(x) \
36949 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MDRESOL_MainVResol_SHIFT)) & MIPI_DSI_DSI_MDRESOL_MainVResol_MASK)
36950#define MIPI_DSI_DSI_MDRESOL_MainStandby_MASK (0x80000000U)
36951#define MIPI_DSI_DSI_MDRESOL_MainStandby_SHIFT (31U)
36952#define MIPI_DSI_DSI_MDRESOL_MainStandby(x) \
36953 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MDRESOL_MainStandby_SHIFT)) & MIPI_DSI_DSI_MDRESOL_MainStandby_MASK)
36954/*! @} */
36955
36956/*! @name DSI_MVPORCH - Specifies the main display Vporch register. */
36957/*! @{ */
36958#define MIPI_DSI_DSI_MVPORCH_MainVbp_MASK (0x7FFU)
36959#define MIPI_DSI_DSI_MVPORCH_MainVbp_SHIFT (0U)
36960#define MIPI_DSI_DSI_MVPORCH_MainVbp(x) \
36961 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MVPORCH_MainVbp_SHIFT)) & MIPI_DSI_DSI_MVPORCH_MainVbp_MASK)
36962#define MIPI_DSI_DSI_MVPORCH_StableVfp_MASK (0x7FF0000U)
36963#define MIPI_DSI_DSI_MVPORCH_StableVfp_SHIFT (16U)
36964#define MIPI_DSI_DSI_MVPORCH_StableVfp(x) \
36965 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MVPORCH_StableVfp_SHIFT)) & MIPI_DSI_DSI_MVPORCH_StableVfp_MASK)
36966#define MIPI_DSI_DSI_MVPORCH_CmdAllow_MASK (0xF0000000U)
36967#define MIPI_DSI_DSI_MVPORCH_CmdAllow_SHIFT (28U)
36968#define MIPI_DSI_DSI_MVPORCH_CmdAllow(x) \
36969 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MVPORCH_CmdAllow_SHIFT)) & MIPI_DSI_DSI_MVPORCH_CmdAllow_MASK)
36970/*! @} */
36971
36972/*! @name DSI_MHPORCH - Specifies the main display Hporch register. */
36973/*! @{ */
36974#define MIPI_DSI_DSI_MHPORCH_MainHbp_MASK (0xFFFFU)
36975#define MIPI_DSI_DSI_MHPORCH_MainHbp_SHIFT (0U)
36976#define MIPI_DSI_DSI_MHPORCH_MainHbp(x) \
36977 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MHPORCH_MainHbp_SHIFT)) & MIPI_DSI_DSI_MHPORCH_MainHbp_MASK)
36978#define MIPI_DSI_DSI_MHPORCH_MainHfp_MASK (0xFFFF0000U)
36979#define MIPI_DSI_DSI_MHPORCH_MainHfp_SHIFT (16U)
36980#define MIPI_DSI_DSI_MHPORCH_MainHfp(x) \
36981 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MHPORCH_MainHfp_SHIFT)) & MIPI_DSI_DSI_MHPORCH_MainHfp_MASK)
36982/*! @} */
36983
36984/*! @name DSI_MSYNC - Specifies the main display Sync Area register. */
36985/*! @{ */
36986#define MIPI_DSI_DSI_MSYNC_MainHsa_MASK (0xFFFFU)
36987#define MIPI_DSI_DSI_MSYNC_MainHsa_SHIFT (0U)
36988#define MIPI_DSI_DSI_MSYNC_MainHsa(x) \
36989 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MSYNC_MainHsa_SHIFT)) & MIPI_DSI_DSI_MSYNC_MainHsa_MASK)
36990#define MIPI_DSI_DSI_MSYNC_MainVsa_MASK (0xFFC00000U)
36991#define MIPI_DSI_DSI_MSYNC_MainVsa_SHIFT (22U)
36992#define MIPI_DSI_DSI_MSYNC_MainVsa(x) \
36993 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MSYNC_MainVsa_SHIFT)) & MIPI_DSI_DSI_MSYNC_MainVsa_MASK)
36994/*! @} */
36995
36996/*! @name DSI_SDRESOL - Specifies the sub display image resolution register. */
36997/*! @{ */
36998#define MIPI_DSI_DSI_SDRESOL_SubHResol_MASK (0x7FFU)
36999#define MIPI_DSI_DSI_SDRESOL_SubHResol_SHIFT (0U)
37000#define MIPI_DSI_DSI_SDRESOL_SubHResol(x) \
37001 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_SDRESOL_SubHResol_SHIFT)) & MIPI_DSI_DSI_SDRESOL_SubHResol_MASK)
37002#define MIPI_DSI_DSI_SDRESOL_SubVResol_MASK (0x7FF0000U)
37003#define MIPI_DSI_DSI_SDRESOL_SubVResol_SHIFT (16U)
37004#define MIPI_DSI_DSI_SDRESOL_SubVResol(x) \
37005 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_SDRESOL_SubVResol_SHIFT)) & MIPI_DSI_DSI_SDRESOL_SubVResol_MASK)
37006#define MIPI_DSI_DSI_SDRESOL_SubStandby_MASK (0x80000000U)
37007#define MIPI_DSI_DSI_SDRESOL_SubStandby_SHIFT (31U)
37008#define MIPI_DSI_DSI_SDRESOL_SubStandby(x) \
37009 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_SDRESOL_SubStandby_SHIFT)) & MIPI_DSI_DSI_SDRESOL_SubStandby_MASK)
37010/*! @} */
37011
37012/*! @name DSI_INTSRC - Specifies the interrupt source register. */
37013/*! @{ */
37014#define MIPI_DSI_DSI_INTSRC_ErrContentLP1_MASK (0x1U)
37015#define MIPI_DSI_DSI_INTSRC_ErrContentLP1_SHIFT (0U)
37016#define MIPI_DSI_DSI_INTSRC_ErrContentLP1(x) \
37017 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrContentLP1_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrContentLP1_MASK)
37018#define MIPI_DSI_DSI_INTSRC_ErrContentLP0_MASK (0x2U)
37019#define MIPI_DSI_DSI_INTSRC_ErrContentLP0_SHIFT (1U)
37020#define MIPI_DSI_DSI_INTSRC_ErrContentLP0(x) \
37021 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrContentLP0_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrContentLP0_MASK)
37022#define MIPI_DSI_DSI_INTSRC_ErrControl0_MASK (0x4U)
37023#define MIPI_DSI_DSI_INTSRC_ErrControl0_SHIFT (2U)
37024#define MIPI_DSI_DSI_INTSRC_ErrControl0(x) \
37025 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrControl0_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrControl0_MASK)
37026#define MIPI_DSI_DSI_INTSRC_ErrControl1_MASK (0x8U)
37027#define MIPI_DSI_DSI_INTSRC_ErrControl1_SHIFT (3U)
37028#define MIPI_DSI_DSI_INTSRC_ErrControl1(x) \
37029 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrControl1_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrControl1_MASK)
37030#define MIPI_DSI_DSI_INTSRC_ErrControl2_MASK (0x10U)
37031#define MIPI_DSI_DSI_INTSRC_ErrControl2_SHIFT (4U)
37032#define MIPI_DSI_DSI_INTSRC_ErrControl2(x) \
37033 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrControl2_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrControl2_MASK)
37034#define MIPI_DSI_DSI_INTSRC_ErrControl3_MASK (0x20U)
37035#define MIPI_DSI_DSI_INTSRC_ErrControl3_SHIFT (5U)
37036#define MIPI_DSI_DSI_INTSRC_ErrControl3(x) \
37037 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrControl3_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrControl3_MASK)
37038#define MIPI_DSI_DSI_INTSRC_ErrSync0_MASK (0x40U)
37039#define MIPI_DSI_DSI_INTSRC_ErrSync0_SHIFT (6U)
37040#define MIPI_DSI_DSI_INTSRC_ErrSync0(x) \
37041 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrSync0_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrSync0_MASK)
37042#define MIPI_DSI_DSI_INTSRC_ErrSync1_MASK (0x80U)
37043#define MIPI_DSI_DSI_INTSRC_ErrSync1_SHIFT (7U)
37044#define MIPI_DSI_DSI_INTSRC_ErrSync1(x) \
37045 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrSync1_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrSync1_MASK)
37046#define MIPI_DSI_DSI_INTSRC_ErrSync2_MASK (0x100U)
37047#define MIPI_DSI_DSI_INTSRC_ErrSync2_SHIFT (8U)
37048#define MIPI_DSI_DSI_INTSRC_ErrSync2(x) \
37049 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrSync2_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrSync2_MASK)
37050#define MIPI_DSI_DSI_INTSRC_ErrSync3_MASK (0x200U)
37051#define MIPI_DSI_DSI_INTSRC_ErrSync3_SHIFT (9U)
37052#define MIPI_DSI_DSI_INTSRC_ErrSync3(x) \
37053 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrSync3_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrSync3_MASK)
37054#define MIPI_DSI_DSI_INTSRC_ErrEsc0_MASK (0x400U)
37055#define MIPI_DSI_DSI_INTSRC_ErrEsc0_SHIFT (10U)
37056#define MIPI_DSI_DSI_INTSRC_ErrEsc0(x) \
37057 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrEsc0_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrEsc0_MASK)
37058#define MIPI_DSI_DSI_INTSRC_ErrEsc1_MASK (0x800U)
37059#define MIPI_DSI_DSI_INTSRC_ErrEsc1_SHIFT (11U)
37060#define MIPI_DSI_DSI_INTSRC_ErrEsc1(x) \
37061 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrEsc1_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrEsc1_MASK)
37062#define MIPI_DSI_DSI_INTSRC_ErrEsc2_MASK (0x1000U)
37063#define MIPI_DSI_DSI_INTSRC_ErrEsc2_SHIFT (12U)
37064#define MIPI_DSI_DSI_INTSRC_ErrEsc2(x) \
37065 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrEsc2_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrEsc2_MASK)
37066#define MIPI_DSI_DSI_INTSRC_ErrEsc3_MASK (0x2000U)
37067#define MIPI_DSI_DSI_INTSRC_ErrEsc3_SHIFT (13U)
37068#define MIPI_DSI_DSI_INTSRC_ErrEsc3(x) \
37069 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrEsc3_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrEsc3_MASK)
37070#define MIPI_DSI_DSI_INTSRC_ErrRxCRC_MASK (0x4000U)
37071#define MIPI_DSI_DSI_INTSRC_ErrRxCRC_SHIFT (14U)
37072#define MIPI_DSI_DSI_INTSRC_ErrRxCRC(x) \
37073 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrRxCRC_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrRxCRC_MASK)
37074#define MIPI_DSI_DSI_INTSRC_ErrRxECC_MASK (0x8000U)
37075#define MIPI_DSI_DSI_INTSRC_ErrRxECC_SHIFT (15U)
37076#define MIPI_DSI_DSI_INTSRC_ErrRxECC(x) \
37077 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_ErrRxECC_SHIFT)) & MIPI_DSI_DSI_INTSRC_ErrRxECC_MASK)
37078#define MIPI_DSI_DSI_INTSRC_RxAck_MASK (0x10000U)
37079#define MIPI_DSI_DSI_INTSRC_RxAck_SHIFT (16U)
37080#define MIPI_DSI_DSI_INTSRC_RxAck(x) \
37081 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_RxAck_SHIFT)) & MIPI_DSI_DSI_INTSRC_RxAck_MASK)
37082#define MIPI_DSI_DSI_INTSRC_RxTE_MASK (0x20000U)
37083#define MIPI_DSI_DSI_INTSRC_RxTE_SHIFT (17U)
37084#define MIPI_DSI_DSI_INTSRC_RxTE(x) \
37085 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_RxTE_SHIFT)) & MIPI_DSI_DSI_INTSRC_RxTE_MASK)
37086#define MIPI_DSI_DSI_INTSRC_RxDatDone_MASK (0x40000U)
37087#define MIPI_DSI_DSI_INTSRC_RxDatDone_SHIFT (18U)
37088#define MIPI_DSI_DSI_INTSRC_RxDatDone(x) \
37089 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_RxDatDone_SHIFT)) & MIPI_DSI_DSI_INTSRC_RxDatDone_MASK)
37090#define MIPI_DSI_DSI_INTSRC_TaTout_MASK (0x100000U)
37091#define MIPI_DSI_DSI_INTSRC_TaTout_SHIFT (20U)
37092#define MIPI_DSI_DSI_INTSRC_TaTout(x) \
37093 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_TaTout_SHIFT)) & MIPI_DSI_DSI_INTSRC_TaTout_MASK)
37094#define MIPI_DSI_DSI_INTSRC_LpdrTout_MASK (0x200000U)
37095#define MIPI_DSI_DSI_INTSRC_LpdrTout_SHIFT (21U)
37096#define MIPI_DSI_DSI_INTSRC_LpdrTout(x) \
37097 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_LpdrTout_SHIFT)) & MIPI_DSI_DSI_INTSRC_LpdrTout_MASK)
37098#define MIPI_DSI_DSI_INTSRC_FrameDone_MASK (0x1000000U)
37099#define MIPI_DSI_DSI_INTSRC_FrameDone_SHIFT (24U)
37100#define MIPI_DSI_DSI_INTSRC_FrameDone(x) \
37101 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_FrameDone_SHIFT)) & MIPI_DSI_DSI_INTSRC_FrameDone_MASK)
37102#define MIPI_DSI_DSI_INTSRC_BusTurnOver_MASK (0x2000000U)
37103#define MIPI_DSI_DSI_INTSRC_BusTurnOver_SHIFT (25U)
37104#define MIPI_DSI_DSI_INTSRC_BusTurnOver(x) \
37105 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_BusTurnOver_SHIFT)) & MIPI_DSI_DSI_INTSRC_BusTurnOver_MASK)
37106#define MIPI_DSI_DSI_INTSRC_SyncOverride_MASK (0x8000000U)
37107#define MIPI_DSI_DSI_INTSRC_SyncOverride_SHIFT (27U)
37108#define MIPI_DSI_DSI_INTSRC_SyncOverride(x) \
37109 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_SyncOverride_SHIFT)) & MIPI_DSI_DSI_INTSRC_SyncOverride_MASK)
37110#define MIPI_DSI_DSI_INTSRC_SFRPHFifoEmpty_MASK (0x10000000U)
37111#define MIPI_DSI_DSI_INTSRC_SFRPHFifoEmpty_SHIFT (28U)
37112#define MIPI_DSI_DSI_INTSRC_SFRPHFifoEmpty(x) \
37113 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_SFRPHFifoEmpty_SHIFT)) & \
37114 MIPI_DSI_DSI_INTSRC_SFRPHFifoEmpty_MASK)
37115#define MIPI_DSI_DSI_INTSRC_SFRPLFifoEmpty_MASK (0x20000000U)
37116#define MIPI_DSI_DSI_INTSRC_SFRPLFifoEmpty_SHIFT (29U)
37117#define MIPI_DSI_DSI_INTSRC_SFRPLFifoEmpty(x) \
37118 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_SFRPLFifoEmpty_SHIFT)) & \
37119 MIPI_DSI_DSI_INTSRC_SFRPLFifoEmpty_MASK)
37120#define MIPI_DSI_DSI_INTSRC_SwRstRelease_MASK (0x40000000U)
37121#define MIPI_DSI_DSI_INTSRC_SwRstRelease_SHIFT (30U)
37122#define MIPI_DSI_DSI_INTSRC_SwRstRelease(x) \
37123 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_SwRstRelease_SHIFT)) & MIPI_DSI_DSI_INTSRC_SwRstRelease_MASK)
37124#define MIPI_DSI_DSI_INTSRC_PllStable_MASK (0x80000000U)
37125#define MIPI_DSI_DSI_INTSRC_PllStable_SHIFT (31U)
37126#define MIPI_DSI_DSI_INTSRC_PllStable(x) \
37127 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTSRC_PllStable_SHIFT)) & MIPI_DSI_DSI_INTSRC_PllStable_MASK)
37128/*! @} */
37129
37130/*! @name DSI_INTMSK - Specifies the interrupt mask register. */
37131/*! @{ */
37132#define MIPI_DSI_DSI_INTMSK_MskContentLP1_MASK (0x1U)
37133#define MIPI_DSI_DSI_INTMSK_MskContentLP1_SHIFT (0U)
37134#define MIPI_DSI_DSI_INTMSK_MskContentLP1(x) \
37135 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskContentLP1_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskContentLP1_MASK)
37136#define MIPI_DSI_DSI_INTMSK_MskContentLP0_MASK (0x2U)
37137#define MIPI_DSI_DSI_INTMSK_MskContentLP0_SHIFT (1U)
37138#define MIPI_DSI_DSI_INTMSK_MskContentLP0(x) \
37139 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskContentLP0_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskContentLP0_MASK)
37140#define MIPI_DSI_DSI_INTMSK_MskControl0_MASK (0x4U)
37141#define MIPI_DSI_DSI_INTMSK_MskControl0_SHIFT (2U)
37142#define MIPI_DSI_DSI_INTMSK_MskControl0(x) \
37143 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskControl0_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskControl0_MASK)
37144#define MIPI_DSI_DSI_INTMSK_MskControl1_MASK (0x8U)
37145#define MIPI_DSI_DSI_INTMSK_MskControl1_SHIFT (3U)
37146#define MIPI_DSI_DSI_INTMSK_MskControl1(x) \
37147 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskControl1_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskControl1_MASK)
37148#define MIPI_DSI_DSI_INTMSK_MskControl2_MASK (0x10U)
37149#define MIPI_DSI_DSI_INTMSK_MskControl2_SHIFT (4U)
37150#define MIPI_DSI_DSI_INTMSK_MskControl2(x) \
37151 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskControl2_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskControl2_MASK)
37152#define MIPI_DSI_DSI_INTMSK_MskControl3_MASK (0x20U)
37153#define MIPI_DSI_DSI_INTMSK_MskControl3_SHIFT (5U)
37154#define MIPI_DSI_DSI_INTMSK_MskControl3(x) \
37155 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskControl3_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskControl3_MASK)
37156#define MIPI_DSI_DSI_INTMSK_MskSync0_MASK (0x40U)
37157#define MIPI_DSI_DSI_INTMSK_MskSync0_SHIFT (6U)
37158#define MIPI_DSI_DSI_INTMSK_MskSync0(x) \
37159 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskSync0_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskSync0_MASK)
37160#define MIPI_DSI_DSI_INTMSK_MskSync1_MASK (0x80U)
37161#define MIPI_DSI_DSI_INTMSK_MskSync1_SHIFT (7U)
37162#define MIPI_DSI_DSI_INTMSK_MskSync1(x) \
37163 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskSync1_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskSync1_MASK)
37164#define MIPI_DSI_DSI_INTMSK_MskSync2_MASK (0x100U)
37165#define MIPI_DSI_DSI_INTMSK_MskSync2_SHIFT (8U)
37166#define MIPI_DSI_DSI_INTMSK_MskSync2(x) \
37167 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskSync2_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskSync2_MASK)
37168#define MIPI_DSI_DSI_INTMSK_MskSync3_MASK (0x200U)
37169#define MIPI_DSI_DSI_INTMSK_MskSync3_SHIFT (9U)
37170#define MIPI_DSI_DSI_INTMSK_MskSync3(x) \
37171 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskSync3_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskSync3_MASK)
37172#define MIPI_DSI_DSI_INTMSK_MskEsc0_MASK (0x400U)
37173#define MIPI_DSI_DSI_INTMSK_MskEsc0_SHIFT (10U)
37174#define MIPI_DSI_DSI_INTMSK_MskEsc0(x) \
37175 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskEsc0_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskEsc0_MASK)
37176#define MIPI_DSI_DSI_INTMSK_MskEsc1_MASK (0x800U)
37177#define MIPI_DSI_DSI_INTMSK_MskEsc1_SHIFT (11U)
37178#define MIPI_DSI_DSI_INTMSK_MskEsc1(x) \
37179 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskEsc1_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskEsc1_MASK)
37180#define MIPI_DSI_DSI_INTMSK_MskEsc2_MASK (0x1000U)
37181#define MIPI_DSI_DSI_INTMSK_MskEsc2_SHIFT (12U)
37182#define MIPI_DSI_DSI_INTMSK_MskEsc2(x) \
37183 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskEsc2_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskEsc2_MASK)
37184#define MIPI_DSI_DSI_INTMSK_MskEsc3_MASK (0x2000U)
37185#define MIPI_DSI_DSI_INTMSK_MskEsc3_SHIFT (13U)
37186#define MIPI_DSI_DSI_INTMSK_MskEsc3(x) \
37187 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskEsc3_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskEsc3_MASK)
37188#define MIPI_DSI_DSI_INTMSK_MskRxCRC_MASK (0x4000U)
37189#define MIPI_DSI_DSI_INTMSK_MskRxCRC_SHIFT (14U)
37190#define MIPI_DSI_DSI_INTMSK_MskRxCRC(x) \
37191 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskRxCRC_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskRxCRC_MASK)
37192#define MIPI_DSI_DSI_INTMSK_MskRxECC_MASK (0x8000U)
37193#define MIPI_DSI_DSI_INTMSK_MskRxECC_SHIFT (15U)
37194#define MIPI_DSI_DSI_INTMSK_MskRxECC(x) \
37195 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskRxECC_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskRxECC_MASK)
37196#define MIPI_DSI_DSI_INTMSK_MskRxAck_MASK (0x10000U)
37197#define MIPI_DSI_DSI_INTMSK_MskRxAck_SHIFT (16U)
37198#define MIPI_DSI_DSI_INTMSK_MskRxAck(x) \
37199 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskRxAck_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskRxAck_MASK)
37200#define MIPI_DSI_DSI_INTMSK_MskRxTE_MASK (0x20000U)
37201#define MIPI_DSI_DSI_INTMSK_MskRxTE_SHIFT (17U)
37202#define MIPI_DSI_DSI_INTMSK_MskRxTE(x) \
37203 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskRxTE_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskRxTE_MASK)
37204#define MIPI_DSI_DSI_INTMSK_MskRxDatDone_MASK (0x40000U)
37205#define MIPI_DSI_DSI_INTMSK_MskRxDatDone_SHIFT (18U)
37206#define MIPI_DSI_DSI_INTMSK_MskRxDatDone(x) \
37207 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskRxDatDone_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskRxDatDone_MASK)
37208#define MIPI_DSI_DSI_INTMSK_MskTaTout_MASK (0x100000U)
37209#define MIPI_DSI_DSI_INTMSK_MskTaTout_SHIFT (20U)
37210#define MIPI_DSI_DSI_INTMSK_MskTaTout(x) \
37211 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskTaTout_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskTaTout_MASK)
37212#define MIPI_DSI_DSI_INTMSK_MskLpdrTout_MASK (0x200000U)
37213#define MIPI_DSI_DSI_INTMSK_MskLpdrTout_SHIFT (21U)
37214#define MIPI_DSI_DSI_INTMSK_MskLpdrTout(x) \
37215 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskLpdrTout_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskLpdrTout_MASK)
37216#define MIPI_DSI_DSI_INTMSK_MskFrameDone_MASK (0x1000000U)
37217#define MIPI_DSI_DSI_INTMSK_MskFrameDone_SHIFT (24U)
37218#define MIPI_DSI_DSI_INTMSK_MskFrameDone(x) \
37219 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskFrameDone_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskFrameDone_MASK)
37220#define MIPI_DSI_DSI_INTMSK_MskBusTurnOver_MASK (0x2000000U)
37221#define MIPI_DSI_DSI_INTMSK_MskBusTurnOver_SHIFT (25U)
37222#define MIPI_DSI_DSI_INTMSK_MskBusTurnOver(x) \
37223 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskBusTurnOver_SHIFT)) & \
37224 MIPI_DSI_DSI_INTMSK_MskBusTurnOver_MASK)
37225#define MIPI_DSI_DSI_INTMSK_MskSyncOverride_MASK (0x8000000U)
37226#define MIPI_DSI_DSI_INTMSK_MskSyncOverride_SHIFT (27U)
37227#define MIPI_DSI_DSI_INTMSK_MskSyncOverride(x) \
37228 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskSyncOverride_SHIFT)) & \
37229 MIPI_DSI_DSI_INTMSK_MskSyncOverride_MASK)
37230#define MIPI_DSI_DSI_INTMSK_MskSFRPHFifoEmpty_MASK (0x10000000U)
37231#define MIPI_DSI_DSI_INTMSK_MskSFRPHFifoEmpty_SHIFT (28U)
37232#define MIPI_DSI_DSI_INTMSK_MskSFRPHFifoEmpty(x) \
37233 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskSFRPHFifoEmpty_SHIFT)) & \
37234 MIPI_DSI_DSI_INTMSK_MskSFRPHFifoEmpty_MASK)
37235#define MIPI_DSI_DSI_INTMSK_MskSFRPLFifoEmpty_MASK (0x20000000U)
37236#define MIPI_DSI_DSI_INTMSK_MskSFRPLFifoEmpty_SHIFT (29U)
37237#define MIPI_DSI_DSI_INTMSK_MskSFRPLFifoEmpty(x) \
37238 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskSFRPLFifoEmpty_SHIFT)) & \
37239 MIPI_DSI_DSI_INTMSK_MskSFRPLFifoEmpty_MASK)
37240#define MIPI_DSI_DSI_INTMSK_MskSwRstRelease_MASK (0x40000000U)
37241#define MIPI_DSI_DSI_INTMSK_MskSwRstRelease_SHIFT (30U)
37242#define MIPI_DSI_DSI_INTMSK_MskSwRstRelease(x) \
37243 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskSwRstRelease_SHIFT)) & \
37244 MIPI_DSI_DSI_INTMSK_MskSwRstRelease_MASK)
37245#define MIPI_DSI_DSI_INTMSK_MskPllStable_MASK (0x80000000U)
37246#define MIPI_DSI_DSI_INTMSK_MskPllStable_SHIFT (31U)
37247#define MIPI_DSI_DSI_INTMSK_MskPllStable(x) \
37248 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_INTMSK_MskPllStable_SHIFT)) & MIPI_DSI_DSI_INTMSK_MskPllStable_MASK)
37249/*! @} */
37250
37251/*! @name DSI_PKTHDR - Specifies the packet header FIFO register. */
37252/*! @{ */
37253#define MIPI_DSI_DSI_PKTHDR_PacketHeader_MASK (0xFFFFFFU)
37254#define MIPI_DSI_DSI_PKTHDR_PacketHeader_SHIFT (0U)
37255#define MIPI_DSI_DSI_PKTHDR_PacketHeader(x) \
37256 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PKTHDR_PacketHeader_SHIFT)) & MIPI_DSI_DSI_PKTHDR_PacketHeader_MASK)
37257/*! @} */
37258
37259/*! @name DSI_PAYLOAD - Specifies the payload FIFO register. */
37260/*! @{ */
37261#define MIPI_DSI_DSI_PAYLOAD_Payload_MASK (0xFFFFFFFFU)
37262#define MIPI_DSI_DSI_PAYLOAD_Payload_SHIFT (0U)
37263#define MIPI_DSI_DSI_PAYLOAD_Payload(x) \
37264 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PAYLOAD_Payload_SHIFT)) & MIPI_DSI_DSI_PAYLOAD_Payload_MASK)
37265/*! @} */
37266
37267/*! @name DSI_RXFIFO - Specifies the read FIFO register. */
37268/*! @{ */
37269#define MIPI_DSI_DSI_RXFIFO_RxDat_MASK (0xFFFFFFFFU)
37270#define MIPI_DSI_DSI_RXFIFO_RxDat_SHIFT (0U)
37271#define MIPI_DSI_DSI_RXFIFO_RxDat(x) \
37272 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_RXFIFO_RxDat_SHIFT)) & MIPI_DSI_DSI_RXFIFO_RxDat_MASK)
37273/*! @} */
37274
37275/*! @name DSI_FIFOTHLD - Specifies the FIFO threshold level register. */
37276/*! @{ */
37277#define MIPI_DSI_DSI_FIFOTHLD_WfullLevelSfr_MASK (0x1FFU)
37278#define MIPI_DSI_DSI_FIFOTHLD_WfullLevelSfr_SHIFT (0U)
37279#define MIPI_DSI_DSI_FIFOTHLD_WfullLevelSfr(x) \
37280 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOTHLD_WfullLevelSfr_SHIFT)) & \
37281 MIPI_DSI_DSI_FIFOTHLD_WfullLevelSfr_MASK)
37282/*! @} */
37283
37284/*! @name DSI_FIFOCTRL - Specifies the FIFO status and control register. */
37285/*! @{ */
37286#define MIPI_DSI_DSI_FIFOCTRL_nInitMain_MASK (0x1U)
37287#define MIPI_DSI_DSI_FIFOCTRL_nInitMain_SHIFT (0U)
37288#define MIPI_DSI_DSI_FIFOCTRL_nInitMain(x) \
37289 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_nInitMain_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_nInitMain_MASK)
37290#define MIPI_DSI_DSI_FIFOCTRL_nInitSub_MASK (0x2U)
37291#define MIPI_DSI_DSI_FIFOCTRL_nInitSub_SHIFT (1U)
37292#define MIPI_DSI_DSI_FIFOCTRL_nInitSub(x) \
37293 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_nInitSub_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_nInitSub_MASK)
37294#define MIPI_DSI_DSI_FIFOCTRL_nInitI80_MASK (0x4U)
37295#define MIPI_DSI_DSI_FIFOCTRL_nInitI80_SHIFT (2U)
37296#define MIPI_DSI_DSI_FIFOCTRL_nInitI80(x) \
37297 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_nInitI80_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_nInitI80_MASK)
37298#define MIPI_DSI_DSI_FIFOCTRL_nInitSfr_MASK (0x8U)
37299#define MIPI_DSI_DSI_FIFOCTRL_nInitSfr_SHIFT (3U)
37300#define MIPI_DSI_DSI_FIFOCTRL_nInitSfr(x) \
37301 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_nInitSfr_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_nInitSfr_MASK)
37302#define MIPI_DSI_DSI_FIFOCTRL_nInitRx_MASK (0x10U)
37303#define MIPI_DSI_DSI_FIFOCTRL_nInitRx_SHIFT (4U)
37304#define MIPI_DSI_DSI_FIFOCTRL_nInitRx(x) \
37305 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_nInitRx_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_nInitRx_MASK)
37306#define MIPI_DSI_DSI_FIFOCTRL_EmptyLMain_MASK (0x100U)
37307#define MIPI_DSI_DSI_FIFOCTRL_EmptyLMain_SHIFT (8U)
37308#define MIPI_DSI_DSI_FIFOCTRL_EmptyLMain(x) \
37309 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EmptyLMain_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EmptyLMain_MASK)
37310#define MIPI_DSI_DSI_FIFOCTRL_FullLMain_MASK (0x200U)
37311#define MIPI_DSI_DSI_FIFOCTRL_FullLMain_SHIFT (9U)
37312#define MIPI_DSI_DSI_FIFOCTRL_FullLMain(x) \
37313 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FullLMain_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FullLMain_MASK)
37314#define MIPI_DSI_DSI_FIFOCTRL_EmptyHMain_MASK (0x400U)
37315#define MIPI_DSI_DSI_FIFOCTRL_EmptyHMain_SHIFT (10U)
37316#define MIPI_DSI_DSI_FIFOCTRL_EmptyHMain(x) \
37317 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EmptyHMain_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EmptyHMain_MASK)
37318#define MIPI_DSI_DSI_FIFOCTRL_FullHMain_MASK (0x800U)
37319#define MIPI_DSI_DSI_FIFOCTRL_FullHMain_SHIFT (11U)
37320#define MIPI_DSI_DSI_FIFOCTRL_FullHMain(x) \
37321 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FullHMain_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FullHMain_MASK)
37322#define MIPI_DSI_DSI_FIFOCTRL_EmptyLSub_MASK (0x1000U)
37323#define MIPI_DSI_DSI_FIFOCTRL_EmptyLSub_SHIFT (12U)
37324#define MIPI_DSI_DSI_FIFOCTRL_EmptyLSub(x) \
37325 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EmptyLSub_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EmptyLSub_MASK)
37326#define MIPI_DSI_DSI_FIFOCTRL_FullLSub_MASK (0x2000U)
37327#define MIPI_DSI_DSI_FIFOCTRL_FullLSub_SHIFT (13U)
37328#define MIPI_DSI_DSI_FIFOCTRL_FullLSub(x) \
37329 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FullLSub_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FullLSub_MASK)
37330#define MIPI_DSI_DSI_FIFOCTRL_EmptyHSub_MASK (0x4000U)
37331#define MIPI_DSI_DSI_FIFOCTRL_EmptyHSub_SHIFT (14U)
37332#define MIPI_DSI_DSI_FIFOCTRL_EmptyHSub(x) \
37333 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EmptyHSub_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EmptyHSub_MASK)
37334#define MIPI_DSI_DSI_FIFOCTRL_FullHSub_MASK (0x8000U)
37335#define MIPI_DSI_DSI_FIFOCTRL_FullHSub_SHIFT (15U)
37336#define MIPI_DSI_DSI_FIFOCTRL_FullHSub(x) \
37337 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FullHSub_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FullHSub_MASK)
37338#define MIPI_DSI_DSI_FIFOCTRL_EmptyLI80_MASK (0x10000U)
37339#define MIPI_DSI_DSI_FIFOCTRL_EmptyLI80_SHIFT (16U)
37340#define MIPI_DSI_DSI_FIFOCTRL_EmptyLI80(x) \
37341 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EmptyLI80_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EmptyLI80_MASK)
37342#define MIPI_DSI_DSI_FIFOCTRL_FullLI80_MASK (0x20000U)
37343#define MIPI_DSI_DSI_FIFOCTRL_FullLI80_SHIFT (17U)
37344#define MIPI_DSI_DSI_FIFOCTRL_FullLI80(x) \
37345 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FullLI80_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FullLI80_MASK)
37346#define MIPI_DSI_DSI_FIFOCTRL_EmptyHI80_MASK (0x40000U)
37347#define MIPI_DSI_DSI_FIFOCTRL_EmptyHI80_SHIFT (18U)
37348#define MIPI_DSI_DSI_FIFOCTRL_EmptyHI80(x) \
37349 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EmptyHI80_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EmptyHI80_MASK)
37350#define MIPI_DSI_DSI_FIFOCTRL_FullHI80_MASK (0x80000U)
37351#define MIPI_DSI_DSI_FIFOCTRL_FullHI80_SHIFT (19U)
37352#define MIPI_DSI_DSI_FIFOCTRL_FullHI80(x) \
37353 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FullHI80_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FullHI80_MASK)
37354#define MIPI_DSI_DSI_FIFOCTRL_EmptyLSfr_MASK (0x100000U)
37355#define MIPI_DSI_DSI_FIFOCTRL_EmptyLSfr_SHIFT (20U)
37356#define MIPI_DSI_DSI_FIFOCTRL_EmptyLSfr(x) \
37357 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EmptyLSfr_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EmptyLSfr_MASK)
37358#define MIPI_DSI_DSI_FIFOCTRL_FullLSfr_MASK (0x200000U)
37359#define MIPI_DSI_DSI_FIFOCTRL_FullLSfr_SHIFT (21U)
37360#define MIPI_DSI_DSI_FIFOCTRL_FullLSfr(x) \
37361 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FullLSfr_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FullLSfr_MASK)
37362#define MIPI_DSI_DSI_FIFOCTRL_EmptyHSfr_MASK (0x400000U)
37363#define MIPI_DSI_DSI_FIFOCTRL_EmptyHSfr_SHIFT (22U)
37364#define MIPI_DSI_DSI_FIFOCTRL_EmptyHSfr(x) \
37365 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EmptyHSfr_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EmptyHSfr_MASK)
37366#define MIPI_DSI_DSI_FIFOCTRL_FullHSfr_MASK (0x800000U)
37367#define MIPI_DSI_DSI_FIFOCTRL_FullHSfr_SHIFT (23U)
37368#define MIPI_DSI_DSI_FIFOCTRL_FullHSfr(x) \
37369 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FullHSfr_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FullHSfr_MASK)
37370#define MIPI_DSI_DSI_FIFOCTRL_EmptyRx_MASK (0x1000000U)
37371#define MIPI_DSI_DSI_FIFOCTRL_EmptyRx_SHIFT (24U)
37372#define MIPI_DSI_DSI_FIFOCTRL_EmptyRx(x) \
37373 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_EmptyRx_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_EmptyRx_MASK)
37374#define MIPI_DSI_DSI_FIFOCTRL_FullRx_MASK (0x2000000U)
37375#define MIPI_DSI_DSI_FIFOCTRL_FullRx_SHIFT (25U)
37376#define MIPI_DSI_DSI_FIFOCTRL_FullRx(x) \
37377 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_FIFOCTRL_FullRx_SHIFT)) & MIPI_DSI_DSI_FIFOCTRL_FullRx_MASK)
37378/*! @} */
37379
37380/*! @name DSI_MEMACCHR - Specifies the FIFO memory AC characteristic register. */
37381/*! @{ */
37382#define MIPI_DSI_DSI_MEMACCHR_EMAA_MD_MASK (0x7U)
37383#define MIPI_DSI_DSI_MEMACCHR_EMAA_MD_SHIFT (0U)
37384#define MIPI_DSI_DSI_MEMACCHR_EMAA_MD(x) \
37385 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_EMAA_MD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_EMAA_MD_MASK)
37386#define MIPI_DSI_DSI_MEMACCHR_EMAB_MD_MASK (0x38U)
37387#define MIPI_DSI_DSI_MEMACCHR_EMAB_MD_SHIFT (3U)
37388#define MIPI_DSI_DSI_MEMACCHR_EMAB_MD(x) \
37389 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_EMAB_MD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_EMAB_MD_MASK)
37390#define MIPI_DSI_DSI_MEMACCHR_RETN_MD_MASK (0x40U)
37391#define MIPI_DSI_DSI_MEMACCHR_RETN_MD_SHIFT (6U)
37392#define MIPI_DSI_DSI_MEMACCHR_RETN_MD(x) \
37393 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_RETN_MD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_RETN_MD_MASK)
37394#define MIPI_DSI_DSI_MEMACCHR_PGEN_MD_MASK (0x80U)
37395#define MIPI_DSI_DSI_MEMACCHR_PGEN_MD_SHIFT (7U)
37396#define MIPI_DSI_DSI_MEMACCHR_PGEN_MD(x) \
37397 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_PGEN_MD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_PGEN_MD_MASK)
37398#define MIPI_DSI_DSI_MEMACCHR_EMAA_SD_MASK (0x700U)
37399#define MIPI_DSI_DSI_MEMACCHR_EMAA_SD_SHIFT (8U)
37400#define MIPI_DSI_DSI_MEMACCHR_EMAA_SD(x) \
37401 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_EMAA_SD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_EMAA_SD_MASK)
37402#define MIPI_DSI_DSI_MEMACCHR_EMAB_SD_MASK (0x3800U)
37403#define MIPI_DSI_DSI_MEMACCHR_EMAB_SD_SHIFT (11U)
37404#define MIPI_DSI_DSI_MEMACCHR_EMAB_SD(x) \
37405 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_EMAB_SD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_EMAB_SD_MASK)
37406#define MIPI_DSI_DSI_MEMACCHR_RETN_SD_MASK (0x4000U)
37407#define MIPI_DSI_DSI_MEMACCHR_RETN_SD_SHIFT (14U)
37408#define MIPI_DSI_DSI_MEMACCHR_RETN_SD(x) \
37409 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_RETN_SD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_RETN_SD_MASK)
37410#define MIPI_DSI_DSI_MEMACCHR_PGEN_SD_MASK (0x8000U)
37411#define MIPI_DSI_DSI_MEMACCHR_PGEN_SD_SHIFT (15U)
37412#define MIPI_DSI_DSI_MEMACCHR_PGEN_SD(x) \
37413 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MEMACCHR_PGEN_SD_SHIFT)) & MIPI_DSI_DSI_MEMACCHR_PGEN_SD_MASK)
37414/*! @} */
37415
37416/*! @name DSI_MULTI_PKT - Specifies the Multi Packet, Packet Go register. */
37417/*! @{ */
37418#define MIPI_DSI_DSI_MULTI_PKT_Multi_PKT_Cnt_Ref_MASK (0xFFFFU)
37419#define MIPI_DSI_DSI_MULTI_PKT_Multi_PKT_Cnt_Ref_SHIFT (0U)
37420#define MIPI_DSI_DSI_MULTI_PKT_Multi_PKT_Cnt_Ref(x) \
37421 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MULTI_PKT_Multi_PKT_Cnt_Ref_SHIFT)) & \
37422 MIPI_DSI_DSI_MULTI_PKT_Multi_PKT_Cnt_Ref_MASK)
37423#define MIPI_DSI_DSI_MULTI_PKT_PKT_Send_Cnt_Ref_MASK (0xFFF0000U)
37424#define MIPI_DSI_DSI_MULTI_PKT_PKT_Send_Cnt_Ref_SHIFT (16U)
37425#define MIPI_DSI_DSI_MULTI_PKT_PKT_Send_Cnt_Ref(x) \
37426 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MULTI_PKT_PKT_Send_Cnt_Ref_SHIFT)) & \
37427 MIPI_DSI_DSI_MULTI_PKT_PKT_Send_Cnt_Ref_MASK)
37428#define MIPI_DSI_DSI_MULTI_PKT_PKT_Go_Rdy_MASK (0x10000000U)
37429#define MIPI_DSI_DSI_MULTI_PKT_PKT_Go_Rdy_SHIFT (28U)
37430#define MIPI_DSI_DSI_MULTI_PKT_PKT_Go_Rdy(x) \
37431 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MULTI_PKT_PKT_Go_Rdy_SHIFT)) & MIPI_DSI_DSI_MULTI_PKT_PKT_Go_Rdy_MASK)
37432#define MIPI_DSI_DSI_MULTI_PKT_PKT_Go_EN_MASK (0x20000000U)
37433#define MIPI_DSI_DSI_MULTI_PKT_PKT_Go_EN_SHIFT (29U)
37434#define MIPI_DSI_DSI_MULTI_PKT_PKT_Go_EN(x) \
37435 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MULTI_PKT_PKT_Go_EN_SHIFT)) & MIPI_DSI_DSI_MULTI_PKT_PKT_Go_EN_MASK)
37436#define MIPI_DSI_DSI_MULTI_PKT_Multi_PKT_EN_MASK (0x40000000U)
37437#define MIPI_DSI_DSI_MULTI_PKT_Multi_PKT_EN_SHIFT (30U)
37438#define MIPI_DSI_DSI_MULTI_PKT_Multi_PKT_EN(x) \
37439 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_MULTI_PKT_Multi_PKT_EN_SHIFT)) & \
37440 MIPI_DSI_DSI_MULTI_PKT_Multi_PKT_EN_MASK)
37441/*! @} */
37442
37443/*! @name DSI_PLLCTRL_1G - Specifies the 1Gbps D-PHY PLL control register. */
37444/*! @{ */
37445#define MIPI_DSI_DSI_PLLCTRL_1G_PRPRCtlClk_MASK (0x7U)
37446#define MIPI_DSI_DSI_PLLCTRL_1G_PRPRCtlClk_SHIFT (0U)
37447#define MIPI_DSI_DSI_PLLCTRL_1G_PRPRCtlClk(x) \
37448 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_1G_PRPRCtlClk_SHIFT)) & \
37449 MIPI_DSI_DSI_PLLCTRL_1G_PRPRCtlClk_MASK)
37450#define MIPI_DSI_DSI_PLLCTRL_1G_PREPRCtl_MASK (0x70U)
37451#define MIPI_DSI_DSI_PLLCTRL_1G_PREPRCtl_SHIFT (4U)
37452#define MIPI_DSI_DSI_PLLCTRL_1G_PREPRCtl(x) \
37453 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_1G_PREPRCtl_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_1G_PREPRCtl_MASK)
37454#define MIPI_DSI_DSI_PLLCTRL_1G_Freq_Band_MASK (0xF00U)
37455#define MIPI_DSI_DSI_PLLCTRL_1G_Freq_Band_SHIFT (8U)
37456#define MIPI_DSI_DSI_PLLCTRL_1G_Freq_Band(x) \
37457 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_1G_Freq_Band_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_1G_Freq_Band_MASK)
37458#define MIPI_DSI_DSI_PLLCTRL_1G_HSzeroCtl_MASK (0xF000U)
37459#define MIPI_DSI_DSI_PLLCTRL_1G_HSzeroCtl_SHIFT (12U)
37460#define MIPI_DSI_DSI_PLLCTRL_1G_HSzeroCtl(x) \
37461 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_1G_HSzeroCtl_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_1G_HSzeroCtl_MASK)
37462/*! @} */
37463
37464/*! @name DSI_PLLCTRL - Specifies the PLL control register. */
37465/*! @{ */
37466#define MIPI_DSI_DSI_PLLCTRL_PMS_MASK (0xFFFFEU)
37467#define MIPI_DSI_DSI_PLLCTRL_PMS_SHIFT (1U)
37468#define MIPI_DSI_DSI_PLLCTRL_PMS(x) \
37469 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_PMS_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_PMS_MASK)
37470#define MIPI_DSI_DSI_PLLCTRL_PllEn_MASK (0x800000U)
37471#define MIPI_DSI_DSI_PLLCTRL_PllEn_SHIFT (23U)
37472#define MIPI_DSI_DSI_PLLCTRL_PllEn(x) \
37473 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_PllEn_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_PllEn_MASK)
37474#define MIPI_DSI_DSI_PLLCTRL_DpDnSwap_DAT_MASK (0x1000000U)
37475#define MIPI_DSI_DSI_PLLCTRL_DpDnSwap_DAT_SHIFT (24U)
37476#define MIPI_DSI_DSI_PLLCTRL_DpDnSwap_DAT(x) \
37477 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_DpDnSwap_DAT_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_DpDnSwap_DAT_MASK)
37478#define MIPI_DSI_DSI_PLLCTRL_DpDnSwap_CLK_MASK (0x2000000U)
37479#define MIPI_DSI_DSI_PLLCTRL_DpDnSwap_CLK_SHIFT (25U)
37480#define MIPI_DSI_DSI_PLLCTRL_DpDnSwap_CLK(x) \
37481 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL_DpDnSwap_CLK_SHIFT)) & MIPI_DSI_DSI_PLLCTRL_DpDnSwap_CLK_MASK)
37482/*! @} */
37483
37484/*! @name DSI_PLLCTRL1 - Specifies the PLL control register 1. */
37485/*! @{ */
37486#define MIPI_DSI_DSI_PLLCTRL1_M_PLLCTL0_MASK (0xFFFFFFFFU)
37487#define MIPI_DSI_DSI_PLLCTRL1_M_PLLCTL0_SHIFT (0U)
37488#define MIPI_DSI_DSI_PLLCTRL1_M_PLLCTL0(x) \
37489 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL1_M_PLLCTL0_SHIFT)) & MIPI_DSI_DSI_PLLCTRL1_M_PLLCTL0_MASK)
37490/*! @} */
37491
37492/*! @name DSI_PLLCTRL2 - Specifies the PLL control register 2. */
37493/*! @{ */
37494#define MIPI_DSI_DSI_PLLCTRL2_M_PLLCTL1_MASK (0xFFU)
37495#define MIPI_DSI_DSI_PLLCTRL2_M_PLLCTL1_SHIFT (0U)
37496#define MIPI_DSI_DSI_PLLCTRL2_M_PLLCTL1(x) \
37497 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLCTRL2_M_PLLCTL1_SHIFT)) & MIPI_DSI_DSI_PLLCTRL2_M_PLLCTL1_MASK)
37498/*! @} */
37499
37500/*! @name DSI_PLLTMR - Specifies the PLL timer register. */
37501/*! @{ */
37502#define MIPI_DSI_DSI_PLLTMR_PllTimer_MASK (0xFFFFFFFFU)
37503#define MIPI_DSI_DSI_PLLTMR_PllTimer_SHIFT (0U)
37504#define MIPI_DSI_DSI_PLLTMR_PllTimer(x) \
37505 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PLLTMR_PllTimer_SHIFT)) & MIPI_DSI_DSI_PLLTMR_PllTimer_MASK)
37506/*! @} */
37507
37508/*! @name DSI_PHYCTRL_B1 - Specifies the D-PHY control register 1. */
37509/*! @{ */
37510#define MIPI_DSI_DSI_PHYCTRL_B1_B_DPHYCTL0_MASK (0xFFFFFFFFU)
37511#define MIPI_DSI_DSI_PHYCTRL_B1_B_DPHYCTL0_SHIFT (0U)
37512#define MIPI_DSI_DSI_PHYCTRL_B1_B_DPHYCTL0(x) \
37513 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYCTRL_B1_B_DPHYCTL0_SHIFT)) & \
37514 MIPI_DSI_DSI_PHYCTRL_B1_B_DPHYCTL0_MASK)
37515/*! @} */
37516
37517/*! @name DSI_PHYCTRL_B2 - Specifies the D-PHY control register 2. */
37518/*! @{ */
37519#define MIPI_DSI_DSI_PHYCTRL_B2_B_DPHYCTL1_MASK (0xFFFFFFFFU)
37520#define MIPI_DSI_DSI_PHYCTRL_B2_B_DPHYCTL1_SHIFT (0U)
37521#define MIPI_DSI_DSI_PHYCTRL_B2_B_DPHYCTL1(x) \
37522 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYCTRL_B2_B_DPHYCTL1_SHIFT)) & \
37523 MIPI_DSI_DSI_PHYCTRL_B2_B_DPHYCTL1_MASK)
37524/*! @} */
37525
37526/*! @name DSI_PHYCTRL_M1 - Specifies the D-PHY control register 1. */
37527/*! @{ */
37528#define MIPI_DSI_DSI_PHYCTRL_M1_M_DPHYCTL0_MASK (0xFFFFFFFFU)
37529#define MIPI_DSI_DSI_PHYCTRL_M1_M_DPHYCTL0_SHIFT (0U)
37530#define MIPI_DSI_DSI_PHYCTRL_M1_M_DPHYCTL0(x) \
37531 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYCTRL_M1_M_DPHYCTL0_SHIFT)) & \
37532 MIPI_DSI_DSI_PHYCTRL_M1_M_DPHYCTL0_MASK)
37533/*! @} */
37534
37535/*! @name DSI_PHYCTRL_M2 - Specifies the D-PHY control register 2. */
37536/*! @{ */
37537#define MIPI_DSI_DSI_PHYCTRL_M2_M_DPHYCTL1_MASK (0xFFFFFFFFU)
37538#define MIPI_DSI_DSI_PHYCTRL_M2_M_DPHYCTL1_SHIFT (0U)
37539#define MIPI_DSI_DSI_PHYCTRL_M2_M_DPHYCTL1(x) \
37540 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYCTRL_M2_M_DPHYCTL1_SHIFT)) & \
37541 MIPI_DSI_DSI_PHYCTRL_M2_M_DPHYCTL1_MASK)
37542/*! @} */
37543
37544/*! @name DSI_PHYTIMING - Specifies the D-PHY timing register. */
37545/*! @{ */
37546#define MIPI_DSI_DSI_PHYTIMING_M_THSEXITCTL_MASK (0xFFU)
37547#define MIPI_DSI_DSI_PHYTIMING_M_THSEXITCTL_SHIFT (0U)
37548#define MIPI_DSI_DSI_PHYTIMING_M_THSEXITCTL(x) \
37549 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING_M_THSEXITCTL_SHIFT)) & \
37550 MIPI_DSI_DSI_PHYTIMING_M_THSEXITCTL_MASK)
37551#define MIPI_DSI_DSI_PHYTIMING_M_TLPXCTL_MASK (0xFF00U)
37552#define MIPI_DSI_DSI_PHYTIMING_M_TLPXCTL_SHIFT (8U)
37553#define MIPI_DSI_DSI_PHYTIMING_M_TLPXCTL(x) \
37554 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING_M_TLPXCTL_SHIFT)) & MIPI_DSI_DSI_PHYTIMING_M_TLPXCTL_MASK)
37555/*! @} */
37556
37557/*! @name DSI_PHYTIMING1 - Specifies the D-PHY timing register 1. */
37558/*! @{ */
37559#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKTRAILCTL_MASK (0xFFU)
37560#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKTRAILCTL_SHIFT (0U)
37561#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKTRAILCTL(x) \
37562 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING1_M_TCLKTRAILCTL_SHIFT)) & \
37563 MIPI_DSI_DSI_PHYTIMING1_M_TCLKTRAILCTL_MASK)
37564#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPOSTCTL_MASK (0xFF00U)
37565#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPOSTCTL_SHIFT (8U)
37566#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPOSTCTL(x) \
37567 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING1_M_TCLKPOSTCTL_SHIFT)) & \
37568 MIPI_DSI_DSI_PHYTIMING1_M_TCLKPOSTCTL_MASK)
37569#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKZEROCTL_MASK (0xFF0000U)
37570#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKZEROCTL_SHIFT (16U)
37571#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKZEROCTL(x) \
37572 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING1_M_TCLKZEROCTL_SHIFT)) & \
37573 MIPI_DSI_DSI_PHYTIMING1_M_TCLKZEROCTL_MASK)
37574#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPRPRCTL_MASK (0xFF000000U)
37575#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPRPRCTL_SHIFT (24U)
37576#define MIPI_DSI_DSI_PHYTIMING1_M_TCLKPRPRCTL(x) \
37577 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING1_M_TCLKPRPRCTL_SHIFT)) & \
37578 MIPI_DSI_DSI_PHYTIMING1_M_TCLKPRPRCTL_MASK)
37579/*! @} */
37580
37581/*! @name DSI_PHYTIMING2 - Specifies the D-PHY timing register 2. */
37582/*! @{ */
37583#define MIPI_DSI_DSI_PHYTIMING2_M_THSTRAILCTL_MASK (0xFFU)
37584#define MIPI_DSI_DSI_PHYTIMING2_M_THSTRAILCTL_SHIFT (0U)
37585#define MIPI_DSI_DSI_PHYTIMING2_M_THSTRAILCTL(x) \
37586 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING2_M_THSTRAILCTL_SHIFT)) & \
37587 MIPI_DSI_DSI_PHYTIMING2_M_THSTRAILCTL_MASK)
37588#define MIPI_DSI_DSI_PHYTIMING2_M_THSZEROCTL_MASK (0xFF00U)
37589#define MIPI_DSI_DSI_PHYTIMING2_M_THSZEROCTL_SHIFT (8U)
37590#define MIPI_DSI_DSI_PHYTIMING2_M_THSZEROCTL(x) \
37591 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING2_M_THSZEROCTL_SHIFT)) & \
37592 MIPI_DSI_DSI_PHYTIMING2_M_THSZEROCTL_MASK)
37593#define MIPI_DSI_DSI_PHYTIMING2_M_THSPRPRCTL_MASK (0xFF0000U)
37594#define MIPI_DSI_DSI_PHYTIMING2_M_THSPRPRCTL_SHIFT (16U)
37595#define MIPI_DSI_DSI_PHYTIMING2_M_THSPRPRCTL(x) \
37596 (((uint32_t)(((uint32_t)(x)) << MIPI_DSI_DSI_PHYTIMING2_M_THSPRPRCTL_SHIFT)) & \
37597 MIPI_DSI_DSI_PHYTIMING2_M_THSPRPRCTL_MASK)
37598/*! @} */
37599
37600/*!
37601 * @}
37602 */ /* end of group MIPI_DSI_Register_Masks */
37603
37604/* MIPI_DSI - Peripheral instance base addresses */
37605/** Peripheral MIPI_DSI base address */
37606#define MIPI_DSI_BASE (0x32E10000u)
37607/** Peripheral MIPI_DSI base pointer */
37608#define MIPI_DSI ((MIPI_DSI_Type *)MIPI_DSI_BASE)
37609/** Array initializer of MIPI_DSI peripheral base addresses */
37610#define MIPI_DSI_BASE_ADDRS \
37611 { \
37612 MIPI_DSI_BASE \
37613 }
37614/** Array initializer of MIPI_DSI peripheral base pointers */
37615#define MIPI_DSI_BASE_PTRS \
37616 { \
37617 MIPI_DSI \
37618 }
37619
37620/*!
37621 * @}
37622 */ /* end of group MIPI_DSI_Peripheral_Access_Layer */
37623
37624/*!
37625 * @brief Power mode on the other side definition.
37626 */
37627typedef enum _mu_power_mode
37628{
37629 kMU_PowerModeRun = 0x00U, /*!< Run mode. */
37630 kMU_PowerModeWait = 0x01U, /*!< WAIT mode. */
37631 kMU_PowerModeStop = 0x03U, /*!< STOP mode. */
37632} mu_power_mode_t;
37633
37634/* ----------------------------------------------------------------------------
37635 -- MU Peripheral Access Layer
37636 ---------------------------------------------------------------------------- */
37637
37638/*!
37639 * @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
37640 * @{
37641 */
37642
37643/** MU - Register Layout Typedef */
37644typedef struct
37645{
37646 __IO uint32_t TR[4]; /**< Processor B Transmit Register 0..Processor B Transmit Register 3, array offset: 0x0, array
37647 step: 0x4 */
37648 __I uint32_t RR[4]; /**< Processor B Receive Register 0..Processor B Receive Register 3, array offset: 0x10, array
37649 step: 0x4 */
37650 __IO uint32_t SR; /**< Processor B Status Register, offset: 0x20 */
37651 __IO uint32_t CR; /**< Processor B Control Register, offset: 0x24 */
37652} MU_Type;
37653
37654/* ----------------------------------------------------------------------------
37655 -- MU Register Masks
37656 ---------------------------------------------------------------------------- */
37657
37658/*!
37659 * @addtogroup MU_Register_Masks MU Register Masks
37660 * @{
37661 */
37662
37663/*! @name TR - Processor B Transmit Register 0..Processor B Transmit Register 3 */
37664/*! @{ */
37665#define MU_TR_BTR0_MASK (0xFFFFFFFFU)
37666#define MU_TR_BTR0_SHIFT (0U)
37667#define MU_TR_BTR0(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR0_SHIFT)) & MU_TR_BTR0_MASK)
37668#define MU_TR_BTR1_MASK (0xFFFFFFFFU)
37669#define MU_TR_BTR1_SHIFT (0U)
37670#define MU_TR_BTR1(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR1_SHIFT)) & MU_TR_BTR1_MASK)
37671#define MU_TR_BTR2_MASK (0xFFFFFFFFU)
37672#define MU_TR_BTR2_SHIFT (0U)
37673#define MU_TR_BTR2(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR2_SHIFT)) & MU_TR_BTR2_MASK)
37674#define MU_TR_BTR3_MASK (0xFFFFFFFFU)
37675#define MU_TR_BTR3_SHIFT (0U)
37676#define MU_TR_BTR3(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_BTR3_SHIFT)) & MU_TR_BTR3_MASK)
37677/*! @} */
37678
37679/* The count of MU_TR */
37680#define MU_TR_COUNT (4U)
37681
37682/*! @name RR - Processor B Receive Register 0..Processor B Receive Register 3 */
37683/*! @{ */
37684#define MU_RR_BRR0_MASK (0xFFFFFFFFU)
37685#define MU_RR_BRR0_SHIFT (0U)
37686#define MU_RR_BRR0(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR0_SHIFT)) & MU_RR_BRR0_MASK)
37687#define MU_RR_BRR1_MASK (0xFFFFFFFFU)
37688#define MU_RR_BRR1_SHIFT (0U)
37689#define MU_RR_BRR1(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR1_SHIFT)) & MU_RR_BRR1_MASK)
37690#define MU_RR_BRR2_MASK (0xFFFFFFFFU)
37691#define MU_RR_BRR2_SHIFT (0U)
37692#define MU_RR_BRR2(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR2_SHIFT)) & MU_RR_BRR2_MASK)
37693#define MU_RR_BRR3_MASK (0xFFFFFFFFU)
37694#define MU_RR_BRR3_SHIFT (0U)
37695#define MU_RR_BRR3(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_BRR3_SHIFT)) & MU_RR_BRR3_MASK)
37696/*! @} */
37697
37698/* The count of MU_RR */
37699#define MU_RR_COUNT (4U)
37700
37701/*! @name SR - Processor B Status Register */
37702/*! @{ */
37703#define MU_SR_Fn_MASK (0x7U)
37704#define MU_SR_Fn_SHIFT (0U)
37705/*! Fn
37706 * 0b000..ABFn bit in ACR register is written 0 (default).
37707 * 0b001..ABFn bit in ACR register is written 1.
37708 */
37709#define MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK)
37710#define MU_SR_EP_MASK (0x10U)
37711#define MU_SR_EP_SHIFT (4U)
37712/*! EP
37713 * 0b0..The Processor B-side event is not pending (default).
37714 * 0b1..The Processor B-side event is pending.
37715 */
37716#define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)
37717#define MU_SR_APM_MASK (0x60U)
37718#define MU_SR_APM_SHIFT (5U)
37719/*! APM
37720 * 0b00..The System is in Run Mode.
37721 * 0b01..The System is in WAIT Mode.
37722 * 0b10..Reserved.
37723 * 0b11..The System is in STOP Mode.
37724 */
37725#define MU_SR_APM(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_APM_SHIFT)) & MU_SR_APM_MASK)
37726#define MU_SR_ARS_MASK (0x80U)
37727#define MU_SR_ARS_SHIFT (7U)
37728/*! ARS
37729 * 0b0..The Processor A or the Processor A-side of the MU is not in reset.
37730 * 0b1..The Processor A or the Processor A-side of the MU is in reset.
37731 */
37732#define MU_SR_ARS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_ARS_SHIFT)) & MU_SR_ARS_MASK)
37733#define MU_SR_FUP_MASK (0x100U)
37734#define MU_SR_FUP_SHIFT (8U)
37735/*! FUP
37736 * 0b0..No flags updated, initiated by the Processor B, in progress (default)
37737 * 0b1..Processor B initiated flags update, processing
37738 */
37739#define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)
37740#define MU_SR_TEn_MASK (0xF00000U)
37741#define MU_SR_TEn_SHIFT (20U)
37742/*! TEn
37743 * 0b0000..BTRn register is not empty.
37744 * 0b0001..BTRn register is empty (default).
37745 */
37746#define MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK)
37747#define MU_SR_RFn_MASK (0xF000000U)
37748#define MU_SR_RFn_SHIFT (24U)
37749/*! RFn
37750 * 0b0000..BRRn register is not full (default).
37751 * 0b0001..BRRn register has received data from ATRn register and is ready to be read by the Processor B.
37752 */
37753#define MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)
37754#define MU_SR_GIPn_MASK (0xF0000000U)
37755#define MU_SR_GIPn_SHIFT (28U)
37756/*! GIPn
37757 * 0b0000..Processor B general purpose interrupt n is not pending. (default)
37758 * 0b0001..Processor B general purpose interrupt n is pending.
37759 */
37760#define MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK)
37761/*! @} */
37762
37763/*! @name CR - Processor B Control Register */
37764/*! @{ */
37765#define MU_CR_BAFn_MASK (0x7U)
37766#define MU_CR_BAFn_SHIFT (0U)
37767/*! BAFn
37768 * 0b000..Clears the Fn bit in the ASR register.
37769 * 0b001..Sets the Fn bit in the ASR register.
37770 */
37771#define MU_CR_BAFn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_BAFn_SHIFT)) & MU_CR_BAFn_MASK)
37772#define MU_CR_HRM_MASK (0x10U)
37773#define MU_CR_HRM_SHIFT (4U)
37774/*! HRM
37775 * 0b0..BHR bit in ACR is not masked, enables the hardware reset to the Processor B (default after hardware reset).
37776 * 0b1..BHR bit in ACR is masked, disables the hardware reset request to the Processor B.
37777 */
37778#define MU_CR_HRM(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_HRM_SHIFT)) & MU_CR_HRM_MASK)
37779#define MU_CR_GIRn_MASK (0xF0000U)
37780#define MU_CR_GIRn_SHIFT (16U)
37781/*! GIRn
37782 * 0b0000..Processor B General Interrupt n is not requested to the Processor A (default).
37783 * 0b0001..Processor B General Interrupt n is requested to the Processor A.
37784 */
37785#define MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
37786#define MU_CR_TIEn_MASK (0xF00000U)
37787#define MU_CR_TIEn_SHIFT (20U)
37788/*! TIEn
37789 * 0b0000..Disables Processor B Transmit Interrupt n. (default)
37790 * 0b0001..Enables Processor B Transmit Interrupt n.
37791 */
37792#define MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK)
37793#define MU_CR_RIEn_MASK (0xF000000U)
37794#define MU_CR_RIEn_SHIFT (24U)
37795/*! RIEn
37796 * 0b0000..Disables Processor B Receive Interrupt n. (default)
37797 * 0b0001..Enables Processor B Receive Interrupt n.
37798 */
37799#define MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK)
37800#define MU_CR_GIEn_MASK (0xF0000000U)
37801#define MU_CR_GIEn_SHIFT (28U)
37802/*! GIEn
37803 * 0b0000..Disables Processor B General Interrupt n. (default)
37804 * 0b0001..Enables Processor B General Interrupt n.
37805 */
37806#define MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK)
37807/*! @} */
37808
37809/*!
37810 * @}
37811 */ /* end of group MU_Register_Masks */
37812
37813/* MU - Peripheral instance base addresses */
37814/** Peripheral MUB base address */
37815#define MUB_BASE (0x30AB0000u)
37816/** Peripheral MUB base pointer */
37817#define MUB ((MU_Type *)MUB_BASE)
37818/** Array initializer of MU peripheral base addresses */
37819#define MU_BASE_ADDRS \
37820 { \
37821 MUB_BASE \
37822 }
37823/** Array initializer of MU peripheral base pointers */
37824#define MU_BASE_PTRS \
37825 { \
37826 MUB \
37827 }
37828/** Interrupt vectors for the MU peripheral type */
37829#define MU_IRQS \
37830 { \
37831 MU_M7_IRQn \
37832 }
37833/* Backward compatibility */
37834#define MU_SR_PM_MASK MU_SR_APM_MASK
37835#define MU_SR_PM_SHIFT MU_SR_APM_SHIFT
37836#define MU_SR_PM(x) MU_SR_APM(x)
37837#define MU_SR_RS_MASK MU_SR_ARS_MASK
37838#define MU_SR_RS_SHIFT MU_SR_ARS_SHIFT
37839#define MU_SR_RS(x) MU_SR_ARS(x)
37840#define MU_CR_Fn_MASK MU_CR_BAFn_MASK
37841#define MU_CR_Fn_SHIFT MU_CR_BAFn_SHIFT
37842#define MU_CR_Fn(x) MU_CR_BAFn(x)
37843
37844/*!
37845 * @}
37846 */ /* end of group MU_Peripheral_Access_Layer */
37847
37848/* ----------------------------------------------------------------------------
37849 -- OCOTP Peripheral Access Layer
37850 ---------------------------------------------------------------------------- */
37851
37852/*!
37853 * @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer
37854 * @{
37855 */
37856
37857/** OCOTP - Register Layout Typedef */
37858typedef struct
37859{
37860 __IO uint32_t HW_OCOTP_CTRL; /**< OTP Controller Control Register, offset: 0x0 */
37861 __IO uint32_t HW_OCOTP_CTRL_SET; /**< OTP Controller Control Register, offset: 0x4 */
37862 __IO uint32_t HW_OCOTP_CTRL_CLR; /**< OTP Controller Control Register, offset: 0x8 */
37863 __IO uint32_t HW_OCOTP_CTRL_TOG; /**< OTP Controller Control Register, offset: 0xC */
37864 __IO uint32_t HW_OCOTP_TIMING; /**< OTP Controller Timing Register, offset: 0x10 */
37865 uint8_t RESERVED_0[12];
37866 __IO uint32_t HW_OCOTP_DATA; /**< OTP Controller Write Data Register, offset: 0x20 */
37867 uint8_t RESERVED_1[12];
37868 __IO uint32_t HW_OCOTP_READ_CTRL; /**< OTP Controller Write Data Register, offset: 0x30 */
37869 uint8_t RESERVED_2[12];
37870 __IO uint32_t HW_OCOTP_READ_FUSE_DATA; /**< OTP Controller Read Data Register, offset: 0x40 */
37871 uint8_t RESERVED_3[12];
37872 __IO uint32_t HW_OCOTP_SW_STICKY; /**< Sticky bit Register, offset: 0x50 */
37873 uint8_t RESERVED_4[12];
37874 __IO uint32_t HW_OCOTP_SCS; /**< Software Controllable Signals Register, offset: 0x60 */
37875 __IO uint32_t HW_OCOTP_SCS_SET; /**< Software Controllable Signals Register, offset: 0x64 */
37876 __IO uint32_t HW_OCOTP_SCS_CLR; /**< Software Controllable Signals Register, offset: 0x68 */
37877 __IO uint32_t HW_OCOTP_SCS_TOG; /**< Software Controllable Signals Register, offset: 0x6C */
37878 uint8_t RESERVED_5[32];
37879 __I uint32_t HW_OCOTP_VERSION; /**< OTP Controller Version Register, offset: 0x90 */
37880 uint8_t RESERVED_6[876];
37881 __I uint32_t HW_OCOTP_LOCK; /**< Value of OTP Bank0 Word0 (Lock controls), offset: 0x400 */
37882 uint8_t RESERVED_7[12];
37883 __IO uint32_t HW_OCOTP_TESTER0; /**< Value of OTP Bank0 Word1 (Tester Info.), offset: 0x410 */
37884 uint8_t RESERVED_8[12];
37885 __IO uint32_t HW_OCOTP_TESTER1; /**< Value of OTP Bank0 Word2 (tester Info.), offset: 0x420 */
37886 uint8_t RESERVED_9[12];
37887 __IO uint32_t HW_OCOTP_TESTER2; /**< Value of OTP Bank0 Word3 (Tester Info.), offset: 0x430 */
37888 uint8_t RESERVED_10[12];
37889 __IO uint32_t HW_OCOTP_TESTER3; /**< Value of OTP Bank1 Word0 (Tester Info.), offset: 0x440 */
37890 uint8_t RESERVED_11[12];
37891 __IO uint32_t HW_OCOTP_TESTER4; /**< Value of OTP Bank1 Word1 (Tester Info.), offset: 0x450 */
37892 uint8_t RESERVED_12[12];
37893 __IO uint32_t HW_OCOTP_TESTER5; /**< Value of OTP Bank1 Word2 (Tester Info.), offset: 0x460 */
37894 uint8_t RESERVED_13[12];
37895 __IO uint32_t HW_OCOTP_BOOT_CFG0; /**< Value of OTP Bank1 Word3 (Boot Configuration Info.), offset: 0x470 */
37896 uint8_t RESERVED_14[12];
37897 __IO uint32_t HW_OCOTP_BOOT_CFG1; /**< Value of OTP Bank2 Word0 (Boot Configuration Info.), offset: 0x480 */
37898 uint8_t RESERVED_15[12];
37899 __IO uint32_t HW_OCOTP_BOOT_CFG2; /**< Value of OTP Bank2 Word1 (Boot Configuration Info.), offset: 0x490 */
37900 uint8_t RESERVED_16[12];
37901 __IO uint32_t HW_OCOTP_BOOT_CFG3; /**< Value of OTP Bank2 Word2 (Boot Configuration Info.), offset: 0x4A0 */
37902 uint8_t RESERVED_17[12];
37903 __IO uint32_t HW_OCOTP_BOOT_CFG4; /**< Value of OTP Bank2 Word3 (BOOT Configuration Info.), offset: 0x4B0 */
37904 uint8_t RESERVED_18[12];
37905 __IO uint32_t HW_OCOTP_MEM_TRIM0; /**< Value of OTP Bank3 Word0 (Memory Related Info.), offset: 0x4C0 */
37906 uint8_t RESERVED_19[12];
37907 __IO uint32_t HW_OCOTP_MEM_TRIM1; /**< Value of OTP Bank3 Word1 (Memory Related Info.), offset: 0x4D0 */
37908 uint8_t RESERVED_20[12];
37909 __IO uint32_t HW_OCOTP_ANA0; /**< Value of OTP Bank3 Word2 (Analog Info.), offset: 0x4E0 */
37910 uint8_t RESERVED_21[12];
37911 __IO uint32_t HW_OCOTP_ANA1; /**< Value of OTP Bank3 Word3 (Analog Info.), offset: 0x4F0 */
37912 uint8_t RESERVED_22[140];
37913 __IO uint32_t HW_OCOTP_SRK0; /**< Shadow Register for OTP Bank6 Word0 (SRK Hash), offset: 0x580 */
37914 uint8_t RESERVED_23[12];
37915 __IO uint32_t HW_OCOTP_SRK1; /**< Shadow Register for OTP Bank6 Word1 (SRK Hash), offset: 0x590 */
37916 uint8_t RESERVED_24[12];
37917 __IO uint32_t HW_OCOTP_SRK2; /**< Shadow Register for OTP Bank6 Word2 (SRK Hash), offset: 0x5A0 */
37918 uint8_t RESERVED_25[12];
37919 __IO uint32_t HW_OCOTP_SRK3; /**< Shadow Register for OTP Bank6 Word3 (SRK Hash), offset: 0x5B0 */
37920 uint8_t RESERVED_26[12];
37921 __IO uint32_t HW_OCOTP_SRK4; /**< Shadow Register for OTP Bank7 Word0 (SRK Hash), offset: 0x5C0 */
37922 uint8_t RESERVED_27[12];
37923 __IO uint32_t HW_OCOTP_SRK5; /**< Shadow Register for OTP Bank7 Word1 (SRK Hash), offset: 0x5D0 */
37924 uint8_t RESERVED_28[12];
37925 __IO uint32_t HW_OCOTP_SRK6; /**< Shadow Register for OTP Bank7 Word2 (SRK Hash), offset: 0x5E0 */
37926 uint8_t RESERVED_29[12];
37927 __IO uint32_t HW_OCOTP_SRK7; /**< Shadow Register for OTP Bank7 Word3 (SRK Hash), offset: 0x5F0 */
37928 uint8_t RESERVED_30[12];
37929 __IO uint32_t HW_OCOTP_SJC_RESP0; /**< Value of OTP Bank8 Word0 (Secure JTAG Response Field), offset: 0x600 */
37930 uint8_t RESERVED_31[12];
37931 __IO uint32_t HW_OCOTP_SJC_RESP1; /**< Value of OTP Bank8 Word1 (Secure JTAG Response Field), offset: 0x610 */
37932 uint8_t RESERVED_32[12];
37933 __IO uint32_t HW_OCOTP_USB_ID; /**< Value of OTP Bank8 Word2 (USB ID info), offset: 0x620 */
37934 uint8_t RESERVED_33[12];
37935 __IO uint32_t HW_OCOTP_FIELD_RETURN; /**< Value of OTP Bank5 Word6 (Field Return), offset: 0x630 */
37936 uint8_t RESERVED_34[12];
37937 __IO uint32_t HW_OCOTP_MAC_ADDR0; /**< Value of OTP Bank9 Word0 (MAC Address), offset: 0x640 */
37938 uint8_t RESERVED_35[12];
37939 __IO uint32_t HW_OCOTP_MAC_ADDR1; /**< Value of OTP Bank9 Word1 (MAC Address), offset: 0x650 */
37940 uint8_t RESERVED_36[12];
37941 __IO uint32_t HW_OCOTP_MAC_ADDR2; /**< Value of OTP Bank9 Word2 (MAC Address), offset: 0x660 */
37942 uint8_t RESERVED_37[12];
37943 __IO uint32_t HW_OCOTP_SRK_REVOKE; /**< Value of OTP Bank9 Word3 (SRK Revoke), offset: 0x670 */
37944 uint8_t RESERVED_38[12];
37945 __IO uint32_t HW_OCOTP_MAU_KEY0; /**< Shadow Register for OTP Bank10 Word0 (MAU Key), offset: 0x680 */
37946 uint8_t RESERVED_39[12];
37947 __IO uint32_t HW_OCOTP_MAU_KEY1; /**< Shadow Register for OTP Bank10 Word1 (MAU Key), offset: 0x690 */
37948 uint8_t RESERVED_40[12];
37949 __IO uint32_t HW_OCOTP_MAU_KEY2; /**< Shadow Register for OTP Bank10 Word2 (MAU Key), offset: 0x6A0 */
37950 uint8_t RESERVED_41[12];
37951 __IO uint32_t HW_OCOTP_MAU_KEY3; /**< Shadow Register for OTP Bank10 Word3 (MAU Key), offset: 0x6B0 */
37952 uint8_t RESERVED_42[12];
37953 __IO uint32_t HW_OCOTP_MAU_KEY4; /**< Shadow Register for OTP Bank11 Word0 (MAU Key), offset: 0x6C0 */
37954 uint8_t RESERVED_43[12];
37955 __IO uint32_t HW_OCOTP_MAU_KEY5; /**< Shadow Register for OTP Bank11 Word1 (MAU Key), offset: 0x6D0 */
37956 uint8_t RESERVED_44[12];
37957 __IO uint32_t HW_OCOTP_MAU_KEY6; /**< Shadow Register for OTP Bank11 Word2 (MAU Key), offset: 0x6E0 */
37958 uint8_t RESERVED_45[12];
37959 __IO uint32_t HW_OCOTP_MAU_KEY7; /**< Shadow Register for OTP Bank11 Word3 (MAU Key), offset: 0x6F0 */
37960 uint8_t RESERVED_46[140];
37961 __IO uint32_t HW_OCOTP_GP10; /**< Value of OTP Bank14 Word0 (), offset: 0x780 */
37962 uint8_t RESERVED_47[12];
37963 __IO uint32_t HW_OCOTP_GP11; /**< Value of OTP Bank14 Word1 (), offset: 0x790 */
37964 uint8_t RESERVED_48[12];
37965 __IO uint32_t HW_OCOTP_GP20; /**< Value of OTP Bank14 Word2 (), offset: 0x7A0 */
37966 uint8_t RESERVED_49[12];
37967 __IO uint32_t HW_OCOTP_GP21; /**< Value of OTP Bank14 Word3 (), offset: 0x7B0 */
37968} OCOTP_Type;
37969
37970/* ----------------------------------------------------------------------------
37971 -- OCOTP Register Masks
37972 ---------------------------------------------------------------------------- */
37973
37974/*!
37975 * @addtogroup OCOTP_Register_Masks OCOTP Register Masks
37976 * @{
37977 */
37978
37979/*! @name HW_OCOTP_CTRL - OTP Controller Control Register */
37980/*! @{ */
37981#define OCOTP_HW_OCOTP_CTRL_ADDR_MASK (0xFFU)
37982#define OCOTP_HW_OCOTP_CTRL_ADDR_SHIFT (0U)
37983#define OCOTP_HW_OCOTP_CTRL_ADDR(x) \
37984 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_ADDR_MASK)
37985#define OCOTP_HW_OCOTP_CTRL_BUSY_MASK (0x100U)
37986#define OCOTP_HW_OCOTP_CTRL_BUSY_SHIFT (8U)
37987#define OCOTP_HW_OCOTP_CTRL_BUSY(x) \
37988 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_HW_OCOTP_CTRL_BUSY_MASK)
37989#define OCOTP_HW_OCOTP_CTRL_ERROR_MASK (0x200U)
37990#define OCOTP_HW_OCOTP_CTRL_ERROR_SHIFT (9U)
37991#define OCOTP_HW_OCOTP_CTRL_ERROR(x) \
37992 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_ERROR_MASK)
37993#define OCOTP_HW_OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x400U)
37994#define OCOTP_HW_OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (10U)
37995#define OCOTP_HW_OCOTP_CTRL_RELOAD_SHADOWS(x) \
37996 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & \
37997 OCOTP_HW_OCOTP_CTRL_RELOAD_SHADOWS_MASK)
37998#define OCOTP_HW_OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U)
37999#define OCOTP_HW_OCOTP_CTRL_WR_UNLOCK_SHIFT (16U)
38000#define OCOTP_HW_OCOTP_CTRL_WR_UNLOCK(x) \
38001 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_HW_OCOTP_CTRL_WR_UNLOCK_MASK)
38002/*! @} */
38003
38004/*! @name HW_OCOTP_CTRL_SET - OTP Controller Control Register */
38005/*! @{ */
38006#define OCOTP_HW_OCOTP_CTRL_SET_ADDR_MASK (0xFFU)
38007#define OCOTP_HW_OCOTP_CTRL_SET_ADDR_SHIFT (0U)
38008#define OCOTP_HW_OCOTP_CTRL_SET_ADDR(x) \
38009 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_SET_ADDR_MASK)
38010#define OCOTP_HW_OCOTP_CTRL_SET_BUSY_MASK (0x100U)
38011#define OCOTP_HW_OCOTP_CTRL_SET_BUSY_SHIFT (8U)
38012#define OCOTP_HW_OCOTP_CTRL_SET_BUSY(x) \
38013 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_HW_OCOTP_CTRL_SET_BUSY_MASK)
38014#define OCOTP_HW_OCOTP_CTRL_SET_ERROR_MASK (0x200U)
38015#define OCOTP_HW_OCOTP_CTRL_SET_ERROR_SHIFT (9U)
38016#define OCOTP_HW_OCOTP_CTRL_SET_ERROR(x) \
38017 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_SET_ERROR_MASK)
38018#define OCOTP_HW_OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x400U)
38019#define OCOTP_HW_OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (10U)
38020#define OCOTP_HW_OCOTP_CTRL_SET_RELOAD_SHADOWS(x) \
38021 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & \
38022 OCOTP_HW_OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)
38023#define OCOTP_HW_OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U)
38024#define OCOTP_HW_OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U)
38025#define OCOTP_HW_OCOTP_CTRL_SET_WR_UNLOCK(x) \
38026 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_HW_OCOTP_CTRL_SET_WR_UNLOCK_MASK)
38027/*! @} */
38028
38029/*! @name HW_OCOTP_CTRL_CLR - OTP Controller Control Register */
38030/*! @{ */
38031#define OCOTP_HW_OCOTP_CTRL_CLR_ADDR_MASK (0xFFU)
38032#define OCOTP_HW_OCOTP_CTRL_CLR_ADDR_SHIFT (0U)
38033#define OCOTP_HW_OCOTP_CTRL_CLR_ADDR(x) \
38034 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_CLR_ADDR_MASK)
38035#define OCOTP_HW_OCOTP_CTRL_CLR_BUSY_MASK (0x100U)
38036#define OCOTP_HW_OCOTP_CTRL_CLR_BUSY_SHIFT (8U)
38037#define OCOTP_HW_OCOTP_CTRL_CLR_BUSY(x) \
38038 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_HW_OCOTP_CTRL_CLR_BUSY_MASK)
38039#define OCOTP_HW_OCOTP_CTRL_CLR_ERROR_MASK (0x200U)
38040#define OCOTP_HW_OCOTP_CTRL_CLR_ERROR_SHIFT (9U)
38041#define OCOTP_HW_OCOTP_CTRL_CLR_ERROR(x) \
38042 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_CLR_ERROR_MASK)
38043#define OCOTP_HW_OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x400U)
38044#define OCOTP_HW_OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (10U)
38045#define OCOTP_HW_OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) \
38046 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & \
38047 OCOTP_HW_OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)
38048#define OCOTP_HW_OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U)
38049#define OCOTP_HW_OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U)
38050#define OCOTP_HW_OCOTP_CTRL_CLR_WR_UNLOCK(x) \
38051 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_HW_OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
38052/*! @} */
38053
38054/*! @name HW_OCOTP_CTRL_TOG - OTP Controller Control Register */
38055/*! @{ */
38056#define OCOTP_HW_OCOTP_CTRL_TOG_ADDR_MASK (0xFFU)
38057#define OCOTP_HW_OCOTP_CTRL_TOG_ADDR_SHIFT (0U)
38058#define OCOTP_HW_OCOTP_CTRL_TOG_ADDR(x) \
38059 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_TOG_ADDR_MASK)
38060#define OCOTP_HW_OCOTP_CTRL_TOG_BUSY_MASK (0x100U)
38061#define OCOTP_HW_OCOTP_CTRL_TOG_BUSY_SHIFT (8U)
38062#define OCOTP_HW_OCOTP_CTRL_TOG_BUSY(x) \
38063 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_HW_OCOTP_CTRL_TOG_BUSY_MASK)
38064#define OCOTP_HW_OCOTP_CTRL_TOG_ERROR_MASK (0x200U)
38065#define OCOTP_HW_OCOTP_CTRL_TOG_ERROR_SHIFT (9U)
38066#define OCOTP_HW_OCOTP_CTRL_TOG_ERROR(x) \
38067 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_HW_OCOTP_CTRL_TOG_ERROR_MASK)
38068#define OCOTP_HW_OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x400U)
38069#define OCOTP_HW_OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (10U)
38070#define OCOTP_HW_OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) \
38071 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & \
38072 OCOTP_HW_OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)
38073#define OCOTP_HW_OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U)
38074#define OCOTP_HW_OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U)
38075#define OCOTP_HW_OCOTP_CTRL_TOG_WR_UNLOCK(x) \
38076 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_HW_OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
38077/*! @} */
38078
38079/*! @name HW_OCOTP_TIMING - OTP Controller Timing Register */
38080/*! @{ */
38081#define OCOTP_HW_OCOTP_TIMING_STROBE_PROG_MASK (0xFFFU)
38082#define OCOTP_HW_OCOTP_TIMING_STROBE_PROG_SHIFT (0U)
38083#define OCOTP_HW_OCOTP_TIMING_STROBE_PROG(x) \
38084 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TIMING_STROBE_PROG_SHIFT)) & OCOTP_HW_OCOTP_TIMING_STROBE_PROG_MASK)
38085#define OCOTP_HW_OCOTP_TIMING_RELAX_MASK (0xF000U)
38086#define OCOTP_HW_OCOTP_TIMING_RELAX_SHIFT (12U)
38087#define OCOTP_HW_OCOTP_TIMING_RELAX(x) \
38088 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TIMING_RELAX_SHIFT)) & OCOTP_HW_OCOTP_TIMING_RELAX_MASK)
38089#define OCOTP_HW_OCOTP_TIMING_STROBE_READ_MASK (0x3F0000U)
38090#define OCOTP_HW_OCOTP_TIMING_STROBE_READ_SHIFT (16U)
38091#define OCOTP_HW_OCOTP_TIMING_STROBE_READ(x) \
38092 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TIMING_STROBE_READ_SHIFT)) & OCOTP_HW_OCOTP_TIMING_STROBE_READ_MASK)
38093#define OCOTP_HW_OCOTP_TIMING_WAIT_MASK (0xFC00000U)
38094#define OCOTP_HW_OCOTP_TIMING_WAIT_SHIFT (22U)
38095#define OCOTP_HW_OCOTP_TIMING_WAIT(x) \
38096 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TIMING_WAIT_SHIFT)) & OCOTP_HW_OCOTP_TIMING_WAIT_MASK)
38097#define OCOTP_HW_OCOTP_TIMING_RSRVD0_MASK (0xF0000000U)
38098#define OCOTP_HW_OCOTP_TIMING_RSRVD0_SHIFT (28U)
38099#define OCOTP_HW_OCOTP_TIMING_RSRVD0(x) \
38100 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TIMING_RSRVD0_SHIFT)) & OCOTP_HW_OCOTP_TIMING_RSRVD0_MASK)
38101/*! @} */
38102
38103/*! @name HW_OCOTP_DATA - OTP Controller Write Data Register */
38104/*! @{ */
38105#define OCOTP_HW_OCOTP_DATA_DATA_MASK (0xFFFFFFFFU)
38106#define OCOTP_HW_OCOTP_DATA_DATA_SHIFT (0U)
38107#define OCOTP_HW_OCOTP_DATA_DATA(x) \
38108 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_DATA_DATA_SHIFT)) & OCOTP_HW_OCOTP_DATA_DATA_MASK)
38109/*! @} */
38110
38111/*! @name HW_OCOTP_READ_CTRL - OTP Controller Write Data Register */
38112/*! @{ */
38113#define OCOTP_HW_OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U)
38114#define OCOTP_HW_OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U)
38115#define OCOTP_HW_OCOTP_READ_CTRL_READ_FUSE(x) \
38116 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & \
38117 OCOTP_HW_OCOTP_READ_CTRL_READ_FUSE_MASK)
38118#define OCOTP_HW_OCOTP_READ_CTRL_RSVD0_MASK (0xFFFFFFFEU)
38119#define OCOTP_HW_OCOTP_READ_CTRL_RSVD0_SHIFT (1U)
38120#define OCOTP_HW_OCOTP_READ_CTRL_RSVD0(x) \
38121 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_READ_CTRL_RSVD0_SHIFT)) & OCOTP_HW_OCOTP_READ_CTRL_RSVD0_MASK)
38122/*! @} */
38123
38124/*! @name HW_OCOTP_READ_FUSE_DATA - OTP Controller Read Data Register */
38125/*! @{ */
38126#define OCOTP_HW_OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU)
38127#define OCOTP_HW_OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U)
38128#define OCOTP_HW_OCOTP_READ_FUSE_DATA_DATA(x) \
38129 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & \
38130 OCOTP_HW_OCOTP_READ_FUSE_DATA_DATA_MASK)
38131/*! @} */
38132
38133/*! @name HW_OCOTP_SW_STICKY - Sticky bit Register */
38134/*! @{ */
38135#define OCOTP_HW_OCOTP_SW_STICKY_RSVD0_MASK (0x1U)
38136#define OCOTP_HW_OCOTP_SW_STICKY_RSVD0_SHIFT (0U)
38137#define OCOTP_HW_OCOTP_SW_STICKY_RSVD0(x) \
38138 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_RSVD0_SHIFT)) & OCOTP_HW_OCOTP_SW_STICKY_RSVD0_MASK)
38139#define OCOTP_HW_OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK (0x2U)
38140#define OCOTP_HW_OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT (1U)
38141#define OCOTP_HW_OCOTP_SW_STICKY_SRK_REVOKE_LOCK(x) \
38142 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_SRK_REVOKE_LOCK_SHIFT)) & \
38143 OCOTP_HW_OCOTP_SW_STICKY_SRK_REVOKE_LOCK_MASK)
38144#define OCOTP_HW_OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK (0x4U)
38145#define OCOTP_HW_OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT (2U)
38146#define OCOTP_HW_OCOTP_SW_STICKY_FIELD_RETURN_LOCK(x) \
38147 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_FIELD_RETURN_LOCK_SHIFT)) & \
38148 OCOTP_HW_OCOTP_SW_STICKY_FIELD_RETURN_LOCK_MASK)
38149#define OCOTP_HW_OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK (0x8U)
38150#define OCOTP_HW_OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT (3U)
38151#define OCOTP_HW_OCOTP_SW_STICKY_BLOCK_ROM_PART(x) \
38152 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_BLOCK_ROM_PART_SHIFT)) & \
38153 OCOTP_HW_OCOTP_SW_STICKY_BLOCK_ROM_PART_MASK)
38154#define OCOTP_HW_OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK (0x10U)
38155#define OCOTP_HW_OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT (4U)
38156#define OCOTP_HW_OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE(x) \
38157 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_SHIFT)) & \
38158 OCOTP_HW_OCOTP_SW_STICKY_JTAG_BLOCK_RELEASE_MASK)
38159#define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK_MASK (0x20U)
38160#define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK_SHIFT (5U)
38161#define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK(x) \
38162 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK_SHIFT)) & \
38163 OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_GROUP_MASK_MASK)
38164#define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK_MASK (0x40U)
38165#define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK_SHIFT (6U)
38166#define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK(x) \
38167 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK_SHIFT)) & \
38168 OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDMI_FW_SRK_MASK)
38169#define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK_MASK (0x80U)
38170#define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK_SHIFT (7U)
38171#define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK(x) \
38172 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK_SHIFT)) & \
38173 OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDMI_KMEK_MASK)
38174#define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT_MASK (0x100U)
38175#define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT_SHIFT (8U)
38176#define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT(x) \
38177 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT_SHIFT)) & \
38178 OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_GLOBAL_CONSTANT_MASK)
38179#define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT_MASK (0x200U)
38180#define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT_SHIFT (9U)
38181#define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT(x) \
38182 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT_SHIFT)) & \
38183 OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_TX_CERT_MASK)
38184#define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY_MASK (0x400U)
38185#define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY_SHIFT (10U)
38186#define OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY(x) \
38187 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY_SHIFT)) & \
38188 OCOTP_HW_OCOTP_SW_STICKY_DISABLE_READ_HDCP_DEVICE_KEY_MASK)
38189#define OCOTP_HW_OCOTP_SW_STICKY_RSVD1_MASK (0xFFFFF800U)
38190#define OCOTP_HW_OCOTP_SW_STICKY_RSVD1_SHIFT (11U)
38191#define OCOTP_HW_OCOTP_SW_STICKY_RSVD1(x) \
38192 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SW_STICKY_RSVD1_SHIFT)) & OCOTP_HW_OCOTP_SW_STICKY_RSVD1_MASK)
38193/*! @} */
38194
38195/*! @name HW_OCOTP_SCS - Software Controllable Signals Register */
38196/*! @{ */
38197#define OCOTP_HW_OCOTP_SCS_HAB_JDE_MASK (0x1U)
38198#define OCOTP_HW_OCOTP_SCS_HAB_JDE_SHIFT (0U)
38199#define OCOTP_HW_OCOTP_SCS_HAB_JDE(x) \
38200 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_HAB_JDE_SHIFT)) & OCOTP_HW_OCOTP_SCS_HAB_JDE_MASK)
38201#define OCOTP_HW_OCOTP_SCS_SPARE_MASK (0x7FFFFFFEU)
38202#define OCOTP_HW_OCOTP_SCS_SPARE_SHIFT (1U)
38203#define OCOTP_HW_OCOTP_SCS_SPARE(x) \
38204 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_SPARE_SHIFT)) & OCOTP_HW_OCOTP_SCS_SPARE_MASK)
38205#define OCOTP_HW_OCOTP_SCS_LOCK_MASK (0x80000000U)
38206#define OCOTP_HW_OCOTP_SCS_LOCK_SHIFT (31U)
38207#define OCOTP_HW_OCOTP_SCS_LOCK(x) \
38208 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_LOCK_SHIFT)) & OCOTP_HW_OCOTP_SCS_LOCK_MASK)
38209/*! @} */
38210
38211/*! @name HW_OCOTP_SCS_SET - Software Controllable Signals Register */
38212/*! @{ */
38213#define OCOTP_HW_OCOTP_SCS_SET_HAB_JDE_MASK (0x1U)
38214#define OCOTP_HW_OCOTP_SCS_SET_HAB_JDE_SHIFT (0U)
38215#define OCOTP_HW_OCOTP_SCS_SET_HAB_JDE(x) \
38216 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_SET_HAB_JDE_SHIFT)) & OCOTP_HW_OCOTP_SCS_SET_HAB_JDE_MASK)
38217#define OCOTP_HW_OCOTP_SCS_SET_SPARE_MASK (0x7FFFFFFEU)
38218#define OCOTP_HW_OCOTP_SCS_SET_SPARE_SHIFT (1U)
38219#define OCOTP_HW_OCOTP_SCS_SET_SPARE(x) \
38220 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_SET_SPARE_SHIFT)) & OCOTP_HW_OCOTP_SCS_SET_SPARE_MASK)
38221#define OCOTP_HW_OCOTP_SCS_SET_LOCK_MASK (0x80000000U)
38222#define OCOTP_HW_OCOTP_SCS_SET_LOCK_SHIFT (31U)
38223#define OCOTP_HW_OCOTP_SCS_SET_LOCK(x) \
38224 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_SET_LOCK_SHIFT)) & OCOTP_HW_OCOTP_SCS_SET_LOCK_MASK)
38225/*! @} */
38226
38227/*! @name HW_OCOTP_SCS_CLR - Software Controllable Signals Register */
38228/*! @{ */
38229#define OCOTP_HW_OCOTP_SCS_CLR_HAB_JDE_MASK (0x1U)
38230#define OCOTP_HW_OCOTP_SCS_CLR_HAB_JDE_SHIFT (0U)
38231#define OCOTP_HW_OCOTP_SCS_CLR_HAB_JDE(x) \
38232 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_CLR_HAB_JDE_SHIFT)) & OCOTP_HW_OCOTP_SCS_CLR_HAB_JDE_MASK)
38233#define OCOTP_HW_OCOTP_SCS_CLR_SPARE_MASK (0x7FFFFFFEU)
38234#define OCOTP_HW_OCOTP_SCS_CLR_SPARE_SHIFT (1U)
38235#define OCOTP_HW_OCOTP_SCS_CLR_SPARE(x) \
38236 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_CLR_SPARE_SHIFT)) & OCOTP_HW_OCOTP_SCS_CLR_SPARE_MASK)
38237#define OCOTP_HW_OCOTP_SCS_CLR_LOCK_MASK (0x80000000U)
38238#define OCOTP_HW_OCOTP_SCS_CLR_LOCK_SHIFT (31U)
38239#define OCOTP_HW_OCOTP_SCS_CLR_LOCK(x) \
38240 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_CLR_LOCK_SHIFT)) & OCOTP_HW_OCOTP_SCS_CLR_LOCK_MASK)
38241/*! @} */
38242
38243/*! @name HW_OCOTP_SCS_TOG - Software Controllable Signals Register */
38244/*! @{ */
38245#define OCOTP_HW_OCOTP_SCS_TOG_HAB_JDE_MASK (0x1U)
38246#define OCOTP_HW_OCOTP_SCS_TOG_HAB_JDE_SHIFT (0U)
38247#define OCOTP_HW_OCOTP_SCS_TOG_HAB_JDE(x) \
38248 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_TOG_HAB_JDE_SHIFT)) & OCOTP_HW_OCOTP_SCS_TOG_HAB_JDE_MASK)
38249#define OCOTP_HW_OCOTP_SCS_TOG_SPARE_MASK (0x7FFFFFFEU)
38250#define OCOTP_HW_OCOTP_SCS_TOG_SPARE_SHIFT (1U)
38251#define OCOTP_HW_OCOTP_SCS_TOG_SPARE(x) \
38252 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_TOG_SPARE_SHIFT)) & OCOTP_HW_OCOTP_SCS_TOG_SPARE_MASK)
38253#define OCOTP_HW_OCOTP_SCS_TOG_LOCK_MASK (0x80000000U)
38254#define OCOTP_HW_OCOTP_SCS_TOG_LOCK_SHIFT (31U)
38255#define OCOTP_HW_OCOTP_SCS_TOG_LOCK(x) \
38256 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SCS_TOG_LOCK_SHIFT)) & OCOTP_HW_OCOTP_SCS_TOG_LOCK_MASK)
38257/*! @} */
38258
38259/*! @name HW_OCOTP_VERSION - OTP Controller Version Register */
38260/*! @{ */
38261#define OCOTP_HW_OCOTP_VERSION_STEP_MASK (0xFFFFU)
38262#define OCOTP_HW_OCOTP_VERSION_STEP_SHIFT (0U)
38263#define OCOTP_HW_OCOTP_VERSION_STEP(x) \
38264 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_VERSION_STEP_SHIFT)) & OCOTP_HW_OCOTP_VERSION_STEP_MASK)
38265#define OCOTP_HW_OCOTP_VERSION_MINOR_MASK (0xFF0000U)
38266#define OCOTP_HW_OCOTP_VERSION_MINOR_SHIFT (16U)
38267#define OCOTP_HW_OCOTP_VERSION_MINOR(x) \
38268 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_HW_OCOTP_VERSION_MINOR_MASK)
38269#define OCOTP_HW_OCOTP_VERSION_MAJOR_MASK (0xFF000000U)
38270#define OCOTP_HW_OCOTP_VERSION_MAJOR_SHIFT (24U)
38271#define OCOTP_HW_OCOTP_VERSION_MAJOR(x) \
38272 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_HW_OCOTP_VERSION_MAJOR_MASK)
38273/*! @} */
38274
38275/*! @name HW_OCOTP_LOCK - Value of OTP Bank0 Word0 (Lock controls) */
38276/*! @{ */
38277#define OCOTP_HW_OCOTP_LOCK_TESTER_MASK (0x3U)
38278#define OCOTP_HW_OCOTP_LOCK_TESTER_SHIFT (0U)
38279#define OCOTP_HW_OCOTP_LOCK_TESTER(x) \
38280 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_TESTER_SHIFT)) & OCOTP_HW_OCOTP_LOCK_TESTER_MASK)
38281#define OCOTP_HW_OCOTP_LOCK_BOOT_CFG_MASK (0xCU)
38282#define OCOTP_HW_OCOTP_LOCK_BOOT_CFG_SHIFT (2U)
38283#define OCOTP_HW_OCOTP_LOCK_BOOT_CFG(x) \
38284 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_BOOT_CFG_SHIFT)) & OCOTP_HW_OCOTP_LOCK_BOOT_CFG_MASK)
38285#define OCOTP_HW_OCOTP_LOCK_SRK_MASK (0x200U)
38286#define OCOTP_HW_OCOTP_LOCK_SRK_SHIFT (9U)
38287#define OCOTP_HW_OCOTP_LOCK_SRK(x) \
38288 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_SRK_SHIFT)) & OCOTP_HW_OCOTP_LOCK_SRK_MASK)
38289#define OCOTP_HW_OCOTP_LOCK_SJC_RESP_MASK (0x400U)
38290#define OCOTP_HW_OCOTP_LOCK_SJC_RESP_SHIFT (10U)
38291#define OCOTP_HW_OCOTP_LOCK_SJC_RESP(x) \
38292 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_SJC_RESP_SHIFT)) & OCOTP_HW_OCOTP_LOCK_SJC_RESP_MASK)
38293#define OCOTP_HW_OCOTP_LOCK_USB_ID_MASK (0x3000U)
38294#define OCOTP_HW_OCOTP_LOCK_USB_ID_SHIFT (12U)
38295#define OCOTP_HW_OCOTP_LOCK_USB_ID(x) \
38296 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_USB_ID_SHIFT)) & OCOTP_HW_OCOTP_LOCK_USB_ID_MASK)
38297#define OCOTP_HW_OCOTP_LOCK_MAC_ADDR_MASK (0xC000U)
38298#define OCOTP_HW_OCOTP_LOCK_MAC_ADDR_SHIFT (14U)
38299#define OCOTP_HW_OCOTP_LOCK_MAC_ADDR(x) \
38300 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_MAC_ADDR_SHIFT)) & OCOTP_HW_OCOTP_LOCK_MAC_ADDR_MASK)
38301#define OCOTP_HW_OCOTP_LOCK_GP1_MASK (0x300000U)
38302#define OCOTP_HW_OCOTP_LOCK_GP1_SHIFT (20U)
38303#define OCOTP_HW_OCOTP_LOCK_GP1(x) \
38304 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_GP1_SHIFT)) & OCOTP_HW_OCOTP_LOCK_GP1_MASK)
38305#define OCOTP_HW_OCOTP_LOCK_GP2_MASK (0xC00000U)
38306#define OCOTP_HW_OCOTP_LOCK_GP2_SHIFT (22U)
38307#define OCOTP_HW_OCOTP_LOCK_GP2(x) \
38308 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_LOCK_GP2_SHIFT)) & OCOTP_HW_OCOTP_LOCK_GP2_MASK)
38309/*! @} */
38310
38311/*! @name HW_OCOTP_TESTER0 - Value of OTP Bank0 Word1 (Tester Info.) */
38312/*! @{ */
38313#define OCOTP_HW_OCOTP_TESTER0_BITS_MASK (0xFFFFFFFFU)
38314#define OCOTP_HW_OCOTP_TESTER0_BITS_SHIFT (0U)
38315#define OCOTP_HW_OCOTP_TESTER0_BITS(x) \
38316 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TESTER0_BITS_SHIFT)) & OCOTP_HW_OCOTP_TESTER0_BITS_MASK)
38317/*! @} */
38318
38319/*! @name HW_OCOTP_TESTER1 - Value of OTP Bank0 Word2 (tester Info.) */
38320/*! @{ */
38321#define OCOTP_HW_OCOTP_TESTER1_BITS_MASK (0xFFFFFFFFU)
38322#define OCOTP_HW_OCOTP_TESTER1_BITS_SHIFT (0U)
38323#define OCOTP_HW_OCOTP_TESTER1_BITS(x) \
38324 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TESTER1_BITS_SHIFT)) & OCOTP_HW_OCOTP_TESTER1_BITS_MASK)
38325/*! @} */
38326
38327/*! @name HW_OCOTP_TESTER2 - Value of OTP Bank0 Word3 (Tester Info.) */
38328/*! @{ */
38329#define OCOTP_HW_OCOTP_TESTER2_BITS_MASK (0xFFFFFFFFU)
38330#define OCOTP_HW_OCOTP_TESTER2_BITS_SHIFT (0U)
38331#define OCOTP_HW_OCOTP_TESTER2_BITS(x) \
38332 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TESTER2_BITS_SHIFT)) & OCOTP_HW_OCOTP_TESTER2_BITS_MASK)
38333/*! @} */
38334
38335/*! @name HW_OCOTP_TESTER3 - Value of OTP Bank1 Word0 (Tester Info.) */
38336/*! @{ */
38337#define OCOTP_HW_OCOTP_TESTER3_BITS_MASK (0xFFFFFFFFU)
38338#define OCOTP_HW_OCOTP_TESTER3_BITS_SHIFT (0U)
38339#define OCOTP_HW_OCOTP_TESTER3_BITS(x) \
38340 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TESTER3_BITS_SHIFT)) & OCOTP_HW_OCOTP_TESTER3_BITS_MASK)
38341/*! @} */
38342
38343/*! @name HW_OCOTP_TESTER4 - Value of OTP Bank1 Word1 (Tester Info.) */
38344/*! @{ */
38345#define OCOTP_HW_OCOTP_TESTER4_BITS_MASK (0xFFFFFFFFU)
38346#define OCOTP_HW_OCOTP_TESTER4_BITS_SHIFT (0U)
38347#define OCOTP_HW_OCOTP_TESTER4_BITS(x) \
38348 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TESTER4_BITS_SHIFT)) & OCOTP_HW_OCOTP_TESTER4_BITS_MASK)
38349/*! @} */
38350
38351/*! @name HW_OCOTP_TESTER5 - Value of OTP Bank1 Word2 (Tester Info.) */
38352/*! @{ */
38353#define OCOTP_HW_OCOTP_TESTER5_BITS_MASK (0xFFFFFFFFU)
38354#define OCOTP_HW_OCOTP_TESTER5_BITS_SHIFT (0U)
38355#define OCOTP_HW_OCOTP_TESTER5_BITS(x) \
38356 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_TESTER5_BITS_SHIFT)) & OCOTP_HW_OCOTP_TESTER5_BITS_MASK)
38357/*! @} */
38358
38359/*! @name HW_OCOTP_BOOT_CFG0 - Value of OTP Bank1 Word3 (Boot Configuration Info.) */
38360/*! @{ */
38361#define OCOTP_HW_OCOTP_BOOT_CFG0_BITS_MASK (0xFFFFFFFFU)
38362#define OCOTP_HW_OCOTP_BOOT_CFG0_BITS_SHIFT (0U)
38363#define OCOTP_HW_OCOTP_BOOT_CFG0_BITS(x) \
38364 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_BOOT_CFG0_BITS_SHIFT)) & OCOTP_HW_OCOTP_BOOT_CFG0_BITS_MASK)
38365/*! @} */
38366
38367/*! @name HW_OCOTP_BOOT_CFG1 - Value of OTP Bank2 Word0 (Boot Configuration Info.) */
38368/*! @{ */
38369#define OCOTP_HW_OCOTP_BOOT_CFG1_BITS_MASK (0xFFFFFFFFU)
38370#define OCOTP_HW_OCOTP_BOOT_CFG1_BITS_SHIFT (0U)
38371#define OCOTP_HW_OCOTP_BOOT_CFG1_BITS(x) \
38372 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_BOOT_CFG1_BITS_SHIFT)) & OCOTP_HW_OCOTP_BOOT_CFG1_BITS_MASK)
38373/*! @} */
38374
38375/*! @name HW_OCOTP_BOOT_CFG2 - Value of OTP Bank2 Word1 (Boot Configuration Info.) */
38376/*! @{ */
38377#define OCOTP_HW_OCOTP_BOOT_CFG2_BITS_MASK (0xFFFFFFFFU)
38378#define OCOTP_HW_OCOTP_BOOT_CFG2_BITS_SHIFT (0U)
38379#define OCOTP_HW_OCOTP_BOOT_CFG2_BITS(x) \
38380 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_BOOT_CFG2_BITS_SHIFT)) & OCOTP_HW_OCOTP_BOOT_CFG2_BITS_MASK)
38381/*! @} */
38382
38383/*! @name HW_OCOTP_BOOT_CFG3 - Value of OTP Bank2 Word2 (Boot Configuration Info.) */
38384/*! @{ */
38385#define OCOTP_HW_OCOTP_BOOT_CFG3_BITS_MASK (0xFFFFFFFFU)
38386#define OCOTP_HW_OCOTP_BOOT_CFG3_BITS_SHIFT (0U)
38387#define OCOTP_HW_OCOTP_BOOT_CFG3_BITS(x) \
38388 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_BOOT_CFG3_BITS_SHIFT)) & OCOTP_HW_OCOTP_BOOT_CFG3_BITS_MASK)
38389/*! @} */
38390
38391/*! @name HW_OCOTP_BOOT_CFG4 - Value of OTP Bank2 Word3 (BOOT Configuration Info.) */
38392/*! @{ */
38393#define OCOTP_HW_OCOTP_BOOT_CFG4_BITS_MASK (0xFFFFFFFFU)
38394#define OCOTP_HW_OCOTP_BOOT_CFG4_BITS_SHIFT (0U)
38395#define OCOTP_HW_OCOTP_BOOT_CFG4_BITS(x) \
38396 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_BOOT_CFG4_BITS_SHIFT)) & OCOTP_HW_OCOTP_BOOT_CFG4_BITS_MASK)
38397/*! @} */
38398
38399/*! @name HW_OCOTP_MEM_TRIM0 - Value of OTP Bank3 Word0 (Memory Related Info.) */
38400/*! @{ */
38401#define OCOTP_HW_OCOTP_MEM_TRIM0_BITS_MASK (0xFFFFFFFFU)
38402#define OCOTP_HW_OCOTP_MEM_TRIM0_BITS_SHIFT (0U)
38403#define OCOTP_HW_OCOTP_MEM_TRIM0_BITS(x) \
38404 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MEM_TRIM0_BITS_SHIFT)) & OCOTP_HW_OCOTP_MEM_TRIM0_BITS_MASK)
38405/*! @} */
38406
38407/*! @name HW_OCOTP_MEM_TRIM1 - Value of OTP Bank3 Word1 (Memory Related Info.) */
38408/*! @{ */
38409#define OCOTP_HW_OCOTP_MEM_TRIM1_BITS_MASK (0xFFFFFFFFU)
38410#define OCOTP_HW_OCOTP_MEM_TRIM1_BITS_SHIFT (0U)
38411#define OCOTP_HW_OCOTP_MEM_TRIM1_BITS(x) \
38412 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MEM_TRIM1_BITS_SHIFT)) & OCOTP_HW_OCOTP_MEM_TRIM1_BITS_MASK)
38413/*! @} */
38414
38415/*! @name HW_OCOTP_ANA0 - Value of OTP Bank3 Word2 (Analog Info.) */
38416/*! @{ */
38417#define OCOTP_HW_OCOTP_ANA0_BITS_MASK (0xFFFFFFFFU)
38418#define OCOTP_HW_OCOTP_ANA0_BITS_SHIFT (0U)
38419#define OCOTP_HW_OCOTP_ANA0_BITS(x) \
38420 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_ANA0_BITS_SHIFT)) & OCOTP_HW_OCOTP_ANA0_BITS_MASK)
38421/*! @} */
38422
38423/*! @name HW_OCOTP_ANA1 - Value of OTP Bank3 Word3 (Analog Info.) */
38424/*! @{ */
38425#define OCOTP_HW_OCOTP_ANA1_BITS_MASK (0xFFFFFFFFU)
38426#define OCOTP_HW_OCOTP_ANA1_BITS_SHIFT (0U)
38427#define OCOTP_HW_OCOTP_ANA1_BITS(x) \
38428 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_ANA1_BITS_SHIFT)) & OCOTP_HW_OCOTP_ANA1_BITS_MASK)
38429/*! @} */
38430
38431/*! @name HW_OCOTP_SRK0 - Shadow Register for OTP Bank6 Word0 (SRK Hash) */
38432/*! @{ */
38433#define OCOTP_HW_OCOTP_SRK0_BITS_MASK (0xFFFFFFFFU)
38434#define OCOTP_HW_OCOTP_SRK0_BITS_SHIFT (0U)
38435#define OCOTP_HW_OCOTP_SRK0_BITS(x) \
38436 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SRK0_BITS_SHIFT)) & OCOTP_HW_OCOTP_SRK0_BITS_MASK)
38437/*! @} */
38438
38439/*! @name HW_OCOTP_SRK1 - Shadow Register for OTP Bank6 Word1 (SRK Hash) */
38440/*! @{ */
38441#define OCOTP_HW_OCOTP_SRK1_BITS_MASK (0xFFFFFFFFU)
38442#define OCOTP_HW_OCOTP_SRK1_BITS_SHIFT (0U)
38443#define OCOTP_HW_OCOTP_SRK1_BITS(x) \
38444 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SRK1_BITS_SHIFT)) & OCOTP_HW_OCOTP_SRK1_BITS_MASK)
38445/*! @} */
38446
38447/*! @name HW_OCOTP_SRK2 - Shadow Register for OTP Bank6 Word2 (SRK Hash) */
38448/*! @{ */
38449#define OCOTP_HW_OCOTP_SRK2_BITS_MASK (0xFFFFFFFFU)
38450#define OCOTP_HW_OCOTP_SRK2_BITS_SHIFT (0U)
38451#define OCOTP_HW_OCOTP_SRK2_BITS(x) \
38452 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SRK2_BITS_SHIFT)) & OCOTP_HW_OCOTP_SRK2_BITS_MASK)
38453/*! @} */
38454
38455/*! @name HW_OCOTP_SRK3 - Shadow Register for OTP Bank6 Word3 (SRK Hash) */
38456/*! @{ */
38457#define OCOTP_HW_OCOTP_SRK3_BITS_MASK (0xFFFFFFFFU)
38458#define OCOTP_HW_OCOTP_SRK3_BITS_SHIFT (0U)
38459#define OCOTP_HW_OCOTP_SRK3_BITS(x) \
38460 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SRK3_BITS_SHIFT)) & OCOTP_HW_OCOTP_SRK3_BITS_MASK)
38461/*! @} */
38462
38463/*! @name HW_OCOTP_SRK4 - Shadow Register for OTP Bank7 Word0 (SRK Hash) */
38464/*! @{ */
38465#define OCOTP_HW_OCOTP_SRK4_BITS_MASK (0xFFFFFFFFU)
38466#define OCOTP_HW_OCOTP_SRK4_BITS_SHIFT (0U)
38467#define OCOTP_HW_OCOTP_SRK4_BITS(x) \
38468 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SRK4_BITS_SHIFT)) & OCOTP_HW_OCOTP_SRK4_BITS_MASK)
38469/*! @} */
38470
38471/*! @name HW_OCOTP_SRK5 - Shadow Register for OTP Bank7 Word1 (SRK Hash) */
38472/*! @{ */
38473#define OCOTP_HW_OCOTP_SRK5_BITS_MASK (0xFFFFFFFFU)
38474#define OCOTP_HW_OCOTP_SRK5_BITS_SHIFT (0U)
38475#define OCOTP_HW_OCOTP_SRK5_BITS(x) \
38476 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SRK5_BITS_SHIFT)) & OCOTP_HW_OCOTP_SRK5_BITS_MASK)
38477/*! @} */
38478
38479/*! @name HW_OCOTP_SRK6 - Shadow Register for OTP Bank7 Word2 (SRK Hash) */
38480/*! @{ */
38481#define OCOTP_HW_OCOTP_SRK6_BITS_MASK (0xFFFFFFFFU)
38482#define OCOTP_HW_OCOTP_SRK6_BITS_SHIFT (0U)
38483#define OCOTP_HW_OCOTP_SRK6_BITS(x) \
38484 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SRK6_BITS_SHIFT)) & OCOTP_HW_OCOTP_SRK6_BITS_MASK)
38485/*! @} */
38486
38487/*! @name HW_OCOTP_SRK7 - Shadow Register for OTP Bank7 Word3 (SRK Hash) */
38488/*! @{ */
38489#define OCOTP_HW_OCOTP_SRK7_BITS_MASK (0xFFFFFFFFU)
38490#define OCOTP_HW_OCOTP_SRK7_BITS_SHIFT (0U)
38491#define OCOTP_HW_OCOTP_SRK7_BITS(x) \
38492 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SRK7_BITS_SHIFT)) & OCOTP_HW_OCOTP_SRK7_BITS_MASK)
38493/*! @} */
38494
38495/*! @name HW_OCOTP_SJC_RESP0 - Value of OTP Bank8 Word0 (Secure JTAG Response Field) */
38496/*! @{ */
38497#define OCOTP_HW_OCOTP_SJC_RESP0_BITS_MASK (0xFFFFFFFFU)
38498#define OCOTP_HW_OCOTP_SJC_RESP0_BITS_SHIFT (0U)
38499#define OCOTP_HW_OCOTP_SJC_RESP0_BITS(x) \
38500 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SJC_RESP0_BITS_SHIFT)) & OCOTP_HW_OCOTP_SJC_RESP0_BITS_MASK)
38501/*! @} */
38502
38503/*! @name HW_OCOTP_SJC_RESP1 - Value of OTP Bank8 Word1 (Secure JTAG Response Field) */
38504/*! @{ */
38505#define OCOTP_HW_OCOTP_SJC_RESP1_BITS_MASK (0xFFFFFFFFU)
38506#define OCOTP_HW_OCOTP_SJC_RESP1_BITS_SHIFT (0U)
38507#define OCOTP_HW_OCOTP_SJC_RESP1_BITS(x) \
38508 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SJC_RESP1_BITS_SHIFT)) & OCOTP_HW_OCOTP_SJC_RESP1_BITS_MASK)
38509/*! @} */
38510
38511/*! @name HW_OCOTP_USB_ID - Value of OTP Bank8 Word2 (USB ID info) */
38512/*! @{ */
38513#define OCOTP_HW_OCOTP_USB_ID_BITS_MASK (0xFFFFFFFFU)
38514#define OCOTP_HW_OCOTP_USB_ID_BITS_SHIFT (0U)
38515#define OCOTP_HW_OCOTP_USB_ID_BITS(x) \
38516 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_USB_ID_BITS_SHIFT)) & OCOTP_HW_OCOTP_USB_ID_BITS_MASK)
38517/*! @} */
38518
38519/*! @name HW_OCOTP_FIELD_RETURN - Value of OTP Bank5 Word6 (Field Return) */
38520/*! @{ */
38521#define OCOTP_HW_OCOTP_FIELD_RETURN_BITS_MASK (0xFFFFFFFFU)
38522#define OCOTP_HW_OCOTP_FIELD_RETURN_BITS_SHIFT (0U)
38523#define OCOTP_HW_OCOTP_FIELD_RETURN_BITS(x) \
38524 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_FIELD_RETURN_BITS_SHIFT)) & OCOTP_HW_OCOTP_FIELD_RETURN_BITS_MASK)
38525/*! @} */
38526
38527/*! @name HW_OCOTP_MAC_ADDR0 - Value of OTP Bank9 Word0 (MAC Address) */
38528/*! @{ */
38529#define OCOTP_HW_OCOTP_MAC_ADDR0_BITS_MASK (0xFFFFFFFFU)
38530#define OCOTP_HW_OCOTP_MAC_ADDR0_BITS_SHIFT (0U)
38531#define OCOTP_HW_OCOTP_MAC_ADDR0_BITS(x) \
38532 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAC_ADDR0_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAC_ADDR0_BITS_MASK)
38533/*! @} */
38534
38535/*! @name HW_OCOTP_MAC_ADDR1 - Value of OTP Bank9 Word1 (MAC Address) */
38536/*! @{ */
38537#define OCOTP_HW_OCOTP_MAC_ADDR1_BITS_MASK (0xFFFFFFFFU)
38538#define OCOTP_HW_OCOTP_MAC_ADDR1_BITS_SHIFT (0U)
38539#define OCOTP_HW_OCOTP_MAC_ADDR1_BITS(x) \
38540 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAC_ADDR1_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAC_ADDR1_BITS_MASK)
38541/*! @} */
38542
38543/*! @name HW_OCOTP_MAC_ADDR2 - Value of OTP Bank9 Word2 (MAC Address) */
38544/*! @{ */
38545#define OCOTP_HW_OCOTP_MAC_ADDR2_BITS_MASK (0xFFFFFFFFU)
38546#define OCOTP_HW_OCOTP_MAC_ADDR2_BITS_SHIFT (0U)
38547#define OCOTP_HW_OCOTP_MAC_ADDR2_BITS(x) \
38548 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAC_ADDR2_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAC_ADDR2_BITS_MASK)
38549/*! @} */
38550
38551/*! @name HW_OCOTP_SRK_REVOKE - Value of OTP Bank9 Word3 (SRK Revoke) */
38552/*! @{ */
38553#define OCOTP_HW_OCOTP_SRK_REVOKE_BITS_MASK (0xFFFFFFFFU)
38554#define OCOTP_HW_OCOTP_SRK_REVOKE_BITS_SHIFT (0U)
38555#define OCOTP_HW_OCOTP_SRK_REVOKE_BITS(x) \
38556 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_SRK_REVOKE_BITS_SHIFT)) & OCOTP_HW_OCOTP_SRK_REVOKE_BITS_MASK)
38557/*! @} */
38558
38559/*! @name HW_OCOTP_MAU_KEY0 - Shadow Register for OTP Bank10 Word0 (MAU Key) */
38560/*! @{ */
38561#define OCOTP_HW_OCOTP_MAU_KEY0_BITS_MASK (0xFFFFFFFFU)
38562#define OCOTP_HW_OCOTP_MAU_KEY0_BITS_SHIFT (0U)
38563#define OCOTP_HW_OCOTP_MAU_KEY0_BITS(x) \
38564 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAU_KEY0_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAU_KEY0_BITS_MASK)
38565/*! @} */
38566
38567/*! @name HW_OCOTP_MAU_KEY1 - Shadow Register for OTP Bank10 Word1 (MAU Key) */
38568/*! @{ */
38569#define OCOTP_HW_OCOTP_MAU_KEY1_BITS_MASK (0xFFFFFFFFU)
38570#define OCOTP_HW_OCOTP_MAU_KEY1_BITS_SHIFT (0U)
38571#define OCOTP_HW_OCOTP_MAU_KEY1_BITS(x) \
38572 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAU_KEY1_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAU_KEY1_BITS_MASK)
38573/*! @} */
38574
38575/*! @name HW_OCOTP_MAU_KEY2 - Shadow Register for OTP Bank10 Word2 (MAU Key) */
38576/*! @{ */
38577#define OCOTP_HW_OCOTP_MAU_KEY2_BITS_MASK (0xFFFFFFFFU)
38578#define OCOTP_HW_OCOTP_MAU_KEY2_BITS_SHIFT (0U)
38579#define OCOTP_HW_OCOTP_MAU_KEY2_BITS(x) \
38580 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAU_KEY2_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAU_KEY2_BITS_MASK)
38581/*! @} */
38582
38583/*! @name HW_OCOTP_MAU_KEY3 - Shadow Register for OTP Bank10 Word3 (MAU Key) */
38584/*! @{ */
38585#define OCOTP_HW_OCOTP_MAU_KEY3_BITS_MASK (0xFFFFFFFFU)
38586#define OCOTP_HW_OCOTP_MAU_KEY3_BITS_SHIFT (0U)
38587#define OCOTP_HW_OCOTP_MAU_KEY3_BITS(x) \
38588 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAU_KEY3_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAU_KEY3_BITS_MASK)
38589/*! @} */
38590
38591/*! @name HW_OCOTP_MAU_KEY4 - Shadow Register for OTP Bank11 Word0 (MAU Key) */
38592/*! @{ */
38593#define OCOTP_HW_OCOTP_MAU_KEY4_BITS_MASK (0xFFFFFFFFU)
38594#define OCOTP_HW_OCOTP_MAU_KEY4_BITS_SHIFT (0U)
38595#define OCOTP_HW_OCOTP_MAU_KEY4_BITS(x) \
38596 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAU_KEY4_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAU_KEY4_BITS_MASK)
38597/*! @} */
38598
38599/*! @name HW_OCOTP_MAU_KEY5 - Shadow Register for OTP Bank11 Word1 (MAU Key) */
38600/*! @{ */
38601#define OCOTP_HW_OCOTP_MAU_KEY5_BITS_MASK (0xFFFFFFFFU)
38602#define OCOTP_HW_OCOTP_MAU_KEY5_BITS_SHIFT (0U)
38603#define OCOTP_HW_OCOTP_MAU_KEY5_BITS(x) \
38604 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAU_KEY5_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAU_KEY5_BITS_MASK)
38605/*! @} */
38606
38607/*! @name HW_OCOTP_MAU_KEY6 - Shadow Register for OTP Bank11 Word2 (MAU Key) */
38608/*! @{ */
38609#define OCOTP_HW_OCOTP_MAU_KEY6_BITS_MASK (0xFFFFFFFFU)
38610#define OCOTP_HW_OCOTP_MAU_KEY6_BITS_SHIFT (0U)
38611#define OCOTP_HW_OCOTP_MAU_KEY6_BITS(x) \
38612 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAU_KEY6_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAU_KEY6_BITS_MASK)
38613/*! @} */
38614
38615/*! @name HW_OCOTP_MAU_KEY7 - Shadow Register for OTP Bank11 Word3 (MAU Key) */
38616/*! @{ */
38617#define OCOTP_HW_OCOTP_MAU_KEY7_BITS_MASK (0xFFFFFFFFU)
38618#define OCOTP_HW_OCOTP_MAU_KEY7_BITS_SHIFT (0U)
38619#define OCOTP_HW_OCOTP_MAU_KEY7_BITS(x) \
38620 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_MAU_KEY7_BITS_SHIFT)) & OCOTP_HW_OCOTP_MAU_KEY7_BITS_MASK)
38621/*! @} */
38622
38623/*! @name HW_OCOTP_GP10 - Value of OTP Bank14 Word0 () */
38624/*! @{ */
38625#define OCOTP_HW_OCOTP_GP10_BITS_MASK (0xFFFFFFFFU)
38626#define OCOTP_HW_OCOTP_GP10_BITS_SHIFT (0U)
38627#define OCOTP_HW_OCOTP_GP10_BITS(x) \
38628 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_GP10_BITS_SHIFT)) & OCOTP_HW_OCOTP_GP10_BITS_MASK)
38629/*! @} */
38630
38631/*! @name HW_OCOTP_GP11 - Value of OTP Bank14 Word1 () */
38632/*! @{ */
38633#define OCOTP_HW_OCOTP_GP11_BITS_MASK (0xFFFFFFFFU)
38634#define OCOTP_HW_OCOTP_GP11_BITS_SHIFT (0U)
38635#define OCOTP_HW_OCOTP_GP11_BITS(x) \
38636 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_GP11_BITS_SHIFT)) & OCOTP_HW_OCOTP_GP11_BITS_MASK)
38637/*! @} */
38638
38639/*! @name HW_OCOTP_GP20 - Value of OTP Bank14 Word2 () */
38640/*! @{ */
38641#define OCOTP_HW_OCOTP_GP20_BITS_MASK (0xFFFFFFFFU)
38642#define OCOTP_HW_OCOTP_GP20_BITS_SHIFT (0U)
38643#define OCOTP_HW_OCOTP_GP20_BITS(x) \
38644 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_GP20_BITS_SHIFT)) & OCOTP_HW_OCOTP_GP20_BITS_MASK)
38645/*! @} */
38646
38647/*! @name HW_OCOTP_GP21 - Value of OTP Bank14 Word3 () */
38648/*! @{ */
38649#define OCOTP_HW_OCOTP_GP21_BITS_MASK (0xFFFFFFFFU)
38650#define OCOTP_HW_OCOTP_GP21_BITS_SHIFT (0U)
38651#define OCOTP_HW_OCOTP_GP21_BITS(x) \
38652 (((uint32_t)(((uint32_t)(x)) << OCOTP_HW_OCOTP_GP21_BITS_SHIFT)) & OCOTP_HW_OCOTP_GP21_BITS_MASK)
38653/*! @} */
38654
38655/*!
38656 * @}
38657 */ /* end of group OCOTP_Register_Masks */
38658
38659/* OCOTP - Peripheral instance base addresses */
38660/** Peripheral OCOTP base address */
38661#define OCOTP_BASE (0x30350000u)
38662/** Peripheral OCOTP base pointer */
38663#define OCOTP ((OCOTP_Type *)OCOTP_BASE)
38664/** Array initializer of OCOTP peripheral base addresses */
38665#define OCOTP_BASE_ADDRS \
38666 { \
38667 OCOTP_BASE \
38668 }
38669/** Array initializer of OCOTP peripheral base pointers */
38670#define OCOTP_BASE_PTRS \
38671 { \
38672 OCOTP \
38673 }
38674
38675/*!
38676 * @}
38677 */ /* end of group OCOTP_Peripheral_Access_Layer */
38678
38679/* ----------------------------------------------------------------------------
38680 -- PDM Peripheral Access Layer
38681 ---------------------------------------------------------------------------- */
38682
38683/*!
38684 * @addtogroup PDM_Peripheral_Access_Layer PDM Peripheral Access Layer
38685 * @{
38686 */
38687
38688/** PDM - Register Layout Typedef */
38689typedef struct
38690{
38691 __IO uint32_t CTRL_1; /**< MICFIL Control register 1, offset: 0x0 */
38692 __IO uint32_t CTRL_2; /**< MICFIL Control register 2, offset: 0x4 */
38693 __IO uint32_t STAT; /**< MICFIL Status register, offset: 0x8 */
38694 uint8_t RESERVED_0[4];
38695 __IO uint32_t FIFO_CTRL; /**< MICFIL FIFO Control register, offset: 0x10 */
38696 __IO uint32_t FIFO_STAT; /**< MICFIL FIFO Status register, offset: 0x14 */
38697 uint8_t RESERVED_1[12];
38698 __I uint32_t DATACH[8]; /**< MICFIL Output Result Register, array offset: 0x24, array step: 0x4 */
38699 uint8_t RESERVED_2[32];
38700 __IO uint32_t DC_CTRL; /**< MICFIL DC Remover Control register, offset: 0x64 */
38701 uint8_t RESERVED_3[12];
38702 __IO uint32_t OUT_CTRL; /**< MICFIL Output Control register, offset: 0x74 */
38703 uint8_t RESERVED_4[4];
38704 __IO uint32_t OUT_STAT; /**< MICFIL Output Status register, offset: 0x7C */
38705 uint8_t RESERVED_5[16];
38706 __IO uint32_t VAD0_CTRL_1; /**< Voice Activity Detector 0 Control register, offset: 0x90 */
38707 __IO uint32_t VAD0_CTRL_2; /**< Voice Activity Detector 0 Control register, offset: 0x94 */
38708 __IO uint32_t VAD0_STAT; /**< Voice Activity Detector 0 Status register, offset: 0x98 */
38709 __IO uint32_t VAD0_SCONFIG; /**< Voice Activity Detector 0 Signal Configuration, offset: 0x9C */
38710 __IO uint32_t VAD0_NCONFIG; /**< Voice Activity Detector 0 Noise Configuration, offset: 0xA0 */
38711 __I uint32_t VAD0_NDATA; /**< Voice Activity Detector 0 Noise Data, offset: 0xA4 */
38712 __IO uint32_t VAD0_ZCD; /**< Voice Activity Detector 0 Zero-Crossing Detector, offset: 0xA8 */
38713} PDM_Type;
38714
38715/* ----------------------------------------------------------------------------
38716 -- PDM Register Masks
38717 ---------------------------------------------------------------------------- */
38718
38719/*!
38720 * @addtogroup PDM_Register_Masks PDM Register Masks
38721 * @{
38722 */
38723
38724/*! @name CTRL_1 - MICFIL Control register 1 */
38725/*! @{ */
38726#define PDM_CTRL_1_CH0EN_MASK (0x1U)
38727#define PDM_CTRL_1_CH0EN_SHIFT (0U)
38728/*! CH0EN - Channel 0 Enable
38729 * 0b0..Channel 0 disabled
38730 * 0b1..Channel 0 enabled
38731 */
38732#define PDM_CTRL_1_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK)
38733#define PDM_CTRL_1_CH1EN_MASK (0x2U)
38734#define PDM_CTRL_1_CH1EN_SHIFT (1U)
38735/*! CH1EN - Channel 1 Enable
38736 * 0b0..Channel 1 disabled
38737 * 0b1..Channel 1 enabled
38738 */
38739#define PDM_CTRL_1_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK)
38740#define PDM_CTRL_1_CH2EN_MASK (0x4U)
38741#define PDM_CTRL_1_CH2EN_SHIFT (2U)
38742/*! CH2EN - Channel 2 Enable
38743 * 0b0..Channel 2 enabled
38744 * 0b1..Channel 2 disabled
38745 */
38746#define PDM_CTRL_1_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK)
38747#define PDM_CTRL_1_CH3EN_MASK (0x8U)
38748#define PDM_CTRL_1_CH3EN_SHIFT (3U)
38749/*! CH3EN - Channel 3 Enable
38750 * 0b0..Channel 3 disabled
38751 * 0b1..Channel 3 enabled
38752 */
38753#define PDM_CTRL_1_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK)
38754#define PDM_CTRL_1_CH4EN_MASK (0x10U)
38755#define PDM_CTRL_1_CH4EN_SHIFT (4U)
38756/*! CH4EN - Channel 4 Enable
38757 * 0b0..Channel 4 disabled
38758 * 0b1..Channel 4 enabled
38759 */
38760#define PDM_CTRL_1_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK)
38761#define PDM_CTRL_1_CH5EN_MASK (0x20U)
38762#define PDM_CTRL_1_CH5EN_SHIFT (5U)
38763/*! CH5EN - Channel 5 Enable
38764 * 0b0..Channel 5 disabled
38765 * 0b1..Channel 5 enabled
38766 */
38767#define PDM_CTRL_1_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK)
38768#define PDM_CTRL_1_CH6EN_MASK (0x40U)
38769#define PDM_CTRL_1_CH6EN_SHIFT (6U)
38770/*! CH6EN - Channel 6 Enable
38771 * 0b0..Channel 6 disabled
38772 * 0b1..Channel 6 enabled
38773 */
38774#define PDM_CTRL_1_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK)
38775#define PDM_CTRL_1_CH7EN_MASK (0x80U)
38776#define PDM_CTRL_1_CH7EN_SHIFT (7U)
38777/*! CH7EN - Channel 7 Enable
38778 * 0b0..Channel 7 disabled
38779 * 0b1..Channel 7 enabled
38780 */
38781#define PDM_CTRL_1_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK)
38782#define PDM_CTRL_1_ERREN_MASK (0x800000U)
38783#define PDM_CTRL_1_ERREN_SHIFT (23U)
38784/*! ERREN - Error Interruption Enable
38785 * 0b0..Error Interrupts disabled
38786 * 0b1..Error Interrupts enabled
38787 */
38788#define PDM_CTRL_1_ERREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK)
38789#define PDM_CTRL_1_DISEL_MASK (0x3000000U)
38790#define PDM_CTRL_1_DISEL_SHIFT (24U)
38791/*! DISEL - DMA Interrupt Selection
38792 * 0b00..DMA and interrupt requests disabled
38793 * 0b01..DMA requests enabled
38794 * 0b10..Interrupt requests enabled
38795 * 0b11..Reserved
38796 */
38797#define PDM_CTRL_1_DISEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK)
38798#define PDM_CTRL_1_DBGE_MASK (0x4000000U)
38799#define PDM_CTRL_1_DBGE_SHIFT (26U)
38800/*! DBGE - Module Enable in Debug
38801 * 0b0..PDM Interface is disabled in debug mode, after completing the current frame.
38802 * 0b1..PDM Interface is enabled in debug mode.
38803 */
38804#define PDM_CTRL_1_DBGE(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK)
38805#define PDM_CTRL_1_SRES_MASK (0x8000000U)
38806#define PDM_CTRL_1_SRES_SHIFT (27U)
38807/*! SRES - Software-reset bit
38808 * 0b0..No action
38809 * 0b1..Software reset
38810 */
38811#define PDM_CTRL_1_SRES(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK)
38812#define PDM_CTRL_1_DBG_MASK (0x10000000U)
38813#define PDM_CTRL_1_DBG_SHIFT (28U)
38814/*! DBG - Debug Mode
38815 * 0b0..PDM Interface is in Normal Mode.
38816 * 0b1..PDM Interface is in Debug Mode.
38817 */
38818#define PDM_CTRL_1_DBG(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK)
38819#define PDM_CTRL_1_PDMIEN_MASK (0x20000000U)
38820#define PDM_CTRL_1_PDMIEN_SHIFT (29U)
38821/*! PDMIEN - PDM Inteface Enable
38822 * 0b0..PDM Interface disabled
38823 * 0b1..PDM Interface enabled.
38824 */
38825#define PDM_CTRL_1_PDMIEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK)
38826#define PDM_CTRL_1_DOZEN_MASK (0x40000000U)
38827#define PDM_CTRL_1_DOZEN_SHIFT (30U)
38828/*! DOZEN - DOZE enable
38829 * 0b0..DOZE enable bit is not asserted
38830 * 0b1..DOZE enable bit is asserted
38831 */
38832#define PDM_CTRL_1_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK)
38833#define PDM_CTRL_1_MDIS_MASK (0x80000000U)
38834#define PDM_CTRL_1_MDIS_SHIFT (31U)
38835/*! MDIS - Module Disable
38836 * 0b0..Normal Mode
38837 * 0b1..Disable/Low Leakage Mode
38838 */
38839#define PDM_CTRL_1_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK)
38840/*! @} */
38841
38842/*! @name CTRL_2 - MICFIL Control register 2 */
38843/*! @{ */
38844#define PDM_CTRL_2_CLKDIV_MASK (0xFFU)
38845#define PDM_CTRL_2_CLKDIV_SHIFT (0U)
38846#define PDM_CTRL_2_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK)
38847#define PDM_CTRL_2_CICOSR_MASK (0xF0000U)
38848#define PDM_CTRL_2_CICOSR_SHIFT (16U)
38849#define PDM_CTRL_2_CICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK)
38850#define PDM_CTRL_2_QSEL_MASK (0xE000000U)
38851#define PDM_CTRL_2_QSEL_SHIFT (25U)
38852/*! QSEL - Quality Select
38853 * 0b001..High quality mode.
38854 * 0b000..Medium quality mode.
38855 * 0b111..Low quality mode.
38856 * 0b110..Very low quality 0 mode.
38857 * 0b101..Very low quality 1 mode.
38858 * 0b100..Very low quality 2 mode.
38859 */
38860#define PDM_CTRL_2_QSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK)
38861/*! @} */
38862
38863/*! @name STAT - MICFIL Status register */
38864/*! @{ */
38865#define PDM_STAT_CH0F_MASK (0x1U)
38866#define PDM_STAT_CH0F_SHIFT (0U)
38867/*! CH0F - Channel 0 Output Data Flag
38868 * 0b0..Chanel's FIFO did not reach the number of elements configured in watermark bit-field.
38869 * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
38870 */
38871#define PDM_STAT_CH0F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK)
38872#define PDM_STAT_CH1F_MASK (0x2U)
38873#define PDM_STAT_CH1F_SHIFT (1U)
38874/*! CH1F - Channel 1 Output Data Flag
38875 * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
38876 * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
38877 */
38878#define PDM_STAT_CH1F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK)
38879#define PDM_STAT_CH2F_MASK (0x4U)
38880#define PDM_STAT_CH2F_SHIFT (2U)
38881/*! CH2F - Channel 2 Output Data Flag
38882 * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
38883 * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
38884 */
38885#define PDM_STAT_CH2F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK)
38886#define PDM_STAT_CH3F_MASK (0x8U)
38887#define PDM_STAT_CH3F_SHIFT (3U)
38888/*! CH3F - Channel 3 Output Data Flag
38889 * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
38890 * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
38891 */
38892#define PDM_STAT_CH3F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK)
38893#define PDM_STAT_CH4F_MASK (0x10U)
38894#define PDM_STAT_CH4F_SHIFT (4U)
38895/*! CH4F - Channel 4 Output Data Flag
38896 * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
38897 * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
38898 */
38899#define PDM_STAT_CH4F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK)
38900#define PDM_STAT_CH5F_MASK (0x20U)
38901#define PDM_STAT_CH5F_SHIFT (5U)
38902/*! CH5F - Channel 5 Output Data Flag
38903 * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
38904 * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
38905 */
38906#define PDM_STAT_CH5F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK)
38907#define PDM_STAT_CH6F_MASK (0x40U)
38908#define PDM_STAT_CH6F_SHIFT (6U)
38909/*! CH6F - Channel 6 Output Data Flag
38910 * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
38911 * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
38912 */
38913#define PDM_STAT_CH6F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK)
38914#define PDM_STAT_CH7F_MASK (0x80U)
38915#define PDM_STAT_CH7F_SHIFT (7U)
38916/*! CH7F - Channel 7 Output Data Flag
38917 * 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field.
38918 * 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field.
38919 */
38920#define PDM_STAT_CH7F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK)
38921#define PDM_STAT_LOWFREQF_MASK (0x20000000U)
38922#define PDM_STAT_LOWFREQF_SHIFT (29U)
38923/*! LOWFREQF - Low Frequency Flag
38924 * 0b0..CLKDIV value is OK.
38925 * 0b1..CLKDIV value is too low.
38926 */
38927#define PDM_STAT_LOWFREQF(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_LOWFREQF_SHIFT)) & PDM_STAT_LOWFREQF_MASK)
38928#define PDM_STAT_FIR_RDY_MASK (0x40000000U)
38929#define PDM_STAT_FIR_RDY_SHIFT (30U)
38930/*! FIR_RDY - FIR Filter Data Ready
38931 * 0b0..FIR Filter data not reliable.
38932 * 0b1..FIR Filter data reliable.
38933 */
38934#define PDM_STAT_FIR_RDY(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_FIR_RDY_SHIFT)) & PDM_STAT_FIR_RDY_MASK)
38935#define PDM_STAT_BSY_FIL_MASK (0x80000000U)
38936#define PDM_STAT_BSY_FIL_SHIFT (31U)
38937/*! BSY_FIL - Decimation Filter Busy Flag
38938 * 0b1..At least one Decimation Filter channel is running.
38939 * 0b0..All Decimation Filters are stopped.
38940 */
38941#define PDM_STAT_BSY_FIL(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK)
38942/*! @} */
38943
38944/*! @name FIFO_CTRL - MICFIL FIFO Control register */
38945/*! @{ */
38946#define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U)
38947#define PDM_FIFO_CTRL_FIFOWMK_SHIFT (0U)
38948#define PDM_FIFO_CTRL_FIFOWMK(x) \
38949 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
38950/*! @} */
38951
38952/*! @name FIFO_STAT - MICFIL FIFO Status register */
38953/*! @{ */
38954#define PDM_FIFO_STAT_FIFOOVF0_MASK (0x1U)
38955#define PDM_FIFO_STAT_FIFOOVF0_SHIFT (0U)
38956/*! FIFOOVF0 - FIFO Overflow Exception flag for channel 0
38957 * 0b0..No exception by FIFO overflow
38958 * 0b1..Exception by FIFO overflow
38959 */
38960#define PDM_FIFO_STAT_FIFOOVF0(x) \
38961 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK)
38962#define PDM_FIFO_STAT_FIFOOVF1_MASK (0x2U)
38963#define PDM_FIFO_STAT_FIFOOVF1_SHIFT (1U)
38964/*! FIFOOVF1 - FIFO Overflow Exception flag for channel 1
38965 * 0b0..No exception by FIFO overflow
38966 * 0b1..Exception by FIFO overflow
38967 */
38968#define PDM_FIFO_STAT_FIFOOVF1(x) \
38969 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK)
38970#define PDM_FIFO_STAT_FIFOOVF2_MASK (0x4U)
38971#define PDM_FIFO_STAT_FIFOOVF2_SHIFT (2U)
38972/*! FIFOOVF2 - FIFO Overflow Exception flag for channel 2
38973 * 0b0..No exception by FIFO overflow
38974 * 0b1..Exception by FIFO overflow
38975 */
38976#define PDM_FIFO_STAT_FIFOOVF2(x) \
38977 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK)
38978#define PDM_FIFO_STAT_FIFOOVF3_MASK (0x8U)
38979#define PDM_FIFO_STAT_FIFOOVF3_SHIFT (3U)
38980/*! FIFOOVF3 - FIFO Overflow Exception flag for channel 3
38981 * 0b0..No exception by FIFO overflow
38982 * 0b1..Exception by FIFO overflow
38983 */
38984#define PDM_FIFO_STAT_FIFOOVF3(x) \
38985 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK)
38986#define PDM_FIFO_STAT_FIFOOVF4_MASK (0x10U)
38987#define PDM_FIFO_STAT_FIFOOVF4_SHIFT (4U)
38988/*! FIFOOVF4 - FIFO Overflow Exception flag for channel 4
38989 * 0b0..No exception by FIFO overflow
38990 * 0b1..Exception by FIFO overflow
38991 */
38992#define PDM_FIFO_STAT_FIFOOVF4(x) \
38993 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK)
38994#define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U)
38995#define PDM_FIFO_STAT_FIFOOVF5_SHIFT (5U)
38996/*! FIFOOVF5 - FIFO Overflow Exception flag for channel 5
38997 * 0b0..No exception by FIFO overflow
38998 * 0b1..Exception by FIFO overflow
38999 */
39000#define PDM_FIFO_STAT_FIFOOVF5(x) \
39001 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
39002#define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U)
39003#define PDM_FIFO_STAT_FIFOOVF6_SHIFT (6U)
39004/*! FIFOOVF6 - FIFO Overflow Exception flag for channel 6
39005 * 0b0..No exception by FIFO overflow
39006 * 0b1..Exception by FIFO overflow
39007 */
39008#define PDM_FIFO_STAT_FIFOOVF6(x) \
39009 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
39010#define PDM_FIFO_STAT_FIFOOVF7_MASK (0x80U)
39011#define PDM_FIFO_STAT_FIFOOVF7_SHIFT (7U)
39012/*! FIFOOVF7 - FIFO Overflow Exception flag for channel 7
39013 * 0b0..No exception by FIFO overflow
39014 * 0b1..Exception by FIFO overflow
39015 */
39016#define PDM_FIFO_STAT_FIFOOVF7(x) \
39017 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK)
39018#define PDM_FIFO_STAT_FIFOUND0_MASK (0x100U)
39019#define PDM_FIFO_STAT_FIFOUND0_SHIFT (8U)
39020/*! FIFOUND0 - FIFO Underflow Exception flag for channel 0
39021 * 0b0..No exception by FIFO Underflow
39022 * 0b1..Exception by FIFO underflow
39023 */
39024#define PDM_FIFO_STAT_FIFOUND0(x) \
39025 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK)
39026#define PDM_FIFO_STAT_FIFOUND1_MASK (0x200U)
39027#define PDM_FIFO_STAT_FIFOUND1_SHIFT (9U)
39028/*! FIFOUND1 - FIFO Underflow Exception flag for channel 1
39029 * 0b0..No exception by FIFO Underflow
39030 * 0b1..Exception by FIFO underflow
39031 */
39032#define PDM_FIFO_STAT_FIFOUND1(x) \
39033 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK)
39034#define PDM_FIFO_STAT_FIFOUND2_MASK (0x400U)
39035#define PDM_FIFO_STAT_FIFOUND2_SHIFT (10U)
39036/*! FIFOUND2 - FIFO Underflow Exception flag for channel 2
39037 * 0b0..No exception by FIFO Underflow
39038 * 0b1..Exception by FIFO underflow
39039 */
39040#define PDM_FIFO_STAT_FIFOUND2(x) \
39041 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK)
39042#define PDM_FIFO_STAT_FIFOUND3_MASK (0x800U)
39043#define PDM_FIFO_STAT_FIFOUND3_SHIFT (11U)
39044/*! FIFOUND3 - FIFO Underflow Exception flag for channel 3
39045 * 0b0..No exception by FIFO Underflow
39046 * 0b1..Exception by FIFO underflow
39047 */
39048#define PDM_FIFO_STAT_FIFOUND3(x) \
39049 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK)
39050#define PDM_FIFO_STAT_FIFOUND4_MASK (0x1000U)
39051#define PDM_FIFO_STAT_FIFOUND4_SHIFT (12U)
39052/*! FIFOUND4 - FIFO Underflow Exception flag for channel 4
39053 * 0b0..No exception by FIFO Underflow
39054 * 0b1..Exception by FIFO underflow
39055 */
39056#define PDM_FIFO_STAT_FIFOUND4(x) \
39057 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK)
39058#define PDM_FIFO_STAT_FIFOUND5_MASK (0x2000U)
39059#define PDM_FIFO_STAT_FIFOUND5_SHIFT (13U)
39060/*! FIFOUND5 - FIFO Underflow Exception flag for channel 5
39061 * 0b0..No exception by FIFO Underflow
39062 * 0b1..Exception by FIFO underflow
39063 */
39064#define PDM_FIFO_STAT_FIFOUND5(x) \
39065 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK)
39066#define PDM_FIFO_STAT_FIFOUND6_MASK (0x4000U)
39067#define PDM_FIFO_STAT_FIFOUND6_SHIFT (14U)
39068/*! FIFOUND6 - FIFO Underflow Exception flag for channel 6
39069 * 0b0..No exception by FIFO Underflow
39070 * 0b1..Exception by FIFO underflow
39071 */
39072#define PDM_FIFO_STAT_FIFOUND6(x) \
39073 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK)
39074#define PDM_FIFO_STAT_FIFOUND7_MASK (0x8000U)
39075#define PDM_FIFO_STAT_FIFOUND7_SHIFT (15U)
39076/*! FIFOUND7 - FIFO Underflow Exception flag for channel 7
39077 * 0b0..No exception by FIFO Underflow
39078 * 0b1..Exception by FIFO underflow
39079 */
39080#define PDM_FIFO_STAT_FIFOUND7(x) \
39081 (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND7_SHIFT)) & PDM_FIFO_STAT_FIFOUND7_MASK)
39082/*! @} */
39083
39084/*! @name DATACH - MICFIL Output Result Register */
39085/*! @{ */
39086#define PDM_DATACH_DATA_MASK (0xFFFFU)
39087#define PDM_DATACH_DATA_SHIFT (0U)
39088#define PDM_DATACH_DATA(x) (((uint32_t)(((uint32_t)(x)) << PDM_DATACH_DATA_SHIFT)) & PDM_DATACH_DATA_MASK)
39089/*! @} */
39090
39091/* The count of PDM_DATACH */
39092#define PDM_DATACH_COUNT (8U)
39093
39094/*! @name DC_CTRL - MICFIL DC Remover Control register */
39095/*! @{ */
39096#define PDM_DC_CTRL_DCCONFIG0_MASK (0x3U)
39097#define PDM_DC_CTRL_DCCONFIG0_SHIFT (0U)
39098/*! DCCONFIG0 - Channel 0 DC Remover Configuration
39099 * 0b11..DC Remover is bypassed.
39100 * 0b00..DC Remover cut-off at 21Hz.
39101 * 0b01..DC Remover cut-off at 83Hz.
39102 * 0b10..DC Remover cut-off at 152Hz.
39103 */
39104#define PDM_DC_CTRL_DCCONFIG0(x) \
39105 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK)
39106#define PDM_DC_CTRL_DCCONFIG1_MASK (0xCU)
39107#define PDM_DC_CTRL_DCCONFIG1_SHIFT (2U)
39108/*! DCCONFIG1 - Channel 1 DC Remover Configuration
39109 * 0b11..DC Remover is bypassed.
39110 * 0b00..DC Remover cut-off at 21Hz.
39111 * 0b01..DC Remover cut-off at 83Hz.
39112 * 0b10..DC Remover cut-off at 152Hz.
39113 */
39114#define PDM_DC_CTRL_DCCONFIG1(x) \
39115 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK)
39116#define PDM_DC_CTRL_DCCONFIG2_MASK (0x30U)
39117#define PDM_DC_CTRL_DCCONFIG2_SHIFT (4U)
39118/*! DCCONFIG2 - Channel 2 DC Remover Configuration
39119 * 0b11..DC Remover is bypassed.
39120 * 0b00..DC Remover cut-off at 21Hz.
39121 * 0b01..DC Remover cut-off at 83Hz.
39122 * 0b10..DC Remover cut-off at 152Hz.
39123 */
39124#define PDM_DC_CTRL_DCCONFIG2(x) \
39125 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK)
39126#define PDM_DC_CTRL_DCCONFIG3_MASK (0xC0U)
39127#define PDM_DC_CTRL_DCCONFIG3_SHIFT (6U)
39128/*! DCCONFIG3 - Channel 3 DC Remover Configuration
39129 * 0b11..DC Remover is bypassed.
39130 * 0b00..DC Remover cut-off at 21Hz.
39131 * 0b01..DC Remover cut-off at 83Hz.
39132 * 0b10..DC Remover cut-off at 152Hz.
39133 */
39134#define PDM_DC_CTRL_DCCONFIG3(x) \
39135 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK)
39136#define PDM_DC_CTRL_DCCONFIG4_MASK (0x300U)
39137#define PDM_DC_CTRL_DCCONFIG4_SHIFT (8U)
39138/*! DCCONFIG4 - Channel 4 DC Remover Configuration
39139 * 0b11..DC Remover is bypassed.
39140 * 0b00..DC Remover cut-off at 21Hz.
39141 * 0b01..DC Remover cut-off at 83Hz.
39142 * 0b10..DC Remover cut-off at 152Hz.
39143 */
39144#define PDM_DC_CTRL_DCCONFIG4(x) \
39145 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK)
39146#define PDM_DC_CTRL_DCCONFIG5_MASK (0xC00U)
39147#define PDM_DC_CTRL_DCCONFIG5_SHIFT (10U)
39148/*! DCCONFIG5 - Channel 5 DC Remover Configuration
39149 * 0b11..DC Remover is bypassed.
39150 * 0b00..DC Remover cut-off at 21Hz.
39151 * 0b01..DC Remover cut-off at 83Hz.
39152 * 0b10..DC Remover cut-off at 152Hz.
39153 */
39154#define PDM_DC_CTRL_DCCONFIG5(x) \
39155 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK)
39156#define PDM_DC_CTRL_DCCONFIG6_MASK (0x3000U)
39157#define PDM_DC_CTRL_DCCONFIG6_SHIFT (12U)
39158/*! DCCONFIG6 - Channel 6 DC Remover Configuration
39159 * 0b11..DC Remover is bypassed.
39160 * 0b00..DC Remover cut-off at 21Hz.
39161 * 0b01..DC Remover cut-off at 83Hz.
39162 * 0b10..DC Remover cut-off at 152Hz.
39163 */
39164#define PDM_DC_CTRL_DCCONFIG6(x) \
39165 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK)
39166#define PDM_DC_CTRL_DCCONFIG7_MASK (0xC000U)
39167#define PDM_DC_CTRL_DCCONFIG7_SHIFT (14U)
39168/*! DCCONFIG7 - Channel 7 DC Remover Configuration
39169 * 0b11..DC Remover is bypassed.
39170 * 0b00..DC Remover cut-off at 21Hz.
39171 * 0b01..DC Remover cut-off at 83Hz.
39172 * 0b10..DC Remover cut-off at 152Hz.
39173 */
39174#define PDM_DC_CTRL_DCCONFIG7(x) \
39175 (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK)
39176/*! @} */
39177
39178/*! @name OUT_CTRL - MICFIL Output Control register */
39179/*! @{ */
39180#define PDM_OUT_CTRL_OUTGAIN0_MASK (0xFU)
39181#define PDM_OUT_CTRL_OUTGAIN0_SHIFT (0U)
39182#define PDM_OUT_CTRL_OUTGAIN0(x) \
39183 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_CTRL_OUTGAIN0_SHIFT)) & PDM_OUT_CTRL_OUTGAIN0_MASK)
39184#define PDM_OUT_CTRL_OUTGAIN1_MASK (0xF0U)
39185#define PDM_OUT_CTRL_OUTGAIN1_SHIFT (4U)
39186#define PDM_OUT_CTRL_OUTGAIN1(x) \
39187 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_CTRL_OUTGAIN1_SHIFT)) & PDM_OUT_CTRL_OUTGAIN1_MASK)
39188#define PDM_OUT_CTRL_OUTGAIN2_MASK (0xF00U)
39189#define PDM_OUT_CTRL_OUTGAIN2_SHIFT (8U)
39190#define PDM_OUT_CTRL_OUTGAIN2(x) \
39191 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_CTRL_OUTGAIN2_SHIFT)) & PDM_OUT_CTRL_OUTGAIN2_MASK)
39192#define PDM_OUT_CTRL_OUTGAIN3_MASK (0xF000U)
39193#define PDM_OUT_CTRL_OUTGAIN3_SHIFT (12U)
39194#define PDM_OUT_CTRL_OUTGAIN3(x) \
39195 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_CTRL_OUTGAIN3_SHIFT)) & PDM_OUT_CTRL_OUTGAIN3_MASK)
39196#define PDM_OUT_CTRL_OUTGAIN4_MASK (0xF0000U)
39197#define PDM_OUT_CTRL_OUTGAIN4_SHIFT (16U)
39198#define PDM_OUT_CTRL_OUTGAIN4(x) \
39199 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_CTRL_OUTGAIN4_SHIFT)) & PDM_OUT_CTRL_OUTGAIN4_MASK)
39200#define PDM_OUT_CTRL_OUTGAIN5_MASK (0xF00000U)
39201#define PDM_OUT_CTRL_OUTGAIN5_SHIFT (20U)
39202#define PDM_OUT_CTRL_OUTGAIN5(x) \
39203 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_CTRL_OUTGAIN5_SHIFT)) & PDM_OUT_CTRL_OUTGAIN5_MASK)
39204#define PDM_OUT_CTRL_OUTGAIN6_MASK (0xF000000U)
39205#define PDM_OUT_CTRL_OUTGAIN6_SHIFT (24U)
39206#define PDM_OUT_CTRL_OUTGAIN6(x) \
39207 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_CTRL_OUTGAIN6_SHIFT)) & PDM_OUT_CTRL_OUTGAIN6_MASK)
39208#define PDM_OUT_CTRL_OUTGAIN7_MASK (0xF0000000U)
39209#define PDM_OUT_CTRL_OUTGAIN7_SHIFT (28U)
39210#define PDM_OUT_CTRL_OUTGAIN7(x) \
39211 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_CTRL_OUTGAIN7_SHIFT)) & PDM_OUT_CTRL_OUTGAIN7_MASK)
39212/*! @} */
39213
39214/*! @name OUT_STAT - MICFIL Output Status register */
39215/*! @{ */
39216#define PDM_OUT_STAT_OUTOVF0_MASK (0x1U)
39217#define PDM_OUT_STAT_OUTOVF0_SHIFT (0U)
39218/*! OUTOVF0 - Channel 0 Output Overflow Flag
39219 * 0b0..No exception by output overflow.
39220 * 0b1..Exception by output overflow.
39221 */
39222#define PDM_OUT_STAT_OUTOVF0(x) \
39223 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTOVF0_SHIFT)) & PDM_OUT_STAT_OUTOVF0_MASK)
39224#define PDM_OUT_STAT_OUTOVF1_MASK (0x2U)
39225#define PDM_OUT_STAT_OUTOVF1_SHIFT (1U)
39226/*! OUTOVF1 - Channel 1 Output Overflow Flag
39227 * 0b0..No exception by output overflow.
39228 * 0b1..Exception by output overflow.
39229 */
39230#define PDM_OUT_STAT_OUTOVF1(x) \
39231 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTOVF1_SHIFT)) & PDM_OUT_STAT_OUTOVF1_MASK)
39232#define PDM_OUT_STAT_OUTOVF2_MASK (0x4U)
39233#define PDM_OUT_STAT_OUTOVF2_SHIFT (2U)
39234/*! OUTOVF2 - Channel 2 Output Overflow Flag
39235 * 0b0..No exception by output overflow.
39236 * 0b1..Exception by output overflow.
39237 */
39238#define PDM_OUT_STAT_OUTOVF2(x) \
39239 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTOVF2_SHIFT)) & PDM_OUT_STAT_OUTOVF2_MASK)
39240#define PDM_OUT_STAT_OUTOVF3_MASK (0x8U)
39241#define PDM_OUT_STAT_OUTOVF3_SHIFT (3U)
39242/*! OUTOVF3 - Channel 3 Output Overflow Flag
39243 * 0b0..No exception by output overflow.
39244 * 0b1..Exception by output overflow.
39245 */
39246#define PDM_OUT_STAT_OUTOVF3(x) \
39247 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTOVF3_SHIFT)) & PDM_OUT_STAT_OUTOVF3_MASK)
39248#define PDM_OUT_STAT_OUTOVF4_MASK (0x10U)
39249#define PDM_OUT_STAT_OUTOVF4_SHIFT (4U)
39250/*! OUTOVF4 - Channel 4 Output Overflow Flag
39251 * 0b0..No exception by output overflow.
39252 * 0b1..Exception by output overflow.
39253 */
39254#define PDM_OUT_STAT_OUTOVF4(x) \
39255 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTOVF4_SHIFT)) & PDM_OUT_STAT_OUTOVF4_MASK)
39256#define PDM_OUT_STAT_OUTOVF5_MASK (0x20U)
39257#define PDM_OUT_STAT_OUTOVF5_SHIFT (5U)
39258/*! OUTOVF5 - Channel 5 Output Overflow Flag
39259 * 0b0..No exception by output overflow.
39260 * 0b1..Exception by output overflow.
39261 */
39262#define PDM_OUT_STAT_OUTOVF5(x) \
39263 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTOVF5_SHIFT)) & PDM_OUT_STAT_OUTOVF5_MASK)
39264#define PDM_OUT_STAT_OUTOVF6_MASK (0x40U)
39265#define PDM_OUT_STAT_OUTOVF6_SHIFT (6U)
39266/*! OUTOVF6 - Channel 6 Output Overflow Flag
39267 * 0b0..No exception by output overflow.
39268 * 0b1..Exception by output overflow.
39269 */
39270#define PDM_OUT_STAT_OUTOVF6(x) \
39271 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTOVF6_SHIFT)) & PDM_OUT_STAT_OUTOVF6_MASK)
39272#define PDM_OUT_STAT_OUTOVF7_MASK (0x80U)
39273#define PDM_OUT_STAT_OUTOVF7_SHIFT (7U)
39274/*! OUTOVF7 - Channel 7 Output Overflow Flag
39275 * 0b0..No exception by output overflow.
39276 * 0b1..Exception by output overflow.
39277 */
39278#define PDM_OUT_STAT_OUTOVF7(x) \
39279 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTOVF7_SHIFT)) & PDM_OUT_STAT_OUTOVF7_MASK)
39280#define PDM_OUT_STAT_OUTUNF0_MASK (0x10000U)
39281#define PDM_OUT_STAT_OUTUNF0_SHIFT (16U)
39282/*! OUTUNF0 - Channel 0 Output Underflow Flag
39283 * 0b0..No exception by output underflow.
39284 * 0b1..Exception by output underflow.
39285 */
39286#define PDM_OUT_STAT_OUTUNF0(x) \
39287 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTUNF0_SHIFT)) & PDM_OUT_STAT_OUTUNF0_MASK)
39288#define PDM_OUT_STAT_OUTUNF1_MASK (0x20000U)
39289#define PDM_OUT_STAT_OUTUNF1_SHIFT (17U)
39290/*! OUTUNF1 - Channel 1 Output Underflow Flag
39291 * 0b0..No exception by output underflow.
39292 * 0b1..Exception by output underflow.
39293 */
39294#define PDM_OUT_STAT_OUTUNF1(x) \
39295 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTUNF1_SHIFT)) & PDM_OUT_STAT_OUTUNF1_MASK)
39296#define PDM_OUT_STAT_OUTUNF2_MASK (0x40000U)
39297#define PDM_OUT_STAT_OUTUNF2_SHIFT (18U)
39298/*! OUTUNF2 - Channel 2 Output Underflow Flag
39299 * 0b0..No exception by output underflow.
39300 * 0b1..Exception by output underflow.
39301 */
39302#define PDM_OUT_STAT_OUTUNF2(x) \
39303 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTUNF2_SHIFT)) & PDM_OUT_STAT_OUTUNF2_MASK)
39304#define PDM_OUT_STAT_OUTUNF3_MASK (0x80000U)
39305#define PDM_OUT_STAT_OUTUNF3_SHIFT (19U)
39306/*! OUTUNF3 - Channel 3 Output Underflow Flag
39307 * 0b0..No exception by output underflow.
39308 * 0b1..Exception by output underflow.
39309 */
39310#define PDM_OUT_STAT_OUTUNF3(x) \
39311 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTUNF3_SHIFT)) & PDM_OUT_STAT_OUTUNF3_MASK)
39312#define PDM_OUT_STAT_OUTUNF4_MASK (0x100000U)
39313#define PDM_OUT_STAT_OUTUNF4_SHIFT (20U)
39314/*! OUTUNF4 - Channel 4 Output Underflow Flag
39315 * 0b0..No exception by output underflow.
39316 * 0b1..Exception by output underflow.
39317 */
39318#define PDM_OUT_STAT_OUTUNF4(x) \
39319 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTUNF4_SHIFT)) & PDM_OUT_STAT_OUTUNF4_MASK)
39320#define PDM_OUT_STAT_OUTUNF5_MASK (0x200000U)
39321#define PDM_OUT_STAT_OUTUNF5_SHIFT (21U)
39322/*! OUTUNF5 - Channel 5 Output Underflow Flag
39323 * 0b0..No exception by output underflow.
39324 * 0b1..Exception by output underflow.
39325 */
39326#define PDM_OUT_STAT_OUTUNF5(x) \
39327 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTUNF5_SHIFT)) & PDM_OUT_STAT_OUTUNF5_MASK)
39328#define PDM_OUT_STAT_OUTUNF6_MASK (0x400000U)
39329#define PDM_OUT_STAT_OUTUNF6_SHIFT (22U)
39330/*! OUTUNF6 - Channel 6 Output Underflow Flag
39331 * 0b0..No exception by output underflow.
39332 * 0b1..Exception by output underflow.
39333 */
39334#define PDM_OUT_STAT_OUTUNF6(x) \
39335 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTUNF6_SHIFT)) & PDM_OUT_STAT_OUTUNF6_MASK)
39336#define PDM_OUT_STAT_OUTUNF7_MASK (0x800000U)
39337#define PDM_OUT_STAT_OUTUNF7_SHIFT (23U)
39338/*! OUTUNF7 - Channel 7 Output Underflow Flag
39339 * 0b0..No exception by output underflow.
39340 * 0b1..Exception by output underflow.
39341 */
39342#define PDM_OUT_STAT_OUTUNF7(x) \
39343 (((uint32_t)(((uint32_t)(x)) << PDM_OUT_STAT_OUTUNF7_SHIFT)) & PDM_OUT_STAT_OUTUNF7_MASK)
39344/*! @} */
39345
39346/*! @name VAD0_CTRL_1 - Voice Activity Detector 0 Control register */
39347/*! @{ */
39348#define PDM_VAD0_CTRL_1_VADEN_MASK (0x1U)
39349#define PDM_VAD0_CTRL_1_VADEN_SHIFT (0U)
39350/*! VADEN - Voice Activity Detector Enable
39351 * 0b0..The HWVAD is disabled.
39352 * 0b1..The HWVAD is enabled.
39353 */
39354#define PDM_VAD0_CTRL_1_VADEN(x) \
39355 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK)
39356#define PDM_VAD0_CTRL_1_VADRST_MASK (0x2U)
39357#define PDM_VAD0_CTRL_1_VADRST_SHIFT (1U)
39358#define PDM_VAD0_CTRL_1_VADRST(x) \
39359 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK)
39360#define PDM_VAD0_CTRL_1_VADIE_MASK (0x4U)
39361#define PDM_VAD0_CTRL_1_VADIE_SHIFT (2U)
39362/*! VADIE - Voice Activity Detector Interruption Enable
39363 * 0b0..HWVAD Interrupts disabled
39364 * 0b1..HWVAD Interrupts enabled
39365 */
39366#define PDM_VAD0_CTRL_1_VADIE(x) \
39367 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK)
39368#define PDM_VAD0_CTRL_1_VADERIE_MASK (0x8U)
39369#define PDM_VAD0_CTRL_1_VADERIE_SHIFT (3U)
39370/*! VADERIE - Voice Activity Detector Error Interruption Enable
39371 * 0b0..HWVAD Error Interrupts disabled
39372 * 0b1..HWVAD Error Interrupts enabled
39373 */
39374#define PDM_VAD0_CTRL_1_VADERIE(x) \
39375 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK)
39376#define PDM_VAD0_CTRL_1_VADST10_MASK (0x10U)
39377#define PDM_VAD0_CTRL_1_VADST10_SHIFT (4U)
39378/*! VADST10 - Voice Activity Detector Internal Filters Initialization
39379 * 0b0..Normal operation.
39380 * 0b1..Filters are initialized.
39381 */
39382#define PDM_VAD0_CTRL_1_VADST10(x) \
39383 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK)
39384#define PDM_VAD0_CTRL_1_VADINITT_MASK (0x1F00U)
39385#define PDM_VAD0_CTRL_1_VADINITT_SHIFT (8U)
39386#define PDM_VAD0_CTRL_1_VADINITT(x) \
39387 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK)
39388#define PDM_VAD0_CTRL_1_VADCICOSR_MASK (0xF0000U)
39389#define PDM_VAD0_CTRL_1_VADCICOSR_SHIFT (16U)
39390#define PDM_VAD0_CTRL_1_VADCICOSR(x) \
39391 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK)
39392#define PDM_VAD0_CTRL_1_VADCHSEL_MASK (0x7000000U)
39393#define PDM_VAD0_CTRL_1_VADCHSEL_SHIFT (24U)
39394#define PDM_VAD0_CTRL_1_VADCHSEL(x) \
39395 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCHSEL_SHIFT)) & PDM_VAD0_CTRL_1_VADCHSEL_MASK)
39396/*! @} */
39397
39398/*! @name VAD0_CTRL_2 - Voice Activity Detector 0 Control register */
39399/*! @{ */
39400#define PDM_VAD0_CTRL_2_VADHPF_MASK (0x3U)
39401#define PDM_VAD0_CTRL_2_VADHPF_SHIFT (0U)
39402/*! VADHPF - Voice Activity Detector High-Pass Filter
39403 * 0b00..Filter bypassed.
39404 * 0b01..Cut-off frequency at 1750Hz.
39405 * 0b10..Cut-off frequency at 215Hz.
39406 * 0b11..Cut-off frequency at 102Hz.
39407 */
39408#define PDM_VAD0_CTRL_2_VADHPF(x) \
39409 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK)
39410#define PDM_VAD0_CTRL_2_VADINPGAIN_MASK (0xF00U)
39411#define PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT (8U)
39412#define PDM_VAD0_CTRL_2_VADINPGAIN(x) \
39413 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK)
39414#define PDM_VAD0_CTRL_2_VADFRAMET_MASK (0x3F0000U)
39415#define PDM_VAD0_CTRL_2_VADFRAMET_SHIFT (16U)
39416#define PDM_VAD0_CTRL_2_VADFRAMET(x) \
39417 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK)
39418#define PDM_VAD0_CTRL_2_VADFOUTDIS_MASK (0x10000000U)
39419#define PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT (28U)
39420/*! VADFOUTDIS - Voice Activity Detector Force Output Disable
39421 * 0b0..Output is enabled.
39422 * 0b1..Output is disabled.
39423 */
39424#define PDM_VAD0_CTRL_2_VADFOUTDIS(x) \
39425 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK)
39426#define PDM_VAD0_CTRL_2_VADPREFEN_MASK (0x40000000U)
39427#define PDM_VAD0_CTRL_2_VADPREFEN_SHIFT (30U)
39428/*! VADPREFEN - Voice Activity Detector Pre Filter Enable
39429 * 0b0..Pre-filter is bypassed.
39430 * 0b1..Pre-filter is enabled.
39431 */
39432#define PDM_VAD0_CTRL_2_VADPREFEN(x) \
39433 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK)
39434#define PDM_VAD0_CTRL_2_VADFRENDIS_MASK (0x80000000U)
39435#define PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT (31U)
39436/*! VADFRENDIS - Voice Activity Detector Frame Energy Disable
39437 * 0b1..Frame energy calculus disabled.
39438 * 0b0..Frame energy calculus enabled.
39439 */
39440#define PDM_VAD0_CTRL_2_VADFRENDIS(x) \
39441 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK)
39442/*! @} */
39443
39444/*! @name VAD0_STAT - Voice Activity Detector 0 Status register */
39445/*! @{ */
39446#define PDM_VAD0_STAT_VADIF_MASK (0x1U)
39447#define PDM_VAD0_STAT_VADIF_SHIFT (0U)
39448/*! VADIF - Voice Activity Detector Interrupt Flag
39449 * 0b0..Voice activity has not been detected by the HWVAD.
39450 * 0b1..Voice activity has been detected by the HWVAD.
39451 */
39452#define PDM_VAD0_STAT_VADIF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK)
39453#define PDM_VAD0_STAT_VADEF_MASK (0x8000U)
39454#define PDM_VAD0_STAT_VADEF_SHIFT (15U)
39455/*! VADEF - Voice Activity Detector Event Flag
39456 * 0b0..Voice activity has not been detected by the HWVAD.
39457 * 0b1..Voice activity has been detected by the HWVAD.
39458 */
39459#define PDM_VAD0_STAT_VADEF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADEF_SHIFT)) & PDM_VAD0_STAT_VADEF_MASK)
39460#define PDM_VAD0_STAT_VADINSATF_MASK (0x10000U)
39461#define PDM_VAD0_STAT_VADINSATF_SHIFT (16U)
39462/*! VADINSATF - Voice Activity Detector Input Saturation Flag
39463 * 0b0..No exception by HWVAD input saturation.
39464 * 0b1..Exception by HWVAD input saturation.
39465 */
39466#define PDM_VAD0_STAT_VADINSATF(x) \
39467 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK)
39468#define PDM_VAD0_STAT_VADINITF_MASK (0x80000000U)
39469#define PDM_VAD0_STAT_VADINITF_SHIFT (31U)
39470/*! VADINITF - Voice Activity Detector Initialization Flag
39471 * 0b0..HWVAD is not being initialized.
39472 * 0b1..HWVAD is being initialized.
39473 */
39474#define PDM_VAD0_STAT_VADINITF(x) \
39475 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINITF_SHIFT)) & PDM_VAD0_STAT_VADINITF_MASK)
39476/*! @} */
39477
39478/*! @name VAD0_SCONFIG - Voice Activity Detector 0 Signal Configuration */
39479/*! @{ */
39480#define PDM_VAD0_SCONFIG_VADSGAIN_MASK (0xFU)
39481#define PDM_VAD0_SCONFIG_VADSGAIN_SHIFT (0U)
39482#define PDM_VAD0_SCONFIG_VADSGAIN(x) \
39483 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK)
39484#define PDM_VAD0_SCONFIG_VADSMAXEN_MASK (0x40000000U)
39485#define PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT (30U)
39486/*! VADSMAXEN - Voice Activity Detector Signal Maximum Enable
39487 * 0b0..Maximum block is bypassed.
39488 * 0b1..Maximum block is enabled.
39489 */
39490#define PDM_VAD0_SCONFIG_VADSMAXEN(x) \
39491 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK)
39492#define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U)
39493#define PDM_VAD0_SCONFIG_VADSFILEN_SHIFT (31U)
39494/*! VADSFILEN - Voice Activity Detector Signal Filter Enable
39495 * 0b0..Signal filter is disabled.
39496 * 0b1..Signal filter is enabled.
39497 */
39498#define PDM_VAD0_SCONFIG_VADSFILEN(x) \
39499 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
39500/*! @} */
39501
39502/*! @name VAD0_NCONFIG - Voice Activity Detector 0 Noise Configuration */
39503/*! @{ */
39504#define PDM_VAD0_NCONFIG_VADNGAIN_MASK (0xFU)
39505#define PDM_VAD0_NCONFIG_VADNGAIN_SHIFT (0U)
39506#define PDM_VAD0_NCONFIG_VADNGAIN(x) \
39507 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK)
39508#define PDM_VAD0_NCONFIG_VADNFILADJ_MASK (0x1F00U)
39509#define PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT (8U)
39510#define PDM_VAD0_NCONFIG_VADNFILADJ(x) \
39511 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK)
39512#define PDM_VAD0_NCONFIG_VADNOREN_MASK (0x10000000U)
39513#define PDM_VAD0_NCONFIG_VADNOREN_SHIFT (28U)
39514/*! VADNOREN - Voice Activity Detector Noise OR Enable
39515 * 0b0..Noise input is not decimated.
39516 * 0b1..Noise input is decimated.
39517 */
39518#define PDM_VAD0_NCONFIG_VADNOREN(x) \
39519 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK)
39520#define PDM_VAD0_NCONFIG_VADNDECEN_MASK (0x20000000U)
39521#define PDM_VAD0_NCONFIG_VADNDECEN_SHIFT (29U)
39522/*! VADNDECEN - Voice Activity Detector Noise Decimation Enable
39523 * 0b0..Noise input is not decimated.
39524 * 0b1..Noise input is decimated.
39525 */
39526#define PDM_VAD0_NCONFIG_VADNDECEN(x) \
39527 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK)
39528#define PDM_VAD0_NCONFIG_VADNMINEN_MASK (0x40000000U)
39529#define PDM_VAD0_NCONFIG_VADNMINEN_SHIFT (30U)
39530/*! VADNMINEN - Voice Activity Detector Noise Minimum Enable
39531 * 0b0..Minimum block is bypassed.
39532 * 0b1..Minimum block is enabled.
39533 */
39534#define PDM_VAD0_NCONFIG_VADNMINEN(x) \
39535 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK)
39536#define PDM_VAD0_NCONFIG_VADNFILAUTO_MASK (0x80000000U)
39537#define PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT (31U)
39538/*! VADNFILAUTO - Voice Activity Detector Noise Filter Auto
39539 * 0b0..Noise filter is always enabled.
39540 * 0b1..Noise filter is enabled/disabled based on voice activity information.
39541 */
39542#define PDM_VAD0_NCONFIG_VADNFILAUTO(x) \
39543 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILAUTO_MASK)
39544/*! @} */
39545
39546/*! @name VAD0_NDATA - Voice Activity Detector 0 Noise Data */
39547/*! @{ */
39548#define PDM_VAD0_NDATA_VADNDATA_MASK (0xFFFFU)
39549#define PDM_VAD0_NDATA_VADNDATA_SHIFT (0U)
39550#define PDM_VAD0_NDATA_VADNDATA(x) \
39551 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NDATA_VADNDATA_SHIFT)) & PDM_VAD0_NDATA_VADNDATA_MASK)
39552/*! @} */
39553
39554/*! @name VAD0_ZCD - Voice Activity Detector 0 Zero-Crossing Detector */
39555/*! @{ */
39556#define PDM_VAD0_ZCD_VADZCDEN_MASK (0x1U)
39557#define PDM_VAD0_ZCD_VADZCDEN_SHIFT (0U)
39558/*! VADZCDEN - Zero-Crossing Detector Enable
39559 * 0b0..The ZCD is disabled.
39560 * 0b1..The ZCD is enabled.
39561 */
39562#define PDM_VAD0_ZCD_VADZCDEN(x) \
39563 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK)
39564#define PDM_VAD0_ZCD_VADZCDAUTO_MASK (0x4U)
39565#define PDM_VAD0_ZCD_VADZCDAUTO_SHIFT (2U)
39566/*! VADZCDAUTO - Zero-Crossing Detector Automatic Threshold
39567 * 0b0..The ZCD threshold is not estimated automatically,
39568 * 0b1..The ZCD threshold is estimated automatically.
39569 */
39570#define PDM_VAD0_ZCD_VADZCDAUTO(x) \
39571 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK)
39572#define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U)
39573#define PDM_VAD0_ZCD_VADZCDAND_SHIFT (4U)
39574/*! VADZCDAND - Zero-Crossing Detector AND Behavior
39575 * 0b0..The ZCD result is OR'ed with the energy-based detection.
39576 * 0b1..The ZCD result is AND'ed with the energy-based detection.
39577 */
39578#define PDM_VAD0_ZCD_VADZCDAND(x) \
39579 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
39580#define PDM_VAD0_ZCD_VADZCDADJ_MASK (0xF00U)
39581#define PDM_VAD0_ZCD_VADZCDADJ_SHIFT (8U)
39582#define PDM_VAD0_ZCD_VADZCDADJ(x) \
39583 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK)
39584#define PDM_VAD0_ZCD_VADZCDTH_MASK (0x3FF0000U)
39585#define PDM_VAD0_ZCD_VADZCDTH_SHIFT (16U)
39586#define PDM_VAD0_ZCD_VADZCDTH(x) \
39587 (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDTH_SHIFT)) & PDM_VAD0_ZCD_VADZCDTH_MASK)
39588/*! @} */
39589
39590/*!
39591 * @}
39592 */ /* end of group PDM_Register_Masks */
39593
39594/* PDM - Peripheral instance base addresses */
39595/** Peripheral PDM base address */
39596#define PDM_BASE (0x30080000u)
39597/** Peripheral PDM base pointer */
39598#define PDM ((PDM_Type *)PDM_BASE)
39599/** Array initializer of PDM peripheral base addresses */
39600#define PDM_BASE_ADDRS \
39601 { \
39602 PDM_BASE \
39603 }
39604/** Array initializer of PDM peripheral base pointers */
39605#define PDM_BASE_PTRS \
39606 { \
39607 PDM \
39608 }
39609
39610/*!
39611 * @}
39612 */ /* end of group PDM_Peripheral_Access_Layer */
39613
39614/* ----------------------------------------------------------------------------
39615 -- PWM Peripheral Access Layer
39616 ---------------------------------------------------------------------------- */
39617
39618/*!
39619 * @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
39620 * @{
39621 */
39622
39623/** PWM - Register Layout Typedef */
39624typedef struct
39625{
39626 __IO uint32_t PWMCR; /**< PWM Control Register, offset: 0x0 */
39627 __IO uint32_t PWMSR; /**< PWM Status Register, offset: 0x4 */
39628 __IO uint32_t PWMIR; /**< PWM Interrupt Register, offset: 0x8 */
39629 __IO uint32_t PWMSAR; /**< PWM Sample Register, offset: 0xC */
39630 __IO uint32_t PWMPR; /**< PWM Period Register, offset: 0x10 */
39631 __I uint32_t PWMCNR; /**< PWM Counter Register, offset: 0x14 */
39632} PWM_Type;
39633
39634/* ----------------------------------------------------------------------------
39635 -- PWM Register Masks
39636 ---------------------------------------------------------------------------- */
39637
39638/*!
39639 * @addtogroup PWM_Register_Masks PWM Register Masks
39640 * @{
39641 */
39642
39643/*! @name PWMCR - PWM Control Register */
39644/*! @{ */
39645#define PWM_PWMCR_EN_MASK (0x1U)
39646#define PWM_PWMCR_EN_SHIFT (0U)
39647/*! EN
39648 * 0b0..PWM disabled
39649 * 0b1..PWM enabled
39650 */
39651#define PWM_PWMCR_EN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_EN_SHIFT)) & PWM_PWMCR_EN_MASK)
39652#define PWM_PWMCR_REPEAT_MASK (0x6U)
39653#define PWM_PWMCR_REPEAT_SHIFT (1U)
39654/*! REPEAT
39655 * 0b00..Use each sample once
39656 * 0b01..Use each sample twice
39657 * 0b10..Use each sample four times
39658 * 0b11..Use each sample eight times
39659 */
39660#define PWM_PWMCR_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_REPEAT_SHIFT)) & PWM_PWMCR_REPEAT_MASK)
39661#define PWM_PWMCR_SWR_MASK (0x8U)
39662#define PWM_PWMCR_SWR_SHIFT (3U)
39663/*! SWR
39664 * 0b0..PWM is out of reset
39665 * 0b1..PWM is undergoing reset
39666 */
39667#define PWM_PWMCR_SWR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_SWR_SHIFT)) & PWM_PWMCR_SWR_MASK)
39668#define PWM_PWMCR_PRESCALER_MASK (0xFFF0U)
39669#define PWM_PWMCR_PRESCALER_SHIFT (4U)
39670/*! PRESCALER
39671 * 0b000000000000..Divide by 1
39672 * 0b000000000001..Divide by 2
39673 * 0b111111111111..Divide by 4096
39674 */
39675#define PWM_PWMCR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_PRESCALER_SHIFT)) & PWM_PWMCR_PRESCALER_MASK)
39676#define PWM_PWMCR_CLKSRC_MASK (0x30000U)
39677#define PWM_PWMCR_CLKSRC_SHIFT (16U)
39678/*! CLKSRC
39679 * 0b00..Clock is off
39680 * 0b01..ipg_clk
39681 * 0b10..ipg_clk_highfreq
39682 * 0b11..ipg_clk_32k
39683 */
39684#define PWM_PWMCR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_CLKSRC_SHIFT)) & PWM_PWMCR_CLKSRC_MASK)
39685#define PWM_PWMCR_POUTC_MASK (0xC0000U)
39686#define PWM_PWMCR_POUTC_SHIFT (18U)
39687/*! POUTC
39688 * 0b00..Output pin is set at rollover and cleared at comparison
39689 * 0b01..Output pin is cleared at rollover and set at comparison
39690 * 0b10..PWM output is disconnected
39691 * 0b11..PWM output is disconnected
39692 */
39693#define PWM_PWMCR_POUTC(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_POUTC_SHIFT)) & PWM_PWMCR_POUTC_MASK)
39694#define PWM_PWMCR_HCTR_MASK (0x100000U)
39695#define PWM_PWMCR_HCTR_SHIFT (20U)
39696/*! HCTR
39697 * 0b0..Half word swapping does not take place
39698 * 0b1..Half words from write data bus are swapped
39699 */
39700#define PWM_PWMCR_HCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_HCTR_SHIFT)) & PWM_PWMCR_HCTR_MASK)
39701#define PWM_PWMCR_BCTR_MASK (0x200000U)
39702#define PWM_PWMCR_BCTR_SHIFT (21U)
39703/*! BCTR
39704 * 0b0..byte ordering remains the same
39705 * 0b1..byte ordering is reversed
39706 */
39707#define PWM_PWMCR_BCTR(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_BCTR_SHIFT)) & PWM_PWMCR_BCTR_MASK)
39708#define PWM_PWMCR_DBGEN_MASK (0x400000U)
39709#define PWM_PWMCR_DBGEN_SHIFT (22U)
39710/*! DBGEN
39711 * 0b0..Inactive in debug mode
39712 * 0b1..Active in debug mode
39713 */
39714#define PWM_PWMCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DBGEN_SHIFT)) & PWM_PWMCR_DBGEN_MASK)
39715#define PWM_PWMCR_WAITEN_MASK (0x800000U)
39716#define PWM_PWMCR_WAITEN_SHIFT (23U)
39717/*! WAITEN
39718 * 0b0..Inactive in wait mode
39719 * 0b1..Active in wait mode
39720 */
39721#define PWM_PWMCR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_WAITEN_SHIFT)) & PWM_PWMCR_WAITEN_MASK)
39722#define PWM_PWMCR_DOZEN_MASK (0x1000000U)
39723#define PWM_PWMCR_DOZEN_SHIFT (24U)
39724/*! DOZEN
39725 * 0b0..Inactive in doze mode
39726 * 0b1..Active in doze mode
39727 */
39728#define PWM_PWMCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_DOZEN_SHIFT)) & PWM_PWMCR_DOZEN_MASK)
39729#define PWM_PWMCR_STOPEN_MASK (0x2000000U)
39730#define PWM_PWMCR_STOPEN_SHIFT (25U)
39731/*! STOPEN
39732 * 0b0..Inactive in stop mode
39733 * 0b1..Active in stop mode
39734 */
39735#define PWM_PWMCR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_STOPEN_SHIFT)) & PWM_PWMCR_STOPEN_MASK)
39736#define PWM_PWMCR_FWM_MASK (0xC000000U)
39737#define PWM_PWMCR_FWM_SHIFT (26U)
39738/*! FWM
39739 * 0b00..FIFO empty flag is set when there are more than or equal to 1 empty slots in FIFO
39740 * 0b01..FIFO empty flag is set when there are more than or equal to 2 empty slots in FIFO
39741 * 0b10..FIFO empty flag is set when there are more than or equal to 3 empty slots in FIFO
39742 * 0b11..FIFO empty flag is set when there are more than or equal to 4 empty slots in FIFO
39743 */
39744#define PWM_PWMCR_FWM(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCR_FWM_SHIFT)) & PWM_PWMCR_FWM_MASK)
39745/*! @} */
39746
39747/*! @name PWMSR - PWM Status Register */
39748/*! @{ */
39749#define PWM_PWMSR_FIFOAV_MASK (0x7U)
39750#define PWM_PWMSR_FIFOAV_SHIFT (0U)
39751/*! FIFOAV
39752 * 0b000..No data available
39753 * 0b001..1 word of data in FIFO
39754 * 0b010..2 words of data in FIFO
39755 * 0b011..3 words of data in FIFO
39756 * 0b100..4 words of data in FIFO
39757 * 0b101..unused
39758 * 0b110..unused
39759 * 0b111..unused
39760 */
39761#define PWM_PWMSR_FIFOAV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FIFOAV_SHIFT)) & PWM_PWMSR_FIFOAV_MASK)
39762#define PWM_PWMSR_FE_MASK (0x8U)
39763#define PWM_PWMSR_FE_SHIFT (3U)
39764/*! FE
39765 * 0b0..Data level is above water mark
39766 * 0b1..When the data level falls below the mark set by FWM field
39767 */
39768#define PWM_PWMSR_FE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FE_SHIFT)) & PWM_PWMSR_FE_MASK)
39769#define PWM_PWMSR_ROV_MASK (0x10U)
39770#define PWM_PWMSR_ROV_SHIFT (4U)
39771/*! ROV
39772 * 0b0..Roll-over event not occurred
39773 * 0b1..Roll-over event occurred
39774 */
39775#define PWM_PWMSR_ROV(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_ROV_SHIFT)) & PWM_PWMSR_ROV_MASK)
39776#define PWM_PWMSR_CMP_MASK (0x20U)
39777#define PWM_PWMSR_CMP_SHIFT (5U)
39778/*! CMP
39779 * 0b0..Compare event not occurred
39780 * 0b1..Compare event occurred
39781 */
39782#define PWM_PWMSR_CMP(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_CMP_SHIFT)) & PWM_PWMSR_CMP_MASK)
39783#define PWM_PWMSR_FWE_MASK (0x40U)
39784#define PWM_PWMSR_FWE_SHIFT (6U)
39785/*! FWE
39786 * 0b0..FIFO write error not occurred
39787 * 0b1..FIFO write error occurred
39788 */
39789#define PWM_PWMSR_FWE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSR_FWE_SHIFT)) & PWM_PWMSR_FWE_MASK)
39790/*! @} */
39791
39792/*! @name PWMIR - PWM Interrupt Register */
39793/*! @{ */
39794#define PWM_PWMIR_FIE_MASK (0x1U)
39795#define PWM_PWMIR_FIE_SHIFT (0U)
39796/*! FIE
39797 * 0b0..FIFO Empty interrupt disabled
39798 * 0b1..FIFO Empty interrupt enabled
39799 */
39800#define PWM_PWMIR_FIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_FIE_SHIFT)) & PWM_PWMIR_FIE_MASK)
39801#define PWM_PWMIR_RIE_MASK (0x2U)
39802#define PWM_PWMIR_RIE_SHIFT (1U)
39803/*! RIE
39804 * 0b0..Roll-over interrupt not enabled
39805 * 0b1..Roll-over Interrupt enabled
39806 */
39807#define PWM_PWMIR_RIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_RIE_SHIFT)) & PWM_PWMIR_RIE_MASK)
39808#define PWM_PWMIR_CIE_MASK (0x4U)
39809#define PWM_PWMIR_CIE_SHIFT (2U)
39810/*! CIE
39811 * 0b0..Compare Interrupt not enabled
39812 * 0b1..Compare Interrupt enabled
39813 */
39814#define PWM_PWMIR_CIE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMIR_CIE_SHIFT)) & PWM_PWMIR_CIE_MASK)
39815/*! @} */
39816
39817/*! @name PWMSAR - PWM Sample Register */
39818/*! @{ */
39819#define PWM_PWMSAR_SAMPLE_MASK (0xFFFFU)
39820#define PWM_PWMSAR_SAMPLE_SHIFT (0U)
39821#define PWM_PWMSAR_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMSAR_SAMPLE_SHIFT)) & PWM_PWMSAR_SAMPLE_MASK)
39822/*! @} */
39823
39824/*! @name PWMPR - PWM Period Register */
39825/*! @{ */
39826#define PWM_PWMPR_PERIOD_MASK (0xFFFFU)
39827#define PWM_PWMPR_PERIOD_SHIFT (0U)
39828#define PWM_PWMPR_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMPR_PERIOD_SHIFT)) & PWM_PWMPR_PERIOD_MASK)
39829/*! @} */
39830
39831/*! @name PWMCNR - PWM Counter Register */
39832/*! @{ */
39833#define PWM_PWMCNR_COUNT_MASK (0xFFFFU)
39834#define PWM_PWMCNR_COUNT_SHIFT (0U)
39835#define PWM_PWMCNR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << PWM_PWMCNR_COUNT_SHIFT)) & PWM_PWMCNR_COUNT_MASK)
39836/*! @} */
39837
39838/*!
39839 * @}
39840 */ /* end of group PWM_Register_Masks */
39841
39842/* PWM - Peripheral instance base addresses */
39843/** Peripheral PWM1 base address */
39844#define PWM1_BASE (0x30660000u)
39845/** Peripheral PWM1 base pointer */
39846#define PWM1 ((PWM_Type *)PWM1_BASE)
39847/** Peripheral PWM2 base address */
39848#define PWM2_BASE (0x30670000u)
39849/** Peripheral PWM2 base pointer */
39850#define PWM2 ((PWM_Type *)PWM2_BASE)
39851/** Peripheral PWM3 base address */
39852#define PWM3_BASE (0x30680000u)
39853/** Peripheral PWM3 base pointer */
39854#define PWM3 ((PWM_Type *)PWM3_BASE)
39855/** Peripheral PWM4 base address */
39856#define PWM4_BASE (0x30690000u)
39857/** Peripheral PWM4 base pointer */
39858#define PWM4 ((PWM_Type *)PWM4_BASE)
39859/** Array initializer of PWM peripheral base addresses */
39860#define PWM_BASE_ADDRS \
39861 { \
39862 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE \
39863 }
39864/** Array initializer of PWM peripheral base pointers */
39865#define PWM_BASE_PTRS \
39866 { \
39867 (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 \
39868 }
39869/** Interrupt vectors for the PWM peripheral type */
39870#define PWM_IRQS \
39871 { \
39872 NotAvail_IRQn, PWM1_IRQn, PWM2_IRQn, PWM3_IRQn, PWM4_IRQn \
39873 }
39874
39875/*!
39876 * @}
39877 */ /* end of group PWM_Peripheral_Access_Layer */
39878
39879/* ----------------------------------------------------------------------------
39880 -- RDC Peripheral Access Layer
39881 ---------------------------------------------------------------------------- */
39882
39883/*!
39884 * @addtogroup RDC_Peripheral_Access_Layer RDC Peripheral Access Layer
39885 * @{
39886 */
39887
39888/** RDC - Register Layout Typedef */
39889typedef struct
39890{
39891 __I uint32_t VIR; /**< Version Information, offset: 0x0 */
39892 uint8_t RESERVED_0[32];
39893 __IO uint32_t STAT; /**< Status, offset: 0x24 */
39894 __IO uint32_t INTCTRL; /**< Interrupt and Control, offset: 0x28 */
39895 __IO uint32_t INTSTAT; /**< Interrupt Status, offset: 0x2C */
39896 uint8_t RESERVED_1[464];
39897 __IO uint32_t MDA[27]; /**< Master Domain Assignment, array offset: 0x200, array step: 0x4 */
39898 uint8_t RESERVED_2[404];
39899 __IO uint32_t PDAP[118]; /**< Peripheral Domain Access Permissions, array offset: 0x400, array step: 0x4 */
39900 uint8_t RESERVED_3[552];
39901 struct
39902 { /* offset: 0x800, array step: 0x10 */
39903 __IO uint32_t MRSA; /**< Memory Region Start Address, array offset: 0x800, array step: 0x10 */
39904 __IO uint32_t MREA; /**< Memory Region End Address, array offset: 0x804, array step: 0x10 */
39905 __IO uint32_t MRC; /**< Memory Region Control, array offset: 0x808, array step: 0x10 */
39906 __IO uint32_t MRVS; /**< Memory Region Violation Status, array offset: 0x80C, array step: 0x10 */
39907 } MR[52];
39908} RDC_Type;
39909
39910/* ----------------------------------------------------------------------------
39911 -- RDC Register Masks
39912 ---------------------------------------------------------------------------- */
39913
39914/*!
39915 * @addtogroup RDC_Register_Masks RDC Register Masks
39916 * @{
39917 */
39918
39919/*! @name VIR - Version Information */
39920/*! @{ */
39921#define RDC_VIR_NDID_MASK (0xFU)
39922#define RDC_VIR_NDID_SHIFT (0U)
39923#define RDC_VIR_NDID(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NDID_SHIFT)) & RDC_VIR_NDID_MASK)
39924#define RDC_VIR_NMSTR_MASK (0xFF0U)
39925#define RDC_VIR_NMSTR_SHIFT (4U)
39926#define RDC_VIR_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NMSTR_SHIFT)) & RDC_VIR_NMSTR_MASK)
39927#define RDC_VIR_NPER_MASK (0xFF000U)
39928#define RDC_VIR_NPER_SHIFT (12U)
39929#define RDC_VIR_NPER(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NPER_SHIFT)) & RDC_VIR_NPER_MASK)
39930#define RDC_VIR_NRGN_MASK (0xFF00000U)
39931#define RDC_VIR_NRGN_SHIFT (20U)
39932#define RDC_VIR_NRGN(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NRGN_SHIFT)) & RDC_VIR_NRGN_MASK)
39933/*! @} */
39934
39935/*! @name STAT - Status */
39936/*! @{ */
39937#define RDC_STAT_DID_MASK (0xFU)
39938#define RDC_STAT_DID_SHIFT (0U)
39939#define RDC_STAT_DID(x) (((uint32_t)(((uint32_t)(x)) << RDC_STAT_DID_SHIFT)) & RDC_STAT_DID_MASK)
39940#define RDC_STAT_PDS_MASK (0x100U)
39941#define RDC_STAT_PDS_SHIFT (8U)
39942/*! PDS - Power Domain Status
39943 * 0b0..Power Down Domain is OFF
39944 * 0b1..Power Down Domain is ON
39945 */
39946#define RDC_STAT_PDS(x) (((uint32_t)(((uint32_t)(x)) << RDC_STAT_PDS_SHIFT)) & RDC_STAT_PDS_MASK)
39947/*! @} */
39948
39949/*! @name INTCTRL - Interrupt and Control */
39950/*! @{ */
39951#define RDC_INTCTRL_RCI_EN_MASK (0x1U)
39952#define RDC_INTCTRL_RCI_EN_SHIFT (0U)
39953/*! RCI_EN - Restoration Complete Interrupt
39954 * 0b0..Interrupt Disabled
39955 * 0b1..Interrupt Enabled
39956 */
39957#define RDC_INTCTRL_RCI_EN(x) (((uint32_t)(((uint32_t)(x)) << RDC_INTCTRL_RCI_EN_SHIFT)) & RDC_INTCTRL_RCI_EN_MASK)
39958/*! @} */
39959
39960/*! @name INTSTAT - Interrupt Status */
39961/*! @{ */
39962#define RDC_INTSTAT_INT_MASK (0x1U)
39963#define RDC_INTSTAT_INT_SHIFT (0U)
39964/*! INT - Interrupt Status
39965 * 0b0..No Interrupt Pending
39966 * 0b1..Interrupt Pending
39967 */
39968#define RDC_INTSTAT_INT(x) (((uint32_t)(((uint32_t)(x)) << RDC_INTSTAT_INT_SHIFT)) & RDC_INTSTAT_INT_MASK)
39969/*! @} */
39970
39971/*! @name MDA - Master Domain Assignment */
39972/*! @{ */
39973#define RDC_MDA_DID_MASK (0x3U)
39974#define RDC_MDA_DID_SHIFT (0U)
39975/*! DID - Domain ID
39976 * 0b00..Master assigned to Processing Domain 0
39977 * 0b01..Master assigned to Processing Domain 1
39978 * 0b10..Master assigned to Processing Domain 2
39979 * 0b11..Master assigned to Processing Domain 3
39980 */
39981#define RDC_MDA_DID(x) (((uint32_t)(((uint32_t)(x)) << RDC_MDA_DID_SHIFT)) & RDC_MDA_DID_MASK)
39982#define RDC_MDA_LCK_MASK (0x80000000U)
39983#define RDC_MDA_LCK_SHIFT (31U)
39984/*! LCK
39985 * 0b0..Not Locked
39986 * 0b1..Locked
39987 */
39988#define RDC_MDA_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_MDA_LCK_SHIFT)) & RDC_MDA_LCK_MASK)
39989/*! @} */
39990
39991/* The count of RDC_MDA */
39992#define RDC_MDA_COUNT (27U)
39993
39994/*! @name PDAP - Peripheral Domain Access Permissions */
39995/*! @{ */
39996#define RDC_PDAP_D0W_MASK (0x1U)
39997#define RDC_PDAP_D0W_SHIFT (0U)
39998/*! D0W - Domain 0 Write Access
39999 * 0b0..No Write Access
40000 * 0b1..Write Access Allowed
40001 */
40002#define RDC_PDAP_D0W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0W_SHIFT)) & RDC_PDAP_D0W_MASK)
40003#define RDC_PDAP_D0R_MASK (0x2U)
40004#define RDC_PDAP_D0R_SHIFT (1U)
40005/*! D0R - Domain 0 Read Access
40006 * 0b0..No Read Access
40007 * 0b1..Read Access Allowed
40008 */
40009#define RDC_PDAP_D0R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0R_SHIFT)) & RDC_PDAP_D0R_MASK)
40010#define RDC_PDAP_D1W_MASK (0x4U)
40011#define RDC_PDAP_D1W_SHIFT (2U)
40012/*! D1W - Domain 1 Write Access
40013 * 0b0..No Write Access
40014 * 0b1..Write Access Allowed
40015 */
40016#define RDC_PDAP_D1W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1W_SHIFT)) & RDC_PDAP_D1W_MASK)
40017#define RDC_PDAP_D1R_MASK (0x8U)
40018#define RDC_PDAP_D1R_SHIFT (3U)
40019/*! D1R - Domain 1 Read Access
40020 * 0b0..No Read Access
40021 * 0b1..Read Access Allowed
40022 */
40023#define RDC_PDAP_D1R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1R_SHIFT)) & RDC_PDAP_D1R_MASK)
40024#define RDC_PDAP_D2W_MASK (0x10U)
40025#define RDC_PDAP_D2W_SHIFT (4U)
40026/*! D2W - Domain 2 Write Access
40027 * 0b0..No Write Access
40028 * 0b1..Write Access Allowed
40029 */
40030#define RDC_PDAP_D2W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D2W_SHIFT)) & RDC_PDAP_D2W_MASK)
40031#define RDC_PDAP_D2R_MASK (0x20U)
40032#define RDC_PDAP_D2R_SHIFT (5U)
40033/*! D2R - Domain 2 Read Access
40034 * 0b0..No Read Access
40035 * 0b1..Read Access Allowed
40036 */
40037#define RDC_PDAP_D2R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D2R_SHIFT)) & RDC_PDAP_D2R_MASK)
40038#define RDC_PDAP_D3W_MASK (0x40U)
40039#define RDC_PDAP_D3W_SHIFT (6U)
40040/*! D3W - Domain 3 Write Access
40041 * 0b0..No Write Access
40042 * 0b1..Write Access Allowed
40043 */
40044#define RDC_PDAP_D3W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D3W_SHIFT)) & RDC_PDAP_D3W_MASK)
40045#define RDC_PDAP_D3R_MASK (0x80U)
40046#define RDC_PDAP_D3R_SHIFT (7U)
40047/*! D3R - Domain 3 Read Access
40048 * 0b0..No Read Access
40049 * 0b1..Read Access Allowed
40050 */
40051#define RDC_PDAP_D3R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D3R_SHIFT)) & RDC_PDAP_D3R_MASK)
40052#define RDC_PDAP_SREQ_MASK (0x40000000U)
40053#define RDC_PDAP_SREQ_SHIFT (30U)
40054/*! SREQ - Semaphore Required
40055 * 0b0..Semaphores have no effect
40056 * 0b1..Semaphores are enforced
40057 */
40058#define RDC_PDAP_SREQ(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_SREQ_SHIFT)) & RDC_PDAP_SREQ_MASK)
40059#define RDC_PDAP_LCK_MASK (0x80000000U)
40060#define RDC_PDAP_LCK_SHIFT (31U)
40061/*! LCK - Peripheral Permissions Lock
40062 * 0b0..Not Locked
40063 * 0b1..Locked
40064 */
40065#define RDC_PDAP_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_LCK_SHIFT)) & RDC_PDAP_LCK_MASK)
40066/*! @} */
40067
40068/* The count of RDC_PDAP */
40069#define RDC_PDAP_COUNT (118U)
40070
40071/*! @name MRSA - Memory Region Start Address */
40072/*! @{ */
40073#define RDC_MRSA_SADR_MASK (0xFFFFFF80U)
40074#define RDC_MRSA_SADR_SHIFT (7U)
40075#define RDC_MRSA_SADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRSA_SADR_SHIFT)) & RDC_MRSA_SADR_MASK)
40076/*! @} */
40077
40078/* The count of RDC_MRSA */
40079#define RDC_MRSA_COUNT (52U)
40080
40081/*! @name MREA - Memory Region End Address */
40082/*! @{ */
40083#define RDC_MREA_EADR_MASK (0xFFFFFF80U)
40084#define RDC_MREA_EADR_SHIFT (7U)
40085#define RDC_MREA_EADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MREA_EADR_SHIFT)) & RDC_MREA_EADR_MASK)
40086/*! @} */
40087
40088/* The count of RDC_MREA */
40089#define RDC_MREA_COUNT (52U)
40090
40091/*! @name MRC - Memory Region Control */
40092/*! @{ */
40093#define RDC_MRC_D0W_MASK (0x1U)
40094#define RDC_MRC_D0W_SHIFT (0U)
40095/*! D0W - Domain 0 Write Access to Region
40096 * 0b0..Processing Domain 0 does not have Write access to the memory region
40097 * 0b1..Processing Domain 0 has Write access to the memory region
40098 */
40099#define RDC_MRC_D0W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0W_SHIFT)) & RDC_MRC_D0W_MASK)
40100#define RDC_MRC_D0R_MASK (0x2U)
40101#define RDC_MRC_D0R_SHIFT (1U)
40102/*! D0R - Domain 0 Read Access to Region
40103 * 0b0..Processing Domain 0 does not have Read access to the memory region
40104 * 0b1..Processing Domain 0 has Read access to the memory region
40105 */
40106#define RDC_MRC_D0R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0R_SHIFT)) & RDC_MRC_D0R_MASK)
40107#define RDC_MRC_D1W_MASK (0x4U)
40108#define RDC_MRC_D1W_SHIFT (2U)
40109/*! D1W - Domain 1 Write Access to Region
40110 * 0b0..Processing Domain 1 does not have Write access to the memory region
40111 * 0b1..Processing Domain 1 has Write access to the memory region
40112 */
40113#define RDC_MRC_D1W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1W_SHIFT)) & RDC_MRC_D1W_MASK)
40114#define RDC_MRC_D1R_MASK (0x8U)
40115#define RDC_MRC_D1R_SHIFT (3U)
40116/*! D1R - Domain 1 Read Access to Region
40117 * 0b0..Processing Domain 1 does not have Read access to the memory region
40118 * 0b1..Processing Domain 1 has Read access to the memory region
40119 */
40120#define RDC_MRC_D1R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1R_SHIFT)) & RDC_MRC_D1R_MASK)
40121#define RDC_MRC_D2W_MASK (0x10U)
40122#define RDC_MRC_D2W_SHIFT (4U)
40123/*! D2W - Domain 2 Write Access to Region
40124 * 0b0..Processing Domain 2 does not have Write access to the memory region
40125 * 0b1..Processing Domain 2 has Write access to the memory region
40126 */
40127#define RDC_MRC_D2W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D2W_SHIFT)) & RDC_MRC_D2W_MASK)
40128#define RDC_MRC_D2R_MASK (0x20U)
40129#define RDC_MRC_D2R_SHIFT (5U)
40130/*! D2R - Domain 2 Read Access to Region
40131 * 0b0..Processing Domain 2 does not have Read access to the memory region
40132 * 0b1..Processing Domain 2 has Read access to the memory region
40133 */
40134#define RDC_MRC_D2R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D2R_SHIFT)) & RDC_MRC_D2R_MASK)
40135#define RDC_MRC_D3W_MASK (0x40U)
40136#define RDC_MRC_D3W_SHIFT (6U)
40137/*! D3W - Domain 3 Write Access to Region
40138 * 0b0..Processing Domain 3 does not have Write access to the memory region
40139 * 0b1..Processing Domain 3 has Read access to the memory region
40140 */
40141#define RDC_MRC_D3W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D3W_SHIFT)) & RDC_MRC_D3W_MASK)
40142#define RDC_MRC_D3R_MASK (0x80U)
40143#define RDC_MRC_D3R_SHIFT (7U)
40144/*! D3R - Domain 3 Read Access to Region
40145 * 0b0..Processing Domain 3 does not have Read access to the memory region
40146 * 0b1..Processing Domain 3 has Read access to the memory region
40147 */
40148#define RDC_MRC_D3R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D3R_SHIFT)) & RDC_MRC_D3R_MASK)
40149#define RDC_MRC_ENA_MASK (0x40000000U)
40150#define RDC_MRC_ENA_SHIFT (30U)
40151/*! ENA - Region Enable
40152 * 0b0..Memory region is not defined or restricted.
40153 * 0b1..Memory boundaries, domain permissions and controls are in effect.
40154 */
40155#define RDC_MRC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_ENA_SHIFT)) & RDC_MRC_ENA_MASK)
40156#define RDC_MRC_LCK_MASK (0x80000000U)
40157#define RDC_MRC_LCK_SHIFT (31U)
40158/*! LCK - Region Lock
40159 * 0b0..No Lock. All fields in this register may be modified.
40160 * 0b1..Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
40161 */
40162#define RDC_MRC_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_LCK_SHIFT)) & RDC_MRC_LCK_MASK)
40163/*! @} */
40164
40165/* The count of RDC_MRC */
40166#define RDC_MRC_COUNT (52U)
40167
40168/*! @name MRVS - Memory Region Violation Status */
40169/*! @{ */
40170#define RDC_MRVS_VDID_MASK (0x3U)
40171#define RDC_MRVS_VDID_SHIFT (0U)
40172/*! VDID - Violating Domain ID
40173 * 0b00..Processing Domain 0
40174 * 0b01..Processing Domain 1
40175 * 0b10..Processing Domain 2
40176 * 0b11..Processing Domain 3
40177 */
40178#define RDC_MRVS_VDID(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VDID_SHIFT)) & RDC_MRVS_VDID_MASK)
40179#define RDC_MRVS_AD_MASK (0x10U)
40180#define RDC_MRVS_AD_SHIFT (4U)
40181#define RDC_MRVS_AD(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_AD_SHIFT)) & RDC_MRVS_AD_MASK)
40182#define RDC_MRVS_VADR_MASK (0xFFFFFFE0U)
40183#define RDC_MRVS_VADR_SHIFT (5U)
40184#define RDC_MRVS_VADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VADR_SHIFT)) & RDC_MRVS_VADR_MASK)
40185/*! @} */
40186
40187/* The count of RDC_MRVS */
40188#define RDC_MRVS_COUNT (52U)
40189
40190/*!
40191 * @}
40192 */ /* end of group RDC_Register_Masks */
40193
40194/* RDC - Peripheral instance base addresses */
40195/** Peripheral RDC base address */
40196#define RDC_BASE (0x303D0000u)
40197/** Peripheral RDC base pointer */
40198#define RDC ((RDC_Type *)RDC_BASE)
40199/** Array initializer of RDC peripheral base addresses */
40200#define RDC_BASE_ADDRS \
40201 { \
40202 RDC_BASE \
40203 }
40204/** Array initializer of RDC peripheral base pointers */
40205#define RDC_BASE_PTRS \
40206 { \
40207 RDC \
40208 }
40209/** Interrupt vectors for the RDC peripheral type */
40210#define RDC_IRQS \
40211 { \
40212 RDC_IRQn \
40213 }
40214
40215/*!
40216 * @}
40217 */ /* end of group RDC_Peripheral_Access_Layer */
40218
40219/* ----------------------------------------------------------------------------
40220 -- RDC_SEMAPHORE Peripheral Access Layer
40221 ---------------------------------------------------------------------------- */
40222
40223/*!
40224 * @addtogroup RDC_SEMAPHORE_Peripheral_Access_Layer RDC_SEMAPHORE Peripheral Access Layer
40225 * @{
40226 */
40227
40228/** RDC_SEMAPHORE - Register Layout Typedef */
40229typedef struct
40230{
40231 __IO uint8_t GATE0; /**< Gate Register, offset: 0x0 */
40232 __IO uint8_t GATE1; /**< Gate Register, offset: 0x1 */
40233 __IO uint8_t GATE2; /**< Gate Register, offset: 0x2 */
40234 __IO uint8_t GATE3; /**< Gate Register, offset: 0x3 */
40235 __IO uint8_t GATE4; /**< Gate Register, offset: 0x4 */
40236 __IO uint8_t GATE5; /**< Gate Register, offset: 0x5 */
40237 __IO uint8_t GATE6; /**< Gate Register, offset: 0x6 */
40238 __IO uint8_t GATE7; /**< Gate Register, offset: 0x7 */
40239 __IO uint8_t GATE8; /**< Gate Register, offset: 0x8 */
40240 __IO uint8_t GATE9; /**< Gate Register, offset: 0x9 */
40241 __IO uint8_t GATE10; /**< Gate Register, offset: 0xA */
40242 __IO uint8_t GATE11; /**< Gate Register, offset: 0xB */
40243 __IO uint8_t GATE12; /**< Gate Register, offset: 0xC */
40244 __IO uint8_t GATE13; /**< Gate Register, offset: 0xD */
40245 __IO uint8_t GATE14; /**< Gate Register, offset: 0xE */
40246 __IO uint8_t GATE15; /**< Gate Register, offset: 0xF */
40247 __IO uint8_t GATE16; /**< Gate Register, offset: 0x10 */
40248 __IO uint8_t GATE17; /**< Gate Register, offset: 0x11 */
40249 __IO uint8_t GATE18; /**< Gate Register, offset: 0x12 */
40250 __IO uint8_t GATE19; /**< Gate Register, offset: 0x13 */
40251 __IO uint8_t GATE20; /**< Gate Register, offset: 0x14 */
40252 __IO uint8_t GATE21; /**< Gate Register, offset: 0x15 */
40253 __IO uint8_t GATE22; /**< Gate Register, offset: 0x16 */
40254 __IO uint8_t GATE23; /**< Gate Register, offset: 0x17 */
40255 __IO uint8_t GATE24; /**< Gate Register, offset: 0x18 */
40256 __IO uint8_t GATE25; /**< Gate Register, offset: 0x19 */
40257 __IO uint8_t GATE26; /**< Gate Register, offset: 0x1A */
40258 __IO uint8_t GATE27; /**< Gate Register, offset: 0x1B */
40259 __IO uint8_t GATE28; /**< Gate Register, offset: 0x1C */
40260 __IO uint8_t GATE29; /**< Gate Register, offset: 0x1D */
40261 __IO uint8_t GATE30; /**< Gate Register, offset: 0x1E */
40262 __IO uint8_t GATE31; /**< Gate Register, offset: 0x1F */
40263 __IO uint8_t GATE32; /**< Gate Register, offset: 0x20 */
40264 __IO uint8_t GATE33; /**< Gate Register, offset: 0x21 */
40265 __IO uint8_t GATE34; /**< Gate Register, offset: 0x22 */
40266 __IO uint8_t GATE35; /**< Gate Register, offset: 0x23 */
40267 __IO uint8_t GATE36; /**< Gate Register, offset: 0x24 */
40268 __IO uint8_t GATE37; /**< Gate Register, offset: 0x25 */
40269 __IO uint8_t GATE38; /**< Gate Register, offset: 0x26 */
40270 __IO uint8_t GATE39; /**< Gate Register, offset: 0x27 */
40271 __IO uint8_t GATE40; /**< Gate Register, offset: 0x28 */
40272 __IO uint8_t GATE41; /**< Gate Register, offset: 0x29 */
40273 __IO uint8_t GATE42; /**< Gate Register, offset: 0x2A */
40274 __IO uint8_t GATE43; /**< Gate Register, offset: 0x2B */
40275 __IO uint8_t GATE44; /**< Gate Register, offset: 0x2C */
40276 __IO uint8_t GATE45; /**< Gate Register, offset: 0x2D */
40277 __IO uint8_t GATE46; /**< Gate Register, offset: 0x2E */
40278 __IO uint8_t GATE47; /**< Gate Register, offset: 0x2F */
40279 __IO uint8_t GATE48; /**< Gate Register, offset: 0x30 */
40280 __IO uint8_t GATE49; /**< Gate Register, offset: 0x31 */
40281 __IO uint8_t GATE50; /**< Gate Register, offset: 0x32 */
40282 __IO uint8_t GATE51; /**< Gate Register, offset: 0x33 */
40283 __IO uint8_t GATE52; /**< Gate Register, offset: 0x34 */
40284 __IO uint8_t GATE53; /**< Gate Register, offset: 0x35 */
40285 __IO uint8_t GATE54; /**< Gate Register, offset: 0x36 */
40286 __IO uint8_t GATE55; /**< Gate Register, offset: 0x37 */
40287 __IO uint8_t GATE56; /**< Gate Register, offset: 0x38 */
40288 __IO uint8_t GATE57; /**< Gate Register, offset: 0x39 */
40289 __IO uint8_t GATE58; /**< Gate Register, offset: 0x3A */
40290 __IO uint8_t GATE59; /**< Gate Register, offset: 0x3B */
40291 __IO uint8_t GATE60; /**< Gate Register, offset: 0x3C */
40292 __IO uint8_t GATE61; /**< Gate Register, offset: 0x3D */
40293 __IO uint8_t GATE62; /**< Gate Register, offset: 0x3E */
40294 __IO uint8_t GATE63; /**< Gate Register, offset: 0x3F */
40295 union
40296 { /* offset: 0x40 */
40297 __IO uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x40 */
40298 __IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x40 */
40299 };
40300} RDC_SEMAPHORE_Type;
40301
40302/* ----------------------------------------------------------------------------
40303 -- RDC_SEMAPHORE Register Masks
40304 ---------------------------------------------------------------------------- */
40305
40306/*!
40307 * @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks
40308 * @{
40309 */
40310
40311/*! @name GATE0 - Gate Register */
40312/*! @{ */
40313#define RDC_SEMAPHORE_GATE0_GTFSM_MASK (0xFU)
40314#define RDC_SEMAPHORE_GATE0_GTFSM_SHIFT (0U)
40315/*! GTFSM - Gate Finite State Machine.
40316 * 0b0000..The gate is unlocked (free).
40317 * 0b0001..The gate has been locked by processor with master_index = 0.
40318 * 0b0010..The gate has been locked by processor with master_index = 1.
40319 * 0b0011..The gate has been locked by processor with master_index = 2.
40320 * 0b0100..The gate has been locked by processor with master_index = 3.
40321 * 0b0101..The gate has been locked by processor with master_index = 4.
40322 * 0b0110..The gate has been locked by processor with master_index = 5.
40323 * 0b0111..The gate has been locked by processor with master_index = 6.
40324 * 0b1000..The gate has been locked by processor with master_index = 7.
40325 * 0b1001..The gate has been locked by processor with master_index = 8.
40326 * 0b1010..The gate has been locked by processor with master_index = 9.
40327 * 0b1011..The gate has been locked by processor with master_index = 10.
40328 * 0b1100..The gate has been locked by processor with master_index = 11.
40329 * 0b1101..The gate has been locked by processor with master_index = 12.
40330 * 0b1110..The gate has been locked by processor with master_index = 13.
40331 * 0b1111..The gate has been locked by processor with master_index = 14.
40332 */
40333#define RDC_SEMAPHORE_GATE0_GTFSM(x) \
40334 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE0_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE0_GTFSM_MASK)
40335#define RDC_SEMAPHORE_GATE0_LDOM_MASK (0x30U)
40336#define RDC_SEMAPHORE_GATE0_LDOM_SHIFT (4U)
40337/*! LDOM
40338 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
40339 * 0b01..The gate has been locked by domain 1.
40340 * 0b10..The gate has been locked by domain 2.
40341 * 0b11..The gate has been locked by domain 3.
40342 */
40343#define RDC_SEMAPHORE_GATE0_LDOM(x) \
40344 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE0_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE0_LDOM_MASK)
40345/*! @} */
40346
40347/*! @name GATE1 - Gate Register */
40348/*! @{ */
40349#define RDC_SEMAPHORE_GATE1_GTFSM_MASK (0xFU)
40350#define RDC_SEMAPHORE_GATE1_GTFSM_SHIFT (0U)
40351/*! GTFSM - Gate Finite State Machine.
40352 * 0b0000..The gate is unlocked (free).
40353 * 0b0001..The gate has been locked by processor with master_index = 0.
40354 * 0b0010..The gate has been locked by processor with master_index = 1.
40355 * 0b0011..The gate has been locked by processor with master_index = 2.
40356 * 0b0100..The gate has been locked by processor with master_index = 3.
40357 * 0b0101..The gate has been locked by processor with master_index = 4.
40358 * 0b0110..The gate has been locked by processor with master_index = 5.
40359 * 0b0111..The gate has been locked by processor with master_index = 6.
40360 * 0b1000..The gate has been locked by processor with master_index = 7.
40361 * 0b1001..The gate has been locked by processor with master_index = 8.
40362 * 0b1010..The gate has been locked by processor with master_index = 9.
40363 * 0b1011..The gate has been locked by processor with master_index = 10.
40364 * 0b1100..The gate has been locked by processor with master_index = 11.
40365 * 0b1101..The gate has been locked by processor with master_index = 12.
40366 * 0b1110..The gate has been locked by processor with master_index = 13.
40367 * 0b1111..The gate has been locked by processor with master_index = 14.
40368 */
40369#define RDC_SEMAPHORE_GATE1_GTFSM(x) \
40370 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE1_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE1_GTFSM_MASK)
40371#define RDC_SEMAPHORE_GATE1_LDOM_MASK (0x30U)
40372#define RDC_SEMAPHORE_GATE1_LDOM_SHIFT (4U)
40373/*! LDOM
40374 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
40375 * 0b01..The gate has been locked by domain 1.
40376 * 0b10..The gate has been locked by domain 2.
40377 * 0b11..The gate has been locked by domain 3.
40378 */
40379#define RDC_SEMAPHORE_GATE1_LDOM(x) \
40380 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE1_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE1_LDOM_MASK)
40381/*! @} */
40382
40383/*! @name GATE2 - Gate Register */
40384/*! @{ */
40385#define RDC_SEMAPHORE_GATE2_GTFSM_MASK (0xFU)
40386#define RDC_SEMAPHORE_GATE2_GTFSM_SHIFT (0U)
40387/*! GTFSM - Gate Finite State Machine.
40388 * 0b0000..The gate is unlocked (free).
40389 * 0b0001..The gate has been locked by processor with master_index = 0.
40390 * 0b0010..The gate has been locked by processor with master_index = 1.
40391 * 0b0011..The gate has been locked by processor with master_index = 2.
40392 * 0b0100..The gate has been locked by processor with master_index = 3.
40393 * 0b0101..The gate has been locked by processor with master_index = 4.
40394 * 0b0110..The gate has been locked by processor with master_index = 5.
40395 * 0b0111..The gate has been locked by processor with master_index = 6.
40396 * 0b1000..The gate has been locked by processor with master_index = 7.
40397 * 0b1001..The gate has been locked by processor with master_index = 8.
40398 * 0b1010..The gate has been locked by processor with master_index = 9.
40399 * 0b1011..The gate has been locked by processor with master_index = 10.
40400 * 0b1100..The gate has been locked by processor with master_index = 11.
40401 * 0b1101..The gate has been locked by processor with master_index = 12.
40402 * 0b1110..The gate has been locked by processor with master_index = 13.
40403 * 0b1111..The gate has been locked by processor with master_index = 14.
40404 */
40405#define RDC_SEMAPHORE_GATE2_GTFSM(x) \
40406 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE2_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE2_GTFSM_MASK)
40407#define RDC_SEMAPHORE_GATE2_LDOM_MASK (0x30U)
40408#define RDC_SEMAPHORE_GATE2_LDOM_SHIFT (4U)
40409/*! LDOM
40410 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
40411 * 0b01..The gate has been locked by domain 1.
40412 * 0b10..The gate has been locked by domain 2.
40413 * 0b11..The gate has been locked by domain 3.
40414 */
40415#define RDC_SEMAPHORE_GATE2_LDOM(x) \
40416 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE2_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE2_LDOM_MASK)
40417/*! @} */
40418
40419/*! @name GATE3 - Gate Register */
40420/*! @{ */
40421#define RDC_SEMAPHORE_GATE3_GTFSM_MASK (0xFU)
40422#define RDC_SEMAPHORE_GATE3_GTFSM_SHIFT (0U)
40423/*! GTFSM - Gate Finite State Machine.
40424 * 0b0000..The gate is unlocked (free).
40425 * 0b0001..The gate has been locked by processor with master_index = 0.
40426 * 0b0010..The gate has been locked by processor with master_index = 1.
40427 * 0b0011..The gate has been locked by processor with master_index = 2.
40428 * 0b0100..The gate has been locked by processor with master_index = 3.
40429 * 0b0101..The gate has been locked by processor with master_index = 4.
40430 * 0b0110..The gate has been locked by processor with master_index = 5.
40431 * 0b0111..The gate has been locked by processor with master_index = 6.
40432 * 0b1000..The gate has been locked by processor with master_index = 7.
40433 * 0b1001..The gate has been locked by processor with master_index = 8.
40434 * 0b1010..The gate has been locked by processor with master_index = 9.
40435 * 0b1011..The gate has been locked by processor with master_index = 10.
40436 * 0b1100..The gate has been locked by processor with master_index = 11.
40437 * 0b1101..The gate has been locked by processor with master_index = 12.
40438 * 0b1110..The gate has been locked by processor with master_index = 13.
40439 * 0b1111..The gate has been locked by processor with master_index = 14.
40440 */
40441#define RDC_SEMAPHORE_GATE3_GTFSM(x) \
40442 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE3_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE3_GTFSM_MASK)
40443#define RDC_SEMAPHORE_GATE3_LDOM_MASK (0x30U)
40444#define RDC_SEMAPHORE_GATE3_LDOM_SHIFT (4U)
40445/*! LDOM
40446 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
40447 * 0b01..The gate has been locked by domain 1.
40448 * 0b10..The gate has been locked by domain 2.
40449 * 0b11..The gate has been locked by domain 3.
40450 */
40451#define RDC_SEMAPHORE_GATE3_LDOM(x) \
40452 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE3_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE3_LDOM_MASK)
40453/*! @} */
40454
40455/*! @name GATE4 - Gate Register */
40456/*! @{ */
40457#define RDC_SEMAPHORE_GATE4_GTFSM_MASK (0xFU)
40458#define RDC_SEMAPHORE_GATE4_GTFSM_SHIFT (0U)
40459/*! GTFSM - Gate Finite State Machine.
40460 * 0b0000..The gate is unlocked (free).
40461 * 0b0001..The gate has been locked by processor with master_index = 0.
40462 * 0b0010..The gate has been locked by processor with master_index = 1.
40463 * 0b0011..The gate has been locked by processor with master_index = 2.
40464 * 0b0100..The gate has been locked by processor with master_index = 3.
40465 * 0b0101..The gate has been locked by processor with master_index = 4.
40466 * 0b0110..The gate has been locked by processor with master_index = 5.
40467 * 0b0111..The gate has been locked by processor with master_index = 6.
40468 * 0b1000..The gate has been locked by processor with master_index = 7.
40469 * 0b1001..The gate has been locked by processor with master_index = 8.
40470 * 0b1010..The gate has been locked by processor with master_index = 9.
40471 * 0b1011..The gate has been locked by processor with master_index = 10.
40472 * 0b1100..The gate has been locked by processor with master_index = 11.
40473 * 0b1101..The gate has been locked by processor with master_index = 12.
40474 * 0b1110..The gate has been locked by processor with master_index = 13.
40475 * 0b1111..The gate has been locked by processor with master_index = 14.
40476 */
40477#define RDC_SEMAPHORE_GATE4_GTFSM(x) \
40478 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE4_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE4_GTFSM_MASK)
40479#define RDC_SEMAPHORE_GATE4_LDOM_MASK (0x30U)
40480#define RDC_SEMAPHORE_GATE4_LDOM_SHIFT (4U)
40481/*! LDOM
40482 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
40483 * 0b01..The gate has been locked by domain 1.
40484 * 0b10..The gate has been locked by domain 2.
40485 * 0b11..The gate has been locked by domain 3.
40486 */
40487#define RDC_SEMAPHORE_GATE4_LDOM(x) \
40488 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE4_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE4_LDOM_MASK)
40489/*! @} */
40490
40491/*! @name GATE5 - Gate Register */
40492/*! @{ */
40493#define RDC_SEMAPHORE_GATE5_GTFSM_MASK (0xFU)
40494#define RDC_SEMAPHORE_GATE5_GTFSM_SHIFT (0U)
40495/*! GTFSM - Gate Finite State Machine.
40496 * 0b0000..The gate is unlocked (free).
40497 * 0b0001..The gate has been locked by processor with master_index = 0.
40498 * 0b0010..The gate has been locked by processor with master_index = 1.
40499 * 0b0011..The gate has been locked by processor with master_index = 2.
40500 * 0b0100..The gate has been locked by processor with master_index = 3.
40501 * 0b0101..The gate has been locked by processor with master_index = 4.
40502 * 0b0110..The gate has been locked by processor with master_index = 5.
40503 * 0b0111..The gate has been locked by processor with master_index = 6.
40504 * 0b1000..The gate has been locked by processor with master_index = 7.
40505 * 0b1001..The gate has been locked by processor with master_index = 8.
40506 * 0b1010..The gate has been locked by processor with master_index = 9.
40507 * 0b1011..The gate has been locked by processor with master_index = 10.
40508 * 0b1100..The gate has been locked by processor with master_index = 11.
40509 * 0b1101..The gate has been locked by processor with master_index = 12.
40510 * 0b1110..The gate has been locked by processor with master_index = 13.
40511 * 0b1111..The gate has been locked by processor with master_index = 14.
40512 */
40513#define RDC_SEMAPHORE_GATE5_GTFSM(x) \
40514 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE5_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE5_GTFSM_MASK)
40515#define RDC_SEMAPHORE_GATE5_LDOM_MASK (0x30U)
40516#define RDC_SEMAPHORE_GATE5_LDOM_SHIFT (4U)
40517/*! LDOM
40518 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
40519 * 0b01..The gate has been locked by domain 1.
40520 * 0b10..The gate has been locked by domain 2.
40521 * 0b11..The gate has been locked by domain 3.
40522 */
40523#define RDC_SEMAPHORE_GATE5_LDOM(x) \
40524 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE5_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE5_LDOM_MASK)
40525/*! @} */
40526
40527/*! @name GATE6 - Gate Register */
40528/*! @{ */
40529#define RDC_SEMAPHORE_GATE6_GTFSM_MASK (0xFU)
40530#define RDC_SEMAPHORE_GATE6_GTFSM_SHIFT (0U)
40531/*! GTFSM - Gate Finite State Machine.
40532 * 0b0000..The gate is unlocked (free).
40533 * 0b0001..The gate has been locked by processor with master_index = 0.
40534 * 0b0010..The gate has been locked by processor with master_index = 1.
40535 * 0b0011..The gate has been locked by processor with master_index = 2.
40536 * 0b0100..The gate has been locked by processor with master_index = 3.
40537 * 0b0101..The gate has been locked by processor with master_index = 4.
40538 * 0b0110..The gate has been locked by processor with master_index = 5.
40539 * 0b0111..The gate has been locked by processor with master_index = 6.
40540 * 0b1000..The gate has been locked by processor with master_index = 7.
40541 * 0b1001..The gate has been locked by processor with master_index = 8.
40542 * 0b1010..The gate has been locked by processor with master_index = 9.
40543 * 0b1011..The gate has been locked by processor with master_index = 10.
40544 * 0b1100..The gate has been locked by processor with master_index = 11.
40545 * 0b1101..The gate has been locked by processor with master_index = 12.
40546 * 0b1110..The gate has been locked by processor with master_index = 13.
40547 * 0b1111..The gate has been locked by processor with master_index = 14.
40548 */
40549#define RDC_SEMAPHORE_GATE6_GTFSM(x) \
40550 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE6_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE6_GTFSM_MASK)
40551#define RDC_SEMAPHORE_GATE6_LDOM_MASK (0x30U)
40552#define RDC_SEMAPHORE_GATE6_LDOM_SHIFT (4U)
40553/*! LDOM
40554 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
40555 * 0b01..The gate has been locked by domain 1.
40556 * 0b10..The gate has been locked by domain 2.
40557 * 0b11..The gate has been locked by domain 3.
40558 */
40559#define RDC_SEMAPHORE_GATE6_LDOM(x) \
40560 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE6_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE6_LDOM_MASK)
40561/*! @} */
40562
40563/*! @name GATE7 - Gate Register */
40564/*! @{ */
40565#define RDC_SEMAPHORE_GATE7_GTFSM_MASK (0xFU)
40566#define RDC_SEMAPHORE_GATE7_GTFSM_SHIFT (0U)
40567/*! GTFSM - Gate Finite State Machine.
40568 * 0b0000..The gate is unlocked (free).
40569 * 0b0001..The gate has been locked by processor with master_index = 0.
40570 * 0b0010..The gate has been locked by processor with master_index = 1.
40571 * 0b0011..The gate has been locked by processor with master_index = 2.
40572 * 0b0100..The gate has been locked by processor with master_index = 3.
40573 * 0b0101..The gate has been locked by processor with master_index = 4.
40574 * 0b0110..The gate has been locked by processor with master_index = 5.
40575 * 0b0111..The gate has been locked by processor with master_index = 6.
40576 * 0b1000..The gate has been locked by processor with master_index = 7.
40577 * 0b1001..The gate has been locked by processor with master_index = 8.
40578 * 0b1010..The gate has been locked by processor with master_index = 9.
40579 * 0b1011..The gate has been locked by processor with master_index = 10.
40580 * 0b1100..The gate has been locked by processor with master_index = 11.
40581 * 0b1101..The gate has been locked by processor with master_index = 12.
40582 * 0b1110..The gate has been locked by processor with master_index = 13.
40583 * 0b1111..The gate has been locked by processor with master_index = 14.
40584 */
40585#define RDC_SEMAPHORE_GATE7_GTFSM(x) \
40586 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE7_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE7_GTFSM_MASK)
40587#define RDC_SEMAPHORE_GATE7_LDOM_MASK (0x30U)
40588#define RDC_SEMAPHORE_GATE7_LDOM_SHIFT (4U)
40589/*! LDOM
40590 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
40591 * 0b01..The gate has been locked by domain 1.
40592 * 0b10..The gate has been locked by domain 2.
40593 * 0b11..The gate has been locked by domain 3.
40594 */
40595#define RDC_SEMAPHORE_GATE7_LDOM(x) \
40596 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE7_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE7_LDOM_MASK)
40597/*! @} */
40598
40599/*! @name GATE8 - Gate Register */
40600/*! @{ */
40601#define RDC_SEMAPHORE_GATE8_GTFSM_MASK (0xFU)
40602#define RDC_SEMAPHORE_GATE8_GTFSM_SHIFT (0U)
40603/*! GTFSM - Gate Finite State Machine.
40604 * 0b0000..The gate is unlocked (free).
40605 * 0b0001..The gate has been locked by processor with master_index = 0.
40606 * 0b0010..The gate has been locked by processor with master_index = 1.
40607 * 0b0011..The gate has been locked by processor with master_index = 2.
40608 * 0b0100..The gate has been locked by processor with master_index = 3.
40609 * 0b0101..The gate has been locked by processor with master_index = 4.
40610 * 0b0110..The gate has been locked by processor with master_index = 5.
40611 * 0b0111..The gate has been locked by processor with master_index = 6.
40612 * 0b1000..The gate has been locked by processor with master_index = 7.
40613 * 0b1001..The gate has been locked by processor with master_index = 8.
40614 * 0b1010..The gate has been locked by processor with master_index = 9.
40615 * 0b1011..The gate has been locked by processor with master_index = 10.
40616 * 0b1100..The gate has been locked by processor with master_index = 11.
40617 * 0b1101..The gate has been locked by processor with master_index = 12.
40618 * 0b1110..The gate has been locked by processor with master_index = 13.
40619 * 0b1111..The gate has been locked by processor with master_index = 14.
40620 */
40621#define RDC_SEMAPHORE_GATE8_GTFSM(x) \
40622 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE8_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE8_GTFSM_MASK)
40623#define RDC_SEMAPHORE_GATE8_LDOM_MASK (0x30U)
40624#define RDC_SEMAPHORE_GATE8_LDOM_SHIFT (4U)
40625/*! LDOM
40626 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
40627 * 0b01..The gate has been locked by domain 1.
40628 * 0b10..The gate has been locked by domain 2.
40629 * 0b11..The gate has been locked by domain 3.
40630 */
40631#define RDC_SEMAPHORE_GATE8_LDOM(x) \
40632 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE8_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE8_LDOM_MASK)
40633/*! @} */
40634
40635/*! @name GATE9 - Gate Register */
40636/*! @{ */
40637#define RDC_SEMAPHORE_GATE9_GTFSM_MASK (0xFU)
40638#define RDC_SEMAPHORE_GATE9_GTFSM_SHIFT (0U)
40639/*! GTFSM - Gate Finite State Machine.
40640 * 0b0000..The gate is unlocked (free).
40641 * 0b0001..The gate has been locked by processor with master_index = 0.
40642 * 0b0010..The gate has been locked by processor with master_index = 1.
40643 * 0b0011..The gate has been locked by processor with master_index = 2.
40644 * 0b0100..The gate has been locked by processor with master_index = 3.
40645 * 0b0101..The gate has been locked by processor with master_index = 4.
40646 * 0b0110..The gate has been locked by processor with master_index = 5.
40647 * 0b0111..The gate has been locked by processor with master_index = 6.
40648 * 0b1000..The gate has been locked by processor with master_index = 7.
40649 * 0b1001..The gate has been locked by processor with master_index = 8.
40650 * 0b1010..The gate has been locked by processor with master_index = 9.
40651 * 0b1011..The gate has been locked by processor with master_index = 10.
40652 * 0b1100..The gate has been locked by processor with master_index = 11.
40653 * 0b1101..The gate has been locked by processor with master_index = 12.
40654 * 0b1110..The gate has been locked by processor with master_index = 13.
40655 * 0b1111..The gate has been locked by processor with master_index = 14.
40656 */
40657#define RDC_SEMAPHORE_GATE9_GTFSM(x) \
40658 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE9_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE9_GTFSM_MASK)
40659#define RDC_SEMAPHORE_GATE9_LDOM_MASK (0x30U)
40660#define RDC_SEMAPHORE_GATE9_LDOM_SHIFT (4U)
40661/*! LDOM
40662 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
40663 * 0b01..The gate has been locked by domain 1.
40664 * 0b10..The gate has been locked by domain 2.
40665 * 0b11..The gate has been locked by domain 3.
40666 */
40667#define RDC_SEMAPHORE_GATE9_LDOM(x) \
40668 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE9_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE9_LDOM_MASK)
40669/*! @} */
40670
40671/*! @name GATE10 - Gate Register */
40672/*! @{ */
40673#define RDC_SEMAPHORE_GATE10_GTFSM_MASK (0xFU)
40674#define RDC_SEMAPHORE_GATE10_GTFSM_SHIFT (0U)
40675/*! GTFSM - Gate Finite State Machine.
40676 * 0b0000..The gate is unlocked (free).
40677 * 0b0001..The gate has been locked by processor with master_index = 0.
40678 * 0b0010..The gate has been locked by processor with master_index = 1.
40679 * 0b0011..The gate has been locked by processor with master_index = 2.
40680 * 0b0100..The gate has been locked by processor with master_index = 3.
40681 * 0b0101..The gate has been locked by processor with master_index = 4.
40682 * 0b0110..The gate has been locked by processor with master_index = 5.
40683 * 0b0111..The gate has been locked by processor with master_index = 6.
40684 * 0b1000..The gate has been locked by processor with master_index = 7.
40685 * 0b1001..The gate has been locked by processor with master_index = 8.
40686 * 0b1010..The gate has been locked by processor with master_index = 9.
40687 * 0b1011..The gate has been locked by processor with master_index = 10.
40688 * 0b1100..The gate has been locked by processor with master_index = 11.
40689 * 0b1101..The gate has been locked by processor with master_index = 12.
40690 * 0b1110..The gate has been locked by processor with master_index = 13.
40691 * 0b1111..The gate has been locked by processor with master_index = 14.
40692 */
40693#define RDC_SEMAPHORE_GATE10_GTFSM(x) \
40694 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE10_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE10_GTFSM_MASK)
40695#define RDC_SEMAPHORE_GATE10_LDOM_MASK (0x30U)
40696#define RDC_SEMAPHORE_GATE10_LDOM_SHIFT (4U)
40697/*! LDOM
40698 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
40699 * 0b01..The gate has been locked by domain 1.
40700 * 0b10..The gate has been locked by domain 2.
40701 * 0b11..The gate has been locked by domain 3.
40702 */
40703#define RDC_SEMAPHORE_GATE10_LDOM(x) \
40704 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE10_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE10_LDOM_MASK)
40705/*! @} */
40706
40707/*! @name GATE11 - Gate Register */
40708/*! @{ */
40709#define RDC_SEMAPHORE_GATE11_GTFSM_MASK (0xFU)
40710#define RDC_SEMAPHORE_GATE11_GTFSM_SHIFT (0U)
40711/*! GTFSM - Gate Finite State Machine.
40712 * 0b0000..The gate is unlocked (free).
40713 * 0b0001..The gate has been locked by processor with master_index = 0.
40714 * 0b0010..The gate has been locked by processor with master_index = 1.
40715 * 0b0011..The gate has been locked by processor with master_index = 2.
40716 * 0b0100..The gate has been locked by processor with master_index = 3.
40717 * 0b0101..The gate has been locked by processor with master_index = 4.
40718 * 0b0110..The gate has been locked by processor with master_index = 5.
40719 * 0b0111..The gate has been locked by processor with master_index = 6.
40720 * 0b1000..The gate has been locked by processor with master_index = 7.
40721 * 0b1001..The gate has been locked by processor with master_index = 8.
40722 * 0b1010..The gate has been locked by processor with master_index = 9.
40723 * 0b1011..The gate has been locked by processor with master_index = 10.
40724 * 0b1100..The gate has been locked by processor with master_index = 11.
40725 * 0b1101..The gate has been locked by processor with master_index = 12.
40726 * 0b1110..The gate has been locked by processor with master_index = 13.
40727 * 0b1111..The gate has been locked by processor with master_index = 14.
40728 */
40729#define RDC_SEMAPHORE_GATE11_GTFSM(x) \
40730 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE11_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE11_GTFSM_MASK)
40731#define RDC_SEMAPHORE_GATE11_LDOM_MASK (0x30U)
40732#define RDC_SEMAPHORE_GATE11_LDOM_SHIFT (4U)
40733/*! LDOM
40734 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
40735 * 0b01..The gate has been locked by domain 1.
40736 * 0b10..The gate has been locked by domain 2.
40737 * 0b11..The gate has been locked by domain 3.
40738 */
40739#define RDC_SEMAPHORE_GATE11_LDOM(x) \
40740 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE11_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE11_LDOM_MASK)
40741/*! @} */
40742
40743/*! @name GATE12 - Gate Register */
40744/*! @{ */
40745#define RDC_SEMAPHORE_GATE12_GTFSM_MASK (0xFU)
40746#define RDC_SEMAPHORE_GATE12_GTFSM_SHIFT (0U)
40747/*! GTFSM - Gate Finite State Machine.
40748 * 0b0000..The gate is unlocked (free).
40749 * 0b0001..The gate has been locked by processor with master_index = 0.
40750 * 0b0010..The gate has been locked by processor with master_index = 1.
40751 * 0b0011..The gate has been locked by processor with master_index = 2.
40752 * 0b0100..The gate has been locked by processor with master_index = 3.
40753 * 0b0101..The gate has been locked by processor with master_index = 4.
40754 * 0b0110..The gate has been locked by processor with master_index = 5.
40755 * 0b0111..The gate has been locked by processor with master_index = 6.
40756 * 0b1000..The gate has been locked by processor with master_index = 7.
40757 * 0b1001..The gate has been locked by processor with master_index = 8.
40758 * 0b1010..The gate has been locked by processor with master_index = 9.
40759 * 0b1011..The gate has been locked by processor with master_index = 10.
40760 * 0b1100..The gate has been locked by processor with master_index = 11.
40761 * 0b1101..The gate has been locked by processor with master_index = 12.
40762 * 0b1110..The gate has been locked by processor with master_index = 13.
40763 * 0b1111..The gate has been locked by processor with master_index = 14.
40764 */
40765#define RDC_SEMAPHORE_GATE12_GTFSM(x) \
40766 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE12_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE12_GTFSM_MASK)
40767#define RDC_SEMAPHORE_GATE12_LDOM_MASK (0x30U)
40768#define RDC_SEMAPHORE_GATE12_LDOM_SHIFT (4U)
40769/*! LDOM
40770 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
40771 * 0b01..The gate has been locked by domain 1.
40772 * 0b10..The gate has been locked by domain 2.
40773 * 0b11..The gate has been locked by domain 3.
40774 */
40775#define RDC_SEMAPHORE_GATE12_LDOM(x) \
40776 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE12_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE12_LDOM_MASK)
40777/*! @} */
40778
40779/*! @name GATE13 - Gate Register */
40780/*! @{ */
40781#define RDC_SEMAPHORE_GATE13_GTFSM_MASK (0xFU)
40782#define RDC_SEMAPHORE_GATE13_GTFSM_SHIFT (0U)
40783/*! GTFSM - Gate Finite State Machine.
40784 * 0b0000..The gate is unlocked (free).
40785 * 0b0001..The gate has been locked by processor with master_index = 0.
40786 * 0b0010..The gate has been locked by processor with master_index = 1.
40787 * 0b0011..The gate has been locked by processor with master_index = 2.
40788 * 0b0100..The gate has been locked by processor with master_index = 3.
40789 * 0b0101..The gate has been locked by processor with master_index = 4.
40790 * 0b0110..The gate has been locked by processor with master_index = 5.
40791 * 0b0111..The gate has been locked by processor with master_index = 6.
40792 * 0b1000..The gate has been locked by processor with master_index = 7.
40793 * 0b1001..The gate has been locked by processor with master_index = 8.
40794 * 0b1010..The gate has been locked by processor with master_index = 9.
40795 * 0b1011..The gate has been locked by processor with master_index = 10.
40796 * 0b1100..The gate has been locked by processor with master_index = 11.
40797 * 0b1101..The gate has been locked by processor with master_index = 12.
40798 * 0b1110..The gate has been locked by processor with master_index = 13.
40799 * 0b1111..The gate has been locked by processor with master_index = 14.
40800 */
40801#define RDC_SEMAPHORE_GATE13_GTFSM(x) \
40802 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE13_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE13_GTFSM_MASK)
40803#define RDC_SEMAPHORE_GATE13_LDOM_MASK (0x30U)
40804#define RDC_SEMAPHORE_GATE13_LDOM_SHIFT (4U)
40805/*! LDOM
40806 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
40807 * 0b01..The gate has been locked by domain 1.
40808 * 0b10..The gate has been locked by domain 2.
40809 * 0b11..The gate has been locked by domain 3.
40810 */
40811#define RDC_SEMAPHORE_GATE13_LDOM(x) \
40812 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE13_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE13_LDOM_MASK)
40813/*! @} */
40814
40815/*! @name GATE14 - Gate Register */
40816/*! @{ */
40817#define RDC_SEMAPHORE_GATE14_GTFSM_MASK (0xFU)
40818#define RDC_SEMAPHORE_GATE14_GTFSM_SHIFT (0U)
40819/*! GTFSM - Gate Finite State Machine.
40820 * 0b0000..The gate is unlocked (free).
40821 * 0b0001..The gate has been locked by processor with master_index = 0.
40822 * 0b0010..The gate has been locked by processor with master_index = 1.
40823 * 0b0011..The gate has been locked by processor with master_index = 2.
40824 * 0b0100..The gate has been locked by processor with master_index = 3.
40825 * 0b0101..The gate has been locked by processor with master_index = 4.
40826 * 0b0110..The gate has been locked by processor with master_index = 5.
40827 * 0b0111..The gate has been locked by processor with master_index = 6.
40828 * 0b1000..The gate has been locked by processor with master_index = 7.
40829 * 0b1001..The gate has been locked by processor with master_index = 8.
40830 * 0b1010..The gate has been locked by processor with master_index = 9.
40831 * 0b1011..The gate has been locked by processor with master_index = 10.
40832 * 0b1100..The gate has been locked by processor with master_index = 11.
40833 * 0b1101..The gate has been locked by processor with master_index = 12.
40834 * 0b1110..The gate has been locked by processor with master_index = 13.
40835 * 0b1111..The gate has been locked by processor with master_index = 14.
40836 */
40837#define RDC_SEMAPHORE_GATE14_GTFSM(x) \
40838 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE14_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE14_GTFSM_MASK)
40839#define RDC_SEMAPHORE_GATE14_LDOM_MASK (0x30U)
40840#define RDC_SEMAPHORE_GATE14_LDOM_SHIFT (4U)
40841/*! LDOM
40842 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
40843 * 0b01..The gate has been locked by domain 1.
40844 * 0b10..The gate has been locked by domain 2.
40845 * 0b11..The gate has been locked by domain 3.
40846 */
40847#define RDC_SEMAPHORE_GATE14_LDOM(x) \
40848 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE14_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE14_LDOM_MASK)
40849/*! @} */
40850
40851/*! @name GATE15 - Gate Register */
40852/*! @{ */
40853#define RDC_SEMAPHORE_GATE15_GTFSM_MASK (0xFU)
40854#define RDC_SEMAPHORE_GATE15_GTFSM_SHIFT (0U)
40855/*! GTFSM - Gate Finite State Machine.
40856 * 0b0000..The gate is unlocked (free).
40857 * 0b0001..The gate has been locked by processor with master_index = 0.
40858 * 0b0010..The gate has been locked by processor with master_index = 1.
40859 * 0b0011..The gate has been locked by processor with master_index = 2.
40860 * 0b0100..The gate has been locked by processor with master_index = 3.
40861 * 0b0101..The gate has been locked by processor with master_index = 4.
40862 * 0b0110..The gate has been locked by processor with master_index = 5.
40863 * 0b0111..The gate has been locked by processor with master_index = 6.
40864 * 0b1000..The gate has been locked by processor with master_index = 7.
40865 * 0b1001..The gate has been locked by processor with master_index = 8.
40866 * 0b1010..The gate has been locked by processor with master_index = 9.
40867 * 0b1011..The gate has been locked by processor with master_index = 10.
40868 * 0b1100..The gate has been locked by processor with master_index = 11.
40869 * 0b1101..The gate has been locked by processor with master_index = 12.
40870 * 0b1110..The gate has been locked by processor with master_index = 13.
40871 * 0b1111..The gate has been locked by processor with master_index = 14.
40872 */
40873#define RDC_SEMAPHORE_GATE15_GTFSM(x) \
40874 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE15_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE15_GTFSM_MASK)
40875#define RDC_SEMAPHORE_GATE15_LDOM_MASK (0x30U)
40876#define RDC_SEMAPHORE_GATE15_LDOM_SHIFT (4U)
40877/*! LDOM
40878 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
40879 * 0b01..The gate has been locked by domain 1.
40880 * 0b10..The gate has been locked by domain 2.
40881 * 0b11..The gate has been locked by domain 3.
40882 */
40883#define RDC_SEMAPHORE_GATE15_LDOM(x) \
40884 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE15_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE15_LDOM_MASK)
40885/*! @} */
40886
40887/*! @name GATE16 - Gate Register */
40888/*! @{ */
40889#define RDC_SEMAPHORE_GATE16_GTFSM_MASK (0xFU)
40890#define RDC_SEMAPHORE_GATE16_GTFSM_SHIFT (0U)
40891/*! GTFSM - Gate Finite State Machine.
40892 * 0b0000..The gate is unlocked (free).
40893 * 0b0001..The gate has been locked by processor with master_index = 0.
40894 * 0b0010..The gate has been locked by processor with master_index = 1.
40895 * 0b0011..The gate has been locked by processor with master_index = 2.
40896 * 0b0100..The gate has been locked by processor with master_index = 3.
40897 * 0b0101..The gate has been locked by processor with master_index = 4.
40898 * 0b0110..The gate has been locked by processor with master_index = 5.
40899 * 0b0111..The gate has been locked by processor with master_index = 6.
40900 * 0b1000..The gate has been locked by processor with master_index = 7.
40901 * 0b1001..The gate has been locked by processor with master_index = 8.
40902 * 0b1010..The gate has been locked by processor with master_index = 9.
40903 * 0b1011..The gate has been locked by processor with master_index = 10.
40904 * 0b1100..The gate has been locked by processor with master_index = 11.
40905 * 0b1101..The gate has been locked by processor with master_index = 12.
40906 * 0b1110..The gate has been locked by processor with master_index = 13.
40907 * 0b1111..The gate has been locked by processor with master_index = 14.
40908 */
40909#define RDC_SEMAPHORE_GATE16_GTFSM(x) \
40910 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE16_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE16_GTFSM_MASK)
40911#define RDC_SEMAPHORE_GATE16_LDOM_MASK (0x30U)
40912#define RDC_SEMAPHORE_GATE16_LDOM_SHIFT (4U)
40913/*! LDOM
40914 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
40915 * 0b01..The gate has been locked by domain 1.
40916 * 0b10..The gate has been locked by domain 2.
40917 * 0b11..The gate has been locked by domain 3.
40918 */
40919#define RDC_SEMAPHORE_GATE16_LDOM(x) \
40920 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE16_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE16_LDOM_MASK)
40921/*! @} */
40922
40923/*! @name GATE17 - Gate Register */
40924/*! @{ */
40925#define RDC_SEMAPHORE_GATE17_GTFSM_MASK (0xFU)
40926#define RDC_SEMAPHORE_GATE17_GTFSM_SHIFT (0U)
40927/*! GTFSM - Gate Finite State Machine.
40928 * 0b0000..The gate is unlocked (free).
40929 * 0b0001..The gate has been locked by processor with master_index = 0.
40930 * 0b0010..The gate has been locked by processor with master_index = 1.
40931 * 0b0011..The gate has been locked by processor with master_index = 2.
40932 * 0b0100..The gate has been locked by processor with master_index = 3.
40933 * 0b0101..The gate has been locked by processor with master_index = 4.
40934 * 0b0110..The gate has been locked by processor with master_index = 5.
40935 * 0b0111..The gate has been locked by processor with master_index = 6.
40936 * 0b1000..The gate has been locked by processor with master_index = 7.
40937 * 0b1001..The gate has been locked by processor with master_index = 8.
40938 * 0b1010..The gate has been locked by processor with master_index = 9.
40939 * 0b1011..The gate has been locked by processor with master_index = 10.
40940 * 0b1100..The gate has been locked by processor with master_index = 11.
40941 * 0b1101..The gate has been locked by processor with master_index = 12.
40942 * 0b1110..The gate has been locked by processor with master_index = 13.
40943 * 0b1111..The gate has been locked by processor with master_index = 14.
40944 */
40945#define RDC_SEMAPHORE_GATE17_GTFSM(x) \
40946 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE17_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE17_GTFSM_MASK)
40947#define RDC_SEMAPHORE_GATE17_LDOM_MASK (0x30U)
40948#define RDC_SEMAPHORE_GATE17_LDOM_SHIFT (4U)
40949/*! LDOM
40950 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
40951 * 0b01..The gate has been locked by domain 1.
40952 * 0b10..The gate has been locked by domain 2.
40953 * 0b11..The gate has been locked by domain 3.
40954 */
40955#define RDC_SEMAPHORE_GATE17_LDOM(x) \
40956 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE17_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE17_LDOM_MASK)
40957/*! @} */
40958
40959/*! @name GATE18 - Gate Register */
40960/*! @{ */
40961#define RDC_SEMAPHORE_GATE18_GTFSM_MASK (0xFU)
40962#define RDC_SEMAPHORE_GATE18_GTFSM_SHIFT (0U)
40963/*! GTFSM - Gate Finite State Machine.
40964 * 0b0000..The gate is unlocked (free).
40965 * 0b0001..The gate has been locked by processor with master_index = 0.
40966 * 0b0010..The gate has been locked by processor with master_index = 1.
40967 * 0b0011..The gate has been locked by processor with master_index = 2.
40968 * 0b0100..The gate has been locked by processor with master_index = 3.
40969 * 0b0101..The gate has been locked by processor with master_index = 4.
40970 * 0b0110..The gate has been locked by processor with master_index = 5.
40971 * 0b0111..The gate has been locked by processor with master_index = 6.
40972 * 0b1000..The gate has been locked by processor with master_index = 7.
40973 * 0b1001..The gate has been locked by processor with master_index = 8.
40974 * 0b1010..The gate has been locked by processor with master_index = 9.
40975 * 0b1011..The gate has been locked by processor with master_index = 10.
40976 * 0b1100..The gate has been locked by processor with master_index = 11.
40977 * 0b1101..The gate has been locked by processor with master_index = 12.
40978 * 0b1110..The gate has been locked by processor with master_index = 13.
40979 * 0b1111..The gate has been locked by processor with master_index = 14.
40980 */
40981#define RDC_SEMAPHORE_GATE18_GTFSM(x) \
40982 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE18_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE18_GTFSM_MASK)
40983#define RDC_SEMAPHORE_GATE18_LDOM_MASK (0x30U)
40984#define RDC_SEMAPHORE_GATE18_LDOM_SHIFT (4U)
40985/*! LDOM
40986 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
40987 * 0b01..The gate has been locked by domain 1.
40988 * 0b10..The gate has been locked by domain 2.
40989 * 0b11..The gate has been locked by domain 3.
40990 */
40991#define RDC_SEMAPHORE_GATE18_LDOM(x) \
40992 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE18_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE18_LDOM_MASK)
40993/*! @} */
40994
40995/*! @name GATE19 - Gate Register */
40996/*! @{ */
40997#define RDC_SEMAPHORE_GATE19_GTFSM_MASK (0xFU)
40998#define RDC_SEMAPHORE_GATE19_GTFSM_SHIFT (0U)
40999/*! GTFSM - Gate Finite State Machine.
41000 * 0b0000..The gate is unlocked (free).
41001 * 0b0001..The gate has been locked by processor with master_index = 0.
41002 * 0b0010..The gate has been locked by processor with master_index = 1.
41003 * 0b0011..The gate has been locked by processor with master_index = 2.
41004 * 0b0100..The gate has been locked by processor with master_index = 3.
41005 * 0b0101..The gate has been locked by processor with master_index = 4.
41006 * 0b0110..The gate has been locked by processor with master_index = 5.
41007 * 0b0111..The gate has been locked by processor with master_index = 6.
41008 * 0b1000..The gate has been locked by processor with master_index = 7.
41009 * 0b1001..The gate has been locked by processor with master_index = 8.
41010 * 0b1010..The gate has been locked by processor with master_index = 9.
41011 * 0b1011..The gate has been locked by processor with master_index = 10.
41012 * 0b1100..The gate has been locked by processor with master_index = 11.
41013 * 0b1101..The gate has been locked by processor with master_index = 12.
41014 * 0b1110..The gate has been locked by processor with master_index = 13.
41015 * 0b1111..The gate has been locked by processor with master_index = 14.
41016 */
41017#define RDC_SEMAPHORE_GATE19_GTFSM(x) \
41018 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE19_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE19_GTFSM_MASK)
41019#define RDC_SEMAPHORE_GATE19_LDOM_MASK (0x30U)
41020#define RDC_SEMAPHORE_GATE19_LDOM_SHIFT (4U)
41021/*! LDOM
41022 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41023 * 0b01..The gate has been locked by domain 1.
41024 * 0b10..The gate has been locked by domain 2.
41025 * 0b11..The gate has been locked by domain 3.
41026 */
41027#define RDC_SEMAPHORE_GATE19_LDOM(x) \
41028 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE19_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE19_LDOM_MASK)
41029/*! @} */
41030
41031/*! @name GATE20 - Gate Register */
41032/*! @{ */
41033#define RDC_SEMAPHORE_GATE20_GTFSM_MASK (0xFU)
41034#define RDC_SEMAPHORE_GATE20_GTFSM_SHIFT (0U)
41035/*! GTFSM - Gate Finite State Machine.
41036 * 0b0000..The gate is unlocked (free).
41037 * 0b0001..The gate has been locked by processor with master_index = 0.
41038 * 0b0010..The gate has been locked by processor with master_index = 1.
41039 * 0b0011..The gate has been locked by processor with master_index = 2.
41040 * 0b0100..The gate has been locked by processor with master_index = 3.
41041 * 0b0101..The gate has been locked by processor with master_index = 4.
41042 * 0b0110..The gate has been locked by processor with master_index = 5.
41043 * 0b0111..The gate has been locked by processor with master_index = 6.
41044 * 0b1000..The gate has been locked by processor with master_index = 7.
41045 * 0b1001..The gate has been locked by processor with master_index = 8.
41046 * 0b1010..The gate has been locked by processor with master_index = 9.
41047 * 0b1011..The gate has been locked by processor with master_index = 10.
41048 * 0b1100..The gate has been locked by processor with master_index = 11.
41049 * 0b1101..The gate has been locked by processor with master_index = 12.
41050 * 0b1110..The gate has been locked by processor with master_index = 13.
41051 * 0b1111..The gate has been locked by processor with master_index = 14.
41052 */
41053#define RDC_SEMAPHORE_GATE20_GTFSM(x) \
41054 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE20_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE20_GTFSM_MASK)
41055#define RDC_SEMAPHORE_GATE20_LDOM_MASK (0x30U)
41056#define RDC_SEMAPHORE_GATE20_LDOM_SHIFT (4U)
41057/*! LDOM
41058 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41059 * 0b01..The gate has been locked by domain 1.
41060 * 0b10..The gate has been locked by domain 2.
41061 * 0b11..The gate has been locked by domain 3.
41062 */
41063#define RDC_SEMAPHORE_GATE20_LDOM(x) \
41064 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE20_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE20_LDOM_MASK)
41065/*! @} */
41066
41067/*! @name GATE21 - Gate Register */
41068/*! @{ */
41069#define RDC_SEMAPHORE_GATE21_GTFSM_MASK (0xFU)
41070#define RDC_SEMAPHORE_GATE21_GTFSM_SHIFT (0U)
41071/*! GTFSM - Gate Finite State Machine.
41072 * 0b0000..The gate is unlocked (free).
41073 * 0b0001..The gate has been locked by processor with master_index = 0.
41074 * 0b0010..The gate has been locked by processor with master_index = 1.
41075 * 0b0011..The gate has been locked by processor with master_index = 2.
41076 * 0b0100..The gate has been locked by processor with master_index = 3.
41077 * 0b0101..The gate has been locked by processor with master_index = 4.
41078 * 0b0110..The gate has been locked by processor with master_index = 5.
41079 * 0b0111..The gate has been locked by processor with master_index = 6.
41080 * 0b1000..The gate has been locked by processor with master_index = 7.
41081 * 0b1001..The gate has been locked by processor with master_index = 8.
41082 * 0b1010..The gate has been locked by processor with master_index = 9.
41083 * 0b1011..The gate has been locked by processor with master_index = 10.
41084 * 0b1100..The gate has been locked by processor with master_index = 11.
41085 * 0b1101..The gate has been locked by processor with master_index = 12.
41086 * 0b1110..The gate has been locked by processor with master_index = 13.
41087 * 0b1111..The gate has been locked by processor with master_index = 14.
41088 */
41089#define RDC_SEMAPHORE_GATE21_GTFSM(x) \
41090 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE21_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE21_GTFSM_MASK)
41091#define RDC_SEMAPHORE_GATE21_LDOM_MASK (0x30U)
41092#define RDC_SEMAPHORE_GATE21_LDOM_SHIFT (4U)
41093/*! LDOM
41094 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41095 * 0b01..The gate has been locked by domain 1.
41096 * 0b10..The gate has been locked by domain 2.
41097 * 0b11..The gate has been locked by domain 3.
41098 */
41099#define RDC_SEMAPHORE_GATE21_LDOM(x) \
41100 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE21_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE21_LDOM_MASK)
41101/*! @} */
41102
41103/*! @name GATE22 - Gate Register */
41104/*! @{ */
41105#define RDC_SEMAPHORE_GATE22_GTFSM_MASK (0xFU)
41106#define RDC_SEMAPHORE_GATE22_GTFSM_SHIFT (0U)
41107/*! GTFSM - Gate Finite State Machine.
41108 * 0b0000..The gate is unlocked (free).
41109 * 0b0001..The gate has been locked by processor with master_index = 0.
41110 * 0b0010..The gate has been locked by processor with master_index = 1.
41111 * 0b0011..The gate has been locked by processor with master_index = 2.
41112 * 0b0100..The gate has been locked by processor with master_index = 3.
41113 * 0b0101..The gate has been locked by processor with master_index = 4.
41114 * 0b0110..The gate has been locked by processor with master_index = 5.
41115 * 0b0111..The gate has been locked by processor with master_index = 6.
41116 * 0b1000..The gate has been locked by processor with master_index = 7.
41117 * 0b1001..The gate has been locked by processor with master_index = 8.
41118 * 0b1010..The gate has been locked by processor with master_index = 9.
41119 * 0b1011..The gate has been locked by processor with master_index = 10.
41120 * 0b1100..The gate has been locked by processor with master_index = 11.
41121 * 0b1101..The gate has been locked by processor with master_index = 12.
41122 * 0b1110..The gate has been locked by processor with master_index = 13.
41123 * 0b1111..The gate has been locked by processor with master_index = 14.
41124 */
41125#define RDC_SEMAPHORE_GATE22_GTFSM(x) \
41126 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE22_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE22_GTFSM_MASK)
41127#define RDC_SEMAPHORE_GATE22_LDOM_MASK (0x30U)
41128#define RDC_SEMAPHORE_GATE22_LDOM_SHIFT (4U)
41129/*! LDOM
41130 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41131 * 0b01..The gate has been locked by domain 1.
41132 * 0b10..The gate has been locked by domain 2.
41133 * 0b11..The gate has been locked by domain 3.
41134 */
41135#define RDC_SEMAPHORE_GATE22_LDOM(x) \
41136 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE22_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE22_LDOM_MASK)
41137/*! @} */
41138
41139/*! @name GATE23 - Gate Register */
41140/*! @{ */
41141#define RDC_SEMAPHORE_GATE23_GTFSM_MASK (0xFU)
41142#define RDC_SEMAPHORE_GATE23_GTFSM_SHIFT (0U)
41143/*! GTFSM - Gate Finite State Machine.
41144 * 0b0000..The gate is unlocked (free).
41145 * 0b0001..The gate has been locked by processor with master_index = 0.
41146 * 0b0010..The gate has been locked by processor with master_index = 1.
41147 * 0b0011..The gate has been locked by processor with master_index = 2.
41148 * 0b0100..The gate has been locked by processor with master_index = 3.
41149 * 0b0101..The gate has been locked by processor with master_index = 4.
41150 * 0b0110..The gate has been locked by processor with master_index = 5.
41151 * 0b0111..The gate has been locked by processor with master_index = 6.
41152 * 0b1000..The gate has been locked by processor with master_index = 7.
41153 * 0b1001..The gate has been locked by processor with master_index = 8.
41154 * 0b1010..The gate has been locked by processor with master_index = 9.
41155 * 0b1011..The gate has been locked by processor with master_index = 10.
41156 * 0b1100..The gate has been locked by processor with master_index = 11.
41157 * 0b1101..The gate has been locked by processor with master_index = 12.
41158 * 0b1110..The gate has been locked by processor with master_index = 13.
41159 * 0b1111..The gate has been locked by processor with master_index = 14.
41160 */
41161#define RDC_SEMAPHORE_GATE23_GTFSM(x) \
41162 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE23_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE23_GTFSM_MASK)
41163#define RDC_SEMAPHORE_GATE23_LDOM_MASK (0x30U)
41164#define RDC_SEMAPHORE_GATE23_LDOM_SHIFT (4U)
41165/*! LDOM
41166 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41167 * 0b01..The gate has been locked by domain 1.
41168 * 0b10..The gate has been locked by domain 2.
41169 * 0b11..The gate has been locked by domain 3.
41170 */
41171#define RDC_SEMAPHORE_GATE23_LDOM(x) \
41172 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE23_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE23_LDOM_MASK)
41173/*! @} */
41174
41175/*! @name GATE24 - Gate Register */
41176/*! @{ */
41177#define RDC_SEMAPHORE_GATE24_GTFSM_MASK (0xFU)
41178#define RDC_SEMAPHORE_GATE24_GTFSM_SHIFT (0U)
41179/*! GTFSM - Gate Finite State Machine.
41180 * 0b0000..The gate is unlocked (free).
41181 * 0b0001..The gate has been locked by processor with master_index = 0.
41182 * 0b0010..The gate has been locked by processor with master_index = 1.
41183 * 0b0011..The gate has been locked by processor with master_index = 2.
41184 * 0b0100..The gate has been locked by processor with master_index = 3.
41185 * 0b0101..The gate has been locked by processor with master_index = 4.
41186 * 0b0110..The gate has been locked by processor with master_index = 5.
41187 * 0b0111..The gate has been locked by processor with master_index = 6.
41188 * 0b1000..The gate has been locked by processor with master_index = 7.
41189 * 0b1001..The gate has been locked by processor with master_index = 8.
41190 * 0b1010..The gate has been locked by processor with master_index = 9.
41191 * 0b1011..The gate has been locked by processor with master_index = 10.
41192 * 0b1100..The gate has been locked by processor with master_index = 11.
41193 * 0b1101..The gate has been locked by processor with master_index = 12.
41194 * 0b1110..The gate has been locked by processor with master_index = 13.
41195 * 0b1111..The gate has been locked by processor with master_index = 14.
41196 */
41197#define RDC_SEMAPHORE_GATE24_GTFSM(x) \
41198 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE24_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE24_GTFSM_MASK)
41199#define RDC_SEMAPHORE_GATE24_LDOM_MASK (0x30U)
41200#define RDC_SEMAPHORE_GATE24_LDOM_SHIFT (4U)
41201/*! LDOM
41202 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41203 * 0b01..The gate has been locked by domain 1.
41204 * 0b10..The gate has been locked by domain 2.
41205 * 0b11..The gate has been locked by domain 3.
41206 */
41207#define RDC_SEMAPHORE_GATE24_LDOM(x) \
41208 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE24_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE24_LDOM_MASK)
41209/*! @} */
41210
41211/*! @name GATE25 - Gate Register */
41212/*! @{ */
41213#define RDC_SEMAPHORE_GATE25_GTFSM_MASK (0xFU)
41214#define RDC_SEMAPHORE_GATE25_GTFSM_SHIFT (0U)
41215/*! GTFSM - Gate Finite State Machine.
41216 * 0b0000..The gate is unlocked (free).
41217 * 0b0001..The gate has been locked by processor with master_index = 0.
41218 * 0b0010..The gate has been locked by processor with master_index = 1.
41219 * 0b0011..The gate has been locked by processor with master_index = 2.
41220 * 0b0100..The gate has been locked by processor with master_index = 3.
41221 * 0b0101..The gate has been locked by processor with master_index = 4.
41222 * 0b0110..The gate has been locked by processor with master_index = 5.
41223 * 0b0111..The gate has been locked by processor with master_index = 6.
41224 * 0b1000..The gate has been locked by processor with master_index = 7.
41225 * 0b1001..The gate has been locked by processor with master_index = 8.
41226 * 0b1010..The gate has been locked by processor with master_index = 9.
41227 * 0b1011..The gate has been locked by processor with master_index = 10.
41228 * 0b1100..The gate has been locked by processor with master_index = 11.
41229 * 0b1101..The gate has been locked by processor with master_index = 12.
41230 * 0b1110..The gate has been locked by processor with master_index = 13.
41231 * 0b1111..The gate has been locked by processor with master_index = 14.
41232 */
41233#define RDC_SEMAPHORE_GATE25_GTFSM(x) \
41234 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE25_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE25_GTFSM_MASK)
41235#define RDC_SEMAPHORE_GATE25_LDOM_MASK (0x30U)
41236#define RDC_SEMAPHORE_GATE25_LDOM_SHIFT (4U)
41237/*! LDOM
41238 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41239 * 0b01..The gate has been locked by domain 1.
41240 * 0b10..The gate has been locked by domain 2.
41241 * 0b11..The gate has been locked by domain 3.
41242 */
41243#define RDC_SEMAPHORE_GATE25_LDOM(x) \
41244 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE25_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE25_LDOM_MASK)
41245/*! @} */
41246
41247/*! @name GATE26 - Gate Register */
41248/*! @{ */
41249#define RDC_SEMAPHORE_GATE26_GTFSM_MASK (0xFU)
41250#define RDC_SEMAPHORE_GATE26_GTFSM_SHIFT (0U)
41251/*! GTFSM - Gate Finite State Machine.
41252 * 0b0000..The gate is unlocked (free).
41253 * 0b0001..The gate has been locked by processor with master_index = 0.
41254 * 0b0010..The gate has been locked by processor with master_index = 1.
41255 * 0b0011..The gate has been locked by processor with master_index = 2.
41256 * 0b0100..The gate has been locked by processor with master_index = 3.
41257 * 0b0101..The gate has been locked by processor with master_index = 4.
41258 * 0b0110..The gate has been locked by processor with master_index = 5.
41259 * 0b0111..The gate has been locked by processor with master_index = 6.
41260 * 0b1000..The gate has been locked by processor with master_index = 7.
41261 * 0b1001..The gate has been locked by processor with master_index = 8.
41262 * 0b1010..The gate has been locked by processor with master_index = 9.
41263 * 0b1011..The gate has been locked by processor with master_index = 10.
41264 * 0b1100..The gate has been locked by processor with master_index = 11.
41265 * 0b1101..The gate has been locked by processor with master_index = 12.
41266 * 0b1110..The gate has been locked by processor with master_index = 13.
41267 * 0b1111..The gate has been locked by processor with master_index = 14.
41268 */
41269#define RDC_SEMAPHORE_GATE26_GTFSM(x) \
41270 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE26_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE26_GTFSM_MASK)
41271#define RDC_SEMAPHORE_GATE26_LDOM_MASK (0x30U)
41272#define RDC_SEMAPHORE_GATE26_LDOM_SHIFT (4U)
41273/*! LDOM
41274 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41275 * 0b01..The gate has been locked by domain 1.
41276 * 0b10..The gate has been locked by domain 2.
41277 * 0b11..The gate has been locked by domain 3.
41278 */
41279#define RDC_SEMAPHORE_GATE26_LDOM(x) \
41280 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE26_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE26_LDOM_MASK)
41281/*! @} */
41282
41283/*! @name GATE27 - Gate Register */
41284/*! @{ */
41285#define RDC_SEMAPHORE_GATE27_GTFSM_MASK (0xFU)
41286#define RDC_SEMAPHORE_GATE27_GTFSM_SHIFT (0U)
41287/*! GTFSM - Gate Finite State Machine.
41288 * 0b0000..The gate is unlocked (free).
41289 * 0b0001..The gate has been locked by processor with master_index = 0.
41290 * 0b0010..The gate has been locked by processor with master_index = 1.
41291 * 0b0011..The gate has been locked by processor with master_index = 2.
41292 * 0b0100..The gate has been locked by processor with master_index = 3.
41293 * 0b0101..The gate has been locked by processor with master_index = 4.
41294 * 0b0110..The gate has been locked by processor with master_index = 5.
41295 * 0b0111..The gate has been locked by processor with master_index = 6.
41296 * 0b1000..The gate has been locked by processor with master_index = 7.
41297 * 0b1001..The gate has been locked by processor with master_index = 8.
41298 * 0b1010..The gate has been locked by processor with master_index = 9.
41299 * 0b1011..The gate has been locked by processor with master_index = 10.
41300 * 0b1100..The gate has been locked by processor with master_index = 11.
41301 * 0b1101..The gate has been locked by processor with master_index = 12.
41302 * 0b1110..The gate has been locked by processor with master_index = 13.
41303 * 0b1111..The gate has been locked by processor with master_index = 14.
41304 */
41305#define RDC_SEMAPHORE_GATE27_GTFSM(x) \
41306 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE27_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE27_GTFSM_MASK)
41307#define RDC_SEMAPHORE_GATE27_LDOM_MASK (0x30U)
41308#define RDC_SEMAPHORE_GATE27_LDOM_SHIFT (4U)
41309/*! LDOM
41310 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41311 * 0b01..The gate has been locked by domain 1.
41312 * 0b10..The gate has been locked by domain 2.
41313 * 0b11..The gate has been locked by domain 3.
41314 */
41315#define RDC_SEMAPHORE_GATE27_LDOM(x) \
41316 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE27_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE27_LDOM_MASK)
41317/*! @} */
41318
41319/*! @name GATE28 - Gate Register */
41320/*! @{ */
41321#define RDC_SEMAPHORE_GATE28_GTFSM_MASK (0xFU)
41322#define RDC_SEMAPHORE_GATE28_GTFSM_SHIFT (0U)
41323/*! GTFSM - Gate Finite State Machine.
41324 * 0b0000..The gate is unlocked (free).
41325 * 0b0001..The gate has been locked by processor with master_index = 0.
41326 * 0b0010..The gate has been locked by processor with master_index = 1.
41327 * 0b0011..The gate has been locked by processor with master_index = 2.
41328 * 0b0100..The gate has been locked by processor with master_index = 3.
41329 * 0b0101..The gate has been locked by processor with master_index = 4.
41330 * 0b0110..The gate has been locked by processor with master_index = 5.
41331 * 0b0111..The gate has been locked by processor with master_index = 6.
41332 * 0b1000..The gate has been locked by processor with master_index = 7.
41333 * 0b1001..The gate has been locked by processor with master_index = 8.
41334 * 0b1010..The gate has been locked by processor with master_index = 9.
41335 * 0b1011..The gate has been locked by processor with master_index = 10.
41336 * 0b1100..The gate has been locked by processor with master_index = 11.
41337 * 0b1101..The gate has been locked by processor with master_index = 12.
41338 * 0b1110..The gate has been locked by processor with master_index = 13.
41339 * 0b1111..The gate has been locked by processor with master_index = 14.
41340 */
41341#define RDC_SEMAPHORE_GATE28_GTFSM(x) \
41342 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE28_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE28_GTFSM_MASK)
41343#define RDC_SEMAPHORE_GATE28_LDOM_MASK (0x30U)
41344#define RDC_SEMAPHORE_GATE28_LDOM_SHIFT (4U)
41345/*! LDOM
41346 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41347 * 0b01..The gate has been locked by domain 1.
41348 * 0b10..The gate has been locked by domain 2.
41349 * 0b11..The gate has been locked by domain 3.
41350 */
41351#define RDC_SEMAPHORE_GATE28_LDOM(x) \
41352 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE28_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE28_LDOM_MASK)
41353/*! @} */
41354
41355/*! @name GATE29 - Gate Register */
41356/*! @{ */
41357#define RDC_SEMAPHORE_GATE29_GTFSM_MASK (0xFU)
41358#define RDC_SEMAPHORE_GATE29_GTFSM_SHIFT (0U)
41359/*! GTFSM - Gate Finite State Machine.
41360 * 0b0000..The gate is unlocked (free).
41361 * 0b0001..The gate has been locked by processor with master_index = 0.
41362 * 0b0010..The gate has been locked by processor with master_index = 1.
41363 * 0b0011..The gate has been locked by processor with master_index = 2.
41364 * 0b0100..The gate has been locked by processor with master_index = 3.
41365 * 0b0101..The gate has been locked by processor with master_index = 4.
41366 * 0b0110..The gate has been locked by processor with master_index = 5.
41367 * 0b0111..The gate has been locked by processor with master_index = 6.
41368 * 0b1000..The gate has been locked by processor with master_index = 7.
41369 * 0b1001..The gate has been locked by processor with master_index = 8.
41370 * 0b1010..The gate has been locked by processor with master_index = 9.
41371 * 0b1011..The gate has been locked by processor with master_index = 10.
41372 * 0b1100..The gate has been locked by processor with master_index = 11.
41373 * 0b1101..The gate has been locked by processor with master_index = 12.
41374 * 0b1110..The gate has been locked by processor with master_index = 13.
41375 * 0b1111..The gate has been locked by processor with master_index = 14.
41376 */
41377#define RDC_SEMAPHORE_GATE29_GTFSM(x) \
41378 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE29_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE29_GTFSM_MASK)
41379#define RDC_SEMAPHORE_GATE29_LDOM_MASK (0x30U)
41380#define RDC_SEMAPHORE_GATE29_LDOM_SHIFT (4U)
41381/*! LDOM
41382 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41383 * 0b01..The gate has been locked by domain 1.
41384 * 0b10..The gate has been locked by domain 2.
41385 * 0b11..The gate has been locked by domain 3.
41386 */
41387#define RDC_SEMAPHORE_GATE29_LDOM(x) \
41388 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE29_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE29_LDOM_MASK)
41389/*! @} */
41390
41391/*! @name GATE30 - Gate Register */
41392/*! @{ */
41393#define RDC_SEMAPHORE_GATE30_GTFSM_MASK (0xFU)
41394#define RDC_SEMAPHORE_GATE30_GTFSM_SHIFT (0U)
41395/*! GTFSM - Gate Finite State Machine.
41396 * 0b0000..The gate is unlocked (free).
41397 * 0b0001..The gate has been locked by processor with master_index = 0.
41398 * 0b0010..The gate has been locked by processor with master_index = 1.
41399 * 0b0011..The gate has been locked by processor with master_index = 2.
41400 * 0b0100..The gate has been locked by processor with master_index = 3.
41401 * 0b0101..The gate has been locked by processor with master_index = 4.
41402 * 0b0110..The gate has been locked by processor with master_index = 5.
41403 * 0b0111..The gate has been locked by processor with master_index = 6.
41404 * 0b1000..The gate has been locked by processor with master_index = 7.
41405 * 0b1001..The gate has been locked by processor with master_index = 8.
41406 * 0b1010..The gate has been locked by processor with master_index = 9.
41407 * 0b1011..The gate has been locked by processor with master_index = 10.
41408 * 0b1100..The gate has been locked by processor with master_index = 11.
41409 * 0b1101..The gate has been locked by processor with master_index = 12.
41410 * 0b1110..The gate has been locked by processor with master_index = 13.
41411 * 0b1111..The gate has been locked by processor with master_index = 14.
41412 */
41413#define RDC_SEMAPHORE_GATE30_GTFSM(x) \
41414 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE30_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE30_GTFSM_MASK)
41415#define RDC_SEMAPHORE_GATE30_LDOM_MASK (0x30U)
41416#define RDC_SEMAPHORE_GATE30_LDOM_SHIFT (4U)
41417/*! LDOM
41418 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41419 * 0b01..The gate has been locked by domain 1.
41420 * 0b10..The gate has been locked by domain 2.
41421 * 0b11..The gate has been locked by domain 3.
41422 */
41423#define RDC_SEMAPHORE_GATE30_LDOM(x) \
41424 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE30_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE30_LDOM_MASK)
41425/*! @} */
41426
41427/*! @name GATE31 - Gate Register */
41428/*! @{ */
41429#define RDC_SEMAPHORE_GATE31_GTFSM_MASK (0xFU)
41430#define RDC_SEMAPHORE_GATE31_GTFSM_SHIFT (0U)
41431/*! GTFSM - Gate Finite State Machine.
41432 * 0b0000..The gate is unlocked (free).
41433 * 0b0001..The gate has been locked by processor with master_index = 0.
41434 * 0b0010..The gate has been locked by processor with master_index = 1.
41435 * 0b0011..The gate has been locked by processor with master_index = 2.
41436 * 0b0100..The gate has been locked by processor with master_index = 3.
41437 * 0b0101..The gate has been locked by processor with master_index = 4.
41438 * 0b0110..The gate has been locked by processor with master_index = 5.
41439 * 0b0111..The gate has been locked by processor with master_index = 6.
41440 * 0b1000..The gate has been locked by processor with master_index = 7.
41441 * 0b1001..The gate has been locked by processor with master_index = 8.
41442 * 0b1010..The gate has been locked by processor with master_index = 9.
41443 * 0b1011..The gate has been locked by processor with master_index = 10.
41444 * 0b1100..The gate has been locked by processor with master_index = 11.
41445 * 0b1101..The gate has been locked by processor with master_index = 12.
41446 * 0b1110..The gate has been locked by processor with master_index = 13.
41447 * 0b1111..The gate has been locked by processor with master_index = 14.
41448 */
41449#define RDC_SEMAPHORE_GATE31_GTFSM(x) \
41450 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE31_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE31_GTFSM_MASK)
41451#define RDC_SEMAPHORE_GATE31_LDOM_MASK (0x30U)
41452#define RDC_SEMAPHORE_GATE31_LDOM_SHIFT (4U)
41453/*! LDOM
41454 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41455 * 0b01..The gate has been locked by domain 1.
41456 * 0b10..The gate has been locked by domain 2.
41457 * 0b11..The gate has been locked by domain 3.
41458 */
41459#define RDC_SEMAPHORE_GATE31_LDOM(x) \
41460 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE31_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE31_LDOM_MASK)
41461/*! @} */
41462
41463/*! @name GATE32 - Gate Register */
41464/*! @{ */
41465#define RDC_SEMAPHORE_GATE32_GTFSM_MASK (0xFU)
41466#define RDC_SEMAPHORE_GATE32_GTFSM_SHIFT (0U)
41467/*! GTFSM - Gate Finite State Machine.
41468 * 0b0000..The gate is unlocked (free).
41469 * 0b0001..The gate has been locked by processor with master_index = 0.
41470 * 0b0010..The gate has been locked by processor with master_index = 1.
41471 * 0b0011..The gate has been locked by processor with master_index = 2.
41472 * 0b0100..The gate has been locked by processor with master_index = 3.
41473 * 0b0101..The gate has been locked by processor with master_index = 4.
41474 * 0b0110..The gate has been locked by processor with master_index = 5.
41475 * 0b0111..The gate has been locked by processor with master_index = 6.
41476 * 0b1000..The gate has been locked by processor with master_index = 7.
41477 * 0b1001..The gate has been locked by processor with master_index = 8.
41478 * 0b1010..The gate has been locked by processor with master_index = 9.
41479 * 0b1011..The gate has been locked by processor with master_index = 10.
41480 * 0b1100..The gate has been locked by processor with master_index = 11.
41481 * 0b1101..The gate has been locked by processor with master_index = 12.
41482 * 0b1110..The gate has been locked by processor with master_index = 13.
41483 * 0b1111..The gate has been locked by processor with master_index = 14.
41484 */
41485#define RDC_SEMAPHORE_GATE32_GTFSM(x) \
41486 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE32_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE32_GTFSM_MASK)
41487#define RDC_SEMAPHORE_GATE32_LDOM_MASK (0x30U)
41488#define RDC_SEMAPHORE_GATE32_LDOM_SHIFT (4U)
41489/*! LDOM
41490 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41491 * 0b01..The gate has been locked by domain 1.
41492 * 0b10..The gate has been locked by domain 2.
41493 * 0b11..The gate has been locked by domain 3.
41494 */
41495#define RDC_SEMAPHORE_GATE32_LDOM(x) \
41496 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE32_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE32_LDOM_MASK)
41497/*! @} */
41498
41499/*! @name GATE33 - Gate Register */
41500/*! @{ */
41501#define RDC_SEMAPHORE_GATE33_GTFSM_MASK (0xFU)
41502#define RDC_SEMAPHORE_GATE33_GTFSM_SHIFT (0U)
41503/*! GTFSM - Gate Finite State Machine.
41504 * 0b0000..The gate is unlocked (free).
41505 * 0b0001..The gate has been locked by processor with master_index = 0.
41506 * 0b0010..The gate has been locked by processor with master_index = 1.
41507 * 0b0011..The gate has been locked by processor with master_index = 2.
41508 * 0b0100..The gate has been locked by processor with master_index = 3.
41509 * 0b0101..The gate has been locked by processor with master_index = 4.
41510 * 0b0110..The gate has been locked by processor with master_index = 5.
41511 * 0b0111..The gate has been locked by processor with master_index = 6.
41512 * 0b1000..The gate has been locked by processor with master_index = 7.
41513 * 0b1001..The gate has been locked by processor with master_index = 8.
41514 * 0b1010..The gate has been locked by processor with master_index = 9.
41515 * 0b1011..The gate has been locked by processor with master_index = 10.
41516 * 0b1100..The gate has been locked by processor with master_index = 11.
41517 * 0b1101..The gate has been locked by processor with master_index = 12.
41518 * 0b1110..The gate has been locked by processor with master_index = 13.
41519 * 0b1111..The gate has been locked by processor with master_index = 14.
41520 */
41521#define RDC_SEMAPHORE_GATE33_GTFSM(x) \
41522 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE33_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE33_GTFSM_MASK)
41523#define RDC_SEMAPHORE_GATE33_LDOM_MASK (0x30U)
41524#define RDC_SEMAPHORE_GATE33_LDOM_SHIFT (4U)
41525/*! LDOM
41526 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41527 * 0b01..The gate has been locked by domain 1.
41528 * 0b10..The gate has been locked by domain 2.
41529 * 0b11..The gate has been locked by domain 3.
41530 */
41531#define RDC_SEMAPHORE_GATE33_LDOM(x) \
41532 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE33_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE33_LDOM_MASK)
41533/*! @} */
41534
41535/*! @name GATE34 - Gate Register */
41536/*! @{ */
41537#define RDC_SEMAPHORE_GATE34_GTFSM_MASK (0xFU)
41538#define RDC_SEMAPHORE_GATE34_GTFSM_SHIFT (0U)
41539/*! GTFSM - Gate Finite State Machine.
41540 * 0b0000..The gate is unlocked (free).
41541 * 0b0001..The gate has been locked by processor with master_index = 0.
41542 * 0b0010..The gate has been locked by processor with master_index = 1.
41543 * 0b0011..The gate has been locked by processor with master_index = 2.
41544 * 0b0100..The gate has been locked by processor with master_index = 3.
41545 * 0b0101..The gate has been locked by processor with master_index = 4.
41546 * 0b0110..The gate has been locked by processor with master_index = 5.
41547 * 0b0111..The gate has been locked by processor with master_index = 6.
41548 * 0b1000..The gate has been locked by processor with master_index = 7.
41549 * 0b1001..The gate has been locked by processor with master_index = 8.
41550 * 0b1010..The gate has been locked by processor with master_index = 9.
41551 * 0b1011..The gate has been locked by processor with master_index = 10.
41552 * 0b1100..The gate has been locked by processor with master_index = 11.
41553 * 0b1101..The gate has been locked by processor with master_index = 12.
41554 * 0b1110..The gate has been locked by processor with master_index = 13.
41555 * 0b1111..The gate has been locked by processor with master_index = 14.
41556 */
41557#define RDC_SEMAPHORE_GATE34_GTFSM(x) \
41558 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE34_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE34_GTFSM_MASK)
41559#define RDC_SEMAPHORE_GATE34_LDOM_MASK (0x30U)
41560#define RDC_SEMAPHORE_GATE34_LDOM_SHIFT (4U)
41561/*! LDOM
41562 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41563 * 0b01..The gate has been locked by domain 1.
41564 * 0b10..The gate has been locked by domain 2.
41565 * 0b11..The gate has been locked by domain 3.
41566 */
41567#define RDC_SEMAPHORE_GATE34_LDOM(x) \
41568 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE34_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE34_LDOM_MASK)
41569/*! @} */
41570
41571/*! @name GATE35 - Gate Register */
41572/*! @{ */
41573#define RDC_SEMAPHORE_GATE35_GTFSM_MASK (0xFU)
41574#define RDC_SEMAPHORE_GATE35_GTFSM_SHIFT (0U)
41575/*! GTFSM - Gate Finite State Machine.
41576 * 0b0000..The gate is unlocked (free).
41577 * 0b0001..The gate has been locked by processor with master_index = 0.
41578 * 0b0010..The gate has been locked by processor with master_index = 1.
41579 * 0b0011..The gate has been locked by processor with master_index = 2.
41580 * 0b0100..The gate has been locked by processor with master_index = 3.
41581 * 0b0101..The gate has been locked by processor with master_index = 4.
41582 * 0b0110..The gate has been locked by processor with master_index = 5.
41583 * 0b0111..The gate has been locked by processor with master_index = 6.
41584 * 0b1000..The gate has been locked by processor with master_index = 7.
41585 * 0b1001..The gate has been locked by processor with master_index = 8.
41586 * 0b1010..The gate has been locked by processor with master_index = 9.
41587 * 0b1011..The gate has been locked by processor with master_index = 10.
41588 * 0b1100..The gate has been locked by processor with master_index = 11.
41589 * 0b1101..The gate has been locked by processor with master_index = 12.
41590 * 0b1110..The gate has been locked by processor with master_index = 13.
41591 * 0b1111..The gate has been locked by processor with master_index = 14.
41592 */
41593#define RDC_SEMAPHORE_GATE35_GTFSM(x) \
41594 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE35_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE35_GTFSM_MASK)
41595#define RDC_SEMAPHORE_GATE35_LDOM_MASK (0x30U)
41596#define RDC_SEMAPHORE_GATE35_LDOM_SHIFT (4U)
41597/*! LDOM
41598 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41599 * 0b01..The gate has been locked by domain 1.
41600 * 0b10..The gate has been locked by domain 2.
41601 * 0b11..The gate has been locked by domain 3.
41602 */
41603#define RDC_SEMAPHORE_GATE35_LDOM(x) \
41604 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE35_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE35_LDOM_MASK)
41605/*! @} */
41606
41607/*! @name GATE36 - Gate Register */
41608/*! @{ */
41609#define RDC_SEMAPHORE_GATE36_GTFSM_MASK (0xFU)
41610#define RDC_SEMAPHORE_GATE36_GTFSM_SHIFT (0U)
41611/*! GTFSM - Gate Finite State Machine.
41612 * 0b0000..The gate is unlocked (free).
41613 * 0b0001..The gate has been locked by processor with master_index = 0.
41614 * 0b0010..The gate has been locked by processor with master_index = 1.
41615 * 0b0011..The gate has been locked by processor with master_index = 2.
41616 * 0b0100..The gate has been locked by processor with master_index = 3.
41617 * 0b0101..The gate has been locked by processor with master_index = 4.
41618 * 0b0110..The gate has been locked by processor with master_index = 5.
41619 * 0b0111..The gate has been locked by processor with master_index = 6.
41620 * 0b1000..The gate has been locked by processor with master_index = 7.
41621 * 0b1001..The gate has been locked by processor with master_index = 8.
41622 * 0b1010..The gate has been locked by processor with master_index = 9.
41623 * 0b1011..The gate has been locked by processor with master_index = 10.
41624 * 0b1100..The gate has been locked by processor with master_index = 11.
41625 * 0b1101..The gate has been locked by processor with master_index = 12.
41626 * 0b1110..The gate has been locked by processor with master_index = 13.
41627 * 0b1111..The gate has been locked by processor with master_index = 14.
41628 */
41629#define RDC_SEMAPHORE_GATE36_GTFSM(x) \
41630 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE36_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE36_GTFSM_MASK)
41631#define RDC_SEMAPHORE_GATE36_LDOM_MASK (0x30U)
41632#define RDC_SEMAPHORE_GATE36_LDOM_SHIFT (4U)
41633/*! LDOM
41634 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41635 * 0b01..The gate has been locked by domain 1.
41636 * 0b10..The gate has been locked by domain 2.
41637 * 0b11..The gate has been locked by domain 3.
41638 */
41639#define RDC_SEMAPHORE_GATE36_LDOM(x) \
41640 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE36_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE36_LDOM_MASK)
41641/*! @} */
41642
41643/*! @name GATE37 - Gate Register */
41644/*! @{ */
41645#define RDC_SEMAPHORE_GATE37_GTFSM_MASK (0xFU)
41646#define RDC_SEMAPHORE_GATE37_GTFSM_SHIFT (0U)
41647/*! GTFSM - Gate Finite State Machine.
41648 * 0b0000..The gate is unlocked (free).
41649 * 0b0001..The gate has been locked by processor with master_index = 0.
41650 * 0b0010..The gate has been locked by processor with master_index = 1.
41651 * 0b0011..The gate has been locked by processor with master_index = 2.
41652 * 0b0100..The gate has been locked by processor with master_index = 3.
41653 * 0b0101..The gate has been locked by processor with master_index = 4.
41654 * 0b0110..The gate has been locked by processor with master_index = 5.
41655 * 0b0111..The gate has been locked by processor with master_index = 6.
41656 * 0b1000..The gate has been locked by processor with master_index = 7.
41657 * 0b1001..The gate has been locked by processor with master_index = 8.
41658 * 0b1010..The gate has been locked by processor with master_index = 9.
41659 * 0b1011..The gate has been locked by processor with master_index = 10.
41660 * 0b1100..The gate has been locked by processor with master_index = 11.
41661 * 0b1101..The gate has been locked by processor with master_index = 12.
41662 * 0b1110..The gate has been locked by processor with master_index = 13.
41663 * 0b1111..The gate has been locked by processor with master_index = 14.
41664 */
41665#define RDC_SEMAPHORE_GATE37_GTFSM(x) \
41666 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE37_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE37_GTFSM_MASK)
41667#define RDC_SEMAPHORE_GATE37_LDOM_MASK (0x30U)
41668#define RDC_SEMAPHORE_GATE37_LDOM_SHIFT (4U)
41669/*! LDOM
41670 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41671 * 0b01..The gate has been locked by domain 1.
41672 * 0b10..The gate has been locked by domain 2.
41673 * 0b11..The gate has been locked by domain 3.
41674 */
41675#define RDC_SEMAPHORE_GATE37_LDOM(x) \
41676 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE37_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE37_LDOM_MASK)
41677/*! @} */
41678
41679/*! @name GATE38 - Gate Register */
41680/*! @{ */
41681#define RDC_SEMAPHORE_GATE38_GTFSM_MASK (0xFU)
41682#define RDC_SEMAPHORE_GATE38_GTFSM_SHIFT (0U)
41683/*! GTFSM - Gate Finite State Machine.
41684 * 0b0000..The gate is unlocked (free).
41685 * 0b0001..The gate has been locked by processor with master_index = 0.
41686 * 0b0010..The gate has been locked by processor with master_index = 1.
41687 * 0b0011..The gate has been locked by processor with master_index = 2.
41688 * 0b0100..The gate has been locked by processor with master_index = 3.
41689 * 0b0101..The gate has been locked by processor with master_index = 4.
41690 * 0b0110..The gate has been locked by processor with master_index = 5.
41691 * 0b0111..The gate has been locked by processor with master_index = 6.
41692 * 0b1000..The gate has been locked by processor with master_index = 7.
41693 * 0b1001..The gate has been locked by processor with master_index = 8.
41694 * 0b1010..The gate has been locked by processor with master_index = 9.
41695 * 0b1011..The gate has been locked by processor with master_index = 10.
41696 * 0b1100..The gate has been locked by processor with master_index = 11.
41697 * 0b1101..The gate has been locked by processor with master_index = 12.
41698 * 0b1110..The gate has been locked by processor with master_index = 13.
41699 * 0b1111..The gate has been locked by processor with master_index = 14.
41700 */
41701#define RDC_SEMAPHORE_GATE38_GTFSM(x) \
41702 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE38_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE38_GTFSM_MASK)
41703#define RDC_SEMAPHORE_GATE38_LDOM_MASK (0x30U)
41704#define RDC_SEMAPHORE_GATE38_LDOM_SHIFT (4U)
41705/*! LDOM
41706 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41707 * 0b01..The gate has been locked by domain 1.
41708 * 0b10..The gate has been locked by domain 2.
41709 * 0b11..The gate has been locked by domain 3.
41710 */
41711#define RDC_SEMAPHORE_GATE38_LDOM(x) \
41712 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE38_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE38_LDOM_MASK)
41713/*! @} */
41714
41715/*! @name GATE39 - Gate Register */
41716/*! @{ */
41717#define RDC_SEMAPHORE_GATE39_GTFSM_MASK (0xFU)
41718#define RDC_SEMAPHORE_GATE39_GTFSM_SHIFT (0U)
41719/*! GTFSM - Gate Finite State Machine.
41720 * 0b0000..The gate is unlocked (free).
41721 * 0b0001..The gate has been locked by processor with master_index = 0.
41722 * 0b0010..The gate has been locked by processor with master_index = 1.
41723 * 0b0011..The gate has been locked by processor with master_index = 2.
41724 * 0b0100..The gate has been locked by processor with master_index = 3.
41725 * 0b0101..The gate has been locked by processor with master_index = 4.
41726 * 0b0110..The gate has been locked by processor with master_index = 5.
41727 * 0b0111..The gate has been locked by processor with master_index = 6.
41728 * 0b1000..The gate has been locked by processor with master_index = 7.
41729 * 0b1001..The gate has been locked by processor with master_index = 8.
41730 * 0b1010..The gate has been locked by processor with master_index = 9.
41731 * 0b1011..The gate has been locked by processor with master_index = 10.
41732 * 0b1100..The gate has been locked by processor with master_index = 11.
41733 * 0b1101..The gate has been locked by processor with master_index = 12.
41734 * 0b1110..The gate has been locked by processor with master_index = 13.
41735 * 0b1111..The gate has been locked by processor with master_index = 14.
41736 */
41737#define RDC_SEMAPHORE_GATE39_GTFSM(x) \
41738 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE39_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE39_GTFSM_MASK)
41739#define RDC_SEMAPHORE_GATE39_LDOM_MASK (0x30U)
41740#define RDC_SEMAPHORE_GATE39_LDOM_SHIFT (4U)
41741/*! LDOM
41742 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41743 * 0b01..The gate has been locked by domain 1.
41744 * 0b10..The gate has been locked by domain 2.
41745 * 0b11..The gate has been locked by domain 3.
41746 */
41747#define RDC_SEMAPHORE_GATE39_LDOM(x) \
41748 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE39_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE39_LDOM_MASK)
41749/*! @} */
41750
41751/*! @name GATE40 - Gate Register */
41752/*! @{ */
41753#define RDC_SEMAPHORE_GATE40_GTFSM_MASK (0xFU)
41754#define RDC_SEMAPHORE_GATE40_GTFSM_SHIFT (0U)
41755/*! GTFSM - Gate Finite State Machine.
41756 * 0b0000..The gate is unlocked (free).
41757 * 0b0001..The gate has been locked by processor with master_index = 0.
41758 * 0b0010..The gate has been locked by processor with master_index = 1.
41759 * 0b0011..The gate has been locked by processor with master_index = 2.
41760 * 0b0100..The gate has been locked by processor with master_index = 3.
41761 * 0b0101..The gate has been locked by processor with master_index = 4.
41762 * 0b0110..The gate has been locked by processor with master_index = 5.
41763 * 0b0111..The gate has been locked by processor with master_index = 6.
41764 * 0b1000..The gate has been locked by processor with master_index = 7.
41765 * 0b1001..The gate has been locked by processor with master_index = 8.
41766 * 0b1010..The gate has been locked by processor with master_index = 9.
41767 * 0b1011..The gate has been locked by processor with master_index = 10.
41768 * 0b1100..The gate has been locked by processor with master_index = 11.
41769 * 0b1101..The gate has been locked by processor with master_index = 12.
41770 * 0b1110..The gate has been locked by processor with master_index = 13.
41771 * 0b1111..The gate has been locked by processor with master_index = 14.
41772 */
41773#define RDC_SEMAPHORE_GATE40_GTFSM(x) \
41774 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE40_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE40_GTFSM_MASK)
41775#define RDC_SEMAPHORE_GATE40_LDOM_MASK (0x30U)
41776#define RDC_SEMAPHORE_GATE40_LDOM_SHIFT (4U)
41777/*! LDOM
41778 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41779 * 0b01..The gate has been locked by domain 1.
41780 * 0b10..The gate has been locked by domain 2.
41781 * 0b11..The gate has been locked by domain 3.
41782 */
41783#define RDC_SEMAPHORE_GATE40_LDOM(x) \
41784 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE40_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE40_LDOM_MASK)
41785/*! @} */
41786
41787/*! @name GATE41 - Gate Register */
41788/*! @{ */
41789#define RDC_SEMAPHORE_GATE41_GTFSM_MASK (0xFU)
41790#define RDC_SEMAPHORE_GATE41_GTFSM_SHIFT (0U)
41791/*! GTFSM - Gate Finite State Machine.
41792 * 0b0000..The gate is unlocked (free).
41793 * 0b0001..The gate has been locked by processor with master_index = 0.
41794 * 0b0010..The gate has been locked by processor with master_index = 1.
41795 * 0b0011..The gate has been locked by processor with master_index = 2.
41796 * 0b0100..The gate has been locked by processor with master_index = 3.
41797 * 0b0101..The gate has been locked by processor with master_index = 4.
41798 * 0b0110..The gate has been locked by processor with master_index = 5.
41799 * 0b0111..The gate has been locked by processor with master_index = 6.
41800 * 0b1000..The gate has been locked by processor with master_index = 7.
41801 * 0b1001..The gate has been locked by processor with master_index = 8.
41802 * 0b1010..The gate has been locked by processor with master_index = 9.
41803 * 0b1011..The gate has been locked by processor with master_index = 10.
41804 * 0b1100..The gate has been locked by processor with master_index = 11.
41805 * 0b1101..The gate has been locked by processor with master_index = 12.
41806 * 0b1110..The gate has been locked by processor with master_index = 13.
41807 * 0b1111..The gate has been locked by processor with master_index = 14.
41808 */
41809#define RDC_SEMAPHORE_GATE41_GTFSM(x) \
41810 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE41_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE41_GTFSM_MASK)
41811#define RDC_SEMAPHORE_GATE41_LDOM_MASK (0x30U)
41812#define RDC_SEMAPHORE_GATE41_LDOM_SHIFT (4U)
41813/*! LDOM
41814 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41815 * 0b01..The gate has been locked by domain 1.
41816 * 0b10..The gate has been locked by domain 2.
41817 * 0b11..The gate has been locked by domain 3.
41818 */
41819#define RDC_SEMAPHORE_GATE41_LDOM(x) \
41820 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE41_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE41_LDOM_MASK)
41821/*! @} */
41822
41823/*! @name GATE42 - Gate Register */
41824/*! @{ */
41825#define RDC_SEMAPHORE_GATE42_GTFSM_MASK (0xFU)
41826#define RDC_SEMAPHORE_GATE42_GTFSM_SHIFT (0U)
41827/*! GTFSM - Gate Finite State Machine.
41828 * 0b0000..The gate is unlocked (free).
41829 * 0b0001..The gate has been locked by processor with master_index = 0.
41830 * 0b0010..The gate has been locked by processor with master_index = 1.
41831 * 0b0011..The gate has been locked by processor with master_index = 2.
41832 * 0b0100..The gate has been locked by processor with master_index = 3.
41833 * 0b0101..The gate has been locked by processor with master_index = 4.
41834 * 0b0110..The gate has been locked by processor with master_index = 5.
41835 * 0b0111..The gate has been locked by processor with master_index = 6.
41836 * 0b1000..The gate has been locked by processor with master_index = 7.
41837 * 0b1001..The gate has been locked by processor with master_index = 8.
41838 * 0b1010..The gate has been locked by processor with master_index = 9.
41839 * 0b1011..The gate has been locked by processor with master_index = 10.
41840 * 0b1100..The gate has been locked by processor with master_index = 11.
41841 * 0b1101..The gate has been locked by processor with master_index = 12.
41842 * 0b1110..The gate has been locked by processor with master_index = 13.
41843 * 0b1111..The gate has been locked by processor with master_index = 14.
41844 */
41845#define RDC_SEMAPHORE_GATE42_GTFSM(x) \
41846 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE42_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE42_GTFSM_MASK)
41847#define RDC_SEMAPHORE_GATE42_LDOM_MASK (0x30U)
41848#define RDC_SEMAPHORE_GATE42_LDOM_SHIFT (4U)
41849/*! LDOM
41850 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41851 * 0b01..The gate has been locked by domain 1.
41852 * 0b10..The gate has been locked by domain 2.
41853 * 0b11..The gate has been locked by domain 3.
41854 */
41855#define RDC_SEMAPHORE_GATE42_LDOM(x) \
41856 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE42_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE42_LDOM_MASK)
41857/*! @} */
41858
41859/*! @name GATE43 - Gate Register */
41860/*! @{ */
41861#define RDC_SEMAPHORE_GATE43_GTFSM_MASK (0xFU)
41862#define RDC_SEMAPHORE_GATE43_GTFSM_SHIFT (0U)
41863/*! GTFSM - Gate Finite State Machine.
41864 * 0b0000..The gate is unlocked (free).
41865 * 0b0001..The gate has been locked by processor with master_index = 0.
41866 * 0b0010..The gate has been locked by processor with master_index = 1.
41867 * 0b0011..The gate has been locked by processor with master_index = 2.
41868 * 0b0100..The gate has been locked by processor with master_index = 3.
41869 * 0b0101..The gate has been locked by processor with master_index = 4.
41870 * 0b0110..The gate has been locked by processor with master_index = 5.
41871 * 0b0111..The gate has been locked by processor with master_index = 6.
41872 * 0b1000..The gate has been locked by processor with master_index = 7.
41873 * 0b1001..The gate has been locked by processor with master_index = 8.
41874 * 0b1010..The gate has been locked by processor with master_index = 9.
41875 * 0b1011..The gate has been locked by processor with master_index = 10.
41876 * 0b1100..The gate has been locked by processor with master_index = 11.
41877 * 0b1101..The gate has been locked by processor with master_index = 12.
41878 * 0b1110..The gate has been locked by processor with master_index = 13.
41879 * 0b1111..The gate has been locked by processor with master_index = 14.
41880 */
41881#define RDC_SEMAPHORE_GATE43_GTFSM(x) \
41882 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE43_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE43_GTFSM_MASK)
41883#define RDC_SEMAPHORE_GATE43_LDOM_MASK (0x30U)
41884#define RDC_SEMAPHORE_GATE43_LDOM_SHIFT (4U)
41885/*! LDOM
41886 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41887 * 0b01..The gate has been locked by domain 1.
41888 * 0b10..The gate has been locked by domain 2.
41889 * 0b11..The gate has been locked by domain 3.
41890 */
41891#define RDC_SEMAPHORE_GATE43_LDOM(x) \
41892 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE43_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE43_LDOM_MASK)
41893/*! @} */
41894
41895/*! @name GATE44 - Gate Register */
41896/*! @{ */
41897#define RDC_SEMAPHORE_GATE44_GTFSM_MASK (0xFU)
41898#define RDC_SEMAPHORE_GATE44_GTFSM_SHIFT (0U)
41899/*! GTFSM - Gate Finite State Machine.
41900 * 0b0000..The gate is unlocked (free).
41901 * 0b0001..The gate has been locked by processor with master_index = 0.
41902 * 0b0010..The gate has been locked by processor with master_index = 1.
41903 * 0b0011..The gate has been locked by processor with master_index = 2.
41904 * 0b0100..The gate has been locked by processor with master_index = 3.
41905 * 0b0101..The gate has been locked by processor with master_index = 4.
41906 * 0b0110..The gate has been locked by processor with master_index = 5.
41907 * 0b0111..The gate has been locked by processor with master_index = 6.
41908 * 0b1000..The gate has been locked by processor with master_index = 7.
41909 * 0b1001..The gate has been locked by processor with master_index = 8.
41910 * 0b1010..The gate has been locked by processor with master_index = 9.
41911 * 0b1011..The gate has been locked by processor with master_index = 10.
41912 * 0b1100..The gate has been locked by processor with master_index = 11.
41913 * 0b1101..The gate has been locked by processor with master_index = 12.
41914 * 0b1110..The gate has been locked by processor with master_index = 13.
41915 * 0b1111..The gate has been locked by processor with master_index = 14.
41916 */
41917#define RDC_SEMAPHORE_GATE44_GTFSM(x) \
41918 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE44_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE44_GTFSM_MASK)
41919#define RDC_SEMAPHORE_GATE44_LDOM_MASK (0x30U)
41920#define RDC_SEMAPHORE_GATE44_LDOM_SHIFT (4U)
41921/*! LDOM
41922 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41923 * 0b01..The gate has been locked by domain 1.
41924 * 0b10..The gate has been locked by domain 2.
41925 * 0b11..The gate has been locked by domain 3.
41926 */
41927#define RDC_SEMAPHORE_GATE44_LDOM(x) \
41928 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE44_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE44_LDOM_MASK)
41929/*! @} */
41930
41931/*! @name GATE45 - Gate Register */
41932/*! @{ */
41933#define RDC_SEMAPHORE_GATE45_GTFSM_MASK (0xFU)
41934#define RDC_SEMAPHORE_GATE45_GTFSM_SHIFT (0U)
41935/*! GTFSM - Gate Finite State Machine.
41936 * 0b0000..The gate is unlocked (free).
41937 * 0b0001..The gate has been locked by processor with master_index = 0.
41938 * 0b0010..The gate has been locked by processor with master_index = 1.
41939 * 0b0011..The gate has been locked by processor with master_index = 2.
41940 * 0b0100..The gate has been locked by processor with master_index = 3.
41941 * 0b0101..The gate has been locked by processor with master_index = 4.
41942 * 0b0110..The gate has been locked by processor with master_index = 5.
41943 * 0b0111..The gate has been locked by processor with master_index = 6.
41944 * 0b1000..The gate has been locked by processor with master_index = 7.
41945 * 0b1001..The gate has been locked by processor with master_index = 8.
41946 * 0b1010..The gate has been locked by processor with master_index = 9.
41947 * 0b1011..The gate has been locked by processor with master_index = 10.
41948 * 0b1100..The gate has been locked by processor with master_index = 11.
41949 * 0b1101..The gate has been locked by processor with master_index = 12.
41950 * 0b1110..The gate has been locked by processor with master_index = 13.
41951 * 0b1111..The gate has been locked by processor with master_index = 14.
41952 */
41953#define RDC_SEMAPHORE_GATE45_GTFSM(x) \
41954 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE45_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE45_GTFSM_MASK)
41955#define RDC_SEMAPHORE_GATE45_LDOM_MASK (0x30U)
41956#define RDC_SEMAPHORE_GATE45_LDOM_SHIFT (4U)
41957/*! LDOM
41958 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41959 * 0b01..The gate has been locked by domain 1.
41960 * 0b10..The gate has been locked by domain 2.
41961 * 0b11..The gate has been locked by domain 3.
41962 */
41963#define RDC_SEMAPHORE_GATE45_LDOM(x) \
41964 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE45_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE45_LDOM_MASK)
41965/*! @} */
41966
41967/*! @name GATE46 - Gate Register */
41968/*! @{ */
41969#define RDC_SEMAPHORE_GATE46_GTFSM_MASK (0xFU)
41970#define RDC_SEMAPHORE_GATE46_GTFSM_SHIFT (0U)
41971/*! GTFSM - Gate Finite State Machine.
41972 * 0b0000..The gate is unlocked (free).
41973 * 0b0001..The gate has been locked by processor with master_index = 0.
41974 * 0b0010..The gate has been locked by processor with master_index = 1.
41975 * 0b0011..The gate has been locked by processor with master_index = 2.
41976 * 0b0100..The gate has been locked by processor with master_index = 3.
41977 * 0b0101..The gate has been locked by processor with master_index = 4.
41978 * 0b0110..The gate has been locked by processor with master_index = 5.
41979 * 0b0111..The gate has been locked by processor with master_index = 6.
41980 * 0b1000..The gate has been locked by processor with master_index = 7.
41981 * 0b1001..The gate has been locked by processor with master_index = 8.
41982 * 0b1010..The gate has been locked by processor with master_index = 9.
41983 * 0b1011..The gate has been locked by processor with master_index = 10.
41984 * 0b1100..The gate has been locked by processor with master_index = 11.
41985 * 0b1101..The gate has been locked by processor with master_index = 12.
41986 * 0b1110..The gate has been locked by processor with master_index = 13.
41987 * 0b1111..The gate has been locked by processor with master_index = 14.
41988 */
41989#define RDC_SEMAPHORE_GATE46_GTFSM(x) \
41990 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE46_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE46_GTFSM_MASK)
41991#define RDC_SEMAPHORE_GATE46_LDOM_MASK (0x30U)
41992#define RDC_SEMAPHORE_GATE46_LDOM_SHIFT (4U)
41993/*! LDOM
41994 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
41995 * 0b01..The gate has been locked by domain 1.
41996 * 0b10..The gate has been locked by domain 2.
41997 * 0b11..The gate has been locked by domain 3.
41998 */
41999#define RDC_SEMAPHORE_GATE46_LDOM(x) \
42000 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE46_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE46_LDOM_MASK)
42001/*! @} */
42002
42003/*! @name GATE47 - Gate Register */
42004/*! @{ */
42005#define RDC_SEMAPHORE_GATE47_GTFSM_MASK (0xFU)
42006#define RDC_SEMAPHORE_GATE47_GTFSM_SHIFT (0U)
42007/*! GTFSM - Gate Finite State Machine.
42008 * 0b0000..The gate is unlocked (free).
42009 * 0b0001..The gate has been locked by processor with master_index = 0.
42010 * 0b0010..The gate has been locked by processor with master_index = 1.
42011 * 0b0011..The gate has been locked by processor with master_index = 2.
42012 * 0b0100..The gate has been locked by processor with master_index = 3.
42013 * 0b0101..The gate has been locked by processor with master_index = 4.
42014 * 0b0110..The gate has been locked by processor with master_index = 5.
42015 * 0b0111..The gate has been locked by processor with master_index = 6.
42016 * 0b1000..The gate has been locked by processor with master_index = 7.
42017 * 0b1001..The gate has been locked by processor with master_index = 8.
42018 * 0b1010..The gate has been locked by processor with master_index = 9.
42019 * 0b1011..The gate has been locked by processor with master_index = 10.
42020 * 0b1100..The gate has been locked by processor with master_index = 11.
42021 * 0b1101..The gate has been locked by processor with master_index = 12.
42022 * 0b1110..The gate has been locked by processor with master_index = 13.
42023 * 0b1111..The gate has been locked by processor with master_index = 14.
42024 */
42025#define RDC_SEMAPHORE_GATE47_GTFSM(x) \
42026 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE47_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE47_GTFSM_MASK)
42027#define RDC_SEMAPHORE_GATE47_LDOM_MASK (0x30U)
42028#define RDC_SEMAPHORE_GATE47_LDOM_SHIFT (4U)
42029/*! LDOM
42030 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
42031 * 0b01..The gate has been locked by domain 1.
42032 * 0b10..The gate has been locked by domain 2.
42033 * 0b11..The gate has been locked by domain 3.
42034 */
42035#define RDC_SEMAPHORE_GATE47_LDOM(x) \
42036 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE47_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE47_LDOM_MASK)
42037/*! @} */
42038
42039/*! @name GATE48 - Gate Register */
42040/*! @{ */
42041#define RDC_SEMAPHORE_GATE48_GTFSM_MASK (0xFU)
42042#define RDC_SEMAPHORE_GATE48_GTFSM_SHIFT (0U)
42043/*! GTFSM - Gate Finite State Machine.
42044 * 0b0000..The gate is unlocked (free).
42045 * 0b0001..The gate has been locked by processor with master_index = 0.
42046 * 0b0010..The gate has been locked by processor with master_index = 1.
42047 * 0b0011..The gate has been locked by processor with master_index = 2.
42048 * 0b0100..The gate has been locked by processor with master_index = 3.
42049 * 0b0101..The gate has been locked by processor with master_index = 4.
42050 * 0b0110..The gate has been locked by processor with master_index = 5.
42051 * 0b0111..The gate has been locked by processor with master_index = 6.
42052 * 0b1000..The gate has been locked by processor with master_index = 7.
42053 * 0b1001..The gate has been locked by processor with master_index = 8.
42054 * 0b1010..The gate has been locked by processor with master_index = 9.
42055 * 0b1011..The gate has been locked by processor with master_index = 10.
42056 * 0b1100..The gate has been locked by processor with master_index = 11.
42057 * 0b1101..The gate has been locked by processor with master_index = 12.
42058 * 0b1110..The gate has been locked by processor with master_index = 13.
42059 * 0b1111..The gate has been locked by processor with master_index = 14.
42060 */
42061#define RDC_SEMAPHORE_GATE48_GTFSM(x) \
42062 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE48_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE48_GTFSM_MASK)
42063#define RDC_SEMAPHORE_GATE48_LDOM_MASK (0x30U)
42064#define RDC_SEMAPHORE_GATE48_LDOM_SHIFT (4U)
42065/*! LDOM
42066 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
42067 * 0b01..The gate has been locked by domain 1.
42068 * 0b10..The gate has been locked by domain 2.
42069 * 0b11..The gate has been locked by domain 3.
42070 */
42071#define RDC_SEMAPHORE_GATE48_LDOM(x) \
42072 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE48_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE48_LDOM_MASK)
42073/*! @} */
42074
42075/*! @name GATE49 - Gate Register */
42076/*! @{ */
42077#define RDC_SEMAPHORE_GATE49_GTFSM_MASK (0xFU)
42078#define RDC_SEMAPHORE_GATE49_GTFSM_SHIFT (0U)
42079/*! GTFSM - Gate Finite State Machine.
42080 * 0b0000..The gate is unlocked (free).
42081 * 0b0001..The gate has been locked by processor with master_index = 0.
42082 * 0b0010..The gate has been locked by processor with master_index = 1.
42083 * 0b0011..The gate has been locked by processor with master_index = 2.
42084 * 0b0100..The gate has been locked by processor with master_index = 3.
42085 * 0b0101..The gate has been locked by processor with master_index = 4.
42086 * 0b0110..The gate has been locked by processor with master_index = 5.
42087 * 0b0111..The gate has been locked by processor with master_index = 6.
42088 * 0b1000..The gate has been locked by processor with master_index = 7.
42089 * 0b1001..The gate has been locked by processor with master_index = 8.
42090 * 0b1010..The gate has been locked by processor with master_index = 9.
42091 * 0b1011..The gate has been locked by processor with master_index = 10.
42092 * 0b1100..The gate has been locked by processor with master_index = 11.
42093 * 0b1101..The gate has been locked by processor with master_index = 12.
42094 * 0b1110..The gate has been locked by processor with master_index = 13.
42095 * 0b1111..The gate has been locked by processor with master_index = 14.
42096 */
42097#define RDC_SEMAPHORE_GATE49_GTFSM(x) \
42098 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE49_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE49_GTFSM_MASK)
42099#define RDC_SEMAPHORE_GATE49_LDOM_MASK (0x30U)
42100#define RDC_SEMAPHORE_GATE49_LDOM_SHIFT (4U)
42101/*! LDOM
42102 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
42103 * 0b01..The gate has been locked by domain 1.
42104 * 0b10..The gate has been locked by domain 2.
42105 * 0b11..The gate has been locked by domain 3.
42106 */
42107#define RDC_SEMAPHORE_GATE49_LDOM(x) \
42108 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE49_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE49_LDOM_MASK)
42109/*! @} */
42110
42111/*! @name GATE50 - Gate Register */
42112/*! @{ */
42113#define RDC_SEMAPHORE_GATE50_GTFSM_MASK (0xFU)
42114#define RDC_SEMAPHORE_GATE50_GTFSM_SHIFT (0U)
42115/*! GTFSM - Gate Finite State Machine.
42116 * 0b0000..The gate is unlocked (free).
42117 * 0b0001..The gate has been locked by processor with master_index = 0.
42118 * 0b0010..The gate has been locked by processor with master_index = 1.
42119 * 0b0011..The gate has been locked by processor with master_index = 2.
42120 * 0b0100..The gate has been locked by processor with master_index = 3.
42121 * 0b0101..The gate has been locked by processor with master_index = 4.
42122 * 0b0110..The gate has been locked by processor with master_index = 5.
42123 * 0b0111..The gate has been locked by processor with master_index = 6.
42124 * 0b1000..The gate has been locked by processor with master_index = 7.
42125 * 0b1001..The gate has been locked by processor with master_index = 8.
42126 * 0b1010..The gate has been locked by processor with master_index = 9.
42127 * 0b1011..The gate has been locked by processor with master_index = 10.
42128 * 0b1100..The gate has been locked by processor with master_index = 11.
42129 * 0b1101..The gate has been locked by processor with master_index = 12.
42130 * 0b1110..The gate has been locked by processor with master_index = 13.
42131 * 0b1111..The gate has been locked by processor with master_index = 14.
42132 */
42133#define RDC_SEMAPHORE_GATE50_GTFSM(x) \
42134 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE50_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE50_GTFSM_MASK)
42135#define RDC_SEMAPHORE_GATE50_LDOM_MASK (0x30U)
42136#define RDC_SEMAPHORE_GATE50_LDOM_SHIFT (4U)
42137/*! LDOM
42138 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
42139 * 0b01..The gate has been locked by domain 1.
42140 * 0b10..The gate has been locked by domain 2.
42141 * 0b11..The gate has been locked by domain 3.
42142 */
42143#define RDC_SEMAPHORE_GATE50_LDOM(x) \
42144 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE50_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE50_LDOM_MASK)
42145/*! @} */
42146
42147/*! @name GATE51 - Gate Register */
42148/*! @{ */
42149#define RDC_SEMAPHORE_GATE51_GTFSM_MASK (0xFU)
42150#define RDC_SEMAPHORE_GATE51_GTFSM_SHIFT (0U)
42151/*! GTFSM - Gate Finite State Machine.
42152 * 0b0000..The gate is unlocked (free).
42153 * 0b0001..The gate has been locked by processor with master_index = 0.
42154 * 0b0010..The gate has been locked by processor with master_index = 1.
42155 * 0b0011..The gate has been locked by processor with master_index = 2.
42156 * 0b0100..The gate has been locked by processor with master_index = 3.
42157 * 0b0101..The gate has been locked by processor with master_index = 4.
42158 * 0b0110..The gate has been locked by processor with master_index = 5.
42159 * 0b0111..The gate has been locked by processor with master_index = 6.
42160 * 0b1000..The gate has been locked by processor with master_index = 7.
42161 * 0b1001..The gate has been locked by processor with master_index = 8.
42162 * 0b1010..The gate has been locked by processor with master_index = 9.
42163 * 0b1011..The gate has been locked by processor with master_index = 10.
42164 * 0b1100..The gate has been locked by processor with master_index = 11.
42165 * 0b1101..The gate has been locked by processor with master_index = 12.
42166 * 0b1110..The gate has been locked by processor with master_index = 13.
42167 * 0b1111..The gate has been locked by processor with master_index = 14.
42168 */
42169#define RDC_SEMAPHORE_GATE51_GTFSM(x) \
42170 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE51_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE51_GTFSM_MASK)
42171#define RDC_SEMAPHORE_GATE51_LDOM_MASK (0x30U)
42172#define RDC_SEMAPHORE_GATE51_LDOM_SHIFT (4U)
42173/*! LDOM
42174 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
42175 * 0b01..The gate has been locked by domain 1.
42176 * 0b10..The gate has been locked by domain 2.
42177 * 0b11..The gate has been locked by domain 3.
42178 */
42179#define RDC_SEMAPHORE_GATE51_LDOM(x) \
42180 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE51_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE51_LDOM_MASK)
42181/*! @} */
42182
42183/*! @name GATE52 - Gate Register */
42184/*! @{ */
42185#define RDC_SEMAPHORE_GATE52_GTFSM_MASK (0xFU)
42186#define RDC_SEMAPHORE_GATE52_GTFSM_SHIFT (0U)
42187/*! GTFSM - Gate Finite State Machine.
42188 * 0b0000..The gate is unlocked (free).
42189 * 0b0001..The gate has been locked by processor with master_index = 0.
42190 * 0b0010..The gate has been locked by processor with master_index = 1.
42191 * 0b0011..The gate has been locked by processor with master_index = 2.
42192 * 0b0100..The gate has been locked by processor with master_index = 3.
42193 * 0b0101..The gate has been locked by processor with master_index = 4.
42194 * 0b0110..The gate has been locked by processor with master_index = 5.
42195 * 0b0111..The gate has been locked by processor with master_index = 6.
42196 * 0b1000..The gate has been locked by processor with master_index = 7.
42197 * 0b1001..The gate has been locked by processor with master_index = 8.
42198 * 0b1010..The gate has been locked by processor with master_index = 9.
42199 * 0b1011..The gate has been locked by processor with master_index = 10.
42200 * 0b1100..The gate has been locked by processor with master_index = 11.
42201 * 0b1101..The gate has been locked by processor with master_index = 12.
42202 * 0b1110..The gate has been locked by processor with master_index = 13.
42203 * 0b1111..The gate has been locked by processor with master_index = 14.
42204 */
42205#define RDC_SEMAPHORE_GATE52_GTFSM(x) \
42206 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE52_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE52_GTFSM_MASK)
42207#define RDC_SEMAPHORE_GATE52_LDOM_MASK (0x30U)
42208#define RDC_SEMAPHORE_GATE52_LDOM_SHIFT (4U)
42209/*! LDOM
42210 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
42211 * 0b01..The gate has been locked by domain 1.
42212 * 0b10..The gate has been locked by domain 2.
42213 * 0b11..The gate has been locked by domain 3.
42214 */
42215#define RDC_SEMAPHORE_GATE52_LDOM(x) \
42216 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE52_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE52_LDOM_MASK)
42217/*! @} */
42218
42219/*! @name GATE53 - Gate Register */
42220/*! @{ */
42221#define RDC_SEMAPHORE_GATE53_GTFSM_MASK (0xFU)
42222#define RDC_SEMAPHORE_GATE53_GTFSM_SHIFT (0U)
42223/*! GTFSM - Gate Finite State Machine.
42224 * 0b0000..The gate is unlocked (free).
42225 * 0b0001..The gate has been locked by processor with master_index = 0.
42226 * 0b0010..The gate has been locked by processor with master_index = 1.
42227 * 0b0011..The gate has been locked by processor with master_index = 2.
42228 * 0b0100..The gate has been locked by processor with master_index = 3.
42229 * 0b0101..The gate has been locked by processor with master_index = 4.
42230 * 0b0110..The gate has been locked by processor with master_index = 5.
42231 * 0b0111..The gate has been locked by processor with master_index = 6.
42232 * 0b1000..The gate has been locked by processor with master_index = 7.
42233 * 0b1001..The gate has been locked by processor with master_index = 8.
42234 * 0b1010..The gate has been locked by processor with master_index = 9.
42235 * 0b1011..The gate has been locked by processor with master_index = 10.
42236 * 0b1100..The gate has been locked by processor with master_index = 11.
42237 * 0b1101..The gate has been locked by processor with master_index = 12.
42238 * 0b1110..The gate has been locked by processor with master_index = 13.
42239 * 0b1111..The gate has been locked by processor with master_index = 14.
42240 */
42241#define RDC_SEMAPHORE_GATE53_GTFSM(x) \
42242 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE53_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE53_GTFSM_MASK)
42243#define RDC_SEMAPHORE_GATE53_LDOM_MASK (0x30U)
42244#define RDC_SEMAPHORE_GATE53_LDOM_SHIFT (4U)
42245/*! LDOM
42246 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
42247 * 0b01..The gate has been locked by domain 1.
42248 * 0b10..The gate has been locked by domain 2.
42249 * 0b11..The gate has been locked by domain 3.
42250 */
42251#define RDC_SEMAPHORE_GATE53_LDOM(x) \
42252 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE53_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE53_LDOM_MASK)
42253/*! @} */
42254
42255/*! @name GATE54 - Gate Register */
42256/*! @{ */
42257#define RDC_SEMAPHORE_GATE54_GTFSM_MASK (0xFU)
42258#define RDC_SEMAPHORE_GATE54_GTFSM_SHIFT (0U)
42259/*! GTFSM - Gate Finite State Machine.
42260 * 0b0000..The gate is unlocked (free).
42261 * 0b0001..The gate has been locked by processor with master_index = 0.
42262 * 0b0010..The gate has been locked by processor with master_index = 1.
42263 * 0b0011..The gate has been locked by processor with master_index = 2.
42264 * 0b0100..The gate has been locked by processor with master_index = 3.
42265 * 0b0101..The gate has been locked by processor with master_index = 4.
42266 * 0b0110..The gate has been locked by processor with master_index = 5.
42267 * 0b0111..The gate has been locked by processor with master_index = 6.
42268 * 0b1000..The gate has been locked by processor with master_index = 7.
42269 * 0b1001..The gate has been locked by processor with master_index = 8.
42270 * 0b1010..The gate has been locked by processor with master_index = 9.
42271 * 0b1011..The gate has been locked by processor with master_index = 10.
42272 * 0b1100..The gate has been locked by processor with master_index = 11.
42273 * 0b1101..The gate has been locked by processor with master_index = 12.
42274 * 0b1110..The gate has been locked by processor with master_index = 13.
42275 * 0b1111..The gate has been locked by processor with master_index = 14.
42276 */
42277#define RDC_SEMAPHORE_GATE54_GTFSM(x) \
42278 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE54_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE54_GTFSM_MASK)
42279#define RDC_SEMAPHORE_GATE54_LDOM_MASK (0x30U)
42280#define RDC_SEMAPHORE_GATE54_LDOM_SHIFT (4U)
42281/*! LDOM
42282 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
42283 * 0b01..The gate has been locked by domain 1.
42284 * 0b10..The gate has been locked by domain 2.
42285 * 0b11..The gate has been locked by domain 3.
42286 */
42287#define RDC_SEMAPHORE_GATE54_LDOM(x) \
42288 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE54_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE54_LDOM_MASK)
42289/*! @} */
42290
42291/*! @name GATE55 - Gate Register */
42292/*! @{ */
42293#define RDC_SEMAPHORE_GATE55_GTFSM_MASK (0xFU)
42294#define RDC_SEMAPHORE_GATE55_GTFSM_SHIFT (0U)
42295/*! GTFSM - Gate Finite State Machine.
42296 * 0b0000..The gate is unlocked (free).
42297 * 0b0001..The gate has been locked by processor with master_index = 0.
42298 * 0b0010..The gate has been locked by processor with master_index = 1.
42299 * 0b0011..The gate has been locked by processor with master_index = 2.
42300 * 0b0100..The gate has been locked by processor with master_index = 3.
42301 * 0b0101..The gate has been locked by processor with master_index = 4.
42302 * 0b0110..The gate has been locked by processor with master_index = 5.
42303 * 0b0111..The gate has been locked by processor with master_index = 6.
42304 * 0b1000..The gate has been locked by processor with master_index = 7.
42305 * 0b1001..The gate has been locked by processor with master_index = 8.
42306 * 0b1010..The gate has been locked by processor with master_index = 9.
42307 * 0b1011..The gate has been locked by processor with master_index = 10.
42308 * 0b1100..The gate has been locked by processor with master_index = 11.
42309 * 0b1101..The gate has been locked by processor with master_index = 12.
42310 * 0b1110..The gate has been locked by processor with master_index = 13.
42311 * 0b1111..The gate has been locked by processor with master_index = 14.
42312 */
42313#define RDC_SEMAPHORE_GATE55_GTFSM(x) \
42314 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE55_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE55_GTFSM_MASK)
42315#define RDC_SEMAPHORE_GATE55_LDOM_MASK (0x30U)
42316#define RDC_SEMAPHORE_GATE55_LDOM_SHIFT (4U)
42317/*! LDOM
42318 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
42319 * 0b01..The gate has been locked by domain 1.
42320 * 0b10..The gate has been locked by domain 2.
42321 * 0b11..The gate has been locked by domain 3.
42322 */
42323#define RDC_SEMAPHORE_GATE55_LDOM(x) \
42324 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE55_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE55_LDOM_MASK)
42325/*! @} */
42326
42327/*! @name GATE56 - Gate Register */
42328/*! @{ */
42329#define RDC_SEMAPHORE_GATE56_GTFSM_MASK (0xFU)
42330#define RDC_SEMAPHORE_GATE56_GTFSM_SHIFT (0U)
42331/*! GTFSM - Gate Finite State Machine.
42332 * 0b0000..The gate is unlocked (free).
42333 * 0b0001..The gate has been locked by processor with master_index = 0.
42334 * 0b0010..The gate has been locked by processor with master_index = 1.
42335 * 0b0011..The gate has been locked by processor with master_index = 2.
42336 * 0b0100..The gate has been locked by processor with master_index = 3.
42337 * 0b0101..The gate has been locked by processor with master_index = 4.
42338 * 0b0110..The gate has been locked by processor with master_index = 5.
42339 * 0b0111..The gate has been locked by processor with master_index = 6.
42340 * 0b1000..The gate has been locked by processor with master_index = 7.
42341 * 0b1001..The gate has been locked by processor with master_index = 8.
42342 * 0b1010..The gate has been locked by processor with master_index = 9.
42343 * 0b1011..The gate has been locked by processor with master_index = 10.
42344 * 0b1100..The gate has been locked by processor with master_index = 11.
42345 * 0b1101..The gate has been locked by processor with master_index = 12.
42346 * 0b1110..The gate has been locked by processor with master_index = 13.
42347 * 0b1111..The gate has been locked by processor with master_index = 14.
42348 */
42349#define RDC_SEMAPHORE_GATE56_GTFSM(x) \
42350 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE56_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE56_GTFSM_MASK)
42351#define RDC_SEMAPHORE_GATE56_LDOM_MASK (0x30U)
42352#define RDC_SEMAPHORE_GATE56_LDOM_SHIFT (4U)
42353/*! LDOM
42354 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
42355 * 0b01..The gate has been locked by domain 1.
42356 * 0b10..The gate has been locked by domain 2.
42357 * 0b11..The gate has been locked by domain 3.
42358 */
42359#define RDC_SEMAPHORE_GATE56_LDOM(x) \
42360 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE56_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE56_LDOM_MASK)
42361/*! @} */
42362
42363/*! @name GATE57 - Gate Register */
42364/*! @{ */
42365#define RDC_SEMAPHORE_GATE57_GTFSM_MASK (0xFU)
42366#define RDC_SEMAPHORE_GATE57_GTFSM_SHIFT (0U)
42367/*! GTFSM - Gate Finite State Machine.
42368 * 0b0000..The gate is unlocked (free).
42369 * 0b0001..The gate has been locked by processor with master_index = 0.
42370 * 0b0010..The gate has been locked by processor with master_index = 1.
42371 * 0b0011..The gate has been locked by processor with master_index = 2.
42372 * 0b0100..The gate has been locked by processor with master_index = 3.
42373 * 0b0101..The gate has been locked by processor with master_index = 4.
42374 * 0b0110..The gate has been locked by processor with master_index = 5.
42375 * 0b0111..The gate has been locked by processor with master_index = 6.
42376 * 0b1000..The gate has been locked by processor with master_index = 7.
42377 * 0b1001..The gate has been locked by processor with master_index = 8.
42378 * 0b1010..The gate has been locked by processor with master_index = 9.
42379 * 0b1011..The gate has been locked by processor with master_index = 10.
42380 * 0b1100..The gate has been locked by processor with master_index = 11.
42381 * 0b1101..The gate has been locked by processor with master_index = 12.
42382 * 0b1110..The gate has been locked by processor with master_index = 13.
42383 * 0b1111..The gate has been locked by processor with master_index = 14.
42384 */
42385#define RDC_SEMAPHORE_GATE57_GTFSM(x) \
42386 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE57_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE57_GTFSM_MASK)
42387#define RDC_SEMAPHORE_GATE57_LDOM_MASK (0x30U)
42388#define RDC_SEMAPHORE_GATE57_LDOM_SHIFT (4U)
42389/*! LDOM
42390 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
42391 * 0b01..The gate has been locked by domain 1.
42392 * 0b10..The gate has been locked by domain 2.
42393 * 0b11..The gate has been locked by domain 3.
42394 */
42395#define RDC_SEMAPHORE_GATE57_LDOM(x) \
42396 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE57_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE57_LDOM_MASK)
42397/*! @} */
42398
42399/*! @name GATE58 - Gate Register */
42400/*! @{ */
42401#define RDC_SEMAPHORE_GATE58_GTFSM_MASK (0xFU)
42402#define RDC_SEMAPHORE_GATE58_GTFSM_SHIFT (0U)
42403/*! GTFSM - Gate Finite State Machine.
42404 * 0b0000..The gate is unlocked (free).
42405 * 0b0001..The gate has been locked by processor with master_index = 0.
42406 * 0b0010..The gate has been locked by processor with master_index = 1.
42407 * 0b0011..The gate has been locked by processor with master_index = 2.
42408 * 0b0100..The gate has been locked by processor with master_index = 3.
42409 * 0b0101..The gate has been locked by processor with master_index = 4.
42410 * 0b0110..The gate has been locked by processor with master_index = 5.
42411 * 0b0111..The gate has been locked by processor with master_index = 6.
42412 * 0b1000..The gate has been locked by processor with master_index = 7.
42413 * 0b1001..The gate has been locked by processor with master_index = 8.
42414 * 0b1010..The gate has been locked by processor with master_index = 9.
42415 * 0b1011..The gate has been locked by processor with master_index = 10.
42416 * 0b1100..The gate has been locked by processor with master_index = 11.
42417 * 0b1101..The gate has been locked by processor with master_index = 12.
42418 * 0b1110..The gate has been locked by processor with master_index = 13.
42419 * 0b1111..The gate has been locked by processor with master_index = 14.
42420 */
42421#define RDC_SEMAPHORE_GATE58_GTFSM(x) \
42422 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE58_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE58_GTFSM_MASK)
42423#define RDC_SEMAPHORE_GATE58_LDOM_MASK (0x30U)
42424#define RDC_SEMAPHORE_GATE58_LDOM_SHIFT (4U)
42425/*! LDOM
42426 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
42427 * 0b01..The gate has been locked by domain 1.
42428 * 0b10..The gate has been locked by domain 2.
42429 * 0b11..The gate has been locked by domain 3.
42430 */
42431#define RDC_SEMAPHORE_GATE58_LDOM(x) \
42432 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE58_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE58_LDOM_MASK)
42433/*! @} */
42434
42435/*! @name GATE59 - Gate Register */
42436/*! @{ */
42437#define RDC_SEMAPHORE_GATE59_GTFSM_MASK (0xFU)
42438#define RDC_SEMAPHORE_GATE59_GTFSM_SHIFT (0U)
42439/*! GTFSM - Gate Finite State Machine.
42440 * 0b0000..The gate is unlocked (free).
42441 * 0b0001..The gate has been locked by processor with master_index = 0.
42442 * 0b0010..The gate has been locked by processor with master_index = 1.
42443 * 0b0011..The gate has been locked by processor with master_index = 2.
42444 * 0b0100..The gate has been locked by processor with master_index = 3.
42445 * 0b0101..The gate has been locked by processor with master_index = 4.
42446 * 0b0110..The gate has been locked by processor with master_index = 5.
42447 * 0b0111..The gate has been locked by processor with master_index = 6.
42448 * 0b1000..The gate has been locked by processor with master_index = 7.
42449 * 0b1001..The gate has been locked by processor with master_index = 8.
42450 * 0b1010..The gate has been locked by processor with master_index = 9.
42451 * 0b1011..The gate has been locked by processor with master_index = 10.
42452 * 0b1100..The gate has been locked by processor with master_index = 11.
42453 * 0b1101..The gate has been locked by processor with master_index = 12.
42454 * 0b1110..The gate has been locked by processor with master_index = 13.
42455 * 0b1111..The gate has been locked by processor with master_index = 14.
42456 */
42457#define RDC_SEMAPHORE_GATE59_GTFSM(x) \
42458 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE59_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE59_GTFSM_MASK)
42459#define RDC_SEMAPHORE_GATE59_LDOM_MASK (0x30U)
42460#define RDC_SEMAPHORE_GATE59_LDOM_SHIFT (4U)
42461/*! LDOM
42462 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
42463 * 0b01..The gate has been locked by domain 1.
42464 * 0b10..The gate has been locked by domain 2.
42465 * 0b11..The gate has been locked by domain 3.
42466 */
42467#define RDC_SEMAPHORE_GATE59_LDOM(x) \
42468 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE59_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE59_LDOM_MASK)
42469/*! @} */
42470
42471/*! @name GATE60 - Gate Register */
42472/*! @{ */
42473#define RDC_SEMAPHORE_GATE60_GTFSM_MASK (0xFU)
42474#define RDC_SEMAPHORE_GATE60_GTFSM_SHIFT (0U)
42475/*! GTFSM - Gate Finite State Machine.
42476 * 0b0000..The gate is unlocked (free).
42477 * 0b0001..The gate has been locked by processor with master_index = 0.
42478 * 0b0010..The gate has been locked by processor with master_index = 1.
42479 * 0b0011..The gate has been locked by processor with master_index = 2.
42480 * 0b0100..The gate has been locked by processor with master_index = 3.
42481 * 0b0101..The gate has been locked by processor with master_index = 4.
42482 * 0b0110..The gate has been locked by processor with master_index = 5.
42483 * 0b0111..The gate has been locked by processor with master_index = 6.
42484 * 0b1000..The gate has been locked by processor with master_index = 7.
42485 * 0b1001..The gate has been locked by processor with master_index = 8.
42486 * 0b1010..The gate has been locked by processor with master_index = 9.
42487 * 0b1011..The gate has been locked by processor with master_index = 10.
42488 * 0b1100..The gate has been locked by processor with master_index = 11.
42489 * 0b1101..The gate has been locked by processor with master_index = 12.
42490 * 0b1110..The gate has been locked by processor with master_index = 13.
42491 * 0b1111..The gate has been locked by processor with master_index = 14.
42492 */
42493#define RDC_SEMAPHORE_GATE60_GTFSM(x) \
42494 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE60_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE60_GTFSM_MASK)
42495#define RDC_SEMAPHORE_GATE60_LDOM_MASK (0x30U)
42496#define RDC_SEMAPHORE_GATE60_LDOM_SHIFT (4U)
42497/*! LDOM
42498 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
42499 * 0b01..The gate has been locked by domain 1.
42500 * 0b10..The gate has been locked by domain 2.
42501 * 0b11..The gate has been locked by domain 3.
42502 */
42503#define RDC_SEMAPHORE_GATE60_LDOM(x) \
42504 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE60_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE60_LDOM_MASK)
42505/*! @} */
42506
42507/*! @name GATE61 - Gate Register */
42508/*! @{ */
42509#define RDC_SEMAPHORE_GATE61_GTFSM_MASK (0xFU)
42510#define RDC_SEMAPHORE_GATE61_GTFSM_SHIFT (0U)
42511/*! GTFSM - Gate Finite State Machine.
42512 * 0b0000..The gate is unlocked (free).
42513 * 0b0001..The gate has been locked by processor with master_index = 0.
42514 * 0b0010..The gate has been locked by processor with master_index = 1.
42515 * 0b0011..The gate has been locked by processor with master_index = 2.
42516 * 0b0100..The gate has been locked by processor with master_index = 3.
42517 * 0b0101..The gate has been locked by processor with master_index = 4.
42518 * 0b0110..The gate has been locked by processor with master_index = 5.
42519 * 0b0111..The gate has been locked by processor with master_index = 6.
42520 * 0b1000..The gate has been locked by processor with master_index = 7.
42521 * 0b1001..The gate has been locked by processor with master_index = 8.
42522 * 0b1010..The gate has been locked by processor with master_index = 9.
42523 * 0b1011..The gate has been locked by processor with master_index = 10.
42524 * 0b1100..The gate has been locked by processor with master_index = 11.
42525 * 0b1101..The gate has been locked by processor with master_index = 12.
42526 * 0b1110..The gate has been locked by processor with master_index = 13.
42527 * 0b1111..The gate has been locked by processor with master_index = 14.
42528 */
42529#define RDC_SEMAPHORE_GATE61_GTFSM(x) \
42530 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE61_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE61_GTFSM_MASK)
42531#define RDC_SEMAPHORE_GATE61_LDOM_MASK (0x30U)
42532#define RDC_SEMAPHORE_GATE61_LDOM_SHIFT (4U)
42533/*! LDOM
42534 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
42535 * 0b01..The gate has been locked by domain 1.
42536 * 0b10..The gate has been locked by domain 2.
42537 * 0b11..The gate has been locked by domain 3.
42538 */
42539#define RDC_SEMAPHORE_GATE61_LDOM(x) \
42540 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE61_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE61_LDOM_MASK)
42541/*! @} */
42542
42543/*! @name GATE62 - Gate Register */
42544/*! @{ */
42545#define RDC_SEMAPHORE_GATE62_GTFSM_MASK (0xFU)
42546#define RDC_SEMAPHORE_GATE62_GTFSM_SHIFT (0U)
42547/*! GTFSM - Gate Finite State Machine.
42548 * 0b0000..The gate is unlocked (free).
42549 * 0b0001..The gate has been locked by processor with master_index = 0.
42550 * 0b0010..The gate has been locked by processor with master_index = 1.
42551 * 0b0011..The gate has been locked by processor with master_index = 2.
42552 * 0b0100..The gate has been locked by processor with master_index = 3.
42553 * 0b0101..The gate has been locked by processor with master_index = 4.
42554 * 0b0110..The gate has been locked by processor with master_index = 5.
42555 * 0b0111..The gate has been locked by processor with master_index = 6.
42556 * 0b1000..The gate has been locked by processor with master_index = 7.
42557 * 0b1001..The gate has been locked by processor with master_index = 8.
42558 * 0b1010..The gate has been locked by processor with master_index = 9.
42559 * 0b1011..The gate has been locked by processor with master_index = 10.
42560 * 0b1100..The gate has been locked by processor with master_index = 11.
42561 * 0b1101..The gate has been locked by processor with master_index = 12.
42562 * 0b1110..The gate has been locked by processor with master_index = 13.
42563 * 0b1111..The gate has been locked by processor with master_index = 14.
42564 */
42565#define RDC_SEMAPHORE_GATE62_GTFSM(x) \
42566 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE62_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE62_GTFSM_MASK)
42567#define RDC_SEMAPHORE_GATE62_LDOM_MASK (0x30U)
42568#define RDC_SEMAPHORE_GATE62_LDOM_SHIFT (4U)
42569/*! LDOM
42570 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
42571 * 0b01..The gate has been locked by domain 1.
42572 * 0b10..The gate has been locked by domain 2.
42573 * 0b11..The gate has been locked by domain 3.
42574 */
42575#define RDC_SEMAPHORE_GATE62_LDOM(x) \
42576 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE62_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE62_LDOM_MASK)
42577/*! @} */
42578
42579/*! @name GATE63 - Gate Register */
42580/*! @{ */
42581#define RDC_SEMAPHORE_GATE63_GTFSM_MASK (0xFU)
42582#define RDC_SEMAPHORE_GATE63_GTFSM_SHIFT (0U)
42583/*! GTFSM - Gate Finite State Machine.
42584 * 0b0000..The gate is unlocked (free).
42585 * 0b0001..The gate has been locked by processor with master_index = 0.
42586 * 0b0010..The gate has been locked by processor with master_index = 1.
42587 * 0b0011..The gate has been locked by processor with master_index = 2.
42588 * 0b0100..The gate has been locked by processor with master_index = 3.
42589 * 0b0101..The gate has been locked by processor with master_index = 4.
42590 * 0b0110..The gate has been locked by processor with master_index = 5.
42591 * 0b0111..The gate has been locked by processor with master_index = 6.
42592 * 0b1000..The gate has been locked by processor with master_index = 7.
42593 * 0b1001..The gate has been locked by processor with master_index = 8.
42594 * 0b1010..The gate has been locked by processor with master_index = 9.
42595 * 0b1011..The gate has been locked by processor with master_index = 10.
42596 * 0b1100..The gate has been locked by processor with master_index = 11.
42597 * 0b1101..The gate has been locked by processor with master_index = 12.
42598 * 0b1110..The gate has been locked by processor with master_index = 13.
42599 * 0b1111..The gate has been locked by processor with master_index = 14.
42600 */
42601#define RDC_SEMAPHORE_GATE63_GTFSM(x) \
42602 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE63_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE63_GTFSM_MASK)
42603#define RDC_SEMAPHORE_GATE63_LDOM_MASK (0x30U)
42604#define RDC_SEMAPHORE_GATE63_LDOM_SHIFT (4U)
42605/*! LDOM
42606 * 0b00..The gate is locked by domain 0. (True if bits [3:0] do not equal 0000.)
42607 * 0b01..The gate has been locked by domain 1.
42608 * 0b10..The gate has been locked by domain 2.
42609 * 0b11..The gate has been locked by domain 3.
42610 */
42611#define RDC_SEMAPHORE_GATE63_LDOM(x) \
42612 (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE63_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE63_LDOM_MASK)
42613/*! @} */
42614
42615/*! @name RSTGT_R - Reset Gate Read */
42616/*! @{ */
42617#define RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK (0xFU)
42618#define RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT (0U)
42619#define RDC_SEMAPHORE_RSTGT_R_RSTGMS(x) \
42620 (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK)
42621#define RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK (0x30U)
42622#define RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT (4U)
42623/*! RSTGSM
42624 * 0b00..Idle, waiting for the first data pattern write.
42625 * 0b01..Waiting for the second data pattern write.
42626 * 0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed,
42627 * this machine returns to the idle (waiting for first data pattern write) state. The "01" state persists
42628 * for only one clock cycle. Software will never be able to observe this state.
42629 * 0b11..This state encoding is never used and therefore reserved.
42630 */
42631#define RDC_SEMAPHORE_RSTGT_R_RSTGSM(x) \
42632 (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK)
42633#define RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK (0xFF00U)
42634#define RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT (8U)
42635#define RDC_SEMAPHORE_RSTGT_R_RSTGTN(x) \
42636 (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK)
42637/*! @} */
42638
42639/*! @name RSTGT_W - Reset Gate Write */
42640/*! @{ */
42641#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK (0xFFU)
42642#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT (0U)
42643#define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x) \
42644 (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK)
42645#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK (0xFF00U)
42646#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT (8U)
42647#define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x) \
42648 (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK)
42649/*! @} */
42650
42651/*!
42652 * @}
42653 */ /* end of group RDC_SEMAPHORE_Register_Masks */
42654
42655/* RDC_SEMAPHORE - Peripheral instance base addresses */
42656/** Peripheral RDC_SEMAPHORE1 base address */
42657#define RDC_SEMAPHORE1_BASE (0x303B0000u)
42658/** Peripheral RDC_SEMAPHORE1 base pointer */
42659#define RDC_SEMAPHORE1 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE1_BASE)
42660/** Peripheral RDC_SEMAPHORE2 base address */
42661#define RDC_SEMAPHORE2_BASE (0x303C0000u)
42662/** Peripheral RDC_SEMAPHORE2 base pointer */
42663#define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
42664/** Array initializer of RDC_SEMAPHORE peripheral base addresses */
42665#define RDC_SEMAPHORE_BASE_ADDRS \
42666 { \
42667 0u, RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE \
42668 }
42669/** Array initializer of RDC_SEMAPHORE peripheral base pointers */
42670#define RDC_SEMAPHORE_BASE_PTRS \
42671 { \
42672 (RDC_SEMAPHORE_Type *)0u, RDC_SEMAPHORE1, RDC_SEMAPHORE2 \
42673 }
42674
42675/*!
42676 * @}
42677 */ /* end of group RDC_SEMAPHORE_Peripheral_Access_Layer */
42678
42679/* ----------------------------------------------------------------------------
42680 -- SDMAARM Peripheral Access Layer
42681 ---------------------------------------------------------------------------- */
42682
42683/*!
42684 * @addtogroup SDMAARM_Peripheral_Access_Layer SDMAARM Peripheral Access Layer
42685 * @{
42686 */
42687
42688/** SDMAARM - Register Layout Typedef */
42689typedef struct
42690{
42691 __IO uint32_t MC0PTR; /**< Arm platform Channel 0 Pointer, offset: 0x0 */
42692 __IO uint32_t INTR; /**< Channel Interrupts, offset: 0x4 */
42693 __IO uint32_t STOP_STAT; /**< Channel Stop/Channel Status, offset: 0x8 */
42694 __IO uint32_t HSTART; /**< Channel Start, offset: 0xC */
42695 __IO uint32_t EVTOVR; /**< Channel Event Override, offset: 0x10 */
42696 __IO uint32_t DSPOVR; /**< Channel BP Override, offset: 0x14 */
42697 __IO uint32_t HOSTOVR; /**< Channel Arm platform Override, offset: 0x18 */
42698 __IO uint32_t EVTPEND; /**< Channel Event Pending, offset: 0x1C */
42699 uint8_t RESERVED_0[4];
42700 __I uint32_t RESET; /**< Reset Register, offset: 0x24 */
42701 __I uint32_t EVTERR; /**< DMA Request Error Register, offset: 0x28 */
42702 __IO uint32_t INTRMASK; /**< Channel Arm platform Interrupt Mask, offset: 0x2C */
42703 __I uint32_t PSW; /**< Schedule Status, offset: 0x30 */
42704 __I uint32_t EVTERRDBG; /**< DMA Request Error Register, offset: 0x34 */
42705 __IO uint32_t CONFIG; /**< Configuration Register, offset: 0x38 */
42706 __IO uint32_t SDMA_LOCK; /**< SDMA LOCK, offset: 0x3C */
42707 __IO uint32_t ONCE_ENB; /**< OnCE Enable, offset: 0x40 */
42708 __IO uint32_t ONCE_DATA; /**< OnCE Data Register, offset: 0x44 */
42709 __IO uint32_t ONCE_INSTR; /**< OnCE Instruction Register, offset: 0x48 */
42710 __I uint32_t ONCE_STAT; /**< OnCE Status Register, offset: 0x4C */
42711 __IO uint32_t ONCE_CMD; /**< OnCE Command Register, offset: 0x50 */
42712 uint8_t RESERVED_1[4];
42713 __IO uint32_t ILLINSTADDR; /**< Illegal Instruction Trap Address, offset: 0x58 */
42714 __IO uint32_t CHN0ADDR; /**< Channel 0 Boot Address, offset: 0x5C */
42715 __I uint32_t EVT_MIRROR; /**< DMA Requests, offset: 0x60 */
42716 __I uint32_t EVT_MIRROR2; /**< DMA Requests 2, offset: 0x64 */
42717 uint8_t RESERVED_2[8];
42718 __IO uint32_t XTRIG_CONF1; /**< Cross-Trigger Events Configuration Register 1, offset: 0x70 */
42719 __IO uint32_t XTRIG_CONF2; /**< Cross-Trigger Events Configuration Register 2, offset: 0x74 */
42720 uint8_t RESERVED_3[136];
42721 __IO uint32_t SDMA_CHNPRI[32]; /**< Channel Priority Registers, array offset: 0x100, array step: 0x4 */
42722 uint8_t RESERVED_4[128];
42723 __IO uint32_t CHNENBL[48]; /**< Channel Enable RAM, array offset: 0x200, array step: 0x4 */
42724 uint8_t RESERVED_5[3392];
42725 __IO uint32_t DONE0_CONFIG; /**< SDMA DONE0 Configuration, offset: 0x1000 */
42726 __IO uint32_t DONE1_CONFIG; /**< SDMA DONE1 Configuration, offset: 0x1004 */
42727} SDMAARM_Type;
42728
42729/* ----------------------------------------------------------------------------
42730 -- SDMAARM Register Masks
42731 ---------------------------------------------------------------------------- */
42732
42733/*!
42734 * @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks
42735 * @{
42736 */
42737
42738/*! @name MC0PTR - Arm platform Channel 0 Pointer */
42739/*! @{ */
42740#define SDMAARM_MC0PTR_MC0PTR_MASK (0xFFFFFFFFU)
42741#define SDMAARM_MC0PTR_MC0PTR_SHIFT (0U)
42742#define SDMAARM_MC0PTR_MC0PTR(x) \
42743 (((uint32_t)(((uint32_t)(x)) << SDMAARM_MC0PTR_MC0PTR_SHIFT)) & SDMAARM_MC0PTR_MC0PTR_MASK)
42744/*! @} */
42745
42746/*! @name INTR - Channel Interrupts */
42747/*! @{ */
42748#define SDMAARM_INTR_HI_MASK (0xFFFFFFFFU)
42749#define SDMAARM_INTR_HI_SHIFT (0U)
42750#define SDMAARM_INTR_HI(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTR_HI_SHIFT)) & SDMAARM_INTR_HI_MASK)
42751/*! @} */
42752
42753/*! @name STOP_STAT - Channel Stop/Channel Status */
42754/*! @{ */
42755#define SDMAARM_STOP_STAT_HE_MASK (0xFFFFFFFFU)
42756#define SDMAARM_STOP_STAT_HE_SHIFT (0U)
42757#define SDMAARM_STOP_STAT_HE(x) \
42758 (((uint32_t)(((uint32_t)(x)) << SDMAARM_STOP_STAT_HE_SHIFT)) & SDMAARM_STOP_STAT_HE_MASK)
42759/*! @} */
42760
42761/*! @name HSTART - Channel Start */
42762/*! @{ */
42763#define SDMAARM_HSTART_HSTART_HE_MASK (0xFFFFFFFFU)
42764#define SDMAARM_HSTART_HSTART_HE_SHIFT (0U)
42765#define SDMAARM_HSTART_HSTART_HE(x) \
42766 (((uint32_t)(((uint32_t)(x)) << SDMAARM_HSTART_HSTART_HE_SHIFT)) & SDMAARM_HSTART_HSTART_HE_MASK)
42767/*! @} */
42768
42769/*! @name EVTOVR - Channel Event Override */
42770/*! @{ */
42771#define SDMAARM_EVTOVR_EO_MASK (0xFFFFFFFFU)
42772#define SDMAARM_EVTOVR_EO_SHIFT (0U)
42773#define SDMAARM_EVTOVR_EO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTOVR_EO_SHIFT)) & SDMAARM_EVTOVR_EO_MASK)
42774/*! @} */
42775
42776/*! @name DSPOVR - Channel BP Override */
42777/*! @{ */
42778#define SDMAARM_DSPOVR_DO_MASK (0xFFFFFFFFU)
42779#define SDMAARM_DSPOVR_DO_SHIFT (0U)
42780/*! DO
42781 * 0b00000000000000000000000000000000..- Reserved
42782 * 0b00000000000000000000000000000001..- Reset value.
42783 */
42784#define SDMAARM_DSPOVR_DO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_DSPOVR_DO_SHIFT)) & SDMAARM_DSPOVR_DO_MASK)
42785/*! @} */
42786
42787/*! @name HOSTOVR - Channel Arm platform Override */
42788/*! @{ */
42789#define SDMAARM_HOSTOVR_HO_MASK (0xFFFFFFFFU)
42790#define SDMAARM_HOSTOVR_HO_SHIFT (0U)
42791#define SDMAARM_HOSTOVR_HO(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_HOSTOVR_HO_SHIFT)) & SDMAARM_HOSTOVR_HO_MASK)
42792/*! @} */
42793
42794/*! @name EVTPEND - Channel Event Pending */
42795/*! @{ */
42796#define SDMAARM_EVTPEND_EP_MASK (0xFFFFFFFFU)
42797#define SDMAARM_EVTPEND_EP_SHIFT (0U)
42798#define SDMAARM_EVTPEND_EP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTPEND_EP_SHIFT)) & SDMAARM_EVTPEND_EP_MASK)
42799/*! @} */
42800
42801/*! @name RESET - Reset Register */
42802/*! @{ */
42803#define SDMAARM_RESET_RESET_MASK (0x1U)
42804#define SDMAARM_RESET_RESET_SHIFT (0U)
42805#define SDMAARM_RESET_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESET_SHIFT)) & SDMAARM_RESET_RESET_MASK)
42806#define SDMAARM_RESET_RESCHED_MASK (0x2U)
42807#define SDMAARM_RESET_RESCHED_SHIFT (1U)
42808#define SDMAARM_RESET_RESCHED(x) \
42809 (((uint32_t)(((uint32_t)(x)) << SDMAARM_RESET_RESCHED_SHIFT)) & SDMAARM_RESET_RESCHED_MASK)
42810/*! @} */
42811
42812/*! @name EVTERR - DMA Request Error Register */
42813/*! @{ */
42814#define SDMAARM_EVTERR_CHNERR_MASK (0xFFFFFFFFU)
42815#define SDMAARM_EVTERR_CHNERR_SHIFT (0U)
42816#define SDMAARM_EVTERR_CHNERR(x) \
42817 (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERR_CHNERR_SHIFT)) & SDMAARM_EVTERR_CHNERR_MASK)
42818/*! @} */
42819
42820/*! @name INTRMASK - Channel Arm platform Interrupt Mask */
42821/*! @{ */
42822#define SDMAARM_INTRMASK_HIMASK_MASK (0xFFFFFFFFU)
42823#define SDMAARM_INTRMASK_HIMASK_SHIFT (0U)
42824#define SDMAARM_INTRMASK_HIMASK(x) \
42825 (((uint32_t)(((uint32_t)(x)) << SDMAARM_INTRMASK_HIMASK_SHIFT)) & SDMAARM_INTRMASK_HIMASK_MASK)
42826/*! @} */
42827
42828/*! @name PSW - Schedule Status */
42829/*! @{ */
42830#define SDMAARM_PSW_CCR_MASK (0xFU)
42831#define SDMAARM_PSW_CCR_SHIFT (0U)
42832#define SDMAARM_PSW_CCR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCR_SHIFT)) & SDMAARM_PSW_CCR_MASK)
42833#define SDMAARM_PSW_CCP_MASK (0xF0U)
42834#define SDMAARM_PSW_CCP_SHIFT (4U)
42835/*! CCP
42836 * 0b0000..No running channel
42837 * 0b0001..Active channel priority
42838 */
42839#define SDMAARM_PSW_CCP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_CCP_SHIFT)) & SDMAARM_PSW_CCP_MASK)
42840#define SDMAARM_PSW_NCR_MASK (0x1F00U)
42841#define SDMAARM_PSW_NCR_SHIFT (8U)
42842#define SDMAARM_PSW_NCR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCR_SHIFT)) & SDMAARM_PSW_NCR_MASK)
42843#define SDMAARM_PSW_NCP_MASK (0xE000U)
42844#define SDMAARM_PSW_NCP_SHIFT (13U)
42845/*! NCP
42846 * 0b000..No running channel
42847 * 0b001..Active channel priority
42848 */
42849#define SDMAARM_PSW_NCP(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_PSW_NCP_SHIFT)) & SDMAARM_PSW_NCP_MASK)
42850/*! @} */
42851
42852/*! @name EVTERRDBG - DMA Request Error Register */
42853/*! @{ */
42854#define SDMAARM_EVTERRDBG_CHNERR_MASK (0xFFFFFFFFU)
42855#define SDMAARM_EVTERRDBG_CHNERR_SHIFT (0U)
42856#define SDMAARM_EVTERRDBG_CHNERR(x) \
42857 (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVTERRDBG_CHNERR_SHIFT)) & SDMAARM_EVTERRDBG_CHNERR_MASK)
42858/*! @} */
42859
42860/*! @name CONFIG - Configuration Register */
42861/*! @{ */
42862#define SDMAARM_CONFIG_CSM_MASK (0x3U)
42863#define SDMAARM_CONFIG_CSM_SHIFT (0U)
42864/*! CSM
42865 * 0b00..static
42866 * 0b01..dynamic low power
42867 * 0b10..dynamic with no loop
42868 * 0b11..dynamic
42869 */
42870#define SDMAARM_CONFIG_CSM(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_CSM_SHIFT)) & SDMAARM_CONFIG_CSM_MASK)
42871#define SDMAARM_CONFIG_ACR_MASK (0x10U)
42872#define SDMAARM_CONFIG_ACR_SHIFT (4U)
42873/*! ACR
42874 * 0b0..Arm platform DMA interface frequency equals twice core frequency
42875 * 0b1..Arm platform DMA interface frequency equals core frequency
42876 */
42877#define SDMAARM_CONFIG_ACR(x) (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_ACR_SHIFT)) & SDMAARM_CONFIG_ACR_MASK)
42878#define SDMAARM_CONFIG_RTDOBS_MASK (0x800U)
42879#define SDMAARM_CONFIG_RTDOBS_SHIFT (11U)
42880/*! RTDOBS
42881 * 0b0..RTD pins disabled
42882 * 0b1..RTD pins enabled
42883 */
42884#define SDMAARM_CONFIG_RTDOBS(x) \
42885 (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_RTDOBS_SHIFT)) & SDMAARM_CONFIG_RTDOBS_MASK)
42886#define SDMAARM_CONFIG_DSPDMA_MASK (0x1000U)
42887#define SDMAARM_CONFIG_DSPDMA_SHIFT (12U)
42888/*! DSPDMA
42889 * 0b0..- Reset Value
42890 * 0b1..- Reserved
42891 */
42892#define SDMAARM_CONFIG_DSPDMA(x) \
42893 (((uint32_t)(((uint32_t)(x)) << SDMAARM_CONFIG_DSPDMA_SHIFT)) & SDMAARM_CONFIG_DSPDMA_MASK)
42894/*! @} */
42895
42896/*! @name SDMA_LOCK - SDMA LOCK */
42897/*! @{ */
42898#define SDMAARM_SDMA_LOCK_LOCK_MASK (0x1U)
42899#define SDMAARM_SDMA_LOCK_LOCK_SHIFT (0U)
42900/*! LOCK
42901 * 0b0..LOCK disengaged.
42902 * 0b1..LOCK enabled.
42903 */
42904#define SDMAARM_SDMA_LOCK_LOCK(x) \
42905 (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_LOCK_SHIFT)) & SDMAARM_SDMA_LOCK_LOCK_MASK)
42906#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK (0x2U)
42907#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT (1U)
42908/*! SRESET_LOCK_CLR
42909 * 0b0..Software Reset does not clear the LOCK bit.
42910 * 0b1..Software Reset clears the LOCK bit.
42911 */
42912#define SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR(x) \
42913 (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_SHIFT)) & SDMAARM_SDMA_LOCK_SRESET_LOCK_CLR_MASK)
42914/*! @} */
42915
42916/*! @name ONCE_ENB - OnCE Enable */
42917/*! @{ */
42918#define SDMAARM_ONCE_ENB_ENB_MASK (0x1U)
42919#define SDMAARM_ONCE_ENB_ENB_SHIFT (0U)
42920#define SDMAARM_ONCE_ENB_ENB(x) \
42921 (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_ENB_ENB_SHIFT)) & SDMAARM_ONCE_ENB_ENB_MASK)
42922/*! @} */
42923
42924/*! @name ONCE_DATA - OnCE Data Register */
42925/*! @{ */
42926#define SDMAARM_ONCE_DATA_DATA_MASK (0xFFFFFFFFU)
42927#define SDMAARM_ONCE_DATA_DATA_SHIFT (0U)
42928#define SDMAARM_ONCE_DATA_DATA(x) \
42929 (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_DATA_DATA_SHIFT)) & SDMAARM_ONCE_DATA_DATA_MASK)
42930/*! @} */
42931
42932/*! @name ONCE_INSTR - OnCE Instruction Register */
42933/*! @{ */
42934#define SDMAARM_ONCE_INSTR_INSTR_MASK (0xFFFFU)
42935#define SDMAARM_ONCE_INSTR_INSTR_SHIFT (0U)
42936#define SDMAARM_ONCE_INSTR_INSTR(x) \
42937 (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_INSTR_INSTR_SHIFT)) & SDMAARM_ONCE_INSTR_INSTR_MASK)
42938/*! @} */
42939
42940/*! @name ONCE_STAT - OnCE Status Register */
42941/*! @{ */
42942#define SDMAARM_ONCE_STAT_ECDR_MASK (0x7U)
42943#define SDMAARM_ONCE_STAT_ECDR_SHIFT (0U)
42944/*! ECDR
42945 * 0b000..1 matched addra_cond
42946 * 0b001..1 matched addrb_cond
42947 * 0b010..1 matched data_cond
42948 */
42949#define SDMAARM_ONCE_STAT_ECDR(x) \
42950 (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ECDR_SHIFT)) & SDMAARM_ONCE_STAT_ECDR_MASK)
42951#define SDMAARM_ONCE_STAT_MST_MASK (0x80U)
42952#define SDMAARM_ONCE_STAT_MST_SHIFT (7U)
42953/*! MST
42954 * 0b0..The JTAG interface controls the OnCE.
42955 * 0b1..The Arm platform peripheral interface controls the OnCE.
42956 */
42957#define SDMAARM_ONCE_STAT_MST(x) \
42958 (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_MST_SHIFT)) & SDMAARM_ONCE_STAT_MST_MASK)
42959#define SDMAARM_ONCE_STAT_SWB_MASK (0x100U)
42960#define SDMAARM_ONCE_STAT_SWB_SHIFT (8U)
42961#define SDMAARM_ONCE_STAT_SWB(x) \
42962 (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_SWB_SHIFT)) & SDMAARM_ONCE_STAT_SWB_MASK)
42963#define SDMAARM_ONCE_STAT_ODR_MASK (0x200U)
42964#define SDMAARM_ONCE_STAT_ODR_SHIFT (9U)
42965#define SDMAARM_ONCE_STAT_ODR(x) \
42966 (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_ODR_SHIFT)) & SDMAARM_ONCE_STAT_ODR_MASK)
42967#define SDMAARM_ONCE_STAT_EDR_MASK (0x400U)
42968#define SDMAARM_ONCE_STAT_EDR_SHIFT (10U)
42969#define SDMAARM_ONCE_STAT_EDR(x) \
42970 (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_EDR_SHIFT)) & SDMAARM_ONCE_STAT_EDR_MASK)
42971#define SDMAARM_ONCE_STAT_RCV_MASK (0x800U)
42972#define SDMAARM_ONCE_STAT_RCV_SHIFT (11U)
42973#define SDMAARM_ONCE_STAT_RCV(x) \
42974 (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_RCV_SHIFT)) & SDMAARM_ONCE_STAT_RCV_MASK)
42975#define SDMAARM_ONCE_STAT_PST_MASK (0xF000U)
42976#define SDMAARM_ONCE_STAT_PST_SHIFT (12U)
42977/*! PST
42978 * 0b0000..Program
42979 * 0b0001..Data
42980 * 0b0010..Change of Flow
42981 * 0b0011..Change of Flow in Loop
42982 * 0b0100..Debug
42983 * 0b0101..Functional Unit
42984 * 0b0110..Sleep
42985 * 0b0111..Save
42986 * 0b1000..Program in Sleep
42987 * 0b1001..Data in Sleep
42988 * 0b0010..Change of Flow in Sleep
42989 * 0b0011..Change Flow in Loop in Sleep
42990 * 0b1100..Debug in Sleep
42991 * 0b1101..Functional Unit in Sleep
42992 * 0b1110..Sleep after Reset
42993 * 0b1111..Restore
42994 */
42995#define SDMAARM_ONCE_STAT_PST(x) \
42996 (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_STAT_PST_SHIFT)) & SDMAARM_ONCE_STAT_PST_MASK)
42997/*! @} */
42998
42999/*! @name ONCE_CMD - OnCE Command Register */
43000/*! @{ */
43001#define SDMAARM_ONCE_CMD_CMD_MASK (0xFU)
43002#define SDMAARM_ONCE_CMD_CMD_SHIFT (0U)
43003/*! CMD
43004 * 0b0000..rstatus
43005 * 0b0001..dmov
43006 * 0b0010..exec_once
43007 * 0b0011..run_core
43008 * 0b0100..exec_core
43009 * 0b0101..debug_rqst
43010 * 0b0110..rbuffer
43011 */
43012#define SDMAARM_ONCE_CMD_CMD(x) \
43013 (((uint32_t)(((uint32_t)(x)) << SDMAARM_ONCE_CMD_CMD_SHIFT)) & SDMAARM_ONCE_CMD_CMD_MASK)
43014/*! @} */
43015
43016/*! @name ILLINSTADDR - Illegal Instruction Trap Address */
43017/*! @{ */
43018#define SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK (0x3FFFU)
43019#define SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT (0U)
43020#define SDMAARM_ILLINSTADDR_ILLINSTADDR(x) \
43021 (((uint32_t)(((uint32_t)(x)) << SDMAARM_ILLINSTADDR_ILLINSTADDR_SHIFT)) & SDMAARM_ILLINSTADDR_ILLINSTADDR_MASK)
43022/*! @} */
43023
43024/*! @name CHN0ADDR - Channel 0 Boot Address */
43025/*! @{ */
43026#define SDMAARM_CHN0ADDR_CHN0ADDR_MASK (0x3FFFU)
43027#define SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT (0U)
43028#define SDMAARM_CHN0ADDR_CHN0ADDR(x) \
43029 (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_CHN0ADDR_SHIFT)) & SDMAARM_CHN0ADDR_CHN0ADDR_MASK)
43030#define SDMAARM_CHN0ADDR_SMSZ_MASK (0x4000U)
43031#define SDMAARM_CHN0ADDR_SMSZ_SHIFT (14U)
43032/*! SMSZ
43033 * 0b0..24 words per context
43034 * 0b1..32 words per context
43035 */
43036#define SDMAARM_CHN0ADDR_SMSZ(x) \
43037 (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHN0ADDR_SMSZ_SHIFT)) & SDMAARM_CHN0ADDR_SMSZ_MASK)
43038/*! @} */
43039
43040/*! @name EVT_MIRROR - DMA Requests */
43041/*! @{ */
43042#define SDMAARM_EVT_MIRROR_EVENTS_MASK (0xFFFFFFFFU)
43043#define SDMAARM_EVT_MIRROR_EVENTS_SHIFT (0U)
43044/*! EVENTS
43045 * 0b00000000000000000000000000000000..DMA request event not pending
43046 * 0b00000000000000000000000000000001..DMA request event pending
43047 */
43048#define SDMAARM_EVT_MIRROR_EVENTS(x) \
43049 (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR_EVENTS_MASK)
43050/*! @} */
43051
43052/*! @name EVT_MIRROR2 - DMA Requests 2 */
43053/*! @{ */
43054#define SDMAARM_EVT_MIRROR2_EVENTS_MASK (0xFFFFU)
43055#define SDMAARM_EVT_MIRROR2_EVENTS_SHIFT (0U)
43056/*! EVENTS
43057 * 0b0000000000000000..- DMA request event not pending
43058 */
43059#define SDMAARM_EVT_MIRROR2_EVENTS(x) \
43060 (((uint32_t)(((uint32_t)(x)) << SDMAARM_EVT_MIRROR2_EVENTS_SHIFT)) & SDMAARM_EVT_MIRROR2_EVENTS_MASK)
43061/*! @} */
43062
43063/*! @name XTRIG_CONF1 - Cross-Trigger Events Configuration Register 1 */
43064/*! @{ */
43065#define SDMAARM_XTRIG_CONF1_NUM0_MASK (0x3FU)
43066#define SDMAARM_XTRIG_CONF1_NUM0_SHIFT (0U)
43067#define SDMAARM_XTRIG_CONF1_NUM0(x) \
43068 (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM0_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM0_MASK)
43069#define SDMAARM_XTRIG_CONF1_CNF0_MASK (0x40U)
43070#define SDMAARM_XTRIG_CONF1_CNF0_SHIFT (6U)
43071/*! CNF0
43072 * 0b0..channel
43073 * 0b1..DMA request
43074 */
43075#define SDMAARM_XTRIG_CONF1_CNF0(x) \
43076 (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF0_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF0_MASK)
43077#define SDMAARM_XTRIG_CONF1_NUM1_MASK (0x3F00U)
43078#define SDMAARM_XTRIG_CONF1_NUM1_SHIFT (8U)
43079#define SDMAARM_XTRIG_CONF1_NUM1(x) \
43080 (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM1_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM1_MASK)
43081#define SDMAARM_XTRIG_CONF1_CNF1_MASK (0x4000U)
43082#define SDMAARM_XTRIG_CONF1_CNF1_SHIFT (14U)
43083/*! CNF1
43084 * 0b0..channel
43085 * 0b1..DMA request
43086 */
43087#define SDMAARM_XTRIG_CONF1_CNF1(x) \
43088 (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF1_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF1_MASK)
43089#define SDMAARM_XTRIG_CONF1_NUM2_MASK (0x3F0000U)
43090#define SDMAARM_XTRIG_CONF1_NUM2_SHIFT (16U)
43091#define SDMAARM_XTRIG_CONF1_NUM2(x) \
43092 (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM2_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM2_MASK)
43093#define SDMAARM_XTRIG_CONF1_CNF2_MASK (0x400000U)
43094#define SDMAARM_XTRIG_CONF1_CNF2_SHIFT (22U)
43095/*! CNF2
43096 * 0b0..channel
43097 * 0b1..DMA request
43098 */
43099#define SDMAARM_XTRIG_CONF1_CNF2(x) \
43100 (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF2_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF2_MASK)
43101#define SDMAARM_XTRIG_CONF1_NUM3_MASK (0x3F000000U)
43102#define SDMAARM_XTRIG_CONF1_NUM3_SHIFT (24U)
43103#define SDMAARM_XTRIG_CONF1_NUM3(x) \
43104 (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_NUM3_SHIFT)) & SDMAARM_XTRIG_CONF1_NUM3_MASK)
43105#define SDMAARM_XTRIG_CONF1_CNF3_MASK (0x40000000U)
43106#define SDMAARM_XTRIG_CONF1_CNF3_SHIFT (30U)
43107/*! CNF3
43108 * 0b0..channel
43109 * 0b1..DMA request
43110 */
43111#define SDMAARM_XTRIG_CONF1_CNF3(x) \
43112 (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF1_CNF3_SHIFT)) & SDMAARM_XTRIG_CONF1_CNF3_MASK)
43113/*! @} */
43114
43115/*! @name XTRIG_CONF2 - Cross-Trigger Events Configuration Register 2 */
43116/*! @{ */
43117#define SDMAARM_XTRIG_CONF2_NUM4_MASK (0x3FU)
43118#define SDMAARM_XTRIG_CONF2_NUM4_SHIFT (0U)
43119#define SDMAARM_XTRIG_CONF2_NUM4(x) \
43120 (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM4_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM4_MASK)
43121#define SDMAARM_XTRIG_CONF2_CNF4_MASK (0x40U)
43122#define SDMAARM_XTRIG_CONF2_CNF4_SHIFT (6U)
43123/*! CNF4
43124 * 0b0..channel
43125 * 0b1..DMA request
43126 */
43127#define SDMAARM_XTRIG_CONF2_CNF4(x) \
43128 (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF4_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF4_MASK)
43129#define SDMAARM_XTRIG_CONF2_NUM5_MASK (0x3F00U)
43130#define SDMAARM_XTRIG_CONF2_NUM5_SHIFT (8U)
43131#define SDMAARM_XTRIG_CONF2_NUM5(x) \
43132 (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM5_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM5_MASK)
43133#define SDMAARM_XTRIG_CONF2_CNF5_MASK (0x4000U)
43134#define SDMAARM_XTRIG_CONF2_CNF5_SHIFT (14U)
43135/*! CNF5
43136 * 0b0..channel
43137 * 0b1..DMA request
43138 */
43139#define SDMAARM_XTRIG_CONF2_CNF5(x) \
43140 (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF5_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF5_MASK)
43141#define SDMAARM_XTRIG_CONF2_NUM6_MASK (0x3F0000U)
43142#define SDMAARM_XTRIG_CONF2_NUM6_SHIFT (16U)
43143#define SDMAARM_XTRIG_CONF2_NUM6(x) \
43144 (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM6_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM6_MASK)
43145#define SDMAARM_XTRIG_CONF2_CNF6_MASK (0x400000U)
43146#define SDMAARM_XTRIG_CONF2_CNF6_SHIFT (22U)
43147/*! CNF6
43148 * 0b0..channel
43149 * 0b1..DMA request
43150 */
43151#define SDMAARM_XTRIG_CONF2_CNF6(x) \
43152 (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF6_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF6_MASK)
43153#define SDMAARM_XTRIG_CONF2_NUM7_MASK (0x3F000000U)
43154#define SDMAARM_XTRIG_CONF2_NUM7_SHIFT (24U)
43155#define SDMAARM_XTRIG_CONF2_NUM7(x) \
43156 (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_NUM7_SHIFT)) & SDMAARM_XTRIG_CONF2_NUM7_MASK)
43157#define SDMAARM_XTRIG_CONF2_CNF7_MASK (0x40000000U)
43158#define SDMAARM_XTRIG_CONF2_CNF7_SHIFT (30U)
43159/*! CNF7
43160 * 0b0..channel
43161 * 0b1..DMA request
43162 */
43163#define SDMAARM_XTRIG_CONF2_CNF7(x) \
43164 (((uint32_t)(((uint32_t)(x)) << SDMAARM_XTRIG_CONF2_CNF7_SHIFT)) & SDMAARM_XTRIG_CONF2_CNF7_MASK)
43165/*! @} */
43166
43167/*! @name SDMA_CHNPRI - Channel Priority Registers */
43168/*! @{ */
43169#define SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK (0x7U)
43170#define SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT (0U)
43171#define SDMAARM_SDMA_CHNPRI_CHNPRIn(x) \
43172 (((uint32_t)(((uint32_t)(x)) << SDMAARM_SDMA_CHNPRI_CHNPRIn_SHIFT)) & SDMAARM_SDMA_CHNPRI_CHNPRIn_MASK)
43173/*! @} */
43174
43175/* The count of SDMAARM_SDMA_CHNPRI */
43176#define SDMAARM_SDMA_CHNPRI_COUNT (32U)
43177
43178/*! @name CHNENBL - Channel Enable RAM */
43179/*! @{ */
43180#define SDMAARM_CHNENBL_ENBLn_MASK (0xFFFFFFFFU)
43181#define SDMAARM_CHNENBL_ENBLn_SHIFT (0U)
43182#define SDMAARM_CHNENBL_ENBLn(x) \
43183 (((uint32_t)(((uint32_t)(x)) << SDMAARM_CHNENBL_ENBLn_SHIFT)) & SDMAARM_CHNENBL_ENBLn_MASK)
43184/*! @} */
43185
43186/* The count of SDMAARM_CHNENBL */
43187#define SDMAARM_CHNENBL_COUNT (48U)
43188
43189/*! @name DONE0_CONFIG - SDMA DONE0 Configuration */
43190/*! @{ */
43191#define SDMAARM_DONE0_CONFIG_CH_SEL0_MASK (0x1FU)
43192#define SDMAARM_DONE0_CONFIG_CH_SEL0_SHIFT (0U)
43193#define SDMAARM_DONE0_CONFIG_CH_SEL0(x) \
43194 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_CH_SEL0_SHIFT)) & SDMAARM_DONE0_CONFIG_CH_SEL0_MASK)
43195#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS0_MASK (0x40U)
43196#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS0_SHIFT (6U)
43197/*! SW_DONE_DIS0
43198 * 0b0..Enable
43199 * 0b1..Disable
43200 */
43201#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS0(x) \
43202 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_SW_DONE_DIS0_SHIFT)) & SDMAARM_DONE0_CONFIG_SW_DONE_DIS0_MASK)
43203#define SDMAARM_DONE0_CONFIG_DONE_SEL0_MASK (0x80U)
43204#define SDMAARM_DONE0_CONFIG_DONE_SEL0_SHIFT (7U)
43205/*! DONE_SEL0
43206 * 0b0..HW
43207 * 0b1..SW
43208 */
43209#define SDMAARM_DONE0_CONFIG_DONE_SEL0(x) \
43210 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_DONE_SEL0_SHIFT)) & SDMAARM_DONE0_CONFIG_DONE_SEL0_MASK)
43211#define SDMAARM_DONE0_CONFIG_CH_SEL1_MASK (0x1F00U)
43212#define SDMAARM_DONE0_CONFIG_CH_SEL1_SHIFT (8U)
43213#define SDMAARM_DONE0_CONFIG_CH_SEL1(x) \
43214 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_CH_SEL1_SHIFT)) & SDMAARM_DONE0_CONFIG_CH_SEL1_MASK)
43215#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS1_MASK (0x4000U)
43216#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS1_SHIFT (14U)
43217/*! SW_DONE_DIS1
43218 * 0b0..Enable
43219 * 0b1..Disable
43220 */
43221#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS1(x) \
43222 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_SW_DONE_DIS1_SHIFT)) & SDMAARM_DONE0_CONFIG_SW_DONE_DIS1_MASK)
43223#define SDMAARM_DONE0_CONFIG_DONE_SEL1_MASK (0x8000U)
43224#define SDMAARM_DONE0_CONFIG_DONE_SEL1_SHIFT (15U)
43225/*! DONE_SEL1
43226 * 0b0..HW
43227 * 0b1..SW
43228 */
43229#define SDMAARM_DONE0_CONFIG_DONE_SEL1(x) \
43230 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_DONE_SEL1_SHIFT)) & SDMAARM_DONE0_CONFIG_DONE_SEL1_MASK)
43231#define SDMAARM_DONE0_CONFIG_CH_SEL2_MASK (0x1F0000U)
43232#define SDMAARM_DONE0_CONFIG_CH_SEL2_SHIFT (16U)
43233#define SDMAARM_DONE0_CONFIG_CH_SEL2(x) \
43234 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_CH_SEL2_SHIFT)) & SDMAARM_DONE0_CONFIG_CH_SEL2_MASK)
43235#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS2_MASK (0x400000U)
43236#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS2_SHIFT (22U)
43237/*! SW_DONE_DIS2
43238 * 0b0..Enable
43239 * 0b1..Disable
43240 */
43241#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS2(x) \
43242 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_SW_DONE_DIS2_SHIFT)) & SDMAARM_DONE0_CONFIG_SW_DONE_DIS2_MASK)
43243#define SDMAARM_DONE0_CONFIG_DONE_SEL2_MASK (0x800000U)
43244#define SDMAARM_DONE0_CONFIG_DONE_SEL2_SHIFT (23U)
43245/*! DONE_SEL2
43246 * 0b0..HW
43247 * 0b1..SW
43248 */
43249#define SDMAARM_DONE0_CONFIG_DONE_SEL2(x) \
43250 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_DONE_SEL2_SHIFT)) & SDMAARM_DONE0_CONFIG_DONE_SEL2_MASK)
43251#define SDMAARM_DONE0_CONFIG_CH_SEL3_MASK (0x1F000000U)
43252#define SDMAARM_DONE0_CONFIG_CH_SEL3_SHIFT (24U)
43253#define SDMAARM_DONE0_CONFIG_CH_SEL3(x) \
43254 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_CH_SEL3_SHIFT)) & SDMAARM_DONE0_CONFIG_CH_SEL3_MASK)
43255#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS3_MASK (0x40000000U)
43256#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS3_SHIFT (30U)
43257/*! SW_DONE_DIS3
43258 * 0b0..Enable
43259 * 0b1..Disable
43260 */
43261#define SDMAARM_DONE0_CONFIG_SW_DONE_DIS3(x) \
43262 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_SW_DONE_DIS3_SHIFT)) & SDMAARM_DONE0_CONFIG_SW_DONE_DIS3_MASK)
43263#define SDMAARM_DONE0_CONFIG_DONE_SEL3_MASK (0x80000000U)
43264#define SDMAARM_DONE0_CONFIG_DONE_SEL3_SHIFT (31U)
43265/*! DONE_SEL3
43266 * 0b0..HW
43267 * 0b1..SW
43268 */
43269#define SDMAARM_DONE0_CONFIG_DONE_SEL3(x) \
43270 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE0_CONFIG_DONE_SEL3_SHIFT)) & SDMAARM_DONE0_CONFIG_DONE_SEL3_MASK)
43271/*! @} */
43272
43273/*! @name DONE1_CONFIG - SDMA DONE1 Configuration */
43274/*! @{ */
43275#define SDMAARM_DONE1_CONFIG_CH_SEL4_MASK (0x1FU)
43276#define SDMAARM_DONE1_CONFIG_CH_SEL4_SHIFT (0U)
43277#define SDMAARM_DONE1_CONFIG_CH_SEL4(x) \
43278 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_CH_SEL4_SHIFT)) & SDMAARM_DONE1_CONFIG_CH_SEL4_MASK)
43279#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS4_MASK (0x40U)
43280#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS4_SHIFT (6U)
43281/*! SW_DONE_DIS4
43282 * 0b0..Enable
43283 * 0b1..Disable
43284 */
43285#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS4(x) \
43286 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_SW_DONE_DIS4_SHIFT)) & SDMAARM_DONE1_CONFIG_SW_DONE_DIS4_MASK)
43287#define SDMAARM_DONE1_CONFIG_DONE_SEL4_MASK (0x80U)
43288#define SDMAARM_DONE1_CONFIG_DONE_SEL4_SHIFT (7U)
43289/*! DONE_SEL4
43290 * 0b0..HW
43291 * 0b1..SW
43292 */
43293#define SDMAARM_DONE1_CONFIG_DONE_SEL4(x) \
43294 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_DONE_SEL4_SHIFT)) & SDMAARM_DONE1_CONFIG_DONE_SEL4_MASK)
43295#define SDMAARM_DONE1_CONFIG_CH_SEL5_MASK (0x1F00U)
43296#define SDMAARM_DONE1_CONFIG_CH_SEL5_SHIFT (8U)
43297#define SDMAARM_DONE1_CONFIG_CH_SEL5(x) \
43298 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_CH_SEL5_SHIFT)) & SDMAARM_DONE1_CONFIG_CH_SEL5_MASK)
43299#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS5_MASK (0x4000U)
43300#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS5_SHIFT (14U)
43301/*! SW_DONE_DIS5
43302 * 0b0..Enable
43303 * 0b1..Disable
43304 */
43305#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS5(x) \
43306 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_SW_DONE_DIS5_SHIFT)) & SDMAARM_DONE1_CONFIG_SW_DONE_DIS5_MASK)
43307#define SDMAARM_DONE1_CONFIG_DONE_SEL5_MASK (0x8000U)
43308#define SDMAARM_DONE1_CONFIG_DONE_SEL5_SHIFT (15U)
43309/*! DONE_SEL5
43310 * 0b0..HW
43311 * 0b1..SW
43312 */
43313#define SDMAARM_DONE1_CONFIG_DONE_SEL5(x) \
43314 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_DONE_SEL5_SHIFT)) & SDMAARM_DONE1_CONFIG_DONE_SEL5_MASK)
43315#define SDMAARM_DONE1_CONFIG_CH_SEL6_MASK (0x1F0000U)
43316#define SDMAARM_DONE1_CONFIG_CH_SEL6_SHIFT (16U)
43317#define SDMAARM_DONE1_CONFIG_CH_SEL6(x) \
43318 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_CH_SEL6_SHIFT)) & SDMAARM_DONE1_CONFIG_CH_SEL6_MASK)
43319#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS6_MASK (0x400000U)
43320#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS6_SHIFT (22U)
43321/*! SW_DONE_DIS6
43322 * 0b0..Enable
43323 * 0b1..Disable
43324 */
43325#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS6(x) \
43326 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_SW_DONE_DIS6_SHIFT)) & SDMAARM_DONE1_CONFIG_SW_DONE_DIS6_MASK)
43327#define SDMAARM_DONE1_CONFIG_DONE_SEL6_MASK (0x800000U)
43328#define SDMAARM_DONE1_CONFIG_DONE_SEL6_SHIFT (23U)
43329/*! DONE_SEL6
43330 * 0b0..HW
43331 * 0b1..SW
43332 */
43333#define SDMAARM_DONE1_CONFIG_DONE_SEL6(x) \
43334 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_DONE_SEL6_SHIFT)) & SDMAARM_DONE1_CONFIG_DONE_SEL6_MASK)
43335#define SDMAARM_DONE1_CONFIG_CH_SEL7_MASK (0x1F000000U)
43336#define SDMAARM_DONE1_CONFIG_CH_SEL7_SHIFT (24U)
43337#define SDMAARM_DONE1_CONFIG_CH_SEL7(x) \
43338 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_CH_SEL7_SHIFT)) & SDMAARM_DONE1_CONFIG_CH_SEL7_MASK)
43339#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS7_MASK (0x40000000U)
43340#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS7_SHIFT (30U)
43341/*! SW_DONE_DIS7
43342 * 0b0..Enable
43343 * 0b1..Disable
43344 */
43345#define SDMAARM_DONE1_CONFIG_SW_DONE_DIS7(x) \
43346 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_SW_DONE_DIS7_SHIFT)) & SDMAARM_DONE1_CONFIG_SW_DONE_DIS7_MASK)
43347#define SDMAARM_DONE1_CONFIG_DONE_SEL7_MASK (0x80000000U)
43348#define SDMAARM_DONE1_CONFIG_DONE_SEL7_SHIFT (31U)
43349/*! DONE_SEL7
43350 * 0b0..HW
43351 * 0b1..SW
43352 */
43353#define SDMAARM_DONE1_CONFIG_DONE_SEL7(x) \
43354 (((uint32_t)(((uint32_t)(x)) << SDMAARM_DONE1_CONFIG_DONE_SEL7_SHIFT)) & SDMAARM_DONE1_CONFIG_DONE_SEL7_MASK)
43355/*! @} */
43356
43357/*!
43358 * @}
43359 */ /* end of group SDMAARM_Register_Masks */
43360
43361/* SDMAARM - Peripheral instance base addresses */
43362/** Peripheral SDMAARM1 base address */
43363#define SDMAARM1_BASE (0x30BD0000u)
43364/** Peripheral SDMAARM1 base pointer */
43365#define SDMAARM1 ((SDMAARM_Type *)SDMAARM1_BASE)
43366/** Peripheral SDMAARM2 base address */
43367#define SDMAARM2_BASE (0x302C0000u)
43368/** Peripheral SDMAARM2 base pointer */
43369#define SDMAARM2 ((SDMAARM_Type *)SDMAARM2_BASE)
43370/** Peripheral SDMAARM3 base address */
43371#define SDMAARM3_BASE (0x302B0000u)
43372/** Peripheral SDMAARM3 base pointer */
43373#define SDMAARM3 ((SDMAARM_Type *)SDMAARM3_BASE)
43374/** Array initializer of SDMAARM peripheral base addresses */
43375#define SDMAARM_BASE_ADDRS \
43376 { \
43377 SDMAARM1_BASE, SDMAARM2_BASE, SDMAARM3_BASE \
43378 }
43379/** Array initializer of SDMAARM peripheral base pointers */
43380#define SDMAARM_BASE_PTRS \
43381 { \
43382 SDMAARM1, SDMAARM2, SDMAARM3 \
43383 }
43384/** Interrupt vectors for the SDMAARM peripheral type */
43385#define SDMAARM_IRQS \
43386 { \
43387 SDMA1_IRQn, SDMA2_IRQn, SDMA3_IRQn \
43388 }
43389
43390/*!
43391 * @}
43392 */ /* end of group SDMAARM_Peripheral_Access_Layer */
43393
43394/* ----------------------------------------------------------------------------
43395 -- SEMA4 Peripheral Access Layer
43396 ---------------------------------------------------------------------------- */
43397
43398/*!
43399 * @addtogroup SEMA4_Peripheral_Access_Layer SEMA4 Peripheral Access Layer
43400 * @{
43401 */
43402
43403/** SEMA4 - Register Layout Typedef */
43404typedef struct
43405{
43406 __IO uint8_t Gate00; /**< Semaphores Gate 0 Register, offset: 0x0 */
43407 __IO uint8_t Gate01; /**< Semaphores Gate 1 Register, offset: 0x1 */
43408 __IO uint8_t Gate02; /**< Semaphores Gate 2 Register, offset: 0x2 */
43409 __IO uint8_t Gate03; /**< Semaphores Gate 3 Register, offset: 0x3 */
43410 __IO uint8_t Gate04; /**< Semaphores Gate 4 Register, offset: 0x4 */
43411 __IO uint8_t Gate05; /**< Semaphores Gate 5 Register, offset: 0x5 */
43412 __IO uint8_t Gate06; /**< Semaphores Gate 6 Register, offset: 0x6 */
43413 __IO uint8_t Gate07; /**< Semaphores Gate 7 Register, offset: 0x7 */
43414 __IO uint8_t Gate08; /**< Semaphores Gate 8 Register, offset: 0x8 */
43415 __IO uint8_t Gate09; /**< Semaphores Gate 9 Register, offset: 0x9 */
43416 __IO uint8_t Gate10; /**< Semaphores Gate 10 Register, offset: 0xA */
43417 __IO uint8_t Gate11; /**< Semaphores Gate 11 Register, offset: 0xB */
43418 __IO uint8_t Gate12; /**< Semaphores Gate 12 Register, offset: 0xC */
43419 __IO uint8_t Gate13; /**< Semaphores Gate 13 Register, offset: 0xD */
43420 __IO uint8_t Gate14; /**< Semaphores Gate 14 Register, offset: 0xE */
43421 __IO uint8_t Gate15; /**< Semaphores Gate 15 Register, offset: 0xF */
43422 uint8_t RESERVED_0[48];
43423 struct
43424 { /* offset: 0x40, array step: 0x8 */
43425 __IO uint16_t CPINE; /**< Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8 */
43426 uint8_t RESERVED_0[6];
43427 } CPINE[2];
43428 uint8_t RESERVED_1[48];
43429 struct
43430 { /* offset: 0x80, array step: 0x8 */
43431 __I uint16_t CPNTF; /**< Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8 */
43432 uint8_t RESERVED_0[6];
43433 } CPNTF[2];
43434 uint8_t RESERVED_2[112];
43435 __IO uint16_t RSTGT; /**< Semaphores (Secure) Reset Gate n, offset: 0x100 */
43436 uint8_t RESERVED_3[2];
43437 __IO uint16_t RSTNTF; /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */
43438} SEMA4_Type;
43439
43440/* ----------------------------------------------------------------------------
43441 -- SEMA4 Register Masks
43442 ---------------------------------------------------------------------------- */
43443
43444/*!
43445 * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks
43446 * @{
43447 */
43448
43449/*! @name Gate00 - Semaphores Gate 0 Register */
43450/*! @{ */
43451#define SEMA4_Gate00_GTFSM_MASK (0x3U)
43452#define SEMA4_Gate00_GTFSM_SHIFT (0U)
43453/*! GTFSM - Gate Finite State Machine.
43454 * 0b00..The gate is unlocked (free).
43455 * 0b01..The gate has been locked by processor 0.
43456 * 0b10..The gate has been locked by processor 1.
43457 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
43458 * operation" and do not affect the gate state machine.
43459 */
43460#define SEMA4_Gate00_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate00_GTFSM_SHIFT)) & SEMA4_Gate00_GTFSM_MASK)
43461/*! @} */
43462
43463/*! @name Gate01 - Semaphores Gate 1 Register */
43464/*! @{ */
43465#define SEMA4_Gate01_GTFSM_MASK (0x3U)
43466#define SEMA4_Gate01_GTFSM_SHIFT (0U)
43467/*! GTFSM - Gate Finite State Machine.
43468 * 0b00..The gate is unlocked (free).
43469 * 0b01..The gate has been locked by processor 0.
43470 * 0b10..The gate has been locked by processor 1.
43471 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
43472 * operation" and do not affect the gate state machine.
43473 */
43474#define SEMA4_Gate01_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate01_GTFSM_SHIFT)) & SEMA4_Gate01_GTFSM_MASK)
43475/*! @} */
43476
43477/*! @name Gate02 - Semaphores Gate 2 Register */
43478/*! @{ */
43479#define SEMA4_Gate02_GTFSM_MASK (0x3U)
43480#define SEMA4_Gate02_GTFSM_SHIFT (0U)
43481/*! GTFSM - Gate Finite State Machine.
43482 * 0b00..The gate is unlocked (free).
43483 * 0b01..The gate has been locked by processor 0.
43484 * 0b10..The gate has been locked by processor 1.
43485 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
43486 * operation" and do not affect the gate state machine.
43487 */
43488#define SEMA4_Gate02_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate02_GTFSM_SHIFT)) & SEMA4_Gate02_GTFSM_MASK)
43489/*! @} */
43490
43491/*! @name Gate03 - Semaphores Gate 3 Register */
43492/*! @{ */
43493#define SEMA4_Gate03_GTFSM_MASK (0x3U)
43494#define SEMA4_Gate03_GTFSM_SHIFT (0U)
43495/*! GTFSM - Gate Finite State Machine.
43496 * 0b00..The gate is unlocked (free).
43497 * 0b01..The gate has been locked by processor 0.
43498 * 0b10..The gate has been locked by processor 1.
43499 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
43500 * operation" and do not affect the gate state machine.
43501 */
43502#define SEMA4_Gate03_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate03_GTFSM_SHIFT)) & SEMA4_Gate03_GTFSM_MASK)
43503/*! @} */
43504
43505/*! @name Gate04 - Semaphores Gate 4 Register */
43506/*! @{ */
43507#define SEMA4_Gate04_GTFSM_MASK (0x3U)
43508#define SEMA4_Gate04_GTFSM_SHIFT (0U)
43509/*! GTFSM - Gate Finite State Machine.
43510 * 0b00..The gate is unlocked (free).
43511 * 0b01..The gate has been locked by processor 0.
43512 * 0b10..The gate has been locked by processor 1.
43513 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
43514 * operation" and do not affect the gate state machine.
43515 */
43516#define SEMA4_Gate04_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate04_GTFSM_SHIFT)) & SEMA4_Gate04_GTFSM_MASK)
43517/*! @} */
43518
43519/*! @name Gate05 - Semaphores Gate 5 Register */
43520/*! @{ */
43521#define SEMA4_Gate05_GTFSM_MASK (0x3U)
43522#define SEMA4_Gate05_GTFSM_SHIFT (0U)
43523/*! GTFSM - Gate Finite State Machine.
43524 * 0b00..The gate is unlocked (free).
43525 * 0b01..The gate has been locked by processor 0.
43526 * 0b10..The gate has been locked by processor 1.
43527 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
43528 * operation" and do not affect the gate state machine.
43529 */
43530#define SEMA4_Gate05_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate05_GTFSM_SHIFT)) & SEMA4_Gate05_GTFSM_MASK)
43531/*! @} */
43532
43533/*! @name Gate06 - Semaphores Gate 6 Register */
43534/*! @{ */
43535#define SEMA4_Gate06_GTFSM_MASK (0x3U)
43536#define SEMA4_Gate06_GTFSM_SHIFT (0U)
43537/*! GTFSM - Gate Finite State Machine.
43538 * 0b00..The gate is unlocked (free).
43539 * 0b01..The gate has been locked by processor 0.
43540 * 0b10..The gate has been locked by processor 1.
43541 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
43542 * operation" and do not affect the gate state machine.
43543 */
43544#define SEMA4_Gate06_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate06_GTFSM_SHIFT)) & SEMA4_Gate06_GTFSM_MASK)
43545/*! @} */
43546
43547/*! @name Gate07 - Semaphores Gate 7 Register */
43548/*! @{ */
43549#define SEMA4_Gate07_GTFSM_MASK (0x3U)
43550#define SEMA4_Gate07_GTFSM_SHIFT (0U)
43551/*! GTFSM - Gate Finite State Machine.
43552 * 0b00..The gate is unlocked (free).
43553 * 0b01..The gate has been locked by processor 0.
43554 * 0b10..The gate has been locked by processor 1.
43555 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
43556 * operation" and do not affect the gate state machine.
43557 */
43558#define SEMA4_Gate07_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate07_GTFSM_SHIFT)) & SEMA4_Gate07_GTFSM_MASK)
43559/*! @} */
43560
43561/*! @name Gate08 - Semaphores Gate 8 Register */
43562/*! @{ */
43563#define SEMA4_Gate08_GTFSM_MASK (0x3U)
43564#define SEMA4_Gate08_GTFSM_SHIFT (0U)
43565/*! GTFSM - Gate Finite State Machine.
43566 * 0b00..The gate is unlocked (free).
43567 * 0b01..The gate has been locked by processor 0.
43568 * 0b10..The gate has been locked by processor 1.
43569 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
43570 * operation" and do not affect the gate state machine.
43571 */
43572#define SEMA4_Gate08_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate08_GTFSM_SHIFT)) & SEMA4_Gate08_GTFSM_MASK)
43573/*! @} */
43574
43575/*! @name Gate09 - Semaphores Gate 9 Register */
43576/*! @{ */
43577#define SEMA4_Gate09_GTFSM_MASK (0x3U)
43578#define SEMA4_Gate09_GTFSM_SHIFT (0U)
43579/*! GTFSM - Gate Finite State Machine.
43580 * 0b00..The gate is unlocked (free).
43581 * 0b01..The gate has been locked by processor 0.
43582 * 0b10..The gate has been locked by processor 1.
43583 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
43584 * operation" and do not affect the gate state machine.
43585 */
43586#define SEMA4_Gate09_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate09_GTFSM_SHIFT)) & SEMA4_Gate09_GTFSM_MASK)
43587/*! @} */
43588
43589/*! @name Gate10 - Semaphores Gate 10 Register */
43590/*! @{ */
43591#define SEMA4_Gate10_GTFSM_MASK (0x3U)
43592#define SEMA4_Gate10_GTFSM_SHIFT (0U)
43593/*! GTFSM - Gate Finite State Machine.
43594 * 0b00..The gate is unlocked (free).
43595 * 0b01..The gate has been locked by processor 0.
43596 * 0b10..The gate has been locked by processor 1.
43597 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
43598 * operation" and do not affect the gate state machine.
43599 */
43600#define SEMA4_Gate10_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate10_GTFSM_SHIFT)) & SEMA4_Gate10_GTFSM_MASK)
43601/*! @} */
43602
43603/*! @name Gate11 - Semaphores Gate 11 Register */
43604/*! @{ */
43605#define SEMA4_Gate11_GTFSM_MASK (0x3U)
43606#define SEMA4_Gate11_GTFSM_SHIFT (0U)
43607/*! GTFSM - Gate Finite State Machine.
43608 * 0b00..The gate is unlocked (free).
43609 * 0b01..The gate has been locked by processor 0.
43610 * 0b10..The gate has been locked by processor 1.
43611 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
43612 * operation" and do not affect the gate state machine.
43613 */
43614#define SEMA4_Gate11_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate11_GTFSM_SHIFT)) & SEMA4_Gate11_GTFSM_MASK)
43615/*! @} */
43616
43617/*! @name Gate12 - Semaphores Gate 12 Register */
43618/*! @{ */
43619#define SEMA4_Gate12_GTFSM_MASK (0x3U)
43620#define SEMA4_Gate12_GTFSM_SHIFT (0U)
43621/*! GTFSM - Gate Finite State Machine.
43622 * 0b00..The gate is unlocked (free).
43623 * 0b01..The gate has been locked by processor 0.
43624 * 0b10..The gate has been locked by processor 1.
43625 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
43626 * operation" and do not affect the gate state machine.
43627 */
43628#define SEMA4_Gate12_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate12_GTFSM_SHIFT)) & SEMA4_Gate12_GTFSM_MASK)
43629/*! @} */
43630
43631/*! @name Gate13 - Semaphores Gate 13 Register */
43632/*! @{ */
43633#define SEMA4_Gate13_GTFSM_MASK (0x3U)
43634#define SEMA4_Gate13_GTFSM_SHIFT (0U)
43635/*! GTFSM - Gate Finite State Machine.
43636 * 0b00..The gate is unlocked (free).
43637 * 0b01..The gate has been locked by processor 0.
43638 * 0b10..The gate has been locked by processor 1.
43639 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
43640 * operation" and do not affect the gate state machine.
43641 */
43642#define SEMA4_Gate13_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate13_GTFSM_SHIFT)) & SEMA4_Gate13_GTFSM_MASK)
43643/*! @} */
43644
43645/*! @name Gate14 - Semaphores Gate 14 Register */
43646/*! @{ */
43647#define SEMA4_Gate14_GTFSM_MASK (0x3U)
43648#define SEMA4_Gate14_GTFSM_SHIFT (0U)
43649/*! GTFSM - Gate Finite State Machine.
43650 * 0b00..The gate is unlocked (free).
43651 * 0b01..The gate has been locked by processor 0.
43652 * 0b10..The gate has been locked by processor 1.
43653 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
43654 * operation" and do not affect the gate state machine.
43655 */
43656#define SEMA4_Gate14_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate14_GTFSM_SHIFT)) & SEMA4_Gate14_GTFSM_MASK)
43657/*! @} */
43658
43659/*! @name Gate15 - Semaphores Gate 15 Register */
43660/*! @{ */
43661#define SEMA4_Gate15_GTFSM_MASK (0x3U)
43662#define SEMA4_Gate15_GTFSM_SHIFT (0U)
43663/*! GTFSM - Gate Finite State Machine.
43664 * 0b00..The gate is unlocked (free).
43665 * 0b01..The gate has been locked by processor 0.
43666 * 0b10..The gate has been locked by processor 1.
43667 * 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
43668 * operation" and do not affect the gate state machine.
43669 */
43670#define SEMA4_Gate15_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_Gate15_GTFSM_SHIFT)) & SEMA4_Gate15_GTFSM_MASK)
43671/*! @} */
43672
43673/*! @name CPINE - Semaphores Processor n IRQ Notification Enable */
43674/*! @{ */
43675#define SEMA4_CPINE_INE7_MASK (0x1U)
43676#define SEMA4_CPINE_INE7_SHIFT (0U)
43677/*! INE7 - Interrupt Request Notification Enable 7. This field is a bitmap to enable the generation
43678 * of an interrupt notification from a failed attempt to lock gate 7.
43679 * 0b0..The generation of the notification interrupt is disabled.
43680 * 0b1..The generation of the notification interrupt is enabled.
43681 */
43682#define SEMA4_CPINE_INE7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE7_SHIFT)) & SEMA4_CPINE_INE7_MASK)
43683#define SEMA4_CPINE_INE6_MASK (0x2U)
43684#define SEMA4_CPINE_INE6_SHIFT (1U)
43685/*! INE6 - Interrupt Request Notification Enable 6. This field is a bitmap to enable the generation
43686 * of an interrupt notification from a failed attempt to lock gate 6.
43687 * 0b0..The generation of the notification interrupt is disabled.
43688 * 0b1..The generation of the notification interrupt is enabled.
43689 */
43690#define SEMA4_CPINE_INE6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE6_SHIFT)) & SEMA4_CPINE_INE6_MASK)
43691#define SEMA4_CPINE_INE5_MASK (0x4U)
43692#define SEMA4_CPINE_INE5_SHIFT (2U)
43693/*! INE5 - Interrupt Request Notification Enable 5. This field is a bitmap to enable the generation
43694 * of an interrupt notification from a failed attempt to lock gate 5.
43695 * 0b0..The generation of the notification interrupt is disabled.
43696 * 0b1..The generation of the notification interrupt is enabled.
43697 */
43698#define SEMA4_CPINE_INE5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE5_SHIFT)) & SEMA4_CPINE_INE5_MASK)
43699#define SEMA4_CPINE_INE4_MASK (0x8U)
43700#define SEMA4_CPINE_INE4_SHIFT (3U)
43701/*! INE4 - Interrupt Request Notification Enable 4. This field is a bitmap to enable the generation
43702 * of an interrupt notification from a failed attempt to lock gate 4.
43703 * 0b0..The generation of the notification interrupt is disabled.
43704 * 0b1..The generation of the notification interrupt is enabled.
43705 */
43706#define SEMA4_CPINE_INE4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE4_SHIFT)) & SEMA4_CPINE_INE4_MASK)
43707#define SEMA4_CPINE_INE3_MASK (0x10U)
43708#define SEMA4_CPINE_INE3_SHIFT (4U)
43709/*! INE3
43710 * 0b0..The generation of the notification interrupt is disabled.
43711 * 0b1..The generation of the notification interrupt is enabled.
43712 */
43713#define SEMA4_CPINE_INE3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE3_SHIFT)) & SEMA4_CPINE_INE3_MASK)
43714#define SEMA4_CPINE_INE2_MASK (0x20U)
43715#define SEMA4_CPINE_INE2_SHIFT (5U)
43716/*! INE2
43717 * 0b0..The generation of the notification interrupt is disabled.
43718 * 0b1..The generation of the notification interrupt is enabled.
43719 */
43720#define SEMA4_CPINE_INE2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE2_SHIFT)) & SEMA4_CPINE_INE2_MASK)
43721#define SEMA4_CPINE_INE1_MASK (0x40U)
43722#define SEMA4_CPINE_INE1_SHIFT (6U)
43723/*! INE1
43724 * 0b0..The generation of the notification interrupt is disabled.
43725 * 0b1..The generation of the notification interrupt is enabled.
43726 */
43727#define SEMA4_CPINE_INE1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE1_SHIFT)) & SEMA4_CPINE_INE1_MASK)
43728#define SEMA4_CPINE_INE0_MASK (0x80U)
43729#define SEMA4_CPINE_INE0_SHIFT (7U)
43730/*! INE0
43731 * 0b0..The generation of the notification interrupt is disabled.
43732 * 0b1..The generation of the notification interrupt is enabled.
43733 */
43734#define SEMA4_CPINE_INE0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE0_SHIFT)) & SEMA4_CPINE_INE0_MASK)
43735#define SEMA4_CPINE_INE15_MASK (0x100U)
43736#define SEMA4_CPINE_INE15_SHIFT (8U)
43737/*! INE15 - Interrupt Request Notification Enable 15. This field is a bitmap to enable the
43738 * generation of an interrupt notification from a failed attempt to lock gate 15.
43739 * 0b0..The generation of the notification interrupt is disabled.
43740 * 0b1..The generation of the notification interrupt is enabled.
43741 */
43742#define SEMA4_CPINE_INE15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE15_SHIFT)) & SEMA4_CPINE_INE15_MASK)
43743#define SEMA4_CPINE_INE14_MASK (0x200U)
43744#define SEMA4_CPINE_INE14_SHIFT (9U)
43745/*! INE14 - Interrupt Request Notification Enable 14. This field is a bitmap to enable the
43746 * generation of an interrupt notification from a failed attempt to lock gate 14.
43747 * 0b0..The generation of the notification interrupt is disabled.
43748 * 0b1..The generation of the notification interrupt is enabled.
43749 */
43750#define SEMA4_CPINE_INE14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE14_SHIFT)) & SEMA4_CPINE_INE14_MASK)
43751#define SEMA4_CPINE_INE13_MASK (0x400U)
43752#define SEMA4_CPINE_INE13_SHIFT (10U)
43753/*! INE13 - Interrupt Request Notification Enable 13. This field is a bitmap to enable the
43754 * generation of an interrupt notification from a failed attempt to lock gate 13.
43755 * 0b0..The generation of the notification interrupt is disabled.
43756 * 0b1..The generation of the notification interrupt is enabled.
43757 */
43758#define SEMA4_CPINE_INE13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE13_SHIFT)) & SEMA4_CPINE_INE13_MASK)
43759#define SEMA4_CPINE_INE12_MASK (0x800U)
43760#define SEMA4_CPINE_INE12_SHIFT (11U)
43761/*! INE12 - Interrupt Request Notification Enable 12. This field is a bitmap to enable the
43762 * generation of an interrupt notification from a failed attempt to lock gate 12.
43763 * 0b0..The generation of the notification interrupt is disabled.
43764 * 0b1..The generation of the notification interrupt is enabled.
43765 */
43766#define SEMA4_CPINE_INE12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE12_SHIFT)) & SEMA4_CPINE_INE12_MASK)
43767#define SEMA4_CPINE_INE11_MASK (0x1000U)
43768#define SEMA4_CPINE_INE11_SHIFT (12U)
43769/*! INE11 - Interrupt Request Notification Enable 11. This field is a bitmap to enable the
43770 * generation of an interrupt notification from a failed attempt to lock gate 11.
43771 * 0b0..The generation of the notification interrupt is disabled.
43772 * 0b1..The generation of the notification interrupt is enabled.
43773 */
43774#define SEMA4_CPINE_INE11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE11_SHIFT)) & SEMA4_CPINE_INE11_MASK)
43775#define SEMA4_CPINE_INE10_MASK (0x2000U)
43776#define SEMA4_CPINE_INE10_SHIFT (13U)
43777/*! INE10 - Interrupt Request Notification Enable 10. This field is a bitmap to enable the
43778 * generation of an interrupt notification from a failed attempt to lock gate 10.
43779 * 0b0..The generation of the notification interrupt is disabled.
43780 * 0b1..The generation of the notification interrupt is enabled.
43781 */
43782#define SEMA4_CPINE_INE10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE10_SHIFT)) & SEMA4_CPINE_INE10_MASK)
43783#define SEMA4_CPINE_INE9_MASK (0x4000U)
43784#define SEMA4_CPINE_INE9_SHIFT (14U)
43785/*! INE9 - Interrupt Request Notification Enable 9. This field is a bitmap to enable the generation
43786 * of an interrupt notification from a failed attempt to lock gate 9.
43787 * 0b0..The generation of the notification interrupt is disabled.
43788 * 0b1..The generation of the notification interrupt is enabled.
43789 */
43790#define SEMA4_CPINE_INE9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE9_SHIFT)) & SEMA4_CPINE_INE9_MASK)
43791#define SEMA4_CPINE_INE8_MASK (0x8000U)
43792#define SEMA4_CPINE_INE8_SHIFT (15U)
43793/*! INE8 - Interrupt Request Notification Enable 8. This field is a bitmap to enable the generation
43794 * of an interrupt notification from a failed attempt to lock gate 8.
43795 * 0b0..The generation of the notification interrupt is disabled.
43796 * 0b1..The generation of the notification interrupt is enabled.
43797 */
43798#define SEMA4_CPINE_INE8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE8_SHIFT)) & SEMA4_CPINE_INE8_MASK)
43799/*! @} */
43800
43801/* The count of SEMA4_CPINE */
43802#define SEMA4_CPINE_COUNT (2U)
43803
43804/*! @name CPNTF - Semaphores Processor n IRQ Notification */
43805/*! @{ */
43806#define SEMA4_CPNTF_GN7_MASK (0x1U)
43807#define SEMA4_CPNTF_GN7_SHIFT (0U)
43808#define SEMA4_CPNTF_GN7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN7_SHIFT)) & SEMA4_CPNTF_GN7_MASK)
43809#define SEMA4_CPNTF_GN6_MASK (0x2U)
43810#define SEMA4_CPNTF_GN6_SHIFT (1U)
43811#define SEMA4_CPNTF_GN6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN6_SHIFT)) & SEMA4_CPNTF_GN6_MASK)
43812#define SEMA4_CPNTF_GN5_MASK (0x4U)
43813#define SEMA4_CPNTF_GN5_SHIFT (2U)
43814#define SEMA4_CPNTF_GN5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN5_SHIFT)) & SEMA4_CPNTF_GN5_MASK)
43815#define SEMA4_CPNTF_GN4_MASK (0x8U)
43816#define SEMA4_CPNTF_GN4_SHIFT (3U)
43817#define SEMA4_CPNTF_GN4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN4_SHIFT)) & SEMA4_CPNTF_GN4_MASK)
43818#define SEMA4_CPNTF_GN3_MASK (0x10U)
43819#define SEMA4_CPNTF_GN3_SHIFT (4U)
43820#define SEMA4_CPNTF_GN3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN3_SHIFT)) & SEMA4_CPNTF_GN3_MASK)
43821#define SEMA4_CPNTF_GN2_MASK (0x20U)
43822#define SEMA4_CPNTF_GN2_SHIFT (5U)
43823#define SEMA4_CPNTF_GN2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN2_SHIFT)) & SEMA4_CPNTF_GN2_MASK)
43824#define SEMA4_CPNTF_GN1_MASK (0x40U)
43825#define SEMA4_CPNTF_GN1_SHIFT (6U)
43826#define SEMA4_CPNTF_GN1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN1_SHIFT)) & SEMA4_CPNTF_GN1_MASK)
43827#define SEMA4_CPNTF_GN0_MASK (0x80U)
43828#define SEMA4_CPNTF_GN0_SHIFT (7U)
43829#define SEMA4_CPNTF_GN0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN0_SHIFT)) & SEMA4_CPNTF_GN0_MASK)
43830#define SEMA4_CPNTF_GN15_MASK (0x100U)
43831#define SEMA4_CPNTF_GN15_SHIFT (8U)
43832#define SEMA4_CPNTF_GN15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN15_SHIFT)) & SEMA4_CPNTF_GN15_MASK)
43833#define SEMA4_CPNTF_GN14_MASK (0x200U)
43834#define SEMA4_CPNTF_GN14_SHIFT (9U)
43835#define SEMA4_CPNTF_GN14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN14_SHIFT)) & SEMA4_CPNTF_GN14_MASK)
43836#define SEMA4_CPNTF_GN13_MASK (0x400U)
43837#define SEMA4_CPNTF_GN13_SHIFT (10U)
43838#define SEMA4_CPNTF_GN13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN13_SHIFT)) & SEMA4_CPNTF_GN13_MASK)
43839#define SEMA4_CPNTF_GN12_MASK (0x800U)
43840#define SEMA4_CPNTF_GN12_SHIFT (11U)
43841#define SEMA4_CPNTF_GN12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN12_SHIFT)) & SEMA4_CPNTF_GN12_MASK)
43842#define SEMA4_CPNTF_GN11_MASK (0x1000U)
43843#define SEMA4_CPNTF_GN11_SHIFT (12U)
43844#define SEMA4_CPNTF_GN11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN11_SHIFT)) & SEMA4_CPNTF_GN11_MASK)
43845#define SEMA4_CPNTF_GN10_MASK (0x2000U)
43846#define SEMA4_CPNTF_GN10_SHIFT (13U)
43847#define SEMA4_CPNTF_GN10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN10_SHIFT)) & SEMA4_CPNTF_GN10_MASK)
43848#define SEMA4_CPNTF_GN9_MASK (0x4000U)
43849#define SEMA4_CPNTF_GN9_SHIFT (14U)
43850#define SEMA4_CPNTF_GN9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN9_SHIFT)) & SEMA4_CPNTF_GN9_MASK)
43851#define SEMA4_CPNTF_GN8_MASK (0x8000U)
43852#define SEMA4_CPNTF_GN8_SHIFT (15U)
43853#define SEMA4_CPNTF_GN8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN8_SHIFT)) & SEMA4_CPNTF_GN8_MASK)
43854/*! @} */
43855
43856/* The count of SEMA4_CPNTF */
43857#define SEMA4_CPNTF_COUNT (2U)
43858
43859/*! @name RSTGT - Semaphores (Secure) Reset Gate n */
43860/*! @{ */
43861#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK (0xFFU)
43862#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT (0U)
43863#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x) \
43864 (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT)) & SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK)
43865#define SEMA4_RSTGT_RSTGTN_MASK (0xFF00U)
43866#define SEMA4_RSTGT_RSTGTN_SHIFT (8U)
43867#define SEMA4_RSTGT_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGTN_SHIFT)) & SEMA4_RSTGT_RSTGTN_MASK)
43868/*! @} */
43869
43870/*! @name RSTNTF - Semaphores (Secure) Reset IRQ Notification */
43871/*! @{ */
43872#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK (0xFFU)
43873#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT (0U)
43874#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x) \
43875 (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT)) & SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK)
43876#define SEMA4_RSTNTF_RSTNTN_MASK (0xFF00U)
43877#define SEMA4_RSTNTF_RSTNTN_SHIFT (8U)
43878#define SEMA4_RSTNTF_RSTNTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNTN_SHIFT)) & SEMA4_RSTNTF_RSTNTN_MASK)
43879/*! @} */
43880
43881/*!
43882 * @}
43883 */ /* end of group SEMA4_Register_Masks */
43884
43885/* SEMA4 - Peripheral instance base addresses */
43886/** Peripheral SEMA4 base address */
43887#define SEMA4_BASE (0x30AC0000u)
43888/** Peripheral SEMA4 base pointer */
43889#define SEMA4 ((SEMA4_Type *)SEMA4_BASE)
43890/** Array initializer of SEMA4 peripheral base addresses */
43891#define SEMA4_BASE_ADDRS \
43892 { \
43893 SEMA4_BASE \
43894 }
43895/** Array initializer of SEMA4 peripheral base pointers */
43896#define SEMA4_BASE_PTRS \
43897 { \
43898 SEMA4 \
43899 }
43900
43901/*!
43902 * @}
43903 */ /* end of group SEMA4_Peripheral_Access_Layer */
43904
43905/* ----------------------------------------------------------------------------
43906 -- SNVS Peripheral Access Layer
43907 ---------------------------------------------------------------------------- */
43908
43909/*!
43910 * @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer
43911 * @{
43912 */
43913
43914/** SNVS - Register Layout Typedef */
43915typedef struct
43916{
43917 uint8_t RESERVED_0[4];
43918 __IO uint32_t HPCOMR; /**< SNVS_HP Command Register, offset: 0x4 */
43919 __IO uint32_t HPCR; /**< SNVS_HP Control Register, offset: 0x8 */
43920 uint8_t RESERVED_1[8];
43921 __IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */
43922 uint8_t RESERVED_2[12];
43923 __IO uint32_t HPRTCMR; /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */
43924 __IO uint32_t HPRTCLR; /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */
43925 __IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */
43926 __IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */
43927 __IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */
43928 __IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */
43929 uint8_t RESERVED_3[16];
43930 __IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */
43931 uint8_t RESERVED_4[12];
43932 __IO uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */
43933 __IO uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */
43934 __IO uint32_t LPPGDR; /**< SNVS_LP Power Glitch Detector Register, offset: 0x64 */
43935 __IO uint32_t LPGPR0_LEGACY_ALIAS; /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */
43936 uint8_t RESERVED_5[36];
43937 __IO uint32_t LPGPR_ALIAS[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */
43938 uint8_t RESERVED_6[96];
43939 __IO uint32_t LPGPR[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x100, array step: 0x4 */
43940 uint8_t RESERVED_7[2792];
43941 __I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */
43942 __I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */
43943} SNVS_Type;
43944
43945/* ----------------------------------------------------------------------------
43946 -- SNVS Register Masks
43947 ---------------------------------------------------------------------------- */
43948
43949/*!
43950 * @addtogroup SNVS_Register_Masks SNVS Register Masks
43951 * @{
43952 */
43953
43954/*! @name HPCOMR - SNVS_HP Command Register */
43955/*! @{ */
43956#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U)
43957#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U)
43958#define SNVS_HPCOMR_NPSWA_EN(x) \
43959 (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
43960/*! @} */
43961
43962/*! @name HPCR - SNVS_HP Control Register */
43963/*! @{ */
43964#define SNVS_HPCR_RTC_EN_MASK (0x1U)
43965#define SNVS_HPCR_RTC_EN_SHIFT (0U)
43966/*! RTC_EN
43967 * 0b0..RTC is disabled
43968 * 0b1..RTC is enabled
43969 */
43970#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
43971#define SNVS_HPCR_HPTA_EN_MASK (0x2U)
43972#define SNVS_HPCR_HPTA_EN_SHIFT (1U)
43973/*! HPTA_EN
43974 * 0b0..HP Time Alarm Interrupt is disabled
43975 * 0b1..HP Time Alarm Interrupt is enabled
43976 */
43977#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
43978#define SNVS_HPCR_HPCALB_EN_MASK (0x100U)
43979#define SNVS_HPCR_HPCALB_EN_SHIFT (8U)
43980/*! HPCALB_EN
43981 * 0b0..HP Timer calibration disabled
43982 * 0b1..HP Timer calibration enabled
43983 */
43984#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
43985#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U)
43986#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U)
43987/*! HPCALB_VAL
43988 * 0b00000..+0 counts per each 32768 ticks of the counter
43989 * 0b00001..+1 counts per each 32768 ticks of the counter
43990 * 0b00010..+2 counts per each 32768 ticks of the counter
43991 * 0b01111..+15 counts per each 32768 ticks of the counter
43992 * 0b10000..-16 counts per each 32768 ticks of the counter
43993 * 0b10001..-15 counts per each 32768 ticks of the counter
43994 * 0b11110..-2 counts per each 32768 ticks of the counter
43995 * 0b11111..-1 counts per each 32768 ticks of the counter
43996 */
43997#define SNVS_HPCR_HPCALB_VAL(x) \
43998 (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
43999/*! @} */
44000
44001/*! @name HPSR - SNVS_HP Status Register */
44002/*! @{ */
44003#define SNVS_HPSR_HPTA_MASK (0x1U)
44004#define SNVS_HPSR_HPTA_SHIFT (0U)
44005/*! HPTA
44006 * 0b0..No time alarm interrupt occurred.
44007 * 0b1..A time alarm interrupt occurred.
44008 */
44009#define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
44010#define SNVS_HPSR_LPDIS_MASK (0x10U)
44011#define SNVS_HPSR_LPDIS_SHIFT (4U)
44012#define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
44013/*! @} */
44014
44015/*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */
44016/*! @{ */
44017#define SNVS_HPRTCMR_RTC_MASK (0x7FFFU)
44018#define SNVS_HPRTCMR_RTC_SHIFT (0U)
44019#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
44020/*! @} */
44021
44022/*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */
44023/*! @{ */
44024#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU)
44025#define SNVS_HPRTCLR_RTC_SHIFT (0U)
44026#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
44027/*! @} */
44028
44029/*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */
44030/*! @{ */
44031#define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU)
44032#define SNVS_HPTAMR_HPTA_MS_SHIFT (0U)
44033#define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
44034/*! @} */
44035
44036/*! @name HPTALR - SNVS_HP Time Alarm LSB Register */
44037/*! @{ */
44038#define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU)
44039#define SNVS_HPTALR_HPTA_LS_SHIFT (0U)
44040#define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
44041/*! @} */
44042
44043/*! @name LPLR - SNVS_LP Lock Register */
44044/*! @{ */
44045#define SNVS_LPLR_MC_HL_MASK (0x10U)
44046#define SNVS_LPLR_MC_HL_SHIFT (4U)
44047/*! MC_HL
44048 * 0b0..Write access (increment) is allowed.
44049 * 0b1..Write access (increment) is not allowed.
44050 */
44051#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
44052#define SNVS_LPLR_GPR_HL_MASK (0x20U)
44053#define SNVS_LPLR_GPR_HL_SHIFT (5U)
44054/*! GPR_HL
44055 * 0b0..Write access is allowed.
44056 * 0b1..Write access is not allowed.
44057 */
44058#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
44059/*! @} */
44060
44061/*! @name LPCR - SNVS_LP Control Register */
44062/*! @{ */
44063#define SNVS_LPCR_MC_ENV_MASK (0x4U)
44064#define SNVS_LPCR_MC_ENV_SHIFT (2U)
44065/*! MC_ENV
44066 * 0b0..MC is disabled or invalid.
44067 * 0b1..MC is enabled and valid.
44068 */
44069#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
44070/*! @} */
44071
44072/*! @name LPSR - SNVS_LP Status Register */
44073/*! @{ */
44074#define SNVS_LPSR_MCR_MASK (0x4U)
44075#define SNVS_LPSR_MCR_SHIFT (2U)
44076/*! MCR
44077 * 0b0..MC has not reached its maximum value.
44078 * 0b1..MC has reached its maximum value.
44079 */
44080#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
44081/*! @} */
44082
44083/*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */
44084/*! @{ */
44085#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU)
44086#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U)
44087#define SNVS_LPSMCMR_MON_COUNTER(x) \
44088 (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
44089#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U)
44090#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U)
44091#define SNVS_LPSMCMR_MC_ERA_BITS(x) \
44092 (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
44093/*! @} */
44094
44095/*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */
44096/*! @{ */
44097#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU)
44098#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U)
44099#define SNVS_LPSMCLR_MON_COUNTER(x) \
44100 (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
44101/*! @} */
44102
44103/*! @name LPPGDR - SNVS_LP Power Glitch Detector Register */
44104/*! @{ */
44105#define SNVS_LPPGDR_PGD_MASK (0xFFFFFFFFU)
44106#define SNVS_LPPGDR_PGD_SHIFT (0U)
44107#define SNVS_LPPGDR_PGD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPPGDR_PGD_SHIFT)) & SNVS_LPPGDR_PGD_MASK)
44108/*! @} */
44109
44110/*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */
44111/*! @{ */
44112#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU)
44113#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U)
44114#define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) \
44115 (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
44116/*! @} */
44117
44118/*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */
44119/*! @{ */
44120#define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU)
44121#define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U)
44122#define SNVS_LPGPR_ALIAS_GPR(x) \
44123 (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
44124/*! @} */
44125
44126/* The count of SNVS_LPGPR_ALIAS */
44127#define SNVS_LPGPR_ALIAS_COUNT (4U)
44128
44129/*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 3 */
44130/*! @{ */
44131#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU)
44132#define SNVS_LPGPR_GPR_SHIFT (0U)
44133#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
44134/*! @} */
44135
44136/* The count of SNVS_LPGPR */
44137#define SNVS_LPGPR_COUNT (4U)
44138
44139/*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */
44140/*! @{ */
44141#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU)
44142#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U)
44143#define SNVS_HPVIDR1_MINOR_REV(x) \
44144 (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
44145#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U)
44146#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U)
44147#define SNVS_HPVIDR1_MAJOR_REV(x) \
44148 (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
44149#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U)
44150#define SNVS_HPVIDR1_IP_ID_SHIFT (16U)
44151#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
44152/*! @} */
44153
44154/*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */
44155/*! @{ */
44156#define SNVS_HPVIDR2_CONFIG_OPT_MASK (0xFFU)
44157#define SNVS_HPVIDR2_CONFIG_OPT_SHIFT (0U)
44158#define SNVS_HPVIDR2_CONFIG_OPT(x) \
44159 (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_CONFIG_OPT_SHIFT)) & SNVS_HPVIDR2_CONFIG_OPT_MASK)
44160#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U)
44161#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U)
44162#define SNVS_HPVIDR2_ECO_REV(x) \
44163 (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
44164#define SNVS_HPVIDR2_INTG_OPT_MASK (0xFF0000U)
44165#define SNVS_HPVIDR2_INTG_OPT_SHIFT (16U)
44166#define SNVS_HPVIDR2_INTG_OPT(x) \
44167 (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_INTG_OPT_SHIFT)) & SNVS_HPVIDR2_INTG_OPT_MASK)
44168#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U)
44169#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U)
44170#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)
44171/*! @} */
44172
44173/*!
44174 * @}
44175 */ /* end of group SNVS_Register_Masks */
44176
44177/* SNVS - Peripheral instance base addresses */
44178/** Peripheral SNVS base address */
44179#define SNVS_BASE (0x30370000u)
44180/** Peripheral SNVS base pointer */
44181#define SNVS ((SNVS_Type *)SNVS_BASE)
44182/** Array initializer of SNVS peripheral base addresses */
44183#define SNVS_BASE_ADDRS \
44184 { \
44185 SNVS_BASE \
44186 }
44187/** Array initializer of SNVS peripheral base pointers */
44188#define SNVS_BASE_PTRS \
44189 { \
44190 SNVS \
44191 }
44192
44193/*!
44194 * @}
44195 */ /* end of group SNVS_Peripheral_Access_Layer */
44196
44197/* ----------------------------------------------------------------------------
44198 -- SPBA Peripheral Access Layer
44199 ---------------------------------------------------------------------------- */
44200
44201/*!
44202 * @addtogroup SPBA_Peripheral_Access_Layer SPBA Peripheral Access Layer
44203 * @{
44204 */
44205
44206/** SPBA - Register Layout Typedef */
44207typedef struct
44208{
44209 __IO uint32_t PRR[32]; /**< Peripheral Rights Register, array offset: 0x0, array step: 0x4 */
44210} SPBA_Type;
44211
44212/* ----------------------------------------------------------------------------
44213 -- SPBA Register Masks
44214 ---------------------------------------------------------------------------- */
44215
44216/*!
44217 * @addtogroup SPBA_Register_Masks SPBA Register Masks
44218 * @{
44219 */
44220
44221/*! @name PRR - Peripheral Rights Register */
44222/*! @{ */
44223#define SPBA_PRR_RARA_MASK (0x1U)
44224#define SPBA_PRR_RARA_SHIFT (0U)
44225/*! RARA
44226 * 0b0..Access to peripheral is not allowed.
44227 * 0b1..Access to peripheral is granted.
44228 */
44229#define SPBA_PRR_RARA(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARA_SHIFT)) & SPBA_PRR_RARA_MASK)
44230#define SPBA_PRR_RARB_MASK (0x2U)
44231#define SPBA_PRR_RARB_SHIFT (1U)
44232/*! RARB
44233 * 0b0..Access to peripheral is not allowed.
44234 * 0b1..Access to peripheral is granted.
44235 */
44236#define SPBA_PRR_RARB(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARB_SHIFT)) & SPBA_PRR_RARB_MASK)
44237#define SPBA_PRR_RARC_MASK (0x4U)
44238#define SPBA_PRR_RARC_SHIFT (2U)
44239/*! RARC
44240 * 0b0..Access to peripheral is not allowed.
44241 * 0b1..Access to peripheral is granted.
44242 */
44243#define SPBA_PRR_RARC(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RARC_SHIFT)) & SPBA_PRR_RARC_MASK)
44244#define SPBA_PRR_ROI_MASK (0x30000U)
44245#define SPBA_PRR_ROI_SHIFT (16U)
44246/*! ROI
44247 * 0b00..Unowned resource.
44248 * 0b01..The resource is owned by master A port.
44249 * 0b10..The resource is owned by master B port.
44250 * 0b11..The resource is owned by master C port.
44251 */
44252#define SPBA_PRR_ROI(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_ROI_SHIFT)) & SPBA_PRR_ROI_MASK)
44253#define SPBA_PRR_RMO_MASK (0xC0000000U)
44254#define SPBA_PRR_RMO_SHIFT (30U)
44255/*! RMO
44256 * 0b00..The resource is unowned.
44257 * 0b01..Reserved.
44258 * 0b10..The resource is owned by another master.
44259 * 0b11..The resource is owned by the requesting master.
44260 */
44261#define SPBA_PRR_RMO(x) (((uint32_t)(((uint32_t)(x)) << SPBA_PRR_RMO_SHIFT)) & SPBA_PRR_RMO_MASK)
44262/*! @} */
44263
44264/* The count of SPBA_PRR */
44265#define SPBA_PRR_COUNT (32U)
44266
44267/*!
44268 * @}
44269 */ /* end of group SPBA_Register_Masks */
44270
44271/* SPBA - Peripheral instance base addresses */
44272/** Peripheral SPBA1 base address */
44273#define SPBA1_BASE (0x308F0000u)
44274/** Peripheral SPBA1 base pointer */
44275#define SPBA1 ((SPBA_Type *)SPBA1_BASE)
44276/** Peripheral SPBA2 base address */
44277#define SPBA2_BASE (0x300F0000u)
44278/** Peripheral SPBA2 base pointer */
44279#define SPBA2 ((SPBA_Type *)SPBA2_BASE)
44280/** Array initializer of SPBA peripheral base addresses */
44281#define SPBA_BASE_ADDRS \
44282 { \
44283 SPBA1_BASE, SPBA2_BASE \
44284 }
44285/** Array initializer of SPBA peripheral base pointers */
44286#define SPBA_BASE_PTRS \
44287 { \
44288 SPBA1, SPBA2 \
44289 }
44290
44291/*!
44292 * @}
44293 */ /* end of group SPBA_Peripheral_Access_Layer */
44294
44295/* ----------------------------------------------------------------------------
44296 -- SPDIF Peripheral Access Layer
44297 ---------------------------------------------------------------------------- */
44298
44299/*!
44300 * @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer
44301 * @{
44302 */
44303
44304/** SPDIF - Register Layout Typedef */
44305typedef struct
44306{
44307 __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */
44308 __IO uint32_t SRCD; /**< CDText Control Register, offset: 0x4 */
44309 __IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */
44310 __IO uint32_t SIE; /**< InterruptEn Register, offset: 0xC */
44311 union
44312 { /* offset: 0x10 */
44313 __O uint32_t SIC; /**< InterruptClear Register, offset: 0x10 */
44314 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */
44315 };
44316 __I uint32_t SRL; /**< SPDIFRxLeft Register, offset: 0x14 */
44317 __I uint32_t SRR; /**< SPDIFRxRight Register, offset: 0x18 */
44318 __I uint32_t SRCSH; /**< SPDIFRxCChannel_h Register, offset: 0x1C */
44319 __I uint32_t SRCSL; /**< SPDIFRxCChannel_l Register, offset: 0x20 */
44320 __I uint32_t SRU; /**< UchannelRx Register, offset: 0x24 */
44321 __I uint32_t SRQ; /**< QchannelRx Register, offset: 0x28 */
44322 __O uint32_t STL; /**< SPDIFTxLeft Register, offset: 0x2C */
44323 __O uint32_t STR; /**< SPDIFTxRight Register, offset: 0x30 */
44324 __IO uint32_t STCSCH; /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */
44325 __IO uint32_t STCSCL; /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */
44326 uint8_t RESERVED_0[8];
44327 __I uint32_t SRFM; /**< FreqMeas Register, offset: 0x44 */
44328 uint8_t RESERVED_1[8];
44329 __IO uint32_t STC; /**< SPDIFTxClk Register, offset: 0x50 */
44330} SPDIF_Type;
44331
44332/* ----------------------------------------------------------------------------
44333 -- SPDIF Register Masks
44334 ---------------------------------------------------------------------------- */
44335
44336/*!
44337 * @addtogroup SPDIF_Register_Masks SPDIF Register Masks
44338 * @{
44339 */
44340
44341/*! @name SCR - SPDIF Configuration Register */
44342/*! @{ */
44343#define SPDIF_SCR_USrc_Sel_MASK (0x3U)
44344#define SPDIF_SCR_USrc_Sel_SHIFT (0U)
44345/*! USrc_Sel - USrc_Sel
44346 * 0b00..No embedded U channel
44347 * 0b01..U channel from SPDIF receive block (CD mode)
44348 * 0b10..Reserved
44349 * 0b11..U channel from on chip transmitter
44350 */
44351#define SPDIF_SCR_USrc_Sel(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USrc_Sel_SHIFT)) & SPDIF_SCR_USrc_Sel_MASK)
44352#define SPDIF_SCR_TxSel_MASK (0x1CU)
44353#define SPDIF_SCR_TxSel_SHIFT (2U)
44354/*! TxSel - TxSel
44355 * 0b000..Off and output 0
44356 * 0b001..Feed-through SPDIFIN
44357 * 0b101..Tx Normal operation
44358 */
44359#define SPDIF_SCR_TxSel(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TxSel_SHIFT)) & SPDIF_SCR_TxSel_MASK)
44360#define SPDIF_SCR_ValCtrl_MASK (0x20U)
44361#define SPDIF_SCR_ValCtrl_SHIFT (5U)
44362/*! ValCtrl - ValCtrl
44363 * 0b0..Outgoing Validity always set
44364 * 0b1..Outgoing Validity always clear
44365 */
44366#define SPDIF_SCR_ValCtrl(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_ValCtrl_SHIFT)) & SPDIF_SCR_ValCtrl_MASK)
44367#define SPDIF_SCR_DMA_TX_En_MASK (0x100U)
44368#define SPDIF_SCR_DMA_TX_En_SHIFT (8U)
44369#define SPDIF_SCR_DMA_TX_En(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_En_SHIFT)) & SPDIF_SCR_DMA_TX_En_MASK)
44370#define SPDIF_SCR_DMA_Rx_En_MASK (0x200U)
44371#define SPDIF_SCR_DMA_Rx_En_SHIFT (9U)
44372#define SPDIF_SCR_DMA_Rx_En(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_Rx_En_SHIFT)) & SPDIF_SCR_DMA_Rx_En_MASK)
44373#define SPDIF_SCR_TxFIFO_Ctrl_MASK (0xC00U)
44374#define SPDIF_SCR_TxFIFO_Ctrl_SHIFT (10U)
44375/*! TxFIFO_Ctrl - TxFIFO_Ctrl
44376 * 0b00..Send out digital zero on SPDIF Tx
44377 * 0b01..Tx Normal operation
44378 * 0b10..Reset to 1 sample remaining
44379 * 0b11..Reserved
44380 */
44381#define SPDIF_SCR_TxFIFO_Ctrl(x) \
44382 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TxFIFO_Ctrl_SHIFT)) & SPDIF_SCR_TxFIFO_Ctrl_MASK)
44383#define SPDIF_SCR_soft_reset_MASK (0x1000U)
44384#define SPDIF_SCR_soft_reset_SHIFT (12U)
44385#define SPDIF_SCR_soft_reset(x) \
44386 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_soft_reset_SHIFT)) & SPDIF_SCR_soft_reset_MASK)
44387#define SPDIF_SCR_LOW_POWER_MASK (0x2000U)
44388#define SPDIF_SCR_LOW_POWER_SHIFT (13U)
44389#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)
44390#define SPDIF_SCR_RAW_CAPTURE_MODE_MASK (0x4000U)
44391#define SPDIF_SCR_RAW_CAPTURE_MODE_SHIFT (14U)
44392#define SPDIF_SCR_RAW_CAPTURE_MODE(x) \
44393 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RAW_CAPTURE_MODE_SHIFT)) & SPDIF_SCR_RAW_CAPTURE_MODE_MASK)
44394#define SPDIF_SCR_TxFIFOEmpty_Sel_MASK (0x18000U)
44395#define SPDIF_SCR_TxFIFOEmpty_Sel_SHIFT (15U)
44396/*! TxFIFOEmpty_Sel - TxFIFOEmpty_Sel
44397 * 0b00..Empty interrupt if 0 sample in Tx left and right FIFOs
44398 * 0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs
44399 * 0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs
44400 * 0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs
44401 */
44402#define SPDIF_SCR_TxFIFOEmpty_Sel(x) \
44403 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TxFIFOEmpty_Sel_SHIFT)) & SPDIF_SCR_TxFIFOEmpty_Sel_MASK)
44404#define SPDIF_SCR_TxAutoSync_MASK (0x20000U)
44405#define SPDIF_SCR_TxAutoSync_SHIFT (17U)
44406/*! TxAutoSync - TxAutoSync
44407 * 0b0..Tx FIFO auto sync off
44408 * 0b1..Tx FIFO auto sync on
44409 */
44410#define SPDIF_SCR_TxAutoSync(x) \
44411 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TxAutoSync_SHIFT)) & SPDIF_SCR_TxAutoSync_MASK)
44412#define SPDIF_SCR_RxAutoSync_MASK (0x40000U)
44413#define SPDIF_SCR_RxAutoSync_SHIFT (18U)
44414/*! RxAutoSync - RxAutoSync
44415 * 0b0..Rx FIFO auto sync off
44416 * 0b1..RxFIFO auto sync on
44417 */
44418#define SPDIF_SCR_RxAutoSync(x) \
44419 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RxAutoSync_SHIFT)) & SPDIF_SCR_RxAutoSync_MASK)
44420#define SPDIF_SCR_RxFIFOFull_Sel_MASK (0x180000U)
44421#define SPDIF_SCR_RxFIFOFull_Sel_SHIFT (19U)
44422/*! RxFIFOFull_Sel - RxFIFOFull_Sel
44423 * 0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs
44424 * 0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs
44425 * 0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs
44426 * 0b11..Full interrupt if at least 16 sample in Rx left and right FIFO
44427 */
44428#define SPDIF_SCR_RxFIFOFull_Sel(x) \
44429 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RxFIFOFull_Sel_SHIFT)) & SPDIF_SCR_RxFIFOFull_Sel_MASK)
44430#define SPDIF_SCR_RxFIFO_Rst_MASK (0x200000U)
44431#define SPDIF_SCR_RxFIFO_Rst_SHIFT (21U)
44432/*! RxFIFO_Rst - RxFIFO_Rst
44433 * 0b0..Normal operation
44434 * 0b1..Reset register to 1 sample remaining
44435 */
44436#define SPDIF_SCR_RxFIFO_Rst(x) \
44437 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RxFIFO_Rst_SHIFT)) & SPDIF_SCR_RxFIFO_Rst_MASK)
44438#define SPDIF_SCR_RxFIFO_Off_On_MASK (0x400000U)
44439#define SPDIF_SCR_RxFIFO_Off_On_SHIFT (22U)
44440/*! RxFIFO_Off_On - RxFIFO_Off_On
44441 * 0b0..SPDIF Rx FIFO is on
44442 * 0b1..SPDIF Rx FIFO is off. Does not accept data from interface
44443 */
44444#define SPDIF_SCR_RxFIFO_Off_On(x) \
44445 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RxFIFO_Off_On_SHIFT)) & SPDIF_SCR_RxFIFO_Off_On_MASK)
44446#define SPDIF_SCR_RxFIFO_Ctrl_MASK (0x800000U)
44447#define SPDIF_SCR_RxFIFO_Ctrl_SHIFT (23U)
44448/*! RxFIFO_Ctrl - RxFIFO_Ctrl
44449 * 0b0..Normal operation
44450 * 0b1..Always read zero from Rx data register
44451 */
44452#define SPDIF_SCR_RxFIFO_Ctrl(x) \
44453 (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RxFIFO_Ctrl_SHIFT)) & SPDIF_SCR_RxFIFO_Ctrl_MASK)
44454/*! @} */
44455
44456/*! @name SRCD - CDText Control Register */
44457/*! @{ */
44458#define SPDIF_SRCD_USyncMode_MASK (0x2U)
44459#define SPDIF_SRCD_USyncMode_SHIFT (1U)
44460/*! USyncMode - USyncMode
44461 * 0b0..Non-CD data
44462 * 0b1..CD user channel subcode
44463 */
44464#define SPDIF_SRCD_USyncMode(x) \
44465 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USyncMode_SHIFT)) & SPDIF_SRCD_USyncMode_MASK)
44466/*! @} */
44467
44468/*! @name SRPC - PhaseConfig Register */
44469/*! @{ */
44470#define SPDIF_SRPC_GainSel_MASK (0x38U)
44471#define SPDIF_SRPC_GainSel_SHIFT (3U)
44472/*! GainSel - GainSel
44473 * 0b000..24*(2**10)
44474 * 0b001..16*(2**10)
44475 * 0b010..12*(2**10)
44476 * 0b011..8*(2**10)
44477 * 0b100..6*(2**10)
44478 * 0b101..4*(2**10)
44479 * 0b110..3*(2**10)
44480 */
44481#define SPDIF_SRPC_GainSel(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GainSel_SHIFT)) & SPDIF_SRPC_GainSel_MASK)
44482#define SPDIF_SRPC_LOCK_MASK (0x40U)
44483#define SPDIF_SRPC_LOCK_SHIFT (6U)
44484#define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)
44485#define SPDIF_SRPC_ClkSrc_Sel_MASK (0x780U)
44486#define SPDIF_SRPC_ClkSrc_Sel_SHIFT (7U)
44487/*! ClkSrc_Sel - ClkSrc_Sel
44488 * 0b0000..Clock Selection from Audio Clock Mux (ACM)
44489 */
44490#define SPDIF_SRPC_ClkSrc_Sel(x) \
44491 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_ClkSrc_Sel_SHIFT)) & SPDIF_SRPC_ClkSrc_Sel_MASK)
44492/*! @} */
44493
44494/*! @name SIE - InterruptEn Register */
44495/*! @{ */
44496#define SPDIF_SIE_RxFIFOFul_MASK (0x1U)
44497#define SPDIF_SIE_RxFIFOFul_SHIFT (0U)
44498#define SPDIF_SIE_RxFIFOFul(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RxFIFOFul_SHIFT)) & SPDIF_SIE_RxFIFOFul_MASK)
44499#define SPDIF_SIE_TxEm_MASK (0x2U)
44500#define SPDIF_SIE_TxEm_SHIFT (1U)
44501#define SPDIF_SIE_TxEm(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TxEm_SHIFT)) & SPDIF_SIE_TxEm_MASK)
44502#define SPDIF_SIE_LockLoss_MASK (0x4U)
44503#define SPDIF_SIE_LockLoss_SHIFT (2U)
44504#define SPDIF_SIE_LockLoss(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LockLoss_SHIFT)) & SPDIF_SIE_LockLoss_MASK)
44505#define SPDIF_SIE_RxFIFOResyn_MASK (0x8U)
44506#define SPDIF_SIE_RxFIFOResyn_SHIFT (3U)
44507#define SPDIF_SIE_RxFIFOResyn(x) \
44508 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RxFIFOResyn_SHIFT)) & SPDIF_SIE_RxFIFOResyn_MASK)
44509#define SPDIF_SIE_RxFIFOUnOv_MASK (0x10U)
44510#define SPDIF_SIE_RxFIFOUnOv_SHIFT (4U)
44511#define SPDIF_SIE_RxFIFOUnOv(x) \
44512 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RxFIFOUnOv_SHIFT)) & SPDIF_SIE_RxFIFOUnOv_MASK)
44513#define SPDIF_SIE_UQErr_MASK (0x20U)
44514#define SPDIF_SIE_UQErr_SHIFT (5U)
44515#define SPDIF_SIE_UQErr(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQErr_SHIFT)) & SPDIF_SIE_UQErr_MASK)
44516#define SPDIF_SIE_UQSync_MASK (0x40U)
44517#define SPDIF_SIE_UQSync_SHIFT (6U)
44518#define SPDIF_SIE_UQSync(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSync_SHIFT)) & SPDIF_SIE_UQSync_MASK)
44519#define SPDIF_SIE_QRxOv_MASK (0x80U)
44520#define SPDIF_SIE_QRxOv_SHIFT (7U)
44521#define SPDIF_SIE_QRxOv(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRxOv_SHIFT)) & SPDIF_SIE_QRxOv_MASK)
44522#define SPDIF_SIE_QRxFul_MASK (0x100U)
44523#define SPDIF_SIE_QRxFul_SHIFT (8U)
44524#define SPDIF_SIE_QRxFul(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRxFul_SHIFT)) & SPDIF_SIE_QRxFul_MASK)
44525#define SPDIF_SIE_URxOv_MASK (0x200U)
44526#define SPDIF_SIE_URxOv_SHIFT (9U)
44527#define SPDIF_SIE_URxOv(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URxOv_SHIFT)) & SPDIF_SIE_URxOv_MASK)
44528#define SPDIF_SIE_URxFul_MASK (0x400U)
44529#define SPDIF_SIE_URxFul_SHIFT (10U)
44530#define SPDIF_SIE_URxFul(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URxFul_SHIFT)) & SPDIF_SIE_URxFul_MASK)
44531#define SPDIF_SIE_BitErr_MASK (0x4000U)
44532#define SPDIF_SIE_BitErr_SHIFT (14U)
44533#define SPDIF_SIE_BitErr(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BitErr_SHIFT)) & SPDIF_SIE_BitErr_MASK)
44534#define SPDIF_SIE_SymErr_MASK (0x8000U)
44535#define SPDIF_SIE_SymErr_SHIFT (15U)
44536#define SPDIF_SIE_SymErr(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SymErr_SHIFT)) & SPDIF_SIE_SymErr_MASK)
44537#define SPDIF_SIE_ValNoGood_MASK (0x10000U)
44538#define SPDIF_SIE_ValNoGood_SHIFT (16U)
44539#define SPDIF_SIE_ValNoGood(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_ValNoGood_SHIFT)) & SPDIF_SIE_ValNoGood_MASK)
44540#define SPDIF_SIE_CNew_MASK (0x20000U)
44541#define SPDIF_SIE_CNew_SHIFT (17U)
44542#define SPDIF_SIE_CNew(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNew_SHIFT)) & SPDIF_SIE_CNew_MASK)
44543#define SPDIF_SIE_TxResyn_MASK (0x40000U)
44544#define SPDIF_SIE_TxResyn_SHIFT (18U)
44545#define SPDIF_SIE_TxResyn(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TxResyn_SHIFT)) & SPDIF_SIE_TxResyn_MASK)
44546#define SPDIF_SIE_TxUnOv_MASK (0x80000U)
44547#define SPDIF_SIE_TxUnOv_SHIFT (19U)
44548#define SPDIF_SIE_TxUnOv(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TxUnOv_SHIFT)) & SPDIF_SIE_TxUnOv_MASK)
44549#define SPDIF_SIE_Lock_MASK (0x100000U)
44550#define SPDIF_SIE_Lock_SHIFT (20U)
44551#define SPDIF_SIE_Lock(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_Lock_SHIFT)) & SPDIF_SIE_Lock_MASK)
44552/*! @} */
44553
44554/*! @name SIC - InterruptClear Register */
44555/*! @{ */
44556#define SPDIF_SIC_LockLoss_MASK (0x4U)
44557#define SPDIF_SIC_LockLoss_SHIFT (2U)
44558#define SPDIF_SIC_LockLoss(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LockLoss_SHIFT)) & SPDIF_SIC_LockLoss_MASK)
44559#define SPDIF_SIC_RxFIFOResyn_MASK (0x8U)
44560#define SPDIF_SIC_RxFIFOResyn_SHIFT (3U)
44561#define SPDIF_SIC_RxFIFOResyn(x) \
44562 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RxFIFOResyn_SHIFT)) & SPDIF_SIC_RxFIFOResyn_MASK)
44563#define SPDIF_SIC_RxFIFOUnOv_MASK (0x10U)
44564#define SPDIF_SIC_RxFIFOUnOv_SHIFT (4U)
44565#define SPDIF_SIC_RxFIFOUnOv(x) \
44566 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RxFIFOUnOv_SHIFT)) & SPDIF_SIC_RxFIFOUnOv_MASK)
44567#define SPDIF_SIC_UQErr_MASK (0x20U)
44568#define SPDIF_SIC_UQErr_SHIFT (5U)
44569#define SPDIF_SIC_UQErr(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQErr_SHIFT)) & SPDIF_SIC_UQErr_MASK)
44570#define SPDIF_SIC_UQSync_MASK (0x40U)
44571#define SPDIF_SIC_UQSync_SHIFT (6U)
44572#define SPDIF_SIC_UQSync(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSync_SHIFT)) & SPDIF_SIC_UQSync_MASK)
44573#define SPDIF_SIC_QRxOv_MASK (0x80U)
44574#define SPDIF_SIC_QRxOv_SHIFT (7U)
44575#define SPDIF_SIC_QRxOv(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRxOv_SHIFT)) & SPDIF_SIC_QRxOv_MASK)
44576#define SPDIF_SIC_URxOv_MASK (0x200U)
44577#define SPDIF_SIC_URxOv_SHIFT (9U)
44578#define SPDIF_SIC_URxOv(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URxOv_SHIFT)) & SPDIF_SIC_URxOv_MASK)
44579#define SPDIF_SIC_BitErr_MASK (0x4000U)
44580#define SPDIF_SIC_BitErr_SHIFT (14U)
44581#define SPDIF_SIC_BitErr(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BitErr_SHIFT)) & SPDIF_SIC_BitErr_MASK)
44582#define SPDIF_SIC_SymErr_MASK (0x8000U)
44583#define SPDIF_SIC_SymErr_SHIFT (15U)
44584#define SPDIF_SIC_SymErr(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SymErr_SHIFT)) & SPDIF_SIC_SymErr_MASK)
44585#define SPDIF_SIC_ValNoGood_MASK (0x10000U)
44586#define SPDIF_SIC_ValNoGood_SHIFT (16U)
44587#define SPDIF_SIC_ValNoGood(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_ValNoGood_SHIFT)) & SPDIF_SIC_ValNoGood_MASK)
44588#define SPDIF_SIC_CNew_MASK (0x20000U)
44589#define SPDIF_SIC_CNew_SHIFT (17U)
44590#define SPDIF_SIC_CNew(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNew_SHIFT)) & SPDIF_SIC_CNew_MASK)
44591#define SPDIF_SIC_TxResyn_MASK (0x40000U)
44592#define SPDIF_SIC_TxResyn_SHIFT (18U)
44593#define SPDIF_SIC_TxResyn(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TxResyn_SHIFT)) & SPDIF_SIC_TxResyn_MASK)
44594#define SPDIF_SIC_TxUnOv_MASK (0x80000U)
44595#define SPDIF_SIC_TxUnOv_SHIFT (19U)
44596#define SPDIF_SIC_TxUnOv(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TxUnOv_SHIFT)) & SPDIF_SIC_TxUnOv_MASK)
44597#define SPDIF_SIC_Lock_MASK (0x100000U)
44598#define SPDIF_SIC_Lock_SHIFT (20U)
44599#define SPDIF_SIC_Lock(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_Lock_SHIFT)) & SPDIF_SIC_Lock_MASK)
44600/*! @} */
44601
44602/*! @name SIS - InterruptStat Register */
44603/*! @{ */
44604#define SPDIF_SIS_RxFIFOFul_MASK (0x1U)
44605#define SPDIF_SIS_RxFIFOFul_SHIFT (0U)
44606#define SPDIF_SIS_RxFIFOFul(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RxFIFOFul_SHIFT)) & SPDIF_SIS_RxFIFOFul_MASK)
44607#define SPDIF_SIS_TxEm_MASK (0x2U)
44608#define SPDIF_SIS_TxEm_SHIFT (1U)
44609#define SPDIF_SIS_TxEm(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TxEm_SHIFT)) & SPDIF_SIS_TxEm_MASK)
44610#define SPDIF_SIS_LockLoss_MASK (0x4U)
44611#define SPDIF_SIS_LockLoss_SHIFT (2U)
44612#define SPDIF_SIS_LockLoss(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LockLoss_SHIFT)) & SPDIF_SIS_LockLoss_MASK)
44613#define SPDIF_SIS_RxFIFOResyn_MASK (0x8U)
44614#define SPDIF_SIS_RxFIFOResyn_SHIFT (3U)
44615#define SPDIF_SIS_RxFIFOResyn(x) \
44616 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RxFIFOResyn_SHIFT)) & SPDIF_SIS_RxFIFOResyn_MASK)
44617#define SPDIF_SIS_RxFIFOUnOv_MASK (0x10U)
44618#define SPDIF_SIS_RxFIFOUnOv_SHIFT (4U)
44619#define SPDIF_SIS_RxFIFOUnOv(x) \
44620 (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RxFIFOUnOv_SHIFT)) & SPDIF_SIS_RxFIFOUnOv_MASK)
44621#define SPDIF_SIS_UQErr_MASK (0x20U)
44622#define SPDIF_SIS_UQErr_SHIFT (5U)
44623#define SPDIF_SIS_UQErr(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQErr_SHIFT)) & SPDIF_SIS_UQErr_MASK)
44624#define SPDIF_SIS_UQSync_MASK (0x40U)
44625#define SPDIF_SIS_UQSync_SHIFT (6U)
44626#define SPDIF_SIS_UQSync(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSync_SHIFT)) & SPDIF_SIS_UQSync_MASK)
44627#define SPDIF_SIS_QRxOv_MASK (0x80U)
44628#define SPDIF_SIS_QRxOv_SHIFT (7U)
44629#define SPDIF_SIS_QRxOv(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRxOv_SHIFT)) & SPDIF_SIS_QRxOv_MASK)
44630#define SPDIF_SIS_QRxFul_MASK (0x100U)
44631#define SPDIF_SIS_QRxFul_SHIFT (8U)
44632#define SPDIF_SIS_QRxFul(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRxFul_SHIFT)) & SPDIF_SIS_QRxFul_MASK)
44633#define SPDIF_SIS_URxOv_MASK (0x200U)
44634#define SPDIF_SIS_URxOv_SHIFT (9U)
44635#define SPDIF_SIS_URxOv(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URxOv_SHIFT)) & SPDIF_SIS_URxOv_MASK)
44636#define SPDIF_SIS_URxFul_MASK (0x400U)
44637#define SPDIF_SIS_URxFul_SHIFT (10U)
44638#define SPDIF_SIS_URxFul(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URxFul_SHIFT)) & SPDIF_SIS_URxFul_MASK)
44639#define SPDIF_SIS_BitErr_MASK (0x4000U)
44640#define SPDIF_SIS_BitErr_SHIFT (14U)
44641#define SPDIF_SIS_BitErr(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BitErr_SHIFT)) & SPDIF_SIS_BitErr_MASK)
44642#define SPDIF_SIS_SymErr_MASK (0x8000U)
44643#define SPDIF_SIS_SymErr_SHIFT (15U)
44644#define SPDIF_SIS_SymErr(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SymErr_SHIFT)) & SPDIF_SIS_SymErr_MASK)
44645#define SPDIF_SIS_ValNoGood_MASK (0x10000U)
44646#define SPDIF_SIS_ValNoGood_SHIFT (16U)
44647#define SPDIF_SIS_ValNoGood(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_ValNoGood_SHIFT)) & SPDIF_SIS_ValNoGood_MASK)
44648#define SPDIF_SIS_CNew_MASK (0x20000U)
44649#define SPDIF_SIS_CNew_SHIFT (17U)
44650#define SPDIF_SIS_CNew(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNew_SHIFT)) & SPDIF_SIS_CNew_MASK)
44651#define SPDIF_SIS_TxResyn_MASK (0x40000U)
44652#define SPDIF_SIS_TxResyn_SHIFT (18U)
44653#define SPDIF_SIS_TxResyn(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TxResyn_SHIFT)) & SPDIF_SIS_TxResyn_MASK)
44654#define SPDIF_SIS_TxUnOv_MASK (0x80000U)
44655#define SPDIF_SIS_TxUnOv_SHIFT (19U)
44656#define SPDIF_SIS_TxUnOv(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TxUnOv_SHIFT)) & SPDIF_SIS_TxUnOv_MASK)
44657#define SPDIF_SIS_Lock_MASK (0x100000U)
44658#define SPDIF_SIS_Lock_SHIFT (20U)
44659#define SPDIF_SIS_Lock(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_Lock_SHIFT)) & SPDIF_SIS_Lock_MASK)
44660/*! @} */
44661
44662/*! @name SRL - SPDIFRxLeft Register */
44663/*! @{ */
44664#define SPDIF_SRL_RxDataLeft_MASK (0xFFFFFFU)
44665#define SPDIF_SRL_RxDataLeft_SHIFT (0U)
44666#define SPDIF_SRL_RxDataLeft(x) \
44667 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RxDataLeft_SHIFT)) & SPDIF_SRL_RxDataLeft_MASK)
44668/*! @} */
44669
44670/*! @name SRR - SPDIFRxRight Register */
44671/*! @{ */
44672#define SPDIF_SRR_RxDataRight_MASK (0xFFFFFFU)
44673#define SPDIF_SRR_RxDataRight_SHIFT (0U)
44674#define SPDIF_SRR_RxDataRight(x) \
44675 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RxDataRight_SHIFT)) & SPDIF_SRR_RxDataRight_MASK)
44676/*! @} */
44677
44678/*! @name SRCSH - SPDIFRxCChannel_h Register */
44679/*! @{ */
44680#define SPDIF_SRCSH_RxCChannel_h_MASK (0xFFFFFFU)
44681#define SPDIF_SRCSH_RxCChannel_h_SHIFT (0U)
44682#define SPDIF_SRCSH_RxCChannel_h(x) \
44683 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RxCChannel_h_SHIFT)) & SPDIF_SRCSH_RxCChannel_h_MASK)
44684/*! @} */
44685
44686/*! @name SRCSL - SPDIFRxCChannel_l Register */
44687/*! @{ */
44688#define SPDIF_SRCSL_RxCChannel_l_MASK (0xFFFFFFU)
44689#define SPDIF_SRCSL_RxCChannel_l_SHIFT (0U)
44690#define SPDIF_SRCSL_RxCChannel_l(x) \
44691 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RxCChannel_l_SHIFT)) & SPDIF_SRCSL_RxCChannel_l_MASK)
44692/*! @} */
44693
44694/*! @name SRU - UchannelRx Register */
44695/*! @{ */
44696#define SPDIF_SRU_RxUChannel_MASK (0xFFFFFFU)
44697#define SPDIF_SRU_RxUChannel_SHIFT (0U)
44698#define SPDIF_SRU_RxUChannel(x) \
44699 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RxUChannel_SHIFT)) & SPDIF_SRU_RxUChannel_MASK)
44700/*! @} */
44701
44702/*! @name SRQ - QchannelRx Register */
44703/*! @{ */
44704#define SPDIF_SRQ_RxQChannel_MASK (0xFFFFFFU)
44705#define SPDIF_SRQ_RxQChannel_SHIFT (0U)
44706#define SPDIF_SRQ_RxQChannel(x) \
44707 (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RxQChannel_SHIFT)) & SPDIF_SRQ_RxQChannel_MASK)
44708/*! @} */
44709
44710/*! @name STL - SPDIFTxLeft Register */
44711/*! @{ */
44712#define SPDIF_STL_TxDataLeft_MASK (0xFFFFFFU)
44713#define SPDIF_STL_TxDataLeft_SHIFT (0U)
44714#define SPDIF_STL_TxDataLeft(x) \
44715 (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TxDataLeft_SHIFT)) & SPDIF_STL_TxDataLeft_MASK)
44716/*! @} */
44717
44718/*! @name STR - SPDIFTxRight Register */
44719/*! @{ */
44720#define SPDIF_STR_TxDataRight_MASK (0xFFFFFFU)
44721#define SPDIF_STR_TxDataRight_SHIFT (0U)
44722#define SPDIF_STR_TxDataRight(x) \
44723 (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TxDataRight_SHIFT)) & SPDIF_STR_TxDataRight_MASK)
44724/*! @} */
44725
44726/*! @name STCSCH - SPDIFTxCChannelCons_h Register */
44727/*! @{ */
44728#define SPDIF_STCSCH_TxCChannelCons_h_MASK (0xFFFFFFU)
44729#define SPDIF_STCSCH_TxCChannelCons_h_SHIFT (0U)
44730#define SPDIF_STCSCH_TxCChannelCons_h(x) \
44731 (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TxCChannelCons_h_SHIFT)) & SPDIF_STCSCH_TxCChannelCons_h_MASK)
44732/*! @} */
44733
44734/*! @name STCSCL - SPDIFTxCChannelCons_l Register */
44735/*! @{ */
44736#define SPDIF_STCSCL_TxCChannelCons_l_MASK (0xFFFFFFU)
44737#define SPDIF_STCSCL_TxCChannelCons_l_SHIFT (0U)
44738#define SPDIF_STCSCL_TxCChannelCons_l(x) \
44739 (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TxCChannelCons_l_SHIFT)) & SPDIF_STCSCL_TxCChannelCons_l_MASK)
44740/*! @} */
44741
44742/*! @name SRFM - FreqMeas Register */
44743/*! @{ */
44744#define SPDIF_SRFM_FreqMeas_MASK (0xFFFFFFU)
44745#define SPDIF_SRFM_FreqMeas_SHIFT (0U)
44746#define SPDIF_SRFM_FreqMeas(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FreqMeas_SHIFT)) & SPDIF_SRFM_FreqMeas_MASK)
44747/*! @} */
44748
44749/*! @name STC - SPDIFTxClk Register */
44750/*! @{ */
44751#define SPDIF_STC_TxClk_DF_MASK (0x7FU)
44752#define SPDIF_STC_TxClk_DF_SHIFT (0U)
44753/*! TxClk_DF - TxClk_DF
44754 * 0b0000000..divider factor is 1
44755 * 0b0000001..divider factor is 2
44756 * 0b1111111..divider factor is 128
44757 */
44758#define SPDIF_STC_TxClk_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TxClk_DF_SHIFT)) & SPDIF_STC_TxClk_DF_MASK)
44759#define SPDIF_STC_tx_all_clk_en_MASK (0x80U)
44760#define SPDIF_STC_tx_all_clk_en_SHIFT (7U)
44761/*! tx_all_clk_en - tx_all_clk_en
44762 * 0b0..disable transfer clock.
44763 * 0b1..enable transfer clock.
44764 */
44765#define SPDIF_STC_tx_all_clk_en(x) \
44766 (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_tx_all_clk_en_SHIFT)) & SPDIF_STC_tx_all_clk_en_MASK)
44767#define SPDIF_STC_TxClk_Source_MASK (0x700U)
44768#define SPDIF_STC_TxClk_Source_SHIFT (8U)
44769/*! TxClk_Source - TxClk_Source
44770 * 0b000..Clock Selection from Audio Clock Mux (ACM)
44771 */
44772#define SPDIF_STC_TxClk_Source(x) \
44773 (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TxClk_Source_SHIFT)) & SPDIF_STC_TxClk_Source_MASK)
44774#define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U)
44775#define SPDIF_STC_SYSCLK_DF_SHIFT (11U)
44776/*! SYSCLK_DF - SYSCLK_DF
44777 * 0b000000000..no clock signal
44778 * 0b000000001..divider factor is 2
44779 * 0b111111111..divider factor is 512
44780 */
44781#define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)
44782/*! @} */
44783
44784/*!
44785 * @}
44786 */ /* end of group SPDIF_Register_Masks */
44787
44788/* SPDIF - Peripheral instance base addresses */
44789/** Peripheral SPDIF1 base address */
44790#define SPDIF1_BASE (0x30090000u)
44791/** Peripheral SPDIF1 base pointer */
44792#define SPDIF1 ((SPDIF_Type *)SPDIF1_BASE)
44793/** Peripheral SPDIF2 base address */
44794#define SPDIF2_BASE (0x300A0000u)
44795/** Peripheral SPDIF2 base pointer */
44796#define SPDIF2 ((SPDIF_Type *)SPDIF2_BASE)
44797/** Array initializer of SPDIF peripheral base addresses */
44798#define SPDIF_BASE_ADDRS \
44799 { \
44800 SPDIF1_BASE, SPDIF2_BASE \
44801 }
44802/** Array initializer of SPDIF peripheral base pointers */
44803#define SPDIF_BASE_PTRS \
44804 { \
44805 SPDIF1, SPDIF2 \
44806 }
44807
44808/*!
44809 * @}
44810 */ /* end of group SPDIF_Peripheral_Access_Layer */
44811
44812/* ----------------------------------------------------------------------------
44813 -- SRC Peripheral Access Layer
44814 ---------------------------------------------------------------------------- */
44815
44816/*!
44817 * @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer
44818 * @{
44819 */
44820
44821/** SRC - Register Layout Typedef */
44822typedef struct
44823{
44824 __IO uint32_t SCR; /**< SRC Reset Control Register, offset: 0x0 */
44825 __IO uint32_t A53RCR0; /**< A53 Reset Control Register, offset: 0x4 */
44826 __IO uint32_t A53RCR1; /**< A53 Reset Control Register, offset: 0x8 */
44827 __IO uint32_t M7RCR; /**< M7 Reset Control Register, offset: 0xC */
44828 uint8_t RESERVED_0[16];
44829 __IO uint32_t USBOPHY1_RCR; /**< USB OTG PHY1 Reset Control Register, offset: 0x20 */
44830 uint8_t RESERVED_1[4];
44831 __IO uint32_t MIPIPHY_RCR; /**< MIPI PHY Reset Control Register, offset: 0x28 */
44832 uint8_t RESERVED_2[8];
44833 __IO uint32_t DISP_RCR; /**< DISPLAY Reset Control Register, offset: 0x34 */
44834 uint8_t RESERVED_3[8];
44835 __IO uint32_t GPU_RCR; /**< GPU Reset Control Register, offset: 0x40 */
44836 uint8_t RESERVED_4[20];
44837 __I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x58 */
44838 __IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x5C */
44839 uint8_t RESERVED_5[8];
44840 __IO uint32_t SISR; /**< SRC Interrupt Status Register, offset: 0x68 */
44841 __IO uint32_t SIMR; /**< SRC Interrupt Mask Register, offset: 0x6C */
44842 __I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0x70 */
44843 __IO uint32_t GPR1; /**< SRC General Purpose Register 1, offset: 0x74 */
44844 __IO uint32_t GPR2; /**< SRC General Purpose Register 2, offset: 0x78 */
44845 __IO uint32_t GPR3; /**< SRC General Purpose Register 3, offset: 0x7C */
44846 __IO uint32_t GPR4; /**< SRC General Purpose Register 4, offset: 0x80 */
44847 __IO uint32_t GPR5; /**< SRC General Purpose Register 5, offset: 0x84 */
44848 __IO uint32_t GPR6; /**< SRC General Purpose Register 6, offset: 0x88 */
44849 __IO uint32_t GPR7; /**< SRC General Purpose Register 7, offset: 0x8C */
44850 __IO uint32_t GPR8; /**< SRC General Purpose Register 8, offset: 0x90 */
44851 uint32_t GPR9; /**< SRC General Purpose Register 9, offset: 0x94 */
44852 uint32_t GPR10; /**< SRC General Purpose Register 10, offset: 0x98 */
44853 uint8_t RESERVED_6[3940];
44854 __IO uint32_t DDRC_RCR; /**< SRC DDR Controller Reset Control Register, offset: 0x1000 */
44855} SRC_Type;
44856
44857/* ----------------------------------------------------------------------------
44858 -- SRC Register Masks
44859 ---------------------------------------------------------------------------- */
44860
44861/*!
44862 * @addtogroup SRC_Register_Masks SRC Register Masks
44863 * @{
44864 */
44865
44866/*! @name SCR - SRC Reset Control Register */
44867/*! @{ */
44868#define SRC_SCR_MASK_TEMPSENSE_RESET_MASK (0xF0U)
44869#define SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT (4U)
44870/*! MASK_TEMPSENSE_RESET
44871 * 0b0101..tempsense_reset is masked
44872 * 0b1010..tempsense_reset is not masked
44873 */
44874#define SRC_SCR_MASK_TEMPSENSE_RESET(x) \
44875 (((uint32_t)(((uint32_t)(x)) << SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT)) & SRC_SCR_MASK_TEMPSENSE_RESET_MASK)
44876#define SRC_SCR_DOMAIN0_MASK (0x1000000U)
44877#define SRC_SCR_DOMAIN0_SHIFT (24U)
44878/*! DOMAIN0
44879 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
44880 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
44881 */
44882#define SRC_SCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN0_SHIFT)) & SRC_SCR_DOMAIN0_MASK)
44883#define SRC_SCR_DOMAIN1_MASK (0x2000000U)
44884#define SRC_SCR_DOMAIN1_SHIFT (25U)
44885/*! DOMAIN1
44886 * 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
44887 * 0b1..This register is assigned to domain1. The master from domain1 can write to this register
44888 */
44889#define SRC_SCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN1_SHIFT)) & SRC_SCR_DOMAIN1_MASK)
44890#define SRC_SCR_DOMAIN2_MASK (0x4000000U)
44891#define SRC_SCR_DOMAIN2_SHIFT (26U)
44892/*! DOMAIN2
44893 * 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
44894 * 0b1..This register is assigned to domain2. The master from domain2 can write to this register
44895 */
44896#define SRC_SCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN2_SHIFT)) & SRC_SCR_DOMAIN2_MASK)
44897#define SRC_SCR_DOMAIN3_MASK (0x8000000U)
44898#define SRC_SCR_DOMAIN3_SHIFT (27U)
44899/*! DOMAIN3
44900 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
44901 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
44902 */
44903#define SRC_SCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOMAIN3_SHIFT)) & SRC_SCR_DOMAIN3_MASK)
44904#define SRC_SCR_LOCK_MASK (0x40000000U)
44905#define SRC_SCR_LOCK_SHIFT (30U)
44906/*! LOCK
44907 * 0b0..[31] and [27:24] bits can be modified
44908 * 0b1..[31] and [27:24] bits cannot be modified
44909 */
44910#define SRC_SCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_LOCK_SHIFT)) & SRC_SCR_LOCK_MASK)
44911#define SRC_SCR_DOM_EN_MASK (0x80000000U)
44912#define SRC_SCR_DOM_EN_SHIFT (31U)
44913/*! DOM_EN
44914 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
44915 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
44916 * the masters from the domains specified in [27:24] area.
44917 */
44918#define SRC_SCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_DOM_EN_SHIFT)) & SRC_SCR_DOM_EN_MASK)
44919/*! @} */
44920
44921/*! @name A53RCR0 - A53 Reset Control Register */
44922/*! @{ */
44923#define SRC_A53RCR0_A53_CORE_POR_RESET0_MASK (0x1U)
44924#define SRC_A53RCR0_A53_CORE_POR_RESET0_SHIFT (0U)
44925/*! A53_CORE_POR_RESET0
44926 * 0b0..do not assert core0 reset
44927 * 0b1..assert core0 reset
44928 */
44929#define SRC_A53RCR0_A53_CORE_POR_RESET0(x) \
44930 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET0_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET0_MASK)
44931#define SRC_A53RCR0_A53_CORE_POR_RESET1_MASK (0x2U)
44932#define SRC_A53RCR0_A53_CORE_POR_RESET1_SHIFT (1U)
44933/*! A53_CORE_POR_RESET1
44934 * 0b0..do not assert core1 reset
44935 * 0b1..assert core1 reset
44936 */
44937#define SRC_A53RCR0_A53_CORE_POR_RESET1(x) \
44938 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET1_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET1_MASK)
44939#define SRC_A53RCR0_A53_CORE_POR_RESET2_MASK (0x4U)
44940#define SRC_A53RCR0_A53_CORE_POR_RESET2_SHIFT (2U)
44941/*! A53_CORE_POR_RESET2
44942 * 0b0..do not assert core2 reset
44943 * 0b1..assert core2 reset
44944 */
44945#define SRC_A53RCR0_A53_CORE_POR_RESET2(x) \
44946 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET2_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET2_MASK)
44947#define SRC_A53RCR0_A53_CORE_POR_RESET3_MASK (0x8U)
44948#define SRC_A53RCR0_A53_CORE_POR_RESET3_SHIFT (3U)
44949/*! A53_CORE_POR_RESET3
44950 * 0b0..do not assert core3 reset
44951 * 0b1..assert core3 reset
44952 */
44953#define SRC_A53RCR0_A53_CORE_POR_RESET3(x) \
44954 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_POR_RESET3_SHIFT)) & SRC_A53RCR0_A53_CORE_POR_RESET3_MASK)
44955#define SRC_A53RCR0_A53_CORE_RESET0_MASK (0x10U)
44956#define SRC_A53RCR0_A53_CORE_RESET0_SHIFT (4U)
44957/*! A53_CORE_RESET0
44958 * 0b0..do not assert core0 reset
44959 * 0b1..assert core0 reset
44960 */
44961#define SRC_A53RCR0_A53_CORE_RESET0(x) \
44962 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET0_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET0_MASK)
44963#define SRC_A53RCR0_A53_CORE_RESET1_MASK (0x20U)
44964#define SRC_A53RCR0_A53_CORE_RESET1_SHIFT (5U)
44965/*! A53_CORE_RESET1
44966 * 0b0..do not assert core1 reset
44967 * 0b1..assert core1 reset
44968 */
44969#define SRC_A53RCR0_A53_CORE_RESET1(x) \
44970 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET1_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET1_MASK)
44971#define SRC_A53RCR0_A53_CORE_RESET2_MASK (0x40U)
44972#define SRC_A53RCR0_A53_CORE_RESET2_SHIFT (6U)
44973/*! A53_CORE_RESET2
44974 * 0b0..do not assert core2 reset
44975 * 0b1..assert core2 reset
44976 */
44977#define SRC_A53RCR0_A53_CORE_RESET2(x) \
44978 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET2_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET2_MASK)
44979#define SRC_A53RCR0_A53_CORE_RESET3_MASK (0x80U)
44980#define SRC_A53RCR0_A53_CORE_RESET3_SHIFT (7U)
44981/*! A53_CORE_RESET3
44982 * 0b0..do not assert core3 reset
44983 * 0b1..assert core3 reset
44984 */
44985#define SRC_A53RCR0_A53_CORE_RESET3(x) \
44986 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_CORE_RESET3_SHIFT)) & SRC_A53RCR0_A53_CORE_RESET3_MASK)
44987#define SRC_A53RCR0_A53_DBG_RESET0_MASK (0x100U)
44988#define SRC_A53RCR0_A53_DBG_RESET0_SHIFT (8U)
44989/*! A53_DBG_RESET0
44990 * 0b0..do not assert core0 debug reset
44991 * 0b1..assert core0 debug reset
44992 */
44993#define SRC_A53RCR0_A53_DBG_RESET0(x) \
44994 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET0_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET0_MASK)
44995#define SRC_A53RCR0_A53_DBG_RESET1_MASK (0x200U)
44996#define SRC_A53RCR0_A53_DBG_RESET1_SHIFT (9U)
44997/*! A53_DBG_RESET1
44998 * 0b0..do not assert core1 debug reset
44999 * 0b1..assert core1 debug reset
45000 */
45001#define SRC_A53RCR0_A53_DBG_RESET1(x) \
45002 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET1_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET1_MASK)
45003#define SRC_A53RCR0_A53_DBG_RESET2_MASK (0x400U)
45004#define SRC_A53RCR0_A53_DBG_RESET2_SHIFT (10U)
45005/*! A53_DBG_RESET2
45006 * 0b0..do not assert core2 debug reset
45007 * 0b1..assert core2 debug reset
45008 */
45009#define SRC_A53RCR0_A53_DBG_RESET2(x) \
45010 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET2_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET2_MASK)
45011#define SRC_A53RCR0_A53_DBG_RESET3_MASK (0x800U)
45012#define SRC_A53RCR0_A53_DBG_RESET3_SHIFT (11U)
45013/*! A53_DBG_RESET3
45014 * 0b0..do not assert core3 debug reset
45015 * 0b1..assert core3 debug reset
45016 */
45017#define SRC_A53RCR0_A53_DBG_RESET3(x) \
45018 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_DBG_RESET3_SHIFT)) & SRC_A53RCR0_A53_DBG_RESET3_MASK)
45019#define SRC_A53RCR0_A53_ETM_RESET0_MASK (0x1000U)
45020#define SRC_A53RCR0_A53_ETM_RESET0_SHIFT (12U)
45021/*! A53_ETM_RESET0
45022 * 0b0..do not assert core0 ETM reset
45023 * 0b1..assert core0 ETM reset
45024 */
45025#define SRC_A53RCR0_A53_ETM_RESET0(x) \
45026 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET0_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET0_MASK)
45027#define SRC_A53RCR0_A53_ETM_RESET1_MASK (0x2000U)
45028#define SRC_A53RCR0_A53_ETM_RESET1_SHIFT (13U)
45029/*! A53_ETM_RESET1
45030 * 0b0..do not assert core1 ETM reset
45031 * 0b1..assert core1 ETM reset
45032 */
45033#define SRC_A53RCR0_A53_ETM_RESET1(x) \
45034 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET1_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET1_MASK)
45035#define SRC_A53RCR0_A53_ETM_RESET2_MASK (0x4000U)
45036#define SRC_A53RCR0_A53_ETM_RESET2_SHIFT (14U)
45037/*! A53_ETM_RESET2
45038 * 0b0..do not assert core2 ETM reset
45039 * 0b1..assert core2 ETM reset
45040 */
45041#define SRC_A53RCR0_A53_ETM_RESET2(x) \
45042 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET2_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET2_MASK)
45043#define SRC_A53RCR0_A53_ETM_RESET3_MASK (0x8000U)
45044#define SRC_A53RCR0_A53_ETM_RESET3_SHIFT (15U)
45045/*! A53_ETM_RESET3
45046 * 0b0..do not assert core3 ETM reset
45047 * 0b1..assert core3 ETM reset
45048 */
45049#define SRC_A53RCR0_A53_ETM_RESET3(x) \
45050 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_ETM_RESET3_SHIFT)) & SRC_A53RCR0_A53_ETM_RESET3_MASK)
45051#define SRC_A53RCR0_MASK_WDOG1_RST_MASK (0xF0000U)
45052#define SRC_A53RCR0_MASK_WDOG1_RST_SHIFT (16U)
45053/*! MASK_WDOG1_RST
45054 * 0b0101..wdog1_rst_b is masked
45055 * 0b1010..wdog1_rst_b is not masked
45056 */
45057#define SRC_A53RCR0_MASK_WDOG1_RST(x) \
45058 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_MASK_WDOG1_RST_SHIFT)) & SRC_A53RCR0_MASK_WDOG1_RST_MASK)
45059#define SRC_A53RCR0_A53_SOC_DBG_RESET_MASK (0x100000U)
45060#define SRC_A53RCR0_A53_SOC_DBG_RESET_SHIFT (20U)
45061/*! A53_SOC_DBG_RESET
45062 * 0b0..do not assert system level debug reset
45063 * 0b1..assert system level debug reset
45064 */
45065#define SRC_A53RCR0_A53_SOC_DBG_RESET(x) \
45066 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_SOC_DBG_RESET_SHIFT)) & SRC_A53RCR0_A53_SOC_DBG_RESET_MASK)
45067#define SRC_A53RCR0_A53_L2RESET_MASK (0x200000U)
45068#define SRC_A53RCR0_A53_L2RESET_SHIFT (21U)
45069/*! A53_L2RESET
45070 * 0b0..do not assert SCU reset
45071 * 0b1..assert SCU reset
45072 */
45073#define SRC_A53RCR0_A53_L2RESET(x) \
45074 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_A53_L2RESET_SHIFT)) & SRC_A53RCR0_A53_L2RESET_MASK)
45075#define SRC_A53RCR0_DOMAIN0_MASK (0x1000000U)
45076#define SRC_A53RCR0_DOMAIN0_SHIFT (24U)
45077/*! DOMAIN0
45078 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
45079 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
45080 */
45081#define SRC_A53RCR0_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN0_SHIFT)) & SRC_A53RCR0_DOMAIN0_MASK)
45082#define SRC_A53RCR0_DOMAIN1_MASK (0x2000000U)
45083#define SRC_A53RCR0_DOMAIN1_SHIFT (25U)
45084/*! DOMAIN1
45085 * 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
45086 * 0b1..This register is assigned to domain1. The master from domain1 can write to this register
45087 */
45088#define SRC_A53RCR0_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN1_SHIFT)) & SRC_A53RCR0_DOMAIN1_MASK)
45089#define SRC_A53RCR0_DOMAIN2_MASK (0x4000000U)
45090#define SRC_A53RCR0_DOMAIN2_SHIFT (26U)
45091/*! DOMAIN2
45092 * 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
45093 * 0b1..This register is assigned to domain2. The master from domain2 can write to this register
45094 */
45095#define SRC_A53RCR0_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN2_SHIFT)) & SRC_A53RCR0_DOMAIN2_MASK)
45096#define SRC_A53RCR0_DOMAIN3_MASK (0x8000000U)
45097#define SRC_A53RCR0_DOMAIN3_SHIFT (27U)
45098/*! DOMAIN3
45099 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
45100 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
45101 */
45102#define SRC_A53RCR0_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOMAIN3_SHIFT)) & SRC_A53RCR0_DOMAIN3_MASK)
45103#define SRC_A53RCR0_LOCK_MASK (0x40000000U)
45104#define SRC_A53RCR0_LOCK_SHIFT (30U)
45105/*! LOCK
45106 * 0b0..[31] and [27:24] bits can be modified
45107 * 0b1..[31] and [27:24] bits cannot be modified
45108 */
45109#define SRC_A53RCR0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_LOCK_SHIFT)) & SRC_A53RCR0_LOCK_MASK)
45110#define SRC_A53RCR0_DOM_EN_MASK (0x80000000U)
45111#define SRC_A53RCR0_DOM_EN_SHIFT (31U)
45112/*! DOM_EN
45113 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
45114 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
45115 * the masters from the domains specified in [27:24] area.
45116 */
45117#define SRC_A53RCR0_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR0_DOM_EN_SHIFT)) & SRC_A53RCR0_DOM_EN_MASK)
45118/*! @} */
45119
45120/*! @name A53RCR1 - A53 Reset Control Register */
45121/*! @{ */
45122#define SRC_A53RCR1_A53_CORE0_ENABLE_MASK (0x1U)
45123#define SRC_A53RCR1_A53_CORE0_ENABLE_SHIFT (0U)
45124#define SRC_A53RCR1_A53_CORE0_ENABLE(x) \
45125 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE0_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE0_ENABLE_MASK)
45126#define SRC_A53RCR1_A53_CORE1_ENABLE_MASK (0x2U)
45127#define SRC_A53RCR1_A53_CORE1_ENABLE_SHIFT (1U)
45128/*! A53_CORE1_ENABLE
45129 * 0b0..core1 is disabled
45130 * 0b1..core1 is enabled
45131 */
45132#define SRC_A53RCR1_A53_CORE1_ENABLE(x) \
45133 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE1_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE1_ENABLE_MASK)
45134#define SRC_A53RCR1_A53_CORE2_ENABLE_MASK (0x4U)
45135#define SRC_A53RCR1_A53_CORE2_ENABLE_SHIFT (2U)
45136/*! A53_CORE2_ENABLE
45137 * 0b0..core2 is disabled
45138 * 0b1..core2 is enabled
45139 */
45140#define SRC_A53RCR1_A53_CORE2_ENABLE(x) \
45141 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE2_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE2_ENABLE_MASK)
45142#define SRC_A53RCR1_A53_CORE3_ENABLE_MASK (0x8U)
45143#define SRC_A53RCR1_A53_CORE3_ENABLE_SHIFT (3U)
45144/*! A53_CORE3_ENABLE
45145 * 0b0..core3 is disabled
45146 * 0b1..core3 is enabled
45147 */
45148#define SRC_A53RCR1_A53_CORE3_ENABLE(x) \
45149 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_CORE3_ENABLE_SHIFT)) & SRC_A53RCR1_A53_CORE3_ENABLE_MASK)
45150#define SRC_A53RCR1_A53_RST_SLOW_MASK (0x70U)
45151#define SRC_A53RCR1_A53_RST_SLOW_SHIFT (4U)
45152#define SRC_A53RCR1_A53_RST_SLOW(x) \
45153 (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_A53_RST_SLOW_SHIFT)) & SRC_A53RCR1_A53_RST_SLOW_MASK)
45154#define SRC_A53RCR1_DOMAIN0_MASK (0x1000000U)
45155#define SRC_A53RCR1_DOMAIN0_SHIFT (24U)
45156/*! DOMAIN0
45157 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
45158 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
45159 */
45160#define SRC_A53RCR1_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN0_SHIFT)) & SRC_A53RCR1_DOMAIN0_MASK)
45161#define SRC_A53RCR1_DOMAIN1_MASK (0x2000000U)
45162#define SRC_A53RCR1_DOMAIN1_SHIFT (25U)
45163/*! DOMAIN1
45164 * 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
45165 * 0b1..This register is assigned to domain1. The master from domain1 can write to this register
45166 */
45167#define SRC_A53RCR1_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN1_SHIFT)) & SRC_A53RCR1_DOMAIN1_MASK)
45168#define SRC_A53RCR1_DOMAIN2_MASK (0x4000000U)
45169#define SRC_A53RCR1_DOMAIN2_SHIFT (26U)
45170/*! DOMAIN2
45171 * 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
45172 * 0b1..This register is assigned to domain2. The master from domain2 can write to this register
45173 */
45174#define SRC_A53RCR1_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN2_SHIFT)) & SRC_A53RCR1_DOMAIN2_MASK)
45175#define SRC_A53RCR1_DOMAIN3_MASK (0x8000000U)
45176#define SRC_A53RCR1_DOMAIN3_SHIFT (27U)
45177/*! DOMAIN3
45178 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
45179 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
45180 */
45181#define SRC_A53RCR1_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOMAIN3_SHIFT)) & SRC_A53RCR1_DOMAIN3_MASK)
45182#define SRC_A53RCR1_LOCK_MASK (0x40000000U)
45183#define SRC_A53RCR1_LOCK_SHIFT (30U)
45184/*! LOCK
45185 * 0b0..[31] and [27:24] bits can be modified
45186 * 0b1..[31] and [27:24] bits cannot be modified
45187 */
45188#define SRC_A53RCR1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_LOCK_SHIFT)) & SRC_A53RCR1_LOCK_MASK)
45189#define SRC_A53RCR1_DOM_EN_MASK (0x80000000U)
45190#define SRC_A53RCR1_DOM_EN_SHIFT (31U)
45191/*! DOM_EN
45192 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
45193 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
45194 * the masters from the domains specified in [27:24] area.
45195 */
45196#define SRC_A53RCR1_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_A53RCR1_DOM_EN_SHIFT)) & SRC_A53RCR1_DOM_EN_MASK)
45197/*! @} */
45198
45199/*! @name M7RCR - M7 Reset Control Register */
45200/*! @{ */
45201#define SRC_M7RCR_SW_M7C_NON_SCLR_RST_MASK (0x1U)
45202#define SRC_M7RCR_SW_M7C_NON_SCLR_RST_SHIFT (0U)
45203/*! SW_M7C_NON_SCLR_RST
45204 * 0b0..do not assert M7 core reset
45205 * 0b1..assert M7 core reset
45206 */
45207#define SRC_M7RCR_SW_M7C_NON_SCLR_RST(x) \
45208 (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_SW_M7C_NON_SCLR_RST_SHIFT)) & SRC_M7RCR_SW_M7C_NON_SCLR_RST_MASK)
45209#define SRC_M7RCR_SW_M7C_RST_MASK (0x2U)
45210#define SRC_M7RCR_SW_M7C_RST_SHIFT (1U)
45211/*! SW_M7C_RST
45212 * 0b0..do not assert M7 core reset
45213 * 0b1..assert M7 core reset
45214 */
45215#define SRC_M7RCR_SW_M7C_RST(x) \
45216 (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_SW_M7C_RST_SHIFT)) & SRC_M7RCR_SW_M7C_RST_MASK)
45217#define SRC_M7RCR_ENABLE_M7_MASK (0x8U)
45218#define SRC_M7RCR_ENABLE_M7_SHIFT (3U)
45219/*! ENABLE_M7
45220 * 0b0..M7 is disabled
45221 * 0b1..M7 is enabled
45222 */
45223#define SRC_M7RCR_ENABLE_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_ENABLE_M7_SHIFT)) & SRC_M7RCR_ENABLE_M7_MASK)
45224#define SRC_M7RCR_MASK_WDOG3_RST_MASK (0xF0U)
45225#define SRC_M7RCR_MASK_WDOG3_RST_SHIFT (4U)
45226/*! MASK_WDOG3_RST
45227 * 0b0101..wdog3_rst_b is masked
45228 * 0b1010..wdog3_rst_b is not masked
45229 */
45230#define SRC_M7RCR_MASK_WDOG3_RST(x) \
45231 (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_MASK_WDOG3_RST_SHIFT)) & SRC_M7RCR_MASK_WDOG3_RST_MASK)
45232#define SRC_M7RCR_WDOG3_RST_OPTION_M7_MASK (0x100U)
45233#define SRC_M7RCR_WDOG3_RST_OPTION_M7_SHIFT (8U)
45234/*! WDOG3_RST_OPTION_M7
45235 * 0b0..wdgo3_rst_b Reset M7 core only
45236 * 0b1..Reset both M7 core and platform
45237 */
45238#define SRC_M7RCR_WDOG3_RST_OPTION_M7(x) \
45239 (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_WDOG3_RST_OPTION_M7_SHIFT)) & SRC_M7RCR_WDOG3_RST_OPTION_M7_MASK)
45240#define SRC_M7RCR_WDOG3_RST_OPTION_MASK (0x200U)
45241#define SRC_M7RCR_WDOG3_RST_OPTION_SHIFT (9U)
45242/*! WDOG3_RST_OPTION
45243 * 0b0..Wdog3_rst_b asserts M7 reset
45244 * 0b1..Wdog3_rst_b asserts global reset
45245 */
45246#define SRC_M7RCR_WDOG3_RST_OPTION(x) \
45247 (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_WDOG3_RST_OPTION_SHIFT)) & SRC_M7RCR_WDOG3_RST_OPTION_MASK)
45248#define SRC_M7RCR_DOMAIN0_MASK (0x1000000U)
45249#define SRC_M7RCR_DOMAIN0_SHIFT (24U)
45250/*! DOMAIN0
45251 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
45252 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
45253 */
45254#define SRC_M7RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_DOMAIN0_SHIFT)) & SRC_M7RCR_DOMAIN0_MASK)
45255#define SRC_M7RCR_DOMAIN1_MASK (0x2000000U)
45256#define SRC_M7RCR_DOMAIN1_SHIFT (25U)
45257/*! DOMAIN1
45258 * 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
45259 * 0b1..This register is assigned to domain1. The master from domain1 can write to this register
45260 */
45261#define SRC_M7RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_DOMAIN1_SHIFT)) & SRC_M7RCR_DOMAIN1_MASK)
45262#define SRC_M7RCR_DOMAIN2_MASK (0x4000000U)
45263#define SRC_M7RCR_DOMAIN2_SHIFT (26U)
45264/*! DOMAIN2
45265 * 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
45266 * 0b1..This register is assigned to domain2. The master from domain2 can write to this register
45267 */
45268#define SRC_M7RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_DOMAIN2_SHIFT)) & SRC_M7RCR_DOMAIN2_MASK)
45269#define SRC_M7RCR_DOMAIN3_MASK (0x8000000U)
45270#define SRC_M7RCR_DOMAIN3_SHIFT (27U)
45271/*! DOMAIN3
45272 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
45273 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
45274 */
45275#define SRC_M7RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_DOMAIN3_SHIFT)) & SRC_M7RCR_DOMAIN3_MASK)
45276#define SRC_M7RCR_LOCK_MASK (0x40000000U)
45277#define SRC_M7RCR_LOCK_SHIFT (30U)
45278/*! LOCK
45279 * 0b0..[31] and [27:24] bits can be modified
45280 * 0b1..[31] and [27:24] bits cannot be modified
45281 */
45282#define SRC_M7RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_LOCK_SHIFT)) & SRC_M7RCR_LOCK_MASK)
45283#define SRC_M7RCR_DOM_EN_MASK (0x80000000U)
45284#define SRC_M7RCR_DOM_EN_SHIFT (31U)
45285/*! DOM_EN
45286 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
45287 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
45288 * the masters from the domains specified in [27:24] area.
45289 */
45290#define SRC_M7RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_M7RCR_DOM_EN_SHIFT)) & SRC_M7RCR_DOM_EN_MASK)
45291/*! @} */
45292
45293/*! @name USBOPHY1_RCR - USB OTG PHY1 Reset Control Register */
45294/*! @{ */
45295#define SRC_USBOPHY1_RCR_OTG1_PHY_RESET_MASK (0x1U)
45296#define SRC_USBOPHY1_RCR_OTG1_PHY_RESET_SHIFT (0U)
45297/*! OTG1_PHY_RESET
45298 * 0b0..Don't reset USB OTG1 PHY
45299 * 0b1..Reset USB OTG1 PHY
45300 */
45301#define SRC_USBOPHY1_RCR_OTG1_PHY_RESET(x) \
45302 (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_OTG1_PHY_RESET_SHIFT)) & SRC_USBOPHY1_RCR_OTG1_PHY_RESET_MASK)
45303#define SRC_USBOPHY1_RCR_DOMAIN0_MASK (0x1000000U)
45304#define SRC_USBOPHY1_RCR_DOMAIN0_SHIFT (24U)
45305/*! DOMAIN0
45306 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
45307 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
45308 */
45309#define SRC_USBOPHY1_RCR_DOMAIN0(x) \
45310 (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOMAIN0_SHIFT)) & SRC_USBOPHY1_RCR_DOMAIN0_MASK)
45311#define SRC_USBOPHY1_RCR_DOMAIN1_MASK (0x2000000U)
45312#define SRC_USBOPHY1_RCR_DOMAIN1_SHIFT (25U)
45313/*! DOMAIN1
45314 * 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
45315 * 0b1..This register is assigned to domain1. The master from domain1 can write to this register
45316 */
45317#define SRC_USBOPHY1_RCR_DOMAIN1(x) \
45318 (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOMAIN1_SHIFT)) & SRC_USBOPHY1_RCR_DOMAIN1_MASK)
45319#define SRC_USBOPHY1_RCR_DOMAIN2_MASK (0x4000000U)
45320#define SRC_USBOPHY1_RCR_DOMAIN2_SHIFT (26U)
45321/*! DOMAIN2
45322 * 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
45323 * 0b1..This register is assigned to domain2. The master from domain2 can write to this register
45324 */
45325#define SRC_USBOPHY1_RCR_DOMAIN2(x) \
45326 (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOMAIN2_SHIFT)) & SRC_USBOPHY1_RCR_DOMAIN2_MASK)
45327#define SRC_USBOPHY1_RCR_DOMAIN3_MASK (0x8000000U)
45328#define SRC_USBOPHY1_RCR_DOMAIN3_SHIFT (27U)
45329/*! DOMAIN3
45330 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
45331 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
45332 */
45333#define SRC_USBOPHY1_RCR_DOMAIN3(x) \
45334 (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOMAIN3_SHIFT)) & SRC_USBOPHY1_RCR_DOMAIN3_MASK)
45335#define SRC_USBOPHY1_RCR_LOCK_MASK (0x40000000U)
45336#define SRC_USBOPHY1_RCR_LOCK_SHIFT (30U)
45337/*! LOCK
45338 * 0b0..[31] and [27:24] bits can be modified
45339 * 0b1..[31] and [27:24] bits cannot be modified
45340 */
45341#define SRC_USBOPHY1_RCR_LOCK(x) \
45342 (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_LOCK_SHIFT)) & SRC_USBOPHY1_RCR_LOCK_MASK)
45343#define SRC_USBOPHY1_RCR_DOM_EN_MASK (0x80000000U)
45344#define SRC_USBOPHY1_RCR_DOM_EN_SHIFT (31U)
45345/*! DOM_EN
45346 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
45347 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
45348 * the masters from the domains specified in [27:24] area.
45349 */
45350#define SRC_USBOPHY1_RCR_DOM_EN(x) \
45351 (((uint32_t)(((uint32_t)(x)) << SRC_USBOPHY1_RCR_DOM_EN_SHIFT)) & SRC_USBOPHY1_RCR_DOM_EN_MASK)
45352/*! @} */
45353
45354/*! @name MIPIPHY_RCR - MIPI PHY Reset Control Register */
45355/*! @{ */
45356#define SRC_MIPIPHY_RCR_DOMAIN0_MASK (0x1000000U)
45357#define SRC_MIPIPHY_RCR_DOMAIN0_SHIFT (24U)
45358/*! DOMAIN0
45359 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
45360 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
45361 */
45362#define SRC_MIPIPHY_RCR_DOMAIN0(x) \
45363 (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOMAIN0_SHIFT)) & SRC_MIPIPHY_RCR_DOMAIN0_MASK)
45364#define SRC_MIPIPHY_RCR_DOMAIN1_MASK (0x2000000U)
45365#define SRC_MIPIPHY_RCR_DOMAIN1_SHIFT (25U)
45366/*! DOMAIN1
45367 * 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
45368 * 0b1..This register is assigned to domain1. The master from domain1 can write to this register
45369 */
45370#define SRC_MIPIPHY_RCR_DOMAIN1(x) \
45371 (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOMAIN1_SHIFT)) & SRC_MIPIPHY_RCR_DOMAIN1_MASK)
45372#define SRC_MIPIPHY_RCR_DOMAIN2_MASK (0x4000000U)
45373#define SRC_MIPIPHY_RCR_DOMAIN2_SHIFT (26U)
45374/*! DOMAIN2
45375 * 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
45376 * 0b1..This register is assigned to domain2. The master from domain2 can write to this register
45377 */
45378#define SRC_MIPIPHY_RCR_DOMAIN2(x) \
45379 (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOMAIN2_SHIFT)) & SRC_MIPIPHY_RCR_DOMAIN2_MASK)
45380#define SRC_MIPIPHY_RCR_DOMAIN3_MASK (0x8000000U)
45381#define SRC_MIPIPHY_RCR_DOMAIN3_SHIFT (27U)
45382/*! DOMAIN3
45383 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
45384 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
45385 */
45386#define SRC_MIPIPHY_RCR_DOMAIN3(x) \
45387 (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOMAIN3_SHIFT)) & SRC_MIPIPHY_RCR_DOMAIN3_MASK)
45388#define SRC_MIPIPHY_RCR_LOCK_MASK (0x40000000U)
45389#define SRC_MIPIPHY_RCR_LOCK_SHIFT (30U)
45390/*! LOCK
45391 * 0b0..[31] and [27:24] bits can be modified
45392 * 0b1..[31] and [27:24] bits cannot be modified
45393 */
45394#define SRC_MIPIPHY_RCR_LOCK(x) \
45395 (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_LOCK_SHIFT)) & SRC_MIPIPHY_RCR_LOCK_MASK)
45396#define SRC_MIPIPHY_RCR_DOM_EN_MASK (0x80000000U)
45397#define SRC_MIPIPHY_RCR_DOM_EN_SHIFT (31U)
45398/*! DOM_EN
45399 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
45400 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
45401 * the masters from the domains specified in [27:24] area.
45402 */
45403#define SRC_MIPIPHY_RCR_DOM_EN(x) \
45404 (((uint32_t)(((uint32_t)(x)) << SRC_MIPIPHY_RCR_DOM_EN_SHIFT)) & SRC_MIPIPHY_RCR_DOM_EN_MASK)
45405/*! @} */
45406
45407/*! @name DISP_RCR - DISPLAY Reset Control Register */
45408/*! @{ */
45409#define SRC_DISP_RCR_DISP_RESET_MASK (0x1U)
45410#define SRC_DISP_RCR_DISP_RESET_SHIFT (0U)
45411/*! DISP_RESET
45412 * 0b0..Don't reset dispmix
45413 * 0b1..Reset dispmix
45414 */
45415#define SRC_DISP_RCR_DISP_RESET(x) \
45416 (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DISP_RESET_SHIFT)) & SRC_DISP_RCR_DISP_RESET_MASK)
45417#define SRC_DISP_RCR_DOMAIN0_MASK (0x1000000U)
45418#define SRC_DISP_RCR_DOMAIN0_SHIFT (24U)
45419/*! DOMAIN0
45420 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
45421 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
45422 */
45423#define SRC_DISP_RCR_DOMAIN0(x) \
45424 (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOMAIN0_SHIFT)) & SRC_DISP_RCR_DOMAIN0_MASK)
45425#define SRC_DISP_RCR_DOMAIN1_MASK (0x2000000U)
45426#define SRC_DISP_RCR_DOMAIN1_SHIFT (25U)
45427/*! DOMAIN1
45428 * 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
45429 * 0b1..This register is assigned to domain1. The master from domain1 can write to this register
45430 */
45431#define SRC_DISP_RCR_DOMAIN1(x) \
45432 (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOMAIN1_SHIFT)) & SRC_DISP_RCR_DOMAIN1_MASK)
45433#define SRC_DISP_RCR_DOMAIN2_MASK (0x4000000U)
45434#define SRC_DISP_RCR_DOMAIN2_SHIFT (26U)
45435/*! DOMAIN2
45436 * 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
45437 * 0b1..This register is assigned to domain2. The master from domain2 can write to this register
45438 */
45439#define SRC_DISP_RCR_DOMAIN2(x) \
45440 (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOMAIN2_SHIFT)) & SRC_DISP_RCR_DOMAIN2_MASK)
45441#define SRC_DISP_RCR_DOMAIN3_MASK (0x8000000U)
45442#define SRC_DISP_RCR_DOMAIN3_SHIFT (27U)
45443/*! DOMAIN3
45444 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
45445 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
45446 */
45447#define SRC_DISP_RCR_DOMAIN3(x) \
45448 (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOMAIN3_SHIFT)) & SRC_DISP_RCR_DOMAIN3_MASK)
45449#define SRC_DISP_RCR_LOCK_MASK (0x40000000U)
45450#define SRC_DISP_RCR_LOCK_SHIFT (30U)
45451/*! LOCK
45452 * 0b0..[31] and [27:24] bits can be modified
45453 * 0b1..[31] and [27:24] bits cannot be modified
45454 */
45455#define SRC_DISP_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_LOCK_SHIFT)) & SRC_DISP_RCR_LOCK_MASK)
45456#define SRC_DISP_RCR_DOM_EN_MASK (0x80000000U)
45457#define SRC_DISP_RCR_DOM_EN_SHIFT (31U)
45458/*! DOM_EN
45459 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
45460 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
45461 * the masters from the domains specified in [27:24] area.
45462 */
45463#define SRC_DISP_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DISP_RCR_DOM_EN_SHIFT)) & SRC_DISP_RCR_DOM_EN_MASK)
45464/*! @} */
45465
45466/*! @name GPU_RCR - GPU Reset Control Register */
45467/*! @{ */
45468#define SRC_GPU_RCR_GPU_RESET_MASK (0x1U)
45469#define SRC_GPU_RCR_GPU_RESET_SHIFT (0U)
45470#define SRC_GPU_RCR_GPU_RESET(x) \
45471 (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_GPU_RESET_SHIFT)) & SRC_GPU_RCR_GPU_RESET_MASK)
45472#define SRC_GPU_RCR_DOMAIN0_MASK (0x1000000U)
45473#define SRC_GPU_RCR_DOMAIN0_SHIFT (24U)
45474/*! DOMAIN0
45475 * 0b0..This register is not assigned to domain0. The master from domain3 cannot write to this register.
45476 * 0b1..This register is assigned to domain0. The master from domain3 can write to this register
45477 */
45478#define SRC_GPU_RCR_DOMAIN0(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN0_SHIFT)) & SRC_GPU_RCR_DOMAIN0_MASK)
45479#define SRC_GPU_RCR_DOMAIN1_MASK (0x2000000U)
45480#define SRC_GPU_RCR_DOMAIN1_SHIFT (25U)
45481/*! DOMAIN1
45482 * 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
45483 * 0b1..This register is assigned to domain1. The master from domain1 can write to this register
45484 */
45485#define SRC_GPU_RCR_DOMAIN1(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN1_SHIFT)) & SRC_GPU_RCR_DOMAIN1_MASK)
45486#define SRC_GPU_RCR_DOMAIN2_MASK (0x4000000U)
45487#define SRC_GPU_RCR_DOMAIN2_SHIFT (26U)
45488/*! DOMAIN2
45489 * 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
45490 * 0b1..This register is assigned to domain2. The master from domain2 can write to this register
45491 */
45492#define SRC_GPU_RCR_DOMAIN2(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN2_SHIFT)) & SRC_GPU_RCR_DOMAIN2_MASK)
45493#define SRC_GPU_RCR_DOMAIN3_MASK (0x8000000U)
45494#define SRC_GPU_RCR_DOMAIN3_SHIFT (27U)
45495/*! DOMAIN3
45496 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
45497 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
45498 */
45499#define SRC_GPU_RCR_DOMAIN3(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOMAIN3_SHIFT)) & SRC_GPU_RCR_DOMAIN3_MASK)
45500#define SRC_GPU_RCR_LOCK_MASK (0x40000000U)
45501#define SRC_GPU_RCR_LOCK_SHIFT (30U)
45502/*! LOCK
45503 * 0b0..[31] and [27:24] bits can be modified
45504 * 0b1..[31] and [27:24] bits cannot be modified
45505 */
45506#define SRC_GPU_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_LOCK_SHIFT)) & SRC_GPU_RCR_LOCK_MASK)
45507#define SRC_GPU_RCR_DOM_EN_MASK (0x80000000U)
45508#define SRC_GPU_RCR_DOM_EN_SHIFT (31U)
45509/*! DOM_EN
45510 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
45511 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
45512 * the masters from the domains specified in [27:24] area.
45513 */
45514#define SRC_GPU_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPU_RCR_DOM_EN_SHIFT)) & SRC_GPU_RCR_DOM_EN_MASK)
45515/*! @} */
45516
45517/*! @name SBMR1 - SRC Boot Mode Register 1 */
45518/*! @{ */
45519#define SRC_SBMR1_BOOT_CFG_MASK (0xFFFFFU)
45520#define SRC_SBMR1_BOOT_CFG_SHIFT (0U)
45521#define SRC_SBMR1_BOOT_CFG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG_SHIFT)) & SRC_SBMR1_BOOT_CFG_MASK)
45522/*! @} */
45523
45524/*! @name SRSR - SRC Reset Status Register */
45525/*! @{ */
45526#define SRC_SRSR_ipp_reset_b_MASK (0x1U)
45527#define SRC_SRSR_ipp_reset_b_SHIFT (0U)
45528/*! ipp_reset_b
45529 * 0b0..Reset is not a result of ipp_reset_b pin.
45530 * 0b1..Reset is a result of ipp_reset_b pin.
45531 */
45532#define SRC_SRSR_ipp_reset_b(x) \
45533 (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_ipp_reset_b_SHIFT)) & SRC_SRSR_ipp_reset_b_MASK)
45534#define SRC_SRSR_csu_reset_b_MASK (0x4U)
45535#define SRC_SRSR_csu_reset_b_SHIFT (2U)
45536/*! csu_reset_b
45537 * 0b0..Reset is not a result of the csu_reset_b event.
45538 * 0b1..Reset is a result of the csu_reset_b event.
45539 */
45540#define SRC_SRSR_csu_reset_b(x) \
45541 (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_csu_reset_b_SHIFT)) & SRC_SRSR_csu_reset_b_MASK)
45542#define SRC_SRSR_ipp_user_reset_b_MASK (0x8U)
45543#define SRC_SRSR_ipp_user_reset_b_SHIFT (3U)
45544/*! ipp_user_reset_b
45545 * 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
45546 * 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
45547 */
45548#define SRC_SRSR_ipp_user_reset_b(x) \
45549 (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_ipp_user_reset_b_SHIFT)) & SRC_SRSR_ipp_user_reset_b_MASK)
45550#define SRC_SRSR_wdog1_rst_b_MASK (0x10U)
45551#define SRC_SRSR_wdog1_rst_b_SHIFT (4U)
45552/*! wdog1_rst_b
45553 * 0b0..Reset is not a result of the watchdog1 time-out event.
45554 * 0b1..Reset is a result of the watchdog1 time-out event.
45555 */
45556#define SRC_SRSR_wdog1_rst_b(x) \
45557 (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_wdog1_rst_b_SHIFT)) & SRC_SRSR_wdog1_rst_b_MASK)
45558#define SRC_SRSR_jtag_rst_b_MASK (0x20U)
45559#define SRC_SRSR_jtag_rst_b_SHIFT (5U)
45560/*! jtag_rst_b
45561 * 0b0..Reset is not a result of HIGH-Z reset from JTAG.
45562 * 0b1..Reset is a result of HIGH-Z reset from JTAG.
45563 */
45564#define SRC_SRSR_jtag_rst_b(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_jtag_rst_b_SHIFT)) & SRC_SRSR_jtag_rst_b_MASK)
45565#define SRC_SRSR_jtag_sw_rst_MASK (0x40U)
45566#define SRC_SRSR_jtag_sw_rst_SHIFT (6U)
45567/*! jtag_sw_rst
45568 * 0b0..Reset is not a result of software reset from JTAG.
45569 * 0b1..Reset is a result of software reset from JTAG.
45570 */
45571#define SRC_SRSR_jtag_sw_rst(x) \
45572 (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_jtag_sw_rst_SHIFT)) & SRC_SRSR_jtag_sw_rst_MASK)
45573#define SRC_SRSR_wdog3_rst_b_MASK (0x80U)
45574#define SRC_SRSR_wdog3_rst_b_SHIFT (7U)
45575/*! wdog3_rst_b
45576 * 0b0..Reset is not a result of the watchdog3 time-out event.
45577 * 0b1..Reset is a result of the watchdog3 time-out event.
45578 */
45579#define SRC_SRSR_wdog3_rst_b(x) \
45580 (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_wdog3_rst_b_SHIFT)) & SRC_SRSR_wdog3_rst_b_MASK)
45581#define SRC_SRSR_wdog2_rst_b_MASK (0x100U)
45582#define SRC_SRSR_wdog2_rst_b_SHIFT (8U)
45583/*! wdog2_rst_b
45584 * 0b0..Reset is not a result of the watchdog4 time-out event.
45585 * 0b1..Reset is a result of the watchdog4 time-out event.
45586 */
45587#define SRC_SRSR_wdog2_rst_b(x) \
45588 (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_wdog2_rst_b_SHIFT)) & SRC_SRSR_wdog2_rst_b_MASK)
45589#define SRC_SRSR_tempsense_rst_b_MASK (0x200U)
45590#define SRC_SRSR_tempsense_rst_b_SHIFT (9U)
45591/*! tempsense_rst_b
45592 * 0b0..Reset is not a result of software reset from Temperature Sensor.
45593 * 0b1..Reset is a result of software reset from Temperature Sensor.
45594 */
45595#define SRC_SRSR_tempsense_rst_b(x) \
45596 (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_tempsense_rst_b_SHIFT)) & SRC_SRSR_tempsense_rst_b_MASK)
45597/*! @} */
45598
45599/*! @name SISR - SRC Interrupt Status Register */
45600/*! @{ */
45601#define SRC_SISR_OTGPHY1_PASSED_RESET_MASK (0x4U)
45602#define SRC_SISR_OTGPHY1_PASSED_RESET_SHIFT (2U)
45603/*! OTGPHY1_PASSED_RESET
45604 * 0b0..Interrupt generated not due to OTG PHY1 passed reset
45605 * 0b1..Interrupt generated due to OTG PHY1 passed reset
45606 */
45607#define SRC_SISR_OTGPHY1_PASSED_RESET(x) \
45608 (((uint32_t)(((uint32_t)(x)) << SRC_SISR_OTGPHY1_PASSED_RESET_SHIFT)) & SRC_SISR_OTGPHY1_PASSED_RESET_MASK)
45609#define SRC_SISR_DISPLAY_PASSED_RESET_MASK (0x80U)
45610#define SRC_SISR_DISPLAY_PASSED_RESET_SHIFT (7U)
45611/*! DISPLAY_PASSED_RESET
45612 * 0b0..Interrupt generated not due to DISPLAY passed reset
45613 * 0b1..Interrupt generated due to DISPLAY passed reset
45614 */
45615#define SRC_SISR_DISPLAY_PASSED_RESET(x) \
45616 (((uint32_t)(((uint32_t)(x)) << SRC_SISR_DISPLAY_PASSED_RESET_SHIFT)) & SRC_SISR_DISPLAY_PASSED_RESET_MASK)
45617#define SRC_SISR_M7_PASSED_RESET_MASK (0x100U)
45618#define SRC_SISR_M7_PASSED_RESET_SHIFT (8U)
45619/*! M7_PASSED_RESET
45620 * 0b0..interrupt generated not due to m7 reset
45621 * 0b1..interrupt generated due to m7 reset
45622 */
45623#define SRC_SISR_M7_PASSED_RESET(x) \
45624 (((uint32_t)(((uint32_t)(x)) << SRC_SISR_M7_PASSED_RESET_SHIFT)) & SRC_SISR_M7_PASSED_RESET_MASK)
45625#define SRC_SISR_GPU_PASSED_RESET_MASK (0x400U)
45626#define SRC_SISR_GPU_PASSED_RESET_SHIFT (10U)
45627/*! GPU_PASSED_RESET
45628 * 0b0..interrupt generated not due to GPU reset
45629 * 0b1..interrupt generated due to GPU reset
45630 */
45631#define SRC_SISR_GPU_PASSED_RESET(x) \
45632 (((uint32_t)(((uint32_t)(x)) << SRC_SISR_GPU_PASSED_RESET_SHIFT)) & SRC_SISR_GPU_PASSED_RESET_MASK)
45633/*! @} */
45634
45635/*! @name SIMR - SRC Interrupt Mask Register */
45636/*! @{ */
45637#define SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_MASK (0x4U)
45638#define SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_SHIFT (2U)
45639/*! MASK_OTGPHY1_PASSED_RESET
45640 * 0b0..do not mask interrupt due to OTG PHY1 passed reset - interrupt will be created
45641 * 0b1..mask interrupt due to OTG PHY1 passed reset
45642 */
45643#define SRC_SIMR_MASK_OTGPHY1_PASSED_RESET(x) \
45644 (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_SHIFT)) & \
45645 SRC_SIMR_MASK_OTGPHY1_PASSED_RESET_MASK)
45646#define SRC_SIMR_MASK_DISPLAY_PASSED_RESET_MASK (0x80U)
45647#define SRC_SIMR_MASK_DISPLAY_PASSED_RESET_SHIFT (7U)
45648/*! MASK_DISPLAY_PASSED_RESET
45649 * 0b0..do not mask interrupt due to display passed reset - interrupt will be created
45650 * 0b1..mask interrupt due to display passed reset
45651 */
45652#define SRC_SIMR_MASK_DISPLAY_PASSED_RESET(x) \
45653 (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_DISPLAY_PASSED_RESET_SHIFT)) & \
45654 SRC_SIMR_MASK_DISPLAY_PASSED_RESET_MASK)
45655#define SRC_SIMR_MASK_M7_PASSED_RESET_MASK (0x100U)
45656#define SRC_SIMR_MASK_M7_PASSED_RESET_SHIFT (8U)
45657/*! MASK_M7_PASSED_RESET
45658 * 0b0..do not mask interrupt due to m7 passed reset - interrupt will be created
45659 * 0b1..mask interrupt due to m7 passed reset
45660 */
45661#define SRC_SIMR_MASK_M7_PASSED_RESET(x) \
45662 (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_M7_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_M7_PASSED_RESET_MASK)
45663#define SRC_SIMR_MASK_GPU_PASSED_RESET_MASK (0x400U)
45664#define SRC_SIMR_MASK_GPU_PASSED_RESET_SHIFT (10U)
45665/*! MASK_GPU_PASSED_RESET
45666 * 0b0..do not mask interrupt due to GPU passed reset - interrupt will be created
45667 * 0b1..mask interrupt due to GPU passed reset
45668 */
45669#define SRC_SIMR_MASK_GPU_PASSED_RESET(x) \
45670 (((uint32_t)(((uint32_t)(x)) << SRC_SIMR_MASK_GPU_PASSED_RESET_SHIFT)) & SRC_SIMR_MASK_GPU_PASSED_RESET_MASK)
45671/*! @} */
45672
45673/*! @name SBMR2 - SRC Boot Mode Register 2 */
45674/*! @{ */
45675#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U)
45676#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U)
45677#define SRC_SBMR2_SEC_CONFIG(x) \
45678 (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)
45679#define SRC_SBMR2_DIR_BT_DIS_MASK (0x8U)
45680#define SRC_SBMR2_DIR_BT_DIS_SHIFT (3U)
45681#define SRC_SBMR2_DIR_BT_DIS(x) \
45682 (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_DIR_BT_DIS_SHIFT)) & SRC_SBMR2_DIR_BT_DIS_MASK)
45683#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)
45684#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)
45685#define SRC_SBMR2_BT_FUSE_SEL(x) \
45686 (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)
45687#define SRC_SBMR2_FORCE_COLD_BOOT_MASK (0xE0U)
45688#define SRC_SBMR2_FORCE_COLD_BOOT_SHIFT (5U)
45689#define SRC_SBMR2_FORCE_COLD_BOOT(x) \
45690 (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_FORCE_COLD_BOOT_SHIFT)) & SRC_SBMR2_FORCE_COLD_BOOT_MASK)
45691#define SRC_SBMR2_IPP_BOOT_MODE_MASK (0x3F000000U)
45692#define SRC_SBMR2_IPP_BOOT_MODE_SHIFT (24U)
45693#define SRC_SBMR2_IPP_BOOT_MODE(x) \
45694 (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_IPP_BOOT_MODE_SHIFT)) & SRC_SBMR2_IPP_BOOT_MODE_MASK)
45695/*! @} */
45696
45697/*! @name GPR1 - SRC General Purpose Register 1 */
45698/*! @{ */
45699#define SRC_GPR1_C0_START_ADDRH_MASK (0xFFFFU)
45700#define SRC_GPR1_C0_START_ADDRH_SHIFT (0U)
45701#define SRC_GPR1_C0_START_ADDRH(x) \
45702 (((uint32_t)(((uint32_t)(x)) << SRC_GPR1_C0_START_ADDRH_SHIFT)) & SRC_GPR1_C0_START_ADDRH_MASK)
45703/*! @} */
45704
45705/*! @name GPR2 - SRC General Purpose Register 2 */
45706/*! @{ */
45707#define SRC_GPR2_C0_START_ADDRL_MASK (0x3FFFFFU)
45708#define SRC_GPR2_C0_START_ADDRL_SHIFT (0U)
45709#define SRC_GPR2_C0_START_ADDRL(x) \
45710 (((uint32_t)(((uint32_t)(x)) << SRC_GPR2_C0_START_ADDRL_SHIFT)) & SRC_GPR2_C0_START_ADDRL_MASK)
45711/*! @} */
45712
45713/*! @name GPR3 - SRC General Purpose Register 3 */
45714/*! @{ */
45715#define SRC_GPR3_C1_START_ADDRH_MASK (0xFFFFU)
45716#define SRC_GPR3_C1_START_ADDRH_SHIFT (0U)
45717#define SRC_GPR3_C1_START_ADDRH(x) \
45718 (((uint32_t)(((uint32_t)(x)) << SRC_GPR3_C1_START_ADDRH_SHIFT)) & SRC_GPR3_C1_START_ADDRH_MASK)
45719/*! @} */
45720
45721/*! @name GPR4 - SRC General Purpose Register 4 */
45722/*! @{ */
45723#define SRC_GPR4_C1_START_ADDRL_MASK (0x3FFFFFU)
45724#define SRC_GPR4_C1_START_ADDRL_SHIFT (0U)
45725#define SRC_GPR4_C1_START_ADDRL(x) \
45726 (((uint32_t)(((uint32_t)(x)) << SRC_GPR4_C1_START_ADDRL_SHIFT)) & SRC_GPR4_C1_START_ADDRL_MASK)
45727/*! @} */
45728
45729/*! @name GPR5 - SRC General Purpose Register 5 */
45730/*! @{ */
45731#define SRC_GPR5_C2_START_ADDRH_MASK (0xFFFFU)
45732#define SRC_GPR5_C2_START_ADDRH_SHIFT (0U)
45733#define SRC_GPR5_C2_START_ADDRH(x) \
45734 (((uint32_t)(((uint32_t)(x)) << SRC_GPR5_C2_START_ADDRH_SHIFT)) & SRC_GPR5_C2_START_ADDRH_MASK)
45735/*! @} */
45736
45737/*! @name GPR6 - SRC General Purpose Register 6 */
45738/*! @{ */
45739#define SRC_GPR6_C2_START_ADDRL_MASK (0x3FFFFFU)
45740#define SRC_GPR6_C2_START_ADDRL_SHIFT (0U)
45741#define SRC_GPR6_C2_START_ADDRL(x) \
45742 (((uint32_t)(((uint32_t)(x)) << SRC_GPR6_C2_START_ADDRL_SHIFT)) & SRC_GPR6_C2_START_ADDRL_MASK)
45743/*! @} */
45744
45745/*! @name GPR7 - SRC General Purpose Register 7 */
45746/*! @{ */
45747#define SRC_GPR7_C3_START_ADDRH_MASK (0xFFFFU)
45748#define SRC_GPR7_C3_START_ADDRH_SHIFT (0U)
45749#define SRC_GPR7_C3_START_ADDRH(x) \
45750 (((uint32_t)(((uint32_t)(x)) << SRC_GPR7_C3_START_ADDRH_SHIFT)) & SRC_GPR7_C3_START_ADDRH_MASK)
45751/*! @} */
45752
45753/*! @name GPR8 - SRC General Purpose Register 8 */
45754/*! @{ */
45755#define SRC_GPR8_C3_START_ADDRL_MASK (0x3FFFFFU)
45756#define SRC_GPR8_C3_START_ADDRL_SHIFT (0U)
45757#define SRC_GPR8_C3_START_ADDRL(x) \
45758 (((uint32_t)(((uint32_t)(x)) << SRC_GPR8_C3_START_ADDRL_SHIFT)) & SRC_GPR8_C3_START_ADDRL_MASK)
45759/*! @} */
45760
45761/*! @name DDRC_RCR - SRC DDR Controller Reset Control Register */
45762/*! @{ */
45763#define SRC_DDRC_RCR_DDRC1_PRST_MASK (0x1U)
45764#define SRC_DDRC_RCR_DDRC1_PRST_SHIFT (0U)
45765/*! DDRC1_PRST
45766 * 0b0..De-assert DDR Controller preset and DDR PHY reset reset
45767 * 0b1..Assert DDR Controller preset and DDR PHY reset
45768 */
45769#define SRC_DDRC_RCR_DDRC1_PRST(x) \
45770 (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PRST_SHIFT)) & SRC_DDRC_RCR_DDRC1_PRST_MASK)
45771#define SRC_DDRC_RCR_DDRC1_CORE_RST_MASK (0x2U)
45772#define SRC_DDRC_RCR_DDRC1_CORE_RST_SHIFT (1U)
45773/*! DDRC1_CORE_RST
45774 * 0b0..De-assert DDR controller aresetn and core_ddrc_rstn
45775 * 0b1..Assert DDR Controller preset and DDR PHY reset
45776 */
45777#define SRC_DDRC_RCR_DDRC1_CORE_RST(x) \
45778 (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_CORE_RST_SHIFT)) & SRC_DDRC_RCR_DDRC1_CORE_RST_MASK)
45779#define SRC_DDRC_RCR_DDRC1_PHY_RESET_MASK (0x4U)
45780#define SRC_DDRC_RCR_DDRC1_PHY_RESET_SHIFT (2U)
45781/*! DDRC1_PHY_RESET
45782 * 0b0..De-assert DDR controller
45783 * 0b1..Assert DDR Controller
45784 */
45785#define SRC_DDRC_RCR_DDRC1_PHY_RESET(x) \
45786 (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PHY_RESET_SHIFT)) & SRC_DDRC_RCR_DDRC1_PHY_RESET_MASK)
45787#define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_MASK (0x8U)
45788#define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_SHIFT (3U)
45789/*! DDRC1_PHY_PWROKIN
45790 * 0b0..De-assert DDR controller
45791 * 0b1..Assert DDR Controller
45792 */
45793#define SRC_DDRC_RCR_DDRC1_PHY_PWROKIN(x) \
45794 (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_SHIFT)) & SRC_DDRC_RCR_DDRC1_PHY_PWROKIN_MASK)
45795#define SRC_DDRC_RCR_DDRC1_SYS_RST_MASK (0x10U)
45796#define SRC_DDRC_RCR_DDRC1_SYS_RST_SHIFT (4U)
45797#define SRC_DDRC_RCR_DDRC1_SYS_RST(x) \
45798 (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_SYS_RST_SHIFT)) & SRC_DDRC_RCR_DDRC1_SYS_RST_MASK)
45799#define SRC_DDRC_RCR_DDRC1_PHY_WRST_MASK (0x20U)
45800#define SRC_DDRC_RCR_DDRC1_PHY_WRST_SHIFT (5U)
45801#define SRC_DDRC_RCR_DDRC1_PHY_WRST(x) \
45802 (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DDRC1_PHY_WRST_SHIFT)) & SRC_DDRC_RCR_DDRC1_PHY_WRST_MASK)
45803#define SRC_DDRC_RCR_DOMAIN0_MASK (0x1000000U)
45804#define SRC_DDRC_RCR_DOMAIN0_SHIFT (24U)
45805/*! DOMAIN0
45806 * 0b0..This register is not assigned to domain0. The master from domain0 cannot write to this register.
45807 * 0b1..This register is assigned to domain0. The master from domain0 can write to this register
45808 */
45809#define SRC_DDRC_RCR_DOMAIN0(x) \
45810 (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN0_SHIFT)) & SRC_DDRC_RCR_DOMAIN0_MASK)
45811#define SRC_DDRC_RCR_DOMAIN1_MASK (0x2000000U)
45812#define SRC_DDRC_RCR_DOMAIN1_SHIFT (25U)
45813/*! DOMAIN1
45814 * 0b0..This register is not assigned to domain1. The master from domain1 cannot write to this register.
45815 * 0b1..This register is assigned to domain1. The master from domain1 can write to this register
45816 */
45817#define SRC_DDRC_RCR_DOMAIN1(x) \
45818 (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN1_SHIFT)) & SRC_DDRC_RCR_DOMAIN1_MASK)
45819#define SRC_DDRC_RCR_DOMAIN2_MASK (0x4000000U)
45820#define SRC_DDRC_RCR_DOMAIN2_SHIFT (26U)
45821/*! DOMAIN2
45822 * 0b0..This register is not assigned to domain2. The master from domain2 cannot write to this register.
45823 * 0b1..This register is assigned to domain2. The master from domain2 can write to this register
45824 */
45825#define SRC_DDRC_RCR_DOMAIN2(x) \
45826 (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN2_SHIFT)) & SRC_DDRC_RCR_DOMAIN2_MASK)
45827#define SRC_DDRC_RCR_DOMAIN3_MASK (0x8000000U)
45828#define SRC_DDRC_RCR_DOMAIN3_SHIFT (27U)
45829/*! DOMAIN3
45830 * 0b0..This register is not assigned to domain3. The master from domain3 cannot write to this register.
45831 * 0b1..This register is assigned to domain3. The master from domain3 can write to this register
45832 */
45833#define SRC_DDRC_RCR_DOMAIN3(x) \
45834 (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOMAIN3_SHIFT)) & SRC_DDRC_RCR_DOMAIN3_MASK)
45835#define SRC_DDRC_RCR_LOCK_MASK (0x40000000U)
45836#define SRC_DDRC_RCR_LOCK_SHIFT (30U)
45837/*! LOCK
45838 * 0b0..[31] and [27:24] bits can be modified
45839 * 0b1..[31] and [27:24] bits cannot be modified
45840 */
45841#define SRC_DDRC_RCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_LOCK_SHIFT)) & SRC_DDRC_RCR_LOCK_MASK)
45842#define SRC_DDRC_RCR_DOM_EN_MASK (0x80000000U)
45843#define SRC_DDRC_RCR_DOM_EN_SHIFT (31U)
45844/*! DOM_EN
45845 * 0b0..Disables domain control. All of this register's bits except [31:30] and [27:24] can be modified by any masters
45846 * 0b1..Enables domain control. All of this register's bits except [31:30] and [27:24] can only be modified by
45847 * the masters from the domains specified in [27:24] area.
45848 */
45849#define SRC_DDRC_RCR_DOM_EN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DDRC_RCR_DOM_EN_SHIFT)) & SRC_DDRC_RCR_DOM_EN_MASK)
45850/*! @} */
45851
45852/*!
45853 * @}
45854 */ /* end of group SRC_Register_Masks */
45855
45856/* SRC - Peripheral instance base addresses */
45857/** Peripheral SRC base address */
45858#define SRC_BASE (0x30390000u)
45859/** Peripheral SRC base pointer */
45860#define SRC ((SRC_Type *)SRC_BASE)
45861/** Array initializer of SRC peripheral base addresses */
45862#define SRC_BASE_ADDRS \
45863 { \
45864 SRC_BASE \
45865 }
45866/** Array initializer of SRC peripheral base pointers */
45867#define SRC_BASE_PTRS \
45868 { \
45869 SRC \
45870 }
45871
45872/*!
45873 * @}
45874 */ /* end of group SRC_Peripheral_Access_Layer */
45875
45876/* ----------------------------------------------------------------------------
45877 -- TMU Peripheral Access Layer
45878 ---------------------------------------------------------------------------- */
45879
45880/*!
45881 * @addtogroup TMU_Peripheral_Access_Layer TMU Peripheral Access Layer
45882 * @{
45883 */
45884
45885/** TMU - Register Layout Typedef */
45886typedef struct
45887{
45888 __IO uint32_t TER; /**< TMU Enable Register, offset: 0x0 */
45889 __I uint32_t TSR; /**< TMU Status register, offset: 0x4 */
45890 __IO uint32_t TIER; /**< TMU Interrupt Enable register, offset: 0x8 */
45891 __IO uint32_t TIDR; /**< TMU Interrupt Detect register, offset: 0xC */
45892 __IO uint32_t TMHTITR; /**< TMU Monitor High Temperature Immediate Threshold register, offset: 0x10 */
45893 __IO uint32_t TMHTATR; /**< TMU Monitor High Temperature Average threshold register, offset: 0x14 */
45894 __IO uint32_t TMHTACTR; /**< TMU Monitor High Temperature Average Critical Threshold register, offset: 0x18 */
45895 __I uint32_t TSCR; /**< TMU Sensor Calibration register, offset: 0x1C */
45896 __I uint32_t TRITSR; /**< TMU Report Immediate Temperature Site register n, offset: 0x20 */
45897 __I uint32_t TRATSR; /**< TMU Report Average Temperature Site register n, offset: 0x24 */
45898} TMU_Type;
45899
45900/* ----------------------------------------------------------------------------
45901 -- TMU Register Masks
45902 ---------------------------------------------------------------------------- */
45903
45904/*!
45905 * @addtogroup TMU_Register_Masks TMU Register Masks
45906 * @{
45907 */
45908
45909/*! @name TER - TMU Enable Register */
45910/*! @{ */
45911#define TMU_TER_ALPF_MASK (0x3U)
45912#define TMU_TER_ALPF_SHIFT (0U)
45913/*! ALPF
45914 * 0b00..1.0
45915 * 0b01..0.5
45916 * 0b10..0.25
45917 * 0b11..0.125
45918 */
45919#define TMU_TER_ALPF(x) (((uint32_t)(((uint32_t)(x)) << TMU_TER_ALPF_SHIFT)) & TMU_TER_ALPF_MASK)
45920#define TMU_TER_EN_MASK (0x80000000U)
45921#define TMU_TER_EN_SHIFT (31U)
45922/*! EN
45923 * 0b0..No monitoring
45924 * 0b1..Enable monitoring
45925 */
45926#define TMU_TER_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TER_EN_SHIFT)) & TMU_TER_EN_MASK)
45927/*! @} */
45928
45929/*! @name TSR - TMU Status register */
45930/*! @{ */
45931#define TMU_TSR_TB_MASK (0x80000000U)
45932#define TMU_TSR_TB_SHIFT (31U)
45933/*! TB
45934 * 0b0..TMU idle.
45935 * 0b1..TMU busy. In monitoring mode this indicates a temperature measurement is pending. In calibration mode,
45936 * sensor result has not yet been determined based on last given ambient temperature.
45937 */
45938#define TMU_TSR_TB(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSR_TB_SHIFT)) & TMU_TSR_TB_MASK)
45939/*! @} */
45940
45941/*! @name TIER - TMU Interrupt Enable register */
45942/*! @{ */
45943#define TMU_TIER_ATCTEIE_MASK (0x20000000U)
45944#define TMU_TIER_ATCTEIE_SHIFT (29U)
45945/*! ATCTEIE
45946 * 0b0..Disabled.
45947 * 0b1..Interrupt enabled. Generate an interrupt if TIDR[ATCTE] is set. Write 1 to this bit will clear bit TIDR[ATCTE].
45948 */
45949#define TMU_TIER_ATCTEIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ATCTEIE_SHIFT)) & TMU_TIER_ATCTEIE_MASK)
45950#define TMU_TIER_ATTEIE_MASK (0x40000000U)
45951#define TMU_TIER_ATTEIE_SHIFT (30U)
45952/*! ATTEIE
45953 * 0b0..Disabled.
45954 * 0b1..Interrupt enabled. Generate an interrupt if TIDR[ATTE] is set. Write 1 to this bit will clear bit TIDR[ATTE].
45955 */
45956#define TMU_TIER_ATTEIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ATTEIE_SHIFT)) & TMU_TIER_ATTEIE_MASK)
45957#define TMU_TIER_ITTEIE_MASK (0x80000000U)
45958#define TMU_TIER_ITTEIE_SHIFT (31U)
45959/*! ITTEIE
45960 * 0b0..Disabled.
45961 * 0b1..Interrupt enabled. Generate an interrupt if TIDR[ITTE] is set. Write 1 to this bit will clear bit TIDR[ITTE].
45962 */
45963#define TMU_TIER_ITTEIE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIER_ITTEIE_SHIFT)) & TMU_TIER_ITTEIE_MASK)
45964/*! @} */
45965
45966/*! @name TIDR - TMU Interrupt Detect register */
45967/*! @{ */
45968#define TMU_TIDR_ATCTE_MASK (0x10000000U)
45969#define TMU_TIDR_ATCTE_SHIFT (28U)
45970/*! ATCTE
45971 * 0b0..No threshold exceeded.
45972 * 0b1..Average temperature critical threshold, as defined by TMHTACTR, has been exceeded.
45973 */
45974#define TMU_TIDR_ATCTE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ATCTE_SHIFT)) & TMU_TIDR_ATCTE_MASK)
45975#define TMU_TIDR_ATTE_MASK (0x20000000U)
45976#define TMU_TIDR_ATTE_SHIFT (29U)
45977/*! ATTE
45978 * 0b0..No threshold exceeded.
45979 * 0b1..Average temperature threshold, as defined by TMHTATR, has been exceeded.
45980 */
45981#define TMU_TIDR_ATTE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ATTE_SHIFT)) & TMU_TIDR_ATTE_MASK)
45982#define TMU_TIDR_ITTE_MASK (0x40000000U)
45983#define TMU_TIDR_ITTE_SHIFT (30U)
45984/*! ITTE
45985 * 0b0..No threshold exceeded.
45986 * 0b1..Immediate temperature threshold, as defined by TMHTITR, has been exceeded. This includes an out-of-range
45987 * measured temperature above 125degree C.
45988 */
45989#define TMU_TIDR_ITTE(x) (((uint32_t)(((uint32_t)(x)) << TMU_TIDR_ITTE_SHIFT)) & TMU_TIDR_ITTE_MASK)
45990/*! @} */
45991
45992/*! @name TMHTITR - TMU Monitor High Temperature Immediate Threshold register */
45993/*! @{ */
45994#define TMU_TMHTITR_TEMP_MASK (0xFFU)
45995#define TMU_TMHTITR_TEMP_SHIFT (0U)
45996#define TMU_TMHTITR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_TEMP_SHIFT)) & TMU_TMHTITR_TEMP_MASK)
45997#define TMU_TMHTITR_EN_MASK (0x80000000U)
45998#define TMU_TMHTITR_EN_SHIFT (31U)
45999/*! EN
46000 * 0b0..Disabled.
46001 * 0b1..Threshold enabled.
46002 */
46003#define TMU_TMHTITR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTITR_EN_SHIFT)) & TMU_TMHTITR_EN_MASK)
46004/*! @} */
46005
46006/*! @name TMHTATR - TMU Monitor High Temperature Average threshold register */
46007/*! @{ */
46008#define TMU_TMHTATR_TEMP_MASK (0xFFU)
46009#define TMU_TMHTATR_TEMP_SHIFT (0U)
46010#define TMU_TMHTATR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_TEMP_SHIFT)) & TMU_TMHTATR_TEMP_MASK)
46011#define TMU_TMHTATR_EN_MASK (0x80000000U)
46012#define TMU_TMHTATR_EN_SHIFT (31U)
46013/*! EN
46014 * 0b0..Disabled.
46015 * 0b1..Threshold enabled.
46016 */
46017#define TMU_TMHTATR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTATR_EN_SHIFT)) & TMU_TMHTATR_EN_MASK)
46018/*! @} */
46019
46020/*! @name TMHTACTR - TMU Monitor High Temperature Average Critical Threshold register */
46021/*! @{ */
46022#define TMU_TMHTACTR_TEMP_MASK (0xFFU)
46023#define TMU_TMHTACTR_TEMP_SHIFT (0U)
46024#define TMU_TMHTACTR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_TEMP_SHIFT)) & TMU_TMHTACTR_TEMP_MASK)
46025#define TMU_TMHTACTR_EN_MASK (0x80000000U)
46026#define TMU_TMHTACTR_EN_SHIFT (31U)
46027/*! EN
46028 * 0b0..Disabled.
46029 * 0b1..Threshold enabled.
46030 */
46031#define TMU_TMHTACTR_EN(x) (((uint32_t)(((uint32_t)(x)) << TMU_TMHTACTR_EN_SHIFT)) & TMU_TMHTACTR_EN_MASK)
46032/*! @} */
46033
46034/*! @name TSCR - TMU Sensor Calibration register */
46035/*! @{ */
46036#define TMU_TSCR_SENSOR_MASK (0xFFU)
46037#define TMU_TSCR_SENSOR_SHIFT (0U)
46038#define TMU_TSCR_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSCR_SENSOR_SHIFT)) & TMU_TSCR_SENSOR_MASK)
46039#define TMU_TSCR_BSR_MASK (0x80000000U)
46040#define TMU_TSCR_BSR_SHIFT (31U)
46041#define TMU_TSCR_BSR(x) (((uint32_t)(((uint32_t)(x)) << TMU_TSCR_BSR_SHIFT)) & TMU_TSCR_BSR_MASK)
46042/*! @} */
46043
46044/*! @name TRITSR - TMU Report Immediate Temperature Site register n */
46045/*! @{ */
46046#define TMU_TRITSR_TEMP_MASK (0xFFU)
46047#define TMU_TRITSR_TEMP_SHIFT (0U)
46048#define TMU_TRITSR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_TEMP_SHIFT)) & TMU_TRITSR_TEMP_MASK)
46049#define TMU_TRITSR_V_MASK (0x80000000U)
46050#define TMU_TRITSR_V_SHIFT (31U)
46051/*! V
46052 * 0b0..Not valid. Temperature out of sensor range or first measurement still pending.
46053 * 0b1..Valid.
46054 */
46055#define TMU_TRITSR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRITSR_V_SHIFT)) & TMU_TRITSR_V_MASK)
46056/*! @} */
46057
46058/*! @name TRATSR - TMU Report Average Temperature Site register n */
46059/*! @{ */
46060#define TMU_TRATSR_TEMP_MASK (0xFFU)
46061#define TMU_TRATSR_TEMP_SHIFT (0U)
46062#define TMU_TRATSR_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_TEMP_SHIFT)) & TMU_TRATSR_TEMP_MASK)
46063#define TMU_TRATSR_V_MASK (0x80000000U)
46064#define TMU_TRATSR_V_SHIFT (31U)
46065/*! V
46066 * 0b0..Not valid. Temperature out of sensor range or first measurement still pending.
46067 * 0b1..Valid.
46068 */
46069#define TMU_TRATSR_V(x) (((uint32_t)(((uint32_t)(x)) << TMU_TRATSR_V_SHIFT)) & TMU_TRATSR_V_MASK)
46070/*! @} */
46071
46072/*!
46073 * @}
46074 */ /* end of group TMU_Register_Masks */
46075
46076/* TMU - Peripheral instance base addresses */
46077/** Peripheral TMU base address */
46078#define TMU_BASE (0x30260000u)
46079/** Peripheral TMU base pointer */
46080#define TMU ((TMU_Type *)TMU_BASE)
46081/** Array initializer of TMU peripheral base addresses */
46082#define TMU_BASE_ADDRS \
46083 { \
46084 TMU_BASE \
46085 }
46086/** Array initializer of TMU peripheral base pointers */
46087#define TMU_BASE_PTRS \
46088 { \
46089 TMU \
46090 }
46091
46092/*!
46093 * @}
46094 */ /* end of group TMU_Peripheral_Access_Layer */
46095
46096/* ----------------------------------------------------------------------------
46097 -- UART Peripheral Access Layer
46098 ---------------------------------------------------------------------------- */
46099
46100/*!
46101 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
46102 * @{
46103 */
46104
46105/** UART - Register Layout Typedef */
46106typedef struct
46107{
46108 __I uint32_t URXD; /**< UART Receiver Register, offset: 0x0 */
46109 uint8_t RESERVED_0[60];
46110 __O uint32_t UTXD; /**< UART Transmitter Register, offset: 0x40 */
46111 uint8_t RESERVED_1[60];
46112 __IO uint32_t UCR1; /**< UART Control Register 1, offset: 0x80 */
46113 __IO uint32_t UCR2; /**< UART Control Register 2, offset: 0x84 */
46114 __IO uint32_t UCR3; /**< UART Control Register 3, offset: 0x88 */
46115 __IO uint32_t UCR4; /**< UART Control Register 4, offset: 0x8C */
46116 __IO uint32_t UFCR; /**< UART FIFO Control Register, offset: 0x90 */
46117 __IO uint32_t USR1; /**< UART Status Register 1, offset: 0x94 */
46118 __IO uint32_t USR2; /**< UART Status Register 2, offset: 0x98 */
46119 __IO uint32_t UESC; /**< UART Escape Character Register, offset: 0x9C */
46120 __IO uint32_t UTIM; /**< UART Escape Timer Register, offset: 0xA0 */
46121 __IO uint32_t UBIR; /**< UART BRM Incremental Register, offset: 0xA4 */
46122 __IO uint32_t UBMR; /**< UART BRM Modulator Register, offset: 0xA8 */
46123 __I uint32_t UBRC; /**< UART Baud Rate Count Register, offset: 0xAC */
46124 __IO uint32_t ONEMS; /**< UART One Millisecond Register, offset: 0xB0 */
46125 __IO uint32_t UTS; /**< UART Test Register, offset: 0xB4 */
46126 __IO uint32_t UMCR; /**< UART RS-485 Mode Control Register, offset: 0xB8 */
46127} UART_Type;
46128
46129/* ----------------------------------------------------------------------------
46130 -- UART Register Masks
46131 ---------------------------------------------------------------------------- */
46132
46133/*!
46134 * @addtogroup UART_Register_Masks UART Register Masks
46135 * @{
46136 */
46137
46138/*! @name URXD - UART Receiver Register */
46139/*! @{ */
46140#define UART_URXD_RX_DATA_MASK (0xFFU)
46141#define UART_URXD_RX_DATA_SHIFT (0U)
46142#define UART_URXD_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_RX_DATA_SHIFT)) & UART_URXD_RX_DATA_MASK)
46143#define UART_URXD_PRERR_MASK (0x400U)
46144#define UART_URXD_PRERR_SHIFT (10U)
46145/*! PRERR
46146 * 0b0..= No parity error was detected for data in the RX_DATA field
46147 * 0b1..= A parity error was detected for data in the RX_DATA field
46148 */
46149#define UART_URXD_PRERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_PRERR_SHIFT)) & UART_URXD_PRERR_MASK)
46150#define UART_URXD_BRK_MASK (0x800U)
46151#define UART_URXD_BRK_SHIFT (11U)
46152/*! BRK
46153 * 0b0..The current character is not a BREAK character
46154 * 0b1..The current character is a BREAK character
46155 */
46156#define UART_URXD_BRK(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_BRK_SHIFT)) & UART_URXD_BRK_MASK)
46157#define UART_URXD_FRMERR_MASK (0x1000U)
46158#define UART_URXD_FRMERR_SHIFT (12U)
46159/*! FRMERR
46160 * 0b0..The current character has no framing error
46161 * 0b1..The current character has a framing error
46162 */
46163#define UART_URXD_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_FRMERR_SHIFT)) & UART_URXD_FRMERR_MASK)
46164#define UART_URXD_OVRRUN_MASK (0x2000U)
46165#define UART_URXD_OVRRUN_SHIFT (13U)
46166/*! OVRRUN
46167 * 0b0..No RxFIFO overrun was detected
46168 * 0b1..A RxFIFO overrun was detected
46169 */
46170#define UART_URXD_OVRRUN(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_OVRRUN_SHIFT)) & UART_URXD_OVRRUN_MASK)
46171#define UART_URXD_ERR_MASK (0x4000U)
46172#define UART_URXD_ERR_SHIFT (14U)
46173/*! ERR
46174 * 0b0..No error status was detected
46175 * 0b1..An error status was detected
46176 */
46177#define UART_URXD_ERR(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_ERR_SHIFT)) & UART_URXD_ERR_MASK)
46178#define UART_URXD_CHARRDY_MASK (0x8000U)
46179#define UART_URXD_CHARRDY_SHIFT (15U)
46180/*! CHARRDY
46181 * 0b0..Character in RX_DATA field and associated flags are invalid.
46182 * 0b1..Character in RX_DATA field and associated flags valid and ready for reading.
46183 */
46184#define UART_URXD_CHARRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_URXD_CHARRDY_SHIFT)) & UART_URXD_CHARRDY_MASK)
46185/*! @} */
46186
46187/*! @name UTXD - UART Transmitter Register */
46188/*! @{ */
46189#define UART_UTXD_TX_DATA_MASK (0xFFU)
46190#define UART_UTXD_TX_DATA_SHIFT (0U)
46191#define UART_UTXD_TX_DATA(x) (((uint32_t)(((uint32_t)(x)) << UART_UTXD_TX_DATA_SHIFT)) & UART_UTXD_TX_DATA_MASK)
46192/*! @} */
46193
46194/*! @name UCR1 - UART Control Register 1 */
46195/*! @{ */
46196#define UART_UCR1_UARTEN_MASK (0x1U)
46197#define UART_UCR1_UARTEN_SHIFT (0U)
46198/*! UARTEN
46199 * 0b0..Disable the UART
46200 * 0b1..Enable the UART
46201 */
46202#define UART_UCR1_UARTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_UARTEN_SHIFT)) & UART_UCR1_UARTEN_MASK)
46203#define UART_UCR1_DOZE_MASK (0x2U)
46204#define UART_UCR1_DOZE_SHIFT (1U)
46205/*! DOZE
46206 * 0b0..The UART is enabled when in DOZE state
46207 * 0b1..The UART is disabled when in DOZE state
46208 */
46209#define UART_UCR1_DOZE(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_DOZE_SHIFT)) & UART_UCR1_DOZE_MASK)
46210#define UART_UCR1_ATDMAEN_MASK (0x4U)
46211#define UART_UCR1_ATDMAEN_SHIFT (2U)
46212/*! ATDMAEN
46213 * 0b0..Disable AGTIM DMA request
46214 * 0b1..Enable AGTIM DMA request
46215 */
46216#define UART_UCR1_ATDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ATDMAEN_SHIFT)) & UART_UCR1_ATDMAEN_MASK)
46217#define UART_UCR1_TXDMAEN_MASK (0x8U)
46218#define UART_UCR1_TXDMAEN_SHIFT (3U)
46219/*! TXDMAEN
46220 * 0b0..Disable transmit DMA request
46221 * 0b1..Enable transmit DMA request
46222 */
46223#define UART_UCR1_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXDMAEN_SHIFT)) & UART_UCR1_TXDMAEN_MASK)
46224#define UART_UCR1_SNDBRK_MASK (0x10U)
46225#define UART_UCR1_SNDBRK_SHIFT (4U)
46226/*! SNDBRK
46227 * 0b0..Do not send a BREAK character
46228 * 0b1..Send a BREAK character (continuous 0s)
46229 */
46230#define UART_UCR1_SNDBRK(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_SNDBRK_SHIFT)) & UART_UCR1_SNDBRK_MASK)
46231#define UART_UCR1_RTSDEN_MASK (0x20U)
46232#define UART_UCR1_RTSDEN_SHIFT (5U)
46233/*! RTSDEN
46234 * 0b0..Disable RTSD interrupt
46235 * 0b1..Enable RTSD interrupt
46236 */
46237#define UART_UCR1_RTSDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RTSDEN_SHIFT)) & UART_UCR1_RTSDEN_MASK)
46238#define UART_UCR1_TXMPTYEN_MASK (0x40U)
46239#define UART_UCR1_TXMPTYEN_SHIFT (6U)
46240/*! TXMPTYEN
46241 * 0b0..Disable the transmitter FIFO empty interrupt
46242 * 0b1..Enable the transmitter FIFO empty interrupt
46243 */
46244#define UART_UCR1_TXMPTYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TXMPTYEN_SHIFT)) & UART_UCR1_TXMPTYEN_MASK)
46245#define UART_UCR1_IREN_MASK (0x80U)
46246#define UART_UCR1_IREN_SHIFT (7U)
46247/*! IREN
46248 * 0b0..Disable the IR interface
46249 * 0b1..Enable the IR interface
46250 */
46251#define UART_UCR1_IREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IREN_SHIFT)) & UART_UCR1_IREN_MASK)
46252#define UART_UCR1_RXDMAEN_MASK (0x100U)
46253#define UART_UCR1_RXDMAEN_SHIFT (8U)
46254/*! RXDMAEN
46255 * 0b0..Disable DMA request
46256 * 0b1..Enable DMA request
46257 */
46258#define UART_UCR1_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RXDMAEN_SHIFT)) & UART_UCR1_RXDMAEN_MASK)
46259#define UART_UCR1_RRDYEN_MASK (0x200U)
46260#define UART_UCR1_RRDYEN_SHIFT (9U)
46261/*! RRDYEN
46262 * 0b0..Disables the RRDY interrupt
46263 * 0b1..Enables the RRDY interrupt
46264 */
46265#define UART_UCR1_RRDYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_RRDYEN_SHIFT)) & UART_UCR1_RRDYEN_MASK)
46266#define UART_UCR1_ICD_MASK (0xC00U)
46267#define UART_UCR1_ICD_SHIFT (10U)
46268/*! ICD
46269 * 0b00..Idle for more than 4 frames
46270 * 0b01..Idle for more than 8 frames
46271 * 0b10..Idle for more than 16 frames
46272 * 0b11..Idle for more than 32 frames
46273 */
46274#define UART_UCR1_ICD(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ICD_SHIFT)) & UART_UCR1_ICD_MASK)
46275#define UART_UCR1_IDEN_MASK (0x1000U)
46276#define UART_UCR1_IDEN_SHIFT (12U)
46277/*! IDEN
46278 * 0b0..Disable the IDLE interrupt
46279 * 0b1..Enable the IDLE interrupt
46280 */
46281#define UART_UCR1_IDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_IDEN_SHIFT)) & UART_UCR1_IDEN_MASK)
46282#define UART_UCR1_TRDYEN_MASK (0x2000U)
46283#define UART_UCR1_TRDYEN_SHIFT (13U)
46284/*! TRDYEN
46285 * 0b0..Disable the transmitter ready interrupt
46286 * 0b1..Enable the transmitter ready interrupt
46287 */
46288#define UART_UCR1_TRDYEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_TRDYEN_SHIFT)) & UART_UCR1_TRDYEN_MASK)
46289#define UART_UCR1_ADBR_MASK (0x4000U)
46290#define UART_UCR1_ADBR_SHIFT (14U)
46291/*! ADBR
46292 * 0b0..Disable automatic detection of baud rate
46293 * 0b1..Enable automatic detection of baud rate
46294 */
46295#define UART_UCR1_ADBR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADBR_SHIFT)) & UART_UCR1_ADBR_MASK)
46296#define UART_UCR1_ADEN_MASK (0x8000U)
46297#define UART_UCR1_ADEN_SHIFT (15U)
46298/*! ADEN
46299 * 0b0..Disable the automatic baud rate detection interrupt
46300 * 0b1..Enable the automatic baud rate detection interrupt
46301 */
46302#define UART_UCR1_ADEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR1_ADEN_SHIFT)) & UART_UCR1_ADEN_MASK)
46303/*! @} */
46304
46305/*! @name UCR2 - UART Control Register 2 */
46306/*! @{ */
46307#define UART_UCR2_SRST_MASK (0x1U)
46308#define UART_UCR2_SRST_SHIFT (0U)
46309/*! SRST
46310 * 0b0..Reset the transmit and receive state machines, all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC , URXD, UTXD
46311 * and UTS[6-3]. 0b1..No reset
46312 */
46313#define UART_UCR2_SRST(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_SRST_SHIFT)) & UART_UCR2_SRST_MASK)
46314#define UART_UCR2_RXEN_MASK (0x2U)
46315#define UART_UCR2_RXEN_SHIFT (1U)
46316/*! RXEN
46317 * 0b0..Disable the receiver
46318 * 0b1..Enable the receiver
46319 */
46320#define UART_UCR2_RXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RXEN_SHIFT)) & UART_UCR2_RXEN_MASK)
46321#define UART_UCR2_TXEN_MASK (0x4U)
46322#define UART_UCR2_TXEN_SHIFT (2U)
46323/*! TXEN
46324 * 0b0..Disable the transmitter
46325 * 0b1..Enable the transmitter
46326 */
46327#define UART_UCR2_TXEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_TXEN_SHIFT)) & UART_UCR2_TXEN_MASK)
46328#define UART_UCR2_ATEN_MASK (0x8U)
46329#define UART_UCR2_ATEN_SHIFT (3U)
46330/*! ATEN
46331 * 0b0..AGTIM interrupt disabled
46332 * 0b1..AGTIM interrupt enabled
46333 */
46334#define UART_UCR2_ATEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ATEN_SHIFT)) & UART_UCR2_ATEN_MASK)
46335#define UART_UCR2_RTSEN_MASK (0x10U)
46336#define UART_UCR2_RTSEN_SHIFT (4U)
46337/*! RTSEN
46338 * 0b0..Disable request to send interrupt
46339 * 0b1..Enable request to send interrupt
46340 */
46341#define UART_UCR2_RTSEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTSEN_SHIFT)) & UART_UCR2_RTSEN_MASK)
46342#define UART_UCR2_WS_MASK (0x20U)
46343#define UART_UCR2_WS_SHIFT (5U)
46344/*! WS
46345 * 0b0..7-bit transmit and receive character length (not including START, STOP or PARITY bits)
46346 * 0b1..8-bit transmit and receive character length (not including START, STOP or PARITY bits)
46347 */
46348#define UART_UCR2_WS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_WS_SHIFT)) & UART_UCR2_WS_MASK)
46349#define UART_UCR2_STPB_MASK (0x40U)
46350#define UART_UCR2_STPB_SHIFT (6U)
46351/*! STPB
46352 * 0b0..The transmitter sends 1 stop bit. The receiver expects 1 or more stop bits.
46353 * 0b1..The transmitter sends 2 stop bits. The receiver expects 2 or more stop bits.
46354 */
46355#define UART_UCR2_STPB(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_STPB_SHIFT)) & UART_UCR2_STPB_MASK)
46356#define UART_UCR2_PROE_MASK (0x80U)
46357#define UART_UCR2_PROE_SHIFT (7U)
46358/*! PROE
46359 * 0b0..Even parity
46360 * 0b1..Odd parity
46361 */
46362#define UART_UCR2_PROE(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PROE_SHIFT)) & UART_UCR2_PROE_MASK)
46363#define UART_UCR2_PREN_MASK (0x100U)
46364#define UART_UCR2_PREN_SHIFT (8U)
46365/*! PREN
46366 * 0b0..Disable parity generator and checker
46367 * 0b1..Enable parity generator and checker
46368 */
46369#define UART_UCR2_PREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_PREN_SHIFT)) & UART_UCR2_PREN_MASK)
46370#define UART_UCR2_RTEC_MASK (0x600U)
46371#define UART_UCR2_RTEC_SHIFT (9U)
46372/*! RTEC
46373 * 0b00..Trigger interrupt on a rising edge
46374 * 0b01..Trigger interrupt on a falling edge
46375 * 0b1x..Trigger interrupt on any edge
46376 */
46377#define UART_UCR2_RTEC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_RTEC_SHIFT)) & UART_UCR2_RTEC_MASK)
46378#define UART_UCR2_ESCEN_MASK (0x800U)
46379#define UART_UCR2_ESCEN_SHIFT (11U)
46380/*! ESCEN
46381 * 0b0..Disable escape sequence detection
46382 * 0b1..Enable escape sequence detection
46383 */
46384#define UART_UCR2_ESCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCEN_SHIFT)) & UART_UCR2_ESCEN_MASK)
46385#define UART_UCR2_CTS_MASK (0x1000U)
46386#define UART_UCR2_CTS_SHIFT (12U)
46387/*! CTS
46388 * 0b0..The CTS_B pin is high (inactive)
46389 * 0b1..The CTS_B pin is low (active)
46390 */
46391#define UART_UCR2_CTS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTS_SHIFT)) & UART_UCR2_CTS_MASK)
46392#define UART_UCR2_CTSC_MASK (0x2000U)
46393#define UART_UCR2_CTSC_SHIFT (13U)
46394/*! CTSC
46395 * 0b0..The CTS_B pin is controlled by the CTS bit
46396 * 0b1..The CTS_B pin is controlled by the receiver
46397 */
46398#define UART_UCR2_CTSC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_CTSC_SHIFT)) & UART_UCR2_CTSC_MASK)
46399#define UART_UCR2_IRTS_MASK (0x4000U)
46400#define UART_UCR2_IRTS_SHIFT (14U)
46401/*! IRTS
46402 * 0b0..Transmit only when the RTS pin is asserted
46403 * 0b1..Ignore the RTS pin
46404 */
46405#define UART_UCR2_IRTS(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_IRTS_SHIFT)) & UART_UCR2_IRTS_MASK)
46406#define UART_UCR2_ESCI_MASK (0x8000U)
46407#define UART_UCR2_ESCI_SHIFT (15U)
46408/*! ESCI
46409 * 0b0..Disable the escape sequence interrupt
46410 * 0b1..Enable the escape sequence interrupt
46411 */
46412#define UART_UCR2_ESCI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR2_ESCI_SHIFT)) & UART_UCR2_ESCI_MASK)
46413/*! @} */
46414
46415/*! @name UCR3 - UART Control Register 3 */
46416/*! @{ */
46417#define UART_UCR3_ACIEN_MASK (0x1U)
46418#define UART_UCR3_ACIEN_SHIFT (0U)
46419/*! ACIEN
46420 * 0b0..ACST interrupt disabled
46421 * 0b1..ACST interrupt enabled
46422 */
46423#define UART_UCR3_ACIEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ACIEN_SHIFT)) & UART_UCR3_ACIEN_MASK)
46424#define UART_UCR3_INVT_MASK (0x2U)
46425#define UART_UCR3_INVT_SHIFT (1U)
46426/*! INVT
46427 * 0b0..TXD is not inverted
46428 * 0b1..TXD is inverted
46429 * 0b0..TXD Active low transmission
46430 * 0b1..TXD Active high transmission
46431 */
46432#define UART_UCR3_INVT(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_INVT_SHIFT)) & UART_UCR3_INVT_MASK)
46433#define UART_UCR3_RXDMUXSEL_MASK (0x4U)
46434#define UART_UCR3_RXDMUXSEL_SHIFT (2U)
46435#define UART_UCR3_RXDMUXSEL(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDMUXSEL_SHIFT)) & UART_UCR3_RXDMUXSEL_MASK)
46436#define UART_UCR3_DTRDEN_MASK (0x8U)
46437#define UART_UCR3_DTRDEN_SHIFT (3U)
46438#define UART_UCR3_DTRDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTRDEN_SHIFT)) & UART_UCR3_DTRDEN_MASK)
46439#define UART_UCR3_AWAKEN_MASK (0x10U)
46440#define UART_UCR3_AWAKEN_SHIFT (4U)
46441/*! AWAKEN
46442 * 0b0..Disable the AWAKE interrupt
46443 * 0b1..Enable the AWAKE interrupt
46444 */
46445#define UART_UCR3_AWAKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AWAKEN_SHIFT)) & UART_UCR3_AWAKEN_MASK)
46446#define UART_UCR3_AIRINTEN_MASK (0x20U)
46447#define UART_UCR3_AIRINTEN_SHIFT (5U)
46448/*! AIRINTEN
46449 * 0b0..Disable the AIRINT interrupt
46450 * 0b1..Enable the AIRINT interrupt
46451 */
46452#define UART_UCR3_AIRINTEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_AIRINTEN_SHIFT)) & UART_UCR3_AIRINTEN_MASK)
46453#define UART_UCR3_RXDSEN_MASK (0x40U)
46454#define UART_UCR3_RXDSEN_SHIFT (6U)
46455/*! RXDSEN
46456 * 0b0..Disable the RXDS interrupt
46457 * 0b1..Enable the RXDS interrupt
46458 */
46459#define UART_UCR3_RXDSEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RXDSEN_SHIFT)) & UART_UCR3_RXDSEN_MASK)
46460#define UART_UCR3_ADNIMP_MASK (0x80U)
46461#define UART_UCR3_ADNIMP_SHIFT (7U)
46462/*! ADNIMP
46463 * 0b0..Autobaud detection new features selected
46464 * 0b1..Keep old autobaud detection mechanism
46465 */
46466#define UART_UCR3_ADNIMP(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_ADNIMP_SHIFT)) & UART_UCR3_ADNIMP_MASK)
46467#define UART_UCR3_RI_MASK (0x100U)
46468#define UART_UCR3_RI_SHIFT (8U)
46469#define UART_UCR3_RI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_RI_SHIFT)) & UART_UCR3_RI_MASK)
46470#define UART_UCR3_DCD_MASK (0x200U)
46471#define UART_UCR3_DCD_SHIFT (9U)
46472#define UART_UCR3_DCD(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DCD_SHIFT)) & UART_UCR3_DCD_MASK)
46473#define UART_UCR3_DSR_MASK (0x400U)
46474#define UART_UCR3_DSR_SHIFT (10U)
46475#define UART_UCR3_DSR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DSR_SHIFT)) & UART_UCR3_DSR_MASK)
46476#define UART_UCR3_FRAERREN_MASK (0x800U)
46477#define UART_UCR3_FRAERREN_SHIFT (11U)
46478/*! FRAERREN
46479 * 0b0..Disable the frame error interrupt
46480 * 0b1..Enable the frame error interrupt
46481 */
46482#define UART_UCR3_FRAERREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_FRAERREN_SHIFT)) & UART_UCR3_FRAERREN_MASK)
46483#define UART_UCR3_PARERREN_MASK (0x1000U)
46484#define UART_UCR3_PARERREN_SHIFT (12U)
46485/*! PARERREN
46486 * 0b0..Disable the parity error interrupt
46487 * 0b1..Enable the parity error interrupt
46488 */
46489#define UART_UCR3_PARERREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_PARERREN_SHIFT)) & UART_UCR3_PARERREN_MASK)
46490#define UART_UCR3_DTREN_MASK (0x2000U)
46491#define UART_UCR3_DTREN_SHIFT (13U)
46492#define UART_UCR3_DTREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DTREN_SHIFT)) & UART_UCR3_DTREN_MASK)
46493#define UART_UCR3_DPEC_MASK (0xC000U)
46494#define UART_UCR3_DPEC_SHIFT (14U)
46495#define UART_UCR3_DPEC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR3_DPEC_SHIFT)) & UART_UCR3_DPEC_MASK)
46496/*! @} */
46497
46498/*! @name UCR4 - UART Control Register 4 */
46499/*! @{ */
46500#define UART_UCR4_DREN_MASK (0x1U)
46501#define UART_UCR4_DREN_SHIFT (0U)
46502/*! DREN
46503 * 0b0..Disable RDR interrupt
46504 * 0b1..Enable RDR interrupt
46505 */
46506#define UART_UCR4_DREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_DREN_SHIFT)) & UART_UCR4_DREN_MASK)
46507#define UART_UCR4_OREN_MASK (0x2U)
46508#define UART_UCR4_OREN_SHIFT (1U)
46509/*! OREN
46510 * 0b0..Disable ORE interrupt
46511 * 0b1..Enable ORE interrupt
46512 */
46513#define UART_UCR4_OREN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_OREN_SHIFT)) & UART_UCR4_OREN_MASK)
46514#define UART_UCR4_BKEN_MASK (0x4U)
46515#define UART_UCR4_BKEN_SHIFT (2U)
46516/*! BKEN
46517 * 0b0..Disable the BRCD interrupt
46518 * 0b1..Enable the BRCD interrupt
46519 */
46520#define UART_UCR4_BKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_BKEN_SHIFT)) & UART_UCR4_BKEN_MASK)
46521#define UART_UCR4_TCEN_MASK (0x8U)
46522#define UART_UCR4_TCEN_SHIFT (3U)
46523/*! TCEN
46524 * 0b0..Disable TXDC interrupt
46525 * 0b1..Enable TXDC interrupt
46526 */
46527#define UART_UCR4_TCEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_TCEN_SHIFT)) & UART_UCR4_TCEN_MASK)
46528#define UART_UCR4_LPBYP_MASK (0x10U)
46529#define UART_UCR4_LPBYP_SHIFT (4U)
46530/*! LPBYP
46531 * 0b0..Low power features enabled
46532 * 0b1..Low power features disabled
46533 */
46534#define UART_UCR4_LPBYP(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_LPBYP_SHIFT)) & UART_UCR4_LPBYP_MASK)
46535#define UART_UCR4_IRSC_MASK (0x20U)
46536#define UART_UCR4_IRSC_SHIFT (5U)
46537/*! IRSC
46538 * 0b0..The vote logic uses the sampling clock (16x baud rate) for normal operation
46539 * 0b1..The vote logic uses the UART reference clock
46540 */
46541#define UART_UCR4_IRSC(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IRSC_SHIFT)) & UART_UCR4_IRSC_MASK)
46542#define UART_UCR4_IDDMAEN_MASK (0x40U)
46543#define UART_UCR4_IDDMAEN_SHIFT (6U)
46544/*! IDDMAEN
46545 * 0b0..DMA IDLE interrupt disabled
46546 * 0b1..DMA IDLE interrupt enabled
46547 */
46548#define UART_UCR4_IDDMAEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_IDDMAEN_SHIFT)) & UART_UCR4_IDDMAEN_MASK)
46549#define UART_UCR4_WKEN_MASK (0x80U)
46550#define UART_UCR4_WKEN_SHIFT (7U)
46551/*! WKEN
46552 * 0b0..Disable the WAKE interrupt
46553 * 0b1..Enable the WAKE interrupt
46554 */
46555#define UART_UCR4_WKEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_WKEN_SHIFT)) & UART_UCR4_WKEN_MASK)
46556#define UART_UCR4_ENIRI_MASK (0x100U)
46557#define UART_UCR4_ENIRI_SHIFT (8U)
46558/*! ENIRI
46559 * 0b0..Serial infrared Interrupt disabled
46560 * 0b1..Serial infrared Interrupt enabled
46561 */
46562#define UART_UCR4_ENIRI(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_ENIRI_SHIFT)) & UART_UCR4_ENIRI_MASK)
46563#define UART_UCR4_INVR_MASK (0x200U)
46564#define UART_UCR4_INVR_SHIFT (9U)
46565/*! INVR
46566 * 0b0..RXD input is not inverted
46567 * 0b1..RXD input is inverted
46568 * 0b0..RXD active low detection
46569 * 0b1..RXD active high detection
46570 */
46571#define UART_UCR4_INVR(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_INVR_SHIFT)) & UART_UCR4_INVR_MASK)
46572#define UART_UCR4_CTSTL_MASK (0xFC00U)
46573#define UART_UCR4_CTSTL_SHIFT (10U)
46574/*! CTSTL
46575 * 0b000000..0 characters received
46576 * 0b000001..1 characters in the RxFIFO
46577 * 0b100000..32 characters in the RxFIFO (maximum)
46578 */
46579#define UART_UCR4_CTSTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UCR4_CTSTL_SHIFT)) & UART_UCR4_CTSTL_MASK)
46580/*! @} */
46581
46582/*! @name UFCR - UART FIFO Control Register */
46583/*! @{ */
46584#define UART_UFCR_RXTL_MASK (0x3FU)
46585#define UART_UFCR_RXTL_SHIFT (0U)
46586/*! RXTL
46587 * 0b000000..0 characters received
46588 * 0b000001..RxFIFO has 1 character
46589 * 0b011111..RxFIFO has 31 characters
46590 * 0b100000..RxFIFO has 32 characters (maximum)
46591 */
46592#define UART_UFCR_RXTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RXTL_SHIFT)) & UART_UFCR_RXTL_MASK)
46593#define UART_UFCR_DCEDTE_MASK (0x40U)
46594#define UART_UFCR_DCEDTE_SHIFT (6U)
46595/*! DCEDTE
46596 * 0b0..DCE mode selected
46597 * 0b1..DTE mode selected
46598 */
46599#define UART_UFCR_DCEDTE(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_DCEDTE_SHIFT)) & UART_UFCR_DCEDTE_MASK)
46600#define UART_UFCR_RFDIV_MASK (0x380U)
46601#define UART_UFCR_RFDIV_SHIFT (7U)
46602/*! RFDIV
46603 * 0b000..Divide input clock by 6
46604 * 0b001..Divide input clock by 5
46605 * 0b010..Divide input clock by 4
46606 * 0b011..Divide input clock by 3
46607 * 0b100..Divide input clock by 2
46608 * 0b101..Divide input clock by 1
46609 * 0b110..Divide input clock by 7
46610 * 0b111..Reserved
46611 */
46612#define UART_UFCR_RFDIV(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_RFDIV_SHIFT)) & UART_UFCR_RFDIV_MASK)
46613#define UART_UFCR_TXTL_MASK (0xFC00U)
46614#define UART_UFCR_TXTL_SHIFT (10U)
46615/*! TXTL
46616 * 0b000000..Reserved
46617 * 0b000001..Reserved
46618 * 0b000010..TxFIFO has 2 or fewer characters
46619 * 0b011111..TxFIFO has 31 or fewer characters
46620 * 0b100000..TxFIFO has 32 characters (maximum)
46621 */
46622#define UART_UFCR_TXTL(x) (((uint32_t)(((uint32_t)(x)) << UART_UFCR_TXTL_SHIFT)) & UART_UFCR_TXTL_MASK)
46623/*! @} */
46624
46625/*! @name USR1 - UART Status Register 1 */
46626/*! @{ */
46627#define UART_USR1_SAD_MASK (0x8U)
46628#define UART_USR1_SAD_SHIFT (3U)
46629/*! SAD
46630 * 0b0..No slave address detected
46631 * 0b1..Slave address detected
46632 */
46633#define UART_USR1_SAD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_SAD_SHIFT)) & UART_USR1_SAD_MASK)
46634#define UART_USR1_AWAKE_MASK (0x10U)
46635#define UART_USR1_AWAKE_SHIFT (4U)
46636/*! AWAKE
46637 * 0b0..No falling edge was detected on the RXD Serial pin
46638 * 0b1..A falling edge was detected on the RXD Serial pin
46639 */
46640#define UART_USR1_AWAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AWAKE_SHIFT)) & UART_USR1_AWAKE_MASK)
46641#define UART_USR1_AIRINT_MASK (0x20U)
46642#define UART_USR1_AIRINT_SHIFT (5U)
46643/*! AIRINT
46644 * 0b0..No pulse was detected on the RXD IrDA pin
46645 * 0b1..A pulse was detected on the RXD IrDA pin
46646 */
46647#define UART_USR1_AIRINT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AIRINT_SHIFT)) & UART_USR1_AIRINT_MASK)
46648#define UART_USR1_RXDS_MASK (0x40U)
46649#define UART_USR1_RXDS_SHIFT (6U)
46650/*! RXDS
46651 * 0b0..Receive in progress
46652 * 0b1..Receiver is IDLE
46653 */
46654#define UART_USR1_RXDS(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RXDS_SHIFT)) & UART_USR1_RXDS_MASK)
46655#define UART_USR1_DTRD_MASK (0x80U)
46656#define UART_USR1_DTRD_SHIFT (7U)
46657#define UART_USR1_DTRD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_DTRD_SHIFT)) & UART_USR1_DTRD_MASK)
46658#define UART_USR1_AGTIM_MASK (0x100U)
46659#define UART_USR1_AGTIM_SHIFT (8U)
46660/*! AGTIM
46661 * 0b0..AGTIM is not active
46662 * 0b1..AGTIM is active (write 1 to clear)
46663 */
46664#define UART_USR1_AGTIM(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_AGTIM_SHIFT)) & UART_USR1_AGTIM_MASK)
46665#define UART_USR1_RRDY_MASK (0x200U)
46666#define UART_USR1_RRDY_SHIFT (9U)
46667/*! RRDY
46668 * 0b0..No character ready
46669 * 0b1..Character(s) ready (interrupt posted)
46670 */
46671#define UART_USR1_RRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RRDY_SHIFT)) & UART_USR1_RRDY_MASK)
46672#define UART_USR1_FRAMERR_MASK (0x400U)
46673#define UART_USR1_FRAMERR_SHIFT (10U)
46674/*! FRAMERR
46675 * 0b0..No frame error detected
46676 * 0b1..Frame error detected (write 1 to clear)
46677 */
46678#define UART_USR1_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_FRAMERR_SHIFT)) & UART_USR1_FRAMERR_MASK)
46679#define UART_USR1_ESCF_MASK (0x800U)
46680#define UART_USR1_ESCF_SHIFT (11U)
46681/*! ESCF
46682 * 0b0..No escape sequence detected
46683 * 0b1..Escape sequence detected (write 1 to clear).
46684 */
46685#define UART_USR1_ESCF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_ESCF_SHIFT)) & UART_USR1_ESCF_MASK)
46686#define UART_USR1_RTSD_MASK (0x1000U)
46687#define UART_USR1_RTSD_SHIFT (12U)
46688/*! RTSD
46689 * 0b0..RTS_B pin did not change state since last cleared
46690 * 0b1..RTS_B pin changed state (write 1 to clear)
46691 */
46692#define UART_USR1_RTSD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSD_SHIFT)) & UART_USR1_RTSD_MASK)
46693#define UART_USR1_TRDY_MASK (0x2000U)
46694#define UART_USR1_TRDY_SHIFT (13U)
46695/*! TRDY
46696 * 0b0..The transmitter does not require data
46697 * 0b1..The transmitter requires data (interrupt posted)
46698 */
46699#define UART_USR1_TRDY(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_TRDY_SHIFT)) & UART_USR1_TRDY_MASK)
46700#define UART_USR1_RTSS_MASK (0x4000U)
46701#define UART_USR1_RTSS_SHIFT (14U)
46702/*! RTSS
46703 * 0b0..The RTS_B module input is high (inactive)
46704 * 0b1..The RTS_B module input is low (active)
46705 */
46706#define UART_USR1_RTSS(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_RTSS_SHIFT)) & UART_USR1_RTSS_MASK)
46707#define UART_USR1_PARITYERR_MASK (0x8000U)
46708#define UART_USR1_PARITYERR_SHIFT (15U)
46709/*! PARITYERR
46710 * 0b0..No parity error detected
46711 * 0b1..Parity error detected (write 1 to clear)
46712 */
46713#define UART_USR1_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR1_PARITYERR_SHIFT)) & UART_USR1_PARITYERR_MASK)
46714/*! @} */
46715
46716/*! @name USR2 - UART Status Register 2 */
46717/*! @{ */
46718#define UART_USR2_RDR_MASK (0x1U)
46719#define UART_USR2_RDR_SHIFT (0U)
46720/*! RDR
46721 * 0b0..No receive data ready
46722 * 0b1..Receive data ready
46723 */
46724#define UART_USR2_RDR(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RDR_SHIFT)) & UART_USR2_RDR_MASK)
46725#define UART_USR2_ORE_MASK (0x2U)
46726#define UART_USR2_ORE_SHIFT (1U)
46727/*! ORE
46728 * 0b0..No overrun error
46729 * 0b1..Overrun error (write 1 to clear)
46730 */
46731#define UART_USR2_ORE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ORE_SHIFT)) & UART_USR2_ORE_MASK)
46732#define UART_USR2_BRCD_MASK (0x4U)
46733#define UART_USR2_BRCD_SHIFT (2U)
46734/*! BRCD
46735 * 0b0..No BREAK condition was detected
46736 * 0b1..A BREAK condition was detected (write 1 to clear)
46737 */
46738#define UART_USR2_BRCD(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_BRCD_SHIFT)) & UART_USR2_BRCD_MASK)
46739#define UART_USR2_TXDC_MASK (0x8U)
46740#define UART_USR2_TXDC_SHIFT (3U)
46741/*! TXDC
46742 * 0b0..Transmit is incomplete
46743 * 0b1..Transmit is complete
46744 */
46745#define UART_USR2_TXDC(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXDC_SHIFT)) & UART_USR2_TXDC_MASK)
46746#define UART_USR2_RTSF_MASK (0x10U)
46747#define UART_USR2_RTSF_SHIFT (4U)
46748/*! RTSF
46749 * 0b0..Programmed edge not detected on RTS_B
46750 * 0b1..Programmed edge detected on RTS_B (write 1 to clear)
46751 */
46752#define UART_USR2_RTSF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RTSF_SHIFT)) & UART_USR2_RTSF_MASK)
46753#define UART_USR2_DCDIN_MASK (0x20U)
46754#define UART_USR2_DCDIN_SHIFT (5U)
46755#define UART_USR2_DCDIN(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDIN_SHIFT)) & UART_USR2_DCDIN_MASK)
46756#define UART_USR2_DCDDELT_MASK (0x40U)
46757#define UART_USR2_DCDDELT_SHIFT (6U)
46758#define UART_USR2_DCDDELT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DCDDELT_SHIFT)) & UART_USR2_DCDDELT_MASK)
46759#define UART_USR2_WAKE_MASK (0x80U)
46760#define UART_USR2_WAKE_SHIFT (7U)
46761/*! WAKE
46762 * 0b0..start bit not detected
46763 * 0b1..start bit detected (write 1 to clear)
46764 */
46765#define UART_USR2_WAKE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_WAKE_SHIFT)) & UART_USR2_WAKE_MASK)
46766#define UART_USR2_IRINT_MASK (0x100U)
46767#define UART_USR2_IRINT_SHIFT (8U)
46768/*! IRINT
46769 * 0b0..no edge detected
46770 * 0b1..valid edge detected (write 1 to clear)
46771 */
46772#define UART_USR2_IRINT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_IRINT_SHIFT)) & UART_USR2_IRINT_MASK)
46773#define UART_USR2_RIIN_MASK (0x200U)
46774#define UART_USR2_RIIN_SHIFT (9U)
46775#define UART_USR2_RIIN(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIIN_SHIFT)) & UART_USR2_RIIN_MASK)
46776#define UART_USR2_RIDELT_MASK (0x400U)
46777#define UART_USR2_RIDELT_SHIFT (10U)
46778#define UART_USR2_RIDELT(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_RIDELT_SHIFT)) & UART_USR2_RIDELT_MASK)
46779#define UART_USR2_ACST_MASK (0x800U)
46780#define UART_USR2_ACST_SHIFT (11U)
46781/*! ACST
46782 * 0b0..Measurement of bit length not finished (in autobaud)
46783 * 0b1..Measurement of bit length finished (in autobaud). (write 1 to clear)
46784 */
46785#define UART_USR2_ACST(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ACST_SHIFT)) & UART_USR2_ACST_MASK)
46786#define UART_USR2_IDLE_MASK (0x1000U)
46787#define UART_USR2_IDLE_SHIFT (12U)
46788/*! IDLE
46789 * 0b0..No idle condition detected
46790 * 0b1..Idle condition detected (write 1 to clear)
46791 */
46792#define UART_USR2_IDLE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_IDLE_SHIFT)) & UART_USR2_IDLE_MASK)
46793#define UART_USR2_DTRF_MASK (0x2000U)
46794#define UART_USR2_DTRF_SHIFT (13U)
46795#define UART_USR2_DTRF(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_DTRF_SHIFT)) & UART_USR2_DTRF_MASK)
46796#define UART_USR2_TXFE_MASK (0x4000U)
46797#define UART_USR2_TXFE_SHIFT (14U)
46798/*! TXFE
46799 * 0b0..The transmit buffer (TxFIFO) is not empty
46800 * 0b1..The transmit buffer (TxFIFO) is empty
46801 */
46802#define UART_USR2_TXFE(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_TXFE_SHIFT)) & UART_USR2_TXFE_MASK)
46803#define UART_USR2_ADET_MASK (0x8000U)
46804#define UART_USR2_ADET_SHIFT (15U)
46805/*! ADET
46806 * 0b0..ASCII "A" or "a" was not received
46807 * 0b1..ASCII "A" or "a" was received (write 1 to clear)
46808 */
46809#define UART_USR2_ADET(x) (((uint32_t)(((uint32_t)(x)) << UART_USR2_ADET_SHIFT)) & UART_USR2_ADET_MASK)
46810/*! @} */
46811
46812/*! @name UESC - UART Escape Character Register */
46813/*! @{ */
46814#define UART_UESC_ESC_CHAR_MASK (0xFFU)
46815#define UART_UESC_ESC_CHAR_SHIFT (0U)
46816#define UART_UESC_ESC_CHAR(x) (((uint32_t)(((uint32_t)(x)) << UART_UESC_ESC_CHAR_SHIFT)) & UART_UESC_ESC_CHAR_MASK)
46817/*! @} */
46818
46819/*! @name UTIM - UART Escape Timer Register */
46820/*! @{ */
46821#define UART_UTIM_TIM_MASK (0xFFFU)
46822#define UART_UTIM_TIM_SHIFT (0U)
46823#define UART_UTIM_TIM(x) (((uint32_t)(((uint32_t)(x)) << UART_UTIM_TIM_SHIFT)) & UART_UTIM_TIM_MASK)
46824/*! @} */
46825
46826/*! @name UBIR - UART BRM Incremental Register */
46827/*! @{ */
46828#define UART_UBIR_INC_MASK (0xFFFFU)
46829#define UART_UBIR_INC_SHIFT (0U)
46830#define UART_UBIR_INC(x) (((uint32_t)(((uint32_t)(x)) << UART_UBIR_INC_SHIFT)) & UART_UBIR_INC_MASK)
46831/*! @} */
46832
46833/*! @name UBMR - UART BRM Modulator Register */
46834/*! @{ */
46835#define UART_UBMR_MOD_MASK (0xFFFFU)
46836#define UART_UBMR_MOD_SHIFT (0U)
46837#define UART_UBMR_MOD(x) (((uint32_t)(((uint32_t)(x)) << UART_UBMR_MOD_SHIFT)) & UART_UBMR_MOD_MASK)
46838/*! @} */
46839
46840/*! @name UBRC - UART Baud Rate Count Register */
46841/*! @{ */
46842#define UART_UBRC_BCNT_MASK (0xFFFFU)
46843#define UART_UBRC_BCNT_SHIFT (0U)
46844#define UART_UBRC_BCNT(x) (((uint32_t)(((uint32_t)(x)) << UART_UBRC_BCNT_SHIFT)) & UART_UBRC_BCNT_MASK)
46845/*! @} */
46846
46847/*! @name ONEMS - UART One Millisecond Register */
46848/*! @{ */
46849#define UART_ONEMS_ONEMS_MASK (0xFFFFFFU)
46850#define UART_ONEMS_ONEMS_SHIFT (0U)
46851#define UART_ONEMS_ONEMS(x) (((uint32_t)(((uint32_t)(x)) << UART_ONEMS_ONEMS_SHIFT)) & UART_ONEMS_ONEMS_MASK)
46852/*! @} */
46853
46854/*! @name UTS - UART Test Register */
46855/*! @{ */
46856#define UART_UTS_SOFTRST_MASK (0x1U)
46857#define UART_UTS_SOFTRST_SHIFT (0U)
46858/*! SOFTRST
46859 * 0b0..Software reset inactive
46860 * 0b1..Software reset active
46861 */
46862#define UART_UTS_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_SOFTRST_SHIFT)) & UART_UTS_SOFTRST_MASK)
46863#define UART_UTS_RXFULL_MASK (0x8U)
46864#define UART_UTS_RXFULL_SHIFT (3U)
46865/*! RXFULL
46866 * 0b0..The RxFIFO is not full
46867 * 0b1..The RxFIFO is full
46868 */
46869#define UART_UTS_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXFULL_SHIFT)) & UART_UTS_RXFULL_MASK)
46870#define UART_UTS_TXFULL_MASK (0x10U)
46871#define UART_UTS_TXFULL_SHIFT (4U)
46872/*! TXFULL
46873 * 0b0..The TxFIFO is not full
46874 * 0b1..The TxFIFO is full
46875 */
46876#define UART_UTS_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXFULL_SHIFT)) & UART_UTS_TXFULL_MASK)
46877#define UART_UTS_RXEMPTY_MASK (0x20U)
46878#define UART_UTS_RXEMPTY_SHIFT (5U)
46879/*! RXEMPTY
46880 * 0b0..The RxFIFO is not empty
46881 * 0b1..The RxFIFO is empty
46882 */
46883#define UART_UTS_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXEMPTY_SHIFT)) & UART_UTS_RXEMPTY_MASK)
46884#define UART_UTS_TXEMPTY_MASK (0x40U)
46885#define UART_UTS_TXEMPTY_SHIFT (6U)
46886/*! TXEMPTY
46887 * 0b0..The TxFIFO is not empty
46888 * 0b1..The TxFIFO is empty
46889 */
46890#define UART_UTS_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_TXEMPTY_SHIFT)) & UART_UTS_TXEMPTY_MASK)
46891#define UART_UTS_RXDBG_MASK (0x200U)
46892#define UART_UTS_RXDBG_SHIFT (9U)
46893/*! RXDBG
46894 * 0b0..rx fifo read pointer does not increment
46895 * 0b1..rx_fifo read pointer increments as normal
46896 */
46897#define UART_UTS_RXDBG(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_RXDBG_SHIFT)) & UART_UTS_RXDBG_MASK)
46898#define UART_UTS_LOOPIR_MASK (0x400U)
46899#define UART_UTS_LOOPIR_SHIFT (10U)
46900/*! LOOPIR
46901 * 0b0..No IR loop
46902 * 0b1..Connect IR transmitter to IR receiver
46903 */
46904#define UART_UTS_LOOPIR(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOPIR_SHIFT)) & UART_UTS_LOOPIR_MASK)
46905#define UART_UTS_DBGEN_MASK (0x800U)
46906#define UART_UTS_DBGEN_SHIFT (11U)
46907/*! DBGEN
46908 * 0b0..UART will go into debug mode when debug_req is HIGH
46909 * 0b1..UART will not go into debug mode even if debug_req is HIGH
46910 */
46911#define UART_UTS_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_DBGEN_SHIFT)) & UART_UTS_DBGEN_MASK)
46912#define UART_UTS_LOOP_MASK (0x1000U)
46913#define UART_UTS_LOOP_SHIFT (12U)
46914/*! LOOP
46915 * 0b0..Normal receiver operation
46916 * 0b1..Internally connect the transmitter output to the receiver input
46917 */
46918#define UART_UTS_LOOP(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_LOOP_SHIFT)) & UART_UTS_LOOP_MASK)
46919#define UART_UTS_FRCPERR_MASK (0x2000U)
46920#define UART_UTS_FRCPERR_SHIFT (13U)
46921/*! FRCPERR
46922 * 0b0..Generate normal parity
46923 * 0b1..Generate inverted parity (error)
46924 */
46925#define UART_UTS_FRCPERR(x) (((uint32_t)(((uint32_t)(x)) << UART_UTS_FRCPERR_SHIFT)) & UART_UTS_FRCPERR_MASK)
46926/*! @} */
46927
46928/*! @name UMCR - UART RS-485 Mode Control Register */
46929/*! @{ */
46930#define UART_UMCR_MDEN_MASK (0x1U)
46931#define UART_UMCR_MDEN_SHIFT (0U)
46932/*! MDEN
46933 * 0b0..Normal RS-232 or IrDA mode, see for detail.
46934 * 0b1..Enable RS-485 mode, see for detail
46935 */
46936#define UART_UMCR_MDEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_MDEN_SHIFT)) & UART_UMCR_MDEN_MASK)
46937#define UART_UMCR_SLAM_MASK (0x2U)
46938#define UART_UMCR_SLAM_SHIFT (1U)
46939/*! SLAM
46940 * 0b0..Select Normal Address Detect mode
46941 * 0b1..Select Automatic Address Detect mode
46942 */
46943#define UART_UMCR_SLAM(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLAM_SHIFT)) & UART_UMCR_SLAM_MASK)
46944#define UART_UMCR_TXB8_MASK (0x4U)
46945#define UART_UMCR_TXB8_SHIFT (2U)
46946/*! TXB8
46947 * 0b0..0 will be transmitted as the RS485 9th data bit
46948 * 0b1..1 will be transmitted as the RS485 9th data bit
46949 */
46950#define UART_UMCR_TXB8(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_TXB8_SHIFT)) & UART_UMCR_TXB8_MASK)
46951#define UART_UMCR_SADEN_MASK (0x8U)
46952#define UART_UMCR_SADEN_SHIFT (3U)
46953/*! SADEN
46954 * 0b0..Disable RS-485 Slave Address Detected Interrupt
46955 * 0b1..Enable RS-485 Slave Address Detected Interrupt
46956 */
46957#define UART_UMCR_SADEN(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SADEN_SHIFT)) & UART_UMCR_SADEN_MASK)
46958#define UART_UMCR_SLADDR_MASK (0xFF00U)
46959#define UART_UMCR_SLADDR_SHIFT (8U)
46960#define UART_UMCR_SLADDR(x) (((uint32_t)(((uint32_t)(x)) << UART_UMCR_SLADDR_SHIFT)) & UART_UMCR_SLADDR_MASK)
46961/*! @} */
46962
46963/*!
46964 * @}
46965 */ /* end of group UART_Register_Masks */
46966
46967/* UART - Peripheral instance base addresses */
46968/** Peripheral UART1 base address */
46969#define UART1_BASE (0x30860000u)
46970/** Peripheral UART1 base pointer */
46971#define UART1 ((UART_Type *)UART1_BASE)
46972/** Peripheral UART2 base address */
46973#define UART2_BASE (0x30890000u)
46974/** Peripheral UART2 base pointer */
46975#define UART2 ((UART_Type *)UART2_BASE)
46976/** Peripheral UART3 base address */
46977#define UART3_BASE (0x30880000u)
46978/** Peripheral UART3 base pointer */
46979#define UART3 ((UART_Type *)UART3_BASE)
46980/** Peripheral UART4 base address */
46981#define UART4_BASE (0x30A60000u)
46982/** Peripheral UART4 base pointer */
46983#define UART4 ((UART_Type *)UART4_BASE)
46984/** Array initializer of UART peripheral base addresses */
46985#define UART_BASE_ADDRS \
46986 { \
46987 0u, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE \
46988 }
46989/** Array initializer of UART peripheral base pointers */
46990#define UART_BASE_PTRS \
46991 { \
46992 (UART_Type *)0u, UART1, UART2, UART3, UART4 \
46993 }
46994/** Interrupt vectors for the UART peripheral type */
46995#define UART_IRQS \
46996 { \
46997 NotAvail_IRQn, UART1_IRQn, UART2_IRQn, UART3_IRQn, UART4_IRQn \
46998 }
46999
47000/*!
47001 * @}
47002 */ /* end of group UART_Peripheral_Access_Layer */
47003
47004/* ----------------------------------------------------------------------------
47005 -- USB Peripheral Access Layer
47006 ---------------------------------------------------------------------------- */
47007
47008/*!
47009 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
47010 * @{
47011 */
47012
47013/** USB - Register Layout Typedef */
47014typedef struct
47015{
47016 __I uint32_t ID; /**< Identification register, offset: 0x0 */
47017 __I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */
47018 __I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */
47019 __I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */
47020 __I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */
47021 __I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */
47022 uint8_t RESERVED_0[104];
47023 __IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */
47024 __IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */
47025 __IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */
47026 __IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */
47027 __IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */
47028 uint8_t RESERVED_1[108];
47029 __I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */
47030 uint8_t RESERVED_2[1];
47031 __I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */
47032 __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */
47033 __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */
47034 uint8_t RESERVED_3[20];
47035 __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */
47036 uint8_t RESERVED_4[2];
47037 __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */
47038 uint8_t RESERVED_5[24];
47039 __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */
47040 __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */
47041 __IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */
47042 __IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */
47043 uint8_t RESERVED_6[4];
47044 union
47045 { /* offset: 0x154 */
47046 __IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */
47047 __IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */
47048 };
47049 union
47050 { /* offset: 0x158 */
47051 __IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */
47052 __IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */
47053 };
47054 uint8_t RESERVED_7[4];
47055 __IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */
47056 __IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */
47057 uint8_t RESERVED_8[16];
47058 __IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */
47059 __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */
47060 __I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */
47061 __IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */
47062 uint8_t RESERVED_9[28];
47063 __IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */
47064 __IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */
47065 __IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */
47066 __IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */
47067 __IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */
47068 __I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */
47069 __IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */
47070 __IO uint32_t ENDPTCTRL[8]; /**< Endpoint Control0..Endpoint Control 7, array offset: 0x1C0, array step: 0x4 */
47071} USB_Type;
47072
47073/* ----------------------------------------------------------------------------
47074 -- USB Register Masks
47075 ---------------------------------------------------------------------------- */
47076
47077/*!
47078 * @addtogroup USB_Register_Masks USB Register Masks
47079 * @{
47080 */
47081
47082/*! @name ID - Identification register */
47083/*! @{ */
47084#define USB_ID_ID_MASK (0x3FU)
47085#define USB_ID_ID_SHIFT (0U)
47086#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)
47087#define USB_ID_NID_MASK (0x3F00U)
47088#define USB_ID_NID_SHIFT (8U)
47089#define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)
47090#define USB_ID_REVISION_MASK (0xFF0000U)
47091#define USB_ID_REVISION_SHIFT (16U)
47092#define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)
47093/*! @} */
47094
47095/*! @name HWGENERAL - Hardware General */
47096/*! @{ */
47097#define USB_HWGENERAL_PHYW_MASK (0x30U)
47098#define USB_HWGENERAL_PHYW_SHIFT (4U)
47099/*! PHYW
47100 * 0b11..Reset to 16 bit wide data bus Software programmable
47101 */
47102#define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)
47103#define USB_HWGENERAL_PHYM_MASK (0x1C0U)
47104#define USB_HWGENERAL_PHYM_SHIFT (6U)
47105/*! PHYM
47106 * 0b000..UTMI/UMTI+
47107 * 0b001..ULPI DDR
47108 * 0b010..ULPI
47109 * 0b011..Serial Only
47110 * 0b100..Software programmable - reset to UTMI/UTMI+
47111 * 0b101..Software programmable - reset to ULPI DDR
47112 * 0b110..Software programmable - reset to ULPI
47113 * 0b111..Software programmable - reset to Serial
47114 */
47115#define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)
47116#define USB_HWGENERAL_SM_MASK (0x600U)
47117#define USB_HWGENERAL_SM_SHIFT (9U)
47118/*! SM
47119 * 0b00..No Serial Engine, always use parallel signalling.
47120 * 0b01..Serial Engine present, always use serial signalling for FS/LS.
47121 * 0b10..Software programmable - Reset to use parallel signalling for FS/LS
47122 * 0b11..Software programmable - Reset to use serial signalling for FS/LS
47123 */
47124#define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)
47125/*! @} */
47126
47127/*! @name HWHOST - Host Hardware Parameters */
47128/*! @{ */
47129#define USB_HWHOST_HC_MASK (0x1U)
47130#define USB_HWHOST_HC_SHIFT (0U)
47131/*! HC
47132 * 0b1..Supported
47133 * 0b0..Not supported
47134 */
47135#define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)
47136#define USB_HWHOST_NPORT_MASK (0xEU)
47137#define USB_HWHOST_NPORT_SHIFT (1U)
47138#define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)
47139/*! @} */
47140
47141/*! @name HWDEVICE - Device Hardware Parameters */
47142/*! @{ */
47143#define USB_HWDEVICE_DC_MASK (0x1U)
47144#define USB_HWDEVICE_DC_SHIFT (0U)
47145/*! DC
47146 * 0b1..Supported
47147 * 0b0..Not supported
47148 */
47149#define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)
47150#define USB_HWDEVICE_DEVEP_MASK (0x3EU)
47151#define USB_HWDEVICE_DEVEP_SHIFT (1U)
47152#define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)
47153/*! @} */
47154
47155/*! @name HWTXBUF - TX Buffer Hardware Parameters */
47156/*! @{ */
47157#define USB_HWTXBUF_TXBURST_MASK (0xFFU)
47158#define USB_HWTXBUF_TXBURST_SHIFT (0U)
47159#define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)
47160#define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U)
47161#define USB_HWTXBUF_TXCHANADD_SHIFT (16U)
47162#define USB_HWTXBUF_TXCHANADD(x) \
47163 (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)
47164/*! @} */
47165
47166/*! @name HWRXBUF - RX Buffer Hardware Parameters */
47167/*! @{ */
47168#define USB_HWRXBUF_RXBURST_MASK (0xFFU)
47169#define USB_HWRXBUF_RXBURST_SHIFT (0U)
47170#define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)
47171#define USB_HWRXBUF_RXADD_MASK (0xFF00U)
47172#define USB_HWRXBUF_RXADD_SHIFT (8U)
47173#define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)
47174/*! @} */
47175
47176/*! @name GPTIMER0LD - General Purpose Timer #0 Load */
47177/*! @{ */
47178#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)
47179#define USB_GPTIMER0LD_GPTLD_SHIFT (0U)
47180#define USB_GPTIMER0LD_GPTLD(x) \
47181 (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)
47182/*! @} */
47183
47184/*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */
47185/*! @{ */
47186#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU)
47187#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U)
47188#define USB_GPTIMER0CTRL_GPTCNT(x) \
47189 (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)
47190#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U)
47191#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U)
47192/*! GPTMODE
47193 * 0b0..One Shot Mode
47194 * 0b1..Repeat Mode
47195 */
47196#define USB_GPTIMER0CTRL_GPTMODE(x) \
47197 (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)
47198#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U)
47199#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U)
47200/*! GPTRST
47201 * 0b0..No action
47202 * 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD
47203 */
47204#define USB_GPTIMER0CTRL_GPTRST(x) \
47205 (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)
47206#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U)
47207#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U)
47208/*! GPTRUN
47209 * 0b0..Stop counting
47210 * 0b1..Run
47211 */
47212#define USB_GPTIMER0CTRL_GPTRUN(x) \
47213 (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)
47214/*! @} */
47215
47216/*! @name GPTIMER1LD - General Purpose Timer #1 Load */
47217/*! @{ */
47218#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)
47219#define USB_GPTIMER1LD_GPTLD_SHIFT (0U)
47220#define USB_GPTIMER1LD_GPTLD(x) \
47221 (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)
47222/*! @} */
47223
47224/*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */
47225/*! @{ */
47226#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU)
47227#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U)
47228#define USB_GPTIMER1CTRL_GPTCNT(x) \
47229 (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)
47230#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U)
47231#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U)
47232/*! GPTMODE
47233 * 0b0..One Shot Mode
47234 * 0b1..Repeat Mode
47235 */
47236#define USB_GPTIMER1CTRL_GPTMODE(x) \
47237 (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)
47238#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U)
47239#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U)
47240/*! GPTRST
47241 * 0b0..No action
47242 * 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD
47243 */
47244#define USB_GPTIMER1CTRL_GPTRST(x) \
47245 (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)
47246#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U)
47247#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U)
47248/*! GPTRUN
47249 * 0b0..Stop counting
47250 * 0b1..Run
47251 */
47252#define USB_GPTIMER1CTRL_GPTRUN(x) \
47253 (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)
47254/*! @} */
47255
47256/*! @name SBUSCFG - System Bus Config */
47257/*! @{ */
47258#define USB_SBUSCFG_AHBBRST_MASK (0x7U)
47259#define USB_SBUSCFG_AHBBRST_SHIFT (0U)
47260/*! AHBBRST
47261 * 0b000..Incremental burst of unspecified length only
47262 * 0b001..INCR4 burst, then single transfer
47263 * 0b010..INCR8 burst, INCR4 burst, then single transfer
47264 * 0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer
47265 * 0b100..Reserved, don't use
47266 * 0b101..INCR4 burst, then incremental burst of unspecified length
47267 * 0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length
47268 * 0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length
47269 */
47270#define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)
47271/*! @} */
47272
47273/*! @name CAPLENGTH - Capability Registers Length */
47274/*! @{ */
47275#define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU)
47276#define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U)
47277#define USB_CAPLENGTH_CAPLENGTH(x) \
47278 (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)
47279/*! @} */
47280
47281/*! @name HCIVERSION - Host Controller Interface Version */
47282/*! @{ */
47283#define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU)
47284#define USB_HCIVERSION_HCIVERSION_SHIFT (0U)
47285#define USB_HCIVERSION_HCIVERSION(x) \
47286 (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)
47287/*! @} */
47288
47289/*! @name HCSPARAMS - Host Controller Structural Parameters */
47290/*! @{ */
47291#define USB_HCSPARAMS_N_PORTS_MASK (0xFU)
47292#define USB_HCSPARAMS_N_PORTS_SHIFT (0U)
47293#define USB_HCSPARAMS_N_PORTS(x) \
47294 (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)
47295#define USB_HCSPARAMS_PPC_MASK (0x10U)
47296#define USB_HCSPARAMS_PPC_SHIFT (4U)
47297#define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)
47298#define USB_HCSPARAMS_N_PCC_MASK (0xF00U)
47299#define USB_HCSPARAMS_N_PCC_SHIFT (8U)
47300#define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)
47301#define USB_HCSPARAMS_N_CC_MASK (0xF000U)
47302#define USB_HCSPARAMS_N_CC_SHIFT (12U)
47303/*! N_CC
47304 * 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported.
47305 * 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported.
47306 */
47307#define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)
47308#define USB_HCSPARAMS_PI_MASK (0x10000U)
47309#define USB_HCSPARAMS_PI_SHIFT (16U)
47310#define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)
47311#define USB_HCSPARAMS_N_PTT_MASK (0xF00000U)
47312#define USB_HCSPARAMS_N_PTT_SHIFT (20U)
47313#define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)
47314#define USB_HCSPARAMS_N_TT_MASK (0xF000000U)
47315#define USB_HCSPARAMS_N_TT_SHIFT (24U)
47316#define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)
47317/*! @} */
47318
47319/*! @name HCCPARAMS - Host Controller Capability Parameters */
47320/*! @{ */
47321#define USB_HCCPARAMS_ADC_MASK (0x1U)
47322#define USB_HCCPARAMS_ADC_SHIFT (0U)
47323#define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)
47324#define USB_HCCPARAMS_PFL_MASK (0x2U)
47325#define USB_HCCPARAMS_PFL_SHIFT (1U)
47326#define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)
47327#define USB_HCCPARAMS_ASP_MASK (0x4U)
47328#define USB_HCCPARAMS_ASP_SHIFT (2U)
47329#define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)
47330#define USB_HCCPARAMS_IST_MASK (0xF0U)
47331#define USB_HCCPARAMS_IST_SHIFT (4U)
47332#define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)
47333#define USB_HCCPARAMS_EECP_MASK (0xFF00U)
47334#define USB_HCCPARAMS_EECP_SHIFT (8U)
47335#define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)
47336/*! @} */
47337
47338/*! @name DCIVERSION - Device Controller Interface Version */
47339/*! @{ */
47340#define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU)
47341#define USB_DCIVERSION_DCIVERSION_SHIFT (0U)
47342#define USB_DCIVERSION_DCIVERSION(x) \
47343 (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)
47344/*! @} */
47345
47346/*! @name DCCPARAMS - Device Controller Capability Parameters */
47347/*! @{ */
47348#define USB_DCCPARAMS_DEN_MASK (0x1FU)
47349#define USB_DCCPARAMS_DEN_SHIFT (0U)
47350#define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)
47351#define USB_DCCPARAMS_DC_MASK (0x80U)
47352#define USB_DCCPARAMS_DC_SHIFT (7U)
47353#define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)
47354#define USB_DCCPARAMS_HC_MASK (0x100U)
47355#define USB_DCCPARAMS_HC_SHIFT (8U)
47356#define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)
47357/*! @} */
47358
47359/*! @name USBCMD - USB Command Register */
47360/*! @{ */
47361#define USB_USBCMD_RS_MASK (0x1U)
47362#define USB_USBCMD_RS_SHIFT (0U)
47363#define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)
47364#define USB_USBCMD_RST_MASK (0x2U)
47365#define USB_USBCMD_RST_SHIFT (1U)
47366#define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)
47367#define USB_USBCMD_FS_1_MASK (0xCU)
47368#define USB_USBCMD_FS_1_SHIFT (2U)
47369#define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)
47370#define USB_USBCMD_PSE_MASK (0x10U)
47371#define USB_USBCMD_PSE_SHIFT (4U)
47372/*! PSE
47373 * 0b0..Do not process the Periodic Schedule
47374 * 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule.
47375 */
47376#define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)
47377#define USB_USBCMD_ASE_MASK (0x20U)
47378#define USB_USBCMD_ASE_SHIFT (5U)
47379/*! ASE
47380 * 0b0..Do not process the Asynchronous Schedule.
47381 * 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
47382 */
47383#define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)
47384#define USB_USBCMD_IAA_MASK (0x40U)
47385#define USB_USBCMD_IAA_SHIFT (6U)
47386#define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)
47387#define USB_USBCMD_ASP_MASK (0x300U)
47388#define USB_USBCMD_ASP_SHIFT (8U)
47389#define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)
47390#define USB_USBCMD_ASPE_MASK (0x800U)
47391#define USB_USBCMD_ASPE_SHIFT (11U)
47392#define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)
47393#define USB_USBCMD_SUTW_MASK (0x2000U)
47394#define USB_USBCMD_SUTW_SHIFT (13U)
47395#define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)
47396#define USB_USBCMD_ATDTW_MASK (0x4000U)
47397#define USB_USBCMD_ATDTW_SHIFT (14U)
47398#define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)
47399#define USB_USBCMD_FS_2_MASK (0x8000U)
47400#define USB_USBCMD_FS_2_SHIFT (15U)
47401/*! FS_2
47402 * 0b0..1024 elements (4096 bytes) Default value
47403 * 0b1..512 elements (2048 bytes)
47404 */
47405#define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)
47406#define USB_USBCMD_ITC_MASK (0xFF0000U)
47407#define USB_USBCMD_ITC_SHIFT (16U)
47408/*! ITC
47409 * 0b00000000..Immediate (no threshold)
47410 * 0b00000001..1 micro-frame
47411 * 0b00000010..2 micro-frames
47412 * 0b00000100..4 micro-frames
47413 * 0b00001000..8 micro-frames
47414 * 0b00010000..16 micro-frames
47415 * 0b00100000..32 micro-frames
47416 * 0b01000000..64 micro-frames
47417 */
47418#define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)
47419/*! @} */
47420
47421/*! @name USBSTS - USB Status Register */
47422/*! @{ */
47423#define USB_USBSTS_UI_MASK (0x1U)
47424#define USB_USBSTS_UI_SHIFT (0U)
47425#define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)
47426#define USB_USBSTS_UEI_MASK (0x2U)
47427#define USB_USBSTS_UEI_SHIFT (1U)
47428#define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)
47429#define USB_USBSTS_PCI_MASK (0x4U)
47430#define USB_USBSTS_PCI_SHIFT (2U)
47431#define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)
47432#define USB_USBSTS_FRI_MASK (0x8U)
47433#define USB_USBSTS_FRI_SHIFT (3U)
47434#define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)
47435#define USB_USBSTS_SEI_MASK (0x10U)
47436#define USB_USBSTS_SEI_SHIFT (4U)
47437#define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)
47438#define USB_USBSTS_AAI_MASK (0x20U)
47439#define USB_USBSTS_AAI_SHIFT (5U)
47440#define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)
47441#define USB_USBSTS_URI_MASK (0x40U)
47442#define USB_USBSTS_URI_SHIFT (6U)
47443#define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)
47444#define USB_USBSTS_SRI_MASK (0x80U)
47445#define USB_USBSTS_SRI_SHIFT (7U)
47446#define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)
47447#define USB_USBSTS_SLI_MASK (0x100U)
47448#define USB_USBSTS_SLI_SHIFT (8U)
47449#define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)
47450#define USB_USBSTS_ULPII_MASK (0x400U)
47451#define USB_USBSTS_ULPII_SHIFT (10U)
47452#define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)
47453#define USB_USBSTS_HCH_MASK (0x1000U)
47454#define USB_USBSTS_HCH_SHIFT (12U)
47455#define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)
47456#define USB_USBSTS_RCL_MASK (0x2000U)
47457#define USB_USBSTS_RCL_SHIFT (13U)
47458#define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)
47459#define USB_USBSTS_PS_MASK (0x4000U)
47460#define USB_USBSTS_PS_SHIFT (14U)
47461#define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)
47462#define USB_USBSTS_AS_MASK (0x8000U)
47463#define USB_USBSTS_AS_SHIFT (15U)
47464#define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)
47465#define USB_USBSTS_NAKI_MASK (0x10000U)
47466#define USB_USBSTS_NAKI_SHIFT (16U)
47467#define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)
47468#define USB_USBSTS_TI0_MASK (0x1000000U)
47469#define USB_USBSTS_TI0_SHIFT (24U)
47470#define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)
47471#define USB_USBSTS_TI1_MASK (0x2000000U)
47472#define USB_USBSTS_TI1_SHIFT (25U)
47473#define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)
47474/*! @} */
47475
47476/*! @name USBINTR - Interrupt Enable Register */
47477/*! @{ */
47478#define USB_USBINTR_UE_MASK (0x1U)
47479#define USB_USBINTR_UE_SHIFT (0U)
47480#define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)
47481#define USB_USBINTR_UEE_MASK (0x2U)
47482#define USB_USBINTR_UEE_SHIFT (1U)
47483#define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)
47484#define USB_USBINTR_PCE_MASK (0x4U)
47485#define USB_USBINTR_PCE_SHIFT (2U)
47486#define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)
47487#define USB_USBINTR_FRE_MASK (0x8U)
47488#define USB_USBINTR_FRE_SHIFT (3U)
47489#define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)
47490#define USB_USBINTR_SEE_MASK (0x10U)
47491#define USB_USBINTR_SEE_SHIFT (4U)
47492#define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)
47493#define USB_USBINTR_AAE_MASK (0x20U)
47494#define USB_USBINTR_AAE_SHIFT (5U)
47495#define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)
47496#define USB_USBINTR_URE_MASK (0x40U)
47497#define USB_USBINTR_URE_SHIFT (6U)
47498#define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)
47499#define USB_USBINTR_SRE_MASK (0x80U)
47500#define USB_USBINTR_SRE_SHIFT (7U)
47501#define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)
47502#define USB_USBINTR_SLE_MASK (0x100U)
47503#define USB_USBINTR_SLE_SHIFT (8U)
47504#define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)
47505#define USB_USBINTR_ULPIE_MASK (0x400U)
47506#define USB_USBINTR_ULPIE_SHIFT (10U)
47507#define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)
47508#define USB_USBINTR_NAKE_MASK (0x10000U)
47509#define USB_USBINTR_NAKE_SHIFT (16U)
47510#define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)
47511#define USB_USBINTR_UAIE_MASK (0x40000U)
47512#define USB_USBINTR_UAIE_SHIFT (18U)
47513#define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)
47514#define USB_USBINTR_UPIE_MASK (0x80000U)
47515#define USB_USBINTR_UPIE_SHIFT (19U)
47516#define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)
47517#define USB_USBINTR_TIE0_MASK (0x1000000U)
47518#define USB_USBINTR_TIE0_SHIFT (24U)
47519#define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)
47520#define USB_USBINTR_TIE1_MASK (0x2000000U)
47521#define USB_USBINTR_TIE1_SHIFT (25U)
47522#define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)
47523/*! @} */
47524
47525/*! @name FRINDEX - USB Frame Index */
47526/*! @{ */
47527#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU)
47528#define USB_FRINDEX_FRINDEX_SHIFT (0U)
47529/*! FRINDEX
47530 * 0b00000000000000..(1024) 12
47531 * 0b00000000000001..(512) 11
47532 * 0b00000000000010..(256) 10
47533 * 0b00000000000011..(128) 9
47534 * 0b00000000000100..(64) 8
47535 * 0b00000000000101..(32) 7
47536 * 0b00000000000110..(16) 6
47537 * 0b00000000000111..(8) 5
47538 */
47539#define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)
47540/*! @} */
47541
47542/*! @name DEVICEADDR - Device Address */
47543/*! @{ */
47544#define USB_DEVICEADDR_USBADRA_MASK (0x1000000U)
47545#define USB_DEVICEADDR_USBADRA_SHIFT (24U)
47546#define USB_DEVICEADDR_USBADRA(x) \
47547 (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)
47548#define USB_DEVICEADDR_USBADR_MASK (0xFE000000U)
47549#define USB_DEVICEADDR_USBADR_SHIFT (25U)
47550#define USB_DEVICEADDR_USBADR(x) \
47551 (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)
47552/*! @} */
47553
47554/*! @name PERIODICLISTBASE - Frame List Base Address */
47555/*! @{ */
47556#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U)
47557#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U)
47558#define USB_PERIODICLISTBASE_BASEADR(x) \
47559 (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)
47560/*! @} */
47561
47562/*! @name ASYNCLISTADDR - Next Asynch. Address */
47563/*! @{ */
47564#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)
47565#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U)
47566#define USB_ASYNCLISTADDR_ASYBASE(x) \
47567 (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)
47568/*! @} */
47569
47570/*! @name ENDPTLISTADDR - Endpoint List Address */
47571/*! @{ */
47572#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U)
47573#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U)
47574#define USB_ENDPTLISTADDR_EPBASE(x) \
47575 (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)
47576/*! @} */
47577
47578/*! @name BURSTSIZE - Programmable Burst Size */
47579/*! @{ */
47580#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU)
47581#define USB_BURSTSIZE_RXPBURST_SHIFT (0U)
47582#define USB_BURSTSIZE_RXPBURST(x) \
47583 (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)
47584#define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U)
47585#define USB_BURSTSIZE_TXPBURST_SHIFT (8U)
47586#define USB_BURSTSIZE_TXPBURST(x) \
47587 (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)
47588/*! @} */
47589
47590/*! @name TXFILLTUNING - TX FIFO Fill Tuning */
47591/*! @{ */
47592#define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU)
47593#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U)
47594#define USB_TXFILLTUNING_TXSCHOH(x) \
47595 (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)
47596#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)
47597#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)
47598#define USB_TXFILLTUNING_TXSCHHEALTH(x) \
47599 (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)
47600#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)
47601#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)
47602#define USB_TXFILLTUNING_TXFIFOTHRES(x) \
47603 (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)
47604/*! @} */
47605
47606/*! @name ENDPTNAK - Endpoint NAK */
47607/*! @{ */
47608#define USB_ENDPTNAK_EPRN_MASK (0xFFU)
47609#define USB_ENDPTNAK_EPRN_SHIFT (0U)
47610#define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)
47611#define USB_ENDPTNAK_EPTN_MASK (0xFF0000U)
47612#define USB_ENDPTNAK_EPTN_SHIFT (16U)
47613#define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)
47614/*! @} */
47615
47616/*! @name ENDPTNAKEN - Endpoint NAK Enable */
47617/*! @{ */
47618#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU)
47619#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U)
47620#define USB_ENDPTNAKEN_EPRNE(x) \
47621 (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)
47622#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U)
47623#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U)
47624#define USB_ENDPTNAKEN_EPTNE(x) \
47625 (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)
47626/*! @} */
47627
47628/*! @name CONFIGFLAG - Configure Flag Register */
47629/*! @{ */
47630#define USB_CONFIGFLAG_CF_MASK (0x1U)
47631#define USB_CONFIGFLAG_CF_SHIFT (0U)
47632/*! CF
47633 * 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller.
47634 * 0b1..Port routing control logic default-routes all ports to this host controller.
47635 */
47636#define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)
47637/*! @} */
47638
47639/*! @name PORTSC1 - Port Status & Control */
47640/*! @{ */
47641#define USB_PORTSC1_CCS_MASK (0x1U)
47642#define USB_PORTSC1_CCS_SHIFT (0U)
47643#define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)
47644#define USB_PORTSC1_CSC_MASK (0x2U)
47645#define USB_PORTSC1_CSC_SHIFT (1U)
47646#define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)
47647#define USB_PORTSC1_PE_MASK (0x4U)
47648#define USB_PORTSC1_PE_SHIFT (2U)
47649#define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)
47650#define USB_PORTSC1_PEC_MASK (0x8U)
47651#define USB_PORTSC1_PEC_SHIFT (3U)
47652#define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)
47653#define USB_PORTSC1_OCA_MASK (0x10U)
47654#define USB_PORTSC1_OCA_SHIFT (4U)
47655/*! OCA
47656 * 0b1..This port currently has an over-current condition
47657 * 0b0..This port does not have an over-current condition.
47658 */
47659#define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)
47660#define USB_PORTSC1_OCC_MASK (0x20U)
47661#define USB_PORTSC1_OCC_SHIFT (5U)
47662#define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)
47663#define USB_PORTSC1_FPR_MASK (0x40U)
47664#define USB_PORTSC1_FPR_SHIFT (6U)
47665#define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)
47666#define USB_PORTSC1_SUSP_MASK (0x80U)
47667#define USB_PORTSC1_SUSP_SHIFT (7U)
47668#define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)
47669#define USB_PORTSC1_PR_MASK (0x100U)
47670#define USB_PORTSC1_PR_SHIFT (8U)
47671#define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)
47672#define USB_PORTSC1_HSP_MASK (0x200U)
47673#define USB_PORTSC1_HSP_SHIFT (9U)
47674#define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)
47675#define USB_PORTSC1_LS_MASK (0xC00U)
47676#define USB_PORTSC1_LS_SHIFT (10U)
47677/*! LS
47678 * 0b00..SE0
47679 * 0b10..J-state
47680 * 0b01..K-state
47681 * 0b11..Undefined
47682 */
47683#define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)
47684#define USB_PORTSC1_PP_MASK (0x1000U)
47685#define USB_PORTSC1_PP_SHIFT (12U)
47686#define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)
47687#define USB_PORTSC1_PO_MASK (0x2000U)
47688#define USB_PORTSC1_PO_SHIFT (13U)
47689#define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)
47690#define USB_PORTSC1_PIC_MASK (0xC000U)
47691#define USB_PORTSC1_PIC_SHIFT (14U)
47692/*! PIC
47693 * 0b00..Port indicators are off
47694 * 0b01..Amber
47695 * 0b10..Green
47696 * 0b11..Undefined
47697 */
47698#define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)
47699#define USB_PORTSC1_PTC_MASK (0xF0000U)
47700#define USB_PORTSC1_PTC_SHIFT (16U)
47701/*! PTC
47702 * 0b0000..TEST_MODE_DISABLE
47703 * 0b0001..J_STATE
47704 * 0b0010..K_STATE
47705 * 0b0011..SE0 (host) / NAK (device)
47706 * 0b0100..Packet
47707 * 0b0101..FORCE_ENABLE_HS
47708 * 0b0110..FORCE_ENABLE_FS
47709 * 0b0111..FORCE_ENABLE_LS
47710 */
47711#define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)
47712#define USB_PORTSC1_WKCN_MASK (0x100000U)
47713#define USB_PORTSC1_WKCN_SHIFT (20U)
47714#define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)
47715#define USB_PORTSC1_WKDC_MASK (0x200000U)
47716#define USB_PORTSC1_WKDC_SHIFT (21U)
47717#define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)
47718#define USB_PORTSC1_WKOC_MASK (0x400000U)
47719#define USB_PORTSC1_WKOC_SHIFT (22U)
47720#define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)
47721#define USB_PORTSC1_PHCD_MASK (0x800000U)
47722#define USB_PORTSC1_PHCD_SHIFT (23U)
47723/*! PHCD
47724 * 0b1..Disable PHY clock
47725 * 0b0..Enable PHY clock
47726 */
47727#define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)
47728#define USB_PORTSC1_PFSC_MASK (0x1000000U)
47729#define USB_PORTSC1_PFSC_SHIFT (24U)
47730/*! PFSC
47731 * 0b1..Forced to full speed
47732 * 0b0..Normal operation
47733 */
47734#define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)
47735#define USB_PORTSC1_PTS_2_MASK (0x2000000U)
47736#define USB_PORTSC1_PTS_2_SHIFT (25U)
47737#define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)
47738#define USB_PORTSC1_PSPD_MASK (0xC000000U)
47739#define USB_PORTSC1_PSPD_SHIFT (26U)
47740/*! PSPD
47741 * 0b00..Full Speed
47742 * 0b01..Low Speed
47743 * 0b10..High Speed
47744 * 0b11..Undefined
47745 */
47746#define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)
47747#define USB_PORTSC1_PTW_MASK (0x10000000U)
47748#define USB_PORTSC1_PTW_SHIFT (28U)
47749/*! PTW
47750 * 0b0..Select the 8-bit UTMI interface [60MHz]
47751 * 0b1..Select the 16-bit UTMI interface [30MHz]
47752 */
47753#define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)
47754#define USB_PORTSC1_STS_MASK (0x20000000U)
47755#define USB_PORTSC1_STS_SHIFT (29U)
47756#define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)
47757#define USB_PORTSC1_PTS_1_MASK (0xC0000000U)
47758#define USB_PORTSC1_PTS_1_SHIFT (30U)
47759#define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)
47760/*! @} */
47761
47762/*! @name OTGSC - On-The-Go Status & control */
47763/*! @{ */
47764#define USB_OTGSC_VD_MASK (0x1U)
47765#define USB_OTGSC_VD_SHIFT (0U)
47766#define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)
47767#define USB_OTGSC_VC_MASK (0x2U)
47768#define USB_OTGSC_VC_SHIFT (1U)
47769#define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)
47770#define USB_OTGSC_OT_MASK (0x8U)
47771#define USB_OTGSC_OT_SHIFT (3U)
47772#define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)
47773#define USB_OTGSC_DP_MASK (0x10U)
47774#define USB_OTGSC_DP_SHIFT (4U)
47775#define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)
47776#define USB_OTGSC_IDPU_MASK (0x20U)
47777#define USB_OTGSC_IDPU_SHIFT (5U)
47778#define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)
47779#define USB_OTGSC_ID_MASK (0x100U)
47780#define USB_OTGSC_ID_SHIFT (8U)
47781#define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)
47782#define USB_OTGSC_AVV_MASK (0x200U)
47783#define USB_OTGSC_AVV_SHIFT (9U)
47784#define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)
47785#define USB_OTGSC_ASV_MASK (0x400U)
47786#define USB_OTGSC_ASV_SHIFT (10U)
47787#define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)
47788#define USB_OTGSC_BSV_MASK (0x800U)
47789#define USB_OTGSC_BSV_SHIFT (11U)
47790#define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)
47791#define USB_OTGSC_BSE_MASK (0x1000U)
47792#define USB_OTGSC_BSE_SHIFT (12U)
47793#define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)
47794#define USB_OTGSC_TOG_1MS_MASK (0x2000U)
47795#define USB_OTGSC_TOG_1MS_SHIFT (13U)
47796#define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)
47797#define USB_OTGSC_DPS_MASK (0x4000U)
47798#define USB_OTGSC_DPS_SHIFT (14U)
47799#define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)
47800#define USB_OTGSC_IDIS_MASK (0x10000U)
47801#define USB_OTGSC_IDIS_SHIFT (16U)
47802#define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)
47803#define USB_OTGSC_AVVIS_MASK (0x20000U)
47804#define USB_OTGSC_AVVIS_SHIFT (17U)
47805#define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)
47806#define USB_OTGSC_ASVIS_MASK (0x40000U)
47807#define USB_OTGSC_ASVIS_SHIFT (18U)
47808#define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)
47809#define USB_OTGSC_BSVIS_MASK (0x80000U)
47810#define USB_OTGSC_BSVIS_SHIFT (19U)
47811#define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)
47812#define USB_OTGSC_BSEIS_MASK (0x100000U)
47813#define USB_OTGSC_BSEIS_SHIFT (20U)
47814#define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)
47815#define USB_OTGSC_STATUS_1MS_MASK (0x200000U)
47816#define USB_OTGSC_STATUS_1MS_SHIFT (21U)
47817#define USB_OTGSC_STATUS_1MS(x) \
47818 (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)
47819#define USB_OTGSC_DPIS_MASK (0x400000U)
47820#define USB_OTGSC_DPIS_SHIFT (22U)
47821#define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)
47822#define USB_OTGSC_IDIE_MASK (0x1000000U)
47823#define USB_OTGSC_IDIE_SHIFT (24U)
47824#define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)
47825#define USB_OTGSC_AVVIE_MASK (0x2000000U)
47826#define USB_OTGSC_AVVIE_SHIFT (25U)
47827#define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)
47828#define USB_OTGSC_ASVIE_MASK (0x4000000U)
47829#define USB_OTGSC_ASVIE_SHIFT (26U)
47830#define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)
47831#define USB_OTGSC_BSVIE_MASK (0x8000000U)
47832#define USB_OTGSC_BSVIE_SHIFT (27U)
47833#define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)
47834#define USB_OTGSC_BSEIE_MASK (0x10000000U)
47835#define USB_OTGSC_BSEIE_SHIFT (28U)
47836#define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)
47837#define USB_OTGSC_EN_1MS_MASK (0x20000000U)
47838#define USB_OTGSC_EN_1MS_SHIFT (29U)
47839#define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)
47840#define USB_OTGSC_DPIE_MASK (0x40000000U)
47841#define USB_OTGSC_DPIE_SHIFT (30U)
47842#define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)
47843/*! @} */
47844
47845/*! @name USBMODE - USB Device Mode */
47846/*! @{ */
47847#define USB_USBMODE_CM_MASK (0x3U)
47848#define USB_USBMODE_CM_SHIFT (0U)
47849/*! CM
47850 * 0b00..Idle [Default for combination host/device]
47851 * 0b01..Reserved
47852 * 0b10..Device Controller [Default for device only controller]
47853 * 0b11..Host Controller [Default for host only controller]
47854 */
47855#define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)
47856#define USB_USBMODE_ES_MASK (0x4U)
47857#define USB_USBMODE_ES_SHIFT (2U)
47858/*! ES
47859 * 0b0..Little Endian [Default]
47860 * 0b1..Big Endian
47861 */
47862#define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)
47863#define USB_USBMODE_SLOM_MASK (0x8U)
47864#define USB_USBMODE_SLOM_SHIFT (3U)
47865/*! SLOM
47866 * 0b0..Setup Lockouts On (default);
47867 * 0b1..Setup Lockouts Off (DCD requires use of Setup Data Buffer Tripwire in USBCMDUSB Command Register .
47868 */
47869#define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)
47870#define USB_USBMODE_SDIS_MASK (0x10U)
47871#define USB_USBMODE_SDIS_SHIFT (4U)
47872#define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)
47873/*! @} */
47874
47875/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */
47876/*! @{ */
47877#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU)
47878#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U)
47879#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) \
47880 (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
47881/*! @} */
47882
47883/*! @name ENDPTPRIME - Endpoint Prime */
47884/*! @{ */
47885#define USB_ENDPTPRIME_PERB_MASK (0xFFU)
47886#define USB_ENDPTPRIME_PERB_SHIFT (0U)
47887#define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)
47888#define USB_ENDPTPRIME_PETB_MASK (0xFF0000U)
47889#define USB_ENDPTPRIME_PETB_SHIFT (16U)
47890#define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)
47891/*! @} */
47892
47893/*! @name ENDPTFLUSH - Endpoint Flush */
47894/*! @{ */
47895#define USB_ENDPTFLUSH_FERB_MASK (0xFFU)
47896#define USB_ENDPTFLUSH_FERB_SHIFT (0U)
47897#define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)
47898#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U)
47899#define USB_ENDPTFLUSH_FETB_SHIFT (16U)
47900#define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)
47901/*! @} */
47902
47903/*! @name ENDPTSTAT - Endpoint Status */
47904/*! @{ */
47905#define USB_ENDPTSTAT_ERBR_MASK (0xFFU)
47906#define USB_ENDPTSTAT_ERBR_SHIFT (0U)
47907#define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)
47908#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U)
47909#define USB_ENDPTSTAT_ETBR_SHIFT (16U)
47910#define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)
47911/*! @} */
47912
47913/*! @name ENDPTCOMPLETE - Endpoint Complete */
47914/*! @{ */
47915#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU)
47916#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U)
47917#define USB_ENDPTCOMPLETE_ERCE(x) \
47918 (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)
47919#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U)
47920#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U)
47921#define USB_ENDPTCOMPLETE_ETCE(x) \
47922 (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)
47923/*! @} */
47924
47925/*! @name ENDPTCTRL - Endpoint Control0..Endpoint Control 7 */
47926/*! @{ */
47927#define USB_ENDPTCTRL_RXS_MASK (0x1U)
47928#define USB_ENDPTCTRL_RXS_SHIFT (0U)
47929#define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)
47930#define USB_ENDPTCTRL_RXD_MASK (0x2U)
47931#define USB_ENDPTCTRL_RXD_SHIFT (1U)
47932#define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)
47933#define USB_ENDPTCTRL_RXT_MASK (0xCU)
47934#define USB_ENDPTCTRL_RXT_SHIFT (2U)
47935#define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)
47936#define USB_ENDPTCTRL_RXI_MASK (0x20U)
47937#define USB_ENDPTCTRL_RXI_SHIFT (5U)
47938#define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)
47939#define USB_ENDPTCTRL_RXR_MASK (0x40U)
47940#define USB_ENDPTCTRL_RXR_SHIFT (6U)
47941#define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)
47942#define USB_ENDPTCTRL_RXE_MASK (0x80U)
47943#define USB_ENDPTCTRL_RXE_SHIFT (7U)
47944#define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)
47945#define USB_ENDPTCTRL_TXS_MASK (0x10000U)
47946#define USB_ENDPTCTRL_TXS_SHIFT (16U)
47947#define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)
47948#define USB_ENDPTCTRL_TXD_MASK (0x20000U)
47949#define USB_ENDPTCTRL_TXD_SHIFT (17U)
47950#define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)
47951#define USB_ENDPTCTRL_TXT_MASK (0xC0000U)
47952#define USB_ENDPTCTRL_TXT_SHIFT (18U)
47953#define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)
47954#define USB_ENDPTCTRL_TXI_MASK (0x200000U)
47955#define USB_ENDPTCTRL_TXI_SHIFT (21U)
47956#define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)
47957#define USB_ENDPTCTRL_TXR_MASK (0x400000U)
47958#define USB_ENDPTCTRL_TXR_SHIFT (22U)
47959#define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)
47960#define USB_ENDPTCTRL_TXE_MASK (0x800000U)
47961#define USB_ENDPTCTRL_TXE_SHIFT (23U)
47962#define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)
47963/*! @} */
47964
47965/* The count of USB_ENDPTCTRL */
47966#define USB_ENDPTCTRL_COUNT (8U)
47967
47968/*!
47969 * @}
47970 */ /* end of group USB_Register_Masks */
47971
47972/* USB - Peripheral instance base addresses */
47973/** Peripheral USB base address */
47974#define USB_BASE (0x32E40000u)
47975/** Peripheral USB base pointer */
47976#define USB ((USB_Type *)USB_BASE)
47977/** Array initializer of USB peripheral base addresses */
47978#define USB_BASE_ADDRS \
47979 { \
47980 USB_BASE \
47981 }
47982/** Array initializer of USB peripheral base pointers */
47983#define USB_BASE_PTRS \
47984 { \
47985 USB \
47986 }
47987
47988/*!
47989 * @}
47990 */ /* end of group USB_Peripheral_Access_Layer */
47991
47992/* ----------------------------------------------------------------------------
47993 -- USBNC Peripheral Access Layer
47994 ---------------------------------------------------------------------------- */
47995
47996/*!
47997 * @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer
47998 * @{
47999 */
48000
48001/** USBNC - Register Layout Typedef */
48002typedef struct
48003{
48004 uint8_t RESERVED_0[512];
48005 __IO uint32_t OTG1_CTRL1; /**< , offset: 0x200 */
48006 __IO uint32_t OTG1_CTRL2; /**< , offset: 0x204 */
48007 uint8_t RESERVED_1[40];
48008 __IO uint32_t OTG1_PHY_CFG1; /**< USB OTG PHY Configuration Register 1, offset: 0x230 */
48009 __IO uint32_t OTG1_PHY_CFG2; /**< USB OTG PHY Configuration Register 2, offset: 0x234 */
48010 uint8_t RESERVED_2[4];
48011 __I uint32_t OTG1_PHY_STATUS; /**< USB OTG PHY Status Register, offset: 0x23C */
48012 uint8_t RESERVED_3[16];
48013 __IO uint32_t ADP_CFG1; /**< , offset: 0x250 */
48014 __IO uint32_t ADP_CFG2; /**< , offset: 0x254 */
48015 __I uint32_t ADP_STATUS; /**< , offset: 0x258 */
48016} USBNC_Type;
48017
48018/* ----------------------------------------------------------------------------
48019 -- USBNC Register Masks
48020 ---------------------------------------------------------------------------- */
48021
48022/*!
48023 * @addtogroup USBNC_Register_Masks USBNC Register Masks
48024 * @{
48025 */
48026
48027/*! @name OTG1_CTRL1 - */
48028/*! @{ */
48029#define USBNC_OTG1_CTRL1_OVER_CUR_DIS_MASK (0x80U)
48030#define USBNC_OTG1_CTRL1_OVER_CUR_DIS_SHIFT (7U)
48031/*! OVER_CUR_DIS
48032 * 0b1..Disables overcurrent detection
48033 * 0b0..Enables overcurrent detection
48034 */
48035#define USBNC_OTG1_CTRL1_OVER_CUR_DIS(x) \
48036 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_OTG1_CTRL1_OVER_CUR_DIS_MASK)
48037#define USBNC_OTG1_CTRL1_OVER_CUR_POL_MASK (0x100U)
48038#define USBNC_OTG1_CTRL1_OVER_CUR_POL_SHIFT (8U)
48039/*! OVER_CUR_POL
48040 * 0b1..Low active (low on this signal represents an overcurrent condition)
48041 * 0b0..High active (high on this signal represents an overcurrent condition)
48042 */
48043#define USBNC_OTG1_CTRL1_OVER_CUR_POL(x) \
48044 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_OTG1_CTRL1_OVER_CUR_POL_MASK)
48045#define USBNC_OTG1_CTRL1_PWR_POL_MASK (0x200U)
48046#define USBNC_OTG1_CTRL1_PWR_POL_SHIFT (9U)
48047/*! PWR_POL
48048 * 0b1..PMIC Power Pin is High active.
48049 * 0b0..PMIC Power Pin is Low active.
48050 */
48051#define USBNC_OTG1_CTRL1_PWR_POL(x) \
48052 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL1_PWR_POL_SHIFT)) & USBNC_OTG1_CTRL1_PWR_POL_MASK)
48053#define USBNC_OTG1_CTRL1_WIE_MASK (0x400U)
48054#define USBNC_OTG1_CTRL1_WIE_SHIFT (10U)
48055/*! WIE
48056 * 0b1..Interrupt Enabled
48057 * 0b0..Interrupt Disabled
48058 */
48059#define USBNC_OTG1_CTRL1_WIE(x) \
48060 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL1_WIE_SHIFT)) & USBNC_OTG1_CTRL1_WIE_MASK)
48061#define USBNC_OTG1_CTRL1_WKUP_SW_EN_MASK (0x4000U)
48062#define USBNC_OTG1_CTRL1_WKUP_SW_EN_SHIFT (14U)
48063/*! WKUP_SW_EN
48064 * 0b1..Enable
48065 * 0b0..Disable
48066 */
48067#define USBNC_OTG1_CTRL1_WKUP_SW_EN(x) \
48068 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_OTG1_CTRL1_WKUP_SW_EN_MASK)
48069#define USBNC_OTG1_CTRL1_WKUP_SW_MASK (0x8000U)
48070#define USBNC_OTG1_CTRL1_WKUP_SW_SHIFT (15U)
48071/*! WKUP_SW
48072 * 0b1..Force wake-up
48073 * 0b0..Inactive
48074 */
48075#define USBNC_OTG1_CTRL1_WKUP_SW(x) \
48076 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL1_WKUP_SW_SHIFT)) & USBNC_OTG1_CTRL1_WKUP_SW_MASK)
48077#define USBNC_OTG1_CTRL1_WKUP_ID_EN_MASK (0x10000U)
48078#define USBNC_OTG1_CTRL1_WKUP_ID_EN_SHIFT (16U)
48079/*! WKUP_ID_EN
48080 * 0b1..Enable
48081 * 0b0..Disable
48082 */
48083#define USBNC_OTG1_CTRL1_WKUP_ID_EN(x) \
48084 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_OTG1_CTRL1_WKUP_ID_EN_MASK)
48085#define USBNC_OTG1_CTRL1_WKUP_VBUS_EN_MASK (0x20000U)
48086#define USBNC_OTG1_CTRL1_WKUP_VBUS_EN_SHIFT (17U)
48087/*! WKUP_VBUS_EN
48088 * 0b1..Enable
48089 * 0b0..Disable
48090 */
48091#define USBNC_OTG1_CTRL1_WKUP_VBUS_EN(x) \
48092 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_OTG1_CTRL1_WKUP_VBUS_EN_MASK)
48093#define USBNC_OTG1_CTRL1_WKUP_DPDM_EN_MASK (0x20000000U)
48094#define USBNC_OTG1_CTRL1_WKUP_DPDM_EN_SHIFT (29U)
48095/*! WKUP_DPDM_EN
48096 * 0b1..(Default) DPDM changes wake-up to be enabled, it is for device only.
48097 * 0b0..DPDM changes wake-up to be disabled only when VBUS is 0.
48098 */
48099#define USBNC_OTG1_CTRL1_WKUP_DPDM_EN(x) \
48100 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_OTG1_CTRL1_WKUP_DPDM_EN_MASK)
48101#define USBNC_OTG1_CTRL1_WIR_MASK (0x80000000U)
48102#define USBNC_OTG1_CTRL1_WIR_SHIFT (31U)
48103/*! WIR
48104 * 0b1..Wake-up Interrupt Request received
48105 * 0b0..No wake-up interrupt request received
48106 */
48107#define USBNC_OTG1_CTRL1_WIR(x) \
48108 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL1_WIR_SHIFT)) & USBNC_OTG1_CTRL1_WIR_MASK)
48109/*! @} */
48110
48111/*! @name OTG1_CTRL2 - */
48112/*! @{ */
48113#define USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL_MASK (0x3U)
48114#define USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL_SHIFT (0U)
48115#define USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL(x) \
48116 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL_MASK)
48117#define USBNC_OTG1_CTRL2_AUTURESUME_EN_MASK (0x4U)
48118#define USBNC_OTG1_CTRL2_AUTURESUME_EN_SHIFT (2U)
48119/*! AUTURESUME_EN - Auto Resume Enable
48120 * 0b0..Default
48121 */
48122#define USBNC_OTG1_CTRL2_AUTURESUME_EN(x) \
48123 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_OTG1_CTRL2_AUTURESUME_EN_MASK)
48124#define USBNC_OTG1_CTRL2_LOWSPEED_EN_MASK (0x8U)
48125#define USBNC_OTG1_CTRL2_LOWSPEED_EN_SHIFT (3U)
48126/*! LOWSPEED_EN
48127 * 0b0..Default
48128 */
48129#define USBNC_OTG1_CTRL2_LOWSPEED_EN(x) \
48130 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_OTG1_CTRL2_LOWSPEED_EN_MASK)
48131#define USBNC_OTG1_CTRL2_TERMSEL_OVERRIDE_MASK (0x10U)
48132#define USBNC_OTG1_CTRL2_TERMSEL_OVERRIDE_SHIFT (4U)
48133#define USBNC_OTG1_CTRL2_TERMSEL_OVERRIDE(x) \
48134 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_TERMSEL_OVERRIDE_SHIFT)) & USBNC_OTG1_CTRL2_TERMSEL_OVERRIDE_MASK)
48135#define USBNC_OTG1_CTRL2_TERMSEL_OVERRIDEEN_MASK (0x20U)
48136#define USBNC_OTG1_CTRL2_TERMSEL_OVERRIDEEN_SHIFT (5U)
48137/*! TERMSEL_OVERRIDEEN
48138 * 0b0..The state of the UTMI TermSelect signal to the USB PHY is set by the USB controller.
48139 * 0b1..The state of the UTMI TermSelect signal to the USB PHY is set by the value in the
48140 * USBNC_x_CTRL2[TERMSEL_OVERRIDE] bit field.
48141 */
48142#define USBNC_OTG1_CTRL2_TERMSEL_OVERRIDEEN(x) \
48143 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_TERMSEL_OVERRIDEEN_SHIFT)) & \
48144 USBNC_OTG1_CTRL2_TERMSEL_OVERRIDEEN_MASK)
48145#define USBNC_OTG1_CTRL2_OPMODE_OVERRIDE_MASK (0xC0U)
48146#define USBNC_OTG1_CTRL2_OPMODE_OVERRIDE_SHIFT (6U)
48147#define USBNC_OTG1_CTRL2_OPMODE_OVERRIDE(x) \
48148 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_OPMODE_OVERRIDE_SHIFT)) & USBNC_OTG1_CTRL2_OPMODE_OVERRIDE_MASK)
48149#define USBNC_OTG1_CTRL2_OPMODE_OVERRIDEEN_MASK (0x100U)
48150#define USBNC_OTG1_CTRL2_OPMODE_OVERRIDEEN_SHIFT (8U)
48151/*! OPMODE_OVERRIDEEN
48152 * 0b0..The state of the UTMI OpMode signals to the USB PHY is set by the USB controller.
48153 * 0b1..The state of the UTMI OpMode signals to the USB PHY is set by the values in the USBNC_x_CTRL2[OPMODE_OVERRIDE]
48154 * bit field.
48155 */
48156#define USBNC_OTG1_CTRL2_OPMODE_OVERRIDEEN(x) \
48157 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_OPMODE_OVERRIDEEN_SHIFT)) & \
48158 USBNC_OTG1_CTRL2_OPMODE_OVERRIDEEN_MASK)
48159#define USBNC_OTG1_CTRL2_XCVRSEL_OVERRIDE_MASK (0x600U)
48160#define USBNC_OTG1_CTRL2_XCVRSEL_OVERRIDE_SHIFT (9U)
48161#define USBNC_OTG1_CTRL2_XCVRSEL_OVERRIDE(x) \
48162 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_XCVRSEL_OVERRIDE_SHIFT)) & USBNC_OTG1_CTRL2_XCVRSEL_OVERRIDE_MASK)
48163#define USBNC_OTG1_CTRL2_XCVRSEL_OVERRIDEEN_MASK (0x800U)
48164#define USBNC_OTG1_CTRL2_XCVRSEL_OVERRIDEEN_SHIFT (11U)
48165/*! XCVRSEL_OVERRIDEEN
48166 * 0b0..The state of the UTMI XcvrSelect signals to the USB PHY is set by the USB controller.
48167 * 0b1..The state of the UTMI XcvrSelect signals to the USB PHY is set by the values in the
48168 * USBNC_x_CTRL2[XCVRSEL_OVERRIDE] bit field.
48169 */
48170#define USBNC_OTG1_CTRL2_XCVRSEL_OVERRIDEEN(x) \
48171 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_XCVRSEL_OVERRIDEEN_SHIFT)) & \
48172 USBNC_OTG1_CTRL2_XCVRSEL_OVERRIDEEN_MASK)
48173#define USBNC_OTG1_CTRL2_DPPULLDOWN_OVERRIDE_MASK (0x1000U)
48174#define USBNC_OTG1_CTRL2_DPPULLDOWN_OVERRIDE_SHIFT (12U)
48175/*! DPPULLDOWN_OVERRIDE
48176 * 0b0..DP pulldown resistor disabled
48177 * 0b1..DP pulldown resistor enabled
48178 */
48179#define USBNC_OTG1_CTRL2_DPPULLDOWN_OVERRIDE(x) \
48180 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_DPPULLDOWN_OVERRIDE_SHIFT)) & \
48181 USBNC_OTG1_CTRL2_DPPULLDOWN_OVERRIDE_MASK)
48182#define USBNC_OTG1_CTRL2_DPPULLDOWN_OVERRIDEEN_MASK (0x2000U)
48183#define USBNC_OTG1_CTRL2_DPPULLDOWN_OVERRIDEEN_SHIFT (13U)
48184/*! DPPULLDOWN_OVERRIDEEN
48185 * 0b0..USB controller enables/disables the DP pulldown resistor in the USB PHY.
48186 * 0b1..Use the value set by the USBNC_n_CTRL2[DPPULLDOWN_OVERRIDE] bit field to enable/disable the DP pulldown
48187 * resistor in the USB PHY.
48188 */
48189#define USBNC_OTG1_CTRL2_DPPULLDOWN_OVERRIDEEN(x) \
48190 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_DPPULLDOWN_OVERRIDEEN_SHIFT)) & \
48191 USBNC_OTG1_CTRL2_DPPULLDOWN_OVERRIDEEN_MASK)
48192#define USBNC_OTG1_CTRL2_DMPULLDOWN_OVERRIDE_MASK (0x4000U)
48193#define USBNC_OTG1_CTRL2_DMPULLDOWN_OVERRIDE_SHIFT (14U)
48194/*! DMPULLDOWN_OVERRIDE
48195 * 0b0..DM pulldown resistor disabled
48196 * 0b1..DM pulldown resistor enabled
48197 */
48198#define USBNC_OTG1_CTRL2_DMPULLDOWN_OVERRIDE(x) \
48199 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_DMPULLDOWN_OVERRIDE_SHIFT)) & \
48200 USBNC_OTG1_CTRL2_DMPULLDOWN_OVERRIDE_MASK)
48201#define USBNC_OTG1_CTRL2_DMPULLDOWN_OVERRIDEEN_MASK (0x8000U)
48202#define USBNC_OTG1_CTRL2_DMPULLDOWN_OVERRIDEEN_SHIFT (15U)
48203/*! DMPULLDOWN_OVERRIDEEN
48204 * 0b0..USB controller enables/disables the DM pulldown resistor in the USB PHY.
48205 * 0b1..Use the value set by the USBNC_n_CTRL2[DMPULLDOWN_OVERRIDE] bit field to enable/disable the DM pulldown
48206 * resistor in the USB PHY.
48207 */
48208#define USBNC_OTG1_CTRL2_DMPULLDOWN_OVERRIDEEN(x) \
48209 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_DMPULLDOWN_OVERRIDEEN_SHIFT)) & \
48210 USBNC_OTG1_CTRL2_DMPULLDOWN_OVERRIDEEN_MASK)
48211#define USBNC_OTG1_CTRL2_DIG_ID_SEL_MASK (0x100000U)
48212#define USBNC_OTG1_CTRL2_DIG_ID_SEL_SHIFT (20U)
48213/*! DIG_ID_SEL
48214 * 0b0..Use the USB_OTG*_ID pin for the USB OTG ID pin detection function(default)
48215 * 0b1..Use the pin configured by the IOMUXC_USB_OTG*_ID_SELECT_INPUT register for the USB OTG ID pin detection
48216 * function
48217 */
48218#define USBNC_OTG1_CTRL2_DIG_ID_SEL(x) \
48219 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_DIG_ID_SEL_SHIFT)) & USBNC_OTG1_CTRL2_DIG_ID_SEL_MASK)
48220#define USBNC_OTG1_CTRL2_UTMI_CLK_VLD_MASK (0x80000000U)
48221#define USBNC_OTG1_CTRL2_UTMI_CLK_VLD_SHIFT (31U)
48222/*! UTMI_CLK_VLD
48223 * 0b0..UTMI clock to USB PHY is not toggling (Default)
48224 * 0b1..UTMI clock to USB PHY has toggled several times
48225 */
48226#define USBNC_OTG1_CTRL2_UTMI_CLK_VLD(x) \
48227 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_OTG1_CTRL2_UTMI_CLK_VLD_MASK)
48228/*! @} */
48229
48230/*! @name OTG1_PHY_CFG1 - USB OTG PHY Configuration Register 1 */
48231/*! @{ */
48232#define USBNC_OTG1_PHY_CFG1_COMMONONN_MASK (0x1U)
48233#define USBNC_OTG1_PHY_CFG1_COMMONONN_SHIFT (0U)
48234/*! COMMONONN - Common Block Power-Down Control
48235 * 0b0..In Suspend or Sleep modes, the Bias and PLL blocks remain powered
48236 * 0b1..In Suspend or Sleep modes, the Bias and PLL blocks are powered down
48237 * 0b0..
48238 */
48239#define USBNC_OTG1_PHY_CFG1_COMMONONN(x) \
48240 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_COMMONONN_SHIFT)) & USBNC_OTG1_PHY_CFG1_COMMONONN_MASK)
48241#define USBNC_OTG1_PHY_CFG1_FSEL_MASK (0xEU)
48242#define USBNC_OTG1_PHY_CFG1_FSEL_SHIFT (1U)
48243/*! FSEL - Reference Clock Frequency Select
48244 * 0b000..9.6 MHz
48245 * 0b001..10 MHz
48246 * 0b010..12 MHz
48247 * 0b011..19.2 MHz
48248 * 0b100..20 MHz
48249 * 0b101..24 MHz (only valid setting for this SOC)
48250 * 0b110..Reserved
48251 * 0b111..50 MHz
48252 */
48253#define USBNC_OTG1_PHY_CFG1_FSEL(x) \
48254 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_FSEL_SHIFT)) & USBNC_OTG1_PHY_CFG1_FSEL_MASK)
48255#define USBNC_OTG1_PHY_CFG1_COMPDISTUNE0_MASK (0x70U)
48256#define USBNC_OTG1_PHY_CFG1_COMPDISTUNE0_SHIFT (4U)
48257/*! COMPDISTUNE0 - Disconnect Threshold Adjustment
48258 * 0b000..-6%
48259 * 0b001..-4.5%
48260 * 0b010..-3%
48261 * 0b011..-1.5%
48262 * 0b100..Design default
48263 * 0b101..+1.5%
48264 * 0b110..+3%
48265 * 0b111..+4.5%
48266 */
48267#define USBNC_OTG1_PHY_CFG1_COMPDISTUNE0(x) \
48268 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_COMPDISTUNE0_SHIFT)) & USBNC_OTG1_PHY_CFG1_COMPDISTUNE0_MASK)
48269#define USBNC_OTG1_PHY_CFG1_SQRXTUNE0_MASK (0x380U)
48270#define USBNC_OTG1_PHY_CFG1_SQRXTUNE0_SHIFT (7U)
48271/*! SQRXTUNE0 - Squelch Threshold Adjustment
48272 * 0b000..+15%
48273 * 0b001..+10%
48274 * 0b010..+5%
48275 * 0b011..Design default
48276 * 0b100..-5%
48277 * 0b101..-10%
48278 * 0b110..-15%
48279 * 0b111..-20%
48280 */
48281#define USBNC_OTG1_PHY_CFG1_SQRXTUNE0(x) \
48282 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_SQRXTUNE0_SHIFT)) & USBNC_OTG1_PHY_CFG1_SQRXTUNE0_MASK)
48283#define USBNC_OTG1_PHY_CFG1_OTGTUNE0_MASK (0x1C00U)
48284#define USBNC_OTG1_PHY_CFG1_OTGTUNE0_SHIFT (10U)
48285/*! OTGTUNE0 - VBUS Valid Threshold Adjustment
48286 * 0b000..-6%
48287 * 0b001..-4.5%
48288 * 0b010..-3%
48289 * 0b011..-1.5%
48290 * 0b100..Design default
48291 * 0b101..+1.5%
48292 * 0b110..+3%
48293 * 0b111..+4.5%
48294 */
48295#define USBNC_OTG1_PHY_CFG1_OTGTUNE0(x) \
48296 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_OTGTUNE0_SHIFT)) & USBNC_OTG1_PHY_CFG1_OTGTUNE0_MASK)
48297#define USBNC_OTG1_PHY_CFG1_TXHSXVTUNE0_MASK (0x6000U)
48298#define USBNC_OTG1_PHY_CFG1_TXHSXVTUNE0_SHIFT (13U)
48299/*! TXHSXVTUNE0 - Transmitter High-Speed Crossover Adjustment
48300 * 0b00..Reserved
48301 * 0b01..-15mV
48302 * 0b10..+15mV
48303 * 0b11..Design default
48304 */
48305#define USBNC_OTG1_PHY_CFG1_TXHSXVTUNE0(x) \
48306 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_TXHSXVTUNE0_SHIFT)) & USBNC_OTG1_PHY_CFG1_TXHSXVTUNE0_MASK)
48307#define USBNC_OTG1_PHY_CFG1_TXFSLSTUNE0_MASK (0xF0000U)
48308#define USBNC_OTG1_PHY_CFG1_TXFSLSTUNE0_SHIFT (16U)
48309/*! TXFSLSTUNE0 - FS/LS Source Impedance Adjustment
48310 * 0b0000..+5%
48311 * 0b0001..+2.5%
48312 * 0b0011..Design default
48313 * 0b0111..-2.5%
48314 * 0b1111..-5%
48315 */
48316#define USBNC_OTG1_PHY_CFG1_TXFSLSTUNE0(x) \
48317 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_TXFSLSTUNE0_SHIFT)) & USBNC_OTG1_PHY_CFG1_TXFSLSTUNE0_MASK)
48318#define USBNC_OTG1_PHY_CFG1_TXVREFTUNE0_MASK (0xF00000U)
48319#define USBNC_OTG1_PHY_CFG1_TXVREFTUNE0_SHIFT (20U)
48320/*! TXVREFTUNE0 - HS DC Voltage Level Adjustment
48321 * 0b0000..-6%
48322 * 0b0001..-4%
48323 * 0b0010..-2%
48324 * 0b0011..Design default
48325 * 0b0100..+2%
48326 * 0b0101..+4%
48327 * 0b0110..+6%
48328 * 0b0111..+8%
48329 * 0b1000..+10%
48330 * 0b1001..+12%
48331 * 0b1010..+14%
48332 * 0b1011..+16%
48333 * 0b1100..+18%
48334 * 0b1101..+20%
48335 * 0b1110..+22%
48336 * 0b1111..+24%
48337 */
48338#define USBNC_OTG1_PHY_CFG1_TXVREFTUNE0(x) \
48339 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_TXVREFTUNE0_SHIFT)) & USBNC_OTG1_PHY_CFG1_TXVREFTUNE0_MASK)
48340#define USBNC_OTG1_PHY_CFG1_TXRISETUNE0_MASK (0x3000000U)
48341#define USBNC_OTG1_PHY_CFG1_TXRISETUNE0_SHIFT (24U)
48342/*! TXRISETUNE0 - HS Transmitter Rise/Fall Time Adjustment
48343 * 0b00..-10%
48344 * 0b01..Design default
48345 * 0b10..+15%
48346 * 0b11..+20%
48347 */
48348#define USBNC_OTG1_PHY_CFG1_TXRISETUNE0(x) \
48349 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_TXRISETUNE0_SHIFT)) & USBNC_OTG1_PHY_CFG1_TXRISETUNE0_MASK)
48350#define USBNC_OTG1_PHY_CFG1_TXRESTUNE0_MASK (0xC000000U)
48351#define USBNC_OTG1_PHY_CFG1_TXRESTUNE0_SHIFT (26U)
48352/*! TXRESTUNE0 - USB Source Impedance Adjustment
48353 * 0b00..Source impedance is increased by approximately 1.5 ohm
48354 * 0b01..Design default
48355 * 0b10..Source impedance is decreased by approximately 2 ohm
48356 * 0b11..Source impedance is decreased by approximately 4 ohm
48357 */
48358#define USBNC_OTG1_PHY_CFG1_TXRESTUNE0(x) \
48359 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_TXRESTUNE0_SHIFT)) & USBNC_OTG1_PHY_CFG1_TXRESTUNE0_MASK)
48360#define USBNC_OTG1_PHY_CFG1_TXPREEMPAMPTUNE0_MASK (0x30000000U)
48361#define USBNC_OTG1_PHY_CFG1_TXPREEMPAMPTUNE0_SHIFT (28U)
48362/*! TXPREEMPAMPTUNE0 - HS Treansmitter Pre-Emphasis Current Control
48363 * 0b00..HS Transmitter pre-emphasis is disabled
48364 * 0b01..HS Transmitter pre-emphasis circuit sources 1X pre-emphasis current (design default)
48365 * 0b10..HS Transmitter pre-emphasis circuit sources 2X pre-emphasis current
48366 * 0b11..HS Transmitter pre-emphasis circuit sources 3X pre-emphasis current
48367 */
48368#define USBNC_OTG1_PHY_CFG1_TXPREEMPAMPTUNE0(x) \
48369 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_TXPREEMPAMPTUNE0_SHIFT)) & \
48370 USBNC_OTG1_PHY_CFG1_TXPREEMPAMPTUNE0_MASK)
48371#define USBNC_OTG1_PHY_CFG1_TXPREEMPPULSETUNE0_MASK (0x40000000U)
48372#define USBNC_OTG1_PHY_CFG1_TXPREEMPPULSETUNE0_SHIFT (30U)
48373/*! TXPREEMPPULSETUNE0 - HS Transmitter Pre-Emphasis Duration Control
48374 * 0b0..2X, long pre-emphasis current duration (design default)
48375 * 0b1..1X, short pre-emphasis current duration
48376 */
48377#define USBNC_OTG1_PHY_CFG1_TXPREEMPPULSETUNE0(x) \
48378 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_TXPREEMPPULSETUNE0_SHIFT)) & \
48379 USBNC_OTG1_PHY_CFG1_TXPREEMPPULSETUNE0_MASK)
48380#define USBNC_OTG1_PHY_CFG1_CHRGDET_Megamix_MASK (0x80000000U)
48381#define USBNC_OTG1_PHY_CFG1_CHRGDET_Megamix_SHIFT (31U)
48382/*! CHRGDET_Megamix - USB_OTG1_CHD_B output control
48383 * 0b0..The external state of USB_OTG1_CHD_B is only controlled by the state of the CHRGDET signal
48384 * 0b1..The external state of USB_OTG1_CHD_B is forced low
48385 */
48386#define USBNC_OTG1_PHY_CFG1_CHRGDET_Megamix(x) \
48387 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG1_CHRGDET_Megamix_SHIFT)) & \
48388 USBNC_OTG1_PHY_CFG1_CHRGDET_Megamix_MASK)
48389/*! @} */
48390
48391/*! @name OTG1_PHY_CFG2 - USB OTG PHY Configuration Register 2 */
48392/*! @{ */
48393#define USBNC_OTG1_PHY_CFG2_CHRGSEL_MASK (0x1U)
48394#define USBNC_OTG1_PHY_CFG2_CHRGSEL_SHIFT (0U)
48395/*! CHRGSEL - Battery Charging Source Select
48396 * 0b0..VDP_SRC is connected to USB_OTG*_DP and IDM_SINK is connected to USB_OTG*_DN. Used for Primary Detection.
48397 * 0b1..VDM_SRC is connected to USB_OTG*_DN and IDP_SINK is connected to USB_OTG*_DP. Used for Secondary Detection.
48398 */
48399#define USBNC_OTG1_PHY_CFG2_CHRGSEL(x) \
48400 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_CHRGSEL_SHIFT)) & USBNC_OTG1_PHY_CFG2_CHRGSEL_MASK)
48401#define USBNC_OTG1_PHY_CFG2_VDATDETENB0_MASK (0x2U)
48402#define USBNC_OTG1_PHY_CFG2_VDATDETENB0_SHIFT (1U)
48403/*! VDATDETENB0 - Battery Charging Detection Comparator Enable
48404 * 0b0..Battery Charging detection comparator connected to USB_OTG*_D* pin is disabled
48405 * 0b1..Battery Charging detection comparator connected to USB_OTG*_D* pin is enabled
48406 */
48407#define USBNC_OTG1_PHY_CFG2_VDATDETENB0(x) \
48408 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_VDATDETENB0_SHIFT)) & USBNC_OTG1_PHY_CFG2_VDATDETENB0_MASK)
48409#define USBNC_OTG1_PHY_CFG2_VDATSRCENB0_MASK (0x4U)
48410#define USBNC_OTG1_PHY_CFG2_VDATSRCENB0_SHIFT (2U)
48411/*! VDATSRCENB0 - Battery Charging Source Select
48412 * 0b0..VD*_SRC and ID*_SINK are disabled
48413 * 0b1..VD*_SRC and ID*_SINK are enabled
48414 */
48415#define USBNC_OTG1_PHY_CFG2_VDATSRCENB0(x) \
48416 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_VDATSRCENB0_SHIFT)) & USBNC_OTG1_PHY_CFG2_VDATSRCENB0_MASK)
48417#define USBNC_OTG1_PHY_CFG2_DCDENB_MASK (0x8U)
48418#define USBNC_OTG1_PHY_CFG2_DCDENB_SHIFT (3U)
48419/*! DCDENB - Data Contact Detection Enable
48420 * 0b0..IDP_SRC current and RDM_DWN pull-down resistance are disabled
48421 * 0b1..IDP_SRC current and RDM_DWN pull-down resistance are enabled
48422 */
48423#define USBNC_OTG1_PHY_CFG2_DCDENB(x) \
48424 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_DCDENB_SHIFT)) & USBNC_OTG1_PHY_CFG2_DCDENB_MASK)
48425#define USBNC_OTG1_PHY_CFG2_ACAENB0_MASK (0x10U)
48426#define USBNC_OTG1_PHY_CFG2_ACAENB0_SHIFT (4U)
48427/*! ACAENB0 - ACA USB_OTG*_ID Pin Resistance Detection Enable
48428 * 0b0..Disables detection of resistance on the USB_OTG*_ID pin
48429 * 0b1..Enables detection of resistance on the USB_OTG*_ID pin
48430 */
48431#define USBNC_OTG1_PHY_CFG2_ACAENB0(x) \
48432 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_ACAENB0_SHIFT)) & USBNC_OTG1_PHY_CFG2_ACAENB0_MASK)
48433#define USBNC_OTG1_PHY_CFG2_SLEEPM0_MASK (0x20U)
48434#define USBNC_OTG1_PHY_CFG2_SLEEPM0_SHIFT (5U)
48435/*! SLEEPM0 - Sleep Mode Assertion
48436 * 0b0..Sleep mode
48437 * 0b1..Normal operating mode
48438 */
48439#define USBNC_OTG1_PHY_CFG2_SLEEPM0(x) \
48440 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_SLEEPM0_SHIFT)) & USBNC_OTG1_PHY_CFG2_SLEEPM0_MASK)
48441#define USBNC_OTG1_PHY_CFG2_LOOPBACKENB0_MASK (0x40U)
48442#define USBNC_OTG1_PHY_CFG2_LOOPBACKENB0_SHIFT (6U)
48443/*! LOOPBACKENB0 - Loopback Test Enable
48444 * 0b0..During data transmission, the receive logic is disabled
48445 * 0b1..During data transmission, the receive logic is enabled
48446 */
48447#define USBNC_OTG1_PHY_CFG2_LOOPBACKENB0(x) \
48448 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_LOOPBACKENB0_SHIFT)) & USBNC_OTG1_PHY_CFG2_LOOPBACKENB0_MASK)
48449#define USBNC_OTG1_PHY_CFG2_TXBITSTUFFEN0_MASK (0x100U)
48450#define USBNC_OTG1_PHY_CFG2_TXBITSTUFFEN0_SHIFT (8U)
48451/*! TXBITSTUFFEN0 - Low-Byte Transmit Bit-Stuffing Enable
48452 * 0b0..Bit stuffing is disabled
48453 * 0b1..Bit stuffing is enabled
48454 */
48455#define USBNC_OTG1_PHY_CFG2_TXBITSTUFFEN0(x) \
48456 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_TXBITSTUFFEN0_SHIFT)) & USBNC_OTG1_PHY_CFG2_TXBITSTUFFEN0_MASK)
48457#define USBNC_OTG1_PHY_CFG2_TXBITSTUFFENH0_MASK (0x200U)
48458#define USBNC_OTG1_PHY_CFG2_TXBITSTUFFENH0_SHIFT (9U)
48459/*! TXBITSTUFFENH0 - High-Byte Transmit Bit-Stuffing Enable
48460 * 0b0..Bit stuffing is disabled
48461 * 0b1..Bit stuffing is enabled
48462 */
48463#define USBNC_OTG1_PHY_CFG2_TXBITSTUFFENH0(x) \
48464 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_TXBITSTUFFENH0_SHIFT)) & \
48465 USBNC_OTG1_PHY_CFG2_TXBITSTUFFENH0_MASK)
48466#define USBNC_OTG1_PHY_CFG2_OTGDISABLE0_MASK (0x400U)
48467#define USBNC_OTG1_PHY_CFG2_OTGDISABLE0_SHIFT (10U)
48468/*! OTGDISABLE0 - OTG Block Disable
48469 * 0b0..The OTG block is powered up
48470 * 0b1..The OTG block is powered down
48471 */
48472#define USBNC_OTG1_PHY_CFG2_OTGDISABLE0(x) \
48473 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_OTGDISABLE0_SHIFT)) & USBNC_OTG1_PHY_CFG2_OTGDISABLE0_MASK)
48474#define USBNC_OTG1_PHY_CFG2_ADPCHRG0_MASK (0x800U)
48475#define USBNC_OTG1_PHY_CFG2_ADPCHRG0_SHIFT (11U)
48476/*! ADPCHRG0 - VBUS Input ADP Charge Enable
48477 * 0b0..Disables charging USB_OTG*_VBUS during ADP
48478 * 0b1..Disables charging USB_OTG*_VBUS during ADP
48479 */
48480#define USBNC_OTG1_PHY_CFG2_ADPCHRG0(x) \
48481 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_ADPCHRG0_SHIFT)) & USBNC_OTG1_PHY_CFG2_ADPCHRG0_MASK)
48482#define USBNC_OTG1_PHY_CFG2_ADPDISCHRG0_MASK (0x1000U)
48483#define USBNC_OTG1_PHY_CFG2_ADPDISCHRG0_SHIFT (12U)
48484/*! ADPDISCHRG0 - VBUS Input ADP Discharge Enable
48485 * 0b0..Disables discharging USB_OTG*_VBUS during ADP
48486 * 0b1..Enables discharging USB_OTG*_VBUS during ADP
48487 */
48488#define USBNC_OTG1_PHY_CFG2_ADPDISCHRG0(x) \
48489 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_ADPDISCHRG0_SHIFT)) & USBNC_OTG1_PHY_CFG2_ADPDISCHRG0_MASK)
48490#define USBNC_OTG1_PHY_CFG2_ADPPRBENB0_MASK (0x2000U)
48491#define USBNC_OTG1_PHY_CFG2_ADPPRBENB0_SHIFT (13U)
48492/*! ADPPRBENB0 - ADP Probe Enable
48493 * 0b0..ADP Probe comparator is disabled
48494 * 0b1..ADP Probe comparator is enabled
48495 */
48496#define USBNC_OTG1_PHY_CFG2_ADPPRBENB0(x) \
48497 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_ADPPRBENB0_SHIFT)) & USBNC_OTG1_PHY_CFG2_ADPPRBENB0_MASK)
48498#define USBNC_OTG1_PHY_CFG2_VBUSVLDEXTSEL0_MASK (0x4000U)
48499#define USBNC_OTG1_PHY_CFG2_VBUSVLDEXTSEL0_SHIFT (14U)
48500/*! VBUSVLDEXTSEL0 - External VBUS Valid Select
48501 * 0b0..The USB OTG PHY internal Session Valid comparator is used to enable the pull-up resistor on the USB_OTG*_DP pin
48502 * 0b1..The VBUSVLDEXT signal is used to enable the pull-up resistor on the USB_OTG*_DP pin
48503 */
48504#define USBNC_OTG1_PHY_CFG2_VBUSVLDEXTSEL0(x) \
48505 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_VBUSVLDEXTSEL0_SHIFT)) & \
48506 USBNC_OTG1_PHY_CFG2_VBUSVLDEXTSEL0_MASK)
48507#define USBNC_OTG1_PHY_CFG2_VBUSVLDEXT_MASK (0x8000U)
48508#define USBNC_OTG1_PHY_CFG2_VBUSVLDEXT_SHIFT (15U)
48509/*! VBUSVLDEXT - External VBUS Valid Indicator
48510 * 0b0..The VBUS signal sensed outside the USB OTG PHY is not valid, and the pull-up resistor on USB_OTG*_DP is
48511 * disabled 0b1..The VBUS signal sensed outside the USB OTG PHY is valid, and the pull-up resistor on USB_OTG*_DP is
48512 * enabled
48513 */
48514#define USBNC_OTG1_PHY_CFG2_VBUSVLDEXT(x) \
48515 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_VBUSVLDEXT_SHIFT)) & USBNC_OTG1_PHY_CFG2_VBUSVLDEXT_MASK)
48516#define USBNC_OTG1_PHY_CFG2_DRVVBUS0_MASK (0x10000U)
48517#define USBNC_OTG1_PHY_CFG2_DRVVBUS0_SHIFT (16U)
48518/*! DRVVBUS0 - VBUS Valid Comparator Enable
48519 * 0b0..The VBUS Valid comparator is disabled
48520 * 0b1..The VBUS Valid comparator is enabled
48521 */
48522#define USBNC_OTG1_PHY_CFG2_DRVVBUS0(x) \
48523 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_CFG2_DRVVBUS0_SHIFT)) & USBNC_OTG1_PHY_CFG2_DRVVBUS0_MASK)
48524/*! @} */
48525
48526/*! @name OTG1_PHY_STATUS - USB OTG PHY Status Register */
48527/*! @{ */
48528#define USBNC_OTG1_PHY_STATUS_LINE_STATE_MASK (0x3U)
48529#define USBNC_OTG1_PHY_STATUS_LINE_STATE_SHIFT (0U)
48530/*! LINE_STATE - Line State Indicator outputs from USB OTG PHY
48531 * 0b00..SE0 (DP low, DN low)
48532 * 0b01..J state for high-speed and full-speed USB traffic; K state for low-speed USB traffic (DP high, DN low)
48533 * 0b10..K state for high-speed and full-speed USB traffic; J state for low-speed USB traffic (DP low, DN high)
48534 * 0b11..SE1 (DP high, DN high)
48535 */
48536#define USBNC_OTG1_PHY_STATUS_LINE_STATE(x) \
48537 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_LINE_STATE_SHIFT)) & USBNC_OTG1_PHY_STATUS_LINE_STATE_MASK)
48538#define USBNC_OTG1_PHY_STATUS_SESS_VLD_MASK (0x4U)
48539#define USBNC_OTG1_PHY_STATUS_SESS_VLD_SHIFT (2U)
48540/*! SESS_VLD - OTG Device Session Valid Indicator from USB OTG PHY
48541 * 0b0..The voltage on USB_OTG*_VBUS is below the OTG Device Session Valid threshold
48542 * 0b1..The voltage on USB_OTG*_VBUS is above the OTG Device Session Valid threshold
48543 */
48544#define USBNC_OTG1_PHY_STATUS_SESS_VLD(x) \
48545 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_SESS_VLD_SHIFT)) & USBNC_OTG1_PHY_STATUS_SESS_VLD_MASK)
48546#define USBNC_OTG1_PHY_STATUS_VBUS_VLD_MASK (0x8U)
48547#define USBNC_OTG1_PHY_STATUS_VBUS_VLD_SHIFT (3U)
48548/*! VBUS_VLD - VBUS Valid Indicator from USB OTG PHY
48549 * 0b0..The voltage on USB_OTG*_VBUS is below the VBUS Valid threshold
48550 * 0b1..The voltage on USB_OTG*_VBUS is above the VBUS Valid threshold
48551 */
48552#define USBNC_OTG1_PHY_STATUS_VBUS_VLD(x) \
48553 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_VBUS_VLD_SHIFT)) & USBNC_OTG1_PHY_STATUS_VBUS_VLD_MASK)
48554#define USBNC_OTG1_PHY_STATUS_ID_DIG_MASK (0x10U)
48555#define USBNC_OTG1_PHY_STATUS_ID_DIG_SHIFT (4U)
48556/*! ID_DIG - Micro- or Mini- A/B Plug Indicator
48557 * 0b0..The connnected plug is a Micro- or Mini-A plug
48558 * 0b1..The connnected plug is a Micro- or Mini-B plug
48559 */
48560#define USBNC_OTG1_PHY_STATUS_ID_DIG(x) \
48561 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_ID_DIG_SHIFT)) & USBNC_OTG1_PHY_STATUS_ID_DIG_MASK)
48562#define USBNC_OTG1_PHY_STATUS_HOST_DISCONNECT_MASK (0x20U)
48563#define USBNC_OTG1_PHY_STATUS_HOST_DISCONNECT_SHIFT (5U)
48564/*! HOST_DISCONNECT - Peripheral Disconnect Indicator
48565 * 0b0..Peripheral is connected
48566 * 0b1..No peripheral is connected
48567 */
48568#define USBNC_OTG1_PHY_STATUS_HOST_DISCONNECT(x) \
48569 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_HOST_DISCONNECT_SHIFT)) & \
48570 USBNC_OTG1_PHY_STATUS_HOST_DISCONNECT_MASK)
48571#define USBNC_OTG1_PHY_STATUS_RIDC0_MASK (0x1000000U)
48572#define USBNC_OTG1_PHY_STATUS_RIDC0_SHIFT (24U)
48573/*! RIDC0 - ACA USB_OTG*_ID Pin Resistance Indicator
48574 * 0b0..ACA OTG_ID pin resistance is >= RID_B (min) and <= RID_GND max
48575 * 0b1..ACA OTG_ID pin resistance is >= RID_C (min) and <= RID_C max
48576 */
48577#define USBNC_OTG1_PHY_STATUS_RIDC0(x) \
48578 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_RIDC0_SHIFT)) & USBNC_OTG1_PHY_STATUS_RIDC0_MASK)
48579#define USBNC_OTG1_PHY_STATUS_RIDB0_MASK (0x2000000U)
48580#define USBNC_OTG1_PHY_STATUS_RIDB0_SHIFT (25U)
48581/*! RIDB0 - ACA USB_OTG*_ID Pin Resistance Indicator
48582 * 0b0..ACA OTG_ID pin resistance is >= RID_A (min) and <= RID_C max
48583 * 0b1..ACA OTG_ID pin resistance is >= RID_B (min) and <= RID_B max
48584 */
48585#define USBNC_OTG1_PHY_STATUS_RIDB0(x) \
48586 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_RIDB0_SHIFT)) & USBNC_OTG1_PHY_STATUS_RIDB0_MASK)
48587#define USBNC_OTG1_PHY_STATUS_RIDA0_MASK (0x4000000U)
48588#define USBNC_OTG1_PHY_STATUS_RIDA0_SHIFT (26U)
48589/*! RIDA0 - ACA USB_OTG*_ID Pin Resistance Indicator
48590 * 0b0..ACA OTG_ID pin resistance is >= RID_FLOAT (min) and <= RID_B max
48591 * 0b1..ACA OTG_ID pin resistance is >= RID_A (min) and <= RID_A max
48592 */
48593#define USBNC_OTG1_PHY_STATUS_RIDA0(x) \
48594 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_RIDA0_SHIFT)) & USBNC_OTG1_PHY_STATUS_RIDA0_MASK)
48595#define USBNC_OTG1_PHY_STATUS_RIDGND0_MASK (0x8000000U)
48596#define USBNC_OTG1_PHY_STATUS_RIDGND0_SHIFT (27U)
48597/*! RIDGND0 - ACA USB_OTG*_ID Pin Resistance Indicator
48598 * 0b0..ACA OTG_ID pin resistance is >= RID_C (min)
48599 * 0b1..ACA OTG_ID pin resistance is <= RID_GND (max)
48600 */
48601#define USBNC_OTG1_PHY_STATUS_RIDGND0(x) \
48602 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_RIDGND0_SHIFT)) & USBNC_OTG1_PHY_STATUS_RIDGND0_MASK)
48603#define USBNC_OTG1_PHY_STATUS_RIDFLOAT0_MASK (0x10000000U)
48604#define USBNC_OTG1_PHY_STATUS_RIDFLOAT0_SHIFT (28U)
48605/*! RIDFLOAT0 - ACA USB_OTG*_ID Pin Resistance Indicator
48606 * 0b0..ACA OTG_ID pin resistance is <= RID_A (max)
48607 * 0b1..ACA OTG_ID pin resistance is >= RID_FLOAT (min)
48608 */
48609#define USBNC_OTG1_PHY_STATUS_RIDFLOAT0(x) \
48610 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_RIDFLOAT0_SHIFT)) & USBNC_OTG1_PHY_STATUS_RIDFLOAT0_MASK)
48611#define USBNC_OTG1_PHY_STATUS_CHRGDET_MASK (0x20000000U)
48612#define USBNC_OTG1_PHY_STATUS_CHRGDET_SHIFT (29U)
48613/*! CHRGDET - Battery Charger Detection Output
48614 * 0b0..VD* < VDAT_REF
48615 * 0b1..VD* > VDAT_REF
48616 */
48617#define USBNC_OTG1_PHY_STATUS_CHRGDET(x) \
48618 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_CHRGDET_SHIFT)) & USBNC_OTG1_PHY_STATUS_CHRGDET_MASK)
48619#define USBNC_OTG1_PHY_STATUS_ADPPRB0_MASK (0x40000000U)
48620#define USBNC_OTG1_PHY_STATUS_ADPPRB0_SHIFT (30U)
48621/*! ADPPRB0 - ADP Probe Indicator
48622 * 0b0..The voltage on USB_OTG*_VBUS is below the ADP probing voltage
48623 * 0b1..The voltage on USB_OTG*_VBUS is above the ADP probing voltage
48624 */
48625#define USBNC_OTG1_PHY_STATUS_ADPPRB0(x) \
48626 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_ADPPRB0_SHIFT)) & USBNC_OTG1_PHY_STATUS_ADPPRB0_MASK)
48627#define USBNC_OTG1_PHY_STATUS_ADPSNS0_MASK (0x80000000U)
48628#define USBNC_OTG1_PHY_STATUS_ADPSNS0_SHIFT (31U)
48629/*! ADPSNS0 - ADP Sense Indicator
48630 * 0b0..The voltage on USB_OTG*_VBUS is below the ADP sensing voltage
48631 * 0b1..The voltage on USB_OTG*_VBUS is above the ADP sensing voltage
48632 */
48633#define USBNC_OTG1_PHY_STATUS_ADPSNS0(x) \
48634 (((uint32_t)(((uint32_t)(x)) << USBNC_OTG1_PHY_STATUS_ADPSNS0_SHIFT)) & USBNC_OTG1_PHY_STATUS_ADPSNS0_MASK)
48635/*! @} */
48636
48637/*! @name ADP_CFG1 - */
48638/*! @{ */
48639#define USBNC_ADP_CFG1_ADP_WAIT_MASK (0x3FFFFU)
48640#define USBNC_ADP_CFG1_ADP_WAIT_SHIFT (0U)
48641/*! ADP_WAIT
48642 * 0b001100000000000000..Default
48643 */
48644#define USBNC_ADP_CFG1_ADP_WAIT(x) \
48645 (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG1_ADP_WAIT_SHIFT)) & USBNC_ADP_CFG1_ADP_WAIT_MASK)
48646#define USBNC_ADP_CFG1_TIMER_EN_MASK (0x100000U)
48647#define USBNC_ADP_CFG1_TIMER_EN_SHIFT (20U)
48648/*! TIMER_EN - ADP Timer Test Enable
48649 * 0b0..Default
48650 */
48651#define USBNC_ADP_CFG1_TIMER_EN(x) \
48652 (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG1_TIMER_EN_SHIFT)) & USBNC_ADP_CFG1_TIMER_EN_MASK)
48653#define USBNC_ADP_CFG1_ADP_SNS_INT_EN_MASK (0x200000U)
48654#define USBNC_ADP_CFG1_ADP_SNS_INT_EN_SHIFT (21U)
48655/*! ADP_SNS_INT_EN - ADP Sense Interrupt Enable
48656 * 0b0..Default
48657 */
48658#define USBNC_ADP_CFG1_ADP_SNS_INT_EN(x) \
48659 (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG1_ADP_SNS_INT_EN_SHIFT)) & USBNC_ADP_CFG1_ADP_SNS_INT_EN_MASK)
48660#define USBNC_ADP_CFG1_ADP_PRB_INT_EN_MASK (0x400000U)
48661#define USBNC_ADP_CFG1_ADP_PRB_INT_EN_SHIFT (22U)
48662/*! ADP_PRB_INT_EN
48663 * 0b0..Default
48664 */
48665#define USBNC_ADP_CFG1_ADP_PRB_INT_EN(x) \
48666 (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG1_ADP_PRB_INT_EN_SHIFT)) & USBNC_ADP_CFG1_ADP_PRB_INT_EN_MASK)
48667#define USBNC_ADP_CFG1_ADP_PRB_EN_MASK (0x800000U)
48668#define USBNC_ADP_CFG1_ADP_PRB_EN_SHIFT (23U)
48669/*! ADP_PRB_EN
48670 * 0b0..Default
48671 */
48672#define USBNC_ADP_CFG1_ADP_PRB_EN(x) \
48673 (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG1_ADP_PRB_EN_SHIFT)) & USBNC_ADP_CFG1_ADP_PRB_EN_MASK)
48674/*! @} */
48675
48676/*! @name ADP_CFG2 - */
48677/*! @{ */
48678#define USBNC_ADP_CFG2_ADP_CHRG_DELTA_MASK (0x7FU)
48679#define USBNC_ADP_CFG2_ADP_CHRG_DELTA_SHIFT (0U)
48680/*! ADP_CHRG_DELTA
48681 * 0b0010000..Default
48682 */
48683#define USBNC_ADP_CFG2_ADP_CHRG_DELTA(x) \
48684 (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG2_ADP_CHRG_DELTA_SHIFT)) & USBNC_ADP_CFG2_ADP_CHRG_DELTA_MASK)
48685#define USBNC_ADP_CFG2_ADP_CHRG_SWCMP_MASK (0x80U)
48686#define USBNC_ADP_CFG2_ADP_CHRG_SWCMP_SHIFT (7U)
48687/*! ADP_CHRG_SWCMP
48688 * 0b0..Default
48689 */
48690#define USBNC_ADP_CFG2_ADP_CHRG_SWCMP(x) \
48691 (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG2_ADP_CHRG_SWCMP_SHIFT)) & USBNC_ADP_CFG2_ADP_CHRG_SWCMP_MASK)
48692#define USBNC_ADP_CFG2_ADP_CHRG_SWTIME_MASK (0xFF00U)
48693#define USBNC_ADP_CFG2_ADP_CHRG_SWTIME_SHIFT (8U)
48694/*! ADP_CHRG_SWTIME
48695 * 0b01000000..Default
48696 */
48697#define USBNC_ADP_CFG2_ADP_CHRG_SWTIME(x) \
48698 (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG2_ADP_CHRG_SWTIME_SHIFT)) & USBNC_ADP_CFG2_ADP_CHRG_SWTIME_MASK)
48699#define USBNC_ADP_CFG2_ADP_DISCHG_TIME_MASK (0xFF0000U)
48700#define USBNC_ADP_CFG2_ADP_DISCHG_TIME_SHIFT (16U)
48701/*! ADP_DISCHG_TIME - ADP Discharge time
48702 * 0b01000110..Default
48703 */
48704#define USBNC_ADP_CFG2_ADP_DISCHG_TIME(x) \
48705 (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_CFG2_ADP_DISCHG_TIME_SHIFT)) & USBNC_ADP_CFG2_ADP_DISCHG_TIME_MASK)
48706/*! @} */
48707
48708/*! @name ADP_STATUS - */
48709/*! @{ */
48710#define USBNC_ADP_STATUS_ADP_PRB_TIMR_MASK (0xFFU)
48711#define USBNC_ADP_STATUS_ADP_PRB_TIMR_SHIFT (0U)
48712/*! ADP_PRB_TIMR - ADP Probe Time
48713 * 0b00000000..Default
48714 */
48715#define USBNC_ADP_STATUS_ADP_PRB_TIMR(x) \
48716 (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_STATUS_ADP_PRB_TIMR_SHIFT)) & USBNC_ADP_STATUS_ADP_PRB_TIMR_MASK)
48717#define USBNC_ADP_STATUS_ADP_CNT_MASK (0x3FFFF00U)
48718#define USBNC_ADP_STATUS_ADP_CNT_SHIFT (8U)
48719#define USBNC_ADP_STATUS_ADP_CNT(x) \
48720 (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_STATUS_ADP_CNT_SHIFT)) & USBNC_ADP_STATUS_ADP_CNT_MASK)
48721#define USBNC_ADP_STATUS_ADP_SNS_INT_MASK (0x4000000U)
48722#define USBNC_ADP_STATUS_ADP_SNS_INT_SHIFT (26U)
48723/*! ADP_SNS_INT - ADP Sense Interrupt Status
48724 * 0b0..Default
48725 */
48726#define USBNC_ADP_STATUS_ADP_SNS_INT(x) \
48727 (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_STATUS_ADP_SNS_INT_SHIFT)) & USBNC_ADP_STATUS_ADP_SNS_INT_MASK)
48728#define USBNC_ADP_STATUS_ADP_PRB_INT_MASK (0x8000000U)
48729#define USBNC_ADP_STATUS_ADP_PRB_INT_SHIFT (27U)
48730/*! ADP_PRB_INT - ADP Probe Interrupt Status
48731 * 0b0..Default
48732 */
48733#define USBNC_ADP_STATUS_ADP_PRB_INT(x) \
48734 (((uint32_t)(((uint32_t)(x)) << USBNC_ADP_STATUS_ADP_PRB_INT_SHIFT)) & USBNC_ADP_STATUS_ADP_PRB_INT_MASK)
48735/*! @} */
48736
48737/*!
48738 * @}
48739 */ /* end of group USBNC_Register_Masks */
48740
48741/* USBNC - Peripheral instance base addresses */
48742/** Peripheral USBNC base address */
48743#define USBNC_BASE (0x32E40000u)
48744/** Peripheral USBNC base pointer */
48745#define USBNC ((USBNC_Type *)USBNC_BASE)
48746/** Array initializer of USBNC peripheral base addresses */
48747#define USBNC_BASE_ADDRS \
48748 { \
48749 USBNC_BASE \
48750 }
48751/** Array initializer of USBNC peripheral base pointers */
48752#define USBNC_BASE_PTRS \
48753 { \
48754 USBNC \
48755 }
48756
48757/*!
48758 * @}
48759 */ /* end of group USBNC_Peripheral_Access_Layer */
48760
48761/* ----------------------------------------------------------------------------
48762 -- USDHC Peripheral Access Layer
48763 ---------------------------------------------------------------------------- */
48764
48765/*!
48766 * @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
48767 * @{
48768 */
48769
48770/** USDHC - Register Layout Typedef */
48771typedef struct
48772{
48773 __IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */
48774 __IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */
48775 __IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */
48776 __IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */
48777 __I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */
48778 __I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */
48779 __I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */
48780 __I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */
48781 __IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */
48782 __I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */
48783 __IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */
48784 __IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */
48785 __IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */
48786 __IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */
48787 __IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */
48788 __IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */
48789 __IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */
48790 __IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */
48791 __IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */
48792 uint8_t RESERVED_0[4];
48793 __O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */
48794 __I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status Register, offset: 0x54 */
48795 __IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */
48796 uint8_t RESERVED_1[4];
48797 __IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */
48798 __I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */
48799 __IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */
48800 uint8_t RESERVED_2[4];
48801 __IO uint32_t STROBE_DLL_CTRL; /**< Strobe DLL Control, offset: 0x70 */
48802 __I uint32_t STROBE_DLL_STATUS; /**< Strobe DLL Status, offset: 0x74 */
48803 uint8_t RESERVED_3[72];
48804 __IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */
48805 __IO uint32_t MMC_BOOT; /**< MMC Boot Register, offset: 0xC4 */
48806 __IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */
48807 __IO uint32_t TUNING_CTRL; /**< Tuning Control Register, offset: 0xCC */
48808} USDHC_Type;
48809
48810/* ----------------------------------------------------------------------------
48811 -- USDHC Register Masks
48812 ---------------------------------------------------------------------------- */
48813
48814/*!
48815 * @addtogroup USDHC_Register_Masks USDHC Register Masks
48816 * @{
48817 */
48818
48819/*! @name DS_ADDR - DMA System Address */
48820/*! @{ */
48821#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFCU)
48822#define USDHC_DS_ADDR_DS_ADDR_SHIFT (2U)
48823#define USDHC_DS_ADDR_DS_ADDR(x) \
48824 (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
48825/*! @} */
48826
48827/*! @name BLK_ATT - Block Attributes */
48828/*! @{ */
48829#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)
48830#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)
48831/*! BLKSIZE
48832 * 0b0000000001000..4096 Bytes
48833 * 0b0001100100000..2048 Bytes
48834 * 0b0000011001000..512 Bytes
48835 * 0b0000000000100..4 Bytes
48836 * 0b0000000000011..3 Bytes
48837 * 0b0000000000010..2 Bytes
48838 * 0b0000000000001..1 Byte
48839 * 0b0000000000000..No data transfer
48840 */
48841#define USDHC_BLK_ATT_BLKSIZE(x) \
48842 (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
48843#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)
48844#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U)
48845/*! BLKCNT
48846 * 0b0000000000000010..2 blocks
48847 * 0b0000000000000001..1 block
48848 * 0b0000000000000000..Stop Count
48849 */
48850#define USDHC_BLK_ATT_BLKCNT(x) \
48851 (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
48852/*! @} */
48853
48854/*! @name CMD_ARG - Command Argument */
48855/*! @{ */
48856#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)
48857#define USDHC_CMD_ARG_CMDARG_SHIFT (0U)
48858#define USDHC_CMD_ARG_CMDARG(x) \
48859 (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
48860/*! @} */
48861
48862/*! @name CMD_XFR_TYP - Command Transfer Type */
48863/*! @{ */
48864#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)
48865#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)
48866/*! RSPTYP - Response Type Select
48867 * 0b00..No Response
48868 * 0b01..Response Length 136
48869 * 0b10..Response Length 48
48870 * 0b11..Response Length 48, check Busy after response
48871 */
48872#define USDHC_CMD_XFR_TYP_RSPTYP(x) \
48873 (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
48874#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)
48875#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)
48876/*! CCCEN - Command CRC Check Enable
48877 * 0b1..Enable
48878 * 0b0..Disable
48879 */
48880#define USDHC_CMD_XFR_TYP_CCCEN(x) \
48881 (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
48882#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)
48883#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)
48884/*! CICEN - Command Index Check Enable
48885 * 0b1..Enable
48886 * 0b0..Disable
48887 */
48888#define USDHC_CMD_XFR_TYP_CICEN(x) \
48889 (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
48890#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)
48891#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)
48892/*! DPSEL - Data Present Select
48893 * 0b1..Data Present
48894 * 0b0..No Data Present
48895 */
48896#define USDHC_CMD_XFR_TYP_DPSEL(x) \
48897 (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
48898#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)
48899#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)
48900/*! CMDTYP - Command Type
48901 * 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
48902 * 0b10..Resume CMD52 for writing Function Select in CCCR
48903 * 0b01..Suspend CMD52 for writing Bus Suspend in CCCR
48904 * 0b00..Normal Other commands
48905 */
48906#define USDHC_CMD_XFR_TYP_CMDTYP(x) \
48907 (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
48908#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)
48909#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)
48910#define USDHC_CMD_XFR_TYP_CMDINX(x) \
48911 (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
48912/*! @} */
48913
48914/*! @name CMD_RSP0 - Command Response0 */
48915/*! @{ */
48916#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)
48917#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)
48918#define USDHC_CMD_RSP0_CMDRSP0(x) \
48919 (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
48920/*! @} */
48921
48922/*! @name CMD_RSP1 - Command Response1 */
48923/*! @{ */
48924#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)
48925#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)
48926#define USDHC_CMD_RSP1_CMDRSP1(x) \
48927 (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
48928/*! @} */
48929
48930/*! @name CMD_RSP2 - Command Response2 */
48931/*! @{ */
48932#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)
48933#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)
48934#define USDHC_CMD_RSP2_CMDRSP2(x) \
48935 (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
48936/*! @} */
48937
48938/*! @name CMD_RSP3 - Command Response3 */
48939/*! @{ */
48940#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)
48941#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)
48942#define USDHC_CMD_RSP3_CMDRSP3(x) \
48943 (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
48944/*! @} */
48945
48946/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
48947/*! @{ */
48948#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)
48949#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)
48950#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) \
48951 (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
48952/*! @} */
48953
48954/*! @name PRES_STATE - Present State */
48955/*! @{ */
48956#define USDHC_PRES_STATE_CIHB_MASK (0x1U)
48957#define USDHC_PRES_STATE_CIHB_SHIFT (0U)
48958/*! CIHB - Command Inhibit (CMD)
48959 * 0b1..Cannot issue command
48960 * 0b0..Can issue command using only CMD line
48961 */
48962#define USDHC_PRES_STATE_CIHB(x) \
48963 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
48964#define USDHC_PRES_STATE_CDIHB_MASK (0x2U)
48965#define USDHC_PRES_STATE_CDIHB_SHIFT (1U)
48966/*! CDIHB - Command Inhibit (DATA)
48967 * 0b1..Cannot issue command which uses the DATA line
48968 * 0b0..Can issue command which uses the DATA line
48969 */
48970#define USDHC_PRES_STATE_CDIHB(x) \
48971 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
48972#define USDHC_PRES_STATE_DLA_MASK (0x4U)
48973#define USDHC_PRES_STATE_DLA_SHIFT (2U)
48974/*! DLA - Data Line Active
48975 * 0b1..DATA Line Active
48976 * 0b0..DATA Line Inactive
48977 */
48978#define USDHC_PRES_STATE_DLA(x) \
48979 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
48980#define USDHC_PRES_STATE_SDSTB_MASK (0x8U)
48981#define USDHC_PRES_STATE_SDSTB_SHIFT (3U)
48982/*! SDSTB - SD Clock Stable
48983 * 0b1..Clock is stable.
48984 * 0b0..Clock is changing frequency and not stable.
48985 */
48986#define USDHC_PRES_STATE_SDSTB(x) \
48987 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
48988#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U)
48989#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U)
48990/*! IPGOFF - IPG_CLK Gated Off Internally
48991 * 0b1..IPG_CLK is gated off.
48992 * 0b0..IPG_CLK is active.
48993 */
48994#define USDHC_PRES_STATE_IPGOFF(x) \
48995 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
48996#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U)
48997#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U)
48998/*! HCKOFF - HCLK Gated Off Internally
48999 * 0b1..HCLK is gated off.
49000 * 0b0..HCLK is active.
49001 */
49002#define USDHC_PRES_STATE_HCKOFF(x) \
49003 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
49004#define USDHC_PRES_STATE_PEROFF_MASK (0x40U)
49005#define USDHC_PRES_STATE_PEROFF_SHIFT (6U)
49006/*! PEROFF - IPG_PERCLK Gated Off Internally
49007 * 0b1..IPG_PERCLK is gated off.
49008 * 0b0..IPG_PERCLK is active.
49009 */
49010#define USDHC_PRES_STATE_PEROFF(x) \
49011 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
49012#define USDHC_PRES_STATE_SDOFF_MASK (0x80U)
49013#define USDHC_PRES_STATE_SDOFF_SHIFT (7U)
49014/*! SDOFF - SD Clock Gated Off Internally
49015 * 0b1..SD Clock is gated off.
49016 * 0b0..SD Clock is active.
49017 */
49018#define USDHC_PRES_STATE_SDOFF(x) \
49019 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
49020#define USDHC_PRES_STATE_WTA_MASK (0x100U)
49021#define USDHC_PRES_STATE_WTA_SHIFT (8U)
49022/*! WTA - Write Transfer Active
49023 * 0b1..Transferring data
49024 * 0b0..No valid data
49025 */
49026#define USDHC_PRES_STATE_WTA(x) \
49027 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
49028#define USDHC_PRES_STATE_RTA_MASK (0x200U)
49029#define USDHC_PRES_STATE_RTA_SHIFT (9U)
49030/*! RTA - Read Transfer Active
49031 * 0b1..Transferring data
49032 * 0b0..No valid data
49033 */
49034#define USDHC_PRES_STATE_RTA(x) \
49035 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
49036#define USDHC_PRES_STATE_BWEN_MASK (0x400U)
49037#define USDHC_PRES_STATE_BWEN_SHIFT (10U)
49038/*! BWEN - Buffer Write Enable
49039 * 0b1..Write enable
49040 * 0b0..Write disable
49041 */
49042#define USDHC_PRES_STATE_BWEN(x) \
49043 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
49044#define USDHC_PRES_STATE_BREN_MASK (0x800U)
49045#define USDHC_PRES_STATE_BREN_SHIFT (11U)
49046/*! BREN - Buffer Read Enable
49047 * 0b1..Read enable
49048 * 0b0..Read disable
49049 */
49050#define USDHC_PRES_STATE_BREN(x) \
49051 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
49052#define USDHC_PRES_STATE_RTR_MASK (0x1000U)
49053#define USDHC_PRES_STATE_RTR_SHIFT (12U)
49054/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode)
49055 * 0b1..Sampling clock needs re-tuning
49056 * 0b0..Fixed or well tuned sampling clock
49057 */
49058#define USDHC_PRES_STATE_RTR(x) \
49059 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
49060#define USDHC_PRES_STATE_TSCD_MASK (0x8000U)
49061#define USDHC_PRES_STATE_TSCD_SHIFT (15U)
49062/*! TSCD - Tape Select Change Done
49063 * 0b1..Delay cell select change is finished.
49064 * 0b0..Delay cell select change is not finished.
49065 */
49066#define USDHC_PRES_STATE_TSCD(x) \
49067 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
49068#define USDHC_PRES_STATE_CINST_MASK (0x10000U)
49069#define USDHC_PRES_STATE_CINST_SHIFT (16U)
49070/*! CINST - Card Inserted
49071 * 0b1..Card Inserted
49072 * 0b0..Power on Reset or No Card
49073 */
49074#define USDHC_PRES_STATE_CINST(x) \
49075 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
49076#define USDHC_PRES_STATE_CDPL_MASK (0x40000U)
49077#define USDHC_PRES_STATE_CDPL_SHIFT (18U)
49078/*! CDPL - Card Detect Pin Level
49079 * 0b1..Card present (CD_B = 0)
49080 * 0b0..No card present (CD_B = 1)
49081 */
49082#define USDHC_PRES_STATE_CDPL(x) \
49083 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
49084#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U)
49085#define USDHC_PRES_STATE_WPSPL_SHIFT (19U)
49086/*! WPSPL - Write Protect Switch Pin Level
49087 * 0b1..Write enabled (WP = 0)
49088 * 0b0..Write protected (WP = 1)
49089 */
49090#define USDHC_PRES_STATE_WPSPL(x) \
49091 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
49092#define USDHC_PRES_STATE_CLSL_MASK (0x800000U)
49093#define USDHC_PRES_STATE_CLSL_SHIFT (23U)
49094#define USDHC_PRES_STATE_CLSL(x) \
49095 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
49096#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)
49097#define USDHC_PRES_STATE_DLSL_SHIFT (24U)
49098#define USDHC_PRES_STATE_DLSL(x) \
49099 (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
49100/*! @} */
49101
49102/*! @name PROT_CTRL - Protocol Control */
49103/*! @{ */
49104#define USDHC_PROT_CTRL_LCTL_MASK (0x1U)
49105#define USDHC_PROT_CTRL_LCTL_SHIFT (0U)
49106/*! LCTL - LED Control
49107 * 0b1..LED on
49108 * 0b0..LED off
49109 */
49110#define USDHC_PROT_CTRL_LCTL(x) \
49111 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_LCTL_SHIFT)) & USDHC_PROT_CTRL_LCTL_MASK)
49112#define USDHC_PROT_CTRL_DTW_MASK (0x6U)
49113#define USDHC_PROT_CTRL_DTW_SHIFT (1U)
49114/*! DTW - Data Transfer Width
49115 * 0b10..8-bit mode
49116 * 0b01..4-bit mode
49117 * 0b00..1-bit mode
49118 * 0b11..Reserved
49119 */
49120#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
49121#define USDHC_PROT_CTRL_D3CD_MASK (0x8U)
49122#define USDHC_PROT_CTRL_D3CD_SHIFT (3U)
49123/*! D3CD - DATA3 as Card Detection Pin
49124 * 0b1..DATA3 as Card Detection Pin
49125 * 0b0..DATA3 does not monitor Card Insertion
49126 */
49127#define USDHC_PROT_CTRL_D3CD(x) \
49128 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
49129#define USDHC_PROT_CTRL_EMODE_MASK (0x30U)
49130#define USDHC_PROT_CTRL_EMODE_SHIFT (4U)
49131/*! EMODE - Endian Mode
49132 * 0b00..Big Endian Mode
49133 * 0b01..Half Word Big Endian Mode
49134 * 0b10..Little Endian Mode
49135 * 0b11..Reserved
49136 */
49137#define USDHC_PROT_CTRL_EMODE(x) \
49138 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
49139#define USDHC_PROT_CTRL_CDTL_MASK (0x40U)
49140#define USDHC_PROT_CTRL_CDTL_SHIFT (6U)
49141/*! CDTL - Card Detect Test Level
49142 * 0b1..Card Detect Test Level is 1, card inserted
49143 * 0b0..Card Detect Test Level is 0, no card inserted
49144 */
49145#define USDHC_PROT_CTRL_CDTL(x) \
49146 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
49147#define USDHC_PROT_CTRL_CDSS_MASK (0x80U)
49148#define USDHC_PROT_CTRL_CDSS_SHIFT (7U)
49149/*! CDSS - Card Detect Signal Selection
49150 * 0b1..Card Detection Test Level is selected (for test purpose).
49151 * 0b0..Card Detection Level is selected (for normal purpose).
49152 */
49153#define USDHC_PROT_CTRL_CDSS(x) \
49154 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
49155#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U)
49156#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U)
49157/*! DMASEL - DMA Select
49158 * 0b00..No DMA or Simple DMA is selected
49159 * 0b01..ADMA1 is selected
49160 * 0b10..ADMA2 is selected
49161 * 0b11..reserved
49162 */
49163#define USDHC_PROT_CTRL_DMASEL(x) \
49164 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
49165#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)
49166#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)
49167/*! SABGREQ - Stop At Block Gap Request
49168 * 0b1..Stop
49169 * 0b0..Transfer
49170 */
49171#define USDHC_PROT_CTRL_SABGREQ(x) \
49172 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
49173#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U)
49174#define USDHC_PROT_CTRL_CREQ_SHIFT (17U)
49175/*! CREQ - Continue Request
49176 * 0b1..Restart
49177 * 0b0..No effect
49178 */
49179#define USDHC_PROT_CTRL_CREQ(x) \
49180 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
49181#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)
49182#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U)
49183/*! RWCTL - Read Wait Control
49184 * 0b1..Enable Read Wait Control, and assert Read Wait without stopping SD Clock at block gap when SABGREQ bit is set
49185 * 0b0..Disable Read Wait Control, and stop SD Clock at block gap when SABGREQ bit is set
49186 */
49187#define USDHC_PROT_CTRL_RWCTL(x) \
49188 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
49189#define USDHC_PROT_CTRL_IABG_MASK (0x80000U)
49190#define USDHC_PROT_CTRL_IABG_SHIFT (19U)
49191/*! IABG - Interrupt At Block Gap
49192 * 0b1..Enabled
49193 * 0b0..Disabled
49194 */
49195#define USDHC_PROT_CTRL_IABG(x) \
49196 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
49197#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)
49198#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)
49199#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) \
49200 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
49201#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)
49202#define USDHC_PROT_CTRL_WECINT_SHIFT (24U)
49203/*! WECINT - Wakeup Event Enable On Card Interrupt
49204 * 0b1..Enable
49205 * 0b0..Disable
49206 */
49207#define USDHC_PROT_CTRL_WECINT(x) \
49208 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
49209#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)
49210#define USDHC_PROT_CTRL_WECINS_SHIFT (25U)
49211/*! WECINS - Wakeup Event Enable On SD Card Insertion
49212 * 0b1..Enable
49213 * 0b0..Disable
49214 */
49215#define USDHC_PROT_CTRL_WECINS(x) \
49216 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
49217#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)
49218#define USDHC_PROT_CTRL_WECRM_SHIFT (26U)
49219/*! WECRM - Wakeup Event Enable On SD Card Removal
49220 * 0b1..Enable
49221 * 0b0..Disable
49222 */
49223#define USDHC_PROT_CTRL_WECRM(x) \
49224 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
49225#define USDHC_PROT_CTRL_BURST_LEN_EN_MASK (0x38000000U)
49226#define USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT (27U)
49227/*! BURST_LEN_EN - BURST length enable for INCR, INCR4 / INCR8 / INCR16, INCR4-WRAP / INCR8-WRAP / INCR16-WRAP
49228 * 0bxx1..Burst length is enabled for INCR
49229 * 0bx1x..Burst length is enabled for INCR4 / INCR8 / INCR16
49230 * 0b1xx..Burst length is enabled for INCR4-WRAP / INCR8-WRAP / INCR16-WRAP
49231 */
49232#define USDHC_PROT_CTRL_BURST_LEN_EN(x) \
49233 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_BURST_LEN_EN_SHIFT)) & USDHC_PROT_CTRL_BURST_LEN_EN_MASK)
49234#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)
49235#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)
49236/*! NON_EXACT_BLK_RD
49237 * 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block
49238 * read. 0b0..The block read is exact block read. Host driver doesn't need to issue abort command to terminate this
49239 * multi-block read.
49240 */
49241#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) \
49242 (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
49243/*! @} */
49244
49245/*! @name SYS_CTRL - System Control */
49246/*! @{ */
49247#define USDHC_SYS_CTRL_DVS_MASK (0xF0U)
49248#define USDHC_SYS_CTRL_DVS_SHIFT (4U)
49249/*! DVS - Divisor
49250 * 0b0000..Divide-by-1
49251 * 0b0001..Divide-by-2
49252 * 0b1110..Divide-by-15
49253 * 0b1111..Divide-by-16
49254 */
49255#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
49256#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)
49257#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)
49258#define USDHC_SYS_CTRL_SDCLKFS(x) \
49259 (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
49260#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)
49261#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U)
49262/*! DTOCV - Data Timeout Counter Value
49263 * 0b1111..SDCLK x 2 29
49264 * 0b1110..SDCLK x 2 28
49265 * 0b0001..SDCLK x 2 15
49266 * 0b0000..SDCLK x 2 14
49267 */
49268#define USDHC_SYS_CTRL_DTOCV(x) \
49269 (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
49270#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)
49271#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)
49272#define USDHC_SYS_CTRL_IPP_RST_N(x) \
49273 (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
49274#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)
49275#define USDHC_SYS_CTRL_RSTA_SHIFT (24U)
49276/*! RSTA - Software Reset For ALL
49277 * 0b1..Reset
49278 * 0b0..No Reset
49279 */
49280#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
49281#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)
49282#define USDHC_SYS_CTRL_RSTC_SHIFT (25U)
49283/*! RSTC - Software Reset For CMD Line
49284 * 0b1..Reset
49285 * 0b0..No Reset
49286 */
49287#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
49288#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)
49289#define USDHC_SYS_CTRL_RSTD_SHIFT (26U)
49290/*! RSTD - Software Reset For DATA Line
49291 * 0b1..Reset
49292 * 0b0..No Reset
49293 */
49294#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
49295#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U)
49296#define USDHC_SYS_CTRL_INITA_SHIFT (27U)
49297#define USDHC_SYS_CTRL_INITA(x) \
49298 (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
49299#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)
49300#define USDHC_SYS_CTRL_RSTT_SHIFT (28U)
49301#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
49302/*! @} */
49303
49304/*! @name INT_STATUS - Interrupt Status */
49305/*! @{ */
49306#define USDHC_INT_STATUS_CC_MASK (0x1U)
49307#define USDHC_INT_STATUS_CC_SHIFT (0U)
49308/*! CC - Command Complete
49309 * 0b1..Command complete
49310 * 0b0..Command not complete
49311 */
49312#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
49313#define USDHC_INT_STATUS_TC_MASK (0x2U)
49314#define USDHC_INT_STATUS_TC_SHIFT (1U)
49315/*! TC - Transfer Complete
49316 * 0b1..Transfer complete
49317 * 0b0..Transfer not complete
49318 */
49319#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
49320#define USDHC_INT_STATUS_BGE_MASK (0x4U)
49321#define USDHC_INT_STATUS_BGE_SHIFT (2U)
49322/*! BGE - Block Gap Event
49323 * 0b1..Transaction stopped at block gap
49324 * 0b0..No block gap event
49325 */
49326#define USDHC_INT_STATUS_BGE(x) \
49327 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
49328#define USDHC_INT_STATUS_DINT_MASK (0x8U)
49329#define USDHC_INT_STATUS_DINT_SHIFT (3U)
49330/*! DINT - DMA Interrupt
49331 * 0b1..DMA Interrupt is generated
49332 * 0b0..No DMA Interrupt
49333 */
49334#define USDHC_INT_STATUS_DINT(x) \
49335 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
49336#define USDHC_INT_STATUS_BWR_MASK (0x10U)
49337#define USDHC_INT_STATUS_BWR_SHIFT (4U)
49338/*! BWR - Buffer Write Ready
49339 * 0b1..Ready to write buffer:
49340 * 0b0..Not ready to write buffer
49341 */
49342#define USDHC_INT_STATUS_BWR(x) \
49343 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
49344#define USDHC_INT_STATUS_BRR_MASK (0x20U)
49345#define USDHC_INT_STATUS_BRR_SHIFT (5U)
49346/*! BRR - Buffer Read Ready
49347 * 0b1..Ready to read buffer
49348 * 0b0..Not ready to read buffer
49349 */
49350#define USDHC_INT_STATUS_BRR(x) \
49351 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
49352#define USDHC_INT_STATUS_CINS_MASK (0x40U)
49353#define USDHC_INT_STATUS_CINS_SHIFT (6U)
49354/*! CINS - Card Insertion
49355 * 0b1..Card inserted
49356 * 0b0..Card state unstable or removed
49357 */
49358#define USDHC_INT_STATUS_CINS(x) \
49359 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
49360#define USDHC_INT_STATUS_CRM_MASK (0x80U)
49361#define USDHC_INT_STATUS_CRM_SHIFT (7U)
49362/*! CRM - Card Removal
49363 * 0b1..Card removed
49364 * 0b0..Card state unstable or inserted
49365 */
49366#define USDHC_INT_STATUS_CRM(x) \
49367 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
49368#define USDHC_INT_STATUS_CINT_MASK (0x100U)
49369#define USDHC_INT_STATUS_CINT_SHIFT (8U)
49370/*! CINT - Card Interrupt
49371 * 0b1..Generate Card Interrupt
49372 * 0b0..No Card Interrupt
49373 */
49374#define USDHC_INT_STATUS_CINT(x) \
49375 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
49376#define USDHC_INT_STATUS_RTE_MASK (0x1000U)
49377#define USDHC_INT_STATUS_RTE_SHIFT (12U)
49378/*! RTE - Re-Tuning Event: (only for SD3.0 SDR104 mode)
49379 * 0b1..Re-Tuning should be performed
49380 * 0b0..Re-Tuning is not required
49381 */
49382#define USDHC_INT_STATUS_RTE(x) \
49383 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
49384#define USDHC_INT_STATUS_TP_MASK (0x4000U)
49385#define USDHC_INT_STATUS_TP_SHIFT (14U)
49386#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
49387#define USDHC_INT_STATUS_CTOE_MASK (0x10000U)
49388#define USDHC_INT_STATUS_CTOE_SHIFT (16U)
49389/*! CTOE - Command Timeout Error
49390 * 0b1..Time out
49391 * 0b0..No Error
49392 */
49393#define USDHC_INT_STATUS_CTOE(x) \
49394 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
49395#define USDHC_INT_STATUS_CCE_MASK (0x20000U)
49396#define USDHC_INT_STATUS_CCE_SHIFT (17U)
49397/*! CCE - Command CRC Error
49398 * 0b1..CRC Error Generated.
49399 * 0b0..No Error
49400 */
49401#define USDHC_INT_STATUS_CCE(x) \
49402 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
49403#define USDHC_INT_STATUS_CEBE_MASK (0x40000U)
49404#define USDHC_INT_STATUS_CEBE_SHIFT (18U)
49405/*! CEBE - Command End Bit Error
49406 * 0b1..End Bit Error Generated
49407 * 0b0..No Error
49408 */
49409#define USDHC_INT_STATUS_CEBE(x) \
49410 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
49411#define USDHC_INT_STATUS_CIE_MASK (0x80000U)
49412#define USDHC_INT_STATUS_CIE_SHIFT (19U)
49413/*! CIE - Command Index Error
49414 * 0b1..Error
49415 * 0b0..No Error
49416 */
49417#define USDHC_INT_STATUS_CIE(x) \
49418 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
49419#define USDHC_INT_STATUS_DTOE_MASK (0x100000U)
49420#define USDHC_INT_STATUS_DTOE_SHIFT (20U)
49421/*! DTOE - Data Timeout Error
49422 * 0b1..Time out
49423 * 0b0..No Error
49424 */
49425#define USDHC_INT_STATUS_DTOE(x) \
49426 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
49427#define USDHC_INT_STATUS_DCE_MASK (0x200000U)
49428#define USDHC_INT_STATUS_DCE_SHIFT (21U)
49429/*! DCE - Data CRC Error
49430 * 0b1..Error
49431 * 0b0..No Error
49432 */
49433#define USDHC_INT_STATUS_DCE(x) \
49434 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
49435#define USDHC_INT_STATUS_DEBE_MASK (0x400000U)
49436#define USDHC_INT_STATUS_DEBE_SHIFT (22U)
49437/*! DEBE - Data End Bit Error
49438 * 0b1..Error
49439 * 0b0..No Error
49440 */
49441#define USDHC_INT_STATUS_DEBE(x) \
49442 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
49443#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U)
49444#define USDHC_INT_STATUS_AC12E_SHIFT (24U)
49445/*! AC12E - Auto CMD12 Error
49446 * 0b1..Error
49447 * 0b0..No Error
49448 */
49449#define USDHC_INT_STATUS_AC12E(x) \
49450 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
49451#define USDHC_INT_STATUS_TNE_MASK (0x4000000U)
49452#define USDHC_INT_STATUS_TNE_SHIFT (26U)
49453#define USDHC_INT_STATUS_TNE(x) \
49454 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
49455#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U)
49456#define USDHC_INT_STATUS_DMAE_SHIFT (28U)
49457/*! DMAE - DMA Error
49458 * 0b1..Error
49459 * 0b0..No Error
49460 */
49461#define USDHC_INT_STATUS_DMAE(x) \
49462 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
49463/*! @} */
49464
49465/*! @name INT_STATUS_EN - Interrupt Status Enable */
49466/*! @{ */
49467#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)
49468#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)
49469/*! CCSEN - Command Complete Status Enable
49470 * 0b1..Enabled
49471 * 0b0..Masked
49472 */
49473#define USDHC_INT_STATUS_EN_CCSEN(x) \
49474 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
49475#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)
49476#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)
49477/*! TCSEN - Transfer Complete Status Enable
49478 * 0b1..Enabled
49479 * 0b0..Masked
49480 */
49481#define USDHC_INT_STATUS_EN_TCSEN(x) \
49482 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
49483#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)
49484#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)
49485/*! BGESEN - Block Gap Event Status Enable
49486 * 0b1..Enabled
49487 * 0b0..Masked
49488 */
49489#define USDHC_INT_STATUS_EN_BGESEN(x) \
49490 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
49491#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)
49492#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)
49493/*! DINTSEN - DMA Interrupt Status Enable
49494 * 0b1..Enabled
49495 * 0b0..Masked
49496 */
49497#define USDHC_INT_STATUS_EN_DINTSEN(x) \
49498 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
49499#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)
49500#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)
49501/*! BWRSEN - Buffer Write Ready Status Enable
49502 * 0b1..Enabled
49503 * 0b0..Masked
49504 */
49505#define USDHC_INT_STATUS_EN_BWRSEN(x) \
49506 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
49507#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)
49508#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)
49509/*! BRRSEN - Buffer Read Ready Status Enable
49510 * 0b1..Enabled
49511 * 0b0..Masked
49512 */
49513#define USDHC_INT_STATUS_EN_BRRSEN(x) \
49514 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
49515#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)
49516#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)
49517/*! CINSSEN - Card Insertion Status Enable
49518 * 0b1..Enabled
49519 * 0b0..Masked
49520 */
49521#define USDHC_INT_STATUS_EN_CINSSEN(x) \
49522 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
49523#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)
49524#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)
49525/*! CRMSEN - Card Removal Status Enable
49526 * 0b1..Enabled
49527 * 0b0..Masked
49528 */
49529#define USDHC_INT_STATUS_EN_CRMSEN(x) \
49530 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
49531#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)
49532#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)
49533/*! CINTSEN - Card Interrupt Status Enable
49534 * 0b1..Enabled
49535 * 0b0..Masked
49536 */
49537#define USDHC_INT_STATUS_EN_CINTSEN(x) \
49538 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
49539#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)
49540#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)
49541/*! RTESEN - Re-Tuning Event Status Enable
49542 * 0b1..Enabled
49543 * 0b0..Masked
49544 */
49545#define USDHC_INT_STATUS_EN_RTESEN(x) \
49546 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
49547#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)
49548#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)
49549/*! TPSEN - Tuning Pass Status Enable
49550 * 0b1..Enabled
49551 * 0b0..Masked
49552 */
49553#define USDHC_INT_STATUS_EN_TPSEN(x) \
49554 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
49555#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)
49556#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)
49557/*! CTOESEN - Command Timeout Error Status Enable
49558 * 0b1..Enabled
49559 * 0b0..Masked
49560 */
49561#define USDHC_INT_STATUS_EN_CTOESEN(x) \
49562 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
49563#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)
49564#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)
49565/*! CCESEN - Command CRC Error Status Enable
49566 * 0b1..Enabled
49567 * 0b0..Masked
49568 */
49569#define USDHC_INT_STATUS_EN_CCESEN(x) \
49570 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
49571#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)
49572#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)
49573/*! CEBESEN - Command End Bit Error Status Enable
49574 * 0b1..Enabled
49575 * 0b0..Masked
49576 */
49577#define USDHC_INT_STATUS_EN_CEBESEN(x) \
49578 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
49579#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)
49580#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)
49581/*! CIESEN - Command Index Error Status Enable
49582 * 0b1..Enabled
49583 * 0b0..Masked
49584 */
49585#define USDHC_INT_STATUS_EN_CIESEN(x) \
49586 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
49587#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)
49588#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)
49589/*! DTOESEN - Data Timeout Error Status Enable
49590 * 0b1..Enabled
49591 * 0b0..Masked
49592 */
49593#define USDHC_INT_STATUS_EN_DTOESEN(x) \
49594 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
49595#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)
49596#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)
49597/*! DCESEN - Data CRC Error Status Enable
49598 * 0b1..Enabled
49599 * 0b0..Masked
49600 */
49601#define USDHC_INT_STATUS_EN_DCESEN(x) \
49602 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
49603#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)
49604#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)
49605/*! DEBESEN - Data End Bit Error Status Enable
49606 * 0b1..Enabled
49607 * 0b0..Masked
49608 */
49609#define USDHC_INT_STATUS_EN_DEBESEN(x) \
49610 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
49611#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)
49612#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)
49613/*! AC12ESEN - Auto CMD12 Error Status Enable
49614 * 0b1..Enabled
49615 * 0b0..Masked
49616 */
49617#define USDHC_INT_STATUS_EN_AC12ESEN(x) \
49618 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
49619#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)
49620#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)
49621/*! TNESEN - Tuning Error Status Enable
49622 * 0b1..Enabled
49623 * 0b0..Masked
49624 */
49625#define USDHC_INT_STATUS_EN_TNESEN(x) \
49626 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
49627#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)
49628#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)
49629/*! DMAESEN - DMA Error Status Enable
49630 * 0b1..Enabled
49631 * 0b0..Masked
49632 */
49633#define USDHC_INT_STATUS_EN_DMAESEN(x) \
49634 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
49635/*! @} */
49636
49637/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
49638/*! @{ */
49639#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)
49640#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)
49641/*! CCIEN - Command Complete Interrupt Enable
49642 * 0b1..Enabled
49643 * 0b0..Masked
49644 */
49645#define USDHC_INT_SIGNAL_EN_CCIEN(x) \
49646 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
49647#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)
49648#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)
49649/*! TCIEN - Transfer Complete Interrupt Enable
49650 * 0b1..Enabled
49651 * 0b0..Masked
49652 */
49653#define USDHC_INT_SIGNAL_EN_TCIEN(x) \
49654 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
49655#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)
49656#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)
49657/*! BGEIEN - Block Gap Event Interrupt Enable
49658 * 0b1..Enabled
49659 * 0b0..Masked
49660 */
49661#define USDHC_INT_SIGNAL_EN_BGEIEN(x) \
49662 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
49663#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)
49664#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)
49665/*! DINTIEN - DMA Interrupt Enable
49666 * 0b1..Enabled
49667 * 0b0..Masked
49668 */
49669#define USDHC_INT_SIGNAL_EN_DINTIEN(x) \
49670 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
49671#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)
49672#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)
49673/*! BWRIEN - Buffer Write Ready Interrupt Enable
49674 * 0b1..Enabled
49675 * 0b0..Masked
49676 */
49677#define USDHC_INT_SIGNAL_EN_BWRIEN(x) \
49678 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
49679#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)
49680#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)
49681/*! BRRIEN - Buffer Read Ready Interrupt Enable
49682 * 0b1..Enabled
49683 * 0b0..Masked
49684 */
49685#define USDHC_INT_SIGNAL_EN_BRRIEN(x) \
49686 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
49687#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)
49688#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)
49689/*! CINSIEN - Card Insertion Interrupt Enable
49690 * 0b1..Enabled
49691 * 0b0..Masked
49692 */
49693#define USDHC_INT_SIGNAL_EN_CINSIEN(x) \
49694 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
49695#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)
49696#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)
49697/*! CRMIEN - Card Removal Interrupt Enable
49698 * 0b1..Enabled
49699 * 0b0..Masked
49700 */
49701#define USDHC_INT_SIGNAL_EN_CRMIEN(x) \
49702 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
49703#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)
49704#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)
49705/*! CINTIEN - Card Interrupt Interrupt Enable
49706 * 0b1..Enabled
49707 * 0b0..Masked
49708 */
49709#define USDHC_INT_SIGNAL_EN_CINTIEN(x) \
49710 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
49711#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)
49712#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)
49713/*! RTEIEN - Re-Tuning Event Interrupt Enable
49714 * 0b1..Enabled
49715 * 0b0..Masked
49716 */
49717#define USDHC_INT_SIGNAL_EN_RTEIEN(x) \
49718 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
49719#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)
49720#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)
49721/*! TPIEN - Tuning Pass Interrupt Enable
49722 * 0b1..Enabled
49723 * 0b0..Masked
49724 */
49725#define USDHC_INT_SIGNAL_EN_TPIEN(x) \
49726 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
49727#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)
49728#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)
49729/*! CTOEIEN - Command Timeout Error Interrupt Enable
49730 * 0b1..Enabled
49731 * 0b0..Masked
49732 */
49733#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) \
49734 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
49735#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)
49736#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)
49737/*! CCEIEN - Command CRC Error Interrupt Enable
49738 * 0b1..Enabled
49739 * 0b0..Masked
49740 */
49741#define USDHC_INT_SIGNAL_EN_CCEIEN(x) \
49742 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
49743#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)
49744#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)
49745/*! CEBEIEN - Command End Bit Error Interrupt Enable
49746 * 0b1..Enabled
49747 * 0b0..Masked
49748 */
49749#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) \
49750 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
49751#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)
49752#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)
49753/*! CIEIEN - Command Index Error Interrupt Enable
49754 * 0b1..Enabled
49755 * 0b0..Masked
49756 */
49757#define USDHC_INT_SIGNAL_EN_CIEIEN(x) \
49758 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
49759#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)
49760#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)
49761/*! DTOEIEN - Data Timeout Error Interrupt Enable
49762 * 0b1..Enabled
49763 * 0b0..Masked
49764 */
49765#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) \
49766 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
49767#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)
49768#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)
49769/*! DCEIEN - Data CRC Error Interrupt Enable
49770 * 0b1..Enabled
49771 * 0b0..Masked
49772 */
49773#define USDHC_INT_SIGNAL_EN_DCEIEN(x) \
49774 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
49775#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)
49776#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)
49777/*! DEBEIEN - Data End Bit Error Interrupt Enable
49778 * 0b1..Enabled
49779 * 0b0..Masked
49780 */
49781#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) \
49782 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
49783#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)
49784#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)
49785/*! AC12EIEN - Auto CMD12 Error Interrupt Enable
49786 * 0b1..Enabled
49787 * 0b0..Masked
49788 */
49789#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) \
49790 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
49791#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)
49792#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)
49793/*! TNEIEN - Tuning Error Interrupt Enable
49794 * 0b1..Enabled
49795 * 0b0..Masked
49796 */
49797#define USDHC_INT_SIGNAL_EN_TNEIEN(x) \
49798 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
49799#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)
49800#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)
49801/*! DMAEIEN - DMA Error Interrupt Enable
49802 * 0b1..Enable
49803 * 0b0..Masked
49804 */
49805#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) \
49806 (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
49807/*! @} */
49808
49809/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
49810/*! @{ */
49811#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)
49812#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)
49813/*! AC12NE - Auto CMD12 Not Executed
49814 * 0b1..Not executed
49815 * 0b0..Executed
49816 */
49817#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) \
49818 (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
49819#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)
49820#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
49821/*! AC12TOE - Auto CMD12 / 23 Timeout Error
49822 * 0b1..Time out
49823 * 0b0..No error
49824 */
49825#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) \
49826 (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & \
49827 USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
49828#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)
49829#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
49830/*! AC12EBE - Auto CMD12 / 23 End Bit Error
49831 * 0b1..End Bit Error Generated
49832 * 0b0..No error
49833 */
49834#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) \
49835 (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & \
49836 USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
49837#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)
49838#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)
49839/*! AC12CE - Auto CMD12 / 23 CRC Error
49840 * 0b1..CRC Error Met in Auto CMD12/23 Response
49841 * 0b0..No CRC error
49842 */
49843#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) \
49844 (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
49845#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)
49846#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)
49847/*! AC12IE - Auto CMD12 / 23 Index Error
49848 * 0b1..Error, the CMD index in response is not CMD12/23
49849 * 0b0..No error
49850 */
49851#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) \
49852 (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
49853#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
49854#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
49855/*! CNIBAC12E - Command Not Issued By Auto CMD12 Error
49856 * 0b1..Not Issued
49857 * 0b0..No error
49858 */
49859#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) \
49860 (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & \
49861 USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
49862#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
49863#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
49864#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) \
49865 (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & \
49866 USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
49867#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
49868#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
49869/*! SMP_CLK_SEL - Sample Clock Select
49870 * 0b1..Tuned clock is used to sample data
49871 * 0b0..Fixed clock is used to sample data
49872 */
49873#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) \
49874 (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & \
49875 USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
49876/*! @} */
49877
49878/*! @name HOST_CTRL_CAP - Host Controller Capabilities */
49879/*! @{ */
49880#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)
49881#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)
49882#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) \
49883 (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
49884#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)
49885#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
49886#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) \
49887 (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & \
49888 USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
49889#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)
49890#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)
49891#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) \
49892 (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
49893#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK (0xF00U)
49894#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT (8U)
49895#define USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING(x) \
49896 (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_SHIFT)) & \
49897 USDHC_HOST_CTRL_CAP_TIME_COUNT_RETUNING_MASK)
49898#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
49899#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
49900/*! USE_TUNING_SDR50 - Use Tuning for SDR50
49901 * 0b1..SDR50 requires tuning
49902 * 0b0..SDR does not require tuning
49903 */
49904#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) \
49905 (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & \
49906 USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
49907#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK (0xC000U)
49908#define USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT (14U)
49909/*! RETUNING_MODE - Retuning Mode
49910 * 0b00..Mode 1
49911 * 0b01..Mode 2
49912 * 0b10..Mode 3
49913 * 0b11..Reserved
49914 */
49915#define USDHC_HOST_CTRL_CAP_RETUNING_MODE(x) \
49916 (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_RETUNING_MODE_SHIFT)) & USDHC_HOST_CTRL_CAP_RETUNING_MODE_MASK)
49917#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)
49918#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)
49919/*! MBL - Max Block Length
49920 * 0b000..512 bytes
49921 * 0b001..1024 bytes
49922 * 0b010..2048 bytes
49923 * 0b011..4096 bytes
49924 */
49925#define USDHC_HOST_CTRL_CAP_MBL(x) \
49926 (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
49927#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)
49928#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)
49929/*! ADMAS - ADMA Support
49930 * 0b1..Advanced DMA Supported
49931 * 0b0..Advanced DMA Not supported
49932 */
49933#define USDHC_HOST_CTRL_CAP_ADMAS(x) \
49934 (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
49935#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)
49936#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)
49937/*! HSS - High Speed Support
49938 * 0b1..High Speed Supported
49939 * 0b0..High Speed Not Supported
49940 */
49941#define USDHC_HOST_CTRL_CAP_HSS(x) \
49942 (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
49943#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)
49944#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)
49945/*! DMAS - DMA Support
49946 * 0b1..DMA Supported
49947 * 0b0..DMA not supported
49948 */
49949#define USDHC_HOST_CTRL_CAP_DMAS(x) \
49950 (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
49951#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)
49952#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)
49953/*! SRS - Suspend / Resume Support
49954 * 0b1..Supported
49955 * 0b0..Not supported
49956 */
49957#define USDHC_HOST_CTRL_CAP_SRS(x) \
49958 (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
49959#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)
49960#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)
49961/*! VS33 - Voltage Support 3.3V
49962 * 0b1..3.3V supported
49963 * 0b0..3.3V not supported
49964 */
49965#define USDHC_HOST_CTRL_CAP_VS33(x) \
49966 (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
49967#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)
49968#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)
49969/*! VS30 - Voltage Support 3.0 V
49970 * 0b1..3.0V supported
49971 * 0b0..3.0V not supported
49972 */
49973#define USDHC_HOST_CTRL_CAP_VS30(x) \
49974 (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
49975#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)
49976#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)
49977/*! VS18 - Voltage Support 1.8 V
49978 * 0b1..1.8V supported
49979 * 0b0..1.8V not supported
49980 */
49981#define USDHC_HOST_CTRL_CAP_VS18(x) \
49982 (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
49983/*! @} */
49984
49985/*! @name WTMK_LVL - Watermark Level */
49986/*! @{ */
49987#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)
49988#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U)
49989#define USDHC_WTMK_LVL_RD_WML(x) \
49990 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
49991#define USDHC_WTMK_LVL_RD_BRST_LEN_MASK (0x1F00U)
49992#define USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT (8U)
49993#define USDHC_WTMK_LVL_RD_BRST_LEN(x) \
49994 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_RD_BRST_LEN_MASK)
49995#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)
49996#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U)
49997#define USDHC_WTMK_LVL_WR_WML(x) \
49998 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
49999#define USDHC_WTMK_LVL_WR_BRST_LEN_MASK (0x1F000000U)
50000#define USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT (24U)
50001#define USDHC_WTMK_LVL_WR_BRST_LEN(x) \
50002 (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_BRST_LEN_SHIFT)) & USDHC_WTMK_LVL_WR_BRST_LEN_MASK)
50003/*! @} */
50004
50005/*! @name MIX_CTRL - Mixer Control */
50006/*! @{ */
50007#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U)
50008#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U)
50009/*! DMAEN - DMA Enable
50010 * 0b1..Enable
50011 * 0b0..Disable
50012 */
50013#define USDHC_MIX_CTRL_DMAEN(x) \
50014 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
50015#define USDHC_MIX_CTRL_BCEN_MASK (0x2U)
50016#define USDHC_MIX_CTRL_BCEN_SHIFT (1U)
50017/*! BCEN - Block Count Enable
50018 * 0b1..Enable
50019 * 0b0..Disable
50020 */
50021#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
50022#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U)
50023#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U)
50024/*! AC12EN - Auto CMD12 Enable
50025 * 0b1..Enable
50026 * 0b0..Disable
50027 */
50028#define USDHC_MIX_CTRL_AC12EN(x) \
50029 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
50030#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)
50031#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)
50032#define USDHC_MIX_CTRL_DDR_EN(x) \
50033 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
50034#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)
50035#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)
50036/*! DTDSEL - Data Transfer Direction Select
50037 * 0b1..Read (Card to Host)
50038 * 0b0..Write (Host to Card)
50039 */
50040#define USDHC_MIX_CTRL_DTDSEL(x) \
50041 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
50042#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)
50043#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)
50044/*! MSBSEL - Multi / Single Block Select
50045 * 0b1..Multiple Blocks
50046 * 0b0..Single Block
50047 */
50048#define USDHC_MIX_CTRL_MSBSEL(x) \
50049 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
50050#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)
50051#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)
50052#define USDHC_MIX_CTRL_NIBBLE_POS(x) \
50053 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
50054#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U)
50055#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U)
50056#define USDHC_MIX_CTRL_AC23EN(x) \
50057 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
50058#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)
50059#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)
50060/*! EXE_TUNE - Execute Tuning: (Only used for SD3.0, SDR104 mode)
50061 * 0b1..Execute Tuning
50062 * 0b0..Not Tuned or Tuning Completed
50063 */
50064#define USDHC_MIX_CTRL_EXE_TUNE(x) \
50065 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
50066#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)
50067#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)
50068/*! SMP_CLK_SEL
50069 * 0b1..Tuned clock is used to sample data / cmd
50070 * 0b0..Fixed clock is used to sample data / cmd
50071 */
50072#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) \
50073 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
50074#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)
50075#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)
50076/*! AUTO_TUNE_EN - Auto Tuning Enable (Only used for SD3.0, SDR104 mode)
50077 * 0b1..Enable auto tuning
50078 * 0b0..Disable auto tuning
50079 */
50080#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) \
50081 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
50082#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)
50083#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)
50084/*! FBCLK_SEL - Feedback Clock Source Selection (Only used for SD3.0, SDR104 mode)
50085 * 0b1..Feedback clock comes from the ipp_card_clk_out
50086 * 0b0..Feedback clock comes from the loopback CLK
50087 */
50088#define USDHC_MIX_CTRL_FBCLK_SEL(x) \
50089 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
50090#define USDHC_MIX_CTRL_HS400_MODE_MASK (0x4000000U)
50091#define USDHC_MIX_CTRL_HS400_MODE_SHIFT (26U)
50092#define USDHC_MIX_CTRL_HS400_MODE(x) \
50093 (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK)
50094/*! @} */
50095
50096/*! @name FORCE_EVENT - Force Event */
50097/*! @{ */
50098#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)
50099#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)
50100#define USDHC_FORCE_EVENT_FEVTAC12NE(x) \
50101 (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
50102#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)
50103#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)
50104#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) \
50105 (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
50106#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)
50107#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)
50108#define USDHC_FORCE_EVENT_FEVTAC12CE(x) \
50109 (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
50110#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)
50111#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)
50112#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) \
50113 (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
50114#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)
50115#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)
50116#define USDHC_FORCE_EVENT_FEVTAC12IE(x) \
50117 (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
50118#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)
50119#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)
50120#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) \
50121 (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
50122#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)
50123#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)
50124#define USDHC_FORCE_EVENT_FEVTCTOE(x) \
50125 (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
50126#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)
50127#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)
50128#define USDHC_FORCE_EVENT_FEVTCCE(x) \
50129 (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
50130#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)
50131#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)
50132#define USDHC_FORCE_EVENT_FEVTCEBE(x) \
50133 (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
50134#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)
50135#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)
50136#define USDHC_FORCE_EVENT_FEVTCIE(x) \
50137 (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
50138#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)
50139#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)
50140#define USDHC_FORCE_EVENT_FEVTDTOE(x) \
50141 (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
50142#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)
50143#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)
50144#define USDHC_FORCE_EVENT_FEVTDCE(x) \
50145 (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
50146#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)
50147#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)
50148#define USDHC_FORCE_EVENT_FEVTDEBE(x) \
50149 (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
50150#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)
50151#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)
50152#define USDHC_FORCE_EVENT_FEVTAC12E(x) \
50153 (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
50154#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)
50155#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)
50156#define USDHC_FORCE_EVENT_FEVTTNE(x) \
50157 (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
50158#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)
50159#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)
50160#define USDHC_FORCE_EVENT_FEVTDMAE(x) \
50161 (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
50162#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)
50163#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)
50164#define USDHC_FORCE_EVENT_FEVTCINT(x) \
50165 (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
50166/*! @} */
50167
50168/*! @name ADMA_ERR_STATUS - ADMA Error Status Register */
50169/*! @{ */
50170#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)
50171#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)
50172#define USDHC_ADMA_ERR_STATUS_ADMAES(x) \
50173 (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
50174#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)
50175#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)
50176/*! ADMALME - ADMA Length Mismatch Error
50177 * 0b1..Error
50178 * 0b0..No Error
50179 */
50180#define USDHC_ADMA_ERR_STATUS_ADMALME(x) \
50181 (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
50182#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)
50183#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)
50184/*! ADMADCE - ADMA Descritor Error
50185 * 0b1..Error
50186 * 0b0..No Error
50187 */
50188#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) \
50189 (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
50190/*! @} */
50191
50192/*! @name ADMA_SYS_ADDR - ADMA System Address */
50193/*! @{ */
50194#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)
50195#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)
50196#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) \
50197 (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
50198/*! @} */
50199
50200/*! @name DLL_CTRL - DLL (Delay Line) Control */
50201/*! @{ */
50202#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)
50203#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)
50204#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) \
50205 (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
50206#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)
50207#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)
50208#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) \
50209 (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
50210#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
50211#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
50212#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) \
50213 (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & \
50214 USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
50215#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
50216#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
50217#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) \
50218 (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & \
50219 USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
50220#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
50221#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
50222#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) \
50223 (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & \
50224 USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
50225#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
50226#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
50227#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) \
50228 (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & \
50229 USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
50230#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
50231#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
50232#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) \
50233 (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & \
50234 USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
50235#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
50236#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
50237#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) \
50238 (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & \
50239 USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
50240#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
50241#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
50242#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) \
50243 (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & \
50244 USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
50245#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
50246#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
50247#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) \
50248 (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & \
50249 USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
50250/*! @} */
50251
50252/*! @name DLL_STATUS - DLL Status */
50253/*! @{ */
50254#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)
50255#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)
50256#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) \
50257 (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
50258#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)
50259#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)
50260#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) \
50261 (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
50262#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)
50263#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)
50264#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) \
50265 (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
50266#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)
50267#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)
50268#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) \
50269 (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
50270/*! @} */
50271
50272/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */
50273/*! @{ */
50274#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
50275#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
50276#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) \
50277 (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & \
50278 USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
50279#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
50280#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
50281#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) \
50282 (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & \
50283 USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
50284#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
50285#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
50286#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) \
50287 (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & \
50288 USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
50289#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)
50290#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
50291#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) \
50292 (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & \
50293 USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
50294#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
50295#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
50296#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) \
50297 (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & \
50298 USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
50299#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
50300#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
50301#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) \
50302 (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & \
50303 USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
50304#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
50305#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
50306#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) \
50307 (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & \
50308 USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
50309#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)
50310#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
50311#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) \
50312 (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & \
50313 USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
50314/*! @} */
50315
50316/*! @name STROBE_DLL_CTRL - Strobe DLL Control */
50317/*! @{ */
50318#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U)
50319#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U)
50320#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) \
50321 (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & \
50322 USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK)
50323#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U)
50324#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U)
50325#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) \
50326 (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & \
50327 USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK)
50328#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
50329#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
50330#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) \
50331 (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & \
50332 USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK)
50333#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x38U)
50334#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
50335#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) \
50336 (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & \
50337 USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)
50338#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK (0x40U)
50339#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT (6U)
50340#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0(x) \
50341 (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_SHIFT)) & \
50342 USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_0_MASK)
50343#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK (0x80U)
50344#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT (7U)
50345#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1(x) \
50346 (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_SHIFT)) & \
50347 USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_1_MASK)
50348#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
50349#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
50350#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) \
50351 (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & \
50352 USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK)
50353#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
50354#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
50355#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) \
50356 (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & \
50357 USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
50358#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
50359#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
50360#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) \
50361 (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & \
50362 USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)
50363#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
50364#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
50365#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) \
50366 (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & \
50367 USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)
50368/*! @} */
50369
50370/*! @name STROBE_DLL_STATUS - Strobe DLL Status */
50371/*! @{ */
50372#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U)
50373#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U)
50374#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) \
50375 (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & \
50376 USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK)
50377#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U)
50378#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U)
50379#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) \
50380 (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & \
50381 USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK)
50382#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU)
50383#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U)
50384#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) \
50385 (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & \
50386 USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)
50387#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U)
50388#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U)
50389#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) \
50390 (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & \
50391 USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)
50392/*! @} */
50393
50394/*! @name VEND_SPEC - Vendor Specific Register */
50395/*! @{ */
50396#define USDHC_VEND_SPEC_EXT_DMA_EN_MASK (0x1U)
50397#define USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT (0U)
50398/*! EXT_DMA_EN - External DMA Request Enable
50399 * 0b0..In any scenario, uSDHC does not send out external DMA request.
50400 * 0b1..When internal DMA is not active, the external DMA request will be sent out.
50401 */
50402#define USDHC_VEND_SPEC_EXT_DMA_EN(x) \
50403 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_EXT_DMA_EN_SHIFT)) & USDHC_VEND_SPEC_EXT_DMA_EN_MASK)
50404#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U)
50405#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U)
50406/*! VSELECT - Voltage Selection
50407 * 0b1..Change the voltage to low voltage range, around 1.8 V
50408 * 0b0..Change the voltage to high voltage range, around 3.0 V
50409 */
50410#define USDHC_VEND_SPEC_VSELECT(x) \
50411 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
50412#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)
50413#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)
50414/*! CONFLICT_CHK_EN - Conflict check enable.
50415 * 0b0..Conflict check disable
50416 * 0b1..Conflict check enable
50417 */
50418#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) \
50419 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
50420#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)
50421#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
50422/*! AC12_WR_CHKBUSY_EN
50423 * 0b0..Do not check busy after auto CMD12 for write data packet
50424 * 0b1..Check busy after auto CMD12 for write data packet
50425 */
50426#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) \
50427 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & \
50428 USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
50429#define USDHC_VEND_SPEC_DAT3_CD_POL_MASK (0x10U)
50430#define USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT (4U)
50431/*! DAT3_CD_POL
50432 * 0b0..Card detected when DATA3 is high.
50433 * 0b1..Card detected when DATA3 is low.
50434 */
50435#define USDHC_VEND_SPEC_DAT3_CD_POL(x) \
50436 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_DAT3_CD_POL_SHIFT)) & USDHC_VEND_SPEC_DAT3_CD_POL_MASK)
50437#define USDHC_VEND_SPEC_CD_POL_MASK (0x20U)
50438#define USDHC_VEND_SPEC_CD_POL_SHIFT (5U)
50439/*! CD_POL
50440 * 0b0..CD_B pin is low active.
50441 * 0b1..CD_B pin is high active.
50442 */
50443#define USDHC_VEND_SPEC_CD_POL(x) \
50444 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CD_POL_SHIFT)) & USDHC_VEND_SPEC_CD_POL_MASK)
50445#define USDHC_VEND_SPEC_WP_POL_MASK (0x40U)
50446#define USDHC_VEND_SPEC_WP_POL_SHIFT (6U)
50447/*! WP_POL
50448 * 0b0..WP pin is high active.
50449 * 0b1..WP pin is low active.
50450 */
50451#define USDHC_VEND_SPEC_WP_POL(x) \
50452 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_WP_POL_SHIFT)) & USDHC_VEND_SPEC_WP_POL_MASK)
50453#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK (0x80U)
50454#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT (7U)
50455/*! CLKONJ_IN_ABORT
50456 * 0b0..The CLK output is active when sending abort command while data is transmitting even if the internal FIFO
50457 * is full (for read) or empty (for write).
50458 * 0b1..The CLK output is inactive when sending abort command while data is transmitting if the internal FIFO is
50459 * full (for read) or empty (for write).
50460 */
50461#define USDHC_VEND_SPEC_CLKONJ_IN_ABORT(x) \
50462 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CLKONJ_IN_ABORT_SHIFT)) & USDHC_VEND_SPEC_CLKONJ_IN_ABORT_MASK)
50463#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)
50464#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)
50465/*! FRC_SDCLK_ON
50466 * 0b0..CLK active or inactive is fully controlled by the hardware.
50467 * 0b1..Force CLK active.
50468 */
50469#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) \
50470 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
50471#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK (0x800U)
50472#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT (11U)
50473/*! IPG_CLK_SOFT_EN - IPG_CLK Software Enable
50474 * 0b0..Gate off the IPG_CLK
50475 * 0b1..Enable the IPG_CLK
50476 */
50477#define USDHC_VEND_SPEC_IPG_CLK_SOFT_EN(x) \
50478 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_IPG_CLK_SOFT_EN_MASK)
50479#define USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK (0x1000U)
50480#define USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT (12U)
50481/*! HCLK_SOFT_EN - AHB Clock Software Enable
50482 * 0b0..Gate off the AHB clock.
50483 * 0b1..Enable the AHB clock.
50484 */
50485#define USDHC_VEND_SPEC_HCLK_SOFT_EN(x) \
50486 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_HCLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_HCLK_SOFT_EN_MASK)
50487#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK (0x2000U)
50488#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT (13U)
50489/*! IPG_PERCLK_SOFT_EN - IPG_PERCLK Software Enable
50490 * 0b0..Gate off the IPG_PERCLK
50491 * 0b1..Enable the IPG_PERCLK
50492 */
50493#define USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN(x) \
50494 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_SHIFT)) & \
50495 USDHC_VEND_SPEC_IPG_PERCLK_SOFT_EN_MASK)
50496#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK (0x4000U)
50497#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT (14U)
50498/*! CARD_CLK_SOFT_EN - Card Clock Software Enable
50499 * 0b0..Gate off the sd_clk
50500 * 0b1..Enable the sd_clk
50501 */
50502#define USDHC_VEND_SPEC_CARD_CLK_SOFT_EN(x) \
50503 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_SHIFT)) & USDHC_VEND_SPEC_CARD_CLK_SOFT_EN_MASK)
50504#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)
50505#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)
50506/*! CRC_CHK_DIS - CRC Check Disable
50507 * 0b0..Check CRC16 for every read data packet and check CRC bits for every write data packet
50508 * 0b1..Ignore CRC16 check for every read data packet and ignore CRC bits check for every write data packet
50509 */
50510#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) \
50511 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
50512#define USDHC_VEND_SPEC_INT_ST_VAL_MASK (0xFF0000U)
50513#define USDHC_VEND_SPEC_INT_ST_VAL_SHIFT (16U)
50514#define USDHC_VEND_SPEC_INT_ST_VAL(x) \
50515 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_INT_ST_VAL_SHIFT)) & USDHC_VEND_SPEC_INT_ST_VAL_MASK)
50516#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)
50517#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)
50518/*! CMD_BYTE_EN
50519 * 0b0..Disable
50520 * 0b1..Enable
50521 */
50522#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) \
50523 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
50524/*! @} */
50525
50526/*! @name MMC_BOOT - MMC Boot Register */
50527/*! @{ */
50528#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)
50529#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)
50530/*! DTOCV_ACK
50531 * 0b0000..SDCLK x 2^13
50532 * 0b0001..SDCLK x 2^14
50533 * 0b0010..SDCLK x 2^15
50534 * 0b0011..SDCLK x 2^16
50535 * 0b0100..SDCLK x 2^17
50536 * 0b0101..SDCLK x 2^18
50537 * 0b0110..SDCLK x 2^19
50538 * 0b0111..SDCLK x 2^20
50539 * 0b1110..SDCLK x 2^27
50540 * 0b1111..SDCLK x 2^28
50541 */
50542#define USDHC_MMC_BOOT_DTOCV_ACK(x) \
50543 (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
50544#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)
50545#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)
50546/*! BOOT_ACK
50547 * 0b0..No ack
50548 * 0b1..Ack
50549 */
50550#define USDHC_MMC_BOOT_BOOT_ACK(x) \
50551 (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
50552#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)
50553#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)
50554/*! BOOT_MODE
50555 * 0b0..Normal boot
50556 * 0b1..Alternative boot
50557 */
50558#define USDHC_MMC_BOOT_BOOT_MODE(x) \
50559 (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
50560#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)
50561#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)
50562/*! BOOT_EN
50563 * 0b0..Fast boot disable
50564 * 0b1..Fast boot enable
50565 */
50566#define USDHC_MMC_BOOT_BOOT_EN(x) \
50567 (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
50568#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)
50569#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)
50570#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) \
50571 (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
50572#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)
50573#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)
50574/*! DISABLE_TIME_OUT - Disable Time Out
50575 * 0b0..Enable time out
50576 * 0b1..Disable time out
50577 */
50578#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) \
50579 (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
50580#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)
50581#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)
50582#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) \
50583 (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
50584/*! @} */
50585
50586/*! @name VEND_SPEC2 - Vendor Specific 2 Register */
50587/*! @{ */
50588#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK (0x1U)
50589#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT (0U)
50590/*! SDR104_TIMING_DIS
50591 * 0b0..The timeout counter for Ncr changes to 80, Ncrc changes to 21.
50592 * 0b1..The timeout counter for Ncr changes to 72, Ncrc changes to 15.
50593 */
50594#define USDHC_VEND_SPEC2_SDR104_TIMING_DIS(x) \
50595 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_TIMING_DIS_SHIFT)) & \
50596 USDHC_VEND_SPEC2_SDR104_TIMING_DIS_MASK)
50597#define USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK (0x2U)
50598#define USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT (1U)
50599/*! SDR104_OE_DIS
50600 * 0b0..Drive the CMD_OE / DATA_OE for one more clock cycle after the end bit.
50601 * 0b1..Stop to drive the CMD_OE / DATA_OE at once after driving the end bit.
50602 */
50603#define USDHC_VEND_SPEC2_SDR104_OE_DIS(x) \
50604 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_OE_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_OE_DIS_MASK)
50605#define USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK (0x4U)
50606#define USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT (2U)
50607/*! SDR104_NSD_DIS
50608 * 0b0..Enable the interrupt window 9 cycles later after the end of the I/O abort command (or CMD12) is sent.
50609 * 0b1..Enable the interrupt window 5 cycles later after the end of the I/O abort command (or CMD12) is sent.
50610 */
50611#define USDHC_VEND_SPEC2_SDR104_NSD_DIS(x) \
50612 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_SDR104_NSD_DIS_SHIFT)) & USDHC_VEND_SPEC2_SDR104_NSD_DIS_MASK)
50613#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)
50614#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)
50615/*! CARD_INT_D3_TEST - Card Interrupt Detection Test
50616 * 0b0..Check the card interrupt only when DATA3 is high.
50617 * 0b1..Check the card interrupt by ignoring the status of DATA3.
50618 */
50619#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) \
50620 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
50621#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)
50622#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)
50623/*! TUNING_8bit_EN
50624 * 0b0..Tuning circuit only checks the DATA[3:0].
50625 * 0b1..Tuning circuit only checks the DATA0.
50626 */
50627#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) \
50628 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
50629#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)
50630#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)
50631#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) \
50632 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
50633#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)
50634#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)
50635/*! TUNING_CMD_EN
50636 * 0b0..Auto tuning circuit does not check the CMD line.
50637 * 0b1..Auto tuning circuit checks the CMD line.
50638 */
50639#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) \
50640 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
50641#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK (0x80U)
50642#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT (7U)
50643/*! CARD_INT_AUTO_CLR_DIS
50644 * 0b0..Card interrupt status bit (CINT) can be cleared when Card Interrupt status enable bit is 0.
50645 * 0b1..Card interrupt status bit (CINT) can only be cleared by writting a 1 to CINT bit.
50646 */
50647#define USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS(x) \
50648 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_SHIFT)) & \
50649 USDHC_VEND_SPEC2_CARD_INT_AUTO_CLR_DIS_MASK)
50650#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U)
50651#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U)
50652#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) \
50653 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & \
50654 USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK)
50655#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U)
50656#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U)
50657#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) \
50658 (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & \
50659 USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK)
50660/*! @} */
50661
50662/*! @name TUNING_CTRL - Tuning Control Register */
50663/*! @{ */
50664#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0xFFU)
50665#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
50666#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) \
50667 (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & \
50668 USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
50669#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)
50670#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)
50671#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) \
50672 (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
50673#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)
50674#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)
50675#define USDHC_TUNING_CTRL_TUNING_STEP(x) \
50676 (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
50677#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)
50678#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)
50679#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) \
50680 (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
50681#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)
50682#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)
50683#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) \
50684 (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
50685/*! @} */
50686
50687/*!
50688 * @}
50689 */ /* end of group USDHC_Register_Masks */
50690
50691/* USDHC - Peripheral instance base addresses */
50692/** Peripheral uSDHC1 base address */
50693#define uSDHC1_BASE (0x30B40000u)
50694/** Peripheral uSDHC1 base pointer */
50695#define uSDHC1 ((USDHC_Type *)uSDHC1_BASE)
50696/** Peripheral uSDHC2 base address */
50697#define uSDHC2_BASE (0x30B50000u)
50698/** Peripheral uSDHC2 base pointer */
50699#define uSDHC2 ((USDHC_Type *)uSDHC2_BASE)
50700/** Peripheral uSDHC3 base address */
50701#define uSDHC3_BASE (0x30B60000u)
50702/** Peripheral uSDHC3 base pointer */
50703#define uSDHC3 ((USDHC_Type *)uSDHC3_BASE)
50704/** Array initializer of USDHC peripheral base addresses */
50705#define USDHC_BASE_ADDRS \
50706 { \
50707 0u, uSDHC1_BASE, uSDHC2_BASE, uSDHC3_BASE \
50708 }
50709/** Array initializer of USDHC peripheral base pointers */
50710#define USDHC_BASE_PTRS \
50711 { \
50712 (USDHC_Type *)0u, uSDHC1, uSDHC2, uSDHC3 \
50713 }
50714/** Interrupt vectors for the USDHC peripheral type */
50715#define USDHC_IRQS \
50716 { \
50717 NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn, USDHC3_IRQn \
50718 }
50719
50720/*!
50721 * @}
50722 */ /* end of group USDHC_Peripheral_Access_Layer */
50723
50724/* ----------------------------------------------------------------------------
50725 -- WDOG Peripheral Access Layer
50726 ---------------------------------------------------------------------------- */
50727
50728/*!
50729 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
50730 * @{
50731 */
50732
50733/** WDOG - Register Layout Typedef */
50734typedef struct
50735{
50736 __IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */
50737 __IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */
50738 __I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */
50739 __IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */
50740 __IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */
50741} WDOG_Type;
50742
50743/* ----------------------------------------------------------------------------
50744 -- WDOG Register Masks
50745 ---------------------------------------------------------------------------- */
50746
50747/*!
50748 * @addtogroup WDOG_Register_Masks WDOG Register Masks
50749 * @{
50750 */
50751
50752/*! @name WCR - Watchdog Control Register */
50753/*! @{ */
50754#define WDOG_WCR_WDZST_MASK (0x1U)
50755#define WDOG_WCR_WDZST_SHIFT (0U)
50756/*! WDZST
50757 * 0b0..Continue timer operation (Default).
50758 * 0b1..Suspend the watchdog timer.
50759 */
50760#define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)
50761#define WDOG_WCR_WDBG_MASK (0x2U)
50762#define WDOG_WCR_WDBG_SHIFT (1U)
50763/*! WDBG
50764 * 0b0..Continue WDOG timer operation (Default).
50765 * 0b1..Suspend the watchdog timer.
50766 */
50767#define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)
50768#define WDOG_WCR_WDE_MASK (0x4U)
50769#define WDOG_WCR_WDE_SHIFT (2U)
50770/*! WDE
50771 * 0b0..Disable the Watchdog (Default).
50772 * 0b1..Enable the Watchdog.
50773 */
50774#define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)
50775#define WDOG_WCR_WDT_MASK (0x8U)
50776#define WDOG_WCR_WDT_SHIFT (3U)
50777/*! WDT
50778 * 0b0..No effect on WDOG_B (Default).
50779 * 0b1..Assert WDOG_B upon a Watchdog Time-out event.
50780 */
50781#define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)
50782#define WDOG_WCR_SRS_MASK (0x10U)
50783#define WDOG_WCR_SRS_SHIFT (4U)
50784/*! SRS
50785 * 0b0..Assert system reset signal.
50786 * 0b1..No effect on the system (Default).
50787 */
50788#define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)
50789#define WDOG_WCR_WDA_MASK (0x20U)
50790#define WDOG_WCR_WDA_SHIFT (5U)
50791/*! WDA
50792 * 0b0..Assert WDOG_B output.
50793 * 0b1..No effect on system (Default).
50794 */
50795#define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)
50796#define WDOG_WCR_SRE_MASK (0x40U)
50797#define WDOG_WCR_SRE_SHIFT (6U)
50798/*! SRE - Software Reset Extension. Required to be set to 1 when used in conjunction with the Software Reset Signal
50799 * (SRS). 0b0..Reserved 0b1..This bit must be set to 1.
50800 */
50801#define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)
50802#define WDOG_WCR_WDW_MASK (0x80U)
50803#define WDOG_WCR_WDW_SHIFT (7U)
50804/*! WDW
50805 * 0b0..Continue WDOG timer operation (Default).
50806 * 0b1..Suspend WDOG timer operation.
50807 */
50808#define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)
50809#define WDOG_WCR_WT_MASK (0xFF00U)
50810#define WDOG_WCR_WT_SHIFT (8U)
50811/*! WT
50812 * 0b00000000..- 0.5 Seconds (Default).
50813 * 0b00000001..- 1.0 Seconds.
50814 * 0b00000010..- 1.5 Seconds.
50815 * 0b00000011..- 2.0 Seconds.
50816 * 0b11111111..- 128 Seconds.
50817 */
50818#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)
50819/*! @} */
50820
50821/*! @name WSR - Watchdog Service Register */
50822/*! @{ */
50823#define WDOG_WSR_WSR_MASK (0xFFFFU)
50824#define WDOG_WSR_WSR_SHIFT (0U)
50825/*! WSR
50826 * 0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR).
50827 * 0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR).
50828 */
50829#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)
50830/*! @} */
50831
50832/*! @name WRSR - Watchdog Reset Status Register */
50833/*! @{ */
50834#define WDOG_WRSR_SFTW_MASK (0x1U)
50835#define WDOG_WRSR_SFTW_SHIFT (0U)
50836/*! SFTW
50837 * 0b0..Reset is not the result of a software reset.
50838 * 0b1..Reset is the result of a software reset.
50839 */
50840#define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)
50841#define WDOG_WRSR_TOUT_MASK (0x2U)
50842#define WDOG_WRSR_TOUT_SHIFT (1U)
50843/*! TOUT
50844 * 0b0..Reset is not the result of a WDOG timeout.
50845 * 0b1..Reset is the result of a WDOG timeout.
50846 */
50847#define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)
50848#define WDOG_WRSR_POR_MASK (0x10U)
50849#define WDOG_WRSR_POR_SHIFT (4U)
50850/*! POR
50851 * 0b0..Reset is not the result of a power on reset.
50852 * 0b1..Reset is the result of a power on reset.
50853 */
50854#define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)
50855/*! @} */
50856
50857/*! @name WICR - Watchdog Interrupt Control Register */
50858/*! @{ */
50859#define WDOG_WICR_WICT_MASK (0xFFU)
50860#define WDOG_WICR_WICT_SHIFT (0U)
50861/*! WICT
50862 * 0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds.
50863 * 0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds.
50864 * 0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default).
50865 * 0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.
50866 */
50867#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)
50868#define WDOG_WICR_WTIS_MASK (0x4000U)
50869#define WDOG_WICR_WTIS_SHIFT (14U)
50870/*! WTIS
50871 * 0b0..No interrupt has occurred (Default).
50872 * 0b1..Interrupt has occurred
50873 */
50874#define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)
50875#define WDOG_WICR_WIE_MASK (0x8000U)
50876#define WDOG_WICR_WIE_SHIFT (15U)
50877/*! WIE
50878 * 0b0..Disable Interrupt (Default).
50879 * 0b1..Enable Interrupt.
50880 */
50881#define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)
50882/*! @} */
50883
50884/*! @name WMCR - Watchdog Miscellaneous Control Register */
50885/*! @{ */
50886#define WDOG_WMCR_PDE_MASK (0x1U)
50887#define WDOG_WMCR_PDE_SHIFT (0U)
50888/*! PDE
50889 * 0b0..Power Down Counter of WDOG is disabled.
50890 * 0b1..Power Down Counter of WDOG is enabled (Default).
50891 */
50892#define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)
50893/*! @} */
50894
50895/*!
50896 * @}
50897 */ /* end of group WDOG_Register_Masks */
50898
50899/* WDOG - Peripheral instance base addresses */
50900/** Peripheral WDOG1 base address */
50901#define WDOG1_BASE (0x30280000u)
50902/** Peripheral WDOG1 base pointer */
50903#define WDOG1 ((WDOG_Type *)WDOG1_BASE)
50904/** Peripheral WDOG2 base address */
50905#define WDOG2_BASE (0x30290000u)
50906/** Peripheral WDOG2 base pointer */
50907#define WDOG2 ((WDOG_Type *)WDOG2_BASE)
50908/** Peripheral WDOG3 base address */
50909#define WDOG3_BASE (0x302A0000u)
50910/** Peripheral WDOG3 base pointer */
50911#define WDOG3 ((WDOG_Type *)WDOG3_BASE)
50912/** Array initializer of WDOG peripheral base addresses */
50913#define WDOG_BASE_ADDRS \
50914 { \
50915 0u, WDOG1_BASE, WDOG2_BASE, WDOG3_BASE \
50916 }
50917/** Array initializer of WDOG peripheral base pointers */
50918#define WDOG_BASE_PTRS \
50919 { \
50920 (WDOG_Type *)0u, WDOG1, WDOG2, WDOG3 \
50921 }
50922/** Interrupt vectors for the WDOG peripheral type */
50923#define WDOG_IRQS \
50924 { \
50925 NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn, WDOG3_IRQn \
50926 }
50927
50928/*!
50929 * @}
50930 */ /* end of group WDOG_Peripheral_Access_Layer */
50931
50932/* ----------------------------------------------------------------------------
50933 -- XTALOSC Peripheral Access Layer
50934 ---------------------------------------------------------------------------- */
50935
50936/*!
50937 * @addtogroup XTALOSC_Peripheral_Access_Layer XTALOSC Peripheral Access Layer
50938 * @{
50939 */
50940
50941/** XTALOSC - Register Layout Typedef */
50942typedef struct
50943{
50944 __IO uint32_t SYS_OSCNML_CTL0; /**< OSC Normal Clock Generation Control Register0, offset: 0x0 */
50945 __IO uint32_t SYS_OSCNML_CTL1; /**< OSC Normal Clock Generation Control Register1, offset: 0x4 */
50946} XTALOSC_Type;
50947
50948/* ----------------------------------------------------------------------------
50949 -- XTALOSC Register Masks
50950 ---------------------------------------------------------------------------- */
50951
50952/*!
50953 * @addtogroup XTALOSC_Register_Masks XTALOSC Register Masks
50954 * @{
50955 */
50956
50957/*! @name SYS_OSCNML_CTL0 - OSC Normal Clock Generation Control Register0 */
50958/*! @{ */
50959#define XTALOSC_SYS_OSCNML_CTL0_SF0_MASK (0x1U)
50960#define XTALOSC_SYS_OSCNML_CTL0_SF0_SHIFT (0U)
50961#define XTALOSC_SYS_OSCNML_CTL0_SF0(x) \
50962 (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL0_SF0_SHIFT)) & XTALOSC_SYS_OSCNML_CTL0_SF0_MASK)
50963#define XTALOSC_SYS_OSCNML_CTL0_SF1_MASK (0x2U)
50964#define XTALOSC_SYS_OSCNML_CTL0_SF1_SHIFT (1U)
50965#define XTALOSC_SYS_OSCNML_CTL0_SF1(x) \
50966 (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL0_SF1_SHIFT)) & XTALOSC_SYS_OSCNML_CTL0_SF1_MASK)
50967#define XTALOSC_SYS_OSCNML_CTL0_SP_MASK (0x4U)
50968#define XTALOSC_SYS_OSCNML_CTL0_SP_SHIFT (2U)
50969#define XTALOSC_SYS_OSCNML_CTL0_SP(x) \
50970 (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL0_SP_SHIFT)) & XTALOSC_SYS_OSCNML_CTL0_SP_MASK)
50971#define XTALOSC_SYS_OSCNML_CTL0_RTO_MASK (0x10U)
50972#define XTALOSC_SYS_OSCNML_CTL0_RTO_SHIFT (4U)
50973#define XTALOSC_SYS_OSCNML_CTL0_RTO(x) \
50974 (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL0_RTO_SHIFT)) & XTALOSC_SYS_OSCNML_CTL0_RTO_MASK)
50975#define XTALOSC_SYS_OSCNML_CTL0_EN_MASK (0x80000000U)
50976#define XTALOSC_SYS_OSCNML_CTL0_EN_SHIFT (31U)
50977#define XTALOSC_SYS_OSCNML_CTL0_EN(x) \
50978 (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL0_EN_SHIFT)) & XTALOSC_SYS_OSCNML_CTL0_EN_MASK)
50979/*! @} */
50980
50981/*! @name SYS_OSCNML_CTL1 - OSC Normal Clock Generation Control Register1 */
50982/*! @{ */
50983#define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_OVERRIDE_MASK (0x2U)
50984#define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_OVERRIDE_SHIFT (1U)
50985#define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_OVERRIDE(x) \
50986 (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_OVERRIDE_SHIFT)) & \
50987 XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_OVERRIDE_MASK)
50988#define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_MASK (0x4U)
50989#define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_SHIFT (2U)
50990#define XTALOSC_SYS_OSCNML_CTL1_CLK_CKE(x) \
50991 (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_SHIFT)) & XTALOSC_SYS_OSCNML_CTL1_CLK_CKE_MASK)
50992#define XTALOSC_SYS_OSCNML_CTL1_LOCK_COUNT_MASK (0xFF0U)
50993#define XTALOSC_SYS_OSCNML_CTL1_LOCK_COUNT_SHIFT (4U)
50994#define XTALOSC_SYS_OSCNML_CTL1_LOCK_COUNT(x) \
50995 (((uint32_t)(((uint32_t)(x)) << XTALOSC_SYS_OSCNML_CTL1_LOCK_COUNT_SHIFT)) & \
50996 XTALOSC_SYS_OSCNML_CTL1_LOCK_COUNT_MASK)
50997/*! @} */
50998
50999/*!
51000 * @}
51001 */ /* end of group XTALOSC_Register_Masks */
51002
51003/* XTALOSC - Peripheral instance base addresses */
51004/** Peripheral XTALOSC base address */
51005#define XTALOSC_BASE (0x30270000u)
51006/** Peripheral XTALOSC base pointer */
51007#define XTALOSC ((XTALOSC_Type *)XTALOSC_BASE)
51008/** Array initializer of XTALOSC peripheral base addresses */
51009#define XTALOSC_BASE_ADDRS \
51010 { \
51011 XTALOSC_BASE \
51012 }
51013/** Array initializer of XTALOSC peripheral base pointers */
51014#define XTALOSC_BASE_PTRS \
51015 { \
51016 XTALOSC \
51017 }
51018
51019/*!
51020 * @}
51021 */ /* end of group XTALOSC_Peripheral_Access_Layer */
51022
51023/*
51024** End of section using anonymous unions
51025*/
51026
51027#if defined(__ARMCC_VERSION)
51028#if (__ARMCC_VERSION >= 6010050)
51029#pragma clang diagnostic pop
51030#else
51031#pragma pop
51032#endif
51033#elif defined(__GNUC__)
51034/* leave anonymous unions enabled */
51035#elif defined(__IAR_SYSTEMS_ICC__)
51036#pragma language = default
51037#else
51038#error Not supported compiler type
51039#endif
51040
51041/*!
51042 * @}
51043 */ /* end of group Peripheral_access_layer */
51044
51045/* ----------------------------------------------------------------------------
51046 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
51047 ---------------------------------------------------------------------------- */
51048
51049/*!
51050 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
51051 * @{
51052 */
51053
51054#if defined(__ARMCC_VERSION)
51055#if (__ARMCC_VERSION >= 6010050)
51056#pragma clang system_header
51057#endif
51058#elif defined(__IAR_SYSTEMS_ICC__)
51059#pragma system_include
51060#endif
51061
51062/**
51063 * @brief Mask and left-shift a bit field value for use in a register bit range.
51064 * @param field Name of the register bit field.
51065 * @param value Value of the bit field.
51066 * @return Masked and shifted value.
51067 */
51068#define NXP_VAL2FLD(field, value) (((value) << (field##_SHIFT)) & (field##_MASK))
51069/**
51070 * @brief Mask and right-shift a register value to extract a bit field value.
51071 * @param field Name of the register bit field.
51072 * @param value Value of the register.
51073 * @return Masked and shifted bit field value.
51074 */
51075#define NXP_FLD2VAL(field, value) (((value) & (field##_MASK)) >> (field##_SHIFT))
51076
51077/*!
51078 * @}
51079 */ /* end of group Bit_Field_Generic_Macros */
51080
51081/* ----------------------------------------------------------------------------
51082 -- SDK Compatibility
51083 ---------------------------------------------------------------------------- */
51084
51085/*!
51086 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
51087 * @{
51088 */
51089
51090/* No SDK compatibility issues. */
51091
51092/*!
51093 * @}
51094 */ /* end of group SDK_Compatibility_Symbols */
51095
51096#endif /* _MIMX8MN3_CM7_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 17:04:59 +0100