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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/MIMX8MN4_cm7.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/MIMX8MN4_cm7.h
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@@ -0,0 +1,51096 @@
1/*
2** ###################################################################
3** Processors: MIMX8MN4CVTIZ
4** MIMX8MN4DVTJZ
5**
6** Compilers: GNU C Compiler
7** IAR ANSI C/C++ Compiler for ARM
8** Keil ARM C/C++ Compiler
9**
10** Reference manual: MX8MNRM, Rev.A, 04/2019
11** Version: rev. 2.0, 2019-09-23
12** Build: b190830
13**
14** Abstract:
15** CMSIS Peripheral Access Layer for MIMX8MN4_cm7
16**
17** Copyright 1997-2016 Freescale Semiconductor, Inc.
18** Copyright 2016-2019 NXP
19** All rights reserved.
20**
21** SPDX-License-Identifier: BSD-3-Clause
22**
23** http: www.nxp.com
24** mail: [email protected]
25**
26** Revisions:
27** - rev. 1.0 (2019-04-22)
28** Initial version.
29** - rev. 2.0 (2019-09-23)
30** Rev.B Header RFP
31**
32** ###################################################################
33*/
34
35/*!
36 * @file MIMX8MN4_cm7.h
37 * @version 2.0
38 * @date 2019-09-23
39 * @brief CMSIS Peripheral Access Layer for MIMX8MN4_cm7
40 *
41 * CMSIS Peripheral Access Layer for MIMX8MN4_cm7
42 */
43
44#ifndef _MIMX8MN4_CM7_H_
45#define _MIMX8MN4_CM7_H_ /**< Symbol preventing repeated inclusion */
46
47/** Memory map major version (memory maps with equal major version number are
48 * compatible) */
49#define MCU_MEM_MAP_VERSION 0x0200U
50/** Memory map minor version */
51#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
52
53/* ----------------------------------------------------------------------------
54 -- Interrupt vector numbers
55 ---------------------------------------------------------------------------- */
56
57/*!
58 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
59 * @{
60 */
61
62/** Interrupt Number Definitions */
63#define NUMBER_OF_INT_VECTORS 144 /**< Number of interrupts in the Vector table */
64
65typedef enum IRQn
66{
67 /* Auxiliary constants */
68 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
69
70 /* Core interrupts */
71 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
72 HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */
73 MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */
74 BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */
75 UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */
76 SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */
77 DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */
78 PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */
79 SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */
80
81 /* Device specific interrupts */
82 GPR_IRQ_IRQn = 0, /**< GPR Interrupt. Used to notify cores on exception condition while boot. */
83 DAP_IRQn = 1, /**< DAP Interrupt */
84 SDMA1_IRQn = 2, /**< AND of all 48 SDMA1 interrupts (events) from all the channels */
85 GPU3D_IRQn = 3, /**< GPU3D Interrupt */
86 SNVS_IRQn = 4, /**< ON-OFF button press shorter than 5 seconds (pulse event) */
87 LCDIF_IRQn = 5, /**< LCDIF Interrupt */
88 SPDIF1_IRQn = 6, /**< SPDIF1 RZX/TX Interrupt */
89 Reserved23_IRQn = 7, /**< Reserved Interrupt */
90 Reserved24_IRQn = 8, /**< Reserved Interrupt */
91 QOS_IRQn = 9, /**< QOS interrupt */
92 WDOG3_IRQn = 10, /**< Watchdog Timer reset */
93 HS_CP1_IRQn = 11, /**< HS Interrupt Request */
94 APBHDMA_IRQn = 12, /**< GPMI operation channel 0-3 description complete interrupt */
95 Reserved29_IRQn = 13, /**< Reserved */
96 BCH_IRQn = 14, /**< BCH operation complete interrupt */
97 GPMI_IRQn = 15, /**< GPMI operation TIMEOUT ERROR interrupt */
98 ISI_CH0_IRQn = 16, /**< ISI Camera Channel 0 Interrupt */
99 MIPI_CSI1_IRQn = 17, /**< MIPI CSI Interrupt */
100 MIPI_DSI_IRQn = 18, /**< MIPI DSI Interrupt */
101 SNVS_Consolidated_IRQn = 19, /**< SRTC Consolidated Interrupt. Non TZ. */
102 SNVS_Security_IRQn = 20, /**< SRTC Security Interrupt. TZ. */
103 CSU_IRQn =
104 21, /**< CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted. */
105 USDHC1_IRQn = 22, /**< uSDHC1 Enhanced SDHC Interrupt Request */
106 USDHC2_IRQn = 23, /**< uSDHC2 Enhanced SDHC Interrupt Request */
107 USDHC3_IRQn = 24, /**< uSDHC3 Enhanced SDHC Interrupt Request */
108 Reserved41_IRQn = 25, /**< Reserved Interrupt */
109 UART1_IRQn = 26, /**< UART-1 ORed interrupt */
110 UART2_IRQn = 27, /**< UART-2 ORed interrupt */
111 UART3_IRQn = 28, /**< UART-3 ORed interrupt */
112 UART4_IRQn = 29, /**< UART-4 ORed interrupt */
113 Reserved46_IRQn = 30, /**< Reserved Interrupt */
114 ECSPI1_IRQn = 31, /**< ECSPI1 interrupt request line to the core. */
115 ECSPI2_IRQn = 32, /**< ECSPI2 interrupt request line to the core. */
116 ECSPI3_IRQn = 33, /**< ECSPI3 interrupt request line to the core. */
117 SDMA3_IRQn = 34, /**< AND of all 48 SDMA3 interrupts (events) from all the channels */
118 I2C1_IRQn = 35, /**< I2C-1 Interrupt */
119 I2C2_IRQn = 36, /**< I2C-2 Interrupt */
120 I2C3_IRQn = 37, /**< I2C-3 Interrupt */
121 I2C4_IRQn = 38, /**< I2C-4 Interrupt */
122 RDC_IRQn = 39, /**< RDC interrupt */
123 USB1_IRQn = 40, /**< USB1 Interrupt */
124 Reserved57_IRQn = 41, /**< Reserved Interrupt */
125 ISI_CH1_IRQn = 42, /**< ISI Camera Channel 1 Interrupt */
126 ISI_CH2_IRQn = 43, /**< ISI Camera Channel 2 Interrupt */
127 PDM_HWVAD_EVENT_IRQn = 44, /**< Digital Microphone interface voice activity detector event interrupt */
128 PDM_HWVAD_ERROR_IRQn = 45, /**< Digital Microphone interface voice activity detector error interrupt */
129 GPT6_IRQn = 46, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3
130 Interrupt lines */
131 SCTR_IRQ0_IRQn = 47, /**< System Counter Interrupt 0 */
132 SCTR_IRQ1_IRQn = 48, /**< System Counter Interrupt 1 */
133 TEMPMON_LOW_IRQn = 49, /**< TempSensor (Temperature low alarm). */
134 I2S3_IRQn = 50, /**< SAI3 Receive / Transmit Interrupt */
135 GPT5_IRQn = 51, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3
136 Interrupt lines */
137 GPT4_IRQn = 52, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3
138 Interrupt lines */
139 GPT3_IRQn = 53, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3
140 Interrupt lines */
141 GPT2_IRQn = 54, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3
142 Interrupt lines */
143 GPT1_IRQn = 55, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3
144 Interrupt lines */
145 GPIO1_INT7_IRQn = 56, /**< Active HIGH Interrupt from INT7 from GPIO */
146 GPIO1_INT6_IRQn = 57, /**< Active HIGH Interrupt from INT6 from GPIO */
147 GPIO1_INT5_IRQn = 58, /**< Active HIGH Interrupt from INT5 from GPIO */
148 GPIO1_INT4_IRQn = 59, /**< Active HIGH Interrupt from INT4 from GPIO */
149 GPIO1_INT3_IRQn = 60, /**< Active HIGH Interrupt from INT3 from GPIO */
150 GPIO1_INT2_IRQn = 61, /**< Active HIGH Interrupt from INT2 from GPIO */
151 GPIO1_INT1_IRQn = 62, /**< Active HIGH Interrupt from INT1 from GPIO */
152 GPIO1_INT0_IRQn = 63, /**< Active HIGH Interrupt from INT0 from GPIO */
153 GPIO1_Combined_0_15_IRQn = 64, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
154 GPIO1_Combined_16_31_IRQn = 65, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
155 GPIO2_Combined_0_15_IRQn = 66, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
156 GPIO2_Combined_16_31_IRQn = 67, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */
157 GPIO3_Combined_0_15_IRQn = 68, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */
158 GPIO3_Combined_16_31_IRQn = 69, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */
159 GPIO4_Combined_0_15_IRQn = 70, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */
160 GPIO4_Combined_16_31_IRQn = 71, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */
161 GPIO5_Combined_0_15_IRQn = 72, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
162 GPIO5_Combined_16_31_IRQn = 73, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */
163 Reserved90_IRQn = 74, /**< Reserved interrupt */
164 Reserved91_IRQn = 75, /**< Reserved interrupt */
165 Reserved92_IRQn = 76, /**< Reserved interrupt */
166 Reserved93_IRQn = 77, /**< Reserved interrupt */
167 WDOG1_IRQn = 78, /**< Watchdog Timer reset */
168 WDOG2_IRQn = 79, /**< Watchdog Timer reset */
169 Reserved96_IRQn = 80, /**< Reserved interrupt */
170 PWM1_IRQn = 81, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO
171 Waterlevel crossing interrupt line. */
172 PWM2_IRQn = 82, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO
173 Waterlevel crossing interrupt line. */
174 PWM3_IRQn = 83, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO
175 Waterlevel crossing interrupt line. */
176 PWM4_IRQn = 84, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO
177 Waterlevel crossing interrupt line. */
178 CCM_IRQ1_IRQn = 85, /**< CCM Interrupt Request 1 */
179 CCM_IRQ2_IRQn = 86, /**< CCM Interrupt Request 2 */
180 GPC_IRQn = 87, /**< GPC Interrupt Request 1 */
181 MU_A53_IRQn = 88, /**< Interrupt to A53 */
182 SRC_IRQn = 89, /**< SRC interrupt request */
183 I2S56_IRQn = 90, /**< SAI5/6 Receive / Transmit Interrupt */
184 RTIC_IRQn = 91, /**< RTIC Interrupt */
185 CPU_PerformanceUnit_IRQn = 92, /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[n] */
186 CPU_CTI_Trigger_IRQn = 93, /**< CTI trigger outputs (internal: nCTIIRQ[n] */
187 SRC_Combined_IRQn = 94, /**< Combined CPU wdog interrupts (4x) out of SRC. */
188 Reserved111_IRQn = 95, /**< Reserved Interrupt */
189 I2S2_IRQn = 96, /**< SAI2 Receive / Transmit Interrupt */
190 MU_M7_IRQn = 97, /**< Interrupt to M7 */
191 DDR_PerformanceMonitor_IRQn = 98, /**< ddr Interrupt for performance monitor */
192 DDR_IRQn = 99, /**< ddr Interrupt */
193 Reserved116_IRQn = 100, /**< Reserved interrupt */
194 CPU_Error_AXI_IRQn = 101, /**< CPU Error indicator for AXI transaction with a write response error condition */
195 CPU_Error_L2RAM_IRQn = 102, /**< CPU Error indicator for L2 RAM double-bit ECC error */
196 SDMA2_IRQn = 103, /**< AND of all 48 SDMA2 interrupts (events) from all the channels */
197 SJC_IRQn = 104, /**< Interrupt triggered by SJC register */
198 CAAM_IRQ0_IRQn = 105, /**< CAAM interrupt queue for JQ */
199 CAAM_IRQ1_IRQn = 106, /**< CAAM interrupt queue for JQ */
200 QSPI_IRQn = 107, /**< QSPI Interrupt */
201 TZASC_IRQn = 108, /**< TZASC (PL380) interrupt */
202 PDM_EVENT_IRQn = 109, /**< Digital Microphone interface interrupt */
203 PDM_ERROR_IRQn = 110, /**< Digital Microphone interface error interrupt */
204 I2S7_IRQn = 111, /**< SAI7 Receive / Transmit Interrupt */
205 PERFMON1_IRQn = 112, /**< General Interrupt */
206 PERFMON2_IRQn = 113, /**< General Interrupt */
207 CAAM_IRQ2_IRQn = 114, /**< CAAM interrupt queue for JQ */
208 CAAM_ERROR_IRQn = 115, /**< Recoverable error interrupt */
209 HS_CP0_IRQn = 116, /**< HS Interrupt Request */
210 CM7_CTI_IRQn = 117, /**< CTI trigger outputs from CM7 platform */
211 ENET_MAC0_Rx_Tx_Done1_IRQn = 118, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */
212 ENET_MAC0_Rx_Tx_Done2_IRQn = 119, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */
213 ENET_IRQn = 120, /**< MAC 0 IRQ */
214 ENET_1588_IRQn = 121, /**< MAC 0 1588 Timer Interrupt - synchronous */
215 ASRC_IRQn = 122, /**< ASRC Interrupt */
216 Reserved139_IRQn = 123, /**< Reserved Interrupt */
217 Reserved140_IRQn = 124, /**< Reserved Interrupt */
218 Reserved141_IRQn = 125, /**< Reserved Interrupt */
219 ISI_CH3_IRQn = 126, /**< ISI Camera Channel 3 Interrupt */
220 Reserved143_IRQn = 127 /**< Reserved Interrupt */
221} IRQn_Type;
222
223/*!
224 * @}
225 */ /* end of group Interrupt_vector_numbers */
226
227/* ----------------------------------------------------------------------------
228 -- Cortex M7 Core Configuration
229 ---------------------------------------------------------------------------- */
230
231/*!
232 * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration
233 * @{
234 */
235
236#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
237#define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */
238#define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */
239#define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */
240#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
241#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
242#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
243
244#include "core_cm7.h" /* Core Peripheral Access Layer */
245#include "system_MIMX8MN4_cm7.h" /* Device specific configuration file */
246
247/*!
248 * @}
249 */ /* end of group Cortex_Core_Configuration */
250
251/* ----------------------------------------------------------------------------
252 -- Mapping Information
253 ---------------------------------------------------------------------------- */
254
255/*!
256 * @addtogroup Mapping_Information Mapping Information
257 * @{
258 */
259
260/** Mapping Information */
261/*!
262 * @addtogroup iomuxc_pads
263 * @{ */
264
265/*******************************************************************************
266 * Definitions
267 *******************************************************************************/
268
269/*!
270 * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
271 *
272 * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
273 */
274typedef enum _iomuxc_sw_mux_ctl_pad
275{
276 kIOMUXC_SW_MUX_CTL_PAD_BOOT_MODE2 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
277 kIOMUXC_SW_MUX_CTL_PAD_BOOT_MODE3 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
278 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
279 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
280 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
281 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
282 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */
283 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */
284 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */
285 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */
286 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */
287 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */
288 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
289 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
290 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
291 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
292 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */
293 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */
294 kIOMUXC_SW_MUX_CTL_PAD_ENET_MDC = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */
295 kIOMUXC_SW_MUX_CTL_PAD_ENET_MDIO = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */
296 kIOMUXC_SW_MUX_CTL_PAD_ENET_TD3 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */
297 kIOMUXC_SW_MUX_CTL_PAD_ENET_TD2 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */
298 kIOMUXC_SW_MUX_CTL_PAD_ENET_TD1 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */
299 kIOMUXC_SW_MUX_CTL_PAD_ENET_TD0 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */
300 kIOMUXC_SW_MUX_CTL_PAD_ENET_TX_CTL = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */
301 kIOMUXC_SW_MUX_CTL_PAD_ENET_TXC = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */
302 kIOMUXC_SW_MUX_CTL_PAD_ENET_RX_CTL = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */
303 kIOMUXC_SW_MUX_CTL_PAD_ENET_RXC = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */
304 kIOMUXC_SW_MUX_CTL_PAD_ENET_RD0 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */
305 kIOMUXC_SW_MUX_CTL_PAD_ENET_RD1 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */
306 kIOMUXC_SW_MUX_CTL_PAD_ENET_RD2 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */
307 kIOMUXC_SW_MUX_CTL_PAD_ENET_RD3 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */
308 kIOMUXC_SW_MUX_CTL_PAD_SD1_CLK = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */
309 kIOMUXC_SW_MUX_CTL_PAD_SD1_CMD = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */
310 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */
311 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */
312 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */
313 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */
314 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA4 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */
315 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA5 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */
316 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA6 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */
317 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA7 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */
318 kIOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */
319 kIOMUXC_SW_MUX_CTL_PAD_SD1_STROBE = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */
320 kIOMUXC_SW_MUX_CTL_PAD_SD2_CD_B = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */
321 kIOMUXC_SW_MUX_CTL_PAD_SD2_CLK = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */
322 kIOMUXC_SW_MUX_CTL_PAD_SD2_CMD = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */
323 kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */
324 kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */
325 kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */
326 kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */
327 kIOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */
328 kIOMUXC_SW_MUX_CTL_PAD_SD2_WP = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */
329 kIOMUXC_SW_MUX_CTL_PAD_NAND_ALE = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */
330 kIOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */
331 kIOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */
332 kIOMUXC_SW_MUX_CTL_PAD_NAND_CE2_B = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */
333 kIOMUXC_SW_MUX_CTL_PAD_NAND_CE3_B = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */
334 kIOMUXC_SW_MUX_CTL_PAD_NAND_CLE = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */
335 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */
336 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */
337 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */
338 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */
339 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */
340 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */
341 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */
342 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */
343 kIOMUXC_SW_MUX_CTL_PAD_NAND_DQS = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */
344 kIOMUXC_SW_MUX_CTL_PAD_NAND_RE_B = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */
345 kIOMUXC_SW_MUX_CTL_PAD_NAND_READY_B = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */
346 kIOMUXC_SW_MUX_CTL_PAD_NAND_WE_B = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */
347 kIOMUXC_SW_MUX_CTL_PAD_NAND_WP_B = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */
348 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */
349 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXC = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */
350 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD0 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */
351 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD1 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */
352 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD2 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */
353 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD3 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */
354 kIOMUXC_SW_MUX_CTL_PAD_SAI5_MCLK = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */
355 kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */
356 kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXC = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */
357 kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXD0 = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */
358 kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXFS = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */
359 kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXC = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */
360 kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXD0 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */
361 kIOMUXC_SW_MUX_CTL_PAD_SAI2_MCLK = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */
362 kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXFS = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */
363 kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXC = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */
364 kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXD = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */
365 kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */
366 kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXC = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */
367 kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXD = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */
368 kIOMUXC_SW_MUX_CTL_PAD_SAI3_MCLK = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */
369 kIOMUXC_SW_MUX_CTL_PAD_SPDIF_TX = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */
370 kIOMUXC_SW_MUX_CTL_PAD_SPDIF_RX = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */
371 kIOMUXC_SW_MUX_CTL_PAD_SPDIF_EXT_CLK = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */
372 kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */
373 kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */
374 kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */
375 kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */
376 kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */
377 kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */
378 kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */
379 kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 = 124U, /**< IOMUXC SW_MUX_CTL_PAD index */
380 kIOMUXC_SW_MUX_CTL_PAD_I2C1_SCL = 125U, /**< IOMUXC SW_MUX_CTL_PAD index */
381 kIOMUXC_SW_MUX_CTL_PAD_I2C1_SDA = 126U, /**< IOMUXC SW_MUX_CTL_PAD index */
382 kIOMUXC_SW_MUX_CTL_PAD_I2C2_SCL = 127U, /**< IOMUXC SW_MUX_CTL_PAD index */
383 kIOMUXC_SW_MUX_CTL_PAD_I2C2_SDA = 128U, /**< IOMUXC SW_MUX_CTL_PAD index */
384 kIOMUXC_SW_MUX_CTL_PAD_I2C3_SCL = 129U, /**< IOMUXC SW_MUX_CTL_PAD index */
385 kIOMUXC_SW_MUX_CTL_PAD_I2C3_SDA = 130U, /**< IOMUXC SW_MUX_CTL_PAD index */
386 kIOMUXC_SW_MUX_CTL_PAD_I2C4_SCL = 131U, /**< IOMUXC SW_MUX_CTL_PAD index */
387 kIOMUXC_SW_MUX_CTL_PAD_I2C4_SDA = 132U, /**< IOMUXC SW_MUX_CTL_PAD index */
388 kIOMUXC_SW_MUX_CTL_PAD_UART1_RXD = 133U, /**< IOMUXC SW_MUX_CTL_PAD index */
389 kIOMUXC_SW_MUX_CTL_PAD_UART1_TXD = 134U, /**< IOMUXC SW_MUX_CTL_PAD index */
390 kIOMUXC_SW_MUX_CTL_PAD_UART2_RXD = 135U, /**< IOMUXC SW_MUX_CTL_PAD index */
391 kIOMUXC_SW_MUX_CTL_PAD_UART2_TXD = 136U, /**< IOMUXC SW_MUX_CTL_PAD index */
392 kIOMUXC_SW_MUX_CTL_PAD_UART3_RXD = 137U, /**< IOMUXC SW_MUX_CTL_PAD index */
393 kIOMUXC_SW_MUX_CTL_PAD_UART3_TXD = 138U, /**< IOMUXC SW_MUX_CTL_PAD index */
394 kIOMUXC_SW_MUX_CTL_PAD_UART4_RXD = 139U, /**< IOMUXC SW_MUX_CTL_PAD index */
395 kIOMUXC_SW_MUX_CTL_PAD_UART4_TXD = 140U, /**< IOMUXC SW_MUX_CTL_PAD index */
396} iomuxc_sw_mux_ctl_pad_t;
397
398/*!
399 * @addtogroup iomuxc_pads
400 * @{ */
401
402/*******************************************************************************
403 * Definitions
404 *******************************************************************************/
405
406/*!
407 * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
408 *
409 * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
410 */
411typedef enum _iomuxc_sw_pad_ctl_pad
412{
413 kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */
414 kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */
415 kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE2 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */
416 kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE3 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */
417 kIOMUXC_SW_PAD_CTL_PAD_JTAG_MOD = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */
418 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDI = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */
419 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TMS = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */
420 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TCK = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */
421 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDO = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */
422 kIOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */
423 kIOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */
424 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */
425 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */
426 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */
427 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */
428 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */
429 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */
430 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */
431 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */
432 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */
433 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */
434 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */
435 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */
436 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */
437 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */
438 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */
439 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */
440 kIOMUXC_SW_PAD_CTL_PAD_ENET_MDC = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */
441 kIOMUXC_SW_PAD_CTL_PAD_ENET_MDIO = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */
442 kIOMUXC_SW_PAD_CTL_PAD_ENET_TD3 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */
443 kIOMUXC_SW_PAD_CTL_PAD_ENET_TD2 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */
444 kIOMUXC_SW_PAD_CTL_PAD_ENET_TD1 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */
445 kIOMUXC_SW_PAD_CTL_PAD_ENET_TD0 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */
446 kIOMUXC_SW_PAD_CTL_PAD_ENET_TX_CTL = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */
447 kIOMUXC_SW_PAD_CTL_PAD_ENET_TXC = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */
448 kIOMUXC_SW_PAD_CTL_PAD_ENET_RX_CTL = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */
449 kIOMUXC_SW_PAD_CTL_PAD_ENET_RXC = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */
450 kIOMUXC_SW_PAD_CTL_PAD_ENET_RD0 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */
451 kIOMUXC_SW_PAD_CTL_PAD_ENET_RD1 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */
452 kIOMUXC_SW_PAD_CTL_PAD_ENET_RD2 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */
453 kIOMUXC_SW_PAD_CTL_PAD_ENET_RD3 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */
454 kIOMUXC_SW_PAD_CTL_PAD_SD1_CLK = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */
455 kIOMUXC_SW_PAD_CTL_PAD_SD1_CMD = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */
456 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */
457 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */
458 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */
459 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */
460 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA4 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */
461 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA5 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */
462 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA6 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */
463 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA7 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */
464 kIOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */
465 kIOMUXC_SW_PAD_CTL_PAD_SD1_STROBE = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */
466 kIOMUXC_SW_PAD_CTL_PAD_SD2_CD_B = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */
467 kIOMUXC_SW_PAD_CTL_PAD_SD2_CLK = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */
468 kIOMUXC_SW_PAD_CTL_PAD_SD2_CMD = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */
469 kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */
470 kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */
471 kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */
472 kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */
473 kIOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */
474 kIOMUXC_SW_PAD_CTL_PAD_SD2_WP = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */
475 kIOMUXC_SW_PAD_CTL_PAD_NAND_ALE = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */
476 kIOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */
477 kIOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */
478 kIOMUXC_SW_PAD_CTL_PAD_NAND_CE2_B = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */
479 kIOMUXC_SW_PAD_CTL_PAD_NAND_CE3_B = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */
480 kIOMUXC_SW_PAD_CTL_PAD_NAND_CLE = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */
481 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */
482 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */
483 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */
484 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */
485 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */
486 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */
487 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */
488 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */
489 kIOMUXC_SW_PAD_CTL_PAD_NAND_DQS = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */
490 kIOMUXC_SW_PAD_CTL_PAD_NAND_RE_B = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */
491 kIOMUXC_SW_PAD_CTL_PAD_NAND_READY_B = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */
492 kIOMUXC_SW_PAD_CTL_PAD_NAND_WE_B = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */
493 kIOMUXC_SW_PAD_CTL_PAD_NAND_WP_B = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */
494 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXFS = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */
495 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXC = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */
496 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD0 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */
497 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD1 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */
498 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD2 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */
499 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD3 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */
500 kIOMUXC_SW_PAD_CTL_PAD_SAI5_MCLK = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */
501 kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXFS = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */
502 kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXC = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */
503 kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXD0 = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */
504 kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXFS = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */
505 kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXC = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */
506 kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXD0 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */
507 kIOMUXC_SW_PAD_CTL_PAD_SAI2_MCLK = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */
508 kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXFS = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */
509 kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXC = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */
510 kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXD = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */
511 kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXFS = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */
512 kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXC = 124U, /**< IOMUXC SW_PAD_CTL_PAD index */
513 kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXD = 125U, /**< IOMUXC SW_PAD_CTL_PAD index */
514 kIOMUXC_SW_PAD_CTL_PAD_SAI3_MCLK = 126U, /**< IOMUXC SW_PAD_CTL_PAD index */
515 kIOMUXC_SW_PAD_CTL_PAD_SPDIF_TX = 127U, /**< IOMUXC SW_PAD_CTL_PAD index */
516 kIOMUXC_SW_PAD_CTL_PAD_SPDIF_RX = 128U, /**< IOMUXC SW_PAD_CTL_PAD index */
517 kIOMUXC_SW_PAD_CTL_PAD_SPDIF_EXT_CLK = 129U, /**< IOMUXC SW_PAD_CTL_PAD index */
518 kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK = 130U, /**< IOMUXC SW_PAD_CTL_PAD index */
519 kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI = 131U, /**< IOMUXC SW_PAD_CTL_PAD index */
520 kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO = 132U, /**< IOMUXC SW_PAD_CTL_PAD index */
521 kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0 = 133U, /**< IOMUXC SW_PAD_CTL_PAD index */
522 kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK = 134U, /**< IOMUXC SW_PAD_CTL_PAD index */
523 kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI = 135U, /**< IOMUXC SW_PAD_CTL_PAD index */
524 kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO = 136U, /**< IOMUXC SW_PAD_CTL_PAD index */
525 kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0 = 137U, /**< IOMUXC SW_PAD_CTL_PAD index */
526 kIOMUXC_SW_PAD_CTL_PAD_I2C1_SCL = 138U, /**< IOMUXC SW_PAD_CTL_PAD index */
527 kIOMUXC_SW_PAD_CTL_PAD_I2C1_SDA = 139U, /**< IOMUXC SW_PAD_CTL_PAD index */
528 kIOMUXC_SW_PAD_CTL_PAD_I2C2_SCL = 140U, /**< IOMUXC SW_PAD_CTL_PAD index */
529 kIOMUXC_SW_PAD_CTL_PAD_I2C2_SDA = 141U, /**< IOMUXC SW_PAD_CTL_PAD index */
530 kIOMUXC_SW_PAD_CTL_PAD_I2C3_SCL = 142U, /**< IOMUXC SW_PAD_CTL_PAD index */
531 kIOMUXC_SW_PAD_CTL_PAD_I2C3_SDA = 143U, /**< IOMUXC SW_PAD_CTL_PAD index */
532 kIOMUXC_SW_PAD_CTL_PAD_I2C4_SCL = 144U, /**< IOMUXC SW_PAD_CTL_PAD index */
533 kIOMUXC_SW_PAD_CTL_PAD_I2C4_SDA = 145U, /**< IOMUXC SW_PAD_CTL_PAD index */
534 kIOMUXC_SW_PAD_CTL_PAD_UART1_RXD = 146U, /**< IOMUXC SW_PAD_CTL_PAD index */
535 kIOMUXC_SW_PAD_CTL_PAD_UART1_TXD = 147U, /**< IOMUXC SW_PAD_CTL_PAD index */
536 kIOMUXC_SW_PAD_CTL_PAD_UART2_RXD = 148U, /**< IOMUXC SW_PAD_CTL_PAD index */
537 kIOMUXC_SW_PAD_CTL_PAD_UART2_TXD = 149U, /**< IOMUXC SW_PAD_CTL_PAD index */
538 kIOMUXC_SW_PAD_CTL_PAD_UART3_RXD = 150U, /**< IOMUXC SW_PAD_CTL_PAD index */
539 kIOMUXC_SW_PAD_CTL_PAD_UART3_TXD = 151U, /**< IOMUXC SW_PAD_CTL_PAD index */
540 kIOMUXC_SW_PAD_CTL_PAD_UART4_RXD = 152U, /**< IOMUXC SW_PAD_CTL_PAD index */
541 kIOMUXC_SW_PAD_CTL_PAD_UART4_TXD = 153U, /**< IOMUXC SW_PAD_CTL_PAD index */
542} iomuxc_sw_pad_ctl_pad_t;
543
544/* @} */
545
546/*!
547 * @brief Enumeration for the IOMUXC select input
548 *
549 * Defines the enumeration for the IOMUXC select input collections.
550 */
551typedef enum _iomuxc_select_input
552{
553 kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 0U, /**< IOMUXC select input index */
554 kIOMUXC_ENET1_MDIO_SELECT_INPUT = 1U, /**< IOMUXC select input index */
555 kIOMUXC_SAI5_RX_BCLK_SELECT_INPUT = 5U, /**< IOMUXC select input index */
556 kIOMUXC_SAI5_RX_DATA0_SELECT_INPUT = 6U, /**< IOMUXC select input index */
557 kIOMUXC_SAI5_RX_DATA1_SELECT_INPUT = 7U, /**< IOMUXC select input index */
558 kIOMUXC_SAI5_RX_DATA2_SELECT_INPUT = 8U, /**< IOMUXC select input index */
559 kIOMUXC_SAI5_RX_DATA3_SELECT_INPUT = 9U, /**< IOMUXC select input index */
560 kIOMUXC_SAI5_RX_SYNC_SELECT_INPUT = 10U, /**< IOMUXC select input index */
561 kIOMUXC_SAI5_TX_BCLK_SELECT_INPUT = 11U, /**< IOMUXC select input index */
562 kIOMUXC_SAI5_TX_SYNC_SELECT_INPUT = 12U, /**< IOMUXC select input index */
563 kIOMUXC_UART1_RTS_B_SELECT_INPUT = 13U, /**< IOMUXC select input index */
564 kIOMUXC_UART1_RX_SELECT_INPUT = 14U, /**< IOMUXC select input index */
565 kIOMUXC_UART2_RTS_B_SELECT_INPUT = 15U, /**< IOMUXC select input index */
566 kIOMUXC_UART2_RX_SELECT_INPUT = 16U, /**< IOMUXC select input index */
567 kIOMUXC_UART3_RTS_B_SELECT_INPUT = 17U, /**< IOMUXC select input index */
568 kIOMUXC_UART3_RX_SELECT_INPUT = 18U, /**< IOMUXC select input index */
569 kIOMUXC_UART4_RTS_B_SELECT_INPUT = 19U, /**< IOMUXC select input index */
570 kIOMUXC_UART4_RX_SELECT_INPUT = 20U, /**< IOMUXC select input index */
571 kIOMUXC_PDM_BIT_STREAM0_SELECT_INPUT = 30U, /**< IOMUXC select input index */
572 kIOMUXC_PDM_BIT_STREAM1_SELECT_INPUT = 31U, /**< IOMUXC select input index */
573 kIOMUXC_PDM_BIT_STREAM2_SELECT_INPUT = 32U, /**< IOMUXC select input index */
574 kIOMUXC_PDM_BIT_STREAM3_SELECT_INPUT = 33U, /**< IOMUXC select input index */
575 kIOMUXC_USDHC3_DATA7_SELECT_INPUT = 36U, /**< IOMUXC select input index */
576 kIOMUXC_USDHC3_DATA5_SELECT_INPUT = 37U, /**< IOMUXC select input index */
577 kIOMUXC_ENET1_RGMII_RD1_SELECT_INPUT = 38U, /**< IOMUXC select input index */
578 kIOMUXC_USDHC3_DATA4_SELECT_INPUT = 39U, /**< IOMUXC select input index */
579 kIOMUXC_I2C1_SCL_SELECT_INPUT = 40U, /**< IOMUXC select input index */
580 kIOMUXC_I2C2_SDA_SELECT_INPUT = 41U, /**< IOMUXC select input index */
581 kIOMUXC_ECSPI1_SS0_SELECT_INPUT = 42U, /**< IOMUXC select input index */
582 kIOMUXC_SPDIF1_EXT_CLK_SELECT_INPUT = 43U, /**< IOMUXC select input index */
583 kIOMUXC_I2C1_SDA_SELECT_INPUT = 44U, /**< IOMUXC select input index */
584 kIOMUXC_ECSPI2_SS0_SELECT_INPUT = 45U, /**< IOMUXC select input index */
585 kIOMUXC_ENET1_RGMII_RX_CTL_SELECT_INPUT = 46U, /**< IOMUXC select input index */
586 kIOMUXC_ECSPI2_MISO_SELECT_INPUT = 47U, /**< IOMUXC select input index */
587 kIOMUXC_ENET1_RGMII_RD0_SELECT_INPUT = 48U, /**< IOMUXC select input index */
588 kIOMUXC_ECSPI2_SCLK_SELECT_INPUT = 49U, /**< IOMUXC select input index */
589 kIOMUXC_USDHC3_DATA6_SELECT_INPUT = 50U, /**< IOMUXC select input index */
590 kIOMUXC_I2C3_SCL_SELECT_INPUT = 51U, /**< IOMUXC select input index */
591 kIOMUXC_I2C4_SDA_SELECT_INPUT = 52U, /**< IOMUXC select input index */
592 kIOMUXC_ECSPI2_MOSI_SELECT_INPUT = 53U, /**< IOMUXC select input index */
593 kIOMUXC_SAI5_MCLK_SELECT_INPUT = 54U, /**< IOMUXC select input index */
594 kIOMUXC_USDHC3_CD_B_SELECT_INPUT = 55U, /**< IOMUXC select input index */
595 kIOMUXC_USDHC3_STROBE_SELECT_INPUT = 56U, /**< IOMUXC select input index */
596 kIOMUXC_USDHC3_CLK_SELECT_INPUT = 57U, /**< IOMUXC select input index */
597 kIOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT = 58U, /**< IOMUXC select input index */
598 kIOMUXC_ECSPI1_MOSI_SELECT_INPUT = 59U, /**< IOMUXC select input index */
599 kIOMUXC_SAI2_RX_DATA1_SELECT_INPUT = 60U, /**< IOMUXC select input index */
600 kIOMUXC_USDHC3_DATA1_SELECT_INPUT = 61U, /**< IOMUXC select input index */
601 kIOMUXC_USDHC3_DATA0_SELECT_INPUT = 62U, /**< IOMUXC select input index */
602 kIOMUXC_USDHC3_WP_SELECT_INPUT = 63U, /**< IOMUXC select input index */
603 kIOMUXC_I2C3_SDA_SELECT_INPUT = 64U, /**< IOMUXC select input index */
604 kIOMUXC_SAI3_MCLK_SELECT_INPUT = 65U, /**< IOMUXC select input index */
605 kIOMUXC_ECSPI1_MISO_SELECT_INPUT = 66U, /**< IOMUXC select input index */
606 kIOMUXC_ENET1_RX_ER_SELECT_INPUT = 67U, /**< IOMUXC select input index */
607 kIOMUXC_SPDIF1_IN_SELECT_INPUT = 68U, /**< IOMUXC select input index */
608 kIOMUXC_I2C2_SCL_SELECT_INPUT = 69U, /**< IOMUXC select input index */
609 kIOMUXC_I2C4_SCL_SELECT_INPUT = 70U, /**< IOMUXC select input index */
610 kIOMUXC_ECSPI1_SCLK_SELECT_INPUT = 71U, /**< IOMUXC select input index */
611 kIOMUXC_USDHC3_CMD_SELECT_INPUT = 72U, /**< IOMUXC select input index */
612 kIOMUXC_USDHC3_DATA3_SELECT_INPUT = 73U, /**< IOMUXC select input index */
613 kIOMUXC_USDHC3_DATA2_SELECT_INPUT = 74U, /**< IOMUXC select input index */
614 kIOMUXC_GPT1_CLK_SELECT_INPUT = 75U, /**< IOMUXC select input index */
615 kIOMUXC_GPT1_CAPTURE2_SELECT_INPUT = 76U, /**< IOMUXC select input index */
616 kIOMUXC_GPT1_CAPTURE1_SELECT_INPUT = 77U, /**< IOMUXC select input index */
617} iomuxc_select_input_t;
618
619/*!
620 * @addtogroup rdc_mapping
621 * @{
622 */
623
624/*******************************************************************************
625 * Definitions
626 ******************************************************************************/
627
628/*!
629 * @brief Structure for the RDC mapping
630 *
631 * Defines the structure for the RDC resource collections.
632 */
633
634typedef enum _rdc_master
635{
636 kRDC_Master_A53 = 0U, /**< ARM Cortex-A53 RDC Master */
637 kRDC_Master_M7 = 1U, /**< ARM Cortex-M7 RDC Master */
638 kRDC_Reserved0 = 2U, /**< Reserved */
639 kRDC_Master_SDMA3_PERIPH = 3U, /**< SDMA3 PERIPHERAL RDC Master */
640 kRDC_Reserved1 = 4U, /**< Reserved */
641 kRDC_Master_LCDIF = 5U, /**< LCDIF RDC Master */
642 kRDC_Master_ISI = 6U, /**< ISI PORT RDC Master */
643 kRDC_Master_SDMA3_BURST = 7U, /**< SDMA3 BURST RDC Master */
644 kRDC_Master_Coresight = 8U, /**< CORESIGHT RDC Master */
645 kRDC_Master_DAP = 9U, /**< DAP RDC Master */
646 kRDC_Master_CAAM = 10U, /**< CAAM RDC Master */
647 kRDC_Master_SDMA1_PERIPH = 11U, /**< SDMA1 PERIPHERAL RDC Master */
648 kRDC_Master_SDMA1_BURST = 12U, /**< SDMA1 BURST RDC Master */
649 kRDC_Master_APBHDMA = 13U, /**< APBH DMA RDC Master */
650 kRDC_Master_RAWNAND = 14U, /**< RAW NAND RDC Master */
651 kRDC_Master_USDHC1 = 15U, /**< USDHC1 RDC Master */
652 kRDC_Master_USDHC2 = 16U, /**< USDHC2 RDC Master */
653 kRDC_Master_USDHC3 = 17U, /**< USDHC3 RDC Master */
654 kRDC_Master_GPU = 18U, /**< GPU RDC Master */
655 kRDC_Master_USB1 = 19U, /**< USB1 RDC Master */
656 kRDC_Reserved2 = 20U, /**< Reserved */
657 kRDC_Master_TESTPORT = 21U, /**< TESTPORT RDC Master */
658 kRDC_Master_ENET1TX = 22U, /**< ENET1 TX RDC Master */
659 kRDC_Master_ENET1RX = 23U, /**< ENET1 RX RDC Master */
660 kRDC_Master_SDMA2_PERIPH = 24U, /**< SDMA2 PERIPH RDC Master */
661 kRDC_Master_SDMA2_BURST = 24U, /**< SDMA2 BURST RDC Master */
662 kRDC_Master_SDMA2_SPBA2 = 24U, /**< SDMA2 to SPBA2 RDC Master */
663 kRDC_Master_SDMA3_SPBA2 = 25U, /**< SDMA3 to SPBA2 RDC Master */
664 kRDC_Master_SDMA1_SPBA1 = 26U, /**< SDMA1 to SPBA1 RDC Master */
665} rdc_master_t;
666
667typedef enum _rdc_mem
668{
669 kRDC_Mem_MRC0_0 = 0U, /**< DRAM. Region resolution 4KB. */
670 kRDC_Mem_MRC0_1 = 1U,
671 kRDC_Mem_MRC0_2 = 2U,
672 kRDC_Mem_MRC0_3 = 3U,
673 kRDC_Mem_MRC0_4 = 4U,
674 kRDC_Mem_MRC0_5 = 5U,
675 kRDC_Mem_MRC0_6 = 6U,
676 kRDC_Mem_MRC0_7 = 7U,
677 kRDC_Mem_MRC1_0 = 8U, /**< QSPI. Region resolution 4KB. */
678 kRDC_Mem_MRC1_1 = 9U,
679 kRDC_Mem_MRC1_2 = 10U,
680 kRDC_Mem_MRC1_3 = 11U,
681 kRDC_Mem_MRC1_4 = 12U,
682 kRDC_Mem_MRC1_5 = 13U,
683 kRDC_Mem_MRC1_6 = 14U,
684 kRDC_Mem_MRC1_7 = 15U,
685 kRDC_Mem_MRC2_0 = 16U, /**< OCRAM. Region resolution 128B. */
686 kRDC_Mem_MRC2_1 = 17U,
687 kRDC_Mem_MRC2_2 = 18U,
688 kRDC_Mem_MRC2_3 = 19U,
689 kRDC_Mem_MRC2_4 = 20U,
690 kRDC_Mem_MRC3_0 = 21U, /**< OCRAM_S. Region resolution 128B. */
691 kRDC_Mem_MRC3_1 = 22U,
692 kRDC_Mem_MRC3_2 = 23U,
693 kRDC_Mem_MRC3_3 = 24U,
694 kRDC_Mem_MRC3_4 = 25U,
695 kRDC_Mem_MRC4_0 = 26U, /**< TCM. Region resolution 128B. */
696 kRDC_Mem_MRC4_1 = 27U,
697 kRDC_Mem_MRC4_2 = 28U,
698 kRDC_Mem_MRC4_3 = 29U,
699 kRDC_Mem_MRC4_4 = 30U,
700 kRDC_Mem_MRC5_0 = 31U, /**< GIC. Region resolution 4KB. */
701 kRDC_Mem_MRC5_1 = 32U,
702 kRDC_Mem_MRC5_2 = 33U,
703 kRDC_Mem_MRC5_3 = 34U,
704 kRDC_Mem_MRC6_0 = 35U, /**< GPU. Region resolution 4KB. */
705 kRDC_Mem_MRC6_1 = 36U,
706 kRDC_Mem_MRC6_2 = 37U,
707 kRDC_Mem_MRC6_3 = 38U,
708 kRDC_Mem_MRC6_4 = 39U,
709 kRDC_Mem_MRC6_5 = 40U,
710 kRDC_Mem_MRC6_6 = 41U,
711 kRDC_Mem_MRC6_7 = 42U,
712 kRDC_Mem_MRC7_0 = 43U, /**< DEBUG(DAP). Region resolution 4KB. */
713 kRDC_Mem_MRC7_1 = 44U,
714 kRDC_Mem_MRC7_2 = 45U,
715 kRDC_Mem_MRC7_3 = 46U,
716 kRDC_Mem_MRC8_0 = 47U, /**< DDRC(REG). Region resolution 4KB. */
717 kRDC_Mem_MRC8_1 = 48U,
718 kRDC_Mem_MRC8_2 = 49U,
719 kRDC_Mem_MRC8_3 = 50U,
720 kRDC_Mem_MRC8_4 = 51U,
721} rdc_mem_t;
722
723typedef enum _rdc_periph
724{
725 kRDC_Periph_GPIO1 = 0U, /**< GPIO1 RDC Peripheral */
726 kRDC_Periph_GPIO2 = 1U, /**< GPIO2 RDC Peripheral */
727 kRDC_Periph_GPIO3 = 2U, /**< GPIO3 RDC Peripheral */
728 kRDC_Periph_GPIO4 = 3U, /**< GPIO4 RDC Peripheral */
729 kRDC_Periph_GPIO5 = 4U, /**< GPIO5 RDC Peripheral */
730 kRDC_Periph_ANA_TSENSOR = 6U, /**< ANA_TSENSOR RDC Peripheral */
731 kRDC_Periph_ANA_OSC = 7U, /**< ANA_OSC RDC Peripheral */
732 kRDC_Periph_WDOG1 = 8U, /**< WDOG1 RDC Peripheral */
733 kRDC_Periph_WDOG2 = 9U, /**< WDOG2 RDC Peripheral */
734 kRDC_Periph_WDOG3 = 10U, /**< WDOG3 RDC Peripheral */
735 kRDC_Periph_SDMA3 = 11U, /**< SDMA3 RDC Peripheral */
736 kRDC_Periph_SDMA2 = 12U, /**< SDMA2 RDC Peripheral */
737 kRDC_Periph_GPT1 = 13U, /**< GPT1 RDC Peripheral */
738 kRDC_Periph_GPT2 = 14U, /**< GPT2 RDC Peripheral */
739 kRDC_Periph_GPT3 = 15U, /**< GPT3 RDC Peripheral */
740 kRDC_Periph_ROMCP = 17U, /**< ROMCP RDC Peripheral */
741 kRDC_Periph_IOMUXC = 19U, /**< IOMUXC RDC Peripheral */
742 kRDC_Periph_IOMUXC_GPR = 20U, /**< IOMUXC_GPR RDC Peripheral */
743 kRDC_Periph_OCOTP_CTRL = 21U, /**< OCOTP_CTRL RDC Peripheral */
744 kRDC_Periph_ANA_PLL = 22U, /**< ANA_PLL RDC Peripheral */
745 kRDC_Periph_SNVS_HP = 23U, /**< SNVS_HP GPR RDC Peripheral */
746 kRDC_Periph_CCM = 24U, /**< CCM RDC Peripheral */
747 kRDC_Periph_SRC = 25U, /**< SRC RDC Peripheral */
748 kRDC_Periph_GPC = 26U, /**< GPC RDC Peripheral */
749 kRDC_Periph_SEMAPHORE1 = 27U, /**< SEMAPHORE1 RDC Peripheral */
750 kRDC_Periph_SEMAPHORE2 = 28U, /**< SEMAPHORE2 RDC Peripheral */
751 kRDC_Periph_RDC = 29U, /**< RDC RDC Peripheral */
752 kRDC_Periph_CSU = 30U, /**< CSU RDC Peripheral */
753 kRDC_Periph_LCDIF = 32U, /**< LCDIF RDC Peripheral */
754 kRDC_Periph_MIPI_DSI = 33U, /**< MIPI_DSI RDC Peripheral */
755 kRDC_Periph_ISI = 34U, /**< ISI RDC Peripheral */
756 kRDC_Periph_MIPI_CSI = 35U, /**< MIPI_CSI RDC Peripheral */
757 kRDC_Periph_USB1 = 36U, /**< USB1 RDC Peripheral */
758 kRDC_Periph_PWM1 = 38U, /**< PWM1 RDC Peripheral */
759 kRDC_Periph_PWM2 = 39U, /**< PWM2 RDC Peripheral */
760 kRDC_Periph_PWM3 = 40U, /**< PWM3 RDC Peripheral */
761 kRDC_Periph_PWM4 = 41U, /**< PWM4 RDC Peripheral */
762 kRDC_Periph_SYS_COUNTER_RD = 42U, /**< System counter read RDC Peripheral */
763 kRDC_Periph_SYS_COUNTER_CMP = 43U, /**< System counter compare RDC Peripheral */
764 kRDC_Periph_SYS_COUNTER_CTRL = 44U, /**< System counter control RDC Peripheral */
765 kRDC_Periph_GPT6 = 46U, /**< GPT6 RDC Peripheral */
766 kRDC_Periph_GPT5 = 47U, /**< GPT5 RDC Peripheral */
767 kRDC_Periph_GPT4 = 48U, /**< GPT4 RDC Peripheral */
768 kRDC_Periph_TZASC = 56U, /**< TZASC RDC Peripheral */
769 kRDC_Periph_PERFMON1 = 60U, /**< PERFMON1 RDC Peripheral */
770 kRDC_Periph_PERFMON2 = 61U, /**< PERFMON2 RDC Peripheral */
771 kRDC_Periph_PLATFORM_CTRL = 62U, /**< PLATFORM_CTRL RDC Peripheral */
772 kRDC_Periph_QOSC = 63U, /**< QOSC RDC Peripheral */
773 kRDC_Periph_I2C1 = 66U, /**< I2C1 RDC Peripheral */
774 kRDC_Periph_I2C2 = 67U, /**< I2C2 RDC Peripheral */
775 kRDC_Periph_I2C3 = 68U, /**< I2C3 RDC Peripheral */
776 kRDC_Periph_I2C4 = 69U, /**< I2C4 RDC Peripheral */
777 kRDC_Periph_UART4 = 70U, /**< UART4 RDC Peripheral */
778 kRDC_Periph_MU_A = 74U, /**< MU_A RDC Peripheral */
779 kRDC_Periph_MU_B = 75U, /**< MU_B RDC Peripheral */
780 kRDC_Periph_SEMAPHORE_HS = 76U, /**< SEMAPHORE_HS RDC Peripheral */
781 kRDC_Periph_SAI2 = 79U, /**< SAI2 RDC Peripheral */
782 kRDC_Periph_SAI3 = 80U, /**< SAI3 RDC Peripheral */
783 kRDC_Periph_SAI5 = 82U, /**< SAI5 RDC Peripheral */
784 kRDC_Periph_SAI6 = 83U, /**< SAI6 RDC Peripheral */
785 kRDC_Periph_USDHC1 = 84U, /**< USDHC1 RDC Peripheral */
786 kRDC_Periph_USDHC2 = 85U, /**< USDHC2 RDC Peripheral */
787 kRDC_Periph_USDHC3 = 86U, /**< USDHC3 RDC Peripheral */
788 kRDC_Periph_SAI7 = 87U, /**< SAI7 RDC Peripheral */
789 kRDC_Periph_SPBA2 = 90U, /**< SPBA2 RDC Peripheral */
790 kRDC_Periph_QSPI = 91U, /**< QSPI RDC Peripheral */
791 kRDC_Periph_SDMA1 = 93U, /**< SDMA1 RDC Peripheral */
792 kRDC_Periph_ENET1 = 94U, /**< ENET1 RDC Peripheral */
793 kRDC_Periph_SPDIF1 = 97U, /**< SPDIF1 RDC Peripheral */
794 kRDC_Periph_ECSPI1 = 98U, /**< ECSPI1 RDC Peripheral */
795 kRDC_Periph_ECSPI2 = 99U, /**< ECSPI2 RDC Peripheral */
796 kRDC_Periph_ECSPI3 = 100U, /**< ECSPI3 RDC Peripheral */
797 kRDC_Periph_MICFIL = 101U, /**< MICFIL RDC Peripheral */
798 kRDC_Periph_UART1 = 102U, /**< UART1 RDC Peripheral */
799 kRDC_Periph_UART3 = 104U, /**< UART3 RDC Peripheral */
800 kRDC_Periph_UART2 = 105U, /**< UART2 RDC Peripheral */
801 kRDC_Periph_ASRC = 107U, /**< ASRC RDC Peripheral */
802 kRDC_Periph_SPBA1 = 111U, /**< SPBA1 RDC Peripheral */
803 kRDC_Periph_CAAM = 114U, /**< CAAM RDC Peripheral */
804} rdc_periph_t;
805
806/* @} */
807
808/*!
809 * @}
810 */ /* end of group Mapping_Information */
811
812/* ----------------------------------------------------------------------------
813 -- Device Peripheral Access Layer
814 ---------------------------------------------------------------------------- */
815
816/*!
817 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
818 * @{
819 */
820
821/*
822** Start of section using anonymous unions
823*/
824
825#if defined(__ARMCC_VERSION)
826#if (__ARMCC_VERSION >= 6010050)
827#pragma clang diagnostic push
828#else
829#pragma push
830#pragma anon_unions
831#endif
832#elif defined(__GNUC__)
833/* anonymous unions are enabled by default */
834#elif defined(__IAR_SYSTEMS_ICC__)
835#pragma language = extended
836#else
837#error Not supported compiler type
838#endif
839
840/* ----------------------------------------------------------------------------
841 -- AIPSTZ Peripheral Access Layer
842 ---------------------------------------------------------------------------- */
843
844/*!
845 * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer
846 * @{
847 */
848
849/** AIPSTZ - Register Layout Typedef */
850typedef struct
851{
852 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */
853 uint8_t RESERVED_0[60];
854 __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */
855 __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */
856 __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */
857 __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */
858 __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */
859} AIPSTZ_Type;
860
861/* ----------------------------------------------------------------------------
862 -- AIPSTZ Register Masks
863 ---------------------------------------------------------------------------- */
864
865/*!
866 * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks
867 * @{
868 */
869
870/*! @name MPR - Master Priviledge Registers */
871/*! @{ */
872#define AIPSTZ_MPR_MPROT5_MASK (0xF00U)
873#define AIPSTZ_MPR_MPROT5_SHIFT (8U)
874/*! MPROT5
875 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of
876 * the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access
877 * attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses.
878 * 0bxx1x..This master is trusted for write accesses.
879 * 0bx0xx..This master is not trusted for read accesses.
880 * 0bx1xx..This master is trusted for read accesses.
881 * 0b1xxx..Write accesses from this master are allowed to be buffered
882 */
883#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
884#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
885#define AIPSTZ_MPR_MPROT3_SHIFT (16U)
886/*! MPROT3
887 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of
888 * the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access
889 * attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses.
890 * 0bxx1x..This master is trusted for write accesses.
891 * 0bx0xx..This master is not trusted for read accesses.
892 * 0bx1xx..This master is trusted for read accesses.
893 * 0b1xxx..Write accesses from this master are allowed to be buffered
894 */
895#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
896#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
897#define AIPSTZ_MPR_MPROT2_SHIFT (20U)
898/*! MPROT2
899 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of
900 * the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access
901 * attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses.
902 * 0bxx1x..This master is trusted for write accesses.
903 * 0bx0xx..This master is not trusted for read accesses.
904 * 0bx1xx..This master is trusted for read accesses.
905 * 0b1xxx..Write accesses from this master are allowed to be buffered
906 */
907#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
908#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
909#define AIPSTZ_MPR_MPROT1_SHIFT (24U)
910/*! MPROT1
911 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of
912 * the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access
913 * attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses.
914 * 0bxx1x..This master is trusted for write accesses.
915 * 0bx0xx..This master is not trusted for read accesses.
916 * 0bx1xx..This master is trusted for read accesses.
917 * 0b1xxx..Write accesses from this master are allowed to be buffered
918 */
919#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
920#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
921#define AIPSTZ_MPR_MPROT0_SHIFT (28U)
922/*! MPROT0
923 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of
924 * the hprot[1] access attribute. 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access
925 * attribute is used directly to determine ips_supervisor_access. 0bxx0x..This master is not trusted for write accesses.
926 * 0bxx1x..This master is trusted for write accesses.
927 * 0bx0xx..This master is not trusted for read accesses.
928 * 0bx1xx..This master is trusted for read accesses.
929 * 0b1xxx..Write accesses from this master are allowed to be buffered
930 */
931#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
932/*! @} */
933
934/*! @name OPACR - Off-Platform Peripheral Access Control Registers */
935/*! @{ */
936#define AIPSTZ_OPACR_OPAC7_MASK (0xFU)
937#define AIPSTZ_OPACR_OPAC7_SHIFT (0U)
938/*! OPAC7
939 * 0bxxx0..Accesses from an untrusted master are allowed.
940 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
941 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
942 * 0bxx0x..This peripheral allows write accesses.
943 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
944 * error response and no peripheral access is initiated on the IPS bus.
945 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
946 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
947 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
948 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
949 * on the IPS bus.
950 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
951 */
952#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
953#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
954#define AIPSTZ_OPACR_OPAC6_SHIFT (4U)
955/*! OPAC6
956 * 0bxxx0..Accesses from an untrusted master are allowed.
957 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
958 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
959 * 0bxx0x..This peripheral allows write accesses.
960 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
961 * error response and no peripheral access is initiated on the IPS bus.
962 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
963 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
964 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
965 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
966 * on the IPS bus.
967 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
968 */
969#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
970#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
971#define AIPSTZ_OPACR_OPAC5_SHIFT (8U)
972/*! OPAC5
973 * 0bxxx0..Accesses from an untrusted master are allowed.
974 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
975 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
976 * 0bxx0x..This peripheral allows write accesses.
977 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
978 * error response and no peripheral access is initiated on the IPS bus.
979 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
980 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
981 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
982 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
983 * on the IPS bus.
984 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
985 */
986#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
987#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
988#define AIPSTZ_OPACR_OPAC4_SHIFT (12U)
989/*! OPAC4
990 * 0bxxx0..Accesses from an untrusted master are allowed.
991 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
992 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
993 * 0bxx0x..This peripheral allows write accesses.
994 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
995 * error response and no peripheral access is initiated on the IPS bus.
996 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
997 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
998 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
999 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1000 * on the IPS bus.
1001 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1002 */
1003#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
1004#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
1005#define AIPSTZ_OPACR_OPAC3_SHIFT (16U)
1006/*! OPAC3
1007 * 0bxxx0..Accesses from an untrusted master are allowed.
1008 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1009 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1010 * 0bxx0x..This peripheral allows write accesses.
1011 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1012 * error response and no peripheral access is initiated on the IPS bus.
1013 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1014 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1015 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1016 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1017 * on the IPS bus.
1018 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1019 */
1020#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
1021#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
1022#define AIPSTZ_OPACR_OPAC2_SHIFT (20U)
1023/*! OPAC2
1024 * 0bxxx0..Accesses from an untrusted master are allowed.
1025 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1026 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1027 * 0bxx0x..This peripheral allows write accesses.
1028 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1029 * error response and no peripheral access is initiated on the IPS bus.
1030 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1031 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1032 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1033 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1034 * on the IPS bus.
1035 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1036 */
1037#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
1038#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
1039#define AIPSTZ_OPACR_OPAC1_SHIFT (24U)
1040/*! OPAC1
1041 * 0bxxx0..Accesses from an untrusted master are allowed.
1042 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1043 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1044 * 0bxx0x..This peripheral allows write accesses.
1045 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1046 * error response and no peripheral access is initiated on the IPS bus.
1047 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1048 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1049 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1050 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1051 * on the IPS bus.
1052 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1053 */
1054#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
1055#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
1056#define AIPSTZ_OPACR_OPAC0_SHIFT (28U)
1057/*! OPAC0
1058 * 0bxxx0..Accesses from an untrusted master are allowed.
1059 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1060 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1061 * 0bxx0x..This peripheral allows write accesses.
1062 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1063 * error response and no peripheral access is initiated on the IPS bus.
1064 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1065 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1066 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1067 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1068 * on the IPS bus.
1069 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1070 */
1071#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
1072/*! @} */
1073
1074/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */
1075/*! @{ */
1076#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
1077#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
1078/*! OPAC15
1079 * 0bxxx0..Accesses from an untrusted master are allowed.
1080 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1081 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1082 * 0bxx0x..This peripheral allows write accesses.
1083 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1084 * error response and no peripheral access is initiated on the IPS bus.
1085 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1086 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1087 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1088 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1089 * on the IPS bus.
1090 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1091 */
1092#define AIPSTZ_OPACR1_OPAC15(x) \
1093 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
1094#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
1095#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
1096/*! OPAC14
1097 * 0bxxx0..Accesses from an untrusted master are allowed.
1098 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1099 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1100 * 0bxx0x..This peripheral allows write accesses.
1101 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1102 * error response and no peripheral access is initiated on the IPS bus.
1103 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1104 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1105 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1106 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1107 * on the IPS bus.
1108 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1109 */
1110#define AIPSTZ_OPACR1_OPAC14(x) \
1111 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
1112#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
1113#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
1114/*! OPAC13
1115 * 0bxxx0..Accesses from an untrusted master are allowed.
1116 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1117 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1118 * 0bxx0x..This peripheral allows write accesses.
1119 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1120 * error response and no peripheral access is initiated on the IPS bus.
1121 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1122 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1123 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1124 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1125 * on the IPS bus.
1126 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1127 */
1128#define AIPSTZ_OPACR1_OPAC13(x) \
1129 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
1130#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
1131#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
1132/*! OPAC12
1133 * 0bxxx0..Accesses from an untrusted master are allowed.
1134 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1135 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1136 * 0bxx0x..This peripheral allows write accesses.
1137 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1138 * error response and no peripheral access is initiated on the IPS bus.
1139 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1140 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1141 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1142 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1143 * on the IPS bus.
1144 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1145 */
1146#define AIPSTZ_OPACR1_OPAC12(x) \
1147 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
1148#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
1149#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
1150/*! OPAC11
1151 * 0bxxx0..Accesses from an untrusted master are allowed.
1152 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1153 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1154 * 0bxx0x..This peripheral allows write accesses.
1155 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1156 * error response and no peripheral access is initiated on the IPS bus.
1157 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1158 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1159 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1160 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1161 * on the IPS bus.
1162 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1163 */
1164#define AIPSTZ_OPACR1_OPAC11(x) \
1165 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
1166#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
1167#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
1168/*! OPAC10
1169 * 0bxxx0..Accesses from an untrusted master are allowed.
1170 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1171 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1172 * 0bxx0x..This peripheral allows write accesses.
1173 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1174 * error response and no peripheral access is initiated on the IPS bus.
1175 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1176 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1177 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1178 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1179 * on the IPS bus.
1180 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1181 */
1182#define AIPSTZ_OPACR1_OPAC10(x) \
1183 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
1184#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
1185#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
1186/*! OPAC9
1187 * 0bxxx0..Accesses from an untrusted master are allowed.
1188 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1189 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1190 * 0bxx0x..This peripheral allows write accesses.
1191 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1192 * error response and no peripheral access is initiated on the IPS bus.
1193 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1194 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1195 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1196 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1197 * on the IPS bus.
1198 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1199 */
1200#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
1201#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
1202#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
1203/*! OPAC8
1204 * 0bxxx0..Accesses from an untrusted master are allowed.
1205 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1206 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1207 * 0bxx0x..This peripheral allows write accesses.
1208 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1209 * error response and no peripheral access is initiated on the IPS bus.
1210 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1211 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1212 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1213 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1214 * on the IPS bus.
1215 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1216 */
1217#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
1218/*! @} */
1219
1220/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */
1221/*! @{ */
1222#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
1223#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
1224/*! OPAC23
1225 * 0bxxx0..Accesses from an untrusted master are allowed.
1226 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1227 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1228 * 0bxx0x..This peripheral allows write accesses.
1229 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1230 * error response and no peripheral access is initiated on the IPS bus.
1231 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1232 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1233 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1234 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1235 * on the IPS bus.
1236 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1237 */
1238#define AIPSTZ_OPACR2_OPAC23(x) \
1239 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
1240#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
1241#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
1242/*! OPAC22
1243 * 0bxxx0..Accesses from an untrusted master are allowed.
1244 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1245 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1246 * 0bxx0x..This peripheral allows write accesses.
1247 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1248 * error response and no peripheral access is initiated on the IPS bus.
1249 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1250 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1251 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1252 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1253 * on the IPS bus.
1254 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1255 */
1256#define AIPSTZ_OPACR2_OPAC22(x) \
1257 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
1258#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
1259#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
1260/*! OPAC21
1261 * 0bxxx0..Accesses from an untrusted master are allowed.
1262 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1263 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1264 * 0bxx0x..This peripheral allows write accesses.
1265 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1266 * error response and no peripheral access is initiated on the IPS bus.
1267 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1268 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1269 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1270 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1271 * on the IPS bus.
1272 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1273 */
1274#define AIPSTZ_OPACR2_OPAC21(x) \
1275 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
1276#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
1277#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
1278/*! OPAC20
1279 * 0bxxx0..Accesses from an untrusted master are allowed.
1280 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1281 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1282 * 0bxx0x..This peripheral allows write accesses.
1283 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1284 * error response and no peripheral access is initiated on the IPS bus.
1285 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1286 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1287 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1288 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1289 * on the IPS bus.
1290 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1291 */
1292#define AIPSTZ_OPACR2_OPAC20(x) \
1293 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
1294#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
1295#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
1296/*! OPAC19
1297 * 0bxxx0..Accesses from an untrusted master are allowed.
1298 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1299 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1300 * 0bxx0x..This peripheral allows write accesses.
1301 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1302 * error response and no peripheral access is initiated on the IPS bus.
1303 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1304 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1305 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1306 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1307 * on the IPS bus.
1308 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1309 */
1310#define AIPSTZ_OPACR2_OPAC19(x) \
1311 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
1312#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
1313#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
1314/*! OPAC18
1315 * 0bxxx0..Accesses from an untrusted master are allowed.
1316 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1317 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1318 * 0bxx0x..This peripheral allows write accesses.
1319 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1320 * error response and no peripheral access is initiated on the IPS bus.
1321 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1322 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1323 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1324 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1325 * on the IPS bus.
1326 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1327 */
1328#define AIPSTZ_OPACR2_OPAC18(x) \
1329 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
1330#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
1331#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
1332/*! OPAC17
1333 * 0bxxx0..Accesses from an untrusted master are allowed.
1334 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1335 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1336 * 0bxx0x..This peripheral allows write accesses.
1337 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1338 * error response and no peripheral access is initiated on the IPS bus.
1339 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1340 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1341 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1342 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1343 * on the IPS bus.
1344 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1345 */
1346#define AIPSTZ_OPACR2_OPAC17(x) \
1347 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
1348#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
1349#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
1350/*! OPAC16
1351 * 0bxxx0..Accesses from an untrusted master are allowed.
1352 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1353 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1354 * 0bxx0x..This peripheral allows write accesses.
1355 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1356 * error response and no peripheral access is initiated on the IPS bus.
1357 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1358 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1359 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1360 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1361 * on the IPS bus.
1362 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1363 */
1364#define AIPSTZ_OPACR2_OPAC16(x) \
1365 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
1366/*! @} */
1367
1368/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */
1369/*! @{ */
1370#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
1371#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
1372/*! OPAC31
1373 * 0bxxx0..Accesses from an untrusted master are allowed.
1374 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1375 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1376 * 0bxx0x..This peripheral allows write accesses.
1377 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1378 * error response and no peripheral access is initiated on the IPS bus.
1379 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1380 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1381 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1382 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1383 * on the IPS bus.
1384 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1385 */
1386#define AIPSTZ_OPACR3_OPAC31(x) \
1387 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
1388#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
1389#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
1390/*! OPAC30
1391 * 0bxxx0..Accesses from an untrusted master are allowed.
1392 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1393 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1394 * 0bxx0x..This peripheral allows write accesses.
1395 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1396 * error response and no peripheral access is initiated on the IPS bus.
1397 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1398 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1399 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1400 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1401 * on the IPS bus.
1402 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1403 */
1404#define AIPSTZ_OPACR3_OPAC30(x) \
1405 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
1406#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
1407#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
1408/*! OPAC29
1409 * 0bxxx0..Accesses from an untrusted master are allowed.
1410 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1411 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1412 * 0bxx0x..This peripheral allows write accesses.
1413 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1414 * error response and no peripheral access is initiated on the IPS bus.
1415 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1416 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1417 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1418 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1419 * on the IPS bus.
1420 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1421 */
1422#define AIPSTZ_OPACR3_OPAC29(x) \
1423 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
1424#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
1425#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
1426/*! OPAC28
1427 * 0bxxx0..Accesses from an untrusted master are allowed.
1428 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1429 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1430 * 0bxx0x..This peripheral allows write accesses.
1431 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1432 * error response and no peripheral access is initiated on the IPS bus.
1433 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1434 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1435 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1436 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1437 * on the IPS bus.
1438 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1439 */
1440#define AIPSTZ_OPACR3_OPAC28(x) \
1441 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
1442#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
1443#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
1444/*! OPAC27
1445 * 0bxxx0..Accesses from an untrusted master are allowed.
1446 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1447 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1448 * 0bxx0x..This peripheral allows write accesses.
1449 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1450 * error response and no peripheral access is initiated on the IPS bus.
1451 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1452 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1453 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1454 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1455 * on the IPS bus.
1456 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1457 */
1458#define AIPSTZ_OPACR3_OPAC27(x) \
1459 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
1460#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
1461#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
1462/*! OPAC26
1463 * 0bxxx0..Accesses from an untrusted master are allowed.
1464 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1465 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1466 * 0bxx0x..This peripheral allows write accesses.
1467 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1468 * error response and no peripheral access is initiated on the IPS bus.
1469 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1470 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1471 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1472 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1473 * on the IPS bus.
1474 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1475 */
1476#define AIPSTZ_OPACR3_OPAC26(x) \
1477 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
1478#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
1479#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
1480/*! OPAC25
1481 * 0bxxx0..Accesses from an untrusted master are allowed.
1482 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1483 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1484 * 0bxx0x..This peripheral allows write accesses.
1485 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1486 * error response and no peripheral access is initiated on the IPS bus.
1487 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1488 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1489 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1490 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1491 * on the IPS bus.
1492 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1493 */
1494#define AIPSTZ_OPACR3_OPAC25(x) \
1495 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
1496#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
1497#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
1498/*! OPAC24
1499 * 0bxxx0..Accesses from an untrusted master are allowed.
1500 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1501 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1502 * 0bxx0x..This peripheral allows write accesses.
1503 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1504 * error response and no peripheral access is initiated on the IPS bus.
1505 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1506 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1507 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1508 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1509 * on the IPS bus.
1510 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1511 */
1512#define AIPSTZ_OPACR3_OPAC24(x) \
1513 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
1514/*! @} */
1515
1516/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */
1517/*! @{ */
1518#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
1519#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
1520/*! OPAC33
1521 * 0bxxx0..Accesses from an untrusted master are allowed.
1522 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1523 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1524 * 0bxx0x..This peripheral allows write accesses.
1525 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1526 * error response and no peripheral access is initiated on the IPS bus.
1527 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1528 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1529 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1530 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1531 * on the IPS bus.
1532 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1533 */
1534#define AIPSTZ_OPACR4_OPAC33(x) \
1535 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
1536#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
1537#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
1538/*! OPAC32
1539 * 0bxxx0..Accesses from an untrusted master are allowed.
1540 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1541 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1542 * 0bxx0x..This peripheral allows write accesses.
1543 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1544 * error response and no peripheral access is initiated on the IPS bus.
1545 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1546 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1547 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1548 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1549 * on the IPS bus.
1550 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1551 */
1552#define AIPSTZ_OPACR4_OPAC32(x) \
1553 (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
1554/*! @} */
1555
1556/*!
1557 * @}
1558 */ /* end of group AIPSTZ_Register_Masks */
1559
1560/* AIPSTZ - Peripheral instance base addresses */
1561/** Peripheral AIPSTZ base address */
1562#define AIPSTZ_BASE (0x301F0000u)
1563/** Peripheral AIPSTZ base pointer */
1564#define AIPSTZ ((AIPSTZ_Type *)AIPSTZ_BASE)
1565/** Array initializer of AIPSTZ peripheral base addresses */
1566#define AIPSTZ_BASE_ADDRS \
1567 { \
1568 AIPSTZ_BASE \
1569 }
1570/** Array initializer of AIPSTZ peripheral base pointers */
1571#define AIPSTZ_BASE_PTRS \
1572 { \
1573 AIPSTZ \
1574 }
1575
1576/*!
1577 * @}
1578 */ /* end of group AIPSTZ_Peripheral_Access_Layer */
1579
1580/* ----------------------------------------------------------------------------
1581 -- APBH Peripheral Access Layer
1582 ---------------------------------------------------------------------------- */
1583
1584/*!
1585 * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer
1586 * @{
1587 */
1588
1589/** APBH - Register Layout Typedef */
1590typedef struct
1591{
1592 __IO uint32_t CTRL0; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */
1593 __IO uint32_t CTRL0_SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */
1594 __IO uint32_t CTRL0_CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */
1595 __IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */
1596 __IO uint32_t CTRL1; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */
1597 __IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */
1598 __IO uint32_t CTRL1_CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */
1599 __IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */
1600 __IO uint32_t CTRL2; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */
1601 __IO uint32_t CTRL2_SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */
1602 __IO uint32_t CTRL2_CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */
1603 __IO uint32_t CTRL2_TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */
1604 __IO uint32_t CHANNEL_CTRL; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */
1605 __IO uint32_t CHANNEL_CTRL_SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */
1606 __IO uint32_t CHANNEL_CTRL_CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */
1607 __IO uint32_t CHANNEL_CTRL_TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */
1608 __I uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */
1609 uint8_t RESERVED_0[12];
1610 __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */
1611 uint8_t RESERVED_1[12];
1612 __IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60 */
1613 uint8_t RESERVED_2[156];
1614 struct
1615 { /* offset: 0x100, array step: 0x70 */
1616 __I uint32_t CH_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, array offset: 0x100, array
1617 step: 0x70 */
1618 uint8_t RESERVED_0[12];
1619 __IO uint32_t
1620 CH_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, array offset: 0x110, array step: 0x70 */
1621 uint8_t RESERVED_1[12];
1622 __I uint32_t CH_CMD; /**< APBH DMA Channel n Command Register, array offset: 0x120, array step: 0x70 */
1623 uint8_t RESERVED_2[12];
1624 __I uint32_t CH_BAR; /**< APBH DMA Channel n Buffer Address Register, array offset: 0x130, array step: 0x70 */
1625 uint8_t RESERVED_3[12];
1626 __IO uint32_t CH_SEMA; /**< APBH DMA Channel n Semaphore Register, array offset: 0x140, array step: 0x70 */
1627 uint8_t RESERVED_4[12];
1628 __I uint32_t
1629 CH_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x150, array step: 0x70 */
1630 uint8_t RESERVED_5[12];
1631 __I uint32_t
1632 CH_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x160, array step: 0x70 */
1633 uint8_t RESERVED_6[12];
1634 } CH_CFGn[16];
1635 __I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */
1636} APBH_Type;
1637
1638/* ----------------------------------------------------------------------------
1639 -- APBH Register Masks
1640 ---------------------------------------------------------------------------- */
1641
1642/*!
1643 * @addtogroup APBH_Register_Masks APBH Register Masks
1644 * @{
1645 */
1646
1647/*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */
1648/*! @{ */
1649#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU)
1650#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U)
1651/*! CLKGATE_CHANNEL
1652 * 0b0000000000000001..NAND0
1653 * 0b0000000000000010..NAND1
1654 * 0b0000000000000100..NAND2
1655 * 0b0000000000001000..NAND3
1656 * 0b0000000000010000..NAND4
1657 * 0b0000000000100000..NAND5
1658 * 0b0000000001000000..NAND6
1659 * 0b0000000010000000..NAND7
1660 * 0b0000000100000000..SSP
1661 */
1662#define APBH_CTRL0_CLKGATE_CHANNEL(x) \
1663 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK)
1664#define APBH_CTRL0_RSVD0_MASK (0xFFF0000U)
1665#define APBH_CTRL0_RSVD0_SHIFT (16U)
1666#define APBH_CTRL0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_RSVD0_SHIFT)) & APBH_CTRL0_RSVD0_MASK)
1667#define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U)
1668#define APBH_CTRL0_APB_BURST_EN_SHIFT (28U)
1669#define APBH_CTRL0_APB_BURST_EN(x) \
1670 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK)
1671#define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U)
1672#define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U)
1673#define APBH_CTRL0_AHB_BURST8_EN(x) \
1674 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK)
1675#define APBH_CTRL0_CLKGATE_MASK (0x40000000U)
1676#define APBH_CTRL0_CLKGATE_SHIFT (30U)
1677#define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK)
1678#define APBH_CTRL0_SFTRST_MASK (0x80000000U)
1679#define APBH_CTRL0_SFTRST_SHIFT (31U)
1680#define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK)
1681/*! @} */
1682
1683/*! @name CTRL0_SET - AHB to APBH Bridge Control and Status Register 0 */
1684/*! @{ */
1685#define APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK (0xFFFFU)
1686#define APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT (0U)
1687/*! CLKGATE_CHANNEL
1688 * 0b0000000000000001..NAND0
1689 * 0b0000000000000010..NAND1
1690 * 0b0000000000000100..NAND2
1691 * 0b0000000000001000..NAND3
1692 * 0b0000000000010000..NAND4
1693 * 0b0000000000100000..NAND5
1694 * 0b0000000001000000..NAND6
1695 * 0b0000000010000000..NAND7
1696 * 0b0000000100000000..SSP
1697 */
1698#define APBH_CTRL0_SET_CLKGATE_CHANNEL(x) \
1699 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK)
1700#define APBH_CTRL0_SET_RSVD0_MASK (0xFFF0000U)
1701#define APBH_CTRL0_SET_RSVD0_SHIFT (16U)
1702#define APBH_CTRL0_SET_RSVD0(x) \
1703 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_RSVD0_SHIFT)) & APBH_CTRL0_SET_RSVD0_MASK)
1704#define APBH_CTRL0_SET_APB_BURST_EN_MASK (0x10000000U)
1705#define APBH_CTRL0_SET_APB_BURST_EN_SHIFT (28U)
1706#define APBH_CTRL0_SET_APB_BURST_EN(x) \
1707 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_APB_BURST_EN_SHIFT)) & APBH_CTRL0_SET_APB_BURST_EN_MASK)
1708#define APBH_CTRL0_SET_AHB_BURST8_EN_MASK (0x20000000U)
1709#define APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT (29U)
1710#define APBH_CTRL0_SET_AHB_BURST8_EN(x) \
1711 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_SET_AHB_BURST8_EN_MASK)
1712#define APBH_CTRL0_SET_CLKGATE_MASK (0x40000000U)
1713#define APBH_CTRL0_SET_CLKGATE_SHIFT (30U)
1714#define APBH_CTRL0_SET_CLKGATE(x) \
1715 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_SHIFT)) & APBH_CTRL0_SET_CLKGATE_MASK)
1716#define APBH_CTRL0_SET_SFTRST_MASK (0x80000000U)
1717#define APBH_CTRL0_SET_SFTRST_SHIFT (31U)
1718#define APBH_CTRL0_SET_SFTRST(x) \
1719 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_SFTRST_SHIFT)) & APBH_CTRL0_SET_SFTRST_MASK)
1720/*! @} */
1721
1722/*! @name CTRL0_CLR - AHB to APBH Bridge Control and Status Register 0 */
1723/*! @{ */
1724#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK (0xFFFFU)
1725#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT (0U)
1726/*! CLKGATE_CHANNEL
1727 * 0b0000000000000001..NAND0
1728 * 0b0000000000000010..NAND1
1729 * 0b0000000000000100..NAND2
1730 * 0b0000000000001000..NAND3
1731 * 0b0000000000010000..NAND4
1732 * 0b0000000000100000..NAND5
1733 * 0b0000000001000000..NAND6
1734 * 0b0000000010000000..NAND7
1735 * 0b0000000100000000..SSP
1736 */
1737#define APBH_CTRL0_CLR_CLKGATE_CHANNEL(x) \
1738 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK)
1739#define APBH_CTRL0_CLR_RSVD0_MASK (0xFFF0000U)
1740#define APBH_CTRL0_CLR_RSVD0_SHIFT (16U)
1741#define APBH_CTRL0_CLR_RSVD0(x) \
1742 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_RSVD0_SHIFT)) & APBH_CTRL0_CLR_RSVD0_MASK)
1743#define APBH_CTRL0_CLR_APB_BURST_EN_MASK (0x10000000U)
1744#define APBH_CTRL0_CLR_APB_BURST_EN_SHIFT (28U)
1745#define APBH_CTRL0_CLR_APB_BURST_EN(x) \
1746 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_APB_BURST_EN_SHIFT)) & APBH_CTRL0_CLR_APB_BURST_EN_MASK)
1747#define APBH_CTRL0_CLR_AHB_BURST8_EN_MASK (0x20000000U)
1748#define APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT (29U)
1749#define APBH_CTRL0_CLR_AHB_BURST8_EN(x) \
1750 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_CLR_AHB_BURST8_EN_MASK)
1751#define APBH_CTRL0_CLR_CLKGATE_MASK (0x40000000U)
1752#define APBH_CTRL0_CLR_CLKGATE_SHIFT (30U)
1753#define APBH_CTRL0_CLR_CLKGATE(x) \
1754 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_MASK)
1755#define APBH_CTRL0_CLR_SFTRST_MASK (0x80000000U)
1756#define APBH_CTRL0_CLR_SFTRST_SHIFT (31U)
1757#define APBH_CTRL0_CLR_SFTRST(x) \
1758 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_SFTRST_SHIFT)) & APBH_CTRL0_CLR_SFTRST_MASK)
1759/*! @} */
1760
1761/*! @name CTRL0_TOG - AHB to APBH Bridge Control and Status Register 0 */
1762/*! @{ */
1763#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK (0xFFFFU)
1764#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT (0U)
1765/*! CLKGATE_CHANNEL
1766 * 0b0000000000000001..NAND0
1767 * 0b0000000000000010..NAND1
1768 * 0b0000000000000100..NAND2
1769 * 0b0000000000001000..NAND3
1770 * 0b0000000000010000..NAND4
1771 * 0b0000000000100000..NAND5
1772 * 0b0000000001000000..NAND6
1773 * 0b0000000010000000..NAND7
1774 * 0b0000000100000000..SSP
1775 */
1776#define APBH_CTRL0_TOG_CLKGATE_CHANNEL(x) \
1777 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK)
1778#define APBH_CTRL0_TOG_RSVD0_MASK (0xFFF0000U)
1779#define APBH_CTRL0_TOG_RSVD0_SHIFT (16U)
1780#define APBH_CTRL0_TOG_RSVD0(x) \
1781 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_RSVD0_SHIFT)) & APBH_CTRL0_TOG_RSVD0_MASK)
1782#define APBH_CTRL0_TOG_APB_BURST_EN_MASK (0x10000000U)
1783#define APBH_CTRL0_TOG_APB_BURST_EN_SHIFT (28U)
1784#define APBH_CTRL0_TOG_APB_BURST_EN(x) \
1785 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_APB_BURST_EN_SHIFT)) & APBH_CTRL0_TOG_APB_BURST_EN_MASK)
1786#define APBH_CTRL0_TOG_AHB_BURST8_EN_MASK (0x20000000U)
1787#define APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT (29U)
1788#define APBH_CTRL0_TOG_AHB_BURST8_EN(x) \
1789 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_TOG_AHB_BURST8_EN_MASK)
1790#define APBH_CTRL0_TOG_CLKGATE_MASK (0x40000000U)
1791#define APBH_CTRL0_TOG_CLKGATE_SHIFT (30U)
1792#define APBH_CTRL0_TOG_CLKGATE(x) \
1793 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_MASK)
1794#define APBH_CTRL0_TOG_SFTRST_MASK (0x80000000U)
1795#define APBH_CTRL0_TOG_SFTRST_SHIFT (31U)
1796#define APBH_CTRL0_TOG_SFTRST(x) \
1797 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_SFTRST_SHIFT)) & APBH_CTRL0_TOG_SFTRST_MASK)
1798/*! @} */
1799
1800/*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */
1801/*! @{ */
1802#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U)
1803#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U)
1804#define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) \
1805 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK)
1806#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U)
1807#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U)
1808#define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) \
1809 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK)
1810#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U)
1811#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U)
1812#define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) \
1813 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK)
1814#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U)
1815#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U)
1816#define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) \
1817 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK)
1818#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U)
1819#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U)
1820#define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) \
1821 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK)
1822#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U)
1823#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U)
1824#define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) \
1825 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK)
1826#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U)
1827#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U)
1828#define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) \
1829 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK)
1830#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U)
1831#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U)
1832#define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) \
1833 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK)
1834#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U)
1835#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U)
1836#define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) \
1837 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK)
1838#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U)
1839#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U)
1840#define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) \
1841 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK)
1842#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U)
1843#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U)
1844#define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) \
1845 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK)
1846#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U)
1847#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U)
1848#define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) \
1849 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK)
1850#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
1851#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U)
1852#define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) \
1853 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK)
1854#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
1855#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U)
1856#define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) \
1857 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK)
1858#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
1859#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U)
1860#define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) \
1861 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK)
1862#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
1863#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U)
1864#define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) \
1865 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK)
1866#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
1867#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
1868#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) \
1869 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK)
1870#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
1871#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
1872#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) \
1873 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK)
1874#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
1875#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
1876#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) \
1877 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK)
1878#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
1879#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
1880#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) \
1881 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK)
1882#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
1883#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
1884#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) \
1885 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK)
1886#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
1887#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
1888#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) \
1889 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK)
1890#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
1891#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
1892#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) \
1893 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK)
1894#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
1895#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
1896#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) \
1897 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK)
1898#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
1899#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
1900#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) \
1901 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK)
1902#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
1903#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
1904#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) \
1905 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK)
1906#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
1907#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
1908#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) \
1909 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
1910#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
1911#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
1912#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) \
1913 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK)
1914#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
1915#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
1916#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) \
1917 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK)
1918#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
1919#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
1920#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) \
1921 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK)
1922#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
1923#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
1924#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) \
1925 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK)
1926#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
1927#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
1928#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) \
1929 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK)
1930/*! @} */
1931
1932/*! @name CTRL1_SET - AHB to APBH Bridge Control and Status Register 1 */
1933/*! @{ */
1934#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK (0x1U)
1935#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT (0U)
1936#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ(x) \
1937 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK)
1938#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK (0x2U)
1939#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT (1U)
1940#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ(x) \
1941 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK)
1942#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK (0x4U)
1943#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT (2U)
1944#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ(x) \
1945 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK)
1946#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK (0x8U)
1947#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT (3U)
1948#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ(x) \
1949 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK)
1950#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK (0x10U)
1951#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT (4U)
1952#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ(x) \
1953 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK)
1954#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK (0x20U)
1955#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT (5U)
1956#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ(x) \
1957 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK)
1958#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK (0x40U)
1959#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT (6U)
1960#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ(x) \
1961 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK)
1962#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK (0x80U)
1963#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT (7U)
1964#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ(x) \
1965 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK)
1966#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK (0x100U)
1967#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT (8U)
1968#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ(x) \
1969 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK)
1970#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK (0x200U)
1971#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT (9U)
1972#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ(x) \
1973 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK)
1974#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK (0x400U)
1975#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT (10U)
1976#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ(x) \
1977 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK)
1978#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK (0x800U)
1979#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT (11U)
1980#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ(x) \
1981 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK)
1982#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
1983#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT (12U)
1984#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ(x) \
1985 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK)
1986#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
1987#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT (13U)
1988#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ(x) \
1989 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK)
1990#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
1991#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT (14U)
1992#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ(x) \
1993 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK)
1994#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
1995#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT (15U)
1996#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ(x) \
1997 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK)
1998#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
1999#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
2000#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN(x) \
2001 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & \
2002 APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK)
2003#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
2004#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
2005#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN(x) \
2006 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & \
2007 APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK)
2008#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
2009#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
2010#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN(x) \
2011 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & \
2012 APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK)
2013#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
2014#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
2015#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN(x) \
2016 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & \
2017 APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK)
2018#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
2019#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
2020#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN(x) \
2021 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & \
2022 APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK)
2023#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
2024#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
2025#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN(x) \
2026 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & \
2027 APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK)
2028#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
2029#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
2030#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN(x) \
2031 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & \
2032 APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK)
2033#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
2034#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
2035#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN(x) \
2036 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & \
2037 APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK)
2038#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
2039#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
2040#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN(x) \
2041 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & \
2042 APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK)
2043#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
2044#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
2045#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN(x) \
2046 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & \
2047 APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK)
2048#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
2049#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
2050#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN(x) \
2051 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & \
2052 APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK)
2053#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
2054#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
2055#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN(x) \
2056 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & \
2057 APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK)
2058#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
2059#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
2060#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN(x) \
2061 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & \
2062 APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK)
2063#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
2064#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
2065#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN(x) \
2066 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & \
2067 APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK)
2068#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
2069#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
2070#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN(x) \
2071 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & \
2072 APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK)
2073#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
2074#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
2075#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN(x) \
2076 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & \
2077 APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK)
2078/*! @} */
2079
2080/*! @name CTRL1_CLR - AHB to APBH Bridge Control and Status Register 1 */
2081/*! @{ */
2082#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK (0x1U)
2083#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT (0U)
2084#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ(x) \
2085 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK)
2086#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK (0x2U)
2087#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT (1U)
2088#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ(x) \
2089 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK)
2090#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK (0x4U)
2091#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT (2U)
2092#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ(x) \
2093 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK)
2094#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK (0x8U)
2095#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT (3U)
2096#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ(x) \
2097 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK)
2098#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK (0x10U)
2099#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT (4U)
2100#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ(x) \
2101 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK)
2102#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK (0x20U)
2103#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT (5U)
2104#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ(x) \
2105 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK)
2106#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK (0x40U)
2107#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT (6U)
2108#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ(x) \
2109 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK)
2110#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK (0x80U)
2111#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT (7U)
2112#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ(x) \
2113 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK)
2114#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK (0x100U)
2115#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT (8U)
2116#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ(x) \
2117 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK)
2118#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK (0x200U)
2119#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT (9U)
2120#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ(x) \
2121 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK)
2122#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK (0x400U)
2123#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT (10U)
2124#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ(x) \
2125 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK)
2126#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK (0x800U)
2127#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT (11U)
2128#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ(x) \
2129 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK)
2130#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
2131#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT (12U)
2132#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ(x) \
2133 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK)
2134#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
2135#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT (13U)
2136#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ(x) \
2137 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK)
2138#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
2139#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT (14U)
2140#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ(x) \
2141 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK)
2142#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
2143#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT (15U)
2144#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ(x) \
2145 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK)
2146#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
2147#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
2148#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN(x) \
2149 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & \
2150 APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK)
2151#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
2152#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
2153#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN(x) \
2154 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & \
2155 APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK)
2156#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
2157#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
2158#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN(x) \
2159 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & \
2160 APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK)
2161#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
2162#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
2163#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN(x) \
2164 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & \
2165 APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK)
2166#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
2167#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
2168#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN(x) \
2169 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & \
2170 APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK)
2171#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
2172#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
2173#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN(x) \
2174 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & \
2175 APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK)
2176#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
2177#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
2178#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN(x) \
2179 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & \
2180 APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK)
2181#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
2182#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
2183#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN(x) \
2184 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & \
2185 APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK)
2186#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
2187#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
2188#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN(x) \
2189 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & \
2190 APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK)
2191#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
2192#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
2193#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN(x) \
2194 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & \
2195 APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK)
2196#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
2197#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
2198#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN(x) \
2199 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & \
2200 APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK)
2201#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
2202#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
2203#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN(x) \
2204 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & \
2205 APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK)
2206#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
2207#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
2208#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN(x) \
2209 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & \
2210 APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK)
2211#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
2212#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
2213#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN(x) \
2214 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & \
2215 APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK)
2216#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
2217#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
2218#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN(x) \
2219 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & \
2220 APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK)
2221#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
2222#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
2223#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN(x) \
2224 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & \
2225 APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK)
2226/*! @} */
2227
2228/*! @name CTRL1_TOG - AHB to APBH Bridge Control and Status Register 1 */
2229/*! @{ */
2230#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK (0x1U)
2231#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT (0U)
2232#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ(x) \
2233 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK)
2234#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK (0x2U)
2235#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT (1U)
2236#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ(x) \
2237 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK)
2238#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK (0x4U)
2239#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT (2U)
2240#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ(x) \
2241 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK)
2242#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK (0x8U)
2243#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT (3U)
2244#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ(x) \
2245 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK)
2246#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK (0x10U)
2247#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT (4U)
2248#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ(x) \
2249 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK)
2250#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK (0x20U)
2251#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT (5U)
2252#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ(x) \
2253 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK)
2254#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK (0x40U)
2255#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT (6U)
2256#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ(x) \
2257 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK)
2258#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK (0x80U)
2259#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT (7U)
2260#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ(x) \
2261 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK)
2262#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK (0x100U)
2263#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT (8U)
2264#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ(x) \
2265 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK)
2266#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK (0x200U)
2267#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT (9U)
2268#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ(x) \
2269 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK)
2270#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK (0x400U)
2271#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT (10U)
2272#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ(x) \
2273 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK)
2274#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK (0x800U)
2275#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT (11U)
2276#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ(x) \
2277 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK)
2278#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
2279#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT (12U)
2280#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ(x) \
2281 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK)
2282#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
2283#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT (13U)
2284#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ(x) \
2285 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK)
2286#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
2287#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT (14U)
2288#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ(x) \
2289 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK)
2290#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
2291#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT (15U)
2292#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ(x) \
2293 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK)
2294#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
2295#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
2296#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN(x) \
2297 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & \
2298 APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK)
2299#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
2300#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
2301#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN(x) \
2302 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & \
2303 APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK)
2304#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
2305#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
2306#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN(x) \
2307 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & \
2308 APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK)
2309#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
2310#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
2311#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN(x) \
2312 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & \
2313 APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK)
2314#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
2315#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
2316#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN(x) \
2317 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & \
2318 APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK)
2319#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
2320#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
2321#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN(x) \
2322 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & \
2323 APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK)
2324#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
2325#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
2326#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN(x) \
2327 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & \
2328 APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK)
2329#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
2330#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
2331#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN(x) \
2332 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & \
2333 APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK)
2334#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
2335#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
2336#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN(x) \
2337 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & \
2338 APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK)
2339#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
2340#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
2341#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN(x) \
2342 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & \
2343 APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK)
2344#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
2345#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
2346#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN(x) \
2347 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & \
2348 APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK)
2349#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
2350#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
2351#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN(x) \
2352 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & \
2353 APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK)
2354#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
2355#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
2356#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN(x) \
2357 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & \
2358 APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK)
2359#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
2360#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
2361#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN(x) \
2362 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & \
2363 APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK)
2364#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
2365#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
2366#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN(x) \
2367 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & \
2368 APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK)
2369#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
2370#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
2371#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN(x) \
2372 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & \
2373 APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK)
2374/*! @} */
2375
2376/*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */
2377/*! @{ */
2378#define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U)
2379#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U)
2380#define APBH_CTRL2_CH0_ERROR_IRQ(x) \
2381 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK)
2382#define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U)
2383#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U)
2384#define APBH_CTRL2_CH1_ERROR_IRQ(x) \
2385 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK)
2386#define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U)
2387#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U)
2388#define APBH_CTRL2_CH2_ERROR_IRQ(x) \
2389 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK)
2390#define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U)
2391#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U)
2392#define APBH_CTRL2_CH3_ERROR_IRQ(x) \
2393 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK)
2394#define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U)
2395#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U)
2396#define APBH_CTRL2_CH4_ERROR_IRQ(x) \
2397 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK)
2398#define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U)
2399#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U)
2400#define APBH_CTRL2_CH5_ERROR_IRQ(x) \
2401 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK)
2402#define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U)
2403#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U)
2404#define APBH_CTRL2_CH6_ERROR_IRQ(x) \
2405 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK)
2406#define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U)
2407#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U)
2408#define APBH_CTRL2_CH7_ERROR_IRQ(x) \
2409 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK)
2410#define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U)
2411#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U)
2412#define APBH_CTRL2_CH8_ERROR_IRQ(x) \
2413 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK)
2414#define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U)
2415#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U)
2416#define APBH_CTRL2_CH9_ERROR_IRQ(x) \
2417 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK)
2418#define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U)
2419#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U)
2420#define APBH_CTRL2_CH10_ERROR_IRQ(x) \
2421 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK)
2422#define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U)
2423#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U)
2424#define APBH_CTRL2_CH11_ERROR_IRQ(x) \
2425 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK)
2426#define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U)
2427#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U)
2428#define APBH_CTRL2_CH12_ERROR_IRQ(x) \
2429 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK)
2430#define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U)
2431#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U)
2432#define APBH_CTRL2_CH13_ERROR_IRQ(x) \
2433 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK)
2434#define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U)
2435#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U)
2436#define APBH_CTRL2_CH14_ERROR_IRQ(x) \
2437 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK)
2438#define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U)
2439#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U)
2440#define APBH_CTRL2_CH15_ERROR_IRQ(x) \
2441 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK)
2442#define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U)
2443#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U)
2444/*! CH0_ERROR_STATUS
2445 * 0b0..An early termination from the device causes error IRQ.
2446 * 0b1..An AHB bus error causes error IRQ.
2447 */
2448#define APBH_CTRL2_CH0_ERROR_STATUS(x) \
2449 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK)
2450#define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U)
2451#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U)
2452/*! CH1_ERROR_STATUS
2453 * 0b0..An early termination from the device causes error IRQ.
2454 * 0b1..An AHB bus error causes error IRQ.
2455 */
2456#define APBH_CTRL2_CH1_ERROR_STATUS(x) \
2457 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK)
2458#define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U)
2459#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U)
2460/*! CH2_ERROR_STATUS
2461 * 0b0..An early termination from the device causes error IRQ.
2462 * 0b1..An AHB bus error causes error IRQ.
2463 */
2464#define APBH_CTRL2_CH2_ERROR_STATUS(x) \
2465 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK)
2466#define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U)
2467#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U)
2468/*! CH3_ERROR_STATUS
2469 * 0b0..An early termination from the device causes error IRQ.
2470 * 0b1..An AHB bus error causes error IRQ.
2471 */
2472#define APBH_CTRL2_CH3_ERROR_STATUS(x) \
2473 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK)
2474#define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U)
2475#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U)
2476/*! CH4_ERROR_STATUS
2477 * 0b0..An early termination from the device causes error IRQ.
2478 * 0b1..An AHB bus error causes error IRQ.
2479 */
2480#define APBH_CTRL2_CH4_ERROR_STATUS(x) \
2481 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK)
2482#define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U)
2483#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U)
2484/*! CH5_ERROR_STATUS
2485 * 0b0..An early termination from the device causes error IRQ.
2486 * 0b1..An AHB bus error causes error IRQ.
2487 */
2488#define APBH_CTRL2_CH5_ERROR_STATUS(x) \
2489 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK)
2490#define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U)
2491#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U)
2492/*! CH6_ERROR_STATUS
2493 * 0b0..An early termination from the device causes error IRQ.
2494 * 0b1..An AHB bus error causes error IRQ.
2495 */
2496#define APBH_CTRL2_CH6_ERROR_STATUS(x) \
2497 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK)
2498#define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U)
2499#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U)
2500/*! CH7_ERROR_STATUS
2501 * 0b0..An early termination from the device causes error IRQ.
2502 * 0b1..An AHB bus error causes error IRQ.
2503 */
2504#define APBH_CTRL2_CH7_ERROR_STATUS(x) \
2505 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK)
2506#define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U)
2507#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U)
2508/*! CH8_ERROR_STATUS
2509 * 0b0..An early termination from the device causes error IRQ.
2510 * 0b1..An AHB bus error causes error IRQ.
2511 */
2512#define APBH_CTRL2_CH8_ERROR_STATUS(x) \
2513 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK)
2514#define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U)
2515#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U)
2516/*! CH9_ERROR_STATUS
2517 * 0b0..An early termination from the device causes error IRQ.
2518 * 0b1..An AHB bus error causes error IRQ.
2519 */
2520#define APBH_CTRL2_CH9_ERROR_STATUS(x) \
2521 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK)
2522#define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U)
2523#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U)
2524/*! CH10_ERROR_STATUS
2525 * 0b0..An early termination from the device causes error IRQ.
2526 * 0b1..An AHB bus error causes error IRQ.
2527 */
2528#define APBH_CTRL2_CH10_ERROR_STATUS(x) \
2529 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK)
2530#define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U)
2531#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U)
2532/*! CH11_ERROR_STATUS
2533 * 0b0..An early termination from the device causes error IRQ.
2534 * 0b1..An AHB bus error causes error IRQ.
2535 */
2536#define APBH_CTRL2_CH11_ERROR_STATUS(x) \
2537 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK)
2538#define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U)
2539#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U)
2540/*! CH12_ERROR_STATUS
2541 * 0b0..An early termination from the device causes error IRQ.
2542 * 0b1..An AHB bus error causes error IRQ.
2543 */
2544#define APBH_CTRL2_CH12_ERROR_STATUS(x) \
2545 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK)
2546#define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U)
2547#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U)
2548/*! CH13_ERROR_STATUS
2549 * 0b0..An early termination from the device causes error IRQ.
2550 * 0b1..An AHB bus error causes error IRQ.
2551 */
2552#define APBH_CTRL2_CH13_ERROR_STATUS(x) \
2553 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK)
2554#define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U)
2555#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U)
2556/*! CH14_ERROR_STATUS
2557 * 0b0..An early termination from the device causes error IRQ.
2558 * 0b1..An AHB bus error causes error IRQ.
2559 */
2560#define APBH_CTRL2_CH14_ERROR_STATUS(x) \
2561 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK)
2562#define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U)
2563#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U)
2564/*! CH15_ERROR_STATUS
2565 * 0b0..An early termination from the device causes error IRQ.
2566 * 0b1..An AHB bus error causes error IRQ.
2567 */
2568#define APBH_CTRL2_CH15_ERROR_STATUS(x) \
2569 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK)
2570/*! @} */
2571
2572/*! @name CTRL2_SET - AHB to APBH Bridge Control and Status Register 2 */
2573/*! @{ */
2574#define APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK (0x1U)
2575#define APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT (0U)
2576#define APBH_CTRL2_SET_CH0_ERROR_IRQ(x) \
2577 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK)
2578#define APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK (0x2U)
2579#define APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT (1U)
2580#define APBH_CTRL2_SET_CH1_ERROR_IRQ(x) \
2581 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK)
2582#define APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK (0x4U)
2583#define APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT (2U)
2584#define APBH_CTRL2_SET_CH2_ERROR_IRQ(x) \
2585 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK)
2586#define APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK (0x8U)
2587#define APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT (3U)
2588#define APBH_CTRL2_SET_CH3_ERROR_IRQ(x) \
2589 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK)
2590#define APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK (0x10U)
2591#define APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT (4U)
2592#define APBH_CTRL2_SET_CH4_ERROR_IRQ(x) \
2593 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK)
2594#define APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK (0x20U)
2595#define APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT (5U)
2596#define APBH_CTRL2_SET_CH5_ERROR_IRQ(x) \
2597 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK)
2598#define APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK (0x40U)
2599#define APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT (6U)
2600#define APBH_CTRL2_SET_CH6_ERROR_IRQ(x) \
2601 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK)
2602#define APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK (0x80U)
2603#define APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT (7U)
2604#define APBH_CTRL2_SET_CH7_ERROR_IRQ(x) \
2605 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK)
2606#define APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK (0x100U)
2607#define APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT (8U)
2608#define APBH_CTRL2_SET_CH8_ERROR_IRQ(x) \
2609 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK)
2610#define APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK (0x200U)
2611#define APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT (9U)
2612#define APBH_CTRL2_SET_CH9_ERROR_IRQ(x) \
2613 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK)
2614#define APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK (0x400U)
2615#define APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT (10U)
2616#define APBH_CTRL2_SET_CH10_ERROR_IRQ(x) \
2617 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK)
2618#define APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK (0x800U)
2619#define APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT (11U)
2620#define APBH_CTRL2_SET_CH11_ERROR_IRQ(x) \
2621 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK)
2622#define APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK (0x1000U)
2623#define APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT (12U)
2624#define APBH_CTRL2_SET_CH12_ERROR_IRQ(x) \
2625 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK)
2626#define APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK (0x2000U)
2627#define APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT (13U)
2628#define APBH_CTRL2_SET_CH13_ERROR_IRQ(x) \
2629 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK)
2630#define APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK (0x4000U)
2631#define APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT (14U)
2632#define APBH_CTRL2_SET_CH14_ERROR_IRQ(x) \
2633 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK)
2634#define APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK (0x8000U)
2635#define APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT (15U)
2636#define APBH_CTRL2_SET_CH15_ERROR_IRQ(x) \
2637 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK)
2638#define APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK (0x10000U)
2639#define APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT (16U)
2640/*! CH0_ERROR_STATUS
2641 * 0b0..An early termination from the device causes error IRQ.
2642 * 0b1..An AHB bus error causes error IRQ.
2643 */
2644#define APBH_CTRL2_SET_CH0_ERROR_STATUS(x) \
2645 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK)
2646#define APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK (0x20000U)
2647#define APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT (17U)
2648/*! CH1_ERROR_STATUS
2649 * 0b0..An early termination from the device causes error IRQ.
2650 * 0b1..An AHB bus error causes error IRQ.
2651 */
2652#define APBH_CTRL2_SET_CH1_ERROR_STATUS(x) \
2653 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK)
2654#define APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK (0x40000U)
2655#define APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT (18U)
2656/*! CH2_ERROR_STATUS
2657 * 0b0..An early termination from the device causes error IRQ.
2658 * 0b1..An AHB bus error causes error IRQ.
2659 */
2660#define APBH_CTRL2_SET_CH2_ERROR_STATUS(x) \
2661 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK)
2662#define APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK (0x80000U)
2663#define APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT (19U)
2664/*! CH3_ERROR_STATUS
2665 * 0b0..An early termination from the device causes error IRQ.
2666 * 0b1..An AHB bus error causes error IRQ.
2667 */
2668#define APBH_CTRL2_SET_CH3_ERROR_STATUS(x) \
2669 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK)
2670#define APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK (0x100000U)
2671#define APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT (20U)
2672/*! CH4_ERROR_STATUS
2673 * 0b0..An early termination from the device causes error IRQ.
2674 * 0b1..An AHB bus error causes error IRQ.
2675 */
2676#define APBH_CTRL2_SET_CH4_ERROR_STATUS(x) \
2677 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK)
2678#define APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK (0x200000U)
2679#define APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT (21U)
2680/*! CH5_ERROR_STATUS
2681 * 0b0..An early termination from the device causes error IRQ.
2682 * 0b1..An AHB bus error causes error IRQ.
2683 */
2684#define APBH_CTRL2_SET_CH5_ERROR_STATUS(x) \
2685 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK)
2686#define APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK (0x400000U)
2687#define APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT (22U)
2688/*! CH6_ERROR_STATUS
2689 * 0b0..An early termination from the device causes error IRQ.
2690 * 0b1..An AHB bus error causes error IRQ.
2691 */
2692#define APBH_CTRL2_SET_CH6_ERROR_STATUS(x) \
2693 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK)
2694#define APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK (0x800000U)
2695#define APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT (23U)
2696/*! CH7_ERROR_STATUS
2697 * 0b0..An early termination from the device causes error IRQ.
2698 * 0b1..An AHB bus error causes error IRQ.
2699 */
2700#define APBH_CTRL2_SET_CH7_ERROR_STATUS(x) \
2701 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK)
2702#define APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK (0x1000000U)
2703#define APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT (24U)
2704/*! CH8_ERROR_STATUS
2705 * 0b0..An early termination from the device causes error IRQ.
2706 * 0b1..An AHB bus error causes error IRQ.
2707 */
2708#define APBH_CTRL2_SET_CH8_ERROR_STATUS(x) \
2709 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK)
2710#define APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK (0x2000000U)
2711#define APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT (25U)
2712/*! CH9_ERROR_STATUS
2713 * 0b0..An early termination from the device causes error IRQ.
2714 * 0b1..An AHB bus error causes error IRQ.
2715 */
2716#define APBH_CTRL2_SET_CH9_ERROR_STATUS(x) \
2717 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK)
2718#define APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK (0x4000000U)
2719#define APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT (26U)
2720/*! CH10_ERROR_STATUS
2721 * 0b0..An early termination from the device causes error IRQ.
2722 * 0b1..An AHB bus error causes error IRQ.
2723 */
2724#define APBH_CTRL2_SET_CH10_ERROR_STATUS(x) \
2725 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK)
2726#define APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK (0x8000000U)
2727#define APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT (27U)
2728/*! CH11_ERROR_STATUS
2729 * 0b0..An early termination from the device causes error IRQ.
2730 * 0b1..An AHB bus error causes error IRQ.
2731 */
2732#define APBH_CTRL2_SET_CH11_ERROR_STATUS(x) \
2733 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK)
2734#define APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK (0x10000000U)
2735#define APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT (28U)
2736/*! CH12_ERROR_STATUS
2737 * 0b0..An early termination from the device causes error IRQ.
2738 * 0b1..An AHB bus error causes error IRQ.
2739 */
2740#define APBH_CTRL2_SET_CH12_ERROR_STATUS(x) \
2741 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK)
2742#define APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK (0x20000000U)
2743#define APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT (29U)
2744/*! CH13_ERROR_STATUS
2745 * 0b0..An early termination from the device causes error IRQ.
2746 * 0b1..An AHB bus error causes error IRQ.
2747 */
2748#define APBH_CTRL2_SET_CH13_ERROR_STATUS(x) \
2749 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK)
2750#define APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK (0x40000000U)
2751#define APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT (30U)
2752/*! CH14_ERROR_STATUS
2753 * 0b0..An early termination from the device causes error IRQ.
2754 * 0b1..An AHB bus error causes error IRQ.
2755 */
2756#define APBH_CTRL2_SET_CH14_ERROR_STATUS(x) \
2757 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK)
2758#define APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK (0x80000000U)
2759#define APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT (31U)
2760/*! CH15_ERROR_STATUS
2761 * 0b0..An early termination from the device causes error IRQ.
2762 * 0b1..An AHB bus error causes error IRQ.
2763 */
2764#define APBH_CTRL2_SET_CH15_ERROR_STATUS(x) \
2765 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK)
2766/*! @} */
2767
2768/*! @name CTRL2_CLR - AHB to APBH Bridge Control and Status Register 2 */
2769/*! @{ */
2770#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK (0x1U)
2771#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT (0U)
2772#define APBH_CTRL2_CLR_CH0_ERROR_IRQ(x) \
2773 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK)
2774#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK (0x2U)
2775#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT (1U)
2776#define APBH_CTRL2_CLR_CH1_ERROR_IRQ(x) \
2777 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK)
2778#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK (0x4U)
2779#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT (2U)
2780#define APBH_CTRL2_CLR_CH2_ERROR_IRQ(x) \
2781 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK)
2782#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK (0x8U)
2783#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT (3U)
2784#define APBH_CTRL2_CLR_CH3_ERROR_IRQ(x) \
2785 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK)
2786#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK (0x10U)
2787#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT (4U)
2788#define APBH_CTRL2_CLR_CH4_ERROR_IRQ(x) \
2789 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK)
2790#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK (0x20U)
2791#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT (5U)
2792#define APBH_CTRL2_CLR_CH5_ERROR_IRQ(x) \
2793 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK)
2794#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK (0x40U)
2795#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT (6U)
2796#define APBH_CTRL2_CLR_CH6_ERROR_IRQ(x) \
2797 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK)
2798#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK (0x80U)
2799#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT (7U)
2800#define APBH_CTRL2_CLR_CH7_ERROR_IRQ(x) \
2801 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK)
2802#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK (0x100U)
2803#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT (8U)
2804#define APBH_CTRL2_CLR_CH8_ERROR_IRQ(x) \
2805 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK)
2806#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK (0x200U)
2807#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT (9U)
2808#define APBH_CTRL2_CLR_CH9_ERROR_IRQ(x) \
2809 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK)
2810#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK (0x400U)
2811#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT (10U)
2812#define APBH_CTRL2_CLR_CH10_ERROR_IRQ(x) \
2813 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK)
2814#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK (0x800U)
2815#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT (11U)
2816#define APBH_CTRL2_CLR_CH11_ERROR_IRQ(x) \
2817 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK)
2818#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK (0x1000U)
2819#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT (12U)
2820#define APBH_CTRL2_CLR_CH12_ERROR_IRQ(x) \
2821 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK)
2822#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK (0x2000U)
2823#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT (13U)
2824#define APBH_CTRL2_CLR_CH13_ERROR_IRQ(x) \
2825 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK)
2826#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK (0x4000U)
2827#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT (14U)
2828#define APBH_CTRL2_CLR_CH14_ERROR_IRQ(x) \
2829 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK)
2830#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK (0x8000U)
2831#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT (15U)
2832#define APBH_CTRL2_CLR_CH15_ERROR_IRQ(x) \
2833 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK)
2834#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK (0x10000U)
2835#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT (16U)
2836/*! CH0_ERROR_STATUS
2837 * 0b0..An early termination from the device causes error IRQ.
2838 * 0b1..An AHB bus error causes error IRQ.
2839 */
2840#define APBH_CTRL2_CLR_CH0_ERROR_STATUS(x) \
2841 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK)
2842#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK (0x20000U)
2843#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT (17U)
2844/*! CH1_ERROR_STATUS
2845 * 0b0..An early termination from the device causes error IRQ.
2846 * 0b1..An AHB bus error causes error IRQ.
2847 */
2848#define APBH_CTRL2_CLR_CH1_ERROR_STATUS(x) \
2849 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK)
2850#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK (0x40000U)
2851#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT (18U)
2852/*! CH2_ERROR_STATUS
2853 * 0b0..An early termination from the device causes error IRQ.
2854 * 0b1..An AHB bus error causes error IRQ.
2855 */
2856#define APBH_CTRL2_CLR_CH2_ERROR_STATUS(x) \
2857 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK)
2858#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK (0x80000U)
2859#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT (19U)
2860/*! CH3_ERROR_STATUS
2861 * 0b0..An early termination from the device causes error IRQ.
2862 * 0b1..An AHB bus error causes error IRQ.
2863 */
2864#define APBH_CTRL2_CLR_CH3_ERROR_STATUS(x) \
2865 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK)
2866#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK (0x100000U)
2867#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT (20U)
2868/*! CH4_ERROR_STATUS
2869 * 0b0..An early termination from the device causes error IRQ.
2870 * 0b1..An AHB bus error causes error IRQ.
2871 */
2872#define APBH_CTRL2_CLR_CH4_ERROR_STATUS(x) \
2873 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK)
2874#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK (0x200000U)
2875#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT (21U)
2876/*! CH5_ERROR_STATUS
2877 * 0b0..An early termination from the device causes error IRQ.
2878 * 0b1..An AHB bus error causes error IRQ.
2879 */
2880#define APBH_CTRL2_CLR_CH5_ERROR_STATUS(x) \
2881 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK)
2882#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK (0x400000U)
2883#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT (22U)
2884/*! CH6_ERROR_STATUS
2885 * 0b0..An early termination from the device causes error IRQ.
2886 * 0b1..An AHB bus error causes error IRQ.
2887 */
2888#define APBH_CTRL2_CLR_CH6_ERROR_STATUS(x) \
2889 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK)
2890#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK (0x800000U)
2891#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT (23U)
2892/*! CH7_ERROR_STATUS
2893 * 0b0..An early termination from the device causes error IRQ.
2894 * 0b1..An AHB bus error causes error IRQ.
2895 */
2896#define APBH_CTRL2_CLR_CH7_ERROR_STATUS(x) \
2897 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK)
2898#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK (0x1000000U)
2899#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT (24U)
2900/*! CH8_ERROR_STATUS
2901 * 0b0..An early termination from the device causes error IRQ.
2902 * 0b1..An AHB bus error causes error IRQ.
2903 */
2904#define APBH_CTRL2_CLR_CH8_ERROR_STATUS(x) \
2905 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK)
2906#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK (0x2000000U)
2907#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT (25U)
2908/*! CH9_ERROR_STATUS
2909 * 0b0..An early termination from the device causes error IRQ.
2910 * 0b1..An AHB bus error causes error IRQ.
2911 */
2912#define APBH_CTRL2_CLR_CH9_ERROR_STATUS(x) \
2913 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK)
2914#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK (0x4000000U)
2915#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT (26U)
2916/*! CH10_ERROR_STATUS
2917 * 0b0..An early termination from the device causes error IRQ.
2918 * 0b1..An AHB bus error causes error IRQ.
2919 */
2920#define APBH_CTRL2_CLR_CH10_ERROR_STATUS(x) \
2921 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK)
2922#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK (0x8000000U)
2923#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT (27U)
2924/*! CH11_ERROR_STATUS
2925 * 0b0..An early termination from the device causes error IRQ.
2926 * 0b1..An AHB bus error causes error IRQ.
2927 */
2928#define APBH_CTRL2_CLR_CH11_ERROR_STATUS(x) \
2929 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK)
2930#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK (0x10000000U)
2931#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT (28U)
2932/*! CH12_ERROR_STATUS
2933 * 0b0..An early termination from the device causes error IRQ.
2934 * 0b1..An AHB bus error causes error IRQ.
2935 */
2936#define APBH_CTRL2_CLR_CH12_ERROR_STATUS(x) \
2937 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK)
2938#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK (0x20000000U)
2939#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT (29U)
2940/*! CH13_ERROR_STATUS
2941 * 0b0..An early termination from the device causes error IRQ.
2942 * 0b1..An AHB bus error causes error IRQ.
2943 */
2944#define APBH_CTRL2_CLR_CH13_ERROR_STATUS(x) \
2945 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK)
2946#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK (0x40000000U)
2947#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT (30U)
2948/*! CH14_ERROR_STATUS
2949 * 0b0..An early termination from the device causes error IRQ.
2950 * 0b1..An AHB bus error causes error IRQ.
2951 */
2952#define APBH_CTRL2_CLR_CH14_ERROR_STATUS(x) \
2953 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK)
2954#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK (0x80000000U)
2955#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT (31U)
2956/*! CH15_ERROR_STATUS
2957 * 0b0..An early termination from the device causes error IRQ.
2958 * 0b1..An AHB bus error causes error IRQ.
2959 */
2960#define APBH_CTRL2_CLR_CH15_ERROR_STATUS(x) \
2961 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK)
2962/*! @} */
2963
2964/*! @name CTRL2_TOG - AHB to APBH Bridge Control and Status Register 2 */
2965/*! @{ */
2966#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK (0x1U)
2967#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT (0U)
2968#define APBH_CTRL2_TOG_CH0_ERROR_IRQ(x) \
2969 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK)
2970#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK (0x2U)
2971#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT (1U)
2972#define APBH_CTRL2_TOG_CH1_ERROR_IRQ(x) \
2973 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK)
2974#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK (0x4U)
2975#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT (2U)
2976#define APBH_CTRL2_TOG_CH2_ERROR_IRQ(x) \
2977 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK)
2978#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK (0x8U)
2979#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT (3U)
2980#define APBH_CTRL2_TOG_CH3_ERROR_IRQ(x) \
2981 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK)
2982#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK (0x10U)
2983#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT (4U)
2984#define APBH_CTRL2_TOG_CH4_ERROR_IRQ(x) \
2985 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK)
2986#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK (0x20U)
2987#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT (5U)
2988#define APBH_CTRL2_TOG_CH5_ERROR_IRQ(x) \
2989 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK)
2990#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK (0x40U)
2991#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT (6U)
2992#define APBH_CTRL2_TOG_CH6_ERROR_IRQ(x) \
2993 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK)
2994#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK (0x80U)
2995#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT (7U)
2996#define APBH_CTRL2_TOG_CH7_ERROR_IRQ(x) \
2997 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK)
2998#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK (0x100U)
2999#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT (8U)
3000#define APBH_CTRL2_TOG_CH8_ERROR_IRQ(x) \
3001 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK)
3002#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK (0x200U)
3003#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT (9U)
3004#define APBH_CTRL2_TOG_CH9_ERROR_IRQ(x) \
3005 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK)
3006#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK (0x400U)
3007#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT (10U)
3008#define APBH_CTRL2_TOG_CH10_ERROR_IRQ(x) \
3009 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK)
3010#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK (0x800U)
3011#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT (11U)
3012#define APBH_CTRL2_TOG_CH11_ERROR_IRQ(x) \
3013 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK)
3014#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK (0x1000U)
3015#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT (12U)
3016#define APBH_CTRL2_TOG_CH12_ERROR_IRQ(x) \
3017 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK)
3018#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK (0x2000U)
3019#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT (13U)
3020#define APBH_CTRL2_TOG_CH13_ERROR_IRQ(x) \
3021 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK)
3022#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK (0x4000U)
3023#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT (14U)
3024#define APBH_CTRL2_TOG_CH14_ERROR_IRQ(x) \
3025 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK)
3026#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK (0x8000U)
3027#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT (15U)
3028#define APBH_CTRL2_TOG_CH15_ERROR_IRQ(x) \
3029 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK)
3030#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK (0x10000U)
3031#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT (16U)
3032/*! CH0_ERROR_STATUS
3033 * 0b0..An early termination from the device causes error IRQ.
3034 * 0b1..An AHB bus error causes error IRQ.
3035 */
3036#define APBH_CTRL2_TOG_CH0_ERROR_STATUS(x) \
3037 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK)
3038#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK (0x20000U)
3039#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT (17U)
3040/*! CH1_ERROR_STATUS
3041 * 0b0..An early termination from the device causes error IRQ.
3042 * 0b1..An AHB bus error causes error IRQ.
3043 */
3044#define APBH_CTRL2_TOG_CH1_ERROR_STATUS(x) \
3045 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK)
3046#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK (0x40000U)
3047#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT (18U)
3048/*! CH2_ERROR_STATUS
3049 * 0b0..An early termination from the device causes error IRQ.
3050 * 0b1..An AHB bus error causes error IRQ.
3051 */
3052#define APBH_CTRL2_TOG_CH2_ERROR_STATUS(x) \
3053 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK)
3054#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK (0x80000U)
3055#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT (19U)
3056/*! CH3_ERROR_STATUS
3057 * 0b0..An early termination from the device causes error IRQ.
3058 * 0b1..An AHB bus error causes error IRQ.
3059 */
3060#define APBH_CTRL2_TOG_CH3_ERROR_STATUS(x) \
3061 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK)
3062#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK (0x100000U)
3063#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT (20U)
3064/*! CH4_ERROR_STATUS
3065 * 0b0..An early termination from the device causes error IRQ.
3066 * 0b1..An AHB bus error causes error IRQ.
3067 */
3068#define APBH_CTRL2_TOG_CH4_ERROR_STATUS(x) \
3069 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK)
3070#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK (0x200000U)
3071#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT (21U)
3072/*! CH5_ERROR_STATUS
3073 * 0b0..An early termination from the device causes error IRQ.
3074 * 0b1..An AHB bus error causes error IRQ.
3075 */
3076#define APBH_CTRL2_TOG_CH5_ERROR_STATUS(x) \
3077 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK)
3078#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK (0x400000U)
3079#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT (22U)
3080/*! CH6_ERROR_STATUS
3081 * 0b0..An early termination from the device causes error IRQ.
3082 * 0b1..An AHB bus error causes error IRQ.
3083 */
3084#define APBH_CTRL2_TOG_CH6_ERROR_STATUS(x) \
3085 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK)
3086#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK (0x800000U)
3087#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT (23U)
3088/*! CH7_ERROR_STATUS
3089 * 0b0..An early termination from the device causes error IRQ.
3090 * 0b1..An AHB bus error causes error IRQ.
3091 */
3092#define APBH_CTRL2_TOG_CH7_ERROR_STATUS(x) \
3093 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK)
3094#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK (0x1000000U)
3095#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT (24U)
3096/*! CH8_ERROR_STATUS
3097 * 0b0..An early termination from the device causes error IRQ.
3098 * 0b1..An AHB bus error causes error IRQ.
3099 */
3100#define APBH_CTRL2_TOG_CH8_ERROR_STATUS(x) \
3101 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK)
3102#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK (0x2000000U)
3103#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT (25U)
3104/*! CH9_ERROR_STATUS
3105 * 0b0..An early termination from the device causes error IRQ.
3106 * 0b1..An AHB bus error causes error IRQ.
3107 */
3108#define APBH_CTRL2_TOG_CH9_ERROR_STATUS(x) \
3109 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK)
3110#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK (0x4000000U)
3111#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT (26U)
3112/*! CH10_ERROR_STATUS
3113 * 0b0..An early termination from the device causes error IRQ.
3114 * 0b1..An AHB bus error causes error IRQ.
3115 */
3116#define APBH_CTRL2_TOG_CH10_ERROR_STATUS(x) \
3117 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK)
3118#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK (0x8000000U)
3119#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT (27U)
3120/*! CH11_ERROR_STATUS
3121 * 0b0..An early termination from the device causes error IRQ.
3122 * 0b1..An AHB bus error causes error IRQ.
3123 */
3124#define APBH_CTRL2_TOG_CH11_ERROR_STATUS(x) \
3125 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK)
3126#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK (0x10000000U)
3127#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT (28U)
3128/*! CH12_ERROR_STATUS
3129 * 0b0..An early termination from the device causes error IRQ.
3130 * 0b1..An AHB bus error causes error IRQ.
3131 */
3132#define APBH_CTRL2_TOG_CH12_ERROR_STATUS(x) \
3133 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK)
3134#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK (0x20000000U)
3135#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT (29U)
3136/*! CH13_ERROR_STATUS
3137 * 0b0..An early termination from the device causes error IRQ.
3138 * 0b1..An AHB bus error causes error IRQ.
3139 */
3140#define APBH_CTRL2_TOG_CH13_ERROR_STATUS(x) \
3141 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK)
3142#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK (0x40000000U)
3143#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT (30U)
3144/*! CH14_ERROR_STATUS
3145 * 0b0..An early termination from the device causes error IRQ.
3146 * 0b1..An AHB bus error causes error IRQ.
3147 */
3148#define APBH_CTRL2_TOG_CH14_ERROR_STATUS(x) \
3149 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK)
3150#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK (0x80000000U)
3151#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT (31U)
3152/*! CH15_ERROR_STATUS
3153 * 0b0..An early termination from the device causes error IRQ.
3154 * 0b1..An AHB bus error causes error IRQ.
3155 */
3156#define APBH_CTRL2_TOG_CH15_ERROR_STATUS(x) \
3157 (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK)
3158/*! @} */
3159
3160/*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */
3161/*! @{ */
3162#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU)
3163#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U)
3164/*! FREEZE_CHANNEL
3165 * 0b0000000000000001..NAND0
3166 * 0b0000000000000010..NAND1
3167 * 0b0000000000000100..NAND2
3168 * 0b0000000000001000..NAND3
3169 * 0b0000000000010000..NAND4
3170 * 0b0000000000100000..NAND5
3171 * 0b0000000001000000..NAND6
3172 * 0b0000000010000000..NAND7
3173 * 0b0000000100000000..SSP
3174 */
3175#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) \
3176 (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK)
3177#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U)
3178#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U)
3179/*! RESET_CHANNEL
3180 * 0b0000000000000001..NAND0
3181 * 0b0000000000000010..NAND1
3182 * 0b0000000000000100..NAND2
3183 * 0b0000000000001000..NAND3
3184 * 0b0000000000010000..NAND4
3185 * 0b0000000000100000..NAND5
3186 * 0b0000000001000000..NAND6
3187 * 0b0000000010000000..NAND7
3188 * 0b0000000100000000..SSP
3189 */
3190#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) \
3191 (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK)
3192/*! @} */
3193
3194/*! @name CHANNEL_CTRL_SET - AHB to APBH Bridge Channel Register */
3195/*! @{ */
3196#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK (0xFFFFU)
3197#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT (0U)
3198/*! FREEZE_CHANNEL
3199 * 0b0000000000000001..NAND0
3200 * 0b0000000000000010..NAND1
3201 * 0b0000000000000100..NAND2
3202 * 0b0000000000001000..NAND3
3203 * 0b0000000000010000..NAND4
3204 * 0b0000000000100000..NAND5
3205 * 0b0000000001000000..NAND6
3206 * 0b0000000010000000..NAND7
3207 * 0b0000000100000000..SSP
3208 */
3209#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL(x) \
3210 (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT)) & \
3211 APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK)
3212#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK (0xFFFF0000U)
3213#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT (16U)
3214/*! RESET_CHANNEL
3215 * 0b0000000000000001..NAND0
3216 * 0b0000000000000010..NAND1
3217 * 0b0000000000000100..NAND2
3218 * 0b0000000000001000..NAND3
3219 * 0b0000000000010000..NAND4
3220 * 0b0000000000100000..NAND5
3221 * 0b0000000001000000..NAND6
3222 * 0b0000000010000000..NAND7
3223 * 0b0000000100000000..SSP
3224 */
3225#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL(x) \
3226 (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT)) & \
3227 APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK)
3228/*! @} */
3229
3230/*! @name CHANNEL_CTRL_CLR - AHB to APBH Bridge Channel Register */
3231/*! @{ */
3232#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK (0xFFFFU)
3233#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT (0U)
3234/*! FREEZE_CHANNEL
3235 * 0b0000000000000001..NAND0
3236 * 0b0000000000000010..NAND1
3237 * 0b0000000000000100..NAND2
3238 * 0b0000000000001000..NAND3
3239 * 0b0000000000010000..NAND4
3240 * 0b0000000000100000..NAND5
3241 * 0b0000000001000000..NAND6
3242 * 0b0000000010000000..NAND7
3243 * 0b0000000100000000..SSP
3244 */
3245#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL(x) \
3246 (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT)) & \
3247 APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK)
3248#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK (0xFFFF0000U)
3249#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT (16U)
3250/*! RESET_CHANNEL
3251 * 0b0000000000000001..NAND0
3252 * 0b0000000000000010..NAND1
3253 * 0b0000000000000100..NAND2
3254 * 0b0000000000001000..NAND3
3255 * 0b0000000000010000..NAND4
3256 * 0b0000000000100000..NAND5
3257 * 0b0000000001000000..NAND6
3258 * 0b0000000010000000..NAND7
3259 * 0b0000000100000000..SSP
3260 */
3261#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL(x) \
3262 (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT)) & \
3263 APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK)
3264/*! @} */
3265
3266/*! @name CHANNEL_CTRL_TOG - AHB to APBH Bridge Channel Register */
3267/*! @{ */
3268#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK (0xFFFFU)
3269#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT (0U)
3270/*! FREEZE_CHANNEL
3271 * 0b0000000000000001..NAND0
3272 * 0b0000000000000010..NAND1
3273 * 0b0000000000000100..NAND2
3274 * 0b0000000000001000..NAND3
3275 * 0b0000000000010000..NAND4
3276 * 0b0000000000100000..NAND5
3277 * 0b0000000001000000..NAND6
3278 * 0b0000000010000000..NAND7
3279 * 0b0000000100000000..SSP
3280 */
3281#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL(x) \
3282 (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT)) & \
3283 APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK)
3284#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK (0xFFFF0000U)
3285#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT (16U)
3286/*! RESET_CHANNEL
3287 * 0b0000000000000001..NAND0
3288 * 0b0000000000000010..NAND1
3289 * 0b0000000000000100..NAND2
3290 * 0b0000000000001000..NAND3
3291 * 0b0000000000010000..NAND4
3292 * 0b0000000000100000..NAND5
3293 * 0b0000000001000000..NAND6
3294 * 0b0000000010000000..NAND7
3295 * 0b0000000100000000..SSP
3296 */
3297#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL(x) \
3298 (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT)) & \
3299 APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK)
3300/*! @} */
3301
3302/*! @name DEVSEL - AHB to APBH DMA Device Assignment Register */
3303/*! @{ */
3304#define APBH_DEVSEL_CH0_MASK (0x3U)
3305#define APBH_DEVSEL_CH0_SHIFT (0U)
3306#define APBH_DEVSEL_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH0_SHIFT)) & APBH_DEVSEL_CH0_MASK)
3307#define APBH_DEVSEL_CH1_MASK (0xCU)
3308#define APBH_DEVSEL_CH1_SHIFT (2U)
3309#define APBH_DEVSEL_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH1_SHIFT)) & APBH_DEVSEL_CH1_MASK)
3310#define APBH_DEVSEL_CH2_MASK (0x30U)
3311#define APBH_DEVSEL_CH2_SHIFT (4U)
3312#define APBH_DEVSEL_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH2_SHIFT)) & APBH_DEVSEL_CH2_MASK)
3313#define APBH_DEVSEL_CH3_MASK (0xC0U)
3314#define APBH_DEVSEL_CH3_SHIFT (6U)
3315#define APBH_DEVSEL_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH3_SHIFT)) & APBH_DEVSEL_CH3_MASK)
3316#define APBH_DEVSEL_CH4_MASK (0x300U)
3317#define APBH_DEVSEL_CH4_SHIFT (8U)
3318#define APBH_DEVSEL_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH4_SHIFT)) & APBH_DEVSEL_CH4_MASK)
3319#define APBH_DEVSEL_CH5_MASK (0xC00U)
3320#define APBH_DEVSEL_CH5_SHIFT (10U)
3321#define APBH_DEVSEL_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH5_SHIFT)) & APBH_DEVSEL_CH5_MASK)
3322#define APBH_DEVSEL_CH6_MASK (0x3000U)
3323#define APBH_DEVSEL_CH6_SHIFT (12U)
3324#define APBH_DEVSEL_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH6_SHIFT)) & APBH_DEVSEL_CH6_MASK)
3325#define APBH_DEVSEL_CH7_MASK (0xC000U)
3326#define APBH_DEVSEL_CH7_SHIFT (14U)
3327#define APBH_DEVSEL_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH7_SHIFT)) & APBH_DEVSEL_CH7_MASK)
3328#define APBH_DEVSEL_CH8_MASK (0x30000U)
3329#define APBH_DEVSEL_CH8_SHIFT (16U)
3330#define APBH_DEVSEL_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH8_SHIFT)) & APBH_DEVSEL_CH8_MASK)
3331#define APBH_DEVSEL_CH9_MASK (0xC0000U)
3332#define APBH_DEVSEL_CH9_SHIFT (18U)
3333#define APBH_DEVSEL_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH9_SHIFT)) & APBH_DEVSEL_CH9_MASK)
3334#define APBH_DEVSEL_CH10_MASK (0x300000U)
3335#define APBH_DEVSEL_CH10_SHIFT (20U)
3336#define APBH_DEVSEL_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH10_SHIFT)) & APBH_DEVSEL_CH10_MASK)
3337#define APBH_DEVSEL_CH11_MASK (0xC00000U)
3338#define APBH_DEVSEL_CH11_SHIFT (22U)
3339#define APBH_DEVSEL_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH11_SHIFT)) & APBH_DEVSEL_CH11_MASK)
3340#define APBH_DEVSEL_CH12_MASK (0x3000000U)
3341#define APBH_DEVSEL_CH12_SHIFT (24U)
3342#define APBH_DEVSEL_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH12_SHIFT)) & APBH_DEVSEL_CH12_MASK)
3343#define APBH_DEVSEL_CH13_MASK (0xC000000U)
3344#define APBH_DEVSEL_CH13_SHIFT (26U)
3345#define APBH_DEVSEL_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH13_SHIFT)) & APBH_DEVSEL_CH13_MASK)
3346#define APBH_DEVSEL_CH14_MASK (0x30000000U)
3347#define APBH_DEVSEL_CH14_SHIFT (28U)
3348#define APBH_DEVSEL_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH14_SHIFT)) & APBH_DEVSEL_CH14_MASK)
3349#define APBH_DEVSEL_CH15_MASK (0xC0000000U)
3350#define APBH_DEVSEL_CH15_SHIFT (30U)
3351#define APBH_DEVSEL_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH15_SHIFT)) & APBH_DEVSEL_CH15_MASK)
3352/*! @} */
3353
3354/*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */
3355/*! @{ */
3356#define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U)
3357#define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U)
3358#define APBH_DMA_BURST_SIZE_CH0(x) \
3359 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK)
3360#define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU)
3361#define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U)
3362#define APBH_DMA_BURST_SIZE_CH1(x) \
3363 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK)
3364#define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U)
3365#define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U)
3366#define APBH_DMA_BURST_SIZE_CH2(x) \
3367 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK)
3368#define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U)
3369#define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U)
3370#define APBH_DMA_BURST_SIZE_CH3(x) \
3371 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK)
3372#define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U)
3373#define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U)
3374#define APBH_DMA_BURST_SIZE_CH4(x) \
3375 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK)
3376#define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U)
3377#define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U)
3378#define APBH_DMA_BURST_SIZE_CH5(x) \
3379 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK)
3380#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U)
3381#define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U)
3382#define APBH_DMA_BURST_SIZE_CH6(x) \
3383 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK)
3384#define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U)
3385#define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U)
3386#define APBH_DMA_BURST_SIZE_CH7(x) \
3387 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK)
3388#define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U)
3389#define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U)
3390/*! CH8
3391 * 0b00..BURST0
3392 * 0b01..BURST4
3393 * 0b10..BURST8
3394 */
3395#define APBH_DMA_BURST_SIZE_CH8(x) \
3396 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK)
3397#define APBH_DMA_BURST_SIZE_CH9_MASK (0xC0000U)
3398#define APBH_DMA_BURST_SIZE_CH9_SHIFT (18U)
3399#define APBH_DMA_BURST_SIZE_CH9(x) \
3400 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH9_SHIFT)) & APBH_DMA_BURST_SIZE_CH9_MASK)
3401#define APBH_DMA_BURST_SIZE_CH10_MASK (0x300000U)
3402#define APBH_DMA_BURST_SIZE_CH10_SHIFT (20U)
3403#define APBH_DMA_BURST_SIZE_CH10(x) \
3404 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH10_SHIFT)) & APBH_DMA_BURST_SIZE_CH10_MASK)
3405#define APBH_DMA_BURST_SIZE_CH11_MASK (0xC00000U)
3406#define APBH_DMA_BURST_SIZE_CH11_SHIFT (22U)
3407#define APBH_DMA_BURST_SIZE_CH11(x) \
3408 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH11_SHIFT)) & APBH_DMA_BURST_SIZE_CH11_MASK)
3409#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3000000U)
3410#define APBH_DMA_BURST_SIZE_CH12_SHIFT (24U)
3411#define APBH_DMA_BURST_SIZE_CH12(x) \
3412 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH12_SHIFT)) & APBH_DMA_BURST_SIZE_CH12_MASK)
3413#define APBH_DMA_BURST_SIZE_CH13_MASK (0xC000000U)
3414#define APBH_DMA_BURST_SIZE_CH13_SHIFT (26U)
3415#define APBH_DMA_BURST_SIZE_CH13(x) \
3416 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH13_SHIFT)) & APBH_DMA_BURST_SIZE_CH13_MASK)
3417#define APBH_DMA_BURST_SIZE_CH14_MASK (0x30000000U)
3418#define APBH_DMA_BURST_SIZE_CH14_SHIFT (28U)
3419#define APBH_DMA_BURST_SIZE_CH14(x) \
3420 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH14_SHIFT)) & APBH_DMA_BURST_SIZE_CH14_MASK)
3421#define APBH_DMA_BURST_SIZE_CH15_MASK (0xC0000000U)
3422#define APBH_DMA_BURST_SIZE_CH15_SHIFT (30U)
3423#define APBH_DMA_BURST_SIZE_CH15(x) \
3424 (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH15_SHIFT)) & APBH_DMA_BURST_SIZE_CH15_MASK)
3425/*! @} */
3426
3427/*! @name DEBUG - AHB to APBH DMA Debug Register */
3428/*! @{ */
3429#define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U)
3430#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U)
3431#define APBH_DEBUG_GPMI_ONE_FIFO(x) \
3432 (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK)
3433/*! @} */
3434
3435/*! @name CH_CURCMDAR - APBH DMA Channel n Current Command Address Register */
3436/*! @{ */
3437#define APBH_CH_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3438#define APBH_CH_CURCMDAR_CMD_ADDR_SHIFT (0U)
3439#define APBH_CH_CURCMDAR_CMD_ADDR(x) \
3440 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_CURCMDAR_CMD_ADDR_MASK)
3441/*! @} */
3442
3443/* The count of APBH_CH_CURCMDAR */
3444#define APBH_CH_CURCMDAR_COUNT (16U)
3445
3446/*! @name CH_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
3447/*! @{ */
3448#define APBH_CH_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3449#define APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT (0U)
3450#define APBH_CH_NXTCMDAR_CMD_ADDR(x) \
3451 (((uint32_t)(((uint32_t)(x)) << APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_NXTCMDAR_CMD_ADDR_MASK)
3452/*! @} */
3453
3454/* The count of APBH_CH_NXTCMDAR */
3455#define APBH_CH_NXTCMDAR_COUNT (16U)
3456
3457/*! @name CH_CMD - APBH DMA Channel n Command Register */
3458/*! @{ */
3459#define APBH_CH_CMD_COMMAND_MASK (0x3U)
3460#define APBH_CH_CMD_COMMAND_SHIFT (0U)
3461/*! COMMAND
3462 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
3463 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified
3464 * number of bytes. 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for
3465 * the specified number of bytes. 0b11..Perform any requested PIO word transfers and then perform a conditional branch
3466 * to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS
3467 * as a chain pointer if the peripheral sense line is false.
3468 */
3469#define APBH_CH_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_COMMAND_SHIFT)) & APBH_CH_CMD_COMMAND_MASK)
3470#define APBH_CH_CMD_CHAIN_MASK (0x4U)
3471#define APBH_CH_CMD_CHAIN_SHIFT (2U)
3472#define APBH_CH_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CHAIN_SHIFT)) & APBH_CH_CMD_CHAIN_MASK)
3473#define APBH_CH_CMD_IRQONCMPLT_MASK (0x8U)
3474#define APBH_CH_CMD_IRQONCMPLT_SHIFT (3U)
3475#define APBH_CH_CMD_IRQONCMPLT(x) \
3476 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_IRQONCMPLT_SHIFT)) & APBH_CH_CMD_IRQONCMPLT_MASK)
3477#define APBH_CH_CMD_NANDLOCK_MASK (0x10U)
3478#define APBH_CH_CMD_NANDLOCK_SHIFT (4U)
3479#define APBH_CH_CMD_NANDLOCK(x) \
3480 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDLOCK_SHIFT)) & APBH_CH_CMD_NANDLOCK_MASK)
3481#define APBH_CH_CMD_NANDWAIT4READY_MASK (0x20U)
3482#define APBH_CH_CMD_NANDWAIT4READY_SHIFT (5U)
3483#define APBH_CH_CMD_NANDWAIT4READY(x) \
3484 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH_CMD_NANDWAIT4READY_MASK)
3485#define APBH_CH_CMD_SEMAPHORE_MASK (0x40U)
3486#define APBH_CH_CMD_SEMAPHORE_SHIFT (6U)
3487#define APBH_CH_CMD_SEMAPHORE(x) \
3488 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_SEMAPHORE_SHIFT)) & APBH_CH_CMD_SEMAPHORE_MASK)
3489#define APBH_CH_CMD_WAIT4ENDCMD_MASK (0x80U)
3490#define APBH_CH_CMD_WAIT4ENDCMD_SHIFT (7U)
3491#define APBH_CH_CMD_WAIT4ENDCMD(x) \
3492 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH_CMD_WAIT4ENDCMD_MASK)
3493#define APBH_CH_CMD_HALTONTERMINATE_MASK (0x100U)
3494#define APBH_CH_CMD_HALTONTERMINATE_SHIFT (8U)
3495#define APBH_CH_CMD_HALTONTERMINATE(x) \
3496 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH_CMD_HALTONTERMINATE_MASK)
3497#define APBH_CH_CMD_CMDWORDS_MASK (0xF000U)
3498#define APBH_CH_CMD_CMDWORDS_SHIFT (12U)
3499#define APBH_CH_CMD_CMDWORDS(x) \
3500 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CMDWORDS_SHIFT)) & APBH_CH_CMD_CMDWORDS_MASK)
3501#define APBH_CH_CMD_XFER_COUNT_MASK (0xFFFF0000U)
3502#define APBH_CH_CMD_XFER_COUNT_SHIFT (16U)
3503#define APBH_CH_CMD_XFER_COUNT(x) \
3504 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_XFER_COUNT_SHIFT)) & APBH_CH_CMD_XFER_COUNT_MASK)
3505/*! @} */
3506
3507/* The count of APBH_CH_CMD */
3508#define APBH_CH_CMD_COUNT (16U)
3509
3510/*! @name CH_BAR - APBH DMA Channel n Buffer Address Register */
3511/*! @{ */
3512#define APBH_CH_BAR_ADDRESS_MASK (0xFFFFFFFFU)
3513#define APBH_CH_BAR_ADDRESS_SHIFT (0U)
3514#define APBH_CH_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_BAR_ADDRESS_SHIFT)) & APBH_CH_BAR_ADDRESS_MASK)
3515/*! @} */
3516
3517/* The count of APBH_CH_BAR */
3518#define APBH_CH_BAR_COUNT (16U)
3519
3520/*! @name CH_SEMA - APBH DMA Channel n Semaphore Register */
3521/*! @{ */
3522#define APBH_CH_SEMA_INCREMENT_SEMA_MASK (0xFFU)
3523#define APBH_CH_SEMA_INCREMENT_SEMA_SHIFT (0U)
3524#define APBH_CH_SEMA_INCREMENT_SEMA(x) \
3525 (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH_SEMA_INCREMENT_SEMA_MASK)
3526#define APBH_CH_SEMA_PHORE_MASK (0xFF0000U)
3527#define APBH_CH_SEMA_PHORE_SHIFT (16U)
3528#define APBH_CH_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_PHORE_SHIFT)) & APBH_CH_SEMA_PHORE_MASK)
3529/*! @} */
3530
3531/* The count of APBH_CH_SEMA */
3532#define APBH_CH_SEMA_COUNT (16U)
3533
3534/*! @name CH_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
3535/*! @{ */
3536#define APBH_CH_DEBUG1_STATEMACHINE_MASK (0x1FU)
3537#define APBH_CH_DEBUG1_STATEMACHINE_SHIFT (0U)
3538/*! STATEMACHINE
3539 * 0b00000..This is the idle state of the DMA state machine.
3540 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
3541 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
3542 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
3543 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
3544 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
3545 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the
3546 * PIO words when PIO count is greater than 1.
3547 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
3548 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on
3549 * the APB. 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to
3550 * complete. 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter
3551 * accepts the request from this channel. 0b01101..During DMA Read transfers, the state machine waits in this state
3552 * until the AHB master arbiter accepts the request from this channel. 0b01110..Upon completion of the DMA transfers,
3553 * this state checks the value of the Chain bit and branches accordingly. 0b01111..The state machine goes to this state
3554 * after the DMA transfers are complete, and determines what step to take next. 0b10100..When a terminate signal is set,
3555 * the state machine enters this state until the current AHB transfer is completed. 0b10101..When the Wait for Command
3556 * End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
3557 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write
3558 * to the AHB memory space. 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters
3559 * this state and effectively halts. A channel reset is required to exit this state 0b11110..If the Chain bit is a 0,
3560 * the state machine enters this state and effectively halts. 0b11111..When the NAND Wait for Ready bit is set, the
3561 * state machine enters this state until the GPMI device indicates that the external device is ready.
3562 */
3563#define APBH_CH_DEBUG1_STATEMACHINE(x) \
3564 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH_DEBUG1_STATEMACHINE_MASK)
3565#define APBH_CH_DEBUG1_RSVD1_MASK (0xFFFE0U)
3566#define APBH_CH_DEBUG1_RSVD1_SHIFT (5U)
3567#define APBH_CH_DEBUG1_RSVD1(x) \
3568 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RSVD1_SHIFT)) & APBH_CH_DEBUG1_RSVD1_MASK)
3569#define APBH_CH_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
3570#define APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
3571#define APBH_CH_DEBUG1_WR_FIFO_FULL(x) \
3572 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_FULL_MASK)
3573#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
3574#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
3575#define APBH_CH_DEBUG1_WR_FIFO_EMPTY(x) \
3576 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK)
3577#define APBH_CH_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
3578#define APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
3579#define APBH_CH_DEBUG1_RD_FIFO_FULL(x) \
3580 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_FULL_MASK)
3581#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
3582#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
3583#define APBH_CH_DEBUG1_RD_FIFO_EMPTY(x) \
3584 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK)
3585#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
3586#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
3587#define APBH_CH_DEBUG1_NEXTCMDADDRVALID(x) \
3588 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK)
3589#define APBH_CH_DEBUG1_LOCK_MASK (0x2000000U)
3590#define APBH_CH_DEBUG1_LOCK_SHIFT (25U)
3591#define APBH_CH_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_LOCK_SHIFT)) & APBH_CH_DEBUG1_LOCK_MASK)
3592#define APBH_CH_DEBUG1_READY_MASK (0x4000000U)
3593#define APBH_CH_DEBUG1_READY_SHIFT (26U)
3594#define APBH_CH_DEBUG1_READY(x) \
3595 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_READY_SHIFT)) & APBH_CH_DEBUG1_READY_MASK)
3596#define APBH_CH_DEBUG1_SENSE_MASK (0x8000000U)
3597#define APBH_CH_DEBUG1_SENSE_SHIFT (27U)
3598#define APBH_CH_DEBUG1_SENSE(x) \
3599 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_SENSE_SHIFT)) & APBH_CH_DEBUG1_SENSE_MASK)
3600#define APBH_CH_DEBUG1_END_MASK (0x10000000U)
3601#define APBH_CH_DEBUG1_END_SHIFT (28U)
3602#define APBH_CH_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_END_SHIFT)) & APBH_CH_DEBUG1_END_MASK)
3603#define APBH_CH_DEBUG1_KICK_MASK (0x20000000U)
3604#define APBH_CH_DEBUG1_KICK_SHIFT (29U)
3605#define APBH_CH_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_KICK_SHIFT)) & APBH_CH_DEBUG1_KICK_MASK)
3606#define APBH_CH_DEBUG1_BURST_MASK (0x40000000U)
3607#define APBH_CH_DEBUG1_BURST_SHIFT (30U)
3608#define APBH_CH_DEBUG1_BURST(x) \
3609 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_BURST_SHIFT)) & APBH_CH_DEBUG1_BURST_MASK)
3610#define APBH_CH_DEBUG1_REQ_MASK (0x80000000U)
3611#define APBH_CH_DEBUG1_REQ_SHIFT (31U)
3612#define APBH_CH_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_REQ_SHIFT)) & APBH_CH_DEBUG1_REQ_MASK)
3613/*! @} */
3614
3615/* The count of APBH_CH_DEBUG1 */
3616#define APBH_CH_DEBUG1_COUNT (16U)
3617
3618/*! @name CH_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
3619/*! @{ */
3620#define APBH_CH_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
3621#define APBH_CH_DEBUG2_AHB_BYTES_SHIFT (0U)
3622#define APBH_CH_DEBUG2_AHB_BYTES(x) \
3623 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH_DEBUG2_AHB_BYTES_MASK)
3624#define APBH_CH_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
3625#define APBH_CH_DEBUG2_APB_BYTES_SHIFT (16U)
3626#define APBH_CH_DEBUG2_APB_BYTES(x) \
3627 (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH_DEBUG2_APB_BYTES_MASK)
3628/*! @} */
3629
3630/* The count of APBH_CH_DEBUG2 */
3631#define APBH_CH_DEBUG2_COUNT (16U)
3632
3633/*! @name VERSION - APBH Bridge Version Register */
3634/*! @{ */
3635#define APBH_VERSION_STEP_MASK (0xFFFFU)
3636#define APBH_VERSION_STEP_SHIFT (0U)
3637#define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK)
3638#define APBH_VERSION_MINOR_MASK (0xFF0000U)
3639#define APBH_VERSION_MINOR_SHIFT (16U)
3640#define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK)
3641#define APBH_VERSION_MAJOR_MASK (0xFF000000U)
3642#define APBH_VERSION_MAJOR_SHIFT (24U)
3643#define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK)
3644/*! @} */
3645
3646/*!
3647 * @}
3648 */ /* end of group APBH_Register_Masks */
3649
3650/* APBH - Peripheral instance base addresses */
3651/** Peripheral APBH base address */
3652#define APBH_BASE (0x33000000u)
3653/** Peripheral APBH base pointer */
3654#define APBH ((APBH_Type *)APBH_BASE)
3655/** Array initializer of APBH peripheral base addresses */
3656#define APBH_BASE_ADDRS \
3657 { \
3658 APBH_BASE \
3659 }
3660/** Array initializer of APBH peripheral base pointers */
3661#define APBH_BASE_PTRS \
3662 { \
3663 APBH \
3664 }
3665/** Interrupt vectors for the APBH peripheral type */
3666#define APBH_IRQS \
3667 { \
3668 APBHDMA_IRQn \
3669 }
3670
3671/*!
3672 * @}
3673 */ /* end of group APBH_Peripheral_Access_Layer */
3674
3675/* ----------------------------------------------------------------------------
3676 -- ASRC Peripheral Access Layer
3677 ---------------------------------------------------------------------------- */
3678
3679/*!
3680 * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer
3681 * @{
3682 */
3683
3684/** ASRC - Register Layout Typedef */
3685typedef struct
3686{
3687 __O uint32_t WRFIFO[4]; /**< ASRC Input Write FIFO, array offset: 0x0, array step: 0x4 */
3688 __I uint32_t RDFIFO[4]; /**< ASRC Output Read FIFO, array offset: 0x10, array step: 0x4 */
3689 __IO uint32_t CTX_CTRL[4]; /**< ASRC Context Control, array offset: 0x20, array step: 0x4 */
3690 __IO uint32_t CTX_CTRL_EXT1[4]; /**< ASRC Context Control Extended 1, array offset: 0x30, array step: 0x4 */
3691 __IO uint32_t CTX_CTRL_EXT2[4]; /**< ASRC Context Control Extended 2, array offset: 0x40, array step: 0x4 */
3692 __IO uint32_t CTRL_IN_ACCESS[4]; /**< ASRC Control Input Access, array offset: 0x50, array step: 0x4 */
3693 __IO uint32_t PROC_CTRL_SLOT0_R0[4]; /**< ASRC Datapath Processor Control Slot0 Register0, array offset: 0x60, array
3694 step: 0x4 */
3695 __IO uint32_t PROC_CTRL_SLOT0_R1[4]; /**< ASRC Datapath Processor Control Slot0 Register1, array offset: 0x70, array
3696 step: 0x4 */
3697 __IO uint32_t PROC_CTRL_SLOT0_R2[4]; /**< ASRC Datapath Processor Control Slot0 Register2, array offset: 0x80, array
3698 step: 0x4 */
3699 __IO uint32_t PROC_CTRL_SLOT0_R3[4]; /**< ASRC Datapath Processor Control Slot0 Register3, array offset: 0x90, array
3700 step: 0x4 */
3701 __IO uint32_t PROC_CTRL_SLOT1_R0[4]; /**< ASRC Datapath Processor Control Slot1 Register0, array offset: 0xA0, array
3702 step: 0x4 */
3703 __IO uint32_t PROC_CTRL_SLOT1_R1[4]; /**< ASRC Datapath Processor Control SLOT1 Register1, array offset: 0xB0, array
3704 step: 0x4 */
3705 __IO uint32_t PROC_CTRL_SLOT1_R2[4]; /**< ASRC Datapath Processor Control SLOT1 Register2, array offset: 0xC0, array
3706 step: 0x4 */
3707 __IO uint32_t PROC_CTRL_SLOT1_R3[4]; /**< ASRC Datapath Processor Control SLOT1 Register3, array offset: 0xD0, array
3708 step: 0x4 */
3709 __IO uint32_t CTX_OUT_CTRL[4]; /**< ASRC Context Output Control, array offset: 0xE0, array step: 0x4 */
3710 __IO uint32_t CTRL_OUT_ACCESS[4]; /**< ASRC Control Output Access, array offset: 0xF0, array step: 0x4 */
3711 __I uint32_t SAMPLE_FIFO_STATUS[4]; /**< ASRC Sample FIFO Status, array offset: 0x100, array step: 0x4 */
3712 struct
3713 { /* offset: 0x110, array step: 0x8 */
3714 __IO uint32_t RS_RATIO_LOW; /**< ASRC Resampling Ratio Low, array offset: 0x110, array step: 0x8 */
3715 __IO uint32_t RS_RATIO_HIGH; /**< ASRC Resampling Ratio High, array offset: 0x114, array step: 0x8 */
3716 } RS_RATIO_LOW[4];
3717 __IO uint32_t RS_UPDATE_CTRL[4]; /**< ASRC Resampling Ratio Update Control, array offset: 0x130, array step: 0x4 */
3718 __IO uint32_t RS_UPDATE_RATE[4]; /**< ASRC Resampling Ratio Update Rate, array offset: 0x140, array step: 0x4 */
3719 __IO uint32_t RS_CT_LOW; /**< ASRC Resampling Center Tap Coefficient Low, offset: 0x150 */
3720 __IO uint32_t RS_CT_HIGH; /**< ASRC Resampling Center Tap Coefficient High, offset: 0x154 */
3721 uint8_t RESERVED_0[8];
3722 __IO uint32_t PRE_COEFF_FIFO[4]; /**< ASRC Prefilter Coefficient FIFO, array offset: 0x160, array step: 0x4 */
3723 __O uint32_t CTX_RS_COEFF_MEM; /**< ASRC Context Resampling Coefficient Memory, offset: 0x170 */
3724 __IO uint32_t CTX_RS_COEFF_CTRL; /**< ASRC Context Resampling Coefficient Control, offset: 0x174 */
3725 __IO uint32_t IRQ_CTRL; /**< ASRC Interrupt Control, offset: 0x178 */
3726 __IO uint32_t IRQ_FLAGS; /**< ASRC Interrupt Status Flags, offset: 0x17C */
3727 __IO uint32_t CHANNEL_STATUS_0[4]; /**< ASRC Channel Status 0, array offset: 0x180, array step: 0x4 */
3728 __IO uint32_t CHANNEL_STATUS_1[4]; /**< ASRC Channel Status 1, array offset: 0x190, array step: 0x4 */
3729 __IO uint32_t CHANNEL_STATUS_2[4]; /**< ASRC Channel Status 2, array offset: 0x1A0, array step: 0x4 */
3730 __IO uint32_t CHANNEL_STATUS_3[4]; /**< ASRC Channel Status 3, array offset: 0x1B0, array step: 0x4 */
3731 __IO uint32_t CHANNEL_STATUS_4[4]; /**< ASRC Channel Status 4, array offset: 0x1C0, array step: 0x4 */
3732 __IO uint32_t CHANNEL_STATUS_5[4]; /**< ASRC Channel Status 5, array offset: 0x1D0, array step: 0x4 */
3733} ASRC_Type;
3734
3735/* ----------------------------------------------------------------------------
3736 -- ASRC Register Masks
3737 ---------------------------------------------------------------------------- */
3738
3739/*!
3740 * @addtogroup ASRC_Register_Masks ASRC Register Masks
3741 * @{
3742 */
3743
3744/*! @name WRFIFO - ASRC Input Write FIFO */
3745/*! @{ */
3746#define ASRC_WRFIFO_CTX_WR_DATA_MASK (0xFFFFFFFFU)
3747#define ASRC_WRFIFO_CTX_WR_DATA_SHIFT (0U)
3748#define ASRC_WRFIFO_CTX_WR_DATA(x) \
3749 (((uint32_t)(((uint32_t)(x)) << ASRC_WRFIFO_CTX_WR_DATA_SHIFT)) & ASRC_WRFIFO_CTX_WR_DATA_MASK)
3750/*! @} */
3751
3752/* The count of ASRC_WRFIFO */
3753#define ASRC_WRFIFO_COUNT (4U)
3754
3755/*! @name RDFIFO - ASRC Output Read FIFO */
3756/*! @{ */
3757#define ASRC_RDFIFO_CTX_RD_DATA_MASK (0xFFFFFFFFU)
3758#define ASRC_RDFIFO_CTX_RD_DATA_SHIFT (0U)
3759#define ASRC_RDFIFO_CTX_RD_DATA(x) \
3760 (((uint32_t)(((uint32_t)(x)) << ASRC_RDFIFO_CTX_RD_DATA_SHIFT)) & ASRC_RDFIFO_CTX_RD_DATA_MASK)
3761/*! @} */
3762
3763/* The count of ASRC_RDFIFO */
3764#define ASRC_RDFIFO_COUNT (4U)
3765
3766/*! @name CTX_CTRL - ASRC Context Control */
3767/*! @{ */
3768#define ASRC_CTX_CTRL_NUM_CH_EN_MASK (0x1FU)
3769#define ASRC_CTX_CTRL_NUM_CH_EN_SHIFT (0U)
3770#define ASRC_CTX_CTRL_NUM_CH_EN(x) \
3771 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_NUM_CH_EN_SHIFT)) & ASRC_CTX_CTRL_NUM_CH_EN_MASK)
3772#define ASRC_CTX_CTRL_SIGN_IN_MASK (0x40U)
3773#define ASRC_CTX_CTRL_SIGN_IN_SHIFT (6U)
3774/*! SIGN_IN - Input Data Sign
3775 * 0b0..Signed Format
3776 * 0b1..Unsigned Format
3777 */
3778#define ASRC_CTX_CTRL_SIGN_IN(x) \
3779 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_SIGN_IN_SHIFT)) & ASRC_CTX_CTRL_SIGN_IN_MASK)
3780#define ASRC_CTX_CTRL_FLOAT_FMT_MASK (0x80U)
3781#define ASRC_CTX_CTRL_FLOAT_FMT_SHIFT (7U)
3782/*! FLOAT_FMT - Context Input Floating Point Format
3783 * 0b0..Integer Format
3784 * 0b1..Single Precision Floating Point Format
3785 */
3786#define ASRC_CTX_CTRL_FLOAT_FMT(x) \
3787 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_FLOAT_FMT_SHIFT)) & ASRC_CTX_CTRL_FLOAT_FMT_MASK)
3788#define ASRC_CTX_CTRL_BITS_PER_SAMPLE_MASK (0x300U)
3789#define ASRC_CTX_CTRL_BITS_PER_SAMPLE_SHIFT (8U)
3790/*! BITS_PER_SAMPLE - Number of Bits Per Audio Sample
3791 * 0b00..16-bits Per Sample
3792 * 0b01..20-bits Per Sample
3793 * 0b10..24-bits Per Sample
3794 * 0b11..32-bits Per Sample
3795 */
3796#define ASRC_CTX_CTRL_BITS_PER_SAMPLE(x) \
3797 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_BITS_PER_SAMPLE_SHIFT)) & ASRC_CTX_CTRL_BITS_PER_SAMPLE_MASK)
3798#define ASRC_CTX_CTRL_BIT_REV_MASK (0x400U)
3799#define ASRC_CTX_CTRL_BIT_REV_SHIFT (10U)
3800/*! BIT_REV - Sample Bit Reversal
3801 * 0b0..Keep Input Ordering
3802 * 0b1..Reverse Bit Ordering
3803 */
3804#define ASRC_CTX_CTRL_BIT_REV(x) \
3805 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_BIT_REV_SHIFT)) & ASRC_CTX_CTRL_BIT_REV_MASK)
3806#define ASRC_CTX_CTRL_SAMPLE_POSITION_MASK (0xF800U)
3807#define ASRC_CTX_CTRL_SAMPLE_POSITION_SHIFT (11U)
3808#define ASRC_CTX_CTRL_SAMPLE_POSITION(x) \
3809 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_SAMPLE_POSITION_SHIFT)) & ASRC_CTX_CTRL_SAMPLE_POSITION_MASK)
3810#define ASRC_CTX_CTRL_FIFO_WTMK_MASK (0x7F0000U)
3811#define ASRC_CTX_CTRL_FIFO_WTMK_SHIFT (16U)
3812#define ASRC_CTX_CTRL_FIFO_WTMK(x) \
3813 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_FIFO_WTMK_SHIFT)) & ASRC_CTX_CTRL_FIFO_WTMK_MASK)
3814#define ASRC_CTX_CTRL_FWMDE_MASK (0x10000000U)
3815#define ASRC_CTX_CTRL_FWMDE_SHIFT (28U)
3816/*! FWMDE - FIFO Watermark DMA Enable
3817 * 0b0..Input DMA Requests Not Enabled for This Context
3818 * 0b1..Input DMA Requests Enabled for This Context
3819 */
3820#define ASRC_CTX_CTRL_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_FWMDE_SHIFT)) & ASRC_CTX_CTRL_FWMDE_MASK)
3821#define ASRC_CTX_CTRL_RUN_STOP_MASK (0x20000000U)
3822#define ASRC_CTX_CTRL_RUN_STOP_SHIFT (29U)
3823#define ASRC_CTX_CTRL_RUN_STOP(x) \
3824 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_RUN_STOP_SHIFT)) & ASRC_CTX_CTRL_RUN_STOP_MASK)
3825#define ASRC_CTX_CTRL_RUN_EN_MASK (0x80000000U)
3826#define ASRC_CTX_CTRL_RUN_EN_SHIFT (31U)
3827#define ASRC_CTX_CTRL_RUN_EN(x) \
3828 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_RUN_EN_SHIFT)) & ASRC_CTX_CTRL_RUN_EN_MASK)
3829/*! @} */
3830
3831/* The count of ASRC_CTX_CTRL */
3832#define ASRC_CTX_CTRL_COUNT (4U)
3833
3834/*! @name CTX_CTRL_EXT1 - ASRC Context Control Extended 1 */
3835/*! @{ */
3836#define ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_MASK (0x3U)
3837#define ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_SHIFT (0U)
3838/*! PF_INIT_MODE - Prefilter Initialization Mode
3839 * 0b00..Do not pre-fill any prefilter taps. The first sample written to the ASRC corresponds to the highest index
3840 * prefilter filter tap. 0b01..Replicate the first sample to fill the right half of the prefilter. 0b10..Zero fill the
3841 * right half of the prefilter. 0b11..N/A
3842 */
3843#define ASRC_CTX_CTRL_EXT1_PF_INIT_MODE(x) \
3844 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_INIT_MODE_MASK)
3845#define ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_MASK (0xCU)
3846#define ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_SHIFT (2U)
3847/*! RS_INIT_MODE - Resampler Initialization Mode
3848 * 0b00..Do not pre-fill any resampler taps. The first sample output from the prefilter corresponds to the highest
3849 * index resampling filter tap. 0b01..Replicate the first prefilter output sample to fill the right half of the
3850 * resampler. 0b10..Fill the right half of the re-sampler with zeros. 0b11..N/A
3851 */
3852#define ASRC_CTX_CTRL_EXT1_RS_INIT_MODE(x) \
3853 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_RS_INIT_MODE_MASK)
3854#define ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_MASK (0x10U)
3855#define ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_SHIFT (4U)
3856/*! PF_STOP_MODE - Pre-Filter Stop Mode
3857 * 0b0..Replicate the last sample input to the ASRC_WRFIFO for the left-half of the pre-filter on RUN_STOP.
3858 * 0b1..Zero-Fill the left-half of the pre-filter on RUN_STOP.
3859 */
3860#define ASRC_CTX_CTRL_EXT1_PF_STOP_MODE(x) \
3861 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_STOP_MODE_MASK)
3862#define ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_MASK (0x20U)
3863#define ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_SHIFT (5U)
3864/*! RS_STOP_MODE - Resampler Stop Mode
3865 * 0b0..Replicate the final prefilter output for the left-half of the resampler on RUN_STOP.
3866 * 0b1..Zero-Fill the left-half of the resampler on RUN_STOP.
3867 */
3868#define ASRC_CTX_CTRL_EXT1_RS_STOP_MODE(x) \
3869 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_RS_STOP_MODE_MASK)
3870#define ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_MASK (0x40U)
3871#define ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_SHIFT (6U)
3872/*! PF_BYPASS_MODE - Prefilter Bypass Mode
3873 * 0b0..Run the prefilter in normal operation.
3874 * 0b1..Run the prefilter in bypass mode.
3875 */
3876#define ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE(x) \
3877 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_PF_BYPASS_MODE_MASK)
3878#define ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_MASK (0x80U)
3879#define ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_SHIFT (7U)
3880/*! RS_BYPASS_MODE - Resampler Bypass Mode
3881 * 0b0..Run the resampler in normal operation.
3882 * 0b1..Run the resampler in bypass mode.
3883 */
3884#define ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE(x) \
3885 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_SHIFT)) & ASRC_CTX_CTRL_EXT1_RS_BYPASS_MODE_MASK)
3886#define ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_MASK (0x100U)
3887#define ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_SHIFT (8U)
3888/*! PF_TWO_STAGE_EN - Prefilter Two-Stage Enable
3889 * 0b0..The pre-filter will run in single stage mode (ST1 only)
3890 * 0b1..The pre-filter will run in two stage mode (ST1 and ST2)
3891 */
3892#define ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN(x) \
3893 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_SHIFT)) & \
3894 ASRC_CTX_CTRL_EXT1_PF_TWO_STAGE_EN_MASK)
3895#define ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_MASK (0x200U)
3896#define ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_SHIFT (9U)
3897/*! PF_ST1_WB_FLOAT - Prefilter Stage1 Writeback Floating Point
3898 * 0b0..The pre-filter stage1 results are stored in 32-bit integer format.
3899 * 0b1..The pre-filter stage1 results are stored in 32-bit floating point format.
3900 */
3901#define ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT(x) \
3902 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_SHIFT)) & \
3903 ASRC_CTX_CTRL_EXT1_PF_ST1_WB_FLOAT_MASK)
3904#define ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_MASK (0xFF0000U)
3905#define ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_SHIFT (16U)
3906#define ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR(x) \
3907 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_SHIFT)) & \
3908 ASRC_CTX_CTRL_EXT1_PF_EXPANSION_FACTOR_MASK)
3909#define ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_MASK (0x1000000U)
3910#define ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_SHIFT (24U)
3911#define ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST(x) \
3912 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_SHIFT)) & \
3913 ASRC_CTX_CTRL_EXT1_PF_COEFF_MEM_RST_MASK)
3914#define ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_MASK (0x2000000U)
3915#define ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_SHIFT (25U)
3916#define ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR(x) \
3917 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_SHIFT)) & \
3918 ASRC_CTX_CTRL_EXT1_PF_COEFF_STAGE_WR_MASK)
3919/*! @} */
3920
3921/* The count of ASRC_CTX_CTRL_EXT1 */
3922#define ASRC_CTX_CTRL_EXT1_COUNT (4U)
3923
3924/*! @name CTX_CTRL_EXT2 - ASRC Context Control Extended 2 */
3925/*! @{ */
3926#define ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_MASK (0x1FFU)
3927#define ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_SHIFT (0U)
3928#define ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS(x) \
3929 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_SHIFT)) & ASRC_CTX_CTRL_EXT2_ST1_NUM_TAPS_MASK)
3930#define ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_MASK (0x1FF0000U)
3931#define ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_SHIFT (16U)
3932#define ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS(x) \
3933 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_SHIFT)) & ASRC_CTX_CTRL_EXT2_ST2_NUM_TAPS_MASK)
3934/*! @} */
3935
3936/* The count of ASRC_CTX_CTRL_EXT2 */
3937#define ASRC_CTX_CTRL_EXT2_COUNT (4U)
3938
3939/*! @name CTRL_IN_ACCESS - ASRC Control Input Access */
3940/*! @{ */
3941#define ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_MASK (0x3FU)
3942#define ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_SHIFT (0U)
3943#define ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH(x) \
3944 (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_SHIFT)) & ASRC_CTRL_IN_ACCESS_ACCESS_LENGTH_MASK)
3945#define ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_MASK (0x3F00U)
3946#define ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_SHIFT (8U)
3947#define ASRC_CTRL_IN_ACCESS_GROUP_LENGTH(x) \
3948 (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_SHIFT)) & ASRC_CTRL_IN_ACCESS_GROUP_LENGTH_MASK)
3949#define ASRC_CTRL_IN_ACCESS_ITERATIONS_MASK (0x3F0000U)
3950#define ASRC_CTRL_IN_ACCESS_ITERATIONS_SHIFT (16U)
3951#define ASRC_CTRL_IN_ACCESS_ITERATIONS(x) \
3952 (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_IN_ACCESS_ITERATIONS_SHIFT)) & ASRC_CTRL_IN_ACCESS_ITERATIONS_MASK)
3953/*! @} */
3954
3955/* The count of ASRC_CTRL_IN_ACCESS */
3956#define ASRC_CTRL_IN_ACCESS_COUNT (4U)
3957
3958/*! @name PROC_CTRL_SLOT0_R0 - ASRC Datapath Processor Control Slot0 Register0 */
3959/*! @{ */
3960#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_MASK (0x1U)
3961#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_SHIFT (0U)
3962/*! SLOT0_EN - SLOT0 Enable
3963 * 0b0..Context SLOT0 is disabled
3964 * 0b1..Context SLOT0 is enabled
3965 */
3966#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN(x) \
3967 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_SHIFT)) & ASRC_PROC_CTRL_SLOT0_R0_SLOT0_EN_MASK)
3968#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_MASK (0x6U)
3969#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_SHIFT (1U)
3970#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM(x) \
3971 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_SHIFT)) & \
3972 ASRC_PROC_CTRL_SLOT0_R0_SLOT0_CTX_NUM_MASK)
3973#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_MASK (0x1F00U)
3974#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_SHIFT (8U)
3975/*! SLOT0_NUM_CH - SLOT0 Number of Channels
3976 * 0b00000..Context SLOT0 owns 1 of 8 channels
3977 * 0b00001..Context SLOT0 owns 2 of 8 channels
3978 * 0b00010..Context SLOT0 owns 3 of 8 channels
3979 * 0b00011-0b00111..Context SLOT0 owns N of 8 channels
3980 */
3981#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH(x) \
3982 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_SHIFT)) & \
3983 ASRC_PROC_CTRL_SLOT0_R0_SLOT0_NUM_CH_MASK)
3984#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_MASK (0x1F0000U)
3985#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_SHIFT (16U)
3986#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH(x) \
3987 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_SHIFT)) & \
3988 ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MIN_CH_MASK)
3989#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_MASK (0x1F000000U)
3990#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_SHIFT (24U)
3991#define ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH(x) \
3992 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_SHIFT)) & \
3993 ASRC_PROC_CTRL_SLOT0_R0_SLOT0_MAX_CH_MASK)
3994/*! @} */
3995
3996/* The count of ASRC_PROC_CTRL_SLOT0_R0 */
3997#define ASRC_PROC_CTRL_SLOT0_R0_COUNT (4U)
3998
3999/*! @name PROC_CTRL_SLOT0_R1 - ASRC Datapath Processor Control Slot0 Register1 */
4000/*! @{ */
4001#define ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_MASK (0x1FFFU)
4002#define ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_SHIFT (0U)
4003#define ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP(x) \
4004 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_SHIFT)) & \
4005 ASRC_PROC_CTRL_SLOT0_R1_SLOT0_ST1_CHANxEXP_MASK)
4006/*! @} */
4007
4008/* The count of ASRC_PROC_CTRL_SLOT0_R1 */
4009#define ASRC_PROC_CTRL_SLOT0_R1_COUNT (4U)
4010
4011/*! @name PROC_CTRL_SLOT0_R2 - ASRC Datapath Processor Control Slot0 Register2 */
4012/*! @{ */
4013#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_MASK (0x1FFFU)
4014#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_SHIFT (0U)
4015#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR(x) \
4016 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_SHIFT)) & \
4017 ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_ST_ADDR_MASK)
4018#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_MASK (0x1FFF0000U)
4019#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_SHIFT (16U)
4020#define ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC(x) \
4021 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_SHIFT)) & \
4022 ASRC_PROC_CTRL_SLOT0_R2_SLOT0_ST1_MEM_ALLOC_MASK)
4023/*! @} */
4024
4025/* The count of ASRC_PROC_CTRL_SLOT0_R2 */
4026#define ASRC_PROC_CTRL_SLOT0_R2_COUNT (4U)
4027
4028/*! @name PROC_CTRL_SLOT0_R3 - ASRC Datapath Processor Control Slot0 Register3 */
4029/*! @{ */
4030#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_MASK (0x1FFFU)
4031#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_SHIFT (0U)
4032#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR(x) \
4033 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_SHIFT)) & \
4034 ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_ST_ADDR_MASK)
4035#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_MASK (0x1FFF0000U)
4036#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_SHIFT (16U)
4037#define ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC(x) \
4038 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_SHIFT)) & \
4039 ASRC_PROC_CTRL_SLOT0_R3_SLOT0_ST2_MEM_ALLOC_MASK)
4040/*! @} */
4041
4042/* The count of ASRC_PROC_CTRL_SLOT0_R3 */
4043#define ASRC_PROC_CTRL_SLOT0_R3_COUNT (4U)
4044
4045/*! @name PROC_CTRL_SLOT1_R0 - ASRC Datapath Processor Control Slot1 Register0 */
4046/*! @{ */
4047#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_MASK (0x1U)
4048#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_SHIFT (0U)
4049/*! SLOT1_EN - SLOT1 Enable
4050 * 0b0..Context SLOT1 is disabled
4051 * 0b1..Context SLOT1 is enabled
4052 */
4053#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN(x) \
4054 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_SHIFT)) & ASRC_PROC_CTRL_SLOT1_R0_SLOT1_EN_MASK)
4055#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_MASK (0x6U)
4056#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_SHIFT (1U)
4057#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM(x) \
4058 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_SHIFT)) & \
4059 ASRC_PROC_CTRL_SLOT1_R0_SLOT1_CTX_NUM_MASK)
4060#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_MASK (0x1F00U)
4061#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_SHIFT (8U)
4062/*! SLOT1_NUM_CH - SLOT1 Number of Channels
4063 * 0b00000..Context SLOT1 owns 1 of 8 channels
4064 * 0b00001..Context SLOT1 owns 2 of 8 channels
4065 * 0b00010..Context SLOT1 owns 3 of 8 channels
4066 * 0b00011-0b00111..Context SLOT1 owns N of 8 channels
4067 */
4068#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH(x) \
4069 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_SHIFT)) & \
4070 ASRC_PROC_CTRL_SLOT1_R0_SLOT1_NUM_CH_MASK)
4071#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_MASK (0x1F0000U)
4072#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_SHIFT (16U)
4073#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH(x) \
4074 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_SHIFT)) & \
4075 ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MIN_CH_MASK)
4076#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_MASK (0x1F000000U)
4077#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_SHIFT (24U)
4078#define ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH(x) \
4079 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_SHIFT)) & \
4080 ASRC_PROC_CTRL_SLOT1_R0_SLOT1_MAX_CH_MASK)
4081/*! @} */
4082
4083/* The count of ASRC_PROC_CTRL_SLOT1_R0 */
4084#define ASRC_PROC_CTRL_SLOT1_R0_COUNT (4U)
4085
4086/*! @name PROC_CTRL_SLOT1_R1 - ASRC Datapath Processor Control SLOT1 Register1 */
4087/*! @{ */
4088#define ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_MASK (0x1FFFU)
4089#define ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_SHIFT (0U)
4090#define ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP(x) \
4091 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_SHIFT)) & \
4092 ASRC_PROC_CTRL_SLOT1_R1_SLOT1_ST1_CHANxEXP_MASK)
4093/*! @} */
4094
4095/* The count of ASRC_PROC_CTRL_SLOT1_R1 */
4096#define ASRC_PROC_CTRL_SLOT1_R1_COUNT (4U)
4097
4098/*! @name PROC_CTRL_SLOT1_R2 - ASRC Datapath Processor Control SLOT1 Register2 */
4099/*! @{ */
4100#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_MASK (0x1FFFU)
4101#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_SHIFT (0U)
4102#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR(x) \
4103 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_SHIFT)) & \
4104 ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_ST_ADDR_MASK)
4105#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_MASK (0x1FFF0000U)
4106#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_SHIFT (16U)
4107#define ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC(x) \
4108 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_SHIFT)) & \
4109 ASRC_PROC_CTRL_SLOT1_R2_SLOT1_ST1_MEM_ALLOC_MASK)
4110/*! @} */
4111
4112/* The count of ASRC_PROC_CTRL_SLOT1_R2 */
4113#define ASRC_PROC_CTRL_SLOT1_R2_COUNT (4U)
4114
4115/*! @name PROC_CTRL_SLOT1_R3 - ASRC Datapath Processor Control SLOT1 Register3 */
4116/*! @{ */
4117#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_MASK (0x1FFFU)
4118#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_SHIFT (0U)
4119#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR(x) \
4120 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_SHIFT)) & \
4121 ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_ST_ADDR_MASK)
4122#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_MASK (0x1FFF0000U)
4123#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_SHIFT (16U)
4124#define ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC(x) \
4125 (((uint32_t)(((uint32_t)(x)) << ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_SHIFT)) & \
4126 ASRC_PROC_CTRL_SLOT1_R3_SLOT1_ST2_MEM_ALLOC_MASK)
4127/*! @} */
4128
4129/* The count of ASRC_PROC_CTRL_SLOT1_R3 */
4130#define ASRC_PROC_CTRL_SLOT1_R3_COUNT (4U)
4131
4132/*! @name CTX_OUT_CTRL - ASRC Context Output Control */
4133/*! @{ */
4134#define ASRC_CTX_OUT_CTRL_DITHER_EN_MASK (0x1U)
4135#define ASRC_CTX_OUT_CTRL_DITHER_EN_SHIFT (0U)
4136#define ASRC_CTX_OUT_CTRL_DITHER_EN(x) \
4137 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_DITHER_EN_SHIFT)) & ASRC_CTX_OUT_CTRL_DITHER_EN_MASK)
4138#define ASRC_CTX_OUT_CTRL_IEC_EN_MASK (0x2U)
4139#define ASRC_CTX_OUT_CTRL_IEC_EN_SHIFT (1U)
4140/*! IEC_EN - IEC60958 Bit-Field Insertion Enable
4141 * 0b0..No Data Insertion Enabled.
4142 * 0b1..IEC60958 Bit-Field Insertion Enabled.
4143 */
4144#define ASRC_CTX_OUT_CTRL_IEC_EN(x) \
4145 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_IEC_EN_SHIFT)) & ASRC_CTX_OUT_CTRL_IEC_EN_MASK)
4146#define ASRC_CTX_OUT_CTRL_IEC_V_DATA_MASK (0x4U)
4147#define ASRC_CTX_OUT_CTRL_IEC_V_DATA_SHIFT (2U)
4148#define ASRC_CTX_OUT_CTRL_IEC_V_DATA(x) \
4149 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_IEC_V_DATA_SHIFT)) & ASRC_CTX_OUT_CTRL_IEC_V_DATA_MASK)
4150#define ASRC_CTX_OUT_CTRL_SIGN_OUT_MASK (0x40U)
4151#define ASRC_CTX_OUT_CTRL_SIGN_OUT_SHIFT (6U)
4152/*! SIGN_OUT - Output Data Sign
4153 * 0b0..Signed Format
4154 * 0b1..Convert to Unsigned
4155 */
4156#define ASRC_CTX_OUT_CTRL_SIGN_OUT(x) \
4157 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_SIGN_OUT_SHIFT)) & ASRC_CTX_OUT_CTRL_SIGN_OUT_MASK)
4158#define ASRC_CTX_OUT_CTRL_FLOAT_FMT_MASK (0x80U)
4159#define ASRC_CTX_OUT_CTRL_FLOAT_FMT_SHIFT (7U)
4160/*! FLOAT_FMT - Context Output Floating Point Format
4161 * 0b0..Integer Format
4162 * 0b1..Single Precision Floating Point Format
4163 */
4164#define ASRC_CTX_OUT_CTRL_FLOAT_FMT(x) \
4165 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_FLOAT_FMT_SHIFT)) & ASRC_CTX_OUT_CTRL_FLOAT_FMT_MASK)
4166#define ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_MASK (0x300U)
4167#define ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_SHIFT (8U)
4168/*! BITS_PER_SAMPLE - Number of Bits Per Audio Sample
4169 * 0b00..16-bits Per Sample
4170 * 0b01..20-bits Per Sample
4171 * 0b10..24-bits Per Sample
4172 * 0b11..32-bits Per Sample
4173 */
4174#define ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE(x) \
4175 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_SHIFT)) & ASRC_CTX_OUT_CTRL_BITS_PER_SAMPLE_MASK)
4176#define ASRC_CTX_OUT_CTRL_BIT_REV_MASK (0x400U)
4177#define ASRC_CTX_OUT_CTRL_BIT_REV_SHIFT (10U)
4178/*! BIT_REV - Sample Bit-Reversal
4179 * 0b0..No change.
4180 * 0b1..Bit-reverse sample data.
4181 */
4182#define ASRC_CTX_OUT_CTRL_BIT_REV(x) \
4183 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_BIT_REV_SHIFT)) & ASRC_CTX_OUT_CTRL_BIT_REV_MASK)
4184#define ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_MASK (0xF800U)
4185#define ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_SHIFT (11U)
4186#define ASRC_CTX_OUT_CTRL_SAMPLE_POSITION(x) \
4187 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_SHIFT)) & ASRC_CTX_OUT_CTRL_SAMPLE_POSITION_MASK)
4188#define ASRC_CTX_OUT_CTRL_FIFO_WTMK_MASK (0x7F0000U)
4189#define ASRC_CTX_OUT_CTRL_FIFO_WTMK_SHIFT (16U)
4190#define ASRC_CTX_OUT_CTRL_FIFO_WTMK(x) \
4191 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_FIFO_WTMK_SHIFT)) & ASRC_CTX_OUT_CTRL_FIFO_WTMK_MASK)
4192#define ASRC_CTX_OUT_CTRL_FWMDE_MASK (0x10000000U)
4193#define ASRC_CTX_OUT_CTRL_FWMDE_SHIFT (28U)
4194/*! FWMDE - Output FIFO Watermark DMA Enable
4195 * 0b0..Output DMA Requests Not Enabled for This Context
4196 * 0b1..Output DMA Requests Enabled for This Context
4197 */
4198#define ASRC_CTX_OUT_CTRL_FWMDE(x) \
4199 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_OUT_CTRL_FWMDE_SHIFT)) & ASRC_CTX_OUT_CTRL_FWMDE_MASK)
4200/*! @} */
4201
4202/* The count of ASRC_CTX_OUT_CTRL */
4203#define ASRC_CTX_OUT_CTRL_COUNT (4U)
4204
4205/*! @name CTRL_OUT_ACCESS - ASRC Control Output Access */
4206/*! @{ */
4207#define ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_MASK (0x3FU)
4208#define ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_SHIFT (0U)
4209#define ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH(x) \
4210 (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_SHIFT)) & \
4211 ASRC_CTRL_OUT_ACCESS_ACCESS_LENGTH_MASK)
4212#define ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_MASK (0x3F00U)
4213#define ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_SHIFT (8U)
4214#define ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH(x) \
4215 (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_SHIFT)) & ASRC_CTRL_OUT_ACCESS_GROUP_LENGTH_MASK)
4216#define ASRC_CTRL_OUT_ACCESS_ITERATIONS_MASK (0x3F0000U)
4217#define ASRC_CTRL_OUT_ACCESS_ITERATIONS_SHIFT (16U)
4218#define ASRC_CTRL_OUT_ACCESS_ITERATIONS(x) \
4219 (((uint32_t)(((uint32_t)(x)) << ASRC_CTRL_OUT_ACCESS_ITERATIONS_SHIFT)) & ASRC_CTRL_OUT_ACCESS_ITERATIONS_MASK)
4220/*! @} */
4221
4222/* The count of ASRC_CTRL_OUT_ACCESS */
4223#define ASRC_CTRL_OUT_ACCESS_COUNT (4U)
4224
4225/*! @name SAMPLE_FIFO_STATUS - ASRC Sample FIFO Status */
4226/*! @{ */
4227#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_MASK (0x7FU)
4228#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_SHIFT (0U)
4229#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT(x) \
4230 (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_SHIFT)) & \
4231 ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_OUT_MASK)
4232#define ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_MASK (0x80U)
4233#define ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_SHIFT (7U)
4234#define ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK(x) \
4235 (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_SHIFT)) & \
4236 ASRC_SAMPLE_FIFO_STATUS_OUTFIFO_WTMK_MASK)
4237#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_MASK (0x7F0000U)
4238#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_SHIFT (16U)
4239#define ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN(x) \
4240 (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_SHIFT)) & \
4241 ASRC_SAMPLE_FIFO_STATUS_NUM_SAMPLE_GROUPS_IN_MASK)
4242#define ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_MASK (0x800000U)
4243#define ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_SHIFT (23U)
4244#define ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK(x) \
4245 (((uint32_t)(((uint32_t)(x)) << ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_SHIFT)) & \
4246 ASRC_SAMPLE_FIFO_STATUS_INFIFO_WTMK_MASK)
4247/*! @} */
4248
4249/* The count of ASRC_SAMPLE_FIFO_STATUS */
4250#define ASRC_SAMPLE_FIFO_STATUS_COUNT (4U)
4251
4252/*! @name RS_RATIO_LOW - ASRC Resampling Ratio Low */
4253/*! @{ */
4254#define ASRC_RS_RATIO_LOW_RS_RATIO_LOW_MASK (0xFFFFFFFFU)
4255#define ASRC_RS_RATIO_LOW_RS_RATIO_LOW_SHIFT (0U)
4256#define ASRC_RS_RATIO_LOW_RS_RATIO_LOW(x) \
4257 (((uint32_t)(((uint32_t)(x)) << ASRC_RS_RATIO_LOW_RS_RATIO_LOW_SHIFT)) & ASRC_RS_RATIO_LOW_RS_RATIO_LOW_MASK)
4258/*! @} */
4259
4260/* The count of ASRC_RS_RATIO_LOW */
4261#define ASRC_RS_RATIO_LOW_COUNT (4U)
4262
4263/*! @name RS_RATIO_HIGH - ASRC Resampling Ratio High */
4264/*! @{ */
4265#define ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_MASK (0xFFFU)
4266#define ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_SHIFT (0U)
4267#define ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH(x) \
4268 (((uint32_t)(((uint32_t)(x)) << ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_SHIFT)) & ASRC_RS_RATIO_HIGH_RS_RATIO_HIGH_MASK)
4269#define ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_MASK (0x80000000U)
4270#define ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_SHIFT (31U)
4271#define ASRC_RS_RATIO_HIGH_RS_RATIO_VLD(x) \
4272 (((uint32_t)(((uint32_t)(x)) << ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_SHIFT)) & ASRC_RS_RATIO_HIGH_RS_RATIO_VLD_MASK)
4273/*! @} */
4274
4275/* The count of ASRC_RS_RATIO_HIGH */
4276#define ASRC_RS_RATIO_HIGH_COUNT (4U)
4277
4278/*! @name RS_UPDATE_CTRL - ASRC Resampling Ratio Update Control */
4279/*! @{ */
4280#define ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_MASK (0xFFFFFFFFU)
4281#define ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_SHIFT (0U)
4282#define ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD(x) \
4283 (((uint32_t)(((uint32_t)(x)) << ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_SHIFT)) & ASRC_RS_UPDATE_CTRL_RS_RATIO_MOD_MASK)
4284/*! @} */
4285
4286/* The count of ASRC_RS_UPDATE_CTRL */
4287#define ASRC_RS_UPDATE_CTRL_COUNT (4U)
4288
4289/*! @name RS_UPDATE_RATE - ASRC Resampling Ratio Update Rate */
4290/*! @{ */
4291#define ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_MASK (0x7FFFFFFFU)
4292#define ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_SHIFT (0U)
4293#define ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE(x) \
4294 (((uint32_t)(((uint32_t)(x)) << ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_SHIFT)) & \
4295 ASRC_RS_UPDATE_RATE_RS_RATIO_RAMP_RATE_MASK)
4296/*! @} */
4297
4298/* The count of ASRC_RS_UPDATE_RATE */
4299#define ASRC_RS_UPDATE_RATE_COUNT (4U)
4300
4301/*! @name RS_CT_LOW - ASRC Resampling Center Tap Coefficient Low */
4302/*! @{ */
4303#define ASRC_RS_CT_LOW_RS_CT_LOW_MASK (0xFFFFFFFFU)
4304#define ASRC_RS_CT_LOW_RS_CT_LOW_SHIFT (0U)
4305#define ASRC_RS_CT_LOW_RS_CT_LOW(x) \
4306 (((uint32_t)(((uint32_t)(x)) << ASRC_RS_CT_LOW_RS_CT_LOW_SHIFT)) & ASRC_RS_CT_LOW_RS_CT_LOW_MASK)
4307/*! @} */
4308
4309/*! @name RS_CT_HIGH - ASRC Resampling Center Tap Coefficient High */
4310/*! @{ */
4311#define ASRC_RS_CT_HIGH_RS_CT_HIGH_MASK (0xFFFFFFFFU)
4312#define ASRC_RS_CT_HIGH_RS_CT_HIGH_SHIFT (0U)
4313#define ASRC_RS_CT_HIGH_RS_CT_HIGH(x) \
4314 (((uint32_t)(((uint32_t)(x)) << ASRC_RS_CT_HIGH_RS_CT_HIGH_SHIFT)) & ASRC_RS_CT_HIGH_RS_CT_HIGH_MASK)
4315/*! @} */
4316
4317/*! @name PRE_COEFF_FIFO - ASRC Prefilter Coefficient FIFO */
4318/*! @{ */
4319#define ASRC_PRE_COEFF_FIFO_COEFF_DATA_MASK (0xFFFFFFFFU)
4320#define ASRC_PRE_COEFF_FIFO_COEFF_DATA_SHIFT (0U)
4321#define ASRC_PRE_COEFF_FIFO_COEFF_DATA(x) \
4322 (((uint32_t)(((uint32_t)(x)) << ASRC_PRE_COEFF_FIFO_COEFF_DATA_SHIFT)) & ASRC_PRE_COEFF_FIFO_COEFF_DATA_MASK)
4323/*! @} */
4324
4325/* The count of ASRC_PRE_COEFF_FIFO */
4326#define ASRC_PRE_COEFF_FIFO_COUNT (4U)
4327
4328/*! @name CTX_RS_COEFF_MEM - ASRC Context Resampling Coefficient Memory */
4329/*! @{ */
4330#define ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_MASK (0xFFFFFFFFU)
4331#define ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_SHIFT (0U)
4332#define ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA(x) \
4333 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_SHIFT)) & \
4334 ASRC_CTX_RS_COEFF_MEM_RS_COEFF_WDATA_MASK)
4335/*! @} */
4336
4337/*! @name CTX_RS_COEFF_CTRL - ASRC Context Resampling Coefficient Control */
4338/*! @{ */
4339#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_MASK (0x1U)
4340#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_SHIFT (0U)
4341#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST(x) \
4342 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_SHIFT)) & \
4343 ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_PTR_RST_MASK)
4344#define ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_MASK (0x6U)
4345#define ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_SHIFT (1U)
4346/*! NUM_RES_TAPS - Number of Resampling Coefficient Taps
4347 * 0b00..32-Tap Resampling Filter
4348 * 0b01..64-Tap Resampling Filter
4349 * 0b10..128-Tap Resampling Filter
4350 * 0b11..N/A
4351 */
4352#define ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS(x) \
4353 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_SHIFT)) & \
4354 ASRC_CTX_RS_COEFF_CTRL_NUM_RES_TAPS_MASK)
4355#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_MASK (0x7FF0000U)
4356#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_SHIFT (16U)
4357#define ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR(x) \
4358 (((uint32_t)(((uint32_t)(x)) << ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_SHIFT)) & \
4359 ASRC_CTX_RS_COEFF_CTRL_RS_COEFF_ADDR_MASK)
4360/*! @} */
4361
4362/*! @name IRQ_CTRL - ASRC Interrupt Control */
4363/*! @{ */
4364#define ASRC_IRQ_CTRL_INFIFO_OVF_MASK_MASK (0xFU)
4365#define ASRC_IRQ_CTRL_INFIFO_OVF_MASK_SHIFT (0U)
4366/*! INFIFO_OVF_MASK - ASRC Input FIFO Overflow Mask
4367 * 0b0000..The INFIFO_OVF interrupt is enabled for Context 0 to 3.
4368 * 0b0001..The INFIFO_OVF interrupt is disabled for Context 0 and enabled for Context 1 to 3.
4369 * 0b0010..The INFIFO_OVF interrupt is disabled for Context 1 and enabled for Context 0, 2, and 3.
4370 * 0b0011-0b1110..The INFIFO_OVF interrupt is enabled for any context with a 1'b0 bit field.
4371 * 0b1111..The INFIFO_OVF interrupt is disabled for Context 0 to 3.
4372 */
4373#define ASRC_IRQ_CTRL_INFIFO_OVF_MASK(x) \
4374 (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_CTRL_INFIFO_OVF_MASK_SHIFT)) & ASRC_IRQ_CTRL_INFIFO_OVF_MASK_MASK)
4375#define ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_MASK (0xF0U)
4376#define ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_SHIFT (4U)
4377/*! OUTFIFO_EMPTY_RD_MASK - ASRC Output FIFO Empty Read Mask
4378 * 0b0000..The OUTFIFO_EMPTY_RD interrupt is enabled for Context 0 to 3.
4379 * 0b0001..The OUTFIFO_EMPTY_RD interrupt is disabled for Context 0 and enabled for Context 1 to 3.
4380 * 0b0010..The OUTFIFO_EMPTY_RD interrupt is disabled for Context 1 and enabled for Context 0, 2, and 3.
4381 * 0b0011-0b1110..The OUTFIFO_EMPTY_RD interrupt is enabled for any context with a 1'b0 bit field.
4382 * 0b1111..The OUTFIFO_EMPTY_RD interrupt is disabled for Context 0 to 3.
4383 */
4384#define ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK(x) \
4385 (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_SHIFT)) & \
4386 ASRC_IRQ_CTRL_OUTFIFO_EMPTY_RD_MASK_MASK)
4387#define ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_MASK (0xF00U)
4388#define ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_SHIFT (8U)
4389/*! RUN_STOP_DONE_MASK - ASRC RUN STOP DONE MASK
4390 * 0b0000..The RUN_STOP_DONE interrupt is enabled for Context 0 to 3.
4391 * 0b0001..The RUN_STOP_DONE interrupt is disabled for Context 0 and enabled for Context 1 to 3.
4392 * 0b0010..The RUN_STOP_DONE interrupt is disabled for Context 1 and enabled for Context 0, 2, and 3.
4393 * 0b0011-0b1110..The RUN_STOP_DONE interrupt is enabled for any context with a 1'b0 bit field.
4394 * 0b1111..The RUN_STOP_DONE interrupt is disabled for Context 0 to 3.
4395 */
4396#define ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK(x) \
4397 (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_SHIFT)) & ASRC_IRQ_CTRL_RUN_STOP_DONE_MASK_MASK)
4398/*! @} */
4399
4400/*! @name IRQ_FLAGS - ASRC Interrupt Status Flags */
4401/*! @{ */
4402#define ASRC_IRQ_FLAGS_INFIFO_OVF_MASK (0xFU)
4403#define ASRC_IRQ_FLAGS_INFIFO_OVF_SHIFT (0U)
4404/*! INFIFO_OVF - ASRC Input FIFO Overflow Flag
4405 * 0b0000..No INFIFO_OVF errors have been recorded.
4406 * 0b0001..The ASRC_WRFIFO0 has overflown.
4407 * 0b0010..The ASRC_WRFIFO1 has overflown.
4408 * 0b0011-0b1110..The ASRC_WRFIFOn has overflown. Where n = any bit position set to 0b1.
4409 * 0b1111..ASRC_WRFIFO0, ASRC_WRFIFO1, ASRC_WRFIFO2, and ASRC_WRFIFO3 have overflown.
4410 */
4411#define ASRC_IRQ_FLAGS_INFIFO_OVF(x) \
4412 (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_FLAGS_INFIFO_OVF_SHIFT)) & ASRC_IRQ_FLAGS_INFIFO_OVF_MASK)
4413#define ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD_MASK (0xF0U)
4414#define ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD_SHIFT (4U)
4415/*! OUTFIFO_EMPTY_RD - ASRC Output FIFO Empty Read Flag
4416 * 0b0000..No reads have been requested from an empty ASRC_RDFIFO.
4417 * 0b0001..A read has been requested from ASRC_RDFIFO0 when it was empty.
4418 * 0b0010..A read has been requested from ASRC_RDFIFO1 when it was empty.
4419 * 0b0011-0b1110..A read has been requested from ASRC_RDFIFOn when it was empty. n = any bit position with a 0b1.
4420 * 0b1111..A read has been requested from ASRC_RDFIFO0, ASRC_RDFIFO1, ASRC_RDFIFO2, and ASRC_RDFIFO3 while empty.
4421 */
4422#define ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD(x) \
4423 (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD_SHIFT)) & ASRC_IRQ_FLAGS_OUTFIFO_EMPTY_RD_MASK)
4424#define ASRC_IRQ_FLAGS_RUN_STOP_DONE_MASK (0xF00U)
4425#define ASRC_IRQ_FLAGS_RUN_STOP_DONE_SHIFT (8U)
4426/*! RUN_STOP_DONE - ASRC RUN STOP DONE FLAG
4427 * 0b0000..No RUN_STOP operations have been completed.
4428 * 0b0001..The RUN_STOP operation for Context 0 has completed.
4429 * 0b0010..The RUN_STOP operation for Context 1 has completed.
4430 * 0b0011-0b1110..The RUN_STOP operation has completed for any context with a 1'b1 bit field.
4431 * 0b1111..The RUN_STOP operation has completed for Context 0 to 3.
4432 */
4433#define ASRC_IRQ_FLAGS_RUN_STOP_DONE(x) \
4434 (((uint32_t)(((uint32_t)(x)) << ASRC_IRQ_FLAGS_RUN_STOP_DONE_SHIFT)) & ASRC_IRQ_FLAGS_RUN_STOP_DONE_MASK)
4435/*! @} */
4436
4437/*! @name CHANNEL_STATUS_0 - ASRC Channel Status 0 */
4438/*! @{ */
4439#define ASRC_CHANNEL_STATUS_0_CHN_STAT_MASK (0xFFFFFFFFU)
4440#define ASRC_CHANNEL_STATUS_0_CHN_STAT_SHIFT (0U)
4441#define ASRC_CHANNEL_STATUS_0_CHN_STAT(x) \
4442 (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_0_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_0_CHN_STAT_MASK)
4443/*! @} */
4444
4445/* The count of ASRC_CHANNEL_STATUS_0 */
4446#define ASRC_CHANNEL_STATUS_0_COUNT (4U)
4447
4448/*! @name CHANNEL_STATUS_1 - ASRC Channel Status 1 */
4449/*! @{ */
4450#define ASRC_CHANNEL_STATUS_1_CHN_STAT_MASK (0xFFFFFFFFU)
4451#define ASRC_CHANNEL_STATUS_1_CHN_STAT_SHIFT (0U)
4452#define ASRC_CHANNEL_STATUS_1_CHN_STAT(x) \
4453 (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_1_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_1_CHN_STAT_MASK)
4454/*! @} */
4455
4456/* The count of ASRC_CHANNEL_STATUS_1 */
4457#define ASRC_CHANNEL_STATUS_1_COUNT (4U)
4458
4459/*! @name CHANNEL_STATUS_2 - ASRC Channel Status 2 */
4460/*! @{ */
4461#define ASRC_CHANNEL_STATUS_2_CHN_STAT_MASK (0xFFFFFFFFU)
4462#define ASRC_CHANNEL_STATUS_2_CHN_STAT_SHIFT (0U)
4463#define ASRC_CHANNEL_STATUS_2_CHN_STAT(x) \
4464 (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_2_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_2_CHN_STAT_MASK)
4465/*! @} */
4466
4467/* The count of ASRC_CHANNEL_STATUS_2 */
4468#define ASRC_CHANNEL_STATUS_2_COUNT (4U)
4469
4470/*! @name CHANNEL_STATUS_3 - ASRC Channel Status 3 */
4471/*! @{ */
4472#define ASRC_CHANNEL_STATUS_3_CHN_STAT_MASK (0xFFFFFFFFU)
4473#define ASRC_CHANNEL_STATUS_3_CHN_STAT_SHIFT (0U)
4474#define ASRC_CHANNEL_STATUS_3_CHN_STAT(x) \
4475 (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_3_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_3_CHN_STAT_MASK)
4476/*! @} */
4477
4478/* The count of ASRC_CHANNEL_STATUS_3 */
4479#define ASRC_CHANNEL_STATUS_3_COUNT (4U)
4480
4481/*! @name CHANNEL_STATUS_4 - ASRC Channel Status 4 */
4482/*! @{ */
4483#define ASRC_CHANNEL_STATUS_4_CHN_STAT_MASK (0xFFFFFFFFU)
4484#define ASRC_CHANNEL_STATUS_4_CHN_STAT_SHIFT (0U)
4485#define ASRC_CHANNEL_STATUS_4_CHN_STAT(x) \
4486 (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_4_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_4_CHN_STAT_MASK)
4487/*! @} */
4488
4489/* The count of ASRC_CHANNEL_STATUS_4 */
4490#define ASRC_CHANNEL_STATUS_4_COUNT (4U)
4491
4492/*! @name CHANNEL_STATUS_5 - ASRC Channel Status 5 */
4493/*! @{ */
4494#define ASRC_CHANNEL_STATUS_5_CHN_STAT_MASK (0xFFFFFFFFU)
4495#define ASRC_CHANNEL_STATUS_5_CHN_STAT_SHIFT (0U)
4496#define ASRC_CHANNEL_STATUS_5_CHN_STAT(x) \
4497 (((uint32_t)(((uint32_t)(x)) << ASRC_CHANNEL_STATUS_5_CHN_STAT_SHIFT)) & ASRC_CHANNEL_STATUS_5_CHN_STAT_MASK)
4498/*! @} */
4499
4500/* The count of ASRC_CHANNEL_STATUS_5 */
4501#define ASRC_CHANNEL_STATUS_5_COUNT (4U)
4502
4503/*!
4504 * @}
4505 */ /* end of group ASRC_Register_Masks */
4506
4507/* ASRC - Peripheral instance base addresses */
4508/** Peripheral ASRC base address */
4509#define ASRC_BASE (0x300C0000u)
4510/** Peripheral ASRC base pointer */
4511#define ASRC ((ASRC_Type *)ASRC_BASE)
4512/** Array initializer of ASRC peripheral base addresses */
4513#define ASRC_BASE_ADDRS \
4514 { \
4515 ASRC_BASE \
4516 }
4517/** Array initializer of ASRC peripheral base pointers */
4518#define ASRC_BASE_PTRS \
4519 { \
4520 ASRC \
4521 }
4522
4523/*!
4524 * @}
4525 */ /* end of group ASRC_Peripheral_Access_Layer */
4526
4527/* ----------------------------------------------------------------------------
4528 -- BCH Peripheral Access Layer
4529 ---------------------------------------------------------------------------- */
4530
4531/*!
4532 * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer
4533 * @{
4534 */
4535
4536/** BCH - Register Layout Typedef */
4537typedef struct
4538{
4539 __IO uint32_t CTRL; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */
4540 __IO uint32_t CTRL_SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */
4541 __IO uint32_t CTRL_CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */
4542 __IO uint32_t CTRL_TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */
4543 __I uint32_t STATUS0; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */
4544 uint8_t RESERVED_0[12];
4545 __IO uint32_t MODE; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */
4546 uint8_t RESERVED_1[12];
4547 __IO uint32_t ENCODEPTR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */
4548 uint8_t RESERVED_2[12];
4549 __IO uint32_t DATAPTR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */
4550 uint8_t RESERVED_3[12];
4551 __IO uint32_t METAPTR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */
4552 uint8_t RESERVED_4[28];
4553 __IO uint32_t LAYOUTSELECT; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */
4554 uint8_t RESERVED_5[12];
4555 __IO uint32_t FLASH0LAYOUT0; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */
4556 uint8_t RESERVED_6[12];
4557 __IO uint32_t FLASH0LAYOUT1; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */
4558 uint8_t RESERVED_7[12];
4559 __IO uint32_t FLASH1LAYOUT0; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */
4560 uint8_t RESERVED_8[12];
4561 __IO uint32_t FLASH1LAYOUT1; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */
4562 uint8_t RESERVED_9[12];
4563 __IO uint32_t FLASH2LAYOUT0; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */
4564 uint8_t RESERVED_10[12];
4565 __IO uint32_t FLASH2LAYOUT1; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */
4566 uint8_t RESERVED_11[12];
4567 __IO uint32_t FLASH3LAYOUT0; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */
4568 uint8_t RESERVED_12[12];
4569 __IO uint32_t FLASH3LAYOUT1; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */
4570 uint8_t RESERVED_13[12];
4571 __IO uint32_t DEBUG0; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */
4572 __IO uint32_t DEBUG0_SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */
4573 __IO uint32_t DEBUG0_CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */
4574 __IO uint32_t DEBUG0_TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */
4575 __I uint32_t DBGKESREAD; /**< KES Debug Read Register, offset: 0x110 */
4576 uint8_t RESERVED_14[12];
4577 __I uint32_t DBGCSFEREAD; /**< Chien Search Debug Read Register, offset: 0x120 */
4578 uint8_t RESERVED_15[12];
4579 __I uint32_t DBGSYNDGENREAD; /**< Syndrome Generator Debug Read Register, offset: 0x130 */
4580 uint8_t RESERVED_16[12];
4581 __I uint32_t DBGAHBMREAD; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */
4582 uint8_t RESERVED_17[12];
4583 __I uint32_t BLOCKNAME; /**< Block Name Register, offset: 0x150 */
4584 uint8_t RESERVED_18[12];
4585 __I uint32_t VERSION; /**< BCH Version Register, offset: 0x160 */
4586 uint8_t RESERVED_19[12];
4587 __IO uint32_t DEBUG1; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */
4588} BCH_Type;
4589
4590/* ----------------------------------------------------------------------------
4591 -- BCH Register Masks
4592 ---------------------------------------------------------------------------- */
4593
4594/*!
4595 * @addtogroup BCH_Register_Masks BCH Register Masks
4596 * @{
4597 */
4598
4599/*! @name CTRL - Hardware BCH ECC Accelerator Control Register */
4600/*! @{ */
4601#define BCH_CTRL_COMPLETE_IRQ_MASK (0x1U)
4602#define BCH_CTRL_COMPLETE_IRQ_SHIFT (0U)
4603#define BCH_CTRL_COMPLETE_IRQ(x) \
4604 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK)
4605#define BCH_CTRL_RSVD0_MASK (0x2U)
4606#define BCH_CTRL_RSVD0_SHIFT (1U)
4607#define BCH_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK)
4608#define BCH_CTRL_DEBUG_STALL_IRQ_MASK (0x4U)
4609#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT (2U)
4610#define BCH_CTRL_DEBUG_STALL_IRQ(x) \
4611 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK)
4612#define BCH_CTRL_BM_ERROR_IRQ_MASK (0x8U)
4613#define BCH_CTRL_BM_ERROR_IRQ_SHIFT (3U)
4614#define BCH_CTRL_BM_ERROR_IRQ(x) \
4615 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK)
4616#define BCH_CTRL_RSVD1_MASK (0xF0U)
4617#define BCH_CTRL_RSVD1_SHIFT (4U)
4618#define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK)
4619#define BCH_CTRL_COMPLETE_IRQ_EN_MASK (0x100U)
4620#define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT (8U)
4621#define BCH_CTRL_COMPLETE_IRQ_EN(x) \
4622 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK)
4623#define BCH_CTRL_RSVD2_MASK (0x200U)
4624#define BCH_CTRL_RSVD2_SHIFT (9U)
4625#define BCH_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK)
4626#define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK (0x400U)
4627#define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT (10U)
4628#define BCH_CTRL_DEBUG_STALL_IRQ_EN(x) \
4629 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK)
4630#define BCH_CTRL_RSVD3_MASK (0xF800U)
4631#define BCH_CTRL_RSVD3_SHIFT (11U)
4632#define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK)
4633#define BCH_CTRL_M2M_ENABLE_MASK (0x10000U)
4634#define BCH_CTRL_M2M_ENABLE_SHIFT (16U)
4635#define BCH_CTRL_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK)
4636#define BCH_CTRL_M2M_ENCODE_MASK (0x20000U)
4637#define BCH_CTRL_M2M_ENCODE_SHIFT (17U)
4638#define BCH_CTRL_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK)
4639#define BCH_CTRL_M2M_LAYOUT_MASK (0xC0000U)
4640#define BCH_CTRL_M2M_LAYOUT_SHIFT (18U)
4641#define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK)
4642#define BCH_CTRL_RSVD4_MASK (0x300000U)
4643#define BCH_CTRL_RSVD4_SHIFT (20U)
4644#define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK)
4645#define BCH_CTRL_DEBUGSYNDROME_MASK (0x400000U)
4646#define BCH_CTRL_DEBUGSYNDROME_SHIFT (22U)
4647#define BCH_CTRL_DEBUGSYNDROME(x) \
4648 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK)
4649#define BCH_CTRL_RSVD5_MASK (0x3F800000U)
4650#define BCH_CTRL_RSVD5_SHIFT (23U)
4651#define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK)
4652#define BCH_CTRL_CLKGATE_MASK (0x40000000U)
4653#define BCH_CTRL_CLKGATE_SHIFT (30U)
4654/*! CLKGATE
4655 * 0b0..Allow BCH to operate normally.
4656 * 0b1..Do not clock BCH gates in order to minimize power consumption.
4657 */
4658#define BCH_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK)
4659#define BCH_CTRL_SFTRST_MASK (0x80000000U)
4660#define BCH_CTRL_SFTRST_SHIFT (31U)
4661/*! SFTRST
4662 * 0b0..Allow BCH to operate normally.
4663 * 0b1..Hold BCH in reset.
4664 */
4665#define BCH_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK)
4666/*! @} */
4667
4668/*! @name CTRL_SET - Hardware BCH ECC Accelerator Control Register */
4669/*! @{ */
4670#define BCH_CTRL_SET_COMPLETE_IRQ_MASK (0x1U)
4671#define BCH_CTRL_SET_COMPLETE_IRQ_SHIFT (0U)
4672#define BCH_CTRL_SET_COMPLETE_IRQ(x) \
4673 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_MASK)
4674#define BCH_CTRL_SET_RSVD0_MASK (0x2U)
4675#define BCH_CTRL_SET_RSVD0_SHIFT (1U)
4676#define BCH_CTRL_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD0_SHIFT)) & BCH_CTRL_SET_RSVD0_MASK)
4677#define BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK (0x4U)
4678#define BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT (2U)
4679#define BCH_CTRL_SET_DEBUG_STALL_IRQ(x) \
4680 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_MASK)
4681#define BCH_CTRL_SET_BM_ERROR_IRQ_MASK (0x8U)
4682#define BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT (3U)
4683#define BCH_CTRL_SET_BM_ERROR_IRQ(x) \
4684 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_SET_BM_ERROR_IRQ_MASK)
4685#define BCH_CTRL_SET_RSVD1_MASK (0xF0U)
4686#define BCH_CTRL_SET_RSVD1_SHIFT (4U)
4687#define BCH_CTRL_SET_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD1_SHIFT)) & BCH_CTRL_SET_RSVD1_MASK)
4688#define BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK (0x100U)
4689#define BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT (8U)
4690#define BCH_CTRL_SET_COMPLETE_IRQ_EN(x) \
4691 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_SET_COMPLETE_IRQ_EN_MASK)
4692#define BCH_CTRL_SET_RSVD2_MASK (0x200U)
4693#define BCH_CTRL_SET_RSVD2_SHIFT (9U)
4694#define BCH_CTRL_SET_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD2_SHIFT)) & BCH_CTRL_SET_RSVD2_MASK)
4695#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK (0x400U)
4696#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT (10U)
4697#define BCH_CTRL_SET_DEBUG_STALL_IRQ_EN(x) \
4698 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_SET_DEBUG_STALL_IRQ_EN_MASK)
4699#define BCH_CTRL_SET_RSVD3_MASK (0xF800U)
4700#define BCH_CTRL_SET_RSVD3_SHIFT (11U)
4701#define BCH_CTRL_SET_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD3_SHIFT)) & BCH_CTRL_SET_RSVD3_MASK)
4702#define BCH_CTRL_SET_M2M_ENABLE_MASK (0x10000U)
4703#define BCH_CTRL_SET_M2M_ENABLE_SHIFT (16U)
4704#define BCH_CTRL_SET_M2M_ENABLE(x) \
4705 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENABLE_SHIFT)) & BCH_CTRL_SET_M2M_ENABLE_MASK)
4706#define BCH_CTRL_SET_M2M_ENCODE_MASK (0x20000U)
4707#define BCH_CTRL_SET_M2M_ENCODE_SHIFT (17U)
4708#define BCH_CTRL_SET_M2M_ENCODE(x) \
4709 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_ENCODE_SHIFT)) & BCH_CTRL_SET_M2M_ENCODE_MASK)
4710#define BCH_CTRL_SET_M2M_LAYOUT_MASK (0xC0000U)
4711#define BCH_CTRL_SET_M2M_LAYOUT_SHIFT (18U)
4712#define BCH_CTRL_SET_M2M_LAYOUT(x) \
4713 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_M2M_LAYOUT_SHIFT)) & BCH_CTRL_SET_M2M_LAYOUT_MASK)
4714#define BCH_CTRL_SET_RSVD4_MASK (0x300000U)
4715#define BCH_CTRL_SET_RSVD4_SHIFT (20U)
4716#define BCH_CTRL_SET_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD4_SHIFT)) & BCH_CTRL_SET_RSVD4_MASK)
4717#define BCH_CTRL_SET_DEBUGSYNDROME_MASK (0x400000U)
4718#define BCH_CTRL_SET_DEBUGSYNDROME_SHIFT (22U)
4719#define BCH_CTRL_SET_DEBUGSYNDROME(x) \
4720 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_SET_DEBUGSYNDROME_MASK)
4721#define BCH_CTRL_SET_RSVD5_MASK (0x3F800000U)
4722#define BCH_CTRL_SET_RSVD5_SHIFT (23U)
4723#define BCH_CTRL_SET_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_RSVD5_SHIFT)) & BCH_CTRL_SET_RSVD5_MASK)
4724#define BCH_CTRL_SET_CLKGATE_MASK (0x40000000U)
4725#define BCH_CTRL_SET_CLKGATE_SHIFT (30U)
4726/*! CLKGATE
4727 * 0b0..Allow BCH to operate normally.
4728 * 0b1..Do not clock BCH gates in order to minimize power consumption.
4729 */
4730#define BCH_CTRL_SET_CLKGATE(x) \
4731 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_CLKGATE_SHIFT)) & BCH_CTRL_SET_CLKGATE_MASK)
4732#define BCH_CTRL_SET_SFTRST_MASK (0x80000000U)
4733#define BCH_CTRL_SET_SFTRST_SHIFT (31U)
4734/*! SFTRST
4735 * 0b0..Allow BCH to operate normally.
4736 * 0b1..Hold BCH in reset.
4737 */
4738#define BCH_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SET_SFTRST_SHIFT)) & BCH_CTRL_SET_SFTRST_MASK)
4739/*! @} */
4740
4741/*! @name CTRL_CLR - Hardware BCH ECC Accelerator Control Register */
4742/*! @{ */
4743#define BCH_CTRL_CLR_COMPLETE_IRQ_MASK (0x1U)
4744#define BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT (0U)
4745#define BCH_CTRL_CLR_COMPLETE_IRQ(x) \
4746 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_MASK)
4747#define BCH_CTRL_CLR_RSVD0_MASK (0x2U)
4748#define BCH_CTRL_CLR_RSVD0_SHIFT (1U)
4749#define BCH_CTRL_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD0_SHIFT)) & BCH_CTRL_CLR_RSVD0_MASK)
4750#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK (0x4U)
4751#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT (2U)
4752#define BCH_CTRL_CLR_DEBUG_STALL_IRQ(x) \
4753 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_MASK)
4754#define BCH_CTRL_CLR_BM_ERROR_IRQ_MASK (0x8U)
4755#define BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT (3U)
4756#define BCH_CTRL_CLR_BM_ERROR_IRQ(x) \
4757 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_CLR_BM_ERROR_IRQ_MASK)
4758#define BCH_CTRL_CLR_RSVD1_MASK (0xF0U)
4759#define BCH_CTRL_CLR_RSVD1_SHIFT (4U)
4760#define BCH_CTRL_CLR_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD1_SHIFT)) & BCH_CTRL_CLR_RSVD1_MASK)
4761#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK (0x100U)
4762#define BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT (8U)
4763#define BCH_CTRL_CLR_COMPLETE_IRQ_EN(x) \
4764 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_COMPLETE_IRQ_EN_MASK)
4765#define BCH_CTRL_CLR_RSVD2_MASK (0x200U)
4766#define BCH_CTRL_CLR_RSVD2_SHIFT (9U)
4767#define BCH_CTRL_CLR_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD2_SHIFT)) & BCH_CTRL_CLR_RSVD2_MASK)
4768#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK (0x400U)
4769#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT (10U)
4770#define BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN(x) \
4771 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_CLR_DEBUG_STALL_IRQ_EN_MASK)
4772#define BCH_CTRL_CLR_RSVD3_MASK (0xF800U)
4773#define BCH_CTRL_CLR_RSVD3_SHIFT (11U)
4774#define BCH_CTRL_CLR_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD3_SHIFT)) & BCH_CTRL_CLR_RSVD3_MASK)
4775#define BCH_CTRL_CLR_M2M_ENABLE_MASK (0x10000U)
4776#define BCH_CTRL_CLR_M2M_ENABLE_SHIFT (16U)
4777#define BCH_CTRL_CLR_M2M_ENABLE(x) \
4778 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENABLE_SHIFT)) & BCH_CTRL_CLR_M2M_ENABLE_MASK)
4779#define BCH_CTRL_CLR_M2M_ENCODE_MASK (0x20000U)
4780#define BCH_CTRL_CLR_M2M_ENCODE_SHIFT (17U)
4781#define BCH_CTRL_CLR_M2M_ENCODE(x) \
4782 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_ENCODE_SHIFT)) & BCH_CTRL_CLR_M2M_ENCODE_MASK)
4783#define BCH_CTRL_CLR_M2M_LAYOUT_MASK (0xC0000U)
4784#define BCH_CTRL_CLR_M2M_LAYOUT_SHIFT (18U)
4785#define BCH_CTRL_CLR_M2M_LAYOUT(x) \
4786 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_M2M_LAYOUT_SHIFT)) & BCH_CTRL_CLR_M2M_LAYOUT_MASK)
4787#define BCH_CTRL_CLR_RSVD4_MASK (0x300000U)
4788#define BCH_CTRL_CLR_RSVD4_SHIFT (20U)
4789#define BCH_CTRL_CLR_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD4_SHIFT)) & BCH_CTRL_CLR_RSVD4_MASK)
4790#define BCH_CTRL_CLR_DEBUGSYNDROME_MASK (0x400000U)
4791#define BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT (22U)
4792#define BCH_CTRL_CLR_DEBUGSYNDROME(x) \
4793 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_CLR_DEBUGSYNDROME_MASK)
4794#define BCH_CTRL_CLR_RSVD5_MASK (0x3F800000U)
4795#define BCH_CTRL_CLR_RSVD5_SHIFT (23U)
4796#define BCH_CTRL_CLR_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_RSVD5_SHIFT)) & BCH_CTRL_CLR_RSVD5_MASK)
4797#define BCH_CTRL_CLR_CLKGATE_MASK (0x40000000U)
4798#define BCH_CTRL_CLR_CLKGATE_SHIFT (30U)
4799/*! CLKGATE
4800 * 0b0..Allow BCH to operate normally.
4801 * 0b1..Do not clock BCH gates in order to minimize power consumption.
4802 */
4803#define BCH_CTRL_CLR_CLKGATE(x) \
4804 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_CLKGATE_SHIFT)) & BCH_CTRL_CLR_CLKGATE_MASK)
4805#define BCH_CTRL_CLR_SFTRST_MASK (0x80000000U)
4806#define BCH_CTRL_CLR_SFTRST_SHIFT (31U)
4807/*! SFTRST
4808 * 0b0..Allow BCH to operate normally.
4809 * 0b1..Hold BCH in reset.
4810 */
4811#define BCH_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLR_SFTRST_SHIFT)) & BCH_CTRL_CLR_SFTRST_MASK)
4812/*! @} */
4813
4814/*! @name CTRL_TOG - Hardware BCH ECC Accelerator Control Register */
4815/*! @{ */
4816#define BCH_CTRL_TOG_COMPLETE_IRQ_MASK (0x1U)
4817#define BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT (0U)
4818#define BCH_CTRL_TOG_COMPLETE_IRQ(x) \
4819 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_MASK)
4820#define BCH_CTRL_TOG_RSVD0_MASK (0x2U)
4821#define BCH_CTRL_TOG_RSVD0_SHIFT (1U)
4822#define BCH_CTRL_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD0_SHIFT)) & BCH_CTRL_TOG_RSVD0_MASK)
4823#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK (0x4U)
4824#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT (2U)
4825#define BCH_CTRL_TOG_DEBUG_STALL_IRQ(x) \
4826 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_MASK)
4827#define BCH_CTRL_TOG_BM_ERROR_IRQ_MASK (0x8U)
4828#define BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT (3U)
4829#define BCH_CTRL_TOG_BM_ERROR_IRQ(x) \
4830 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_TOG_BM_ERROR_IRQ_MASK)
4831#define BCH_CTRL_TOG_RSVD1_MASK (0xF0U)
4832#define BCH_CTRL_TOG_RSVD1_SHIFT (4U)
4833#define BCH_CTRL_TOG_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD1_SHIFT)) & BCH_CTRL_TOG_RSVD1_MASK)
4834#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK (0x100U)
4835#define BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT (8U)
4836#define BCH_CTRL_TOG_COMPLETE_IRQ_EN(x) \
4837 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_COMPLETE_IRQ_EN_MASK)
4838#define BCH_CTRL_TOG_RSVD2_MASK (0x200U)
4839#define BCH_CTRL_TOG_RSVD2_SHIFT (9U)
4840#define BCH_CTRL_TOG_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD2_SHIFT)) & BCH_CTRL_TOG_RSVD2_MASK)
4841#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK (0x400U)
4842#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT (10U)
4843#define BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN(x) \
4844 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_TOG_DEBUG_STALL_IRQ_EN_MASK)
4845#define BCH_CTRL_TOG_RSVD3_MASK (0xF800U)
4846#define BCH_CTRL_TOG_RSVD3_SHIFT (11U)
4847#define BCH_CTRL_TOG_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD3_SHIFT)) & BCH_CTRL_TOG_RSVD3_MASK)
4848#define BCH_CTRL_TOG_M2M_ENABLE_MASK (0x10000U)
4849#define BCH_CTRL_TOG_M2M_ENABLE_SHIFT (16U)
4850#define BCH_CTRL_TOG_M2M_ENABLE(x) \
4851 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENABLE_SHIFT)) & BCH_CTRL_TOG_M2M_ENABLE_MASK)
4852#define BCH_CTRL_TOG_M2M_ENCODE_MASK (0x20000U)
4853#define BCH_CTRL_TOG_M2M_ENCODE_SHIFT (17U)
4854#define BCH_CTRL_TOG_M2M_ENCODE(x) \
4855 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_ENCODE_SHIFT)) & BCH_CTRL_TOG_M2M_ENCODE_MASK)
4856#define BCH_CTRL_TOG_M2M_LAYOUT_MASK (0xC0000U)
4857#define BCH_CTRL_TOG_M2M_LAYOUT_SHIFT (18U)
4858#define BCH_CTRL_TOG_M2M_LAYOUT(x) \
4859 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_M2M_LAYOUT_SHIFT)) & BCH_CTRL_TOG_M2M_LAYOUT_MASK)
4860#define BCH_CTRL_TOG_RSVD4_MASK (0x300000U)
4861#define BCH_CTRL_TOG_RSVD4_SHIFT (20U)
4862#define BCH_CTRL_TOG_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD4_SHIFT)) & BCH_CTRL_TOG_RSVD4_MASK)
4863#define BCH_CTRL_TOG_DEBUGSYNDROME_MASK (0x400000U)
4864#define BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT (22U)
4865#define BCH_CTRL_TOG_DEBUGSYNDROME(x) \
4866 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_TOG_DEBUGSYNDROME_MASK)
4867#define BCH_CTRL_TOG_RSVD5_MASK (0x3F800000U)
4868#define BCH_CTRL_TOG_RSVD5_SHIFT (23U)
4869#define BCH_CTRL_TOG_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_RSVD5_SHIFT)) & BCH_CTRL_TOG_RSVD5_MASK)
4870#define BCH_CTRL_TOG_CLKGATE_MASK (0x40000000U)
4871#define BCH_CTRL_TOG_CLKGATE_SHIFT (30U)
4872/*! CLKGATE
4873 * 0b0..Allow BCH to operate normally.
4874 * 0b1..Do not clock BCH gates in order to minimize power consumption.
4875 */
4876#define BCH_CTRL_TOG_CLKGATE(x) \
4877 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_CLKGATE_SHIFT)) & BCH_CTRL_TOG_CLKGATE_MASK)
4878#define BCH_CTRL_TOG_SFTRST_MASK (0x80000000U)
4879#define BCH_CTRL_TOG_SFTRST_SHIFT (31U)
4880/*! SFTRST
4881 * 0b0..Allow BCH to operate normally.
4882 * 0b1..Hold BCH in reset.
4883 */
4884#define BCH_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_TOG_SFTRST_SHIFT)) & BCH_CTRL_TOG_SFTRST_MASK)
4885/*! @} */
4886
4887/*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */
4888/*! @{ */
4889#define BCH_STATUS0_RSVD0_MASK (0x3U)
4890#define BCH_STATUS0_RSVD0_SHIFT (0U)
4891#define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK)
4892#define BCH_STATUS0_UNCORRECTABLE_MASK (0x4U)
4893#define BCH_STATUS0_UNCORRECTABLE_SHIFT (2U)
4894#define BCH_STATUS0_UNCORRECTABLE(x) \
4895 (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK)
4896#define BCH_STATUS0_CORRECTED_MASK (0x8U)
4897#define BCH_STATUS0_CORRECTED_SHIFT (3U)
4898#define BCH_STATUS0_CORRECTED(x) \
4899 (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK)
4900#define BCH_STATUS0_ALLONES_MASK (0x10U)
4901#define BCH_STATUS0_ALLONES_SHIFT (4U)
4902#define BCH_STATUS0_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK)
4903#define BCH_STATUS0_RSVD1_MASK (0xE0U)
4904#define BCH_STATUS0_RSVD1_SHIFT (5U)
4905#define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK)
4906#define BCH_STATUS0_STATUS_BLK0_MASK (0xFF00U)
4907#define BCH_STATUS0_STATUS_BLK0_SHIFT (8U)
4908/*! STATUS_BLK0
4909 * 0b00000000..No errors found on block.
4910 * 0b00000001..One error found on block.
4911 * 0b00000010..One errors found on block.
4912 * 0b00000011..One errors found on block.
4913 * 0b00000100..One errors found on block.
4914 * 0b11111110..Block exhibited uncorrectable errors.
4915 * 0b11111111..Page is erased.
4916 */
4917#define BCH_STATUS0_STATUS_BLK0(x) \
4918 (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK)
4919#define BCH_STATUS0_COMPLETED_CE_MASK (0xF0000U)
4920#define BCH_STATUS0_COMPLETED_CE_SHIFT (16U)
4921#define BCH_STATUS0_COMPLETED_CE(x) \
4922 (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK)
4923#define BCH_STATUS0_HANDLE_MASK (0xFFF00000U)
4924#define BCH_STATUS0_HANDLE_SHIFT (20U)
4925#define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK)
4926/*! @} */
4927
4928/*! @name MODE - Hardware ECC Accelerator Mode Register */
4929/*! @{ */
4930#define BCH_MODE_ERASE_THRESHOLD_MASK (0xFFU)
4931#define BCH_MODE_ERASE_THRESHOLD_SHIFT (0U)
4932#define BCH_MODE_ERASE_THRESHOLD(x) \
4933 (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK)
4934#define BCH_MODE_RSVD_MASK (0xFFFFFF00U)
4935#define BCH_MODE_RSVD_SHIFT (8U)
4936#define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK)
4937/*! @} */
4938
4939/*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */
4940/*! @{ */
4941#define BCH_ENCODEPTR_ADDR_MASK (0xFFFFFFFFU)
4942#define BCH_ENCODEPTR_ADDR_SHIFT (0U)
4943#define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK)
4944/*! @} */
4945
4946/*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */
4947/*! @{ */
4948#define BCH_DATAPTR_ADDR_MASK (0xFFFFFFFFU)
4949#define BCH_DATAPTR_ADDR_SHIFT (0U)
4950#define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK)
4951/*! @} */
4952
4953/*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */
4954/*! @{ */
4955#define BCH_METAPTR_ADDR_MASK (0xFFFFFFFFU)
4956#define BCH_METAPTR_ADDR_SHIFT (0U)
4957#define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK)
4958/*! @} */
4959
4960/*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */
4961/*! @{ */
4962#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3U)
4963#define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT (0U)
4964#define BCH_LAYOUTSELECT_CS0_SELECT(x) \
4965 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK)
4966#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0xCU)
4967#define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT (2U)
4968#define BCH_LAYOUTSELECT_CS1_SELECT(x) \
4969 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK)
4970#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x30U)
4971#define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT (4U)
4972#define BCH_LAYOUTSELECT_CS2_SELECT(x) \
4973 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK)
4974#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0xC0U)
4975#define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT (6U)
4976#define BCH_LAYOUTSELECT_CS3_SELECT(x) \
4977 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK)
4978#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x300U)
4979#define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT (8U)
4980#define BCH_LAYOUTSELECT_CS4_SELECT(x) \
4981 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK)
4982#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0xC00U)
4983#define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT (10U)
4984#define BCH_LAYOUTSELECT_CS5_SELECT(x) \
4985 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK)
4986#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3000U)
4987#define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT (12U)
4988#define BCH_LAYOUTSELECT_CS6_SELECT(x) \
4989 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK)
4990#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0xC000U)
4991#define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT (14U)
4992#define BCH_LAYOUTSELECT_CS7_SELECT(x) \
4993 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK)
4994#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x30000U)
4995#define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT (16U)
4996#define BCH_LAYOUTSELECT_CS8_SELECT(x) \
4997 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK)
4998#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0xC0000U)
4999#define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT (18U)
5000#define BCH_LAYOUTSELECT_CS9_SELECT(x) \
5001 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK)
5002#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x300000U)
5003#define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT (20U)
5004#define BCH_LAYOUTSELECT_CS10_SELECT(x) \
5005 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK)
5006#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0xC00000U)
5007#define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT (22U)
5008#define BCH_LAYOUTSELECT_CS11_SELECT(x) \
5009 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK)
5010#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3000000U)
5011#define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT (24U)
5012#define BCH_LAYOUTSELECT_CS12_SELECT(x) \
5013 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK)
5014#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0xC000000U)
5015#define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT (26U)
5016#define BCH_LAYOUTSELECT_CS13_SELECT(x) \
5017 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK)
5018#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x30000000U)
5019#define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT (28U)
5020#define BCH_LAYOUTSELECT_CS14_SELECT(x) \
5021 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK)
5022#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0xC0000000U)
5023#define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT (30U)
5024#define BCH_LAYOUTSELECT_CS15_SELECT(x) \
5025 (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK)
5026/*! @} */
5027
5028/*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */
5029/*! @{ */
5030#define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
5031#define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT (0U)
5032#define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) \
5033 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK)
5034#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
5035#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
5036#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x) \
5037 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK)
5038#define BCH_FLASH0LAYOUT0_ECC0_MASK (0xF800U)
5039#define BCH_FLASH0LAYOUT0_ECC0_SHIFT (11U)
5040/*! ECC0
5041 * 0b00000..No ECC to be performed
5042 * 0b00001..ECC 2 to be performed
5043 * 0b00010..ECC 4 to be performed
5044 * 0b11110..ECC 60 to be performed
5045 * 0b11111..ECC 62 to be performed
5046 */
5047#define BCH_FLASH0LAYOUT0_ECC0(x) \
5048 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK)
5049#define BCH_FLASH0LAYOUT0_META_SIZE_MASK (0xFF0000U)
5050#define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT (16U)
5051#define BCH_FLASH0LAYOUT0_META_SIZE(x) \
5052 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK)
5053#define BCH_FLASH0LAYOUT0_NBLOCKS_MASK (0xFF000000U)
5054#define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT (24U)
5055#define BCH_FLASH0LAYOUT0_NBLOCKS(x) \
5056 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK)
5057/*! @} */
5058
5059/*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */
5060/*! @{ */
5061#define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
5062#define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT (0U)
5063#define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) \
5064 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK)
5065#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
5066#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
5067#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x) \
5068 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK)
5069#define BCH_FLASH0LAYOUT1_ECCN_MASK (0xF800U)
5070#define BCH_FLASH0LAYOUT1_ECCN_SHIFT (11U)
5071/*! ECCN
5072 * 0b00000..No ECC to be performed
5073 * 0b00001..ECC 2 to be performed
5074 * 0b00010..ECC 4 to be performed
5075 * 0b11110..ECC 60 to be performed
5076 * 0b11111..ECC 62 to be performed
5077 */
5078#define BCH_FLASH0LAYOUT1_ECCN(x) \
5079 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK)
5080#define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
5081#define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT (16U)
5082#define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) \
5083 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK)
5084/*! @} */
5085
5086/*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */
5087/*! @{ */
5088#define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
5089#define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT (0U)
5090#define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) \
5091 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK)
5092#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
5093#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
5094#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x) \
5095 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK)
5096#define BCH_FLASH1LAYOUT0_ECC0_MASK (0xF800U)
5097#define BCH_FLASH1LAYOUT0_ECC0_SHIFT (11U)
5098/*! ECC0
5099 * 0b00000..No ECC to be performed
5100 * 0b00001..ECC 2 to be performed
5101 * 0b00010..ECC 4 to be performed
5102 * 0b11110..ECC 60 to be performed
5103 * 0b11111..ECC 62 to be performed
5104 */
5105#define BCH_FLASH1LAYOUT0_ECC0(x) \
5106 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK)
5107#define BCH_FLASH1LAYOUT0_META_SIZE_MASK (0xFF0000U)
5108#define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT (16U)
5109#define BCH_FLASH1LAYOUT0_META_SIZE(x) \
5110 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK)
5111#define BCH_FLASH1LAYOUT0_NBLOCKS_MASK (0xFF000000U)
5112#define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT (24U)
5113#define BCH_FLASH1LAYOUT0_NBLOCKS(x) \
5114 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK)
5115/*! @} */
5116
5117/*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */
5118/*! @{ */
5119#define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
5120#define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT (0U)
5121#define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) \
5122 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK)
5123#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
5124#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
5125#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x) \
5126 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK)
5127#define BCH_FLASH1LAYOUT1_ECCN_MASK (0xF800U)
5128#define BCH_FLASH1LAYOUT1_ECCN_SHIFT (11U)
5129/*! ECCN
5130 * 0b00000..No ECC to be performed
5131 * 0b00001..ECC 2 to be performed
5132 * 0b00010..ECC 4 to be performed
5133 * 0b11110..ECC 60 to be performed
5134 * 0b11111..ECC 62 to be performed
5135 */
5136#define BCH_FLASH1LAYOUT1_ECCN(x) \
5137 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK)
5138#define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
5139#define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT (16U)
5140#define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) \
5141 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK)
5142/*! @} */
5143
5144/*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */
5145/*! @{ */
5146#define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
5147#define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT (0U)
5148#define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) \
5149 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK)
5150#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
5151#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
5152#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x) \
5153 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK)
5154#define BCH_FLASH2LAYOUT0_ECC0_MASK (0xF800U)
5155#define BCH_FLASH2LAYOUT0_ECC0_SHIFT (11U)
5156/*! ECC0
5157 * 0b00000..No ECC to be performed
5158 * 0b00001..ECC 2 to be performed
5159 * 0b00010..ECC 4 to be performed
5160 * 0b11110..ECC 60 to be performed
5161 * 0b11111..ECC 62 to be performed
5162 */
5163#define BCH_FLASH2LAYOUT0_ECC0(x) \
5164 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK)
5165#define BCH_FLASH2LAYOUT0_META_SIZE_MASK (0xFF0000U)
5166#define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT (16U)
5167#define BCH_FLASH2LAYOUT0_META_SIZE(x) \
5168 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK)
5169#define BCH_FLASH2LAYOUT0_NBLOCKS_MASK (0xFF000000U)
5170#define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT (24U)
5171#define BCH_FLASH2LAYOUT0_NBLOCKS(x) \
5172 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK)
5173/*! @} */
5174
5175/*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */
5176/*! @{ */
5177#define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
5178#define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT (0U)
5179#define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) \
5180 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK)
5181#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
5182#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
5183#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x) \
5184 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK)
5185#define BCH_FLASH2LAYOUT1_ECCN_MASK (0xF800U)
5186#define BCH_FLASH2LAYOUT1_ECCN_SHIFT (11U)
5187/*! ECCN
5188 * 0b00000..No ECC to be performed
5189 * 0b00001..ECC 2 to be performed
5190 * 0b00010..ECC 4 to be performed
5191 * 0b11110..ECC 60 to be performed
5192 * 0b11111..ECC 62 to be performed
5193 */
5194#define BCH_FLASH2LAYOUT1_ECCN(x) \
5195 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK)
5196#define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
5197#define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT (16U)
5198#define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) \
5199 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK)
5200/*! @} */
5201
5202/*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */
5203/*! @{ */
5204#define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
5205#define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT (0U)
5206#define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) \
5207 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK)
5208#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
5209#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
5210#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x) \
5211 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK)
5212#define BCH_FLASH3LAYOUT0_ECC0_MASK (0xF800U)
5213#define BCH_FLASH3LAYOUT0_ECC0_SHIFT (11U)
5214/*! ECC0
5215 * 0b00000..No ECC to be performed
5216 * 0b00001..ECC 2 to be performed
5217 * 0b00010..ECC 4 to be performed
5218 * 0b11110..ECC 60 to be performed
5219 * 0b11111..ECC 62 to be performed
5220 */
5221#define BCH_FLASH3LAYOUT0_ECC0(x) \
5222 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK)
5223#define BCH_FLASH3LAYOUT0_META_SIZE_MASK (0xFF0000U)
5224#define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT (16U)
5225#define BCH_FLASH3LAYOUT0_META_SIZE(x) \
5226 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK)
5227#define BCH_FLASH3LAYOUT0_NBLOCKS_MASK (0xFF000000U)
5228#define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT (24U)
5229#define BCH_FLASH3LAYOUT0_NBLOCKS(x) \
5230 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK)
5231/*! @} */
5232
5233/*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */
5234/*! @{ */
5235#define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
5236#define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT (0U)
5237#define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) \
5238 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK)
5239#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
5240#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
5241#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x) \
5242 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK)
5243#define BCH_FLASH3LAYOUT1_ECCN_MASK (0xF800U)
5244#define BCH_FLASH3LAYOUT1_ECCN_SHIFT (11U)
5245/*! ECCN
5246 * 0b00000..No ECC to be performed
5247 * 0b00001..ECC 2 to be performed
5248 * 0b00010..ECC 4 to be performed
5249 * 0b11110..ECC 60 to be performed
5250 * 0b11111..ECC 62 to be performed
5251 */
5252#define BCH_FLASH3LAYOUT1_ECCN(x) \
5253 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK)
5254#define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
5255#define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT (16U)
5256#define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) \
5257 (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK)
5258/*! @} */
5259
5260/*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */
5261/*! @{ */
5262#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK (0x3FU)
5263#define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT (0U)
5264#define BCH_DEBUG0_DEBUG_REG_SELECT(x) \
5265 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK)
5266#define BCH_DEBUG0_RSVD0_MASK (0xC0U)
5267#define BCH_DEBUG0_RSVD0_SHIFT (6U)
5268#define BCH_DEBUG0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK)
5269#define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK (0x100U)
5270#define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT (8U)
5271/*! BM_KES_TEST_BYPASS
5272 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
5273 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
5274 */
5275#define BCH_DEBUG0_BM_KES_TEST_BYPASS(x) \
5276 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK)
5277#define BCH_DEBUG0_KES_DEBUG_STALL_MASK (0x200U)
5278#define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT (9U)
5279/*! KES_DEBUG_STALL
5280 * 0b0..KES FSM proceeds to next block supplied by bus master.
5281 * 0b1..KES FSM waits after current equations are solved and the search engine is started.
5282 */
5283#define BCH_DEBUG0_KES_DEBUG_STALL(x) \
5284 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK)
5285#define BCH_DEBUG0_KES_DEBUG_STEP_MASK (0x400U)
5286#define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT (10U)
5287#define BCH_DEBUG0_KES_DEBUG_STEP(x) \
5288 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK)
5289#define BCH_DEBUG0_KES_STANDALONE_MASK (0x800U)
5290#define BCH_DEBUG0_KES_STANDALONE_SHIFT (11U)
5291/*! KES_STANDALONE
5292 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
5293 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
5294 */
5295#define BCH_DEBUG0_KES_STANDALONE(x) \
5296 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK)
5297#define BCH_DEBUG0_KES_DEBUG_KICK_MASK (0x1000U)
5298#define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT (12U)
5299#define BCH_DEBUG0_KES_DEBUG_KICK(x) \
5300 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK)
5301#define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK (0x2000U)
5302#define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT (13U)
5303/*! KES_DEBUG_MODE4K
5304 * 0b1..Mode is set for 4K NAND pages.
5305 * 0b1..Mode is set for 2K NAND pages.
5306 */
5307#define BCH_DEBUG0_KES_DEBUG_MODE4K(x) \
5308 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK)
5309#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
5310#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
5311/*! KES_DEBUG_PAYLOAD_FLAG
5312 * 0b1..Payload is set for 512 bytes data block.
5313 * 0b1..Payload is set for 65 or 19 bytes auxiliary block.
5314 */
5315#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x) \
5316 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK)
5317#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
5318#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
5319#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x) \
5320 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK)
5321#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
5322#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
5323/*! KES_DEBUG_SYNDROME_SYMBOL
5324 * 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
5325 * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
5326 */
5327#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x) \
5328 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & \
5329 BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK)
5330#define BCH_DEBUG0_RSVD1_MASK (0xFE000000U)
5331#define BCH_DEBUG0_RSVD1_SHIFT (25U)
5332#define BCH_DEBUG0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK)
5333/*! @} */
5334
5335/*! @name DEBUG0_SET - Hardware BCH ECC Debug Register0 */
5336/*! @{ */
5337#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK (0x3FU)
5338#define BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT (0U)
5339#define BCH_DEBUG0_SET_DEBUG_REG_SELECT(x) \
5340 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_SET_DEBUG_REG_SELECT_MASK)
5341#define BCH_DEBUG0_SET_RSVD0_MASK (0xC0U)
5342#define BCH_DEBUG0_SET_RSVD0_SHIFT (6U)
5343#define BCH_DEBUG0_SET_RSVD0(x) \
5344 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD0_SHIFT)) & BCH_DEBUG0_SET_RSVD0_MASK)
5345#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK (0x100U)
5346#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT (8U)
5347/*! BM_KES_TEST_BYPASS
5348 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
5349 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
5350 */
5351#define BCH_DEBUG0_SET_BM_KES_TEST_BYPASS(x) \
5352 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_SET_BM_KES_TEST_BYPASS_MASK)
5353#define BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK (0x200U)
5354#define BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT (9U)
5355/*! KES_DEBUG_STALL
5356 * 0b0..KES FSM proceeds to next block supplied by bus master.
5357 * 0b1..KES FSM waits after current equations are solved and the search engine is started.
5358 */
5359#define BCH_DEBUG0_SET_KES_DEBUG_STALL(x) \
5360 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STALL_MASK)
5361#define BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK (0x400U)
5362#define BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT (10U)
5363#define BCH_DEBUG0_SET_KES_DEBUG_STEP(x) \
5364 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_STEP_MASK)
5365#define BCH_DEBUG0_SET_KES_STANDALONE_MASK (0x800U)
5366#define BCH_DEBUG0_SET_KES_STANDALONE_SHIFT (11U)
5367/*! KES_STANDALONE
5368 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
5369 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
5370 */
5371#define BCH_DEBUG0_SET_KES_STANDALONE(x) \
5372 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_SET_KES_STANDALONE_MASK)
5373#define BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK (0x1000U)
5374#define BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT (12U)
5375#define BCH_DEBUG0_SET_KES_DEBUG_KICK(x) \
5376 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_KICK_MASK)
5377#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK (0x2000U)
5378#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT (13U)
5379/*! KES_DEBUG_MODE4K
5380 * 0b1..Mode is set for 4K NAND pages.
5381 * 0b1..Mode is set for 2K NAND pages.
5382 */
5383#define BCH_DEBUG0_SET_KES_DEBUG_MODE4K(x) \
5384 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_SET_KES_DEBUG_MODE4K_MASK)
5385#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
5386#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
5387/*! KES_DEBUG_PAYLOAD_FLAG
5388 * 0b1..Payload is set for 512 bytes data block.
5389 * 0b1..Payload is set for 65 or 19 bytes auxiliary block.
5390 */
5391#define BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG(x) \
5392 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & \
5393 BCH_DEBUG0_SET_KES_DEBUG_PAYLOAD_FLAG_MASK)
5394#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
5395#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
5396#define BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND(x) \
5397 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_SHIFT)) & \
5398 BCH_DEBUG0_SET_KES_DEBUG_SHIFT_SYND_MASK)
5399#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
5400#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
5401/*! KES_DEBUG_SYNDROME_SYMBOL
5402 * 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
5403 * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
5404 */
5405#define BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL(x) \
5406 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & \
5407 BCH_DEBUG0_SET_KES_DEBUG_SYNDROME_SYMBOL_MASK)
5408#define BCH_DEBUG0_SET_RSVD1_MASK (0xFE000000U)
5409#define BCH_DEBUG0_SET_RSVD1_SHIFT (25U)
5410#define BCH_DEBUG0_SET_RSVD1(x) \
5411 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_SET_RSVD1_SHIFT)) & BCH_DEBUG0_SET_RSVD1_MASK)
5412/*! @} */
5413
5414/*! @name DEBUG0_CLR - Hardware BCH ECC Debug Register0 */
5415/*! @{ */
5416#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK (0x3FU)
5417#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT (0U)
5418#define BCH_DEBUG0_CLR_DEBUG_REG_SELECT(x) \
5419 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_CLR_DEBUG_REG_SELECT_MASK)
5420#define BCH_DEBUG0_CLR_RSVD0_MASK (0xC0U)
5421#define BCH_DEBUG0_CLR_RSVD0_SHIFT (6U)
5422#define BCH_DEBUG0_CLR_RSVD0(x) \
5423 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD0_SHIFT)) & BCH_DEBUG0_CLR_RSVD0_MASK)
5424#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK (0x100U)
5425#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT (8U)
5426/*! BM_KES_TEST_BYPASS
5427 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
5428 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
5429 */
5430#define BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS(x) \
5431 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_CLR_BM_KES_TEST_BYPASS_MASK)
5432#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK (0x200U)
5433#define BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT (9U)
5434/*! KES_DEBUG_STALL
5435 * 0b0..KES FSM proceeds to next block supplied by bus master.
5436 * 0b1..KES FSM waits after current equations are solved and the search engine is started.
5437 */
5438#define BCH_DEBUG0_CLR_KES_DEBUG_STALL(x) \
5439 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STALL_MASK)
5440#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK (0x400U)
5441#define BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT (10U)
5442#define BCH_DEBUG0_CLR_KES_DEBUG_STEP(x) \
5443 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_STEP_MASK)
5444#define BCH_DEBUG0_CLR_KES_STANDALONE_MASK (0x800U)
5445#define BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT (11U)
5446/*! KES_STANDALONE
5447 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
5448 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
5449 */
5450#define BCH_DEBUG0_CLR_KES_STANDALONE(x) \
5451 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_CLR_KES_STANDALONE_MASK)
5452#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK (0x1000U)
5453#define BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT (12U)
5454#define BCH_DEBUG0_CLR_KES_DEBUG_KICK(x) \
5455 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_KICK_MASK)
5456#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK (0x2000U)
5457#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT (13U)
5458/*! KES_DEBUG_MODE4K
5459 * 0b1..Mode is set for 4K NAND pages.
5460 * 0b1..Mode is set for 2K NAND pages.
5461 */
5462#define BCH_DEBUG0_CLR_KES_DEBUG_MODE4K(x) \
5463 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_CLR_KES_DEBUG_MODE4K_MASK)
5464#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
5465#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
5466/*! KES_DEBUG_PAYLOAD_FLAG
5467 * 0b1..Payload is set for 512 bytes data block.
5468 * 0b1..Payload is set for 65 or 19 bytes auxiliary block.
5469 */
5470#define BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG(x) \
5471 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & \
5472 BCH_DEBUG0_CLR_KES_DEBUG_PAYLOAD_FLAG_MASK)
5473#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
5474#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
5475#define BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND(x) \
5476 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_SHIFT)) & \
5477 BCH_DEBUG0_CLR_KES_DEBUG_SHIFT_SYND_MASK)
5478#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
5479#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
5480/*! KES_DEBUG_SYNDROME_SYMBOL
5481 * 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
5482 * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
5483 */
5484#define BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL(x) \
5485 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & \
5486 BCH_DEBUG0_CLR_KES_DEBUG_SYNDROME_SYMBOL_MASK)
5487#define BCH_DEBUG0_CLR_RSVD1_MASK (0xFE000000U)
5488#define BCH_DEBUG0_CLR_RSVD1_SHIFT (25U)
5489#define BCH_DEBUG0_CLR_RSVD1(x) \
5490 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_CLR_RSVD1_SHIFT)) & BCH_DEBUG0_CLR_RSVD1_MASK)
5491/*! @} */
5492
5493/*! @name DEBUG0_TOG - Hardware BCH ECC Debug Register0 */
5494/*! @{ */
5495#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK (0x3FU)
5496#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT (0U)
5497#define BCH_DEBUG0_TOG_DEBUG_REG_SELECT(x) \
5498 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_TOG_DEBUG_REG_SELECT_MASK)
5499#define BCH_DEBUG0_TOG_RSVD0_MASK (0xC0U)
5500#define BCH_DEBUG0_TOG_RSVD0_SHIFT (6U)
5501#define BCH_DEBUG0_TOG_RSVD0(x) \
5502 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD0_SHIFT)) & BCH_DEBUG0_TOG_RSVD0_MASK)
5503#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK (0x100U)
5504#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT (8U)
5505/*! BM_KES_TEST_BYPASS
5506 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
5507 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
5508 */
5509#define BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS(x) \
5510 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_TOG_BM_KES_TEST_BYPASS_MASK)
5511#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK (0x200U)
5512#define BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT (9U)
5513/*! KES_DEBUG_STALL
5514 * 0b0..KES FSM proceeds to next block supplied by bus master.
5515 * 0b1..KES FSM waits after current equations are solved and the search engine is started.
5516 */
5517#define BCH_DEBUG0_TOG_KES_DEBUG_STALL(x) \
5518 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STALL_MASK)
5519#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK (0x400U)
5520#define BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT (10U)
5521#define BCH_DEBUG0_TOG_KES_DEBUG_STEP(x) \
5522 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_STEP_MASK)
5523#define BCH_DEBUG0_TOG_KES_STANDALONE_MASK (0x800U)
5524#define BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT (11U)
5525/*! KES_STANDALONE
5526 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
5527 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
5528 */
5529#define BCH_DEBUG0_TOG_KES_STANDALONE(x) \
5530 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_TOG_KES_STANDALONE_MASK)
5531#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK (0x1000U)
5532#define BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT (12U)
5533#define BCH_DEBUG0_TOG_KES_DEBUG_KICK(x) \
5534 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_KICK_MASK)
5535#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK (0x2000U)
5536#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT (13U)
5537/*! KES_DEBUG_MODE4K
5538 * 0b1..Mode is set for 4K NAND pages.
5539 * 0b1..Mode is set for 2K NAND pages.
5540 */
5541#define BCH_DEBUG0_TOG_KES_DEBUG_MODE4K(x) \
5542 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_TOG_KES_DEBUG_MODE4K_MASK)
5543#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
5544#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
5545/*! KES_DEBUG_PAYLOAD_FLAG
5546 * 0b1..Payload is set for 512 bytes data block.
5547 * 0b1..Payload is set for 65 or 19 bytes auxiliary block.
5548 */
5549#define BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG(x) \
5550 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & \
5551 BCH_DEBUG0_TOG_KES_DEBUG_PAYLOAD_FLAG_MASK)
5552#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
5553#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
5554#define BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND(x) \
5555 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_SHIFT)) & \
5556 BCH_DEBUG0_TOG_KES_DEBUG_SHIFT_SYND_MASK)
5557#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
5558#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
5559/*! KES_DEBUG_SYNDROME_SYMBOL
5560 * 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
5561 * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
5562 */
5563#define BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL(x) \
5564 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & \
5565 BCH_DEBUG0_TOG_KES_DEBUG_SYNDROME_SYMBOL_MASK)
5566#define BCH_DEBUG0_TOG_RSVD1_MASK (0xFE000000U)
5567#define BCH_DEBUG0_TOG_RSVD1_SHIFT (25U)
5568#define BCH_DEBUG0_TOG_RSVD1(x) \
5569 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_TOG_RSVD1_SHIFT)) & BCH_DEBUG0_TOG_RSVD1_MASK)
5570/*! @} */
5571
5572/*! @name DBGKESREAD - KES Debug Read Register */
5573/*! @{ */
5574#define BCH_DBGKESREAD_VALUES_MASK (0xFFFFFFFFU)
5575#define BCH_DBGKESREAD_VALUES_SHIFT (0U)
5576#define BCH_DBGKESREAD_VALUES(x) \
5577 (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK)
5578/*! @} */
5579
5580/*! @name DBGCSFEREAD - Chien Search Debug Read Register */
5581/*! @{ */
5582#define BCH_DBGCSFEREAD_VALUES_MASK (0xFFFFFFFFU)
5583#define BCH_DBGCSFEREAD_VALUES_SHIFT (0U)
5584#define BCH_DBGCSFEREAD_VALUES(x) \
5585 (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK)
5586/*! @} */
5587
5588/*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */
5589/*! @{ */
5590#define BCH_DBGSYNDGENREAD_VALUES_MASK (0xFFFFFFFFU)
5591#define BCH_DBGSYNDGENREAD_VALUES_SHIFT (0U)
5592#define BCH_DBGSYNDGENREAD_VALUES(x) \
5593 (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK)
5594/*! @} */
5595
5596/*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */
5597/*! @{ */
5598#define BCH_DBGAHBMREAD_VALUES_MASK (0xFFFFFFFFU)
5599#define BCH_DBGAHBMREAD_VALUES_SHIFT (0U)
5600#define BCH_DBGAHBMREAD_VALUES(x) \
5601 (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK)
5602/*! @} */
5603
5604/*! @name BLOCKNAME - Block Name Register */
5605/*! @{ */
5606#define BCH_BLOCKNAME_NAME_MASK (0xFFFFFFFFU)
5607#define BCH_BLOCKNAME_NAME_SHIFT (0U)
5608#define BCH_BLOCKNAME_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK)
5609/*! @} */
5610
5611/*! @name VERSION - BCH Version Register */
5612/*! @{ */
5613#define BCH_VERSION_STEP_MASK (0xFFFFU)
5614#define BCH_VERSION_STEP_SHIFT (0U)
5615#define BCH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK)
5616#define BCH_VERSION_MINOR_MASK (0xFF0000U)
5617#define BCH_VERSION_MINOR_SHIFT (16U)
5618#define BCH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK)
5619#define BCH_VERSION_MAJOR_MASK (0xFF000000U)
5620#define BCH_VERSION_MAJOR_SHIFT (24U)
5621#define BCH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK)
5622/*! @} */
5623
5624/*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */
5625/*! @{ */
5626#define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK (0x1FFU)
5627#define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT (0U)
5628#define BCH_DEBUG1_ERASED_ZERO_COUNT(x) \
5629 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK)
5630#define BCH_DEBUG1_RSVD_MASK (0x7FFFFE00U)
5631#define BCH_DEBUG1_RSVD_SHIFT (9U)
5632#define BCH_DEBUG1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK)
5633#define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK (0x80000000U)
5634#define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT (31U)
5635/*! DEBUG1_PREERASECHK
5636 * 0b0..Turn off pre-erase check
5637 * 0b1..Turn on pre-erase check
5638 */
5639#define BCH_DEBUG1_DEBUG1_PREERASECHK(x) \
5640 (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK)
5641/*! @} */
5642
5643/*!
5644 * @}
5645 */ /* end of group BCH_Register_Masks */
5646
5647/* BCH - Peripheral instance base addresses */
5648/** Peripheral BCH base address */
5649#define BCH_BASE (0x33004000u)
5650/** Peripheral BCH base pointer */
5651#define BCH ((BCH_Type *)BCH_BASE)
5652/** Array initializer of BCH peripheral base addresses */
5653#define BCH_BASE_ADDRS \
5654 { \
5655 BCH_BASE \
5656 }
5657/** Array initializer of BCH peripheral base pointers */
5658#define BCH_BASE_PTRS \
5659 { \
5660 BCH \
5661 }
5662/** Interrupt vectors for the BCH peripheral type */
5663#define BCH_IRQS \
5664 { \
5665 BCH_IRQn \
5666 }
5667
5668/*!
5669 * @}
5670 */ /* end of group BCH_Peripheral_Access_Layer */
5671
5672/* ----------------------------------------------------------------------------
5673 -- CCM Peripheral Access Layer
5674 ---------------------------------------------------------------------------- */
5675
5676/*!
5677 * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
5678 * @{
5679 */
5680
5681/** CCM - Register Layout Typedef */
5682typedef struct
5683{
5684 __IO uint32_t GPR0; /**< General Purpose Register, offset: 0x0 */
5685 __IO uint32_t GPR0_SET; /**< General Purpose Register, offset: 0x4 */
5686 __IO uint32_t GPR0_CLR; /**< General Purpose Register, offset: 0x8 */
5687 __IO uint32_t GPR0_TOG; /**< General Purpose Register, offset: 0xC */
5688 uint8_t RESERVED_0[2032];
5689 struct
5690 { /* offset: 0x800, array step: 0x10 */
5691 __IO uint32_t PLL_CTRL; /**< CCM PLL Control Register, array offset: 0x800, array step: 0x10 */
5692 __IO uint32_t PLL_CTRL_SET; /**< CCM PLL Control Register, array offset: 0x804, array step: 0x10 */
5693 __IO uint32_t PLL_CTRL_CLR; /**< CCM PLL Control Register, array offset: 0x808, array step: 0x10 */
5694 __IO uint32_t PLL_CTRL_TOG; /**< CCM PLL Control Register, array offset: 0x80C, array step: 0x10 */
5695 } PLL_CTRL[39];
5696 uint8_t RESERVED_1[13712];
5697 struct
5698 { /* offset: 0x4000, array step: 0x10 */
5699 __IO uint32_t CCGR; /**< CCM Clock Gating Register, array offset: 0x4000, array step: 0x10 */
5700 __IO uint32_t CCGR_SET; /**< CCM Clock Gating Register, array offset: 0x4004, array step: 0x10 */
5701 __IO uint32_t CCGR_CLR; /**< CCM Clock Gating Register, array offset: 0x4008, array step: 0x10 */
5702 __IO uint32_t CCGR_TOG; /**< CCM Clock Gating Register, array offset: 0x400C, array step: 0x10 */
5703 } CCGR[103];
5704 uint8_t RESERVED_2[14736];
5705 struct
5706 { /* offset: 0x8000, array step: 0x80 */
5707 __IO uint32_t TARGET_ROOT; /**< Target Register, array offset: 0x8000, array step: 0x80 */
5708 __IO uint32_t TARGET_ROOT_SET; /**< Target Register, array offset: 0x8004, array step: 0x80 */
5709 __IO uint32_t TARGET_ROOT_CLR; /**< Target Register, array offset: 0x8008, array step: 0x80 */
5710 __IO uint32_t TARGET_ROOT_TOG; /**< Target Register, array offset: 0x800C, array step: 0x80 */
5711 __IO uint32_t MISC; /**< Miscellaneous Register, array offset: 0x8010, array step: 0x80 */
5712 __IO uint32_t MISC_ROOT_SET; /**< Miscellaneous Register, array offset: 0x8014, array step: 0x80 */
5713 __IO uint32_t MISC_ROOT_CLR; /**< Miscellaneous Register, array offset: 0x8018, array step: 0x80 */
5714 __IO uint32_t MISC_ROOT_TOG; /**< Miscellaneous Register, array offset: 0x801C, array step: 0x80 */
5715 __IO uint32_t POST; /**< Post Divider Register, array offset: 0x8020, array step: 0x80 */
5716 __IO uint32_t POST_ROOT_SET; /**< Post Divider Register, array offset: 0x8024, array step: 0x80 */
5717 __IO uint32_t POST_ROOT_CLR; /**< Post Divider Register, array offset: 0x8028, array step: 0x80 */
5718 __IO uint32_t POST_ROOT_TOG; /**< Post Divider Register, array offset: 0x802C, array step: 0x80 */
5719 __IO uint32_t PRE; /**< Pre Divider Register, array offset: 0x8030, array step: 0x80 */
5720 __IO uint32_t PRE_ROOT_SET; /**< Pre Divider Register, array offset: 0x8034, array step: 0x80 */
5721 __IO uint32_t PRE_ROOT_CLR; /**< Pre Divider Register, array offset: 0x8038, array step: 0x80 */
5722 __IO uint32_t PRE_ROOT_TOG; /**< Pre Divider Register, array offset: 0x803C, array step: 0x80 */
5723 uint8_t RESERVED_0[48];
5724 __IO uint32_t ACCESS_CTRL; /**< Access Control Register, array offset: 0x8070, array step: 0x80 */
5725 __IO uint32_t ACCESS_CTRL_ROOT_SET; /**< Access Control Register, array offset: 0x8074, array step: 0x80 */
5726 __IO uint32_t ACCESS_CTRL_ROOT_CLR; /**< Access Control Register, array offset: 0x8078, array step: 0x80 */
5727 __IO uint32_t ACCESS_CTRL_ROOT_TOG; /**< Access Control Register, array offset: 0x807C, array step: 0x80 */
5728 } ROOT[135];
5729} CCM_Type;
5730
5731/* ----------------------------------------------------------------------------
5732 -- CCM Register Masks
5733 ---------------------------------------------------------------------------- */
5734
5735/*!
5736 * @addtogroup CCM_Register_Masks CCM Register Masks
5737 * @{
5738 */
5739
5740/*! @name GPR0 - General Purpose Register */
5741/*! @{ */
5742#define CCM_GPR0_GP0_MASK (0xFFFFFFFFU)
5743#define CCM_GPR0_GP0_SHIFT (0U)
5744#define CCM_GPR0_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_GP0_SHIFT)) & CCM_GPR0_GP0_MASK)
5745/*! @} */
5746
5747/*! @name GPR0_SET - General Purpose Register */
5748/*! @{ */
5749#define CCM_GPR0_SET_GP0_MASK (0xFFFFFFFFU)
5750#define CCM_GPR0_SET_GP0_SHIFT (0U)
5751#define CCM_GPR0_SET_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_SET_GP0_SHIFT)) & CCM_GPR0_SET_GP0_MASK)
5752/*! @} */
5753
5754/*! @name GPR0_CLR - General Purpose Register */
5755/*! @{ */
5756#define CCM_GPR0_CLR_GP0_MASK (0xFFFFFFFFU)
5757#define CCM_GPR0_CLR_GP0_SHIFT (0U)
5758#define CCM_GPR0_CLR_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_CLR_GP0_SHIFT)) & CCM_GPR0_CLR_GP0_MASK)
5759/*! @} */
5760
5761/*! @name GPR0_TOG - General Purpose Register */
5762/*! @{ */
5763#define CCM_GPR0_TOG_GP0_MASK (0xFFFFFFFFU)
5764#define CCM_GPR0_TOG_GP0_SHIFT (0U)
5765#define CCM_GPR0_TOG_GP0(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR0_TOG_GP0_SHIFT)) & CCM_GPR0_TOG_GP0_MASK)
5766/*! @} */
5767
5768/*! @name PLL_CTRL - CCM PLL Control Register */
5769/*! @{ */
5770#define CCM_PLL_CTRL_SETTING0_MASK (0x3U)
5771#define CCM_PLL_CTRL_SETTING0_SHIFT (0U)
5772/*! SETTING0
5773 * 0b00..Domain clocks not needed
5774 * 0b01..Domain clocks needed when in RUN
5775 * 0b10..Domain clocks needed when in RUN and WAIT
5776 * 0b11..Domain clocks needed all the time
5777 */
5778#define CCM_PLL_CTRL_SETTING0(x) \
5779 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING0_SHIFT)) & CCM_PLL_CTRL_SETTING0_MASK)
5780#define CCM_PLL_CTRL_SETTING1_MASK (0x30U)
5781#define CCM_PLL_CTRL_SETTING1_SHIFT (4U)
5782/*! SETTING1
5783 * 0b00..Domain clocks not needed
5784 * 0b01..Domain clocks needed when in RUN
5785 * 0b10..Domain clocks needed when in RUN and WAIT
5786 * 0b11..Domain clocks needed all the time
5787 */
5788#define CCM_PLL_CTRL_SETTING1(x) \
5789 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING1_SHIFT)) & CCM_PLL_CTRL_SETTING1_MASK)
5790#define CCM_PLL_CTRL_SETTING2_MASK (0x300U)
5791#define CCM_PLL_CTRL_SETTING2_SHIFT (8U)
5792/*! SETTING2
5793 * 0b00..Domain clocks not needed
5794 * 0b01..Domain clocks needed when in RUN
5795 * 0b10..Domain clocks needed when in RUN and WAIT
5796 * 0b11..Domain clocks needed all the time
5797 */
5798#define CCM_PLL_CTRL_SETTING2(x) \
5799 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING2_SHIFT)) & CCM_PLL_CTRL_SETTING2_MASK)
5800#define CCM_PLL_CTRL_SETTING3_MASK (0x3000U)
5801#define CCM_PLL_CTRL_SETTING3_SHIFT (12U)
5802/*! SETTING3
5803 * 0b00..Domain clocks not needed
5804 * 0b01..Domain clocks needed when in RUN
5805 * 0b10..Domain clocks needed when in RUN and WAIT
5806 * 0b11..Domain clocks needed all the time
5807 */
5808#define CCM_PLL_CTRL_SETTING3(x) \
5809 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SETTING3_SHIFT)) & CCM_PLL_CTRL_SETTING3_MASK)
5810/*! @} */
5811
5812/* The count of CCM_PLL_CTRL */
5813#define CCM_PLL_CTRL_COUNT (39U)
5814
5815/*! @name PLL_CTRL_SET - CCM PLL Control Register */
5816/*! @{ */
5817#define CCM_PLL_CTRL_SET_SETTING0_MASK (0x3U)
5818#define CCM_PLL_CTRL_SET_SETTING0_SHIFT (0U)
5819/*! SETTING0
5820 * 0b00..Domain clocks not needed
5821 * 0b01..Domain clocks needed when in RUN
5822 * 0b10..Domain clocks needed when in RUN and WAIT
5823 * 0b11..Domain clocks needed all the time
5824 */
5825#define CCM_PLL_CTRL_SET_SETTING0(x) \
5826 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING0_SHIFT)) & CCM_PLL_CTRL_SET_SETTING0_MASK)
5827#define CCM_PLL_CTRL_SET_SETTING1_MASK (0x30U)
5828#define CCM_PLL_CTRL_SET_SETTING1_SHIFT (4U)
5829/*! SETTING1
5830 * 0b00..Domain clocks not needed
5831 * 0b01..Domain clocks needed when in RUN
5832 * 0b10..Domain clocks needed when in RUN and WAIT
5833 * 0b11..Domain clocks needed all the time
5834 */
5835#define CCM_PLL_CTRL_SET_SETTING1(x) \
5836 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING1_SHIFT)) & CCM_PLL_CTRL_SET_SETTING1_MASK)
5837#define CCM_PLL_CTRL_SET_SETTING2_MASK (0x300U)
5838#define CCM_PLL_CTRL_SET_SETTING2_SHIFT (8U)
5839/*! SETTING2
5840 * 0b00..Domain clocks not needed
5841 * 0b01..Domain clocks needed when in RUN
5842 * 0b10..Domain clocks needed when in RUN and WAIT
5843 * 0b11..Domain clocks needed all the time
5844 */
5845#define CCM_PLL_CTRL_SET_SETTING2(x) \
5846 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING2_SHIFT)) & CCM_PLL_CTRL_SET_SETTING2_MASK)
5847#define CCM_PLL_CTRL_SET_SETTING3_MASK (0x3000U)
5848#define CCM_PLL_CTRL_SET_SETTING3_SHIFT (12U)
5849/*! SETTING3
5850 * 0b00..Domain clocks not needed
5851 * 0b01..Domain clocks needed when in RUN
5852 * 0b10..Domain clocks needed when in RUN and WAIT
5853 * 0b11..Domain clocks needed all the time
5854 */
5855#define CCM_PLL_CTRL_SET_SETTING3(x) \
5856 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_SET_SETTING3_SHIFT)) & CCM_PLL_CTRL_SET_SETTING3_MASK)
5857/*! @} */
5858
5859/* The count of CCM_PLL_CTRL_SET */
5860#define CCM_PLL_CTRL_SET_COUNT (39U)
5861
5862/*! @name PLL_CTRL_CLR - CCM PLL Control Register */
5863/*! @{ */
5864#define CCM_PLL_CTRL_CLR_SETTING0_MASK (0x3U)
5865#define CCM_PLL_CTRL_CLR_SETTING0_SHIFT (0U)
5866/*! SETTING0
5867 * 0b00..Domain clocks not needed
5868 * 0b01..Domain clocks needed when in RUN
5869 * 0b10..Domain clocks needed when in RUN and WAIT
5870 * 0b11..Domain clocks needed all the time
5871 */
5872#define CCM_PLL_CTRL_CLR_SETTING0(x) \
5873 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING0_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING0_MASK)
5874#define CCM_PLL_CTRL_CLR_SETTING1_MASK (0x30U)
5875#define CCM_PLL_CTRL_CLR_SETTING1_SHIFT (4U)
5876/*! SETTING1
5877 * 0b00..Domain clocks not needed
5878 * 0b01..Domain clocks needed when in RUN
5879 * 0b10..Domain clocks needed when in RUN and WAIT
5880 * 0b11..Domain clocks needed all the time
5881 */
5882#define CCM_PLL_CTRL_CLR_SETTING1(x) \
5883 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING1_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING1_MASK)
5884#define CCM_PLL_CTRL_CLR_SETTING2_MASK (0x300U)
5885#define CCM_PLL_CTRL_CLR_SETTING2_SHIFT (8U)
5886/*! SETTING2
5887 * 0b00..Domain clocks not needed
5888 * 0b01..Domain clocks needed when in RUN
5889 * 0b10..Domain clocks needed when in RUN and WAIT
5890 * 0b11..Domain clocks needed all the time
5891 */
5892#define CCM_PLL_CTRL_CLR_SETTING2(x) \
5893 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING2_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING2_MASK)
5894#define CCM_PLL_CTRL_CLR_SETTING3_MASK (0x3000U)
5895#define CCM_PLL_CTRL_CLR_SETTING3_SHIFT (12U)
5896/*! SETTING3
5897 * 0b00..Domain clocks not needed
5898 * 0b01..Domain clocks needed when in RUN
5899 * 0b10..Domain clocks needed when in RUN and WAIT
5900 * 0b11..Domain clocks needed all the time
5901 */
5902#define CCM_PLL_CTRL_CLR_SETTING3(x) \
5903 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_CLR_SETTING3_SHIFT)) & CCM_PLL_CTRL_CLR_SETTING3_MASK)
5904/*! @} */
5905
5906/* The count of CCM_PLL_CTRL_CLR */
5907#define CCM_PLL_CTRL_CLR_COUNT (39U)
5908
5909/*! @name PLL_CTRL_TOG - CCM PLL Control Register */
5910/*! @{ */
5911#define CCM_PLL_CTRL_TOG_SETTING0_MASK (0x3U)
5912#define CCM_PLL_CTRL_TOG_SETTING0_SHIFT (0U)
5913/*! SETTING0
5914 * 0b00..Domain clocks not needed
5915 * 0b01..Domain clocks needed when in RUN
5916 * 0b10..Domain clocks needed when in RUN and WAIT
5917 * 0b11..Domain clocks needed all the time
5918 */
5919#define CCM_PLL_CTRL_TOG_SETTING0(x) \
5920 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING0_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING0_MASK)
5921#define CCM_PLL_CTRL_TOG_SETTING1_MASK (0x30U)
5922#define CCM_PLL_CTRL_TOG_SETTING1_SHIFT (4U)
5923/*! SETTING1
5924 * 0b00..Domain clocks not needed
5925 * 0b01..Domain clocks needed when in RUN
5926 * 0b10..Domain clocks needed when in RUN and WAIT
5927 * 0b11..Domain clocks needed all the time
5928 */
5929#define CCM_PLL_CTRL_TOG_SETTING1(x) \
5930 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING1_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING1_MASK)
5931#define CCM_PLL_CTRL_TOG_SETTING2_MASK (0x300U)
5932#define CCM_PLL_CTRL_TOG_SETTING2_SHIFT (8U)
5933/*! SETTING2
5934 * 0b00..Domain clocks not needed
5935 * 0b01..Domain clocks needed when in RUN
5936 * 0b10..Domain clocks needed when in RUN and WAIT
5937 * 0b11..Domain clocks needed all the time
5938 */
5939#define CCM_PLL_CTRL_TOG_SETTING2(x) \
5940 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING2_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING2_MASK)
5941#define CCM_PLL_CTRL_TOG_SETTING3_MASK (0x3000U)
5942#define CCM_PLL_CTRL_TOG_SETTING3_SHIFT (12U)
5943/*! SETTING3
5944 * 0b00..Domain clocks not needed
5945 * 0b01..Domain clocks needed when in RUN
5946 * 0b10..Domain clocks needed when in RUN and WAIT
5947 * 0b11..Domain clocks needed all the time
5948 */
5949#define CCM_PLL_CTRL_TOG_SETTING3(x) \
5950 (((uint32_t)(((uint32_t)(x)) << CCM_PLL_CTRL_TOG_SETTING3_SHIFT)) & CCM_PLL_CTRL_TOG_SETTING3_MASK)
5951/*! @} */
5952
5953/* The count of CCM_PLL_CTRL_TOG */
5954#define CCM_PLL_CTRL_TOG_COUNT (39U)
5955
5956/*! @name CCGR - CCM Clock Gating Register */
5957/*! @{ */
5958#define CCM_CCGR_SETTING0_MASK (0x3U)
5959#define CCM_CCGR_SETTING0_SHIFT (0U)
5960/*! SETTING0
5961 * 0b00..Domain clocks not needed
5962 * 0b01..Domain clocks needed when in RUN
5963 * 0b10..Domain clocks needed when in RUN and WAIT
5964 * 0b11..Domain clocks needed all the time
5965 */
5966#define CCM_CCGR_SETTING0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING0_SHIFT)) & CCM_CCGR_SETTING0_MASK)
5967#define CCM_CCGR_SETTING1_MASK (0x30U)
5968#define CCM_CCGR_SETTING1_SHIFT (4U)
5969/*! SETTING1
5970 * 0b00..Domain clocks not needed
5971 * 0b01..Domain clocks needed when in RUN
5972 * 0b10..Domain clocks needed when in RUN and WAIT
5973 * 0b11..Domain clocks needed all the time
5974 */
5975#define CCM_CCGR_SETTING1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING1_SHIFT)) & CCM_CCGR_SETTING1_MASK)
5976#define CCM_CCGR_SETTING2_MASK (0x300U)
5977#define CCM_CCGR_SETTING2_SHIFT (8U)
5978/*! SETTING2
5979 * 0b00..Domain clocks not needed
5980 * 0b01..Domain clocks needed when in RUN
5981 * 0b10..Domain clocks needed when in RUN and WAIT
5982 * 0b11..Domain clocks needed all the time
5983 */
5984#define CCM_CCGR_SETTING2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING2_SHIFT)) & CCM_CCGR_SETTING2_MASK)
5985#define CCM_CCGR_SETTING3_MASK (0x3000U)
5986#define CCM_CCGR_SETTING3_SHIFT (12U)
5987/*! SETTING3
5988 * 0b00..Domain clocks not needed
5989 * 0b01..Domain clocks needed when in RUN
5990 * 0b10..Domain clocks needed when in RUN and WAIT
5991 * 0b11..Domain clocks needed all the time
5992 */
5993#define CCM_CCGR_SETTING3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SETTING3_SHIFT)) & CCM_CCGR_SETTING3_MASK)
5994/*! @} */
5995
5996/* The count of CCM_CCGR */
5997#define CCM_CCGR_COUNT (103U)
5998
5999/*! @name CCGR_SET - CCM Clock Gating Register */
6000/*! @{ */
6001#define CCM_CCGR_SET_SETTING0_MASK (0x3U)
6002#define CCM_CCGR_SET_SETTING0_SHIFT (0U)
6003/*! SETTING0
6004 * 0b00..Domain clocks not needed
6005 * 0b01..Domain clocks needed when in RUN
6006 * 0b10..Domain clocks needed when in RUN and WAIT
6007 * 0b11..Domain clocks needed all the time
6008 */
6009#define CCM_CCGR_SET_SETTING0(x) \
6010 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING0_SHIFT)) & CCM_CCGR_SET_SETTING0_MASK)
6011#define CCM_CCGR_SET_SETTING1_MASK (0x30U)
6012#define CCM_CCGR_SET_SETTING1_SHIFT (4U)
6013/*! SETTING1
6014 * 0b00..Domain clocks not needed
6015 * 0b01..Domain clocks needed when in RUN
6016 * 0b10..Domain clocks needed when in RUN and WAIT
6017 * 0b11..Domain clocks needed all the time
6018 */
6019#define CCM_CCGR_SET_SETTING1(x) \
6020 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING1_SHIFT)) & CCM_CCGR_SET_SETTING1_MASK)
6021#define CCM_CCGR_SET_SETTING2_MASK (0x300U)
6022#define CCM_CCGR_SET_SETTING2_SHIFT (8U)
6023/*! SETTING2
6024 * 0b00..Domain clocks not needed
6025 * 0b01..Domain clocks needed when in RUN
6026 * 0b10..Domain clocks needed when in RUN and WAIT
6027 * 0b11..Domain clocks needed all the time
6028 */
6029#define CCM_CCGR_SET_SETTING2(x) \
6030 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING2_SHIFT)) & CCM_CCGR_SET_SETTING2_MASK)
6031#define CCM_CCGR_SET_SETTING3_MASK (0x3000U)
6032#define CCM_CCGR_SET_SETTING3_SHIFT (12U)
6033/*! SETTING3
6034 * 0b00..Domain clocks not needed
6035 * 0b01..Domain clocks needed when in RUN
6036 * 0b10..Domain clocks needed when in RUN and WAIT
6037 * 0b11..Domain clocks needed all the time
6038 */
6039#define CCM_CCGR_SET_SETTING3(x) \
6040 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_SET_SETTING3_SHIFT)) & CCM_CCGR_SET_SETTING3_MASK)
6041/*! @} */
6042
6043/* The count of CCM_CCGR_SET */
6044#define CCM_CCGR_SET_COUNT (103U)
6045
6046/*! @name CCGR_CLR - CCM Clock Gating Register */
6047/*! @{ */
6048#define CCM_CCGR_CLR_SETTING0_MASK (0x3U)
6049#define CCM_CCGR_CLR_SETTING0_SHIFT (0U)
6050/*! SETTING0
6051 * 0b00..Domain clocks not needed
6052 * 0b01..Domain clocks needed when in RUN
6053 * 0b10..Domain clocks needed when in RUN and WAIT
6054 * 0b11..Domain clocks needed all the time
6055 */
6056#define CCM_CCGR_CLR_SETTING0(x) \
6057 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING0_SHIFT)) & CCM_CCGR_CLR_SETTING0_MASK)
6058#define CCM_CCGR_CLR_SETTING1_MASK (0x30U)
6059#define CCM_CCGR_CLR_SETTING1_SHIFT (4U)
6060/*! SETTING1
6061 * 0b00..Domain clocks not needed
6062 * 0b01..Domain clocks needed when in RUN
6063 * 0b10..Domain clocks needed when in RUN and WAIT
6064 * 0b11..Domain clocks needed all the time
6065 */
6066#define CCM_CCGR_CLR_SETTING1(x) \
6067 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING1_SHIFT)) & CCM_CCGR_CLR_SETTING1_MASK)
6068#define CCM_CCGR_CLR_SETTING2_MASK (0x300U)
6069#define CCM_CCGR_CLR_SETTING2_SHIFT (8U)
6070/*! SETTING2
6071 * 0b00..Domain clocks not needed
6072 * 0b01..Domain clocks needed when in RUN
6073 * 0b10..Domain clocks needed when in RUN and WAIT
6074 * 0b11..Domain clocks needed all the time
6075 */
6076#define CCM_CCGR_CLR_SETTING2(x) \
6077 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING2_SHIFT)) & CCM_CCGR_CLR_SETTING2_MASK)
6078#define CCM_CCGR_CLR_SETTING3_MASK (0x3000U)
6079#define CCM_CCGR_CLR_SETTING3_SHIFT (12U)
6080/*! SETTING3
6081 * 0b00..Domain clocks not needed
6082 * 0b01..Domain clocks needed when in RUN
6083 * 0b10..Domain clocks needed when in RUN and WAIT
6084 * 0b11..Domain clocks needed all the time
6085 */
6086#define CCM_CCGR_CLR_SETTING3(x) \
6087 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_CLR_SETTING3_SHIFT)) & CCM_CCGR_CLR_SETTING3_MASK)
6088/*! @} */
6089
6090/* The count of CCM_CCGR_CLR */
6091#define CCM_CCGR_CLR_COUNT (103U)
6092
6093/*! @name CCGR_TOG - CCM Clock Gating Register */
6094/*! @{ */
6095#define CCM_CCGR_TOG_SETTING0_MASK (0x3U)
6096#define CCM_CCGR_TOG_SETTING0_SHIFT (0U)
6097/*! SETTING0
6098 * 0b00..Domain clocks not needed
6099 * 0b01..Domain clocks needed when in RUN
6100 * 0b10..Domain clocks needed when in RUN and WAIT
6101 * 0b11..Domain clocks needed all the time
6102 */
6103#define CCM_CCGR_TOG_SETTING0(x) \
6104 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING0_SHIFT)) & CCM_CCGR_TOG_SETTING0_MASK)
6105#define CCM_CCGR_TOG_SETTING1_MASK (0x30U)
6106#define CCM_CCGR_TOG_SETTING1_SHIFT (4U)
6107/*! SETTING1
6108 * 0b00..Domain clocks not needed
6109 * 0b01..Domain clocks needed when in RUN
6110 * 0b10..Domain clocks needed when in RUN and WAIT
6111 * 0b11..Domain clocks needed all the time
6112 */
6113#define CCM_CCGR_TOG_SETTING1(x) \
6114 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING1_SHIFT)) & CCM_CCGR_TOG_SETTING1_MASK)
6115#define CCM_CCGR_TOG_SETTING2_MASK (0x300U)
6116#define CCM_CCGR_TOG_SETTING2_SHIFT (8U)
6117/*! SETTING2
6118 * 0b00..Domain clocks not needed
6119 * 0b01..Domain clocks needed when in RUN
6120 * 0b10..Domain clocks needed when in RUN and WAIT
6121 * 0b11..Domain clocks needed all the time
6122 */
6123#define CCM_CCGR_TOG_SETTING2(x) \
6124 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING2_SHIFT)) & CCM_CCGR_TOG_SETTING2_MASK)
6125#define CCM_CCGR_TOG_SETTING3_MASK (0x3000U)
6126#define CCM_CCGR_TOG_SETTING3_SHIFT (12U)
6127/*! SETTING3
6128 * 0b00..Domain clocks not needed
6129 * 0b01..Domain clocks needed when in RUN
6130 * 0b10..Domain clocks needed when in RUN and WAIT
6131 * 0b11..Domain clocks needed all the time
6132 */
6133#define CCM_CCGR_TOG_SETTING3(x) \
6134 (((uint32_t)(((uint32_t)(x)) << CCM_CCGR_TOG_SETTING3_SHIFT)) & CCM_CCGR_TOG_SETTING3_MASK)
6135/*! @} */
6136
6137/* The count of CCM_CCGR_TOG */
6138#define CCM_CCGR_TOG_COUNT (103U)
6139
6140/*! @name TARGET_ROOT - Target Register */
6141/*! @{ */
6142#define CCM_TARGET_ROOT_POST_PODF_MASK (0x3FU)
6143#define CCM_TARGET_ROOT_POST_PODF_SHIFT (0U)
6144/*! POST_PODF
6145 * 0b000000..Divide by 1
6146 * 0b000001..Divide by 2
6147 * 0b000010..Divide by 3
6148 * 0b000011..Divide by 4
6149 * 0b000100..Divide by 5
6150 * 0b000101..Divide by 6
6151 * 0b111111..Divide by 64
6152 */
6153#define CCM_TARGET_ROOT_POST_PODF(x) \
6154 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_POST_PODF_MASK)
6155#define CCM_TARGET_ROOT_PRE_PODF_MASK (0x70000U)
6156#define CCM_TARGET_ROOT_PRE_PODF_SHIFT (16U)
6157/*! PRE_PODF
6158 * 0b000..Divide by 1
6159 * 0b001..Divide by 2
6160 * 0b010..Divide by 3
6161 * 0b011..Divide by 4
6162 * 0b100..Divide by 5
6163 * 0b101..Divide by 6
6164 * 0b110..Divide by 7
6165 * 0b111..Divide by 8
6166 */
6167#define CCM_TARGET_ROOT_PRE_PODF(x) \
6168 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_PRE_PODF_MASK)
6169#define CCM_TARGET_ROOT_MUX_MASK (0x7000000U)
6170#define CCM_TARGET_ROOT_MUX_SHIFT (24U)
6171#define CCM_TARGET_ROOT_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_MUX_SHIFT)) & CCM_TARGET_ROOT_MUX_MASK)
6172#define CCM_TARGET_ROOT_ENABLE_MASK (0x10000000U)
6173#define CCM_TARGET_ROOT_ENABLE_SHIFT (28U)
6174/*! ENABLE
6175 * 0b0..clock root is OFF
6176 * 0b1..clock root is ON
6177 */
6178#define CCM_TARGET_ROOT_ENABLE(x) \
6179 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_ENABLE_SHIFT)) & CCM_TARGET_ROOT_ENABLE_MASK)
6180/*! @} */
6181
6182/* The count of CCM_TARGET_ROOT */
6183#define CCM_TARGET_ROOT_COUNT (135U)
6184
6185/*! @name TARGET_ROOT_SET - Target Register */
6186/*! @{ */
6187#define CCM_TARGET_ROOT_SET_POST_PODF_MASK (0x3FU)
6188#define CCM_TARGET_ROOT_SET_POST_PODF_SHIFT (0U)
6189/*! POST_PODF
6190 * 0b000000..Divide by 1
6191 * 0b000001..Divide by 2
6192 * 0b000010..Divide by 3
6193 * 0b000011..Divide by 4
6194 * 0b000100..Divide by 5
6195 * 0b000101..Divide by 6
6196 * 0b111111..Divide by 64
6197 */
6198#define CCM_TARGET_ROOT_SET_POST_PODF(x) \
6199 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_SET_POST_PODF_MASK)
6200#define CCM_TARGET_ROOT_SET_PRE_PODF_MASK (0x70000U)
6201#define CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT (16U)
6202/*! PRE_PODF
6203 * 0b000..Divide by 1
6204 * 0b001..Divide by 2
6205 * 0b010..Divide by 3
6206 * 0b011..Divide by 4
6207 * 0b100..Divide by 5
6208 * 0b101..Divide by 6
6209 * 0b110..Divide by 7
6210 * 0b111..Divide by 8
6211 */
6212#define CCM_TARGET_ROOT_SET_PRE_PODF(x) \
6213 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_SET_PRE_PODF_MASK)
6214#define CCM_TARGET_ROOT_SET_MUX_MASK (0x7000000U)
6215#define CCM_TARGET_ROOT_SET_MUX_SHIFT (24U)
6216#define CCM_TARGET_ROOT_SET_MUX(x) \
6217 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_MUX_SHIFT)) & CCM_TARGET_ROOT_SET_MUX_MASK)
6218#define CCM_TARGET_ROOT_SET_ENABLE_MASK (0x10000000U)
6219#define CCM_TARGET_ROOT_SET_ENABLE_SHIFT (28U)
6220/*! ENABLE
6221 * 0b0..clock root is OFF
6222 * 0b1..clock root is ON
6223 */
6224#define CCM_TARGET_ROOT_SET_ENABLE(x) \
6225 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_SET_ENABLE_SHIFT)) & CCM_TARGET_ROOT_SET_ENABLE_MASK)
6226/*! @} */
6227
6228/* The count of CCM_TARGET_ROOT_SET */
6229#define CCM_TARGET_ROOT_SET_COUNT (135U)
6230
6231/*! @name TARGET_ROOT_CLR - Target Register */
6232/*! @{ */
6233#define CCM_TARGET_ROOT_CLR_POST_PODF_MASK (0x3FU)
6234#define CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT (0U)
6235/*! POST_PODF
6236 * 0b000000..Divide by 1
6237 * 0b000001..Divide by 2
6238 * 0b000010..Divide by 3
6239 * 0b000011..Divide by 4
6240 * 0b000100..Divide by 5
6241 * 0b000101..Divide by 6
6242 * 0b111111..Divide by 64
6243 */
6244#define CCM_TARGET_ROOT_CLR_POST_PODF(x) \
6245 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_CLR_POST_PODF_MASK)
6246#define CCM_TARGET_ROOT_CLR_PRE_PODF_MASK (0x70000U)
6247#define CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT (16U)
6248/*! PRE_PODF
6249 * 0b000..Divide by 1
6250 * 0b001..Divide by 2
6251 * 0b010..Divide by 3
6252 * 0b011..Divide by 4
6253 * 0b100..Divide by 5
6254 * 0b101..Divide by 6
6255 * 0b110..Divide by 7
6256 * 0b111..Divide by 8
6257 */
6258#define CCM_TARGET_ROOT_CLR_PRE_PODF(x) \
6259 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_CLR_PRE_PODF_MASK)
6260#define CCM_TARGET_ROOT_CLR_MUX_MASK (0x7000000U)
6261#define CCM_TARGET_ROOT_CLR_MUX_SHIFT (24U)
6262#define CCM_TARGET_ROOT_CLR_MUX(x) \
6263 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_MUX_SHIFT)) & CCM_TARGET_ROOT_CLR_MUX_MASK)
6264#define CCM_TARGET_ROOT_CLR_ENABLE_MASK (0x10000000U)
6265#define CCM_TARGET_ROOT_CLR_ENABLE_SHIFT (28U)
6266/*! ENABLE
6267 * 0b0..clock root is OFF
6268 * 0b1..clock root is ON
6269 */
6270#define CCM_TARGET_ROOT_CLR_ENABLE(x) \
6271 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_CLR_ENABLE_SHIFT)) & CCM_TARGET_ROOT_CLR_ENABLE_MASK)
6272/*! @} */
6273
6274/* The count of CCM_TARGET_ROOT_CLR */
6275#define CCM_TARGET_ROOT_CLR_COUNT (135U)
6276
6277/*! @name TARGET_ROOT_TOG - Target Register */
6278/*! @{ */
6279#define CCM_TARGET_ROOT_TOG_POST_PODF_MASK (0x3FU)
6280#define CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT (0U)
6281/*! POST_PODF
6282 * 0b000000..Divide by 1
6283 * 0b000001..Divide by 2
6284 * 0b000010..Divide by 3
6285 * 0b000011..Divide by 4
6286 * 0b000100..Divide by 5
6287 * 0b000101..Divide by 6
6288 * 0b111111..Divide by 64
6289 */
6290#define CCM_TARGET_ROOT_TOG_POST_PODF(x) \
6291 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_POST_PODF_SHIFT)) & CCM_TARGET_ROOT_TOG_POST_PODF_MASK)
6292#define CCM_TARGET_ROOT_TOG_PRE_PODF_MASK (0x70000U)
6293#define CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT (16U)
6294/*! PRE_PODF
6295 * 0b000..Divide by 1
6296 * 0b001..Divide by 2
6297 * 0b010..Divide by 3
6298 * 0b011..Divide by 4
6299 * 0b100..Divide by 5
6300 * 0b101..Divide by 6
6301 * 0b110..Divide by 7
6302 * 0b111..Divide by 8
6303 */
6304#define CCM_TARGET_ROOT_TOG_PRE_PODF(x) \
6305 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_PRE_PODF_SHIFT)) & CCM_TARGET_ROOT_TOG_PRE_PODF_MASK)
6306#define CCM_TARGET_ROOT_TOG_MUX_MASK (0x7000000U)
6307#define CCM_TARGET_ROOT_TOG_MUX_SHIFT (24U)
6308#define CCM_TARGET_ROOT_TOG_MUX(x) \
6309 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_MUX_SHIFT)) & CCM_TARGET_ROOT_TOG_MUX_MASK)
6310#define CCM_TARGET_ROOT_TOG_ENABLE_MASK (0x10000000U)
6311#define CCM_TARGET_ROOT_TOG_ENABLE_SHIFT (28U)
6312/*! ENABLE
6313 * 0b0..clock root is OFF
6314 * 0b1..clock root is ON
6315 */
6316#define CCM_TARGET_ROOT_TOG_ENABLE(x) \
6317 (((uint32_t)(((uint32_t)(x)) << CCM_TARGET_ROOT_TOG_ENABLE_SHIFT)) & CCM_TARGET_ROOT_TOG_ENABLE_MASK)
6318/*! @} */
6319
6320/* The count of CCM_TARGET_ROOT_TOG */
6321#define CCM_TARGET_ROOT_TOG_COUNT (135U)
6322
6323/*! @name MISC - Miscellaneous Register */
6324/*! @{ */
6325#define CCM_MISC_AUTHEN_FAIL_MASK (0x1U)
6326#define CCM_MISC_AUTHEN_FAIL_SHIFT (0U)
6327#define CCM_MISC_AUTHEN_FAIL(x) \
6328 (((uint32_t)(((uint32_t)(x)) << CCM_MISC_AUTHEN_FAIL_SHIFT)) & CCM_MISC_AUTHEN_FAIL_MASK)
6329#define CCM_MISC_TIMEOUT_MASK (0x10U)
6330#define CCM_MISC_TIMEOUT_SHIFT (4U)
6331#define CCM_MISC_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_TIMEOUT_SHIFT)) & CCM_MISC_TIMEOUT_MASK)
6332#define CCM_MISC_VIOLATE_MASK (0x100U)
6333#define CCM_MISC_VIOLATE_SHIFT (8U)
6334#define CCM_MISC_VIOLATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_MISC_VIOLATE_SHIFT)) & CCM_MISC_VIOLATE_MASK)
6335/*! @} */
6336
6337/* The count of CCM_MISC */
6338#define CCM_MISC_COUNT (135U)
6339
6340/*! @name MISC_ROOT_SET - Miscellaneous Register */
6341/*! @{ */
6342#define CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK (0x1U)
6343#define CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT (0U)
6344#define CCM_MISC_ROOT_SET_AUTHEN_FAIL(x) \
6345 (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_SET_AUTHEN_FAIL_MASK)
6346#define CCM_MISC_ROOT_SET_TIMEOUT_MASK (0x10U)
6347#define CCM_MISC_ROOT_SET_TIMEOUT_SHIFT (4U)
6348#define CCM_MISC_ROOT_SET_TIMEOUT(x) \
6349 (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_SET_TIMEOUT_MASK)
6350#define CCM_MISC_ROOT_SET_VIOLATE_MASK (0x100U)
6351#define CCM_MISC_ROOT_SET_VIOLATE_SHIFT (8U)
6352#define CCM_MISC_ROOT_SET_VIOLATE(x) \
6353 (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_SET_VIOLATE_SHIFT)) & CCM_MISC_ROOT_SET_VIOLATE_MASK)
6354/*! @} */
6355
6356/* The count of CCM_MISC_ROOT_SET */
6357#define CCM_MISC_ROOT_SET_COUNT (135U)
6358
6359/*! @name MISC_ROOT_CLR - Miscellaneous Register */
6360/*! @{ */
6361#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK (0x1U)
6362#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT (0U)
6363#define CCM_MISC_ROOT_CLR_AUTHEN_FAIL(x) \
6364 (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_CLR_AUTHEN_FAIL_MASK)
6365#define CCM_MISC_ROOT_CLR_TIMEOUT_MASK (0x10U)
6366#define CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT (4U)
6367#define CCM_MISC_ROOT_CLR_TIMEOUT(x) \
6368 (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_CLR_TIMEOUT_MASK)
6369#define CCM_MISC_ROOT_CLR_VIOLATE_MASK (0x100U)
6370#define CCM_MISC_ROOT_CLR_VIOLATE_SHIFT (8U)
6371#define CCM_MISC_ROOT_CLR_VIOLATE(x) \
6372 (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_CLR_VIOLATE_SHIFT)) & CCM_MISC_ROOT_CLR_VIOLATE_MASK)
6373/*! @} */
6374
6375/* The count of CCM_MISC_ROOT_CLR */
6376#define CCM_MISC_ROOT_CLR_COUNT (135U)
6377
6378/*! @name MISC_ROOT_TOG - Miscellaneous Register */
6379/*! @{ */
6380#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK (0x1U)
6381#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT (0U)
6382#define CCM_MISC_ROOT_TOG_AUTHEN_FAIL(x) \
6383 (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_AUTHEN_FAIL_SHIFT)) & CCM_MISC_ROOT_TOG_AUTHEN_FAIL_MASK)
6384#define CCM_MISC_ROOT_TOG_TIMEOUT_MASK (0x10U)
6385#define CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT (4U)
6386#define CCM_MISC_ROOT_TOG_TIMEOUT(x) \
6387 (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_TIMEOUT_SHIFT)) & CCM_MISC_ROOT_TOG_TIMEOUT_MASK)
6388#define CCM_MISC_ROOT_TOG_VIOLATE_MASK (0x100U)
6389#define CCM_MISC_ROOT_TOG_VIOLATE_SHIFT (8U)
6390#define CCM_MISC_ROOT_TOG_VIOLATE(x) \
6391 (((uint32_t)(((uint32_t)(x)) << CCM_MISC_ROOT_TOG_VIOLATE_SHIFT)) & CCM_MISC_ROOT_TOG_VIOLATE_MASK)
6392/*! @} */
6393
6394/* The count of CCM_MISC_ROOT_TOG */
6395#define CCM_MISC_ROOT_TOG_COUNT (135U)
6396
6397/*! @name POST - Post Divider Register */
6398/*! @{ */
6399#define CCM_POST_POST_PODF_MASK (0x3FU)
6400#define CCM_POST_POST_PODF_SHIFT (0U)
6401/*! POST_PODF
6402 * 0b000000..Divide by 1
6403 * 0b000001..Divide by 2
6404 * 0b000010..Divide by 3
6405 * 0b000011..Divide by 4
6406 * 0b000100..Divide by 5
6407 * 0b000101..Divide by 6
6408 * 0b111111..Divide by 64
6409 */
6410#define CCM_POST_POST_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_POST_PODF_SHIFT)) & CCM_POST_POST_PODF_MASK)
6411#define CCM_POST_BUSY1_MASK (0x80U)
6412#define CCM_POST_BUSY1_SHIFT (7U)
6413#define CCM_POST_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_BUSY1_SHIFT)) & CCM_POST_BUSY1_MASK)
6414#define CCM_POST_SELECT_MASK (0x10000000U)
6415#define CCM_POST_SELECT_SHIFT (28U)
6416/*! SELECT
6417 * 0b0..select branch A
6418 * 0b1..select branch B
6419 */
6420#define CCM_POST_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_SELECT_SHIFT)) & CCM_POST_SELECT_MASK)
6421#define CCM_POST_BUSY2_MASK (0x80000000U)
6422#define CCM_POST_BUSY2_SHIFT (31U)
6423#define CCM_POST_BUSY2(x) (((uint32_t)(((uint32_t)(x)) << CCM_POST_BUSY2_SHIFT)) & CCM_POST_BUSY2_MASK)
6424/*! @} */
6425
6426/* The count of CCM_POST */
6427#define CCM_POST_COUNT (135U)
6428
6429/*! @name POST_ROOT_SET - Post Divider Register */
6430/*! @{ */
6431#define CCM_POST_ROOT_SET_POST_PODF_MASK (0x3FU)
6432#define CCM_POST_ROOT_SET_POST_PODF_SHIFT (0U)
6433/*! POST_PODF
6434 * 0b000000..Divide by 1
6435 * 0b000001..Divide by 2
6436 * 0b000010..Divide by 3
6437 * 0b000011..Divide by 4
6438 * 0b000100..Divide by 5
6439 * 0b000101..Divide by 6
6440 * 0b111111..Divide by 64
6441 */
6442#define CCM_POST_ROOT_SET_POST_PODF(x) \
6443 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_POST_PODF_SHIFT)) & CCM_POST_ROOT_SET_POST_PODF_MASK)
6444#define CCM_POST_ROOT_SET_BUSY1_MASK (0x80U)
6445#define CCM_POST_ROOT_SET_BUSY1_SHIFT (7U)
6446#define CCM_POST_ROOT_SET_BUSY1(x) \
6447 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_BUSY1_SHIFT)) & CCM_POST_ROOT_SET_BUSY1_MASK)
6448#define CCM_POST_ROOT_SET_SELECT_MASK (0x10000000U)
6449#define CCM_POST_ROOT_SET_SELECT_SHIFT (28U)
6450/*! SELECT
6451 * 0b0..select branch A
6452 * 0b1..select branch B
6453 */
6454#define CCM_POST_ROOT_SET_SELECT(x) \
6455 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_SELECT_SHIFT)) & CCM_POST_ROOT_SET_SELECT_MASK)
6456#define CCM_POST_ROOT_SET_BUSY2_MASK (0x80000000U)
6457#define CCM_POST_ROOT_SET_BUSY2_SHIFT (31U)
6458#define CCM_POST_ROOT_SET_BUSY2(x) \
6459 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_SET_BUSY2_SHIFT)) & CCM_POST_ROOT_SET_BUSY2_MASK)
6460/*! @} */
6461
6462/* The count of CCM_POST_ROOT_SET */
6463#define CCM_POST_ROOT_SET_COUNT (135U)
6464
6465/*! @name POST_ROOT_CLR - Post Divider Register */
6466/*! @{ */
6467#define CCM_POST_ROOT_CLR_POST_PODF_MASK (0x3FU)
6468#define CCM_POST_ROOT_CLR_POST_PODF_SHIFT (0U)
6469/*! POST_PODF
6470 * 0b000000..Divide by 1
6471 * 0b000001..Divide by 2
6472 * 0b000010..Divide by 3
6473 * 0b000011..Divide by 4
6474 * 0b000100..Divide by 5
6475 * 0b000101..Divide by 6
6476 * 0b111111..Divide by 64
6477 */
6478#define CCM_POST_ROOT_CLR_POST_PODF(x) \
6479 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_POST_PODF_SHIFT)) & CCM_POST_ROOT_CLR_POST_PODF_MASK)
6480#define CCM_POST_ROOT_CLR_BUSY1_MASK (0x80U)
6481#define CCM_POST_ROOT_CLR_BUSY1_SHIFT (7U)
6482#define CCM_POST_ROOT_CLR_BUSY1(x) \
6483 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_BUSY1_SHIFT)) & CCM_POST_ROOT_CLR_BUSY1_MASK)
6484#define CCM_POST_ROOT_CLR_SELECT_MASK (0x10000000U)
6485#define CCM_POST_ROOT_CLR_SELECT_SHIFT (28U)
6486/*! SELECT
6487 * 0b0..select branch A
6488 * 0b1..select branch B
6489 */
6490#define CCM_POST_ROOT_CLR_SELECT(x) \
6491 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_SELECT_SHIFT)) & CCM_POST_ROOT_CLR_SELECT_MASK)
6492#define CCM_POST_ROOT_CLR_BUSY2_MASK (0x80000000U)
6493#define CCM_POST_ROOT_CLR_BUSY2_SHIFT (31U)
6494#define CCM_POST_ROOT_CLR_BUSY2(x) \
6495 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_CLR_BUSY2_SHIFT)) & CCM_POST_ROOT_CLR_BUSY2_MASK)
6496/*! @} */
6497
6498/* The count of CCM_POST_ROOT_CLR */
6499#define CCM_POST_ROOT_CLR_COUNT (135U)
6500
6501/*! @name POST_ROOT_TOG - Post Divider Register */
6502/*! @{ */
6503#define CCM_POST_ROOT_TOG_POST_PODF_MASK (0x3FU)
6504#define CCM_POST_ROOT_TOG_POST_PODF_SHIFT (0U)
6505/*! POST_PODF
6506 * 0b000000..Divide by 1
6507 * 0b000001..Divide by 2
6508 * 0b000010..Divide by 3
6509 * 0b000011..Divide by 4
6510 * 0b000100..Divide by 5
6511 * 0b000101..Divide by 6
6512 * 0b111111..Divide by 64
6513 */
6514#define CCM_POST_ROOT_TOG_POST_PODF(x) \
6515 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_POST_PODF_SHIFT)) & CCM_POST_ROOT_TOG_POST_PODF_MASK)
6516#define CCM_POST_ROOT_TOG_BUSY1_MASK (0x80U)
6517#define CCM_POST_ROOT_TOG_BUSY1_SHIFT (7U)
6518#define CCM_POST_ROOT_TOG_BUSY1(x) \
6519 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_BUSY1_SHIFT)) & CCM_POST_ROOT_TOG_BUSY1_MASK)
6520#define CCM_POST_ROOT_TOG_SELECT_MASK (0x10000000U)
6521#define CCM_POST_ROOT_TOG_SELECT_SHIFT (28U)
6522/*! SELECT
6523 * 0b0..select branch A
6524 * 0b1..select branch B
6525 */
6526#define CCM_POST_ROOT_TOG_SELECT(x) \
6527 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_SELECT_SHIFT)) & CCM_POST_ROOT_TOG_SELECT_MASK)
6528#define CCM_POST_ROOT_TOG_BUSY2_MASK (0x80000000U)
6529#define CCM_POST_ROOT_TOG_BUSY2_SHIFT (31U)
6530#define CCM_POST_ROOT_TOG_BUSY2(x) \
6531 (((uint32_t)(((uint32_t)(x)) << CCM_POST_ROOT_TOG_BUSY2_SHIFT)) & CCM_POST_ROOT_TOG_BUSY2_MASK)
6532/*! @} */
6533
6534/* The count of CCM_POST_ROOT_TOG */
6535#define CCM_POST_ROOT_TOG_COUNT (135U)
6536
6537/*! @name PRE - Pre Divider Register */
6538/*! @{ */
6539#define CCM_PRE_PRE_PODF_B_MASK (0x7U)
6540#define CCM_PRE_PRE_PODF_B_SHIFT (0U)
6541/*! PRE_PODF_B
6542 * 0b000..Divide by 1
6543 * 0b001..Divide by 2
6544 * 0b010..Divide by 3
6545 * 0b011..Divide by 4
6546 * 0b100..Divide by 5
6547 * 0b101..Divide by 6
6548 * 0b110..Divide by 7
6549 * 0b111..Divide by 8
6550 */
6551#define CCM_PRE_PRE_PODF_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_PRE_PODF_B_SHIFT)) & CCM_PRE_PRE_PODF_B_MASK)
6552#define CCM_PRE_BUSY0_MASK (0x8U)
6553#define CCM_PRE_BUSY0_SHIFT (3U)
6554#define CCM_PRE_BUSY0(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY0_SHIFT)) & CCM_PRE_BUSY0_MASK)
6555#define CCM_PRE_MUX_B_MASK (0x700U)
6556#define CCM_PRE_MUX_B_SHIFT (8U)
6557#define CCM_PRE_MUX_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_MUX_B_SHIFT)) & CCM_PRE_MUX_B_MASK)
6558#define CCM_PRE_EN_B_MASK (0x1000U)
6559#define CCM_PRE_EN_B_SHIFT (12U)
6560/*! EN_B
6561 * 0b0..Clock shutdown
6562 * 0b1..Clock ON
6563 */
6564#define CCM_PRE_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_EN_B_SHIFT)) & CCM_PRE_EN_B_MASK)
6565#define CCM_PRE_BUSY1_MASK (0x8000U)
6566#define CCM_PRE_BUSY1_SHIFT (15U)
6567#define CCM_PRE_BUSY1(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY1_SHIFT)) & CCM_PRE_BUSY1_MASK)
6568#define CCM_PRE_PRE_PODF_A_MASK (0x70000U)
6569#define CCM_PRE_PRE_PODF_A_SHIFT (16U)
6570/*! PRE_PODF_A
6571 * 0b000..Divide by 1
6572 * 0b001..Divide by 2
6573 * 0b010..Divide by 3
6574 * 0b011..Divide by 4
6575 * 0b100..Divide by 5
6576 * 0b101..Divide by 6
6577 * 0b110..Divide by 7
6578 * 0b111..Divide by 8
6579 */
6580#define CCM_PRE_PRE_PODF_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_PRE_PODF_A_SHIFT)) & CCM_PRE_PRE_PODF_A_MASK)
6581#define CCM_PRE_BUSY3_MASK (0x80000U)
6582#define CCM_PRE_BUSY3_SHIFT (19U)
6583#define CCM_PRE_BUSY3(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY3_SHIFT)) & CCM_PRE_BUSY3_MASK)
6584#define CCM_PRE_MUX_A_MASK (0x7000000U)
6585#define CCM_PRE_MUX_A_SHIFT (24U)
6586#define CCM_PRE_MUX_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_MUX_A_SHIFT)) & CCM_PRE_MUX_A_MASK)
6587#define CCM_PRE_EN_A_MASK (0x10000000U)
6588#define CCM_PRE_EN_A_SHIFT (28U)
6589/*! EN_A
6590 * 0b0..Clock shutdown
6591 * 0b1..clock ON
6592 */
6593#define CCM_PRE_EN_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_EN_A_SHIFT)) & CCM_PRE_EN_A_MASK)
6594#define CCM_PRE_BUSY4_MASK (0x80000000U)
6595#define CCM_PRE_BUSY4_SHIFT (31U)
6596#define CCM_PRE_BUSY4(x) (((uint32_t)(((uint32_t)(x)) << CCM_PRE_BUSY4_SHIFT)) & CCM_PRE_BUSY4_MASK)
6597/*! @} */
6598
6599/* The count of CCM_PRE */
6600#define CCM_PRE_COUNT (135U)
6601
6602/*! @name PRE_ROOT_SET - Pre Divider Register */
6603/*! @{ */
6604#define CCM_PRE_ROOT_SET_PRE_PODF_B_MASK (0x7U)
6605#define CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT (0U)
6606/*! PRE_PODF_B
6607 * 0b000..Divide by 1
6608 * 0b001..Divide by 2
6609 * 0b010..Divide by 3
6610 * 0b011..Divide by 4
6611 * 0b100..Divide by 5
6612 * 0b101..Divide by 6
6613 * 0b110..Divide by 7
6614 * 0b111..Divide by 8
6615 */
6616#define CCM_PRE_ROOT_SET_PRE_PODF_B(x) \
6617 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_SET_PRE_PODF_B_MASK)
6618#define CCM_PRE_ROOT_SET_BUSY0_MASK (0x8U)
6619#define CCM_PRE_ROOT_SET_BUSY0_SHIFT (3U)
6620#define CCM_PRE_ROOT_SET_BUSY0(x) \
6621 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY0_SHIFT)) & CCM_PRE_ROOT_SET_BUSY0_MASK)
6622#define CCM_PRE_ROOT_SET_MUX_B_MASK (0x700U)
6623#define CCM_PRE_ROOT_SET_MUX_B_SHIFT (8U)
6624#define CCM_PRE_ROOT_SET_MUX_B(x) \
6625 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_MUX_B_SHIFT)) & CCM_PRE_ROOT_SET_MUX_B_MASK)
6626#define CCM_PRE_ROOT_SET_EN_B_MASK (0x1000U)
6627#define CCM_PRE_ROOT_SET_EN_B_SHIFT (12U)
6628/*! EN_B
6629 * 0b0..Clock shutdown
6630 * 0b1..Clock ON
6631 */
6632#define CCM_PRE_ROOT_SET_EN_B(x) \
6633 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_EN_B_SHIFT)) & CCM_PRE_ROOT_SET_EN_B_MASK)
6634#define CCM_PRE_ROOT_SET_BUSY1_MASK (0x8000U)
6635#define CCM_PRE_ROOT_SET_BUSY1_SHIFT (15U)
6636#define CCM_PRE_ROOT_SET_BUSY1(x) \
6637 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY1_SHIFT)) & CCM_PRE_ROOT_SET_BUSY1_MASK)
6638#define CCM_PRE_ROOT_SET_PRE_PODF_A_MASK (0x70000U)
6639#define CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT (16U)
6640/*! PRE_PODF_A
6641 * 0b000..Divide by 1
6642 * 0b001..Divide by 2
6643 * 0b010..Divide by 3
6644 * 0b011..Divide by 4
6645 * 0b100..Divide by 5
6646 * 0b101..Divide by 6
6647 * 0b110..Divide by 7
6648 * 0b111..Divide by 8
6649 */
6650#define CCM_PRE_ROOT_SET_PRE_PODF_A(x) \
6651 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_SET_PRE_PODF_A_MASK)
6652#define CCM_PRE_ROOT_SET_BUSY3_MASK (0x80000U)
6653#define CCM_PRE_ROOT_SET_BUSY3_SHIFT (19U)
6654#define CCM_PRE_ROOT_SET_BUSY3(x) \
6655 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY3_SHIFT)) & CCM_PRE_ROOT_SET_BUSY3_MASK)
6656#define CCM_PRE_ROOT_SET_MUX_A_MASK (0x7000000U)
6657#define CCM_PRE_ROOT_SET_MUX_A_SHIFT (24U)
6658#define CCM_PRE_ROOT_SET_MUX_A(x) \
6659 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_MUX_A_SHIFT)) & CCM_PRE_ROOT_SET_MUX_A_MASK)
6660#define CCM_PRE_ROOT_SET_EN_A_MASK (0x10000000U)
6661#define CCM_PRE_ROOT_SET_EN_A_SHIFT (28U)
6662/*! EN_A
6663 * 0b0..Clock shutdown
6664 * 0b1..clock ON
6665 */
6666#define CCM_PRE_ROOT_SET_EN_A(x) \
6667 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_EN_A_SHIFT)) & CCM_PRE_ROOT_SET_EN_A_MASK)
6668#define CCM_PRE_ROOT_SET_BUSY4_MASK (0x80000000U)
6669#define CCM_PRE_ROOT_SET_BUSY4_SHIFT (31U)
6670#define CCM_PRE_ROOT_SET_BUSY4(x) \
6671 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_SET_BUSY4_SHIFT)) & CCM_PRE_ROOT_SET_BUSY4_MASK)
6672/*! @} */
6673
6674/* The count of CCM_PRE_ROOT_SET */
6675#define CCM_PRE_ROOT_SET_COUNT (135U)
6676
6677/*! @name PRE_ROOT_CLR - Pre Divider Register */
6678/*! @{ */
6679#define CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK (0x7U)
6680#define CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT (0U)
6681/*! PRE_PODF_B
6682 * 0b000..Divide by 1
6683 * 0b001..Divide by 2
6684 * 0b010..Divide by 3
6685 * 0b011..Divide by 4
6686 * 0b100..Divide by 5
6687 * 0b101..Divide by 6
6688 * 0b110..Divide by 7
6689 * 0b111..Divide by 8
6690 */
6691#define CCM_PRE_ROOT_CLR_PRE_PODF_B(x) \
6692 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_CLR_PRE_PODF_B_MASK)
6693#define CCM_PRE_ROOT_CLR_BUSY0_MASK (0x8U)
6694#define CCM_PRE_ROOT_CLR_BUSY0_SHIFT (3U)
6695#define CCM_PRE_ROOT_CLR_BUSY0(x) \
6696 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY0_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY0_MASK)
6697#define CCM_PRE_ROOT_CLR_MUX_B_MASK (0x700U)
6698#define CCM_PRE_ROOT_CLR_MUX_B_SHIFT (8U)
6699#define CCM_PRE_ROOT_CLR_MUX_B(x) \
6700 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_MUX_B_SHIFT)) & CCM_PRE_ROOT_CLR_MUX_B_MASK)
6701#define CCM_PRE_ROOT_CLR_EN_B_MASK (0x1000U)
6702#define CCM_PRE_ROOT_CLR_EN_B_SHIFT (12U)
6703/*! EN_B
6704 * 0b0..Clock shutdown
6705 * 0b1..Clock ON
6706 */
6707#define CCM_PRE_ROOT_CLR_EN_B(x) \
6708 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_EN_B_SHIFT)) & CCM_PRE_ROOT_CLR_EN_B_MASK)
6709#define CCM_PRE_ROOT_CLR_BUSY1_MASK (0x8000U)
6710#define CCM_PRE_ROOT_CLR_BUSY1_SHIFT (15U)
6711#define CCM_PRE_ROOT_CLR_BUSY1(x) \
6712 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY1_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY1_MASK)
6713#define CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK (0x70000U)
6714#define CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT (16U)
6715/*! PRE_PODF_A
6716 * 0b000..Divide by 1
6717 * 0b001..Divide by 2
6718 * 0b010..Divide by 3
6719 * 0b011..Divide by 4
6720 * 0b100..Divide by 5
6721 * 0b101..Divide by 6
6722 * 0b110..Divide by 7
6723 * 0b111..Divide by 8
6724 */
6725#define CCM_PRE_ROOT_CLR_PRE_PODF_A(x) \
6726 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_CLR_PRE_PODF_A_MASK)
6727#define CCM_PRE_ROOT_CLR_BUSY3_MASK (0x80000U)
6728#define CCM_PRE_ROOT_CLR_BUSY3_SHIFT (19U)
6729#define CCM_PRE_ROOT_CLR_BUSY3(x) \
6730 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY3_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY3_MASK)
6731#define CCM_PRE_ROOT_CLR_MUX_A_MASK (0x7000000U)
6732#define CCM_PRE_ROOT_CLR_MUX_A_SHIFT (24U)
6733#define CCM_PRE_ROOT_CLR_MUX_A(x) \
6734 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_MUX_A_SHIFT)) & CCM_PRE_ROOT_CLR_MUX_A_MASK)
6735#define CCM_PRE_ROOT_CLR_EN_A_MASK (0x10000000U)
6736#define CCM_PRE_ROOT_CLR_EN_A_SHIFT (28U)
6737/*! EN_A
6738 * 0b0..Clock shutdown
6739 * 0b1..clock ON
6740 */
6741#define CCM_PRE_ROOT_CLR_EN_A(x) \
6742 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_EN_A_SHIFT)) & CCM_PRE_ROOT_CLR_EN_A_MASK)
6743#define CCM_PRE_ROOT_CLR_BUSY4_MASK (0x80000000U)
6744#define CCM_PRE_ROOT_CLR_BUSY4_SHIFT (31U)
6745#define CCM_PRE_ROOT_CLR_BUSY4(x) \
6746 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_CLR_BUSY4_SHIFT)) & CCM_PRE_ROOT_CLR_BUSY4_MASK)
6747/*! @} */
6748
6749/* The count of CCM_PRE_ROOT_CLR */
6750#define CCM_PRE_ROOT_CLR_COUNT (135U)
6751
6752/*! @name PRE_ROOT_TOG - Pre Divider Register */
6753/*! @{ */
6754#define CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK (0x7U)
6755#define CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT (0U)
6756/*! PRE_PODF_B
6757 * 0b000..Divide by 1
6758 * 0b001..Divide by 2
6759 * 0b010..Divide by 3
6760 * 0b011..Divide by 4
6761 * 0b100..Divide by 5
6762 * 0b101..Divide by 6
6763 * 0b110..Divide by 7
6764 * 0b111..Divide by 8
6765 */
6766#define CCM_PRE_ROOT_TOG_PRE_PODF_B(x) \
6767 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_PRE_PODF_B_SHIFT)) & CCM_PRE_ROOT_TOG_PRE_PODF_B_MASK)
6768#define CCM_PRE_ROOT_TOG_BUSY0_MASK (0x8U)
6769#define CCM_PRE_ROOT_TOG_BUSY0_SHIFT (3U)
6770#define CCM_PRE_ROOT_TOG_BUSY0(x) \
6771 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY0_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY0_MASK)
6772#define CCM_PRE_ROOT_TOG_MUX_B_MASK (0x700U)
6773#define CCM_PRE_ROOT_TOG_MUX_B_SHIFT (8U)
6774#define CCM_PRE_ROOT_TOG_MUX_B(x) \
6775 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_MUX_B_SHIFT)) & CCM_PRE_ROOT_TOG_MUX_B_MASK)
6776#define CCM_PRE_ROOT_TOG_EN_B_MASK (0x1000U)
6777#define CCM_PRE_ROOT_TOG_EN_B_SHIFT (12U)
6778/*! EN_B
6779 * 0b0..Clock shutdown
6780 * 0b1..Clock ON
6781 */
6782#define CCM_PRE_ROOT_TOG_EN_B(x) \
6783 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_EN_B_SHIFT)) & CCM_PRE_ROOT_TOG_EN_B_MASK)
6784#define CCM_PRE_ROOT_TOG_BUSY1_MASK (0x8000U)
6785#define CCM_PRE_ROOT_TOG_BUSY1_SHIFT (15U)
6786#define CCM_PRE_ROOT_TOG_BUSY1(x) \
6787 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY1_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY1_MASK)
6788#define CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK (0x70000U)
6789#define CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT (16U)
6790/*! PRE_PODF_A
6791 * 0b000..Divide by 1
6792 * 0b001..Divide by 2
6793 * 0b010..Divide by 3
6794 * 0b011..Divide by 4
6795 * 0b100..Divide by 5
6796 * 0b101..Divide by 6
6797 * 0b110..Divide by 7
6798 * 0b111..Divide by 8
6799 */
6800#define CCM_PRE_ROOT_TOG_PRE_PODF_A(x) \
6801 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_PRE_PODF_A_SHIFT)) & CCM_PRE_ROOT_TOG_PRE_PODF_A_MASK)
6802#define CCM_PRE_ROOT_TOG_BUSY3_MASK (0x80000U)
6803#define CCM_PRE_ROOT_TOG_BUSY3_SHIFT (19U)
6804#define CCM_PRE_ROOT_TOG_BUSY3(x) \
6805 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY3_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY3_MASK)
6806#define CCM_PRE_ROOT_TOG_MUX_A_MASK (0x7000000U)
6807#define CCM_PRE_ROOT_TOG_MUX_A_SHIFT (24U)
6808#define CCM_PRE_ROOT_TOG_MUX_A(x) \
6809 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_MUX_A_SHIFT)) & CCM_PRE_ROOT_TOG_MUX_A_MASK)
6810#define CCM_PRE_ROOT_TOG_EN_A_MASK (0x10000000U)
6811#define CCM_PRE_ROOT_TOG_EN_A_SHIFT (28U)
6812/*! EN_A
6813 * 0b0..Clock shutdown
6814 * 0b1..clock ON
6815 */
6816#define CCM_PRE_ROOT_TOG_EN_A(x) \
6817 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_EN_A_SHIFT)) & CCM_PRE_ROOT_TOG_EN_A_MASK)
6818#define CCM_PRE_ROOT_TOG_BUSY4_MASK (0x80000000U)
6819#define CCM_PRE_ROOT_TOG_BUSY4_SHIFT (31U)
6820#define CCM_PRE_ROOT_TOG_BUSY4(x) \
6821 (((uint32_t)(((uint32_t)(x)) << CCM_PRE_ROOT_TOG_BUSY4_SHIFT)) & CCM_PRE_ROOT_TOG_BUSY4_MASK)
6822/*! @} */
6823
6824/* The count of CCM_PRE_ROOT_TOG */
6825#define CCM_PRE_ROOT_TOG_COUNT (135U)
6826
6827/*! @name ACCESS_CTRL - Access Control Register */
6828/*! @{ */
6829#define CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK (0xFU)
6830#define CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT (0U)
6831#define CCM_ACCESS_CTRL_DOMAIN0_INFO(x) \
6832 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN0_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN0_INFO_MASK)
6833#define CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK (0xF0U)
6834#define CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT (4U)
6835#define CCM_ACCESS_CTRL_DOMAIN1_INFO(x) \
6836 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN1_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN1_INFO_MASK)
6837#define CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK (0xF00U)
6838#define CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT (8U)
6839#define CCM_ACCESS_CTRL_DOMAIN2_INFO(x) \
6840 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN2_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN2_INFO_MASK)
6841#define CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK (0xF000U)
6842#define CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT (12U)
6843#define CCM_ACCESS_CTRL_DOMAIN3_INFO(x) \
6844 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN3_INFO_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN3_INFO_MASK)
6845#define CCM_ACCESS_CTRL_OWNER_ID_MASK (0x30000U)
6846#define CCM_ACCESS_CTRL_OWNER_ID_SHIFT (16U)
6847/*! OWNER_ID
6848 * 0b00..domaino
6849 * 0b01..domain1
6850 * 0b10..domain2
6851 * 0b11..domain3
6852 */
6853#define CCM_ACCESS_CTRL_OWNER_ID(x) \
6854 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_OWNER_ID_MASK)
6855#define CCM_ACCESS_CTRL_MUTEX_MASK (0x100000U)
6856#define CCM_ACCESS_CTRL_MUTEX_SHIFT (20U)
6857/*! MUTEX
6858 * 0b0..Semaphore is free to take
6859 * 0b1..Semaphore is taken
6860 */
6861#define CCM_ACCESS_CTRL_MUTEX(x) \
6862 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_MUTEX_MASK)
6863#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK (0x1000000U)
6864#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT (24U)
6865/*! DOMAIN0_WHITELIST
6866 * 0b0..Domain cannot change the setting
6867 * 0b1..Domain can change the setting
6868 */
6869#define CCM_ACCESS_CTRL_DOMAIN0_WHITELIST(x) \
6870 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN0_WHITELIST_MASK)
6871#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK (0x2000000U)
6872#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT (25U)
6873/*! DOMAIN1_WHITELIST
6874 * 0b0..Domain cannot change the setting
6875 * 0b1..Domain can change the setting
6876 */
6877#define CCM_ACCESS_CTRL_DOMAIN1_WHITELIST(x) \
6878 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN1_WHITELIST_MASK)
6879#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK (0x4000000U)
6880#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT (26U)
6881/*! DOMAIN2_WHITELIST
6882 * 0b0..Domain cannot change the setting
6883 * 0b1..Domain can change the setting
6884 */
6885#define CCM_ACCESS_CTRL_DOMAIN2_WHITELIST(x) \
6886 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN2_WHITELIST_MASK)
6887#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK (0x8000000U)
6888#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT (27U)
6889/*! DOMAIN3_WHITELIST
6890 * 0b0..Domain cannot change the setting
6891 * 0b1..Domain can change the setting
6892 */
6893#define CCM_ACCESS_CTRL_DOMAIN3_WHITELIST(x) \
6894 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_SHIFT)) & CCM_ACCESS_CTRL_DOMAIN3_WHITELIST_MASK)
6895#define CCM_ACCESS_CTRL_SEMA_EN_MASK (0x10000000U)
6896#define CCM_ACCESS_CTRL_SEMA_EN_SHIFT (28U)
6897/*! SEMA_EN
6898 * 0b0..Disable
6899 * 0b1..Enable
6900 */
6901#define CCM_ACCESS_CTRL_SEMA_EN(x) \
6902 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_SEMA_EN_MASK)
6903#define CCM_ACCESS_CTRL_LOCK_MASK (0x80000000U)
6904#define CCM_ACCESS_CTRL_LOCK_SHIFT (31U)
6905/*! LOCK
6906 * 0b0..Access control inactive
6907 * 0b1..Access control active
6908 */
6909#define CCM_ACCESS_CTRL_LOCK(x) \
6910 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_LOCK_SHIFT)) & CCM_ACCESS_CTRL_LOCK_MASK)
6911/*! @} */
6912
6913/* The count of CCM_ACCESS_CTRL */
6914#define CCM_ACCESS_CTRL_COUNT (135U)
6915
6916/*! @name ACCESS_CTRL_ROOT_SET - Access Control Register */
6917/*! @{ */
6918#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK (0xFU)
6919#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT (0U)
6920#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO(x) \
6921 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_SHIFT)) & \
6922 CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_INFO_MASK)
6923#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK (0xF0U)
6924#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT (4U)
6925#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO(x) \
6926 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_SHIFT)) & \
6927 CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_INFO_MASK)
6928#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK (0xF00U)
6929#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT (8U)
6930#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO(x) \
6931 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_SHIFT)) & \
6932 CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_INFO_MASK)
6933#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK (0xF000U)
6934#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT (12U)
6935#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO(x) \
6936 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_SHIFT)) & \
6937 CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_INFO_MASK)
6938#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK (0x30000U)
6939#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT (16U)
6940/*! OWNER_ID
6941 * 0b00..domaino
6942 * 0b01..domain1
6943 * 0b10..domain2
6944 * 0b11..domain3
6945 */
6946#define CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID(x) \
6947 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_OWNER_ID_MASK)
6948#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK (0x100000U)
6949#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT (20U)
6950/*! MUTEX
6951 * 0b0..Semaphore is free to take
6952 * 0b1..Semaphore is taken
6953 */
6954#define CCM_ACCESS_CTRL_ROOT_SET_MUTEX(x) \
6955 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_MUTEX_MASK)
6956#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK (0x1000000U)
6957#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT (24U)
6958/*! DOMAIN0_WHITELIST
6959 * 0b0..Domain cannot change the setting
6960 * 0b1..Domain can change the setting
6961 */
6962#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST(x) \
6963 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_SHIFT)) & \
6964 CCM_ACCESS_CTRL_ROOT_SET_DOMAIN0_WHITELIST_MASK)
6965#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK (0x2000000U)
6966#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT (25U)
6967/*! DOMAIN1_WHITELIST
6968 * 0b0..Domain cannot change the setting
6969 * 0b1..Domain can change the setting
6970 */
6971#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST(x) \
6972 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_SHIFT)) & \
6973 CCM_ACCESS_CTRL_ROOT_SET_DOMAIN1_WHITELIST_MASK)
6974#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK (0x4000000U)
6975#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT (26U)
6976/*! DOMAIN2_WHITELIST
6977 * 0b0..Domain cannot change the setting
6978 * 0b1..Domain can change the setting
6979 */
6980#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST(x) \
6981 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_SHIFT)) & \
6982 CCM_ACCESS_CTRL_ROOT_SET_DOMAIN2_WHITELIST_MASK)
6983#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK (0x8000000U)
6984#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT (27U)
6985/*! DOMAIN3_WHITELIST
6986 * 0b0..Domain cannot change the setting
6987 * 0b1..Domain can change the setting
6988 */
6989#define CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST(x) \
6990 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_SHIFT)) & \
6991 CCM_ACCESS_CTRL_ROOT_SET_DOMAIN3_WHITELIST_MASK)
6992#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK (0x10000000U)
6993#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT (28U)
6994/*! SEMA_EN
6995 * 0b0..Disable
6996 * 0b1..Enable
6997 */
6998#define CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN(x) \
6999 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_SEMA_EN_MASK)
7000#define CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK (0x80000000U)
7001#define CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT (31U)
7002/*! LOCK
7003 * 0b0..Access control inactive
7004 * 0b1..Access control active
7005 */
7006#define CCM_ACCESS_CTRL_ROOT_SET_LOCK(x) \
7007 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_SET_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_SET_LOCK_MASK)
7008/*! @} */
7009
7010/* The count of CCM_ACCESS_CTRL_ROOT_SET */
7011#define CCM_ACCESS_CTRL_ROOT_SET_COUNT (135U)
7012
7013/*! @name ACCESS_CTRL_ROOT_CLR - Access Control Register */
7014/*! @{ */
7015#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK (0xFU)
7016#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT (0U)
7017#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO(x) \
7018 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_SHIFT)) & \
7019 CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_INFO_MASK)
7020#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK (0xF0U)
7021#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT (4U)
7022#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO(x) \
7023 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_SHIFT)) & \
7024 CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_INFO_MASK)
7025#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK (0xF00U)
7026#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT (8U)
7027#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO(x) \
7028 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_SHIFT)) & \
7029 CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_INFO_MASK)
7030#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK (0xF000U)
7031#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT (12U)
7032#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO(x) \
7033 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_SHIFT)) & \
7034 CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_INFO_MASK)
7035#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK (0x30000U)
7036#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT (16U)
7037/*! OWNER_ID
7038 * 0b00..domaino
7039 * 0b01..domain1
7040 * 0b10..domain2
7041 * 0b11..domain3
7042 */
7043#define CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID(x) \
7044 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_OWNER_ID_MASK)
7045#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK (0x100000U)
7046#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT (20U)
7047/*! MUTEX
7048 * 0b0..Semaphore is free to take
7049 * 0b1..Semaphore is taken
7050 */
7051#define CCM_ACCESS_CTRL_ROOT_CLR_MUTEX(x) \
7052 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_MUTEX_MASK)
7053#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK (0x1000000U)
7054#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT (24U)
7055/*! DOMAIN0_WHITELIST
7056 * 0b0..Domain cannot change the setting
7057 * 0b1..Domain can change the setting
7058 */
7059#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST(x) \
7060 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_SHIFT)) & \
7061 CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN0_WHITELIST_MASK)
7062#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK (0x2000000U)
7063#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT (25U)
7064/*! DOMAIN1_WHITELIST
7065 * 0b0..Domain cannot change the setting
7066 * 0b1..Domain can change the setting
7067 */
7068#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST(x) \
7069 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_SHIFT)) & \
7070 CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN1_WHITELIST_MASK)
7071#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK (0x4000000U)
7072#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT (26U)
7073/*! DOMAIN2_WHITELIST
7074 * 0b0..Domain cannot change the setting
7075 * 0b1..Domain can change the setting
7076 */
7077#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST(x) \
7078 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_SHIFT)) & \
7079 CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN2_WHITELIST_MASK)
7080#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK (0x8000000U)
7081#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT (27U)
7082/*! DOMAIN3_WHITELIST
7083 * 0b0..Domain cannot change the setting
7084 * 0b1..Domain can change the setting
7085 */
7086#define CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST(x) \
7087 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_SHIFT)) & \
7088 CCM_ACCESS_CTRL_ROOT_CLR_DOMAIN3_WHITELIST_MASK)
7089#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK (0x10000000U)
7090#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT (28U)
7091/*! SEMA_EN
7092 * 0b0..Disable
7093 * 0b1..Enable
7094 */
7095#define CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN(x) \
7096 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_SEMA_EN_MASK)
7097#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK (0x80000000U)
7098#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT (31U)
7099/*! LOCK
7100 * 0b0..Access control inactive
7101 * 0b1..Access control active
7102 */
7103#define CCM_ACCESS_CTRL_ROOT_CLR_LOCK(x) \
7104 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_CLR_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_CLR_LOCK_MASK)
7105/*! @} */
7106
7107/* The count of CCM_ACCESS_CTRL_ROOT_CLR */
7108#define CCM_ACCESS_CTRL_ROOT_CLR_COUNT (135U)
7109
7110/*! @name ACCESS_CTRL_ROOT_TOG - Access Control Register */
7111/*! @{ */
7112#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK (0xFU)
7113#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT (0U)
7114#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO(x) \
7115 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_SHIFT)) & \
7116 CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_INFO_MASK)
7117#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK (0xF0U)
7118#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT (4U)
7119#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO(x) \
7120 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_SHIFT)) & \
7121 CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_INFO_MASK)
7122#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK (0xF00U)
7123#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT (8U)
7124#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO(x) \
7125 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_SHIFT)) & \
7126 CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_INFO_MASK)
7127#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK (0xF000U)
7128#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT (12U)
7129#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO(x) \
7130 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_SHIFT)) & \
7131 CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_INFO_MASK)
7132#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK (0x30000U)
7133#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT (16U)
7134/*! OWNER_ID
7135 * 0b00..domaino
7136 * 0b01..domain1
7137 * 0b10..domain2
7138 * 0b11..domain3
7139 */
7140#define CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID(x) \
7141 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_OWNER_ID_MASK)
7142#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK (0x100000U)
7143#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT (20U)
7144/*! MUTEX
7145 * 0b0..Semaphore is free to take
7146 * 0b1..Semaphore is taken
7147 */
7148#define CCM_ACCESS_CTRL_ROOT_TOG_MUTEX(x) \
7149 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_MUTEX_MASK)
7150#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK (0x1000000U)
7151#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT (24U)
7152/*! DOMAIN0_WHITELIST
7153 * 0b0..Domain cannot change the setting
7154 * 0b1..Domain can change the setting
7155 */
7156#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST(x) \
7157 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_SHIFT)) & \
7158 CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN0_WHITELIST_MASK)
7159#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK (0x2000000U)
7160#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT (25U)
7161/*! DOMAIN1_WHITELIST
7162 * 0b0..Domain cannot change the setting
7163 * 0b1..Domain can change the setting
7164 */
7165#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST(x) \
7166 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_SHIFT)) & \
7167 CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN1_WHITELIST_MASK)
7168#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK (0x4000000U)
7169#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT (26U)
7170/*! DOMAIN2_WHITELIST
7171 * 0b0..Domain cannot change the setting
7172 * 0b1..Domain can change the setting
7173 */
7174#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST(x) \
7175 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_SHIFT)) & \
7176 CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN2_WHITELIST_MASK)
7177#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK (0x8000000U)
7178#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT (27U)
7179/*! DOMAIN3_WHITELIST
7180 * 0b0..Domain cannot change the setting
7181 * 0b1..Domain can change the setting
7182 */
7183#define CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST(x) \
7184 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_SHIFT)) & \
7185 CCM_ACCESS_CTRL_ROOT_TOG_DOMAIN3_WHITELIST_MASK)
7186#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK (0x10000000U)
7187#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT (28U)
7188/*! SEMA_EN
7189 * 0b0..Disable
7190 * 0b1..Enable
7191 */
7192#define CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN(x) \
7193 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_SEMA_EN_MASK)
7194#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK (0x80000000U)
7195#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT (31U)
7196/*! LOCK
7197 * 0b0..Access control inactive
7198 * 0b1..Access control active
7199 */
7200#define CCM_ACCESS_CTRL_ROOT_TOG_LOCK(x) \
7201 (((uint32_t)(((uint32_t)(x)) << CCM_ACCESS_CTRL_ROOT_TOG_LOCK_SHIFT)) & CCM_ACCESS_CTRL_ROOT_TOG_LOCK_MASK)
7202/*! @} */
7203
7204/* The count of CCM_ACCESS_CTRL_ROOT_TOG */
7205#define CCM_ACCESS_CTRL_ROOT_TOG_COUNT (135U)
7206
7207/*!
7208 * @}
7209 */ /* end of group CCM_Register_Masks */
7210
7211/* CCM - Peripheral instance base addresses */
7212/** Peripheral CCM base address */
7213#define CCM_BASE (0x30380000u)
7214/** Peripheral CCM base pointer */
7215#define CCM ((CCM_Type *)CCM_BASE)
7216/** Array initializer of CCM peripheral base addresses */
7217#define CCM_BASE_ADDRS \
7218 { \
7219 CCM_BASE \
7220 }
7221/** Array initializer of CCM peripheral base pointers */
7222#define CCM_BASE_PTRS \
7223 { \
7224 CCM \
7225 }
7226/** Interrupt vectors for the CCM peripheral type */
7227#define CCM_IRQS \
7228 { \
7229 CCM_IRQ1_IRQn, CCM_IRQ2_IRQn \
7230 }
7231
7232/*!
7233 * @}
7234 */ /* end of group CCM_Peripheral_Access_Layer */
7235
7236/* ----------------------------------------------------------------------------
7237 -- CCM_ANALOG Peripheral Access Layer
7238 ---------------------------------------------------------------------------- */
7239
7240/*!
7241 * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer
7242 * @{
7243 */
7244
7245/** CCM_ANALOG - Register Layout Typedef */
7246typedef struct
7247{
7248 __IO uint32_t AUDIO_PLL1_GEN_CTRL; /**< AUDIO PLL1 General Function Control Register, offset: 0x0 */
7249 __IO uint32_t AUDIO_PLL1_FDIV_CTL0; /**< AUDIO PLL1 Divide and Fraction Data Control 0 Register, offset: 0x4 */
7250 __IO uint32_t AUDIO_PLL1_FDIV_CTL1; /**< AUDIO PLL1 Divide and Fraction Data Control 1 Register, offset: 0x8 */
7251 __IO uint32_t AUDIO_PLL1_SSCG_CTRL; /**< AUDIO PLL1 PLL SSCG Control Register, offset: 0xC */
7252 __IO uint32_t AUDIO_PLL1_MNIT_CTRL; /**< AUDIO PLL1 PLL Monitoring Control Register, offset: 0x10 */
7253 __IO uint32_t AUDIO_PLL2_GEN_CTRL; /**< AUDIO PLL2 General Function Control Register, offset: 0x14 */
7254 __IO uint32_t AUDIO_PLL2_FDIV_CTL0; /**< AUDIO PLL2 Divide and Fraction Data Control 0 Register, offset: 0x18 */
7255 __IO uint32_t AUDIO_PLL2_FDIV_CTL1; /**< AUDIO PLL2 Divide and Fraction Data Control 1 Register, offset: 0x1C */
7256 __IO uint32_t AUDIO_PLL2_SSCG_CTRL; /**< AUDIO PLL2 PLL SSCG Control Register, offset: 0x20 */
7257 __IO uint32_t AUDIO_PLL2_MNIT_CTRL; /**< AUDIO PLL2 PLL Monitoring Control Register, offset: 0x24 */
7258 __IO uint32_t VIDEO_PLL1_GEN_CTRL; /**< VIDEO PLL1 General Function Control Register, offset: 0x28 */
7259 __IO uint32_t VIDEO_PLL1_FDIV_CTL0; /**< VIDEO PLL1 Divide and Fraction Data Control 0 Register, offset: 0x2C */
7260 __IO uint32_t VIDEO_PLL1_FDIV_CTL1; /**< VIDEO PLL1 Divide and Fraction Data Control 1 Register, offset: 0x30 */
7261 __IO uint32_t VIDEO_PLL1_SSCG_CTRL; /**< VIDEO PLL1 PLL SSCG Control Register, offset: 0x34 */
7262 __IO uint32_t VIDEO_PLL1_MNIT_CTRL; /**< VIDEO PLL1 PLL Monitoring Control Register, offset: 0x38 */
7263 uint8_t RESERVED_0[20];
7264 __IO uint32_t DRAM_PLL_GEN_CTRL; /**< DRAM PLL General Function Control Register, offset: 0x50 */
7265 __IO uint32_t DRAM_PLL_FDIV_CTL0; /**< DRAM PLL Divide and Fraction Data Control 0 Register, offset: 0x54 */
7266 __IO uint32_t DRAM_PLL_FDIV_CTL1; /**< DRAM PLL Divide and Fraction Data Control 1 Register, offset: 0x58 */
7267 __IO uint32_t DRAM_PLL_SSCG_CTRL; /**< DRAM PLL PLL SSCG Control Register, offset: 0x5C */
7268 __IO uint32_t DRAM_PLL_MNIT_CTRL; /**< DRAM PLL PLL Monitoring Control Register, offset: 0x60 */
7269 __IO uint32_t GPU_PLL_GEN_CTRL; /**< GPU PLL General Function Control Register, offset: 0x64 */
7270 __IO uint32_t GPU_PLL_FDIV_CTL0; /**< GPU PLL Divide and Fraction Data Control 0 Register, offset: 0x68 */
7271 __IO uint32_t GPU_PLL_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x6C */
7272 __IO uint32_t GPU_PLL_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x70 */
7273 __IO uint32_t M7_ALT_PLL_GEN_CTRL; /**< M7 Alternate PLL General Function Control Register, offset: 0x74 */
7274 __IO uint32_t
7275 M7_ALT_PLL_FDIV_CTL0; /**< M7 Alternate PLL Divide and Fraction Data Control 0 Register, offset: 0x78 */
7276 __IO uint32_t M7_ALT_PLL_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x7C */
7277 __IO uint32_t M7_ALT_PLL_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x80 */
7278 __IO uint32_t ARM_PLL_GEN_CTRL; /**< ARM PLL General Function Control Register, offset: 0x84 */
7279 __IO uint32_t ARM_PLL_FDIV_CTL0; /**< ARM PLL Divide and Fraction Data Control 0 Register, offset: 0x88 */
7280 __IO uint32_t ARM_PLL_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x8C */
7281 __IO uint32_t ARM_PLL_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x90 */
7282 __IO uint32_t SYS_PLL1_GEN_CTRL; /**< SYS PLL1 General Function Control Register, offset: 0x94 */
7283 __IO uint32_t SYS_PLL1_FDIV_CTL0; /**< SYS PLL1 Divide and Fraction Data Control 0 Register, offset: 0x98 */
7284 __IO uint32_t SYS_PLL1_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x9C */
7285 uint8_t RESERVED_1[96];
7286 __IO uint32_t SYS_PLL1_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x100 */
7287 __IO uint32_t SYS_PLL2_GEN_CTRL; /**< SYS PLL2 General Function Control Register, offset: 0x104 */
7288 __IO uint32_t SYS_PLL2_FDIV_CTL0; /**< SYS PLL2 Divide and Fraction Data Control 0 Register, offset: 0x108 */
7289 __IO uint32_t SYS_PLL2_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x10C */
7290 __IO uint32_t SYS_PLL2_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x110 */
7291 __IO uint32_t SYS_PLL3_GEN_CTRL; /**< SYS PLL3 General Function Control Register, offset: 0x114 */
7292 __IO uint32_t SYS_PLL3_FDIV_CTL0; /**< SYS PLL3 Divide and Fraction Data Control 0 Register, offset: 0x118 */
7293 __IO uint32_t SYS_PLL3_LOCKD_CTRL; /**< PLL Lock Detector Control Register, offset: 0x11C */
7294 __IO uint32_t SYS_PLL3_MNIT_CTRL; /**< PLL Monitoring Control Register, offset: 0x120 */
7295 __IO uint32_t OSC_MISC_CFG; /**< Osc Misc Configuration Register, offset: 0x124 */
7296 __IO uint32_t ANAMIX_PLL_MNIT_CTL; /**< PLL Clock Output for Test Enable and Select Register, offset: 0x128 */
7297 uint8_t RESERVED_2[1748];
7298 __I uint32_t DIGPROG; /**< DIGPROG Register, offset: 0x800 */
7299} CCM_ANALOG_Type;
7300
7301/* ----------------------------------------------------------------------------
7302 -- CCM_ANALOG Register Masks
7303 ---------------------------------------------------------------------------- */
7304
7305/*!
7306 * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks
7307 * @{
7308 */
7309
7310/*! @name AUDIO_PLL1_GEN_CTRL - AUDIO PLL1 General Function Control Register */
7311/*! @{ */
7312#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
7313#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
7314/*! PLL_REF_CLK_SEL
7315 * 0b00..SYS_XTAL
7316 * 0b01..PAD_CLK
7317 * 0b10..Reserved
7318 * 0b11..Reserved
7319 */
7320#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) \
7321 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \
7322 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
7323#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
7324#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
7325/*! PAD_CLK_SEL
7326 * 0b00..CLKIN1 XOR CLKIN2
7327 * 0b01..CLKIN2
7328 * 0b10..CLKIN1
7329 * 0b11..Reserved
7330 */
7331#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL(x) \
7332 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \
7333 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK)
7334#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
7335#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
7336#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS(x) \
7337 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & \
7338 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_MASK)
7339#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
7340#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
7341#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) \
7342 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \
7343 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
7344#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U)
7345#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U)
7346#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST(x) \
7347 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & \
7348 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_MASK)
7349#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
7350#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
7351#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \
7352 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \
7353 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
7354#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
7355#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (13U)
7356#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE(x) \
7357 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & \
7358 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_MASK)
7359#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
7360#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
7361#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) \
7362 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \
7363 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK)
7364#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
7365#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U)
7366#define CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK(x) \
7367 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & \
7368 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_LOCK_MASK)
7369/*! @} */
7370
7371/*! @name AUDIO_PLL1_FDIV_CTL0 - AUDIO PLL1 Divide and Fraction Data Control 0 Register */
7372/*! @{ */
7373#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
7374#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
7375#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV(x) \
7376 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \
7377 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK)
7378#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
7379#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
7380#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) \
7381 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \
7382 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK)
7383#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
7384#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
7385#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) \
7386 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \
7387 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK)
7388/*! @} */
7389
7390/*! @name AUDIO_PLL1_FDIV_CTL1 - AUDIO PLL1 Divide and Fraction Data Control 1 Register */
7391/*! @{ */
7392#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
7393#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT (0U)
7394#define CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM(x) \
7395 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT)) & \
7396 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_MASK)
7397/*! @} */
7398
7399/*! @name AUDIO_PLL1_SSCG_CTRL - AUDIO PLL1 PLL SSCG Control Register */
7400/*! @{ */
7401#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_MASK (0x3U)
7402#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_SHIFT (0U)
7403/*! SEL_PF
7404 * 0b00..Down spread
7405 * 0b01..Up spread
7406 * 0b1x..Center spread
7407 */
7408#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF(x) \
7409 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_SHIFT)) & \
7410 CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SEL_PF_MASK)
7411#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
7412#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
7413#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL(x) \
7414 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & \
7415 CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK)
7416#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
7417#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
7418#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL(x) \
7419 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & \
7420 CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
7421#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
7422#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT (31U)
7423#define CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN(x) \
7424 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT)) & \
7425 CCM_ANALOG_AUDIO_PLL1_SSCG_CTRL_SSCG_EN_MASK)
7426/*! @} */
7427
7428/*! @name AUDIO_PLL1_MNIT_CTRL - AUDIO PLL1 PLL Monitoring Control Register */
7429/*! @{ */
7430#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_MASK (0x7U)
7431#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_SHIFT (0U)
7432#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP(x) \
7433 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_SHIFT)) & \
7434 CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_ICP_MASK)
7435#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_MASK (0x8U)
7436#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_SHIFT (3U)
7437#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN(x) \
7438 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & \
7439 CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_EN_MASK)
7440#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
7441#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_SHIFT (4U)
7442#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC(x) \
7443 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & \
7444 CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_EXTAFC_MASK)
7445#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_MASK (0x4000U)
7446#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_SHIFT (14U)
7447#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN(x) \
7448 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & \
7449 CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FEED_EN_MASK)
7450#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_MASK (0x8000U)
7451#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_SHIFT (15U)
7452/*! FSEL
7453 * 0b0..FEED_OUT = FREF
7454 * 0b1..FEED_OUT = FEED
7455 */
7456#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL(x) \
7457 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_SHIFT)) & \
7458 CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_FSEL_MASK)
7459#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
7460#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
7461/*! AFCINIT_SEL
7462 * 0b0..nominal delay
7463 * 0b1..nominal delay * 2
7464 */
7465#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL(x) \
7466 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \
7467 CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK)
7468#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
7469#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
7470#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) \
7471 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \
7472 CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
7473#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
7474#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
7475/*! PBIAS_CTRL
7476 * 0b0..0.50*VDD
7477 * 0b1..0.67*VDD
7478 */
7479#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL(x) \
7480 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \
7481 CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK)
7482#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
7483#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (20U)
7484#define CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL(x) \
7485 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & \
7486 CCM_ANALOG_AUDIO_PLL1_MNIT_CTRL_AFC_SEL_MASK)
7487/*! @} */
7488
7489/*! @name AUDIO_PLL2_GEN_CTRL - AUDIO PLL2 General Function Control Register */
7490/*! @{ */
7491#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
7492#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
7493/*! PLL_REF_CLK_SEL
7494 * 0b00..SYS_XTAL
7495 * 0b01..PAD_CLK
7496 * 0b10..Reserved
7497 * 0b11..Reserved
7498 */
7499#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL(x) \
7500 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \
7501 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
7502#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
7503#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
7504/*! PAD_CLK_SEL
7505 * 0b00..CLKIN1 XOR CLKIN2
7506 * 0b01..CLKIN2
7507 * 0b10..CLKIN1
7508 * 0b11..Reserved
7509 */
7510#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL(x) \
7511 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \
7512 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK)
7513#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
7514#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
7515#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS(x) \
7516 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT)) & \
7517 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_MASK)
7518#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
7519#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
7520#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE(x) \
7521 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \
7522 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
7523#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_MASK (0x200U)
7524#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_SHIFT (9U)
7525#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST(x) \
7526 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_SHIFT)) & \
7527 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_MASK)
7528#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
7529#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
7530#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \
7531 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \
7532 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
7533#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
7534#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_SHIFT (13U)
7535#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE(x) \
7536 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_SHIFT)) & \
7537 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_MASK)
7538#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
7539#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
7540#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS(x) \
7541 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \
7542 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK)
7543#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
7544#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_SHIFT (31U)
7545#define CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK(x) \
7546 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_SHIFT)) & \
7547 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_LOCK_MASK)
7548/*! @} */
7549
7550/*! @name AUDIO_PLL2_FDIV_CTL0 - AUDIO PLL2 Divide and Fraction Data Control 0 Register */
7551/*! @{ */
7552#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
7553#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
7554#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV(x) \
7555 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \
7556 CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK)
7557#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
7558#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
7559#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV(x) \
7560 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \
7561 CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK)
7562#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
7563#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
7564#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV(x) \
7565 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \
7566 CCM_ANALOG_AUDIO_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK)
7567/*! @} */
7568
7569/*! @name AUDIO_PLL2_FDIV_CTL1 - AUDIO PLL2 Divide and Fraction Data Control 1 Register */
7570/*! @{ */
7571#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
7572#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_SHIFT (0U)
7573#define CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM(x) \
7574 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_SHIFT)) & \
7575 CCM_ANALOG_AUDIO_PLL2_FDIV_CTL1_PLL_DSM_MASK)
7576/*! @} */
7577
7578/*! @name AUDIO_PLL2_SSCG_CTRL - AUDIO PLL2 PLL SSCG Control Register */
7579/*! @{ */
7580#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_MASK (0x3U)
7581#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_SHIFT (0U)
7582/*! SEL_PF
7583 * 0b00..Down spread
7584 * 0b01..Up spread
7585 * 0b1x..Center spread
7586 */
7587#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF(x) \
7588 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_SHIFT)) & \
7589 CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SEL_PF_MASK)
7590#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
7591#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
7592#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL(x) \
7593 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & \
7594 CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MRAT_CTL_MASK)
7595#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
7596#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
7597#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL(x) \
7598 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & \
7599 CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
7600#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
7601#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_SHIFT (31U)
7602#define CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN(x) \
7603 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_SHIFT)) & \
7604 CCM_ANALOG_AUDIO_PLL2_SSCG_CTRL_SSCG_EN_MASK)
7605/*! @} */
7606
7607/*! @name AUDIO_PLL2_MNIT_CTRL - AUDIO PLL2 PLL Monitoring Control Register */
7608/*! @{ */
7609#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_MASK (0x7U)
7610#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_SHIFT (0U)
7611#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP(x) \
7612 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_SHIFT)) & \
7613 CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_ICP_MASK)
7614#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_MASK (0x8U)
7615#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_SHIFT (3U)
7616#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN(x) \
7617 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_SHIFT)) & \
7618 CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_EN_MASK)
7619#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
7620#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_SHIFT (4U)
7621#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC(x) \
7622 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_SHIFT)) & \
7623 CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_EXTAFC_MASK)
7624#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_MASK (0x4000U)
7625#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_SHIFT (14U)
7626#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN(x) \
7627 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_SHIFT)) & \
7628 CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FEED_EN_MASK)
7629#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_MASK (0x8000U)
7630#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_SHIFT (15U)
7631/*! FSEL
7632 * 0b0..FEED_OUT = FREF
7633 * 0b1..FEED_OUT = FEED
7634 */
7635#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL(x) \
7636 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_SHIFT)) & \
7637 CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_FSEL_MASK)
7638#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
7639#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
7640/*! AFCINIT_SEL
7641 * 0b0..nominal delay
7642 * 0b1..nominal delay * 2
7643 */
7644#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL(x) \
7645 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \
7646 CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK)
7647#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
7648#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
7649#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN(x) \
7650 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \
7651 CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
7652#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
7653#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
7654/*! PBIAS_CTRL
7655 * 0b0..0.50*VDD
7656 * 0b1..0.67*VDD
7657 */
7658#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL(x) \
7659 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \
7660 CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK)
7661#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
7662#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_SHIFT (20U)
7663#define CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL(x) \
7664 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_SHIFT)) & \
7665 CCM_ANALOG_AUDIO_PLL2_MNIT_CTRL_AFC_SEL_MASK)
7666/*! @} */
7667
7668/*! @name VIDEO_PLL1_GEN_CTRL - VIDEO PLL1 General Function Control Register */
7669/*! @{ */
7670#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
7671#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
7672/*! PLL_REF_CLK_SEL
7673 * 0b00..SYS_XTAL
7674 * 0b01..PAD_CLK
7675 * 0b10..Reserved
7676 * 0b11..Reserved
7677 */
7678#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) \
7679 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \
7680 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
7681#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
7682#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
7683/*! PAD_CLK_SEL
7684 * 0b00..CLKIN1 XOR CLKIN2
7685 * 0b01..CLKIN2
7686 * 0b10..CLKIN1
7687 * 0b11..Reserved
7688 */
7689#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL(x) \
7690 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \
7691 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK)
7692#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
7693#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
7694#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS(x) \
7695 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & \
7696 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_MASK)
7697#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
7698#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
7699#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) \
7700 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \
7701 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
7702#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U)
7703#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U)
7704#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST(x) \
7705 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & \
7706 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_MASK)
7707#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
7708#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
7709#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \
7710 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \
7711 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
7712#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
7713#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (13U)
7714#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE(x) \
7715 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & \
7716 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_MASK)
7717#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
7718#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
7719#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) \
7720 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \
7721 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK)
7722#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
7723#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U)
7724#define CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK(x) \
7725 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & \
7726 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_LOCK_MASK)
7727/*! @} */
7728
7729/*! @name VIDEO_PLL1_FDIV_CTL0 - VIDEO PLL1 Divide and Fraction Data Control 0 Register */
7730/*! @{ */
7731#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
7732#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
7733#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV(x) \
7734 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \
7735 CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK)
7736#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
7737#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
7738#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) \
7739 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \
7740 CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK)
7741#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
7742#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
7743#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) \
7744 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \
7745 CCM_ANALOG_VIDEO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK)
7746/*! @} */
7747
7748/*! @name VIDEO_PLL1_FDIV_CTL1 - VIDEO PLL1 Divide and Fraction Data Control 1 Register */
7749/*! @{ */
7750#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
7751#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT (0U)
7752#define CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM(x) \
7753 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT)) & \
7754 CCM_ANALOG_VIDEO_PLL1_FDIV_CTL1_PLL_DSM_MASK)
7755/*! @} */
7756
7757/*! @name VIDEO_PLL1_SSCG_CTRL - VIDEO PLL1 PLL SSCG Control Register */
7758/*! @{ */
7759#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_MASK (0x3U)
7760#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_SHIFT (0U)
7761/*! SEL_PF
7762 * 0b00..Down spread
7763 * 0b01..Up spread
7764 * 0b1x..Center spread
7765 */
7766#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF(x) \
7767 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_SHIFT)) & \
7768 CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SEL_PF_MASK)
7769#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
7770#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
7771#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL(x) \
7772 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & \
7773 CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MRAT_CTL_MASK)
7774#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
7775#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
7776#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL(x) \
7777 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & \
7778 CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
7779#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
7780#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT (31U)
7781#define CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN(x) \
7782 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_SHIFT)) & \
7783 CCM_ANALOG_VIDEO_PLL1_SSCG_CTRL_SSCG_EN_MASK)
7784/*! @} */
7785
7786/*! @name VIDEO_PLL1_MNIT_CTRL - VIDEO PLL1 PLL Monitoring Control Register */
7787/*! @{ */
7788#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_MASK (0x7U)
7789#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_SHIFT (0U)
7790#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP(x) \
7791 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_SHIFT)) & \
7792 CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_ICP_MASK)
7793#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_MASK (0x8U)
7794#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_SHIFT (3U)
7795#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN(x) \
7796 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & \
7797 CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_EN_MASK)
7798#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
7799#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_SHIFT (4U)
7800#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC(x) \
7801 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & \
7802 CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_EXTAFC_MASK)
7803#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_MASK (0x4000U)
7804#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_SHIFT (14U)
7805#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN(x) \
7806 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & \
7807 CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FEED_EN_MASK)
7808#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_MASK (0x8000U)
7809#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_SHIFT (15U)
7810/*! FSEL
7811 * 0b0..FEED_OUT = FREF
7812 * 0b1..FEED_OUT = FEED
7813 */
7814#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL(x) \
7815 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_SHIFT)) & \
7816 CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_FSEL_MASK)
7817#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
7818#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
7819/*! AFCINIT_SEL
7820 * 0b0..nominal delay
7821 * 0b1..nominal delay * 2
7822 */
7823#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL(x) \
7824 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \
7825 CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK)
7826#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
7827#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
7828#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) \
7829 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \
7830 CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
7831#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
7832#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
7833/*! PBIAS_CTRL
7834 * 0b0..0.50*VDD
7835 * 0b1..0.67*VDD
7836 */
7837#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL(x) \
7838 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \
7839 CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK)
7840#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
7841#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (20U)
7842#define CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL(x) \
7843 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & \
7844 CCM_ANALOG_VIDEO_PLL1_MNIT_CTRL_AFC_SEL_MASK)
7845/*! @} */
7846
7847/*! @name DRAM_PLL_GEN_CTRL - DRAM PLL General Function Control Register */
7848/*! @{ */
7849#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
7850#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
7851/*! PLL_REF_CLK_SEL
7852 * 0b00..SYS_XTAL
7853 * 0b01..PAD_CLK
7854 * 0b10..Reserved
7855 * 0b11..Reserved
7856 */
7857#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) \
7858 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \
7859 CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
7860#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
7861#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
7862/*! PAD_CLK_SEL
7863 * 0b00..CLKIN1 XOR CLKIN2
7864 * 0b01..CLKIN2
7865 * 0b10..CLKIN1
7866 * 0b11..Reserved
7867 */
7868#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL(x) \
7869 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \
7870 CCM_ANALOG_DRAM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
7871#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
7872#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
7873#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS(x) \
7874 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & \
7875 CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_MASK)
7876#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
7877#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
7878#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) \
7879 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \
7880 CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
7881#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
7882#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
7883#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST(x) \
7884 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_SHIFT)) & \
7885 CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_MASK)
7886#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x1000U)
7887#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (12U)
7888#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \
7889 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \
7890 CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
7891#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_MASK (0x2000U)
7892#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_SHIFT (13U)
7893#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE(x) \
7894 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & \
7895 CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_MASK)
7896#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000U)
7897#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (16U)
7898#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) \
7899 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \
7900 CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
7901#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
7902#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
7903#define CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK(x) \
7904 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & \
7905 CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_LOCK_MASK)
7906/*! @} */
7907
7908/*! @name DRAM_PLL_FDIV_CTL0 - DRAM PLL Divide and Fraction Data Control 0 Register */
7909/*! @{ */
7910#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
7911#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
7912#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV(x) \
7913 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \
7914 CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
7915#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
7916#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
7917#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV(x) \
7918 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \
7919 CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
7920#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
7921#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
7922#define CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) \
7923 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \
7924 CCM_ANALOG_DRAM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
7925/*! @} */
7926
7927/*! @name DRAM_PLL_FDIV_CTL1 - DRAM PLL Divide and Fraction Data Control 1 Register */
7928/*! @{ */
7929#define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_MASK (0xFFFFU)
7930#define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_SHIFT (0U)
7931#define CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM(x) \
7932 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_SHIFT)) & \
7933 CCM_ANALOG_DRAM_PLL_FDIV_CTL1_PLL_DSM_MASK)
7934/*! @} */
7935
7936/*! @name DRAM_PLL_SSCG_CTRL - DRAM PLL PLL SSCG Control Register */
7937/*! @{ */
7938#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_MASK (0x3U)
7939#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_SHIFT (0U)
7940/*! SEL_PF
7941 * 0b00..Down spread
7942 * 0b01..Up spread
7943 * 0b1x..Center spread
7944 */
7945#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF(x) \
7946 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_SHIFT)) & \
7947 CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SEL_PF_MASK)
7948#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_MASK (0x3F0U)
7949#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_SHIFT (4U)
7950#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL(x) \
7951 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_SHIFT)) & \
7952 CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MRAT_CTL_MASK)
7953#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_MASK (0xFF000U)
7954#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT (12U)
7955#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL(x) \
7956 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_SHIFT)) & \
7957 CCM_ANALOG_DRAM_PLL_SSCG_CTRL_PLL_MFREQ_CTL_MASK)
7958#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_MASK (0x80000000U)
7959#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_SHIFT (31U)
7960#define CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN(x) \
7961 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_SHIFT)) & \
7962 CCM_ANALOG_DRAM_PLL_SSCG_CTRL_SSCG_EN_MASK)
7963/*! @} */
7964
7965/*! @name DRAM_PLL_MNIT_CTRL - DRAM PLL PLL Monitoring Control Register */
7966/*! @{ */
7967#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_MASK (0x7U)
7968#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_SHIFT (0U)
7969#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP(x) \
7970 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_DRAM_PLL_MNIT_CTRL_ICP_MASK)
7971#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_MASK (0x8U)
7972#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_SHIFT (3U)
7973#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN(x) \
7974 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & \
7975 CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_EN_MASK)
7976#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_MASK (0x1F0U)
7977#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_SHIFT (4U)
7978#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC(x) \
7979 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & \
7980 CCM_ANALOG_DRAM_PLL_MNIT_CTRL_EXTAFC_MASK)
7981#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_MASK (0x4000U)
7982#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_SHIFT (14U)
7983#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN(x) \
7984 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & \
7985 CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FEED_EN_MASK)
7986#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_MASK (0x8000U)
7987#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_SHIFT (15U)
7988/*! FSEL
7989 * 0b0..FEED_OUT = FREF
7990 * 0b1..FEED_OUT = FEED
7991 */
7992#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL(x) \
7993 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_SHIFT)) & \
7994 CCM_ANALOG_DRAM_PLL_MNIT_CTRL_FSEL_MASK)
7995#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x20000U)
7996#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (17U)
7997/*! AFCINIT_SEL
7998 * 0b0..nominal delay
7999 * 0b1..nominal delay * 2
8000 */
8001#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL(x) \
8002 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \
8003 CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
8004#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x40000U)
8005#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (18U)
8006#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) \
8007 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \
8008 CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
8009#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x80000U)
8010#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (19U)
8011/*! PBIAS_CTRL
8012 * 0b0..0.50*VDD
8013 * 0b1..0.67*VDD
8014 */
8015#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL(x) \
8016 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \
8017 CCM_ANALOG_DRAM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
8018#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_MASK (0x100000U)
8019#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_SHIFT (20U)
8020#define CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL(x) \
8021 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & \
8022 CCM_ANALOG_DRAM_PLL_MNIT_CTRL_AFC_SEL_MASK)
8023/*! @} */
8024
8025/*! @name GPU_PLL_GEN_CTRL - GPU PLL General Function Control Register */
8026/*! @{ */
8027#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
8028#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
8029/*! PLL_REF_CLK_SEL
8030 * 0b00..SYS_XTAL
8031 * 0b01..PAD_CLK
8032 * 0b10..Reserved
8033 * 0b11..Reserved
8034 */
8035#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) \
8036 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \
8037 CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
8038#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
8039#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
8040/*! PAD_CLK_SEL
8041 * 0b00..CLKIN1 XOR CLKIN2
8042 * 0b01..CLKIN2
8043 * 0b10..CLKIN1
8044 * 0b11..Reserved
8045 */
8046#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL(x) \
8047 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \
8048 CCM_ANALOG_GPU_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
8049#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
8050#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
8051#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS(x) \
8052 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & \
8053 CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_BYPASS_MASK)
8054#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
8055#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
8056#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) \
8057 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \
8058 CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
8059#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
8060#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
8061#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST(x) \
8062 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_SHIFT)) & \
8063 CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_RST_MASK)
8064#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
8065#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
8066#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \
8067 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \
8068 CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
8069#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U)
8070#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U)
8071#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE(x) \
8072 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & \
8073 CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_CLKE_MASK)
8074#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
8075#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
8076#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) \
8077 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \
8078 CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
8079#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
8080#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
8081/*! PLL_LOCK_SEL
8082 * 0b0..Using PLL maximum lock time
8083 * 0b1..Using PLL output lock
8084 */
8085#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL(x) \
8086 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & \
8087 CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK)
8088#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
8089#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
8090#define CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK(x) \
8091 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & \
8092 CCM_ANALOG_GPU_PLL_GEN_CTRL_PLL_LOCK_MASK)
8093/*! @} */
8094
8095/*! @name GPU_PLL_FDIV_CTL0 - GPU PLL Divide and Fraction Data Control 0 Register */
8096/*! @{ */
8097#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
8098#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
8099#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV(x) \
8100 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \
8101 CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
8102#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
8103#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
8104#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV(x) \
8105 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \
8106 CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
8107#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
8108#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
8109#define CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) \
8110 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \
8111 CCM_ANALOG_GPU_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
8112/*! @} */
8113
8114/*! @name GPU_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
8115/*! @{ */
8116#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
8117#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
8118#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN(x) \
8119 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & \
8120 CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK)
8121#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
8122#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
8123#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) \
8124 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & \
8125 CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK)
8126#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
8127#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
8128#define CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) \
8129 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & \
8130 CCM_ANALOG_GPU_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK)
8131/*! @} */
8132
8133/*! @name GPU_PLL_MNIT_CTRL - PLL Monitoring Control Register */
8134/*! @{ */
8135#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_MASK (0x3U)
8136#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_SHIFT (0U)
8137#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP(x) \
8138 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_ICP_MASK)
8139#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U)
8140#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U)
8141#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN(x) \
8142 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & \
8143 CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_EN_MASK)
8144#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U)
8145#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U)
8146#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC(x) \
8147 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & \
8148 CCM_ANALOG_GPU_PLL_MNIT_CTRL_EXTAFC_MASK)
8149#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U)
8150#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U)
8151#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN(x) \
8152 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & \
8153 CCM_ANALOG_GPU_PLL_MNIT_CTRL_FEED_EN_MASK)
8154#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_MASK (0x4000U)
8155#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_SHIFT (14U)
8156/*! FSEL
8157 * 0b0..FEED_OUT = FREF
8158 * 0b1..FEED_OUT = FEED
8159 */
8160#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL(x) \
8161 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_GPU_PLL_MNIT_CTRL_FSEL_MASK)
8162#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
8163#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
8164/*! AFCINIT_SEL
8165 * 0b0..nominal delay
8166 * 0b1..nominal delay * 2
8167 */
8168#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL(x) \
8169 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \
8170 CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
8171#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
8172#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
8173#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) \
8174 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \
8175 CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
8176#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
8177#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
8178/*! PBIAS_CTRL
8179 * 0b0..0.50*VDD
8180 * 0b1..0.67*VDD
8181 */
8182#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL(x) \
8183 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \
8184 CCM_ANALOG_GPU_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
8185#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
8186#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U)
8187#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL(x) \
8188 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & \
8189 CCM_ANALOG_GPU_PLL_MNIT_CTRL_AFC_SEL_MASK)
8190#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
8191#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
8192#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK(x) \
8193 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & \
8194 CCM_ANALOG_GPU_PLL_MNIT_CTRL_FOUT_MASK_MASK)
8195#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U)
8196#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U)
8197#define CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN(x) \
8198 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & \
8199 CCM_ANALOG_GPU_PLL_MNIT_CTRL_LRD_EN_MASK)
8200/*! @} */
8201
8202/*! @name M7_ALT_PLL_GEN_CTRL - M7 Alternate PLL General Function Control Register */
8203/*! @{ */
8204#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
8205#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
8206/*! PLL_REF_CLK_SEL
8207 * 0b00..SYS_XTAL
8208 * 0b01..PAD_CLK
8209 * 0b10..Reserved
8210 * 0b11..Reserved
8211 */
8212#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) \
8213 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \
8214 CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
8215#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
8216#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
8217/*! PAD_CLK_SEL
8218 * 0b00..CLKIN1 XOR CLKIN2
8219 * 0b01..CLKIN2
8220 * 0b10..CLKIN1
8221 * 0b11..Reserved
8222 */
8223#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PAD_CLK_SEL(x) \
8224 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \
8225 CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
8226#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
8227#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
8228#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_BYPASS(x) \
8229 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & \
8230 CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_BYPASS_MASK)
8231#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
8232#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
8233#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) \
8234 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \
8235 CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
8236#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
8237#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
8238#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST(x) \
8239 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_SHIFT)) & \
8240 CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_RST_MASK)
8241#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
8242#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
8243#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \
8244 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \
8245 CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
8246#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U)
8247#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U)
8248#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE(x) \
8249 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & \
8250 CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_CLKE_MASK)
8251#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
8252#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
8253#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) \
8254 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \
8255 CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
8256#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
8257#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
8258/*! PLL_LOCK_SEL
8259 * 0b0..Using PLL maximum lock time
8260 * 0b1..Using PLL output lock
8261 */
8262#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SEL(x) \
8263 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & \
8264 CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK)
8265#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
8266#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
8267#define CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK(x) \
8268 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & \
8269 CCM_ANALOG_M7_ALT_PLL_GEN_CTRL_PLL_LOCK_MASK)
8270/*! @} */
8271
8272/*! @name M7_ALT_PLL_FDIV_CTL0 - M7 Alternate PLL Divide and Fraction Data Control 0 Register */
8273/*! @{ */
8274#define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
8275#define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
8276#define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_POST_DIV(x) \
8277 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \
8278 CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
8279#define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
8280#define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
8281#define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_PRE_DIV(x) \
8282 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \
8283 CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
8284#define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
8285#define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
8286#define CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) \
8287 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \
8288 CCM_ANALOG_M7_ALT_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
8289/*! @} */
8290
8291/*! @name M7_ALT_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
8292/*! @{ */
8293#define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
8294#define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
8295#define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_IN(x) \
8296 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & \
8297 CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK)
8298#define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
8299#define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
8300#define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) \
8301 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & \
8302 CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK)
8303#define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
8304#define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
8305#define CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) \
8306 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & \
8307 CCM_ANALOG_M7_ALT_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK)
8308/*! @} */
8309
8310/*! @name M7_ALT_PLL_MNIT_CTRL - PLL Monitoring Control Register */
8311/*! @{ */
8312#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_ICP_MASK (0x3U)
8313#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_ICP_SHIFT (0U)
8314#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_ICP(x) \
8315 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_ICP_SHIFT)) & \
8316 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_ICP_MASK)
8317#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U)
8318#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U)
8319#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_EN(x) \
8320 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & \
8321 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_EN_MASK)
8322#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U)
8323#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U)
8324#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_EXTAFC(x) \
8325 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & \
8326 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_EXTAFC_MASK)
8327#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U)
8328#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U)
8329#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FEED_EN(x) \
8330 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & \
8331 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FEED_EN_MASK)
8332#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FSEL_MASK (0x4000U)
8333#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FSEL_SHIFT (14U)
8334/*! FSEL
8335 * 0b0..FEED_OUT = FREF
8336 * 0b1..FEED_OUT = FEED
8337 */
8338#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FSEL(x) \
8339 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FSEL_SHIFT)) & \
8340 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FSEL_MASK)
8341#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
8342#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
8343/*! AFCINIT_SEL
8344 * 0b0..nominal delay
8345 * 0b1..nominal delay * 2
8346 */
8347#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFCINIT_SEL(x) \
8348 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \
8349 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
8350#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
8351#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
8352#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) \
8353 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \
8354 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
8355#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
8356#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
8357/*! PBIAS_CTRL
8358 * 0b0..0.50*VDD
8359 * 0b1..0.67*VDD
8360 */
8361#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL(x) \
8362 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \
8363 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
8364#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
8365#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U)
8366#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_SEL(x) \
8367 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & \
8368 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_AFC_SEL_MASK)
8369#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
8370#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
8371#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FOUT_MASK(x) \
8372 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & \
8373 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_FOUT_MASK_MASK)
8374#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U)
8375#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U)
8376#define CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_LRD_EN(x) \
8377 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & \
8378 CCM_ANALOG_M7_ALT_PLL_MNIT_CTRL_LRD_EN_MASK)
8379/*! @} */
8380
8381/*! @name ARM_PLL_GEN_CTRL - ARM PLL General Function Control Register */
8382/*! @{ */
8383#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
8384#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
8385/*! PLL_REF_CLK_SEL
8386 * 0b00..SYS_XTAL
8387 * 0b01..PAD_CLK
8388 * 0b10..Reserved
8389 * 0b11..Reserved
8390 */
8391#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL(x) \
8392 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \
8393 CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
8394#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
8395#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
8396/*! PAD_CLK_SEL
8397 * 0b00..CLKIN1 XOR CLKIN2
8398 * 0b01..CLKIN2
8399 * 0b10..CLKIN1
8400 * 0b11..Reserved
8401 */
8402#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL(x) \
8403 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \
8404 CCM_ANALOG_ARM_PLL_GEN_CTRL_PAD_CLK_SEL_MASK)
8405#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
8406#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
8407#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS(x) \
8408 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT)) & \
8409 CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_MASK)
8410#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
8411#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
8412#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE(x) \
8413 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \
8414 CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
8415#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_MASK (0x200U)
8416#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_SHIFT (9U)
8417#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST(x) \
8418 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_SHIFT)) & \
8419 CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_MASK)
8420#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
8421#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
8422#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \
8423 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \
8424 CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
8425#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_MASK (0x800U)
8426#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_SHIFT (11U)
8427#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE(x) \
8428 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_SHIFT)) & \
8429 CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_MASK)
8430#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
8431#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
8432#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS(x) \
8433 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \
8434 CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_EXT_BYPASS_MASK)
8435#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
8436#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
8437/*! PLL_LOCK_SEL
8438 * 0b0..Using PLL maximum lock time
8439 * 0b1..Using PLL output lock
8440 */
8441#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL(x) \
8442 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & \
8443 CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SEL_MASK)
8444#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
8445#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SHIFT (31U)
8446#define CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK(x) \
8447 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_SHIFT)) & \
8448 CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_LOCK_MASK)
8449/*! @} */
8450
8451/*! @name ARM_PLL_FDIV_CTL0 - ARM PLL Divide and Fraction Data Control 0 Register */
8452/*! @{ */
8453#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
8454#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
8455#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV(x) \
8456 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \
8457 CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_POST_DIV_MASK)
8458#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
8459#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
8460#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV(x) \
8461 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \
8462 CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_PRE_DIV_MASK)
8463#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
8464#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
8465#define CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV(x) \
8466 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \
8467 CCM_ANALOG_ARM_PLL_FDIV_CTL0_PLL_MAIN_DIV_MASK)
8468/*! @} */
8469
8470/*! @name ARM_PLL_LOCKD_CTRL - PLL Lock Detector Control Register */
8471/*! @{ */
8472#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
8473#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
8474#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN(x) \
8475 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & \
8476 CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_IN_MASK)
8477#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
8478#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
8479#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT(x) \
8480 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & \
8481 CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_OUT_MASK)
8482#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
8483#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
8484#define CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY(x) \
8485 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & \
8486 CCM_ANALOG_ARM_PLL_LOCKD_CTRL_LOCK_CON_DLY_MASK)
8487/*! @} */
8488
8489/*! @name ARM_PLL_MNIT_CTRL - PLL Monitoring Control Register */
8490/*! @{ */
8491#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_MASK (0x3U)
8492#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_SHIFT (0U)
8493#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP(x) \
8494 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_ICP_MASK)
8495#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_MASK (0x4U)
8496#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_SHIFT (2U)
8497#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN(x) \
8498 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_SHIFT)) & \
8499 CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_EN_MASK)
8500#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_MASK (0xF8U)
8501#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_SHIFT (3U)
8502#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC(x) \
8503 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_SHIFT)) & \
8504 CCM_ANALOG_ARM_PLL_MNIT_CTRL_EXTAFC_MASK)
8505#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_MASK (0x2000U)
8506#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_SHIFT (13U)
8507#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN(x) \
8508 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_SHIFT)) & \
8509 CCM_ANALOG_ARM_PLL_MNIT_CTRL_FEED_EN_MASK)
8510#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_MASK (0x4000U)
8511#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_SHIFT (14U)
8512/*! FSEL
8513 * 0b0..FEED_OUT = FREF
8514 * 0b1..FEED_OUT = FEED
8515 */
8516#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL(x) \
8517 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_SHIFT)) & CCM_ANALOG_ARM_PLL_MNIT_CTRL_FSEL_MASK)
8518#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
8519#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
8520/*! AFCINIT_SEL
8521 * 0b0..nominal delay
8522 * 0b1..nominal delay * 2
8523 */
8524#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL(x) \
8525 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \
8526 CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFCINIT_SEL_MASK)
8527#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
8528#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
8529#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN(x) \
8530 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \
8531 CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
8532#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
8533#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
8534/*! PBIAS_CTRL
8535 * 0b0..0.50*VDD
8536 * 0b1..0.67*VDD
8537 */
8538#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL(x) \
8539 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \
8540 CCM_ANALOG_ARM_PLL_MNIT_CTRL_PBIAS_CTRL_MASK)
8541#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
8542#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_SHIFT (19U)
8543#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL(x) \
8544 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_SHIFT)) & \
8545 CCM_ANALOG_ARM_PLL_MNIT_CTRL_AFC_SEL_MASK)
8546#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
8547#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
8548#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK(x) \
8549 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_SHIFT)) & \
8550 CCM_ANALOG_ARM_PLL_MNIT_CTRL_FOUT_MASK_MASK)
8551#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_MASK (0x200000U)
8552#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_SHIFT (21U)
8553#define CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN(x) \
8554 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_SHIFT)) & \
8555 CCM_ANALOG_ARM_PLL_MNIT_CTRL_LRD_EN_MASK)
8556/*! @} */
8557
8558/*! @name SYS_PLL1_GEN_CTRL - SYS PLL1 General Function Control Register */
8559/*! @{ */
8560#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
8561#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
8562/*! PLL_REF_CLK_SEL
8563 * 0b00..SYS_XTAL
8564 * 0b01..PAD_CLK
8565 * 0b10..Reserved
8566 * 0b11..Reserved
8567 */
8568#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL(x) \
8569 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \
8570 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
8571#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
8572#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
8573/*! PAD_CLK_SEL
8574 * 0b00..CLKIN1 XOR CLKIN2
8575 * 0b01..CLKIN2
8576 * 0b10..CLKIN1
8577 * 0b11..Reserved
8578 */
8579#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL(x) \
8580 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \
8581 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PAD_CLK_SEL_MASK)
8582#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
8583#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
8584#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS(x) \
8585 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT)) & \
8586 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_MASK)
8587#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
8588#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
8589#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE(x) \
8590 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \
8591 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
8592#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_MASK (0x200U)
8593#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT (9U)
8594#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST(x) \
8595 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT)) & \
8596 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_MASK)
8597#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
8598#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
8599#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \
8600 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \
8601 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
8602#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_MASK (0x800U)
8603#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_SHIFT (11U)
8604#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE(x) \
8605 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_SHIFT)) & \
8606 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_MASK)
8607#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK (0x1000U)
8608#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT (12U)
8609#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE(x) \
8610 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT)) & \
8611 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK)
8612#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_MASK (0x2000U)
8613#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_SHIFT (13U)
8614#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE(x) \
8615 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_SHIFT)) & \
8616 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_MASK)
8617#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK (0x4000U)
8618#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT (14U)
8619#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE(x) \
8620 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT)) & \
8621 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK)
8622#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_MASK (0x8000U)
8623#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_SHIFT (15U)
8624#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE(x) \
8625 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_SHIFT)) & \
8626 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_MASK)
8627#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK (0x10000U)
8628#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT (16U)
8629#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE(x) \
8630 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT)) & \
8631 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK)
8632#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_MASK (0x20000U)
8633#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_SHIFT (17U)
8634#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE(x) \
8635 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_SHIFT)) & \
8636 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_MASK)
8637#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK (0x40000U)
8638#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT (18U)
8639#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE(x) \
8640 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT)) & \
8641 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK)
8642#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_MASK (0x80000U)
8643#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_SHIFT (19U)
8644#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE(x) \
8645 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_SHIFT)) & \
8646 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_MASK)
8647#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK (0x100000U)
8648#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT (20U)
8649#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE(x) \
8650 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT)) & \
8651 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK)
8652#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_MASK (0x200000U)
8653#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_SHIFT (21U)
8654#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE(x) \
8655 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_SHIFT)) & \
8656 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_MASK)
8657#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK (0x400000U)
8658#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT (22U)
8659#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE(x) \
8660 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT)) & \
8661 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK)
8662#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_MASK (0x800000U)
8663#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_SHIFT (23U)
8664#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE(x) \
8665 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_SHIFT)) & \
8666 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_MASK)
8667#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK (0x1000000U)
8668#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT (24U)
8669#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE(x) \
8670 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT)) & \
8671 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK)
8672#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_MASK (0x2000000U)
8673#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_SHIFT (25U)
8674#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE(x) \
8675 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_SHIFT)) & \
8676 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_MASK)
8677#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK (0x4000000U)
8678#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT (26U)
8679#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE(x) \
8680 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT)) & \
8681 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK)
8682#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_MASK (0x8000000U)
8683#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_SHIFT (27U)
8684#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE(x) \
8685 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_SHIFT)) & \
8686 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_MASK)
8687#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
8688#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
8689#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS(x) \
8690 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \
8691 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_EXT_BYPASS_MASK)
8692#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
8693#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
8694/*! PLL_LOCK_SEL
8695 * 0b0..Using PLL maximum lock time
8696 * 0b1..Using PLL output lock
8697 */
8698#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL(x) \
8699 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & \
8700 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SEL_MASK)
8701#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
8702#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SHIFT (31U)
8703#define CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK(x) \
8704 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_SHIFT)) & \
8705 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_MASK)
8706/*! @} */
8707
8708/*! @name SYS_PLL1_FDIV_CTL0 - SYS PLL1 Divide and Fraction Data Control 0 Register */
8709/*! @{ */
8710#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
8711#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
8712#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV(x) \
8713 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \
8714 CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK)
8715#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
8716#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
8717#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV(x) \
8718 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \
8719 CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK)
8720#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
8721#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
8722#define CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV(x) \
8723 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \
8724 CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK)
8725/*! @} */
8726
8727/*! @name SYS_PLL1_LOCKD_CTRL - PLL Lock Detector Control Register */
8728/*! @{ */
8729#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
8730#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
8731#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN(x) \
8732 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & \
8733 CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_IN_MASK)
8734#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
8735#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
8736#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT(x) \
8737 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & \
8738 CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_OUT_MASK)
8739#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
8740#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
8741#define CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY(x) \
8742 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & \
8743 CCM_ANALOG_SYS_PLL1_LOCKD_CTRL_LOCK_CON_DLY_MASK)
8744/*! @} */
8745
8746/*! @name SYS_PLL1_MNIT_CTRL - PLL Monitoring Control Register */
8747/*! @{ */
8748#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_MASK (0x3U)
8749#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_SHIFT (0U)
8750#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP(x) \
8751 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL1_MNIT_CTRL_ICP_MASK)
8752#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_MASK (0x4U)
8753#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_SHIFT (2U)
8754#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN(x) \
8755 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_SHIFT)) & \
8756 CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_EN_MASK)
8757#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_MASK (0xF8U)
8758#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_SHIFT (3U)
8759#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC(x) \
8760 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_SHIFT)) & \
8761 CCM_ANALOG_SYS_PLL1_MNIT_CTRL_EXTAFC_MASK)
8762#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_MASK (0x2000U)
8763#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_SHIFT (13U)
8764#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN(x) \
8765 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_SHIFT)) & \
8766 CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FEED_EN_MASK)
8767#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_MASK (0x4000U)
8768#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_SHIFT (14U)
8769/*! FSEL
8770 * 0b0..FEED_OUT = FREF
8771 * 0b1..FEED_OUT = FEED
8772 */
8773#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL(x) \
8774 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_SHIFT)) & \
8775 CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FSEL_MASK)
8776#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
8777#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
8778/*! AFCINIT_SEL
8779 * 0b0..nominal delay
8780 * 0b1..nominal delay * 2
8781 */
8782#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL(x) \
8783 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \
8784 CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFCINIT_SEL_MASK)
8785#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
8786#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
8787#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN(x) \
8788 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \
8789 CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
8790#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
8791#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
8792/*! PBIAS_CTRL
8793 * 0b0..0.50*VDD
8794 * 0b1..0.67*VDD
8795 */
8796#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL(x) \
8797 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \
8798 CCM_ANALOG_SYS_PLL1_MNIT_CTRL_PBIAS_CTRL_MASK)
8799#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
8800#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_SHIFT (19U)
8801#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL(x) \
8802 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_SHIFT)) & \
8803 CCM_ANALOG_SYS_PLL1_MNIT_CTRL_AFC_SEL_MASK)
8804#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
8805#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
8806#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK(x) \
8807 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_SHIFT)) & \
8808 CCM_ANALOG_SYS_PLL1_MNIT_CTRL_FOUT_MASK_MASK)
8809#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_MASK (0x200000U)
8810#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_SHIFT (21U)
8811#define CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN(x) \
8812 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_SHIFT)) & \
8813 CCM_ANALOG_SYS_PLL1_MNIT_CTRL_LRD_EN_MASK)
8814/*! @} */
8815
8816/*! @name SYS_PLL2_GEN_CTRL - SYS PLL2 General Function Control Register */
8817/*! @{ */
8818#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
8819#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
8820/*! PLL_REF_CLK_SEL
8821 * 0b00..SYS_XTAL
8822 * 0b01..PAD_CLK
8823 * 0b10..Reserved
8824 * 0b11..Reserved
8825 */
8826#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL(x) \
8827 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \
8828 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
8829#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
8830#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
8831/*! PAD_CLK_SEL
8832 * 0b00..CLKIN1 XOR CLKIN2
8833 * 0b01..CLKIN2
8834 * 0b10..CLKIN1
8835 * 0b11..Reserved
8836 */
8837#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL(x) \
8838 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \
8839 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PAD_CLK_SEL_MASK)
8840#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
8841#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
8842#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS(x) \
8843 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT)) & \
8844 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_MASK)
8845#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
8846#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
8847#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE(x) \
8848 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \
8849 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
8850#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_MASK (0x200U)
8851#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_SHIFT (9U)
8852#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST(x) \
8853 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_SHIFT)) & \
8854 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_MASK)
8855#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
8856#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
8857#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \
8858 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \
8859 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
8860#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_MASK (0x800U)
8861#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_SHIFT (11U)
8862#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE(x) \
8863 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_SHIFT)) & \
8864 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_MASK)
8865#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK (0x1000U)
8866#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT (12U)
8867#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE(x) \
8868 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_SHIFT)) & \
8869 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_OVERRIDE_MASK)
8870#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_MASK (0x2000U)
8871#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_SHIFT (13U)
8872#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE(x) \
8873 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_SHIFT)) & \
8874 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_MASK)
8875#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK (0x4000U)
8876#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT (14U)
8877#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE(x) \
8878 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_SHIFT)) & \
8879 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_OVERRIDE_MASK)
8880#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_MASK (0x8000U)
8881#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_SHIFT (15U)
8882#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE(x) \
8883 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_SHIFT)) & \
8884 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_MASK)
8885#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK (0x10000U)
8886#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT (16U)
8887#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE(x) \
8888 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_SHIFT)) & \
8889 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_OVERRIDE_MASK)
8890#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_MASK (0x20000U)
8891#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_SHIFT (17U)
8892#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE(x) \
8893 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_SHIFT)) & \
8894 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_MASK)
8895#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK (0x40000U)
8896#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT (18U)
8897#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE(x) \
8898 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_SHIFT)) & \
8899 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_OVERRIDE_MASK)
8900#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_MASK (0x80000U)
8901#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_SHIFT (19U)
8902#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE(x) \
8903 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_SHIFT)) & \
8904 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_MASK)
8905#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK (0x100000U)
8906#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT (20U)
8907#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE(x) \
8908 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_SHIFT)) & \
8909 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_OVERRIDE_MASK)
8910#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_MASK (0x200000U)
8911#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_SHIFT (21U)
8912#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE(x) \
8913 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_SHIFT)) & \
8914 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_MASK)
8915#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK (0x400000U)
8916#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT (22U)
8917#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE(x) \
8918 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_SHIFT)) & \
8919 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_OVERRIDE_MASK)
8920#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_MASK (0x800000U)
8921#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_SHIFT (23U)
8922#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE(x) \
8923 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_SHIFT)) & \
8924 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_MASK)
8925#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK (0x1000000U)
8926#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT (24U)
8927#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE(x) \
8928 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_SHIFT)) & \
8929 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_OVERRIDE_MASK)
8930#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_MASK (0x2000000U)
8931#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_SHIFT (25U)
8932#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE(x) \
8933 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_SHIFT)) & \
8934 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_MASK)
8935#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK (0x4000000U)
8936#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT (26U)
8937#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE(x) \
8938 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_SHIFT)) & \
8939 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_OVERRIDE_MASK)
8940#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_MASK (0x8000000U)
8941#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_SHIFT (27U)
8942#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE(x) \
8943 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_SHIFT)) & \
8944 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_MASK)
8945#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
8946#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
8947#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS(x) \
8948 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \
8949 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_EXT_BYPASS_MASK)
8950#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
8951#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
8952/*! PLL_LOCK_SEL
8953 * 0b0..Using PLL maximum lock time
8954 * 0b1..Using PLL output lock
8955 */
8956#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL(x) \
8957 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & \
8958 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SEL_MASK)
8959#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
8960#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SHIFT (31U)
8961#define CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK(x) \
8962 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_SHIFT)) & \
8963 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_LOCK_MASK)
8964/*! @} */
8965
8966/*! @name SYS_PLL2_FDIV_CTL0 - SYS PLL2 Divide and Fraction Data Control 0 Register */
8967/*! @{ */
8968#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
8969#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
8970#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV(x) \
8971 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \
8972 CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_POST_DIV_MASK)
8973#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
8974#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
8975#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV(x) \
8976 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \
8977 CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_PRE_DIV_MASK)
8978#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
8979#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
8980#define CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV(x) \
8981 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \
8982 CCM_ANALOG_SYS_PLL2_FDIV_CTL0_PLL_MAIN_DIV_MASK)
8983/*! @} */
8984
8985/*! @name SYS_PLL2_LOCKD_CTRL - PLL Lock Detector Control Register */
8986/*! @{ */
8987#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
8988#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
8989#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN(x) \
8990 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & \
8991 CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_IN_MASK)
8992#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
8993#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
8994#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT(x) \
8995 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & \
8996 CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_OUT_MASK)
8997#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
8998#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
8999#define CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY(x) \
9000 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & \
9001 CCM_ANALOG_SYS_PLL2_LOCKD_CTRL_LOCK_CON_DLY_MASK)
9002/*! @} */
9003
9004/*! @name SYS_PLL2_MNIT_CTRL - PLL Monitoring Control Register */
9005/*! @{ */
9006#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_MASK (0x3U)
9007#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_SHIFT (0U)
9008#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP(x) \
9009 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL2_MNIT_CTRL_ICP_MASK)
9010#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_MASK (0x4U)
9011#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_SHIFT (2U)
9012#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN(x) \
9013 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_SHIFT)) & \
9014 CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_EN_MASK)
9015#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_MASK (0xF8U)
9016#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_SHIFT (3U)
9017#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC(x) \
9018 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_SHIFT)) & \
9019 CCM_ANALOG_SYS_PLL2_MNIT_CTRL_EXTAFC_MASK)
9020#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_MASK (0x2000U)
9021#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_SHIFT (13U)
9022#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN(x) \
9023 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_SHIFT)) & \
9024 CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FEED_EN_MASK)
9025#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_MASK (0x4000U)
9026#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_SHIFT (14U)
9027/*! FSEL
9028 * 0b0..FEED_OUT = FREF
9029 * 0b1..FEED_OUT = FEED
9030 */
9031#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL(x) \
9032 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_SHIFT)) & \
9033 CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FSEL_MASK)
9034#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
9035#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
9036/*! AFCINIT_SEL
9037 * 0b0..nominal delay
9038 * 0b1..nominal delay * 2
9039 */
9040#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL(x) \
9041 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \
9042 CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFCINIT_SEL_MASK)
9043#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
9044#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
9045#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN(x) \
9046 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \
9047 CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_EN_MASK)
9048#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK (0x40000U)
9049#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT (18U)
9050/*! PBIAS_CTRL
9051 * 0b0..0.50*VDD
9052 * 0b1..0.67*VDD
9053 */
9054#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL(x) \
9055 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_SHIFT)) & \
9056 CCM_ANALOG_SYS_PLL2_MNIT_CTRL_PBIAS_CTRL_MASK)
9057#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_MASK (0x80000U)
9058#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_SHIFT (19U)
9059#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL(x) \
9060 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_SHIFT)) & \
9061 CCM_ANALOG_SYS_PLL2_MNIT_CTRL_AFC_SEL_MASK)
9062#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_MASK (0x100000U)
9063#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_SHIFT (20U)
9064#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK(x) \
9065 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_SHIFT)) & \
9066 CCM_ANALOG_SYS_PLL2_MNIT_CTRL_FOUT_MASK_MASK)
9067#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_MASK (0x200000U)
9068#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_SHIFT (21U)
9069#define CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN(x) \
9070 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_SHIFT)) & \
9071 CCM_ANALOG_SYS_PLL2_MNIT_CTRL_LRD_EN_MASK)
9072/*! @} */
9073
9074/*! @name SYS_PLL3_GEN_CTRL - SYS PLL3 General Function Control Register */
9075/*! @{ */
9076#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_MASK (0x3U)
9077#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT (0U)
9078/*! PLL_REF_CLK_SEL
9079 * 0b00..SYS_XTAL
9080 * 0b01..PAD_CLK
9081 * 0b10..Reserved
9082 * 0b11..Reserved
9083 */
9084#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL(x) \
9085 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_SHIFT)) & \
9086 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_REF_CLK_SEL_MASK)
9087#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_MASK (0xCU)
9088#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_SHIFT (2U)
9089/*! PAD_CLK_SEL
9090 * 0b00..CLKIN1 XOR CLKIN2
9091 * 0b01..CLKIN2
9092 * 0b10..CLKIN1
9093 * 0b11..Reserved
9094 */
9095#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL(x) \
9096 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_SHIFT)) & \
9097 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PAD_CLK_SEL_MASK)
9098#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_MASK (0x10U)
9099#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_SHIFT (4U)
9100#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS(x) \
9101 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_SHIFT)) & \
9102 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_MASK)
9103#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_MASK (0x100U)
9104#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT (8U)
9105#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE(x) \
9106 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_SHIFT)) & \
9107 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_OVERRIDE_MASK)
9108#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_MASK (0x200U)
9109#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_SHIFT (9U)
9110#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST(x) \
9111 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_SHIFT)) & \
9112 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_MASK)
9113#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK (0x400U)
9114#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT (10U)
9115#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE(x) \
9116 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_SHIFT)) & \
9117 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_OVERRIDE_MASK)
9118#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_MASK (0x800U)
9119#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_SHIFT (11U)
9120#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE(x) \
9121 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_SHIFT)) & \
9122 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_MASK)
9123#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_MASK (0x10000000U)
9124#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_SHIFT (28U)
9125#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS(x) \
9126 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_SHIFT)) & \
9127 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_EXT_BYPASS_MASK)
9128#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_MASK (0x20000000U)
9129#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_SHIFT (29U)
9130/*! PLL_LOCK_SEL
9131 * 0b0..Using PLL maximum lock time
9132 * 0b1..Using PLL output lock
9133 */
9134#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL(x) \
9135 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_SHIFT)) & \
9136 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SEL_MASK)
9137#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_MASK (0x80000000U)
9138#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SHIFT (31U)
9139#define CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK(x) \
9140 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_SHIFT)) & \
9141 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_LOCK_MASK)
9142/*! @} */
9143
9144/*! @name SYS_PLL3_FDIV_CTL0 - SYS PLL3 Divide and Fraction Data Control 0 Register */
9145/*! @{ */
9146#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_MASK (0x7U)
9147#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_SHIFT (0U)
9148#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV(x) \
9149 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_SHIFT)) & \
9150 CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_POST_DIV_MASK)
9151#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_MASK (0x3F0U)
9152#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_SHIFT (4U)
9153#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV(x) \
9154 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_SHIFT)) & \
9155 CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_PRE_DIV_MASK)
9156#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_MASK (0x3FF000U)
9157#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_SHIFT (12U)
9158#define CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV(x) \
9159 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_SHIFT)) & \
9160 CCM_ANALOG_SYS_PLL3_FDIV_CTL0_PLL_MAIN_DIV_MASK)
9161/*! @} */
9162
9163/*! @name SYS_PLL3_LOCKD_CTRL - PLL Lock Detector Control Register */
9164/*! @{ */
9165#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_MASK (0x3U)
9166#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_SHIFT (0U)
9167#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN(x) \
9168 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_SHIFT)) & \
9169 CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_IN_MASK)
9170#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_MASK (0xCU)
9171#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_SHIFT (2U)
9172#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT(x) \
9173 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_SHIFT)) & \
9174 CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_OUT_MASK)
9175#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_MASK (0x30U)
9176#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_SHIFT (4U)
9177#define CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY(x) \
9178 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_SHIFT)) & \
9179 CCM_ANALOG_SYS_PLL3_LOCKD_CTRL_LOCK_CON_DLY_MASK)
9180/*! @} */
9181
9182/*! @name SYS_PLL3_MNIT_CTRL - PLL Monitoring Control Register */
9183/*! @{ */
9184#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_MASK (0x3U)
9185#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_SHIFT (0U)
9186#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP(x) \
9187 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_SHIFT)) & CCM_ANALOG_SYS_PLL3_MNIT_CTRL_ICP_MASK)
9188#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_MASK (0x4U)
9189#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_SHIFT (2U)
9190#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN(x) \
9191 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_SHIFT)) & \
9192 CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFC_EN_MASK)
9193#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_MASK (0xF8U)
9194#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_SHIFT (3U)
9195#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC(x) \
9196 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_SHIFT)) & \
9197 CCM_ANALOG_SYS_PLL3_MNIT_CTRL_EXTAFC_MASK)
9198#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_MASK (0x2000U)
9199#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_SHIFT (13U)
9200#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN(x) \
9201 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_SHIFT)) & \
9202 CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FEED_EN_MASK)
9203#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_MASK (0x4000U)
9204#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_SHIFT (14U)
9205/*! FSEL
9206 * 0b0..FEED_OUT = FREF
9207 * 0b1..FEED_OUT = FEED
9208 */
9209#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL(x) \
9210 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_SHIFT)) & \
9211 CCM_ANALOG_SYS_PLL3_MNIT_CTRL_FSEL_MASK)
9212#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_MASK (0x10000U)
9213#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_SHIFT (16U)
9214/*! AFCINIT_SEL
9215 * 0b0..nominal delay
9216 * 0b1..nominal delay * 2
9217 */
9218#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL(x) \
9219 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_SHIFT)) & \
9220 CCM_ANALOG_SYS_PLL3_MNIT_CTRL_AFCINIT_SEL_MASK)
9221#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_MASK (0x20000U)
9222#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT (17U)
9223#define CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN(x) \
9224 (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_SYS_PLL3_MNIT_CTRL_PBIAS_CTRL_EN_SHIFT)) & \
9225