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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/drivers/driver_reset.cmake14
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/drivers/fsl_clock.c786
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/drivers/fsl_clock.h1254
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/drivers/fsl_iomuxc.h746
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/drivers/fsl_memory.h146
5 files changed, 2946 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/drivers/driver_reset.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/drivers/driver_reset.cmake
new file mode 100644
index 000000000..989530f6f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/drivers/driver_reset.cmake
@@ -0,0 +1,14 @@
1if(NOT DRIVER_RESET_INCLUDED)
2
3 set(DRIVER_RESET_INCLUDED true CACHE BOOL "driver_reset component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 )
7
8 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
9 ${CMAKE_CURRENT_LIST_DIR}/.
10 )
11
12
13
14endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/drivers/fsl_clock.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/drivers/fsl_clock.c
new file mode 100644
index 000000000..6fc2f2232
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/drivers/fsl_clock.c
@@ -0,0 +1,786 @@
1/*
2 * Copyright 2018 - 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7#include "fsl_common.h"
8#include "fsl_clock.h"
9
10/*******************************************************************************
11 * Definitions
12 ******************************************************************************/
13/* Component ID definition, used by tools. */
14#ifndef FSL_COMPONENT_ID
15#define FSL_COMPONENT_ID "platform.drivers.clock"
16#endif
17
18#define FracPLL_GNRL_CTL_Offset (0U)
19#define FracPLL_FDIV_CTL0_Offset (4U)
20#define FracPLL_FDIV_CTL1_Offset (8U)
21
22#define IntegerPLL_GNRL_CTL_Offset (0U)
23#define IntegerPLL_DIV_CTL_Offset (4U)
24/*******************************************************************************
25 * Prototypes
26 ******************************************************************************/
27
28/*******************************************************************************
29 * Variables
30 ******************************************************************************/
31
32/*******************************************************************************
33 * Code
34 ******************************************************************************/
35/*!
36 * brief Gets the clock frequency for a specific clock name.
37 *
38 * This function checks the current clock configurations and then calculates
39 * the clock frequency for a specific clock name defined in clock_name_t.
40 *
41 * param clockName Clock names defined in clock_name_t
42 * return Clock frequency value in hertz
43 */
44uint32_t CLOCK_GetFreq(clock_name_t clockName)
45{
46 uint32_t freq;
47 uint32_t temp;
48
49 switch (clockName)
50 {
51 case kCLOCK_CoreM7Clk:
52 freq = CLOCK_GetCoreM7Freq();
53 break;
54 case kCLOCK_AxiClk:
55 freq = CLOCK_GetAxiFreq();
56 break;
57 case kCLOCK_AhbClk:
58 freq = CLOCK_GetAhbFreq();
59 break;
60 case kCLOCK_IpgClk:
61 {
62 temp = CLOCK_GetAhbFreq();
63 freq = temp / CLOCK_GetRootPostDivider(kCLOCK_RootIpg);
64 break;
65 }
66 default:
67 freq = 0U;
68 break;
69 }
70 return freq;
71}
72
73/*!
74 * brief Get the CCM Cortex M7 core frequency.
75 *
76 * return Clock frequency; If the clock is invalid, returns 0.
77 */
78uint32_t CLOCK_GetCoreM7Freq(void)
79{
80 uint32_t freq;
81 uint32_t pre = CLOCK_GetRootPreDivider(kCLOCK_RootM7);
82 uint32_t post = CLOCK_GetRootPostDivider(kCLOCK_RootM7);
83
84 switch (CLOCK_GetRootMux(kCLOCK_RootM7))
85 {
86 case (uint32_t)kCLOCK_M7RootmuxOsc24M:
87 freq = OSC24M_CLK_FREQ;
88 break;
89 case (uint32_t)kCLOCK_M7RootmuxSysPll2Div5:
90 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl) / 5U;
91 break;
92 case (uint32_t)kCLOCK_M7RootmuxSysPll2Div4:
93 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl) / 4U;
94 break;
95 case (uint32_t)kCLOCK_M7RootmuxSysPll1Div3:
96 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / 3U;
97 break;
98 case (uint32_t)kCLOCK_M7RootmuxSysPll1:
99 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl);
100 break;
101 case (uint32_t)kCLOCK_M7RootmuxAudioPll1:
102 freq = CLOCK_GetPllFreq(kCLOCK_AudioPll1Ctrl);
103 break;
104 case (uint32_t)kCLOCK_M7RootmuxVideoPll1:
105 freq = CLOCK_GetPllFreq(kCLOCK_VideoPll1Ctrl);
106 break;
107 case (uint32_t)kCLOCK_M7RootmuxSysPll3:
108 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll3Ctrl);
109 break;
110 default:
111 freq = 0U;
112 break;
113 }
114
115 return freq / pre / post;
116}
117
118/*!
119 * brief Get the CCM Axi bus frequency.
120 *
121 * return Clock frequency; If the clock is invalid, returns 0.
122 */
123uint32_t CLOCK_GetAxiFreq(void)
124{
125 uint32_t freq;
126 uint32_t pre = CLOCK_GetRootPreDivider(kCLOCK_RootAxi);
127 uint32_t post = CLOCK_GetRootPostDivider(kCLOCK_RootAxi);
128
129 switch (CLOCK_GetRootMux(kCLOCK_RootAxi))
130 {
131 case (uint32_t)kCLOCK_AxiRootmuxOsc24M:
132 freq = OSC24M_CLK_FREQ;
133 break;
134 case (uint32_t)kCLOCK_AxiRootmuxSysPll2Div3:
135 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl) / 3U;
136 break;
137 case (uint32_t)kCLOCK_AxiRootmuxSysPll2Div4:
138 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl) / 4U;
139 break;
140 case (uint32_t)kCLOCK_AxiRootmuxSysPll2:
141 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl);
142 break;
143 case (uint32_t)kCLOCK_AxiRootmuxAudioPll1:
144 freq = CLOCK_GetPllFreq(kCLOCK_AudioPll1Ctrl);
145 break;
146 case (uint32_t)kCLOCK_AxiRootmuxVideoPll1:
147 freq = CLOCK_GetPllFreq(kCLOCK_VideoPll1Ctrl);
148 break;
149 case (uint32_t)kCLOCK_AxiRootmuxSysPll1Div8:
150 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / 8UL;
151 break;
152 case (uint32_t)kCLOCK_AxiRootmuxSysPll1:
153 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl);
154 break;
155 default:
156 freq = 0U;
157 break;
158 }
159
160 return freq / pre / post;
161}
162
163/*!
164 * brief Get the CCM Ahb bus frequency.
165 *
166 * return Clock frequency; If the clock is invalid, returns 0.
167 */
168uint32_t CLOCK_GetAhbFreq(void)
169{
170 uint32_t freq;
171 uint32_t pre = CLOCK_GetRootPreDivider(kCLOCK_RootAhb);
172 uint32_t post = CLOCK_GetRootPostDivider(kCLOCK_RootAhb);
173
174 switch (CLOCK_GetRootMux(kCLOCK_RootAhb))
175 {
176 case (uint32_t)kCLOCK_AhbRootmuxOsc24M:
177 freq = OSC24M_CLK_FREQ;
178 break;
179 case (uint32_t)kCLOCK_AhbRootmuxSysPll1Div6:
180 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / 6U;
181 break;
182 case (uint32_t)kCLOCK_AhbRootmuxSysPll1Div2:
183 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) / 2U;
184 break;
185 case (uint32_t)kCLOCK_AhbRootmuxSysPll1:
186 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl);
187 break;
188 case (uint32_t)kCLOCK_AhbRootmuxSysPll2Div8:
189 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll2Ctrl) / 8U;
190 break;
191 case (uint32_t)kCLOCK_AhbRootmuxSysPll3:
192 freq = CLOCK_GetPllFreq(kCLOCK_SystemPll3Ctrl);
193 break;
194 case (uint32_t)kCLOCK_AhbRootmuxAudioPll1:
195 freq = CLOCK_GetPllFreq(kCLOCK_AudioPll1Ctrl);
196 break;
197 case (uint32_t)kCLOCK_AhbRootmuxVideoPll1:
198 freq = CLOCK_GetPllFreq(kCLOCK_VideoPll1Ctrl);
199 break;
200 default:
201 freq = 0U;
202 break;
203 }
204
205 return freq / pre / post;
206}
207
208/*!
209 * brief Gets PLL reference clock frequency.
210 *
211 * param type fractional pll type.
212
213 * return Clock frequency
214 */
215uint32_t CLOCK_GetPllRefClkFreq(clock_pll_ctrl_t ctrl)
216{
217 uint32_t refClkFreq = 0U;
218 uint8_t clkSel = 0U;
219
220 if (ctrl < kCLOCK_ArmPllCtrl)
221 {
222 clkSel =
223 (uint8_t)((CCM_ANALOG_TUPLE_REG(CCM_ANALOG, ctrl) & CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK));
224 }
225 else
226 {
227 clkSel = (uint8_t)(CCM_ANALOG_TUPLE_REG(CCM_ANALOG, ctrl) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK);
228 }
229
230 switch (clkSel)
231 {
232 case kANALOG_PllRefOsc24M:
233 refClkFreq = OSC24M_CLK_FREQ;
234 break;
235
236 case kANALOG_PllPadClk:
237 /* The value of PAD CLK need user to define according to the actual condition. */
238 refClkFreq = CLKPAD_FREQ;
239 break;
240
241 default:
242 refClkFreq = 0U;
243 break;
244 }
245
246 return refClkFreq;
247}
248
249/*!
250 * brief Gets PLL clock frequency.
251 *
252 * param type fractional pll type.
253
254 * return Clock frequency
255 */
256uint32_t CLOCK_GetPllFreq(clock_pll_ctrl_t pll)
257{
258 uint32_t pllFreq = 0U;
259 uint32_t pllRefFreq = 0U;
260 bool intergerPllBypass = false;
261 bool fracPllBypass = false;
262
263 pllRefFreq = CLOCK_GetPllRefClkFreq(pll);
264
265 switch (pll)
266 {
267 /* Integer PLL frequency */
268 case kCLOCK_ArmPllCtrl:
269 intergerPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_ArmPllPwrBypassCtrl);
270 break;
271 case kCLOCK_SystemPll1Ctrl:
272 intergerPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll1InternalPll1BypassCtrl);
273 break;
274 case kCLOCK_SystemPll2Ctrl:
275 intergerPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll2InternalPll1BypassCtrl);
276 break;
277 case kCLOCK_SystemPll3Ctrl:
278 intergerPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_SysPll3InternalPll1BypassCtrl);
279 break;
280 /* Fractional PLL frequency */
281 case kCLOCK_AudioPll1Ctrl:
282 fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_AudioPll1BypassCtrl);
283 break;
284 case kCLOCK_AudioPll2Ctrl:
285 fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_AudioPll2BypassCtrl);
286 break;
287 case kCLOCK_VideoPll1Ctrl:
288 fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_VideoPll1BypassCtrl);
289 break;
290 case kCLOCK_DramPllCtrl:
291 fracPllBypass = CLOCK_IsPllBypassed(CCM_ANALOG, kCLOCK_DramPllInternalPll1BypassCtrl);
292 break;
293 default:
294 fracPllBypass = false;
295 break;
296 }
297 if (pll < kCLOCK_ArmPllCtrl)
298 {
299 if (fracPllBypass)
300 {
301 pllFreq = pllRefFreq;
302 }
303 else
304 {
305 pllFreq = CLOCK_GetFracPllFreq(CCM_ANALOG, pll, pllRefFreq);
306 }
307 }
308 else
309 {
310 if (intergerPllBypass)
311 {
312 /* if PLL is bypass, return reference clock directly */
313 pllFreq = pllRefFreq;
314 }
315 else
316 {
317 pllFreq = CLOCK_GetIntegerPllFreq(CCM_ANALOG, pll, pllRefFreq, false);
318 }
319 }
320
321 return (uint32_t)pllFreq;
322}
323
324/*!
325 * brief Initializes the ANALOG ARM PLL.
326 *
327 * param config Pointer to the configuration structure(see ref ccm_analog_integer_pll_config_t enumeration).
328 *
329 * note This function can't detect whether the Arm PLL has been enabled and
330 * used by some IPs.
331 */
332void CLOCK_InitArmPll(const ccm_analog_integer_pll_config_t *config)
333{
334 assert(config != NULL);
335
336 /* Integer PLL configuration */
337 CLOCK_InitIntegerPll(CCM_ANALOG, config, kCLOCK_ArmPllCtrl);
338 /* Disable PLL bypass */
339 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_ArmPllPwrBypassCtrl, false);
340 /* Enable and power up PLL clock. */
341 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_ArmPllClke);
342
343 /* Wait for PLL to be locked. */
344 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_ArmPllCtrl))
345 {
346 }
347}
348
349/*!
350 * brief De-initialize the ARM PLL.
351 */
352void CLOCK_DeinitArmPll(void)
353{
354 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_ArmPllCtrl);
355}
356
357/*!
358 * brief Initializes the ANALOG AUDIO PLL1.
359 *
360 * param config Pointer to the configuration structure(see ref ccm_analog_frac_pll_config_t enumeration).
361 *
362 * note This function can't detect whether the AUDIO PLL has been enabled and
363 * used by some IPs.
364 */
365void CLOCK_InitAudioPll1(const ccm_analog_frac_pll_config_t *config)
366{
367 assert(config != NULL);
368
369 /* Disable PLL bypass */
370 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_AudioPll1BypassCtrl, false);
371 /* Fractional pll configuration */
372 CLOCK_InitFracPll(CCM_ANALOG, config, kCLOCK_AudioPll1Ctrl);
373 /* Enable and power up PLL clock. */
374 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_AudioPll1Clke);
375
376 /* Wait for PLL to be locked. */
377 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_AudioPll1Ctrl))
378 {
379 }
380}
381
382/*!
383 * brief De-initialize the Audio PLL1.
384 */
385void CLOCK_DeinitAudioPll1(void)
386{
387 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_AudioPll1Ctrl);
388}
389
390/*!
391 * brief Initializes the ANALOG AUDIO PLL2.
392 *
393 * param config Pointer to the configuration structure(see ref ccm_analog_frac_pll_config_t enumeration).
394 *
395 * note This function can't detect whether the AUDIO PLL has been enabled and
396 * used by some IPs.
397 */
398void CLOCK_InitAudioPll2(const ccm_analog_frac_pll_config_t *config)
399{
400 assert(config != NULL);
401
402 /* Disable PLL bypass */
403 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_AudioPll2BypassCtrl, false);
404 /* Fractional pll configuration */
405 CLOCK_InitFracPll(CCM_ANALOG, config, kCLOCK_AudioPll2Ctrl);
406 /* Enable and power up PLL clock. */
407 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_AudioPll2Clke);
408
409 /* Wait for PLL to be locked. */
410 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_AudioPll2Ctrl))
411 {
412 }
413}
414
415/*!
416 * brief De-initialize the Audio PLL2.
417 */
418void CLOCK_DeinitAudioPll2(void)
419{
420 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_AudioPll2Ctrl);
421}
422
423/*!
424 * brief Initializes the ANALOG VIDEO PLL1.
425 *
426 * param config Pointer to the configuration structure(see ref ccm_analog_frac_pll_config_t enumeration).
427 *
428 */
429void CLOCK_InitVideoPll1(const ccm_analog_frac_pll_config_t *config)
430{
431 assert(config != NULL);
432
433 /* Disable PLL bypass */
434 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_VideoPll1BypassCtrl, false);
435 /* Fractional pll configuration */
436 CLOCK_InitFracPll(CCM_ANALOG, config, kCLOCK_VideoPll1Ctrl);
437 /* Enable and power up PLL clock. */
438 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_VideoPll1Clke);
439
440 /* Wait for PLL to be locked. */
441 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_VideoPll1Ctrl))
442 {
443 }
444}
445
446/*!
447 * brief De-initialize the Video PLL1.
448 */
449void CLOCK_DeinitVideoPll1(void)
450{
451 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_VideoPll1Ctrl);
452}
453
454/*!
455 * brief Initializes the ANALOG SYS PLL1.
456 *
457 * param config Pointer to the configuration structure(see ref ccm_analog_integer_pll_config_t enumeration).
458 *
459 * note This function can't detect whether the SYS PLL has been enabled and
460 * used by some IPs.
461 */
462void CLOCK_InitSysPll1(const ccm_analog_integer_pll_config_t *config)
463{
464 assert(config != NULL);
465
466 /* Integer PLL configuration */
467 CLOCK_InitIntegerPll(CCM_ANALOG, config, kCLOCK_SystemPll1Ctrl);
468 /* Disable PLL bypass */
469 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll1InternalPll1BypassCtrl, false);
470 /* Enable and power up PLL clock. */
471 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_SystemPll1Clke);
472
473 /* Wait for PLL to be locked. */
474 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_SystemPll1Ctrl))
475 {
476 }
477}
478
479/*!
480 * brief De-initialize the System PLL1.
481 */
482void CLOCK_DeinitSysPll1(void)
483{
484 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_SystemPll1Ctrl);
485}
486
487/*!
488 * brief Initializes the ANALOG SYS PLL2.
489 *
490 * param config Pointer to the configuration structure(see ref ccm_analog_integer_pll_config_t enumeration).
491 *
492 * note This function can't detect whether the SYS PLL has been enabled and
493 * used by some IPs.
494 */
495void CLOCK_InitSysPll2(const ccm_analog_integer_pll_config_t *config)
496{
497 assert(config != NULL);
498
499 /* Integer PLL configuration */
500 CLOCK_InitIntegerPll(CCM_ANALOG, config, kCLOCK_SystemPll2Ctrl);
501 /* Disable PLL bypass */
502 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll2InternalPll1BypassCtrl, false);
503 /* Enable and power up PLL clock. */
504 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_SystemPll2Clke);
505
506 /* Wait for PLL to be locked. */
507 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_SystemPll2Ctrl))
508 {
509 }
510}
511
512/*!
513 * brief De-initialize the System PLL2.
514 */
515void CLOCK_DeinitSysPll2(void)
516{
517 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_SystemPll2Ctrl);
518}
519
520/*!
521 * brief Initializes the ANALOG SYS PLL3.
522 *
523 * param config Pointer to the configuration structure(see ref ccm_analog_integer_pll_config_t enumeration).
524 *
525 * note This function can't detect whether the SYS PLL has been enabled and
526 * used by some IPs.
527 */
528void CLOCK_InitSysPll3(const ccm_analog_integer_pll_config_t *config)
529{
530 assert(config != NULL);
531
532 /* Integer PLL configuration */
533 CLOCK_InitIntegerPll(CCM_ANALOG, config, kCLOCK_SystemPll3Ctrl);
534 /* Disable PLL bypass */
535 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_SysPll3InternalPll1BypassCtrl, false);
536 /* Enable and power up PLL clock. */
537 CLOCK_EnableAnalogClock(CCM_ANALOG, kCLOCK_SystemPll3Clke);
538
539 /* Wait for PLL to be locked. */
540 while (!CLOCK_IsPllLocked(CCM_ANALOG, kCLOCK_SystemPll3Ctrl))
541 {
542 }
543}
544
545/*!
546 * brief De-initialize the System PLL3.
547 */
548void CLOCK_DeinitSysPll3(void)
549{
550 CLOCK_PowerDownPll(CCM_ANALOG, kCLOCK_SystemPll3Ctrl);
551}
552
553/*!
554 * brief Initializes the ANALOG Fractional PLL.
555 *
556 * param base CCM ANALOG base address.
557 * param config Pointer to the configuration structure(see ref ccm_analog_frac_pll_config_t enumeration).
558 * param type fractional pll type.
559 *
560 */
561void CLOCK_InitFracPll(CCM_ANALOG_Type *base, const ccm_analog_frac_pll_config_t *config, clock_pll_ctrl_t type)
562{
563 assert(config != NULL);
564 assert((config->mainDiv >= 64U) && (config->mainDiv <= 1023U));
565 assert((config->preDiv >= 1U) && (config->preDiv <= 63U));
566 assert(config->postDiv <= 6U);
567
568 assert(type < kCLOCK_ArmPllCtrl);
569
570 uint32_t fracCfg0 = CCM_ANALOG_TUPLE_REG_OFF(base, type, FracPLL_GNRL_CTL_Offset) &
571 ~((uint32_t)1 << CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT);
572 uint32_t fracCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, FracPLL_FDIV_CTL0_Offset);
573 uint32_t fracCfg2 = CCM_ANALOG_TUPLE_REG_OFF(base, type, FracPLL_FDIV_CTL1_Offset);
574
575 /* power down the fractional PLL first */
576 CCM_ANALOG_TUPLE_REG_OFF(base, type, FracPLL_GNRL_CTL_Offset) = fracCfg0;
577
578 CCM_ANALOG_TUPLE_REG_OFF(base, type, FracPLL_FDIV_CTL0_Offset) =
579 (fracCfg1 &
580 (~(CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK | CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK |
581 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK))) |
582 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV(config->mainDiv) |
583 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV(config->preDiv) |
584 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV(config->postDiv);
585
586 CCM_ANALOG_TUPLE_REG_OFF(base, type, FracPLL_FDIV_CTL1_Offset) =
587 (fracCfg2 & (~(CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_MASK))) |
588 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM(config->dsm);
589
590 /* power up the fractional pll */
591 CCM_ANALOG_TUPLE_REG_OFF(base, type, FracPLL_GNRL_CTL_Offset) |= CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_MASK;
592}
593
594/*!
595 * brief Gets the ANALOG Fractional PLL clock frequency.
596 *
597 * param base CCM_ANALOG base pointer.
598 * param type fractional pll type.
599 * param fractional pll reference clock frequency
600 *
601 * return Clock frequency
602 */
603uint32_t CLOCK_GetFracPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq)
604{
605 assert(type < kCLOCK_ArmPllCtrl);
606
607 uint32_t fracCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, FracPLL_FDIV_CTL0_Offset);
608 uint32_t fracCfg2 = CCM_ANALOG_TUPLE_REG_OFF(base, type, FracPLL_FDIV_CTL1_Offset);
609 uint64_t fracClk = 0U;
610
611 uint32_t mainDiv = CCM_BIT_FIELD_EXTRACTION(fracCfg1, CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK,
612 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT);
613 uint8_t preDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg1, CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK,
614 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT);
615 uint8_t postDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(fracCfg1, CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK,
616 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT);
617 uint32_t dsm = CCM_BIT_FIELD_EXTRACTION(fracCfg2, CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_MASK,
618 CCM_ANALOG_AUDIO_PLL1_FDIV_CTL1_PLL_DSM_SHIFT);
619
620 fracClk = (uint64_t)((uint64_t)refClkFreq * ((uint64_t)mainDiv * 65536ULL + dsm) /
621 (65536ULL * (uint32_t)preDiv * (1ULL << postDiv)));
622
623 return (uint32_t)fracClk;
624}
625
626/*!
627 * brief Initializes the ANALOG Integer PLL.
628 *
629 * param base CCM ANALOG base address
630 * param config Pointer to the configuration structure(see ref ccm_analog_integer_pll_config_t enumeration).
631 * param type integer pll type
632 *
633 */
634void CLOCK_InitIntegerPll(CCM_ANALOG_Type *base, const ccm_analog_integer_pll_config_t *config, clock_pll_ctrl_t type)
635{
636 assert(config != NULL);
637 assert((config->mainDiv >= 64U) && (config->mainDiv <= 1023U));
638 assert((config->preDiv >= 1U) && (config->preDiv <= 63U));
639 assert(config->postDiv <= 6U);
640
641 assert(type >= kCLOCK_SystemPll1Ctrl);
642
643 uint32_t integerCfg0 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_GNRL_CTL_Offset) &
644 ~((uint32_t)1 << CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT);
645 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset);
646
647 /* power down the Integer PLL first */
648 CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_GNRL_CTL_Offset) = integerCfg0;
649
650 /* pll mux configuration */
651 CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_GNRL_CTL_Offset) =
652 (integerCfg0 & (~CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_REF_CLK_SEL_MASK)) | config->refSel;
653
654 /* divider configuration */
655 CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset) =
656 (integerCfg1 &
657 (~(CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK | CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK |
658 CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK))) |
659 CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV(config->mainDiv) |
660 CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV(config->preDiv) |
661 CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV(config->postDiv);
662
663 /* power up the Integer PLL */
664 CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_GNRL_CTL_Offset) |= CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_MASK;
665}
666
667/*!
668 * brief Get the ANALOG Integer PLL clock frequency.
669 *
670 * param base CCM ANALOG base address.
671 * param type integer pll type
672 * param pll1Bypass pll1 bypass flag
673 *
674 * return Clock frequency
675 */
676uint32_t CLOCK_GetIntegerPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq, bool pll1Bypass)
677{
678 assert(type >= kCLOCK_SystemPll1Ctrl);
679
680 uint32_t integerCfg1 = CCM_ANALOG_TUPLE_REG_OFF(base, type, IntegerPLL_DIV_CTL_Offset);
681 uint64_t pllOutClock = 0U;
682
683 uint32_t mainDiv = CCM_BIT_FIELD_EXTRACTION(integerCfg1, CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_MASK,
684 CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_MAIN_DIV_SHIFT);
685 uint8_t preDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(integerCfg1, CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_MASK,
686 CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_PRE_DIV_SHIFT);
687 uint8_t postDiv = (uint8_t)CCM_BIT_FIELD_EXTRACTION(integerCfg1, CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_MASK,
688 CCM_ANALOG_SYS_PLL1_FDIV_CTL0_PLL_POST_DIV_SHIFT);
689
690 if (pll1Bypass)
691 {
692 pllOutClock = refClkFreq;
693 }
694
695 else
696 {
697 pllOutClock = (uint64_t)refClkFreq * mainDiv / (((uint64_t)(1U) << postDiv) * preDiv);
698 }
699
700 return (uint32_t)pllOutClock;
701}
702
703/*!
704 * brief Set root clock divider
705 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
706 *
707 * param ccmRootClk Root control (see ref clock_root_control_t enumeration)
708 * param pre Pre divider value (1-8)
709 * param post Post divider value (1-64)
710 */
711void CLOCK_SetRootDivider(clock_root_control_t ccmRootClk, uint32_t pre, uint32_t post)
712{
713 assert((pre <= 8U) && (pre != 0U));
714 assert((post <= 64U) && (post != 0U));
715
716 CCM_REG(ccmRootClk) = (CCM_REG(ccmRootClk) & (~(CCM_TARGET_ROOT_PRE_PODF_MASK | CCM_TARGET_ROOT_POST_PODF_MASK))) |
717 CCM_TARGET_ROOT_PRE_PODF(pre - 1U) | CCM_TARGET_ROOT_POST_PODF(post - 1U);
718}
719
720/*!
721 * brief Update clock root in one step, for dynamical clock switching
722 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
723 *
724 * param ccmRootClk Root control (see ref clock_root_control_t enumeration)
725 * param root mux value (see ref _ccm_rootmux_xxx enumeration)
726 * param pre Pre divider value (0-7, divider=n+1)
727 * param post Post divider value (0-63, divider=n+1)
728 */
729void CLOCK_UpdateRoot(clock_root_control_t ccmRootClk, uint32_t mux, uint32_t pre, uint32_t post)
730{
731 assert((pre <= 8U) && (pre != 0U));
732 assert((post <= 64U) && (post != 0U));
733
734 CCM_REG(ccmRootClk) =
735 (CCM_REG(ccmRootClk) &
736 (~(CCM_TARGET_ROOT_MUX_MASK | CCM_TARGET_ROOT_PRE_PODF_MASK | CCM_TARGET_ROOT_POST_PODF_MASK))) |
737 CCM_TARGET_ROOT_MUX(mux) | CCM_TARGET_ROOT_PRE_PODF(pre - 1U) | CCM_TARGET_ROOT_POST_PODF(post - 1U);
738}
739
740/*!
741 * brief Enable CCGR clock gate and root clock gate for each module
742 * User should set specific gate for each module according to the description
743 * of the table of system clocks, gating and override in CCM chapter of
744 * reference manual. Take care of that one module may need to set more than
745 * one clock gate.
746 *
747 * param ccmGate Gate control for each module (see ref clock_ip_name_t enumeration).
748 */
749void CLOCK_EnableClock(clock_ip_name_t ccmGate)
750{
751 uint32_t ccgr = CCM_TUPLE_CCGR(ccmGate);
752
753 CCM_REG_SET(ccgr) = (uint32_t)kCLOCK_ClockNeededAll;
754#if !(defined(NOT_CONFIG_CLK_ROOT) && NOT_CONFIG_CLK_ROOT)
755 uint32_t rootClk = CCM_TUPLE_ROOT(ccmGate);
756 /* if root clock is 0xFFFFU, then skip enable root clock */
757 if (rootClk != 0xFFFFU)
758 {
759 CCM_REG_SET(rootClk) = CCM_TARGET_ROOT_SET_ENABLE_MASK;
760 }
761#endif
762}
763
764/*!
765 * brief Disable CCGR clock gate for the each module
766 * User should set specific gate for each module according to the description
767 * of the table of system clocks, gating and override in CCM chapter of
768 * reference manual. Take care of that one module may need to set more than
769 * one clock gate.
770 *
771 * param ccmGate Gate control for each module (see ref clock_ip_name_t enumeration).
772 */
773void CLOCK_DisableClock(clock_ip_name_t ccmGate)
774{
775 uint32_t ccgr = CCM_TUPLE_CCGR(ccmGate);
776
777 CCM_REG(ccgr) = (uint32_t)kCLOCK_ClockNotNeeded;
778#if !(defined(NOT_CONFIG_CLK_ROOT) && NOT_CONFIG_CLK_ROOT)
779 uint32_t rootClk = CCM_TUPLE_ROOT(ccmGate);
780 /* if root clock is 0xFFFFU, then skip disable root clock */
781 if (rootClk != 0xFFFFU)
782 {
783 CCM_REG_CLR(rootClk) = CCM_TARGET_ROOT_CLR_ENABLE_MASK;
784 }
785#endif
786}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/drivers/fsl_clock.h
new file mode 100644
index 000000000..3aa6c538b
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/drivers/fsl_clock.h
@@ -0,0 +1,1254 @@
1/*
2 * Copyright 2018 -2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CLOCK_H_
9#define _FSL_CLOCK_H_
10
11#include "fsl_device_registers.h"
12#include "fsl_common.h"
13#include <stdint.h>
14#include <stdbool.h>
15#include <stddef.h>
16#include <assert.h>
17
18/*!
19 * @addtogroup clock
20 * @{
21 */
22
23/*******************************************************************************
24 * Definitions
25 ******************************************************************************/
26
27/*! @name Driver version */
28/*@{*/
29/*! @brief CLOCK driver version 2.2.2. */
30#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))
31/*@}*/
32
33/* Definition for delay API in clock driver, users can redefine it to the real application. */
34#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
35#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL)
36#endif
37
38/*!
39 * @brief XTAL 24M clock frequency.
40 */
41#define OSC24M_CLK_FREQ 24000000U
42/*!
43 * @brief pad clock frequency.
44 */
45#define CLKPAD_FREQ 0U
46
47/*! @brief Clock ip name array for ECSPI. */
48#define ECSPI_CLOCKS \
49 { \
50 kCLOCK_IpInvalid, kCLOCK_Ecspi1, kCLOCK_Ecspi2, kCLOCK_Ecspi3, \
51 }
52
53/*! @brief Clock ip name array for GPIO. */
54#define GPIO_CLOCKS \
55 { \
56 kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5, \
57 }
58
59/*! @brief Clock ip name array for GPT. */
60#define GPT_CLOCKS \
61 { \
62 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3, kCLOCK_Gpt4, kCLOCK_Gpt5, kCLOCK_Gpt6, \
63 }
64
65/*! @brief Clock ip name array for I2C. */
66#define I2C_CLOCKS \
67 { \
68 kCLOCK_IpInvalid, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, kCLOCK_I2c4, \
69 }
70
71/*! @brief Clock ip name array for IOMUX. */
72#define IOMUX_CLOCKS \
73 { \
74 kCLOCK_Iomux, \
75 }
76
77/*! @brief Clock ip name array for IPMUX. */
78#define IPMUX_CLOCKS \
79 { \
80 kCLOCK_Ipmux1, kCLOCK_Ipmux2, kCLOCK_Ipmux3, kCLOCK_Ipmux4, \
81 }
82
83/*! @brief Clock ip name array for PWM. */
84#define PWM_CLOCKS \
85 { \
86 kCLOCK_IpInvalid, kCLOCK_Pwm1, kCLOCK_Pwm2, kCLOCK_Pwm3, kCLOCK_Pwm4, \
87 }
88
89/*! @brief Clock ip name array for RDC. */
90#define RDC_CLOCKS \
91 { \
92 kCLOCK_Rdc, \
93 }
94
95/*! @brief Clock ip name array for SAI. */
96#define SAI_CLOCKS \
97 { \
98 kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_IpInvalid, kCLOCK_Sai5, kCLOCK_Sai6, \
99 kCLOCK_Sai7 \
100 }
101
102/*! @brief Clock ip name array for RDC SEMA42. */
103#define RDC_SEMA42_CLOCKS \
104 { \
105 kCLOCK_IpInvalid, kCLOCK_Sema42_1, kCLOCK_Sema42_2 \
106 }
107
108/*! @brief Clock ip name array for UART. */
109#define UART_CLOCKS \
110 { \
111 kCLOCK_IpInvalid, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, \
112 }
113
114/*! @brief Clock ip name array for USDHC. */
115#define USDHC_CLOCKS \
116 { \
117 kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2, kCLOCK_Usdhc3 \
118 }
119
120/*! @brief Clock ip name array for WDOG. */
121#define WDOG_CLOCKS \
122 { \
123 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3 \
124 }
125
126/*! @brief Clock ip name array for TEMPSENSOR. */
127#define TMU_CLOCKS \
128 { \
129 kCLOCK_TempSensor, \
130 }
131
132/*! @brief Clock ip name array for SDMA. */
133#define SDMA_CLOCKS \
134 { \
135 kCLOCK_Sdma1, kCLOCK_Sdma2, kCLOCK_Sdma3 \
136 }
137
138/*! @brief Clock ip name array for MU. */
139#define MU_CLOCKS \
140 { \
141 kCLOCK_Mu \
142 }
143
144/*! @brief Clock ip name array for QSPI. */
145#define QSPI_CLOCKS \
146 { \
147 kCLOCK_Qspi \
148 }
149
150/*! @brief Clock ip name array for PDM. */
151#define PDM_CLOCKS \
152 { \
153 kCLOCK_Pdm \
154 }
155
156/*! @brief Clock ip name array for ASRC. */
157#define ASRC_CLOCKS \
158 { \
159 kCLOCK_Asrc \
160 }
161
162/*!
163 * @brief CCM reg macros to extract corresponding registers bit field.
164 */
165#define CCM_BIT_FIELD_EXTRACTION(val, mask, shift) (((val) & (mask)) >> (shift))
166
167/*!
168 * @brief CCM reg macros to map corresponding registers.
169 */
170#define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uint32_t)(root) + (off))))
171#define CCM_REG(root) CCM_REG_OFF(root, 0U)
172#define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
173#define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
174
175/*!
176 * @brief CCM Analog registers offset.
177 */
178#define AUDIO_PLL1_GEN_CTRL_OFFSET 0x00
179#define AUDIO_PLL2_GEN_CTRL_OFFSET 0x14
180#define VIDEO_PLL1_GEN_CTRL_OFFSET 0x28
181#define GPU_PLL_GEN_CTRL_OFFSET 0x64
182#define VPU_PLL_GEN_CTRL_OFFSET 0x74
183#define ARM_PLL_GEN_CTRL_OFFSET 0x84
184#define SYS_PLL1_GEN_CTRL_OFFSET 0x94
185#define SYS_PLL2_GEN_CTRL_OFFSET 0x104
186#define SYS_PLL3_GEN_CTRL_OFFSET 0x114
187#define DRAM_PLL_GEN_CTRL_OFFSET 0x50
188
189/*!
190 * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
191 */
192#define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFFU) << 16U) | ((shift)))
193#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)(tuple)) & 0x1FU)
194#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
195 (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFFU) + (off))))
196#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
197
198/*!
199 * @brief CCM CCGR and root tuple
200 */
201#define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root))
202#define CCM_TUPLE_CCGR(tuple) ((uint32_t)(&(CCM)->CCGR[(uint32_t)(tuple) >> 16U].CCGR))
203#define CCM_TUPLE_ROOT(tuple) ((uint32_t)(&(CCM)->ROOT[(uint32_t)(tuple)&0xFFFFU].TARGET_ROOT))
204
205/*! @brief Clock name used to get clock frequency. */
206typedef enum _clock_name
207{
208 kCLOCK_CoreM7Clk, /*!< ARM M7 Core clock */
209
210 kCLOCK_AxiClk, /*!< Main AXI bus clock. */
211 kCLOCK_AhbClk, /*!< AHB bus clock. */
212 kCLOCK_IpgClk, /*!< IPG bus clock. */
213
214 /* -------------------------------- Other clock --------------------------*/
215} clock_name_t;
216
217#define kCLOCK_CoreSysClk kCLOCK_CoreM7Clk /*!< For compatible with other platforms without CCM. */
218#define CLOCK_GetCoreSysClkFreq CLOCK_GetCoreM7Freq /*!< For compatible with other platforms without CCM. */
219
220/*! @brief CCM CCGR gate control. */
221typedef enum _clock_ip_name
222{
223 kCLOCK_IpInvalid = -1,
224
225 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
226
227 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
228
229 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
230 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
231 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
232
233 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
234 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
235 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
236 kCLOCK_Gpio4 = CCM_TUPLE(14U, 33U), /*!< GPIO4 Clock Gate.*/
237 kCLOCK_Gpio5 = CCM_TUPLE(15U, 33U), /*!< GPIO5 Clock Gate.*/
238
239 kCLOCK_Gpt1 = CCM_TUPLE(16U, 107U), /*!< GPT1 Clock Gate.*/
240 kCLOCK_Gpt2 = CCM_TUPLE(17U, 108U), /*!< GPT2 Clock Gate.*/
241 kCLOCK_Gpt3 = CCM_TUPLE(18U, 109U), /*!< GPT3 Clock Gate.*/
242 kCLOCK_Gpt4 = CCM_TUPLE(19U, 110U), /*!< GPT4 Clock Gate.*/
243 kCLOCK_Gpt5 = CCM_TUPLE(20U, 111U), /*!< GPT5 Clock Gate.*/
244 kCLOCK_Gpt6 = CCM_TUPLE(21U, 112U), /*!< GPT6 Clock Gate.*/
245
246 kCLOCK_I2c1 = CCM_TUPLE(23U, 90U), /*!< I2C1 Clock Gate.*/
247 kCLOCK_I2c2 = CCM_TUPLE(24U, 91U), /*!< I2C2 Clock Gate.*/
248 kCLOCK_I2c3 = CCM_TUPLE(25U, 92U), /*!< I2C3 Clock Gate.*/
249 kCLOCK_I2c4 = CCM_TUPLE(26U, 93U), /*!< I2C4 Clock Gate.*/
250
251 kCLOCK_Iomux = CCM_TUPLE(27U, 33U), /*!< IOMUX Clock Gate.*/
252 kCLOCK_Ipmux1 = CCM_TUPLE(28U, 33U), /*!< IPMUX1 Clock Gate.*/
253 kCLOCK_Ipmux2 = CCM_TUPLE(29U, 33U), /*!< IPMUX2 Clock Gate.*/
254 kCLOCK_Ipmux3 = CCM_TUPLE(30U, 33U), /*!< IPMUX3 Clock Gate.*/
255 kCLOCK_Ipmux4 = CCM_TUPLE(31U, 33U), /*!< IPMUX4 Clock Gate.*/
256
257 kCLOCK_Mu = CCM_TUPLE(33U, 33U), /*!< MU Clock Gate.*/
258
259 kCLOCK_Ocram = CCM_TUPLE(35U, 16U), /*!< OCRAM Clock Gate.*/
260 kCLOCK_OcramS = CCM_TUPLE(36U, 32U), /*!< OCRAM S Clock Gate.*/
261
262 kCLOCK_Pwm1 = CCM_TUPLE(40U, 103U), /*!< PWM1 Clock Gate.*/
263 kCLOCK_Pwm2 = CCM_TUPLE(41U, 104U), /*!< PWM2 Clock Gate.*/
264 kCLOCK_Pwm3 = CCM_TUPLE(42U, 105U), /*!< PWM3 Clock Gate.*/
265 kCLOCK_Pwm4 = CCM_TUPLE(43U, 106U), /*!< PWM4 Clock Gate.*/
266
267 kCLOCK_Qspi = CCM_TUPLE(47U, 87U), /*!< QSPI Clock Gate.*/
268
269 kCLOCK_Rdc = CCM_TUPLE(49U, 33U), /*!< RDC Clock Gate.*/
270
271 kCLOCK_Sai2 = CCM_TUPLE(52U, 76U), /*!< SAI2 Clock Gate.*/
272 kCLOCK_Sai3 = CCM_TUPLE(53U, 77U), /*!< SAI3 Clock Gate.*/
273 kCLOCK_Sai5 = CCM_TUPLE(55U, 79U), /*!< SAI5 Clock Gate.*/
274 kCLOCK_Sai6 = CCM_TUPLE(56U, 80U), /*!< SAI6 Clock Gate.*/
275 kCLOCK_Sai7 = CCM_TUPLE(101U, 134U), /*!< SAI7 Clock Gate.*/
276
277 kCLOCK_Sdma1 = CCM_TUPLE(58U, 33U), /*!< SDMA1 Clock Gate.*/
278 kCLOCK_Sdma2 = CCM_TUPLE(59U, 35U), /*!< SDMA2 Clock Gate.*/
279
280 kCLOCK_Sec_Debug = CCM_TUPLE(60U, 33U), /*!< SEC_DEBUG Clock Gate.*/
281
282 kCLOCK_Sema42_1 = CCM_TUPLE(61U, 33U), /*!< RDC SEMA42 Clock Gate.*/
283 kCLOCK_Sema42_2 = CCM_TUPLE(62U, 33U), /*!< RDC SEMA42 Clock Gate.*/
284
285 kCLOCK_Sim_display = CCM_TUPLE(63U, 16U), /*!< SIM_Display Clock Gate.*/
286 kCLOCK_Sim_m = CCM_TUPLE(65U, 32U), /*!< SIM_M Clock Gate.*/
287 kCLOCK_Sim_main = CCM_TUPLE(66U, 16U), /*!< SIM_MAIN Clock Gate.*/
288 kCLOCK_Sim_s = CCM_TUPLE(67U, 32U), /*!< SIM_S Clock Gate.*/
289 kCLOCK_Sim_wakeup = CCM_TUPLE(68U, 32U), /*!< SIM_WAKEUP Clock Gate.*/
290
291 kCLOCK_Uart1 = CCM_TUPLE(73U, 94U), /*!< UART1 Clock Gate.*/
292 kCLOCK_Uart2 = CCM_TUPLE(74U, 95U), /*!< UART2 Clock Gate.*/
293 kCLOCK_Uart3 = CCM_TUPLE(75U, 96U), /*!< UART3 Clock Gate.*/
294 kCLOCK_Uart4 = CCM_TUPLE(76U, 97U), /*!< UART4 Clock Gate.*/
295
296 kCLOCK_Usdhc1 = CCM_TUPLE(81U, 88U), /*!< USDHC1 Clock Gate.*/
297 kCLOCK_Usdhc2 = CCM_TUPLE(82U, 89U), /*!< USDHC2 Clock Gate.*/
298 kCLOCK_Wdog1 = CCM_TUPLE(83U, 114U), /*!< WDOG1 Clock Gate.*/
299 kCLOCK_Wdog2 = CCM_TUPLE(84U, 114U), /*!< WDOG2 Clock Gate.*/
300 kCLOCK_Wdog3 = CCM_TUPLE(85U, 114U), /*!< WDOG3 Clock Gate.*/
301
302 kCLOCK_Asrc = CCM_TUPLE(88U, 33U), /*!< ASRC Clock Gate.*/
303 kCLOCK_Pdm = CCM_TUPLE(91U, 132U), /*!< PDM Clock Gate.*/
304 kCLOCK_Usdhc3 = CCM_TUPLE(94U, 121U), /*!< USDHC3 Clock Gate.*/
305 kCLOCK_Sdma3 = CCM_TUPLE(95U, 35U), /*!< SDMA3 Clock Gate.*/
306
307 kCLOCK_TempSensor = CCM_TUPLE(98U, 0xFFFF), /*!< TempSensor Clock Gate.*/
308
309} clock_ip_name_t;
310
311/*! @brief ccm root name used to get clock frequency. */
312typedef enum _clock_root_control
313{
314 kCLOCK_RootM7 = (uint32_t)(&(CCM)->ROOT[1].TARGET_ROOT), /*!< ARM Cortex-M7 Clock control name.*/
315 kCLOCK_RootAxi = (uint32_t)(&(CCM)->ROOT[16].TARGET_ROOT), /*!< AXI Clock control name.*/
316 kCLOCK_RootNoc = (uint32_t)(&(CCM)->ROOT[26].TARGET_ROOT), /*!< NOC Clock control name.*/
317 kCLOCK_RootAhb = (uint32_t)(&(CCM)->ROOT[32].TARGET_ROOT), /*!< AHB Clock control name.*/
318 kCLOCK_RootIpg = (uint32_t)(&(CCM)->ROOT[33].TARGET_ROOT), /*!< IPG Clock control name.*/
319 kCLOCK_RootAudioAhb = (uint32_t)(&(CCM)->ROOT[34].TARGET_ROOT), /*!< Audio AHB Clock control name.*/
320 kCLOCK_RootAudioIpg = (uint32_t)(&(CCM)->ROOT[35].TARGET_ROOT), /*!< Audio IPG Clock control name.*/
321 kCLOCK_RootDramAlt = (uint32_t)(&(CCM)->ROOT[64].TARGET_ROOT), /*!< DRAM ALT Clock control name.*/
322
323 kCLOCK_RootSai2 = (uint32_t)(&(CCM)->ROOT[76].TARGET_ROOT), /*!< SAI2 Clock control name.*/
324 kCLOCK_RootSai3 = (uint32_t)(&(CCM)->ROOT[77].TARGET_ROOT), /*!< SAI3 Clock control name.*/
325 kCLOCK_RootSai5 = (uint32_t)(&(CCM)->ROOT[79].TARGET_ROOT), /*!< SAI5 Clock control name.*/
326 kCLOCK_RootSai6 = (uint32_t)(&(CCM)->ROOT[80].TARGET_ROOT), /*!< SAI6 Clock control name.*/
327 kCLOCK_RootSai7 = (uint32_t)(&(CCM)->ROOT[134].TARGET_ROOT), /*!< SAI7 Clock control name.*/
328
329 kCLOCK_RootQspi = (uint32_t)(&(CCM)->ROOT[87].TARGET_ROOT), /*!< QSPI Clock control name.*/
330
331 kCLOCK_RootI2c1 = (uint32_t)(&(CCM)->ROOT[90].TARGET_ROOT), /*!< I2C1 Clock control name.*/
332 kCLOCK_RootI2c2 = (uint32_t)(&(CCM)->ROOT[91].TARGET_ROOT), /*!< I2C2 Clock control name.*/
333 kCLOCK_RootI2c3 = (uint32_t)(&(CCM)->ROOT[92].TARGET_ROOT), /*!< I2C3 Clock control name.*/
334 kCLOCK_RootI2c4 = (uint32_t)(&(CCM)->ROOT[93].TARGET_ROOT), /*!< I2C4 Clock control name.*/
335
336 kCLOCK_RootUart1 = (uint32_t)(&(CCM)->ROOT[94].TARGET_ROOT), /*!< UART1 Clock control name.*/
337 kCLOCK_RootUart2 = (uint32_t)(&(CCM)->ROOT[95].TARGET_ROOT), /*!< UART2 Clock control name.*/
338 kCLOCK_RootUart3 = (uint32_t)(&(CCM)->ROOT[96].TARGET_ROOT), /*!< UART3 Clock control name.*/
339 kCLOCK_RootUart4 = (uint32_t)(&(CCM)->ROOT[97].TARGET_ROOT), /*!< UART4 Clock control name.*/
340
341 kCLOCK_RootEcspi1 = (uint32_t)(&(CCM)->ROOT[101].TARGET_ROOT), /*!< ECSPI1 Clock control name.*/
342 kCLOCK_RootEcspi2 = (uint32_t)(&(CCM)->ROOT[102].TARGET_ROOT), /*!< ECSPI2 Clock control name.*/
343 kCLOCK_RootEcspi3 = (uint32_t)(&(CCM)->ROOT[131].TARGET_ROOT), /*!< ECSPI3 Clock control name.*/
344
345 kCLOCK_RootPwm1 = (uint32_t)(&(CCM)->ROOT[103].TARGET_ROOT), /*!< PWM1 Clock control name.*/
346 kCLOCK_RootPwm2 = (uint32_t)(&(CCM)->ROOT[104].TARGET_ROOT), /*!< PWM2 Clock control name.*/
347 kCLOCK_RootPwm3 = (uint32_t)(&(CCM)->ROOT[105].TARGET_ROOT), /*!< PWM3 Clock control name.*/
348 kCLOCK_RootPwm4 = (uint32_t)(&(CCM)->ROOT[106].TARGET_ROOT), /*!< PWM4 Clock control name.*/
349
350 kCLOCK_RootGpt1 = (uint32_t)(&(CCM)->ROOT[107].TARGET_ROOT), /*!< GPT1 Clock control name.*/
351 kCLOCK_RootGpt2 = (uint32_t)(&(CCM)->ROOT[108].TARGET_ROOT), /*!< GPT2 Clock control name.*/
352 kCLOCK_RootGpt3 = (uint32_t)(&(CCM)->ROOT[109].TARGET_ROOT), /*!< GPT3 Clock control name.*/
353 kCLOCK_RootGpt4 = (uint32_t)(&(CCM)->ROOT[110].TARGET_ROOT), /*!< GPT4 Clock control name.*/
354 kCLOCK_RootGpt5 = (uint32_t)(&(CCM)->ROOT[111].TARGET_ROOT), /*!< GPT5 Clock control name.*/
355 kCLOCK_RootGpt6 = (uint32_t)(&(CCM)->ROOT[112].TARGET_ROOT), /*!< GPT6 Clock control name.*/
356
357 kCLOCK_RootWdog = (uint32_t)(&(CCM)->ROOT[114].TARGET_ROOT), /*!< WDOG Clock control name.*/
358
359 kCLOCK_RootPdm = (uint32_t)(&(CCM)->ROOT[132].TARGET_ROOT), /*!< PDM Clock control name.*/
360
361} clock_root_control_t;
362
363/*! @brief Root clock select enumeration for ARM Cortex-M7 core. */
364typedef enum _clock_rootmux_m7_clk_sel
365{
366 kCLOCK_M7RootmuxOsc24M = 0U, /*!< ARM Cortex-M7 Clock from OSC 24M.*/
367 kCLOCK_M7RootmuxSysPll2Div5 = 1U, /*!< ARM Cortex-M7 Clock from SYSTEM PLL2 divided by 5.*/
368 kCLOCK_M7RootmuxSysPll2Div4 = 2U, /*!< ARM Cortex-M7 Clock from SYSTEM PLL2 divided by 4.*/
369 kCLOCK_M7RootmuxSysPll1Div3 = 3U, /*!< ARM Cortex-M7 Clock from SYSTEM PLL1 divided by 3.*/
370 kCLOCK_M7RootmuxSysPll1 = 4U, /*!< ARM Cortex-M7 Clock from SYSTEM PLL1.*/
371 kCLOCK_M7RootmuxAudioPll1 = 5U, /*!< ARM Cortex-M7 Clock from AUDIO PLL1.*/
372 kCLOCK_M7RootmuxVideoPll1 = 6U, /*!< ARM Cortex-M7 Clock from VIDEO PLL1.*/
373 kCLOCK_M7RootmuxSysPll3 = 7U, /*!< ARM Cortex-M7 Clock from SYSTEM PLL3.*/
374} clock_rootmux_m7_clk_sel_t;
375
376/*! @brief Root clock select enumeration for AXI bus. */
377typedef enum _clock_rootmux_axi_clk_sel
378{
379 kCLOCK_AxiRootmuxOsc24M = 0U, /*!< ARM AXI Clock from OSC 24M.*/
380 kCLOCK_AxiRootmuxSysPll2Div3 = 1U, /*!< ARM AXI Clock from SYSTEM PLL2 divided by 3.*/
381 kCLOCK_AxiRootmuxSysPll1 = 2U, /*!< ARM AXI Clock from SYSTEM PLL1.*/
382 kCLOCK_AxiRootmuxSysPll2Div4 = 3U, /*!< ARM AXI Clock from SYSTEM PLL2 divided by 4.*/
383 kCLOCK_AxiRootmuxSysPll2 = 4U, /*!< ARM AXI Clock from SYSTEM PLL2.*/
384 kCLOCK_AxiRootmuxAudioPll1 = 5U, /*!< ARM AXI Clock from AUDIO PLL1.*/
385 kCLOCK_AxiRootmuxVideoPll1 = 6U, /*!< ARM AXI Clock from VIDEO PLL1.*/
386 kCLOCK_AxiRootmuxSysPll1Div8 = 7U, /*!< ARM AXI Clock from SYSTEM PLL1 divided by 8.*/
387} clock_rootmux_axi_clk_sel_t;
388
389/*! @brief Root clock select enumeration for AHB bus. */
390typedef enum _clock_rootmux_ahb_clk_sel
391{
392 kCLOCK_AhbRootmuxOsc24M = 0U, /*!< ARM AHB Clock from OSC 24M.*/
393 kCLOCK_AhbRootmuxSysPll1Div6 = 1U, /*!< ARM AHB Clock from SYSTEM PLL1 divided by 6.*/
394 kCLOCK_AhbRootmuxSysPll1 = 2U, /*!< ARM AHB Clock from SYSTEM PLL1.*/
395 kCLOCK_AhbRootmuxSysPll1Div2 = 3U, /*!< ARM AHB Clock from SYSTEM PLL1 divided by 2.*/
396 kCLOCK_AhbRootmuxSysPll2Div8 = 4U, /*!< ARM AHB Clock from SYSTEM PLL2 divided by 8.*/
397 kCLOCK_AhbRootmuxSysPll3 = 5U, /*!< ARM AHB Clock from SYSTEM PLL3.*/
398 kCLOCK_AhbRootmuxAudioPll1 = 6U, /*!< ARM AHB Clock from AUDIO PLL1.*/
399 kCLOCK_AhbRootmuxVideoPll1 = 7U, /*!< ARM AHB Clock from VIDEO PLL1.*/
400} clock_rootmux_ahb_clk_sel_t;
401
402/*! @brief Root clock select enumeration for Audio AHB bus. */
403typedef enum _clock_rootmux_audio_ahb_clk_sel
404{
405 kCLOCK_AudioAhbRootmuxOsc24M = 0U, /*!< ARM Audio AHB Clock from OSC 24M.*/
406 kCLOCK_AudioAhbRootmuxSysPll2Div2 = 1U, /*!< ARM Audio AHB Clock from SYSTEM PLL2 divided by 2.*/
407 kCLOCK_AudioAhbRootmuxSysPll1 = 2U, /*!< ARM Audio AHB Clock from SYSTEM PLL1.*/
408 kCLOCK_AudioAhbRootmuxSysPll2 = 3U, /*!< ARM Audio AHB Clock from SYSTEM PLL2.*/
409 kCLOCK_AudioAhbRootmuxSysPll2Div6 = 4U, /*!< ARM Audio AHB Clock from SYSTEM PLL2 divided by 6.*/
410 kCLOCK_AudioAhbRootmuxSysPll3 = 5U, /*!< ARM Audio AHB Clock from SYSTEM PLL3.*/
411 kCLOCK_AudioAhbRootmuxAudioPll1 = 6U, /*!< ARM Audio AHB Clock from AUDIO PLL1.*/
412 kCLOCK_AudioAhbRootmuxVideoPll1 = 7U, /*!< ARM Audio AHB Clock from VIDEO PLL1.*/
413} clock_rootmux_audio_ahb_clk_sel_t;
414/*! @brief Root clock select enumeration for QSPI peripheral. */
415typedef enum _clock_rootmux_qspi_clk_sel
416{
417 kCLOCK_QspiRootmuxOsc24M = 0U, /*!< ARM QSPI Clock from OSC 24M.*/
418 kCLOCK_QspiRootmuxSysPll1Div2 = 1U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 2.*/
419 kCLOCK_QspiRootmuxSysPll2Div3 = 2U, /*!< ARM QSPI Clock from SYSTEM PLL2 divided by 3.*/
420 kCLOCK_QspiRootmuxSysPll2Div2 = 3U, /*!< ARM QSPI Clock from SYSTEM PLL2 divided by 2.*/
421 kCLOCK_QspiRootmuxAudioPll2 = 4U, /*!< ARM QSPI Clock from AUDIO PLL2.*/
422 kCLOCK_QspiRootmuxSysPll1Div3 = 5U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 3 */
423 kCLOCK_QspiRootmuxSysPll3 = 6, /*!< ARM QSPI Clock from SYSTEM PLL3.*/
424 kCLOCK_QspiRootmuxSysPll1Div8 = 7U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 8.*/
425} clock_rootmux_qspi_clk_sel_t;
426
427/*! @brief Root clock select enumeration for ECSPI peripheral. */
428typedef enum _clock_rootmux_ecspi_clk_sel
429{
430 kCLOCK_EcspiRootmuxOsc24M = 0U, /*!< ECSPI Clock from OSC 24M.*/
431 kCLOCK_EcspiRootmuxSysPll2Div5 = 1U, /*!< ECSPI Clock from SYSTEM PLL2 divided by 5.*/
432 kCLOCK_EcspiRootmuxSysPll1Div20 = 2U, /*!< ECSPI Clock from SYSTEM PLL1 divided by 20.*/
433 kCLOCK_EcspiRootmuxSysPll1Div5 = 3U, /*!< ECSPI Clock from SYSTEM PLL1 divided by 5.*/
434 kCLOCK_EcspiRootmuxSysPll1 = 4U, /*!< ECSPI Clock from SYSTEM PLL1.*/
435 kCLOCK_EcspiRootmuxSysPll3 = 5U, /*!< ECSPI Clock from SYSTEM PLL3.*/
436 kCLOCK_EcspiRootmuxSysPll2Div4 = 6U, /*!< ECSPI Clock from SYSTEM PLL2 divided by 4.*/
437 kCLOCK_EcspiRootmuxAudioPll2 = 7U, /*!< ECSPI Clock from AUDIO PLL2.*/
438} clock_rootmux_ecspi_clk_sel_t;
439
440/*! @brief Root clock select enumeration for I2C peripheral. */
441typedef enum _clock_rootmux_i2c_clk_sel
442{
443 kCLOCK_I2cRootmuxOsc24M = 0U, /*!< I2C Clock from OSC 24M.*/
444 kCLOCK_I2cRootmuxSysPll1Div5 = 1U, /*!< I2C Clock from SYSTEM PLL1 divided by 5.*/
445 kCLOCK_I2cRootmuxSysPll2Div20 = 2U, /*!< I2C Clock from SYSTEM PLL2 divided by 20.*/
446 kCLOCK_I2cRootmuxSysPll3 = 3U, /*!< I2C Clock from SYSTEM PLL3 .*/
447 kCLOCK_I2cRootmuxAudioPll1 = 4U, /*!< I2C Clock from AUDIO PLL1.*/
448 kCLOCK_I2cRootmuxVideoPll1 = 5U, /*!< I2C Clock from VIDEO PLL1.*/
449 kCLOCK_I2cRootmuxAudioPll2 = 6U, /*!< I2C Clock from AUDIO PLL2.*/
450 kCLOCK_I2cRootmuxSysPll1Div6 = 7U, /*!< I2C Clock from SYSTEM PLL1 divided by 6.*/
451} clock_rootmux_i2c_clk_sel_t;
452
453/*! @brief Root clock select enumeration for UART peripheral. */
454typedef enum _clock_rootmux_uart_clk_sel
455{
456 kCLOCK_UartRootmuxOsc24M = 0U, /*!< UART Clock from OSC 24M.*/
457 kCLOCK_UartRootmuxSysPll1Div10 = 1U, /*!< UART Clock from SYSTEM PLL1 divided by 10.*/
458 kCLOCK_UartRootmuxSysPll2Div5 = 2U, /*!< UART Clock from SYSTEM PLL2 divided by 5.*/
459 kCLOCK_UartRootmuxSysPll2Div10 = 3U, /*!< UART Clock from SYSTEM PLL2 divided by 10.*/
460 kCLOCK_UartRootmuxSysPll3 = 4U, /*!< UART Clock from SYSTEM PLL3.*/
461 kCLOCK_UartRootmuxExtClk2 = 5U, /*!< UART Clock from External Clock 2.*/
462 kCLOCK_UartRootmuxExtClk34 = 6U, /*!< UART Clock from External Clock 3, External Clock 4.*/
463 kCLOCK_UartRootmuxAudioPll2 = 7U, /*!< UART Clock from Audio PLL2.*/
464} clock_rootmux_uart_clk_sel_t;
465
466/*! @brief Root clock select enumeration for GPT peripheral. */
467typedef enum _clock_rootmux_gpt
468{
469 kCLOCK_GptRootmuxOsc24M = 0U, /*!< GPT Clock from OSC 24M.*/
470 kCLOCK_GptRootmuxSystemPll2Div10 = 1U, /*!< GPT Clock from SYSTEM PLL2 divided by 10.*/
471 kCLOCK_GptRootmuxSysPll1Div2 = 2U, /*!< GPT Clock from SYSTEM PLL1 divided by 2.*/
472 kCLOCK_GptRootmuxSysPll1Div20 = 3U, /*!< GPT Clock from SYSTEM PLL1 divided by 20.*/
473 kCLOCK_GptRootmuxVideoPll1 = 4U, /*!< GPT Clock from VIDEO PLL1.*/
474 kCLOCK_GptRootmuxSystemPll1Div10 = 5U, /*!< GPT Clock from SYSTEM PLL1 divided by 10.*/
475 kCLOCK_GptRootmuxAudioPll1 = 6U, /*!< GPT Clock from AUDIO PLL1.*/
476 kCLOCK_GptRootmuxExtClk123 = 7U, /*!< GPT Clock from External Clock1, External Clock2, External Clock3.*/
477} clock_rootmux_gpt_t;
478
479/*! @brief Root clock select enumeration for WDOG peripheral. */
480typedef enum _clock_rootmux_wdog_clk_sel
481{
482 kCLOCK_WdogRootmuxOsc24M = 0U, /*!< WDOG Clock from OSC 24M.*/
483 kCLOCK_WdogRootmuxSysPll1Div6 = 1U, /*!< WDOG Clock from SYSTEM PLL1 divided by 6.*/
484 kCLOCK_WdogRootmuxSysPll1Div5 = 2U, /*!< WDOG Clock from SYSTEM PLL1 divided by 5.*/
485 kCLOCK_WdogRootmuxVpuPll = 3U, /*!< WDOG Clock from VPU DLL.*/
486 kCLOCK_WdogRootmuxSystemPll2Div8 = 4U, /*!< WDOG Clock from SYSTEM PLL2 divided by 8.*/
487 kCLOCK_WdogRootmuxSystemPll3 = 5U, /*!< WDOG Clock from SYSTEM PLL3.*/
488 kCLOCK_WdogRootmuxSystemPll1Div10 = 6U, /*!< WDOG Clock from SYSTEM PLL1 divided by 10.*/
489 kCLOCK_WdogRootmuxSystemPll2Div6 = 7U, /*!< WDOG Clock from SYSTEM PLL2 divided by 6.*/
490} clock_rootmux_wdog_clk_sel_t;
491
492/*! @brief Root clock select enumeration for PWM peripheral. */
493typedef enum _clock_rootmux_pwm_clk_sel
494{
495 kCLOCK_PwmRootmuxOsc24M = 0U, /*!< PWM Clock from OSC 24M.*/
496 kCLOCK_PwmRootmuxSysPll2Div10 = 1U, /*!< PWM Clock from SYSTEM PLL2 divided by 10.*/
497 kCLOCK_PwmRootmuxSysPll1Div5 = 2U, /*!< PWM Clock from SYSTEM PLL1 divided by 5.*/
498 kCLOCK_PwmRootmuxSysPll1Div20 = 3U, /*!< PWM Clock from SYSTEM PLL1 divided by 20.*/
499 kCLOCK_PwmRootmuxSystemPll3 = 4U, /*!< PWM Clock from SYSTEM PLL3.*/
500 kCLOCK_PwmRootmuxExtClk12 = 5U, /*!< PWM Clock from External Clock1, External Clock2.*/
501 kCLOCK_PwmRootmuxSystemPll1Div10 = 6U, /*!< PWM Clock from SYSTEM PLL1 divided by 10.*/
502 kCLOCK_PwmRootmuxVideoPll1 = 7U, /*!< PWM Clock from VIDEO PLL1.*/
503} clock_rootmux_Pwm_clk_sel_t;
504
505/*! @brief Root clock select enumeration for SAI peripheral. */
506typedef enum _clock_rootmux_sai_clk_sel
507{
508 kCLOCK_SaiRootmuxOsc24M = 0U, /*!< SAI Clock from OSC 24M.*/
509 kCLOCK_SaiRootmuxAudioPll1 = 1U, /*!< SAI Clock from AUDIO PLL1.*/
510 kCLOCK_SaiRootmuxAudioPll2 = 2U, /*!< SAI Clock from AUDIO PLL2.*/
511 kCLOCK_SaiRootmuxVideoPll1 = 3U, /*!< SAI Clock from VIDEO PLL1.*/
512 kCLOCK_SaiRootmuxSysPll1Div6 = 4U, /*!< SAI Clock from SYSTEM PLL1 divided by 6.*/
513 kCLOCK_SaiRootmuxOsc26m = 5U, /*!< SAI Clock from OSC HDMI 26M.*/
514 kCLOCK_SaiRootmuxExtClk1 = 6U, /*!< SAI Clock from External Clock1, External Clock2, External Clock3.*/
515 kCLOCK_SaiRootmuxExtClk2 = 7U, /*!< SAI Clock from External Clock2, External Clock3, External Clock4.*/
516} clock_rootmux_sai_clk_sel_t;
517
518/*! @brief Root clock select enumeration for PDM peripheral. */
519typedef enum _clock_rootmux_pdm_clk_sel
520{
521 kCLOCK_PdmRootmuxOsc24M = 0U, /*!< GPT Clock from OSC 24M.*/
522 kCLOCK_PdmRootmuxSystemPll2 = 1U, /*!< GPT Clock from SYSTEM PLL2 divided by 10.*/
523 kCLOCK_PdmRootmuxAudioPll1 = 2U, /*!< GPT Clock from SYSTEM PLL1 divided by 2.*/
524 kCLOCK_PdmRootmuxSysPll1 = 3U, /*!< GPT Clock from SYSTEM PLL1 divided by 20.*/
525 kCLOCK_PdmRootmuxSysPll2 = 4U, /*!< GPT Clock from VIDEO PLL1.*/
526 kCLOCK_PdmRootmuxSysPll3 = 5U, /*!< GPT Clock from SYSTEM PLL1 divided by 10.*/
527 kCLOCK_PdmRootmuxExtClk3 = 6U, /*!< GPT Clock from AUDIO PLL1.*/
528 kCLOCK_PdmRootmuxAudioPll2 = 7U, /*!< GPT Clock from External Clock1, External Clock2, External Clock3.*/
529} clock_rootmux_pdm_clk_sel_t;
530
531/*! @brief Root clock select enumeration for NOC CLK. */
532typedef enum _clock_rootmux_noc_clk_sel
533{
534 kCLOCK_NocRootmuxOsc24M = 0U, /*!< NOC Clock from OSC 24M.*/
535 kCLOCK_NocRootmuxSysPll1 = 1U, /*!< NOC Clock from SYSTEM PLL1.*/
536 kCLOCK_NocRootmuxSysPll3 = 2U, /*!< NOC Clock from SYSTEM PLL3.*/
537 kCLOCK_NocRootmuxSysPll2 = 3U, /*!< NOC Clock from SYSTEM PLL2.*/
538 kCLOCK_NocRootmuxSysPll2Div2 = 4U, /*!< NOC Clock from SYSTEM PLL2 divided by 2.*/
539 kCLOCK_NocRootmuxAudioPll1 = 5U, /*!< NOC Clock from AUDIO PLL1.*/
540 kCLOCK_NocRootmuxVideoPll1 = 6U, /*!< NOC Clock from VIDEO PLL1.*/
541 kCLOCK_NocRootmuxAudioPll2 = 7U, /*!< NOC Clock from AUDIO PLL2.*/
542
543} clock_rootmux_noc_clk_sel_t;
544
545/*! @brief CCM PLL gate control. */
546typedef enum _clock_pll_gate
547{
548 kCLOCK_ArmPllGate = (uint32_t)(&(CCM)->PLL_CTRL[12].PLL_CTRL), /*!< ARM PLL Gate.*/
549
550 kCLOCK_GpuPllGate = (uint32_t)(&(CCM)->PLL_CTRL[13].PLL_CTRL), /*!< GPU PLL Gate.*/
551 kCLOCK_VpuPllGate = (uint32_t)(&(CCM)->PLL_CTRL[14].PLL_CTRL), /*!< VPU PLL Gate.*/
552 kCLOCK_DramPllGate = (uint32_t)(&(CCM)->PLL_CTRL[15].PLL_CTRL), /*!< DRAM PLL1 Gate.*/
553
554 kCLOCK_SysPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[16].PLL_CTRL), /*!< SYSTEM PLL1 Gate.*/
555 kCLOCK_SysPll1Div2Gate = (uint32_t)(&(CCM)->PLL_CTRL[17].PLL_CTRL), /*!< SYSTEM PLL1 Div2 Gate.*/
556 kCLOCK_SysPll1Div3Gate = (uint32_t)(&(CCM)->PLL_CTRL[18].PLL_CTRL), /*!< SYSTEM PLL1 Div3 Gate.*/
557 kCLOCK_SysPll1Div4Gate = (uint32_t)(&(CCM)->PLL_CTRL[19].PLL_CTRL), /*!< SYSTEM PLL1 Div4 Gate.*/
558 kCLOCK_SysPll1Div5Gate = (uint32_t)(&(CCM)->PLL_CTRL[20].PLL_CTRL), /*!< SYSTEM PLL1 Div5 Gate.*/
559 kCLOCK_SysPll1Div6Gate = (uint32_t)(&(CCM)->PLL_CTRL[21].PLL_CTRL), /*!< SYSTEM PLL1 Div6 Gate.*/
560 kCLOCK_SysPll1Div8Gate = (uint32_t)(&(CCM)->PLL_CTRL[22].PLL_CTRL), /*!< SYSTEM PLL1 Div8 Gate.*/
561 kCLOCK_SysPll1Div10Gate = (uint32_t)(&(CCM)->PLL_CTRL[23].PLL_CTRL), /*!< SYSTEM PLL1 Div10 Gate.*/
562 kCLOCK_SysPll1Div20Gate = (uint32_t)(&(CCM)->PLL_CTRL[24].PLL_CTRL), /*!< SYSTEM PLL1 Div20 Gate.*/
563
564 kCLOCK_SysPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[25].PLL_CTRL), /*!< SYSTEM PLL2 Gate.*/
565 kCLOCK_SysPll2Div2Gate = (uint32_t)(&(CCM)->PLL_CTRL[26].PLL_CTRL), /*!< SYSTEM PLL2 Div2 Gate.*/
566 kCLOCK_SysPll2Div3Gate = (uint32_t)(&(CCM)->PLL_CTRL[27].PLL_CTRL), /*!< SYSTEM PLL2 Div3 Gate.*/
567 kCLOCK_SysPll2Div4Gate = (uint32_t)(&(CCM)->PLL_CTRL[28].PLL_CTRL), /*!< SYSTEM PLL2 Div4 Gate.*/
568 kCLOCK_SysPll2Div5Gate = (uint32_t)(&(CCM)->PLL_CTRL[29].PLL_CTRL), /*!< SYSTEM PLL2 Div5 Gate.*/
569 kCLOCK_SysPll2Div6Gate = (uint32_t)(&(CCM)->PLL_CTRL[30].PLL_CTRL), /*!< SYSTEM PLL2 Div6 Gate.*/
570 kCLOCK_SysPll2Div8Gate = (uint32_t)(&(CCM)->PLL_CTRL[31].PLL_CTRL), /*!< SYSTEM PLL2 Div8 Gate.*/
571 kCLOCK_SysPll2Div10Gate = (uint32_t)(&(CCM)->PLL_CTRL[32].PLL_CTRL), /*!< SYSTEM PLL2 Div10 Gate.*/
572 kCLOCK_SysPll2Div20Gate = (uint32_t)(&(CCM)->PLL_CTRL[33].PLL_CTRL), /*!< SYSTEM PLL2 Div20 Gate.*/
573
574 kCLOCK_SysPll3Gate = (uint32_t)(&(CCM)->PLL_CTRL[34].PLL_CTRL), /*!< SYSTEM PLL3 Gate.*/
575
576 kCLOCK_AudioPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[35].PLL_CTRL), /*!< AUDIO PLL1 Gate.*/
577 kCLOCK_AudioPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[36].PLL_CTRL), /*!< AUDIO PLL2 Gate.*/
578 kCLOCK_VideoPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[37].PLL_CTRL), /*!< VIDEO PLL1 Gate.*/
579 kCLOCK_VideoPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[38].PLL_CTRL), /*!< VIDEO PLL2 Gate.*/
580} clock_pll_gate_t;
581
582/*! @brief CCM gate control value. */
583typedef enum _clock_gate_value
584{
585 kCLOCK_ClockNotNeeded = 0x0U, /*!< Clock always disabled.*/
586 kCLOCK_ClockNeededRun = 0x1111U, /*!< Clock enabled when CPU is running.*/
587 kCLOCK_ClockNeededRunWait = 0x2222U, /*!< Clock enabled when CPU is running or in WAIT mode.*/
588 kCLOCK_ClockNeededAll = 0x3333U, /*!< Clock always enabled.*/
589} clock_gate_value_t;
590
591/*!
592 * @brief PLL control names for PLL bypass.
593 *
594 * These constants define the PLL control names for PLL bypass.\n
595 * - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
596 * - 16:20: bypass bit shift.
597 */
598typedef enum _clock_pll_bypass_ctrl
599{
600 kCLOCK_AudioPll1BypassCtrl =
601 CCM_ANALOG_TUPLE(AUDIO_PLL1_GEN_CTRL_OFFSET,
602 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Audio PLL1 bypass Control.*/
603
604 kCLOCK_AudioPll2BypassCtrl =
605 CCM_ANALOG_TUPLE(AUDIO_PLL2_GEN_CTRL_OFFSET,
606 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Audio PLL2 bypass Control.*/
607
608 kCLOCK_VideoPll1BypassCtrl =
609 CCM_ANALOG_TUPLE(VIDEO_PLL1_GEN_CTRL_OFFSET,
610 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Video Pll1 bypass Control.*/
611
612 kCLOCK_DramPllInternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
613 DRAM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM DRAM PLL bypass Control.*/
614
615 kCLOCK_ArmPllPwrBypassCtrl = CCM_ANALOG_TUPLE(
616 ARM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Arm PLL bypass Control.*/
617
618 kCLOCK_SysPll1InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
619 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM System PLL1 bypass Control.*/
620
621 kCLOCK_SysPll2InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
622 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM System PLL2 bypass Control.*/
623
624 kCLOCK_SysPll3InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
625 SYS_PLL3_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM System PLL3 bypass Control.*/
626} clock_pll_bypass_ctrl_t;
627
628/*!
629 * @brief PLL clock names for clock enable/disable settings.
630 *
631 * These constants define the PLL clock names for PLL clock enable/disable operations.\n
632 * - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
633 * - 16:20: Clock enable bit shift.
634 */
635typedef enum _ccm_analog_pll_clke
636{
637 kCLOCK_AudioPll1Clke = CCM_ANALOG_TUPLE(AUDIO_PLL1_GEN_CTRL_OFFSET,
638 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Audio pll1 clke */
639 kCLOCK_AudioPll2Clke = CCM_ANALOG_TUPLE(AUDIO_PLL2_GEN_CTRL_OFFSET,
640 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Audio pll2 clke */
641 kCLOCK_VideoPll1Clke = CCM_ANALOG_TUPLE(VIDEO_PLL1_GEN_CTRL_OFFSET,
642 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Video pll1 clke */
643 kCLOCK_DramPllClke =
644 CCM_ANALOG_TUPLE(DRAM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Dram pll clke */
645
646 kCLOCK_ArmPllClke =
647 CCM_ANALOG_TUPLE(ARM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Arm pll clke */
648
649 kCLOCK_SystemPll1Clke = CCM_ANALOG_TUPLE(SYS_PLL1_GEN_CTRL_OFFSET,
650 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_SHIFT), /*!< System pll1 clke */
651 kCLOCK_SystemPll1Div2Clke = CCM_ANALOG_TUPLE(
652 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_SHIFT), /*!< System pll1 Div2 clke */
653 kCLOCK_SystemPll1Div3Clke = CCM_ANALOG_TUPLE(
654 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_SHIFT), /*!< System pll1 Div3 clke */
655 kCLOCK_SystemPll1Div4Clke = CCM_ANALOG_TUPLE(
656 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_SHIFT), /*!< System pll1 Div4 clke */
657 kCLOCK_SystemPll1Div5Clke = CCM_ANALOG_TUPLE(
658 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_SHIFT), /*!< System pll1 Div5 clke */
659 kCLOCK_SystemPll1Div6Clke = CCM_ANALOG_TUPLE(
660 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_SHIFT), /*!< System pll1 Div6 clke */
661 kCLOCK_SystemPll1Div8Clke = CCM_ANALOG_TUPLE(
662 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_SHIFT), /*!< System pll1 Div8 clke */
663 kCLOCK_SystemPll1Div10Clke = CCM_ANALOG_TUPLE(
664 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_SHIFT), /*!< System pll1 Div10 clke */
665 kCLOCK_SystemPll1Div20Clke = CCM_ANALOG_TUPLE(
666 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_SHIFT), /*!< System pll1 Div20 clke */
667
668 kCLOCK_SystemPll2Clke = CCM_ANALOG_TUPLE(SYS_PLL2_GEN_CTRL_OFFSET,
669 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_SHIFT), /*!< System pll2 clke */
670 kCLOCK_SystemPll2Div2Clke = CCM_ANALOG_TUPLE(
671 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_SHIFT), /*!< System pll2 Div2 clke */
672 kCLOCK_SystemPll2Div3Clke = CCM_ANALOG_TUPLE(
673 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_SHIFT), /*!< System pll2 Div3 clke */
674 kCLOCK_SystemPll2Div4Clke = CCM_ANALOG_TUPLE(
675 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_SHIFT), /*!< System pll2 Div4 clke */
676 kCLOCK_SystemPll2Div5Clke = CCM_ANALOG_TUPLE(
677 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_SHIFT), /*!< System pll2 Div5 clke */
678 kCLOCK_SystemPll2Div6Clke = CCM_ANALOG_TUPLE(
679 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_SHIFT), /*!< System pll2 Div6 clke */
680 kCLOCK_SystemPll2Div8Clke = CCM_ANALOG_TUPLE(
681 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_SHIFT), /*!< System pll2 Div8 clke */
682 kCLOCK_SystemPll2Div10Clke = CCM_ANALOG_TUPLE(
683 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_SHIFT), /*!< System pll2 Div10 clke */
684 kCLOCK_SystemPll2Div20Clke = CCM_ANALOG_TUPLE(
685 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_SHIFT), /*!< System pll2 Div20 clke */
686
687 kCLOCK_SystemPll3Clke = CCM_ANALOG_TUPLE(SYS_PLL3_GEN_CTRL_OFFSET,
688 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_SHIFT), /*!< System pll3 clke */
689} clock_pll_clke_t;
690
691/*!
692 * @brief ANALOG Power down override control.
693 */
694typedef enum _clock_pll_ctrl
695{
696 /* Fractional PLL frequency */
697 kCLOCK_AudioPll1Ctrl = CCM_ANALOG_TUPLE(AUDIO_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT),
698 kCLOCK_AudioPll2Ctrl = CCM_ANALOG_TUPLE(AUDIO_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_SHIFT),
699 kCLOCK_VideoPll1Ctrl = CCM_ANALOG_TUPLE(VIDEO_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_SHIFT),
700 kCLOCK_DramPllCtrl = CCM_ANALOG_TUPLE(DRAM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_SHIFT),
701 /* Integer PLL frequency */
702 kCLOCK_ArmPllCtrl = CCM_ANALOG_TUPLE(ARM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_SHIFT),
703 kCLOCK_SystemPll1Ctrl = CCM_ANALOG_TUPLE(SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT),
704 kCLOCK_SystemPll2Ctrl = CCM_ANALOG_TUPLE(SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_SHIFT),
705 kCLOCK_SystemPll3Ctrl = CCM_ANALOG_TUPLE(SYS_PLL3_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_SHIFT),
706} clock_pll_ctrl_t;
707
708/*! @brief PLL reference clock select. */
709enum
710{
711 kANALOG_PllRefOsc24M = 0U, /*!< reference OSC 24M */
712 kANALOG_PllPadClk = 1U, /*!< reference PAD CLK */
713};
714
715/*!
716 * @brief Fractional-N PLL configuration.
717 * Note: all the dividers in this configuration structure are the actually divider, software will map it to register
718 * value
719 */
720typedef struct _ccm_analog_frac_pll_config
721{
722 uint8_t refSel; /*!< pll reference clock sel */
723
724 uint32_t mainDiv; /*!< Value of the 10-bit programmable main-divider, range must be 64~1023 */
725
726 uint32_t dsm; /*!< Value of 16-bit DSM */
727
728 uint8_t preDiv; /*!< Value of the 6-bit programmable pre-divider, range must be 1~63 */
729
730 uint8_t postDiv; /*!< Value of the 3-bit programmable Scaler, range must be 0~6 */
731} ccm_analog_frac_pll_config_t;
732
733/*!
734 * @brief Integer PLL configuration.
735 * Note: all the dividers in this configuration structure are the actually divider, software will map it to register
736 * value
737 */
738typedef struct _ccm_analog_integer_pll_config
739{
740 uint8_t refSel; /*!< pll reference clock sel */
741
742 uint32_t mainDiv; /*!< Value of the 10-bit programmable main-divider, range must be 64~1023 */
743
744 uint8_t preDiv; /*!< Value of the 6-bit programmable pre-divider, range must be 1~63 */
745
746 uint8_t postDiv; /*!< Value of the 3-bit programmable Scaler, range must be 0~6 */
747
748} ccm_analog_integer_pll_config_t;
749
750/*******************************************************************************
751 * API
752 ******************************************************************************/
753
754#if defined(__cplusplus)
755extern "C" {
756#endif
757
758/*!
759 * @name CCM Root Clock Setting
760 * @{
761 */
762
763/*!
764 * @brief Set clock root mux.
765 * User maybe need to set more than one mux ROOT according to the clock tree
766 * description in the reference manual.
767 *
768 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration).
769 * @param mux Root mux value, refer to _ccm_rootmux_xxx enumeration.
770 */
771static inline void CLOCK_SetRootMux(clock_root_control_t rootClk, uint32_t mux)
772{
773 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux);
774}
775
776/*!
777 * @brief Get clock root mux.
778 * In order to get the clock source of root, user maybe need to get more than one
779 * ROOT's mux value to obtain the final clock source of root.
780 *
781 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration).
782 * @return Root mux value, refer to _ccm_rootmux_xxx enumeration.
783 */
784static inline uint32_t CLOCK_GetRootMux(clock_root_control_t rootClk)
785{
786 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT;
787}
788
789/*!
790 * @brief Enable clock root
791 *
792 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration)
793 */
794static inline void CLOCK_EnableRoot(clock_root_control_t rootClk)
795{
796 CCM_REG_SET(rootClk) = CCM_TARGET_ROOT_SET_ENABLE_MASK;
797}
798
799/*!
800 * @brief Disable clock root
801 *
802 * @param rootClk Root control (see @ref clock_root_control_t enumeration)
803 */
804static inline void CLOCK_DisableRoot(clock_root_control_t rootClk)
805{
806 CCM_REG_CLR(rootClk) = CCM_TARGET_ROOT_CLR_ENABLE_MASK;
807}
808
809/*!
810 * @brief Check whether clock root is enabled
811 *
812 * @param rootClk Root control (see @ref clock_root_control_t enumeration)
813 * @return CCM root enabled or not.
814 * - true: Clock root is enabled.
815 * - false: Clock root is disabled.
816 */
817static inline bool CLOCK_IsRootEnabled(clock_root_control_t rootClk)
818{
819 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK);
820}
821
822/*!
823 * @brief Update clock root in one step, for dynamical clock switching
824 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
825 *
826 * @param ccmRootClk Root control (see @ref clock_root_control_t enumeration)
827 * @param mux Root mux value, refer to _ccm_rootmux_xxx enumeration
828 * @param pre Pre divider value (0-7, divider=n+1)
829 * @param post Post divider value (0-63, divider=n+1)
830 */
831void CLOCK_UpdateRoot(clock_root_control_t ccmRootClk, uint32_t mux, uint32_t pre, uint32_t post);
832
833/*!
834 * @brief Set root clock divider
835 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
836 *
837 * @param ccmRootClk Root control (see @ref clock_root_control_t enumeration)
838 * @param pre Pre divider value (1-8)
839 * @param post Post divider value (1-64)
840 */
841void CLOCK_SetRootDivider(clock_root_control_t ccmRootClk, uint32_t pre, uint32_t post);
842
843/*!
844 * @brief Get clock root PRE_PODF.
845 * In order to get the clock source of root, user maybe need to get more than one
846 * ROOT's mux value to obtain the final clock source of root.
847 *
848 * @param rootClk Root clock name (see @ref clock_root_control_t enumeration).
849 * @return Root Pre divider value.
850 */
851static inline uint32_t CLOCK_GetRootPreDivider(clock_root_control_t rootClk)
852{
853 return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U;
854}
855
856/*!
857 * @brief Get clock root POST_PODF.
858 * In order to get the clock source of root, user maybe need to get more than one
859 * ROOT's mux value to obtain the final clock source of root.
860 *
861 * @param rootClk Root clock name (see @ref clock_root_control_t enumeration).
862 * @return Root Post divider value.
863 */
864static inline uint32_t CLOCK_GetRootPostDivider(clock_root_control_t rootClk)
865{
866 return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + 1U;
867}
868
869/*!
870 * @name CCM Gate Control
871 * @{
872 */
873
874/*!
875 * lockrief Set PLL or CCGR gate control
876 *
877 * @param ccmGate Gate control (see @ref clock_pll_gate_t and @ref clock_ip_name_t enumeration)
878 * @param control Gate control value (see @ref clock_gate_value_t)
879 */
880static inline void CLOCK_ControlGate(uint32_t ccmGate, clock_gate_value_t control)
881{
882 CCM_REG(ccmGate) = (uint32_t)control;
883}
884
885/*!
886 * @brief Enable CCGR clock gate and root clock gate for each module
887 * User should set specific gate for each module according to the description
888 * of the table of system clocks, gating and override in CCM chapter of
889 * reference manual. Take care of that one module may need to set more than
890 * one clock gate.
891 *
892 * @param ccmGate Gate control for each module (see @ref clock_ip_name_t enumeration).
893 */
894void CLOCK_EnableClock(clock_ip_name_t ccmGate);
895
896/*!
897 * @brief Disable CCGR clock gate for the each module
898 * User should set specific gate for each module according to the description
899 * of the table of system clocks, gating and override in CCM chapter of
900 * reference manual. Take care of that one module may need to set more than
901 * one clock gate.
902 *
903 * @param ccmGate Gate control for each module (see @ref clock_ip_name_t enumeration).
904 */
905void CLOCK_DisableClock(clock_ip_name_t ccmGate);
906
907/*!
908 * @name CCM Analog PLL Operatoin Functions
909 * @{
910 */
911
912/*!
913 * @brief Power up PLL
914 *
915 * @param base CCM_ANALOG base pointer.
916 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
917 */
918static inline void CLOCK_PowerUpPll(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
919{
920 CCM_ANALOG_TUPLE_REG(base, pllControl) |= (1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
921}
922
923/*!
924 * @brief Power down PLL
925 *
926 * @param base CCM_ANALOG base pointer.
927 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
928 */
929static inline void CLOCK_PowerDownPll(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
930{
931 CCM_ANALOG_TUPLE_REG(base, pllControl) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
932}
933
934/*!
935 * @brief PLL bypass setting
936 *
937 * @param base CCM_ANALOG base pointer.
938 * @param pllControl PLL control name, refer to ccm_analog_pll_control_t enumeration
939 * @param bypass Bypass the PLL.
940 * - true: Bypass the PLL.
941 * - false: Do not bypass the PLL.
942 */
943static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl, bool bypass)
944{
945 if (bypass)
946 {
947 CCM_ANALOG_TUPLE_REG(base, pllControl) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl);
948 }
949 else
950 {
951 CCM_ANALOG_TUPLE_REG(base, pllControl) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
952 }
953}
954
955/*!
956 * @brief Check if PLL is bypassed
957 *
958 * @param base CCM_ANALOG base pointer.
959 * @param pllControl PLL control name, refer to ccm_analog_pll_control_t enumeration
960 * @return PLL bypass status.
961 * - true: The PLL is bypassed.
962 * - false: The PLL is not bypassed.
963 */
964static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl)
965{
966 return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl)));
967}
968
969/*!
970 * @brief Check if PLL clock is locked
971 *
972 * @param base CCM_ANALOG base pointer.
973 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
974 * @return PLL lock status.
975 * - true: The PLL clock is locked.
976 * - false: The PLL clock is not locked.
977 */
978static inline bool CLOCK_IsPllLocked(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
979{
980 return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_MASK);
981}
982
983/*!
984 * @brief Enable PLL clock
985 *
986 * @param base CCM_ANALOG base pointer.
987 * @param pllClock PLL clock name, refer to ccm_analog_pll_clock_t enumeration
988 */
989static inline void CLOCK_EnableAnalogClock(CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)
990{
991 CCM_ANALOG_TUPLE_REG(base, pllClock) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllClock);
992}
993
994/*!
995 * @brief Disable PLL clock
996 *
997 * @param base CCM_ANALOG base pointer.
998 * @param pllClock PLL clock name, refer to ccm_analog_pll_clock_t enumeration
999 */
1000static inline void CLOCK_DisableAnalogClock(CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)
1001{
1002 CCM_ANALOG_TUPLE_REG(base, pllClock) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllClock));
1003}
1004
1005/*!
1006 * @brief Override PLL clock output enable
1007 *
1008 * @param base CCM_ANALOG base pointer.
1009 * @param ovClock PLL clock name (see @ref clock_pll_clke_t enumeration)
1010 * @param override Override the PLL.
1011 * - true: Override the PLL clke, CCM will handle it.
1012 * - false: Do not override the PLL clke.
1013 */
1014static inline void CLOCK_OverridePllClke(CCM_ANALOG_Type *base, clock_pll_clke_t ovClock, bool override)
1015{
1016 if (override)
1017 {
1018 CCM_ANALOG_TUPLE_REG(base, ovClock) |= 1UL << (CCM_ANALOG_TUPLE_SHIFT(ovClock) - 1UL);
1019 }
1020 else
1021 {
1022 CCM_ANALOG_TUPLE_REG(base, ovClock) &= ~(1UL << (CCM_ANALOG_TUPLE_SHIFT(ovClock) - 1UL));
1023 }
1024}
1025
1026/*!
1027 * @brief Override PLL power down
1028 *
1029 * @param base CCM_ANALOG base pointer.
1030 * @param pdClock PLL clock name (see @ref clock_pll_ctrl_t enumeration)
1031 * @param override Override the PLL.
1032 * - true: Override the PLL clke, CCM will handle it.
1033 * - false: Do not override the PLL clke.
1034 */
1035static inline void CLOCK_OverridePllPd(CCM_ANALOG_Type *base, clock_pll_ctrl_t pdClock, bool override)
1036{
1037 if (override)
1038 {
1039 CCM_ANALOG_TUPLE_REG(base, pdClock) |= 1UL << (CCM_ANALOG_TUPLE_SHIFT(pdClock) - 1UL);
1040 }
1041 else
1042 {
1043 CCM_ANALOG_TUPLE_REG(base, pdClock) &= ~(1UL << (CCM_ANALOG_TUPLE_SHIFT(pdClock) - 1UL));
1044 }
1045}
1046
1047/*!
1048 * @brief Initializes the ANALOG ARM PLL.
1049 *
1050 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1051 *
1052 * @note This function can't detect whether the Arm PLL has been enabled and
1053 * used by some IPs.
1054 */
1055void CLOCK_InitArmPll(const ccm_analog_integer_pll_config_t *config);
1056
1057/*!
1058 * @brief De-initialize the ARM PLL.
1059 */
1060void CLOCK_DeinitArmPll(void);
1061
1062/*!
1063 * @brief Initializes the ANALOG SYS PLL1.
1064 *
1065 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1066 *
1067 * @note This function can't detect whether the SYS PLL has been enabled and
1068 * used by some IPs.
1069 */
1070void CLOCK_InitSysPll1(const ccm_analog_integer_pll_config_t *config);
1071
1072/*!
1073 * @brief De-initialize the System PLL1.
1074 */
1075void CLOCK_DeinitSysPll1(void);
1076
1077/*!
1078 * @brief Initializes the ANALOG SYS PLL2.
1079 *
1080 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1081 *
1082 * @note This function can't detect whether the SYS PLL has been enabled and
1083 * used by some IPs.
1084 */
1085void CLOCK_InitSysPll2(const ccm_analog_integer_pll_config_t *config);
1086
1087/*!
1088 * @brief De-initialize the System PLL2.
1089 */
1090void CLOCK_DeinitSysPll2(void);
1091
1092/*!
1093 * @brief Initializes the ANALOG SYS PLL3.
1094 *
1095 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1096 *
1097 * @note This function can't detect whether the SYS PLL has been enabled and
1098 * used by some IPs.
1099 */
1100void CLOCK_InitSysPll3(const ccm_analog_integer_pll_config_t *config);
1101
1102/*!
1103 * @brief De-initialize the System PLL3.
1104 */
1105void CLOCK_DeinitSysPll3(void);
1106
1107/*!
1108 * @brief Initializes the ANALOG AUDIO PLL1.
1109 *
1110 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1111 *
1112 * @note This function can't detect whether the AUDIO PLL has been enabled and
1113 * used by some IPs.
1114 */
1115void CLOCK_InitAudioPll1(const ccm_analog_frac_pll_config_t *config);
1116
1117/*!
1118 * @brief De-initialize the Audio PLL1.
1119 */
1120void CLOCK_DeinitAudioPll1(void);
1121
1122/*!
1123 * @brief Initializes the ANALOG AUDIO PLL2.
1124 *
1125 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1126 *
1127 * @note This function can't detect whether the AUDIO PLL has been enabled and
1128 * used by some IPs.
1129 */
1130void CLOCK_InitAudioPll2(const ccm_analog_frac_pll_config_t *config);
1131
1132/*!
1133 * @brief De-initialize the Audio PLL2.
1134 */
1135void CLOCK_DeinitAudioPll2(void);
1136
1137/*!
1138 * @brief Initializes the ANALOG VIDEO PLL1.
1139 *
1140 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1141 *
1142 */
1143void CLOCK_InitVideoPll1(const ccm_analog_frac_pll_config_t *config);
1144
1145/*!
1146 * @brief De-initialize the Video PLL1.
1147 */
1148void CLOCK_DeinitVideoPll1(void);
1149
1150/*!
1151 * @brief Initializes the ANALOG Integer PLL.
1152 *
1153 * @param base CCM ANALOG base address
1154 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1155 * @param type integer pll type
1156 *
1157 */
1158void CLOCK_InitIntegerPll(CCM_ANALOG_Type *base, const ccm_analog_integer_pll_config_t *config, clock_pll_ctrl_t type);
1159
1160/*!
1161 * @brief Get the ANALOG Integer PLL clock frequency.
1162 *
1163 * @param base CCM ANALOG base address.
1164 * @param type integer pll type
1165 * @param refClkFreq pll reference clock frequency
1166 * @param pll1Bypass pll1 bypass flag
1167 *
1168 * @return Clock frequency
1169 */
1170uint32_t CLOCK_GetIntegerPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq, bool pll1Bypass);
1171
1172/*!
1173 * @brief Initializes the ANALOG Fractional PLL.
1174 *
1175 * @param base CCM ANALOG base address.
1176 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1177 * @param type fractional pll type.
1178 *
1179 */
1180void CLOCK_InitFracPll(CCM_ANALOG_Type *base, const ccm_analog_frac_pll_config_t *config, clock_pll_ctrl_t type);
1181
1182/*!
1183 * @brief Gets the ANALOG Fractional PLL clock frequency.
1184 *
1185 * @param base CCM_ANALOG base pointer.
1186 * @param type Fractional pll type.
1187 * @param refClkFreq Pll reference clock frequency
1188 *
1189 * @return Clock frequency
1190 */
1191uint32_t CLOCK_GetFracPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq);
1192
1193/*!
1194 * @brief Gets PLL clock frequency.
1195 *
1196 * @param pll Fractional pll type.
1197
1198 * @return Clock frequency
1199 */
1200uint32_t CLOCK_GetPllFreq(clock_pll_ctrl_t pll);
1201
1202/*!
1203 * @brief Gets PLL reference clock frequency.
1204 *
1205 * @param ctrl Fractional pll type.
1206
1207 * @return Clock frequency
1208 */
1209uint32_t CLOCK_GetPllRefClkFreq(clock_pll_ctrl_t ctrl);
1210
1211/*!
1212 * @name CCM Get frequency
1213 * @{
1214 */
1215
1216/*!
1217 * @brief Gets the clock frequency for a specific clock name.
1218 *
1219 * This function checks the current clock configurations and then calculates
1220 * the clock frequency for a specific clock name defined in clock_name_t.
1221 *
1222 * @param clockName Clock names defined in clock_name_t
1223 * @return Clock frequency value in hertz
1224 */
1225uint32_t CLOCK_GetFreq(clock_name_t clockName);
1226
1227/*!
1228 * @brief Get the CCM Cortex M7 core frequency.
1229 *
1230 * @return Clock frequency; If the clock is invalid, returns 0.
1231 */
1232uint32_t CLOCK_GetCoreM7Freq(void);
1233
1234/*!
1235 * @brief Get the CCM Axi bus frequency.
1236 *
1237 * @return Clock frequency; If the clock is invalid, returns 0.
1238 */
1239uint32_t CLOCK_GetAxiFreq(void);
1240
1241/*!
1242 * @brief Get the CCM Ahb bus frequency.
1243 *
1244 * @return Clock frequency; If the clock is invalid, returns 0.
1245 */
1246uint32_t CLOCK_GetAhbFreq(void);
1247
1248/* @} */
1249
1250#if defined(__cplusplus)
1251}
1252#endif
1253/* @} */
1254#endif
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/drivers/fsl_iomuxc.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/drivers/fsl_iomuxc.h
new file mode 100644
index 000000000..438e21e11
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/drivers/fsl_iomuxc.h
@@ -0,0 +1,746 @@
1/*
2 * Copyright 2019-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7#ifndef _FSL_IOMUXC_H_
8#define _FSL_IOMUXC_H_
9
10#include "fsl_common.h"
11
12/*!
13 * @addtogroup iomuxc_driver
14 * @{
15 */
16
17/*! @file */
18
19/*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22/* Component ID definition, used by tools. */
23#ifndef FSL_COMPONENT_ID
24#define FSL_COMPONENT_ID "platform.drivers.iomuxc"
25#endif
26
27/*! @name Driver version */
28/*@{*/
29/*! @brief IOMUXC driver version 2.0.1. */
30#define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
31/*@}*/
32
33/*!
34 * @name Pin function ID
35 * The pin function ID is a tuple of \<muxRegister muxMode inputRegister inputDaisy configRegister\>
36 *
37 * @{
38 */
39#define IOMUXC_BOOT_MODE0_SRC_BOOT_MODE0 0x00000000, 0x0, 0x00000000, 0x0, 0x30330254
40#define IOMUXC_BOOT_MODE1_SRC_BOOT_MODE1 0x00000000, 0x0, 0x00000000, 0x0, 0x30330258
41#define IOMUXC_BOOT_MODE2_SRC_BOOT_MODE2 0x30330020, 0x0, 0x00000000, 0x0, 0x3033025C
42#define IOMUXC_BOOT_MODE2_I2C1_SCL 0x30330020, 0x1, 0x3033055C, 0x3, 0x3033025C
43#define IOMUXC_BOOT_MODE3_SRC_BOOT_MODE3 0x30330024, 0x0, 0x00000000, 0x0, 0x30330260
44#define IOMUXC_BOOT_MODE3_I2C1_SDA 0x30330024, 0x1, 0x3033056C, 0x3, 0x30330260
45#define IOMUXC_JTAG_MOD_JTAG_MODE 0x00000000, 0x0, 0x00000000, 0x0, 0x30330264
46#define IOMUXC_JTAG_TDI_JTAG_TDI 0x00000000, 0x0, 0x00000000, 0x0, 0x30330268
47#define IOMUXC_JTAG_TMS_JTAG_TMS 0x00000000, 0x0, 0x00000000, 0x0, 0x3033026C
48#define IOMUXC_JTAG_TCK_JTAG_TCK 0x00000000, 0x0, 0x00000000, 0x0, 0x30330270
49#define IOMUXC_JTAG_TDO_JTAG_TDO 0x00000000, 0x0, 0x00000000, 0x0, 0x30330274
50#define IOMUXC_RTC_XTALI_SNVS_RTC 0x00000000, 0x0, 0x00000000, 0x0, 0x00000000
51#define IOMUXC_PMIC_STBY_REQ_CCM_PMIC_STBY_REQ 0x30330014, 0x0, 0x00000000, 0x0, 0x3033027C
52#define IOMUXC_PMIC_ON_REQ_SNVS_PMIC_ON_REQ 0x30330018, 0x0, 0x00000000, 0x0, 0x30330280
53#define IOMUXC_ONOFF_SNVS_ONOFF 0x3033001C, 0x0, 0x00000000, 0x0, 0x30330284
54#define IOMUXC_POR_B_SNVS_POR_B 0x00000000, 0x0, 0x00000000, 0x0, 0x30330288
55#define IOMUXC_RTC_RESET_B_SNVS_RTC_RESET_B 0x00000000, 0x0, 0x00000000, 0x0, 0x3033028C
56#define IOMUXC_GPIO1_IO00_GPIO1_IO00 0x30330028, 0x0, 0x00000000, 0x0, 0x30330290
57#define IOMUXC_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT 0x30330028, 0x1, 0x00000000, 0x0, 0x30330290
58#define IOMUXC_GPIO1_IO00_CCM_REF_CLK_32K 0x30330028, 0x5, 0x00000000, 0x0, 0x30330290
59#define IOMUXC_GPIO1_IO00_CCM_EXT_CLK1 0x30330028, 0x6, 0x00000000, 0x0, 0x30330290
60#define IOMUXC_GPIO1_IO01_GPIO1_IO01 0x3033002C, 0x0, 0x00000000, 0x0, 0x30330294
61#define IOMUXC_GPIO1_IO01_PWM1_OUT 0x3033002C, 0x1, 0x00000000, 0x0, 0x30330294
62#define IOMUXC_GPIO1_IO01_CCM_REF_CLK_24M 0x3033002C, 0x5, 0x00000000, 0x0, 0x30330294
63#define IOMUXC_GPIO1_IO01_CCM_EXT_CLK2 0x3033002C, 0x6, 0x00000000, 0x0, 0x30330294
64#define IOMUXC_GPIO1_IO02_GPIO1_IO02 0x30330030, 0x0, 0x00000000, 0x0, 0x30330298
65#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x30330030, 0x1, 0x00000000, 0x0, 0x30330298
66#define IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY 0x30330030, 0x5, 0x00000000, 0x0, 0x30330298
67#define IOMUXC_GPIO1_IO02_SJC_DE_B 0x30330030, 0x7, 0x00000000, 0x0, 0x30330298
68#define IOMUXC_GPIO1_IO03_GPIO1_IO03 0x30330034, 0x0, 0x00000000, 0x0, 0x3033029C
69#define IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x30330034, 0x1, 0x00000000, 0x0, 0x3033029C
70#define IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0 0x30330034, 0x5, 0x00000000, 0x0, 0x3033029C
71#define IOMUXC_GPIO1_IO04_GPIO1_IO04 0x30330038, 0x0, 0x00000000, 0x0, 0x303302A0
72#define IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x30330038, 0x1, 0x00000000, 0x0, 0x303302A0
73#define IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1 0x30330038, 0x5, 0x00000000, 0x0, 0x303302A0
74#define IOMUXC_GPIO1_IO05_GPIO1_IO05 0x3033003C, 0x0, 0x00000000, 0x0, 0x303302A4
75#define IOMUXC_GPIO1_IO05_M7_NMI 0x3033003C, 0x1, 0x00000000, 0x0, 0x303302A4
76#define IOMUXC_GPIO1_IO05_CCM_PMIC_READY 0x3033003C, 0x5, 0x303304BC, 0x0, 0x303302A4
77#define IOMUXC_GPIO1_IO06_GPIO1_IO06 0x30330040, 0x0, 0x00000000, 0x0, 0x303302A8
78#define IOMUXC_GPIO1_IO06_ENET1_MDC 0x30330040, 0x1, 0x00000000, 0x0, 0x303302A8
79#define IOMUXC_GPIO1_IO06_USDHC1_CD_B 0x30330040, 0x5, 0x00000000, 0x0, 0x303302A8
80#define IOMUXC_GPIO1_IO06_CCM_EXT_CLK3 0x30330040, 0x6, 0x00000000, 0x0, 0x303302A8
81#define IOMUXC_GPIO1_IO07_GPIO1_IO07 0x30330044, 0x0, 0x00000000, 0x0, 0x303302AC
82#define IOMUXC_GPIO1_IO07_ENET1_MDIO 0x30330044, 0x1, 0x303304C0, 0x0, 0x303302AC
83#define IOMUXC_GPIO1_IO07_USDHC1_WP 0x30330044, 0x5, 0x00000000, 0x0, 0x303302AC
84#define IOMUXC_GPIO1_IO07_CCM_EXT_CLK4 0x30330044, 0x6, 0x00000000, 0x0, 0x303302AC
85#define IOMUXC_GPIO1_IO08_GPIO1_IO08 0x30330048, 0x0, 0x00000000, 0x0, 0x303302B0
86#define IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x30330048, 0x1, 0x00000000, 0x0, 0x303302B0
87#define IOMUXC_GPIO1_IO08_PWM1_OUT 0x30330048, 0x2, 0x00000000, 0x0, 0x303302B0
88#define IOMUXC_GPIO1_IO08_USDHC2_RESET_B 0x30330048, 0x5, 0x00000000, 0x0, 0x303302B0
89#define IOMUXC_GPIO1_IO09_GPIO1_IO09 0x3033004C, 0x0, 0x00000000, 0x0, 0x303302B4
90#define IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x3033004C, 0x1, 0x00000000, 0x0, 0x303302B4
91#define IOMUXC_GPIO1_IO09_PWM2_OUT 0x3033004C, 0x2, 0x00000000, 0x0, 0x303302B4
92#define IOMUXC_GPIO1_IO09_USDHC3_RESET_B 0x3033004C, 0x4, 0x00000000, 0x0, 0x303302B4
93#define IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0 0x3033004C, 0x5, 0x00000000, 0x0, 0x303302B4
94#define IOMUXC_GPIO1_IO10_GPIO1_IO10 0x30330050, 0x0, 0x00000000, 0x0, 0x303302B8
95#define IOMUXC_GPIO1_IO10_USB1_OTG_ID 0x30330050, 0x1, 0x00000000, 0x0, 0x303302B8
96#define IOMUXC_GPIO1_IO10_PWM3_OUT 0x30330050, 0x2, 0x00000000, 0x0, 0x303302B8
97#define IOMUXC_GPIO1_IO11_GPIO1_IO11 0x30330054, 0x0, 0x00000000, 0x0, 0x303302BC
98#define IOMUXC_GPIO1_IO11_PWM2_OUT 0x30330054, 0x1, 0x00000000, 0x0, 0x303302BC
99#define IOMUXC_GPIO1_IO11_USDHC3_VSELECT 0x30330054, 0x4, 0x00000000, 0x0, 0x303302BC
100#define IOMUXC_GPIO1_IO11_CCM_PMIC_READY 0x30330054, 0x5, 0x303304BC, 0x1, 0x303302BC
101#define IOMUXC_GPIO1_IO12_GPIO1_IO12 0x30330058, 0x0, 0x00000000, 0x0, 0x303302C0
102#define IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x30330058, 0x1, 0x00000000, 0x0, 0x303302C0
103#define IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1 0x30330058, 0x5, 0x00000000, 0x0, 0x303302C0
104#define IOMUXC_GPIO1_IO13_GPIO1_IO13 0x3033005C, 0x0, 0x00000000, 0x0, 0x303302C4
105#define IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x3033005C, 0x1, 0x00000000, 0x0, 0x303302C4
106#define IOMUXC_GPIO1_IO13_PWM2_OUT 0x3033005C, 0x5, 0x00000000, 0x0, 0x303302C4
107#define IOMUXC_GPIO1_IO14_GPIO1_IO14 0x30330060, 0x0, 0x00000000, 0x0, 0x303302C8
108#define IOMUXC_GPIO1_IO14_USDHC3_CD_B 0x30330060, 0x4, 0x30330598, 0x2, 0x303302C8
109#define IOMUXC_GPIO1_IO14_PWM3_OUT 0x30330060, 0x5, 0x00000000, 0x0, 0x303302C8
110#define IOMUXC_GPIO1_IO14_CCM_CLKO1 0x30330060, 0x6, 0x00000000, 0x0, 0x303302C8
111#define IOMUXC_GPIO1_IO15_GPIO1_IO15 0x30330064, 0x0, 0x00000000, 0x0, 0x303302CC
112#define IOMUXC_GPIO1_IO15_USDHC3_WP 0x30330064, 0x4, 0x303305B8, 0x2, 0x303302CC
113#define IOMUXC_GPIO1_IO15_PWM4_OUT 0x30330064, 0x5, 0x00000000, 0x0, 0x303302CC
114#define IOMUXC_GPIO1_IO15_CCM_CLKO2 0x30330064, 0x6, 0x00000000, 0x0, 0x303302CC
115#define IOMUXC_ENET_MDC_ENET1_MDC 0x30330068, 0x0, 0x00000000, 0x0, 0x303302D0
116#define IOMUXC_ENET_MDC_SAI6_TX_DATA0 0x30330068, 0x2, 0x00000000, 0x0, 0x303302D0
117#define IOMUXC_ENET_MDC_PDM_BIT_STREAM3 0x30330068, 0x3, 0x30330540, 0x1, 0x303302D0
118#define IOMUXC_ENET_MDC_SPDIF1_OUT 0x30330068, 0x4, 0x00000000, 0x0, 0x303302D0
119#define IOMUXC_ENET_MDC_GPIO1_IO16 0x30330068, 0x5, 0x00000000, 0x0, 0x303302D0
120#define IOMUXC_ENET_MDC_USDHC3_STROBE 0x30330068, 0x6, 0x3033059C, 0x1, 0x303302D0
121#define IOMUXC_ENET_MDIO_ENET1_MDIO 0x3033006C, 0x0, 0x303304C0, 0x1, 0x303302D4
122#define IOMUXC_ENET_MDIO_SAI6_TX_SYNC 0x3033006C, 0x2, 0x00000000, 0x0, 0x303302D4
123#define IOMUXC_ENET_MDIO_PDM_BIT_STREAM2 0x3033006C, 0x3, 0x3033053C, 0x1, 0x303302D4
124#define IOMUXC_ENET_MDIO_SPDIF1_IN 0x3033006C, 0x4, 0x303305CC, 0x1, 0x303302D4
125#define IOMUXC_ENET_MDIO_GPIO1_IO17 0x3033006C, 0x5, 0x00000000, 0x0, 0x303302D4
126#define IOMUXC_ENET_MDIO_USDHC3_DATA5 0x3033006C, 0x6, 0x30330550, 0x1, 0x303302D4
127#define IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x30330070, 0x0, 0x00000000, 0x0, 0x303302D8
128#define IOMUXC_ENET_TD3_SAI6_TX_BCLK 0x30330070, 0x2, 0x00000000, 0x0, 0x303302D8
129#define IOMUXC_ENET_TD3_PDM_BIT_STREAM1 0x30330070, 0x3, 0x30330538, 0x1, 0x303302D8
130#define IOMUXC_ENET_TD3_SPDIF1_EXT_CLK 0x30330070, 0x4, 0x30330568, 0x1, 0x303302D8
131#define IOMUXC_ENET_TD3_GPIO1_IO18 0x30330070, 0x5, 0x00000000, 0x0, 0x303302D8
132#define IOMUXC_ENET_TD3_USDHC3_DATA6 0x30330070, 0x6, 0x30330584, 0x1, 0x303302D8
133#define IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x30330074, 0x0, 0x00000000, 0x0, 0x303302DC
134#define IOMUXC_ENET_TD2_ENET1_TX_CLK 0x30330074, 0x1, 0x303305A4, 0x0, 0x303302DC
135#define IOMUXC_ENET_TD2_SAI6_RX_DATA0 0x30330074, 0x2, 0x00000000, 0x0, 0x303302DC
136#define IOMUXC_ENET_TD2_PDM_BIT_STREAM3 0x30330074, 0x3, 0x30330540, 0x2, 0x303302DC
137#define IOMUXC_ENET_TD2_GPIO1_IO19 0x30330074, 0x5, 0x00000000, 0x0, 0x303302DC
138#define IOMUXC_ENET_TD2_USDHC3_DATA7 0x30330074, 0x6, 0x3033054C, 0x1, 0x303302DC
139#define IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x30330078, 0x0, 0x00000000, 0x0, 0x303302E0
140#define IOMUXC_ENET_TD1_SAI6_RX_SYNC 0x30330078, 0x2, 0x00000000, 0x0, 0x303302E0
141#define IOMUXC_ENET_TD1_PDM_BIT_STREAM2 0x30330078, 0x3, 0x3033053C, 0x2, 0x303302E0
142#define IOMUXC_ENET_TD1_GPIO1_IO20 0x30330078, 0x5, 0x00000000, 0x0, 0x303302E0
143#define IOMUXC_ENET_TD1_USDHC3_CD_B 0x30330078, 0x6, 0x30330598, 0x3, 0x303302E0
144#define IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x3033007C, 0x0, 0x00000000, 0x0, 0x303302E4
145#define IOMUXC_ENET_TD0_SAI6_RX_BCLK 0x3033007C, 0x2, 0x00000000, 0x0, 0x303302E4
146#define IOMUXC_ENET_TD0_PDM_BIT_STREAM1 0x3033007C, 0x3, 0x30330538, 0x2, 0x303302E4
147#define IOMUXC_ENET_TD0_GPIO1_IO21 0x3033007C, 0x5, 0x00000000, 0x0, 0x303302E4
148#define IOMUXC_ENET_TD0_USDHC3_WP 0x3033007C, 0x6, 0x303305B8, 0x3, 0x303302E4
149#define IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x30330080, 0x0, 0x00000000, 0x0, 0x303302E8
150#define IOMUXC_ENET_TX_CTL_SAI6_MCLK 0x30330080, 0x2, 0x00000000, 0x0, 0x303302E8
151#define IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x30330080, 0x5, 0x00000000, 0x0, 0x303302E8
152#define IOMUXC_ENET_TX_CTL_USDHC3_DATA0 0x30330080, 0x6, 0x303305B4, 0x1, 0x303302E8
153#define IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x30330084, 0x0, 0x00000000, 0x0, 0x303302EC
154#define IOMUXC_ENET_TXC_ENET1_TX_ER 0x30330084, 0x1, 0x00000000, 0x0, 0x303302EC
155#define IOMUXC_ENET_TXC_SAI7_TX_DATA0 0x30330084, 0x2, 0x00000000, 0x0, 0x303302EC
156#define IOMUXC_ENET_TXC_GPIO1_IO23 0x30330084, 0x5, 0x00000000, 0x0, 0x303302EC
157#define IOMUXC_ENET_TXC_USDHC3_DATA1 0x30330084, 0x6, 0x303305B0, 0x1, 0x303302EC
158#define IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x30330088, 0x0, 0x30330574, 0x0, 0x303302F0
159#define IOMUXC_ENET_RX_CTL_SAI7_TX_SYNC 0x30330088, 0x2, 0x00000000, 0x0, 0x303302F0
160#define IOMUXC_ENET_RX_CTL_PDM_BIT_STREAM3 0x30330088, 0x3, 0x30330540, 0x3, 0x303302F0
161#define IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x30330088, 0x5, 0x00000000, 0x0, 0x303302F0
162#define IOMUXC_ENET_RX_CTL_USDHC3_DATA2 0x30330088, 0x6, 0x303305E4, 0x1, 0x303302F0
163#define IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x3033008C, 0x0, 0x00000000, 0x0, 0x303302F4
164#define IOMUXC_ENET_RXC_ENET1_RX_ER 0x3033008C, 0x1, 0x303305C8, 0x0, 0x303302F4
165#define IOMUXC_ENET_RXC_SAI7_TX_BCLK 0x3033008C, 0x2, 0x00000000, 0x0, 0x303302F4
166#define IOMUXC_ENET_RXC_PDM_BIT_STREAM2 0x3033008C, 0x3, 0x3033053C, 0x3, 0x303302F4
167#define IOMUXC_ENET_RXC_GPIO1_IO25 0x3033008C, 0x5, 0x00000000, 0x0, 0x303302F4
168#define IOMUXC_ENET_RXC_USDHC3_DATA3 0x3033008C, 0x6, 0x303305E0, 0x1, 0x303302F4
169#define IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x30330090, 0x0, 0x3033057C, 0x0, 0x303302F8
170#define IOMUXC_ENET_RD0_SAI7_RX_DATA0 0x30330090, 0x2, 0x00000000, 0x0, 0x303302F8
171#define IOMUXC_ENET_RD0_PDM_BIT_STREAM1 0x30330090, 0x3, 0x30330538, 0x3, 0x303302F8
172#define IOMUXC_ENET_RD0_GPIO1_IO26 0x30330090, 0x5, 0x00000000, 0x0, 0x303302F8
173#define IOMUXC_ENET_RD0_USDHC3_DATA4 0x30330090, 0x6, 0x30330558, 0x1, 0x303302F8
174#define IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x30330094, 0x0, 0x30330554, 0x0, 0x303302FC
175#define IOMUXC_ENET_RD1_SAI7_RX_SYNC 0x30330094, 0x2, 0x00000000, 0x0, 0x303302FC
176#define IOMUXC_ENET_RD1_PDM_BIT_STREAM0 0x30330094, 0x3, 0x30330534, 0x1, 0x303302FC
177#define IOMUXC_ENET_RD1_GPIO1_IO27 0x30330094, 0x5, 0x00000000, 0x0, 0x303302FC
178#define IOMUXC_ENET_RD1_USDHC3_RESET_B 0x30330094, 0x6, 0x00000000, 0x0, 0x303302FC
179#define IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x30330098, 0x0, 0x00000000, 0x0, 0x30330300
180#define IOMUXC_ENET_RD2_SAI7_RX_BCLK 0x30330098, 0x2, 0x00000000, 0x0, 0x30330300
181#define IOMUXC_ENET_RD2_PDM_CLK 0x30330098, 0x3, 0x00000000, 0x0, 0x30330300
182#define IOMUXC_ENET_RD2_GPIO1_IO28 0x30330098, 0x5, 0x00000000, 0x0, 0x30330300
183#define IOMUXC_ENET_RD2_USDHC3_CLK 0x30330098, 0x6, 0x303305A0, 0x1, 0x30330300
184#define IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x3033009C, 0x0, 0x00000000, 0x0, 0x30330304
185#define IOMUXC_ENET_RD3_SAI7_MCLK 0x3033009C, 0x2, 0x00000000, 0x0, 0x30330304
186#define IOMUXC_ENET_RD3_SPDIF1_IN 0x3033009C, 0x3, 0x303305CC, 0x5, 0x30330304
187#define IOMUXC_ENET_RD3_GPIO1_IO29 0x3033009C, 0x5, 0x00000000, 0x0, 0x30330304
188#define IOMUXC_ENET_RD3_USDHC3_CMD 0x3033009C, 0x6, 0x303305DC, 0x1, 0x30330304
189#define IOMUXC_SD1_CLK_USDHC1_CLK 0x303300A0, 0x0, 0x00000000, 0x0, 0x30330308
190#define IOMUXC_SD1_CLK_ENET1_MDC 0x303300A0, 0x1, 0x00000000, 0x0, 0x30330308
191#define IOMUXC_SD1_CLK_UART1_TX 0x303300A0, 0x4, 0x00000000, 0x0, 0x30330308
192#define IOMUXC_SD1_CLK_UART1_RX 0x303300A0, 0x4, 0x303304F4, 0x4, 0x30330308
193#define IOMUXC_SD1_CLK_GPIO2_IO00 0x303300A0, 0x5, 0x00000000, 0x0, 0x30330308
194#define IOMUXC_SD1_CMD_USDHC1_CMD 0x303300A4, 0x0, 0x00000000, 0x0, 0x3033030C
195#define IOMUXC_SD1_CMD_ENET1_MDIO 0x303300A4, 0x1, 0x303304C0, 0x3, 0x3033030C
196#define IOMUXC_SD1_CMD_UART1_RX 0x303300A4, 0x4, 0x303304F4, 0x5, 0x3033030C
197#define IOMUXC_SD1_CMD_UART1_TX 0x303300A4, 0x4, 0x00000000, 0x0, 0x3033030C
198#define IOMUXC_SD1_CMD_GPIO2_IO01 0x303300A4, 0x5, 0x00000000, 0x0, 0x3033030C
199#define IOMUXC_SD1_DATA0_USDHC1_DATA0 0x303300A8, 0x0, 0x00000000, 0x0, 0x30330310
200#define IOMUXC_SD1_DATA0_ENET1_RGMII_TD1 0x303300A8, 0x1, 0x00000000, 0x0, 0x30330310
201#define IOMUXC_SD1_DATA0_UART1_RTS_B 0x303300A8, 0x4, 0x303304F0, 0x4, 0x30330310
202#define IOMUXC_SD1_DATA0_UART1_CTS_B 0x303300A8, 0x4, 0x00000000, 0x0, 0x30330310
203#define IOMUXC_SD1_DATA0_GPIO2_IO02 0x303300A8, 0x5, 0x00000000, 0x0, 0x30330310
204#define IOMUXC_SD1_DATA1_USDHC1_DATA1 0x303300AC, 0x0, 0x00000000, 0x0, 0x30330314
205#define IOMUXC_SD1_DATA1_ENET1_RGMII_TD0 0x303300AC, 0x1, 0x00000000, 0x0, 0x30330314
206#define IOMUXC_SD1_DATA1_UART1_CTS_B 0x303300AC, 0x4, 0x00000000, 0x0, 0x30330314
207#define IOMUXC_SD1_DATA1_UART1_RTS_B 0x303300AC, 0x4, 0x303304F0, 0x5, 0x30330314
208#define IOMUXC_SD1_DATA1_GPIO2_IO03 0x303300AC, 0x5, 0x00000000, 0x0, 0x30330314
209#define IOMUXC_SD1_DATA2_USDHC1_DATA2 0x303300B0, 0x0, 0x00000000, 0x0, 0x30330318
210#define IOMUXC_SD1_DATA2_ENET1_RGMII_RD0 0x303300B0, 0x1, 0x3033057C, 0x1, 0x30330318
211#define IOMUXC_SD1_DATA2_UART2_TX 0x303300B0, 0x4, 0x00000000, 0x0, 0x30330318
212#define IOMUXC_SD1_DATA2_UART2_RX 0x303300B0, 0x4, 0x303304FC, 0x4, 0x30330318
213#define IOMUXC_SD1_DATA2_GPIO2_IO04 0x303300B0, 0x5, 0x00000000, 0x0, 0x30330318
214#define IOMUXC_SD1_DATA3_USDHC1_DATA3 0x303300B4, 0x0, 0x00000000, 0x0, 0x3033031C
215#define IOMUXC_SD1_DATA3_ENET1_RGMII_RD1 0x303300B4, 0x1, 0x30330554, 0x1, 0x3033031C
216#define IOMUXC_SD1_DATA3_UART2_RX 0x303300B4, 0x4, 0x303304FC, 0x5, 0x3033031C
217#define IOMUXC_SD1_DATA3_UART2_TX 0x303300B4, 0x4, 0x00000000, 0x0, 0x3033031C
218#define IOMUXC_SD1_DATA3_GPIO2_IO05 0x303300B4, 0x5, 0x00000000, 0x0, 0x3033031C
219#define IOMUXC_SD1_DATA4_USDHC1_DATA4 0x303300B8, 0x0, 0x00000000, 0x0, 0x30330320
220#define IOMUXC_SD1_DATA4_ENET1_RGMII_TX_CTL 0x303300B8, 0x1, 0x00000000, 0x0, 0x30330320
221#define IOMUXC_SD1_DATA4_I2C1_SCL 0x303300B8, 0x3, 0x3033055C, 0x1, 0x30330320
222#define IOMUXC_SD1_DATA4_UART2_RTS_B 0x303300B8, 0x4, 0x303304F8, 0x4, 0x30330320
223#define IOMUXC_SD1_DATA4_UART2_CTS_B 0x303300B8, 0x4, 0x00000000, 0x0, 0x30330320
224#define IOMUXC_SD1_DATA4_GPIO2_IO06 0x303300B8, 0x5, 0x00000000, 0x0, 0x30330320
225#define IOMUXC_SD1_DATA5_USDHC1_DATA5 0x303300BC, 0x0, 0x00000000, 0x0, 0x30330324
226#define IOMUXC_SD1_DATA5_ENET1_TX_ER 0x303300BC, 0x1, 0x00000000, 0x0, 0x30330324
227#define IOMUXC_SD1_DATA5_I2C1_SDA 0x303300BC, 0x3, 0x3033056C, 0x1, 0x30330324
228#define IOMUXC_SD1_DATA5_UART2_CTS_B 0x303300BC, 0x4, 0x00000000, 0x0, 0x30330324
229#define IOMUXC_SD1_DATA5_UART2_RTS_B 0x303300BC, 0x4, 0x303304F8, 0x5, 0x30330324
230#define IOMUXC_SD1_DATA5_GPIO2_IO07 0x303300BC, 0x5, 0x00000000, 0x0, 0x30330324
231#define IOMUXC_SD1_DATA6_USDHC1_DATA6 0x303300C0, 0x0, 0x00000000, 0x0, 0x30330328
232#define IOMUXC_SD1_DATA6_ENET1_RGMII_RX_CTL 0x303300C0, 0x1, 0x30330574, 0x1, 0x30330328
233#define IOMUXC_SD1_DATA6_I2C2_SCL 0x303300C0, 0x3, 0x303305D0, 0x1, 0x30330328
234#define IOMUXC_SD1_DATA6_UART3_TX 0x303300C0, 0x4, 0x00000000, 0x0, 0x30330328
235#define IOMUXC_SD1_DATA6_UART3_RX 0x303300C0, 0x4, 0x30330504, 0x4, 0x30330328
236#define IOMUXC_SD1_DATA6_GPIO2_IO08 0x303300C0, 0x5, 0x00000000, 0x0, 0x30330328
237#define IOMUXC_SD1_DATA7_USDHC1_DATA7 0x303300C4, 0x0, 0x00000000, 0x0, 0x3033032C
238#define IOMUXC_SD1_DATA7_ENET1_RX_ER 0x303300C4, 0x1, 0x303305C8, 0x1, 0x3033032C
239#define IOMUXC_SD1_DATA7_I2C2_SDA 0x303300C4, 0x3, 0x30330560, 0x1, 0x3033032C
240#define IOMUXC_SD1_DATA7_UART3_RX 0x303300C4, 0x4, 0x30330504, 0x5, 0x3033032C
241#define IOMUXC_SD1_DATA7_UART3_TX 0x303300C4, 0x4, 0x00000000, 0x0, 0x3033032C
242#define IOMUXC_SD1_DATA7_GPIO2_IO09 0x303300C4, 0x5, 0x00000000, 0x0, 0x3033032C
243#define IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x303300C8, 0x0, 0x00000000, 0x0, 0x30330330
244#define IOMUXC_SD1_RESET_B_ENET1_TX_CLK 0x303300C8, 0x1, 0x303305A4, 0x1, 0x30330330
245#define IOMUXC_SD1_RESET_B_I2C3_SCL 0x303300C8, 0x3, 0x30330588, 0x1, 0x30330330
246#define IOMUXC_SD1_RESET_B_UART3_RTS_B 0x303300C8, 0x4, 0x30330500, 0x2, 0x30330330
247#define IOMUXC_SD1_RESET_B_UART3_CTS_B 0x303300C8, 0x4, 0x00000000, 0x0, 0x30330330
248#define IOMUXC_SD1_RESET_B_GPIO2_IO10 0x303300C8, 0x5, 0x00000000, 0x0, 0x30330330
249#define IOMUXC_SD1_STROBE_USDHC1_STROBE 0x303300CC, 0x0, 0x00000000, 0x0, 0x30330334
250#define IOMUXC_SD1_STROBE_I2C3_SDA 0x303300CC, 0x3, 0x303305BC, 0x1, 0x30330334
251#define IOMUXC_SD1_STROBE_UART3_CTS_B 0x303300CC, 0x4, 0x00000000, 0x0, 0x30330334
252#define IOMUXC_SD1_STROBE_UART3_RTS_B 0x303300CC, 0x4, 0x30330500, 0x3, 0x30330334
253#define IOMUXC_SD1_STROBE_GPIO2_IO11 0x303300CC, 0x5, 0x00000000, 0x0, 0x30330334
254#define IOMUXC_SD2_CD_B_USDHC2_CD_B 0x303300D0, 0x0, 0x00000000, 0x0, 0x30330338
255#define IOMUXC_SD2_CD_B_GPIO2_IO12 0x303300D0, 0x5, 0x00000000, 0x0, 0x30330338
256#define IOMUXC_SD2_CLK_USDHC2_CLK 0x303300D4, 0x0, 0x00000000, 0x0, 0x3033033C
257#define IOMUXC_SD2_CLK_SAI5_RX_SYNC 0x303300D4, 0x1, 0x303304E4, 0x1, 0x3033033C
258#define IOMUXC_SD2_CLK_ECSPI2_SCLK 0x303300D4, 0x2, 0x30330580, 0x1, 0x3033033C
259#define IOMUXC_SD2_CLK_UART4_RX 0x303300D4, 0x3, 0x3033050C, 0x4, 0x3033033C
260#define IOMUXC_SD2_CLK_UART4_TX 0x303300D4, 0x3, 0x00000000, 0x0, 0x3033033C
261#define IOMUXC_SD2_CLK_SAI5_MCLK 0x303300D4, 0x4, 0x30330594, 0x1, 0x3033033C
262#define IOMUXC_SD2_CLK_GPIO2_IO13 0x303300D4, 0x5, 0x00000000, 0x0, 0x3033033C
263#define IOMUXC_SD2_CMD_USDHC2_CMD 0x303300D8, 0x0, 0x00000000, 0x0, 0x30330340
264#define IOMUXC_SD2_CMD_SAI5_RX_BCLK 0x303300D8, 0x1, 0x303304D0, 0x1, 0x30330340
265#define IOMUXC_SD2_CMD_ECSPI2_MOSI 0x303300D8, 0x2, 0x30330590, 0x1, 0x30330340
266#define IOMUXC_SD2_CMD_UART4_TX 0x303300D8, 0x3, 0x00000000, 0x0, 0x30330340
267#define IOMUXC_SD2_CMD_UART4_RX 0x303300D8, 0x3, 0x3033050C, 0x5, 0x30330340
268#define IOMUXC_SD2_CMD_PDM_CLK 0x303300D8, 0x4, 0x00000000, 0x0, 0x30330340
269#define IOMUXC_SD2_CMD_GPIO2_IO14 0x303300D8, 0x5, 0x00000000, 0x0, 0x30330340
270#define IOMUXC_SD2_DATA0_USDHC2_DATA0 0x303300DC, 0x0, 0x00000000, 0x0, 0x30330344
271#define IOMUXC_SD2_DATA0_SAI5_RX_DATA0 0x303300DC, 0x1, 0x303304D4, 0x1, 0x30330344
272#define IOMUXC_SD2_DATA0_I2C4_SDA 0x303300DC, 0x2, 0x3033058C, 0x1, 0x30330344
273#define IOMUXC_SD2_DATA0_UART2_RX 0x303300DC, 0x3, 0x303304FC, 0x6, 0x30330344
274#define IOMUXC_SD2_DATA0_UART2_TX 0x303300DC, 0x3, 0x00000000, 0x0, 0x30330344
275#define IOMUXC_SD2_DATA0_PDM_BIT_STREAM0 0x303300DC, 0x4, 0x30330534, 0x2, 0x30330344
276#define IOMUXC_SD2_DATA0_GPIO2_IO15 0x303300DC, 0x5, 0x00000000, 0x0, 0x30330344
277#define IOMUXC_SD2_DATA1_USDHC2_DATA1 0x303300E0, 0x0, 0x00000000, 0x0, 0x30330348
278#define IOMUXC_SD2_DATA1_SAI5_TX_SYNC 0x303300E0, 0x1, 0x303304EC, 0x1, 0x30330348
279#define IOMUXC_SD2_DATA1_I2C4_SCL 0x303300E0, 0x2, 0x303305D4, 0x1, 0x30330348
280#define IOMUXC_SD2_DATA1_UART2_TX 0x303300E0, 0x3, 0x00000000, 0x0, 0x30330348
281#define IOMUXC_SD2_DATA1_UART2_RX 0x303300E0, 0x3, 0x303304FC, 0x7, 0x30330348
282#define IOMUXC_SD2_DATA1_PDM_BIT_STREAM1 0x303300E0, 0x4, 0x30330538, 0x4, 0x30330348
283#define IOMUXC_SD2_DATA1_GPIO2_IO16 0x303300E0, 0x5, 0x00000000, 0x0, 0x30330348
284#define IOMUXC_SD2_DATA2_USDHC2_DATA2 0x303300E4, 0x0, 0x00000000, 0x0, 0x3033034C
285#define IOMUXC_SD2_DATA2_SAI5_TX_BCLK 0x303300E4, 0x1, 0x303304E8, 0x1, 0x3033034C
286#define IOMUXC_SD2_DATA2_ECSPI2_SS0 0x303300E4, 0x2, 0x30330570, 0x2, 0x3033034C
287#define IOMUXC_SD2_DATA2_SPDIF1_OUT 0x303300E4, 0x3, 0x00000000, 0x0, 0x3033034C
288#define IOMUXC_SD2_DATA2_PDM_BIT_STREAM2 0x303300E4, 0x4, 0x3033053C, 0x4, 0x3033034C
289#define IOMUXC_SD2_DATA2_GPIO2_IO17 0x303300E4, 0x5, 0x00000000, 0x0, 0x3033034C
290#define IOMUXC_SD2_DATA3_USDHC2_DATA3 0x303300E8, 0x0, 0x00000000, 0x0, 0x30330350
291#define IOMUXC_SD2_DATA3_SAI5_TX_DATA0 0x303300E8, 0x1, 0x00000000, 0x0, 0x30330350
292#define IOMUXC_SD2_DATA3_ECSPI2_MISO 0x303300E8, 0x2, 0x30330578, 0x1, 0x30330350
293#define IOMUXC_SD2_DATA3_SPDIF1_IN 0x303300E8, 0x3, 0x303305CC, 0x2, 0x30330350
294#define IOMUXC_SD2_DATA3_PDM_BIT_STREAM3 0x303300E8, 0x4, 0x30330540, 0x4, 0x30330350
295#define IOMUXC_SD2_DATA3_GPIO2_IO18 0x303300E8, 0x5, 0x00000000, 0x0, 0x30330350
296#define IOMUXC_SD2_DATA3_SRC_EARLY_RESET 0x303300E8, 0x6, 0x00000000, 0x0, 0x30330350
297#define IOMUXC_SD2_RESET_B_USDHC2_RESET_B 0x303300EC, 0x0, 0x00000000, 0x0, 0x30330354
298#define IOMUXC_SD2_RESET_B_GPIO2_IO19 0x303300EC, 0x5, 0x00000000, 0x0, 0x30330354
299#define IOMUXC_SD2_RESET_B_SRC_SYSTEM_RESET 0x303300EC, 0x6, 0x00000000, 0x0, 0x30330354
300#define IOMUXC_SD2_WP_USDHC2_WP 0x303300F0, 0x0, 0x00000000, 0x0, 0x30330358
301#define IOMUXC_SD2_WP_GPIO2_IO20 0x303300F0, 0x5, 0x00000000, 0x0, 0x30330358
302#define IOMUXC_SD2_WP_CORESIGHT_EVENTI 0x303300F0, 0x6, 0x00000000, 0x0, 0x30330358
303#define IOMUXC_NAND_ALE_NAND_ALE 0x303300F4, 0x0, 0x00000000, 0x0, 0x3033035C
304#define IOMUXC_NAND_ALE_QSPI_A_SCLK 0x303300F4, 0x1, 0x00000000, 0x0, 0x3033035C
305#define IOMUXC_NAND_ALE_PDM_BIT_STREAM0 0x303300F4, 0x3, 0x30330534, 0x3, 0x3033035C
306#define IOMUXC_NAND_ALE_UART3_RX 0x303300F4, 0x4, 0x30330504, 0x6, 0x3033035C
307#define IOMUXC_NAND_ALE_UART3_TX 0x303300F4, 0x4, 0x00000000, 0x0, 0x3033035C
308#define IOMUXC_NAND_ALE_GPIO3_IO00 0x303300F4, 0x5, 0x00000000, 0x0, 0x3033035C
309#define IOMUXC_NAND_ALE_CORESIGHT_TRACE_CLK 0x303300F4, 0x6, 0x00000000, 0x0, 0x3033035C
310#define IOMUXC_NAND_CE0_B_NAND_CE0_B 0x303300F8, 0x0, 0x00000000, 0x0, 0x30330360
311#define IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x303300F8, 0x1, 0x00000000, 0x0, 0x30330360
312#define IOMUXC_NAND_CE0_B_PDM_BIT_STREAM1 0x303300F8, 0x3, 0x30330538, 0x5, 0x30330360
313#define IOMUXC_NAND_CE0_B_UART3_TX 0x303300F8, 0x4, 0x00000000, 0x0, 0x30330360
314#define IOMUXC_NAND_CE0_B_UART3_RX 0x303300F8, 0x4, 0x30330504, 0x7, 0x30330360
315#define IOMUXC_NAND_CE0_B_GPIO3_IO01 0x303300F8, 0x5, 0x00000000, 0x0, 0x30330360
316#define IOMUXC_NAND_CE0_B_CORESIGHT_TRACE_CTL 0x303300F8, 0x6, 0x00000000, 0x0, 0x30330360
317#define IOMUXC_NAND_CE1_B_NAND_CE1_B 0x303300FC, 0x0, 0x00000000, 0x0, 0x30330364
318#define IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x303300FC, 0x1, 0x00000000, 0x0, 0x30330364
319#define IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x303300FC, 0x2, 0x3033059C, 0x0, 0x30330364
320#define IOMUXC_NAND_CE1_B_PDM_BIT_STREAM0 0x303300FC, 0x3, 0x30330534, 0x4, 0x30330364
321#define IOMUXC_NAND_CE1_B_I2C4_SCL 0x303300FC, 0x4, 0x303305D4, 0x2, 0x30330364
322#define IOMUXC_NAND_CE1_B_GPIO3_IO02 0x303300FC, 0x5, 0x00000000, 0x0, 0x30330364
323#define IOMUXC_NAND_CE1_B_CORESIGHT_TRACE00 0x303300FC, 0x6, 0x00000000, 0x0, 0x30330364
324#define IOMUXC_NAND_CE2_B_NAND_CE2_B 0x30330100, 0x0, 0x00000000, 0x0, 0x30330368
325#define IOMUXC_NAND_CE2_B_QSPI_B_SS0_B 0x30330100, 0x1, 0x00000000, 0x0, 0x30330368
326#define IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x30330100, 0x2, 0x30330550, 0x0, 0x30330368
327#define IOMUXC_NAND_CE2_B_PDM_BIT_STREAM1 0x30330100, 0x3, 0x30330538, 0x6, 0x30330368
328#define IOMUXC_NAND_CE2_B_I2C4_SDA 0x30330100, 0x4, 0x3033058C, 0x2, 0x30330368
329#define IOMUXC_NAND_CE2_B_GPIO3_IO03 0x30330100, 0x5, 0x00000000, 0x0, 0x30330368
330#define IOMUXC_NAND_CE2_B_CORESIGHT_TRACE01 0x30330100, 0x6, 0x00000000, 0x0, 0x30330368
331#define IOMUXC_NAND_CE3_B_NAND_CE3_B 0x30330104, 0x0, 0x00000000, 0x0, 0x3033036C
332#define IOMUXC_NAND_CE3_B_QSPI_B_SS1_B 0x30330104, 0x1, 0x00000000, 0x0, 0x3033036C
333#define IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x30330104, 0x2, 0x30330584, 0x0, 0x3033036C
334#define IOMUXC_NAND_CE3_B_PDM_BIT_STREAM2 0x30330104, 0x3, 0x3033053C, 0x5, 0x3033036C
335#define IOMUXC_NAND_CE3_B_I2C3_SDA 0x30330104, 0x4, 0x303305BC, 0x2, 0x3033036C
336#define IOMUXC_NAND_CE3_B_GPIO3_IO04 0x30330104, 0x5, 0x00000000, 0x0, 0x3033036C
337#define IOMUXC_NAND_CE3_B_CORESIGHT_TRACE02 0x30330104, 0x6, 0x00000000, 0x0, 0x3033036C
338#define IOMUXC_NAND_CLE_NAND_CLE 0x30330108, 0x0, 0x00000000, 0x0, 0x30330370
339#define IOMUXC_NAND_CLE_QSPI_B_SCLK 0x30330108, 0x1, 0x00000000, 0x0, 0x30330370
340#define IOMUXC_NAND_CLE_USDHC3_DATA7 0x30330108, 0x2, 0x3033054C, 0x0, 0x30330370
341#define IOMUXC_NAND_CLE_GPIO3_IO05 0x30330108, 0x5, 0x00000000, 0x0, 0x30330370
342#define IOMUXC_NAND_CLE_CORESIGHT_TRACE03 0x30330108, 0x6, 0x00000000, 0x0, 0x30330370
343#define IOMUXC_NAND_DATA00_NAND_DATA00 0x3033010C, 0x0, 0x00000000, 0x0, 0x30330374
344#define IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x3033010C, 0x1, 0x00000000, 0x0, 0x30330374
345#define IOMUXC_NAND_DATA00_PDM_BIT_STREAM2 0x3033010C, 0x3, 0x3033053C, 0x6, 0x30330374
346#define IOMUXC_NAND_DATA00_UART4_RX 0x3033010C, 0x4, 0x3033050C, 0x6, 0x30330374
347#define IOMUXC_NAND_DATA00_UART4_TX 0x3033010C, 0x4, 0x00000000, 0x0, 0x30330374
348#define IOMUXC_NAND_DATA00_GPIO3_IO06 0x3033010C, 0x5, 0x00000000, 0x0, 0x30330374
349#define IOMUXC_NAND_DATA00_CORESIGHT_TRACE04 0x3033010C, 0x6, 0x00000000, 0x0, 0x30330374
350#define IOMUXC_NAND_DATA01_NAND_DATA01 0x30330110, 0x0, 0x00000000, 0x0, 0x30330378
351#define IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x30330110, 0x1, 0x00000000, 0x0, 0x30330378
352#define IOMUXC_NAND_DATA01_PDM_BIT_STREAM3 0x30330110, 0x3, 0x30330540, 0x5, 0x30330378
353#define IOMUXC_NAND_DATA01_UART4_TX 0x30330110, 0x4, 0x00000000, 0x0, 0x30330378
354#define IOMUXC_NAND_DATA01_UART4_RX 0x30330110, 0x4, 0x3033050C, 0x7, 0x30330378
355#define IOMUXC_NAND_DATA01_GPIO3_IO07 0x30330110, 0x5, 0x00000000, 0x0, 0x30330378
356#define IOMUXC_NAND_DATA01_CORESIGHT_TRACE05 0x30330110, 0x6, 0x00000000, 0x0, 0x30330378
357#define IOMUXC_NAND_DATA02_NAND_DATA02 0x30330114, 0x0, 0x00000000, 0x0, 0x3033037C
358#define IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x30330114, 0x1, 0x00000000, 0x0, 0x3033037C
359#define IOMUXC_NAND_DATA02_USDHC3_CD_B 0x30330114, 0x2, 0x30330598, 0x0, 0x3033037C
360#define IOMUXC_NAND_DATA02_I2C4_SDA 0x30330114, 0x4, 0x3033058C, 0x3, 0x3033037C
361#define IOMUXC_NAND_DATA02_GPIO3_IO08 0x30330114, 0x5, 0x00000000, 0x0, 0x3033037C
362#define IOMUXC_NAND_DATA02_CORESIGHT_TRACE06 0x30330114, 0x6, 0x00000000, 0x0, 0x3033037C
363#define IOMUXC_NAND_DATA03_NAND_DATA03 0x30330118, 0x0, 0x00000000, 0x0, 0x30330380
364#define IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x30330118, 0x1, 0x00000000, 0x0, 0x30330380
365#define IOMUXC_NAND_DATA03_USDHC3_WP 0x30330118, 0x2, 0x303305B8, 0x0, 0x30330380
366#define IOMUXC_NAND_DATA03_GPIO3_IO09 0x30330118, 0x5, 0x00000000, 0x0, 0x30330380
367#define IOMUXC_NAND_DATA03_CORESIGHT_TRACE07 0x30330118, 0x6, 0x00000000, 0x0, 0x30330380
368#define IOMUXC_NAND_DATA04_NAND_DATA04 0x3033011C, 0x0, 0x00000000, 0x0, 0x30330384
369#define IOMUXC_NAND_DATA04_QSPI_B_DATA0 0x3033011C, 0x1, 0x00000000, 0x0, 0x30330384
370#define IOMUXC_NAND_DATA04_USDHC3_DATA0 0x3033011C, 0x2, 0x303305B4, 0x0, 0x30330384
371#define IOMUXC_NAND_DATA04_GPIO3_IO10 0x3033011C, 0x5, 0x00000000, 0x0, 0x30330384
372#define IOMUXC_NAND_DATA04_CORESIGHT_TRACE08 0x3033011C, 0x6, 0x00000000, 0x0, 0x30330384
373#define IOMUXC_NAND_DATA05_NAND_DATA05 0x30330120, 0x0, 0x00000000, 0x0, 0x30330388
374#define IOMUXC_NAND_DATA05_QSPI_B_DATA1 0x30330120, 0x1, 0x00000000, 0x0, 0x30330388
375#define IOMUXC_NAND_DATA05_USDHC3_DATA1 0x30330120, 0x2, 0x303305B0, 0x0, 0x30330388
376#define IOMUXC_NAND_DATA05_GPIO3_IO11 0x30330120, 0x5, 0x00000000, 0x0, 0x30330388
377#define IOMUXC_NAND_DATA05_CORESIGHT_TRACE09 0x30330120, 0x6, 0x00000000, 0x0, 0x30330388
378#define IOMUXC_NAND_DATA06_NAND_DATA06 0x30330124, 0x0, 0x00000000, 0x0, 0x3033038C
379#define IOMUXC_NAND_DATA06_QSPI_B_DATA2 0x30330124, 0x1, 0x00000000, 0x0, 0x3033038C
380#define IOMUXC_NAND_DATA06_USDHC3_DATA2 0x30330124, 0x2, 0x303305E4, 0x0, 0x3033038C
381#define IOMUXC_NAND_DATA06_GPIO3_IO12 0x30330124, 0x5, 0x00000000, 0x0, 0x3033038C
382#define IOMUXC_NAND_DATA06_CORESIGHT_TRACE10 0x30330124, 0x6, 0x00000000, 0x0, 0x3033038C
383#define IOMUXC_NAND_DATA07_NAND_DATA07 0x30330128, 0x0, 0x00000000, 0x0, 0x30330390
384#define IOMUXC_NAND_DATA07_QSPI_B_DATA3 0x30330128, 0x1, 0x00000000, 0x0, 0x30330390
385#define IOMUXC_NAND_DATA07_USDHC3_DATA3 0x30330128, 0x2, 0x303305E0, 0x0, 0x30330390
386#define IOMUXC_NAND_DATA07_GPIO3_IO13 0x30330128, 0x5, 0x00000000, 0x0, 0x30330390
387#define IOMUXC_NAND_DATA07_CORESIGHT_TRACE11 0x30330128, 0x6, 0x00000000, 0x0, 0x30330390
388#define IOMUXC_NAND_DQS_NAND_DQS 0x3033012C, 0x0, 0x00000000, 0x0, 0x30330394
389#define IOMUXC_NAND_DQS_QSPI_A_DQS 0x3033012C, 0x1, 0x00000000, 0x0, 0x30330394
390#define IOMUXC_NAND_DQS_PDM_CLK 0x3033012C, 0x3, 0x00000000, 0x0, 0x30330394
391#define IOMUXC_NAND_DQS_I2C3_SCL 0x3033012C, 0x4, 0x30330588, 0x2, 0x30330394
392#define IOMUXC_NAND_DQS_GPIO3_IO14 0x3033012C, 0x5, 0x00000000, 0x0, 0x30330394
393#define IOMUXC_NAND_DQS_CORESIGHT_TRACE12 0x3033012C, 0x6, 0x00000000, 0x0, 0x30330394
394#define IOMUXC_NAND_RE_B_NAND_RE_B 0x30330130, 0x0, 0x00000000, 0x0, 0x30330398
395#define IOMUXC_NAND_RE_B_QSPI_B_DQS 0x30330130, 0x1, 0x00000000, 0x0, 0x30330398
396#define IOMUXC_NAND_RE_B_USDHC3_DATA4 0x30330130, 0x2, 0x30330558, 0x0, 0x30330398
397#define IOMUXC_NAND_RE_B_PDM_BIT_STREAM1 0x30330130, 0x3, 0x30330538, 0x7, 0x30330398
398#define IOMUXC_NAND_RE_B_GPIO3_IO15 0x30330130, 0x5, 0x00000000, 0x0, 0x30330398
399#define IOMUXC_NAND_RE_B_CORESIGHT_TRACE13 0x30330130, 0x6, 0x00000000, 0x0, 0x30330398
400#define IOMUXC_NAND_READY_B_NAND_READY_B 0x30330134, 0x0, 0x00000000, 0x0, 0x3033039C
401#define IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x30330134, 0x2, 0x00000000, 0x0, 0x3033039C
402#define IOMUXC_NAND_READY_B_PDM_BIT_STREAM3 0x30330134, 0x3, 0x30330540, 0x6, 0x3033039C
403#define IOMUXC_NAND_READY_B_I2C3_SCL 0x30330134, 0x4, 0x30330588, 0x3, 0x3033039C
404#define IOMUXC_NAND_READY_B_GPIO3_IO16 0x30330134, 0x5, 0x00000000, 0x0, 0x3033039C
405#define IOMUXC_NAND_READY_B_CORESIGHT_TRACE14 0x30330134, 0x6, 0x00000000, 0x0, 0x3033039C
406#define IOMUXC_NAND_WE_B_NAND_WE_B 0x30330138, 0x0, 0x00000000, 0x0, 0x303303A0
407#define IOMUXC_NAND_WE_B_USDHC3_CLK 0x30330138, 0x2, 0x303305A0, 0x0, 0x303303A0
408#define IOMUXC_NAND_WE_B_I2C3_SDA 0x30330138, 0x4, 0x303305BC, 0x3, 0x303303A0
409#define IOMUXC_NAND_WE_B_GPIO3_IO17 0x30330138, 0x5, 0x00000000, 0x0, 0x303303A0
410#define IOMUXC_NAND_WE_B_CORESIGHT_TRACE15 0x30330138, 0x6, 0x00000000, 0x0, 0x303303A0
411#define IOMUXC_NAND_WP_B_NAND_WP_B 0x3033013C, 0x0, 0x00000000, 0x0, 0x303303A4
412#define IOMUXC_NAND_WP_B_USDHC3_CMD 0x3033013C, 0x2, 0x303305DC, 0x0, 0x303303A4
413#define IOMUXC_NAND_WP_B_I2C4_SDA 0x3033013C, 0x4, 0x3033058C, 0x4, 0x303303A4
414#define IOMUXC_NAND_WP_B_GPIO3_IO18 0x3033013C, 0x5, 0x00000000, 0x0, 0x303303A4
415#define IOMUXC_NAND_WP_B_CORESIGHT_EVENTO 0x3033013C, 0x6, 0x00000000, 0x0, 0x303303A4
416#define IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0x30330140, 0x0, 0x303304E4, 0x0, 0x303303A8
417#define IOMUXC_SAI5_RXFS_GPIO3_IO19 0x30330140, 0x5, 0x00000000, 0x0, 0x303303A8
418#define IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0x30330144, 0x0, 0x303304D0, 0x0, 0x303303AC
419#define IOMUXC_SAI5_RXC_PDM_CLK 0x30330144, 0x4, 0x00000000, 0x0, 0x303303AC
420#define IOMUXC_SAI5_RXC_GPIO3_IO20 0x30330144, 0x5, 0x00000000, 0x0, 0x303303AC
421#define IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x30330148, 0x0, 0x303304D4, 0x0, 0x303303B0
422#define IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0x30330148, 0x4, 0x30330534, 0x0, 0x303303B0
423#define IOMUXC_SAI5_RXD0_GPIO3_IO21 0x30330148, 0x5, 0x00000000, 0x0, 0x303303B0
424#define IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0x3033014C, 0x0, 0x303304D8, 0x0, 0x303303B4
425#define IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x3033014C, 0x3, 0x303304EC, 0x0, 0x303303B4
426#define IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0x3033014C, 0x4, 0x30330538, 0x0, 0x303303B4
427#define IOMUXC_SAI5_RXD1_GPIO3_IO22 0x3033014C, 0x5, 0x00000000, 0x0, 0x303303B4
428#define IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0x30330150, 0x0, 0x303304DC, 0x0, 0x303303B8
429#define IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x30330150, 0x3, 0x303304E8, 0x0, 0x303303B8
430#define IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0x30330150, 0x4, 0x3033053C, 0x0, 0x303303B8
431#define IOMUXC_SAI5_RXD2_GPIO3_IO23 0x30330150, 0x5, 0x00000000, 0x0, 0x303303B8
432#define IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x30330154, 0x0, 0x303304E0, 0x0, 0x303303BC
433#define IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x30330154, 0x3, 0x00000000, 0x0, 0x303303BC
434#define IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0x30330154, 0x4, 0x30330540, 0x0, 0x303303BC
435#define IOMUXC_SAI5_RXD3_GPIO3_IO24 0x30330154, 0x5, 0x00000000, 0x0, 0x303303BC
436#define IOMUXC_SAI5_MCLK_SAI5_MCLK 0x30330158, 0x0, 0x30330594, 0x0, 0x303303C0
437#define IOMUXC_SAI5_MCLK_GPIO3_IO25 0x30330158, 0x5, 0x00000000, 0x0, 0x303303C0
438#define IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x303301B0, 0x0, 0x00000000, 0x0, 0x30330418
439#define IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x303301B0, 0x1, 0x303304EC, 0x2, 0x30330418
440#define IOMUXC_SAI2_RXFS_SAI5_TX_DATA1 0x303301B0, 0x2, 0x00000000, 0x0, 0x30330418
441#define IOMUXC_SAI2_RXFS_SAI2_RX_DATA1 0x303301B0, 0x3, 0x303305AC, 0x0, 0x30330418
442#define IOMUXC_SAI2_RXFS_UART1_TX 0x303301B0, 0x4, 0x00000000, 0x0, 0x30330418
443#define IOMUXC_SAI2_RXFS_UART1_RX 0x303301B0, 0x4, 0x303304F4, 0x2, 0x30330418
444#define IOMUXC_SAI2_RXFS_GPIO4_IO21 0x303301B0, 0x5, 0x00000000, 0x0, 0x30330418
445#define IOMUXC_SAI2_RXFS_PDM_BIT_STREAM2 0x303301B0, 0x6, 0x3033053C, 0x7, 0x30330418
446#define IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x303301B4, 0x0, 0x00000000, 0x0, 0x3033041C
447#define IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x303301B4, 0x1, 0x303304E8, 0x2, 0x3033041C
448#define IOMUXC_SAI2_RXC_UART1_RX 0x303301B4, 0x4, 0x303304F4, 0x3, 0x3033041C
449#define IOMUXC_SAI2_RXC_UART1_TX 0x303301B4, 0x4, 0x00000000, 0x0, 0x3033041C
450#define IOMUXC_SAI2_RXC_GPIO4_IO22 0x303301B4, 0x5, 0x00000000, 0x0, 0x3033041C
451#define IOMUXC_SAI2_RXC_PDM_BIT_STREAM1 0x303301B4, 0x6, 0x30330538, 0x8, 0x3033041C
452#define IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x303301B8, 0x0, 0x00000000, 0x0, 0x30330420
453#define IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x303301B8, 0x1, 0x00000000, 0x0, 0x30330420
454#define IOMUXC_SAI2_RXD0_SAI2_TX_DATA1 0x303301B8, 0x3, 0x00000000, 0x0, 0x30330420
455#define IOMUXC_SAI2_RXD0_UART1_RTS_B 0x303301B8, 0x4, 0x303304F0, 0x2, 0x30330420
456#define IOMUXC_SAI2_RXD0_UART1_CTS_B 0x303301B8, 0x4, 0x00000000, 0x0, 0x30330420
457#define IOMUXC_SAI2_RXD0_GPIO4_IO23 0x303301B8, 0x5, 0x00000000, 0x0, 0x30330420
458#define IOMUXC_SAI2_RXD0_PDM_BIT_STREAM3 0x303301B8, 0x6, 0x30330540, 0x7, 0x30330420
459#define IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x303301BC, 0x0, 0x00000000, 0x0, 0x30330424
460#define IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x303301BC, 0x1, 0x00000000, 0x0, 0x30330424
461#define IOMUXC_SAI2_TXFS_SAI2_TX_DATA1 0x303301BC, 0x3, 0x00000000, 0x0, 0x30330424
462#define IOMUXC_SAI2_TXFS_UART1_CTS_B 0x303301BC, 0x4, 0x00000000, 0x0, 0x30330424
463#define IOMUXC_SAI2_TXFS_UART1_RTS_B 0x303301BC, 0x4, 0x303304F0, 0x3, 0x30330424
464#define IOMUXC_SAI2_TXFS_GPIO4_IO24 0x303301BC, 0x5, 0x00000000, 0x0, 0x30330424
465#define IOMUXC_SAI2_TXFS_PDM_BIT_STREAM2 0x303301BC, 0x6, 0x3033053C, 0x8, 0x30330424
466#define IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x303301C0, 0x0, 0x00000000, 0x0, 0x30330428
467#define IOMUXC_SAI2_TXC_SAI5_TX_DATA2 0x303301C0, 0x1, 0x00000000, 0x0, 0x30330428
468#define IOMUXC_SAI2_TXC_GPIO4_IO25 0x303301C0, 0x5, 0x00000000, 0x0, 0x30330428
469#define IOMUXC_SAI2_TXC_PDM_BIT_STREAM1 0x303301C0, 0x6, 0x30330538, 0x9, 0x30330428
470#define IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x303301C4, 0x0, 0x00000000, 0x0, 0x3033042C
471#define IOMUXC_SAI2_TXD0_SAI5_TX_DATA3 0x303301C4, 0x1, 0x00000000, 0x0, 0x3033042C
472#define IOMUXC_SAI2_TXD0_GPIO4_IO26 0x303301C4, 0x5, 0x00000000, 0x0, 0x3033042C
473#define IOMUXC_SAI2_TXD0_SRC_BOOT_MODE4 0x303301C4, 0x6, 0x00000000, 0x0, 0x3033042C
474#define IOMUXC_SAI2_MCLK_SAI2_MCLK 0x303301C8, 0x0, 0x00000000, 0x0, 0x30330430
475#define IOMUXC_SAI2_MCLK_SAI5_MCLK 0x303301C8, 0x1, 0x30330594, 0x2, 0x30330430
476#define IOMUXC_SAI2_MCLK_GPIO4_IO27 0x303301C8, 0x5, 0x00000000, 0x0, 0x30330430
477#define IOMUXC_SAI2_MCLK_SAI3_MCLK 0x303301C8, 0x6, 0x303305C0, 0x1, 0x30330430
478#define IOMUXC_SAI3_RXFS_SAI3_RX_SYNC 0x303301CC, 0x0, 0x00000000, 0x0, 0x30330434
479#define IOMUXC_SAI3_RXFS_GPT1_CAPTURE1 0x303301CC, 0x1, 0x303305F0, 0x0, 0x30330434
480#define IOMUXC_SAI3_RXFS_SAI5_RX_SYNC 0x303301CC, 0x2, 0x303304E4, 0x2, 0x30330434
481#define IOMUXC_SAI3_RXFS_SAI3_RX_DATA1 0x303301CC, 0x3, 0x00000000, 0x0, 0x30330434
482#define IOMUXC_SAI3_RXFS_SPDIF1_IN 0x303301CC, 0x4, 0x303305CC, 0x3, 0x30330434
483#define IOMUXC_SAI3_RXFS_GPIO4_IO28 0x303301CC, 0x5, 0x00000000, 0x0, 0x30330434
484#define IOMUXC_SAI3_RXFS_PDM_BIT_STREAM0 0x303301CC, 0x6, 0x30330534, 0x5, 0x30330434
485#define IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x303301D0, 0x0, 0x00000000, 0x0, 0x30330438
486#define IOMUXC_SAI3_RXC_GPT1_CLK 0x303301D0, 0x1, 0x303305E8, 0x0, 0x30330438
487#define IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x303301D0, 0x2, 0x303304D0, 0x2, 0x30330438
488#define IOMUXC_SAI3_RXC_SAI2_RX_DATA1 0x303301D0, 0x3, 0x303305AC, 0x2, 0x30330438
489#define IOMUXC_SAI3_RXC_UART2_CTS_B 0x303301D0, 0x4, 0x00000000, 0x0, 0x30330438
490#define IOMUXC_SAI3_RXC_UART2_RTS_B 0x303301D0, 0x4, 0x303304F8, 0x2, 0x30330438
491#define IOMUXC_SAI3_RXC_GPIO4_IO29 0x303301D0, 0x5, 0x00000000, 0x0, 0x30330438
492#define IOMUXC_SAI3_RXC_PDM_CLK 0x303301D0, 0x6, 0x00000000, 0x0, 0x30330438
493#define IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x303301D4, 0x0, 0x00000000, 0x0, 0x3033043C
494#define IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x303301D4, 0x1, 0x00000000, 0x0, 0x3033043C
495#define IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x303301D4, 0x2, 0x303304D4, 0x2, 0x3033043C
496#define IOMUXC_SAI3_RXD_SAI3_TX_DATA1 0x303301D4, 0x3, 0x00000000, 0x0, 0x3033043C
497#define IOMUXC_SAI3_RXD_UART2_RTS_B 0x303301D4, 0x4, 0x303304F8, 0x3, 0x3033043C
498#define IOMUXC_SAI3_RXD_UART2_CTS_B 0x303301D4, 0x4, 0x00000000, 0x0, 0x3033043C
499#define IOMUXC_SAI3_RXD_GPIO4_IO30 0x303301D4, 0x5, 0x00000000, 0x0, 0x3033043C
500#define IOMUXC_SAI3_RXD_PDM_BIT_STREAM1 0x303301D4, 0x6, 0x30330538, 0x10, 0x3033043C
501#define IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x303301D8, 0x0, 0x00000000, 0x0, 0x30330440
502#define IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x303301D8, 0x1, 0x303305EC, 0x0, 0x30330440
503#define IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x303301D8, 0x2, 0x303304D8, 0x1, 0x30330440
504#define IOMUXC_SAI3_TXFS_SAI3_TX_DATA1 0x303301D8, 0x3, 0x00000000, 0x0, 0x30330440
505#define IOMUXC_SAI3_TXFS_UART2_RX 0x303301D8, 0x4, 0x303304FC, 0x2, 0x30330440
506#define IOMUXC_SAI3_TXFS_UART2_TX 0x303301D8, 0x4, 0x00000000, 0x0, 0x30330440
507#define IOMUXC_SAI3_TXFS_GPIO4_IO31 0x303301D8, 0x5, 0x00000000, 0x0, 0x30330440
508#define IOMUXC_SAI3_TXFS_PDM_BIT_STREAM3 0x303301D8, 0x6, 0x30330540, 0x9, 0x30330440
509#define IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x303301DC, 0x0, 0x00000000, 0x0, 0x30330444
510#define IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x303301DC, 0x1, 0x00000000, 0x0, 0x30330444
511#define IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x303301DC, 0x2, 0x303304DC, 0x1, 0x30330444
512#define IOMUXC_SAI3_TXC_SAI2_TX_DATA1 0x303301DC, 0x3, 0x00000000, 0x0, 0x30330444
513#define IOMUXC_SAI3_TXC_UART2_TX 0x303301DC, 0x4, 0x00000000, 0x0, 0x30330444
514#define IOMUXC_SAI3_TXC_UART2_RX 0x303301DC, 0x4, 0x303304FC, 0x3, 0x30330444
515#define IOMUXC_SAI3_TXC_GPIO5_IO00 0x303301DC, 0x5, 0x00000000, 0x0, 0x30330444
516#define IOMUXC_SAI3_TXC_PDM_BIT_STREAM2 0x303301DC, 0x6, 0x3033053C, 0x9, 0x30330444
517#define IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x303301E0, 0x0, 0x00000000, 0x0, 0x30330448
518#define IOMUXC_SAI3_TXD_GPT1_COMPARE3 0x303301E0, 0x1, 0x00000000, 0x0, 0x30330448
519#define IOMUXC_SAI3_TXD_SAI5_RX_DATA3 0x303301E0, 0x2, 0x303304E0, 0x1, 0x30330448
520#define IOMUXC_SAI3_TXD_SPDIF1_EXT_CLK 0x303301E0, 0x4, 0x30330568, 0x2, 0x30330448
521#define IOMUXC_SAI3_TXD_GPIO5_IO01 0x303301E0, 0x5, 0x00000000, 0x0, 0x30330448
522#define IOMUXC_SAI3_TXD_SRC_BOOT_MODE5 0x303301E0, 0x6, 0x00000000, 0x0, 0x30330448
523#define IOMUXC_SAI3_MCLK_SAI3_MCLK 0x303301E4, 0x0, 0x303305C0, 0x0, 0x3033044C
524#define IOMUXC_SAI3_MCLK_PWM4_OUT 0x303301E4, 0x1, 0x00000000, 0x0, 0x3033044C
525#define IOMUXC_SAI3_MCLK_SAI5_MCLK 0x303301E4, 0x2, 0x30330594, 0x3, 0x3033044C
526#define IOMUXC_SAI3_MCLK_SPDIF1_OUT 0x303301E4, 0x4, 0x00000000, 0x0, 0x3033044C
527#define IOMUXC_SAI3_MCLK_GPIO5_IO02 0x303301E4, 0x5, 0x00000000, 0x0, 0x3033044C
528#define IOMUXC_SAI3_MCLK_SPDIF1_IN 0x303301E4, 0x6, 0x303305CC, 0x4, 0x3033044C
529#define IOMUXC_SPDIF_TX_SPDIF1_OUT 0x303301E8, 0x0, 0x00000000, 0x0, 0x30330450
530#define IOMUXC_SPDIF_TX_PWM3_OUT 0x303301E8, 0x1, 0x00000000, 0x0, 0x30330450
531#define IOMUXC_SPDIF_TX_GPIO5_IO03 0x303301E8, 0x5, 0x00000000, 0x0, 0x30330450
532#define IOMUXC_SPDIF_RX_SPDIF1_IN 0x303301EC, 0x0, 0x303305CC, 0x0, 0x30330454
533#define IOMUXC_SPDIF_RX_PWM2_OUT 0x303301EC, 0x1, 0x00000000, 0x0, 0x30330454
534#define IOMUXC_SPDIF_RX_GPIO5_IO04 0x303301EC, 0x5, 0x00000000, 0x0, 0x30330454
535#define IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK 0x303301F0, 0x0, 0x30330568, 0x0, 0x30330458
536#define IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x303301F0, 0x1, 0x00000000, 0x0, 0x30330458
537#define IOMUXC_SPDIF_EXT_CLK_GPIO5_IO05 0x303301F0, 0x5, 0x00000000, 0x0, 0x30330458
538#define IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x303301F4, 0x0, 0x303305D8, 0x0, 0x3033045C
539#define IOMUXC_ECSPI1_SCLK_UART3_RX 0x303301F4, 0x1, 0x30330504, 0x0, 0x3033045C
540#define IOMUXC_ECSPI1_SCLK_UART3_TX 0x303301F4, 0x1, 0x00000000, 0x0, 0x3033045C
541#define IOMUXC_ECSPI1_SCLK_I2C1_SCL 0x303301F4, 0x2, 0x3033055C, 0x2, 0x3033045C
542#define IOMUXC_ECSPI1_SCLK_SAI5_RX_SYNC 0x303301F4, 0x3, 0x303304E4, 0x3, 0x3033045C
543#define IOMUXC_ECSPI1_SCLK_GPIO5_IO06 0x303301F4, 0x5, 0x00000000, 0x0, 0x3033045C
544#define IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x303301F8, 0x0, 0x303305A8, 0x0, 0x30330460
545#define IOMUXC_ECSPI1_MOSI_UART3_TX 0x303301F8, 0x1, 0x00000000, 0x0, 0x30330460
546#define IOMUXC_ECSPI1_MOSI_UART3_RX 0x303301F8, 0x1, 0x30330504, 0x1, 0x30330460
547#define IOMUXC_ECSPI1_MOSI_I2C1_SDA 0x303301F8, 0x2, 0x3033056C, 0x2, 0x30330460
548#define IOMUXC_ECSPI1_MOSI_SAI5_RX_BCLK 0x303301F8, 0x3, 0x303304D0, 0x3, 0x30330460
549#define IOMUXC_ECSPI1_MOSI_GPIO5_IO07 0x303301F8, 0x5, 0x00000000, 0x0, 0x30330460
550#define IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x303301FC, 0x0, 0x303305C4, 0x0, 0x30330464
551#define IOMUXC_ECSPI1_MISO_UART3_CTS_B 0x303301FC, 0x1, 0x00000000, 0x0, 0x30330464
552#define IOMUXC_ECSPI1_MISO_UART3_RTS_B 0x303301FC, 0x1, 0x30330500, 0x0, 0x30330464
553#define IOMUXC_ECSPI1_MISO_I2C2_SCL 0x303301FC, 0x2, 0x303305D0, 0x2, 0x30330464
554#define IOMUXC_ECSPI1_MISO_SAI5_RX_DATA0 0x303301FC, 0x3, 0x303304D4, 0x3, 0x30330464
555#define IOMUXC_ECSPI1_MISO_GPIO5_IO08 0x303301FC, 0x5, 0x00000000, 0x0, 0x30330464
556#define IOMUXC_ECSPI1_SS0_ECSPI1_SS0 0x30330200, 0x0, 0x30330564, 0x0, 0x30330468
557#define IOMUXC_ECSPI1_SS0_UART3_RTS_B 0x30330200, 0x1, 0x30330500, 0x1, 0x30330468
558#define IOMUXC_ECSPI1_SS0_UART3_CTS_B 0x30330200, 0x1, 0x00000000, 0x0, 0x30330468
559#define IOMUXC_ECSPI1_SS0_I2C2_SDA 0x30330200, 0x2, 0x30330560, 0x2, 0x30330468
560#define IOMUXC_ECSPI1_SS0_SAI5_RX_DATA1 0x30330200, 0x3, 0x303304D8, 0x2, 0x30330468
561#define IOMUXC_ECSPI1_SS0_SAI5_TX_SYNC 0x30330200, 0x4, 0x303304EC, 0x3, 0x30330468
562#define IOMUXC_ECSPI1_SS0_GPIO5_IO09 0x30330200, 0x5, 0x00000000, 0x0, 0x30330468
563#define IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x30330204, 0x0, 0x30330580, 0x0, 0x3033046C
564#define IOMUXC_ECSPI2_SCLK_UART4_RX 0x30330204, 0x1, 0x3033050C, 0x0, 0x3033046C
565#define IOMUXC_ECSPI2_SCLK_UART4_TX 0x30330204, 0x1, 0x00000000, 0x0, 0x3033046C
566#define IOMUXC_ECSPI2_SCLK_I2C3_SCL 0x30330204, 0x2, 0x30330588, 0x4, 0x3033046C
567#define IOMUXC_ECSPI2_SCLK_SAI5_RX_DATA2 0x30330204, 0x3, 0x303304DC, 0x2, 0x3033046C
568#define IOMUXC_ECSPI2_SCLK_SAI5_TX_BCLK 0x30330204, 0x4, 0x303304E8, 0x3, 0x3033046C
569#define IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x30330204, 0x5, 0x00000000, 0x0, 0x3033046C
570#define IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x30330208, 0x0, 0x30330590, 0x0, 0x30330470
571#define IOMUXC_ECSPI2_MOSI_UART4_TX 0x30330208, 0x1, 0x00000000, 0x0, 0x30330470
572#define IOMUXC_ECSPI2_MOSI_UART4_RX 0x30330208, 0x1, 0x3033050C, 0x1, 0x30330470
573#define IOMUXC_ECSPI2_MOSI_I2C3_SDA 0x30330208, 0x2, 0x303305BC, 0x4, 0x30330470
574#define IOMUXC_ECSPI2_MOSI_SAI5_RX_DATA3 0x30330208, 0x3, 0x303304E0, 0x2, 0x30330470
575#define IOMUXC_ECSPI2_MOSI_SAI5_TX_DATA0 0x30330208, 0x4, 0x00000000, 0x0, 0x30330470
576#define IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x30330208, 0x5, 0x00000000, 0x0, 0x30330470
577#define IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x3033020C, 0x0, 0x30330578, 0x0, 0x30330474
578#define IOMUXC_ECSPI2_MISO_UART4_CTS_B 0x3033020C, 0x1, 0x00000000, 0x0, 0x30330474
579#define IOMUXC_ECSPI2_MISO_UART4_RTS_B 0x3033020C, 0x1, 0x30330508, 0x0, 0x30330474
580#define IOMUXC_ECSPI2_MISO_I2C4_SCL 0x3033020C, 0x2, 0x303305D4, 0x3, 0x30330474
581#define IOMUXC_ECSPI2_MISO_SAI5_MCLK 0x3033020C, 0x3, 0x30330594, 0x4, 0x30330474
582#define IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x3033020C, 0x5, 0x00000000, 0x0, 0x30330474
583#define IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x30330210, 0x0, 0x30330570, 0x0, 0x30330478
584#define IOMUXC_ECSPI2_SS0_UART4_RTS_B 0x30330210, 0x1, 0x30330508, 0x1, 0x30330478
585#define IOMUXC_ECSPI2_SS0_UART4_CTS_B 0x30330210, 0x1, 0x00000000, 0x0, 0x30330478
586#define IOMUXC_ECSPI2_SS0_I2C4_SDA 0x30330210, 0x2, 0x3033058C, 0x5, 0x30330478
587#define IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x30330210, 0x5, 0x00000000, 0x0, 0x30330478
588#define IOMUXC_I2C1_SCL_I2C1_SCL 0x30330214, 0x0, 0x3033055C, 0x0, 0x3033047C
589#define IOMUXC_I2C1_SCL_ENET1_MDC 0x30330214, 0x1, 0x00000000, 0x0, 0x3033047C
590#define IOMUXC_I2C1_SCL_ECSPI1_SCLK 0x30330214, 0x3, 0x303305D8, 0x1, 0x3033047C
591#define IOMUXC_I2C1_SCL_GPIO5_IO14 0x30330214, 0x5, 0x00000000, 0x0, 0x3033047C
592#define IOMUXC_I2C1_SDA_I2C1_SDA 0x30330218, 0x0, 0x3033056C, 0x0, 0x30330480
593#define IOMUXC_I2C1_SDA_ENET1_MDIO 0x30330218, 0x1, 0x303304C0, 0x2, 0x30330480
594#define IOMUXC_I2C1_SDA_ECSPI1_MOSI 0x30330218, 0x3, 0x303305A8, 0x1, 0x30330480
595#define IOMUXC_I2C1_SDA_GPIO5_IO15 0x30330218, 0x5, 0x00000000, 0x0, 0x30330480
596#define IOMUXC_I2C2_SCL_I2C2_SCL 0x3033021C, 0x0, 0x303305D0, 0x0, 0x30330484
597#define IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN 0x3033021C, 0x1, 0x00000000, 0x0, 0x30330484
598#define IOMUXC_I2C2_SCL_USDHC3_CD_B 0x3033021C, 0x2, 0x30330598, 0x1, 0x30330484
599#define IOMUXC_I2C2_SCL_ECSPI1_MISO 0x3033021C, 0x3, 0x303305C4, 0x1, 0x30330484
600#define IOMUXC_I2C2_SCL_GPIO5_IO16 0x3033021C, 0x5, 0x00000000, 0x0, 0x30330484
601#define IOMUXC_I2C2_SDA_I2C2_SDA 0x30330220, 0x0, 0x30330560, 0x0, 0x30330488
602#define IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT 0x30330220, 0x1, 0x00000000, 0x0, 0x30330488
603#define IOMUXC_I2C2_SDA_USDHC3_WP 0x30330220, 0x2, 0x303305B8, 0x1, 0x30330488
604#define IOMUXC_I2C2_SDA_ECSPI1_SS0 0x30330220, 0x3, 0x30330564, 0x1, 0x30330488
605#define IOMUXC_I2C2_SDA_GPIO5_IO17 0x30330220, 0x5, 0x00000000, 0x0, 0x30330488
606#define IOMUXC_I2C3_SCL_I2C3_SCL 0x30330224, 0x0, 0x30330588, 0x0, 0x3033048C
607#define IOMUXC_I2C3_SCL_PWM4_OUT 0x30330224, 0x1, 0x00000000, 0x0, 0x3033048C
608#define IOMUXC_I2C3_SCL_GPT2_CLK 0x30330224, 0x2, 0x00000000, 0x0, 0x3033048C
609#define IOMUXC_I2C3_SCL_ECSPI2_SCLK 0x30330224, 0x3, 0x30330580, 0x2, 0x3033048C
610#define IOMUXC_I2C3_SCL_GPIO5_IO18 0x30330224, 0x5, 0x00000000, 0x0, 0x3033048C
611#define IOMUXC_I2C3_SDA_I2C3_SDA 0x30330228, 0x0, 0x303305BC, 0x0, 0x30330490
612#define IOMUXC_I2C3_SDA_PWM3_OUT 0x30330228, 0x1, 0x00000000, 0x0, 0x30330490
613#define IOMUXC_I2C3_SDA_GPT3_CLK 0x30330228, 0x2, 0x00000000, 0x0, 0x30330490
614#define IOMUXC_I2C3_SDA_ECSPI2_MOSI 0x30330228, 0x3, 0x30330590, 0x2, 0x30330490
615#define IOMUXC_I2C3_SDA_GPIO5_IO19 0x30330228, 0x5, 0x00000000, 0x0, 0x30330490
616#define IOMUXC_I2C4_SCL_I2C4_SCL 0x3033022C, 0x0, 0x303305D4, 0x0, 0x30330494
617#define IOMUXC_I2C4_SCL_PWM2_OUT 0x3033022C, 0x1, 0x00000000, 0x0, 0x30330494
618#define IOMUXC_I2C4_SCL_ECSPI2_MISO 0x3033022C, 0x3, 0x30330578, 0x2, 0x30330494
619#define IOMUXC_I2C4_SCL_GPIO5_IO20 0x3033022C, 0x5, 0x00000000, 0x0, 0x30330494
620#define IOMUXC_I2C4_SDA_I2C4_SDA 0x30330230, 0x0, 0x3033058C, 0x0, 0x30330498
621#define IOMUXC_I2C4_SDA_PWM1_OUT 0x30330230, 0x1, 0x00000000, 0x0, 0x30330498
622#define IOMUXC_I2C4_SDA_ECSPI2_SS0 0x30330230, 0x3, 0x30330570, 0x1, 0x30330498
623#define IOMUXC_I2C4_SDA_GPIO5_IO21 0x30330230, 0x5, 0x00000000, 0x0, 0x30330498
624#define IOMUXC_UART1_RXD_UART1_RX 0x30330234, 0x0, 0x303304F4, 0x0, 0x3033049C
625#define IOMUXC_UART1_RXD_UART1_TX 0x30330234, 0x0, 0x00000000, 0x0, 0x3033049C
626#define IOMUXC_UART1_RXD_ECSPI3_SCLK 0x30330234, 0x1, 0x00000000, 0x0, 0x3033049C
627#define IOMUXC_UART1_RXD_GPIO5_IO22 0x30330234, 0x5, 0x00000000, 0x0, 0x3033049C
628#define IOMUXC_UART1_TXD_UART1_TX 0x30330238, 0x0, 0x00000000, 0x0, 0x303304A0
629#define IOMUXC_UART1_TXD_UART1_RX 0x30330238, 0x0, 0x303304F4, 0x1, 0x303304A0
630#define IOMUXC_UART1_TXD_ECSPI3_MOSI 0x30330238, 0x1, 0x00000000, 0x0, 0x303304A0
631#define IOMUXC_UART1_TXD_GPIO5_IO23 0x30330238, 0x5, 0x00000000, 0x0, 0x303304A0
632#define IOMUXC_UART2_RXD_UART2_RX 0x3033023C, 0x0, 0x303304FC, 0x0, 0x303304A4
633#define IOMUXC_UART2_RXD_UART2_TX 0x3033023C, 0x0, 0x00000000, 0x0, 0x303304A4
634#define IOMUXC_UART2_RXD_ECSPI3_MISO 0x3033023C, 0x1, 0x00000000, 0x0, 0x303304A4
635#define IOMUXC_UART2_RXD_GPT1_COMPARE3 0x3033023C, 0x3, 0x00000000, 0x0, 0x303304A4
636#define IOMUXC_UART2_RXD_GPIO5_IO24 0x3033023C, 0x5, 0x00000000, 0x0, 0x303304A4
637#define IOMUXC_UART2_TXD_UART2_TX 0x30330240, 0x0, 0x00000000, 0x0, 0x303304A8
638#define IOMUXC_UART2_TXD_UART2_RX 0x30330240, 0x0, 0x303304FC, 0x1, 0x303304A8
639#define IOMUXC_UART2_TXD_ECSPI3_SS0 0x30330240, 0x1, 0x00000000, 0x0, 0x303304A8
640#define IOMUXC_UART2_TXD_GPT1_COMPARE2 0x30330240, 0x3, 0x00000000, 0x0, 0x303304A8
641#define IOMUXC_UART2_TXD_GPIO5_IO25 0x30330240, 0x5, 0x00000000, 0x0, 0x303304A8
642#define IOMUXC_UART3_RXD_UART3_RX 0x30330244, 0x0, 0x30330504, 0x2, 0x303304AC
643#define IOMUXC_UART3_RXD_UART3_TX 0x30330244, 0x0, 0x00000000, 0x0, 0x303304AC
644#define IOMUXC_UART3_RXD_UART1_CTS_B 0x30330244, 0x1, 0x00000000, 0x0, 0x303304AC
645#define IOMUXC_UART3_RXD_UART1_RTS_B 0x30330244, 0x1, 0x303304F0, 0x0, 0x303304AC
646#define IOMUXC_UART3_RXD_USDHC3_RESET_B 0x30330244, 0x2, 0x00000000, 0x0, 0x303304AC
647#define IOMUXC_UART3_RXD_GPT1_CAPTURE2 0x30330244, 0x3, 0x303305EC, 0x1, 0x303304AC
648#define IOMUXC_UART3_RXD_GPIO5_IO26 0x30330244, 0x5, 0x00000000, 0x0, 0x303304AC
649#define IOMUXC_UART3_TXD_UART3_TX 0x30330248, 0x0, 0x00000000, 0x0, 0x303304B0
650#define IOMUXC_UART3_TXD_UART3_RX 0x30330248, 0x0, 0x30330504, 0x3, 0x303304B0
651#define IOMUXC_UART3_TXD_UART1_RTS_B 0x30330248, 0x1, 0x303304F0, 0x1, 0x303304B0
652#define IOMUXC_UART3_TXD_UART1_CTS_B 0x30330248, 0x1, 0x00000000, 0x0, 0x303304B0
653#define IOMUXC_UART3_TXD_USDHC3_VSELECT 0x30330248, 0x2, 0x00000000, 0x0, 0x303304B0
654#define IOMUXC_UART3_TXD_GPT1_CLK 0x30330248, 0x3, 0x303305E8, 0x1, 0x303304B0
655#define IOMUXC_UART3_TXD_GPIO5_IO27 0x30330248, 0x5, 0x00000000, 0x0, 0x303304B0
656#define IOMUXC_UART4_RXD_UART4_RX 0x3033024C, 0x0, 0x3033050C, 0x2, 0x303304B4
657#define IOMUXC_UART4_RXD_UART4_TX 0x3033024C, 0x0, 0x00000000, 0x0, 0x303304B4
658#define IOMUXC_UART4_RXD_UART2_CTS_B 0x3033024C, 0x1, 0x00000000, 0x0, 0x303304B4
659#define IOMUXC_UART4_RXD_UART2_RTS_B 0x3033024C, 0x1, 0x303304F8, 0x0, 0x303304B4
660#define IOMUXC_UART4_RXD_GPT1_COMPARE1 0x3033024C, 0x3, 0x00000000, 0x0, 0x303304B4
661#define IOMUXC_UART4_RXD_GPIO5_IO28 0x3033024C, 0x5, 0x00000000, 0x0, 0x303304B4
662#define IOMUXC_UART4_TXD_UART4_TX 0x30330250, 0x0, 0x00000000, 0x0, 0x303304B8
663#define IOMUXC_UART4_TXD_UART4_RX 0x30330250, 0x0, 0x3033050C, 0x3, 0x303304B8
664#define IOMUXC_UART4_TXD_UART2_RTS_B 0x30330250, 0x1, 0x303304F8, 0x1, 0x303304B8
665#define IOMUXC_UART4_TXD_UART2_CTS_B 0x30330250, 0x1, 0x00000000, 0x0, 0x303304B8
666#define IOMUXC_UART4_TXD_GPT1_CAPTURE1 0x30330250, 0x3, 0x303305F0, 0x1, 0x303304B8
667#define IOMUXC_UART4_TXD_GPIO5_IO29 0x30330250, 0x5, 0x00000000, 0x0, 0x303304B8
668
669/*@}*/
670
671#if defined(__cplusplus)
672extern "C" {
673#endif /*__cplusplus */
674
675/*! @name Configuration */
676/*@{*/
677
678/*!
679 * @brief Sets the IOMUXC pin mux mode.
680 * @note The first five parameters can be filled with the pin function ID macros.
681 *
682 * This is an example to set the I2C4_SDA as the pwm1_OUT:
683 * @code
684 * IOMUXC_SetPinMux(IOMUXC_I2C4_SDA_PWM1_OUT, 0);
685 * @endcode
686 *
687 *
688 * @param muxRegister The pin mux register_
689 * @param muxMode The pin mux mode_
690 * @param inputRegister The select input register_
691 * @param inputDaisy The input daisy_
692 * @param configRegister The config register_
693 * @param inputOnfield The pad->module input inversion_
694 */
695static inline void IOMUXC_SetPinMux(uint32_t muxRegister,
696 uint32_t muxMode,
697 uint32_t inputRegister,
698 uint32_t inputDaisy,
699 uint32_t configRegister,
700 uint32_t inputOnfield)
701{
702 *((volatile uint32_t *)muxRegister) =
703 IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield);
704
705 if (inputRegister)
706 {
707 *((volatile uint32_t *)inputRegister) = IOMUXC_SELECT_INPUT_DAISY(inputDaisy);
708 }
709}
710/*!
711 * @brief Sets the IOMUXC pin configuration.
712 * @note The previous five parameters can be filled with the pin function ID macros.
713 *
714 * This is an example to set pin configuration for IOMUXC_I2C4_SDA_PWM1_OUT:
715 * @code
716 * IOMUXC_SetPinConfig(IOMUXC_I2C4_SDA_PWM1_OUT, IOMUXC_SW_PAD_CTL_PAD_ODE_MASK | IOMUXC0_SW_PAD_CTL_PAD_DSE(2U))
717 * @endcode
718 *
719 * @param muxRegister The pin mux register_
720 * @param muxMode The pin mux mode_
721 * @param inputRegister The select input register_
722 * @param inputDaisy The input daisy_
723 * @param configRegister The config register_
724 * @param configValue The pin config value_
725 */
726static inline void IOMUXC_SetPinConfig(uint32_t muxRegister,
727 uint32_t muxMode,
728 uint32_t inputRegister,
729 uint32_t inputDaisy,
730 uint32_t configRegister,
731 uint32_t configValue)
732{
733 if (configRegister)
734 {
735 *((volatile uint32_t *)configRegister) = configValue;
736 }
737}
738/*@}*/
739
740#if defined(__cplusplus)
741}
742#endif /*__cplusplus */
743
744/*! @}*/
745
746#endif /* _FSL_IOMUXC_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/drivers/fsl_memory.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/drivers/fsl_memory.h
new file mode 100644
index 000000000..53db17c39
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN4/drivers/fsl_memory.h
@@ -0,0 +1,146 @@
1/*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_MEMORY_H_
9#define _FSL_MEMORY_H_
10
11#include "fsl_common.h"
12
13/*******************************************************************************
14 * Definitions
15 ******************************************************************************/
16/* Component ID definition, used by tools. */
17#ifndef FSL_COMPONENT_ID
18#define FSL_COMPONENT_ID "platform.drivers.memory"
19#endif
20
21/*! @name Driver version */
22/*@{*/
23/*! @brief IMEMORY driver version 2.0.0. */
24#define FSL_MEMORY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
25/*@}*/
26
27/* The CM7 subsystem local ITCM start address, refer to Reference Manual for detailed information */
28#define FSL_MEM_M7_ITCM_BEGIN 0x00000000U
29/* The CM7 subsystem local ITCM end address, refer to Reference Manual for detailed information */
30#define FSL_MEM_M7_ITCM_END 0x0001FFFFU
31
32/* The CM7 subsystem local DTCM start address, refer to Reference Manual for detailed information */
33#define FSL_MEM_M7_DTCM_BEGIN 0x20000000U
34/* The CM7 subsystem local DTCM end address, refer to Reference Manual for detailed information */
35#define FSL_MEM_M7_DTCM_END 0x2001FFFFU
36
37/* The CM7 subsystem local OCRAM start address, refer to Reference Manual for detailed information */
38#define FSL_MEM_M7_OCRAM_BEGIN 0x20200000U
39/* The CM7 subsystem local OCRAM end address, refer to Reference Manual for detailed information */
40#define FSL_MEM_M7_OCRAM_END 0x2021FFFFU
41
42/* The CM7 subsystem local OCRAMS start address, refer to Reference Manual for detailed information */
43#define FSL_MEM_M7_OCRAMS_BEGIN 0x20180000U
44/* The CM7 subsystem local OCRAMS end address, refer to Reference Manual for detailed information */
45#define FSL_MEM_M7_OCRAMS_END 0x20187FFFU
46
47/* System level ITCM memory address = CM7 subsystem local ITCM address + FSL_FEATURE_ITCM_OFFSET */
48#define FSL_MEM_M7_ITCM_OFFSET (0x7E0000U)
49/* System level DTCM memory address = CM7 subsystem local DTCM address - FSL_FEATURE_DTCM_OFFSET */
50#define FSL_MEM_M7_DTCM_OFFSET 0x1F800000U
51/* System level OCRAM memory address = CM7 subsystem local OCRAM address - FSL_MEM_M7_OCRAM_OFFSET */
52#define FSL_MEM_M7_OCRAM_OFFSET 0x1F900000U
53/* System level OCRAMS memory address = CM7 subsystem local OCRAMS address - FSL_MEM_M7_OCRAMS_OFFSET */
54#define FSL_MEM_M7_OCRAMS_OFFSET 0x20000000U
55
56typedef enum _mem_direction
57{
58 kMEMORY_Local2DMA = 0,
59 kMEMORY_DMA2Local,
60} mem_direction_t;
61
62/*******************************************************************************
63 * API
64 ******************************************************************************/
65#if defined(__cplusplus)
66extern "C" {
67#endif
68/*!
69 * @brief Convert the memory map address.
70 *
71 * This function convert the address between system mapped address and native mapped address.
72 * There maybe offset between subsystem native address and system address for some memory,
73 * this funciton convert the address to different memory map.
74 * @param addr address need to be converted.
75 * @param direction convert direction.
76 * @return the converted address
77 */
78static inline uint32_t MEMORY_ConvertMemoryMapAddress(uint32_t addr, mem_direction_t direction)
79{
80 uint32_t dest;
81
82 switch (direction)
83 {
84 case kMEMORY_Local2DMA:
85 {
86 if ((addr <= FSL_MEM_M7_ITCM_END))
87 {
88 dest = addr + FSL_MEM_M7_ITCM_OFFSET;
89 }
90 else if ((addr >= FSL_MEM_M7_DTCM_BEGIN) && (addr <= FSL_MEM_M7_DTCM_END))
91 {
92 dest = addr - FSL_MEM_M7_DTCM_OFFSET;
93 }
94 else if ((addr >= FSL_MEM_M7_OCRAM_BEGIN) && (addr <= FSL_MEM_M7_OCRAM_END))
95 {
96 dest = addr - FSL_MEM_M7_OCRAM_OFFSET;
97 }
98 else if ((addr >= FSL_MEM_M7_OCRAMS_BEGIN) && (addr <= FSL_MEM_M7_OCRAMS_END))
99 {
100 dest = addr - FSL_MEM_M7_OCRAMS_OFFSET;
101 }
102 else
103 {
104 dest = addr;
105 }
106 break;
107 }
108 case kMEMORY_DMA2Local:
109 {
110 if ((addr >= (FSL_MEM_M7_ITCM_BEGIN + FSL_MEM_M7_ITCM_OFFSET)) &&
111 (addr <= (FSL_MEM_M7_ITCM_END + FSL_MEM_M7_ITCM_OFFSET)))
112 {
113 dest = addr - FSL_MEM_M7_ITCM_OFFSET;
114 }
115 else if ((addr >= (FSL_MEM_M7_DTCM_BEGIN - FSL_MEM_M7_DTCM_OFFSET)) &&
116 (addr <= (FSL_MEM_M7_DTCM_END - FSL_MEM_M7_DTCM_OFFSET)))
117 {
118 dest = addr + FSL_MEM_M7_DTCM_OFFSET;
119 }
120 else if ((addr >= (FSL_MEM_M7_OCRAM_BEGIN - FSL_MEM_M7_OCRAM_OFFSET)) &&
121 (addr <= (FSL_MEM_M7_OCRAM_END - FSL_MEM_M7_OCRAM_OFFSET)))
122 {
123 dest = addr + FSL_MEM_M7_OCRAM_OFFSET;
124 }
125 else if ((addr >= (FSL_MEM_M7_OCRAMS_BEGIN - FSL_MEM_M7_OCRAMS_OFFSET)) &&
126 (addr <= (FSL_MEM_M7_OCRAMS_END - FSL_MEM_M7_OCRAMS_OFFSET)))
127 {
128 dest = addr + FSL_MEM_M7_OCRAMS_OFFSET;
129 }
130 else
131 {
132 dest = addr;
133 }
134 break;
135 }
136 default:
137 dest = addr;
138 break;
139 }
140
141 return dest;
142}
143#if defined(__cplusplus)
144}
145#endif /* __cplusplus */
146#endif /* _FSL_MEMORY_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 17:59:06 +0100