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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN5/drivers/fsl_clock.h1254
1 files changed, 1254 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN5/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN5/drivers/fsl_clock.h
new file mode 100644
index 000000000..3aa6c538b
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MN5/drivers/fsl_clock.h
@@ -0,0 +1,1254 @@
1/*
2 * Copyright 2018 -2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CLOCK_H_
9#define _FSL_CLOCK_H_
10
11#include "fsl_device_registers.h"
12#include "fsl_common.h"
13#include <stdint.h>
14#include <stdbool.h>
15#include <stddef.h>
16#include <assert.h>
17
18/*!
19 * @addtogroup clock
20 * @{
21 */
22
23/*******************************************************************************
24 * Definitions
25 ******************************************************************************/
26
27/*! @name Driver version */
28/*@{*/
29/*! @brief CLOCK driver version 2.2.2. */
30#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))
31/*@}*/
32
33/* Definition for delay API in clock driver, users can redefine it to the real application. */
34#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
35#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL)
36#endif
37
38/*!
39 * @brief XTAL 24M clock frequency.
40 */
41#define OSC24M_CLK_FREQ 24000000U
42/*!
43 * @brief pad clock frequency.
44 */
45#define CLKPAD_FREQ 0U
46
47/*! @brief Clock ip name array for ECSPI. */
48#define ECSPI_CLOCKS \
49 { \
50 kCLOCK_IpInvalid, kCLOCK_Ecspi1, kCLOCK_Ecspi2, kCLOCK_Ecspi3, \
51 }
52
53/*! @brief Clock ip name array for GPIO. */
54#define GPIO_CLOCKS \
55 { \
56 kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5, \
57 }
58
59/*! @brief Clock ip name array for GPT. */
60#define GPT_CLOCKS \
61 { \
62 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2, kCLOCK_Gpt3, kCLOCK_Gpt4, kCLOCK_Gpt5, kCLOCK_Gpt6, \
63 }
64
65/*! @brief Clock ip name array for I2C. */
66#define I2C_CLOCKS \
67 { \
68 kCLOCK_IpInvalid, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, kCLOCK_I2c4, \
69 }
70
71/*! @brief Clock ip name array for IOMUX. */
72#define IOMUX_CLOCKS \
73 { \
74 kCLOCK_Iomux, \
75 }
76
77/*! @brief Clock ip name array for IPMUX. */
78#define IPMUX_CLOCKS \
79 { \
80 kCLOCK_Ipmux1, kCLOCK_Ipmux2, kCLOCK_Ipmux3, kCLOCK_Ipmux4, \
81 }
82
83/*! @brief Clock ip name array for PWM. */
84#define PWM_CLOCKS \
85 { \
86 kCLOCK_IpInvalid, kCLOCK_Pwm1, kCLOCK_Pwm2, kCLOCK_Pwm3, kCLOCK_Pwm4, \
87 }
88
89/*! @brief Clock ip name array for RDC. */
90#define RDC_CLOCKS \
91 { \
92 kCLOCK_Rdc, \
93 }
94
95/*! @brief Clock ip name array for SAI. */
96#define SAI_CLOCKS \
97 { \
98 kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Sai2, kCLOCK_Sai3, kCLOCK_IpInvalid, kCLOCK_Sai5, kCLOCK_Sai6, \
99 kCLOCK_Sai7 \
100 }
101
102/*! @brief Clock ip name array for RDC SEMA42. */
103#define RDC_SEMA42_CLOCKS \
104 { \
105 kCLOCK_IpInvalid, kCLOCK_Sema42_1, kCLOCK_Sema42_2 \
106 }
107
108/*! @brief Clock ip name array for UART. */
109#define UART_CLOCKS \
110 { \
111 kCLOCK_IpInvalid, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4, \
112 }
113
114/*! @brief Clock ip name array for USDHC. */
115#define USDHC_CLOCKS \
116 { \
117 kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2, kCLOCK_Usdhc3 \
118 }
119
120/*! @brief Clock ip name array for WDOG. */
121#define WDOG_CLOCKS \
122 { \
123 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2, kCLOCK_Wdog3 \
124 }
125
126/*! @brief Clock ip name array for TEMPSENSOR. */
127#define TMU_CLOCKS \
128 { \
129 kCLOCK_TempSensor, \
130 }
131
132/*! @brief Clock ip name array for SDMA. */
133#define SDMA_CLOCKS \
134 { \
135 kCLOCK_Sdma1, kCLOCK_Sdma2, kCLOCK_Sdma3 \
136 }
137
138/*! @brief Clock ip name array for MU. */
139#define MU_CLOCKS \
140 { \
141 kCLOCK_Mu \
142 }
143
144/*! @brief Clock ip name array for QSPI. */
145#define QSPI_CLOCKS \
146 { \
147 kCLOCK_Qspi \
148 }
149
150/*! @brief Clock ip name array for PDM. */
151#define PDM_CLOCKS \
152 { \
153 kCLOCK_Pdm \
154 }
155
156/*! @brief Clock ip name array for ASRC. */
157#define ASRC_CLOCKS \
158 { \
159 kCLOCK_Asrc \
160 }
161
162/*!
163 * @brief CCM reg macros to extract corresponding registers bit field.
164 */
165#define CCM_BIT_FIELD_EXTRACTION(val, mask, shift) (((val) & (mask)) >> (shift))
166
167/*!
168 * @brief CCM reg macros to map corresponding registers.
169 */
170#define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uint32_t)(root) + (off))))
171#define CCM_REG(root) CCM_REG_OFF(root, 0U)
172#define CCM_REG_SET(root) CCM_REG_OFF(root, 4U)
173#define CCM_REG_CLR(root) CCM_REG_OFF(root, 8U)
174
175/*!
176 * @brief CCM Analog registers offset.
177 */
178#define AUDIO_PLL1_GEN_CTRL_OFFSET 0x00
179#define AUDIO_PLL2_GEN_CTRL_OFFSET 0x14
180#define VIDEO_PLL1_GEN_CTRL_OFFSET 0x28
181#define GPU_PLL_GEN_CTRL_OFFSET 0x64
182#define VPU_PLL_GEN_CTRL_OFFSET 0x74
183#define ARM_PLL_GEN_CTRL_OFFSET 0x84
184#define SYS_PLL1_GEN_CTRL_OFFSET 0x94
185#define SYS_PLL2_GEN_CTRL_OFFSET 0x104
186#define SYS_PLL3_GEN_CTRL_OFFSET 0x114
187#define DRAM_PLL_GEN_CTRL_OFFSET 0x50
188
189/*!
190 * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
191 */
192#define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFFU) << 16U) | ((shift)))
193#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)(tuple)) & 0x1FU)
194#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
195 (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFFU) + (off))))
196#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
197
198/*!
199 * @brief CCM CCGR and root tuple
200 */
201#define CCM_TUPLE(ccgr, root) ((ccgr) << 16U | (root))
202#define CCM_TUPLE_CCGR(tuple) ((uint32_t)(&(CCM)->CCGR[(uint32_t)(tuple) >> 16U].CCGR))
203#define CCM_TUPLE_ROOT(tuple) ((uint32_t)(&(CCM)->ROOT[(uint32_t)(tuple)&0xFFFFU].TARGET_ROOT))
204
205/*! @brief Clock name used to get clock frequency. */
206typedef enum _clock_name
207{
208 kCLOCK_CoreM7Clk, /*!< ARM M7 Core clock */
209
210 kCLOCK_AxiClk, /*!< Main AXI bus clock. */
211 kCLOCK_AhbClk, /*!< AHB bus clock. */
212 kCLOCK_IpgClk, /*!< IPG bus clock. */
213
214 /* -------------------------------- Other clock --------------------------*/
215} clock_name_t;
216
217#define kCLOCK_CoreSysClk kCLOCK_CoreM7Clk /*!< For compatible with other platforms without CCM. */
218#define CLOCK_GetCoreSysClkFreq CLOCK_GetCoreM7Freq /*!< For compatible with other platforms without CCM. */
219
220/*! @brief CCM CCGR gate control. */
221typedef enum _clock_ip_name
222{
223 kCLOCK_IpInvalid = -1,
224
225 kCLOCK_Debug = CCM_TUPLE(4U, 32U), /*!< DEBUG Clock Gate.*/
226
227 kCLOCK_Dram = CCM_TUPLE(5U, 64U), /*!< DRAM Clock Gate.*/
228
229 kCLOCK_Ecspi1 = CCM_TUPLE(7U, 101U), /*!< ECSPI1 Clock Gate.*/
230 kCLOCK_Ecspi2 = CCM_TUPLE(8U, 102U), /*!< ECSPI2 Clock Gate.*/
231 kCLOCK_Ecspi3 = CCM_TUPLE(9U, 131U), /*!< ECSPI3 Clock Gate.*/
232
233 kCLOCK_Gpio1 = CCM_TUPLE(11U, 33U), /*!< GPIO1 Clock Gate.*/
234 kCLOCK_Gpio2 = CCM_TUPLE(12U, 33U), /*!< GPIO2 Clock Gate.*/
235 kCLOCK_Gpio3 = CCM_TUPLE(13U, 33U), /*!< GPIO3 Clock Gate.*/
236 kCLOCK_Gpio4 = CCM_TUPLE(14U, 33U), /*!< GPIO4 Clock Gate.*/
237 kCLOCK_Gpio5 = CCM_TUPLE(15U, 33U), /*!< GPIO5 Clock Gate.*/
238
239 kCLOCK_Gpt1 = CCM_TUPLE(16U, 107U), /*!< GPT1 Clock Gate.*/
240 kCLOCK_Gpt2 = CCM_TUPLE(17U, 108U), /*!< GPT2 Clock Gate.*/
241 kCLOCK_Gpt3 = CCM_TUPLE(18U, 109U), /*!< GPT3 Clock Gate.*/
242 kCLOCK_Gpt4 = CCM_TUPLE(19U, 110U), /*!< GPT4 Clock Gate.*/
243 kCLOCK_Gpt5 = CCM_TUPLE(20U, 111U), /*!< GPT5 Clock Gate.*/
244 kCLOCK_Gpt6 = CCM_TUPLE(21U, 112U), /*!< GPT6 Clock Gate.*/
245
246 kCLOCK_I2c1 = CCM_TUPLE(23U, 90U), /*!< I2C1 Clock Gate.*/
247 kCLOCK_I2c2 = CCM_TUPLE(24U, 91U), /*!< I2C2 Clock Gate.*/
248 kCLOCK_I2c3 = CCM_TUPLE(25U, 92U), /*!< I2C3 Clock Gate.*/
249 kCLOCK_I2c4 = CCM_TUPLE(26U, 93U), /*!< I2C4 Clock Gate.*/
250
251 kCLOCK_Iomux = CCM_TUPLE(27U, 33U), /*!< IOMUX Clock Gate.*/
252 kCLOCK_Ipmux1 = CCM_TUPLE(28U, 33U), /*!< IPMUX1 Clock Gate.*/
253 kCLOCK_Ipmux2 = CCM_TUPLE(29U, 33U), /*!< IPMUX2 Clock Gate.*/
254 kCLOCK_Ipmux3 = CCM_TUPLE(30U, 33U), /*!< IPMUX3 Clock Gate.*/
255 kCLOCK_Ipmux4 = CCM_TUPLE(31U, 33U), /*!< IPMUX4 Clock Gate.*/
256
257 kCLOCK_Mu = CCM_TUPLE(33U, 33U), /*!< MU Clock Gate.*/
258
259 kCLOCK_Ocram = CCM_TUPLE(35U, 16U), /*!< OCRAM Clock Gate.*/
260 kCLOCK_OcramS = CCM_TUPLE(36U, 32U), /*!< OCRAM S Clock Gate.*/
261
262 kCLOCK_Pwm1 = CCM_TUPLE(40U, 103U), /*!< PWM1 Clock Gate.*/
263 kCLOCK_Pwm2 = CCM_TUPLE(41U, 104U), /*!< PWM2 Clock Gate.*/
264 kCLOCK_Pwm3 = CCM_TUPLE(42U, 105U), /*!< PWM3 Clock Gate.*/
265 kCLOCK_Pwm4 = CCM_TUPLE(43U, 106U), /*!< PWM4 Clock Gate.*/
266
267 kCLOCK_Qspi = CCM_TUPLE(47U, 87U), /*!< QSPI Clock Gate.*/
268
269 kCLOCK_Rdc = CCM_TUPLE(49U, 33U), /*!< RDC Clock Gate.*/
270
271 kCLOCK_Sai2 = CCM_TUPLE(52U, 76U), /*!< SAI2 Clock Gate.*/
272 kCLOCK_Sai3 = CCM_TUPLE(53U, 77U), /*!< SAI3 Clock Gate.*/
273 kCLOCK_Sai5 = CCM_TUPLE(55U, 79U), /*!< SAI5 Clock Gate.*/
274 kCLOCK_Sai6 = CCM_TUPLE(56U, 80U), /*!< SAI6 Clock Gate.*/
275 kCLOCK_Sai7 = CCM_TUPLE(101U, 134U), /*!< SAI7 Clock Gate.*/
276
277 kCLOCK_Sdma1 = CCM_TUPLE(58U, 33U), /*!< SDMA1 Clock Gate.*/
278 kCLOCK_Sdma2 = CCM_TUPLE(59U, 35U), /*!< SDMA2 Clock Gate.*/
279
280 kCLOCK_Sec_Debug = CCM_TUPLE(60U, 33U), /*!< SEC_DEBUG Clock Gate.*/
281
282 kCLOCK_Sema42_1 = CCM_TUPLE(61U, 33U), /*!< RDC SEMA42 Clock Gate.*/
283 kCLOCK_Sema42_2 = CCM_TUPLE(62U, 33U), /*!< RDC SEMA42 Clock Gate.*/
284
285 kCLOCK_Sim_display = CCM_TUPLE(63U, 16U), /*!< SIM_Display Clock Gate.*/
286 kCLOCK_Sim_m = CCM_TUPLE(65U, 32U), /*!< SIM_M Clock Gate.*/
287 kCLOCK_Sim_main = CCM_TUPLE(66U, 16U), /*!< SIM_MAIN Clock Gate.*/
288 kCLOCK_Sim_s = CCM_TUPLE(67U, 32U), /*!< SIM_S Clock Gate.*/
289 kCLOCK_Sim_wakeup = CCM_TUPLE(68U, 32U), /*!< SIM_WAKEUP Clock Gate.*/
290
291 kCLOCK_Uart1 = CCM_TUPLE(73U, 94U), /*!< UART1 Clock Gate.*/
292 kCLOCK_Uart2 = CCM_TUPLE(74U, 95U), /*!< UART2 Clock Gate.*/
293 kCLOCK_Uart3 = CCM_TUPLE(75U, 96U), /*!< UART3 Clock Gate.*/
294 kCLOCK_Uart4 = CCM_TUPLE(76U, 97U), /*!< UART4 Clock Gate.*/
295
296 kCLOCK_Usdhc1 = CCM_TUPLE(81U, 88U), /*!< USDHC1 Clock Gate.*/
297 kCLOCK_Usdhc2 = CCM_TUPLE(82U, 89U), /*!< USDHC2 Clock Gate.*/
298 kCLOCK_Wdog1 = CCM_TUPLE(83U, 114U), /*!< WDOG1 Clock Gate.*/
299 kCLOCK_Wdog2 = CCM_TUPLE(84U, 114U), /*!< WDOG2 Clock Gate.*/
300 kCLOCK_Wdog3 = CCM_TUPLE(85U, 114U), /*!< WDOG3 Clock Gate.*/
301
302 kCLOCK_Asrc = CCM_TUPLE(88U, 33U), /*!< ASRC Clock Gate.*/
303 kCLOCK_Pdm = CCM_TUPLE(91U, 132U), /*!< PDM Clock Gate.*/
304 kCLOCK_Usdhc3 = CCM_TUPLE(94U, 121U), /*!< USDHC3 Clock Gate.*/
305 kCLOCK_Sdma3 = CCM_TUPLE(95U, 35U), /*!< SDMA3 Clock Gate.*/
306
307 kCLOCK_TempSensor = CCM_TUPLE(98U, 0xFFFF), /*!< TempSensor Clock Gate.*/
308
309} clock_ip_name_t;
310
311/*! @brief ccm root name used to get clock frequency. */
312typedef enum _clock_root_control
313{
314 kCLOCK_RootM7 = (uint32_t)(&(CCM)->ROOT[1].TARGET_ROOT), /*!< ARM Cortex-M7 Clock control name.*/
315 kCLOCK_RootAxi = (uint32_t)(&(CCM)->ROOT[16].TARGET_ROOT), /*!< AXI Clock control name.*/
316 kCLOCK_RootNoc = (uint32_t)(&(CCM)->ROOT[26].TARGET_ROOT), /*!< NOC Clock control name.*/
317 kCLOCK_RootAhb = (uint32_t)(&(CCM)->ROOT[32].TARGET_ROOT), /*!< AHB Clock control name.*/
318 kCLOCK_RootIpg = (uint32_t)(&(CCM)->ROOT[33].TARGET_ROOT), /*!< IPG Clock control name.*/
319 kCLOCK_RootAudioAhb = (uint32_t)(&(CCM)->ROOT[34].TARGET_ROOT), /*!< Audio AHB Clock control name.*/
320 kCLOCK_RootAudioIpg = (uint32_t)(&(CCM)->ROOT[35].TARGET_ROOT), /*!< Audio IPG Clock control name.*/
321 kCLOCK_RootDramAlt = (uint32_t)(&(CCM)->ROOT[64].TARGET_ROOT), /*!< DRAM ALT Clock control name.*/
322
323 kCLOCK_RootSai2 = (uint32_t)(&(CCM)->ROOT[76].TARGET_ROOT), /*!< SAI2 Clock control name.*/
324 kCLOCK_RootSai3 = (uint32_t)(&(CCM)->ROOT[77].TARGET_ROOT), /*!< SAI3 Clock control name.*/
325 kCLOCK_RootSai5 = (uint32_t)(&(CCM)->ROOT[79].TARGET_ROOT), /*!< SAI5 Clock control name.*/
326 kCLOCK_RootSai6 = (uint32_t)(&(CCM)->ROOT[80].TARGET_ROOT), /*!< SAI6 Clock control name.*/
327 kCLOCK_RootSai7 = (uint32_t)(&(CCM)->ROOT[134].TARGET_ROOT), /*!< SAI7 Clock control name.*/
328
329 kCLOCK_RootQspi = (uint32_t)(&(CCM)->ROOT[87].TARGET_ROOT), /*!< QSPI Clock control name.*/
330
331 kCLOCK_RootI2c1 = (uint32_t)(&(CCM)->ROOT[90].TARGET_ROOT), /*!< I2C1 Clock control name.*/
332 kCLOCK_RootI2c2 = (uint32_t)(&(CCM)->ROOT[91].TARGET_ROOT), /*!< I2C2 Clock control name.*/
333 kCLOCK_RootI2c3 = (uint32_t)(&(CCM)->ROOT[92].TARGET_ROOT), /*!< I2C3 Clock control name.*/
334 kCLOCK_RootI2c4 = (uint32_t)(&(CCM)->ROOT[93].TARGET_ROOT), /*!< I2C4 Clock control name.*/
335
336 kCLOCK_RootUart1 = (uint32_t)(&(CCM)->ROOT[94].TARGET_ROOT), /*!< UART1 Clock control name.*/
337 kCLOCK_RootUart2 = (uint32_t)(&(CCM)->ROOT[95].TARGET_ROOT), /*!< UART2 Clock control name.*/
338 kCLOCK_RootUart3 = (uint32_t)(&(CCM)->ROOT[96].TARGET_ROOT), /*!< UART3 Clock control name.*/
339 kCLOCK_RootUart4 = (uint32_t)(&(CCM)->ROOT[97].TARGET_ROOT), /*!< UART4 Clock control name.*/
340
341 kCLOCK_RootEcspi1 = (uint32_t)(&(CCM)->ROOT[101].TARGET_ROOT), /*!< ECSPI1 Clock control name.*/
342 kCLOCK_RootEcspi2 = (uint32_t)(&(CCM)->ROOT[102].TARGET_ROOT), /*!< ECSPI2 Clock control name.*/
343 kCLOCK_RootEcspi3 = (uint32_t)(&(CCM)->ROOT[131].TARGET_ROOT), /*!< ECSPI3 Clock control name.*/
344
345 kCLOCK_RootPwm1 = (uint32_t)(&(CCM)->ROOT[103].TARGET_ROOT), /*!< PWM1 Clock control name.*/
346 kCLOCK_RootPwm2 = (uint32_t)(&(CCM)->ROOT[104].TARGET_ROOT), /*!< PWM2 Clock control name.*/
347 kCLOCK_RootPwm3 = (uint32_t)(&(CCM)->ROOT[105].TARGET_ROOT), /*!< PWM3 Clock control name.*/
348 kCLOCK_RootPwm4 = (uint32_t)(&(CCM)->ROOT[106].TARGET_ROOT), /*!< PWM4 Clock control name.*/
349
350 kCLOCK_RootGpt1 = (uint32_t)(&(CCM)->ROOT[107].TARGET_ROOT), /*!< GPT1 Clock control name.*/
351 kCLOCK_RootGpt2 = (uint32_t)(&(CCM)->ROOT[108].TARGET_ROOT), /*!< GPT2 Clock control name.*/
352 kCLOCK_RootGpt3 = (uint32_t)(&(CCM)->ROOT[109].TARGET_ROOT), /*!< GPT3 Clock control name.*/
353 kCLOCK_RootGpt4 = (uint32_t)(&(CCM)->ROOT[110].TARGET_ROOT), /*!< GPT4 Clock control name.*/
354 kCLOCK_RootGpt5 = (uint32_t)(&(CCM)->ROOT[111].TARGET_ROOT), /*!< GPT5 Clock control name.*/
355 kCLOCK_RootGpt6 = (uint32_t)(&(CCM)->ROOT[112].TARGET_ROOT), /*!< GPT6 Clock control name.*/
356
357 kCLOCK_RootWdog = (uint32_t)(&(CCM)->ROOT[114].TARGET_ROOT), /*!< WDOG Clock control name.*/
358
359 kCLOCK_RootPdm = (uint32_t)(&(CCM)->ROOT[132].TARGET_ROOT), /*!< PDM Clock control name.*/
360
361} clock_root_control_t;
362
363/*! @brief Root clock select enumeration for ARM Cortex-M7 core. */
364typedef enum _clock_rootmux_m7_clk_sel
365{
366 kCLOCK_M7RootmuxOsc24M = 0U, /*!< ARM Cortex-M7 Clock from OSC 24M.*/
367 kCLOCK_M7RootmuxSysPll2Div5 = 1U, /*!< ARM Cortex-M7 Clock from SYSTEM PLL2 divided by 5.*/
368 kCLOCK_M7RootmuxSysPll2Div4 = 2U, /*!< ARM Cortex-M7 Clock from SYSTEM PLL2 divided by 4.*/
369 kCLOCK_M7RootmuxSysPll1Div3 = 3U, /*!< ARM Cortex-M7 Clock from SYSTEM PLL1 divided by 3.*/
370 kCLOCK_M7RootmuxSysPll1 = 4U, /*!< ARM Cortex-M7 Clock from SYSTEM PLL1.*/
371 kCLOCK_M7RootmuxAudioPll1 = 5U, /*!< ARM Cortex-M7 Clock from AUDIO PLL1.*/
372 kCLOCK_M7RootmuxVideoPll1 = 6U, /*!< ARM Cortex-M7 Clock from VIDEO PLL1.*/
373 kCLOCK_M7RootmuxSysPll3 = 7U, /*!< ARM Cortex-M7 Clock from SYSTEM PLL3.*/
374} clock_rootmux_m7_clk_sel_t;
375
376/*! @brief Root clock select enumeration for AXI bus. */
377typedef enum _clock_rootmux_axi_clk_sel
378{
379 kCLOCK_AxiRootmuxOsc24M = 0U, /*!< ARM AXI Clock from OSC 24M.*/
380 kCLOCK_AxiRootmuxSysPll2Div3 = 1U, /*!< ARM AXI Clock from SYSTEM PLL2 divided by 3.*/
381 kCLOCK_AxiRootmuxSysPll1 = 2U, /*!< ARM AXI Clock from SYSTEM PLL1.*/
382 kCLOCK_AxiRootmuxSysPll2Div4 = 3U, /*!< ARM AXI Clock from SYSTEM PLL2 divided by 4.*/
383 kCLOCK_AxiRootmuxSysPll2 = 4U, /*!< ARM AXI Clock from SYSTEM PLL2.*/
384 kCLOCK_AxiRootmuxAudioPll1 = 5U, /*!< ARM AXI Clock from AUDIO PLL1.*/
385 kCLOCK_AxiRootmuxVideoPll1 = 6U, /*!< ARM AXI Clock from VIDEO PLL1.*/
386 kCLOCK_AxiRootmuxSysPll1Div8 = 7U, /*!< ARM AXI Clock from SYSTEM PLL1 divided by 8.*/
387} clock_rootmux_axi_clk_sel_t;
388
389/*! @brief Root clock select enumeration for AHB bus. */
390typedef enum _clock_rootmux_ahb_clk_sel
391{
392 kCLOCK_AhbRootmuxOsc24M = 0U, /*!< ARM AHB Clock from OSC 24M.*/
393 kCLOCK_AhbRootmuxSysPll1Div6 = 1U, /*!< ARM AHB Clock from SYSTEM PLL1 divided by 6.*/
394 kCLOCK_AhbRootmuxSysPll1 = 2U, /*!< ARM AHB Clock from SYSTEM PLL1.*/
395 kCLOCK_AhbRootmuxSysPll1Div2 = 3U, /*!< ARM AHB Clock from SYSTEM PLL1 divided by 2.*/
396 kCLOCK_AhbRootmuxSysPll2Div8 = 4U, /*!< ARM AHB Clock from SYSTEM PLL2 divided by 8.*/
397 kCLOCK_AhbRootmuxSysPll3 = 5U, /*!< ARM AHB Clock from SYSTEM PLL3.*/
398 kCLOCK_AhbRootmuxAudioPll1 = 6U, /*!< ARM AHB Clock from AUDIO PLL1.*/
399 kCLOCK_AhbRootmuxVideoPll1 = 7U, /*!< ARM AHB Clock from VIDEO PLL1.*/
400} clock_rootmux_ahb_clk_sel_t;
401
402/*! @brief Root clock select enumeration for Audio AHB bus. */
403typedef enum _clock_rootmux_audio_ahb_clk_sel
404{
405 kCLOCK_AudioAhbRootmuxOsc24M = 0U, /*!< ARM Audio AHB Clock from OSC 24M.*/
406 kCLOCK_AudioAhbRootmuxSysPll2Div2 = 1U, /*!< ARM Audio AHB Clock from SYSTEM PLL2 divided by 2.*/
407 kCLOCK_AudioAhbRootmuxSysPll1 = 2U, /*!< ARM Audio AHB Clock from SYSTEM PLL1.*/
408 kCLOCK_AudioAhbRootmuxSysPll2 = 3U, /*!< ARM Audio AHB Clock from SYSTEM PLL2.*/
409 kCLOCK_AudioAhbRootmuxSysPll2Div6 = 4U, /*!< ARM Audio AHB Clock from SYSTEM PLL2 divided by 6.*/
410 kCLOCK_AudioAhbRootmuxSysPll3 = 5U, /*!< ARM Audio AHB Clock from SYSTEM PLL3.*/
411 kCLOCK_AudioAhbRootmuxAudioPll1 = 6U, /*!< ARM Audio AHB Clock from AUDIO PLL1.*/
412 kCLOCK_AudioAhbRootmuxVideoPll1 = 7U, /*!< ARM Audio AHB Clock from VIDEO PLL1.*/
413} clock_rootmux_audio_ahb_clk_sel_t;
414/*! @brief Root clock select enumeration for QSPI peripheral. */
415typedef enum _clock_rootmux_qspi_clk_sel
416{
417 kCLOCK_QspiRootmuxOsc24M = 0U, /*!< ARM QSPI Clock from OSC 24M.*/
418 kCLOCK_QspiRootmuxSysPll1Div2 = 1U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 2.*/
419 kCLOCK_QspiRootmuxSysPll2Div3 = 2U, /*!< ARM QSPI Clock from SYSTEM PLL2 divided by 3.*/
420 kCLOCK_QspiRootmuxSysPll2Div2 = 3U, /*!< ARM QSPI Clock from SYSTEM PLL2 divided by 2.*/
421 kCLOCK_QspiRootmuxAudioPll2 = 4U, /*!< ARM QSPI Clock from AUDIO PLL2.*/
422 kCLOCK_QspiRootmuxSysPll1Div3 = 5U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 3 */
423 kCLOCK_QspiRootmuxSysPll3 = 6, /*!< ARM QSPI Clock from SYSTEM PLL3.*/
424 kCLOCK_QspiRootmuxSysPll1Div8 = 7U, /*!< ARM QSPI Clock from SYSTEM PLL1 divided by 8.*/
425} clock_rootmux_qspi_clk_sel_t;
426
427/*! @brief Root clock select enumeration for ECSPI peripheral. */
428typedef enum _clock_rootmux_ecspi_clk_sel
429{
430 kCLOCK_EcspiRootmuxOsc24M = 0U, /*!< ECSPI Clock from OSC 24M.*/
431 kCLOCK_EcspiRootmuxSysPll2Div5 = 1U, /*!< ECSPI Clock from SYSTEM PLL2 divided by 5.*/
432 kCLOCK_EcspiRootmuxSysPll1Div20 = 2U, /*!< ECSPI Clock from SYSTEM PLL1 divided by 20.*/
433 kCLOCK_EcspiRootmuxSysPll1Div5 = 3U, /*!< ECSPI Clock from SYSTEM PLL1 divided by 5.*/
434 kCLOCK_EcspiRootmuxSysPll1 = 4U, /*!< ECSPI Clock from SYSTEM PLL1.*/
435 kCLOCK_EcspiRootmuxSysPll3 = 5U, /*!< ECSPI Clock from SYSTEM PLL3.*/
436 kCLOCK_EcspiRootmuxSysPll2Div4 = 6U, /*!< ECSPI Clock from SYSTEM PLL2 divided by 4.*/
437 kCLOCK_EcspiRootmuxAudioPll2 = 7U, /*!< ECSPI Clock from AUDIO PLL2.*/
438} clock_rootmux_ecspi_clk_sel_t;
439
440/*! @brief Root clock select enumeration for I2C peripheral. */
441typedef enum _clock_rootmux_i2c_clk_sel
442{
443 kCLOCK_I2cRootmuxOsc24M = 0U, /*!< I2C Clock from OSC 24M.*/
444 kCLOCK_I2cRootmuxSysPll1Div5 = 1U, /*!< I2C Clock from SYSTEM PLL1 divided by 5.*/
445 kCLOCK_I2cRootmuxSysPll2Div20 = 2U, /*!< I2C Clock from SYSTEM PLL2 divided by 20.*/
446 kCLOCK_I2cRootmuxSysPll3 = 3U, /*!< I2C Clock from SYSTEM PLL3 .*/
447 kCLOCK_I2cRootmuxAudioPll1 = 4U, /*!< I2C Clock from AUDIO PLL1.*/
448 kCLOCK_I2cRootmuxVideoPll1 = 5U, /*!< I2C Clock from VIDEO PLL1.*/
449 kCLOCK_I2cRootmuxAudioPll2 = 6U, /*!< I2C Clock from AUDIO PLL2.*/
450 kCLOCK_I2cRootmuxSysPll1Div6 = 7U, /*!< I2C Clock from SYSTEM PLL1 divided by 6.*/
451} clock_rootmux_i2c_clk_sel_t;
452
453/*! @brief Root clock select enumeration for UART peripheral. */
454typedef enum _clock_rootmux_uart_clk_sel
455{
456 kCLOCK_UartRootmuxOsc24M = 0U, /*!< UART Clock from OSC 24M.*/
457 kCLOCK_UartRootmuxSysPll1Div10 = 1U, /*!< UART Clock from SYSTEM PLL1 divided by 10.*/
458 kCLOCK_UartRootmuxSysPll2Div5 = 2U, /*!< UART Clock from SYSTEM PLL2 divided by 5.*/
459 kCLOCK_UartRootmuxSysPll2Div10 = 3U, /*!< UART Clock from SYSTEM PLL2 divided by 10.*/
460 kCLOCK_UartRootmuxSysPll3 = 4U, /*!< UART Clock from SYSTEM PLL3.*/
461 kCLOCK_UartRootmuxExtClk2 = 5U, /*!< UART Clock from External Clock 2.*/
462 kCLOCK_UartRootmuxExtClk34 = 6U, /*!< UART Clock from External Clock 3, External Clock 4.*/
463 kCLOCK_UartRootmuxAudioPll2 = 7U, /*!< UART Clock from Audio PLL2.*/
464} clock_rootmux_uart_clk_sel_t;
465
466/*! @brief Root clock select enumeration for GPT peripheral. */
467typedef enum _clock_rootmux_gpt
468{
469 kCLOCK_GptRootmuxOsc24M = 0U, /*!< GPT Clock from OSC 24M.*/
470 kCLOCK_GptRootmuxSystemPll2Div10 = 1U, /*!< GPT Clock from SYSTEM PLL2 divided by 10.*/
471 kCLOCK_GptRootmuxSysPll1Div2 = 2U, /*!< GPT Clock from SYSTEM PLL1 divided by 2.*/
472 kCLOCK_GptRootmuxSysPll1Div20 = 3U, /*!< GPT Clock from SYSTEM PLL1 divided by 20.*/
473 kCLOCK_GptRootmuxVideoPll1 = 4U, /*!< GPT Clock from VIDEO PLL1.*/
474 kCLOCK_GptRootmuxSystemPll1Div10 = 5U, /*!< GPT Clock from SYSTEM PLL1 divided by 10.*/
475 kCLOCK_GptRootmuxAudioPll1 = 6U, /*!< GPT Clock from AUDIO PLL1.*/
476 kCLOCK_GptRootmuxExtClk123 = 7U, /*!< GPT Clock from External Clock1, External Clock2, External Clock3.*/
477} clock_rootmux_gpt_t;
478
479/*! @brief Root clock select enumeration for WDOG peripheral. */
480typedef enum _clock_rootmux_wdog_clk_sel
481{
482 kCLOCK_WdogRootmuxOsc24M = 0U, /*!< WDOG Clock from OSC 24M.*/
483 kCLOCK_WdogRootmuxSysPll1Div6 = 1U, /*!< WDOG Clock from SYSTEM PLL1 divided by 6.*/
484 kCLOCK_WdogRootmuxSysPll1Div5 = 2U, /*!< WDOG Clock from SYSTEM PLL1 divided by 5.*/
485 kCLOCK_WdogRootmuxVpuPll = 3U, /*!< WDOG Clock from VPU DLL.*/
486 kCLOCK_WdogRootmuxSystemPll2Div8 = 4U, /*!< WDOG Clock from SYSTEM PLL2 divided by 8.*/
487 kCLOCK_WdogRootmuxSystemPll3 = 5U, /*!< WDOG Clock from SYSTEM PLL3.*/
488 kCLOCK_WdogRootmuxSystemPll1Div10 = 6U, /*!< WDOG Clock from SYSTEM PLL1 divided by 10.*/
489 kCLOCK_WdogRootmuxSystemPll2Div6 = 7U, /*!< WDOG Clock from SYSTEM PLL2 divided by 6.*/
490} clock_rootmux_wdog_clk_sel_t;
491
492/*! @brief Root clock select enumeration for PWM peripheral. */
493typedef enum _clock_rootmux_pwm_clk_sel
494{
495 kCLOCK_PwmRootmuxOsc24M = 0U, /*!< PWM Clock from OSC 24M.*/
496 kCLOCK_PwmRootmuxSysPll2Div10 = 1U, /*!< PWM Clock from SYSTEM PLL2 divided by 10.*/
497 kCLOCK_PwmRootmuxSysPll1Div5 = 2U, /*!< PWM Clock from SYSTEM PLL1 divided by 5.*/
498 kCLOCK_PwmRootmuxSysPll1Div20 = 3U, /*!< PWM Clock from SYSTEM PLL1 divided by 20.*/
499 kCLOCK_PwmRootmuxSystemPll3 = 4U, /*!< PWM Clock from SYSTEM PLL3.*/
500 kCLOCK_PwmRootmuxExtClk12 = 5U, /*!< PWM Clock from External Clock1, External Clock2.*/
501 kCLOCK_PwmRootmuxSystemPll1Div10 = 6U, /*!< PWM Clock from SYSTEM PLL1 divided by 10.*/
502 kCLOCK_PwmRootmuxVideoPll1 = 7U, /*!< PWM Clock from VIDEO PLL1.*/
503} clock_rootmux_Pwm_clk_sel_t;
504
505/*! @brief Root clock select enumeration for SAI peripheral. */
506typedef enum _clock_rootmux_sai_clk_sel
507{
508 kCLOCK_SaiRootmuxOsc24M = 0U, /*!< SAI Clock from OSC 24M.*/
509 kCLOCK_SaiRootmuxAudioPll1 = 1U, /*!< SAI Clock from AUDIO PLL1.*/
510 kCLOCK_SaiRootmuxAudioPll2 = 2U, /*!< SAI Clock from AUDIO PLL2.*/
511 kCLOCK_SaiRootmuxVideoPll1 = 3U, /*!< SAI Clock from VIDEO PLL1.*/
512 kCLOCK_SaiRootmuxSysPll1Div6 = 4U, /*!< SAI Clock from SYSTEM PLL1 divided by 6.*/
513 kCLOCK_SaiRootmuxOsc26m = 5U, /*!< SAI Clock from OSC HDMI 26M.*/
514 kCLOCK_SaiRootmuxExtClk1 = 6U, /*!< SAI Clock from External Clock1, External Clock2, External Clock3.*/
515 kCLOCK_SaiRootmuxExtClk2 = 7U, /*!< SAI Clock from External Clock2, External Clock3, External Clock4.*/
516} clock_rootmux_sai_clk_sel_t;
517
518/*! @brief Root clock select enumeration for PDM peripheral. */
519typedef enum _clock_rootmux_pdm_clk_sel
520{
521 kCLOCK_PdmRootmuxOsc24M = 0U, /*!< GPT Clock from OSC 24M.*/
522 kCLOCK_PdmRootmuxSystemPll2 = 1U, /*!< GPT Clock from SYSTEM PLL2 divided by 10.*/
523 kCLOCK_PdmRootmuxAudioPll1 = 2U, /*!< GPT Clock from SYSTEM PLL1 divided by 2.*/
524 kCLOCK_PdmRootmuxSysPll1 = 3U, /*!< GPT Clock from SYSTEM PLL1 divided by 20.*/
525 kCLOCK_PdmRootmuxSysPll2 = 4U, /*!< GPT Clock from VIDEO PLL1.*/
526 kCLOCK_PdmRootmuxSysPll3 = 5U, /*!< GPT Clock from SYSTEM PLL1 divided by 10.*/
527 kCLOCK_PdmRootmuxExtClk3 = 6U, /*!< GPT Clock from AUDIO PLL1.*/
528 kCLOCK_PdmRootmuxAudioPll2 = 7U, /*!< GPT Clock from External Clock1, External Clock2, External Clock3.*/
529} clock_rootmux_pdm_clk_sel_t;
530
531/*! @brief Root clock select enumeration for NOC CLK. */
532typedef enum _clock_rootmux_noc_clk_sel
533{
534 kCLOCK_NocRootmuxOsc24M = 0U, /*!< NOC Clock from OSC 24M.*/
535 kCLOCK_NocRootmuxSysPll1 = 1U, /*!< NOC Clock from SYSTEM PLL1.*/
536 kCLOCK_NocRootmuxSysPll3 = 2U, /*!< NOC Clock from SYSTEM PLL3.*/
537 kCLOCK_NocRootmuxSysPll2 = 3U, /*!< NOC Clock from SYSTEM PLL2.*/
538 kCLOCK_NocRootmuxSysPll2Div2 = 4U, /*!< NOC Clock from SYSTEM PLL2 divided by 2.*/
539 kCLOCK_NocRootmuxAudioPll1 = 5U, /*!< NOC Clock from AUDIO PLL1.*/
540 kCLOCK_NocRootmuxVideoPll1 = 6U, /*!< NOC Clock from VIDEO PLL1.*/
541 kCLOCK_NocRootmuxAudioPll2 = 7U, /*!< NOC Clock from AUDIO PLL2.*/
542
543} clock_rootmux_noc_clk_sel_t;
544
545/*! @brief CCM PLL gate control. */
546typedef enum _clock_pll_gate
547{
548 kCLOCK_ArmPllGate = (uint32_t)(&(CCM)->PLL_CTRL[12].PLL_CTRL), /*!< ARM PLL Gate.*/
549
550 kCLOCK_GpuPllGate = (uint32_t)(&(CCM)->PLL_CTRL[13].PLL_CTRL), /*!< GPU PLL Gate.*/
551 kCLOCK_VpuPllGate = (uint32_t)(&(CCM)->PLL_CTRL[14].PLL_CTRL), /*!< VPU PLL Gate.*/
552 kCLOCK_DramPllGate = (uint32_t)(&(CCM)->PLL_CTRL[15].PLL_CTRL), /*!< DRAM PLL1 Gate.*/
553
554 kCLOCK_SysPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[16].PLL_CTRL), /*!< SYSTEM PLL1 Gate.*/
555 kCLOCK_SysPll1Div2Gate = (uint32_t)(&(CCM)->PLL_CTRL[17].PLL_CTRL), /*!< SYSTEM PLL1 Div2 Gate.*/
556 kCLOCK_SysPll1Div3Gate = (uint32_t)(&(CCM)->PLL_CTRL[18].PLL_CTRL), /*!< SYSTEM PLL1 Div3 Gate.*/
557 kCLOCK_SysPll1Div4Gate = (uint32_t)(&(CCM)->PLL_CTRL[19].PLL_CTRL), /*!< SYSTEM PLL1 Div4 Gate.*/
558 kCLOCK_SysPll1Div5Gate = (uint32_t)(&(CCM)->PLL_CTRL[20].PLL_CTRL), /*!< SYSTEM PLL1 Div5 Gate.*/
559 kCLOCK_SysPll1Div6Gate = (uint32_t)(&(CCM)->PLL_CTRL[21].PLL_CTRL), /*!< SYSTEM PLL1 Div6 Gate.*/
560 kCLOCK_SysPll1Div8Gate = (uint32_t)(&(CCM)->PLL_CTRL[22].PLL_CTRL), /*!< SYSTEM PLL1 Div8 Gate.*/
561 kCLOCK_SysPll1Div10Gate = (uint32_t)(&(CCM)->PLL_CTRL[23].PLL_CTRL), /*!< SYSTEM PLL1 Div10 Gate.*/
562 kCLOCK_SysPll1Div20Gate = (uint32_t)(&(CCM)->PLL_CTRL[24].PLL_CTRL), /*!< SYSTEM PLL1 Div20 Gate.*/
563
564 kCLOCK_SysPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[25].PLL_CTRL), /*!< SYSTEM PLL2 Gate.*/
565 kCLOCK_SysPll2Div2Gate = (uint32_t)(&(CCM)->PLL_CTRL[26].PLL_CTRL), /*!< SYSTEM PLL2 Div2 Gate.*/
566 kCLOCK_SysPll2Div3Gate = (uint32_t)(&(CCM)->PLL_CTRL[27].PLL_CTRL), /*!< SYSTEM PLL2 Div3 Gate.*/
567 kCLOCK_SysPll2Div4Gate = (uint32_t)(&(CCM)->PLL_CTRL[28].PLL_CTRL), /*!< SYSTEM PLL2 Div4 Gate.*/
568 kCLOCK_SysPll2Div5Gate = (uint32_t)(&(CCM)->PLL_CTRL[29].PLL_CTRL), /*!< SYSTEM PLL2 Div5 Gate.*/
569 kCLOCK_SysPll2Div6Gate = (uint32_t)(&(CCM)->PLL_CTRL[30].PLL_CTRL), /*!< SYSTEM PLL2 Div6 Gate.*/
570 kCLOCK_SysPll2Div8Gate = (uint32_t)(&(CCM)->PLL_CTRL[31].PLL_CTRL), /*!< SYSTEM PLL2 Div8 Gate.*/
571 kCLOCK_SysPll2Div10Gate = (uint32_t)(&(CCM)->PLL_CTRL[32].PLL_CTRL), /*!< SYSTEM PLL2 Div10 Gate.*/
572 kCLOCK_SysPll2Div20Gate = (uint32_t)(&(CCM)->PLL_CTRL[33].PLL_CTRL), /*!< SYSTEM PLL2 Div20 Gate.*/
573
574 kCLOCK_SysPll3Gate = (uint32_t)(&(CCM)->PLL_CTRL[34].PLL_CTRL), /*!< SYSTEM PLL3 Gate.*/
575
576 kCLOCK_AudioPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[35].PLL_CTRL), /*!< AUDIO PLL1 Gate.*/
577 kCLOCK_AudioPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[36].PLL_CTRL), /*!< AUDIO PLL2 Gate.*/
578 kCLOCK_VideoPll1Gate = (uint32_t)(&(CCM)->PLL_CTRL[37].PLL_CTRL), /*!< VIDEO PLL1 Gate.*/
579 kCLOCK_VideoPll2Gate = (uint32_t)(&(CCM)->PLL_CTRL[38].PLL_CTRL), /*!< VIDEO PLL2 Gate.*/
580} clock_pll_gate_t;
581
582/*! @brief CCM gate control value. */
583typedef enum _clock_gate_value
584{
585 kCLOCK_ClockNotNeeded = 0x0U, /*!< Clock always disabled.*/
586 kCLOCK_ClockNeededRun = 0x1111U, /*!< Clock enabled when CPU is running.*/
587 kCLOCK_ClockNeededRunWait = 0x2222U, /*!< Clock enabled when CPU is running or in WAIT mode.*/
588 kCLOCK_ClockNeededAll = 0x3333U, /*!< Clock always enabled.*/
589} clock_gate_value_t;
590
591/*!
592 * @brief PLL control names for PLL bypass.
593 *
594 * These constants define the PLL control names for PLL bypass.\n
595 * - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
596 * - 16:20: bypass bit shift.
597 */
598typedef enum _clock_pll_bypass_ctrl
599{
600 kCLOCK_AudioPll1BypassCtrl =
601 CCM_ANALOG_TUPLE(AUDIO_PLL1_GEN_CTRL_OFFSET,
602 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Audio PLL1 bypass Control.*/
603
604 kCLOCK_AudioPll2BypassCtrl =
605 CCM_ANALOG_TUPLE(AUDIO_PLL2_GEN_CTRL_OFFSET,
606 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Audio PLL2 bypass Control.*/
607
608 kCLOCK_VideoPll1BypassCtrl =
609 CCM_ANALOG_TUPLE(VIDEO_PLL1_GEN_CTRL_OFFSET,
610 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Video Pll1 bypass Control.*/
611
612 kCLOCK_DramPllInternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
613 DRAM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM DRAM PLL bypass Control.*/
614
615 kCLOCK_ArmPllPwrBypassCtrl = CCM_ANALOG_TUPLE(
616 ARM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM Arm PLL bypass Control.*/
617
618 kCLOCK_SysPll1InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
619 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM System PLL1 bypass Control.*/
620
621 kCLOCK_SysPll2InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
622 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM System PLL2 bypass Control.*/
623
624 kCLOCK_SysPll3InternalPll1BypassCtrl = CCM_ANALOG_TUPLE(
625 SYS_PLL3_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_BYPASS_SHIFT), /*!< CCM System PLL3 bypass Control.*/
626} clock_pll_bypass_ctrl_t;
627
628/*!
629 * @brief PLL clock names for clock enable/disable settings.
630 *
631 * These constants define the PLL clock names for PLL clock enable/disable operations.\n
632 * - 0:15: REG offset to CCM_ANALOG_BASE in bytes.
633 * - 16:20: Clock enable bit shift.
634 */
635typedef enum _ccm_analog_pll_clke
636{
637 kCLOCK_AudioPll1Clke = CCM_ANALOG_TUPLE(AUDIO_PLL1_GEN_CTRL_OFFSET,
638 CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Audio pll1 clke */
639 kCLOCK_AudioPll2Clke = CCM_ANALOG_TUPLE(AUDIO_PLL2_GEN_CTRL_OFFSET,
640 CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Audio pll2 clke */
641 kCLOCK_VideoPll1Clke = CCM_ANALOG_TUPLE(VIDEO_PLL1_GEN_CTRL_OFFSET,
642 CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Video pll1 clke */
643 kCLOCK_DramPllClke =
644 CCM_ANALOG_TUPLE(DRAM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Dram pll clke */
645
646 kCLOCK_ArmPllClke =
647 CCM_ANALOG_TUPLE(ARM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_CLKE_SHIFT), /*!< Arm pll clke */
648
649 kCLOCK_SystemPll1Clke = CCM_ANALOG_TUPLE(SYS_PLL1_GEN_CTRL_OFFSET,
650 CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_CLKE_SHIFT), /*!< System pll1 clke */
651 kCLOCK_SystemPll1Div2Clke = CCM_ANALOG_TUPLE(
652 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV2_CLKE_SHIFT), /*!< System pll1 Div2 clke */
653 kCLOCK_SystemPll1Div3Clke = CCM_ANALOG_TUPLE(
654 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV3_CLKE_SHIFT), /*!< System pll1 Div3 clke */
655 kCLOCK_SystemPll1Div4Clke = CCM_ANALOG_TUPLE(
656 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV4_CLKE_SHIFT), /*!< System pll1 Div4 clke */
657 kCLOCK_SystemPll1Div5Clke = CCM_ANALOG_TUPLE(
658 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV5_CLKE_SHIFT), /*!< System pll1 Div5 clke */
659 kCLOCK_SystemPll1Div6Clke = CCM_ANALOG_TUPLE(
660 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV6_CLKE_SHIFT), /*!< System pll1 Div6 clke */
661 kCLOCK_SystemPll1Div8Clke = CCM_ANALOG_TUPLE(
662 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV8_CLKE_SHIFT), /*!< System pll1 Div8 clke */
663 kCLOCK_SystemPll1Div10Clke = CCM_ANALOG_TUPLE(
664 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV10_CLKE_SHIFT), /*!< System pll1 Div10 clke */
665 kCLOCK_SystemPll1Div20Clke = CCM_ANALOG_TUPLE(
666 SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_DIV20_CLKE_SHIFT), /*!< System pll1 Div20 clke */
667
668 kCLOCK_SystemPll2Clke = CCM_ANALOG_TUPLE(SYS_PLL2_GEN_CTRL_OFFSET,
669 CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_CLKE_SHIFT), /*!< System pll2 clke */
670 kCLOCK_SystemPll2Div2Clke = CCM_ANALOG_TUPLE(
671 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV2_CLKE_SHIFT), /*!< System pll2 Div2 clke */
672 kCLOCK_SystemPll2Div3Clke = CCM_ANALOG_TUPLE(
673 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV3_CLKE_SHIFT), /*!< System pll2 Div3 clke */
674 kCLOCK_SystemPll2Div4Clke = CCM_ANALOG_TUPLE(
675 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV4_CLKE_SHIFT), /*!< System pll2 Div4 clke */
676 kCLOCK_SystemPll2Div5Clke = CCM_ANALOG_TUPLE(
677 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV5_CLKE_SHIFT), /*!< System pll2 Div5 clke */
678 kCLOCK_SystemPll2Div6Clke = CCM_ANALOG_TUPLE(
679 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV6_CLKE_SHIFT), /*!< System pll2 Div6 clke */
680 kCLOCK_SystemPll2Div8Clke = CCM_ANALOG_TUPLE(
681 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV8_CLKE_SHIFT), /*!< System pll2 Div8 clke */
682 kCLOCK_SystemPll2Div10Clke = CCM_ANALOG_TUPLE(
683 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV10_CLKE_SHIFT), /*!< System pll2 Div10 clke */
684 kCLOCK_SystemPll2Div20Clke = CCM_ANALOG_TUPLE(
685 SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_DIV20_CLKE_SHIFT), /*!< System pll2 Div20 clke */
686
687 kCLOCK_SystemPll3Clke = CCM_ANALOG_TUPLE(SYS_PLL3_GEN_CTRL_OFFSET,
688 CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_CLKE_SHIFT), /*!< System pll3 clke */
689} clock_pll_clke_t;
690
691/*!
692 * @brief ANALOG Power down override control.
693 */
694typedef enum _clock_pll_ctrl
695{
696 /* Fractional PLL frequency */
697 kCLOCK_AudioPll1Ctrl = CCM_ANALOG_TUPLE(AUDIO_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_AUDIO_PLL1_GEN_CTRL_PLL_RST_SHIFT),
698 kCLOCK_AudioPll2Ctrl = CCM_ANALOG_TUPLE(AUDIO_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_AUDIO_PLL2_GEN_CTRL_PLL_RST_SHIFT),
699 kCLOCK_VideoPll1Ctrl = CCM_ANALOG_TUPLE(VIDEO_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_VIDEO_PLL1_GEN_CTRL_PLL_RST_SHIFT),
700 kCLOCK_DramPllCtrl = CCM_ANALOG_TUPLE(DRAM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_DRAM_PLL_GEN_CTRL_PLL_RST_SHIFT),
701 /* Integer PLL frequency */
702 kCLOCK_ArmPllCtrl = CCM_ANALOG_TUPLE(ARM_PLL_GEN_CTRL_OFFSET, CCM_ANALOG_ARM_PLL_GEN_CTRL_PLL_RST_SHIFT),
703 kCLOCK_SystemPll1Ctrl = CCM_ANALOG_TUPLE(SYS_PLL1_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_RST_SHIFT),
704 kCLOCK_SystemPll2Ctrl = CCM_ANALOG_TUPLE(SYS_PLL2_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL2_GEN_CTRL_PLL_RST_SHIFT),
705 kCLOCK_SystemPll3Ctrl = CCM_ANALOG_TUPLE(SYS_PLL3_GEN_CTRL_OFFSET, CCM_ANALOG_SYS_PLL3_GEN_CTRL_PLL_RST_SHIFT),
706} clock_pll_ctrl_t;
707
708/*! @brief PLL reference clock select. */
709enum
710{
711 kANALOG_PllRefOsc24M = 0U, /*!< reference OSC 24M */
712 kANALOG_PllPadClk = 1U, /*!< reference PAD CLK */
713};
714
715/*!
716 * @brief Fractional-N PLL configuration.
717 * Note: all the dividers in this configuration structure are the actually divider, software will map it to register
718 * value
719 */
720typedef struct _ccm_analog_frac_pll_config
721{
722 uint8_t refSel; /*!< pll reference clock sel */
723
724 uint32_t mainDiv; /*!< Value of the 10-bit programmable main-divider, range must be 64~1023 */
725
726 uint32_t dsm; /*!< Value of 16-bit DSM */
727
728 uint8_t preDiv; /*!< Value of the 6-bit programmable pre-divider, range must be 1~63 */
729
730 uint8_t postDiv; /*!< Value of the 3-bit programmable Scaler, range must be 0~6 */
731} ccm_analog_frac_pll_config_t;
732
733/*!
734 * @brief Integer PLL configuration.
735 * Note: all the dividers in this configuration structure are the actually divider, software will map it to register
736 * value
737 */
738typedef struct _ccm_analog_integer_pll_config
739{
740 uint8_t refSel; /*!< pll reference clock sel */
741
742 uint32_t mainDiv; /*!< Value of the 10-bit programmable main-divider, range must be 64~1023 */
743
744 uint8_t preDiv; /*!< Value of the 6-bit programmable pre-divider, range must be 1~63 */
745
746 uint8_t postDiv; /*!< Value of the 3-bit programmable Scaler, range must be 0~6 */
747
748} ccm_analog_integer_pll_config_t;
749
750/*******************************************************************************
751 * API
752 ******************************************************************************/
753
754#if defined(__cplusplus)
755extern "C" {
756#endif
757
758/*!
759 * @name CCM Root Clock Setting
760 * @{
761 */
762
763/*!
764 * @brief Set clock root mux.
765 * User maybe need to set more than one mux ROOT according to the clock tree
766 * description in the reference manual.
767 *
768 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration).
769 * @param mux Root mux value, refer to _ccm_rootmux_xxx enumeration.
770 */
771static inline void CLOCK_SetRootMux(clock_root_control_t rootClk, uint32_t mux)
772{
773 CCM_REG(rootClk) = (CCM_REG(rootClk) & (~CCM_TARGET_ROOT_MUX_MASK)) | CCM_TARGET_ROOT_MUX(mux);
774}
775
776/*!
777 * @brief Get clock root mux.
778 * In order to get the clock source of root, user maybe need to get more than one
779 * ROOT's mux value to obtain the final clock source of root.
780 *
781 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration).
782 * @return Root mux value, refer to _ccm_rootmux_xxx enumeration.
783 */
784static inline uint32_t CLOCK_GetRootMux(clock_root_control_t rootClk)
785{
786 return (CCM_REG(rootClk) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT;
787}
788
789/*!
790 * @brief Enable clock root
791 *
792 * @param rootClk Root clock control (see @ref clock_root_control_t enumeration)
793 */
794static inline void CLOCK_EnableRoot(clock_root_control_t rootClk)
795{
796 CCM_REG_SET(rootClk) = CCM_TARGET_ROOT_SET_ENABLE_MASK;
797}
798
799/*!
800 * @brief Disable clock root
801 *
802 * @param rootClk Root control (see @ref clock_root_control_t enumeration)
803 */
804static inline void CLOCK_DisableRoot(clock_root_control_t rootClk)
805{
806 CCM_REG_CLR(rootClk) = CCM_TARGET_ROOT_CLR_ENABLE_MASK;
807}
808
809/*!
810 * @brief Check whether clock root is enabled
811 *
812 * @param rootClk Root control (see @ref clock_root_control_t enumeration)
813 * @return CCM root enabled or not.
814 * - true: Clock root is enabled.
815 * - false: Clock root is disabled.
816 */
817static inline bool CLOCK_IsRootEnabled(clock_root_control_t rootClk)
818{
819 return (bool)(CCM_REG(rootClk) & CCM_TARGET_ROOT_ENABLE_MASK);
820}
821
822/*!
823 * @brief Update clock root in one step, for dynamical clock switching
824 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
825 *
826 * @param ccmRootClk Root control (see @ref clock_root_control_t enumeration)
827 * @param mux Root mux value, refer to _ccm_rootmux_xxx enumeration
828 * @param pre Pre divider value (0-7, divider=n+1)
829 * @param post Post divider value (0-63, divider=n+1)
830 */
831void CLOCK_UpdateRoot(clock_root_control_t ccmRootClk, uint32_t mux, uint32_t pre, uint32_t post);
832
833/*!
834 * @brief Set root clock divider
835 * Note: The PRE and POST dividers in this function are the actually divider, software will map it to register value
836 *
837 * @param ccmRootClk Root control (see @ref clock_root_control_t enumeration)
838 * @param pre Pre divider value (1-8)
839 * @param post Post divider value (1-64)
840 */
841void CLOCK_SetRootDivider(clock_root_control_t ccmRootClk, uint32_t pre, uint32_t post);
842
843/*!
844 * @brief Get clock root PRE_PODF.
845 * In order to get the clock source of root, user maybe need to get more than one
846 * ROOT's mux value to obtain the final clock source of root.
847 *
848 * @param rootClk Root clock name (see @ref clock_root_control_t enumeration).
849 * @return Root Pre divider value.
850 */
851static inline uint32_t CLOCK_GetRootPreDivider(clock_root_control_t rootClk)
852{
853 return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT) + 1U;
854}
855
856/*!
857 * @brief Get clock root POST_PODF.
858 * In order to get the clock source of root, user maybe need to get more than one
859 * ROOT's mux value to obtain the final clock source of root.
860 *
861 * @param rootClk Root clock name (see @ref clock_root_control_t enumeration).
862 * @return Root Post divider value.
863 */
864static inline uint32_t CLOCK_GetRootPostDivider(clock_root_control_t rootClk)
865{
866 return ((CCM_REG(rootClk) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT) + 1U;
867}
868
869/*!
870 * @name CCM Gate Control
871 * @{
872 */
873
874/*!
875 * lockrief Set PLL or CCGR gate control
876 *
877 * @param ccmGate Gate control (see @ref clock_pll_gate_t and @ref clock_ip_name_t enumeration)
878 * @param control Gate control value (see @ref clock_gate_value_t)
879 */
880static inline void CLOCK_ControlGate(uint32_t ccmGate, clock_gate_value_t control)
881{
882 CCM_REG(ccmGate) = (uint32_t)control;
883}
884
885/*!
886 * @brief Enable CCGR clock gate and root clock gate for each module
887 * User should set specific gate for each module according to the description
888 * of the table of system clocks, gating and override in CCM chapter of
889 * reference manual. Take care of that one module may need to set more than
890 * one clock gate.
891 *
892 * @param ccmGate Gate control for each module (see @ref clock_ip_name_t enumeration).
893 */
894void CLOCK_EnableClock(clock_ip_name_t ccmGate);
895
896/*!
897 * @brief Disable CCGR clock gate for the each module
898 * User should set specific gate for each module according to the description
899 * of the table of system clocks, gating and override in CCM chapter of
900 * reference manual. Take care of that one module may need to set more than
901 * one clock gate.
902 *
903 * @param ccmGate Gate control for each module (see @ref clock_ip_name_t enumeration).
904 */
905void CLOCK_DisableClock(clock_ip_name_t ccmGate);
906
907/*!
908 * @name CCM Analog PLL Operatoin Functions
909 * @{
910 */
911
912/*!
913 * @brief Power up PLL
914 *
915 * @param base CCM_ANALOG base pointer.
916 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
917 */
918static inline void CLOCK_PowerUpPll(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
919{
920 CCM_ANALOG_TUPLE_REG(base, pllControl) |= (1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
921}
922
923/*!
924 * @brief Power down PLL
925 *
926 * @param base CCM_ANALOG base pointer.
927 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
928 */
929static inline void CLOCK_PowerDownPll(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
930{
931 CCM_ANALOG_TUPLE_REG(base, pllControl) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
932}
933
934/*!
935 * @brief PLL bypass setting
936 *
937 * @param base CCM_ANALOG base pointer.
938 * @param pllControl PLL control name, refer to ccm_analog_pll_control_t enumeration
939 * @param bypass Bypass the PLL.
940 * - true: Bypass the PLL.
941 * - false: Do not bypass the PLL.
942 */
943static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl, bool bypass)
944{
945 if (bypass)
946 {
947 CCM_ANALOG_TUPLE_REG(base, pllControl) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl);
948 }
949 else
950 {
951 CCM_ANALOG_TUPLE_REG(base, pllControl) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl));
952 }
953}
954
955/*!
956 * @brief Check if PLL is bypassed
957 *
958 * @param base CCM_ANALOG base pointer.
959 * @param pllControl PLL control name, refer to ccm_analog_pll_control_t enumeration
960 * @return PLL bypass status.
961 * - true: The PLL is bypassed.
962 * - false: The PLL is not bypassed.
963 */
964static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_bypass_ctrl_t pllControl)
965{
966 return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pllControl)));
967}
968
969/*!
970 * @brief Check if PLL clock is locked
971 *
972 * @param base CCM_ANALOG base pointer.
973 * @param pllControl PLL control name (see @ref clock_pll_ctrl_t enumeration)
974 * @return PLL lock status.
975 * - true: The PLL clock is locked.
976 * - false: The PLL clock is not locked.
977 */
978static inline bool CLOCK_IsPllLocked(CCM_ANALOG_Type *base, clock_pll_ctrl_t pllControl)
979{
980 return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & CCM_ANALOG_SYS_PLL1_GEN_CTRL_PLL_LOCK_MASK);
981}
982
983/*!
984 * @brief Enable PLL clock
985 *
986 * @param base CCM_ANALOG base pointer.
987 * @param pllClock PLL clock name, refer to ccm_analog_pll_clock_t enumeration
988 */
989static inline void CLOCK_EnableAnalogClock(CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)
990{
991 CCM_ANALOG_TUPLE_REG(base, pllClock) |= 1UL << CCM_ANALOG_TUPLE_SHIFT(pllClock);
992}
993
994/*!
995 * @brief Disable PLL clock
996 *
997 * @param base CCM_ANALOG base pointer.
998 * @param pllClock PLL clock name, refer to ccm_analog_pll_clock_t enumeration
999 */
1000static inline void CLOCK_DisableAnalogClock(CCM_ANALOG_Type *base, clock_pll_clke_t pllClock)
1001{
1002 CCM_ANALOG_TUPLE_REG(base, pllClock) &= ~(1UL << CCM_ANALOG_TUPLE_SHIFT(pllClock));
1003}
1004
1005/*!
1006 * @brief Override PLL clock output enable
1007 *
1008 * @param base CCM_ANALOG base pointer.
1009 * @param ovClock PLL clock name (see @ref clock_pll_clke_t enumeration)
1010 * @param override Override the PLL.
1011 * - true: Override the PLL clke, CCM will handle it.
1012 * - false: Do not override the PLL clke.
1013 */
1014static inline void CLOCK_OverridePllClke(CCM_ANALOG_Type *base, clock_pll_clke_t ovClock, bool override)
1015{
1016 if (override)
1017 {
1018 CCM_ANALOG_TUPLE_REG(base, ovClock) |= 1UL << (CCM_ANALOG_TUPLE_SHIFT(ovClock) - 1UL);
1019 }
1020 else
1021 {
1022 CCM_ANALOG_TUPLE_REG(base, ovClock) &= ~(1UL << (CCM_ANALOG_TUPLE_SHIFT(ovClock) - 1UL));
1023 }
1024}
1025
1026/*!
1027 * @brief Override PLL power down
1028 *
1029 * @param base CCM_ANALOG base pointer.
1030 * @param pdClock PLL clock name (see @ref clock_pll_ctrl_t enumeration)
1031 * @param override Override the PLL.
1032 * - true: Override the PLL clke, CCM will handle it.
1033 * - false: Do not override the PLL clke.
1034 */
1035static inline void CLOCK_OverridePllPd(CCM_ANALOG_Type *base, clock_pll_ctrl_t pdClock, bool override)
1036{
1037 if (override)
1038 {
1039 CCM_ANALOG_TUPLE_REG(base, pdClock) |= 1UL << (CCM_ANALOG_TUPLE_SHIFT(pdClock) - 1UL);
1040 }
1041 else
1042 {
1043 CCM_ANALOG_TUPLE_REG(base, pdClock) &= ~(1UL << (CCM_ANALOG_TUPLE_SHIFT(pdClock) - 1UL));
1044 }
1045}
1046
1047/*!
1048 * @brief Initializes the ANALOG ARM PLL.
1049 *
1050 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1051 *
1052 * @note This function can't detect whether the Arm PLL has been enabled and
1053 * used by some IPs.
1054 */
1055void CLOCK_InitArmPll(const ccm_analog_integer_pll_config_t *config);
1056
1057/*!
1058 * @brief De-initialize the ARM PLL.
1059 */
1060void CLOCK_DeinitArmPll(void);
1061
1062/*!
1063 * @brief Initializes the ANALOG SYS PLL1.
1064 *
1065 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1066 *
1067 * @note This function can't detect whether the SYS PLL has been enabled and
1068 * used by some IPs.
1069 */
1070void CLOCK_InitSysPll1(const ccm_analog_integer_pll_config_t *config);
1071
1072/*!
1073 * @brief De-initialize the System PLL1.
1074 */
1075void CLOCK_DeinitSysPll1(void);
1076
1077/*!
1078 * @brief Initializes the ANALOG SYS PLL2.
1079 *
1080 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1081 *
1082 * @note This function can't detect whether the SYS PLL has been enabled and
1083 * used by some IPs.
1084 */
1085void CLOCK_InitSysPll2(const ccm_analog_integer_pll_config_t *config);
1086
1087/*!
1088 * @brief De-initialize the System PLL2.
1089 */
1090void CLOCK_DeinitSysPll2(void);
1091
1092/*!
1093 * @brief Initializes the ANALOG SYS PLL3.
1094 *
1095 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1096 *
1097 * @note This function can't detect whether the SYS PLL has been enabled and
1098 * used by some IPs.
1099 */
1100void CLOCK_InitSysPll3(const ccm_analog_integer_pll_config_t *config);
1101
1102/*!
1103 * @brief De-initialize the System PLL3.
1104 */
1105void CLOCK_DeinitSysPll3(void);
1106
1107/*!
1108 * @brief Initializes the ANALOG AUDIO PLL1.
1109 *
1110 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1111 *
1112 * @note This function can't detect whether the AUDIO PLL has been enabled and
1113 * used by some IPs.
1114 */
1115void CLOCK_InitAudioPll1(const ccm_analog_frac_pll_config_t *config);
1116
1117/*!
1118 * @brief De-initialize the Audio PLL1.
1119 */
1120void CLOCK_DeinitAudioPll1(void);
1121
1122/*!
1123 * @brief Initializes the ANALOG AUDIO PLL2.
1124 *
1125 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1126 *
1127 * @note This function can't detect whether the AUDIO PLL has been enabled and
1128 * used by some IPs.
1129 */
1130void CLOCK_InitAudioPll2(const ccm_analog_frac_pll_config_t *config);
1131
1132/*!
1133 * @brief De-initialize the Audio PLL2.
1134 */
1135void CLOCK_DeinitAudioPll2(void);
1136
1137/*!
1138 * @brief Initializes the ANALOG VIDEO PLL1.
1139 *
1140 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1141 *
1142 */
1143void CLOCK_InitVideoPll1(const ccm_analog_frac_pll_config_t *config);
1144
1145/*!
1146 * @brief De-initialize the Video PLL1.
1147 */
1148void CLOCK_DeinitVideoPll1(void);
1149
1150/*!
1151 * @brief Initializes the ANALOG Integer PLL.
1152 *
1153 * @param base CCM ANALOG base address
1154 * @param config Pointer to the configuration structure(see @ref ccm_analog_integer_pll_config_t enumeration).
1155 * @param type integer pll type
1156 *
1157 */
1158void CLOCK_InitIntegerPll(CCM_ANALOG_Type *base, const ccm_analog_integer_pll_config_t *config, clock_pll_ctrl_t type);
1159
1160/*!
1161 * @brief Get the ANALOG Integer PLL clock frequency.
1162 *
1163 * @param base CCM ANALOG base address.
1164 * @param type integer pll type
1165 * @param refClkFreq pll reference clock frequency
1166 * @param pll1Bypass pll1 bypass flag
1167 *
1168 * @return Clock frequency
1169 */
1170uint32_t CLOCK_GetIntegerPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq, bool pll1Bypass);
1171
1172/*!
1173 * @brief Initializes the ANALOG Fractional PLL.
1174 *
1175 * @param base CCM ANALOG base address.
1176 * @param config Pointer to the configuration structure(see @ref ccm_analog_frac_pll_config_t enumeration).
1177 * @param type fractional pll type.
1178 *
1179 */
1180void CLOCK_InitFracPll(CCM_ANALOG_Type *base, const ccm_analog_frac_pll_config_t *config, clock_pll_ctrl_t type);
1181
1182/*!
1183 * @brief Gets the ANALOG Fractional PLL clock frequency.
1184 *
1185 * @param base CCM_ANALOG base pointer.
1186 * @param type Fractional pll type.
1187 * @param refClkFreq Pll reference clock frequency
1188 *
1189 * @return Clock frequency
1190 */
1191uint32_t CLOCK_GetFracPllFreq(CCM_ANALOG_Type *base, clock_pll_ctrl_t type, uint32_t refClkFreq);
1192
1193/*!
1194 * @brief Gets PLL clock frequency.
1195 *
1196 * @param pll Fractional pll type.
1197
1198 * @return Clock frequency
1199 */
1200uint32_t CLOCK_GetPllFreq(clock_pll_ctrl_t pll);
1201
1202/*!
1203 * @brief Gets PLL reference clock frequency.
1204 *
1205 * @param ctrl Fractional pll type.
1206
1207 * @return Clock frequency
1208 */
1209uint32_t CLOCK_GetPllRefClkFreq(clock_pll_ctrl_t ctrl);
1210
1211/*!
1212 * @name CCM Get frequency
1213 * @{
1214 */
1215
1216/*!
1217 * @brief Gets the clock frequency for a specific clock name.
1218 *
1219 * This function checks the current clock configurations and then calculates
1220 * the clock frequency for a specific clock name defined in clock_name_t.
1221 *
1222 * @param clockName Clock names defined in clock_name_t
1223 * @return Clock frequency value in hertz
1224 */
1225uint32_t CLOCK_GetFreq(clock_name_t clockName);
1226
1227/*!
1228 * @brief Get the CCM Cortex M7 core frequency.
1229 *
1230 * @return Clock frequency; If the clock is invalid, returns 0.
1231 */
1232uint32_t CLOCK_GetCoreM7Freq(void);
1233
1234/*!
1235 * @brief Get the CCM Axi bus frequency.
1236 *
1237 * @return Clock frequency; If the clock is invalid, returns 0.
1238 */
1239uint32_t CLOCK_GetAxiFreq(void);
1240
1241/*!
1242 * @brief Get the CCM Ahb bus frequency.
1243 *
1244 * @return Clock frequency; If the clock is invalid, returns 0.
1245 */
1246uint32_t CLOCK_GetAhbFreq(void);
1247
1248/* @} */
1249
1250#if defined(__cplusplus)
1251}
1252#endif
1253/* @} */
1254#endif
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 22:56:26 +0100