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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MQ5/MIMX8MQ5_cm4.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8MQ5/MIMX8MQ5_cm4.h
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@@ -0,0 +1,45763 @@
1/*
2** ###################################################################
3** Processors: MIMX8MQ5CVAHZ
4** MIMX8MQ5DVAJZ
5**
6** Compilers: Keil ARM C/C++ Compiler
7** GNU C Compiler
8** IAR ANSI C/C++ Compiler for ARM
9**
10** Reference manual: IMX8MDQLQRM, Rev. 0, Jan. 2018
11** Version: rev. 4.0, 2018-01-26
12** Build: b180903
13**
14** Abstract:
15** CMSIS Peripheral Access Layer for MIMX8MQ5_cm4
16**
17** Copyright 1997-2016 Freescale Semiconductor, Inc.
18** Copyright 2016-2018 NXP
19** All rights reserved.
20**
21** SPDX-License-Identifier: BSD-3-Clause
22**
23** http: www.nxp.com
24** mail: [email protected]
25**
26** Revisions:
27** - rev. 1.0 (2017-01-10)
28** Initial version.
29** - rev. 2.0 (2017-04-27)
30** Rev.B Header EAR1
31** - rev. 3.0 (2017-07-19)
32** Rev.C Header EAR2
33** - rev. 4.0 (2018-01-26)
34** Rev.D Header RFP
35**
36** ###################################################################
37*/
38
39/*!
40 * @file MIMX8MQ5_cm4.h
41 * @version 4.0
42 * @date 2018-01-26
43 * @brief CMSIS Peripheral Access Layer for MIMX8MQ5_cm4
44 *
45 * CMSIS Peripheral Access Layer for MIMX8MQ5_cm4
46 */
47
48#ifndef _MIMX8MQ5_CM4_H_
49#define _MIMX8MQ5_CM4_H_ /**< Symbol preventing repeated inclusion */
50
51/** Memory map major version (memory maps with equal major version number are
52 * compatible) */
53#define MCU_MEM_MAP_VERSION 0x0400U
54/** Memory map minor version */
55#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
56
57
58/* ----------------------------------------------------------------------------
59 -- Interrupt vector numbers
60 ---------------------------------------------------------------------------- */
61
62/*!
63 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
64 * @{
65 */
66
67/** Interrupt Number Definitions */
68#define NUMBER_OF_INT_VECTORS 144 /**< Number of interrupts in the Vector table */
69
70typedef enum IRQn {
71 /* Auxiliary constants */
72 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
73
74 /* Core interrupts */
75 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
76 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
77 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
78 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
79 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
80 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
81 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
82 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
83 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
84
85 /* Device specific interrupts */
86 GPR_IRQ_IRQn = 0, /**< GPR Interrupt. Used to notify cores on exception condition while boot. */
87 DAP_IRQn = 1, /**< DAP Interrupt */
88 SDMA1_IRQn = 2, /**< AND of all 48 SDMA interrupts (events) from all the channels */
89 GPU_IRQn = 3, /**< GPU Interrupt */
90 SNVS_IRQn = 4, /**< ON-OFF button press shorter than 5 seconds (pulse event) */
91 LCDIF_IRQn = 5, /**< LCDIF Sync Interrupt */
92 SPDIF1_IRQn = 6, /**< SPDIF1 Interrupt */
93 H264_IRQn = 7, /**< h264 Decoder Interrupt */
94 VPUDMA_IRQn = 8, /**< VPU DMA Interrupt */
95 QOS_IRQn = 9, /**< QOS interrupt */
96 WDOG3_IRQn = 10, /**< Watchdog Timer reset */
97 HS_CP1_IRQn = 11, /**< HS Interrupt Request */
98 APBHDMA_IRQn = 12, /**< GPMI operation channel 0-3 description complete interrupt */
99 SPDIF2_IRQn = 13, /**< SPDIF2 Interrupt */
100 BCH_IRQn = 14, /**< BCH operation complete interrupt */
101 GPMI_IRQn = 15, /**< GPMI operation TIMEOUT ERROR interrupt */
102 HDMI_IRQ0_IRQn = 16, /**< HDMI Interrupt 0 */
103 HDMI_IRQ1_IRQn = 17, /**< HDMI Interrupt 1 */
104 HDMI_IRQ2_IRQn = 18, /**< HDMI Interrupt 2 */
105 SNVS_Consolidated_IRQn = 19, /**< SRTC Consolidated Interrupt. Non TZ. */
106 SNVS_Security_IRQn = 20, /**< SRTC Security Interrupt. TZ. */
107 CSU_IRQn = 21, /**< CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted. */
108 USDHC1_IRQn = 22, /**< uSDHC1 Enhanced SDHC Interrupt Request */
109 USDHC2_IRQn = 23, /**< uSDHC2 Enhanced SDHC Interrupt Request */
110 DDC_IRQn = 24, /**< DC8000 Display Controller IRQ */
111 DTRC_IRQn = 25, /**< DTRC interrupt */
112 UART1_IRQn = 26, /**< UART-1 ORed interrupt */
113 UART2_IRQn = 27, /**< UART-2 ORed interrupt */
114 UART3_IRQn = 28, /**< UART-3 ORed interrupt */
115 UART4_IRQn = 29, /**< UART-4 ORed interrupt */
116 VP9_IRQn = 30, /**< VP9 Decoder interrupt */
117 ECSPI1_IRQn = 31, /**< ECSPI1 interrupt request line to the core. */
118 ECSPI2_IRQn = 32, /**< ECSPI2 interrupt request line to the core. */
119 ECSPI3_IRQn = 33, /**< ECSPI3 interrupt request line to the core. */
120 MIPI_DSI_IRQn = 34, /**< DSI Interrupt */
121 I2C1_IRQn = 35, /**< I2C-1 Interrupt */
122 I2C2_IRQn = 36, /**< I2C-2 Interrupt */
123 I2C3_IRQn = 37, /**< I2C-3 Interrupt */
124 I2C4_IRQn = 38, /**< I2C-4 Interrupt */
125 RDC_IRQn = 39, /**< RDC interrupt */
126 USB1_IRQn = 40, /**< USB1 Interrupt */
127 USB2_IRQn = 41, /**< USB1 Interrupt */
128 CSI1_IRQn = 42, /**< CSI1 interrupt */
129 CSI2_IRQn = 43, /**< CSI2 interrupt */
130 MIPI_CSI1_IRQn = 44, /**< MIPI-CSI-1 Interrupt */
131 MIPI_CSI2_IRQn = 45, /**< MIPI-CSI-2 Interrupt */
132 GPT6_IRQn = 46, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
133 SCTR_IRQ0_IRQn = 47, /**< ISO7816IP Interrupt 0 */
134 SCTR_IRQ1_IRQn = 48, /**< ISO7816IP Interrupt 1 */
135 TEMPMON_IRQn = 49, /**< TempSensor (Temperature alarm). */
136 I2S3_IRQn = 50, /**< SAI3 Receive / Transmit Interrupt */
137 GPT5_IRQn = 51, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
138 GPT4_IRQn = 52, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
139 GPT3_IRQn = 53, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
140 GPT2_IRQn = 54, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
141 GPT1_IRQn = 55, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1, 2, and 3 Interrupt lines */
142 GPIO1_INT7_IRQn = 56, /**< Active HIGH Interrupt from INT7 from GPIO */
143 GPIO1_INT6_IRQn = 57, /**< Active HIGH Interrupt from INT6 from GPIO */
144 GPIO1_INT5_IRQn = 58, /**< Active HIGH Interrupt from INT5 from GPIO */
145 GPIO1_INT4_IRQn = 59, /**< Active HIGH Interrupt from INT4 from GPIO */
146 GPIO1_INT3_IRQn = 60, /**< Active HIGH Interrupt from INT3 from GPIO */
147 GPIO1_INT2_IRQn = 61, /**< Active HIGH Interrupt from INT2 from GPIO */
148 GPIO1_INT1_IRQn = 62, /**< Active HIGH Interrupt from INT1 from GPIO */
149 GPIO1_INT0_IRQn = 63, /**< Active HIGH Interrupt from INT0 from GPIO */
150 GPIO1_Combined_0_15_IRQn = 64, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
151 GPIO1_Combined_16_31_IRQn = 65, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
152 GPIO2_Combined_0_15_IRQn = 66, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
153 GPIO2_Combined_16_31_IRQn = 67, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */
154 GPIO3_Combined_0_15_IRQn = 68, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */
155 GPIO3_Combined_16_31_IRQn = 69, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */
156 GPIO4_Combined_0_15_IRQn = 70, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */
157 GPIO4_Combined_16_31_IRQn = 71, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */
158 GPIO5_Combined_0_15_IRQn = 72, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
159 GPIO5_Combined_16_31_IRQn = 73, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */
160 PCIE_CTRL2_IRQ0_IRQn = 74, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
161 PCIE_CTRL2_IRQ1_IRQn = 75, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
162 PCIE_CTRL2_IRQ2_IRQn = 76, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
163 PCIE_CTRL2_IRQ3_IRQn = 77, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
164 WDOG1_IRQn = 78, /**< Watchdog Timer reset */
165 WDOG2_IRQn = 79, /**< Watchdog Timer reset */
166 PCIE_CTRL2_IRQn = 80, /**< Channels [63:32] interrupts requests */
167 PWM1_IRQn = 81, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */
168 PWM2_IRQn = 82, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */
169 PWM3_IRQn = 83, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */
170 PWM4_IRQn = 84, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line. */
171 CCM_IRQ1_IRQn = 85, /**< CCM, Interrupt Request 1 */
172 CCM_IRQ2_IRQn = 86, /**< CCM, Interrupt Request 2 */
173 GPC_IRQn = 87, /**< GPC Interrupt Request 1 */
174 MU_A53_IRQn = 88, /**< Interrupt to A53 */
175 SRC_IRQn = 89, /**< SRC interrupt request */
176 I2S56_IRQn = 90, /**< SAI5/6 Receive / Transmit Interrupt */
177 RTIC_IRQn = 91, /**< RTIC Interrupt */
178 CPU_PerformanceUnit_IRQn = 92, /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[n] */
179 CPU_CTI_Trigger_IRQn = 93, /**< CTI trigger outputs (internal: nCTIIRQ[n] */
180 SRC_Combined_IRQn = 94, /**< Combined CPU wdog interrupts (4x) out of SRC. */
181 I2S1_IRQn = 95, /**< SAI1 Receive / Transmit Interrupt */
182 I2S2_IRQn = 96, /**< SAI2 Receive / Transmit Interrupt */
183 MU_M4_IRQn = 97, /**< Interrupt to M4 */
184 DDR_PerformanceMonitor_IRQn = 98, /**< ddr Interrupt for performance monitor */
185 DDR_IRQn = 99, /**< ddr Interrupt */
186 I2S4_IRQn = 100, /**< SAI4 Receive / Transmit Interrupt */
187 CPU_Error_AXI_IRQn = 101, /**< CPU Error indicator for AXI transaction with a write response error condition */
188 CPU_Error_L2RAM_IRQn = 102, /**< CPU Error indicator for L2 RAM double-bit ECC error */
189 SDMA2_IRQn = 103, /**< AND of all 48 SDMA interrupts (events) from all the channels */
190 Reserved120_IRQn = 104, /**< Reserved */
191 CAAM_IRQ0_IRQn = 105, /**< CAAM interrupt queue for JQ */
192 CAAM_IRQ1_IRQn = 106, /**< CAAM interrupt queue for JQ */
193 QSPI_IRQn = 107, /**< QSPI Interrupt */
194 TZASC_IRQn = 108, /**< TZASC (PL380) interrupt */
195 Reserved125_IRQn = 109, /**< Reserved */
196 Reserved126_IRQn = 110, /**< Reserved */
197 Reserved127_IRQn = 111, /**< Reserved */
198 PERFMON1_IRQn = 112, /**< General Interrupt */
199 PERFMON2_IRQn = 113, /**< General Interrupt */
200 CAAM_IRQ2_IRQn = 114, /**< CAAM interrupt queue for JQ */
201 CAAM_ERROR_IRQn = 115, /**< Recoverable error interrupt */
202 HS_CP0_IRQn = 116, /**< HS Interrupt Request */
203 HEVC_IRQn = 117, /**< HEVC interrupt */
204 ENET_MAC0_Rx_Tx_Done1_IRQn = 118, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */
205 ENET_MAC0_Rx_Tx_Done2_IRQn = 119, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */
206 ENET_IRQn = 120, /**< MAC 0 IRQ */
207 ENET_1588_IRQn = 121, /**< MAC 0 1588 Timer Interrupt - synchronous */
208 PCIE_CTRL1_IRQ0_IRQn = 122, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
209 PCIE_CTRL1_IRQ1_IRQn = 123, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
210 PCIE_CTRL1_IRQ2_IRQn = 124, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
211 PCIE_CTRL1_IRQ3_IRQn = 125, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */
212 Reserved142_IRQn = 126, /**< Reserved */
213 PCIE_CTRL1_IRQn = 127 /**< Channels [63:32] interrupts requests */
214} IRQn_Type;
215
216/*!
217 * @}
218 */ /* end of group Interrupt_vector_numbers */
219
220
221/* ----------------------------------------------------------------------------
222 -- Cortex M4 Core Configuration
223 ---------------------------------------------------------------------------- */
224
225/*!
226 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
227 * @{
228 */
229
230#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
231#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
232#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
233#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
234
235#include "core_cm4.h" /* Core Peripheral Access Layer */
236#include "system_MIMX8MQ5_cm4.h" /* Device specific configuration file */
237
238/*!
239 * @}
240 */ /* end of group Cortex_Core_Configuration */
241
242
243/* ----------------------------------------------------------------------------
244 -- Mapping Information
245 ---------------------------------------------------------------------------- */
246
247/*!
248 * @addtogroup Mapping_Information Mapping Information
249 * @{
250 */
251
252/** Mapping Information */
253/*!
254 * @addtogroup iomuxc_pads
255 * @{ */
256
257/*******************************************************************************
258 * Definitions
259*******************************************************************************/
260
261/*!
262 * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
263 *
264 * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
265 */
266typedef enum _iomuxc_sw_mux_ctl_pad
267{
268 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
269 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
270 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
271 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
272 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
273 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
274 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */
275 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */
276 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */
277 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */
278 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */
279 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */
280 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
281 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
282 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
283 kIOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
284 kIOMUXC_SW_MUX_CTL_PAD_ENET_MDC = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */
285 kIOMUXC_SW_MUX_CTL_PAD_ENET_MDIO = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */
286 kIOMUXC_SW_MUX_CTL_PAD_ENET_TD3 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */
287 kIOMUXC_SW_MUX_CTL_PAD_ENET_TD2 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */
288 kIOMUXC_SW_MUX_CTL_PAD_ENET_TD1 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */
289 kIOMUXC_SW_MUX_CTL_PAD_ENET_TD0 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */
290 kIOMUXC_SW_MUX_CTL_PAD_ENET_TX_CTL = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */
291 kIOMUXC_SW_MUX_CTL_PAD_ENET_TXC = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */
292 kIOMUXC_SW_MUX_CTL_PAD_ENET_RX_CTL = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */
293 kIOMUXC_SW_MUX_CTL_PAD_ENET_RXC = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */
294 kIOMUXC_SW_MUX_CTL_PAD_ENET_RD0 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */
295 kIOMUXC_SW_MUX_CTL_PAD_ENET_RD1 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */
296 kIOMUXC_SW_MUX_CTL_PAD_ENET_RD2 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */
297 kIOMUXC_SW_MUX_CTL_PAD_ENET_RD3 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */
298 kIOMUXC_SW_MUX_CTL_PAD_SD1_CLK = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */
299 kIOMUXC_SW_MUX_CTL_PAD_SD1_CMD = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */
300 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA0 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */
301 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA1 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */
302 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA2 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */
303 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA3 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */
304 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA4 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */
305 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA5 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */
306 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA6 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */
307 kIOMUXC_SW_MUX_CTL_PAD_SD1_DATA7 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */
308 kIOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */
309 kIOMUXC_SW_MUX_CTL_PAD_SD1_STROBE = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */
310 kIOMUXC_SW_MUX_CTL_PAD_SD2_CD_B = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */
311 kIOMUXC_SW_MUX_CTL_PAD_SD2_CLK = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */
312 kIOMUXC_SW_MUX_CTL_PAD_SD2_CMD = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */
313 kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */
314 kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */
315 kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */
316 kIOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */
317 kIOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */
318 kIOMUXC_SW_MUX_CTL_PAD_SD2_WP = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */
319 kIOMUXC_SW_MUX_CTL_PAD_NAND_ALE = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */
320 kIOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */
321 kIOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */
322 kIOMUXC_SW_MUX_CTL_PAD_NAND_CE2_B = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */
323 kIOMUXC_SW_MUX_CTL_PAD_NAND_CE3_B = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */
324 kIOMUXC_SW_MUX_CTL_PAD_NAND_CLE = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */
325 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */
326 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */
327 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */
328 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */
329 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */
330 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */
331 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */
332 kIOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */
333 kIOMUXC_SW_MUX_CTL_PAD_NAND_DQS = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */
334 kIOMUXC_SW_MUX_CTL_PAD_NAND_RE_B = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */
335 kIOMUXC_SW_MUX_CTL_PAD_NAND_READY_B = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */
336 kIOMUXC_SW_MUX_CTL_PAD_NAND_WE_B = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */
337 kIOMUXC_SW_MUX_CTL_PAD_NAND_WP_B = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */
338 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXFS = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */
339 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXC = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */
340 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD0 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */
341 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD1 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */
342 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD2 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */
343 kIOMUXC_SW_MUX_CTL_PAD_SAI5_RXD3 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */
344 kIOMUXC_SW_MUX_CTL_PAD_SAI5_MCLK = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */
345 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXFS = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */
346 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXC = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */
347 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD0 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */
348 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD1 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */
349 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD2 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */
350 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD3 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */
351 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD4 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */
352 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD5 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */
353 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD6 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */
354 kIOMUXC_SW_MUX_CTL_PAD_SAI1_RXD7 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */
355 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXFS = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */
356 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXC = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */
357 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD0 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */
358 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD1 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */
359 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD2 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */
360 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD3 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */
361 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD4 = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */
362 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD5 = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */
363 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD6 = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */
364 kIOMUXC_SW_MUX_CTL_PAD_SAI1_TXD7 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */
365 kIOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */
366 kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXFS = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */
367 kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXC = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */
368 kIOMUXC_SW_MUX_CTL_PAD_SAI2_RXD0 = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */
369 kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXFS = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */
370 kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXC = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */
371 kIOMUXC_SW_MUX_CTL_PAD_SAI2_TXD0 = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */
372 kIOMUXC_SW_MUX_CTL_PAD_SAI2_MCLK = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */
373 kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXFS = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */
374 kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXC = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */
375 kIOMUXC_SW_MUX_CTL_PAD_SAI3_RXD = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */
376 kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXFS = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */
377 kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXC = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */
378 kIOMUXC_SW_MUX_CTL_PAD_SAI3_TXD = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */
379 kIOMUXC_SW_MUX_CTL_PAD_SAI3_MCLK = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */
380 kIOMUXC_SW_MUX_CTL_PAD_SPDIF_TX = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */
381 kIOMUXC_SW_MUX_CTL_PAD_SPDIF_RX = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */
382 kIOMUXC_SW_MUX_CTL_PAD_SPDIF_EXT_CLK = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */
383 kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */
384 kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */
385 kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */
386 kIOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */
387 kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */
388 kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */
389 kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */
390 kIOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */
391 kIOMUXC_SW_MUX_CTL_PAD_I2C1_SCL = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */
392 kIOMUXC_SW_MUX_CTL_PAD_I2C1_SDA = 124U, /**< IOMUXC SW_MUX_CTL_PAD index */
393 kIOMUXC_SW_MUX_CTL_PAD_I2C2_SCL = 125U, /**< IOMUXC SW_MUX_CTL_PAD index */
394 kIOMUXC_SW_MUX_CTL_PAD_I2C2_SDA = 126U, /**< IOMUXC SW_MUX_CTL_PAD index */
395 kIOMUXC_SW_MUX_CTL_PAD_I2C3_SCL = 127U, /**< IOMUXC SW_MUX_CTL_PAD index */
396 kIOMUXC_SW_MUX_CTL_PAD_I2C3_SDA = 128U, /**< IOMUXC SW_MUX_CTL_PAD index */
397 kIOMUXC_SW_MUX_CTL_PAD_I2C4_SCL = 129U, /**< IOMUXC SW_MUX_CTL_PAD index */
398 kIOMUXC_SW_MUX_CTL_PAD_I2C4_SDA = 130U, /**< IOMUXC SW_MUX_CTL_PAD index */
399 kIOMUXC_SW_MUX_CTL_PAD_UART1_RXD = 131U, /**< IOMUXC SW_MUX_CTL_PAD index */
400 kIOMUXC_SW_MUX_CTL_PAD_UART1_TXD = 132U, /**< IOMUXC SW_MUX_CTL_PAD index */
401 kIOMUXC_SW_MUX_CTL_PAD_UART2_RXD = 133U, /**< IOMUXC SW_MUX_CTL_PAD index */
402 kIOMUXC_SW_MUX_CTL_PAD_UART2_TXD = 134U, /**< IOMUXC SW_MUX_CTL_PAD index */
403 kIOMUXC_SW_MUX_CTL_PAD_UART3_RXD = 135U, /**< IOMUXC SW_MUX_CTL_PAD index */
404 kIOMUXC_SW_MUX_CTL_PAD_UART3_TXD = 136U, /**< IOMUXC SW_MUX_CTL_PAD index */
405 kIOMUXC_SW_MUX_CTL_PAD_UART4_RXD = 137U, /**< IOMUXC SW_MUX_CTL_PAD index */
406 kIOMUXC_SW_MUX_CTL_PAD_UART4_TXD = 138U, /**< IOMUXC SW_MUX_CTL_PAD index */
407} iomuxc_sw_mux_ctl_pad_t;
408
409/*!
410 * @addtogroup iomuxc_pads
411 * @{ */
412
413/*******************************************************************************
414 * Definitions
415*******************************************************************************/
416
417/*!
418 * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
419 *
420 * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
421 */
422typedef enum _iomuxc_sw_pad_ctl_pad
423{
424 kIOMUXC_SW_PAD_CTL_PAD_TEST_MODE = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */
425 kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE0 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */
426 kIOMUXC_SW_PAD_CTL_PAD_BOOT_MODE1 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */
427 kIOMUXC_SW_PAD_CTL_PAD_JTAG_MOD = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */
428 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */
429 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDI = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */
430 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TMS = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */
431 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TCK = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */
432 kIOMUXC_SW_PAD_CTL_PAD_JTAG_TDO = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */
433 kIOMUXC_SW_PAD_CTL_PAD_RTC = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */
434 kIOMUXC_SW_PAD_CTL_PAD_PMIC_STBY_REQ = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */
435 kIOMUXC_SW_PAD_CTL_PAD_PMIC_ON_REQ = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */
436 kIOMUXC_SW_PAD_CTL_PAD_ONOFF = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */
437 kIOMUXC_SW_PAD_CTL_PAD_POR_B = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */
438 kIOMUXC_SW_PAD_CTL_PAD_RTC_RESET_B = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */
439 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */
440 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */
441 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */
442 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */
443 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */
444 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */
445 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */
446 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */
447 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */
448 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */
449 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */
450 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */
451 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */
452 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */
453 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */
454 kIOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */
455 kIOMUXC_SW_PAD_CTL_PAD_ENET_MDC = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */
456 kIOMUXC_SW_PAD_CTL_PAD_ENET_MDIO = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */
457 kIOMUXC_SW_PAD_CTL_PAD_ENET_TD3 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */
458 kIOMUXC_SW_PAD_CTL_PAD_ENET_TD2 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */
459 kIOMUXC_SW_PAD_CTL_PAD_ENET_TD1 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */
460 kIOMUXC_SW_PAD_CTL_PAD_ENET_TD0 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */
461 kIOMUXC_SW_PAD_CTL_PAD_ENET_TX_CTL = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */
462 kIOMUXC_SW_PAD_CTL_PAD_ENET_TXC = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */
463 kIOMUXC_SW_PAD_CTL_PAD_ENET_RX_CTL = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */
464 kIOMUXC_SW_PAD_CTL_PAD_ENET_RXC = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */
465 kIOMUXC_SW_PAD_CTL_PAD_ENET_RD0 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */
466 kIOMUXC_SW_PAD_CTL_PAD_ENET_RD1 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */
467 kIOMUXC_SW_PAD_CTL_PAD_ENET_RD2 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */
468 kIOMUXC_SW_PAD_CTL_PAD_ENET_RD3 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */
469 kIOMUXC_SW_PAD_CTL_PAD_SD1_CLK = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */
470 kIOMUXC_SW_PAD_CTL_PAD_SD1_CMD = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */
471 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA0 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */
472 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA1 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */
473 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA2 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */
474 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA3 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */
475 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA4 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */
476 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA5 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */
477 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA6 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */
478 kIOMUXC_SW_PAD_CTL_PAD_SD1_DATA7 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */
479 kIOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */
480 kIOMUXC_SW_PAD_CTL_PAD_SD1_STROBE = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */
481 kIOMUXC_SW_PAD_CTL_PAD_SD2_CD_B = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */
482 kIOMUXC_SW_PAD_CTL_PAD_SD2_CLK = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */
483 kIOMUXC_SW_PAD_CTL_PAD_SD2_CMD = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */
484 kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */
485 kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */
486 kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */
487 kIOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */
488 kIOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */
489 kIOMUXC_SW_PAD_CTL_PAD_SD2_WP = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */
490 kIOMUXC_SW_PAD_CTL_PAD_NAND_ALE = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */
491 kIOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */
492 kIOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */
493 kIOMUXC_SW_PAD_CTL_PAD_NAND_CE2_B = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */
494 kIOMUXC_SW_PAD_CTL_PAD_NAND_CE3_B = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */
495 kIOMUXC_SW_PAD_CTL_PAD_NAND_CLE = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */
496 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA00 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */
497 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA01 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */
498 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA02 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */
499 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA03 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */
500 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA04 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */
501 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA05 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */
502 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA06 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */
503 kIOMUXC_SW_PAD_CTL_PAD_NAND_DATA07 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */
504 kIOMUXC_SW_PAD_CTL_PAD_NAND_DQS = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */
505 kIOMUXC_SW_PAD_CTL_PAD_NAND_RE_B = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */
506 kIOMUXC_SW_PAD_CTL_PAD_NAND_READY_B = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */
507 kIOMUXC_SW_PAD_CTL_PAD_NAND_WE_B = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */
508 kIOMUXC_SW_PAD_CTL_PAD_NAND_WP_B = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */
509 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXFS = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */
510 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXC = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */
511 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD0 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */
512 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD1 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */
513 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD2 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */
514 kIOMUXC_SW_PAD_CTL_PAD_SAI5_RXD3 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */
515 kIOMUXC_SW_PAD_CTL_PAD_SAI5_MCLK = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */
516 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXFS = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */
517 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXC = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */
518 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD0 = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */
519 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD1 = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */
520 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD2 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */
521 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD3 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */
522 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD4 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */
523 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD5 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */
524 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD6 = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */
525 kIOMUXC_SW_PAD_CTL_PAD_SAI1_RXD7 = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */
526 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXFS = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */
527 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXC = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */
528 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD0 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */
529 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD1 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */
530 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD2 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */
531 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD3 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */
532 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD4 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */
533 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD5 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */
534 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD6 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */
535 kIOMUXC_SW_PAD_CTL_PAD_SAI1_TXD7 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */
536 kIOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK = 112U, /**< IOMUXC SW_PAD_CTL_PAD index */
537 kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXFS = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */
538 kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXC = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */
539 kIOMUXC_SW_PAD_CTL_PAD_SAI2_RXD0 = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */
540 kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXFS = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */
541 kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXC = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */
542 kIOMUXC_SW_PAD_CTL_PAD_SAI2_TXD0 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */
543 kIOMUXC_SW_PAD_CTL_PAD_SAI2_MCLK = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */
544 kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXFS = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */
545 kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXC = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */
546 kIOMUXC_SW_PAD_CTL_PAD_SAI3_RXD = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */
547 kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXFS = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */
548 kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXC = 124U, /**< IOMUXC SW_PAD_CTL_PAD index */
549 kIOMUXC_SW_PAD_CTL_PAD_SAI3_TXD = 125U, /**< IOMUXC SW_PAD_CTL_PAD index */
550 kIOMUXC_SW_PAD_CTL_PAD_SAI3_MCLK = 126U, /**< IOMUXC SW_PAD_CTL_PAD index */
551 kIOMUXC_SW_PAD_CTL_PAD_SPDIF_TX = 127U, /**< IOMUXC SW_PAD_CTL_PAD index */
552 kIOMUXC_SW_PAD_CTL_PAD_SPDIF_RX = 128U, /**< IOMUXC SW_PAD_CTL_PAD index */
553 kIOMUXC_SW_PAD_CTL_PAD_SPDIF_EXT_CLK = 129U, /**< IOMUXC SW_PAD_CTL_PAD index */
554 kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK = 130U, /**< IOMUXC SW_PAD_CTL_PAD index */
555 kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI = 131U, /**< IOMUXC SW_PAD_CTL_PAD index */
556 kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO = 132U, /**< IOMUXC SW_PAD_CTL_PAD index */
557 kIOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0 = 133U, /**< IOMUXC SW_PAD_CTL_PAD index */
558 kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK = 134U, /**< IOMUXC SW_PAD_CTL_PAD index */
559 kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI = 135U, /**< IOMUXC SW_PAD_CTL_PAD index */
560 kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO = 136U, /**< IOMUXC SW_PAD_CTL_PAD index */
561 kIOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0 = 137U, /**< IOMUXC SW_PAD_CTL_PAD index */
562 kIOMUXC_SW_PAD_CTL_PAD_I2C1_SCL = 138U, /**< IOMUXC SW_PAD_CTL_PAD index */
563 kIOMUXC_SW_PAD_CTL_PAD_I2C1_SDA = 139U, /**< IOMUXC SW_PAD_CTL_PAD index */
564 kIOMUXC_SW_PAD_CTL_PAD_I2C2_SCL = 140U, /**< IOMUXC SW_PAD_CTL_PAD index */
565 kIOMUXC_SW_PAD_CTL_PAD_I2C2_SDA = 141U, /**< IOMUXC SW_PAD_CTL_PAD index */
566 kIOMUXC_SW_PAD_CTL_PAD_I2C3_SCL = 142U, /**< IOMUXC SW_PAD_CTL_PAD index */
567 kIOMUXC_SW_PAD_CTL_PAD_I2C3_SDA = 143U, /**< IOMUXC SW_PAD_CTL_PAD index */
568 kIOMUXC_SW_PAD_CTL_PAD_I2C4_SCL = 144U, /**< IOMUXC SW_PAD_CTL_PAD index */
569 kIOMUXC_SW_PAD_CTL_PAD_I2C4_SDA = 145U, /**< IOMUXC SW_PAD_CTL_PAD index */
570 kIOMUXC_SW_PAD_CTL_PAD_UART1_RXD = 146U, /**< IOMUXC SW_PAD_CTL_PAD index */
571 kIOMUXC_SW_PAD_CTL_PAD_UART1_TXD = 147U, /**< IOMUXC SW_PAD_CTL_PAD index */
572 kIOMUXC_SW_PAD_CTL_PAD_UART2_RXD = 148U, /**< IOMUXC SW_PAD_CTL_PAD index */
573 kIOMUXC_SW_PAD_CTL_PAD_UART2_TXD = 149U, /**< IOMUXC SW_PAD_CTL_PAD index */
574 kIOMUXC_SW_PAD_CTL_PAD_UART3_RXD = 150U, /**< IOMUXC SW_PAD_CTL_PAD index */
575 kIOMUXC_SW_PAD_CTL_PAD_UART3_TXD = 151U, /**< IOMUXC SW_PAD_CTL_PAD index */
576 kIOMUXC_SW_PAD_CTL_PAD_UART4_RXD = 152U, /**< IOMUXC SW_PAD_CTL_PAD index */
577 kIOMUXC_SW_PAD_CTL_PAD_UART4_TXD = 153U, /**< IOMUXC SW_PAD_CTL_PAD index */
578} iomuxc_sw_pad_ctl_pad_t;
579
580/* @} */
581
582/*!
583 * @brief Enumeration for the IOMUXC select input
584 *
585 * Defines the enumeration for the IOMUXC select input collections.
586 */
587typedef enum _iomuxc_select_input
588{
589 kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 0U, /**< IOMUXC select input index */
590 kIOMUXC_ENET1_MDIO_SELECT_INPUT = 1U, /**< IOMUXC select input index */
591 kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 2U, /**< IOMUXC select input index */
592 kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 3U, /**< IOMUXC select input index */
593 kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 4U, /**< IOMUXC select input index */
594 kIOMUXC_SAI5_RX_BCLK_SELECT_INPUT = 5U, /**< IOMUXC select input index */
595 kIOMUXC_SAI5_RXD0_SELECT_INPUT = 6U, /**< IOMUXC select input index */
596 kIOMUXC_SAI5_RXD1_SELECT_INPUT = 7U, /**< IOMUXC select input index */
597 kIOMUXC_SAI5_RXD2_SELECT_INPUT = 8U, /**< IOMUXC select input index */
598 kIOMUXC_SAI5_RXD3_SELECT_INPUT = 9U, /**< IOMUXC select input index */
599 kIOMUXC_SAI5_RX_SYNC_SELECT_INPUT = 10U, /**< IOMUXC select input index */
600 kIOMUXC_SAI5_TX_BCLK_SELECT_INPUT = 11U, /**< IOMUXC select input index */
601 kIOMUXC_SAI5_TX_SYNC_SELECT_INPUT = 12U, /**< IOMUXC select input index */
602 kIOMUXC_UART1_RTS_B_SELECT_INPUT = 13U, /**< IOMUXC select input index */
603 kIOMUXC_UART1_RXD_SELECT_INPUT = 14U, /**< IOMUXC select input index */
604 kIOMUXC_UART2_RTS_B_SELECT_INPUT = 15U, /**< IOMUXC select input index */
605 kIOMUXC_UART2_RXD_SELECT_INPUT = 16U, /**< IOMUXC select input index */
606 kIOMUXC_UART3_RTS_B_SELECT_INPUT = 17U, /**< IOMUXC select input index */
607 kIOMUXC_UART3_RXD_SELECT_INPUT = 18U, /**< IOMUXC select input index */
608 kIOMUXC_UART4_RTS_B_SELECT_INPUT = 19U, /**< IOMUXC select input index */
609 kIOMUXC_UART4_RXD_SELECT_INPUT = 20U, /**< IOMUXC select input index */
610 kIOMUXC_SAI6_RX_BCLK_SELECT_INPUT = 21U, /**< IOMUXC select input index */
611 kIOMUXC_SAI6_RXD0_SELECT_INPUT = 22U, /**< IOMUXC select input index */
612 kIOMUXC_SAI6_RX_SYNC_SELECT_INPUT = 23U, /**< IOMUXC select input index */
613 kIOMUXC_SAI6_TX_BCLK_SELECT_INPUT = 24U, /**< IOMUXC select input index */
614 kIOMUXC_SAI6_TX_SYNC_SELECT_INPUT = 25U, /**< IOMUXC select input index */
615 kIOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT = 26U, /**< IOMUXC select input index */
616 kIOMUXC_PCIE2_CLKREQ_B_SELECT_INPUT = 27U, /**< IOMUXC select input index */
617 kIOMUXC_SAI5_MCLK_SELECT_INPUT = 28U, /**< IOMUXC select input index */
618 kIOMUXC_SAI6_MCLK_SELECT_INPUT = 29U, /**< IOMUXC select input index */
619} iomuxc_select_input_t;
620
621/*!
622 * @addtogroup rdc_mapping
623 * @{
624 */
625
626/*******************************************************************************
627 * Definitions
628 ******************************************************************************/
629
630/*!
631 * @brief Structure for the RDC mapping
632 *
633 * Defines the structure for the RDC resource collections.
634 */
635
636typedef enum _rdc_master
637{
638 kRDC_Master_A53 = 0U, /**< ARM Cortex-A53 RDC Master */
639 kRDC_Master_M4 = 1U, /**< ARM Cortex-M4 RDC Master */
640 kRDC_Master_PCIE1 = 2U, /**< PCIE1 RDC Master */
641 kRDC_Master_PCIE2 = 3U, /**< PCIE2 RDC Master */
642 kRDC_Master_VPU = 4U, /**< VPU RDC Master */
643 kRDC_Master_LCDIF = 5U, /**< LCDIF RDC Master */
644 kRDC_Master_CSI1 = 6U, /**< CSI1 PORT RDC Master */
645 kRDC_Master_CSI2 = 7U, /**< CSI2 RDC Master */
646 kRDC_Master_Coresight = 8U, /**< CORESIGHT RDC Master */
647 kRDC_Master_DAP = 9U, /**< DAP RDC Master */
648 kRDC_Master_CAAM = 10U, /**< CAAM RDC Master */
649 kRDC_Master_SDMA1_PERIPH = 11U, /**< SDMA1 PERIPHERAL RDC Master */
650 kRDC_Master_SDMA1_BURST = 12U, /**< SDMA1 BURST RDC Master */
651 kRDC_Master_APBHDMA = 13U, /**< APBH DMA RDC Master */
652 kRDC_Master_RAWNAND = 14U, /**< RAW NAND RDC Master */
653 kRDC_Master_USDHC1 = 15U, /**< USDHC1 RDC Master */
654 kRDC_Master_USDHC2 = 16U, /**< USDHC2 RDC Master */
655 kRDC_Master_DP = 17U, /**< DP RDC Master */
656 kRDC_Master_GPU = 18U, /**< GPU RDC Master */
657 kRDC_Master_USB1 = 19U, /**< USB1 RDC Master */
658 kRDC_Master_USB2 = 20U, /**< USB2 RDC Master */
659 kRDC_Master_TESTPORT = 21U, /**< TESTPORT RDC Master */
660 kRDC_Master_ENET1TX = 22U, /**< ENET1 TX RDC Master */
661 kRDC_Master_ENET1RX = 23U, /**< ENET1 RX RDC Master */
662 kRDC_Master_SDMA2_PERIPH = 24U, /**< SDMA2 PERIPH RDC Master */
663 kRDC_Master_SDMA2_BURST = 24U, /**< SDMA2 BURST RDC Master */
664 kRDC_Master_SDMA2_SPDA2 = 24U, /**< SDMA2 to SPDA2 RDC Master */
665 kRDC_Master_SDMA1_SPBA1 = 26U, /**< SDMA1 to SPBA1 RDC Master */
666} rdc_master_t;
667
668typedef enum _rdc_mem
669{
670 kRDC_Mem_MRC0_0 = 0U, /**< MMDC/DRAM. Region resolution 4KB. */
671 kRDC_Mem_MRC0_1 = 1U,
672 kRDC_Mem_MRC0_2 = 2U,
673 kRDC_Mem_MRC0_3 = 3U,
674 kRDC_Mem_MRC0_4 = 4U,
675 kRDC_Mem_MRC0_5 = 5U,
676 kRDC_Mem_MRC0_6 = 6U,
677 kRDC_Mem_MRC0_7 = 7U,
678 kRDC_Mem_MRC1_0 = 8U, /**< PCIE2. Region resolution 4KB. */
679 kRDC_Mem_MRC1_1 = 9U,
680 kRDC_Mem_MRC1_2 = 10U,
681 kRDC_Mem_MRC1_3 = 11U,
682 kRDC_Mem_MRC2_0 = 12U, /**< QSPI. Region resolution 4KB. */
683 kRDC_Mem_MRC2_1 = 13U,
684 kRDC_Mem_MRC2_2 = 14U,
685 kRDC_Mem_MRC2_3 = 15U,
686 kRDC_Mem_MRC2_4 = 16U,
687 kRDC_Mem_MRC2_5 = 17U,
688 kRDC_Mem_MRC2_6 = 18U,
689 kRDC_Mem_MRC2_7 = 19U,
690 kRDC_Mem_MRC3_0 = 20U, /**< PCIE1. Region resolution 4KB. */
691 kRDC_Mem_MRC3_1 = 21U,
692 kRDC_Mem_MRC3_2 = 22U,
693 kRDC_Mem_MRC3_3 = 23U,
694 kRDC_Mem_MRC4_0 = 24U, /**< OCRAM. Region resolution 128B. */
695 kRDC_Mem_MRC4_1 = 25U,
696 kRDC_Mem_MRC4_2 = 26U,
697 kRDC_Mem_MRC4_3 = 27U,
698 kRDC_Mem_MRC4_4 = 28U,
699 kRDC_Mem_MRC5_0 = 29U, /**< OCRAM_S. Region resolution 128B. */
700 kRDC_Mem_MRC5_1 = 30U,
701 kRDC_Mem_MRC5_2 = 31U,
702 kRDC_Mem_MRC5_3 = 32U,
703 kRDC_Mem_MRC5_4 = 33U,
704 kRDC_Mem_MRC6_0 = 34U, /**< TCM. Region resolution 128B. */
705 kRDC_Mem_MRC6_1 = 35U,
706 kRDC_Mem_MRC6_2 = 36U,
707 kRDC_Mem_MRC6_3 = 37U,
708 kRDC_Mem_MRC6_4 = 38U,
709 kRDC_Mem_MRC7_0 = 39U, /**< GIC. Region resolution 4KB. */
710 kRDC_Mem_MRC7_1 = 40U,
711 kRDC_Mem_MRC7_2 = 41U,
712 kRDC_Mem_MRC7_3 = 42U,
713 kRDC_Mem_MRC8_0 = 43U, /**< USBMIX. Region resolution 4KB. */
714 kRDC_Mem_MRC8_1 = 44U,
715 kRDC_Mem_MRC8_2 = 45U,
716 kRDC_Mem_MRC8_3 = 46U,
717 kRDC_Mem_MRC9_0 = 47U, /**< GPU. Region resolution 4KB. */
718 kRDC_Mem_MRC9_1 = 48U,
719 kRDC_Mem_MRC9_2 = 49U,
720 kRDC_Mem_MRC9_3 = 50U,
721 kRDC_Mem_MRC10_0 = 51U, /**< VPU(Decoder). Region resolution 4KB. */
722 kRDC_Mem_MRC10_1 = 52U,
723 kRDC_Mem_MRC10_2 = 53U,
724 kRDC_Mem_MRC10_3 = 54U,
725 kRDC_Mem_MRC11_0 = 55U, /**< DEBUG(DAP). Region resolution 4KB. */
726 kRDC_Mem_MRC11_1 = 56U,
727 kRDC_Mem_MRC11_2 = 57U,
728 kRDC_Mem_MRC11_3 = 58U,
729 kRDC_Mem_MRC12_0 = 59U, /**< DDRC(REG). Region resolution 4KB. */
730 kRDC_Mem_MRC12_1 = 60U,
731 kRDC_Mem_MRC12_2 = 61U,
732 kRDC_Mem_MRC12_3 = 62U,
733 kRDC_Mem_MRC12_4 = 63U,
734} rdc_mem_t;
735
736typedef enum _rdc_periph
737{
738 kRDC_Periph_GPIO1 = 0U, /**< GPIO1 RDC Peripheral */
739 kRDC_Periph_GPIO2 = 1U, /**< GPIO2 RDC Peripheral */
740 kRDC_Periph_GPIO3 = 2U, /**< GPIO3 RDC Peripheral */
741 kRDC_Periph_GPIO4 = 3U, /**< GPIO4 RDC Peripheral */
742 kRDC_Periph_GPIO5 = 4U, /**< GPIO5 RDC Peripheral */
743 kRDC_Periph_ANA_TSENSOR = 6U, /**< ANA_TSENSOR RDC Peripheral */
744 kRDC_Periph_ANA_OSC = 7U, /**< ANA_OSC RDC Peripheral */
745 kRDC_Periph_WDOG1 = 8U, /**< WDOG1 RDC Peripheral */
746 kRDC_Periph_WDOG2 = 9U, /**< WDOG2 RDC Peripheral */
747 kRDC_Periph_WDOG3 = 10U, /**< WDOG3 RDC Peripheral */
748 kRDC_Periph_SDMA2 = 12U, /**< SDMA2 RDC Peripheral */
749 kRDC_Periph_GPT1 = 13U, /**< GPT1 RDC Peripheral */
750 kRDC_Periph_GPT2 = 14U, /**< GPT2 RDC Peripheral */
751 kRDC_Periph_GPT3 = 15U, /**< GPT3 RDC Peripheral */
752 kRDC_Periph_ROMCP = 17U, /**< ROMCP RDC Peripheral */
753 kRDC_Periph_LCDIF = 18U, /**< LCDIF RDC Peripheral */
754 kRDC_Periph_IOMUXC = 19U, /**< IOMUXC RDC Peripheral */
755 kRDC_Periph_IOMUXC_GPR = 20U, /**< IOMUXC_GPR RDC Peripheral */
756 kRDC_Periph_OCOTP_CTRL = 21U, /**< OCOTP_CTRL RDC Peripheral */
757 kRDC_Periph_ANA_PLL = 22U, /**< ANA_PLL RDC Peripheral */
758 kRDC_Periph_SNVS_HP = 23U, /**< SNVS_HP GPR RDC Peripheral */
759 kRDC_Periph_CCM = 24U, /**< CCM RDC Peripheral */
760 kRDC_Periph_SRC = 25U, /**< SRC RDC Peripheral */
761 kRDC_Periph_GPC = 26U, /**< GPC RDC Peripheral */
762 kRDC_Periph_SEMAPHORE1 = 27U, /**< SEMAPHORE1 RDC Peripheral */
763 kRDC_Periph_SEMAPHORE2 = 28U, /**< SEMAPHORE2 RDC Peripheral */
764 kRDC_Periph_RDC = 29U, /**< RDC RDC Peripheral */
765 kRDC_Periph_CSU = 30U, /**< CSU RDC Peripheral */
766 kRDC_Periph_DC_MST0 = 32U, /**< DC_MST0 RDC Peripheral */
767 kRDC_Periph_DC_MST1 = 33U, /**< DC_MST1 RDC Peripheral */
768 kRDC_Periph_DC_MST2 = 34U, /**< DC_MST2 RDC Peripheral */
769 kRDC_Periph_DC_MST3 = 35U, /**< DC_MST3 RDC Peripheral */
770 kRDC_Periph_HDMI_SEC = 36U, /**< HDMI_SEC RDC Peripheral */
771 kRDC_Periph_PWM1 = 38U, /**< PWM1 RDC Peripheral */
772 kRDC_Periph_PWM2 = 39U, /**< PWM2 RDC Peripheral */
773 kRDC_Periph_PWM3 = 40U, /**< PWM3 RDC Peripheral */
774 kRDC_Periph_PWM4 = 41U, /**< PWM4 RDC Peripheral */
775 kRDC_Periph_SYS_COUNTER_RD = 42U, /**< System counter read RDC Peripheral */
776 kRDC_Periph_SYS_COUNTER_CMP = 43U, /**< System counter compare RDC Peripheral */
777 kRDC_Periph_SYS_COUNTER_CTRL = 44U, /**< System counter control RDC Peripheral */
778 kRDC_Periph_HDMI_CTRL = 45U, /**< HDMI_CTRL RDC Peripheral */
779 kRDC_Periph_GPT6 = 46U, /**< GPT6 RDC Peripheral */
780 kRDC_Periph_GPT5 = 47U, /**< GPT5 RDC Peripheral */
781 kRDC_Periph_GPT4 = 48U, /**< GPT4 RDC Peripheral */
782 kRDC_Periph_TZASC = 56U, /**< TZASC RDC Peripheral */
783 kRDC_Periph_MTR = 59U, /**< MTR RDC Peripheral */
784 kRDC_Periph_PERFMON1 = 60U, /**< PERFMON1 RDC Peripheral */
785 kRDC_Periph_PERFMON2 = 61U, /**< PERFMON2 RDC Peripheral */
786 kRDC_Periph_PLATFORM_CTRL = 62U, /**< PLATFORM_CTRL RDC Peripheral */
787 kRDC_Periph_QOSC = 63U, /**< QOSC RDC Peripheral */
788 kRDC_Periph_MIPI_PHY = 64U, /**< MIPI_PHY RDC Peripheral */
789 kRDC_Periph_MIPI_DSI = 65U, /**< MIPI_DSI RDC Peripheral */
790 kRDC_Periph_I2C1 = 66U, /**< I2C1 RDC Peripheral */
791 kRDC_Periph_I2C2 = 67U, /**< I2C2 RDC Peripheral */
792 kRDC_Periph_I2C3 = 68U, /**< I2C3 RDC Peripheral */
793 kRDC_Periph_I2C4 = 69U, /**< I2C4 RDC Peripheral */
794 kRDC_Periph_UART4 = 70U, /**< UART4 RDC Peripheral */
795 kRDC_Periph_MIPI_CSI1 = 71U, /**< MIPI_CSI1 RDC Peripheral */
796 kRDC_Periph_MIPI_CSI_PHY1 = 72U, /**< MIPI_CSI_PHY1 RDC Peripheral */
797 kRDC_Periph_CSI1 = 73U, /**< CSI1 RDC Peripheral */
798 kRDC_Periph_MU_A = 74U, /**< MU_A RDC Peripheral */
799 kRDC_Periph_MU_B = 75U, /**< MU_B RDC Peripheral */
800 kRDC_Periph_SEMAPHORE_HS = 76U, /**< SEMAPHORE_HS RDC Peripheral */
801 kRDC_Periph_SAI1 = 78U, /**< SAI1 RDC Peripheral */
802 kRDC_Periph_SAI6 = 80U, /**< SAI6 RDC Peripheral */
803 kRDC_Periph_SAI5 = 81U, /**< SAI5 RDC Peripheral */
804 kRDC_Periph_SAI4 = 82U, /**< SAI4 RDC Peripheral */
805 kRDC_Periph_USDHC1 = 84U, /**< USDHC1 RDC Peripheral */
806 kRDC_Periph_USDHC2 = 85U, /**< USDHC2 RDC Peripheral */
807 kRDC_Periph_MIPI_CSI2 = 86U, /**< MIPI_CSI2 RDC Peripheral */
808 kRDC_Periph_MIPI_CSI_PHY2 = 87U, /**< MIPI_CSI_PHY2 RDC Peripheral */
809 kRDC_Periph_CSI2 = 88U, /**< CSI2 RDC Peripheral */
810 kRDC_Periph_SPBA2 = 90U, /**< SPBA2 RDC Peripheral */
811 kRDC_Periph_QSPI = 91U, /**< QSPI RDC Peripheral */
812 kRDC_Periph_SDMA1 = 93U, /**< SDMA1 RDC Peripheral */
813 kRDC_Periph_ENET1 = 94U, /**< ENET1 RDC Peripheral */
814 kRDC_Periph_SPDIF1 = 97U, /**< SPDIF1 RDC Peripheral */
815 kRDC_Periph_ECSPI1 = 98U, /**< ECSPI1 RDC Peripheral */
816 kRDC_Periph_ECSPI2 = 99U, /**< ECSPI2 RDC Peripheral */
817 kRDC_Periph_ECSPI3 = 100U, /**< ECSPI3 RDC Peripheral */
818 kRDC_Periph_UART1 = 102U, /**< UART1 RDC Peripheral */
819 kRDC_Periph_UART3 = 104U, /**< UART3 RDC Peripheral */
820 kRDC_Periph_UART2 = 105U, /**< UART2 RDC Peripheral */
821 kRDC_Periph_SPDIF2 = 106U, /**< SPDIF2 RDC Peripheral */
822 kRDC_Periph_SAI2 = 107U, /**< SAI2 RDC Peripheral */
823 kRDC_Periph_SAI3 = 108U, /**< SAI3 RDC Peripheral */
824 kRDC_Periph_SPBA1 = 111U, /**< SPBA1 RDC Peripheral */
825 kRDC_Periph_CAAM = 114U, /**< CAAM RDC Peripheral */
826} rdc_periph_t;
827
828/* @} */
829
830
831/*!
832 * @}
833 */ /* end of group Mapping_Information */
834
835
836/* ----------------------------------------------------------------------------
837 -- Device Peripheral Access Layer
838 ---------------------------------------------------------------------------- */
839
840/*!
841 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
842 * @{
843 */
844
845
846/*
847** Start of section using anonymous unions
848*/
849
850#if defined(__ARMCC_VERSION)
851 #if (__ARMCC_VERSION >= 6010050)
852 #pragma clang diagnostic push
853 #else
854 #pragma push
855 #pragma anon_unions
856 #endif
857#elif defined(__GNUC__)
858 /* anonymous unions are enabled by default */
859#elif defined(__IAR_SYSTEMS_ICC__)
860 #pragma language=extended
861#else
862 #error Not supported compiler type
863#endif
864
865/* ----------------------------------------------------------------------------
866 -- AIPSTZ Peripheral Access Layer
867 ---------------------------------------------------------------------------- */
868
869/*!
870 * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer
871 * @{
872 */
873
874/** AIPSTZ - Register Layout Typedef */
875typedef struct {
876 __IO uint32_t MPR; /**< MPR, offset: 0x0 */
877 uint8_t RESERVED_0[60];
878 __IO uint32_t OPACR; /**< OPACR, offset: 0x40 */
879 __IO uint32_t OPACR1; /**< OPACR1, offset: 0x44 */
880 __IO uint32_t OPACR2; /**< OPACR2, offset: 0x48 */
881 __IO uint32_t OPACR3; /**< OPACR3, offset: 0x4C */
882 __IO uint32_t OPACR4; /**< OPACR4, offset: 0x50 */
883} AIPSTZ_Type;
884
885/* ----------------------------------------------------------------------------
886 -- AIPSTZ Register Masks
887 ---------------------------------------------------------------------------- */
888
889/*!
890 * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks
891 * @{
892 */
893
894/*! @name MPR - MPR */
895/*! @{ */
896#define AIPSTZ_MPR_MPROT5_MASK (0xF00U)
897#define AIPSTZ_MPR_MPROT5_SHIFT (8U)
898#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
899#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
900#define AIPSTZ_MPR_MPROT3_SHIFT (16U)
901#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
902#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
903#define AIPSTZ_MPR_MPROT2_SHIFT (20U)
904#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
905#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
906#define AIPSTZ_MPR_MPROT1_SHIFT (24U)
907#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
908#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
909#define AIPSTZ_MPR_MPROT0_SHIFT (28U)
910#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
911/*! @} */
912
913/*! @name OPACR - OPACR */
914/*! @{ */
915#define AIPSTZ_OPACR_OPAC7_MASK (0xFU)
916#define AIPSTZ_OPACR_OPAC7_SHIFT (0U)
917#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
918#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
919#define AIPSTZ_OPACR_OPAC6_SHIFT (4U)
920#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
921#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
922#define AIPSTZ_OPACR_OPAC5_SHIFT (8U)
923#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
924#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
925#define AIPSTZ_OPACR_OPAC4_SHIFT (12U)
926#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
927#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
928#define AIPSTZ_OPACR_OPAC3_SHIFT (16U)
929#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
930#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
931#define AIPSTZ_OPACR_OPAC2_SHIFT (20U)
932#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
933#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
934#define AIPSTZ_OPACR_OPAC1_SHIFT (24U)
935#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
936#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
937#define AIPSTZ_OPACR_OPAC0_SHIFT (28U)
938#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
939/*! @} */
940
941/*! @name OPACR1 - OPACR1 */
942/*! @{ */
943#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
944#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
945#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
946#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
947#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
948#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
949#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
950#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
951#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
952#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
953#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
954#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
955#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
956#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
957#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
958#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
959#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
960#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
961#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
962#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
963#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
964#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
965#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
966#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
967/*! @} */
968
969/*! @name OPACR2 - OPACR2 */
970/*! @{ */
971#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
972#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
973#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
974#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
975#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
976#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
977#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
978#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
979#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
980#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
981#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
982#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
983#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
984#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
985#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
986#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
987#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
988#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
989#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
990#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
991#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
992#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
993#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
994#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
995/*! @} */
996
997/*! @name OPACR3 - OPACR3 */
998/*! @{ */
999#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
1000#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
1001#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
1002#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
1003#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
1004#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
1005#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
1006#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
1007#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
1008#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
1009#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
1010#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
1011#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
1012#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
1013#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
1014#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
1015#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
1016#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
1017#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
1018#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
1019#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
1020#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
1021#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
1022#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
1023/*! @} */
1024
1025/*! @name OPACR4 - OPACR4 */
1026/*! @{ */
1027#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
1028#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
1029#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
1030#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
1031#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
1032#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
1033/*! @} */
1034
1035
1036/*!
1037 * @}
1038 */ /* end of group AIPSTZ_Register_Masks */
1039
1040
1041/* AIPSTZ - Peripheral instance base addresses */
1042/** Peripheral AIPSTZ1 base address */
1043#define AIPSTZ1_BASE (0x301F0000u)
1044/** Peripheral AIPSTZ1 base pointer */
1045#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)
1046/** Peripheral AIPSTZ2 base address */
1047#define AIPSTZ2_BASE (0x305F0000u)
1048/** Peripheral AIPSTZ2 base pointer */
1049#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)
1050/** Peripheral AIPSTZ3 base address */
1051#define AIPSTZ3_BASE (0x309F0000u)
1052/** Peripheral AIPSTZ3 base pointer */
1053#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)
1054/** Peripheral AIPSTZ4 base address */
1055#define AIPSTZ4_BASE (0x32DF0000u)
1056/** Peripheral AIPSTZ4 base pointer */
1057#define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)
1058/** Array initializer of AIPSTZ peripheral base addresses */
1059#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }
1060/** Array initializer of AIPSTZ peripheral base pointers */
1061#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }
1062
1063/*!
1064 * @}
1065 */ /* end of group AIPSTZ_Peripheral_Access_Layer */
1066
1067
1068/* ----------------------------------------------------------------------------
1069 -- APBH Peripheral Access Layer
1070 ---------------------------------------------------------------------------- */
1071
1072/*!
1073 * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer
1074 * @{
1075 */
1076
1077/** APBH - Register Layout Typedef */
1078typedef struct {
1079 __IO uint32_t CTRL0; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */
1080 __IO uint32_t CTRL0_SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */
1081 __IO uint32_t CTRL0_CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */
1082 __IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */
1083 __IO uint32_t CTRL1; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */
1084 __IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */
1085 __IO uint32_t CTRL1_CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */
1086 __IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */
1087 __IO uint32_t CTRL2; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */
1088 __IO uint32_t CTRL2_SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */
1089 __IO uint32_t CTRL2_CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */
1090 __IO uint32_t CTRL2_TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */
1091 __IO uint32_t CHANNEL_CTRL; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */
1092 __IO uint32_t CHANNEL_CTRL_SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */
1093 __IO uint32_t CHANNEL_CTRL_CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */
1094 __IO uint32_t CHANNEL_CTRL_TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */
1095 __I uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */
1096 uint8_t RESERVED_0[12];
1097 __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */
1098 uint8_t RESERVED_1[12];
1099 __IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60 */
1100 uint8_t RESERVED_2[156];
1101 __I uint32_t CH0_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x100 */
1102 uint8_t RESERVED_3[12];
1103 __IO uint32_t CH0_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x110 */
1104 uint8_t RESERVED_4[12];
1105 __I uint32_t CH0_CMD; /**< APBH DMA Channel n Command Register, offset: 0x120 */
1106 uint8_t RESERVED_5[12];
1107 __I uint32_t CH0_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x130 */
1108 uint8_t RESERVED_6[12];
1109 __IO uint32_t CH0_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x140 */
1110 uint8_t RESERVED_7[12];
1111 __I uint32_t CH0_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x150 */
1112 uint8_t RESERVED_8[12];
1113 __I uint32_t CH0_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x160 */
1114 uint8_t RESERVED_9[12];
1115 __I uint32_t CH1_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x170 */
1116 uint8_t RESERVED_10[12];
1117 __IO uint32_t CH1_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x180 */
1118 uint8_t RESERVED_11[12];
1119 __I uint32_t CH1_CMD; /**< APBH DMA Channel n Command Register, offset: 0x190 */
1120 uint8_t RESERVED_12[12];
1121 __I uint32_t CH1_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x1A0 */
1122 uint8_t RESERVED_13[12];
1123 __IO uint32_t CH1_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x1B0 */
1124 uint8_t RESERVED_14[12];
1125 __I uint32_t CH1_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x1C0 */
1126 uint8_t RESERVED_15[12];
1127 __I uint32_t CH1_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x1D0 */
1128 uint8_t RESERVED_16[12];
1129 __I uint32_t CH2_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x1E0 */
1130 uint8_t RESERVED_17[12];
1131 __IO uint32_t CH2_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x1F0 */
1132 uint8_t RESERVED_18[12];
1133 __I uint32_t CH2_CMD; /**< APBH DMA Channel n Command Register, offset: 0x200 */
1134 uint8_t RESERVED_19[12];
1135 __I uint32_t CH2_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x210 */
1136 uint8_t RESERVED_20[12];
1137 __IO uint32_t CH2_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x220 */
1138 uint8_t RESERVED_21[12];
1139 __I uint32_t CH2_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x230 */
1140 uint8_t RESERVED_22[12];
1141 __I uint32_t CH2_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x240 */
1142 uint8_t RESERVED_23[12];
1143 __I uint32_t CH3_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x250 */
1144 uint8_t RESERVED_24[12];
1145 __IO uint32_t CH3_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x260 */
1146 uint8_t RESERVED_25[12];
1147 __I uint32_t CH3_CMD; /**< APBH DMA Channel n Command Register, offset: 0x270 */
1148 uint8_t RESERVED_26[12];
1149 __I uint32_t CH3_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x280 */
1150 uint8_t RESERVED_27[12];
1151 __IO uint32_t CH3_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x290 */
1152 uint8_t RESERVED_28[12];
1153 __I uint32_t CH3_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x2A0 */
1154 uint8_t RESERVED_29[12];
1155 __I uint32_t CH3_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x2B0 */
1156 uint8_t RESERVED_30[12];
1157 __I uint32_t CH4_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x2C0 */
1158 uint8_t RESERVED_31[12];
1159 __IO uint32_t CH4_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x2D0 */
1160 uint8_t RESERVED_32[12];
1161 __I uint32_t CH4_CMD; /**< APBH DMA Channel n Command Register, offset: 0x2E0 */
1162 uint8_t RESERVED_33[12];
1163 __I uint32_t CH4_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x2F0 */
1164 uint8_t RESERVED_34[12];
1165 __IO uint32_t CH4_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x300 */
1166 uint8_t RESERVED_35[12];
1167 __I uint32_t CH4_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x310 */
1168 uint8_t RESERVED_36[12];
1169 __I uint32_t CH4_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x320 */
1170 uint8_t RESERVED_37[12];
1171 __I uint32_t CH5_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x330 */
1172 uint8_t RESERVED_38[12];
1173 __IO uint32_t CH5_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x340 */
1174 uint8_t RESERVED_39[12];
1175 __I uint32_t CH5_CMD; /**< APBH DMA Channel n Command Register, offset: 0x350 */
1176 uint8_t RESERVED_40[12];
1177 __I uint32_t CH5_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x360 */
1178 uint8_t RESERVED_41[12];
1179 __IO uint32_t CH5_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x370 */
1180 uint8_t RESERVED_42[12];
1181 __I uint32_t CH5_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x380 */
1182 uint8_t RESERVED_43[12];
1183 __I uint32_t CH5_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x390 */
1184 uint8_t RESERVED_44[12];
1185 __I uint32_t CH6_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x3A0 */
1186 uint8_t RESERVED_45[12];
1187 __IO uint32_t CH6_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x3B0 */
1188 uint8_t RESERVED_46[12];
1189 __I uint32_t CH6_CMD; /**< APBH DMA Channel n Command Register, offset: 0x3C0 */
1190 uint8_t RESERVED_47[12];
1191 __I uint32_t CH6_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x3D0 */
1192 uint8_t RESERVED_48[12];
1193 __IO uint32_t CH6_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x3E0 */
1194 uint8_t RESERVED_49[12];
1195 __I uint32_t CH6_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x3F0 */
1196 uint8_t RESERVED_50[12];
1197 __I uint32_t CH6_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x400 */
1198 uint8_t RESERVED_51[12];
1199 __I uint32_t CH7_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x410 */
1200 uint8_t RESERVED_52[12];
1201 __IO uint32_t CH7_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x420 */
1202 uint8_t RESERVED_53[12];
1203 __I uint32_t CH7_CMD; /**< APBH DMA Channel n Command Register, offset: 0x430 */
1204 uint8_t RESERVED_54[12];
1205 __I uint32_t CH7_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x440 */
1206 uint8_t RESERVED_55[12];
1207 __IO uint32_t CH7_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x450 */
1208 uint8_t RESERVED_56[12];
1209 __I uint32_t CH7_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x460 */
1210 uint8_t RESERVED_57[12];
1211 __I uint32_t CH7_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x470 */
1212 uint8_t RESERVED_58[12];
1213 __I uint32_t CH8_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x480 */
1214 uint8_t RESERVED_59[12];
1215 __IO uint32_t CH8_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x490 */
1216 uint8_t RESERVED_60[12];
1217 __I uint32_t CH8_CMD; /**< APBH DMA Channel n Command Register, offset: 0x4A0 */
1218 uint8_t RESERVED_61[12];
1219 __I uint32_t CH8_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x4B0 */
1220 uint8_t RESERVED_62[12];
1221 __IO uint32_t CH8_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x4C0 */
1222 uint8_t RESERVED_63[12];
1223 __I uint32_t CH8_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x4D0 */
1224 uint8_t RESERVED_64[12];
1225 __I uint32_t CH8_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x4E0 */
1226 uint8_t RESERVED_65[12];
1227 __I uint32_t CH9_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x4F0 */
1228 uint8_t RESERVED_66[12];
1229 __IO uint32_t CH9_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x500 */
1230 uint8_t RESERVED_67[12];
1231 __I uint32_t CH9_CMD; /**< APBH DMA Channel n Command Register, offset: 0x510 */
1232 uint8_t RESERVED_68[12];
1233 __I uint32_t CH9_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x520 */
1234 uint8_t RESERVED_69[12];
1235 __IO uint32_t CH9_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x530 */
1236 uint8_t RESERVED_70[12];
1237 __I uint32_t CH9_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x540 */
1238 uint8_t RESERVED_71[12];
1239 __I uint32_t CH9_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x550 */
1240 uint8_t RESERVED_72[12];
1241 __I uint32_t CH10_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x560 */
1242 uint8_t RESERVED_73[12];
1243 __IO uint32_t CH10_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x570 */
1244 uint8_t RESERVED_74[12];
1245 __I uint32_t CH10_CMD; /**< APBH DMA Channel n Command Register, offset: 0x580 */
1246 uint8_t RESERVED_75[12];
1247 __I uint32_t CH10_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x590 */
1248 uint8_t RESERVED_76[12];
1249 __IO uint32_t CH10_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x5A0 */
1250 uint8_t RESERVED_77[12];
1251 __I uint32_t CH10_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x5B0 */
1252 uint8_t RESERVED_78[12];
1253 __I uint32_t CH10_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x5C0 */
1254 uint8_t RESERVED_79[12];
1255 __I uint32_t CH11_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x5D0 */
1256 uint8_t RESERVED_80[12];
1257 __IO uint32_t CH11_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x5E0 */
1258 uint8_t RESERVED_81[12];
1259 __I uint32_t CH11_CMD; /**< APBH DMA Channel n Command Register, offset: 0x5F0 */
1260 uint8_t RESERVED_82[12];
1261 __I uint32_t CH11_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x600 */
1262 uint8_t RESERVED_83[12];
1263 __IO uint32_t CH11_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x610 */
1264 uint8_t RESERVED_84[12];
1265 __I uint32_t CH11_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x620 */
1266 uint8_t RESERVED_85[12];
1267 __I uint32_t CH11_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x630 */
1268 uint8_t RESERVED_86[12];
1269 __I uint32_t CH12_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x640 */
1270 uint8_t RESERVED_87[12];
1271 __IO uint32_t CH12_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x650 */
1272 uint8_t RESERVED_88[12];
1273 __I uint32_t CH12_CMD; /**< APBH DMA Channel n Command Register, offset: 0x660 */
1274 uint8_t RESERVED_89[12];
1275 __I uint32_t CH12_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x670 */
1276 uint8_t RESERVED_90[12];
1277 __IO uint32_t CH12_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x680 */
1278 uint8_t RESERVED_91[12];
1279 __I uint32_t CH12_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x690 */
1280 uint8_t RESERVED_92[12];
1281 __I uint32_t CH12_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x6A0 */
1282 uint8_t RESERVED_93[12];
1283 __I uint32_t CH13_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x6B0 */
1284 uint8_t RESERVED_94[12];
1285 __IO uint32_t CH13_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x6C0 */
1286 uint8_t RESERVED_95[12];
1287 __I uint32_t CH13_CMD; /**< APBH DMA Channel n Command Register, offset: 0x6D0 */
1288 uint8_t RESERVED_96[12];
1289 __I uint32_t CH13_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x6E0 */
1290 uint8_t RESERVED_97[12];
1291 __IO uint32_t CH13_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x6F0 */
1292 uint8_t RESERVED_98[12];
1293 __I uint32_t CH13_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x700 */
1294 uint8_t RESERVED_99[12];
1295 __I uint32_t CH13_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x710 */
1296 uint8_t RESERVED_100[12];
1297 __I uint32_t CH14_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x720 */
1298 uint8_t RESERVED_101[12];
1299 __IO uint32_t CH14_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x730 */
1300 uint8_t RESERVED_102[12];
1301 __I uint32_t CH14_CMD; /**< APBH DMA Channel n Command Register, offset: 0x740 */
1302 uint8_t RESERVED_103[12];
1303 __I uint32_t CH14_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x750 */
1304 uint8_t RESERVED_104[12];
1305 __IO uint32_t CH14_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x760 */
1306 uint8_t RESERVED_105[12];
1307 __I uint32_t CH14_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x770 */
1308 uint8_t RESERVED_106[12];
1309 __I uint32_t CH14_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x780 */
1310 uint8_t RESERVED_107[12];
1311 __I uint32_t CH15_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, offset: 0x790 */
1312 uint8_t RESERVED_108[12];
1313 __IO uint32_t CH15_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, offset: 0x7A0 */
1314 uint8_t RESERVED_109[12];
1315 __I uint32_t CH15_CMD; /**< APBH DMA Channel n Command Register, offset: 0x7B0 */
1316 uint8_t RESERVED_110[12];
1317 __I uint32_t CH15_BAR; /**< APBH DMA Channel n Buffer Address Register, offset: 0x7C0 */
1318 uint8_t RESERVED_111[12];
1319 __IO uint32_t CH15_SEMA; /**< APBH DMA Channel n Semaphore Register, offset: 0x7D0 */
1320 uint8_t RESERVED_112[12];
1321 __I uint32_t CH15_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x7E0 */
1322 uint8_t RESERVED_113[12];
1323 __I uint32_t CH15_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, offset: 0x7F0 */
1324 uint8_t RESERVED_114[12];
1325 __I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */
1326} APBH_Type;
1327
1328/* ----------------------------------------------------------------------------
1329 -- APBH Register Masks
1330 ---------------------------------------------------------------------------- */
1331
1332/*!
1333 * @addtogroup APBH_Register_Masks APBH Register Masks
1334 * @{
1335 */
1336
1337/*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */
1338/*! @{ */
1339#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU)
1340#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U)
1341/*! CLKGATE_CHANNEL
1342 * 0b0000000000000001..NAND0
1343 * 0b0000000000000010..NAND1
1344 * 0b0000000000000100..NAND2
1345 * 0b0000000000001000..NAND3
1346 * 0b0000000000010000..NAND4
1347 * 0b0000000000100000..NAND5
1348 * 0b0000000001000000..NAND6
1349 * 0b0000000010000000..NAND7
1350 * 0b0000000100000000..SSP
1351 */
1352#define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK)
1353#define APBH_CTRL0_RSVD0_MASK (0xFFF0000U)
1354#define APBH_CTRL0_RSVD0_SHIFT (16U)
1355#define APBH_CTRL0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_RSVD0_SHIFT)) & APBH_CTRL0_RSVD0_MASK)
1356#define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U)
1357#define APBH_CTRL0_APB_BURST_EN_SHIFT (28U)
1358#define APBH_CTRL0_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK)
1359#define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U)
1360#define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U)
1361#define APBH_CTRL0_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK)
1362#define APBH_CTRL0_CLKGATE_MASK (0x40000000U)
1363#define APBH_CTRL0_CLKGATE_SHIFT (30U)
1364#define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK)
1365#define APBH_CTRL0_SFTRST_MASK (0x80000000U)
1366#define APBH_CTRL0_SFTRST_SHIFT (31U)
1367#define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK)
1368/*! @} */
1369
1370/*! @name CTRL0_SET - AHB to APBH Bridge Control and Status Register 0 */
1371/*! @{ */
1372#define APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK (0xFFFFU)
1373#define APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT (0U)
1374/*! CLKGATE_CHANNEL
1375 * 0b0000000000000001..NAND0
1376 * 0b0000000000000010..NAND1
1377 * 0b0000000000000100..NAND2
1378 * 0b0000000000001000..NAND3
1379 * 0b0000000000010000..NAND4
1380 * 0b0000000000100000..NAND5
1381 * 0b0000000001000000..NAND6
1382 * 0b0000000010000000..NAND7
1383 * 0b0000000100000000..SSP
1384 */
1385#define APBH_CTRL0_SET_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_SET_CLKGATE_CHANNEL_MASK)
1386#define APBH_CTRL0_SET_RSVD0_MASK (0xFFF0000U)
1387#define APBH_CTRL0_SET_RSVD0_SHIFT (16U)
1388#define APBH_CTRL0_SET_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_RSVD0_SHIFT)) & APBH_CTRL0_SET_RSVD0_MASK)
1389#define APBH_CTRL0_SET_APB_BURST_EN_MASK (0x10000000U)
1390#define APBH_CTRL0_SET_APB_BURST_EN_SHIFT (28U)
1391#define APBH_CTRL0_SET_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_APB_BURST_EN_SHIFT)) & APBH_CTRL0_SET_APB_BURST_EN_MASK)
1392#define APBH_CTRL0_SET_AHB_BURST8_EN_MASK (0x20000000U)
1393#define APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT (29U)
1394#define APBH_CTRL0_SET_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_SET_AHB_BURST8_EN_MASK)
1395#define APBH_CTRL0_SET_CLKGATE_MASK (0x40000000U)
1396#define APBH_CTRL0_SET_CLKGATE_SHIFT (30U)
1397#define APBH_CTRL0_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_CLKGATE_SHIFT)) & APBH_CTRL0_SET_CLKGATE_MASK)
1398#define APBH_CTRL0_SET_SFTRST_MASK (0x80000000U)
1399#define APBH_CTRL0_SET_SFTRST_SHIFT (31U)
1400#define APBH_CTRL0_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SET_SFTRST_SHIFT)) & APBH_CTRL0_SET_SFTRST_MASK)
1401/*! @} */
1402
1403/*! @name CTRL0_CLR - AHB to APBH Bridge Control and Status Register 0 */
1404/*! @{ */
1405#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK (0xFFFFU)
1406#define APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT (0U)
1407/*! CLKGATE_CHANNEL
1408 * 0b0000000000000001..NAND0
1409 * 0b0000000000000010..NAND1
1410 * 0b0000000000000100..NAND2
1411 * 0b0000000000001000..NAND3
1412 * 0b0000000000010000..NAND4
1413 * 0b0000000000100000..NAND5
1414 * 0b0000000001000000..NAND6
1415 * 0b0000000010000000..NAND7
1416 * 0b0000000100000000..SSP
1417 */
1418#define APBH_CTRL0_CLR_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_CHANNEL_MASK)
1419#define APBH_CTRL0_CLR_RSVD0_MASK (0xFFF0000U)
1420#define APBH_CTRL0_CLR_RSVD0_SHIFT (16U)
1421#define APBH_CTRL0_CLR_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_RSVD0_SHIFT)) & APBH_CTRL0_CLR_RSVD0_MASK)
1422#define APBH_CTRL0_CLR_APB_BURST_EN_MASK (0x10000000U)
1423#define APBH_CTRL0_CLR_APB_BURST_EN_SHIFT (28U)
1424#define APBH_CTRL0_CLR_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_APB_BURST_EN_SHIFT)) & APBH_CTRL0_CLR_APB_BURST_EN_MASK)
1425#define APBH_CTRL0_CLR_AHB_BURST8_EN_MASK (0x20000000U)
1426#define APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT (29U)
1427#define APBH_CTRL0_CLR_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_CLR_AHB_BURST8_EN_MASK)
1428#define APBH_CTRL0_CLR_CLKGATE_MASK (0x40000000U)
1429#define APBH_CTRL0_CLR_CLKGATE_SHIFT (30U)
1430#define APBH_CTRL0_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_CLKGATE_SHIFT)) & APBH_CTRL0_CLR_CLKGATE_MASK)
1431#define APBH_CTRL0_CLR_SFTRST_MASK (0x80000000U)
1432#define APBH_CTRL0_CLR_SFTRST_SHIFT (31U)
1433#define APBH_CTRL0_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLR_SFTRST_SHIFT)) & APBH_CTRL0_CLR_SFTRST_MASK)
1434/*! @} */
1435
1436/*! @name CTRL0_TOG - AHB to APBH Bridge Control and Status Register 0 */
1437/*! @{ */
1438#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK (0xFFFFU)
1439#define APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT (0U)
1440/*! CLKGATE_CHANNEL
1441 * 0b0000000000000001..NAND0
1442 * 0b0000000000000010..NAND1
1443 * 0b0000000000000100..NAND2
1444 * 0b0000000000001000..NAND3
1445 * 0b0000000000010000..NAND4
1446 * 0b0000000000100000..NAND5
1447 * 0b0000000001000000..NAND6
1448 * 0b0000000010000000..NAND7
1449 * 0b0000000100000000..SSP
1450 */
1451#define APBH_CTRL0_TOG_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_CHANNEL_MASK)
1452#define APBH_CTRL0_TOG_RSVD0_MASK (0xFFF0000U)
1453#define APBH_CTRL0_TOG_RSVD0_SHIFT (16U)
1454#define APBH_CTRL0_TOG_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_RSVD0_SHIFT)) & APBH_CTRL0_TOG_RSVD0_MASK)
1455#define APBH_CTRL0_TOG_APB_BURST_EN_MASK (0x10000000U)
1456#define APBH_CTRL0_TOG_APB_BURST_EN_SHIFT (28U)
1457#define APBH_CTRL0_TOG_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_APB_BURST_EN_SHIFT)) & APBH_CTRL0_TOG_APB_BURST_EN_MASK)
1458#define APBH_CTRL0_TOG_AHB_BURST8_EN_MASK (0x20000000U)
1459#define APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT (29U)
1460#define APBH_CTRL0_TOG_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_TOG_AHB_BURST8_EN_MASK)
1461#define APBH_CTRL0_TOG_CLKGATE_MASK (0x40000000U)
1462#define APBH_CTRL0_TOG_CLKGATE_SHIFT (30U)
1463#define APBH_CTRL0_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_CLKGATE_SHIFT)) & APBH_CTRL0_TOG_CLKGATE_MASK)
1464#define APBH_CTRL0_TOG_SFTRST_MASK (0x80000000U)
1465#define APBH_CTRL0_TOG_SFTRST_SHIFT (31U)
1466#define APBH_CTRL0_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_TOG_SFTRST_SHIFT)) & APBH_CTRL0_TOG_SFTRST_MASK)
1467/*! @} */
1468
1469/*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */
1470/*! @{ */
1471#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U)
1472#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U)
1473#define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK)
1474#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U)
1475#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U)
1476#define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK)
1477#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U)
1478#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U)
1479#define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK)
1480#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U)
1481#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U)
1482#define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK)
1483#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U)
1484#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U)
1485#define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK)
1486#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U)
1487#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U)
1488#define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK)
1489#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U)
1490#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U)
1491#define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK)
1492#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U)
1493#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U)
1494#define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK)
1495#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U)
1496#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U)
1497#define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK)
1498#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U)
1499#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U)
1500#define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK)
1501#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U)
1502#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U)
1503#define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK)
1504#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U)
1505#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U)
1506#define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK)
1507#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
1508#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U)
1509#define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK)
1510#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
1511#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U)
1512#define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK)
1513#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
1514#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U)
1515#define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK)
1516#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
1517#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U)
1518#define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK)
1519#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
1520#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
1521#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK)
1522#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
1523#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
1524#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK)
1525#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
1526#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
1527#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK)
1528#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
1529#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
1530#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK)
1531#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
1532#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
1533#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK)
1534#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
1535#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
1536#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK)
1537#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
1538#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
1539#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK)
1540#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
1541#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
1542#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK)
1543#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
1544#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
1545#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK)
1546#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
1547#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
1548#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK)
1549#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
1550#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
1551#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
1552#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
1553#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
1554#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK)
1555#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
1556#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
1557#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK)
1558#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
1559#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
1560#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK)
1561#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
1562#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
1563#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK)
1564#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
1565#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
1566#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK)
1567/*! @} */
1568
1569/*! @name CTRL1_SET - AHB to APBH Bridge Control and Status Register 1 */
1570/*! @{ */
1571#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK (0x1U)
1572#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT (0U)
1573#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_MASK)
1574#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK (0x2U)
1575#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT (1U)
1576#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_MASK)
1577#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK (0x4U)
1578#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT (2U)
1579#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_MASK)
1580#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK (0x8U)
1581#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT (3U)
1582#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_MASK)
1583#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK (0x10U)
1584#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT (4U)
1585#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_MASK)
1586#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK (0x20U)
1587#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT (5U)
1588#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_MASK)
1589#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK (0x40U)
1590#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT (6U)
1591#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_MASK)
1592#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK (0x80U)
1593#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT (7U)
1594#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_MASK)
1595#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK (0x100U)
1596#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT (8U)
1597#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_MASK)
1598#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK (0x200U)
1599#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT (9U)
1600#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_MASK)
1601#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK (0x400U)
1602#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT (10U)
1603#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_MASK)
1604#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK (0x800U)
1605#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT (11U)
1606#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_MASK)
1607#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
1608#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT (12U)
1609#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_MASK)
1610#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
1611#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT (13U)
1612#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_MASK)
1613#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
1614#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT (14U)
1615#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_MASK)
1616#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
1617#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT (15U)
1618#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_MASK)
1619#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
1620#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
1621#define APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH0_CMDCMPLT_IRQ_EN_MASK)
1622#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
1623#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
1624#define APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH1_CMDCMPLT_IRQ_EN_MASK)
1625#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
1626#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
1627#define APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH2_CMDCMPLT_IRQ_EN_MASK)
1628#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
1629#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
1630#define APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH3_CMDCMPLT_IRQ_EN_MASK)
1631#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
1632#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
1633#define APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH4_CMDCMPLT_IRQ_EN_MASK)
1634#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
1635#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
1636#define APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH5_CMDCMPLT_IRQ_EN_MASK)
1637#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
1638#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
1639#define APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH6_CMDCMPLT_IRQ_EN_MASK)
1640#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
1641#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
1642#define APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH7_CMDCMPLT_IRQ_EN_MASK)
1643#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
1644#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
1645#define APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH8_CMDCMPLT_IRQ_EN_MASK)
1646#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
1647#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
1648#define APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH9_CMDCMPLT_IRQ_EN_MASK)
1649#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
1650#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
1651#define APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH10_CMDCMPLT_IRQ_EN_MASK)
1652#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
1653#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
1654#define APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH11_CMDCMPLT_IRQ_EN_MASK)
1655#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
1656#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
1657#define APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH12_CMDCMPLT_IRQ_EN_MASK)
1658#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
1659#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
1660#define APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH13_CMDCMPLT_IRQ_EN_MASK)
1661#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
1662#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
1663#define APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH14_CMDCMPLT_IRQ_EN_MASK)
1664#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
1665#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
1666#define APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_SET_CH15_CMDCMPLT_IRQ_EN_MASK)
1667/*! @} */
1668
1669/*! @name CTRL1_CLR - AHB to APBH Bridge Control and Status Register 1 */
1670/*! @{ */
1671#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK (0x1U)
1672#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT (0U)
1673#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_MASK)
1674#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK (0x2U)
1675#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT (1U)
1676#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_MASK)
1677#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK (0x4U)
1678#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT (2U)
1679#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_MASK)
1680#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK (0x8U)
1681#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT (3U)
1682#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_MASK)
1683#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK (0x10U)
1684#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT (4U)
1685#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_MASK)
1686#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK (0x20U)
1687#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT (5U)
1688#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_MASK)
1689#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK (0x40U)
1690#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT (6U)
1691#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_MASK)
1692#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK (0x80U)
1693#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT (7U)
1694#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_MASK)
1695#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK (0x100U)
1696#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT (8U)
1697#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_MASK)
1698#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK (0x200U)
1699#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT (9U)
1700#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_MASK)
1701#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK (0x400U)
1702#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT (10U)
1703#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_MASK)
1704#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK (0x800U)
1705#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT (11U)
1706#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_MASK)
1707#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
1708#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT (12U)
1709#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_MASK)
1710#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
1711#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT (13U)
1712#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_MASK)
1713#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
1714#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT (14U)
1715#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_MASK)
1716#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
1717#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT (15U)
1718#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_MASK)
1719#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
1720#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
1721#define APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH0_CMDCMPLT_IRQ_EN_MASK)
1722#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
1723#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
1724#define APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH1_CMDCMPLT_IRQ_EN_MASK)
1725#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
1726#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
1727#define APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH2_CMDCMPLT_IRQ_EN_MASK)
1728#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
1729#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
1730#define APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH3_CMDCMPLT_IRQ_EN_MASK)
1731#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
1732#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
1733#define APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH4_CMDCMPLT_IRQ_EN_MASK)
1734#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
1735#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
1736#define APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH5_CMDCMPLT_IRQ_EN_MASK)
1737#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
1738#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
1739#define APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH6_CMDCMPLT_IRQ_EN_MASK)
1740#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
1741#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
1742#define APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH7_CMDCMPLT_IRQ_EN_MASK)
1743#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
1744#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
1745#define APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH8_CMDCMPLT_IRQ_EN_MASK)
1746#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
1747#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
1748#define APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH9_CMDCMPLT_IRQ_EN_MASK)
1749#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
1750#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
1751#define APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH10_CMDCMPLT_IRQ_EN_MASK)
1752#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
1753#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
1754#define APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH11_CMDCMPLT_IRQ_EN_MASK)
1755#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
1756#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
1757#define APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH12_CMDCMPLT_IRQ_EN_MASK)
1758#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
1759#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
1760#define APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH13_CMDCMPLT_IRQ_EN_MASK)
1761#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
1762#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
1763#define APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH14_CMDCMPLT_IRQ_EN_MASK)
1764#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
1765#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
1766#define APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CLR_CH15_CMDCMPLT_IRQ_EN_MASK)
1767/*! @} */
1768
1769/*! @name CTRL1_TOG - AHB to APBH Bridge Control and Status Register 1 */
1770/*! @{ */
1771#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK (0x1U)
1772#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT (0U)
1773#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_MASK)
1774#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK (0x2U)
1775#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT (1U)
1776#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_MASK)
1777#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK (0x4U)
1778#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT (2U)
1779#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_MASK)
1780#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK (0x8U)
1781#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT (3U)
1782#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_MASK)
1783#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK (0x10U)
1784#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT (4U)
1785#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_MASK)
1786#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK (0x20U)
1787#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT (5U)
1788#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_MASK)
1789#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK (0x40U)
1790#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT (6U)
1791#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_MASK)
1792#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK (0x80U)
1793#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT (7U)
1794#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_MASK)
1795#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK (0x100U)
1796#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT (8U)
1797#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_MASK)
1798#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK (0x200U)
1799#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT (9U)
1800#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_MASK)
1801#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK (0x400U)
1802#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT (10U)
1803#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_MASK)
1804#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK (0x800U)
1805#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT (11U)
1806#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_MASK)
1807#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
1808#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT (12U)
1809#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_MASK)
1810#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
1811#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT (13U)
1812#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_MASK)
1813#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
1814#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT (14U)
1815#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_MASK)
1816#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
1817#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT (15U)
1818#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_MASK)
1819#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
1820#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
1821#define APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH0_CMDCMPLT_IRQ_EN_MASK)
1822#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
1823#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
1824#define APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH1_CMDCMPLT_IRQ_EN_MASK)
1825#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
1826#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
1827#define APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH2_CMDCMPLT_IRQ_EN_MASK)
1828#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
1829#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
1830#define APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH3_CMDCMPLT_IRQ_EN_MASK)
1831#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
1832#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
1833#define APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH4_CMDCMPLT_IRQ_EN_MASK)
1834#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
1835#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
1836#define APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH5_CMDCMPLT_IRQ_EN_MASK)
1837#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
1838#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
1839#define APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH6_CMDCMPLT_IRQ_EN_MASK)
1840#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
1841#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
1842#define APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH7_CMDCMPLT_IRQ_EN_MASK)
1843#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
1844#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
1845#define APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH8_CMDCMPLT_IRQ_EN_MASK)
1846#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
1847#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
1848#define APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH9_CMDCMPLT_IRQ_EN_MASK)
1849#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
1850#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
1851#define APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH10_CMDCMPLT_IRQ_EN_MASK)
1852#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
1853#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
1854#define APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH11_CMDCMPLT_IRQ_EN_MASK)
1855#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
1856#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
1857#define APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH12_CMDCMPLT_IRQ_EN_MASK)
1858#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
1859#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
1860#define APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH13_CMDCMPLT_IRQ_EN_MASK)
1861#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
1862#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
1863#define APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH14_CMDCMPLT_IRQ_EN_MASK)
1864#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
1865#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
1866#define APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_TOG_CH15_CMDCMPLT_IRQ_EN_MASK)
1867/*! @} */
1868
1869/*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */
1870/*! @{ */
1871#define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U)
1872#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U)
1873#define APBH_CTRL2_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK)
1874#define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U)
1875#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U)
1876#define APBH_CTRL2_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK)
1877#define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U)
1878#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U)
1879#define APBH_CTRL2_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK)
1880#define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U)
1881#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U)
1882#define APBH_CTRL2_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK)
1883#define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U)
1884#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U)
1885#define APBH_CTRL2_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK)
1886#define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U)
1887#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U)
1888#define APBH_CTRL2_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK)
1889#define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U)
1890#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U)
1891#define APBH_CTRL2_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK)
1892#define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U)
1893#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U)
1894#define APBH_CTRL2_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK)
1895#define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U)
1896#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U)
1897#define APBH_CTRL2_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK)
1898#define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U)
1899#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U)
1900#define APBH_CTRL2_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK)
1901#define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U)
1902#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U)
1903#define APBH_CTRL2_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK)
1904#define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U)
1905#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U)
1906#define APBH_CTRL2_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK)
1907#define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U)
1908#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U)
1909#define APBH_CTRL2_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK)
1910#define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U)
1911#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U)
1912#define APBH_CTRL2_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK)
1913#define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U)
1914#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U)
1915#define APBH_CTRL2_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK)
1916#define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U)
1917#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U)
1918#define APBH_CTRL2_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK)
1919#define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U)
1920#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U)
1921/*! CH0_ERROR_STATUS
1922 * 0b0..An early termination from the device causes error IRQ.
1923 * 0b1..An AHB bus error causes error IRQ.
1924 */
1925#define APBH_CTRL2_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK)
1926#define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U)
1927#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U)
1928/*! CH1_ERROR_STATUS
1929 * 0b0..An early termination from the device causes error IRQ.
1930 * 0b1..An AHB bus error causes error IRQ.
1931 */
1932#define APBH_CTRL2_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK)
1933#define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U)
1934#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U)
1935/*! CH2_ERROR_STATUS
1936 * 0b0..An early termination from the device causes error IRQ.
1937 * 0b1..An AHB bus error causes error IRQ.
1938 */
1939#define APBH_CTRL2_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK)
1940#define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U)
1941#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U)
1942/*! CH3_ERROR_STATUS
1943 * 0b0..An early termination from the device causes error IRQ.
1944 * 0b1..An AHB bus error causes error IRQ.
1945 */
1946#define APBH_CTRL2_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK)
1947#define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U)
1948#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U)
1949/*! CH4_ERROR_STATUS
1950 * 0b0..An early termination from the device causes error IRQ.
1951 * 0b1..An AHB bus error causes error IRQ.
1952 */
1953#define APBH_CTRL2_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK)
1954#define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U)
1955#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U)
1956/*! CH5_ERROR_STATUS
1957 * 0b0..An early termination from the device causes error IRQ.
1958 * 0b1..An AHB bus error causes error IRQ.
1959 */
1960#define APBH_CTRL2_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK)
1961#define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U)
1962#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U)
1963/*! CH6_ERROR_STATUS
1964 * 0b0..An early termination from the device causes error IRQ.
1965 * 0b1..An AHB bus error causes error IRQ.
1966 */
1967#define APBH_CTRL2_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK)
1968#define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U)
1969#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U)
1970/*! CH7_ERROR_STATUS
1971 * 0b0..An early termination from the device causes error IRQ.
1972 * 0b1..An AHB bus error causes error IRQ.
1973 */
1974#define APBH_CTRL2_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK)
1975#define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U)
1976#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U)
1977/*! CH8_ERROR_STATUS
1978 * 0b0..An early termination from the device causes error IRQ.
1979 * 0b1..An AHB bus error causes error IRQ.
1980 */
1981#define APBH_CTRL2_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK)
1982#define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U)
1983#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U)
1984/*! CH9_ERROR_STATUS
1985 * 0b0..An early termination from the device causes error IRQ.
1986 * 0b1..An AHB bus error causes error IRQ.
1987 */
1988#define APBH_CTRL2_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK)
1989#define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U)
1990#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U)
1991/*! CH10_ERROR_STATUS
1992 * 0b0..An early termination from the device causes error IRQ.
1993 * 0b1..An AHB bus error causes error IRQ.
1994 */
1995#define APBH_CTRL2_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK)
1996#define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U)
1997#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U)
1998/*! CH11_ERROR_STATUS
1999 * 0b0..An early termination from the device causes error IRQ.
2000 * 0b1..An AHB bus error causes error IRQ.
2001 */
2002#define APBH_CTRL2_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK)
2003#define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U)
2004#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U)
2005/*! CH12_ERROR_STATUS
2006 * 0b0..An early termination from the device causes error IRQ.
2007 * 0b1..An AHB bus error causes error IRQ.
2008 */
2009#define APBH_CTRL2_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK)
2010#define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U)
2011#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U)
2012/*! CH13_ERROR_STATUS
2013 * 0b0..An early termination from the device causes error IRQ.
2014 * 0b1..An AHB bus error causes error IRQ.
2015 */
2016#define APBH_CTRL2_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK)
2017#define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U)
2018#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U)
2019/*! CH14_ERROR_STATUS
2020 * 0b0..An early termination from the device causes error IRQ.
2021 * 0b1..An AHB bus error causes error IRQ.
2022 */
2023#define APBH_CTRL2_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK)
2024#define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U)
2025#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U)
2026/*! CH15_ERROR_STATUS
2027 * 0b0..An early termination from the device causes error IRQ.
2028 * 0b1..An AHB bus error causes error IRQ.
2029 */
2030#define APBH_CTRL2_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK)
2031/*! @} */
2032
2033/*! @name CTRL2_SET - AHB to APBH Bridge Control and Status Register 2 */
2034/*! @{ */
2035#define APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK (0x1U)
2036#define APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT (0U)
2037#define APBH_CTRL2_SET_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_IRQ_MASK)
2038#define APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK (0x2U)
2039#define APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT (1U)
2040#define APBH_CTRL2_SET_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_IRQ_MASK)
2041#define APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK (0x4U)
2042#define APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT (2U)
2043#define APBH_CTRL2_SET_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_IRQ_MASK)
2044#define APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK (0x8U)
2045#define APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT (3U)
2046#define APBH_CTRL2_SET_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_IRQ_MASK)
2047#define APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK (0x10U)
2048#define APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT (4U)
2049#define APBH_CTRL2_SET_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_IRQ_MASK)
2050#define APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK (0x20U)
2051#define APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT (5U)
2052#define APBH_CTRL2_SET_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_IRQ_MASK)
2053#define APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK (0x40U)
2054#define APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT (6U)
2055#define APBH_CTRL2_SET_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_IRQ_MASK)
2056#define APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK (0x80U)
2057#define APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT (7U)
2058#define APBH_CTRL2_SET_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_IRQ_MASK)
2059#define APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK (0x100U)
2060#define APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT (8U)
2061#define APBH_CTRL2_SET_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_IRQ_MASK)
2062#define APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK (0x200U)
2063#define APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT (9U)
2064#define APBH_CTRL2_SET_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_IRQ_MASK)
2065#define APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK (0x400U)
2066#define APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT (10U)
2067#define APBH_CTRL2_SET_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_IRQ_MASK)
2068#define APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK (0x800U)
2069#define APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT (11U)
2070#define APBH_CTRL2_SET_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_IRQ_MASK)
2071#define APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK (0x1000U)
2072#define APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT (12U)
2073#define APBH_CTRL2_SET_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_IRQ_MASK)
2074#define APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK (0x2000U)
2075#define APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT (13U)
2076#define APBH_CTRL2_SET_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_IRQ_MASK)
2077#define APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK (0x4000U)
2078#define APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT (14U)
2079#define APBH_CTRL2_SET_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_IRQ_MASK)
2080#define APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK (0x8000U)
2081#define APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT (15U)
2082#define APBH_CTRL2_SET_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_IRQ_MASK)
2083#define APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK (0x10000U)
2084#define APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT (16U)
2085/*! CH0_ERROR_STATUS
2086 * 0b0..An early termination from the device causes error IRQ.
2087 * 0b1..An AHB bus error causes error IRQ.
2088 */
2089#define APBH_CTRL2_SET_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH0_ERROR_STATUS_MASK)
2090#define APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK (0x20000U)
2091#define APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT (17U)
2092/*! CH1_ERROR_STATUS
2093 * 0b0..An early termination from the device causes error IRQ.
2094 * 0b1..An AHB bus error causes error IRQ.
2095 */
2096#define APBH_CTRL2_SET_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH1_ERROR_STATUS_MASK)
2097#define APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK (0x40000U)
2098#define APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT (18U)
2099/*! CH2_ERROR_STATUS
2100 * 0b0..An early termination from the device causes error IRQ.
2101 * 0b1..An AHB bus error causes error IRQ.
2102 */
2103#define APBH_CTRL2_SET_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH2_ERROR_STATUS_MASK)
2104#define APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK (0x80000U)
2105#define APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT (19U)
2106/*! CH3_ERROR_STATUS
2107 * 0b0..An early termination from the device causes error IRQ.
2108 * 0b1..An AHB bus error causes error IRQ.
2109 */
2110#define APBH_CTRL2_SET_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH3_ERROR_STATUS_MASK)
2111#define APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK (0x100000U)
2112#define APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT (20U)
2113/*! CH4_ERROR_STATUS
2114 * 0b0..An early termination from the device causes error IRQ.
2115 * 0b1..An AHB bus error causes error IRQ.
2116 */
2117#define APBH_CTRL2_SET_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH4_ERROR_STATUS_MASK)
2118#define APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK (0x200000U)
2119#define APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT (21U)
2120/*! CH5_ERROR_STATUS
2121 * 0b0..An early termination from the device causes error IRQ.
2122 * 0b1..An AHB bus error causes error IRQ.
2123 */
2124#define APBH_CTRL2_SET_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH5_ERROR_STATUS_MASK)
2125#define APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK (0x400000U)
2126#define APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT (22U)
2127/*! CH6_ERROR_STATUS
2128 * 0b0..An early termination from the device causes error IRQ.
2129 * 0b1..An AHB bus error causes error IRQ.
2130 */
2131#define APBH_CTRL2_SET_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH6_ERROR_STATUS_MASK)
2132#define APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK (0x800000U)
2133#define APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT (23U)
2134/*! CH7_ERROR_STATUS
2135 * 0b0..An early termination from the device causes error IRQ.
2136 * 0b1..An AHB bus error causes error IRQ.
2137 */
2138#define APBH_CTRL2_SET_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH7_ERROR_STATUS_MASK)
2139#define APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK (0x1000000U)
2140#define APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT (24U)
2141/*! CH8_ERROR_STATUS
2142 * 0b0..An early termination from the device causes error IRQ.
2143 * 0b1..An AHB bus error causes error IRQ.
2144 */
2145#define APBH_CTRL2_SET_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH8_ERROR_STATUS_MASK)
2146#define APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK (0x2000000U)
2147#define APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT (25U)
2148/*! CH9_ERROR_STATUS
2149 * 0b0..An early termination from the device causes error IRQ.
2150 * 0b1..An AHB bus error causes error IRQ.
2151 */
2152#define APBH_CTRL2_SET_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH9_ERROR_STATUS_MASK)
2153#define APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK (0x4000000U)
2154#define APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT (26U)
2155/*! CH10_ERROR_STATUS
2156 * 0b0..An early termination from the device causes error IRQ.
2157 * 0b1..An AHB bus error causes error IRQ.
2158 */
2159#define APBH_CTRL2_SET_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH10_ERROR_STATUS_MASK)
2160#define APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK (0x8000000U)
2161#define APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT (27U)
2162/*! CH11_ERROR_STATUS
2163 * 0b0..An early termination from the device causes error IRQ.
2164 * 0b1..An AHB bus error causes error IRQ.
2165 */
2166#define APBH_CTRL2_SET_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH11_ERROR_STATUS_MASK)
2167#define APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK (0x10000000U)
2168#define APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT (28U)
2169/*! CH12_ERROR_STATUS
2170 * 0b0..An early termination from the device causes error IRQ.
2171 * 0b1..An AHB bus error causes error IRQ.
2172 */
2173#define APBH_CTRL2_SET_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH12_ERROR_STATUS_MASK)
2174#define APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK (0x20000000U)
2175#define APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT (29U)
2176/*! CH13_ERROR_STATUS
2177 * 0b0..An early termination from the device causes error IRQ.
2178 * 0b1..An AHB bus error causes error IRQ.
2179 */
2180#define APBH_CTRL2_SET_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH13_ERROR_STATUS_MASK)
2181#define APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK (0x40000000U)
2182#define APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT (30U)
2183/*! CH14_ERROR_STATUS
2184 * 0b0..An early termination from the device causes error IRQ.
2185 * 0b1..An AHB bus error causes error IRQ.
2186 */
2187#define APBH_CTRL2_SET_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH14_ERROR_STATUS_MASK)
2188#define APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK (0x80000000U)
2189#define APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT (31U)
2190/*! CH15_ERROR_STATUS
2191 * 0b0..An early termination from the device causes error IRQ.
2192 * 0b1..An AHB bus error causes error IRQ.
2193 */
2194#define APBH_CTRL2_SET_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_SET_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_SET_CH15_ERROR_STATUS_MASK)
2195/*! @} */
2196
2197/*! @name CTRL2_CLR - AHB to APBH Bridge Control and Status Register 2 */
2198/*! @{ */
2199#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK (0x1U)
2200#define APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT (0U)
2201#define APBH_CTRL2_CLR_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_IRQ_MASK)
2202#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK (0x2U)
2203#define APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT (1U)
2204#define APBH_CTRL2_CLR_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_IRQ_MASK)
2205#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK (0x4U)
2206#define APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT (2U)
2207#define APBH_CTRL2_CLR_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_IRQ_MASK)
2208#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK (0x8U)
2209#define APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT (3U)
2210#define APBH_CTRL2_CLR_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_IRQ_MASK)
2211#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK (0x10U)
2212#define APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT (4U)
2213#define APBH_CTRL2_CLR_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_IRQ_MASK)
2214#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK (0x20U)
2215#define APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT (5U)
2216#define APBH_CTRL2_CLR_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_IRQ_MASK)
2217#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK (0x40U)
2218#define APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT (6U)
2219#define APBH_CTRL2_CLR_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_IRQ_MASK)
2220#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK (0x80U)
2221#define APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT (7U)
2222#define APBH_CTRL2_CLR_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_IRQ_MASK)
2223#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK (0x100U)
2224#define APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT (8U)
2225#define APBH_CTRL2_CLR_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_IRQ_MASK)
2226#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK (0x200U)
2227#define APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT (9U)
2228#define APBH_CTRL2_CLR_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_IRQ_MASK)
2229#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK (0x400U)
2230#define APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT (10U)
2231#define APBH_CTRL2_CLR_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_IRQ_MASK)
2232#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK (0x800U)
2233#define APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT (11U)
2234#define APBH_CTRL2_CLR_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_IRQ_MASK)
2235#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK (0x1000U)
2236#define APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT (12U)
2237#define APBH_CTRL2_CLR_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_IRQ_MASK)
2238#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK (0x2000U)
2239#define APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT (13U)
2240#define APBH_CTRL2_CLR_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_IRQ_MASK)
2241#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK (0x4000U)
2242#define APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT (14U)
2243#define APBH_CTRL2_CLR_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_IRQ_MASK)
2244#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK (0x8000U)
2245#define APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT (15U)
2246#define APBH_CTRL2_CLR_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_IRQ_MASK)
2247#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK (0x10000U)
2248#define APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT (16U)
2249/*! CH0_ERROR_STATUS
2250 * 0b0..An early termination from the device causes error IRQ.
2251 * 0b1..An AHB bus error causes error IRQ.
2252 */
2253#define APBH_CTRL2_CLR_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH0_ERROR_STATUS_MASK)
2254#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK (0x20000U)
2255#define APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT (17U)
2256/*! CH1_ERROR_STATUS
2257 * 0b0..An early termination from the device causes error IRQ.
2258 * 0b1..An AHB bus error causes error IRQ.
2259 */
2260#define APBH_CTRL2_CLR_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH1_ERROR_STATUS_MASK)
2261#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK (0x40000U)
2262#define APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT (18U)
2263/*! CH2_ERROR_STATUS
2264 * 0b0..An early termination from the device causes error IRQ.
2265 * 0b1..An AHB bus error causes error IRQ.
2266 */
2267#define APBH_CTRL2_CLR_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH2_ERROR_STATUS_MASK)
2268#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK (0x80000U)
2269#define APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT (19U)
2270/*! CH3_ERROR_STATUS
2271 * 0b0..An early termination from the device causes error IRQ.
2272 * 0b1..An AHB bus error causes error IRQ.
2273 */
2274#define APBH_CTRL2_CLR_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH3_ERROR_STATUS_MASK)
2275#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK (0x100000U)
2276#define APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT (20U)
2277/*! CH4_ERROR_STATUS
2278 * 0b0..An early termination from the device causes error IRQ.
2279 * 0b1..An AHB bus error causes error IRQ.
2280 */
2281#define APBH_CTRL2_CLR_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH4_ERROR_STATUS_MASK)
2282#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK (0x200000U)
2283#define APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT (21U)
2284/*! CH5_ERROR_STATUS
2285 * 0b0..An early termination from the device causes error IRQ.
2286 * 0b1..An AHB bus error causes error IRQ.
2287 */
2288#define APBH_CTRL2_CLR_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH5_ERROR_STATUS_MASK)
2289#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK (0x400000U)
2290#define APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT (22U)
2291/*! CH6_ERROR_STATUS
2292 * 0b0..An early termination from the device causes error IRQ.
2293 * 0b1..An AHB bus error causes error IRQ.
2294 */
2295#define APBH_CTRL2_CLR_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH6_ERROR_STATUS_MASK)
2296#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK (0x800000U)
2297#define APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT (23U)
2298/*! CH7_ERROR_STATUS
2299 * 0b0..An early termination from the device causes error IRQ.
2300 * 0b1..An AHB bus error causes error IRQ.
2301 */
2302#define APBH_CTRL2_CLR_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH7_ERROR_STATUS_MASK)
2303#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK (0x1000000U)
2304#define APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT (24U)
2305/*! CH8_ERROR_STATUS
2306 * 0b0..An early termination from the device causes error IRQ.
2307 * 0b1..An AHB bus error causes error IRQ.
2308 */
2309#define APBH_CTRL2_CLR_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH8_ERROR_STATUS_MASK)
2310#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK (0x2000000U)
2311#define APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT (25U)
2312/*! CH9_ERROR_STATUS
2313 * 0b0..An early termination from the device causes error IRQ.
2314 * 0b1..An AHB bus error causes error IRQ.
2315 */
2316#define APBH_CTRL2_CLR_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH9_ERROR_STATUS_MASK)
2317#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK (0x4000000U)
2318#define APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT (26U)
2319/*! CH10_ERROR_STATUS
2320 * 0b0..An early termination from the device causes error IRQ.
2321 * 0b1..An AHB bus error causes error IRQ.
2322 */
2323#define APBH_CTRL2_CLR_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH10_ERROR_STATUS_MASK)
2324#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK (0x8000000U)
2325#define APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT (27U)
2326/*! CH11_ERROR_STATUS
2327 * 0b0..An early termination from the device causes error IRQ.
2328 * 0b1..An AHB bus error causes error IRQ.
2329 */
2330#define APBH_CTRL2_CLR_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH11_ERROR_STATUS_MASK)
2331#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK (0x10000000U)
2332#define APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT (28U)
2333/*! CH12_ERROR_STATUS
2334 * 0b0..An early termination from the device causes error IRQ.
2335 * 0b1..An AHB bus error causes error IRQ.
2336 */
2337#define APBH_CTRL2_CLR_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH12_ERROR_STATUS_MASK)
2338#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK (0x20000000U)
2339#define APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT (29U)
2340/*! CH13_ERROR_STATUS
2341 * 0b0..An early termination from the device causes error IRQ.
2342 * 0b1..An AHB bus error causes error IRQ.
2343 */
2344#define APBH_CTRL2_CLR_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH13_ERROR_STATUS_MASK)
2345#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK (0x40000000U)
2346#define APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT (30U)
2347/*! CH14_ERROR_STATUS
2348 * 0b0..An early termination from the device causes error IRQ.
2349 * 0b1..An AHB bus error causes error IRQ.
2350 */
2351#define APBH_CTRL2_CLR_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH14_ERROR_STATUS_MASK)
2352#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK (0x80000000U)
2353#define APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT (31U)
2354/*! CH15_ERROR_STATUS
2355 * 0b0..An early termination from the device causes error IRQ.
2356 * 0b1..An AHB bus error causes error IRQ.
2357 */
2358#define APBH_CTRL2_CLR_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CLR_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CLR_CH15_ERROR_STATUS_MASK)
2359/*! @} */
2360
2361/*! @name CTRL2_TOG - AHB to APBH Bridge Control and Status Register 2 */
2362/*! @{ */
2363#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK (0x1U)
2364#define APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT (0U)
2365#define APBH_CTRL2_TOG_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_IRQ_MASK)
2366#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK (0x2U)
2367#define APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT (1U)
2368#define APBH_CTRL2_TOG_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_IRQ_MASK)
2369#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK (0x4U)
2370#define APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT (2U)
2371#define APBH_CTRL2_TOG_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_IRQ_MASK)
2372#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK (0x8U)
2373#define APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT (3U)
2374#define APBH_CTRL2_TOG_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_IRQ_MASK)
2375#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK (0x10U)
2376#define APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT (4U)
2377#define APBH_CTRL2_TOG_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_IRQ_MASK)
2378#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK (0x20U)
2379#define APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT (5U)
2380#define APBH_CTRL2_TOG_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_IRQ_MASK)
2381#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK (0x40U)
2382#define APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT (6U)
2383#define APBH_CTRL2_TOG_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_IRQ_MASK)
2384#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK (0x80U)
2385#define APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT (7U)
2386#define APBH_CTRL2_TOG_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_IRQ_MASK)
2387#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK (0x100U)
2388#define APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT (8U)
2389#define APBH_CTRL2_TOG_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_IRQ_MASK)
2390#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK (0x200U)
2391#define APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT (9U)
2392#define APBH_CTRL2_TOG_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_IRQ_MASK)
2393#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK (0x400U)
2394#define APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT (10U)
2395#define APBH_CTRL2_TOG_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_IRQ_MASK)
2396#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK (0x800U)
2397#define APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT (11U)
2398#define APBH_CTRL2_TOG_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_IRQ_MASK)
2399#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK (0x1000U)
2400#define APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT (12U)
2401#define APBH_CTRL2_TOG_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_IRQ_MASK)
2402#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK (0x2000U)
2403#define APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT (13U)
2404#define APBH_CTRL2_TOG_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_IRQ_MASK)
2405#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK (0x4000U)
2406#define APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT (14U)
2407#define APBH_CTRL2_TOG_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_IRQ_MASK)
2408#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK (0x8000U)
2409#define APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT (15U)
2410#define APBH_CTRL2_TOG_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_IRQ_MASK)
2411#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK (0x10000U)
2412#define APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT (16U)
2413/*! CH0_ERROR_STATUS
2414 * 0b0..An early termination from the device causes error IRQ.
2415 * 0b1..An AHB bus error causes error IRQ.
2416 */
2417#define APBH_CTRL2_TOG_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH0_ERROR_STATUS_MASK)
2418#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK (0x20000U)
2419#define APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT (17U)
2420/*! CH1_ERROR_STATUS
2421 * 0b0..An early termination from the device causes error IRQ.
2422 * 0b1..An AHB bus error causes error IRQ.
2423 */
2424#define APBH_CTRL2_TOG_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH1_ERROR_STATUS_MASK)
2425#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK (0x40000U)
2426#define APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT (18U)
2427/*! CH2_ERROR_STATUS
2428 * 0b0..An early termination from the device causes error IRQ.
2429 * 0b1..An AHB bus error causes error IRQ.
2430 */
2431#define APBH_CTRL2_TOG_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH2_ERROR_STATUS_MASK)
2432#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK (0x80000U)
2433#define APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT (19U)
2434/*! CH3_ERROR_STATUS
2435 * 0b0..An early termination from the device causes error IRQ.
2436 * 0b1..An AHB bus error causes error IRQ.
2437 */
2438#define APBH_CTRL2_TOG_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH3_ERROR_STATUS_MASK)
2439#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK (0x100000U)
2440#define APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT (20U)
2441/*! CH4_ERROR_STATUS
2442 * 0b0..An early termination from the device causes error IRQ.
2443 * 0b1..An AHB bus error causes error IRQ.
2444 */
2445#define APBH_CTRL2_TOG_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH4_ERROR_STATUS_MASK)
2446#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK (0x200000U)
2447#define APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT (21U)
2448/*! CH5_ERROR_STATUS
2449 * 0b0..An early termination from the device causes error IRQ.
2450 * 0b1..An AHB bus error causes error IRQ.
2451 */
2452#define APBH_CTRL2_TOG_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH5_ERROR_STATUS_MASK)
2453#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK (0x400000U)
2454#define APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT (22U)
2455/*! CH6_ERROR_STATUS
2456 * 0b0..An early termination from the device causes error IRQ.
2457 * 0b1..An AHB bus error causes error IRQ.
2458 */
2459#define APBH_CTRL2_TOG_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH6_ERROR_STATUS_MASK)
2460#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK (0x800000U)
2461#define APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT (23U)
2462/*! CH7_ERROR_STATUS
2463 * 0b0..An early termination from the device causes error IRQ.
2464 * 0b1..An AHB bus error causes error IRQ.
2465 */
2466#define APBH_CTRL2_TOG_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH7_ERROR_STATUS_MASK)
2467#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK (0x1000000U)
2468#define APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT (24U)
2469/*! CH8_ERROR_STATUS
2470 * 0b0..An early termination from the device causes error IRQ.
2471 * 0b1..An AHB bus error causes error IRQ.
2472 */
2473#define APBH_CTRL2_TOG_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH8_ERROR_STATUS_MASK)
2474#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK (0x2000000U)
2475#define APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT (25U)
2476/*! CH9_ERROR_STATUS
2477 * 0b0..An early termination from the device causes error IRQ.
2478 * 0b1..An AHB bus error causes error IRQ.
2479 */
2480#define APBH_CTRL2_TOG_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH9_ERROR_STATUS_MASK)
2481#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK (0x4000000U)
2482#define APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT (26U)
2483/*! CH10_ERROR_STATUS
2484 * 0b0..An early termination from the device causes error IRQ.
2485 * 0b1..An AHB bus error causes error IRQ.
2486 */
2487#define APBH_CTRL2_TOG_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH10_ERROR_STATUS_MASK)
2488#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK (0x8000000U)
2489#define APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT (27U)
2490/*! CH11_ERROR_STATUS
2491 * 0b0..An early termination from the device causes error IRQ.
2492 * 0b1..An AHB bus error causes error IRQ.
2493 */
2494#define APBH_CTRL2_TOG_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH11_ERROR_STATUS_MASK)
2495#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK (0x10000000U)
2496#define APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT (28U)
2497/*! CH12_ERROR_STATUS
2498 * 0b0..An early termination from the device causes error IRQ.
2499 * 0b1..An AHB bus error causes error IRQ.
2500 */
2501#define APBH_CTRL2_TOG_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH12_ERROR_STATUS_MASK)
2502#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK (0x20000000U)
2503#define APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT (29U)
2504/*! CH13_ERROR_STATUS
2505 * 0b0..An early termination from the device causes error IRQ.
2506 * 0b1..An AHB bus error causes error IRQ.
2507 */
2508#define APBH_CTRL2_TOG_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH13_ERROR_STATUS_MASK)
2509#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK (0x40000000U)
2510#define APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT (30U)
2511/*! CH14_ERROR_STATUS
2512 * 0b0..An early termination from the device causes error IRQ.
2513 * 0b1..An AHB bus error causes error IRQ.
2514 */
2515#define APBH_CTRL2_TOG_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH14_ERROR_STATUS_MASK)
2516#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK (0x80000000U)
2517#define APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT (31U)
2518/*! CH15_ERROR_STATUS
2519 * 0b0..An early termination from the device causes error IRQ.
2520 * 0b1..An AHB bus error causes error IRQ.
2521 */
2522#define APBH_CTRL2_TOG_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_TOG_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_TOG_CH15_ERROR_STATUS_MASK)
2523/*! @} */
2524
2525/*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */
2526/*! @{ */
2527#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU)
2528#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U)
2529/*! FREEZE_CHANNEL
2530 * 0b0000000000000001..NAND0
2531 * 0b0000000000000010..NAND1
2532 * 0b0000000000000100..NAND2
2533 * 0b0000000000001000..NAND3
2534 * 0b0000000000010000..NAND4
2535 * 0b0000000000100000..NAND5
2536 * 0b0000000001000000..NAND6
2537 * 0b0000000010000000..NAND7
2538 * 0b0000000100000000..SSP
2539 */
2540#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK)
2541#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U)
2542#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U)
2543/*! RESET_CHANNEL
2544 * 0b0000000000000001..NAND0
2545 * 0b0000000000000010..NAND1
2546 * 0b0000000000000100..NAND2
2547 * 0b0000000000001000..NAND3
2548 * 0b0000000000010000..NAND4
2549 * 0b0000000000100000..NAND5
2550 * 0b0000000001000000..NAND6
2551 * 0b0000000010000000..NAND7
2552 * 0b0000000100000000..SSP
2553 */
2554#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK)
2555/*! @} */
2556
2557/*! @name CHANNEL_CTRL_SET - AHB to APBH Bridge Channel Register */
2558/*! @{ */
2559#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK (0xFFFFU)
2560#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT (0U)
2561/*! FREEZE_CHANNEL
2562 * 0b0000000000000001..NAND0
2563 * 0b0000000000000010..NAND1
2564 * 0b0000000000000100..NAND2
2565 * 0b0000000000001000..NAND3
2566 * 0b0000000000010000..NAND4
2567 * 0b0000000000100000..NAND5
2568 * 0b0000000001000000..NAND6
2569 * 0b0000000010000000..NAND7
2570 * 0b0000000100000000..SSP
2571 */
2572#define APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_FREEZE_CHANNEL_MASK)
2573#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK (0xFFFF0000U)
2574#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT (16U)
2575/*! RESET_CHANNEL
2576 * 0b0000000000000001..NAND0
2577 * 0b0000000000000010..NAND1
2578 * 0b0000000000000100..NAND2
2579 * 0b0000000000001000..NAND3
2580 * 0b0000000000010000..NAND4
2581 * 0b0000000000100000..NAND5
2582 * 0b0000000001000000..NAND6
2583 * 0b0000000010000000..NAND7
2584 * 0b0000000100000000..SSP
2585 */
2586#define APBH_CHANNEL_CTRL_SET_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_SET_RESET_CHANNEL_MASK)
2587/*! @} */
2588
2589/*! @name CHANNEL_CTRL_CLR - AHB to APBH Bridge Channel Register */
2590/*! @{ */
2591#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK (0xFFFFU)
2592#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT (0U)
2593/*! FREEZE_CHANNEL
2594 * 0b0000000000000001..NAND0
2595 * 0b0000000000000010..NAND1
2596 * 0b0000000000000100..NAND2
2597 * 0b0000000000001000..NAND3
2598 * 0b0000000000010000..NAND4
2599 * 0b0000000000100000..NAND5
2600 * 0b0000000001000000..NAND6
2601 * 0b0000000010000000..NAND7
2602 * 0b0000000100000000..SSP
2603 */
2604#define APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_FREEZE_CHANNEL_MASK)
2605#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK (0xFFFF0000U)
2606#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT (16U)
2607/*! RESET_CHANNEL
2608 * 0b0000000000000001..NAND0
2609 * 0b0000000000000010..NAND1
2610 * 0b0000000000000100..NAND2
2611 * 0b0000000000001000..NAND3
2612 * 0b0000000000010000..NAND4
2613 * 0b0000000000100000..NAND5
2614 * 0b0000000001000000..NAND6
2615 * 0b0000000010000000..NAND7
2616 * 0b0000000100000000..SSP
2617 */
2618#define APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_CLR_RESET_CHANNEL_MASK)
2619/*! @} */
2620
2621/*! @name CHANNEL_CTRL_TOG - AHB to APBH Bridge Channel Register */
2622/*! @{ */
2623#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK (0xFFFFU)
2624#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT (0U)
2625/*! FREEZE_CHANNEL
2626 * 0b0000000000000001..NAND0
2627 * 0b0000000000000010..NAND1
2628 * 0b0000000000000100..NAND2
2629 * 0b0000000000001000..NAND3
2630 * 0b0000000000010000..NAND4
2631 * 0b0000000000100000..NAND5
2632 * 0b0000000001000000..NAND6
2633 * 0b0000000010000000..NAND7
2634 * 0b0000000100000000..SSP
2635 */
2636#define APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_FREEZE_CHANNEL_MASK)
2637#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK (0xFFFF0000U)
2638#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT (16U)
2639/*! RESET_CHANNEL
2640 * 0b0000000000000001..NAND0
2641 * 0b0000000000000010..NAND1
2642 * 0b0000000000000100..NAND2
2643 * 0b0000000000001000..NAND3
2644 * 0b0000000000010000..NAND4
2645 * 0b0000000000100000..NAND5
2646 * 0b0000000001000000..NAND6
2647 * 0b0000000010000000..NAND7
2648 * 0b0000000100000000..SSP
2649 */
2650#define APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_TOG_RESET_CHANNEL_MASK)
2651/*! @} */
2652
2653/*! @name DEVSEL - AHB to APBH DMA Device Assignment Register */
2654/*! @{ */
2655#define APBH_DEVSEL_CH0_MASK (0x3U)
2656#define APBH_DEVSEL_CH0_SHIFT (0U)
2657#define APBH_DEVSEL_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH0_SHIFT)) & APBH_DEVSEL_CH0_MASK)
2658#define APBH_DEVSEL_CH1_MASK (0xCU)
2659#define APBH_DEVSEL_CH1_SHIFT (2U)
2660#define APBH_DEVSEL_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH1_SHIFT)) & APBH_DEVSEL_CH1_MASK)
2661#define APBH_DEVSEL_CH2_MASK (0x30U)
2662#define APBH_DEVSEL_CH2_SHIFT (4U)
2663#define APBH_DEVSEL_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH2_SHIFT)) & APBH_DEVSEL_CH2_MASK)
2664#define APBH_DEVSEL_CH3_MASK (0xC0U)
2665#define APBH_DEVSEL_CH3_SHIFT (6U)
2666#define APBH_DEVSEL_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH3_SHIFT)) & APBH_DEVSEL_CH3_MASK)
2667#define APBH_DEVSEL_CH4_MASK (0x300U)
2668#define APBH_DEVSEL_CH4_SHIFT (8U)
2669#define APBH_DEVSEL_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH4_SHIFT)) & APBH_DEVSEL_CH4_MASK)
2670#define APBH_DEVSEL_CH5_MASK (0xC00U)
2671#define APBH_DEVSEL_CH5_SHIFT (10U)
2672#define APBH_DEVSEL_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH5_SHIFT)) & APBH_DEVSEL_CH5_MASK)
2673#define APBH_DEVSEL_CH6_MASK (0x3000U)
2674#define APBH_DEVSEL_CH6_SHIFT (12U)
2675#define APBH_DEVSEL_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH6_SHIFT)) & APBH_DEVSEL_CH6_MASK)
2676#define APBH_DEVSEL_CH7_MASK (0xC000U)
2677#define APBH_DEVSEL_CH7_SHIFT (14U)
2678#define APBH_DEVSEL_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH7_SHIFT)) & APBH_DEVSEL_CH7_MASK)
2679#define APBH_DEVSEL_CH8_MASK (0x30000U)
2680#define APBH_DEVSEL_CH8_SHIFT (16U)
2681#define APBH_DEVSEL_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH8_SHIFT)) & APBH_DEVSEL_CH8_MASK)
2682#define APBH_DEVSEL_CH9_MASK (0xC0000U)
2683#define APBH_DEVSEL_CH9_SHIFT (18U)
2684#define APBH_DEVSEL_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH9_SHIFT)) & APBH_DEVSEL_CH9_MASK)
2685#define APBH_DEVSEL_CH10_MASK (0x300000U)
2686#define APBH_DEVSEL_CH10_SHIFT (20U)
2687#define APBH_DEVSEL_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH10_SHIFT)) & APBH_DEVSEL_CH10_MASK)
2688#define APBH_DEVSEL_CH11_MASK (0xC00000U)
2689#define APBH_DEVSEL_CH11_SHIFT (22U)
2690#define APBH_DEVSEL_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH11_SHIFT)) & APBH_DEVSEL_CH11_MASK)
2691#define APBH_DEVSEL_CH12_MASK (0x3000000U)
2692#define APBH_DEVSEL_CH12_SHIFT (24U)
2693#define APBH_DEVSEL_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH12_SHIFT)) & APBH_DEVSEL_CH12_MASK)
2694#define APBH_DEVSEL_CH13_MASK (0xC000000U)
2695#define APBH_DEVSEL_CH13_SHIFT (26U)
2696#define APBH_DEVSEL_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH13_SHIFT)) & APBH_DEVSEL_CH13_MASK)
2697#define APBH_DEVSEL_CH14_MASK (0x30000000U)
2698#define APBH_DEVSEL_CH14_SHIFT (28U)
2699#define APBH_DEVSEL_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH14_SHIFT)) & APBH_DEVSEL_CH14_MASK)
2700#define APBH_DEVSEL_CH15_MASK (0xC0000000U)
2701#define APBH_DEVSEL_CH15_SHIFT (30U)
2702#define APBH_DEVSEL_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEVSEL_CH15_SHIFT)) & APBH_DEVSEL_CH15_MASK)
2703/*! @} */
2704
2705/*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */
2706/*! @{ */
2707#define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U)
2708#define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U)
2709#define APBH_DMA_BURST_SIZE_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK)
2710#define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU)
2711#define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U)
2712#define APBH_DMA_BURST_SIZE_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK)
2713#define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U)
2714#define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U)
2715#define APBH_DMA_BURST_SIZE_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK)
2716#define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U)
2717#define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U)
2718#define APBH_DMA_BURST_SIZE_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK)
2719#define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U)
2720#define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U)
2721#define APBH_DMA_BURST_SIZE_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK)
2722#define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U)
2723#define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U)
2724#define APBH_DMA_BURST_SIZE_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK)
2725#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U)
2726#define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U)
2727#define APBH_DMA_BURST_SIZE_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK)
2728#define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U)
2729#define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U)
2730#define APBH_DMA_BURST_SIZE_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK)
2731#define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U)
2732#define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U)
2733/*! CH8
2734 * 0b00..BURST0
2735 * 0b01..BURST4
2736 * 0b10..BURST8
2737 */
2738#define APBH_DMA_BURST_SIZE_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK)
2739#define APBH_DMA_BURST_SIZE_CH9_MASK (0xC0000U)
2740#define APBH_DMA_BURST_SIZE_CH9_SHIFT (18U)
2741#define APBH_DMA_BURST_SIZE_CH9(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH9_SHIFT)) & APBH_DMA_BURST_SIZE_CH9_MASK)
2742#define APBH_DMA_BURST_SIZE_CH10_MASK (0x300000U)
2743#define APBH_DMA_BURST_SIZE_CH10_SHIFT (20U)
2744#define APBH_DMA_BURST_SIZE_CH10(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH10_SHIFT)) & APBH_DMA_BURST_SIZE_CH10_MASK)
2745#define APBH_DMA_BURST_SIZE_CH11_MASK (0xC00000U)
2746#define APBH_DMA_BURST_SIZE_CH11_SHIFT (22U)
2747#define APBH_DMA_BURST_SIZE_CH11(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH11_SHIFT)) & APBH_DMA_BURST_SIZE_CH11_MASK)
2748#define APBH_DMA_BURST_SIZE_CH12_MASK (0x3000000U)
2749#define APBH_DMA_BURST_SIZE_CH12_SHIFT (24U)
2750#define APBH_DMA_BURST_SIZE_CH12(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH12_SHIFT)) & APBH_DMA_BURST_SIZE_CH12_MASK)
2751#define APBH_DMA_BURST_SIZE_CH13_MASK (0xC000000U)
2752#define APBH_DMA_BURST_SIZE_CH13_SHIFT (26U)
2753#define APBH_DMA_BURST_SIZE_CH13(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH13_SHIFT)) & APBH_DMA_BURST_SIZE_CH13_MASK)
2754#define APBH_DMA_BURST_SIZE_CH14_MASK (0x30000000U)
2755#define APBH_DMA_BURST_SIZE_CH14_SHIFT (28U)
2756#define APBH_DMA_BURST_SIZE_CH14(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH14_SHIFT)) & APBH_DMA_BURST_SIZE_CH14_MASK)
2757#define APBH_DMA_BURST_SIZE_CH15_MASK (0xC0000000U)
2758#define APBH_DMA_BURST_SIZE_CH15_SHIFT (30U)
2759#define APBH_DMA_BURST_SIZE_CH15(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH15_SHIFT)) & APBH_DMA_BURST_SIZE_CH15_MASK)
2760/*! @} */
2761
2762/*! @name DEBUG - AHB to APBH DMA Debug Register */
2763/*! @{ */
2764#define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U)
2765#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U)
2766#define APBH_DEBUG_GPMI_ONE_FIFO(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK)
2767/*! @} */
2768
2769/*! @name CH0_CURCMDAR - APBH DMA Channel n Current Command Address Register */
2770/*! @{ */
2771#define APBH_CH0_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
2772#define APBH_CH0_CURCMDAR_CMD_ADDR_SHIFT (0U)
2773#define APBH_CH0_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH0_CURCMDAR_CMD_ADDR_MASK)
2774/*! @} */
2775
2776/*! @name CH0_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
2777/*! @{ */
2778#define APBH_CH0_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
2779#define APBH_CH0_NXTCMDAR_CMD_ADDR_SHIFT (0U)
2780#define APBH_CH0_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH0_NXTCMDAR_CMD_ADDR_MASK)
2781/*! @} */
2782
2783/*! @name CH0_CMD - APBH DMA Channel n Command Register */
2784/*! @{ */
2785#define APBH_CH0_CMD_COMMAND_MASK (0x3U)
2786#define APBH_CH0_CMD_COMMAND_SHIFT (0U)
2787/*! COMMAND
2788 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
2789 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
2790 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
2791 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
2792 */
2793#define APBH_CH0_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_COMMAND_SHIFT)) & APBH_CH0_CMD_COMMAND_MASK)
2794#define APBH_CH0_CMD_CHAIN_MASK (0x4U)
2795#define APBH_CH0_CMD_CHAIN_SHIFT (2U)
2796#define APBH_CH0_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_CHAIN_SHIFT)) & APBH_CH0_CMD_CHAIN_MASK)
2797#define APBH_CH0_CMD_IRQONCMPLT_MASK (0x8U)
2798#define APBH_CH0_CMD_IRQONCMPLT_SHIFT (3U)
2799#define APBH_CH0_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_IRQONCMPLT_SHIFT)) & APBH_CH0_CMD_IRQONCMPLT_MASK)
2800#define APBH_CH0_CMD_NANDLOCK_MASK (0x10U)
2801#define APBH_CH0_CMD_NANDLOCK_SHIFT (4U)
2802#define APBH_CH0_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_NANDLOCK_SHIFT)) & APBH_CH0_CMD_NANDLOCK_MASK)
2803#define APBH_CH0_CMD_NANDWAIT4READY_MASK (0x20U)
2804#define APBH_CH0_CMD_NANDWAIT4READY_SHIFT (5U)
2805#define APBH_CH0_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH0_CMD_NANDWAIT4READY_MASK)
2806#define APBH_CH0_CMD_SEMAPHORE_MASK (0x40U)
2807#define APBH_CH0_CMD_SEMAPHORE_SHIFT (6U)
2808#define APBH_CH0_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_SEMAPHORE_SHIFT)) & APBH_CH0_CMD_SEMAPHORE_MASK)
2809#define APBH_CH0_CMD_WAIT4ENDCMD_MASK (0x80U)
2810#define APBH_CH0_CMD_WAIT4ENDCMD_SHIFT (7U)
2811#define APBH_CH0_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH0_CMD_WAIT4ENDCMD_MASK)
2812#define APBH_CH0_CMD_HALTONTERMINATE_MASK (0x100U)
2813#define APBH_CH0_CMD_HALTONTERMINATE_SHIFT (8U)
2814#define APBH_CH0_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH0_CMD_HALTONTERMINATE_MASK)
2815#define APBH_CH0_CMD_CMDWORDS_MASK (0xF000U)
2816#define APBH_CH0_CMD_CMDWORDS_SHIFT (12U)
2817#define APBH_CH0_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_CMDWORDS_SHIFT)) & APBH_CH0_CMD_CMDWORDS_MASK)
2818#define APBH_CH0_CMD_XFER_COUNT_MASK (0xFFFF0000U)
2819#define APBH_CH0_CMD_XFER_COUNT_SHIFT (16U)
2820#define APBH_CH0_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_CMD_XFER_COUNT_SHIFT)) & APBH_CH0_CMD_XFER_COUNT_MASK)
2821/*! @} */
2822
2823/*! @name CH0_BAR - APBH DMA Channel n Buffer Address Register */
2824/*! @{ */
2825#define APBH_CH0_BAR_ADDRESS_MASK (0xFFFFFFFFU)
2826#define APBH_CH0_BAR_ADDRESS_SHIFT (0U)
2827#define APBH_CH0_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_BAR_ADDRESS_SHIFT)) & APBH_CH0_BAR_ADDRESS_MASK)
2828/*! @} */
2829
2830/*! @name CH0_SEMA - APBH DMA Channel n Semaphore Register */
2831/*! @{ */
2832#define APBH_CH0_SEMA_INCREMENT_SEMA_MASK (0xFFU)
2833#define APBH_CH0_SEMA_INCREMENT_SEMA_SHIFT (0U)
2834#define APBH_CH0_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH0_SEMA_INCREMENT_SEMA_MASK)
2835#define APBH_CH0_SEMA_PHORE_MASK (0xFF0000U)
2836#define APBH_CH0_SEMA_PHORE_SHIFT (16U)
2837#define APBH_CH0_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_SEMA_PHORE_SHIFT)) & APBH_CH0_SEMA_PHORE_MASK)
2838/*! @} */
2839
2840/*! @name CH0_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
2841/*! @{ */
2842#define APBH_CH0_DEBUG1_STATEMACHINE_MASK (0x1FU)
2843#define APBH_CH0_DEBUG1_STATEMACHINE_SHIFT (0U)
2844/*! STATEMACHINE
2845 * 0b00000..This is the idle state of the DMA state machine.
2846 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
2847 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
2848 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
2849 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
2850 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
2851 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
2852 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
2853 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
2854 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
2855 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
2856 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
2857 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
2858 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
2859 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
2860 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
2861 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
2862 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
2863 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
2864 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
2865 */
2866#define APBH_CH0_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH0_DEBUG1_STATEMACHINE_MASK)
2867#define APBH_CH0_DEBUG1_RSVD1_MASK (0xFFFE0U)
2868#define APBH_CH0_DEBUG1_RSVD1_SHIFT (5U)
2869#define APBH_CH0_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RSVD1_SHIFT)) & APBH_CH0_DEBUG1_RSVD1_MASK)
2870#define APBH_CH0_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
2871#define APBH_CH0_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
2872#define APBH_CH0_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH0_DEBUG1_WR_FIFO_FULL_MASK)
2873#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
2874#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
2875#define APBH_CH0_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH0_DEBUG1_WR_FIFO_EMPTY_MASK)
2876#define APBH_CH0_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
2877#define APBH_CH0_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
2878#define APBH_CH0_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH0_DEBUG1_RD_FIFO_FULL_MASK)
2879#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
2880#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
2881#define APBH_CH0_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH0_DEBUG1_RD_FIFO_EMPTY_MASK)
2882#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
2883#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
2884#define APBH_CH0_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH0_DEBUG1_NEXTCMDADDRVALID_MASK)
2885#define APBH_CH0_DEBUG1_LOCK_MASK (0x2000000U)
2886#define APBH_CH0_DEBUG1_LOCK_SHIFT (25U)
2887#define APBH_CH0_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_LOCK_SHIFT)) & APBH_CH0_DEBUG1_LOCK_MASK)
2888#define APBH_CH0_DEBUG1_READY_MASK (0x4000000U)
2889#define APBH_CH0_DEBUG1_READY_SHIFT (26U)
2890#define APBH_CH0_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_READY_SHIFT)) & APBH_CH0_DEBUG1_READY_MASK)
2891#define APBH_CH0_DEBUG1_SENSE_MASK (0x8000000U)
2892#define APBH_CH0_DEBUG1_SENSE_SHIFT (27U)
2893#define APBH_CH0_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_SENSE_SHIFT)) & APBH_CH0_DEBUG1_SENSE_MASK)
2894#define APBH_CH0_DEBUG1_END_MASK (0x10000000U)
2895#define APBH_CH0_DEBUG1_END_SHIFT (28U)
2896#define APBH_CH0_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_END_SHIFT)) & APBH_CH0_DEBUG1_END_MASK)
2897#define APBH_CH0_DEBUG1_KICK_MASK (0x20000000U)
2898#define APBH_CH0_DEBUG1_KICK_SHIFT (29U)
2899#define APBH_CH0_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_KICK_SHIFT)) & APBH_CH0_DEBUG1_KICK_MASK)
2900#define APBH_CH0_DEBUG1_BURST_MASK (0x40000000U)
2901#define APBH_CH0_DEBUG1_BURST_SHIFT (30U)
2902#define APBH_CH0_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_BURST_SHIFT)) & APBH_CH0_DEBUG1_BURST_MASK)
2903#define APBH_CH0_DEBUG1_REQ_MASK (0x80000000U)
2904#define APBH_CH0_DEBUG1_REQ_SHIFT (31U)
2905#define APBH_CH0_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG1_REQ_SHIFT)) & APBH_CH0_DEBUG1_REQ_MASK)
2906/*! @} */
2907
2908/*! @name CH0_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
2909/*! @{ */
2910#define APBH_CH0_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
2911#define APBH_CH0_DEBUG2_AHB_BYTES_SHIFT (0U)
2912#define APBH_CH0_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH0_DEBUG2_AHB_BYTES_MASK)
2913#define APBH_CH0_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
2914#define APBH_CH0_DEBUG2_APB_BYTES_SHIFT (16U)
2915#define APBH_CH0_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH0_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH0_DEBUG2_APB_BYTES_MASK)
2916/*! @} */
2917
2918/*! @name CH1_CURCMDAR - APBH DMA Channel n Current Command Address Register */
2919/*! @{ */
2920#define APBH_CH1_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
2921#define APBH_CH1_CURCMDAR_CMD_ADDR_SHIFT (0U)
2922#define APBH_CH1_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH1_CURCMDAR_CMD_ADDR_MASK)
2923/*! @} */
2924
2925/*! @name CH1_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
2926/*! @{ */
2927#define APBH_CH1_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
2928#define APBH_CH1_NXTCMDAR_CMD_ADDR_SHIFT (0U)
2929#define APBH_CH1_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH1_NXTCMDAR_CMD_ADDR_MASK)
2930/*! @} */
2931
2932/*! @name CH1_CMD - APBH DMA Channel n Command Register */
2933/*! @{ */
2934#define APBH_CH1_CMD_COMMAND_MASK (0x3U)
2935#define APBH_CH1_CMD_COMMAND_SHIFT (0U)
2936/*! COMMAND
2937 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
2938 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
2939 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
2940 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
2941 */
2942#define APBH_CH1_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_COMMAND_SHIFT)) & APBH_CH1_CMD_COMMAND_MASK)
2943#define APBH_CH1_CMD_CHAIN_MASK (0x4U)
2944#define APBH_CH1_CMD_CHAIN_SHIFT (2U)
2945#define APBH_CH1_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_CHAIN_SHIFT)) & APBH_CH1_CMD_CHAIN_MASK)
2946#define APBH_CH1_CMD_IRQONCMPLT_MASK (0x8U)
2947#define APBH_CH1_CMD_IRQONCMPLT_SHIFT (3U)
2948#define APBH_CH1_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_IRQONCMPLT_SHIFT)) & APBH_CH1_CMD_IRQONCMPLT_MASK)
2949#define APBH_CH1_CMD_NANDLOCK_MASK (0x10U)
2950#define APBH_CH1_CMD_NANDLOCK_SHIFT (4U)
2951#define APBH_CH1_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_NANDLOCK_SHIFT)) & APBH_CH1_CMD_NANDLOCK_MASK)
2952#define APBH_CH1_CMD_NANDWAIT4READY_MASK (0x20U)
2953#define APBH_CH1_CMD_NANDWAIT4READY_SHIFT (5U)
2954#define APBH_CH1_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH1_CMD_NANDWAIT4READY_MASK)
2955#define APBH_CH1_CMD_SEMAPHORE_MASK (0x40U)
2956#define APBH_CH1_CMD_SEMAPHORE_SHIFT (6U)
2957#define APBH_CH1_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_SEMAPHORE_SHIFT)) & APBH_CH1_CMD_SEMAPHORE_MASK)
2958#define APBH_CH1_CMD_WAIT4ENDCMD_MASK (0x80U)
2959#define APBH_CH1_CMD_WAIT4ENDCMD_SHIFT (7U)
2960#define APBH_CH1_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH1_CMD_WAIT4ENDCMD_MASK)
2961#define APBH_CH1_CMD_HALTONTERMINATE_MASK (0x100U)
2962#define APBH_CH1_CMD_HALTONTERMINATE_SHIFT (8U)
2963#define APBH_CH1_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH1_CMD_HALTONTERMINATE_MASK)
2964#define APBH_CH1_CMD_CMDWORDS_MASK (0xF000U)
2965#define APBH_CH1_CMD_CMDWORDS_SHIFT (12U)
2966#define APBH_CH1_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_CMDWORDS_SHIFT)) & APBH_CH1_CMD_CMDWORDS_MASK)
2967#define APBH_CH1_CMD_XFER_COUNT_MASK (0xFFFF0000U)
2968#define APBH_CH1_CMD_XFER_COUNT_SHIFT (16U)
2969#define APBH_CH1_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_CMD_XFER_COUNT_SHIFT)) & APBH_CH1_CMD_XFER_COUNT_MASK)
2970/*! @} */
2971
2972/*! @name CH1_BAR - APBH DMA Channel n Buffer Address Register */
2973/*! @{ */
2974#define APBH_CH1_BAR_ADDRESS_MASK (0xFFFFFFFFU)
2975#define APBH_CH1_BAR_ADDRESS_SHIFT (0U)
2976#define APBH_CH1_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_BAR_ADDRESS_SHIFT)) & APBH_CH1_BAR_ADDRESS_MASK)
2977/*! @} */
2978
2979/*! @name CH1_SEMA - APBH DMA Channel n Semaphore Register */
2980/*! @{ */
2981#define APBH_CH1_SEMA_INCREMENT_SEMA_MASK (0xFFU)
2982#define APBH_CH1_SEMA_INCREMENT_SEMA_SHIFT (0U)
2983#define APBH_CH1_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH1_SEMA_INCREMENT_SEMA_MASK)
2984#define APBH_CH1_SEMA_PHORE_MASK (0xFF0000U)
2985#define APBH_CH1_SEMA_PHORE_SHIFT (16U)
2986#define APBH_CH1_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_SEMA_PHORE_SHIFT)) & APBH_CH1_SEMA_PHORE_MASK)
2987/*! @} */
2988
2989/*! @name CH1_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
2990/*! @{ */
2991#define APBH_CH1_DEBUG1_STATEMACHINE_MASK (0x1FU)
2992#define APBH_CH1_DEBUG1_STATEMACHINE_SHIFT (0U)
2993/*! STATEMACHINE
2994 * 0b00000..This is the idle state of the DMA state machine.
2995 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
2996 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
2997 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
2998 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
2999 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
3000 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
3001 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
3002 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
3003 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
3004 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3005 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3006 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
3007 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
3008 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
3009 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
3010 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
3011 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
3012 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
3013 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
3014 */
3015#define APBH_CH1_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH1_DEBUG1_STATEMACHINE_MASK)
3016#define APBH_CH1_DEBUG1_RSVD1_MASK (0xFFFE0U)
3017#define APBH_CH1_DEBUG1_RSVD1_SHIFT (5U)
3018#define APBH_CH1_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RSVD1_SHIFT)) & APBH_CH1_DEBUG1_RSVD1_MASK)
3019#define APBH_CH1_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
3020#define APBH_CH1_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
3021#define APBH_CH1_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH1_DEBUG1_WR_FIFO_FULL_MASK)
3022#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
3023#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
3024#define APBH_CH1_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH1_DEBUG1_WR_FIFO_EMPTY_MASK)
3025#define APBH_CH1_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
3026#define APBH_CH1_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
3027#define APBH_CH1_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH1_DEBUG1_RD_FIFO_FULL_MASK)
3028#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
3029#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
3030#define APBH_CH1_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH1_DEBUG1_RD_FIFO_EMPTY_MASK)
3031#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
3032#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
3033#define APBH_CH1_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH1_DEBUG1_NEXTCMDADDRVALID_MASK)
3034#define APBH_CH1_DEBUG1_LOCK_MASK (0x2000000U)
3035#define APBH_CH1_DEBUG1_LOCK_SHIFT (25U)
3036#define APBH_CH1_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_LOCK_SHIFT)) & APBH_CH1_DEBUG1_LOCK_MASK)
3037#define APBH_CH1_DEBUG1_READY_MASK (0x4000000U)
3038#define APBH_CH1_DEBUG1_READY_SHIFT (26U)
3039#define APBH_CH1_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_READY_SHIFT)) & APBH_CH1_DEBUG1_READY_MASK)
3040#define APBH_CH1_DEBUG1_SENSE_MASK (0x8000000U)
3041#define APBH_CH1_DEBUG1_SENSE_SHIFT (27U)
3042#define APBH_CH1_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_SENSE_SHIFT)) & APBH_CH1_DEBUG1_SENSE_MASK)
3043#define APBH_CH1_DEBUG1_END_MASK (0x10000000U)
3044#define APBH_CH1_DEBUG1_END_SHIFT (28U)
3045#define APBH_CH1_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_END_SHIFT)) & APBH_CH1_DEBUG1_END_MASK)
3046#define APBH_CH1_DEBUG1_KICK_MASK (0x20000000U)
3047#define APBH_CH1_DEBUG1_KICK_SHIFT (29U)
3048#define APBH_CH1_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_KICK_SHIFT)) & APBH_CH1_DEBUG1_KICK_MASK)
3049#define APBH_CH1_DEBUG1_BURST_MASK (0x40000000U)
3050#define APBH_CH1_DEBUG1_BURST_SHIFT (30U)
3051#define APBH_CH1_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_BURST_SHIFT)) & APBH_CH1_DEBUG1_BURST_MASK)
3052#define APBH_CH1_DEBUG1_REQ_MASK (0x80000000U)
3053#define APBH_CH1_DEBUG1_REQ_SHIFT (31U)
3054#define APBH_CH1_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG1_REQ_SHIFT)) & APBH_CH1_DEBUG1_REQ_MASK)
3055/*! @} */
3056
3057/*! @name CH1_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
3058/*! @{ */
3059#define APBH_CH1_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
3060#define APBH_CH1_DEBUG2_AHB_BYTES_SHIFT (0U)
3061#define APBH_CH1_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH1_DEBUG2_AHB_BYTES_MASK)
3062#define APBH_CH1_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
3063#define APBH_CH1_DEBUG2_APB_BYTES_SHIFT (16U)
3064#define APBH_CH1_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH1_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH1_DEBUG2_APB_BYTES_MASK)
3065/*! @} */
3066
3067/*! @name CH2_CURCMDAR - APBH DMA Channel n Current Command Address Register */
3068/*! @{ */
3069#define APBH_CH2_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3070#define APBH_CH2_CURCMDAR_CMD_ADDR_SHIFT (0U)
3071#define APBH_CH2_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH2_CURCMDAR_CMD_ADDR_MASK)
3072/*! @} */
3073
3074/*! @name CH2_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
3075/*! @{ */
3076#define APBH_CH2_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3077#define APBH_CH2_NXTCMDAR_CMD_ADDR_SHIFT (0U)
3078#define APBH_CH2_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH2_NXTCMDAR_CMD_ADDR_MASK)
3079/*! @} */
3080
3081/*! @name CH2_CMD - APBH DMA Channel n Command Register */
3082/*! @{ */
3083#define APBH_CH2_CMD_COMMAND_MASK (0x3U)
3084#define APBH_CH2_CMD_COMMAND_SHIFT (0U)
3085/*! COMMAND
3086 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
3087 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
3088 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
3089 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
3090 */
3091#define APBH_CH2_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_COMMAND_SHIFT)) & APBH_CH2_CMD_COMMAND_MASK)
3092#define APBH_CH2_CMD_CHAIN_MASK (0x4U)
3093#define APBH_CH2_CMD_CHAIN_SHIFT (2U)
3094#define APBH_CH2_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_CHAIN_SHIFT)) & APBH_CH2_CMD_CHAIN_MASK)
3095#define APBH_CH2_CMD_IRQONCMPLT_MASK (0x8U)
3096#define APBH_CH2_CMD_IRQONCMPLT_SHIFT (3U)
3097#define APBH_CH2_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_IRQONCMPLT_SHIFT)) & APBH_CH2_CMD_IRQONCMPLT_MASK)
3098#define APBH_CH2_CMD_NANDLOCK_MASK (0x10U)
3099#define APBH_CH2_CMD_NANDLOCK_SHIFT (4U)
3100#define APBH_CH2_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_NANDLOCK_SHIFT)) & APBH_CH2_CMD_NANDLOCK_MASK)
3101#define APBH_CH2_CMD_NANDWAIT4READY_MASK (0x20U)
3102#define APBH_CH2_CMD_NANDWAIT4READY_SHIFT (5U)
3103#define APBH_CH2_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH2_CMD_NANDWAIT4READY_MASK)
3104#define APBH_CH2_CMD_SEMAPHORE_MASK (0x40U)
3105#define APBH_CH2_CMD_SEMAPHORE_SHIFT (6U)
3106#define APBH_CH2_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_SEMAPHORE_SHIFT)) & APBH_CH2_CMD_SEMAPHORE_MASK)
3107#define APBH_CH2_CMD_WAIT4ENDCMD_MASK (0x80U)
3108#define APBH_CH2_CMD_WAIT4ENDCMD_SHIFT (7U)
3109#define APBH_CH2_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH2_CMD_WAIT4ENDCMD_MASK)
3110#define APBH_CH2_CMD_HALTONTERMINATE_MASK (0x100U)
3111#define APBH_CH2_CMD_HALTONTERMINATE_SHIFT (8U)
3112#define APBH_CH2_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH2_CMD_HALTONTERMINATE_MASK)
3113#define APBH_CH2_CMD_CMDWORDS_MASK (0xF000U)
3114#define APBH_CH2_CMD_CMDWORDS_SHIFT (12U)
3115#define APBH_CH2_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_CMDWORDS_SHIFT)) & APBH_CH2_CMD_CMDWORDS_MASK)
3116#define APBH_CH2_CMD_XFER_COUNT_MASK (0xFFFF0000U)
3117#define APBH_CH2_CMD_XFER_COUNT_SHIFT (16U)
3118#define APBH_CH2_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_CMD_XFER_COUNT_SHIFT)) & APBH_CH2_CMD_XFER_COUNT_MASK)
3119/*! @} */
3120
3121/*! @name CH2_BAR - APBH DMA Channel n Buffer Address Register */
3122/*! @{ */
3123#define APBH_CH2_BAR_ADDRESS_MASK (0xFFFFFFFFU)
3124#define APBH_CH2_BAR_ADDRESS_SHIFT (0U)
3125#define APBH_CH2_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_BAR_ADDRESS_SHIFT)) & APBH_CH2_BAR_ADDRESS_MASK)
3126/*! @} */
3127
3128/*! @name CH2_SEMA - APBH DMA Channel n Semaphore Register */
3129/*! @{ */
3130#define APBH_CH2_SEMA_INCREMENT_SEMA_MASK (0xFFU)
3131#define APBH_CH2_SEMA_INCREMENT_SEMA_SHIFT (0U)
3132#define APBH_CH2_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH2_SEMA_INCREMENT_SEMA_MASK)
3133#define APBH_CH2_SEMA_PHORE_MASK (0xFF0000U)
3134#define APBH_CH2_SEMA_PHORE_SHIFT (16U)
3135#define APBH_CH2_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_SEMA_PHORE_SHIFT)) & APBH_CH2_SEMA_PHORE_MASK)
3136/*! @} */
3137
3138/*! @name CH2_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
3139/*! @{ */
3140#define APBH_CH2_DEBUG1_STATEMACHINE_MASK (0x1FU)
3141#define APBH_CH2_DEBUG1_STATEMACHINE_SHIFT (0U)
3142/*! STATEMACHINE
3143 * 0b00000..This is the idle state of the DMA state machine.
3144 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
3145 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
3146 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
3147 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
3148 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
3149 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
3150 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
3151 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
3152 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
3153 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3154 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3155 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
3156 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
3157 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
3158 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
3159 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
3160 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
3161 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
3162 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
3163 */
3164#define APBH_CH2_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH2_DEBUG1_STATEMACHINE_MASK)
3165#define APBH_CH2_DEBUG1_RSVD1_MASK (0xFFFE0U)
3166#define APBH_CH2_DEBUG1_RSVD1_SHIFT (5U)
3167#define APBH_CH2_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RSVD1_SHIFT)) & APBH_CH2_DEBUG1_RSVD1_MASK)
3168#define APBH_CH2_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
3169#define APBH_CH2_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
3170#define APBH_CH2_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH2_DEBUG1_WR_FIFO_FULL_MASK)
3171#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
3172#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
3173#define APBH_CH2_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH2_DEBUG1_WR_FIFO_EMPTY_MASK)
3174#define APBH_CH2_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
3175#define APBH_CH2_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
3176#define APBH_CH2_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH2_DEBUG1_RD_FIFO_FULL_MASK)
3177#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
3178#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
3179#define APBH_CH2_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH2_DEBUG1_RD_FIFO_EMPTY_MASK)
3180#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
3181#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
3182#define APBH_CH2_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH2_DEBUG1_NEXTCMDADDRVALID_MASK)
3183#define APBH_CH2_DEBUG1_LOCK_MASK (0x2000000U)
3184#define APBH_CH2_DEBUG1_LOCK_SHIFT (25U)
3185#define APBH_CH2_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_LOCK_SHIFT)) & APBH_CH2_DEBUG1_LOCK_MASK)
3186#define APBH_CH2_DEBUG1_READY_MASK (0x4000000U)
3187#define APBH_CH2_DEBUG1_READY_SHIFT (26U)
3188#define APBH_CH2_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_READY_SHIFT)) & APBH_CH2_DEBUG1_READY_MASK)
3189#define APBH_CH2_DEBUG1_SENSE_MASK (0x8000000U)
3190#define APBH_CH2_DEBUG1_SENSE_SHIFT (27U)
3191#define APBH_CH2_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_SENSE_SHIFT)) & APBH_CH2_DEBUG1_SENSE_MASK)
3192#define APBH_CH2_DEBUG1_END_MASK (0x10000000U)
3193#define APBH_CH2_DEBUG1_END_SHIFT (28U)
3194#define APBH_CH2_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_END_SHIFT)) & APBH_CH2_DEBUG1_END_MASK)
3195#define APBH_CH2_DEBUG1_KICK_MASK (0x20000000U)
3196#define APBH_CH2_DEBUG1_KICK_SHIFT (29U)
3197#define APBH_CH2_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_KICK_SHIFT)) & APBH_CH2_DEBUG1_KICK_MASK)
3198#define APBH_CH2_DEBUG1_BURST_MASK (0x40000000U)
3199#define APBH_CH2_DEBUG1_BURST_SHIFT (30U)
3200#define APBH_CH2_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_BURST_SHIFT)) & APBH_CH2_DEBUG1_BURST_MASK)
3201#define APBH_CH2_DEBUG1_REQ_MASK (0x80000000U)
3202#define APBH_CH2_DEBUG1_REQ_SHIFT (31U)
3203#define APBH_CH2_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG1_REQ_SHIFT)) & APBH_CH2_DEBUG1_REQ_MASK)
3204/*! @} */
3205
3206/*! @name CH2_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
3207/*! @{ */
3208#define APBH_CH2_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
3209#define APBH_CH2_DEBUG2_AHB_BYTES_SHIFT (0U)
3210#define APBH_CH2_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH2_DEBUG2_AHB_BYTES_MASK)
3211#define APBH_CH2_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
3212#define APBH_CH2_DEBUG2_APB_BYTES_SHIFT (16U)
3213#define APBH_CH2_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH2_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH2_DEBUG2_APB_BYTES_MASK)
3214/*! @} */
3215
3216/*! @name CH3_CURCMDAR - APBH DMA Channel n Current Command Address Register */
3217/*! @{ */
3218#define APBH_CH3_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3219#define APBH_CH3_CURCMDAR_CMD_ADDR_SHIFT (0U)
3220#define APBH_CH3_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH3_CURCMDAR_CMD_ADDR_MASK)
3221/*! @} */
3222
3223/*! @name CH3_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
3224/*! @{ */
3225#define APBH_CH3_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3226#define APBH_CH3_NXTCMDAR_CMD_ADDR_SHIFT (0U)
3227#define APBH_CH3_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH3_NXTCMDAR_CMD_ADDR_MASK)
3228/*! @} */
3229
3230/*! @name CH3_CMD - APBH DMA Channel n Command Register */
3231/*! @{ */
3232#define APBH_CH3_CMD_COMMAND_MASK (0x3U)
3233#define APBH_CH3_CMD_COMMAND_SHIFT (0U)
3234/*! COMMAND
3235 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
3236 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
3237 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
3238 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
3239 */
3240#define APBH_CH3_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_COMMAND_SHIFT)) & APBH_CH3_CMD_COMMAND_MASK)
3241#define APBH_CH3_CMD_CHAIN_MASK (0x4U)
3242#define APBH_CH3_CMD_CHAIN_SHIFT (2U)
3243#define APBH_CH3_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_CHAIN_SHIFT)) & APBH_CH3_CMD_CHAIN_MASK)
3244#define APBH_CH3_CMD_IRQONCMPLT_MASK (0x8U)
3245#define APBH_CH3_CMD_IRQONCMPLT_SHIFT (3U)
3246#define APBH_CH3_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_IRQONCMPLT_SHIFT)) & APBH_CH3_CMD_IRQONCMPLT_MASK)
3247#define APBH_CH3_CMD_NANDLOCK_MASK (0x10U)
3248#define APBH_CH3_CMD_NANDLOCK_SHIFT (4U)
3249#define APBH_CH3_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_NANDLOCK_SHIFT)) & APBH_CH3_CMD_NANDLOCK_MASK)
3250#define APBH_CH3_CMD_NANDWAIT4READY_MASK (0x20U)
3251#define APBH_CH3_CMD_NANDWAIT4READY_SHIFT (5U)
3252#define APBH_CH3_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH3_CMD_NANDWAIT4READY_MASK)
3253#define APBH_CH3_CMD_SEMAPHORE_MASK (0x40U)
3254#define APBH_CH3_CMD_SEMAPHORE_SHIFT (6U)
3255#define APBH_CH3_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_SEMAPHORE_SHIFT)) & APBH_CH3_CMD_SEMAPHORE_MASK)
3256#define APBH_CH3_CMD_WAIT4ENDCMD_MASK (0x80U)
3257#define APBH_CH3_CMD_WAIT4ENDCMD_SHIFT (7U)
3258#define APBH_CH3_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH3_CMD_WAIT4ENDCMD_MASK)
3259#define APBH_CH3_CMD_HALTONTERMINATE_MASK (0x100U)
3260#define APBH_CH3_CMD_HALTONTERMINATE_SHIFT (8U)
3261#define APBH_CH3_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH3_CMD_HALTONTERMINATE_MASK)
3262#define APBH_CH3_CMD_CMDWORDS_MASK (0xF000U)
3263#define APBH_CH3_CMD_CMDWORDS_SHIFT (12U)
3264#define APBH_CH3_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_CMDWORDS_SHIFT)) & APBH_CH3_CMD_CMDWORDS_MASK)
3265#define APBH_CH3_CMD_XFER_COUNT_MASK (0xFFFF0000U)
3266#define APBH_CH3_CMD_XFER_COUNT_SHIFT (16U)
3267#define APBH_CH3_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_CMD_XFER_COUNT_SHIFT)) & APBH_CH3_CMD_XFER_COUNT_MASK)
3268/*! @} */
3269
3270/*! @name CH3_BAR - APBH DMA Channel n Buffer Address Register */
3271/*! @{ */
3272#define APBH_CH3_BAR_ADDRESS_MASK (0xFFFFFFFFU)
3273#define APBH_CH3_BAR_ADDRESS_SHIFT (0U)
3274#define APBH_CH3_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_BAR_ADDRESS_SHIFT)) & APBH_CH3_BAR_ADDRESS_MASK)
3275/*! @} */
3276
3277/*! @name CH3_SEMA - APBH DMA Channel n Semaphore Register */
3278/*! @{ */
3279#define APBH_CH3_SEMA_INCREMENT_SEMA_MASK (0xFFU)
3280#define APBH_CH3_SEMA_INCREMENT_SEMA_SHIFT (0U)
3281#define APBH_CH3_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH3_SEMA_INCREMENT_SEMA_MASK)
3282#define APBH_CH3_SEMA_PHORE_MASK (0xFF0000U)
3283#define APBH_CH3_SEMA_PHORE_SHIFT (16U)
3284#define APBH_CH3_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_SEMA_PHORE_SHIFT)) & APBH_CH3_SEMA_PHORE_MASK)
3285/*! @} */
3286
3287/*! @name CH3_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
3288/*! @{ */
3289#define APBH_CH3_DEBUG1_STATEMACHINE_MASK (0x1FU)
3290#define APBH_CH3_DEBUG1_STATEMACHINE_SHIFT (0U)
3291/*! STATEMACHINE
3292 * 0b00000..This is the idle state of the DMA state machine.
3293 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
3294 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
3295 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
3296 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
3297 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
3298 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
3299 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
3300 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
3301 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
3302 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3303 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3304 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
3305 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
3306 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
3307 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
3308 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
3309 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
3310 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
3311 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
3312 */
3313#define APBH_CH3_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH3_DEBUG1_STATEMACHINE_MASK)
3314#define APBH_CH3_DEBUG1_RSVD1_MASK (0xFFFE0U)
3315#define APBH_CH3_DEBUG1_RSVD1_SHIFT (5U)
3316#define APBH_CH3_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RSVD1_SHIFT)) & APBH_CH3_DEBUG1_RSVD1_MASK)
3317#define APBH_CH3_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
3318#define APBH_CH3_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
3319#define APBH_CH3_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH3_DEBUG1_WR_FIFO_FULL_MASK)
3320#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
3321#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
3322#define APBH_CH3_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH3_DEBUG1_WR_FIFO_EMPTY_MASK)
3323#define APBH_CH3_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
3324#define APBH_CH3_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
3325#define APBH_CH3_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH3_DEBUG1_RD_FIFO_FULL_MASK)
3326#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
3327#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
3328#define APBH_CH3_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH3_DEBUG1_RD_FIFO_EMPTY_MASK)
3329#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
3330#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
3331#define APBH_CH3_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH3_DEBUG1_NEXTCMDADDRVALID_MASK)
3332#define APBH_CH3_DEBUG1_LOCK_MASK (0x2000000U)
3333#define APBH_CH3_DEBUG1_LOCK_SHIFT (25U)
3334#define APBH_CH3_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_LOCK_SHIFT)) & APBH_CH3_DEBUG1_LOCK_MASK)
3335#define APBH_CH3_DEBUG1_READY_MASK (0x4000000U)
3336#define APBH_CH3_DEBUG1_READY_SHIFT (26U)
3337#define APBH_CH3_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_READY_SHIFT)) & APBH_CH3_DEBUG1_READY_MASK)
3338#define APBH_CH3_DEBUG1_SENSE_MASK (0x8000000U)
3339#define APBH_CH3_DEBUG1_SENSE_SHIFT (27U)
3340#define APBH_CH3_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_SENSE_SHIFT)) & APBH_CH3_DEBUG1_SENSE_MASK)
3341#define APBH_CH3_DEBUG1_END_MASK (0x10000000U)
3342#define APBH_CH3_DEBUG1_END_SHIFT (28U)
3343#define APBH_CH3_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_END_SHIFT)) & APBH_CH3_DEBUG1_END_MASK)
3344#define APBH_CH3_DEBUG1_KICK_MASK (0x20000000U)
3345#define APBH_CH3_DEBUG1_KICK_SHIFT (29U)
3346#define APBH_CH3_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_KICK_SHIFT)) & APBH_CH3_DEBUG1_KICK_MASK)
3347#define APBH_CH3_DEBUG1_BURST_MASK (0x40000000U)
3348#define APBH_CH3_DEBUG1_BURST_SHIFT (30U)
3349#define APBH_CH3_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_BURST_SHIFT)) & APBH_CH3_DEBUG1_BURST_MASK)
3350#define APBH_CH3_DEBUG1_REQ_MASK (0x80000000U)
3351#define APBH_CH3_DEBUG1_REQ_SHIFT (31U)
3352#define APBH_CH3_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG1_REQ_SHIFT)) & APBH_CH3_DEBUG1_REQ_MASK)
3353/*! @} */
3354
3355/*! @name CH3_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
3356/*! @{ */
3357#define APBH_CH3_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
3358#define APBH_CH3_DEBUG2_AHB_BYTES_SHIFT (0U)
3359#define APBH_CH3_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH3_DEBUG2_AHB_BYTES_MASK)
3360#define APBH_CH3_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
3361#define APBH_CH3_DEBUG2_APB_BYTES_SHIFT (16U)
3362#define APBH_CH3_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH3_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH3_DEBUG2_APB_BYTES_MASK)
3363/*! @} */
3364
3365/*! @name CH4_CURCMDAR - APBH DMA Channel n Current Command Address Register */
3366/*! @{ */
3367#define APBH_CH4_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3368#define APBH_CH4_CURCMDAR_CMD_ADDR_SHIFT (0U)
3369#define APBH_CH4_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH4_CURCMDAR_CMD_ADDR_MASK)
3370/*! @} */
3371
3372/*! @name CH4_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
3373/*! @{ */
3374#define APBH_CH4_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3375#define APBH_CH4_NXTCMDAR_CMD_ADDR_SHIFT (0U)
3376#define APBH_CH4_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH4_NXTCMDAR_CMD_ADDR_MASK)
3377/*! @} */
3378
3379/*! @name CH4_CMD - APBH DMA Channel n Command Register */
3380/*! @{ */
3381#define APBH_CH4_CMD_COMMAND_MASK (0x3U)
3382#define APBH_CH4_CMD_COMMAND_SHIFT (0U)
3383/*! COMMAND
3384 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
3385 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
3386 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
3387 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
3388 */
3389#define APBH_CH4_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_COMMAND_SHIFT)) & APBH_CH4_CMD_COMMAND_MASK)
3390#define APBH_CH4_CMD_CHAIN_MASK (0x4U)
3391#define APBH_CH4_CMD_CHAIN_SHIFT (2U)
3392#define APBH_CH4_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_CHAIN_SHIFT)) & APBH_CH4_CMD_CHAIN_MASK)
3393#define APBH_CH4_CMD_IRQONCMPLT_MASK (0x8U)
3394#define APBH_CH4_CMD_IRQONCMPLT_SHIFT (3U)
3395#define APBH_CH4_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_IRQONCMPLT_SHIFT)) & APBH_CH4_CMD_IRQONCMPLT_MASK)
3396#define APBH_CH4_CMD_NANDLOCK_MASK (0x10U)
3397#define APBH_CH4_CMD_NANDLOCK_SHIFT (4U)
3398#define APBH_CH4_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_NANDLOCK_SHIFT)) & APBH_CH4_CMD_NANDLOCK_MASK)
3399#define APBH_CH4_CMD_NANDWAIT4READY_MASK (0x20U)
3400#define APBH_CH4_CMD_NANDWAIT4READY_SHIFT (5U)
3401#define APBH_CH4_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH4_CMD_NANDWAIT4READY_MASK)
3402#define APBH_CH4_CMD_SEMAPHORE_MASK (0x40U)
3403#define APBH_CH4_CMD_SEMAPHORE_SHIFT (6U)
3404#define APBH_CH4_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_SEMAPHORE_SHIFT)) & APBH_CH4_CMD_SEMAPHORE_MASK)
3405#define APBH_CH4_CMD_WAIT4ENDCMD_MASK (0x80U)
3406#define APBH_CH4_CMD_WAIT4ENDCMD_SHIFT (7U)
3407#define APBH_CH4_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH4_CMD_WAIT4ENDCMD_MASK)
3408#define APBH_CH4_CMD_HALTONTERMINATE_MASK (0x100U)
3409#define APBH_CH4_CMD_HALTONTERMINATE_SHIFT (8U)
3410#define APBH_CH4_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH4_CMD_HALTONTERMINATE_MASK)
3411#define APBH_CH4_CMD_CMDWORDS_MASK (0xF000U)
3412#define APBH_CH4_CMD_CMDWORDS_SHIFT (12U)
3413#define APBH_CH4_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_CMDWORDS_SHIFT)) & APBH_CH4_CMD_CMDWORDS_MASK)
3414#define APBH_CH4_CMD_XFER_COUNT_MASK (0xFFFF0000U)
3415#define APBH_CH4_CMD_XFER_COUNT_SHIFT (16U)
3416#define APBH_CH4_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_CMD_XFER_COUNT_SHIFT)) & APBH_CH4_CMD_XFER_COUNT_MASK)
3417/*! @} */
3418
3419/*! @name CH4_BAR - APBH DMA Channel n Buffer Address Register */
3420/*! @{ */
3421#define APBH_CH4_BAR_ADDRESS_MASK (0xFFFFFFFFU)
3422#define APBH_CH4_BAR_ADDRESS_SHIFT (0U)
3423#define APBH_CH4_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_BAR_ADDRESS_SHIFT)) & APBH_CH4_BAR_ADDRESS_MASK)
3424/*! @} */
3425
3426/*! @name CH4_SEMA - APBH DMA Channel n Semaphore Register */
3427/*! @{ */
3428#define APBH_CH4_SEMA_INCREMENT_SEMA_MASK (0xFFU)
3429#define APBH_CH4_SEMA_INCREMENT_SEMA_SHIFT (0U)
3430#define APBH_CH4_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH4_SEMA_INCREMENT_SEMA_MASK)
3431#define APBH_CH4_SEMA_PHORE_MASK (0xFF0000U)
3432#define APBH_CH4_SEMA_PHORE_SHIFT (16U)
3433#define APBH_CH4_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_SEMA_PHORE_SHIFT)) & APBH_CH4_SEMA_PHORE_MASK)
3434/*! @} */
3435
3436/*! @name CH4_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
3437/*! @{ */
3438#define APBH_CH4_DEBUG1_STATEMACHINE_MASK (0x1FU)
3439#define APBH_CH4_DEBUG1_STATEMACHINE_SHIFT (0U)
3440/*! STATEMACHINE
3441 * 0b00000..This is the idle state of the DMA state machine.
3442 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
3443 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
3444 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
3445 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
3446 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
3447 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
3448 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
3449 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
3450 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
3451 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3452 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3453 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
3454 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
3455 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
3456 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
3457 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
3458 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
3459 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
3460 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
3461 */
3462#define APBH_CH4_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH4_DEBUG1_STATEMACHINE_MASK)
3463#define APBH_CH4_DEBUG1_RSVD1_MASK (0xFFFE0U)
3464#define APBH_CH4_DEBUG1_RSVD1_SHIFT (5U)
3465#define APBH_CH4_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RSVD1_SHIFT)) & APBH_CH4_DEBUG1_RSVD1_MASK)
3466#define APBH_CH4_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
3467#define APBH_CH4_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
3468#define APBH_CH4_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH4_DEBUG1_WR_FIFO_FULL_MASK)
3469#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
3470#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
3471#define APBH_CH4_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH4_DEBUG1_WR_FIFO_EMPTY_MASK)
3472#define APBH_CH4_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
3473#define APBH_CH4_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
3474#define APBH_CH4_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH4_DEBUG1_RD_FIFO_FULL_MASK)
3475#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
3476#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
3477#define APBH_CH4_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH4_DEBUG1_RD_FIFO_EMPTY_MASK)
3478#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
3479#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
3480#define APBH_CH4_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH4_DEBUG1_NEXTCMDADDRVALID_MASK)
3481#define APBH_CH4_DEBUG1_LOCK_MASK (0x2000000U)
3482#define APBH_CH4_DEBUG1_LOCK_SHIFT (25U)
3483#define APBH_CH4_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_LOCK_SHIFT)) & APBH_CH4_DEBUG1_LOCK_MASK)
3484#define APBH_CH4_DEBUG1_READY_MASK (0x4000000U)
3485#define APBH_CH4_DEBUG1_READY_SHIFT (26U)
3486#define APBH_CH4_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_READY_SHIFT)) & APBH_CH4_DEBUG1_READY_MASK)
3487#define APBH_CH4_DEBUG1_SENSE_MASK (0x8000000U)
3488#define APBH_CH4_DEBUG1_SENSE_SHIFT (27U)
3489#define APBH_CH4_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_SENSE_SHIFT)) & APBH_CH4_DEBUG1_SENSE_MASK)
3490#define APBH_CH4_DEBUG1_END_MASK (0x10000000U)
3491#define APBH_CH4_DEBUG1_END_SHIFT (28U)
3492#define APBH_CH4_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_END_SHIFT)) & APBH_CH4_DEBUG1_END_MASK)
3493#define APBH_CH4_DEBUG1_KICK_MASK (0x20000000U)
3494#define APBH_CH4_DEBUG1_KICK_SHIFT (29U)
3495#define APBH_CH4_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_KICK_SHIFT)) & APBH_CH4_DEBUG1_KICK_MASK)
3496#define APBH_CH4_DEBUG1_BURST_MASK (0x40000000U)
3497#define APBH_CH4_DEBUG1_BURST_SHIFT (30U)
3498#define APBH_CH4_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_BURST_SHIFT)) & APBH_CH4_DEBUG1_BURST_MASK)
3499#define APBH_CH4_DEBUG1_REQ_MASK (0x80000000U)
3500#define APBH_CH4_DEBUG1_REQ_SHIFT (31U)
3501#define APBH_CH4_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG1_REQ_SHIFT)) & APBH_CH4_DEBUG1_REQ_MASK)
3502/*! @} */
3503
3504/*! @name CH4_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
3505/*! @{ */
3506#define APBH_CH4_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
3507#define APBH_CH4_DEBUG2_AHB_BYTES_SHIFT (0U)
3508#define APBH_CH4_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH4_DEBUG2_AHB_BYTES_MASK)
3509#define APBH_CH4_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
3510#define APBH_CH4_DEBUG2_APB_BYTES_SHIFT (16U)
3511#define APBH_CH4_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH4_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH4_DEBUG2_APB_BYTES_MASK)
3512/*! @} */
3513
3514/*! @name CH5_CURCMDAR - APBH DMA Channel n Current Command Address Register */
3515/*! @{ */
3516#define APBH_CH5_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3517#define APBH_CH5_CURCMDAR_CMD_ADDR_SHIFT (0U)
3518#define APBH_CH5_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH5_CURCMDAR_CMD_ADDR_MASK)
3519/*! @} */
3520
3521/*! @name CH5_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
3522/*! @{ */
3523#define APBH_CH5_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3524#define APBH_CH5_NXTCMDAR_CMD_ADDR_SHIFT (0U)
3525#define APBH_CH5_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH5_NXTCMDAR_CMD_ADDR_MASK)
3526/*! @} */
3527
3528/*! @name CH5_CMD - APBH DMA Channel n Command Register */
3529/*! @{ */
3530#define APBH_CH5_CMD_COMMAND_MASK (0x3U)
3531#define APBH_CH5_CMD_COMMAND_SHIFT (0U)
3532/*! COMMAND
3533 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
3534 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
3535 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
3536 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
3537 */
3538#define APBH_CH5_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_COMMAND_SHIFT)) & APBH_CH5_CMD_COMMAND_MASK)
3539#define APBH_CH5_CMD_CHAIN_MASK (0x4U)
3540#define APBH_CH5_CMD_CHAIN_SHIFT (2U)
3541#define APBH_CH5_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_CHAIN_SHIFT)) & APBH_CH5_CMD_CHAIN_MASK)
3542#define APBH_CH5_CMD_IRQONCMPLT_MASK (0x8U)
3543#define APBH_CH5_CMD_IRQONCMPLT_SHIFT (3U)
3544#define APBH_CH5_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_IRQONCMPLT_SHIFT)) & APBH_CH5_CMD_IRQONCMPLT_MASK)
3545#define APBH_CH5_CMD_NANDLOCK_MASK (0x10U)
3546#define APBH_CH5_CMD_NANDLOCK_SHIFT (4U)
3547#define APBH_CH5_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDLOCK_SHIFT)) & APBH_CH5_CMD_NANDLOCK_MASK)
3548#define APBH_CH5_CMD_NANDWAIT4READY_MASK (0x20U)
3549#define APBH_CH5_CMD_NANDWAIT4READY_SHIFT (5U)
3550#define APBH_CH5_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH5_CMD_NANDWAIT4READY_MASK)
3551#define APBH_CH5_CMD_SEMAPHORE_MASK (0x40U)
3552#define APBH_CH5_CMD_SEMAPHORE_SHIFT (6U)
3553#define APBH_CH5_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_SEMAPHORE_SHIFT)) & APBH_CH5_CMD_SEMAPHORE_MASK)
3554#define APBH_CH5_CMD_WAIT4ENDCMD_MASK (0x80U)
3555#define APBH_CH5_CMD_WAIT4ENDCMD_SHIFT (7U)
3556#define APBH_CH5_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH5_CMD_WAIT4ENDCMD_MASK)
3557#define APBH_CH5_CMD_HALTONTERMINATE_MASK (0x100U)
3558#define APBH_CH5_CMD_HALTONTERMINATE_SHIFT (8U)
3559#define APBH_CH5_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH5_CMD_HALTONTERMINATE_MASK)
3560#define APBH_CH5_CMD_CMDWORDS_MASK (0xF000U)
3561#define APBH_CH5_CMD_CMDWORDS_SHIFT (12U)
3562#define APBH_CH5_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_CMDWORDS_SHIFT)) & APBH_CH5_CMD_CMDWORDS_MASK)
3563#define APBH_CH5_CMD_XFER_COUNT_MASK (0xFFFF0000U)
3564#define APBH_CH5_CMD_XFER_COUNT_SHIFT (16U)
3565#define APBH_CH5_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_CMD_XFER_COUNT_SHIFT)) & APBH_CH5_CMD_XFER_COUNT_MASK)
3566/*! @} */
3567
3568/*! @name CH5_BAR - APBH DMA Channel n Buffer Address Register */
3569/*! @{ */
3570#define APBH_CH5_BAR_ADDRESS_MASK (0xFFFFFFFFU)
3571#define APBH_CH5_BAR_ADDRESS_SHIFT (0U)
3572#define APBH_CH5_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_BAR_ADDRESS_SHIFT)) & APBH_CH5_BAR_ADDRESS_MASK)
3573/*! @} */
3574
3575/*! @name CH5_SEMA - APBH DMA Channel n Semaphore Register */
3576/*! @{ */
3577#define APBH_CH5_SEMA_INCREMENT_SEMA_MASK (0xFFU)
3578#define APBH_CH5_SEMA_INCREMENT_SEMA_SHIFT (0U)
3579#define APBH_CH5_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH5_SEMA_INCREMENT_SEMA_MASK)
3580#define APBH_CH5_SEMA_PHORE_MASK (0xFF0000U)
3581#define APBH_CH5_SEMA_PHORE_SHIFT (16U)
3582#define APBH_CH5_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_SEMA_PHORE_SHIFT)) & APBH_CH5_SEMA_PHORE_MASK)
3583/*! @} */
3584
3585/*! @name CH5_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
3586/*! @{ */
3587#define APBH_CH5_DEBUG1_STATEMACHINE_MASK (0x1FU)
3588#define APBH_CH5_DEBUG1_STATEMACHINE_SHIFT (0U)
3589/*! STATEMACHINE
3590 * 0b00000..This is the idle state of the DMA state machine.
3591 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
3592 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
3593 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
3594 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
3595 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
3596 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
3597 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
3598 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
3599 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
3600 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3601 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3602 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
3603 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
3604 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
3605 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
3606 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
3607 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
3608 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
3609 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
3610 */
3611#define APBH_CH5_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH5_DEBUG1_STATEMACHINE_MASK)
3612#define APBH_CH5_DEBUG1_RSVD1_MASK (0xFFFE0U)
3613#define APBH_CH5_DEBUG1_RSVD1_SHIFT (5U)
3614#define APBH_CH5_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RSVD1_SHIFT)) & APBH_CH5_DEBUG1_RSVD1_MASK)
3615#define APBH_CH5_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
3616#define APBH_CH5_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
3617#define APBH_CH5_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH5_DEBUG1_WR_FIFO_FULL_MASK)
3618#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
3619#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
3620#define APBH_CH5_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH5_DEBUG1_WR_FIFO_EMPTY_MASK)
3621#define APBH_CH5_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
3622#define APBH_CH5_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
3623#define APBH_CH5_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH5_DEBUG1_RD_FIFO_FULL_MASK)
3624#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
3625#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
3626#define APBH_CH5_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH5_DEBUG1_RD_FIFO_EMPTY_MASK)
3627#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
3628#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
3629#define APBH_CH5_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH5_DEBUG1_NEXTCMDADDRVALID_MASK)
3630#define APBH_CH5_DEBUG1_LOCK_MASK (0x2000000U)
3631#define APBH_CH5_DEBUG1_LOCK_SHIFT (25U)
3632#define APBH_CH5_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_LOCK_SHIFT)) & APBH_CH5_DEBUG1_LOCK_MASK)
3633#define APBH_CH5_DEBUG1_READY_MASK (0x4000000U)
3634#define APBH_CH5_DEBUG1_READY_SHIFT (26U)
3635#define APBH_CH5_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_READY_SHIFT)) & APBH_CH5_DEBUG1_READY_MASK)
3636#define APBH_CH5_DEBUG1_SENSE_MASK (0x8000000U)
3637#define APBH_CH5_DEBUG1_SENSE_SHIFT (27U)
3638#define APBH_CH5_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_SENSE_SHIFT)) & APBH_CH5_DEBUG1_SENSE_MASK)
3639#define APBH_CH5_DEBUG1_END_MASK (0x10000000U)
3640#define APBH_CH5_DEBUG1_END_SHIFT (28U)
3641#define APBH_CH5_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_END_SHIFT)) & APBH_CH5_DEBUG1_END_MASK)
3642#define APBH_CH5_DEBUG1_KICK_MASK (0x20000000U)
3643#define APBH_CH5_DEBUG1_KICK_SHIFT (29U)
3644#define APBH_CH5_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_KICK_SHIFT)) & APBH_CH5_DEBUG1_KICK_MASK)
3645#define APBH_CH5_DEBUG1_BURST_MASK (0x40000000U)
3646#define APBH_CH5_DEBUG1_BURST_SHIFT (30U)
3647#define APBH_CH5_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_BURST_SHIFT)) & APBH_CH5_DEBUG1_BURST_MASK)
3648#define APBH_CH5_DEBUG1_REQ_MASK (0x80000000U)
3649#define APBH_CH5_DEBUG1_REQ_SHIFT (31U)
3650#define APBH_CH5_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG1_REQ_SHIFT)) & APBH_CH5_DEBUG1_REQ_MASK)
3651/*! @} */
3652
3653/*! @name CH5_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
3654/*! @{ */
3655#define APBH_CH5_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
3656#define APBH_CH5_DEBUG2_AHB_BYTES_SHIFT (0U)
3657#define APBH_CH5_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH5_DEBUG2_AHB_BYTES_MASK)
3658#define APBH_CH5_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
3659#define APBH_CH5_DEBUG2_APB_BYTES_SHIFT (16U)
3660#define APBH_CH5_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH5_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH5_DEBUG2_APB_BYTES_MASK)
3661/*! @} */
3662
3663/*! @name CH6_CURCMDAR - APBH DMA Channel n Current Command Address Register */
3664/*! @{ */
3665#define APBH_CH6_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3666#define APBH_CH6_CURCMDAR_CMD_ADDR_SHIFT (0U)
3667#define APBH_CH6_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH6_CURCMDAR_CMD_ADDR_MASK)
3668/*! @} */
3669
3670/*! @name CH6_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
3671/*! @{ */
3672#define APBH_CH6_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3673#define APBH_CH6_NXTCMDAR_CMD_ADDR_SHIFT (0U)
3674#define APBH_CH6_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH6_NXTCMDAR_CMD_ADDR_MASK)
3675/*! @} */
3676
3677/*! @name CH6_CMD - APBH DMA Channel n Command Register */
3678/*! @{ */
3679#define APBH_CH6_CMD_COMMAND_MASK (0x3U)
3680#define APBH_CH6_CMD_COMMAND_SHIFT (0U)
3681/*! COMMAND
3682 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
3683 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
3684 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
3685 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
3686 */
3687#define APBH_CH6_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_COMMAND_SHIFT)) & APBH_CH6_CMD_COMMAND_MASK)
3688#define APBH_CH6_CMD_CHAIN_MASK (0x4U)
3689#define APBH_CH6_CMD_CHAIN_SHIFT (2U)
3690#define APBH_CH6_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_CHAIN_SHIFT)) & APBH_CH6_CMD_CHAIN_MASK)
3691#define APBH_CH6_CMD_IRQONCMPLT_MASK (0x8U)
3692#define APBH_CH6_CMD_IRQONCMPLT_SHIFT (3U)
3693#define APBH_CH6_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_IRQONCMPLT_SHIFT)) & APBH_CH6_CMD_IRQONCMPLT_MASK)
3694#define APBH_CH6_CMD_NANDLOCK_MASK (0x10U)
3695#define APBH_CH6_CMD_NANDLOCK_SHIFT (4U)
3696#define APBH_CH6_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_NANDLOCK_SHIFT)) & APBH_CH6_CMD_NANDLOCK_MASK)
3697#define APBH_CH6_CMD_NANDWAIT4READY_MASK (0x20U)
3698#define APBH_CH6_CMD_NANDWAIT4READY_SHIFT (5U)
3699#define APBH_CH6_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH6_CMD_NANDWAIT4READY_MASK)
3700#define APBH_CH6_CMD_SEMAPHORE_MASK (0x40U)
3701#define APBH_CH6_CMD_SEMAPHORE_SHIFT (6U)
3702#define APBH_CH6_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_SEMAPHORE_SHIFT)) & APBH_CH6_CMD_SEMAPHORE_MASK)
3703#define APBH_CH6_CMD_WAIT4ENDCMD_MASK (0x80U)
3704#define APBH_CH6_CMD_WAIT4ENDCMD_SHIFT (7U)
3705#define APBH_CH6_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH6_CMD_WAIT4ENDCMD_MASK)
3706#define APBH_CH6_CMD_HALTONTERMINATE_MASK (0x100U)
3707#define APBH_CH6_CMD_HALTONTERMINATE_SHIFT (8U)
3708#define APBH_CH6_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH6_CMD_HALTONTERMINATE_MASK)
3709#define APBH_CH6_CMD_CMDWORDS_MASK (0xF000U)
3710#define APBH_CH6_CMD_CMDWORDS_SHIFT (12U)
3711#define APBH_CH6_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_CMDWORDS_SHIFT)) & APBH_CH6_CMD_CMDWORDS_MASK)
3712#define APBH_CH6_CMD_XFER_COUNT_MASK (0xFFFF0000U)
3713#define APBH_CH6_CMD_XFER_COUNT_SHIFT (16U)
3714#define APBH_CH6_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_CMD_XFER_COUNT_SHIFT)) & APBH_CH6_CMD_XFER_COUNT_MASK)
3715/*! @} */
3716
3717/*! @name CH6_BAR - APBH DMA Channel n Buffer Address Register */
3718/*! @{ */
3719#define APBH_CH6_BAR_ADDRESS_MASK (0xFFFFFFFFU)
3720#define APBH_CH6_BAR_ADDRESS_SHIFT (0U)
3721#define APBH_CH6_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_BAR_ADDRESS_SHIFT)) & APBH_CH6_BAR_ADDRESS_MASK)
3722/*! @} */
3723
3724/*! @name CH6_SEMA - APBH DMA Channel n Semaphore Register */
3725/*! @{ */
3726#define APBH_CH6_SEMA_INCREMENT_SEMA_MASK (0xFFU)
3727#define APBH_CH6_SEMA_INCREMENT_SEMA_SHIFT (0U)
3728#define APBH_CH6_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH6_SEMA_INCREMENT_SEMA_MASK)
3729#define APBH_CH6_SEMA_PHORE_MASK (0xFF0000U)
3730#define APBH_CH6_SEMA_PHORE_SHIFT (16U)
3731#define APBH_CH6_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_SEMA_PHORE_SHIFT)) & APBH_CH6_SEMA_PHORE_MASK)
3732/*! @} */
3733
3734/*! @name CH6_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
3735/*! @{ */
3736#define APBH_CH6_DEBUG1_STATEMACHINE_MASK (0x1FU)
3737#define APBH_CH6_DEBUG1_STATEMACHINE_SHIFT (0U)
3738/*! STATEMACHINE
3739 * 0b00000..This is the idle state of the DMA state machine.
3740 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
3741 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
3742 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
3743 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
3744 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
3745 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the PIO words when PIO count is greater than 1.
3746 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
3747 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
3748 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
3749 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3750 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
3751 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
3752 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
3753 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
3754 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
3755 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
3756 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and effectively halts. A channel reset is required to exit this state
3757 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
3758 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device indicates that the external device is ready.
3759 */
3760#define APBH_CH6_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH6_DEBUG1_STATEMACHINE_MASK)
3761#define APBH_CH6_DEBUG1_RSVD1_MASK (0xFFFE0U)
3762#define APBH_CH6_DEBUG1_RSVD1_SHIFT (5U)
3763#define APBH_CH6_DEBUG1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RSVD1_SHIFT)) & APBH_CH6_DEBUG1_RSVD1_MASK)
3764#define APBH_CH6_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
3765#define APBH_CH6_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
3766#define APBH_CH6_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH6_DEBUG1_WR_FIFO_FULL_MASK)
3767#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
3768#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
3769#define APBH_CH6_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH6_DEBUG1_WR_FIFO_EMPTY_MASK)
3770#define APBH_CH6_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
3771#define APBH_CH6_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
3772#define APBH_CH6_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH6_DEBUG1_RD_FIFO_FULL_MASK)
3773#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
3774#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
3775#define APBH_CH6_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH6_DEBUG1_RD_FIFO_EMPTY_MASK)
3776#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
3777#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
3778#define APBH_CH6_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH6_DEBUG1_NEXTCMDADDRVALID_MASK)
3779#define APBH_CH6_DEBUG1_LOCK_MASK (0x2000000U)
3780#define APBH_CH6_DEBUG1_LOCK_SHIFT (25U)
3781#define APBH_CH6_DEBUG1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_LOCK_SHIFT)) & APBH_CH6_DEBUG1_LOCK_MASK)
3782#define APBH_CH6_DEBUG1_READY_MASK (0x4000000U)
3783#define APBH_CH6_DEBUG1_READY_SHIFT (26U)
3784#define APBH_CH6_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_READY_SHIFT)) & APBH_CH6_DEBUG1_READY_MASK)
3785#define APBH_CH6_DEBUG1_SENSE_MASK (0x8000000U)
3786#define APBH_CH6_DEBUG1_SENSE_SHIFT (27U)
3787#define APBH_CH6_DEBUG1_SENSE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_SENSE_SHIFT)) & APBH_CH6_DEBUG1_SENSE_MASK)
3788#define APBH_CH6_DEBUG1_END_MASK (0x10000000U)
3789#define APBH_CH6_DEBUG1_END_SHIFT (28U)
3790#define APBH_CH6_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_END_SHIFT)) & APBH_CH6_DEBUG1_END_MASK)
3791#define APBH_CH6_DEBUG1_KICK_MASK (0x20000000U)
3792#define APBH_CH6_DEBUG1_KICK_SHIFT (29U)
3793#define APBH_CH6_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_KICK_SHIFT)) & APBH_CH6_DEBUG1_KICK_MASK)
3794#define APBH_CH6_DEBUG1_BURST_MASK (0x40000000U)
3795#define APBH_CH6_DEBUG1_BURST_SHIFT (30U)
3796#define APBH_CH6_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_BURST_SHIFT)) & APBH_CH6_DEBUG1_BURST_MASK)
3797#define APBH_CH6_DEBUG1_REQ_MASK (0x80000000U)
3798#define APBH_CH6_DEBUG1_REQ_SHIFT (31U)
3799#define APBH_CH6_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG1_REQ_SHIFT)) & APBH_CH6_DEBUG1_REQ_MASK)
3800/*! @} */
3801
3802/*! @name CH6_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
3803/*! @{ */
3804#define APBH_CH6_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
3805#define APBH_CH6_DEBUG2_AHB_BYTES_SHIFT (0U)
3806#define APBH_CH6_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH6_DEBUG2_AHB_BYTES_MASK)
3807#define APBH_CH6_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
3808#define APBH_CH6_DEBUG2_APB_BYTES_SHIFT (16U)
3809#define APBH_CH6_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH6_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH6_DEBUG2_APB_BYTES_MASK)
3810/*! @} */
3811
3812/*! @name CH7_CURCMDAR - APBH DMA Channel n Current Command Address Register */
3813/*! @{ */
3814#define APBH_CH7_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3815#define APBH_CH7_CURCMDAR_CMD_ADDR_SHIFT (0U)
3816#define APBH_CH7_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH7_CURCMDAR_CMD_ADDR_MASK)
3817/*! @} */
3818
3819/*! @name CH7_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
3820/*! @{ */
3821#define APBH_CH7_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
3822#define APBH_CH7_NXTCMDAR_CMD_ADDR_SHIFT (0U)
3823#define APBH_CH7_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH7_NXTCMDAR_CMD_ADDR_MASK)
3824/*! @} */
3825
3826/*! @name CH7_CMD - APBH DMA Channel n Command Register */
3827/*! @{ */
3828#define APBH_CH7_CMD_COMMAND_MASK (0x3U)
3829#define APBH_CH7_CMD_COMMAND_SHIFT (0U)
3830/*! COMMAND
3831 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
3832 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
3833 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
3834 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain pointer if the peripheral sense line is false.
3835 */
3836#define APBH_CH7_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_COMMAND_SHIFT)) & APBH_CH7_CMD_COMMAND_MASK)
3837#define APBH_CH7_CMD_CHAIN_MASK (0x4U)
3838#define APBH_CH7_CMD_CHAIN_SHIFT (2U)
3839#define APBH_CH7_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_CHAIN_SHIFT)) & APBH_CH7_CMD_CHAIN_MASK)
3840#define APBH_CH7_CMD_IRQONCMPLT_MASK (0x8U)
3841#define APBH_CH7_CMD_IRQONCMPLT_SHIFT (3U)
3842#define APBH_CH7_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH7_CMD_IRQONCMPLT_SHIFT)) & APBH_CH7_CMD_IRQONCMPLT_MASK)
3843#define APBH_CH7_CMD_NANDLOCK_MASK (0x10U)