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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QM6/drivers/fsl_clock.h517
1 files changed, 517 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QM6/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QM6/drivers/fsl_clock.h
new file mode 100644
index 000000000..a49264442
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QM6/drivers/fsl_clock.h
@@ -0,0 +1,517 @@
1/*
2 * Copyright 2017-2020 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef _FSL_CLOCK_H_
8#define _FSL_CLOCK_H_
9
10#include "fsl_device_registers.h"
11#include <stdint.h>
12#include <stdbool.h>
13#include <assert.h>
14
15#include "svc/pm/pm_api.h"
16
17/*! @addtogroup clock */
18/*! @{ */
19
20/*******************************************************************************
21 * Definitions
22 ******************************************************************************/
23/*! @brief Configure whether driver controls clock
24 *
25 * When set to 0, peripheral drivers will enable clock in initialize function
26 * and disable clock in de-initialize function. When set to 1, peripheral
27 * driver will not control the clock, application could control the clock out of
28 * the driver.
29 *
30 * @note All drivers share this feature switcher. If it is set to 1, application
31 * should handle clock enable and disable for all drivers.
32 */
33#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
34#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
35#endif
36
37/*! @name Driver version */
38/*@{*/
39/*! @brief CLOCK driver version 2.4.0. */
40#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
41/*@}*/
42
43/* Definition for delay API in clock driver, users can redefine it to the real application. */
44#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
45#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (400000000UL)
46#endif
47
48/*! @brief Clock ip name array for MU. */
49#define MU_CLOCKS \
50 { \
51 kCLOCK_M4_0_Mu0B, kCLOCK_M4_0_Mu0B, kCLOCK_M4_0_Mu0B, kCLOCK_M4_0_Mu0B, kCLOCK_M4_0_Mu0A0, kCLOCK_M4_0_Mu0A1, \
52 kCLOCK_M4_0_Mu0A2, kCLOCK_M4_0_Mu0A3, kCLOCK_M4_0_Mu1A, kCLOCK_M4_1_Mu0B, kCLOCK_M4_1_Mu0B, \
53 kCLOCK_M4_1_Mu0B, kCLOCK_M4_1_Mu0B, kCLOCK_M4_1_Mu0A0, kCLOCK_M4_1_Mu0A1, kCLOCK_M4_1_Mu0A2, \
54 kCLOCK_M4_1_Mu0A3, kCLOCK_M4_1_Mu1A, kCLOCK_LSIO_Mu0A, kCLOCK_LSIO_Mu1A, kCLOCK_LSIO_Mu2A, \
55 kCLOCK_LSIO_Mu3A, kCLOCK_LSIO_Mu4A, kCLOCK_LSIO_Mu5A, kCLOCK_LSIO_Mu6A, kCLOCK_LSIO_Mu7A, \
56 kCLOCK_LSIO_Mu8A, kCLOCK_LSIO_Mu9A, kCLOCK_LSIO_Mu10A, kCLOCK_LSIO_Mu11A, kCLOCK_LSIO_Mu12A, \
57 kCLOCK_LSIO_Mu13A, kCLOCK_LSIO_Mu5B, kCLOCK_LSIO_Mu6B, kCLOCK_LSIO_Mu7B, kCLOCK_LSIO_Mu8B, \
58 kCLOCK_LSIO_Mu9B, kCLOCK_LSIO_Mu10B, kCLOCK_LSIO_Mu11B, kCLOCK_LSIO_Mu12B, kCLOCK_LSIO_Mu13B, \
59 }
60
61/*! @brief Clock ip name array for GPIO. */
62#define GPIO_CLOCKS \
63 { \
64 kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_HSIO_Gpio, \
65 kCLOCK_LSIO_Gpio0, kCLOCK_LSIO_Gpio1, kCLOCK_LSIO_Gpio2, kCLOCK_LSIO_Gpio3, kCLOCK_LSIO_Gpio4, \
66 kCLOCK_LSIO_Gpio5, kCLOCK_LSIO_Gpio6, kCLOCK_LSIO_Gpio7, kCLOCK_IpInvalid, kCLOCK_IpInvalid, \
67 kCLOCK_IpInvalid, \
68 }
69
70/*! @brief Clock ip name array for RGPIO. */
71#define RGPIO_CLOCKS \
72 { \
73 kCLOCK_M4_0_Rgpio, kCLOCK_M4_1_Rgpio, \
74 }
75
76/*! @brief Clock ip name array for FTM. */
77#define FTM_CLOCKS \
78 { \
79 kCLOCK_DMA_Ftm0, kCLOCK_DMA_Ftm1, \
80 }
81
82/*! @brief Clock ip name array for GPT. */
83#define GPT_CLOCKS \
84 { \
85 kCLOCK_AUDIO_Gpt0, kCLOCK_AUDIO_Gpt1, kCLOCK_AUDIO_Gpt2, kCLOCK_AUDIO_Gpt3, kCLOCK_AUDIO_Gpt4, \
86 kCLOCK_AUDIO_Gpt5, kCLOCK_LSIO_Gpt0, kCLOCK_LSIO_Gpt1, kCLOCK_LSIO_Gpt2, kCLOCK_LSIO_Gpt3, \
87 kCLOCK_LSIO_Gpt4, \
88 }
89/*! @brief Clock ip name array for FLEXCAN. */
90#define FLEXCAN_CLOCKS \
91 { \
92 kCLOCK_DMA_Can0, kCLOCK_DMA_Can1, kCLOCK_DMA_Can2, \
93 }
94/*! @brief Clock ip name array for FLEXSPI. */
95#define FLEXSPI_CLOCKS \
96 { \
97 kCLOCK_LSIO_Flexspi0, kCLOCK_LSIO_Flexspi1, \
98 }
99/*! @brief Clock ip name array for LPUART. */
100#define LPUART_CLOCKS \
101 { \
102 kCLOCK_M4_0_Lpuart, kCLOCK_M4_1_Lpuart, kCLOCK_DMA_Lpuart0, kCLOCK_DMA_Lpuart1, kCLOCK_DMA_Lpuart2, \
103 kCLOCK_DMA_Lpuart3, kCLOCK_DMA_Lpuart4, kCLOCK_SCU_Lpuart, \
104 }
105
106/*! @brief Clock ip name array for LPADC. */
107#define LPADC_CLOCKS \
108 { \
109 kCLOCK_DMA_Lpadc0, kCLOCK_DMA_Lpadc1, \
110 }
111
112/*! @brief Clock ip name array for INTMUX. */
113#define INTMUX_CLOCKS \
114 { \
115 kCLOCK_M4_0_Intmux, kCLOCK_M4_1_Intmux, kCLOCK_IpInvalid, \
116 }
117
118/*! @brief Clock ip name array for SAI. */
119#define SAI_CLOCKS \
120 { \
121 kCLOCK_AUDIO_Sai0, kCLOCK_AUDIO_Sai1, kCLOCK_AUDIO_Sai2, kCLOCK_AUDIO_Sai3, kCLOCK_AUDIO_Sai4, \
122 kCLOCK_AUDIO_Sai5, kCLOCK_AUDIO_Sai6, kCLOCK_AUDIO_Sai7, \
123 }
124
125/*! @brief Clock ip name array for SEMA42. */
126#define SEMA42_CLOCKS \
127 { \
128 kCLOCK_M4_0_Sema42, kCLOCK_M4_1_Sema42, kCLOCK_SCU_Sema42, \
129 }
130
131/*! @brief Clock ip name array for TPM. */
132#define TPM_CLOCKS \
133 { \
134 kCLOCK_M4_0_Tpm, kCLOCK_M4_1_Tpm, kCLOCK_SCU_Tpm, \
135 }
136
137/*! @brief Clock ip name array for LPIT. */
138#define LPIT_CLOCKS \
139 { \
140 kCLOCK_M4_0_Lpit, kCLOCK_M4_1_Lpit, kCLOCK_SCU_Lpit, \
141 }
142
143/*! @brief Clock ip name array for LPI2C. */
144#define LPI2C_CLOCKS \
145 { \
146 kCLOCK_M4_0_Lpi2c, kCLOCK_M4_1_Lpi2c, kCLOCK_HDMI_Lpi2c0, kCLOCK_LVDS_0_Lpi2c1, kCLOCK_LVDS_0_Lpi2c0, \
147 kCLOCK_LVDS_1_Lpi2c1, kCLOCK_LVDS_1_Lpi2c0, kCLOCK_MIPI_0_Lpi2c0, kCLOCK_MIPI_0_Lpi2c1, \
148 kCLOCK_MIPI_1_Lpi2c0, kCLOCK_MIPI_1_Lpi2c1, kCLOCK_DMA_Lpi2c0, kCLOCK_DMA_Lpi2c1, kCLOCK_DMA_Lpi2c2, \
149 kCLOCK_DMA_Lpi2c3, kCLOCK_DMA_Lpi2c4, kCLOCK_CSI_0_Lpi2c0, kCLOCK_CSI_1_Lpi2c0, kCLOCK_HDMI_RX_Lpi2c0, \
150 kCLOCK_SCU_Lpi2c, \
151 }
152
153/*! @brief Clock ip name array for LPSPI. */
154#define LPSPI_CLOCKS \
155 { \
156 kCLOCK_DMA_Lpspi0, kCLOCK_DMA_Lpspi1, kCLOCK_DMA_Lpspi2, kCLOCK_DMA_Lpspi3, \
157 }
158#if defined(MIMX8QM_CM4_CORE0)
159#define IRQSTEER_CLOCKS \
160 { \
161 kCLOCK_M4_0_Irqsteer, \
162 }
163#elif defined(MIMX8QM_CM4_CORE1)
164#define IRQSTEER_CLOCKS \
165 { \
166 kCLOCK_M4_1_Irqsteer, \
167 }
168#endif
169
170/*! @brief Clock ip name array for EDMA. */
171#define EDMA_CLOCKS \
172 { \
173 kCLOCK_DMA_Dma0, \
174 }
175
176/*! @brief Clock ip name array for ESAI. */
177#define ESAI_CLOCKS \
178 { \
179 kCLOCK_AUDIO_Esai0, kCLOCK_AUDIO_Esai1 \
180 }
181
182/*! @brief Clock ip name array for ISI. */
183#define ISI_CLOCKS \
184 { \
185 kCLOCK_IMAGING_Isi0, kCLOCK_IMAGING_Isi1, kCLOCK_IMAGING_Isi2, kCLOCK_IMAGING_Isi3, kCLOCK_IMAGING_Isi4, \
186 kCLOCK_IMAGING_Isi5, kCLOCK_IMAGING_Isi6, kCLOCK_IMAGING_Isi7, \
187 }
188
189/*! @brief Clock ip name array for MIPI CSI2 RX. */
190#define MIPI_CSI2RX_CLOCKS \
191 { \
192 kCLOCK_MipiCsi2Rx0, kCLOCK_MipiCsi2Rx1 \
193 }
194
195/*! @brief Clock ip name array for MIPI DSI host. */
196#define MIPI_DSI_HOST_CLOCKS \
197 { \
198 kCLOCK_MipiDsiHost0, kCLOCK_MipiDsiHost1 \
199 }
200
201/*! @brief Clock ip name array for ENET. */
202#define ENET_CLOCKS \
203 { \
204 kCLOCK_CONNECTIVITY_Enet0, kCLOCK_CONNECTIVITY_Enet1 \
205 }
206
207/*! @brief Clock ip name array for EMVSIM. */
208#define EMVSIM_CLOCKS \
209 { \
210 kCLOCK_DMA_EmvSim0, kCLOCK_DMA_EmvSim1, \
211 }
212
213/*! @brief Clock ip name array for DPU. */
214#define DPU_CLOCKS \
215 { \
216 kCLOCK_Dpu0, kCLOCK_Dpu1, \
217 }
218
219/*! @brief Clock ip name array for LVDS display bridge(LDB). */
220#define LDB_CLOCKS \
221 { \
222 kCLOCK_Ldb0, kCLOCK_Ldb1 \
223 }
224
225/*!
226 * @brief Clock source for peripherals that support various clock selections.
227 */
228typedef enum _clock_ip_src
229{
230 kCLOCK_IpSrcNone = 0U, /*!< Clock is off. */
231 kCLOCK_IpSrcDummy = 1U, /*!< Clock option 1. */
232} clock_ip_src_t;
233
234/*! @brief Clock name used to get clock frequency. */
235typedef enum _clock_name
236{
237 /* ----------------------------- System layer clock ---------------------- */
238 kCLOCK_CoreSysClk, /*!< Core/system clock for M4 */
239
240 /* --------------------------------- Other clock ------------------------- */
241 kCLOCK_CONECTIVITY_AhbClk, /*!< AHB clock in Connectivity subsystem */
242} clock_name_t;
243
244/*!
245 * @brief LPCG TUPLE macors to map corresponding ip clock name, SCFW API resource index and LPCG Register base address.
246 * The LPCG base should be 4KB aligned, if not it will be truncated.
247 */
248#define LPCG_TUPLE(rsrc, base) ((uint32_t)((((base) >> 12U) << 10U) | (rsrc)))
249/*! @brief Get the LPCG REG base address. */
250#define LPCG_TUPLE_REG_BASE(tuple) ((volatile uint32_t *)((((uint32_t)(tuple) >> 10U) & 0xFFFFFU) << 12U))
251/*! @brief Get the resource index. */
252#define LPCG_TUPLE_RSRC(tuple) ((sc_rsrc_t)((uint32_t)(tuple)&0x3FFU))
253/*! @brief LPCG Cell not available. */
254#define NV (0U)
255
256/*!
257 * @brief Peripheral clock name difinition used for clock gate, clock source
258 * and clock divider setting. It is defined as the corresponding register address.
259 */
260typedef enum _clock_ip_name
261{
262 kCLOCK_M4_0_Irqsteer = LPCG_TUPLE(SC_R_IRQSTR_M4_0, NV),
263 kCLOCK_M4_1_Irqsteer = LPCG_TUPLE(SC_R_IRQSTR_M4_1, NV),
264 kCLOCK_DMA_Lpspi0 = LPCG_TUPLE(SC_R_SPI_0, DMA__LPCG_LPSPI0_BASE),
265 kCLOCK_DMA_Lpspi1 = LPCG_TUPLE(SC_R_SPI_1, DMA__LPCG_LPSPI1_BASE),
266 kCLOCK_DMA_Lpspi2 = LPCG_TUPLE(SC_R_SPI_2, DMA__LPCG_LPSPI2_BASE),
267 kCLOCK_DMA_Lpspi3 = LPCG_TUPLE(SC_R_SPI_3, DMA__LPCG_LPSPI3_BASE),
268 kCLOCK_DMA_Lpuart0 = LPCG_TUPLE(SC_R_UART_0, DMA__LPCG_LPUART0_BASE),
269 kCLOCK_DMA_Lpuart1 = LPCG_TUPLE(SC_R_UART_1, DMA__LPCG_LPUART1_BASE),
270 kCLOCK_DMA_Lpuart2 = LPCG_TUPLE(SC_R_UART_2, DMA__LPCG_LPUART2_BASE),
271 kCLOCK_DMA_Lpuart3 = LPCG_TUPLE(SC_R_UART_3, DMA__LPCG_LPUART3_BASE),
272 kCLOCK_DMA_Lpuart4 = LPCG_TUPLE(SC_R_UART_4, DMA__LPCG_LPUART4_BASE),
273 kCLOCK_DMA_EmvSim0 = LPCG_TUPLE(SC_R_EMVSIM_0, DMA__LPCG_EMV_SIM0_BASE),
274 kCLOCK_DMA_EmvSim1 = LPCG_TUPLE(SC_R_EMVSIM_1, DMA__LPCG_EMV_SIM1_BASE),
275 kCLOCK_DMA_Dma0 = LPCG_TUPLE(SC_R_DMA_0_CH0, NV),
276 kCLOCK_DMA_Lpi2c0 = LPCG_TUPLE(SC_R_I2C_0, DMA__LPCG_LPI2C0_BASE),
277 kCLOCK_DMA_Lpi2c1 = LPCG_TUPLE(SC_R_I2C_1, DMA__LPCG_LPI2C1_BASE),
278 kCLOCK_DMA_Lpi2c2 = LPCG_TUPLE(SC_R_I2C_2, DMA__LPCG_LPI2C2_BASE),
279 kCLOCK_DMA_Lpi2c3 = LPCG_TUPLE(SC_R_I2C_3, DMA__LPCG_LPI2C3_BASE),
280 kCLOCK_DMA_Lpi2c4 = LPCG_TUPLE(SC_R_I2C_4, DMA__LPCG_LPI2C4_BASE),
281 kCLOCK_DMA_Lpadc0 = LPCG_TUPLE(SC_R_ADC_0, DMA__LPCG_ADC0_BASE),
282 kCLOCK_DMA_Lpadc1 = LPCG_TUPLE(SC_R_ADC_1, DMA__LPCG_ADC1_BASE),
283 kCLOCK_DMA_Ftm0 = LPCG_TUPLE(SC_R_FTM_0, DMA__LPCG_FTM0_BASE),
284 kCLOCK_DMA_Ftm1 = LPCG_TUPLE(SC_R_FTM_1, DMA__LPCG_FTM1_BASE),
285 kCLOCK_DMA_Can0 = LPCG_TUPLE(SC_R_CAN_0, DMA__LPCG_CAN0_BASE),
286 kCLOCK_DMA_Can1 = LPCG_TUPLE(SC_R_CAN_1, DMA__LPCG_CAN1_BASE),
287 kCLOCK_DMA_Can2 = LPCG_TUPLE(SC_R_CAN_2, DMA__LPCG_CAN2_BASE),
288 kCLOCK_HSIO_Gpio = LPCG_TUPLE(SC_R_HSIO_GPIO, HSIO__LPCG_GPIO_BASE),
289 kCLOCK_LVDS_0_Lpi2c0 = LPCG_TUPLE(SC_R_LVDS_0_I2C_0, DI_LVDS_0__LPCG_CLK_BASE),
290 kCLOCK_LVDS_0_Lpi2c1 = LPCG_TUPLE(SC_R_LVDS_0_I2C_1, DI_LVDS_0__LPCG_CLK_BASE),
291 kCLOCK_LVDS_1_Lpi2c0 = LPCG_TUPLE(SC_R_LVDS_1_I2C_0, DI_LVDS_1__LPCG_CLK_BASE),
292 kCLOCK_LVDS_1_Lpi2c1 = LPCG_TUPLE(SC_R_LVDS_1_I2C_1, DI_LVDS_1__LPCG_CLK_BASE),
293 kCLOCK_LSIO_Gpio0 = LPCG_TUPLE(SC_R_GPIO_0, LSIO__LPCG_GPIO0_BASE),
294 kCLOCK_LSIO_Gpio1 = LPCG_TUPLE(SC_R_GPIO_1, LSIO__LPCG_GPIO1_BASE),
295 kCLOCK_LSIO_Gpio2 = LPCG_TUPLE(SC_R_GPIO_2, LSIO__LPCG_GPIO2_BASE),
296 kCLOCK_LSIO_Gpio3 = LPCG_TUPLE(SC_R_GPIO_3, LSIO__LPCG_GPIO3_BASE),
297 kCLOCK_LSIO_Gpio4 = LPCG_TUPLE(SC_R_GPIO_4, LSIO__LPCG_GPIO4_BASE),
298 kCLOCK_LSIO_Gpio5 = LPCG_TUPLE(SC_R_GPIO_5, LSIO__LPCG_GPIO5_BASE),
299 kCLOCK_LSIO_Gpio6 = LPCG_TUPLE(SC_R_GPIO_6, LSIO__LPCG_GPIO6_BASE),
300 kCLOCK_LSIO_Gpio7 = LPCG_TUPLE(SC_R_GPIO_7, LSIO__LPCG_GPIO7_BASE),
301 kCLOCK_AUDIO_Gpt0 = LPCG_TUPLE(SC_R_GPT_5, AUDIO__LPCG_GPT0_BASE),
302 kCLOCK_AUDIO_Gpt1 = LPCG_TUPLE(SC_R_GPT_6, AUDIO__LPCG_GPT1_BASE),
303 kCLOCK_AUDIO_Gpt2 = LPCG_TUPLE(SC_R_GPT_7, AUDIO__LPCG_GPT2_BASE),
304 kCLOCK_AUDIO_Gpt3 = LPCG_TUPLE(SC_R_GPT_8, AUDIO__LPCG_GPT3_BASE),
305 kCLOCK_AUDIO_Gpt4 = LPCG_TUPLE(SC_R_GPT_9, AUDIO__LPCG_GPT4_BASE),
306 kCLOCK_AUDIO_Gpt5 = LPCG_TUPLE(SC_R_GPT_10, AUDIO__LPCG_GPT5_BASE),
307 kCLOCK_LSIO_Gpt0 = LPCG_TUPLE(SC_R_GPT_0, LSIO__LPCG_GPT0_BASE),
308 kCLOCK_LSIO_Gpt1 = LPCG_TUPLE(SC_R_GPT_1, LSIO__LPCG_GPT1_BASE),
309 kCLOCK_LSIO_Gpt2 = LPCG_TUPLE(SC_R_GPT_2, LSIO__LPCG_GPT2_BASE),
310 kCLOCK_LSIO_Gpt3 = LPCG_TUPLE(SC_R_GPT_3, LSIO__LPCG_GPT3_BASE),
311 kCLOCK_LSIO_Gpt4 = LPCG_TUPLE(SC_R_GPT_4, LSIO__LPCG_GPT4_BASE),
312 kCLOCK_LSIO_Mu0A = LPCG_TUPLE(SC_R_MU_0A, NV),
313 kCLOCK_LSIO_Mu1A = LPCG_TUPLE(SC_R_MU_1A, NV),
314 kCLOCK_LSIO_Mu2A = LPCG_TUPLE(SC_R_MU_2A, NV),
315 kCLOCK_LSIO_Mu3A = LPCG_TUPLE(SC_R_MU_3A, NV),
316 kCLOCK_LSIO_Mu4A = LPCG_TUPLE(SC_R_MU_4A, NV),
317 kCLOCK_LSIO_Mu5A = LPCG_TUPLE(SC_R_MU_5A, LSIO__LPCG_MU5_MCU_BASE),
318 kCLOCK_LSIO_Mu6A = LPCG_TUPLE(SC_R_MU_6A, LSIO__LPCG_MU6_MCU_BASE),
319 kCLOCK_LSIO_Mu7A = LPCG_TUPLE(SC_R_MU_7A, LSIO__LPCG_MU7_MCU_BASE),
320 kCLOCK_LSIO_Mu8A = LPCG_TUPLE(SC_R_MU_8A, LSIO__LPCG_MU8_MCU_BASE),
321 kCLOCK_LSIO_Mu9A = LPCG_TUPLE(SC_R_MU_9A, LSIO__LPCG_MU9_MCU_BASE),
322 kCLOCK_LSIO_Mu10A = LPCG_TUPLE(SC_R_MU_10A, LSIO__LPCG_MU10_MCU_BASE),
323 kCLOCK_LSIO_Mu11A = LPCG_TUPLE(SC_R_MU_11A, LSIO__LPCG_MU11_MCU_BASE),
324 kCLOCK_LSIO_Mu12A = LPCG_TUPLE(SC_R_MU_12A, LSIO__LPCG_MU12_MCU_BASE),
325 kCLOCK_LSIO_Mu13A = LPCG_TUPLE(SC_R_MU_13A, LSIO__LPCG_MU13_MCU_BASE),
326 kCLOCK_LSIO_Mu5B = LPCG_TUPLE(SC_R_MU_5B, LSIO__LPCG_MU5_DSP_BASE),
327 kCLOCK_LSIO_Mu6B = LPCG_TUPLE(SC_R_MU_6B, LSIO__LPCG_MU6_DSP_BASE),
328 kCLOCK_LSIO_Mu7B = LPCG_TUPLE(SC_R_MU_7B, LSIO__LPCG_MU7_DSP_BASE),
329 kCLOCK_LSIO_Mu8B = LPCG_TUPLE(SC_R_MU_8B, LSIO__LPCG_MU8_DSP_BASE),
330 kCLOCK_LSIO_Mu9B = LPCG_TUPLE(SC_R_MU_9B, LSIO__LPCG_MU9_DSP_BASE),
331 kCLOCK_LSIO_Mu10B = LPCG_TUPLE(SC_R_MU_10B, LSIO__LPCG_MU10_DSP_BASE),
332 kCLOCK_LSIO_Mu11B = LPCG_TUPLE(SC_R_MU_11B, LSIO__LPCG_MU11_DSP_BASE),
333 kCLOCK_LSIO_Mu12B = LPCG_TUPLE(SC_R_MU_12B, LSIO__LPCG_MU12_DSP_BASE),
334 kCLOCK_LSIO_Mu13B = LPCG_TUPLE(SC_R_MU_13B, LSIO__LPCG_MU13_DSP_BASE),
335 kCLOCK_LSIO_Flexspi0 = LPCG_TUPLE(SC_R_FSPI_0, LSIO__LPCG_QSPI0_BASE),
336 kCLOCK_LSIO_Flexspi1 = LPCG_TUPLE(SC_R_FSPI_1, LSIO__LPCG_QSPI1_BASE),
337 kCLOCK_M4_0_Rgpio = LPCG_TUPLE(SC_R_M4_0_RGPIO, NV),
338 kCLOCK_M4_0_Sema42 = LPCG_TUPLE(SC_R_M4_0_SEMA42, NV),
339 kCLOCK_M4_0_Tpm = LPCG_TUPLE(SC_R_M4_0_TPM, CM4_0__LPCG_TPM_BASE),
340 kCLOCK_M4_0_Lpit = LPCG_TUPLE(SC_R_M4_0_PIT, CM4_0__LPCG_LPIT_BASE),
341 kCLOCK_M4_0_Lpuart = LPCG_TUPLE(SC_R_M4_0_UART, CM4_0__LPCG_LPUART_BASE),
342 kCLOCK_M4_0_Lpi2c = LPCG_TUPLE(SC_R_M4_0_I2C, CM4_0__LPCG_LPI2C_BASE),
343 kCLOCK_M4_0_Intmux = LPCG_TUPLE(SC_R_M4_0_INTMUX, NV),
344 kCLOCK_M4_0_Mu0B = LPCG_TUPLE(SC_R_M4_0_MU_0B, NV),
345 kCLOCK_M4_0_Mu0A0 = LPCG_TUPLE(SC_R_M4_0_MU_0A0, NV),
346 kCLOCK_M4_0_Mu0A1 = LPCG_TUPLE(SC_R_M4_0_MU_0A1, NV),
347 kCLOCK_M4_0_Mu0A2 = LPCG_TUPLE(SC_R_M4_0_MU_0A2, NV),
348 kCLOCK_M4_0_Mu0A3 = LPCG_TUPLE(SC_R_M4_0_MU_0A3, NV),
349 kCLOCK_M4_0_Mu1A = LPCG_TUPLE(SC_R_M4_0_MU_1A, NV),
350 kCLOCK_M4_1_Rgpio = LPCG_TUPLE(SC_R_M4_1_RGPIO, NV),
351 kCLOCK_M4_1_Sema42 = LPCG_TUPLE(SC_R_M4_1_SEMA42, NV),
352 kCLOCK_M4_1_Tpm = LPCG_TUPLE(SC_R_M4_1_TPM, CM4_1__LPCG_TPM_BASE),
353 kCLOCK_M4_1_Lpit = LPCG_TUPLE(SC_R_M4_1_PIT, CM4_1__LPCG_LPIT_BASE),
354 kCLOCK_M4_1_Lpuart = LPCG_TUPLE(SC_R_M4_1_UART, CM4_1__LPCG_LPUART_BASE),
355 kCLOCK_SCU_Lpuart = LPCG_TUPLE(SC_R_SC_UART, SCU__LPCG_LPUART_BASE),
356 kCLOCK_M4_1_Lpi2c = LPCG_TUPLE(SC_R_M4_1_I2C, CM4_1__LPCG_LPI2C_BASE),
357 kCLOCK_M4_1_Intmux = LPCG_TUPLE(SC_R_M4_1_INTMUX, NV),
358 kCLOCK_M4_1_Mu0B = LPCG_TUPLE(SC_R_M4_1_MU_0B, NV),
359 kCLOCK_M4_1_Mu0A0 = LPCG_TUPLE(SC_R_M4_1_MU_0A0, NV),
360 kCLOCK_M4_1_Mu0A1 = LPCG_TUPLE(SC_R_M4_1_MU_0A1, NV),
361 kCLOCK_M4_1_Mu0A2 = LPCG_TUPLE(SC_R_M4_1_MU_0A2, NV),
362 kCLOCK_M4_1_Mu0A3 = LPCG_TUPLE(SC_R_M4_1_MU_0A3, NV),
363 kCLOCK_M4_1_Mu1A = LPCG_TUPLE(SC_R_M4_1_MU_1A, NV),
364 kCLOCK_SCU_Lpi2c = LPCG_TUPLE(SC_R_SC_I2C, SCU__LPCG_LPI2C_BASE),
365 kCLOCK_SCU_Sema42 = LPCG_TUPLE(SC_R_SC_SEMA42, NV),
366 kCLOCK_SCU_Lpit = LPCG_TUPLE(SC_R_SC_PIT, SCU__LPCG_LPIT_BASE),
367 kCLOCK_SCU_Tpm = LPCG_TUPLE(SC_R_SC_TPM, SCU__LPCG_TPM_BASE),
368 kCLOCK_AUDIO_Sai0 = LPCG_TUPLE(SC_R_SAI_0, AUDIO__LPCG_SAI0_BASE),
369 kCLOCK_AUDIO_Sai1 = LPCG_TUPLE(SC_R_SAI_1, AUDIO__LPCG_SAI1_BASE),
370 kCLOCK_AUDIO_Sai2 = LPCG_TUPLE(SC_R_SAI_2, AUDIO__LPCG_SAI2_BASE),
371 kCLOCK_AUDIO_Sai3 = LPCG_TUPLE(SC_R_SAI_3, AUDIO__LPCG_SAI3_BASE),
372 kCLOCK_AUDIO_Sai4 = LPCG_TUPLE(SC_R_SAI_4, AUDIO__LPCG_SAI_HDMIRX0_BASE),
373 kCLOCK_AUDIO_Sai5 = LPCG_TUPLE(SC_R_SAI_5, AUDIO__LPCG_SAI_HDMITX0_BASE),
374 kCLOCK_AUDIO_Sai6 = LPCG_TUPLE(SC_R_SAI_6, AUDIO__LPCG_SAI6_BASE),
375 kCLOCK_AUDIO_Sai7 = LPCG_TUPLE(SC_R_SAI_7, AUDIO__LPCG_SAI7_BASE),
376 kCLOCK_AUDIO_Esai0 = LPCG_TUPLE(SC_R_ESAI_0, AUDIO__LPCG_ESAI0_BASE),
377 kCLOCK_AUDIO_Esai1 = LPCG_TUPLE(SC_R_ESAI_1, AUDIO__LPCG_ESAI1_BASE),
378 kCLOCK_IMAGING_Isi0 = LPCG_TUPLE(SC_R_ISI_CH0, NV),
379 kCLOCK_IMAGING_Isi1 = LPCG_TUPLE(SC_R_ISI_CH1, NV),
380 kCLOCK_IMAGING_Isi2 = LPCG_TUPLE(SC_R_ISI_CH2, NV),
381 kCLOCK_IMAGING_Isi3 = LPCG_TUPLE(SC_R_ISI_CH3, NV),
382 kCLOCK_IMAGING_Isi4 = LPCG_TUPLE(SC_R_ISI_CH4, NV),
383 kCLOCK_IMAGING_Isi5 = LPCG_TUPLE(SC_R_ISI_CH5, NV),
384 kCLOCK_IMAGING_Isi6 = LPCG_TUPLE(SC_R_ISI_CH6, NV),
385 kCLOCK_IMAGING_Isi7 = LPCG_TUPLE(SC_R_ISI_CH7, NV),
386 kCLOCK_MIPI_0_Lpi2c0 = LPCG_TUPLE(SC_R_MIPI_0_I2C_0, DI_MIPI_0__LPCG_CLK_BASE),
387 kCLOCK_MIPI_0_Lpi2c1 = LPCG_TUPLE(SC_R_MIPI_0_I2C_1, DI_MIPI_0__LPCG_CLK_BASE),
388 kCLOCK_MIPI_1_Lpi2c0 = LPCG_TUPLE(SC_R_MIPI_1_I2C_0, DI_MIPI_1__LPCG_CLK_BASE),
389 kCLOCK_MIPI_1_Lpi2c1 = LPCG_TUPLE(SC_R_MIPI_1_I2C_1, DI_MIPI_1__LPCG_CLK_BASE),
390 kCLOCK_CSI_0_Lpi2c0 = LPCG_TUPLE(SC_R_CSI_0_I2C_0, MIPI_CSI_0__LPCG_CLK_BASE),
391 kCLOCK_CSI_1_Lpi2c0 = LPCG_TUPLE(SC_R_CSI_1_I2C_0, MIPI_CSI_1__LPCG_CLK_BASE),
392 kCLOCK_Dpu0 = LPCG_TUPLE(SC_R_DC_0, DC_0__LPCG_DSP0_CLK_BASE),
393 kCLOCK_Dpu1 = LPCG_TUPLE(SC_R_DC_1, DC_1__LPCG_DSP0_CLK_BASE),
394 kCLOCK_HDMI_Lpi2c0 = LPCG_TUPLE(SC_R_HDMI_I2C_0, DI_HDMI__LPCG_CLK_BASE),
395 kCLOCK_HDMI_RX_Lpi2c0 = LPCG_TUPLE(SC_R_HDMI_RX_I2C_0, RX_HDMI__LPCG_GPIO_IPG_CLK_S_BASE),
396 kCLOCK_MipiCsi2Rx0 = LPCG_TUPLE(SC_R_CSI_0, MIPI_CSI_0__LPCG_CLK_BASE),
397 kCLOCK_MipiCsi2Rx1 = LPCG_TUPLE(SC_R_CSI_1, MIPI_CSI_1__LPCG_CLK_BASE),
398 kCLOCK_MipiDsiHost0 = LPCG_TUPLE(SC_R_MIPI_0, DI_MIPI_0__LPCG_CLK_BASE),
399 kCLOCK_MipiDsiHost1 = LPCG_TUPLE(SC_R_MIPI_1, DI_MIPI_1__LPCG_CLK_BASE),
400 kCLOCK_Ldb0 = LPCG_TUPLE(SC_R_LVDS_0, NV),
401 kCLOCK_Ldb1 = LPCG_TUPLE(SC_R_LVDS_1, NV),
402 kCLOCK_CONNECTIVITY_Enet0 = LPCG_TUPLE(SC_R_ENET_0, CONNECTIVITY__LPCG_ENET0_BASE),
403 kCLOCK_CONNECTIVITY_Enet1 = LPCG_TUPLE(SC_R_ENET_1, CONNECTIVITY__LPCG_ENET1_BASE),
404 kCLOCK_AUDIO_Pll0 = LPCG_TUPLE(SC_R_AUDIO_PLL_0, NV),
405 kCLOCK_AUDIO_Pll1 = LPCG_TUPLE(SC_R_AUDIO_PLL_1, NV),
406 kCLOCK_IpInvalid = LPCG_TUPLE(SC_R_LAST, NV) /* The selected IP does not support clock control. */
407} clock_ip_name_t;
408
409#if defined(__cplusplus)
410extern "C" {
411#endif /* _cplusplus */
412
413/*!
414 * @brief Initialize Clock module.
415 *
416 * @param ipc IPC handle for communication with SCU, see sc_ipc_t.
417 */
418void CLOCK_Init(sc_ipc_t ipc);
419
420/*!
421 * @brief Deinitialize Clock module.
422 */
423void CLOCK_Deinit(void);
424
425/*!
426 * @brief Enable the clock for specific IP, with gate setting.
427 *
428 * @param name Which clock to enable, see \ref clock_ip_name_t.
429 * @param gate 0: clock always on, 1: HW auto clock gating.
430 * @return true if success, false if failure.
431 */
432bool CLOCK_EnableClockExt(clock_ip_name_t name, uint32_t gate);
433
434/*!
435 * @brief Enable the clock for specific IP.
436 *
437 * @param name Which clock to enable, see \ref clock_ip_name_t.
438 * @return true for success, false for failure.
439 */
440static inline bool CLOCK_EnableClock(clock_ip_name_t name)
441{
442 return CLOCK_EnableClockExt(name, 0);
443}
444
445/*!
446 * @brief Disable the clock for specific IP.
447 *
448 * @param name Which clock to disable, see \ref clock_ip_name_t.
449 * @return true for success, false for failure.
450 */
451bool CLOCK_DisableClock(clock_ip_name_t name);
452
453/*!
454 * @brief Set the clock frequency for specific IP module.
455 *
456 * This function sets the IP module clock frequency.
457 *
458 * @param name Which peripheral to check, see \ref clock_ip_name_t.
459 * @param freq Target clock frequency value in hertz.
460 * @return the Real clock frequency value in hertz, or 0 if failed
461 */
462uint32_t CLOCK_SetIpFreq(clock_ip_name_t name, uint32_t freq);
463
464/*!
465 * @brief Get the clock frequency for a specific IP module.
466 *
467 * This function gets the IP module clock frequency.
468 *
469 * @param name Which peripheral to get, see \ref clock_ip_name_t.
470 * @return Clock frequency value in hertz, or 0 if failed
471 */
472uint32_t CLOCK_GetIpFreq(clock_ip_name_t name);
473
474/*!
475 * @brief Gets the clock frequency for a specific clock name.
476 *
477 * This function checks the current clock configurations and then calculates
478 * the clock frequency for a specific clock name defined in clock_name_t.
479 *
480 * @param name Clock names defined in clock_name_t
481 * @return Clock frequency value in hertz
482 */
483uint32_t CLOCK_GetFreq(clock_name_t name);
484
485/*!
486 * @brief Get the core clock or system clock frequency.
487 *
488 * @return Clock frequency in Hz.
489 */
490uint32_t CLOCK_GetCoreSysClkFreq(void);
491
492/*!
493 * @brief Config the LPCG cell for specific IP.
494 *
495 * @param name Which clock to enable, see \ref clock_ip_name_t.
496 * @param swGate Software clock gating. false: clock is gated; true: clock is enabled
497 * @param hwGate Hardware auto gating. false: disable the HW clock gate control; true: HW clock gating is enabled
498 */
499void CLOCK_ConfigLPCG(clock_ip_name_t name, bool swGate, bool hwGate);
500
501/*!
502 * @brief Set LPCG gate for specific LPCG.
503 *
504 * @param regBase LPCG register base address.
505 * @param swGate Software clock gating. false: clock is gated; true: clock is enabled
506 * @param hwGate Hardware auto gating. false: disable the HW clock gate control; true: HW clock gating is enabled
507 * @param bitsMask The available bits in LPCG register. Each bit indicate the corresponding bit is available or not.
508 */
509void CLOCK_SetLpcgGate(volatile uint32_t *regBase, bool swGate, bool hwGate, uint32_t bitsMask);
510
511#if defined(__cplusplus)
512}
513#endif /* __cplusplus */
514
515/*! @} */
516
517#endif /* _FSL_CLOCK_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 21:13:12 +0100