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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/imx8qx_pads.h225
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/ipc.h92
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/ipc_imx8qx.c159
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/rpc.h175
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/scfw.h60
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/types.h918
6 files changed, 1629 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/imx8qx_pads.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/imx8qx_pads.h
new file mode 100644
index 000000000..6316694ff
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/imx8qx_pads.h
@@ -0,0 +1,225 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2017-2019 NXP
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without modification,
8 * are permitted provided that the following conditions are met:
9 *
10 * o Redistributions of source code must retain the above copyright notice, this list
11 * of conditions and the following disclaimer.
12 *
13 * o Redistributions in binary form must reproduce the above copyright notice, this
14 * list of conditions and the following disclaimer in the documentation and/or
15 * other materials provided with the distribution.
16 *
17 * o Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/*!
34 * Header file used to configure SoC pad list.
35 */
36
37#ifndef SC_PADS_H
38#define SC_PADS_H
39
40/* Includes */
41
42/* Defines */
43
44/*!
45 * @name Pad Definitions
46 */
47/*@{*/
48#define SC_P_PCIE_CTRL0_PERST_B 0 /*!< HSIO.PCIE0.PERST_B, LSIO.GPIO4.IO00 */
49#define SC_P_PCIE_CTRL0_CLKREQ_B 1 /*!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO4.IO01 */
50#define SC_P_PCIE_CTRL0_WAKE_B 2 /*!< HSIO.PCIE0.WAKE_B, LSIO.GPIO4.IO02 */
51#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 /*!< */
52#define SC_P_USB_SS3_TC0 4 /*!< ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */
53#define SC_P_USB_SS3_TC1 5 /*!< ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */
54#define SC_P_USB_SS3_TC2 6 /*!< ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 */
55#define SC_P_USB_SS3_TC3 7 /*!< ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */
56#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 /*!< */
57#define SC_P_EMMC0_CLK 9 /*!< CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */
58#define SC_P_EMMC0_CMD 10 /*!< CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */
59#define SC_P_EMMC0_DATA0 11 /*!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.GPIO4.IO09 */
60#define SC_P_EMMC0_DATA1 12 /*!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.GPIO4.IO10 */
61#define SC_P_EMMC0_DATA2 13 /*!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.GPIO4.IO11 */
62#define SC_P_EMMC0_DATA3 14 /*!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.GPIO4.IO12 */
63#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 15 /*!< */
64#define SC_P_EMMC0_DATA4 16 /*!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */
65#define SC_P_EMMC0_DATA5 17 /*!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */
66#define SC_P_EMMC0_DATA6 18 /*!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 */
67#define SC_P_EMMC0_DATA7 19 /*!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 */
68#define SC_P_EMMC0_STROBE 20 /*!< CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 */
69#define SC_P_EMMC0_RESET_B 21 /*!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */
70#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22 /*!< */
71#define SC_P_USDHC1_RESET_B 23 /*!< CONN.USDHC1.RESET_B, CONN.NAND.RE_N, ADMA.SPI2.SCK, LSIO.GPIO4.IO19 */
72#define SC_P_USDHC1_VSELECT 24 /*!< CONN.USDHC1.VSELECT, CONN.NAND.RE_P, ADMA.SPI2.SDO, CONN.NAND.RE_B, LSIO.GPIO4.IO20 */
73#define SC_P_CTL_NAND_RE_P_N 25 /*!< */
74#define SC_P_USDHC1_WP 26 /*!< CONN.USDHC1.WP, CONN.NAND.DQS_N, ADMA.SPI2.SDI, LSIO.GPIO4.IO21 */
75#define SC_P_USDHC1_CD_B 27 /*!< CONN.USDHC1.CD_B, CONN.NAND.DQS_P, ADMA.SPI2.CS0, CONN.NAND.DQS, LSIO.GPIO4.IO22 */
76#define SC_P_CTL_NAND_DQS_P_N 28 /*!< */
77#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29 /*!< */
78#define SC_P_USDHC1_CLK 30 /*!< CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */
79#define SC_P_USDHC1_CMD 31 /*!< CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */
80#define SC_P_USDHC1_DATA0 32 /*!< CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 */
81#define SC_P_USDHC1_DATA1 33 /*!< CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */
82#define SC_P_USDHC1_DATA2 34 /*!< CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART3.CTS_B, LSIO.GPIO4.IO27 */
83#define SC_P_USDHC1_DATA3 35 /*!< CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART3.RTS_B, LSIO.GPIO4.IO28 */
84#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 36 /*!< */
85#define SC_P_ENET0_RGMII_TXC 37 /*!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B, LSIO.GPIO4.IO29 */
86#define SC_P_ENET0_RGMII_TX_CTL 38 /*!< CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */
87#define SC_P_ENET0_RGMII_TXD0 39 /*!< CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 */
88#define SC_P_ENET0_RGMII_TXD1 40 /*!< CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */
89#define SC_P_ENET0_RGMII_TXD2 41 /*!< CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 */
90#define SC_P_ENET0_RGMII_TXD3 42 /*!< CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, LSIO.GPIO5.IO02 */
91#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 43 /*!< */
92#define SC_P_ENET0_RGMII_RXC 44 /*!< CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */
93#define SC_P_ENET0_RGMII_RX_CTL 45 /*!< CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 */
94#define SC_P_ENET0_RGMII_RXD0 46 /*!< CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */
95#define SC_P_ENET0_RGMII_RXD1 47 /*!< CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */
96#define SC_P_ENET0_RGMII_RXD2 48 /*!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */
97#define SC_P_ENET0_RGMII_RXD3 49 /*!< CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3, LSIO.GPIO5.IO08 */
98#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 50 /*!< */
99#define SC_P_ENET0_REFCLK_125M_25M 51 /*!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO5.IO09 */
100#define SC_P_ENET0_MDIO 52 /*!< CONN.ENET0.MDIO, ADMA.I2C3.SDA, CONN.ENET1.MDIO, LSIO.GPIO5.IO10 */
101#define SC_P_ENET0_MDC 53 /*!< CONN.ENET0.MDC, ADMA.I2C3.SCL, CONN.ENET1.MDC, LSIO.GPIO5.IO11 */
102#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 54 /*!< */
103#define SC_P_ESAI0_FSR 55 /*!< ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.ENET1.RGMII_TXC, CONN.ENET1.RCLK50M_IN */
104#define SC_P_ESAI0_FST 56 /*!< ADMA.ESAI0.FST, CONN.MLB.CLK, ADMA.LCDIF.D01, CONN.ENET1.RGMII_TXD2, LSIO.GPIO0.IO01 */
105#define SC_P_ESAI0_SCKR 57 /*!< ADMA.ESAI0.SCKR, ADMA.LCDIF.D02, CONN.ENET1.RGMII_TX_CTL, LSIO.GPIO0.IO02 */
106#define SC_P_ESAI0_SCKT 58 /*!< ADMA.ESAI0.SCKT, CONN.MLB.SIG, ADMA.LCDIF.D03, CONN.ENET1.RGMII_TXD3, LSIO.GPIO0.IO03 */
107#define SC_P_ESAI0_TX0 59 /*!< ADMA.ESAI0.TX0, CONN.MLB.DATA, ADMA.LCDIF.D04, CONN.ENET1.RGMII_RXC, LSIO.GPIO0.IO04 */
108#define SC_P_ESAI0_TX1 60 /*!< ADMA.ESAI0.TX1, ADMA.LCDIF.D05, CONN.ENET1.RGMII_RXD3, LSIO.GPIO0.IO05 */
109#define SC_P_ESAI0_TX2_RX3 61 /*!< ADMA.ESAI0.TX2_RX3, CONN.ENET1.RMII_RX_ER, ADMA.LCDIF.D06, CONN.ENET1.RGMII_RXD2, LSIO.GPIO0.IO06 */
110#define SC_P_ESAI0_TX3_RX2 62 /*!< ADMA.ESAI0.TX3_RX2, ADMA.LCDIF.D07, CONN.ENET1.RGMII_RXD1, LSIO.GPIO0.IO07 */
111#define SC_P_ESAI0_TX4_RX1 63 /*!< ADMA.ESAI0.TX4_RX1, ADMA.LCDIF.D08, CONN.ENET1.RGMII_TXD0, LSIO.GPIO0.IO08 */
112#define SC_P_ESAI0_TX5_RX0 64 /*!< ADMA.ESAI0.TX5_RX0, ADMA.LCDIF.D09, CONN.ENET1.RGMII_TXD1, LSIO.GPIO0.IO09 */
113#define SC_P_SPDIF0_RX 65 /*!< ADMA.SPDIF0.RX, ADMA.MQS.R, ADMA.LCDIF.D10, CONN.ENET1.RGMII_RXD0, LSIO.GPIO0.IO10 */
114#define SC_P_SPDIF0_TX 66 /*!< ADMA.SPDIF0.TX, ADMA.MQS.L, ADMA.LCDIF.D11, CONN.ENET1.RGMII_RX_CTL, LSIO.GPIO0.IO11 */
115#define SC_P_SPDIF0_EXT_CLK 67 /*!< ADMA.SPDIF0.EXT_CLK, ADMA.LCDIF.D12, CONN.ENET1.REFCLK_125M_25M, LSIO.GPIO0.IO12 */
116#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 68 /*!< */
117#define SC_P_SPI3_SCK 69 /*!< ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */
118#define SC_P_SPI3_SDO 70 /*!< ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */
119#define SC_P_SPI3_SDI 71 /*!< ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */
120#define SC_P_SPI3_CS0 72 /*!< ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 */
121#define SC_P_SPI3_CS1 73 /*!< ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */
122#define SC_P_MCLK_IN1 74 /*!< ADMA.ACM.MCLK_IN1, ADMA.I2C3.SDA, ADMA.LCDIF.EN, ADMA.SPI2.SCK, ADMA.LCDIF.D17 */
123#define SC_P_MCLK_IN0 75 /*!< ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, ADMA.LCDIF.VSYNC, ADMA.SPI2.SDI, LSIO.GPIO0.IO19 */
124#define SC_P_MCLK_OUT0 76 /*!< ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, ADMA.LCDIF.CLK, ADMA.SPI2.SDO, LSIO.GPIO0.IO20 */
125#define SC_P_UART1_TX 77 /*!< ADMA.UART1.TX, LSIO.PWM0.OUT, LSIO.GPT0.CAPTURE, LSIO.GPIO0.IO21 */
126#define SC_P_UART1_RX 78 /*!< ADMA.UART1.RX, LSIO.PWM1.OUT, LSIO.GPT0.COMPARE, LSIO.GPT1.CLK, LSIO.GPIO0.IO22 */
127#define SC_P_UART1_RTS_B 79 /*!< ADMA.UART1.RTS_B, LSIO.PWM2.OUT, ADMA.LCDIF.D16, LSIO.GPT1.CAPTURE, LSIO.GPT0.CLK */
128#define SC_P_UART1_CTS_B 80 /*!< ADMA.UART1.CTS_B, LSIO.PWM3.OUT, ADMA.LCDIF.D17, LSIO.GPT1.COMPARE, LSIO.GPIO0.IO24 */
129#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHK 81 /*!< */
130#define SC_P_SAI0_TXD 82 /*!< ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, ADMA.LCDIF.D18, LSIO.GPIO0.IO25 */
131#define SC_P_SAI0_TXC 83 /*!< ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, ADMA.LCDIF.D19, LSIO.GPIO0.IO26 */
132#define SC_P_SAI0_RXD 84 /*!< ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, ADMA.LCDIF.D20, LSIO.GPIO0.IO27 */
133#define SC_P_SAI0_TXFS 85 /*!< ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO0.IO28 */
134#define SC_P_SAI1_RXD 86 /*!< ADMA.SAI1.RXD, ADMA.SAI0.RXFS, ADMA.SPI1.CS1, ADMA.LCDIF.D21, LSIO.GPIO0.IO29 */
135#define SC_P_SAI1_RXC 87 /*!< ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.LCDIF.D22, LSIO.GPIO0.IO30 */
136#define SC_P_SAI1_RXFS 88 /*!< ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.LCDIF.D23, LSIO.GPIO0.IO31 */
137#define SC_P_SPI2_CS0 89 /*!< ADMA.SPI2.CS0, LSIO.GPIO1.IO00 */
138#define SC_P_SPI2_SDO 90 /*!< ADMA.SPI2.SDO, LSIO.GPIO1.IO01 */
139#define SC_P_SPI2_SDI 91 /*!< ADMA.SPI2.SDI, LSIO.GPIO1.IO02 */
140#define SC_P_SPI2_SCK 92 /*!< ADMA.SPI2.SCK, LSIO.GPIO1.IO03 */
141#define SC_P_SPI0_SCK 93 /*!< ADMA.SPI0.SCK, ADMA.SAI0.TXC, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO04 */
142#define SC_P_SPI0_SDI 94 /*!< ADMA.SPI0.SDI, ADMA.SAI0.TXD, M40.TPM0.CH0, M40.GPIO0.IO02, LSIO.GPIO1.IO05 */
143#define SC_P_SPI0_SDO 95 /*!< ADMA.SPI0.SDO, ADMA.SAI0.TXFS, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO06 */
144#define SC_P_SPI0_CS1 96 /*!< ADMA.SPI0.CS1, ADMA.SAI0.RXC, ADMA.SAI1.TXD, ADMA.LCD_PWM0.OUT, LSIO.GPIO1.IO07 */
145#define SC_P_SPI0_CS0 97 /*!< ADMA.SPI0.CS0, ADMA.SAI0.RXD, M40.TPM0.CH1, M40.GPIO0.IO03, LSIO.GPIO1.IO08 */
146#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 98 /*!< */
147#define SC_P_ADC_IN1 99 /*!< ADMA.ADC.IN1, M40.I2C0.SDA, M40.GPIO0.IO01, LSIO.GPIO1.IO09 */
148#define SC_P_ADC_IN0 100 /*!< ADMA.ADC.IN0, M40.I2C0.SCL, M40.GPIO0.IO00, LSIO.GPIO1.IO10 */
149#define SC_P_ADC_IN3 101 /*!< ADMA.ADC.IN3, M40.UART0.TX, M40.GPIO0.IO03, ADMA.ACM.MCLK_OUT0, LSIO.GPIO1.IO11 */
150#define SC_P_ADC_IN2 102 /*!< ADMA.ADC.IN2, M40.UART0.RX, M40.GPIO0.IO02, ADMA.ACM.MCLK_IN0, LSIO.GPIO1.IO12 */
151#define SC_P_ADC_IN5 103 /*!< ADMA.ADC.IN5, M40.TPM0.CH1, M40.GPIO0.IO05, LSIO.GPIO1.IO13 */
152#define SC_P_ADC_IN4 104 /*!< ADMA.ADC.IN4, M40.TPM0.CH0, M40.GPIO0.IO04, LSIO.GPIO1.IO14 */
153#define SC_P_FLEXCAN0_RX 105 /*!< ADMA.FLEXCAN0.RX, ADMA.SAI2.RXC, ADMA.UART0.RTS_B, ADMA.SAI1.TXC, LSIO.GPIO1.IO15 */
154#define SC_P_FLEXCAN0_TX 106 /*!< ADMA.FLEXCAN0.TX, ADMA.SAI2.RXD, ADMA.UART0.CTS_B, ADMA.SAI1.TXFS, LSIO.GPIO1.IO16 */
155#define SC_P_FLEXCAN1_RX 107 /*!< ADMA.FLEXCAN1.RX, ADMA.SAI2.RXFS, ADMA.FTM.CH2, ADMA.SAI1.TXD, LSIO.GPIO1.IO17 */
156#define SC_P_FLEXCAN1_TX 108 /*!< ADMA.FLEXCAN1.TX, ADMA.SAI3.RXC, ADMA.DMA0.REQ_IN0, ADMA.SAI1.RXD, LSIO.GPIO1.IO18 */
157#define SC_P_FLEXCAN2_RX 109 /*!< ADMA.FLEXCAN2.RX, ADMA.SAI3.RXD, ADMA.UART3.RX, ADMA.SAI1.RXFS, LSIO.GPIO1.IO19 */
158#define SC_P_FLEXCAN2_TX 110 /*!< ADMA.FLEXCAN2.TX, ADMA.SAI3.RXFS, ADMA.UART3.TX, ADMA.SAI1.RXC, LSIO.GPIO1.IO20 */
159#define SC_P_UART0_RX 111 /*!< ADMA.UART0.RX, ADMA.MQS.R, ADMA.FLEXCAN0.RX, SCU.UART0.RX, LSIO.GPIO1.IO21 */
160#define SC_P_UART0_TX 112 /*!< ADMA.UART0.TX, ADMA.MQS.L, ADMA.FLEXCAN0.TX, SCU.UART0.TX, LSIO.GPIO1.IO22 */
161#define SC_P_UART2_TX 113 /*!< ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */
162#define SC_P_UART2_RX 114 /*!< ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */
163#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115 /*!< */
164#define SC_P_MIPI_DSI0_I2C0_SCL 116 /*!< MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 */
165#define SC_P_MIPI_DSI0_I2C0_SDA 117 /*!< MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 */
166#define SC_P_MIPI_DSI0_GPIO0_00 118 /*!< MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */
167#define SC_P_MIPI_DSI0_GPIO0_01 119 /*!< MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */
168#define SC_P_MIPI_DSI1_I2C0_SCL 120 /*!< MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 */
169#define SC_P_MIPI_DSI1_I2C0_SDA 121 /*!< MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 */
170#define SC_P_MIPI_DSI1_GPIO0_00 122 /*!< MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */
171#define SC_P_MIPI_DSI1_GPIO0_01 123 /*!< MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */
172#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 124 /*!< */
173#define SC_P_JTAG_TRST_B 125 /*!< SCU.JTAG.TRST_B, SCU.WDOG0.WDOG_OUT */
174#define SC_P_PMIC_I2C_SCL 126 /*!< SCU.PMIC_I2C.SCL, SCU.GPIO0.IOXX_PMIC_A35_ON, LSIO.GPIO2.IO01 */
175#define SC_P_PMIC_I2C_SDA 127 /*!< SCU.PMIC_I2C.SDA, SCU.GPIO0.IOXX_PMIC_GPU_ON, LSIO.GPIO2.IO02 */
176#define SC_P_PMIC_INT_B 128 /*!< SCU.DSC.PMIC_INT_B */
177#define SC_P_SCU_GPIO0_00 129 /*!< SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART3.RX, LSIO.GPIO2.IO03 */
178#define SC_P_SCU_GPIO0_01 130 /*!< SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART3.TX, SCU.WDOG0.WDOG_OUT */
179#define SC_P_SCU_PMIC_STANDBY 131 /*!< SCU.DSC.PMIC_STANDBY */
180#define SC_P_SCU_BOOT_MODE0 132 /*!< SCU.DSC.BOOT_MODE0 */
181#define SC_P_SCU_BOOT_MODE1 133 /*!< SCU.DSC.BOOT_MODE1 */
182#define SC_P_SCU_BOOT_MODE2 134 /*!< SCU.DSC.BOOT_MODE2, SCU.PMIC_I2C.SDA */
183#define SC_P_SCU_BOOT_MODE3 135 /*!< SCU.DSC.BOOT_MODE3, SCU.PMIC_I2C.SCL, SCU.DSC.RTC_CLOCK_OUTPUT_32K */
184#define SC_P_CSI_D00 136 /*!< CI_PI.D02, ADMA.SAI0.RXC */
185#define SC_P_CSI_D01 137 /*!< CI_PI.D03, ADMA.SAI0.RXD */
186#define SC_P_CSI_D02 138 /*!< CI_PI.D04, ADMA.SAI0.RXFS */
187#define SC_P_CSI_D03 139 /*!< CI_PI.D05, ADMA.SAI2.RXC */
188#define SC_P_CSI_D04 140 /*!< CI_PI.D06, ADMA.SAI2.RXD */
189#define SC_P_CSI_D05 141 /*!< CI_PI.D07, ADMA.SAI2.RXFS */
190#define SC_P_CSI_D06 142 /*!< CI_PI.D08, ADMA.SAI3.RXC */
191#define SC_P_CSI_D07 143 /*!< CI_PI.D09, ADMA.SAI3.RXD */
192#define SC_P_CSI_HSYNC 144 /*!< CI_PI.HSYNC, CI_PI.D00, ADMA.SAI3.RXFS */
193#define SC_P_CSI_VSYNC 145 /*!< CI_PI.VSYNC, CI_PI.D01 */
194#define SC_P_CSI_PCLK 146 /*!< CI_PI.PCLK, MIPI_CSI0.I2C0.SCL, ADMA.SPI1.SCK, LSIO.GPIO3.IO00 */
195#define SC_P_CSI_MCLK 147 /*!< CI_PI.MCLK, MIPI_CSI0.I2C0.SDA, ADMA.SPI1.SDO, LSIO.GPIO3.IO01 */
196#define SC_P_CSI_EN 148 /*!< CI_PI.EN, CI_PI.I2C.SCL, ADMA.I2C3.SCL, ADMA.SPI1.SDI, LSIO.GPIO3.IO02 */
197#define SC_P_CSI_RESET 149 /*!< CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */
198#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150 /*!< */
199#define SC_P_MIPI_CSI0_MCLK_OUT 151 /*!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */
200#define SC_P_MIPI_CSI0_I2C0_SCL 152 /*!< MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 */
201#define SC_P_MIPI_CSI0_I2C0_SDA 153 /*!< MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 */
202#define SC_P_MIPI_CSI0_GPIO0_01 154 /*!< MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */
203#define SC_P_MIPI_CSI0_GPIO0_00 155 /*!< MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */
204#define SC_P_QSPI0A_DATA0 156 /*!< LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */
205#define SC_P_QSPI0A_DATA1 157 /*!< LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */
206#define SC_P_QSPI0A_DATA2 158 /*!< LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */
207#define SC_P_QSPI0A_DATA3 159 /*!< LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */
208#define SC_P_QSPI0A_DQS 160 /*!< LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */
209#define SC_P_QSPI0A_SS0_B 161 /*!< LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */
210#define SC_P_QSPI0A_SS1_B 162 /*!< LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */
211#define SC_P_QSPI0A_SCLK 163 /*!< LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */
212#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164 /*!< */
213#define SC_P_QSPI0B_SCLK 165 /*!< LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */
214#define SC_P_QSPI0B_DATA0 166 /*!< LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1, LSIO.GPIO3.IO18 */
215#define SC_P_QSPI0B_DATA1 167 /*!< LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2, LSIO.GPIO3.IO19 */
216#define SC_P_QSPI0B_DATA2 168 /*!< LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */
217#define SC_P_QSPI0B_DATA3 169 /*!< LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */
218#define SC_P_QSPI0B_DQS 170 /*!< LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 */
219#define SC_P_QSPI0B_SS0_B 171 /*!< LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */
220#define SC_P_QSPI0B_SS1_B 172 /*!< LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3, LSIO.GPIO3.IO24 */
221#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0B 173 /*!< */
222/*@}*/
223
224#endif /* SC_PADS_H */
225
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/ipc.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/ipc.h
new file mode 100644
index 000000000..b5ce3062b
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/ipc.h
@@ -0,0 +1,92 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2017-2019 NXP
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without modification,
8 * are permitted provided that the following conditions are met:
9 *
10 * o Redistributions of source code must retain the above copyright notice, this list
11 * of conditions and the following disclaimer.
12 *
13 * o Redistributions in binary form must reproduce the above copyright notice, this
14 * list of conditions and the following disclaimer in the documentation and/or
15 * other materials provided with the distribution.
16 *
17 * o Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/*!
34 * Header file for the IPC implementation.
35 */
36
37#ifndef SC_IPC_H
38#define SC_IPC_H
39
40/* Includes */
41
42#include "main/types.h"
43
44/* Defines */
45
46/* Types */
47
48/* Functions */
49
50/*!
51 * This function opens an IPC channel.
52 *
53 * @param[out] ipc return pointer for ipc handle
54 * @param[in] id id of channel to open
55 *
56 * @return Returns an error code (SC_ERR_NONE = success, SC_ERR_IPC
57 * otherwise).
58 *
59 * The \a id parameter is implementation specific. Could be an MU
60 * address, pointer to a driver path, channel index, etc.
61 */
62sc_err_t sc_ipc_open(sc_ipc_t *ipc, sc_ipc_id_t id);
63
64/*!
65 * This function closes an IPC channel.
66 *
67 * @param[in] ipc id of channel to close
68 */
69void sc_ipc_close(sc_ipc_t ipc);
70
71/*!
72 * This function reads a message from an IPC channel.
73 *
74 * @param[in] ipc id of channel read from
75 * @param[out] data pointer to message buffer to read
76 *
77 * This function will block if no message is available to be read.
78 */
79void sc_ipc_read(sc_ipc_t ipc, void *data);
80
81/*!
82 * This function writes a message to an IPC channel.
83 *
84 * @param[in] ipc id of channel to write to
85 * @param[in] data pointer to message buffer to write
86 *
87 * This function will block if the outgoing buffer is full.
88 */
89void sc_ipc_write(sc_ipc_t ipc, const void *data);
90
91#endif /* SC_IPC_H */
92
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/ipc_imx8qx.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/ipc_imx8qx.c
new file mode 100644
index 000000000..8280c222a
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/ipc_imx8qx.c
@@ -0,0 +1,159 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2017-2019 NXP
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "MIMX8QX2_cm4.h"
9#include "main/ipc.h"
10#include "main/rpc.h"
11#ifdef FSL_RTOS_FREE_RTOS
12#include "FreeRTOS.h"
13#include "task.h"
14#endif
15
16/*******************************************************************************
17 * Definitions
18 ******************************************************************************/
19
20/* Component ID definition, used by tools. */
21#ifndef FSL_COMPONENT_ID
22#define FSL_COMPONENT_ID "platform.drivers.scfwapi"
23#endif
24
25/*----------------------------------------------------------------------*/
26/* RPC command/response */
27/*----------------------------------------------------------------------*/
28void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, sc_bool_t no_resp)
29{
30#ifdef FSL_RTOS_FREE_RTOS
31 if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED)
32 {
33 /* Suspends the scheduler to make sure there's only one rpc call ongoing at a time. */
34 vTaskSuspendAll();
35 }
36#endif
37 sc_ipc_write(ipc, msg);
38 if (!no_resp)
39 {
40 sc_ipc_read(ipc, msg);
41 }
42#ifdef FSL_RTOS_FREE_RTOS
43 if (xTaskGetSchedulerState() != taskSCHEDULER_NOT_STARTED)
44 {
45 (void)xTaskResumeAll();
46 }
47#endif
48}
49
50/*--------------------------------------------------------------------------*/
51/* Open an IPC channel */
52/*--------------------------------------------------------------------------*/
53sc_err_t sc_ipc_open(sc_ipc_t *ipc, sc_ipc_id_t id)
54{
55 MU_Type *base = (MU_Type *)id;
56
57 /* get mu base associated with ipc channel */
58 if ((ipc == NULL) || (base == NULL))
59 {
60 return SC_ERR_IPC;
61 }
62
63 /* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */
64 base->CR &= ~(MU_CR_GIEn_MASK | MU_CR_RIEn_MASK | MU_CR_TIEn_MASK | MU_CR_GIRn_MASK | MU_CR_Fn_MASK);
65
66 /* Return MU address as handle */
67 *ipc = (sc_ipc_t)id;
68
69 return SC_ERR_NONE;
70}
71
72/*--------------------------------------------------------------------------*/
73/* Close an IPC channel */
74/*--------------------------------------------------------------------------*/
75void sc_ipc_close(sc_ipc_t ipc)
76{
77}
78
79/*--------------------------------------------------------------------------*/
80/* Read message from an IPC channel */
81/*--------------------------------------------------------------------------*/
82void sc_ipc_read(sc_ipc_t ipc, void *data)
83{
84 MU_Type *base = (MU_Type *)ipc;
85 sc_rpc_msg_t *msg = (sc_rpc_msg_t *)data;
86 uint8_t count = 0;
87
88 /* Check parms */
89 if ((base == NULL) || (msg == NULL))
90 {
91 return;
92 }
93
94 /* Read first word */
95 /* Wait RX register to be full. */
96 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U))) == 0U)
97 {
98 }
99 msg->header = base->RR[0];
100 count++;
101
102 /* Check size */
103 if (msg->size > SC_RPC_MAX_MSG)
104 {
105 msg->header = 0;
106 return;
107 }
108
109 /* Read remaining words */
110 while (count < msg->size)
111 {
112 /* Wait RX register to be full. */
113 while ((base->SR & (1UL << (MU_SR_RFn_SHIFT + 3U - count % MU_RR_COUNT))) == 0U)
114 {
115 }
116 msg->DATA.u32[count - 1U] = base->RR[count % MU_RR_COUNT];
117 count++;
118 }
119}
120
121/*--------------------------------------------------------------------------*/
122/* Write a message to an IPC channel */
123/*--------------------------------------------------------------------------*/
124void sc_ipc_write(sc_ipc_t ipc, const void *data)
125{
126 MU_Type *base = (MU_Type *)ipc;
127 const sc_rpc_msg_t *msg = (const sc_rpc_msg_t *)data;
128 uint8_t count = 0;
129
130 /* Check parms */
131 if ((base == NULL) || (msg == NULL))
132 {
133 return;
134 }
135
136 /* Check size */
137 if (msg->size > SC_RPC_MAX_MSG)
138 {
139 return;
140 }
141
142 /* Write first word */
143 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U))) == 0U)
144 {
145 }
146 base->TR[0] = msg->header;
147 count++;
148
149 /* Write remaining words */
150 while (count < msg->size)
151 {
152 /* Wait Tx register to be empty and send Tx Data. */
153 while ((base->SR & (1UL << (MU_SR_TEn_SHIFT + 3U - count % MU_TR_COUNT))) == 0U)
154 {
155 }
156 base->TR[count % MU_TR_COUNT] = msg->DATA.u32[count - 1U];
157 count++;
158 }
159}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/rpc.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/rpc.h
new file mode 100644
index 000000000..469a6991c
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/rpc.h
@@ -0,0 +1,175 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2017-2019 NXP
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without modification,
8 * are permitted provided that the following conditions are met:
9 *
10 * o Redistributions of source code must retain the above copyright notice, this list
11 * of conditions and the following disclaimer.
12 *
13 * o Redistributions in binary form must reproduce the above copyright notice, this
14 * list of conditions and the following disclaimer in the documentation and/or
15 * other materials provided with the distribution.
16 *
17 * o Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/*!
34 * Header file for the RPC implementation.
35 */
36
37#ifndef SC_RPC_H
38#define SC_RPC_H
39
40/* Includes */
41
42#include "main/types.h"
43#include "main/ipc.h"
44
45/* Defines */
46
47#define SCFW_API_VERSION_MAJOR 1U
48#define SCFW_API_VERSION_MINOR 16U
49
50#define SC_RPC_VERSION 1U
51
52#define SC_RPC_MAX_MSG 8U
53
54#define RPC_VER(MESG) ((MESG)->version)
55#define RPC_SIZE(MESG) ((MESG)->size)
56#define RPC_SVC(MESG) ((MESG)->svc)
57#define RPC_FUNC(MESG) ((MESG)->func)
58#define RPC_R8(MESG) ((MESG)->func)
59#define RPC_I64(MESG, IDX) ((I64(RPC_U32((MESG), (IDX))) << 32ULL) \
60 | I64(RPC_U32((MESG), (IDX) + 4U)))
61#define RPC_I32(MESG, IDX) ((MESG)->DATA.i32[(IDX) / 4U])
62#define RPC_I16(MESG, IDX) ((MESG)->DATA.i16[(IDX) / 2U])
63#define RPC_I8(MESG, IDX) ((MESG)->DATA.i8[(IDX)])
64#define RPC_U64(MESG, IDX) ((U64(RPC_U32((MESG), (IDX))) << 32ULL) \
65 | U64(RPC_U32((MESG), (IDX) + 4U)))
66#define RPC_U32(MESG, IDX) ((MESG)->DATA.u32[(IDX) / 4U])
67#define RPC_U16(MESG, IDX) ((MESG)->DATA.u16[(IDX) / 2U])
68#define RPC_U8(MESG, IDX) ((MESG)->DATA.u8[(IDX)])
69
70#define SC_RPC_SVC_UNKNOWN 0U
71#define SC_RPC_SVC_RETURN 1U
72#define SC_RPC_SVC_PM 2U
73#define SC_RPC_SVC_RM 3U
74#define SC_RPC_SVC_TIMER 5U
75#define SC_RPC_SVC_PAD 6U
76#define SC_RPC_SVC_MISC 7U
77#define SC_RPC_SVC_IRQ 8U
78#define SC_RPC_SVC_SECO 9U
79#define SC_RPC_SVC_ABORT 10U
80
81#define SC_RPC_ASYNC_STATE_RD_START 0U
82#define SC_RPC_ASYNC_STATE_RD_ACTIVE 1U
83#define SC_RPC_ASYNC_STATE_RD_DONE 2U
84#define SC_RPC_ASYNC_STATE_WR_START 3U
85#define SC_RPC_ASYNC_STATE_WR_ACTIVE 4U
86#define SC_RPC_ASYNC_STATE_WR_DONE 5U
87
88/* SC -> Client general-purpose MU IRQs */
89#define SC_RPC_MU_GIR_SVC 0x1U
90#define SC_RPC_MU_GIR_WAKE 0x2U
91#define SC_RPC_MU_GIR_BOOT 0x4U
92#define SC_RPC_MU_GIR_DBG 0x8U
93
94/* Client -> SC general-purpose MU IRQs */
95#define SC_RPC_MU_GIR_RST 0x1U
96
97#define I8(X) ((int8_t) (X))
98#define I16(X) ((int16_t) (X))
99#define I32(X) ((int32_t) (X))
100#define I64(X) ((int64_t) (X))
101#define U8(X) ((uint8_t) (X))
102#define U16(X) ((uint16_t) (X))
103#define U32(X) ((uint32_t) (X))
104#define U64(X) ((uint64_t) (X))
105
106#define PTR_I8(X) ((int8_t*) (X))
107#define PTR_I16(X) ((int16_t*) (X))
108#define PTR_I32(X) ((int32_t*) (X))
109#define PTR_I64(X) ((int64_t*) (X))
110#define PTR_U8(X) ((uint8_t*) (X))
111#define PTR_U16(X) ((uint16_t*) (X))
112#define PTR_U32(X) ((uint32_t*) (X))
113#define PTR_U64(X) ((uint64_t*) (X))
114
115#define U2B(X) (((X) != 0U) ? SC_TRUE : SC_FALSE)
116#define U2B32(X) (((X) != 0UL) ? SC_TRUE : SC_FALSE)
117#define B2U8(X) (((X) != SC_FALSE) ? U8(0x01U) : U8(0x00U))
118#define B2U16(X) (((X) != SC_FALSE) ? U16(0x01U) : U16(0x00U))
119#define B2U32(X) (((X) != SC_FALSE) ? U32(0x01U) : U32(0x00U))
120
121/* Types */
122
123typedef uint8_t sc_rpc_svc_t;
124
125typedef struct
126{
127 union
128 {
129 uint32_t header;
130 struct
131 {
132 uint8_t version;
133 uint8_t size;
134 uint8_t svc;
135 uint8_t func;
136 };
137 };
138 union
139 {
140 int32_t i32[(SC_RPC_MAX_MSG - 1U)];
141 int16_t i16[(SC_RPC_MAX_MSG - 1U) * 2U];
142 int8_t i8[(SC_RPC_MAX_MSG - 1U) * 4U];
143 uint32_t u32[(SC_RPC_MAX_MSG - 1U)];
144 uint16_t u16[(SC_RPC_MAX_MSG - 1U) * 2U];
145 uint8_t u8[(SC_RPC_MAX_MSG - 1U) * 4U];
146 } DATA;
147} sc_rpc_msg_t;
148
149typedef uint8_t sc_rpc_async_state_t;
150
151typedef struct
152{
153 sc_rpc_async_state_t state;
154 uint8_t wordIdx;
155 sc_rpc_msg_t msg;
156 uint32_t timeStamp;
157} sc_rpc_async_msg_t;
158
159/* Functions */
160
161/*!
162 * This is an internal function to send an RPC message over an IPC
163 * channel. It is called by client-side SCFW API function shims.
164 *
165 * @param[in] ipc IPC handle
166 * @param[in,out] msg handle to a message
167 * @param[in] no_resp response flag
168 *
169 * If \a no_resp is SC_FALSE then this function waits for a response
170 * and returns the result in \a msg.
171 */
172void sc_call_rpc(sc_ipc_t ipc, sc_rpc_msg_t *msg, sc_bool_t no_resp);
173
174#endif /* SC_RPC_H */
175
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/scfw.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/scfw.h
new file mode 100644
index 000000000..c39de1d39
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/scfw.h
@@ -0,0 +1,60 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2017-2019 NXP
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without modification,
8 * are permitted provided that the following conditions are met:
9 *
10 * o Redistributions of source code must retain the above copyright notice, this list
11 * of conditions and the following disclaimer.
12 *
13 * o Redistributions in binary form must reproduce the above copyright notice, this
14 * list of conditions and the following disclaimer in the documentation and/or
15 * other materials provided with the distribution.
16 *
17 * o Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/*!
34 * Header file containing includes to system headers and porting types.
35 */
36
37#ifndef SC_SCFW_H
38#define SC_SCFW_H
39
40/* Includes */
41
42#include <stdint.h>
43#include <stddef.h>
44#include <string.h>
45#include <stdbool.h>
46
47/*!
48 * This type is used to declare a handle for an IPC communication
49 * channel. Its meaning is specific to the IPC implementation.
50 */
51typedef uint32_t sc_ipc_t;
52
53/*!
54 * This type is used to declare an ID for an IPC communication
55 * channel. Its meaning is specific to the IPC implementation.
56 */
57typedef uint32_t sc_ipc_id_t;
58
59#endif /* SC_SCFW_H */
60
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/types.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/types.h
new file mode 100644
index 000000000..249c898e6
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX2/scfw_api/main/types.h
@@ -0,0 +1,918 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2017-2019 NXP
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 * Redistribution and use in source and binary forms, with or without modification,
8 * are permitted provided that the following conditions are met:
9 *
10 * o Redistributions of source code must retain the above copyright notice, this list
11 * of conditions and the following disclaimer.
12 *
13 * o Redistributions in binary form must reproduce the above copyright notice, this
14 * list of conditions and the following disclaimer in the documentation and/or
15 * other materials provided with the distribution.
16 *
17 * o Neither the name of the copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived from this
19 * software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33/*!
34 * Header file containing types used across multiple service APIs.
35 */
36
37#ifndef SC_TYPES_H
38#define SC_TYPES_H
39
40/* Includes */
41
42#include "main/scfw.h"
43
44/* Defines */
45
46/*!
47 * @name Defines for common frequencies
48 */
49/*@{*/
50#define SC_32KHZ 32768U /*!< 32KHz */
51#define SC_10MHZ 10000000U /*!< 10MHz */
52#define SC_16MHZ 16000000U /*!< 16MHz */
53#define SC_20MHZ 20000000U /*!< 20MHz */
54#define SC_25MHZ 25000000U /*!< 25MHz */
55#define SC_27MHZ 27000000U /*!< 27MHz */
56#define SC_40MHZ 40000000U /*!< 40MHz */
57#define SC_45MHZ 45000000U /*!< 45MHz */
58#define SC_50MHZ 50000000U /*!< 50MHz */
59#define SC_60MHZ 60000000U /*!< 60MHz */
60#define SC_66MHZ 66666666U /*!< 66MHz */
61#define SC_74MHZ 74250000U /*!< 74.25MHz */
62#define SC_80MHZ 80000000U /*!< 80MHz */
63#define SC_83MHZ 83333333U /*!< 83MHz */
64#define SC_84MHZ 84375000U /*!< 84.37MHz */
65#define SC_100MHZ 100000000U /*!< 100MHz */
66#define SC_114MHZ 114000000U /*!< 114MHz */
67#define SC_125MHZ 125000000U /*!< 125MHz */
68#define SC_133MHZ 133333333U /*!< 133MHz */
69#define SC_135MHZ 135000000U /*!< 135MHz */
70#define SC_150MHZ 150000000U /*!< 150MHz */
71#define SC_160MHZ 160000000U /*!< 160MHz */
72#define SC_166MHZ 166666666U /*!< 166MHz */
73#define SC_175MHZ 175000000U /*!< 175MHz */
74#define SC_180MHZ 180000000U /*!< 180MHz */
75#define SC_200MHZ 200000000U /*!< 200MHz */
76#define SC_250MHZ 250000000U /*!< 250MHz */
77#define SC_266MHZ 266666666U /*!< 266MHz */
78#define SC_300MHZ 300000000U /*!< 300MHz */
79#define SC_312MHZ 312500000U /*!< 312.5MHZ */
80#define SC_320MHZ 320000000U /*!< 320MHz */
81#define SC_325MHZ 325000000U /*!< 325MHz */
82#define SC_333MHZ 333333333U /*!< 333MHz */
83#define SC_350MHZ 350000000U /*!< 350MHz */
84#define SC_372MHZ 372000000U /*!< 372MHz */
85#define SC_375MHZ 375000000U /*!< 375MHz */
86#define SC_400MHZ 400000000U /*!< 400MHz */
87#define SC_465MHZ 465000000U /*!< 465MHz */
88#define SC_500MHZ 500000000U /*!< 500MHz */
89#define SC_594MHZ 594000000U /*!< 594MHz */
90#define SC_625MHZ 625000000U /*!< 625MHz */
91#define SC_640MHZ 640000000U /*!< 640MHz */
92#define SC_648MHZ 648000000U /*!< 648MHz */
93#define SC_650MHZ 650000000U /*!< 650MHz */
94#define SC_667MHZ 666666667U /*!< 667MHz */
95#define SC_675MHZ 675000000U /*!< 675MHz */
96#define SC_700MHZ 700000000U /*!< 700MHz */
97#define SC_720MHZ 720000000U /*!< 720MHz */
98#define SC_750MHZ 750000000U /*!< 750MHz */
99#define SC_753MHZ 753000000U /*!< 753MHz */
100#define SC_793MHZ 793000000U /*!< 793MHz */
101#define SC_800MHZ 800000000U /*!< 800MHz */
102#define SC_850MHZ 850000000U /*!< 850MHz */
103#define SC_858MHZ 858000000U /*!< 858MHz */
104#define SC_900MHZ 900000000U /*!< 900MHz */
105#define SC_953MHZ 953000000U /*!< 953MHz */
106#define SC_963MHZ 963000000U /*!< 963MHz */
107#define SC_1000MHZ 1000000000U /*!< 1GHz */
108#define SC_1060MHZ 1060000000U /*!< 1.06GHz */
109#define SC_1068MHZ 1068000000U /*!< 1.068GHz */
110#define SC_1121MHZ 1121000000U /*!< 1.121GHz */
111#define SC_1173MHZ 1173000000U /*!< 1.173GHz */
112#define SC_1188MHZ 1188000000U /*!< 1.188GHz */
113#define SC_1260MHZ 1260000000U /*!< 1.26GHz */
114#define SC_1278MHZ 1278000000U /*!< 1.278GHz */
115#define SC_1280MHZ 1280000000U /*!< 1.28GHz */
116#define SC_1300MHZ 1300000000U /*!< 1.3GHz */
117#define SC_1313MHZ 1313000000U /*!< 1.313GHz */
118#define SC_1345MHZ 1345000000U /*!< 1.345GHz */
119#define SC_1400MHZ 1400000000U /*!< 1.4GHz */
120#define SC_1500MHZ 1500000000U /*!< 1.5GHz */
121#define SC_1600MHZ 1600000000U /*!< 1.6GHz */
122#define SC_1800MHZ 1800000000U /*!< 1.8GHz */
123#define SC_1860MHZ 1860000000U /*!< 1.86GHz */
124#define SC_2000MHZ 2000000000U /*!< 2.0GHz */
125#define SC_2112MHZ 2112000000U /*!< 2.12GHz */
126/*@}*/
127
128/*!
129 * @name Defines for 24M related frequencies
130 */
131/*@{*/
132#define SC_8MHZ 8000000U /*!< 8MHz */
133#define SC_12MHZ 12000000U /*!< 12MHz */
134#define SC_19MHZ 19800000U /*!< 19.8MHz */
135#define SC_24MHZ 24000000U /*!< 24MHz */
136#define SC_48MHZ 48000000U /*!< 48MHz */
137#define SC_120MHZ 120000000U /*!< 120MHz */
138#define SC_132MHZ 132000000U /*!< 132MHz */
139#define SC_144MHZ 144000000U /*!< 144MHz */
140#define SC_192MHZ 192000000U /*!< 192MHz */
141#define SC_211MHZ 211200000U /*!< 211.2MHz */
142#define SC_228MHZ 228000000U /*!< 233MHz */
143#define SC_240MHZ 240000000U /*!< 240MHz */
144#define SC_264MHZ 264000000U /*!< 264MHz */
145#define SC_352MHZ 352000000U /*!< 352MHz */
146#define SC_360MHZ 360000000U /*!< 360MHz */
147#define SC_384MHZ 384000000U /*!< 384MHz */
148#define SC_396MHZ 396000000U /*!< 396MHz */
149#define SC_432MHZ 432000000U /*!< 432MHz */
150#define SC_456MHZ 456000000U /*!< 466MHz */
151#define SC_480MHZ 480000000U /*!< 480MHz */
152#define SC_600MHZ 600000000U /*!< 600MHz */
153#define SC_744MHZ 744000000U /*!< 744MHz */
154#define SC_792MHZ 792000000U /*!< 792MHz */
155#define SC_864MHZ 864000000U /*!< 864MHz */
156#define SC_912MHZ 912000000U /*!< 912MHz */
157#define SC_960MHZ 960000000U /*!< 960MHz */
158#define SC_1056MHZ 1056000000U /*!< 1056MHz */
159#define SC_1104MHZ 1104000000U /*!< 1104MHz */
160#define SC_1200MHZ 1200000000U /*!< 1.2GHz */
161#define SC_1464MHZ 1464000000U /*!< 1.464GHz */
162#define SC_2400MHZ 2400000000U /*!< 2.4GHz */
163/*@}*/
164
165/*!
166 * @name Defines for A/V related frequencies
167 */
168/*@{*/
169#define SC_62MHZ 62937500U /*!< 62.9375MHz */
170#define SC_755MHZ 755250000U /*!< 755.25MHz */
171/*@}*/
172
173/*!
174 * @name Defines for type widths
175 */
176/*@{*/
177#define SC_BOOL_W 1U /*!< Width of sc_bool_t */
178#define SC_ERR_W 4U /*!< Width of sc_err_t */
179#define SC_RSRC_W 10U /*!< Width of sc_rsrc_t */
180#define SC_CTRL_W 6U /*!< Width of sc_ctrl_t */
181/*@}*/
182
183/*!
184 * @name Defines for sc_bool_t
185 */
186/*@{*/
187#define SC_FALSE ((sc_bool_t) 0U) /*!< False */
188#define SC_TRUE ((sc_bool_t) 1U) /*!< True */
189/*@}*/
190
191/*!
192 * @name Defines for sc_err_t.
193 */
194/*@{*/
195#define SC_ERR_NONE 0U /*!< Success */
196#define SC_ERR_VERSION 1U /*!< Incompatible API version */
197#define SC_ERR_CONFIG 2U /*!< Configuration error */
198#define SC_ERR_PARM 3U /*!< Bad parameter */
199#define SC_ERR_NOACCESS 4U /*!< Permission error (no access) */
200#define SC_ERR_LOCKED 5U /*!< Permission error (locked) */
201#define SC_ERR_UNAVAILABLE 6U /*!< Unavailable (out of resources) */
202#define SC_ERR_NOTFOUND 7U /*!< Not found */
203#define SC_ERR_NOPOWER 8U /*!< No power */
204#define SC_ERR_IPC 9U /*!< Generic IPC error */
205#define SC_ERR_BUSY 10U /*!< Resource is currently busy/active */
206#define SC_ERR_FAIL 11U /*!< General I/O failure */
207#define SC_ERR_LAST 12U
208/*@}*/
209
210/*!
211 * @name Defines for sc_rsrc_t.
212 */
213/*@{*/
214#define SC_R_A53 0U
215#define SC_R_A53_0 1U
216#define SC_R_A53_1 2U
217#define SC_R_A53_2 3U
218#define SC_R_A53_3 4U
219#define SC_R_A72 5U
220#define SC_R_A72_0 6U
221#define SC_R_A72_1 7U
222#define SC_R_A72_2 8U
223#define SC_R_A72_3 9U
224#define SC_R_CCI 10U
225#define SC_R_DB 11U
226#define SC_R_DRC_0 12U
227#define SC_R_DRC_1 13U
228#define SC_R_GIC_SMMU 14U
229#define SC_R_IRQSTR_M4_0 15U
230#define SC_R_IRQSTR_M4_1 16U
231#define SC_R_SMMU 17U
232#define SC_R_GIC 18U
233#define SC_R_DC_0_BLIT0 19U
234#define SC_R_DC_0_BLIT1 20U
235#define SC_R_DC_0_BLIT2 21U
236#define SC_R_DC_0_BLIT_OUT 22U
237#define SC_R_PERF 23U
238#define SC_R_USB_1_PHY 24U
239#define SC_R_DC_0_WARP 25U
240#define SC_R_V2X_MU_0 26U
241#define SC_R_V2X_MU_1 27U
242#define SC_R_DC_0_VIDEO0 28U
243#define SC_R_DC_0_VIDEO1 29U
244#define SC_R_DC_0_FRAC0 30U
245#define SC_R_V2X_MU_2 31U
246#define SC_R_DC_0 32U
247#define SC_R_GPU_2_PID0 33U
248#define SC_R_DC_0_PLL_0 34U
249#define SC_R_DC_0_PLL_1 35U
250#define SC_R_DC_1_BLIT0 36U
251#define SC_R_DC_1_BLIT1 37U
252#define SC_R_DC_1_BLIT2 38U
253#define SC_R_DC_1_BLIT_OUT 39U
254#define SC_R_V2X_MU_3 40U
255#define SC_R_V2X_MU_4 41U
256#define SC_R_DC_1_WARP 42U
257#define SC_R_TBU_CTL 43U
258#define SC_R_SECVIO 44U
259#define SC_R_DC_1_VIDEO0 45U
260#define SC_R_DC_1_VIDEO1 46U
261#define SC_R_DC_1_FRAC0 47U
262#define SC_R_UNUSED13 48U
263#define SC_R_DC_1 49U
264#define SC_R_UNUSED14 50U
265#define SC_R_DC_1_PLL_0 51U
266#define SC_R_DC_1_PLL_1 52U
267#define SC_R_SPI_0 53U
268#define SC_R_SPI_1 54U
269#define SC_R_SPI_2 55U
270#define SC_R_SPI_3 56U
271#define SC_R_UART_0 57U
272#define SC_R_UART_1 58U
273#define SC_R_UART_2 59U
274#define SC_R_UART_3 60U
275#define SC_R_UART_4 61U
276#define SC_R_EMVSIM_0 62U
277#define SC_R_EMVSIM_1 63U
278#define SC_R_DMA_0_CH0 64U
279#define SC_R_DMA_0_CH1 65U
280#define SC_R_DMA_0_CH2 66U
281#define SC_R_DMA_0_CH3 67U
282#define SC_R_DMA_0_CH4 68U
283#define SC_R_DMA_0_CH5 69U
284#define SC_R_DMA_0_CH6 70U
285#define SC_R_DMA_0_CH7 71U
286#define SC_R_DMA_0_CH8 72U
287#define SC_R_DMA_0_CH9 73U
288#define SC_R_DMA_0_CH10 74U
289#define SC_R_DMA_0_CH11 75U
290#define SC_R_DMA_0_CH12 76U
291#define SC_R_DMA_0_CH13 77U
292#define SC_R_DMA_0_CH14 78U
293#define SC_R_DMA_0_CH15 79U
294#define SC_R_DMA_0_CH16 80U
295#define SC_R_DMA_0_CH17 81U
296#define SC_R_DMA_0_CH18 82U
297#define SC_R_DMA_0_CH19 83U
298#define SC_R_DMA_0_CH20 84U
299#define SC_R_DMA_0_CH21 85U
300#define SC_R_DMA_0_CH22 86U
301#define SC_R_DMA_0_CH23 87U
302#define SC_R_DMA_0_CH24 88U
303#define SC_R_DMA_0_CH25 89U
304#define SC_R_DMA_0_CH26 90U
305#define SC_R_DMA_0_CH27 91U
306#define SC_R_DMA_0_CH28 92U
307#define SC_R_DMA_0_CH29 93U
308#define SC_R_DMA_0_CH30 94U
309#define SC_R_DMA_0_CH31 95U
310#define SC_R_I2C_0 96U
311#define SC_R_I2C_1 97U
312#define SC_R_I2C_2 98U
313#define SC_R_I2C_3 99U
314#define SC_R_I2C_4 100U
315#define SC_R_ADC_0 101U
316#define SC_R_ADC_1 102U
317#define SC_R_FTM_0 103U
318#define SC_R_FTM_1 104U
319#define SC_R_CAN_0 105U
320#define SC_R_CAN_1 106U
321#define SC_R_CAN_2 107U
322#define SC_R_DMA_1_CH0 108U
323#define SC_R_DMA_1_CH1 109U
324#define SC_R_DMA_1_CH2 110U
325#define SC_R_DMA_1_CH3 111U
326#define SC_R_DMA_1_CH4 112U
327#define SC_R_DMA_1_CH5 113U
328#define SC_R_DMA_1_CH6 114U
329#define SC_R_DMA_1_CH7 115U
330#define SC_R_DMA_1_CH8 116U
331#define SC_R_DMA_1_CH9 117U
332#define SC_R_DMA_1_CH10 118U
333#define SC_R_DMA_1_CH11 119U
334#define SC_R_DMA_1_CH12 120U
335#define SC_R_DMA_1_CH13 121U
336#define SC_R_DMA_1_CH14 122U
337#define SC_R_DMA_1_CH15 123U
338#define SC_R_DMA_1_CH16 124U
339#define SC_R_DMA_1_CH17 125U
340#define SC_R_DMA_1_CH18 126U
341#define SC_R_DMA_1_CH19 127U
342#define SC_R_DMA_1_CH20 128U
343#define SC_R_DMA_1_CH21 129U
344#define SC_R_DMA_1_CH22 130U
345#define SC_R_DMA_1_CH23 131U
346#define SC_R_DMA_1_CH24 132U
347#define SC_R_DMA_1_CH25 133U
348#define SC_R_DMA_1_CH26 134U
349#define SC_R_DMA_1_CH27 135U
350#define SC_R_DMA_1_CH28 136U
351#define SC_R_DMA_1_CH29 137U
352#define SC_R_DMA_1_CH30 138U
353#define SC_R_DMA_1_CH31 139U
354#define SC_R_V2X_PID0 140U
355#define SC_R_V2X_PID1 141U
356#define SC_R_V2X_PID2 142U
357#define SC_R_V2X_PID3 143U
358#define SC_R_GPU_0_PID0 144U
359#define SC_R_GPU_0_PID1 145U
360#define SC_R_GPU_0_PID2 146U
361#define SC_R_GPU_0_PID3 147U
362#define SC_R_GPU_1_PID0 148U
363#define SC_R_GPU_1_PID1 149U
364#define SC_R_GPU_1_PID2 150U
365#define SC_R_GPU_1_PID3 151U
366#define SC_R_PCIE_A 152U
367#define SC_R_SERDES_0 153U
368#define SC_R_MATCH_0 154U
369#define SC_R_MATCH_1 155U
370#define SC_R_MATCH_2 156U
371#define SC_R_MATCH_3 157U
372#define SC_R_MATCH_4 158U
373#define SC_R_MATCH_5 159U
374#define SC_R_MATCH_6 160U
375#define SC_R_MATCH_7 161U
376#define SC_R_MATCH_8 162U
377#define SC_R_MATCH_9 163U
378#define SC_R_MATCH_10 164U
379#define SC_R_MATCH_11 165U
380#define SC_R_MATCH_12 166U
381#define SC_R_MATCH_13 167U
382#define SC_R_MATCH_14 168U
383#define SC_R_PCIE_B 169U
384#define SC_R_SATA_0 170U
385#define SC_R_SERDES_1 171U
386#define SC_R_HSIO_GPIO 172U
387#define SC_R_MATCH_15 173U
388#define SC_R_MATCH_16 174U
389#define SC_R_MATCH_17 175U
390#define SC_R_MATCH_18 176U
391#define SC_R_MATCH_19 177U
392#define SC_R_MATCH_20 178U
393#define SC_R_MATCH_21 179U
394#define SC_R_MATCH_22 180U
395#define SC_R_MATCH_23 181U
396#define SC_R_MATCH_24 182U
397#define SC_R_MATCH_25 183U
398#define SC_R_MATCH_26 184U
399#define SC_R_MATCH_27 185U
400#define SC_R_MATCH_28 186U
401#define SC_R_LCD_0 187U
402#define SC_R_LCD_0_PWM_0 188U
403#define SC_R_LCD_0_I2C_0 189U
404#define SC_R_LCD_0_I2C_1 190U
405#define SC_R_PWM_0 191U
406#define SC_R_PWM_1 192U
407#define SC_R_PWM_2 193U
408#define SC_R_PWM_3 194U
409#define SC_R_PWM_4 195U
410#define SC_R_PWM_5 196U
411#define SC_R_PWM_6 197U
412#define SC_R_PWM_7 198U
413#define SC_R_GPIO_0 199U
414#define SC_R_GPIO_1 200U
415#define SC_R_GPIO_2 201U
416#define SC_R_GPIO_3 202U
417#define SC_R_GPIO_4 203U
418#define SC_R_GPIO_5 204U
419#define SC_R_GPIO_6 205U
420#define SC_R_GPIO_7 206U
421#define SC_R_GPT_0 207U
422#define SC_R_GPT_1 208U
423#define SC_R_GPT_2 209U
424#define SC_R_GPT_3 210U
425#define SC_R_GPT_4 211U
426#define SC_R_KPP 212U
427#define SC_R_MU_0A 213U
428#define SC_R_MU_1A 214U
429#define SC_R_MU_2A 215U
430#define SC_R_MU_3A 216U
431#define SC_R_MU_4A 217U
432#define SC_R_MU_5A 218U
433#define SC_R_MU_6A 219U
434#define SC_R_MU_7A 220U
435#define SC_R_MU_8A 221U
436#define SC_R_MU_9A 222U
437#define SC_R_MU_10A 223U
438#define SC_R_MU_11A 224U
439#define SC_R_MU_12A 225U
440#define SC_R_MU_13A 226U
441#define SC_R_MU_5B 227U
442#define SC_R_MU_6B 228U
443#define SC_R_MU_7B 229U
444#define SC_R_MU_8B 230U
445#define SC_R_MU_9B 231U
446#define SC_R_MU_10B 232U
447#define SC_R_MU_11B 233U
448#define SC_R_MU_12B 234U
449#define SC_R_MU_13B 235U
450#define SC_R_ROM_0 236U
451#define SC_R_FSPI_0 237U
452#define SC_R_FSPI_1 238U
453#define SC_R_IEE 239U
454#define SC_R_IEE_R0 240U
455#define SC_R_IEE_R1 241U
456#define SC_R_IEE_R2 242U
457#define SC_R_IEE_R3 243U
458#define SC_R_IEE_R4 244U
459#define SC_R_IEE_R5 245U
460#define SC_R_IEE_R6 246U
461#define SC_R_IEE_R7 247U
462#define SC_R_SDHC_0 248U
463#define SC_R_SDHC_1 249U
464#define SC_R_SDHC_2 250U
465#define SC_R_ENET_0 251U
466#define SC_R_ENET_1 252U
467#define SC_R_MLB_0 253U
468#define SC_R_DMA_2_CH0 254U
469#define SC_R_DMA_2_CH1 255U
470#define SC_R_DMA_2_CH2 256U
471#define SC_R_DMA_2_CH3 257U
472#define SC_R_DMA_2_CH4 258U
473#define SC_R_USB_0 259U
474#define SC_R_USB_1 260U
475#define SC_R_USB_0_PHY 261U
476#define SC_R_USB_2 262U
477#define SC_R_USB_2_PHY 263U
478#define SC_R_DTCP 264U
479#define SC_R_NAND 265U
480#define SC_R_LVDS_0 266U
481#define SC_R_LVDS_0_PWM_0 267U
482#define SC_R_LVDS_0_I2C_0 268U
483#define SC_R_LVDS_0_I2C_1 269U
484#define SC_R_LVDS_1 270U
485#define SC_R_LVDS_1_PWM_0 271U
486#define SC_R_LVDS_1_I2C_0 272U
487#define SC_R_LVDS_1_I2C_1 273U
488#define SC_R_LVDS_2 274U
489#define SC_R_LVDS_2_PWM_0 275U
490#define SC_R_LVDS_2_I2C_0 276U
491#define SC_R_LVDS_2_I2C_1 277U
492#define SC_R_M4_0_PID0 278U
493#define SC_R_M4_0_PID1 279U
494#define SC_R_M4_0_PID2 280U
495#define SC_R_M4_0_PID3 281U
496#define SC_R_M4_0_PID4 282U
497#define SC_R_M4_0_RGPIO 283U
498#define SC_R_M4_0_SEMA42 284U
499#define SC_R_M4_0_TPM 285U
500#define SC_R_M4_0_PIT 286U
501#define SC_R_M4_0_UART 287U
502#define SC_R_M4_0_I2C 288U
503#define SC_R_M4_0_INTMUX 289U
504#define SC_R_ENET_0_A0 290U
505#define SC_R_ENET_0_A1 291U
506#define SC_R_M4_0_MU_0B 292U
507#define SC_R_M4_0_MU_0A0 293U
508#define SC_R_M4_0_MU_0A1 294U
509#define SC_R_M4_0_MU_0A2 295U
510#define SC_R_M4_0_MU_0A3 296U
511#define SC_R_M4_0_MU_1A 297U
512#define SC_R_M4_1_PID0 298U
513#define SC_R_M4_1_PID1 299U
514#define SC_R_M4_1_PID2 300U
515#define SC_R_M4_1_PID3 301U
516#define SC_R_M4_1_PID4 302U
517#define SC_R_M4_1_RGPIO 303U
518#define SC_R_M4_1_SEMA42 304U
519#define SC_R_M4_1_TPM 305U
520#define SC_R_M4_1_PIT 306U
521#define SC_R_M4_1_UART 307U
522#define SC_R_M4_1_I2C 308U
523#define SC_R_M4_1_INTMUX 309U
524#define SC_R_UNUSED17 310U
525#define SC_R_UNUSED18 311U
526#define SC_R_M4_1_MU_0B 312U
527#define SC_R_M4_1_MU_0A0 313U
528#define SC_R_M4_1_MU_0A1 314U
529#define SC_R_M4_1_MU_0A2 315U
530#define SC_R_M4_1_MU_0A3 316U
531#define SC_R_M4_1_MU_1A 317U
532#define SC_R_SAI_0 318U
533#define SC_R_SAI_1 319U
534#define SC_R_SAI_2 320U
535#define SC_R_IRQSTR_SCU2 321U
536#define SC_R_IRQSTR_DSP 322U
537#define SC_R_ELCDIF_PLL 323U
538#define SC_R_OCRAM 324U
539#define SC_R_AUDIO_PLL_0 325U
540#define SC_R_PI_0 326U
541#define SC_R_PI_0_PWM_0 327U
542#define SC_R_PI_0_PWM_1 328U
543#define SC_R_PI_0_I2C_0 329U
544#define SC_R_PI_0_PLL 330U
545#define SC_R_PI_1 331U
546#define SC_R_PI_1_PWM_0 332U
547#define SC_R_PI_1_PWM_1 333U
548#define SC_R_PI_1_I2C_0 334U
549#define SC_R_PI_1_PLL 335U
550#define SC_R_SC_PID0 336U
551#define SC_R_SC_PID1 337U
552#define SC_R_SC_PID2 338U
553#define SC_R_SC_PID3 339U
554#define SC_R_SC_PID4 340U
555#define SC_R_SC_SEMA42 341U
556#define SC_R_SC_TPM 342U
557#define SC_R_SC_PIT 343U
558#define SC_R_SC_UART 344U
559#define SC_R_SC_I2C 345U
560#define SC_R_SC_MU_0B 346U
561#define SC_R_SC_MU_0A0 347U
562#define SC_R_SC_MU_0A1 348U
563#define SC_R_SC_MU_0A2 349U
564#define SC_R_SC_MU_0A3 350U
565#define SC_R_SC_MU_1A 351U
566#define SC_R_SYSCNT_RD 352U
567#define SC_R_SYSCNT_CMP 353U
568#define SC_R_DEBUG 354U
569#define SC_R_SYSTEM 355U
570#define SC_R_SNVS 356U
571#define SC_R_OTP 357U
572#define SC_R_VPU_PID0 358U
573#define SC_R_VPU_PID1 359U
574#define SC_R_VPU_PID2 360U
575#define SC_R_VPU_PID3 361U
576#define SC_R_VPU_PID4 362U
577#define SC_R_VPU_PID5 363U
578#define SC_R_VPU_PID6 364U
579#define SC_R_VPU_PID7 365U
580#define SC_R_ENET_0_A2 366U
581#define SC_R_ENET_1_A0 367U
582#define SC_R_ENET_1_A1 368U
583#define SC_R_ENET_1_A2 369U
584#define SC_R_ENET_1_A3 370U
585#define SC_R_ENET_1_A4 371U
586#define SC_R_DMA_4_CH0 372U
587#define SC_R_DMA_4_CH1 373U
588#define SC_R_DMA_4_CH2 374U
589#define SC_R_DMA_4_CH3 375U
590#define SC_R_DMA_4_CH4 376U
591#define SC_R_ISI_CH0 377U
592#define SC_R_ISI_CH1 378U
593#define SC_R_ISI_CH2 379U
594#define SC_R_ISI_CH3 380U
595#define SC_R_ISI_CH4 381U
596#define SC_R_ISI_CH5 382U
597#define SC_R_ISI_CH6 383U
598#define SC_R_ISI_CH7 384U
599#define SC_R_MJPEG_DEC_S0 385U
600#define SC_R_MJPEG_DEC_S1 386U
601#define SC_R_MJPEG_DEC_S2 387U
602#define SC_R_MJPEG_DEC_S3 388U
603#define SC_R_MJPEG_ENC_S0 389U
604#define SC_R_MJPEG_ENC_S1 390U
605#define SC_R_MJPEG_ENC_S2 391U
606#define SC_R_MJPEG_ENC_S3 392U
607#define SC_R_MIPI_0 393U
608#define SC_R_MIPI_0_PWM_0 394U
609#define SC_R_MIPI_0_I2C_0 395U
610#define SC_R_MIPI_0_I2C_1 396U
611#define SC_R_MIPI_1 397U
612#define SC_R_MIPI_1_PWM_0 398U
613#define SC_R_MIPI_1_I2C_0 399U
614#define SC_R_MIPI_1_I2C_1 400U
615#define SC_R_CSI_0 401U
616#define SC_R_CSI_0_PWM_0 402U
617#define SC_R_CSI_0_I2C_0 403U
618#define SC_R_CSI_1 404U
619#define SC_R_CSI_1_PWM_0 405U
620#define SC_R_CSI_1_I2C_0 406U
621#define SC_R_HDMI 407U
622#define SC_R_HDMI_I2S 408U
623#define SC_R_HDMI_I2C_0 409U
624#define SC_R_HDMI_PLL_0 410U
625#define SC_R_HDMI_RX 411U
626#define SC_R_HDMI_RX_BYPASS 412U
627#define SC_R_HDMI_RX_I2C_0 413U
628#define SC_R_ASRC_0 414U
629#define SC_R_ESAI_0 415U
630#define SC_R_SPDIF_0 416U
631#define SC_R_SPDIF_1 417U
632#define SC_R_SAI_3 418U
633#define SC_R_SAI_4 419U
634#define SC_R_SAI_5 420U
635#define SC_R_GPT_5 421U
636#define SC_R_GPT_6 422U
637#define SC_R_GPT_7 423U
638#define SC_R_GPT_8 424U
639#define SC_R_GPT_9 425U
640#define SC_R_GPT_10 426U
641#define SC_R_DMA_2_CH5 427U
642#define SC_R_DMA_2_CH6 428U
643#define SC_R_DMA_2_CH7 429U
644#define SC_R_DMA_2_CH8 430U
645#define SC_R_DMA_2_CH9 431U
646#define SC_R_DMA_2_CH10 432U
647#define SC_R_DMA_2_CH11 433U
648#define SC_R_DMA_2_CH12 434U
649#define SC_R_DMA_2_CH13 435U
650#define SC_R_DMA_2_CH14 436U
651#define SC_R_DMA_2_CH15 437U
652#define SC_R_DMA_2_CH16 438U
653#define SC_R_DMA_2_CH17 439U
654#define SC_R_DMA_2_CH18 440U
655#define SC_R_DMA_2_CH19 441U
656#define SC_R_DMA_2_CH20 442U
657#define SC_R_DMA_2_CH21 443U
658#define SC_R_DMA_2_CH22 444U
659#define SC_R_DMA_2_CH23 445U
660#define SC_R_DMA_2_CH24 446U
661#define SC_R_DMA_2_CH25 447U
662#define SC_R_DMA_2_CH26 448U
663#define SC_R_DMA_2_CH27 449U
664#define SC_R_DMA_2_CH28 450U
665#define SC_R_DMA_2_CH29 451U
666#define SC_R_DMA_2_CH30 452U
667#define SC_R_DMA_2_CH31 453U
668#define SC_R_ASRC_1 454U
669#define SC_R_ESAI_1 455U
670#define SC_R_SAI_6 456U
671#define SC_R_SAI_7 457U
672#define SC_R_AMIX 458U
673#define SC_R_MQS_0 459U
674#define SC_R_DMA_3_CH0 460U
675#define SC_R_DMA_3_CH1 461U
676#define SC_R_DMA_3_CH2 462U
677#define SC_R_DMA_3_CH3 463U
678#define SC_R_DMA_3_CH4 464U
679#define SC_R_DMA_3_CH5 465U
680#define SC_R_DMA_3_CH6 466U
681#define SC_R_DMA_3_CH7 467U
682#define SC_R_DMA_3_CH8 468U
683#define SC_R_DMA_3_CH9 469U
684#define SC_R_DMA_3_CH10 470U
685#define SC_R_DMA_3_CH11 471U
686#define SC_R_DMA_3_CH12 472U
687#define SC_R_DMA_3_CH13 473U
688#define SC_R_DMA_3_CH14 474U
689#define SC_R_DMA_3_CH15 475U
690#define SC_R_DMA_3_CH16 476U
691#define SC_R_DMA_3_CH17 477U
692#define SC_R_DMA_3_CH18 478U
693#define SC_R_DMA_3_CH19 479U
694#define SC_R_DMA_3_CH20 480U
695#define SC_R_DMA_3_CH21 481U
696#define SC_R_DMA_3_CH22 482U
697#define SC_R_DMA_3_CH23 483U
698#define SC_R_DMA_3_CH24 484U
699#define SC_R_DMA_3_CH25 485U
700#define SC_R_DMA_3_CH26 486U
701#define SC_R_DMA_3_CH27 487U
702#define SC_R_DMA_3_CH28 488U
703#define SC_R_DMA_3_CH29 489U
704#define SC_R_DMA_3_CH30 490U
705#define SC_R_DMA_3_CH31 491U
706#define SC_R_AUDIO_PLL_1 492U
707#define SC_R_AUDIO_CLK_0 493U
708#define SC_R_AUDIO_CLK_1 494U
709#define SC_R_MCLK_OUT_0 495U
710#define SC_R_MCLK_OUT_1 496U
711#define SC_R_PMIC_0 497U
712#define SC_R_PMIC_1 498U
713#define SC_R_SECO 499U
714#define SC_R_CAAM_JR1 500U
715#define SC_R_CAAM_JR2 501U
716#define SC_R_CAAM_JR3 502U
717#define SC_R_SECO_MU_2 503U
718#define SC_R_SECO_MU_3 504U
719#define SC_R_SECO_MU_4 505U
720#define SC_R_HDMI_RX_PWM_0 506U
721#define SC_R_A35 507U
722#define SC_R_A35_0 508U
723#define SC_R_A35_1 509U
724#define SC_R_A35_2 510U
725#define SC_R_A35_3 511U
726#define SC_R_DSP 512U
727#define SC_R_DSP_RAM 513U
728#define SC_R_CAAM_JR1_OUT 514U
729#define SC_R_CAAM_JR2_OUT 515U
730#define SC_R_CAAM_JR3_OUT 516U
731#define SC_R_VPU_DEC_0 517U
732#define SC_R_VPU_ENC_0 518U
733#define SC_R_CAAM_JR0 519U
734#define SC_R_CAAM_JR0_OUT 520U
735#define SC_R_PMIC_2 521U
736#define SC_R_DBLOGIC 522U
737#define SC_R_HDMI_PLL_1 523U
738#define SC_R_BOARD_R0 524U
739#define SC_R_BOARD_R1 525U
740#define SC_R_BOARD_R2 526U
741#define SC_R_BOARD_R3 527U
742#define SC_R_BOARD_R4 528U
743#define SC_R_BOARD_R5 529U
744#define SC_R_BOARD_R6 530U
745#define SC_R_BOARD_R7 531U
746#define SC_R_MJPEG_DEC_MP 532U
747#define SC_R_MJPEG_ENC_MP 533U
748#define SC_R_VPU_TS_0 534U
749#define SC_R_VPU_MU_0 535U
750#define SC_R_VPU_MU_1 536U
751#define SC_R_VPU_MU_2 537U
752#define SC_R_VPU_MU_3 538U
753#define SC_R_VPU_ENC_1 539U
754#define SC_R_VPU 540U
755#define SC_R_DMA_5_CH0 541U
756#define SC_R_DMA_5_CH1 542U
757#define SC_R_DMA_5_CH2 543U
758#define SC_R_DMA_5_CH3 544U
759#define SC_R_ATTESTATION 545U
760#define SC_R_LAST 546U
761#define SC_R_ALL ((sc_rsrc_t) UINT16_MAX) /*!< All resources */
762/*@}*/
763
764/*!
765 * Define for ATF/Linux. Not used by SCFW. Not a valid parameter
766 * for any SCFW API calls!
767 */
768#define SC_R_NONE 0xFFF0U
769
770/* NOTE - please add by replacing some of the UNUSED from above! */
771
772/*!
773 * Defines for sc_ctrl_t.
774 */
775#define SC_C_TEMP 0U
776#define SC_C_TEMP_HI 1U
777#define SC_C_TEMP_LOW 2U
778#define SC_C_PXL_LINK_MST1_ADDR 3U
779#define SC_C_PXL_LINK_MST2_ADDR 4U
780#define SC_C_PXL_LINK_MST_ENB 5U
781#define SC_C_PXL_LINK_MST1_ENB 6U
782#define SC_C_PXL_LINK_MST2_ENB 7U
783#define SC_C_PXL_LINK_SLV1_ADDR 8U
784#define SC_C_PXL_LINK_SLV2_ADDR 9U
785#define SC_C_PXL_LINK_MST_VLD 10U
786#define SC_C_PXL_LINK_MST1_VLD 11U
787#define SC_C_PXL_LINK_MST2_VLD 12U
788#define SC_C_SINGLE_MODE 13U
789#define SC_C_ID 14U
790#define SC_C_PXL_CLK_POLARITY 15U
791#define SC_C_LINESTATE 16U
792#define SC_C_PCIE_G_RST 17U
793#define SC_C_PCIE_BUTTON_RST 18U
794#define SC_C_PCIE_PERST 19U
795#define SC_C_PHY_RESET 20U
796#define SC_C_PXL_LINK_RATE_CORRECTION 21U
797#define SC_C_PANIC 22U
798#define SC_C_PRIORITY_GROUP 23U
799#define SC_C_TXCLK 24U
800#define SC_C_CLKDIV 25U
801#define SC_C_DISABLE_50 26U
802#define SC_C_DISABLE_125 27U
803#define SC_C_SEL_125 28U
804#define SC_C_MODE 29U
805#define SC_C_SYNC_CTRL0 30U
806#define SC_C_KACHUNK_CNT 31U
807#define SC_C_KACHUNK_SEL 32U
808#define SC_C_SYNC_CTRL1 33U
809#define SC_C_DPI_RESET 34U
810#define SC_C_MIPI_RESET 35U
811#define SC_C_DUAL_MODE 36U
812#define SC_C_VOLTAGE 37U
813#define SC_C_PXL_LINK_SEL 38U
814#define SC_C_OFS_SEL 39U
815#define SC_C_OFS_AUDIO 40U
816#define SC_C_OFS_PERIPH 41U
817#define SC_C_OFS_IRQ 42U
818#define SC_C_RST0 43U
819#define SC_C_RST1 44U
820#define SC_C_SEL0 45U
821#define SC_C_CALIB0 46U
822#define SC_C_CALIB1 47U
823#define SC_C_CALIB2 48U
824#define SC_C_IPG_DEBUG 49U
825#define SC_C_IPG_DOZE 50U
826#define SC_C_IPG_WAIT 51U
827#define SC_C_IPG_STOP 52U
828#define SC_C_IPG_STOP_MODE 53U
829#define SC_C_IPG_STOP_ACK 54U
830#define SC_C_SYNC_CTRL 55U
831#define SC_C_OFS_AUDIO_ALT 56U
832#define SC_C_DSP_BYP 57U
833#define SC_C_LAST 58U
834
835#define SC_P_ALL ((sc_pad_t) UINT16_MAX) /*!< All pads */
836
837/* Types */
838
839/*!
840 * This type is used to store a boolean
841 */
842typedef uint8_t sc_bool_t;
843
844/*!
845 * This type is used to store a system (full-size) address.
846 */
847typedef uint64_t sc_faddr_t;
848
849/*!
850 * This type is used to indicate error response for most functions.
851 */
852typedef uint8_t sc_err_t;
853
854/*!
855 * This type is used to indicate a resource. Resources include peripherals
856 * and bus masters (but not memory regions). Note items from list should
857 * never be changed or removed (only added to at the end of the list).
858 */
859typedef uint16_t sc_rsrc_t;
860
861/*!
862 * This type is used to indicate a control.
863 */
864typedef uint32_t sc_ctrl_t;
865
866/*!
867 * This type is used to indicate a pad. Valid values are SoC specific.
868 *
869 * Refer to the SoC [Pad List](@ref PADS) for valid pad values.
870 */
871typedef uint16_t sc_pad_t;
872
873/* Extra documentation of standard types */
874
875#ifdef DOXYGEN
876 /*!
877 * Type used to declare an 8-bit integer.
878 */
879 typedef __INT8_TYPE__ int8_t;
880
881 /*!
882 * Type used to declare a 16-bit integer.
883 */
884 typedef __INT16_TYPE__ int16_t;
885
886 /*!
887 * Type used to declare a 32-bit integer.
888 */
889 typedef __INT32_TYPE__ int32_t;
890
891 /*!
892 * Type used to declare a 64-bit integer.
893 */
894 typedef __INT64_TYPE__ int64_t;
895
896 /*!
897 * Type used to declare an 8-bit unsigned integer.
898 */
899 typedef __UINT8_TYPE__ uint8_t;
900
901 /*!
902 * Type used to declare a 16-bit unsigned integer.
903 */
904 typedef __UINT16_TYPE__ uint16_t;
905
906 /*!
907 * Type used to declare a 32-bit unsigned integer.
908 */
909 typedef __UINT32_TYPE__ uint32_t;
910
911 /*!
912 * Type used to declare a 64-bit unsigned integer.
913 */
914 typedef __UINT64_TYPE__ uint64_t;
915#endif
916
917#endif /* SC_TYPES_H */
918
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