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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX3/MIMX8QX3_cm4.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX3/MIMX8QX3_cm4.h
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@@ -0,0 +1,144413 @@
1/*
2** ###################################################################
3** Processor: MIMX8QX3AVLFZ
4** Compilers: GNU C Compiler
5** IAR ANSI C/C++ Compiler for ARM
6** Keil ARM C/C++ Compiler
7**
8** Reference manual: IMX8DQXPRM, Rev. E, 6/2019
9** Version: rev. 4.0, 2020-06-19
10** Build: b200825
11**
12** Abstract:
13** CMSIS Peripheral Access Layer for MIMX8QX3_cm4
14**
15** Copyright 1997-2016 Freescale Semiconductor, Inc.
16** Copyright 2016-2020 NXP
17** All rights reserved.
18**
19** SPDX-License-Identifier: BSD-3-Clause
20**
21** http: www.nxp.com
22** mail: [email protected]
23**
24** Revisions:
25** - rev. 1.0 (2016-06-02)
26** Initial version.
27** - rev. 2.0 (2017-08-23)
28** RevA Header EAR
29** - rev. 3.0 (2018-08-22)
30** RevB Header EAR
31** - rev. 4.0 (2020-06-19)
32** RevC Header RFP
33**
34** ###################################################################
35*/
36
37/*!
38 * @file MIMX8QX3_cm4.h
39 * @version 4.0
40 * @date 2020-06-19
41 * @brief CMSIS Peripheral Access Layer for MIMX8QX3_cm4
42 *
43 * CMSIS Peripheral Access Layer for MIMX8QX3_cm4
44 */
45
46#ifndef _MIMX8QX3_CM4_H_
47#define _MIMX8QX3_CM4_H_ /**< Symbol preventing repeated inclusion */
48
49/** Memory map major version (memory maps with equal major version number are
50 * compatible) */
51#define MCU_MEM_MAP_VERSION 0x0400U
52/** Memory map minor version */
53#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
54
55
56/* ----------------------------------------------------------------------------
57 -- Interrupt vector numbers
58 ---------------------------------------------------------------------------- */
59
60/*!
61 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
62 * @{
63 */
64
65/** Interrupt Number Definitions */
66#define NUMBER_OF_INT_VECTORS 611 /**< Number of interrupts in the Vector table */
67
68typedef enum IRQn {
69 /* Auxiliary constants */
70 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
71
72 /* Core interrupts */
73 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
74 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
75 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
76 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
77 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
78 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
79 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
80 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
81 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
82
83 /* Device specific interrupts */
84 Reserved16_IRQn = 0, /**< Reserved */
85 Reserved17_IRQn = 1, /**< Reserved */
86 Reserved18_IRQn = 2, /**< Reserved */
87 Reserved19_IRQn = 3, /**< Reserved */
88 Reserved20_IRQn = 4, /**< Reserved */
89 M4_MCM_IRQn = 5, /**< MCM IRQ */
90 Reserved22_IRQn = 6, /**< Reserved */
91 Reserved23_IRQn = 7, /**< Reserved */
92 Reserved24_IRQn = 8, /**< Reserved */
93 Reserved25_IRQn = 9, /**< Reserved */
94 Reserved26_IRQn = 10, /**< Reserved */
95 Reserved27_IRQn = 11, /**< Reserved */
96 Reserved28_IRQn = 12, /**< Reserved */
97 Reserved29_IRQn = 13, /**< Reserved */
98 Reserved30_IRQn = 14, /**< Reserved */
99 Reserved31_IRQn = 15, /**< Reserved */
100 Reserved32_IRQn = 16, /**< Reserved */
101 Reserved33_IRQn = 17, /**< Reserved */
102 Reserved34_IRQn = 18, /**< Reserved */
103 M4_TPM_IRQn = 19, /**< Timer PWM Module */
104 Reserved36_IRQn = 20, /**< Reserved */
105 Reserved37_IRQn = 21, /**< Reserved */
106 M4_LPIT_IRQn = 22, /**< Low-Power Periodic Interrupt Timer */
107 Reserved39_IRQn = 23, /**< Reserved */
108 Reserved40_IRQn = 24, /**< Reserved */
109 M4_LPUART_IRQn = 25, /**< Low Power UART */
110 Reserved42_IRQn = 26, /**< Reserved */
111 M4_LPI2C_IRQn = 27, /**< Low-Power I2C - Logical OR of master and slave interrupts */
112 Reserved44_IRQn = 28, /**< Reserved */
113 M4_MU0_B0_IRQn = 29, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 0, Logical OR of all general-purpose, TX, and RX interrupts */
114 Reserved46_IRQn = 30, /**< Reserved */
115 Reserved47_IRQn = 31, /**< Reserved */
116 IRQSTEER_0_IRQn = 32, /**< External interrupt 0 */
117 IRQSTEER_1_IRQn = 33, /**< External interrupt 1 */
118 IRQSTEER_2_IRQn = 34, /**< External interrupt 2 */
119 IRQSTEER_3_IRQn = 35, /**< External interrupt 3 */
120 IRQSTEER_4_IRQn = 36, /**< External interrupt 4 */
121 IRQSTEER_5_IRQn = 37, /**< External interrupt 5 */
122 IRQSTEER_6_IRQn = 38, /**< External interrupt 6 */
123 IRQSTEER_7_IRQn = 39, /**< External interrupt 7 */
124 Reserved56_IRQn = 40, /**< Reserved */
125 Reserved57_IRQn = 41, /**< Reserved */
126 Reserved58_IRQn = 42, /**< Reserved */
127 Reserved59_IRQn = 43, /**< Reserved */
128 M4_MU0_B1_IRQn = 44, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 1, Logical OR of all general-purpose, TX, and RX interrupts */
129 M4_MU0_B2_IRQn = 45, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 2, Logical OR of all general-purpose, TX, and RX interrupts */
130 M4_MU0_B3_IRQn = 46, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 3, Logical OR of all general-purpose, TX, and RX interrupts */
131 Reserved63_IRQn = 47, /**< Reserved */
132 Reserved64_IRQn = 48, /**< Reserved */
133 M4_MU1_A_IRQn = 49, /**< Messaging Unit 1 (IPC with System Controller) - Side A (MCU), Logical OR of all general-purpose, TX, and RX interrupts */
134 M4_SW_IRQn = 50, /**< Software interrupt (asserted/cleared via NVIC registers, INTISR[50] input tied low) */
135 A35_NINTERRIRQ_IRQn = 83, /**< Shared Int Source nINTERRIRQ from A35 Sub-System */
136 A35_NEXTERRIRQ_IRQn = 84, /**< Shared Int Source nEXTERRIRQ from A35 Sub-System */
137 M4_INT_OUT0_IRQn = 99, /**< Shared Int Source INT_OUT[0] from M4 Sub-System */
138 M4_INT_OUT1_IRQn = 100, /**< Shared Int Source INT_OUT[1] from M4 Sub-System */
139 M4_INT_OUT2_IRQn = 101, /**< Shared Int Source INT_OUT[2] from M4 Sub-System */
140 M4_INT_OUT3_IRQn = 102, /**< Shared Int Source INT_OUT[3] from M4 Sub-System */
141 M4_INT_OUT4_IRQn = 103, /**< Shared Int Source INT_OUT[4] from M4 Sub-System */
142 M4_INT_OUT5_IRQn = 104, /**< Shared Int Source INT_OUT[5] from M4 Sub-System */
143 M4_INT_OUT6_IRQn = 105, /**< Shared Int Source INT_OUT[6] from M4 Sub-System */
144 M4_INT_OUT7_IRQn = 106, /**< Shared Int Source INT_OUT[7] from M4 Sub-System */
145 DISPLAY0_INT_OUT0_IRQn = 123, /**< Shared Int Source INT_OUT[0] from Display0 Sub-System */
146 DISPLAY0_INT_OUT1_IRQn = 124, /**< Shared Int Source INT_OUT[1] from Display0 Sub-System */
147 DISPLAY0_INT_OUT2_IRQn = 125, /**< Shared Int Source INT_OUT[2] from Display0 Sub-System */
148 DISPLAY0_INT_OUT3_IRQn = 126, /**< Shared Int Source INT_OUT[3] from Display0 Sub-System */
149 DISPLAY0_INT_OUT4_IRQn = 127, /**< Shared Int Source INT_OUT[4] from Display0 Sub-System */
150 DISPLAY0_INT_OUT5_IRQn = 128, /**< Shared Int Source INT_OUT[5] from Display0 Sub-System */
151 DISPLAY0_INT_OUT6_IRQn = 129, /**< Shared Int Source INT_OUT[6] from Display0 Sub-System */
152 DISPLAY0_INT_OUT7_IRQn = 130, /**< Shared Int Source INT_OUT[7] from Display0 Sub-System */
153 DISPLAY0_RESERVED_IRQn = 131, /**< Shared Int Source Reserved from Display0 Sub-System */
154 DISPLAY0_INT_OUT9_IRQn = 132, /**< Shared Int Source INT_OUT[9] from Display0 Sub-System */
155 DISPLAY0_INT_OUT10_IRQn = 133, /**< Shared Int Source INT_OUT[10] from Display0 Sub-System */
156 DISPLAY0_INT_OUT11_IRQn = 134, /**< Shared Int Source INT_OUT[11] from Display0 Sub-System */
157 DISPLAY0_INT_OUT12_IRQn = 135, /**< Shared Int Source INT_OUT[12] from Display0 Sub-System */
158 MIPI_DSI0_INT_OUT_IRQn = 142, /**< Shared Int Source INT_OUT from MIPI_DSI0 Sub-System */
159 MIPI_DSI1_INT_OUT_IRQn = 143, /**< Shared Int Source INT_OUT from MIPI_DSI1 Sub-System */
160 LCD_MOD_INT_IRQn = 145, /**< Shared Int Source INT_OUT from ADMA Sub-System */
161 LCD_PWM_INT_IRQn = 146, /**< Shared Int Source INT_OUT from ADMA Sub-System */
162 GPU0_XAQ2_INTR_IRQn = 147, /**< Shared Int Source xaq2_intr from GPU0 Sub-System */
163 ADMA_EDMA2_INT_IRQn = 149, /**< Shared Int Source eDMA2_INT from ADMA Sub-System */
164 ADMA_EDMA2_ERR_INT_IRQn = 150, /**< Shared Int Source eDMA2_ERR_INT from ADMA Sub-System */
165 ADMA_EDMA3_INT_IRQn = 151, /**< Shared Int Source eDMA3_INT from ADMA Sub-System */
166 ADMA_EDMA3_ERR_INT_IRQn = 152, /**< Shared Int Source eDMA3_ERR_INT from ADMA Sub-System */
167 LSIO_GPT0_INT_IRQn = 163, /**< Shared Int Source GPT0_INT from LSIO Sub-System */
168 LSIO_GPT1_INT_IRQn = 164, /**< Shared Int Source GPT1_INT from LSIO Sub-System */
169 LSIO_GPT2_INT_IRQn = 165, /**< Shared Int Source GPT2_INT from LSIO Sub-System */
170 LSIO_GPT3_INT_IRQn = 166, /**< Shared Int Source GPT3_INT from LSIO Sub-System */
171 LSIO_GPT4_INT_IRQn = 167, /**< Shared Int Source GPT4_INT from LSIO Sub-System */
172 LSIO_KPP_INT_IRQn = 168, /**< Shared Int Source KPP_INT from LSIO Sub-System */
173 LSIO_OCTASPI0_INT_IRQn = 175, /**< Shared Int Source OctaSPI0_INT from LSIO Sub-System */
174 LSIO_OCTASPI1_INT_IRQn = 176, /**< Shared Int Source OctaSPI1_INT from LSIO Sub-System */
175 LSIO_PWM0_INT_IRQn = 177, /**< Shared Int Source PWM0_INT from LSIO Sub-System */
176 LSIO_PWM1_INT_IRQn = 178, /**< Shared Int Source PWM1_INT from LSIO Sub-System */
177 LSIO_PWM2_INT_IRQn = 179, /**< Shared Int Source PWM2_INT from LSIO Sub-System */
178 LSIO_PWM3_INT_IRQn = 180, /**< Shared Int Source PWM3_INT from LSIO Sub-System */
179 LSIO_PWM4_INT_IRQn = 181, /**< Shared Int Source PWM4_INT from LSIO Sub-System */
180 LSIO_PWM5_INT_IRQn = 182, /**< Shared Int Source PWM5_INT from LSIO Sub-System */
181 LSIO_PWM6_INT_IRQn = 183, /**< Shared Int Source PWM6_INT from LSIO Sub-System */
182 LSIO_PWM7_INT_IRQn = 184, /**< Shared Int Source PWM7_INT from LSIO Sub-System */
183 HSIO_PCIEB_MSI_CTRL_INT_IRQn = 185, /**< Shared Int Source PCIeB_MSI_CTRL_INT from HSIO Sub-System */
184 HSIO_PCIEB_CLK_REQ_INT_IRQn = 186, /**< Shared Int Source PCIeB_CLK_REQ_INT from HSIO Sub-System */
185 HSIO_PCIEB_DMA_INT_IRQn = 187, /**< Shared Int Source PCIeB_DMA_INT from HSIO Sub-System */
186 HSIO_PCIEB_INT_D_IRQn = 188, /**< Shared Int Source PCIeB_INT_D from HSIO Sub-System */
187 HSIO_PCIEB_INT_C_IRQn = 189, /**< Shared Int Source PCIeB_INT_C from HSIO Sub-System */
188 HSIO_PCIEB_INT_B_IRQn = 190, /**< Shared Int Source PCIeB_INT_B from HSIO Sub-System */
189 HSIO_PCIEB_INT_A_IRQn = 191, /**< Shared Int Source PCIeB_INT_A from HSIO Sub-System */
190 HSIO_PCIEB_SMLH_REQ_RST_IRQn = 192, /**< Shared Int Source PCIeB_SMLH_REQ_RST from HSIO Sub-System */
191 HSIO_PCIEB_GPIO_WAKEUP0_IRQn = 193, /**< Shared Int Source PCIeB_GPIO_WAKEUP[0] from HSIO Sub-System */
192 HSIO_PCIEB_GPIO_WAKEUP1_IRQn = 194, /**< Shared Int Source PCIeB_GPIO_WAKEUP[1] from HSIO Sub-System */
193 SCU_INT_OUT0_IRQn = 195, /**< Shared Int Source INT_OUT[0] from SCU Sub-System */
194 SCU_INT_OUT1_IRQn = 196, /**< Shared Int Source INT_OUT[1] from SCU Sub-System */
195 SCU_INT_OUT2_IRQn = 197, /**< Shared Int Source INT_OUT[2] from SCU Sub-System */
196 SCU_INT_OUT3_IRQn = 198, /**< Shared Int Source INT_OUT[3] from SCU Sub-System */
197 SCU_INT_OUT4_IRQn = 199, /**< Shared Int Source INT_OUT[4] from SCU Sub-System */
198 SCU_INT_OUT5_IRQn = 200, /**< Shared Int Source INT_OUT[5] from SCU Sub-System */
199 SCU_INT_OUT6_IRQn = 201, /**< Shared Int Source INT_OUT[6] from SCU Sub-System */
200 SCU_INT_OUT7_IRQn = 202, /**< Shared Int Source INT_OUT[7] from SCU Sub-System */
201 SCU_SYS_COUNT_INT0_IRQn = 203, /**< Shared Int Source SYS_COUNT_INT0 from SCU Sub-System */
202 SCU_SYS_COUNT_INT1_IRQn = 204, /**< Shared Int Source SYS_COUNT_INT1 from SCU Sub-System */
203 SCU_SYS_COUNT_INT2_IRQn = 205, /**< Shared Int Source SYS_COUNT_INT2 from SCU Sub-System */
204 SCU_SYS_COUNT_INT3_IRQn = 206, /**< Shared Int Source SYS_COUNT_INT3 from SCU Sub-System */
205 DRC_ECC_CORRECT_INT_IRQn = 211, /**< Shared Int Source ECC_CORRECT_INT from DRC Sub-System */
206 DRC_ECC_NCORRECT_INT_IRQn = 212, /**< Shared Int Source ECC_NCORRECT_INT from DRC Sub-System */
207 DRC_SBR_DONE_INT_IRQn = 213, /**< Shared Int Source SBR_DONE_INT from DRC Sub-System */
208 DRC_PERF_CNT_INT_IRQn = 214, /**< Shared Int Source PERF_CNT_INT from DRC Sub-System */
209 LSIO_GPIO_INT0_IRQn = 219, /**< Shared Int Source GPIO_INT[0] from LSIO Sub-System */
210 LSIO_GPIO_INT1_IRQn = 220, /**< Shared Int Source GPIO_INT[1] from LSIO Sub-System */
211 LSIO_GPIO_INT2_IRQn = 221, /**< Shared Int Source GPIO_INT[2] from LSIO Sub-System */
212 LSIO_GPIO_INT3_IRQn = 222, /**< Shared Int Source GPIO_INT[3] from LSIO Sub-System */
213 LSIO_GPIO_INT4_IRQn = 223, /**< Shared Int Source GPIO_INT[4] from LSIO Sub-System */
214 LSIO_GPIO_INT5_IRQn = 224, /**< Shared Int Source GPIO_INT[5] from LSIO Sub-System */
215 LSIO_GPIO_INT6_IRQn = 225, /**< Shared Int Source GPIO_INT[6] from LSIO Sub-System */
216 LSIO_GPIO_INT7_IRQn = 226, /**< Shared Int Source GPIO_INT[7] from LSIO Sub-System */
217 LSIO_MU0_INT_IRQn = 259, /**< Shared Int Source MU0_INT from LSIO Sub-System */
218 LSIO_MU1_INT_IRQn = 260, /**< Shared Int Source MU1_INT from LSIO Sub-System */
219 LSIO_MU2_INT_IRQn = 261, /**< Shared Int Source MU2_INT from LSIO Sub-System */
220 LSIO_MU3_INT_IRQn = 262, /**< Shared Int Source MU3_INT from LSIO Sub-System */
221 LSIO_MU4_INT_IRQn = 263, /**< Shared Int Source MU4_INT from LSIO Sub-System */
222 LSIO_MU5_INT_A_IRQn = 267, /**< Shared Int Source MU5_INT_A from LSIO Sub-System */
223 LSIO_MU6_INT_A_IRQn = 268, /**< Shared Int Source MU6_INT_A from LSIO Sub-System */
224 LSIO_MU7_INT_A_IRQn = 269, /**< Shared Int Source MU7_INT_A from LSIO Sub-System */
225 LSIO_MU8_INT_A_IRQn = 270, /**< Shared Int Source MU8_INT_A from LSIO Sub-System */
226 LSIO_MU9_INT_A_IRQn = 271, /**< Shared Int Source MU9_INT_A from LSIO Sub-System */
227 LSIO_MU10_INT_A_IRQn = 272, /**< Shared Int Source MU10_INT_A from LSIO Sub-System */
228 LSIO_MU11_INT_A_IRQn = 273, /**< Shared Int Source MU11_INT_A from LSIO Sub-System */
229 LSIO_MU12_INT_A_IRQn = 274, /**< Shared Int Source MU12_INT_A from LSIO Sub-System */
230 LSIO_MU13_INT_A_IRQn = 275, /**< Shared Int Source MU13_INT_A from LSIO Sub-System */
231 LSIO_MU5_INT_B_IRQn = 283, /**< Shared Int Source MU5_INT_B from LSIO Sub-System */
232 LSIO_MU6_INT_B_IRQn = 284, /**< Shared Int Source MU6_INT_B from LSIO Sub-System */
233 LSIO_MU7_INT_B_IRQn = 285, /**< Shared Int Source MU7_INT_B from LSIO Sub-System */
234 LSIO_MU8_INT_B_IRQn = 286, /**< Shared Int Source MU8_INT_B from LSIO Sub-System */
235 LSIO_MU9_INT_B_IRQn = 287, /**< Shared Int Source MU9_INT_B from LSIO Sub-System */
236 LSIO_MU10_INT_B_IRQn = 288, /**< Shared Int Source MU10_INT_B from LSIO Sub-System */
237 LSIO_MU11_INT_B_IRQn = 289, /**< Shared Int Source MU11_INT_B from LSIO Sub-System */
238 LSIO_MU12_INT_B_IRQn = 290, /**< Shared Int Source MU12_INT_B from LSIO Sub-System */
239 LSIO_MU13_INT_B_IRQn = 291, /**< Shared Int Source MU13_INT_B from LSIO Sub-System */
240 ADMA_SPI0_INT_IRQn = 299, /**< Shared Int Source SPI0_INT from ADMA Sub-System */
241 ADMA_SPI1_INT_IRQn = 300, /**< Shared Int Source SPI1_INT from ADMA Sub-System */
242 ADMA_SPI2_INT_IRQn = 301, /**< Shared Int Source SPI2_INT from ADMA Sub-System */
243 ADMA_SPI3_INT_IRQn = 302, /**< Shared Int Source SPI3_INT from ADMA Sub-System */
244 ADMA_I2C0_INT_IRQn = 303, /**< Shared Int Source I2C0_INT from ADMA Sub-System */
245 ADMA_I2C1_INT_IRQn = 304, /**< Shared Int Source I2C1_INT from ADMA Sub-System */
246 ADMA_I2C2_INT_IRQn = 305, /**< Shared Int Source I2C2_INT from ADMA Sub-System */
247 ADMA_I2C3_INT_IRQn = 306, /**< Shared Int Source I2C3_INT from ADMA Sub-System */
248 ADMA_UART0_INT_IRQn = 308, /**< Shared Int Source UART0_INT from ADMA Sub-System */
249 ADMA_UART1_INT_IRQn = 309, /**< Shared Int Source UART1_INT from ADMA Sub-System */
250 ADMA_UART2_INT_IRQn = 310, /**< Shared Int Source UART2_INT from ADMA Sub-System */
251 ADMA_UART3_INT_IRQn = 311, /**< Shared Int Source UART3_INT from ADMA Sub-System */
252 CONNECTIVITY_USDHC0_INT_IRQn = 315, /**< Shared Int Source uSDHC0_INT from Connectivity Sub-System */
253 CONNECTIVITY_USDHC1_INT_IRQn = 316, /**< Shared Int Source uSDHC1_INT from Connectivity Sub-System */
254 CONNECTIVITY_USDHC2_INT_IRQn = 317, /**< Shared Int Source uSDHC2_INT from Connectivity Sub-System */
255 ADMA_FLEXCAN0_INT_IRQn = 318, /**< Shared Int Source FlexCAN0_INT from ADMA Sub-System */
256 ADMA_FLEXCAN1_INT_IRQn = 319, /**< Shared Int Source FlexCAN1_INT from ADMA Sub-System */
257 ADMA_FLEXCAN2_INT_IRQn = 320, /**< Shared Int Source FlexCAN2_INT from ADMA Sub-System */
258 ADMA_FTM0_INT_IRQn = 321, /**< Shared Int Source FTM0_INT from ADMA Sub-System */
259 ADMA_FTM1_INT_IRQn = 322, /**< Shared Int Source FTM1_INT from ADMA Sub-System */
260 ADMA_ADC0_INT_IRQn = 323, /**< Shared Int Source ADC0_INT from ADMA Sub-System */
261 ADMA_EXTERNAL_DMA_INT_0_IRQn = 325, /**< Shared Int Source EXTERNAL_DMA_INT_0 from ADMA Sub-System */
262 ADMA_EXTERNAL_DMA_INT_1_IRQn = 326, /**< Shared Int Source EXTERNAL_DMA_INT_1 from ADMA Sub-System */
263 ADMA_EXTERNAL_DMA_INT_2_IRQn = 327, /**< Shared Int Source EXTERNAL_DMA_INT_2 from ADMA Sub-System */
264 ADMA_EXTERNAL_DMA_INT_3_IRQn = 328, /**< Shared Int Source EXTERNAL_DMA_INT_3 from ADMA Sub-System */
265 ADMA_EXTERNAL_DMA_INT_4_IRQn = 329, /**< Shared Int Source EXTERNAL_DMA_INT_4 from ADMA Sub-System */
266 ADMA_EXTERNAL_DMA_INT_5_IRQn = 330, /**< Shared Int Source EXTERNAL_DMA_INT_5 from ADMA Sub-System */
267 CONNECTIVITY_ENET0_FRAME1_INT_IRQn = 339, /**< Shared Int Source ENET0_FRAME1_INT from Connectivity Sub-System */
268 CONNECTIVITY_ENET0_FRAME2_INT_IRQn = 340, /**< Shared Int Source ENET0_FRAME2_INT from Connectivity Sub-System */
269 CONNECTIVITY_ENET0_FRAME0_EVENT_INT_IRQn = 341, /**< Shared Int Source ENET0_FRAME0_EVENT_INT from Connectivity Sub-System */
270 CONNECTIVITY_ENET0_TIMER_INT_IRQn = 342, /**< Shared Int Source ENET0_TIMER_INT from Connectivity Sub-System */
271 CONNECTIVITY_ENET1_FRAME1_INT_IRQn = 343, /**< Shared Int Source ENET1_FRAME1_INT from Connectivity Sub-System */
272 CONNECTIVITY_ENET1_FRAME2_INT_IRQn = 344, /**< Shared Int Source ENET1_FRAME2_INT from Connectivity Sub-System */
273 CONNECTIVITY_ENET1_FRAME0_EVENT_INT_IRQn = 345, /**< Shared Int Source ENET1_FRAME0_EVENT_INT from Connectivity Sub-System */
274 CONNECTIVITY_ENET1_TIMER_INT_IRQn = 346, /**< Shared Int Source ENET1_TIMER_INT from Connectivity Sub-System */
275 CONNECTIVITY_DTCP_INT_IRQn = 347, /**< Shared Int Source DTCP_INT from Connectivity Sub-System */
276 CONNECTIVITY_MLB_INT_IRQn = 348, /**< Shared Int Source MLB_INT from Connectivity Sub-System */
277 CONNECTIVITY_MLB_AHB_INT_IRQn = 349, /**< Shared Int Source MLB_AHB_INT from Connectivity Sub-System */
278 CONNECTIVITY_USB_OTG_INT_IRQn = 350, /**< Shared Int Source USB_OTG_INT from Connectivity Sub-System */
279 CONNECTIVITY_USB_HOST_INT_IRQn = 351, /**< Shared Int Source USB_HOST_INT from Connectivity Sub-System */
280 CONNECTIVITY_UTMI_INT_IRQn = 352, /**< Shared Int Source UTMI_INT from Connectivity Sub-System */
281 CONNECTIVITY_WAKEUP_INT_IRQn = 353, /**< Shared Int Source WAKEUP_INT from Connectivity Sub-System */
282 CONNECTIVITY_USB3_INT_IRQn = 354, /**< Shared Int Source USB3_INT from Connectivity Sub-System */
283 CONNECTIVITY_ND_FLASH_BCH_INT_IRQn = 355, /**< Shared Int Source ND_FLASH_BCH_INT from Connectivity Sub-System */
284 CONNECTIVITY_ND_FLASH_GPMI_INT_IRQn = 356, /**< Shared Int Source ND_FLASH_GPMI_INT from Connectivity Sub-System */
285 CONNECTIVITY_APBHDMA_IRQn = 357, /**< Shared Int Source APBHDMA from Connectivity Sub-System */
286 CONNECTIVITY_DMA_INT_IRQn = 358, /**< Shared Int Source DMA_INT from Connectivity Sub-System */
287 CONNECTIVITY_DMA_ERR_INT_IRQn = 359, /**< Shared Int Source DMA_ERR_INT from Connectivity Sub-System */
288 IMAGING_MSI_INT_IRQn = 371, /**< Shared Int Source MSI_INT from Imaging Sub-System */
289 IMAGING_PDMA_STREAM0_INT_IRQn = 380, /**< Shared Int Source PDMA_STREAM0_INT from Imaging Sub-System */
290 IMAGING_PDMA_STREAM1_INT_IRQn = 381, /**< Shared Int Source PDMA_STREAM1_INT from Imaging Sub-System */
291 IMAGING_PDMA_STREAM2_INT_IRQn = 382, /**< Shared Int Source PDMA_STREAM2_INT from Imaging Sub-System */
292 IMAGING_PDMA_STREAM3_INT_IRQn = 383, /**< Shared Int Source PDMA_STREAM3_INT from Imaging Sub-System */
293 IMAGING_PDMA_STREAM4_INT_IRQn = 384, /**< Shared Int Source PDMA_STREAM4_INT from Imaging Sub-System */
294 IMAGING_PDMA_STREAM5_INT_IRQn = 385, /**< Shared Int Source PDMA_STREAM5_INT from Imaging Sub-System */
295 IMAGING_PDMA_STREAM6_INT_IRQn = 386, /**< Shared Int Source PDMA_STREAM6_INT from Imaging Sub-System */
296 IMAGING_PDMA_STREAM7_INT_IRQn = 387, /**< Shared Int Source PDMA_STREAM7_INT from Imaging Sub-System */
297 IMAGING_MJPEG_ENC0_INT_IRQn = 388, /**< Shared Int Source MJPEG_ENC0_INT from Imaging Sub-System */
298 IMAGING_MJPEG_ENC1_INT_IRQn = 389, /**< Shared Int Source MJPEG_ENC1_INT from Imaging Sub-System */
299 IMAGING_MJPEG_ENC2_INT_IRQn = 390, /**< Shared Int Source MJPEG_ENC2_INT from Imaging Sub-System */
300 IMAGING_MJPEG_ENC3_INT_IRQn = 391, /**< Shared Int Source MJPEG_ENC3_INT from Imaging Sub-System */
301 IMAGING_MJPEG_DEC0_INT_IRQn = 392, /**< Shared Int Source MJPEG_DEC0_INT from Imaging Sub-System */
302 IMAGING_MJPEG_DEC1_INT_IRQn = 393, /**< Shared Int Source MJPEG_DEC1_INT from Imaging Sub-System */
303 IMAGING_MJPEG_DEC2_INT_IRQn = 394, /**< Shared Int Source MJPEG_DEC2_INT from Imaging Sub-System */
304 IMAGING_MJPEG_DEC3_INT_IRQn = 395, /**< Shared Int Source MJPEG_DEC3_INT from Imaging Sub-System */
305 ADMA_SAI0_MOD_INT_IRQn = 397, /**< Shared Int Source SAI0_MOD_INT from ADMA Sub-System */
306 ADMA_SAI0_DMA_INT_IRQn = 398, /**< Shared Int Source SAI0_DMA_INT from ADMA Sub-System */
307 ADMA_SAI1_MOD_INT_IRQn = 399, /**< Shared Int Source SAI1_MOD_INT from ADMA Sub-System */
308 ADMA_SAI1_DMA_INT_IRQn = 400, /**< Shared Int Source SAI1_DMA_INT from ADMA Sub-System */
309 ADMA_SAI2_MOD_INT_IRQn = 401, /**< Shared Int Source SAI2_MOD_INT from ADMA Sub-System */
310 ADMA_SAI2_DMA_INT_IRQn = 402, /**< Shared Int Source SAI2_DMA_INT from ADMA Sub-System */
311 MIPI_CSI0_OUT_INT_IRQn = 403, /**< Shared Int Source OUT_INT from MIPI_CSI0 Sub-System */
312 ADMA_SAI3_MOD_INT_IRQn = 406, /**< Shared Int Source SAI3_MOD_INT from ADMA Sub-System */
313 ADMA_SAI3_DMA_INT_IRQn = 407, /**< Shared Int Source SAI3_DMA_INT from ADMA Sub-System */
314 ADMA_SAI4_MOD_INT_IRQn = 412, /**< Shared Int Source SAI4_MOD_INT from ADMA Sub-System */
315 ADMA_SAI4_DMA_INT_IRQn = 413, /**< Shared Int Source SAI4_DMA_INT from ADMA Sub-System */
316 ADMA_SAI5_MOD_INT_IRQn = 414, /**< Shared Int Source SAI5_MOD_INT from ADMA Sub-System */
317 ADMA_SAI5_DMA_INT_IRQn = 415, /**< Shared Int Source SAI5_DMA_INT from ADMA Sub-System */
318 ADMA_SPI0_MOD_INT_IRQn = 419, /**< Shared Int Source SPI0_MOD_INT from ADMA Sub-System */
319 ADMA_SPI1_MOD_INT_IRQn = 420, /**< Shared Int Source SPI1_MOD_INT from ADMA Sub-System */
320 ADMA_SPI2_MOD_INT_IRQn = 421, /**< Shared Int Source SPI2_MOD_INT from ADMA Sub-System */
321 ADMA_SPI3_MOD_INT_IRQn = 422, /**< Shared Int Source SPI3_MOD_INT from ADMA Sub-System */
322 ADMA_I2C0_MOD_INT_IRQn = 423, /**< Shared Int Source I2C0_MOD_INT from ADMA Sub-System */
323 ADMA_I2C1_MOD_INT_IRQn = 424, /**< Shared Int Source I2C1_MOD_INT from ADMA Sub-System */
324 ADMA_I2C2_MOD_INT_IRQn = 425, /**< Shared Int Source I2C2_MOD_INT from ADMA Sub-System */
325 ADMA_I2C3_MOD_INT_IRQn = 426, /**< Shared Int Source I2C3_MOD_INT from ADMA Sub-System */
326 ADMA_UART0_MOD_INT_IRQn = 428, /**< Shared Int Source UART0_MOD_INT from ADMA Sub-System */
327 ADMA_UART1_MOD_INT_IRQn = 429, /**< Shared Int Source UART1_MOD_INT from ADMA Sub-System */
328 ADMA_UART2_MOD_INT_IRQn = 430, /**< Shared Int Source UART2_MOD_INT from ADMA Sub-System */
329 ADMA_UART3_MOD_INT_IRQn = 431, /**< Shared Int Source UART3_MOD_INT from ADMA Sub-System */
330 ADMA_FLEXCAN0_MOD_INT_IRQn = 435, /**< Shared Int Source FLEXCAN0_MOD_INT from ADMA Sub-System */
331 ADMA_FLEXCAN1_MOD_INT_IRQn = 436, /**< Shared Int Source FLEXCAN1_MOD_INT from ADMA Sub-System */
332 ADMA_FLEXCAN2_MOD_INT_IRQn = 437, /**< Shared Int Source FLEXCAN2_MOD_INT from ADMA Sub-System */
333 ADMA_FTM0_MOD_INT_IRQn = 438, /**< Shared Int Source FTM0_MOD_INT from ADMA Sub-System */
334 ADMA_FTM1_MOD_INT_IRQn = 439, /**< Shared Int Source FTM1_MOD_INT from ADMA Sub-System */
335 ADMA_ADC0_MOD_INT_IRQn = 440, /**< Shared Int Source ADC0_MOD_INT from ADMA Sub-System */
336 ADMA_FLEXCAN0_DMA_INT_IRQn = 442, /**< Shared Int Source FLEXCAN0_DMA_INT from ADMA Sub-System */
337 ADMA_FLEXCAN1_DMA_INT_IRQn = 443, /**< Shared Int Source FLEXCAN1_DMA_INT from ADMA Sub-System */
338 ADMA_FLEXCAN2_DMA_INT_IRQn = 444, /**< Shared Int Source FLEXCAN2_DMA_INT from ADMA Sub-System */
339 ADMA_FTM0_DMA_INT_IRQn = 445, /**< Shared Int Source FTM0_DMA_INT from ADMA Sub-System */
340 ADMA_FTM1_DMA_INT_IRQn = 446, /**< Shared Int Source FTM1_DMA_INT from ADMA Sub-System */
341 ADMA_ADC0_DMA_INT_IRQn = 447, /**< Shared Int Source ADC0_DMA_INT from ADMA Sub-System */
342 ADMA_EDMA0_INT_IRQn = 451, /**< Shared Int Source eDMA0_INT from ADMA Sub-System */
343 ADMA_EDMA0_ERR_INT_IRQn = 452, /**< Shared Int Source eDMA0_ERR_INT from ADMA Sub-System */
344 ADMA_EDMA1_INT_IRQn = 453, /**< Shared Int Source eDMA1_INT from ADMA Sub-System */
345 ADMA_EDMA1_ERR_INT_IRQn = 454, /**< Shared Int Source eDMA1_ERR_INT from ADMA Sub-System */
346 ADMA_ASRC0_INT1_IRQn = 455, /**< Shared Int Source ASRC0_INT1 from ADMA Sub-System */
347 ADMA_ASRC0_INT2_IRQn = 456, /**< Shared Int Source ASRC0_INT2 from ADMA Sub-System */
348 ADMA_DMA0_CH0_INT_IRQn = 457, /**< Shared Int Source DMA0_CH0_INT from ADMA Sub-System */
349 ADMA_DMA0_CH1_INT_IRQn = 458, /**< Shared Int Source DMA0_CH1_INT from ADMA Sub-System */
350 ADMA_DMA0_CH2_INT_IRQn = 459, /**< Shared Int Source DMA0_CH2_INT from ADMA Sub-System */
351 ADMA_DMA0_CH3_INT_IRQn = 460, /**< Shared Int Source DMA0_CH3_INT from ADMA Sub-System */
352 ADMA_DMA0_CH4_INT_IRQn = 461, /**< Shared Int Source DMA0_CH4_INT from ADMA Sub-System */
353 ADMA_DMA0_CH5_INT_IRQn = 462, /**< Shared Int Source DMA0_CH5_INT from ADMA Sub-System */
354 ADMA_ASRC1_INT1_IRQn = 463, /**< Shared Int Source ASRC1_INT1 from ADMA Sub-System */
355 ADMA_ASRC1_INT2_IRQn = 464, /**< Shared Int Source ASRC1_INT2 from ADMA Sub-System */
356 ADMA_DMA1_CH0_INT_IRQn = 465, /**< Shared Int Source DMA1_CH0_INT from ADMA Sub-System */
357 ADMA_DMA1_CH1_INT_IRQn = 466, /**< Shared Int Source DMA1_CH1_INT from ADMA Sub-System */
358 ADMA_DMA1_CH2_INT_IRQn = 467, /**< Shared Int Source DMA1_CH2_INT from ADMA Sub-System */
359 ADMA_DMA1_CH3_INT_IRQn = 468, /**< Shared Int Source DMA1_CH3_INT from ADMA Sub-System */
360 ADMA_DMA1_CH4_INT_IRQn = 469, /**< Shared Int Source DMA1_CH4_INT from ADMA Sub-System */
361 ADMA_DMA1_CH5_INT_IRQn = 470, /**< Shared Int Source DMA1_CH5_INT from ADMA Sub-System */
362 ADMA_ESAI0_INT_IRQn = 471, /**< Shared Int Source ESAI0_INT from ADMA Sub-System */
363 ADMA_GPT0_INT_IRQn = 474, /**< Shared Int Source GPT0_INT from ADMA Sub-System */
364 ADMA_GPT1_INT_IRQn = 475, /**< Shared Int Source GPT1_INT from ADMA Sub-System */
365 ADMA_GPT2_INT_IRQn = 476, /**< Shared Int Source GPT2_INT from ADMA Sub-System */
366 ADMA_GPT3_INT_IRQn = 477, /**< Shared Int Source GPT3_INT from ADMA Sub-System */
367 ADMA_GPT4_INT_IRQn = 478, /**< Shared Int Source GPT4_INT from ADMA Sub-System */
368 ADMA_GPT5_INT_IRQn = 479, /**< Shared Int Source GPT5_INT from ADMA Sub-System */
369 ADMA_SAI0_INT_IRQn = 480, /**< Shared Int Source SAI0_INT from ADMA Sub-System */
370 ADMA_SAI1_INT_IRQn = 481, /**< Shared Int Source SAI1_INT from ADMA Sub-System */
371 ADMA_SAI2_INT_IRQn = 482, /**< Shared Int Source SAI2_INT from ADMA Sub-System */
372 ADMA_SAI3_INT_IRQn = 483, /**< Shared Int Source SAI3_INT from ADMA Sub-System */
373 ADMA_SAI4_INT_IRQn = 486, /**< Shared Int Source SAI4_INT from ADMA Sub-System */
374 ADMA_SAI5_INT_IRQn = 487, /**< Shared Int Source SAI5_INT from ADMA Sub-System */
375 ADMA_SPDIF0_RX_INT_IRQn = 488, /**< Shared Int Source SPDIF0_RX_INT from ADMA Sub-System */
376 ADMA_SPDIF0_TX_INT_IRQn = 489, /**< Shared Int Source SPDIF0_TX_INT from ADMA Sub-System */
377 ADMA_ESAI0_MOD_INT_IRQn = 492, /**< Shared Int Source ESAI0_MOD_INT from ADMA Sub-System */
378 ADMA_ESAI0_DMA_INT_IRQn = 493, /**< Shared Int Source ESAI0_DMA_INT from ADMA Sub-System */
379 ADMA_SPI0_DMA_RX_INT_IRQn = 499, /**< Shared Int Source SPI0_DMA_RX_INT from ADMA Sub-System */
380 ADMA_SPI0_DMA_TX_INT_IRQn = 500, /**< Shared Int Source SPI0_DMA_TX_INT from ADMA Sub-System */
381 ADMA_SPI1_DMA_RX_INT_IRQn = 501, /**< Shared Int Source SPI1_DMA_RX_INT from ADMA Sub-System */
382 ADMA_SPI1_DMA_TX_INT_IRQn = 502, /**< Shared Int Source SPI1_DMA_TX_INT from ADMA Sub-System */
383 ADMA_SPI2_DMA_RX_INT_IRQn = 503, /**< Shared Int Source SPI2_DMA_RX_INT from ADMA Sub-System */
384 ADMA_SPI2_DMA_TX_INT_IRQn = 504, /**< Shared Int Source SPI2_DMA_TX_INT from ADMA Sub-System */
385 ADMA_SPI3_DMA_RX_INT_IRQn = 505, /**< Shared Int Source SPI3_DMA_RX_INT from ADMA Sub-System */
386 ADMA_SPI3_DMA_TX_INT_IRQn = 506, /**< Shared Int Source SPI3_DMA_TX_INT from ADMA Sub-System */
387 ADMA_I2C0_DMA_RX_INT_IRQn = 507, /**< Shared Int Source I2C0_DMA_RX_INT from ADMA Sub-System */
388 ADMA_I2C0_DMA_TX_INT_IRQn = 508, /**< Shared Int Source I2C0_DMA_TX_INT from ADMA Sub-System */
389 ADMA_I2C1_DMA_RX_INT_IRQn = 509, /**< Shared Int Source I2C1_DMA_RX_INT from ADMA Sub-System */
390 ADMA_I2C1_DMA_TX_INT_IRQn = 510, /**< Shared Int Source I2C1_DMA_TX_INT from ADMA Sub-System */
391 ADMA_I2C2_DMA_RX_INT_IRQn = 511, /**< Shared Int Source I2C2_DMA_RX_INT from ADMA Sub-System */
392 ADMA_I2C2_DMA_TX_INT_IRQn = 512, /**< Shared Int Source I2C2_DMA_TX_INT from ADMA Sub-System */
393 ADMA_I2C3_DMA_RX_INT_IRQn = 513, /**< Shared Int Source I2C3_DMA_RX_INT from ADMA Sub-System */
394 ADMA_I2C3_DMA_TX_INT_IRQn = 514, /**< Shared Int Source I2C3_DMA_TX_INT from ADMA Sub-System */
395 ADMA_UART0_DMA_RX_INT_IRQn = 517, /**< Shared Int Source UART0_DMA_RX_INT from ADMA Sub-System */
396 ADMA_UART0_DMA_TX_INT_IRQn = 518, /**< Shared Int Source UART0_DMA_TX_INT from ADMA Sub-System */
397 ADMA_UART1_DMA_RX_INT_IRQn = 519, /**< Shared Int Source UART1_DMA_RX_INT from ADMA Sub-System */
398 ADMA_UART1_DMA_TX_INT_IRQn = 520, /**< Shared Int Source UART1_DMA_TX_INT from ADMA Sub-System */
399 ADMA_UART2_DMA_RX_INT_IRQn = 521, /**< Shared Int Source UART2_DMA_RX_INT from ADMA Sub-System */
400 ADMA_UART2_DMA_TX_INT_IRQn = 522, /**< Shared Int Source UART2_DMA_TX_INT from ADMA Sub-System */
401 ADMA_UART3_DMA_RX_INT_IRQn = 523, /**< Shared Int Source UART3_DMA_RX_INT from ADMA Sub-System */
402 ADMA_UART3_DMA_TX_INT_IRQn = 524, /**< Shared Int Source UART3_DMA_TX_INT from ADMA Sub-System */
403 SECURITY_MU1_A_INT_IRQn = 531, /**< Shared Int Source MU1_A_INT from Security Sub-System */
404 SECURITY_MU2_A_INT_IRQn = 532, /**< Shared Int Source MU2_A_INT from Security Sub-System */
405 SECURITY_MU3_A_INT_IRQn = 533, /**< Shared Int Source MU3_A_INT from Security Sub-System */
406 SECURITY_CAAM_INT0_IRQn = 534, /**< Shared Int Source CAAM_INT0 from Security Sub-System */
407 SECURITY_CAAM_INT1_IRQn = 535, /**< Shared Int Source CAAM_INT1 from Security Sub-System */
408 SECURITY_CAAM_INT2_IRQn = 536, /**< Shared Int Source CAAM_INT2 from Security Sub-System */
409 SECURITY_CAAM_INT3_IRQn = 537, /**< Shared Int Source CAAM_INT3 from Security Sub-System */
410 SECURITY_CAAM_RTIC_INT_IRQn = 538, /**< Shared Int Source CAAM_RTIC_INT from Security Sub-System */
411 ADMA_SPDIF0_RX_MOD_INT_IRQn = 539, /**< Shared Int Source SPDIF0_RX_MOD_INT from ADMA Sub-System */
412 ADMA_SPDIF0_RX_DMA_INT_IRQn = 540, /**< Shared Int Source SPDIF0_RX_DMA_INT from ADMA Sub-System */
413 ADMA_SPDIF0_TX_MOD_INT_IRQn = 541, /**< Shared Int Source SPDIF0_TX_MOD_INT from ADMA Sub-System */
414 ADMA_SPDIF0_TX_DMA_INT_IRQn = 542, /**< Shared Int Source SPDIF0_TX_DMA_INT from ADMA Sub-System */
415 VPU_VPU_INT_0_IRQn = 547, /**< Shared Int Source VPU_INT_0 from VPU Sub-System */
416 VPU_VPU_INT_1_IRQn = 548, /**< Shared Int Source VPU_INT_1 from VPU Sub-System */
417 VPU_VPU_INT_2_IRQn = 549, /**< Shared Int Source VPU_INT_2 from VPU Sub-System */
418 VPU_VPU_INT_3_IRQn = 550, /**< Shared Int Source VPU_INT_3 from VPU Sub-System */
419 VPU_VPU_INT_4_IRQn = 551, /**< Shared Int Source VPU_INT_4 from VPU Sub-System */
420 M4_INTMUX_SOURCE_TPM_IRQn = 564, /**< INTMUX Input source: TPM Interrupt */
421 M4_INTMUX_SOURCE_LPIT_IRQn = 567, /**< INTMUX Input source: LPIT Interrupt */
422 M4_INTMUX_SOURCE_LPUART_IRQn = 570, /**< INTMUX Input source: LPUART Interrupt */
423 M4_INTMUX_SOURCE_LPI2C_IRQn = 572, /**< INTMUX Input source: LPI2C Interrupt */
424 M4_INTMUX_SOURCE_MU0_A3_IRQn = 591, /**< INTMUX Input source: MU0_A3 Interrupt */
425 M4_INTMUX_SOURCE_MU0_A2_IRQn = 592, /**< INTMUX Input source: MU0_A2 Interrupt */
426 M4_INTMUX_SOURCE_MU0_A1_IRQn = 593, /**< INTMUX Input source: MU0_A1 Interrupt */
427 M4_INTMUX_SOURCE_MU0_A0_IRQn = 594 /**< INTMUX Input source: MU0_A0 Interrupt */
428} IRQn_Type;
429
430/*!
431 * @}
432 */ /* end of group Interrupt_vector_numbers */
433
434
435/* ----------------------------------------------------------------------------
436 -- Configuration of the Cortex-M4 Processor and Core Peripherals
437 ---------------------------------------------------------------------------- */
438
439/*!
440 * @addtogroup Cortex_Core_Configuration Configuration of the Cortex-M4 Processor and Core Peripherals
441 * @{
442 */
443
444#define __CM4_REV 0x0001 /**< Core revision r0p1 */
445#define __MPU_PRESENT 1 /**< MPU present or not */
446#define __NVIC_PRIO_BITS 4 /**< Number of Bits used for Priority Levels */
447#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
448#define __FPU_PRESENT 1 /**< FPU present or not */
449
450#include "core_cm4.h" /* Core Peripheral Access Layer */
451#include "system_MIMX8QX3_cm4.h" /* Device specific configuration file */
452
453/*!
454 * @}
455 */ /* end of group Cortex_Core_Configuration */
456
457
458/* ----------------------------------------------------------------------------
459 -- Device Peripheral Access Layer
460 ---------------------------------------------------------------------------- */
461
462/*!
463 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
464 * @{
465 */
466
467
468/*
469** Start of section using anonymous unions
470*/
471
472#if defined(__ARMCC_VERSION)
473 #if (__ARMCC_VERSION >= 6010050)
474 #pragma clang diagnostic push
475 #else
476 #pragma push
477 #pragma anon_unions
478 #endif
479#elif defined(__GNUC__)
480 /* anonymous unions are enabled by default */
481#elif defined(__IAR_SYSTEMS_ICC__)
482 #pragma language=extended
483#else
484 #error Not supported compiler type
485#endif
486
487/* ----------------------------------------------------------------------------
488 -- ACM Peripheral Access Layer
489 ---------------------------------------------------------------------------- */
490
491/*!
492 * @addtogroup ACM_Peripheral_Access_Layer ACM Peripheral Access Layer
493 * @{
494 */
495
496/** ACM - Register Layout Typedef */
497typedef struct {
498 uint8_t RESERVED_0[14680064];
499 __IO uint32_t AUD_CLK0; /**< ACM_AUD_CLK0 Register, offset: 0xE00000 */
500 uint8_t RESERVED_1[65532];
501 __IO uint32_t AUD_CLK1; /**< ACM_AUD_CLK1 Register, offset: 0xE10000 */
502 uint8_t RESERVED_2[65532];
503 __IO uint32_t MCLKOUT0; /**< ACM_MCLKOUT0 Register, offset: 0xE20000 */
504 uint8_t RESERVED_3[65532];
505 __IO uint32_t MCLKOUT1; /**< ACM_MCLKOUT1 Register, offset: 0xE30000 */
506 uint8_t RESERVED_4[196604];
507 __IO uint32_t ESAI0_CLK; /**< ACM_ESAI0_CLK Register, offset: 0xE60000 */
508 uint8_t RESERVED_5[131068];
509 struct { /* offset: 0xE80000, array step: 0x10000 */
510 __IO uint32_t GPT_CLK; /**< ACM_GPT_CLK Register, array offset: 0xE80000, array step: 0x10000 */
511 uint8_t RESERVED_0[65532];
512 } GPT_CLK[6];
513 struct { /* offset: 0xEE0000, array step: 0x10000 */
514 __IO uint32_t SAI_MCLK; /**< ACM_SAI_MCLK Register, array offset: 0xEE0000, array step: 0x10000 */
515 uint8_t RESERVED_0[65532];
516 } SAI_MCLK[8];
517 uint8_t RESERVED_6[262144];
518 __IO uint32_t SPDIF0_TX_CLK; /**< ACM_SPDIF0_TX_CLK Register, offset: 0xFA0000 */
519 uint8_t RESERVED_7[131068];
520 __IO uint32_t MQS_HMCLK_CLK; /**< ACM_MQS_HMCLK_CLK Register, offset: 0xFC0000 */
521} ACM_Type;
522
523/* ----------------------------------------------------------------------------
524 -- ACM Register Masks
525 ---------------------------------------------------------------------------- */
526
527/*!
528 * @addtogroup ACM_Register_Masks ACM Register Masks
529 * @{
530 */
531
532/*! @name AUD_CLK0 - ACM_AUD_CLK0 Register */
533/*! @{ */
534#define ACM_AUD_CLK0_SEL_MASK (0x1FU)
535#define ACM_AUD_CLK0_SEL_SHIFT (0U)
536/*! SEL - Select
537 * 0b00000..ADMA_SLSLICE2
538 * 0b00001..ADMA_SLSLICE3
539 * 0b00010..EXT_AUD_MCLK0
540 * 0b00011..EXT_AUD_MCLK1
541 * 0b00100..ESAI0_RX_CLK
542 * 0b00101..ESAI0_RX_HF_CLKK
543 * 0b00110..ESAI0_TX_CLK
544 * 0b00111..ESAI0_TX_HF_CLK
545 * 0b01000..SPDIF0_RX
546 * 0b01001..SAI0_RX_BCLK
547 * 0b01010..SAI0_TX_BCLK
548 * 0b01011..SAI1_RX_BCLK
549 * 0b01100..SAI1_TX_BCLK
550 * 0b01101..SAI2_RX_BCLK
551 * 0b01110..SAI3_RX_BCLK
552 */
553#define ACM_AUD_CLK0_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_AUD_CLK0_SEL_SHIFT)) & ACM_AUD_CLK0_SEL_MASK)
554/*! @} */
555
556/*! @name AUD_CLK1 - ACM_AUD_CLK1 Register */
557/*! @{ */
558#define ACM_AUD_CLK1_SEL_MASK (0x1FU)
559#define ACM_AUD_CLK1_SEL_SHIFT (0U)
560/*! SEL - Select
561 * 0b00000..ADMA_SLSLICE2
562 * 0b00001..ADMA_SLSLICE3
563 * 0b00010..EXT_AUD_MCLK0
564 * 0b00011..EXT_AUD_MCLK1
565 * 0b00100..ESAI0_RX_CLK
566 * 0b00101..ESAI0_RX_HF_CLKK
567 * 0b00110..ESAI0_TX_CLK
568 * 0b00111..ESAI0_TX_HF_CLK
569 * 0b01000..SPDIF0_RX
570 * 0b01001..SAI0_RX_BCLK
571 * 0b01010..SAI0_TX_BCLK
572 * 0b01011..SAI1_RX_BCLK
573 * 0b01100..SAI1_TX_BCLK
574 * 0b01101..SAI2_RX_BCLK
575 * 0b01110..SAI3_RX_BCLK
576 */
577#define ACM_AUD_CLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_AUD_CLK1_SEL_SHIFT)) & ACM_AUD_CLK1_SEL_MASK)
578/*! @} */
579
580/*! @name MCLKOUT0 - ACM_MCLKOUT0 Register */
581/*! @{ */
582#define ACM_MCLKOUT0_SEL_MASK (0x7U)
583#define ACM_MCLKOUT0_SEL_SHIFT (0U)
584/*! SEL - Select
585 * 0b000..ADMA_SLSLICE2
586 * 0b001..ADMA_SLSLICE3
587 * 0b010..Reserved
588 * 0b011..Reserved
589 * 0b100..SPDIF0_RX
590 * 0b101..Reserved
591 * 0b110..Reserved
592 * 0b111..SAI4_RX_BCLK
593 */
594#define ACM_MCLKOUT0_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MCLKOUT0_SEL_SHIFT)) & ACM_MCLKOUT0_SEL_MASK)
595/*! @} */
596
597/*! @name MCLKOUT1 - ACM_MCLKOUT1 Register */
598/*! @{ */
599#define ACM_MCLKOUT1_SEL_MASK (0x7U)
600#define ACM_MCLKOUT1_SEL_SHIFT (0U)
601/*! SEL - Select
602 * 0b000..ADMA_SLSLICE2
603 * 0b001..ADMA_SLSLICE3
604 * 0b010..Reserved
605 * 0b011..Reserved
606 * 0b100..SPDIF0_RX
607 * 0b101..Reserved
608 * 0b110..Reserved
609 * 0b111..SAI4_RX_BCLK
610 */
611#define ACM_MCLKOUT1_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MCLKOUT1_SEL_SHIFT)) & ACM_MCLKOUT1_SEL_MASK)
612/*! @} */
613
614/*! @name ESAI0_CLK - ACM_ESAI0_CLK Register */
615/*! @{ */
616#define ACM_ESAI0_CLK_SEL_MASK (0x3U)
617#define ACM_ESAI0_CLK_SEL_SHIFT (0U)
618/*! SEL - Select
619 * 0b00..AUD_PLL_DIV_CLK0
620 * 0b01..AUD_PLL_DIV_CLK1
621 * 0b10..AUD_CLK0
622 * 0b11..AUD_CLK1
623 */
624#define ACM_ESAI0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_ESAI0_CLK_SEL_SHIFT)) & ACM_ESAI0_CLK_SEL_MASK)
625/*! @} */
626
627/*! @name GPT_CLK - ACM_GPT_CLK Register */
628/*! @{ */
629#define ACM_GPT_CLK_SEL_MASK (0x7U)
630#define ACM_GPT_CLK_SEL_SHIFT (0U)
631/*! SEL - Select
632 * 0b000..AUD_PLL_DIV_CLK0
633 * 0b001..AUD_PLL_DIV_CLK1
634 * 0b010..AUD_CLK0
635 * 0b011..AUD_CLK1
636 * 0b100..24M_REF_CLK
637 */
638#define ACM_GPT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT_CLK_SEL_SHIFT)) & ACM_GPT_CLK_SEL_MASK)
639/*! @} */
640
641/* The count of ACM_GPT_CLK */
642#define ACM_GPT_CLK_COUNT (6U)
643
644/*! @name SAI_MCLK - ACM_SAI_MCLK Register */
645/*! @{ */
646#define ACM_SAI_MCLK_SEL_MASK (0x3U)
647#define ACM_SAI_MCLK_SEL_SHIFT (0U)
648/*! SEL - Select
649 * 0b00..AUD_PLL_DIV_CLK0
650 * 0b01..AUD_PLL_DIV_CLK1
651 * 0b10..AUD_CLK0
652 * 0b11..AUD_CLK1
653 */
654#define ACM_SAI_MCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SAI_MCLK_SEL_SHIFT)) & ACM_SAI_MCLK_SEL_MASK)
655/*! @} */
656
657/* The count of ACM_SAI_MCLK */
658#define ACM_SAI_MCLK_COUNT (8U)
659
660/*! @name SPDIF0_TX_CLK - ACM_SPDIF0_TX_CLK Register */
661/*! @{ */
662#define ACM_SPDIF0_TX_CLK_SEL_MASK (0x3U)
663#define ACM_SPDIF0_TX_CLK_SEL_SHIFT (0U)
664/*! SEL - Select
665 * 0b00..AUD_PLL_DIV_CLK0
666 * 0b01..AUD_PLL_DIV_CLK1
667 * 0b10..AUD_CLK0
668 * 0b11..AUD_CLK1
669 */
670#define ACM_SPDIF0_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SPDIF0_TX_CLK_SEL_SHIFT)) & ACM_SPDIF0_TX_CLK_SEL_MASK)
671/*! @} */
672
673/*! @name MQS_HMCLK_CLK - ACM_MQS_HMCLK_CLK Register */
674/*! @{ */
675#define ACM_MQS_HMCLK_CLK_SEL_MASK (0x3U)
676#define ACM_MQS_HMCLK_CLK_SEL_SHIFT (0U)
677/*! SEL - Select
678 * 0b00..AUD_PLL_DIV_CLK0
679 * 0b01..AUD_PLL_DIV_CLK1
680 * 0b10..AUD_CLK0
681 * 0b11..AUD_CLK1
682 */
683#define ACM_MQS_HMCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MQS_HMCLK_CLK_SEL_SHIFT)) & ACM_MQS_HMCLK_CLK_SEL_MASK)
684/*! @} */
685
686
687/*!
688 * @}
689 */ /* end of group ACM_Register_Masks */
690
691
692/* ACM - Peripheral instance base addresses */
693/** Peripheral ADMA__ACM base address */
694#define ADMA__ACM_BASE (0x59000000u)
695/** Peripheral ADMA__ACM base pointer */
696#define ADMA__ACM ((ACM_Type *)ADMA__ACM_BASE)
697/** Array initializer of ACM peripheral base addresses */
698#define ACM_BASE_ADDRS { ADMA__ACM_BASE }
699/** Array initializer of ACM peripheral base pointers */
700#define ACM_BASE_PTRS { ADMA__ACM }
701
702/*!
703 * @}
704 */ /* end of group ACM_Peripheral_Access_Layer */
705
706
707/* ----------------------------------------------------------------------------
708 -- ADC Peripheral Access Layer
709 ---------------------------------------------------------------------------- */
710
711/*!
712 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
713 * @{
714 */
715
716/** ADC - Register Layout Typedef */
717typedef struct {
718 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
719 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
720 uint8_t RESERVED_0[8];
721 __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */
722 __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */
723 __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */
724 __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */
725 __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */
726 __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */
727 uint8_t RESERVED_1[8];
728 __IO uint32_t FCTRL; /**< ADC FIFO Control Register, offset: 0x30 */
729 __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */
730 uint8_t RESERVED_2[136];
731 __IO uint32_t TCTRL[8]; /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */
732 uint8_t RESERVED_3[32];
733 struct { /* offset: 0x100, array step: 0x8 */
734 __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
735 __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
736 } CMD[15];
737 uint8_t RESERVED_4[136];
738 __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
739 uint8_t RESERVED_5[240];
740 __I uint32_t RESFIFO; /**< ADC Data Result FIFO Register, offset: 0x300 */
741} ADC_Type;
742
743/* ----------------------------------------------------------------------------
744 -- ADC Register Masks
745 ---------------------------------------------------------------------------- */
746
747/*!
748 * @addtogroup ADC_Register_Masks ADC Register Masks
749 * @{
750 */
751
752/*! @name VERID - Version ID Register */
753/*! @{ */
754#define ADC_VERID_RES_MASK (0x1U)
755#define ADC_VERID_RES_SHIFT (0U)
756/*! RES - Resolution
757 * 0b0..Up to 13-bit differential/12-bit single ended resolution supported.
758 * 0b1..Up to 16-bit differential/15-bit single ended resolution supported.
759 */
760#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
761#define ADC_VERID_DIFFEN_MASK (0x2U)
762#define ADC_VERID_DIFFEN_SHIFT (1U)
763/*! DIFFEN - Differential Supported
764 * 0b0..Differential operation not supported.
765 * 0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.
766 */
767#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
768#define ADC_VERID_MVI_MASK (0x8U)
769#define ADC_VERID_MVI_SHIFT (3U)
770/*! MVI - Multi Vref Implemented
771 * 0b0..Single voltage reference high (VREFH) input supported.
772 * 0b1..Multiple voltage reference high (VREFH) inputs supported.
773 */
774#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
775#define ADC_VERID_CSW_MASK (0x70U)
776#define ADC_VERID_CSW_SHIFT (4U)
777/*! CSW - Channel Scale Width
778 * 0b000..Channel scaling not supported.
779 * 0b001..Channel scaling supported. 1-bit CSCALE control field.
780 * 0b110..Channel scaling supported. 6-bit CSCALE control field.
781 */
782#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
783#define ADC_VERID_VR1RNGI_MASK (0x100U)
784#define ADC_VERID_VR1RNGI_SHIFT (8U)
785/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
786 * 0b0..Range control not required. CFG[VREF1RNG] is not implemented.
787 * 0b1..Range control required. CFG[VREF1RNG] is implemented.
788 */
789#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
790#define ADC_VERID_IADCKI_MASK (0x200U)
791#define ADC_VERID_IADCKI_SHIFT (9U)
792/*! IADCKI - Internal ADC Clock implemented
793 * 0b0..Internal clock source not implemented.
794 * 0b1..Internal clock source (and CFG[ADCKEN]) implemented.
795 */
796#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
797#define ADC_VERID_CALOFSI_MASK (0x400U)
798#define ADC_VERID_CALOFSI_SHIFT (10U)
799/*! CALOFSI - Calibration Offset Function Implemented
800 * 0b0..Offset calibration and offset trimming not implemented.
801 * 0b1..Offset calibration and offset trimming implemented.
802 */
803#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
804#define ADC_VERID_MINOR_MASK (0xFF0000U)
805#define ADC_VERID_MINOR_SHIFT (16U)
806/*! MINOR - Minor Version Number
807 */
808#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
809#define ADC_VERID_MAJOR_MASK (0xFF000000U)
810#define ADC_VERID_MAJOR_SHIFT (24U)
811/*! MAJOR - Major Version Number
812 */
813#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
814/*! @} */
815
816/*! @name PARAM - Parameter Register */
817/*! @{ */
818#define ADC_PARAM_TRIG_NUM_MASK (0xFFU)
819#define ADC_PARAM_TRIG_NUM_SHIFT (0U)
820/*! TRIG_NUM - Trigger Number
821 */
822#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
823#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U)
824#define ADC_PARAM_FIFOSIZE_SHIFT (8U)
825/*! FIFOSIZE - Result FIFO Depth
826 * 0b00000001..Result FIFO depth = 1 dataword.
827 * 0b00000100..Result FIFO depth = 4 datawords.
828 * 0b00001000..Result FIFO depth = 8 datawords.
829 * 0b00010000..Result FIFO depth = 16 datawords.
830 * 0b00100000..Result FIFO depth = 32 datawords.
831 * 0b01000000..Result FIFO depth = 64 datawords.
832 */
833#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
834#define ADC_PARAM_CV_NUM_MASK (0xFF0000U)
835#define ADC_PARAM_CV_NUM_SHIFT (16U)
836/*! CV_NUM - Compare Value Number
837 */
838#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
839#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U)
840#define ADC_PARAM_CMD_NUM_SHIFT (24U)
841/*! CMD_NUM - Command Buffer Number
842 */
843#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
844/*! @} */
845
846/*! @name CTRL - ADC Control Register */
847/*! @{ */
848#define ADC_CTRL_ADCEN_MASK (0x1U)
849#define ADC_CTRL_ADCEN_SHIFT (0U)
850/*! ADCEN - ADC Enable
851 * 0b0..ADC is disabled.
852 * 0b1..ADC is enabled.
853 */
854#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
855#define ADC_CTRL_RST_MASK (0x2U)
856#define ADC_CTRL_RST_SHIFT (1U)
857/*! RST - Software Reset
858 * 0b0..ADC logic is not reset.
859 * 0b1..ADC logic is reset.
860 */
861#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
862#define ADC_CTRL_DOZEN_MASK (0x4U)
863#define ADC_CTRL_DOZEN_SHIFT (2U)
864/*! DOZEN - Doze Enable
865 * 0b0..ADC is enabled in Doze mode.
866 * 0b1..ADC is disabled in Doze mode.
867 */
868#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
869#define ADC_CTRL_RSTFIFO_MASK (0x100U)
870#define ADC_CTRL_RSTFIFO_SHIFT (8U)
871/*! RSTFIFO - Reset FIFO
872 * 0b0..No effect.
873 * 0b1..FIFO is reset.
874 */
875#define ADC_CTRL_RSTFIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)
876/*! @} */
877
878/*! @name STAT - ADC Status Register */
879/*! @{ */
880#define ADC_STAT_RDY_MASK (0x1U)
881#define ADC_STAT_RDY_SHIFT (0U)
882/*! RDY - Result FIFO Ready Flag
883 * 0b0..Result FIFO data level not above watermark level.
884 * 0b1..Result FIFO holding data above watermark level.
885 */
886#define ADC_STAT_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)
887#define ADC_STAT_FOF_MASK (0x2U)
888#define ADC_STAT_FOF_SHIFT (1U)
889/*! FOF - Result FIFO Overflow Flag
890 * 0b0..No result FIFO overflow has occurred since the last time the flag was cleared.
891 * 0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared.
892 */
893#define ADC_STAT_FOF(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)
894#define ADC_STAT_ADC_ACTIVE_MASK (0x100U)
895#define ADC_STAT_ADC_ACTIVE_SHIFT (8U)
896/*! ADC_ACTIVE - ADC Active
897 * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
898 * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
899 */
900#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
901#define ADC_STAT_TRGACT_MASK (0x70000U)
902#define ADC_STAT_TRGACT_SHIFT (16U)
903/*! TRGACT - Trigger Active
904 * 0b000..Command (sequence) associated with Trigger 0 currently being executed.
905 * 0b001..Command (sequence) associated with Trigger 1 currently being executed.
906 * 0b010..Command (sequence) associated with Trigger 2 currently being executed.
907 * 0b011-0b111..Command (sequence) from the associated Trigger number is currently being executed.
908 */
909#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
910#define ADC_STAT_CMDACT_MASK (0xF000000U)
911#define ADC_STAT_CMDACT_SHIFT (24U)
912/*! CMDACT - Command Active
913 * 0b0000..No command is currently in progress.
914 * 0b0001..Command 1 currently being executed.
915 * 0b0010..Command 2 currently being executed.
916 * 0b0011-0b1111..Associated command number is currently being executed.
917 */
918#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
919/*! @} */
920
921/*! @name IE - Interrupt Enable Register */
922/*! @{ */
923#define ADC_IE_FWMIE_MASK (0x1U)
924#define ADC_IE_FWMIE_SHIFT (0U)
925/*! FWMIE - FIFO Watermark Interrupt Enable
926 * 0b0..FIFO watermark interrupts are not enabled.
927 * 0b1..FIFO watermark interrupts are enabled.
928 */
929#define ADC_IE_FWMIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)
930#define ADC_IE_FOFIE_MASK (0x2U)
931#define ADC_IE_FOFIE_SHIFT (1U)
932/*! FOFIE - Result FIFO Overflow Interrupt Enable
933 * 0b0..FIFO overflow interrupts are not enabled.
934 * 0b1..FIFO overflow interrupts are enabled.
935 */
936#define ADC_IE_FOFIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)
937/*! @} */
938
939/*! @name DE - DMA Enable Register */
940/*! @{ */
941#define ADC_DE_FWMDE_MASK (0x1U)
942#define ADC_DE_FWMDE_SHIFT (0U)
943/*! FWMDE - FIFO Watermark DMA Enable
944 * 0b0..DMA request disabled.
945 * 0b1..DMA request enabled.
946 */
947#define ADC_DE_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)
948/*! @} */
949
950/*! @name CFG - ADC Configuration Register */
951/*! @{ */
952#define ADC_CFG_TPRICTRL_MASK (0x1U)
953#define ADC_CFG_TPRICTRL_SHIFT (0U)
954/*! TPRICTRL - ADC trigger priority control
955 * 0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and
956 * the new command specified by the trigger is started.
957 * 0b1..If a higher priority trigger is received during command processing, the current conversion is completed
958 * (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority
959 * trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true
960 * conversion.
961 */
962#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
963#define ADC_CFG_PWRSEL_MASK (0x30U)
964#define ADC_CFG_PWRSEL_SHIFT (4U)
965/*! PWRSEL - Power Configuration Select
966 * 0b00..Level 1 (Lowest power setting)
967 * 0b01..Level 2
968 * 0b10..Level 3
969 * 0b11..Level 4 (Highest power setting)
970 */
971#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
972#define ADC_CFG_REFSEL_MASK (0xC0U)
973#define ADC_CFG_REFSEL_SHIFT (6U)
974/*! REFSEL - Voltage Reference Selection
975 * 0b00..(Default) Option 1 setting.
976 * 0b01..Option 2 setting.
977 * 0b10..Option 3 setting.
978 * 0b11..Reserved
979 */
980#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
981#define ADC_CFG_PUDLY_MASK (0xFF0000U)
982#define ADC_CFG_PUDLY_SHIFT (16U)
983/*! PUDLY - Power Up Delay
984 */
985#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
986#define ADC_CFG_PWREN_MASK (0x10000000U)
987#define ADC_CFG_PWREN_SHIFT (28U)
988/*! PWREN - ADC Analog Pre-Enable
989 * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
990 * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
991 * of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any
992 * detected trigger does not begin ADC operation until the power up delay time has passed.
993 */
994#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
995/*! @} */
996
997/*! @name PAUSE - ADC Pause Register */
998/*! @{ */
999#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU)
1000#define ADC_PAUSE_PAUSEDLY_SHIFT (0U)
1001/*! PAUSEDLY - Pause Delay
1002 */
1003#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
1004#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U)
1005#define ADC_PAUSE_PAUSEEN_SHIFT (31U)
1006/*! PAUSEEN - PAUSE Option Enable
1007 * 0b0..Pause operation disabled
1008 * 0b1..Pause operation enabled
1009 */
1010#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
1011/*! @} */
1012
1013/*! @name FCTRL - ADC FIFO Control Register */
1014/*! @{ */
1015#define ADC_FCTRL_FCOUNT_MASK (0x1FU)
1016#define ADC_FCTRL_FCOUNT_SHIFT (0U)
1017/*! FCOUNT - Result FIFO counter
1018 */
1019#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
1020#define ADC_FCTRL_FWMARK_MASK (0xF0000U)
1021#define ADC_FCTRL_FWMARK_SHIFT (16U)
1022/*! FWMARK - Watermark level selection
1023 */
1024#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
1025/*! @} */
1026
1027/*! @name SWTRIG - Software Trigger Register */
1028/*! @{ */
1029#define ADC_SWTRIG_SWT0_MASK (0x1U)
1030#define ADC_SWTRIG_SWT0_SHIFT (0U)
1031/*! SWT0 - Software trigger 0 event
1032 * 0b0..No trigger 0 event generated.
1033 * 0b1..Trigger 0 event generated.
1034 */
1035#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
1036#define ADC_SWTRIG_SWT1_MASK (0x2U)
1037#define ADC_SWTRIG_SWT1_SHIFT (1U)
1038/*! SWT1 - Software trigger 1 event
1039 * 0b0..No trigger 1 event generated.
1040 * 0b1..Trigger 1 event generated.
1041 */
1042#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
1043#define ADC_SWTRIG_SWT2_MASK (0x4U)
1044#define ADC_SWTRIG_SWT2_SHIFT (2U)
1045/*! SWT2 - Software trigger 2 event
1046 * 0b0..No trigger 2 event generated.
1047 * 0b1..Trigger 2 event generated.
1048 */
1049#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
1050#define ADC_SWTRIG_SWT3_MASK (0x8U)
1051#define ADC_SWTRIG_SWT3_SHIFT (3U)
1052/*! SWT3 - Software trigger 3 event
1053 * 0b0..No trigger 3 event generated.
1054 * 0b1..Trigger 3 event generated.
1055 */
1056#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
1057#define ADC_SWTRIG_SWT4_MASK (0x10U)
1058#define ADC_SWTRIG_SWT4_SHIFT (4U)
1059/*! SWT4 - Software trigger 4 event
1060 * 0b0..No trigger 4 event generated.
1061 * 0b1..Trigger 4 event generated.
1062 */
1063#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
1064#define ADC_SWTRIG_SWT5_MASK (0x20U)
1065#define ADC_SWTRIG_SWT5_SHIFT (5U)
1066/*! SWT5 - Software trigger 5 event
1067 * 0b0..No trigger 5 event generated.
1068 * 0b1..Trigger 5 event generated.
1069 */
1070#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
1071#define ADC_SWTRIG_SWT6_MASK (0x40U)
1072#define ADC_SWTRIG_SWT6_SHIFT (6U)
1073/*! SWT6 - Software trigger 6 event
1074 * 0b0..No trigger 6 event generated.
1075 * 0b1..Trigger 6 event generated.
1076 */
1077#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
1078#define ADC_SWTRIG_SWT7_MASK (0x80U)
1079#define ADC_SWTRIG_SWT7_SHIFT (7U)
1080/*! SWT7 - Software trigger 7 event
1081 * 0b0..No trigger 7 event generated.
1082 * 0b1..Trigger 7 event generated.
1083 */
1084#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
1085/*! @} */
1086
1087/*! @name TCTRL - Trigger Control Register */
1088/*! @{ */
1089#define ADC_TCTRL_HTEN_MASK (0x1U)
1090#define ADC_TCTRL_HTEN_SHIFT (0U)
1091/*! HTEN - Trigger enable
1092 * 0b0..Hardware trigger source disabled
1093 * 0b1..Hardware trigger source enabled
1094 */
1095#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
1096#define ADC_TCTRL_TPRI_MASK (0x700U)
1097#define ADC_TCTRL_TPRI_SHIFT (8U)
1098/*! TPRI - Trigger priority setting
1099 * 0b000..Set to highest priority, Level 1
1100 * 0b001-0b110..Set to corresponding priority level
1101 * 0b111..Set to lowest priority, Level 8
1102 */
1103#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
1104#define ADC_TCTRL_TDLY_MASK (0xF0000U)
1105#define ADC_TCTRL_TDLY_SHIFT (16U)
1106/*! TDLY - Trigger delay select
1107 */
1108#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
1109#define ADC_TCTRL_TCMD_MASK (0xF000000U)
1110#define ADC_TCTRL_TCMD_SHIFT (24U)
1111/*! TCMD - Trigger command select
1112 * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
1113 * 0b0001..CMD1 is executed
1114 * 0b0010-0b1110..Corresponding CMD is executed
1115 * 0b1111..CMD15 is executed
1116 */
1117#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
1118/*! @} */
1119
1120/* The count of ADC_TCTRL */
1121#define ADC_TCTRL_COUNT (8U)
1122
1123/*! @name CMDL - ADC Command Low Buffer Register */
1124/*! @{ */
1125#define ADC_CMDL_ADCH_MASK (0x1FU)
1126#define ADC_CMDL_ADCH_SHIFT (0U)
1127/*! ADCH - Input channel select
1128 * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
1129 * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
1130 * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
1131 * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
1132 * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
1133 * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
1134 * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
1135 */
1136#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
1137#define ADC_CMDL_ABSEL_MASK (0x20U)
1138#define ADC_CMDL_ABSEL_SHIFT (5U)
1139/*! ABSEL - A-side vs. B-side Select
1140 * 0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB).
1141 * 0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA).
1142 */
1143#define ADC_CMDL_ABSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
1144#define ADC_CMDL_DIFF_MASK (0x40U)
1145#define ADC_CMDL_DIFF_SHIFT (6U)
1146/*! DIFF - Differential Mode Enable
1147 * 0b0..Single-ended mode.
1148 * 0b1..Differential mode.
1149 */
1150#define ADC_CMDL_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)
1151#define ADC_CMDL_CSCALE_MASK (0x2000U)
1152#define ADC_CMDL_CSCALE_SHIFT (13U)
1153/*! CSCALE - Channel Scale
1154 * 0b0..Scale selected analog channel (Factor of 30/64)
1155 * 0b1..(Default) Full scale (Factor of 1)
1156 */
1157#define ADC_CMDL_CSCALE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)
1158/*! @} */
1159
1160/* The count of ADC_CMDL */
1161#define ADC_CMDL_COUNT (15U)
1162
1163/*! @name CMDH - ADC Command High Buffer Register */
1164/*! @{ */
1165#define ADC_CMDH_CMPEN_MASK (0x3U)
1166#define ADC_CMDH_CMPEN_SHIFT (0U)
1167/*! CMPEN - Compare Function Enable
1168 * 0b00..Compare disabled.
1169 * 0b01..Reserved
1170 * 0b10..Compare enabled. Store on true.
1171 * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
1172 */
1173#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
1174#define ADC_CMDH_LWI_MASK (0x80U)
1175#define ADC_CMDH_LWI_SHIFT (7U)
1176/*! LWI - Loop with Increment
1177 * 0b0..Auto channel increment disabled
1178 * 0b1..Auto channel increment enabled
1179 */
1180#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
1181#define ADC_CMDH_STS_MASK (0x700U)
1182#define ADC_CMDH_STS_SHIFT (8U)
1183/*! STS - Sample Time Select
1184 * 0b000..Minimum sample time of 3 ADCK cycles.
1185 * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
1186 * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
1187 * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
1188 * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
1189 * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
1190 * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
1191 * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
1192 */
1193#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
1194#define ADC_CMDH_AVGS_MASK (0x7000U)
1195#define ADC_CMDH_AVGS_SHIFT (12U)
1196/*! AVGS - Hardware Average Select
1197 * 0b000..Single conversion.
1198 * 0b001..2 conversions averaged.
1199 * 0b010..4 conversions averaged.
1200 * 0b011..8 conversions averaged.
1201 * 0b100..16 conversions averaged.
1202 * 0b101..32 conversions averaged.
1203 * 0b110..64 conversions averaged.
1204 * 0b111..128 conversions averaged.
1205 */
1206#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
1207#define ADC_CMDH_LOOP_MASK (0xF0000U)
1208#define ADC_CMDH_LOOP_SHIFT (16U)
1209/*! LOOP - Loop Count Select
1210 * 0b0000..Looping not enabled. Command executes 1 time.
1211 * 0b0001..Loop 1 time. Command executes 2 times.
1212 * 0b0010..Loop 2 times. Command executes 3 times.
1213 * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
1214 * 0b1111..Loop 15 times. Command executes 16 times.
1215 */
1216#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
1217#define ADC_CMDH_NEXT_MASK (0xF000000U)
1218#define ADC_CMDH_NEXT_SHIFT (24U)
1219/*! NEXT - Next Command Select
1220 * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
1221 * trigger pending, begin command associated with lower priority trigger.
1222 * 0b0001..Select CMD1 command buffer register as next command.
1223 * 0b0010-0b1110..Select corresponding CMD command buffer register as next command
1224 * 0b1111..Select CMD15 command buffer register as next command.
1225 */
1226#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
1227/*! @} */
1228
1229/* The count of ADC_CMDH */
1230#define ADC_CMDH_COUNT (15U)
1231
1232/*! @name CV - Compare Value Register */
1233/*! @{ */
1234#define ADC_CV_CVL_MASK (0xFFFFU)
1235#define ADC_CV_CVL_SHIFT (0U)
1236/*! CVL - Compare Value Low.
1237 */
1238#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
1239#define ADC_CV_CVH_MASK (0xFFFF0000U)
1240#define ADC_CV_CVH_SHIFT (16U)
1241/*! CVH - Compare Value High.
1242 */
1243#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
1244/*! @} */
1245
1246/* The count of ADC_CV */
1247#define ADC_CV_COUNT (4U)
1248
1249/*! @name RESFIFO - ADC Data Result FIFO Register */
1250/*! @{ */
1251#define ADC_RESFIFO_D_MASK (0xFFFFU)
1252#define ADC_RESFIFO_D_SHIFT (0U)
1253/*! D - Data result
1254 */
1255#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
1256#define ADC_RESFIFO_TSRC_MASK (0x70000U)
1257#define ADC_RESFIFO_TSRC_SHIFT (16U)
1258/*! TSRC - Trigger Source
1259 * 0b000..Trigger source 0 initiated this conversion.
1260 * 0b001..Trigger source 1 initiated this conversion.
1261 * 0b010-0b110..Corresponding trigger source initiated this conversion.
1262 * 0b111..Trigger source 7 initiated this conversion.
1263 */
1264#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
1265#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U)
1266#define ADC_RESFIFO_LOOPCNT_SHIFT (20U)
1267/*! LOOPCNT - Loop count value
1268 * 0b0000..Result is from initial conversion in command.
1269 * 0b0001..Result is from second conversion in command.
1270 * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
1271 * 0b1111..Result is from 16th conversion in command.
1272 */
1273#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
1274#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U)
1275#define ADC_RESFIFO_CMDSRC_SHIFT (24U)
1276/*! CMDSRC - Command Buffer Source
1277 * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
1278 * prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
1279 * 0b0001..CMD1 buffer used as control settings for this conversion.
1280 * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
1281 * 0b1111..CMD15 buffer used as control settings for this conversion.
1282 */
1283#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
1284#define ADC_RESFIFO_VALID_MASK (0x80000000U)
1285#define ADC_RESFIFO_VALID_SHIFT (31U)
1286/*! VALID - FIFO entry is valid
1287 * 0b0..FIFO is empty. Discard any read from RESFIFO.
1288 * 0b1..FIFO record read from RESFIFO is valid.
1289 */
1290#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
1291/*! @} */
1292
1293
1294/*!
1295 * @}
1296 */ /* end of group ADC_Register_Masks */
1297
1298
1299/* ADC - Peripheral instance base addresses */
1300/** Peripheral ADMA__ADC0 base address */
1301#define ADMA__ADC0_BASE (0x5A880000u)
1302/** Peripheral ADMA__ADC0 base pointer */
1303#define ADMA__ADC0 ((ADC_Type *)ADMA__ADC0_BASE)
1304/** Array initializer of ADC peripheral base addresses */
1305#define ADC_BASE_ADDRS { ADMA__ADC0_BASE }
1306/** Array initializer of ADC peripheral base pointers */
1307#define ADC_BASE_PTRS { ADMA__ADC0 }
1308/** Interrupt vectors for the ADC peripheral type */
1309#define ADC_IRQS { ADMA_ADC0_INT_IRQn }
1310
1311/*!
1312 * @}
1313 */ /* end of group ADC_Peripheral_Access_Layer */
1314
1315
1316/* ----------------------------------------------------------------------------
1317 -- APBH Peripheral Access Layer
1318 ---------------------------------------------------------------------------- */
1319
1320/*!
1321 * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer
1322 * @{
1323 */
1324
1325/** APBH - Register Layout Typedef */
1326typedef struct {
1327 struct { /* offset: 0x0 */
1328 __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */
1329 __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */
1330 __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */
1331 __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */
1332 } CTRL0;
1333 struct { /* offset: 0x10 */
1334 __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */
1335 __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */
1336 __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */
1337 __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */
1338 } CTRL1;
1339 struct { /* offset: 0x20 */
1340 __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */
1341 __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */
1342 __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */
1343 __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */
1344 } CTRL2;
1345 struct { /* offset: 0x30 */
1346 __IO uint32_t RW; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */
1347 __IO uint32_t SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */
1348 __IO uint32_t CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */
1349 __IO uint32_t TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */
1350 } CHANNEL_CTRL;
1351 uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */
1352 uint8_t RESERVED_0[12];
1353 __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */
1354 uint8_t RESERVED_1[12];
1355 __IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60 */
1356 uint8_t RESERVED_2[156];
1357 struct { /* offset: 0x100, array step: 0x70 */
1358 __I uint32_t CH_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, array offset: 0x100, array step: 0x70 */
1359 uint8_t RESERVED_0[12];
1360 __IO uint32_t CH_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, array offset: 0x110, array step: 0x70 */
1361 uint8_t RESERVED_1[12];
1362 __I uint32_t CH_CMD; /**< APBH DMA Channel n Command Register, array offset: 0x120, array step: 0x70 */
1363 uint8_t RESERVED_2[12];
1364 __I uint32_t CH_BAR; /**< APBH DMA Channel n Buffer Address Register, array offset: 0x130, array step: 0x70 */
1365 uint8_t RESERVED_3[12];
1366 __IO uint32_t CH_SEMA; /**< APBH DMA Channel n Semaphore Register, array offset: 0x140, array step: 0x70 */
1367 uint8_t RESERVED_4[12];
1368 __I uint32_t CH_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x150, array step: 0x70 */
1369 uint8_t RESERVED_5[12];
1370 __I uint32_t CH_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x160, array step: 0x70 */
1371 uint8_t RESERVED_6[12];
1372 } CH_CFGn[16];
1373 __I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */
1374} APBH_Type;
1375
1376/* ----------------------------------------------------------------------------
1377 -- APBH Register Masks
1378 ---------------------------------------------------------------------------- */
1379
1380/*!
1381 * @addtogroup APBH_Register_Masks APBH Register Masks
1382 * @{
1383 */
1384
1385/*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */
1386/*! @{ */
1387#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU)
1388#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U)
1389/*! CLKGATE_CHANNEL - CLKGATE_CHANNEL
1390 * 0b0000000000000001..
1391 * 0b0000000000000010..
1392 * 0b0000000000000100..
1393 * 0b0000000000001000..
1394 * 0b0000000000010000..
1395 * 0b0000000000100000..
1396 * 0b0000000001000000..
1397 * 0b0000000010000000..
1398 * 0b0000000100000000..
1399 */
1400#define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK)
1401#define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U)
1402#define APBH_CTRL0_APB_BURST_EN_SHIFT (28U)
1403/*! APB_BURST_EN - APB_BURST_EN
1404 */
1405#define APBH_CTRL0_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK)
1406#define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U)
1407#define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U)
1408/*! AHB_BURST8_EN - AHB_BURST8_EN
1409 */
1410#define APBH_CTRL0_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK)
1411#define APBH_CTRL0_CLKGATE_MASK (0x40000000U)
1412#define APBH_CTRL0_CLKGATE_SHIFT (30U)
1413/*! CLKGATE - CLKGATE
1414 */
1415#define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK)
1416#define APBH_CTRL0_SFTRST_MASK (0x80000000U)
1417#define APBH_CTRL0_SFTRST_SHIFT (31U)
1418/*! SFTRST - SFTRST
1419 */
1420#define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK)
1421/*! @} */
1422
1423/*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */
1424/*! @{ */
1425#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U)
1426#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U)
1427/*! CH0_CMDCMPLT_IRQ - CH0_CMDCMPLT_IRQ
1428 */
1429#define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK)
1430#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U)
1431#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U)
1432/*! CH1_CMDCMPLT_IRQ - CH1_CMDCMPLT_IRQ
1433 */
1434#define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK)
1435#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U)
1436#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U)
1437/*! CH2_CMDCMPLT_IRQ - CH2_CMDCMPLT_IRQ
1438 */
1439#define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK)
1440#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U)
1441#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U)
1442/*! CH3_CMDCMPLT_IRQ - CH3_CMDCMPLT_IRQ
1443 */
1444#define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK)
1445#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U)
1446#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U)
1447/*! CH4_CMDCMPLT_IRQ - CH4_CMDCMPLT_IRQ
1448 */
1449#define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK)
1450#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U)
1451#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U)
1452/*! CH5_CMDCMPLT_IRQ - CH5_CMDCMPLT_IRQ
1453 */
1454#define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK)
1455#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U)
1456#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U)
1457/*! CH6_CMDCMPLT_IRQ - CH6_CMDCMPLT_IRQ
1458 */
1459#define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK)
1460#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U)
1461#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U)
1462/*! CH7_CMDCMPLT_IRQ - CH7_CMDCMPLT_IRQ
1463 */
1464#define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK)
1465#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U)
1466#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U)
1467/*! CH8_CMDCMPLT_IRQ - CH8_CMDCMPLT_IRQ
1468 */
1469#define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK)
1470#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U)
1471#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U)
1472/*! CH9_CMDCMPLT_IRQ - CH9_CMDCMPLT_IRQ
1473 */
1474#define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK)
1475#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U)
1476#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U)
1477/*! CH10_CMDCMPLT_IRQ - CH10_CMDCMPLT_IRQ
1478 */
1479#define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK)
1480#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U)
1481#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U)
1482/*! CH11_CMDCMPLT_IRQ - CH11_CMDCMPLT_IRQ
1483 */
1484#define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK)
1485#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
1486#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U)
1487/*! CH12_CMDCMPLT_IRQ - CH12_CMDCMPLT_IRQ
1488 */
1489#define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK)
1490#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
1491#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U)
1492/*! CH13_CMDCMPLT_IRQ - CH13_CMDCMPLT_IRQ
1493 */
1494#define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK)
1495#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
1496#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U)
1497/*! CH14_CMDCMPLT_IRQ - CH14_CMDCMPLT_IRQ
1498 */
1499#define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK)
1500#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
1501#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U)
1502/*! CH15_CMDCMPLT_IRQ - CH15_CMDCMPLT_IRQ
1503 */
1504#define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK)
1505#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
1506#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
1507/*! CH0_CMDCMPLT_IRQ_EN - CH0_CMDCMPLT_IRQ_EN
1508 */
1509#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK)
1510#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
1511#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
1512/*! CH1_CMDCMPLT_IRQ_EN - CH1_CMDCMPLT_IRQ_EN
1513 */
1514#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK)
1515#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
1516#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
1517/*! CH2_CMDCMPLT_IRQ_EN - CH2_CMDCMPLT_IRQ_EN
1518 */
1519#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK)
1520#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
1521#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
1522/*! CH3_CMDCMPLT_IRQ_EN - CH3_CMDCMPLT_IRQ_EN
1523 */
1524#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK)
1525#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
1526#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
1527/*! CH4_CMDCMPLT_IRQ_EN - CH4_CMDCMPLT_IRQ_EN
1528 */
1529#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK)
1530#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
1531#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
1532/*! CH5_CMDCMPLT_IRQ_EN - CH5_CMDCMPLT_IRQ_EN
1533 */
1534#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK)
1535#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
1536#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
1537/*! CH6_CMDCMPLT_IRQ_EN - CH6_CMDCMPLT_IRQ_EN
1538 */
1539#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK)
1540#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
1541#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
1542/*! CH7_CMDCMPLT_IRQ_EN - CH7_CMDCMPLT_IRQ_EN
1543 */
1544#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK)
1545#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
1546#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
1547/*! CH8_CMDCMPLT_IRQ_EN - CH8_CMDCMPLT_IRQ_EN
1548 */
1549#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK)
1550#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
1551#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
1552/*! CH9_CMDCMPLT_IRQ_EN - CH9_CMDCMPLT_IRQ_EN
1553 */
1554#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK)
1555#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
1556#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
1557/*! CH10_CMDCMPLT_IRQ_EN - CH10_CMDCMPLT_IRQ_EN
1558 */
1559#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
1560#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
1561#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
1562/*! CH11_CMDCMPLT_IRQ_EN - CH11_CMDCMPLT_IRQ_EN
1563 */
1564#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK)
1565#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
1566#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
1567/*! CH12_CMDCMPLT_IRQ_EN - CH12_CMDCMPLT_IRQ_EN
1568 */
1569#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK)
1570#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
1571#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
1572/*! CH13_CMDCMPLT_IRQ_EN - CH13_CMDCMPLT_IRQ_EN
1573 */
1574#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK)
1575#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
1576#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
1577/*! CH14_CMDCMPLT_IRQ_EN - CH14_CMDCMPLT_IRQ_EN
1578 */
1579#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK)
1580#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
1581#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
1582/*! CH15_CMDCMPLT_IRQ_EN - CH15_CMDCMPLT_IRQ_EN
1583 */
1584#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK)
1585/*! @} */
1586
1587/*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */
1588/*! @{ */
1589#define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U)
1590#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U)
1591/*! CH0_ERROR_IRQ - CH0_ERROR_IRQ
1592 */
1593#define APBH_CTRL2_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK)
1594#define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U)
1595#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U)
1596/*! CH1_ERROR_IRQ - CH1_ERROR_IRQ
1597 */
1598#define APBH_CTRL2_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK)
1599#define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U)
1600#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U)
1601/*! CH2_ERROR_IRQ - CH2_ERROR_IRQ
1602 */
1603#define APBH_CTRL2_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK)
1604#define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U)
1605#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U)
1606/*! CH3_ERROR_IRQ - CH3_ERROR_IRQ
1607 */
1608#define APBH_CTRL2_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK)
1609#define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U)
1610#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U)
1611/*! CH4_ERROR_IRQ - CH4_ERROR_IRQ
1612 */
1613#define APBH_CTRL2_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK)
1614#define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U)
1615#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U)
1616/*! CH5_ERROR_IRQ - CH5_ERROR_IRQ
1617 */
1618#define APBH_CTRL2_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK)
1619#define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U)
1620#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U)
1621/*! CH6_ERROR_IRQ - CH6_ERROR_IRQ
1622 */
1623#define APBH_CTRL2_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK)
1624#define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U)
1625#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U)
1626/*! CH7_ERROR_IRQ - CH7_ERROR_IRQ
1627 */
1628#define APBH_CTRL2_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK)
1629#define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U)
1630#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U)
1631/*! CH8_ERROR_IRQ - CH8_ERROR_IRQ
1632 */
1633#define APBH_CTRL2_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK)
1634#define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U)
1635#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U)
1636/*! CH9_ERROR_IRQ - CH9_ERROR_IRQ
1637 */
1638#define APBH_CTRL2_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK)
1639#define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U)
1640#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U)
1641/*! CH10_ERROR_IRQ - CH10_ERROR_IRQ
1642 */
1643#define APBH_CTRL2_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK)
1644#define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U)
1645#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U)
1646/*! CH11_ERROR_IRQ - CH11_ERROR_IRQ
1647 */
1648#define APBH_CTRL2_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK)
1649#define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U)
1650#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U)
1651/*! CH12_ERROR_IRQ - CH12_ERROR_IRQ
1652 */
1653#define APBH_CTRL2_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK)
1654#define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U)
1655#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U)
1656/*! CH13_ERROR_IRQ - CH13_ERROR_IRQ
1657 */
1658#define APBH_CTRL2_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK)
1659#define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U)
1660#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U)
1661/*! CH14_ERROR_IRQ - CH14_ERROR_IRQ
1662 */
1663#define APBH_CTRL2_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK)
1664#define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U)
1665#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U)
1666/*! CH15_ERROR_IRQ - CH15_ERROR_IRQ
1667 */
1668#define APBH_CTRL2_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK)
1669#define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U)
1670#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U)
1671/*! CH0_ERROR_STATUS - CH0_ERROR_STATUS
1672 * 0b0..An early termination from the device causes error IRQ.
1673 * 0b1..An AHB bus error causes error IRQ.
1674 */
1675#define APBH_CTRL2_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK)
1676#define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U)
1677#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U)
1678/*! CH1_ERROR_STATUS - CH1_ERROR_STATUS
1679 * 0b0..An early termination from the device causes error IRQ.
1680 * 0b1..An AHB bus error causes error IRQ.
1681 */
1682#define APBH_CTRL2_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK)
1683#define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U)
1684#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U)
1685/*! CH2_ERROR_STATUS - CH2_ERROR_STATUS
1686 * 0b0..An early termination from the device causes error IRQ.
1687 * 0b1..An AHB bus error causes error IRQ.
1688 */
1689#define APBH_CTRL2_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK)
1690#define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U)
1691#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U)
1692/*! CH3_ERROR_STATUS - CH3_ERROR_STATUS
1693 * 0b0..An early termination from the device causes error IRQ.
1694 * 0b1..An AHB bus error causes error IRQ.
1695 */
1696#define APBH_CTRL2_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK)
1697#define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U)
1698#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U)
1699/*! CH4_ERROR_STATUS - CH4_ERROR_STATUS
1700 * 0b0..An early termination from the device causes error IRQ.
1701 * 0b1..An AHB bus error causes error IRQ.
1702 */
1703#define APBH_CTRL2_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK)
1704#define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U)
1705#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U)
1706/*! CH5_ERROR_STATUS - CH5_ERROR_STATUS
1707 * 0b0..An early termination from the device causes error IRQ.
1708 * 0b1..An AHB bus error causes error IRQ.
1709 */
1710#define APBH_CTRL2_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK)
1711#define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U)
1712#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U)
1713/*! CH6_ERROR_STATUS - CH6_ERROR_STATUS
1714 * 0b0..An early termination from the device causes error IRQ.
1715 * 0b1..An AHB bus error causes error IRQ.
1716 */
1717#define APBH_CTRL2_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK)
1718#define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U)
1719#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U)
1720/*! CH7_ERROR_STATUS - CH7_ERROR_STATUS
1721 * 0b0..An early termination from the device causes error IRQ.
1722 * 0b1..An AHB bus error causes error IRQ.
1723 */
1724#define APBH_CTRL2_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK)
1725#define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U)
1726#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U)
1727/*! CH8_ERROR_STATUS - CH8_ERROR_STATUS
1728 * 0b0..An early termination from the device causes error IRQ.
1729 * 0b1..An AHB bus error causes error IRQ.
1730 */
1731#define APBH_CTRL2_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK)
1732#define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U)
1733#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U)
1734/*! CH9_ERROR_STATUS - CH9_ERROR_STATUS
1735 * 0b0..An early termination from the device causes error IRQ.
1736 * 0b1..An AHB bus error causes error IRQ.
1737 */
1738#define APBH_CTRL2_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK)
1739#define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U)
1740#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U)
1741/*! CH10_ERROR_STATUS - CH10_ERROR_STATUS
1742 * 0b0..An early termination from the device causes error IRQ.
1743 * 0b1..An AHB bus error causes error IRQ.
1744 */
1745#define APBH_CTRL2_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK)
1746#define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U)
1747#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U)
1748/*! CH11_ERROR_STATUS - CH11_ERROR_STATUS
1749 * 0b0..An early termination from the device causes error IRQ.
1750 * 0b1..An AHB bus error causes error IRQ.
1751 */
1752#define APBH_CTRL2_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK)
1753#define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U)
1754#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U)
1755/*! CH12_ERROR_STATUS - CH12_ERROR_STATUS
1756 * 0b0..An early termination from the device causes error IRQ.
1757 * 0b1..An AHB bus error causes error IRQ.
1758 */
1759#define APBH_CTRL2_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK)
1760#define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U)
1761#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U)
1762/*! CH13_ERROR_STATUS - CH13_ERROR_STATUS
1763 * 0b0..An early termination from the device causes error IRQ.
1764 * 0b1..An AHB bus error causes error IRQ.
1765 */
1766#define APBH_CTRL2_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK)
1767#define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U)
1768#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U)
1769/*! CH14_ERROR_STATUS - CH14_ERROR_STATUS
1770 * 0b0..An early termination from the device causes error IRQ.
1771 * 0b1..An AHB bus error causes error IRQ.
1772 */
1773#define APBH_CTRL2_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK)
1774#define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U)
1775#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U)
1776/*! CH15_ERROR_STATUS - CH15_ERROR_STATUS
1777 * 0b0..An early termination from the device causes error IRQ.
1778 * 0b1..An AHB bus error causes error IRQ.
1779 */
1780#define APBH_CTRL2_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK)
1781/*! @} */
1782
1783/*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */
1784/*! @{ */
1785#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU)
1786#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U)
1787/*! FREEZE_CHANNEL - FREEZE_CHANNEL
1788 * 0b0000000000000001..
1789 * 0b0000000000000010..
1790 * 0b0000000000000100..
1791 * 0b0000000000001000..
1792 * 0b0000000000010000..
1793 * 0b0000000000100000..
1794 * 0b0000000001000000..
1795 * 0b0000000010000000..
1796 * 0b0000000100000000..
1797 */
1798#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK)
1799#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U)
1800#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U)
1801/*! RESET_CHANNEL - RESET_CHANNEL
1802 * 0b0000000000000001..
1803 * 0b0000000000000010..
1804 * 0b0000000000000100..
1805 * 0b0000000000001000..
1806 * 0b0000000000010000..
1807 * 0b0000000000100000..
1808 * 0b0000000001000000..
1809 * 0b0000000010000000..
1810 * 0b0000000100000000..
1811 */
1812#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK)
1813/*! @} */
1814
1815/*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */
1816/*! @{ */
1817#define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U)
1818#define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U)
1819/*! CH0 - CH0
1820 */
1821#define APBH_DMA_BURST_SIZE_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK)
1822#define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU)
1823#define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U)
1824/*! CH1 - CH1
1825 */
1826#define APBH_DMA_BURST_SIZE_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK)
1827#define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U)
1828#define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U)
1829/*! CH2 - CH2
1830 */
1831#define APBH_DMA_BURST_SIZE_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK)
1832#define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U)
1833#define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U)
1834/*! CH3 - CH3
1835 */
1836#define APBH_DMA_BURST_SIZE_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK)
1837#define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U)
1838#define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U)
1839/*! CH4 - CH4
1840 */
1841#define APBH_DMA_BURST_SIZE_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK)
1842#define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U)
1843#define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U)
1844/*! CH5 - CH5
1845 */
1846#define APBH_DMA_BURST_SIZE_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK)
1847#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U)
1848#define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U)
1849/*! CH6 - CH6
1850 */
1851#define APBH_DMA_BURST_SIZE_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK)
1852#define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U)
1853#define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U)
1854/*! CH7 - CH7
1855 */
1856#define APBH_DMA_BURST_SIZE_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK)
1857#define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U)
1858#define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U)
1859/*! CH8 - CH8
1860 * 0b00..
1861 * 0b01..
1862 * 0b10..
1863 */
1864#define APBH_DMA_BURST_SIZE_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK)
1865/*! @} */
1866
1867/*! @name DEBUG - AHB to APBH DMA Debug Register */
1868/*! @{ */
1869#define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U)
1870#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U)
1871/*! GPMI_ONE_FIFO - GPMI_ONE_FIFO
1872 */
1873#define APBH_DEBUG_GPMI_ONE_FIFO(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK)
1874/*! @} */
1875
1876/*! @name CH_CURCMDAR - APBH DMA Channel n Current Command Address Register */
1877/*! @{ */
1878#define APBH_CH_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
1879#define APBH_CH_CURCMDAR_CMD_ADDR_SHIFT (0U)
1880/*! CMD_ADDR - CMD_ADDR
1881 */
1882#define APBH_CH_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_CURCMDAR_CMD_ADDR_MASK)
1883/*! @} */
1884
1885/* The count of APBH_CH_CURCMDAR */
1886#define APBH_CH_CURCMDAR_COUNT (16U)
1887
1888/*! @name CH_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
1889/*! @{ */
1890#define APBH_CH_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
1891#define APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT (0U)
1892/*! CMD_ADDR - CMD_ADDR
1893 */
1894#define APBH_CH_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_NXTCMDAR_CMD_ADDR_MASK)
1895/*! @} */
1896
1897/* The count of APBH_CH_NXTCMDAR */
1898#define APBH_CH_NXTCMDAR_COUNT (16U)
1899
1900/*! @name CH_CMD - APBH DMA Channel n Command Register */
1901/*! @{ */
1902#define APBH_CH_CMD_COMMAND_MASK (0x3U)
1903#define APBH_CH_CMD_COMMAND_SHIFT (0U)
1904/*! COMMAND - COMMAND
1905 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
1906 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
1907 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
1908 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained
1909 * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain
1910 * pointer if the peripheral sense line is false.
1911 */
1912#define APBH_CH_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_COMMAND_SHIFT)) & APBH_CH_CMD_COMMAND_MASK)
1913#define APBH_CH_CMD_CHAIN_MASK (0x4U)
1914#define APBH_CH_CMD_CHAIN_SHIFT (2U)
1915/*! CHAIN - CHAIN
1916 */
1917#define APBH_CH_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CHAIN_SHIFT)) & APBH_CH_CMD_CHAIN_MASK)
1918#define APBH_CH_CMD_IRQONCMPLT_MASK (0x8U)
1919#define APBH_CH_CMD_IRQONCMPLT_SHIFT (3U)
1920/*! IRQONCMPLT - IRQONCMPLT
1921 */
1922#define APBH_CH_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_IRQONCMPLT_SHIFT)) & APBH_CH_CMD_IRQONCMPLT_MASK)
1923#define APBH_CH_CMD_NANDLOCK_MASK (0x10U)
1924#define APBH_CH_CMD_NANDLOCK_SHIFT (4U)
1925/*! NANDLOCK - NANDLOCK
1926 */
1927#define APBH_CH_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDLOCK_SHIFT)) & APBH_CH_CMD_NANDLOCK_MASK)
1928#define APBH_CH_CMD_NANDWAIT4READY_MASK (0x20U)
1929#define APBH_CH_CMD_NANDWAIT4READY_SHIFT (5U)
1930/*! NANDWAIT4READY - NANDWAIT4READY
1931 */
1932#define APBH_CH_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH_CMD_NANDWAIT4READY_MASK)
1933#define APBH_CH_CMD_SEMAPHORE_MASK (0x40U)
1934#define APBH_CH_CMD_SEMAPHORE_SHIFT (6U)
1935/*! SEMAPHORE - SEMAPHORE
1936 */
1937#define APBH_CH_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_SEMAPHORE_SHIFT)) & APBH_CH_CMD_SEMAPHORE_MASK)
1938#define APBH_CH_CMD_WAIT4ENDCMD_MASK (0x80U)
1939#define APBH_CH_CMD_WAIT4ENDCMD_SHIFT (7U)
1940/*! WAIT4ENDCMD - WAIT4ENDCMD
1941 */
1942#define APBH_CH_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH_CMD_WAIT4ENDCMD_MASK)
1943#define APBH_CH_CMD_HALTONTERMINATE_MASK (0x100U)
1944#define APBH_CH_CMD_HALTONTERMINATE_SHIFT (8U)
1945/*! HALTONTERMINATE - HALTONTERMINATE
1946 */
1947#define APBH_CH_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH_CMD_HALTONTERMINATE_MASK)
1948#define APBH_CH_CMD_CMDWORDS_MASK (0xF000U)
1949#define APBH_CH_CMD_CMDWORDS_SHIFT (12U)
1950/*! CMDWORDS - CMDWORDS
1951 */
1952#define APBH_CH_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CMDWORDS_SHIFT)) & APBH_CH_CMD_CMDWORDS_MASK)
1953#define APBH_CH_CMD_XFER_COUNT_MASK (0xFFFF0000U)
1954#define APBH_CH_CMD_XFER_COUNT_SHIFT (16U)
1955/*! XFER_COUNT - XFER_COUNT
1956 */
1957#define APBH_CH_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_XFER_COUNT_SHIFT)) & APBH_CH_CMD_XFER_COUNT_MASK)
1958/*! @} */
1959
1960/* The count of APBH_CH_CMD */
1961#define APBH_CH_CMD_COUNT (16U)
1962
1963/*! @name CH_BAR - APBH DMA Channel n Buffer Address Register */
1964/*! @{ */
1965#define APBH_CH_BAR_ADDRESS_MASK (0xFFFFFFFFU)
1966#define APBH_CH_BAR_ADDRESS_SHIFT (0U)
1967/*! ADDRESS - ADDRESS
1968 */
1969#define APBH_CH_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_BAR_ADDRESS_SHIFT)) & APBH_CH_BAR_ADDRESS_MASK)
1970/*! @} */
1971
1972/* The count of APBH_CH_BAR */
1973#define APBH_CH_BAR_COUNT (16U)
1974
1975/*! @name CH_SEMA - APBH DMA Channel n Semaphore Register */
1976/*! @{ */
1977#define APBH_CH_SEMA_INCREMENT_SEMA_MASK (0xFFU)
1978#define APBH_CH_SEMA_INCREMENT_SEMA_SHIFT (0U)
1979/*! INCREMENT_SEMA - INCREMENT_SEMA
1980 */
1981#define APBH_CH_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH_SEMA_INCREMENT_SEMA_MASK)
1982#define APBH_CH_SEMA_PHORE_MASK (0xFF0000U)
1983#define APBH_CH_SEMA_PHORE_SHIFT (16U)
1984/*! PHORE - PHORE
1985 */
1986#define APBH_CH_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_PHORE_SHIFT)) & APBH_CH_SEMA_PHORE_MASK)
1987/*! @} */
1988
1989/* The count of APBH_CH_SEMA */
1990#define APBH_CH_SEMA_COUNT (16U)
1991
1992/*! @name CH_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
1993/*! @{ */
1994#define APBH_CH_DEBUG1_STATEMACHINE_MASK (0x1FU)
1995#define APBH_CH_DEBUG1_STATEMACHINE_SHIFT (0U)
1996/*! STATEMACHINE - STATEMACHINE
1997 * 0b00000..This is the idle state of the DMA state machine.
1998 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
1999 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
2000 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
2001 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
2002 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
2003 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the
2004 * PIO words when PIO count is greater than 1.
2005 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
2006 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
2007 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
2008 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
2009 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
2010 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
2011 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
2012 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
2013 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
2014 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
2015 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and
2016 * effectively halts. A channel reset is required to exit this state
2017 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
2018 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device
2019 * indicates that the external device is ready.
2020 */
2021#define APBH_CH_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH_DEBUG1_STATEMACHINE_MASK)
2022#define APBH_CH_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
2023#define APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
2024/*! WR_FIFO_FULL - WR_FIFO_FULL
2025 */
2026#define APBH_CH_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_FULL_MASK)
2027#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
2028#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
2029/*! WR_FIFO_EMPTY - WR_FIFO_EMPTY
2030 */
2031#define APBH_CH_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK)
2032#define APBH_CH_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
2033#define APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
2034/*! RD_FIFO_FULL - RD_FIFO_FULL
2035 */
2036#define APBH_CH_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_FULL_MASK)
2037#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
2038#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
2039/*! RD_FIFO_EMPTY - RD_FIFO_EMPTY
2040 */
2041#define APBH_CH_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK)
2042#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
2043#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
2044/*! NEXTCMDADDRVALID - NEXTCMDADDRVALID
2045 */
2046#define APBH_CH_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK)
2047#define APBH_CH_DEBUG1_READY_MASK (0x4000000U)
2048#define APBH_CH_DEBUG1_READY_SHIFT (26U)
2049/*! READY - READY
2050 */
2051#define APBH_CH_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_READY_SHIFT)) & APBH_CH_DEBUG1_READY_MASK)
2052#define APBH_CH_DEBUG1_END_MASK (0x10000000U)
2053#define APBH_CH_DEBUG1_END_SHIFT (28U)
2054/*! END - END
2055 */
2056#define APBH_CH_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_END_SHIFT)) & APBH_CH_DEBUG1_END_MASK)
2057#define APBH_CH_DEBUG1_KICK_MASK (0x20000000U)
2058#define APBH_CH_DEBUG1_KICK_SHIFT (29U)
2059/*! KICK - KICK
2060 */
2061#define APBH_CH_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_KICK_SHIFT)) & APBH_CH_DEBUG1_KICK_MASK)
2062#define APBH_CH_DEBUG1_BURST_MASK (0x40000000U)
2063#define APBH_CH_DEBUG1_BURST_SHIFT (30U)
2064/*! BURST - BURST
2065 */
2066#define APBH_CH_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_BURST_SHIFT)) & APBH_CH_DEBUG1_BURST_MASK)
2067#define APBH_CH_DEBUG1_REQ_MASK (0x80000000U)
2068#define APBH_CH_DEBUG1_REQ_SHIFT (31U)
2069/*! REQ - REQ
2070 */
2071#define APBH_CH_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_REQ_SHIFT)) & APBH_CH_DEBUG1_REQ_MASK)
2072/*! @} */
2073
2074/* The count of APBH_CH_DEBUG1 */
2075#define APBH_CH_DEBUG1_COUNT (16U)
2076
2077/*! @name CH_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
2078/*! @{ */
2079#define APBH_CH_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
2080#define APBH_CH_DEBUG2_AHB_BYTES_SHIFT (0U)
2081/*! AHB_BYTES - AHB_BYTES
2082 */
2083#define APBH_CH_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH_DEBUG2_AHB_BYTES_MASK)
2084#define APBH_CH_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
2085#define APBH_CH_DEBUG2_APB_BYTES_SHIFT (16U)
2086/*! APB_BYTES - APB_BYTES
2087 */
2088#define APBH_CH_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH_DEBUG2_APB_BYTES_MASK)
2089/*! @} */
2090
2091/* The count of APBH_CH_DEBUG2 */
2092#define APBH_CH_DEBUG2_COUNT (16U)
2093
2094/*! @name VERSION - APBH Bridge Version Register */
2095/*! @{ */
2096#define APBH_VERSION_STEP_MASK (0xFFFFU)
2097#define APBH_VERSION_STEP_SHIFT (0U)
2098/*! STEP - STEP
2099 */
2100#define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK)
2101#define APBH_VERSION_MINOR_MASK (0xFF0000U)
2102#define APBH_VERSION_MINOR_SHIFT (16U)
2103/*! MINOR - MINOR
2104 */
2105#define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK)
2106#define APBH_VERSION_MAJOR_MASK (0xFF000000U)
2107#define APBH_VERSION_MAJOR_SHIFT (24U)
2108/*! MAJOR - MAJOR
2109 */
2110#define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK)
2111/*! @} */
2112
2113
2114/*!
2115 * @}
2116 */ /* end of group APBH_Register_Masks */
2117
2118
2119/* APBH - Peripheral instance base addresses */
2120/** Peripheral CONNECTIVITY__APBH base address */
2121#define CONNECTIVITY__APBH_BASE (0x5B810000u)
2122/** Peripheral CONNECTIVITY__APBH base pointer */
2123#define CONNECTIVITY__APBH ((APBH_Type *)CONNECTIVITY__APBH_BASE)
2124/** Array initializer of APBH peripheral base addresses */
2125#define APBH_BASE_ADDRS { CONNECTIVITY__APBH_BASE }
2126/** Array initializer of APBH peripheral base pointers */
2127#define APBH_BASE_PTRS { CONNECTIVITY__APBH }
2128/** Interrupt vectors for the APBH peripheral type */
2129#define APBH_IRQS { CONNECTIVITY_APBHDMA_IRQn }
2130
2131/*!
2132 * @}
2133 */ /* end of group APBH_Peripheral_Access_Layer */
2134
2135
2136/* ----------------------------------------------------------------------------
2137 -- ASMC Peripheral Access Layer
2138 ---------------------------------------------------------------------------- */
2139
2140/*!
2141 * @addtogroup ASMC_Peripheral_Access_Layer ASMC Peripheral Access Layer
2142 * @{
2143 */
2144
2145/** ASMC - Register Layout Typedef */
2146typedef struct {
2147 __I uint32_t SRS; /**< System Reset Status Register, offset: 0x0 */
2148 uint8_t RESERVED_0[4];
2149 __IO uint32_t PMPROT; /**< Power Mode Protection register, offset: 0x8 */
2150 __IO uint32_t PMCTRL; /**< Power Mode Control register, offset: 0xC */
2151 __IO uint32_t STOPCTRL; /**< Stop Control Register, offset: 0x10 */
2152 __I uint32_t PMSTAT; /**< Power Mode Status register, offset: 0x14 */
2153} ASMC_Type;
2154
2155/* ----------------------------------------------------------------------------
2156 -- ASMC Register Masks
2157 ---------------------------------------------------------------------------- */
2158
2159/*!
2160 * @addtogroup ASMC_Register_Masks ASMC Register Masks
2161 * @{
2162 */
2163
2164/*! @name SRS - System Reset Status Register */
2165/*! @{ */
2166#define ASMC_SRS_WAKEUP_MASK (0x1U)
2167#define ASMC_SRS_WAKEUP_SHIFT (0U)
2168/*! WAKEUP - Low Leakage Wakeup Reset
2169 * 0b0..Reset not caused by LLWU module wakeup source
2170 * 0b1..Reset caused by LLWU module wakeup source
2171 */
2172#define ASMC_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WAKEUP_SHIFT)) & ASMC_SRS_WAKEUP_MASK)
2173#define ASMC_SRS_WDOG1_MASK (0x20U)
2174#define ASMC_SRS_WDOG1_SHIFT (5U)
2175/*! WDOG1 - Watchdog
2176 * 0b0..Reset not caused by watchdog timeout
2177 * 0b1..Reset caused by watchdog timeout
2178 */
2179#define ASMC_SRS_WDOG1(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WDOG1_SHIFT)) & ASMC_SRS_WDOG1_MASK)
2180#define ASMC_SRS_RES_MASK (0x40U)
2181#define ASMC_SRS_RES_SHIFT (6U)
2182/*! RES - Chip Reset not POR
2183 * 0b0..Chip Reset did not occur
2184 * 0b1..Chip Reset caused by a source other than POR occured
2185 */
2186#define ASMC_SRS_RES(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_RES_SHIFT)) & ASMC_SRS_RES_MASK)
2187#define ASMC_SRS_POR_MASK (0x80U)
2188#define ASMC_SRS_POR_SHIFT (7U)
2189/*! POR - Power-On Reset
2190 * 0b0..Reset not caused by POR
2191 * 0b1..Reset caused by POR
2192 */
2193#define ASMC_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_POR_SHIFT)) & ASMC_SRS_POR_MASK)
2194#define ASMC_SRS_LOCKUP_MASK (0x200U)
2195#define ASMC_SRS_LOCKUP_SHIFT (9U)
2196/*! LOCKUP - Core 1 Lockup
2197 * 0b0..Reset not caused by core LOCKUP event
2198 * 0b1..Reset caused by core LOCKUP event
2199 */
2200#define ASMC_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_LOCKUP_SHIFT)) & ASMC_SRS_LOCKUP_MASK)
2201#define ASMC_SRS_SW_MASK (0x400U)
2202#define ASMC_SRS_SW_SHIFT (10U)
2203/*! SW - Software
2204 * 0b0..Reset not caused by software setting of SYSRESETREQ bit
2205 * 0b1..Reset caused by software setting of SYSRESETREQ bit
2206 */
2207#define ASMC_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SW_SHIFT)) & ASMC_SRS_SW_MASK)
2208#define ASMC_SRS_SACKERR_MASK (0x1000U)
2209#define ASMC_SRS_SACKERR_SHIFT (12U)
2210/*! SACKERR - Stop Mode Acknowledge Error Reset
2211 * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
2212 * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
2213 */
2214#define ASMC_SRS_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SACKERR_SHIFT)) & ASMC_SRS_SACKERR_MASK)
2215/*! @} */
2216
2217/*! @name PMPROT - Power Mode Protection register */
2218/*! @{ */
2219#define ASMC_PMPROT_AVLLS_MASK (0x2U)
2220#define ASMC_PMPROT_AVLLS_SHIFT (1U)
2221/*! AVLLS - Allow Very-Low-Leakage Stop Mode
2222 * 0b0..Not Allowed
2223 * 0b1..Allowed
2224 */
2225#define ASMC_PMPROT_AVLLS(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLLS_SHIFT)) & ASMC_PMPROT_AVLLS_MASK)
2226#define ASMC_PMPROT_ALLS_MASK (0x8U)
2227#define ASMC_PMPROT_ALLS_SHIFT (3U)
2228/*! ALLS - Allow Low-Leakage Stop Mode
2229 * 0b0..Not Allowed
2230 * 0b1..Allowed
2231 */
2232#define ASMC_PMPROT_ALLS(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_ALLS_SHIFT)) & ASMC_PMPROT_ALLS_MASK)
2233#define ASMC_PMPROT_AVLP_MASK (0x20U)
2234#define ASMC_PMPROT_AVLP_SHIFT (5U)
2235/*! AVLP - Allow Very-Low-Power Modes
2236 * 0b0..VLPR, VLPW, and VLPS are not allowed.
2237 * 0b1..VLPR, VLPW, and VLPS are allowed.
2238 */
2239#define ASMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLP_SHIFT)) & ASMC_PMPROT_AVLP_MASK)
2240#define ASMC_PMPROT_AHSRUN_MASK (0x80U)
2241#define ASMC_PMPROT_AHSRUN_SHIFT (7U)
2242/*! AHSRUN - Allow High Speed Run mode
2243 * 0b0..HSRUN is not allowed
2244 * 0b1..HSRUN is allowed
2245 */
2246#define ASMC_PMPROT_AHSRUN(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AHSRUN_SHIFT)) & ASMC_PMPROT_AHSRUN_MASK)
2247/*! @} */
2248
2249/*! @name PMCTRL - Power Mode Control register */
2250/*! @{ */
2251#define ASMC_PMCTRL_STOPM_MASK (0x7U)
2252#define ASMC_PMCTRL_STOPM_SHIFT (0U)
2253/*! STOPM - Stop Mode Control
2254 * 0b000..Normal Stop (STOP)
2255 * 0b001..Reserved
2256 * 0b010..Very-Low-Power Stop (VLPS)
2257 * 0b011..Low-leakage stop
2258 * 0b100..Very-low-leakage stop
2259 * 0b101..Reserved
2260 * 0b110..Reseved
2261 * 0b111..Reserved
2262 */
2263#define ASMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_STOPM_SHIFT)) & ASMC_PMCTRL_STOPM_MASK)
2264#define ASMC_PMCTRL_RUNM_MASK (0x60U)
2265#define ASMC_PMCTRL_RUNM_SHIFT (5U)
2266/*! RUNM - Run Mode Control
2267 * 0b00..Normal Run mode (RUN)
2268 * 0b01..Reserved
2269 * 0b10..Very-Low-Power Run mode (VLPR)
2270 * 0b11..High Speed Run mode (HSRUN)
2271 */
2272#define ASMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_RUNM_SHIFT)) & ASMC_PMCTRL_RUNM_MASK)
2273/*! @} */
2274
2275/*! @name STOPCTRL - Stop Control Register */
2276/*! @{ */
2277#define ASMC_STOPCTRL_PSTOPO_MASK (0xC0U)
2278#define ASMC_STOPCTRL_PSTOPO_SHIFT (6U)
2279/*! PSTOPO - Partial Stop Option
2280 * 0b00..STOP - Normal Stop mode
2281 * 0b01..PSTOP1 - Partial Stop with both system and bus clocks disabled
2282 * 0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
2283 * 0b11..Reserved
2284 */
2285#define ASMC_STOPCTRL_PSTOPO(x) (((uint32_t)(((uint32_t)(x)) << ASMC_STOPCTRL_PSTOPO_SHIFT)) & ASMC_STOPCTRL_PSTOPO_MASK)
2286/*! @} */
2287
2288/*! @name PMSTAT - Power Mode Status register */
2289/*! @{ */
2290#define ASMC_PMSTAT_PMSTAT_MASK (0xFFU) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */
2291#define ASMC_PMSTAT_PMSTAT_SHIFT (0U)
2292/*! PMSTAT - Power Mode Status
2293 * 0b00000001..Current power mode is RUN.
2294 * 0b00000010..Current power mode is STOP.
2295 * 0b00000100..Current power mode is VLPR.
2296 * 0b00001000..Current power mode is VLPW.
2297 * 0b00010000..Current power mode is VLPS.
2298 * 0b00100000..Current power mode is LLS.
2299 * 0b01000000..Current power mode is VLLS.
2300 * 0b10000000..Current power mode is HSRUN
2301 */
2302#define ASMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMSTAT_PMSTAT_SHIFT)) & ASMC_PMSTAT_PMSTAT_MASK) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */
2303/*! @} */
2304
2305
2306/*!
2307 * @}
2308 */ /* end of group ASMC_Register_Masks */
2309
2310
2311/* ASMC - Peripheral instance base addresses */
2312/** Peripheral CM4__ASMC base address */
2313#define CM4__ASMC_BASE (0x41410000u)
2314/** Peripheral CM4__ASMC base pointer */
2315#define CM4__ASMC ((ASMC_Type *)CM4__ASMC_BASE)
2316/** Peripheral SCU__ASMC base address */
2317#define SCU__ASMC_BASE (0x33410000u)
2318/** Peripheral SCU__ASMC base pointer */
2319#define SCU__ASMC ((ASMC_Type *)SCU__ASMC_BASE)
2320/** Array initializer of ASMC peripheral base addresses */
2321#define ASMC_BASE_ADDRS { CM4__ASMC_BASE, SCU__ASMC_BASE }
2322/** Array initializer of ASMC peripheral base pointers */
2323#define ASMC_BASE_PTRS { CM4__ASMC, SCU__ASMC }
2324
2325/*!
2326 * @}
2327 */ /* end of group ASMC_Peripheral_Access_Layer */
2328
2329
2330/* ----------------------------------------------------------------------------
2331 -- ASRC Peripheral Access Layer
2332 ---------------------------------------------------------------------------- */
2333
2334/*!
2335 * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer
2336 * @{
2337 */
2338
2339/** ASRC - Register Layout Typedef */
2340typedef struct {
2341 __IO uint32_t ASRCTR; /**< ASRC Control Register, offset: 0x0 */
2342 __IO uint32_t ASRIER; /**< ASRC Interrupt Enable Register, offset: 0x4 */
2343 uint8_t RESERVED_0[4];
2344 __IO uint32_t ASRCNCR; /**< ASRC Channel Number Configuration Register, offset: 0xC */
2345 __IO uint32_t ASRCFG; /**< ASRC Filter Configuration Status Register, offset: 0x10 */
2346 __IO uint32_t ASRCSR; /**< ASRC Clock Source Register, offset: 0x14 */
2347 __IO uint32_t ASRCDR1; /**< ASRC Clock Divider Register 1, offset: 0x18 */
2348 __IO uint32_t ASRCDR2; /**< ASRC Clock Divider Register 2, offset: 0x1C */
2349 __I uint32_t ASRSTR; /**< ASRC Status Register, offset: 0x20 */
2350 uint8_t RESERVED_1[28];
2351 __IO uint32_t ASRPM[5]; /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */
2352 __IO uint32_t ASRTFR1; /**< ASRC ASRC Task Queue FIFO Register 1, offset: 0x54 */
2353 uint8_t RESERVED_2[4];
2354 __IO uint32_t ASRCCR; /**< ASRC Channel Counter Register, offset: 0x5C */
2355 __O uint32_t ASRDIA; /**< ASRC Data Input Register for Pair x, offset: 0x60 */
2356 __I uint32_t ASRDOA; /**< ASRC Data Output Register for Pair x, offset: 0x64 */
2357 __O uint32_t ASRDIB; /**< ASRC Data Input Register for Pair x, offset: 0x68 */
2358 __I uint32_t ASRDOB; /**< ASRC Data Output Register for Pair x, offset: 0x6C */
2359 __O uint32_t ASRDIC; /**< ASRC Data Input Register for Pair x, offset: 0x70 */
2360 __I uint32_t ASRDOC; /**< ASRC Data Output Register for Pair x, offset: 0x74 */
2361 uint8_t RESERVED_3[8];
2362 __IO uint32_t ASRIDRHA; /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */
2363 __IO uint32_t ASRIDRLA; /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */
2364 __IO uint32_t ASRIDRHB; /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */
2365 __IO uint32_t ASRIDRLB; /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */
2366 __IO uint32_t ASRIDRHC; /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */
2367 __IO uint32_t ASRIDRLC; /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */
2368 __IO uint32_t ASR76K; /**< ASRC 76 kHz Period in terms of ASRC processing clock, offset: 0x98 */
2369 __IO uint32_t ASR56K; /**< ASRC 56 kHz Period in terms of ASRC processing clock, offset: 0x9C */
2370 __IO uint32_t ASRMCRA; /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */
2371 __I uint32_t ASRFSTA; /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */
2372 __IO uint32_t ASRMCRB; /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */
2373 __I uint32_t ASRFSTB; /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */
2374 __IO uint32_t ASRMCRC; /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */
2375 __I uint32_t ASRFSTC; /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */
2376 uint8_t RESERVED_4[8];
2377 __IO uint32_t ASRMCR1[3]; /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4 */
2378} ASRC_Type;
2379
2380/* ----------------------------------------------------------------------------
2381 -- ASRC Register Masks
2382 ---------------------------------------------------------------------------- */
2383
2384/*!
2385 * @addtogroup ASRC_Register_Masks ASRC Register Masks
2386 * @{
2387 */
2388
2389/*! @name ASRCTR - ASRC Control Register */
2390/*! @{ */
2391#define ASRC_ASRCTR_ASRCEN_MASK (0x1U)
2392#define ASRC_ASRCTR_ASRCEN_SHIFT (0U)
2393/*! ASRCEN - ASRCEN
2394 */
2395#define ASRC_ASRCTR_ASRCEN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK)
2396#define ASRC_ASRCTR_ASREA_MASK (0x2U)
2397#define ASRC_ASRCTR_ASREA_SHIFT (1U)
2398/*! ASREA - ASREA
2399 */
2400#define ASRC_ASRCTR_ASREA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK)
2401#define ASRC_ASRCTR_ASREB_MASK (0x4U)
2402#define ASRC_ASRCTR_ASREB_SHIFT (2U)
2403/*! ASREB - ASREB
2404 */
2405#define ASRC_ASRCTR_ASREB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK)
2406#define ASRC_ASRCTR_ASREC_MASK (0x8U)
2407#define ASRC_ASRCTR_ASREC_SHIFT (3U)
2408/*! ASREC - ASREC
2409 */
2410#define ASRC_ASRCTR_ASREC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK)
2411#define ASRC_ASRCTR_SRST_MASK (0x10U)
2412#define ASRC_ASRCTR_SRST_SHIFT (4U)
2413/*! SRST - SRST
2414 */
2415#define ASRC_ASRCTR_SRST(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK)
2416#define ASRC_ASRCTR_IDRA_MASK (0x2000U)
2417#define ASRC_ASRCTR_IDRA_SHIFT (13U)
2418/*! IDRA - IDRA
2419 */
2420#define ASRC_ASRCTR_IDRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK)
2421#define ASRC_ASRCTR_USRA_MASK (0x4000U)
2422#define ASRC_ASRCTR_USRA_SHIFT (14U)
2423/*! USRA - USRA
2424 */
2425#define ASRC_ASRCTR_USRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK)
2426#define ASRC_ASRCTR_IDRB_MASK (0x8000U)
2427#define ASRC_ASRCTR_IDRB_SHIFT (15U)
2428/*! IDRB - IDRB
2429 */
2430#define ASRC_ASRCTR_IDRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK)
2431#define ASRC_ASRCTR_USRB_MASK (0x10000U)
2432#define ASRC_ASRCTR_USRB_SHIFT (16U)
2433/*! USRB - USRB
2434 */
2435#define ASRC_ASRCTR_USRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK)
2436#define ASRC_ASRCTR_IDRC_MASK (0x20000U)
2437#define ASRC_ASRCTR_IDRC_SHIFT (17U)
2438/*! IDRC - IDRC
2439 */
2440#define ASRC_ASRCTR_IDRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK)
2441#define ASRC_ASRCTR_USRC_MASK (0x40000U)
2442#define ASRC_ASRCTR_USRC_SHIFT (18U)
2443/*! USRC - USRC
2444 */
2445#define ASRC_ASRCTR_USRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK)
2446#define ASRC_ASRCTR_ATSA_MASK (0x100000U)
2447#define ASRC_ASRCTR_ATSA_SHIFT (20U)
2448/*! ATSA - ATSA
2449 */
2450#define ASRC_ASRCTR_ATSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK)
2451#define ASRC_ASRCTR_ATSB_MASK (0x200000U)
2452#define ASRC_ASRCTR_ATSB_SHIFT (21U)
2453/*! ATSB - ATSB
2454 */
2455#define ASRC_ASRCTR_ATSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK)
2456#define ASRC_ASRCTR_ATSC_MASK (0x400000U)
2457#define ASRC_ASRCTR_ATSC_SHIFT (22U)
2458/*! ATSC - ATSC
2459 */
2460#define ASRC_ASRCTR_ATSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK)
2461/*! @} */
2462
2463/*! @name ASRIER - ASRC Interrupt Enable Register */
2464/*! @{ */
2465#define ASRC_ASRIER_ADIEA_MASK (0x1U)
2466#define ASRC_ASRIER_ADIEA_SHIFT (0U)
2467/*! ADIEA - ADIEA
2468 * 0b1..interrupt enabled
2469 * 0b0..interrupt disabled
2470 */
2471#define ASRC_ASRIER_ADIEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK)
2472#define ASRC_ASRIER_ADIEB_MASK (0x2U)
2473#define ASRC_ASRIER_ADIEB_SHIFT (1U)
2474/*! ADIEB - ADIEB
2475 * 0b1..interrupt enabled
2476 * 0b0..interrupt disabled
2477 */
2478#define ASRC_ASRIER_ADIEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK)
2479#define ASRC_ASRIER_ADIEC_MASK (0x4U)
2480#define ASRC_ASRIER_ADIEC_SHIFT (2U)
2481/*! ADIEC - ADIEC
2482 * 0b1..interrupt enabled
2483 * 0b0..interrupt disabled
2484 */
2485#define ASRC_ASRIER_ADIEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK)
2486#define ASRC_ASRIER_ADOEA_MASK (0x8U)
2487#define ASRC_ASRIER_ADOEA_SHIFT (3U)
2488/*! ADOEA - ADOEA
2489 * 0b1..interrupt enabled
2490 * 0b0..interrupt disabled
2491 */
2492#define ASRC_ASRIER_ADOEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK)
2493#define ASRC_ASRIER_ADOEB_MASK (0x10U)
2494#define ASRC_ASRIER_ADOEB_SHIFT (4U)
2495/*! ADOEB - ADOEB
2496 * 0b1..interrupt enabled
2497 * 0b0..interrupt disabled
2498 */
2499#define ASRC_ASRIER_ADOEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK)
2500#define ASRC_ASRIER_ADOEC_MASK (0x20U)
2501#define ASRC_ASRIER_ADOEC_SHIFT (5U)
2502/*! ADOEC - ADOEC
2503 * 0b1..interrupt enabled
2504 * 0b0..interrupt disabled
2505 */
2506#define ASRC_ASRIER_ADOEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK)
2507#define ASRC_ASRIER_AOLIE_MASK (0x40U)
2508#define ASRC_ASRIER_AOLIE_SHIFT (6U)
2509/*! AOLIE - AOLIE
2510 * 0b1..interrupt enabled
2511 * 0b0..interrupt disabled
2512 */
2513#define ASRC_ASRIER_AOLIE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK)
2514#define ASRC_ASRIER_AFPWE_MASK (0x80U)
2515#define ASRC_ASRIER_AFPWE_SHIFT (7U)
2516/*! AFPWE - AFPWE
2517 * 0b1..interrupt enabled
2518 * 0b0..interrupt disabled
2519 */
2520#define ASRC_ASRIER_AFPWE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK)
2521/*! @} */
2522
2523/*! @name ASRCNCR - ASRC Channel Number Configuration Register */
2524/*! @{ */
2525#define ASRC_ASRCNCR_ANCA_MASK (0xFU)
2526#define ASRC_ASRCNCR_ANCA_SHIFT (0U)
2527/*! ANCA - ANCA
2528 * 0b0000..0 channels in A (Pair A is disabled)
2529 * 0b0001..1 channel in A
2530 * 0b0010..2 channels in A
2531 * 0b0011..3 channels in A
2532 * 0b0100..4 channels in A
2533 * 0b0101..5 channels in A
2534 * 0b0110..6 channels in A
2535 * 0b0111..7 channels in A
2536 * 0b1000..8 channels in A
2537 * 0b1001..9 channels in A
2538 * 0b1010..10 channels in A
2539 * 0b1011-0b1111..Should not be used.
2540 */
2541#define ASRC_ASRCNCR_ANCA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK)
2542#define ASRC_ASRCNCR_ANCB_MASK (0xF0U)
2543#define ASRC_ASRCNCR_ANCB_SHIFT (4U)
2544/*! ANCB - ANCB
2545 * 0b0000..0 channels in B (Pair B is disabled)
2546 * 0b0001..1 channel in B
2547 * 0b0010..2 channels in B
2548 * 0b0011..3 channels in B
2549 * 0b0100..4 channels in B
2550 * 0b0101..5 channels in B
2551 * 0b0110..6 channels in B
2552 * 0b0111..7 channels in B
2553 * 0b1000..8 channels in B
2554 * 0b1001..9 channels in B
2555 * 0b1010..10 channels in B
2556 * 0b1011-0b1111..Should not be used.
2557 */
2558#define ASRC_ASRCNCR_ANCB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK)
2559#define ASRC_ASRCNCR_ANCC_MASK (0xF00U)
2560#define ASRC_ASRCNCR_ANCC_SHIFT (8U)
2561/*! ANCC - ANCC
2562 * 0b0000..0 channels in C (Pair C is disabled)
2563 * 0b0001..1 channel in C
2564 * 0b0010..2 channels in C
2565 * 0b0011..3 channels in C
2566 * 0b0100..4 channels in C
2567 * 0b0101..5 channels in C
2568 * 0b0110..6 channels in C
2569 * 0b0111..7 channels in C
2570 * 0b1000..8 channels in C
2571 * 0b1001..9 channels in C
2572 * 0b1010..10 channels in C
2573 * 0b1011-0b1111..Should not be used.
2574 */
2575#define ASRC_ASRCNCR_ANCC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK)
2576/*! @} */
2577
2578/*! @name ASRCFG - ASRC Filter Configuration Status Register */
2579/*! @{ */
2580#define ASRC_ASRCFG_PREMODA_MASK (0xC0U)
2581#define ASRC_ASRCFG_PREMODA_SHIFT (6U)
2582/*! PREMODA - PREMODA
2583 * 0b00..Select Upsampling-by-2 as defined in
2584 * 0b01..Select Direct-Connection as defined in
2585 * 0b10..Select Downsampling-by-2 as defined in
2586 * 0b11..Select passthrough mode. In this case, POSTMODA[1-0] have no use.
2587 */
2588#define ASRC_ASRCFG_PREMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK)
2589#define ASRC_ASRCFG_POSTMODA_MASK (0x300U)
2590#define ASRC_ASRCFG_POSTMODA_SHIFT (8U)
2591/*! POSTMODA - POSTMODA
2592 * 0b00..Select Upsampling-by-2 as defined in
2593 * 0b01..Select Direct-Connection as defined in
2594 * 0b10..Select Downsampling-by-2 as defined in
2595 */
2596#define ASRC_ASRCFG_POSTMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK)
2597#define ASRC_ASRCFG_PREMODB_MASK (0xC00U)
2598#define ASRC_ASRCFG_PREMODB_SHIFT (10U)
2599/*! PREMODB - PREMODB
2600 * 0b00..Select Upsampling-by-2 as defined in
2601 * 0b01..Select Direct-Connection as defined in
2602 * 0b10..Select Downsampling-by-2 as defined in
2603 * 0b11..Select passthrough mode. In this case, POSTMODB[1-0] have no use.
2604 */
2605#define ASRC_ASRCFG_PREMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK)
2606#define ASRC_ASRCFG_POSTMODB_MASK (0x3000U)
2607#define ASRC_ASRCFG_POSTMODB_SHIFT (12U)
2608/*! POSTMODB - POSTMODB
2609 * 0b00..Select Upsampling-by-2 as defined in
2610 * 0b01..Select Direct-Connection as defined in
2611 * 0b10..Select Downsampling-by-2 as defined in
2612 */
2613#define ASRC_ASRCFG_POSTMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK)
2614#define ASRC_ASRCFG_PREMODC_MASK (0xC000U)
2615#define ASRC_ASRCFG_PREMODC_SHIFT (14U)
2616/*! PREMODC - PREMODC
2617 * 0b00..Select Upsampling-by-2 as defined in
2618 * 0b01..Select Direct-Connection as defined in
2619 * 0b10..Select Downsampling-by-2 as defined in
2620 * 0b11..Select passthrough mode. In this case, POSTMODC[1-0] have no use.
2621 */
2622#define ASRC_ASRCFG_PREMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK)
2623#define ASRC_ASRCFG_POSTMODC_MASK (0x30000U)
2624#define ASRC_ASRCFG_POSTMODC_SHIFT (16U)
2625/*! POSTMODC - POSTMODC
2626 * 0b00..Select Upsampling-by-2 as defined in Signal Processing Flow.
2627 * 0b01..Select Direct-Connection as defined in Signal Processing Flow.
2628 * 0b10..Select Downsampling-by-2 as defined in Signal Processing Flow.
2629 */
2630#define ASRC_ASRCFG_POSTMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK)
2631#define ASRC_ASRCFG_NDPRA_MASK (0x40000U)
2632#define ASRC_ASRCFG_NDPRA_SHIFT (18U)
2633/*! NDPRA - NDPRA
2634 * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
2635 * 0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
2636 */
2637#define ASRC_ASRCFG_NDPRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK)
2638#define ASRC_ASRCFG_NDPRB_MASK (0x80000U)
2639#define ASRC_ASRCFG_NDPRB_SHIFT (19U)
2640/*! NDPRB - NDPRB
2641 * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
2642 * 0b1..Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM.
2643 */
2644#define ASRC_ASRCFG_NDPRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK)
2645#define ASRC_ASRCFG_NDPRC_MASK (0x100000U)
2646#define ASRC_ASRCFG_NDPRC_SHIFT (20U)
2647/*! NDPRC - NDPRC
2648 * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
2649 * 0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
2650 */
2651#define ASRC_ASRCFG_NDPRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK)
2652#define ASRC_ASRCFG_INIRQA_MASK (0x200000U)
2653#define ASRC_ASRCFG_INIRQA_SHIFT (21U)
2654/*! INIRQA - INIRQA
2655 */
2656#define ASRC_ASRCFG_INIRQA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK)
2657#define ASRC_ASRCFG_INIRQB_MASK (0x400000U)
2658#define ASRC_ASRCFG_INIRQB_SHIFT (22U)
2659/*! INIRQB - INIRQB
2660 */
2661#define ASRC_ASRCFG_INIRQB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK)
2662#define ASRC_ASRCFG_INIRQC_MASK (0x800000U)
2663#define ASRC_ASRCFG_INIRQC_SHIFT (23U)
2664/*! INIRQC - INIRQC
2665 */
2666#define ASRC_ASRCFG_INIRQC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK)
2667/*! @} */
2668
2669/*! @name ASRCSR - ASRC Clock Source Register */
2670/*! @{ */
2671#define ASRC_ASRCSR_AICSA_MASK (0xFU)
2672#define ASRC_ASRCSR_AICSA_SHIFT (0U)
2673/*! AICSA - AICSA
2674 * 0b0000..bit clock 0
2675 * 0b0001..bit clock 1
2676 * 0b0010..bit clock 2
2677 * 0b0011..bit clock 3
2678 * 0b0100..bit clock 4
2679 * 0b0101..bit clock 5
2680 * 0b0110..bit clock 6
2681 * 0b0111..bit clock 7
2682 * 0b1000..bit clock 8
2683 * 0b1001..bit clock 9
2684 * 0b1010..bit clock A
2685 * 0b1011..bit clock B
2686 * 0b1100..bit clock C
2687 * 0b1101..bit clock D
2688 * 0b1110..bit clock E
2689 * 0b1111..clock disabled, connected to zero
2690 */
2691#define ASRC_ASRCSR_AICSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK)
2692#define ASRC_ASRCSR_AICSB_MASK (0xF0U)
2693#define ASRC_ASRCSR_AICSB_SHIFT (4U)
2694/*! AICSB - AICSB
2695 * 0b0000..bit clock 0
2696 * 0b0001..bit clock 1
2697 * 0b0010..bit clock 2
2698 * 0b0011..bit clock 3
2699 * 0b0100..bit clock 4
2700 * 0b0101..bit clock 5
2701 * 0b0110..bit clock 6
2702 * 0b0111..bit clock 7
2703 * 0b1000..bit clock 8
2704 * 0b1001..bit clock 9
2705 * 0b1010..bit clock A
2706 * 0b1011..bit clock B
2707 * 0b1100..bit clock C
2708 * 0b1101..bit clock D
2709 * 0b1110..bit clock E
2710 * 0b1111..clock disabled, connected to zero
2711 */
2712#define ASRC_ASRCSR_AICSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK)
2713#define ASRC_ASRCSR_AICSC_MASK (0xF00U)
2714#define ASRC_ASRCSR_AICSC_SHIFT (8U)
2715/*! AICSC - AICSC
2716 * 0b0000..bit clock 0
2717 * 0b0001..bit clock 1
2718 * 0b0010..bit clock 2
2719 * 0b0011..bit clock 3
2720 * 0b0100..bit clock 4
2721 * 0b0101..bit clock 5
2722 * 0b0110..bit clock 6
2723 * 0b0111..bit clock 7
2724 * 0b1000..bit clock 8
2725 * 0b1001..bit clock 9
2726 * 0b1010..bit clock A
2727 * 0b1011..bit clock B
2728 * 0b1100..bit clock C
2729 * 0b1101..bit clock D
2730 * 0b1110..bit clock E
2731 * 0b1111..clock disabled, connected to zero
2732 */
2733#define ASRC_ASRCSR_AICSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK)
2734#define ASRC_ASRCSR_AOCSA_MASK (0xF000U)
2735#define ASRC_ASRCSR_AOCSA_SHIFT (12U)
2736/*! AOCSA - AOCSA
2737 * 0b0000..bit clock 0
2738 * 0b0001..bit clock 1
2739 * 0b0010..bit clock 2
2740 * 0b0011..bit clock 3
2741 * 0b0100..bit clock 4
2742 * 0b0101..bit clock 5
2743 * 0b0110..bit clock 6
2744 * 0b0111..bit clock 7
2745 * 0b1000..bit clock 8
2746 * 0b1001..bit clock 9
2747 * 0b1010..bit clock A
2748 * 0b1011..bit clock B
2749 * 0b1100..bit clock C
2750 * 0b1101..bit clock D
2751 * 0b1110..bit clock E
2752 * 0b1111..clock disabled, connected to zero
2753 */
2754#define ASRC_ASRCSR_AOCSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK)
2755#define ASRC_ASRCSR_AOCSB_MASK (0xF0000U)
2756#define ASRC_ASRCSR_AOCSB_SHIFT (16U)
2757/*! AOCSB - AOCSB
2758 * 0b0000..bit clock 0
2759 * 0b0001..bit clock 1
2760 * 0b0010..bit clock 2
2761 * 0b0011..bit clock 3
2762 * 0b0100..bit clock 4
2763 * 0b0101..bit clock 5
2764 * 0b0110..bit clock 6
2765 * 0b0111..bit clock 7
2766 * 0b1000..bit clock 8
2767 * 0b1001..bit clock 9
2768 * 0b1010..bit clock A
2769 * 0b1011..bit clock B
2770 * 0b1100..bit clock C
2771 * 0b1101..bit clock D
2772 * 0b1110..bit clock E
2773 * 0b1111..clock disabled, connected to zero
2774 */
2775#define ASRC_ASRCSR_AOCSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK)
2776#define ASRC_ASRCSR_AOCSC_MASK (0xF00000U)
2777#define ASRC_ASRCSR_AOCSC_SHIFT (20U)
2778/*! AOCSC - AOCSC
2779 * 0b0000..bit clock 0
2780 * 0b0001..bit clock 1
2781 * 0b0010..bit clock 2
2782 * 0b0011..bit clock 3
2783 * 0b0100..bit clock 4
2784 * 0b0101..bit clock 5
2785 * 0b0110..bit clock 6
2786 * 0b0111..bit clock 7
2787 * 0b1000..bit clock 8
2788 * 0b1001..bit clock 9
2789 * 0b1010..bit clock A
2790 * 0b1011..bit clock B
2791 * 0b1100..bit clock C
2792 * 0b1101..bit clock D
2793 * 0b1110..bit clock E
2794 * 0b1111..clock disabled, connected to zero
2795 */
2796#define ASRC_ASRCSR_AOCSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK)
2797/*! @} */
2798
2799/*! @name ASRCDR1 - ASRC Clock Divider Register 1 */
2800/*! @{ */
2801#define ASRC_ASRCDR1_AICPA_MASK (0x7U)
2802#define ASRC_ASRCDR1_AICPA_SHIFT (0U)
2803/*! AICPA - AICPA
2804 */
2805#define ASRC_ASRCDR1_AICPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK)
2806#define ASRC_ASRCDR1_AICDA_MASK (0x38U)
2807#define ASRC_ASRCDR1_AICDA_SHIFT (3U)
2808/*! AICDA - AICDA
2809 */
2810#define ASRC_ASRCDR1_AICDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK)
2811#define ASRC_ASRCDR1_AICPB_MASK (0x1C0U)
2812#define ASRC_ASRCDR1_AICPB_SHIFT (6U)
2813/*! AICPB - AICPB
2814 */
2815#define ASRC_ASRCDR1_AICPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK)
2816#define ASRC_ASRCDR1_AICDB_MASK (0xE00U)
2817#define ASRC_ASRCDR1_AICDB_SHIFT (9U)
2818/*! AICDB - AICDB
2819 */
2820#define ASRC_ASRCDR1_AICDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK)
2821#define ASRC_ASRCDR1_AOCPA_MASK (0x7000U)
2822#define ASRC_ASRCDR1_AOCPA_SHIFT (12U)
2823/*! AOCPA - AOCPA
2824 */
2825#define ASRC_ASRCDR1_AOCPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK)
2826#define ASRC_ASRCDR1_AOCDA_MASK (0x38000U)
2827#define ASRC_ASRCDR1_AOCDA_SHIFT (15U)
2828/*! AOCDA - AOCDA
2829 */
2830#define ASRC_ASRCDR1_AOCDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK)
2831#define ASRC_ASRCDR1_AOCPB_MASK (0x1C0000U)
2832#define ASRC_ASRCDR1_AOCPB_SHIFT (18U)
2833/*! AOCPB - AOCPB
2834 */
2835#define ASRC_ASRCDR1_AOCPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK)
2836#define ASRC_ASRCDR1_AOCDB_MASK (0xE00000U)
2837#define ASRC_ASRCDR1_AOCDB_SHIFT (21U)
2838/*! AOCDB - AOCDB
2839 */
2840#define ASRC_ASRCDR1_AOCDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK)
2841/*! @} */
2842
2843/*! @name ASRCDR2 - ASRC Clock Divider Register 2 */
2844/*! @{ */
2845#define ASRC_ASRCDR2_AICPC_MASK (0x7U)
2846#define ASRC_ASRCDR2_AICPC_SHIFT (0U)
2847/*! AICPC - AICPC
2848 */
2849#define ASRC_ASRCDR2_AICPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK)
2850#define ASRC_ASRCDR2_AICDC_MASK (0x38U)
2851#define ASRC_ASRCDR2_AICDC_SHIFT (3U)
2852/*! AICDC - AICDC
2853 */
2854#define ASRC_ASRCDR2_AICDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK)
2855#define ASRC_ASRCDR2_AOCPC_MASK (0x1C0U)
2856#define ASRC_ASRCDR2_AOCPC_SHIFT (6U)
2857/*! AOCPC - AOCPC
2858 */
2859#define ASRC_ASRCDR2_AOCPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK)
2860#define ASRC_ASRCDR2_AOCDC_MASK (0xE00U)
2861#define ASRC_ASRCDR2_AOCDC_SHIFT (9U)
2862/*! AOCDC - AOCDC
2863 */
2864#define ASRC_ASRCDR2_AOCDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK)
2865/*! @} */
2866
2867/*! @name ASRSTR - ASRC Status Register */
2868/*! @{ */
2869#define ASRC_ASRSTR_AIDEA_MASK (0x1U)
2870#define ASRC_ASRSTR_AIDEA_SHIFT (0U)
2871/*! AIDEA - AIDEA
2872 */
2873#define ASRC_ASRSTR_AIDEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK)
2874#define ASRC_ASRSTR_AIDEB_MASK (0x2U)
2875#define ASRC_ASRSTR_AIDEB_SHIFT (1U)
2876/*! AIDEB - AIDEB
2877 */
2878#define ASRC_ASRSTR_AIDEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK)
2879#define ASRC_ASRSTR_AIDEC_MASK (0x4U)
2880#define ASRC_ASRSTR_AIDEC_SHIFT (2U)
2881/*! AIDEC - AIDEC
2882 */
2883#define ASRC_ASRSTR_AIDEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK)
2884#define ASRC_ASRSTR_AODFA_MASK (0x8U)
2885#define ASRC_ASRSTR_AODFA_SHIFT (3U)
2886/*! AODFA - AODFA
2887 */
2888#define ASRC_ASRSTR_AODFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK)
2889#define ASRC_ASRSTR_AODFB_MASK (0x10U)
2890#define ASRC_ASRSTR_AODFB_SHIFT (4U)
2891/*! AODFB - AODFB
2892 */
2893#define ASRC_ASRSTR_AODFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK)
2894#define ASRC_ASRSTR_AODFC_MASK (0x20U)
2895#define ASRC_ASRSTR_AODFC_SHIFT (5U)
2896/*! AODFC - AODFC
2897 */
2898#define ASRC_ASRSTR_AODFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK)
2899#define ASRC_ASRSTR_AOLE_MASK (0x40U)
2900#define ASRC_ASRSTR_AOLE_SHIFT (6U)
2901/*! AOLE - AOLE
2902 */
2903#define ASRC_ASRSTR_AOLE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK)
2904#define ASRC_ASRSTR_FPWT_MASK (0x80U)
2905#define ASRC_ASRSTR_FPWT_SHIFT (7U)
2906/*! FPWT - FPWT
2907 */
2908#define ASRC_ASRSTR_FPWT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK)
2909#define ASRC_ASRSTR_AIDUA_MASK (0x100U)
2910#define ASRC_ASRSTR_AIDUA_SHIFT (8U)
2911/*! AIDUA - AIDUA
2912 */
2913#define ASRC_ASRSTR_AIDUA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK)
2914#define ASRC_ASRSTR_AIDUB_MASK (0x200U)
2915#define ASRC_ASRSTR_AIDUB_SHIFT (9U)
2916/*! AIDUB - AIDUB
2917 */
2918#define ASRC_ASRSTR_AIDUB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK)
2919#define ASRC_ASRSTR_AIDUC_MASK (0x400U)
2920#define ASRC_ASRSTR_AIDUC_SHIFT (10U)
2921/*! AIDUC - AIDUC
2922 */
2923#define ASRC_ASRSTR_AIDUC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK)
2924#define ASRC_ASRSTR_AODOA_MASK (0x800U)
2925#define ASRC_ASRSTR_AODOA_SHIFT (11U)
2926/*! AODOA - AODOA
2927 */
2928#define ASRC_ASRSTR_AODOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK)
2929#define ASRC_ASRSTR_AODOB_MASK (0x1000U)
2930#define ASRC_ASRSTR_AODOB_SHIFT (12U)
2931/*! AODOB - AODOB
2932 */
2933#define ASRC_ASRSTR_AODOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK)
2934#define ASRC_ASRSTR_AODOC_MASK (0x2000U)
2935#define ASRC_ASRSTR_AODOC_SHIFT (13U)
2936/*! AODOC - AODOC
2937 */
2938#define ASRC_ASRSTR_AODOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK)
2939#define ASRC_ASRSTR_AIOLA_MASK (0x4000U)
2940#define ASRC_ASRSTR_AIOLA_SHIFT (14U)
2941/*! AIOLA - AIOLA
2942 */
2943#define ASRC_ASRSTR_AIOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK)
2944#define ASRC_ASRSTR_AIOLB_MASK (0x8000U)
2945#define ASRC_ASRSTR_AIOLB_SHIFT (15U)
2946/*! AIOLB - AIOLB
2947 */
2948#define ASRC_ASRSTR_AIOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK)
2949#define ASRC_ASRSTR_AIOLC_MASK (0x10000U)
2950#define ASRC_ASRSTR_AIOLC_SHIFT (16U)
2951/*! AIOLC - AIOLC
2952 */
2953#define ASRC_ASRSTR_AIOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK)
2954#define ASRC_ASRSTR_AOOLA_MASK (0x20000U)
2955#define ASRC_ASRSTR_AOOLA_SHIFT (17U)
2956/*! AOOLA - AOOLA
2957 */
2958#define ASRC_ASRSTR_AOOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK)
2959#define ASRC_ASRSTR_AOOLB_MASK (0x40000U)
2960#define ASRC_ASRSTR_AOOLB_SHIFT (18U)
2961/*! AOOLB - AOOLB
2962 */
2963#define ASRC_ASRSTR_AOOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK)
2964#define ASRC_ASRSTR_AOOLC_MASK (0x80000U)
2965#define ASRC_ASRSTR_AOOLC_SHIFT (19U)
2966/*! AOOLC - AOOLC
2967 */
2968#define ASRC_ASRSTR_AOOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK)
2969#define ASRC_ASRSTR_ATQOL_MASK (0x100000U)
2970#define ASRC_ASRSTR_ATQOL_SHIFT (20U)
2971/*! ATQOL - ATQOL
2972 */
2973#define ASRC_ASRSTR_ATQOL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK)
2974#define ASRC_ASRSTR_DSLCNT_MASK (0x200000U)
2975#define ASRC_ASRSTR_DSLCNT_SHIFT (21U)
2976/*! DSLCNT - DSLCNT
2977 */
2978#define ASRC_ASRSTR_DSLCNT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK)
2979/*! @} */
2980
2981/*! @name ASRPM - ASRC Parameter Register n */
2982/*! @{ */
2983#define ASRC_ASRPM_PARAMETER_VALUE_MASK (0xFFFFFFU)
2984#define ASRC_ASRPM_PARAMETER_VALUE_SHIFT (0U)
2985/*! PARAMETER_VALUE - PARAMETER_VALUE
2986 */
2987#define ASRC_ASRPM_PARAMETER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPM_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPM_PARAMETER_VALUE_MASK)
2988/*! @} */
2989
2990/* The count of ASRC_ASRPM */
2991#define ASRC_ASRPM_COUNT (5U)
2992
2993/*! @name ASRTFR1 - ASRC ASRC Task Queue FIFO Register 1 */
2994/*! @{ */
2995#define ASRC_ASRTFR1_TF_BASE_MASK (0x1FC0U)
2996#define ASRC_ASRTFR1_TF_BASE_SHIFT (6U)
2997/*! TF_BASE - TF_BASE
2998 */
2999#define ASRC_ASRTFR1_TF_BASE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK)
3000#define ASRC_ASRTFR1_TF_FILL_MASK (0xFE000U)
3001#define ASRC_ASRTFR1_TF_FILL_SHIFT (13U)
3002/*! TF_FILL - TF_FILL
3003 */
3004#define ASRC_ASRTFR1_TF_FILL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK)
3005/*! @} */
3006
3007/*! @name ASRCCR - ASRC Channel Counter Register */
3008/*! @{ */
3009#define ASRC_ASRCCR_ACIA_MASK (0xFU)
3010#define ASRC_ASRCCR_ACIA_SHIFT (0U)
3011/*! ACIA - ACIA
3012 */
3013#define ASRC_ASRCCR_ACIA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK)
3014#define ASRC_ASRCCR_ACIB_MASK (0xF0U)
3015#define ASRC_ASRCCR_ACIB_SHIFT (4U)
3016/*! ACIB - ACIB
3017 */
3018#define ASRC_ASRCCR_ACIB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK)
3019#define ASRC_ASRCCR_ACIC_MASK (0xF00U)
3020#define ASRC_ASRCCR_ACIC_SHIFT (8U)
3021/*! ACIC - ACIC
3022 */
3023#define ASRC_ASRCCR_ACIC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK)
3024#define ASRC_ASRCCR_ACOA_MASK (0xF000U)
3025#define ASRC_ASRCCR_ACOA_SHIFT (12U)
3026/*! ACOA - ACOA
3027 */
3028#define ASRC_ASRCCR_ACOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK)
3029#define ASRC_ASRCCR_ACOB_MASK (0xF0000U)
3030#define ASRC_ASRCCR_ACOB_SHIFT (16U)
3031/*! ACOB - ACOB
3032 */
3033#define ASRC_ASRCCR_ACOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK)
3034#define ASRC_ASRCCR_ACOC_MASK (0xF00000U)
3035#define ASRC_ASRCCR_ACOC_SHIFT (20U)
3036/*! ACOC - ACOC
3037 */
3038#define ASRC_ASRCCR_ACOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK)
3039/*! @} */
3040
3041/*! @name ASRDIA - ASRC Data Input Register for Pair x */
3042/*! @{ */
3043#define ASRC_ASRDIA_DATA_MASK (0xFFFFFFU)
3044#define ASRC_ASRDIA_DATA_SHIFT (0U)
3045/*! DATA - DATA
3046 */
3047#define ASRC_ASRDIA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK)
3048/*! @} */
3049
3050/*! @name ASRDOA - ASRC Data Output Register for Pair x */
3051/*! @{ */
3052#define ASRC_ASRDOA_DATA_MASK (0xFFFFFFU)
3053#define ASRC_ASRDOA_DATA_SHIFT (0U)
3054/*! DATA - DATA
3055 */
3056#define ASRC_ASRDOA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK)
3057/*! @} */
3058
3059/*! @name ASRDIB - ASRC Data Input Register for Pair x */
3060/*! @{ */
3061#define ASRC_ASRDIB_DATA_MASK (0xFFFFFFU)
3062#define ASRC_ASRDIB_DATA_SHIFT (0U)
3063/*! DATA - DATA
3064 */
3065#define ASRC_ASRDIB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK)
3066/*! @} */
3067
3068/*! @name ASRDOB - ASRC Data Output Register for Pair x */
3069/*! @{ */
3070#define ASRC_ASRDOB_DATA_MASK (0xFFFFFFU)
3071#define ASRC_ASRDOB_DATA_SHIFT (0U)
3072/*! DATA - DATA
3073 */
3074#define ASRC_ASRDOB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK)
3075/*! @} */
3076
3077/*! @name ASRDIC - ASRC Data Input Register for Pair x */
3078/*! @{ */
3079#define ASRC_ASRDIC_DATA_MASK (0xFFFFFFU)
3080#define ASRC_ASRDIC_DATA_SHIFT (0U)
3081/*! DATA - DATA
3082 */
3083#define ASRC_ASRDIC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK)
3084/*! @} */
3085
3086/*! @name ASRDOC - ASRC Data Output Register for Pair x */
3087/*! @{ */
3088#define ASRC_ASRDOC_DATA_MASK (0xFFFFFFU)
3089#define ASRC_ASRDOC_DATA_SHIFT (0U)
3090/*! DATA - DATA
3091 */
3092#define ASRC_ASRDOC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK)
3093/*! @} */
3094
3095/*! @name ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part */
3096/*! @{ */
3097#define ASRC_ASRIDRHA_IDRATIOA_H_MASK (0xFFU)
3098#define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT (0U)
3099/*! IDRATIOA_H - IDRATIOA_H
3100 */
3101#define ASRC_ASRIDRHA_IDRATIOA_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK)
3102/*! @} */
3103
3104/*! @name ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part */
3105/*! @{ */
3106#define ASRC_ASRIDRLA_IDRATIOA_L_MASK (0xFFFFFFU)
3107#define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT (0U)
3108/*! IDRATIOA_L - IDRATIOA_L
3109 */
3110#define ASRC_ASRIDRLA_IDRATIOA_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK)
3111/*! @} */
3112
3113/*! @name ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part */
3114/*! @{ */
3115#define ASRC_ASRIDRHB_IDRATIOB_H_MASK (0xFFU)
3116#define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT (0U)
3117/*! IDRATIOB_H - IDRATIOB_H
3118 */
3119#define ASRC_ASRIDRHB_IDRATIOB_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK)
3120/*! @} */
3121
3122/*! @name ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part */
3123/*! @{ */
3124#define ASRC_ASRIDRLB_IDRATIOB_L_MASK (0xFFFFFFU)
3125#define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT (0U)
3126/*! IDRATIOB_L - IDRATIOB_L
3127 */
3128#define ASRC_ASRIDRLB_IDRATIOB_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK)
3129/*! @} */
3130
3131/*! @name ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part */
3132/*! @{ */
3133#define ASRC_ASRIDRHC_IDRATIOC_H_MASK (0xFFU)
3134#define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT (0U)
3135/*! IDRATIOC_H - IDRATIOC_H
3136 */
3137#define ASRC_ASRIDRHC_IDRATIOC_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK)
3138/*! @} */
3139
3140/*! @name ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part */
3141/*! @{ */
3142#define ASRC_ASRIDRLC_IDRATIOC_L_MASK (0xFFFFFFU)
3143#define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT (0U)
3144/*! IDRATIOC_L - IDRATIOC_L
3145 */
3146#define ASRC_ASRIDRLC_IDRATIOC_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK)
3147/*! @} */
3148
3149/*! @name ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock */
3150/*! @{ */
3151#define ASRC_ASR76K_ASR76K_MASK (0x1FFFFU)
3152#define ASRC_ASR76K_ASR76K_SHIFT (0U)
3153/*! ASR76K - ASR76K
3154 */
3155#define ASRC_ASR76K_ASR76K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK)
3156/*! @} */
3157
3158/*! @name ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock */
3159/*! @{ */
3160#define ASRC_ASR56K_ASR56K_MASK (0x1FFFFU)
3161#define ASRC_ASR56K_ASR56K_SHIFT (0U)
3162/*! ASR56K - ASR56K
3163 */
3164#define ASRC_ASR56K_ASR56K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK)
3165/*! @} */
3166
3167/*! @name ASRMCRA - ASRC Misc Control Register for Pair A */
3168/*! @{ */
3169#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK (0x3FU)
3170#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT (0U)
3171/*! INFIFO_THRESHOLDA - INFIFO_THRESHOLDA
3172 */
3173#define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK)
3174#define ASRC_ASRMCRA_RSYNOFA_MASK (0x400U)
3175#define ASRC_ASRMCRA_RSYNOFA_SHIFT (10U)
3176/*! RSYNOFA - RSYNOFA
3177 */
3178#define ASRC_ASRMCRA_RSYNOFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK)
3179#define ASRC_ASRMCRA_RSYNIFA_MASK (0x800U)
3180#define ASRC_ASRMCRA_RSYNIFA_SHIFT (11U)
3181/*! RSYNIFA - RSYNIFA
3182 */
3183#define ASRC_ASRMCRA_RSYNIFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK)
3184#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK (0x3F000U)
3185#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT (12U)
3186/*! OUTFIFO_THRESHOLDA - OUTFIFO_THRESHOLDA
3187 */
3188#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK)
3189#define ASRC_ASRMCRA_BYPASSPOLYA_MASK (0x100000U)
3190#define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT (20U)
3191/*! BYPASSPOLYA - BYPASSPOLYA
3192 * 0b1..Bypass polyphase filtering.
3193 * 0b0..Don't bypass polyphase filtering.
3194 */
3195#define ASRC_ASRMCRA_BYPASSPOLYA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK)
3196#define ASRC_ASRMCRA_BUFSTALLA_MASK (0x200000U)
3197#define ASRC_ASRMCRA_BUFSTALLA_SHIFT (21U)
3198/*! BUFSTALLA - BUFSTALLA
3199 * 0b1..Stall Pair A conversion in case of near empty/full FIFO conditions.
3200 * 0b0..Don't stall Pair A conversion even in case of near empty/full FIFO conditions.
3201 */
3202#define ASRC_ASRMCRA_BUFSTALLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK)
3203#define ASRC_ASRMCRA_EXTTHRSHA_MASK (0x400000U)
3204#define ASRC_ASRMCRA_EXTTHRSHA_SHIFT (22U)
3205/*! EXTTHRSHA - EXTTHRSHA
3206 * 0b1..Use external defined thresholds.
3207 * 0b0..Use default thresholds.
3208 */
3209#define ASRC_ASRMCRA_EXTTHRSHA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK)
3210#define ASRC_ASRMCRA_ZEROBUFA_MASK (0x800000U)
3211#define ASRC_ASRMCRA_ZEROBUFA_SHIFT (23U)
3212/*! ZEROBUFA - ZEROBUFA
3213 * 0b1..Don't zeroize the buffer
3214 * 0b0..Zeroize the buffer
3215 */
3216#define ASRC_ASRMCRA_ZEROBUFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK)
3217/*! @} */
3218
3219/*! @name ASRFSTA - ASRC FIFO Status Register for Pair A */
3220/*! @{ */
3221#define ASRC_ASRFSTA_INFIFO_FILLA_MASK (0x7FU)
3222#define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT (0U)
3223/*! INFIFO_FILLA - INFIFO_FILLA
3224 */
3225#define ASRC_ASRFSTA_INFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK)
3226#define ASRC_ASRFSTA_IAEA_MASK (0x800U)
3227#define ASRC_ASRFSTA_IAEA_SHIFT (11U)
3228/*! IAEA - IAEA
3229 */
3230#define ASRC_ASRFSTA_IAEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK)
3231#define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK (0x7F000U)
3232#define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT (12U)
3233/*! OUTFIFO_FILLA - OUTFIFO_FILLA
3234 */
3235#define ASRC_ASRFSTA_OUTFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK)
3236#define ASRC_ASRFSTA_OAFA_MASK (0x800000U)
3237#define ASRC_ASRFSTA_OAFA_SHIFT (23U)
3238/*! OAFA - OAFA
3239 */
3240#define ASRC_ASRFSTA_OAFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK)
3241/*! @} */
3242
3243/*! @name ASRMCRB - ASRC Misc Control Register for Pair B */
3244/*! @{ */
3245#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK (0x3FU)
3246#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT (0U)
3247/*! INFIFO_THRESHOLDB - INFIFO_THRESHOLDB
3248 */
3249#define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK)
3250#define ASRC_ASRMCRB_RSYNOFB_MASK (0x400U)
3251#define ASRC_ASRMCRB_RSYNOFB_SHIFT (10U)
3252/*! RSYNOFB - RSYNOFB
3253 */
3254#define ASRC_ASRMCRB_RSYNOFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK)
3255#define ASRC_ASRMCRB_RSYNIFB_MASK (0x800U)
3256#define ASRC_ASRMCRB_RSYNIFB_SHIFT (11U)
3257/*! RSYNIFB - RSYNIFB
3258 */
3259#define ASRC_ASRMCRB_RSYNIFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK)
3260#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK (0x3F000U)
3261#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT (12U)
3262/*! OUTFIFO_THRESHOLDB - OUTFIFO_THRESHOLDB
3263 */
3264#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK)
3265#define ASRC_ASRMCRB_BYPASSPOLYB_MASK (0x100000U)
3266#define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT (20U)
3267/*! BYPASSPOLYB - BYPASSPOLYB
3268 * 0b1..Bypass polyphase filtering.
3269 * 0b0..Don't bypass polyphase filtering.
3270 */
3271#define ASRC_ASRMCRB_BYPASSPOLYB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK)
3272#define ASRC_ASRMCRB_BUFSTALLB_MASK (0x200000U)
3273#define ASRC_ASRMCRB_BUFSTALLB_SHIFT (21U)
3274/*! BUFSTALLB - BUFSTALLB
3275 * 0b1..Stall Pair B conversion in case of near empty/full FIFO conditions.
3276 * 0b0..Don't stall Pair B conversion even in case of near empty/full FIFO conditions.
3277 */
3278#define ASRC_ASRMCRB_BUFSTALLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK)
3279#define ASRC_ASRMCRB_EXTTHRSHB_MASK (0x400000U)
3280#define ASRC_ASRMCRB_EXTTHRSHB_SHIFT (22U)
3281/*! EXTTHRSHB - EXTTHRSHB
3282 * 0b1..Use external defined thresholds.
3283 * 0b0..Use default thresholds.
3284 */
3285#define ASRC_ASRMCRB_EXTTHRSHB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK)
3286#define ASRC_ASRMCRB_ZEROBUFB_MASK (0x800000U)
3287#define ASRC_ASRMCRB_ZEROBUFB_SHIFT (23U)
3288/*! ZEROBUFB - ZEROBUFB
3289 * 0b1..Don't zeroize the buffer
3290 * 0b0..Zeroize the buffer
3291 */
3292#define ASRC_ASRMCRB_ZEROBUFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK)
3293/*! @} */
3294
3295/*! @name ASRFSTB - ASRC FIFO Status Register for Pair B */
3296/*! @{ */
3297#define ASRC_ASRFSTB_INFIFO_FILLB_MASK (0x7FU)
3298#define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT (0U)
3299/*! INFIFO_FILLB - INFIFO_FILLB
3300 */
3301#define ASRC_ASRFSTB_INFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK)
3302#define ASRC_ASRFSTB_IAEB_MASK (0x800U)
3303#define ASRC_ASRFSTB_IAEB_SHIFT (11U)
3304/*! IAEB - IAEB
3305 */
3306#define ASRC_ASRFSTB_IAEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK)
3307#define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK (0x7F000U)
3308#define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT (12U)
3309/*! OUTFIFO_FILLB - OUTFIFO_FILLB
3310 */
3311#define ASRC_ASRFSTB_OUTFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK)
3312#define ASRC_ASRFSTB_OAFB_MASK (0x800000U)
3313#define ASRC_ASRFSTB_OAFB_SHIFT (23U)
3314/*! OAFB - OAFB
3315 */
3316#define ASRC_ASRFSTB_OAFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK)
3317/*! @} */
3318
3319/*! @name ASRMCRC - ASRC Misc Control Register for Pair C */
3320/*! @{ */
3321#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK (0x3FU)
3322#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT (0U)
3323/*! INFIFO_THRESHOLDC - INFIFO_THRESHOLDC
3324 */
3325#define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK)
3326#define ASRC_ASRMCRC_RSYNOFC_MASK (0x400U)
3327#define ASRC_ASRMCRC_RSYNOFC_SHIFT (10U)
3328/*! RSYNOFC - RSYNOFC
3329 */
3330#define ASRC_ASRMCRC_RSYNOFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK)
3331#define ASRC_ASRMCRC_RSYNIFC_MASK (0x800U)
3332#define ASRC_ASRMCRC_RSYNIFC_SHIFT (11U)
3333/*! RSYNIFC - RSYNIFC
3334 */
3335#define ASRC_ASRMCRC_RSYNIFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK)
3336#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK (0x3F000U)
3337#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT (12U)
3338/*! OUTFIFO_THRESHOLDC - OUTFIFO_THRESHOLDC
3339 */
3340#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK)
3341#define ASRC_ASRMCRC_BYPASSPOLYC_MASK (0x100000U)
3342#define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT (20U)
3343/*! BYPASSPOLYC - BYPASSPOLYC
3344 * 0b1..Bypass polyphase filtering.
3345 * 0b0..Don't bypass polyphase filtering.
3346 */
3347#define ASRC_ASRMCRC_BYPASSPOLYC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK)
3348#define ASRC_ASRMCRC_BUFSTALLC_MASK (0x200000U)
3349#define ASRC_ASRMCRC_BUFSTALLC_SHIFT (21U)
3350/*! BUFSTALLC - BUFSTALLC
3351 * 0b1..Stall Pair C conversion in case of near empty/full FIFO conditions.
3352 * 0b0..Don't stall Pair C conversion even in case of near empty/full FIFO conditions.
3353 */
3354#define ASRC_ASRMCRC_BUFSTALLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK)
3355#define ASRC_ASRMCRC_EXTTHRSHC_MASK (0x400000U)
3356#define ASRC_ASRMCRC_EXTTHRSHC_SHIFT (22U)
3357/*! EXTTHRSHC - EXTTHRSHC
3358 * 0b1..Use external defined thresholds.
3359 * 0b0..Use default thresholds.
3360 */
3361#define ASRC_ASRMCRC_EXTTHRSHC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK)
3362#define ASRC_ASRMCRC_ZEROBUFC_MASK (0x800000U)
3363#define ASRC_ASRMCRC_ZEROBUFC_SHIFT (23U)
3364/*! ZEROBUFC - ZEROBUFC
3365 * 0b1..Don't zeroize the buffer
3366 * 0b0..Zeroize the buffer
3367 */
3368#define ASRC_ASRMCRC_ZEROBUFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK)
3369/*! @} */
3370
3371/*! @name ASRFSTC - ASRC FIFO Status Register for Pair C */
3372/*! @{ */
3373#define ASRC_ASRFSTC_INFIFO_FILLC_MASK (0x7FU)
3374#define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT (0U)
3375/*! INFIFO_FILLC - INFIFO_FILLC
3376 */
3377#define ASRC_ASRFSTC_INFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK)
3378#define ASRC_ASRFSTC_IAEC_MASK (0x800U)
3379#define ASRC_ASRFSTC_IAEC_SHIFT (11U)
3380/*! IAEC - IAEC
3381 */
3382#define ASRC_ASRFSTC_IAEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK)
3383#define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK (0x7F000U)
3384#define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT (12U)
3385/*! OUTFIFO_FILLC - OUTFIFO_FILLC
3386 */
3387#define ASRC_ASRFSTC_OUTFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK)
3388#define ASRC_ASRFSTC_OAFC_MASK (0x800000U)
3389#define ASRC_ASRFSTC_OAFC_SHIFT (23U)
3390/*! OAFC - OAFC
3391 */
3392#define ASRC_ASRFSTC_OAFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK)
3393/*! @} */
3394
3395/*! @name ASRMCR1 - ASRC Misc Control Register 1 for Pair X */
3396/*! @{ */
3397#define ASRC_ASRMCR1_OW16_MASK (0x1U)
3398#define ASRC_ASRMCR1_OW16_SHIFT (0U)
3399/*! OW16 - OW16
3400 * 0b1..16-bit output data
3401 * 0b0..24-bit output data.
3402 */
3403#define ASRC_ASRMCR1_OW16(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK)
3404#define ASRC_ASRMCR1_OSGN_MASK (0x2U)
3405#define ASRC_ASRMCR1_OSGN_SHIFT (1U)
3406/*! OSGN - OSGN
3407 * 0b1..Sign extension.
3408 * 0b0..No sign extension.
3409 */
3410#define ASRC_ASRMCR1_OSGN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK)
3411#define ASRC_ASRMCR1_OMSB_MASK (0x4U)
3412#define ASRC_ASRMCR1_OMSB_SHIFT (2U)
3413/*! OMSB - OMSB
3414 * 0b1..MSB aligned.
3415 * 0b0..LSB aligned.
3416 */
3417#define ASRC_ASRMCR1_OMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK)
3418#define ASRC_ASRMCR1_IMSB_MASK (0x100U)
3419#define ASRC_ASRMCR1_IMSB_SHIFT (8U)
3420/*! IMSB - IMSB
3421 * 0b1..MSB aligned.
3422 * 0b0..LSB aligned.
3423 */
3424#define ASRC_ASRMCR1_IMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK)
3425#define ASRC_ASRMCR1_IWD_MASK (0xE00U)
3426#define ASRC_ASRMCR1_IWD_SHIFT (9U)
3427/*! IWD - IWD
3428 */
3429#define ASRC_ASRMCR1_IWD(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK)
3430/*! @} */
3431
3432/* The count of ASRC_ASRMCR1 */
3433#define ASRC_ASRMCR1_COUNT (3U)
3434
3435
3436/*!
3437 * @}
3438 */ /* end of group ASRC_Register_Masks */
3439
3440
3441/* ASRC - Peripheral instance base addresses */
3442/** Peripheral ADMA__ASRC0 base address */
3443#define ADMA__ASRC0_BASE (0x59000000u)
3444/** Peripheral ADMA__ASRC0 base pointer */
3445#define ADMA__ASRC0 ((ASRC_Type *)ADMA__ASRC0_BASE)
3446/** Peripheral ADMA__ASRC1 base address */
3447#define ADMA__ASRC1_BASE (0x59800000u)
3448/** Peripheral ADMA__ASRC1 base pointer */
3449#define ADMA__ASRC1 ((ASRC_Type *)ADMA__ASRC1_BASE)
3450/** Array initializer of ASRC peripheral base addresses */
3451#define ASRC_BASE_ADDRS { ADMA__ASRC0_BASE, ADMA__ASRC1_BASE }
3452/** Array initializer of ASRC peripheral base pointers */
3453#define ASRC_BASE_PTRS { ADMA__ASRC0, ADMA__ASRC1 }
3454
3455/*!
3456 * @}
3457 */ /* end of group ASRC_Peripheral_Access_Layer */
3458
3459
3460/* ----------------------------------------------------------------------------
3461 -- BCH Peripheral Access Layer
3462 ---------------------------------------------------------------------------- */
3463
3464/*!
3465 * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer
3466 * @{
3467 */
3468
3469/** BCH - Register Layout Typedef */
3470typedef struct {
3471 struct { /* offset: 0x0 */
3472 __IO uint32_t RW; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */
3473 __IO uint32_t SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */
3474 __IO uint32_t CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */
3475 __IO uint32_t TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */
3476 } CTRL;
3477 struct { /* offset: 0x10 */
3478 __I uint32_t RW; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */
3479 __I uint32_t SET; /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */
3480 __I uint32_t CLR; /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */
3481 __I uint32_t TOG; /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */
3482 } STATUS0;
3483 struct { /* offset: 0x20 */
3484 __IO uint32_t RW; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */
3485 __IO uint32_t SET; /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */
3486 __IO uint32_t CLR; /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */
3487 __IO uint32_t TOG; /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */
3488 } MODE;
3489 struct { /* offset: 0x30 */
3490 __IO uint32_t RW; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */
3491 __IO uint32_t SET; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */
3492 __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */
3493 __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */
3494 } ENCODEPTR;
3495 struct { /* offset: 0x40 */
3496 __IO uint32_t RW; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */
3497 __IO uint32_t SET; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */
3498 __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */
3499 __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */
3500 } DATAPTR;
3501 struct { /* offset: 0x50 */
3502 __IO uint32_t RW; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */
3503 __IO uint32_t SET; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */
3504 __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */
3505 __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */
3506 } METAPTR;
3507 uint8_t RESERVED_0[16];
3508 struct { /* offset: 0x70 */
3509 __IO uint32_t RW; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */
3510 __IO uint32_t SET; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */
3511 __IO uint32_t CLR; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */
3512 __IO uint32_t TOG; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */
3513 } LAYOUTSELECT;
3514 struct { /* offset: 0x80 */
3515 __IO uint32_t RW; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */
3516 __IO uint32_t SET; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */
3517 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */
3518 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */
3519 } FLASH0LAYOUT0;
3520 struct { /* offset: 0x90 */
3521 __IO uint32_t RW; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */
3522 __IO uint32_t SET; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */
3523 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */
3524 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */
3525 } FLASH0LAYOUT1;
3526 struct { /* offset: 0xA0 */
3527 __IO uint32_t RW; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */
3528 __IO uint32_t SET; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */
3529 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */
3530 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */
3531 } FLASH1LAYOUT0;
3532 struct { /* offset: 0xB0 */
3533 __IO uint32_t RW; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */
3534 __IO uint32_t SET; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */
3535 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */
3536 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */
3537 } FLASH1LAYOUT1;
3538 struct { /* offset: 0xC0 */
3539 __IO uint32_t RW; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */
3540 __IO uint32_t SET; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */
3541 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */
3542 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */
3543 } FLASH2LAYOUT0;
3544 struct { /* offset: 0xD0 */
3545 __IO uint32_t RW; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */
3546 __IO uint32_t SET; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */
3547 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */
3548 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */
3549 } FLASH2LAYOUT1;
3550 struct { /* offset: 0xE0 */
3551 __IO uint32_t RW; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */
3552 __IO uint32_t SET; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */
3553 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */
3554 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */
3555 } FLASH3LAYOUT0;
3556 struct { /* offset: 0xF0 */
3557 __IO uint32_t RW; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */
3558 __IO uint32_t SET; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */
3559 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */
3560 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */
3561 } FLASH3LAYOUT1;
3562 struct { /* offset: 0x100 */
3563 __IO uint32_t RW; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */
3564 __IO uint32_t SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */
3565 __IO uint32_t CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */
3566 __IO uint32_t TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */
3567 } DEBUG0;
3568 struct { /* offset: 0x110 */
3569 __I uint32_t RW; /**< KES Debug Read Register, offset: 0x110 */
3570 __I uint32_t SET; /**< KES Debug Read Register, offset: 0x114 */
3571 __I uint32_t CLR; /**< KES Debug Read Register, offset: 0x118 */
3572 __I uint32_t TOG; /**< KES Debug Read Register, offset: 0x11C */
3573 } DBGKESREAD;
3574 struct { /* offset: 0x120 */
3575 __I uint32_t RW; /**< Chien Search Debug Read Register, offset: 0x120 */
3576 __I uint32_t SET; /**< Chien Search Debug Read Register, offset: 0x124 */
3577 __I uint32_t CLR; /**< Chien Search Debug Read Register, offset: 0x128 */
3578 __I uint32_t TOG; /**< Chien Search Debug Read Register, offset: 0x12C */
3579 } DBGCSFEREAD;
3580 struct { /* offset: 0x130 */
3581 __I uint32_t RW; /**< Syndrome Generator Debug Read Register, offset: 0x130 */
3582 __I uint32_t SET; /**< Syndrome Generator Debug Read Register, offset: 0x134 */
3583 __I uint32_t CLR; /**< Syndrome Generator Debug Read Register, offset: 0x138 */
3584 __I uint32_t TOG; /**< Syndrome Generator Debug Read Register, offset: 0x13C */
3585 } DBGSYNDGENREAD;
3586 struct { /* offset: 0x140 */
3587 __I uint32_t RW; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */
3588 __I uint32_t SET; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */
3589 __I uint32_t CLR; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */
3590 __I uint32_t TOG; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */
3591 } DBGAHBMREAD;
3592 struct { /* offset: 0x150 */
3593 __I uint32_t RW; /**< Block Name Register, offset: 0x150 */
3594 __I uint32_t SET; /**< Block Name Register, offset: 0x154 */
3595 __I uint32_t CLR; /**< Block Name Register, offset: 0x158 */
3596 __I uint32_t TOG; /**< Block Name Register, offset: 0x15C */
3597 } BLOCKNAME;
3598 struct { /* offset: 0x160 */
3599 __I uint32_t RW; /**< BCH Version Register, offset: 0x160 */
3600 __I uint32_t SET; /**< BCH Version Register, offset: 0x164 */
3601 __I uint32_t CLR; /**< BCH Version Register, offset: 0x168 */
3602 __I uint32_t TOG; /**< BCH Version Register, offset: 0x16C */
3603 } VERSION;
3604 struct { /* offset: 0x170 */
3605 __IO uint32_t RW; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */
3606 __IO uint32_t SET; /**< Hardware BCH ECC Debug Register 1, offset: 0x174 */
3607 __IO uint32_t CLR; /**< Hardware BCH ECC Debug Register 1, offset: 0x178 */
3608 __IO uint32_t TOG; /**< Hardware BCH ECC Debug Register 1, offset: 0x17C */
3609 } DEBUG1;
3610} BCH_Type;
3611
3612/* ----------------------------------------------------------------------------
3613 -- BCH Register Masks
3614 ---------------------------------------------------------------------------- */
3615
3616/*!
3617 * @addtogroup BCH_Register_Masks BCH Register Masks
3618 * @{
3619 */
3620
3621/*! @name CTRL - Hardware BCH ECC Accelerator Control Register */
3622/*! @{ */
3623#define BCH_CTRL_COMPLETE_IRQ_MASK (0x1U)
3624#define BCH_CTRL_COMPLETE_IRQ_SHIFT (0U)
3625/*! COMPLETE_IRQ - COMPLETE_IRQ
3626 */
3627#define BCH_CTRL_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK)
3628#define BCH_CTRL_RSVD0_MASK (0x2U)
3629#define BCH_CTRL_RSVD0_SHIFT (1U)
3630/*! RSVD0 - This field is reserved.
3631 */
3632#define BCH_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK)
3633#define BCH_CTRL_DEBUG_STALL_IRQ_MASK (0x4U)
3634#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT (2U)
3635/*! DEBUG_STALL_IRQ - DEBUG_STALL_IRQ
3636 */
3637#define BCH_CTRL_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK)
3638#define BCH_CTRL_BM_ERROR_IRQ_MASK (0x8U)
3639#define BCH_CTRL_BM_ERROR_IRQ_SHIFT (3U)
3640/*! BM_ERROR_IRQ - BM_ERROR_IRQ
3641 */
3642#define BCH_CTRL_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK)
3643#define BCH_CTRL_RSVD1_MASK (0xF0U)
3644#define BCH_CTRL_RSVD1_SHIFT (4U)
3645/*! RSVD1 - This field is reserved.
3646 */
3647#define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK)
3648#define BCH_CTRL_COMPLETE_IRQ_EN_MASK (0x100U)
3649#define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT (8U)
3650/*! COMPLETE_IRQ_EN - COMPLETE_IRQ_EN
3651 */
3652#define BCH_CTRL_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK)
3653#define BCH_CTRL_RSVD2_MASK (0x200U)
3654#define BCH_CTRL_RSVD2_SHIFT (9U)
3655/*! RSVD2 - This field is reserved.
3656 */
3657#define BCH_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK)
3658#define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK (0x400U)
3659#define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT (10U)
3660/*! DEBUG_STALL_IRQ_EN - DEBUG_STALL_IRQ_EN
3661 */
3662#define BCH_CTRL_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK)
3663#define BCH_CTRL_RSVD3_MASK (0xF800U)
3664#define BCH_CTRL_RSVD3_SHIFT (11U)
3665/*! RSVD3 - This field is reserved.
3666 */
3667#define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK)
3668#define BCH_CTRL_M2M_ENABLE_MASK (0x10000U)
3669#define BCH_CTRL_M2M_ENABLE_SHIFT (16U)
3670/*! M2M_ENABLE - M2M_ENABLE
3671 */
3672#define BCH_CTRL_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK)
3673#define BCH_CTRL_M2M_ENCODE_MASK (0x20000U)
3674#define BCH_CTRL_M2M_ENCODE_SHIFT (17U)
3675/*! M2M_ENCODE - M2M_ENCODE
3676 */
3677#define BCH_CTRL_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK)
3678#define BCH_CTRL_M2M_LAYOUT_MASK (0xC0000U)
3679#define BCH_CTRL_M2M_LAYOUT_SHIFT (18U)
3680/*! M2M_LAYOUT - M2M_LAYOUT
3681 */
3682#define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK)
3683#define BCH_CTRL_RSVD4_MASK (0x300000U)
3684#define BCH_CTRL_RSVD4_SHIFT (20U)
3685/*! RSVD4 - This field is reserved.
3686 */
3687#define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK)
3688#define BCH_CTRL_DEBUGSYNDROME_MASK (0x400000U)
3689#define BCH_CTRL_DEBUGSYNDROME_SHIFT (22U)
3690/*! DEBUGSYNDROME - DEBUGSYNDROME
3691 */
3692#define BCH_CTRL_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK)
3693#define BCH_CTRL_RSVD5_MASK (0x3F800000U)
3694#define BCH_CTRL_RSVD5_SHIFT (23U)
3695/*! RSVD5 - This field is reserved.
3696 */
3697#define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK)
3698#define BCH_CTRL_CLKGATE_MASK (0x40000000U)
3699#define BCH_CTRL_CLKGATE_SHIFT (30U)
3700/*! CLKGATE - CLKGATE
3701 * 0b0..Allow BCH to operate normally.
3702 * 0b1..Do not clock BCH gates in order to minimize power consumption.
3703 */
3704#define BCH_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK)
3705#define BCH_CTRL_SFTRST_MASK (0x80000000U)
3706#define BCH_CTRL_SFTRST_SHIFT (31U)
3707/*! SFTRST - SFTRST
3708 * 0b0..Allow BCH to operate normally.
3709 * 0b1..Hold BCH in reset.
3710 */
3711#define BCH_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK)
3712/*! @} */
3713
3714/*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */
3715/*! @{ */
3716#define BCH_STATUS0_RSVD0_MASK (0x3U)
3717#define BCH_STATUS0_RSVD0_SHIFT (0U)
3718/*! RSVD0 - This field is reserved.
3719 */
3720#define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK)
3721#define BCH_STATUS0_UNCORRECTABLE_MASK (0x4U)
3722#define BCH_STATUS0_UNCORRECTABLE_SHIFT (2U)
3723/*! UNCORRECTABLE - UNCORRECTABLE
3724 */
3725#define BCH_STATUS0_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK)
3726#define BCH_STATUS0_CORRECTED_MASK (0x8U)
3727#define BCH_STATUS0_CORRECTED_SHIFT (3U)
3728/*! CORRECTED - CORRECTED
3729 */
3730#define BCH_STATUS0_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK)
3731#define BCH_STATUS0_ALLONES_MASK (0x10U)
3732#define BCH_STATUS0_ALLONES_SHIFT (4U)
3733/*! ALLONES - ALLONES
3734 */
3735#define BCH_STATUS0_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK)
3736#define BCH_STATUS0_RSVD1_MASK (0xE0U)
3737#define BCH_STATUS0_RSVD1_SHIFT (5U)
3738/*! RSVD1 - This field is reserved.
3739 */
3740#define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK)
3741#define BCH_STATUS0_STATUS_BLK0_MASK (0xFF00U)
3742#define BCH_STATUS0_STATUS_BLK0_SHIFT (8U)
3743/*! STATUS_BLK0 - STATUS_BLK0
3744 * 0b00000000..No errors found on block.
3745 * 0b00000001..One error found on block.
3746 * 0b00000010..One errors found on block.
3747 * 0b00000011..One errors found on block.
3748 * 0b00000100..One errors found on block.
3749 * 0b11111110..Block exhibited uncorrectable errors.
3750 * 0b11111111..Page is erased.
3751 */
3752#define BCH_STATUS0_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK)
3753#define BCH_STATUS0_COMPLETED_CE_MASK (0xF0000U)
3754#define BCH_STATUS0_COMPLETED_CE_SHIFT (16U)
3755/*! COMPLETED_CE - COMPLETED_CE
3756 */
3757#define BCH_STATUS0_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK)
3758#define BCH_STATUS0_HANDLE_MASK (0xFFF00000U)
3759#define BCH_STATUS0_HANDLE_SHIFT (20U)
3760/*! HANDLE - HANDLE
3761 */
3762#define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK)
3763/*! @} */
3764
3765/*! @name MODE - Hardware ECC Accelerator Mode Register */
3766/*! @{ */
3767#define BCH_MODE_ERASE_THRESHOLD_MASK (0xFFU)
3768#define BCH_MODE_ERASE_THRESHOLD_SHIFT (0U)
3769/*! ERASE_THRESHOLD - ERASE_THRESHOLD
3770 */
3771#define BCH_MODE_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK)
3772#define BCH_MODE_RSVD_MASK (0xFFFFFF00U)
3773#define BCH_MODE_RSVD_SHIFT (8U)
3774/*! RSVD - This field is reserved.
3775 */
3776#define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK)
3777/*! @} */
3778
3779/*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */
3780/*! @{ */
3781#define BCH_ENCODEPTR_ADDR_MASK (0xFFFFFFFFU)
3782#define BCH_ENCODEPTR_ADDR_SHIFT (0U)
3783/*! ADDR - ADDR
3784 */
3785#define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK)
3786/*! @} */
3787
3788/*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */
3789/*! @{ */
3790#define BCH_DATAPTR_ADDR_MASK (0xFFFFFFFFU)
3791#define BCH_DATAPTR_ADDR_SHIFT (0U)
3792/*! ADDR - ADDR
3793 */
3794#define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK)
3795/*! @} */
3796
3797/*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */
3798/*! @{ */
3799#define BCH_METAPTR_ADDR_MASK (0xFFFFFFFFU)
3800#define BCH_METAPTR_ADDR_SHIFT (0U)
3801/*! ADDR - ADDR
3802 */
3803#define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK)
3804/*! @} */
3805
3806/*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */
3807/*! @{ */
3808#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3U)
3809#define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT (0U)
3810/*! CS0_SELECT - CS0_SELECT
3811 */
3812#define BCH_LAYOUTSELECT_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK)
3813#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0xCU)
3814#define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT (2U)
3815/*! CS1_SELECT - CS1_SELECT
3816 */
3817#define BCH_LAYOUTSELECT_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK)
3818#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x30U)
3819#define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT (4U)
3820/*! CS2_SELECT - CS2_SELECT
3821 */
3822#define BCH_LAYOUTSELECT_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK)
3823#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0xC0U)
3824#define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT (6U)
3825/*! CS3_SELECT - CS3_SELECT
3826 */
3827#define BCH_LAYOUTSELECT_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK)
3828#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x300U)
3829#define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT (8U)
3830/*! CS4_SELECT - CS4_SELECT
3831 */
3832#define BCH_LAYOUTSELECT_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK)
3833#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0xC00U)
3834#define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT (10U)
3835/*! CS5_SELECT - CS5_SELECT
3836 */
3837#define BCH_LAYOUTSELECT_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK)
3838#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3000U)
3839#define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT (12U)
3840/*! CS6_SELECT - CS6_SELECT
3841 */
3842#define BCH_LAYOUTSELECT_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK)
3843#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0xC000U)
3844#define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT (14U)
3845/*! CS7_SELECT - CS7_SELECT
3846 */
3847#define BCH_LAYOUTSELECT_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK)
3848#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x30000U)
3849#define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT (16U)
3850/*! CS8_SELECT - CS8_SELECT
3851 */
3852#define BCH_LAYOUTSELECT_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK)
3853#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0xC0000U)
3854#define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT (18U)
3855/*! CS9_SELECT - CS9_SELECT
3856 */
3857#define BCH_LAYOUTSELECT_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK)
3858#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x300000U)
3859#define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT (20U)
3860/*! CS10_SELECT - CS10_SELECT
3861 */
3862#define BCH_LAYOUTSELECT_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK)
3863#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0xC00000U)
3864#define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT (22U)
3865/*! CS11_SELECT - CS11_SELECT
3866 */
3867#define BCH_LAYOUTSELECT_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK)
3868#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3000000U)
3869#define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT (24U)
3870/*! CS12_SELECT - CS12_SELECT
3871 */
3872#define BCH_LAYOUTSELECT_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK)
3873#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0xC000000U)
3874#define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT (26U)
3875/*! CS13_SELECT - CS13_SELECT
3876 */
3877#define BCH_LAYOUTSELECT_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK)
3878#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x30000000U)
3879#define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT (28U)
3880/*! CS14_SELECT - CS14_SELECT
3881 */
3882#define BCH_LAYOUTSELECT_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK)
3883#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0xC0000000U)
3884#define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT (30U)
3885/*! CS15_SELECT - CS15_SELECT
3886 */
3887#define BCH_LAYOUTSELECT_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK)
3888/*! @} */
3889
3890/*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */
3891/*! @{ */
3892#define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
3893#define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT (0U)
3894/*! DATA0_SIZE - DATA0_SIZE
3895 */
3896#define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK)
3897#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
3898#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
3899/*! GF13_0_GF14_1 - GF13_0_GF14_1
3900 */
3901#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK)
3902#define BCH_FLASH0LAYOUT0_ECC0_MASK (0xF800U)
3903#define BCH_FLASH0LAYOUT0_ECC0_SHIFT (11U)
3904/*! ECC0 - ECC0
3905 * 0b00000..No ECC to be performed
3906 * 0b00001..ECC 2 to be performed
3907 * 0b00010..ECC 4 to be performed
3908 * 0b11110..ECC 60 to be performed
3909 * 0b11111..ECC 62 to be performed
3910 */
3911#define BCH_FLASH0LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK)
3912#define BCH_FLASH0LAYOUT0_META_SIZE_MASK (0xFF0000U)
3913#define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT (16U)
3914/*! META_SIZE - META_SIZE
3915 */
3916#define BCH_FLASH0LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK)
3917#define BCH_FLASH0LAYOUT0_NBLOCKS_MASK (0xFF000000U)
3918#define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT (24U)
3919/*! NBLOCKS - NBLOCKS
3920 */
3921#define BCH_FLASH0LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK)
3922/*! @} */
3923
3924/*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */
3925/*! @{ */
3926#define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
3927#define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT (0U)
3928/*! DATAN_SIZE - DATAN_SIZE
3929 */
3930#define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK)
3931#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
3932#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
3933/*! GF13_0_GF14_1 - GF13_0_GF14_1
3934 */
3935#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK)
3936#define BCH_FLASH0LAYOUT1_ECCN_MASK (0xF800U)
3937#define BCH_FLASH0LAYOUT1_ECCN_SHIFT (11U)
3938/*! ECCN - ECCN
3939 * 0b00000..No ECC to be performed
3940 * 0b00001..ECC 2 to be performed
3941 * 0b00010..ECC 4 to be performed
3942 * 0b11110..ECC 60 to be performed
3943 * 0b11111..ECC 62 to be performed
3944 */
3945#define BCH_FLASH0LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK)
3946#define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
3947#define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT (16U)
3948/*! PAGE_SIZE - PAGE_SIZE
3949 */
3950#define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK)
3951/*! @} */
3952
3953/*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */
3954/*! @{ */
3955#define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
3956#define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT (0U)
3957/*! DATA0_SIZE - DATA0_SIZE
3958 */
3959#define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK)
3960#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
3961#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
3962/*! GF13_0_GF14_1 - GF13_0_GF14_1
3963 */
3964#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK)
3965#define BCH_FLASH1LAYOUT0_ECC0_MASK (0xF800U)
3966#define BCH_FLASH1LAYOUT0_ECC0_SHIFT (11U)
3967/*! ECC0 - ECC0
3968 * 0b00000..No ECC to be performed
3969 * 0b00001..ECC 2 to be performed
3970 * 0b00010..ECC 4 to be performed
3971 * 0b11110..ECC 60 to be performed
3972 * 0b11111..ECC 62 to be performed
3973 */
3974#define BCH_FLASH1LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK)
3975#define BCH_FLASH1LAYOUT0_META_SIZE_MASK (0xFF0000U)
3976#define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT (16U)
3977/*! META_SIZE - META_SIZE
3978 */
3979#define BCH_FLASH1LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK)
3980#define BCH_FLASH1LAYOUT0_NBLOCKS_MASK (0xFF000000U)
3981#define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT (24U)
3982/*! NBLOCKS - NBLOCKS
3983 */
3984#define BCH_FLASH1LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK)
3985/*! @} */
3986
3987/*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */
3988/*! @{ */
3989#define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
3990#define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT (0U)
3991/*! DATAN_SIZE - DATAN_SIZE
3992 */
3993#define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK)
3994#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
3995#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
3996/*! GF13_0_GF14_1 - GF13_0_GF14_1
3997 */
3998#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK)
3999#define BCH_FLASH1LAYOUT1_ECCN_MASK (0xF800U)
4000#define BCH_FLASH1LAYOUT1_ECCN_SHIFT (11U)
4001/*! ECCN - ECCN
4002 * 0b00000..No ECC to be performed
4003 * 0b00001..ECC 2 to be performed
4004 * 0b00010..ECC 4 to be performed
4005 * 0b11110..ECC 60 to be performed
4006 * 0b11111..ECC 62 to be performed
4007 */
4008#define BCH_FLASH1LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK)
4009#define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
4010#define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT (16U)
4011/*! PAGE_SIZE - PAGE_SIZE
4012 */
4013#define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK)
4014/*! @} */
4015
4016/*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */
4017/*! @{ */
4018#define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
4019#define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT (0U)
4020/*! DATA0_SIZE - DATA0_SIZE
4021 */
4022#define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK)
4023#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
4024#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
4025/*! GF13_0_GF14_1 - GF13_0_GF14_1
4026 */
4027#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK)
4028#define BCH_FLASH2LAYOUT0_ECC0_MASK (0xF800U)
4029#define BCH_FLASH2LAYOUT0_ECC0_SHIFT (11U)
4030/*! ECC0 - ECC0
4031 * 0b00000..No ECC to be performed
4032 * 0b00001..ECC 2 to be performed
4033 * 0b00010..ECC 4 to be performed
4034 * 0b11110..ECC 60 to be performed
4035 * 0b11111..ECC 62 to be performed
4036 */
4037#define BCH_FLASH2LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK)
4038#define BCH_FLASH2LAYOUT0_META_SIZE_MASK (0xFF0000U)
4039#define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT (16U)
4040/*! META_SIZE - META_SIZE
4041 */
4042#define BCH_FLASH2LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK)
4043#define BCH_FLASH2LAYOUT0_NBLOCKS_MASK (0xFF000000U)
4044#define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT (24U)
4045/*! NBLOCKS - NBLOCKS
4046 */
4047#define BCH_FLASH2LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK)
4048/*! @} */
4049
4050/*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */
4051/*! @{ */
4052#define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
4053#define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT (0U)
4054/*! DATAN_SIZE - DATAN_SIZE
4055 */
4056#define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK)
4057#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
4058#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
4059/*! GF13_0_GF14_1 - GF13_0_GF14_1
4060 */
4061#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK)
4062#define BCH_FLASH2LAYOUT1_ECCN_MASK (0xF800U)
4063#define BCH_FLASH2LAYOUT1_ECCN_SHIFT (11U)
4064/*! ECCN - ECCN
4065 * 0b00000..No ECC to be performed
4066 * 0b00001..ECC 2 to be performed
4067 * 0b00010..ECC 4 to be performed
4068 * 0b11110..ECC 60 to be performed
4069 * 0b11111..ECC 62 to be performed
4070 */
4071#define BCH_FLASH2LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK)
4072#define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
4073#define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT (16U)
4074/*! PAGE_SIZE - PAGE_SIZE
4075 */
4076#define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK)
4077/*! @} */
4078
4079/*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */
4080/*! @{ */
4081#define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
4082#define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT (0U)
4083/*! DATA0_SIZE - DATA0_SIZE
4084 */
4085#define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK)
4086#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
4087#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
4088/*! GF13_0_GF14_1 - GF13_0_GF14_1
4089 */
4090#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK)
4091#define BCH_FLASH3LAYOUT0_ECC0_MASK (0xF800U)
4092#define BCH_FLASH3LAYOUT0_ECC0_SHIFT (11U)
4093/*! ECC0 - ECC0
4094 * 0b00000..No ECC to be performed
4095 * 0b00001..ECC 2 to be performed
4096 * 0b00010..ECC 4 to be performed
4097 * 0b11110..ECC 60 to be performed
4098 * 0b11111..ECC 62 to be performed
4099 */
4100#define BCH_FLASH3LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK)
4101#define BCH_FLASH3LAYOUT0_META_SIZE_MASK (0xFF0000U)
4102#define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT (16U)
4103/*! META_SIZE - META_SIZE
4104 */
4105#define BCH_FLASH3LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK)
4106#define BCH_FLASH3LAYOUT0_NBLOCKS_MASK (0xFF000000U)
4107#define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT (24U)
4108/*! NBLOCKS - NBLOCKS
4109 */
4110#define BCH_FLASH3LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK)
4111/*! @} */
4112
4113/*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */
4114/*! @{ */
4115#define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
4116#define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT (0U)
4117/*! DATAN_SIZE - DATAN_SIZE
4118 */
4119#define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK)
4120#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
4121#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
4122/*! GF13_0_GF14_1 - GF13_0_GF14_1
4123 */
4124#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK)
4125#define BCH_FLASH3LAYOUT1_ECCN_MASK (0xF800U)
4126#define BCH_FLASH3LAYOUT1_ECCN_SHIFT (11U)
4127/*! ECCN - ECCN
4128 * 0b00000..No ECC to be performed
4129 * 0b00001..ECC 2 to be performed
4130 * 0b00010..ECC 4 to be performed
4131 * 0b11110..ECC 60 to be performed
4132 * 0b11111..ECC 62 to be performed
4133 */
4134#define BCH_FLASH3LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK)
4135#define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
4136#define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT (16U)
4137/*! PAGE_SIZE - PAGE_SIZE
4138 */
4139#define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK)
4140/*! @} */
4141
4142/*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */
4143/*! @{ */
4144#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK (0x3FU)
4145#define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT (0U)
4146/*! DEBUG_REG_SELECT - DEBUG_REG_SELECT
4147 */
4148#define BCH_DEBUG0_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK)
4149#define BCH_DEBUG0_RSVD0_MASK (0xC0U)
4150#define BCH_DEBUG0_RSVD0_SHIFT (6U)
4151/*! RSVD0 - This field is reserved.
4152 */
4153#define BCH_DEBUG0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK)
4154#define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK (0x100U)
4155#define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT (8U)
4156/*! BM_KES_TEST_BYPASS - BM_KES_TEST_BYPASS
4157 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
4158 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
4159 */
4160#define BCH_DEBUG0_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK)
4161#define BCH_DEBUG0_KES_DEBUG_STALL_MASK (0x200U)
4162#define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT (9U)
4163/*! KES_DEBUG_STALL - KES_DEBUG_STALL
4164 * 0b0..KES FSM proceeds to next block supplied by bus master.
4165 * 0b1..KES FSM waits after current equations are solved and the search engine is started.
4166 */
4167#define BCH_DEBUG0_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK)
4168#define BCH_DEBUG0_KES_DEBUG_STEP_MASK (0x400U)
4169#define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT (10U)
4170/*! KES_DEBUG_STEP - KES_DEBUG_STEP
4171 */
4172#define BCH_DEBUG0_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK)
4173#define BCH_DEBUG0_KES_STANDALONE_MASK (0x800U)
4174#define BCH_DEBUG0_KES_STANDALONE_SHIFT (11U)
4175/*! KES_STANDALONE - KES_STANDALONE
4176 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
4177 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
4178 */
4179#define BCH_DEBUG0_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK)
4180#define BCH_DEBUG0_KES_DEBUG_KICK_MASK (0x1000U)
4181#define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT (12U)
4182/*! KES_DEBUG_KICK - KES_DEBUG_KICK
4183 */
4184#define BCH_DEBUG0_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK)
4185#define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK (0x2000U)
4186#define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT (13U)
4187/*! KES_DEBUG_MODE4K - KES_DEBUG_MODE4K
4188 * 0b1..Mode is set for 4K NAND pages.
4189 * 0b1..Mode is set for 2K NAND pages.
4190 */
4191#define BCH_DEBUG0_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK)
4192#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
4193#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
4194/*! KES_DEBUG_PAYLOAD_FLAG - KES_DEBUG_PAYLOAD_FLAG
4195 * 0b1..Payload is set for 512 bytes data block.
4196 * 0b1..Payload is set for 65 or 19 bytes auxiliary block.
4197 */
4198#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK)
4199#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
4200#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
4201/*! KES_DEBUG_SHIFT_SYND - KES_DEBUG_SHIFT_SYND
4202 */
4203#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK)
4204#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
4205#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
4206/*! KES_DEBUG_SYNDROME_SYMBOL - KES_DEBUG_SYNDROME_SYMBOL
4207 * 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
4208 * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
4209 */
4210#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK)
4211#define BCH_DEBUG0_RSVD1_MASK (0xFE000000U)
4212#define BCH_DEBUG0_RSVD1_SHIFT (25U)
4213/*! RSVD1 - This field is reserved.
4214 */
4215#define BCH_DEBUG0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK)
4216/*! @} */
4217
4218/*! @name DBGKESREAD - KES Debug Read Register */
4219/*! @{ */
4220#define BCH_DBGKESREAD_VALUES_MASK (0xFFFFFFFFU)
4221#define BCH_DBGKESREAD_VALUES_SHIFT (0U)
4222/*! VALUES - VALUES
4223 */
4224#define BCH_DBGKESREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK)
4225/*! @} */
4226
4227/*! @name DBGCSFEREAD - Chien Search Debug Read Register */
4228/*! @{ */
4229#define BCH_DBGCSFEREAD_VALUES_MASK (0xFFFFFFFFU)
4230#define BCH_DBGCSFEREAD_VALUES_SHIFT (0U)
4231/*! VALUES - VALUES
4232 */
4233#define BCH_DBGCSFEREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK)
4234/*! @} */
4235
4236/*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */
4237/*! @{ */
4238#define BCH_DBGSYNDGENREAD_VALUES_MASK (0xFFFFFFFFU)
4239#define BCH_DBGSYNDGENREAD_VALUES_SHIFT (0U)
4240/*! VALUES - VALUES
4241 */
4242#define BCH_DBGSYNDGENREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK)
4243/*! @} */
4244
4245/*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */
4246/*! @{ */
4247#define BCH_DBGAHBMREAD_VALUES_MASK (0xFFFFFFFFU)
4248#define BCH_DBGAHBMREAD_VALUES_SHIFT (0U)
4249/*! VALUES - VALUES
4250 */
4251#define BCH_DBGAHBMREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK)
4252/*! @} */
4253
4254/*! @name BLOCKNAME - Block Name Register */
4255/*! @{ */
4256#define BCH_BLOCKNAME_NAME_MASK (0xFFFFFFFFU)
4257#define BCH_BLOCKNAME_NAME_SHIFT (0U)
4258/*! NAME - NAME
4259 */
4260#define BCH_BLOCKNAME_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK)
4261/*! @} */
4262
4263/*! @name VERSION - BCH Version Register */
4264/*! @{ */
4265#define BCH_VERSION_STEP_MASK (0xFFFFU)
4266#define BCH_VERSION_STEP_SHIFT (0U)
4267/*! STEP - STEP
4268 */
4269#define BCH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK)
4270#define BCH_VERSION_MINOR_MASK (0xFF0000U)
4271#define BCH_VERSION_MINOR_SHIFT (16U)
4272/*! MINOR - MINOR
4273 */
4274#define BCH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK)
4275#define BCH_VERSION_MAJOR_MASK (0xFF000000U)
4276#define BCH_VERSION_MAJOR_SHIFT (24U)
4277/*! MAJOR - MAJOR
4278 */
4279#define BCH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK)
4280/*! @} */
4281
4282/*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */
4283/*! @{ */
4284#define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK (0x1FFU)
4285#define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT (0U)
4286/*! ERASED_ZERO_COUNT - ERASED_ZERO_COUNT
4287 */
4288#define BCH_DEBUG1_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK)
4289#define BCH_DEBUG1_RSVD_MASK (0x7FFFFE00U)
4290#define BCH_DEBUG1_RSVD_SHIFT (9U)
4291/*! RSVD - This field is reserved.
4292 */
4293#define BCH_DEBUG1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK)
4294#define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK (0x80000000U)
4295#define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT (31U)
4296/*! DEBUG1_PREERASECHK - DEBUG1_PREERASECHK
4297 * 0b0..Turn off pre-erase check
4298 * 0b1..Turn on pre-erase check
4299 */
4300#define BCH_DEBUG1_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK)
4301/*! @} */
4302
4303
4304/*!
4305 * @}
4306 */ /* end of group BCH_Register_Masks */
4307
4308
4309/* BCH - Peripheral instance base addresses */
4310/** Peripheral CONNECTIVITY__BCH base address */
4311#define CONNECTIVITY__BCH_BASE (0x5B814000u)
4312/** Peripheral CONNECTIVITY__BCH base pointer */
4313#define CONNECTIVITY__BCH ((BCH_Type *)CONNECTIVITY__BCH_BASE)
4314/** Array initializer of BCH peripheral base addresses */
4315#define BCH_BASE_ADDRS { CONNECTIVITY__BCH_BASE }
4316/** Array initializer of BCH peripheral base pointers */
4317#define BCH_BASE_PTRS { CONNECTIVITY__BCH }
4318
4319/*!
4320 * @}
4321 */ /* end of group BCH_Peripheral_Access_Layer */
4322
4323
4324/* ----------------------------------------------------------------------------
4325 -- CAN Peripheral Access Layer
4326 ---------------------------------------------------------------------------- */
4327
4328/*!
4329 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
4330 * @{
4331 */
4332
4333/** CAN - Register Layout Typedef */
4334typedef struct {
4335 __IO uint32_t MCR; /**< Module Configuration register, offset: 0x0 */
4336 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
4337 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
4338 uint8_t RESERVED_0[4];
4339 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask register, offset: 0x10 */
4340 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
4341 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
4342 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
4343 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
4344 __IO uint32_t IMASK2; /**< Interrupt Masks 2 register, offset: 0x24 */
4345 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
4346 __IO uint32_t IFLAG2; /**< Interrupt Flags 2 register, offset: 0x2C */
4347 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
4348 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
4349 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
4350 uint8_t RESERVED_1[8];
4351 __I uint32_t CRCR; /**< CRC register, offset: 0x44 */
4352 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
4353 __I uint32_t RXFIR; /**< Rx FIFO Information register, offset: 0x4C */
4354 __IO uint32_t CBT; /**< CAN Bit Timing register, offset: 0x50 */
4355 uint8_t RESERVED_2[4];
4356 __I uint32_t DBG1; /**< Debug 1 register, offset: 0x58 */
4357 __I uint32_t DBG2; /**< Debug 2 register, offset: 0x5C */
4358 uint8_t RESERVED_3[32];
4359 struct { /* offset: 0x80, array step: 0x10 */
4360 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
4361 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
4362 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
4363 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
4364 } MB[64];
4365 uint8_t RESERVED_4[1024];
4366 __IO uint32_t RXIMR[64]; /**< Rx Individual Mask registers, array offset: 0x880, array step: 0x4 */
4367 uint8_t RESERVED_5[640];
4368 __IO uint32_t FDCTRL; /**< CAN FD Control register, offset: 0xC00 */
4369 __IO uint32_t FDCBT; /**< CAN FD Bit Timing register, offset: 0xC04 */
4370 __I uint32_t FDCRC; /**< CAN FD CRC register, offset: 0xC08 */
4371} CAN_Type;
4372
4373/* ----------------------------------------------------------------------------
4374 -- CAN Register Masks
4375 ---------------------------------------------------------------------------- */
4376
4377/*!
4378 * @addtogroup CAN_Register_Masks CAN Register Masks
4379 * @{
4380 */
4381
4382/*! @name MCR - Module Configuration register */
4383/*! @{ */
4384#define CAN_MCR_MAXMB_MASK (0x7FU)
4385#define CAN_MCR_MAXMB_SHIFT (0U)
4386/*! MAXMB - Number Of The Last Message Buffer
4387 */
4388#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
4389#define CAN_MCR_IDAM_MASK (0x300U)
4390#define CAN_MCR_IDAM_SHIFT (8U)
4391/*! IDAM - ID Acceptance Mode
4392 * 0b00..Format A: One full ID (standard and extended) per ID filter table element.
4393 * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element.
4394 * 0b10..Format C: Four partial 8-bit standard IDs per ID filter table element.
4395 * 0b11..Format D: All frames rejected.
4396 */
4397#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
4398#define CAN_MCR_FDEN_MASK (0x800U)
4399#define CAN_MCR_FDEN_SHIFT (11U)
4400/*! FDEN - CAN FD operation enable
4401 * 0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats.
4402 * 0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.
4403 */
4404#define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
4405#define CAN_MCR_AEN_MASK (0x1000U)
4406#define CAN_MCR_AEN_SHIFT (12U)
4407/*! AEN - Abort Enable
4408 * 0b0..Abort disabled.
4409 * 0b1..Abort enabled.
4410 */
4411#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
4412#define CAN_MCR_LPRIOEN_MASK (0x2000U)
4413#define CAN_MCR_LPRIOEN_SHIFT (13U)
4414/*! LPRIOEN - Local Priority Enable
4415 * 0b0..Local Priority disabled.
4416 * 0b1..Local Priority enabled.
4417 */
4418#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
4419#define CAN_MCR_DMA_MASK (0x8000U)
4420#define CAN_MCR_DMA_SHIFT (15U)
4421/*! DMA - DMA Enable
4422 * 0b0..DMA feature for RX FIFO disabled.
4423 * 0b1..DMA feature for RX FIFO enabled.
4424 */
4425#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
4426#define CAN_MCR_IRMQ_MASK (0x10000U)
4427#define CAN_MCR_IRMQ_SHIFT (16U)
4428/*! IRMQ - Individual Rx Masking And Queue Enable
4429 * 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy
4430 * applications, the reading of C/S word locks the MB even if it is EMPTY.
4431 * 0b1..Individual Rx masking and queue feature are enabled.
4432 */
4433#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
4434#define CAN_MCR_SRXDIS_MASK (0x20000U)
4435#define CAN_MCR_SRXDIS_SHIFT (17U)
4436/*! SRXDIS - Self Reception Disable
4437 * 0b0..Self-reception enabled.
4438 * 0b1..Self-reception disabled.
4439 */
4440#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
4441#define CAN_MCR_DOZE_MASK (0x40000U)
4442#define CAN_MCR_DOZE_SHIFT (18U)
4443/*! DOZE - Doze Mode Enable
4444 * 0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested.
4445 * 0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.
4446 */
4447#define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
4448#define CAN_MCR_WAKSRC_MASK (0x80000U)
4449#define CAN_MCR_WAKSRC_SHIFT (19U)
4450/*! WAKSRC - Wake Up Source
4451 * 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.
4452 * 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.
4453 */
4454#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
4455#define CAN_MCR_LPMACK_MASK (0x100000U)
4456#define CAN_MCR_LPMACK_SHIFT (20U)
4457/*! LPMACK - Low-Power Mode Acknowledge
4458 * 0b0..FlexCAN is not in a low-power mode.
4459 * 0b1..FlexCAN is in a low-power mode.
4460 */
4461#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
4462#define CAN_MCR_WRNEN_MASK (0x200000U)
4463#define CAN_MCR_WRNEN_SHIFT (21U)
4464/*! WRNEN - Warning Interrupt Enable
4465 * 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
4466 * 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.
4467 */
4468#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
4469#define CAN_MCR_SLFWAK_MASK (0x400000U)
4470#define CAN_MCR_SLFWAK_SHIFT (22U)
4471/*! SLFWAK - Self Wake Up
4472 * 0b0..FlexCAN Self Wake Up feature is disabled.
4473 * 0b1..FlexCAN Self Wake Up feature is enabled.
4474 */
4475#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
4476#define CAN_MCR_FRZACK_MASK (0x1000000U)
4477#define CAN_MCR_FRZACK_SHIFT (24U)
4478/*! FRZACK - Freeze Mode Acknowledge
4479 * 0b0..FlexCAN not in Freeze mode, prescaler running.
4480 * 0b1..FlexCAN in Freeze mode, prescaler stopped.
4481 */
4482#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
4483#define CAN_MCR_SOFTRST_MASK (0x2000000U)
4484#define CAN_MCR_SOFTRST_SHIFT (25U)
4485/*! SOFTRST - Soft Reset
4486 * 0b0..No reset request.
4487 * 0b1..Resets the registers affected by soft reset.
4488 */
4489#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
4490#define CAN_MCR_WAKMSK_MASK (0x4000000U)
4491#define CAN_MCR_WAKMSK_SHIFT (26U)
4492/*! WAKMSK - Wake Up Interrupt Mask
4493 * 0b0..Wake Up interrupt is disabled.
4494 * 0b1..Wake Up interrupt is enabled.
4495 */
4496#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
4497#define CAN_MCR_NOTRDY_MASK (0x8000000U)
4498#define CAN_MCR_NOTRDY_SHIFT (27U)
4499/*! NOTRDY - FlexCAN Not Ready
4500 * 0b0..FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode.
4501 * 0b1..FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode.
4502 */
4503#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
4504#define CAN_MCR_HALT_MASK (0x10000000U)
4505#define CAN_MCR_HALT_SHIFT (28U)
4506/*! HALT - Halt FlexCAN
4507 * 0b0..No Freeze mode request.
4508 * 0b1..Enters Freeze mode if the FRZ bit is asserted.
4509 */
4510#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
4511#define CAN_MCR_RFEN_MASK (0x20000000U)
4512#define CAN_MCR_RFEN_SHIFT (29U)
4513/*! RFEN - Rx FIFO Enable
4514 * 0b0..Rx FIFO not enabled.
4515 * 0b1..Rx FIFO enabled.
4516 */
4517#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
4518#define CAN_MCR_FRZ_MASK (0x40000000U)
4519#define CAN_MCR_FRZ_SHIFT (30U)
4520/*! FRZ - Freeze Enable
4521 * 0b0..Not enabled to enter Freeze mode.
4522 * 0b1..Enabled to enter Freeze mode.
4523 */
4524#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
4525#define CAN_MCR_MDIS_MASK (0x80000000U)
4526#define CAN_MCR_MDIS_SHIFT (31U)
4527/*! MDIS - Module Disable
4528 * 0b0..Enable the FlexCAN module.
4529 * 0b1..Disable the FlexCAN module.
4530 */
4531#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
4532/*! @} */
4533
4534/*! @name CTRL1 - Control 1 register */
4535/*! @{ */
4536#define CAN_CTRL1_PROPSEG_MASK (0x7U)
4537#define CAN_CTRL1_PROPSEG_SHIFT (0U)
4538/*! PROPSEG - Propagation Segment
4539 */
4540#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
4541#define CAN_CTRL1_LOM_MASK (0x8U)
4542#define CAN_CTRL1_LOM_SHIFT (3U)
4543/*! LOM - Listen-Only Mode
4544 * 0b0..Listen-Only mode is deactivated.
4545 * 0b1..FlexCAN module operates in Listen-Only mode.
4546 */
4547#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
4548#define CAN_CTRL1_LBUF_MASK (0x10U)
4549#define CAN_CTRL1_LBUF_SHIFT (4U)
4550/*! LBUF - Lowest Buffer Transmitted First
4551 * 0b0..Buffer with highest priority is transmitted first.
4552 * 0b1..Lowest number buffer is transmitted first.
4553 */
4554#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
4555#define CAN_CTRL1_TSYN_MASK (0x20U)
4556#define CAN_CTRL1_TSYN_SHIFT (5U)
4557/*! TSYN - Timer Sync
4558 * 0b0..Timer sync feature disabled
4559 * 0b1..Timer sync feature enabled
4560 */
4561#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
4562#define CAN_CTRL1_BOFFREC_MASK (0x40U)
4563#define CAN_CTRL1_BOFFREC_SHIFT (6U)
4564/*! BOFFREC - Bus Off Recovery
4565 * 0b0..Automatic recovering from Bus Off state enabled.
4566 * 0b1..Automatic recovering from Bus Off state disabled.
4567 */
4568#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
4569#define CAN_CTRL1_SMP_MASK (0x80U)
4570#define CAN_CTRL1_SMP_SHIFT (7U)
4571/*! SMP - CAN Bit Sampling
4572 * 0b0..Just one sample is used to determine the bit value.
4573 * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two
4574 * preceding samples; a majority rule is used.
4575 */
4576#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
4577#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
4578#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
4579/*! RWRNMSK - Rx Warning Interrupt Mask
4580 * 0b0..Rx Warning interrupt disabled.
4581 * 0b1..Rx Warning interrupt enabled.
4582 */
4583#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
4584#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
4585#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
4586/*! TWRNMSK - Tx Warning Interrupt Mask
4587 * 0b0..Tx Warning interrupt disabled.
4588 * 0b1..Tx Warning interrupt enabled.
4589 */
4590#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
4591#define CAN_CTRL1_LPB_MASK (0x1000U)
4592#define CAN_CTRL1_LPB_SHIFT (12U)
4593/*! LPB - Loop Back Mode
4594 * 0b0..Loop Back disabled.
4595 * 0b1..Loop Back enabled.
4596 */
4597#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
4598#define CAN_CTRL1_CLKSRC_MASK (0x2000U)
4599#define CAN_CTRL1_CLKSRC_SHIFT (13U)
4600/*! CLKSRC - CAN Engine Clock Source
4601 * 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.
4602 * 0b1..The CAN engine clock source is the peripheral clock.
4603 */
4604#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
4605#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
4606#define CAN_CTRL1_ERRMSK_SHIFT (14U)
4607/*! ERRMSK - Error Interrupt Mask
4608 * 0b0..Error interrupt disabled.
4609 * 0b1..Error interrupt enabled.
4610 */
4611#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
4612#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
4613#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
4614/*! BOFFMSK - Bus Off Interrupt Mask
4615 * 0b0..Bus Off interrupt disabled.
4616 * 0b1..Bus Off interrupt enabled.
4617 */
4618#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
4619#define CAN_CTRL1_PSEG2_MASK (0x70000U)
4620#define CAN_CTRL1_PSEG2_SHIFT (16U)
4621/*! PSEG2 - Phase Segment 2
4622 */
4623#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
4624#define CAN_CTRL1_PSEG1_MASK (0x380000U)
4625#define CAN_CTRL1_PSEG1_SHIFT (19U)
4626/*! PSEG1 - Phase Segment 1
4627 */
4628#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
4629#define CAN_CTRL1_RJW_MASK (0xC00000U)
4630#define CAN_CTRL1_RJW_SHIFT (22U)
4631/*! RJW - Resync Jump Width
4632 */
4633#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
4634#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
4635#define CAN_CTRL1_PRESDIV_SHIFT (24U)
4636/*! PRESDIV - Prescaler Division Factor
4637 */
4638#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
4639/*! @} */
4640
4641/*! @name TIMER - Free Running Timer */
4642/*! @{ */
4643#define CAN_TIMER_TIMER_MASK (0xFFFFU)
4644#define CAN_TIMER_TIMER_SHIFT (0U)
4645/*! TIMER - Timer Value
4646 */
4647#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
4648/*! @} */
4649
4650/*! @name RXMGMASK - Rx Mailboxes Global Mask register */
4651/*! @{ */
4652#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
4653#define CAN_RXMGMASK_MG_SHIFT (0U)
4654/*! MG - Rx Mailboxes Global Mask Bits
4655 */
4656#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
4657/*! @} */
4658
4659/*! @name RX14MASK - Rx 14 Mask register */
4660/*! @{ */
4661#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
4662#define CAN_RX14MASK_RX14M_SHIFT (0U)
4663/*! RX14M - Rx Buffer 14 Mask Bits
4664 */
4665#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
4666/*! @} */
4667
4668/*! @name RX15MASK - Rx 15 Mask register */
4669/*! @{ */
4670#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
4671#define CAN_RX15MASK_RX15M_SHIFT (0U)
4672/*! RX15M - Rx Buffer 15 Mask Bits
4673 */
4674#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
4675/*! @} */
4676
4677/*! @name ECR - Error Counter */
4678/*! @{ */
4679#define CAN_ECR_TXERRCNT_MASK (0xFFU)
4680#define CAN_ECR_TXERRCNT_SHIFT (0U)
4681/*! TXERRCNT - Transmit Error Counter
4682 */
4683#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
4684#define CAN_ECR_RXERRCNT_MASK (0xFF00U)
4685#define CAN_ECR_RXERRCNT_SHIFT (8U)
4686/*! RXERRCNT - Receive Error Counter
4687 */
4688#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
4689#define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U)
4690#define CAN_ECR_TXERRCNT_FAST_SHIFT (16U)
4691/*! TXERRCNT_FAST - Transmit Error Counter for fast bits
4692 */
4693#define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
4694#define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U)
4695#define CAN_ECR_RXERRCNT_FAST_SHIFT (24U)
4696/*! RXERRCNT_FAST - Receive Error Counter for fast bits
4697 */
4698#define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
4699/*! @} */
4700
4701/*! @name ESR1 - Error and Status 1 register */
4702/*! @{ */
4703#define CAN_ESR1_WAKINT_MASK (0x1U)
4704#define CAN_ESR1_WAKINT_SHIFT (0U)
4705/*! WAKINT - Wake-Up Interrupt
4706 * 0b0..No such occurrence.
4707 * 0b1..Indicates a recessive to dominant transition was received on the CAN bus.
4708 */
4709#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
4710#define CAN_ESR1_ERRINT_MASK (0x2U)
4711#define CAN_ESR1_ERRINT_SHIFT (1U)
4712/*! ERRINT - Error Interrupt
4713 * 0b0..No such occurrence.
4714 * 0b1..Indicates setting of any error bit in the Error and Status register.
4715 */
4716#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
4717#define CAN_ESR1_BOFFINT_MASK (0x4U)
4718#define CAN_ESR1_BOFFINT_SHIFT (2U)
4719/*! BOFFINT - Bus Off Interrupt
4720 * 0b0..No such occurrence.
4721 * 0b1..FlexCAN module entered Bus Off state.
4722 */
4723#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
4724#define CAN_ESR1_RX_MASK (0x8U)
4725#define CAN_ESR1_RX_SHIFT (3U)
4726/*! RX - FlexCAN In Reception
4727 * 0b0..FlexCAN is not receiving a message.
4728 * 0b1..FlexCAN is receiving a message.
4729 */
4730#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
4731#define CAN_ESR1_FLTCONF_MASK (0x30U)
4732#define CAN_ESR1_FLTCONF_SHIFT (4U)
4733/*! FLTCONF - Fault Confinement State
4734 * 0b00..Error Active
4735 * 0b01..Error Passive
4736 * 0b1x..Bus Off
4737 */
4738#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
4739#define CAN_ESR1_TX_MASK (0x40U)
4740#define CAN_ESR1_TX_SHIFT (6U)
4741/*! TX - FlexCAN In Transmission
4742 * 0b0..FlexCAN is not transmitting a message.
4743 * 0b1..FlexCAN is transmitting a message.
4744 */
4745#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
4746#define CAN_ESR1_IDLE_MASK (0x80U)
4747#define CAN_ESR1_IDLE_SHIFT (7U)
4748/*! IDLE - IDLE
4749 * 0b0..No such occurrence.
4750 * 0b1..CAN bus is now IDLE.
4751 */
4752#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
4753#define CAN_ESR1_RXWRN_MASK (0x100U)
4754#define CAN_ESR1_RXWRN_SHIFT (8U)
4755/*! RXWRN - Rx Error Warning
4756 * 0b0..No such occurrence.
4757 * 0b1..RXERRCNT is greater than or equal to 96.
4758 */
4759#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
4760#define CAN_ESR1_TXWRN_MASK (0x200U)
4761#define CAN_ESR1_TXWRN_SHIFT (9U)
4762/*! TXWRN - TX Error Warning
4763 * 0b0..No such occurrence.
4764 * 0b1..TXERRCNT is greater than or equal to 96.
4765 */
4766#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
4767#define CAN_ESR1_STFERR_MASK (0x400U)
4768#define CAN_ESR1_STFERR_SHIFT (10U)
4769/*! STFERR - Stuffing Error
4770 * 0b0..No such occurrence.
4771 * 0b1..A stuffing error occurred since last read of this register.
4772 */
4773#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
4774#define CAN_ESR1_FRMERR_MASK (0x800U)
4775#define CAN_ESR1_FRMERR_SHIFT (11U)
4776/*! FRMERR - Form Error
4777 * 0b0..No such occurrence.
4778 * 0b1..A Form Error occurred since last read of this register.
4779 */
4780#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
4781#define CAN_ESR1_CRCERR_MASK (0x1000U)
4782#define CAN_ESR1_CRCERR_SHIFT (12U)
4783/*! CRCERR - Cyclic Redundancy Check Error
4784 * 0b0..No such occurrence.
4785 * 0b1..A CRC error occurred since last read of this register.
4786 */
4787#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
4788#define CAN_ESR1_ACKERR_MASK (0x2000U)
4789#define CAN_ESR1_ACKERR_SHIFT (13U)
4790/*! ACKERR - Acknowledge Error
4791 * 0b0..No such occurrence.
4792 * 0b1..An ACK error occurred since last read of this register.
4793 */
4794#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
4795#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
4796#define CAN_ESR1_BIT0ERR_SHIFT (14U)
4797/*! BIT0ERR - Bit0 Error
4798 * 0b0..No such occurrence.
4799 * 0b1..At least one bit sent as dominant is received as recessive.
4800 */
4801#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
4802#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
4803#define CAN_ESR1_BIT1ERR_SHIFT (15U)
4804/*! BIT1ERR - Bit1 Error
4805 * 0b0..No such occurrence.
4806 * 0b1..At least one bit sent as recessive is received as dominant.
4807 */
4808#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
4809#define CAN_ESR1_RWRNINT_MASK (0x10000U)
4810#define CAN_ESR1_RWRNINT_SHIFT (16U)
4811/*! RWRNINT - Rx Warning Interrupt Flag
4812 * 0b0..No such occurrence.
4813 * 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.
4814 */
4815#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
4816#define CAN_ESR1_TWRNINT_MASK (0x20000U)
4817#define CAN_ESR1_TWRNINT_SHIFT (17U)
4818/*! TWRNINT - Tx Warning Interrupt Flag
4819 * 0b0..No such occurrence.
4820 * 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.
4821 */
4822#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
4823#define CAN_ESR1_SYNCH_MASK (0x40000U)
4824#define CAN_ESR1_SYNCH_SHIFT (18U)
4825/*! SYNCH - CAN Synchronization Status
4826 * 0b0..FlexCAN is not synchronized to the CAN bus.
4827 * 0b1..FlexCAN is synchronized to the CAN bus.
4828 */
4829#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
4830#define CAN_ESR1_BOFFDONEINT_MASK (0x80000U)
4831#define CAN_ESR1_BOFFDONEINT_SHIFT (19U)
4832/*! BOFFDONEINT - Bus Off Done Interrupt
4833 * 0b0..No such occurrence.
4834 * 0b1..FlexCAN module has completed Bus Off process.
4835 */
4836#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
4837#define CAN_ESR1_ERRINT_FAST_MASK (0x100000U)
4838#define CAN_ESR1_ERRINT_FAST_SHIFT (20U)
4839/*! ERRINT_FAST - Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set
4840 * 0b0..No such occurrence.
4841 * 0b1..Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set.
4842 */
4843#define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
4844#define CAN_ESR1_ERROVR_MASK (0x200000U)
4845#define CAN_ESR1_ERROVR_SHIFT (21U)
4846/*! ERROVR - Error Overrun
4847 * 0b0..Overrun has not occurred.
4848 * 0b1..Overrun has occurred.
4849 */
4850#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
4851#define CAN_ESR1_STFERR_FAST_MASK (0x4000000U)
4852#define CAN_ESR1_STFERR_FAST_SHIFT (26U)
4853/*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set
4854 * 0b0..No such occurrence.
4855 * 0b1..A stuffing error occurred since last read of this register.
4856 */
4857#define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
4858#define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U)
4859#define CAN_ESR1_FRMERR_FAST_SHIFT (27U)
4860/*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set
4861 * 0b0..No such occurrence.
4862 * 0b1..A form error occurred since last read of this register.
4863 */
4864#define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
4865#define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U)
4866#define CAN_ESR1_CRCERR_FAST_SHIFT (28U)
4867/*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set
4868 * 0b0..No such occurrence.
4869 * 0b1..A CRC error occurred since last read of this register.
4870 */
4871#define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
4872#define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U)
4873#define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U)
4874/*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set
4875 * 0b0..No such occurrence.
4876 * 0b1..At least one bit sent as dominant is received as recessive.
4877 */
4878#define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
4879#define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U)
4880#define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U)
4881/*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set
4882 * 0b0..No such occurrence.
4883 * 0b1..At least one bit sent as recessive is received as dominant.
4884 */
4885#define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
4886/*! @} */
4887
4888/*! @name IMASK2 - Interrupt Masks 2 register */
4889/*! @{ */
4890#define CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU)
4891#define CAN_IMASK2_BUF63TO32M_SHIFT (0U)
4892/*! BUF63TO32M - Buffer MBi Mask
4893 */
4894#define CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)
4895/*! @} */
4896
4897/*! @name IMASK1 - Interrupt Masks 1 register */
4898/*! @{ */
4899#define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU)
4900#define CAN_IMASK1_BUF31TO0M_SHIFT (0U)
4901/*! BUF31TO0M - Buffer MBi Mask
4902 */
4903#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
4904/*! @} */
4905
4906/*! @name IFLAG2 - Interrupt Flags 2 register */
4907/*! @{ */
4908#define CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU)
4909#define CAN_IFLAG2_BUF63TO32I_SHIFT (0U)
4910/*! BUF63TO32I - Buffer MBi Interrupt
4911 */
4912#define CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)
4913/*! @} */
4914
4915/*! @name IFLAG1 - Interrupt Flags 1 register */
4916/*! @{ */
4917#define CAN_IFLAG1_BUF0I_MASK (0x1U)
4918#define CAN_IFLAG1_BUF0I_SHIFT (0U)
4919/*! BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit
4920 * 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
4921 * 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
4922 */
4923#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
4924#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
4925#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
4926/*! BUF4TO1I - Buffer MBi Interrupt Or Reserved
4927 */
4928#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
4929#define CAN_IFLAG1_BUF5I_MASK (0x20U)
4930#define CAN_IFLAG1_BUF5I_SHIFT (5U)
4931/*! BUF5I - Buffer MB5 Interrupt Or Frames available in Rx FIFO
4932 * 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
4933 * 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when
4934 * MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.
4935 */
4936#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
4937#define CAN_IFLAG1_BUF6I_MASK (0x40U)
4938#define CAN_IFLAG1_BUF6I_SHIFT (6U)
4939/*! BUF6I - Buffer MB6 Interrupt Or Rx FIFO Warning
4940 * 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
4941 * 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1
4942 */
4943#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
4944#define CAN_IFLAG1_BUF7I_MASK (0x80U)
4945#define CAN_IFLAG1_BUF7I_SHIFT (7U)
4946/*! BUF7I - Buffer MB7 Interrupt Or Rx FIFO Overflow
4947 * 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
4948 * 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1
4949 */
4950#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
4951#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
4952#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
4953/*! BUF31TO8I - Buffer MBi Interrupt
4954 */
4955#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
4956/*! @} */
4957
4958/*! @name CTRL2 - Control 2 register */
4959/*! @{ */
4960#define CAN_CTRL2_EDFLTDIS_MASK (0x800U)
4961#define CAN_CTRL2_EDFLTDIS_SHIFT (11U)
4962/*! EDFLTDIS - Edge Filter Disable
4963 * 0b0..Edge filter is enabled
4964 * 0b1..Edge filter is disabled
4965 */
4966#define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)
4967#define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U)
4968#define CAN_CTRL2_ISOCANFDEN_SHIFT (12U)
4969/*! ISOCANFDEN - ISO CAN FD Enable
4970 * 0b0..FlexCAN operates using the non-ISO CAN FD protocol.
4971 * 0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1).
4972 */
4973#define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)
4974#define CAN_CTRL2_PREXCEN_MASK (0x4000U)
4975#define CAN_CTRL2_PREXCEN_SHIFT (14U)
4976/*! PREXCEN - Protocol Exception Enable
4977 * 0b0..Protocol exception is disabled.
4978 * 0b1..Protocol exception is enabled.
4979 */
4980#define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)
4981#define CAN_CTRL2_EACEN_MASK (0x10000U)
4982#define CAN_CTRL2_EACEN_SHIFT (16U)
4983/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
4984 * 0b0..Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
4985 * 0b1..Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within
4986 * the incoming frame. Mask bits do apply.
4987 */
4988#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
4989#define CAN_CTRL2_RRS_MASK (0x20000U)
4990#define CAN_CTRL2_RRS_SHIFT (17U)
4991/*! RRS - Remote Request Storing
4992 * 0b0..Remote response frame is generated.
4993 * 0b1..Remote request frame is stored.
4994 */
4995#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
4996#define CAN_CTRL2_MRP_MASK (0x40000U)
4997#define CAN_CTRL2_MRP_SHIFT (18U)
4998/*! MRP - Mailboxes Reception Priority
4999 * 0b0..Matching starts from Rx FIFO and continues on mailboxes.
5000 * 0b1..Matching starts from mailboxes and continues on Rx FIFO.
5001 */
5002#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
5003#define CAN_CTRL2_TASD_MASK (0xF80000U)
5004#define CAN_CTRL2_TASD_SHIFT (19U)
5005/*! TASD - Tx Arbitration Start Delay
5006 */
5007#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
5008#define CAN_CTRL2_RFFN_MASK (0xF000000U)
5009#define CAN_CTRL2_RFFN_SHIFT (24U)
5010/*! RFFN - Number Of Rx FIFO Filters
5011 */
5012#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
5013#define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U)
5014#define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U)
5015/*! BOFFDONEMSK - Bus Off Done Interrupt Mask
5016 * 0b0..Bus off done interrupt disabled.
5017 * 0b1..Bus off done interrupt enabled.
5018 */
5019#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
5020#define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U)
5021#define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U)
5022/*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames
5023 * 0b0..ERRINT_FAST error interrupt disabled.
5024 * 0b1..ERRINT_FAST error interrupt enabled.
5025 */
5026#define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
5027/*! @} */
5028
5029/*! @name ESR2 - Error and Status 2 register */
5030/*! @{ */
5031#define CAN_ESR2_IMB_MASK (0x2000U)
5032#define CAN_ESR2_IMB_SHIFT (13U)
5033/*! IMB - Inactive Mailbox
5034 * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox.
5035 * 0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one.
5036 */
5037#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
5038#define CAN_ESR2_VPS_MASK (0x4000U)
5039#define CAN_ESR2_VPS_SHIFT (14U)
5040/*! VPS - Valid Priority Status
5041 * 0b0..Contents of IMB and LPTM are invalid.
5042 * 0b1..Contents of IMB and LPTM are valid.
5043 */
5044#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
5045#define CAN_ESR2_LPTM_MASK (0x7F0000U)
5046#define CAN_ESR2_LPTM_SHIFT (16U)
5047/*! LPTM - Lowest Priority Tx Mailbox
5048 */
5049#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
5050/*! @} */
5051
5052/*! @name CRCR - CRC register */
5053/*! @{ */
5054#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
5055#define CAN_CRCR_TXCRC_SHIFT (0U)
5056/*! TXCRC - Transmitted CRC value
5057 */
5058#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
5059#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
5060#define CAN_CRCR_MBCRC_SHIFT (16U)
5061/*! MBCRC - CRC Mailbox
5062 */
5063#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
5064/*! @} */
5065
5066/*! @name RXFGMASK - Rx FIFO Global Mask register */
5067/*! @{ */
5068#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
5069#define CAN_RXFGMASK_FGM_SHIFT (0U)
5070/*! FGM - Rx FIFO Global Mask Bits
5071 */
5072#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
5073/*! @} */
5074
5075/*! @name RXFIR - Rx FIFO Information register */
5076/*! @{ */
5077#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
5078#define CAN_RXFIR_IDHIT_SHIFT (0U)
5079/*! IDHIT - Identifier Acceptance Filter Hit Indicator
5080 */
5081#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
5082/*! @} */
5083
5084/*! @name CBT - CAN Bit Timing register */
5085/*! @{ */
5086#define CAN_CBT_EPSEG2_MASK (0x1FU)
5087#define CAN_CBT_EPSEG2_SHIFT (0U)
5088/*! EPSEG2 - Extended Phase Segment 2
5089 */
5090#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
5091#define CAN_CBT_EPSEG1_MASK (0x3E0U)
5092#define CAN_CBT_EPSEG1_SHIFT (5U)
5093/*! EPSEG1 - Extended Phase Segment 1
5094 */
5095#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
5096#define CAN_CBT_EPROPSEG_MASK (0xFC00U)
5097#define CAN_CBT_EPROPSEG_SHIFT (10U)
5098/*! EPROPSEG - Extended Propagation Segment
5099 */
5100#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
5101#define CAN_CBT_ERJW_MASK (0x1F0000U)
5102#define CAN_CBT_ERJW_SHIFT (16U)
5103/*! ERJW - Extended Resync Jump Width
5104 */
5105#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
5106#define CAN_CBT_EPRESDIV_MASK (0x7FE00000U)
5107#define CAN_CBT_EPRESDIV_SHIFT (21U)
5108/*! EPRESDIV - Extended Prescaler Division Factor
5109 */
5110#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
5111#define CAN_CBT_BTF_MASK (0x80000000U)
5112#define CAN_CBT_BTF_SHIFT (31U)
5113/*! BTF - Bit Timing Format Enable
5114 * 0b0..Extended bit time definitions disabled.
5115 * 0b1..Extended bit time definitions enabled.
5116 */
5117#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
5118/*! @} */
5119
5120/*! @name DBG1 - Debug 1 register */
5121/*! @{ */
5122#define CAN_DBG1_CFSM_MASK (0x7FU)
5123#define CAN_DBG1_CFSM_SHIFT (0U)
5124/*! CFSM - CAN Finite State Machine
5125 */
5126#define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)
5127#define CAN_DBG1_CBN_MASK (0x3FF0000U)
5128#define CAN_DBG1_CBN_SHIFT (16U)
5129/*! CBN - CAN Bit Number
5130 */
5131#define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)
5132/*! @} */
5133
5134/*! @name DBG2 - Debug 2 register */
5135/*! @{ */
5136#define CAN_DBG2_RMP_MASK (0x7FU)
5137#define CAN_DBG2_RMP_SHIFT (0U)
5138/*! RMP - Rx Matching Pointer
5139 */
5140#define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)
5141#define CAN_DBG2_MPP_MASK (0x80U)
5142#define CAN_DBG2_MPP_SHIFT (7U)
5143/*! MPP - Matching Process in Progress
5144 * 0b0..No matching process ongoing
5145 * 0b1..Matching process is in progress.
5146 */
5147#define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)
5148#define CAN_DBG2_TAP_MASK (0x7F00U)
5149#define CAN_DBG2_TAP_SHIFT (8U)
5150/*! TAP - Tx Arbitration Pointer
5151 */
5152#define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)
5153#define CAN_DBG2_APP_MASK (0x8000U)
5154#define CAN_DBG2_APP_SHIFT (15U)
5155/*! APP - Arbitration Process in Progress
5156 * 0b0..No arbitration process ongoing
5157 * 0b1..Arbitration process is in progress.
5158 */
5159#define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)
5160/*! @} */
5161
5162/*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */
5163/*! @{ */
5164#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
5165#define CAN_CS_TIME_STAMP_SHIFT (0U)
5166/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
5167 * Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
5168 * appears on the CAN bus.
5169 */
5170#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
5171#define CAN_CS_DLC_MASK (0xF0000U)
5172#define CAN_CS_DLC_SHIFT (16U)
5173/*! DLC - Length of the data to be stored/transmitted.
5174 */
5175#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
5176#define CAN_CS_RTR_MASK (0x100000U)
5177#define CAN_CS_RTR_SHIFT (20U)
5178/*! RTR - Remote Transmission Request. One/zero for remote/data frame.
5179 */
5180#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
5181#define CAN_CS_IDE_MASK (0x200000U)
5182#define CAN_CS_IDE_SHIFT (21U)
5183/*! IDE - ID Extended. One/zero for extended/standard format frame.
5184 */
5185#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
5186#define CAN_CS_SRR_MASK (0x400000U)
5187#define CAN_CS_SRR_SHIFT (22U)
5188/*! SRR - Substitute Remote Request. Contains a fixed recessive bit.
5189 */
5190#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
5191#define CAN_CS_CODE_MASK (0xF000000U)
5192#define CAN_CS_CODE_SHIFT (24U)
5193/*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
5194 * the FlexCAN module itself, as part of the message buffer matching and arbitration process.
5195 */
5196#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
5197#define CAN_CS_ESI_MASK (0x20000000U)
5198#define CAN_CS_ESI_SHIFT (29U)
5199/*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive.
5200 */
5201#define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
5202#define CAN_CS_BRS_MASK (0x40000000U)
5203#define CAN_CS_BRS_SHIFT (30U)
5204/*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.
5205 */
5206#define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
5207#define CAN_CS_EDL_MASK (0x80000000U)
5208#define CAN_CS_EDL_SHIFT (31U)
5209/*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
5210 * The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
5211 */
5212#define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
5213/*! @} */
5214
5215/* The count of CAN_CS */
5216#define CAN_CS_COUNT (64U)
5217
5218/*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */
5219/*! @{ */
5220#define CAN_ID_EXT_MASK (0x3FFFFU)
5221#define CAN_ID_EXT_SHIFT (0U)
5222/*! EXT - Contains extended (LOW word) identifier of message buffer.
5223 */
5224#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
5225#define CAN_ID_STD_MASK (0x1FFC0000U)
5226#define CAN_ID_STD_SHIFT (18U)
5227/*! STD - Contains standard/extended (HIGH word) identifier of message buffer.
5228 */
5229#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
5230#define CAN_ID_PRIO_MASK (0xE0000000U)
5231#define CAN_ID_PRIO_SHIFT (29U)
5232/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
5233 * makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
5234 * ID to define the transmission priority.
5235 */
5236#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
5237/*! @} */
5238
5239/* The count of CAN_ID */
5240#define CAN_ID_COUNT (64U)
5241
5242/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
5243/*! @{ */
5244#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
5245#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
5246/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.
5247 */
5248#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
5249#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
5250#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
5251/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.
5252 */
5253#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
5254#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
5255#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
5256/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.
5257 */
5258#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
5259#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
5260#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
5261/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.
5262 */
5263#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
5264/*! @} */
5265
5266/* The count of CAN_WORD0 */
5267#define CAN_WORD0_COUNT (64U)
5268
5269/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
5270/*! @{ */
5271#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
5272#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
5273/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.
5274 */
5275#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
5276#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
5277#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
5278/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.
5279 */
5280#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
5281#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
5282#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
5283/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.
5284 */
5285#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
5286#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
5287#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
5288/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.
5289 */
5290#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
5291/*! @} */
5292
5293/* The count of CAN_WORD1 */
5294#define CAN_WORD1_COUNT (64U)
5295
5296/*! @name RXIMR - Rx Individual Mask registers */
5297/*! @{ */
5298#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
5299#define CAN_RXIMR_MI_SHIFT (0U)
5300/*! MI - Individual Mask Bits
5301 */
5302#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
5303/*! @} */
5304
5305/* The count of CAN_RXIMR */
5306#define CAN_RXIMR_COUNT (64U)
5307
5308/*! @name FDCTRL - CAN FD Control register */
5309/*! @{ */
5310#define CAN_FDCTRL_TDCVAL_MASK (0x3FU)
5311#define CAN_FDCTRL_TDCVAL_SHIFT (0U)
5312/*! TDCVAL - Transceiver Delay Compensation Value
5313 */
5314#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
5315#define CAN_FDCTRL_TDCOFF_MASK (0x1F00U)
5316#define CAN_FDCTRL_TDCOFF_SHIFT (8U)
5317/*! TDCOFF - Transceiver Delay Compensation Offset
5318 */
5319#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
5320#define CAN_FDCTRL_TDCFAIL_MASK (0x4000U)
5321#define CAN_FDCTRL_TDCFAIL_SHIFT (14U)
5322/*! TDCFAIL - Transceiver Delay Compensation Fail
5323 * 0b0..Measured loop delay is in range.
5324 * 0b1..Measured loop delay is out of range.
5325 */
5326#define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
5327#define CAN_FDCTRL_TDCEN_MASK (0x8000U)
5328#define CAN_FDCTRL_TDCEN_SHIFT (15U)
5329/*! TDCEN - Transceiver Delay Compensation Enable
5330 * 0b0..TDC is disabled
5331 * 0b1..TDC is enabled
5332 */
5333#define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
5334#define CAN_FDCTRL_MBDSR0_MASK (0x30000U)
5335#define CAN_FDCTRL_MBDSR0_SHIFT (16U)
5336/*! MBDSR0 - Message Buffer Data Size for Region 0
5337 * 0b00..Selects 8 bytes per message buffer.
5338 * 0b01..Selects 16 bytes per message buffer.
5339 * 0b10..Selects 32 bytes per message buffer.
5340 * 0b11..Selects 64 bytes per message buffer.
5341 */
5342#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
5343#define CAN_FDCTRL_MBDSR1_MASK (0x180000U)
5344#define CAN_FDCTRL_MBDSR1_SHIFT (19U)
5345/*! MBDSR1 - Message Buffer Data Size for Region 1
5346 * 0b00..Selects 8 bytes per message buffer.
5347 * 0b01..Selects 16 bytes per message buffer.
5348 * 0b10..Selects 32 bytes per message buffer.
5349 * 0b11..Selects 64 bytes per message buffer.
5350 */
5351#define CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)
5352#define CAN_FDCTRL_FDRATE_MASK (0x80000000U)
5353#define CAN_FDCTRL_FDRATE_SHIFT (31U)
5354/*! FDRATE - Bit Rate Switch Enable
5355 * 0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect.
5356 * 0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive.
5357 */
5358#define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
5359/*! @} */
5360
5361/*! @name FDCBT - CAN FD Bit Timing register */
5362/*! @{ */
5363#define CAN_FDCBT_FPSEG2_MASK (0x7U)
5364#define CAN_FDCBT_FPSEG2_SHIFT (0U)
5365/*! FPSEG2 - Fast Phase Segment 2
5366 */
5367#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
5368#define CAN_FDCBT_FPSEG1_MASK (0xE0U)
5369#define CAN_FDCBT_FPSEG1_SHIFT (5U)
5370/*! FPSEG1 - Fast Phase Segment 1
5371 */
5372#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
5373#define CAN_FDCBT_FPROPSEG_MASK (0x7C00U)
5374#define CAN_FDCBT_FPROPSEG_SHIFT (10U)
5375/*! FPROPSEG - Fast Propagation Segment
5376 */
5377#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
5378#define CAN_FDCBT_FRJW_MASK (0x70000U)
5379#define CAN_FDCBT_FRJW_SHIFT (16U)
5380/*! FRJW - Fast Resync Jump Width
5381 */
5382#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
5383#define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U)
5384#define CAN_FDCBT_FPRESDIV_SHIFT (20U)
5385/*! FPRESDIV - Fast Prescaler Division Factor
5386 */
5387#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
5388/*! @} */
5389
5390/*! @name FDCRC - CAN FD CRC register */
5391/*! @{ */
5392#define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU)
5393#define CAN_FDCRC_FD_TXCRC_SHIFT (0U)
5394/*! FD_TXCRC - Extended Transmitted CRC value
5395 */
5396#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
5397#define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U)
5398#define CAN_FDCRC_FD_MBCRC_SHIFT (24U)
5399/*! FD_MBCRC - CRC Mailbox Number for FD_TXCRC
5400 */
5401#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
5402/*! @} */
5403
5404
5405/*!
5406 * @}
5407 */ /* end of group CAN_Register_Masks */
5408
5409
5410/* CAN - Peripheral instance base addresses */
5411/** Peripheral ADMA__CAN0 base address */
5412#define ADMA__CAN0_BASE (0x5A8D0000u)
5413/** Peripheral ADMA__CAN0 base pointer */
5414#define ADMA__CAN0 ((CAN_Type *)ADMA__CAN0_BASE)
5415/** Peripheral ADMA__CAN1 base address */
5416#define ADMA__CAN1_BASE (0x5A8E0000u)
5417/** Peripheral ADMA__CAN1 base pointer */
5418#define ADMA__CAN1 ((CAN_Type *)ADMA__CAN1_BASE)
5419/** Peripheral ADMA__CAN2 base address */
5420#define ADMA__CAN2_BASE (0x5A8F0000u)
5421/** Peripheral ADMA__CAN2 base pointer */
5422#define ADMA__CAN2 ((CAN_Type *)ADMA__CAN2_BASE)
5423/** Array initializer of CAN peripheral base addresses */
5424#define CAN_BASE_ADDRS { ADMA__CAN0_BASE, ADMA__CAN1_BASE, ADMA__CAN2_BASE }
5425/** Array initializer of CAN peripheral base pointers */
5426#define CAN_BASE_PTRS { ADMA__CAN0, ADMA__CAN1, ADMA__CAN2 }
5427/** Interrupt vectors for the CAN peripheral type */
5428#define CAN_Rx_Warning_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5429#define CAN_Tx_Warning_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5430#define CAN_Wake_Up_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5431#define CAN_Error_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5432#define CAN_Bus_Off_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5433#define CAN_ORed_Message_buffer_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5434
5435/*!
5436 * @}
5437 */ /* end of group CAN_Peripheral_Access_Layer */
5438
5439
5440/* ----------------------------------------------------------------------------
5441 -- CI_PI_CSR Peripheral Access Layer
5442 ---------------------------------------------------------------------------- */
5443
5444/*!
5445 * @addtogroup CI_PI_CSR_Peripheral_Access_Layer CI_PI_CSR Peripheral Access Layer
5446 * @{
5447 */
5448
5449/** CI_PI_CSR - Register Layout Typedef */
5450typedef struct {
5451 struct { /* offset: 0x0 */
5452 __IO uint32_t RW; /**< CI_PI Interface Control Register, offset: 0x0 */
5453 __IO uint32_t SET; /**< CI_PI Interface Control Register, offset: 0x4 */
5454 __IO uint32_t CLR; /**< CI_PI Interface Control Register, offset: 0x8 */
5455 __IO uint32_t TOG; /**< CI_PI Interface Control Register, offset: 0xC */
5456 } IF_CTRL_REG;
5457 struct { /* offset: 0x10 */
5458 __IO uint32_t RW; /**< CSI Interface Control Register, offset: 0x10 */
5459 __IO uint32_t SET; /**< CSI Interface Control Register, offset: 0x14 */
5460 __IO uint32_t CLR; /**< CSI Interface Control Register, offset: 0x18 */
5461 __IO uint32_t TOG; /**< CSI Interface Control Register, offset: 0x1C */
5462 } CSI_CTRL_REG;
5463 struct { /* offset: 0x20 */
5464 __I uint32_t RW; /**< CSI Interface Status Register, offset: 0x20 */
5465 __I uint32_t SET; /**< CSI Interface Status Register, offset: 0x24 */
5466 __I uint32_t CLR; /**< CSI Interface Status Register, offset: 0x28 */
5467 __I uint32_t TOG; /**< CSI Interface Status Register, offset: 0x2C */
5468 } CSI_STATUS;
5469 struct { /* offset: 0x30 */
5470 __IO uint32_t RW; /**< CSI Interface Control Register1, offset: 0x30 */
5471 __IO uint32_t SET; /**< CSI Interface Control Register1, offset: 0x34 */
5472 __IO uint32_t CLR; /**< CSI Interface Control Register1, offset: 0x38 */
5473 __IO uint32_t TOG; /**< CSI Interface Control Register1, offset: 0x3C */
5474 } CSI_CTRL_REG1;
5475} CI_PI_CSR_Type;
5476
5477/* ----------------------------------------------------------------------------
5478 -- CI_PI_CSR Register Masks
5479 ---------------------------------------------------------------------------- */
5480
5481/*!
5482 * @addtogroup CI_PI_CSR_Register_Masks CI_PI_CSR Register Masks
5483 * @{
5484 */
5485
5486/*! @name IF_CTRL_REG - CI_PI Interface Control Register */
5487/*! @{ */
5488#define CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_MASK (0x1U)
5489#define CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_SHIFT (0U)
5490#define CI_PI_CSR_IF_CTRL_REG_PL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_MASK)
5491#define CI_PI_CSR_IF_CTRL_REG_PL_VALID_MASK (0x2U)
5492#define CI_PI_CSR_IF_CTRL_REG_PL_VALID_SHIFT (1U)
5493#define CI_PI_CSR_IF_CTRL_REG_PL_VALID(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_PL_VALID_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_PL_VALID_MASK)
5494#define CI_PI_CSR_IF_CTRL_REG_PL_ADDR_MASK (0x1CU)
5495#define CI_PI_CSR_IF_CTRL_REG_PL_ADDR_SHIFT (2U)
5496#define CI_PI_CSR_IF_CTRL_REG_PL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_PL_ADDR_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_PL_ADDR_MASK)
5497#define CI_PI_CSR_IF_CTRL_REG_IF_FORCE_MASK (0xE0U)
5498#define CI_PI_CSR_IF_CTRL_REG_IF_FORCE_SHIFT (5U)
5499#define CI_PI_CSR_IF_CTRL_REG_IF_FORCE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_IF_FORCE_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_IF_FORCE_MASK)
5500#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_MASK (0x100U)
5501#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_SHIFT (8U)
5502/*! DATA_TYPE_SEL - Pixel link data type select
5503 * 0b0..PL data type comes from the csi_interface
5504 * 0b1..PL data type comes from IF_CTRL DATA_TYPE[4:0]
5505 */
5506#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_MASK)
5507#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_MASK (0x3E00U)
5508#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SHIFT (9U)
5509/*! DATA_TYPE - Data type
5510 * 0b00000..Null data
5511 * 0b00100..RGB format
5512 * 0b01000..YUV444 Format
5513 * 0b10000..YYU420 odd line
5514 * 0b10010..YYU420 even line
5515 * 0b11000..YYY odd line
5516 * 0b11010..UYVY Even line
5517 * 0b11100..Raw
5518 */
5519#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_MASK)
5520/*! @} */
5521
5522/*! @name CSI_CTRL_REG - CSI Interface Control Register */
5523/*! @{ */
5524#define CI_PI_CSR_CSI_CTRL_REG_CSI_EN_MASK (0x1U)
5525#define CI_PI_CSR_CSI_CTRL_REG_CSI_EN_SHIFT (0U)
5526/*! CSI_EN - CSI interface enable
5527 */
5528#define CI_PI_CSR_CSI_CTRL_REG_CSI_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CSI_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CSI_EN_MASK)
5529#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_MASK (0x2U)
5530#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_SHIFT (1U)
5531/*! PIXEL_CLK_POL - Pixel Clock polarity control
5532 * 0b0..Pixel Clock input is not inverted
5533 * 0b1..Pixel Clock input is inverted
5534 */
5535#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_MASK)
5536#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_MASK (0x4U)
5537#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_SHIFT (2U)
5538/*! HSYNC_POL - HSYNC polarity control
5539 * 0b0..HSYNC output to Pixel Link is not inverted
5540 * 0b1..HSYNC output to Pixel Link is inverted
5541 */
5542#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_MASK)
5543#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_MASK (0x8U)
5544#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_SHIFT (3U)
5545/*! VSYNC_POL - VSYNC polarity control
5546 * 0b0..VSYNC output to Pixel Link is not inverted
5547 * 0b1..VSYNC output to Pixel Link is inverted
5548 */
5549#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_MASK)
5550#define CI_PI_CSR_CSI_CTRL_REG_DE_POL_MASK (0x10U)
5551#define CI_PI_CSR_CSI_CTRL_REG_DE_POL_SHIFT (4U)
5552/*! DE_POL - DE polarity control
5553 * 0b0..DE output to Pixel Link is not inverted
5554 * 0b1..DE output to Pixel Link is inverted
5555 */
5556#define CI_PI_CSR_CSI_CTRL_REG_DE_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_DE_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_DE_POL_MASK)
5557#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_MASK (0x20U)
5558#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_SHIFT (5U)
5559/*! PIXEL_DATA_POL - PIXEL_DATA polarity control
5560 * 0b0..PIXEL_DATA output to Pixel Link is not inverted
5561 * 0b1..PIXEL_DATA output to Pixel Link is inverted
5562 */
5563#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_MASK)
5564#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_MASK (0x40U)
5565#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_SHIFT (6U)
5566/*! CCIR_EXT_VSYNC_EN - External VSYNC enable
5567 */
5568#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_MASK)
5569#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_MASK (0x80U)
5570#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_SHIFT (7U)
5571/*! CCIR_EN - CCIR mode enable
5572 * 0b0..CCIR mode disable
5573 * 0b1..CCIR mode enable
5574 */
5575#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_MASK)
5576#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_MASK (0x100U)
5577#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_SHIFT (8U)
5578/*! CCIR_VIDEO_MODE - CCIR_VIDEO_MODE
5579 * 0b0..Progressive mode
5580 * 0b1..Interlace mode
5581 */
5582#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_MASK)
5583#define CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_MASK (0x200U)
5584#define CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_SHIFT (9U)
5585/*! CCIR_NTSC_EN - CCIR_NTSC enable
5586 * 0b0..PAL
5587 * 0b1..NTSC
5588 */
5589#define CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_MASK)
5590#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_MASK (0x400U)
5591#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_SHIFT (10U)
5592/*! CCIR_VSYNC_RESET_EN - CCIR_VSYNC_RESET_EN
5593 */
5594#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_MASK)
5595#define CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_MASK (0x800U)
5596#define CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_SHIFT (11U)
5597/*! CCIR_ECC_ERR_CORRECT_EN - CCIR_ECC_ERR_CORRECT_EN
5598 * 0b0..ECC error correction is disabled.
5599 * 0b1..ECC error correction is enabled.
5600 */
5601#define CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_MASK)
5602#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_MASK (0x1000U)
5603#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_SHIFT (12U)
5604/*! HSYNC_FORCE_EN - HSYNC_FORCE_EN
5605 * 0b0..Do not override HSYNC
5606 * 0b1..Override HSYNC
5607 */
5608#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_MASK)
5609#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_MASK (0x2000U)
5610#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_SHIFT (13U)
5611/*! VSYNC_FORCE_EN - VSYNC_FORCE_EN
5612 * 0b0..Do not override VSYNC
5613 * 0b1..Override VSYNC
5614 */
5615#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_MASK)
5616#define CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_MASK (0x4000U)
5617#define CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_SHIFT (14U)
5618/*! GCLK_MODE_EN - GCLK_MODE_EN
5619 * 0b0..Disable
5620 * 0b1..Enable
5621 */
5622#define CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_MASK)
5623#define CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_MASK (0x8000U)
5624#define CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_SHIFT (15U)
5625/*! VALID_SEL - VALID_SEL
5626 */
5627#define CI_PI_CSR_CSI_CTRL_REG_VALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_MASK)
5628#define CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_MASK (0x10000U)
5629#define CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_SHIFT (16U)
5630/*! RAW_OUT_SEL - RAW_OUT_SEL
5631 * 0b0..Right justified output
5632 * 0b1..Left justified to 14bit output
5633 */
5634#define CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_MASK)
5635#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_MASK (0x20000U)
5636#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_SHIFT (17U)
5637/*! HSYNC_OUT_SEL - HSYNC_OUT_SEL
5638 * 0b0..HSYNC output level
5639 * 0b1..HSYNC output pulse
5640 */
5641#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_MASK)
5642#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_MASK (0x380000U)
5643#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_SHIFT (19U)
5644/*! HSYNC_PULSE - HSYNC_PULSE
5645 */
5646#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_MASK)
5647#define CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_MASK (0x400000U)
5648#define CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_SHIFT (22U)
5649/*! UV_SWAP_EN - UV Swap enable
5650 * 0b0..UV swap disable
5651 * 0b1..UV swap enable
5652 */
5653#define CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_MASK)
5654#define CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_MASK (0x7800000U)
5655#define CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_SHIFT (23U)
5656/*! DATA_TYPE_IN - CSI input data type
5657 * 0b0000..UYVY bt656 8bit
5658 * 0b0001..UYVY bt656 10bit
5659 * 0b0010..RGB 8bit
5660 * 0b0011..BGR 8bit
5661 * 0b0100..RGB 24bit
5662 * 0b0101..YVYU 8bit
5663 * 0b0110..YUV 8bit
5664 * 0b0111..YVYU 16bit
5665 * 0b1000..YUV 24bit
5666 * 0b1001..Bayer 8bit
5667 * 0b1010..Bayer 10bit
5668 * 0b1011..Bayer 12bit
5669 * 0b1100..Bayer 16bit
5670 */
5671#define CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_MASK)
5672#define CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_MASK (0x18000000U)
5673#define CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_SHIFT (27U)
5674/*! MASK_VSYNC_COUNTER - CSI mask VSYNC counter
5675 * 0b00..not mask
5676 * 0b01..mask 1 frame
5677 * 0b10..mask 2 frames
5678 * 0b11..mask 3 frames
5679 */
5680#define CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_MASK)
5681#define CI_PI_CSR_CSI_CTRL_REG_SOFTRST_MASK (0x80000000U)
5682#define CI_PI_CSR_CSI_CTRL_REG_SOFTRST_SHIFT (31U)
5683/*! SOFTRST - SOFTRST
5684 */
5685#define CI_PI_CSR_CSI_CTRL_REG_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_SOFTRST_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_SOFTRST_MASK)
5686/*! @} */
5687
5688/*! @name CSI_STATUS - CSI Interface Status Register */
5689/*! @{ */
5690#define CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_MASK (0x1U)
5691#define CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_SHIFT (0U)
5692#define CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_SHIFT)) & CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_MASK)
5693#define CI_PI_CSR_CSI_STATUS_ECC_ERROR_MASK (0x2U)
5694#define CI_PI_CSR_CSI_STATUS_ECC_ERROR_SHIFT (1U)
5695#define CI_PI_CSR_CSI_STATUS_ECC_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_STATUS_ECC_ERROR_SHIFT)) & CI_PI_CSR_CSI_STATUS_ECC_ERROR_MASK)
5696/*! @} */
5697
5698/*! @name CSI_CTRL_REG1 - CSI Interface Control Register1 */
5699/*! @{ */
5700#define CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_MASK (0xFFFFU)
5701#define CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_SHIFT (0U)
5702/*! PIXEL_WIDTH - CSI interface enable
5703 */
5704#define CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_MASK)
5705#define CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_MASK (0xFFFF0000U)
5706#define CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_SHIFT (16U)
5707/*! VSYNC_PULSE - VSYNC_PULSE
5708 */
5709#define CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_MASK)
5710/*! @} */
5711
5712
5713/*!
5714 * @}
5715 */ /* end of group CI_PI_CSR_Register_Masks */
5716
5717
5718/* CI_PI_CSR - Peripheral instance base addresses */
5719/** Peripheral CI_PI_CSR base address */
5720#define CI_PI_CSR_BASE (0x58261000u)
5721/** Peripheral CI_PI_CSR base pointer */
5722#define CI_PI_CSR ((CI_PI_CSR_Type *)CI_PI_CSR_BASE)
5723/** Array initializer of CI_PI_CSR peripheral base addresses */
5724#define CI_PI_CSR_BASE_ADDRS { CI_PI_CSR_BASE }
5725/** Array initializer of CI_PI_CSR peripheral base pointers */
5726#define CI_PI_CSR_BASE_PTRS { CI_PI_CSR }
5727
5728/*!
5729 * @}
5730 */ /* end of group CI_PI_CSR_Peripheral_Access_Layer */
5731
5732
5733/* ----------------------------------------------------------------------------
5734 -- CM4_LPCG_LPI2C Peripheral Access Layer
5735 ---------------------------------------------------------------------------- */
5736
5737/*!
5738 * @addtogroup CM4_LPCG_LPI2C_Peripheral_Access_Layer CM4_LPCG_LPI2C Peripheral Access Layer
5739 * @{
5740 */
5741
5742/** CM4_LPCG_LPI2C - Register Layout Typedef */
5743typedef struct {
5744 __IO uint32_t LPCG_LPI2C_0; /**< na, offset: 0x0 */
5745} CM4_LPCG_LPI2C_Type;
5746
5747/* ----------------------------------------------------------------------------
5748 -- CM4_LPCG_LPI2C Register Masks
5749 ---------------------------------------------------------------------------- */
5750
5751/*!
5752 * @addtogroup CM4_LPCG_LPI2C_Register_Masks CM4_LPCG_LPI2C Register Masks
5753 * @{
5754 */
5755
5756/*! @name LPCG_LPI2C_0 - na */
5757/*! @{ */
5758#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK (0x1U)
5759#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT (0U)
5760/*! lpi2c1_lpi2c_div_clk_HWEN - Hardware Enable
5761 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
5762 * 0b1..Enable HW automatic gating
5763 */
5764#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK)
5765#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK (0x2U)
5766#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT (1U)
5767/*! lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN - Software Enable
5768 * 0b0..Disable SW clock regardless of HWEN
5769 * 0b1..Enable SW clock gating
5770 */
5771#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK)
5772#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK (0x4U)
5773#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT (2U)
5774/*! LPCG_LPI2C_0_reserved_2_2 - reserved
5775 */
5776#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK)
5777#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK (0x8U)
5778#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT (3U)
5779/*! lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped
5780 */
5781#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK)
5782#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK (0x10U)
5783#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT (4U)
5784/*! LPCG_LPI2C_0_reserved_4_4 - reserved
5785 */
5786#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK)
5787#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK (0x20U)
5788#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT (5U)
5789/*! lpi2c1_ipg_clk_SWEN - Software Enable
5790 * 0b0..Disable SW clock regardless of HWEN
5791 * 0b1..Enable SW clock gating
5792 */
5793#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK)
5794#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK (0x40U)
5795#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT (6U)
5796/*! LPCG_LPI2C_0_reserved_6_6 - reserved
5797 */
5798#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK)
5799#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK (0x80U)
5800#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT (7U)
5801/*! lpi2c1_ipg_clk_STOP - show clock root status, 1 means clock stopped
5802 */
5803#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK)
5804#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK (0xFFFFFF00U)
5805#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT (8U)
5806/*! LPCG_LPI2C_0_reserved_8_31 - reserved
5807 */
5808#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK)
5809/*! @} */
5810
5811
5812/*!
5813 * @}
5814 */ /* end of group CM4_LPCG_LPI2C_Register_Masks */
5815
5816
5817/* CM4_LPCG_LPI2C - Peripheral instance base addresses */
5818/** Peripheral CM4__LPCG_LPI2C base address */
5819#define CM4__LPCG_LPI2C_BASE (0x41630000u)
5820/** Peripheral CM4__LPCG_LPI2C base pointer */
5821#define CM4__LPCG_LPI2C ((CM4_LPCG_LPI2C_Type *)CM4__LPCG_LPI2C_BASE)
5822/** Array initializer of CM4_LPCG_LPI2C peripheral base addresses */
5823#define CM4_LPCG_LPI2C_BASE_ADDRS { CM4__LPCG_LPI2C_BASE }
5824/** Array initializer of CM4_LPCG_LPI2C peripheral base pointers */
5825#define CM4_LPCG_LPI2C_BASE_PTRS { CM4__LPCG_LPI2C }
5826
5827/*!
5828 * @}
5829 */ /* end of group CM4_LPCG_LPI2C_Peripheral_Access_Layer */
5830
5831
5832/* ----------------------------------------------------------------------------
5833 -- CM4_LPCG_LPIT Peripheral Access Layer
5834 ---------------------------------------------------------------------------- */
5835
5836/*!
5837 * @addtogroup CM4_LPCG_LPIT_Peripheral_Access_Layer CM4_LPCG_LPIT Peripheral Access Layer
5838 * @{
5839 */
5840
5841/** CM4_LPCG_LPIT - Register Layout Typedef */
5842typedef struct {
5843 __IO uint32_t LPCG_LPIT_0; /**< na, offset: 0x0 */
5844} CM4_LPCG_LPIT_Type;
5845
5846/* ----------------------------------------------------------------------------
5847 -- CM4_LPCG_LPIT Register Masks
5848 ---------------------------------------------------------------------------- */
5849
5850/*!
5851 * @addtogroup CM4_LPCG_LPIT_Register_Masks CM4_LPCG_LPIT Register Masks
5852 * @{
5853 */
5854
5855/*! @name LPCG_LPIT_0 - na */
5856/*! @{ */
5857#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK (0x1U)
5858#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT (0U)
5859/*! lpit1_ipg_per_clk_HWEN - Hardware Enable
5860 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
5861 * 0b1..Enable HW automatic gating
5862 */
5863#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK)
5864#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK (0x2U)
5865#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT (1U)
5866/*! lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN - Software Enable
5867 * 0b0..Disable SW clock regardless of HWEN
5868 * 0b1..Enable SW clock gating
5869 */
5870#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK)
5871#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK (0x4U)
5872#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT (2U)
5873/*! LPCG_LPIT_0_reserved_2_2 - reserved
5874 */
5875#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK)
5876#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK (0x8U)
5877#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT (3U)
5878/*! lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP - show clock root status, 1 means clock stopped
5879 */
5880#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK)
5881#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK (0x10U)
5882#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT (4U)
5883/*! LPCG_LPIT_0_reserved_4_4 - reserved
5884 */
5885#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK)
5886#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK (0x20U)
5887#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT (5U)
5888/*! lpit1_ipg_clk_SWEN - Software Enable
5889 * 0b0..Disable SW clock regardless of HWEN
5890 * 0b1..Enable SW clock gating
5891 */
5892#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK)
5893#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK (0x40U)
5894#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT (6U)
5895/*! LPCG_LPIT_0_reserved_6_6 - reserved
5896 */
5897#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK)
5898#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK (0x80U)
5899#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT (7U)
5900/*! lpit1_ipg_clk_STOP - show clock root status, 1 means clock stopped
5901 */
5902#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK)
5903#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK (0xFFFFFF00U)
5904#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT (8U)
5905/*! LPCG_LPIT_0_reserved_8_31 - reserved
5906 */
5907#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK)
5908/*! @} */
5909
5910
5911/*!
5912 * @}
5913 */ /* end of group CM4_LPCG_LPIT_Register_Masks */
5914
5915
5916/* CM4_LPCG_LPIT - Peripheral instance base addresses */
5917/** Peripheral CM4__LPCG_LPIT base address */
5918#define CM4__LPCG_LPIT_BASE (0x41610000u)
5919/** Peripheral CM4__LPCG_LPIT base pointer */
5920#define CM4__LPCG_LPIT ((CM4_LPCG_LPIT_Type *)CM4__LPCG_LPIT_BASE)
5921/** Array initializer of CM4_LPCG_LPIT peripheral base addresses */
5922#define CM4_LPCG_LPIT_BASE_ADDRS { CM4__LPCG_LPIT_BASE }
5923/** Array initializer of CM4_LPCG_LPIT peripheral base pointers */
5924#define CM4_LPCG_LPIT_BASE_PTRS { CM4__LPCG_LPIT }
5925
5926/*!
5927 * @}
5928 */ /* end of group CM4_LPCG_LPIT_Peripheral_Access_Layer */
5929
5930
5931/* ----------------------------------------------------------------------------
5932 -- CM4_LPCG_LPUART Peripheral Access Layer
5933 ---------------------------------------------------------------------------- */
5934
5935/*!
5936 * @addtogroup CM4_LPCG_LPUART_Peripheral_Access_Layer CM4_LPCG_LPUART Peripheral Access Layer
5937 * @{
5938 */
5939
5940/** CM4_LPCG_LPUART - Register Layout Typedef */
5941typedef struct {
5942 __IO uint32_t LPCG_LPUART_0; /**< na, offset: 0x0 */
5943} CM4_LPCG_LPUART_Type;
5944
5945/* ----------------------------------------------------------------------------
5946 -- CM4_LPCG_LPUART Register Masks
5947 ---------------------------------------------------------------------------- */
5948
5949/*!
5950 * @addtogroup CM4_LPCG_LPUART_Register_Masks CM4_LPCG_LPUART Register Masks
5951 * @{
5952 */
5953
5954/*! @name LPCG_LPUART_0 - na */
5955/*! @{ */
5956#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK (0x1U)
5957#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT (0U)
5958/*! lpuart1_lpuart_baud_gated_clk_HWEN - Hardware Enable
5959 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
5960 * 0b1..Enable HW automatic gating
5961 */
5962#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK)
5963#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK (0x2U)
5964#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT (1U)
5965/*! lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN - Software Enable
5966 * 0b0..Disable SW clock regardless of HWEN
5967 * 0b1..Enable SW clock gating
5968 */
5969#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK)
5970#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK (0x4U)
5971#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT (2U)
5972/*! LPCG_LPUART_0_reserved_2_2 - reserved
5973 */
5974#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK)
5975#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK (0x8U)
5976#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT (3U)
5977/*! lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP - show clock root status, 1 means clock stopped
5978 */
5979#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK)
5980#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK (0x10U)
5981#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT (4U)
5982/*! LPCG_LPUART_0_reserved_4_4 - reserved
5983 */
5984#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK)
5985#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK (0x20U)
5986#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT (5U)
5987/*! lpuart1_ipg_clk_SWEN - Software Enable
5988 * 0b0..Disable SW clock regardless of HWEN
5989 * 0b1..Enable SW clock gating
5990 */
5991#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK)
5992#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK (0x40U)
5993#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT (6U)
5994/*! LPCG_LPUART_0_reserved_6_6 - reserved
5995 */
5996#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK)
5997#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK (0x80U)
5998#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT (7U)
5999/*! lpuart1_ipg_clk_STOP - show clock root status, 1 means clock stopped
6000 */
6001#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK)
6002#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK (0xFFFFFF00U)
6003#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT (8U)
6004/*! LPCG_LPUART_0_reserved_8_31 - reserved
6005 */
6006#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK)
6007/*! @} */
6008
6009
6010/*!
6011 * @}
6012 */ /* end of group CM4_LPCG_LPUART_Register_Masks */
6013
6014
6015/* CM4_LPCG_LPUART - Peripheral instance base addresses */
6016/** Peripheral CM4__LPCG_LPUART base address */
6017#define CM4__LPCG_LPUART_BASE (0x41620000u)
6018/** Peripheral CM4__LPCG_LPUART base pointer */
6019#define CM4__LPCG_LPUART ((CM4_LPCG_LPUART_Type *)CM4__LPCG_LPUART_BASE)
6020/** Array initializer of CM4_LPCG_LPUART peripheral base addresses */
6021#define CM4_LPCG_LPUART_BASE_ADDRS { CM4__LPCG_LPUART_BASE }
6022/** Array initializer of CM4_LPCG_LPUART peripheral base pointers */
6023#define CM4_LPCG_LPUART_BASE_PTRS { CM4__LPCG_LPUART }
6024
6025/*!
6026 * @}
6027 */ /* end of group CM4_LPCG_LPUART_Peripheral_Access_Layer */
6028
6029
6030/* ----------------------------------------------------------------------------
6031 -- CM4_LPCG_MMCAU_HCLK Peripheral Access Layer
6032 ---------------------------------------------------------------------------- */
6033
6034/*!
6035 * @addtogroup CM4_LPCG_MMCAU_HCLK_Peripheral_Access_Layer CM4_LPCG_MMCAU_HCLK Peripheral Access Layer
6036 * @{
6037 */
6038
6039/** CM4_LPCG_MMCAU_HCLK - Register Layout Typedef */
6040typedef struct {
6041 __IO uint32_t LPCG_MMCAU_HCLK_0; /**< na, offset: 0x0 */
6042} CM4_LPCG_MMCAU_HCLK_Type;
6043
6044/* ----------------------------------------------------------------------------
6045 -- CM4_LPCG_MMCAU_HCLK Register Masks
6046 ---------------------------------------------------------------------------- */
6047
6048/*!
6049 * @addtogroup CM4_LPCG_MMCAU_HCLK_Register_Masks CM4_LPCG_MMCAU_HCLK Register Masks
6050 * @{
6051 */
6052
6053/*! @name LPCG_MMCAU_HCLK_0 - na */
6054/*! @{ */
6055#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK (0x1U)
6056#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT (0U)
6057/*! LPCG_MMCAU_HCLK_0_reserved_0_0 - reserved
6058 */
6059#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK)
6060#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK (0x2U)
6061#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT (1U)
6062/*! cm4_mmcau_hclk_SWEN - Software Enable
6063 * 0b0..Disable SW clock regardless of HWEN
6064 * 0b1..Enable SW clock gating
6065 */
6066#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK)
6067#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK (0x4U)
6068#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT (2U)
6069/*! LPCG_MMCAU_HCLK_0_reserved_2_2 - reserved
6070 */
6071#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK)
6072#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK (0x8U)
6073#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT (3U)
6074/*! cm4_mmcau_hclk_STOP - show clock root status, 1 means clock stopped
6075 */
6076#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK)
6077#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U)
6078#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT (4U)
6079/*! LPCG_MMCAU_HCLK_0_reserved_4_31 - reserved
6080 */
6081#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK)
6082/*! @} */
6083
6084
6085/*!
6086 * @}
6087 */ /* end of group CM4_LPCG_MMCAU_HCLK_Register_Masks */
6088
6089
6090/* CM4_LPCG_MMCAU_HCLK - Peripheral instance base addresses */
6091/** Peripheral CM4__LPCG_MMCAU_HCLK base address */
6092#define CM4__LPCG_MMCAU_HCLK_BASE (0x415F0000u)
6093/** Peripheral CM4__LPCG_MMCAU_HCLK base pointer */
6094#define CM4__LPCG_MMCAU_HCLK ((CM4_LPCG_MMCAU_HCLK_Type *)CM4__LPCG_MMCAU_HCLK_BASE)
6095/** Array initializer of CM4_LPCG_MMCAU_HCLK peripheral base addresses */
6096#define CM4_LPCG_MMCAU_HCLK_BASE_ADDRS { CM4__LPCG_MMCAU_HCLK_BASE }
6097/** Array initializer of CM4_LPCG_MMCAU_HCLK peripheral base pointers */
6098#define CM4_LPCG_MMCAU_HCLK_BASE_PTRS { CM4__LPCG_MMCAU_HCLK }
6099
6100/*!
6101 * @}
6102 */ /* end of group CM4_LPCG_MMCAU_HCLK_Peripheral_Access_Layer */
6103
6104
6105/* ----------------------------------------------------------------------------
6106 -- CM4_LPCG_TCMC_HCLK Peripheral Access Layer
6107 ---------------------------------------------------------------------------- */
6108
6109/*!
6110 * @addtogroup CM4_LPCG_TCMC_HCLK_Peripheral_Access_Layer CM4_LPCG_TCMC_HCLK Peripheral Access Layer
6111 * @{
6112 */
6113
6114/** CM4_LPCG_TCMC_HCLK - Register Layout Typedef */
6115typedef struct {
6116 __IO uint32_t LPCG_TCMC_HCLK_0; /**< na, offset: 0x0 */
6117} CM4_LPCG_TCMC_HCLK_Type;
6118
6119/* ----------------------------------------------------------------------------
6120 -- CM4_LPCG_TCMC_HCLK Register Masks
6121 ---------------------------------------------------------------------------- */
6122
6123/*!
6124 * @addtogroup CM4_LPCG_TCMC_HCLK_Register_Masks CM4_LPCG_TCMC_HCLK Register Masks
6125 * @{
6126 */
6127
6128/*! @name LPCG_TCMC_HCLK_0 - na */
6129/*! @{ */
6130#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK (0x1U)
6131#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT (0U)
6132/*! cm4_tcmc_hclk_HWEN - Hardware Enable
6133 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6134 * 0b1..Enable HW automatic gating
6135 */
6136#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK)
6137#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK (0x2U)
6138#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT (1U)
6139/*! cm4_tcmc_hclk_SWEN - Software Enable
6140 * 0b0..Disable SW clock regardless of HWEN
6141 * 0b1..Enable SW clock gating
6142 */
6143#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK)
6144#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK (0x4U)
6145#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT (2U)
6146/*! LPCG_TCMC_HCLK_0_reserved_2_2 - reserved
6147 */
6148#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK)
6149#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK (0x8U)
6150#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT (3U)
6151/*! cm4_tcmc_hclk_STOP - show clock root status, 1 means clock stopped
6152 */
6153#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK)
6154#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U)
6155#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT (4U)
6156/*! LPCG_TCMC_HCLK_0_reserved_4_31 - reserved
6157 */
6158#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK)
6159/*! @} */
6160
6161
6162/*!
6163 * @}
6164 */ /* end of group CM4_LPCG_TCMC_HCLK_Register_Masks */
6165
6166
6167/* CM4_LPCG_TCMC_HCLK - Peripheral instance base addresses */
6168/** Peripheral CM4__LPCG_TCMC_HCLK base address */
6169#define CM4__LPCG_TCMC_HCLK_BASE (0x415E0000u)
6170/** Peripheral CM4__LPCG_TCMC_HCLK base pointer */
6171#define CM4__LPCG_TCMC_HCLK ((CM4_LPCG_TCMC_HCLK_Type *)CM4__LPCG_TCMC_HCLK_BASE)
6172/** Array initializer of CM4_LPCG_TCMC_HCLK peripheral base addresses */
6173#define CM4_LPCG_TCMC_HCLK_BASE_ADDRS { CM4__LPCG_TCMC_HCLK_BASE }
6174/** Array initializer of CM4_LPCG_TCMC_HCLK peripheral base pointers */
6175#define CM4_LPCG_TCMC_HCLK_BASE_PTRS { CM4__LPCG_TCMC_HCLK }
6176
6177/*!
6178 * @}
6179 */ /* end of group CM4_LPCG_TCMC_HCLK_Peripheral_Access_Layer */
6180
6181
6182/* ----------------------------------------------------------------------------
6183 -- CM4_LPCG_TPM Peripheral Access Layer
6184 ---------------------------------------------------------------------------- */
6185
6186/*!
6187 * @addtogroup CM4_LPCG_TPM_Peripheral_Access_Layer CM4_LPCG_TPM Peripheral Access Layer
6188 * @{
6189 */
6190
6191/** CM4_LPCG_TPM - Register Layout Typedef */
6192typedef struct {
6193 __IO uint32_t LPCG_TPM_0; /**< na, offset: 0x0 */
6194} CM4_LPCG_TPM_Type;
6195
6196/* ----------------------------------------------------------------------------
6197 -- CM4_LPCG_TPM Register Masks
6198 ---------------------------------------------------------------------------- */
6199
6200/*!
6201 * @addtogroup CM4_LPCG_TPM_Register_Masks CM4_LPCG_TPM Register Masks
6202 * @{
6203 */
6204
6205/*! @name LPCG_TPM_0 - na */
6206/*! @{ */
6207#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK (0x1U)
6208#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT (0U)
6209/*! LPCG_TPM_0_reserved_0_0 - reserved
6210 */
6211#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK)
6212#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK (0x2U)
6213#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT (1U)
6214/*! tpm1_lptpm_clk_SWEN - Software Enable
6215 * 0b0..Disable SW clock regardless of HWEN
6216 * 0b1..Enable SW clock gating
6217 */
6218#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK)
6219#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK (0x4U)
6220#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT (2U)
6221/*! LPCG_TPM_0_reserved_2_2 - reserved
6222 */
6223#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK)
6224#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK (0x8U)
6225#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT (3U)
6226/*! tpm1_lptpm_clk_STOP - show clock root status, 1 means clock stopped
6227 */
6228#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK)
6229#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK (0x10U)
6230#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT (4U)
6231/*! LPCG_TPM_0_reserved_4_4 - reserved
6232 */
6233#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK)
6234#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK (0x20U)
6235#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT (5U)
6236/*! tpm1_ipg_clk_SWEN - Software Enable
6237 * 0b0..Disable SW clock regardless of HWEN
6238 * 0b1..Enable SW clock gating
6239 */
6240#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK)
6241#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK (0x40U)
6242#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT (6U)
6243/*! LPCG_TPM_0_reserved_6_6 - reserved
6244 */
6245#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK)
6246#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK (0x80U)
6247#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT (7U)
6248/*! tpm1_ipg_clk_STOP - show clock root status, 1 means clock stopped
6249 */
6250#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK)
6251#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK (0xFFFFFF00U)
6252#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT (8U)
6253/*! LPCG_TPM_0_reserved_8_31 - reserved
6254 */
6255#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK)
6256/*! @} */
6257
6258
6259/*!
6260 * @}
6261 */ /* end of group CM4_LPCG_TPM_Register_Masks */
6262
6263
6264/* CM4_LPCG_TPM - Peripheral instance base addresses */
6265/** Peripheral CM4__LPCG_TPM base address */
6266#define CM4__LPCG_TPM_BASE (0x41600000u)
6267/** Peripheral CM4__LPCG_TPM base pointer */
6268#define CM4__LPCG_TPM ((CM4_LPCG_TPM_Type *)CM4__LPCG_TPM_BASE)
6269/** Array initializer of CM4_LPCG_TPM peripheral base addresses */
6270#define CM4_LPCG_TPM_BASE_ADDRS { CM4__LPCG_TPM_BASE }
6271/** Array initializer of CM4_LPCG_TPM peripheral base pointers */
6272#define CM4_LPCG_TPM_BASE_PTRS { CM4__LPCG_TPM }
6273
6274/*!
6275 * @}
6276 */ /* end of group CM4_LPCG_TPM_Peripheral_Access_Layer */
6277
6278
6279/* ----------------------------------------------------------------------------
6280 -- CONNECTIVITY_LPCG_EDMA Peripheral Access Layer
6281 ---------------------------------------------------------------------------- */
6282
6283/*!
6284 * @addtogroup CONNECTIVITY_LPCG_EDMA_Peripheral_Access_Layer CONNECTIVITY_LPCG_EDMA Peripheral Access Layer
6285 * @{
6286 */
6287
6288/** CONNECTIVITY_LPCG_EDMA - Register Layout Typedef */
6289typedef struct {
6290 __IO uint32_t LPCG_LPCG_EDMA_0; /**< na, offset: 0x0 */
6291} CONNECTIVITY_LPCG_EDMA_Type;
6292
6293/* ----------------------------------------------------------------------------
6294 -- CONNECTIVITY_LPCG_EDMA Register Masks
6295 ---------------------------------------------------------------------------- */
6296
6297/*!
6298 * @addtogroup CONNECTIVITY_LPCG_EDMA_Register_Masks CONNECTIVITY_LPCG_EDMA Register Masks
6299 * @{
6300 */
6301
6302/*! @name LPCG_LPCG_EDMA_0 - na */
6303/*! @{ */
6304#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_MASK (0x1U)
6305#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_SHIFT (0U)
6306/*! edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN - Hardware Enable
6307 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6308 * 0b1..Enable HW automatic gating
6309 */
6310#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_MASK)
6311#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_MASK (0x2U)
6312#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_SHIFT (1U)
6313/*! edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN - Software Enable
6314 * 0b0..Disable SW clock regardless of HWEN
6315 * 0b1..Enable SW clock gating
6316 */
6317#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_MASK)
6318#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_MASK (0x4U)
6319#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_SHIFT (2U)
6320/*! LPCG_lpcg_edma_0_reserved_2_2 - reserved
6321 */
6322#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_MASK)
6323#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_MASK (0x8U)
6324#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_SHIFT (3U)
6325/*! edma_hclk_STOP_AND_edma_mem_dma_clk_STOP - show clock root status, 1 means clock stopped
6326 */
6327#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_MASK)
6328#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_MASK (0x1FFF0U)
6329#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_SHIFT (4U)
6330/*! LPCG_lpcg_edma_0_reserved_4_16 - reserved
6331 */
6332#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_MASK)
6333#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_MASK (0x20000U)
6334#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_SHIFT (17U)
6335/*! edma_ipg_clk_SWEN - Software Enable
6336 * 0b0..Disable SW clock regardless of HWEN
6337 * 0b1..Enable SW clock gating
6338 */
6339#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_MASK)
6340#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_MASK (0x40000U)
6341#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_SHIFT (18U)
6342/*! LPCG_lpcg_edma_0_reserved_18_18 - reserved
6343 */
6344#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_MASK)
6345#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_MASK (0x80000U)
6346#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_SHIFT (19U)
6347/*! edma_ipg_clk_STOP - show clock root status, 1 means clock stopped
6348 */
6349#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_MASK)
6350#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_MASK (0xFFF00000U)
6351#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_SHIFT (20U)
6352/*! LPCG_lpcg_edma_0_reserved_20_31 - reserved
6353 */
6354#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_MASK)
6355/*! @} */
6356
6357
6358/*!
6359 * @}
6360 */ /* end of group CONNECTIVITY_LPCG_EDMA_Register_Masks */
6361
6362
6363/* CONNECTIVITY_LPCG_EDMA - Peripheral instance base addresses */
6364/** Peripheral CONNECTIVITY__LPCG_EDMA base address */
6365#define CONNECTIVITY__LPCG_EDMA_BASE (0x5B2A0000u)
6366/** Peripheral CONNECTIVITY__LPCG_EDMA base pointer */
6367#define CONNECTIVITY__LPCG_EDMA ((CONNECTIVITY_LPCG_EDMA_Type *)CONNECTIVITY__LPCG_EDMA_BASE)
6368/** Array initializer of CONNECTIVITY_LPCG_EDMA peripheral base addresses */
6369#define CONNECTIVITY_LPCG_EDMA_BASE_ADDRS { CONNECTIVITY__LPCG_EDMA_BASE }
6370/** Array initializer of CONNECTIVITY_LPCG_EDMA peripheral base pointers */
6371#define CONNECTIVITY_LPCG_EDMA_BASE_PTRS { CONNECTIVITY__LPCG_EDMA }
6372
6373/*!
6374 * @}
6375 */ /* end of group CONNECTIVITY_LPCG_EDMA_Peripheral_Access_Layer */
6376
6377
6378/* ----------------------------------------------------------------------------
6379 -- CONNECTIVITY_LPCG_ENET0 Peripheral Access Layer
6380 ---------------------------------------------------------------------------- */
6381
6382/*!
6383 * @addtogroup CONNECTIVITY_LPCG_ENET0_Peripheral_Access_Layer CONNECTIVITY_LPCG_ENET0 Peripheral Access Layer
6384 * @{
6385 */
6386
6387/** CONNECTIVITY_LPCG_ENET0 - Register Layout Typedef */
6388typedef struct {
6389 __IO uint32_t LPCG_LPCG_ENET1_0; /**< na, offset: 0x0 */
6390 __IO uint32_t LPCG_LPCG_ENET1_4; /**< na, offset: 0x4 */
6391} CONNECTIVITY_LPCG_ENET0_Type;
6392
6393/* ----------------------------------------------------------------------------
6394 -- CONNECTIVITY_LPCG_ENET0 Register Masks
6395 ---------------------------------------------------------------------------- */
6396
6397/*!
6398 * @addtogroup CONNECTIVITY_LPCG_ENET0_Register_Masks CONNECTIVITY_LPCG_ENET0 Register Masks
6399 * @{
6400 */
6401
6402/*! @name LPCG_LPCG_ENET1_0 - na */
6403/*! @{ */
6404#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_MASK (0x1U)
6405#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_SHIFT (0U)
6406/*! enet1_ipg_clk_time_HWEN - Hardware Enable
6407 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6408 * 0b1..Enable HW automatic gating
6409 */
6410#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_MASK)
6411#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_MASK (0x2U)
6412#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_SHIFT (1U)
6413/*! enet1_ipg_clk_time_SWEN - Software Enable
6414 * 0b0..Disable SW clock regardless of HWEN
6415 * 0b1..Enable SW clock gating
6416 */
6417#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_MASK)
6418#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_MASK (0x4U)
6419#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_SHIFT (2U)
6420/*! LPCG_lpcg_enet1_0_reserved_2_2 - reserved
6421 */
6422#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_MASK)
6423#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_MASK (0x8U)
6424#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_SHIFT (3U)
6425/*! enet1_ipg_clk_time_STOP - show clock root status, 1 means clock stopped
6426 */
6427#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_MASK)
6428#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_MASK (0x10U)
6429#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_SHIFT (4U)
6430/*! LPCG_lpcg_enet1_0_reserved_4_4 - reserved
6431 */
6432#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_MASK)
6433#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_MASK (0x20U)
6434#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_SHIFT (5U)
6435/*! enet1_2x_txclk_SWEN - Software Enable
6436 * 0b0..Disable SW clock regardless of HWEN
6437 * 0b1..Enable SW clock gating
6438 */
6439#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_MASK)
6440#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_MASK (0x40U)
6441#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_SHIFT (6U)
6442/*! LPCG_lpcg_enet1_0_reserved_6_6 - reserved
6443 */
6444#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_MASK)
6445#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_MASK (0x80U)
6446#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_SHIFT (7U)
6447/*! enet1_2x_txclk_STOP - show clock root status, 1 means clock stopped
6448 */
6449#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_MASK)
6450#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_MASK (0x100U)
6451#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_SHIFT (8U)
6452/*! LPCG_lpcg_enet1_0_reserved_8_8 - reserved
6453 */
6454#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_MASK)
6455#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_MASK (0x200U)
6456#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_SHIFT (9U)
6457/*! enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN - Software Enable
6458 * 0b0..Disable SW clock regardless of HWEN
6459 * 0b1..Enable SW clock gating
6460 */
6461#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_MASK)
6462#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_MASK (0x400U)
6463#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_SHIFT (10U)
6464/*! LPCG_lpcg_enet1_0_reserved_10_10 - reserved
6465 */
6466#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_MASK)
6467#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_MASK (0x800U)
6468#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_SHIFT (11U)
6469/*! enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP - show clock root status, 1 means clock stopped
6470 */
6471#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_MASK)
6472#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_MASK (0x1000U)
6473#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_SHIFT (12U)
6474/*! LPCG_lpcg_enet1_0_reserved_12_12 - reserved
6475 */
6476#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_MASK)
6477#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_MASK (0x2000U)
6478#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_SHIFT (13U)
6479/*! enet1_clkdiv_clk_in_SWEN - Software Enable
6480 * 0b0..Disable SW clock regardless of HWEN
6481 * 0b1..Enable SW clock gating
6482 */
6483#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_MASK)
6484#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_MASK (0x4000U)
6485#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_SHIFT (14U)
6486/*! LPCG_lpcg_enet1_0_reserved_14_14 - reserved
6487 */
6488#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_MASK)
6489#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_MASK (0x8000U)
6490#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_SHIFT (15U)
6491/*! enet1_clkdiv_clk_in_STOP - show clock root status, 1 means clock stopped
6492 */
6493#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_MASK)
6494#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_MASK (0x10000U)
6495#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_SHIFT (16U)
6496/*! enet1_ipg_clk_mac0_HWEN - Hardware Enable
6497 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6498 * 0b1..Enable HW automatic gating
6499 */
6500#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_MASK)
6501#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_MASK (0x20000U)
6502#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_SHIFT (17U)
6503/*! enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN - Software Enable
6504 * 0b0..Disable SW clock regardless of HWEN
6505 * 0b1..Enable SW clock gating
6506 */
6507#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_MASK)
6508#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_MASK (0x40000U)
6509#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_SHIFT (18U)
6510/*! LPCG_lpcg_enet1_0_reserved_18_18 - reserved
6511 */
6512#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_MASK)
6513#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_MASK (0x80000U)
6514#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_SHIFT (19U)
6515/*! enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP - show clock root status, 1 means clock stopped
6516 */
6517#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_MASK)
6518#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_MASK (0x100000U)
6519#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_SHIFT (20U)
6520/*! enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN - Hardware Enable
6521 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6522 * 0b1..Enable HW automatic gating
6523 */
6524#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_MASK)
6525#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_MASK (0x200000U)
6526#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_SHIFT (21U)
6527/*! enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN - Software Enable
6528 * 0b0..Disable SW clock regardless of HWEN
6529 * 0b1..Enable SW clock gating
6530 */
6531#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_MASK)
6532#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_MASK (0x400000U)
6533#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_SHIFT (22U)
6534/*! LPCG_lpcg_enet1_0_reserved_22_22 - reserved
6535 */
6536#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_MASK)
6537#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_MASK (0x800000U)
6538#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_SHIFT (23U)
6539/*! enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
6540 */
6541#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_MASK)
6542#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_MASK (0xFF000000U)
6543#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_SHIFT (24U)
6544/*! LPCG_lpcg_enet1_0_reserved_24_31 - reserved
6545 */
6546#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_MASK)
6547/*! @} */
6548
6549/*! @name LPCG_LPCG_ENET1_4 - na */
6550/*! @{ */
6551#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_MASK (0x1U)
6552#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_SHIFT (0U)
6553/*! LPCG_lpcg_enet1_4_reserved_0_0 - reserved
6554 */
6555#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_MASK)
6556#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_MASK (0x2U)
6557#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_SHIFT (1U)
6558/*! enet1_mac0_rxclk_SWEN - Software Enable
6559 * 0b0..Disable SW clock regardless of HWEN
6560 * 0b1..Enable SW clock gating
6561 */
6562#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_MASK)
6563#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_MASK (0x4U)
6564#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_SHIFT (2U)
6565/*! LPCG_lpcg_enet1_4_reserved_2_2 - reserved
6566 */
6567#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_MASK)
6568#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_MASK (0x8U)
6569#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_SHIFT (3U)
6570/*! enet1_mac0_rxclk_STOP - show clock root status, 1 means clock stopped
6571 */
6572#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_MASK)
6573#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_MASK (0xFFFFFFF0U)
6574#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_SHIFT (4U)
6575/*! LPCG_lpcg_enet1_4_reserved_4_31 - reserved
6576 */
6577#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_MASK)
6578/*! @} */
6579
6580
6581/*!
6582 * @}
6583 */ /* end of group CONNECTIVITY_LPCG_ENET0_Register_Masks */
6584
6585
6586/* CONNECTIVITY_LPCG_ENET0 - Peripheral instance base addresses */
6587/** Peripheral CONNECTIVITY__LPCG_ENET0 base address */
6588#define CONNECTIVITY__LPCG_ENET0_BASE (0x5B230000u)
6589/** Peripheral CONNECTIVITY__LPCG_ENET0 base pointer */
6590#define CONNECTIVITY__LPCG_ENET0 ((CONNECTIVITY_LPCG_ENET0_Type *)CONNECTIVITY__LPCG_ENET0_BASE)
6591/** Array initializer of CONNECTIVITY_LPCG_ENET0 peripheral base addresses */
6592#define CONNECTIVITY_LPCG_ENET0_BASE_ADDRS { CONNECTIVITY__LPCG_ENET0_BASE }
6593/** Array initializer of CONNECTIVITY_LPCG_ENET0 peripheral base pointers */
6594#define CONNECTIVITY_LPCG_ENET0_BASE_PTRS { CONNECTIVITY__LPCG_ENET0 }
6595
6596/*!
6597 * @}
6598 */ /* end of group CONNECTIVITY_LPCG_ENET0_Peripheral_Access_Layer */
6599
6600
6601/* ----------------------------------------------------------------------------
6602 -- CONNECTIVITY_LPCG_ENET1 Peripheral Access Layer
6603 ---------------------------------------------------------------------------- */
6604
6605/*!
6606 * @addtogroup CONNECTIVITY_LPCG_ENET1_Peripheral_Access_Layer CONNECTIVITY_LPCG_ENET1 Peripheral Access Layer
6607 * @{
6608 */
6609
6610/** CONNECTIVITY_LPCG_ENET1 - Register Layout Typedef */
6611typedef struct {
6612 __IO uint32_t LPCG_LPCG_ENET2_0; /**< na, offset: 0x0 */
6613 __IO uint32_t LPCG_LPCG_ENET2_4; /**< na, offset: 0x4 */
6614} CONNECTIVITY_LPCG_ENET1_Type;
6615
6616/* ----------------------------------------------------------------------------
6617 -- CONNECTIVITY_LPCG_ENET1 Register Masks
6618 ---------------------------------------------------------------------------- */
6619
6620/*!
6621 * @addtogroup CONNECTIVITY_LPCG_ENET1_Register_Masks CONNECTIVITY_LPCG_ENET1 Register Masks
6622 * @{
6623 */
6624
6625/*! @name LPCG_LPCG_ENET2_0 - na */
6626/*! @{ */
6627#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_MASK (0x1U)
6628#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_SHIFT (0U)
6629/*! enet2_ipg_clk_time_HWEN - Hardware Enable
6630 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6631 * 0b1..Enable HW automatic gating
6632 */
6633#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_MASK)
6634#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_MASK (0x2U)
6635#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_SHIFT (1U)
6636/*! enet2_ipg_clk_time_SWEN - Software Enable
6637 * 0b0..Disable SW clock regardless of HWEN
6638 * 0b1..Enable SW clock gating
6639 */
6640#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_MASK)
6641#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_MASK (0x4U)
6642#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_SHIFT (2U)
6643/*! LPCG_lpcg_enet2_0_reserved_2_2 - reserved
6644 */
6645#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_MASK)
6646#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_MASK (0x8U)
6647#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_SHIFT (3U)
6648/*! enet2_ipg_clk_time_STOP - show clock root status, 1 means clock stopped
6649 */
6650#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_MASK)
6651#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_MASK (0x10U)
6652#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_SHIFT (4U)
6653/*! LPCG_lpcg_enet2_0_reserved_4_4 - reserved
6654 */
6655#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_MASK)
6656#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_MASK (0x20U)
6657#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_SHIFT (5U)
6658/*! enet2_2x_txclk_SWEN - Software Enable
6659 * 0b0..Disable SW clock regardless of HWEN
6660 * 0b1..Enable SW clock gating
6661 */
6662#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_MASK)
6663#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_MASK (0x40U)
6664#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_SHIFT (6U)
6665/*! LPCG_lpcg_enet2_0_reserved_6_6 - reserved
6666 */
6667#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_MASK)
6668#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_MASK (0x80U)
6669#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_SHIFT (7U)
6670/*! enet2_2x_txclk_STOP - show clock root status, 1 means clock stopped
6671 */
6672#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_MASK)
6673#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_MASK (0x100U)
6674#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_SHIFT (8U)
6675/*! LPCG_lpcg_enet2_0_reserved_8_8 - reserved
6676 */
6677#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_MASK)
6678#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_MASK (0x200U)
6679#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_SHIFT (9U)
6680/*! enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN - Software Enable
6681 * 0b0..Disable SW clock regardless of HWEN
6682 * 0b1..Enable SW clock gating
6683 */
6684#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_MASK)
6685#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_MASK (0x400U)
6686#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_SHIFT (10U)
6687/*! LPCG_lpcg_enet2_0_reserved_10_10 - reserved
6688 */
6689#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_MASK)
6690#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_MASK (0x800U)
6691#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_SHIFT (11U)
6692/*! enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP - show clock root status, 1 means clock stopped
6693 */
6694#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_MASK)
6695#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_MASK (0x1000U)
6696#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_SHIFT (12U)
6697/*! LPCG_lpcg_enet2_0_reserved_12_12 - reserved
6698 */
6699#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_MASK)
6700#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_MASK (0x2000U)
6701#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_SHIFT (13U)
6702/*! enet2_clkdiv_clk_in_SWEN - Software Enable
6703 * 0b0..Disable SW clock regardless of HWEN
6704 * 0b1..Enable SW clock gating
6705 */
6706#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_MASK)
6707#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_MASK (0x4000U)
6708#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_SHIFT (14U)
6709/*! LPCG_lpcg_enet2_0_reserved_14_14 - reserved
6710 */
6711#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_MASK)
6712#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_MASK (0x8000U)
6713#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_SHIFT (15U)
6714/*! enet2_clkdiv_clk_in_STOP - show clock root status, 1 means clock stopped
6715 */
6716#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_MASK)
6717#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_MASK (0x10000U)
6718#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_SHIFT (16U)
6719/*! enet2_ipg_clk_mac0_HWEN - Hardware Enable
6720 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6721 * 0b1..Enable HW automatic gating
6722 */
6723#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_MASK)
6724#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_MASK (0x20000U)
6725#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_SHIFT (17U)
6726/*! enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN - Software Enable
6727 * 0b0..Disable SW clock regardless of HWEN
6728 * 0b1..Enable SW clock gating
6729 */
6730#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_MASK)
6731#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_MASK (0x40000U)
6732#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_SHIFT (18U)
6733/*! LPCG_lpcg_enet2_0_reserved_18_18 - reserved
6734 */
6735#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_MASK)
6736#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_MASK (0x80000U)
6737#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_SHIFT (19U)
6738/*! enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP - show clock root status, 1 means clock stopped
6739 */
6740#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_MASK)
6741#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_MASK (0x100000U)
6742#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_SHIFT (20U)
6743/*! enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN - Hardware Enable
6744 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6745 * 0b1..Enable HW automatic gating
6746 */
6747#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_MASK)
6748#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_MASK (0x200000U)
6749#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_SHIFT (21U)
6750/*! enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN - Software Enable
6751 * 0b0..Disable SW clock regardless of HWEN
6752 * 0b1..Enable SW clock gating
6753 */
6754#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_MASK)
6755#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_MASK (0x400000U)
6756#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_SHIFT (22U)
6757/*! LPCG_lpcg_enet2_0_reserved_22_22 - reserved
6758 */
6759#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_MASK)
6760#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_MASK (0x800000U)
6761#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_SHIFT (23U)
6762/*! enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
6763 */
6764#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_MASK)
6765#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_MASK (0xFF000000U)
6766#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_SHIFT (24U)
6767/*! LPCG_lpcg_enet2_0_reserved_24_31 - reserved
6768 */
6769#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_MASK)
6770/*! @} */
6771
6772/*! @name LPCG_LPCG_ENET2_4 - na */
6773/*! @{ */
6774#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_MASK (0x1U)
6775#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_SHIFT (0U)
6776/*! LPCG_lpcg_enet2_4_reserved_0_0 - reserved
6777 */
6778#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_MASK)
6779#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_MASK (0x2U)
6780#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_SHIFT (1U)
6781/*! enet2_mac0_rxclk_SWEN - Software Enable
6782 * 0b0..Disable SW clock regardless of HWEN
6783 * 0b1..Enable SW clock gating
6784 */
6785#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_MASK)
6786#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_MASK (0x4U)
6787#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_SHIFT (2U)
6788/*! LPCG_lpcg_enet2_4_reserved_2_2 - reserved
6789 */
6790#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_MASK)
6791#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_MASK (0x8U)
6792#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_SHIFT (3U)
6793/*! enet2_mac0_rxclk_STOP - show clock root status, 1 means clock stopped
6794 */
6795#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_MASK)
6796#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_MASK (0xFFFFFFF0U)
6797#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_SHIFT (4U)
6798/*! LPCG_lpcg_enet2_4_reserved_4_31 - reserved
6799 */
6800#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_MASK)
6801/*! @} */
6802
6803
6804/*!
6805 * @}
6806 */ /* end of group CONNECTIVITY_LPCG_ENET1_Register_Masks */
6807
6808
6809/* CONNECTIVITY_LPCG_ENET1 - Peripheral instance base addresses */
6810/** Peripheral CONNECTIVITY__LPCG_ENET1 base address */
6811#define CONNECTIVITY__LPCG_ENET1_BASE (0x5B240000u)
6812/** Peripheral CONNECTIVITY__LPCG_ENET1 base pointer */
6813#define CONNECTIVITY__LPCG_ENET1 ((CONNECTIVITY_LPCG_ENET1_Type *)CONNECTIVITY__LPCG_ENET1_BASE)
6814/** Array initializer of CONNECTIVITY_LPCG_ENET1 peripheral base addresses */
6815#define CONNECTIVITY_LPCG_ENET1_BASE_ADDRS { CONNECTIVITY__LPCG_ENET1_BASE }
6816/** Array initializer of CONNECTIVITY_LPCG_ENET1 peripheral base pointers */
6817#define CONNECTIVITY_LPCG_ENET1_BASE_PTRS { CONNECTIVITY__LPCG_ENET1 }
6818
6819/*!
6820 * @}
6821 */ /* end of group CONNECTIVITY_LPCG_ENET1_Peripheral_Access_Layer */
6822
6823
6824/* ----------------------------------------------------------------------------
6825 -- CONNECTIVITY_LPCG_MLB Peripheral Access Layer
6826 ---------------------------------------------------------------------------- */
6827
6828/*!
6829 * @addtogroup CONNECTIVITY_LPCG_MLB_Peripheral_Access_Layer CONNECTIVITY_LPCG_MLB Peripheral Access Layer
6830 * @{
6831 */
6832
6833/** CONNECTIVITY_LPCG_MLB - Register Layout Typedef */
6834typedef struct {
6835 __IO uint32_t LPCG_LPCG_MLB_0; /**< na, offset: 0x0 */
6836} CONNECTIVITY_LPCG_MLB_Type;
6837
6838/* ----------------------------------------------------------------------------
6839 -- CONNECTIVITY_LPCG_MLB Register Masks
6840 ---------------------------------------------------------------------------- */
6841
6842/*!
6843 * @addtogroup CONNECTIVITY_LPCG_MLB_Register_Masks CONNECTIVITY_LPCG_MLB Register Masks
6844 * @{
6845 */
6846
6847/*! @name LPCG_LPCG_MLB_0 - na */
6848/*! @{ */
6849#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_MASK (0x1U)
6850#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_SHIFT (0U)
6851/*! LPCG_lpcg_mlb_0_reserved_0_0 - reserved
6852 */
6853#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_MASK)
6854#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_MASK (0x2U)
6855#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_SHIFT (1U)
6856/*! mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN - Software Enable
6857 * 0b0..Disable SW clock regardless of HWEN
6858 * 0b1..Enable SW clock gating
6859 */
6860#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_MASK)
6861#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_MASK (0x4U)
6862#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_SHIFT (2U)
6863/*! LPCG_lpcg_mlb_0_reserved_2_2 - reserved
6864 */
6865#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_MASK)
6866#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_MASK (0x8U)
6867#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_SHIFT (3U)
6868/*! mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP - show clock root status, 1 means clock stopped
6869 */
6870#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_MASK)
6871#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_MASK (0xFFF0U)
6872#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_SHIFT (4U)
6873/*! LPCG_lpcg_mlb_0_reserved_4_15 - reserved
6874 */
6875#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_MASK)
6876#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_MASK (0x10000U)
6877#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_SHIFT (16U)
6878/*! mlb_ipg_clk_s_HWEN - Hardware Enable
6879 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6880 * 0b1..Enable HW automatic gating
6881 */
6882#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_MASK)
6883#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_MASK (0x20000U)
6884#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_SHIFT (17U)
6885/*! mlb_ipg_clk_s_SWEN - Software Enable
6886 * 0b0..Disable SW clock regardless of HWEN
6887 * 0b1..Enable SW clock gating
6888 */
6889#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_MASK)
6890#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_MASK (0x40000U)
6891#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_SHIFT (18U)
6892/*! LPCG_lpcg_mlb_0_reserved_18_18 - reserved
6893 */
6894#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_MASK)
6895#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_MASK (0x80000U)
6896#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_SHIFT (19U)
6897/*! mlb_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
6898 */
6899#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_MASK)
6900#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_MASK (0x100000U)
6901#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_SHIFT (20U)
6902/*! LPCG_lpcg_mlb_0_reserved_20_20 - reserved
6903 */
6904#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_MASK)
6905#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_MASK (0x200000U)
6906#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_SHIFT (21U)
6907/*! mlb_hclk_SWEN - Software Enable
6908 * 0b0..Disable SW clock regardless of HWEN
6909 * 0b1..Enable SW clock gating
6910 */
6911#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_MASK)
6912#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_MASK (0x400000U)
6913#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_SHIFT (22U)
6914/*! LPCG_lpcg_mlb_0_reserved_22_22 - reserved
6915 */
6916#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_MASK)
6917#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_MASK (0x800000U)
6918#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_SHIFT (23U)
6919/*! mlb_hclk_STOP - show clock root status, 1 means clock stopped
6920 */
6921#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_MASK)
6922#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_MASK (0xFF000000U)
6923#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_SHIFT (24U)
6924/*! LPCG_lpcg_mlb_0_reserved_24_31 - reserved
6925 */
6926#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_MASK)
6927/*! @} */
6928
6929
6930/*!
6931 * @}
6932 */ /* end of group CONNECTIVITY_LPCG_MLB_Register_Masks */
6933
6934
6935/* CONNECTIVITY_LPCG_MLB - Peripheral instance base addresses */
6936/** Peripheral CONNECTIVITY__LPCG_MLB base address */
6937#define CONNECTIVITY__LPCG_MLB_BASE (0x5B260000u)
6938/** Peripheral CONNECTIVITY__LPCG_MLB base pointer */
6939#define CONNECTIVITY__LPCG_MLB ((CONNECTIVITY_LPCG_MLB_Type *)CONNECTIVITY__LPCG_MLB_BASE)
6940/** Array initializer of CONNECTIVITY_LPCG_MLB peripheral base addresses */
6941#define CONNECTIVITY_LPCG_MLB_BASE_ADDRS { CONNECTIVITY__LPCG_MLB_BASE }
6942/** Array initializer of CONNECTIVITY_LPCG_MLB peripheral base pointers */
6943#define CONNECTIVITY_LPCG_MLB_BASE_PTRS { CONNECTIVITY__LPCG_MLB }
6944
6945/*!
6946 * @}
6947 */ /* end of group CONNECTIVITY_LPCG_MLB_Peripheral_Access_Layer */
6948
6949
6950/* ----------------------------------------------------------------------------
6951 -- CONNECTIVITY_LPCG_RAWNAND Peripheral Access Layer
6952 ---------------------------------------------------------------------------- */
6953
6954/*!
6955 * @addtogroup CONNECTIVITY_LPCG_RAWNAND_Peripheral_Access_Layer CONNECTIVITY_LPCG_RAWNAND Peripheral Access Layer
6956 * @{
6957 */
6958
6959/** CONNECTIVITY_LPCG_RAWNAND - Register Layout Typedef */
6960typedef struct {
6961 __IO uint32_t LPCG_LPCG_RAWNAND_0; /**< na, offset: 0x0 */
6962 __IO uint32_t LPCG_LPCG_RAWNAND_4; /**< na, offset: 0x4 */
6963} CONNECTIVITY_LPCG_RAWNAND_Type;
6964
6965/* ----------------------------------------------------------------------------
6966 -- CONNECTIVITY_LPCG_RAWNAND Register Masks
6967 ---------------------------------------------------------------------------- */
6968
6969/*!
6970 * @addtogroup CONNECTIVITY_LPCG_RAWNAND_Register_Masks CONNECTIVITY_LPCG_RAWNAND Register Masks
6971 * @{
6972 */
6973
6974/*! @name LPCG_LPCG_RAWNAND_0 - na */
6975/*! @{ */
6976#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_MASK (0x1U)
6977#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_SHIFT (0U)
6978/*! LPCG_lpcg_rawnand_0_reserved_0_0 - reserved
6979 */
6980#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_MASK)
6981#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_MASK (0x2U)
6982#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_SHIFT (1U)
6983/*! rawnand_u_gpmi_bch_input_bch_clk_SWEN - Software Enable
6984 * 0b0..Disable SW clock regardless of HWEN
6985 * 0b1..Enable SW clock gating
6986 */
6987#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_MASK)
6988#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_MASK (0x4U)
6989#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_SHIFT (2U)
6990/*! LPCG_lpcg_rawnand_0_reserved_2_2 - reserved
6991 */
6992#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_MASK)
6993#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_MASK (0x8U)
6994#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_SHIFT (3U)
6995/*! rawnand_u_gpmi_bch_input_bch_clk_STOP - show clock root status, 1 means clock stopped
6996 */
6997#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_MASK)
6998#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_MASK (0x10U)
6999#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_SHIFT (4U)
7000/*! LPCG_lpcg_rawnand_0_reserved_4_4 - reserved
7001 */
7002#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_MASK)
7003#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_MASK (0x20U)
7004#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_SHIFT (5U)
7005/*! rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN - Software Enable
7006 * 0b0..Disable SW clock regardless of HWEN
7007 * 0b1..Enable SW clock gating
7008 */
7009#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_MASK)
7010#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_MASK (0x40U)
7011#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_SHIFT (6U)
7012/*! LPCG_lpcg_rawnand_0_reserved_6_6 - reserved
7013 */
7014#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_MASK)
7015#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_MASK (0x80U)
7016#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_SHIFT (7U)
7017/*! rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP - show clock root status, 1 means clock stopped
7018 */
7019#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_MASK)
7020#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_MASK (0x1FF00U)
7021#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_SHIFT (8U)
7022/*! LPCG_lpcg_rawnand_0_reserved_8_16 - reserved
7023 */
7024#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_MASK)
7025#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_MASK (0x20000U)
7026#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_SHIFT (17U)
7027/*! rawnand_u_gpmi_input_apb_clk_SWEN - Software Enable
7028 * 0b0..Disable SW clock regardless of HWEN
7029 * 0b1..Enable SW clock gating
7030 */
7031#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_MASK)
7032#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_MASK (0x40000U)
7033#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_SHIFT (18U)
7034/*! LPCG_lpcg_rawnand_0_reserved_18_18 - reserved
7035 */
7036#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_MASK)
7037#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_MASK (0x80000U)
7038#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_SHIFT (19U)
7039/*! rawnand_u_gpmi_input_apb_clk_STOP - show clock root status, 1 means clock stopped
7040 */
7041#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_MASK)
7042#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_MASK (0x100000U)
7043#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_SHIFT (20U)
7044/*! LPCG_lpcg_rawnand_0_reserved_20_20 - reserved
7045 */
7046#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_MASK)
7047#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_MASK (0x200000U)
7048#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_SHIFT (21U)
7049/*! rawnand_u_bch_input_apb_clk_SWEN - Software Enable
7050 * 0b0..Disable SW clock regardless of HWEN
7051 * 0b1..Enable SW clock gating
7052 */
7053#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_MASK)
7054#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_MASK (0x400000U)
7055#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_SHIFT (22U)
7056/*! LPCG_lpcg_rawnand_0_reserved_22_22 - reserved
7057 */
7058#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_MASK)
7059#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_MASK (0x800000U)
7060#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_SHIFT (23U)
7061/*! rawnand_u_bch_input_apb_clk_STOP - show clock root status, 1 means clock stopped
7062 */
7063#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_MASK)
7064#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_MASK (0xFF000000U)
7065#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_SHIFT (24U)
7066/*! LPCG_lpcg_rawnand_0_reserved_24_31 - reserved
7067 */
7068#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_MASK)
7069/*! @} */
7070
7071/*! @name LPCG_LPCG_RAWNAND_4 - na */
7072/*! @{ */
7073#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_MASK (0x1FFFFU)
7074#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_SHIFT (0U)
7075/*! LPCG_lpcg_rawnand_4_reserved_0_16 - reserved
7076 */
7077#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_MASK)
7078#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_MASK (0x20000U)
7079#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_SHIFT (17U)
7080/*! apbhdma_hclk_SWEN - Software Enable
7081 * 0b0..Disable SW clock regardless of HWEN
7082 * 0b1..Enable SW clock gating
7083 */
7084#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_MASK)
7085#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_MASK (0x40000U)
7086#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_SHIFT (18U)
7087/*! LPCG_lpcg_rawnand_4_reserved_18_18 - reserved
7088 */
7089#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_MASK)
7090#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_MASK (0x80000U)
7091#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_SHIFT (19U)
7092/*! apbhdma_hclk_STOP - show clock root status, 1 means clock stopped
7093 */
7094#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_MASK)
7095#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_MASK (0xFFF00000U)
7096#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_SHIFT (20U)
7097/*! LPCG_lpcg_rawnand_4_reserved_20_31 - reserved
7098 */
7099#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_MASK)
7100/*! @} */
7101
7102
7103/*!
7104 * @}
7105 */ /* end of group CONNECTIVITY_LPCG_RAWNAND_Register_Masks */
7106
7107
7108/* CONNECTIVITY_LPCG_RAWNAND - Peripheral instance base addresses */
7109/** Peripheral CONNECTIVITY__LPCG_RAWNAND base address */
7110#define CONNECTIVITY__LPCG_RAWNAND_BASE (0x5B290000u)
7111/** Peripheral CONNECTIVITY__LPCG_RAWNAND base pointer */
7112#define CONNECTIVITY__LPCG_RAWNAND ((CONNECTIVITY_LPCG_RAWNAND_Type *)CONNECTIVITY__LPCG_RAWNAND_BASE)
7113/** Array initializer of CONNECTIVITY_LPCG_RAWNAND peripheral base addresses */
7114#define CONNECTIVITY_LPCG_RAWNAND_BASE_ADDRS { CONNECTIVITY__LPCG_RAWNAND_BASE }
7115/** Array initializer of CONNECTIVITY_LPCG_RAWNAND peripheral base pointers */
7116#define CONNECTIVITY_LPCG_RAWNAND_BASE_PTRS { CONNECTIVITY__LPCG_RAWNAND }
7117
7118/*!
7119 * @}
7120 */ /* end of group CONNECTIVITY_LPCG_RAWNAND_Peripheral_Access_Layer */
7121
7122
7123/* ----------------------------------------------------------------------------
7124 -- CONNECTIVITY_LPCG_USB2 Peripheral Access Layer
7125 ---------------------------------------------------------------------------- */
7126
7127/*!
7128 * @addtogroup CONNECTIVITY_LPCG_USB2_Peripheral_Access_Layer CONNECTIVITY_LPCG_USB2 Peripheral Access Layer
7129 * @{
7130 */
7131
7132/** CONNECTIVITY_LPCG_USB2 - Register Layout Typedef */
7133typedef struct {
7134 __IO uint32_t LPCG_LPCG_USB2_0; /**< na, offset: 0x0 */
7135} CONNECTIVITY_LPCG_USB2_Type;
7136
7137/* ----------------------------------------------------------------------------
7138 -- CONNECTIVITY_LPCG_USB2 Register Masks
7139 ---------------------------------------------------------------------------- */
7140
7141/*!
7142 * @addtogroup CONNECTIVITY_LPCG_USB2_Register_Masks CONNECTIVITY_LPCG_USB2 Register Masks
7143 * @{
7144 */
7145
7146/*! @name LPCG_LPCG_USB2_0 - na */
7147/*! @{ */
7148#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_MASK (0x1FFFFU)
7149#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_SHIFT (0U)
7150/*! LPCG_lpcg_usb2_0_reserved_0_16 - reserved
7151 */
7152#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_MASK)
7153#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_MASK (0x20000U)
7154#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_SHIFT (17U)
7155/*! usboh_ipg_clk_s_SWEN - Software Enable
7156 * 0b0..Disable SW clock regardless of HWEN
7157 * 0b1..Enable SW clock gating
7158 */
7159#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_MASK)
7160#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_MASK (0x40000U)
7161#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_SHIFT (18U)
7162/*! LPCG_lpcg_usb2_0_reserved_18_18 - reserved
7163 */
7164#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_MASK)
7165#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_MASK (0x80000U)
7166#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_SHIFT (19U)
7167/*! usboh_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
7168 */
7169#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_MASK)
7170#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_MASK (0x100000U)
7171#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_SHIFT (20U)
7172/*! LPCG_lpcg_usb2_0_reserved_20_20 - reserved
7173 */
7174#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_MASK)
7175#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_MASK (0x200000U)
7176#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_SHIFT (21U)
7177/*! usboh_ipg_clk_s_pl301_SWEN - Software Enable
7178 * 0b0..Disable SW clock regardless of HWEN
7179 * 0b1..Enable SW clock gating
7180 */
7181#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_MASK)
7182#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_MASK (0x400000U)
7183#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_SHIFT (22U)
7184/*! LPCG_lpcg_usb2_0_reserved_22_22 - reserved
7185 */
7186#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_MASK)
7187#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_MASK (0x800000U)
7188#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_SHIFT (23U)
7189/*! usboh_ipg_clk_s_pl301_STOP - show clock root status, 1 means clock stopped
7190 */
7191#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_MASK)
7192#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_MASK (0x1000000U)
7193#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_SHIFT (24U)
7194/*! LPCG_lpcg_usb2_0_reserved_24_24 - reserved
7195 */
7196#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_MASK)
7197#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_MASK (0x2000000U)
7198#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_SHIFT (25U)
7199/*! usboh_ipg_ahb_clk_SWEN - Software Enable
7200 * 0b0..Disable SW clock regardless of HWEN
7201 * 0b1..Enable SW clock gating
7202 */
7203#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_MASK)
7204#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_MASK (0x4000000U)
7205#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_SHIFT (26U)
7206/*! LPCG_lpcg_usb2_0_reserved_26_26 - reserved
7207 */
7208#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_MASK)
7209#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_MASK (0x8000000U)
7210#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_SHIFT (27U)
7211/*! usboh_ipg_ahb_clk_STOP - show clock root status, 1 means clock stopped
7212 */
7213#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_MASK)
7214#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_MASK (0x10000000U)
7215#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_SHIFT (28U)
7216/*! da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN - Hardware Enable
7217 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7218 * 0b1..Enable HW automatic gating
7219 */
7220#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_MASK)
7221#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_MASK (0x20000000U)
7222#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_SHIFT (29U)
7223/*! da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN - Software Enable
7224 * 0b0..Disable SW clock regardless of HWEN
7225 * 0b1..Enable SW clock gating
7226 */
7227#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_MASK)
7228#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_MASK (0x40000000U)
7229#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_SHIFT (30U)
7230/*! LPCG_lpcg_usb2_0_reserved_30_30 - reserved
7231 */
7232#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_MASK)
7233#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_MASK (0x80000000U)
7234#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_SHIFT (31U)
7235/*! da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
7236 */
7237#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_MASK)
7238/*! @} */
7239
7240
7241/*!
7242 * @}
7243 */ /* end of group CONNECTIVITY_LPCG_USB2_Register_Masks */
7244
7245
7246/* CONNECTIVITY_LPCG_USB2 - Peripheral instance base addresses */
7247/** Peripheral CONNECTIVITY__LPCG_USB2 base address */
7248#define CONNECTIVITY__LPCG_USB2_BASE (0x5B270000u)
7249/** Peripheral CONNECTIVITY__LPCG_USB2 base pointer */
7250#define CONNECTIVITY__LPCG_USB2 ((CONNECTIVITY_LPCG_USB2_Type *)CONNECTIVITY__LPCG_USB2_BASE)
7251/** Array initializer of CONNECTIVITY_LPCG_USB2 peripheral base addresses */
7252#define CONNECTIVITY_LPCG_USB2_BASE_ADDRS { CONNECTIVITY__LPCG_USB2_BASE }
7253/** Array initializer of CONNECTIVITY_LPCG_USB2 peripheral base pointers */
7254#define CONNECTIVITY_LPCG_USB2_BASE_PTRS { CONNECTIVITY__LPCG_USB2 }
7255
7256/*!
7257 * @}
7258 */ /* end of group CONNECTIVITY_LPCG_USB2_Peripheral_Access_Layer */
7259
7260
7261/* ----------------------------------------------------------------------------
7262 -- CONNECTIVITY_LPCG_USB3 Peripheral Access Layer
7263 ---------------------------------------------------------------------------- */
7264
7265/*!
7266 * @addtogroup CONNECTIVITY_LPCG_USB3_Peripheral_Access_Layer CONNECTIVITY_LPCG_USB3 Peripheral Access Layer
7267 * @{
7268 */
7269
7270/** CONNECTIVITY_LPCG_USB3 - Register Layout Typedef */
7271typedef struct {
7272 __IO uint32_t LPCG_LPCG_USB3_0; /**< na, offset: 0x0 */
7273} CONNECTIVITY_LPCG_USB3_Type;
7274
7275/* ----------------------------------------------------------------------------
7276 -- CONNECTIVITY_LPCG_USB3 Register Masks
7277 ---------------------------------------------------------------------------- */
7278
7279/*!
7280 * @addtogroup CONNECTIVITY_LPCG_USB3_Register_Masks CONNECTIVITY_LPCG_USB3 Register Masks
7281 * @{
7282 */
7283
7284/*! @name LPCG_LPCG_USB3_0 - na */
7285/*! @{ */
7286#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_MASK (0x1U)
7287#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_SHIFT (0U)
7288/*! LPCG_lpcg_usb3_0_reserved_0_0 - reserved
7289 */
7290#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_MASK)
7291#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_MASK (0x2U)
7292#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_SHIFT (1U)
7293/*! da_ip_usb3_wrap_app_clk_125_predft_SWEN - Software Enable
7294 * 0b0..Disable SW clock regardless of HWEN
7295 * 0b1..Enable SW clock gating
7296 */
7297#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_MASK)
7298#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_MASK (0x4U)
7299#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_SHIFT (2U)
7300/*! LPCG_lpcg_usb3_0_reserved_2_2 - reserved
7301 */
7302#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_MASK)
7303#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_MASK (0x8U)
7304#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_SHIFT (3U)
7305/*! da_ip_usb3_wrap_app_clk_125_predft_STOP - show clock root status, 1 means clock stopped
7306 */
7307#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_MASK)
7308#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_MASK (0x10U)
7309#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_SHIFT (4U)
7310/*! LPCG_lpcg_usb3_0_reserved_4_4 - reserved
7311 */
7312#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_MASK)
7313#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_MASK (0x20U)
7314#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_SHIFT (5U)
7315/*! da_ip_usb3_wrap_lpm_clk_predft_SWEN - Software Enable
7316 * 0b0..Disable SW clock regardless of HWEN
7317 * 0b1..Enable SW clock gating
7318 */
7319#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_MASK)
7320#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_MASK (0x40U)
7321#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_SHIFT (6U)
7322/*! LPCG_lpcg_usb3_0_reserved_6_6 - reserved
7323 */
7324#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_MASK)
7325#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_MASK (0x80U)
7326#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_SHIFT (7U)
7327/*! da_ip_usb3_wrap_lpm_clk_predft_STOP - show clock root status, 1 means clock stopped
7328 */
7329#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_MASK)
7330#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_MASK (0x1FF00U)
7331#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_SHIFT (8U)
7332/*! LPCG_lpcg_usb3_0_reserved_8_16 - reserved
7333 */
7334#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_MASK)
7335#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_MASK (0x20000U)
7336#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_SHIFT (17U)
7337/*! da_ip_usb3_wrap_ipg_clk_SWEN - Software Enable
7338 * 0b0..Disable SW clock regardless of HWEN
7339 * 0b1..Enable SW clock gating
7340 */
7341#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_MASK)
7342#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_MASK (0x40000U)
7343#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_SHIFT (18U)
7344/*! LPCG_lpcg_usb3_0_reserved_18_18 - reserved
7345 */
7346#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_MASK)
7347#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_MASK (0x80000U)
7348#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_SHIFT (19U)
7349/*! da_ip_usb3_wrap_ipg_clk_STOP - show clock root status, 1 means clock stopped
7350 */
7351#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_MASK)
7352#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_MASK (0x100000U)
7353#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_SHIFT (20U)
7354/*! LPCG_lpcg_usb3_0_reserved_20_20 - reserved
7355 */
7356#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_MASK)
7357#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_MASK (0x200000U)
7358#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_SHIFT (21U)
7359/*! da_ip_usb3_wrap_usb3_core_pclk_SWEN - Software Enable
7360 * 0b0..Disable SW clock regardless of HWEN
7361 * 0b1..Enable SW clock gating
7362 */
7363#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_MASK)
7364#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_MASK (0x400000U)
7365#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_SHIFT (22U)
7366/*! LPCG_lpcg_usb3_0_reserved_22_22 - reserved
7367 */
7368#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_MASK)
7369#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_MASK (0x800000U)
7370#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_SHIFT (23U)
7371/*! da_ip_usb3_wrap_usb3_core_pclk_STOP - show clock root status, 1 means clock stopped
7372 */
7373#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_MASK)
7374#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_MASK (0x1000000U)
7375#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_SHIFT (24U)
7376/*! LPCG_lpcg_usb3_0_reserved_24_24 - reserved
7377 */
7378#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_MASK)
7379#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_MASK (0x2000000U)
7380#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_SHIFT (25U)
7381/*! da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN - Software Enable
7382 * 0b0..Disable SW clock regardless of HWEN
7383 * 0b1..Enable SW clock gating
7384 */
7385#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_MASK)
7386#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_MASK (0x4000000U)
7387#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_SHIFT (26U)
7388/*! LPCG_lpcg_usb3_0_reserved_26_26 - reserved
7389 */
7390#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_MASK)
7391#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_MASK (0x8000000U)
7392#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_SHIFT (27U)
7393/*! da_ip_usb3_wrap_usb3_ssphy_pclk_STOP - show clock root status, 1 means clock stopped
7394 */
7395#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_MASK)
7396#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_MASK (0x10000000U)
7397#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_SHIFT (28U)
7398/*! LPCG_lpcg_usb3_0_reserved_28_28 - reserved
7399 */
7400#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_MASK)
7401#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_MASK (0x20000000U)
7402#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_SHIFT (29U)
7403/*! da_ip_usb3_wrap_usb3_aclk_SWEN - Software Enable
7404 * 0b0..Disable SW clock regardless of HWEN
7405 * 0b1..Enable SW clock gating
7406 */
7407#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_MASK)
7408#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_MASK (0x40000000U)
7409#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_SHIFT (30U)
7410/*! LPCG_lpcg_usb3_0_reserved_30_30 - reserved
7411 */
7412#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_MASK)
7413#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_MASK (0x80000000U)
7414#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_SHIFT (31U)
7415/*! da_ip_usb3_wrap_usb3_aclk_STOP - show clock root status, 1 means clock stopped
7416 */
7417#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_MASK)
7418/*! @} */
7419
7420
7421/*!
7422 * @}
7423 */ /* end of group CONNECTIVITY_LPCG_USB3_Register_Masks */
7424
7425
7426/* CONNECTIVITY_LPCG_USB3 - Peripheral instance base addresses */
7427/** Peripheral CONNECTIVITY__LPCG_USB3 base address */
7428#define CONNECTIVITY__LPCG_USB3_BASE (0x5B280000u)
7429/** Peripheral CONNECTIVITY__LPCG_USB3 base pointer */
7430#define CONNECTIVITY__LPCG_USB3 ((CONNECTIVITY_LPCG_USB3_Type *)CONNECTIVITY__LPCG_USB3_BASE)
7431/** Array initializer of CONNECTIVITY_LPCG_USB3 peripheral base addresses */
7432#define CONNECTIVITY_LPCG_USB3_BASE_ADDRS { CONNECTIVITY__LPCG_USB3_BASE }
7433/** Array initializer of CONNECTIVITY_LPCG_USB3 peripheral base pointers */
7434#define CONNECTIVITY_LPCG_USB3_BASE_PTRS { CONNECTIVITY__LPCG_USB3 }
7435
7436/*!
7437 * @}
7438 */ /* end of group CONNECTIVITY_LPCG_USB3_Peripheral_Access_Layer */
7439
7440
7441/* ----------------------------------------------------------------------------
7442 -- CONNECTIVITY_LPCG_USDHC0 Peripheral Access Layer
7443 ---------------------------------------------------------------------------- */
7444
7445/*!
7446 * @addtogroup CONNECTIVITY_LPCG_USDHC0_Peripheral_Access_Layer CONNECTIVITY_LPCG_USDHC0 Peripheral Access Layer
7447 * @{
7448 */
7449
7450/** CONNECTIVITY_LPCG_USDHC0 - Register Layout Typedef */
7451typedef struct {
7452 __IO uint32_t LPCG_LPCG_USDHC1_0; /**< na, offset: 0x0 */
7453} CONNECTIVITY_LPCG_USDHC0_Type;
7454
7455/* ----------------------------------------------------------------------------
7456 -- CONNECTIVITY_LPCG_USDHC0 Register Masks
7457 ---------------------------------------------------------------------------- */
7458
7459/*!
7460 * @addtogroup CONNECTIVITY_LPCG_USDHC0_Register_Masks CONNECTIVITY_LPCG_USDHC0 Register Masks
7461 * @{
7462 */
7463
7464/*! @name LPCG_LPCG_USDHC1_0 - na */
7465/*! @{ */
7466#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_MASK (0x1U)
7467#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_SHIFT (0U)
7468/*! LPCG_lpcg_usdhc1_0_reserved_0_0 - reserved
7469 */
7470#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_MASK)
7471#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_MASK (0x2U)
7472#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_SHIFT (1U)
7473/*! usdhc1_ipg_clk_perclk_SWEN - Software Enable
7474 * 0b0..Disable SW clock regardless of HWEN
7475 * 0b1..Enable SW clock gating
7476 */
7477#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_MASK)
7478#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_MASK (0x4U)
7479#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_SHIFT (2U)
7480/*! LPCG_lpcg_usdhc1_0_reserved_2_2 - reserved
7481 */
7482#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_MASK)
7483#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_MASK (0x8U)
7484#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_SHIFT (3U)
7485/*! usdhc1_ipg_clk_perclk_STOP - show clock root status, 1 means clock stopped
7486 */
7487#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_MASK)
7488#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_MASK (0xFFF0U)
7489#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_SHIFT (4U)
7490/*! LPCG_lpcg_usdhc1_0_reserved_4_15 - reserved
7491 */
7492#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_MASK)
7493#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_MASK (0x10000U)
7494#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_SHIFT (16U)
7495/*! usdhc1_ipg_clk_s_HWEN - Hardware Enable
7496 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7497 * 0b1..Enable HW automatic gating
7498 */
7499#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_MASK)
7500#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_MASK (0x20000U)
7501#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_SHIFT (17U)
7502/*! usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN - Software Enable
7503 * 0b0..Disable SW clock regardless of HWEN
7504 * 0b1..Enable SW clock gating
7505 */
7506#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_MASK)
7507#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_MASK (0x40000U)
7508#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_SHIFT (18U)
7509/*! LPCG_lpcg_usdhc1_0_reserved_18_18 - reserved
7510 */
7511#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_MASK)
7512#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_MASK (0x80000U)
7513#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_SHIFT (19U)
7514/*! usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP - show clock root status, 1 means clock stopped
7515 */
7516#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_MASK)
7517#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_MASK (0x100000U)
7518#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_SHIFT (20U)
7519/*! LPCG_lpcg_usdhc1_0_reserved_20_20 - reserved
7520 */
7521#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_MASK)
7522#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_MASK (0x200000U)
7523#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_SHIFT (21U)
7524/*! usdhc1_hclk_SWEN - Software Enable
7525 * 0b0..Disable SW clock regardless of HWEN
7526 * 0b1..Enable SW clock gating
7527 */
7528#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_MASK)
7529#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_MASK (0x400000U)
7530#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_SHIFT (22U)
7531/*! LPCG_lpcg_usdhc1_0_reserved_22_22 - reserved
7532 */
7533#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_MASK)
7534#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_MASK (0x800000U)
7535#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_SHIFT (23U)
7536/*! usdhc1_hclk_STOP - show clock root status, 1 means clock stopped
7537 */
7538#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_MASK)
7539#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_MASK (0xFF000000U)
7540#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_SHIFT (24U)
7541/*! LPCG_lpcg_usdhc1_0_reserved_24_31 - reserved
7542 */
7543#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_MASK)
7544/*! @} */
7545
7546
7547/*!
7548 * @}
7549 */ /* end of group CONNECTIVITY_LPCG_USDHC0_Register_Masks */
7550
7551
7552/* CONNECTIVITY_LPCG_USDHC0 - Peripheral instance base addresses */
7553/** Peripheral CONNECTIVITY__LPCG_USDHC0 base address */
7554#define CONNECTIVITY__LPCG_USDHC0_BASE (0x5B200000u)
7555/** Peripheral CONNECTIVITY__LPCG_USDHC0 base pointer */
7556#define CONNECTIVITY__LPCG_USDHC0 ((CONNECTIVITY_LPCG_USDHC0_Type *)CONNECTIVITY__LPCG_USDHC0_BASE)
7557/** Array initializer of CONNECTIVITY_LPCG_USDHC0 peripheral base addresses */
7558#define CONNECTIVITY_LPCG_USDHC0_BASE_ADDRS { CONNECTIVITY__LPCG_USDHC0_BASE }
7559/** Array initializer of CONNECTIVITY_LPCG_USDHC0 peripheral base pointers */
7560#define CONNECTIVITY_LPCG_USDHC0_BASE_PTRS { CONNECTIVITY__LPCG_USDHC0 }
7561
7562/*!
7563 * @}
7564 */ /* end of group CONNECTIVITY_LPCG_USDHC0_Peripheral_Access_Layer */
7565
7566
7567/* ----------------------------------------------------------------------------
7568 -- CONNECTIVITY_LPCG_USDHC1 Peripheral Access Layer
7569 ---------------------------------------------------------------------------- */
7570
7571/*!
7572 * @addtogroup CONNECTIVITY_LPCG_USDHC1_Peripheral_Access_Layer CONNECTIVITY_LPCG_USDHC1 Peripheral Access Layer
7573 * @{
7574 */
7575
7576/** CONNECTIVITY_LPCG_USDHC1 - Register Layout Typedef */
7577typedef struct {
7578 __IO uint32_t LPCG_LPCG_USDHC2_0; /**< na, offset: 0x0 */
7579} CONNECTIVITY_LPCG_USDHC1_Type;
7580
7581/* ----------------------------------------------------------------------------
7582 -- CONNECTIVITY_LPCG_USDHC1 Register Masks
7583 ---------------------------------------------------------------------------- */
7584
7585/*!
7586 * @addtogroup CONNECTIVITY_LPCG_USDHC1_Register_Masks CONNECTIVITY_LPCG_USDHC1 Register Masks
7587 * @{
7588 */
7589
7590/*! @name LPCG_LPCG_USDHC2_0 - na */
7591/*! @{ */
7592#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_MASK (0x1U)
7593#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_SHIFT (0U)
7594/*! LPCG_lpcg_usdhc2_0_reserved_0_0 - reserved
7595 */
7596#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_MASK)
7597#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_MASK (0x2U)
7598#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_SHIFT (1U)
7599/*! usdhc2_ipg_clk_perclk_SWEN - Software Enable
7600 * 0b0..Disable SW clock regardless of HWEN
7601 * 0b1..Enable SW clock gating
7602 */
7603#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_MASK)
7604#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_MASK (0x4U)
7605#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_SHIFT (2U)
7606/*! LPCG_lpcg_usdhc2_0_reserved_2_2 - reserved
7607 */
7608#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_MASK)
7609#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_MASK (0x8U)
7610#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_SHIFT (3U)
7611/*! usdhc2_ipg_clk_perclk_STOP - show clock root status, 1 means clock stopped
7612 */
7613#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_MASK)
7614#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_MASK (0xFFF0U)
7615#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_SHIFT (4U)
7616/*! LPCG_lpcg_usdhc2_0_reserved_4_15 - reserved
7617 */
7618#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_MASK)
7619#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_MASK (0x10000U)
7620#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_SHIFT (16U)
7621/*! usdhc2_ipg_clk_s_HWEN - Hardware Enable
7622 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7623 * 0b1..Enable HW automatic gating
7624 */
7625#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_MASK)
7626#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_MASK (0x20000U)
7627#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_SHIFT (17U)
7628/*! usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN - Software Enable
7629 * 0b0..Disable SW clock regardless of HWEN
7630 * 0b1..Enable SW clock gating
7631 */
7632#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_MASK)
7633#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_MASK (0x40000U)
7634#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_SHIFT (18U)
7635/*! LPCG_lpcg_usdhc2_0_reserved_18_18 - reserved
7636 */
7637#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_MASK)
7638#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_MASK (0x80000U)
7639#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_SHIFT (19U)
7640/*! usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP - show clock root status, 1 means clock stopped
7641 */
7642#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_MASK)
7643#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_MASK (0x100000U)
7644#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_SHIFT (20U)
7645/*! LPCG_lpcg_usdhc2_0_reserved_20_20 - reserved
7646 */
7647#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_MASK)
7648#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_MASK (0x200000U)
7649#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_SHIFT (21U)
7650/*! usdhc2_hclk_SWEN - Software Enable
7651 * 0b0..Disable SW clock regardless of HWEN
7652 * 0b1..Enable SW clock gating
7653 */
7654#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_MASK)
7655#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_MASK (0x400000U)
7656#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_SHIFT (22U)
7657/*! LPCG_lpcg_usdhc2_0_reserved_22_22 - reserved
7658 */
7659#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_MASK)
7660#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_MASK (0x800000U)
7661#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_SHIFT (23U)
7662/*! usdhc2_hclk_STOP - show clock root status, 1 means clock stopped
7663 */
7664#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_MASK)
7665#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_MASK (0xFF000000U)
7666#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_SHIFT (24U)
7667/*! LPCG_lpcg_usdhc2_0_reserved_24_31 - reserved
7668 */
7669#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_MASK)
7670/*! @} */
7671
7672
7673/*!
7674 * @}
7675 */ /* end of group CONNECTIVITY_LPCG_USDHC1_Register_Masks */
7676
7677
7678/* CONNECTIVITY_LPCG_USDHC1 - Peripheral instance base addresses */
7679/** Peripheral CONNECTIVITY__LPCG_USDHC1 base address */
7680#define CONNECTIVITY__LPCG_USDHC1_BASE (0x5B210000u)
7681/** Peripheral CONNECTIVITY__LPCG_USDHC1 base pointer */
7682#define CONNECTIVITY__LPCG_USDHC1 ((CONNECTIVITY_LPCG_USDHC1_Type *)CONNECTIVITY__LPCG_USDHC1_BASE)
7683/** Array initializer of CONNECTIVITY_LPCG_USDHC1 peripheral base addresses */
7684#define CONNECTIVITY_LPCG_USDHC1_BASE_ADDRS { CONNECTIVITY__LPCG_USDHC1_BASE }
7685/** Array initializer of CONNECTIVITY_LPCG_USDHC1 peripheral base pointers */
7686#define CONNECTIVITY_LPCG_USDHC1_BASE_PTRS { CONNECTIVITY__LPCG_USDHC1 }
7687
7688/*!
7689 * @}
7690 */ /* end of group CONNECTIVITY_LPCG_USDHC1_Peripheral_Access_Layer */
7691
7692
7693/* ----------------------------------------------------------------------------
7694 -- DC_LPCG Peripheral Access Layer
7695 ---------------------------------------------------------------------------- */
7696
7697/*!
7698 * @addtogroup DC_LPCG_Peripheral_Access_Layer DC_LPCG Peripheral Access Layer
7699 * @{
7700 */
7701
7702/** DC_LPCG - Register Layout Typedef */
7703typedef struct {
7704 __IO uint32_t LPCG_DC_LPCG_0; /**< na, offset: 0x0 */
7705 __IO uint32_t LPCG_DC_LPCG_4; /**< na, offset: 0x4 */
7706 __IO uint32_t LPCG_DC_LPCG_8; /**< na, offset: 0x8 */
7707 uint8_t RESERVED_0[4];
7708 __IO uint32_t LPCG_DC_LPCG_16; /**< na, offset: 0x10 */
7709 __IO uint32_t LPCG_DC_LPCG_20; /**< na, offset: 0x14 */
7710 __IO uint32_t LPCG_DC_LPCG_24; /**< na, offset: 0x18 */
7711 __IO uint32_t LPCG_DC_LPCG_28; /**< na, offset: 0x1C */
7712 __IO uint32_t LPCG_DC_LPCG_32; /**< na, offset: 0x20 */
7713 __IO uint32_t LPCG_DC_LPCG_36; /**< na, offset: 0x24 */
7714 __IO uint32_t LPCG_DC_LPCG_40; /**< na, offset: 0x28 */
7715 __IO uint32_t LPCG_DC_LPCG_44; /**< na, offset: 0x2C */
7716 __IO uint32_t LPCG_DC_LPCG_48; /**< na, offset: 0x30 */
7717 __IO uint32_t LPCG_DC_LPCG_52; /**< na, offset: 0x34 */
7718 __IO uint32_t LPCG_DC_LPCG_56; /**< na, offset: 0x38 */
7719 __IO uint32_t LPCG_DC_LPCG_60; /**< na, offset: 0x3C */
7720 __IO uint32_t LPCG_DC_LPCG_64; /**< na, offset: 0x40 */
7721 __IO uint32_t LPCG_DC_LPCG_68; /**< na, offset: 0x44 */
7722 __IO uint32_t LPCG_DC_LPCG_72; /**< na, offset: 0x48 */
7723} DC_LPCG_Type;
7724
7725/* ----------------------------------------------------------------------------
7726 -- DC_LPCG Register Masks
7727 ---------------------------------------------------------------------------- */
7728
7729/*!
7730 * @addtogroup DC_LPCG_Register_Masks DC_LPCG Register Masks
7731 * @{
7732 */
7733
7734/*! @name LPCG_DC_LPCG_0 - na */
7735/*! @{ */
7736#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_MASK (0x1U)
7737#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_SHIFT (0U)
7738/*! LPCG_dc_lpcg_0_reserved_0_0 - reserved
7739 */
7740#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_MASK)
7741#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_MASK (0x2U)
7742#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_SHIFT (1U)
7743/*! dsp0_clk_SWEN - Software Enable
7744 * 0b0..Disable SW clock regardless of HWEN
7745 * 0b1..Enable SW clock gating
7746 */
7747#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_MASK)
7748#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_MASK (0x4U)
7749#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_SHIFT (2U)
7750/*! LPCG_dc_lpcg_0_reserved_2_2 - reserved
7751 */
7752#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_MASK)
7753#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_MASK (0x8U)
7754#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_SHIFT (3U)
7755/*! dsp0_clk_STOP - show clock root status, 1 means clock stopped
7756 */
7757#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_MASK)
7758#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_MASK (0x10U)
7759#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_SHIFT (4U)
7760/*! LPCG_dc_lpcg_0_reserved_4_4 - reserved
7761 */
7762#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_MASK)
7763#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_MASK (0x20U)
7764#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_SHIFT (5U)
7765/*! dsp1_clk_SWEN - Software Enable
7766 * 0b0..Disable SW clock regardless of HWEN
7767 * 0b1..Enable SW clock gating
7768 */
7769#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_MASK)
7770#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_MASK (0x40U)
7771#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_SHIFT (6U)
7772/*! LPCG_dc_lpcg_0_reserved_6_6 - reserved
7773 */
7774#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_MASK)
7775#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_MASK (0x80U)
7776#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_SHIFT (7U)
7777/*! dsp1_clk_STOP - show clock root status, 1 means clock stopped
7778 */
7779#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_MASK)
7780#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_MASK (0xFFFFFF00U)
7781#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_SHIFT (8U)
7782/*! LPCG_dc_lpcg_0_reserved_8_31 - reserved
7783 */
7784#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_MASK)
7785/*! @} */
7786
7787/*! @name LPCG_DC_LPCG_4 - na */
7788/*! @{ */
7789#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_MASK (0xFFFFU)
7790#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_SHIFT (0U)
7791/*! LPCG_dc_lpcg_4_reserved_0_15 - reserved
7792 */
7793#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_MASK)
7794#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_MASK (0x10000U)
7795#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_SHIFT (16U)
7796/*! lis_ipg_clk_HWEN - Hardware Enable
7797 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7798 * 0b1..Enable HW automatic gating
7799 */
7800#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_MASK)
7801#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_MASK (0x20000U)
7802#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_SHIFT (17U)
7803/*! lis_ipg_clk_SWEN - Software Enable
7804 * 0b0..Disable SW clock regardless of HWEN
7805 * 0b1..Enable SW clock gating
7806 */
7807#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_MASK)
7808#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_MASK (0x40000U)
7809#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_SHIFT (18U)
7810/*! LPCG_dc_lpcg_4_reserved_18_18 - reserved
7811 */
7812#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_MASK)
7813#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_MASK (0x80000U)
7814#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_SHIFT (19U)
7815/*! lis_ipg_clk_STOP - show clock root status, 1 means clock stopped
7816 */
7817#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_MASK)
7818#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_MASK (0xFFF00000U)
7819#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_SHIFT (20U)
7820/*! LPCG_dc_lpcg_4_reserved_20_31 - reserved
7821 */
7822#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_MASK)
7823/*! @} */
7824
7825/*! @name LPCG_DC_LPCG_8 - na */
7826/*! @{ */
7827#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_MASK (0xFFFFU)
7828#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_SHIFT (0U)
7829/*! LPCG_dc_lpcg_8_reserved_0_15 - reserved
7830 */
7831#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_MASK)
7832#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_MASK (0x10000U)
7833#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_SHIFT (16U)
7834/*! display_ctrl_link_mst0_msi_clk_HWEN - Hardware Enable
7835 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7836 * 0b1..Enable HW automatic gating
7837 */
7838#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_MASK)
7839#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_MASK (0x20000U)
7840#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_SHIFT (17U)
7841/*! display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN - Software Enable
7842 * 0b0..Disable SW clock regardless of HWEN
7843 * 0b1..Enable SW clock gating
7844 */
7845#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_MASK)
7846#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_MASK (0x40000U)
7847#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_SHIFT (18U)
7848/*! LPCG_dc_lpcg_8_reserved_18_18 - reserved
7849 */
7850#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_MASK)
7851#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_MASK (0x80000U)
7852#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_SHIFT (19U)
7853/*! display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP - show clock root status, 1 means clock stopped
7854 */
7855#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_MASK)
7856#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_MASK (0xFFF00000U)
7857#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_SHIFT (20U)
7858/*! LPCG_dc_lpcg_8_reserved_20_31 - reserved
7859 */
7860#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_MASK)
7861/*! @} */
7862
7863/*! @name LPCG_DC_LPCG_16 - na */
7864/*! @{ */
7865#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_MASK (0xFFFFU)
7866#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_SHIFT (0U)
7867/*! LPCG_dc_lpcg_16_reserved_0_15 - reserved
7868 */
7869#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_MASK)
7870#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_MASK (0x10000U)
7871#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_SHIFT (16U)
7872/*! pixel_combiner_apb_clk_HWEN - Hardware Enable
7873 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7874 * 0b1..Enable HW automatic gating
7875 */
7876#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_MASK)
7877#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_MASK (0x20000U)
7878#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_SHIFT (17U)
7879/*! pixel_combiner_apb_clk_SWEN - Software Enable
7880 * 0b0..Disable SW clock regardless of HWEN
7881 * 0b1..Enable SW clock gating
7882 */
7883#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_MASK)
7884#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_MASK (0x40000U)
7885#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_SHIFT (18U)
7886/*! LPCG_dc_lpcg_16_reserved_18_18 - reserved
7887 */
7888#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_MASK)
7889#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_MASK (0x80000U)
7890#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_SHIFT (19U)
7891/*! pixel_combiner_apb_clk_STOP - show clock root status, 1 means clock stopped
7892 */
7893#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_MASK)
7894#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_MASK (0xFFF00000U)
7895#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_SHIFT (20U)
7896/*! LPCG_dc_lpcg_16_reserved_20_31 - reserved
7897 */
7898#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_MASK)
7899/*! @} */
7900
7901/*! @name LPCG_DC_LPCG_20 - na */
7902/*! @{ */
7903#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_MASK (0xFFFFU)
7904#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_SHIFT (0U)
7905/*! LPCG_dc_lpcg_20_reserved_0_15 - reserved
7906 */
7907#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_MASK)
7908#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_MASK (0x10000U)
7909#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_SHIFT (16U)
7910/*! iris_mvpl_cfg_clk_HWEN - Hardware Enable
7911 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7912 * 0b1..Enable HW automatic gating
7913 */
7914#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_MASK)
7915#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_MASK (0x20000U)
7916#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_SHIFT (17U)
7917/*! iris_mvpl_cfg_clk_SWEN - Software Enable
7918 * 0b0..Disable SW clock regardless of HWEN
7919 * 0b1..Enable SW clock gating
7920 */
7921#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_MASK)
7922#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_MASK (0x40000U)
7923#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_SHIFT (18U)
7924/*! LPCG_dc_lpcg_20_reserved_18_18 - reserved
7925 */
7926#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_MASK)
7927#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_MASK (0x80000U)
7928#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_SHIFT (19U)
7929/*! iris_mvpl_cfg_clk_STOP - show clock root status, 1 means clock stopped
7930 */
7931#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_MASK)
7932#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_MASK (0x100000U)
7933#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_SHIFT (20U)
7934/*! LPCG_dc_lpcg_20_reserved_20_20 - reserved
7935 */
7936#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_MASK)
7937#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_MASK (0x200000U)
7938#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_SHIFT (21U)
7939/*! iris_mvpl_axi_clk_SWEN - Software Enable
7940 * 0b0..Disable SW clock regardless of HWEN
7941 * 0b1..Enable SW clock gating
7942 */
7943#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_MASK)
7944#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_MASK (0x400000U)
7945#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_SHIFT (22U)
7946/*! LPCG_dc_lpcg_20_reserved_22_22 - reserved
7947 */
7948#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_MASK)
7949#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_MASK (0x800000U)
7950#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_SHIFT (23U)
7951/*! iris_mvpl_axi_clk_STOP - show clock root status, 1 means clock stopped
7952 */
7953#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_MASK)
7954#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_MASK (0xFF000000U)
7955#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_SHIFT (24U)
7956/*! LPCG_dc_lpcg_20_reserved_24_31 - reserved
7957 */
7958#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_MASK)
7959/*! @} */
7960
7961/*! @name LPCG_DC_LPCG_24 - na */
7962/*! @{ */
7963#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_MASK (0xFFFFU)
7964#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_SHIFT (0U)
7965/*! LPCG_dc_lpcg_24_reserved_0_15 - reserved
7966 */
7967#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_MASK)
7968#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_MASK (0x10000U)
7969#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_SHIFT (16U)
7970/*! dpr0_dpr_apb_clkg_HWEN - Hardware Enable
7971 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7972 * 0b1..Enable HW automatic gating
7973 */
7974#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_MASK)
7975#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_MASK (0x20000U)
7976#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_SHIFT (17U)
7977/*! dpr0_dpr_apb_clkg_SWEN - Software Enable
7978 * 0b0..Disable SW clock regardless of HWEN
7979 * 0b1..Enable SW clock gating
7980 */
7981#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_MASK)
7982#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_MASK (0x40000U)
7983#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_SHIFT (18U)
7984/*! LPCG_dc_lpcg_24_reserved_18_18 - reserved
7985 */
7986#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_MASK)
7987#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_MASK (0x80000U)
7988#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_SHIFT (19U)
7989/*! dpr0_dpr_apb_clkg_STOP - show clock root status, 1 means clock stopped
7990 */
7991#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_MASK)
7992#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_MASK (0x100000U)
7993#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_SHIFT (20U)
7994/*! dpr0_dpr_b_clkg_HWEN - Hardware Enable
7995 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7996 * 0b1..Enable HW automatic gating
7997 */
7998#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_MASK)
7999#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_MASK (0x200000U)
8000#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_SHIFT (21U)
8001/*! dpr0_dpr_b_clkg_SWEN - Software Enable
8002 * 0b0..Disable SW clock regardless of HWEN
8003 * 0b1..Enable SW clock gating
8004 */
8005#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_MASK)
8006#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_MASK (0x400000U)
8007#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_SHIFT (22U)
8008/*! LPCG_dc_lpcg_24_reserved_22_22 - reserved
8009 */
8010#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_MASK)
8011#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_MASK (0x800000U)
8012#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_SHIFT (23U)
8013/*! dpr0_dpr_b_clkg_STOP - show clock root status, 1 means clock stopped
8014 */
8015#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_MASK)
8016#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_MASK (0xFF000000U)
8017#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_SHIFT (24U)
8018/*! LPCG_dc_lpcg_24_reserved_24_31 - reserved
8019 */
8020#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_MASK)
8021/*! @} */
8022
8023/*! @name LPCG_DC_LPCG_28 - na */
8024/*! @{ */
8025#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_MASK (0x1U)
8026#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_SHIFT (0U)
8027/*! LPCG_dc_lpcg_28_reserved_0_0 - reserved
8028 */
8029#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_MASK)
8030#define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_MASK (0x2U)
8031#define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_SHIFT (1U)
8032/*! rtram0_rtr_clk_g_SWEN - Software Enable
8033 * 0b0..Disable SW clock regardless of HWEN
8034 * 0b1..Enable SW clock gating
8035 */
8036#define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_MASK)
8037#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_MASK (0x4U)
8038#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_SHIFT (2U)
8039/*! LPCG_dc_lpcg_28_reserved_2_2 - reserved
8040 */
8041#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_MASK)
8042#define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_MASK (0x8U)
8043#define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_SHIFT (3U)
8044/*! rtram0_rtr_clk_g_STOP - show clock root status, 1 means clock stopped
8045 */
8046#define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_MASK)
8047#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_MASK (0xFFFFFFF0U)
8048#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_SHIFT (4U)
8049/*! LPCG_dc_lpcg_28_reserved_4_31 - reserved
8050 */
8051#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_MASK)
8052/*! @} */
8053
8054/*! @name LPCG_DC_LPCG_32 - na */
8055/*! @{ */
8056#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_MASK (0x1U)
8057#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_SHIFT (0U)
8058/*! LPCG_dc_lpcg_32_reserved_0_0 - reserved
8059 */
8060#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_MASK)
8061#define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_MASK (0x2U)
8062#define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_SHIFT (1U)
8063/*! prg0_rtram_clk_SWEN - Software Enable
8064 * 0b0..Disable SW clock regardless of HWEN
8065 * 0b1..Enable SW clock gating
8066 */
8067#define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_MASK)
8068#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_MASK (0x4U)
8069#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_SHIFT (2U)
8070/*! LPCG_dc_lpcg_32_reserved_2_2 - reserved
8071 */
8072#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_MASK)
8073#define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_MASK (0x8U)
8074#define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_SHIFT (3U)
8075/*! prg0_rtram_clk_STOP - show clock root status, 1 means clock stopped
8076 */
8077#define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_MASK)
8078#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_MASK (0xFFF0U)
8079#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_SHIFT (4U)
8080/*! LPCG_dc_lpcg_32_reserved_4_15 - reserved
8081 */
8082#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_MASK)
8083#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_MASK (0x10000U)
8084#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_SHIFT (16U)
8085/*! prg0_apb_clk_HWEN - Hardware Enable
8086 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8087 * 0b1..Enable HW automatic gating
8088 */
8089#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_MASK)
8090#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_MASK (0x20000U)
8091#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_SHIFT (17U)
8092/*! prg0_apb_clk_SWEN - Software Enable
8093 * 0b0..Disable SW clock regardless of HWEN
8094 * 0b1..Enable SW clock gating
8095 */
8096#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_MASK)
8097#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_MASK (0x40000U)
8098#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_SHIFT (18U)
8099/*! LPCG_dc_lpcg_32_reserved_18_18 - reserved
8100 */
8101#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_MASK)
8102#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_MASK (0x80000U)
8103#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_SHIFT (19U)
8104/*! prg0_apb_clk_STOP - show clock root status, 1 means clock stopped
8105 */
8106#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_MASK)
8107#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_MASK (0xFFF00000U)
8108#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_SHIFT (20U)
8109/*! LPCG_dc_lpcg_32_reserved_20_31 - reserved
8110 */
8111#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_MASK)
8112/*! @} */
8113
8114/*! @name LPCG_DC_LPCG_36 - na */
8115/*! @{ */
8116#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_MASK (0x1U)
8117#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_SHIFT (0U)
8118/*! LPCG_dc_lpcg_36_reserved_0_0 - reserved
8119 */
8120#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_MASK)
8121#define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_MASK (0x2U)
8122#define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_SHIFT (1U)
8123/*! prg1_rtram_clk_SWEN - Software Enable
8124 * 0b0..Disable SW clock regardless of HWEN
8125 * 0b1..Enable SW clock gating
8126 */
8127#define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_MASK)
8128#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_MASK (0x4U)
8129#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_SHIFT (2U)
8130/*! LPCG_dc_lpcg_36_reserved_2_2 - reserved
8131 */
8132#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_MASK)
8133#define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_MASK (0x8U)
8134#define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_SHIFT (3U)
8135/*! prg1_rtram_clk_STOP - show clock root status, 1 means clock stopped
8136 */
8137#define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_MASK)
8138#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_MASK (0xFFF0U)
8139#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_SHIFT (4U)
8140/*! LPCG_dc_lpcg_36_reserved_4_15 - reserved
8141 */
8142#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_MASK)
8143#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_MASK (0x10000U)
8144#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_SHIFT (16U)
8145/*! prg1_apb_clk_HWEN - Hardware Enable
8146 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8147 * 0b1..Enable HW automatic gating
8148 */
8149#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_MASK)
8150#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_MASK (0x20000U)
8151#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_SHIFT (17U)
8152/*! prg1_apb_clk_SWEN - Software Enable
8153 * 0b0..Disable SW clock regardless of HWEN
8154 * 0b1..Enable SW clock gating
8155 */
8156#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_MASK)
8157#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_MASK (0x40000U)
8158#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_SHIFT (18U)
8159/*! LPCG_dc_lpcg_36_reserved_18_18 - reserved
8160 */
8161#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_MASK)
8162#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_MASK (0x80000U)
8163#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_SHIFT (19U)
8164/*! prg1_apb_clk_STOP - show clock root status, 1 means clock stopped
8165 */
8166#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_MASK)
8167#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_MASK (0xFFF00000U)
8168#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_SHIFT (20U)
8169/*! LPCG_dc_lpcg_36_reserved_20_31 - reserved
8170 */
8171#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_MASK)
8172/*! @} */
8173
8174/*! @name LPCG_DC_LPCG_40 - na */
8175/*! @{ */
8176#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_MASK (0x1U)
8177#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_SHIFT (0U)
8178/*! LPCG_dc_lpcg_40_reserved_0_0 - reserved
8179 */
8180#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_MASK)
8181#define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_MASK (0x2U)
8182#define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_SHIFT (1U)
8183/*! prg2_rtram_clk_SWEN - Software Enable
8184 * 0b0..Disable SW clock regardless of HWEN
8185 * 0b1..Enable SW clock gating
8186 */
8187#define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_MASK)
8188#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_MASK (0x4U)
8189#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_SHIFT (2U)
8190/*! LPCG_dc_lpcg_40_reserved_2_2 - reserved
8191 */
8192#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_MASK)
8193#define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_MASK (0x8U)
8194#define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_SHIFT (3U)
8195/*! prg2_rtram_clk_STOP - show clock root status, 1 means clock stopped
8196 */
8197#define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_MASK)
8198#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_MASK (0xFFF0U)
8199#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_SHIFT (4U)
8200/*! LPCG_dc_lpcg_40_reserved_4_15 - reserved
8201 */
8202#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_MASK)
8203#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_MASK (0x10000U)
8204#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_SHIFT (16U)
8205/*! prg2_apb_clk_HWEN - Hardware Enable
8206 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8207 * 0b1..Enable HW automatic gating
8208 */
8209#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_MASK)
8210#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_MASK (0x20000U)
8211#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_SHIFT (17U)
8212/*! prg2_apb_clk_SWEN - Software Enable
8213 * 0b0..Disable SW clock regardless of HWEN
8214 * 0b1..Enable SW clock gating
8215 */
8216#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_MASK)
8217#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_MASK (0x40000U)
8218#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_SHIFT (18U)
8219/*! LPCG_dc_lpcg_40_reserved_18_18 - reserved
8220 */
8221#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_MASK)
8222#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_MASK (0x80000U)
8223#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_SHIFT (19U)
8224/*! prg2_apb_clk_STOP - show clock root status, 1 means clock stopped
8225 */
8226#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_MASK)
8227#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_MASK (0xFFF00000U)
8228#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_SHIFT (20U)
8229/*! LPCG_dc_lpcg_40_reserved_20_31 - reserved
8230 */
8231#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_MASK)
8232/*! @} */
8233
8234/*! @name LPCG_DC_LPCG_44 - na */
8235/*! @{ */
8236#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_MASK (0xFFFFU)
8237#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_SHIFT (0U)
8238/*! LPCG_dc_lpcg_44_reserved_0_15 - reserved
8239 */
8240#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_MASK)
8241#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_MASK (0x10000U)
8242#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_SHIFT (16U)
8243/*! dpr1_dpr_apb_clkg_HWEN - Hardware Enable
8244 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8245 * 0b1..Enable HW automatic gating
8246 */
8247#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_MASK)
8248#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_MASK (0x20000U)
8249#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_SHIFT (17U)
8250/*! dpr1_dpr_apb_clkg_SWEN - Software Enable
8251 * 0b0..Disable SW clock regardless of HWEN
8252 * 0b1..Enable SW clock gating
8253 */
8254#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_MASK)
8255#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_MASK (0x40000U)
8256#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_SHIFT (18U)
8257/*! LPCG_dc_lpcg_44_reserved_18_18 - reserved
8258 */
8259#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_MASK)
8260#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_MASK (0x80000U)
8261#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_SHIFT (19U)
8262/*! dpr1_dpr_apb_clkg_STOP - show clock root status, 1 means clock stopped
8263 */
8264#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_MASK)
8265#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_MASK (0x100000U)
8266#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_SHIFT (20U)
8267/*! dpr1_dpr_b_clkg_HWEN - Hardware Enable
8268 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8269 * 0b1..Enable HW automatic gating
8270 */
8271#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_MASK)
8272#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_MASK (0x200000U)
8273#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_SHIFT (21U)
8274/*! dpr1_dpr_b_clkg_SWEN - Software Enable
8275 * 0b0..Disable SW clock regardless of HWEN
8276 * 0b1..Enable SW clock gating
8277 */
8278#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_MASK)
8279#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_MASK (0x400000U)
8280#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_SHIFT (22U)
8281/*! LPCG_dc_lpcg_44_reserved_22_22 - reserved
8282 */
8283#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_MASK)
8284#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_MASK (0x800000U)
8285#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_SHIFT (23U)
8286/*! dpr1_dpr_b_clkg_STOP - show clock root status, 1 means clock stopped
8287 */
8288#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_MASK)
8289#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_MASK (0xFF000000U)
8290#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_SHIFT (24U)
8291/*! LPCG_dc_lpcg_44_reserved_24_31 - reserved
8292 */
8293#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_MASK)
8294/*! @} */
8295
8296/*! @name LPCG_DC_LPCG_48 - na */
8297/*! @{ */
8298#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_MASK (0x1U)
8299#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_SHIFT (0U)
8300/*! LPCG_dc_lpcg_48_reserved_0_0 - reserved
8301 */
8302#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_MASK)
8303#define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_MASK (0x2U)
8304#define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_SHIFT (1U)
8305/*! rtram1_rtr_clk_g_SWEN - Software Enable
8306 * 0b0..Disable SW clock regardless of HWEN
8307 * 0b1..Enable SW clock gating
8308 */
8309#define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_MASK)
8310#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_MASK (0x4U)
8311#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_SHIFT (2U)
8312/*! LPCG_dc_lpcg_48_reserved_2_2 - reserved
8313 */
8314#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_MASK)
8315#define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_MASK (0x8U)
8316#define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_SHIFT (3U)
8317/*! rtram1_rtr_clk_g_STOP - show clock root status, 1 means clock stopped
8318 */
8319#define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_MASK)
8320#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_MASK (0xFFFFFFF0U)
8321#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_SHIFT (4U)
8322/*! LPCG_dc_lpcg_48_reserved_4_31 - reserved
8323 */
8324#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_MASK)
8325/*! @} */
8326
8327/*! @name LPCG_DC_LPCG_52 - na */
8328/*! @{ */
8329#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_MASK (0x1U)
8330#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_SHIFT (0U)
8331/*! LPCG_dc_lpcg_52_reserved_0_0 - reserved
8332 */
8333#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_MASK)
8334#define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_MASK (0x2U)
8335#define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_SHIFT (1U)
8336/*! prg3_rtram_clk_SWEN - Software Enable
8337 * 0b0..Disable SW clock regardless of HWEN
8338 * 0b1..Enable SW clock gating
8339 */
8340#define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_MASK)
8341#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_MASK (0x4U)
8342#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_SHIFT (2U)
8343/*! LPCG_dc_lpcg_52_reserved_2_2 - reserved
8344 */
8345#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_MASK)
8346#define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_MASK (0x8U)
8347#define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_SHIFT (3U)
8348/*! prg3_rtram_clk_STOP - show clock root status, 1 means clock stopped
8349 */
8350#define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_MASK)
8351#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_MASK (0xFFF0U)
8352#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_SHIFT (4U)
8353/*! LPCG_dc_lpcg_52_reserved_4_15 - reserved
8354 */
8355#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_MASK)
8356#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_MASK (0x10000U)
8357#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_SHIFT (16U)
8358/*! prg3_apb_clk_HWEN - Hardware Enable
8359 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8360 * 0b1..Enable HW automatic gating
8361 */
8362#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_MASK)
8363#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_MASK (0x20000U)
8364#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_SHIFT (17U)
8365/*! prg3_apb_clk_SWEN - Software Enable
8366 * 0b0..Disable SW clock regardless of HWEN
8367 * 0b1..Enable SW clock gating
8368 */
8369#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_MASK)
8370#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_MASK (0x40000U)
8371#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_SHIFT (18U)
8372/*! LPCG_dc_lpcg_52_reserved_18_18 - reserved
8373 */
8374#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_MASK)
8375#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_MASK (0x80000U)
8376#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_SHIFT (19U)
8377/*! prg3_apb_clk_STOP - show clock root status, 1 means clock stopped
8378 */
8379#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_MASK)
8380#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_MASK (0xFFF00000U)
8381#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_SHIFT (20U)
8382/*! LPCG_dc_lpcg_52_reserved_20_31 - reserved
8383 */
8384#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_MASK)
8385/*! @} */
8386
8387/*! @name LPCG_DC_LPCG_56 - na */
8388/*! @{ */
8389#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_MASK (0x1U)
8390#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_SHIFT (0U)
8391/*! LPCG_dc_lpcg_56_reserved_0_0 - reserved
8392 */
8393#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_MASK)
8394#define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_MASK (0x2U)
8395#define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_SHIFT (1U)
8396/*! prg4_rtram_clk_SWEN - Software Enable
8397 * 0b0..Disable SW clock regardless of HWEN
8398 * 0b1..Enable SW clock gating
8399 */
8400#define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_MASK)
8401#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_MASK (0x4U)
8402#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_SHIFT (2U)
8403/*! LPCG_dc_lpcg_56_reserved_2_2 - reserved
8404 */
8405#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_MASK)
8406#define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_MASK (0x8U)
8407#define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_SHIFT (3U)
8408/*! prg4_rtram_clk_STOP - show clock root status, 1 means clock stopped
8409 */
8410#define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_MASK)
8411#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_MASK (0xFFF0U)
8412#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_SHIFT (4U)
8413/*! LPCG_dc_lpcg_56_reserved_4_15 - reserved
8414 */
8415#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_MASK)
8416#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_MASK (0x10000U)
8417#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_SHIFT (16U)
8418/*! prg4_apb_clk_HWEN - Hardware Enable
8419 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8420 * 0b1..Enable HW automatic gating
8421 */
8422#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_MASK)
8423#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_MASK (0x20000U)
8424#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_SHIFT (17U)
8425/*! prg4_apb_clk_SWEN - Software Enable
8426 * 0b0..Disable SW clock regardless of HWEN
8427 * 0b1..Enable SW clock gating
8428 */
8429#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_MASK)
8430#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_MASK (0x40000U)
8431#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_SHIFT (18U)
8432/*! LPCG_dc_lpcg_56_reserved_18_18 - reserved
8433 */
8434#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_MASK)
8435#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_MASK (0x80000U)
8436#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_SHIFT (19U)
8437/*! prg4_apb_clk_STOP - show clock root status, 1 means clock stopped
8438 */
8439#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_MASK)
8440#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_MASK (0xFFF00000U)
8441#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_SHIFT (20U)
8442/*! LPCG_dc_lpcg_56_reserved_20_31 - reserved
8443 */
8444#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_MASK)
8445/*! @} */
8446
8447/*! @name LPCG_DC_LPCG_60 - na */
8448/*! @{ */
8449#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_MASK (0x1U)
8450#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_SHIFT (0U)
8451/*! LPCG_dc_lpcg_60_reserved_0_0 - reserved
8452 */
8453#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_MASK)
8454#define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_MASK (0x2U)
8455#define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_SHIFT (1U)
8456/*! prg5_rtram_clk_SWEN - Software Enable
8457 * 0b0..Disable SW clock regardless of HWEN
8458 * 0b1..Enable SW clock gating
8459 */
8460#define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_MASK)
8461#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_MASK (0x4U)
8462#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_SHIFT (2U)
8463/*! LPCG_dc_lpcg_60_reserved_2_2 - reserved
8464 */
8465#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_MASK)
8466#define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_MASK (0x8U)
8467#define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_SHIFT (3U)
8468/*! prg5_rtram_clk_STOP - show clock root status, 1 means clock stopped
8469 */
8470#define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_MASK)
8471#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_MASK (0xFFF0U)
8472#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_SHIFT (4U)
8473/*! LPCG_dc_lpcg_60_reserved_4_15 - reserved
8474 */
8475#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_MASK)
8476#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_MASK (0x10000U)
8477#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_SHIFT (16U)
8478/*! prg5_apb_clk_HWEN - Hardware Enable
8479 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8480 * 0b1..Enable HW automatic gating
8481 */
8482#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_MASK)
8483#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_MASK (0x20000U)
8484#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_SHIFT (17U)
8485/*! prg5_apb_clk_SWEN - Software Enable
8486 * 0b0..Disable SW clock regardless of HWEN
8487 * 0b1..Enable SW clock gating
8488 */
8489#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_MASK)
8490#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_MASK (0x40000U)
8491#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_SHIFT (18U)
8492/*! LPCG_dc_lpcg_60_reserved_18_18 - reserved
8493 */
8494#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_MASK)
8495#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_MASK (0x80000U)
8496#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_SHIFT (19U)
8497/*! prg5_apb_clk_STOP - show clock root status, 1 means clock stopped
8498 */
8499#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_MASK)
8500#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_MASK (0xFFF00000U)
8501#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_SHIFT (20U)
8502/*! LPCG_dc_lpcg_60_reserved_20_31 - reserved
8503 */
8504#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_MASK)
8505/*! @} */
8506
8507/*! @name LPCG_DC_LPCG_64 - na */
8508/*! @{ */
8509#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_MASK (0x1U)
8510#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_SHIFT (0U)
8511/*! LPCG_dc_lpcg_64_reserved_0_0 - reserved
8512 */
8513#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_MASK)
8514#define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_MASK (0x2U)
8515#define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_SHIFT (1U)
8516/*! prg6_rtram_clk_SWEN - Software Enable
8517 * 0b0..Disable SW clock regardless of HWEN
8518 * 0b1..Enable SW clock gating
8519 */
8520#define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_MASK)
8521#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_MASK (0x4U)
8522#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_SHIFT (2U)
8523/*! LPCG_dc_lpcg_64_reserved_2_2 - reserved
8524 */
8525#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_MASK)
8526#define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_MASK (0x8U)
8527#define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_SHIFT (3U)
8528/*! prg6_rtram_clk_STOP - show clock root status, 1 means clock stopped
8529 */
8530#define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_MASK)
8531#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_MASK (0xFFF0U)
8532#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_SHIFT (4U)
8533/*! LPCG_dc_lpcg_64_reserved_4_15 - reserved
8534 */
8535#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_MASK)
8536#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_MASK (0x10000U)
8537#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_SHIFT (16U)
8538/*! prg6_apb_clk_HWEN - Hardware Enable
8539 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8540 * 0b1..Enable HW automatic gating
8541 */
8542#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_MASK)
8543#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_MASK (0x20000U)
8544#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_SHIFT (17U)
8545/*! prg6_apb_clk_SWEN - Software Enable
8546 * 0b0..Disable SW clock regardless of HWEN
8547 * 0b1..Enable SW clock gating
8548 */
8549#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_MASK)
8550#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_MASK (0x40000U)
8551#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_SHIFT (18U)
8552/*! LPCG_dc_lpcg_64_reserved_18_18 - reserved
8553 */
8554#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_MASK)
8555#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_MASK (0x80000U)
8556#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_SHIFT (19U)
8557/*! prg6_apb_clk_STOP - show clock root status, 1 means clock stopped
8558 */
8559#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_MASK)
8560#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_MASK (0xFFF00000U)
8561#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_SHIFT (20U)
8562/*! LPCG_dc_lpcg_64_reserved_20_31 - reserved
8563 */
8564#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_MASK)
8565/*! @} */
8566
8567/*! @name LPCG_DC_LPCG_68 - na */
8568/*! @{ */
8569#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_MASK (0x1U)
8570#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_SHIFT (0U)
8571/*! LPCG_dc_lpcg_68_reserved_0_0 - reserved
8572 */
8573#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_MASK)
8574#define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_MASK (0x2U)
8575#define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_SHIFT (1U)
8576/*! prg7_rtram_clk_SWEN - Software Enable
8577 * 0b0..Disable SW clock regardless of HWEN
8578 * 0b1..Enable SW clock gating
8579 */
8580#define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_MASK)
8581#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_MASK (0x4U)
8582#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_SHIFT (2U)
8583/*! LPCG_dc_lpcg_68_reserved_2_2 - reserved
8584 */
8585#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_MASK)
8586#define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_MASK (0x8U)
8587#define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_SHIFT (3U)
8588/*! prg7_rtram_clk_STOP - show clock root status, 1 means clock stopped
8589 */
8590#define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_MASK)
8591#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_MASK (0xFFF0U)
8592#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_SHIFT (4U)
8593/*! LPCG_dc_lpcg_68_reserved_4_15 - reserved
8594 */
8595#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_MASK)
8596#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_MASK (0x10000U)
8597#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_SHIFT (16U)
8598/*! prg7_apb_clk_HWEN - Hardware Enable
8599 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8600 * 0b1..Enable HW automatic gating
8601 */
8602#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_MASK)
8603#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_MASK (0x20000U)
8604#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_SHIFT (17U)
8605/*! prg7_apb_clk_SWEN - Software Enable
8606 * 0b0..Disable SW clock regardless of HWEN
8607 * 0b1..Enable SW clock gating
8608 */
8609#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_MASK)
8610#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_MASK (0x40000U)
8611#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_SHIFT (18U)
8612/*! LPCG_dc_lpcg_68_reserved_18_18 - reserved
8613 */
8614#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_MASK)
8615#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_MASK (0x80000U)
8616#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_SHIFT (19U)
8617/*! prg7_apb_clk_STOP - show clock root status, 1 means clock stopped
8618 */
8619#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_MASK)
8620#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_MASK (0xFFF00000U)
8621#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_SHIFT (20U)
8622/*! LPCG_dc_lpcg_68_reserved_20_31 - reserved
8623 */
8624#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_MASK)
8625/*! @} */
8626
8627/*! @name LPCG_DC_LPCG_72 - na */
8628/*! @{ */
8629#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_MASK (0x1U)
8630#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_SHIFT (0U)
8631/*! LPCG_dc_lpcg_72_reserved_0_0 - reserved
8632 */
8633#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_MASK)
8634#define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_MASK (0x2U)
8635#define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_SHIFT (1U)
8636/*! prg8_rtram_clk_SWEN - Software Enable
8637 * 0b0..Disable SW clock regardless of HWEN
8638 * 0b1..Enable SW clock gating
8639 */
8640#define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_MASK)
8641#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_MASK (0x4U)
8642#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_SHIFT (2U)
8643/*! LPCG_dc_lpcg_72_reserved_2_2 - reserved
8644 */
8645#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_MASK)
8646#define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_MASK (0x8U)
8647#define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_SHIFT (3U)
8648/*! prg8_rtram_clk_STOP - show clock root status, 1 means clock stopped
8649 */
8650#define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_MASK)
8651#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_MASK (0xFFF0U)
8652#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_SHIFT (4U)
8653/*! LPCG_dc_lpcg_72_reserved_4_15 - reserved
8654 */
8655#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_MASK)
8656#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_MASK (0x10000U)
8657#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_SHIFT (16U)
8658/*! prg8_apb_clk_HWEN - Hardware Enable
8659 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8660 * 0b1..Enable HW automatic gating
8661 */
8662#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_MASK)
8663#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_MASK (0x20000U)
8664#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_SHIFT (17U)
8665/*! prg8_apb_clk_SWEN - Software Enable
8666 * 0b0..Disable SW clock regardless of HWEN
8667 * 0b1..Enable SW clock gating
8668 */
8669#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_MASK)
8670#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_MASK (0x40000U)
8671#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_SHIFT (18U)
8672/*! LPCG_dc_lpcg_72_reserved_18_18 - reserved
8673 */
8674#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_MASK)
8675#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_MASK (0x80000U)
8676#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_SHIFT (19U)
8677/*! prg8_apb_clk_STOP - show clock root status, 1 means clock stopped
8678 */
8679#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_MASK)
8680#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_MASK (0xFFF00000U)
8681#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_SHIFT (20U)
8682/*! LPCG_dc_lpcg_72_reserved_20_31 - reserved
8683 */
8684#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_MASK)
8685/*! @} */
8686
8687
8688/*!
8689 * @}
8690 */ /* end of group DC_LPCG_Register_Masks */
8691
8692
8693/* DC_LPCG - Peripheral instance base addresses */
8694/** Peripheral DC__LPCG_DSP0_CLK base address */
8695#define DC__LPCG_DSP0_CLK_BASE (0x56010000u)
8696/** Peripheral DC__LPCG_DSP0_CLK base pointer */
8697#define DC__LPCG_DSP0_CLK ((DC_LPCG_Type *)DC__LPCG_DSP0_CLK_BASE)
8698/** Array initializer of DC_LPCG peripheral base addresses */
8699#define DC_LPCG_BASE_ADDRS { DC__LPCG_DSP0_CLK_BASE }
8700/** Array initializer of DC_LPCG peripheral base pointers */
8701#define DC_LPCG_BASE_PTRS { DC__LPCG_DSP0_CLK }
8702
8703/*!
8704 * @}
8705 */ /* end of group DC_LPCG_Peripheral_Access_Layer */
8706
8707
8708/* ----------------------------------------------------------------------------
8709 -- DDRC Peripheral Access Layer
8710 ---------------------------------------------------------------------------- */
8711
8712/*!
8713 * @addtogroup DDRC_Peripheral_Access_Layer DDRC Peripheral Access Layer
8714 * @{
8715 */
8716
8717/** DDRC - Register Layout Typedef */
8718typedef struct {
8719 __IO uint32_t MSTR; /**< Master Register0, offset: 0x0 */
8720 __I uint32_t STAT; /**< Operating Mode Status Register, offset: 0x4 */
8721 __IO uint32_t MSTR1; /**< Operating Mode Status Register, offset: 0x8 */
8722 __IO uint32_t MRCTRL3; /**< Operating Mode Status Register, offset: 0xC */
8723 __IO uint32_t MRCTRL0; /**< Mode Register Read/Write Control Register 0., offset: 0x10 */
8724 __IO uint32_t MRCTRL1; /**< Mode Register Read/Write Control Register 1, offset: 0x14 */
8725 __I uint32_t MRSTAT; /**< Mode Register Read/Write Status Register, offset: 0x18 */
8726 __IO uint32_t MRCTRL2; /**< Mode Register Read/Write Control Register 2, offset: 0x1C */
8727 __IO uint32_t DERATEEN; /**< Temperature Derate Enable Register, offset: 0x20 */
8728 __IO uint32_t DERATEINT; /**< Temperature Derate Interval Register, offset: 0x24 */
8729 uint8_t RESERVED_0[8];
8730 __IO uint32_t PWRCTL; /**< Low Power Control Register, offset: 0x30 */
8731 __IO uint32_t PWRTMG; /**< Low Power Timing Register, offset: 0x34 */
8732 __IO uint32_t HWLPCTL; /**< Hardware Low Power Control Register, offset: 0x38 */
8733 uint8_t RESERVED_1[20];
8734 __IO uint32_t RFSHCTL0; /**< Refresh Control Register 0, offset: 0x50 */
8735 __IO uint32_t RFSHCTL1; /**< Refresh Control Register 1, offset: 0x54 */
8736 uint8_t RESERVED_2[8];
8737 __IO uint32_t RFSHCTL3; /**< Refresh Control Register 3, offset: 0x60 */
8738 __IO uint32_t RFSHTMG; /**< Refresh Timing Register, offset: 0x64 */
8739 uint8_t RESERVED_3[104];
8740 __IO uint32_t INIT0; /**< SDRAM Initialization Register 0, offset: 0xD0 */
8741 __IO uint32_t INIT1; /**< SDRAM Initialization Register 1, offset: 0xD4 */
8742 __IO uint32_t INIT2; /**< SDRAM Initialization Register 2, offset: 0xD8 */
8743 __IO uint32_t INIT3; /**< SDRAM Initialization Register 3, offset: 0xDC */
8744 __IO uint32_t INIT4; /**< SDRAM Initialization Register 4, offset: 0xE0 */
8745 __IO uint32_t INIT5; /**< SDRAM Initialization Register 5, offset: 0xE4 */
8746 __IO uint32_t INIT6; /**< SDRAM Initialization Register 6, offset: 0xE8 */
8747 __IO uint32_t INIT7; /**< SDRAM Initialization Register 7, offset: 0xEC */
8748 __IO uint32_t DIMMCTL; /**< DIMM Control Register, offset: 0xF0 */
8749 __IO uint32_t RANKCTL; /**< Rank Control Register, offset: 0xF4 */
8750 uint8_t RESERVED_4[8];
8751 __IO uint32_t DRAMTMG0; /**< SDRAM Timing Register 0, offset: 0x100 */
8752 __IO uint32_t DRAMTMG1; /**< SDRAM Timing Register 1, offset: 0x104 */
8753 __IO uint32_t DRAMTMG2; /**< SDRAM Timing Register 2, offset: 0x108 */
8754 __IO uint32_t DRAMTMG3; /**< SDRAM Timing Register 3, offset: 0x10C */
8755 __IO uint32_t DRAMTMG4; /**< SDRAM Timing Register 4, offset: 0x110 */
8756 __IO uint32_t DRAMTMG5; /**< SDRAM Timing Register 5, offset: 0x114 */
8757 __IO uint32_t DRAMTMG6; /**< SDRAM Timing Register 6, offset: 0x118 */
8758 __IO uint32_t DRAMTMG7; /**< SDRAM Timing Register 7, offset: 0x11C */
8759 __IO uint32_t DRAMTMG8; /**< SDRAM Timing Register 8, offset: 0x120 */
8760 __IO uint32_t DRAMTMG9; /**< SDRAM Timing Register 9, offset: 0x124 */
8761 __IO uint32_t DRAMTMG10; /**< SDRAM Timing Register 10, offset: 0x128 */
8762 __IO uint32_t DRAMTMG11; /**< SDRAM Timing Register 11, offset: 0x12C */
8763 __IO uint32_t DRAMTMG12; /**< SDRAM Timing Register 12, offset: 0x130 */
8764 __IO uint32_t DRAMTMG13; /**< SDRAM Timing Register 13, offset: 0x134 */
8765 __IO uint32_t DRAMTMG14; /**< SDRAM Timing Register 14, offset: 0x138 */
8766 __IO uint32_t DRAMTMG15; /**< SDRAM Timing Register 15, offset: 0x13C */
8767 uint8_t RESERVED_5[64];
8768 __IO uint32_t ZQCTL0; /**< ZQ Control Register 0, offset: 0x180 */
8769 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */
8770 __IO uint32_t ZQCTL2; /**< ZQ Control Register 2, offset: 0x188 */
8771 __I uint32_t ZQSTAT; /**< ZQ Status Register, offset: 0x18C */
8772 __IO uint32_t DFITMG0; /**< DFI Timing Register 0, offset: 0x190 */
8773 __IO uint32_t DFITMG1; /**< DFI Timing Register 1, offset: 0x194 */
8774 __IO uint32_t DFILPCFG0; /**< DFI Low Power Configuration Register 0, offset: 0x198 */
8775 __IO uint32_t DFILPCFG1; /**< DFI Low Power Configuration Register 1, offset: 0x19C */
8776 __IO uint32_t DFIUPD0; /**< DFI Update Register 0, offset: 0x1A0 */
8777 __IO uint32_t DFIUPD1; /**< DFI Update Register 1, offset: 0x1A4 */
8778 __IO uint32_t DFIUPD2; /**< DFI Update Register 2, offset: 0x1A8 */
8779 uint8_t RESERVED_6[4];
8780 __IO uint32_t DFIMISC; /**< DFI Miscellaneous Control Register, offset: 0x1B0 */
8781 __IO uint32_t DFITMG2; /**< DFI Timing Register 2, offset: 0x1B4 */
8782 __IO uint32_t DFITMG3; /**< DFI Timing Register 3, offset: 0x1B8 */
8783 __I uint32_t DFISTAT; /**< DFI Status Register, offset: 0x1BC */
8784 __IO uint32_t DBICTL; /**< DM/DBI Control Register, offset: 0x1C0 */
8785 uint8_t RESERVED_7[60];
8786 __IO uint32_t ADDRMAP0; /**< Address Map Register 0, offset: 0x200 */
8787 __IO uint32_t ADDRMAP1; /**< Address Map Register 1, offset: 0x204 */
8788 __IO uint32_t ADDRMAP2; /**< Address Map Register 2, offset: 0x208 */
8789 __IO uint32_t ADDRMAP3; /**< Address Map Register 3, offset: 0x20C */
8790 __IO uint32_t ADDRMAP4; /**< Address Map Register 4, offset: 0x210 */
8791 __IO uint32_t ADDRMAP5; /**< Address Map Register 5, offset: 0x214 */
8792 __IO uint32_t ADDRMAP6; /**< Address Map Register 6, offset: 0x218 */
8793 __IO uint32_t ADDRMAP7; /**< Address Map Register 7, offset: 0x21C */
8794 __IO uint32_t ADDRMAP8; /**< Address Map Register 8, offset: 0x220 */
8795 __IO uint32_t ADDRMAP9; /**< Address Map Register 9, offset: 0x224 */
8796 __IO uint32_t ADDRMAP10; /**< Address Map Register 10, offset: 0x228 */
8797 __IO uint32_t ADDRMAP11; /**< Address Map Register 11, offset: 0x22C */
8798 uint8_t RESERVED_8[16];
8799 __IO uint32_t ODTCFG; /**< ODT Configuration Register, offset: 0x240 */
8800 __IO uint32_t ODTMAP; /**< ODT/Rank Map Register, offset: 0x244 */
8801 uint8_t RESERVED_9[8];
8802 __IO uint32_t SCHED; /**< Scheduler Control Register, offset: 0x250 */
8803 __IO uint32_t SCHED1; /**< Scheduler Control Register 1, offset: 0x254 */
8804 uint8_t RESERVED_10[4];
8805 __IO uint32_t PERFHPR1; /**< High Priority Read CAM Register 1, offset: 0x25C */
8806 uint8_t RESERVED_11[4];
8807 __IO uint32_t PERFLPR1; /**< Low Priority Read CAM Register 1, offset: 0x264 */
8808 uint8_t RESERVED_12[4];
8809 __IO uint32_t PERFWR1; /**< Write CAM Register 1, offset: 0x26C */
8810 uint8_t RESERVED_13[144];
8811 __IO uint32_t DBG0; /**< Debug Register 0, offset: 0x300 */
8812 __IO uint32_t DBG1; /**< Debug Register 1, offset: 0x304 */
8813 __I uint32_t DBGCAM; /**< CAM Debug Register, offset: 0x308 */
8814 __IO uint32_t DBGCMD; /**< Command Debug Register, offset: 0x30C */
8815 __I uint32_t DBGSTAT; /**< Status Debug Register, offset: 0x310 */
8816 uint8_t RESERVED_14[12];
8817 __IO uint32_t SWCTL; /**< Software Register Programming Control Enable, offset: 0x320 */
8818 __I uint32_t SWSTAT; /**< Software Register Programming Control Status, offset: 0x324 */
8819 uint8_t RESERVED_15[68];
8820 __IO uint32_t POISONCFG; /**< AXI Poison Configuration Register., offset: 0x36C */
8821 __I uint32_t POISONSTAT; /**< AXI Poison Status Register, offset: 0x370 */
8822 uint8_t RESERVED_16[136];
8823 __I uint32_t PSTAT; /**< Port Status Register, offset: 0x3FC */
8824 __IO uint32_t PCCFG; /**< Port Common Configuration Register, offset: 0x400 */
8825 __IO uint32_t PCFGR_0; /**< Port n Configuration Read Register, offset: 0x404 */
8826 __IO uint32_t PCFGW_0; /**< Port n Configuration Write Register, offset: 0x408 */
8827 uint8_t RESERVED_17[132];
8828 __IO uint32_t PCTRL_0; /**< Port n Control Register, offset: 0x490 */
8829 __IO uint32_t PCFGQOS0_0; /**< Port n Read QoS Configuration Register 0, offset: 0x494 */
8830 __IO uint32_t PCFGQOS1_0; /**< Port n Read QoS Configuration Register 1, offset: 0x498 */
8831 __IO uint32_t PCFGWQOS0_0; /**< Port n Write QoS Configuration Register 0, offset: 0x49C */
8832 __IO uint32_t PCFGWQOS1_0; /**< Port n Write QoS Configuration Register 1, offset: 0x4A0 */
8833 uint8_t RESERVED_18[7036];
8834 __IO uint32_t DERATEEN_SHADOW; /**< [SHADOW] Temperature Derate Enable Register, offset: 0x2020 */
8835 __IO uint32_t DERATEINT_SHADOW; /**< [SHADOW] Temperature Derate Interval Register, offset: 0x2024 */
8836 uint8_t RESERVED_19[40];
8837 __IO uint32_t RFSHCTL0_SHADOW; /**< [SHADOW] Refresh Control Register 0, offset: 0x2050 */
8838 uint8_t RESERVED_20[16];
8839 __IO uint32_t RFSHTMG_SHADOW; /**< [SHADOW] Refresh Timing Register, offset: 0x2064 */
8840 uint8_t RESERVED_21[116];
8841 __IO uint32_t INIT3_SHADOW; /**< [SHADOW] SDRAM Initialization Register 3, offset: 0x20DC */
8842 __IO uint32_t INIT4_SHADOW; /**< [SHADOW] SDRAM Initialization Register 4, offset: 0x20E0 */
8843 uint8_t RESERVED_22[4];
8844 __IO uint32_t INIT6_SHADOW; /**< [SHADOW] SDRAM Initialization Register 6, offset: 0x20E8 */
8845 __IO uint32_t INIT7_SHADOW; /**< [SHADOW] SDRAM Initialization Register 7, offset: 0x20EC */
8846 uint8_t RESERVED_23[16];
8847 __IO uint32_t DRAMTMG0_SHADOW; /**< [SHADOW] SDRAM Timing Register 0, offset: 0x2100 */
8848 __IO uint32_t DRAMTMG1_SHADOW; /**< [SHADOW] SDRAM Timing Register 1, offset: 0x2104 */
8849 __IO uint32_t DRAMTMG2_SHADOW; /**< [SHADOW] SDRAM Timing Register 2, offset: 0x2108 */
8850 __IO uint32_t DRAMTMG3_SHADOW; /**< [SHADOW] SDRAM Timing Register 3, offset: 0x210C */
8851 __IO uint32_t DRAMTMG4_SHADOW; /**< [SHADOW] SDRAM Timing Register 4, offset: 0x2110 */
8852 __IO uint32_t DRAMTMG5_SHADOW; /**< [SHADOW] SDRAM Timing Register 5, offset: 0x2114 */
8853 __IO uint32_t DRAMTMG6_SHADOW; /**< [SHADOW] SDRAM Timing Register 6, offset: 0x2118 */
8854 __IO uint32_t DRAMTMG7_SHADOW; /**< [SHADOW] SDRAM Timing Register 7, offset: 0x211C */
8855 __IO uint32_t DRAMTMG8_SHADOW; /**< [SHADOW] SDRAM Timing Register 8, offset: 0x2120 */
8856 __IO uint32_t DRAMTMG9_SHADOW; /**< [SHADOW] SDRAM Timing Register 9, offset: 0x2124 */
8857 __IO uint32_t DRAMTMG10_SHADOW; /**< [SHADOW] SDRAM Timing Register 10, offset: 0x2128 */
8858 __IO uint32_t DRAMTMG11_SHADOW; /**< [SHADOW] SDRAM Timing Register 11, offset: 0x212C */
8859 __IO uint32_t DRAMTMG12_SHADOW; /**< [SHADOW] SDRAM Timing Register 12, offset: 0x2130 */
8860 __IO uint32_t DRAMTMG13_SHADOW; /**< [SHADOW] SDRAM Timing Register 13, offset: 0x2134 */
8861 __IO uint32_t DRAMTMG14_SHADOW; /**< [SHADOW] SDRAM Timing Register 14, offset: 0x2138 */
8862 __IO uint32_t DRAMTMG15_SHADOW; /**< [SHADOW] SDRAM Timing Register 15, offset: 0x213C */
8863 uint8_t RESERVED_24[64];
8864 __IO uint32_t ZQCTL0_SHADOW; /**< [SHADOW] ZQ Control Register 0, offset: 0x2180 */
8865 uint8_t RESERVED_25[12];
8866 __IO uint32_t DFITMG0_SHADOW; /**< [SHADOW] DFI Timing Register 0, offset: 0x2190 */
8867 __IO uint32_t DFITMG1_SHADOW; /**< [SHADOW] DFI Timing Register 1, offset: 0x2194 */
8868 uint8_t RESERVED_26[28];
8869 __IO uint32_t DFITMG2_SHADOW; /**< [SHADOW] DFI Timing Register 2, offset: 0x21B4 */
8870 __IO uint32_t DFITMG3_SHADOW; /**< [SHADOW] DFI Timing Register 3, offset: 0x21B8 */
8871 uint8_t RESERVED_27[132];
8872 __IO uint32_t ODTCFG_SHADOW; /**< [SHADOW] ODT Configuration Register, offset: 0x2240 */
8873} DDRC_Type;
8874
8875/* ----------------------------------------------------------------------------
8876 -- DDRC Register Masks
8877 ---------------------------------------------------------------------------- */
8878
8879/*!
8880 * @addtogroup DDRC_Register_Masks DDRC Register Masks
8881 * @{
8882 */
8883
8884/*! @name MSTR - Master Register0 */
8885/*! @{ */
8886#define DDRC_MSTR_ddr3_MASK (0x1U)
8887#define DDRC_MSTR_ddr3_SHIFT (0U)
8888/*! ddr3 - Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only
8889 * present in designs that support DDR3.
8890 */
8891#define DDRC_MSTR_ddr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_ddr3_SHIFT)) & DDRC_MSTR_ddr3_MASK)
8892#define DDRC_MSTR_lpddr2_MASK (0x4U)
8893#define DDRC_MSTR_lpddr2_SHIFT (2U)
8894/*! lpddr2 - Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use
8895 * Present only in designs configured to support LPDDR2.
8896 */
8897#define DDRC_MSTR_lpddr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr2_SHIFT)) & DDRC_MSTR_lpddr2_MASK)
8898#define DDRC_MSTR_lpddr3_MASK (0x8U)
8899#define DDRC_MSTR_lpddr3_SHIFT (3U)
8900/*! lpddr3 - Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use
8901 * Present only in designs configured to support LPDDR3.
8902 */
8903#define DDRC_MSTR_lpddr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr3_SHIFT)) & DDRC_MSTR_lpddr3_MASK)
8904#define DDRC_MSTR_ddr4_MASK (0x10U)
8905#define DDRC_MSTR_ddr4_SHIFT (4U)
8906/*! ddr4 - Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present
8907 * only in designs configured to support DDR4.
8908 */
8909#define DDRC_MSTR_ddr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_ddr4_SHIFT)) & DDRC_MSTR_ddr4_MASK)
8910#define DDRC_MSTR_lpddr4_MASK (0x20U)
8911#define DDRC_MSTR_lpddr4_SHIFT (5U)
8912/*! lpddr4 - Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use
8913 * Present only in designs configured to support LPDDR4.
8914 */
8915#define DDRC_MSTR_lpddr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr4_SHIFT)) & DDRC_MSTR_lpddr4_MASK)
8916#define DDRC_MSTR_burstchop_MASK (0x200U)
8917#define DDRC_MSTR_burstchop_SHIFT (9U)
8918/*! burstchop - When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. Burst Chop for Reads
8919 * is exercised only in HIF configurations (DDRC_INCL_ARB not set) and if in full bus width mode
8920 * (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. Burst Chop for Writes is
8921 * exercised only if Partial Writes enabled (DDRC_PARTIAL_WR=1) and if CRC is disabled
8922 * (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1),
8923 * burst chop is not supported, and this bit must be set to '0'. BC4 (fixed) mode is not supported.
8924 */
8925#define DDRC_MSTR_burstchop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_burstchop_SHIFT)) & DDRC_MSTR_burstchop_MASK)
8926#define DDRC_MSTR_en_2t_timing_mode_MASK (0x400U)
8927#define DDRC_MSTR_en_2t_timing_mode_SHIFT (10U)
8928/*! en_2t_timing_mode - If 1, then DDRC uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all
8929 * command signals (except chip select) are held for 2 clocks on the SDRAM bus. Chip select is
8930 * asserted on the second cycle of the command Note: 2T timing is not supported in
8931 * LPDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE
8932 * is set Note: 2T timing is not supported in DDR4 geardown mode. Note: 2T timing is not supported
8933 * in Shared-AC dual channel mode and the register value is don't care.
8934 */
8935#define DDRC_MSTR_en_2t_timing_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_en_2t_timing_mode_SHIFT)) & DDRC_MSTR_en_2t_timing_mode_MASK)
8936#define DDRC_MSTR_geardown_mode_MASK (0x800U)
8937#define DDRC_MSTR_geardown_mode_SHIFT (11U)
8938/*! geardown_mode - 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in
8939 * normal mode (1N). This register can be changed, only when the Controller is in self-refresh
8940 * mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode is not supported
8941 * if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: Geardown mode is not supported
8942 * if the configuration parameter DDRC_SHARED_AC is set (in Shared-AC mode) and the register value
8943 * is don't care
8944 */
8945#define DDRC_MSTR_geardown_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_geardown_mode_SHIFT)) & DDRC_MSTR_geardown_mode_MASK)
8946#define DDRC_MSTR_data_bus_width_MASK (0x3000U)
8947#define DDRC_MSTR_data_bus_width_SHIFT (12U)
8948/*! data_bus_width - Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus
8949 * width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter DQ bus width to SDRAM - 11 -
8950 * Reserved. Note that half bus width mode is only supported when the SDRAM bus width is a
8951 * multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple
8952 * of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus
8953 * width (excluding any ECC width).
8954 */
8955#define DDRC_MSTR_data_bus_width(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_data_bus_width_SHIFT)) & DDRC_MSTR_data_bus_width_MASK)
8956#define DDRC_MSTR_dll_off_mode_MASK (0x8000U)
8957#define DDRC_MSTR_dll_off_mode_SHIFT (15U)
8958/*! dll_off_mode - Set to 1 when the DDRC and DRAM has to be put in DLL-off mode for low frequency
8959 * operation. Set to 0 to put DDRC and DRAM in DLL-on mode for normal frequency operation. If DDR4
8960 * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), dll_off_mode is not
8961 * supported, and this bit must be set to '0'.
8962 */
8963#define DDRC_MSTR_dll_off_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_dll_off_mode_SHIFT)) & DDRC_MSTR_dll_off_mode_MASK)
8964#define DDRC_MSTR_burst_rdwr_MASK (0xF0000U)
8965#define DDRC_MSTR_burst_rdwr_SHIFT (16U)
8966/*! burst_rdwr - SDRAM burst length used
8967 * 0b0001..Burst length of 2 (only supported for mDDR)
8968 * 0b0010..Burst length of 4
8969 * 0b0100..Burst length of 8
8970 * 0b1000..Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4)
8971 */
8972#define DDRC_MSTR_burst_rdwr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_burst_rdwr_SHIFT)) & DDRC_MSTR_burst_rdwr_MASK)
8973#define DDRC_MSTR_frequency_ratio_MASK (0x400000U)
8974#define DDRC_MSTR_frequency_ratio_SHIFT (22U)
8975/*! frequency_ratio - Selects the Frequency Ratio
8976 * 0b0..1:2 Mode
8977 * 0b1..1:1 Mode
8978 */
8979#define DDRC_MSTR_frequency_ratio(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_frequency_ratio_SHIFT)) & DDRC_MSTR_frequency_ratio_MASK)
8980#define DDRC_MSTR_active_ranks_MASK (0x3000000U)
8981#define DDRC_MSTR_active_ranks_SHIFT (24U)
8982/*! active_ranks - Only present for multi-rank configurations. Each bit represents one rank. For
8983 * two-rank configurations, only bits[25:24] are present.
8984 */
8985#define DDRC_MSTR_active_ranks(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_active_ranks_SHIFT)) & DDRC_MSTR_active_ranks_MASK)
8986#define DDRC_MSTR_frequency_mode_MASK (0x20000000U)
8987#define DDRC_MSTR_frequency_mode_SHIFT (29U)
8988/*! frequency_mode - Choose which registers are used.
8989 * 0b0..Original Registers
8990 * 0b1..Shadow Registers
8991 */
8992#define DDRC_MSTR_frequency_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_frequency_mode_SHIFT)) & DDRC_MSTR_frequency_mode_MASK)
8993#define DDRC_MSTR_device_config_MASK (0xC0000000U)
8994#define DDRC_MSTR_device_config_SHIFT (30U)
8995/*! device_config - Indicates the configuration of the device used in the system.
8996 * 0b00..x4 device
8997 * 0b01..x8 device
8998 * 0b10..x16 device
8999 * 0b11..x32 device
9000 */
9001#define DDRC_MSTR_device_config(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_device_config_SHIFT)) & DDRC_MSTR_device_config_MASK)
9002/*! @} */
9003
9004/*! @name STAT - Operating Mode Status Register */
9005/*! @{ */
9006#define DDRC_STAT_operating_mode_MASK (0x7U)
9007#define DDRC_STAT_operating_mode_SHIFT (0U)
9008/*! operating_mode - Operating mode
9009 */
9010#define DDRC_STAT_operating_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_operating_mode_SHIFT)) & DDRC_STAT_operating_mode_MASK)
9011#define DDRC_STAT_selfref_type_MASK (0x30U)
9012#define DDRC_STAT_selfref_type_SHIFT (4U)
9013/*! selfref_type - Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if
9014 * it was under Automatic Self Refresh control only or not.
9015 * 0b00..SDRAM is not in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by
9016 * CRCPARCTRL1.crc_parity_retry_enable, this also indicates SRE command is still in parity error window or retry is
9017 * in-progress.
9018 * 0b11..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was caused by Automatic Self
9019 * Refresh only. If retry is enabled, this guarantees SRE command is executed correctly without parity error.
9020 * 0b10..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was not caused solely under
9021 * Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software
9022 * (reg_ddrc_selfref_sw). If retry is enabled, this guarantees SRE command is executed correctly without parity
9023 */
9024#define DDRC_STAT_selfref_type(x) (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_selfref_type_SHIFT)) & DDRC_STAT_selfref_type_MASK)
9025#define DDRC_STAT_selfref_state_MASK (0x300U)
9026#define DDRC_STAT_selfref_state_SHIFT (8U)
9027/*! selfref_state - Self refresh state. This indicates self refresh or self refresh power down state
9028 * for LPDDR4. This register is used for frequency change and MRR/MRW access during self refresh.
9029 * 0b00..SDRAM is not in Self Refresh.
9030 * 0b01..Self refresh 1
9031 * 0b10..Self refresh power down
9032 * 0b11..Self refresh
9033 */
9034#define DDRC_STAT_selfref_state(x) (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_selfref_state_SHIFT)) & DDRC_STAT_selfref_state_MASK)
9035/*! @} */
9036
9037/*! @name MSTR1 - Operating Mode Status Register */
9038/*! @{ */
9039#define DDRC_MSTR1_rank_tmgreg_sel_MASK (0x3U)
9040#define DDRC_MSTR1_rank_tmgreg_sel_SHIFT (0U)
9041/*! rank_tmgreg_sel - rank_tmgreg_sel
9042 * 0b00..USE DRAMTMGx registers for the rank
9043 * 0b01..USE MRAMTMGx registers for the rank
9044 */
9045#define DDRC_MSTR1_rank_tmgreg_sel(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR1_rank_tmgreg_sel_SHIFT)) & DDRC_MSTR1_rank_tmgreg_sel_MASK)
9046#define DDRC_MSTR1_alt_addrmap_en_MASK (0x10000U)
9047#define DDRC_MSTR1_alt_addrmap_en_SHIFT (16U)
9048/*! alt_addrmap_en - Enable Alternative Address Map
9049 * 0b0..Disable Alternative Address Map
9050 * 0b1..Enable Alternative Address Map
9051 */
9052#define DDRC_MSTR1_alt_addrmap_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR1_alt_addrmap_en_SHIFT)) & DDRC_MSTR1_alt_addrmap_en_MASK)
9053/*! @} */
9054
9055/*! @name MRCTRL3 - Operating Mode Status Register */
9056/*! @{ */
9057#define DDRC_MRCTRL3_mr_rank_sel_MASK (0x3U)
9058#define DDRC_MRCTRL3_mr_rank_sel_SHIFT (0U)
9059/*! mr_rank_sel - mr_rank_sel
9060 */
9061#define DDRC_MRCTRL3_mr_rank_sel(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL3_mr_rank_sel_SHIFT)) & DDRC_MRCTRL3_mr_rank_sel_MASK)
9062/*! @} */
9063
9064/*! @name MRCTRL0 - Mode Register Read/Write Control Register 0. */
9065/*! @{ */
9066#define DDRC_MRCTRL0_mr_type_MASK (0x1U)
9067#define DDRC_MRCTRL0_mr_type_SHIFT (0U)
9068/*! mr_type - Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4.
9069 * 0b0..Write
9070 * 0b1..Read
9071 */
9072#define DDRC_MRCTRL0_mr_type(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_type_SHIFT)) & DDRC_MRCTRL0_mr_type_MASK)
9073#define DDRC_MRCTRL0_mpr_en_MASK (0x2U)
9074#define DDRC_MRCTRL0_mpr_en_SHIFT (1U)
9075/*! mpr_en - Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4).
9076 * 0b0..MRS
9077 * 0b1..WR/RD for MPR
9078 */
9079#define DDRC_MRCTRL0_mpr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mpr_en_SHIFT)) & DDRC_MRCTRL0_mpr_en_MASK)
9080#define DDRC_MRCTRL0_pda_en_MASK (0x4U)
9081#define DDRC_MRCTRL0_pda_en_SHIFT (2U)
9082/*! pda_en - Indicates whether the mode register operation is MRS in PDA mode or not. Note that when
9083 * pba_mode=1, PBA access is initiated instead of PDA access.
9084 * 0b0..MRS
9085 * 0b1..MRS in Per DRAM Addressability
9086 */
9087#define DDRC_MRCTRL0_pda_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_pda_en_SHIFT)) & DDRC_MRCTRL0_pda_en_MASK)
9088#define DDRC_MRCTRL0_sw_init_int_MASK (0x8U)
9089#define DDRC_MRCTRL0_sw_init_int_SHIFT (3U)
9090/*! sw_init_int - Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before
9091 * automatic SDRAM initialization routine or not. For DDR4, this bit can be used to initialize the
9092 * DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit can be used to
9093 * program additional mode registers before automatic SDRAM initialization if necessary. In LPDDR4
9094 * independent channel mode, note that this must be programmed to both channels beforehand. Note that
9095 * this must be cleared to 0 after completing Software operation. Otherwise, SDRAM
9096 * initialization routine will not re-start.
9097 * 0b0..Software intervention is not allowed
9098 * 0b1..Software intervention is allowed
9099 */
9100#define DDRC_MRCTRL0_sw_init_int(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_sw_init_int_SHIFT)) & DDRC_MRCTRL0_sw_init_int_MASK)
9101#define DDRC_MRCTRL0_mr_rank_MASK (0x30U)
9102#define DDRC_MRCTRL0_mr_rank_SHIFT (4U)
9103/*! mr_rank - Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access
9104 * all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which
9105 * implement address mirroring, it may be necessary to access ranks individually. Examples (assume
9106 * DDRC is configured for 4 ranks): 0x1 - select rank 0 only 0x2 - select rank 1 only 0x5 -
9107 * select ranks 0 and 2 0xA - select ranks 1 and 3 0xF - select ranks 0, 1, 2 and 3
9108 */
9109#define DDRC_MRCTRL0_mr_rank(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_rank_SHIFT)) & DDRC_MRCTRL0_mr_rank_MASK)
9110#define DDRC_MRCTRL0_mr_addr_MASK (0xF000U)
9111#define DDRC_MRCTRL0_mr_addr_SHIFT (12U)
9112/*! mr_addr - Address of the mode register that is to be written to.
9113 * 0b0000..MR0
9114 * 0b0001..MR1
9115 * 0b0010..MR2
9116 * 0b0011..MR3
9117 * 0b0100..MR4
9118 * 0b0101..MR5
9119 * 0b0110..MR6
9120 * 0b0111..MR7
9121 */
9122#define DDRC_MRCTRL0_mr_addr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_addr_SHIFT)) & DDRC_MRCTRL0_mr_addr_MASK)
9123#define DDRC_MRCTRL0_pba_mode_MASK (0x40000000U)
9124#define DDRC_MRCTRL0_pba_mode_SHIFT (30U)
9125/*! pba_mode - Indicates whether PBA access is executed. When setting this bit to 1 along with
9126 * setting pda_en to 1, DDRC initiates PBA access instead of PDA access. - 0 - Per DRAM Addressability
9127 * mode - 1 - Per Buffer Addressability mode The completion of PBA access is confirmed by
9128 * MRSTAT.pda_done in the same way as PDA.
9129 */
9130#define DDRC_MRCTRL0_pba_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_pba_mode_SHIFT)) & DDRC_MRCTRL0_pba_mode_MASK)
9131#define DDRC_MRCTRL0_mr_wr_MASK (0x80000000U)
9132#define DDRC_MRCTRL0_mr_wr_SHIFT (31U)
9133/*! mr_wr - Setting this register bit to 1 triggers a mode register read or write operation. When
9134 * the MR operation is complete, the DDRC automatically clears this bit. The other register fields
9135 * of this register must be written in a separate APB transaction, before setting this mr_wr bit.
9136 * It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.
9137 */
9138#define DDRC_MRCTRL0_mr_wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_wr_SHIFT)) & DDRC_MRCTRL0_mr_wr_MASK)
9139/*! @} */
9140
9141/*! @name MRCTRL1 - Mode Register Read/Write Control Register 1 */
9142/*! @{ */
9143#define DDRC_MRCTRL1_mr_data_MASK (0x3FFFFU)
9144#define DDRC_MRCTRL1_mr_data_SHIFT (0U)
9145/*! mr_data - Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. For
9146 * LPDDR2/LPDDR3/LPDDR4, MRCTRL1[15:0] are interpreted as [15:8] MR Address [7:0] MR data for writes,
9147 * don't care for reads. This is 18-bits wide in configurations with DDR4 support and 16-bits in all
9148 * other configurations.
9149 */
9150#define DDRC_MRCTRL1_mr_data(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL1_mr_data_SHIFT)) & DDRC_MRCTRL1_mr_data_MASK)
9151/*! @} */
9152
9153/*! @name MRSTAT - Mode Register Read/Write Status Register */
9154/*! @{ */
9155#define DDRC_MRSTAT_mr_wr_busy_MASK (0x1U)
9156#define DDRC_MRSTAT_mr_wr_busy_SHIFT (0U)
9157/*! mr_wr_busy - The SoC core may initiate a MR write operation only if this signal is low. This
9158 * signal goes high in the clock after the DDRC accepts the MRW/MRR request. It goes low when the
9159 * MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when
9160 * 'MRSTAT.mr_wr_busy' is high.
9161 * 0b0..Indicates that the SoC core can initiate a mode register write operation
9162 * 0b1..Indicates that mode register write operation is in progress
9163 */
9164#define DDRC_MRSTAT_mr_wr_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_mr_wr_busy_SHIFT)) & DDRC_MRSTAT_mr_wr_busy_MASK)
9165#define DDRC_MRSTAT_pda_done_MASK (0x100U)
9166#define DDRC_MRSTAT_pda_done_SHIFT (8U)
9167/*! pda_done - The SoC core may initiate a MR write operation in PDA/PBA mode only if this signal is
9168 * low. This signal goes high when three consecutive MRS commands related to the PDA/PBA mode
9169 * are issued to the SDRAM. This signal goes low when MRCTRL0.pda_en becomes 0. Therefore, it is
9170 * recommended to write MRCTRL0.pda_en to 0 after this signal goes high in order to prepare to
9171 * perform PDA operation next time
9172 * 0b0..Indicates that mode register write operation related to PDA/PBA is in progress or has not started yet.
9173 * 0b1..Indicates that mode register write operation related to PDA/PBA has competed.
9174 */
9175#define DDRC_MRSTAT_pda_done(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_pda_done_SHIFT)) & DDRC_MRSTAT_pda_done_MASK)
9176/*! @} */
9177
9178/*! @name MRCTRL2 - Mode Register Read/Write Control Register 2 */
9179/*! @{ */
9180#define DDRC_MRCTRL2_mr_device_sel_MASK (0xFFFFFFFFU)
9181#define DDRC_MRCTRL2_mr_device_sel_SHIFT (0U)
9182/*! mr_device_sel - Indicates the device(s) to be selected during the MRS that happens in PDA mode.
9183 * Each bit is associated with one device. For example, bit[0] corresponds to Device 0, bit[1] to
9184 * Device 1 etc. A '1' should be programmed to indicate that the MRS command should be applied
9185 * to that device. A '0' indicates that the MRS commands should be skipped for that device.
9186 */
9187#define DDRC_MRCTRL2_mr_device_sel(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL2_mr_device_sel_SHIFT)) & DDRC_MRCTRL2_mr_device_sel_MASK)
9188/*! @} */
9189
9190/*! @name DERATEEN - Temperature Derate Enable Register */
9191/*! @{ */
9192#define DDRC_DERATEEN_derate_enable_MASK (0x1U)
9193#define DDRC_DERATEEN_derate_enable_SHIFT (0U)
9194/*! derate_enable - Enables derating. Present only in designs configured to support
9195 * LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
9196 * 0b0..Timing parameter derating is disabled
9197 * 0b1..Timing parameter derating is enabled using MR4 read value.
9198 */
9199#define DDRC_DERATEEN_derate_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_enable_SHIFT)) & DDRC_DERATEEN_derate_enable_MASK)
9200#define DDRC_DERATEEN_derate_value_MASK (0x2U)
9201#define DDRC_DERATEEN_derate_value_SHIFT (1U)
9202/*! derate_value - Derate value. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
9203 * Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a
9204 * core_ddrc_core_clk period. For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this
9205 * register field should be set to 1; otherwise it should be set to 0.
9206 * 0b0..Derating uses +1
9207 * 0b1..Derating uses +2
9208 */
9209#define DDRC_DERATEEN_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_value_SHIFT)) & DDRC_DERATEEN_derate_value_MASK)
9210#define DDRC_DERATEEN_derate_byte_MASK (0xF0U)
9211#define DDRC_DERATEEN_derate_byte_SHIFT (4U)
9212/*! derate_byte - Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
9213 * Indicates which byte of the MRR data is used for derating. The maximum valid value depends on
9214 * MEMC_DRAM_TOTAL_DATA_WIDTH.
9215 */
9216#define DDRC_DERATEEN_derate_byte(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_byte_SHIFT)) & DDRC_DERATEEN_derate_byte_MASK)
9217#define DDRC_DERATEEN_rc_derate_value_MASK (0x300U)
9218#define DDRC_DERATEEN_rc_derate_value_SHIFT (8U)
9219/*! rc_derate_value - Derate value of tRC for LPDDR4. Present only in designs configured to support
9220 * LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by the
9221 * core_ddrc_core_clk period, and rounding up the next integer.
9222 * 0b00..Derating uses +1
9223 * 0b01..Derating uses +2
9224 * 0b10..Derating uses +3
9225 * 0b11..Derating uses +4
9226 */
9227#define DDRC_DERATEEN_rc_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_rc_derate_value_SHIFT)) & DDRC_DERATEEN_rc_derate_value_MASK)
9228/*! @} */
9229
9230/*! @name DERATEINT - Temperature Derate Interval Register */
9231/*! @{ */
9232#define DDRC_DERATEINT_mr4_read_interval_MASK (0xFFFFFFFFU)
9233#define DDRC_DERATEINT_mr4_read_interval_SHIFT (0U)
9234/*! mr4_read_interval - Interval between two MR4 reads, used to derate the timing parameters.
9235 * Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to
9236 * zero. Unit: DFI clock cycle.
9237 */
9238#define DDRC_DERATEINT_mr4_read_interval(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEINT_mr4_read_interval_SHIFT)) & DDRC_DERATEINT_mr4_read_interval_MASK)
9239/*! @} */
9240
9241/*! @name PWRCTL - Low Power Control Register */
9242/*! @{ */
9243#define DDRC_PWRCTL_selfref_en_MASK (0x1U)
9244#define DDRC_PWRCTL_selfref_en_SHIFT (0U)
9245/*! selfref_en - If true then the DDRC puts the SDRAM into Self Refresh after a programmable number
9246 * of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit
9247 * may be re-programmed during the course of normal operation.
9248 */
9249#define DDRC_PWRCTL_selfref_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_selfref_en_SHIFT)) & DDRC_PWRCTL_selfref_en_MASK)
9250#define DDRC_PWRCTL_powerdown_en_MASK (0x2U)
9251#define DDRC_PWRCTL_powerdown_en_SHIFT (1U)
9252/*! powerdown_en - If true then the DDRC goes into power-down after a programmable number of cycles
9253 * "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). This register bit may be
9254 * re-programmed during the course of normal operation.
9255 */
9256#define DDRC_PWRCTL_powerdown_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_powerdown_en_SHIFT)) & DDRC_PWRCTL_powerdown_en_MASK)
9257#define DDRC_PWRCTL_deeppowerdown_en_MASK (0x4U)
9258#define DDRC_PWRCTL_deeppowerdown_en_SHIFT (2U)
9259/*! deeppowerdown_en - When this is 1, DDRC puts the SDRAM into deep power-down mode when the
9260 * transaction store is empty. This register must be reset to '0' to bring DDRC out of deep power-down
9261 * mode. Controller performs automatic SDRAM initialization on deep power-down exit. Present only
9262 * in designs configured to support mDDR or LPDDR2 or LPDDR3. For
9263 * non-mDDR/non-LPDDR2/non-LPDDR3, this register should not be set to 1. FOR PERFORMANCE ONLY.
9264 */
9265#define DDRC_PWRCTL_deeppowerdown_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_deeppowerdown_en_SHIFT)) & DDRC_PWRCTL_deeppowerdown_en_MASK)
9266#define DDRC_PWRCTL_en_dfi_dram_clk_disable_MASK (0x8U)
9267#define DDRC_PWRCTL_en_dfi_dram_clk_disable_SHIFT (3U)
9268/*! en_dfi_dram_clk_disable - Enable the assertion of dfi_dram_clk_disable whenever a clock is not
9269 * required by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. Assertion of
9270 * dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DDR4, can
9271 * be asserted in following: in Self Refresh in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3,
9272 * can be asserted in following: in Self Refresh in Power Down in Deep Power Down during Normal
9273 * operation (Clock Stop) In LPDDR4, can be asserted in following: in Self Refresh Power Down in
9274 * Power Down during Normal operation (Clock Stop)
9275 */
9276#define DDRC_PWRCTL_en_dfi_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_en_dfi_dram_clk_disable_SHIFT)) & DDRC_PWRCTL_en_dfi_dram_clk_disable_MASK)
9277#define DDRC_PWRCTL_mpsm_en_MASK (0x10U)
9278#define DDRC_PWRCTL_mpsm_en_SHIFT (4U)
9279/*! mpsm_en - When this is 1, the DDRC puts the SDRAM into maximum power saving mode when the
9280 * transaction store is empty. This register must be reset to '0' to bring DDRC out of maximum power
9281 * saving mode. Present only in designs configured to support DDR4. For non-DDR4, this register
9282 * should not be set to 1. Note that MPSM is not supported when using a DDR PHY, if the PHY
9283 * parameter DDRC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to
9284 * toggle. FOR PERFORMANCE ONLY.
9285 */
9286#define DDRC_PWRCTL_mpsm_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_mpsm_en_SHIFT)) & DDRC_PWRCTL_mpsm_en_MASK)
9287#define DDRC_PWRCTL_selfref_sw_MASK (0x20U)
9288#define DDRC_PWRCTL_selfref_sw_SHIFT (5U)
9289/*! selfref_sw - A value of 1 to this register causes system to move to Self Refresh state
9290 * immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software
9291 * Entry/Exit to Self Refresh.
9292 * 0b0..Software Exit from Self Refresh
9293 * 0b1..Software Entry to Self Refresh
9294 */
9295#define DDRC_PWRCTL_selfref_sw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_selfref_sw_SHIFT)) & DDRC_PWRCTL_selfref_sw_MASK)
9296#define DDRC_PWRCTL_stay_in_selfref_MASK (0x40U)
9297#define DDRC_PWRCTL_stay_in_selfref_SHIFT (6U)
9298/*! stay_in_selfref - Self refresh state is an intermediate state to enter to Self refresh power
9299 * down state or exit Self refresh power down state for LPDDR4. This register controls transition
9300 * from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 0 - Allow
9301 * transition from Self refresh state
9302 * 0b0..
9303 * 0b1..
9304 */
9305#define DDRC_PWRCTL_stay_in_selfref(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_stay_in_selfref_SHIFT)) & DDRC_PWRCTL_stay_in_selfref_MASK)
9306/*! @} */
9307
9308/*! @name PWRTMG - Low Power Timing Register */
9309/*! @{ */
9310#define DDRC_PWRTMG_powerdown_to_x32_MASK (0x1FU)
9311#define DDRC_PWRTMG_powerdown_to_x32_SHIFT (0U)
9312/*! powerdown_to_x32 - After this many clocks of the DDRC command channel being idle the DDRC
9313 * automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there
9314 * are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. Unit:
9315 * Multiples of 32 DFI clocks FOR PERFORMANCE ONLY.
9316 */
9317#define DDRC_PWRTMG_powerdown_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_powerdown_to_x32_SHIFT)) & DDRC_PWRTMG_powerdown_to_x32_MASK)
9318#define DDRC_PWRTMG_t_dpd_x4096_MASK (0xFF00U)
9319#define DDRC_PWRTMG_t_dpd_x4096_SHIFT (8U)
9320/*! t_dpd_x4096 - Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as
9321 * mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is
9322 * de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Multiples of 4096 DFI
9323 * clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE
9324 * ONLY.
9325 */
9326#define DDRC_PWRTMG_t_dpd_x4096(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_t_dpd_x4096_SHIFT)) & DDRC_PWRTMG_t_dpd_x4096_MASK)
9327#define DDRC_PWRTMG_selfref_to_x32_MASK (0xFF0000U)
9328#define DDRC_PWRTMG_selfref_to_x32_SHIFT (16U)
9329/*! selfref_to_x32 - After this many clocks of the DDRC command channel being idle the DDRC
9330 * automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there
9331 * are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. Unit:
9332 * Multiples of 32 DFI clocks. FOR PERFORMANCE ONLY.
9333 */
9334#define DDRC_PWRTMG_selfref_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_selfref_to_x32_SHIFT)) & DDRC_PWRTMG_selfref_to_x32_MASK)
9335/*! @} */
9336
9337/*! @name HWLPCTL - Hardware Low Power Control Register */
9338/*! @{ */
9339#define DDRC_HWLPCTL_hw_lp_en_MASK (0x1U)
9340#define DDRC_HWLPCTL_hw_lp_en_SHIFT (0U)
9341/*! hw_lp_en - Enable for Hardware Low Power Interface.
9342 */
9343#define DDRC_HWLPCTL_hw_lp_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_en_SHIFT)) & DDRC_HWLPCTL_hw_lp_en_MASK)
9344#define DDRC_HWLPCTL_hw_lp_exit_idle_en_MASK (0x2U)
9345#define DDRC_HWLPCTL_hw_lp_exit_idle_en_SHIFT (1U)
9346/*! hw_lp_exit_idle_en - When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be
9347 * used to exit from the automatic clock stop, automatic power down or automatic self-refresh
9348 * modes. Note, it will not cause exit of Self-Refresh that was caused by Hardware Low Power
9349 * Interface and/or Software (PWRCTL.selfref_sw).
9350 */
9351#define DDRC_HWLPCTL_hw_lp_exit_idle_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_exit_idle_en_SHIFT)) & DDRC_HWLPCTL_hw_lp_exit_idle_en_MASK)
9352#define DDRC_HWLPCTL_hw_lp_idle_x32_MASK (0xFFF0000U)
9353#define DDRC_HWLPCTL_hw_lp_idle_x32_SHIFT (16U)
9354/*! hw_lp_idle_x32 - Hardware idle period. The cactive_ddrc output is driven low if the DDRC command
9355 * channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The
9356 * DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware
9357 * idle function is disabled when hw_lp_idle_x32=0. Unit: Multiples of 32 DFI clocks. FOR
9358 * PERFORMANCE ONLY.
9359 */
9360#define DDRC_HWLPCTL_hw_lp_idle_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_idle_x32_SHIFT)) & DDRC_HWLPCTL_hw_lp_idle_x32_MASK)
9361/*! @} */
9362
9363/*! @name RFSHCTL0 - Refresh Control Register 0 */
9364/*! @{ */
9365#define DDRC_RFSHCTL0_per_bank_refresh_MASK (0x4U)
9366#define DDRC_RFSHCTL0_per_bank_refresh_SHIFT (2U)
9367/*! per_bank_refresh - Per bank refresh allows traffic to flow to other banks. Per bank refresh is
9368 * not supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices.
9369 * Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
9370 * 0b1..Per bank refresh
9371 * 0b0..All bank refresh
9372 */
9373#define DDRC_RFSHCTL0_per_bank_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_per_bank_refresh_SHIFT)) & DDRC_RFSHCTL0_per_bank_refresh_MASK)
9374#define DDRC_RFSHCTL0_refresh_burst_MASK (0x1F0U)
9375#define DDRC_RFSHCTL0_refresh_burst_SHIFT (4U)
9376/*! refresh_burst - The programmed value + 1 is the number of refresh timeouts that is allowed to
9377 * accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to
9378 * perform a refresh is a one-time penalty that must be paid for each group of refreshes.
9379 * Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings.
9380 * Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases
9381 * the worst-case latency associated with refreshes. - 0 - single refresh - 1 - burst-of-2
9382 * refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to section 3.9 of
9383 * DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not
9384 * per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh
9385 * feature. In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X
9386 * mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care
9387 * must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated
9388 * due to a PHY-initiated update occurring shortly before a refresh burst was due. In this
9389 * situation, the refresh burst will be delayed until the PHY-initiated update is complete.
9390 */
9391#define DDRC_RFSHCTL0_refresh_burst(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_burst_SHIFT)) & DDRC_RFSHCTL0_refresh_burst_MASK)
9392#define DDRC_RFSHCTL0_refresh_to_x32_MASK (0x1F000U)
9393#define DDRC_RFSHCTL0_refresh_to_x32_SHIFT (12U)
9394/*! refresh_to_x32 - If the refresh timer (tRFCnom, also known as tREFI) has expired at least once,
9395 * but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be
9396 * performed. A speculative refresh is a refresh performed at a time when refresh would be
9397 * useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time
9398 * determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since
9399 * the last refresh, then a speculative refresh is performed. Speculative refreshes continues
9400 * successively until there are no refreshes pending or until new reads or writes are issued to the
9401 * DDRC. FOR PERFORMANCE ONLY. Unit: Multiples of 32 DFI clocks.
9402 */
9403#define DDRC_RFSHCTL0_refresh_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_to_x32_SHIFT)) & DDRC_RFSHCTL0_refresh_to_x32_MASK)
9404#define DDRC_RFSHCTL0_refresh_margin_MASK (0xF00000U)
9405#define DDRC_RFSHCTL0_refresh_margin_SHIFT (20U)
9406/*! refresh_margin - Threshold value in number of DFI clock cycles before the critical refresh or
9407 * page timer expires. A critical refresh is to be issued before this threshold is reached. It is
9408 * recommended that this not be changed from the default value, currently shown as 0x2. It must
9409 * always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4,
9410 * internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled
9411 * (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to
9412 * RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 DFI clocks.
9413 */
9414#define DDRC_RFSHCTL0_refresh_margin(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_margin_SHIFT)) & DDRC_RFSHCTL0_refresh_margin_MASK)
9415/*! @} */
9416
9417/*! @name RFSHCTL1 - Refresh Control Register 1 */
9418/*! @{ */
9419#define DDRC_RFSHCTL1_refresh_timer0_start_value_x32_MASK (0xFFFU)
9420#define DDRC_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT (0U)
9421/*! refresh_timer0_start_value_x32 - Refresh timer start for rank 0 (only present in multi-rank
9422 * configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to
9423 * proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples
9424 * of 32 DFI clock cycles. FOR PERFORMANCE ONLY.
9425 */
9426#define DDRC_RFSHCTL1_refresh_timer0_start_value_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT)) & DDRC_RFSHCTL1_refresh_timer0_start_value_x32_MASK)
9427#define DDRC_RFSHCTL1_refresh_timer1_start_value_x32_MASK (0xFFF0000U)
9428#define DDRC_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT (16U)
9429/*! refresh_timer1_start_value_x32 - Refresh timer start for rank 1 (only present in multi-rank
9430 * configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to
9431 * proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples
9432 * of 32 DFI clock cycles. FOR PERFORMANCE ONLY.
9433 */
9434#define DDRC_RFSHCTL1_refresh_timer1_start_value_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT)) & DDRC_RFSHCTL1_refresh_timer1_start_value_x32_MASK)
9435/*! @} */
9436
9437/*! @name RFSHCTL3 - Refresh Control Register 3 */
9438/*! @{ */
9439#define DDRC_RFSHCTL3_dis_auto_refresh_MASK (0x1U)
9440#define DDRC_RFSHCTL3_dis_auto_refresh_SHIFT (0U)
9441/*! dis_auto_refresh - When '1', disable auto-refresh generated by the DDRC. When auto-refresh is
9442 * disabled, the SoC core must generate refreshes using the registers reg_ddrc_rank0_refresh,
9443 * reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis_auto_refresh
9444 * transitions from 0 to 1, any pending refreshes are immediately scheduled by the DDRC. If DDR4
9445 * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is
9446 * not supported, and this bit must be set to '0'. (DDR4 only) If FGR mode is enabled
9447 * (RFSHCTL3.refresh_mode > 0), disable auto-refresh is not supported, and this bit must be set to '0'. This
9448 * register field is changeable on the fly.
9449 */
9450#define DDRC_RFSHCTL3_dis_auto_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_dis_auto_refresh_SHIFT)) & DDRC_RFSHCTL3_dis_auto_refresh_MASK)
9451#define DDRC_RFSHCTL3_refresh_update_level_MASK (0x2U)
9452#define DDRC_RFSHCTL3_refresh_update_level_SHIFT (1U)
9453/*! refresh_update_level - Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that
9454 * the refresh register(s) have been updated. refresh_update_level must not be toggled when the
9455 * DDRC is in reset (core_ddrc_rstn = 0). The refresh register(s) are automatically updated when
9456 * exiting reset.
9457 */
9458#define DDRC_RFSHCTL3_refresh_update_level(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_refresh_update_level_SHIFT)) & DDRC_RFSHCTL3_refresh_update_level_MASK)
9459#define DDRC_RFSHCTL3_refresh_mode_MASK (0x70U)
9460#define DDRC_RFSHCTL3_refresh_mode_SHIFT (4U)
9461/*! refresh_mode - Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x -
9462 * 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 110 - Enable on the fly 4x (not
9463 * supported) - Everything else - reserved Note: Only Fixed 1x mode is supported if
9464 * RFSHCTL3.dis_auto_refresh = 1. Note: The on-the-fly modes are not supported in this version of the DDRC.
9465 * Note: This must be set up while the Controller is in reset or while the Controller is in
9466 * self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic
9467 * register will be supported in future version of the DDRC. Note: This register field has effect only
9468 * if a DDR4 SDRAM device is in use (MSTR.ddr4 = 1).
9469 */
9470#define DDRC_RFSHCTL3_refresh_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_refresh_mode_SHIFT)) & DDRC_RFSHCTL3_refresh_mode_MASK)
9471/*! @} */
9472
9473/*! @name RFSHTMG - Refresh Timing Register */
9474/*! @{ */
9475#define DDRC_RFSHTMG_t_rfc_min_MASK (0x3FFU)
9476#define DDRC_RFSHTMG_t_rfc_min_SHIFT (0U)
9477/*! t_rfc_min - tRFC (min): Minimum time from refresh to refresh or activate. When the controller is
9478 * operating in 1:1 mode, t_rfc_min should be set to RoundUp(tRFCmin/tCK). When the controller
9479 * is operating in 1:2 mode, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In
9480 * LPDDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations
9481 * is equal to tRFCab - if using per-bank refreshes, the tRFCmin value in the above equations is
9482 * equal to tRFCpb In DDR4 mode, the tRFCmin value in the above equations is different depending
9483 * on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the
9484 * appropriate value from the spec based on the 'refresh_mode' and the device density that is used.
9485 * Unit: Clocks.
9486 */
9487#define DDRC_RFSHTMG_t_rfc_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_t_rfc_min_SHIFT)) & DDRC_RFSHTMG_t_rfc_min_MASK)
9488#define DDRC_RFSHTMG_lpddr3_trefbw_en_MASK (0x8000U)
9489#define DDRC_RFSHTMG_lpddr3_trefbw_en_SHIFT (15U)
9490/*! lpddr3_trefbw_en - Used only when LPDDR3 memory type is connected. Should only be changed when
9491 * DDRC is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3
9492 * devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: - 0 - tREFBW
9493 * parameter not used - 1 - tREFBW parameter used
9494 */
9495#define DDRC_RFSHTMG_lpddr3_trefbw_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_lpddr3_trefbw_en_SHIFT)) & DDRC_RFSHTMG_lpddr3_trefbw_en_MASK)
9496#define DDRC_RFSHTMG_t_rfc_nom_x32_MASK (0xFFF0000U)
9497#define DDRC_RFSHTMG_t_rfc_nom_x32_SHIFT (16U)
9498/*! t_rfc_nom_x32 - tREFI: Average time interval between refreshes per rank (Specification: 7.8us
9499 * for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). For
9500 * LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register
9501 * should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this
9502 * register should be set to tREFIpb When the controller is operating in 1:2 frequency ratio mode,
9503 * program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI value is different depending
9504 * on the refresh mode. The user should program the appropriate value from the spec based on the
9505 * value programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be
9506 * greater than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater than 0x1. - Non-DDR4 or
9507 * DDR4 Fixed 1x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0xFFE. - DDR4 Fixed
9508 * 2x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x7FF. - DDR4 Fixed 4x mode:
9509 * RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x3FF. Unit: Multiples of 32 clocks.
9510 */
9511#define DDRC_RFSHTMG_t_rfc_nom_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_t_rfc_nom_x32_SHIFT)) & DDRC_RFSHTMG_t_rfc_nom_x32_MASK)
9512/*! @} */
9513
9514/*! @name INIT0 - SDRAM Initialization Register 0 */
9515/*! @{ */
9516#define DDRC_INIT0_pre_cke_x1024_MASK (0xFFFU)
9517#define DDRC_INIT0_pre_cke_x1024_SHIFT (0U)
9518/*! pre_cke_x1024 - Cycles to wait after reset before driving CKE high to start the SDRAM
9519 * initialization sequence. Unit: 1024 DFI clock cycles. DDR2 specifications typically require this to be
9520 * programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2
9521 * ms (min) When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC
9522 * spec value divided by 2, and round it up to the next integer value. For DDR3/DDR4 RDIMMs, this
9523 * should include the time needed to satisfy tSTAB
9524 */
9525#define DDRC_INIT0_pre_cke_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_pre_cke_x1024_SHIFT)) & DDRC_INIT0_pre_cke_x1024_MASK)
9526#define DDRC_INIT0_post_cke_x1024_MASK (0x3FF0000U)
9527#define DDRC_INIT0_post_cke_x1024_SHIFT (16U)
9528/*! post_cke_x1024 - Cycles to wait after driving CKE high to start the SDRAM initialization
9529 * sequence. Unit: 1024 DFI clock cycles. DDR2 typically requires a 400 ns delay, requiring this value
9530 * to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be
9531 * programmed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us.
9532 * When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec
9533 * value divided by 2, and round it up to the next integer value.
9534 */
9535#define DDRC_INIT0_post_cke_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_post_cke_x1024_SHIFT)) & DDRC_INIT0_post_cke_x1024_MASK)
9536#define DDRC_INIT0_skip_dram_init_MASK (0xC0000000U)
9537#define DDRC_INIT0_skip_dram_init_SHIFT (30U)
9538/*! skip_dram_init - If lower bit is enabled the SDRAM initialization routine is skipped. The upper
9539 * bit decides what state the controller starts up in when reset is removed - 00 - SDRAM
9540 * Intialization routine is run after power-up - 01 - SDRAM Initialization routine is skipped after
9541 * power-up. Controller starts up in Normal Mode - 11 - SDRAM Initialization routine is skipped after
9542 * power-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Initialization routine is run
9543 * after power-up.
9544 * 0b00..SDRAM Initialization routine is run after power-up
9545 * 0b01..SDRAM Initialization routine is skipped after power-up
9546 * 0b10..SDRAM Initialization routine is run after power-up
9547 * 0b11..SDRAM Initialization routine is skipped after power-up
9548 */
9549#define DDRC_INIT0_skip_dram_init(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_skip_dram_init_SHIFT)) & DDRC_INIT0_skip_dram_init_MASK)
9550/*! @} */
9551
9552/*! @name INIT1 - SDRAM Initialization Register 1 */
9553/*! @{ */
9554#define DDRC_INIT1_pre_ocd_x32_MASK (0xFU)
9555#define DDRC_INIT1_pre_ocd_x32_SHIFT (0U)
9556/*! pre_ocd_x32 - Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a
9557 * global timer that pulses every 32 DFI clock cycles. There is no known specific requirement for
9558 * this; it may be set to zero.
9559 */
9560#define DDRC_INIT1_pre_ocd_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_pre_ocd_x32_SHIFT)) & DDRC_INIT1_pre_ocd_x32_MASK)
9561#define DDRC_INIT1_dram_rstn_x1024_MASK (0x1FF0000U)
9562#define DDRC_INIT1_dram_rstn_x1024_SHIFT (16U)
9563/*! dram_rstn_x1024 - Number of cycles to assert SDRAM reset signal during init sequence. This is
9564 * only present for designs supporting DDR3, DDR4 or LPDDR4 devices. For use with a DDR PHY, this
9565 * should be set to a minimum of 1. When the controller is operating in 1:2 frequency ratio mode,
9566 * program this to JEDEC spec value divided by 2, and round it up to the next integer value.
9567 * Unit: 1024 DFI clock cycles.
9568 */
9569#define DDRC_INIT1_dram_rstn_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_dram_rstn_x1024_SHIFT)) & DDRC_INIT1_dram_rstn_x1024_MASK)
9570/*! @} */
9571
9572/*! @name INIT2 - SDRAM Initialization Register 2 */
9573/*! @{ */
9574#define DDRC_INIT2_min_stable_clock_x1_MASK (0xFU)
9575#define DDRC_INIT2_min_stable_clock_x1_SHIFT (0U)
9576/*! min_stable_clock_x1 - Time to wait after the first CKE high, tINIT2. Present only in designs
9577 * configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 5 x tCK delay. When the
9578 * controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by
9579 * 2, and round it up to the next integer value. Unit: DFI clock cycles.
9580 */
9581#define DDRC_INIT2_min_stable_clock_x1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_min_stable_clock_x1_SHIFT)) & DDRC_INIT2_min_stable_clock_x1_MASK)
9582#define DDRC_INIT2_idle_after_reset_x32_MASK (0xFF00U)
9583#define DDRC_INIT2_idle_after_reset_x32_SHIFT (8U)
9584/*! idle_after_reset_x32 - Idle time after the reset command, tINIT4. Present only in designs
9585 * configured to support LPDDR2. When the controller is operating in 1:2 frequency ratio mode, program
9586 * this to JEDEC spec value divided by 2, and round it up to the next integer value. Unit: 32 DFI
9587 * clock cycles.
9588 */
9589#define DDRC_INIT2_idle_after_reset_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_idle_after_reset_x32_SHIFT)) & DDRC_INIT2_idle_after_reset_x32_MASK)
9590/*! @} */
9591
9592/*! @name INIT3 - SDRAM Initialization Register 3 */
9593/*! @{ */
9594#define DDRC_INIT3_emr_MASK (0xFFFFU)
9595#define DDRC_INIT3_emr_SHIFT (0U)
9596/*! emr - DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this
9597 * register is ignored. The DDRC sets those bits appropriately. DDR3/DDR4: Value to write to MR1
9598 * register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by
9599 * the DDRC during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 -
9600 * Value to write to MR2 register
9601 */
9602#define DDRC_INIT3_emr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_emr_SHIFT)) & DDRC_INIT3_emr_MASK)
9603#define DDRC_INIT3_mr_MASK (0xFFFF0000U)
9604#define DDRC_INIT3_mr_SHIFT (16U)
9605/*! mr - DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The
9606 * DDRC sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to
9607 * write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 register
9608 */
9609#define DDRC_INIT3_mr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_mr_SHIFT)) & DDRC_INIT3_mr_MASK)
9610/*! @} */
9611
9612/*! @name INIT4 - SDRAM Initialization Register 4 */
9613/*! @{ */
9614#define DDRC_INIT4_emr3_MASK (0xFFFFU)
9615#define DDRC_INIT4_emr3_SHIFT (0U)
9616/*! emr3 - DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register
9617 * mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 register
9618 */
9619#define DDRC_INIT4_emr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_emr3_SHIFT)) & DDRC_INIT4_emr3_MASK)
9620#define DDRC_INIT4_emr2_MASK (0xFFFF0000U)
9621#define DDRC_INIT4_emr2_SHIFT (16U)
9622/*! emr2 - DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register
9623 * LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unused
9624 */
9625#define DDRC_INIT4_emr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_emr2_SHIFT)) & DDRC_INIT4_emr2_MASK)
9626/*! @} */
9627
9628/*! @name INIT5 - SDRAM Initialization Register 5 */
9629/*! @{ */
9630#define DDRC_INIT5_max_auto_init_x1024_MASK (0x3FFU)
9631#define DDRC_INIT5_max_auto_init_x1024_SHIFT (0U)
9632/*! max_auto_init_x1024 - Maximum duration of the auto initialization, tINIT5. Present only in
9633 * designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 10 us. Unit: 1024 DFI
9634 * clock cycles.
9635 */
9636#define DDRC_INIT5_max_auto_init_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_max_auto_init_x1024_SHIFT)) & DDRC_INIT5_max_auto_init_x1024_MASK)
9637#define DDRC_INIT5_dev_zqinit_x32_MASK (0xFF0000U)
9638#define DDRC_INIT5_dev_zqinit_x32_SHIFT (16U)
9639/*! dev_zqinit_x32 - ZQ initial calibration, tZQINIT. Present only in designs configured to support
9640 * DDR3 or DDR4 or LPDDR2/LPDDR3. DDR3 typically requires 512 SDRAM clock cycles. DDR4 requires
9641 * 1024 SDRAM clock cycles. LPDDR2/LPDDR3 requires 1 us. When the controller is operating in 1:2
9642 * frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the
9643 * next integer value. Unit: 32 DFI clock cycles.
9644 */
9645#define DDRC_INIT5_dev_zqinit_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_dev_zqinit_x32_SHIFT)) & DDRC_INIT5_dev_zqinit_x32_MASK)
9646/*! @} */
9647
9648/*! @name INIT6 - SDRAM Initialization Register 6 */
9649/*! @{ */
9650#define DDRC_INIT6_mr5_MASK (0xFFFFU)
9651#define DDRC_INIT6_mr5_SHIFT (0U)
9652/*! mr5 - DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.
9653 */
9654#define DDRC_INIT6_mr5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_mr5_SHIFT)) & DDRC_INIT6_mr5_MASK)
9655#define DDRC_INIT6_mr4_MASK (0xFFFF0000U)
9656#define DDRC_INIT6_mr4_SHIFT (16U)
9657/*! mr4 - DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.
9658 */
9659#define DDRC_INIT6_mr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_mr4_SHIFT)) & DDRC_INIT6_mr4_MASK)
9660/*! @} */
9661
9662/*! @name INIT7 - SDRAM Initialization Register 7 */
9663/*! @{ */
9664#define DDRC_INIT7_mr6_MASK (0xFFFF0000U)
9665#define DDRC_INIT7_mr6_SHIFT (16U)
9666/*! mr6 - DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.
9667 */
9668#define DDRC_INIT7_mr6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT7_mr6_SHIFT)) & DDRC_INIT7_mr6_MASK)
9669/*! @} */
9670
9671/*! @name DIMMCTL - DIMM Control Register */
9672/*! @{ */
9673#define DDRC_DIMMCTL_dimm_stagger_cs_en_MASK (0x1U)
9674#define DDRC_DIMMCTL_dimm_stagger_cs_en_SHIFT (0U)
9675/*! dimm_stagger_cs_en - Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and
9676 * LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs.
9677 * Even if this bit is set it does not take care of software driven MR commands (via
9678 * MRCTRL0/MRCTRL1), where software is responsible to send them to separate ranks as appropriate.
9679 * 0b0..Do not stagger accesses
9680 * 0b1..(non-DDR4) Send all commands to even and odd ranks separately
9681 * 0b1..(DDR4) Send MRS commands to each ranks separately
9682 */
9683#define DDRC_DIMMCTL_dimm_stagger_cs_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_stagger_cs_en_SHIFT)) & DDRC_DIMMCTL_dimm_stagger_cs_en_MASK)
9684#define DDRC_DIMMCTL_dimm_addr_mirr_en_MASK (0x2U)
9685#define DDRC_DIMMCTL_dimm_addr_mirr_en_SHIFT (1U)
9686/*! dimm_addr_mirr_en - Address Mirroring Enable (for multi-rank UDIMM implementations and
9687 * multi-rank DDR4 RDIMM/LRDIMM implementations). Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address
9688 * mirroring for odd ranks, which means that the following address, bank address and bank group
9689 * bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for
9690 * the DDR4. Setting this bit ensures that, for mode register accesses during the automatic
9691 * initialization routine, these bits are swapped within the DDRC to compensate for this
9692 * UDIMM/RDIMM/LRDIMM swapping. In addition to the automatic initialization routine, in case of DDR4
9693 * UDIMM/RDIMM/LRDIMM, they are swapped during the automatic MRS access to enable/disable of a particular
9694 * DDR4 feature. Note: This has no effect on the address of any other memory accesses, or of
9695 * software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4
9696 * SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0
9697 * because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1.
9698 * 0b0..Do not implement address mirroring
9699 * 0b1..For odd ranks, implement address mirroring for MRS commands to during initialization and for any
9700 * automatic DDR4 MRS commands (to be used if UDIMM/RDIMM/LRDIMM implements address mirroring)
9701 */
9702#define DDRC_DIMMCTL_dimm_addr_mirr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_addr_mirr_en_SHIFT)) & DDRC_DIMMCTL_dimm_addr_mirr_en_MASK)
9703#define DDRC_DIMMCTL_dimm_output_inv_en_MASK (0x4U)
9704#define DDRC_DIMMCTL_dimm_output_inv_en_SHIFT (2U)
9705/*! dimm_output_inv_en - Output Inversion Enable (for DDR4 RDIMM/LRDIMM implementations only). DDR4
9706 * RDIMM/LRDIMM implements the Output Inversion feature by default, which means that the
9707 * following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13,
9708 * A17, BA0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the
9709 * DDRC during the automatic initialization routine and enabling of a particular DDR4 feature,
9710 * separate A-side and B-side mode register accesses are generated. For B-side mode register
9711 * accesses, these bits are inverted within the DDRC to compensate for this RDIMM/LRDIMM inversion. It
9712 * is recommended to set this bit always, if using DDR4 RDIMMs/LRDIMMs. Note: This has no effect
9713 * on the address of any other memory accesses, or of software-driven mode register accesses.
9714 * 0b0..Do not implement output inversion for B-side DRAMs.
9715 * 0b1..Implement output inversion for B-side DRAMs.
9716 */
9717#define DDRC_DIMMCTL_dimm_output_inv_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_output_inv_en_SHIFT)) & DDRC_DIMMCTL_dimm_output_inv_en_MASK)
9718#define DDRC_DIMMCTL_mrs_a17_en_MASK (0x8U)
9719#define DDRC_DIMMCTL_mrs_a17_en_SHIFT (3U)
9720/*! mrs_a17_en - Enable for A17 bit of MRS command. A17 bit of the mode register address is
9721 * specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs
9722 * which do not have A17 are attached and the Output Inversion are enabled, this must be set to
9723 * 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on
9724 * the address of any other memory accesses, or of software-driven mode register accesses.
9725 * 0b0..Disabled
9726 * 0b1..Enabled
9727 */
9728#define DDRC_DIMMCTL_mrs_a17_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_mrs_a17_en_SHIFT)) & DDRC_DIMMCTL_mrs_a17_en_MASK)
9729#define DDRC_DIMMCTL_mrs_bg1_en_MASK (0x10U)
9730#define DDRC_DIMMCTL_mrs_bg1_en_SHIFT (4U)
9731/*! mrs_bg1_en - Enable for BG1 bit of MRS command. BG1 bit of the mode register address is
9732 * specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs
9733 * which do not have BG1 are attached and both the CA parity and the Output Inversion are
9734 * enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note:
9735 * This has no effect on the address of any other memory accesses, or of software-driven mode
9736 * register accesses. If address mirroring is enabled, this is applied to BG1 of even ranks and BG0
9737 * of odd ranks.
9738 * 0b0..Disabled
9739 * 0b1..Enabled
9740 */
9741#define DDRC_DIMMCTL_mrs_bg1_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_mrs_bg1_en_SHIFT)) & DDRC_DIMMCTL_mrs_bg1_en_MASK)
9742#define DDRC_DIMMCTL_dimm_dis_bg_mirroring_MASK (0x20U)
9743#define DDRC_DIMMCTL_dimm_dis_bg_mirroring_SHIFT (5U)
9744/*! dimm_dis_bg_mirroring - Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and
9745 * BG1 are NOT swapped even if Address Mirroring is enabled. This will be required for DDR4 DIMMs
9746 * with x16 devices.
9747 * 0b0..BG0 and BG1 are swapped if address mirroring is enabled.
9748 * 0b1..BG0 and BG1 are NOT swapped.
9749 */
9750#define DDRC_DIMMCTL_dimm_dis_bg_mirroring(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_dis_bg_mirroring_SHIFT)) & DDRC_DIMMCTL_dimm_dis_bg_mirroring_MASK)
9751#define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_MASK (0x40U)
9752#define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT (6U)
9753/*! lrdimm_bcom_cmd_prot - Protects the timing restrictions (tBCW/tMRC) between consecutive BCOM
9754 * commands defined in the Data Buffer specification. When using DDR4 LRDIMM, this bit must be set
9755 * to 1. Otherwise, this bit must be set to 0.
9756 */
9757#define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT)) & DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_MASK)
9758/*! @} */
9759
9760/*! @name RANKCTL - Rank Control Register */
9761/*! @{ */
9762#define DDRC_RANKCTL_max_rank_rd_MASK (0xFU)
9763#define DDRC_RANKCTL_max_rank_rd_SHIFT (0U)
9764/*! max_rank_rd - Only present for multi-rank configurations. Background: Reads to the same rank can
9765 * be performed back-to-back. Reads to different ranks require additional gap dictated by the
9766 * register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus contention as well as to
9767 * give PHY enough time to switch the delay when changing ranks. The DDRC arbitrates for bus
9768 * access on a cycle-by-cycle basis; therefore after a read is scheduled, there are few clock cycles
9769 * (determined by the value on RANKCTL.diff_rank_rd_gap register) in which only reads from the
9770 * same rank are eligible to be scheduled. This prevents reads from other ranks from having fair
9771 * access to the data bus. This parameter represents the maximum number of reads that can be
9772 * scheduled consecutively to the same rank. After this number is reached, a delay equal to
9773 * RANKCTL.diff_rank_rd_gap is inserted by the scheduler to allow all ranks a fair opportunity to be
9774 * scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness. This
9775 * feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on
9776 * the same rank as long as commands are available for it. Minimum programmable value is 0 (feature
9777 * disabled) and maximum programmable value is 0xF. FOR PERFORMANCE ONLY.
9778 */
9779#define DDRC_RANKCTL_max_rank_rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_max_rank_rd_SHIFT)) & DDRC_RANKCTL_max_rank_rd_MASK)
9780#define DDRC_RANKCTL_diff_rank_rd_gap_MASK (0xF0U)
9781#define DDRC_RANKCTL_diff_rank_rd_gap_SHIFT (4U)
9782/*! diff_rank_rd_gap - Only present for multi-rank configurations. Indicates the number of clocks of
9783 * gap in data responses when performing consecutive reads to different ranks. This is used to
9784 * switch the delays in the PHY to match the rank requirements. This value should consider both
9785 * PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for
9786 * value of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased
9787 * by 1. If read postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT
9788 * requirement: The value programmed in this register takes care of the ODT switch off timing requirement
9789 * when switching ranks during reads. When the controller is operating in 1:1 mode, program this
9790 * to the larger of PHY requirement or ODT requirement. When the controller is operating in 1:2
9791 * mode, program this to the larger value divided by two and round it up to the next integer.
9792 * Note that, if using DDR4-LRDIMM, refer to TRDRD timing requirements in JEDEC DDR4 Data Buffer
9793 * (DDR4DB01) Specification.
9794 */
9795#define DDRC_RANKCTL_diff_rank_rd_gap(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_diff_rank_rd_gap_SHIFT)) & DDRC_RANKCTL_diff_rank_rd_gap_MASK)
9796#define DDRC_RANKCTL_diff_rank_wr_gap_MASK (0xF00U)
9797#define DDRC_RANKCTL_diff_rank_wr_gap_SHIFT (8U)
9798/*! diff_rank_wr_gap - Only present for multi-rank configurations. Indicates the number of clocks of
9799 * gap in data responses when performing consecutive writes to different ranks. This is used to
9800 * switch the delays in the PHY to match the rank requirements. This value should consider both
9801 * PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for
9802 * value of tphy_wrcsgap) If CRC feature is enabled, should be increased by 1. If write preamble
9803 * is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If write postamble is set to
9804 * 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed in this
9805 * register takes care of the ODT switch off timing requirement when switching ranks during writes.
9806 * For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 When the controller is operating in
9807 * 1:1 mode, program this to the larger of PHY requirement or ODT requirement. When the
9808 * controller is operating in 1:2 mode, program this to the larger value divided by two and round it up to
9809 * the next integer. Note that, if using DDR4-LRDIMM, refer to TWRWR timing requirements in
9810 * JEDEC DDR4 Data Buffer (DDR4DB01) Specification.
9811 */
9812#define DDRC_RANKCTL_diff_rank_wr_gap(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_diff_rank_wr_gap_SHIFT)) & DDRC_RANKCTL_diff_rank_wr_gap_MASK)
9813/*! @} */
9814
9815/*! @name DRAMTMG0 - SDRAM Timing Register 0 */
9816/*! @{ */
9817#define DDRC_DRAMTMG0_t_ras_min_MASK (0x3FU)
9818#define DDRC_DRAMTMG0_t_ras_min_SHIFT (0U)
9819/*! t_ras_min - tRAS(min): Minimum time between activate and precharge to the same bank. When the
9820 * controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2. No rounding
9821 * up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode,
9822 * program this to (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks
9823 */
9824#define DDRC_DRAMTMG0_t_ras_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_ras_min_SHIFT)) & DDRC_DRAMTMG0_t_ras_min_MASK)
9825#define DDRC_DRAMTMG0_t_ras_max_MASK (0x7F00U)
9826#define DDRC_DRAMTMG0_t_ras_max_SHIFT (8U)
9827/*! t_ras_max - tRAS(max): Maximum time between activate and precharge to same bank. This is the
9828 * maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid.
9829 * When the controller is operating in 1:2 frequency ratio mode, program this to (tRAS(max)-1)/2.
9830 * No rounding up. Unit: Multiples of 1024 clocks.
9831 */
9832#define DDRC_DRAMTMG0_t_ras_max(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_ras_max_SHIFT)) & DDRC_DRAMTMG0_t_ras_max_MASK)
9833#define DDRC_DRAMTMG0_t_faw_MASK (0x3F0000U)
9834#define DDRC_DRAMTMG0_t_faw_SHIFT (16U)
9835/*! t_faw - tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank
9836 * design, at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller
9837 * is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next
9838 * integer value. In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency
9839 * mode. Unit: Clocks
9840 */
9841#define DDRC_DRAMTMG0_t_faw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_faw_SHIFT)) & DDRC_DRAMTMG0_t_faw_MASK)
9842#define DDRC_DRAMTMG0_wr2pre_MASK (0x7F000000U)
9843#define DDRC_DRAMTMG0_wr2pre_SHIFT (24U)
9844/*! wr2pre - Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL
9845 * + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower
9846 * frequencies where: - WL = write latency - BL = burst length. This must match the value programmed in
9847 * the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present.
9848 * - tWR = Write recovery time. This comes directly from the SDRAM specification. Add one extra
9849 * cycle for LPDDR2/LPDDR3/LPDDR4 for this parameter. When the controller is operating in 1:2
9850 * frequency ratio mode, 1T mode, divide the above value by 2. No rounding up. When the controller
9851 * is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, divide the above value by 2
9852 * and round it up to the next integer value. Note that, depending on the PHY, if using LRDIMM, it
9853 * may be necessary to adjust the value of this parameter to compensate for the extra cycle of
9854 * latency through the LRDIMM.
9855 */
9856#define DDRC_DRAMTMG0_wr2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_wr2pre_SHIFT)) & DDRC_DRAMTMG0_wr2pre_MASK)
9857/*! @} */
9858
9859/*! @name DRAMTMG1 - SDRAM Timing Register 1 */
9860/*! @{ */
9861#define DDRC_DRAMTMG1_t_rc_MASK (0x7FU)
9862#define DDRC_DRAMTMG1_t_rc_SHIFT (0U)
9863/*! t_rc - tRC: Minimum time between activates to same bank. When the controller is operating in 1:2
9864 * frequency ratio mode, program this to (tRC/2) and round up to next integer value. Unit:
9865 * Clocks.
9866 */
9867#define DDRC_DRAMTMG1_t_rc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_t_rc_SHIFT)) & DDRC_DRAMTMG1_t_rc_MASK)
9868#define DDRC_DRAMTMG1_rd2pre_MASK (0x3F00U)
9869#define DDRC_DRAMTMG1_rd2pre_SHIFT (8U)
9870/*! rd2pre - tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP,
9871 * 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of following two equations: tAL + max (tRTP, 4)
9872 * or, RL + BL/2 - tRP (*). - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4:
9873 * LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4
9874 * - LPDDR4: BL/2 + max(tRTP,8) - 8 (*) When both DDR4 SDRAM and ST-MRAM are used simultaneously,
9875 * use SDRAM's tRP value for calculation. When the controller is operating in 1:2 mode, 1T mode,
9876 * divide the above value by 2. No rounding up. When the controller is operating in 1:2 mode, 2T
9877 * mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.
9878 * Unit: Clocks.
9879 */
9880#define DDRC_DRAMTMG1_rd2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_rd2pre_SHIFT)) & DDRC_DRAMTMG1_rd2pre_MASK)
9881#define DDRC_DRAMTMG1_t_xp_MASK (0x1F0000U)
9882#define DDRC_DRAMTMG1_t_xp_SHIFT (16U)
9883/*! t_xp - tXP: Minimum time after power-down exit to any operation. For DDR3, this should be
9884 * programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used,
9885 * set to (tXP+PL) instead. When the controller is operating in 1:2 frequency ratio mode, program
9886 * this to (tXP/2) and round it up to the next integer value. Units: Clocks
9887 */
9888#define DDRC_DRAMTMG1_t_xp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_t_xp_SHIFT)) & DDRC_DRAMTMG1_t_xp_MASK)
9889/*! @} */
9890
9891/*! @name DRAMTMG2 - SDRAM Timing Register 2 */
9892/*! @{ */
9893#define DDRC_DRAMTMG2_wr2rd_MASK (0x3FU)
9894#define DDRC_DRAMTMG2_wr2rd_SHIFT (0U)
9895/*! wr2rd - DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from
9896 * write command to read command for same bank group. In others, minimum time from write command to
9897 * read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and
9898 * global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL
9899 * = burst length. This must match the value programmed in the BL bit of the mode register to
9900 * the SDRAM - tWTR_L = internal write to read command delay for same bank group. This comes
9901 * directly from the SDRAM specification. - tWTR = internal write to read command delay. This comes
9902 * directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation.
9903 * When the controller is operating in 1:2 mode, divide the value calculated using the above
9904 * equation by 2, and round it up to next integer.
9905 */
9906#define DDRC_DRAMTMG2_wr2rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_wr2rd_SHIFT)) & DDRC_DRAMTMG2_wr2rd_MASK)
9907#define DDRC_DRAMTMG2_rd2wr_MASK (0x3F00U)
9908#define DDRC_DRAMTMG2_rd2wr_SHIFT (8U)
9909/*! rd2wr - DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL
9910 * + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK)
9911 * + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) +
9912 * RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command.
9913 * Include time for bus turnaround and all per-bank, per-rank, and global constraints. Please see
9914 * the relevant PHY databook for details of what should be included here. Unit: Clocks. Where: -
9915 * WL = write latency - BL = burst length. This must match the value programmed in the BL bit of
9916 * the mode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBLE = write
9917 * preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to
9918 * LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated
9919 * tDQSCKmax should be used. When the controller is operating in 1:2 frequency ratio mode, divide the
9920 * value calculated using the above equation by 2, and round it up to next integer. Note that,
9921 * depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter
9922 * to compensate for the extra cycle of latency through the LRDIMM.
9923 */
9924#define DDRC_DRAMTMG2_rd2wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_rd2wr_SHIFT)) & DDRC_DRAMTMG2_rd2wr_MASK)
9925#define DDRC_DRAMTMG2_read_latency_MASK (0x3F0000U)
9926#define DDRC_DRAMTMG2_read_latency_SHIFT (16U)
9927/*! read_latency - Set to RL Time from read command to read data on SDRAM interface. This must be
9928 * set to RL. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust
9929 * the value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When
9930 * the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the
9931 * above equation by 2, and round it up to next integer. This register field is not required for
9932 * DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in
9933 * DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
9934 */
9935#define DDRC_DRAMTMG2_read_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_read_latency_SHIFT)) & DDRC_DRAMTMG2_read_latency_MASK)
9936#define DDRC_DRAMTMG2_write_latency_MASK (0x3F000000U)
9937#define DDRC_DRAMTMG2_write_latency_SHIFT (24U)
9938/*! write_latency - Set to WL Time from write command to write data on SDRAM interface. This must be
9939 * set to WL. For mDDR, it should normally be set to 1. Note that, depending on the PHY, if
9940 * using RDIMM/LRDIMM, it may be necessary to adjust the value of WL to compensate for the extra
9941 * cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio
9942 * mode, divide the value calculated using the above equation by 2, and round it up to next
9943 * integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set),
9944 * as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those
9945 * protocols Unit: clocks
9946 */
9947#define DDRC_DRAMTMG2_write_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_write_latency_SHIFT)) & DDRC_DRAMTMG2_write_latency_MASK)
9948/*! @} */
9949
9950/*! @name DRAMTMG3 - SDRAM Timing Register 3 */
9951/*! @{ */
9952#define DDRC_DRAMTMG3_t_mod_MASK (0x3FFU)
9953#define DDRC_DRAMTMG3_t_mod_SHIFT (0U)
9954/*! t_mod - tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and
9955 * following non-load mode command. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead.
9956 * Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to
9957 * next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using
9958 * RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this parameter to
9959 * compensate for the extra cycle of latency applied to mode register writes by the RDIMM/LRDIMM chip.
9960 * Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller
9961 * is operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if
9962 * controller is operating in 1:2 frequency ratio mode.
9963 */
9964#define DDRC_DRAMTMG3_t_mod(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mod_SHIFT)) & DDRC_DRAMTMG3_t_mod_MASK)
9965#define DDRC_DRAMTMG3_t_mrd_MASK (0x3F000U)
9966#define DDRC_DRAMTMG3_t_mrd_SHIFT (12U)
9967/*! t_mrd - tMRD: Cycles to wait after a mode register write or read. Depending on the connected
9968 * SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any command DDR3/4: Time from MRS to MRS
9969 * command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command. When the controller is
9970 * operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer
9971 * value. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead.
9972 */
9973#define DDRC_DRAMTMG3_t_mrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mrd_SHIFT)) & DDRC_DRAMTMG3_t_mrd_MASK)
9974#define DDRC_DRAMTMG3_t_mrw_MASK (0x3FF00000U)
9975#define DDRC_DRAMTMG3_t_mrw_SHIFT (20U)
9976/*! t_mrw - Time to wait after a mode register write or read (MRW or MRR). Present only in designs
9977 * configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3
9978 * typically requires value of 10. LPDDR4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2,
9979 * this register is used for the time from a MRW/MRR to all other commands. When the controller
9980 * is operating in 1:2 frequency ratio mode, program this to the above values divided by 2 and
9981 * round it up to the next integer value. For LDPDR3, this register is used for the time from a
9982 * MRW/MRR to a MRW/MRR.
9983 */
9984#define DDRC_DRAMTMG3_t_mrw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mrw_SHIFT)) & DDRC_DRAMTMG3_t_mrw_MASK)
9985/*! @} */
9986
9987/*! @name DRAMTMG4 - SDRAM Timing Register 4 */
9988/*! @{ */
9989#define DDRC_DRAMTMG4_t_rp_MASK (0x1FU)
9990#define DDRC_DRAMTMG4_t_rp_SHIFT (0U)
9991/*! t_rp - tRP: Minimum time from precharge to activate of same bank. When the controller is
9992 * operating in 1:1 frequency ratio mode, t_rp should be set to RoundUp(tRP/tCK). When the controller is
9993 * operating in 1:2 frequency ratio mode, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) +
9994 * 1. When the controller is operating in 1:2 frequency ratio mode in LPDDR4, t_rp should be set
9995 * to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
9996 */
9997#define DDRC_DRAMTMG4_t_rp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rp_SHIFT)) & DDRC_DRAMTMG4_t_rp_MASK)
9998#define DDRC_DRAMTMG4_t_rrd_MASK (0xF00U)
9999#define DDRC_DRAMTMG4_t_rrd_SHIFT (8U)
10000/*! t_rrd - DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank
10001 * group. Others: tRRD: Minimum time between activates from bank "a" to bank "b" When the controller
10002 * is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or tRRD/2) and round it
10003 * up to the next integer value. Unit: Clocks.
10004 */
10005#define DDRC_DRAMTMG4_t_rrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rrd_SHIFT)) & DDRC_DRAMTMG4_t_rrd_MASK)
10006#define DDRC_DRAMTMG4_t_ccd_MASK (0xF0000U)
10007#define DDRC_DRAMTMG4_t_ccd_SHIFT (16U)
10008/*! t_ccd - DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank
10009 * group. Others: tCCD: This is the minimum time between two reads or two writes. When the
10010 * controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it
10011 * up to the next integer value. Unit: clocks.
10012 */
10013#define DDRC_DRAMTMG4_t_ccd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_ccd_SHIFT)) & DDRC_DRAMTMG4_t_ccd_MASK)
10014#define DDRC_DRAMTMG4_t_rcd_MASK (0x1F000000U)
10015#define DDRC_DRAMTMG4_t_rcd_SHIFT (24U)
10016/*! t_rcd - tRCD - tAL: Minimum time from activate to read or write command to same bank. When the
10017 * controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round
10018 * it up to the next integer value. Minimum value allowed for this register is 1, which implies
10019 * minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio
10020 * mode. Unit: Clocks.
10021 */
10022#define DDRC_DRAMTMG4_t_rcd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rcd_SHIFT)) & DDRC_DRAMTMG4_t_rcd_MASK)
10023/*! @} */
10024
10025/*! @name DRAMTMG5 - SDRAM Timing Register 5 */
10026/*! @{ */
10027#define DDRC_DRAMTMG5_t_cke_MASK (0x1FU)
10028#define DDRC_DRAMTMG5_t_cke_SHIFT (0U)
10029/*! t_cke - Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. -
10030 * LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LPDDR4 mode: Set this to the larger of
10031 * tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. When
10032 * the controller is operating in 1:2 frequency ratio mode, program this to (value described
10033 * above)/2 and round it up to the next integer value. Unit: Clocks.
10034 */
10035#define DDRC_DRAMTMG5_t_cke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cke_SHIFT)) & DDRC_DRAMTMG5_t_cke_MASK)
10036#define DDRC_DRAMTMG5_t_ckesr_MASK (0x3F00U)
10037#define DDRC_DRAMTMG5_t_ckesr_SHIFT (8U)
10038/*! t_ckesr - Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing
10039 * in memory clock cycles. Recommended settings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR
10040 * - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 (+ PL(parity
10041 * latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased
10042 * by PL. When the controller is operating in 1:2 frequency ratio mode, program this to
10043 * recommended value divided by two and round it up to next integer.
10044 */
10045#define DDRC_DRAMTMG5_t_ckesr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_ckesr_SHIFT)) & DDRC_DRAMTMG5_t_ckesr_MASK)
10046#define DDRC_DRAMTMG5_t_cksre_MASK (0xF0000U)
10047#define DDRC_DRAMTMG5_t_cksre_SHIFT (16U)
10048/*! t_cksre - This is the time after Self Refresh Down Entry that CK is maintained as a valid clock.
10049 * Specifies the clock disable delay after SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 -
10050 * LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) (+
10051 * PL(parity latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should
10052 * be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program
10053 * this to recommended value divided by two and round it up to next integer.
10054 */
10055#define DDRC_DRAMTMG5_t_cksre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cksre_SHIFT)) & DDRC_DRAMTMG5_t_cksre_MASK)
10056#define DDRC_DRAMTMG5_t_cksrx_MASK (0xF000000U)
10057#define DDRC_DRAMTMG5_t_cksrx_SHIFT (24U)
10058/*! t_cksrx - This is the time before Self Refresh Exit that CK is maintained as a valid clock
10059 * before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR: 1 -
10060 * LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX When the
10061 * controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by
10062 * two and round it up to next integer.
10063 */
10064#define DDRC_DRAMTMG5_t_cksrx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cksrx_SHIFT)) & DDRC_DRAMTMG5_t_cksrx_MASK)
10065/*! @} */
10066
10067/*! @name DRAMTMG6 - SDRAM Timing Register 6 */
10068/*! @{ */
10069#define DDRC_DRAMTMG6_t_ckcsx_MASK (0xFU)
10070#define DDRC_DRAMTMG6_t_ckcsx_SHIFT (0U)
10071/*! t_ckcsx - This is the time before Clock Stop Exit that CK is maintained as a valid clock before
10072 * issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop
10073 * Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2
10074 * When the controller is operating in 1:2 frequency ratio mode, program this to recommended value
10075 * divided by two and round it up to next integer. This is only present for designs supporting
10076 * mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
10077 */
10078#define DDRC_DRAMTMG6_t_ckcsx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckcsx_SHIFT)) & DDRC_DRAMTMG6_t_ckcsx_MASK)
10079#define DDRC_DRAMTMG6_t_ckdpdx_MASK (0xF0000U)
10080#define DDRC_DRAMTMG6_t_ckdpdx_SHIFT (16U)
10081/*! t_ckdpdx - This is the time before Deep Power Down Exit that CK is maintained as a valid clock
10082 * before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR:
10083 * 1 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode,
10084 * program this to recommended value divided by two and round it up to next integer. This is only
10085 * present for designs supporting mDDR or LPDDR2 devices.
10086 */
10087#define DDRC_DRAMTMG6_t_ckdpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckdpdx_SHIFT)) & DDRC_DRAMTMG6_t_ckdpdx_MASK)
10088#define DDRC_DRAMTMG6_t_ckdpde_MASK (0xF000000U)
10089#define DDRC_DRAMTMG6_t_ckdpde_SHIFT (24U)
10090/*! t_ckdpde - This is the time after Deep Power Down Entry that CK is maintained as a valid clock.
10091 * Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 -
10092 * LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to
10093 * recommended value divided by two and round it up to next integer. This is only present for designs
10094 * supporting mDDR or LPDDR2/LPDDR3 devices.
10095 */
10096#define DDRC_DRAMTMG6_t_ckdpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckdpde_SHIFT)) & DDRC_DRAMTMG6_t_ckdpde_MASK)
10097/*! @} */
10098
10099/*! @name DRAMTMG7 - SDRAM Timing Register 7 */
10100/*! @{ */
10101#define DDRC_DRAMTMG7_t_ckpdx_MASK (0xFU)
10102#define DDRC_DRAMTMG7_t_ckpdx_SHIFT (0U)
10103/*! t_ckpdx - This is the time before Power Down Exit that CK is maintained as a valid clock before
10104 * issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR: 0 -
10105 * LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 When using DDR2/3/4 SDRAM, this register should be set to the
10106 * same value as DRAMTMG5.t_cksrx. When the controller is operating in 1:2 frequency ratio mode,
10107 * program this to recommended value divided by two and round it up to next integer. This is only
10108 * present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
10109 */
10110#define DDRC_DRAMTMG7_t_ckpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_t_ckpdx_SHIFT)) & DDRC_DRAMTMG7_t_ckpdx_MASK)
10111#define DDRC_DRAMTMG7_t_ckpde_MASK (0xF00U)
10112#define DDRC_DRAMTMG7_t_ckpde_SHIFT (8U)
10113/*! t_ckpde - This is the time after Power Down Entry that CK is maintained as a valid clock.
10114 * Specifies the clock disable delay after PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2
10115 * - LPDDR4: tCKCKEL When using DDR2/3/4 SDRAM, this register should be set to the same value as
10116 * DRAMTMG5.t_cksre. When the controller is operating in 1:2 frequency ratio mode, program this
10117 * to recommended value divided by two and round it up to next integer. This is only present for
10118 * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
10119 */
10120#define DDRC_DRAMTMG7_t_ckpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_t_ckpde_SHIFT)) & DDRC_DRAMTMG7_t_ckpde_MASK)
10121/*! @} */
10122
10123/*! @name DRAMTMG8 - SDRAM Timing Register 8 */
10124/*! @{ */
10125#define DDRC_DRAMTMG8_t_xs_x32_MASK (0x7FU)
10126#define DDRC_DRAMTMG8_t_xs_x32_SHIFT (0U)
10127/*! t_xs_x32 - tXS: Exit Self Refresh to commands not requiring a locked DLL. When the controller is
10128 * operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round
10129 * up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
10130 * DDR4 SDRAMs.
10131 */
10132#define DDRC_DRAMTMG8_t_xs_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_x32_MASK)
10133#define DDRC_DRAMTMG8_t_xs_dll_x32_MASK (0x7F00U)
10134#define DDRC_DRAMTMG8_t_xs_dll_x32_SHIFT (8U)
10135/*! t_xs_dll_x32 - tXSDLL: Exit Self Refresh to commands requiring a locked DLL. When the controller
10136 * is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and
10137 * round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
10138 * DDR4 SDRAMs.
10139 */
10140#define DDRC_DRAMTMG8_t_xs_dll_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_dll_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_dll_x32_MASK)
10141#define DDRC_DRAMTMG8_t_xs_abort_x32_MASK (0x7F0000U)
10142#define DDRC_DRAMTMG8_t_xs_abort_x32_SHIFT (16U)
10143/*! t_xs_abort_x32 - tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self
10144 * Refresh Abort. When the controller is operating in 1:2 frequency ratio mode, program this to the
10145 * above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
10146 * Note: Ensure this is less than or equal to t_xs_x32.
10147 */
10148#define DDRC_DRAMTMG8_t_xs_abort_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_abort_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_abort_x32_MASK)
10149#define DDRC_DRAMTMG8_t_xs_fast_x32_MASK (0x7F000000U)
10150#define DDRC_DRAMTMG8_t_xs_fast_x32_SHIFT (24U)
10151/*! t_xs_fast_x32 - tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown
10152 * mode). When the controller is operating in 1:2 frequency ratio mode, program this to the
10153 * above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note:
10154 * This is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to
10155 * t_xs_x32.
10156 */
10157#define DDRC_DRAMTMG8_t_xs_fast_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_fast_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_fast_x32_MASK)
10158/*! @} */
10159
10160/*! @name DRAMTMG9 - SDRAM Timing Register 9 */
10161/*! @{ */
10162#define DDRC_DRAMTMG9_wr2rd_s_MASK (0x3FU)
10163#define DDRC_DRAMTMG9_wr2rd_s_SHIFT (0U)
10164/*! wr2rd_s - CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different
10165 * bank group. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and
10166 * global constraints. Present only in designs configured to support DDR4. Unit: Clocks. Where:
10167 * - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value
10168 * programmed in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read
10169 * command delay for different bank group. This comes directly from the SDRAM specification. When
10170 * the controller is operating in 1:2 mode, divide the value calculated using the above equation
10171 * by 2, and round it up to next integer.
10172 */
10173#define DDRC_DRAMTMG9_wr2rd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_wr2rd_s_SHIFT)) & DDRC_DRAMTMG9_wr2rd_s_MASK)
10174#define DDRC_DRAMTMG9_t_rrd_s_MASK (0xF00U)
10175#define DDRC_DRAMTMG9_t_rrd_s_SHIFT (8U)
10176/*! t_rrd_s - tRRD_S: Minimum time between activates from bank "a" to bank "b" for different bank
10177 * group. When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_S/2)
10178 * and round it up to the next integer value. Present only in designs configured to support DDR4.
10179 * Unit: Clocks.
10180 */
10181#define DDRC_DRAMTMG9_t_rrd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_t_rrd_s_SHIFT)) & DDRC_DRAMTMG9_t_rrd_s_MASK)
10182#define DDRC_DRAMTMG9_t_ccd_s_MASK (0x70000U)
10183#define DDRC_DRAMTMG9_t_ccd_s_SHIFT (16U)
10184/*! t_ccd_s - tCCD_S: This is the minimum time between two reads or two writes for different bank
10185 * group. For bank switching (from bank "a" to bank "b"), the minimum time is this value + 1. When
10186 * the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_S/2) and round
10187 * it up to the next integer value. Present only in designs configured to support DDR4. Unit:
10188 * clocks.
10189 */
10190#define DDRC_DRAMTMG9_t_ccd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_t_ccd_s_SHIFT)) & DDRC_DRAMTMG9_t_ccd_s_MASK)
10191#define DDRC_DRAMTMG9_ddr4_wr_preamble_MASK (0x40000000U)
10192#define DDRC_DRAMTMG9_ddr4_wr_preamble_SHIFT (30U)
10193/*! ddr4_wr_preamble - DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2
10194 */
10195#define DDRC_DRAMTMG9_ddr4_wr_preamble(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_ddr4_wr_preamble_SHIFT)) & DDRC_DRAMTMG9_ddr4_wr_preamble_MASK)
10196/*! @} */
10197
10198/*! @name DRAMTMG10 - SDRAM Timing Register 10 */
10199/*! @{ */
10200#define DDRC_DRAMTMG10_t_gear_hold_MASK (0x3U)
10201#define DDRC_DRAMTMG10_t_gear_hold_SHIFT (0U)
10202/*! t_gear_hold - Geardown hold time. Minimum value of this register is 1. Zero is invalid. For
10203 * DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in
10204 * 1:2 frequency ratio mode, program this to (tGEAR_hold/2) and round it up to the next integer
10205 * value. Unit: Clocks
10206 */
10207#define DDRC_DRAMTMG10_t_gear_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_gear_hold_SHIFT)) & DDRC_DRAMTMG10_t_gear_hold_MASK)
10208#define DDRC_DRAMTMG10_t_gear_setup_MASK (0xCU)
10209#define DDRC_DRAMTMG10_t_gear_setup_SHIFT (2U)
10210/*! t_gear_setup - Geardown setup time. Minimum value of this register is 1. Zero is invalid. For
10211 * DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in
10212 * 1:2 frequency ratio mode, program this to (tGEAR_setup/2) and round it up to the next integer
10213 * value. Unit: Clocks
10214 */
10215#define DDRC_DRAMTMG10_t_gear_setup(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_gear_setup_SHIFT)) & DDRC_DRAMTMG10_t_gear_setup_MASK)
10216#define DDRC_DRAMTMG10_t_cmd_gear_MASK (0x1F00U)
10217#define DDRC_DRAMTMG10_t_cmd_gear_SHIFT (8U)
10218/*! t_cmd_gear - Sync pulse to first valid command. For DDR4-2666 and DDR4-3200, this parameter is
10219 * defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for
10220 * this register is 24 When the controller is operating in 1:2 mode, program this to (tCMD_GEAR/2)
10221 * and round it up to the next integer value. Unit: Clocks
10222 */
10223#define DDRC_DRAMTMG10_t_cmd_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_cmd_gear_SHIFT)) & DDRC_DRAMTMG10_t_cmd_gear_MASK)
10224#define DDRC_DRAMTMG10_t_sync_gear_MASK (0x1F0000U)
10225#define DDRC_DRAMTMG10_t_sync_gear_SHIFT (16U)
10226/*! t_sync_gear - Indicates the time between MRS command and the sync pulse time. This must be even
10227 * number of clocks. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min)+4nCK
10228 * tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24+4 = 28
10229 * When the controller is operating in 1:2 mode, program this to (tSYNC_GEAR/2) and round it up
10230 * to the next integer value. Unit: Clocks
10231 */
10232#define DDRC_DRAMTMG10_t_sync_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_sync_gear_SHIFT)) & DDRC_DRAMTMG10_t_sync_gear_MASK)
10233/*! @} */
10234
10235/*! @name DRAMTMG11 - SDRAM Timing Register 11 */
10236/*! @{ */
10237#define DDRC_DRAMTMG11_t_ckmpe_MASK (0x1FU)
10238#define DDRC_DRAMTMG11_t_ckmpe_SHIFT (0U)
10239/*! t_ckmpe - tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs
10240 * configured to support DDR4. Unit: Clocks. When the controller is operating in 1:2 frequency ratio
10241 * mode, divide the value calculated using the above equation by 2, and round it up to next
10242 * integer.
10243 */
10244#define DDRC_DRAMTMG11_t_ckmpe(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_ckmpe_SHIFT)) & DDRC_DRAMTMG11_t_ckmpe_MASK)
10245#define DDRC_DRAMTMG11_t_mpx_s_MASK (0x300U)
10246#define DDRC_DRAMTMG11_t_mpx_s_SHIFT (8U)
10247/*! t_mpx_s - tMPX_S: Minimum time CS setup time to CKE. When the controller is operating in 1:2
10248 * frequency ratio mode, program this to (tMPX_S/2) and round it up to the next integer value.
10249 * Present only in designs configured to support DDR4. Unit: Clocks.
10250 */
10251#define DDRC_DRAMTMG11_t_mpx_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_mpx_s_SHIFT)) & DDRC_DRAMTMG11_t_mpx_s_MASK)
10252#define DDRC_DRAMTMG11_t_mpx_lh_MASK (0x1F0000U)
10253#define DDRC_DRAMTMG11_t_mpx_lh_SHIFT (16U)
10254/*! t_mpx_lh - tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the
10255 * controller is operating in 1:2 frequency ratio mode, program this to RoundUp(tMPX_LH/2)+1. Present
10256 * only in designs configured to support DDR4. Unit: clocks.
10257 */
10258#define DDRC_DRAMTMG11_t_mpx_lh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_mpx_lh_SHIFT)) & DDRC_DRAMTMG11_t_mpx_lh_MASK)
10259#define DDRC_DRAMTMG11_post_mpsm_gap_x32_MASK (0x7F000000U)
10260#define DDRC_DRAMTMG11_post_mpsm_gap_x32_SHIFT (24U)
10261/*! post_mpsm_gap_x32 - tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL.
10262 * When the controller is operating in 1:2 frequency ratio mode, program this to (tXMPDLL/2) and
10263 * round it up to the next integer value. Present only in designs configured to support DDR4.
10264 * Unit: Multiples of 32 clocks.
10265 */
10266#define DDRC_DRAMTMG11_post_mpsm_gap_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_post_mpsm_gap_x32_SHIFT)) & DDRC_DRAMTMG11_post_mpsm_gap_x32_MASK)
10267/*! @} */
10268
10269/*! @name DRAMTMG12 - SDRAM Timing Register 12 */
10270/*! @{ */
10271#define DDRC_DRAMTMG12_t_mrd_pda_MASK (0x1FU)
10272#define DDRC_DRAMTMG12_t_mrd_pda_SHIFT (0U)
10273/*! t_mrd_pda - tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the
10274 * controller is operating in 1:2 frequency ratio mode, program this to (tMRD_PDA/2) and round it up
10275 * to the next integer value.
10276 */
10277#define DDRC_DRAMTMG12_t_mrd_pda(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_mrd_pda_SHIFT)) & DDRC_DRAMTMG12_t_mrd_pda_MASK)
10278#define DDRC_DRAMTMG12_t_ckehcmd_MASK (0xF00U)
10279#define DDRC_DRAMTMG12_t_ckehcmd_SHIFT (8U)
10280/*! t_ckehcmd - tCKEHCMD: Valid command requirement after CKE input HIGH. When the controller is
10281 * operating in 1:2 frequency ratio mode, program this to (tCKEHCMD/2) and round it up to the next
10282 * integer value.
10283 */
10284#define DDRC_DRAMTMG12_t_ckehcmd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_ckehcmd_SHIFT)) & DDRC_DRAMTMG12_t_ckehcmd_MASK)
10285#define DDRC_DRAMTMG12_t_cmdcke_MASK (0x30000U)
10286#define DDRC_DRAMTMG12_t_cmdcke_SHIFT (16U)
10287/*! t_cmdcke - tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE
10288 * or tCMDCKE When the controller is operating in 1:2 frequency ratio mode, program this to
10289 * (max(tESCKE, tCMDCKE)/2) and round it up to the next integer value.
10290 */
10291#define DDRC_DRAMTMG12_t_cmdcke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_cmdcke_SHIFT)) & DDRC_DRAMTMG12_t_cmdcke_MASK)
10292/*! @} */
10293
10294/*! @name DRAMTMG13 - SDRAM Timing Register 13 */
10295/*! @{ */
10296#define DDRC_DRAMTMG13_t_ppd_MASK (0x7U)
10297#define DDRC_DRAMTMG13_t_ppd_SHIFT (0U)
10298/*! t_ppd - LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the
10299 * controller is operating in 1:2 frequency ratio mode, program this to (tPPD/2) and round it up to
10300 * the next integer value. Unit: Clocks.
10301 */
10302#define DDRC_DRAMTMG13_t_ppd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_t_ppd_SHIFT)) & DDRC_DRAMTMG13_t_ppd_MASK)
10303#define DDRC_DRAMTMG13_t_ccd_mw_MASK (0x3F0000U)
10304#define DDRC_DRAMTMG13_t_ccd_mw_SHIFT (16U)
10305/*! t_ccd_mw - LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write
10306 * command for same bank. When the controller is operating in 1:2 frequency ratio mode, program
10307 * this to (tCCDMW/2) and round it up to the next integer value. Unit: Clocks.
10308 */
10309#define DDRC_DRAMTMG13_t_ccd_mw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_t_ccd_mw_SHIFT)) & DDRC_DRAMTMG13_t_ccd_mw_MASK)
10310#define DDRC_DRAMTMG13_odtloff_MASK (0x7F000000U)
10311#define DDRC_DRAMTMG13_odtloff_SHIFT (24U)
10312/*! odtloff - LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference. When
10313 * the controller is operating in 1:2 frequency ratio mode, program this to (tODTLoff/2) and round
10314 * it up to the next integer value. Unit: Clocks.
10315 */
10316#define DDRC_DRAMTMG13_odtloff(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_odtloff_SHIFT)) & DDRC_DRAMTMG13_odtloff_MASK)
10317/*! @} */
10318
10319/*! @name DRAMTMG14 - SDRAM Timing Register 14 */
10320/*! @{ */
10321#define DDRC_DRAMTMG14_t_xsr_MASK (0xFFFU)
10322#define DDRC_DRAMTMG14_t_xsr_SHIFT (0U)
10323/*! t_xsr - tXSR: Exit Self Refresh to any command. When the controller is operating in 1:2
10324 * frequency ratio mode, program this to the above value divided by 2 and round up to next integer value.
10325 * Note: Used only for mDDR/LPDDR2/LPDDR3/LPDDR4 mode.
10326 */
10327#define DDRC_DRAMTMG14_t_xsr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG14_t_xsr_SHIFT)) & DDRC_DRAMTMG14_t_xsr_MASK)
10328/*! @} */
10329
10330/*! @name DRAMTMG15 - SDRAM Timing Register 15 */
10331/*! @{ */
10332#define DDRC_DRAMTMG15_t_stab_x32_MASK (0xFFU)
10333#define DDRC_DRAMTMG15_t_stab_x32_SHIFT (0U)
10334/*! t_stab_x32 - tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4
10335 * RDIMM : - when exiting power saving mode, if the clock was stopped, after re-enabling it the
10336 * clock must be stable for a time specified by tSTAB - in the case of input clock frequency
10337 * change (DDR4) - after issuing control words that refers to clock timing (Specification: 6us for
10338 * DDR3, 5us for DDR4) When the controller is operating in 1:2 frequency ratio mode, program this to
10339 * recommended value divided by two and round it up to next integer. Unit: Multiples of 32 clock
10340 * cycles.
10341 */
10342#define DDRC_DRAMTMG15_t_stab_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_t_stab_x32_SHIFT)) & DDRC_DRAMTMG15_t_stab_x32_MASK)
10343#define DDRC_DRAMTMG15_en_dfi_lp_t_stab_MASK (0x80000000U)
10344#define DDRC_DRAMTMG15_en_dfi_lp_t_stab_SHIFT (31U)
10345/*! en_dfi_lp_t_stab - Enable DFI tSTAB
10346 * 0b0..Disable using tSTAB when exiting DFI LP
10347 * 0b1..Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power.
10348 */
10349#define DDRC_DRAMTMG15_en_dfi_lp_t_stab(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_en_dfi_lp_t_stab_SHIFT)) & DDRC_DRAMTMG15_en_dfi_lp_t_stab_MASK)
10350/*! @} */
10351
10352/*! @name ZQCTL0 - ZQ Control Register 0 */
10353/*! @{ */
10354#define DDRC_ZQCTL0_t_zq_short_nop_MASK (0x3FFU)
10355#define DDRC_ZQCTL0_t_zq_short_nop_SHIFT (0U)
10356/*! t_zq_short_nop - tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles
10357 * of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM.
10358 * When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and
10359 * round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or
10360 * LPDDR2/LPDDR3/LPDDR4 devices.
10361 */
10362#define DDRC_ZQCTL0_t_zq_short_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_t_zq_short_nop_SHIFT)) & DDRC_ZQCTL0_t_zq_short_nop_MASK)
10363#define DDRC_ZQCTL0_t_zq_long_nop_MASK (0x7FF0000U)
10364#define DDRC_ZQCTL0_t_zq_long_nop_SHIFT (16U)
10365/*! t_zq_long_nop - tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI
10366 * clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is
10367 * issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode: DDR3/DDR4: program
10368 * this to tZQoper/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to
10369 * tZQCL/2 and round it up to the next integer value. LPDDR4: program this to tZQCAL/2 and round it
10370 * up to the next integer value. This is only present for designs supporting DDR3/DDR4 or
10371 * LPDDR2/LPDDR3/LPDDR4 devices.
10372 */
10373#define DDRC_ZQCTL0_t_zq_long_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_t_zq_long_nop_SHIFT)) & DDRC_ZQCTL0_t_zq_long_nop_MASK)
10374#define DDRC_ZQCTL0_dis_mpsmx_zqcl_MASK (0x10000000U)
10375#define DDRC_ZQCTL0_dis_mpsmx_zqcl_SHIFT (28U)
10376/*! dis_mpsmx_zqcl - Do not issue ZQCL command at Maximum Power Save Mode exit if the DDRC_SHARED_AC
10377 * configuration parameter is set. Program it to 1'b1. The software can send ZQCS after exiting
10378 * MPSM mode.
10379 * 0b0..Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode.
10380 * This is only present for designs supporting DDR4 devices.
10381 * 0b1..Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode.
10382 */
10383#define DDRC_ZQCTL0_dis_mpsmx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_mpsmx_zqcl_SHIFT)) & DDRC_ZQCTL0_dis_mpsmx_zqcl_MASK)
10384#define DDRC_ZQCTL0_zq_resistor_shared_MASK (0x20000000U)
10385#define DDRC_ZQCTL0_zq_resistor_shared_SHIFT (29U)
10386/*! zq_resistor_shared - ZQ resistor sharing
10387 * 0b0..ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
10388 * 0b1..Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are
10389 * sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that
10390 * commands to different ranks do not overlap.
10391 */
10392#define DDRC_ZQCTL0_zq_resistor_shared(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_zq_resistor_shared_SHIFT)) & DDRC_ZQCTL0_zq_resistor_shared_MASK)
10393#define DDRC_ZQCTL0_dis_srx_zqcl_MASK (0x40000000U)
10394#define DDRC_ZQCTL0_dis_srx_zqcl_SHIFT (30U)
10395/*! dis_srx_zqcl - Disable ZQCL/MPC
10396 * 0b0..Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable
10397 * when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs supporting
10398 * DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
10399 * 0b1..Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable
10400 * when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode.
10401 */
10402#define DDRC_ZQCTL0_dis_srx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_srx_zqcl_SHIFT)) & DDRC_ZQCTL0_dis_srx_zqcl_MASK)
10403#define DDRC_ZQCTL0_dis_auto_zq_MASK (0x80000000U)
10404#define DDRC_ZQCTL0_dis_auto_zq_SHIFT (31U)
10405/*! dis_auto_zq - Disable Auto ZQCS/MPC
10406 * 0b0..Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024.
10407 * 0b1..Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used
10408 * instead to issue ZQ calibration request from APB module.
10409 */
10410#define DDRC_ZQCTL0_dis_auto_zq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_auto_zq_SHIFT)) & DDRC_ZQCTL0_dis_auto_zq_MASK)
10411/*! @} */
10412
10413/*! @name ZQCTL1 - ZQ Control Register 1 */
10414/*! @{ */
10415#define DDRC_ZQCTL1_t_zq_short_interval_x1024_MASK (0xFFFFFU)
10416#define DDRC_ZQCTL1_t_zq_short_interval_x1024_SHIFT (0U)
10417/*! t_zq_short_interval_x1024 - Average interval to wait between automatically issuing ZQCS (ZQ
10418 * calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices.
10419 * Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 DFI clock cycles. This is only present for designs
10420 * supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
10421 */
10422#define DDRC_ZQCTL1_t_zq_short_interval_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_t_zq_short_interval_x1024_SHIFT)) & DDRC_ZQCTL1_t_zq_short_interval_x1024_MASK)
10423#define DDRC_ZQCTL1_t_zq_reset_nop_MASK (0x3FF00000U)
10424#define DDRC_ZQCTL1_t_zq_reset_nop_SHIFT (20U)
10425/*! t_zq_reset_nop - tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ
10426 * calibration Reset) command is issued to SDRAM. When the controller is operating in 1:2 frequency
10427 * ratio mode, program this to tZQReset/2 and round it up to the next integer value. This is only
10428 * present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
10429 */
10430#define DDRC_ZQCTL1_t_zq_reset_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_t_zq_reset_nop_SHIFT)) & DDRC_ZQCTL1_t_zq_reset_nop_MASK)
10431/*! @} */
10432
10433/*! @name ZQCTL2 - ZQ Control Register 2 */
10434/*! @{ */
10435#define DDRC_ZQCTL2_zq_reset_MASK (0x1U)
10436#define DDRC_ZQCTL2_zq_reset_SHIFT (0U)
10437/*! zq_reset - Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset
10438 * operation is complete, the DDRC automatically clears this bit. It is recommended NOT to set this
10439 * signal if in Init, Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down
10440 * operating modes. This is only present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
10441 */
10442#define DDRC_ZQCTL2_zq_reset(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL2_zq_reset_SHIFT)) & DDRC_ZQCTL2_zq_reset_MASK)
10443/*! @} */
10444
10445/*! @name ZQSTAT - ZQ Status Register */
10446/*! @{ */
10447#define DDRC_ZQSTAT_zq_reset_busy_MASK (0x1U)
10448#define DDRC_ZQSTAT_zq_reset_busy_SHIFT (0U)
10449/*! zq_reset_busy - SoC core may initiate a ZQ Reset operation only if this signal is low. This
10450 * signal goes high in the clock after the DDRC accepts the ZQ Reset request. It goes low when the ZQ
10451 * Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended
10452 * not to perform ZQ Reset commands when this signal is high.
10453 * 0b0..Indicates that the SoC core can initiate a ZQ Reset operation
10454 * 0b1..Indicates that ZQ Reset operation is in progress
10455 */
10456#define DDRC_ZQSTAT_zq_reset_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQSTAT_zq_reset_busy_SHIFT)) & DDRC_ZQSTAT_zq_reset_busy_MASK)
10457/*! @} */
10458
10459/*! @name DFITMG0 - DFI Timing Register 0 */
10460/*! @{ */
10461#define DDRC_DFITMG0_dfi_tphy_wrlat_MASK (0x3FU)
10462#define DDRC_DFITMG0_dfi_tphy_wrlat_SHIFT (0U)
10463/*! dfi_tphy_wrlat - Write latency Number of clocks from the write command to write data enable
10464 * (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY
10465 * specification for correct value.Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be
10466 * necessary to use the adjusted value of CL in the calculation of tphy_wrlat. This is to compensate for
10467 * the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY
10468 * clock cycles, depending on DFITMG0.dfi_wrdata_use_sdr.
10469 */
10470#define DDRC_DFITMG0_dfi_tphy_wrlat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_tphy_wrlat_SHIFT)) & DDRC_DFITMG0_dfi_tphy_wrlat_MASK)
10471#define DDRC_DFITMG0_dfi_tphy_wrdata_MASK (0x3F00U)
10472#define DDRC_DFITMG0_dfi_tphy_wrdata_SHIFT (8U)
10473/*! dfi_tphy_wrdata - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to
10474 * when the associated write data is driven on the dfi_wrdata signal. This corresponds to the
10475 * DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max
10476 * supported value is 8. Unit: DFI clock cycles or DFI PHY clock cycles, depending on
10477 * DFITMG0.dfi_wrdata_use_sdr.
10478 */
10479#define DDRC_DFITMG0_dfi_tphy_wrdata(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_tphy_wrdata_SHIFT)) & DDRC_DFITMG0_dfi_tphy_wrdata_MASK)
10480#define DDRC_DFITMG0_dfi_wrdata_use_sdr_MASK (0x8000U)
10481#define DDRC_DFITMG0_dfi_wrdata_use_sdr_SHIFT (15U)
10482/*! dfi_wrdata_use_sdr - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using
10483 * HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value in DFITMG0.dfi_tphy_wrlat
10484 * is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles Selects whether value in
10485 * DFITMG0.dfi_tphy_wrdata is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles - 0 in terms of
10486 * HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification
10487 * for correct value.
10488 */
10489#define DDRC_DFITMG0_dfi_wrdata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_wrdata_use_sdr_SHIFT)) & DDRC_DFITMG0_dfi_wrdata_use_sdr_MASK)
10490#define DDRC_DFITMG0_dfi_t_rddata_en_MASK (0x7F0000U)
10491#define DDRC_DFITMG0_dfi_t_rddata_en_SHIFT (16U)
10492/*! dfi_t_rddata_en - Time from the assertion of a read command on the DFI interface to the
10493 * assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds
10494 * to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM/LRDIMM, it
10495 * may be necessary to use the adjusted value of CL in the calculation of trddata_en. This is to
10496 * compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or
10497 * DFI PHY clock cycles, depending on DFITMG0.dfi_rddata_use_sdr.
10498 */
10499#define DDRC_DFITMG0_dfi_t_rddata_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_t_rddata_en_SHIFT)) & DDRC_DFITMG0_dfi_t_rddata_en_MASK)
10500#define DDRC_DFITMG0_dfi_rddata_use_sdr_MASK (0x800000U)
10501#define DDRC_DFITMG0_dfi_rddata_use_sdr_SHIFT (23U)
10502/*! dfi_rddata_use_sdr - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated
10503 * using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in
10504 * DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles: - 0 in terms of HDR (DFI
10505 * clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct
10506 * value.
10507 */
10508#define DDRC_DFITMG0_dfi_rddata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_rddata_use_sdr_SHIFT)) & DDRC_DFITMG0_dfi_rddata_use_sdr_MASK)
10509#define DDRC_DFITMG0_dfi_t_ctrl_delay_MASK (0x1F000000U)
10510#define DDRC_DFITMG0_dfi_t_ctrl_delay_SHIFT (24U)
10511/*! dfi_t_ctrl_delay - Specifies the number of DFI clock cycles after an assertion or de-assertion
10512 * of the DFI control signals that the control signals at the PHY-DRAM interface reflect the
10513 * assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing
10514 * parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it
10515 * is necessary to increment this parameter by RDIMM's/LRDIMM's extra cycle of latency in terms
10516 * of DFI clock.
10517 */
10518#define DDRC_DFITMG0_dfi_t_ctrl_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_t_ctrl_delay_SHIFT)) & DDRC_DFITMG0_dfi_t_ctrl_delay_MASK)
10519/*! @} */
10520
10521/*! @name DFITMG1 - DFI Timing Register 1 */
10522/*! @{ */
10523#define DDRC_DFITMG1_dfi_t_dram_clk_enable_MASK (0x1FU)
10524#define DDRC_DFITMG1_dfi_t_dram_clk_enable_SHIFT (0U)
10525/*! dfi_t_dram_clk_enable - Specifies the number of DFI clock cycles from the de-assertion of the
10526 * dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the
10527 * DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not
10528 * phase aligned, this timing parameter should be rounded up to the next integer value.
10529 */
10530#define DDRC_DFITMG1_dfi_t_dram_clk_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_dram_clk_enable_SHIFT)) & DDRC_DFITMG1_dfi_t_dram_clk_enable_MASK)
10531#define DDRC_DFITMG1_dfi_t_dram_clk_disable_MASK (0x1F00U)
10532#define DDRC_DFITMG1_dfi_t_dram_clk_disable_SHIFT (8U)
10533/*! dfi_t_dram_clk_disable - Specifies the number of DFI clock cycles from the assertion of the
10534 * dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM
10535 * boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned,
10536 * this timing parameter should be rounded up to the next integer value.
10537 */
10538#define DDRC_DFITMG1_dfi_t_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_dram_clk_disable_SHIFT)) & DDRC_DFITMG1_dfi_t_dram_clk_disable_MASK)
10539#define DDRC_DFITMG1_dfi_t_wrdata_delay_MASK (0x1F0000U)
10540#define DDRC_DFITMG1_dfi_t_wrdata_delay_SHIFT (16U)
10541/*! dfi_t_wrdata_delay - Specifies the number of DFI clock cycles between when the dfi_wrdata_en
10542 * signal is asserted and when the corresponding write data transfer is completed on the DRAM bus.
10543 * This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for
10544 * correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI
10545 * 3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be
10546 * programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2
10547 * and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit:
10548 * Clocks
10549 */
10550#define DDRC_DFITMG1_dfi_t_wrdata_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_wrdata_delay_SHIFT)) & DDRC_DFITMG1_dfi_t_wrdata_delay_MASK)
10551#define DDRC_DFITMG1_dfi_t_parin_lat_MASK (0x3000000U)
10552#define DDRC_DFITMG1_dfi_t_parin_lat_SHIFT (24U)
10553/*! dfi_t_parin_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is
10554 * asserted and when the associated dfi_parity_in signal is driven.
10555 */
10556#define DDRC_DFITMG1_dfi_t_parin_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_parin_lat_SHIFT)) & DDRC_DFITMG1_dfi_t_parin_lat_MASK)
10557#define DDRC_DFITMG1_dfi_t_cmd_lat_MASK (0xF0000000U)
10558#define DDRC_DFITMG1_dfi_t_cmd_lat_SHIFT (28U)
10559/*! dfi_t_cmd_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is
10560 * asserted and when the associated command is driven. This field is used for CAL mode, should be
10561 * set to '0' or the value which matches the CAL mode register setting in the D