59 files changed, 163020 insertions, 0 deletions

diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX6/MIMX8QX6_cm4.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX6/MIMX8QX6_cm4.h
new file mode 100644
index 000000000..3b92e471c
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8QX6/MIMX8QX6_cm4.h
@@ -0,0 +1,144415 @@
+/*
+** ###################################################################
+**     Processors:          MIMX8QX6AVLFZ
+**                          MIMX8QX6CVLDZ
+**
+**     Compilers:           GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**
+**     Reference manual:    IMX8DQXPRM, Rev. E, 6/2019
+**     Version:             rev. 4.0, 2020-06-19
+**     Build:               b200825
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MIMX8QX6_cm4
+**
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2020 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+**     Revisions:
+**     - rev. 1.0 (2016-06-02)
+**         Initial version.
+**     - rev. 2.0 (2017-08-23)
+**         RevA Header EAR
+**     - rev. 3.0 (2018-08-22)
+**         RevB Header EAR
+**     - rev. 4.0 (2020-06-19)
+**         RevC Header RFP
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MIMX8QX6_cm4.h
+ * @version 4.0
+ * @date 2020-06-19
+ * @brief CMSIS Peripheral Access Layer for MIMX8QX6_cm4
+ *
+ * CMSIS Peripheral Access Layer for MIMX8QX6_cm4
+ */
+
+#ifndef _MIMX8QX6_CM4_H_
+#define _MIMX8QX6_CM4_H_                         /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0400U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
+
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 611                /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  Reserved16_IRQn              = 0,                /**< Reserved */
+  Reserved17_IRQn              = 1,                /**< Reserved */
+  Reserved18_IRQn              = 2,                /**< Reserved */
+  Reserved19_IRQn              = 3,                /**< Reserved */
+  Reserved20_IRQn              = 4,                /**< Reserved */
+  M4_MCM_IRQn                  = 5,                /**< MCM IRQ */
+  Reserved22_IRQn              = 6,                /**< Reserved */
+  Reserved23_IRQn              = 7,                /**< Reserved */
+  Reserved24_IRQn              = 8,                /**< Reserved */
+  Reserved25_IRQn              = 9,                /**< Reserved */
+  Reserved26_IRQn              = 10,               /**< Reserved */
+  Reserved27_IRQn              = 11,               /**< Reserved */
+  Reserved28_IRQn              = 12,               /**< Reserved */
+  Reserved29_IRQn              = 13,               /**< Reserved */
+  Reserved30_IRQn              = 14,               /**< Reserved */
+  Reserved31_IRQn              = 15,               /**< Reserved */
+  Reserved32_IRQn              = 16,               /**< Reserved */
+  Reserved33_IRQn              = 17,               /**< Reserved */
+  Reserved34_IRQn              = 18,               /**< Reserved */
+  M4_TPM_IRQn                  = 19,               /**< Timer PWM Module */
+  Reserved36_IRQn              = 20,               /**< Reserved */
+  Reserved37_IRQn              = 21,               /**< Reserved */
+  M4_LPIT_IRQn                 = 22,               /**< Low-Power Periodic Interrupt Timer */
+  Reserved39_IRQn              = 23,               /**< Reserved */
+  Reserved40_IRQn              = 24,               /**< Reserved */
+  M4_LPUART_IRQn               = 25,               /**< Low Power UART */
+  Reserved42_IRQn              = 26,               /**< Reserved */
+  M4_LPI2C_IRQn                = 27,               /**< Low-Power I2C - Logical OR of master and slave interrupts */
+  Reserved44_IRQn              = 28,               /**< Reserved */
+  M4_MU0_B0_IRQn               = 29,               /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 0, Logical OR of all general-purpose, TX, and RX interrupts */
+  Reserved46_IRQn              = 30,               /**< Reserved */
+  Reserved47_IRQn              = 31,               /**< Reserved */
+  IRQSTEER_0_IRQn              = 32,               /**< External interrupt 0 */
+  IRQSTEER_1_IRQn              = 33,               /**< External interrupt 1 */
+  IRQSTEER_2_IRQn              = 34,               /**< External interrupt 2 */
+  IRQSTEER_3_IRQn              = 35,               /**< External interrupt 3 */
+  IRQSTEER_4_IRQn              = 36,               /**< External interrupt 4 */
+  IRQSTEER_5_IRQn              = 37,               /**< External interrupt 5 */
+  IRQSTEER_6_IRQn              = 38,               /**< External interrupt 6 */
+  IRQSTEER_7_IRQn              = 39,               /**< External interrupt 7 */
+  Reserved56_IRQn              = 40,               /**< Reserved */
+  Reserved57_IRQn              = 41,               /**< Reserved */
+  Reserved58_IRQn              = 42,               /**< Reserved */
+  Reserved59_IRQn              = 43,               /**< Reserved */
+  M4_MU0_B1_IRQn               = 44,               /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 1, Logical OR of all general-purpose, TX, and RX interrupts */
+  M4_MU0_B2_IRQn               = 45,               /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 2, Logical OR of all general-purpose, TX, and RX interrupts */
+  M4_MU0_B3_IRQn               = 46,               /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 3, Logical OR of all general-purpose, TX, and RX interrupts */
+  Reserved63_IRQn              = 47,               /**< Reserved */
+  Reserved64_IRQn              = 48,               /**< Reserved */
+  M4_MU1_A_IRQn                = 49,               /**< Messaging Unit 1 (IPC with System Controller) - Side A (MCU), Logical OR of all general-purpose, TX, and RX interrupts */
+  M4_SW_IRQn                   = 50,               /**< Software interrupt (asserted/cleared via NVIC registers, INTISR[50] input tied low) */
+  A35_NINTERRIRQ_IRQn          = 83,               /**< Shared Int Source nINTERRIRQ from A35 Sub-System */
+  A35_NEXTERRIRQ_IRQn          = 84,               /**< Shared Int Source nEXTERRIRQ from A35 Sub-System */
+  M4_INT_OUT0_IRQn             = 99,               /**< Shared Int Source INT_OUT[0] from M4 Sub-System */
+  M4_INT_OUT1_IRQn             = 100,              /**< Shared Int Source INT_OUT[1] from M4 Sub-System */
+  M4_INT_OUT2_IRQn             = 101,              /**< Shared Int Source INT_OUT[2] from M4 Sub-System */
+  M4_INT_OUT3_IRQn             = 102,              /**< Shared Int Source INT_OUT[3] from M4 Sub-System */
+  M4_INT_OUT4_IRQn             = 103,              /**< Shared Int Source INT_OUT[4] from M4 Sub-System */
+  M4_INT_OUT5_IRQn             = 104,              /**< Shared Int Source INT_OUT[5] from M4 Sub-System */
+  M4_INT_OUT6_IRQn             = 105,              /**< Shared Int Source INT_OUT[6] from M4 Sub-System */
+  M4_INT_OUT7_IRQn             = 106,              /**< Shared Int Source INT_OUT[7] from M4 Sub-System */
+  DISPLAY0_INT_OUT0_IRQn       = 123,              /**< Shared Int Source INT_OUT[0] from Display0 Sub-System */
+  DISPLAY0_INT_OUT1_IRQn       = 124,              /**< Shared Int Source INT_OUT[1] from Display0 Sub-System */
+  DISPLAY0_INT_OUT2_IRQn       = 125,              /**< Shared Int Source INT_OUT[2] from Display0 Sub-System */
+  DISPLAY0_INT_OUT3_IRQn       = 126,              /**< Shared Int Source INT_OUT[3] from Display0 Sub-System */
+  DISPLAY0_INT_OUT4_IRQn       = 127,              /**< Shared Int Source INT_OUT[4] from Display0 Sub-System */
+  DISPLAY0_INT_OUT5_IRQn       = 128,              /**< Shared Int Source INT_OUT[5] from Display0 Sub-System */
+  DISPLAY0_INT_OUT6_IRQn       = 129,              /**< Shared Int Source INT_OUT[6] from Display0 Sub-System */
+  DISPLAY0_INT_OUT7_IRQn       = 130,              /**< Shared Int Source INT_OUT[7] from Display0 Sub-System */
+  DISPLAY0_RESERVED_IRQn       = 131,              /**< Shared Int Source Reserved from Display0 Sub-System */
+  DISPLAY0_INT_OUT9_IRQn       = 132,              /**< Shared Int Source INT_OUT[9] from Display0 Sub-System */
+  DISPLAY0_INT_OUT10_IRQn      = 133,              /**< Shared Int Source INT_OUT[10] from Display0 Sub-System */
+  DISPLAY0_INT_OUT11_IRQn      = 134,              /**< Shared Int Source INT_OUT[11] from Display0 Sub-System */
+  DISPLAY0_INT_OUT12_IRQn      = 135,              /**< Shared Int Source INT_OUT[12] from Display0 Sub-System */
+  MIPI_DSI0_INT_OUT_IRQn       = 142,              /**< Shared Int Source INT_OUT from MIPI_DSI0 Sub-System */
+  MIPI_DSI1_INT_OUT_IRQn       = 143,              /**< Shared Int Source INT_OUT from MIPI_DSI1 Sub-System */
+  LCD_MOD_INT_IRQn             = 145,              /**< Shared Int Source INT_OUT from ADMA Sub-System */
+  LCD_PWM_INT_IRQn             = 146,              /**< Shared Int Source INT_OUT from ADMA Sub-System */
+  GPU0_XAQ2_INTR_IRQn          = 147,              /**< Shared Int Source xaq2_intr from GPU0 Sub-System */
+  ADMA_EDMA2_INT_IRQn          = 149,              /**< Shared Int Source eDMA2_INT from ADMA Sub-System */
+  ADMA_EDMA2_ERR_INT_IRQn      = 150,              /**< Shared Int Source eDMA2_ERR_INT from ADMA Sub-System */
+  ADMA_EDMA3_INT_IRQn          = 151,              /**< Shared Int Source eDMA3_INT from ADMA Sub-System */
+  ADMA_EDMA3_ERR_INT_IRQn      = 152,              /**< Shared Int Source eDMA3_ERR_INT from ADMA Sub-System */
+  LSIO_GPT0_INT_IRQn           = 163,              /**< Shared Int Source GPT0_INT from LSIO Sub-System */
+  LSIO_GPT1_INT_IRQn           = 164,              /**< Shared Int Source GPT1_INT from LSIO Sub-System */
+  LSIO_GPT2_INT_IRQn           = 165,              /**< Shared Int Source GPT2_INT from LSIO Sub-System */
+  LSIO_GPT3_INT_IRQn           = 166,              /**< Shared Int Source GPT3_INT from LSIO Sub-System */
+  LSIO_GPT4_INT_IRQn           = 167,              /**< Shared Int Source GPT4_INT from LSIO Sub-System */
+  LSIO_KPP_INT_IRQn            = 168,              /**< Shared Int Source KPP_INT from LSIO Sub-System */
+  LSIO_OCTASPI0_INT_IRQn       = 175,              /**< Shared Int Source OctaSPI0_INT from LSIO Sub-System */
+  LSIO_OCTASPI1_INT_IRQn       = 176,              /**< Shared Int Source OctaSPI1_INT from LSIO Sub-System */
+  LSIO_PWM0_INT_IRQn           = 177,              /**< Shared Int Source PWM0_INT from LSIO Sub-System */
+  LSIO_PWM1_INT_IRQn           = 178,              /**< Shared Int Source PWM1_INT from LSIO Sub-System */
+  LSIO_PWM2_INT_IRQn           = 179,              /**< Shared Int Source PWM2_INT from LSIO Sub-System */
+  LSIO_PWM3_INT_IRQn           = 180,              /**< Shared Int Source PWM3_INT from LSIO Sub-System */
+  LSIO_PWM4_INT_IRQn           = 181,              /**< Shared Int Source PWM4_INT from LSIO Sub-System */
+  LSIO_PWM5_INT_IRQn           = 182,              /**< Shared Int Source PWM5_INT from LSIO Sub-System */
+  LSIO_PWM6_INT_IRQn           = 183,              /**< Shared Int Source PWM6_INT from LSIO Sub-System */
+  LSIO_PWM7_INT_IRQn           = 184,              /**< Shared Int Source PWM7_INT from LSIO Sub-System */
+  HSIO_PCIEB_MSI_CTRL_INT_IRQn = 185,              /**< Shared Int Source PCIeB_MSI_CTRL_INT from HSIO Sub-System */
+  HSIO_PCIEB_CLK_REQ_INT_IRQn  = 186,              /**< Shared Int Source PCIeB_CLK_REQ_INT from HSIO Sub-System */
+  HSIO_PCIEB_DMA_INT_IRQn      = 187,              /**< Shared Int Source PCIeB_DMA_INT from HSIO Sub-System */
+  HSIO_PCIEB_INT_D_IRQn        = 188,              /**< Shared Int Source PCIeB_INT_D from HSIO Sub-System */
+  HSIO_PCIEB_INT_C_IRQn        = 189,              /**< Shared Int Source PCIeB_INT_C from HSIO Sub-System */
+  HSIO_PCIEB_INT_B_IRQn        = 190,              /**< Shared Int Source PCIeB_INT_B from HSIO Sub-System */
+  HSIO_PCIEB_INT_A_IRQn        = 191,              /**< Shared Int Source PCIeB_INT_A from HSIO Sub-System */
+  HSIO_PCIEB_SMLH_REQ_RST_IRQn = 192,              /**< Shared Int Source PCIeB_SMLH_REQ_RST from HSIO Sub-System */
+  HSIO_PCIEB_GPIO_WAKEUP0_IRQn = 193,              /**< Shared Int Source PCIeB_GPIO_WAKEUP[0] from HSIO Sub-System */
+  HSIO_PCIEB_GPIO_WAKEUP1_IRQn = 194,              /**< Shared Int Source PCIeB_GPIO_WAKEUP[1] from HSIO Sub-System */
+  SCU_INT_OUT0_IRQn            = 195,              /**< Shared Int Source INT_OUT[0] from SCU Sub-System */
+  SCU_INT_OUT1_IRQn            = 196,              /**< Shared Int Source INT_OUT[1] from SCU Sub-System */
+  SCU_INT_OUT2_IRQn            = 197,              /**< Shared Int Source INT_OUT[2] from SCU Sub-System */
+  SCU_INT_OUT3_IRQn            = 198,              /**< Shared Int Source INT_OUT[3] from SCU Sub-System */
+  SCU_INT_OUT4_IRQn            = 199,              /**< Shared Int Source INT_OUT[4] from SCU Sub-System */
+  SCU_INT_OUT5_IRQn            = 200,              /**< Shared Int Source INT_OUT[5] from SCU Sub-System */
+  SCU_INT_OUT6_IRQn            = 201,              /**< Shared Int Source INT_OUT[6] from SCU Sub-System */
+  SCU_INT_OUT7_IRQn            = 202,              /**< Shared Int Source INT_OUT[7] from SCU Sub-System */
+  SCU_SYS_COUNT_INT0_IRQn      = 203,              /**< Shared Int Source SYS_COUNT_INT0 from SCU Sub-System */
+  SCU_SYS_COUNT_INT1_IRQn      = 204,              /**< Shared Int Source SYS_COUNT_INT1 from SCU Sub-System */
+  SCU_SYS_COUNT_INT2_IRQn      = 205,              /**< Shared Int Source SYS_COUNT_INT2 from SCU Sub-System */
+  SCU_SYS_COUNT_INT3_IRQn      = 206,              /**< Shared Int Source SYS_COUNT_INT3 from SCU Sub-System */
+  DRC_ECC_CORRECT_INT_IRQn     = 211,              /**< Shared Int Source ECC_CORRECT_INT from DRC Sub-System */
+  DRC_ECC_NCORRECT_INT_IRQn    = 212,              /**< Shared Int Source ECC_NCORRECT_INT from DRC Sub-System */
+  DRC_SBR_DONE_INT_IRQn        = 213,              /**< Shared Int Source SBR_DONE_INT from DRC Sub-System */
+  DRC_PERF_CNT_INT_IRQn        = 214,              /**< Shared Int Source PERF_CNT_INT from DRC Sub-System */
+  LSIO_GPIO_INT0_IRQn          = 219,              /**< Shared Int Source GPIO_INT[0] from LSIO Sub-System */
+  LSIO_GPIO_INT1_IRQn          = 220,              /**< Shared Int Source GPIO_INT[1] from LSIO Sub-System */
+  LSIO_GPIO_INT2_IRQn          = 221,              /**< Shared Int Source GPIO_INT[2] from LSIO Sub-System */
+  LSIO_GPIO_INT3_IRQn          = 222,              /**< Shared Int Source GPIO_INT[3] from LSIO Sub-System */
+  LSIO_GPIO_INT4_IRQn          = 223,              /**< Shared Int Source GPIO_INT[4] from LSIO Sub-System */
+  LSIO_GPIO_INT5_IRQn          = 224,              /**< Shared Int Source GPIO_INT[5] from LSIO Sub-System */
+  LSIO_GPIO_INT6_IRQn          = 225,              /**< Shared Int Source GPIO_INT[6] from LSIO Sub-System */
+  LSIO_GPIO_INT7_IRQn          = 226,              /**< Shared Int Source GPIO_INT[7] from LSIO Sub-System */
+  LSIO_MU0_INT_IRQn            = 259,              /**< Shared Int Source MU0_INT from LSIO Sub-System */
+  LSIO_MU1_INT_IRQn            = 260,              /**< Shared Int Source MU1_INT from LSIO Sub-System */
+  LSIO_MU2_INT_IRQn            = 261,              /**< Shared Int Source MU2_INT from LSIO Sub-System */
+  LSIO_MU3_INT_IRQn            = 262,              /**< Shared Int Source MU3_INT from LSIO Sub-System */
+  LSIO_MU4_INT_IRQn            = 263,              /**< Shared Int Source MU4_INT from LSIO Sub-System */
+  LSIO_MU5_INT_A_IRQn          = 267,              /**< Shared Int Source MU5_INT_A from LSIO Sub-System */
+  LSIO_MU6_INT_A_IRQn          = 268,              /**< Shared Int Source MU6_INT_A from LSIO Sub-System */
+  LSIO_MU7_INT_A_IRQn          = 269,              /**< Shared Int Source MU7_INT_A from LSIO Sub-System */
+  LSIO_MU8_INT_A_IRQn          = 270,              /**< Shared Int Source MU8_INT_A from LSIO Sub-System */
+  LSIO_MU9_INT_A_IRQn          = 271,              /**< Shared Int Source MU9_INT_A from LSIO Sub-System */
+  LSIO_MU10_INT_A_IRQn         = 272,              /**< Shared Int Source MU10_INT_A from LSIO Sub-System */
+  LSIO_MU11_INT_A_IRQn         = 273,              /**< Shared Int Source MU11_INT_A from LSIO Sub-System */
+  LSIO_MU12_INT_A_IRQn         = 274,              /**< Shared Int Source MU12_INT_A from LSIO Sub-System */
+  LSIO_MU13_INT_A_IRQn         = 275,              /**< Shared Int Source MU13_INT_A from LSIO Sub-System */
+  LSIO_MU5_INT_B_IRQn          = 283,              /**< Shared Int Source MU5_INT_B from LSIO Sub-System */
+  LSIO_MU6_INT_B_IRQn          = 284,              /**< Shared Int Source MU6_INT_B from LSIO Sub-System */
+  LSIO_MU7_INT_B_IRQn          = 285,              /**< Shared Int Source MU7_INT_B from LSIO Sub-System */
+  LSIO_MU8_INT_B_IRQn          = 286,              /**< Shared Int Source MU8_INT_B from LSIO Sub-System */
+  LSIO_MU9_INT_B_IRQn          = 287,              /**< Shared Int Source MU9_INT_B from LSIO Sub-System */
+  LSIO_MU10_INT_B_IRQn         = 288,              /**< Shared Int Source MU10_INT_B from LSIO Sub-System */
+  LSIO_MU11_INT_B_IRQn         = 289,              /**< Shared Int Source MU11_INT_B from LSIO Sub-System */
+  LSIO_MU12_INT_B_IRQn         = 290,              /**< Shared Int Source MU12_INT_B from LSIO Sub-System */
+  LSIO_MU13_INT_B_IRQn         = 291,              /**< Shared Int Source MU13_INT_B from LSIO Sub-System */
+  ADMA_SPI0_INT_IRQn           = 299,              /**< Shared Int Source SPI0_INT from ADMA Sub-System */
+  ADMA_SPI1_INT_IRQn           = 300,              /**< Shared Int Source SPI1_INT from ADMA Sub-System */
+  ADMA_SPI2_INT_IRQn           = 301,              /**< Shared Int Source SPI2_INT from ADMA Sub-System */
+  ADMA_SPI3_INT_IRQn           = 302,              /**< Shared Int Source SPI3_INT from ADMA Sub-System */
+  ADMA_I2C0_INT_IRQn           = 303,              /**< Shared Int Source I2C0_INT from ADMA Sub-System */
+  ADMA_I2C1_INT_IRQn           = 304,              /**< Shared Int Source I2C1_INT from ADMA Sub-System */
+  ADMA_I2C2_INT_IRQn           = 305,              /**< Shared Int Source I2C2_INT from ADMA Sub-System */
+  ADMA_I2C3_INT_IRQn           = 306,              /**< Shared Int Source I2C3_INT from ADMA Sub-System */
+  ADMA_UART0_INT_IRQn          = 308,              /**< Shared Int Source UART0_INT from ADMA Sub-System */
+  ADMA_UART1_INT_IRQn          = 309,              /**< Shared Int Source UART1_INT from ADMA Sub-System */
+  ADMA_UART2_INT_IRQn          = 310,              /**< Shared Int Source UART2_INT from ADMA Sub-System */
+  ADMA_UART3_INT_IRQn          = 311,              /**< Shared Int Source UART3_INT from ADMA Sub-System */
+  CONNECTIVITY_USDHC0_INT_IRQn = 315,              /**< Shared Int Source uSDHC0_INT from Connectivity Sub-System */
+  CONNECTIVITY_USDHC1_INT_IRQn = 316,              /**< Shared Int Source uSDHC1_INT from Connectivity Sub-System */
+  CONNECTIVITY_USDHC2_INT_IRQn = 317,              /**< Shared Int Source uSDHC2_INT from Connectivity Sub-System */
+  ADMA_FLEXCAN0_INT_IRQn       = 318,              /**< Shared Int Source FlexCAN0_INT from ADMA Sub-System */
+  ADMA_FLEXCAN1_INT_IRQn       = 319,              /**< Shared Int Source FlexCAN1_INT from ADMA Sub-System */
+  ADMA_FLEXCAN2_INT_IRQn       = 320,              /**< Shared Int Source FlexCAN2_INT from ADMA Sub-System */
+  ADMA_FTM0_INT_IRQn           = 321,              /**< Shared Int Source FTM0_INT from ADMA Sub-System */
+  ADMA_FTM1_INT_IRQn           = 322,              /**< Shared Int Source FTM1_INT from ADMA Sub-System */
+  ADMA_ADC0_INT_IRQn           = 323,              /**< Shared Int Source ADC0_INT from ADMA Sub-System */
+  ADMA_EXTERNAL_DMA_INT_0_IRQn = 325,              /**< Shared Int Source EXTERNAL_DMA_INT_0 from ADMA Sub-System */
+  ADMA_EXTERNAL_DMA_INT_1_IRQn = 326,              /**< Shared Int Source EXTERNAL_DMA_INT_1 from ADMA Sub-System */
+  ADMA_EXTERNAL_DMA_INT_2_IRQn = 327,              /**< Shared Int Source EXTERNAL_DMA_INT_2 from ADMA Sub-System */
+  ADMA_EXTERNAL_DMA_INT_3_IRQn = 328,              /**< Shared Int Source EXTERNAL_DMA_INT_3 from ADMA Sub-System */
+  ADMA_EXTERNAL_DMA_INT_4_IRQn = 329,              /**< Shared Int Source EXTERNAL_DMA_INT_4 from ADMA Sub-System */
+  ADMA_EXTERNAL_DMA_INT_5_IRQn = 330,              /**< Shared Int Source EXTERNAL_DMA_INT_5 from ADMA Sub-System */
+  CONNECTIVITY_ENET0_FRAME1_INT_IRQn = 339,        /**< Shared Int Source ENET0_FRAME1_INT from Connectivity Sub-System */
+  CONNECTIVITY_ENET0_FRAME2_INT_IRQn = 340,        /**< Shared Int Source ENET0_FRAME2_INT from Connectivity Sub-System */
+  CONNECTIVITY_ENET0_FRAME0_EVENT_INT_IRQn = 341,  /**< Shared Int Source ENET0_FRAME0_EVENT_INT from Connectivity Sub-System */
+  CONNECTIVITY_ENET0_TIMER_INT_IRQn = 342,         /**< Shared Int Source ENET0_TIMER_INT from Connectivity Sub-System */
+  CONNECTIVITY_ENET1_FRAME1_INT_IRQn = 343,        /**< Shared Int Source ENET1_FRAME1_INT from Connectivity Sub-System */
+  CONNECTIVITY_ENET1_FRAME2_INT_IRQn = 344,        /**< Shared Int Source ENET1_FRAME2_INT from Connectivity Sub-System */
+  CONNECTIVITY_ENET1_FRAME0_EVENT_INT_IRQn = 345,  /**< Shared Int Source ENET1_FRAME0_EVENT_INT from Connectivity Sub-System */
+  CONNECTIVITY_ENET1_TIMER_INT_IRQn = 346,         /**< Shared Int Source ENET1_TIMER_INT from Connectivity Sub-System */
+  CONNECTIVITY_DTCP_INT_IRQn   = 347,              /**< Shared Int Source DTCP_INT from Connectivity Sub-System */
+  CONNECTIVITY_MLB_INT_IRQn    = 348,              /**< Shared Int Source MLB_INT from Connectivity Sub-System */
+  CONNECTIVITY_MLB_AHB_INT_IRQn = 349,             /**< Shared Int Source MLB_AHB_INT from Connectivity Sub-System */
+  CONNECTIVITY_USB_OTG_INT_IRQn = 350,             /**< Shared Int Source USB_OTG_INT from Connectivity Sub-System */
+  CONNECTIVITY_USB_HOST_INT_IRQn = 351,            /**< Shared Int Source USB_HOST_INT from Connectivity Sub-System */
+  CONNECTIVITY_UTMI_INT_IRQn   = 352,              /**< Shared Int Source UTMI_INT from Connectivity Sub-System */
+  CONNECTIVITY_WAKEUP_INT_IRQn = 353,              /**< Shared Int Source WAKEUP_INT from Connectivity Sub-System */
+  CONNECTIVITY_USB3_INT_IRQn   = 354,              /**< Shared Int Source USB3_INT from Connectivity Sub-System */
+  CONNECTIVITY_ND_FLASH_BCH_INT_IRQn = 355,        /**< Shared Int Source ND_FLASH_BCH_INT from Connectivity Sub-System */
+  CONNECTIVITY_ND_FLASH_GPMI_INT_IRQn = 356,       /**< Shared Int Source ND_FLASH_GPMI_INT from Connectivity Sub-System */
+  CONNECTIVITY_APBHDMA_IRQn    = 357,              /**< Shared Int Source APBHDMA from Connectivity Sub-System */
+  CONNECTIVITY_DMA_INT_IRQn    = 358,              /**< Shared Int Source DMA_INT from Connectivity Sub-System */
+  CONNECTIVITY_DMA_ERR_INT_IRQn = 359,             /**< Shared Int Source DMA_ERR_INT from Connectivity Sub-System */
+  IMAGING_MSI_INT_IRQn         = 371,              /**< Shared Int Source MSI_INT from Imaging Sub-System */
+  IMAGING_PDMA_STREAM0_INT_IRQn = 380,             /**< Shared Int Source PDMA_STREAM0_INT from Imaging Sub-System */
+  IMAGING_PDMA_STREAM1_INT_IRQn = 381,             /**< Shared Int Source PDMA_STREAM1_INT from Imaging Sub-System */
+  IMAGING_PDMA_STREAM2_INT_IRQn = 382,             /**< Shared Int Source PDMA_STREAM2_INT from Imaging Sub-System */
+  IMAGING_PDMA_STREAM3_INT_IRQn = 383,             /**< Shared Int Source PDMA_STREAM3_INT from Imaging Sub-System */
+  IMAGING_PDMA_STREAM4_INT_IRQn = 384,             /**< Shared Int Source PDMA_STREAM4_INT from Imaging Sub-System */
+  IMAGING_PDMA_STREAM5_INT_IRQn = 385,             /**< Shared Int Source PDMA_STREAM5_INT from Imaging Sub-System */
+  IMAGING_PDMA_STREAM6_INT_IRQn = 386,             /**< Shared Int Source PDMA_STREAM6_INT from Imaging Sub-System */
+  IMAGING_PDMA_STREAM7_INT_IRQn = 387,             /**< Shared Int Source PDMA_STREAM7_INT from Imaging Sub-System */
+  IMAGING_MJPEG_ENC0_INT_IRQn  = 388,              /**< Shared Int Source MJPEG_ENC0_INT from Imaging Sub-System */
+  IMAGING_MJPEG_ENC1_INT_IRQn  = 389,              /**< Shared Int Source MJPEG_ENC1_INT from Imaging Sub-System */
+  IMAGING_MJPEG_ENC2_INT_IRQn  = 390,              /**< Shared Int Source MJPEG_ENC2_INT from Imaging Sub-System */
+  IMAGING_MJPEG_ENC3_INT_IRQn  = 391,              /**< Shared Int Source MJPEG_ENC3_INT from Imaging Sub-System */
+  IMAGING_MJPEG_DEC0_INT_IRQn  = 392,              /**< Shared Int Source MJPEG_DEC0_INT from Imaging Sub-System */
+  IMAGING_MJPEG_DEC1_INT_IRQn  = 393,              /**< Shared Int Source MJPEG_DEC1_INT from Imaging Sub-System */
+  IMAGING_MJPEG_DEC2_INT_IRQn  = 394,              /**< Shared Int Source MJPEG_DEC2_INT from Imaging Sub-System */
+  IMAGING_MJPEG_DEC3_INT_IRQn  = 395,              /**< Shared Int Source MJPEG_DEC3_INT from Imaging Sub-System */
+  ADMA_SAI0_MOD_INT_IRQn       = 397,              /**< Shared Int Source SAI0_MOD_INT from ADMA Sub-System */
+  ADMA_SAI0_DMA_INT_IRQn       = 398,              /**< Shared Int Source SAI0_DMA_INT from ADMA Sub-System */
+  ADMA_SAI1_MOD_INT_IRQn       = 399,              /**< Shared Int Source SAI1_MOD_INT from ADMA Sub-System */
+  ADMA_SAI1_DMA_INT_IRQn       = 400,              /**< Shared Int Source SAI1_DMA_INT from ADMA Sub-System */
+  ADMA_SAI2_MOD_INT_IRQn       = 401,              /**< Shared Int Source SAI2_MOD_INT from ADMA Sub-System */
+  ADMA_SAI2_DMA_INT_IRQn       = 402,              /**< Shared Int Source SAI2_DMA_INT from ADMA Sub-System */
+  MIPI_CSI0_OUT_INT_IRQn       = 403,              /**< Shared Int Source OUT_INT from MIPI_CSI0 Sub-System */
+  ADMA_SAI3_MOD_INT_IRQn       = 406,              /**< Shared Int Source SAI3_MOD_INT from ADMA Sub-System */
+  ADMA_SAI3_DMA_INT_IRQn       = 407,              /**< Shared Int Source SAI3_DMA_INT from ADMA Sub-System */
+  ADMA_SAI4_MOD_INT_IRQn       = 412,              /**< Shared Int Source SAI4_MOD_INT from ADMA Sub-System */
+  ADMA_SAI4_DMA_INT_IRQn       = 413,              /**< Shared Int Source SAI4_DMA_INT from ADMA Sub-System */
+  ADMA_SAI5_MOD_INT_IRQn       = 414,              /**< Shared Int Source SAI5_MOD_INT from ADMA Sub-System */
+  ADMA_SAI5_DMA_INT_IRQn       = 415,              /**< Shared Int Source SAI5_DMA_INT from ADMA Sub-System */
+  ADMA_SPI0_MOD_INT_IRQn       = 419,              /**< Shared Int Source SPI0_MOD_INT from ADMA Sub-System */
+  ADMA_SPI1_MOD_INT_IRQn       = 420,              /**< Shared Int Source SPI1_MOD_INT from ADMA Sub-System */
+  ADMA_SPI2_MOD_INT_IRQn       = 421,              /**< Shared Int Source SPI2_MOD_INT from ADMA Sub-System */
+  ADMA_SPI3_MOD_INT_IRQn       = 422,              /**< Shared Int Source SPI3_MOD_INT from ADMA Sub-System */
+  ADMA_I2C0_MOD_INT_IRQn       = 423,              /**< Shared Int Source I2C0_MOD_INT from ADMA Sub-System */
+  ADMA_I2C1_MOD_INT_IRQn       = 424,              /**< Shared Int Source I2C1_MOD_INT from ADMA Sub-System */
+  ADMA_I2C2_MOD_INT_IRQn       = 425,              /**< Shared Int Source I2C2_MOD_INT from ADMA Sub-System */
+  ADMA_I2C3_MOD_INT_IRQn       = 426,              /**< Shared Int Source I2C3_MOD_INT from ADMA Sub-System */
+  ADMA_UART0_MOD_INT_IRQn      = 428,              /**< Shared Int Source UART0_MOD_INT from ADMA Sub-System */
+  ADMA_UART1_MOD_INT_IRQn      = 429,              /**< Shared Int Source UART1_MOD_INT from ADMA Sub-System */
+  ADMA_UART2_MOD_INT_IRQn      = 430,              /**< Shared Int Source UART2_MOD_INT from ADMA Sub-System */
+  ADMA_UART3_MOD_INT_IRQn      = 431,              /**< Shared Int Source UART3_MOD_INT from ADMA Sub-System */
+  ADMA_FLEXCAN0_MOD_INT_IRQn   = 435,              /**< Shared Int Source FLEXCAN0_MOD_INT from ADMA Sub-System */
+  ADMA_FLEXCAN1_MOD_INT_IRQn   = 436,              /**< Shared Int Source FLEXCAN1_MOD_INT from ADMA Sub-System */
+  ADMA_FLEXCAN2_MOD_INT_IRQn   = 437,              /**< Shared Int Source FLEXCAN2_MOD_INT from ADMA Sub-System */
+  ADMA_FTM0_MOD_INT_IRQn       = 438,              /**< Shared Int Source FTM0_MOD_INT from ADMA Sub-System */
+  ADMA_FTM1_MOD_INT_IRQn       = 439,              /**< Shared Int Source FTM1_MOD_INT from ADMA Sub-System */
+  ADMA_ADC0_MOD_INT_IRQn       = 440,              /**< Shared Int Source ADC0_MOD_INT from ADMA Sub-System */
+  ADMA_FLEXCAN0_DMA_INT_IRQn   = 442,              /**< Shared Int Source FLEXCAN0_DMA_INT from ADMA Sub-System */
+  ADMA_FLEXCAN1_DMA_INT_IRQn   = 443,              /**< Shared Int Source FLEXCAN1_DMA_INT from ADMA Sub-System */
+  ADMA_FLEXCAN2_DMA_INT_IRQn   = 444,              /**< Shared Int Source FLEXCAN2_DMA_INT from ADMA Sub-System */
+  ADMA_FTM0_DMA_INT_IRQn       = 445,              /**< Shared Int Source FTM0_DMA_INT from ADMA Sub-System */
+  ADMA_FTM1_DMA_INT_IRQn       = 446,              /**< Shared Int Source FTM1_DMA_INT from ADMA Sub-System */
+  ADMA_ADC0_DMA_INT_IRQn       = 447,              /**< Shared Int Source ADC0_DMA_INT from ADMA Sub-System */
+  ADMA_EDMA0_INT_IRQn          = 451,              /**< Shared Int Source eDMA0_INT from ADMA Sub-System */
+  ADMA_EDMA0_ERR_INT_IRQn      = 452,              /**< Shared Int Source eDMA0_ERR_INT from ADMA Sub-System */
+  ADMA_EDMA1_INT_IRQn          = 453,              /**< Shared Int Source eDMA1_INT from ADMA Sub-System */
+  ADMA_EDMA1_ERR_INT_IRQn      = 454,              /**< Shared Int Source eDMA1_ERR_INT from ADMA Sub-System */
+  ADMA_ASRC0_INT1_IRQn         = 455,              /**< Shared Int Source ASRC0_INT1 from ADMA Sub-System */
+  ADMA_ASRC0_INT2_IRQn         = 456,              /**< Shared Int Source ASRC0_INT2 from ADMA Sub-System */
+  ADMA_DMA0_CH0_INT_IRQn       = 457,              /**< Shared Int Source DMA0_CH0_INT from ADMA Sub-System */
+  ADMA_DMA0_CH1_INT_IRQn       = 458,              /**< Shared Int Source DMA0_CH1_INT from ADMA Sub-System */
+  ADMA_DMA0_CH2_INT_IRQn       = 459,              /**< Shared Int Source DMA0_CH2_INT from ADMA Sub-System */
+  ADMA_DMA0_CH3_INT_IRQn       = 460,              /**< Shared Int Source DMA0_CH3_INT from ADMA Sub-System */
+  ADMA_DMA0_CH4_INT_IRQn       = 461,              /**< Shared Int Source DMA0_CH4_INT from ADMA Sub-System */
+  ADMA_DMA0_CH5_INT_IRQn       = 462,              /**< Shared Int Source DMA0_CH5_INT from ADMA Sub-System */
+  ADMA_ASRC1_INT1_IRQn         = 463,              /**< Shared Int Source ASRC1_INT1 from ADMA Sub-System */
+  ADMA_ASRC1_INT2_IRQn         = 464,              /**< Shared Int Source ASRC1_INT2 from ADMA Sub-System */
+  ADMA_DMA1_CH0_INT_IRQn       = 465,              /**< Shared Int Source DMA1_CH0_INT from ADMA Sub-System */
+  ADMA_DMA1_CH1_INT_IRQn       = 466,              /**< Shared Int Source DMA1_CH1_INT from ADMA Sub-System */
+  ADMA_DMA1_CH2_INT_IRQn       = 467,              /**< Shared Int Source DMA1_CH2_INT from ADMA Sub-System */
+  ADMA_DMA1_CH3_INT_IRQn       = 468,              /**< Shared Int Source DMA1_CH3_INT from ADMA Sub-System */
+  ADMA_DMA1_CH4_INT_IRQn       = 469,              /**< Shared Int Source DMA1_CH4_INT from ADMA Sub-System */
+  ADMA_DMA1_CH5_INT_IRQn       = 470,              /**< Shared Int Source DMA1_CH5_INT from ADMA Sub-System */
+  ADMA_ESAI0_INT_IRQn          = 471,              /**< Shared Int Source ESAI0_INT from ADMA Sub-System */
+  ADMA_GPT0_INT_IRQn           = 474,              /**< Shared Int Source GPT0_INT from ADMA Sub-System */
+  ADMA_GPT1_INT_IRQn           = 475,              /**< Shared Int Source GPT1_INT from ADMA Sub-System */
+  ADMA_GPT2_INT_IRQn           = 476,              /**< Shared Int Source GPT2_INT from ADMA Sub-System */
+  ADMA_GPT3_INT_IRQn           = 477,              /**< Shared Int Source GPT3_INT from ADMA Sub-System */
+  ADMA_GPT4_INT_IRQn           = 478,              /**< Shared Int Source GPT4_INT from ADMA Sub-System */
+  ADMA_GPT5_INT_IRQn           = 479,              /**< Shared Int Source GPT5_INT from ADMA Sub-System */
+  ADMA_SAI0_INT_IRQn           = 480,              /**< Shared Int Source SAI0_INT from ADMA Sub-System */
+  ADMA_SAI1_INT_IRQn           = 481,              /**< Shared Int Source SAI1_INT from ADMA Sub-System */
+  ADMA_SAI2_INT_IRQn           = 482,              /**< Shared Int Source SAI2_INT from ADMA Sub-System */
+  ADMA_SAI3_INT_IRQn           = 483,              /**< Shared Int Source SAI3_INT from ADMA Sub-System */
+  ADMA_SAI4_INT_IRQn           = 486,              /**< Shared Int Source SAI4_INT from ADMA Sub-System */
+  ADMA_SAI5_INT_IRQn           = 487,              /**< Shared Int Source SAI5_INT from ADMA Sub-System */
+  ADMA_SPDIF0_RX_INT_IRQn      = 488,              /**< Shared Int Source SPDIF0_RX_INT from ADMA Sub-System */
+  ADMA_SPDIF0_TX_INT_IRQn      = 489,              /**< Shared Int Source SPDIF0_TX_INT from ADMA Sub-System */
+  ADMA_ESAI0_MOD_INT_IRQn      = 492,              /**< Shared Int Source ESAI0_MOD_INT from ADMA Sub-System */
+  ADMA_ESAI0_DMA_INT_IRQn      = 493,              /**< Shared Int Source ESAI0_DMA_INT from ADMA Sub-System */
+  ADMA_SPI0_DMA_RX_INT_IRQn    = 499,              /**< Shared Int Source SPI0_DMA_RX_INT from ADMA Sub-System */
+  ADMA_SPI0_DMA_TX_INT_IRQn    = 500,              /**< Shared Int Source SPI0_DMA_TX_INT from ADMA Sub-System */
+  ADMA_SPI1_DMA_RX_INT_IRQn    = 501,              /**< Shared Int Source SPI1_DMA_RX_INT from ADMA Sub-System */
+  ADMA_SPI1_DMA_TX_INT_IRQn    = 502,              /**< Shared Int Source SPI1_DMA_TX_INT from ADMA Sub-System */
+  ADMA_SPI2_DMA_RX_INT_IRQn    = 503,              /**< Shared Int Source SPI2_DMA_RX_INT from ADMA Sub-System */
+  ADMA_SPI2_DMA_TX_INT_IRQn    = 504,              /**< Shared Int Source SPI2_DMA_TX_INT from ADMA Sub-System */
+  ADMA_SPI3_DMA_RX_INT_IRQn    = 505,              /**< Shared Int Source SPI3_DMA_RX_INT from ADMA Sub-System */
+  ADMA_SPI3_DMA_TX_INT_IRQn    = 506,              /**< Shared Int Source SPI3_DMA_TX_INT from ADMA Sub-System */
+  ADMA_I2C0_DMA_RX_INT_IRQn    = 507,              /**< Shared Int Source I2C0_DMA_RX_INT from ADMA Sub-System */
+  ADMA_I2C0_DMA_TX_INT_IRQn    = 508,              /**< Shared Int Source I2C0_DMA_TX_INT from ADMA Sub-System */
+  ADMA_I2C1_DMA_RX_INT_IRQn    = 509,              /**< Shared Int Source I2C1_DMA_RX_INT from ADMA Sub-System */
+  ADMA_I2C1_DMA_TX_INT_IRQn    = 510,              /**< Shared Int Source I2C1_DMA_TX_INT from ADMA Sub-System */
+  ADMA_I2C2_DMA_RX_INT_IRQn    = 511,              /**< Shared Int Source I2C2_DMA_RX_INT from ADMA Sub-System */
+  ADMA_I2C2_DMA_TX_INT_IRQn    = 512,              /**< Shared Int Source I2C2_DMA_TX_INT from ADMA Sub-System */
+  ADMA_I2C3_DMA_RX_INT_IRQn    = 513,              /**< Shared Int Source I2C3_DMA_RX_INT from ADMA Sub-System */
+  ADMA_I2C3_DMA_TX_INT_IRQn    = 514,              /**< Shared Int Source I2C3_DMA_TX_INT from ADMA Sub-System */
+  ADMA_UART0_DMA_RX_INT_IRQn   = 517,              /**< Shared Int Source UART0_DMA_RX_INT from ADMA Sub-System */
+  ADMA_UART0_DMA_TX_INT_IRQn   = 518,              /**< Shared Int Source UART0_DMA_TX_INT from ADMA Sub-System */
+  ADMA_UART1_DMA_RX_INT_IRQn   = 519,              /**< Shared Int Source UART1_DMA_RX_INT from ADMA Sub-System */
+  ADMA_UART1_DMA_TX_INT_IRQn   = 520,              /**< Shared Int Source UART1_DMA_TX_INT from ADMA Sub-System */
+  ADMA_UART2_DMA_RX_INT_IRQn   = 521,              /**< Shared Int Source UART2_DMA_RX_INT from ADMA Sub-System */
+  ADMA_UART2_DMA_TX_INT_IRQn   = 522,              /**< Shared Int Source UART2_DMA_TX_INT from ADMA Sub-System */
+  ADMA_UART3_DMA_RX_INT_IRQn   = 523,              /**< Shared Int Source UART3_DMA_RX_INT from ADMA Sub-System */
+  ADMA_UART3_DMA_TX_INT_IRQn   = 524,              /**< Shared Int Source UART3_DMA_TX_INT from ADMA Sub-System */
+  SECURITY_MU1_A_INT_IRQn      = 531,              /**< Shared Int Source MU1_A_INT from Security Sub-System */
+  SECURITY_MU2_A_INT_IRQn      = 532,              /**< Shared Int Source MU2_A_INT from Security Sub-System */
+  SECURITY_MU3_A_INT_IRQn      = 533,              /**< Shared Int Source MU3_A_INT from Security Sub-System */
+  SECURITY_CAAM_INT0_IRQn      = 534,              /**< Shared Int Source CAAM_INT0 from Security Sub-System */
+  SECURITY_CAAM_INT1_IRQn      = 535,              /**< Shared Int Source CAAM_INT1 from Security Sub-System */
+  SECURITY_CAAM_INT2_IRQn      = 536,              /**< Shared Int Source CAAM_INT2 from Security Sub-System */
+  SECURITY_CAAM_INT3_IRQn      = 537,              /**< Shared Int Source CAAM_INT3 from Security Sub-System */
+  SECURITY_CAAM_RTIC_INT_IRQn  = 538,              /**< Shared Int Source CAAM_RTIC_INT from Security Sub-System */
+  ADMA_SPDIF0_RX_MOD_INT_IRQn  = 539,              /**< Shared Int Source SPDIF0_RX_MOD_INT from ADMA Sub-System */
+  ADMA_SPDIF0_RX_DMA_INT_IRQn  = 540,              /**< Shared Int Source SPDIF0_RX_DMA_INT from ADMA Sub-System */
+  ADMA_SPDIF0_TX_MOD_INT_IRQn  = 541,              /**< Shared Int Source SPDIF0_TX_MOD_INT from ADMA Sub-System */
+  ADMA_SPDIF0_TX_DMA_INT_IRQn  = 542,              /**< Shared Int Source SPDIF0_TX_DMA_INT from ADMA Sub-System */
+  VPU_VPU_INT_0_IRQn           = 547,              /**< Shared Int Source VPU_INT_0 from VPU Sub-System */
+  VPU_VPU_INT_1_IRQn           = 548,              /**< Shared Int Source VPU_INT_1 from VPU Sub-System */
+  VPU_VPU_INT_2_IRQn           = 549,              /**< Shared Int Source VPU_INT_2 from VPU Sub-System */
+  VPU_VPU_INT_3_IRQn           = 550,              /**< Shared Int Source VPU_INT_3 from VPU Sub-System */
+  VPU_VPU_INT_4_IRQn           = 551,              /**< Shared Int Source VPU_INT_4 from VPU Sub-System */
+  M4_INTMUX_SOURCE_TPM_IRQn    = 564,              /**< INTMUX Input source: TPM Interrupt */
+  M4_INTMUX_SOURCE_LPIT_IRQn   = 567,              /**< INTMUX Input source: LPIT Interrupt */
+  M4_INTMUX_SOURCE_LPUART_IRQn = 570,              /**< INTMUX Input source: LPUART Interrupt */
+  M4_INTMUX_SOURCE_LPI2C_IRQn  = 572,              /**< INTMUX Input source: LPI2C Interrupt */
+  M4_INTMUX_SOURCE_MU0_A3_IRQn = 591,              /**< INTMUX Input source: MU0_A3 Interrupt */
+  M4_INTMUX_SOURCE_MU0_A2_IRQn = 592,              /**< INTMUX Input source: MU0_A2 Interrupt */
+  M4_INTMUX_SOURCE_MU0_A1_IRQn = 593,              /**< INTMUX Input source: MU0_A1 Interrupt */
+  M4_INTMUX_SOURCE_MU0_A0_IRQn = 594               /**< INTMUX Input source: MU0_A0 Interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Configuration of the Cortex-M4 Processor and Core Peripherals
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Configuration of the Cortex-M4 Processor and Core Peripherals
+ * @{
+ */
+
+#define __CM4_REV                      0x0001    /**< Core revision r0p1 */
+#define __MPU_PRESENT                  1         /**< MPU present or not */
+#define __NVIC_PRIO_BITS               4         /**< Number of Bits used for Priority Levels */
+#define __Vendor_SysTickConfig         0         /**< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT                  1         /**< FPU present or not */
+
+#include "core_cm4.h"                  /* Core Peripheral Access Layer */
+#include "system_MIMX8QX6_cm4.h"       /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ACM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ACM_Peripheral_Access_Layer ACM Peripheral Access Layer
+ * @{
+ */
+
+/** ACM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[14680064];
+  __IO uint32_t AUD_CLK0;                          /**< ACM_AUD_CLK0 Register, offset: 0xE00000 */
+       uint8_t RESERVED_1[65532];
+  __IO uint32_t AUD_CLK1;                          /**< ACM_AUD_CLK1 Register, offset: 0xE10000 */
+       uint8_t RESERVED_2[65532];
+  __IO uint32_t MCLKOUT0;                          /**< ACM_MCLKOUT0 Register, offset: 0xE20000 */
+       uint8_t RESERVED_3[65532];
+  __IO uint32_t MCLKOUT1;                          /**< ACM_MCLKOUT1 Register, offset: 0xE30000 */
+       uint8_t RESERVED_4[196604];
+  __IO uint32_t ESAI0_CLK;                         /**< ACM_ESAI0_CLK Register, offset: 0xE60000 */
+       uint8_t RESERVED_5[131068];
+  struct {                                         /* offset: 0xE80000, array step: 0x10000 */
+    __IO uint32_t GPT_CLK;                           /**< ACM_GPT_CLK Register, array offset: 0xE80000, array step: 0x10000 */
+         uint8_t RESERVED_0[65532];
+  } GPT_CLK[6];
+  struct {                                         /* offset: 0xEE0000, array step: 0x10000 */
+    __IO uint32_t SAI_MCLK;                          /**< ACM_SAI_MCLK Register, array offset: 0xEE0000, array step: 0x10000 */
+         uint8_t RESERVED_0[65532];
+  } SAI_MCLK[8];
+       uint8_t RESERVED_6[262144];
+  __IO uint32_t SPDIF0_TX_CLK;                     /**< ACM_SPDIF0_TX_CLK Register, offset: 0xFA0000 */
+       uint8_t RESERVED_7[131068];
+  __IO uint32_t MQS_HMCLK_CLK;                     /**< ACM_MQS_HMCLK_CLK Register, offset: 0xFC0000 */
+} ACM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ACM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ACM_Register_Masks ACM Register Masks
+ * @{
+ */
+
+/*! @name AUD_CLK0 - ACM_AUD_CLK0 Register */
+/*! @{ */
+#define ACM_AUD_CLK0_SEL_MASK                    (0x1FU)
+#define ACM_AUD_CLK0_SEL_SHIFT                   (0U)
+/*! SEL - Select
+ *  0b00000..ADMA_SLSLICE2
+ *  0b00001..ADMA_SLSLICE3
+ *  0b00010..EXT_AUD_MCLK0
+ *  0b00011..EXT_AUD_MCLK1
+ *  0b00100..ESAI0_RX_CLK
+ *  0b00101..ESAI0_RX_HF_CLKK
+ *  0b00110..ESAI0_TX_CLK
+ *  0b00111..ESAI0_TX_HF_CLK
+ *  0b01000..SPDIF0_RX
+ *  0b01001..SAI0_RX_BCLK
+ *  0b01010..SAI0_TX_BCLK
+ *  0b01011..SAI1_RX_BCLK
+ *  0b01100..SAI1_TX_BCLK
+ *  0b01101..SAI2_RX_BCLK
+ *  0b01110..SAI3_RX_BCLK
+ */
+#define ACM_AUD_CLK0_SEL(x)                      (((uint32_t)(((uint32_t)(x)) << ACM_AUD_CLK0_SEL_SHIFT)) & ACM_AUD_CLK0_SEL_MASK)
+/*! @} */
+
+/*! @name AUD_CLK1 - ACM_AUD_CLK1 Register */
+/*! @{ */
+#define ACM_AUD_CLK1_SEL_MASK                    (0x1FU)
+#define ACM_AUD_CLK1_SEL_SHIFT                   (0U)
+/*! SEL - Select
+ *  0b00000..ADMA_SLSLICE2
+ *  0b00001..ADMA_SLSLICE3
+ *  0b00010..EXT_AUD_MCLK0
+ *  0b00011..EXT_AUD_MCLK1
+ *  0b00100..ESAI0_RX_CLK
+ *  0b00101..ESAI0_RX_HF_CLKK
+ *  0b00110..ESAI0_TX_CLK
+ *  0b00111..ESAI0_TX_HF_CLK
+ *  0b01000..SPDIF0_RX
+ *  0b01001..SAI0_RX_BCLK
+ *  0b01010..SAI0_TX_BCLK
+ *  0b01011..SAI1_RX_BCLK
+ *  0b01100..SAI1_TX_BCLK
+ *  0b01101..SAI2_RX_BCLK
+ *  0b01110..SAI3_RX_BCLK
+ */
+#define ACM_AUD_CLK1_SEL(x)                      (((uint32_t)(((uint32_t)(x)) << ACM_AUD_CLK1_SEL_SHIFT)) & ACM_AUD_CLK1_SEL_MASK)
+/*! @} */
+
+/*! @name MCLKOUT0 - ACM_MCLKOUT0 Register */
+/*! @{ */
+#define ACM_MCLKOUT0_SEL_MASK                    (0x7U)
+#define ACM_MCLKOUT0_SEL_SHIFT                   (0U)
+/*! SEL - Select
+ *  0b000..ADMA_SLSLICE2
+ *  0b001..ADMA_SLSLICE3
+ *  0b010..Reserved
+ *  0b011..Reserved
+ *  0b100..SPDIF0_RX
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..SAI4_RX_BCLK
+ */
+#define ACM_MCLKOUT0_SEL(x)                      (((uint32_t)(((uint32_t)(x)) << ACM_MCLKOUT0_SEL_SHIFT)) & ACM_MCLKOUT0_SEL_MASK)
+/*! @} */
+
+/*! @name MCLKOUT1 - ACM_MCLKOUT1 Register */
+/*! @{ */
+#define ACM_MCLKOUT1_SEL_MASK                    (0x7U)
+#define ACM_MCLKOUT1_SEL_SHIFT                   (0U)
+/*! SEL - Select
+ *  0b000..ADMA_SLSLICE2
+ *  0b001..ADMA_SLSLICE3
+ *  0b010..Reserved
+ *  0b011..Reserved
+ *  0b100..SPDIF0_RX
+ *  0b101..Reserved
+ *  0b110..Reserved
+ *  0b111..SAI4_RX_BCLK
+ */
+#define ACM_MCLKOUT1_SEL(x)                      (((uint32_t)(((uint32_t)(x)) << ACM_MCLKOUT1_SEL_SHIFT)) & ACM_MCLKOUT1_SEL_MASK)
+/*! @} */
+
+/*! @name ESAI0_CLK - ACM_ESAI0_CLK Register */
+/*! @{ */
+#define ACM_ESAI0_CLK_SEL_MASK                   (0x3U)
+#define ACM_ESAI0_CLK_SEL_SHIFT                  (0U)
+/*! SEL - Select
+ *  0b00..AUD_PLL_DIV_CLK0
+ *  0b01..AUD_PLL_DIV_CLK1
+ *  0b10..AUD_CLK0
+ *  0b11..AUD_CLK1
+ */
+#define ACM_ESAI0_CLK_SEL(x)                     (((uint32_t)(((uint32_t)(x)) << ACM_ESAI0_CLK_SEL_SHIFT)) & ACM_ESAI0_CLK_SEL_MASK)
+/*! @} */
+
+/*! @name GPT_CLK - ACM_GPT_CLK Register */
+/*! @{ */
+#define ACM_GPT_CLK_SEL_MASK                     (0x7U)
+#define ACM_GPT_CLK_SEL_SHIFT                    (0U)
+/*! SEL - Select
+ *  0b000..AUD_PLL_DIV_CLK0
+ *  0b001..AUD_PLL_DIV_CLK1
+ *  0b010..AUD_CLK0
+ *  0b011..AUD_CLK1
+ *  0b100..24M_REF_CLK
+ */
+#define ACM_GPT_CLK_SEL(x)                       (((uint32_t)(((uint32_t)(x)) << ACM_GPT_CLK_SEL_SHIFT)) & ACM_GPT_CLK_SEL_MASK)
+/*! @} */
+
+/* The count of ACM_GPT_CLK */
+#define ACM_GPT_CLK_COUNT                        (6U)
+
+/*! @name SAI_MCLK - ACM_SAI_MCLK Register */
+/*! @{ */
+#define ACM_SAI_MCLK_SEL_MASK                    (0x3U)
+#define ACM_SAI_MCLK_SEL_SHIFT                   (0U)
+/*! SEL - Select
+ *  0b00..AUD_PLL_DIV_CLK0
+ *  0b01..AUD_PLL_DIV_CLK1
+ *  0b10..AUD_CLK0
+ *  0b11..AUD_CLK1
+ */
+#define ACM_SAI_MCLK_SEL(x)                      (((uint32_t)(((uint32_t)(x)) << ACM_SAI_MCLK_SEL_SHIFT)) & ACM_SAI_MCLK_SEL_MASK)
+/*! @} */
+
+/* The count of ACM_SAI_MCLK */
+#define ACM_SAI_MCLK_COUNT                       (8U)
+
+/*! @name SPDIF0_TX_CLK - ACM_SPDIF0_TX_CLK Register */
+/*! @{ */
+#define ACM_SPDIF0_TX_CLK_SEL_MASK               (0x3U)
+#define ACM_SPDIF0_TX_CLK_SEL_SHIFT              (0U)
+/*! SEL - Select
+ *  0b00..AUD_PLL_DIV_CLK0
+ *  0b01..AUD_PLL_DIV_CLK1
+ *  0b10..AUD_CLK0
+ *  0b11..AUD_CLK1
+ */
+#define ACM_SPDIF0_TX_CLK_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << ACM_SPDIF0_TX_CLK_SEL_SHIFT)) & ACM_SPDIF0_TX_CLK_SEL_MASK)
+/*! @} */
+
+/*! @name MQS_HMCLK_CLK - ACM_MQS_HMCLK_CLK Register */
+/*! @{ */
+#define ACM_MQS_HMCLK_CLK_SEL_MASK               (0x3U)
+#define ACM_MQS_HMCLK_CLK_SEL_SHIFT              (0U)
+/*! SEL - Select
+ *  0b00..AUD_PLL_DIV_CLK0
+ *  0b01..AUD_PLL_DIV_CLK1
+ *  0b10..AUD_CLK0
+ *  0b11..AUD_CLK1
+ */
+#define ACM_MQS_HMCLK_CLK_SEL(x)                 (((uint32_t)(((uint32_t)(x)) << ACM_MQS_HMCLK_CLK_SEL_SHIFT)) & ACM_MQS_HMCLK_CLK_SEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ACM_Register_Masks */
+
+
+/* ACM - Peripheral instance base addresses */
+/** Peripheral ADMA__ACM base address */
+#define ADMA__ACM_BASE                           (0x59000000u)
+/** Peripheral ADMA__ACM base pointer */
+#define ADMA__ACM                                ((ACM_Type *)ADMA__ACM_BASE)
+/** Array initializer of ACM peripheral base addresses */
+#define ACM_BASE_ADDRS                           { ADMA__ACM_BASE }
+/** Array initializer of ACM peripheral base pointers */
+#define ACM_BASE_PTRS                            { ADMA__ACM }
+
+/*!
+ * @}
+ */ /* end of group ACM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t VERID;                             /**< Version ID Register, offset: 0x0 */
+  __I  uint32_t PARAM;                             /**< Parameter Register, offset: 0x4 */
+       uint8_t RESERVED_0[8];
+  __IO uint32_t CTRL;                              /**< ADC Control Register, offset: 0x10 */
+  __IO uint32_t STAT;                              /**< ADC Status Register, offset: 0x14 */
+  __IO uint32_t IE;                                /**< Interrupt Enable Register, offset: 0x18 */
+  __IO uint32_t DE;                                /**< DMA Enable Register, offset: 0x1C */
+  __IO uint32_t CFG;                               /**< ADC Configuration Register, offset: 0x20 */
+  __IO uint32_t PAUSE;                             /**< ADC Pause Register, offset: 0x24 */
+       uint8_t RESERVED_1[8];
+  __IO uint32_t FCTRL;                             /**< ADC FIFO Control Register, offset: 0x30 */
+  __O  uint32_t SWTRIG;                            /**< Software Trigger Register, offset: 0x34 */
+       uint8_t RESERVED_2[136];
+  __IO uint32_t TCTRL[8];                          /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */
+       uint8_t RESERVED_3[32];
+  struct {                                         /* offset: 0x100, array step: 0x8 */
+    __IO uint32_t CMDL;                              /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
+    __IO uint32_t CMDH;                              /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
+  } CMD[15];
+       uint8_t RESERVED_4[136];
+  __IO uint32_t CV[4];                             /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
+       uint8_t RESERVED_5[240];
+  __I  uint32_t RESFIFO;                           /**< ADC Data Result FIFO Register, offset: 0x300 */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name VERID - Version ID Register */
+/*! @{ */
+#define ADC_VERID_RES_MASK                       (0x1U)
+#define ADC_VERID_RES_SHIFT                      (0U)
+/*! RES - Resolution
+ *  0b0..Up to 13-bit differential/12-bit single ended resolution supported.
+ *  0b1..Up to 16-bit differential/15-bit single ended resolution supported.
+ */
+#define ADC_VERID_RES(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
+#define ADC_VERID_DIFFEN_MASK                    (0x2U)
+#define ADC_VERID_DIFFEN_SHIFT                   (1U)
+/*! DIFFEN - Differential Supported
+ *  0b0..Differential operation not supported.
+ *  0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.
+ */
+#define ADC_VERID_DIFFEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
+#define ADC_VERID_MVI_MASK                       (0x8U)
+#define ADC_VERID_MVI_SHIFT                      (3U)
+/*! MVI - Multi Vref Implemented
+ *  0b0..Single voltage reference high (VREFH) input supported.
+ *  0b1..Multiple voltage reference high (VREFH) inputs supported.
+ */
+#define ADC_VERID_MVI(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
+#define ADC_VERID_CSW_MASK                       (0x70U)
+#define ADC_VERID_CSW_SHIFT                      (4U)
+/*! CSW - Channel Scale Width
+ *  0b000..Channel scaling not supported.
+ *  0b001..Channel scaling supported. 1-bit CSCALE control field.
+ *  0b110..Channel scaling supported. 6-bit CSCALE control field.
+ */
+#define ADC_VERID_CSW(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
+#define ADC_VERID_VR1RNGI_MASK                   (0x100U)
+#define ADC_VERID_VR1RNGI_SHIFT                  (8U)
+/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
+ *  0b0..Range control not required. CFG[VREF1RNG] is not implemented.
+ *  0b1..Range control required. CFG[VREF1RNG] is implemented.
+ */
+#define ADC_VERID_VR1RNGI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
+#define ADC_VERID_IADCKI_MASK                    (0x200U)
+#define ADC_VERID_IADCKI_SHIFT                   (9U)
+/*! IADCKI - Internal ADC Clock implemented
+ *  0b0..Internal clock source not implemented.
+ *  0b1..Internal clock source (and CFG[ADCKEN]) implemented.
+ */
+#define ADC_VERID_IADCKI(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
+#define ADC_VERID_CALOFSI_MASK                   (0x400U)
+#define ADC_VERID_CALOFSI_SHIFT                  (10U)
+/*! CALOFSI - Calibration Offset Function Implemented
+ *  0b0..Offset calibration and offset trimming not implemented.
+ *  0b1..Offset calibration and offset trimming implemented.
+ */
+#define ADC_VERID_CALOFSI(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
+#define ADC_VERID_MINOR_MASK                     (0xFF0000U)
+#define ADC_VERID_MINOR_SHIFT                    (16U)
+/*! MINOR - Minor Version Number
+ */
+#define ADC_VERID_MINOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
+#define ADC_VERID_MAJOR_MASK                     (0xFF000000U)
+#define ADC_VERID_MAJOR_SHIFT                    (24U)
+/*! MAJOR - Major Version Number
+ */
+#define ADC_VERID_MAJOR(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
+/*! @} */
+
+/*! @name PARAM - Parameter Register */
+/*! @{ */
+#define ADC_PARAM_TRIG_NUM_MASK                  (0xFFU)
+#define ADC_PARAM_TRIG_NUM_SHIFT                 (0U)
+/*! TRIG_NUM - Trigger Number
+ */
+#define ADC_PARAM_TRIG_NUM(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
+#define ADC_PARAM_FIFOSIZE_MASK                  (0xFF00U)
+#define ADC_PARAM_FIFOSIZE_SHIFT                 (8U)
+/*! FIFOSIZE - Result FIFO Depth
+ *  0b00000001..Result FIFO depth = 1 dataword.
+ *  0b00000100..Result FIFO depth = 4 datawords.
+ *  0b00001000..Result FIFO depth = 8 datawords.
+ *  0b00010000..Result FIFO depth = 16 datawords.
+ *  0b00100000..Result FIFO depth = 32 datawords.
+ *  0b01000000..Result FIFO depth = 64 datawords.
+ */
+#define ADC_PARAM_FIFOSIZE(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
+#define ADC_PARAM_CV_NUM_MASK                    (0xFF0000U)
+#define ADC_PARAM_CV_NUM_SHIFT                   (16U)
+/*! CV_NUM - Compare Value Number
+ */
+#define ADC_PARAM_CV_NUM(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
+#define ADC_PARAM_CMD_NUM_MASK                   (0xFF000000U)
+#define ADC_PARAM_CMD_NUM_SHIFT                  (24U)
+/*! CMD_NUM - Command Buffer Number
+ */
+#define ADC_PARAM_CMD_NUM(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
+/*! @} */
+
+/*! @name CTRL - ADC Control Register */
+/*! @{ */
+#define ADC_CTRL_ADCEN_MASK                      (0x1U)
+#define ADC_CTRL_ADCEN_SHIFT                     (0U)
+/*! ADCEN - ADC Enable
+ *  0b0..ADC is disabled.
+ *  0b1..ADC is enabled.
+ */
+#define ADC_CTRL_ADCEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
+#define ADC_CTRL_RST_MASK                        (0x2U)
+#define ADC_CTRL_RST_SHIFT                       (1U)
+/*! RST - Software Reset
+ *  0b0..ADC logic is not reset.
+ *  0b1..ADC logic is reset.
+ */
+#define ADC_CTRL_RST(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
+#define ADC_CTRL_DOZEN_MASK                      (0x4U)
+#define ADC_CTRL_DOZEN_SHIFT                     (2U)
+/*! DOZEN - Doze Enable
+ *  0b0..ADC is enabled in Doze mode.
+ *  0b1..ADC is disabled in Doze mode.
+ */
+#define ADC_CTRL_DOZEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
+#define ADC_CTRL_RSTFIFO_MASK                    (0x100U)
+#define ADC_CTRL_RSTFIFO_SHIFT                   (8U)
+/*! RSTFIFO - Reset FIFO
+ *  0b0..No effect.
+ *  0b1..FIFO is reset.
+ */
+#define ADC_CTRL_RSTFIFO(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)
+/*! @} */
+
+/*! @name STAT - ADC Status Register */
+/*! @{ */
+#define ADC_STAT_RDY_MASK                        (0x1U)
+#define ADC_STAT_RDY_SHIFT                       (0U)
+/*! RDY - Result FIFO Ready Flag
+ *  0b0..Result FIFO data level not above watermark level.
+ *  0b1..Result FIFO holding data above watermark level.
+ */
+#define ADC_STAT_RDY(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)
+#define ADC_STAT_FOF_MASK                        (0x2U)
+#define ADC_STAT_FOF_SHIFT                       (1U)
+/*! FOF - Result FIFO Overflow Flag
+ *  0b0..No result FIFO overflow has occurred since the last time the flag was cleared.
+ *  0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared.
+ */
+#define ADC_STAT_FOF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)
+#define ADC_STAT_ADC_ACTIVE_MASK                 (0x100U)
+#define ADC_STAT_ADC_ACTIVE_SHIFT                (8U)
+/*! ADC_ACTIVE - ADC Active
+ *  0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
+ *  0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
+ */
+#define ADC_STAT_ADC_ACTIVE(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
+#define ADC_STAT_TRGACT_MASK                     (0x70000U)
+#define ADC_STAT_TRGACT_SHIFT                    (16U)
+/*! TRGACT - Trigger Active
+ *  0b000..Command (sequence) associated with Trigger 0 currently being executed.
+ *  0b001..Command (sequence) associated with Trigger 1 currently being executed.
+ *  0b010..Command (sequence) associated with Trigger 2 currently being executed.
+ *  0b011-0b111..Command (sequence) from the associated Trigger number is currently being executed.
+ */
+#define ADC_STAT_TRGACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
+#define ADC_STAT_CMDACT_MASK                     (0xF000000U)
+#define ADC_STAT_CMDACT_SHIFT                    (24U)
+/*! CMDACT - Command Active
+ *  0b0000..No command is currently in progress.
+ *  0b0001..Command 1 currently being executed.
+ *  0b0010..Command 2 currently being executed.
+ *  0b0011-0b1111..Associated command number is currently being executed.
+ */
+#define ADC_STAT_CMDACT(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
+/*! @} */
+
+/*! @name IE - Interrupt Enable Register */
+/*! @{ */
+#define ADC_IE_FWMIE_MASK                        (0x1U)
+#define ADC_IE_FWMIE_SHIFT                       (0U)
+/*! FWMIE - FIFO Watermark Interrupt Enable
+ *  0b0..FIFO watermark interrupts are not enabled.
+ *  0b1..FIFO watermark interrupts are enabled.
+ */
+#define ADC_IE_FWMIE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)
+#define ADC_IE_FOFIE_MASK                        (0x2U)
+#define ADC_IE_FOFIE_SHIFT                       (1U)
+/*! FOFIE - Result FIFO Overflow Interrupt Enable
+ *  0b0..FIFO overflow interrupts are not enabled.
+ *  0b1..FIFO overflow interrupts are enabled.
+ */
+#define ADC_IE_FOFIE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)
+/*! @} */
+
+/*! @name DE - DMA Enable Register */
+/*! @{ */
+#define ADC_DE_FWMDE_MASK                        (0x1U)
+#define ADC_DE_FWMDE_SHIFT                       (0U)
+/*! FWMDE - FIFO Watermark DMA Enable
+ *  0b0..DMA request disabled.
+ *  0b1..DMA request enabled.
+ */
+#define ADC_DE_FWMDE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)
+/*! @} */
+
+/*! @name CFG - ADC Configuration Register */
+/*! @{ */
+#define ADC_CFG_TPRICTRL_MASK                    (0x1U)
+#define ADC_CFG_TPRICTRL_SHIFT                   (0U)
+/*! TPRICTRL - ADC trigger priority control
+ *  0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and
+ *       the new command specified by the trigger is started.
+ *  0b1..If a higher priority trigger is received during command processing, the current conversion is completed
+ *       (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority
+ *       trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true
+ *       conversion.
+ */
+#define ADC_CFG_TPRICTRL(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
+#define ADC_CFG_PWRSEL_MASK                      (0x30U)
+#define ADC_CFG_PWRSEL_SHIFT                     (4U)
+/*! PWRSEL - Power Configuration Select
+ *  0b00..Level 1 (Lowest power setting)
+ *  0b01..Level 2
+ *  0b10..Level 3
+ *  0b11..Level 4 (Highest power setting)
+ */
+#define ADC_CFG_PWRSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
+#define ADC_CFG_REFSEL_MASK                      (0xC0U)
+#define ADC_CFG_REFSEL_SHIFT                     (6U)
+/*! REFSEL - Voltage Reference Selection
+ *  0b00..(Default) Option 1 setting.
+ *  0b01..Option 2 setting.
+ *  0b10..Option 3 setting.
+ *  0b11..Reserved
+ */
+#define ADC_CFG_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
+#define ADC_CFG_PUDLY_MASK                       (0xFF0000U)
+#define ADC_CFG_PUDLY_SHIFT                      (16U)
+/*! PUDLY - Power Up Delay
+ */
+#define ADC_CFG_PUDLY(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
+#define ADC_CFG_PWREN_MASK                       (0x10000000U)
+#define ADC_CFG_PWREN_SHIFT                      (28U)
+/*! PWREN - ADC Analog Pre-Enable
+ *  0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
+ *  0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
+ *       of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any
+ *       detected trigger does not begin ADC operation until the power up delay time has passed.
+ */
+#define ADC_CFG_PWREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
+/*! @} */
+
+/*! @name PAUSE - ADC Pause Register */
+/*! @{ */
+#define ADC_PAUSE_PAUSEDLY_MASK                  (0x1FFU)
+#define ADC_PAUSE_PAUSEDLY_SHIFT                 (0U)
+/*! PAUSEDLY - Pause Delay
+ */
+#define ADC_PAUSE_PAUSEDLY(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
+#define ADC_PAUSE_PAUSEEN_MASK                   (0x80000000U)
+#define ADC_PAUSE_PAUSEEN_SHIFT                  (31U)
+/*! PAUSEEN - PAUSE Option Enable
+ *  0b0..Pause operation disabled
+ *  0b1..Pause operation enabled
+ */
+#define ADC_PAUSE_PAUSEEN(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
+/*! @} */
+
+/*! @name FCTRL - ADC FIFO Control Register */
+/*! @{ */
+#define ADC_FCTRL_FCOUNT_MASK                    (0x1FU)
+#define ADC_FCTRL_FCOUNT_SHIFT                   (0U)
+/*! FCOUNT - Result FIFO counter
+ */
+#define ADC_FCTRL_FCOUNT(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
+#define ADC_FCTRL_FWMARK_MASK                    (0xF0000U)
+#define ADC_FCTRL_FWMARK_SHIFT                   (16U)
+/*! FWMARK - Watermark level selection
+ */
+#define ADC_FCTRL_FWMARK(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
+/*! @} */
+
+/*! @name SWTRIG - Software Trigger Register */
+/*! @{ */
+#define ADC_SWTRIG_SWT0_MASK                     (0x1U)
+#define ADC_SWTRIG_SWT0_SHIFT                    (0U)
+/*! SWT0 - Software trigger 0 event
+ *  0b0..No trigger 0 event generated.
+ *  0b1..Trigger 0 event generated.
+ */
+#define ADC_SWTRIG_SWT0(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
+#define ADC_SWTRIG_SWT1_MASK                     (0x2U)
+#define ADC_SWTRIG_SWT1_SHIFT                    (1U)
+/*! SWT1 - Software trigger 1 event
+ *  0b0..No trigger 1 event generated.
+ *  0b1..Trigger 1 event generated.
+ */
+#define ADC_SWTRIG_SWT1(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
+#define ADC_SWTRIG_SWT2_MASK                     (0x4U)
+#define ADC_SWTRIG_SWT2_SHIFT                    (2U)
+/*! SWT2 - Software trigger 2 event
+ *  0b0..No trigger 2 event generated.
+ *  0b1..Trigger 2 event generated.
+ */
+#define ADC_SWTRIG_SWT2(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
+#define ADC_SWTRIG_SWT3_MASK                     (0x8U)
+#define ADC_SWTRIG_SWT3_SHIFT                    (3U)
+/*! SWT3 - Software trigger 3 event
+ *  0b0..No trigger 3 event generated.
+ *  0b1..Trigger 3 event generated.
+ */
+#define ADC_SWTRIG_SWT3(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
+#define ADC_SWTRIG_SWT4_MASK                     (0x10U)
+#define ADC_SWTRIG_SWT4_SHIFT                    (4U)
+/*! SWT4 - Software trigger 4 event
+ *  0b0..No trigger 4 event generated.
+ *  0b1..Trigger 4 event generated.
+ */
+#define ADC_SWTRIG_SWT4(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
+#define ADC_SWTRIG_SWT5_MASK                     (0x20U)
+#define ADC_SWTRIG_SWT5_SHIFT                    (5U)
+/*! SWT5 - Software trigger 5 event
+ *  0b0..No trigger 5 event generated.
+ *  0b1..Trigger 5 event generated.
+ */
+#define ADC_SWTRIG_SWT5(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
+#define ADC_SWTRIG_SWT6_MASK                     (0x40U)
+#define ADC_SWTRIG_SWT6_SHIFT                    (6U)
+/*! SWT6 - Software trigger 6 event
+ *  0b0..No trigger 6 event generated.
+ *  0b1..Trigger 6 event generated.
+ */
+#define ADC_SWTRIG_SWT6(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
+#define ADC_SWTRIG_SWT7_MASK                     (0x80U)
+#define ADC_SWTRIG_SWT7_SHIFT                    (7U)
+/*! SWT7 - Software trigger 7 event
+ *  0b0..No trigger 7 event generated.
+ *  0b1..Trigger 7 event generated.
+ */
+#define ADC_SWTRIG_SWT7(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
+/*! @} */
+
+/*! @name TCTRL - Trigger Control Register */
+/*! @{ */
+#define ADC_TCTRL_HTEN_MASK                      (0x1U)
+#define ADC_TCTRL_HTEN_SHIFT                     (0U)
+/*! HTEN - Trigger enable
+ *  0b0..Hardware trigger source disabled
+ *  0b1..Hardware trigger source enabled
+ */
+#define ADC_TCTRL_HTEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
+#define ADC_TCTRL_TPRI_MASK                      (0x700U)
+#define ADC_TCTRL_TPRI_SHIFT                     (8U)
+/*! TPRI - Trigger priority setting
+ *  0b000..Set to highest priority, Level 1
+ *  0b001-0b110..Set to corresponding priority level
+ *  0b111..Set to lowest priority, Level 8
+ */
+#define ADC_TCTRL_TPRI(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
+#define ADC_TCTRL_TDLY_MASK                      (0xF0000U)
+#define ADC_TCTRL_TDLY_SHIFT                     (16U)
+/*! TDLY - Trigger delay select
+ */
+#define ADC_TCTRL_TDLY(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
+#define ADC_TCTRL_TCMD_MASK                      (0xF000000U)
+#define ADC_TCTRL_TCMD_SHIFT                     (24U)
+/*! TCMD - Trigger command select
+ *  0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
+ *  0b0001..CMD1 is executed
+ *  0b0010-0b1110..Corresponding CMD is executed
+ *  0b1111..CMD15 is executed
+ */
+#define ADC_TCTRL_TCMD(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
+/*! @} */
+
+/* The count of ADC_TCTRL */
+#define ADC_TCTRL_COUNT                          (8U)
+
+/*! @name CMDL - ADC Command Low Buffer Register */
+/*! @{ */
+#define ADC_CMDL_ADCH_MASK                       (0x1FU)
+#define ADC_CMDL_ADCH_SHIFT                      (0U)
+/*! ADCH - Input channel select
+ *  0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
+ *  0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
+ *  0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
+ *  0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
+ *  0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
+ *  0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
+ *  0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
+ */
+#define ADC_CMDL_ADCH(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
+#define ADC_CMDL_ABSEL_MASK                      (0x20U)
+#define ADC_CMDL_ABSEL_SHIFT                     (5U)
+/*! ABSEL - A-side vs. B-side Select
+ *  0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB).
+ *  0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA).
+ */
+#define ADC_CMDL_ABSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
+#define ADC_CMDL_DIFF_MASK                       (0x40U)
+#define ADC_CMDL_DIFF_SHIFT                      (6U)
+/*! DIFF - Differential Mode Enable
+ *  0b0..Single-ended mode.
+ *  0b1..Differential mode.
+ */
+#define ADC_CMDL_DIFF(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)
+#define ADC_CMDL_CSCALE_MASK                     (0x2000U)
+#define ADC_CMDL_CSCALE_SHIFT                    (13U)
+/*! CSCALE - Channel Scale
+ *  0b0..Scale selected analog channel (Factor of 30/64)
+ *  0b1..(Default) Full scale (Factor of 1)
+ */
+#define ADC_CMDL_CSCALE(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)
+/*! @} */
+
+/* The count of ADC_CMDL */
+#define ADC_CMDL_COUNT                           (15U)
+
+/*! @name CMDH - ADC Command High Buffer Register */
+/*! @{ */
+#define ADC_CMDH_CMPEN_MASK                      (0x3U)
+#define ADC_CMDH_CMPEN_SHIFT                     (0U)
+/*! CMPEN - Compare Function Enable
+ *  0b00..Compare disabled.
+ *  0b01..Reserved
+ *  0b10..Compare enabled. Store on true.
+ *  0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
+ */
+#define ADC_CMDH_CMPEN(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
+#define ADC_CMDH_LWI_MASK                        (0x80U)
+#define ADC_CMDH_LWI_SHIFT                       (7U)
+/*! LWI - Loop with Increment
+ *  0b0..Auto channel increment disabled
+ *  0b1..Auto channel increment enabled
+ */
+#define ADC_CMDH_LWI(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
+#define ADC_CMDH_STS_MASK                        (0x700U)
+#define ADC_CMDH_STS_SHIFT                       (8U)
+/*! STS - Sample Time Select
+ *  0b000..Minimum sample time of 3 ADCK cycles.
+ *  0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
+ *  0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
+ *  0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
+ *  0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
+ *  0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
+ *  0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
+ *  0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
+ */
+#define ADC_CMDH_STS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
+#define ADC_CMDH_AVGS_MASK                       (0x7000U)
+#define ADC_CMDH_AVGS_SHIFT                      (12U)
+/*! AVGS - Hardware Average Select
+ *  0b000..Single conversion.
+ *  0b001..2 conversions averaged.
+ *  0b010..4 conversions averaged.
+ *  0b011..8 conversions averaged.
+ *  0b100..16 conversions averaged.
+ *  0b101..32 conversions averaged.
+ *  0b110..64 conversions averaged.
+ *  0b111..128 conversions averaged.
+ */
+#define ADC_CMDH_AVGS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
+#define ADC_CMDH_LOOP_MASK                       (0xF0000U)
+#define ADC_CMDH_LOOP_SHIFT                      (16U)
+/*! LOOP - Loop Count Select
+ *  0b0000..Looping not enabled. Command executes 1 time.
+ *  0b0001..Loop 1 time. Command executes 2 times.
+ *  0b0010..Loop 2 times. Command executes 3 times.
+ *  0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
+ *  0b1111..Loop 15 times. Command executes 16 times.
+ */
+#define ADC_CMDH_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
+#define ADC_CMDH_NEXT_MASK                       (0xF000000U)
+#define ADC_CMDH_NEXT_SHIFT                      (24U)
+/*! NEXT - Next Command Select
+ *  0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
+ *          trigger pending, begin command associated with lower priority trigger.
+ *  0b0001..Select CMD1 command buffer register as next command.
+ *  0b0010-0b1110..Select corresponding CMD command buffer register as next command
+ *  0b1111..Select CMD15 command buffer register as next command.
+ */
+#define ADC_CMDH_NEXT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
+/*! @} */
+
+/* The count of ADC_CMDH */
+#define ADC_CMDH_COUNT                           (15U)
+
+/*! @name CV - Compare Value Register */
+/*! @{ */
+#define ADC_CV_CVL_MASK                          (0xFFFFU)
+#define ADC_CV_CVL_SHIFT                         (0U)
+/*! CVL - Compare Value Low.
+ */
+#define ADC_CV_CVL(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
+#define ADC_CV_CVH_MASK                          (0xFFFF0000U)
+#define ADC_CV_CVH_SHIFT                         (16U)
+/*! CVH - Compare Value High.
+ */
+#define ADC_CV_CVH(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
+/*! @} */
+
+/* The count of ADC_CV */
+#define ADC_CV_COUNT                             (4U)
+
+/*! @name RESFIFO - ADC Data Result FIFO Register */
+/*! @{ */
+#define ADC_RESFIFO_D_MASK                       (0xFFFFU)
+#define ADC_RESFIFO_D_SHIFT                      (0U)
+/*! D - Data result
+ */
+#define ADC_RESFIFO_D(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
+#define ADC_RESFIFO_TSRC_MASK                    (0x70000U)
+#define ADC_RESFIFO_TSRC_SHIFT                   (16U)
+/*! TSRC - Trigger Source
+ *  0b000..Trigger source 0 initiated this conversion.
+ *  0b001..Trigger source 1 initiated this conversion.
+ *  0b010-0b110..Corresponding trigger source initiated this conversion.
+ *  0b111..Trigger source 7 initiated this conversion.
+ */
+#define ADC_RESFIFO_TSRC(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
+#define ADC_RESFIFO_LOOPCNT_MASK                 (0xF00000U)
+#define ADC_RESFIFO_LOOPCNT_SHIFT                (20U)
+/*! LOOPCNT - Loop count value
+ *  0b0000..Result is from initial conversion in command.
+ *  0b0001..Result is from second conversion in command.
+ *  0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
+ *  0b1111..Result is from 16th conversion in command.
+ */
+#define ADC_RESFIFO_LOOPCNT(x)                   (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
+#define ADC_RESFIFO_CMDSRC_MASK                  (0xF000000U)
+#define ADC_RESFIFO_CMDSRC_SHIFT                 (24U)
+/*! CMDSRC - Command Buffer Source
+ *  0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
+ *          prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
+ *  0b0001..CMD1 buffer used as control settings for this conversion.
+ *  0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
+ *  0b1111..CMD15 buffer used as control settings for this conversion.
+ */
+#define ADC_RESFIFO_CMDSRC(x)                    (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
+#define ADC_RESFIFO_VALID_MASK                   (0x80000000U)
+#define ADC_RESFIFO_VALID_SHIFT                  (31U)
+/*! VALID - FIFO entry is valid
+ *  0b0..FIFO is empty. Discard any read from RESFIFO.
+ *  0b1..FIFO record read from RESFIFO is valid.
+ */
+#define ADC_RESFIFO_VALID(x)                     (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADMA__ADC0 base address */
+#define ADMA__ADC0_BASE                          (0x5A880000u)
+/** Peripheral ADMA__ADC0 base pointer */
+#define ADMA__ADC0                               ((ADC_Type *)ADMA__ADC0_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADMA__ADC0_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADMA__ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS                                 { ADMA_ADC0_INT_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- APBH Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer
+ * @{
+ */
+
+/** APBH - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0 */
+    __IO uint32_t RW;                                /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */
+    __IO uint32_t SET;                               /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */
+    __IO uint32_t CLR;                               /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */
+    __IO uint32_t TOG;                               /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */
+  } CTRL0;
+  struct {                                         /* offset: 0x10 */
+    __IO uint32_t RW;                                /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */
+    __IO uint32_t SET;                               /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */
+    __IO uint32_t CLR;                               /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */
+    __IO uint32_t TOG;                               /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */
+  } CTRL1;
+  struct {                                         /* offset: 0x20 */
+    __IO uint32_t RW;                                /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */
+    __IO uint32_t SET;                               /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */
+    __IO uint32_t CLR;                               /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */
+    __IO uint32_t TOG;                               /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */
+  } CTRL2;
+  struct {                                         /* offset: 0x30 */
+    __IO uint32_t RW;                                /**< AHB to APBH Bridge Channel Register, offset: 0x30 */
+    __IO uint32_t SET;                               /**< AHB to APBH Bridge Channel Register, offset: 0x34 */
+    __IO uint32_t CLR;                               /**< AHB to APBH Bridge Channel Register, offset: 0x38 */
+    __IO uint32_t TOG;                               /**< AHB to APBH Bridge Channel Register, offset: 0x3C */
+  } CHANNEL_CTRL;
+       uint32_t DEVSEL;                            /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t DMA_BURST_SIZE;                    /**< AHB to APBH DMA burst size, offset: 0x50 */
+       uint8_t RESERVED_1[12];
+  __IO uint32_t DEBUGr;                            /**< AHB to APBH DMA Debug Register, offset: 0x60 */
+       uint8_t RESERVED_2[156];
+  struct {                                         /* offset: 0x100, array step: 0x70 */
+    __I  uint32_t CH_CURCMDAR;                       /**< APBH DMA Channel n Current Command Address Register, array offset: 0x100, array step: 0x70 */
+         uint8_t RESERVED_0[12];
+    __IO uint32_t CH_NXTCMDAR;                       /**< APBH DMA Channel n Next Command Address Register, array offset: 0x110, array step: 0x70 */
+         uint8_t RESERVED_1[12];
+    __I  uint32_t CH_CMD;                            /**< APBH DMA Channel n Command Register, array offset: 0x120, array step: 0x70 */
+         uint8_t RESERVED_2[12];
+    __I  uint32_t CH_BAR;                            /**< APBH DMA Channel n Buffer Address Register, array offset: 0x130, array step: 0x70 */
+         uint8_t RESERVED_3[12];
+    __IO uint32_t CH_SEMA;                           /**< APBH DMA Channel n Semaphore Register, array offset: 0x140, array step: 0x70 */
+         uint8_t RESERVED_4[12];
+    __I  uint32_t CH_DEBUG1;                         /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x150, array step: 0x70 */
+         uint8_t RESERVED_5[12];
+    __I  uint32_t CH_DEBUG2;                         /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x160, array step: 0x70 */
+         uint8_t RESERVED_6[12];
+  } CH_CFGn[16];
+  __I  uint32_t VERSION;                           /**< APBH Bridge Version Register, offset: 0x800 */
+} APBH_Type;
+
+/* ----------------------------------------------------------------------------
+   -- APBH Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup APBH_Register_Masks APBH Register Masks
+ * @{
+ */
+
+/*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */
+/*! @{ */
+#define APBH_CTRL0_CLKGATE_CHANNEL_MASK          (0xFFFFU)
+#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT         (0U)
+/*! CLKGATE_CHANNEL - CLKGATE_CHANNEL
+ *  0b0000000000000001..
+ *  0b0000000000000010..
+ *  0b0000000000000100..
+ *  0b0000000000001000..
+ *  0b0000000000010000..
+ *  0b0000000000100000..
+ *  0b0000000001000000..
+ *  0b0000000010000000..
+ *  0b0000000100000000..
+ */
+#define APBH_CTRL0_CLKGATE_CHANNEL(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK)
+#define APBH_CTRL0_APB_BURST_EN_MASK             (0x10000000U)
+#define APBH_CTRL0_APB_BURST_EN_SHIFT            (28U)
+/*! APB_BURST_EN - APB_BURST_EN
+ */
+#define APBH_CTRL0_APB_BURST_EN(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK)
+#define APBH_CTRL0_AHB_BURST8_EN_MASK            (0x20000000U)
+#define APBH_CTRL0_AHB_BURST8_EN_SHIFT           (29U)
+/*! AHB_BURST8_EN - AHB_BURST8_EN
+ */
+#define APBH_CTRL0_AHB_BURST8_EN(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK)
+#define APBH_CTRL0_CLKGATE_MASK                  (0x40000000U)
+#define APBH_CTRL0_CLKGATE_SHIFT                 (30U)
+/*! CLKGATE - CLKGATE
+ */
+#define APBH_CTRL0_CLKGATE(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK)
+#define APBH_CTRL0_SFTRST_MASK                   (0x80000000U)
+#define APBH_CTRL0_SFTRST_SHIFT                  (31U)
+/*! SFTRST - SFTRST
+ */
+#define APBH_CTRL0_SFTRST(x)                     (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK)
+/*! @} */
+
+/*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */
+/*! @{ */
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK         (0x1U)
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT        (0U)
+/*! CH0_CMDCMPLT_IRQ - CH0_CMDCMPLT_IRQ
+ */
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK         (0x2U)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT        (1U)
+/*! CH1_CMDCMPLT_IRQ - CH1_CMDCMPLT_IRQ
+ */
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK         (0x4U)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT        (2U)
+/*! CH2_CMDCMPLT_IRQ - CH2_CMDCMPLT_IRQ
+ */
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK         (0x8U)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT        (3U)
+/*! CH3_CMDCMPLT_IRQ - CH3_CMDCMPLT_IRQ
+ */
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK         (0x10U)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT        (4U)
+/*! CH4_CMDCMPLT_IRQ - CH4_CMDCMPLT_IRQ
+ */
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK         (0x20U)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT        (5U)
+/*! CH5_CMDCMPLT_IRQ - CH5_CMDCMPLT_IRQ
+ */
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK         (0x40U)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT        (6U)
+/*! CH6_CMDCMPLT_IRQ - CH6_CMDCMPLT_IRQ
+ */
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK         (0x80U)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT        (7U)
+/*! CH7_CMDCMPLT_IRQ - CH7_CMDCMPLT_IRQ
+ */
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK         (0x100U)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT        (8U)
+/*! CH8_CMDCMPLT_IRQ - CH8_CMDCMPLT_IRQ
+ */
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK         (0x200U)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT        (9U)
+/*! CH9_CMDCMPLT_IRQ - CH9_CMDCMPLT_IRQ
+ */
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK        (0x400U)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT       (10U)
+/*! CH10_CMDCMPLT_IRQ - CH10_CMDCMPLT_IRQ
+ */
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK        (0x800U)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT       (11U)
+/*! CH11_CMDCMPLT_IRQ - CH11_CMDCMPLT_IRQ
+ */
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK        (0x1000U)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT       (12U)
+/*! CH12_CMDCMPLT_IRQ - CH12_CMDCMPLT_IRQ
+ */
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK        (0x2000U)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT       (13U)
+/*! CH13_CMDCMPLT_IRQ - CH13_CMDCMPLT_IRQ
+ */
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK        (0x4000U)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT       (14U)
+/*! CH14_CMDCMPLT_IRQ - CH14_CMDCMPLT_IRQ
+ */
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK        (0x8000U)
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT       (15U)
+/*! CH15_CMDCMPLT_IRQ - CH15_CMDCMPLT_IRQ
+ */
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK)
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK      (0x10000U)
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT     (16U)
+/*! CH0_CMDCMPLT_IRQ_EN - CH0_CMDCMPLT_IRQ_EN
+ */
+#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK      (0x20000U)
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT     (17U)
+/*! CH1_CMDCMPLT_IRQ_EN - CH1_CMDCMPLT_IRQ_EN
+ */
+#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK      (0x40000U)
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT     (18U)
+/*! CH2_CMDCMPLT_IRQ_EN - CH2_CMDCMPLT_IRQ_EN
+ */
+#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK      (0x80000U)
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT     (19U)
+/*! CH3_CMDCMPLT_IRQ_EN - CH3_CMDCMPLT_IRQ_EN
+ */
+#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK      (0x100000U)
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT     (20U)
+/*! CH4_CMDCMPLT_IRQ_EN - CH4_CMDCMPLT_IRQ_EN
+ */
+#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK      (0x200000U)
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT     (21U)
+/*! CH5_CMDCMPLT_IRQ_EN - CH5_CMDCMPLT_IRQ_EN
+ */
+#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK      (0x400000U)
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT     (22U)
+/*! CH6_CMDCMPLT_IRQ_EN - CH6_CMDCMPLT_IRQ_EN
+ */
+#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK      (0x800000U)
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT     (23U)
+/*! CH7_CMDCMPLT_IRQ_EN - CH7_CMDCMPLT_IRQ_EN
+ */
+#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK      (0x1000000U)
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT     (24U)
+/*! CH8_CMDCMPLT_IRQ_EN - CH8_CMDCMPLT_IRQ_EN
+ */
+#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK      (0x2000000U)
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT     (25U)
+/*! CH9_CMDCMPLT_IRQ_EN - CH9_CMDCMPLT_IRQ_EN
+ */
+#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x)        (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK     (0x4000000U)
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT    (26U)
+/*! CH10_CMDCMPLT_IRQ_EN - CH10_CMDCMPLT_IRQ_EN
+ */
+#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK     (0x8000000U)
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT    (27U)
+/*! CH11_CMDCMPLT_IRQ_EN - CH11_CMDCMPLT_IRQ_EN
+ */
+#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK     (0x10000000U)
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT    (28U)
+/*! CH12_CMDCMPLT_IRQ_EN - CH12_CMDCMPLT_IRQ_EN
+ */
+#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK     (0x20000000U)
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT    (29U)
+/*! CH13_CMDCMPLT_IRQ_EN - CH13_CMDCMPLT_IRQ_EN
+ */
+#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK     (0x40000000U)
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT    (30U)
+/*! CH14_CMDCMPLT_IRQ_EN - CH14_CMDCMPLT_IRQ_EN
+ */
+#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK)
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK     (0x80000000U)
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT    (31U)
+/*! CH15_CMDCMPLT_IRQ_EN - CH15_CMDCMPLT_IRQ_EN
+ */
+#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK)
+/*! @} */
+
+/*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */
+/*! @{ */
+#define APBH_CTRL2_CH0_ERROR_IRQ_MASK            (0x1U)
+#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT           (0U)
+/*! CH0_ERROR_IRQ - CH0_ERROR_IRQ
+ */
+#define APBH_CTRL2_CH0_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH1_ERROR_IRQ_MASK            (0x2U)
+#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT           (1U)
+/*! CH1_ERROR_IRQ - CH1_ERROR_IRQ
+ */
+#define APBH_CTRL2_CH1_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH2_ERROR_IRQ_MASK            (0x4U)
+#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT           (2U)
+/*! CH2_ERROR_IRQ - CH2_ERROR_IRQ
+ */
+#define APBH_CTRL2_CH2_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH3_ERROR_IRQ_MASK            (0x8U)
+#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT           (3U)
+/*! CH3_ERROR_IRQ - CH3_ERROR_IRQ
+ */
+#define APBH_CTRL2_CH3_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH4_ERROR_IRQ_MASK            (0x10U)
+#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT           (4U)
+/*! CH4_ERROR_IRQ - CH4_ERROR_IRQ
+ */
+#define APBH_CTRL2_CH4_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH5_ERROR_IRQ_MASK            (0x20U)
+#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT           (5U)
+/*! CH5_ERROR_IRQ - CH5_ERROR_IRQ
+ */
+#define APBH_CTRL2_CH5_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH6_ERROR_IRQ_MASK            (0x40U)
+#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT           (6U)
+/*! CH6_ERROR_IRQ - CH6_ERROR_IRQ
+ */
+#define APBH_CTRL2_CH6_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH7_ERROR_IRQ_MASK            (0x80U)
+#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT           (7U)
+/*! CH7_ERROR_IRQ - CH7_ERROR_IRQ
+ */
+#define APBH_CTRL2_CH7_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH8_ERROR_IRQ_MASK            (0x100U)
+#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT           (8U)
+/*! CH8_ERROR_IRQ - CH8_ERROR_IRQ
+ */
+#define APBH_CTRL2_CH8_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH9_ERROR_IRQ_MASK            (0x200U)
+#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT           (9U)
+/*! CH9_ERROR_IRQ - CH9_ERROR_IRQ
+ */
+#define APBH_CTRL2_CH9_ERROR_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH10_ERROR_IRQ_MASK           (0x400U)
+#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT          (10U)
+/*! CH10_ERROR_IRQ - CH10_ERROR_IRQ
+ */
+#define APBH_CTRL2_CH10_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH11_ERROR_IRQ_MASK           (0x800U)
+#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT          (11U)
+/*! CH11_ERROR_IRQ - CH11_ERROR_IRQ
+ */
+#define APBH_CTRL2_CH11_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH12_ERROR_IRQ_MASK           (0x1000U)
+#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT          (12U)
+/*! CH12_ERROR_IRQ - CH12_ERROR_IRQ
+ */
+#define APBH_CTRL2_CH12_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH13_ERROR_IRQ_MASK           (0x2000U)
+#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT          (13U)
+/*! CH13_ERROR_IRQ - CH13_ERROR_IRQ
+ */
+#define APBH_CTRL2_CH13_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH14_ERROR_IRQ_MASK           (0x4000U)
+#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT          (14U)
+/*! CH14_ERROR_IRQ - CH14_ERROR_IRQ
+ */
+#define APBH_CTRL2_CH14_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH15_ERROR_IRQ_MASK           (0x8000U)
+#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT          (15U)
+/*! CH15_ERROR_IRQ - CH15_ERROR_IRQ
+ */
+#define APBH_CTRL2_CH15_ERROR_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK)
+#define APBH_CTRL2_CH0_ERROR_STATUS_MASK         (0x10000U)
+#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT        (16U)
+/*! CH0_ERROR_STATUS - CH0_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH0_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH1_ERROR_STATUS_MASK         (0x20000U)
+#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT        (17U)
+/*! CH1_ERROR_STATUS - CH1_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH1_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH2_ERROR_STATUS_MASK         (0x40000U)
+#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT        (18U)
+/*! CH2_ERROR_STATUS - CH2_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH2_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH3_ERROR_STATUS_MASK         (0x80000U)
+#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT        (19U)
+/*! CH3_ERROR_STATUS - CH3_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH3_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH4_ERROR_STATUS_MASK         (0x100000U)
+#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT        (20U)
+/*! CH4_ERROR_STATUS - CH4_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH4_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH5_ERROR_STATUS_MASK         (0x200000U)
+#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT        (21U)
+/*! CH5_ERROR_STATUS - CH5_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH5_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH6_ERROR_STATUS_MASK         (0x400000U)
+#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT        (22U)
+/*! CH6_ERROR_STATUS - CH6_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH6_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH7_ERROR_STATUS_MASK         (0x800000U)
+#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT        (23U)
+/*! CH7_ERROR_STATUS - CH7_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH7_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH8_ERROR_STATUS_MASK         (0x1000000U)
+#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT        (24U)
+/*! CH8_ERROR_STATUS - CH8_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH8_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH9_ERROR_STATUS_MASK         (0x2000000U)
+#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT        (25U)
+/*! CH9_ERROR_STATUS - CH9_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH9_ERROR_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH10_ERROR_STATUS_MASK        (0x4000000U)
+#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT       (26U)
+/*! CH10_ERROR_STATUS - CH10_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH10_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH11_ERROR_STATUS_MASK        (0x8000000U)
+#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT       (27U)
+/*! CH11_ERROR_STATUS - CH11_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH11_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH12_ERROR_STATUS_MASK        (0x10000000U)
+#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT       (28U)
+/*! CH12_ERROR_STATUS - CH12_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH12_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH13_ERROR_STATUS_MASK        (0x20000000U)
+#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT       (29U)
+/*! CH13_ERROR_STATUS - CH13_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH13_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH14_ERROR_STATUS_MASK        (0x40000000U)
+#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT       (30U)
+/*! CH14_ERROR_STATUS - CH14_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH14_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK)
+#define APBH_CTRL2_CH15_ERROR_STATUS_MASK        (0x80000000U)
+#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT       (31U)
+/*! CH15_ERROR_STATUS - CH15_ERROR_STATUS
+ *  0b0..An early termination from the device causes error IRQ.
+ *  0b1..An AHB bus error causes error IRQ.
+ */
+#define APBH_CTRL2_CH15_ERROR_STATUS(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK)
+/*! @} */
+
+/*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */
+/*! @{ */
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK    (0xFFFFU)
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT   (0U)
+/*! FREEZE_CHANNEL - FREEZE_CHANNEL
+ *  0b0000000000000001..
+ *  0b0000000000000010..
+ *  0b0000000000000100..
+ *  0b0000000000001000..
+ *  0b0000000000010000..
+ *  0b0000000000100000..
+ *  0b0000000001000000..
+ *  0b0000000010000000..
+ *  0b0000000100000000..
+ */
+#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x)      (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK     (0xFFFF0000U)
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT    (16U)
+/*! RESET_CHANNEL - RESET_CHANNEL
+ *  0b0000000000000001..
+ *  0b0000000000000010..
+ *  0b0000000000000100..
+ *  0b0000000000001000..
+ *  0b0000000000010000..
+ *  0b0000000000100000..
+ *  0b0000000001000000..
+ *  0b0000000010000000..
+ *  0b0000000100000000..
+ */
+#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK)
+/*! @} */
+
+/*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */
+/*! @{ */
+#define APBH_DMA_BURST_SIZE_CH0_MASK             (0x3U)
+#define APBH_DMA_BURST_SIZE_CH0_SHIFT            (0U)
+/*! CH0 - CH0
+ */
+#define APBH_DMA_BURST_SIZE_CH0(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK)
+#define APBH_DMA_BURST_SIZE_CH1_MASK             (0xCU)
+#define APBH_DMA_BURST_SIZE_CH1_SHIFT            (2U)
+/*! CH1 - CH1
+ */
+#define APBH_DMA_BURST_SIZE_CH1(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK)
+#define APBH_DMA_BURST_SIZE_CH2_MASK             (0x30U)
+#define APBH_DMA_BURST_SIZE_CH2_SHIFT            (4U)
+/*! CH2 - CH2
+ */
+#define APBH_DMA_BURST_SIZE_CH2(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK)
+#define APBH_DMA_BURST_SIZE_CH3_MASK             (0xC0U)
+#define APBH_DMA_BURST_SIZE_CH3_SHIFT            (6U)
+/*! CH3 - CH3
+ */
+#define APBH_DMA_BURST_SIZE_CH3(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK)
+#define APBH_DMA_BURST_SIZE_CH4_MASK             (0x300U)
+#define APBH_DMA_BURST_SIZE_CH4_SHIFT            (8U)
+/*! CH4 - CH4
+ */
+#define APBH_DMA_BURST_SIZE_CH4(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK)
+#define APBH_DMA_BURST_SIZE_CH5_MASK             (0xC00U)
+#define APBH_DMA_BURST_SIZE_CH5_SHIFT            (10U)
+/*! CH5 - CH5
+ */
+#define APBH_DMA_BURST_SIZE_CH5(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK)
+#define APBH_DMA_BURST_SIZE_CH6_MASK             (0x3000U)
+#define APBH_DMA_BURST_SIZE_CH6_SHIFT            (12U)
+/*! CH6 - CH6
+ */
+#define APBH_DMA_BURST_SIZE_CH6(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK)
+#define APBH_DMA_BURST_SIZE_CH7_MASK             (0xC000U)
+#define APBH_DMA_BURST_SIZE_CH7_SHIFT            (14U)
+/*! CH7 - CH7
+ */
+#define APBH_DMA_BURST_SIZE_CH7(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK)
+#define APBH_DMA_BURST_SIZE_CH8_MASK             (0x30000U)
+#define APBH_DMA_BURST_SIZE_CH8_SHIFT            (16U)
+/*! CH8 - CH8
+ *  0b00..
+ *  0b01..
+ *  0b10..
+ */
+#define APBH_DMA_BURST_SIZE_CH8(x)               (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK)
+/*! @} */
+
+/*! @name DEBUG - AHB to APBH DMA Debug Register */
+/*! @{ */
+#define APBH_DEBUG_GPMI_ONE_FIFO_MASK            (0x1U)
+#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT           (0U)
+/*! GPMI_ONE_FIFO - GPMI_ONE_FIFO
+ */
+#define APBH_DEBUG_GPMI_ONE_FIFO(x)              (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK)
+/*! @} */
+
+/*! @name CH_CURCMDAR - APBH DMA Channel n Current Command Address Register */
+/*! @{ */
+#define APBH_CH_CURCMDAR_CMD_ADDR_MASK           (0xFFFFFFFFU)
+#define APBH_CH_CURCMDAR_CMD_ADDR_SHIFT          (0U)
+/*! CMD_ADDR - CMD_ADDR
+ */
+#define APBH_CH_CURCMDAR_CMD_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_CURCMDAR_CMD_ADDR_MASK)
+/*! @} */
+
+/* The count of APBH_CH_CURCMDAR */
+#define APBH_CH_CURCMDAR_COUNT                   (16U)
+
+/*! @name CH_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
+/*! @{ */
+#define APBH_CH_NXTCMDAR_CMD_ADDR_MASK           (0xFFFFFFFFU)
+#define APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT          (0U)
+/*! CMD_ADDR - CMD_ADDR
+ */
+#define APBH_CH_NXTCMDAR_CMD_ADDR(x)             (((uint32_t)(((uint32_t)(x)) << APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_NXTCMDAR_CMD_ADDR_MASK)
+/*! @} */
+
+/* The count of APBH_CH_NXTCMDAR */
+#define APBH_CH_NXTCMDAR_COUNT                   (16U)
+
+/*! @name CH_CMD - APBH DMA Channel n Command Register */
+/*! @{ */
+#define APBH_CH_CMD_COMMAND_MASK                 (0x3U)
+#define APBH_CH_CMD_COMMAND_SHIFT                (0U)
+/*! COMMAND - COMMAND
+ *  0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
+ *  0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
+ *  0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
+ *  0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained
+ *        device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain
+ *        pointer if the peripheral sense line is false.
+ */
+#define APBH_CH_CMD_COMMAND(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_COMMAND_SHIFT)) & APBH_CH_CMD_COMMAND_MASK)
+#define APBH_CH_CMD_CHAIN_MASK                   (0x4U)
+#define APBH_CH_CMD_CHAIN_SHIFT                  (2U)
+/*! CHAIN - CHAIN
+ */
+#define APBH_CH_CMD_CHAIN(x)                     (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CHAIN_SHIFT)) & APBH_CH_CMD_CHAIN_MASK)
+#define APBH_CH_CMD_IRQONCMPLT_MASK              (0x8U)
+#define APBH_CH_CMD_IRQONCMPLT_SHIFT             (3U)
+/*! IRQONCMPLT - IRQONCMPLT
+ */
+#define APBH_CH_CMD_IRQONCMPLT(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_IRQONCMPLT_SHIFT)) & APBH_CH_CMD_IRQONCMPLT_MASK)
+#define APBH_CH_CMD_NANDLOCK_MASK                (0x10U)
+#define APBH_CH_CMD_NANDLOCK_SHIFT               (4U)
+/*! NANDLOCK - NANDLOCK
+ */
+#define APBH_CH_CMD_NANDLOCK(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDLOCK_SHIFT)) & APBH_CH_CMD_NANDLOCK_MASK)
+#define APBH_CH_CMD_NANDWAIT4READY_MASK          (0x20U)
+#define APBH_CH_CMD_NANDWAIT4READY_SHIFT         (5U)
+/*! NANDWAIT4READY - NANDWAIT4READY
+ */
+#define APBH_CH_CMD_NANDWAIT4READY(x)            (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH_CMD_NANDWAIT4READY_MASK)
+#define APBH_CH_CMD_SEMAPHORE_MASK               (0x40U)
+#define APBH_CH_CMD_SEMAPHORE_SHIFT              (6U)
+/*! SEMAPHORE - SEMAPHORE
+ */
+#define APBH_CH_CMD_SEMAPHORE(x)                 (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_SEMAPHORE_SHIFT)) & APBH_CH_CMD_SEMAPHORE_MASK)
+#define APBH_CH_CMD_WAIT4ENDCMD_MASK             (0x80U)
+#define APBH_CH_CMD_WAIT4ENDCMD_SHIFT            (7U)
+/*! WAIT4ENDCMD - WAIT4ENDCMD
+ */
+#define APBH_CH_CMD_WAIT4ENDCMD(x)               (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH_CMD_WAIT4ENDCMD_MASK)
+#define APBH_CH_CMD_HALTONTERMINATE_MASK         (0x100U)
+#define APBH_CH_CMD_HALTONTERMINATE_SHIFT        (8U)
+/*! HALTONTERMINATE - HALTONTERMINATE
+ */
+#define APBH_CH_CMD_HALTONTERMINATE(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH_CMD_HALTONTERMINATE_MASK)
+#define APBH_CH_CMD_CMDWORDS_MASK                (0xF000U)
+#define APBH_CH_CMD_CMDWORDS_SHIFT               (12U)
+/*! CMDWORDS - CMDWORDS
+ */
+#define APBH_CH_CMD_CMDWORDS(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CMDWORDS_SHIFT)) & APBH_CH_CMD_CMDWORDS_MASK)
+#define APBH_CH_CMD_XFER_COUNT_MASK              (0xFFFF0000U)
+#define APBH_CH_CMD_XFER_COUNT_SHIFT             (16U)
+/*! XFER_COUNT - XFER_COUNT
+ */
+#define APBH_CH_CMD_XFER_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_XFER_COUNT_SHIFT)) & APBH_CH_CMD_XFER_COUNT_MASK)
+/*! @} */
+
+/* The count of APBH_CH_CMD */
+#define APBH_CH_CMD_COUNT                        (16U)
+
+/*! @name CH_BAR - APBH DMA Channel n Buffer Address Register */
+/*! @{ */
+#define APBH_CH_BAR_ADDRESS_MASK                 (0xFFFFFFFFU)
+#define APBH_CH_BAR_ADDRESS_SHIFT                (0U)
+/*! ADDRESS - ADDRESS
+ */
+#define APBH_CH_BAR_ADDRESS(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH_BAR_ADDRESS_SHIFT)) & APBH_CH_BAR_ADDRESS_MASK)
+/*! @} */
+
+/* The count of APBH_CH_BAR */
+#define APBH_CH_BAR_COUNT                        (16U)
+
+/*! @name CH_SEMA - APBH DMA Channel n Semaphore Register */
+/*! @{ */
+#define APBH_CH_SEMA_INCREMENT_SEMA_MASK         (0xFFU)
+#define APBH_CH_SEMA_INCREMENT_SEMA_SHIFT        (0U)
+/*! INCREMENT_SEMA - INCREMENT_SEMA
+ */
+#define APBH_CH_SEMA_INCREMENT_SEMA(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH_SEMA_INCREMENT_SEMA_MASK)
+#define APBH_CH_SEMA_PHORE_MASK                  (0xFF0000U)
+#define APBH_CH_SEMA_PHORE_SHIFT                 (16U)
+/*! PHORE - PHORE
+ */
+#define APBH_CH_SEMA_PHORE(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_PHORE_SHIFT)) & APBH_CH_SEMA_PHORE_MASK)
+/*! @} */
+
+/* The count of APBH_CH_SEMA */
+#define APBH_CH_SEMA_COUNT                       (16U)
+
+/*! @name CH_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
+/*! @{ */
+#define APBH_CH_DEBUG1_STATEMACHINE_MASK         (0x1FU)
+#define APBH_CH_DEBUG1_STATEMACHINE_SHIFT        (0U)
+/*! STATEMACHINE - STATEMACHINE
+ *  0b00000..This is the idle state of the DMA state machine.
+ *  0b00001..State in which the DMA is waiting to receive the first word of a command.
+ *  0b00010..State in which the DMA is waiting to receive the third word of a command.
+ *  0b00011..State in which the DMA is waiting to receive the second word of a command.
+ *  0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
+ *  0b00101..The state machine waits in this state for the PIO APB cycles to complete.
+ *  0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the
+ *           PIO words when PIO count is greater than 1.
+ *  0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
+ *  0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
+ *  0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
+ *  0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
+ *  0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
+ *  0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
+ *  0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
+ *  0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
+ *  0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
+ *  0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
+ *  0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and
+ *           effectively halts. A channel reset is required to exit this state
+ *  0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
+ *  0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device
+ *           indicates that the external device is ready.
+ */
+#define APBH_CH_DEBUG1_STATEMACHINE(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH_DEBUG1_STATEMACHINE_MASK)
+#define APBH_CH_DEBUG1_WR_FIFO_FULL_MASK         (0x100000U)
+#define APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT        (20U)
+/*! WR_FIFO_FULL - WR_FIFO_FULL
+ */
+#define APBH_CH_DEBUG1_WR_FIFO_FULL(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_FULL_MASK)
+#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK        (0x200000U)
+#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT       (21U)
+/*! WR_FIFO_EMPTY - WR_FIFO_EMPTY
+ */
+#define APBH_CH_DEBUG1_WR_FIFO_EMPTY(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK)
+#define APBH_CH_DEBUG1_RD_FIFO_FULL_MASK         (0x400000U)
+#define APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT        (22U)
+/*! RD_FIFO_FULL - RD_FIFO_FULL
+ */
+#define APBH_CH_DEBUG1_RD_FIFO_FULL(x)           (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_FULL_MASK)
+#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK        (0x800000U)
+#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT       (23U)
+/*! RD_FIFO_EMPTY - RD_FIFO_EMPTY
+ */
+#define APBH_CH_DEBUG1_RD_FIFO_EMPTY(x)          (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK)
+#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK     (0x1000000U)
+#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT    (24U)
+/*! NEXTCMDADDRVALID - NEXTCMDADDRVALID
+ */
+#define APBH_CH_DEBUG1_NEXTCMDADDRVALID(x)       (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK)
+#define APBH_CH_DEBUG1_READY_MASK                (0x4000000U)
+#define APBH_CH_DEBUG1_READY_SHIFT               (26U)
+/*! READY - READY
+ */
+#define APBH_CH_DEBUG1_READY(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_READY_SHIFT)) & APBH_CH_DEBUG1_READY_MASK)
+#define APBH_CH_DEBUG1_END_MASK                  (0x10000000U)
+#define APBH_CH_DEBUG1_END_SHIFT                 (28U)
+/*! END - END
+ */
+#define APBH_CH_DEBUG1_END(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_END_SHIFT)) & APBH_CH_DEBUG1_END_MASK)
+#define APBH_CH_DEBUG1_KICK_MASK                 (0x20000000U)
+#define APBH_CH_DEBUG1_KICK_SHIFT                (29U)
+/*! KICK - KICK
+ */
+#define APBH_CH_DEBUG1_KICK(x)                   (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_KICK_SHIFT)) & APBH_CH_DEBUG1_KICK_MASK)
+#define APBH_CH_DEBUG1_BURST_MASK                (0x40000000U)
+#define APBH_CH_DEBUG1_BURST_SHIFT               (30U)
+/*! BURST - BURST
+ */
+#define APBH_CH_DEBUG1_BURST(x)                  (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_BURST_SHIFT)) & APBH_CH_DEBUG1_BURST_MASK)
+#define APBH_CH_DEBUG1_REQ_MASK                  (0x80000000U)
+#define APBH_CH_DEBUG1_REQ_SHIFT                 (31U)
+/*! REQ - REQ
+ */
+#define APBH_CH_DEBUG1_REQ(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_REQ_SHIFT)) & APBH_CH_DEBUG1_REQ_MASK)
+/*! @} */
+
+/* The count of APBH_CH_DEBUG1 */
+#define APBH_CH_DEBUG1_COUNT                     (16U)
+
+/*! @name CH_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
+/*! @{ */
+#define APBH_CH_DEBUG2_AHB_BYTES_MASK            (0xFFFFU)
+#define APBH_CH_DEBUG2_AHB_BYTES_SHIFT           (0U)
+/*! AHB_BYTES - AHB_BYTES
+ */
+#define APBH_CH_DEBUG2_AHB_BYTES(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH_DEBUG2_AHB_BYTES_MASK)
+#define APBH_CH_DEBUG2_APB_BYTES_MASK            (0xFFFF0000U)
+#define APBH_CH_DEBUG2_APB_BYTES_SHIFT           (16U)
+/*! APB_BYTES - APB_BYTES
+ */
+#define APBH_CH_DEBUG2_APB_BYTES(x)              (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH_DEBUG2_APB_BYTES_MASK)
+/*! @} */
+
+/* The count of APBH_CH_DEBUG2 */
+#define APBH_CH_DEBUG2_COUNT                     (16U)
+
+/*! @name VERSION - APBH Bridge Version Register */
+/*! @{ */
+#define APBH_VERSION_STEP_MASK                   (0xFFFFU)
+#define APBH_VERSION_STEP_SHIFT                  (0U)
+/*! STEP - STEP
+ */
+#define APBH_VERSION_STEP(x)                     (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK)
+#define APBH_VERSION_MINOR_MASK                  (0xFF0000U)
+#define APBH_VERSION_MINOR_SHIFT                 (16U)
+/*! MINOR - MINOR
+ */
+#define APBH_VERSION_MINOR(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK)
+#define APBH_VERSION_MAJOR_MASK                  (0xFF000000U)
+#define APBH_VERSION_MAJOR_SHIFT                 (24U)
+/*! MAJOR - MAJOR
+ */
+#define APBH_VERSION_MAJOR(x)                    (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group APBH_Register_Masks */
+
+
+/* APBH - Peripheral instance base addresses */
+/** Peripheral CONNECTIVITY__APBH base address */
+#define CONNECTIVITY__APBH_BASE                  (0x5B810000u)
+/** Peripheral CONNECTIVITY__APBH base pointer */
+#define CONNECTIVITY__APBH                       ((APBH_Type *)CONNECTIVITY__APBH_BASE)
+/** Array initializer of APBH peripheral base addresses */
+#define APBH_BASE_ADDRS                          { CONNECTIVITY__APBH_BASE }
+/** Array initializer of APBH peripheral base pointers */
+#define APBH_BASE_PTRS                           { CONNECTIVITY__APBH }
+/** Interrupt vectors for the APBH peripheral type */
+#define APBH_IRQS                                { CONNECTIVITY_APBHDMA_IRQn }
+
+/*!
+ * @}
+ */ /* end of group APBH_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ASMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASMC_Peripheral_Access_Layer ASMC Peripheral Access Layer
+ * @{
+ */
+
+/** ASMC - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t SRS;                               /**< System Reset Status Register, offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t PMPROT;                            /**< Power Mode Protection register, offset: 0x8 */
+  __IO uint32_t PMCTRL;                            /**< Power Mode Control register, offset: 0xC */
+  __IO uint32_t STOPCTRL;                          /**< Stop Control Register, offset: 0x10 */
+  __I  uint32_t PMSTAT;                            /**< Power Mode Status register, offset: 0x14 */
+} ASMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ASMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASMC_Register_Masks ASMC Register Masks
+ * @{
+ */
+
+/*! @name SRS - System Reset Status Register */
+/*! @{ */
+#define ASMC_SRS_WAKEUP_MASK                     (0x1U)
+#define ASMC_SRS_WAKEUP_SHIFT                    (0U)
+/*! WAKEUP - Low Leakage Wakeup Reset
+ *  0b0..Reset not caused by LLWU module wakeup source
+ *  0b1..Reset caused by LLWU module wakeup source
+ */
+#define ASMC_SRS_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WAKEUP_SHIFT)) & ASMC_SRS_WAKEUP_MASK)
+#define ASMC_SRS_WDOG1_MASK                      (0x20U)
+#define ASMC_SRS_WDOG1_SHIFT                     (5U)
+/*! WDOG1 - Watchdog
+ *  0b0..Reset not caused by watchdog timeout
+ *  0b1..Reset caused by watchdog timeout
+ */
+#define ASMC_SRS_WDOG1(x)                        (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WDOG1_SHIFT)) & ASMC_SRS_WDOG1_MASK)
+#define ASMC_SRS_RES_MASK                        (0x40U)
+#define ASMC_SRS_RES_SHIFT                       (6U)
+/*! RES - Chip Reset not POR
+ *  0b0..Chip Reset did not occur
+ *  0b1..Chip Reset caused by a source other than POR occured
+ */
+#define ASMC_SRS_RES(x)                          (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_RES_SHIFT)) & ASMC_SRS_RES_MASK)
+#define ASMC_SRS_POR_MASK                        (0x80U)
+#define ASMC_SRS_POR_SHIFT                       (7U)
+/*! POR - Power-On Reset
+ *  0b0..Reset not caused by POR
+ *  0b1..Reset caused by POR
+ */
+#define ASMC_SRS_POR(x)                          (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_POR_SHIFT)) & ASMC_SRS_POR_MASK)
+#define ASMC_SRS_LOCKUP_MASK                     (0x200U)
+#define ASMC_SRS_LOCKUP_SHIFT                    (9U)
+/*! LOCKUP - Core 1 Lockup
+ *  0b0..Reset not caused by core LOCKUP event
+ *  0b1..Reset caused by core LOCKUP event
+ */
+#define ASMC_SRS_LOCKUP(x)                       (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_LOCKUP_SHIFT)) & ASMC_SRS_LOCKUP_MASK)
+#define ASMC_SRS_SW_MASK                         (0x400U)
+#define ASMC_SRS_SW_SHIFT                        (10U)
+/*! SW - Software
+ *  0b0..Reset not caused by software setting of SYSRESETREQ bit
+ *  0b1..Reset caused by software setting of SYSRESETREQ bit
+ */
+#define ASMC_SRS_SW(x)                           (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SW_SHIFT)) & ASMC_SRS_SW_MASK)
+#define ASMC_SRS_SACKERR_MASK                    (0x1000U)
+#define ASMC_SRS_SACKERR_SHIFT                   (12U)
+/*! SACKERR - Stop Mode Acknowledge Error Reset
+ *  0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
+ *  0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
+ */
+#define ASMC_SRS_SACKERR(x)                      (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SACKERR_SHIFT)) & ASMC_SRS_SACKERR_MASK)
+/*! @} */
+
+/*! @name PMPROT - Power Mode Protection register */
+/*! @{ */
+#define ASMC_PMPROT_AVLLS_MASK                   (0x2U)
+#define ASMC_PMPROT_AVLLS_SHIFT                  (1U)
+/*! AVLLS - Allow Very-Low-Leakage Stop Mode
+ *  0b0..Not Allowed
+ *  0b1..Allowed
+ */
+#define ASMC_PMPROT_AVLLS(x)                     (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLLS_SHIFT)) & ASMC_PMPROT_AVLLS_MASK)
+#define ASMC_PMPROT_ALLS_MASK                    (0x8U)
+#define ASMC_PMPROT_ALLS_SHIFT                   (3U)
+/*! ALLS - Allow Low-Leakage Stop Mode
+ *  0b0..Not Allowed
+ *  0b1..Allowed
+ */
+#define ASMC_PMPROT_ALLS(x)                      (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_ALLS_SHIFT)) & ASMC_PMPROT_ALLS_MASK)
+#define ASMC_PMPROT_AVLP_MASK                    (0x20U)
+#define ASMC_PMPROT_AVLP_SHIFT                   (5U)
+/*! AVLP - Allow Very-Low-Power Modes
+ *  0b0..VLPR, VLPW, and VLPS are not allowed.
+ *  0b1..VLPR, VLPW, and VLPS are allowed.
+ */
+#define ASMC_PMPROT_AVLP(x)                      (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLP_SHIFT)) & ASMC_PMPROT_AVLP_MASK)
+#define ASMC_PMPROT_AHSRUN_MASK                  (0x80U)
+#define ASMC_PMPROT_AHSRUN_SHIFT                 (7U)
+/*! AHSRUN - Allow High Speed Run mode
+ *  0b0..HSRUN is not allowed
+ *  0b1..HSRUN is allowed
+ */
+#define ASMC_PMPROT_AHSRUN(x)                    (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AHSRUN_SHIFT)) & ASMC_PMPROT_AHSRUN_MASK)
+/*! @} */
+
+/*! @name PMCTRL - Power Mode Control register */
+/*! @{ */
+#define ASMC_PMCTRL_STOPM_MASK                   (0x7U)
+#define ASMC_PMCTRL_STOPM_SHIFT                  (0U)
+/*! STOPM - Stop Mode Control
+ *  0b000..Normal Stop (STOP)
+ *  0b001..Reserved
+ *  0b010..Very-Low-Power Stop (VLPS)
+ *  0b011..Low-leakage stop
+ *  0b100..Very-low-leakage stop
+ *  0b101..Reserved
+ *  0b110..Reseved
+ *  0b111..Reserved
+ */
+#define ASMC_PMCTRL_STOPM(x)                     (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_STOPM_SHIFT)) & ASMC_PMCTRL_STOPM_MASK)
+#define ASMC_PMCTRL_RUNM_MASK                    (0x60U)
+#define ASMC_PMCTRL_RUNM_SHIFT                   (5U)
+/*! RUNM - Run Mode Control
+ *  0b00..Normal Run mode (RUN)
+ *  0b01..Reserved
+ *  0b10..Very-Low-Power Run mode (VLPR)
+ *  0b11..High Speed Run mode (HSRUN)
+ */
+#define ASMC_PMCTRL_RUNM(x)                      (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_RUNM_SHIFT)) & ASMC_PMCTRL_RUNM_MASK)
+/*! @} */
+
+/*! @name STOPCTRL - Stop Control Register */
+/*! @{ */
+#define ASMC_STOPCTRL_PSTOPO_MASK                (0xC0U)
+#define ASMC_STOPCTRL_PSTOPO_SHIFT               (6U)
+/*! PSTOPO - Partial Stop Option
+ *  0b00..STOP - Normal Stop mode
+ *  0b01..PSTOP1 - Partial Stop with both system and bus clocks disabled
+ *  0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
+ *  0b11..Reserved
+ */
+#define ASMC_STOPCTRL_PSTOPO(x)                  (((uint32_t)(((uint32_t)(x)) << ASMC_STOPCTRL_PSTOPO_SHIFT)) & ASMC_STOPCTRL_PSTOPO_MASK)
+/*! @} */
+
+/*! @name PMSTAT - Power Mode Status register */
+/*! @{ */
+#define ASMC_PMSTAT_PMSTAT_MASK                  (0xFFU)  /* Merged from fields with different position or width, of widths (7, 8), largest definition used */
+#define ASMC_PMSTAT_PMSTAT_SHIFT                 (0U)
+/*! PMSTAT - Power Mode Status
+ *  0b00000001..Current power mode is RUN.
+ *  0b00000010..Current power mode is STOP.
+ *  0b00000100..Current power mode is VLPR.
+ *  0b00001000..Current power mode is VLPW.
+ *  0b00010000..Current power mode is VLPS.
+ *  0b00100000..Current power mode is LLS.
+ *  0b01000000..Current power mode is VLLS.
+ *  0b10000000..Current power mode is HSRUN
+ */
+#define ASMC_PMSTAT_PMSTAT(x)                    (((uint32_t)(((uint32_t)(x)) << ASMC_PMSTAT_PMSTAT_SHIFT)) & ASMC_PMSTAT_PMSTAT_MASK)  /* Merged from fields with different position or width, of widths (7, 8), largest definition used */
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ASMC_Register_Masks */
+
+
+/* ASMC - Peripheral instance base addresses */
+/** Peripheral CM4__ASMC base address */
+#define CM4__ASMC_BASE                           (0x41410000u)
+/** Peripheral CM4__ASMC base pointer */
+#define CM4__ASMC                                ((ASMC_Type *)CM4__ASMC_BASE)
+/** Peripheral SCU__ASMC base address */
+#define SCU__ASMC_BASE                           (0x33410000u)
+/** Peripheral SCU__ASMC base pointer */
+#define SCU__ASMC                                ((ASMC_Type *)SCU__ASMC_BASE)
+/** Array initializer of ASMC peripheral base addresses */
+#define ASMC_BASE_ADDRS                          { CM4__ASMC_BASE, SCU__ASMC_BASE }
+/** Array initializer of ASMC peripheral base pointers */
+#define ASMC_BASE_PTRS                           { CM4__ASMC, SCU__ASMC }
+
+/*!
+ * @}
+ */ /* end of group ASMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ASRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer
+ * @{
+ */
+
+/** ASRC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t ASRCTR;                            /**< ASRC Control Register, offset: 0x0 */
+  __IO uint32_t ASRIER;                            /**< ASRC Interrupt Enable Register, offset: 0x4 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ASRCNCR;                           /**< ASRC Channel Number Configuration Register, offset: 0xC */
+  __IO uint32_t ASRCFG;                            /**< ASRC Filter Configuration Status Register, offset: 0x10 */
+  __IO uint32_t ASRCSR;                            /**< ASRC Clock Source Register, offset: 0x14 */
+  __IO uint32_t ASRCDR1;                           /**< ASRC Clock Divider Register 1, offset: 0x18 */
+  __IO uint32_t ASRCDR2;                           /**< ASRC Clock Divider Register 2, offset: 0x1C */
+  __I  uint32_t ASRSTR;                            /**< ASRC Status Register, offset: 0x20 */
+       uint8_t RESERVED_1[28];
+  __IO uint32_t ASRPM[5];                          /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */
+  __IO uint32_t ASRTFR1;                           /**< ASRC ASRC Task Queue FIFO Register 1, offset: 0x54 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t ASRCCR;                            /**< ASRC Channel Counter Register, offset: 0x5C */
+  __O  uint32_t ASRDIA;                            /**< ASRC Data Input Register for Pair x, offset: 0x60 */
+  __I  uint32_t ASRDOA;                            /**< ASRC Data Output Register for Pair x, offset: 0x64 */
+  __O  uint32_t ASRDIB;                            /**< ASRC Data Input Register for Pair x, offset: 0x68 */
+  __I  uint32_t ASRDOB;                            /**< ASRC Data Output Register for Pair x, offset: 0x6C */
+  __O  uint32_t ASRDIC;                            /**< ASRC Data Input Register for Pair x, offset: 0x70 */
+  __I  uint32_t ASRDOC;                            /**< ASRC Data Output Register for Pair x, offset: 0x74 */
+       uint8_t RESERVED_3[8];
+  __IO uint32_t ASRIDRHA;                          /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */
+  __IO uint32_t ASRIDRLA;                          /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */
+  __IO uint32_t ASRIDRHB;                          /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */
+  __IO uint32_t ASRIDRLB;                          /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */
+  __IO uint32_t ASRIDRHC;                          /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */
+  __IO uint32_t ASRIDRLC;                          /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */
+  __IO uint32_t ASR76K;                            /**< ASRC 76 kHz Period in terms of ASRC processing clock, offset: 0x98 */
+  __IO uint32_t ASR56K;                            /**< ASRC 56 kHz Period in terms of ASRC processing clock, offset: 0x9C */
+  __IO uint32_t ASRMCRA;                           /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */
+  __I  uint32_t ASRFSTA;                           /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */
+  __IO uint32_t ASRMCRB;                           /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */
+  __I  uint32_t ASRFSTB;                           /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */
+  __IO uint32_t ASRMCRC;                           /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */
+  __I  uint32_t ASRFSTC;                           /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */
+       uint8_t RESERVED_4[8];
+  __IO uint32_t ASRMCR1[3];                        /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4 */
+} ASRC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ASRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASRC_Register_Masks ASRC Register Masks
+ * @{
+ */
+
+/*! @name ASRCTR - ASRC Control Register */
+/*! @{ */
+#define ASRC_ASRCTR_ASRCEN_MASK                  (0x1U)
+#define ASRC_ASRCTR_ASRCEN_SHIFT                 (0U)
+/*! ASRCEN - ASRCEN
+ */
+#define ASRC_ASRCTR_ASRCEN(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK)
+#define ASRC_ASRCTR_ASREA_MASK                   (0x2U)
+#define ASRC_ASRCTR_ASREA_SHIFT                  (1U)
+/*! ASREA - ASREA
+ */
+#define ASRC_ASRCTR_ASREA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK)
+#define ASRC_ASRCTR_ASREB_MASK                   (0x4U)
+#define ASRC_ASRCTR_ASREB_SHIFT                  (2U)
+/*! ASREB - ASREB
+ */
+#define ASRC_ASRCTR_ASREB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK)
+#define ASRC_ASRCTR_ASREC_MASK                   (0x8U)
+#define ASRC_ASRCTR_ASREC_SHIFT                  (3U)
+/*! ASREC - ASREC
+ */
+#define ASRC_ASRCTR_ASREC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK)
+#define ASRC_ASRCTR_SRST_MASK                    (0x10U)
+#define ASRC_ASRCTR_SRST_SHIFT                   (4U)
+/*! SRST - SRST
+ */
+#define ASRC_ASRCTR_SRST(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK)
+#define ASRC_ASRCTR_IDRA_MASK                    (0x2000U)
+#define ASRC_ASRCTR_IDRA_SHIFT                   (13U)
+/*! IDRA - IDRA
+ */
+#define ASRC_ASRCTR_IDRA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK)
+#define ASRC_ASRCTR_USRA_MASK                    (0x4000U)
+#define ASRC_ASRCTR_USRA_SHIFT                   (14U)
+/*! USRA - USRA
+ */
+#define ASRC_ASRCTR_USRA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK)
+#define ASRC_ASRCTR_IDRB_MASK                    (0x8000U)
+#define ASRC_ASRCTR_IDRB_SHIFT                   (15U)
+/*! IDRB - IDRB
+ */
+#define ASRC_ASRCTR_IDRB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK)
+#define ASRC_ASRCTR_USRB_MASK                    (0x10000U)
+#define ASRC_ASRCTR_USRB_SHIFT                   (16U)
+/*! USRB - USRB
+ */
+#define ASRC_ASRCTR_USRB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK)
+#define ASRC_ASRCTR_IDRC_MASK                    (0x20000U)
+#define ASRC_ASRCTR_IDRC_SHIFT                   (17U)
+/*! IDRC - IDRC
+ */
+#define ASRC_ASRCTR_IDRC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK)
+#define ASRC_ASRCTR_USRC_MASK                    (0x40000U)
+#define ASRC_ASRCTR_USRC_SHIFT                   (18U)
+/*! USRC - USRC
+ */
+#define ASRC_ASRCTR_USRC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK)
+#define ASRC_ASRCTR_ATSA_MASK                    (0x100000U)
+#define ASRC_ASRCTR_ATSA_SHIFT                   (20U)
+/*! ATSA - ATSA
+ */
+#define ASRC_ASRCTR_ATSA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK)
+#define ASRC_ASRCTR_ATSB_MASK                    (0x200000U)
+#define ASRC_ASRCTR_ATSB_SHIFT                   (21U)
+/*! ATSB - ATSB
+ */
+#define ASRC_ASRCTR_ATSB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK)
+#define ASRC_ASRCTR_ATSC_MASK                    (0x400000U)
+#define ASRC_ASRCTR_ATSC_SHIFT                   (22U)
+/*! ATSC - ATSC
+ */
+#define ASRC_ASRCTR_ATSC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK)
+/*! @} */
+
+/*! @name ASRIER - ASRC Interrupt Enable Register */
+/*! @{ */
+#define ASRC_ASRIER_ADIEA_MASK                   (0x1U)
+#define ASRC_ASRIER_ADIEA_SHIFT                  (0U)
+/*! ADIEA - ADIEA
+ *  0b1..interrupt enabled
+ *  0b0..interrupt disabled
+ */
+#define ASRC_ASRIER_ADIEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK)
+#define ASRC_ASRIER_ADIEB_MASK                   (0x2U)
+#define ASRC_ASRIER_ADIEB_SHIFT                  (1U)
+/*! ADIEB - ADIEB
+ *  0b1..interrupt enabled
+ *  0b0..interrupt disabled
+ */
+#define ASRC_ASRIER_ADIEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK)
+#define ASRC_ASRIER_ADIEC_MASK                   (0x4U)
+#define ASRC_ASRIER_ADIEC_SHIFT                  (2U)
+/*! ADIEC - ADIEC
+ *  0b1..interrupt enabled
+ *  0b0..interrupt disabled
+ */
+#define ASRC_ASRIER_ADIEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK)
+#define ASRC_ASRIER_ADOEA_MASK                   (0x8U)
+#define ASRC_ASRIER_ADOEA_SHIFT                  (3U)
+/*! ADOEA - ADOEA
+ *  0b1..interrupt enabled
+ *  0b0..interrupt disabled
+ */
+#define ASRC_ASRIER_ADOEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK)
+#define ASRC_ASRIER_ADOEB_MASK                   (0x10U)
+#define ASRC_ASRIER_ADOEB_SHIFT                  (4U)
+/*! ADOEB - ADOEB
+ *  0b1..interrupt enabled
+ *  0b0..interrupt disabled
+ */
+#define ASRC_ASRIER_ADOEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK)
+#define ASRC_ASRIER_ADOEC_MASK                   (0x20U)
+#define ASRC_ASRIER_ADOEC_SHIFT                  (5U)
+/*! ADOEC - ADOEC
+ *  0b1..interrupt enabled
+ *  0b0..interrupt disabled
+ */
+#define ASRC_ASRIER_ADOEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK)
+#define ASRC_ASRIER_AOLIE_MASK                   (0x40U)
+#define ASRC_ASRIER_AOLIE_SHIFT                  (6U)
+/*! AOLIE - AOLIE
+ *  0b1..interrupt enabled
+ *  0b0..interrupt disabled
+ */
+#define ASRC_ASRIER_AOLIE(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK)
+#define ASRC_ASRIER_AFPWE_MASK                   (0x80U)
+#define ASRC_ASRIER_AFPWE_SHIFT                  (7U)
+/*! AFPWE - AFPWE
+ *  0b1..interrupt enabled
+ *  0b0..interrupt disabled
+ */
+#define ASRC_ASRIER_AFPWE(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK)
+/*! @} */
+
+/*! @name ASRCNCR - ASRC Channel Number Configuration Register */
+/*! @{ */
+#define ASRC_ASRCNCR_ANCA_MASK                   (0xFU)
+#define ASRC_ASRCNCR_ANCA_SHIFT                  (0U)
+/*! ANCA - ANCA
+ *  0b0000..0 channels in A (Pair A is disabled)
+ *  0b0001..1 channel in A
+ *  0b0010..2 channels in A
+ *  0b0011..3 channels in A
+ *  0b0100..4 channels in A
+ *  0b0101..5 channels in A
+ *  0b0110..6 channels in A
+ *  0b0111..7 channels in A
+ *  0b1000..8 channels in A
+ *  0b1001..9 channels in A
+ *  0b1010..10 channels in A
+ *  0b1011-0b1111..Should not be used.
+ */
+#define ASRC_ASRCNCR_ANCA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK)
+#define ASRC_ASRCNCR_ANCB_MASK                   (0xF0U)
+#define ASRC_ASRCNCR_ANCB_SHIFT                  (4U)
+/*! ANCB - ANCB
+ *  0b0000..0 channels in B (Pair B is disabled)
+ *  0b0001..1 channel in B
+ *  0b0010..2 channels in B
+ *  0b0011..3 channels in B
+ *  0b0100..4 channels in B
+ *  0b0101..5 channels in B
+ *  0b0110..6 channels in B
+ *  0b0111..7 channels in B
+ *  0b1000..8 channels in B
+ *  0b1001..9 channels in B
+ *  0b1010..10 channels in B
+ *  0b1011-0b1111..Should not be used.
+ */
+#define ASRC_ASRCNCR_ANCB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK)
+#define ASRC_ASRCNCR_ANCC_MASK                   (0xF00U)
+#define ASRC_ASRCNCR_ANCC_SHIFT                  (8U)
+/*! ANCC - ANCC
+ *  0b0000..0 channels in C (Pair C is disabled)
+ *  0b0001..1 channel in C
+ *  0b0010..2 channels in C
+ *  0b0011..3 channels in C
+ *  0b0100..4 channels in C
+ *  0b0101..5 channels in C
+ *  0b0110..6 channels in C
+ *  0b0111..7 channels in C
+ *  0b1000..8 channels in C
+ *  0b1001..9 channels in C
+ *  0b1010..10 channels in C
+ *  0b1011-0b1111..Should not be used.
+ */
+#define ASRC_ASRCNCR_ANCC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK)
+/*! @} */
+
+/*! @name ASRCFG - ASRC Filter Configuration Status Register */
+/*! @{ */
+#define ASRC_ASRCFG_PREMODA_MASK                 (0xC0U)
+#define ASRC_ASRCFG_PREMODA_SHIFT                (6U)
+/*! PREMODA - PREMODA
+ *  0b00..Select Upsampling-by-2 as defined in
+ *  0b01..Select Direct-Connection as defined in
+ *  0b10..Select Downsampling-by-2 as defined in
+ *  0b11..Select passthrough mode. In this case, POSTMODA[1-0] have no use.
+ */
+#define ASRC_ASRCFG_PREMODA(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK)
+#define ASRC_ASRCFG_POSTMODA_MASK                (0x300U)
+#define ASRC_ASRCFG_POSTMODA_SHIFT               (8U)
+/*! POSTMODA - POSTMODA
+ *  0b00..Select Upsampling-by-2 as defined in
+ *  0b01..Select Direct-Connection as defined in
+ *  0b10..Select Downsampling-by-2 as defined in
+ */
+#define ASRC_ASRCFG_POSTMODA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK)
+#define ASRC_ASRCFG_PREMODB_MASK                 (0xC00U)
+#define ASRC_ASRCFG_PREMODB_SHIFT                (10U)
+/*! PREMODB - PREMODB
+ *  0b00..Select Upsampling-by-2 as defined in
+ *  0b01..Select Direct-Connection as defined in
+ *  0b10..Select Downsampling-by-2 as defined in
+ *  0b11..Select passthrough mode. In this case, POSTMODB[1-0] have no use.
+ */
+#define ASRC_ASRCFG_PREMODB(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK)
+#define ASRC_ASRCFG_POSTMODB_MASK                (0x3000U)
+#define ASRC_ASRCFG_POSTMODB_SHIFT               (12U)
+/*! POSTMODB - POSTMODB
+ *  0b00..Select Upsampling-by-2 as defined in
+ *  0b01..Select Direct-Connection as defined in
+ *  0b10..Select Downsampling-by-2 as defined in
+ */
+#define ASRC_ASRCFG_POSTMODB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK)
+#define ASRC_ASRCFG_PREMODC_MASK                 (0xC000U)
+#define ASRC_ASRCFG_PREMODC_SHIFT                (14U)
+/*! PREMODC - PREMODC
+ *  0b00..Select Upsampling-by-2 as defined in
+ *  0b01..Select Direct-Connection as defined in
+ *  0b10..Select Downsampling-by-2 as defined in
+ *  0b11..Select passthrough mode. In this case, POSTMODC[1-0] have no use.
+ */
+#define ASRC_ASRCFG_PREMODC(x)                   (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK)
+#define ASRC_ASRCFG_POSTMODC_MASK                (0x30000U)
+#define ASRC_ASRCFG_POSTMODC_SHIFT               (16U)
+/*! POSTMODC - POSTMODC
+ *  0b00..Select Upsampling-by-2 as defined in Signal Processing Flow.
+ *  0b01..Select Direct-Connection as defined in Signal Processing Flow.
+ *  0b10..Select Downsampling-by-2 as defined in Signal Processing Flow.
+ */
+#define ASRC_ASRCFG_POSTMODC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK)
+#define ASRC_ASRCFG_NDPRA_MASK                   (0x40000U)
+#define ASRC_ASRCFG_NDPRA_SHIFT                  (18U)
+/*! NDPRA - NDPRA
+ *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
+ *  0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
+ */
+#define ASRC_ASRCFG_NDPRA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK)
+#define ASRC_ASRCFG_NDPRB_MASK                   (0x80000U)
+#define ASRC_ASRCFG_NDPRB_SHIFT                  (19U)
+/*! NDPRB - NDPRB
+ *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
+ *  0b1..Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM.
+ */
+#define ASRC_ASRCFG_NDPRB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK)
+#define ASRC_ASRCFG_NDPRC_MASK                   (0x100000U)
+#define ASRC_ASRCFG_NDPRC_SHIFT                  (20U)
+/*! NDPRC - NDPRC
+ *  0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
+ *  0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
+ */
+#define ASRC_ASRCFG_NDPRC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK)
+#define ASRC_ASRCFG_INIRQA_MASK                  (0x200000U)
+#define ASRC_ASRCFG_INIRQA_SHIFT                 (21U)
+/*! INIRQA - INIRQA
+ */
+#define ASRC_ASRCFG_INIRQA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK)
+#define ASRC_ASRCFG_INIRQB_MASK                  (0x400000U)
+#define ASRC_ASRCFG_INIRQB_SHIFT                 (22U)
+/*! INIRQB - INIRQB
+ */
+#define ASRC_ASRCFG_INIRQB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK)
+#define ASRC_ASRCFG_INIRQC_MASK                  (0x800000U)
+#define ASRC_ASRCFG_INIRQC_SHIFT                 (23U)
+/*! INIRQC - INIRQC
+ */
+#define ASRC_ASRCFG_INIRQC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK)
+/*! @} */
+
+/*! @name ASRCSR - ASRC Clock Source Register */
+/*! @{ */
+#define ASRC_ASRCSR_AICSA_MASK                   (0xFU)
+#define ASRC_ASRCSR_AICSA_SHIFT                  (0U)
+/*! AICSA - AICSA
+ *  0b0000..bit clock 0
+ *  0b0001..bit clock 1
+ *  0b0010..bit clock 2
+ *  0b0011..bit clock 3
+ *  0b0100..bit clock 4
+ *  0b0101..bit clock 5
+ *  0b0110..bit clock 6
+ *  0b0111..bit clock 7
+ *  0b1000..bit clock 8
+ *  0b1001..bit clock 9
+ *  0b1010..bit clock A
+ *  0b1011..bit clock B
+ *  0b1100..bit clock C
+ *  0b1101..bit clock D
+ *  0b1110..bit clock E
+ *  0b1111..clock disabled, connected to zero
+ */
+#define ASRC_ASRCSR_AICSA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK)
+#define ASRC_ASRCSR_AICSB_MASK                   (0xF0U)
+#define ASRC_ASRCSR_AICSB_SHIFT                  (4U)
+/*! AICSB - AICSB
+ *  0b0000..bit clock 0
+ *  0b0001..bit clock 1
+ *  0b0010..bit clock 2
+ *  0b0011..bit clock 3
+ *  0b0100..bit clock 4
+ *  0b0101..bit clock 5
+ *  0b0110..bit clock 6
+ *  0b0111..bit clock 7
+ *  0b1000..bit clock 8
+ *  0b1001..bit clock 9
+ *  0b1010..bit clock A
+ *  0b1011..bit clock B
+ *  0b1100..bit clock C
+ *  0b1101..bit clock D
+ *  0b1110..bit clock E
+ *  0b1111..clock disabled, connected to zero
+ */
+#define ASRC_ASRCSR_AICSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK)
+#define ASRC_ASRCSR_AICSC_MASK                   (0xF00U)
+#define ASRC_ASRCSR_AICSC_SHIFT                  (8U)
+/*! AICSC - AICSC
+ *  0b0000..bit clock 0
+ *  0b0001..bit clock 1
+ *  0b0010..bit clock 2
+ *  0b0011..bit clock 3
+ *  0b0100..bit clock 4
+ *  0b0101..bit clock 5
+ *  0b0110..bit clock 6
+ *  0b0111..bit clock 7
+ *  0b1000..bit clock 8
+ *  0b1001..bit clock 9
+ *  0b1010..bit clock A
+ *  0b1011..bit clock B
+ *  0b1100..bit clock C
+ *  0b1101..bit clock D
+ *  0b1110..bit clock E
+ *  0b1111..clock disabled, connected to zero
+ */
+#define ASRC_ASRCSR_AICSC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK)
+#define ASRC_ASRCSR_AOCSA_MASK                   (0xF000U)
+#define ASRC_ASRCSR_AOCSA_SHIFT                  (12U)
+/*! AOCSA - AOCSA
+ *  0b0000..bit clock 0
+ *  0b0001..bit clock 1
+ *  0b0010..bit clock 2
+ *  0b0011..bit clock 3
+ *  0b0100..bit clock 4
+ *  0b0101..bit clock 5
+ *  0b0110..bit clock 6
+ *  0b0111..bit clock 7
+ *  0b1000..bit clock 8
+ *  0b1001..bit clock 9
+ *  0b1010..bit clock A
+ *  0b1011..bit clock B
+ *  0b1100..bit clock C
+ *  0b1101..bit clock D
+ *  0b1110..bit clock E
+ *  0b1111..clock disabled, connected to zero
+ */
+#define ASRC_ASRCSR_AOCSA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK)
+#define ASRC_ASRCSR_AOCSB_MASK                   (0xF0000U)
+#define ASRC_ASRCSR_AOCSB_SHIFT                  (16U)
+/*! AOCSB - AOCSB
+ *  0b0000..bit clock 0
+ *  0b0001..bit clock 1
+ *  0b0010..bit clock 2
+ *  0b0011..bit clock 3
+ *  0b0100..bit clock 4
+ *  0b0101..bit clock 5
+ *  0b0110..bit clock 6
+ *  0b0111..bit clock 7
+ *  0b1000..bit clock 8
+ *  0b1001..bit clock 9
+ *  0b1010..bit clock A
+ *  0b1011..bit clock B
+ *  0b1100..bit clock C
+ *  0b1101..bit clock D
+ *  0b1110..bit clock E
+ *  0b1111..clock disabled, connected to zero
+ */
+#define ASRC_ASRCSR_AOCSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK)
+#define ASRC_ASRCSR_AOCSC_MASK                   (0xF00000U)
+#define ASRC_ASRCSR_AOCSC_SHIFT                  (20U)
+/*! AOCSC - AOCSC
+ *  0b0000..bit clock 0
+ *  0b0001..bit clock 1
+ *  0b0010..bit clock 2
+ *  0b0011..bit clock 3
+ *  0b0100..bit clock 4
+ *  0b0101..bit clock 5
+ *  0b0110..bit clock 6
+ *  0b0111..bit clock 7
+ *  0b1000..bit clock 8
+ *  0b1001..bit clock 9
+ *  0b1010..bit clock A
+ *  0b1011..bit clock B
+ *  0b1100..bit clock C
+ *  0b1101..bit clock D
+ *  0b1110..bit clock E
+ *  0b1111..clock disabled, connected to zero
+ */
+#define ASRC_ASRCSR_AOCSC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK)
+/*! @} */
+
+/*! @name ASRCDR1 - ASRC Clock Divider Register 1 */
+/*! @{ */
+#define ASRC_ASRCDR1_AICPA_MASK                  (0x7U)
+#define ASRC_ASRCDR1_AICPA_SHIFT                 (0U)
+/*! AICPA - AICPA
+ */
+#define ASRC_ASRCDR1_AICPA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK)
+#define ASRC_ASRCDR1_AICDA_MASK                  (0x38U)
+#define ASRC_ASRCDR1_AICDA_SHIFT                 (3U)
+/*! AICDA - AICDA
+ */
+#define ASRC_ASRCDR1_AICDA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK)
+#define ASRC_ASRCDR1_AICPB_MASK                  (0x1C0U)
+#define ASRC_ASRCDR1_AICPB_SHIFT                 (6U)
+/*! AICPB - AICPB
+ */
+#define ASRC_ASRCDR1_AICPB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK)
+#define ASRC_ASRCDR1_AICDB_MASK                  (0xE00U)
+#define ASRC_ASRCDR1_AICDB_SHIFT                 (9U)
+/*! AICDB - AICDB
+ */
+#define ASRC_ASRCDR1_AICDB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK)
+#define ASRC_ASRCDR1_AOCPA_MASK                  (0x7000U)
+#define ASRC_ASRCDR1_AOCPA_SHIFT                 (12U)
+/*! AOCPA - AOCPA
+ */
+#define ASRC_ASRCDR1_AOCPA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK)
+#define ASRC_ASRCDR1_AOCDA_MASK                  (0x38000U)
+#define ASRC_ASRCDR1_AOCDA_SHIFT                 (15U)
+/*! AOCDA - AOCDA
+ */
+#define ASRC_ASRCDR1_AOCDA(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK)
+#define ASRC_ASRCDR1_AOCPB_MASK                  (0x1C0000U)
+#define ASRC_ASRCDR1_AOCPB_SHIFT                 (18U)
+/*! AOCPB - AOCPB
+ */
+#define ASRC_ASRCDR1_AOCPB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK)
+#define ASRC_ASRCDR1_AOCDB_MASK                  (0xE00000U)
+#define ASRC_ASRCDR1_AOCDB_SHIFT                 (21U)
+/*! AOCDB - AOCDB
+ */
+#define ASRC_ASRCDR1_AOCDB(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK)
+/*! @} */
+
+/*! @name ASRCDR2 - ASRC Clock Divider Register 2 */
+/*! @{ */
+#define ASRC_ASRCDR2_AICPC_MASK                  (0x7U)
+#define ASRC_ASRCDR2_AICPC_SHIFT                 (0U)
+/*! AICPC - AICPC
+ */
+#define ASRC_ASRCDR2_AICPC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK)
+#define ASRC_ASRCDR2_AICDC_MASK                  (0x38U)
+#define ASRC_ASRCDR2_AICDC_SHIFT                 (3U)
+/*! AICDC - AICDC
+ */
+#define ASRC_ASRCDR2_AICDC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK)
+#define ASRC_ASRCDR2_AOCPC_MASK                  (0x1C0U)
+#define ASRC_ASRCDR2_AOCPC_SHIFT                 (6U)
+/*! AOCPC - AOCPC
+ */
+#define ASRC_ASRCDR2_AOCPC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK)
+#define ASRC_ASRCDR2_AOCDC_MASK                  (0xE00U)
+#define ASRC_ASRCDR2_AOCDC_SHIFT                 (9U)
+/*! AOCDC - AOCDC
+ */
+#define ASRC_ASRCDR2_AOCDC(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK)
+/*! @} */
+
+/*! @name ASRSTR - ASRC Status Register */
+/*! @{ */
+#define ASRC_ASRSTR_AIDEA_MASK                   (0x1U)
+#define ASRC_ASRSTR_AIDEA_SHIFT                  (0U)
+/*! AIDEA - AIDEA
+ */
+#define ASRC_ASRSTR_AIDEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK)
+#define ASRC_ASRSTR_AIDEB_MASK                   (0x2U)
+#define ASRC_ASRSTR_AIDEB_SHIFT                  (1U)
+/*! AIDEB - AIDEB
+ */
+#define ASRC_ASRSTR_AIDEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK)
+#define ASRC_ASRSTR_AIDEC_MASK                   (0x4U)
+#define ASRC_ASRSTR_AIDEC_SHIFT                  (2U)
+/*! AIDEC - AIDEC
+ */
+#define ASRC_ASRSTR_AIDEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK)
+#define ASRC_ASRSTR_AODFA_MASK                   (0x8U)
+#define ASRC_ASRSTR_AODFA_SHIFT                  (3U)
+/*! AODFA - AODFA
+ */
+#define ASRC_ASRSTR_AODFA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK)
+#define ASRC_ASRSTR_AODFB_MASK                   (0x10U)
+#define ASRC_ASRSTR_AODFB_SHIFT                  (4U)
+/*! AODFB - AODFB
+ */
+#define ASRC_ASRSTR_AODFB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK)
+#define ASRC_ASRSTR_AODFC_MASK                   (0x20U)
+#define ASRC_ASRSTR_AODFC_SHIFT                  (5U)
+/*! AODFC - AODFC
+ */
+#define ASRC_ASRSTR_AODFC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK)
+#define ASRC_ASRSTR_AOLE_MASK                    (0x40U)
+#define ASRC_ASRSTR_AOLE_SHIFT                   (6U)
+/*! AOLE - AOLE
+ */
+#define ASRC_ASRSTR_AOLE(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK)
+#define ASRC_ASRSTR_FPWT_MASK                    (0x80U)
+#define ASRC_ASRSTR_FPWT_SHIFT                   (7U)
+/*! FPWT - FPWT
+ */
+#define ASRC_ASRSTR_FPWT(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK)
+#define ASRC_ASRSTR_AIDUA_MASK                   (0x100U)
+#define ASRC_ASRSTR_AIDUA_SHIFT                  (8U)
+/*! AIDUA - AIDUA
+ */
+#define ASRC_ASRSTR_AIDUA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK)
+#define ASRC_ASRSTR_AIDUB_MASK                   (0x200U)
+#define ASRC_ASRSTR_AIDUB_SHIFT                  (9U)
+/*! AIDUB - AIDUB
+ */
+#define ASRC_ASRSTR_AIDUB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK)
+#define ASRC_ASRSTR_AIDUC_MASK                   (0x400U)
+#define ASRC_ASRSTR_AIDUC_SHIFT                  (10U)
+/*! AIDUC - AIDUC
+ */
+#define ASRC_ASRSTR_AIDUC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK)
+#define ASRC_ASRSTR_AODOA_MASK                   (0x800U)
+#define ASRC_ASRSTR_AODOA_SHIFT                  (11U)
+/*! AODOA - AODOA
+ */
+#define ASRC_ASRSTR_AODOA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK)
+#define ASRC_ASRSTR_AODOB_MASK                   (0x1000U)
+#define ASRC_ASRSTR_AODOB_SHIFT                  (12U)
+/*! AODOB - AODOB
+ */
+#define ASRC_ASRSTR_AODOB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK)
+#define ASRC_ASRSTR_AODOC_MASK                   (0x2000U)
+#define ASRC_ASRSTR_AODOC_SHIFT                  (13U)
+/*! AODOC - AODOC
+ */
+#define ASRC_ASRSTR_AODOC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK)
+#define ASRC_ASRSTR_AIOLA_MASK                   (0x4000U)
+#define ASRC_ASRSTR_AIOLA_SHIFT                  (14U)
+/*! AIOLA - AIOLA
+ */
+#define ASRC_ASRSTR_AIOLA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK)
+#define ASRC_ASRSTR_AIOLB_MASK                   (0x8000U)
+#define ASRC_ASRSTR_AIOLB_SHIFT                  (15U)
+/*! AIOLB - AIOLB
+ */
+#define ASRC_ASRSTR_AIOLB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK)
+#define ASRC_ASRSTR_AIOLC_MASK                   (0x10000U)
+#define ASRC_ASRSTR_AIOLC_SHIFT                  (16U)
+/*! AIOLC - AIOLC
+ */
+#define ASRC_ASRSTR_AIOLC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK)
+#define ASRC_ASRSTR_AOOLA_MASK                   (0x20000U)
+#define ASRC_ASRSTR_AOOLA_SHIFT                  (17U)
+/*! AOOLA - AOOLA
+ */
+#define ASRC_ASRSTR_AOOLA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK)
+#define ASRC_ASRSTR_AOOLB_MASK                   (0x40000U)
+#define ASRC_ASRSTR_AOOLB_SHIFT                  (18U)
+/*! AOOLB - AOOLB
+ */
+#define ASRC_ASRSTR_AOOLB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK)
+#define ASRC_ASRSTR_AOOLC_MASK                   (0x80000U)
+#define ASRC_ASRSTR_AOOLC_SHIFT                  (19U)
+/*! AOOLC - AOOLC
+ */
+#define ASRC_ASRSTR_AOOLC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK)
+#define ASRC_ASRSTR_ATQOL_MASK                   (0x100000U)
+#define ASRC_ASRSTR_ATQOL_SHIFT                  (20U)
+/*! ATQOL - ATQOL
+ */
+#define ASRC_ASRSTR_ATQOL(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK)
+#define ASRC_ASRSTR_DSLCNT_MASK                  (0x200000U)
+#define ASRC_ASRSTR_DSLCNT_SHIFT                 (21U)
+/*! DSLCNT - DSLCNT
+ */
+#define ASRC_ASRSTR_DSLCNT(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK)
+/*! @} */
+
+/*! @name ASRPM - ASRC Parameter Register n */
+/*! @{ */
+#define ASRC_ASRPM_PARAMETER_VALUE_MASK          (0xFFFFFFU)
+#define ASRC_ASRPM_PARAMETER_VALUE_SHIFT         (0U)
+/*! PARAMETER_VALUE - PARAMETER_VALUE
+ */
+#define ASRC_ASRPM_PARAMETER_VALUE(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPM_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPM_PARAMETER_VALUE_MASK)
+/*! @} */
+
+/* The count of ASRC_ASRPM */
+#define ASRC_ASRPM_COUNT                         (5U)
+
+/*! @name ASRTFR1 - ASRC ASRC Task Queue FIFO Register 1 */
+/*! @{ */
+#define ASRC_ASRTFR1_TF_BASE_MASK                (0x1FC0U)
+#define ASRC_ASRTFR1_TF_BASE_SHIFT               (6U)
+/*! TF_BASE - TF_BASE
+ */
+#define ASRC_ASRTFR1_TF_BASE(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK)
+#define ASRC_ASRTFR1_TF_FILL_MASK                (0xFE000U)
+#define ASRC_ASRTFR1_TF_FILL_SHIFT               (13U)
+/*! TF_FILL - TF_FILL
+ */
+#define ASRC_ASRTFR1_TF_FILL(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK)
+/*! @} */
+
+/*! @name ASRCCR - ASRC Channel Counter Register */
+/*! @{ */
+#define ASRC_ASRCCR_ACIA_MASK                    (0xFU)
+#define ASRC_ASRCCR_ACIA_SHIFT                   (0U)
+/*! ACIA - ACIA
+ */
+#define ASRC_ASRCCR_ACIA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK)
+#define ASRC_ASRCCR_ACIB_MASK                    (0xF0U)
+#define ASRC_ASRCCR_ACIB_SHIFT                   (4U)
+/*! ACIB - ACIB
+ */
+#define ASRC_ASRCCR_ACIB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK)
+#define ASRC_ASRCCR_ACIC_MASK                    (0xF00U)
+#define ASRC_ASRCCR_ACIC_SHIFT                   (8U)
+/*! ACIC - ACIC
+ */
+#define ASRC_ASRCCR_ACIC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK)
+#define ASRC_ASRCCR_ACOA_MASK                    (0xF000U)
+#define ASRC_ASRCCR_ACOA_SHIFT                   (12U)
+/*! ACOA - ACOA
+ */
+#define ASRC_ASRCCR_ACOA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK)
+#define ASRC_ASRCCR_ACOB_MASK                    (0xF0000U)
+#define ASRC_ASRCCR_ACOB_SHIFT                   (16U)
+/*! ACOB - ACOB
+ */
+#define ASRC_ASRCCR_ACOB(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK)
+#define ASRC_ASRCCR_ACOC_MASK                    (0xF00000U)
+#define ASRC_ASRCCR_ACOC_SHIFT                   (20U)
+/*! ACOC - ACOC
+ */
+#define ASRC_ASRCCR_ACOC(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK)
+/*! @} */
+
+/*! @name ASRDIA - ASRC Data Input Register for Pair x */
+/*! @{ */
+#define ASRC_ASRDIA_DATA_MASK                    (0xFFFFFFU)
+#define ASRC_ASRDIA_DATA_SHIFT                   (0U)
+/*! DATA - DATA
+ */
+#define ASRC_ASRDIA_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK)
+/*! @} */
+
+/*! @name ASRDOA - ASRC Data Output Register for Pair x */
+/*! @{ */
+#define ASRC_ASRDOA_DATA_MASK                    (0xFFFFFFU)
+#define ASRC_ASRDOA_DATA_SHIFT                   (0U)
+/*! DATA - DATA
+ */
+#define ASRC_ASRDOA_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK)
+/*! @} */
+
+/*! @name ASRDIB - ASRC Data Input Register for Pair x */
+/*! @{ */
+#define ASRC_ASRDIB_DATA_MASK                    (0xFFFFFFU)
+#define ASRC_ASRDIB_DATA_SHIFT                   (0U)
+/*! DATA - DATA
+ */
+#define ASRC_ASRDIB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK)
+/*! @} */
+
+/*! @name ASRDOB - ASRC Data Output Register for Pair x */
+/*! @{ */
+#define ASRC_ASRDOB_DATA_MASK                    (0xFFFFFFU)
+#define ASRC_ASRDOB_DATA_SHIFT                   (0U)
+/*! DATA - DATA
+ */
+#define ASRC_ASRDOB_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK)
+/*! @} */
+
+/*! @name ASRDIC - ASRC Data Input Register for Pair x */
+/*! @{ */
+#define ASRC_ASRDIC_DATA_MASK                    (0xFFFFFFU)
+#define ASRC_ASRDIC_DATA_SHIFT                   (0U)
+/*! DATA - DATA
+ */
+#define ASRC_ASRDIC_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK)
+/*! @} */
+
+/*! @name ASRDOC - ASRC Data Output Register for Pair x */
+/*! @{ */
+#define ASRC_ASRDOC_DATA_MASK                    (0xFFFFFFU)
+#define ASRC_ASRDOC_DATA_SHIFT                   (0U)
+/*! DATA - DATA
+ */
+#define ASRC_ASRDOC_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK)
+/*! @} */
+
+/*! @name ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part */
+/*! @{ */
+#define ASRC_ASRIDRHA_IDRATIOA_H_MASK            (0xFFU)
+#define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT           (0U)
+/*! IDRATIOA_H - IDRATIOA_H
+ */
+#define ASRC_ASRIDRHA_IDRATIOA_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK)
+/*! @} */
+
+/*! @name ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part */
+/*! @{ */
+#define ASRC_ASRIDRLA_IDRATIOA_L_MASK            (0xFFFFFFU)
+#define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT           (0U)
+/*! IDRATIOA_L - IDRATIOA_L
+ */
+#define ASRC_ASRIDRLA_IDRATIOA_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK)
+/*! @} */
+
+/*! @name ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part */
+/*! @{ */
+#define ASRC_ASRIDRHB_IDRATIOB_H_MASK            (0xFFU)
+#define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT           (0U)
+/*! IDRATIOB_H - IDRATIOB_H
+ */
+#define ASRC_ASRIDRHB_IDRATIOB_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK)
+/*! @} */
+
+/*! @name ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part */
+/*! @{ */
+#define ASRC_ASRIDRLB_IDRATIOB_L_MASK            (0xFFFFFFU)
+#define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT           (0U)
+/*! IDRATIOB_L - IDRATIOB_L
+ */
+#define ASRC_ASRIDRLB_IDRATIOB_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK)
+/*! @} */
+
+/*! @name ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part */
+/*! @{ */
+#define ASRC_ASRIDRHC_IDRATIOC_H_MASK            (0xFFU)
+#define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT           (0U)
+/*! IDRATIOC_H - IDRATIOC_H
+ */
+#define ASRC_ASRIDRHC_IDRATIOC_H(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK)
+/*! @} */
+
+/*! @name ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part */
+/*! @{ */
+#define ASRC_ASRIDRLC_IDRATIOC_L_MASK            (0xFFFFFFU)
+#define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT           (0U)
+/*! IDRATIOC_L - IDRATIOC_L
+ */
+#define ASRC_ASRIDRLC_IDRATIOC_L(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK)
+/*! @} */
+
+/*! @name ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock */
+/*! @{ */
+#define ASRC_ASR76K_ASR76K_MASK                  (0x1FFFFU)
+#define ASRC_ASR76K_ASR76K_SHIFT                 (0U)
+/*! ASR76K - ASR76K
+ */
+#define ASRC_ASR76K_ASR76K(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK)
+/*! @} */
+
+/*! @name ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock */
+/*! @{ */
+#define ASRC_ASR56K_ASR56K_MASK                  (0x1FFFFU)
+#define ASRC_ASR56K_ASR56K_SHIFT                 (0U)
+/*! ASR56K - ASR56K
+ */
+#define ASRC_ASR56K_ASR56K(x)                    (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK)
+/*! @} */
+
+/*! @name ASRMCRA - ASRC Misc Control Register for Pair A */
+/*! @{ */
+#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK      (0x3FU)
+#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT     (0U)
+/*! INFIFO_THRESHOLDA - INFIFO_THRESHOLDA
+ */
+#define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK)
+#define ASRC_ASRMCRA_RSYNOFA_MASK                (0x400U)
+#define ASRC_ASRMCRA_RSYNOFA_SHIFT               (10U)
+/*! RSYNOFA - RSYNOFA
+ */
+#define ASRC_ASRMCRA_RSYNOFA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK)
+#define ASRC_ASRMCRA_RSYNIFA_MASK                (0x800U)
+#define ASRC_ASRMCRA_RSYNIFA_SHIFT               (11U)
+/*! RSYNIFA - RSYNIFA
+ */
+#define ASRC_ASRMCRA_RSYNIFA(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK)
+#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK     (0x3F000U)
+#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT    (12U)
+/*! OUTFIFO_THRESHOLDA - OUTFIFO_THRESHOLDA
+ */
+#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK)
+#define ASRC_ASRMCRA_BYPASSPOLYA_MASK            (0x100000U)
+#define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT           (20U)
+/*! BYPASSPOLYA - BYPASSPOLYA
+ *  0b1..Bypass polyphase filtering.
+ *  0b0..Don't bypass polyphase filtering.
+ */
+#define ASRC_ASRMCRA_BYPASSPOLYA(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK)
+#define ASRC_ASRMCRA_BUFSTALLA_MASK              (0x200000U)
+#define ASRC_ASRMCRA_BUFSTALLA_SHIFT             (21U)
+/*! BUFSTALLA - BUFSTALLA
+ *  0b1..Stall Pair A conversion in case of near empty/full FIFO conditions.
+ *  0b0..Don't stall Pair A conversion even in case of near empty/full FIFO conditions.
+ */
+#define ASRC_ASRMCRA_BUFSTALLA(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK)
+#define ASRC_ASRMCRA_EXTTHRSHA_MASK              (0x400000U)
+#define ASRC_ASRMCRA_EXTTHRSHA_SHIFT             (22U)
+/*! EXTTHRSHA - EXTTHRSHA
+ *  0b1..Use external defined thresholds.
+ *  0b0..Use default thresholds.
+ */
+#define ASRC_ASRMCRA_EXTTHRSHA(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK)
+#define ASRC_ASRMCRA_ZEROBUFA_MASK               (0x800000U)
+#define ASRC_ASRMCRA_ZEROBUFA_SHIFT              (23U)
+/*! ZEROBUFA - ZEROBUFA
+ *  0b1..Don't zeroize the buffer
+ *  0b0..Zeroize the buffer
+ */
+#define ASRC_ASRMCRA_ZEROBUFA(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK)
+/*! @} */
+
+/*! @name ASRFSTA - ASRC FIFO Status Register for Pair A */
+/*! @{ */
+#define ASRC_ASRFSTA_INFIFO_FILLA_MASK           (0x7FU)
+#define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT          (0U)
+/*! INFIFO_FILLA - INFIFO_FILLA
+ */
+#define ASRC_ASRFSTA_INFIFO_FILLA(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK)
+#define ASRC_ASRFSTA_IAEA_MASK                   (0x800U)
+#define ASRC_ASRFSTA_IAEA_SHIFT                  (11U)
+/*! IAEA - IAEA
+ */
+#define ASRC_ASRFSTA_IAEA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK)
+#define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK          (0x7F000U)
+#define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT         (12U)
+/*! OUTFIFO_FILLA - OUTFIFO_FILLA
+ */
+#define ASRC_ASRFSTA_OUTFIFO_FILLA(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK)
+#define ASRC_ASRFSTA_OAFA_MASK                   (0x800000U)
+#define ASRC_ASRFSTA_OAFA_SHIFT                  (23U)
+/*! OAFA - OAFA
+ */
+#define ASRC_ASRFSTA_OAFA(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK)
+/*! @} */
+
+/*! @name ASRMCRB - ASRC Misc Control Register for Pair B */
+/*! @{ */
+#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK      (0x3FU)
+#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT     (0U)
+/*! INFIFO_THRESHOLDB - INFIFO_THRESHOLDB
+ */
+#define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK)
+#define ASRC_ASRMCRB_RSYNOFB_MASK                (0x400U)
+#define ASRC_ASRMCRB_RSYNOFB_SHIFT               (10U)
+/*! RSYNOFB - RSYNOFB
+ */
+#define ASRC_ASRMCRB_RSYNOFB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK)
+#define ASRC_ASRMCRB_RSYNIFB_MASK                (0x800U)
+#define ASRC_ASRMCRB_RSYNIFB_SHIFT               (11U)
+/*! RSYNIFB - RSYNIFB
+ */
+#define ASRC_ASRMCRB_RSYNIFB(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK)
+#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK     (0x3F000U)
+#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT    (12U)
+/*! OUTFIFO_THRESHOLDB - OUTFIFO_THRESHOLDB
+ */
+#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK)
+#define ASRC_ASRMCRB_BYPASSPOLYB_MASK            (0x100000U)
+#define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT           (20U)
+/*! BYPASSPOLYB - BYPASSPOLYB
+ *  0b1..Bypass polyphase filtering.
+ *  0b0..Don't bypass polyphase filtering.
+ */
+#define ASRC_ASRMCRB_BYPASSPOLYB(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK)
+#define ASRC_ASRMCRB_BUFSTALLB_MASK              (0x200000U)
+#define ASRC_ASRMCRB_BUFSTALLB_SHIFT             (21U)
+/*! BUFSTALLB - BUFSTALLB
+ *  0b1..Stall Pair B conversion in case of near empty/full FIFO conditions.
+ *  0b0..Don't stall Pair B conversion even in case of near empty/full FIFO conditions.
+ */
+#define ASRC_ASRMCRB_BUFSTALLB(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK)
+#define ASRC_ASRMCRB_EXTTHRSHB_MASK              (0x400000U)
+#define ASRC_ASRMCRB_EXTTHRSHB_SHIFT             (22U)
+/*! EXTTHRSHB - EXTTHRSHB
+ *  0b1..Use external defined thresholds.
+ *  0b0..Use default thresholds.
+ */
+#define ASRC_ASRMCRB_EXTTHRSHB(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK)
+#define ASRC_ASRMCRB_ZEROBUFB_MASK               (0x800000U)
+#define ASRC_ASRMCRB_ZEROBUFB_SHIFT              (23U)
+/*! ZEROBUFB - ZEROBUFB
+ *  0b1..Don't zeroize the buffer
+ *  0b0..Zeroize the buffer
+ */
+#define ASRC_ASRMCRB_ZEROBUFB(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK)
+/*! @} */
+
+/*! @name ASRFSTB - ASRC FIFO Status Register for Pair B */
+/*! @{ */
+#define ASRC_ASRFSTB_INFIFO_FILLB_MASK           (0x7FU)
+#define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT          (0U)
+/*! INFIFO_FILLB - INFIFO_FILLB
+ */
+#define ASRC_ASRFSTB_INFIFO_FILLB(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK)
+#define ASRC_ASRFSTB_IAEB_MASK                   (0x800U)
+#define ASRC_ASRFSTB_IAEB_SHIFT                  (11U)
+/*! IAEB - IAEB
+ */
+#define ASRC_ASRFSTB_IAEB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK)
+#define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK          (0x7F000U)
+#define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT         (12U)
+/*! OUTFIFO_FILLB - OUTFIFO_FILLB
+ */
+#define ASRC_ASRFSTB_OUTFIFO_FILLB(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK)
+#define ASRC_ASRFSTB_OAFB_MASK                   (0x800000U)
+#define ASRC_ASRFSTB_OAFB_SHIFT                  (23U)
+/*! OAFB - OAFB
+ */
+#define ASRC_ASRFSTB_OAFB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK)
+/*! @} */
+
+/*! @name ASRMCRC - ASRC Misc Control Register for Pair C */
+/*! @{ */
+#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK      (0x3FU)
+#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT     (0U)
+/*! INFIFO_THRESHOLDC - INFIFO_THRESHOLDC
+ */
+#define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x)        (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK)
+#define ASRC_ASRMCRC_RSYNOFC_MASK                (0x400U)
+#define ASRC_ASRMCRC_RSYNOFC_SHIFT               (10U)
+/*! RSYNOFC - RSYNOFC
+ */
+#define ASRC_ASRMCRC_RSYNOFC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK)
+#define ASRC_ASRMCRC_RSYNIFC_MASK                (0x800U)
+#define ASRC_ASRMCRC_RSYNIFC_SHIFT               (11U)
+/*! RSYNIFC - RSYNIFC
+ */
+#define ASRC_ASRMCRC_RSYNIFC(x)                  (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK)
+#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK     (0x3F000U)
+#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT    (12U)
+/*! OUTFIFO_THRESHOLDC - OUTFIFO_THRESHOLDC
+ */
+#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x)       (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK)
+#define ASRC_ASRMCRC_BYPASSPOLYC_MASK            (0x100000U)
+#define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT           (20U)
+/*! BYPASSPOLYC - BYPASSPOLYC
+ *  0b1..Bypass polyphase filtering.
+ *  0b0..Don't bypass polyphase filtering.
+ */
+#define ASRC_ASRMCRC_BYPASSPOLYC(x)              (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK)
+#define ASRC_ASRMCRC_BUFSTALLC_MASK              (0x200000U)
+#define ASRC_ASRMCRC_BUFSTALLC_SHIFT             (21U)
+/*! BUFSTALLC - BUFSTALLC
+ *  0b1..Stall Pair C conversion in case of near empty/full FIFO conditions.
+ *  0b0..Don't stall Pair C conversion even in case of near empty/full FIFO conditions.
+ */
+#define ASRC_ASRMCRC_BUFSTALLC(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK)
+#define ASRC_ASRMCRC_EXTTHRSHC_MASK              (0x400000U)
+#define ASRC_ASRMCRC_EXTTHRSHC_SHIFT             (22U)
+/*! EXTTHRSHC - EXTTHRSHC
+ *  0b1..Use external defined thresholds.
+ *  0b0..Use default thresholds.
+ */
+#define ASRC_ASRMCRC_EXTTHRSHC(x)                (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK)
+#define ASRC_ASRMCRC_ZEROBUFC_MASK               (0x800000U)
+#define ASRC_ASRMCRC_ZEROBUFC_SHIFT              (23U)
+/*! ZEROBUFC - ZEROBUFC
+ *  0b1..Don't zeroize the buffer
+ *  0b0..Zeroize the buffer
+ */
+#define ASRC_ASRMCRC_ZEROBUFC(x)                 (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK)
+/*! @} */
+
+/*! @name ASRFSTC - ASRC FIFO Status Register for Pair C */
+/*! @{ */
+#define ASRC_ASRFSTC_INFIFO_FILLC_MASK           (0x7FU)
+#define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT          (0U)
+/*! INFIFO_FILLC - INFIFO_FILLC
+ */
+#define ASRC_ASRFSTC_INFIFO_FILLC(x)             (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK)
+#define ASRC_ASRFSTC_IAEC_MASK                   (0x800U)
+#define ASRC_ASRFSTC_IAEC_SHIFT                  (11U)
+/*! IAEC - IAEC
+ */
+#define ASRC_ASRFSTC_IAEC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK)
+#define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK          (0x7F000U)
+#define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT         (12U)
+/*! OUTFIFO_FILLC - OUTFIFO_FILLC
+ */
+#define ASRC_ASRFSTC_OUTFIFO_FILLC(x)            (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK)
+#define ASRC_ASRFSTC_OAFC_MASK                   (0x800000U)
+#define ASRC_ASRFSTC_OAFC_SHIFT                  (23U)
+/*! OAFC - OAFC
+ */
+#define ASRC_ASRFSTC_OAFC(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK)
+/*! @} */
+
+/*! @name ASRMCR1 - ASRC Misc Control Register 1 for Pair X */
+/*! @{ */
+#define ASRC_ASRMCR1_OW16_MASK                   (0x1U)
+#define ASRC_ASRMCR1_OW16_SHIFT                  (0U)
+/*! OW16 - OW16
+ *  0b1..16-bit output data
+ *  0b0..24-bit output data.
+ */
+#define ASRC_ASRMCR1_OW16(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK)
+#define ASRC_ASRMCR1_OSGN_MASK                   (0x2U)
+#define ASRC_ASRMCR1_OSGN_SHIFT                  (1U)
+/*! OSGN - OSGN
+ *  0b1..Sign extension.
+ *  0b0..No sign extension.
+ */
+#define ASRC_ASRMCR1_OSGN(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK)
+#define ASRC_ASRMCR1_OMSB_MASK                   (0x4U)
+#define ASRC_ASRMCR1_OMSB_SHIFT                  (2U)
+/*! OMSB - OMSB
+ *  0b1..MSB aligned.
+ *  0b0..LSB aligned.
+ */
+#define ASRC_ASRMCR1_OMSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK)
+#define ASRC_ASRMCR1_IMSB_MASK                   (0x100U)
+#define ASRC_ASRMCR1_IMSB_SHIFT                  (8U)
+/*! IMSB - IMSB
+ *  0b1..MSB aligned.
+ *  0b0..LSB aligned.
+ */
+#define ASRC_ASRMCR1_IMSB(x)                     (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK)
+#define ASRC_ASRMCR1_IWD_MASK                    (0xE00U)
+#define ASRC_ASRMCR1_IWD_SHIFT                   (9U)
+/*! IWD - IWD
+ */
+#define ASRC_ASRMCR1_IWD(x)                      (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK)
+/*! @} */
+
+/* The count of ASRC_ASRMCR1 */
+#define ASRC_ASRMCR1_COUNT                       (3U)
+
+
+/*!
+ * @}
+ */ /* end of group ASRC_Register_Masks */
+
+
+/* ASRC - Peripheral instance base addresses */
+/** Peripheral ADMA__ASRC0 base address */
+#define ADMA__ASRC0_BASE                         (0x59000000u)
+/** Peripheral ADMA__ASRC0 base pointer */
+#define ADMA__ASRC0                              ((ASRC_Type *)ADMA__ASRC0_BASE)
+/** Peripheral ADMA__ASRC1 base address */
+#define ADMA__ASRC1_BASE                         (0x59800000u)
+/** Peripheral ADMA__ASRC1 base pointer */
+#define ADMA__ASRC1                              ((ASRC_Type *)ADMA__ASRC1_BASE)
+/** Array initializer of ASRC peripheral base addresses */
+#define ASRC_BASE_ADDRS                          { ADMA__ASRC0_BASE, ADMA__ASRC1_BASE }
+/** Array initializer of ASRC peripheral base pointers */
+#define ASRC_BASE_PTRS                           { ADMA__ASRC0, ADMA__ASRC1 }
+
+/*!
+ * @}
+ */ /* end of group ASRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- BCH Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer
+ * @{
+ */
+
+/** BCH - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0 */
+    __IO uint32_t RW;                                /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */
+    __IO uint32_t SET;                               /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */
+    __IO uint32_t CLR;                               /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */
+    __IO uint32_t TOG;                               /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */
+  } CTRL;
+  struct {                                         /* offset: 0x10 */
+    __I  uint32_t RW;                                /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */
+    __I  uint32_t SET;                               /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */
+    __I  uint32_t CLR;                               /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */
+    __I  uint32_t TOG;                               /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */
+  } STATUS0;
+  struct {                                         /* offset: 0x20 */
+    __IO uint32_t RW;                                /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */
+    __IO uint32_t SET;                               /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */
+    __IO uint32_t CLR;                               /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */
+    __IO uint32_t TOG;                               /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */
+  } MODE;
+  struct {                                         /* offset: 0x30 */
+    __IO uint32_t RW;                                /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */
+    __IO uint32_t SET;                               /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */
+    __IO uint32_t CLR;                               /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */
+    __IO uint32_t TOG;                               /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */
+  } ENCODEPTR;
+  struct {                                         /* offset: 0x40 */
+    __IO uint32_t RW;                                /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */
+    __IO uint32_t SET;                               /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */
+    __IO uint32_t CLR;                               /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */
+    __IO uint32_t TOG;                               /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */
+  } DATAPTR;
+  struct {                                         /* offset: 0x50 */
+    __IO uint32_t RW;                                /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */
+    __IO uint32_t SET;                               /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */
+    __IO uint32_t CLR;                               /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */
+    __IO uint32_t TOG;                               /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */
+  } METAPTR;
+       uint8_t RESERVED_0[16];
+  struct {                                         /* offset: 0x70 */
+    __IO uint32_t RW;                                /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */
+    __IO uint32_t SET;                               /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */
+    __IO uint32_t CLR;                               /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */
+    __IO uint32_t TOG;                               /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */
+  } LAYOUTSELECT;
+  struct {                                         /* offset: 0x80 */
+    __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */
+    __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */
+    __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */
+    __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */
+  } FLASH0LAYOUT0;
+  struct {                                         /* offset: 0x90 */
+    __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */
+    __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */
+    __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */
+    __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */
+  } FLASH0LAYOUT1;
+  struct {                                         /* offset: 0xA0 */
+    __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */
+    __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */
+    __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */
+    __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */
+  } FLASH1LAYOUT0;
+  struct {                                         /* offset: 0xB0 */
+    __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */
+    __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */
+    __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */
+    __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */
+  } FLASH1LAYOUT1;
+  struct {                                         /* offset: 0xC0 */
+    __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */
+    __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */
+    __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */
+    __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */
+  } FLASH2LAYOUT0;
+  struct {                                         /* offset: 0xD0 */
+    __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */
+    __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */
+    __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */
+    __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */
+  } FLASH2LAYOUT1;
+  struct {                                         /* offset: 0xE0 */
+    __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */
+    __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */
+    __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */
+    __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */
+  } FLASH3LAYOUT0;
+  struct {                                         /* offset: 0xF0 */
+    __IO uint32_t RW;                                /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */
+    __IO uint32_t SET;                               /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */
+    __IO uint32_t CLR;                               /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */
+    __IO uint32_t TOG;                               /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */
+  } FLASH3LAYOUT1;
+  struct {                                         /* offset: 0x100 */
+    __IO uint32_t RW;                                /**< Hardware BCH ECC Debug Register0, offset: 0x100 */
+    __IO uint32_t SET;                               /**< Hardware BCH ECC Debug Register0, offset: 0x104 */
+    __IO uint32_t CLR;                               /**< Hardware BCH ECC Debug Register0, offset: 0x108 */
+    __IO uint32_t TOG;                               /**< Hardware BCH ECC Debug Register0, offset: 0x10C */
+  } DEBUG0;
+  struct {                                         /* offset: 0x110 */
+    __I  uint32_t RW;                                /**< KES Debug Read Register, offset: 0x110 */
+    __I  uint32_t SET;                               /**< KES Debug Read Register, offset: 0x114 */
+    __I  uint32_t CLR;                               /**< KES Debug Read Register, offset: 0x118 */
+    __I  uint32_t TOG;                               /**< KES Debug Read Register, offset: 0x11C */
+  } DBGKESREAD;
+  struct {                                         /* offset: 0x120 */
+    __I  uint32_t RW;                                /**< Chien Search Debug Read Register, offset: 0x120 */
+    __I  uint32_t SET;                               /**< Chien Search Debug Read Register, offset: 0x124 */
+    __I  uint32_t CLR;                               /**< Chien Search Debug Read Register, offset: 0x128 */
+    __I  uint32_t TOG;                               /**< Chien Search Debug Read Register, offset: 0x12C */
+  } DBGCSFEREAD;
+  struct {                                         /* offset: 0x130 */
+    __I  uint32_t RW;                                /**< Syndrome Generator Debug Read Register, offset: 0x130 */
+    __I  uint32_t SET;                               /**< Syndrome Generator Debug Read Register, offset: 0x134 */
+    __I  uint32_t CLR;                               /**< Syndrome Generator Debug Read Register, offset: 0x138 */
+    __I  uint32_t TOG;                               /**< Syndrome Generator Debug Read Register, offset: 0x13C */
+  } DBGSYNDGENREAD;
+  struct {                                         /* offset: 0x140 */
+    __I  uint32_t RW;                                /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */
+    __I  uint32_t SET;                               /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */
+    __I  uint32_t CLR;                               /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */
+    __I  uint32_t TOG;                               /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */
+  } DBGAHBMREAD;
+  struct {                                         /* offset: 0x150 */
+    __I  uint32_t RW;                                /**< Block Name Register, offset: 0x150 */
+    __I  uint32_t SET;                               /**< Block Name Register, offset: 0x154 */
+    __I  uint32_t CLR;                               /**< Block Name Register, offset: 0x158 */
+    __I  uint32_t TOG;                               /**< Block Name Register, offset: 0x15C */
+  } BLOCKNAME;
+  struct {                                         /* offset: 0x160 */
+    __I  uint32_t RW;                                /**< BCH Version Register, offset: 0x160 */
+    __I  uint32_t SET;                               /**< BCH Version Register, offset: 0x164 */
+    __I  uint32_t CLR;                               /**< BCH Version Register, offset: 0x168 */
+    __I  uint32_t TOG;                               /**< BCH Version Register, offset: 0x16C */
+  } VERSION;
+  struct {                                         /* offset: 0x170 */
+    __IO uint32_t RW;                                /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */
+    __IO uint32_t SET;                               /**< Hardware BCH ECC Debug Register 1, offset: 0x174 */
+    __IO uint32_t CLR;                               /**< Hardware BCH ECC Debug Register 1, offset: 0x178 */
+    __IO uint32_t TOG;                               /**< Hardware BCH ECC Debug Register 1, offset: 0x17C */
+  } DEBUG1;
+} BCH_Type;
+
+/* ----------------------------------------------------------------------------
+   -- BCH Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup BCH_Register_Masks BCH Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Hardware BCH ECC Accelerator Control Register */
+/*! @{ */
+#define BCH_CTRL_COMPLETE_IRQ_MASK               (0x1U)
+#define BCH_CTRL_COMPLETE_IRQ_SHIFT              (0U)
+/*! COMPLETE_IRQ - COMPLETE_IRQ
+ */
+#define BCH_CTRL_COMPLETE_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK)
+#define BCH_CTRL_RSVD0_MASK                      (0x2U)
+#define BCH_CTRL_RSVD0_SHIFT                     (1U)
+/*! RSVD0 - This field is reserved.
+ */
+#define BCH_CTRL_RSVD0(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK)
+#define BCH_CTRL_DEBUG_STALL_IRQ_MASK            (0x4U)
+#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT           (2U)
+/*! DEBUG_STALL_IRQ - DEBUG_STALL_IRQ
+ */
+#define BCH_CTRL_DEBUG_STALL_IRQ(x)              (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK)
+#define BCH_CTRL_BM_ERROR_IRQ_MASK               (0x8U)
+#define BCH_CTRL_BM_ERROR_IRQ_SHIFT              (3U)
+/*! BM_ERROR_IRQ - BM_ERROR_IRQ
+ */
+#define BCH_CTRL_BM_ERROR_IRQ(x)                 (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK)
+#define BCH_CTRL_RSVD1_MASK                      (0xF0U)
+#define BCH_CTRL_RSVD1_SHIFT                     (4U)
+/*! RSVD1 - This field is reserved.
+ */
+#define BCH_CTRL_RSVD1(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK)
+#define BCH_CTRL_COMPLETE_IRQ_EN_MASK            (0x100U)
+#define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT           (8U)
+/*! COMPLETE_IRQ_EN - COMPLETE_IRQ_EN
+ */
+#define BCH_CTRL_COMPLETE_IRQ_EN(x)              (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK)
+#define BCH_CTRL_RSVD2_MASK                      (0x200U)
+#define BCH_CTRL_RSVD2_SHIFT                     (9U)
+/*! RSVD2 - This field is reserved.
+ */
+#define BCH_CTRL_RSVD2(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK)
+#define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK         (0x400U)
+#define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT        (10U)
+/*! DEBUG_STALL_IRQ_EN - DEBUG_STALL_IRQ_EN
+ */
+#define BCH_CTRL_DEBUG_STALL_IRQ_EN(x)           (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK)
+#define BCH_CTRL_RSVD3_MASK                      (0xF800U)
+#define BCH_CTRL_RSVD3_SHIFT                     (11U)
+/*! RSVD3 - This field is reserved.
+ */
+#define BCH_CTRL_RSVD3(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK)
+#define BCH_CTRL_M2M_ENABLE_MASK                 (0x10000U)
+#define BCH_CTRL_M2M_ENABLE_SHIFT                (16U)
+/*! M2M_ENABLE - M2M_ENABLE
+ */
+#define BCH_CTRL_M2M_ENABLE(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK)
+#define BCH_CTRL_M2M_ENCODE_MASK                 (0x20000U)
+#define BCH_CTRL_M2M_ENCODE_SHIFT                (17U)
+/*! M2M_ENCODE - M2M_ENCODE
+ */
+#define BCH_CTRL_M2M_ENCODE(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK)
+#define BCH_CTRL_M2M_LAYOUT_MASK                 (0xC0000U)
+#define BCH_CTRL_M2M_LAYOUT_SHIFT                (18U)
+/*! M2M_LAYOUT - M2M_LAYOUT
+ */
+#define BCH_CTRL_M2M_LAYOUT(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK)
+#define BCH_CTRL_RSVD4_MASK                      (0x300000U)
+#define BCH_CTRL_RSVD4_SHIFT                     (20U)
+/*! RSVD4 - This field is reserved.
+ */
+#define BCH_CTRL_RSVD4(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK)
+#define BCH_CTRL_DEBUGSYNDROME_MASK              (0x400000U)
+#define BCH_CTRL_DEBUGSYNDROME_SHIFT             (22U)
+/*! DEBUGSYNDROME - DEBUGSYNDROME
+ */
+#define BCH_CTRL_DEBUGSYNDROME(x)                (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK)
+#define BCH_CTRL_RSVD5_MASK                      (0x3F800000U)
+#define BCH_CTRL_RSVD5_SHIFT                     (23U)
+/*! RSVD5 - This field is reserved.
+ */
+#define BCH_CTRL_RSVD5(x)                        (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK)
+#define BCH_CTRL_CLKGATE_MASK                    (0x40000000U)
+#define BCH_CTRL_CLKGATE_SHIFT                   (30U)
+/*! CLKGATE - CLKGATE
+ *  0b0..Allow BCH to operate normally.
+ *  0b1..Do not clock BCH gates in order to minimize power consumption.
+ */
+#define BCH_CTRL_CLKGATE(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK)
+#define BCH_CTRL_SFTRST_MASK                     (0x80000000U)
+#define BCH_CTRL_SFTRST_SHIFT                    (31U)
+/*! SFTRST - SFTRST
+ *  0b0..Allow BCH to operate normally.
+ *  0b1..Hold BCH in reset.
+ */
+#define BCH_CTRL_SFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK)
+/*! @} */
+
+/*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */
+/*! @{ */
+#define BCH_STATUS0_RSVD0_MASK                   (0x3U)
+#define BCH_STATUS0_RSVD0_SHIFT                  (0U)
+/*! RSVD0 - This field is reserved.
+ */
+#define BCH_STATUS0_RSVD0(x)                     (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK)
+#define BCH_STATUS0_UNCORRECTABLE_MASK           (0x4U)
+#define BCH_STATUS0_UNCORRECTABLE_SHIFT          (2U)
+/*! UNCORRECTABLE - UNCORRECTABLE
+ */
+#define BCH_STATUS0_UNCORRECTABLE(x)             (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK)
+#define BCH_STATUS0_CORRECTED_MASK               (0x8U)
+#define BCH_STATUS0_CORRECTED_SHIFT              (3U)
+/*! CORRECTED - CORRECTED
+ */
+#define BCH_STATUS0_CORRECTED(x)                 (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK)
+#define BCH_STATUS0_ALLONES_MASK                 (0x10U)
+#define BCH_STATUS0_ALLONES_SHIFT                (4U)
+/*! ALLONES - ALLONES
+ */
+#define BCH_STATUS0_ALLONES(x)                   (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK)
+#define BCH_STATUS0_RSVD1_MASK                   (0xE0U)
+#define BCH_STATUS0_RSVD1_SHIFT                  (5U)
+/*! RSVD1 - This field is reserved.
+ */
+#define BCH_STATUS0_RSVD1(x)                     (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK)
+#define BCH_STATUS0_STATUS_BLK0_MASK             (0xFF00U)
+#define BCH_STATUS0_STATUS_BLK0_SHIFT            (8U)
+/*! STATUS_BLK0 - STATUS_BLK0
+ *  0b00000000..No errors found on block.
+ *  0b00000001..One error found on block.
+ *  0b00000010..One errors found on block.
+ *  0b00000011..One errors found on block.
+ *  0b00000100..One errors found on block.
+ *  0b11111110..Block exhibited uncorrectable errors.
+ *  0b11111111..Page is erased.
+ */
+#define BCH_STATUS0_STATUS_BLK0(x)               (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK)
+#define BCH_STATUS0_COMPLETED_CE_MASK            (0xF0000U)
+#define BCH_STATUS0_COMPLETED_CE_SHIFT           (16U)
+/*! COMPLETED_CE - COMPLETED_CE
+ */
+#define BCH_STATUS0_COMPLETED_CE(x)              (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK)
+#define BCH_STATUS0_HANDLE_MASK                  (0xFFF00000U)
+#define BCH_STATUS0_HANDLE_SHIFT                 (20U)
+/*! HANDLE - HANDLE
+ */
+#define BCH_STATUS0_HANDLE(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK)
+/*! @} */
+
+/*! @name MODE - Hardware ECC Accelerator Mode Register */
+/*! @{ */
+#define BCH_MODE_ERASE_THRESHOLD_MASK            (0xFFU)
+#define BCH_MODE_ERASE_THRESHOLD_SHIFT           (0U)
+/*! ERASE_THRESHOLD - ERASE_THRESHOLD
+ */
+#define BCH_MODE_ERASE_THRESHOLD(x)              (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK)
+#define BCH_MODE_RSVD_MASK                       (0xFFFFFF00U)
+#define BCH_MODE_RSVD_SHIFT                      (8U)
+/*! RSVD - This field is reserved.
+ */
+#define BCH_MODE_RSVD(x)                         (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK)
+/*! @} */
+
+/*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */
+/*! @{ */
+#define BCH_ENCODEPTR_ADDR_MASK                  (0xFFFFFFFFU)
+#define BCH_ENCODEPTR_ADDR_SHIFT                 (0U)
+/*! ADDR - ADDR
+ */
+#define BCH_ENCODEPTR_ADDR(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK)
+/*! @} */
+
+/*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */
+/*! @{ */
+#define BCH_DATAPTR_ADDR_MASK                    (0xFFFFFFFFU)
+#define BCH_DATAPTR_ADDR_SHIFT                   (0U)
+/*! ADDR - ADDR
+ */
+#define BCH_DATAPTR_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK)
+/*! @} */
+
+/*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */
+/*! @{ */
+#define BCH_METAPTR_ADDR_MASK                    (0xFFFFFFFFU)
+#define BCH_METAPTR_ADDR_SHIFT                   (0U)
+/*! ADDR - ADDR
+ */
+#define BCH_METAPTR_ADDR(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK)
+/*! @} */
+
+/*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */
+/*! @{ */
+#define BCH_LAYOUTSELECT_CS0_SELECT_MASK         (0x3U)
+#define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT        (0U)
+/*! CS0_SELECT - CS0_SELECT
+ */
+#define BCH_LAYOUTSELECT_CS0_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS1_SELECT_MASK         (0xCU)
+#define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT        (2U)
+/*! CS1_SELECT - CS1_SELECT
+ */
+#define BCH_LAYOUTSELECT_CS1_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS2_SELECT_MASK         (0x30U)
+#define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT        (4U)
+/*! CS2_SELECT - CS2_SELECT
+ */
+#define BCH_LAYOUTSELECT_CS2_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS3_SELECT_MASK         (0xC0U)
+#define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT        (6U)
+/*! CS3_SELECT - CS3_SELECT
+ */
+#define BCH_LAYOUTSELECT_CS3_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS4_SELECT_MASK         (0x300U)
+#define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT        (8U)
+/*! CS4_SELECT - CS4_SELECT
+ */
+#define BCH_LAYOUTSELECT_CS4_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS5_SELECT_MASK         (0xC00U)
+#define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT        (10U)
+/*! CS5_SELECT - CS5_SELECT
+ */
+#define BCH_LAYOUTSELECT_CS5_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS6_SELECT_MASK         (0x3000U)
+#define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT        (12U)
+/*! CS6_SELECT - CS6_SELECT
+ */
+#define BCH_LAYOUTSELECT_CS6_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS7_SELECT_MASK         (0xC000U)
+#define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT        (14U)
+/*! CS7_SELECT - CS7_SELECT
+ */
+#define BCH_LAYOUTSELECT_CS7_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS8_SELECT_MASK         (0x30000U)
+#define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT        (16U)
+/*! CS8_SELECT - CS8_SELECT
+ */
+#define BCH_LAYOUTSELECT_CS8_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS9_SELECT_MASK         (0xC0000U)
+#define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT        (18U)
+/*! CS9_SELECT - CS9_SELECT
+ */
+#define BCH_LAYOUTSELECT_CS9_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS10_SELECT_MASK        (0x300000U)
+#define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT       (20U)
+/*! CS10_SELECT - CS10_SELECT
+ */
+#define BCH_LAYOUTSELECT_CS10_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS11_SELECT_MASK        (0xC00000U)
+#define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT       (22U)
+/*! CS11_SELECT - CS11_SELECT
+ */
+#define BCH_LAYOUTSELECT_CS11_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS12_SELECT_MASK        (0x3000000U)
+#define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT       (24U)
+/*! CS12_SELECT - CS12_SELECT
+ */
+#define BCH_LAYOUTSELECT_CS12_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS13_SELECT_MASK        (0xC000000U)
+#define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT       (26U)
+/*! CS13_SELECT - CS13_SELECT
+ */
+#define BCH_LAYOUTSELECT_CS13_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS14_SELECT_MASK        (0x30000000U)
+#define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT       (28U)
+/*! CS14_SELECT - CS14_SELECT
+ */
+#define BCH_LAYOUTSELECT_CS14_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK)
+#define BCH_LAYOUTSELECT_CS15_SELECT_MASK        (0xC0000000U)
+#define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT       (30U)
+/*! CS15_SELECT - CS15_SELECT
+ */
+#define BCH_LAYOUTSELECT_CS15_SELECT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK)
+/*! @} */
+
+/*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */
+/*! @{ */
+#define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK        (0x3FFU)
+#define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT       (0U)
+/*! DATA0_SIZE - DATA0_SIZE
+ */
+#define BCH_FLASH0LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK)
+#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK     (0x400U)
+#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT    (10U)
+/*! GF13_0_GF14_1 - GF13_0_GF14_1
+ */
+#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK)
+#define BCH_FLASH0LAYOUT0_ECC0_MASK              (0xF800U)
+#define BCH_FLASH0LAYOUT0_ECC0_SHIFT             (11U)
+/*! ECC0 - ECC0
+ *  0b00000..No ECC to be performed
+ *  0b00001..ECC 2 to be performed
+ *  0b00010..ECC 4 to be performed
+ *  0b11110..ECC 60 to be performed
+ *  0b11111..ECC 62 to be performed
+ */
+#define BCH_FLASH0LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK)
+#define BCH_FLASH0LAYOUT0_META_SIZE_MASK         (0xFF0000U)
+#define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT        (16U)
+/*! META_SIZE - META_SIZE
+ */
+#define BCH_FLASH0LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK)
+#define BCH_FLASH0LAYOUT0_NBLOCKS_MASK           (0xFF000000U)
+#define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT          (24U)
+/*! NBLOCKS - NBLOCKS
+ */
+#define BCH_FLASH0LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK)
+/*! @} */
+
+/*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */
+/*! @{ */
+#define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK        (0x3FFU)
+#define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT       (0U)
+/*! DATAN_SIZE - DATAN_SIZE
+ */
+#define BCH_FLASH0LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK)
+#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK     (0x400U)
+#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT    (10U)
+/*! GF13_0_GF14_1 - GF13_0_GF14_1
+ */
+#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK)
+#define BCH_FLASH0LAYOUT1_ECCN_MASK              (0xF800U)
+#define BCH_FLASH0LAYOUT1_ECCN_SHIFT             (11U)
+/*! ECCN - ECCN
+ *  0b00000..No ECC to be performed
+ *  0b00001..ECC 2 to be performed
+ *  0b00010..ECC 4 to be performed
+ *  0b11110..ECC 60 to be performed
+ *  0b11111..ECC 62 to be performed
+ */
+#define BCH_FLASH0LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK)
+#define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK         (0xFFFF0000U)
+#define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT        (16U)
+/*! PAGE_SIZE - PAGE_SIZE
+ */
+#define BCH_FLASH0LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK)
+/*! @} */
+
+/*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */
+/*! @{ */
+#define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK        (0x3FFU)
+#define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT       (0U)
+/*! DATA0_SIZE - DATA0_SIZE
+ */
+#define BCH_FLASH1LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK)
+#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK     (0x400U)
+#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT    (10U)
+/*! GF13_0_GF14_1 - GF13_0_GF14_1
+ */
+#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK)
+#define BCH_FLASH1LAYOUT0_ECC0_MASK              (0xF800U)
+#define BCH_FLASH1LAYOUT0_ECC0_SHIFT             (11U)
+/*! ECC0 - ECC0
+ *  0b00000..No ECC to be performed
+ *  0b00001..ECC 2 to be performed
+ *  0b00010..ECC 4 to be performed
+ *  0b11110..ECC 60 to be performed
+ *  0b11111..ECC 62 to be performed
+ */
+#define BCH_FLASH1LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK)
+#define BCH_FLASH1LAYOUT0_META_SIZE_MASK         (0xFF0000U)
+#define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT        (16U)
+/*! META_SIZE - META_SIZE
+ */
+#define BCH_FLASH1LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK)
+#define BCH_FLASH1LAYOUT0_NBLOCKS_MASK           (0xFF000000U)
+#define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT          (24U)
+/*! NBLOCKS - NBLOCKS
+ */
+#define BCH_FLASH1LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK)
+/*! @} */
+
+/*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */
+/*! @{ */
+#define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK        (0x3FFU)
+#define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT       (0U)
+/*! DATAN_SIZE - DATAN_SIZE
+ */
+#define BCH_FLASH1LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK)
+#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK     (0x400U)
+#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT    (10U)
+/*! GF13_0_GF14_1 - GF13_0_GF14_1
+ */
+#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK)
+#define BCH_FLASH1LAYOUT1_ECCN_MASK              (0xF800U)
+#define BCH_FLASH1LAYOUT1_ECCN_SHIFT             (11U)
+/*! ECCN - ECCN
+ *  0b00000..No ECC to be performed
+ *  0b00001..ECC 2 to be performed
+ *  0b00010..ECC 4 to be performed
+ *  0b11110..ECC 60 to be performed
+ *  0b11111..ECC 62 to be performed
+ */
+#define BCH_FLASH1LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK)
+#define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK         (0xFFFF0000U)
+#define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT        (16U)
+/*! PAGE_SIZE - PAGE_SIZE
+ */
+#define BCH_FLASH1LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK)
+/*! @} */
+
+/*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */
+/*! @{ */
+#define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK        (0x3FFU)
+#define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT       (0U)
+/*! DATA0_SIZE - DATA0_SIZE
+ */
+#define BCH_FLASH2LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK)
+#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK     (0x400U)
+#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT    (10U)
+/*! GF13_0_GF14_1 - GF13_0_GF14_1
+ */
+#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK)
+#define BCH_FLASH2LAYOUT0_ECC0_MASK              (0xF800U)
+#define BCH_FLASH2LAYOUT0_ECC0_SHIFT             (11U)
+/*! ECC0 - ECC0
+ *  0b00000..No ECC to be performed
+ *  0b00001..ECC 2 to be performed
+ *  0b00010..ECC 4 to be performed
+ *  0b11110..ECC 60 to be performed
+ *  0b11111..ECC 62 to be performed
+ */
+#define BCH_FLASH2LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK)
+#define BCH_FLASH2LAYOUT0_META_SIZE_MASK         (0xFF0000U)
+#define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT        (16U)
+/*! META_SIZE - META_SIZE
+ */
+#define BCH_FLASH2LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK)
+#define BCH_FLASH2LAYOUT0_NBLOCKS_MASK           (0xFF000000U)
+#define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT          (24U)
+/*! NBLOCKS - NBLOCKS
+ */
+#define BCH_FLASH2LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK)
+/*! @} */
+
+/*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */
+/*! @{ */
+#define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK        (0x3FFU)
+#define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT       (0U)
+/*! DATAN_SIZE - DATAN_SIZE
+ */
+#define BCH_FLASH2LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK)
+#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK     (0x400U)
+#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT    (10U)
+/*! GF13_0_GF14_1 - GF13_0_GF14_1
+ */
+#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK)
+#define BCH_FLASH2LAYOUT1_ECCN_MASK              (0xF800U)
+#define BCH_FLASH2LAYOUT1_ECCN_SHIFT             (11U)
+/*! ECCN - ECCN
+ *  0b00000..No ECC to be performed
+ *  0b00001..ECC 2 to be performed
+ *  0b00010..ECC 4 to be performed
+ *  0b11110..ECC 60 to be performed
+ *  0b11111..ECC 62 to be performed
+ */
+#define BCH_FLASH2LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK)
+#define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK         (0xFFFF0000U)
+#define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT        (16U)
+/*! PAGE_SIZE - PAGE_SIZE
+ */
+#define BCH_FLASH2LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK)
+/*! @} */
+
+/*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */
+/*! @{ */
+#define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK        (0x3FFU)
+#define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT       (0U)
+/*! DATA0_SIZE - DATA0_SIZE
+ */
+#define BCH_FLASH3LAYOUT0_DATA0_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK)
+#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK     (0x400U)
+#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT    (10U)
+/*! GF13_0_GF14_1 - GF13_0_GF14_1
+ */
+#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK)
+#define BCH_FLASH3LAYOUT0_ECC0_MASK              (0xF800U)
+#define BCH_FLASH3LAYOUT0_ECC0_SHIFT             (11U)
+/*! ECC0 - ECC0
+ *  0b00000..No ECC to be performed
+ *  0b00001..ECC 2 to be performed
+ *  0b00010..ECC 4 to be performed
+ *  0b11110..ECC 60 to be performed
+ *  0b11111..ECC 62 to be performed
+ */
+#define BCH_FLASH3LAYOUT0_ECC0(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK)
+#define BCH_FLASH3LAYOUT0_META_SIZE_MASK         (0xFF0000U)
+#define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT        (16U)
+/*! META_SIZE - META_SIZE
+ */
+#define BCH_FLASH3LAYOUT0_META_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK)
+#define BCH_FLASH3LAYOUT0_NBLOCKS_MASK           (0xFF000000U)
+#define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT          (24U)
+/*! NBLOCKS - NBLOCKS
+ */
+#define BCH_FLASH3LAYOUT0_NBLOCKS(x)             (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK)
+/*! @} */
+
+/*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */
+/*! @{ */
+#define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK        (0x3FFU)
+#define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT       (0U)
+/*! DATAN_SIZE - DATAN_SIZE
+ */
+#define BCH_FLASH3LAYOUT1_DATAN_SIZE(x)          (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK)
+#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK     (0x400U)
+#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT    (10U)
+/*! GF13_0_GF14_1 - GF13_0_GF14_1
+ */
+#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x)       (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK)
+#define BCH_FLASH3LAYOUT1_ECCN_MASK              (0xF800U)
+#define BCH_FLASH3LAYOUT1_ECCN_SHIFT             (11U)
+/*! ECCN - ECCN
+ *  0b00000..No ECC to be performed
+ *  0b00001..ECC 2 to be performed
+ *  0b00010..ECC 4 to be performed
+ *  0b11110..ECC 60 to be performed
+ *  0b11111..ECC 62 to be performed
+ */
+#define BCH_FLASH3LAYOUT1_ECCN(x)                (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK)
+#define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK         (0xFFFF0000U)
+#define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT        (16U)
+/*! PAGE_SIZE - PAGE_SIZE
+ */
+#define BCH_FLASH3LAYOUT1_PAGE_SIZE(x)           (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK)
+/*! @} */
+
+/*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */
+/*! @{ */
+#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK         (0x3FU)
+#define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT        (0U)
+/*! DEBUG_REG_SELECT - DEBUG_REG_SELECT
+ */
+#define BCH_DEBUG0_DEBUG_REG_SELECT(x)           (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK)
+#define BCH_DEBUG0_RSVD0_MASK                    (0xC0U)
+#define BCH_DEBUG0_RSVD0_SHIFT                   (6U)
+/*! RSVD0 - This field is reserved.
+ */
+#define BCH_DEBUG0_RSVD0(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK)
+#define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK       (0x100U)
+#define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT      (8U)
+/*! BM_KES_TEST_BYPASS - BM_KES_TEST_BYPASS
+ *  0b0..Bus master address generator for SYND_GEN writes operates normally.
+ *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
+ */
+#define BCH_DEBUG0_BM_KES_TEST_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK)
+#define BCH_DEBUG0_KES_DEBUG_STALL_MASK          (0x200U)
+#define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT         (9U)
+/*! KES_DEBUG_STALL - KES_DEBUG_STALL
+ *  0b0..KES FSM proceeds to next block supplied by bus master.
+ *  0b1..KES FSM waits after current equations are solved and the search engine is started.
+ */
+#define BCH_DEBUG0_KES_DEBUG_STALL(x)            (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK)
+#define BCH_DEBUG0_KES_DEBUG_STEP_MASK           (0x400U)
+#define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT          (10U)
+/*! KES_DEBUG_STEP - KES_DEBUG_STEP
+ */
+#define BCH_DEBUG0_KES_DEBUG_STEP(x)             (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK)
+#define BCH_DEBUG0_KES_STANDALONE_MASK           (0x800U)
+#define BCH_DEBUG0_KES_STANDALONE_SHIFT          (11U)
+/*! KES_STANDALONE - KES_STANDALONE
+ *  0b0..Bus master address generator for SYND_GEN writes operates normally.
+ *  0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
+ */
+#define BCH_DEBUG0_KES_STANDALONE(x)             (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK)
+#define BCH_DEBUG0_KES_DEBUG_KICK_MASK           (0x1000U)
+#define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT          (12U)
+/*! KES_DEBUG_KICK - KES_DEBUG_KICK
+ */
+#define BCH_DEBUG0_KES_DEBUG_KICK(x)             (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK)
+#define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK         (0x2000U)
+#define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT        (13U)
+/*! KES_DEBUG_MODE4K - KES_DEBUG_MODE4K
+ *  0b1..Mode is set for 4K NAND pages.
+ *  0b1..Mode is set for 2K NAND pages.
+ */
+#define BCH_DEBUG0_KES_DEBUG_MODE4K(x)           (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK)
+#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK   (0x4000U)
+#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT  (14U)
+/*! KES_DEBUG_PAYLOAD_FLAG - KES_DEBUG_PAYLOAD_FLAG
+ *  0b1..Payload is set for 512 bytes data block.
+ *  0b1..Payload is set for 65 or 19 bytes auxiliary block.
+ */
+#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x)     (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK)
+#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK     (0x8000U)
+#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT    (15U)
+/*! KES_DEBUG_SHIFT_SYND - KES_DEBUG_SHIFT_SYND
+ */
+#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x)       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK)
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
+/*! KES_DEBUG_SYNDROME_SYMBOL - KES_DEBUG_SYNDROME_SYMBOL
+ *  0b000000000..Bus master address generator for SYND_GEN writes operates normally.
+ *  0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
+ */
+#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x)  (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK)
+#define BCH_DEBUG0_RSVD1_MASK                    (0xFE000000U)
+#define BCH_DEBUG0_RSVD1_SHIFT                   (25U)
+/*! RSVD1 - This field is reserved.
+ */
+#define BCH_DEBUG0_RSVD1(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK)
+/*! @} */
+
+/*! @name DBGKESREAD - KES Debug Read Register */
+/*! @{ */
+#define BCH_DBGKESREAD_VALUES_MASK               (0xFFFFFFFFU)
+#define BCH_DBGKESREAD_VALUES_SHIFT              (0U)
+/*! VALUES - VALUES
+ */
+#define BCH_DBGKESREAD_VALUES(x)                 (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK)
+/*! @} */
+
+/*! @name DBGCSFEREAD - Chien Search Debug Read Register */
+/*! @{ */
+#define BCH_DBGCSFEREAD_VALUES_MASK              (0xFFFFFFFFU)
+#define BCH_DBGCSFEREAD_VALUES_SHIFT             (0U)
+/*! VALUES - VALUES
+ */
+#define BCH_DBGCSFEREAD_VALUES(x)                (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK)
+/*! @} */
+
+/*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */
+/*! @{ */
+#define BCH_DBGSYNDGENREAD_VALUES_MASK           (0xFFFFFFFFU)
+#define BCH_DBGSYNDGENREAD_VALUES_SHIFT          (0U)
+/*! VALUES - VALUES
+ */
+#define BCH_DBGSYNDGENREAD_VALUES(x)             (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK)
+/*! @} */
+
+/*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */
+/*! @{ */
+#define BCH_DBGAHBMREAD_VALUES_MASK              (0xFFFFFFFFU)
+#define BCH_DBGAHBMREAD_VALUES_SHIFT             (0U)
+/*! VALUES - VALUES
+ */
+#define BCH_DBGAHBMREAD_VALUES(x)                (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK)
+/*! @} */
+
+/*! @name BLOCKNAME - Block Name Register */
+/*! @{ */
+#define BCH_BLOCKNAME_NAME_MASK                  (0xFFFFFFFFU)
+#define BCH_BLOCKNAME_NAME_SHIFT                 (0U)
+/*! NAME - NAME
+ */
+#define BCH_BLOCKNAME_NAME(x)                    (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK)
+/*! @} */
+
+/*! @name VERSION - BCH Version Register */
+/*! @{ */
+#define BCH_VERSION_STEP_MASK                    (0xFFFFU)
+#define BCH_VERSION_STEP_SHIFT                   (0U)
+/*! STEP - STEP
+ */
+#define BCH_VERSION_STEP(x)                      (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK)
+#define BCH_VERSION_MINOR_MASK                   (0xFF0000U)
+#define BCH_VERSION_MINOR_SHIFT                  (16U)
+/*! MINOR - MINOR
+ */
+#define BCH_VERSION_MINOR(x)                     (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK)
+#define BCH_VERSION_MAJOR_MASK                   (0xFF000000U)
+#define BCH_VERSION_MAJOR_SHIFT                  (24U)
+/*! MAJOR - MAJOR
+ */
+#define BCH_VERSION_MAJOR(x)                     (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK)
+/*! @} */
+
+/*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */
+/*! @{ */
+#define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK        (0x1FFU)
+#define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT       (0U)
+/*! ERASED_ZERO_COUNT - ERASED_ZERO_COUNT
+ */
+#define BCH_DEBUG1_ERASED_ZERO_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK)
+#define BCH_DEBUG1_RSVD_MASK                     (0x7FFFFE00U)
+#define BCH_DEBUG1_RSVD_SHIFT                    (9U)
+/*! RSVD - This field is reserved.
+ */
+#define BCH_DEBUG1_RSVD(x)                       (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK)
+#define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK       (0x80000000U)
+#define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT      (31U)
+/*! DEBUG1_PREERASECHK - DEBUG1_PREERASECHK
+ *  0b0..Turn off pre-erase check
+ *  0b1..Turn on pre-erase check
+ */
+#define BCH_DEBUG1_DEBUG1_PREERASECHK(x)         (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group BCH_Register_Masks */
+
+
+/* BCH - Peripheral instance base addresses */
+/** Peripheral CONNECTIVITY__BCH base address */
+#define CONNECTIVITY__BCH_BASE                   (0x5B814000u)
+/** Peripheral CONNECTIVITY__BCH base pointer */
+#define CONNECTIVITY__BCH                        ((BCH_Type *)CONNECTIVITY__BCH_BASE)
+/** Array initializer of BCH peripheral base addresses */
+#define BCH_BASE_ADDRS                           { CONNECTIVITY__BCH_BASE }
+/** Array initializer of BCH peripheral base pointers */
+#define BCH_BASE_PTRS                            { CONNECTIVITY__BCH }
+
+/*!
+ * @}
+ */ /* end of group BCH_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration register, offset: 0x0 */
+  __IO uint32_t CTRL1;                             /**< Control 1 register, offset: 0x4 */
+  __IO uint32_t TIMER;                             /**< Free Running Timer, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask register, offset: 0x10 */
+  __IO uint32_t RX14MASK;                          /**< Rx 14 Mask register, offset: 0x14 */
+  __IO uint32_t RX15MASK;                          /**< Rx 15 Mask register, offset: 0x18 */
+  __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
+  __IO uint32_t ESR1;                              /**< Error and Status 1 register, offset: 0x20 */
+  __IO uint32_t IMASK2;                            /**< Interrupt Masks 2 register, offset: 0x24 */
+  __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 register, offset: 0x28 */
+  __IO uint32_t IFLAG2;                            /**< Interrupt Flags 2 register, offset: 0x2C */
+  __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 register, offset: 0x30 */
+  __IO uint32_t CTRL2;                             /**< Control 2 register, offset: 0x34 */
+  __I  uint32_t ESR2;                              /**< Error and Status 2 register, offset: 0x38 */
+       uint8_t RESERVED_1[8];
+  __I  uint32_t CRCR;                              /**< CRC register, offset: 0x44 */
+  __IO uint32_t RXFGMASK;                          /**< Rx FIFO Global Mask register, offset: 0x48 */
+  __I  uint32_t RXFIR;                             /**< Rx FIFO Information register, offset: 0x4C */
+  __IO uint32_t CBT;                               /**< CAN Bit Timing register, offset: 0x50 */
+       uint8_t RESERVED_2[4];
+  __I  uint32_t DBG1;                              /**< Debug 1 register, offset: 0x58 */
+  __I  uint32_t DBG2;                              /**< Debug 2 register, offset: 0x5C */
+       uint8_t RESERVED_3[32];
+  struct {                                         /* offset: 0x80, array step: 0x10 */
+    __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
+    __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
+    __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
+    __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
+  } MB[64];
+       uint8_t RESERVED_4[1024];
+  __IO uint32_t RXIMR[64];                         /**< Rx Individual Mask registers, array offset: 0x880, array step: 0x4 */
+       uint8_t RESERVED_5[640];
+  __IO uint32_t FDCTRL;                            /**< CAN FD Control register, offset: 0xC00 */
+  __IO uint32_t FDCBT;                             /**< CAN FD Bit Timing register, offset: 0xC04 */
+  __I  uint32_t FDCRC;                             /**< CAN FD CRC register, offset: 0xC08 */
+} CAN_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CAN Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/*! @name MCR - Module Configuration register */
+/*! @{ */
+#define CAN_MCR_MAXMB_MASK                       (0x7FU)
+#define CAN_MCR_MAXMB_SHIFT                      (0U)
+/*! MAXMB - Number Of The Last Message Buffer
+ */
+#define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
+#define CAN_MCR_IDAM_MASK                        (0x300U)
+#define CAN_MCR_IDAM_SHIFT                       (8U)
+/*! IDAM - ID Acceptance Mode
+ *  0b00..Format A: One full ID (standard and extended) per ID filter table element.
+ *  0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element.
+ *  0b10..Format C: Four partial 8-bit standard IDs per ID filter table element.
+ *  0b11..Format D: All frames rejected.
+ */
+#define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
+#define CAN_MCR_FDEN_MASK                        (0x800U)
+#define CAN_MCR_FDEN_SHIFT                       (11U)
+/*! FDEN - CAN FD operation enable
+ *  0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats.
+ *  0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.
+ */
+#define CAN_MCR_FDEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
+#define CAN_MCR_AEN_MASK                         (0x1000U)
+#define CAN_MCR_AEN_SHIFT                        (12U)
+/*! AEN - Abort Enable
+ *  0b0..Abort disabled.
+ *  0b1..Abort enabled.
+ */
+#define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
+#define CAN_MCR_LPRIOEN_MASK                     (0x2000U)
+#define CAN_MCR_LPRIOEN_SHIFT                    (13U)
+/*! LPRIOEN - Local Priority Enable
+ *  0b0..Local Priority disabled.
+ *  0b1..Local Priority enabled.
+ */
+#define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
+#define CAN_MCR_DMA_MASK                         (0x8000U)
+#define CAN_MCR_DMA_SHIFT                        (15U)
+/*! DMA - DMA Enable
+ *  0b0..DMA feature for RX FIFO disabled.
+ *  0b1..DMA feature for RX FIFO enabled.
+ */
+#define CAN_MCR_DMA(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
+#define CAN_MCR_IRMQ_MASK                        (0x10000U)
+#define CAN_MCR_IRMQ_SHIFT                       (16U)
+/*! IRMQ - Individual Rx Masking And Queue Enable
+ *  0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy
+ *       applications, the reading of C/S word locks the MB even if it is EMPTY.
+ *  0b1..Individual Rx masking and queue feature are enabled.
+ */
+#define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
+#define CAN_MCR_SRXDIS_MASK                      (0x20000U)
+#define CAN_MCR_SRXDIS_SHIFT                     (17U)
+/*! SRXDIS - Self Reception Disable
+ *  0b0..Self-reception enabled.
+ *  0b1..Self-reception disabled.
+ */
+#define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
+#define CAN_MCR_DOZE_MASK                        (0x40000U)
+#define CAN_MCR_DOZE_SHIFT                       (18U)
+/*! DOZE - Doze Mode Enable
+ *  0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested.
+ *  0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.
+ */
+#define CAN_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
+#define CAN_MCR_WAKSRC_MASK                      (0x80000U)
+#define CAN_MCR_WAKSRC_SHIFT                     (19U)
+/*! WAKSRC - Wake Up Source
+ *  0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.
+ *  0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.
+ */
+#define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
+#define CAN_MCR_LPMACK_MASK                      (0x100000U)
+#define CAN_MCR_LPMACK_SHIFT                     (20U)
+/*! LPMACK - Low-Power Mode Acknowledge
+ *  0b0..FlexCAN is not in a low-power mode.
+ *  0b1..FlexCAN is in a low-power mode.
+ */
+#define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
+#define CAN_MCR_WRNEN_MASK                       (0x200000U)
+#define CAN_MCR_WRNEN_SHIFT                      (21U)
+/*! WRNEN - Warning Interrupt Enable
+ *  0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
+ *  0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.
+ */
+#define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
+#define CAN_MCR_SLFWAK_MASK                      (0x400000U)
+#define CAN_MCR_SLFWAK_SHIFT                     (22U)
+/*! SLFWAK - Self Wake Up
+ *  0b0..FlexCAN Self Wake Up feature is disabled.
+ *  0b1..FlexCAN Self Wake Up feature is enabled.
+ */
+#define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
+#define CAN_MCR_FRZACK_MASK                      (0x1000000U)
+#define CAN_MCR_FRZACK_SHIFT                     (24U)
+/*! FRZACK - Freeze Mode Acknowledge
+ *  0b0..FlexCAN not in Freeze mode, prescaler running.
+ *  0b1..FlexCAN in Freeze mode, prescaler stopped.
+ */
+#define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
+#define CAN_MCR_SOFTRST_MASK                     (0x2000000U)
+#define CAN_MCR_SOFTRST_SHIFT                    (25U)
+/*! SOFTRST - Soft Reset
+ *  0b0..No reset request.
+ *  0b1..Resets the registers affected by soft reset.
+ */
+#define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
+#define CAN_MCR_WAKMSK_MASK                      (0x4000000U)
+#define CAN_MCR_WAKMSK_SHIFT                     (26U)
+/*! WAKMSK - Wake Up Interrupt Mask
+ *  0b0..Wake Up interrupt is disabled.
+ *  0b1..Wake Up interrupt is enabled.
+ */
+#define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
+#define CAN_MCR_NOTRDY_MASK                      (0x8000000U)
+#define CAN_MCR_NOTRDY_SHIFT                     (27U)
+/*! NOTRDY - FlexCAN Not Ready
+ *  0b0..FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode.
+ *  0b1..FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode.
+ */
+#define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
+#define CAN_MCR_HALT_MASK                        (0x10000000U)
+#define CAN_MCR_HALT_SHIFT                       (28U)
+/*! HALT - Halt FlexCAN
+ *  0b0..No Freeze mode request.
+ *  0b1..Enters Freeze mode if the FRZ bit is asserted.
+ */
+#define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
+#define CAN_MCR_RFEN_MASK                        (0x20000000U)
+#define CAN_MCR_RFEN_SHIFT                       (29U)
+/*! RFEN - Rx FIFO Enable
+ *  0b0..Rx FIFO not enabled.
+ *  0b1..Rx FIFO enabled.
+ */
+#define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
+#define CAN_MCR_FRZ_MASK                         (0x40000000U)
+#define CAN_MCR_FRZ_SHIFT                        (30U)
+/*! FRZ - Freeze Enable
+ *  0b0..Not enabled to enter Freeze mode.
+ *  0b1..Enabled to enter Freeze mode.
+ */
+#define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
+#define CAN_MCR_MDIS_MASK                        (0x80000000U)
+#define CAN_MCR_MDIS_SHIFT                       (31U)
+/*! MDIS - Module Disable
+ *  0b0..Enable the FlexCAN module.
+ *  0b1..Disable the FlexCAN module.
+ */
+#define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
+/*! @} */
+
+/*! @name CTRL1 - Control 1 register */
+/*! @{ */
+#define CAN_CTRL1_PROPSEG_MASK                   (0x7U)
+#define CAN_CTRL1_PROPSEG_SHIFT                  (0U)
+/*! PROPSEG - Propagation Segment
+ */
+#define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
+#define CAN_CTRL1_LOM_MASK                       (0x8U)
+#define CAN_CTRL1_LOM_SHIFT                      (3U)
+/*! LOM - Listen-Only Mode
+ *  0b0..Listen-Only mode is deactivated.
+ *  0b1..FlexCAN module operates in Listen-Only mode.
+ */
+#define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
+#define CAN_CTRL1_LBUF_MASK                      (0x10U)
+#define CAN_CTRL1_LBUF_SHIFT                     (4U)
+/*! LBUF - Lowest Buffer Transmitted First
+ *  0b0..Buffer with highest priority is transmitted first.
+ *  0b1..Lowest number buffer is transmitted first.
+ */
+#define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
+#define CAN_CTRL1_TSYN_MASK                      (0x20U)
+#define CAN_CTRL1_TSYN_SHIFT                     (5U)
+/*! TSYN - Timer Sync
+ *  0b0..Timer sync feature disabled
+ *  0b1..Timer sync feature enabled
+ */
+#define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
+#define CAN_CTRL1_BOFFREC_MASK                   (0x40U)
+#define CAN_CTRL1_BOFFREC_SHIFT                  (6U)
+/*! BOFFREC - Bus Off Recovery
+ *  0b0..Automatic recovering from Bus Off state enabled.
+ *  0b1..Automatic recovering from Bus Off state disabled.
+ */
+#define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
+#define CAN_CTRL1_SMP_MASK                       (0x80U)
+#define CAN_CTRL1_SMP_SHIFT                      (7U)
+/*! SMP - CAN Bit Sampling
+ *  0b0..Just one sample is used to determine the bit value.
+ *  0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two
+ *       preceding samples; a majority rule is used.
+ */
+#define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
+#define CAN_CTRL1_RWRNMSK_MASK                   (0x400U)
+#define CAN_CTRL1_RWRNMSK_SHIFT                  (10U)
+/*! RWRNMSK - Rx Warning Interrupt Mask
+ *  0b0..Rx Warning interrupt disabled.
+ *  0b1..Rx Warning interrupt enabled.
+ */
+#define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
+#define CAN_CTRL1_TWRNMSK_MASK                   (0x800U)
+#define CAN_CTRL1_TWRNMSK_SHIFT                  (11U)
+/*! TWRNMSK - Tx Warning Interrupt Mask
+ *  0b0..Tx Warning interrupt disabled.
+ *  0b1..Tx Warning interrupt enabled.
+ */
+#define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
+#define CAN_CTRL1_LPB_MASK                       (0x1000U)
+#define CAN_CTRL1_LPB_SHIFT                      (12U)
+/*! LPB - Loop Back Mode
+ *  0b0..Loop Back disabled.
+ *  0b1..Loop Back enabled.
+ */
+#define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
+#define CAN_CTRL1_CLKSRC_MASK                    (0x2000U)
+#define CAN_CTRL1_CLKSRC_SHIFT                   (13U)
+/*! CLKSRC - CAN Engine Clock Source
+ *  0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.
+ *  0b1..The CAN engine clock source is the peripheral clock.
+ */
+#define CAN_CTRL1_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
+#define CAN_CTRL1_ERRMSK_MASK                    (0x4000U)
+#define CAN_CTRL1_ERRMSK_SHIFT                   (14U)
+/*! ERRMSK - Error Interrupt Mask
+ *  0b0..Error interrupt disabled.
+ *  0b1..Error interrupt enabled.
+ */
+#define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
+#define CAN_CTRL1_BOFFMSK_MASK                   (0x8000U)
+#define CAN_CTRL1_BOFFMSK_SHIFT                  (15U)
+/*! BOFFMSK - Bus Off Interrupt Mask
+ *  0b0..Bus Off interrupt disabled.
+ *  0b1..Bus Off interrupt enabled.
+ */
+#define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
+#define CAN_CTRL1_PSEG2_MASK                     (0x70000U)
+#define CAN_CTRL1_PSEG2_SHIFT                    (16U)
+/*! PSEG2 - Phase Segment 2
+ */
+#define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
+#define CAN_CTRL1_PSEG1_MASK                     (0x380000U)
+#define CAN_CTRL1_PSEG1_SHIFT                    (19U)
+/*! PSEG1 - Phase Segment 1
+ */
+#define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
+#define CAN_CTRL1_RJW_MASK                       (0xC00000U)
+#define CAN_CTRL1_RJW_SHIFT                      (22U)
+/*! RJW - Resync Jump Width
+ */
+#define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
+#define CAN_CTRL1_PRESDIV_MASK                   (0xFF000000U)
+#define CAN_CTRL1_PRESDIV_SHIFT                  (24U)
+/*! PRESDIV - Prescaler Division Factor
+ */
+#define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
+/*! @} */
+
+/*! @name TIMER - Free Running Timer */
+/*! @{ */
+#define CAN_TIMER_TIMER_MASK                     (0xFFFFU)
+#define CAN_TIMER_TIMER_SHIFT                    (0U)
+/*! TIMER - Timer Value
+ */
+#define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
+/*! @} */
+
+/*! @name RXMGMASK - Rx Mailboxes Global Mask register */
+/*! @{ */
+#define CAN_RXMGMASK_MG_MASK                     (0xFFFFFFFFU)
+#define CAN_RXMGMASK_MG_SHIFT                    (0U)
+/*! MG - Rx Mailboxes Global Mask Bits
+ */
+#define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
+/*! @} */
+
+/*! @name RX14MASK - Rx 14 Mask register */
+/*! @{ */
+#define CAN_RX14MASK_RX14M_MASK                  (0xFFFFFFFFU)
+#define CAN_RX14MASK_RX14M_SHIFT                 (0U)
+/*! RX14M - Rx Buffer 14 Mask Bits
+ */
+#define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
+/*! @} */
+
+/*! @name RX15MASK - Rx 15 Mask register */
+/*! @{ */
+#define CAN_RX15MASK_RX15M_MASK                  (0xFFFFFFFFU)
+#define CAN_RX15MASK_RX15M_SHIFT                 (0U)
+/*! RX15M - Rx Buffer 15 Mask Bits
+ */
+#define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
+/*! @} */
+
+/*! @name ECR - Error Counter */
+/*! @{ */
+#define CAN_ECR_TXERRCNT_MASK                    (0xFFU)
+#define CAN_ECR_TXERRCNT_SHIFT                   (0U)
+/*! TXERRCNT - Transmit Error Counter
+ */
+#define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
+#define CAN_ECR_RXERRCNT_MASK                    (0xFF00U)
+#define CAN_ECR_RXERRCNT_SHIFT                   (8U)
+/*! RXERRCNT - Receive Error Counter
+ */
+#define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
+#define CAN_ECR_TXERRCNT_FAST_MASK               (0xFF0000U)
+#define CAN_ECR_TXERRCNT_FAST_SHIFT              (16U)
+/*! TXERRCNT_FAST - Transmit Error Counter for fast bits
+ */
+#define CAN_ECR_TXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
+#define CAN_ECR_RXERRCNT_FAST_MASK               (0xFF000000U)
+#define CAN_ECR_RXERRCNT_FAST_SHIFT              (24U)
+/*! RXERRCNT_FAST - Receive Error Counter for fast bits
+ */
+#define CAN_ECR_RXERRCNT_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
+/*! @} */
+
+/*! @name ESR1 - Error and Status 1 register */
+/*! @{ */
+#define CAN_ESR1_WAKINT_MASK                     (0x1U)
+#define CAN_ESR1_WAKINT_SHIFT                    (0U)
+/*! WAKINT - Wake-Up Interrupt
+ *  0b0..No such occurrence.
+ *  0b1..Indicates a recessive to dominant transition was received on the CAN bus.
+ */
+#define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
+#define CAN_ESR1_ERRINT_MASK                     (0x2U)
+#define CAN_ESR1_ERRINT_SHIFT                    (1U)
+/*! ERRINT - Error Interrupt
+ *  0b0..No such occurrence.
+ *  0b1..Indicates setting of any error bit in the Error and Status register.
+ */
+#define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
+#define CAN_ESR1_BOFFINT_MASK                    (0x4U)
+#define CAN_ESR1_BOFFINT_SHIFT                   (2U)
+/*! BOFFINT - Bus Off Interrupt
+ *  0b0..No such occurrence.
+ *  0b1..FlexCAN module entered Bus Off state.
+ */
+#define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
+#define CAN_ESR1_RX_MASK                         (0x8U)
+#define CAN_ESR1_RX_SHIFT                        (3U)
+/*! RX - FlexCAN In Reception
+ *  0b0..FlexCAN is not receiving a message.
+ *  0b1..FlexCAN is receiving a message.
+ */
+#define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
+#define CAN_ESR1_FLTCONF_MASK                    (0x30U)
+#define CAN_ESR1_FLTCONF_SHIFT                   (4U)
+/*! FLTCONF - Fault Confinement State
+ *  0b00..Error Active
+ *  0b01..Error Passive
+ *  0b1x..Bus Off
+ */
+#define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
+#define CAN_ESR1_TX_MASK                         (0x40U)
+#define CAN_ESR1_TX_SHIFT                        (6U)
+/*! TX - FlexCAN In Transmission
+ *  0b0..FlexCAN is not transmitting a message.
+ *  0b1..FlexCAN is transmitting a message.
+ */
+#define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
+#define CAN_ESR1_IDLE_MASK                       (0x80U)
+#define CAN_ESR1_IDLE_SHIFT                      (7U)
+/*! IDLE - IDLE
+ *  0b0..No such occurrence.
+ *  0b1..CAN bus is now IDLE.
+ */
+#define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
+#define CAN_ESR1_RXWRN_MASK                      (0x100U)
+#define CAN_ESR1_RXWRN_SHIFT                     (8U)
+/*! RXWRN - Rx Error Warning
+ *  0b0..No such occurrence.
+ *  0b1..RXERRCNT is greater than or equal to 96.
+ */
+#define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
+#define CAN_ESR1_TXWRN_MASK                      (0x200U)
+#define CAN_ESR1_TXWRN_SHIFT                     (9U)
+/*! TXWRN - TX Error Warning
+ *  0b0..No such occurrence.
+ *  0b1..TXERRCNT is greater than or equal to 96.
+ */
+#define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
+#define CAN_ESR1_STFERR_MASK                     (0x400U)
+#define CAN_ESR1_STFERR_SHIFT                    (10U)
+/*! STFERR - Stuffing Error
+ *  0b0..No such occurrence.
+ *  0b1..A stuffing error occurred since last read of this register.
+ */
+#define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
+#define CAN_ESR1_FRMERR_MASK                     (0x800U)
+#define CAN_ESR1_FRMERR_SHIFT                    (11U)
+/*! FRMERR - Form Error
+ *  0b0..No such occurrence.
+ *  0b1..A Form Error occurred since last read of this register.
+ */
+#define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
+#define CAN_ESR1_CRCERR_MASK                     (0x1000U)
+#define CAN_ESR1_CRCERR_SHIFT                    (12U)
+/*! CRCERR - Cyclic Redundancy Check Error
+ *  0b0..No such occurrence.
+ *  0b1..A CRC error occurred since last read of this register.
+ */
+#define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
+#define CAN_ESR1_ACKERR_MASK                     (0x2000U)
+#define CAN_ESR1_ACKERR_SHIFT                    (13U)
+/*! ACKERR - Acknowledge Error
+ *  0b0..No such occurrence.
+ *  0b1..An ACK error occurred since last read of this register.
+ */
+#define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
+#define CAN_ESR1_BIT0ERR_MASK                    (0x4000U)
+#define CAN_ESR1_BIT0ERR_SHIFT                   (14U)
+/*! BIT0ERR - Bit0 Error
+ *  0b0..No such occurrence.
+ *  0b1..At least one bit sent as dominant is received as recessive.
+ */
+#define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
+#define CAN_ESR1_BIT1ERR_MASK                    (0x8000U)
+#define CAN_ESR1_BIT1ERR_SHIFT                   (15U)
+/*! BIT1ERR - Bit1 Error
+ *  0b0..No such occurrence.
+ *  0b1..At least one bit sent as recessive is received as dominant.
+ */
+#define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
+#define CAN_ESR1_RWRNINT_MASK                    (0x10000U)
+#define CAN_ESR1_RWRNINT_SHIFT                   (16U)
+/*! RWRNINT - Rx Warning Interrupt Flag
+ *  0b0..No such occurrence.
+ *  0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.
+ */
+#define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
+#define CAN_ESR1_TWRNINT_MASK                    (0x20000U)
+#define CAN_ESR1_TWRNINT_SHIFT                   (17U)
+/*! TWRNINT - Tx Warning Interrupt Flag
+ *  0b0..No such occurrence.
+ *  0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.
+ */
+#define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
+#define CAN_ESR1_SYNCH_MASK                      (0x40000U)
+#define CAN_ESR1_SYNCH_SHIFT                     (18U)
+/*! SYNCH - CAN Synchronization Status
+ *  0b0..FlexCAN is not synchronized to the CAN bus.
+ *  0b1..FlexCAN is synchronized to the CAN bus.
+ */
+#define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
+#define CAN_ESR1_BOFFDONEINT_MASK                (0x80000U)
+#define CAN_ESR1_BOFFDONEINT_SHIFT               (19U)
+/*! BOFFDONEINT - Bus Off Done Interrupt
+ *  0b0..No such occurrence.
+ *  0b1..FlexCAN module has completed Bus Off process.
+ */
+#define CAN_ESR1_BOFFDONEINT(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
+#define CAN_ESR1_ERRINT_FAST_MASK                (0x100000U)
+#define CAN_ESR1_ERRINT_FAST_SHIFT               (20U)
+/*! ERRINT_FAST - Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set
+ *  0b0..No such occurrence.
+ *  0b1..Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set.
+ */
+#define CAN_ESR1_ERRINT_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
+#define CAN_ESR1_ERROVR_MASK                     (0x200000U)
+#define CAN_ESR1_ERROVR_SHIFT                    (21U)
+/*! ERROVR - Error Overrun
+ *  0b0..Overrun has not occurred.
+ *  0b1..Overrun has occurred.
+ */
+#define CAN_ESR1_ERROVR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
+#define CAN_ESR1_STFERR_FAST_MASK                (0x4000000U)
+#define CAN_ESR1_STFERR_FAST_SHIFT               (26U)
+/*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set
+ *  0b0..No such occurrence.
+ *  0b1..A stuffing error occurred since last read of this register.
+ */
+#define CAN_ESR1_STFERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
+#define CAN_ESR1_FRMERR_FAST_MASK                (0x8000000U)
+#define CAN_ESR1_FRMERR_FAST_SHIFT               (27U)
+/*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set
+ *  0b0..No such occurrence.
+ *  0b1..A form error occurred since last read of this register.
+ */
+#define CAN_ESR1_FRMERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
+#define CAN_ESR1_CRCERR_FAST_MASK                (0x10000000U)
+#define CAN_ESR1_CRCERR_FAST_SHIFT               (28U)
+/*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set
+ *  0b0..No such occurrence.
+ *  0b1..A CRC error occurred since last read of this register.
+ */
+#define CAN_ESR1_CRCERR_FAST(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
+#define CAN_ESR1_BIT0ERR_FAST_MASK               (0x40000000U)
+#define CAN_ESR1_BIT0ERR_FAST_SHIFT              (30U)
+/*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set
+ *  0b0..No such occurrence.
+ *  0b1..At least one bit sent as dominant is received as recessive.
+ */
+#define CAN_ESR1_BIT0ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
+#define CAN_ESR1_BIT1ERR_FAST_MASK               (0x80000000U)
+#define CAN_ESR1_BIT1ERR_FAST_SHIFT              (31U)
+/*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set
+ *  0b0..No such occurrence.
+ *  0b1..At least one bit sent as recessive is received as dominant.
+ */
+#define CAN_ESR1_BIT1ERR_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
+/*! @} */
+
+/*! @name IMASK2 - Interrupt Masks 2 register */
+/*! @{ */
+#define CAN_IMASK2_BUF63TO32M_MASK               (0xFFFFFFFFU)
+#define CAN_IMASK2_BUF63TO32M_SHIFT              (0U)
+/*! BUF63TO32M - Buffer MBi Mask
+ */
+#define CAN_IMASK2_BUF63TO32M(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)
+/*! @} */
+
+/*! @name IMASK1 - Interrupt Masks 1 register */
+/*! @{ */
+#define CAN_IMASK1_BUF31TO0M_MASK                (0xFFFFFFFFU)
+#define CAN_IMASK1_BUF31TO0M_SHIFT               (0U)
+/*! BUF31TO0M - Buffer MBi Mask
+ */
+#define CAN_IMASK1_BUF31TO0M(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
+/*! @} */
+
+/*! @name IFLAG2 - Interrupt Flags 2 register */
+/*! @{ */
+#define CAN_IFLAG2_BUF63TO32I_MASK               (0xFFFFFFFFU)
+#define CAN_IFLAG2_BUF63TO32I_SHIFT              (0U)
+/*! BUF63TO32I - Buffer MBi Interrupt
+ */
+#define CAN_IFLAG2_BUF63TO32I(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)
+/*! @} */
+
+/*! @name IFLAG1 - Interrupt Flags 1 register */
+/*! @{ */
+#define CAN_IFLAG1_BUF0I_MASK                    (0x1U)
+#define CAN_IFLAG1_BUF0I_SHIFT                   (0U)
+/*! BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit
+ *  0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
+ *  0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
+ */
+#define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
+#define CAN_IFLAG1_BUF4TO1I_MASK                 (0x1EU)
+#define CAN_IFLAG1_BUF4TO1I_SHIFT                (1U)
+/*! BUF4TO1I - Buffer MBi Interrupt Or Reserved
+ */
+#define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
+#define CAN_IFLAG1_BUF5I_MASK                    (0x20U)
+#define CAN_IFLAG1_BUF5I_SHIFT                   (5U)
+/*! BUF5I - Buffer MB5 Interrupt Or Frames available in Rx FIFO
+ *  0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
+ *  0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when
+ *       MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.
+ */
+#define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
+#define CAN_IFLAG1_BUF6I_MASK                    (0x40U)
+#define CAN_IFLAG1_BUF6I_SHIFT                   (6U)
+/*! BUF6I - Buffer MB6 Interrupt Or Rx FIFO Warning
+ *  0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
+ *  0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1
+ */
+#define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
+#define CAN_IFLAG1_BUF7I_MASK                    (0x80U)
+#define CAN_IFLAG1_BUF7I_SHIFT                   (7U)
+/*! BUF7I - Buffer MB7 Interrupt Or Rx FIFO Overflow
+ *  0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
+ *  0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1
+ */
+#define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
+#define CAN_IFLAG1_BUF31TO8I_MASK                (0xFFFFFF00U)
+#define CAN_IFLAG1_BUF31TO8I_SHIFT               (8U)
+/*! BUF31TO8I - Buffer MBi Interrupt
+ */
+#define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
+/*! @} */
+
+/*! @name CTRL2 - Control 2 register */
+/*! @{ */
+#define CAN_CTRL2_EDFLTDIS_MASK                  (0x800U)
+#define CAN_CTRL2_EDFLTDIS_SHIFT                 (11U)
+/*! EDFLTDIS - Edge Filter Disable
+ *  0b0..Edge filter is enabled
+ *  0b1..Edge filter is disabled
+ */
+#define CAN_CTRL2_EDFLTDIS(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)
+#define CAN_CTRL2_ISOCANFDEN_MASK                (0x1000U)
+#define CAN_CTRL2_ISOCANFDEN_SHIFT               (12U)
+/*! ISOCANFDEN - ISO CAN FD Enable
+ *  0b0..FlexCAN operates using the non-ISO CAN FD protocol.
+ *  0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1).
+ */
+#define CAN_CTRL2_ISOCANFDEN(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)
+#define CAN_CTRL2_PREXCEN_MASK                   (0x4000U)
+#define CAN_CTRL2_PREXCEN_SHIFT                  (14U)
+/*! PREXCEN - Protocol Exception Enable
+ *  0b0..Protocol exception is disabled.
+ *  0b1..Protocol exception is enabled.
+ */
+#define CAN_CTRL2_PREXCEN(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)
+#define CAN_CTRL2_EACEN_MASK                     (0x10000U)
+#define CAN_CTRL2_EACEN_SHIFT                    (16U)
+/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
+ *  0b0..Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
+ *  0b1..Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within
+ *       the incoming frame. Mask bits do apply.
+ */
+#define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
+#define CAN_CTRL2_RRS_MASK                       (0x20000U)
+#define CAN_CTRL2_RRS_SHIFT                      (17U)
+/*! RRS - Remote Request Storing
+ *  0b0..Remote response frame is generated.
+ *  0b1..Remote request frame is stored.
+ */
+#define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
+#define CAN_CTRL2_MRP_MASK                       (0x40000U)
+#define CAN_CTRL2_MRP_SHIFT                      (18U)
+/*! MRP - Mailboxes Reception Priority
+ *  0b0..Matching starts from Rx FIFO and continues on mailboxes.
+ *  0b1..Matching starts from mailboxes and continues on Rx FIFO.
+ */
+#define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
+#define CAN_CTRL2_TASD_MASK                      (0xF80000U)
+#define CAN_CTRL2_TASD_SHIFT                     (19U)
+/*! TASD - Tx Arbitration Start Delay
+ */
+#define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
+#define CAN_CTRL2_RFFN_MASK                      (0xF000000U)
+#define CAN_CTRL2_RFFN_SHIFT                     (24U)
+/*! RFFN - Number Of Rx FIFO Filters
+ */
+#define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
+#define CAN_CTRL2_BOFFDONEMSK_MASK               (0x40000000U)
+#define CAN_CTRL2_BOFFDONEMSK_SHIFT              (30U)
+/*! BOFFDONEMSK - Bus Off Done Interrupt Mask
+ *  0b0..Bus off done interrupt disabled.
+ *  0b1..Bus off done interrupt enabled.
+ */
+#define CAN_CTRL2_BOFFDONEMSK(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
+#define CAN_CTRL2_ERRMSK_FAST_MASK               (0x80000000U)
+#define CAN_CTRL2_ERRMSK_FAST_SHIFT              (31U)
+/*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames
+ *  0b0..ERRINT_FAST error interrupt disabled.
+ *  0b1..ERRINT_FAST error interrupt enabled.
+ */
+#define CAN_CTRL2_ERRMSK_FAST(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
+/*! @} */
+
+/*! @name ESR2 - Error and Status 2 register */
+/*! @{ */
+#define CAN_ESR2_IMB_MASK                        (0x2000U)
+#define CAN_ESR2_IMB_SHIFT                       (13U)
+/*! IMB - Inactive Mailbox
+ *  0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox.
+ *  0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one.
+ */
+#define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
+#define CAN_ESR2_VPS_MASK                        (0x4000U)
+#define CAN_ESR2_VPS_SHIFT                       (14U)
+/*! VPS - Valid Priority Status
+ *  0b0..Contents of IMB and LPTM are invalid.
+ *  0b1..Contents of IMB and LPTM are valid.
+ */
+#define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
+#define CAN_ESR2_LPTM_MASK                       (0x7F0000U)
+#define CAN_ESR2_LPTM_SHIFT                      (16U)
+/*! LPTM - Lowest Priority Tx Mailbox
+ */
+#define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
+/*! @} */
+
+/*! @name CRCR - CRC register */
+/*! @{ */
+#define CAN_CRCR_TXCRC_MASK                      (0x7FFFU)
+#define CAN_CRCR_TXCRC_SHIFT                     (0U)
+/*! TXCRC - Transmitted CRC value
+ */
+#define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
+#define CAN_CRCR_MBCRC_MASK                      (0x7F0000U)
+#define CAN_CRCR_MBCRC_SHIFT                     (16U)
+/*! MBCRC - CRC Mailbox
+ */
+#define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
+/*! @} */
+
+/*! @name RXFGMASK - Rx FIFO Global Mask register */
+/*! @{ */
+#define CAN_RXFGMASK_FGM_MASK                    (0xFFFFFFFFU)
+#define CAN_RXFGMASK_FGM_SHIFT                   (0U)
+/*! FGM - Rx FIFO Global Mask Bits
+ */
+#define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
+/*! @} */
+
+/*! @name RXFIR - Rx FIFO Information register */
+/*! @{ */
+#define CAN_RXFIR_IDHIT_MASK                     (0x1FFU)
+#define CAN_RXFIR_IDHIT_SHIFT                    (0U)
+/*! IDHIT - Identifier Acceptance Filter Hit Indicator
+ */
+#define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
+/*! @} */
+
+/*! @name CBT - CAN Bit Timing register */
+/*! @{ */
+#define CAN_CBT_EPSEG2_MASK                      (0x1FU)
+#define CAN_CBT_EPSEG2_SHIFT                     (0U)
+/*! EPSEG2 - Extended Phase Segment 2
+ */
+#define CAN_CBT_EPSEG2(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
+#define CAN_CBT_EPSEG1_MASK                      (0x3E0U)
+#define CAN_CBT_EPSEG1_SHIFT                     (5U)
+/*! EPSEG1 - Extended Phase Segment 1
+ */
+#define CAN_CBT_EPSEG1(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
+#define CAN_CBT_EPROPSEG_MASK                    (0xFC00U)
+#define CAN_CBT_EPROPSEG_SHIFT                   (10U)
+/*! EPROPSEG - Extended Propagation Segment
+ */
+#define CAN_CBT_EPROPSEG(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
+#define CAN_CBT_ERJW_MASK                        (0x1F0000U)
+#define CAN_CBT_ERJW_SHIFT                       (16U)
+/*! ERJW - Extended Resync Jump Width
+ */
+#define CAN_CBT_ERJW(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
+#define CAN_CBT_EPRESDIV_MASK                    (0x7FE00000U)
+#define CAN_CBT_EPRESDIV_SHIFT                   (21U)
+/*! EPRESDIV - Extended Prescaler Division Factor
+ */
+#define CAN_CBT_EPRESDIV(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
+#define CAN_CBT_BTF_MASK                         (0x80000000U)
+#define CAN_CBT_BTF_SHIFT                        (31U)
+/*! BTF - Bit Timing Format Enable
+ *  0b0..Extended bit time definitions disabled.
+ *  0b1..Extended bit time definitions enabled.
+ */
+#define CAN_CBT_BTF(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
+/*! @} */
+
+/*! @name DBG1 - Debug 1 register */
+/*! @{ */
+#define CAN_DBG1_CFSM_MASK                       (0x7FU)
+#define CAN_DBG1_CFSM_SHIFT                      (0U)
+/*! CFSM - CAN Finite State Machine
+ */
+#define CAN_DBG1_CFSM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)
+#define CAN_DBG1_CBN_MASK                        (0x3FF0000U)
+#define CAN_DBG1_CBN_SHIFT                       (16U)
+/*! CBN - CAN Bit Number
+ */
+#define CAN_DBG1_CBN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)
+/*! @} */
+
+/*! @name DBG2 - Debug 2 register */
+/*! @{ */
+#define CAN_DBG2_RMP_MASK                        (0x7FU)
+#define CAN_DBG2_RMP_SHIFT                       (0U)
+/*! RMP - Rx Matching Pointer
+ */
+#define CAN_DBG2_RMP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)
+#define CAN_DBG2_MPP_MASK                        (0x80U)
+#define CAN_DBG2_MPP_SHIFT                       (7U)
+/*! MPP - Matching Process in Progress
+ *  0b0..No matching process ongoing
+ *  0b1..Matching process is in progress.
+ */
+#define CAN_DBG2_MPP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)
+#define CAN_DBG2_TAP_MASK                        (0x7F00U)
+#define CAN_DBG2_TAP_SHIFT                       (8U)
+/*! TAP - Tx Arbitration Pointer
+ */
+#define CAN_DBG2_TAP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)
+#define CAN_DBG2_APP_MASK                        (0x8000U)
+#define CAN_DBG2_APP_SHIFT                       (15U)
+/*! APP - Arbitration Process in Progress
+ *  0b0..No arbitration process ongoing
+ *  0b1..Arbitration process is in progress.
+ */
+#define CAN_DBG2_APP(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)
+/*! @} */
+
+/*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */
+/*! @{ */
+#define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
+#define CAN_CS_TIME_STAMP_SHIFT                  (0U)
+/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
+ *    Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
+ *    appears on the CAN bus.
+ */
+#define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
+#define CAN_CS_DLC_MASK                          (0xF0000U)
+#define CAN_CS_DLC_SHIFT                         (16U)
+/*! DLC - Length of the data to be stored/transmitted.
+ */
+#define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
+#define CAN_CS_RTR_MASK                          (0x100000U)
+#define CAN_CS_RTR_SHIFT                         (20U)
+/*! RTR - Remote Transmission Request. One/zero for remote/data frame.
+ */
+#define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
+#define CAN_CS_IDE_MASK                          (0x200000U)
+#define CAN_CS_IDE_SHIFT                         (21U)
+/*! IDE - ID Extended. One/zero for extended/standard format frame.
+ */
+#define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
+#define CAN_CS_SRR_MASK                          (0x400000U)
+#define CAN_CS_SRR_SHIFT                         (22U)
+/*! SRR - Substitute Remote Request. Contains a fixed recessive bit.
+ */
+#define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
+#define CAN_CS_CODE_MASK                         (0xF000000U)
+#define CAN_CS_CODE_SHIFT                        (24U)
+/*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
+ *    the FlexCAN module itself, as part of the message buffer matching and arbitration process.
+ */
+#define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
+#define CAN_CS_ESI_MASK                          (0x20000000U)
+#define CAN_CS_ESI_SHIFT                         (29U)
+/*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive.
+ */
+#define CAN_CS_ESI(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
+#define CAN_CS_BRS_MASK                          (0x40000000U)
+#define CAN_CS_BRS_SHIFT                         (30U)
+/*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.
+ */
+#define CAN_CS_BRS(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
+#define CAN_CS_EDL_MASK                          (0x80000000U)
+#define CAN_CS_EDL_SHIFT                         (31U)
+/*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
+ *    The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
+ */
+#define CAN_CS_EDL(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
+/*! @} */
+
+/* The count of CAN_CS */
+#define CAN_CS_COUNT                             (64U)
+
+/*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */
+/*! @{ */
+#define CAN_ID_EXT_MASK                          (0x3FFFFU)
+#define CAN_ID_EXT_SHIFT                         (0U)
+/*! EXT - Contains extended (LOW word) identifier of message buffer.
+ */
+#define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
+#define CAN_ID_STD_MASK                          (0x1FFC0000U)
+#define CAN_ID_STD_SHIFT                         (18U)
+/*! STD - Contains standard/extended (HIGH word) identifier of message buffer.
+ */
+#define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
+#define CAN_ID_PRIO_MASK                         (0xE0000000U)
+#define CAN_ID_PRIO_SHIFT                        (29U)
+/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
+ *    makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
+ *    ID to define the transmission priority.
+ */
+#define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
+/*! @} */
+
+/* The count of CAN_ID */
+#define CAN_ID_COUNT                             (64U)
+
+/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
+/*! @{ */
+#define CAN_WORD0_DATA_BYTE_3_MASK               (0xFFU)
+#define CAN_WORD0_DATA_BYTE_3_SHIFT              (0U)
+/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.
+ */
+#define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
+#define CAN_WORD0_DATA_BYTE_2_MASK               (0xFF00U)
+#define CAN_WORD0_DATA_BYTE_2_SHIFT              (8U)
+/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.
+ */
+#define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
+#define CAN_WORD0_DATA_BYTE_1_MASK               (0xFF0000U)
+#define CAN_WORD0_DATA_BYTE_1_SHIFT              (16U)
+/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.
+ */
+#define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
+#define CAN_WORD0_DATA_BYTE_0_MASK               (0xFF000000U)
+#define CAN_WORD0_DATA_BYTE_0_SHIFT              (24U)
+/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.
+ */
+#define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
+/*! @} */
+
+/* The count of CAN_WORD0 */
+#define CAN_WORD0_COUNT                          (64U)
+
+/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
+/*! @{ */
+#define CAN_WORD1_DATA_BYTE_7_MASK               (0xFFU)
+#define CAN_WORD1_DATA_BYTE_7_SHIFT              (0U)
+/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.
+ */
+#define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
+#define CAN_WORD1_DATA_BYTE_6_MASK               (0xFF00U)
+#define CAN_WORD1_DATA_BYTE_6_SHIFT              (8U)
+/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.
+ */
+#define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
+#define CAN_WORD1_DATA_BYTE_5_MASK               (0xFF0000U)
+#define CAN_WORD1_DATA_BYTE_5_SHIFT              (16U)
+/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.
+ */
+#define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
+#define CAN_WORD1_DATA_BYTE_4_MASK               (0xFF000000U)
+#define CAN_WORD1_DATA_BYTE_4_SHIFT              (24U)
+/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.
+ */
+#define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
+/*! @} */
+
+/* The count of CAN_WORD1 */
+#define CAN_WORD1_COUNT                          (64U)
+
+/*! @name RXIMR - Rx Individual Mask registers */
+/*! @{ */
+#define CAN_RXIMR_MI_MASK                        (0xFFFFFFFFU)
+#define CAN_RXIMR_MI_SHIFT                       (0U)
+/*! MI - Individual Mask Bits
+ */
+#define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
+/*! @} */
+
+/* The count of CAN_RXIMR */
+#define CAN_RXIMR_COUNT                          (64U)
+
+/*! @name FDCTRL - CAN FD Control register */
+/*! @{ */
+#define CAN_FDCTRL_TDCVAL_MASK                   (0x3FU)
+#define CAN_FDCTRL_TDCVAL_SHIFT                  (0U)
+/*! TDCVAL - Transceiver Delay Compensation Value
+ */
+#define CAN_FDCTRL_TDCVAL(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
+#define CAN_FDCTRL_TDCOFF_MASK                   (0x1F00U)
+#define CAN_FDCTRL_TDCOFF_SHIFT                  (8U)
+/*! TDCOFF - Transceiver Delay Compensation Offset
+ */
+#define CAN_FDCTRL_TDCOFF(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
+#define CAN_FDCTRL_TDCFAIL_MASK                  (0x4000U)
+#define CAN_FDCTRL_TDCFAIL_SHIFT                 (14U)
+/*! TDCFAIL - Transceiver Delay Compensation Fail
+ *  0b0..Measured loop delay is in range.
+ *  0b1..Measured loop delay is out of range.
+ */
+#define CAN_FDCTRL_TDCFAIL(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
+#define CAN_FDCTRL_TDCEN_MASK                    (0x8000U)
+#define CAN_FDCTRL_TDCEN_SHIFT                   (15U)
+/*! TDCEN - Transceiver Delay Compensation Enable
+ *  0b0..TDC is disabled
+ *  0b1..TDC is enabled
+ */
+#define CAN_FDCTRL_TDCEN(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
+#define CAN_FDCTRL_MBDSR0_MASK                   (0x30000U)
+#define CAN_FDCTRL_MBDSR0_SHIFT                  (16U)
+/*! MBDSR0 - Message Buffer Data Size for Region 0
+ *  0b00..Selects 8 bytes per message buffer.
+ *  0b01..Selects 16 bytes per message buffer.
+ *  0b10..Selects 32 bytes per message buffer.
+ *  0b11..Selects 64 bytes per message buffer.
+ */
+#define CAN_FDCTRL_MBDSR0(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
+#define CAN_FDCTRL_MBDSR1_MASK                   (0x180000U)
+#define CAN_FDCTRL_MBDSR1_SHIFT                  (19U)
+/*! MBDSR1 - Message Buffer Data Size for Region 1
+ *  0b00..Selects 8 bytes per message buffer.
+ *  0b01..Selects 16 bytes per message buffer.
+ *  0b10..Selects 32 bytes per message buffer.
+ *  0b11..Selects 64 bytes per message buffer.
+ */
+#define CAN_FDCTRL_MBDSR1(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)
+#define CAN_FDCTRL_FDRATE_MASK                   (0x80000000U)
+#define CAN_FDCTRL_FDRATE_SHIFT                  (31U)
+/*! FDRATE - Bit Rate Switch Enable
+ *  0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect.
+ *  0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive.
+ */
+#define CAN_FDCTRL_FDRATE(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
+/*! @} */
+
+/*! @name FDCBT - CAN FD Bit Timing register */
+/*! @{ */
+#define CAN_FDCBT_FPSEG2_MASK                    (0x7U)
+#define CAN_FDCBT_FPSEG2_SHIFT                   (0U)
+/*! FPSEG2 - Fast Phase Segment 2
+ */
+#define CAN_FDCBT_FPSEG2(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
+#define CAN_FDCBT_FPSEG1_MASK                    (0xE0U)
+#define CAN_FDCBT_FPSEG1_SHIFT                   (5U)
+/*! FPSEG1 - Fast Phase Segment 1
+ */
+#define CAN_FDCBT_FPSEG1(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
+#define CAN_FDCBT_FPROPSEG_MASK                  (0x7C00U)
+#define CAN_FDCBT_FPROPSEG_SHIFT                 (10U)
+/*! FPROPSEG - Fast Propagation Segment
+ */
+#define CAN_FDCBT_FPROPSEG(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
+#define CAN_FDCBT_FRJW_MASK                      (0x70000U)
+#define CAN_FDCBT_FRJW_SHIFT                     (16U)
+/*! FRJW - Fast Resync Jump Width
+ */
+#define CAN_FDCBT_FRJW(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
+#define CAN_FDCBT_FPRESDIV_MASK                  (0x3FF00000U)
+#define CAN_FDCBT_FPRESDIV_SHIFT                 (20U)
+/*! FPRESDIV - Fast Prescaler Division Factor
+ */
+#define CAN_FDCBT_FPRESDIV(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
+/*! @} */
+
+/*! @name FDCRC - CAN FD CRC register */
+/*! @{ */
+#define CAN_FDCRC_FD_TXCRC_MASK                  (0x1FFFFFU)
+#define CAN_FDCRC_FD_TXCRC_SHIFT                 (0U)
+/*! FD_TXCRC - Extended Transmitted CRC value
+ */
+#define CAN_FDCRC_FD_TXCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
+#define CAN_FDCRC_FD_MBCRC_MASK                  (0x7F000000U)
+#define CAN_FDCRC_FD_MBCRC_SHIFT                 (24U)
+/*! FD_MBCRC - CRC Mailbox Number for FD_TXCRC
+ */
+#define CAN_FDCRC_FD_MBCRC(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral ADMA__CAN0 base address */
+#define ADMA__CAN0_BASE                          (0x5A8D0000u)
+/** Peripheral ADMA__CAN0 base pointer */
+#define ADMA__CAN0                               ((CAN_Type *)ADMA__CAN0_BASE)
+/** Peripheral ADMA__CAN1 base address */
+#define ADMA__CAN1_BASE                          (0x5A8E0000u)
+/** Peripheral ADMA__CAN1 base pointer */
+#define ADMA__CAN1                               ((CAN_Type *)ADMA__CAN1_BASE)
+/** Peripheral ADMA__CAN2 base address */
+#define ADMA__CAN2_BASE                          (0x5A8F0000u)
+/** Peripheral ADMA__CAN2 base pointer */
+#define ADMA__CAN2                               ((CAN_Type *)ADMA__CAN2_BASE)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS                           { ADMA__CAN0_BASE, ADMA__CAN1_BASE, ADMA__CAN2_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS                            { ADMA__CAN0, ADMA__CAN1, ADMA__CAN2 }
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_Rx_Warning_IRQS                      { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
+#define CAN_Tx_Warning_IRQS                      { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
+#define CAN_Wake_Up_IRQS                         { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
+#define CAN_Error_IRQS                           { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
+#define CAN_Bus_Off_IRQS                         { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
+#define CAN_ORed_Message_buffer_IRQS             { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CI_PI_CSR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CI_PI_CSR_Peripheral_Access_Layer CI_PI_CSR Peripheral Access Layer
+ * @{
+ */
+
+/** CI_PI_CSR - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0 */
+    __IO uint32_t RW;                                /**< CI_PI Interface Control Register, offset: 0x0 */
+    __IO uint32_t SET;                               /**< CI_PI Interface Control Register, offset: 0x4 */
+    __IO uint32_t CLR;                               /**< CI_PI Interface Control Register, offset: 0x8 */
+    __IO uint32_t TOG;                               /**< CI_PI Interface Control Register, offset: 0xC */
+  } IF_CTRL_REG;
+  struct {                                         /* offset: 0x10 */
+    __IO uint32_t RW;                                /**< CSI Interface Control Register, offset: 0x10 */
+    __IO uint32_t SET;                               /**< CSI Interface Control Register, offset: 0x14 */
+    __IO uint32_t CLR;                               /**< CSI Interface Control Register, offset: 0x18 */
+    __IO uint32_t TOG;                               /**< CSI Interface Control Register, offset: 0x1C */
+  } CSI_CTRL_REG;
+  struct {                                         /* offset: 0x20 */
+    __I  uint32_t RW;                                /**< CSI Interface Status Register, offset: 0x20 */
+    __I  uint32_t SET;                               /**< CSI Interface Status Register, offset: 0x24 */
+    __I  uint32_t CLR;                               /**< CSI Interface Status Register, offset: 0x28 */
+    __I  uint32_t TOG;                               /**< CSI Interface Status Register, offset: 0x2C */
+  } CSI_STATUS;
+  struct {                                         /* offset: 0x30 */
+    __IO uint32_t RW;                                /**< CSI Interface Control Register1, offset: 0x30 */
+    __IO uint32_t SET;                               /**< CSI Interface Control Register1, offset: 0x34 */
+    __IO uint32_t CLR;                               /**< CSI Interface Control Register1, offset: 0x38 */
+    __IO uint32_t TOG;                               /**< CSI Interface Control Register1, offset: 0x3C */
+  } CSI_CTRL_REG1;
+} CI_PI_CSR_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CI_PI_CSR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CI_PI_CSR_Register_Masks CI_PI_CSR Register Masks
+ * @{
+ */
+
+/*! @name IF_CTRL_REG - CI_PI Interface Control Register */
+/*! @{ */
+#define CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_MASK     (0x1U)
+#define CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_SHIFT    (0U)
+#define CI_PI_CSR_IF_CTRL_REG_PL_ENABLE(x)       (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_MASK)
+#define CI_PI_CSR_IF_CTRL_REG_PL_VALID_MASK      (0x2U)
+#define CI_PI_CSR_IF_CTRL_REG_PL_VALID_SHIFT     (1U)
+#define CI_PI_CSR_IF_CTRL_REG_PL_VALID(x)        (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_PL_VALID_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_PL_VALID_MASK)
+#define CI_PI_CSR_IF_CTRL_REG_PL_ADDR_MASK       (0x1CU)
+#define CI_PI_CSR_IF_CTRL_REG_PL_ADDR_SHIFT      (2U)
+#define CI_PI_CSR_IF_CTRL_REG_PL_ADDR(x)         (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_PL_ADDR_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_PL_ADDR_MASK)
+#define CI_PI_CSR_IF_CTRL_REG_IF_FORCE_MASK      (0xE0U)
+#define CI_PI_CSR_IF_CTRL_REG_IF_FORCE_SHIFT     (5U)
+#define CI_PI_CSR_IF_CTRL_REG_IF_FORCE(x)        (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_IF_FORCE_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_IF_FORCE_MASK)
+#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_MASK (0x100U)
+#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_SHIFT (8U)
+/*! DATA_TYPE_SEL - Pixel link data type select
+ *  0b0..PL data type comes from the csi_interface
+ *  0b1..PL data type comes from IF_CTRL DATA_TYPE[4:0]
+ */
+#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL(x)   (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_MASK)
+#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_MASK     (0x3E00U)
+#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SHIFT    (9U)
+/*! DATA_TYPE - Data type
+ *  0b00000..Null data
+ *  0b00100..RGB format
+ *  0b01000..YUV444 Format
+ *  0b10000..YYU420 odd line
+ *  0b10010..YYU420 even line
+ *  0b11000..YYY odd line
+ *  0b11010..UYVY Even line
+ *  0b11100..Raw
+ */
+#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE(x)       (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_MASK)
+/*! @} */
+
+/*! @name CSI_CTRL_REG - CSI Interface Control Register */
+/*! @{ */
+#define CI_PI_CSR_CSI_CTRL_REG_CSI_EN_MASK       (0x1U)
+#define CI_PI_CSR_CSI_CTRL_REG_CSI_EN_SHIFT      (0U)
+/*! CSI_EN - CSI interface enable
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_CSI_EN(x)         (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CSI_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CSI_EN_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_MASK (0x2U)
+#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_SHIFT (1U)
+/*! PIXEL_CLK_POL - Pixel Clock polarity control
+ *  0b0..Pixel Clock input is not inverted
+ *  0b1..Pixel Clock input is inverted
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL(x)  (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_MASK    (0x4U)
+#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_SHIFT   (2U)
+/*! HSYNC_POL - HSYNC polarity control
+ *  0b0..HSYNC output to Pixel Link is not inverted
+ *  0b1..HSYNC output to Pixel Link is inverted
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL(x)      (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_MASK    (0x8U)
+#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_SHIFT   (3U)
+/*! VSYNC_POL - VSYNC polarity control
+ *  0b0..VSYNC output to Pixel Link is not inverted
+ *  0b1..VSYNC output to Pixel Link is inverted
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL(x)      (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_DE_POL_MASK       (0x10U)
+#define CI_PI_CSR_CSI_CTRL_REG_DE_POL_SHIFT      (4U)
+/*! DE_POL - DE polarity control
+ *  0b0..DE output to Pixel Link is not inverted
+ *  0b1..DE output to Pixel Link is inverted
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_DE_POL(x)         (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_DE_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_DE_POL_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_MASK (0x20U)
+#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_SHIFT (5U)
+/*! PIXEL_DATA_POL - PIXEL_DATA polarity control
+ *  0b0..PIXEL_DATA output to Pixel Link is not inverted
+ *  0b1..PIXEL_DATA output to Pixel Link is inverted
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_MASK (0x40U)
+#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_SHIFT (6U)
+/*! CCIR_EXT_VSYNC_EN - External VSYNC enable
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_MASK      (0x80U)
+#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_SHIFT     (7U)
+/*! CCIR_EN - CCIR mode enable
+ *  0b0..CCIR mode disable
+ *  0b1..CCIR mode enable
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EN(x)        (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_MASK (0x100U)
+#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_SHIFT (8U)
+/*! CCIR_VIDEO_MODE - CCIR_VIDEO_MODE
+ *  0b0..Progressive mode
+ *  0b1..Interlace mode
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_MASK (0x200U)
+#define CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_SHIFT (9U)
+/*! CCIR_NTSC_EN - CCIR_NTSC enable
+ *  0b0..PAL
+ *  0b1..NTSC
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN(x)   (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_MASK (0x400U)
+#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_SHIFT (10U)
+/*! CCIR_VSYNC_RESET_EN - CCIR_VSYNC_RESET_EN
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_MASK (0x800U)
+#define CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_SHIFT (11U)
+/*! CCIR_ECC_ERR_CORRECT_EN - CCIR_ECC_ERR_CORRECT_EN
+ *  0b0..ECC error correction is disabled.
+ *  0b1..ECC error correction is enabled.
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_MASK (0x1000U)
+#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_SHIFT (12U)
+/*! HSYNC_FORCE_EN - HSYNC_FORCE_EN
+ *  0b0..Do not override HSYNC
+ *  0b1..Override HSYNC
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_MASK (0x2000U)
+#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_SHIFT (13U)
+/*! VSYNC_FORCE_EN - VSYNC_FORCE_EN
+ *  0b0..Do not override VSYNC
+ *  0b1..Override VSYNC
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_MASK (0x4000U)
+#define CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_SHIFT (14U)
+/*! GCLK_MODE_EN - GCLK_MODE_EN
+ *  0b0..Disable
+ *  0b1..Enable
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN(x)   (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_MASK    (0x8000U)
+#define CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_SHIFT   (15U)
+/*! VALID_SEL - VALID_SEL
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_VALID_SEL(x)      (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_MASK  (0x10000U)
+#define CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_SHIFT (16U)
+/*! RAW_OUT_SEL - RAW_OUT_SEL
+ *  0b0..Right justified output
+ *  0b1..Left justified to 14bit output
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL(x)    (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_MASK (0x20000U)
+#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_SHIFT (17U)
+/*! HSYNC_OUT_SEL - HSYNC_OUT_SEL
+ *  0b0..HSYNC output level
+ *  0b1..HSYNC output pulse
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL(x)  (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_MASK  (0x380000U)
+#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_SHIFT (19U)
+/*! HSYNC_PULSE - HSYNC_PULSE
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE(x)    (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_MASK   (0x400000U)
+#define CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_SHIFT  (22U)
+/*! UV_SWAP_EN - UV Swap enable
+ *  0b0..UV swap disable
+ *  0b1..UV swap enable
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN(x)     (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_MASK (0x7800000U)
+#define CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_SHIFT (23U)
+/*! DATA_TYPE_IN - CSI input data type
+ *  0b0000..UYVY bt656 8bit
+ *  0b0001..UYVY bt656 10bit
+ *  0b0010..RGB 8bit
+ *  0b0011..BGR 8bit
+ *  0b0100..RGB 24bit
+ *  0b0101..YVYU 8bit
+ *  0b0110..YUV 8bit
+ *  0b0111..YVYU 16bit
+ *  0b1000..YUV 24bit
+ *  0b1001..Bayer 8bit
+ *  0b1010..Bayer 10bit
+ *  0b1011..Bayer 12bit
+ *  0b1100..Bayer 16bit
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN(x)   (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_MASK (0x18000000U)
+#define CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_SHIFT (27U)
+/*! MASK_VSYNC_COUNTER - CSI mask VSYNC counter
+ *  0b00..not mask
+ *  0b01..mask 1 frame
+ *  0b10..mask 2 frames
+ *  0b11..mask 3 frames
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG_SOFTRST_MASK      (0x80000000U)
+#define CI_PI_CSR_CSI_CTRL_REG_SOFTRST_SHIFT     (31U)
+/*! SOFTRST - SOFTRST
+ */
+#define CI_PI_CSR_CSI_CTRL_REG_SOFTRST(x)        (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_SOFTRST_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_SOFTRST_MASK)
+/*! @} */
+
+/*! @name CSI_STATUS - CSI Interface Status Register */
+/*! @{ */
+#define CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_MASK   (0x1U)
+#define CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_SHIFT  (0U)
+#define CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE(x)     (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_SHIFT)) & CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_MASK)
+#define CI_PI_CSR_CSI_STATUS_ECC_ERROR_MASK      (0x2U)
+#define CI_PI_CSR_CSI_STATUS_ECC_ERROR_SHIFT     (1U)
+#define CI_PI_CSR_CSI_STATUS_ECC_ERROR(x)        (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_STATUS_ECC_ERROR_SHIFT)) & CI_PI_CSR_CSI_STATUS_ECC_ERROR_MASK)
+/*! @} */
+
+/*! @name CSI_CTRL_REG1 - CSI Interface Control Register1 */
+/*! @{ */
+#define CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_MASK (0xFFFFU)
+#define CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_SHIFT (0U)
+/*! PIXEL_WIDTH - CSI interface enable
+ */
+#define CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH(x)   (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_MASK)
+#define CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_MASK (0xFFFF0000U)
+#define CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_SHIFT (16U)
+/*! VSYNC_PULSE - VSYNC_PULSE
+ */
+#define CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE(x)   (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CI_PI_CSR_Register_Masks */
+
+
+/* CI_PI_CSR - Peripheral instance base addresses */
+/** Peripheral CI_PI_CSR base address */
+#define CI_PI_CSR_BASE                           (0x58261000u)
+/** Peripheral CI_PI_CSR base pointer */
+#define CI_PI_CSR                                ((CI_PI_CSR_Type *)CI_PI_CSR_BASE)
+/** Array initializer of CI_PI_CSR peripheral base addresses */
+#define CI_PI_CSR_BASE_ADDRS                     { CI_PI_CSR_BASE }
+/** Array initializer of CI_PI_CSR peripheral base pointers */
+#define CI_PI_CSR_BASE_PTRS                      { CI_PI_CSR }
+
+/*!
+ * @}
+ */ /* end of group CI_PI_CSR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CM4_LPCG_LPI2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CM4_LPCG_LPI2C_Peripheral_Access_Layer CM4_LPCG_LPI2C Peripheral Access Layer
+ * @{
+ */
+
+/** CM4_LPCG_LPI2C - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t LPCG_LPI2C_0;                      /**< na, offset: 0x0 */
+} CM4_LPCG_LPI2C_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CM4_LPCG_LPI2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CM4_LPCG_LPI2C_Register_Masks CM4_LPCG_LPI2C Register Masks
+ * @{
+ */
+
+/*! @name LPCG_LPI2C_0 - na */
+/*! @{ */
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK (0x1U)
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT (0U)
+/*! lpi2c1_lpi2c_div_clk_HWEN - Hardware Enable
+ *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
+ *  0b1..Enable HW automatic gating
+ */
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK)
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK (0x2U)
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT (1U)
+/*! lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK)
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK (0x4U)
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT (2U)
+/*! LPCG_LPI2C_0_reserved_2_2 - reserved
+ */
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK)
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK (0x8U)
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT (3U)
+/*! lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK)
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK (0x10U)
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT (4U)
+/*! LPCG_LPI2C_0_reserved_4_4 - reserved
+ */
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK)
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK (0x20U)
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT (5U)
+/*! lpi2c1_ipg_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK)
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK (0x40U)
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT (6U)
+/*! LPCG_LPI2C_0_reserved_6_6 - reserved
+ */
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK)
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK (0x80U)
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT (7U)
+/*! lpi2c1_ipg_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK)
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK (0xFFFFFF00U)
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT (8U)
+/*! LPCG_LPI2C_0_reserved_8_31 - reserved
+ */
+#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CM4_LPCG_LPI2C_Register_Masks */
+
+
+/* CM4_LPCG_LPI2C - Peripheral instance base addresses */
+/** Peripheral CM4__LPCG_LPI2C base address */
+#define CM4__LPCG_LPI2C_BASE                     (0x41630000u)
+/** Peripheral CM4__LPCG_LPI2C base pointer */
+#define CM4__LPCG_LPI2C                          ((CM4_LPCG_LPI2C_Type *)CM4__LPCG_LPI2C_BASE)
+/** Array initializer of CM4_LPCG_LPI2C peripheral base addresses */
+#define CM4_LPCG_LPI2C_BASE_ADDRS                { CM4__LPCG_LPI2C_BASE }
+/** Array initializer of CM4_LPCG_LPI2C peripheral base pointers */
+#define CM4_LPCG_LPI2C_BASE_PTRS                 { CM4__LPCG_LPI2C }
+
+/*!
+ * @}
+ */ /* end of group CM4_LPCG_LPI2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CM4_LPCG_LPIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CM4_LPCG_LPIT_Peripheral_Access_Layer CM4_LPCG_LPIT Peripheral Access Layer
+ * @{
+ */
+
+/** CM4_LPCG_LPIT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t LPCG_LPIT_0;                       /**< na, offset: 0x0 */
+} CM4_LPCG_LPIT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CM4_LPCG_LPIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CM4_LPCG_LPIT_Register_Masks CM4_LPCG_LPIT Register Masks
+ * @{
+ */
+
+/*! @name LPCG_LPIT_0 - na */
+/*! @{ */
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK (0x1U)
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT (0U)
+/*! lpit1_ipg_per_clk_HWEN - Hardware Enable
+ *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
+ *  0b1..Enable HW automatic gating
+ */
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK)
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK (0x2U)
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT (1U)
+/*! lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK)
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK (0x4U)
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT (2U)
+/*! LPCG_LPIT_0_reserved_2_2 - reserved
+ */
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK)
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK (0x8U)
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT (3U)
+/*! lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK)
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK (0x10U)
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT (4U)
+/*! LPCG_LPIT_0_reserved_4_4 - reserved
+ */
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK)
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK (0x20U)
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT (5U)
+/*! lpit1_ipg_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK)
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK (0x40U)
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT (6U)
+/*! LPCG_LPIT_0_reserved_6_6 - reserved
+ */
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK)
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK (0x80U)
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT (7U)
+/*! lpit1_ipg_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK)
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK (0xFFFFFF00U)
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT (8U)
+/*! LPCG_LPIT_0_reserved_8_31 - reserved
+ */
+#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CM4_LPCG_LPIT_Register_Masks */
+
+
+/* CM4_LPCG_LPIT - Peripheral instance base addresses */
+/** Peripheral CM4__LPCG_LPIT base address */
+#define CM4__LPCG_LPIT_BASE                      (0x41610000u)
+/** Peripheral CM4__LPCG_LPIT base pointer */
+#define CM4__LPCG_LPIT                           ((CM4_LPCG_LPIT_Type *)CM4__LPCG_LPIT_BASE)
+/** Array initializer of CM4_LPCG_LPIT peripheral base addresses */
+#define CM4_LPCG_LPIT_BASE_ADDRS                 { CM4__LPCG_LPIT_BASE }
+/** Array initializer of CM4_LPCG_LPIT peripheral base pointers */
+#define CM4_LPCG_LPIT_BASE_PTRS                  { CM4__LPCG_LPIT }
+
+/*!
+ * @}
+ */ /* end of group CM4_LPCG_LPIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CM4_LPCG_LPUART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CM4_LPCG_LPUART_Peripheral_Access_Layer CM4_LPCG_LPUART Peripheral Access Layer
+ * @{
+ */
+
+/** CM4_LPCG_LPUART - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t LPCG_LPUART_0;                     /**< na, offset: 0x0 */
+} CM4_LPCG_LPUART_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CM4_LPCG_LPUART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CM4_LPCG_LPUART_Register_Masks CM4_LPCG_LPUART Register Masks
+ * @{
+ */
+
+/*! @name LPCG_LPUART_0 - na */
+/*! @{ */
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK (0x1U)
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT (0U)
+/*! lpuart1_lpuart_baud_gated_clk_HWEN - Hardware Enable
+ *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
+ *  0b1..Enable HW automatic gating
+ */
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK)
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK (0x2U)
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT (1U)
+/*! lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK)
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK (0x4U)
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT (2U)
+/*! LPCG_LPUART_0_reserved_2_2 - reserved
+ */
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK)
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK (0x8U)
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT (3U)
+/*! lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK)
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK (0x10U)
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT (4U)
+/*! LPCG_LPUART_0_reserved_4_4 - reserved
+ */
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK)
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK (0x20U)
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT (5U)
+/*! lpuart1_ipg_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK)
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK (0x40U)
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT (6U)
+/*! LPCG_LPUART_0_reserved_6_6 - reserved
+ */
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK)
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK (0x80U)
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT (7U)
+/*! lpuart1_ipg_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK)
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK (0xFFFFFF00U)
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT (8U)
+/*! LPCG_LPUART_0_reserved_8_31 - reserved
+ */
+#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CM4_LPCG_LPUART_Register_Masks */
+
+
+/* CM4_LPCG_LPUART - Peripheral instance base addresses */
+/** Peripheral CM4__LPCG_LPUART base address */
+#define CM4__LPCG_LPUART_BASE                    (0x41620000u)
+/** Peripheral CM4__LPCG_LPUART base pointer */
+#define CM4__LPCG_LPUART                         ((CM4_LPCG_LPUART_Type *)CM4__LPCG_LPUART_BASE)
+/** Array initializer of CM4_LPCG_LPUART peripheral base addresses */
+#define CM4_LPCG_LPUART_BASE_ADDRS               { CM4__LPCG_LPUART_BASE }
+/** Array initializer of CM4_LPCG_LPUART peripheral base pointers */
+#define CM4_LPCG_LPUART_BASE_PTRS                { CM4__LPCG_LPUART }
+
+/*!
+ * @}
+ */ /* end of group CM4_LPCG_LPUART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CM4_LPCG_MMCAU_HCLK Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CM4_LPCG_MMCAU_HCLK_Peripheral_Access_Layer CM4_LPCG_MMCAU_HCLK Peripheral Access Layer
+ * @{
+ */
+
+/** CM4_LPCG_MMCAU_HCLK - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t LPCG_MMCAU_HCLK_0;                 /**< na, offset: 0x0 */
+} CM4_LPCG_MMCAU_HCLK_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CM4_LPCG_MMCAU_HCLK Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CM4_LPCG_MMCAU_HCLK_Register_Masks CM4_LPCG_MMCAU_HCLK Register Masks
+ * @{
+ */
+
+/*! @name LPCG_MMCAU_HCLK_0 - na */
+/*! @{ */
+#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK (0x1U)
+#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT (0U)
+/*! LPCG_MMCAU_HCLK_0_reserved_0_0 - reserved
+ */
+#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK)
+#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK (0x2U)
+#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT (1U)
+/*! cm4_mmcau_hclk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK)
+#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK (0x4U)
+#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT (2U)
+/*! LPCG_MMCAU_HCLK_0_reserved_2_2 - reserved
+ */
+#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK)
+#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK (0x8U)
+#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT (3U)
+/*! cm4_mmcau_hclk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK)
+#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U)
+#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT (4U)
+/*! LPCG_MMCAU_HCLK_0_reserved_4_31 - reserved
+ */
+#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CM4_LPCG_MMCAU_HCLK_Register_Masks */
+
+
+/* CM4_LPCG_MMCAU_HCLK - Peripheral instance base addresses */
+/** Peripheral CM4__LPCG_MMCAU_HCLK base address */
+#define CM4__LPCG_MMCAU_HCLK_BASE                (0x415F0000u)
+/** Peripheral CM4__LPCG_MMCAU_HCLK base pointer */
+#define CM4__LPCG_MMCAU_HCLK                     ((CM4_LPCG_MMCAU_HCLK_Type *)CM4__LPCG_MMCAU_HCLK_BASE)
+/** Array initializer of CM4_LPCG_MMCAU_HCLK peripheral base addresses */
+#define CM4_LPCG_MMCAU_HCLK_BASE_ADDRS           { CM4__LPCG_MMCAU_HCLK_BASE }
+/** Array initializer of CM4_LPCG_MMCAU_HCLK peripheral base pointers */
+#define CM4_LPCG_MMCAU_HCLK_BASE_PTRS            { CM4__LPCG_MMCAU_HCLK }
+
+/*!
+ * @}
+ */ /* end of group CM4_LPCG_MMCAU_HCLK_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CM4_LPCG_TCMC_HCLK Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CM4_LPCG_TCMC_HCLK_Peripheral_Access_Layer CM4_LPCG_TCMC_HCLK Peripheral Access Layer
+ * @{
+ */
+
+/** CM4_LPCG_TCMC_HCLK - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t LPCG_TCMC_HCLK_0;                  /**< na, offset: 0x0 */
+} CM4_LPCG_TCMC_HCLK_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CM4_LPCG_TCMC_HCLK Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CM4_LPCG_TCMC_HCLK_Register_Masks CM4_LPCG_TCMC_HCLK Register Masks
+ * @{
+ */
+
+/*! @name LPCG_TCMC_HCLK_0 - na */
+/*! @{ */
+#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK (0x1U)
+#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT (0U)
+/*! cm4_tcmc_hclk_HWEN - Hardware Enable
+ *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
+ *  0b1..Enable HW automatic gating
+ */
+#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK)
+#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK (0x2U)
+#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT (1U)
+/*! cm4_tcmc_hclk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK)
+#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK (0x4U)
+#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT (2U)
+/*! LPCG_TCMC_HCLK_0_reserved_2_2 - reserved
+ */
+#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK)
+#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK (0x8U)
+#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT (3U)
+/*! cm4_tcmc_hclk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK)
+#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U)
+#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT (4U)
+/*! LPCG_TCMC_HCLK_0_reserved_4_31 - reserved
+ */
+#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CM4_LPCG_TCMC_HCLK_Register_Masks */
+
+
+/* CM4_LPCG_TCMC_HCLK - Peripheral instance base addresses */
+/** Peripheral CM4__LPCG_TCMC_HCLK base address */
+#define CM4__LPCG_TCMC_HCLK_BASE                 (0x415E0000u)
+/** Peripheral CM4__LPCG_TCMC_HCLK base pointer */
+#define CM4__LPCG_TCMC_HCLK                      ((CM4_LPCG_TCMC_HCLK_Type *)CM4__LPCG_TCMC_HCLK_BASE)
+/** Array initializer of CM4_LPCG_TCMC_HCLK peripheral base addresses */
+#define CM4_LPCG_TCMC_HCLK_BASE_ADDRS            { CM4__LPCG_TCMC_HCLK_BASE }
+/** Array initializer of CM4_LPCG_TCMC_HCLK peripheral base pointers */
+#define CM4_LPCG_TCMC_HCLK_BASE_PTRS             { CM4__LPCG_TCMC_HCLK }
+
+/*!
+ * @}
+ */ /* end of group CM4_LPCG_TCMC_HCLK_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CM4_LPCG_TPM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CM4_LPCG_TPM_Peripheral_Access_Layer CM4_LPCG_TPM Peripheral Access Layer
+ * @{
+ */
+
+/** CM4_LPCG_TPM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t LPCG_TPM_0;                        /**< na, offset: 0x0 */
+} CM4_LPCG_TPM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CM4_LPCG_TPM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CM4_LPCG_TPM_Register_Masks CM4_LPCG_TPM Register Masks
+ * @{
+ */
+
+/*! @name LPCG_TPM_0 - na */
+/*! @{ */
+#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK (0x1U)
+#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT (0U)
+/*! LPCG_TPM_0_reserved_0_0 - reserved
+ */
+#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK)
+#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK (0x2U)
+#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT (1U)
+/*! tpm1_lptpm_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK)
+#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK (0x4U)
+#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT (2U)
+/*! LPCG_TPM_0_reserved_2_2 - reserved
+ */
+#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK)
+#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK (0x8U)
+#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT (3U)
+/*! tpm1_lptpm_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK)
+#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK (0x10U)
+#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT (4U)
+/*! LPCG_TPM_0_reserved_4_4 - reserved
+ */
+#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK)
+#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK (0x20U)
+#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT (5U)
+/*! tpm1_ipg_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK)
+#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK (0x40U)
+#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT (6U)
+/*! LPCG_TPM_0_reserved_6_6 - reserved
+ */
+#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK)
+#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK (0x80U)
+#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT (7U)
+/*! tpm1_ipg_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK)
+#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK (0xFFFFFF00U)
+#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT (8U)
+/*! LPCG_TPM_0_reserved_8_31 - reserved
+ */
+#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CM4_LPCG_TPM_Register_Masks */
+
+
+/* CM4_LPCG_TPM - Peripheral instance base addresses */
+/** Peripheral CM4__LPCG_TPM base address */
+#define CM4__LPCG_TPM_BASE                       (0x41600000u)
+/** Peripheral CM4__LPCG_TPM base pointer */
+#define CM4__LPCG_TPM                            ((CM4_LPCG_TPM_Type *)CM4__LPCG_TPM_BASE)
+/** Array initializer of CM4_LPCG_TPM peripheral base addresses */
+#define CM4_LPCG_TPM_BASE_ADDRS                  { CM4__LPCG_TPM_BASE }
+/** Array initializer of CM4_LPCG_TPM peripheral base pointers */
+#define CM4_LPCG_TPM_BASE_PTRS                   { CM4__LPCG_TPM }
+
+/*!
+ * @}
+ */ /* end of group CM4_LPCG_TPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CONNECTIVITY_LPCG_EDMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CONNECTIVITY_LPCG_EDMA_Peripheral_Access_Layer CONNECTIVITY_LPCG_EDMA Peripheral Access Layer
+ * @{
+ */
+
+/** CONNECTIVITY_LPCG_EDMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t LPCG_LPCG_EDMA_0;                  /**< na, offset: 0x0 */
+} CONNECTIVITY_LPCG_EDMA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CONNECTIVITY_LPCG_EDMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CONNECTIVITY_LPCG_EDMA_Register_Masks CONNECTIVITY_LPCG_EDMA Register Masks
+ * @{
+ */
+
+/*! @name LPCG_LPCG_EDMA_0 - na */
+/*! @{ */
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_MASK (0x1U)
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_SHIFT (0U)
+/*! edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN - Hardware Enable
+ *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
+ *  0b1..Enable HW automatic gating
+ */
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_MASK)
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_MASK (0x2U)
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_SHIFT (1U)
+/*! edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_MASK (0x4U)
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_SHIFT (2U)
+/*! LPCG_lpcg_edma_0_reserved_2_2 - reserved
+ */
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_MASK)
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_MASK (0x8U)
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_SHIFT (3U)
+/*! edma_hclk_STOP_AND_edma_mem_dma_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_MASK)
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_MASK (0x1FFF0U)
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_SHIFT (4U)
+/*! LPCG_lpcg_edma_0_reserved_4_16 - reserved
+ */
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_MASK)
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_MASK (0x20000U)
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_SHIFT (17U)
+/*! edma_ipg_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_MASK (0x40000U)
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_SHIFT (18U)
+/*! LPCG_lpcg_edma_0_reserved_18_18 - reserved
+ */
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_MASK)
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_MASK (0x80000U)
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_SHIFT (19U)
+/*! edma_ipg_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_MASK)
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_MASK (0xFFF00000U)
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_SHIFT (20U)
+/*! LPCG_lpcg_edma_0_reserved_20_31 - reserved
+ */
+#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CONNECTIVITY_LPCG_EDMA_Register_Masks */
+
+
+/* CONNECTIVITY_LPCG_EDMA - Peripheral instance base addresses */
+/** Peripheral CONNECTIVITY__LPCG_EDMA base address */
+#define CONNECTIVITY__LPCG_EDMA_BASE             (0x5B2A0000u)
+/** Peripheral CONNECTIVITY__LPCG_EDMA base pointer */
+#define CONNECTIVITY__LPCG_EDMA                  ((CONNECTIVITY_LPCG_EDMA_Type *)CONNECTIVITY__LPCG_EDMA_BASE)
+/** Array initializer of CONNECTIVITY_LPCG_EDMA peripheral base addresses */
+#define CONNECTIVITY_LPCG_EDMA_BASE_ADDRS        { CONNECTIVITY__LPCG_EDMA_BASE }
+/** Array initializer of CONNECTIVITY_LPCG_EDMA peripheral base pointers */
+#define CONNECTIVITY_LPCG_EDMA_BASE_PTRS         { CONNECTIVITY__LPCG_EDMA }
+
+/*!
+ * @}
+ */ /* end of group CONNECTIVITY_LPCG_EDMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CONNECTIVITY_LPCG_ENET0 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CONNECTIVITY_LPCG_ENET0_Peripheral_Access_Layer CONNECTIVITY_LPCG_ENET0 Peripheral Access Layer
+ * @{
+ */
+
+/** CONNECTIVITY_LPCG_ENET0 - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t LPCG_LPCG_ENET1_0;                 /**< na, offset: 0x0 */
+  __IO uint32_t LPCG_LPCG_ENET1_4;                 /**< na, offset: 0x4 */
+} CONNECTIVITY_LPCG_ENET0_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CONNECTIVITY_LPCG_ENET0 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CONNECTIVITY_LPCG_ENET0_Register_Masks CONNECTIVITY_LPCG_ENET0 Register Masks
+ * @{
+ */
+
+/*! @name LPCG_LPCG_ENET1_0 - na */
+/*! @{ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_MASK (0x1U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_SHIFT (0U)
+/*! enet1_ipg_clk_time_HWEN - Hardware Enable
+ *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
+ *  0b1..Enable HW automatic gating
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_MASK (0x2U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_SHIFT (1U)
+/*! enet1_ipg_clk_time_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_MASK (0x4U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_SHIFT (2U)
+/*! LPCG_lpcg_enet1_0_reserved_2_2 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_MASK (0x8U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_SHIFT (3U)
+/*! enet1_ipg_clk_time_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_MASK (0x10U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_SHIFT (4U)
+/*! LPCG_lpcg_enet1_0_reserved_4_4 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_MASK (0x20U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_SHIFT (5U)
+/*! enet1_2x_txclk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_MASK (0x40U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_SHIFT (6U)
+/*! LPCG_lpcg_enet1_0_reserved_6_6 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_MASK (0x80U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_SHIFT (7U)
+/*! enet1_2x_txclk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_MASK (0x100U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_SHIFT (8U)
+/*! LPCG_lpcg_enet1_0_reserved_8_8 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_MASK (0x200U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_SHIFT (9U)
+/*! enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_MASK (0x400U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_SHIFT (10U)
+/*! LPCG_lpcg_enet1_0_reserved_10_10 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_MASK (0x800U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_SHIFT (11U)
+/*! enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_MASK (0x1000U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_SHIFT (12U)
+/*! LPCG_lpcg_enet1_0_reserved_12_12 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_MASK (0x2000U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_SHIFT (13U)
+/*! enet1_clkdiv_clk_in_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_MASK (0x4000U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_SHIFT (14U)
+/*! LPCG_lpcg_enet1_0_reserved_14_14 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_MASK (0x8000U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_SHIFT (15U)
+/*! enet1_clkdiv_clk_in_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_MASK (0x10000U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_SHIFT (16U)
+/*! enet1_ipg_clk_mac0_HWEN - Hardware Enable
+ *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
+ *  0b1..Enable HW automatic gating
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_MASK (0x20000U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_SHIFT (17U)
+/*! enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_MASK (0x40000U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_SHIFT (18U)
+/*! LPCG_lpcg_enet1_0_reserved_18_18 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_MASK (0x80000U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_SHIFT (19U)
+/*! enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_MASK (0x100000U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_SHIFT (20U)
+/*! enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN - Hardware Enable
+ *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
+ *  0b1..Enable HW automatic gating
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_MASK (0x200000U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_SHIFT (21U)
+/*! enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_MASK (0x400000U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_SHIFT (22U)
+/*! LPCG_lpcg_enet1_0_reserved_22_22 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_MASK (0x800000U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_SHIFT (23U)
+/*! enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_MASK (0xFF000000U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_SHIFT (24U)
+/*! LPCG_lpcg_enet1_0_reserved_24_31 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_MASK)
+/*! @} */
+
+/*! @name LPCG_LPCG_ENET1_4 - na */
+/*! @{ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_MASK (0x1U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_SHIFT (0U)
+/*! LPCG_lpcg_enet1_4_reserved_0_0 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_MASK (0x2U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_SHIFT (1U)
+/*! enet1_mac0_rxclk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_MASK (0x4U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_SHIFT (2U)
+/*! LPCG_lpcg_enet1_4_reserved_2_2 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_MASK (0x8U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_SHIFT (3U)
+/*! enet1_mac0_rxclk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_MASK)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_MASK (0xFFFFFFF0U)
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_SHIFT (4U)
+/*! LPCG_lpcg_enet1_4_reserved_4_31 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CONNECTIVITY_LPCG_ENET0_Register_Masks */
+
+
+/* CONNECTIVITY_LPCG_ENET0 - Peripheral instance base addresses */
+/** Peripheral CONNECTIVITY__LPCG_ENET0 base address */
+#define CONNECTIVITY__LPCG_ENET0_BASE            (0x5B230000u)
+/** Peripheral CONNECTIVITY__LPCG_ENET0 base pointer */
+#define CONNECTIVITY__LPCG_ENET0                 ((CONNECTIVITY_LPCG_ENET0_Type *)CONNECTIVITY__LPCG_ENET0_BASE)
+/** Array initializer of CONNECTIVITY_LPCG_ENET0 peripheral base addresses */
+#define CONNECTIVITY_LPCG_ENET0_BASE_ADDRS       { CONNECTIVITY__LPCG_ENET0_BASE }
+/** Array initializer of CONNECTIVITY_LPCG_ENET0 peripheral base pointers */
+#define CONNECTIVITY_LPCG_ENET0_BASE_PTRS        { CONNECTIVITY__LPCG_ENET0 }
+
+/*!
+ * @}
+ */ /* end of group CONNECTIVITY_LPCG_ENET0_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CONNECTIVITY_LPCG_ENET1 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CONNECTIVITY_LPCG_ENET1_Peripheral_Access_Layer CONNECTIVITY_LPCG_ENET1 Peripheral Access Layer
+ * @{
+ */
+
+/** CONNECTIVITY_LPCG_ENET1 - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t LPCG_LPCG_ENET2_0;                 /**< na, offset: 0x0 */
+  __IO uint32_t LPCG_LPCG_ENET2_4;                 /**< na, offset: 0x4 */
+} CONNECTIVITY_LPCG_ENET1_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CONNECTIVITY_LPCG_ENET1 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CONNECTIVITY_LPCG_ENET1_Register_Masks CONNECTIVITY_LPCG_ENET1 Register Masks
+ * @{
+ */
+
+/*! @name LPCG_LPCG_ENET2_0 - na */
+/*! @{ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_MASK (0x1U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_SHIFT (0U)
+/*! enet2_ipg_clk_time_HWEN - Hardware Enable
+ *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
+ *  0b1..Enable HW automatic gating
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_MASK (0x2U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_SHIFT (1U)
+/*! enet2_ipg_clk_time_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_MASK (0x4U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_SHIFT (2U)
+/*! LPCG_lpcg_enet2_0_reserved_2_2 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_MASK (0x8U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_SHIFT (3U)
+/*! enet2_ipg_clk_time_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_MASK (0x10U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_SHIFT (4U)
+/*! LPCG_lpcg_enet2_0_reserved_4_4 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_MASK (0x20U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_SHIFT (5U)
+/*! enet2_2x_txclk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_MASK (0x40U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_SHIFT (6U)
+/*! LPCG_lpcg_enet2_0_reserved_6_6 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_MASK (0x80U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_SHIFT (7U)
+/*! enet2_2x_txclk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_MASK (0x100U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_SHIFT (8U)
+/*! LPCG_lpcg_enet2_0_reserved_8_8 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_MASK (0x200U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_SHIFT (9U)
+/*! enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_MASK (0x400U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_SHIFT (10U)
+/*! LPCG_lpcg_enet2_0_reserved_10_10 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_MASK (0x800U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_SHIFT (11U)
+/*! enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_MASK (0x1000U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_SHIFT (12U)
+/*! LPCG_lpcg_enet2_0_reserved_12_12 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_MASK (0x2000U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_SHIFT (13U)
+/*! enet2_clkdiv_clk_in_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_MASK (0x4000U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_SHIFT (14U)
+/*! LPCG_lpcg_enet2_0_reserved_14_14 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_MASK (0x8000U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_SHIFT (15U)
+/*! enet2_clkdiv_clk_in_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_MASK (0x10000U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_SHIFT (16U)
+/*! enet2_ipg_clk_mac0_HWEN - Hardware Enable
+ *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
+ *  0b1..Enable HW automatic gating
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_MASK (0x20000U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_SHIFT (17U)
+/*! enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_MASK (0x40000U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_SHIFT (18U)
+/*! LPCG_lpcg_enet2_0_reserved_18_18 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_MASK (0x80000U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_SHIFT (19U)
+/*! enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_MASK (0x100000U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_SHIFT (20U)
+/*! enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN - Hardware Enable
+ *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
+ *  0b1..Enable HW automatic gating
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_MASK (0x200000U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_SHIFT (21U)
+/*! enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_MASK (0x400000U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_SHIFT (22U)
+/*! LPCG_lpcg_enet2_0_reserved_22_22 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_MASK (0x800000U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_SHIFT (23U)
+/*! enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_MASK (0xFF000000U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_SHIFT (24U)
+/*! LPCG_lpcg_enet2_0_reserved_24_31 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_MASK)
+/*! @} */
+
+/*! @name LPCG_LPCG_ENET2_4 - na */
+/*! @{ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_MASK (0x1U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_SHIFT (0U)
+/*! LPCG_lpcg_enet2_4_reserved_0_0 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_MASK (0x2U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_SHIFT (1U)
+/*! enet2_mac0_rxclk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_MASK (0x4U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_SHIFT (2U)
+/*! LPCG_lpcg_enet2_4_reserved_2_2 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_MASK (0x8U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_SHIFT (3U)
+/*! enet2_mac0_rxclk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_MASK)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_MASK (0xFFFFFFF0U)
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_SHIFT (4U)
+/*! LPCG_lpcg_enet2_4_reserved_4_31 - reserved
+ */
+#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CONNECTIVITY_LPCG_ENET1_Register_Masks */
+
+
+/* CONNECTIVITY_LPCG_ENET1 - Peripheral instance base addresses */
+/** Peripheral CONNECTIVITY__LPCG_ENET1 base address */
+#define CONNECTIVITY__LPCG_ENET1_BASE            (0x5B240000u)
+/** Peripheral CONNECTIVITY__LPCG_ENET1 base pointer */
+#define CONNECTIVITY__LPCG_ENET1                 ((CONNECTIVITY_LPCG_ENET1_Type *)CONNECTIVITY__LPCG_ENET1_BASE)
+/** Array initializer of CONNECTIVITY_LPCG_ENET1 peripheral base addresses */
+#define CONNECTIVITY_LPCG_ENET1_BASE_ADDRS       { CONNECTIVITY__LPCG_ENET1_BASE }
+/** Array initializer of CONNECTIVITY_LPCG_ENET1 peripheral base pointers */
+#define CONNECTIVITY_LPCG_ENET1_BASE_PTRS        { CONNECTIVITY__LPCG_ENET1 }
+
+/*!
+ * @}
+ */ /* end of group CONNECTIVITY_LPCG_ENET1_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CONNECTIVITY_LPCG_MLB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CONNECTIVITY_LPCG_MLB_Peripheral_Access_Layer CONNECTIVITY_LPCG_MLB Peripheral Access Layer
+ * @{
+ */
+
+/** CONNECTIVITY_LPCG_MLB - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t LPCG_LPCG_MLB_0;                   /**< na, offset: 0x0 */
+} CONNECTIVITY_LPCG_MLB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CONNECTIVITY_LPCG_MLB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CONNECTIVITY_LPCG_MLB_Register_Masks CONNECTIVITY_LPCG_MLB Register Masks
+ * @{
+ */
+
+/*! @name LPCG_LPCG_MLB_0 - na */
+/*! @{ */
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_MASK (0x1U)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_SHIFT (0U)
+/*! LPCG_lpcg_mlb_0_reserved_0_0 - reserved
+ */
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_MASK)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_MASK (0x2U)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_SHIFT (1U)
+/*! mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_MASK)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_MASK (0x4U)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_SHIFT (2U)
+/*! LPCG_lpcg_mlb_0_reserved_2_2 - reserved
+ */
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_MASK)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_MASK (0x8U)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_SHIFT (3U)
+/*! mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_MASK)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_MASK (0xFFF0U)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_SHIFT (4U)
+/*! LPCG_lpcg_mlb_0_reserved_4_15 - reserved
+ */
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_MASK)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_MASK (0x10000U)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_SHIFT (16U)
+/*! mlb_ipg_clk_s_HWEN - Hardware Enable
+ *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
+ *  0b1..Enable HW automatic gating
+ */
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_MASK)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_MASK (0x20000U)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_SHIFT (17U)
+/*! mlb_ipg_clk_s_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_MASK)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_MASK (0x40000U)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_SHIFT (18U)
+/*! LPCG_lpcg_mlb_0_reserved_18_18 - reserved
+ */
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_MASK)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_MASK (0x80000U)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_SHIFT (19U)
+/*! mlb_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_MASK)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_MASK (0x100000U)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_SHIFT (20U)
+/*! LPCG_lpcg_mlb_0_reserved_20_20 - reserved
+ */
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_MASK)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_MASK (0x200000U)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_SHIFT (21U)
+/*! mlb_hclk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_MASK (0x400000U)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_SHIFT (22U)
+/*! LPCG_lpcg_mlb_0_reserved_22_22 - reserved
+ */
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_MASK)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_MASK (0x800000U)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_SHIFT (23U)
+/*! mlb_hclk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_MASK)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_MASK (0xFF000000U)
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_SHIFT (24U)
+/*! LPCG_lpcg_mlb_0_reserved_24_31 - reserved
+ */
+#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CONNECTIVITY_LPCG_MLB_Register_Masks */
+
+
+/* CONNECTIVITY_LPCG_MLB - Peripheral instance base addresses */
+/** Peripheral CONNECTIVITY__LPCG_MLB base address */
+#define CONNECTIVITY__LPCG_MLB_BASE              (0x5B260000u)
+/** Peripheral CONNECTIVITY__LPCG_MLB base pointer */
+#define CONNECTIVITY__LPCG_MLB                   ((CONNECTIVITY_LPCG_MLB_Type *)CONNECTIVITY__LPCG_MLB_BASE)
+/** Array initializer of CONNECTIVITY_LPCG_MLB peripheral base addresses */
+#define CONNECTIVITY_LPCG_MLB_BASE_ADDRS         { CONNECTIVITY__LPCG_MLB_BASE }
+/** Array initializer of CONNECTIVITY_LPCG_MLB peripheral base pointers */
+#define CONNECTIVITY_LPCG_MLB_BASE_PTRS          { CONNECTIVITY__LPCG_MLB }
+
+/*!
+ * @}
+ */ /* end of group CONNECTIVITY_LPCG_MLB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CONNECTIVITY_LPCG_RAWNAND Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CONNECTIVITY_LPCG_RAWNAND_Peripheral_Access_Layer CONNECTIVITY_LPCG_RAWNAND Peripheral Access Layer
+ * @{
+ */
+
+/** CONNECTIVITY_LPCG_RAWNAND - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t LPCG_LPCG_RAWNAND_0;               /**< na, offset: 0x0 */
+  __IO uint32_t LPCG_LPCG_RAWNAND_4;               /**< na, offset: 0x4 */
+} CONNECTIVITY_LPCG_RAWNAND_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CONNECTIVITY_LPCG_RAWNAND Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CONNECTIVITY_LPCG_RAWNAND_Register_Masks CONNECTIVITY_LPCG_RAWNAND Register Masks
+ * @{
+ */
+
+/*! @name LPCG_LPCG_RAWNAND_0 - na */
+/*! @{ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_MASK (0x1U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_SHIFT (0U)
+/*! LPCG_lpcg_rawnand_0_reserved_0_0 - reserved
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_MASK)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_MASK (0x2U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_SHIFT (1U)
+/*! rawnand_u_gpmi_bch_input_bch_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_MASK (0x4U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_SHIFT (2U)
+/*! LPCG_lpcg_rawnand_0_reserved_2_2 - reserved
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_MASK)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_MASK (0x8U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_SHIFT (3U)
+/*! rawnand_u_gpmi_bch_input_bch_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_MASK)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_MASK (0x10U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_SHIFT (4U)
+/*! LPCG_lpcg_rawnand_0_reserved_4_4 - reserved
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_MASK)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_MASK (0x20U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_SHIFT (5U)
+/*! rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_MASK (0x40U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_SHIFT (6U)
+/*! LPCG_lpcg_rawnand_0_reserved_6_6 - reserved
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_MASK)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_MASK (0x80U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_SHIFT (7U)
+/*! rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_MASK)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_MASK (0x1FF00U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_SHIFT (8U)
+/*! LPCG_lpcg_rawnand_0_reserved_8_16 - reserved
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_MASK)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_MASK (0x20000U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_SHIFT (17U)
+/*! rawnand_u_gpmi_input_apb_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_MASK (0x40000U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_SHIFT (18U)
+/*! LPCG_lpcg_rawnand_0_reserved_18_18 - reserved
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_MASK)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_MASK (0x80000U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_SHIFT (19U)
+/*! rawnand_u_gpmi_input_apb_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_MASK)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_MASK (0x100000U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_SHIFT (20U)
+/*! LPCG_lpcg_rawnand_0_reserved_20_20 - reserved
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_MASK)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_MASK (0x200000U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_SHIFT (21U)
+/*! rawnand_u_bch_input_apb_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_MASK (0x400000U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_SHIFT (22U)
+/*! LPCG_lpcg_rawnand_0_reserved_22_22 - reserved
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_MASK)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_MASK (0x800000U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_SHIFT (23U)
+/*! rawnand_u_bch_input_apb_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_MASK)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_MASK (0xFF000000U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_SHIFT (24U)
+/*! LPCG_lpcg_rawnand_0_reserved_24_31 - reserved
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_MASK)
+/*! @} */
+
+/*! @name LPCG_LPCG_RAWNAND_4 - na */
+/*! @{ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_MASK (0x1FFFFU)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_SHIFT (0U)
+/*! LPCG_lpcg_rawnand_4_reserved_0_16 - reserved
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_MASK)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_MASK (0x20000U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_SHIFT (17U)
+/*! apbhdma_hclk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_MASK (0x40000U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_SHIFT (18U)
+/*! LPCG_lpcg_rawnand_4_reserved_18_18 - reserved
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_MASK)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_MASK (0x80000U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_SHIFT (19U)
+/*! apbhdma_hclk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_MASK)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_MASK (0xFFF00000U)
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_SHIFT (20U)
+/*! LPCG_lpcg_rawnand_4_reserved_20_31 - reserved
+ */
+#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CONNECTIVITY_LPCG_RAWNAND_Register_Masks */
+
+
+/* CONNECTIVITY_LPCG_RAWNAND - Peripheral instance base addresses */
+/** Peripheral CONNECTIVITY__LPCG_RAWNAND base address */
+#define CONNECTIVITY__LPCG_RAWNAND_BASE          (0x5B290000u)
+/** Peripheral CONNECTIVITY__LPCG_RAWNAND base pointer */
+#define CONNECTIVITY__LPCG_RAWNAND               ((CONNECTIVITY_LPCG_RAWNAND_Type *)CONNECTIVITY__LPCG_RAWNAND_BASE)
+/** Array initializer of CONNECTIVITY_LPCG_RAWNAND peripheral base addresses */
+#define CONNECTIVITY_LPCG_RAWNAND_BASE_ADDRS     { CONNECTIVITY__LPCG_RAWNAND_BASE }
+/** Array initializer of CONNECTIVITY_LPCG_RAWNAND peripheral base pointers */
+#define CONNECTIVITY_LPCG_RAWNAND_BASE_PTRS      { CONNECTIVITY__LPCG_RAWNAND }
+
+/*!
+ * @}
+ */ /* end of group CONNECTIVITY_LPCG_RAWNAND_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CONNECTIVITY_LPCG_USB2 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CONNECTIVITY_LPCG_USB2_Peripheral_Access_Layer CONNECTIVITY_LPCG_USB2 Peripheral Access Layer
+ * @{
+ */
+
+/** CONNECTIVITY_LPCG_USB2 - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t LPCG_LPCG_USB2_0;                  /**< na, offset: 0x0 */
+} CONNECTIVITY_LPCG_USB2_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CONNECTIVITY_LPCG_USB2 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CONNECTIVITY_LPCG_USB2_Register_Masks CONNECTIVITY_LPCG_USB2 Register Masks
+ * @{
+ */
+
+/*! @name LPCG_LPCG_USB2_0 - na */
+/*! @{ */
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_MASK (0x1FFFFU)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_SHIFT (0U)
+/*! LPCG_lpcg_usb2_0_reserved_0_16 - reserved
+ */
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_MASK)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_MASK (0x20000U)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_SHIFT (17U)
+/*! usboh_ipg_clk_s_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_MASK)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_MASK (0x40000U)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_SHIFT (18U)
+/*! LPCG_lpcg_usb2_0_reserved_18_18 - reserved
+ */
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_MASK)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_MASK (0x80000U)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_SHIFT (19U)
+/*! usboh_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_MASK)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_MASK (0x100000U)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_SHIFT (20U)
+/*! LPCG_lpcg_usb2_0_reserved_20_20 - reserved
+ */
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_MASK)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_MASK (0x200000U)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_SHIFT (21U)
+/*! usboh_ipg_clk_s_pl301_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_MASK)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_MASK (0x400000U)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_SHIFT (22U)
+/*! LPCG_lpcg_usb2_0_reserved_22_22 - reserved
+ */
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_MASK)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_MASK (0x800000U)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_SHIFT (23U)
+/*! usboh_ipg_clk_s_pl301_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_MASK)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_MASK (0x1000000U)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_SHIFT (24U)
+/*! LPCG_lpcg_usb2_0_reserved_24_24 - reserved
+ */
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_MASK)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_MASK (0x2000000U)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_SHIFT (25U)
+/*! usboh_ipg_ahb_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_MASK (0x4000000U)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_SHIFT (26U)
+/*! LPCG_lpcg_usb2_0_reserved_26_26 - reserved
+ */
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_MASK)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_MASK (0x8000000U)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_SHIFT (27U)
+/*! usboh_ipg_ahb_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_MASK)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_MASK (0x10000000U)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_SHIFT (28U)
+/*! da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN - Hardware Enable
+ *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
+ *  0b1..Enable HW automatic gating
+ */
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_MASK)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_MASK (0x20000000U)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_SHIFT (29U)
+/*! da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_MASK)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_MASK (0x40000000U)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_SHIFT (30U)
+/*! LPCG_lpcg_usb2_0_reserved_30_30 - reserved
+ */
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_MASK)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_MASK (0x80000000U)
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_SHIFT (31U)
+/*! da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CONNECTIVITY_LPCG_USB2_Register_Masks */
+
+
+/* CONNECTIVITY_LPCG_USB2 - Peripheral instance base addresses */
+/** Peripheral CONNECTIVITY__LPCG_USB2 base address */
+#define CONNECTIVITY__LPCG_USB2_BASE             (0x5B270000u)
+/** Peripheral CONNECTIVITY__LPCG_USB2 base pointer */
+#define CONNECTIVITY__LPCG_USB2                  ((CONNECTIVITY_LPCG_USB2_Type *)CONNECTIVITY__LPCG_USB2_BASE)
+/** Array initializer of CONNECTIVITY_LPCG_USB2 peripheral base addresses */
+#define CONNECTIVITY_LPCG_USB2_BASE_ADDRS        { CONNECTIVITY__LPCG_USB2_BASE }
+/** Array initializer of CONNECTIVITY_LPCG_USB2 peripheral base pointers */
+#define CONNECTIVITY_LPCG_USB2_BASE_PTRS         { CONNECTIVITY__LPCG_USB2 }
+
+/*!
+ * @}
+ */ /* end of group CONNECTIVITY_LPCG_USB2_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CONNECTIVITY_LPCG_USB3 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CONNECTIVITY_LPCG_USB3_Peripheral_Access_Layer CONNECTIVITY_LPCG_USB3 Peripheral Access Layer
+ * @{
+ */
+
+/** CONNECTIVITY_LPCG_USB3 - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t LPCG_LPCG_USB3_0;                  /**< na, offset: 0x0 */
+} CONNECTIVITY_LPCG_USB3_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CONNECTIVITY_LPCG_USB3 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CONNECTIVITY_LPCG_USB3_Register_Masks CONNECTIVITY_LPCG_USB3 Register Masks
+ * @{
+ */
+
+/*! @name LPCG_LPCG_USB3_0 - na */
+/*! @{ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_MASK (0x1U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_SHIFT (0U)
+/*! LPCG_lpcg_usb3_0_reserved_0_0 - reserved
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_MASK (0x2U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_SHIFT (1U)
+/*! da_ip_usb3_wrap_app_clk_125_predft_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_MASK (0x4U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_SHIFT (2U)
+/*! LPCG_lpcg_usb3_0_reserved_2_2 - reserved
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_MASK (0x8U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_SHIFT (3U)
+/*! da_ip_usb3_wrap_app_clk_125_predft_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_MASK (0x10U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_SHIFT (4U)
+/*! LPCG_lpcg_usb3_0_reserved_4_4 - reserved
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_MASK (0x20U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_SHIFT (5U)
+/*! da_ip_usb3_wrap_lpm_clk_predft_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_MASK (0x40U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_SHIFT (6U)
+/*! LPCG_lpcg_usb3_0_reserved_6_6 - reserved
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_MASK (0x80U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_SHIFT (7U)
+/*! da_ip_usb3_wrap_lpm_clk_predft_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_MASK (0x1FF00U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_SHIFT (8U)
+/*! LPCG_lpcg_usb3_0_reserved_8_16 - reserved
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_MASK (0x20000U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_SHIFT (17U)
+/*! da_ip_usb3_wrap_ipg_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_MASK (0x40000U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_SHIFT (18U)
+/*! LPCG_lpcg_usb3_0_reserved_18_18 - reserved
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_MASK (0x80000U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_SHIFT (19U)
+/*! da_ip_usb3_wrap_ipg_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_MASK (0x100000U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_SHIFT (20U)
+/*! LPCG_lpcg_usb3_0_reserved_20_20 - reserved
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_MASK (0x200000U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_SHIFT (21U)
+/*! da_ip_usb3_wrap_usb3_core_pclk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_MASK (0x400000U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_SHIFT (22U)
+/*! LPCG_lpcg_usb3_0_reserved_22_22 - reserved
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_MASK (0x800000U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_SHIFT (23U)
+/*! da_ip_usb3_wrap_usb3_core_pclk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_MASK (0x1000000U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_SHIFT (24U)
+/*! LPCG_lpcg_usb3_0_reserved_24_24 - reserved
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_MASK (0x2000000U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_SHIFT (25U)
+/*! da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_MASK (0x4000000U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_SHIFT (26U)
+/*! LPCG_lpcg_usb3_0_reserved_26_26 - reserved
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_MASK (0x8000000U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_SHIFT (27U)
+/*! da_ip_usb3_wrap_usb3_ssphy_pclk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_MASK (0x10000000U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_SHIFT (28U)
+/*! LPCG_lpcg_usb3_0_reserved_28_28 - reserved
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_MASK (0x20000000U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_SHIFT (29U)
+/*! da_ip_usb3_wrap_usb3_aclk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_MASK (0x40000000U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_SHIFT (30U)
+/*! LPCG_lpcg_usb3_0_reserved_30_30 - reserved
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_MASK)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_MASK (0x80000000U)
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_SHIFT (31U)
+/*! da_ip_usb3_wrap_usb3_aclk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CONNECTIVITY_LPCG_USB3_Register_Masks */
+
+
+/* CONNECTIVITY_LPCG_USB3 - Peripheral instance base addresses */
+/** Peripheral CONNECTIVITY__LPCG_USB3 base address */
+#define CONNECTIVITY__LPCG_USB3_BASE             (0x5B280000u)
+/** Peripheral CONNECTIVITY__LPCG_USB3 base pointer */
+#define CONNECTIVITY__LPCG_USB3                  ((CONNECTIVITY_LPCG_USB3_Type *)CONNECTIVITY__LPCG_USB3_BASE)
+/** Array initializer of CONNECTIVITY_LPCG_USB3 peripheral base addresses */
+#define CONNECTIVITY_LPCG_USB3_BASE_ADDRS        { CONNECTIVITY__LPCG_USB3_BASE }
+/** Array initializer of CONNECTIVITY_LPCG_USB3 peripheral base pointers */
+#define CONNECTIVITY_LPCG_USB3_BASE_PTRS         { CONNECTIVITY__LPCG_USB3 }
+
+/*!
+ * @}
+ */ /* end of group CONNECTIVITY_LPCG_USB3_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CONNECTIVITY_LPCG_USDHC0 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CONNECTIVITY_LPCG_USDHC0_Peripheral_Access_Layer CONNECTIVITY_LPCG_USDHC0 Peripheral Access Layer
+ * @{
+ */
+
+/** CONNECTIVITY_LPCG_USDHC0 - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t LPCG_LPCG_USDHC1_0;                /**< na, offset: 0x0 */
+} CONNECTIVITY_LPCG_USDHC0_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CONNECTIVITY_LPCG_USDHC0 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CONNECTIVITY_LPCG_USDHC0_Register_Masks CONNECTIVITY_LPCG_USDHC0 Register Masks
+ * @{
+ */
+
+/*! @name LPCG_LPCG_USDHC1_0 - na */
+/*! @{ */
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_MASK (0x1U)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_SHIFT (0U)
+/*! LPCG_lpcg_usdhc1_0_reserved_0_0 - reserved
+ */
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_MASK)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_MASK (0x2U)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_SHIFT (1U)
+/*! usdhc1_ipg_clk_perclk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_MASK (0x4U)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_SHIFT (2U)
+/*! LPCG_lpcg_usdhc1_0_reserved_2_2 - reserved
+ */
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_MASK)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_MASK (0x8U)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_SHIFT (3U)
+/*! usdhc1_ipg_clk_perclk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_MASK)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_MASK (0xFFF0U)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_SHIFT (4U)
+/*! LPCG_lpcg_usdhc1_0_reserved_4_15 - reserved
+ */
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_MASK)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_MASK (0x10000U)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_SHIFT (16U)
+/*! usdhc1_ipg_clk_s_HWEN - Hardware Enable
+ *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
+ *  0b1..Enable HW automatic gating
+ */
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_MASK)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_MASK (0x20000U)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_SHIFT (17U)
+/*! usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_MASK (0x40000U)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_SHIFT (18U)
+/*! LPCG_lpcg_usdhc1_0_reserved_18_18 - reserved
+ */
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_MASK)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_MASK (0x80000U)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_SHIFT (19U)
+/*! usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_MASK)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_MASK (0x100000U)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_SHIFT (20U)
+/*! LPCG_lpcg_usdhc1_0_reserved_20_20 - reserved
+ */
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_MASK)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_MASK (0x200000U)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_SHIFT (21U)
+/*! usdhc1_hclk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_MASK (0x400000U)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_SHIFT (22U)
+/*! LPCG_lpcg_usdhc1_0_reserved_22_22 - reserved
+ */
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_MASK)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_MASK (0x800000U)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_SHIFT (23U)
+/*! usdhc1_hclk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_MASK)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_MASK (0xFF000000U)
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_SHIFT (24U)
+/*! LPCG_lpcg_usdhc1_0_reserved_24_31 - reserved
+ */
+#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CONNECTIVITY_LPCG_USDHC0_Register_Masks */
+
+
+/* CONNECTIVITY_LPCG_USDHC0 - Peripheral instance base addresses */
+/** Peripheral CONNECTIVITY__LPCG_USDHC0 base address */
+#define CONNECTIVITY__LPCG_USDHC0_BASE           (0x5B200000u)
+/** Peripheral CONNECTIVITY__LPCG_USDHC0 base pointer */
+#define CONNECTIVITY__LPCG_USDHC0                ((CONNECTIVITY_LPCG_USDHC0_Type *)CONNECTIVITY__LPCG_USDHC0_BASE)
+/** Array initializer of CONNECTIVITY_LPCG_USDHC0 peripheral base addresses */
+#define CONNECTIVITY_LPCG_USDHC0_BASE_ADDRS      { CONNECTIVITY__LPCG_USDHC0_BASE }
+/** Array initializer of CONNECTIVITY_LPCG_USDHC0 peripheral base pointers */
+#define CONNECTIVITY_LPCG_USDHC0_BASE_PTRS       { CONNECTIVITY__LPCG_USDHC0 }
+
+/*!
+ * @}
+ */ /* end of group CONNECTIVITY_LPCG_USDHC0_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CONNECTIVITY_LPCG_USDHC1 Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CONNECTIVITY_LPCG_USDHC1_Peripheral_Access_Layer CONNECTIVITY_LPCG_USDHC1 Peripheral Access Layer
+ * @{
+ */
+
+/** CONNECTIVITY_LPCG_USDHC1 - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t LPCG_LPCG_USDHC2_0;                /**< na, offset: 0x0 */
+} CONNECTIVITY_LPCG_USDHC1_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CONNECTIVITY_LPCG_USDHC1 Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CONNECTIVITY_LPCG_USDHC1_Register_Masks CONNECTIVITY_LPCG_USDHC1 Register Masks
+ * @{
+ */
+
+/*! @name LPCG_LPCG_USDHC2_0 - na */
+/*! @{ */
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_MASK (0x1U)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_SHIFT (0U)
+/*! LPCG_lpcg_usdhc2_0_reserved_0_0 - reserved
+ */
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_MASK)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_MASK (0x2U)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_SHIFT (1U)
+/*! usdhc2_ipg_clk_perclk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_MASK (0x4U)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_SHIFT (2U)
+/*! LPCG_lpcg_usdhc2_0_reserved_2_2 - reserved
+ */
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_MASK)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_MASK (0x8U)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_SHIFT (3U)
+/*! usdhc2_ipg_clk_perclk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_MASK)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_MASK (0xFFF0U)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_SHIFT (4U)
+/*! LPCG_lpcg_usdhc2_0_reserved_4_15 - reserved
+ */
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_MASK)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_MASK (0x10000U)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_SHIFT (16U)
+/*! usdhc2_ipg_clk_s_HWEN - Hardware Enable
+ *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
+ *  0b1..Enable HW automatic gating
+ */
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_MASK)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_MASK (0x20000U)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_SHIFT (17U)
+/*! usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_MASK (0x40000U)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_SHIFT (18U)
+/*! LPCG_lpcg_usdhc2_0_reserved_18_18 - reserved
+ */
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_MASK)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_MASK (0x80000U)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_SHIFT (19U)
+/*! usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_MASK)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_MASK (0x100000U)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_SHIFT (20U)
+/*! LPCG_lpcg_usdhc2_0_reserved_20_20 - reserved
+ */
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_MASK)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_MASK (0x200000U)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_SHIFT (21U)
+/*! usdhc2_hclk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_MASK)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_MASK (0x400000U)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_SHIFT (22U)
+/*! LPCG_lpcg_usdhc2_0_reserved_22_22 - reserved
+ */
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_MASK)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_MASK (0x800000U)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_SHIFT (23U)
+/*! usdhc2_hclk_STOP - show clock root status, 1 means clock stopped
+ */
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_MASK)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_MASK (0xFF000000U)
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_SHIFT (24U)
+/*! LPCG_lpcg_usdhc2_0_reserved_24_31 - reserved
+ */
+#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CONNECTIVITY_LPCG_USDHC1_Register_Masks */
+
+
+/* CONNECTIVITY_LPCG_USDHC1 - Peripheral instance base addresses */
+/** Peripheral CONNECTIVITY__LPCG_USDHC1 base address */
+#define CONNECTIVITY__LPCG_USDHC1_BASE           (0x5B210000u)
+/** Peripheral CONNECTIVITY__LPCG_USDHC1 base pointer */
+#define CONNECTIVITY__LPCG_USDHC1                ((CONNECTIVITY_LPCG_USDHC1_Type *)CONNECTIVITY__LPCG_USDHC1_BASE)
+/** Array initializer of CONNECTIVITY_LPCG_USDHC1 peripheral base addresses */
+#define CONNECTIVITY_LPCG_USDHC1_BASE_ADDRS      { CONNECTIVITY__LPCG_USDHC1_BASE }
+/** Array initializer of CONNECTIVITY_LPCG_USDHC1 peripheral base pointers */
+#define CONNECTIVITY_LPCG_USDHC1_BASE_PTRS       { CONNECTIVITY__LPCG_USDHC1 }
+
+/*!
+ * @}
+ */ /* end of group CONNECTIVITY_LPCG_USDHC1_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DC_LPCG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DC_LPCG_Peripheral_Access_Layer DC_LPCG Peripheral Access Layer
+ * @{
+ */
+
+/** DC_LPCG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t LPCG_DC_LPCG_0;                    /**< na, offset: 0x0 */
+  __IO uint32_t LPCG_DC_LPCG_4;                    /**< na, offset: 0x4 */
+  __IO uint32_t LPCG_DC_LPCG_8;                    /**< na, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t LPCG_DC_LPCG_16;                   /**< na, offset: 0x10 */
+  __IO uint32_t LPCG_DC_LPCG_20;                   /**< na, offset: 0x14 */
+  __IO uint32_t LPCG_DC_LPCG_24;                   /**< na, offset: 0x18 */
+  __IO uint32_t LPCG_DC_LPCG_28;                   /**< na, offset: 0x1C */
+  __IO uint32_t LPCG_DC_LPCG_32;                   /**< na, offset: 0x20 */
+  __IO uint32_t LPCG_DC_LPCG_36;                   /**< na, offset: 0x24 */
+  __IO uint32_t LPCG_DC_LPCG_40;                   /**< na, offset: 0x28 */
+  __IO uint32_t LPCG_DC_LPCG_44;                   /**< na, offset: 0x2C */
+  __IO uint32_t LPCG_DC_LPCG_48;                   /**< na, offset: 0x30 */
+  __IO uint32_t LPCG_DC_LPCG_52;                   /**< na, offset: 0x34 */
+  __IO uint32_t LPCG_DC_LPCG_56;                   /**< na, offset: 0x38 */
+  __IO uint32_t LPCG_DC_LPCG_60;                   /**< na, offset: 0x3C */
+  __IO uint32_t LPCG_DC_LPCG_64;                   /**< na, offset: 0x40 */
+  __IO uint32_t LPCG_DC_LPCG_68;                   /**< na, offset: 0x44 */
+  __IO uint32_t LPCG_DC_LPCG_72;                   /**< na, offset: 0x48 */
+} DC_LPCG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DC_LPCG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DC_LPCG_Register_Masks DC_LPCG Register Masks
+ * @{
+ */
+
+/*! @name LPCG_DC_LPCG_0 - na */
+/*! @{ */
+#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_MASK (0x1U)
+#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_SHIFT (0U)
+/*! LPCG_dc_lpcg_0_reserved_0_0 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_MASK (0x2U)
+#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_SHIFT (1U)
+/*! dsp0_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN(x)  (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_MASK (0x4U)
+#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_SHIFT (2U)
+/*! LPCG_dc_lpcg_0_reserved_2_2 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_MASK (0x8U)
+#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_SHIFT (3U)
+/*! dsp0_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP(x)  (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_MASK (0x10U)
+#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_SHIFT (4U)
+/*! LPCG_dc_lpcg_0_reserved_4_4 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_MASK (0x20U)
+#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_SHIFT (5U)
+/*! dsp1_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN(x)  (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_MASK (0x40U)
+#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_SHIFT (6U)
+/*! LPCG_dc_lpcg_0_reserved_6_6 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_MASK (0x80U)
+#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_SHIFT (7U)
+/*! dsp1_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP(x)  (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_MASK (0xFFFFFF00U)
+#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_SHIFT (8U)
+/*! LPCG_dc_lpcg_0_reserved_8_31 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_MASK)
+/*! @} */
+
+/*! @name LPCG_DC_LPCG_4 - na */
+/*! @{ */
+#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_MASK (0xFFFFU)
+#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_SHIFT (0U)
+/*! LPCG_dc_lpcg_4_reserved_0_15 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_MASK (0x10000U)
+#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_SHIFT (16U)
+/*! lis_ipg_clk_HWEN - Hardware Enable
+ *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
+ *  0b1..Enable HW automatic gating
+ */
+#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_MASK (0x20000U)
+#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_SHIFT (17U)
+/*! lis_ipg_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_MASK (0x40000U)
+#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_SHIFT (18U)
+/*! LPCG_dc_lpcg_4_reserved_18_18 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_MASK (0x80000U)
+#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_SHIFT (19U)
+/*! lis_ipg_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_MASK (0xFFF00000U)
+#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_SHIFT (20U)
+/*! LPCG_dc_lpcg_4_reserved_20_31 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_MASK)
+/*! @} */
+
+/*! @name LPCG_DC_LPCG_8 - na */
+/*! @{ */
+#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_MASK (0xFFFFU)
+#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_SHIFT (0U)
+/*! LPCG_dc_lpcg_8_reserved_0_15 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_MASK (0x10000U)
+#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_SHIFT (16U)
+/*! display_ctrl_link_mst0_msi_clk_HWEN - Hardware Enable
+ *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
+ *  0b1..Enable HW automatic gating
+ */
+#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_MASK (0x20000U)
+#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_SHIFT (17U)
+/*! display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_MASK (0x40000U)
+#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_SHIFT (18U)
+/*! LPCG_dc_lpcg_8_reserved_18_18 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_MASK (0x80000U)
+#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_SHIFT (19U)
+/*! display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP - show clock root status, 1 means clock stopped
+ */
+#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_MASK (0xFFF00000U)
+#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_SHIFT (20U)
+/*! LPCG_dc_lpcg_8_reserved_20_31 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_MASK)
+/*! @} */
+
+/*! @name LPCG_DC_LPCG_16 - na */
+/*! @{ */
+#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_MASK (0xFFFFU)
+#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_SHIFT (0U)
+/*! LPCG_dc_lpcg_16_reserved_0_15 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_MASK (0x10000U)
+#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_SHIFT (16U)
+/*! pixel_combiner_apb_clk_HWEN - Hardware Enable
+ *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
+ *  0b1..Enable HW automatic gating
+ */
+#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_MASK (0x20000U)
+#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_SHIFT (17U)
+/*! pixel_combiner_apb_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_MASK (0x40000U)
+#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_SHIFT (18U)
+/*! LPCG_dc_lpcg_16_reserved_18_18 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_MASK (0x80000U)
+#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_SHIFT (19U)
+/*! pixel_combiner_apb_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_MASK (0xFFF00000U)
+#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_SHIFT (20U)
+/*! LPCG_dc_lpcg_16_reserved_20_31 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_MASK)
+/*! @} */
+
+/*! @name LPCG_DC_LPCG_20 - na */
+/*! @{ */
+#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_MASK (0xFFFFU)
+#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_SHIFT (0U)
+/*! LPCG_dc_lpcg_20_reserved_0_15 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_MASK (0x10000U)
+#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_SHIFT (16U)
+/*! iris_mvpl_cfg_clk_HWEN - Hardware Enable
+ *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
+ *  0b1..Enable HW automatic gating
+ */
+#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_MASK (0x20000U)
+#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_SHIFT (17U)
+/*! iris_mvpl_cfg_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_MASK (0x40000U)
+#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_SHIFT (18U)
+/*! LPCG_dc_lpcg_20_reserved_18_18 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_MASK (0x80000U)
+#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_SHIFT (19U)
+/*! iris_mvpl_cfg_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_MASK (0x100000U)
+#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_SHIFT (20U)
+/*! LPCG_dc_lpcg_20_reserved_20_20 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_MASK (0x200000U)
+#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_SHIFT (21U)
+/*! iris_mvpl_axi_clk_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_MASK (0x400000U)
+#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_SHIFT (22U)
+/*! LPCG_dc_lpcg_20_reserved_22_22 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_MASK (0x800000U)
+#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_SHIFT (23U)
+/*! iris_mvpl_axi_clk_STOP - show clock root status, 1 means clock stopped
+ */
+#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_MASK (0xFF000000U)
+#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_SHIFT (24U)
+/*! LPCG_dc_lpcg_20_reserved_24_31 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_MASK)
+/*! @} */
+
+/*! @name LPCG_DC_LPCG_24 - na */
+/*! @{ */
+#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_MASK (0xFFFFU)
+#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_SHIFT (0U)
+/*! LPCG_dc_lpcg_24_reserved_0_15 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_MASK (0x10000U)
+#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_SHIFT (16U)
+/*! dpr0_dpr_apb_clkg_HWEN - Hardware Enable
+ *  0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
+ *  0b1..Enable HW automatic gating
+ */
+#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_MASK (0x20000U)
+#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_SHIFT (17U)
+/*! dpr0_dpr_apb_clkg_SWEN - Software Enable
+ *  0b0..Disable SW clock regardless of HWEN
+ *  0b1..Enable SW clock gating
+ */
+#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_MASK (0x40000U)
+#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_SHIFT (18U)
+/*! LPCG_dc_lpcg_24_reserved_18_18 - reserved
+ */
+#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_MASK)
+#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_MASK (0x80000U)
+#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_SHIFT (19U)
+/*! dpr0_dpr_apb_clkg_STOP - show clock root status, 1 means clock stopped
+ */
+#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_MASK)