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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX5/MIMX8UX5_cm4.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX5/MIMX8UX5_cm4.h
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index 000000000..43b0d3a50
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+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX5/MIMX8UX5_cm4.h
@@ -0,0 +1,144416 @@
1/*
2** ###################################################################
3** Processors: MIMX8UX5AVLFZ
4** MIMX8UX5AVOFZ
5** MIMX8UX5CVLDZ
6**
7** Compilers: GNU C Compiler
8** IAR ANSI C/C++ Compiler for ARM
9** Keil ARM C/C++ Compiler
10**
11** Reference manual: IMX8DQXPRM, Rev. E, 6/2019
12** Version: rev. 4.0, 2020-06-19
13** Build: b200825
14**
15** Abstract:
16** CMSIS Peripheral Access Layer for MIMX8UX5_cm4
17**
18** Copyright 1997-2016 Freescale Semiconductor, Inc.
19** Copyright 2016-2020 NXP
20** All rights reserved.
21**
22** SPDX-License-Identifier: BSD-3-Clause
23**
24** http: www.nxp.com
25** mail: [email protected]
26**
27** Revisions:
28** - rev. 1.0 (2016-06-02)
29** Initial version.
30** - rev. 2.0 (2017-08-23)
31** RevA Header EAR
32** - rev. 3.0 (2018-08-22)
33** RevB Header EAR
34** - rev. 4.0 (2020-06-19)
35** RevC Header RFP
36**
37** ###################################################################
38*/
39
40/*!
41 * @file MIMX8UX5_cm4.h
42 * @version 4.0
43 * @date 2020-06-19
44 * @brief CMSIS Peripheral Access Layer for MIMX8UX5_cm4
45 *
46 * CMSIS Peripheral Access Layer for MIMX8UX5_cm4
47 */
48
49#ifndef _MIMX8UX5_CM4_H_
50#define _MIMX8UX5_CM4_H_ /**< Symbol preventing repeated inclusion */
51
52/** Memory map major version (memory maps with equal major version number are
53 * compatible) */
54#define MCU_MEM_MAP_VERSION 0x0400U
55/** Memory map minor version */
56#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
57
58
59/* ----------------------------------------------------------------------------
60 -- Interrupt vector numbers
61 ---------------------------------------------------------------------------- */
62
63/*!
64 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
65 * @{
66 */
67
68/** Interrupt Number Definitions */
69#define NUMBER_OF_INT_VECTORS 611 /**< Number of interrupts in the Vector table */
70
71typedef enum IRQn {
72 /* Auxiliary constants */
73 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
74
75 /* Core interrupts */
76 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
77 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
78 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
79 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
80 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
81 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
82 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
83 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
84 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
85
86 /* Device specific interrupts */
87 Reserved16_IRQn = 0, /**< Reserved */
88 Reserved17_IRQn = 1, /**< Reserved */
89 Reserved18_IRQn = 2, /**< Reserved */
90 Reserved19_IRQn = 3, /**< Reserved */
91 Reserved20_IRQn = 4, /**< Reserved */
92 M4_MCM_IRQn = 5, /**< MCM IRQ */
93 Reserved22_IRQn = 6, /**< Reserved */
94 Reserved23_IRQn = 7, /**< Reserved */
95 Reserved24_IRQn = 8, /**< Reserved */
96 Reserved25_IRQn = 9, /**< Reserved */
97 Reserved26_IRQn = 10, /**< Reserved */
98 Reserved27_IRQn = 11, /**< Reserved */
99 Reserved28_IRQn = 12, /**< Reserved */
100 Reserved29_IRQn = 13, /**< Reserved */
101 Reserved30_IRQn = 14, /**< Reserved */
102 Reserved31_IRQn = 15, /**< Reserved */
103 Reserved32_IRQn = 16, /**< Reserved */
104 Reserved33_IRQn = 17, /**< Reserved */
105 Reserved34_IRQn = 18, /**< Reserved */
106 M4_TPM_IRQn = 19, /**< Timer PWM Module */
107 Reserved36_IRQn = 20, /**< Reserved */
108 Reserved37_IRQn = 21, /**< Reserved */
109 M4_LPIT_IRQn = 22, /**< Low-Power Periodic Interrupt Timer */
110 Reserved39_IRQn = 23, /**< Reserved */
111 Reserved40_IRQn = 24, /**< Reserved */
112 M4_LPUART_IRQn = 25, /**< Low Power UART */
113 Reserved42_IRQn = 26, /**< Reserved */
114 M4_LPI2C_IRQn = 27, /**< Low-Power I2C - Logical OR of master and slave interrupts */
115 Reserved44_IRQn = 28, /**< Reserved */
116 M4_MU0_B0_IRQn = 29, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 0, Logical OR of all general-purpose, TX, and RX interrupts */
117 Reserved46_IRQn = 30, /**< Reserved */
118 Reserved47_IRQn = 31, /**< Reserved */
119 IRQSTEER_0_IRQn = 32, /**< External interrupt 0 */
120 IRQSTEER_1_IRQn = 33, /**< External interrupt 1 */
121 IRQSTEER_2_IRQn = 34, /**< External interrupt 2 */
122 IRQSTEER_3_IRQn = 35, /**< External interrupt 3 */
123 IRQSTEER_4_IRQn = 36, /**< External interrupt 4 */
124 IRQSTEER_5_IRQn = 37, /**< External interrupt 5 */
125 IRQSTEER_6_IRQn = 38, /**< External interrupt 6 */
126 IRQSTEER_7_IRQn = 39, /**< External interrupt 7 */
127 Reserved56_IRQn = 40, /**< Reserved */
128 Reserved57_IRQn = 41, /**< Reserved */
129 Reserved58_IRQn = 42, /**< Reserved */
130 Reserved59_IRQn = 43, /**< Reserved */
131 M4_MU0_B1_IRQn = 44, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 1, Logical OR of all general-purpose, TX, and RX interrupts */
132 M4_MU0_B2_IRQn = 45, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 2, Logical OR of all general-purpose, TX, and RX interrupts */
133 M4_MU0_B3_IRQn = 46, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 3, Logical OR of all general-purpose, TX, and RX interrupts */
134 Reserved63_IRQn = 47, /**< Reserved */
135 Reserved64_IRQn = 48, /**< Reserved */
136 M4_MU1_A_IRQn = 49, /**< Messaging Unit 1 (IPC with System Controller) - Side A (MCU), Logical OR of all general-purpose, TX, and RX interrupts */
137 M4_SW_IRQn = 50, /**< Software interrupt (asserted/cleared via NVIC registers, INTISR[50] input tied low) */
138 A35_NINTERRIRQ_IRQn = 83, /**< Shared Int Source nINTERRIRQ from A35 Sub-System */
139 A35_NEXTERRIRQ_IRQn = 84, /**< Shared Int Source nEXTERRIRQ from A35 Sub-System */
140 M4_INT_OUT0_IRQn = 99, /**< Shared Int Source INT_OUT[0] from M4 Sub-System */
141 M4_INT_OUT1_IRQn = 100, /**< Shared Int Source INT_OUT[1] from M4 Sub-System */
142 M4_INT_OUT2_IRQn = 101, /**< Shared Int Source INT_OUT[2] from M4 Sub-System */
143 M4_INT_OUT3_IRQn = 102, /**< Shared Int Source INT_OUT[3] from M4 Sub-System */
144 M4_INT_OUT4_IRQn = 103, /**< Shared Int Source INT_OUT[4] from M4 Sub-System */
145 M4_INT_OUT5_IRQn = 104, /**< Shared Int Source INT_OUT[5] from M4 Sub-System */
146 M4_INT_OUT6_IRQn = 105, /**< Shared Int Source INT_OUT[6] from M4 Sub-System */
147 M4_INT_OUT7_IRQn = 106, /**< Shared Int Source INT_OUT[7] from M4 Sub-System */
148 DISPLAY0_INT_OUT0_IRQn = 123, /**< Shared Int Source INT_OUT[0] from Display0 Sub-System */
149 DISPLAY0_INT_OUT1_IRQn = 124, /**< Shared Int Source INT_OUT[1] from Display0 Sub-System */
150 DISPLAY0_INT_OUT2_IRQn = 125, /**< Shared Int Source INT_OUT[2] from Display0 Sub-System */
151 DISPLAY0_INT_OUT3_IRQn = 126, /**< Shared Int Source INT_OUT[3] from Display0 Sub-System */
152 DISPLAY0_INT_OUT4_IRQn = 127, /**< Shared Int Source INT_OUT[4] from Display0 Sub-System */
153 DISPLAY0_INT_OUT5_IRQn = 128, /**< Shared Int Source INT_OUT[5] from Display0 Sub-System */
154 DISPLAY0_INT_OUT6_IRQn = 129, /**< Shared Int Source INT_OUT[6] from Display0 Sub-System */
155 DISPLAY0_INT_OUT7_IRQn = 130, /**< Shared Int Source INT_OUT[7] from Display0 Sub-System */
156 DISPLAY0_RESERVED_IRQn = 131, /**< Shared Int Source Reserved from Display0 Sub-System */
157 DISPLAY0_INT_OUT9_IRQn = 132, /**< Shared Int Source INT_OUT[9] from Display0 Sub-System */
158 DISPLAY0_INT_OUT10_IRQn = 133, /**< Shared Int Source INT_OUT[10] from Display0 Sub-System */
159 DISPLAY0_INT_OUT11_IRQn = 134, /**< Shared Int Source INT_OUT[11] from Display0 Sub-System */
160 DISPLAY0_INT_OUT12_IRQn = 135, /**< Shared Int Source INT_OUT[12] from Display0 Sub-System */
161 MIPI_DSI0_INT_OUT_IRQn = 142, /**< Shared Int Source INT_OUT from MIPI_DSI0 Sub-System */
162 MIPI_DSI1_INT_OUT_IRQn = 143, /**< Shared Int Source INT_OUT from MIPI_DSI1 Sub-System */
163 LCD_MOD_INT_IRQn = 145, /**< Shared Int Source INT_OUT from ADMA Sub-System */
164 LCD_PWM_INT_IRQn = 146, /**< Shared Int Source INT_OUT from ADMA Sub-System */
165 GPU0_XAQ2_INTR_IRQn = 147, /**< Shared Int Source xaq2_intr from GPU0 Sub-System */
166 ADMA_EDMA2_INT_IRQn = 149, /**< Shared Int Source eDMA2_INT from ADMA Sub-System */
167 ADMA_EDMA2_ERR_INT_IRQn = 150, /**< Shared Int Source eDMA2_ERR_INT from ADMA Sub-System */
168 ADMA_EDMA3_INT_IRQn = 151, /**< Shared Int Source eDMA3_INT from ADMA Sub-System */
169 ADMA_EDMA3_ERR_INT_IRQn = 152, /**< Shared Int Source eDMA3_ERR_INT from ADMA Sub-System */
170 LSIO_GPT0_INT_IRQn = 163, /**< Shared Int Source GPT0_INT from LSIO Sub-System */
171 LSIO_GPT1_INT_IRQn = 164, /**< Shared Int Source GPT1_INT from LSIO Sub-System */
172 LSIO_GPT2_INT_IRQn = 165, /**< Shared Int Source GPT2_INT from LSIO Sub-System */
173 LSIO_GPT3_INT_IRQn = 166, /**< Shared Int Source GPT3_INT from LSIO Sub-System */
174 LSIO_GPT4_INT_IRQn = 167, /**< Shared Int Source GPT4_INT from LSIO Sub-System */
175 LSIO_KPP_INT_IRQn = 168, /**< Shared Int Source KPP_INT from LSIO Sub-System */
176 LSIO_OCTASPI0_INT_IRQn = 175, /**< Shared Int Source OctaSPI0_INT from LSIO Sub-System */
177 LSIO_OCTASPI1_INT_IRQn = 176, /**< Shared Int Source OctaSPI1_INT from LSIO Sub-System */
178 LSIO_PWM0_INT_IRQn = 177, /**< Shared Int Source PWM0_INT from LSIO Sub-System */
179 LSIO_PWM1_INT_IRQn = 178, /**< Shared Int Source PWM1_INT from LSIO Sub-System */
180 LSIO_PWM2_INT_IRQn = 179, /**< Shared Int Source PWM2_INT from LSIO Sub-System */
181 LSIO_PWM3_INT_IRQn = 180, /**< Shared Int Source PWM3_INT from LSIO Sub-System */
182 LSIO_PWM4_INT_IRQn = 181, /**< Shared Int Source PWM4_INT from LSIO Sub-System */
183 LSIO_PWM5_INT_IRQn = 182, /**< Shared Int Source PWM5_INT from LSIO Sub-System */
184 LSIO_PWM6_INT_IRQn = 183, /**< Shared Int Source PWM6_INT from LSIO Sub-System */
185 LSIO_PWM7_INT_IRQn = 184, /**< Shared Int Source PWM7_INT from LSIO Sub-System */
186 HSIO_PCIEB_MSI_CTRL_INT_IRQn = 185, /**< Shared Int Source PCIeB_MSI_CTRL_INT from HSIO Sub-System */
187 HSIO_PCIEB_CLK_REQ_INT_IRQn = 186, /**< Shared Int Source PCIeB_CLK_REQ_INT from HSIO Sub-System */
188 HSIO_PCIEB_DMA_INT_IRQn = 187, /**< Shared Int Source PCIeB_DMA_INT from HSIO Sub-System */
189 HSIO_PCIEB_INT_D_IRQn = 188, /**< Shared Int Source PCIeB_INT_D from HSIO Sub-System */
190 HSIO_PCIEB_INT_C_IRQn = 189, /**< Shared Int Source PCIeB_INT_C from HSIO Sub-System */
191 HSIO_PCIEB_INT_B_IRQn = 190, /**< Shared Int Source PCIeB_INT_B from HSIO Sub-System */
192 HSIO_PCIEB_INT_A_IRQn = 191, /**< Shared Int Source PCIeB_INT_A from HSIO Sub-System */
193 HSIO_PCIEB_SMLH_REQ_RST_IRQn = 192, /**< Shared Int Source PCIeB_SMLH_REQ_RST from HSIO Sub-System */
194 HSIO_PCIEB_GPIO_WAKEUP0_IRQn = 193, /**< Shared Int Source PCIeB_GPIO_WAKEUP[0] from HSIO Sub-System */
195 HSIO_PCIEB_GPIO_WAKEUP1_IRQn = 194, /**< Shared Int Source PCIeB_GPIO_WAKEUP[1] from HSIO Sub-System */
196 SCU_INT_OUT0_IRQn = 195, /**< Shared Int Source INT_OUT[0] from SCU Sub-System */
197 SCU_INT_OUT1_IRQn = 196, /**< Shared Int Source INT_OUT[1] from SCU Sub-System */
198 SCU_INT_OUT2_IRQn = 197, /**< Shared Int Source INT_OUT[2] from SCU Sub-System */
199 SCU_INT_OUT3_IRQn = 198, /**< Shared Int Source INT_OUT[3] from SCU Sub-System */
200 SCU_INT_OUT4_IRQn = 199, /**< Shared Int Source INT_OUT[4] from SCU Sub-System */
201 SCU_INT_OUT5_IRQn = 200, /**< Shared Int Source INT_OUT[5] from SCU Sub-System */
202 SCU_INT_OUT6_IRQn = 201, /**< Shared Int Source INT_OUT[6] from SCU Sub-System */
203 SCU_INT_OUT7_IRQn = 202, /**< Shared Int Source INT_OUT[7] from SCU Sub-System */
204 SCU_SYS_COUNT_INT0_IRQn = 203, /**< Shared Int Source SYS_COUNT_INT0 from SCU Sub-System */
205 SCU_SYS_COUNT_INT1_IRQn = 204, /**< Shared Int Source SYS_COUNT_INT1 from SCU Sub-System */
206 SCU_SYS_COUNT_INT2_IRQn = 205, /**< Shared Int Source SYS_COUNT_INT2 from SCU Sub-System */
207 SCU_SYS_COUNT_INT3_IRQn = 206, /**< Shared Int Source SYS_COUNT_INT3 from SCU Sub-System */
208 DRC_ECC_CORRECT_INT_IRQn = 211, /**< Shared Int Source ECC_CORRECT_INT from DRC Sub-System */
209 DRC_ECC_NCORRECT_INT_IRQn = 212, /**< Shared Int Source ECC_NCORRECT_INT from DRC Sub-System */
210 DRC_SBR_DONE_INT_IRQn = 213, /**< Shared Int Source SBR_DONE_INT from DRC Sub-System */
211 DRC_PERF_CNT_INT_IRQn = 214, /**< Shared Int Source PERF_CNT_INT from DRC Sub-System */
212 LSIO_GPIO_INT0_IRQn = 219, /**< Shared Int Source GPIO_INT[0] from LSIO Sub-System */
213 LSIO_GPIO_INT1_IRQn = 220, /**< Shared Int Source GPIO_INT[1] from LSIO Sub-System */
214 LSIO_GPIO_INT2_IRQn = 221, /**< Shared Int Source GPIO_INT[2] from LSIO Sub-System */
215 LSIO_GPIO_INT3_IRQn = 222, /**< Shared Int Source GPIO_INT[3] from LSIO Sub-System */
216 LSIO_GPIO_INT4_IRQn = 223, /**< Shared Int Source GPIO_INT[4] from LSIO Sub-System */
217 LSIO_GPIO_INT5_IRQn = 224, /**< Shared Int Source GPIO_INT[5] from LSIO Sub-System */
218 LSIO_GPIO_INT6_IRQn = 225, /**< Shared Int Source GPIO_INT[6] from LSIO Sub-System */
219 LSIO_GPIO_INT7_IRQn = 226, /**< Shared Int Source GPIO_INT[7] from LSIO Sub-System */
220 LSIO_MU0_INT_IRQn = 259, /**< Shared Int Source MU0_INT from LSIO Sub-System */
221 LSIO_MU1_INT_IRQn = 260, /**< Shared Int Source MU1_INT from LSIO Sub-System */
222 LSIO_MU2_INT_IRQn = 261, /**< Shared Int Source MU2_INT from LSIO Sub-System */
223 LSIO_MU3_INT_IRQn = 262, /**< Shared Int Source MU3_INT from LSIO Sub-System */
224 LSIO_MU4_INT_IRQn = 263, /**< Shared Int Source MU4_INT from LSIO Sub-System */
225 LSIO_MU5_INT_A_IRQn = 267, /**< Shared Int Source MU5_INT_A from LSIO Sub-System */
226 LSIO_MU6_INT_A_IRQn = 268, /**< Shared Int Source MU6_INT_A from LSIO Sub-System */
227 LSIO_MU7_INT_A_IRQn = 269, /**< Shared Int Source MU7_INT_A from LSIO Sub-System */
228 LSIO_MU8_INT_A_IRQn = 270, /**< Shared Int Source MU8_INT_A from LSIO Sub-System */
229 LSIO_MU9_INT_A_IRQn = 271, /**< Shared Int Source MU9_INT_A from LSIO Sub-System */
230 LSIO_MU10_INT_A_IRQn = 272, /**< Shared Int Source MU10_INT_A from LSIO Sub-System */
231 LSIO_MU11_INT_A_IRQn = 273, /**< Shared Int Source MU11_INT_A from LSIO Sub-System */
232 LSIO_MU12_INT_A_IRQn = 274, /**< Shared Int Source MU12_INT_A from LSIO Sub-System */
233 LSIO_MU13_INT_A_IRQn = 275, /**< Shared Int Source MU13_INT_A from LSIO Sub-System */
234 LSIO_MU5_INT_B_IRQn = 283, /**< Shared Int Source MU5_INT_B from LSIO Sub-System */
235 LSIO_MU6_INT_B_IRQn = 284, /**< Shared Int Source MU6_INT_B from LSIO Sub-System */
236 LSIO_MU7_INT_B_IRQn = 285, /**< Shared Int Source MU7_INT_B from LSIO Sub-System */
237 LSIO_MU8_INT_B_IRQn = 286, /**< Shared Int Source MU8_INT_B from LSIO Sub-System */
238 LSIO_MU9_INT_B_IRQn = 287, /**< Shared Int Source MU9_INT_B from LSIO Sub-System */
239 LSIO_MU10_INT_B_IRQn = 288, /**< Shared Int Source MU10_INT_B from LSIO Sub-System */
240 LSIO_MU11_INT_B_IRQn = 289, /**< Shared Int Source MU11_INT_B from LSIO Sub-System */
241 LSIO_MU12_INT_B_IRQn = 290, /**< Shared Int Source MU12_INT_B from LSIO Sub-System */
242 LSIO_MU13_INT_B_IRQn = 291, /**< Shared Int Source MU13_INT_B from LSIO Sub-System */
243 ADMA_SPI0_INT_IRQn = 299, /**< Shared Int Source SPI0_INT from ADMA Sub-System */
244 ADMA_SPI1_INT_IRQn = 300, /**< Shared Int Source SPI1_INT from ADMA Sub-System */
245 ADMA_SPI2_INT_IRQn = 301, /**< Shared Int Source SPI2_INT from ADMA Sub-System */
246 ADMA_SPI3_INT_IRQn = 302, /**< Shared Int Source SPI3_INT from ADMA Sub-System */
247 ADMA_I2C0_INT_IRQn = 303, /**< Shared Int Source I2C0_INT from ADMA Sub-System */
248 ADMA_I2C1_INT_IRQn = 304, /**< Shared Int Source I2C1_INT from ADMA Sub-System */
249 ADMA_I2C2_INT_IRQn = 305, /**< Shared Int Source I2C2_INT from ADMA Sub-System */
250 ADMA_I2C3_INT_IRQn = 306, /**< Shared Int Source I2C3_INT from ADMA Sub-System */
251 ADMA_UART0_INT_IRQn = 308, /**< Shared Int Source UART0_INT from ADMA Sub-System */
252 ADMA_UART1_INT_IRQn = 309, /**< Shared Int Source UART1_INT from ADMA Sub-System */
253 ADMA_UART2_INT_IRQn = 310, /**< Shared Int Source UART2_INT from ADMA Sub-System */
254 ADMA_UART3_INT_IRQn = 311, /**< Shared Int Source UART3_INT from ADMA Sub-System */
255 CONNECTIVITY_USDHC0_INT_IRQn = 315, /**< Shared Int Source uSDHC0_INT from Connectivity Sub-System */
256 CONNECTIVITY_USDHC1_INT_IRQn = 316, /**< Shared Int Source uSDHC1_INT from Connectivity Sub-System */
257 CONNECTIVITY_USDHC2_INT_IRQn = 317, /**< Shared Int Source uSDHC2_INT from Connectivity Sub-System */
258 ADMA_FLEXCAN0_INT_IRQn = 318, /**< Shared Int Source FlexCAN0_INT from ADMA Sub-System */
259 ADMA_FLEXCAN1_INT_IRQn = 319, /**< Shared Int Source FlexCAN1_INT from ADMA Sub-System */
260 ADMA_FLEXCAN2_INT_IRQn = 320, /**< Shared Int Source FlexCAN2_INT from ADMA Sub-System */
261 ADMA_FTM0_INT_IRQn = 321, /**< Shared Int Source FTM0_INT from ADMA Sub-System */
262 ADMA_FTM1_INT_IRQn = 322, /**< Shared Int Source FTM1_INT from ADMA Sub-System */
263 ADMA_ADC0_INT_IRQn = 323, /**< Shared Int Source ADC0_INT from ADMA Sub-System */
264 ADMA_EXTERNAL_DMA_INT_0_IRQn = 325, /**< Shared Int Source EXTERNAL_DMA_INT_0 from ADMA Sub-System */
265 ADMA_EXTERNAL_DMA_INT_1_IRQn = 326, /**< Shared Int Source EXTERNAL_DMA_INT_1 from ADMA Sub-System */
266 ADMA_EXTERNAL_DMA_INT_2_IRQn = 327, /**< Shared Int Source EXTERNAL_DMA_INT_2 from ADMA Sub-System */
267 ADMA_EXTERNAL_DMA_INT_3_IRQn = 328, /**< Shared Int Source EXTERNAL_DMA_INT_3 from ADMA Sub-System */
268 ADMA_EXTERNAL_DMA_INT_4_IRQn = 329, /**< Shared Int Source EXTERNAL_DMA_INT_4 from ADMA Sub-System */
269 ADMA_EXTERNAL_DMA_INT_5_IRQn = 330, /**< Shared Int Source EXTERNAL_DMA_INT_5 from ADMA Sub-System */
270 CONNECTIVITY_ENET0_FRAME1_INT_IRQn = 339, /**< Shared Int Source ENET0_FRAME1_INT from Connectivity Sub-System */
271 CONNECTIVITY_ENET0_FRAME2_INT_IRQn = 340, /**< Shared Int Source ENET0_FRAME2_INT from Connectivity Sub-System */
272 CONNECTIVITY_ENET0_FRAME0_EVENT_INT_IRQn = 341, /**< Shared Int Source ENET0_FRAME0_EVENT_INT from Connectivity Sub-System */
273 CONNECTIVITY_ENET0_TIMER_INT_IRQn = 342, /**< Shared Int Source ENET0_TIMER_INT from Connectivity Sub-System */
274 CONNECTIVITY_ENET1_FRAME1_INT_IRQn = 343, /**< Shared Int Source ENET1_FRAME1_INT from Connectivity Sub-System */
275 CONNECTIVITY_ENET1_FRAME2_INT_IRQn = 344, /**< Shared Int Source ENET1_FRAME2_INT from Connectivity Sub-System */
276 CONNECTIVITY_ENET1_FRAME0_EVENT_INT_IRQn = 345, /**< Shared Int Source ENET1_FRAME0_EVENT_INT from Connectivity Sub-System */
277 CONNECTIVITY_ENET1_TIMER_INT_IRQn = 346, /**< Shared Int Source ENET1_TIMER_INT from Connectivity Sub-System */
278 CONNECTIVITY_DTCP_INT_IRQn = 347, /**< Shared Int Source DTCP_INT from Connectivity Sub-System */
279 CONNECTIVITY_MLB_INT_IRQn = 348, /**< Shared Int Source MLB_INT from Connectivity Sub-System */
280 CONNECTIVITY_MLB_AHB_INT_IRQn = 349, /**< Shared Int Source MLB_AHB_INT from Connectivity Sub-System */
281 CONNECTIVITY_USB_OTG_INT_IRQn = 350, /**< Shared Int Source USB_OTG_INT from Connectivity Sub-System */
282 CONNECTIVITY_USB_HOST_INT_IRQn = 351, /**< Shared Int Source USB_HOST_INT from Connectivity Sub-System */
283 CONNECTIVITY_UTMI_INT_IRQn = 352, /**< Shared Int Source UTMI_INT from Connectivity Sub-System */
284 CONNECTIVITY_WAKEUP_INT_IRQn = 353, /**< Shared Int Source WAKEUP_INT from Connectivity Sub-System */
285 CONNECTIVITY_USB3_INT_IRQn = 354, /**< Shared Int Source USB3_INT from Connectivity Sub-System */
286 CONNECTIVITY_ND_FLASH_BCH_INT_IRQn = 355, /**< Shared Int Source ND_FLASH_BCH_INT from Connectivity Sub-System */
287 CONNECTIVITY_ND_FLASH_GPMI_INT_IRQn = 356, /**< Shared Int Source ND_FLASH_GPMI_INT from Connectivity Sub-System */
288 CONNECTIVITY_APBHDMA_IRQn = 357, /**< Shared Int Source APBHDMA from Connectivity Sub-System */
289 CONNECTIVITY_DMA_INT_IRQn = 358, /**< Shared Int Source DMA_INT from Connectivity Sub-System */
290 CONNECTIVITY_DMA_ERR_INT_IRQn = 359, /**< Shared Int Source DMA_ERR_INT from Connectivity Sub-System */
291 IMAGING_MSI_INT_IRQn = 371, /**< Shared Int Source MSI_INT from Imaging Sub-System */
292 IMAGING_PDMA_STREAM0_INT_IRQn = 380, /**< Shared Int Source PDMA_STREAM0_INT from Imaging Sub-System */
293 IMAGING_PDMA_STREAM1_INT_IRQn = 381, /**< Shared Int Source PDMA_STREAM1_INT from Imaging Sub-System */
294 IMAGING_PDMA_STREAM2_INT_IRQn = 382, /**< Shared Int Source PDMA_STREAM2_INT from Imaging Sub-System */
295 IMAGING_PDMA_STREAM3_INT_IRQn = 383, /**< Shared Int Source PDMA_STREAM3_INT from Imaging Sub-System */
296 IMAGING_PDMA_STREAM4_INT_IRQn = 384, /**< Shared Int Source PDMA_STREAM4_INT from Imaging Sub-System */
297 IMAGING_PDMA_STREAM5_INT_IRQn = 385, /**< Shared Int Source PDMA_STREAM5_INT from Imaging Sub-System */
298 IMAGING_PDMA_STREAM6_INT_IRQn = 386, /**< Shared Int Source PDMA_STREAM6_INT from Imaging Sub-System */
299 IMAGING_PDMA_STREAM7_INT_IRQn = 387, /**< Shared Int Source PDMA_STREAM7_INT from Imaging Sub-System */
300 IMAGING_MJPEG_ENC0_INT_IRQn = 388, /**< Shared Int Source MJPEG_ENC0_INT from Imaging Sub-System */
301 IMAGING_MJPEG_ENC1_INT_IRQn = 389, /**< Shared Int Source MJPEG_ENC1_INT from Imaging Sub-System */
302 IMAGING_MJPEG_ENC2_INT_IRQn = 390, /**< Shared Int Source MJPEG_ENC2_INT from Imaging Sub-System */
303 IMAGING_MJPEG_ENC3_INT_IRQn = 391, /**< Shared Int Source MJPEG_ENC3_INT from Imaging Sub-System */
304 IMAGING_MJPEG_DEC0_INT_IRQn = 392, /**< Shared Int Source MJPEG_DEC0_INT from Imaging Sub-System */
305 IMAGING_MJPEG_DEC1_INT_IRQn = 393, /**< Shared Int Source MJPEG_DEC1_INT from Imaging Sub-System */
306 IMAGING_MJPEG_DEC2_INT_IRQn = 394, /**< Shared Int Source MJPEG_DEC2_INT from Imaging Sub-System */
307 IMAGING_MJPEG_DEC3_INT_IRQn = 395, /**< Shared Int Source MJPEG_DEC3_INT from Imaging Sub-System */
308 ADMA_SAI0_MOD_INT_IRQn = 397, /**< Shared Int Source SAI0_MOD_INT from ADMA Sub-System */
309 ADMA_SAI0_DMA_INT_IRQn = 398, /**< Shared Int Source SAI0_DMA_INT from ADMA Sub-System */
310 ADMA_SAI1_MOD_INT_IRQn = 399, /**< Shared Int Source SAI1_MOD_INT from ADMA Sub-System */
311 ADMA_SAI1_DMA_INT_IRQn = 400, /**< Shared Int Source SAI1_DMA_INT from ADMA Sub-System */
312 ADMA_SAI2_MOD_INT_IRQn = 401, /**< Shared Int Source SAI2_MOD_INT from ADMA Sub-System */
313 ADMA_SAI2_DMA_INT_IRQn = 402, /**< Shared Int Source SAI2_DMA_INT from ADMA Sub-System */
314 MIPI_CSI0_OUT_INT_IRQn = 403, /**< Shared Int Source OUT_INT from MIPI_CSI0 Sub-System */
315 ADMA_SAI3_MOD_INT_IRQn = 406, /**< Shared Int Source SAI3_MOD_INT from ADMA Sub-System */
316 ADMA_SAI3_DMA_INT_IRQn = 407, /**< Shared Int Source SAI3_DMA_INT from ADMA Sub-System */
317 ADMA_SAI4_MOD_INT_IRQn = 412, /**< Shared Int Source SAI4_MOD_INT from ADMA Sub-System */
318 ADMA_SAI4_DMA_INT_IRQn = 413, /**< Shared Int Source SAI4_DMA_INT from ADMA Sub-System */
319 ADMA_SAI5_MOD_INT_IRQn = 414, /**< Shared Int Source SAI5_MOD_INT from ADMA Sub-System */
320 ADMA_SAI5_DMA_INT_IRQn = 415, /**< Shared Int Source SAI5_DMA_INT from ADMA Sub-System */
321 ADMA_SPI0_MOD_INT_IRQn = 419, /**< Shared Int Source SPI0_MOD_INT from ADMA Sub-System */
322 ADMA_SPI1_MOD_INT_IRQn = 420, /**< Shared Int Source SPI1_MOD_INT from ADMA Sub-System */
323 ADMA_SPI2_MOD_INT_IRQn = 421, /**< Shared Int Source SPI2_MOD_INT from ADMA Sub-System */
324 ADMA_SPI3_MOD_INT_IRQn = 422, /**< Shared Int Source SPI3_MOD_INT from ADMA Sub-System */
325 ADMA_I2C0_MOD_INT_IRQn = 423, /**< Shared Int Source I2C0_MOD_INT from ADMA Sub-System */
326 ADMA_I2C1_MOD_INT_IRQn = 424, /**< Shared Int Source I2C1_MOD_INT from ADMA Sub-System */
327 ADMA_I2C2_MOD_INT_IRQn = 425, /**< Shared Int Source I2C2_MOD_INT from ADMA Sub-System */
328 ADMA_I2C3_MOD_INT_IRQn = 426, /**< Shared Int Source I2C3_MOD_INT from ADMA Sub-System */
329 ADMA_UART0_MOD_INT_IRQn = 428, /**< Shared Int Source UART0_MOD_INT from ADMA Sub-System */
330 ADMA_UART1_MOD_INT_IRQn = 429, /**< Shared Int Source UART1_MOD_INT from ADMA Sub-System */
331 ADMA_UART2_MOD_INT_IRQn = 430, /**< Shared Int Source UART2_MOD_INT from ADMA Sub-System */
332 ADMA_UART3_MOD_INT_IRQn = 431, /**< Shared Int Source UART3_MOD_INT from ADMA Sub-System */
333 ADMA_FLEXCAN0_MOD_INT_IRQn = 435, /**< Shared Int Source FLEXCAN0_MOD_INT from ADMA Sub-System */
334 ADMA_FLEXCAN1_MOD_INT_IRQn = 436, /**< Shared Int Source FLEXCAN1_MOD_INT from ADMA Sub-System */
335 ADMA_FLEXCAN2_MOD_INT_IRQn = 437, /**< Shared Int Source FLEXCAN2_MOD_INT from ADMA Sub-System */
336 ADMA_FTM0_MOD_INT_IRQn = 438, /**< Shared Int Source FTM0_MOD_INT from ADMA Sub-System */
337 ADMA_FTM1_MOD_INT_IRQn = 439, /**< Shared Int Source FTM1_MOD_INT from ADMA Sub-System */
338 ADMA_ADC0_MOD_INT_IRQn = 440, /**< Shared Int Source ADC0_MOD_INT from ADMA Sub-System */
339 ADMA_FLEXCAN0_DMA_INT_IRQn = 442, /**< Shared Int Source FLEXCAN0_DMA_INT from ADMA Sub-System */
340 ADMA_FLEXCAN1_DMA_INT_IRQn = 443, /**< Shared Int Source FLEXCAN1_DMA_INT from ADMA Sub-System */
341 ADMA_FLEXCAN2_DMA_INT_IRQn = 444, /**< Shared Int Source FLEXCAN2_DMA_INT from ADMA Sub-System */
342 ADMA_FTM0_DMA_INT_IRQn = 445, /**< Shared Int Source FTM0_DMA_INT from ADMA Sub-System */
343 ADMA_FTM1_DMA_INT_IRQn = 446, /**< Shared Int Source FTM1_DMA_INT from ADMA Sub-System */
344 ADMA_ADC0_DMA_INT_IRQn = 447, /**< Shared Int Source ADC0_DMA_INT from ADMA Sub-System */
345 ADMA_EDMA0_INT_IRQn = 451, /**< Shared Int Source eDMA0_INT from ADMA Sub-System */
346 ADMA_EDMA0_ERR_INT_IRQn = 452, /**< Shared Int Source eDMA0_ERR_INT from ADMA Sub-System */
347 ADMA_EDMA1_INT_IRQn = 453, /**< Shared Int Source eDMA1_INT from ADMA Sub-System */
348 ADMA_EDMA1_ERR_INT_IRQn = 454, /**< Shared Int Source eDMA1_ERR_INT from ADMA Sub-System */
349 ADMA_ASRC0_INT1_IRQn = 455, /**< Shared Int Source ASRC0_INT1 from ADMA Sub-System */
350 ADMA_ASRC0_INT2_IRQn = 456, /**< Shared Int Source ASRC0_INT2 from ADMA Sub-System */
351 ADMA_DMA0_CH0_INT_IRQn = 457, /**< Shared Int Source DMA0_CH0_INT from ADMA Sub-System */
352 ADMA_DMA0_CH1_INT_IRQn = 458, /**< Shared Int Source DMA0_CH1_INT from ADMA Sub-System */
353 ADMA_DMA0_CH2_INT_IRQn = 459, /**< Shared Int Source DMA0_CH2_INT from ADMA Sub-System */
354 ADMA_DMA0_CH3_INT_IRQn = 460, /**< Shared Int Source DMA0_CH3_INT from ADMA Sub-System */
355 ADMA_DMA0_CH4_INT_IRQn = 461, /**< Shared Int Source DMA0_CH4_INT from ADMA Sub-System */
356 ADMA_DMA0_CH5_INT_IRQn = 462, /**< Shared Int Source DMA0_CH5_INT from ADMA Sub-System */
357 ADMA_ASRC1_INT1_IRQn = 463, /**< Shared Int Source ASRC1_INT1 from ADMA Sub-System */
358 ADMA_ASRC1_INT2_IRQn = 464, /**< Shared Int Source ASRC1_INT2 from ADMA Sub-System */
359 ADMA_DMA1_CH0_INT_IRQn = 465, /**< Shared Int Source DMA1_CH0_INT from ADMA Sub-System */
360 ADMA_DMA1_CH1_INT_IRQn = 466, /**< Shared Int Source DMA1_CH1_INT from ADMA Sub-System */
361 ADMA_DMA1_CH2_INT_IRQn = 467, /**< Shared Int Source DMA1_CH2_INT from ADMA Sub-System */
362 ADMA_DMA1_CH3_INT_IRQn = 468, /**< Shared Int Source DMA1_CH3_INT from ADMA Sub-System */
363 ADMA_DMA1_CH4_INT_IRQn = 469, /**< Shared Int Source DMA1_CH4_INT from ADMA Sub-System */
364 ADMA_DMA1_CH5_INT_IRQn = 470, /**< Shared Int Source DMA1_CH5_INT from ADMA Sub-System */
365 ADMA_ESAI0_INT_IRQn = 471, /**< Shared Int Source ESAI0_INT from ADMA Sub-System */
366 ADMA_GPT0_INT_IRQn = 474, /**< Shared Int Source GPT0_INT from ADMA Sub-System */
367 ADMA_GPT1_INT_IRQn = 475, /**< Shared Int Source GPT1_INT from ADMA Sub-System */
368 ADMA_GPT2_INT_IRQn = 476, /**< Shared Int Source GPT2_INT from ADMA Sub-System */
369 ADMA_GPT3_INT_IRQn = 477, /**< Shared Int Source GPT3_INT from ADMA Sub-System */
370 ADMA_GPT4_INT_IRQn = 478, /**< Shared Int Source GPT4_INT from ADMA Sub-System */
371 ADMA_GPT5_INT_IRQn = 479, /**< Shared Int Source GPT5_INT from ADMA Sub-System */
372 ADMA_SAI0_INT_IRQn = 480, /**< Shared Int Source SAI0_INT from ADMA Sub-System */
373 ADMA_SAI1_INT_IRQn = 481, /**< Shared Int Source SAI1_INT from ADMA Sub-System */
374 ADMA_SAI2_INT_IRQn = 482, /**< Shared Int Source SAI2_INT from ADMA Sub-System */
375 ADMA_SAI3_INT_IRQn = 483, /**< Shared Int Source SAI3_INT from ADMA Sub-System */
376 ADMA_SAI4_INT_IRQn = 486, /**< Shared Int Source SAI4_INT from ADMA Sub-System */
377 ADMA_SAI5_INT_IRQn = 487, /**< Shared Int Source SAI5_INT from ADMA Sub-System */
378 ADMA_SPDIF0_RX_INT_IRQn = 488, /**< Shared Int Source SPDIF0_RX_INT from ADMA Sub-System */
379 ADMA_SPDIF0_TX_INT_IRQn = 489, /**< Shared Int Source SPDIF0_TX_INT from ADMA Sub-System */
380 ADMA_ESAI0_MOD_INT_IRQn = 492, /**< Shared Int Source ESAI0_MOD_INT from ADMA Sub-System */
381 ADMA_ESAI0_DMA_INT_IRQn = 493, /**< Shared Int Source ESAI0_DMA_INT from ADMA Sub-System */
382 ADMA_SPI0_DMA_RX_INT_IRQn = 499, /**< Shared Int Source SPI0_DMA_RX_INT from ADMA Sub-System */
383 ADMA_SPI0_DMA_TX_INT_IRQn = 500, /**< Shared Int Source SPI0_DMA_TX_INT from ADMA Sub-System */
384 ADMA_SPI1_DMA_RX_INT_IRQn = 501, /**< Shared Int Source SPI1_DMA_RX_INT from ADMA Sub-System */
385 ADMA_SPI1_DMA_TX_INT_IRQn = 502, /**< Shared Int Source SPI1_DMA_TX_INT from ADMA Sub-System */
386 ADMA_SPI2_DMA_RX_INT_IRQn = 503, /**< Shared Int Source SPI2_DMA_RX_INT from ADMA Sub-System */
387 ADMA_SPI2_DMA_TX_INT_IRQn = 504, /**< Shared Int Source SPI2_DMA_TX_INT from ADMA Sub-System */
388 ADMA_SPI3_DMA_RX_INT_IRQn = 505, /**< Shared Int Source SPI3_DMA_RX_INT from ADMA Sub-System */
389 ADMA_SPI3_DMA_TX_INT_IRQn = 506, /**< Shared Int Source SPI3_DMA_TX_INT from ADMA Sub-System */
390 ADMA_I2C0_DMA_RX_INT_IRQn = 507, /**< Shared Int Source I2C0_DMA_RX_INT from ADMA Sub-System */
391 ADMA_I2C0_DMA_TX_INT_IRQn = 508, /**< Shared Int Source I2C0_DMA_TX_INT from ADMA Sub-System */
392 ADMA_I2C1_DMA_RX_INT_IRQn = 509, /**< Shared Int Source I2C1_DMA_RX_INT from ADMA Sub-System */
393 ADMA_I2C1_DMA_TX_INT_IRQn = 510, /**< Shared Int Source I2C1_DMA_TX_INT from ADMA Sub-System */
394 ADMA_I2C2_DMA_RX_INT_IRQn = 511, /**< Shared Int Source I2C2_DMA_RX_INT from ADMA Sub-System */
395 ADMA_I2C2_DMA_TX_INT_IRQn = 512, /**< Shared Int Source I2C2_DMA_TX_INT from ADMA Sub-System */
396 ADMA_I2C3_DMA_RX_INT_IRQn = 513, /**< Shared Int Source I2C3_DMA_RX_INT from ADMA Sub-System */
397 ADMA_I2C3_DMA_TX_INT_IRQn = 514, /**< Shared Int Source I2C3_DMA_TX_INT from ADMA Sub-System */
398 ADMA_UART0_DMA_RX_INT_IRQn = 517, /**< Shared Int Source UART0_DMA_RX_INT from ADMA Sub-System */
399 ADMA_UART0_DMA_TX_INT_IRQn = 518, /**< Shared Int Source UART0_DMA_TX_INT from ADMA Sub-System */
400 ADMA_UART1_DMA_RX_INT_IRQn = 519, /**< Shared Int Source UART1_DMA_RX_INT from ADMA Sub-System */
401 ADMA_UART1_DMA_TX_INT_IRQn = 520, /**< Shared Int Source UART1_DMA_TX_INT from ADMA Sub-System */
402 ADMA_UART2_DMA_RX_INT_IRQn = 521, /**< Shared Int Source UART2_DMA_RX_INT from ADMA Sub-System */
403 ADMA_UART2_DMA_TX_INT_IRQn = 522, /**< Shared Int Source UART2_DMA_TX_INT from ADMA Sub-System */
404 ADMA_UART3_DMA_RX_INT_IRQn = 523, /**< Shared Int Source UART3_DMA_RX_INT from ADMA Sub-System */
405 ADMA_UART3_DMA_TX_INT_IRQn = 524, /**< Shared Int Source UART3_DMA_TX_INT from ADMA Sub-System */
406 SECURITY_MU1_A_INT_IRQn = 531, /**< Shared Int Source MU1_A_INT from Security Sub-System */
407 SECURITY_MU2_A_INT_IRQn = 532, /**< Shared Int Source MU2_A_INT from Security Sub-System */
408 SECURITY_MU3_A_INT_IRQn = 533, /**< Shared Int Source MU3_A_INT from Security Sub-System */
409 SECURITY_CAAM_INT0_IRQn = 534, /**< Shared Int Source CAAM_INT0 from Security Sub-System */
410 SECURITY_CAAM_INT1_IRQn = 535, /**< Shared Int Source CAAM_INT1 from Security Sub-System */
411 SECURITY_CAAM_INT2_IRQn = 536, /**< Shared Int Source CAAM_INT2 from Security Sub-System */
412 SECURITY_CAAM_INT3_IRQn = 537, /**< Shared Int Source CAAM_INT3 from Security Sub-System */
413 SECURITY_CAAM_RTIC_INT_IRQn = 538, /**< Shared Int Source CAAM_RTIC_INT from Security Sub-System */
414 ADMA_SPDIF0_RX_MOD_INT_IRQn = 539, /**< Shared Int Source SPDIF0_RX_MOD_INT from ADMA Sub-System */
415 ADMA_SPDIF0_RX_DMA_INT_IRQn = 540, /**< Shared Int Source SPDIF0_RX_DMA_INT from ADMA Sub-System */
416 ADMA_SPDIF0_TX_MOD_INT_IRQn = 541, /**< Shared Int Source SPDIF0_TX_MOD_INT from ADMA Sub-System */
417 ADMA_SPDIF0_TX_DMA_INT_IRQn = 542, /**< Shared Int Source SPDIF0_TX_DMA_INT from ADMA Sub-System */
418 VPU_VPU_INT_0_IRQn = 547, /**< Shared Int Source VPU_INT_0 from VPU Sub-System */
419 VPU_VPU_INT_1_IRQn = 548, /**< Shared Int Source VPU_INT_1 from VPU Sub-System */
420 VPU_VPU_INT_2_IRQn = 549, /**< Shared Int Source VPU_INT_2 from VPU Sub-System */
421 VPU_VPU_INT_3_IRQn = 550, /**< Shared Int Source VPU_INT_3 from VPU Sub-System */
422 VPU_VPU_INT_4_IRQn = 551, /**< Shared Int Source VPU_INT_4 from VPU Sub-System */
423 M4_INTMUX_SOURCE_TPM_IRQn = 564, /**< INTMUX Input source: TPM Interrupt */
424 M4_INTMUX_SOURCE_LPIT_IRQn = 567, /**< INTMUX Input source: LPIT Interrupt */
425 M4_INTMUX_SOURCE_LPUART_IRQn = 570, /**< INTMUX Input source: LPUART Interrupt */
426 M4_INTMUX_SOURCE_LPI2C_IRQn = 572, /**< INTMUX Input source: LPI2C Interrupt */
427 M4_INTMUX_SOURCE_MU0_A3_IRQn = 591, /**< INTMUX Input source: MU0_A3 Interrupt */
428 M4_INTMUX_SOURCE_MU0_A2_IRQn = 592, /**< INTMUX Input source: MU0_A2 Interrupt */
429 M4_INTMUX_SOURCE_MU0_A1_IRQn = 593, /**< INTMUX Input source: MU0_A1 Interrupt */
430 M4_INTMUX_SOURCE_MU0_A0_IRQn = 594 /**< INTMUX Input source: MU0_A0 Interrupt */
431} IRQn_Type;
432
433/*!
434 * @}
435 */ /* end of group Interrupt_vector_numbers */
436
437
438/* ----------------------------------------------------------------------------
439 -- Configuration of the Cortex-M4 Processor and Core Peripherals
440 ---------------------------------------------------------------------------- */
441
442/*!
443 * @addtogroup Cortex_Core_Configuration Configuration of the Cortex-M4 Processor and Core Peripherals
444 * @{
445 */
446
447#define __CM4_REV 0x0001 /**< Core revision r0p1 */
448#define __MPU_PRESENT 1 /**< MPU present or not */
449#define __NVIC_PRIO_BITS 4 /**< Number of Bits used for Priority Levels */
450#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
451#define __FPU_PRESENT 1 /**< FPU present or not */
452
453#include "core_cm4.h" /* Core Peripheral Access Layer */
454#include "system_MIMX8UX5_cm4.h" /* Device specific configuration file */
455
456/*!
457 * @}
458 */ /* end of group Cortex_Core_Configuration */
459
460
461/* ----------------------------------------------------------------------------
462 -- Device Peripheral Access Layer
463 ---------------------------------------------------------------------------- */
464
465/*!
466 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
467 * @{
468 */
469
470
471/*
472** Start of section using anonymous unions
473*/
474
475#if defined(__ARMCC_VERSION)
476 #if (__ARMCC_VERSION >= 6010050)
477 #pragma clang diagnostic push
478 #else
479 #pragma push
480 #pragma anon_unions
481 #endif
482#elif defined(__GNUC__)
483 /* anonymous unions are enabled by default */
484#elif defined(__IAR_SYSTEMS_ICC__)
485 #pragma language=extended
486#else
487 #error Not supported compiler type
488#endif
489
490/* ----------------------------------------------------------------------------
491 -- ACM Peripheral Access Layer
492 ---------------------------------------------------------------------------- */
493
494/*!
495 * @addtogroup ACM_Peripheral_Access_Layer ACM Peripheral Access Layer
496 * @{
497 */
498
499/** ACM - Register Layout Typedef */
500typedef struct {
501 uint8_t RESERVED_0[14680064];
502 __IO uint32_t AUD_CLK0; /**< ACM_AUD_CLK0 Register, offset: 0xE00000 */
503 uint8_t RESERVED_1[65532];
504 __IO uint32_t AUD_CLK1; /**< ACM_AUD_CLK1 Register, offset: 0xE10000 */
505 uint8_t RESERVED_2[65532];
506 __IO uint32_t MCLKOUT0; /**< ACM_MCLKOUT0 Register, offset: 0xE20000 */
507 uint8_t RESERVED_3[65532];
508 __IO uint32_t MCLKOUT1; /**< ACM_MCLKOUT1 Register, offset: 0xE30000 */
509 uint8_t RESERVED_4[196604];
510 __IO uint32_t ESAI0_CLK; /**< ACM_ESAI0_CLK Register, offset: 0xE60000 */
511 uint8_t RESERVED_5[131068];
512 struct { /* offset: 0xE80000, array step: 0x10000 */
513 __IO uint32_t GPT_CLK; /**< ACM_GPT_CLK Register, array offset: 0xE80000, array step: 0x10000 */
514 uint8_t RESERVED_0[65532];
515 } GPT_CLK[6];
516 struct { /* offset: 0xEE0000, array step: 0x10000 */
517 __IO uint32_t SAI_MCLK; /**< ACM_SAI_MCLK Register, array offset: 0xEE0000, array step: 0x10000 */
518 uint8_t RESERVED_0[65532];
519 } SAI_MCLK[8];
520 uint8_t RESERVED_6[262144];
521 __IO uint32_t SPDIF0_TX_CLK; /**< ACM_SPDIF0_TX_CLK Register, offset: 0xFA0000 */
522 uint8_t RESERVED_7[131068];
523 __IO uint32_t MQS_HMCLK_CLK; /**< ACM_MQS_HMCLK_CLK Register, offset: 0xFC0000 */
524} ACM_Type;
525
526/* ----------------------------------------------------------------------------
527 -- ACM Register Masks
528 ---------------------------------------------------------------------------- */
529
530/*!
531 * @addtogroup ACM_Register_Masks ACM Register Masks
532 * @{
533 */
534
535/*! @name AUD_CLK0 - ACM_AUD_CLK0 Register */
536/*! @{ */
537#define ACM_AUD_CLK0_SEL_MASK (0x1FU)
538#define ACM_AUD_CLK0_SEL_SHIFT (0U)
539/*! SEL - Select
540 * 0b00000..ADMA_SLSLICE2
541 * 0b00001..ADMA_SLSLICE3
542 * 0b00010..EXT_AUD_MCLK0
543 * 0b00011..EXT_AUD_MCLK1
544 * 0b00100..ESAI0_RX_CLK
545 * 0b00101..ESAI0_RX_HF_CLKK
546 * 0b00110..ESAI0_TX_CLK
547 * 0b00111..ESAI0_TX_HF_CLK
548 * 0b01000..SPDIF0_RX
549 * 0b01001..SAI0_RX_BCLK
550 * 0b01010..SAI0_TX_BCLK
551 * 0b01011..SAI1_RX_BCLK
552 * 0b01100..SAI1_TX_BCLK
553 * 0b01101..SAI2_RX_BCLK
554 * 0b01110..SAI3_RX_BCLK
555 */
556#define ACM_AUD_CLK0_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_AUD_CLK0_SEL_SHIFT)) & ACM_AUD_CLK0_SEL_MASK)
557/*! @} */
558
559/*! @name AUD_CLK1 - ACM_AUD_CLK1 Register */
560/*! @{ */
561#define ACM_AUD_CLK1_SEL_MASK (0x1FU)
562#define ACM_AUD_CLK1_SEL_SHIFT (0U)
563/*! SEL - Select
564 * 0b00000..ADMA_SLSLICE2
565 * 0b00001..ADMA_SLSLICE3
566 * 0b00010..EXT_AUD_MCLK0
567 * 0b00011..EXT_AUD_MCLK1
568 * 0b00100..ESAI0_RX_CLK
569 * 0b00101..ESAI0_RX_HF_CLKK
570 * 0b00110..ESAI0_TX_CLK
571 * 0b00111..ESAI0_TX_HF_CLK
572 * 0b01000..SPDIF0_RX
573 * 0b01001..SAI0_RX_BCLK
574 * 0b01010..SAI0_TX_BCLK
575 * 0b01011..SAI1_RX_BCLK
576 * 0b01100..SAI1_TX_BCLK
577 * 0b01101..SAI2_RX_BCLK
578 * 0b01110..SAI3_RX_BCLK
579 */
580#define ACM_AUD_CLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_AUD_CLK1_SEL_SHIFT)) & ACM_AUD_CLK1_SEL_MASK)
581/*! @} */
582
583/*! @name MCLKOUT0 - ACM_MCLKOUT0 Register */
584/*! @{ */
585#define ACM_MCLKOUT0_SEL_MASK (0x7U)
586#define ACM_MCLKOUT0_SEL_SHIFT (0U)
587/*! SEL - Select
588 * 0b000..ADMA_SLSLICE2
589 * 0b001..ADMA_SLSLICE3
590 * 0b010..Reserved
591 * 0b011..Reserved
592 * 0b100..SPDIF0_RX
593 * 0b101..Reserved
594 * 0b110..Reserved
595 * 0b111..SAI4_RX_BCLK
596 */
597#define ACM_MCLKOUT0_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MCLKOUT0_SEL_SHIFT)) & ACM_MCLKOUT0_SEL_MASK)
598/*! @} */
599
600/*! @name MCLKOUT1 - ACM_MCLKOUT1 Register */
601/*! @{ */
602#define ACM_MCLKOUT1_SEL_MASK (0x7U)
603#define ACM_MCLKOUT1_SEL_SHIFT (0U)
604/*! SEL - Select
605 * 0b000..ADMA_SLSLICE2
606 * 0b001..ADMA_SLSLICE3
607 * 0b010..Reserved
608 * 0b011..Reserved
609 * 0b100..SPDIF0_RX
610 * 0b101..Reserved
611 * 0b110..Reserved
612 * 0b111..SAI4_RX_BCLK
613 */
614#define ACM_MCLKOUT1_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MCLKOUT1_SEL_SHIFT)) & ACM_MCLKOUT1_SEL_MASK)
615/*! @} */
616
617/*! @name ESAI0_CLK - ACM_ESAI0_CLK Register */
618/*! @{ */
619#define ACM_ESAI0_CLK_SEL_MASK (0x3U)
620#define ACM_ESAI0_CLK_SEL_SHIFT (0U)
621/*! SEL - Select
622 * 0b00..AUD_PLL_DIV_CLK0
623 * 0b01..AUD_PLL_DIV_CLK1
624 * 0b10..AUD_CLK0
625 * 0b11..AUD_CLK1
626 */
627#define ACM_ESAI0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_ESAI0_CLK_SEL_SHIFT)) & ACM_ESAI0_CLK_SEL_MASK)
628/*! @} */
629
630/*! @name GPT_CLK - ACM_GPT_CLK Register */
631/*! @{ */
632#define ACM_GPT_CLK_SEL_MASK (0x7U)
633#define ACM_GPT_CLK_SEL_SHIFT (0U)
634/*! SEL - Select
635 * 0b000..AUD_PLL_DIV_CLK0
636 * 0b001..AUD_PLL_DIV_CLK1
637 * 0b010..AUD_CLK0
638 * 0b011..AUD_CLK1
639 * 0b100..24M_REF_CLK
640 */
641#define ACM_GPT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT_CLK_SEL_SHIFT)) & ACM_GPT_CLK_SEL_MASK)
642/*! @} */
643
644/* The count of ACM_GPT_CLK */
645#define ACM_GPT_CLK_COUNT (6U)
646
647/*! @name SAI_MCLK - ACM_SAI_MCLK Register */
648/*! @{ */
649#define ACM_SAI_MCLK_SEL_MASK (0x3U)
650#define ACM_SAI_MCLK_SEL_SHIFT (0U)
651/*! SEL - Select
652 * 0b00..AUD_PLL_DIV_CLK0
653 * 0b01..AUD_PLL_DIV_CLK1
654 * 0b10..AUD_CLK0
655 * 0b11..AUD_CLK1
656 */
657#define ACM_SAI_MCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SAI_MCLK_SEL_SHIFT)) & ACM_SAI_MCLK_SEL_MASK)
658/*! @} */
659
660/* The count of ACM_SAI_MCLK */
661#define ACM_SAI_MCLK_COUNT (8U)
662
663/*! @name SPDIF0_TX_CLK - ACM_SPDIF0_TX_CLK Register */
664/*! @{ */
665#define ACM_SPDIF0_TX_CLK_SEL_MASK (0x3U)
666#define ACM_SPDIF0_TX_CLK_SEL_SHIFT (0U)
667/*! SEL - Select
668 * 0b00..AUD_PLL_DIV_CLK0
669 * 0b01..AUD_PLL_DIV_CLK1
670 * 0b10..AUD_CLK0
671 * 0b11..AUD_CLK1
672 */
673#define ACM_SPDIF0_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SPDIF0_TX_CLK_SEL_SHIFT)) & ACM_SPDIF0_TX_CLK_SEL_MASK)
674/*! @} */
675
676/*! @name MQS_HMCLK_CLK - ACM_MQS_HMCLK_CLK Register */
677/*! @{ */
678#define ACM_MQS_HMCLK_CLK_SEL_MASK (0x3U)
679#define ACM_MQS_HMCLK_CLK_SEL_SHIFT (0U)
680/*! SEL - Select
681 * 0b00..AUD_PLL_DIV_CLK0
682 * 0b01..AUD_PLL_DIV_CLK1
683 * 0b10..AUD_CLK0
684 * 0b11..AUD_CLK1
685 */
686#define ACM_MQS_HMCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MQS_HMCLK_CLK_SEL_SHIFT)) & ACM_MQS_HMCLK_CLK_SEL_MASK)
687/*! @} */
688
689
690/*!
691 * @}
692 */ /* end of group ACM_Register_Masks */
693
694
695/* ACM - Peripheral instance base addresses */
696/** Peripheral ADMA__ACM base address */
697#define ADMA__ACM_BASE (0x59000000u)
698/** Peripheral ADMA__ACM base pointer */
699#define ADMA__ACM ((ACM_Type *)ADMA__ACM_BASE)
700/** Array initializer of ACM peripheral base addresses */
701#define ACM_BASE_ADDRS { ADMA__ACM_BASE }
702/** Array initializer of ACM peripheral base pointers */
703#define ACM_BASE_PTRS { ADMA__ACM }
704
705/*!
706 * @}
707 */ /* end of group ACM_Peripheral_Access_Layer */
708
709
710/* ----------------------------------------------------------------------------
711 -- ADC Peripheral Access Layer
712 ---------------------------------------------------------------------------- */
713
714/*!
715 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
716 * @{
717 */
718
719/** ADC - Register Layout Typedef */
720typedef struct {
721 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
722 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
723 uint8_t RESERVED_0[8];
724 __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */
725 __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */
726 __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */
727 __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */
728 __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */
729 __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */
730 uint8_t RESERVED_1[8];
731 __IO uint32_t FCTRL; /**< ADC FIFO Control Register, offset: 0x30 */
732 __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */
733 uint8_t RESERVED_2[136];
734 __IO uint32_t TCTRL[8]; /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */
735 uint8_t RESERVED_3[32];
736 struct { /* offset: 0x100, array step: 0x8 */
737 __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
738 __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
739 } CMD[15];
740 uint8_t RESERVED_4[136];
741 __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
742 uint8_t RESERVED_5[240];
743 __I uint32_t RESFIFO; /**< ADC Data Result FIFO Register, offset: 0x300 */
744} ADC_Type;
745
746/* ----------------------------------------------------------------------------
747 -- ADC Register Masks
748 ---------------------------------------------------------------------------- */
749
750/*!
751 * @addtogroup ADC_Register_Masks ADC Register Masks
752 * @{
753 */
754
755/*! @name VERID - Version ID Register */
756/*! @{ */
757#define ADC_VERID_RES_MASK (0x1U)
758#define ADC_VERID_RES_SHIFT (0U)
759/*! RES - Resolution
760 * 0b0..Up to 13-bit differential/12-bit single ended resolution supported.
761 * 0b1..Up to 16-bit differential/15-bit single ended resolution supported.
762 */
763#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
764#define ADC_VERID_DIFFEN_MASK (0x2U)
765#define ADC_VERID_DIFFEN_SHIFT (1U)
766/*! DIFFEN - Differential Supported
767 * 0b0..Differential operation not supported.
768 * 0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.
769 */
770#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
771#define ADC_VERID_MVI_MASK (0x8U)
772#define ADC_VERID_MVI_SHIFT (3U)
773/*! MVI - Multi Vref Implemented
774 * 0b0..Single voltage reference high (VREFH) input supported.
775 * 0b1..Multiple voltage reference high (VREFH) inputs supported.
776 */
777#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
778#define ADC_VERID_CSW_MASK (0x70U)
779#define ADC_VERID_CSW_SHIFT (4U)
780/*! CSW - Channel Scale Width
781 * 0b000..Channel scaling not supported.
782 * 0b001..Channel scaling supported. 1-bit CSCALE control field.
783 * 0b110..Channel scaling supported. 6-bit CSCALE control field.
784 */
785#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
786#define ADC_VERID_VR1RNGI_MASK (0x100U)
787#define ADC_VERID_VR1RNGI_SHIFT (8U)
788/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
789 * 0b0..Range control not required. CFG[VREF1RNG] is not implemented.
790 * 0b1..Range control required. CFG[VREF1RNG] is implemented.
791 */
792#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
793#define ADC_VERID_IADCKI_MASK (0x200U)
794#define ADC_VERID_IADCKI_SHIFT (9U)
795/*! IADCKI - Internal ADC Clock implemented
796 * 0b0..Internal clock source not implemented.
797 * 0b1..Internal clock source (and CFG[ADCKEN]) implemented.
798 */
799#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
800#define ADC_VERID_CALOFSI_MASK (0x400U)
801#define ADC_VERID_CALOFSI_SHIFT (10U)
802/*! CALOFSI - Calibration Offset Function Implemented
803 * 0b0..Offset calibration and offset trimming not implemented.
804 * 0b1..Offset calibration and offset trimming implemented.
805 */
806#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
807#define ADC_VERID_MINOR_MASK (0xFF0000U)
808#define ADC_VERID_MINOR_SHIFT (16U)
809/*! MINOR - Minor Version Number
810 */
811#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
812#define ADC_VERID_MAJOR_MASK (0xFF000000U)
813#define ADC_VERID_MAJOR_SHIFT (24U)
814/*! MAJOR - Major Version Number
815 */
816#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
817/*! @} */
818
819/*! @name PARAM - Parameter Register */
820/*! @{ */
821#define ADC_PARAM_TRIG_NUM_MASK (0xFFU)
822#define ADC_PARAM_TRIG_NUM_SHIFT (0U)
823/*! TRIG_NUM - Trigger Number
824 */
825#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
826#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U)
827#define ADC_PARAM_FIFOSIZE_SHIFT (8U)
828/*! FIFOSIZE - Result FIFO Depth
829 * 0b00000001..Result FIFO depth = 1 dataword.
830 * 0b00000100..Result FIFO depth = 4 datawords.
831 * 0b00001000..Result FIFO depth = 8 datawords.
832 * 0b00010000..Result FIFO depth = 16 datawords.
833 * 0b00100000..Result FIFO depth = 32 datawords.
834 * 0b01000000..Result FIFO depth = 64 datawords.
835 */
836#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
837#define ADC_PARAM_CV_NUM_MASK (0xFF0000U)
838#define ADC_PARAM_CV_NUM_SHIFT (16U)
839/*! CV_NUM - Compare Value Number
840 */
841#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
842#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U)
843#define ADC_PARAM_CMD_NUM_SHIFT (24U)
844/*! CMD_NUM - Command Buffer Number
845 */
846#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
847/*! @} */
848
849/*! @name CTRL - ADC Control Register */
850/*! @{ */
851#define ADC_CTRL_ADCEN_MASK (0x1U)
852#define ADC_CTRL_ADCEN_SHIFT (0U)
853/*! ADCEN - ADC Enable
854 * 0b0..ADC is disabled.
855 * 0b1..ADC is enabled.
856 */
857#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
858#define ADC_CTRL_RST_MASK (0x2U)
859#define ADC_CTRL_RST_SHIFT (1U)
860/*! RST - Software Reset
861 * 0b0..ADC logic is not reset.
862 * 0b1..ADC logic is reset.
863 */
864#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
865#define ADC_CTRL_DOZEN_MASK (0x4U)
866#define ADC_CTRL_DOZEN_SHIFT (2U)
867/*! DOZEN - Doze Enable
868 * 0b0..ADC is enabled in Doze mode.
869 * 0b1..ADC is disabled in Doze mode.
870 */
871#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
872#define ADC_CTRL_RSTFIFO_MASK (0x100U)
873#define ADC_CTRL_RSTFIFO_SHIFT (8U)
874/*! RSTFIFO - Reset FIFO
875 * 0b0..No effect.
876 * 0b1..FIFO is reset.
877 */
878#define ADC_CTRL_RSTFIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)
879/*! @} */
880
881/*! @name STAT - ADC Status Register */
882/*! @{ */
883#define ADC_STAT_RDY_MASK (0x1U)
884#define ADC_STAT_RDY_SHIFT (0U)
885/*! RDY - Result FIFO Ready Flag
886 * 0b0..Result FIFO data level not above watermark level.
887 * 0b1..Result FIFO holding data above watermark level.
888 */
889#define ADC_STAT_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)
890#define ADC_STAT_FOF_MASK (0x2U)
891#define ADC_STAT_FOF_SHIFT (1U)
892/*! FOF - Result FIFO Overflow Flag
893 * 0b0..No result FIFO overflow has occurred since the last time the flag was cleared.
894 * 0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared.
895 */
896#define ADC_STAT_FOF(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)
897#define ADC_STAT_ADC_ACTIVE_MASK (0x100U)
898#define ADC_STAT_ADC_ACTIVE_SHIFT (8U)
899/*! ADC_ACTIVE - ADC Active
900 * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
901 * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
902 */
903#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
904#define ADC_STAT_TRGACT_MASK (0x70000U)
905#define ADC_STAT_TRGACT_SHIFT (16U)
906/*! TRGACT - Trigger Active
907 * 0b000..Command (sequence) associated with Trigger 0 currently being executed.
908 * 0b001..Command (sequence) associated with Trigger 1 currently being executed.
909 * 0b010..Command (sequence) associated with Trigger 2 currently being executed.
910 * 0b011-0b111..Command (sequence) from the associated Trigger number is currently being executed.
911 */
912#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
913#define ADC_STAT_CMDACT_MASK (0xF000000U)
914#define ADC_STAT_CMDACT_SHIFT (24U)
915/*! CMDACT - Command Active
916 * 0b0000..No command is currently in progress.
917 * 0b0001..Command 1 currently being executed.
918 * 0b0010..Command 2 currently being executed.
919 * 0b0011-0b1111..Associated command number is currently being executed.
920 */
921#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
922/*! @} */
923
924/*! @name IE - Interrupt Enable Register */
925/*! @{ */
926#define ADC_IE_FWMIE_MASK (0x1U)
927#define ADC_IE_FWMIE_SHIFT (0U)
928/*! FWMIE - FIFO Watermark Interrupt Enable
929 * 0b0..FIFO watermark interrupts are not enabled.
930 * 0b1..FIFO watermark interrupts are enabled.
931 */
932#define ADC_IE_FWMIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)
933#define ADC_IE_FOFIE_MASK (0x2U)
934#define ADC_IE_FOFIE_SHIFT (1U)
935/*! FOFIE - Result FIFO Overflow Interrupt Enable
936 * 0b0..FIFO overflow interrupts are not enabled.
937 * 0b1..FIFO overflow interrupts are enabled.
938 */
939#define ADC_IE_FOFIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)
940/*! @} */
941
942/*! @name DE - DMA Enable Register */
943/*! @{ */
944#define ADC_DE_FWMDE_MASK (0x1U)
945#define ADC_DE_FWMDE_SHIFT (0U)
946/*! FWMDE - FIFO Watermark DMA Enable
947 * 0b0..DMA request disabled.
948 * 0b1..DMA request enabled.
949 */
950#define ADC_DE_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)
951/*! @} */
952
953/*! @name CFG - ADC Configuration Register */
954/*! @{ */
955#define ADC_CFG_TPRICTRL_MASK (0x1U)
956#define ADC_CFG_TPRICTRL_SHIFT (0U)
957/*! TPRICTRL - ADC trigger priority control
958 * 0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and
959 * the new command specified by the trigger is started.
960 * 0b1..If a higher priority trigger is received during command processing, the current conversion is completed
961 * (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority
962 * trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true
963 * conversion.
964 */
965#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
966#define ADC_CFG_PWRSEL_MASK (0x30U)
967#define ADC_CFG_PWRSEL_SHIFT (4U)
968/*! PWRSEL - Power Configuration Select
969 * 0b00..Level 1 (Lowest power setting)
970 * 0b01..Level 2
971 * 0b10..Level 3
972 * 0b11..Level 4 (Highest power setting)
973 */
974#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
975#define ADC_CFG_REFSEL_MASK (0xC0U)
976#define ADC_CFG_REFSEL_SHIFT (6U)
977/*! REFSEL - Voltage Reference Selection
978 * 0b00..(Default) Option 1 setting.
979 * 0b01..Option 2 setting.
980 * 0b10..Option 3 setting.
981 * 0b11..Reserved
982 */
983#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
984#define ADC_CFG_PUDLY_MASK (0xFF0000U)
985#define ADC_CFG_PUDLY_SHIFT (16U)
986/*! PUDLY - Power Up Delay
987 */
988#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
989#define ADC_CFG_PWREN_MASK (0x10000000U)
990#define ADC_CFG_PWREN_SHIFT (28U)
991/*! PWREN - ADC Analog Pre-Enable
992 * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
993 * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
994 * of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any
995 * detected trigger does not begin ADC operation until the power up delay time has passed.
996 */
997#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
998/*! @} */
999
1000/*! @name PAUSE - ADC Pause Register */
1001/*! @{ */
1002#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU)
1003#define ADC_PAUSE_PAUSEDLY_SHIFT (0U)
1004/*! PAUSEDLY - Pause Delay
1005 */
1006#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
1007#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U)
1008#define ADC_PAUSE_PAUSEEN_SHIFT (31U)
1009/*! PAUSEEN - PAUSE Option Enable
1010 * 0b0..Pause operation disabled
1011 * 0b1..Pause operation enabled
1012 */
1013#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
1014/*! @} */
1015
1016/*! @name FCTRL - ADC FIFO Control Register */
1017/*! @{ */
1018#define ADC_FCTRL_FCOUNT_MASK (0x1FU)
1019#define ADC_FCTRL_FCOUNT_SHIFT (0U)
1020/*! FCOUNT - Result FIFO counter
1021 */
1022#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
1023#define ADC_FCTRL_FWMARK_MASK (0xF0000U)
1024#define ADC_FCTRL_FWMARK_SHIFT (16U)
1025/*! FWMARK - Watermark level selection
1026 */
1027#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
1028/*! @} */
1029
1030/*! @name SWTRIG - Software Trigger Register */
1031/*! @{ */
1032#define ADC_SWTRIG_SWT0_MASK (0x1U)
1033#define ADC_SWTRIG_SWT0_SHIFT (0U)
1034/*! SWT0 - Software trigger 0 event
1035 * 0b0..No trigger 0 event generated.
1036 * 0b1..Trigger 0 event generated.
1037 */
1038#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
1039#define ADC_SWTRIG_SWT1_MASK (0x2U)
1040#define ADC_SWTRIG_SWT1_SHIFT (1U)
1041/*! SWT1 - Software trigger 1 event
1042 * 0b0..No trigger 1 event generated.
1043 * 0b1..Trigger 1 event generated.
1044 */
1045#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
1046#define ADC_SWTRIG_SWT2_MASK (0x4U)
1047#define ADC_SWTRIG_SWT2_SHIFT (2U)
1048/*! SWT2 - Software trigger 2 event
1049 * 0b0..No trigger 2 event generated.
1050 * 0b1..Trigger 2 event generated.
1051 */
1052#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
1053#define ADC_SWTRIG_SWT3_MASK (0x8U)
1054#define ADC_SWTRIG_SWT3_SHIFT (3U)
1055/*! SWT3 - Software trigger 3 event
1056 * 0b0..No trigger 3 event generated.
1057 * 0b1..Trigger 3 event generated.
1058 */
1059#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
1060#define ADC_SWTRIG_SWT4_MASK (0x10U)
1061#define ADC_SWTRIG_SWT4_SHIFT (4U)
1062/*! SWT4 - Software trigger 4 event
1063 * 0b0..No trigger 4 event generated.
1064 * 0b1..Trigger 4 event generated.
1065 */
1066#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
1067#define ADC_SWTRIG_SWT5_MASK (0x20U)
1068#define ADC_SWTRIG_SWT5_SHIFT (5U)
1069/*! SWT5 - Software trigger 5 event
1070 * 0b0..No trigger 5 event generated.
1071 * 0b1..Trigger 5 event generated.
1072 */
1073#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
1074#define ADC_SWTRIG_SWT6_MASK (0x40U)
1075#define ADC_SWTRIG_SWT6_SHIFT (6U)
1076/*! SWT6 - Software trigger 6 event
1077 * 0b0..No trigger 6 event generated.
1078 * 0b1..Trigger 6 event generated.
1079 */
1080#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
1081#define ADC_SWTRIG_SWT7_MASK (0x80U)
1082#define ADC_SWTRIG_SWT7_SHIFT (7U)
1083/*! SWT7 - Software trigger 7 event
1084 * 0b0..No trigger 7 event generated.
1085 * 0b1..Trigger 7 event generated.
1086 */
1087#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
1088/*! @} */
1089
1090/*! @name TCTRL - Trigger Control Register */
1091/*! @{ */
1092#define ADC_TCTRL_HTEN_MASK (0x1U)
1093#define ADC_TCTRL_HTEN_SHIFT (0U)
1094/*! HTEN - Trigger enable
1095 * 0b0..Hardware trigger source disabled
1096 * 0b1..Hardware trigger source enabled
1097 */
1098#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
1099#define ADC_TCTRL_TPRI_MASK (0x700U)
1100#define ADC_TCTRL_TPRI_SHIFT (8U)
1101/*! TPRI - Trigger priority setting
1102 * 0b000..Set to highest priority, Level 1
1103 * 0b001-0b110..Set to corresponding priority level
1104 * 0b111..Set to lowest priority, Level 8
1105 */
1106#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
1107#define ADC_TCTRL_TDLY_MASK (0xF0000U)
1108#define ADC_TCTRL_TDLY_SHIFT (16U)
1109/*! TDLY - Trigger delay select
1110 */
1111#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
1112#define ADC_TCTRL_TCMD_MASK (0xF000000U)
1113#define ADC_TCTRL_TCMD_SHIFT (24U)
1114/*! TCMD - Trigger command select
1115 * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
1116 * 0b0001..CMD1 is executed
1117 * 0b0010-0b1110..Corresponding CMD is executed
1118 * 0b1111..CMD15 is executed
1119 */
1120#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
1121/*! @} */
1122
1123/* The count of ADC_TCTRL */
1124#define ADC_TCTRL_COUNT (8U)
1125
1126/*! @name CMDL - ADC Command Low Buffer Register */
1127/*! @{ */
1128#define ADC_CMDL_ADCH_MASK (0x1FU)
1129#define ADC_CMDL_ADCH_SHIFT (0U)
1130/*! ADCH - Input channel select
1131 * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
1132 * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
1133 * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
1134 * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
1135 * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
1136 * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
1137 * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
1138 */
1139#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
1140#define ADC_CMDL_ABSEL_MASK (0x20U)
1141#define ADC_CMDL_ABSEL_SHIFT (5U)
1142/*! ABSEL - A-side vs. B-side Select
1143 * 0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB).
1144 * 0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA).
1145 */
1146#define ADC_CMDL_ABSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
1147#define ADC_CMDL_DIFF_MASK (0x40U)
1148#define ADC_CMDL_DIFF_SHIFT (6U)
1149/*! DIFF - Differential Mode Enable
1150 * 0b0..Single-ended mode.
1151 * 0b1..Differential mode.
1152 */
1153#define ADC_CMDL_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)
1154#define ADC_CMDL_CSCALE_MASK (0x2000U)
1155#define ADC_CMDL_CSCALE_SHIFT (13U)
1156/*! CSCALE - Channel Scale
1157 * 0b0..Scale selected analog channel (Factor of 30/64)
1158 * 0b1..(Default) Full scale (Factor of 1)
1159 */
1160#define ADC_CMDL_CSCALE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)
1161/*! @} */
1162
1163/* The count of ADC_CMDL */
1164#define ADC_CMDL_COUNT (15U)
1165
1166/*! @name CMDH - ADC Command High Buffer Register */
1167/*! @{ */
1168#define ADC_CMDH_CMPEN_MASK (0x3U)
1169#define ADC_CMDH_CMPEN_SHIFT (0U)
1170/*! CMPEN - Compare Function Enable
1171 * 0b00..Compare disabled.
1172 * 0b01..Reserved
1173 * 0b10..Compare enabled. Store on true.
1174 * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
1175 */
1176#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
1177#define ADC_CMDH_LWI_MASK (0x80U)
1178#define ADC_CMDH_LWI_SHIFT (7U)
1179/*! LWI - Loop with Increment
1180 * 0b0..Auto channel increment disabled
1181 * 0b1..Auto channel increment enabled
1182 */
1183#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
1184#define ADC_CMDH_STS_MASK (0x700U)
1185#define ADC_CMDH_STS_SHIFT (8U)
1186/*! STS - Sample Time Select
1187 * 0b000..Minimum sample time of 3 ADCK cycles.
1188 * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
1189 * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
1190 * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
1191 * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
1192 * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
1193 * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
1194 * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
1195 */
1196#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
1197#define ADC_CMDH_AVGS_MASK (0x7000U)
1198#define ADC_CMDH_AVGS_SHIFT (12U)
1199/*! AVGS - Hardware Average Select
1200 * 0b000..Single conversion.
1201 * 0b001..2 conversions averaged.
1202 * 0b010..4 conversions averaged.
1203 * 0b011..8 conversions averaged.
1204 * 0b100..16 conversions averaged.
1205 * 0b101..32 conversions averaged.
1206 * 0b110..64 conversions averaged.
1207 * 0b111..128 conversions averaged.
1208 */
1209#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
1210#define ADC_CMDH_LOOP_MASK (0xF0000U)
1211#define ADC_CMDH_LOOP_SHIFT (16U)
1212/*! LOOP - Loop Count Select
1213 * 0b0000..Looping not enabled. Command executes 1 time.
1214 * 0b0001..Loop 1 time. Command executes 2 times.
1215 * 0b0010..Loop 2 times. Command executes 3 times.
1216 * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
1217 * 0b1111..Loop 15 times. Command executes 16 times.
1218 */
1219#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
1220#define ADC_CMDH_NEXT_MASK (0xF000000U)
1221#define ADC_CMDH_NEXT_SHIFT (24U)
1222/*! NEXT - Next Command Select
1223 * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
1224 * trigger pending, begin command associated with lower priority trigger.
1225 * 0b0001..Select CMD1 command buffer register as next command.
1226 * 0b0010-0b1110..Select corresponding CMD command buffer register as next command
1227 * 0b1111..Select CMD15 command buffer register as next command.
1228 */
1229#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
1230/*! @} */
1231
1232/* The count of ADC_CMDH */
1233#define ADC_CMDH_COUNT (15U)
1234
1235/*! @name CV - Compare Value Register */
1236/*! @{ */
1237#define ADC_CV_CVL_MASK (0xFFFFU)
1238#define ADC_CV_CVL_SHIFT (0U)
1239/*! CVL - Compare Value Low.
1240 */
1241#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
1242#define ADC_CV_CVH_MASK (0xFFFF0000U)
1243#define ADC_CV_CVH_SHIFT (16U)
1244/*! CVH - Compare Value High.
1245 */
1246#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
1247/*! @} */
1248
1249/* The count of ADC_CV */
1250#define ADC_CV_COUNT (4U)
1251
1252/*! @name RESFIFO - ADC Data Result FIFO Register */
1253/*! @{ */
1254#define ADC_RESFIFO_D_MASK (0xFFFFU)
1255#define ADC_RESFIFO_D_SHIFT (0U)
1256/*! D - Data result
1257 */
1258#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
1259#define ADC_RESFIFO_TSRC_MASK (0x70000U)
1260#define ADC_RESFIFO_TSRC_SHIFT (16U)
1261/*! TSRC - Trigger Source
1262 * 0b000..Trigger source 0 initiated this conversion.
1263 * 0b001..Trigger source 1 initiated this conversion.
1264 * 0b010-0b110..Corresponding trigger source initiated this conversion.
1265 * 0b111..Trigger source 7 initiated this conversion.
1266 */
1267#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
1268#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U)
1269#define ADC_RESFIFO_LOOPCNT_SHIFT (20U)
1270/*! LOOPCNT - Loop count value
1271 * 0b0000..Result is from initial conversion in command.
1272 * 0b0001..Result is from second conversion in command.
1273 * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
1274 * 0b1111..Result is from 16th conversion in command.
1275 */
1276#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
1277#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U)
1278#define ADC_RESFIFO_CMDSRC_SHIFT (24U)
1279/*! CMDSRC - Command Buffer Source
1280 * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
1281 * prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
1282 * 0b0001..CMD1 buffer used as control settings for this conversion.
1283 * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
1284 * 0b1111..CMD15 buffer used as control settings for this conversion.
1285 */
1286#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
1287#define ADC_RESFIFO_VALID_MASK (0x80000000U)
1288#define ADC_RESFIFO_VALID_SHIFT (31U)
1289/*! VALID - FIFO entry is valid
1290 * 0b0..FIFO is empty. Discard any read from RESFIFO.
1291 * 0b1..FIFO record read from RESFIFO is valid.
1292 */
1293#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
1294/*! @} */
1295
1296
1297/*!
1298 * @}
1299 */ /* end of group ADC_Register_Masks */
1300
1301
1302/* ADC - Peripheral instance base addresses */
1303/** Peripheral ADMA__ADC0 base address */
1304#define ADMA__ADC0_BASE (0x5A880000u)
1305/** Peripheral ADMA__ADC0 base pointer */
1306#define ADMA__ADC0 ((ADC_Type *)ADMA__ADC0_BASE)
1307/** Array initializer of ADC peripheral base addresses */
1308#define ADC_BASE_ADDRS { ADMA__ADC0_BASE }
1309/** Array initializer of ADC peripheral base pointers */
1310#define ADC_BASE_PTRS { ADMA__ADC0 }
1311/** Interrupt vectors for the ADC peripheral type */
1312#define ADC_IRQS { ADMA_ADC0_INT_IRQn }
1313
1314/*!
1315 * @}
1316 */ /* end of group ADC_Peripheral_Access_Layer */
1317
1318
1319/* ----------------------------------------------------------------------------
1320 -- APBH Peripheral Access Layer
1321 ---------------------------------------------------------------------------- */
1322
1323/*!
1324 * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer
1325 * @{
1326 */
1327
1328/** APBH - Register Layout Typedef */
1329typedef struct {
1330 struct { /* offset: 0x0 */
1331 __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */
1332 __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */
1333 __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */
1334 __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */
1335 } CTRL0;
1336 struct { /* offset: 0x10 */
1337 __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */
1338 __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */
1339 __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */
1340 __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */
1341 } CTRL1;
1342 struct { /* offset: 0x20 */
1343 __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */
1344 __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */
1345 __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */
1346 __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */
1347 } CTRL2;
1348 struct { /* offset: 0x30 */
1349 __IO uint32_t RW; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */
1350 __IO uint32_t SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */
1351 __IO uint32_t CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */
1352 __IO uint32_t TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */
1353 } CHANNEL_CTRL;
1354 uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */
1355 uint8_t RESERVED_0[12];
1356 __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */
1357 uint8_t RESERVED_1[12];
1358 __IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60 */
1359 uint8_t RESERVED_2[156];
1360 struct { /* offset: 0x100, array step: 0x70 */
1361 __I uint32_t CH_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, array offset: 0x100, array step: 0x70 */
1362 uint8_t RESERVED_0[12];
1363 __IO uint32_t CH_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, array offset: 0x110, array step: 0x70 */
1364 uint8_t RESERVED_1[12];
1365 __I uint32_t CH_CMD; /**< APBH DMA Channel n Command Register, array offset: 0x120, array step: 0x70 */
1366 uint8_t RESERVED_2[12];
1367 __I uint32_t CH_BAR; /**< APBH DMA Channel n Buffer Address Register, array offset: 0x130, array step: 0x70 */
1368 uint8_t RESERVED_3[12];
1369 __IO uint32_t CH_SEMA; /**< APBH DMA Channel n Semaphore Register, array offset: 0x140, array step: 0x70 */
1370 uint8_t RESERVED_4[12];
1371 __I uint32_t CH_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x150, array step: 0x70 */
1372 uint8_t RESERVED_5[12];
1373 __I uint32_t CH_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x160, array step: 0x70 */
1374 uint8_t RESERVED_6[12];
1375 } CH_CFGn[16];
1376 __I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */
1377} APBH_Type;
1378
1379/* ----------------------------------------------------------------------------
1380 -- APBH Register Masks
1381 ---------------------------------------------------------------------------- */
1382
1383/*!
1384 * @addtogroup APBH_Register_Masks APBH Register Masks
1385 * @{
1386 */
1387
1388/*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */
1389/*! @{ */
1390#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU)
1391#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U)
1392/*! CLKGATE_CHANNEL - CLKGATE_CHANNEL
1393 * 0b0000000000000001..
1394 * 0b0000000000000010..
1395 * 0b0000000000000100..
1396 * 0b0000000000001000..
1397 * 0b0000000000010000..
1398 * 0b0000000000100000..
1399 * 0b0000000001000000..
1400 * 0b0000000010000000..
1401 * 0b0000000100000000..
1402 */
1403#define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK)
1404#define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U)
1405#define APBH_CTRL0_APB_BURST_EN_SHIFT (28U)
1406/*! APB_BURST_EN - APB_BURST_EN
1407 */
1408#define APBH_CTRL0_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK)
1409#define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U)
1410#define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U)
1411/*! AHB_BURST8_EN - AHB_BURST8_EN
1412 */
1413#define APBH_CTRL0_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK)
1414#define APBH_CTRL0_CLKGATE_MASK (0x40000000U)
1415#define APBH_CTRL0_CLKGATE_SHIFT (30U)
1416/*! CLKGATE - CLKGATE
1417 */
1418#define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK)
1419#define APBH_CTRL0_SFTRST_MASK (0x80000000U)
1420#define APBH_CTRL0_SFTRST_SHIFT (31U)
1421/*! SFTRST - SFTRST
1422 */
1423#define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK)
1424/*! @} */
1425
1426/*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */
1427/*! @{ */
1428#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U)
1429#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U)
1430/*! CH0_CMDCMPLT_IRQ - CH0_CMDCMPLT_IRQ
1431 */
1432#define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK)
1433#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U)
1434#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U)
1435/*! CH1_CMDCMPLT_IRQ - CH1_CMDCMPLT_IRQ
1436 */
1437#define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK)
1438#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U)
1439#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U)
1440/*! CH2_CMDCMPLT_IRQ - CH2_CMDCMPLT_IRQ
1441 */
1442#define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK)
1443#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U)
1444#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U)
1445/*! CH3_CMDCMPLT_IRQ - CH3_CMDCMPLT_IRQ
1446 */
1447#define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK)
1448#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U)
1449#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U)
1450/*! CH4_CMDCMPLT_IRQ - CH4_CMDCMPLT_IRQ
1451 */
1452#define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK)
1453#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U)
1454#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U)
1455/*! CH5_CMDCMPLT_IRQ - CH5_CMDCMPLT_IRQ
1456 */
1457#define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK)
1458#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U)
1459#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U)
1460/*! CH6_CMDCMPLT_IRQ - CH6_CMDCMPLT_IRQ
1461 */
1462#define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK)
1463#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U)
1464#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U)
1465/*! CH7_CMDCMPLT_IRQ - CH7_CMDCMPLT_IRQ
1466 */
1467#define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK)
1468#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U)
1469#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U)
1470/*! CH8_CMDCMPLT_IRQ - CH8_CMDCMPLT_IRQ
1471 */
1472#define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK)
1473#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U)
1474#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U)
1475/*! CH9_CMDCMPLT_IRQ - CH9_CMDCMPLT_IRQ
1476 */
1477#define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK)
1478#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U)
1479#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U)
1480/*! CH10_CMDCMPLT_IRQ - CH10_CMDCMPLT_IRQ
1481 */
1482#define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK)
1483#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U)
1484#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U)
1485/*! CH11_CMDCMPLT_IRQ - CH11_CMDCMPLT_IRQ
1486 */
1487#define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK)
1488#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
1489#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U)
1490/*! CH12_CMDCMPLT_IRQ - CH12_CMDCMPLT_IRQ
1491 */
1492#define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK)
1493#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
1494#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U)
1495/*! CH13_CMDCMPLT_IRQ - CH13_CMDCMPLT_IRQ
1496 */
1497#define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK)
1498#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
1499#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U)
1500/*! CH14_CMDCMPLT_IRQ - CH14_CMDCMPLT_IRQ
1501 */
1502#define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK)
1503#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
1504#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U)
1505/*! CH15_CMDCMPLT_IRQ - CH15_CMDCMPLT_IRQ
1506 */
1507#define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK)
1508#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
1509#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
1510/*! CH0_CMDCMPLT_IRQ_EN - CH0_CMDCMPLT_IRQ_EN
1511 */
1512#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK)
1513#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
1514#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
1515/*! CH1_CMDCMPLT_IRQ_EN - CH1_CMDCMPLT_IRQ_EN
1516 */
1517#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK)
1518#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
1519#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
1520/*! CH2_CMDCMPLT_IRQ_EN - CH2_CMDCMPLT_IRQ_EN
1521 */
1522#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK)
1523#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
1524#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
1525/*! CH3_CMDCMPLT_IRQ_EN - CH3_CMDCMPLT_IRQ_EN
1526 */
1527#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK)
1528#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
1529#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
1530/*! CH4_CMDCMPLT_IRQ_EN - CH4_CMDCMPLT_IRQ_EN
1531 */
1532#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK)
1533#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
1534#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
1535/*! CH5_CMDCMPLT_IRQ_EN - CH5_CMDCMPLT_IRQ_EN
1536 */
1537#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK)
1538#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
1539#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
1540/*! CH6_CMDCMPLT_IRQ_EN - CH6_CMDCMPLT_IRQ_EN
1541 */
1542#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK)
1543#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
1544#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
1545/*! CH7_CMDCMPLT_IRQ_EN - CH7_CMDCMPLT_IRQ_EN
1546 */
1547#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK)
1548#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
1549#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
1550/*! CH8_CMDCMPLT_IRQ_EN - CH8_CMDCMPLT_IRQ_EN
1551 */
1552#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK)
1553#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
1554#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
1555/*! CH9_CMDCMPLT_IRQ_EN - CH9_CMDCMPLT_IRQ_EN
1556 */
1557#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK)
1558#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
1559#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
1560/*! CH10_CMDCMPLT_IRQ_EN - CH10_CMDCMPLT_IRQ_EN
1561 */
1562#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
1563#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
1564#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
1565/*! CH11_CMDCMPLT_IRQ_EN - CH11_CMDCMPLT_IRQ_EN
1566 */
1567#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK)
1568#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
1569#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
1570/*! CH12_CMDCMPLT_IRQ_EN - CH12_CMDCMPLT_IRQ_EN
1571 */
1572#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK)
1573#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
1574#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
1575/*! CH13_CMDCMPLT_IRQ_EN - CH13_CMDCMPLT_IRQ_EN
1576 */
1577#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK)
1578#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
1579#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
1580/*! CH14_CMDCMPLT_IRQ_EN - CH14_CMDCMPLT_IRQ_EN
1581 */
1582#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK)
1583#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
1584#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
1585/*! CH15_CMDCMPLT_IRQ_EN - CH15_CMDCMPLT_IRQ_EN
1586 */
1587#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK)
1588/*! @} */
1589
1590/*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */
1591/*! @{ */
1592#define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U)
1593#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U)
1594/*! CH0_ERROR_IRQ - CH0_ERROR_IRQ
1595 */
1596#define APBH_CTRL2_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK)
1597#define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U)
1598#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U)
1599/*! CH1_ERROR_IRQ - CH1_ERROR_IRQ
1600 */
1601#define APBH_CTRL2_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK)
1602#define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U)
1603#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U)
1604/*! CH2_ERROR_IRQ - CH2_ERROR_IRQ
1605 */
1606#define APBH_CTRL2_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK)
1607#define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U)
1608#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U)
1609/*! CH3_ERROR_IRQ - CH3_ERROR_IRQ
1610 */
1611#define APBH_CTRL2_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK)
1612#define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U)
1613#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U)
1614/*! CH4_ERROR_IRQ - CH4_ERROR_IRQ
1615 */
1616#define APBH_CTRL2_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK)
1617#define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U)
1618#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U)
1619/*! CH5_ERROR_IRQ - CH5_ERROR_IRQ
1620 */
1621#define APBH_CTRL2_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK)
1622#define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U)
1623#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U)
1624/*! CH6_ERROR_IRQ - CH6_ERROR_IRQ
1625 */
1626#define APBH_CTRL2_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK)
1627#define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U)
1628#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U)
1629/*! CH7_ERROR_IRQ - CH7_ERROR_IRQ
1630 */
1631#define APBH_CTRL2_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK)
1632#define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U)
1633#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U)
1634/*! CH8_ERROR_IRQ - CH8_ERROR_IRQ
1635 */
1636#define APBH_CTRL2_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK)
1637#define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U)
1638#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U)
1639/*! CH9_ERROR_IRQ - CH9_ERROR_IRQ
1640 */
1641#define APBH_CTRL2_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK)
1642#define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U)
1643#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U)
1644/*! CH10_ERROR_IRQ - CH10_ERROR_IRQ
1645 */
1646#define APBH_CTRL2_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK)
1647#define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U)
1648#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U)
1649/*! CH11_ERROR_IRQ - CH11_ERROR_IRQ
1650 */
1651#define APBH_CTRL2_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK)
1652#define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U)
1653#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U)
1654/*! CH12_ERROR_IRQ - CH12_ERROR_IRQ
1655 */
1656#define APBH_CTRL2_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK)
1657#define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U)
1658#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U)
1659/*! CH13_ERROR_IRQ - CH13_ERROR_IRQ
1660 */
1661#define APBH_CTRL2_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK)
1662#define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U)
1663#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U)
1664/*! CH14_ERROR_IRQ - CH14_ERROR_IRQ
1665 */
1666#define APBH_CTRL2_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK)
1667#define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U)
1668#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U)
1669/*! CH15_ERROR_IRQ - CH15_ERROR_IRQ
1670 */
1671#define APBH_CTRL2_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK)
1672#define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U)
1673#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U)
1674/*! CH0_ERROR_STATUS - CH0_ERROR_STATUS
1675 * 0b0..An early termination from the device causes error IRQ.
1676 * 0b1..An AHB bus error causes error IRQ.
1677 */
1678#define APBH_CTRL2_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK)
1679#define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U)
1680#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U)
1681/*! CH1_ERROR_STATUS - CH1_ERROR_STATUS
1682 * 0b0..An early termination from the device causes error IRQ.
1683 * 0b1..An AHB bus error causes error IRQ.
1684 */
1685#define APBH_CTRL2_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK)
1686#define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U)
1687#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U)
1688/*! CH2_ERROR_STATUS - CH2_ERROR_STATUS
1689 * 0b0..An early termination from the device causes error IRQ.
1690 * 0b1..An AHB bus error causes error IRQ.
1691 */
1692#define APBH_CTRL2_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK)
1693#define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U)
1694#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U)
1695/*! CH3_ERROR_STATUS - CH3_ERROR_STATUS
1696 * 0b0..An early termination from the device causes error IRQ.
1697 * 0b1..An AHB bus error causes error IRQ.
1698 */
1699#define APBH_CTRL2_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK)
1700#define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U)
1701#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U)
1702/*! CH4_ERROR_STATUS - CH4_ERROR_STATUS
1703 * 0b0..An early termination from the device causes error IRQ.
1704 * 0b1..An AHB bus error causes error IRQ.
1705 */
1706#define APBH_CTRL2_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK)
1707#define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U)
1708#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U)
1709/*! CH5_ERROR_STATUS - CH5_ERROR_STATUS
1710 * 0b0..An early termination from the device causes error IRQ.
1711 * 0b1..An AHB bus error causes error IRQ.
1712 */
1713#define APBH_CTRL2_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK)
1714#define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U)
1715#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U)
1716/*! CH6_ERROR_STATUS - CH6_ERROR_STATUS
1717 * 0b0..An early termination from the device causes error IRQ.
1718 * 0b1..An AHB bus error causes error IRQ.
1719 */
1720#define APBH_CTRL2_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK)
1721#define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U)
1722#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U)
1723/*! CH7_ERROR_STATUS - CH7_ERROR_STATUS
1724 * 0b0..An early termination from the device causes error IRQ.
1725 * 0b1..An AHB bus error causes error IRQ.
1726 */
1727#define APBH_CTRL2_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK)
1728#define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U)
1729#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U)
1730/*! CH8_ERROR_STATUS - CH8_ERROR_STATUS
1731 * 0b0..An early termination from the device causes error IRQ.
1732 * 0b1..An AHB bus error causes error IRQ.
1733 */
1734#define APBH_CTRL2_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK)
1735#define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U)
1736#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U)
1737/*! CH9_ERROR_STATUS - CH9_ERROR_STATUS
1738 * 0b0..An early termination from the device causes error IRQ.
1739 * 0b1..An AHB bus error causes error IRQ.
1740 */
1741#define APBH_CTRL2_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK)
1742#define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U)
1743#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U)
1744/*! CH10_ERROR_STATUS - CH10_ERROR_STATUS
1745 * 0b0..An early termination from the device causes error IRQ.
1746 * 0b1..An AHB bus error causes error IRQ.
1747 */
1748#define APBH_CTRL2_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK)
1749#define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U)
1750#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U)
1751/*! CH11_ERROR_STATUS - CH11_ERROR_STATUS
1752 * 0b0..An early termination from the device causes error IRQ.
1753 * 0b1..An AHB bus error causes error IRQ.
1754 */
1755#define APBH_CTRL2_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK)
1756#define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U)
1757#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U)
1758/*! CH12_ERROR_STATUS - CH12_ERROR_STATUS
1759 * 0b0..An early termination from the device causes error IRQ.
1760 * 0b1..An AHB bus error causes error IRQ.
1761 */
1762#define APBH_CTRL2_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK)
1763#define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U)
1764#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U)
1765/*! CH13_ERROR_STATUS - CH13_ERROR_STATUS
1766 * 0b0..An early termination from the device causes error IRQ.
1767 * 0b1..An AHB bus error causes error IRQ.
1768 */
1769#define APBH_CTRL2_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK)
1770#define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U)
1771#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U)
1772/*! CH14_ERROR_STATUS - CH14_ERROR_STATUS
1773 * 0b0..An early termination from the device causes error IRQ.
1774 * 0b1..An AHB bus error causes error IRQ.
1775 */
1776#define APBH_CTRL2_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK)
1777#define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U)
1778#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U)
1779/*! CH15_ERROR_STATUS - CH15_ERROR_STATUS
1780 * 0b0..An early termination from the device causes error IRQ.
1781 * 0b1..An AHB bus error causes error IRQ.
1782 */
1783#define APBH_CTRL2_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK)
1784/*! @} */
1785
1786/*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */
1787/*! @{ */
1788#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU)
1789#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U)
1790/*! FREEZE_CHANNEL - FREEZE_CHANNEL
1791 * 0b0000000000000001..
1792 * 0b0000000000000010..
1793 * 0b0000000000000100..
1794 * 0b0000000000001000..
1795 * 0b0000000000010000..
1796 * 0b0000000000100000..
1797 * 0b0000000001000000..
1798 * 0b0000000010000000..
1799 * 0b0000000100000000..
1800 */
1801#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK)
1802#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U)
1803#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U)
1804/*! RESET_CHANNEL - RESET_CHANNEL
1805 * 0b0000000000000001..
1806 * 0b0000000000000010..
1807 * 0b0000000000000100..
1808 * 0b0000000000001000..
1809 * 0b0000000000010000..
1810 * 0b0000000000100000..
1811 * 0b0000000001000000..
1812 * 0b0000000010000000..
1813 * 0b0000000100000000..
1814 */
1815#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK)
1816/*! @} */
1817
1818/*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */
1819/*! @{ */
1820#define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U)
1821#define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U)
1822/*! CH0 - CH0
1823 */
1824#define APBH_DMA_BURST_SIZE_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK)
1825#define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU)
1826#define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U)
1827/*! CH1 - CH1
1828 */
1829#define APBH_DMA_BURST_SIZE_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK)
1830#define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U)
1831#define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U)
1832/*! CH2 - CH2
1833 */
1834#define APBH_DMA_BURST_SIZE_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK)
1835#define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U)
1836#define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U)
1837/*! CH3 - CH3
1838 */
1839#define APBH_DMA_BURST_SIZE_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK)
1840#define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U)
1841#define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U)
1842/*! CH4 - CH4
1843 */
1844#define APBH_DMA_BURST_SIZE_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK)
1845#define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U)
1846#define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U)
1847/*! CH5 - CH5
1848 */
1849#define APBH_DMA_BURST_SIZE_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK)
1850#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U)
1851#define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U)
1852/*! CH6 - CH6
1853 */
1854#define APBH_DMA_BURST_SIZE_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK)
1855#define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U)
1856#define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U)
1857/*! CH7 - CH7
1858 */
1859#define APBH_DMA_BURST_SIZE_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK)
1860#define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U)
1861#define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U)
1862/*! CH8 - CH8
1863 * 0b00..
1864 * 0b01..
1865 * 0b10..
1866 */
1867#define APBH_DMA_BURST_SIZE_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK)
1868/*! @} */
1869
1870/*! @name DEBUG - AHB to APBH DMA Debug Register */
1871/*! @{ */
1872#define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U)
1873#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U)
1874/*! GPMI_ONE_FIFO - GPMI_ONE_FIFO
1875 */
1876#define APBH_DEBUG_GPMI_ONE_FIFO(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK)
1877/*! @} */
1878
1879/*! @name CH_CURCMDAR - APBH DMA Channel n Current Command Address Register */
1880/*! @{ */
1881#define APBH_CH_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
1882#define APBH_CH_CURCMDAR_CMD_ADDR_SHIFT (0U)
1883/*! CMD_ADDR - CMD_ADDR
1884 */
1885#define APBH_CH_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_CURCMDAR_CMD_ADDR_MASK)
1886/*! @} */
1887
1888/* The count of APBH_CH_CURCMDAR */
1889#define APBH_CH_CURCMDAR_COUNT (16U)
1890
1891/*! @name CH_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
1892/*! @{ */
1893#define APBH_CH_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
1894#define APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT (0U)
1895/*! CMD_ADDR - CMD_ADDR
1896 */
1897#define APBH_CH_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_NXTCMDAR_CMD_ADDR_MASK)
1898/*! @} */
1899
1900/* The count of APBH_CH_NXTCMDAR */
1901#define APBH_CH_NXTCMDAR_COUNT (16U)
1902
1903/*! @name CH_CMD - APBH DMA Channel n Command Register */
1904/*! @{ */
1905#define APBH_CH_CMD_COMMAND_MASK (0x3U)
1906#define APBH_CH_CMD_COMMAND_SHIFT (0U)
1907/*! COMMAND - COMMAND
1908 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
1909 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
1910 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
1911 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained
1912 * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain
1913 * pointer if the peripheral sense line is false.
1914 */
1915#define APBH_CH_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_COMMAND_SHIFT)) & APBH_CH_CMD_COMMAND_MASK)
1916#define APBH_CH_CMD_CHAIN_MASK (0x4U)
1917#define APBH_CH_CMD_CHAIN_SHIFT (2U)
1918/*! CHAIN - CHAIN
1919 */
1920#define APBH_CH_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CHAIN_SHIFT)) & APBH_CH_CMD_CHAIN_MASK)
1921#define APBH_CH_CMD_IRQONCMPLT_MASK (0x8U)
1922#define APBH_CH_CMD_IRQONCMPLT_SHIFT (3U)
1923/*! IRQONCMPLT - IRQONCMPLT
1924 */
1925#define APBH_CH_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_IRQONCMPLT_SHIFT)) & APBH_CH_CMD_IRQONCMPLT_MASK)
1926#define APBH_CH_CMD_NANDLOCK_MASK (0x10U)
1927#define APBH_CH_CMD_NANDLOCK_SHIFT (4U)
1928/*! NANDLOCK - NANDLOCK
1929 */
1930#define APBH_CH_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDLOCK_SHIFT)) & APBH_CH_CMD_NANDLOCK_MASK)
1931#define APBH_CH_CMD_NANDWAIT4READY_MASK (0x20U)
1932#define APBH_CH_CMD_NANDWAIT4READY_SHIFT (5U)
1933/*! NANDWAIT4READY - NANDWAIT4READY
1934 */
1935#define APBH_CH_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH_CMD_NANDWAIT4READY_MASK)
1936#define APBH_CH_CMD_SEMAPHORE_MASK (0x40U)
1937#define APBH_CH_CMD_SEMAPHORE_SHIFT (6U)
1938/*! SEMAPHORE - SEMAPHORE
1939 */
1940#define APBH_CH_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_SEMAPHORE_SHIFT)) & APBH_CH_CMD_SEMAPHORE_MASK)
1941#define APBH_CH_CMD_WAIT4ENDCMD_MASK (0x80U)
1942#define APBH_CH_CMD_WAIT4ENDCMD_SHIFT (7U)
1943/*! WAIT4ENDCMD - WAIT4ENDCMD
1944 */
1945#define APBH_CH_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH_CMD_WAIT4ENDCMD_MASK)
1946#define APBH_CH_CMD_HALTONTERMINATE_MASK (0x100U)
1947#define APBH_CH_CMD_HALTONTERMINATE_SHIFT (8U)
1948/*! HALTONTERMINATE - HALTONTERMINATE
1949 */
1950#define APBH_CH_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH_CMD_HALTONTERMINATE_MASK)
1951#define APBH_CH_CMD_CMDWORDS_MASK (0xF000U)
1952#define APBH_CH_CMD_CMDWORDS_SHIFT (12U)
1953/*! CMDWORDS - CMDWORDS
1954 */
1955#define APBH_CH_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CMDWORDS_SHIFT)) & APBH_CH_CMD_CMDWORDS_MASK)
1956#define APBH_CH_CMD_XFER_COUNT_MASK (0xFFFF0000U)
1957#define APBH_CH_CMD_XFER_COUNT_SHIFT (16U)
1958/*! XFER_COUNT - XFER_COUNT
1959 */
1960#define APBH_CH_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_XFER_COUNT_SHIFT)) & APBH_CH_CMD_XFER_COUNT_MASK)
1961/*! @} */
1962
1963/* The count of APBH_CH_CMD */
1964#define APBH_CH_CMD_COUNT (16U)
1965
1966/*! @name CH_BAR - APBH DMA Channel n Buffer Address Register */
1967/*! @{ */
1968#define APBH_CH_BAR_ADDRESS_MASK (0xFFFFFFFFU)
1969#define APBH_CH_BAR_ADDRESS_SHIFT (0U)
1970/*! ADDRESS - ADDRESS
1971 */
1972#define APBH_CH_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_BAR_ADDRESS_SHIFT)) & APBH_CH_BAR_ADDRESS_MASK)
1973/*! @} */
1974
1975/* The count of APBH_CH_BAR */
1976#define APBH_CH_BAR_COUNT (16U)
1977
1978/*! @name CH_SEMA - APBH DMA Channel n Semaphore Register */
1979/*! @{ */
1980#define APBH_CH_SEMA_INCREMENT_SEMA_MASK (0xFFU)
1981#define APBH_CH_SEMA_INCREMENT_SEMA_SHIFT (0U)
1982/*! INCREMENT_SEMA - INCREMENT_SEMA
1983 */
1984#define APBH_CH_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH_SEMA_INCREMENT_SEMA_MASK)
1985#define APBH_CH_SEMA_PHORE_MASK (0xFF0000U)
1986#define APBH_CH_SEMA_PHORE_SHIFT (16U)
1987/*! PHORE - PHORE
1988 */
1989#define APBH_CH_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_PHORE_SHIFT)) & APBH_CH_SEMA_PHORE_MASK)
1990/*! @} */
1991
1992/* The count of APBH_CH_SEMA */
1993#define APBH_CH_SEMA_COUNT (16U)
1994
1995/*! @name CH_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
1996/*! @{ */
1997#define APBH_CH_DEBUG1_STATEMACHINE_MASK (0x1FU)
1998#define APBH_CH_DEBUG1_STATEMACHINE_SHIFT (0U)
1999/*! STATEMACHINE - STATEMACHINE
2000 * 0b00000..This is the idle state of the DMA state machine.
2001 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
2002 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
2003 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
2004 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
2005 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
2006 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the
2007 * PIO words when PIO count is greater than 1.
2008 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
2009 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
2010 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
2011 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
2012 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
2013 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
2014 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
2015 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
2016 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
2017 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
2018 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and
2019 * effectively halts. A channel reset is required to exit this state
2020 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
2021 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device
2022 * indicates that the external device is ready.
2023 */
2024#define APBH_CH_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH_DEBUG1_STATEMACHINE_MASK)
2025#define APBH_CH_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
2026#define APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
2027/*! WR_FIFO_FULL - WR_FIFO_FULL
2028 */
2029#define APBH_CH_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_FULL_MASK)
2030#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
2031#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
2032/*! WR_FIFO_EMPTY - WR_FIFO_EMPTY
2033 */
2034#define APBH_CH_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK)
2035#define APBH_CH_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
2036#define APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
2037/*! RD_FIFO_FULL - RD_FIFO_FULL
2038 */
2039#define APBH_CH_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_FULL_MASK)
2040#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
2041#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
2042/*! RD_FIFO_EMPTY - RD_FIFO_EMPTY
2043 */
2044#define APBH_CH_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK)
2045#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
2046#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
2047/*! NEXTCMDADDRVALID - NEXTCMDADDRVALID
2048 */
2049#define APBH_CH_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK)
2050#define APBH_CH_DEBUG1_READY_MASK (0x4000000U)
2051#define APBH_CH_DEBUG1_READY_SHIFT (26U)
2052/*! READY - READY
2053 */
2054#define APBH_CH_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_READY_SHIFT)) & APBH_CH_DEBUG1_READY_MASK)
2055#define APBH_CH_DEBUG1_END_MASK (0x10000000U)
2056#define APBH_CH_DEBUG1_END_SHIFT (28U)
2057/*! END - END
2058 */
2059#define APBH_CH_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_END_SHIFT)) & APBH_CH_DEBUG1_END_MASK)
2060#define APBH_CH_DEBUG1_KICK_MASK (0x20000000U)
2061#define APBH_CH_DEBUG1_KICK_SHIFT (29U)
2062/*! KICK - KICK
2063 */
2064#define APBH_CH_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_KICK_SHIFT)) & APBH_CH_DEBUG1_KICK_MASK)
2065#define APBH_CH_DEBUG1_BURST_MASK (0x40000000U)
2066#define APBH_CH_DEBUG1_BURST_SHIFT (30U)
2067/*! BURST - BURST
2068 */
2069#define APBH_CH_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_BURST_SHIFT)) & APBH_CH_DEBUG1_BURST_MASK)
2070#define APBH_CH_DEBUG1_REQ_MASK (0x80000000U)
2071#define APBH_CH_DEBUG1_REQ_SHIFT (31U)
2072/*! REQ - REQ
2073 */
2074#define APBH_CH_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_REQ_SHIFT)) & APBH_CH_DEBUG1_REQ_MASK)
2075/*! @} */
2076
2077/* The count of APBH_CH_DEBUG1 */
2078#define APBH_CH_DEBUG1_COUNT (16U)
2079
2080/*! @name CH_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
2081/*! @{ */
2082#define APBH_CH_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
2083#define APBH_CH_DEBUG2_AHB_BYTES_SHIFT (0U)
2084/*! AHB_BYTES - AHB_BYTES
2085 */
2086#define APBH_CH_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH_DEBUG2_AHB_BYTES_MASK)
2087#define APBH_CH_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
2088#define APBH_CH_DEBUG2_APB_BYTES_SHIFT (16U)
2089/*! APB_BYTES - APB_BYTES
2090 */
2091#define APBH_CH_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH_DEBUG2_APB_BYTES_MASK)
2092/*! @} */
2093
2094/* The count of APBH_CH_DEBUG2 */
2095#define APBH_CH_DEBUG2_COUNT (16U)
2096
2097/*! @name VERSION - APBH Bridge Version Register */
2098/*! @{ */
2099#define APBH_VERSION_STEP_MASK (0xFFFFU)
2100#define APBH_VERSION_STEP_SHIFT (0U)
2101/*! STEP - STEP
2102 */
2103#define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK)
2104#define APBH_VERSION_MINOR_MASK (0xFF0000U)
2105#define APBH_VERSION_MINOR_SHIFT (16U)
2106/*! MINOR - MINOR
2107 */
2108#define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK)
2109#define APBH_VERSION_MAJOR_MASK (0xFF000000U)
2110#define APBH_VERSION_MAJOR_SHIFT (24U)
2111/*! MAJOR - MAJOR
2112 */
2113#define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK)
2114/*! @} */
2115
2116
2117/*!
2118 * @}
2119 */ /* end of group APBH_Register_Masks */
2120
2121
2122/* APBH - Peripheral instance base addresses */
2123/** Peripheral CONNECTIVITY__APBH base address */
2124#define CONNECTIVITY__APBH_BASE (0x5B810000u)
2125/** Peripheral CONNECTIVITY__APBH base pointer */
2126#define CONNECTIVITY__APBH ((APBH_Type *)CONNECTIVITY__APBH_BASE)
2127/** Array initializer of APBH peripheral base addresses */
2128#define APBH_BASE_ADDRS { CONNECTIVITY__APBH_BASE }
2129/** Array initializer of APBH peripheral base pointers */
2130#define APBH_BASE_PTRS { CONNECTIVITY__APBH }
2131/** Interrupt vectors for the APBH peripheral type */
2132#define APBH_IRQS { CONNECTIVITY_APBHDMA_IRQn }
2133
2134/*!
2135 * @}
2136 */ /* end of group APBH_Peripheral_Access_Layer */
2137
2138
2139/* ----------------------------------------------------------------------------
2140 -- ASMC Peripheral Access Layer
2141 ---------------------------------------------------------------------------- */
2142
2143/*!
2144 * @addtogroup ASMC_Peripheral_Access_Layer ASMC Peripheral Access Layer
2145 * @{
2146 */
2147
2148/** ASMC - Register Layout Typedef */
2149typedef struct {
2150 __I uint32_t SRS; /**< System Reset Status Register, offset: 0x0 */
2151 uint8_t RESERVED_0[4];
2152 __IO uint32_t PMPROT; /**< Power Mode Protection register, offset: 0x8 */
2153 __IO uint32_t PMCTRL; /**< Power Mode Control register, offset: 0xC */
2154 __IO uint32_t STOPCTRL; /**< Stop Control Register, offset: 0x10 */
2155 __I uint32_t PMSTAT; /**< Power Mode Status register, offset: 0x14 */
2156} ASMC_Type;
2157
2158/* ----------------------------------------------------------------------------
2159 -- ASMC Register Masks
2160 ---------------------------------------------------------------------------- */
2161
2162/*!
2163 * @addtogroup ASMC_Register_Masks ASMC Register Masks
2164 * @{
2165 */
2166
2167/*! @name SRS - System Reset Status Register */
2168/*! @{ */
2169#define ASMC_SRS_WAKEUP_MASK (0x1U)
2170#define ASMC_SRS_WAKEUP_SHIFT (0U)
2171/*! WAKEUP - Low Leakage Wakeup Reset
2172 * 0b0..Reset not caused by LLWU module wakeup source
2173 * 0b1..Reset caused by LLWU module wakeup source
2174 */
2175#define ASMC_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WAKEUP_SHIFT)) & ASMC_SRS_WAKEUP_MASK)
2176#define ASMC_SRS_WDOG1_MASK (0x20U)
2177#define ASMC_SRS_WDOG1_SHIFT (5U)
2178/*! WDOG1 - Watchdog
2179 * 0b0..Reset not caused by watchdog timeout
2180 * 0b1..Reset caused by watchdog timeout
2181 */
2182#define ASMC_SRS_WDOG1(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WDOG1_SHIFT)) & ASMC_SRS_WDOG1_MASK)
2183#define ASMC_SRS_RES_MASK (0x40U)
2184#define ASMC_SRS_RES_SHIFT (6U)
2185/*! RES - Chip Reset not POR
2186 * 0b0..Chip Reset did not occur
2187 * 0b1..Chip Reset caused by a source other than POR occured
2188 */
2189#define ASMC_SRS_RES(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_RES_SHIFT)) & ASMC_SRS_RES_MASK)
2190#define ASMC_SRS_POR_MASK (0x80U)
2191#define ASMC_SRS_POR_SHIFT (7U)
2192/*! POR - Power-On Reset
2193 * 0b0..Reset not caused by POR
2194 * 0b1..Reset caused by POR
2195 */
2196#define ASMC_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_POR_SHIFT)) & ASMC_SRS_POR_MASK)
2197#define ASMC_SRS_LOCKUP_MASK (0x200U)
2198#define ASMC_SRS_LOCKUP_SHIFT (9U)
2199/*! LOCKUP - Core 1 Lockup
2200 * 0b0..Reset not caused by core LOCKUP event
2201 * 0b1..Reset caused by core LOCKUP event
2202 */
2203#define ASMC_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_LOCKUP_SHIFT)) & ASMC_SRS_LOCKUP_MASK)
2204#define ASMC_SRS_SW_MASK (0x400U)
2205#define ASMC_SRS_SW_SHIFT (10U)
2206/*! SW - Software
2207 * 0b0..Reset not caused by software setting of SYSRESETREQ bit
2208 * 0b1..Reset caused by software setting of SYSRESETREQ bit
2209 */
2210#define ASMC_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SW_SHIFT)) & ASMC_SRS_SW_MASK)
2211#define ASMC_SRS_SACKERR_MASK (0x1000U)
2212#define ASMC_SRS_SACKERR_SHIFT (12U)
2213/*! SACKERR - Stop Mode Acknowledge Error Reset
2214 * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
2215 * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
2216 */
2217#define ASMC_SRS_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SACKERR_SHIFT)) & ASMC_SRS_SACKERR_MASK)
2218/*! @} */
2219
2220/*! @name PMPROT - Power Mode Protection register */
2221/*! @{ */
2222#define ASMC_PMPROT_AVLLS_MASK (0x2U)
2223#define ASMC_PMPROT_AVLLS_SHIFT (1U)
2224/*! AVLLS - Allow Very-Low-Leakage Stop Mode
2225 * 0b0..Not Allowed
2226 * 0b1..Allowed
2227 */
2228#define ASMC_PMPROT_AVLLS(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLLS_SHIFT)) & ASMC_PMPROT_AVLLS_MASK)
2229#define ASMC_PMPROT_ALLS_MASK (0x8U)
2230#define ASMC_PMPROT_ALLS_SHIFT (3U)
2231/*! ALLS - Allow Low-Leakage Stop Mode
2232 * 0b0..Not Allowed
2233 * 0b1..Allowed
2234 */
2235#define ASMC_PMPROT_ALLS(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_ALLS_SHIFT)) & ASMC_PMPROT_ALLS_MASK)
2236#define ASMC_PMPROT_AVLP_MASK (0x20U)
2237#define ASMC_PMPROT_AVLP_SHIFT (5U)
2238/*! AVLP - Allow Very-Low-Power Modes
2239 * 0b0..VLPR, VLPW, and VLPS are not allowed.
2240 * 0b1..VLPR, VLPW, and VLPS are allowed.
2241 */
2242#define ASMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLP_SHIFT)) & ASMC_PMPROT_AVLP_MASK)
2243#define ASMC_PMPROT_AHSRUN_MASK (0x80U)
2244#define ASMC_PMPROT_AHSRUN_SHIFT (7U)
2245/*! AHSRUN - Allow High Speed Run mode
2246 * 0b0..HSRUN is not allowed
2247 * 0b1..HSRUN is allowed
2248 */
2249#define ASMC_PMPROT_AHSRUN(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AHSRUN_SHIFT)) & ASMC_PMPROT_AHSRUN_MASK)
2250/*! @} */
2251
2252/*! @name PMCTRL - Power Mode Control register */
2253/*! @{ */
2254#define ASMC_PMCTRL_STOPM_MASK (0x7U)
2255#define ASMC_PMCTRL_STOPM_SHIFT (0U)
2256/*! STOPM - Stop Mode Control
2257 * 0b000..Normal Stop (STOP)
2258 * 0b001..Reserved
2259 * 0b010..Very-Low-Power Stop (VLPS)
2260 * 0b011..Low-leakage stop
2261 * 0b100..Very-low-leakage stop
2262 * 0b101..Reserved
2263 * 0b110..Reseved
2264 * 0b111..Reserved
2265 */
2266#define ASMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_STOPM_SHIFT)) & ASMC_PMCTRL_STOPM_MASK)
2267#define ASMC_PMCTRL_RUNM_MASK (0x60U)
2268#define ASMC_PMCTRL_RUNM_SHIFT (5U)
2269/*! RUNM - Run Mode Control
2270 * 0b00..Normal Run mode (RUN)
2271 * 0b01..Reserved
2272 * 0b10..Very-Low-Power Run mode (VLPR)
2273 * 0b11..High Speed Run mode (HSRUN)
2274 */
2275#define ASMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_RUNM_SHIFT)) & ASMC_PMCTRL_RUNM_MASK)
2276/*! @} */
2277
2278/*! @name STOPCTRL - Stop Control Register */
2279/*! @{ */
2280#define ASMC_STOPCTRL_PSTOPO_MASK (0xC0U)
2281#define ASMC_STOPCTRL_PSTOPO_SHIFT (6U)
2282/*! PSTOPO - Partial Stop Option
2283 * 0b00..STOP - Normal Stop mode
2284 * 0b01..PSTOP1 - Partial Stop with both system and bus clocks disabled
2285 * 0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
2286 * 0b11..Reserved
2287 */
2288#define ASMC_STOPCTRL_PSTOPO(x) (((uint32_t)(((uint32_t)(x)) << ASMC_STOPCTRL_PSTOPO_SHIFT)) & ASMC_STOPCTRL_PSTOPO_MASK)
2289/*! @} */
2290
2291/*! @name PMSTAT - Power Mode Status register */
2292/*! @{ */
2293#define ASMC_PMSTAT_PMSTAT_MASK (0xFFU) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */
2294#define ASMC_PMSTAT_PMSTAT_SHIFT (0U)
2295/*! PMSTAT - Power Mode Status
2296 * 0b00000001..Current power mode is RUN.
2297 * 0b00000010..Current power mode is STOP.
2298 * 0b00000100..Current power mode is VLPR.
2299 * 0b00001000..Current power mode is VLPW.
2300 * 0b00010000..Current power mode is VLPS.
2301 * 0b00100000..Current power mode is LLS.
2302 * 0b01000000..Current power mode is VLLS.
2303 * 0b10000000..Current power mode is HSRUN
2304 */
2305#define ASMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMSTAT_PMSTAT_SHIFT)) & ASMC_PMSTAT_PMSTAT_MASK) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */
2306/*! @} */
2307
2308
2309/*!
2310 * @}
2311 */ /* end of group ASMC_Register_Masks */
2312
2313
2314/* ASMC - Peripheral instance base addresses */
2315/** Peripheral CM4__ASMC base address */
2316#define CM4__ASMC_BASE (0x41410000u)
2317/** Peripheral CM4__ASMC base pointer */
2318#define CM4__ASMC ((ASMC_Type *)CM4__ASMC_BASE)
2319/** Peripheral SCU__ASMC base address */
2320#define SCU__ASMC_BASE (0x33410000u)
2321/** Peripheral SCU__ASMC base pointer */
2322#define SCU__ASMC ((ASMC_Type *)SCU__ASMC_BASE)
2323/** Array initializer of ASMC peripheral base addresses */
2324#define ASMC_BASE_ADDRS { CM4__ASMC_BASE, SCU__ASMC_BASE }
2325/** Array initializer of ASMC peripheral base pointers */
2326#define ASMC_BASE_PTRS { CM4__ASMC, SCU__ASMC }
2327
2328/*!
2329 * @}
2330 */ /* end of group ASMC_Peripheral_Access_Layer */
2331
2332
2333/* ----------------------------------------------------------------------------
2334 -- ASRC Peripheral Access Layer
2335 ---------------------------------------------------------------------------- */
2336
2337/*!
2338 * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer
2339 * @{
2340 */
2341
2342/** ASRC - Register Layout Typedef */
2343typedef struct {
2344 __IO uint32_t ASRCTR; /**< ASRC Control Register, offset: 0x0 */
2345 __IO uint32_t ASRIER; /**< ASRC Interrupt Enable Register, offset: 0x4 */
2346 uint8_t RESERVED_0[4];
2347 __IO uint32_t ASRCNCR; /**< ASRC Channel Number Configuration Register, offset: 0xC */
2348 __IO uint32_t ASRCFG; /**< ASRC Filter Configuration Status Register, offset: 0x10 */
2349 __IO uint32_t ASRCSR; /**< ASRC Clock Source Register, offset: 0x14 */
2350 __IO uint32_t ASRCDR1; /**< ASRC Clock Divider Register 1, offset: 0x18 */
2351 __IO uint32_t ASRCDR2; /**< ASRC Clock Divider Register 2, offset: 0x1C */
2352 __I uint32_t ASRSTR; /**< ASRC Status Register, offset: 0x20 */
2353 uint8_t RESERVED_1[28];
2354 __IO uint32_t ASRPM[5]; /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */
2355 __IO uint32_t ASRTFR1; /**< ASRC ASRC Task Queue FIFO Register 1, offset: 0x54 */
2356 uint8_t RESERVED_2[4];
2357 __IO uint32_t ASRCCR; /**< ASRC Channel Counter Register, offset: 0x5C */
2358 __O uint32_t ASRDIA; /**< ASRC Data Input Register for Pair x, offset: 0x60 */
2359 __I uint32_t ASRDOA; /**< ASRC Data Output Register for Pair x, offset: 0x64 */
2360 __O uint32_t ASRDIB; /**< ASRC Data Input Register for Pair x, offset: 0x68 */
2361 __I uint32_t ASRDOB; /**< ASRC Data Output Register for Pair x, offset: 0x6C */
2362 __O uint32_t ASRDIC; /**< ASRC Data Input Register for Pair x, offset: 0x70 */
2363 __I uint32_t ASRDOC; /**< ASRC Data Output Register for Pair x, offset: 0x74 */
2364 uint8_t RESERVED_3[8];
2365 __IO uint32_t ASRIDRHA; /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */
2366 __IO uint32_t ASRIDRLA; /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */
2367 __IO uint32_t ASRIDRHB; /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */
2368 __IO uint32_t ASRIDRLB; /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */
2369 __IO uint32_t ASRIDRHC; /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */
2370 __IO uint32_t ASRIDRLC; /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */
2371 __IO uint32_t ASR76K; /**< ASRC 76 kHz Period in terms of ASRC processing clock, offset: 0x98 */
2372 __IO uint32_t ASR56K; /**< ASRC 56 kHz Period in terms of ASRC processing clock, offset: 0x9C */
2373 __IO uint32_t ASRMCRA; /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */
2374 __I uint32_t ASRFSTA; /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */
2375 __IO uint32_t ASRMCRB; /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */
2376 __I uint32_t ASRFSTB; /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */
2377 __IO uint32_t ASRMCRC; /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */
2378 __I uint32_t ASRFSTC; /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */
2379 uint8_t RESERVED_4[8];
2380 __IO uint32_t ASRMCR1[3]; /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4 */
2381} ASRC_Type;
2382
2383/* ----------------------------------------------------------------------------
2384 -- ASRC Register Masks
2385 ---------------------------------------------------------------------------- */
2386
2387/*!
2388 * @addtogroup ASRC_Register_Masks ASRC Register Masks
2389 * @{
2390 */
2391
2392/*! @name ASRCTR - ASRC Control Register */
2393/*! @{ */
2394#define ASRC_ASRCTR_ASRCEN_MASK (0x1U)
2395#define ASRC_ASRCTR_ASRCEN_SHIFT (0U)
2396/*! ASRCEN - ASRCEN
2397 */
2398#define ASRC_ASRCTR_ASRCEN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK)
2399#define ASRC_ASRCTR_ASREA_MASK (0x2U)
2400#define ASRC_ASRCTR_ASREA_SHIFT (1U)
2401/*! ASREA - ASREA
2402 */
2403#define ASRC_ASRCTR_ASREA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK)
2404#define ASRC_ASRCTR_ASREB_MASK (0x4U)
2405#define ASRC_ASRCTR_ASREB_SHIFT (2U)
2406/*! ASREB - ASREB
2407 */
2408#define ASRC_ASRCTR_ASREB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK)
2409#define ASRC_ASRCTR_ASREC_MASK (0x8U)
2410#define ASRC_ASRCTR_ASREC_SHIFT (3U)
2411/*! ASREC - ASREC
2412 */
2413#define ASRC_ASRCTR_ASREC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK)
2414#define ASRC_ASRCTR_SRST_MASK (0x10U)
2415#define ASRC_ASRCTR_SRST_SHIFT (4U)
2416/*! SRST - SRST
2417 */
2418#define ASRC_ASRCTR_SRST(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK)
2419#define ASRC_ASRCTR_IDRA_MASK (0x2000U)
2420#define ASRC_ASRCTR_IDRA_SHIFT (13U)
2421/*! IDRA - IDRA
2422 */
2423#define ASRC_ASRCTR_IDRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK)
2424#define ASRC_ASRCTR_USRA_MASK (0x4000U)
2425#define ASRC_ASRCTR_USRA_SHIFT (14U)
2426/*! USRA - USRA
2427 */
2428#define ASRC_ASRCTR_USRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK)
2429#define ASRC_ASRCTR_IDRB_MASK (0x8000U)
2430#define ASRC_ASRCTR_IDRB_SHIFT (15U)
2431/*! IDRB - IDRB
2432 */
2433#define ASRC_ASRCTR_IDRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK)
2434#define ASRC_ASRCTR_USRB_MASK (0x10000U)
2435#define ASRC_ASRCTR_USRB_SHIFT (16U)
2436/*! USRB - USRB
2437 */
2438#define ASRC_ASRCTR_USRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK)
2439#define ASRC_ASRCTR_IDRC_MASK (0x20000U)
2440#define ASRC_ASRCTR_IDRC_SHIFT (17U)
2441/*! IDRC - IDRC
2442 */
2443#define ASRC_ASRCTR_IDRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK)
2444#define ASRC_ASRCTR_USRC_MASK (0x40000U)
2445#define ASRC_ASRCTR_USRC_SHIFT (18U)
2446/*! USRC - USRC
2447 */
2448#define ASRC_ASRCTR_USRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK)
2449#define ASRC_ASRCTR_ATSA_MASK (0x100000U)
2450#define ASRC_ASRCTR_ATSA_SHIFT (20U)
2451/*! ATSA - ATSA
2452 */
2453#define ASRC_ASRCTR_ATSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK)
2454#define ASRC_ASRCTR_ATSB_MASK (0x200000U)
2455#define ASRC_ASRCTR_ATSB_SHIFT (21U)
2456/*! ATSB - ATSB
2457 */
2458#define ASRC_ASRCTR_ATSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK)
2459#define ASRC_ASRCTR_ATSC_MASK (0x400000U)
2460#define ASRC_ASRCTR_ATSC_SHIFT (22U)
2461/*! ATSC - ATSC
2462 */
2463#define ASRC_ASRCTR_ATSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK)
2464/*! @} */
2465
2466/*! @name ASRIER - ASRC Interrupt Enable Register */
2467/*! @{ */
2468#define ASRC_ASRIER_ADIEA_MASK (0x1U)
2469#define ASRC_ASRIER_ADIEA_SHIFT (0U)
2470/*! ADIEA - ADIEA
2471 * 0b1..interrupt enabled
2472 * 0b0..interrupt disabled
2473 */
2474#define ASRC_ASRIER_ADIEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK)
2475#define ASRC_ASRIER_ADIEB_MASK (0x2U)
2476#define ASRC_ASRIER_ADIEB_SHIFT (1U)
2477/*! ADIEB - ADIEB
2478 * 0b1..interrupt enabled
2479 * 0b0..interrupt disabled
2480 */
2481#define ASRC_ASRIER_ADIEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK)
2482#define ASRC_ASRIER_ADIEC_MASK (0x4U)
2483#define ASRC_ASRIER_ADIEC_SHIFT (2U)
2484/*! ADIEC - ADIEC
2485 * 0b1..interrupt enabled
2486 * 0b0..interrupt disabled
2487 */
2488#define ASRC_ASRIER_ADIEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK)
2489#define ASRC_ASRIER_ADOEA_MASK (0x8U)
2490#define ASRC_ASRIER_ADOEA_SHIFT (3U)
2491/*! ADOEA - ADOEA
2492 * 0b1..interrupt enabled
2493 * 0b0..interrupt disabled
2494 */
2495#define ASRC_ASRIER_ADOEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK)
2496#define ASRC_ASRIER_ADOEB_MASK (0x10U)
2497#define ASRC_ASRIER_ADOEB_SHIFT (4U)
2498/*! ADOEB - ADOEB
2499 * 0b1..interrupt enabled
2500 * 0b0..interrupt disabled
2501 */
2502#define ASRC_ASRIER_ADOEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK)
2503#define ASRC_ASRIER_ADOEC_MASK (0x20U)
2504#define ASRC_ASRIER_ADOEC_SHIFT (5U)
2505/*! ADOEC - ADOEC
2506 * 0b1..interrupt enabled
2507 * 0b0..interrupt disabled
2508 */
2509#define ASRC_ASRIER_ADOEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK)
2510#define ASRC_ASRIER_AOLIE_MASK (0x40U)
2511#define ASRC_ASRIER_AOLIE_SHIFT (6U)
2512/*! AOLIE - AOLIE
2513 * 0b1..interrupt enabled
2514 * 0b0..interrupt disabled
2515 */
2516#define ASRC_ASRIER_AOLIE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK)
2517#define ASRC_ASRIER_AFPWE_MASK (0x80U)
2518#define ASRC_ASRIER_AFPWE_SHIFT (7U)
2519/*! AFPWE - AFPWE
2520 * 0b1..interrupt enabled
2521 * 0b0..interrupt disabled
2522 */
2523#define ASRC_ASRIER_AFPWE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK)
2524/*! @} */
2525
2526/*! @name ASRCNCR - ASRC Channel Number Configuration Register */
2527/*! @{ */
2528#define ASRC_ASRCNCR_ANCA_MASK (0xFU)
2529#define ASRC_ASRCNCR_ANCA_SHIFT (0U)
2530/*! ANCA - ANCA
2531 * 0b0000..0 channels in A (Pair A is disabled)
2532 * 0b0001..1 channel in A
2533 * 0b0010..2 channels in A
2534 * 0b0011..3 channels in A
2535 * 0b0100..4 channels in A
2536 * 0b0101..5 channels in A
2537 * 0b0110..6 channels in A
2538 * 0b0111..7 channels in A
2539 * 0b1000..8 channels in A
2540 * 0b1001..9 channels in A
2541 * 0b1010..10 channels in A
2542 * 0b1011-0b1111..Should not be used.
2543 */
2544#define ASRC_ASRCNCR_ANCA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK)
2545#define ASRC_ASRCNCR_ANCB_MASK (0xF0U)
2546#define ASRC_ASRCNCR_ANCB_SHIFT (4U)
2547/*! ANCB - ANCB
2548 * 0b0000..0 channels in B (Pair B is disabled)
2549 * 0b0001..1 channel in B
2550 * 0b0010..2 channels in B
2551 * 0b0011..3 channels in B
2552 * 0b0100..4 channels in B
2553 * 0b0101..5 channels in B
2554 * 0b0110..6 channels in B
2555 * 0b0111..7 channels in B
2556 * 0b1000..8 channels in B
2557 * 0b1001..9 channels in B
2558 * 0b1010..10 channels in B
2559 * 0b1011-0b1111..Should not be used.
2560 */
2561#define ASRC_ASRCNCR_ANCB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK)
2562#define ASRC_ASRCNCR_ANCC_MASK (0xF00U)
2563#define ASRC_ASRCNCR_ANCC_SHIFT (8U)
2564/*! ANCC - ANCC
2565 * 0b0000..0 channels in C (Pair C is disabled)
2566 * 0b0001..1 channel in C
2567 * 0b0010..2 channels in C
2568 * 0b0011..3 channels in C
2569 * 0b0100..4 channels in C
2570 * 0b0101..5 channels in C
2571 * 0b0110..6 channels in C
2572 * 0b0111..7 channels in C
2573 * 0b1000..8 channels in C
2574 * 0b1001..9 channels in C
2575 * 0b1010..10 channels in C
2576 * 0b1011-0b1111..Should not be used.
2577 */
2578#define ASRC_ASRCNCR_ANCC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK)
2579/*! @} */
2580
2581/*! @name ASRCFG - ASRC Filter Configuration Status Register */
2582/*! @{ */
2583#define ASRC_ASRCFG_PREMODA_MASK (0xC0U)
2584#define ASRC_ASRCFG_PREMODA_SHIFT (6U)
2585/*! PREMODA - PREMODA
2586 * 0b00..Select Upsampling-by-2 as defined in
2587 * 0b01..Select Direct-Connection as defined in
2588 * 0b10..Select Downsampling-by-2 as defined in
2589 * 0b11..Select passthrough mode. In this case, POSTMODA[1-0] have no use.
2590 */
2591#define ASRC_ASRCFG_PREMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK)
2592#define ASRC_ASRCFG_POSTMODA_MASK (0x300U)
2593#define ASRC_ASRCFG_POSTMODA_SHIFT (8U)
2594/*! POSTMODA - POSTMODA
2595 * 0b00..Select Upsampling-by-2 as defined in
2596 * 0b01..Select Direct-Connection as defined in
2597 * 0b10..Select Downsampling-by-2 as defined in
2598 */
2599#define ASRC_ASRCFG_POSTMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK)
2600#define ASRC_ASRCFG_PREMODB_MASK (0xC00U)
2601#define ASRC_ASRCFG_PREMODB_SHIFT (10U)
2602/*! PREMODB - PREMODB
2603 * 0b00..Select Upsampling-by-2 as defined in
2604 * 0b01..Select Direct-Connection as defined in
2605 * 0b10..Select Downsampling-by-2 as defined in
2606 * 0b11..Select passthrough mode. In this case, POSTMODB[1-0] have no use.
2607 */
2608#define ASRC_ASRCFG_PREMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK)
2609#define ASRC_ASRCFG_POSTMODB_MASK (0x3000U)
2610#define ASRC_ASRCFG_POSTMODB_SHIFT (12U)
2611/*! POSTMODB - POSTMODB
2612 * 0b00..Select Upsampling-by-2 as defined in
2613 * 0b01..Select Direct-Connection as defined in
2614 * 0b10..Select Downsampling-by-2 as defined in
2615 */
2616#define ASRC_ASRCFG_POSTMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK)
2617#define ASRC_ASRCFG_PREMODC_MASK (0xC000U)
2618#define ASRC_ASRCFG_PREMODC_SHIFT (14U)
2619/*! PREMODC - PREMODC
2620 * 0b00..Select Upsampling-by-2 as defined in
2621 * 0b01..Select Direct-Connection as defined in
2622 * 0b10..Select Downsampling-by-2 as defined in
2623 * 0b11..Select passthrough mode. In this case, POSTMODC[1-0] have no use.
2624 */
2625#define ASRC_ASRCFG_PREMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK)
2626#define ASRC_ASRCFG_POSTMODC_MASK (0x30000U)
2627#define ASRC_ASRCFG_POSTMODC_SHIFT (16U)
2628/*! POSTMODC - POSTMODC
2629 * 0b00..Select Upsampling-by-2 as defined in Signal Processing Flow.
2630 * 0b01..Select Direct-Connection as defined in Signal Processing Flow.
2631 * 0b10..Select Downsampling-by-2 as defined in Signal Processing Flow.
2632 */
2633#define ASRC_ASRCFG_POSTMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK)
2634#define ASRC_ASRCFG_NDPRA_MASK (0x40000U)
2635#define ASRC_ASRCFG_NDPRA_SHIFT (18U)
2636/*! NDPRA - NDPRA
2637 * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
2638 * 0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
2639 */
2640#define ASRC_ASRCFG_NDPRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK)
2641#define ASRC_ASRCFG_NDPRB_MASK (0x80000U)
2642#define ASRC_ASRCFG_NDPRB_SHIFT (19U)
2643/*! NDPRB - NDPRB
2644 * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
2645 * 0b1..Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM.
2646 */
2647#define ASRC_ASRCFG_NDPRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK)
2648#define ASRC_ASRCFG_NDPRC_MASK (0x100000U)
2649#define ASRC_ASRCFG_NDPRC_SHIFT (20U)
2650/*! NDPRC - NDPRC
2651 * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
2652 * 0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
2653 */
2654#define ASRC_ASRCFG_NDPRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK)
2655#define ASRC_ASRCFG_INIRQA_MASK (0x200000U)
2656#define ASRC_ASRCFG_INIRQA_SHIFT (21U)
2657/*! INIRQA - INIRQA
2658 */
2659#define ASRC_ASRCFG_INIRQA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK)
2660#define ASRC_ASRCFG_INIRQB_MASK (0x400000U)
2661#define ASRC_ASRCFG_INIRQB_SHIFT (22U)
2662/*! INIRQB - INIRQB
2663 */
2664#define ASRC_ASRCFG_INIRQB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK)
2665#define ASRC_ASRCFG_INIRQC_MASK (0x800000U)
2666#define ASRC_ASRCFG_INIRQC_SHIFT (23U)
2667/*! INIRQC - INIRQC
2668 */
2669#define ASRC_ASRCFG_INIRQC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK)
2670/*! @} */
2671
2672/*! @name ASRCSR - ASRC Clock Source Register */
2673/*! @{ */
2674#define ASRC_ASRCSR_AICSA_MASK (0xFU)
2675#define ASRC_ASRCSR_AICSA_SHIFT (0U)
2676/*! AICSA - AICSA
2677 * 0b0000..bit clock 0
2678 * 0b0001..bit clock 1
2679 * 0b0010..bit clock 2
2680 * 0b0011..bit clock 3
2681 * 0b0100..bit clock 4
2682 * 0b0101..bit clock 5
2683 * 0b0110..bit clock 6
2684 * 0b0111..bit clock 7
2685 * 0b1000..bit clock 8
2686 * 0b1001..bit clock 9
2687 * 0b1010..bit clock A
2688 * 0b1011..bit clock B
2689 * 0b1100..bit clock C
2690 * 0b1101..bit clock D
2691 * 0b1110..bit clock E
2692 * 0b1111..clock disabled, connected to zero
2693 */
2694#define ASRC_ASRCSR_AICSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK)
2695#define ASRC_ASRCSR_AICSB_MASK (0xF0U)
2696#define ASRC_ASRCSR_AICSB_SHIFT (4U)
2697/*! AICSB - AICSB
2698 * 0b0000..bit clock 0
2699 * 0b0001..bit clock 1
2700 * 0b0010..bit clock 2
2701 * 0b0011..bit clock 3
2702 * 0b0100..bit clock 4
2703 * 0b0101..bit clock 5
2704 * 0b0110..bit clock 6
2705 * 0b0111..bit clock 7
2706 * 0b1000..bit clock 8
2707 * 0b1001..bit clock 9
2708 * 0b1010..bit clock A
2709 * 0b1011..bit clock B
2710 * 0b1100..bit clock C
2711 * 0b1101..bit clock D
2712 * 0b1110..bit clock E
2713 * 0b1111..clock disabled, connected to zero
2714 */
2715#define ASRC_ASRCSR_AICSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK)
2716#define ASRC_ASRCSR_AICSC_MASK (0xF00U)
2717#define ASRC_ASRCSR_AICSC_SHIFT (8U)
2718/*! AICSC - AICSC
2719 * 0b0000..bit clock 0
2720 * 0b0001..bit clock 1
2721 * 0b0010..bit clock 2
2722 * 0b0011..bit clock 3
2723 * 0b0100..bit clock 4
2724 * 0b0101..bit clock 5
2725 * 0b0110..bit clock 6
2726 * 0b0111..bit clock 7
2727 * 0b1000..bit clock 8
2728 * 0b1001..bit clock 9
2729 * 0b1010..bit clock A
2730 * 0b1011..bit clock B
2731 * 0b1100..bit clock C
2732 * 0b1101..bit clock D
2733 * 0b1110..bit clock E
2734 * 0b1111..clock disabled, connected to zero
2735 */
2736#define ASRC_ASRCSR_AICSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK)
2737#define ASRC_ASRCSR_AOCSA_MASK (0xF000U)
2738#define ASRC_ASRCSR_AOCSA_SHIFT (12U)
2739/*! AOCSA - AOCSA
2740 * 0b0000..bit clock 0
2741 * 0b0001..bit clock 1
2742 * 0b0010..bit clock 2
2743 * 0b0011..bit clock 3
2744 * 0b0100..bit clock 4
2745 * 0b0101..bit clock 5
2746 * 0b0110..bit clock 6
2747 * 0b0111..bit clock 7
2748 * 0b1000..bit clock 8
2749 * 0b1001..bit clock 9
2750 * 0b1010..bit clock A
2751 * 0b1011..bit clock B
2752 * 0b1100..bit clock C
2753 * 0b1101..bit clock D
2754 * 0b1110..bit clock E
2755 * 0b1111..clock disabled, connected to zero
2756 */
2757#define ASRC_ASRCSR_AOCSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK)
2758#define ASRC_ASRCSR_AOCSB_MASK (0xF0000U)
2759#define ASRC_ASRCSR_AOCSB_SHIFT (16U)
2760/*! AOCSB - AOCSB
2761 * 0b0000..bit clock 0
2762 * 0b0001..bit clock 1
2763 * 0b0010..bit clock 2
2764 * 0b0011..bit clock 3
2765 * 0b0100..bit clock 4
2766 * 0b0101..bit clock 5
2767 * 0b0110..bit clock 6
2768 * 0b0111..bit clock 7
2769 * 0b1000..bit clock 8
2770 * 0b1001..bit clock 9
2771 * 0b1010..bit clock A
2772 * 0b1011..bit clock B
2773 * 0b1100..bit clock C
2774 * 0b1101..bit clock D
2775 * 0b1110..bit clock E
2776 * 0b1111..clock disabled, connected to zero
2777 */
2778#define ASRC_ASRCSR_AOCSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK)
2779#define ASRC_ASRCSR_AOCSC_MASK (0xF00000U)
2780#define ASRC_ASRCSR_AOCSC_SHIFT (20U)
2781/*! AOCSC - AOCSC
2782 * 0b0000..bit clock 0
2783 * 0b0001..bit clock 1
2784 * 0b0010..bit clock 2
2785 * 0b0011..bit clock 3
2786 * 0b0100..bit clock 4
2787 * 0b0101..bit clock 5
2788 * 0b0110..bit clock 6
2789 * 0b0111..bit clock 7
2790 * 0b1000..bit clock 8
2791 * 0b1001..bit clock 9
2792 * 0b1010..bit clock A
2793 * 0b1011..bit clock B
2794 * 0b1100..bit clock C
2795 * 0b1101..bit clock D
2796 * 0b1110..bit clock E
2797 * 0b1111..clock disabled, connected to zero
2798 */
2799#define ASRC_ASRCSR_AOCSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK)
2800/*! @} */
2801
2802/*! @name ASRCDR1 - ASRC Clock Divider Register 1 */
2803/*! @{ */
2804#define ASRC_ASRCDR1_AICPA_MASK (0x7U)
2805#define ASRC_ASRCDR1_AICPA_SHIFT (0U)
2806/*! AICPA - AICPA
2807 */
2808#define ASRC_ASRCDR1_AICPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK)
2809#define ASRC_ASRCDR1_AICDA_MASK (0x38U)
2810#define ASRC_ASRCDR1_AICDA_SHIFT (3U)
2811/*! AICDA - AICDA
2812 */
2813#define ASRC_ASRCDR1_AICDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK)
2814#define ASRC_ASRCDR1_AICPB_MASK (0x1C0U)
2815#define ASRC_ASRCDR1_AICPB_SHIFT (6U)
2816/*! AICPB - AICPB
2817 */
2818#define ASRC_ASRCDR1_AICPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK)
2819#define ASRC_ASRCDR1_AICDB_MASK (0xE00U)
2820#define ASRC_ASRCDR1_AICDB_SHIFT (9U)
2821/*! AICDB - AICDB
2822 */
2823#define ASRC_ASRCDR1_AICDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK)
2824#define ASRC_ASRCDR1_AOCPA_MASK (0x7000U)
2825#define ASRC_ASRCDR1_AOCPA_SHIFT (12U)
2826/*! AOCPA - AOCPA
2827 */
2828#define ASRC_ASRCDR1_AOCPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK)
2829#define ASRC_ASRCDR1_AOCDA_MASK (0x38000U)
2830#define ASRC_ASRCDR1_AOCDA_SHIFT (15U)
2831/*! AOCDA - AOCDA
2832 */
2833#define ASRC_ASRCDR1_AOCDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK)
2834#define ASRC_ASRCDR1_AOCPB_MASK (0x1C0000U)
2835#define ASRC_ASRCDR1_AOCPB_SHIFT (18U)
2836/*! AOCPB - AOCPB
2837 */
2838#define ASRC_ASRCDR1_AOCPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK)
2839#define ASRC_ASRCDR1_AOCDB_MASK (0xE00000U)
2840#define ASRC_ASRCDR1_AOCDB_SHIFT (21U)
2841/*! AOCDB - AOCDB
2842 */
2843#define ASRC_ASRCDR1_AOCDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK)
2844/*! @} */
2845
2846/*! @name ASRCDR2 - ASRC Clock Divider Register 2 */
2847/*! @{ */
2848#define ASRC_ASRCDR2_AICPC_MASK (0x7U)
2849#define ASRC_ASRCDR2_AICPC_SHIFT (0U)
2850/*! AICPC - AICPC
2851 */
2852#define ASRC_ASRCDR2_AICPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK)
2853#define ASRC_ASRCDR2_AICDC_MASK (0x38U)
2854#define ASRC_ASRCDR2_AICDC_SHIFT (3U)
2855/*! AICDC - AICDC
2856 */
2857#define ASRC_ASRCDR2_AICDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK)
2858#define ASRC_ASRCDR2_AOCPC_MASK (0x1C0U)
2859#define ASRC_ASRCDR2_AOCPC_SHIFT (6U)
2860/*! AOCPC - AOCPC
2861 */
2862#define ASRC_ASRCDR2_AOCPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK)
2863#define ASRC_ASRCDR2_AOCDC_MASK (0xE00U)
2864#define ASRC_ASRCDR2_AOCDC_SHIFT (9U)
2865/*! AOCDC - AOCDC
2866 */
2867#define ASRC_ASRCDR2_AOCDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK)
2868/*! @} */
2869
2870/*! @name ASRSTR - ASRC Status Register */
2871/*! @{ */
2872#define ASRC_ASRSTR_AIDEA_MASK (0x1U)
2873#define ASRC_ASRSTR_AIDEA_SHIFT (0U)
2874/*! AIDEA - AIDEA
2875 */
2876#define ASRC_ASRSTR_AIDEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK)
2877#define ASRC_ASRSTR_AIDEB_MASK (0x2U)
2878#define ASRC_ASRSTR_AIDEB_SHIFT (1U)
2879/*! AIDEB - AIDEB
2880 */
2881#define ASRC_ASRSTR_AIDEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK)
2882#define ASRC_ASRSTR_AIDEC_MASK (0x4U)
2883#define ASRC_ASRSTR_AIDEC_SHIFT (2U)
2884/*! AIDEC - AIDEC
2885 */
2886#define ASRC_ASRSTR_AIDEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK)
2887#define ASRC_ASRSTR_AODFA_MASK (0x8U)
2888#define ASRC_ASRSTR_AODFA_SHIFT (3U)
2889/*! AODFA - AODFA
2890 */
2891#define ASRC_ASRSTR_AODFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK)
2892#define ASRC_ASRSTR_AODFB_MASK (0x10U)
2893#define ASRC_ASRSTR_AODFB_SHIFT (4U)
2894/*! AODFB - AODFB
2895 */
2896#define ASRC_ASRSTR_AODFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK)
2897#define ASRC_ASRSTR_AODFC_MASK (0x20U)
2898#define ASRC_ASRSTR_AODFC_SHIFT (5U)
2899/*! AODFC - AODFC
2900 */
2901#define ASRC_ASRSTR_AODFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK)
2902#define ASRC_ASRSTR_AOLE_MASK (0x40U)
2903#define ASRC_ASRSTR_AOLE_SHIFT (6U)
2904/*! AOLE - AOLE
2905 */
2906#define ASRC_ASRSTR_AOLE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK)
2907#define ASRC_ASRSTR_FPWT_MASK (0x80U)
2908#define ASRC_ASRSTR_FPWT_SHIFT (7U)
2909/*! FPWT - FPWT
2910 */
2911#define ASRC_ASRSTR_FPWT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK)
2912#define ASRC_ASRSTR_AIDUA_MASK (0x100U)
2913#define ASRC_ASRSTR_AIDUA_SHIFT (8U)
2914/*! AIDUA - AIDUA
2915 */
2916#define ASRC_ASRSTR_AIDUA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK)
2917#define ASRC_ASRSTR_AIDUB_MASK (0x200U)
2918#define ASRC_ASRSTR_AIDUB_SHIFT (9U)
2919/*! AIDUB - AIDUB
2920 */
2921#define ASRC_ASRSTR_AIDUB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK)
2922#define ASRC_ASRSTR_AIDUC_MASK (0x400U)
2923#define ASRC_ASRSTR_AIDUC_SHIFT (10U)
2924/*! AIDUC - AIDUC
2925 */
2926#define ASRC_ASRSTR_AIDUC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK)
2927#define ASRC_ASRSTR_AODOA_MASK (0x800U)
2928#define ASRC_ASRSTR_AODOA_SHIFT (11U)
2929/*! AODOA - AODOA
2930 */
2931#define ASRC_ASRSTR_AODOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK)
2932#define ASRC_ASRSTR_AODOB_MASK (0x1000U)
2933#define ASRC_ASRSTR_AODOB_SHIFT (12U)
2934/*! AODOB - AODOB
2935 */
2936#define ASRC_ASRSTR_AODOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK)
2937#define ASRC_ASRSTR_AODOC_MASK (0x2000U)
2938#define ASRC_ASRSTR_AODOC_SHIFT (13U)
2939/*! AODOC - AODOC
2940 */
2941#define ASRC_ASRSTR_AODOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK)
2942#define ASRC_ASRSTR_AIOLA_MASK (0x4000U)
2943#define ASRC_ASRSTR_AIOLA_SHIFT (14U)
2944/*! AIOLA - AIOLA
2945 */
2946#define ASRC_ASRSTR_AIOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK)
2947#define ASRC_ASRSTR_AIOLB_MASK (0x8000U)
2948#define ASRC_ASRSTR_AIOLB_SHIFT (15U)
2949/*! AIOLB - AIOLB
2950 */
2951#define ASRC_ASRSTR_AIOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK)
2952#define ASRC_ASRSTR_AIOLC_MASK (0x10000U)
2953#define ASRC_ASRSTR_AIOLC_SHIFT (16U)
2954/*! AIOLC - AIOLC
2955 */
2956#define ASRC_ASRSTR_AIOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK)
2957#define ASRC_ASRSTR_AOOLA_MASK (0x20000U)
2958#define ASRC_ASRSTR_AOOLA_SHIFT (17U)
2959/*! AOOLA - AOOLA
2960 */
2961#define ASRC_ASRSTR_AOOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK)
2962#define ASRC_ASRSTR_AOOLB_MASK (0x40000U)
2963#define ASRC_ASRSTR_AOOLB_SHIFT (18U)
2964/*! AOOLB - AOOLB
2965 */
2966#define ASRC_ASRSTR_AOOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK)
2967#define ASRC_ASRSTR_AOOLC_MASK (0x80000U)
2968#define ASRC_ASRSTR_AOOLC_SHIFT (19U)
2969/*! AOOLC - AOOLC
2970 */
2971#define ASRC_ASRSTR_AOOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK)
2972#define ASRC_ASRSTR_ATQOL_MASK (0x100000U)
2973#define ASRC_ASRSTR_ATQOL_SHIFT (20U)
2974/*! ATQOL - ATQOL
2975 */
2976#define ASRC_ASRSTR_ATQOL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK)
2977#define ASRC_ASRSTR_DSLCNT_MASK (0x200000U)
2978#define ASRC_ASRSTR_DSLCNT_SHIFT (21U)
2979/*! DSLCNT - DSLCNT
2980 */
2981#define ASRC_ASRSTR_DSLCNT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK)
2982/*! @} */
2983
2984/*! @name ASRPM - ASRC Parameter Register n */
2985/*! @{ */
2986#define ASRC_ASRPM_PARAMETER_VALUE_MASK (0xFFFFFFU)
2987#define ASRC_ASRPM_PARAMETER_VALUE_SHIFT (0U)
2988/*! PARAMETER_VALUE - PARAMETER_VALUE
2989 */
2990#define ASRC_ASRPM_PARAMETER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPM_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPM_PARAMETER_VALUE_MASK)
2991/*! @} */
2992
2993/* The count of ASRC_ASRPM */
2994#define ASRC_ASRPM_COUNT (5U)
2995
2996/*! @name ASRTFR1 - ASRC ASRC Task Queue FIFO Register 1 */
2997/*! @{ */
2998#define ASRC_ASRTFR1_TF_BASE_MASK (0x1FC0U)
2999#define ASRC_ASRTFR1_TF_BASE_SHIFT (6U)
3000/*! TF_BASE - TF_BASE
3001 */
3002#define ASRC_ASRTFR1_TF_BASE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK)
3003#define ASRC_ASRTFR1_TF_FILL_MASK (0xFE000U)
3004#define ASRC_ASRTFR1_TF_FILL_SHIFT (13U)
3005/*! TF_FILL - TF_FILL
3006 */
3007#define ASRC_ASRTFR1_TF_FILL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK)
3008/*! @} */
3009
3010/*! @name ASRCCR - ASRC Channel Counter Register */
3011/*! @{ */
3012#define ASRC_ASRCCR_ACIA_MASK (0xFU)
3013#define ASRC_ASRCCR_ACIA_SHIFT (0U)
3014/*! ACIA - ACIA
3015 */
3016#define ASRC_ASRCCR_ACIA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK)
3017#define ASRC_ASRCCR_ACIB_MASK (0xF0U)
3018#define ASRC_ASRCCR_ACIB_SHIFT (4U)
3019/*! ACIB - ACIB
3020 */
3021#define ASRC_ASRCCR_ACIB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK)
3022#define ASRC_ASRCCR_ACIC_MASK (0xF00U)
3023#define ASRC_ASRCCR_ACIC_SHIFT (8U)
3024/*! ACIC - ACIC
3025 */
3026#define ASRC_ASRCCR_ACIC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK)
3027#define ASRC_ASRCCR_ACOA_MASK (0xF000U)
3028#define ASRC_ASRCCR_ACOA_SHIFT (12U)
3029/*! ACOA - ACOA
3030 */
3031#define ASRC_ASRCCR_ACOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK)
3032#define ASRC_ASRCCR_ACOB_MASK (0xF0000U)
3033#define ASRC_ASRCCR_ACOB_SHIFT (16U)
3034/*! ACOB - ACOB
3035 */
3036#define ASRC_ASRCCR_ACOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK)
3037#define ASRC_ASRCCR_ACOC_MASK (0xF00000U)
3038#define ASRC_ASRCCR_ACOC_SHIFT (20U)
3039/*! ACOC - ACOC
3040 */
3041#define ASRC_ASRCCR_ACOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK)
3042/*! @} */
3043
3044/*! @name ASRDIA - ASRC Data Input Register for Pair x */
3045/*! @{ */
3046#define ASRC_ASRDIA_DATA_MASK (0xFFFFFFU)
3047#define ASRC_ASRDIA_DATA_SHIFT (0U)
3048/*! DATA - DATA
3049 */
3050#define ASRC_ASRDIA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK)
3051/*! @} */
3052
3053/*! @name ASRDOA - ASRC Data Output Register for Pair x */
3054/*! @{ */
3055#define ASRC_ASRDOA_DATA_MASK (0xFFFFFFU)
3056#define ASRC_ASRDOA_DATA_SHIFT (0U)
3057/*! DATA - DATA
3058 */
3059#define ASRC_ASRDOA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK)
3060/*! @} */
3061
3062/*! @name ASRDIB - ASRC Data Input Register for Pair x */
3063/*! @{ */
3064#define ASRC_ASRDIB_DATA_MASK (0xFFFFFFU)
3065#define ASRC_ASRDIB_DATA_SHIFT (0U)
3066/*! DATA - DATA
3067 */
3068#define ASRC_ASRDIB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK)
3069/*! @} */
3070
3071/*! @name ASRDOB - ASRC Data Output Register for Pair x */
3072/*! @{ */
3073#define ASRC_ASRDOB_DATA_MASK (0xFFFFFFU)
3074#define ASRC_ASRDOB_DATA_SHIFT (0U)
3075/*! DATA - DATA
3076 */
3077#define ASRC_ASRDOB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK)
3078/*! @} */
3079
3080/*! @name ASRDIC - ASRC Data Input Register for Pair x */
3081/*! @{ */
3082#define ASRC_ASRDIC_DATA_MASK (0xFFFFFFU)
3083#define ASRC_ASRDIC_DATA_SHIFT (0U)
3084/*! DATA - DATA
3085 */
3086#define ASRC_ASRDIC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK)
3087/*! @} */
3088
3089/*! @name ASRDOC - ASRC Data Output Register for Pair x */
3090/*! @{ */
3091#define ASRC_ASRDOC_DATA_MASK (0xFFFFFFU)
3092#define ASRC_ASRDOC_DATA_SHIFT (0U)
3093/*! DATA - DATA
3094 */
3095#define ASRC_ASRDOC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK)
3096/*! @} */
3097
3098/*! @name ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part */
3099/*! @{ */
3100#define ASRC_ASRIDRHA_IDRATIOA_H_MASK (0xFFU)
3101#define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT (0U)
3102/*! IDRATIOA_H - IDRATIOA_H
3103 */
3104#define ASRC_ASRIDRHA_IDRATIOA_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK)
3105/*! @} */
3106
3107/*! @name ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part */
3108/*! @{ */
3109#define ASRC_ASRIDRLA_IDRATIOA_L_MASK (0xFFFFFFU)
3110#define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT (0U)
3111/*! IDRATIOA_L - IDRATIOA_L
3112 */
3113#define ASRC_ASRIDRLA_IDRATIOA_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK)
3114/*! @} */
3115
3116/*! @name ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part */
3117/*! @{ */
3118#define ASRC_ASRIDRHB_IDRATIOB_H_MASK (0xFFU)
3119#define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT (0U)
3120/*! IDRATIOB_H - IDRATIOB_H
3121 */
3122#define ASRC_ASRIDRHB_IDRATIOB_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK)
3123/*! @} */
3124
3125/*! @name ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part */
3126/*! @{ */
3127#define ASRC_ASRIDRLB_IDRATIOB_L_MASK (0xFFFFFFU)
3128#define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT (0U)
3129/*! IDRATIOB_L - IDRATIOB_L
3130 */
3131#define ASRC_ASRIDRLB_IDRATIOB_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK)
3132/*! @} */
3133
3134/*! @name ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part */
3135/*! @{ */
3136#define ASRC_ASRIDRHC_IDRATIOC_H_MASK (0xFFU)
3137#define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT (0U)
3138/*! IDRATIOC_H - IDRATIOC_H
3139 */
3140#define ASRC_ASRIDRHC_IDRATIOC_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK)
3141/*! @} */
3142
3143/*! @name ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part */
3144/*! @{ */
3145#define ASRC_ASRIDRLC_IDRATIOC_L_MASK (0xFFFFFFU)
3146#define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT (0U)
3147/*! IDRATIOC_L - IDRATIOC_L
3148 */
3149#define ASRC_ASRIDRLC_IDRATIOC_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK)
3150/*! @} */
3151
3152/*! @name ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock */
3153/*! @{ */
3154#define ASRC_ASR76K_ASR76K_MASK (0x1FFFFU)
3155#define ASRC_ASR76K_ASR76K_SHIFT (0U)
3156/*! ASR76K - ASR76K
3157 */
3158#define ASRC_ASR76K_ASR76K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK)
3159/*! @} */
3160
3161/*! @name ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock */
3162/*! @{ */
3163#define ASRC_ASR56K_ASR56K_MASK (0x1FFFFU)
3164#define ASRC_ASR56K_ASR56K_SHIFT (0U)
3165/*! ASR56K - ASR56K
3166 */
3167#define ASRC_ASR56K_ASR56K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK)
3168/*! @} */
3169
3170/*! @name ASRMCRA - ASRC Misc Control Register for Pair A */
3171/*! @{ */
3172#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK (0x3FU)
3173#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT (0U)
3174/*! INFIFO_THRESHOLDA - INFIFO_THRESHOLDA
3175 */
3176#define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK)
3177#define ASRC_ASRMCRA_RSYNOFA_MASK (0x400U)
3178#define ASRC_ASRMCRA_RSYNOFA_SHIFT (10U)
3179/*! RSYNOFA - RSYNOFA
3180 */
3181#define ASRC_ASRMCRA_RSYNOFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK)
3182#define ASRC_ASRMCRA_RSYNIFA_MASK (0x800U)
3183#define ASRC_ASRMCRA_RSYNIFA_SHIFT (11U)
3184/*! RSYNIFA - RSYNIFA
3185 */
3186#define ASRC_ASRMCRA_RSYNIFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK)
3187#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK (0x3F000U)
3188#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT (12U)
3189/*! OUTFIFO_THRESHOLDA - OUTFIFO_THRESHOLDA
3190 */
3191#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK)
3192#define ASRC_ASRMCRA_BYPASSPOLYA_MASK (0x100000U)
3193#define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT (20U)
3194/*! BYPASSPOLYA - BYPASSPOLYA
3195 * 0b1..Bypass polyphase filtering.
3196 * 0b0..Don't bypass polyphase filtering.
3197 */
3198#define ASRC_ASRMCRA_BYPASSPOLYA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK)
3199#define ASRC_ASRMCRA_BUFSTALLA_MASK (0x200000U)
3200#define ASRC_ASRMCRA_BUFSTALLA_SHIFT (21U)
3201/*! BUFSTALLA - BUFSTALLA
3202 * 0b1..Stall Pair A conversion in case of near empty/full FIFO conditions.
3203 * 0b0..Don't stall Pair A conversion even in case of near empty/full FIFO conditions.
3204 */
3205#define ASRC_ASRMCRA_BUFSTALLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK)
3206#define ASRC_ASRMCRA_EXTTHRSHA_MASK (0x400000U)
3207#define ASRC_ASRMCRA_EXTTHRSHA_SHIFT (22U)
3208/*! EXTTHRSHA - EXTTHRSHA
3209 * 0b1..Use external defined thresholds.
3210 * 0b0..Use default thresholds.
3211 */
3212#define ASRC_ASRMCRA_EXTTHRSHA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK)
3213#define ASRC_ASRMCRA_ZEROBUFA_MASK (0x800000U)
3214#define ASRC_ASRMCRA_ZEROBUFA_SHIFT (23U)
3215/*! ZEROBUFA - ZEROBUFA
3216 * 0b1..Don't zeroize the buffer
3217 * 0b0..Zeroize the buffer
3218 */
3219#define ASRC_ASRMCRA_ZEROBUFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK)
3220/*! @} */
3221
3222/*! @name ASRFSTA - ASRC FIFO Status Register for Pair A */
3223/*! @{ */
3224#define ASRC_ASRFSTA_INFIFO_FILLA_MASK (0x7FU)
3225#define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT (0U)
3226/*! INFIFO_FILLA - INFIFO_FILLA
3227 */
3228#define ASRC_ASRFSTA_INFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK)
3229#define ASRC_ASRFSTA_IAEA_MASK (0x800U)
3230#define ASRC_ASRFSTA_IAEA_SHIFT (11U)
3231/*! IAEA - IAEA
3232 */
3233#define ASRC_ASRFSTA_IAEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK)
3234#define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK (0x7F000U)
3235#define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT (12U)
3236/*! OUTFIFO_FILLA - OUTFIFO_FILLA
3237 */
3238#define ASRC_ASRFSTA_OUTFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK)
3239#define ASRC_ASRFSTA_OAFA_MASK (0x800000U)
3240#define ASRC_ASRFSTA_OAFA_SHIFT (23U)
3241/*! OAFA - OAFA
3242 */
3243#define ASRC_ASRFSTA_OAFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK)
3244/*! @} */
3245
3246/*! @name ASRMCRB - ASRC Misc Control Register for Pair B */
3247/*! @{ */
3248#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK (0x3FU)
3249#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT (0U)
3250/*! INFIFO_THRESHOLDB - INFIFO_THRESHOLDB
3251 */
3252#define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK)
3253#define ASRC_ASRMCRB_RSYNOFB_MASK (0x400U)
3254#define ASRC_ASRMCRB_RSYNOFB_SHIFT (10U)
3255/*! RSYNOFB - RSYNOFB
3256 */
3257#define ASRC_ASRMCRB_RSYNOFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK)
3258#define ASRC_ASRMCRB_RSYNIFB_MASK (0x800U)
3259#define ASRC_ASRMCRB_RSYNIFB_SHIFT (11U)
3260/*! RSYNIFB - RSYNIFB
3261 */
3262#define ASRC_ASRMCRB_RSYNIFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK)
3263#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK (0x3F000U)
3264#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT (12U)
3265/*! OUTFIFO_THRESHOLDB - OUTFIFO_THRESHOLDB
3266 */
3267#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK)
3268#define ASRC_ASRMCRB_BYPASSPOLYB_MASK (0x100000U)
3269#define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT (20U)
3270/*! BYPASSPOLYB - BYPASSPOLYB
3271 * 0b1..Bypass polyphase filtering.
3272 * 0b0..Don't bypass polyphase filtering.
3273 */
3274#define ASRC_ASRMCRB_BYPASSPOLYB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK)
3275#define ASRC_ASRMCRB_BUFSTALLB_MASK (0x200000U)
3276#define ASRC_ASRMCRB_BUFSTALLB_SHIFT (21U)
3277/*! BUFSTALLB - BUFSTALLB
3278 * 0b1..Stall Pair B conversion in case of near empty/full FIFO conditions.
3279 * 0b0..Don't stall Pair B conversion even in case of near empty/full FIFO conditions.
3280 */
3281#define ASRC_ASRMCRB_BUFSTALLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK)
3282#define ASRC_ASRMCRB_EXTTHRSHB_MASK (0x400000U)
3283#define ASRC_ASRMCRB_EXTTHRSHB_SHIFT (22U)
3284/*! EXTTHRSHB - EXTTHRSHB
3285 * 0b1..Use external defined thresholds.
3286 * 0b0..Use default thresholds.
3287 */
3288#define ASRC_ASRMCRB_EXTTHRSHB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK)
3289#define ASRC_ASRMCRB_ZEROBUFB_MASK (0x800000U)
3290#define ASRC_ASRMCRB_ZEROBUFB_SHIFT (23U)
3291/*! ZEROBUFB - ZEROBUFB
3292 * 0b1..Don't zeroize the buffer
3293 * 0b0..Zeroize the buffer
3294 */
3295#define ASRC_ASRMCRB_ZEROBUFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK)
3296/*! @} */
3297
3298/*! @name ASRFSTB - ASRC FIFO Status Register for Pair B */
3299/*! @{ */
3300#define ASRC_ASRFSTB_INFIFO_FILLB_MASK (0x7FU)
3301#define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT (0U)
3302/*! INFIFO_FILLB - INFIFO_FILLB
3303 */
3304#define ASRC_ASRFSTB_INFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK)
3305#define ASRC_ASRFSTB_IAEB_MASK (0x800U)
3306#define ASRC_ASRFSTB_IAEB_SHIFT (11U)
3307/*! IAEB - IAEB
3308 */
3309#define ASRC_ASRFSTB_IAEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK)
3310#define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK (0x7F000U)
3311#define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT (12U)
3312/*! OUTFIFO_FILLB - OUTFIFO_FILLB
3313 */
3314#define ASRC_ASRFSTB_OUTFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK)
3315#define ASRC_ASRFSTB_OAFB_MASK (0x800000U)
3316#define ASRC_ASRFSTB_OAFB_SHIFT (23U)
3317/*! OAFB - OAFB
3318 */
3319#define ASRC_ASRFSTB_OAFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK)
3320/*! @} */
3321
3322/*! @name ASRMCRC - ASRC Misc Control Register for Pair C */
3323/*! @{ */
3324#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK (0x3FU)
3325#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT (0U)
3326/*! INFIFO_THRESHOLDC - INFIFO_THRESHOLDC
3327 */
3328#define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK)
3329#define ASRC_ASRMCRC_RSYNOFC_MASK (0x400U)
3330#define ASRC_ASRMCRC_RSYNOFC_SHIFT (10U)
3331/*! RSYNOFC - RSYNOFC
3332 */
3333#define ASRC_ASRMCRC_RSYNOFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK)
3334#define ASRC_ASRMCRC_RSYNIFC_MASK (0x800U)
3335#define ASRC_ASRMCRC_RSYNIFC_SHIFT (11U)
3336/*! RSYNIFC - RSYNIFC
3337 */
3338#define ASRC_ASRMCRC_RSYNIFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK)
3339#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK (0x3F000U)
3340#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT (12U)
3341/*! OUTFIFO_THRESHOLDC - OUTFIFO_THRESHOLDC
3342 */
3343#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK)
3344#define ASRC_ASRMCRC_BYPASSPOLYC_MASK (0x100000U)
3345#define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT (20U)
3346/*! BYPASSPOLYC - BYPASSPOLYC
3347 * 0b1..Bypass polyphase filtering.
3348 * 0b0..Don't bypass polyphase filtering.
3349 */
3350#define ASRC_ASRMCRC_BYPASSPOLYC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK)
3351#define ASRC_ASRMCRC_BUFSTALLC_MASK (0x200000U)
3352#define ASRC_ASRMCRC_BUFSTALLC_SHIFT (21U)
3353/*! BUFSTALLC - BUFSTALLC
3354 * 0b1..Stall Pair C conversion in case of near empty/full FIFO conditions.
3355 * 0b0..Don't stall Pair C conversion even in case of near empty/full FIFO conditions.
3356 */
3357#define ASRC_ASRMCRC_BUFSTALLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK)
3358#define ASRC_ASRMCRC_EXTTHRSHC_MASK (0x400000U)
3359#define ASRC_ASRMCRC_EXTTHRSHC_SHIFT (22U)
3360/*! EXTTHRSHC - EXTTHRSHC
3361 * 0b1..Use external defined thresholds.
3362 * 0b0..Use default thresholds.
3363 */
3364#define ASRC_ASRMCRC_EXTTHRSHC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK)
3365#define ASRC_ASRMCRC_ZEROBUFC_MASK (0x800000U)
3366#define ASRC_ASRMCRC_ZEROBUFC_SHIFT (23U)
3367/*! ZEROBUFC - ZEROBUFC
3368 * 0b1..Don't zeroize the buffer
3369 * 0b0..Zeroize the buffer
3370 */
3371#define ASRC_ASRMCRC_ZEROBUFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK)
3372/*! @} */
3373
3374/*! @name ASRFSTC - ASRC FIFO Status Register for Pair C */
3375/*! @{ */
3376#define ASRC_ASRFSTC_INFIFO_FILLC_MASK (0x7FU)
3377#define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT (0U)
3378/*! INFIFO_FILLC - INFIFO_FILLC
3379 */
3380#define ASRC_ASRFSTC_INFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK)
3381#define ASRC_ASRFSTC_IAEC_MASK (0x800U)
3382#define ASRC_ASRFSTC_IAEC_SHIFT (11U)
3383/*! IAEC - IAEC
3384 */
3385#define ASRC_ASRFSTC_IAEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK)
3386#define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK (0x7F000U)
3387#define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT (12U)
3388/*! OUTFIFO_FILLC - OUTFIFO_FILLC
3389 */
3390#define ASRC_ASRFSTC_OUTFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK)
3391#define ASRC_ASRFSTC_OAFC_MASK (0x800000U)
3392#define ASRC_ASRFSTC_OAFC_SHIFT (23U)
3393/*! OAFC - OAFC
3394 */
3395#define ASRC_ASRFSTC_OAFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK)
3396/*! @} */
3397
3398/*! @name ASRMCR1 - ASRC Misc Control Register 1 for Pair X */
3399/*! @{ */
3400#define ASRC_ASRMCR1_OW16_MASK (0x1U)
3401#define ASRC_ASRMCR1_OW16_SHIFT (0U)
3402/*! OW16 - OW16
3403 * 0b1..16-bit output data
3404 * 0b0..24-bit output data.
3405 */
3406#define ASRC_ASRMCR1_OW16(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK)
3407#define ASRC_ASRMCR1_OSGN_MASK (0x2U)
3408#define ASRC_ASRMCR1_OSGN_SHIFT (1U)
3409/*! OSGN - OSGN
3410 * 0b1..Sign extension.
3411 * 0b0..No sign extension.
3412 */
3413#define ASRC_ASRMCR1_OSGN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK)
3414#define ASRC_ASRMCR1_OMSB_MASK (0x4U)
3415#define ASRC_ASRMCR1_OMSB_SHIFT (2U)
3416/*! OMSB - OMSB
3417 * 0b1..MSB aligned.
3418 * 0b0..LSB aligned.
3419 */
3420#define ASRC_ASRMCR1_OMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK)
3421#define ASRC_ASRMCR1_IMSB_MASK (0x100U)
3422#define ASRC_ASRMCR1_IMSB_SHIFT (8U)
3423/*! IMSB - IMSB
3424 * 0b1..MSB aligned.
3425 * 0b0..LSB aligned.
3426 */
3427#define ASRC_ASRMCR1_IMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK)
3428#define ASRC_ASRMCR1_IWD_MASK (0xE00U)
3429#define ASRC_ASRMCR1_IWD_SHIFT (9U)
3430/*! IWD - IWD
3431 */
3432#define ASRC_ASRMCR1_IWD(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK)
3433/*! @} */
3434
3435/* The count of ASRC_ASRMCR1 */
3436#define ASRC_ASRMCR1_COUNT (3U)
3437
3438
3439/*!
3440 * @}
3441 */ /* end of group ASRC_Register_Masks */
3442
3443
3444/* ASRC - Peripheral instance base addresses */
3445/** Peripheral ADMA__ASRC0 base address */
3446#define ADMA__ASRC0_BASE (0x59000000u)
3447/** Peripheral ADMA__ASRC0 base pointer */
3448#define ADMA__ASRC0 ((ASRC_Type *)ADMA__ASRC0_BASE)
3449/** Peripheral ADMA__ASRC1 base address */
3450#define ADMA__ASRC1_BASE (0x59800000u)
3451/** Peripheral ADMA__ASRC1 base pointer */
3452#define ADMA__ASRC1 ((ASRC_Type *)ADMA__ASRC1_BASE)
3453/** Array initializer of ASRC peripheral base addresses */
3454#define ASRC_BASE_ADDRS { ADMA__ASRC0_BASE, ADMA__ASRC1_BASE }
3455/** Array initializer of ASRC peripheral base pointers */
3456#define ASRC_BASE_PTRS { ADMA__ASRC0, ADMA__ASRC1 }
3457
3458/*!
3459 * @}
3460 */ /* end of group ASRC_Peripheral_Access_Layer */
3461
3462
3463/* ----------------------------------------------------------------------------
3464 -- BCH Peripheral Access Layer
3465 ---------------------------------------------------------------------------- */
3466
3467/*!
3468 * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer
3469 * @{
3470 */
3471
3472/** BCH - Register Layout Typedef */
3473typedef struct {
3474 struct { /* offset: 0x0 */
3475 __IO uint32_t RW; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */
3476 __IO uint32_t SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */
3477 __IO uint32_t CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */
3478 __IO uint32_t TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */
3479 } CTRL;
3480 struct { /* offset: 0x10 */
3481 __I uint32_t RW; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */
3482 __I uint32_t SET; /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */
3483 __I uint32_t CLR; /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */
3484 __I uint32_t TOG; /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */
3485 } STATUS0;
3486 struct { /* offset: 0x20 */
3487 __IO uint32_t RW; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */
3488 __IO uint32_t SET; /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */
3489 __IO uint32_t CLR; /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */
3490 __IO uint32_t TOG; /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */
3491 } MODE;
3492 struct { /* offset: 0x30 */
3493 __IO uint32_t RW; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */
3494 __IO uint32_t SET; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */
3495 __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */
3496 __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */
3497 } ENCODEPTR;
3498 struct { /* offset: 0x40 */
3499 __IO uint32_t RW; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */
3500 __IO uint32_t SET; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */
3501 __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */
3502 __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */
3503 } DATAPTR;
3504 struct { /* offset: 0x50 */
3505 __IO uint32_t RW; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */
3506 __IO uint32_t SET; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */
3507 __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */
3508 __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */
3509 } METAPTR;
3510 uint8_t RESERVED_0[16];
3511 struct { /* offset: 0x70 */
3512 __IO uint32_t RW; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */
3513 __IO uint32_t SET; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */
3514 __IO uint32_t CLR; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */
3515 __IO uint32_t TOG; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */
3516 } LAYOUTSELECT;
3517 struct { /* offset: 0x80 */
3518 __IO uint32_t RW; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */
3519 __IO uint32_t SET; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */
3520 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */
3521 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */
3522 } FLASH0LAYOUT0;
3523 struct { /* offset: 0x90 */
3524 __IO uint32_t RW; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */
3525 __IO uint32_t SET; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */
3526 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */
3527 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */
3528 } FLASH0LAYOUT1;
3529 struct { /* offset: 0xA0 */
3530 __IO uint32_t RW; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */
3531 __IO uint32_t SET; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */
3532 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */
3533 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */
3534 } FLASH1LAYOUT0;
3535 struct { /* offset: 0xB0 */
3536 __IO uint32_t RW; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */
3537 __IO uint32_t SET; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */
3538 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */
3539 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */
3540 } FLASH1LAYOUT1;
3541 struct { /* offset: 0xC0 */
3542 __IO uint32_t RW; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */
3543 __IO uint32_t SET; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */
3544 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */
3545 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */
3546 } FLASH2LAYOUT0;
3547 struct { /* offset: 0xD0 */
3548 __IO uint32_t RW; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */
3549 __IO uint32_t SET; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */
3550 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */
3551 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */
3552 } FLASH2LAYOUT1;
3553 struct { /* offset: 0xE0 */
3554 __IO uint32_t RW; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */
3555 __IO uint32_t SET; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */
3556 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */
3557 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */
3558 } FLASH3LAYOUT0;
3559 struct { /* offset: 0xF0 */
3560 __IO uint32_t RW; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */
3561 __IO uint32_t SET; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */
3562 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */
3563 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */
3564 } FLASH3LAYOUT1;
3565 struct { /* offset: 0x100 */
3566 __IO uint32_t RW; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */
3567 __IO uint32_t SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */
3568 __IO uint32_t CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */
3569 __IO uint32_t TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */
3570 } DEBUG0;
3571 struct { /* offset: 0x110 */
3572 __I uint32_t RW; /**< KES Debug Read Register, offset: 0x110 */
3573 __I uint32_t SET; /**< KES Debug Read Register, offset: 0x114 */
3574 __I uint32_t CLR; /**< KES Debug Read Register, offset: 0x118 */
3575 __I uint32_t TOG; /**< KES Debug Read Register, offset: 0x11C */
3576 } DBGKESREAD;
3577 struct { /* offset: 0x120 */
3578 __I uint32_t RW; /**< Chien Search Debug Read Register, offset: 0x120 */
3579 __I uint32_t SET; /**< Chien Search Debug Read Register, offset: 0x124 */
3580 __I uint32_t CLR; /**< Chien Search Debug Read Register, offset: 0x128 */
3581 __I uint32_t TOG; /**< Chien Search Debug Read Register, offset: 0x12C */
3582 } DBGCSFEREAD;
3583 struct { /* offset: 0x130 */
3584 __I uint32_t RW; /**< Syndrome Generator Debug Read Register, offset: 0x130 */
3585 __I uint32_t SET; /**< Syndrome Generator Debug Read Register, offset: 0x134 */
3586 __I uint32_t CLR; /**< Syndrome Generator Debug Read Register, offset: 0x138 */
3587 __I uint32_t TOG; /**< Syndrome Generator Debug Read Register, offset: 0x13C */
3588 } DBGSYNDGENREAD;
3589 struct { /* offset: 0x140 */
3590 __I uint32_t RW; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */
3591 __I uint32_t SET; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */
3592 __I uint32_t CLR; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */
3593 __I uint32_t TOG; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */
3594 } DBGAHBMREAD;
3595 struct { /* offset: 0x150 */
3596 __I uint32_t RW; /**< Block Name Register, offset: 0x150 */
3597 __I uint32_t SET; /**< Block Name Register, offset: 0x154 */
3598 __I uint32_t CLR; /**< Block Name Register, offset: 0x158 */
3599 __I uint32_t TOG; /**< Block Name Register, offset: 0x15C */
3600 } BLOCKNAME;
3601 struct { /* offset: 0x160 */
3602 __I uint32_t RW; /**< BCH Version Register, offset: 0x160 */
3603 __I uint32_t SET; /**< BCH Version Register, offset: 0x164 */
3604 __I uint32_t CLR; /**< BCH Version Register, offset: 0x168 */
3605 __I uint32_t TOG; /**< BCH Version Register, offset: 0x16C */
3606 } VERSION;
3607 struct { /* offset: 0x170 */
3608 __IO uint32_t RW; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */
3609 __IO uint32_t SET; /**< Hardware BCH ECC Debug Register 1, offset: 0x174 */
3610 __IO uint32_t CLR; /**< Hardware BCH ECC Debug Register 1, offset: 0x178 */
3611 __IO uint32_t TOG; /**< Hardware BCH ECC Debug Register 1, offset: 0x17C */
3612 } DEBUG1;
3613} BCH_Type;
3614
3615/* ----------------------------------------------------------------------------
3616 -- BCH Register Masks
3617 ---------------------------------------------------------------------------- */
3618
3619/*!
3620 * @addtogroup BCH_Register_Masks BCH Register Masks
3621 * @{
3622 */
3623
3624/*! @name CTRL - Hardware BCH ECC Accelerator Control Register */
3625/*! @{ */
3626#define BCH_CTRL_COMPLETE_IRQ_MASK (0x1U)
3627#define BCH_CTRL_COMPLETE_IRQ_SHIFT (0U)
3628/*! COMPLETE_IRQ - COMPLETE_IRQ
3629 */
3630#define BCH_CTRL_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK)
3631#define BCH_CTRL_RSVD0_MASK (0x2U)
3632#define BCH_CTRL_RSVD0_SHIFT (1U)
3633/*! RSVD0 - This field is reserved.
3634 */
3635#define BCH_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK)
3636#define BCH_CTRL_DEBUG_STALL_IRQ_MASK (0x4U)
3637#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT (2U)
3638/*! DEBUG_STALL_IRQ - DEBUG_STALL_IRQ
3639 */
3640#define BCH_CTRL_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK)
3641#define BCH_CTRL_BM_ERROR_IRQ_MASK (0x8U)
3642#define BCH_CTRL_BM_ERROR_IRQ_SHIFT (3U)
3643/*! BM_ERROR_IRQ - BM_ERROR_IRQ
3644 */
3645#define BCH_CTRL_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK)
3646#define BCH_CTRL_RSVD1_MASK (0xF0U)
3647#define BCH_CTRL_RSVD1_SHIFT (4U)
3648/*! RSVD1 - This field is reserved.
3649 */
3650#define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK)
3651#define BCH_CTRL_COMPLETE_IRQ_EN_MASK (0x100U)
3652#define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT (8U)
3653/*! COMPLETE_IRQ_EN - COMPLETE_IRQ_EN
3654 */
3655#define BCH_CTRL_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK)
3656#define BCH_CTRL_RSVD2_MASK (0x200U)
3657#define BCH_CTRL_RSVD2_SHIFT (9U)
3658/*! RSVD2 - This field is reserved.
3659 */
3660#define BCH_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK)
3661#define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK (0x400U)
3662#define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT (10U)
3663/*! DEBUG_STALL_IRQ_EN - DEBUG_STALL_IRQ_EN
3664 */
3665#define BCH_CTRL_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK)
3666#define BCH_CTRL_RSVD3_MASK (0xF800U)
3667#define BCH_CTRL_RSVD3_SHIFT (11U)
3668/*! RSVD3 - This field is reserved.
3669 */
3670#define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK)
3671#define BCH_CTRL_M2M_ENABLE_MASK (0x10000U)
3672#define BCH_CTRL_M2M_ENABLE_SHIFT (16U)
3673/*! M2M_ENABLE - M2M_ENABLE
3674 */
3675#define BCH_CTRL_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK)
3676#define BCH_CTRL_M2M_ENCODE_MASK (0x20000U)
3677#define BCH_CTRL_M2M_ENCODE_SHIFT (17U)
3678/*! M2M_ENCODE - M2M_ENCODE
3679 */
3680#define BCH_CTRL_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK)
3681#define BCH_CTRL_M2M_LAYOUT_MASK (0xC0000U)
3682#define BCH_CTRL_M2M_LAYOUT_SHIFT (18U)
3683/*! M2M_LAYOUT - M2M_LAYOUT
3684 */
3685#define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK)
3686#define BCH_CTRL_RSVD4_MASK (0x300000U)
3687#define BCH_CTRL_RSVD4_SHIFT (20U)
3688/*! RSVD4 - This field is reserved.
3689 */
3690#define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK)
3691#define BCH_CTRL_DEBUGSYNDROME_MASK (0x400000U)
3692#define BCH_CTRL_DEBUGSYNDROME_SHIFT (22U)
3693/*! DEBUGSYNDROME - DEBUGSYNDROME
3694 */
3695#define BCH_CTRL_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK)
3696#define BCH_CTRL_RSVD5_MASK (0x3F800000U)
3697#define BCH_CTRL_RSVD5_SHIFT (23U)
3698/*! RSVD5 - This field is reserved.
3699 */
3700#define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK)
3701#define BCH_CTRL_CLKGATE_MASK (0x40000000U)
3702#define BCH_CTRL_CLKGATE_SHIFT (30U)
3703/*! CLKGATE - CLKGATE
3704 * 0b0..Allow BCH to operate normally.
3705 * 0b1..Do not clock BCH gates in order to minimize power consumption.
3706 */
3707#define BCH_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK)
3708#define BCH_CTRL_SFTRST_MASK (0x80000000U)
3709#define BCH_CTRL_SFTRST_SHIFT (31U)
3710/*! SFTRST - SFTRST
3711 * 0b0..Allow BCH to operate normally.
3712 * 0b1..Hold BCH in reset.
3713 */
3714#define BCH_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK)
3715/*! @} */
3716
3717/*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */
3718/*! @{ */
3719#define BCH_STATUS0_RSVD0_MASK (0x3U)
3720#define BCH_STATUS0_RSVD0_SHIFT (0U)
3721/*! RSVD0 - This field is reserved.
3722 */
3723#define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK)
3724#define BCH_STATUS0_UNCORRECTABLE_MASK (0x4U)
3725#define BCH_STATUS0_UNCORRECTABLE_SHIFT (2U)
3726/*! UNCORRECTABLE - UNCORRECTABLE
3727 */
3728#define BCH_STATUS0_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK)
3729#define BCH_STATUS0_CORRECTED_MASK (0x8U)
3730#define BCH_STATUS0_CORRECTED_SHIFT (3U)
3731/*! CORRECTED - CORRECTED
3732 */
3733#define BCH_STATUS0_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK)
3734#define BCH_STATUS0_ALLONES_MASK (0x10U)
3735#define BCH_STATUS0_ALLONES_SHIFT (4U)
3736/*! ALLONES - ALLONES
3737 */
3738#define BCH_STATUS0_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK)
3739#define BCH_STATUS0_RSVD1_MASK (0xE0U)
3740#define BCH_STATUS0_RSVD1_SHIFT (5U)
3741/*! RSVD1 - This field is reserved.
3742 */
3743#define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK)
3744#define BCH_STATUS0_STATUS_BLK0_MASK (0xFF00U)
3745#define BCH_STATUS0_STATUS_BLK0_SHIFT (8U)
3746/*! STATUS_BLK0 - STATUS_BLK0
3747 * 0b00000000..No errors found on block.
3748 * 0b00000001..One error found on block.
3749 * 0b00000010..One errors found on block.
3750 * 0b00000011..One errors found on block.
3751 * 0b00000100..One errors found on block.
3752 * 0b11111110..Block exhibited uncorrectable errors.
3753 * 0b11111111..Page is erased.
3754 */
3755#define BCH_STATUS0_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK)
3756#define BCH_STATUS0_COMPLETED_CE_MASK (0xF0000U)
3757#define BCH_STATUS0_COMPLETED_CE_SHIFT (16U)
3758/*! COMPLETED_CE - COMPLETED_CE
3759 */
3760#define BCH_STATUS0_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK)
3761#define BCH_STATUS0_HANDLE_MASK (0xFFF00000U)
3762#define BCH_STATUS0_HANDLE_SHIFT (20U)
3763/*! HANDLE - HANDLE
3764 */
3765#define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK)
3766/*! @} */
3767
3768/*! @name MODE - Hardware ECC Accelerator Mode Register */
3769/*! @{ */
3770#define BCH_MODE_ERASE_THRESHOLD_MASK (0xFFU)
3771#define BCH_MODE_ERASE_THRESHOLD_SHIFT (0U)
3772/*! ERASE_THRESHOLD - ERASE_THRESHOLD
3773 */
3774#define BCH_MODE_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK)
3775#define BCH_MODE_RSVD_MASK (0xFFFFFF00U)
3776#define BCH_MODE_RSVD_SHIFT (8U)
3777/*! RSVD - This field is reserved.
3778 */
3779#define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK)
3780/*! @} */
3781
3782/*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */
3783/*! @{ */
3784#define BCH_ENCODEPTR_ADDR_MASK (0xFFFFFFFFU)
3785#define BCH_ENCODEPTR_ADDR_SHIFT (0U)
3786/*! ADDR - ADDR
3787 */
3788#define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK)
3789/*! @} */
3790
3791/*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */
3792/*! @{ */
3793#define BCH_DATAPTR_ADDR_MASK (0xFFFFFFFFU)
3794#define BCH_DATAPTR_ADDR_SHIFT (0U)
3795/*! ADDR - ADDR
3796 */
3797#define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK)
3798/*! @} */
3799
3800/*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */
3801/*! @{ */
3802#define BCH_METAPTR_ADDR_MASK (0xFFFFFFFFU)
3803#define BCH_METAPTR_ADDR_SHIFT (0U)
3804/*! ADDR - ADDR
3805 */
3806#define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK)
3807/*! @} */
3808
3809/*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */
3810/*! @{ */
3811#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3U)
3812#define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT (0U)
3813/*! CS0_SELECT - CS0_SELECT
3814 */
3815#define BCH_LAYOUTSELECT_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK)
3816#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0xCU)
3817#define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT (2U)
3818/*! CS1_SELECT - CS1_SELECT
3819 */
3820#define BCH_LAYOUTSELECT_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK)
3821#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x30U)
3822#define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT (4U)
3823/*! CS2_SELECT - CS2_SELECT
3824 */
3825#define BCH_LAYOUTSELECT_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK)
3826#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0xC0U)
3827#define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT (6U)
3828/*! CS3_SELECT - CS3_SELECT
3829 */
3830#define BCH_LAYOUTSELECT_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK)
3831#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x300U)
3832#define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT (8U)
3833/*! CS4_SELECT - CS4_SELECT
3834 */
3835#define BCH_LAYOUTSELECT_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK)
3836#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0xC00U)
3837#define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT (10U)
3838/*! CS5_SELECT - CS5_SELECT
3839 */
3840#define BCH_LAYOUTSELECT_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK)
3841#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3000U)
3842#define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT (12U)
3843/*! CS6_SELECT - CS6_SELECT
3844 */
3845#define BCH_LAYOUTSELECT_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK)
3846#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0xC000U)
3847#define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT (14U)
3848/*! CS7_SELECT - CS7_SELECT
3849 */
3850#define BCH_LAYOUTSELECT_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK)
3851#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x30000U)
3852#define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT (16U)
3853/*! CS8_SELECT - CS8_SELECT
3854 */
3855#define BCH_LAYOUTSELECT_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK)
3856#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0xC0000U)
3857#define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT (18U)
3858/*! CS9_SELECT - CS9_SELECT
3859 */
3860#define BCH_LAYOUTSELECT_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK)
3861#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x300000U)
3862#define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT (20U)
3863/*! CS10_SELECT - CS10_SELECT
3864 */
3865#define BCH_LAYOUTSELECT_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK)
3866#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0xC00000U)
3867#define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT (22U)
3868/*! CS11_SELECT - CS11_SELECT
3869 */
3870#define BCH_LAYOUTSELECT_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK)
3871#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3000000U)
3872#define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT (24U)
3873/*! CS12_SELECT - CS12_SELECT
3874 */
3875#define BCH_LAYOUTSELECT_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK)
3876#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0xC000000U)
3877#define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT (26U)
3878/*! CS13_SELECT - CS13_SELECT
3879 */
3880#define BCH_LAYOUTSELECT_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK)
3881#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x30000000U)
3882#define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT (28U)
3883/*! CS14_SELECT - CS14_SELECT
3884 */
3885#define BCH_LAYOUTSELECT_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK)
3886#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0xC0000000U)
3887#define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT (30U)
3888/*! CS15_SELECT - CS15_SELECT
3889 */
3890#define BCH_LAYOUTSELECT_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK)
3891/*! @} */
3892
3893/*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */
3894/*! @{ */
3895#define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
3896#define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT (0U)
3897/*! DATA0_SIZE - DATA0_SIZE
3898 */
3899#define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK)
3900#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
3901#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
3902/*! GF13_0_GF14_1 - GF13_0_GF14_1
3903 */
3904#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK)
3905#define BCH_FLASH0LAYOUT0_ECC0_MASK (0xF800U)
3906#define BCH_FLASH0LAYOUT0_ECC0_SHIFT (11U)
3907/*! ECC0 - ECC0
3908 * 0b00000..No ECC to be performed
3909 * 0b00001..ECC 2 to be performed
3910 * 0b00010..ECC 4 to be performed
3911 * 0b11110..ECC 60 to be performed
3912 * 0b11111..ECC 62 to be performed
3913 */
3914#define BCH_FLASH0LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK)
3915#define BCH_FLASH0LAYOUT0_META_SIZE_MASK (0xFF0000U)
3916#define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT (16U)
3917/*! META_SIZE - META_SIZE
3918 */
3919#define BCH_FLASH0LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK)
3920#define BCH_FLASH0LAYOUT0_NBLOCKS_MASK (0xFF000000U)
3921#define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT (24U)
3922/*! NBLOCKS - NBLOCKS
3923 */
3924#define BCH_FLASH0LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK)
3925/*! @} */
3926
3927/*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */
3928/*! @{ */
3929#define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
3930#define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT (0U)
3931/*! DATAN_SIZE - DATAN_SIZE
3932 */
3933#define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK)
3934#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
3935#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
3936/*! GF13_0_GF14_1 - GF13_0_GF14_1
3937 */
3938#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK)
3939#define BCH_FLASH0LAYOUT1_ECCN_MASK (0xF800U)
3940#define BCH_FLASH0LAYOUT1_ECCN_SHIFT (11U)
3941/*! ECCN - ECCN
3942 * 0b00000..No ECC to be performed
3943 * 0b00001..ECC 2 to be performed
3944 * 0b00010..ECC 4 to be performed
3945 * 0b11110..ECC 60 to be performed
3946 * 0b11111..ECC 62 to be performed
3947 */
3948#define BCH_FLASH0LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK)
3949#define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
3950#define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT (16U)
3951/*! PAGE_SIZE - PAGE_SIZE
3952 */
3953#define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK)
3954/*! @} */
3955
3956/*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */
3957/*! @{ */
3958#define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
3959#define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT (0U)
3960/*! DATA0_SIZE - DATA0_SIZE
3961 */
3962#define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK)
3963#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
3964#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
3965/*! GF13_0_GF14_1 - GF13_0_GF14_1
3966 */
3967#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK)
3968#define BCH_FLASH1LAYOUT0_ECC0_MASK (0xF800U)
3969#define BCH_FLASH1LAYOUT0_ECC0_SHIFT (11U)
3970/*! ECC0 - ECC0
3971 * 0b00000..No ECC to be performed
3972 * 0b00001..ECC 2 to be performed
3973 * 0b00010..ECC 4 to be performed
3974 * 0b11110..ECC 60 to be performed
3975 * 0b11111..ECC 62 to be performed
3976 */
3977#define BCH_FLASH1LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK)
3978#define BCH_FLASH1LAYOUT0_META_SIZE_MASK (0xFF0000U)
3979#define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT (16U)
3980/*! META_SIZE - META_SIZE
3981 */
3982#define BCH_FLASH1LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK)
3983#define BCH_FLASH1LAYOUT0_NBLOCKS_MASK (0xFF000000U)
3984#define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT (24U)
3985/*! NBLOCKS - NBLOCKS
3986 */
3987#define BCH_FLASH1LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK)
3988/*! @} */
3989
3990/*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */
3991/*! @{ */
3992#define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
3993#define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT (0U)
3994/*! DATAN_SIZE - DATAN_SIZE
3995 */
3996#define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK)
3997#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
3998#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
3999/*! GF13_0_GF14_1 - GF13_0_GF14_1
4000 */
4001#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK)
4002#define BCH_FLASH1LAYOUT1_ECCN_MASK (0xF800U)
4003#define BCH_FLASH1LAYOUT1_ECCN_SHIFT (11U)
4004/*! ECCN - ECCN
4005 * 0b00000..No ECC to be performed
4006 * 0b00001..ECC 2 to be performed
4007 * 0b00010..ECC 4 to be performed
4008 * 0b11110..ECC 60 to be performed
4009 * 0b11111..ECC 62 to be performed
4010 */
4011#define BCH_FLASH1LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK)
4012#define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
4013#define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT (16U)
4014/*! PAGE_SIZE - PAGE_SIZE
4015 */
4016#define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK)
4017/*! @} */
4018
4019/*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */
4020/*! @{ */
4021#define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
4022#define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT (0U)
4023/*! DATA0_SIZE - DATA0_SIZE
4024 */
4025#define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK)
4026#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
4027#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
4028/*! GF13_0_GF14_1 - GF13_0_GF14_1
4029 */
4030#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK)
4031#define BCH_FLASH2LAYOUT0_ECC0_MASK (0xF800U)
4032#define BCH_FLASH2LAYOUT0_ECC0_SHIFT (11U)
4033/*! ECC0 - ECC0
4034 * 0b00000..No ECC to be performed
4035 * 0b00001..ECC 2 to be performed
4036 * 0b00010..ECC 4 to be performed
4037 * 0b11110..ECC 60 to be performed
4038 * 0b11111..ECC 62 to be performed
4039 */
4040#define BCH_FLASH2LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK)
4041#define BCH_FLASH2LAYOUT0_META_SIZE_MASK (0xFF0000U)
4042#define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT (16U)
4043/*! META_SIZE - META_SIZE
4044 */
4045#define BCH_FLASH2LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK)
4046#define BCH_FLASH2LAYOUT0_NBLOCKS_MASK (0xFF000000U)
4047#define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT (24U)
4048/*! NBLOCKS - NBLOCKS
4049 */
4050#define BCH_FLASH2LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK)
4051/*! @} */
4052
4053/*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */
4054/*! @{ */
4055#define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
4056#define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT (0U)
4057/*! DATAN_SIZE - DATAN_SIZE
4058 */
4059#define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK)
4060#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
4061#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
4062/*! GF13_0_GF14_1 - GF13_0_GF14_1
4063 */
4064#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK)
4065#define BCH_FLASH2LAYOUT1_ECCN_MASK (0xF800U)
4066#define BCH_FLASH2LAYOUT1_ECCN_SHIFT (11U)
4067/*! ECCN - ECCN
4068 * 0b00000..No ECC to be performed
4069 * 0b00001..ECC 2 to be performed
4070 * 0b00010..ECC 4 to be performed
4071 * 0b11110..ECC 60 to be performed
4072 * 0b11111..ECC 62 to be performed
4073 */
4074#define BCH_FLASH2LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK)
4075#define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
4076#define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT (16U)
4077/*! PAGE_SIZE - PAGE_SIZE
4078 */
4079#define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK)
4080/*! @} */
4081
4082/*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */
4083/*! @{ */
4084#define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
4085#define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT (0U)
4086/*! DATA0_SIZE - DATA0_SIZE
4087 */
4088#define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK)
4089#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
4090#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
4091/*! GF13_0_GF14_1 - GF13_0_GF14_1
4092 */
4093#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK)
4094#define BCH_FLASH3LAYOUT0_ECC0_MASK (0xF800U)
4095#define BCH_FLASH3LAYOUT0_ECC0_SHIFT (11U)
4096/*! ECC0 - ECC0
4097 * 0b00000..No ECC to be performed
4098 * 0b00001..ECC 2 to be performed
4099 * 0b00010..ECC 4 to be performed
4100 * 0b11110..ECC 60 to be performed
4101 * 0b11111..ECC 62 to be performed
4102 */
4103#define BCH_FLASH3LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK)
4104#define BCH_FLASH3LAYOUT0_META_SIZE_MASK (0xFF0000U)
4105#define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT (16U)
4106/*! META_SIZE - META_SIZE
4107 */
4108#define BCH_FLASH3LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK)
4109#define BCH_FLASH3LAYOUT0_NBLOCKS_MASK (0xFF000000U)
4110#define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT (24U)
4111/*! NBLOCKS - NBLOCKS
4112 */
4113#define BCH_FLASH3LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK)
4114/*! @} */
4115
4116/*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */
4117/*! @{ */
4118#define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
4119#define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT (0U)
4120/*! DATAN_SIZE - DATAN_SIZE
4121 */
4122#define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK)
4123#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
4124#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
4125/*! GF13_0_GF14_1 - GF13_0_GF14_1
4126 */
4127#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK)
4128#define BCH_FLASH3LAYOUT1_ECCN_MASK (0xF800U)
4129#define BCH_FLASH3LAYOUT1_ECCN_SHIFT (11U)
4130/*! ECCN - ECCN
4131 * 0b00000..No ECC to be performed
4132 * 0b00001..ECC 2 to be performed
4133 * 0b00010..ECC 4 to be performed
4134 * 0b11110..ECC 60 to be performed
4135 * 0b11111..ECC 62 to be performed
4136 */
4137#define BCH_FLASH3LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK)
4138#define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
4139#define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT (16U)
4140/*! PAGE_SIZE - PAGE_SIZE
4141 */
4142#define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK)
4143/*! @} */
4144
4145/*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */
4146/*! @{ */
4147#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK (0x3FU)
4148#define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT (0U)
4149/*! DEBUG_REG_SELECT - DEBUG_REG_SELECT
4150 */
4151#define BCH_DEBUG0_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK)
4152#define BCH_DEBUG0_RSVD0_MASK (0xC0U)
4153#define BCH_DEBUG0_RSVD0_SHIFT (6U)
4154/*! RSVD0 - This field is reserved.
4155 */
4156#define BCH_DEBUG0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK)
4157#define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK (0x100U)
4158#define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT (8U)
4159/*! BM_KES_TEST_BYPASS - BM_KES_TEST_BYPASS
4160 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
4161 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
4162 */
4163#define BCH_DEBUG0_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK)
4164#define BCH_DEBUG0_KES_DEBUG_STALL_MASK (0x200U)
4165#define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT (9U)
4166/*! KES_DEBUG_STALL - KES_DEBUG_STALL
4167 * 0b0..KES FSM proceeds to next block supplied by bus master.
4168 * 0b1..KES FSM waits after current equations are solved and the search engine is started.
4169 */
4170#define BCH_DEBUG0_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK)
4171#define BCH_DEBUG0_KES_DEBUG_STEP_MASK (0x400U)
4172#define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT (10U)
4173/*! KES_DEBUG_STEP - KES_DEBUG_STEP
4174 */
4175#define BCH_DEBUG0_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK)
4176#define BCH_DEBUG0_KES_STANDALONE_MASK (0x800U)
4177#define BCH_DEBUG0_KES_STANDALONE_SHIFT (11U)
4178/*! KES_STANDALONE - KES_STANDALONE
4179 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
4180 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
4181 */
4182#define BCH_DEBUG0_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK)
4183#define BCH_DEBUG0_KES_DEBUG_KICK_MASK (0x1000U)
4184#define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT (12U)
4185/*! KES_DEBUG_KICK - KES_DEBUG_KICK
4186 */
4187#define BCH_DEBUG0_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK)
4188#define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK (0x2000U)
4189#define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT (13U)
4190/*! KES_DEBUG_MODE4K - KES_DEBUG_MODE4K
4191 * 0b1..Mode is set for 4K NAND pages.
4192 * 0b1..Mode is set for 2K NAND pages.
4193 */
4194#define BCH_DEBUG0_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK)
4195#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
4196#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
4197/*! KES_DEBUG_PAYLOAD_FLAG - KES_DEBUG_PAYLOAD_FLAG
4198 * 0b1..Payload is set for 512 bytes data block.
4199 * 0b1..Payload is set for 65 or 19 bytes auxiliary block.
4200 */
4201#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK)
4202#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
4203#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
4204/*! KES_DEBUG_SHIFT_SYND - KES_DEBUG_SHIFT_SYND
4205 */
4206#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK)
4207#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
4208#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
4209/*! KES_DEBUG_SYNDROME_SYMBOL - KES_DEBUG_SYNDROME_SYMBOL
4210 * 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
4211 * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
4212 */
4213#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK)
4214#define BCH_DEBUG0_RSVD1_MASK (0xFE000000U)
4215#define BCH_DEBUG0_RSVD1_SHIFT (25U)
4216/*! RSVD1 - This field is reserved.
4217 */
4218#define BCH_DEBUG0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK)
4219/*! @} */
4220
4221/*! @name DBGKESREAD - KES Debug Read Register */
4222/*! @{ */
4223#define BCH_DBGKESREAD_VALUES_MASK (0xFFFFFFFFU)
4224#define BCH_DBGKESREAD_VALUES_SHIFT (0U)
4225/*! VALUES - VALUES
4226 */
4227#define BCH_DBGKESREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK)
4228/*! @} */
4229
4230/*! @name DBGCSFEREAD - Chien Search Debug Read Register */
4231/*! @{ */
4232#define BCH_DBGCSFEREAD_VALUES_MASK (0xFFFFFFFFU)
4233#define BCH_DBGCSFEREAD_VALUES_SHIFT (0U)
4234/*! VALUES - VALUES
4235 */
4236#define BCH_DBGCSFEREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK)
4237/*! @} */
4238
4239/*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */
4240/*! @{ */
4241#define BCH_DBGSYNDGENREAD_VALUES_MASK (0xFFFFFFFFU)
4242#define BCH_DBGSYNDGENREAD_VALUES_SHIFT (0U)
4243/*! VALUES - VALUES
4244 */
4245#define BCH_DBGSYNDGENREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK)
4246/*! @} */
4247
4248/*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */
4249/*! @{ */
4250#define BCH_DBGAHBMREAD_VALUES_MASK (0xFFFFFFFFU)
4251#define BCH_DBGAHBMREAD_VALUES_SHIFT (0U)
4252/*! VALUES - VALUES
4253 */
4254#define BCH_DBGAHBMREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK)
4255/*! @} */
4256
4257/*! @name BLOCKNAME - Block Name Register */
4258/*! @{ */
4259#define BCH_BLOCKNAME_NAME_MASK (0xFFFFFFFFU)
4260#define BCH_BLOCKNAME_NAME_SHIFT (0U)
4261/*! NAME - NAME
4262 */
4263#define BCH_BLOCKNAME_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK)
4264/*! @} */
4265
4266/*! @name VERSION - BCH Version Register */
4267/*! @{ */
4268#define BCH_VERSION_STEP_MASK (0xFFFFU)
4269#define BCH_VERSION_STEP_SHIFT (0U)
4270/*! STEP - STEP
4271 */
4272#define BCH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK)
4273#define BCH_VERSION_MINOR_MASK (0xFF0000U)
4274#define BCH_VERSION_MINOR_SHIFT (16U)
4275/*! MINOR - MINOR
4276 */
4277#define BCH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK)
4278#define BCH_VERSION_MAJOR_MASK (0xFF000000U)
4279#define BCH_VERSION_MAJOR_SHIFT (24U)
4280/*! MAJOR - MAJOR
4281 */
4282#define BCH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK)
4283/*! @} */
4284
4285/*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */
4286/*! @{ */
4287#define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK (0x1FFU)
4288#define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT (0U)
4289/*! ERASED_ZERO_COUNT - ERASED_ZERO_COUNT
4290 */
4291#define BCH_DEBUG1_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK)
4292#define BCH_DEBUG1_RSVD_MASK (0x7FFFFE00U)
4293#define BCH_DEBUG1_RSVD_SHIFT (9U)
4294/*! RSVD - This field is reserved.
4295 */
4296#define BCH_DEBUG1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK)
4297#define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK (0x80000000U)
4298#define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT (31U)
4299/*! DEBUG1_PREERASECHK - DEBUG1_PREERASECHK
4300 * 0b0..Turn off pre-erase check
4301 * 0b1..Turn on pre-erase check
4302 */
4303#define BCH_DEBUG1_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK)
4304/*! @} */
4305
4306
4307/*!
4308 * @}
4309 */ /* end of group BCH_Register_Masks */
4310
4311
4312/* BCH - Peripheral instance base addresses */
4313/** Peripheral CONNECTIVITY__BCH base address */
4314#define CONNECTIVITY__BCH_BASE (0x5B814000u)
4315/** Peripheral CONNECTIVITY__BCH base pointer */
4316#define CONNECTIVITY__BCH ((BCH_Type *)CONNECTIVITY__BCH_BASE)
4317/** Array initializer of BCH peripheral base addresses */
4318#define BCH_BASE_ADDRS { CONNECTIVITY__BCH_BASE }
4319/** Array initializer of BCH peripheral base pointers */
4320#define BCH_BASE_PTRS { CONNECTIVITY__BCH }
4321
4322/*!
4323 * @}
4324 */ /* end of group BCH_Peripheral_Access_Layer */
4325
4326
4327/* ----------------------------------------------------------------------------
4328 -- CAN Peripheral Access Layer
4329 ---------------------------------------------------------------------------- */
4330
4331/*!
4332 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
4333 * @{
4334 */
4335
4336/** CAN - Register Layout Typedef */
4337typedef struct {
4338 __IO uint32_t MCR; /**< Module Configuration register, offset: 0x0 */
4339 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
4340 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
4341 uint8_t RESERVED_0[4];
4342 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask register, offset: 0x10 */
4343 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
4344 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
4345 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
4346 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
4347 __IO uint32_t IMASK2; /**< Interrupt Masks 2 register, offset: 0x24 */
4348 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
4349 __IO uint32_t IFLAG2; /**< Interrupt Flags 2 register, offset: 0x2C */
4350 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
4351 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
4352 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
4353 uint8_t RESERVED_1[8];
4354 __I uint32_t CRCR; /**< CRC register, offset: 0x44 */
4355 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
4356 __I uint32_t RXFIR; /**< Rx FIFO Information register, offset: 0x4C */
4357 __IO uint32_t CBT; /**< CAN Bit Timing register, offset: 0x50 */
4358 uint8_t RESERVED_2[4];
4359 __I uint32_t DBG1; /**< Debug 1 register, offset: 0x58 */
4360 __I uint32_t DBG2; /**< Debug 2 register, offset: 0x5C */
4361 uint8_t RESERVED_3[32];
4362 struct { /* offset: 0x80, array step: 0x10 */
4363 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
4364 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
4365 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
4366 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
4367 } MB[64];
4368 uint8_t RESERVED_4[1024];
4369 __IO uint32_t RXIMR[64]; /**< Rx Individual Mask registers, array offset: 0x880, array step: 0x4 */
4370 uint8_t RESERVED_5[640];
4371 __IO uint32_t FDCTRL; /**< CAN FD Control register, offset: 0xC00 */
4372 __IO uint32_t FDCBT; /**< CAN FD Bit Timing register, offset: 0xC04 */
4373 __I uint32_t FDCRC; /**< CAN FD CRC register, offset: 0xC08 */
4374} CAN_Type;
4375
4376/* ----------------------------------------------------------------------------
4377 -- CAN Register Masks
4378 ---------------------------------------------------------------------------- */
4379
4380/*!
4381 * @addtogroup CAN_Register_Masks CAN Register Masks
4382 * @{
4383 */
4384
4385/*! @name MCR - Module Configuration register */
4386/*! @{ */
4387#define CAN_MCR_MAXMB_MASK (0x7FU)
4388#define CAN_MCR_MAXMB_SHIFT (0U)
4389/*! MAXMB - Number Of The Last Message Buffer
4390 */
4391#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
4392#define CAN_MCR_IDAM_MASK (0x300U)
4393#define CAN_MCR_IDAM_SHIFT (8U)
4394/*! IDAM - ID Acceptance Mode
4395 * 0b00..Format A: One full ID (standard and extended) per ID filter table element.
4396 * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element.
4397 * 0b10..Format C: Four partial 8-bit standard IDs per ID filter table element.
4398 * 0b11..Format D: All frames rejected.
4399 */
4400#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
4401#define CAN_MCR_FDEN_MASK (0x800U)
4402#define CAN_MCR_FDEN_SHIFT (11U)
4403/*! FDEN - CAN FD operation enable
4404 * 0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats.
4405 * 0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.
4406 */
4407#define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
4408#define CAN_MCR_AEN_MASK (0x1000U)
4409#define CAN_MCR_AEN_SHIFT (12U)
4410/*! AEN - Abort Enable
4411 * 0b0..Abort disabled.
4412 * 0b1..Abort enabled.
4413 */
4414#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
4415#define CAN_MCR_LPRIOEN_MASK (0x2000U)
4416#define CAN_MCR_LPRIOEN_SHIFT (13U)
4417/*! LPRIOEN - Local Priority Enable
4418 * 0b0..Local Priority disabled.
4419 * 0b1..Local Priority enabled.
4420 */
4421#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
4422#define CAN_MCR_DMA_MASK (0x8000U)
4423#define CAN_MCR_DMA_SHIFT (15U)
4424/*! DMA - DMA Enable
4425 * 0b0..DMA feature for RX FIFO disabled.
4426 * 0b1..DMA feature for RX FIFO enabled.
4427 */
4428#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
4429#define CAN_MCR_IRMQ_MASK (0x10000U)
4430#define CAN_MCR_IRMQ_SHIFT (16U)
4431/*! IRMQ - Individual Rx Masking And Queue Enable
4432 * 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy
4433 * applications, the reading of C/S word locks the MB even if it is EMPTY.
4434 * 0b1..Individual Rx masking and queue feature are enabled.
4435 */
4436#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
4437#define CAN_MCR_SRXDIS_MASK (0x20000U)
4438#define CAN_MCR_SRXDIS_SHIFT (17U)
4439/*! SRXDIS - Self Reception Disable
4440 * 0b0..Self-reception enabled.
4441 * 0b1..Self-reception disabled.
4442 */
4443#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
4444#define CAN_MCR_DOZE_MASK (0x40000U)
4445#define CAN_MCR_DOZE_SHIFT (18U)
4446/*! DOZE - Doze Mode Enable
4447 * 0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested.
4448 * 0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.
4449 */
4450#define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
4451#define CAN_MCR_WAKSRC_MASK (0x80000U)
4452#define CAN_MCR_WAKSRC_SHIFT (19U)
4453/*! WAKSRC - Wake Up Source
4454 * 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.
4455 * 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.
4456 */
4457#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
4458#define CAN_MCR_LPMACK_MASK (0x100000U)
4459#define CAN_MCR_LPMACK_SHIFT (20U)
4460/*! LPMACK - Low-Power Mode Acknowledge
4461 * 0b0..FlexCAN is not in a low-power mode.
4462 * 0b1..FlexCAN is in a low-power mode.
4463 */
4464#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
4465#define CAN_MCR_WRNEN_MASK (0x200000U)
4466#define CAN_MCR_WRNEN_SHIFT (21U)
4467/*! WRNEN - Warning Interrupt Enable
4468 * 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
4469 * 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.
4470 */
4471#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
4472#define CAN_MCR_SLFWAK_MASK (0x400000U)
4473#define CAN_MCR_SLFWAK_SHIFT (22U)
4474/*! SLFWAK - Self Wake Up
4475 * 0b0..FlexCAN Self Wake Up feature is disabled.
4476 * 0b1..FlexCAN Self Wake Up feature is enabled.
4477 */
4478#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
4479#define CAN_MCR_FRZACK_MASK (0x1000000U)
4480#define CAN_MCR_FRZACK_SHIFT (24U)
4481/*! FRZACK - Freeze Mode Acknowledge
4482 * 0b0..FlexCAN not in Freeze mode, prescaler running.
4483 * 0b1..FlexCAN in Freeze mode, prescaler stopped.
4484 */
4485#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
4486#define CAN_MCR_SOFTRST_MASK (0x2000000U)
4487#define CAN_MCR_SOFTRST_SHIFT (25U)
4488/*! SOFTRST - Soft Reset
4489 * 0b0..No reset request.
4490 * 0b1..Resets the registers affected by soft reset.
4491 */
4492#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
4493#define CAN_MCR_WAKMSK_MASK (0x4000000U)
4494#define CAN_MCR_WAKMSK_SHIFT (26U)
4495/*! WAKMSK - Wake Up Interrupt Mask
4496 * 0b0..Wake Up interrupt is disabled.
4497 * 0b1..Wake Up interrupt is enabled.
4498 */
4499#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
4500#define CAN_MCR_NOTRDY_MASK (0x8000000U)
4501#define CAN_MCR_NOTRDY_SHIFT (27U)
4502/*! NOTRDY - FlexCAN Not Ready
4503 * 0b0..FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode.
4504 * 0b1..FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode.
4505 */
4506#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
4507#define CAN_MCR_HALT_MASK (0x10000000U)
4508#define CAN_MCR_HALT_SHIFT (28U)
4509/*! HALT - Halt FlexCAN
4510 * 0b0..No Freeze mode request.
4511 * 0b1..Enters Freeze mode if the FRZ bit is asserted.
4512 */
4513#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
4514#define CAN_MCR_RFEN_MASK (0x20000000U)
4515#define CAN_MCR_RFEN_SHIFT (29U)
4516/*! RFEN - Rx FIFO Enable
4517 * 0b0..Rx FIFO not enabled.
4518 * 0b1..Rx FIFO enabled.
4519 */
4520#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
4521#define CAN_MCR_FRZ_MASK (0x40000000U)
4522#define CAN_MCR_FRZ_SHIFT (30U)
4523/*! FRZ - Freeze Enable
4524 * 0b0..Not enabled to enter Freeze mode.
4525 * 0b1..Enabled to enter Freeze mode.
4526 */
4527#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
4528#define CAN_MCR_MDIS_MASK (0x80000000U)
4529#define CAN_MCR_MDIS_SHIFT (31U)
4530/*! MDIS - Module Disable
4531 * 0b0..Enable the FlexCAN module.
4532 * 0b1..Disable the FlexCAN module.
4533 */
4534#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
4535/*! @} */
4536
4537/*! @name CTRL1 - Control 1 register */
4538/*! @{ */
4539#define CAN_CTRL1_PROPSEG_MASK (0x7U)
4540#define CAN_CTRL1_PROPSEG_SHIFT (0U)
4541/*! PROPSEG - Propagation Segment
4542 */
4543#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
4544#define CAN_CTRL1_LOM_MASK (0x8U)
4545#define CAN_CTRL1_LOM_SHIFT (3U)
4546/*! LOM - Listen-Only Mode
4547 * 0b0..Listen-Only mode is deactivated.
4548 * 0b1..FlexCAN module operates in Listen-Only mode.
4549 */
4550#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
4551#define CAN_CTRL1_LBUF_MASK (0x10U)
4552#define CAN_CTRL1_LBUF_SHIFT (4U)
4553/*! LBUF - Lowest Buffer Transmitted First
4554 * 0b0..Buffer with highest priority is transmitted first.
4555 * 0b1..Lowest number buffer is transmitted first.
4556 */
4557#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
4558#define CAN_CTRL1_TSYN_MASK (0x20U)
4559#define CAN_CTRL1_TSYN_SHIFT (5U)
4560/*! TSYN - Timer Sync
4561 * 0b0..Timer sync feature disabled
4562 * 0b1..Timer sync feature enabled
4563 */
4564#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
4565#define CAN_CTRL1_BOFFREC_MASK (0x40U)
4566#define CAN_CTRL1_BOFFREC_SHIFT (6U)
4567/*! BOFFREC - Bus Off Recovery
4568 * 0b0..Automatic recovering from Bus Off state enabled.
4569 * 0b1..Automatic recovering from Bus Off state disabled.
4570 */
4571#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
4572#define CAN_CTRL1_SMP_MASK (0x80U)
4573#define CAN_CTRL1_SMP_SHIFT (7U)
4574/*! SMP - CAN Bit Sampling
4575 * 0b0..Just one sample is used to determine the bit value.
4576 * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two
4577 * preceding samples; a majority rule is used.
4578 */
4579#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
4580#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
4581#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
4582/*! RWRNMSK - Rx Warning Interrupt Mask
4583 * 0b0..Rx Warning interrupt disabled.
4584 * 0b1..Rx Warning interrupt enabled.
4585 */
4586#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
4587#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
4588#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
4589/*! TWRNMSK - Tx Warning Interrupt Mask
4590 * 0b0..Tx Warning interrupt disabled.
4591 * 0b1..Tx Warning interrupt enabled.
4592 */
4593#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
4594#define CAN_CTRL1_LPB_MASK (0x1000U)
4595#define CAN_CTRL1_LPB_SHIFT (12U)
4596/*! LPB - Loop Back Mode
4597 * 0b0..Loop Back disabled.
4598 * 0b1..Loop Back enabled.
4599 */
4600#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
4601#define CAN_CTRL1_CLKSRC_MASK (0x2000U)
4602#define CAN_CTRL1_CLKSRC_SHIFT (13U)
4603/*! CLKSRC - CAN Engine Clock Source
4604 * 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.
4605 * 0b1..The CAN engine clock source is the peripheral clock.
4606 */
4607#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
4608#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
4609#define CAN_CTRL1_ERRMSK_SHIFT (14U)
4610/*! ERRMSK - Error Interrupt Mask
4611 * 0b0..Error interrupt disabled.
4612 * 0b1..Error interrupt enabled.
4613 */
4614#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
4615#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
4616#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
4617/*! BOFFMSK - Bus Off Interrupt Mask
4618 * 0b0..Bus Off interrupt disabled.
4619 * 0b1..Bus Off interrupt enabled.
4620 */
4621#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
4622#define CAN_CTRL1_PSEG2_MASK (0x70000U)
4623#define CAN_CTRL1_PSEG2_SHIFT (16U)
4624/*! PSEG2 - Phase Segment 2
4625 */
4626#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
4627#define CAN_CTRL1_PSEG1_MASK (0x380000U)
4628#define CAN_CTRL1_PSEG1_SHIFT (19U)
4629/*! PSEG1 - Phase Segment 1
4630 */
4631#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
4632#define CAN_CTRL1_RJW_MASK (0xC00000U)
4633#define CAN_CTRL1_RJW_SHIFT (22U)
4634/*! RJW - Resync Jump Width
4635 */
4636#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
4637#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
4638#define CAN_CTRL1_PRESDIV_SHIFT (24U)
4639/*! PRESDIV - Prescaler Division Factor
4640 */
4641#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
4642/*! @} */
4643
4644/*! @name TIMER - Free Running Timer */
4645/*! @{ */
4646#define CAN_TIMER_TIMER_MASK (0xFFFFU)
4647#define CAN_TIMER_TIMER_SHIFT (0U)
4648/*! TIMER - Timer Value
4649 */
4650#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
4651/*! @} */
4652
4653/*! @name RXMGMASK - Rx Mailboxes Global Mask register */
4654/*! @{ */
4655#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
4656#define CAN_RXMGMASK_MG_SHIFT (0U)
4657/*! MG - Rx Mailboxes Global Mask Bits
4658 */
4659#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
4660/*! @} */
4661
4662/*! @name RX14MASK - Rx 14 Mask register */
4663/*! @{ */
4664#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
4665#define CAN_RX14MASK_RX14M_SHIFT (0U)
4666/*! RX14M - Rx Buffer 14 Mask Bits
4667 */
4668#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
4669/*! @} */
4670
4671/*! @name RX15MASK - Rx 15 Mask register */
4672/*! @{ */
4673#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
4674#define CAN_RX15MASK_RX15M_SHIFT (0U)
4675/*! RX15M - Rx Buffer 15 Mask Bits
4676 */
4677#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
4678/*! @} */
4679
4680/*! @name ECR - Error Counter */
4681/*! @{ */
4682#define CAN_ECR_TXERRCNT_MASK (0xFFU)
4683#define CAN_ECR_TXERRCNT_SHIFT (0U)
4684/*! TXERRCNT - Transmit Error Counter
4685 */
4686#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
4687#define CAN_ECR_RXERRCNT_MASK (0xFF00U)
4688#define CAN_ECR_RXERRCNT_SHIFT (8U)
4689/*! RXERRCNT - Receive Error Counter
4690 */
4691#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
4692#define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U)
4693#define CAN_ECR_TXERRCNT_FAST_SHIFT (16U)
4694/*! TXERRCNT_FAST - Transmit Error Counter for fast bits
4695 */
4696#define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
4697#define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U)
4698#define CAN_ECR_RXERRCNT_FAST_SHIFT (24U)
4699/*! RXERRCNT_FAST - Receive Error Counter for fast bits
4700 */
4701#define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
4702/*! @} */
4703
4704/*! @name ESR1 - Error and Status 1 register */
4705/*! @{ */
4706#define CAN_ESR1_WAKINT_MASK (0x1U)
4707#define CAN_ESR1_WAKINT_SHIFT (0U)
4708/*! WAKINT - Wake-Up Interrupt
4709 * 0b0..No such occurrence.
4710 * 0b1..Indicates a recessive to dominant transition was received on the CAN bus.
4711 */
4712#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
4713#define CAN_ESR1_ERRINT_MASK (0x2U)
4714#define CAN_ESR1_ERRINT_SHIFT (1U)
4715/*! ERRINT - Error Interrupt
4716 * 0b0..No such occurrence.
4717 * 0b1..Indicates setting of any error bit in the Error and Status register.
4718 */
4719#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
4720#define CAN_ESR1_BOFFINT_MASK (0x4U)
4721#define CAN_ESR1_BOFFINT_SHIFT (2U)
4722/*! BOFFINT - Bus Off Interrupt
4723 * 0b0..No such occurrence.
4724 * 0b1..FlexCAN module entered Bus Off state.
4725 */
4726#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
4727#define CAN_ESR1_RX_MASK (0x8U)
4728#define CAN_ESR1_RX_SHIFT (3U)
4729/*! RX - FlexCAN In Reception
4730 * 0b0..FlexCAN is not receiving a message.
4731 * 0b1..FlexCAN is receiving a message.
4732 */
4733#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
4734#define CAN_ESR1_FLTCONF_MASK (0x30U)
4735#define CAN_ESR1_FLTCONF_SHIFT (4U)
4736/*! FLTCONF - Fault Confinement State
4737 * 0b00..Error Active
4738 * 0b01..Error Passive
4739 * 0b1x..Bus Off
4740 */
4741#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
4742#define CAN_ESR1_TX_MASK (0x40U)
4743#define CAN_ESR1_TX_SHIFT (6U)
4744/*! TX - FlexCAN In Transmission
4745 * 0b0..FlexCAN is not transmitting a message.
4746 * 0b1..FlexCAN is transmitting a message.
4747 */
4748#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
4749#define CAN_ESR1_IDLE_MASK (0x80U)
4750#define CAN_ESR1_IDLE_SHIFT (7U)
4751/*! IDLE - IDLE
4752 * 0b0..No such occurrence.
4753 * 0b1..CAN bus is now IDLE.
4754 */
4755#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
4756#define CAN_ESR1_RXWRN_MASK (0x100U)
4757#define CAN_ESR1_RXWRN_SHIFT (8U)
4758/*! RXWRN - Rx Error Warning
4759 * 0b0..No such occurrence.
4760 * 0b1..RXERRCNT is greater than or equal to 96.
4761 */
4762#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
4763#define CAN_ESR1_TXWRN_MASK (0x200U)
4764#define CAN_ESR1_TXWRN_SHIFT (9U)
4765/*! TXWRN - TX Error Warning
4766 * 0b0..No such occurrence.
4767 * 0b1..TXERRCNT is greater than or equal to 96.
4768 */
4769#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
4770#define CAN_ESR1_STFERR_MASK (0x400U)
4771#define CAN_ESR1_STFERR_SHIFT (10U)
4772/*! STFERR - Stuffing Error
4773 * 0b0..No such occurrence.
4774 * 0b1..A stuffing error occurred since last read of this register.
4775 */
4776#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
4777#define CAN_ESR1_FRMERR_MASK (0x800U)
4778#define CAN_ESR1_FRMERR_SHIFT (11U)
4779/*! FRMERR - Form Error
4780 * 0b0..No such occurrence.
4781 * 0b1..A Form Error occurred since last read of this register.
4782 */
4783#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
4784#define CAN_ESR1_CRCERR_MASK (0x1000U)
4785#define CAN_ESR1_CRCERR_SHIFT (12U)
4786/*! CRCERR - Cyclic Redundancy Check Error
4787 * 0b0..No such occurrence.
4788 * 0b1..A CRC error occurred since last read of this register.
4789 */
4790#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
4791#define CAN_ESR1_ACKERR_MASK (0x2000U)
4792#define CAN_ESR1_ACKERR_SHIFT (13U)
4793/*! ACKERR - Acknowledge Error
4794 * 0b0..No such occurrence.
4795 * 0b1..An ACK error occurred since last read of this register.
4796 */
4797#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
4798#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
4799#define CAN_ESR1_BIT0ERR_SHIFT (14U)
4800/*! BIT0ERR - Bit0 Error
4801 * 0b0..No such occurrence.
4802 * 0b1..At least one bit sent as dominant is received as recessive.
4803 */
4804#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
4805#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
4806#define CAN_ESR1_BIT1ERR_SHIFT (15U)
4807/*! BIT1ERR - Bit1 Error
4808 * 0b0..No such occurrence.
4809 * 0b1..At least one bit sent as recessive is received as dominant.
4810 */
4811#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
4812#define CAN_ESR1_RWRNINT_MASK (0x10000U)
4813#define CAN_ESR1_RWRNINT_SHIFT (16U)
4814/*! RWRNINT - Rx Warning Interrupt Flag
4815 * 0b0..No such occurrence.
4816 * 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.
4817 */
4818#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
4819#define CAN_ESR1_TWRNINT_MASK (0x20000U)
4820#define CAN_ESR1_TWRNINT_SHIFT (17U)
4821/*! TWRNINT - Tx Warning Interrupt Flag
4822 * 0b0..No such occurrence.
4823 * 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.
4824 */
4825#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
4826#define CAN_ESR1_SYNCH_MASK (0x40000U)
4827#define CAN_ESR1_SYNCH_SHIFT (18U)
4828/*! SYNCH - CAN Synchronization Status
4829 * 0b0..FlexCAN is not synchronized to the CAN bus.
4830 * 0b1..FlexCAN is synchronized to the CAN bus.
4831 */
4832#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
4833#define CAN_ESR1_BOFFDONEINT_MASK (0x80000U)
4834#define CAN_ESR1_BOFFDONEINT_SHIFT (19U)
4835/*! BOFFDONEINT - Bus Off Done Interrupt
4836 * 0b0..No such occurrence.
4837 * 0b1..FlexCAN module has completed Bus Off process.
4838 */
4839#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
4840#define CAN_ESR1_ERRINT_FAST_MASK (0x100000U)
4841#define CAN_ESR1_ERRINT_FAST_SHIFT (20U)
4842/*! ERRINT_FAST - Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set
4843 * 0b0..No such occurrence.
4844 * 0b1..Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set.
4845 */
4846#define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
4847#define CAN_ESR1_ERROVR_MASK (0x200000U)
4848#define CAN_ESR1_ERROVR_SHIFT (21U)
4849/*! ERROVR - Error Overrun
4850 * 0b0..Overrun has not occurred.
4851 * 0b1..Overrun has occurred.
4852 */
4853#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
4854#define CAN_ESR1_STFERR_FAST_MASK (0x4000000U)
4855#define CAN_ESR1_STFERR_FAST_SHIFT (26U)
4856/*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set
4857 * 0b0..No such occurrence.
4858 * 0b1..A stuffing error occurred since last read of this register.
4859 */
4860#define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
4861#define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U)
4862#define CAN_ESR1_FRMERR_FAST_SHIFT (27U)
4863/*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set
4864 * 0b0..No such occurrence.
4865 * 0b1..A form error occurred since last read of this register.
4866 */
4867#define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
4868#define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U)
4869#define CAN_ESR1_CRCERR_FAST_SHIFT (28U)
4870/*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set
4871 * 0b0..No such occurrence.
4872 * 0b1..A CRC error occurred since last read of this register.
4873 */
4874#define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
4875#define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U)
4876#define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U)
4877/*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set
4878 * 0b0..No such occurrence.
4879 * 0b1..At least one bit sent as dominant is received as recessive.
4880 */
4881#define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
4882#define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U)
4883#define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U)
4884/*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set
4885 * 0b0..No such occurrence.
4886 * 0b1..At least one bit sent as recessive is received as dominant.
4887 */
4888#define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
4889/*! @} */
4890
4891/*! @name IMASK2 - Interrupt Masks 2 register */
4892/*! @{ */
4893#define CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU)
4894#define CAN_IMASK2_BUF63TO32M_SHIFT (0U)
4895/*! BUF63TO32M - Buffer MBi Mask
4896 */
4897#define CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)
4898/*! @} */
4899
4900/*! @name IMASK1 - Interrupt Masks 1 register */
4901/*! @{ */
4902#define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU)
4903#define CAN_IMASK1_BUF31TO0M_SHIFT (0U)
4904/*! BUF31TO0M - Buffer MBi Mask
4905 */
4906#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
4907/*! @} */
4908
4909/*! @name IFLAG2 - Interrupt Flags 2 register */
4910/*! @{ */
4911#define CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU)
4912#define CAN_IFLAG2_BUF63TO32I_SHIFT (0U)
4913/*! BUF63TO32I - Buffer MBi Interrupt
4914 */
4915#define CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)
4916/*! @} */
4917
4918/*! @name IFLAG1 - Interrupt Flags 1 register */
4919/*! @{ */
4920#define CAN_IFLAG1_BUF0I_MASK (0x1U)
4921#define CAN_IFLAG1_BUF0I_SHIFT (0U)
4922/*! BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit
4923 * 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
4924 * 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
4925 */
4926#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
4927#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
4928#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
4929/*! BUF4TO1I - Buffer MBi Interrupt Or Reserved
4930 */
4931#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
4932#define CAN_IFLAG1_BUF5I_MASK (0x20U)
4933#define CAN_IFLAG1_BUF5I_SHIFT (5U)
4934/*! BUF5I - Buffer MB5 Interrupt Or Frames available in Rx FIFO
4935 * 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
4936 * 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when
4937 * MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.
4938 */
4939#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
4940#define CAN_IFLAG1_BUF6I_MASK (0x40U)
4941#define CAN_IFLAG1_BUF6I_SHIFT (6U)
4942/*! BUF6I - Buffer MB6 Interrupt Or Rx FIFO Warning
4943 * 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
4944 * 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1
4945 */
4946#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
4947#define CAN_IFLAG1_BUF7I_MASK (0x80U)
4948#define CAN_IFLAG1_BUF7I_SHIFT (7U)
4949/*! BUF7I - Buffer MB7 Interrupt Or Rx FIFO Overflow
4950 * 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
4951 * 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1
4952 */
4953#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
4954#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
4955#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
4956/*! BUF31TO8I - Buffer MBi Interrupt
4957 */
4958#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
4959/*! @} */
4960
4961/*! @name CTRL2 - Control 2 register */
4962/*! @{ */
4963#define CAN_CTRL2_EDFLTDIS_MASK (0x800U)
4964#define CAN_CTRL2_EDFLTDIS_SHIFT (11U)
4965/*! EDFLTDIS - Edge Filter Disable
4966 * 0b0..Edge filter is enabled
4967 * 0b1..Edge filter is disabled
4968 */
4969#define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)
4970#define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U)
4971#define CAN_CTRL2_ISOCANFDEN_SHIFT (12U)
4972/*! ISOCANFDEN - ISO CAN FD Enable
4973 * 0b0..FlexCAN operates using the non-ISO CAN FD protocol.
4974 * 0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1).
4975 */
4976#define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)
4977#define CAN_CTRL2_PREXCEN_MASK (0x4000U)
4978#define CAN_CTRL2_PREXCEN_SHIFT (14U)
4979/*! PREXCEN - Protocol Exception Enable
4980 * 0b0..Protocol exception is disabled.
4981 * 0b1..Protocol exception is enabled.
4982 */
4983#define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)
4984#define CAN_CTRL2_EACEN_MASK (0x10000U)
4985#define CAN_CTRL2_EACEN_SHIFT (16U)
4986/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
4987 * 0b0..Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
4988 * 0b1..Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within
4989 * the incoming frame. Mask bits do apply.
4990 */
4991#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
4992#define CAN_CTRL2_RRS_MASK (0x20000U)
4993#define CAN_CTRL2_RRS_SHIFT (17U)
4994/*! RRS - Remote Request Storing
4995 * 0b0..Remote response frame is generated.
4996 * 0b1..Remote request frame is stored.
4997 */
4998#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
4999#define CAN_CTRL2_MRP_MASK (0x40000U)
5000#define CAN_CTRL2_MRP_SHIFT (18U)
5001/*! MRP - Mailboxes Reception Priority
5002 * 0b0..Matching starts from Rx FIFO and continues on mailboxes.
5003 * 0b1..Matching starts from mailboxes and continues on Rx FIFO.
5004 */
5005#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
5006#define CAN_CTRL2_TASD_MASK (0xF80000U)
5007#define CAN_CTRL2_TASD_SHIFT (19U)
5008/*! TASD - Tx Arbitration Start Delay
5009 */
5010#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
5011#define CAN_CTRL2_RFFN_MASK (0xF000000U)
5012#define CAN_CTRL2_RFFN_SHIFT (24U)
5013/*! RFFN - Number Of Rx FIFO Filters
5014 */
5015#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
5016#define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U)
5017#define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U)
5018/*! BOFFDONEMSK - Bus Off Done Interrupt Mask
5019 * 0b0..Bus off done interrupt disabled.
5020 * 0b1..Bus off done interrupt enabled.
5021 */
5022#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
5023#define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U)
5024#define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U)
5025/*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames
5026 * 0b0..ERRINT_FAST error interrupt disabled.
5027 * 0b1..ERRINT_FAST error interrupt enabled.
5028 */
5029#define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
5030/*! @} */
5031
5032/*! @name ESR2 - Error and Status 2 register */
5033/*! @{ */
5034#define CAN_ESR2_IMB_MASK (0x2000U)
5035#define CAN_ESR2_IMB_SHIFT (13U)
5036/*! IMB - Inactive Mailbox
5037 * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox.
5038 * 0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one.
5039 */
5040#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
5041#define CAN_ESR2_VPS_MASK (0x4000U)
5042#define CAN_ESR2_VPS_SHIFT (14U)
5043/*! VPS - Valid Priority Status
5044 * 0b0..Contents of IMB and LPTM are invalid.
5045 * 0b1..Contents of IMB and LPTM are valid.
5046 */
5047#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
5048#define CAN_ESR2_LPTM_MASK (0x7F0000U)
5049#define CAN_ESR2_LPTM_SHIFT (16U)
5050/*! LPTM - Lowest Priority Tx Mailbox
5051 */
5052#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
5053/*! @} */
5054
5055/*! @name CRCR - CRC register */
5056/*! @{ */
5057#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
5058#define CAN_CRCR_TXCRC_SHIFT (0U)
5059/*! TXCRC - Transmitted CRC value
5060 */
5061#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
5062#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
5063#define CAN_CRCR_MBCRC_SHIFT (16U)
5064/*! MBCRC - CRC Mailbox
5065 */
5066#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
5067/*! @} */
5068
5069/*! @name RXFGMASK - Rx FIFO Global Mask register */
5070/*! @{ */
5071#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
5072#define CAN_RXFGMASK_FGM_SHIFT (0U)
5073/*! FGM - Rx FIFO Global Mask Bits
5074 */
5075#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
5076/*! @} */
5077
5078/*! @name RXFIR - Rx FIFO Information register */
5079/*! @{ */
5080#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
5081#define CAN_RXFIR_IDHIT_SHIFT (0U)
5082/*! IDHIT - Identifier Acceptance Filter Hit Indicator
5083 */
5084#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
5085/*! @} */
5086
5087/*! @name CBT - CAN Bit Timing register */
5088/*! @{ */
5089#define CAN_CBT_EPSEG2_MASK (0x1FU)
5090#define CAN_CBT_EPSEG2_SHIFT (0U)
5091/*! EPSEG2 - Extended Phase Segment 2
5092 */
5093#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
5094#define CAN_CBT_EPSEG1_MASK (0x3E0U)
5095#define CAN_CBT_EPSEG1_SHIFT (5U)
5096/*! EPSEG1 - Extended Phase Segment 1
5097 */
5098#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
5099#define CAN_CBT_EPROPSEG_MASK (0xFC00U)
5100#define CAN_CBT_EPROPSEG_SHIFT (10U)
5101/*! EPROPSEG - Extended Propagation Segment
5102 */
5103#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
5104#define CAN_CBT_ERJW_MASK (0x1F0000U)
5105#define CAN_CBT_ERJW_SHIFT (16U)
5106/*! ERJW - Extended Resync Jump Width
5107 */
5108#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
5109#define CAN_CBT_EPRESDIV_MASK (0x7FE00000U)
5110#define CAN_CBT_EPRESDIV_SHIFT (21U)
5111/*! EPRESDIV - Extended Prescaler Division Factor
5112 */
5113#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
5114#define CAN_CBT_BTF_MASK (0x80000000U)
5115#define CAN_CBT_BTF_SHIFT (31U)
5116/*! BTF - Bit Timing Format Enable
5117 * 0b0..Extended bit time definitions disabled.
5118 * 0b1..Extended bit time definitions enabled.
5119 */
5120#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
5121/*! @} */
5122
5123/*! @name DBG1 - Debug 1 register */
5124/*! @{ */
5125#define CAN_DBG1_CFSM_MASK (0x7FU)
5126#define CAN_DBG1_CFSM_SHIFT (0U)
5127/*! CFSM - CAN Finite State Machine
5128 */
5129#define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)
5130#define CAN_DBG1_CBN_MASK (0x3FF0000U)
5131#define CAN_DBG1_CBN_SHIFT (16U)
5132/*! CBN - CAN Bit Number
5133 */
5134#define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)
5135/*! @} */
5136
5137/*! @name DBG2 - Debug 2 register */
5138/*! @{ */
5139#define CAN_DBG2_RMP_MASK (0x7FU)
5140#define CAN_DBG2_RMP_SHIFT (0U)
5141/*! RMP - Rx Matching Pointer
5142 */
5143#define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)
5144#define CAN_DBG2_MPP_MASK (0x80U)
5145#define CAN_DBG2_MPP_SHIFT (7U)
5146/*! MPP - Matching Process in Progress
5147 * 0b0..No matching process ongoing
5148 * 0b1..Matching process is in progress.
5149 */
5150#define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)
5151#define CAN_DBG2_TAP_MASK (0x7F00U)
5152#define CAN_DBG2_TAP_SHIFT (8U)
5153/*! TAP - Tx Arbitration Pointer
5154 */
5155#define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)
5156#define CAN_DBG2_APP_MASK (0x8000U)
5157#define CAN_DBG2_APP_SHIFT (15U)
5158/*! APP - Arbitration Process in Progress
5159 * 0b0..No arbitration process ongoing
5160 * 0b1..Arbitration process is in progress.
5161 */
5162#define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)
5163/*! @} */
5164
5165/*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */
5166/*! @{ */
5167#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
5168#define CAN_CS_TIME_STAMP_SHIFT (0U)
5169/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
5170 * Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
5171 * appears on the CAN bus.
5172 */
5173#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
5174#define CAN_CS_DLC_MASK (0xF0000U)
5175#define CAN_CS_DLC_SHIFT (16U)
5176/*! DLC - Length of the data to be stored/transmitted.
5177 */
5178#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
5179#define CAN_CS_RTR_MASK (0x100000U)
5180#define CAN_CS_RTR_SHIFT (20U)
5181/*! RTR - Remote Transmission Request. One/zero for remote/data frame.
5182 */
5183#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
5184#define CAN_CS_IDE_MASK (0x200000U)
5185#define CAN_CS_IDE_SHIFT (21U)
5186/*! IDE - ID Extended. One/zero for extended/standard format frame.
5187 */
5188#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
5189#define CAN_CS_SRR_MASK (0x400000U)
5190#define CAN_CS_SRR_SHIFT (22U)
5191/*! SRR - Substitute Remote Request. Contains a fixed recessive bit.
5192 */
5193#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
5194#define CAN_CS_CODE_MASK (0xF000000U)
5195#define CAN_CS_CODE_SHIFT (24U)
5196/*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
5197 * the FlexCAN module itself, as part of the message buffer matching and arbitration process.
5198 */
5199#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
5200#define CAN_CS_ESI_MASK (0x20000000U)
5201#define CAN_CS_ESI_SHIFT (29U)
5202/*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive.
5203 */
5204#define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
5205#define CAN_CS_BRS_MASK (0x40000000U)
5206#define CAN_CS_BRS_SHIFT (30U)
5207/*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.
5208 */
5209#define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
5210#define CAN_CS_EDL_MASK (0x80000000U)
5211#define CAN_CS_EDL_SHIFT (31U)
5212/*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
5213 * The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
5214 */
5215#define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
5216/*! @} */
5217
5218/* The count of CAN_CS */
5219#define CAN_CS_COUNT (64U)
5220
5221/*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */
5222/*! @{ */
5223#define CAN_ID_EXT_MASK (0x3FFFFU)
5224#define CAN_ID_EXT_SHIFT (0U)
5225/*! EXT - Contains extended (LOW word) identifier of message buffer.
5226 */
5227#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
5228#define CAN_ID_STD_MASK (0x1FFC0000U)
5229#define CAN_ID_STD_SHIFT (18U)
5230/*! STD - Contains standard/extended (HIGH word) identifier of message buffer.
5231 */
5232#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
5233#define CAN_ID_PRIO_MASK (0xE0000000U)
5234#define CAN_ID_PRIO_SHIFT (29U)
5235/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
5236 * makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
5237 * ID to define the transmission priority.
5238 */
5239#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
5240/*! @} */
5241
5242/* The count of CAN_ID */
5243#define CAN_ID_COUNT (64U)
5244
5245/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
5246/*! @{ */
5247#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
5248#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
5249/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.
5250 */
5251#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
5252#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
5253#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
5254/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.
5255 */
5256#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
5257#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
5258#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
5259/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.
5260 */
5261#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
5262#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
5263#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
5264/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.
5265 */
5266#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
5267/*! @} */
5268
5269/* The count of CAN_WORD0 */
5270#define CAN_WORD0_COUNT (64U)
5271
5272/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
5273/*! @{ */
5274#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
5275#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
5276/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.
5277 */
5278#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
5279#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
5280#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
5281/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.
5282 */
5283#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
5284#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
5285#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
5286/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.
5287 */
5288#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
5289#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
5290#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
5291/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.
5292 */
5293#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
5294/*! @} */
5295
5296/* The count of CAN_WORD1 */
5297#define CAN_WORD1_COUNT (64U)
5298
5299/*! @name RXIMR - Rx Individual Mask registers */
5300/*! @{ */
5301#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
5302#define CAN_RXIMR_MI_SHIFT (0U)
5303/*! MI - Individual Mask Bits
5304 */
5305#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
5306/*! @} */
5307
5308/* The count of CAN_RXIMR */
5309#define CAN_RXIMR_COUNT (64U)
5310
5311/*! @name FDCTRL - CAN FD Control register */
5312/*! @{ */
5313#define CAN_FDCTRL_TDCVAL_MASK (0x3FU)
5314#define CAN_FDCTRL_TDCVAL_SHIFT (0U)
5315/*! TDCVAL - Transceiver Delay Compensation Value
5316 */
5317#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
5318#define CAN_FDCTRL_TDCOFF_MASK (0x1F00U)
5319#define CAN_FDCTRL_TDCOFF_SHIFT (8U)
5320/*! TDCOFF - Transceiver Delay Compensation Offset
5321 */
5322#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
5323#define CAN_FDCTRL_TDCFAIL_MASK (0x4000U)
5324#define CAN_FDCTRL_TDCFAIL_SHIFT (14U)
5325/*! TDCFAIL - Transceiver Delay Compensation Fail
5326 * 0b0..Measured loop delay is in range.
5327 * 0b1..Measured loop delay is out of range.
5328 */
5329#define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
5330#define CAN_FDCTRL_TDCEN_MASK (0x8000U)
5331#define CAN_FDCTRL_TDCEN_SHIFT (15U)
5332/*! TDCEN - Transceiver Delay Compensation Enable
5333 * 0b0..TDC is disabled
5334 * 0b1..TDC is enabled
5335 */
5336#define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
5337#define CAN_FDCTRL_MBDSR0_MASK (0x30000U)
5338#define CAN_FDCTRL_MBDSR0_SHIFT (16U)
5339/*! MBDSR0 - Message Buffer Data Size for Region 0
5340 * 0b00..Selects 8 bytes per message buffer.
5341 * 0b01..Selects 16 bytes per message buffer.
5342 * 0b10..Selects 32 bytes per message buffer.
5343 * 0b11..Selects 64 bytes per message buffer.
5344 */
5345#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
5346#define CAN_FDCTRL_MBDSR1_MASK (0x180000U)
5347#define CAN_FDCTRL_MBDSR1_SHIFT (19U)
5348/*! MBDSR1 - Message Buffer Data Size for Region 1
5349 * 0b00..Selects 8 bytes per message buffer.
5350 * 0b01..Selects 16 bytes per message buffer.
5351 * 0b10..Selects 32 bytes per message buffer.
5352 * 0b11..Selects 64 bytes per message buffer.
5353 */
5354#define CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)
5355#define CAN_FDCTRL_FDRATE_MASK (0x80000000U)
5356#define CAN_FDCTRL_FDRATE_SHIFT (31U)
5357/*! FDRATE - Bit Rate Switch Enable
5358 * 0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect.
5359 * 0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive.
5360 */
5361#define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
5362/*! @} */
5363
5364/*! @name FDCBT - CAN FD Bit Timing register */
5365/*! @{ */
5366#define CAN_FDCBT_FPSEG2_MASK (0x7U)
5367#define CAN_FDCBT_FPSEG2_SHIFT (0U)
5368/*! FPSEG2 - Fast Phase Segment 2
5369 */
5370#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
5371#define CAN_FDCBT_FPSEG1_MASK (0xE0U)
5372#define CAN_FDCBT_FPSEG1_SHIFT (5U)
5373/*! FPSEG1 - Fast Phase Segment 1
5374 */
5375#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
5376#define CAN_FDCBT_FPROPSEG_MASK (0x7C00U)
5377#define CAN_FDCBT_FPROPSEG_SHIFT (10U)
5378/*! FPROPSEG - Fast Propagation Segment
5379 */
5380#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
5381#define CAN_FDCBT_FRJW_MASK (0x70000U)
5382#define CAN_FDCBT_FRJW_SHIFT (16U)
5383/*! FRJW - Fast Resync Jump Width
5384 */
5385#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
5386#define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U)
5387#define CAN_FDCBT_FPRESDIV_SHIFT (20U)
5388/*! FPRESDIV - Fast Prescaler Division Factor
5389 */
5390#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
5391/*! @} */
5392
5393/*! @name FDCRC - CAN FD CRC register */
5394/*! @{ */
5395#define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU)
5396#define CAN_FDCRC_FD_TXCRC_SHIFT (0U)
5397/*! FD_TXCRC - Extended Transmitted CRC value
5398 */
5399#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
5400#define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U)
5401#define CAN_FDCRC_FD_MBCRC_SHIFT (24U)
5402/*! FD_MBCRC - CRC Mailbox Number for FD_TXCRC
5403 */
5404#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
5405/*! @} */
5406
5407
5408/*!
5409 * @}
5410 */ /* end of group CAN_Register_Masks */
5411
5412
5413/* CAN - Peripheral instance base addresses */
5414/** Peripheral ADMA__CAN0 base address */
5415#define ADMA__CAN0_BASE (0x5A8D0000u)
5416/** Peripheral ADMA__CAN0 base pointer */
5417#define ADMA__CAN0 ((CAN_Type *)ADMA__CAN0_BASE)
5418/** Peripheral ADMA__CAN1 base address */
5419#define ADMA__CAN1_BASE (0x5A8E0000u)
5420/** Peripheral ADMA__CAN1 base pointer */
5421#define ADMA__CAN1 ((CAN_Type *)ADMA__CAN1_BASE)
5422/** Peripheral ADMA__CAN2 base address */
5423#define ADMA__CAN2_BASE (0x5A8F0000u)
5424/** Peripheral ADMA__CAN2 base pointer */
5425#define ADMA__CAN2 ((CAN_Type *)ADMA__CAN2_BASE)
5426/** Array initializer of CAN peripheral base addresses */
5427#define CAN_BASE_ADDRS { ADMA__CAN0_BASE, ADMA__CAN1_BASE, ADMA__CAN2_BASE }
5428/** Array initializer of CAN peripheral base pointers */
5429#define CAN_BASE_PTRS { ADMA__CAN0, ADMA__CAN1, ADMA__CAN2 }
5430/** Interrupt vectors for the CAN peripheral type */
5431#define CAN_Rx_Warning_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5432#define CAN_Tx_Warning_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5433#define CAN_Wake_Up_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5434#define CAN_Error_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5435#define CAN_Bus_Off_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5436#define CAN_ORed_Message_buffer_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5437
5438/*!
5439 * @}
5440 */ /* end of group CAN_Peripheral_Access_Layer */
5441
5442
5443/* ----------------------------------------------------------------------------
5444 -- CI_PI_CSR Peripheral Access Layer
5445 ---------------------------------------------------------------------------- */
5446
5447/*!
5448 * @addtogroup CI_PI_CSR_Peripheral_Access_Layer CI_PI_CSR Peripheral Access Layer
5449 * @{
5450 */
5451
5452/** CI_PI_CSR - Register Layout Typedef */
5453typedef struct {
5454 struct { /* offset: 0x0 */
5455 __IO uint32_t RW; /**< CI_PI Interface Control Register, offset: 0x0 */
5456 __IO uint32_t SET; /**< CI_PI Interface Control Register, offset: 0x4 */
5457 __IO uint32_t CLR; /**< CI_PI Interface Control Register, offset: 0x8 */
5458 __IO uint32_t TOG; /**< CI_PI Interface Control Register, offset: 0xC */
5459 } IF_CTRL_REG;
5460 struct { /* offset: 0x10 */
5461 __IO uint32_t RW; /**< CSI Interface Control Register, offset: 0x10 */
5462 __IO uint32_t SET; /**< CSI Interface Control Register, offset: 0x14 */
5463 __IO uint32_t CLR; /**< CSI Interface Control Register, offset: 0x18 */
5464 __IO uint32_t TOG; /**< CSI Interface Control Register, offset: 0x1C */
5465 } CSI_CTRL_REG;
5466 struct { /* offset: 0x20 */
5467 __I uint32_t RW; /**< CSI Interface Status Register, offset: 0x20 */
5468 __I uint32_t SET; /**< CSI Interface Status Register, offset: 0x24 */
5469 __I uint32_t CLR; /**< CSI Interface Status Register, offset: 0x28 */
5470 __I uint32_t TOG; /**< CSI Interface Status Register, offset: 0x2C */
5471 } CSI_STATUS;
5472 struct { /* offset: 0x30 */
5473 __IO uint32_t RW; /**< CSI Interface Control Register1, offset: 0x30 */
5474 __IO uint32_t SET; /**< CSI Interface Control Register1, offset: 0x34 */
5475 __IO uint32_t CLR; /**< CSI Interface Control Register1, offset: 0x38 */
5476 __IO uint32_t TOG; /**< CSI Interface Control Register1, offset: 0x3C */
5477 } CSI_CTRL_REG1;
5478} CI_PI_CSR_Type;
5479
5480/* ----------------------------------------------------------------------------
5481 -- CI_PI_CSR Register Masks
5482 ---------------------------------------------------------------------------- */
5483
5484/*!
5485 * @addtogroup CI_PI_CSR_Register_Masks CI_PI_CSR Register Masks
5486 * @{
5487 */
5488
5489/*! @name IF_CTRL_REG - CI_PI Interface Control Register */
5490/*! @{ */
5491#define CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_MASK (0x1U)
5492#define CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_SHIFT (0U)
5493#define CI_PI_CSR_IF_CTRL_REG_PL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_MASK)
5494#define CI_PI_CSR_IF_CTRL_REG_PL_VALID_MASK (0x2U)
5495#define CI_PI_CSR_IF_CTRL_REG_PL_VALID_SHIFT (1U)
5496#define CI_PI_CSR_IF_CTRL_REG_PL_VALID(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_PL_VALID_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_PL_VALID_MASK)
5497#define CI_PI_CSR_IF_CTRL_REG_PL_ADDR_MASK (0x1CU)
5498#define CI_PI_CSR_IF_CTRL_REG_PL_ADDR_SHIFT (2U)
5499#define CI_PI_CSR_IF_CTRL_REG_PL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_PL_ADDR_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_PL_ADDR_MASK)
5500#define CI_PI_CSR_IF_CTRL_REG_IF_FORCE_MASK (0xE0U)
5501#define CI_PI_CSR_IF_CTRL_REG_IF_FORCE_SHIFT (5U)
5502#define CI_PI_CSR_IF_CTRL_REG_IF_FORCE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_IF_FORCE_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_IF_FORCE_MASK)
5503#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_MASK (0x100U)
5504#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_SHIFT (8U)
5505/*! DATA_TYPE_SEL - Pixel link data type select
5506 * 0b0..PL data type comes from the csi_interface
5507 * 0b1..PL data type comes from IF_CTRL DATA_TYPE[4:0]
5508 */
5509#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_MASK)
5510#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_MASK (0x3E00U)
5511#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SHIFT (9U)
5512/*! DATA_TYPE - Data type
5513 * 0b00000..Null data
5514 * 0b00100..RGB format
5515 * 0b01000..YUV444 Format
5516 * 0b10000..YYU420 odd line
5517 * 0b10010..YYU420 even line
5518 * 0b11000..YYY odd line
5519 * 0b11010..UYVY Even line
5520 * 0b11100..Raw
5521 */
5522#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_MASK)
5523/*! @} */
5524
5525/*! @name CSI_CTRL_REG - CSI Interface Control Register */
5526/*! @{ */
5527#define CI_PI_CSR_CSI_CTRL_REG_CSI_EN_MASK (0x1U)
5528#define CI_PI_CSR_CSI_CTRL_REG_CSI_EN_SHIFT (0U)
5529/*! CSI_EN - CSI interface enable
5530 */
5531#define CI_PI_CSR_CSI_CTRL_REG_CSI_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CSI_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CSI_EN_MASK)
5532#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_MASK (0x2U)
5533#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_SHIFT (1U)
5534/*! PIXEL_CLK_POL - Pixel Clock polarity control
5535 * 0b0..Pixel Clock input is not inverted
5536 * 0b1..Pixel Clock input is inverted
5537 */
5538#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_MASK)
5539#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_MASK (0x4U)
5540#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_SHIFT (2U)
5541/*! HSYNC_POL - HSYNC polarity control
5542 * 0b0..HSYNC output to Pixel Link is not inverted
5543 * 0b1..HSYNC output to Pixel Link is inverted
5544 */
5545#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_MASK)
5546#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_MASK (0x8U)
5547#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_SHIFT (3U)
5548/*! VSYNC_POL - VSYNC polarity control
5549 * 0b0..VSYNC output to Pixel Link is not inverted
5550 * 0b1..VSYNC output to Pixel Link is inverted
5551 */
5552#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_MASK)
5553#define CI_PI_CSR_CSI_CTRL_REG_DE_POL_MASK (0x10U)
5554#define CI_PI_CSR_CSI_CTRL_REG_DE_POL_SHIFT (4U)
5555/*! DE_POL - DE polarity control
5556 * 0b0..DE output to Pixel Link is not inverted
5557 * 0b1..DE output to Pixel Link is inverted
5558 */
5559#define CI_PI_CSR_CSI_CTRL_REG_DE_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_DE_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_DE_POL_MASK)
5560#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_MASK (0x20U)
5561#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_SHIFT (5U)
5562/*! PIXEL_DATA_POL - PIXEL_DATA polarity control
5563 * 0b0..PIXEL_DATA output to Pixel Link is not inverted
5564 * 0b1..PIXEL_DATA output to Pixel Link is inverted
5565 */
5566#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_MASK)
5567#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_MASK (0x40U)
5568#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_SHIFT (6U)
5569/*! CCIR_EXT_VSYNC_EN - External VSYNC enable
5570 */
5571#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_MASK)
5572#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_MASK (0x80U)
5573#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_SHIFT (7U)
5574/*! CCIR_EN - CCIR mode enable
5575 * 0b0..CCIR mode disable
5576 * 0b1..CCIR mode enable
5577 */
5578#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_MASK)
5579#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_MASK (0x100U)
5580#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_SHIFT (8U)
5581/*! CCIR_VIDEO_MODE - CCIR_VIDEO_MODE
5582 * 0b0..Progressive mode
5583 * 0b1..Interlace mode
5584 */
5585#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_MASK)
5586#define CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_MASK (0x200U)
5587#define CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_SHIFT (9U)
5588/*! CCIR_NTSC_EN - CCIR_NTSC enable
5589 * 0b0..PAL
5590 * 0b1..NTSC
5591 */
5592#define CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_MASK)
5593#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_MASK (0x400U)
5594#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_SHIFT (10U)
5595/*! CCIR_VSYNC_RESET_EN - CCIR_VSYNC_RESET_EN
5596 */
5597#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_MASK)
5598#define CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_MASK (0x800U)
5599#define CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_SHIFT (11U)
5600/*! CCIR_ECC_ERR_CORRECT_EN - CCIR_ECC_ERR_CORRECT_EN
5601 * 0b0..ECC error correction is disabled.
5602 * 0b1..ECC error correction is enabled.
5603 */
5604#define CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_MASK)
5605#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_MASK (0x1000U)
5606#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_SHIFT (12U)
5607/*! HSYNC_FORCE_EN - HSYNC_FORCE_EN
5608 * 0b0..Do not override HSYNC
5609 * 0b1..Override HSYNC
5610 */
5611#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_MASK)
5612#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_MASK (0x2000U)
5613#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_SHIFT (13U)
5614/*! VSYNC_FORCE_EN - VSYNC_FORCE_EN
5615 * 0b0..Do not override VSYNC
5616 * 0b1..Override VSYNC
5617 */
5618#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_MASK)
5619#define CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_MASK (0x4000U)
5620#define CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_SHIFT (14U)
5621/*! GCLK_MODE_EN - GCLK_MODE_EN
5622 * 0b0..Disable
5623 * 0b1..Enable
5624 */
5625#define CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_MASK)
5626#define CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_MASK (0x8000U)
5627#define CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_SHIFT (15U)
5628/*! VALID_SEL - VALID_SEL
5629 */
5630#define CI_PI_CSR_CSI_CTRL_REG_VALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_MASK)
5631#define CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_MASK (0x10000U)
5632#define CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_SHIFT (16U)
5633/*! RAW_OUT_SEL - RAW_OUT_SEL
5634 * 0b0..Right justified output
5635 * 0b1..Left justified to 14bit output
5636 */
5637#define CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_MASK)
5638#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_MASK (0x20000U)
5639#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_SHIFT (17U)
5640/*! HSYNC_OUT_SEL - HSYNC_OUT_SEL
5641 * 0b0..HSYNC output level
5642 * 0b1..HSYNC output pulse
5643 */
5644#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_MASK)
5645#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_MASK (0x380000U)
5646#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_SHIFT (19U)
5647/*! HSYNC_PULSE - HSYNC_PULSE
5648 */
5649#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_MASK)
5650#define CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_MASK (0x400000U)
5651#define CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_SHIFT (22U)
5652/*! UV_SWAP_EN - UV Swap enable
5653 * 0b0..UV swap disable
5654 * 0b1..UV swap enable
5655 */
5656#define CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_MASK)
5657#define CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_MASK (0x7800000U)
5658#define CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_SHIFT (23U)
5659/*! DATA_TYPE_IN - CSI input data type
5660 * 0b0000..UYVY bt656 8bit
5661 * 0b0001..UYVY bt656 10bit
5662 * 0b0010..RGB 8bit
5663 * 0b0011..BGR 8bit
5664 * 0b0100..RGB 24bit
5665 * 0b0101..YVYU 8bit
5666 * 0b0110..YUV 8bit
5667 * 0b0111..YVYU 16bit
5668 * 0b1000..YUV 24bit
5669 * 0b1001..Bayer 8bit
5670 * 0b1010..Bayer 10bit
5671 * 0b1011..Bayer 12bit
5672 * 0b1100..Bayer 16bit
5673 */
5674#define CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_MASK)
5675#define CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_MASK (0x18000000U)
5676#define CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_SHIFT (27U)
5677/*! MASK_VSYNC_COUNTER - CSI mask VSYNC counter
5678 * 0b00..not mask
5679 * 0b01..mask 1 frame
5680 * 0b10..mask 2 frames
5681 * 0b11..mask 3 frames
5682 */
5683#define CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_MASK)
5684#define CI_PI_CSR_CSI_CTRL_REG_SOFTRST_MASK (0x80000000U)
5685#define CI_PI_CSR_CSI_CTRL_REG_SOFTRST_SHIFT (31U)
5686/*! SOFTRST - SOFTRST
5687 */
5688#define CI_PI_CSR_CSI_CTRL_REG_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_SOFTRST_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_SOFTRST_MASK)
5689/*! @} */
5690
5691/*! @name CSI_STATUS - CSI Interface Status Register */
5692/*! @{ */
5693#define CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_MASK (0x1U)
5694#define CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_SHIFT (0U)
5695#define CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_SHIFT)) & CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_MASK)
5696#define CI_PI_CSR_CSI_STATUS_ECC_ERROR_MASK (0x2U)
5697#define CI_PI_CSR_CSI_STATUS_ECC_ERROR_SHIFT (1U)
5698#define CI_PI_CSR_CSI_STATUS_ECC_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_STATUS_ECC_ERROR_SHIFT)) & CI_PI_CSR_CSI_STATUS_ECC_ERROR_MASK)
5699/*! @} */
5700
5701/*! @name CSI_CTRL_REG1 - CSI Interface Control Register1 */
5702/*! @{ */
5703#define CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_MASK (0xFFFFU)
5704#define CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_SHIFT (0U)
5705/*! PIXEL_WIDTH - CSI interface enable
5706 */
5707#define CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_MASK)
5708#define CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_MASK (0xFFFF0000U)
5709#define CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_SHIFT (16U)
5710/*! VSYNC_PULSE - VSYNC_PULSE
5711 */
5712#define CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_MASK)
5713/*! @} */
5714
5715
5716/*!
5717 * @}
5718 */ /* end of group CI_PI_CSR_Register_Masks */
5719
5720
5721/* CI_PI_CSR - Peripheral instance base addresses */
5722/** Peripheral CI_PI_CSR base address */
5723#define CI_PI_CSR_BASE (0x58261000u)
5724/** Peripheral CI_PI_CSR base pointer */
5725#define CI_PI_CSR ((CI_PI_CSR_Type *)CI_PI_CSR_BASE)
5726/** Array initializer of CI_PI_CSR peripheral base addresses */
5727#define CI_PI_CSR_BASE_ADDRS { CI_PI_CSR_BASE }
5728/** Array initializer of CI_PI_CSR peripheral base pointers */
5729#define CI_PI_CSR_BASE_PTRS { CI_PI_CSR }
5730
5731/*!
5732 * @}
5733 */ /* end of group CI_PI_CSR_Peripheral_Access_Layer */
5734
5735
5736/* ----------------------------------------------------------------------------
5737 -- CM4_LPCG_LPI2C Peripheral Access Layer
5738 ---------------------------------------------------------------------------- */
5739
5740/*!
5741 * @addtogroup CM4_LPCG_LPI2C_Peripheral_Access_Layer CM4_LPCG_LPI2C Peripheral Access Layer
5742 * @{
5743 */
5744
5745/** CM4_LPCG_LPI2C - Register Layout Typedef */
5746typedef struct {
5747 __IO uint32_t LPCG_LPI2C_0; /**< na, offset: 0x0 */
5748} CM4_LPCG_LPI2C_Type;
5749
5750/* ----------------------------------------------------------------------------
5751 -- CM4_LPCG_LPI2C Register Masks
5752 ---------------------------------------------------------------------------- */
5753
5754/*!
5755 * @addtogroup CM4_LPCG_LPI2C_Register_Masks CM4_LPCG_LPI2C Register Masks
5756 * @{
5757 */
5758
5759/*! @name LPCG_LPI2C_0 - na */
5760/*! @{ */
5761#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK (0x1U)
5762#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT (0U)
5763/*! lpi2c1_lpi2c_div_clk_HWEN - Hardware Enable
5764 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
5765 * 0b1..Enable HW automatic gating
5766 */
5767#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK)
5768#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK (0x2U)
5769#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT (1U)
5770/*! lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN - Software Enable
5771 * 0b0..Disable SW clock regardless of HWEN
5772 * 0b1..Enable SW clock gating
5773 */
5774#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK)
5775#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK (0x4U)
5776#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT (2U)
5777/*! LPCG_LPI2C_0_reserved_2_2 - reserved
5778 */
5779#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK)
5780#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK (0x8U)
5781#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT (3U)
5782/*! lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped
5783 */
5784#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK)
5785#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK (0x10U)
5786#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT (4U)
5787/*! LPCG_LPI2C_0_reserved_4_4 - reserved
5788 */
5789#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK)
5790#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK (0x20U)
5791#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT (5U)
5792/*! lpi2c1_ipg_clk_SWEN - Software Enable
5793 * 0b0..Disable SW clock regardless of HWEN
5794 * 0b1..Enable SW clock gating
5795 */
5796#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK)
5797#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK (0x40U)
5798#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT (6U)
5799/*! LPCG_LPI2C_0_reserved_6_6 - reserved
5800 */
5801#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK)
5802#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK (0x80U)
5803#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT (7U)
5804/*! lpi2c1_ipg_clk_STOP - show clock root status, 1 means clock stopped
5805 */
5806#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK)
5807#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK (0xFFFFFF00U)
5808#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT (8U)
5809/*! LPCG_LPI2C_0_reserved_8_31 - reserved
5810 */
5811#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK)
5812/*! @} */
5813
5814
5815/*!
5816 * @}
5817 */ /* end of group CM4_LPCG_LPI2C_Register_Masks */
5818
5819
5820/* CM4_LPCG_LPI2C - Peripheral instance base addresses */
5821/** Peripheral CM4__LPCG_LPI2C base address */
5822#define CM4__LPCG_LPI2C_BASE (0x41630000u)
5823/** Peripheral CM4__LPCG_LPI2C base pointer */
5824#define CM4__LPCG_LPI2C ((CM4_LPCG_LPI2C_Type *)CM4__LPCG_LPI2C_BASE)
5825/** Array initializer of CM4_LPCG_LPI2C peripheral base addresses */
5826#define CM4_LPCG_LPI2C_BASE_ADDRS { CM4__LPCG_LPI2C_BASE }
5827/** Array initializer of CM4_LPCG_LPI2C peripheral base pointers */
5828#define CM4_LPCG_LPI2C_BASE_PTRS { CM4__LPCG_LPI2C }
5829
5830/*!
5831 * @}
5832 */ /* end of group CM4_LPCG_LPI2C_Peripheral_Access_Layer */
5833
5834
5835/* ----------------------------------------------------------------------------
5836 -- CM4_LPCG_LPIT Peripheral Access Layer
5837 ---------------------------------------------------------------------------- */
5838
5839/*!
5840 * @addtogroup CM4_LPCG_LPIT_Peripheral_Access_Layer CM4_LPCG_LPIT Peripheral Access Layer
5841 * @{
5842 */
5843
5844/** CM4_LPCG_LPIT - Register Layout Typedef */
5845typedef struct {
5846 __IO uint32_t LPCG_LPIT_0; /**< na, offset: 0x0 */
5847} CM4_LPCG_LPIT_Type;
5848
5849/* ----------------------------------------------------------------------------
5850 -- CM4_LPCG_LPIT Register Masks
5851 ---------------------------------------------------------------------------- */
5852
5853/*!
5854 * @addtogroup CM4_LPCG_LPIT_Register_Masks CM4_LPCG_LPIT Register Masks
5855 * @{
5856 */
5857
5858/*! @name LPCG_LPIT_0 - na */
5859/*! @{ */
5860#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK (0x1U)
5861#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT (0U)
5862/*! lpit1_ipg_per_clk_HWEN - Hardware Enable
5863 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
5864 * 0b1..Enable HW automatic gating
5865 */
5866#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK)
5867#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK (0x2U)
5868#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT (1U)
5869/*! lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN - Software Enable
5870 * 0b0..Disable SW clock regardless of HWEN
5871 * 0b1..Enable SW clock gating
5872 */
5873#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK)
5874#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK (0x4U)
5875#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT (2U)
5876/*! LPCG_LPIT_0_reserved_2_2 - reserved
5877 */
5878#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK)
5879#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK (0x8U)
5880#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT (3U)
5881/*! lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP - show clock root status, 1 means clock stopped
5882 */
5883#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK)
5884#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK (0x10U)
5885#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT (4U)
5886/*! LPCG_LPIT_0_reserved_4_4 - reserved
5887 */
5888#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK)
5889#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK (0x20U)
5890#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT (5U)
5891/*! lpit1_ipg_clk_SWEN - Software Enable
5892 * 0b0..Disable SW clock regardless of HWEN
5893 * 0b1..Enable SW clock gating
5894 */
5895#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK)
5896#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK (0x40U)
5897#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT (6U)
5898/*! LPCG_LPIT_0_reserved_6_6 - reserved
5899 */
5900#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK)
5901#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK (0x80U)
5902#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT (7U)
5903/*! lpit1_ipg_clk_STOP - show clock root status, 1 means clock stopped
5904 */
5905#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK)
5906#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK (0xFFFFFF00U)
5907#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT (8U)
5908/*! LPCG_LPIT_0_reserved_8_31 - reserved
5909 */
5910#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK)
5911/*! @} */
5912
5913
5914/*!
5915 * @}
5916 */ /* end of group CM4_LPCG_LPIT_Register_Masks */
5917
5918
5919/* CM4_LPCG_LPIT - Peripheral instance base addresses */
5920/** Peripheral CM4__LPCG_LPIT base address */
5921#define CM4__LPCG_LPIT_BASE (0x41610000u)
5922/** Peripheral CM4__LPCG_LPIT base pointer */
5923#define CM4__LPCG_LPIT ((CM4_LPCG_LPIT_Type *)CM4__LPCG_LPIT_BASE)
5924/** Array initializer of CM4_LPCG_LPIT peripheral base addresses */
5925#define CM4_LPCG_LPIT_BASE_ADDRS { CM4__LPCG_LPIT_BASE }
5926/** Array initializer of CM4_LPCG_LPIT peripheral base pointers */
5927#define CM4_LPCG_LPIT_BASE_PTRS { CM4__LPCG_LPIT }
5928
5929/*!
5930 * @}
5931 */ /* end of group CM4_LPCG_LPIT_Peripheral_Access_Layer */
5932
5933
5934/* ----------------------------------------------------------------------------
5935 -- CM4_LPCG_LPUART Peripheral Access Layer
5936 ---------------------------------------------------------------------------- */
5937
5938/*!
5939 * @addtogroup CM4_LPCG_LPUART_Peripheral_Access_Layer CM4_LPCG_LPUART Peripheral Access Layer
5940 * @{
5941 */
5942
5943/** CM4_LPCG_LPUART - Register Layout Typedef */
5944typedef struct {
5945 __IO uint32_t LPCG_LPUART_0; /**< na, offset: 0x0 */
5946} CM4_LPCG_LPUART_Type;
5947
5948/* ----------------------------------------------------------------------------
5949 -- CM4_LPCG_LPUART Register Masks
5950 ---------------------------------------------------------------------------- */
5951
5952/*!
5953 * @addtogroup CM4_LPCG_LPUART_Register_Masks CM4_LPCG_LPUART Register Masks
5954 * @{
5955 */
5956
5957/*! @name LPCG_LPUART_0 - na */
5958/*! @{ */
5959#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK (0x1U)
5960#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT (0U)
5961/*! lpuart1_lpuart_baud_gated_clk_HWEN - Hardware Enable
5962 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
5963 * 0b1..Enable HW automatic gating
5964 */
5965#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK)
5966#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK (0x2U)
5967#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT (1U)
5968/*! lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN - Software Enable
5969 * 0b0..Disable SW clock regardless of HWEN
5970 * 0b1..Enable SW clock gating
5971 */
5972#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK)
5973#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK (0x4U)
5974#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT (2U)
5975/*! LPCG_LPUART_0_reserved_2_2 - reserved
5976 */
5977#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK)
5978#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK (0x8U)
5979#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT (3U)
5980/*! lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP - show clock root status, 1 means clock stopped
5981 */
5982#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK)
5983#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK (0x10U)
5984#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT (4U)
5985/*! LPCG_LPUART_0_reserved_4_4 - reserved
5986 */
5987#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK)
5988#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK (0x20U)
5989#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT (5U)
5990/*! lpuart1_ipg_clk_SWEN - Software Enable
5991 * 0b0..Disable SW clock regardless of HWEN
5992 * 0b1..Enable SW clock gating
5993 */
5994#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK)
5995#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK (0x40U)
5996#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT (6U)
5997/*! LPCG_LPUART_0_reserved_6_6 - reserved
5998 */
5999#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK)
6000#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK (0x80U)
6001#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT (7U)
6002/*! lpuart1_ipg_clk_STOP - show clock root status, 1 means clock stopped
6003 */
6004#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK)
6005#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK (0xFFFFFF00U)
6006#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT (8U)
6007/*! LPCG_LPUART_0_reserved_8_31 - reserved
6008 */
6009#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK)
6010/*! @} */
6011
6012
6013/*!
6014 * @}
6015 */ /* end of group CM4_LPCG_LPUART_Register_Masks */
6016
6017
6018/* CM4_LPCG_LPUART - Peripheral instance base addresses */
6019/** Peripheral CM4__LPCG_LPUART base address */
6020#define CM4__LPCG_LPUART_BASE (0x41620000u)
6021/** Peripheral CM4__LPCG_LPUART base pointer */
6022#define CM4__LPCG_LPUART ((CM4_LPCG_LPUART_Type *)CM4__LPCG_LPUART_BASE)
6023/** Array initializer of CM4_LPCG_LPUART peripheral base addresses */
6024#define CM4_LPCG_LPUART_BASE_ADDRS { CM4__LPCG_LPUART_BASE }
6025/** Array initializer of CM4_LPCG_LPUART peripheral base pointers */
6026#define CM4_LPCG_LPUART_BASE_PTRS { CM4__LPCG_LPUART }
6027
6028/*!
6029 * @}
6030 */ /* end of group CM4_LPCG_LPUART_Peripheral_Access_Layer */
6031
6032
6033/* ----------------------------------------------------------------------------
6034 -- CM4_LPCG_MMCAU_HCLK Peripheral Access Layer
6035 ---------------------------------------------------------------------------- */
6036
6037/*!
6038 * @addtogroup CM4_LPCG_MMCAU_HCLK_Peripheral_Access_Layer CM4_LPCG_MMCAU_HCLK Peripheral Access Layer
6039 * @{
6040 */
6041
6042/** CM4_LPCG_MMCAU_HCLK - Register Layout Typedef */
6043typedef struct {
6044 __IO uint32_t LPCG_MMCAU_HCLK_0; /**< na, offset: 0x0 */
6045} CM4_LPCG_MMCAU_HCLK_Type;
6046
6047/* ----------------------------------------------------------------------------
6048 -- CM4_LPCG_MMCAU_HCLK Register Masks
6049 ---------------------------------------------------------------------------- */
6050
6051/*!
6052 * @addtogroup CM4_LPCG_MMCAU_HCLK_Register_Masks CM4_LPCG_MMCAU_HCLK Register Masks
6053 * @{
6054 */
6055
6056/*! @name LPCG_MMCAU_HCLK_0 - na */
6057/*! @{ */
6058#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK (0x1U)
6059#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT (0U)
6060/*! LPCG_MMCAU_HCLK_0_reserved_0_0 - reserved
6061 */
6062#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK)
6063#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK (0x2U)
6064#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT (1U)
6065/*! cm4_mmcau_hclk_SWEN - Software Enable
6066 * 0b0..Disable SW clock regardless of HWEN
6067 * 0b1..Enable SW clock gating
6068 */
6069#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK)
6070#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK (0x4U)
6071#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT (2U)
6072/*! LPCG_MMCAU_HCLK_0_reserved_2_2 - reserved
6073 */
6074#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK)
6075#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK (0x8U)
6076#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT (3U)
6077/*! cm4_mmcau_hclk_STOP - show clock root status, 1 means clock stopped
6078 */
6079#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK)
6080#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U)
6081#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT (4U)
6082/*! LPCG_MMCAU_HCLK_0_reserved_4_31 - reserved
6083 */
6084#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK)
6085/*! @} */
6086
6087
6088/*!
6089 * @}
6090 */ /* end of group CM4_LPCG_MMCAU_HCLK_Register_Masks */
6091
6092
6093/* CM4_LPCG_MMCAU_HCLK - Peripheral instance base addresses */
6094/** Peripheral CM4__LPCG_MMCAU_HCLK base address */
6095#define CM4__LPCG_MMCAU_HCLK_BASE (0x415F0000u)
6096/** Peripheral CM4__LPCG_MMCAU_HCLK base pointer */
6097#define CM4__LPCG_MMCAU_HCLK ((CM4_LPCG_MMCAU_HCLK_Type *)CM4__LPCG_MMCAU_HCLK_BASE)
6098/** Array initializer of CM4_LPCG_MMCAU_HCLK peripheral base addresses */
6099#define CM4_LPCG_MMCAU_HCLK_BASE_ADDRS { CM4__LPCG_MMCAU_HCLK_BASE }
6100/** Array initializer of CM4_LPCG_MMCAU_HCLK peripheral base pointers */
6101#define CM4_LPCG_MMCAU_HCLK_BASE_PTRS { CM4__LPCG_MMCAU_HCLK }
6102
6103/*!
6104 * @}
6105 */ /* end of group CM4_LPCG_MMCAU_HCLK_Peripheral_Access_Layer */
6106
6107
6108/* ----------------------------------------------------------------------------
6109 -- CM4_LPCG_TCMC_HCLK Peripheral Access Layer
6110 ---------------------------------------------------------------------------- */
6111
6112/*!
6113 * @addtogroup CM4_LPCG_TCMC_HCLK_Peripheral_Access_Layer CM4_LPCG_TCMC_HCLK Peripheral Access Layer
6114 * @{
6115 */
6116
6117/** CM4_LPCG_TCMC_HCLK - Register Layout Typedef */
6118typedef struct {
6119 __IO uint32_t LPCG_TCMC_HCLK_0; /**< na, offset: 0x0 */
6120} CM4_LPCG_TCMC_HCLK_Type;
6121
6122/* ----------------------------------------------------------------------------
6123 -- CM4_LPCG_TCMC_HCLK Register Masks
6124 ---------------------------------------------------------------------------- */
6125
6126/*!
6127 * @addtogroup CM4_LPCG_TCMC_HCLK_Register_Masks CM4_LPCG_TCMC_HCLK Register Masks
6128 * @{
6129 */
6130
6131/*! @name LPCG_TCMC_HCLK_0 - na */
6132/*! @{ */
6133#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK (0x1U)
6134#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT (0U)
6135/*! cm4_tcmc_hclk_HWEN - Hardware Enable
6136 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6137 * 0b1..Enable HW automatic gating
6138 */
6139#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK)
6140#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK (0x2U)
6141#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT (1U)
6142/*! cm4_tcmc_hclk_SWEN - Software Enable
6143 * 0b0..Disable SW clock regardless of HWEN
6144 * 0b1..Enable SW clock gating
6145 */
6146#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK)
6147#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK (0x4U)
6148#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT (2U)
6149/*! LPCG_TCMC_HCLK_0_reserved_2_2 - reserved
6150 */
6151#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK)
6152#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK (0x8U)
6153#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT (3U)
6154/*! cm4_tcmc_hclk_STOP - show clock root status, 1 means clock stopped
6155 */
6156#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK)
6157#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U)
6158#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT (4U)
6159/*! LPCG_TCMC_HCLK_0_reserved_4_31 - reserved
6160 */
6161#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK)
6162/*! @} */
6163
6164
6165/*!
6166 * @}
6167 */ /* end of group CM4_LPCG_TCMC_HCLK_Register_Masks */
6168
6169
6170/* CM4_LPCG_TCMC_HCLK - Peripheral instance base addresses */
6171/** Peripheral CM4__LPCG_TCMC_HCLK base address */
6172#define CM4__LPCG_TCMC_HCLK_BASE (0x415E0000u)
6173/** Peripheral CM4__LPCG_TCMC_HCLK base pointer */
6174#define CM4__LPCG_TCMC_HCLK ((CM4_LPCG_TCMC_HCLK_Type *)CM4__LPCG_TCMC_HCLK_BASE)
6175/** Array initializer of CM4_LPCG_TCMC_HCLK peripheral base addresses */
6176#define CM4_LPCG_TCMC_HCLK_BASE_ADDRS { CM4__LPCG_TCMC_HCLK_BASE }
6177/** Array initializer of CM4_LPCG_TCMC_HCLK peripheral base pointers */
6178#define CM4_LPCG_TCMC_HCLK_BASE_PTRS { CM4__LPCG_TCMC_HCLK }
6179
6180/*!
6181 * @}
6182 */ /* end of group CM4_LPCG_TCMC_HCLK_Peripheral_Access_Layer */
6183
6184
6185/* ----------------------------------------------------------------------------
6186 -- CM4_LPCG_TPM Peripheral Access Layer
6187 ---------------------------------------------------------------------------- */
6188
6189/*!
6190 * @addtogroup CM4_LPCG_TPM_Peripheral_Access_Layer CM4_LPCG_TPM Peripheral Access Layer
6191 * @{
6192 */
6193
6194/** CM4_LPCG_TPM - Register Layout Typedef */
6195typedef struct {
6196 __IO uint32_t LPCG_TPM_0; /**< na, offset: 0x0 */
6197} CM4_LPCG_TPM_Type;
6198
6199/* ----------------------------------------------------------------------------
6200 -- CM4_LPCG_TPM Register Masks
6201 ---------------------------------------------------------------------------- */
6202
6203/*!
6204 * @addtogroup CM4_LPCG_TPM_Register_Masks CM4_LPCG_TPM Register Masks
6205 * @{
6206 */
6207
6208/*! @name LPCG_TPM_0 - na */
6209/*! @{ */
6210#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK (0x1U)
6211#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT (0U)
6212/*! LPCG_TPM_0_reserved_0_0 - reserved
6213 */
6214#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK)
6215#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK (0x2U)
6216#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT (1U)
6217/*! tpm1_lptpm_clk_SWEN - Software Enable
6218 * 0b0..Disable SW clock regardless of HWEN
6219 * 0b1..Enable SW clock gating
6220 */
6221#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK)
6222#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK (0x4U)
6223#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT (2U)
6224/*! LPCG_TPM_0_reserved_2_2 - reserved
6225 */
6226#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK)
6227#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK (0x8U)
6228#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT (3U)
6229/*! tpm1_lptpm_clk_STOP - show clock root status, 1 means clock stopped
6230 */
6231#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK)
6232#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK (0x10U)
6233#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT (4U)
6234/*! LPCG_TPM_0_reserved_4_4 - reserved
6235 */
6236#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK)
6237#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK (0x20U)
6238#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT (5U)
6239/*! tpm1_ipg_clk_SWEN - Software Enable
6240 * 0b0..Disable SW clock regardless of HWEN
6241 * 0b1..Enable SW clock gating
6242 */
6243#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK)
6244#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK (0x40U)
6245#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT (6U)
6246/*! LPCG_TPM_0_reserved_6_6 - reserved
6247 */
6248#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK)
6249#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK (0x80U)
6250#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT (7U)
6251/*! tpm1_ipg_clk_STOP - show clock root status, 1 means clock stopped
6252 */
6253#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK)
6254#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK (0xFFFFFF00U)
6255#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT (8U)
6256/*! LPCG_TPM_0_reserved_8_31 - reserved
6257 */
6258#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK)
6259/*! @} */
6260
6261
6262/*!
6263 * @}
6264 */ /* end of group CM4_LPCG_TPM_Register_Masks */
6265
6266
6267/* CM4_LPCG_TPM - Peripheral instance base addresses */
6268/** Peripheral CM4__LPCG_TPM base address */
6269#define CM4__LPCG_TPM_BASE (0x41600000u)
6270/** Peripheral CM4__LPCG_TPM base pointer */
6271#define CM4__LPCG_TPM ((CM4_LPCG_TPM_Type *)CM4__LPCG_TPM_BASE)
6272/** Array initializer of CM4_LPCG_TPM peripheral base addresses */
6273#define CM4_LPCG_TPM_BASE_ADDRS { CM4__LPCG_TPM_BASE }
6274/** Array initializer of CM4_LPCG_TPM peripheral base pointers */
6275#define CM4_LPCG_TPM_BASE_PTRS { CM4__LPCG_TPM }
6276
6277/*!
6278 * @}
6279 */ /* end of group CM4_LPCG_TPM_Peripheral_Access_Layer */
6280
6281
6282/* ----------------------------------------------------------------------------
6283 -- CONNECTIVITY_LPCG_EDMA Peripheral Access Layer
6284 ---------------------------------------------------------------------------- */
6285
6286/*!
6287 * @addtogroup CONNECTIVITY_LPCG_EDMA_Peripheral_Access_Layer CONNECTIVITY_LPCG_EDMA Peripheral Access Layer
6288 * @{
6289 */
6290
6291/** CONNECTIVITY_LPCG_EDMA - Register Layout Typedef */
6292typedef struct {
6293 __IO uint32_t LPCG_LPCG_EDMA_0; /**< na, offset: 0x0 */
6294} CONNECTIVITY_LPCG_EDMA_Type;
6295
6296/* ----------------------------------------------------------------------------
6297 -- CONNECTIVITY_LPCG_EDMA Register Masks
6298 ---------------------------------------------------------------------------- */
6299
6300/*!
6301 * @addtogroup CONNECTIVITY_LPCG_EDMA_Register_Masks CONNECTIVITY_LPCG_EDMA Register Masks
6302 * @{
6303 */
6304
6305/*! @name LPCG_LPCG_EDMA_0 - na */
6306/*! @{ */
6307#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_MASK (0x1U)
6308#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_SHIFT (0U)
6309/*! edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN - Hardware Enable
6310 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6311 * 0b1..Enable HW automatic gating
6312 */
6313#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_MASK)
6314#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_MASK (0x2U)
6315#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_SHIFT (1U)
6316/*! edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN - Software Enable
6317 * 0b0..Disable SW clock regardless of HWEN
6318 * 0b1..Enable SW clock gating
6319 */
6320#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_MASK)
6321#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_MASK (0x4U)
6322#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_SHIFT (2U)
6323/*! LPCG_lpcg_edma_0_reserved_2_2 - reserved
6324 */
6325#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_MASK)
6326#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_MASK (0x8U)
6327#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_SHIFT (3U)
6328/*! edma_hclk_STOP_AND_edma_mem_dma_clk_STOP - show clock root status, 1 means clock stopped
6329 */
6330#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_MASK)
6331#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_MASK (0x1FFF0U)
6332#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_SHIFT (4U)
6333/*! LPCG_lpcg_edma_0_reserved_4_16 - reserved
6334 */
6335#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_MASK)
6336#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_MASK (0x20000U)
6337#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_SHIFT (17U)
6338/*! edma_ipg_clk_SWEN - Software Enable
6339 * 0b0..Disable SW clock regardless of HWEN
6340 * 0b1..Enable SW clock gating
6341 */
6342#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_MASK)
6343#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_MASK (0x40000U)
6344#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_SHIFT (18U)
6345/*! LPCG_lpcg_edma_0_reserved_18_18 - reserved
6346 */
6347#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_MASK)
6348#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_MASK (0x80000U)
6349#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_SHIFT (19U)
6350/*! edma_ipg_clk_STOP - show clock root status, 1 means clock stopped
6351 */
6352#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_MASK)
6353#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_MASK (0xFFF00000U)
6354#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_SHIFT (20U)
6355/*! LPCG_lpcg_edma_0_reserved_20_31 - reserved
6356 */
6357#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_MASK)
6358/*! @} */
6359
6360
6361/*!
6362 * @}
6363 */ /* end of group CONNECTIVITY_LPCG_EDMA_Register_Masks */
6364
6365
6366/* CONNECTIVITY_LPCG_EDMA - Peripheral instance base addresses */
6367/** Peripheral CONNECTIVITY__LPCG_EDMA base address */
6368#define CONNECTIVITY__LPCG_EDMA_BASE (0x5B2A0000u)
6369/** Peripheral CONNECTIVITY__LPCG_EDMA base pointer */
6370#define CONNECTIVITY__LPCG_EDMA ((CONNECTIVITY_LPCG_EDMA_Type *)CONNECTIVITY__LPCG_EDMA_BASE)
6371/** Array initializer of CONNECTIVITY_LPCG_EDMA peripheral base addresses */
6372#define CONNECTIVITY_LPCG_EDMA_BASE_ADDRS { CONNECTIVITY__LPCG_EDMA_BASE }
6373/** Array initializer of CONNECTIVITY_LPCG_EDMA peripheral base pointers */
6374#define CONNECTIVITY_LPCG_EDMA_BASE_PTRS { CONNECTIVITY__LPCG_EDMA }
6375
6376/*!
6377 * @}
6378 */ /* end of group CONNECTIVITY_LPCG_EDMA_Peripheral_Access_Layer */
6379
6380
6381/* ----------------------------------------------------------------------------
6382 -- CONNECTIVITY_LPCG_ENET0 Peripheral Access Layer
6383 ---------------------------------------------------------------------------- */
6384
6385/*!
6386 * @addtogroup CONNECTIVITY_LPCG_ENET0_Peripheral_Access_Layer CONNECTIVITY_LPCG_ENET0 Peripheral Access Layer
6387 * @{
6388 */
6389
6390/** CONNECTIVITY_LPCG_ENET0 - Register Layout Typedef */
6391typedef struct {
6392 __IO uint32_t LPCG_LPCG_ENET1_0; /**< na, offset: 0x0 */
6393 __IO uint32_t LPCG_LPCG_ENET1_4; /**< na, offset: 0x4 */
6394} CONNECTIVITY_LPCG_ENET0_Type;
6395
6396/* ----------------------------------------------------------------------------
6397 -- CONNECTIVITY_LPCG_ENET0 Register Masks
6398 ---------------------------------------------------------------------------- */
6399
6400/*!
6401 * @addtogroup CONNECTIVITY_LPCG_ENET0_Register_Masks CONNECTIVITY_LPCG_ENET0 Register Masks
6402 * @{
6403 */
6404
6405/*! @name LPCG_LPCG_ENET1_0 - na */
6406/*! @{ */
6407#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_MASK (0x1U)
6408#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_SHIFT (0U)
6409/*! enet1_ipg_clk_time_HWEN - Hardware Enable
6410 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6411 * 0b1..Enable HW automatic gating
6412 */
6413#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_MASK)
6414#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_MASK (0x2U)
6415#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_SHIFT (1U)
6416/*! enet1_ipg_clk_time_SWEN - Software Enable
6417 * 0b0..Disable SW clock regardless of HWEN
6418 * 0b1..Enable SW clock gating
6419 */
6420#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_MASK)
6421#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_MASK (0x4U)
6422#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_SHIFT (2U)
6423/*! LPCG_lpcg_enet1_0_reserved_2_2 - reserved
6424 */
6425#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_MASK)
6426#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_MASK (0x8U)
6427#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_SHIFT (3U)
6428/*! enet1_ipg_clk_time_STOP - show clock root status, 1 means clock stopped
6429 */
6430#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_MASK)
6431#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_MASK (0x10U)
6432#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_SHIFT (4U)
6433/*! LPCG_lpcg_enet1_0_reserved_4_4 - reserved
6434 */
6435#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_MASK)
6436#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_MASK (0x20U)
6437#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_SHIFT (5U)
6438/*! enet1_2x_txclk_SWEN - Software Enable
6439 * 0b0..Disable SW clock regardless of HWEN
6440 * 0b1..Enable SW clock gating
6441 */
6442#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_MASK)
6443#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_MASK (0x40U)
6444#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_SHIFT (6U)
6445/*! LPCG_lpcg_enet1_0_reserved_6_6 - reserved
6446 */
6447#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_MASK)
6448#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_MASK (0x80U)
6449#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_SHIFT (7U)
6450/*! enet1_2x_txclk_STOP - show clock root status, 1 means clock stopped
6451 */
6452#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_MASK)
6453#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_MASK (0x100U)
6454#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_SHIFT (8U)
6455/*! LPCG_lpcg_enet1_0_reserved_8_8 - reserved
6456 */
6457#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_MASK)
6458#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_MASK (0x200U)
6459#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_SHIFT (9U)
6460/*! enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN - Software Enable
6461 * 0b0..Disable SW clock regardless of HWEN
6462 * 0b1..Enable SW clock gating
6463 */
6464#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_MASK)
6465#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_MASK (0x400U)
6466#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_SHIFT (10U)
6467/*! LPCG_lpcg_enet1_0_reserved_10_10 - reserved
6468 */
6469#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_MASK)
6470#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_MASK (0x800U)
6471#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_SHIFT (11U)
6472/*! enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP - show clock root status, 1 means clock stopped
6473 */
6474#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_MASK)
6475#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_MASK (0x1000U)
6476#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_SHIFT (12U)
6477/*! LPCG_lpcg_enet1_0_reserved_12_12 - reserved
6478 */
6479#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_MASK)
6480#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_MASK (0x2000U)
6481#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_SHIFT (13U)
6482/*! enet1_clkdiv_clk_in_SWEN - Software Enable
6483 * 0b0..Disable SW clock regardless of HWEN
6484 * 0b1..Enable SW clock gating
6485 */
6486#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_MASK)
6487#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_MASK (0x4000U)
6488#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_SHIFT (14U)
6489/*! LPCG_lpcg_enet1_0_reserved_14_14 - reserved
6490 */
6491#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_MASK)
6492#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_MASK (0x8000U)
6493#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_SHIFT (15U)
6494/*! enet1_clkdiv_clk_in_STOP - show clock root status, 1 means clock stopped
6495 */
6496#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_MASK)
6497#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_MASK (0x10000U)
6498#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_SHIFT (16U)
6499/*! enet1_ipg_clk_mac0_HWEN - Hardware Enable
6500 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6501 * 0b1..Enable HW automatic gating
6502 */
6503#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_MASK)
6504#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_MASK (0x20000U)
6505#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_SHIFT (17U)
6506/*! enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN - Software Enable
6507 * 0b0..Disable SW clock regardless of HWEN
6508 * 0b1..Enable SW clock gating
6509 */
6510#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_MASK)
6511#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_MASK (0x40000U)
6512#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_SHIFT (18U)
6513/*! LPCG_lpcg_enet1_0_reserved_18_18 - reserved
6514 */
6515#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_MASK)
6516#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_MASK (0x80000U)
6517#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_SHIFT (19U)
6518/*! enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP - show clock root status, 1 means clock stopped
6519 */
6520#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_MASK)
6521#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_MASK (0x100000U)
6522#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_SHIFT (20U)
6523/*! enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN - Hardware Enable
6524 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6525 * 0b1..Enable HW automatic gating
6526 */
6527#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_MASK)
6528#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_MASK (0x200000U)
6529#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_SHIFT (21U)
6530/*! enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN - Software Enable
6531 * 0b0..Disable SW clock regardless of HWEN
6532 * 0b1..Enable SW clock gating
6533 */
6534#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_MASK)
6535#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_MASK (0x400000U)
6536#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_SHIFT (22U)
6537/*! LPCG_lpcg_enet1_0_reserved_22_22 - reserved
6538 */
6539#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_MASK)
6540#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_MASK (0x800000U)
6541#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_SHIFT (23U)
6542/*! enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
6543 */
6544#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_MASK)
6545#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_MASK (0xFF000000U)
6546#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_SHIFT (24U)
6547/*! LPCG_lpcg_enet1_0_reserved_24_31 - reserved
6548 */
6549#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_MASK)
6550/*! @} */
6551
6552/*! @name LPCG_LPCG_ENET1_4 - na */
6553/*! @{ */
6554#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_MASK (0x1U)
6555#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_SHIFT (0U)
6556/*! LPCG_lpcg_enet1_4_reserved_0_0 - reserved
6557 */
6558#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_MASK)
6559#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_MASK (0x2U)
6560#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_SHIFT (1U)
6561/*! enet1_mac0_rxclk_SWEN - Software Enable
6562 * 0b0..Disable SW clock regardless of HWEN
6563 * 0b1..Enable SW clock gating
6564 */
6565#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_MASK)
6566#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_MASK (0x4U)
6567#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_SHIFT (2U)
6568/*! LPCG_lpcg_enet1_4_reserved_2_2 - reserved
6569 */
6570#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_MASK)
6571#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_MASK (0x8U)
6572#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_SHIFT (3U)
6573/*! enet1_mac0_rxclk_STOP - show clock root status, 1 means clock stopped
6574 */
6575#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_MASK)
6576#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_MASK (0xFFFFFFF0U)
6577#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_SHIFT (4U)
6578/*! LPCG_lpcg_enet1_4_reserved_4_31 - reserved
6579 */
6580#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_MASK)
6581/*! @} */
6582
6583
6584/*!
6585 * @}
6586 */ /* end of group CONNECTIVITY_LPCG_ENET0_Register_Masks */
6587
6588
6589/* CONNECTIVITY_LPCG_ENET0 - Peripheral instance base addresses */
6590/** Peripheral CONNECTIVITY__LPCG_ENET0 base address */
6591#define CONNECTIVITY__LPCG_ENET0_BASE (0x5B230000u)
6592/** Peripheral CONNECTIVITY__LPCG_ENET0 base pointer */
6593#define CONNECTIVITY__LPCG_ENET0 ((CONNECTIVITY_LPCG_ENET0_Type *)CONNECTIVITY__LPCG_ENET0_BASE)
6594/** Array initializer of CONNECTIVITY_LPCG_ENET0 peripheral base addresses */
6595#define CONNECTIVITY_LPCG_ENET0_BASE_ADDRS { CONNECTIVITY__LPCG_ENET0_BASE }
6596/** Array initializer of CONNECTIVITY_LPCG_ENET0 peripheral base pointers */
6597#define CONNECTIVITY_LPCG_ENET0_BASE_PTRS { CONNECTIVITY__LPCG_ENET0 }
6598
6599/*!
6600 * @}
6601 */ /* end of group CONNECTIVITY_LPCG_ENET0_Peripheral_Access_Layer */
6602
6603
6604/* ----------------------------------------------------------------------------
6605 -- CONNECTIVITY_LPCG_ENET1 Peripheral Access Layer
6606 ---------------------------------------------------------------------------- */
6607
6608/*!
6609 * @addtogroup CONNECTIVITY_LPCG_ENET1_Peripheral_Access_Layer CONNECTIVITY_LPCG_ENET1 Peripheral Access Layer
6610 * @{
6611 */
6612
6613/** CONNECTIVITY_LPCG_ENET1 - Register Layout Typedef */
6614typedef struct {
6615 __IO uint32_t LPCG_LPCG_ENET2_0; /**< na, offset: 0x0 */
6616 __IO uint32_t LPCG_LPCG_ENET2_4; /**< na, offset: 0x4 */
6617} CONNECTIVITY_LPCG_ENET1_Type;
6618
6619/* ----------------------------------------------------------------------------
6620 -- CONNECTIVITY_LPCG_ENET1 Register Masks
6621 ---------------------------------------------------------------------------- */
6622
6623/*!
6624 * @addtogroup CONNECTIVITY_LPCG_ENET1_Register_Masks CONNECTIVITY_LPCG_ENET1 Register Masks
6625 * @{
6626 */
6627
6628/*! @name LPCG_LPCG_ENET2_0 - na */
6629/*! @{ */
6630#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_MASK (0x1U)
6631#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_SHIFT (0U)
6632/*! enet2_ipg_clk_time_HWEN - Hardware Enable
6633 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6634 * 0b1..Enable HW automatic gating
6635 */
6636#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_MASK)
6637#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_MASK (0x2U)
6638#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_SHIFT (1U)
6639/*! enet2_ipg_clk_time_SWEN - Software Enable
6640 * 0b0..Disable SW clock regardless of HWEN
6641 * 0b1..Enable SW clock gating
6642 */
6643#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_MASK)
6644#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_MASK (0x4U)
6645#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_SHIFT (2U)
6646/*! LPCG_lpcg_enet2_0_reserved_2_2 - reserved
6647 */
6648#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_MASK)
6649#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_MASK (0x8U)
6650#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_SHIFT (3U)
6651/*! enet2_ipg_clk_time_STOP - show clock root status, 1 means clock stopped
6652 */
6653#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_MASK)
6654#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_MASK (0x10U)
6655#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_SHIFT (4U)
6656/*! LPCG_lpcg_enet2_0_reserved_4_4 - reserved
6657 */
6658#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_MASK)
6659#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_MASK (0x20U)
6660#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_SHIFT (5U)
6661/*! enet2_2x_txclk_SWEN - Software Enable
6662 * 0b0..Disable SW clock regardless of HWEN
6663 * 0b1..Enable SW clock gating
6664 */
6665#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_MASK)
6666#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_MASK (0x40U)
6667#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_SHIFT (6U)
6668/*! LPCG_lpcg_enet2_0_reserved_6_6 - reserved
6669 */
6670#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_MASK)
6671#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_MASK (0x80U)
6672#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_SHIFT (7U)
6673/*! enet2_2x_txclk_STOP - show clock root status, 1 means clock stopped
6674 */
6675#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_MASK)
6676#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_MASK (0x100U)
6677#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_SHIFT (8U)
6678/*! LPCG_lpcg_enet2_0_reserved_8_8 - reserved
6679 */
6680#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_MASK)
6681#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_MASK (0x200U)
6682#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_SHIFT (9U)
6683/*! enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN - Software Enable
6684 * 0b0..Disable SW clock regardless of HWEN
6685 * 0b1..Enable SW clock gating
6686 */
6687#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_MASK)
6688#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_MASK (0x400U)
6689#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_SHIFT (10U)
6690/*! LPCG_lpcg_enet2_0_reserved_10_10 - reserved
6691 */
6692#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_MASK)
6693#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_MASK (0x800U)
6694#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_SHIFT (11U)
6695/*! enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP - show clock root status, 1 means clock stopped
6696 */
6697#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_MASK)
6698#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_MASK (0x1000U)
6699#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_SHIFT (12U)
6700/*! LPCG_lpcg_enet2_0_reserved_12_12 - reserved
6701 */
6702#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_MASK)
6703#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_MASK (0x2000U)
6704#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_SHIFT (13U)
6705/*! enet2_clkdiv_clk_in_SWEN - Software Enable
6706 * 0b0..Disable SW clock regardless of HWEN
6707 * 0b1..Enable SW clock gating
6708 */
6709#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_MASK)
6710#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_MASK (0x4000U)
6711#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_SHIFT (14U)
6712/*! LPCG_lpcg_enet2_0_reserved_14_14 - reserved
6713 */
6714#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_MASK)
6715#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_MASK (0x8000U)
6716#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_SHIFT (15U)
6717/*! enet2_clkdiv_clk_in_STOP - show clock root status, 1 means clock stopped
6718 */
6719#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_MASK)
6720#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_MASK (0x10000U)
6721#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_SHIFT (16U)
6722/*! enet2_ipg_clk_mac0_HWEN - Hardware Enable
6723 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6724 * 0b1..Enable HW automatic gating
6725 */
6726#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_MASK)
6727#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_MASK (0x20000U)
6728#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_SHIFT (17U)
6729/*! enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN - Software Enable
6730 * 0b0..Disable SW clock regardless of HWEN
6731 * 0b1..Enable SW clock gating
6732 */
6733#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_MASK)
6734#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_MASK (0x40000U)
6735#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_SHIFT (18U)
6736/*! LPCG_lpcg_enet2_0_reserved_18_18 - reserved
6737 */
6738#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_MASK)
6739#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_MASK (0x80000U)
6740#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_SHIFT (19U)
6741/*! enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP - show clock root status, 1 means clock stopped
6742 */
6743#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_MASK)
6744#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_MASK (0x100000U)
6745#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_SHIFT (20U)
6746/*! enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN - Hardware Enable
6747 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6748 * 0b1..Enable HW automatic gating
6749 */
6750#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_MASK)
6751#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_MASK (0x200000U)
6752#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_SHIFT (21U)
6753/*! enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN - Software Enable
6754 * 0b0..Disable SW clock regardless of HWEN
6755 * 0b1..Enable SW clock gating
6756 */
6757#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_MASK)
6758#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_MASK (0x400000U)
6759#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_SHIFT (22U)
6760/*! LPCG_lpcg_enet2_0_reserved_22_22 - reserved
6761 */
6762#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_MASK)
6763#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_MASK (0x800000U)
6764#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_SHIFT (23U)
6765/*! enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
6766 */
6767#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_MASK)
6768#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_MASK (0xFF000000U)
6769#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_SHIFT (24U)
6770/*! LPCG_lpcg_enet2_0_reserved_24_31 - reserved
6771 */
6772#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_MASK)
6773/*! @} */
6774
6775/*! @name LPCG_LPCG_ENET2_4 - na */
6776/*! @{ */
6777#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_MASK (0x1U)
6778#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_SHIFT (0U)
6779/*! LPCG_lpcg_enet2_4_reserved_0_0 - reserved
6780 */
6781#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_MASK)
6782#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_MASK (0x2U)
6783#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_SHIFT (1U)
6784/*! enet2_mac0_rxclk_SWEN - Software Enable
6785 * 0b0..Disable SW clock regardless of HWEN
6786 * 0b1..Enable SW clock gating
6787 */
6788#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_MASK)
6789#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_MASK (0x4U)
6790#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_SHIFT (2U)
6791/*! LPCG_lpcg_enet2_4_reserved_2_2 - reserved
6792 */
6793#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_MASK)
6794#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_MASK (0x8U)
6795#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_SHIFT (3U)
6796/*! enet2_mac0_rxclk_STOP - show clock root status, 1 means clock stopped
6797 */
6798#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_MASK)
6799#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_MASK (0xFFFFFFF0U)
6800#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_SHIFT (4U)
6801/*! LPCG_lpcg_enet2_4_reserved_4_31 - reserved
6802 */
6803#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_MASK)
6804/*! @} */
6805
6806
6807/*!
6808 * @}
6809 */ /* end of group CONNECTIVITY_LPCG_ENET1_Register_Masks */
6810
6811
6812/* CONNECTIVITY_LPCG_ENET1 - Peripheral instance base addresses */
6813/** Peripheral CONNECTIVITY__LPCG_ENET1 base address */
6814#define CONNECTIVITY__LPCG_ENET1_BASE (0x5B240000u)
6815/** Peripheral CONNECTIVITY__LPCG_ENET1 base pointer */
6816#define CONNECTIVITY__LPCG_ENET1 ((CONNECTIVITY_LPCG_ENET1_Type *)CONNECTIVITY__LPCG_ENET1_BASE)
6817/** Array initializer of CONNECTIVITY_LPCG_ENET1 peripheral base addresses */
6818#define CONNECTIVITY_LPCG_ENET1_BASE_ADDRS { CONNECTIVITY__LPCG_ENET1_BASE }
6819/** Array initializer of CONNECTIVITY_LPCG_ENET1 peripheral base pointers */
6820#define CONNECTIVITY_LPCG_ENET1_BASE_PTRS { CONNECTIVITY__LPCG_ENET1 }
6821
6822/*!
6823 * @}
6824 */ /* end of group CONNECTIVITY_LPCG_ENET1_Peripheral_Access_Layer */
6825
6826
6827/* ----------------------------------------------------------------------------
6828 -- CONNECTIVITY_LPCG_MLB Peripheral Access Layer
6829 ---------------------------------------------------------------------------- */
6830
6831/*!
6832 * @addtogroup CONNECTIVITY_LPCG_MLB_Peripheral_Access_Layer CONNECTIVITY_LPCG_MLB Peripheral Access Layer
6833 * @{
6834 */
6835
6836/** CONNECTIVITY_LPCG_MLB - Register Layout Typedef */
6837typedef struct {
6838 __IO uint32_t LPCG_LPCG_MLB_0; /**< na, offset: 0x0 */
6839} CONNECTIVITY_LPCG_MLB_Type;
6840
6841/* ----------------------------------------------------------------------------
6842 -- CONNECTIVITY_LPCG_MLB Register Masks
6843 ---------------------------------------------------------------------------- */
6844
6845/*!
6846 * @addtogroup CONNECTIVITY_LPCG_MLB_Register_Masks CONNECTIVITY_LPCG_MLB Register Masks
6847 * @{
6848 */
6849
6850/*! @name LPCG_LPCG_MLB_0 - na */
6851/*! @{ */
6852#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_MASK (0x1U)
6853#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_SHIFT (0U)
6854/*! LPCG_lpcg_mlb_0_reserved_0_0 - reserved
6855 */
6856#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_MASK)
6857#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_MASK (0x2U)
6858#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_SHIFT (1U)
6859/*! mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN - Software Enable
6860 * 0b0..Disable SW clock regardless of HWEN
6861 * 0b1..Enable SW clock gating
6862 */
6863#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_MASK)
6864#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_MASK (0x4U)
6865#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_SHIFT (2U)
6866/*! LPCG_lpcg_mlb_0_reserved_2_2 - reserved
6867 */
6868#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_MASK)
6869#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_MASK (0x8U)
6870#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_SHIFT (3U)
6871/*! mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP - show clock root status, 1 means clock stopped
6872 */
6873#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_MASK)
6874#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_MASK (0xFFF0U)
6875#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_SHIFT (4U)
6876/*! LPCG_lpcg_mlb_0_reserved_4_15 - reserved
6877 */
6878#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_MASK)
6879#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_MASK (0x10000U)
6880#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_SHIFT (16U)
6881/*! mlb_ipg_clk_s_HWEN - Hardware Enable
6882 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6883 * 0b1..Enable HW automatic gating
6884 */
6885#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_MASK)
6886#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_MASK (0x20000U)
6887#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_SHIFT (17U)
6888/*! mlb_ipg_clk_s_SWEN - Software Enable
6889 * 0b0..Disable SW clock regardless of HWEN
6890 * 0b1..Enable SW clock gating
6891 */
6892#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_MASK)
6893#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_MASK (0x40000U)
6894#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_SHIFT (18U)
6895/*! LPCG_lpcg_mlb_0_reserved_18_18 - reserved
6896 */
6897#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_MASK)
6898#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_MASK (0x80000U)
6899#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_SHIFT (19U)
6900/*! mlb_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
6901 */
6902#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_MASK)
6903#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_MASK (0x100000U)
6904#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_SHIFT (20U)
6905/*! LPCG_lpcg_mlb_0_reserved_20_20 - reserved
6906 */
6907#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_MASK)
6908#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_MASK (0x200000U)
6909#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_SHIFT (21U)
6910/*! mlb_hclk_SWEN - Software Enable
6911 * 0b0..Disable SW clock regardless of HWEN
6912 * 0b1..Enable SW clock gating
6913 */
6914#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_MASK)
6915#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_MASK (0x400000U)
6916#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_SHIFT (22U)
6917/*! LPCG_lpcg_mlb_0_reserved_22_22 - reserved
6918 */
6919#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_MASK)
6920#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_MASK (0x800000U)
6921#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_SHIFT (23U)
6922/*! mlb_hclk_STOP - show clock root status, 1 means clock stopped
6923 */
6924#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_MASK)
6925#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_MASK (0xFF000000U)
6926#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_SHIFT (24U)
6927/*! LPCG_lpcg_mlb_0_reserved_24_31 - reserved
6928 */
6929#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_MASK)
6930/*! @} */
6931
6932
6933/*!
6934 * @}
6935 */ /* end of group CONNECTIVITY_LPCG_MLB_Register_Masks */
6936
6937
6938/* CONNECTIVITY_LPCG_MLB - Peripheral instance base addresses */
6939/** Peripheral CONNECTIVITY__LPCG_MLB base address */
6940#define CONNECTIVITY__LPCG_MLB_BASE (0x5B260000u)
6941/** Peripheral CONNECTIVITY__LPCG_MLB base pointer */
6942#define CONNECTIVITY__LPCG_MLB ((CONNECTIVITY_LPCG_MLB_Type *)CONNECTIVITY__LPCG_MLB_BASE)
6943/** Array initializer of CONNECTIVITY_LPCG_MLB peripheral base addresses */
6944#define CONNECTIVITY_LPCG_MLB_BASE_ADDRS { CONNECTIVITY__LPCG_MLB_BASE }
6945/** Array initializer of CONNECTIVITY_LPCG_MLB peripheral base pointers */
6946#define CONNECTIVITY_LPCG_MLB_BASE_PTRS { CONNECTIVITY__LPCG_MLB }
6947
6948/*!
6949 * @}
6950 */ /* end of group CONNECTIVITY_LPCG_MLB_Peripheral_Access_Layer */
6951
6952
6953/* ----------------------------------------------------------------------------
6954 -- CONNECTIVITY_LPCG_RAWNAND Peripheral Access Layer
6955 ---------------------------------------------------------------------------- */
6956
6957/*!
6958 * @addtogroup CONNECTIVITY_LPCG_RAWNAND_Peripheral_Access_Layer CONNECTIVITY_LPCG_RAWNAND Peripheral Access Layer
6959 * @{
6960 */
6961
6962/** CONNECTIVITY_LPCG_RAWNAND - Register Layout Typedef */
6963typedef struct {
6964 __IO uint32_t LPCG_LPCG_RAWNAND_0; /**< na, offset: 0x0 */
6965 __IO uint32_t LPCG_LPCG_RAWNAND_4; /**< na, offset: 0x4 */
6966} CONNECTIVITY_LPCG_RAWNAND_Type;
6967
6968/* ----------------------------------------------------------------------------
6969 -- CONNECTIVITY_LPCG_RAWNAND Register Masks
6970 ---------------------------------------------------------------------------- */
6971
6972/*!
6973 * @addtogroup CONNECTIVITY_LPCG_RAWNAND_Register_Masks CONNECTIVITY_LPCG_RAWNAND Register Masks
6974 * @{
6975 */
6976
6977/*! @name LPCG_LPCG_RAWNAND_0 - na */
6978/*! @{ */
6979#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_MASK (0x1U)
6980#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_SHIFT (0U)
6981/*! LPCG_lpcg_rawnand_0_reserved_0_0 - reserved
6982 */
6983#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_MASK)
6984#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_MASK (0x2U)
6985#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_SHIFT (1U)
6986/*! rawnand_u_gpmi_bch_input_bch_clk_SWEN - Software Enable
6987 * 0b0..Disable SW clock regardless of HWEN
6988 * 0b1..Enable SW clock gating
6989 */
6990#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_MASK)
6991#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_MASK (0x4U)
6992#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_SHIFT (2U)
6993/*! LPCG_lpcg_rawnand_0_reserved_2_2 - reserved
6994 */
6995#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_MASK)
6996#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_MASK (0x8U)
6997#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_SHIFT (3U)
6998/*! rawnand_u_gpmi_bch_input_bch_clk_STOP - show clock root status, 1 means clock stopped
6999 */
7000#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_MASK)
7001#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_MASK (0x10U)
7002#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_SHIFT (4U)
7003/*! LPCG_lpcg_rawnand_0_reserved_4_4 - reserved
7004 */
7005#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_MASK)
7006#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_MASK (0x20U)
7007#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_SHIFT (5U)
7008/*! rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN - Software Enable
7009 * 0b0..Disable SW clock regardless of HWEN
7010 * 0b1..Enable SW clock gating
7011 */
7012#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_MASK)
7013#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_MASK (0x40U)
7014#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_SHIFT (6U)
7015/*! LPCG_lpcg_rawnand_0_reserved_6_6 - reserved
7016 */
7017#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_MASK)
7018#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_MASK (0x80U)
7019#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_SHIFT (7U)
7020/*! rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP - show clock root status, 1 means clock stopped
7021 */
7022#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_MASK)
7023#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_MASK (0x1FF00U)
7024#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_SHIFT (8U)
7025/*! LPCG_lpcg_rawnand_0_reserved_8_16 - reserved
7026 */
7027#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_MASK)
7028#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_MASK (0x20000U)
7029#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_SHIFT (17U)
7030/*! rawnand_u_gpmi_input_apb_clk_SWEN - Software Enable
7031 * 0b0..Disable SW clock regardless of HWEN
7032 * 0b1..Enable SW clock gating
7033 */
7034#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_MASK)
7035#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_MASK (0x40000U)
7036#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_SHIFT (18U)
7037/*! LPCG_lpcg_rawnand_0_reserved_18_18 - reserved
7038 */
7039#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_MASK)
7040#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_MASK (0x80000U)
7041#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_SHIFT (19U)
7042/*! rawnand_u_gpmi_input_apb_clk_STOP - show clock root status, 1 means clock stopped
7043 */
7044#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_MASK)
7045#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_MASK (0x100000U)
7046#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_SHIFT (20U)
7047/*! LPCG_lpcg_rawnand_0_reserved_20_20 - reserved
7048 */
7049#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_MASK)
7050#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_MASK (0x200000U)
7051#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_SHIFT (21U)
7052/*! rawnand_u_bch_input_apb_clk_SWEN - Software Enable
7053 * 0b0..Disable SW clock regardless of HWEN
7054 * 0b1..Enable SW clock gating
7055 */
7056#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_MASK)
7057#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_MASK (0x400000U)
7058#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_SHIFT (22U)
7059/*! LPCG_lpcg_rawnand_0_reserved_22_22 - reserved
7060 */
7061#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_MASK)
7062#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_MASK (0x800000U)
7063#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_SHIFT (23U)
7064/*! rawnand_u_bch_input_apb_clk_STOP - show clock root status, 1 means clock stopped
7065 */
7066#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_MASK)
7067#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_MASK (0xFF000000U)
7068#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_SHIFT (24U)
7069/*! LPCG_lpcg_rawnand_0_reserved_24_31 - reserved
7070 */
7071#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_MASK)
7072/*! @} */
7073
7074/*! @name LPCG_LPCG_RAWNAND_4 - na */
7075/*! @{ */
7076#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_MASK (0x1FFFFU)
7077#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_SHIFT (0U)
7078/*! LPCG_lpcg_rawnand_4_reserved_0_16 - reserved
7079 */
7080#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_MASK)
7081#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_MASK (0x20000U)
7082#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_SHIFT (17U)
7083/*! apbhdma_hclk_SWEN - Software Enable
7084 * 0b0..Disable SW clock regardless of HWEN
7085 * 0b1..Enable SW clock gating
7086 */
7087#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_MASK)
7088#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_MASK (0x40000U)
7089#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_SHIFT (18U)
7090/*! LPCG_lpcg_rawnand_4_reserved_18_18 - reserved
7091 */
7092#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_MASK)
7093#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_MASK (0x80000U)
7094#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_SHIFT (19U)
7095/*! apbhdma_hclk_STOP - show clock root status, 1 means clock stopped
7096 */
7097#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_MASK)
7098#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_MASK (0xFFF00000U)
7099#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_SHIFT (20U)
7100/*! LPCG_lpcg_rawnand_4_reserved_20_31 - reserved
7101 */
7102#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_MASK)
7103/*! @} */
7104
7105
7106/*!
7107 * @}
7108 */ /* end of group CONNECTIVITY_LPCG_RAWNAND_Register_Masks */
7109
7110
7111/* CONNECTIVITY_LPCG_RAWNAND - Peripheral instance base addresses */
7112/** Peripheral CONNECTIVITY__LPCG_RAWNAND base address */
7113#define CONNECTIVITY__LPCG_RAWNAND_BASE (0x5B290000u)
7114/** Peripheral CONNECTIVITY__LPCG_RAWNAND base pointer */
7115#define CONNECTIVITY__LPCG_RAWNAND ((CONNECTIVITY_LPCG_RAWNAND_Type *)CONNECTIVITY__LPCG_RAWNAND_BASE)
7116/** Array initializer of CONNECTIVITY_LPCG_RAWNAND peripheral base addresses */
7117#define CONNECTIVITY_LPCG_RAWNAND_BASE_ADDRS { CONNECTIVITY__LPCG_RAWNAND_BASE }
7118/** Array initializer of CONNECTIVITY_LPCG_RAWNAND peripheral base pointers */
7119#define CONNECTIVITY_LPCG_RAWNAND_BASE_PTRS { CONNECTIVITY__LPCG_RAWNAND }
7120
7121/*!
7122 * @}
7123 */ /* end of group CONNECTIVITY_LPCG_RAWNAND_Peripheral_Access_Layer */
7124
7125
7126/* ----------------------------------------------------------------------------
7127 -- CONNECTIVITY_LPCG_USB2 Peripheral Access Layer
7128 ---------------------------------------------------------------------------- */
7129
7130/*!
7131 * @addtogroup CONNECTIVITY_LPCG_USB2_Peripheral_Access_Layer CONNECTIVITY_LPCG_USB2 Peripheral Access Layer
7132 * @{
7133 */
7134
7135/** CONNECTIVITY_LPCG_USB2 - Register Layout Typedef */
7136typedef struct {
7137 __IO uint32_t LPCG_LPCG_USB2_0; /**< na, offset: 0x0 */
7138} CONNECTIVITY_LPCG_USB2_Type;
7139
7140/* ----------------------------------------------------------------------------
7141 -- CONNECTIVITY_LPCG_USB2 Register Masks
7142 ---------------------------------------------------------------------------- */
7143
7144/*!
7145 * @addtogroup CONNECTIVITY_LPCG_USB2_Register_Masks CONNECTIVITY_LPCG_USB2 Register Masks
7146 * @{
7147 */
7148
7149/*! @name LPCG_LPCG_USB2_0 - na */
7150/*! @{ */
7151#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_MASK (0x1FFFFU)
7152#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_SHIFT (0U)
7153/*! LPCG_lpcg_usb2_0_reserved_0_16 - reserved
7154 */
7155#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_MASK)
7156#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_MASK (0x20000U)
7157#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_SHIFT (17U)
7158/*! usboh_ipg_clk_s_SWEN - Software Enable
7159 * 0b0..Disable SW clock regardless of HWEN
7160 * 0b1..Enable SW clock gating
7161 */
7162#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_MASK)
7163#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_MASK (0x40000U)
7164#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_SHIFT (18U)
7165/*! LPCG_lpcg_usb2_0_reserved_18_18 - reserved
7166 */
7167#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_MASK)
7168#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_MASK (0x80000U)
7169#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_SHIFT (19U)
7170/*! usboh_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
7171 */
7172#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_MASK)
7173#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_MASK (0x100000U)
7174#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_SHIFT (20U)
7175/*! LPCG_lpcg_usb2_0_reserved_20_20 - reserved
7176 */
7177#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_MASK)
7178#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_MASK (0x200000U)
7179#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_SHIFT (21U)
7180/*! usboh_ipg_clk_s_pl301_SWEN - Software Enable
7181 * 0b0..Disable SW clock regardless of HWEN
7182 * 0b1..Enable SW clock gating
7183 */
7184#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_MASK)
7185#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_MASK (0x400000U)
7186#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_SHIFT (22U)
7187/*! LPCG_lpcg_usb2_0_reserved_22_22 - reserved
7188 */
7189#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_MASK)
7190#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_MASK (0x800000U)
7191#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_SHIFT (23U)
7192/*! usboh_ipg_clk_s_pl301_STOP - show clock root status, 1 means clock stopped
7193 */
7194#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_MASK)
7195#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_MASK (0x1000000U)
7196#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_SHIFT (24U)
7197/*! LPCG_lpcg_usb2_0_reserved_24_24 - reserved
7198 */
7199#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_MASK)
7200#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_MASK (0x2000000U)
7201#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_SHIFT (25U)
7202/*! usboh_ipg_ahb_clk_SWEN - Software Enable
7203 * 0b0..Disable SW clock regardless of HWEN
7204 * 0b1..Enable SW clock gating
7205 */
7206#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_MASK)
7207#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_MASK (0x4000000U)
7208#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_SHIFT (26U)
7209/*! LPCG_lpcg_usb2_0_reserved_26_26 - reserved
7210 */
7211#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_MASK)
7212#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_MASK (0x8000000U)
7213#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_SHIFT (27U)
7214/*! usboh_ipg_ahb_clk_STOP - show clock root status, 1 means clock stopped
7215 */
7216#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_MASK)
7217#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_MASK (0x10000000U)
7218#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_SHIFT (28U)
7219/*! da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN - Hardware Enable
7220 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7221 * 0b1..Enable HW automatic gating
7222 */
7223#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_MASK)
7224#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_MASK (0x20000000U)
7225#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_SHIFT (29U)
7226/*! da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN - Software Enable
7227 * 0b0..Disable SW clock regardless of HWEN
7228 * 0b1..Enable SW clock gating
7229 */
7230#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_MASK)
7231#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_MASK (0x40000000U)
7232#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_SHIFT (30U)
7233/*! LPCG_lpcg_usb2_0_reserved_30_30 - reserved
7234 */
7235#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_MASK)
7236#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_MASK (0x80000000U)
7237#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_SHIFT (31U)
7238/*! da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
7239 */
7240#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_MASK)
7241/*! @} */
7242
7243
7244/*!
7245 * @}
7246 */ /* end of group CONNECTIVITY_LPCG_USB2_Register_Masks */
7247
7248
7249/* CONNECTIVITY_LPCG_USB2 - Peripheral instance base addresses */
7250/** Peripheral CONNECTIVITY__LPCG_USB2 base address */
7251#define CONNECTIVITY__LPCG_USB2_BASE (0x5B270000u)
7252/** Peripheral CONNECTIVITY__LPCG_USB2 base pointer */
7253#define CONNECTIVITY__LPCG_USB2 ((CONNECTIVITY_LPCG_USB2_Type *)CONNECTIVITY__LPCG_USB2_BASE)
7254/** Array initializer of CONNECTIVITY_LPCG_USB2 peripheral base addresses */
7255#define CONNECTIVITY_LPCG_USB2_BASE_ADDRS { CONNECTIVITY__LPCG_USB2_BASE }
7256/** Array initializer of CONNECTIVITY_LPCG_USB2 peripheral base pointers */
7257#define CONNECTIVITY_LPCG_USB2_BASE_PTRS { CONNECTIVITY__LPCG_USB2 }
7258
7259/*!
7260 * @}
7261 */ /* end of group CONNECTIVITY_LPCG_USB2_Peripheral_Access_Layer */
7262
7263
7264/* ----------------------------------------------------------------------------
7265 -- CONNECTIVITY_LPCG_USB3 Peripheral Access Layer
7266 ---------------------------------------------------------------------------- */
7267
7268/*!
7269 * @addtogroup CONNECTIVITY_LPCG_USB3_Peripheral_Access_Layer CONNECTIVITY_LPCG_USB3 Peripheral Access Layer
7270 * @{
7271 */
7272
7273/** CONNECTIVITY_LPCG_USB3 - Register Layout Typedef */
7274typedef struct {
7275 __IO uint32_t LPCG_LPCG_USB3_0; /**< na, offset: 0x0 */
7276} CONNECTIVITY_LPCG_USB3_Type;
7277
7278/* ----------------------------------------------------------------------------
7279 -- CONNECTIVITY_LPCG_USB3 Register Masks
7280 ---------------------------------------------------------------------------- */
7281
7282/*!
7283 * @addtogroup CONNECTIVITY_LPCG_USB3_Register_Masks CONNECTIVITY_LPCG_USB3 Register Masks
7284 * @{
7285 */
7286
7287/*! @name LPCG_LPCG_USB3_0 - na */
7288/*! @{ */
7289#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_MASK (0x1U)
7290#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_SHIFT (0U)
7291/*! LPCG_lpcg_usb3_0_reserved_0_0 - reserved
7292 */
7293#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_MASK)
7294#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_MASK (0x2U)
7295#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_SHIFT (1U)
7296/*! da_ip_usb3_wrap_app_clk_125_predft_SWEN - Software Enable
7297 * 0b0..Disable SW clock regardless of HWEN
7298 * 0b1..Enable SW clock gating
7299 */
7300#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_MASK)
7301#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_MASK (0x4U)
7302#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_SHIFT (2U)
7303/*! LPCG_lpcg_usb3_0_reserved_2_2 - reserved
7304 */
7305#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_MASK)
7306#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_MASK (0x8U)
7307#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_SHIFT (3U)
7308/*! da_ip_usb3_wrap_app_clk_125_predft_STOP - show clock root status, 1 means clock stopped
7309 */
7310#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_MASK)
7311#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_MASK (0x10U)
7312#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_SHIFT (4U)
7313/*! LPCG_lpcg_usb3_0_reserved_4_4 - reserved
7314 */
7315#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_MASK)
7316#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_MASK (0x20U)
7317#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_SHIFT (5U)
7318/*! da_ip_usb3_wrap_lpm_clk_predft_SWEN - Software Enable
7319 * 0b0..Disable SW clock regardless of HWEN
7320 * 0b1..Enable SW clock gating
7321 */
7322#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_MASK)
7323#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_MASK (0x40U)
7324#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_SHIFT (6U)
7325/*! LPCG_lpcg_usb3_0_reserved_6_6 - reserved
7326 */
7327#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_MASK)
7328#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_MASK (0x80U)
7329#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_SHIFT (7U)
7330/*! da_ip_usb3_wrap_lpm_clk_predft_STOP - show clock root status, 1 means clock stopped
7331 */
7332#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_MASK)
7333#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_MASK (0x1FF00U)
7334#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_SHIFT (8U)
7335/*! LPCG_lpcg_usb3_0_reserved_8_16 - reserved
7336 */
7337#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_MASK)
7338#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_MASK (0x20000U)
7339#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_SHIFT (17U)
7340/*! da_ip_usb3_wrap_ipg_clk_SWEN - Software Enable
7341 * 0b0..Disable SW clock regardless of HWEN
7342 * 0b1..Enable SW clock gating
7343 */
7344#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_MASK)
7345#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_MASK (0x40000U)
7346#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_SHIFT (18U)
7347/*! LPCG_lpcg_usb3_0_reserved_18_18 - reserved
7348 */
7349#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_MASK)
7350#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_MASK (0x80000U)
7351#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_SHIFT (19U)
7352/*! da_ip_usb3_wrap_ipg_clk_STOP - show clock root status, 1 means clock stopped
7353 */
7354#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_MASK)
7355#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_MASK (0x100000U)
7356#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_SHIFT (20U)
7357/*! LPCG_lpcg_usb3_0_reserved_20_20 - reserved
7358 */
7359#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_MASK)
7360#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_MASK (0x200000U)
7361#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_SHIFT (21U)
7362/*! da_ip_usb3_wrap_usb3_core_pclk_SWEN - Software Enable
7363 * 0b0..Disable SW clock regardless of HWEN
7364 * 0b1..Enable SW clock gating
7365 */
7366#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_MASK)
7367#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_MASK (0x400000U)
7368#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_SHIFT (22U)
7369/*! LPCG_lpcg_usb3_0_reserved_22_22 - reserved
7370 */
7371#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_MASK)
7372#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_MASK (0x800000U)
7373#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_SHIFT (23U)
7374/*! da_ip_usb3_wrap_usb3_core_pclk_STOP - show clock root status, 1 means clock stopped
7375 */
7376#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_MASK)
7377#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_MASK (0x1000000U)
7378#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_SHIFT (24U)
7379/*! LPCG_lpcg_usb3_0_reserved_24_24 - reserved
7380 */
7381#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_MASK)
7382#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_MASK (0x2000000U)
7383#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_SHIFT (25U)
7384/*! da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN - Software Enable
7385 * 0b0..Disable SW clock regardless of HWEN
7386 * 0b1..Enable SW clock gating
7387 */
7388#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_MASK)
7389#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_MASK (0x4000000U)
7390#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_SHIFT (26U)
7391/*! LPCG_lpcg_usb3_0_reserved_26_26 - reserved
7392 */
7393#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_MASK)
7394#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_MASK (0x8000000U)
7395#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_SHIFT (27U)
7396/*! da_ip_usb3_wrap_usb3_ssphy_pclk_STOP - show clock root status, 1 means clock stopped
7397 */
7398#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_MASK)
7399#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_MASK (0x10000000U)
7400#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_SHIFT (28U)
7401/*! LPCG_lpcg_usb3_0_reserved_28_28 - reserved
7402 */
7403#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_MASK)
7404#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_MASK (0x20000000U)
7405#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_SHIFT (29U)
7406/*! da_ip_usb3_wrap_usb3_aclk_SWEN - Software Enable
7407 * 0b0..Disable SW clock regardless of HWEN
7408 * 0b1..Enable SW clock gating
7409 */
7410#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_MASK)
7411#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_MASK (0x40000000U)
7412#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_SHIFT (30U)
7413/*! LPCG_lpcg_usb3_0_reserved_30_30 - reserved
7414 */
7415#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_MASK)
7416#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_MASK (0x80000000U)
7417#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_SHIFT (31U)
7418/*! da_ip_usb3_wrap_usb3_aclk_STOP - show clock root status, 1 means clock stopped
7419 */
7420#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_MASK)
7421/*! @} */
7422
7423
7424/*!
7425 * @}
7426 */ /* end of group CONNECTIVITY_LPCG_USB3_Register_Masks */
7427
7428
7429/* CONNECTIVITY_LPCG_USB3 - Peripheral instance base addresses */
7430/** Peripheral CONNECTIVITY__LPCG_USB3 base address */
7431#define CONNECTIVITY__LPCG_USB3_BASE (0x5B280000u)
7432/** Peripheral CONNECTIVITY__LPCG_USB3 base pointer */
7433#define CONNECTIVITY__LPCG_USB3 ((CONNECTIVITY_LPCG_USB3_Type *)CONNECTIVITY__LPCG_USB3_BASE)
7434/** Array initializer of CONNECTIVITY_LPCG_USB3 peripheral base addresses */
7435#define CONNECTIVITY_LPCG_USB3_BASE_ADDRS { CONNECTIVITY__LPCG_USB3_BASE }
7436/** Array initializer of CONNECTIVITY_LPCG_USB3 peripheral base pointers */
7437#define CONNECTIVITY_LPCG_USB3_BASE_PTRS { CONNECTIVITY__LPCG_USB3 }
7438
7439/*!
7440 * @}
7441 */ /* end of group CONNECTIVITY_LPCG_USB3_Peripheral_Access_Layer */
7442
7443
7444/* ----------------------------------------------------------------------------
7445 -- CONNECTIVITY_LPCG_USDHC0 Peripheral Access Layer
7446 ---------------------------------------------------------------------------- */
7447
7448/*!
7449 * @addtogroup CONNECTIVITY_LPCG_USDHC0_Peripheral_Access_Layer CONNECTIVITY_LPCG_USDHC0 Peripheral Access Layer
7450 * @{
7451 */
7452
7453/** CONNECTIVITY_LPCG_USDHC0 - Register Layout Typedef */
7454typedef struct {
7455 __IO uint32_t LPCG_LPCG_USDHC1_0; /**< na, offset: 0x0 */
7456} CONNECTIVITY_LPCG_USDHC0_Type;
7457
7458/* ----------------------------------------------------------------------------
7459 -- CONNECTIVITY_LPCG_USDHC0 Register Masks
7460 ---------------------------------------------------------------------------- */
7461
7462/*!
7463 * @addtogroup CONNECTIVITY_LPCG_USDHC0_Register_Masks CONNECTIVITY_LPCG_USDHC0 Register Masks
7464 * @{
7465 */
7466
7467/*! @name LPCG_LPCG_USDHC1_0 - na */
7468/*! @{ */
7469#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_MASK (0x1U)
7470#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_SHIFT (0U)
7471/*! LPCG_lpcg_usdhc1_0_reserved_0_0 - reserved
7472 */
7473#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_MASK)
7474#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_MASK (0x2U)
7475#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_SHIFT (1U)
7476/*! usdhc1_ipg_clk_perclk_SWEN - Software Enable
7477 * 0b0..Disable SW clock regardless of HWEN
7478 * 0b1..Enable SW clock gating
7479 */
7480#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_MASK)
7481#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_MASK (0x4U)
7482#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_SHIFT (2U)
7483/*! LPCG_lpcg_usdhc1_0_reserved_2_2 - reserved
7484 */
7485#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_MASK)
7486#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_MASK (0x8U)
7487#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_SHIFT (3U)
7488/*! usdhc1_ipg_clk_perclk_STOP - show clock root status, 1 means clock stopped
7489 */
7490#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_MASK)
7491#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_MASK (0xFFF0U)
7492#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_SHIFT (4U)
7493/*! LPCG_lpcg_usdhc1_0_reserved_4_15 - reserved
7494 */
7495#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_MASK)
7496#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_MASK (0x10000U)
7497#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_SHIFT (16U)
7498/*! usdhc1_ipg_clk_s_HWEN - Hardware Enable
7499 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7500 * 0b1..Enable HW automatic gating
7501 */
7502#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_MASK)
7503#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_MASK (0x20000U)
7504#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_SHIFT (17U)
7505/*! usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN - Software Enable
7506 * 0b0..Disable SW clock regardless of HWEN
7507 * 0b1..Enable SW clock gating
7508 */
7509#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_MASK)
7510#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_MASK (0x40000U)
7511#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_SHIFT (18U)
7512/*! LPCG_lpcg_usdhc1_0_reserved_18_18 - reserved
7513 */
7514#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_MASK)
7515#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_MASK (0x80000U)
7516#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_SHIFT (19U)
7517/*! usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP - show clock root status, 1 means clock stopped
7518 */
7519#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_MASK)
7520#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_MASK (0x100000U)
7521#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_SHIFT (20U)
7522/*! LPCG_lpcg_usdhc1_0_reserved_20_20 - reserved
7523 */
7524#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_MASK)
7525#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_MASK (0x200000U)
7526#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_SHIFT (21U)
7527/*! usdhc1_hclk_SWEN - Software Enable
7528 * 0b0..Disable SW clock regardless of HWEN
7529 * 0b1..Enable SW clock gating
7530 */
7531#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_MASK)
7532#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_MASK (0x400000U)
7533#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_SHIFT (22U)
7534/*! LPCG_lpcg_usdhc1_0_reserved_22_22 - reserved
7535 */
7536#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_MASK)
7537#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_MASK (0x800000U)
7538#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_SHIFT (23U)
7539/*! usdhc1_hclk_STOP - show clock root status, 1 means clock stopped
7540 */
7541#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_MASK)
7542#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_MASK (0xFF000000U)
7543#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_SHIFT (24U)
7544/*! LPCG_lpcg_usdhc1_0_reserved_24_31 - reserved
7545 */
7546#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_MASK)
7547/*! @} */
7548
7549
7550/*!
7551 * @}
7552 */ /* end of group CONNECTIVITY_LPCG_USDHC0_Register_Masks */
7553
7554
7555/* CONNECTIVITY_LPCG_USDHC0 - Peripheral instance base addresses */
7556/** Peripheral CONNECTIVITY__LPCG_USDHC0 base address */
7557#define CONNECTIVITY__LPCG_USDHC0_BASE (0x5B200000u)
7558/** Peripheral CONNECTIVITY__LPCG_USDHC0 base pointer */
7559#define CONNECTIVITY__LPCG_USDHC0 ((CONNECTIVITY_LPCG_USDHC0_Type *)CONNECTIVITY__LPCG_USDHC0_BASE)
7560/** Array initializer of CONNECTIVITY_LPCG_USDHC0 peripheral base addresses */
7561#define CONNECTIVITY_LPCG_USDHC0_BASE_ADDRS { CONNECTIVITY__LPCG_USDHC0_BASE }
7562/** Array initializer of CONNECTIVITY_LPCG_USDHC0 peripheral base pointers */
7563#define CONNECTIVITY_LPCG_USDHC0_BASE_PTRS { CONNECTIVITY__LPCG_USDHC0 }
7564
7565/*!
7566 * @}
7567 */ /* end of group CONNECTIVITY_LPCG_USDHC0_Peripheral_Access_Layer */
7568
7569
7570/* ----------------------------------------------------------------------------
7571 -- CONNECTIVITY_LPCG_USDHC1 Peripheral Access Layer
7572 ---------------------------------------------------------------------------- */
7573
7574/*!
7575 * @addtogroup CONNECTIVITY_LPCG_USDHC1_Peripheral_Access_Layer CONNECTIVITY_LPCG_USDHC1 Peripheral Access Layer
7576 * @{
7577 */
7578
7579/** CONNECTIVITY_LPCG_USDHC1 - Register Layout Typedef */
7580typedef struct {
7581 __IO uint32_t LPCG_LPCG_USDHC2_0; /**< na, offset: 0x0 */
7582} CONNECTIVITY_LPCG_USDHC1_Type;
7583
7584/* ----------------------------------------------------------------------------
7585 -- CONNECTIVITY_LPCG_USDHC1 Register Masks
7586 ---------------------------------------------------------------------------- */
7587
7588/*!
7589 * @addtogroup CONNECTIVITY_LPCG_USDHC1_Register_Masks CONNECTIVITY_LPCG_USDHC1 Register Masks
7590 * @{
7591 */
7592
7593/*! @name LPCG_LPCG_USDHC2_0 - na */
7594/*! @{ */
7595#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_MASK (0x1U)
7596#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_SHIFT (0U)
7597/*! LPCG_lpcg_usdhc2_0_reserved_0_0 - reserved
7598 */
7599#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_MASK)
7600#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_MASK (0x2U)
7601#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_SHIFT (1U)
7602/*! usdhc2_ipg_clk_perclk_SWEN - Software Enable
7603 * 0b0..Disable SW clock regardless of HWEN
7604 * 0b1..Enable SW clock gating
7605 */
7606#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_MASK)
7607#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_MASK (0x4U)
7608#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_SHIFT (2U)
7609/*! LPCG_lpcg_usdhc2_0_reserved_2_2 - reserved
7610 */
7611#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_MASK)
7612#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_MASK (0x8U)
7613#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_SHIFT (3U)
7614/*! usdhc2_ipg_clk_perclk_STOP - show clock root status, 1 means clock stopped
7615 */
7616#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_MASK)
7617#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_MASK (0xFFF0U)
7618#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_SHIFT (4U)
7619/*! LPCG_lpcg_usdhc2_0_reserved_4_15 - reserved
7620 */
7621#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_MASK)
7622#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_MASK (0x10000U)
7623#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_SHIFT (16U)
7624/*! usdhc2_ipg_clk_s_HWEN - Hardware Enable
7625 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7626 * 0b1..Enable HW automatic gating
7627 */
7628#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_MASK)
7629#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_MASK (0x20000U)
7630#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_SHIFT (17U)
7631/*! usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN - Software Enable
7632 * 0b0..Disable SW clock regardless of HWEN
7633 * 0b1..Enable SW clock gating
7634 */
7635#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_MASK)
7636#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_MASK (0x40000U)
7637#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_SHIFT (18U)
7638/*! LPCG_lpcg_usdhc2_0_reserved_18_18 - reserved
7639 */
7640#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_MASK)
7641#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_MASK (0x80000U)
7642#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_SHIFT (19U)
7643/*! usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP - show clock root status, 1 means clock stopped
7644 */
7645#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_MASK)
7646#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_MASK (0x100000U)
7647#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_SHIFT (20U)
7648/*! LPCG_lpcg_usdhc2_0_reserved_20_20 - reserved
7649 */
7650#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_MASK)
7651#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_MASK (0x200000U)
7652#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_SHIFT (21U)
7653/*! usdhc2_hclk_SWEN - Software Enable
7654 * 0b0..Disable SW clock regardless of HWEN
7655 * 0b1..Enable SW clock gating
7656 */
7657#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_MASK)
7658#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_MASK (0x400000U)
7659#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_SHIFT (22U)
7660/*! LPCG_lpcg_usdhc2_0_reserved_22_22 - reserved
7661 */
7662#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_MASK)
7663#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_MASK (0x800000U)
7664#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_SHIFT (23U)
7665/*! usdhc2_hclk_STOP - show clock root status, 1 means clock stopped
7666 */
7667#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_MASK)
7668#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_MASK (0xFF000000U)
7669#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_SHIFT (24U)
7670/*! LPCG_lpcg_usdhc2_0_reserved_24_31 - reserved
7671 */
7672#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_MASK)
7673/*! @} */
7674
7675
7676/*!
7677 * @}
7678 */ /* end of group CONNECTIVITY_LPCG_USDHC1_Register_Masks */
7679
7680
7681/* CONNECTIVITY_LPCG_USDHC1 - Peripheral instance base addresses */
7682/** Peripheral CONNECTIVITY__LPCG_USDHC1 base address */
7683#define CONNECTIVITY__LPCG_USDHC1_BASE (0x5B210000u)
7684/** Peripheral CONNECTIVITY__LPCG_USDHC1 base pointer */
7685#define CONNECTIVITY__LPCG_USDHC1 ((CONNECTIVITY_LPCG_USDHC1_Type *)CONNECTIVITY__LPCG_USDHC1_BASE)
7686/** Array initializer of CONNECTIVITY_LPCG_USDHC1 peripheral base addresses */
7687#define CONNECTIVITY_LPCG_USDHC1_BASE_ADDRS { CONNECTIVITY__LPCG_USDHC1_BASE }
7688/** Array initializer of CONNECTIVITY_LPCG_USDHC1 peripheral base pointers */
7689#define CONNECTIVITY_LPCG_USDHC1_BASE_PTRS { CONNECTIVITY__LPCG_USDHC1 }
7690
7691/*!
7692 * @}
7693 */ /* end of group CONNECTIVITY_LPCG_USDHC1_Peripheral_Access_Layer */
7694
7695
7696/* ----------------------------------------------------------------------------
7697 -- DC_LPCG Peripheral Access Layer
7698 ---------------------------------------------------------------------------- */
7699
7700/*!
7701 * @addtogroup DC_LPCG_Peripheral_Access_Layer DC_LPCG Peripheral Access Layer
7702 * @{
7703 */
7704
7705/** DC_LPCG - Register Layout Typedef */
7706typedef struct {
7707 __IO uint32_t LPCG_DC_LPCG_0; /**< na, offset: 0x0 */
7708 __IO uint32_t LPCG_DC_LPCG_4; /**< na, offset: 0x4 */
7709 __IO uint32_t LPCG_DC_LPCG_8; /**< na, offset: 0x8 */
7710 uint8_t RESERVED_0[4];
7711 __IO uint32_t LPCG_DC_LPCG_16; /**< na, offset: 0x10 */
7712 __IO uint32_t LPCG_DC_LPCG_20; /**< na, offset: 0x14 */
7713 __IO uint32_t LPCG_DC_LPCG_24; /**< na, offset: 0x18 */
7714 __IO uint32_t LPCG_DC_LPCG_28; /**< na, offset: 0x1C */
7715 __IO uint32_t LPCG_DC_LPCG_32; /**< na, offset: 0x20 */
7716 __IO uint32_t LPCG_DC_LPCG_36; /**< na, offset: 0x24 */
7717 __IO uint32_t LPCG_DC_LPCG_40; /**< na, offset: 0x28 */
7718 __IO uint32_t LPCG_DC_LPCG_44; /**< na, offset: 0x2C */
7719 __IO uint32_t LPCG_DC_LPCG_48; /**< na, offset: 0x30 */
7720 __IO uint32_t LPCG_DC_LPCG_52; /**< na, offset: 0x34 */
7721 __IO uint32_t LPCG_DC_LPCG_56; /**< na, offset: 0x38 */
7722 __IO uint32_t LPCG_DC_LPCG_60; /**< na, offset: 0x3C */
7723 __IO uint32_t LPCG_DC_LPCG_64; /**< na, offset: 0x40 */
7724 __IO uint32_t LPCG_DC_LPCG_68; /**< na, offset: 0x44 */
7725 __IO uint32_t LPCG_DC_LPCG_72; /**< na, offset: 0x48 */
7726} DC_LPCG_Type;
7727
7728/* ----------------------------------------------------------------------------
7729 -- DC_LPCG Register Masks
7730 ---------------------------------------------------------------------------- */
7731
7732/*!
7733 * @addtogroup DC_LPCG_Register_Masks DC_LPCG Register Masks
7734 * @{
7735 */
7736
7737/*! @name LPCG_DC_LPCG_0 - na */
7738/*! @{ */
7739#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_MASK (0x1U)
7740#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_SHIFT (0U)
7741/*! LPCG_dc_lpcg_0_reserved_0_0 - reserved
7742 */
7743#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_MASK)
7744#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_MASK (0x2U)
7745#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_SHIFT (1U)
7746/*! dsp0_clk_SWEN - Software Enable
7747 * 0b0..Disable SW clock regardless of HWEN
7748 * 0b1..Enable SW clock gating
7749 */
7750#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_MASK)
7751#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_MASK (0x4U)
7752#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_SHIFT (2U)
7753/*! LPCG_dc_lpcg_0_reserved_2_2 - reserved
7754 */
7755#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_MASK)
7756#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_MASK (0x8U)
7757#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_SHIFT (3U)
7758/*! dsp0_clk_STOP - show clock root status, 1 means clock stopped
7759 */
7760#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_MASK)
7761#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_MASK (0x10U)
7762#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_SHIFT (4U)
7763/*! LPCG_dc_lpcg_0_reserved_4_4 - reserved
7764 */
7765#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_MASK)
7766#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_MASK (0x20U)
7767#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_SHIFT (5U)
7768/*! dsp1_clk_SWEN - Software Enable
7769 * 0b0..Disable SW clock regardless of HWEN
7770 * 0b1..Enable SW clock gating
7771 */
7772#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_MASK)
7773#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_MASK (0x40U)
7774#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_SHIFT (6U)
7775/*! LPCG_dc_lpcg_0_reserved_6_6 - reserved
7776 */
7777#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_MASK)
7778#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_MASK (0x80U)
7779#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_SHIFT (7U)
7780/*! dsp1_clk_STOP - show clock root status, 1 means clock stopped
7781 */
7782#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_MASK)
7783#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_MASK (0xFFFFFF00U)
7784#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_SHIFT (8U)
7785/*! LPCG_dc_lpcg_0_reserved_8_31 - reserved
7786 */
7787#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_MASK)
7788/*! @} */
7789
7790/*! @name LPCG_DC_LPCG_4 - na */
7791/*! @{ */
7792#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_MASK (0xFFFFU)
7793#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_SHIFT (0U)
7794/*! LPCG_dc_lpcg_4_reserved_0_15 - reserved
7795 */
7796#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_MASK)
7797#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_MASK (0x10000U)
7798#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_SHIFT (16U)
7799/*! lis_ipg_clk_HWEN - Hardware Enable
7800 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7801 * 0b1..Enable HW automatic gating
7802 */
7803#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_MASK)
7804#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_MASK (0x20000U)
7805#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_SHIFT (17U)
7806/*! lis_ipg_clk_SWEN - Software Enable
7807 * 0b0..Disable SW clock regardless of HWEN
7808 * 0b1..Enable SW clock gating
7809 */
7810#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_MASK)
7811#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_MASK (0x40000U)
7812#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_SHIFT (18U)
7813/*! LPCG_dc_lpcg_4_reserved_18_18 - reserved
7814 */
7815#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_MASK)
7816#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_MASK (0x80000U)
7817#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_SHIFT (19U)
7818/*! lis_ipg_clk_STOP - show clock root status, 1 means clock stopped
7819 */
7820#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_MASK)
7821#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_MASK (0xFFF00000U)
7822#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_SHIFT (20U)
7823/*! LPCG_dc_lpcg_4_reserved_20_31 - reserved
7824 */
7825#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_MASK)
7826/*! @} */
7827
7828/*! @name LPCG_DC_LPCG_8 - na */
7829/*! @{ */
7830#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_MASK (0xFFFFU)
7831#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_SHIFT (0U)
7832/*! LPCG_dc_lpcg_8_reserved_0_15 - reserved
7833 */
7834#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_MASK)
7835#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_MASK (0x10000U)
7836#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_SHIFT (16U)
7837/*! display_ctrl_link_mst0_msi_clk_HWEN - Hardware Enable
7838 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7839 * 0b1..Enable HW automatic gating
7840 */
7841#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_MASK)
7842#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_MASK (0x20000U)
7843#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_SHIFT (17U)
7844/*! display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN - Software Enable
7845 * 0b0..Disable SW clock regardless of HWEN
7846 * 0b1..Enable SW clock gating
7847 */
7848#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_MASK)
7849#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_MASK (0x40000U)
7850#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_SHIFT (18U)
7851/*! LPCG_dc_lpcg_8_reserved_18_18 - reserved
7852 */
7853#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_MASK)
7854#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_MASK (0x80000U)
7855#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_SHIFT (19U)
7856/*! display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP - show clock root status, 1 means clock stopped
7857 */
7858#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_MASK)
7859#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_MASK (0xFFF00000U)
7860#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_SHIFT (20U)
7861/*! LPCG_dc_lpcg_8_reserved_20_31 - reserved
7862 */
7863#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_MASK)
7864/*! @} */
7865
7866/*! @name LPCG_DC_LPCG_16 - na */
7867/*! @{ */
7868#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_MASK (0xFFFFU)
7869#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_SHIFT (0U)
7870/*! LPCG_dc_lpcg_16_reserved_0_15 - reserved
7871 */
7872#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_MASK)
7873#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_MASK (0x10000U)
7874#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_SHIFT (16U)
7875/*! pixel_combiner_apb_clk_HWEN - Hardware Enable
7876 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7877 * 0b1..Enable HW automatic gating
7878 */
7879#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_MASK)
7880#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_MASK (0x20000U)
7881#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_SHIFT (17U)
7882/*! pixel_combiner_apb_clk_SWEN - Software Enable
7883 * 0b0..Disable SW clock regardless of HWEN
7884 * 0b1..Enable SW clock gating
7885 */
7886#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_MASK)
7887#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_MASK (0x40000U)
7888#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_SHIFT (18U)
7889/*! LPCG_dc_lpcg_16_reserved_18_18 - reserved
7890 */
7891#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_MASK)
7892#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_MASK (0x80000U)
7893#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_SHIFT (19U)
7894/*! pixel_combiner_apb_clk_STOP - show clock root status, 1 means clock stopped
7895 */
7896#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_MASK)
7897#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_MASK (0xFFF00000U)
7898#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_SHIFT (20U)
7899/*! LPCG_dc_lpcg_16_reserved_20_31 - reserved
7900 */
7901#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_MASK)
7902/*! @} */
7903
7904/*! @name LPCG_DC_LPCG_20 - na */
7905/*! @{ */
7906#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_MASK (0xFFFFU)
7907#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_SHIFT (0U)
7908/*! LPCG_dc_lpcg_20_reserved_0_15 - reserved
7909 */
7910#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_MASK)
7911#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_MASK (0x10000U)
7912#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_SHIFT (16U)
7913/*! iris_mvpl_cfg_clk_HWEN - Hardware Enable
7914 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7915 * 0b1..Enable HW automatic gating
7916 */
7917#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_MASK)
7918#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_MASK (0x20000U)
7919#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_SHIFT (17U)
7920/*! iris_mvpl_cfg_clk_SWEN - Software Enable
7921 * 0b0..Disable SW clock regardless of HWEN
7922 * 0b1..Enable SW clock gating
7923 */
7924#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_MASK)
7925#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_MASK (0x40000U)
7926#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_SHIFT (18U)
7927/*! LPCG_dc_lpcg_20_reserved_18_18 - reserved
7928 */
7929#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_MASK)
7930#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_MASK (0x80000U)
7931#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_SHIFT (19U)
7932/*! iris_mvpl_cfg_clk_STOP - show clock root status, 1 means clock stopped
7933 */
7934#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_MASK)
7935#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_MASK (0x100000U)
7936#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_SHIFT (20U)
7937/*! LPCG_dc_lpcg_20_reserved_20_20 - reserved
7938 */
7939#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_MASK)
7940#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_MASK (0x200000U)
7941#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_SHIFT (21U)
7942/*! iris_mvpl_axi_clk_SWEN - Software Enable
7943 * 0b0..Disable SW clock regardless of HWEN
7944 * 0b1..Enable SW clock gating
7945 */
7946#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_MASK)
7947#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_MASK (0x400000U)
7948#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_SHIFT (22U)
7949/*! LPCG_dc_lpcg_20_reserved_22_22 - reserved
7950 */
7951#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_MASK)
7952#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_MASK (0x800000U)
7953#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_SHIFT (23U)
7954/*! iris_mvpl_axi_clk_STOP - show clock root status, 1 means clock stopped
7955 */
7956#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_MASK)
7957#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_MASK (0xFF000000U)
7958#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_SHIFT (24U)
7959/*! LPCG_dc_lpcg_20_reserved_24_31 - reserved
7960 */
7961#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_MASK)
7962/*! @} */
7963
7964/*! @name LPCG_DC_LPCG_24 - na */
7965/*! @{ */
7966#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_MASK (0xFFFFU)
7967#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_SHIFT (0U)
7968/*! LPCG_dc_lpcg_24_reserved_0_15 - reserved
7969 */
7970#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_MASK)
7971#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_MASK (0x10000U)
7972#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_SHIFT (16U)
7973/*! dpr0_dpr_apb_clkg_HWEN - Hardware Enable
7974 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7975 * 0b1..Enable HW automatic gating
7976 */
7977#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_MASK)
7978#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_MASK (0x20000U)
7979#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_SHIFT (17U)
7980/*! dpr0_dpr_apb_clkg_SWEN - Software Enable
7981 * 0b0..Disable SW clock regardless of HWEN
7982 * 0b1..Enable SW clock gating
7983 */
7984#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_MASK)
7985#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_MASK (0x40000U)
7986#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_SHIFT (18U)
7987/*! LPCG_dc_lpcg_24_reserved_18_18 - reserved
7988 */
7989#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_MASK)
7990#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_MASK (0x80000U)
7991#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_SHIFT (19U)
7992/*! dpr0_dpr_apb_clkg_STOP - show clock root status, 1 means clock stopped
7993 */
7994#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_MASK)
7995#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_MASK (0x100000U)
7996#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_SHIFT (20U)
7997/*! dpr0_dpr_b_clkg_HWEN - Hardware Enable
7998 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7999 * 0b1..Enable HW automatic gating
8000 */
8001#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_MASK)
8002#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_MASK (0x200000U)
8003#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_SHIFT (21U)
8004/*! dpr0_dpr_b_clkg_SWEN - Software Enable
8005 * 0b0..Disable SW clock regardless of HWEN
8006 * 0b1..Enable SW clock gating
8007 */
8008#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_SWEN_MASK)
8009#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_MASK (0x400000U)
8010#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_SHIFT (22U)
8011/*! LPCG_dc_lpcg_24_reserved_22_22 - reserved
8012 */
8013#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_22_22_MASK)
8014#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_MASK (0x800000U)
8015#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_SHIFT (23U)
8016/*! dpr0_dpr_b_clkg_STOP - show clock root status, 1 means clock stopped
8017 */
8018#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_STOP_MASK)
8019#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_MASK (0xFF000000U)
8020#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_SHIFT (24U)
8021/*! LPCG_dc_lpcg_24_reserved_24_31 - reserved
8022 */
8023#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_24_31_MASK)
8024/*! @} */
8025
8026/*! @name LPCG_DC_LPCG_28 - na */
8027/*! @{ */
8028#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_MASK (0x1U)
8029#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_SHIFT (0U)
8030/*! LPCG_dc_lpcg_28_reserved_0_0 - reserved
8031 */
8032#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_0_0_MASK)
8033#define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_MASK (0x2U)
8034#define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_SHIFT (1U)
8035/*! rtram0_rtr_clk_g_SWEN - Software Enable
8036 * 0b0..Disable SW clock regardless of HWEN
8037 * 0b1..Enable SW clock gating
8038 */
8039#define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_SWEN_MASK)
8040#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_MASK (0x4U)
8041#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_SHIFT (2U)
8042/*! LPCG_dc_lpcg_28_reserved_2_2 - reserved
8043 */
8044#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_2_2_MASK)
8045#define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_MASK (0x8U)
8046#define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_SHIFT (3U)
8047/*! rtram0_rtr_clk_g_STOP - show clock root status, 1 means clock stopped
8048 */
8049#define DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_rtram0_rtr_clk_g_STOP_MASK)
8050#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_MASK (0xFFFFFFF0U)
8051#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_SHIFT (4U)
8052/*! LPCG_dc_lpcg_28_reserved_4_31 - reserved
8053 */
8054#define DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_28_LPCG_dc_lpcg_28_reserved_4_31_MASK)
8055/*! @} */
8056
8057/*! @name LPCG_DC_LPCG_32 - na */
8058/*! @{ */
8059#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_MASK (0x1U)
8060#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_SHIFT (0U)
8061/*! LPCG_dc_lpcg_32_reserved_0_0 - reserved
8062 */
8063#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_0_0_MASK)
8064#define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_MASK (0x2U)
8065#define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_SHIFT (1U)
8066/*! prg0_rtram_clk_SWEN - Software Enable
8067 * 0b0..Disable SW clock regardless of HWEN
8068 * 0b1..Enable SW clock gating
8069 */
8070#define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_SWEN_MASK)
8071#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_MASK (0x4U)
8072#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_SHIFT (2U)
8073/*! LPCG_dc_lpcg_32_reserved_2_2 - reserved
8074 */
8075#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_2_2_MASK)
8076#define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_MASK (0x8U)
8077#define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_SHIFT (3U)
8078/*! prg0_rtram_clk_STOP - show clock root status, 1 means clock stopped
8079 */
8080#define DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_rtram_clk_STOP_MASK)
8081#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_MASK (0xFFF0U)
8082#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_SHIFT (4U)
8083/*! LPCG_dc_lpcg_32_reserved_4_15 - reserved
8084 */
8085#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_4_15_MASK)
8086#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_MASK (0x10000U)
8087#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_SHIFT (16U)
8088/*! prg0_apb_clk_HWEN - Hardware Enable
8089 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8090 * 0b1..Enable HW automatic gating
8091 */
8092#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_HWEN_MASK)
8093#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_MASK (0x20000U)
8094#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_SHIFT (17U)
8095/*! prg0_apb_clk_SWEN - Software Enable
8096 * 0b0..Disable SW clock regardless of HWEN
8097 * 0b1..Enable SW clock gating
8098 */
8099#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_SWEN_MASK)
8100#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_MASK (0x40000U)
8101#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_SHIFT (18U)
8102/*! LPCG_dc_lpcg_32_reserved_18_18 - reserved
8103 */
8104#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_18_18_MASK)
8105#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_MASK (0x80000U)
8106#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_SHIFT (19U)
8107/*! prg0_apb_clk_STOP - show clock root status, 1 means clock stopped
8108 */
8109#define DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_prg0_apb_clk_STOP_MASK)
8110#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_MASK (0xFFF00000U)
8111#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_SHIFT (20U)
8112/*! LPCG_dc_lpcg_32_reserved_20_31 - reserved
8113 */
8114#define DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_32_LPCG_dc_lpcg_32_reserved_20_31_MASK)
8115/*! @} */
8116
8117/*! @name LPCG_DC_LPCG_36 - na */
8118/*! @{ */
8119#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_MASK (0x1U)
8120#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_SHIFT (0U)
8121/*! LPCG_dc_lpcg_36_reserved_0_0 - reserved
8122 */
8123#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_0_0_MASK)
8124#define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_MASK (0x2U)
8125#define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_SHIFT (1U)
8126/*! prg1_rtram_clk_SWEN - Software Enable
8127 * 0b0..Disable SW clock regardless of HWEN
8128 * 0b1..Enable SW clock gating
8129 */
8130#define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_SWEN_MASK)
8131#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_MASK (0x4U)
8132#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_SHIFT (2U)
8133/*! LPCG_dc_lpcg_36_reserved_2_2 - reserved
8134 */
8135#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_2_2_MASK)
8136#define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_MASK (0x8U)
8137#define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_SHIFT (3U)
8138/*! prg1_rtram_clk_STOP - show clock root status, 1 means clock stopped
8139 */
8140#define DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_rtram_clk_STOP_MASK)
8141#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_MASK (0xFFF0U)
8142#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_SHIFT (4U)
8143/*! LPCG_dc_lpcg_36_reserved_4_15 - reserved
8144 */
8145#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_4_15_MASK)
8146#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_MASK (0x10000U)
8147#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_SHIFT (16U)
8148/*! prg1_apb_clk_HWEN - Hardware Enable
8149 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8150 * 0b1..Enable HW automatic gating
8151 */
8152#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_HWEN_MASK)
8153#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_MASK (0x20000U)
8154#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_SHIFT (17U)
8155/*! prg1_apb_clk_SWEN - Software Enable
8156 * 0b0..Disable SW clock regardless of HWEN
8157 * 0b1..Enable SW clock gating
8158 */
8159#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_SWEN_MASK)
8160#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_MASK (0x40000U)
8161#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_SHIFT (18U)
8162/*! LPCG_dc_lpcg_36_reserved_18_18 - reserved
8163 */
8164#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_18_18_MASK)
8165#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_MASK (0x80000U)
8166#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_SHIFT (19U)
8167/*! prg1_apb_clk_STOP - show clock root status, 1 means clock stopped
8168 */
8169#define DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_prg1_apb_clk_STOP_MASK)
8170#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_MASK (0xFFF00000U)
8171#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_SHIFT (20U)
8172/*! LPCG_dc_lpcg_36_reserved_20_31 - reserved
8173 */
8174#define DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_36_LPCG_dc_lpcg_36_reserved_20_31_MASK)
8175/*! @} */
8176
8177/*! @name LPCG_DC_LPCG_40 - na */
8178/*! @{ */
8179#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_MASK (0x1U)
8180#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_SHIFT (0U)
8181/*! LPCG_dc_lpcg_40_reserved_0_0 - reserved
8182 */
8183#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_0_0_MASK)
8184#define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_MASK (0x2U)
8185#define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_SHIFT (1U)
8186/*! prg2_rtram_clk_SWEN - Software Enable
8187 * 0b0..Disable SW clock regardless of HWEN
8188 * 0b1..Enable SW clock gating
8189 */
8190#define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_SWEN_MASK)
8191#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_MASK (0x4U)
8192#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_SHIFT (2U)
8193/*! LPCG_dc_lpcg_40_reserved_2_2 - reserved
8194 */
8195#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_2_2_MASK)
8196#define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_MASK (0x8U)
8197#define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_SHIFT (3U)
8198/*! prg2_rtram_clk_STOP - show clock root status, 1 means clock stopped
8199 */
8200#define DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_rtram_clk_STOP_MASK)
8201#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_MASK (0xFFF0U)
8202#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_SHIFT (4U)
8203/*! LPCG_dc_lpcg_40_reserved_4_15 - reserved
8204 */
8205#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_4_15_MASK)
8206#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_MASK (0x10000U)
8207#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_SHIFT (16U)
8208/*! prg2_apb_clk_HWEN - Hardware Enable
8209 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8210 * 0b1..Enable HW automatic gating
8211 */
8212#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_HWEN_MASK)
8213#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_MASK (0x20000U)
8214#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_SHIFT (17U)
8215/*! prg2_apb_clk_SWEN - Software Enable
8216 * 0b0..Disable SW clock regardless of HWEN
8217 * 0b1..Enable SW clock gating
8218 */
8219#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_SWEN_MASK)
8220#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_MASK (0x40000U)
8221#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_SHIFT (18U)
8222/*! LPCG_dc_lpcg_40_reserved_18_18 - reserved
8223 */
8224#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_18_18_MASK)
8225#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_MASK (0x80000U)
8226#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_SHIFT (19U)
8227/*! prg2_apb_clk_STOP - show clock root status, 1 means clock stopped
8228 */
8229#define DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_prg2_apb_clk_STOP_MASK)
8230#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_MASK (0xFFF00000U)
8231#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_SHIFT (20U)
8232/*! LPCG_dc_lpcg_40_reserved_20_31 - reserved
8233 */
8234#define DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_40_LPCG_dc_lpcg_40_reserved_20_31_MASK)
8235/*! @} */
8236
8237/*! @name LPCG_DC_LPCG_44 - na */
8238/*! @{ */
8239#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_MASK (0xFFFFU)
8240#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_SHIFT (0U)
8241/*! LPCG_dc_lpcg_44_reserved_0_15 - reserved
8242 */
8243#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_0_15_MASK)
8244#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_MASK (0x10000U)
8245#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_SHIFT (16U)
8246/*! dpr1_dpr_apb_clkg_HWEN - Hardware Enable
8247 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8248 * 0b1..Enable HW automatic gating
8249 */
8250#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_HWEN_MASK)
8251#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_MASK (0x20000U)
8252#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_SHIFT (17U)
8253/*! dpr1_dpr_apb_clkg_SWEN - Software Enable
8254 * 0b0..Disable SW clock regardless of HWEN
8255 * 0b1..Enable SW clock gating
8256 */
8257#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_SWEN_MASK)
8258#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_MASK (0x40000U)
8259#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_SHIFT (18U)
8260/*! LPCG_dc_lpcg_44_reserved_18_18 - reserved
8261 */
8262#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_18_18_MASK)
8263#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_MASK (0x80000U)
8264#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_SHIFT (19U)
8265/*! dpr1_dpr_apb_clkg_STOP - show clock root status, 1 means clock stopped
8266 */
8267#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_apb_clkg_STOP_MASK)
8268#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_MASK (0x100000U)
8269#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_SHIFT (20U)
8270/*! dpr1_dpr_b_clkg_HWEN - Hardware Enable
8271 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8272 * 0b1..Enable HW automatic gating
8273 */
8274#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_HWEN_MASK)
8275#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_MASK (0x200000U)
8276#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_SHIFT (21U)
8277/*! dpr1_dpr_b_clkg_SWEN - Software Enable
8278 * 0b0..Disable SW clock regardless of HWEN
8279 * 0b1..Enable SW clock gating
8280 */
8281#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_SWEN_MASK)
8282#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_MASK (0x400000U)
8283#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_SHIFT (22U)
8284/*! LPCG_dc_lpcg_44_reserved_22_22 - reserved
8285 */
8286#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_22_22_MASK)
8287#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_MASK (0x800000U)
8288#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_SHIFT (23U)
8289/*! dpr1_dpr_b_clkg_STOP - show clock root status, 1 means clock stopped
8290 */
8291#define DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_dpr1_dpr_b_clkg_STOP_MASK)
8292#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_MASK (0xFF000000U)
8293#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_SHIFT (24U)
8294/*! LPCG_dc_lpcg_44_reserved_24_31 - reserved
8295 */
8296#define DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_44_LPCG_dc_lpcg_44_reserved_24_31_MASK)
8297/*! @} */
8298
8299/*! @name LPCG_DC_LPCG_48 - na */
8300/*! @{ */
8301#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_MASK (0x1U)
8302#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_SHIFT (0U)
8303/*! LPCG_dc_lpcg_48_reserved_0_0 - reserved
8304 */
8305#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_0_0_MASK)
8306#define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_MASK (0x2U)
8307#define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_SHIFT (1U)
8308/*! rtram1_rtr_clk_g_SWEN - Software Enable
8309 * 0b0..Disable SW clock regardless of HWEN
8310 * 0b1..Enable SW clock gating
8311 */
8312#define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_SWEN_MASK)
8313#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_MASK (0x4U)
8314#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_SHIFT (2U)
8315/*! LPCG_dc_lpcg_48_reserved_2_2 - reserved
8316 */
8317#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_2_2_MASK)
8318#define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_MASK (0x8U)
8319#define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_SHIFT (3U)
8320/*! rtram1_rtr_clk_g_STOP - show clock root status, 1 means clock stopped
8321 */
8322#define DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_rtram1_rtr_clk_g_STOP_MASK)
8323#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_MASK (0xFFFFFFF0U)
8324#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_SHIFT (4U)
8325/*! LPCG_dc_lpcg_48_reserved_4_31 - reserved
8326 */
8327#define DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_48_LPCG_dc_lpcg_48_reserved_4_31_MASK)
8328/*! @} */
8329
8330/*! @name LPCG_DC_LPCG_52 - na */
8331/*! @{ */
8332#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_MASK (0x1U)
8333#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_SHIFT (0U)
8334/*! LPCG_dc_lpcg_52_reserved_0_0 - reserved
8335 */
8336#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_0_0_MASK)
8337#define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_MASK (0x2U)
8338#define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_SHIFT (1U)
8339/*! prg3_rtram_clk_SWEN - Software Enable
8340 * 0b0..Disable SW clock regardless of HWEN
8341 * 0b1..Enable SW clock gating
8342 */
8343#define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_SWEN_MASK)
8344#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_MASK (0x4U)
8345#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_SHIFT (2U)
8346/*! LPCG_dc_lpcg_52_reserved_2_2 - reserved
8347 */
8348#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_2_2_MASK)
8349#define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_MASK (0x8U)
8350#define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_SHIFT (3U)
8351/*! prg3_rtram_clk_STOP - show clock root status, 1 means clock stopped
8352 */
8353#define DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_rtram_clk_STOP_MASK)
8354#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_MASK (0xFFF0U)
8355#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_SHIFT (4U)
8356/*! LPCG_dc_lpcg_52_reserved_4_15 - reserved
8357 */
8358#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_4_15_MASK)
8359#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_MASK (0x10000U)
8360#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_SHIFT (16U)
8361/*! prg3_apb_clk_HWEN - Hardware Enable
8362 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8363 * 0b1..Enable HW automatic gating
8364 */
8365#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_HWEN_MASK)
8366#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_MASK (0x20000U)
8367#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_SHIFT (17U)
8368/*! prg3_apb_clk_SWEN - Software Enable
8369 * 0b0..Disable SW clock regardless of HWEN
8370 * 0b1..Enable SW clock gating
8371 */
8372#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_SWEN_MASK)
8373#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_MASK (0x40000U)
8374#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_SHIFT (18U)
8375/*! LPCG_dc_lpcg_52_reserved_18_18 - reserved
8376 */
8377#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_18_18_MASK)
8378#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_MASK (0x80000U)
8379#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_SHIFT (19U)
8380/*! prg3_apb_clk_STOP - show clock root status, 1 means clock stopped
8381 */
8382#define DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_prg3_apb_clk_STOP_MASK)
8383#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_MASK (0xFFF00000U)
8384#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_SHIFT (20U)
8385/*! LPCG_dc_lpcg_52_reserved_20_31 - reserved
8386 */
8387#define DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_52_LPCG_dc_lpcg_52_reserved_20_31_MASK)
8388/*! @} */
8389
8390/*! @name LPCG_DC_LPCG_56 - na */
8391/*! @{ */
8392#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_MASK (0x1U)
8393#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_SHIFT (0U)
8394/*! LPCG_dc_lpcg_56_reserved_0_0 - reserved
8395 */
8396#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_0_0_MASK)
8397#define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_MASK (0x2U)
8398#define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_SHIFT (1U)
8399/*! prg4_rtram_clk_SWEN - Software Enable
8400 * 0b0..Disable SW clock regardless of HWEN
8401 * 0b1..Enable SW clock gating
8402 */
8403#define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_SWEN_MASK)
8404#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_MASK (0x4U)
8405#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_SHIFT (2U)
8406/*! LPCG_dc_lpcg_56_reserved_2_2 - reserved
8407 */
8408#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_2_2_MASK)
8409#define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_MASK (0x8U)
8410#define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_SHIFT (3U)
8411/*! prg4_rtram_clk_STOP - show clock root status, 1 means clock stopped
8412 */
8413#define DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_rtram_clk_STOP_MASK)
8414#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_MASK (0xFFF0U)
8415#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_SHIFT (4U)
8416/*! LPCG_dc_lpcg_56_reserved_4_15 - reserved
8417 */
8418#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_4_15_MASK)
8419#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_MASK (0x10000U)
8420#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_SHIFT (16U)
8421/*! prg4_apb_clk_HWEN - Hardware Enable
8422 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8423 * 0b1..Enable HW automatic gating
8424 */
8425#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_HWEN_MASK)
8426#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_MASK (0x20000U)
8427#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_SHIFT (17U)
8428/*! prg4_apb_clk_SWEN - Software Enable
8429 * 0b0..Disable SW clock regardless of HWEN
8430 * 0b1..Enable SW clock gating
8431 */
8432#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_SWEN_MASK)
8433#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_MASK (0x40000U)
8434#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_SHIFT (18U)
8435/*! LPCG_dc_lpcg_56_reserved_18_18 - reserved
8436 */
8437#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_18_18_MASK)
8438#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_MASK (0x80000U)
8439#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_SHIFT (19U)
8440/*! prg4_apb_clk_STOP - show clock root status, 1 means clock stopped
8441 */
8442#define DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_prg4_apb_clk_STOP_MASK)
8443#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_MASK (0xFFF00000U)
8444#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_SHIFT (20U)
8445/*! LPCG_dc_lpcg_56_reserved_20_31 - reserved
8446 */
8447#define DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_56_LPCG_dc_lpcg_56_reserved_20_31_MASK)
8448/*! @} */
8449
8450/*! @name LPCG_DC_LPCG_60 - na */
8451/*! @{ */
8452#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_MASK (0x1U)
8453#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_SHIFT (0U)
8454/*! LPCG_dc_lpcg_60_reserved_0_0 - reserved
8455 */
8456#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_0_0_MASK)
8457#define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_MASK (0x2U)
8458#define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_SHIFT (1U)
8459/*! prg5_rtram_clk_SWEN - Software Enable
8460 * 0b0..Disable SW clock regardless of HWEN
8461 * 0b1..Enable SW clock gating
8462 */
8463#define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_SWEN_MASK)
8464#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_MASK (0x4U)
8465#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_SHIFT (2U)
8466/*! LPCG_dc_lpcg_60_reserved_2_2 - reserved
8467 */
8468#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_2_2_MASK)
8469#define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_MASK (0x8U)
8470#define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_SHIFT (3U)
8471/*! prg5_rtram_clk_STOP - show clock root status, 1 means clock stopped
8472 */
8473#define DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_rtram_clk_STOP_MASK)
8474#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_MASK (0xFFF0U)
8475#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_SHIFT (4U)
8476/*! LPCG_dc_lpcg_60_reserved_4_15 - reserved
8477 */
8478#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_4_15_MASK)
8479#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_MASK (0x10000U)
8480#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_SHIFT (16U)
8481/*! prg5_apb_clk_HWEN - Hardware Enable
8482 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8483 * 0b1..Enable HW automatic gating
8484 */
8485#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_HWEN_MASK)
8486#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_MASK (0x20000U)
8487#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_SHIFT (17U)
8488/*! prg5_apb_clk_SWEN - Software Enable
8489 * 0b0..Disable SW clock regardless of HWEN
8490 * 0b1..Enable SW clock gating
8491 */
8492#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_SWEN_MASK)
8493#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_MASK (0x40000U)
8494#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_SHIFT (18U)
8495/*! LPCG_dc_lpcg_60_reserved_18_18 - reserved
8496 */
8497#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_18_18_MASK)
8498#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_MASK (0x80000U)
8499#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_SHIFT (19U)
8500/*! prg5_apb_clk_STOP - show clock root status, 1 means clock stopped
8501 */
8502#define DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_prg5_apb_clk_STOP_MASK)
8503#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_MASK (0xFFF00000U)
8504#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_SHIFT (20U)
8505/*! LPCG_dc_lpcg_60_reserved_20_31 - reserved
8506 */
8507#define DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_60_LPCG_dc_lpcg_60_reserved_20_31_MASK)
8508/*! @} */
8509
8510/*! @name LPCG_DC_LPCG_64 - na */
8511/*! @{ */
8512#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_MASK (0x1U)
8513#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_SHIFT (0U)
8514/*! LPCG_dc_lpcg_64_reserved_0_0 - reserved
8515 */
8516#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_0_0_MASK)
8517#define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_MASK (0x2U)
8518#define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_SHIFT (1U)
8519/*! prg6_rtram_clk_SWEN - Software Enable
8520 * 0b0..Disable SW clock regardless of HWEN
8521 * 0b1..Enable SW clock gating
8522 */
8523#define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_SWEN_MASK)
8524#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_MASK (0x4U)
8525#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_SHIFT (2U)
8526/*! LPCG_dc_lpcg_64_reserved_2_2 - reserved
8527 */
8528#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_2_2_MASK)
8529#define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_MASK (0x8U)
8530#define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_SHIFT (3U)
8531/*! prg6_rtram_clk_STOP - show clock root status, 1 means clock stopped
8532 */
8533#define DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_rtram_clk_STOP_MASK)
8534#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_MASK (0xFFF0U)
8535#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_SHIFT (4U)
8536/*! LPCG_dc_lpcg_64_reserved_4_15 - reserved
8537 */
8538#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_4_15_MASK)
8539#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_MASK (0x10000U)
8540#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_SHIFT (16U)
8541/*! prg6_apb_clk_HWEN - Hardware Enable
8542 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8543 * 0b1..Enable HW automatic gating
8544 */
8545#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_HWEN_MASK)
8546#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_MASK (0x20000U)
8547#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_SHIFT (17U)
8548/*! prg6_apb_clk_SWEN - Software Enable
8549 * 0b0..Disable SW clock regardless of HWEN
8550 * 0b1..Enable SW clock gating
8551 */
8552#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_SWEN_MASK)
8553#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_MASK (0x40000U)
8554#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_SHIFT (18U)
8555/*! LPCG_dc_lpcg_64_reserved_18_18 - reserved
8556 */
8557#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_18_18_MASK)
8558#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_MASK (0x80000U)
8559#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_SHIFT (19U)
8560/*! prg6_apb_clk_STOP - show clock root status, 1 means clock stopped
8561 */
8562#define DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_prg6_apb_clk_STOP_MASK)
8563#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_MASK (0xFFF00000U)
8564#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_SHIFT (20U)
8565/*! LPCG_dc_lpcg_64_reserved_20_31 - reserved
8566 */
8567#define DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_64_LPCG_dc_lpcg_64_reserved_20_31_MASK)
8568/*! @} */
8569
8570/*! @name LPCG_DC_LPCG_68 - na */
8571/*! @{ */
8572#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_MASK (0x1U)
8573#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_SHIFT (0U)
8574/*! LPCG_dc_lpcg_68_reserved_0_0 - reserved
8575 */
8576#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_0_0_MASK)
8577#define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_MASK (0x2U)
8578#define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_SHIFT (1U)
8579/*! prg7_rtram_clk_SWEN - Software Enable
8580 * 0b0..Disable SW clock regardless of HWEN
8581 * 0b1..Enable SW clock gating
8582 */
8583#define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_SWEN_MASK)
8584#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_MASK (0x4U)
8585#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_SHIFT (2U)
8586/*! LPCG_dc_lpcg_68_reserved_2_2 - reserved
8587 */
8588#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_2_2_MASK)
8589#define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_MASK (0x8U)
8590#define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_SHIFT (3U)
8591/*! prg7_rtram_clk_STOP - show clock root status, 1 means clock stopped
8592 */
8593#define DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_rtram_clk_STOP_MASK)
8594#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_MASK (0xFFF0U)
8595#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_SHIFT (4U)
8596/*! LPCG_dc_lpcg_68_reserved_4_15 - reserved
8597 */
8598#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_4_15_MASK)
8599#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_MASK (0x10000U)
8600#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_SHIFT (16U)
8601/*! prg7_apb_clk_HWEN - Hardware Enable
8602 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8603 * 0b1..Enable HW automatic gating
8604 */
8605#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_HWEN_MASK)
8606#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_MASK (0x20000U)
8607#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_SHIFT (17U)
8608/*! prg7_apb_clk_SWEN - Software Enable
8609 * 0b0..Disable SW clock regardless of HWEN
8610 * 0b1..Enable SW clock gating
8611 */
8612#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_SWEN_MASK)
8613#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_MASK (0x40000U)
8614#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_SHIFT (18U)
8615/*! LPCG_dc_lpcg_68_reserved_18_18 - reserved
8616 */
8617#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_18_18_MASK)
8618#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_MASK (0x80000U)
8619#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_SHIFT (19U)
8620/*! prg7_apb_clk_STOP - show clock root status, 1 means clock stopped
8621 */
8622#define DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_prg7_apb_clk_STOP_MASK)
8623#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_MASK (0xFFF00000U)
8624#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_SHIFT (20U)
8625/*! LPCG_dc_lpcg_68_reserved_20_31 - reserved
8626 */
8627#define DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_68_LPCG_dc_lpcg_68_reserved_20_31_MASK)
8628/*! @} */
8629
8630/*! @name LPCG_DC_LPCG_72 - na */
8631/*! @{ */
8632#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_MASK (0x1U)
8633#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_SHIFT (0U)
8634/*! LPCG_dc_lpcg_72_reserved_0_0 - reserved
8635 */
8636#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_0_0_MASK)
8637#define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_MASK (0x2U)
8638#define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_SHIFT (1U)
8639/*! prg8_rtram_clk_SWEN - Software Enable
8640 * 0b0..Disable SW clock regardless of HWEN
8641 * 0b1..Enable SW clock gating
8642 */
8643#define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_SWEN_MASK)
8644#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_MASK (0x4U)
8645#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_SHIFT (2U)
8646/*! LPCG_dc_lpcg_72_reserved_2_2 - reserved
8647 */
8648#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_2_2_MASK)
8649#define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_MASK (0x8U)
8650#define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_SHIFT (3U)
8651/*! prg8_rtram_clk_STOP - show clock root status, 1 means clock stopped
8652 */
8653#define DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_rtram_clk_STOP_MASK)
8654#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_MASK (0xFFF0U)
8655#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_SHIFT (4U)
8656/*! LPCG_dc_lpcg_72_reserved_4_15 - reserved
8657 */
8658#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_4_15_MASK)
8659#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_MASK (0x10000U)
8660#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_SHIFT (16U)
8661/*! prg8_apb_clk_HWEN - Hardware Enable
8662 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
8663 * 0b1..Enable HW automatic gating
8664 */
8665#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_HWEN_MASK)
8666#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_MASK (0x20000U)
8667#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_SHIFT (17U)
8668/*! prg8_apb_clk_SWEN - Software Enable
8669 * 0b0..Disable SW clock regardless of HWEN
8670 * 0b1..Enable SW clock gating
8671 */
8672#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_SWEN_MASK)
8673#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_MASK (0x40000U)
8674#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_SHIFT (18U)
8675/*! LPCG_dc_lpcg_72_reserved_18_18 - reserved
8676 */
8677#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_18_18_MASK)
8678#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_MASK (0x80000U)
8679#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_SHIFT (19U)
8680/*! prg8_apb_clk_STOP - show clock root status, 1 means clock stopped
8681 */
8682#define DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_prg8_apb_clk_STOP_MASK)
8683#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_MASK (0xFFF00000U)
8684#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_SHIFT (20U)
8685/*! LPCG_dc_lpcg_72_reserved_20_31 - reserved
8686 */
8687#define DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_72_LPCG_dc_lpcg_72_reserved_20_31_MASK)
8688/*! @} */
8689
8690
8691/*!
8692 * @}
8693 */ /* end of group DC_LPCG_Register_Masks */
8694
8695
8696/* DC_LPCG - Peripheral instance base addresses */
8697/** Peripheral DC__LPCG_DSP0_CLK base address */
8698#define DC__LPCG_DSP0_CLK_BASE (0x56010000u)
8699/** Peripheral DC__LPCG_DSP0_CLK base pointer */
8700#define DC__LPCG_DSP0_CLK ((DC_LPCG_Type *)DC__LPCG_DSP0_CLK_BASE)
8701/** Array initializer of DC_LPCG peripheral base addresses */
8702#define DC_LPCG_BASE_ADDRS { DC__LPCG_DSP0_CLK_BASE }
8703/** Array initializer of DC_LPCG peripheral base pointers */
8704#define DC_LPCG_BASE_PTRS { DC__LPCG_DSP0_CLK }
8705
8706/*!
8707 * @}
8708 */ /* end of group DC_LPCG_Peripheral_Access_Layer */
8709
8710
8711/* ----------------------------------------------------------------------------
8712 -- DDRC Peripheral Access Layer
8713 ---------------------------------------------------------------------------- */
8714
8715/*!
8716 * @addtogroup DDRC_Peripheral_Access_Layer DDRC Peripheral Access Layer
8717 * @{
8718 */
8719
8720/** DDRC - Register Layout Typedef */
8721typedef struct {
8722 __IO uint32_t MSTR; /**< Master Register0, offset: 0x0 */
8723 __I uint32_t STAT; /**< Operating Mode Status Register, offset: 0x4 */
8724 __IO uint32_t MSTR1; /**< Operating Mode Status Register, offset: 0x8 */
8725 __IO uint32_t MRCTRL3; /**< Operating Mode Status Register, offset: 0xC */
8726 __IO uint32_t MRCTRL0; /**< Mode Register Read/Write Control Register 0., offset: 0x10 */
8727 __IO uint32_t MRCTRL1; /**< Mode Register Read/Write Control Register 1, offset: 0x14 */
8728 __I uint32_t MRSTAT; /**< Mode Register Read/Write Status Register, offset: 0x18 */
8729 __IO uint32_t MRCTRL2; /**< Mode Register Read/Write Control Register 2, offset: 0x1C */
8730 __IO uint32_t DERATEEN; /**< Temperature Derate Enable Register, offset: 0x20 */
8731 __IO uint32_t DERATEINT; /**< Temperature Derate Interval Register, offset: 0x24 */
8732 uint8_t RESERVED_0[8];
8733 __IO uint32_t PWRCTL; /**< Low Power Control Register, offset: 0x30 */
8734 __IO uint32_t PWRTMG; /**< Low Power Timing Register, offset: 0x34 */
8735 __IO uint32_t HWLPCTL; /**< Hardware Low Power Control Register, offset: 0x38 */
8736 uint8_t RESERVED_1[20];
8737 __IO uint32_t RFSHCTL0; /**< Refresh Control Register 0, offset: 0x50 */
8738 __IO uint32_t RFSHCTL1; /**< Refresh Control Register 1, offset: 0x54 */
8739 uint8_t RESERVED_2[8];
8740 __IO uint32_t RFSHCTL3; /**< Refresh Control Register 3, offset: 0x60 */
8741 __IO uint32_t RFSHTMG; /**< Refresh Timing Register, offset: 0x64 */
8742 uint8_t RESERVED_3[104];
8743 __IO uint32_t INIT0; /**< SDRAM Initialization Register 0, offset: 0xD0 */
8744 __IO uint32_t INIT1; /**< SDRAM Initialization Register 1, offset: 0xD4 */
8745 __IO uint32_t INIT2; /**< SDRAM Initialization Register 2, offset: 0xD8 */
8746 __IO uint32_t INIT3; /**< SDRAM Initialization Register 3, offset: 0xDC */
8747 __IO uint32_t INIT4; /**< SDRAM Initialization Register 4, offset: 0xE0 */
8748 __IO uint32_t INIT5; /**< SDRAM Initialization Register 5, offset: 0xE4 */
8749 __IO uint32_t INIT6; /**< SDRAM Initialization Register 6, offset: 0xE8 */
8750 __IO uint32_t INIT7; /**< SDRAM Initialization Register 7, offset: 0xEC */
8751 __IO uint32_t DIMMCTL; /**< DIMM Control Register, offset: 0xF0 */
8752 __IO uint32_t RANKCTL; /**< Rank Control Register, offset: 0xF4 */
8753 uint8_t RESERVED_4[8];
8754 __IO uint32_t DRAMTMG0; /**< SDRAM Timing Register 0, offset: 0x100 */
8755 __IO uint32_t DRAMTMG1; /**< SDRAM Timing Register 1, offset: 0x104 */
8756 __IO uint32_t DRAMTMG2; /**< SDRAM Timing Register 2, offset: 0x108 */
8757 __IO uint32_t DRAMTMG3; /**< SDRAM Timing Register 3, offset: 0x10C */
8758 __IO uint32_t DRAMTMG4; /**< SDRAM Timing Register 4, offset: 0x110 */
8759 __IO uint32_t DRAMTMG5; /**< SDRAM Timing Register 5, offset: 0x114 */
8760 __IO uint32_t DRAMTMG6; /**< SDRAM Timing Register 6, offset: 0x118 */
8761 __IO uint32_t DRAMTMG7; /**< SDRAM Timing Register 7, offset: 0x11C */
8762 __IO uint32_t DRAMTMG8; /**< SDRAM Timing Register 8, offset: 0x120 */
8763 __IO uint32_t DRAMTMG9; /**< SDRAM Timing Register 9, offset: 0x124 */
8764 __IO uint32_t DRAMTMG10; /**< SDRAM Timing Register 10, offset: 0x128 */
8765 __IO uint32_t DRAMTMG11; /**< SDRAM Timing Register 11, offset: 0x12C */
8766 __IO uint32_t DRAMTMG12; /**< SDRAM Timing Register 12, offset: 0x130 */
8767 __IO uint32_t DRAMTMG13; /**< SDRAM Timing Register 13, offset: 0x134 */
8768 __IO uint32_t DRAMTMG14; /**< SDRAM Timing Register 14, offset: 0x138 */
8769 __IO uint32_t DRAMTMG15; /**< SDRAM Timing Register 15, offset: 0x13C */
8770 uint8_t RESERVED_5[64];
8771 __IO uint32_t ZQCTL0; /**< ZQ Control Register 0, offset: 0x180 */
8772 __IO uint32_t ZQCTL1; /**< ZQ Control Register 1, offset: 0x184 */
8773 __IO uint32_t ZQCTL2; /**< ZQ Control Register 2, offset: 0x188 */
8774 __I uint32_t ZQSTAT; /**< ZQ Status Register, offset: 0x18C */
8775 __IO uint32_t DFITMG0; /**< DFI Timing Register 0, offset: 0x190 */
8776 __IO uint32_t DFITMG1; /**< DFI Timing Register 1, offset: 0x194 */
8777 __IO uint32_t DFILPCFG0; /**< DFI Low Power Configuration Register 0, offset: 0x198 */
8778 __IO uint32_t DFILPCFG1; /**< DFI Low Power Configuration Register 1, offset: 0x19C */
8779 __IO uint32_t DFIUPD0; /**< DFI Update Register 0, offset: 0x1A0 */
8780 __IO uint32_t DFIUPD1; /**< DFI Update Register 1, offset: 0x1A4 */
8781 __IO uint32_t DFIUPD2; /**< DFI Update Register 2, offset: 0x1A8 */
8782 uint8_t RESERVED_6[4];
8783 __IO uint32_t DFIMISC; /**< DFI Miscellaneous Control Register, offset: 0x1B0 */
8784 __IO uint32_t DFITMG2; /**< DFI Timing Register 2, offset: 0x1B4 */
8785 __IO uint32_t DFITMG3; /**< DFI Timing Register 3, offset: 0x1B8 */
8786 __I uint32_t DFISTAT; /**< DFI Status Register, offset: 0x1BC */
8787 __IO uint32_t DBICTL; /**< DM/DBI Control Register, offset: 0x1C0 */
8788 uint8_t RESERVED_7[60];
8789 __IO uint32_t ADDRMAP0; /**< Address Map Register 0, offset: 0x200 */
8790 __IO uint32_t ADDRMAP1; /**< Address Map Register 1, offset: 0x204 */
8791 __IO uint32_t ADDRMAP2; /**< Address Map Register 2, offset: 0x208 */
8792 __IO uint32_t ADDRMAP3; /**< Address Map Register 3, offset: 0x20C */
8793 __IO uint32_t ADDRMAP4; /**< Address Map Register 4, offset: 0x210 */
8794 __IO uint32_t ADDRMAP5; /**< Address Map Register 5, offset: 0x214 */
8795 __IO uint32_t ADDRMAP6; /**< Address Map Register 6, offset: 0x218 */
8796 __IO uint32_t ADDRMAP7; /**< Address Map Register 7, offset: 0x21C */
8797 __IO uint32_t ADDRMAP8; /**< Address Map Register 8, offset: 0x220 */
8798 __IO uint32_t ADDRMAP9; /**< Address Map Register 9, offset: 0x224 */
8799 __IO uint32_t ADDRMAP10; /**< Address Map Register 10, offset: 0x228 */
8800 __IO uint32_t ADDRMAP11; /**< Address Map Register 11, offset: 0x22C */
8801 uint8_t RESERVED_8[16];
8802 __IO uint32_t ODTCFG; /**< ODT Configuration Register, offset: 0x240 */
8803 __IO uint32_t ODTMAP; /**< ODT/Rank Map Register, offset: 0x244 */
8804 uint8_t RESERVED_9[8];
8805 __IO uint32_t SCHED; /**< Scheduler Control Register, offset: 0x250 */
8806 __IO uint32_t SCHED1; /**< Scheduler Control Register 1, offset: 0x254 */
8807 uint8_t RESERVED_10[4];
8808 __IO uint32_t PERFHPR1; /**< High Priority Read CAM Register 1, offset: 0x25C */
8809 uint8_t RESERVED_11[4];
8810 __IO uint32_t PERFLPR1; /**< Low Priority Read CAM Register 1, offset: 0x264 */
8811 uint8_t RESERVED_12[4];
8812 __IO uint32_t PERFWR1; /**< Write CAM Register 1, offset: 0x26C */
8813 uint8_t RESERVED_13[144];
8814 __IO uint32_t DBG0; /**< Debug Register 0, offset: 0x300 */
8815 __IO uint32_t DBG1; /**< Debug Register 1, offset: 0x304 */
8816 __I uint32_t DBGCAM; /**< CAM Debug Register, offset: 0x308 */
8817 __IO uint32_t DBGCMD; /**< Command Debug Register, offset: 0x30C */
8818 __I uint32_t DBGSTAT; /**< Status Debug Register, offset: 0x310 */
8819 uint8_t RESERVED_14[12];
8820 __IO uint32_t SWCTL; /**< Software Register Programming Control Enable, offset: 0x320 */
8821 __I uint32_t SWSTAT; /**< Software Register Programming Control Status, offset: 0x324 */
8822 uint8_t RESERVED_15[68];
8823 __IO uint32_t POISONCFG; /**< AXI Poison Configuration Register., offset: 0x36C */
8824 __I uint32_t POISONSTAT; /**< AXI Poison Status Register, offset: 0x370 */
8825 uint8_t RESERVED_16[136];
8826 __I uint32_t PSTAT; /**< Port Status Register, offset: 0x3FC */
8827 __IO uint32_t PCCFG; /**< Port Common Configuration Register, offset: 0x400 */
8828 __IO uint32_t PCFGR_0; /**< Port n Configuration Read Register, offset: 0x404 */
8829 __IO uint32_t PCFGW_0; /**< Port n Configuration Write Register, offset: 0x408 */
8830 uint8_t RESERVED_17[132];
8831 __IO uint32_t PCTRL_0; /**< Port n Control Register, offset: 0x490 */
8832 __IO uint32_t PCFGQOS0_0; /**< Port n Read QoS Configuration Register 0, offset: 0x494 */
8833 __IO uint32_t PCFGQOS1_0; /**< Port n Read QoS Configuration Register 1, offset: 0x498 */
8834 __IO uint32_t PCFGWQOS0_0; /**< Port n Write QoS Configuration Register 0, offset: 0x49C */
8835 __IO uint32_t PCFGWQOS1_0; /**< Port n Write QoS Configuration Register 1, offset: 0x4A0 */
8836 uint8_t RESERVED_18[7036];
8837 __IO uint32_t DERATEEN_SHADOW; /**< [SHADOW] Temperature Derate Enable Register, offset: 0x2020 */
8838 __IO uint32_t DERATEINT_SHADOW; /**< [SHADOW] Temperature Derate Interval Register, offset: 0x2024 */
8839 uint8_t RESERVED_19[40];
8840 __IO uint32_t RFSHCTL0_SHADOW; /**< [SHADOW] Refresh Control Register 0, offset: 0x2050 */
8841 uint8_t RESERVED_20[16];
8842 __IO uint32_t RFSHTMG_SHADOW; /**< [SHADOW] Refresh Timing Register, offset: 0x2064 */
8843 uint8_t RESERVED_21[116];
8844 __IO uint32_t INIT3_SHADOW; /**< [SHADOW] SDRAM Initialization Register 3, offset: 0x20DC */
8845 __IO uint32_t INIT4_SHADOW; /**< [SHADOW] SDRAM Initialization Register 4, offset: 0x20E0 */
8846 uint8_t RESERVED_22[4];
8847 __IO uint32_t INIT6_SHADOW; /**< [SHADOW] SDRAM Initialization Register 6, offset: 0x20E8 */
8848 __IO uint32_t INIT7_SHADOW; /**< [SHADOW] SDRAM Initialization Register 7, offset: 0x20EC */
8849 uint8_t RESERVED_23[16];
8850 __IO uint32_t DRAMTMG0_SHADOW; /**< [SHADOW] SDRAM Timing Register 0, offset: 0x2100 */
8851 __IO uint32_t DRAMTMG1_SHADOW; /**< [SHADOW] SDRAM Timing Register 1, offset: 0x2104 */
8852 __IO uint32_t DRAMTMG2_SHADOW; /**< [SHADOW] SDRAM Timing Register 2, offset: 0x2108 */
8853 __IO uint32_t DRAMTMG3_SHADOW; /**< [SHADOW] SDRAM Timing Register 3, offset: 0x210C */
8854 __IO uint32_t DRAMTMG4_SHADOW; /**< [SHADOW] SDRAM Timing Register 4, offset: 0x2110 */
8855 __IO uint32_t DRAMTMG5_SHADOW; /**< [SHADOW] SDRAM Timing Register 5, offset: 0x2114 */
8856 __IO uint32_t DRAMTMG6_SHADOW; /**< [SHADOW] SDRAM Timing Register 6, offset: 0x2118 */
8857 __IO uint32_t DRAMTMG7_SHADOW; /**< [SHADOW] SDRAM Timing Register 7, offset: 0x211C */
8858 __IO uint32_t DRAMTMG8_SHADOW; /**< [SHADOW] SDRAM Timing Register 8, offset: 0x2120 */
8859 __IO uint32_t DRAMTMG9_SHADOW; /**< [SHADOW] SDRAM Timing Register 9, offset: 0x2124 */
8860 __IO uint32_t DRAMTMG10_SHADOW; /**< [SHADOW] SDRAM Timing Register 10, offset: 0x2128 */
8861 __IO uint32_t DRAMTMG11_SHADOW; /**< [SHADOW] SDRAM Timing Register 11, offset: 0x212C */
8862 __IO uint32_t DRAMTMG12_SHADOW; /**< [SHADOW] SDRAM Timing Register 12, offset: 0x2130 */
8863 __IO uint32_t DRAMTMG13_SHADOW; /**< [SHADOW] SDRAM Timing Register 13, offset: 0x2134 */
8864 __IO uint32_t DRAMTMG14_SHADOW; /**< [SHADOW] SDRAM Timing Register 14, offset: 0x2138 */
8865 __IO uint32_t DRAMTMG15_SHADOW; /**< [SHADOW] SDRAM Timing Register 15, offset: 0x213C */
8866 uint8_t RESERVED_24[64];
8867 __IO uint32_t ZQCTL0_SHADOW; /**< [SHADOW] ZQ Control Register 0, offset: 0x2180 */
8868 uint8_t RESERVED_25[12];
8869 __IO uint32_t DFITMG0_SHADOW; /**< [SHADOW] DFI Timing Register 0, offset: 0x2190 */
8870 __IO uint32_t DFITMG1_SHADOW; /**< [SHADOW] DFI Timing Register 1, offset: 0x2194 */
8871 uint8_t RESERVED_26[28];
8872 __IO uint32_t DFITMG2_SHADOW; /**< [SHADOW] DFI Timing Register 2, offset: 0x21B4 */
8873 __IO uint32_t DFITMG3_SHADOW; /**< [SHADOW] DFI Timing Register 3, offset: 0x21B8 */
8874 uint8_t RESERVED_27[132];
8875 __IO uint32_t ODTCFG_SHADOW; /**< [SHADOW] ODT Configuration Register, offset: 0x2240 */
8876} DDRC_Type;
8877
8878/* ----------------------------------------------------------------------------
8879 -- DDRC Register Masks
8880 ---------------------------------------------------------------------------- */
8881
8882/*!
8883 * @addtogroup DDRC_Register_Masks DDRC Register Masks
8884 * @{
8885 */
8886
8887/*! @name MSTR - Master Register0 */
8888/*! @{ */
8889#define DDRC_MSTR_ddr3_MASK (0x1U)
8890#define DDRC_MSTR_ddr3_SHIFT (0U)
8891/*! ddr3 - Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only
8892 * present in designs that support DDR3.
8893 */
8894#define DDRC_MSTR_ddr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_ddr3_SHIFT)) & DDRC_MSTR_ddr3_MASK)
8895#define DDRC_MSTR_lpddr2_MASK (0x4U)
8896#define DDRC_MSTR_lpddr2_SHIFT (2U)
8897/*! lpddr2 - Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use
8898 * Present only in designs configured to support LPDDR2.
8899 */
8900#define DDRC_MSTR_lpddr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr2_SHIFT)) & DDRC_MSTR_lpddr2_MASK)
8901#define DDRC_MSTR_lpddr3_MASK (0x8U)
8902#define DDRC_MSTR_lpddr3_SHIFT (3U)
8903/*! lpddr3 - Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use
8904 * Present only in designs configured to support LPDDR3.
8905 */
8906#define DDRC_MSTR_lpddr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr3_SHIFT)) & DDRC_MSTR_lpddr3_MASK)
8907#define DDRC_MSTR_ddr4_MASK (0x10U)
8908#define DDRC_MSTR_ddr4_SHIFT (4U)
8909/*! ddr4 - Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present
8910 * only in designs configured to support DDR4.
8911 */
8912#define DDRC_MSTR_ddr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_ddr4_SHIFT)) & DDRC_MSTR_ddr4_MASK)
8913#define DDRC_MSTR_lpddr4_MASK (0x20U)
8914#define DDRC_MSTR_lpddr4_SHIFT (5U)
8915/*! lpddr4 - Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use
8916 * Present only in designs configured to support LPDDR4.
8917 */
8918#define DDRC_MSTR_lpddr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_lpddr4_SHIFT)) & DDRC_MSTR_lpddr4_MASK)
8919#define DDRC_MSTR_burstchop_MASK (0x200U)
8920#define DDRC_MSTR_burstchop_SHIFT (9U)
8921/*! burstchop - When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. Burst Chop for Reads
8922 * is exercised only in HIF configurations (DDRC_INCL_ARB not set) and if in full bus width mode
8923 * (MSTR.data_bus_width = 00) and if MEMC_BURST_LENGTH=8 or 16. Burst Chop for Writes is
8924 * exercised only if Partial Writes enabled (DDRC_PARTIAL_WR=1) and if CRC is disabled
8925 * (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1),
8926 * burst chop is not supported, and this bit must be set to '0'. BC4 (fixed) mode is not supported.
8927 */
8928#define DDRC_MSTR_burstchop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_burstchop_SHIFT)) & DDRC_MSTR_burstchop_MASK)
8929#define DDRC_MSTR_en_2t_timing_mode_MASK (0x400U)
8930#define DDRC_MSTR_en_2t_timing_mode_SHIFT (10U)
8931/*! en_2t_timing_mode - If 1, then DDRC uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all
8932 * command signals (except chip select) are held for 2 clocks on the SDRAM bus. Chip select is
8933 * asserted on the second cycle of the command Note: 2T timing is not supported in
8934 * LPDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE
8935 * is set Note: 2T timing is not supported in DDR4 geardown mode. Note: 2T timing is not supported
8936 * in Shared-AC dual channel mode and the register value is don't care.
8937 */
8938#define DDRC_MSTR_en_2t_timing_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_en_2t_timing_mode_SHIFT)) & DDRC_MSTR_en_2t_timing_mode_MASK)
8939#define DDRC_MSTR_geardown_mode_MASK (0x800U)
8940#define DDRC_MSTR_geardown_mode_SHIFT (11U)
8941/*! geardown_mode - 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in
8942 * normal mode (1N). This register can be changed, only when the Controller is in self-refresh
8943 * mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode is not supported
8944 * if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: Geardown mode is not supported
8945 * if the configuration parameter DDRC_SHARED_AC is set (in Shared-AC mode) and the register value
8946 * is don't care
8947 */
8948#define DDRC_MSTR_geardown_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_geardown_mode_SHIFT)) & DDRC_MSTR_geardown_mode_MASK)
8949#define DDRC_MSTR_data_bus_width_MASK (0x3000U)
8950#define DDRC_MSTR_data_bus_width_SHIFT (12U)
8951/*! data_bus_width - Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus
8952 * width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter DQ bus width to SDRAM - 11 -
8953 * Reserved. Note that half bus width mode is only supported when the SDRAM bus width is a
8954 * multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple
8955 * of 32 and the configuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus
8956 * width (excluding any ECC width).
8957 */
8958#define DDRC_MSTR_data_bus_width(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_data_bus_width_SHIFT)) & DDRC_MSTR_data_bus_width_MASK)
8959#define DDRC_MSTR_dll_off_mode_MASK (0x8000U)
8960#define DDRC_MSTR_dll_off_mode_SHIFT (15U)
8961/*! dll_off_mode - Set to 1 when the DDRC and DRAM has to be put in DLL-off mode for low frequency
8962 * operation. Set to 0 to put DDRC and DRAM in DLL-on mode for normal frequency operation. If DDR4
8963 * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), dll_off_mode is not
8964 * supported, and this bit must be set to '0'.
8965 */
8966#define DDRC_MSTR_dll_off_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_dll_off_mode_SHIFT)) & DDRC_MSTR_dll_off_mode_MASK)
8967#define DDRC_MSTR_burst_rdwr_MASK (0xF0000U)
8968#define DDRC_MSTR_burst_rdwr_SHIFT (16U)
8969/*! burst_rdwr - SDRAM burst length used
8970 * 0b0001..Burst length of 2 (only supported for mDDR)
8971 * 0b0010..Burst length of 4
8972 * 0b0100..Burst length of 8
8973 * 0b1000..Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4)
8974 */
8975#define DDRC_MSTR_burst_rdwr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_burst_rdwr_SHIFT)) & DDRC_MSTR_burst_rdwr_MASK)
8976#define DDRC_MSTR_frequency_ratio_MASK (0x400000U)
8977#define DDRC_MSTR_frequency_ratio_SHIFT (22U)
8978/*! frequency_ratio - Selects the Frequency Ratio
8979 * 0b0..1:2 Mode
8980 * 0b1..1:1 Mode
8981 */
8982#define DDRC_MSTR_frequency_ratio(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_frequency_ratio_SHIFT)) & DDRC_MSTR_frequency_ratio_MASK)
8983#define DDRC_MSTR_active_ranks_MASK (0x3000000U)
8984#define DDRC_MSTR_active_ranks_SHIFT (24U)
8985/*! active_ranks - Only present for multi-rank configurations. Each bit represents one rank. For
8986 * two-rank configurations, only bits[25:24] are present.
8987 */
8988#define DDRC_MSTR_active_ranks(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_active_ranks_SHIFT)) & DDRC_MSTR_active_ranks_MASK)
8989#define DDRC_MSTR_frequency_mode_MASK (0x20000000U)
8990#define DDRC_MSTR_frequency_mode_SHIFT (29U)
8991/*! frequency_mode - Choose which registers are used.
8992 * 0b0..Original Registers
8993 * 0b1..Shadow Registers
8994 */
8995#define DDRC_MSTR_frequency_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_frequency_mode_SHIFT)) & DDRC_MSTR_frequency_mode_MASK)
8996#define DDRC_MSTR_device_config_MASK (0xC0000000U)
8997#define DDRC_MSTR_device_config_SHIFT (30U)
8998/*! device_config - Indicates the configuration of the device used in the system.
8999 * 0b00..x4 device
9000 * 0b01..x8 device
9001 * 0b10..x16 device
9002 * 0b11..x32 device
9003 */
9004#define DDRC_MSTR_device_config(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR_device_config_SHIFT)) & DDRC_MSTR_device_config_MASK)
9005/*! @} */
9006
9007/*! @name STAT - Operating Mode Status Register */
9008/*! @{ */
9009#define DDRC_STAT_operating_mode_MASK (0x7U)
9010#define DDRC_STAT_operating_mode_SHIFT (0U)
9011/*! operating_mode - Operating mode
9012 */
9013#define DDRC_STAT_operating_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_operating_mode_SHIFT)) & DDRC_STAT_operating_mode_MASK)
9014#define DDRC_STAT_selfref_type_MASK (0x30U)
9015#define DDRC_STAT_selfref_type_SHIFT (4U)
9016/*! selfref_type - Flags if Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if
9017 * it was under Automatic Self Refresh control only or not.
9018 * 0b00..SDRAM is not in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by
9019 * CRCPARCTRL1.crc_parity_retry_enable, this also indicates SRE command is still in parity error window or retry is
9020 * in-progress.
9021 * 0b11..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was caused by Automatic Self
9022 * Refresh only. If retry is enabled, this guarantees SRE command is executed correctly without parity error.
9023 * 0b10..SDRAM is in Self Refresh (except LPDDR4) or SR-Powerdown (LPDDR4), which was not caused solely under
9024 * Automatic Self Refresh control. It could have been caused by Hardware Low Power Interface and/or Software
9025 * (reg_ddrc_selfref_sw). If retry is enabled, this guarantees SRE command is executed correctly without parity
9026 */
9027#define DDRC_STAT_selfref_type(x) (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_selfref_type_SHIFT)) & DDRC_STAT_selfref_type_MASK)
9028#define DDRC_STAT_selfref_state_MASK (0x300U)
9029#define DDRC_STAT_selfref_state_SHIFT (8U)
9030/*! selfref_state - Self refresh state. This indicates self refresh or self refresh power down state
9031 * for LPDDR4. This register is used for frequency change and MRR/MRW access during self refresh.
9032 * 0b00..SDRAM is not in Self Refresh.
9033 * 0b01..Self refresh 1
9034 * 0b10..Self refresh power down
9035 * 0b11..Self refresh
9036 */
9037#define DDRC_STAT_selfref_state(x) (((uint32_t)(((uint32_t)(x)) << DDRC_STAT_selfref_state_SHIFT)) & DDRC_STAT_selfref_state_MASK)
9038/*! @} */
9039
9040/*! @name MSTR1 - Operating Mode Status Register */
9041/*! @{ */
9042#define DDRC_MSTR1_rank_tmgreg_sel_MASK (0x3U)
9043#define DDRC_MSTR1_rank_tmgreg_sel_SHIFT (0U)
9044/*! rank_tmgreg_sel - rank_tmgreg_sel
9045 * 0b00..USE DRAMTMGx registers for the rank
9046 * 0b01..USE MRAMTMGx registers for the rank
9047 */
9048#define DDRC_MSTR1_rank_tmgreg_sel(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR1_rank_tmgreg_sel_SHIFT)) & DDRC_MSTR1_rank_tmgreg_sel_MASK)
9049#define DDRC_MSTR1_alt_addrmap_en_MASK (0x10000U)
9050#define DDRC_MSTR1_alt_addrmap_en_SHIFT (16U)
9051/*! alt_addrmap_en - Enable Alternative Address Map
9052 * 0b0..Disable Alternative Address Map
9053 * 0b1..Enable Alternative Address Map
9054 */
9055#define DDRC_MSTR1_alt_addrmap_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MSTR1_alt_addrmap_en_SHIFT)) & DDRC_MSTR1_alt_addrmap_en_MASK)
9056/*! @} */
9057
9058/*! @name MRCTRL3 - Operating Mode Status Register */
9059/*! @{ */
9060#define DDRC_MRCTRL3_mr_rank_sel_MASK (0x3U)
9061#define DDRC_MRCTRL3_mr_rank_sel_SHIFT (0U)
9062/*! mr_rank_sel - mr_rank_sel
9063 */
9064#define DDRC_MRCTRL3_mr_rank_sel(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL3_mr_rank_sel_SHIFT)) & DDRC_MRCTRL3_mr_rank_sel_MASK)
9065/*! @} */
9066
9067/*! @name MRCTRL0 - Mode Register Read/Write Control Register 0. */
9068/*! @{ */
9069#define DDRC_MRCTRL0_mr_type_MASK (0x1U)
9070#define DDRC_MRCTRL0_mr_type_SHIFT (0U)
9071/*! mr_type - Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4.
9072 * 0b0..Write
9073 * 0b1..Read
9074 */
9075#define DDRC_MRCTRL0_mr_type(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_type_SHIFT)) & DDRC_MRCTRL0_mr_type_MASK)
9076#define DDRC_MRCTRL0_mpr_en_MASK (0x2U)
9077#define DDRC_MRCTRL0_mpr_en_SHIFT (1U)
9078/*! mpr_en - Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4).
9079 * 0b0..MRS
9080 * 0b1..WR/RD for MPR
9081 */
9082#define DDRC_MRCTRL0_mpr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mpr_en_SHIFT)) & DDRC_MRCTRL0_mpr_en_MASK)
9083#define DDRC_MRCTRL0_pda_en_MASK (0x4U)
9084#define DDRC_MRCTRL0_pda_en_SHIFT (2U)
9085/*! pda_en - Indicates whether the mode register operation is MRS in PDA mode or not. Note that when
9086 * pba_mode=1, PBA access is initiated instead of PDA access.
9087 * 0b0..MRS
9088 * 0b1..MRS in Per DRAM Addressability
9089 */
9090#define DDRC_MRCTRL0_pda_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_pda_en_SHIFT)) & DDRC_MRCTRL0_pda_en_MASK)
9091#define DDRC_MRCTRL0_sw_init_int_MASK (0x8U)
9092#define DDRC_MRCTRL0_sw_init_int_SHIFT (3U)
9093/*! sw_init_int - Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before
9094 * automatic SDRAM initialization routine or not. For DDR4, this bit can be used to initialize the
9095 * DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit can be used to
9096 * program additional mode registers before automatic SDRAM initialization if necessary. In LPDDR4
9097 * independent channel mode, note that this must be programmed to both channels beforehand. Note that
9098 * this must be cleared to 0 after completing Software operation. Otherwise, SDRAM
9099 * initialization routine will not re-start.
9100 * 0b0..Software intervention is not allowed
9101 * 0b1..Software intervention is allowed
9102 */
9103#define DDRC_MRCTRL0_sw_init_int(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_sw_init_int_SHIFT)) & DDRC_MRCTRL0_sw_init_int_MASK)
9104#define DDRC_MRCTRL0_mr_rank_MASK (0x30U)
9105#define DDRC_MRCTRL0_mr_rank_SHIFT (4U)
9106/*! mr_rank - Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access
9107 * all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which
9108 * implement address mirroring, it may be necessary to access ranks individually. Examples (assume
9109 * DDRC is configured for 4 ranks): 0x1 - select rank 0 only 0x2 - select rank 1 only 0x5 -
9110 * select ranks 0 and 2 0xA - select ranks 1 and 3 0xF - select ranks 0, 1, 2 and 3
9111 */
9112#define DDRC_MRCTRL0_mr_rank(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_rank_SHIFT)) & DDRC_MRCTRL0_mr_rank_MASK)
9113#define DDRC_MRCTRL0_mr_addr_MASK (0xF000U)
9114#define DDRC_MRCTRL0_mr_addr_SHIFT (12U)
9115/*! mr_addr - Address of the mode register that is to be written to.
9116 * 0b0000..MR0
9117 * 0b0001..MR1
9118 * 0b0010..MR2
9119 * 0b0011..MR3
9120 * 0b0100..MR4
9121 * 0b0101..MR5
9122 * 0b0110..MR6
9123 * 0b0111..MR7
9124 */
9125#define DDRC_MRCTRL0_mr_addr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_addr_SHIFT)) & DDRC_MRCTRL0_mr_addr_MASK)
9126#define DDRC_MRCTRL0_pba_mode_MASK (0x40000000U)
9127#define DDRC_MRCTRL0_pba_mode_SHIFT (30U)
9128/*! pba_mode - Indicates whether PBA access is executed. When setting this bit to 1 along with
9129 * setting pda_en to 1, DDRC initiates PBA access instead of PDA access. - 0 - Per DRAM Addressability
9130 * mode - 1 - Per Buffer Addressability mode The completion of PBA access is confirmed by
9131 * MRSTAT.pda_done in the same way as PDA.
9132 */
9133#define DDRC_MRCTRL0_pba_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_pba_mode_SHIFT)) & DDRC_MRCTRL0_pba_mode_MASK)
9134#define DDRC_MRCTRL0_mr_wr_MASK (0x80000000U)
9135#define DDRC_MRCTRL0_mr_wr_SHIFT (31U)
9136/*! mr_wr - Setting this register bit to 1 triggers a mode register read or write operation. When
9137 * the MR operation is complete, the DDRC automatically clears this bit. The other register fields
9138 * of this register must be written in a separate APB transaction, before setting this mr_wr bit.
9139 * It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.
9140 */
9141#define DDRC_MRCTRL0_mr_wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL0_mr_wr_SHIFT)) & DDRC_MRCTRL0_mr_wr_MASK)
9142/*! @} */
9143
9144/*! @name MRCTRL1 - Mode Register Read/Write Control Register 1 */
9145/*! @{ */
9146#define DDRC_MRCTRL1_mr_data_MASK (0x3FFFFU)
9147#define DDRC_MRCTRL1_mr_data_SHIFT (0U)
9148/*! mr_data - Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. For
9149 * LPDDR2/LPDDR3/LPDDR4, MRCTRL1[15:0] are interpreted as [15:8] MR Address [7:0] MR data for writes,
9150 * don't care for reads. This is 18-bits wide in configurations with DDR4 support and 16-bits in all
9151 * other configurations.
9152 */
9153#define DDRC_MRCTRL1_mr_data(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL1_mr_data_SHIFT)) & DDRC_MRCTRL1_mr_data_MASK)
9154/*! @} */
9155
9156/*! @name MRSTAT - Mode Register Read/Write Status Register */
9157/*! @{ */
9158#define DDRC_MRSTAT_mr_wr_busy_MASK (0x1U)
9159#define DDRC_MRSTAT_mr_wr_busy_SHIFT (0U)
9160/*! mr_wr_busy - The SoC core may initiate a MR write operation only if this signal is low. This
9161 * signal goes high in the clock after the DDRC accepts the MRW/MRR request. It goes low when the
9162 * MRW/MRR command is issued to the SDRAM. It is recommended not to perform MRW/MRR commands when
9163 * 'MRSTAT.mr_wr_busy' is high.
9164 * 0b0..Indicates that the SoC core can initiate a mode register write operation
9165 * 0b1..Indicates that mode register write operation is in progress
9166 */
9167#define DDRC_MRSTAT_mr_wr_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_mr_wr_busy_SHIFT)) & DDRC_MRSTAT_mr_wr_busy_MASK)
9168#define DDRC_MRSTAT_pda_done_MASK (0x100U)
9169#define DDRC_MRSTAT_pda_done_SHIFT (8U)
9170/*! pda_done - The SoC core may initiate a MR write operation in PDA/PBA mode only if this signal is
9171 * low. This signal goes high when three consecutive MRS commands related to the PDA/PBA mode
9172 * are issued to the SDRAM. This signal goes low when MRCTRL0.pda_en becomes 0. Therefore, it is
9173 * recommended to write MRCTRL0.pda_en to 0 after this signal goes high in order to prepare to
9174 * perform PDA operation next time
9175 * 0b0..Indicates that mode register write operation related to PDA/PBA is in progress or has not started yet.
9176 * 0b1..Indicates that mode register write operation related to PDA/PBA has competed.
9177 */
9178#define DDRC_MRSTAT_pda_done(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRSTAT_pda_done_SHIFT)) & DDRC_MRSTAT_pda_done_MASK)
9179/*! @} */
9180
9181/*! @name MRCTRL2 - Mode Register Read/Write Control Register 2 */
9182/*! @{ */
9183#define DDRC_MRCTRL2_mr_device_sel_MASK (0xFFFFFFFFU)
9184#define DDRC_MRCTRL2_mr_device_sel_SHIFT (0U)
9185/*! mr_device_sel - Indicates the device(s) to be selected during the MRS that happens in PDA mode.
9186 * Each bit is associated with one device. For example, bit[0] corresponds to Device 0, bit[1] to
9187 * Device 1 etc. A '1' should be programmed to indicate that the MRS command should be applied
9188 * to that device. A '0' indicates that the MRS commands should be skipped for that device.
9189 */
9190#define DDRC_MRCTRL2_mr_device_sel(x) (((uint32_t)(((uint32_t)(x)) << DDRC_MRCTRL2_mr_device_sel_SHIFT)) & DDRC_MRCTRL2_mr_device_sel_MASK)
9191/*! @} */
9192
9193/*! @name DERATEEN - Temperature Derate Enable Register */
9194/*! @{ */
9195#define DDRC_DERATEEN_derate_enable_MASK (0x1U)
9196#define DDRC_DERATEEN_derate_enable_SHIFT (0U)
9197/*! derate_enable - Enables derating. Present only in designs configured to support
9198 * LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
9199 * 0b0..Timing parameter derating is disabled
9200 * 0b1..Timing parameter derating is enabled using MR4 read value.
9201 */
9202#define DDRC_DERATEEN_derate_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_enable_SHIFT)) & DDRC_DERATEEN_derate_enable_MASK)
9203#define DDRC_DERATEEN_derate_value_MASK (0x2U)
9204#define DDRC_DERATEEN_derate_value_SHIFT (1U)
9205/*! derate_value - Derate value. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
9206 * Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a
9207 * core_ddrc_core_clk period. For LPDDR3/4, if the period of core_ddrc_core_clk is less than 1.875ns, this
9208 * register field should be set to 1; otherwise it should be set to 0.
9209 * 0b0..Derating uses +1
9210 * 0b1..Derating uses +2
9211 */
9212#define DDRC_DERATEEN_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_value_SHIFT)) & DDRC_DERATEEN_derate_value_MASK)
9213#define DDRC_DERATEEN_derate_byte_MASK (0xF0U)
9214#define DDRC_DERATEEN_derate_byte_SHIFT (4U)
9215/*! derate_byte - Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
9216 * Indicates which byte of the MRR data is used for derating. The maximum valid value depends on
9217 * MEMC_DRAM_TOTAL_DATA_WIDTH.
9218 */
9219#define DDRC_DERATEEN_derate_byte(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_derate_byte_SHIFT)) & DDRC_DERATEEN_derate_byte_MASK)
9220#define DDRC_DERATEEN_rc_derate_value_MASK (0x300U)
9221#define DDRC_DERATEEN_rc_derate_value_SHIFT (8U)
9222/*! rc_derate_value - Derate value of tRC for LPDDR4. Present only in designs configured to support
9223 * LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by the
9224 * core_ddrc_core_clk period, and rounding up the next integer.
9225 * 0b00..Derating uses +1
9226 * 0b01..Derating uses +2
9227 * 0b10..Derating uses +3
9228 * 0b11..Derating uses +4
9229 */
9230#define DDRC_DERATEEN_rc_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_rc_derate_value_SHIFT)) & DDRC_DERATEEN_rc_derate_value_MASK)
9231/*! @} */
9232
9233/*! @name DERATEINT - Temperature Derate Interval Register */
9234/*! @{ */
9235#define DDRC_DERATEINT_mr4_read_interval_MASK (0xFFFFFFFFU)
9236#define DDRC_DERATEINT_mr4_read_interval_SHIFT (0U)
9237/*! mr4_read_interval - Interval between two MR4 reads, used to derate the timing parameters.
9238 * Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to
9239 * zero. Unit: DFI clock cycle.
9240 */
9241#define DDRC_DERATEINT_mr4_read_interval(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEINT_mr4_read_interval_SHIFT)) & DDRC_DERATEINT_mr4_read_interval_MASK)
9242/*! @} */
9243
9244/*! @name PWRCTL - Low Power Control Register */
9245/*! @{ */
9246#define DDRC_PWRCTL_selfref_en_MASK (0x1U)
9247#define DDRC_PWRCTL_selfref_en_SHIFT (0U)
9248/*! selfref_en - If true then the DDRC puts the SDRAM into Self Refresh after a programmable number
9249 * of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit
9250 * may be re-programmed during the course of normal operation.
9251 */
9252#define DDRC_PWRCTL_selfref_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_selfref_en_SHIFT)) & DDRC_PWRCTL_selfref_en_MASK)
9253#define DDRC_PWRCTL_powerdown_en_MASK (0x2U)
9254#define DDRC_PWRCTL_powerdown_en_SHIFT (1U)
9255/*! powerdown_en - If true then the DDRC goes into power-down after a programmable number of cycles
9256 * "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32). This register bit may be
9257 * re-programmed during the course of normal operation.
9258 */
9259#define DDRC_PWRCTL_powerdown_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_powerdown_en_SHIFT)) & DDRC_PWRCTL_powerdown_en_MASK)
9260#define DDRC_PWRCTL_deeppowerdown_en_MASK (0x4U)
9261#define DDRC_PWRCTL_deeppowerdown_en_SHIFT (2U)
9262/*! deeppowerdown_en - When this is 1, DDRC puts the SDRAM into deep power-down mode when the
9263 * transaction store is empty. This register must be reset to '0' to bring DDRC out of deep power-down
9264 * mode. Controller performs automatic SDRAM initialization on deep power-down exit. Present only
9265 * in designs configured to support mDDR or LPDDR2 or LPDDR3. For
9266 * non-mDDR/non-LPDDR2/non-LPDDR3, this register should not be set to 1. FOR PERFORMANCE ONLY.
9267 */
9268#define DDRC_PWRCTL_deeppowerdown_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_deeppowerdown_en_SHIFT)) & DDRC_PWRCTL_deeppowerdown_en_MASK)
9269#define DDRC_PWRCTL_en_dfi_dram_clk_disable_MASK (0x8U)
9270#define DDRC_PWRCTL_en_dfi_dram_clk_disable_SHIFT (3U)
9271/*! en_dfi_dram_clk_disable - Enable the assertion of dfi_dram_clk_disable whenever a clock is not
9272 * required by the SDRAM. If set to 0, dfi_dram_clk_disable is never asserted. Assertion of
9273 * dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DDR4, can
9274 * be asserted in following: in Self Refresh in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3,
9275 * can be asserted in following: in Self Refresh in Power Down in Deep Power Down during Normal
9276 * operation (Clock Stop) In LPDDR4, can be asserted in following: in Self Refresh Power Down in
9277 * Power Down during Normal operation (Clock Stop)
9278 */
9279#define DDRC_PWRCTL_en_dfi_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_en_dfi_dram_clk_disable_SHIFT)) & DDRC_PWRCTL_en_dfi_dram_clk_disable_MASK)
9280#define DDRC_PWRCTL_mpsm_en_MASK (0x10U)
9281#define DDRC_PWRCTL_mpsm_en_SHIFT (4U)
9282/*! mpsm_en - When this is 1, the DDRC puts the SDRAM into maximum power saving mode when the
9283 * transaction store is empty. This register must be reset to '0' to bring DDRC out of maximum power
9284 * saving mode. Present only in designs configured to support DDR4. For non-DDR4, this register
9285 * should not be set to 1. Note that MPSM is not supported when using a DDR PHY, if the PHY
9286 * parameter DDRC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to
9287 * toggle. FOR PERFORMANCE ONLY.
9288 */
9289#define DDRC_PWRCTL_mpsm_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_mpsm_en_SHIFT)) & DDRC_PWRCTL_mpsm_en_MASK)
9290#define DDRC_PWRCTL_selfref_sw_MASK (0x20U)
9291#define DDRC_PWRCTL_selfref_sw_SHIFT (5U)
9292/*! selfref_sw - A value of 1 to this register causes system to move to Self Refresh state
9293 * immediately, as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software
9294 * Entry/Exit to Self Refresh.
9295 * 0b0..Software Exit from Self Refresh
9296 * 0b1..Software Entry to Self Refresh
9297 */
9298#define DDRC_PWRCTL_selfref_sw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_selfref_sw_SHIFT)) & DDRC_PWRCTL_selfref_sw_MASK)
9299#define DDRC_PWRCTL_stay_in_selfref_MASK (0x40U)
9300#define DDRC_PWRCTL_stay_in_selfref_SHIFT (6U)
9301/*! stay_in_selfref - Self refresh state is an intermediate state to enter to Self refresh power
9302 * down state or exit Self refresh power down state for LPDDR4. This register controls transition
9303 * from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 0 - Allow
9304 * transition from Self refresh state
9305 * 0b0..
9306 * 0b1..
9307 */
9308#define DDRC_PWRCTL_stay_in_selfref(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRCTL_stay_in_selfref_SHIFT)) & DDRC_PWRCTL_stay_in_selfref_MASK)
9309/*! @} */
9310
9311/*! @name PWRTMG - Low Power Timing Register */
9312/*! @{ */
9313#define DDRC_PWRTMG_powerdown_to_x32_MASK (0x1FU)
9314#define DDRC_PWRTMG_powerdown_to_x32_SHIFT (0U)
9315/*! powerdown_to_x32 - After this many clocks of the DDRC command channel being idle the DDRC
9316 * automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there
9317 * are no HIF commands outstanding. This must be enabled in the PWRCTL.powerdown_en. Unit:
9318 * Multiples of 32 DFI clocks FOR PERFORMANCE ONLY.
9319 */
9320#define DDRC_PWRTMG_powerdown_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_powerdown_to_x32_SHIFT)) & DDRC_PWRTMG_powerdown_to_x32_MASK)
9321#define DDRC_PWRTMG_t_dpd_x4096_MASK (0xFF00U)
9322#define DDRC_PWRTMG_t_dpd_x4096_SHIFT (8U)
9323/*! t_dpd_x4096 - Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as
9324 * mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is
9325 * de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Multiples of 4096 DFI
9326 * clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE
9327 * ONLY.
9328 */
9329#define DDRC_PWRTMG_t_dpd_x4096(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_t_dpd_x4096_SHIFT)) & DDRC_PWRTMG_t_dpd_x4096_MASK)
9330#define DDRC_PWRTMG_selfref_to_x32_MASK (0xFF0000U)
9331#define DDRC_PWRTMG_selfref_to_x32_SHIFT (16U)
9332/*! selfref_to_x32 - After this many clocks of the DDRC command channel being idle the DDRC
9333 * automatically puts the SDRAM into Self Refresh. The DDRC command channel is considered idle when there
9334 * are no HIF commands outstanding. This must be enabled in the PWRCTL.selfref_en. Unit:
9335 * Multiples of 32 DFI clocks. FOR PERFORMANCE ONLY.
9336 */
9337#define DDRC_PWRTMG_selfref_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PWRTMG_selfref_to_x32_SHIFT)) & DDRC_PWRTMG_selfref_to_x32_MASK)
9338/*! @} */
9339
9340/*! @name HWLPCTL - Hardware Low Power Control Register */
9341/*! @{ */
9342#define DDRC_HWLPCTL_hw_lp_en_MASK (0x1U)
9343#define DDRC_HWLPCTL_hw_lp_en_SHIFT (0U)
9344/*! hw_lp_en - Enable for Hardware Low Power Interface.
9345 */
9346#define DDRC_HWLPCTL_hw_lp_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_en_SHIFT)) & DDRC_HWLPCTL_hw_lp_en_MASK)
9347#define DDRC_HWLPCTL_hw_lp_exit_idle_en_MASK (0x2U)
9348#define DDRC_HWLPCTL_hw_lp_exit_idle_en_SHIFT (1U)
9349/*! hw_lp_exit_idle_en - When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be
9350 * used to exit from the automatic clock stop, automatic power down or automatic self-refresh
9351 * modes. Note, it will not cause exit of Self-Refresh that was caused by Hardware Low Power
9352 * Interface and/or Software (PWRCTL.selfref_sw).
9353 */
9354#define DDRC_HWLPCTL_hw_lp_exit_idle_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_exit_idle_en_SHIFT)) & DDRC_HWLPCTL_hw_lp_exit_idle_en_MASK)
9355#define DDRC_HWLPCTL_hw_lp_idle_x32_MASK (0xFFF0000U)
9356#define DDRC_HWLPCTL_hw_lp_idle_x32_SHIFT (16U)
9357/*! hw_lp_idle_x32 - Hardware idle period. The cactive_ddrc output is driven low if the DDRC command
9358 * channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The
9359 * DDRC command channel is considered idle when there are no HIF commands outstanding. The hardware
9360 * idle function is disabled when hw_lp_idle_x32=0. Unit: Multiples of 32 DFI clocks. FOR
9361 * PERFORMANCE ONLY.
9362 */
9363#define DDRC_HWLPCTL_hw_lp_idle_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_HWLPCTL_hw_lp_idle_x32_SHIFT)) & DDRC_HWLPCTL_hw_lp_idle_x32_MASK)
9364/*! @} */
9365
9366/*! @name RFSHCTL0 - Refresh Control Register 0 */
9367/*! @{ */
9368#define DDRC_RFSHCTL0_per_bank_refresh_MASK (0x4U)
9369#define DDRC_RFSHCTL0_per_bank_refresh_SHIFT (2U)
9370/*! per_bank_refresh - Per bank refresh allows traffic to flow to other banks. Per bank refresh is
9371 * not supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices.
9372 * Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
9373 * 0b1..Per bank refresh
9374 * 0b0..All bank refresh
9375 */
9376#define DDRC_RFSHCTL0_per_bank_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_per_bank_refresh_SHIFT)) & DDRC_RFSHCTL0_per_bank_refresh_MASK)
9377#define DDRC_RFSHCTL0_refresh_burst_MASK (0x1F0U)
9378#define DDRC_RFSHCTL0_refresh_burst_SHIFT (4U)
9379/*! refresh_burst - The programmed value + 1 is the number of refresh timeouts that is allowed to
9380 * accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to
9381 * perform a refresh is a one-time penalty that must be paid for each group of refreshes.
9382 * Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings.
9383 * Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases
9384 * the worst-case latency associated with refreshes. - 0 - single refresh - 1 - burst-of-2
9385 * refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to section 3.9 of
9386 * DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not
9387 * per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh
9388 * feature. In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X
9389 * mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care
9390 * must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated
9391 * due to a PHY-initiated update occurring shortly before a refresh burst was due. In this
9392 * situation, the refresh burst will be delayed until the PHY-initiated update is complete.
9393 */
9394#define DDRC_RFSHCTL0_refresh_burst(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_burst_SHIFT)) & DDRC_RFSHCTL0_refresh_burst_MASK)
9395#define DDRC_RFSHCTL0_refresh_to_x32_MASK (0x1F000U)
9396#define DDRC_RFSHCTL0_refresh_to_x32_SHIFT (12U)
9397/*! refresh_to_x32 - If the refresh timer (tRFCnom, also known as tREFI) has expired at least once,
9398 * but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be
9399 * performed. A speculative refresh is a refresh performed at a time when refresh would be
9400 * useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time
9401 * determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since
9402 * the last refresh, then a speculative refresh is performed. Speculative refreshes continues
9403 * successively until there are no refreshes pending or until new reads or writes are issued to the
9404 * DDRC. FOR PERFORMANCE ONLY. Unit: Multiples of 32 DFI clocks.
9405 */
9406#define DDRC_RFSHCTL0_refresh_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_to_x32_SHIFT)) & DDRC_RFSHCTL0_refresh_to_x32_MASK)
9407#define DDRC_RFSHCTL0_refresh_margin_MASK (0xF00000U)
9408#define DDRC_RFSHCTL0_refresh_margin_SHIFT (20U)
9409/*! refresh_margin - Threshold value in number of DFI clock cycles before the critical refresh or
9410 * page timer expires. A critical refresh is to be issued before this threshold is reached. It is
9411 * recommended that this not be changed from the default value, currently shown as 0x2. It must
9412 * always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4,
9413 * internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled
9414 * (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to
9415 * RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 DFI clocks.
9416 */
9417#define DDRC_RFSHCTL0_refresh_margin(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_refresh_margin_SHIFT)) & DDRC_RFSHCTL0_refresh_margin_MASK)
9418/*! @} */
9419
9420/*! @name RFSHCTL1 - Refresh Control Register 1 */
9421/*! @{ */
9422#define DDRC_RFSHCTL1_refresh_timer0_start_value_x32_MASK (0xFFFU)
9423#define DDRC_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT (0U)
9424/*! refresh_timer0_start_value_x32 - Refresh timer start for rank 0 (only present in multi-rank
9425 * configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to
9426 * proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples
9427 * of 32 DFI clock cycles. FOR PERFORMANCE ONLY.
9428 */
9429#define DDRC_RFSHCTL1_refresh_timer0_start_value_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_refresh_timer0_start_value_x32_SHIFT)) & DDRC_RFSHCTL1_refresh_timer0_start_value_x32_MASK)
9430#define DDRC_RFSHCTL1_refresh_timer1_start_value_x32_MASK (0xFFF0000U)
9431#define DDRC_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT (16U)
9432/*! refresh_timer1_start_value_x32 - Refresh timer start for rank 1 (only present in multi-rank
9433 * configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to
9434 * proceed. This is explained in Refresh Controls section of architecture chapter. Unit: Multiples
9435 * of 32 DFI clock cycles. FOR PERFORMANCE ONLY.
9436 */
9437#define DDRC_RFSHCTL1_refresh_timer1_start_value_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL1_refresh_timer1_start_value_x32_SHIFT)) & DDRC_RFSHCTL1_refresh_timer1_start_value_x32_MASK)
9438/*! @} */
9439
9440/*! @name RFSHCTL3 - Refresh Control Register 3 */
9441/*! @{ */
9442#define DDRC_RFSHCTL3_dis_auto_refresh_MASK (0x1U)
9443#define DDRC_RFSHCTL3_dis_auto_refresh_SHIFT (0U)
9444/*! dis_auto_refresh - When '1', disable auto-refresh generated by the DDRC. When auto-refresh is
9445 * disabled, the SoC core must generate refreshes using the registers reg_ddrc_rank0_refresh,
9446 * reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis_auto_refresh
9447 * transitions from 0 to 1, any pending refreshes are immediately scheduled by the DDRC. If DDR4
9448 * CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is
9449 * not supported, and this bit must be set to '0'. (DDR4 only) If FGR mode is enabled
9450 * (RFSHCTL3.refresh_mode > 0), disable auto-refresh is not supported, and this bit must be set to '0'. This
9451 * register field is changeable on the fly.
9452 */
9453#define DDRC_RFSHCTL3_dis_auto_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_dis_auto_refresh_SHIFT)) & DDRC_RFSHCTL3_dis_auto_refresh_MASK)
9454#define DDRC_RFSHCTL3_refresh_update_level_MASK (0x2U)
9455#define DDRC_RFSHCTL3_refresh_update_level_SHIFT (1U)
9456/*! refresh_update_level - Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that
9457 * the refresh register(s) have been updated. refresh_update_level must not be toggled when the
9458 * DDRC is in reset (core_ddrc_rstn = 0). The refresh register(s) are automatically updated when
9459 * exiting reset.
9460 */
9461#define DDRC_RFSHCTL3_refresh_update_level(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_refresh_update_level_SHIFT)) & DDRC_RFSHCTL3_refresh_update_level_MASK)
9462#define DDRC_RFSHCTL3_refresh_mode_MASK (0x70U)
9463#define DDRC_RFSHCTL3_refresh_mode_SHIFT (4U)
9464/*! refresh_mode - Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x -
9465 * 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 110 - Enable on the fly 4x (not
9466 * supported) - Everything else - reserved Note: Only Fixed 1x mode is supported if
9467 * RFSHCTL3.dis_auto_refresh = 1. Note: The on-the-fly modes are not supported in this version of the DDRC.
9468 * Note: This must be set up while the Controller is in reset or while the Controller is in
9469 * self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic
9470 * register will be supported in future version of the DDRC. Note: This register field has effect only
9471 * if a DDR4 SDRAM device is in use (MSTR.ddr4 = 1).
9472 */
9473#define DDRC_RFSHCTL3_refresh_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL3_refresh_mode_SHIFT)) & DDRC_RFSHCTL3_refresh_mode_MASK)
9474/*! @} */
9475
9476/*! @name RFSHTMG - Refresh Timing Register */
9477/*! @{ */
9478#define DDRC_RFSHTMG_t_rfc_min_MASK (0x3FFU)
9479#define DDRC_RFSHTMG_t_rfc_min_SHIFT (0U)
9480/*! t_rfc_min - tRFC (min): Minimum time from refresh to refresh or activate. When the controller is
9481 * operating in 1:1 mode, t_rfc_min should be set to RoundUp(tRFCmin/tCK). When the controller
9482 * is operating in 1:2 mode, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In
9483 * LPDDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations
9484 * is equal to tRFCab - if using per-bank refreshes, the tRFCmin value in the above equations is
9485 * equal to tRFCpb In DDR4 mode, the tRFCmin value in the above equations is different depending
9486 * on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the
9487 * appropriate value from the spec based on the 'refresh_mode' and the device density that is used.
9488 * Unit: Clocks.
9489 */
9490#define DDRC_RFSHTMG_t_rfc_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_t_rfc_min_SHIFT)) & DDRC_RFSHTMG_t_rfc_min_MASK)
9491#define DDRC_RFSHTMG_lpddr3_trefbw_en_MASK (0x8000U)
9492#define DDRC_RFSHTMG_lpddr3_trefbw_en_SHIFT (15U)
9493/*! lpddr3_trefbw_en - Used only when LPDDR3 memory type is connected. Should only be changed when
9494 * DDRC is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3
9495 * devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: - 0 - tREFBW
9496 * parameter not used - 1 - tREFBW parameter used
9497 */
9498#define DDRC_RFSHTMG_lpddr3_trefbw_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_lpddr3_trefbw_en_SHIFT)) & DDRC_RFSHTMG_lpddr3_trefbw_en_MASK)
9499#define DDRC_RFSHTMG_t_rfc_nom_x32_MASK (0xFFF0000U)
9500#define DDRC_RFSHTMG_t_rfc_nom_x32_SHIFT (16U)
9501/*! t_rfc_nom_x32 - tREFI: Average time interval between refreshes per rank (Specification: 7.8us
9502 * for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). For
9503 * LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register
9504 * should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this
9505 * register should be set to tREFIpb When the controller is operating in 1:2 frequency ratio mode,
9506 * program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI value is different depending
9507 * on the refresh mode. The user should program the appropriate value from the spec based on the
9508 * value programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be
9509 * greater than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater than 0x1. - Non-DDR4 or
9510 * DDR4 Fixed 1x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0xFFE. - DDR4 Fixed
9511 * 2x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x7FF. - DDR4 Fixed 4x mode:
9512 * RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x3FF. Unit: Multiples of 32 clocks.
9513 */
9514#define DDRC_RFSHTMG_t_rfc_nom_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_t_rfc_nom_x32_SHIFT)) & DDRC_RFSHTMG_t_rfc_nom_x32_MASK)
9515/*! @} */
9516
9517/*! @name INIT0 - SDRAM Initialization Register 0 */
9518/*! @{ */
9519#define DDRC_INIT0_pre_cke_x1024_MASK (0xFFFU)
9520#define DDRC_INIT0_pre_cke_x1024_SHIFT (0U)
9521/*! pre_cke_x1024 - Cycles to wait after reset before driving CKE high to start the SDRAM
9522 * initialization sequence. Unit: 1024 DFI clock cycles. DDR2 specifications typically require this to be
9523 * programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4: tINIT3 of 2
9524 * ms (min) When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC
9525 * spec value divided by 2, and round it up to the next integer value. For DDR3/DDR4 RDIMMs, this
9526 * should include the time needed to satisfy tSTAB
9527 */
9528#define DDRC_INIT0_pre_cke_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_pre_cke_x1024_SHIFT)) & DDRC_INIT0_pre_cke_x1024_MASK)
9529#define DDRC_INIT0_post_cke_x1024_MASK (0x3FF0000U)
9530#define DDRC_INIT0_post_cke_x1024_SHIFT (16U)
9531/*! post_cke_x1024 - Cycles to wait after driving CKE high to start the SDRAM initialization
9532 * sequence. Unit: 1024 DFI clock cycles. DDR2 typically requires a 400 ns delay, requiring this value
9533 * to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be
9534 * programmed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us.
9535 * When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec
9536 * value divided by 2, and round it up to the next integer value.
9537 */
9538#define DDRC_INIT0_post_cke_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_post_cke_x1024_SHIFT)) & DDRC_INIT0_post_cke_x1024_MASK)
9539#define DDRC_INIT0_skip_dram_init_MASK (0xC0000000U)
9540#define DDRC_INIT0_skip_dram_init_SHIFT (30U)
9541/*! skip_dram_init - If lower bit is enabled the SDRAM initialization routine is skipped. The upper
9542 * bit decides what state the controller starts up in when reset is removed - 00 - SDRAM
9543 * Intialization routine is run after power-up - 01 - SDRAM Initialization routine is skipped after
9544 * power-up. Controller starts up in Normal Mode - 11 - SDRAM Initialization routine is skipped after
9545 * power-up. Controller starts up in Self-refresh Mode - 10 - SDRAM Initialization routine is run
9546 * after power-up.
9547 * 0b00..SDRAM Initialization routine is run after power-up
9548 * 0b01..SDRAM Initialization routine is skipped after power-up
9549 * 0b10..SDRAM Initialization routine is run after power-up
9550 * 0b11..SDRAM Initialization routine is skipped after power-up
9551 */
9552#define DDRC_INIT0_skip_dram_init(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT0_skip_dram_init_SHIFT)) & DDRC_INIT0_skip_dram_init_MASK)
9553/*! @} */
9554
9555/*! @name INIT1 - SDRAM Initialization Register 1 */
9556/*! @{ */
9557#define DDRC_INIT1_pre_ocd_x32_MASK (0xFU)
9558#define DDRC_INIT1_pre_ocd_x32_SHIFT (0U)
9559/*! pre_ocd_x32 - Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a
9560 * global timer that pulses every 32 DFI clock cycles. There is no known specific requirement for
9561 * this; it may be set to zero.
9562 */
9563#define DDRC_INIT1_pre_ocd_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_pre_ocd_x32_SHIFT)) & DDRC_INIT1_pre_ocd_x32_MASK)
9564#define DDRC_INIT1_dram_rstn_x1024_MASK (0x1FF0000U)
9565#define DDRC_INIT1_dram_rstn_x1024_SHIFT (16U)
9566/*! dram_rstn_x1024 - Number of cycles to assert SDRAM reset signal during init sequence. This is
9567 * only present for designs supporting DDR3, DDR4 or LPDDR4 devices. For use with a DDR PHY, this
9568 * should be set to a minimum of 1. When the controller is operating in 1:2 frequency ratio mode,
9569 * program this to JEDEC spec value divided by 2, and round it up to the next integer value.
9570 * Unit: 1024 DFI clock cycles.
9571 */
9572#define DDRC_INIT1_dram_rstn_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT1_dram_rstn_x1024_SHIFT)) & DDRC_INIT1_dram_rstn_x1024_MASK)
9573/*! @} */
9574
9575/*! @name INIT2 - SDRAM Initialization Register 2 */
9576/*! @{ */
9577#define DDRC_INIT2_min_stable_clock_x1_MASK (0xFU)
9578#define DDRC_INIT2_min_stable_clock_x1_SHIFT (0U)
9579/*! min_stable_clock_x1 - Time to wait after the first CKE high, tINIT2. Present only in designs
9580 * configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 5 x tCK delay. When the
9581 * controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by
9582 * 2, and round it up to the next integer value. Unit: DFI clock cycles.
9583 */
9584#define DDRC_INIT2_min_stable_clock_x1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_min_stable_clock_x1_SHIFT)) & DDRC_INIT2_min_stable_clock_x1_MASK)
9585#define DDRC_INIT2_idle_after_reset_x32_MASK (0xFF00U)
9586#define DDRC_INIT2_idle_after_reset_x32_SHIFT (8U)
9587/*! idle_after_reset_x32 - Idle time after the reset command, tINIT4. Present only in designs
9588 * configured to support LPDDR2. When the controller is operating in 1:2 frequency ratio mode, program
9589 * this to JEDEC spec value divided by 2, and round it up to the next integer value. Unit: 32 DFI
9590 * clock cycles.
9591 */
9592#define DDRC_INIT2_idle_after_reset_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT2_idle_after_reset_x32_SHIFT)) & DDRC_INIT2_idle_after_reset_x32_MASK)
9593/*! @} */
9594
9595/*! @name INIT3 - SDRAM Initialization Register 3 */
9596/*! @{ */
9597#define DDRC_INIT3_emr_MASK (0xFFFFU)
9598#define DDRC_INIT3_emr_SHIFT (0U)
9599/*! emr - DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this
9600 * register is ignored. The DDRC sets those bits appropriately. DDR3/DDR4: Value to write to MR1
9601 * register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by
9602 * the DDRC during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 -
9603 * Value to write to MR2 register
9604 */
9605#define DDRC_INIT3_emr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_emr_SHIFT)) & DDRC_INIT3_emr_MASK)
9606#define DDRC_INIT3_mr_MASK (0xFFFF0000U)
9607#define DDRC_INIT3_mr_SHIFT (16U)
9608/*! mr - DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The
9609 * DDRC sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to
9610 * write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 register
9611 */
9612#define DDRC_INIT3_mr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_mr_SHIFT)) & DDRC_INIT3_mr_MASK)
9613/*! @} */
9614
9615/*! @name INIT4 - SDRAM Initialization Register 4 */
9616/*! @{ */
9617#define DDRC_INIT4_emr3_MASK (0xFFFFU)
9618#define DDRC_INIT4_emr3_SHIFT (0U)
9619/*! emr3 - DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register
9620 * mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 register
9621 */
9622#define DDRC_INIT4_emr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_emr3_SHIFT)) & DDRC_INIT4_emr3_MASK)
9623#define DDRC_INIT4_emr2_MASK (0xFFFF0000U)
9624#define DDRC_INIT4_emr2_SHIFT (16U)
9625/*! emr2 - DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register
9626 * LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unused
9627 */
9628#define DDRC_INIT4_emr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_emr2_SHIFT)) & DDRC_INIT4_emr2_MASK)
9629/*! @} */
9630
9631/*! @name INIT5 - SDRAM Initialization Register 5 */
9632/*! @{ */
9633#define DDRC_INIT5_max_auto_init_x1024_MASK (0x3FFU)
9634#define DDRC_INIT5_max_auto_init_x1024_SHIFT (0U)
9635/*! max_auto_init_x1024 - Maximum duration of the auto initialization, tINIT5. Present only in
9636 * designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 10 us. Unit: 1024 DFI
9637 * clock cycles.
9638 */
9639#define DDRC_INIT5_max_auto_init_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_max_auto_init_x1024_SHIFT)) & DDRC_INIT5_max_auto_init_x1024_MASK)
9640#define DDRC_INIT5_dev_zqinit_x32_MASK (0xFF0000U)
9641#define DDRC_INIT5_dev_zqinit_x32_SHIFT (16U)
9642/*! dev_zqinit_x32 - ZQ initial calibration, tZQINIT. Present only in designs configured to support
9643 * DDR3 or DDR4 or LPDDR2/LPDDR3. DDR3 typically requires 512 SDRAM clock cycles. DDR4 requires
9644 * 1024 SDRAM clock cycles. LPDDR2/LPDDR3 requires 1 us. When the controller is operating in 1:2
9645 * frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the
9646 * next integer value. Unit: 32 DFI clock cycles.
9647 */
9648#define DDRC_INIT5_dev_zqinit_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT5_dev_zqinit_x32_SHIFT)) & DDRC_INIT5_dev_zqinit_x32_MASK)
9649/*! @} */
9650
9651/*! @name INIT6 - SDRAM Initialization Register 6 */
9652/*! @{ */
9653#define DDRC_INIT6_mr5_MASK (0xFFFFU)
9654#define DDRC_INIT6_mr5_SHIFT (0U)
9655/*! mr5 - DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.
9656 */
9657#define DDRC_INIT6_mr5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_mr5_SHIFT)) & DDRC_INIT6_mr5_MASK)
9658#define DDRC_INIT6_mr4_MASK (0xFFFF0000U)
9659#define DDRC_INIT6_mr4_SHIFT (16U)
9660/*! mr4 - DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.
9661 */
9662#define DDRC_INIT6_mr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_mr4_SHIFT)) & DDRC_INIT6_mr4_MASK)
9663/*! @} */
9664
9665/*! @name INIT7 - SDRAM Initialization Register 7 */
9666/*! @{ */
9667#define DDRC_INIT7_mr6_MASK (0xFFFF0000U)
9668#define DDRC_INIT7_mr6_SHIFT (16U)
9669/*! mr6 - DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.
9670 */
9671#define DDRC_INIT7_mr6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT7_mr6_SHIFT)) & DDRC_INIT7_mr6_MASK)
9672/*! @} */
9673
9674/*! @name DIMMCTL - DIMM Control Register */
9675/*! @{ */
9676#define DDRC_DIMMCTL_dimm_stagger_cs_en_MASK (0x1U)
9677#define DDRC_DIMMCTL_dimm_stagger_cs_en_SHIFT (0U)
9678/*! dimm_stagger_cs_en - Staggering enable for multi-rank accesses (for multi-rank UDIMM, RDIMM and
9679 * LRDIMM implementations only). This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4 SDRAMs.
9680 * Even if this bit is set it does not take care of software driven MR commands (via
9681 * MRCTRL0/MRCTRL1), where software is responsible to send them to separate ranks as appropriate.
9682 * 0b0..Do not stagger accesses
9683 * 0b1..(non-DDR4) Send all commands to even and odd ranks separately
9684 * 0b1..(DDR4) Send MRS commands to each ranks separately
9685 */
9686#define DDRC_DIMMCTL_dimm_stagger_cs_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_stagger_cs_en_SHIFT)) & DDRC_DIMMCTL_dimm_stagger_cs_en_MASK)
9687#define DDRC_DIMMCTL_dimm_addr_mirr_en_MASK (0x2U)
9688#define DDRC_DIMMCTL_dimm_addr_mirr_en_SHIFT (1U)
9689/*! dimm_addr_mirr_en - Address Mirroring Enable (for multi-rank UDIMM implementations and
9690 * multi-rank DDR4 RDIMM/LRDIMM implementations). Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address
9691 * mirroring for odd ranks, which means that the following address, bank address and bank group
9692 * bits are swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for
9693 * the DDR4. Setting this bit ensures that, for mode register accesses during the automatic
9694 * initialization routine, these bits are swapped within the DDRC to compensate for this
9695 * UDIMM/RDIMM/LRDIMM swapping. In addition to the automatic initialization routine, in case of DDR4
9696 * UDIMM/RDIMM/LRDIMM, they are swapped during the automatic MRS access to enable/disable of a particular
9697 * DDR4 feature. Note: This has no effect on the address of any other memory accesses, or of
9698 * software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3 or LPDDR4
9699 * SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0
9700 * because BG1 is invalid, hence dimm_dis_bg_mirroring register must be set to 1.
9701 * 0b0..Do not implement address mirroring
9702 * 0b1..For odd ranks, implement address mirroring for MRS commands to during initialization and for any
9703 * automatic DDR4 MRS commands (to be used if UDIMM/RDIMM/LRDIMM implements address mirroring)
9704 */
9705#define DDRC_DIMMCTL_dimm_addr_mirr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_addr_mirr_en_SHIFT)) & DDRC_DIMMCTL_dimm_addr_mirr_en_MASK)
9706#define DDRC_DIMMCTL_dimm_output_inv_en_MASK (0x4U)
9707#define DDRC_DIMMCTL_dimm_output_inv_en_SHIFT (2U)
9708/*! dimm_output_inv_en - Output Inversion Enable (for DDR4 RDIMM/LRDIMM implementations only). DDR4
9709 * RDIMM/LRDIMM implements the Output Inversion feature by default, which means that the
9710 * following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13,
9711 * A17, BA0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the
9712 * DDRC during the automatic initialization routine and enabling of a particular DDR4 feature,
9713 * separate A-side and B-side mode register accesses are generated. For B-side mode register
9714 * accesses, these bits are inverted within the DDRC to compensate for this RDIMM/LRDIMM inversion. It
9715 * is recommended to set this bit always, if using DDR4 RDIMMs/LRDIMMs. Note: This has no effect
9716 * on the address of any other memory accesses, or of software-driven mode register accesses.
9717 * 0b0..Do not implement output inversion for B-side DRAMs.
9718 * 0b1..Implement output inversion for B-side DRAMs.
9719 */
9720#define DDRC_DIMMCTL_dimm_output_inv_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_output_inv_en_SHIFT)) & DDRC_DIMMCTL_dimm_output_inv_en_MASK)
9721#define DDRC_DIMMCTL_mrs_a17_en_MASK (0x8U)
9722#define DDRC_DIMMCTL_mrs_a17_en_SHIFT (3U)
9723/*! mrs_a17_en - Enable for A17 bit of MRS command. A17 bit of the mode register address is
9724 * specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs
9725 * which do not have A17 are attached and the Output Inversion are enabled, this must be set to
9726 * 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on
9727 * the address of any other memory accesses, or of software-driven mode register accesses.
9728 * 0b0..Disabled
9729 * 0b1..Enabled
9730 */
9731#define DDRC_DIMMCTL_mrs_a17_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_mrs_a17_en_SHIFT)) & DDRC_DIMMCTL_mrs_a17_en_MASK)
9732#define DDRC_DIMMCTL_mrs_bg1_en_MASK (0x10U)
9733#define DDRC_DIMMCTL_mrs_bg1_en_SHIFT (4U)
9734/*! mrs_bg1_en - Enable for BG1 bit of MRS command. BG1 bit of the mode register address is
9735 * specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs
9736 * which do not have BG1 are attached and both the CA parity and the Output Inversion are
9737 * enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note:
9738 * This has no effect on the address of any other memory accesses, or of software-driven mode
9739 * register accesses. If address mirroring is enabled, this is applied to BG1 of even ranks and BG0
9740 * of odd ranks.
9741 * 0b0..Disabled
9742 * 0b1..Enabled
9743 */
9744#define DDRC_DIMMCTL_mrs_bg1_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_mrs_bg1_en_SHIFT)) & DDRC_DIMMCTL_mrs_bg1_en_MASK)
9745#define DDRC_DIMMCTL_dimm_dis_bg_mirroring_MASK (0x20U)
9746#define DDRC_DIMMCTL_dimm_dis_bg_mirroring_SHIFT (5U)
9747/*! dimm_dis_bg_mirroring - Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and
9748 * BG1 are NOT swapped even if Address Mirroring is enabled. This will be required for DDR4 DIMMs
9749 * with x16 devices.
9750 * 0b0..BG0 and BG1 are swapped if address mirroring is enabled.
9751 * 0b1..BG0 and BG1 are NOT swapped.
9752 */
9753#define DDRC_DIMMCTL_dimm_dis_bg_mirroring(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_dimm_dis_bg_mirroring_SHIFT)) & DDRC_DIMMCTL_dimm_dis_bg_mirroring_MASK)
9754#define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_MASK (0x40U)
9755#define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT (6U)
9756/*! lrdimm_bcom_cmd_prot - Protects the timing restrictions (tBCW/tMRC) between consecutive BCOM
9757 * commands defined in the Data Buffer specification. When using DDR4 LRDIMM, this bit must be set
9758 * to 1. Otherwise, this bit must be set to 0.
9759 */
9760#define DDRC_DIMMCTL_lrdimm_bcom_cmd_prot(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_SHIFT)) & DDRC_DIMMCTL_lrdimm_bcom_cmd_prot_MASK)
9761/*! @} */
9762
9763/*! @name RANKCTL - Rank Control Register */
9764/*! @{ */
9765#define DDRC_RANKCTL_max_rank_rd_MASK (0xFU)
9766#define DDRC_RANKCTL_max_rank_rd_SHIFT (0U)
9767/*! max_rank_rd - Only present for multi-rank configurations. Background: Reads to the same rank can
9768 * be performed back-to-back. Reads to different ranks require additional gap dictated by the
9769 * register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus contention as well as to
9770 * give PHY enough time to switch the delay when changing ranks. The DDRC arbitrates for bus
9771 * access on a cycle-by-cycle basis; therefore after a read is scheduled, there are few clock cycles
9772 * (determined by the value on RANKCTL.diff_rank_rd_gap register) in which only reads from the
9773 * same rank are eligible to be scheduled. This prevents reads from other ranks from having fair
9774 * access to the data bus. This parameter represents the maximum number of reads that can be
9775 * scheduled consecutively to the same rank. After this number is reached, a delay equal to
9776 * RANKCTL.diff_rank_rd_gap is inserted by the scheduler to allow all ranks a fair opportunity to be
9777 * scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fairness. This
9778 * feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on
9779 * the same rank as long as commands are available for it. Minimum programmable value is 0 (feature
9780 * disabled) and maximum programmable value is 0xF. FOR PERFORMANCE ONLY.
9781 */
9782#define DDRC_RANKCTL_max_rank_rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_max_rank_rd_SHIFT)) & DDRC_RANKCTL_max_rank_rd_MASK)
9783#define DDRC_RANKCTL_diff_rank_rd_gap_MASK (0xF0U)
9784#define DDRC_RANKCTL_diff_rank_rd_gap_SHIFT (4U)
9785/*! diff_rank_rd_gap - Only present for multi-rank configurations. Indicates the number of clocks of
9786 * gap in data responses when performing consecutive reads to different ranks. This is used to
9787 * switch the delays in the PHY to match the rank requirements. This value should consider both
9788 * PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for
9789 * value of tphy_rdcsgap) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased
9790 * by 1. If read postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT
9791 * requirement: The value programmed in this register takes care of the ODT switch off timing requirement
9792 * when switching ranks during reads. When the controller is operating in 1:1 mode, program this
9793 * to the larger of PHY requirement or ODT requirement. When the controller is operating in 1:2
9794 * mode, program this to the larger value divided by two and round it up to the next integer.
9795 * Note that, if using DDR4-LRDIMM, refer to TRDRD timing requirements in JEDEC DDR4 Data Buffer
9796 * (DDR4DB01) Specification.
9797 */
9798#define DDRC_RANKCTL_diff_rank_rd_gap(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_diff_rank_rd_gap_SHIFT)) & DDRC_RANKCTL_diff_rank_rd_gap_MASK)
9799#define DDRC_RANKCTL_diff_rank_wr_gap_MASK (0xF00U)
9800#define DDRC_RANKCTL_diff_rank_wr_gap_SHIFT (8U)
9801/*! diff_rank_wr_gap - Only present for multi-rank configurations. Indicates the number of clocks of
9802 * gap in data responses when performing consecutive writes to different ranks. This is used to
9803 * switch the delays in the PHY to match the rank requirements. This value should consider both
9804 * PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for
9805 * value of tphy_wrcsgap) If CRC feature is enabled, should be increased by 1. If write preamble
9806 * is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If write postamble is set to
9807 * 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed in this
9808 * register takes care of the ODT switch off timing requirement when switching ranks during writes.
9809 * For LPDDR4, the requirement is ODTLoff - ODTLon - BL/2 + 1 When the controller is operating in
9810 * 1:1 mode, program this to the larger of PHY requirement or ODT requirement. When the
9811 * controller is operating in 1:2 mode, program this to the larger value divided by two and round it up to
9812 * the next integer. Note that, if using DDR4-LRDIMM, refer to TWRWR timing requirements in
9813 * JEDEC DDR4 Data Buffer (DDR4DB01) Specification.
9814 */
9815#define DDRC_RANKCTL_diff_rank_wr_gap(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RANKCTL_diff_rank_wr_gap_SHIFT)) & DDRC_RANKCTL_diff_rank_wr_gap_MASK)
9816/*! @} */
9817
9818/*! @name DRAMTMG0 - SDRAM Timing Register 0 */
9819/*! @{ */
9820#define DDRC_DRAMTMG0_t_ras_min_MASK (0x3FU)
9821#define DDRC_DRAMTMG0_t_ras_min_SHIFT (0U)
9822/*! t_ras_min - tRAS(min): Minimum time between activate and precharge to the same bank. When the
9823 * controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2. No rounding
9824 * up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode,
9825 * program this to (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks
9826 */
9827#define DDRC_DRAMTMG0_t_ras_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_ras_min_SHIFT)) & DDRC_DRAMTMG0_t_ras_min_MASK)
9828#define DDRC_DRAMTMG0_t_ras_max_MASK (0x7F00U)
9829#define DDRC_DRAMTMG0_t_ras_max_SHIFT (8U)
9830/*! t_ras_max - tRAS(max): Maximum time between activate and precharge to same bank. This is the
9831 * maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid.
9832 * When the controller is operating in 1:2 frequency ratio mode, program this to (tRAS(max)-1)/2.
9833 * No rounding up. Unit: Multiples of 1024 clocks.
9834 */
9835#define DDRC_DRAMTMG0_t_ras_max(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_ras_max_SHIFT)) & DDRC_DRAMTMG0_t_ras_max_MASK)
9836#define DDRC_DRAMTMG0_t_faw_MASK (0x3F0000U)
9837#define DDRC_DRAMTMG0_t_faw_SHIFT (16U)
9838/*! t_faw - tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank
9839 * design, at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller
9840 * is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next
9841 * integer value. In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency
9842 * mode. Unit: Clocks
9843 */
9844#define DDRC_DRAMTMG0_t_faw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_t_faw_SHIFT)) & DDRC_DRAMTMG0_t_faw_MASK)
9845#define DDRC_DRAMTMG0_wr2pre_MASK (0x7F000000U)
9846#define DDRC_DRAMTMG0_wr2pre_SHIFT (24U)
9847/*! wr2pre - Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL
9848 * + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower
9849 * frequencies where: - WL = write latency - BL = burst length. This must match the value programmed in
9850 * the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present.
9851 * - tWR = Write recovery time. This comes directly from the SDRAM specification. Add one extra
9852 * cycle for LPDDR2/LPDDR3/LPDDR4 for this parameter. When the controller is operating in 1:2
9853 * frequency ratio mode, 1T mode, divide the above value by 2. No rounding up. When the controller
9854 * is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, divide the above value by 2
9855 * and round it up to the next integer value. Note that, depending on the PHY, if using LRDIMM, it
9856 * may be necessary to adjust the value of this parameter to compensate for the extra cycle of
9857 * latency through the LRDIMM.
9858 */
9859#define DDRC_DRAMTMG0_wr2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_wr2pre_SHIFT)) & DDRC_DRAMTMG0_wr2pre_MASK)
9860/*! @} */
9861
9862/*! @name DRAMTMG1 - SDRAM Timing Register 1 */
9863/*! @{ */
9864#define DDRC_DRAMTMG1_t_rc_MASK (0x7FU)
9865#define DDRC_DRAMTMG1_t_rc_SHIFT (0U)
9866/*! t_rc - tRC: Minimum time between activates to same bank. When the controller is operating in 1:2
9867 * frequency ratio mode, program this to (tRC/2) and round up to next integer value. Unit:
9868 * Clocks.
9869 */
9870#define DDRC_DRAMTMG1_t_rc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_t_rc_SHIFT)) & DDRC_DRAMTMG1_t_rc_MASK)
9871#define DDRC_DRAMTMG1_rd2pre_MASK (0x3F00U)
9872#define DDRC_DRAMTMG1_rd2pre_SHIFT (8U)
9873/*! rd2pre - tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP,
9874 * 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of following two equations: tAL + max (tRTP, 4)
9875 * or, RL + BL/2 - tRP (*). - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4:
9876 * LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4
9877 * - LPDDR4: BL/2 + max(tRTP,8) - 8 (*) When both DDR4 SDRAM and ST-MRAM are used simultaneously,
9878 * use SDRAM's tRP value for calculation. When the controller is operating in 1:2 mode, 1T mode,
9879 * divide the above value by 2. No rounding up. When the controller is operating in 1:2 mode, 2T
9880 * mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.
9881 * Unit: Clocks.
9882 */
9883#define DDRC_DRAMTMG1_rd2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_rd2pre_SHIFT)) & DDRC_DRAMTMG1_rd2pre_MASK)
9884#define DDRC_DRAMTMG1_t_xp_MASK (0x1F0000U)
9885#define DDRC_DRAMTMG1_t_xp_SHIFT (16U)
9886/*! t_xp - tXP: Minimum time after power-down exit to any operation. For DDR3, this should be
9887 * programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used,
9888 * set to (tXP+PL) instead. When the controller is operating in 1:2 frequency ratio mode, program
9889 * this to (tXP/2) and round it up to the next integer value. Units: Clocks
9890 */
9891#define DDRC_DRAMTMG1_t_xp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_t_xp_SHIFT)) & DDRC_DRAMTMG1_t_xp_MASK)
9892/*! @} */
9893
9894/*! @name DRAMTMG2 - SDRAM Timing Register 2 */
9895/*! @{ */
9896#define DDRC_DRAMTMG2_wr2rd_MASK (0x3FU)
9897#define DDRC_DRAMTMG2_wr2rd_SHIFT (0U)
9898/*! wr2rd - DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from
9899 * write command to read command for same bank group. In others, minimum time from write command to
9900 * read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and
9901 * global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL
9902 * = burst length. This must match the value programmed in the BL bit of the mode register to
9903 * the SDRAM - tWTR_L = internal write to read command delay for same bank group. This comes
9904 * directly from the SDRAM specification. - tWTR = internal write to read command delay. This comes
9905 * directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation.
9906 * When the controller is operating in 1:2 mode, divide the value calculated using the above
9907 * equation by 2, and round it up to next integer.
9908 */
9909#define DDRC_DRAMTMG2_wr2rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_wr2rd_SHIFT)) & DDRC_DRAMTMG2_wr2rd_MASK)
9910#define DDRC_DRAMTMG2_rd2wr_MASK (0x3F00U)
9911#define DDRC_DRAMTMG2_rd2wr_SHIFT (8U)
9912/*! rd2wr - DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL
9913 * + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK)
9914 * + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) +
9915 * RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command.
9916 * Include time for bus turnaround and all per-bank, per-rank, and global constraints. Please see
9917 * the relevant PHY databook for details of what should be included here. Unit: Clocks. Where: -
9918 * WL = write latency - BL = burst length. This must match the value programmed in the BL bit of
9919 * the mode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBLE = write
9920 * preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to
9921 * LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated
9922 * tDQSCKmax should be used. When the controller is operating in 1:2 frequency ratio mode, divide the
9923 * value calculated using the above equation by 2, and round it up to next integer. Note that,
9924 * depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter
9925 * to compensate for the extra cycle of latency through the LRDIMM.
9926 */
9927#define DDRC_DRAMTMG2_rd2wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_rd2wr_SHIFT)) & DDRC_DRAMTMG2_rd2wr_MASK)
9928#define DDRC_DRAMTMG2_read_latency_MASK (0x3F0000U)
9929#define DDRC_DRAMTMG2_read_latency_SHIFT (16U)
9930/*! read_latency - Set to RL Time from read command to read data on SDRAM interface. This must be
9931 * set to RL. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust
9932 * the value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When
9933 * the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the
9934 * above equation by 2, and round it up to next integer. This register field is not required for
9935 * DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in
9936 * DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
9937 */
9938#define DDRC_DRAMTMG2_read_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_read_latency_SHIFT)) & DDRC_DRAMTMG2_read_latency_MASK)
9939#define DDRC_DRAMTMG2_write_latency_MASK (0x3F000000U)
9940#define DDRC_DRAMTMG2_write_latency_SHIFT (24U)
9941/*! write_latency - Set to WL Time from write command to write data on SDRAM interface. This must be
9942 * set to WL. For mDDR, it should normally be set to 1. Note that, depending on the PHY, if
9943 * using RDIMM/LRDIMM, it may be necessary to adjust the value of WL to compensate for the extra
9944 * cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio
9945 * mode, divide the value calculated using the above equation by 2, and round it up to next
9946 * integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set),
9947 * as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those
9948 * protocols Unit: clocks
9949 */
9950#define DDRC_DRAMTMG2_write_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_write_latency_SHIFT)) & DDRC_DRAMTMG2_write_latency_MASK)
9951/*! @} */
9952
9953/*! @name DRAMTMG3 - SDRAM Timing Register 3 */
9954/*! @{ */
9955#define DDRC_DRAMTMG3_t_mod_MASK (0x3FFU)
9956#define DDRC_DRAMTMG3_t_mod_SHIFT (0U)
9957/*! t_mod - tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and
9958 * following non-load mode command. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead.
9959 * Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to
9960 * next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using
9961 * RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this parameter to
9962 * compensate for the extra cycle of latency applied to mode register writes by the RDIMM/LRDIMM chip.
9963 * Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller
9964 * is operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if
9965 * controller is operating in 1:2 frequency ratio mode.
9966 */
9967#define DDRC_DRAMTMG3_t_mod(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mod_SHIFT)) & DDRC_DRAMTMG3_t_mod_MASK)
9968#define DDRC_DRAMTMG3_t_mrd_MASK (0x3F000U)
9969#define DDRC_DRAMTMG3_t_mrd_SHIFT (12U)
9970/*! t_mrd - tMRD: Cycles to wait after a mode register write or read. Depending on the connected
9971 * SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any command DDR3/4: Time from MRS to MRS
9972 * command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command. When the controller is
9973 * operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer
9974 * value. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead.
9975 */
9976#define DDRC_DRAMTMG3_t_mrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mrd_SHIFT)) & DDRC_DRAMTMG3_t_mrd_MASK)
9977#define DDRC_DRAMTMG3_t_mrw_MASK (0x3FF00000U)
9978#define DDRC_DRAMTMG3_t_mrw_SHIFT (20U)
9979/*! t_mrw - Time to wait after a mode register write or read (MRW or MRR). Present only in designs
9980 * configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3
9981 * typically requires value of 10. LPDDR4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2,
9982 * this register is used for the time from a MRW/MRR to all other commands. When the controller
9983 * is operating in 1:2 frequency ratio mode, program this to the above values divided by 2 and
9984 * round it up to the next integer value. For LDPDR3, this register is used for the time from a
9985 * MRW/MRR to a MRW/MRR.
9986 */
9987#define DDRC_DRAMTMG3_t_mrw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_t_mrw_SHIFT)) & DDRC_DRAMTMG3_t_mrw_MASK)
9988/*! @} */
9989
9990/*! @name DRAMTMG4 - SDRAM Timing Register 4 */
9991/*! @{ */
9992#define DDRC_DRAMTMG4_t_rp_MASK (0x1FU)
9993#define DDRC_DRAMTMG4_t_rp_SHIFT (0U)
9994/*! t_rp - tRP: Minimum time from precharge to activate of same bank. When the controller is
9995 * operating in 1:1 frequency ratio mode, t_rp should be set to RoundUp(tRP/tCK). When the controller is
9996 * operating in 1:2 frequency ratio mode, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) +
9997 * 1. When the controller is operating in 1:2 frequency ratio mode in LPDDR4, t_rp should be set
9998 * to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
9999 */
10000#define DDRC_DRAMTMG4_t_rp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rp_SHIFT)) & DDRC_DRAMTMG4_t_rp_MASK)
10001#define DDRC_DRAMTMG4_t_rrd_MASK (0xF00U)
10002#define DDRC_DRAMTMG4_t_rrd_SHIFT (8U)
10003/*! t_rrd - DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank
10004 * group. Others: tRRD: Minimum time between activates from bank "a" to bank "b" When the controller
10005 * is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or tRRD/2) and round it
10006 * up to the next integer value. Unit: Clocks.
10007 */
10008#define DDRC_DRAMTMG4_t_rrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rrd_SHIFT)) & DDRC_DRAMTMG4_t_rrd_MASK)
10009#define DDRC_DRAMTMG4_t_ccd_MASK (0xF0000U)
10010#define DDRC_DRAMTMG4_t_ccd_SHIFT (16U)
10011/*! t_ccd - DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank
10012 * group. Others: tCCD: This is the minimum time between two reads or two writes. When the
10013 * controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it
10014 * up to the next integer value. Unit: clocks.
10015 */
10016#define DDRC_DRAMTMG4_t_ccd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_ccd_SHIFT)) & DDRC_DRAMTMG4_t_ccd_MASK)
10017#define DDRC_DRAMTMG4_t_rcd_MASK (0x1F000000U)
10018#define DDRC_DRAMTMG4_t_rcd_SHIFT (24U)
10019/*! t_rcd - tRCD - tAL: Minimum time from activate to read or write command to same bank. When the
10020 * controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round
10021 * it up to the next integer value. Minimum value allowed for this register is 1, which implies
10022 * minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio
10023 * mode. Unit: Clocks.
10024 */
10025#define DDRC_DRAMTMG4_t_rcd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_t_rcd_SHIFT)) & DDRC_DRAMTMG4_t_rcd_MASK)
10026/*! @} */
10027
10028/*! @name DRAMTMG5 - SDRAM Timing Register 5 */
10029/*! @{ */
10030#define DDRC_DRAMTMG5_t_cke_MASK (0x1FU)
10031#define DDRC_DRAMTMG5_t_cke_SHIFT (0U)
10032/*! t_cke - Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. -
10033 * LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LPDDR4 mode: Set this to the larger of
10034 * tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. When
10035 * the controller is operating in 1:2 frequency ratio mode, program this to (value described
10036 * above)/2 and round it up to the next integer value. Unit: Clocks.
10037 */
10038#define DDRC_DRAMTMG5_t_cke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cke_SHIFT)) & DDRC_DRAMTMG5_t_cke_MASK)
10039#define DDRC_DRAMTMG5_t_ckesr_MASK (0x3F00U)
10040#define DDRC_DRAMTMG5_t_ckesr_SHIFT (8U)
10041/*! t_ckesr - Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing
10042 * in memory clock cycles. Recommended settings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR
10043 * - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 (+ PL(parity
10044 * latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased
10045 * by PL. When the controller is operating in 1:2 frequency ratio mode, program this to
10046 * recommended value divided by two and round it up to next integer.
10047 */
10048#define DDRC_DRAMTMG5_t_ckesr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_ckesr_SHIFT)) & DDRC_DRAMTMG5_t_ckesr_MASK)
10049#define DDRC_DRAMTMG5_t_cksre_MASK (0xF0000U)
10050#define DDRC_DRAMTMG5_t_cksre_SHIFT (16U)
10051/*! t_cksre - This is the time after Self Refresh Down Entry that CK is maintained as a valid clock.
10052 * Specifies the clock disable delay after SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 -
10053 * LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) (+
10054 * PL(parity latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should
10055 * be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program
10056 * this to recommended value divided by two and round it up to next integer.
10057 */
10058#define DDRC_DRAMTMG5_t_cksre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cksre_SHIFT)) & DDRC_DRAMTMG5_t_cksre_MASK)
10059#define DDRC_DRAMTMG5_t_cksrx_MASK (0xF000000U)
10060#define DDRC_DRAMTMG5_t_cksrx_SHIFT (24U)
10061/*! t_cksrx - This is the time before Self Refresh Exit that CK is maintained as a valid clock
10062 * before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR: 1 -
10063 * LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX When the
10064 * controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by
10065 * two and round it up to next integer.
10066 */
10067#define DDRC_DRAMTMG5_t_cksrx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_t_cksrx_SHIFT)) & DDRC_DRAMTMG5_t_cksrx_MASK)
10068/*! @} */
10069
10070/*! @name DRAMTMG6 - SDRAM Timing Register 6 */
10071/*! @{ */
10072#define DDRC_DRAMTMG6_t_ckcsx_MASK (0xFU)
10073#define DDRC_DRAMTMG6_t_ckcsx_SHIFT (0U)
10074/*! t_ckcsx - This is the time before Clock Stop Exit that CK is maintained as a valid clock before
10075 * issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop
10076 * Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2
10077 * When the controller is operating in 1:2 frequency ratio mode, program this to recommended value
10078 * divided by two and round it up to next integer. This is only present for designs supporting
10079 * mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
10080 */
10081#define DDRC_DRAMTMG6_t_ckcsx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckcsx_SHIFT)) & DDRC_DRAMTMG6_t_ckcsx_MASK)
10082#define DDRC_DRAMTMG6_t_ckdpdx_MASK (0xF0000U)
10083#define DDRC_DRAMTMG6_t_ckdpdx_SHIFT (16U)
10084/*! t_ckdpdx - This is the time before Deep Power Down Exit that CK is maintained as a valid clock
10085 * before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR:
10086 * 1 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode,
10087 * program this to recommended value divided by two and round it up to next integer. This is only
10088 * present for designs supporting mDDR or LPDDR2 devices.
10089 */
10090#define DDRC_DRAMTMG6_t_ckdpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckdpdx_SHIFT)) & DDRC_DRAMTMG6_t_ckdpdx_MASK)
10091#define DDRC_DRAMTMG6_t_ckdpde_MASK (0xF000000U)
10092#define DDRC_DRAMTMG6_t_ckdpde_SHIFT (24U)
10093/*! t_ckdpde - This is the time after Deep Power Down Entry that CK is maintained as a valid clock.
10094 * Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 -
10095 * LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to
10096 * recommended value divided by two and round it up to next integer. This is only present for designs
10097 * supporting mDDR or LPDDR2/LPDDR3 devices.
10098 */
10099#define DDRC_DRAMTMG6_t_ckdpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_t_ckdpde_SHIFT)) & DDRC_DRAMTMG6_t_ckdpde_MASK)
10100/*! @} */
10101
10102/*! @name DRAMTMG7 - SDRAM Timing Register 7 */
10103/*! @{ */
10104#define DDRC_DRAMTMG7_t_ckpdx_MASK (0xFU)
10105#define DDRC_DRAMTMG7_t_ckpdx_SHIFT (0U)
10106/*! t_ckpdx - This is the time before Power Down Exit that CK is maintained as a valid clock before
10107 * issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR: 0 -
10108 * LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 When using DDR2/3/4 SDRAM, this register should be set to the
10109 * same value as DRAMTMG5.t_cksrx. When the controller is operating in 1:2 frequency ratio mode,
10110 * program this to recommended value divided by two and round it up to next integer. This is only
10111 * present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
10112 */
10113#define DDRC_DRAMTMG7_t_ckpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_t_ckpdx_SHIFT)) & DDRC_DRAMTMG7_t_ckpdx_MASK)
10114#define DDRC_DRAMTMG7_t_ckpde_MASK (0xF00U)
10115#define DDRC_DRAMTMG7_t_ckpde_SHIFT (8U)
10116/*! t_ckpde - This is the time after Power Down Entry that CK is maintained as a valid clock.
10117 * Specifies the clock disable delay after PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2
10118 * - LPDDR4: tCKCKEL When using DDR2/3/4 SDRAM, this register should be set to the same value as
10119 * DRAMTMG5.t_cksre. When the controller is operating in 1:2 frequency ratio mode, program this
10120 * to recommended value divided by two and round it up to next integer. This is only present for
10121 * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
10122 */
10123#define DDRC_DRAMTMG7_t_ckpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_t_ckpde_SHIFT)) & DDRC_DRAMTMG7_t_ckpde_MASK)
10124/*! @} */
10125
10126/*! @name DRAMTMG8 - SDRAM Timing Register 8 */
10127/*! @{ */
10128#define DDRC_DRAMTMG8_t_xs_x32_MASK (0x7FU)
10129#define DDRC_DRAMTMG8_t_xs_x32_SHIFT (0U)
10130/*! t_xs_x32 - tXS: Exit Self Refresh to commands not requiring a locked DLL. When the controller is
10131 * operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round
10132 * up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
10133 * DDR4 SDRAMs.
10134 */
10135#define DDRC_DRAMTMG8_t_xs_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_x32_MASK)
10136#define DDRC_DRAMTMG8_t_xs_dll_x32_MASK (0x7F00U)
10137#define DDRC_DRAMTMG8_t_xs_dll_x32_SHIFT (8U)
10138/*! t_xs_dll_x32 - tXSDLL: Exit Self Refresh to commands requiring a locked DLL. When the controller
10139 * is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and
10140 * round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
10141 * DDR4 SDRAMs.
10142 */
10143#define DDRC_DRAMTMG8_t_xs_dll_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_dll_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_dll_x32_MASK)
10144#define DDRC_DRAMTMG8_t_xs_abort_x32_MASK (0x7F0000U)
10145#define DDRC_DRAMTMG8_t_xs_abort_x32_SHIFT (16U)
10146/*! t_xs_abort_x32 - tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self
10147 * Refresh Abort. When the controller is operating in 1:2 frequency ratio mode, program this to the
10148 * above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
10149 * Note: Ensure this is less than or equal to t_xs_x32.
10150 */
10151#define DDRC_DRAMTMG8_t_xs_abort_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_abort_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_abort_x32_MASK)
10152#define DDRC_DRAMTMG8_t_xs_fast_x32_MASK (0x7F000000U)
10153#define DDRC_DRAMTMG8_t_xs_fast_x32_SHIFT (24U)
10154/*! t_xs_fast_x32 - tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown
10155 * mode). When the controller is operating in 1:2 frequency ratio mode, program this to the
10156 * above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note:
10157 * This is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to
10158 * t_xs_x32.
10159 */
10160#define DDRC_DRAMTMG8_t_xs_fast_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_t_xs_fast_x32_SHIFT)) & DDRC_DRAMTMG8_t_xs_fast_x32_MASK)
10161/*! @} */
10162
10163/*! @name DRAMTMG9 - SDRAM Timing Register 9 */
10164/*! @{ */
10165#define DDRC_DRAMTMG9_wr2rd_s_MASK (0x3FU)
10166#define DDRC_DRAMTMG9_wr2rd_s_SHIFT (0U)
10167/*! wr2rd_s - CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different
10168 * bank group. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and
10169 * global constraints. Present only in designs configured to support DDR4. Unit: Clocks. Where:
10170 * - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value
10171 * programmed in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read
10172 * command delay for different bank group. This comes directly from the SDRAM specification. When
10173 * the controller is operating in 1:2 mode, divide the value calculated using the above equation
10174 * by 2, and round it up to next integer.
10175 */
10176#define DDRC_DRAMTMG9_wr2rd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_wr2rd_s_SHIFT)) & DDRC_DRAMTMG9_wr2rd_s_MASK)
10177#define DDRC_DRAMTMG9_t_rrd_s_MASK (0xF00U)
10178#define DDRC_DRAMTMG9_t_rrd_s_SHIFT (8U)
10179/*! t_rrd_s - tRRD_S: Minimum time between activates from bank "a" to bank "b" for different bank
10180 * group. When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_S/2)
10181 * and round it up to the next integer value. Present only in designs configured to support DDR4.
10182 * Unit: Clocks.
10183 */
10184#define DDRC_DRAMTMG9_t_rrd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_t_rrd_s_SHIFT)) & DDRC_DRAMTMG9_t_rrd_s_MASK)
10185#define DDRC_DRAMTMG9_t_ccd_s_MASK (0x70000U)
10186#define DDRC_DRAMTMG9_t_ccd_s_SHIFT (16U)
10187/*! t_ccd_s - tCCD_S: This is the minimum time between two reads or two writes for different bank
10188 * group. For bank switching (from bank "a" to bank "b"), the minimum time is this value + 1. When
10189 * the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_S/2) and round
10190 * it up to the next integer value. Present only in designs configured to support DDR4. Unit:
10191 * clocks.
10192 */
10193#define DDRC_DRAMTMG9_t_ccd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_t_ccd_s_SHIFT)) & DDRC_DRAMTMG9_t_ccd_s_MASK)
10194#define DDRC_DRAMTMG9_ddr4_wr_preamble_MASK (0x40000000U)
10195#define DDRC_DRAMTMG9_ddr4_wr_preamble_SHIFT (30U)
10196/*! ddr4_wr_preamble - DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2
10197 */
10198#define DDRC_DRAMTMG9_ddr4_wr_preamble(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_ddr4_wr_preamble_SHIFT)) & DDRC_DRAMTMG9_ddr4_wr_preamble_MASK)
10199/*! @} */
10200
10201/*! @name DRAMTMG10 - SDRAM Timing Register 10 */
10202/*! @{ */
10203#define DDRC_DRAMTMG10_t_gear_hold_MASK (0x3U)
10204#define DDRC_DRAMTMG10_t_gear_hold_SHIFT (0U)
10205/*! t_gear_hold - Geardown hold time. Minimum value of this register is 1. Zero is invalid. For
10206 * DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in
10207 * 1:2 frequency ratio mode, program this to (tGEAR_hold/2) and round it up to the next integer
10208 * value. Unit: Clocks
10209 */
10210#define DDRC_DRAMTMG10_t_gear_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_gear_hold_SHIFT)) & DDRC_DRAMTMG10_t_gear_hold_MASK)
10211#define DDRC_DRAMTMG10_t_gear_setup_MASK (0xCU)
10212#define DDRC_DRAMTMG10_t_gear_setup_SHIFT (2U)
10213/*! t_gear_setup - Geardown setup time. Minimum value of this register is 1. Zero is invalid. For
10214 * DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in
10215 * 1:2 frequency ratio mode, program this to (tGEAR_setup/2) and round it up to the next integer
10216 * value. Unit: Clocks
10217 */
10218#define DDRC_DRAMTMG10_t_gear_setup(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_gear_setup_SHIFT)) & DDRC_DRAMTMG10_t_gear_setup_MASK)
10219#define DDRC_DRAMTMG10_t_cmd_gear_MASK (0x1F00U)
10220#define DDRC_DRAMTMG10_t_cmd_gear_SHIFT (8U)
10221/*! t_cmd_gear - Sync pulse to first valid command. For DDR4-2666 and DDR4-3200, this parameter is
10222 * defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for
10223 * this register is 24 When the controller is operating in 1:2 mode, program this to (tCMD_GEAR/2)
10224 * and round it up to the next integer value. Unit: Clocks
10225 */
10226#define DDRC_DRAMTMG10_t_cmd_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_cmd_gear_SHIFT)) & DDRC_DRAMTMG10_t_cmd_gear_MASK)
10227#define DDRC_DRAMTMG10_t_sync_gear_MASK (0x1F0000U)
10228#define DDRC_DRAMTMG10_t_sync_gear_SHIFT (16U)
10229/*! t_sync_gear - Indicates the time between MRS command and the sync pulse time. This must be even
10230 * number of clocks. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min)+4nCK
10231 * tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24+4 = 28
10232 * When the controller is operating in 1:2 mode, program this to (tSYNC_GEAR/2) and round it up
10233 * to the next integer value. Unit: Clocks
10234 */
10235#define DDRC_DRAMTMG10_t_sync_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_t_sync_gear_SHIFT)) & DDRC_DRAMTMG10_t_sync_gear_MASK)
10236/*! @} */
10237
10238/*! @name DRAMTMG11 - SDRAM Timing Register 11 */
10239/*! @{ */
10240#define DDRC_DRAMTMG11_t_ckmpe_MASK (0x1FU)
10241#define DDRC_DRAMTMG11_t_ckmpe_SHIFT (0U)
10242/*! t_ckmpe - tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs
10243 * configured to support DDR4. Unit: Clocks. When the controller is operating in 1:2 frequency ratio
10244 * mode, divide the value calculated using the above equation by 2, and round it up to next
10245 * integer.
10246 */
10247#define DDRC_DRAMTMG11_t_ckmpe(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_ckmpe_SHIFT)) & DDRC_DRAMTMG11_t_ckmpe_MASK)
10248#define DDRC_DRAMTMG11_t_mpx_s_MASK (0x300U)
10249#define DDRC_DRAMTMG11_t_mpx_s_SHIFT (8U)
10250/*! t_mpx_s - tMPX_S: Minimum time CS setup time to CKE. When the controller is operating in 1:2
10251 * frequency ratio mode, program this to (tMPX_S/2) and round it up to the next integer value.
10252 * Present only in designs configured to support DDR4. Unit: Clocks.
10253 */
10254#define DDRC_DRAMTMG11_t_mpx_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_mpx_s_SHIFT)) & DDRC_DRAMTMG11_t_mpx_s_MASK)
10255#define DDRC_DRAMTMG11_t_mpx_lh_MASK (0x1F0000U)
10256#define DDRC_DRAMTMG11_t_mpx_lh_SHIFT (16U)
10257/*! t_mpx_lh - tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the
10258 * controller is operating in 1:2 frequency ratio mode, program this to RoundUp(tMPX_LH/2)+1. Present
10259 * only in designs configured to support DDR4. Unit: clocks.
10260 */
10261#define DDRC_DRAMTMG11_t_mpx_lh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_t_mpx_lh_SHIFT)) & DDRC_DRAMTMG11_t_mpx_lh_MASK)
10262#define DDRC_DRAMTMG11_post_mpsm_gap_x32_MASK (0x7F000000U)
10263#define DDRC_DRAMTMG11_post_mpsm_gap_x32_SHIFT (24U)
10264/*! post_mpsm_gap_x32 - tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL.
10265 * When the controller is operating in 1:2 frequency ratio mode, program this to (tXMPDLL/2) and
10266 * round it up to the next integer value. Present only in designs configured to support DDR4.
10267 * Unit: Multiples of 32 clocks.
10268 */
10269#define DDRC_DRAMTMG11_post_mpsm_gap_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_post_mpsm_gap_x32_SHIFT)) & DDRC_DRAMTMG11_post_mpsm_gap_x32_MASK)
10270/*! @} */
10271
10272/*! @name DRAMTMG12 - SDRAM Timing Register 12 */
10273/*! @{ */
10274#define DDRC_DRAMTMG12_t_mrd_pda_MASK (0x1FU)
10275#define DDRC_DRAMTMG12_t_mrd_pda_SHIFT (0U)
10276/*! t_mrd_pda - tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the
10277 * controller is operating in 1:2 frequency ratio mode, program this to (tMRD_PDA/2) and round it up
10278 * to the next integer value.
10279 */
10280#define DDRC_DRAMTMG12_t_mrd_pda(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_mrd_pda_SHIFT)) & DDRC_DRAMTMG12_t_mrd_pda_MASK)
10281#define DDRC_DRAMTMG12_t_ckehcmd_MASK (0xF00U)
10282#define DDRC_DRAMTMG12_t_ckehcmd_SHIFT (8U)
10283/*! t_ckehcmd - tCKEHCMD: Valid command requirement after CKE input HIGH. When the controller is
10284 * operating in 1:2 frequency ratio mode, program this to (tCKEHCMD/2) and round it up to the next
10285 * integer value.
10286 */
10287#define DDRC_DRAMTMG12_t_ckehcmd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_ckehcmd_SHIFT)) & DDRC_DRAMTMG12_t_ckehcmd_MASK)
10288#define DDRC_DRAMTMG12_t_cmdcke_MASK (0x30000U)
10289#define DDRC_DRAMTMG12_t_cmdcke_SHIFT (16U)
10290/*! t_cmdcke - tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE
10291 * or tCMDCKE When the controller is operating in 1:2 frequency ratio mode, program this to
10292 * (max(tESCKE, tCMDCKE)/2) and round it up to the next integer value.
10293 */
10294#define DDRC_DRAMTMG12_t_cmdcke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_t_cmdcke_SHIFT)) & DDRC_DRAMTMG12_t_cmdcke_MASK)
10295/*! @} */
10296
10297/*! @name DRAMTMG13 - SDRAM Timing Register 13 */
10298/*! @{ */
10299#define DDRC_DRAMTMG13_t_ppd_MASK (0x7U)
10300#define DDRC_DRAMTMG13_t_ppd_SHIFT (0U)
10301/*! t_ppd - LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the
10302 * controller is operating in 1:2 frequency ratio mode, program this to (tPPD/2) and round it up to
10303 * the next integer value. Unit: Clocks.
10304 */
10305#define DDRC_DRAMTMG13_t_ppd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_t_ppd_SHIFT)) & DDRC_DRAMTMG13_t_ppd_MASK)
10306#define DDRC_DRAMTMG13_t_ccd_mw_MASK (0x3F0000U)
10307#define DDRC_DRAMTMG13_t_ccd_mw_SHIFT (16U)
10308/*! t_ccd_mw - LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write
10309 * command for same bank. When the controller is operating in 1:2 frequency ratio mode, program
10310 * this to (tCCDMW/2) and round it up to the next integer value. Unit: Clocks.
10311 */
10312#define DDRC_DRAMTMG13_t_ccd_mw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_t_ccd_mw_SHIFT)) & DDRC_DRAMTMG13_t_ccd_mw_MASK)
10313#define DDRC_DRAMTMG13_odtloff_MASK (0x7F000000U)
10314#define DDRC_DRAMTMG13_odtloff_SHIFT (24U)
10315/*! odtloff - LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference. When
10316 * the controller is operating in 1:2 frequency ratio mode, program this to (tODTLoff/2) and round
10317 * it up to the next integer value. Unit: Clocks.
10318 */
10319#define DDRC_DRAMTMG13_odtloff(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_odtloff_SHIFT)) & DDRC_DRAMTMG13_odtloff_MASK)
10320/*! @} */
10321
10322/*! @name DRAMTMG14 - SDRAM Timing Register 14 */
10323/*! @{ */
10324#define DDRC_DRAMTMG14_t_xsr_MASK (0xFFFU)
10325#define DDRC_DRAMTMG14_t_xsr_SHIFT (0U)
10326/*! t_xsr - tXSR: Exit Self Refresh to any command. When the controller is operating in 1:2
10327 * frequency ratio mode, program this to the above value divided by 2 and round up to next integer value.
10328 * Note: Used only for mDDR/LPDDR2/LPDDR3/LPDDR4 mode.
10329 */
10330#define DDRC_DRAMTMG14_t_xsr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG14_t_xsr_SHIFT)) & DDRC_DRAMTMG14_t_xsr_MASK)
10331/*! @} */
10332
10333/*! @name DRAMTMG15 - SDRAM Timing Register 15 */
10334/*! @{ */
10335#define DDRC_DRAMTMG15_t_stab_x32_MASK (0xFFU)
10336#define DDRC_DRAMTMG15_t_stab_x32_SHIFT (0U)
10337/*! t_stab_x32 - tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4
10338 * RDIMM : - when exiting power saving mode, if the clock was stopped, after re-enabling it the
10339 * clock must be stable for a time specified by tSTAB - in the case of input clock frequency
10340 * change (DDR4) - after issuing control words that refers to clock timing (Specification: 6us for
10341 * DDR3, 5us for DDR4) When the controller is operating in 1:2 frequency ratio mode, program this to
10342 * recommended value divided by two and round it up to next integer. Unit: Multiples of 32 clock
10343 * cycles.
10344 */
10345#define DDRC_DRAMTMG15_t_stab_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_t_stab_x32_SHIFT)) & DDRC_DRAMTMG15_t_stab_x32_MASK)
10346#define DDRC_DRAMTMG15_en_dfi_lp_t_stab_MASK (0x80000000U)
10347#define DDRC_DRAMTMG15_en_dfi_lp_t_stab_SHIFT (31U)
10348/*! en_dfi_lp_t_stab - Enable DFI tSTAB
10349 * 0b0..Disable using tSTAB when exiting DFI LP
10350 * 0b1..Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is stopping the clock during DFI LP to save maximum power.
10351 */
10352#define DDRC_DRAMTMG15_en_dfi_lp_t_stab(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_en_dfi_lp_t_stab_SHIFT)) & DDRC_DRAMTMG15_en_dfi_lp_t_stab_MASK)
10353/*! @} */
10354
10355/*! @name ZQCTL0 - ZQ Control Register 0 */
10356/*! @{ */
10357#define DDRC_ZQCTL0_t_zq_short_nop_MASK (0x3FFU)
10358#define DDRC_ZQCTL0_t_zq_short_nop_SHIFT (0U)
10359/*! t_zq_short_nop - tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles
10360 * of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM.
10361 * When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and
10362 * round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or
10363 * LPDDR2/LPDDR3/LPDDR4 devices.
10364 */
10365#define DDRC_ZQCTL0_t_zq_short_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_t_zq_short_nop_SHIFT)) & DDRC_ZQCTL0_t_zq_short_nop_MASK)
10366#define DDRC_ZQCTL0_t_zq_long_nop_MASK (0x7FF0000U)
10367#define DDRC_ZQCTL0_t_zq_long_nop_SHIFT (16U)
10368/*! t_zq_long_nop - tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI
10369 * clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is
10370 * issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode: DDR3/DDR4: program
10371 * this to tZQoper/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to
10372 * tZQCL/2 and round it up to the next integer value. LPDDR4: program this to tZQCAL/2 and round it
10373 * up to the next integer value. This is only present for designs supporting DDR3/DDR4 or
10374 * LPDDR2/LPDDR3/LPDDR4 devices.
10375 */
10376#define DDRC_ZQCTL0_t_zq_long_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_t_zq_long_nop_SHIFT)) & DDRC_ZQCTL0_t_zq_long_nop_MASK)
10377#define DDRC_ZQCTL0_dis_mpsmx_zqcl_MASK (0x10000000U)
10378#define DDRC_ZQCTL0_dis_mpsmx_zqcl_SHIFT (28U)
10379/*! dis_mpsmx_zqcl - Do not issue ZQCL command at Maximum Power Save Mode exit if the DDRC_SHARED_AC
10380 * configuration parameter is set. Program it to 1'b1. The software can send ZQCS after exiting
10381 * MPSM mode.
10382 * 0b0..Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode.
10383 * This is only present for designs supporting DDR4 devices.
10384 * 0b1..Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode.
10385 */
10386#define DDRC_ZQCTL0_dis_mpsmx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_mpsmx_zqcl_SHIFT)) & DDRC_ZQCTL0_dis_mpsmx_zqcl_MASK)
10387#define DDRC_ZQCTL0_zq_resistor_shared_MASK (0x20000000U)
10388#define DDRC_ZQCTL0_zq_resistor_shared_SHIFT (29U)
10389/*! zq_resistor_shared - ZQ resistor sharing
10390 * 0b0..ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
10391 * 0b1..Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are
10392 * sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that
10393 * commands to different ranks do not overlap.
10394 */
10395#define DDRC_ZQCTL0_zq_resistor_shared(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_zq_resistor_shared_SHIFT)) & DDRC_ZQCTL0_zq_resistor_shared_MASK)
10396#define DDRC_ZQCTL0_dis_srx_zqcl_MASK (0x40000000U)
10397#define DDRC_ZQCTL0_dis_srx_zqcl_SHIFT (30U)
10398/*! dis_srx_zqcl - Disable ZQCL/MPC
10399 * 0b0..Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable
10400 * when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs supporting
10401 * DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
10402 * 0b1..Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable
10403 * when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode.
10404 */
10405#define DDRC_ZQCTL0_dis_srx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_srx_zqcl_SHIFT)) & DDRC_ZQCTL0_dis_srx_zqcl_MASK)
10406#define DDRC_ZQCTL0_dis_auto_zq_MASK (0x80000000U)
10407#define DDRC_ZQCTL0_dis_auto_zq_SHIFT (31U)
10408/*! dis_auto_zq - Disable Auto ZQCS/MPC
10409 * 0b0..Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024.
10410 * 0b1..Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used
10411 * instead to issue ZQ calibration request from APB module.
10412 */
10413#define DDRC_ZQCTL0_dis_auto_zq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_dis_auto_zq_SHIFT)) & DDRC_ZQCTL0_dis_auto_zq_MASK)
10414/*! @} */
10415
10416/*! @name ZQCTL1 - ZQ Control Register 1 */
10417/*! @{ */
10418#define DDRC_ZQCTL1_t_zq_short_interval_x1024_MASK (0xFFFFFU)
10419#define DDRC_ZQCTL1_t_zq_short_interval_x1024_SHIFT (0U)
10420/*! t_zq_short_interval_x1024 - Average interval to wait between automatically issuing ZQCS (ZQ
10421 * calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices.
10422 * Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 DFI clock cycles. This is only present for designs
10423 * supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
10424 */
10425#define DDRC_ZQCTL1_t_zq_short_interval_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_t_zq_short_interval_x1024_SHIFT)) & DDRC_ZQCTL1_t_zq_short_interval_x1024_MASK)
10426#define DDRC_ZQCTL1_t_zq_reset_nop_MASK (0x3FF00000U)
10427#define DDRC_ZQCTL1_t_zq_reset_nop_SHIFT (20U)
10428/*! t_zq_reset_nop - tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ
10429 * calibration Reset) command is issued to SDRAM. When the controller is operating in 1:2 frequency
10430 * ratio mode, program this to tZQReset/2 and round it up to the next integer value. This is only
10431 * present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
10432 */
10433#define DDRC_ZQCTL1_t_zq_reset_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL1_t_zq_reset_nop_SHIFT)) & DDRC_ZQCTL1_t_zq_reset_nop_MASK)
10434/*! @} */
10435
10436/*! @name ZQCTL2 - ZQ Control Register 2 */
10437/*! @{ */
10438#define DDRC_ZQCTL2_zq_reset_MASK (0x1U)
10439#define DDRC_ZQCTL2_zq_reset_SHIFT (0U)
10440/*! zq_reset - Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset
10441 * operation is complete, the DDRC automatically clears this bit. It is recommended NOT to set this
10442 * signal if in Init, Self-Refresh(except LPDDR4) or SR-Powerdown(LPDDR4) or Deep power-down
10443 * operating modes. This is only present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
10444 */
10445#define DDRC_ZQCTL2_zq_reset(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL2_zq_reset_SHIFT)) & DDRC_ZQCTL2_zq_reset_MASK)
10446/*! @} */
10447
10448/*! @name ZQSTAT - ZQ Status Register */
10449/*! @{ */
10450#define DDRC_ZQSTAT_zq_reset_busy_MASK (0x1U)
10451#define DDRC_ZQSTAT_zq_reset_busy_SHIFT (0U)
10452/*! zq_reset_busy - SoC core may initiate a ZQ Reset operation only if this signal is low. This
10453 * signal goes high in the clock after the DDRC accepts the ZQ Reset request. It goes low when the ZQ
10454 * Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended
10455 * not to perform ZQ Reset commands when this signal is high.
10456 * 0b0..Indicates that the SoC core can initiate a ZQ Reset operation
10457 * 0b1..Indicates that ZQ Reset operation is in progress
10458 */
10459#define DDRC_ZQSTAT_zq_reset_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQSTAT_zq_reset_busy_SHIFT)) & DDRC_ZQSTAT_zq_reset_busy_MASK)
10460/*! @} */
10461
10462/*! @name DFITMG0 - DFI Timing Register 0 */
10463/*! @{ */
10464#define DDRC_DFITMG0_dfi_tphy_wrlat_MASK (0x3FU)
10465#define DDRC_DFITMG0_dfi_tphy_wrlat_SHIFT (0U)
10466/*! dfi_tphy_wrlat - Write latency Number of clocks from the write command to write data enable
10467 * (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY
10468 * specification for correct value.Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be
10469 * necessary to use the adjusted value of CL in the calculation of tphy_wrlat. This is to compensate for
10470 * the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY
10471 * clock cycles, depending on DFITMG0.dfi_wrdata_use_sdr.
10472 */
10473#define DDRC_DFITMG0_dfi_tphy_wrlat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_tphy_wrlat_SHIFT)) & DDRC_DFITMG0_dfi_tphy_wrlat_MASK)
10474#define DDRC_DFITMG0_dfi_tphy_wrdata_MASK (0x3F00U)
10475#define DDRC_DFITMG0_dfi_tphy_wrdata_SHIFT (8U)
10476/*! dfi_tphy_wrdata - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to
10477 * when the associated write data is driven on the dfi_wrdata signal. This corresponds to the
10478 * DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max
10479 * supported value is 8. Unit: DFI clock cycles or DFI PHY clock cycles, depending on
10480 * DFITMG0.dfi_wrdata_use_sdr.
10481 */
10482#define DDRC_DFITMG0_dfi_tphy_wrdata(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_tphy_wrdata_SHIFT)) & DDRC_DFITMG0_dfi_tphy_wrdata_MASK)
10483#define DDRC_DFITMG0_dfi_wrdata_use_sdr_MASK (0x8000U)
10484#define DDRC_DFITMG0_dfi_wrdata_use_sdr_SHIFT (15U)
10485/*! dfi_wrdata_use_sdr - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using
10486 * HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value in DFITMG0.dfi_tphy_wrlat
10487 * is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles Selects whether value in
10488 * DFITMG0.dfi_tphy_wrdata is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles - 0 in terms of
10489 * HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification
10490 * for correct value.
10491 */
10492#define DDRC_DFITMG0_dfi_wrdata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_wrdata_use_sdr_SHIFT)) & DDRC_DFITMG0_dfi_wrdata_use_sdr_MASK)
10493#define DDRC_DFITMG0_dfi_t_rddata_en_MASK (0x7F0000U)
10494#define DDRC_DFITMG0_dfi_t_rddata_en_SHIFT (16U)
10495/*! dfi_t_rddata_en - Time from the assertion of a read command on the DFI interface to the
10496 * assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds
10497 * to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM/LRDIMM, it
10498 * may be necessary to use the adjusted value of CL in the calculation of trddata_en. This is to
10499 * compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or
10500 * DFI PHY clock cycles, depending on DFITMG0.dfi_rddata_use_sdr.
10501 */
10502#define DDRC_DFITMG0_dfi_t_rddata_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_t_rddata_en_SHIFT)) & DDRC_DFITMG0_dfi_t_rddata_en_MASK)
10503#define DDRC_DFITMG0_dfi_rddata_use_sdr_MASK (0x800000U)
10504#define DDRC_DFITMG0_dfi_rddata_use_sdr_SHIFT (23U)
10505/*! dfi_rddata_use_sdr - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated
10506 * using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in
10507 * DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles: - 0 in terms of HDR (DFI
10508 * clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct
10509 * value.
10510 */
10511#define DDRC_DFITMG0_dfi_rddata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_rddata_use_sdr_SHIFT)) & DDRC_DFITMG0_dfi_rddata_use_sdr_MASK)
10512#define DDRC_DFITMG0_dfi_t_ctrl_delay_MASK (0x1F000000U)
10513#define DDRC_DFITMG0_dfi_t_ctrl_delay_SHIFT (24U)
10514/*! dfi_t_ctrl_delay - Specifies the number of DFI clock cycles after an assertion or de-assertion
10515 * of the DFI control signals that the control signals at the PHY-DRAM interface reflect the
10516 * assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing
10517 * parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it
10518 * is necessary to increment this parameter by RDIMM's/LRDIMM's extra cycle of latency in terms
10519 * of DFI clock.
10520 */
10521#define DDRC_DFITMG0_dfi_t_ctrl_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_dfi_t_ctrl_delay_SHIFT)) & DDRC_DFITMG0_dfi_t_ctrl_delay_MASK)
10522/*! @} */
10523
10524/*! @name DFITMG1 - DFI Timing Register 1 */
10525/*! @{ */
10526#define DDRC_DFITMG1_dfi_t_dram_clk_enable_MASK (0x1FU)
10527#define DDRC_DFITMG1_dfi_t_dram_clk_enable_SHIFT (0U)
10528/*! dfi_t_dram_clk_enable - Specifies the number of DFI clock cycles from the de-assertion of the
10529 * dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the
10530 * DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not
10531 * phase aligned, this timing parameter should be rounded up to the next integer value.
10532 */
10533#define DDRC_DFITMG1_dfi_t_dram_clk_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_dram_clk_enable_SHIFT)) & DDRC_DFITMG1_dfi_t_dram_clk_enable_MASK)
10534#define DDRC_DFITMG1_dfi_t_dram_clk_disable_MASK (0x1F00U)
10535#define DDRC_DFITMG1_dfi_t_dram_clk_disable_SHIFT (8U)
10536/*! dfi_t_dram_clk_disable - Specifies the number of DFI clock cycles from the assertion of the
10537 * dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM
10538 * boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned,
10539 * this timing parameter should be rounded up to the next integer value.
10540 */
10541#define DDRC_DFITMG1_dfi_t_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_dram_clk_disable_SHIFT)) & DDRC_DFITMG1_dfi_t_dram_clk_disable_MASK)
10542#define DDRC_DFITMG1_dfi_t_wrdata_delay_MASK (0x1F0000U)
10543#define DDRC_DFITMG1_dfi_t_wrdata_delay_SHIFT (16U)
10544/*! dfi_t_wrdata_delay - Specifies the number of DFI clock cycles between when the dfi_wrdata_en
10545 * signal is asserted and when the corresponding write data transfer is completed on the DRAM bus.
10546 * This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for
10547 * correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI
10548 * 3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be
10549 * programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2
10550 * and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit:
10551 * Clocks
10552 */
10553#define DDRC_DFITMG1_dfi_t_wrdata_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_wrdata_delay_SHIFT)) & DDRC_DFITMG1_dfi_t_wrdata_delay_MASK)
10554#define DDRC_DFITMG1_dfi_t_parin_lat_MASK (0x3000000U)
10555#define DDRC_DFITMG1_dfi_t_parin_lat_SHIFT (24U)
10556/*! dfi_t_parin_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is
10557 * asserted and when the associated dfi_parity_in signal is driven.
10558 */
10559#define DDRC_DFITMG1_dfi_t_parin_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_parin_lat_SHIFT)) & DDRC_DFITMG1_dfi_t_parin_lat_MASK)
10560#define DDRC_DFITMG1_dfi_t_cmd_lat_MASK (0xF0000000U)
10561#define DDRC_DFITMG1_dfi_t_cmd_lat_SHIFT (28U)
10562/*! dfi_t_cmd_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is
10563 * asserted and when the associated command is driven. This field is used for CAL mode, should be
10564 * set to '0' or the value which matches the CAL mode register setting in the DRAM. If the PHY
10565 * can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
10566 */
10567#define DDRC_DFITMG1_dfi_t_cmd_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_dfi_t_cmd_lat_SHIFT)) & DDRC_DFITMG1_dfi_t_cmd_lat_MASK)
10568/*! @} */
10569
10570/*! @name DFILPCFG0 - DFI Low Power Configuration Register 0 */
10571/*! @{ */
10572#define DDRC_DFILPCFG0_dfi_lp_en_pd_MASK (0x1U)
10573#define DDRC_DFILPCFG0_dfi_lp_en_pd_SHIFT (0U)
10574/*! dfi_lp_en_pd - Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled
10575 */
10576#define DDRC_DFILPCFG0_dfi_lp_en_pd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_pd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_pd_MASK)
10577#define DDRC_DFILPCFG0_dfi_lp_wakeup_pd_MASK (0xF0U)
10578#define DDRC_DFILPCFG0_dfi_lp_wakeup_pd_SHIFT (4U)
10579/*! dfi_lp_wakeup_pd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down
10580 * mode is entered. Determines the DFI's tlp_wakeup time:
10581 * 0b0000..16 cycles
10582 * 0b0001..32 cycles
10583 * 0b0010..64 cycles
10584 * 0b0011..128 cycles
10585 * 0b0100..256 cycles
10586 * 0b0101..512 cycles
10587 * 0b0110..1024 cycles
10588 * 0b0111..2048 cycles
10589 * 0b1000..4096 cycles
10590 * 0b1001..8192 cycles
10591 * 0b1010..16384 cycles
10592 * 0b1011..32768 cycles
10593 * 0b1100..65536 cycles
10594 * 0b1101..131072 cycles
10595 * 0b1110..262144 cycles
10596 * 0b1111..Unlimited cycles
10597 */
10598#define DDRC_DFILPCFG0_dfi_lp_wakeup_pd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_pd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_pd_MASK)
10599#define DDRC_DFILPCFG0_dfi_lp_en_sr_MASK (0x100U)
10600#define DDRC_DFILPCFG0_dfi_lp_en_sr_SHIFT (8U)
10601/*! dfi_lp_en_sr - Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled
10602 * 0b0..Disabled
10603 * 0b1..Enabled
10604 */
10605#define DDRC_DFILPCFG0_dfi_lp_en_sr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_sr_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_sr_MASK)
10606#define DDRC_DFILPCFG0_dfi_lp_wakeup_sr_MASK (0xF000U)
10607#define DDRC_DFILPCFG0_dfi_lp_wakeup_sr_SHIFT (12U)
10608/*! dfi_lp_wakeup_sr - Value in DFI clpck cycles to drive on dfi_lp_wakeup signal when Self Refresh
10609 * mode is entered. Determines the DFI's tlp_wakeup time:
10610 * 0b0000..16 cycles
10611 * 0b0001..32 cycles
10612 * 0b0010..64 cycles
10613 * 0b0011..128 cycles
10614 * 0b0100..256 cycles
10615 * 0b0101..512 cycles
10616 * 0b0110..1024 cycles
10617 * 0b0111..2048 cycles
10618 * 0b1000..4096 cycles
10619 * 0b1001..8192 cycles
10620 * 0b1010..16384 cycles
10621 * 0b1011..32768 cycles
10622 * 0b1100..65536 cycles
10623 * 0b1101..131072 cycles
10624 * 0b1110..262144 cycles
10625 * 0b1111..Unlimited cycles
10626 */
10627#define DDRC_DFILPCFG0_dfi_lp_wakeup_sr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_sr_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_sr_MASK)
10628#define DDRC_DFILPCFG0_dfi_lp_en_dpd_MASK (0x10000U)
10629#define DDRC_DFILPCFG0_dfi_lp_en_dpd_SHIFT (16U)
10630/*! dfi_lp_en_dpd - Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. -
10631 * 0 - Disabled - 1 - Enabled This is only present for designs supporting mDDR or LPDDR2/LPDDR3
10632 * devices.
10633 */
10634#define DDRC_DFILPCFG0_dfi_lp_en_dpd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_en_dpd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_en_dpd_MASK)
10635#define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_MASK (0xF00000U)
10636#define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_SHIFT (20U)
10637/*! dfi_lp_wakeup_dpd - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power
10638 * Down mode is entered. Determines the DFI's tlp_wakeup time: This is only present for designs
10639 * supporting mDDR or LPDDR2/LPDDR3 devices.
10640 * 0b0000..16 cycles
10641 * 0b0001..32 cycles
10642 * 0b0010..64 cycles
10643 * 0b0011..128 cycles
10644 * 0b0100..256 cycles
10645 * 0b0101..512 cycles
10646 * 0b0110..1024 cycles
10647 * 0b0111..2048 cycles
10648 * 0b1000..4096 cycles
10649 * 0b1001..8192 cycles
10650 * 0b1010..16384 cycles
10651 * 0b1011..32768 cycles
10652 * 0b1100..65536 cycles
10653 * 0b1101..131072 cycles
10654 * 0b1110..262144 cycles
10655 * 0b1111..Unlimited cycles
10656 */
10657#define DDRC_DFILPCFG0_dfi_lp_wakeup_dpd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_SHIFT)) & DDRC_DFILPCFG0_dfi_lp_wakeup_dpd_MASK)
10658#define DDRC_DFILPCFG0_dfi_tlp_resp_MASK (0x1F000000U)
10659#define DDRC_DFILPCFG0_dfi_tlp_resp_SHIFT (24U)
10660/*! dfi_tlp_resp - Setting in DFI clock cycles for DFI's tlp_resp time. Same value is used for both
10661 * Power Down, Self Refresh, Deep Power Down and Maximum Power Saving modes. DFI 2.1
10662 * specification onwards, recommends using a fixed value of 7 always.
10663 */
10664#define DDRC_DFILPCFG0_dfi_tlp_resp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG0_dfi_tlp_resp_SHIFT)) & DDRC_DFILPCFG0_dfi_tlp_resp_MASK)
10665/*! @} */
10666
10667/*! @name DFILPCFG1 - DFI Low Power Configuration Register 1 */
10668/*! @{ */
10669#define DDRC_DFILPCFG1_dfi_lp_en_mpsm_MASK (0x1U)
10670#define DDRC_DFILPCFG1_dfi_lp_en_mpsm_SHIFT (0U)
10671/*! dfi_lp_en_mpsm - Enables DFI Low Power interface handshaking during Maximum Power Saving Mode
10672 * Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting DDR4
10673 * devices.
10674 */
10675#define DDRC_DFILPCFG1_dfi_lp_en_mpsm(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG1_dfi_lp_en_mpsm_SHIFT)) & DDRC_DFILPCFG1_dfi_lp_en_mpsm_MASK)
10676#define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_MASK (0xF0U)
10677#define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_SHIFT (4U)
10678/*! dfi_lp_wakeup_mpsm - Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum
10679 * Power Saving Mode is entered. Determines the DFI's tlp_wakeup time:
10680 * 0b0000..16 cycles
10681 * 0b0001..32 cycles
10682 * 0b0010..64 cycles
10683 * 0b0011..128 cycles
10684 * 0b0100..256 cycles
10685 * 0b0101..512 cycles
10686 * 0b0110..1024 cycles
10687 * 0b0111..2048 cycles
10688 * 0b1000..4096 cycles
10689 * 0b1001..8192 cycles
10690 * 0b1010..16384 cycles
10691 * 0b1011..32768 cycles
10692 * 0b1100..65536 cycles
10693 * 0b1101..131072 cycles
10694 * 0b1110..262144 cycles
10695 * 0b1111..Unlimited cycles
10696 */
10697#define DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_SHIFT)) & DDRC_DFILPCFG1_dfi_lp_wakeup_mpsm_MASK)
10698/*! @} */
10699
10700/*! @name DFIUPD0 - DFI Update Register 0 */
10701/*! @{ */
10702#define DDRC_DFIUPD0_dfi_t_ctrlup_min_MASK (0x3FFU)
10703#define DDRC_DFIUPD0_dfi_t_ctrlup_min_SHIFT (0U)
10704/*! dfi_t_ctrlup_min - Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req
10705 * signal must be asserted. The DDRC expects the PHY to respond within this time. If the PHY does
10706 * not respond, the DDRC will de-assert dfi_ctrlupd_req after dfi_t_ctrlup_min + 2 cycles. Lowest
10707 * value to assign to this variable is 0x3.
10708 */
10709#define DDRC_DFIUPD0_dfi_t_ctrlup_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dfi_t_ctrlup_min_SHIFT)) & DDRC_DFIUPD0_dfi_t_ctrlup_min_MASK)
10710#define DDRC_DFIUPD0_dfi_t_ctrlup_max_MASK (0x3FF0000U)
10711#define DDRC_DFIUPD0_dfi_t_ctrlup_max_SHIFT (16U)
10712/*! dfi_t_ctrlup_max - Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req
10713 * signal can assert. Lowest value to assign to this variable is 0x40.
10714 */
10715#define DDRC_DFIUPD0_dfi_t_ctrlup_max(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dfi_t_ctrlup_max_SHIFT)) & DDRC_DFIUPD0_dfi_t_ctrlup_max_MASK)
10716#define DDRC_DFIUPD0_ctrlupd_pre_srx_MASK (0x20000000U)
10717#define DDRC_DFIUPD0_ctrlupd_pre_srx_SHIFT (29U)
10718/*! ctrlupd_pre_srx - Selects dfi_ctrlupd_req requirements at SRX: - 0 : send ctrlupd after SRX - 1
10719 * : send ctrlupd before SRX If DFIUPD0.dis_auto_ctrlupd_srx=1, this register has no impact,
10720 * because no dfi_ctrlupd_req will be issued when SRX.
10721 * 0b0..send ctrlupd after SRX
10722 * 0b1..send ctrlupd before SRX
10723 */
10724#define DDRC_DFIUPD0_ctrlupd_pre_srx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_ctrlupd_pre_srx_SHIFT)) & DDRC_DFIUPD0_ctrlupd_pre_srx_MASK)
10725#define DDRC_DFIUPD0_dis_auto_ctrlupd_srx_MASK (0x40000000U)
10726#define DDRC_DFIUPD0_dis_auto_ctrlupd_srx_SHIFT (30U)
10727/*! dis_auto_ctrlupd_srx - Auto ctrlupd request generation
10728 * 0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC at self-refresh exit.
10729 * 0b0..DDRC issues a dfi_ctrlupd_req before or after exiting self-refresh, depending on DFIUPD0.ctrlupd_pre_srx.
10730 */
10731#define DDRC_DFIUPD0_dis_auto_ctrlupd_srx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dis_auto_ctrlupd_srx_SHIFT)) & DDRC_DFIUPD0_dis_auto_ctrlupd_srx_MASK)
10732#define DDRC_DFIUPD0_dis_auto_ctrlupd_MASK (0x80000000U)
10733#define DDRC_DFIUPD0_dis_auto_ctrlupd_SHIFT (31U)
10734/*! dis_auto_ctrlupd - automatic dfi_ctrlupd_req generation by the DDRC
10735 * 0b0..DDRC issues dfi_ctrlupd_req periodically.
10736 * 0b1..disable the automatic dfi_ctrlupd_req generation by the DDRC. The core must issue the dfi_ctrlupd_req
10737 * signal using register reg_ddrc_ctrlupd.
10738 */
10739#define DDRC_DFIUPD0_dis_auto_ctrlupd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD0_dis_auto_ctrlupd_SHIFT)) & DDRC_DFIUPD0_dis_auto_ctrlupd_MASK)
10740/*! @} */
10741
10742/*! @name DFIUPD1 - DFI Update Register 1 */
10743/*! @{ */
10744#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_MASK (0xFFU)
10745#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_SHIFT (0U)
10746/*! dfi_t_ctrlupd_interval_max_x1024 - This is the maximum amount of time between DDRC initiated DFI
10747 * update requests. This timer resets with each update request; when the timer expires
10748 * dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this
10749 * idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used
10750 * to reset PHY FIFO pointers in case of data capture errors. Updates are required to maintain
10751 * calibration over PVT, but frequent updates may impact performance. Minimum allowed value for
10752 * this field is 1. Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be
10753 * greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x1024. Unit: 1024 DFI clock cycles
10754 */
10755#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_SHIFT)) & DDRC_DFIUPD1_dfi_t_ctrlupd_interval_max_x1024_MASK)
10756#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_MASK (0xFF0000U)
10757#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_SHIFT (16U)
10758/*! dfi_t_ctrlupd_interval_min_x1024 - This is the minimum amount of time between DDRC initiated DFI
10759 * update requests (which is executed whenever the DDRC is idle). Set this number higher to
10760 * reduce the frequency of update requests, which can have a small impact on the latency of the first
10761 * read request when the DDRC is idle. Minimum allowed value for this field is 1. Unit: 1024 DFI
10762 * clock cycles
10763 */
10764#define DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_SHIFT)) & DDRC_DFIUPD1_dfi_t_ctrlupd_interval_min_x1024_MASK)
10765/*! @} */
10766
10767/*! @name DFIUPD2 - DFI Update Register 2 */
10768/*! @{ */
10769#define DDRC_DFIUPD2_dfi_phyupd_en_MASK (0x80000000U)
10770#define DDRC_DFIUPD2_dfi_phyupd_en_SHIFT (31U)
10771/*! dfi_phyupd_en - Enables the support for acknowledging PHY-initiated updates:
10772 * 0b0..Disabled
10773 * 0b1..Enabled
10774 */
10775#define DDRC_DFIUPD2_dfi_phyupd_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIUPD2_dfi_phyupd_en_SHIFT)) & DDRC_DFIUPD2_dfi_phyupd_en_MASK)
10776/*! @} */
10777
10778/*! @name DFIMISC - DFI Miscellaneous Control Register */
10779/*! @{ */
10780#define DDRC_DFIMISC_dfi_init_complete_en_MASK (0x1U)
10781#define DDRC_DFIMISC_dfi_init_complete_en_SHIFT (0U)
10782/*! dfi_init_complete_en - PHY initialization complete enable signal. When asserted the
10783 * dfi_init_complete signal can be used to trigger SDRAM initialisation
10784 */
10785#define DDRC_DFIMISC_dfi_init_complete_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_init_complete_en_SHIFT)) & DDRC_DFIMISC_dfi_init_complete_en_MASK)
10786#define DDRC_DFIMISC_phy_dbi_mode_MASK (0x2U)
10787#define DDRC_DFIMISC_phy_dbi_mode_SHIFT (1U)
10788/*! phy_dbi_mode - DBI implemented in DDRC or PHY. Present only in designs configured to support DDR4 and LPDDR4.
10789 * 0b0..DDRC implements DBI functionality.
10790 * 0b1..PHY implements DBI functionality.
10791 */
10792#define DDRC_DFIMISC_phy_dbi_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_phy_dbi_mode_SHIFT)) & DDRC_DFIMISC_phy_dbi_mode_MASK)
10793#define DDRC_DFIMISC_dfi_data_cs_polarity_MASK (0x4U)
10794#define DDRC_DFIMISC_dfi_data_cs_polarity_SHIFT (2U)
10795/*! dfi_data_cs_polarity - Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals.
10796 * 0b0..Signals are active low
10797 * 0b1..Signals are active high
10798 */
10799#define DDRC_DFIMISC_dfi_data_cs_polarity(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_data_cs_polarity_SHIFT)) & DDRC_DFIMISC_dfi_data_cs_polarity_MASK)
10800#define DDRC_DFIMISC_ctl_idle_en_MASK (0x10U)
10801#define DDRC_DFIMISC_ctl_idle_en_SHIFT (4U)
10802/*! ctl_idle_en - Enables support of ctl_idle signal, which is non-DFI related pin specific to
10803 * certain PHYs. See signal description of ctl_idle signal for further details of ctl_idle
10804 * functionality.
10805 */
10806#define DDRC_DFIMISC_ctl_idle_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_ctl_idle_en_SHIFT)) & DDRC_DFIMISC_ctl_idle_en_MASK)
10807#define DDRC_DFIMISC_dfi_init_start_MASK (0x20U)
10808#define DDRC_DFIMISC_dfi_init_start_SHIFT (5U)
10809/*! dfi_init_start - PHY init start request signal.When asserted it triggers the PHY init start request
10810 */
10811#define DDRC_DFIMISC_dfi_init_start(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_init_start_SHIFT)) & DDRC_DFIMISC_dfi_init_start_MASK)
10812#define DDRC_DFIMISC_dfi_frequency_MASK (0x1F00U)
10813#define DDRC_DFIMISC_dfi_frequency_SHIFT (8U)
10814/*! dfi_frequency - Indicates the operating frequency of the system. The number of supported
10815 * frequencies and the mapping of signal values to clock frequencies are defined by the PHY.
10816 */
10817#define DDRC_DFIMISC_dfi_frequency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFIMISC_dfi_frequency_SHIFT)) & DDRC_DFIMISC_dfi_frequency_MASK)
10818/*! @} */
10819
10820/*! @name DFITMG2 - DFI Timing Register 2 */
10821/*! @{ */
10822#define DDRC_DFITMG2_dfi_tphy_wrcslat_MASK (0x3FU)
10823#define DDRC_DFITMG2_dfi_tphy_wrcslat_SHIFT (0U)
10824/*! dfi_tphy_wrcslat - Number of DFI PHY clock cycles between when a write command is sent on the
10825 * DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds
10826 * to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.
10827 */
10828#define DDRC_DFITMG2_dfi_tphy_wrcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_dfi_tphy_wrcslat_SHIFT)) & DDRC_DFITMG2_dfi_tphy_wrcslat_MASK)
10829#define DDRC_DFITMG2_dfi_tphy_rdcslat_MASK (0x7F00U)
10830#define DDRC_DFITMG2_dfi_tphy_rdcslat_SHIFT (8U)
10831/*! dfi_tphy_rdcslat - Number of DFI PHY clock cycles between when a read command is sent on the DFI
10832 * control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds
10833 * to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.
10834 */
10835#define DDRC_DFITMG2_dfi_tphy_rdcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_dfi_tphy_rdcslat_SHIFT)) & DDRC_DFITMG2_dfi_tphy_rdcslat_MASK)
10836/*! @} */
10837
10838/*! @name DFITMG3 - DFI Timing Register 3 */
10839/*! @{ */
10840#define DDRC_DFITMG3_dfi_t_geardown_delay_MASK (0x1FU)
10841#define DDRC_DFITMG3_dfi_t_geardown_delay_SHIFT (0U)
10842/*! dfi_t_geardown_delay - The delay from dfi_geardown_en assertion to the time of the PHY being
10843 * ready to receive commands. Refer to PHY specification for correct value. When the controller is
10844 * operating in 1:2 frequency ratio mode, program this to (tgeardown_delay/2) and round it up to
10845 * the next integer value. Unit: Clocks
10846 */
10847#define DDRC_DFITMG3_dfi_t_geardown_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG3_dfi_t_geardown_delay_SHIFT)) & DDRC_DFITMG3_dfi_t_geardown_delay_MASK)
10848/*! @} */
10849
10850/*! @name DFISTAT - DFI Status Register */
10851/*! @{ */
10852#define DDRC_DFISTAT_dfi_init_complete_MASK (0x1U)
10853#define DDRC_DFISTAT_dfi_init_complete_SHIFT (0U)
10854/*! dfi_init_complete - The status flag register which announces when the DFI initialization has
10855 * been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete
10856 * flag is polled to know when the initialization is done.
10857 */
10858#define DDRC_DFISTAT_dfi_init_complete(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFISTAT_dfi_init_complete_SHIFT)) & DDRC_DFISTAT_dfi_init_complete_MASK)
10859#define DDRC_DFISTAT_dfi_lp_ack_MASK (0x2U)
10860#define DDRC_DFISTAT_dfi_lp_ack_SHIFT (1U)
10861/*! dfi_lp_ack - Stores the value of the dfi_lp_ack input to the controller.
10862 */
10863#define DDRC_DFISTAT_dfi_lp_ack(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFISTAT_dfi_lp_ack_SHIFT)) & DDRC_DFISTAT_dfi_lp_ack_MASK)
10864/*! @} */
10865
10866/*! @name DBICTL - DM/DBI Control Register */
10867/*! @{ */
10868#define DDRC_DBICTL_dm_en_MASK (0x1U)
10869#define DDRC_DBICTL_dm_en_SHIFT (0U)
10870/*! dm_en - DM enable signal in DDRC. This signal must be set the same logical value as DRAM's mode
10871 * register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal
10872 * must be set to 0. - LPDDR4: Set this to inverted value of MR13[5] which is opposite polarity
10873 * from this signal
10874 * 0b0..DM is disabled
10875 * 0b1..DM is enabled
10876 */
10877#define DDRC_DBICTL_dm_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_dm_en_SHIFT)) & DDRC_DBICTL_dm_en_MASK)
10878#define DDRC_DBICTL_wr_dbi_en_MASK (0x2U)
10879#define DDRC_DBICTL_wr_dbi_en_SHIFT (1U)
10880/*! wr_dbi_en - This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A11.
10881 * When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]
10882 * 0b0..Write DBI is disabled
10883 * 0b1..Write DBI is enabled.
10884 */
10885#define DDRC_DBICTL_wr_dbi_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_wr_dbi_en_SHIFT)) & DDRC_DBICTL_wr_dbi_en_MASK)
10886#define DDRC_DBICTL_rd_dbi_en_MASK (0x4U)
10887#define DDRC_DBICTL_rd_dbi_en_SHIFT (2U)
10888/*! rd_dbi_en - Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is
10889 * enabled. This signal must be set the same value as DRAM's mode register. - DDR4: MR5 bit A12. When
10890 * x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]
10891 */
10892#define DDRC_DBICTL_rd_dbi_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBICTL_rd_dbi_en_SHIFT)) & DDRC_DBICTL_rd_dbi_en_MASK)
10893/*! @} */
10894
10895/*! @name ADDRMAP0 - Address Map Register 0 */
10896/*! @{ */
10897#define DDRC_ADDRMAP0_addrmap_cs_bit0_MASK (0x1FU)
10898#define DDRC_ADDRMAP0_addrmap_cs_bit0_SHIFT (0U)
10899/*! addrmap_cs_bit0 - Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 28,
10900 * and 31 Internal Base: 6 The selected HIF address bit is determined by adding the internal base
10901 * to the value of this field. If set to 31, rank address bit 0 is set to 0.
10902 */
10903#define DDRC_ADDRMAP0_addrmap_cs_bit0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP0_addrmap_cs_bit0_SHIFT)) & DDRC_ADDRMAP0_addrmap_cs_bit0_MASK)
10904/*! @} */
10905
10906/*! @name ADDRMAP1 - Address Map Register 1 */
10907/*! @{ */
10908#define DDRC_ADDRMAP1_addrmap_bank_b0_MASK (0x1FU)
10909#define DDRC_ADDRMAP1_addrmap_bank_b0_SHIFT (0U)
10910/*! addrmap_bank_b0 - Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 31
10911 * Internal Base: 2 The selected HIF address bit for each of the bank address bits is determined
10912 * by adding the internal base to the value of this field.
10913 */
10914#define DDRC_ADDRMAP1_addrmap_bank_b0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b0_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b0_MASK)
10915#define DDRC_ADDRMAP1_addrmap_bank_b1_MASK (0x1F00U)
10916#define DDRC_ADDRMAP1_addrmap_bank_b1_SHIFT (8U)
10917/*! addrmap_bank_b1 - Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 31
10918 * Internal Base: 3 The selected HIF address bit for each of the bank address bits is determined
10919 * by adding the internal base to the value of this field.
10920 */
10921#define DDRC_ADDRMAP1_addrmap_bank_b1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b1_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b1_MASK)
10922#define DDRC_ADDRMAP1_addrmap_bank_b2_MASK (0x1F0000U)
10923#define DDRC_ADDRMAP1_addrmap_bank_b2_SHIFT (16U)
10924/*! addrmap_bank_b2 - Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 30
10925 * and 31 Internal Base: 4 The selected HIF address bit is determined by adding the internal base
10926 * to the value of this field. If set to 31, bank address bit 2 is set to 0.
10927 */
10928#define DDRC_ADDRMAP1_addrmap_bank_b2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP1_addrmap_bank_b2_SHIFT)) & DDRC_ADDRMAP1_addrmap_bank_b2_MASK)
10929/*! @} */
10930
10931/*! @name ADDRMAP2 - Address Map Register 2 */
10932/*! @{ */
10933#define DDRC_ADDRMAP2_addrmap_col_b2_MASK (0xFU)
10934#define DDRC_ADDRMAP2_addrmap_col_b2_SHIFT (0U)
10935/*! addrmap_col_b2 - - Full bus width mode: Selects the HIF address bit used as column address bit
10936 * 2. - Half bus width mode: Selects the HIF address bit used as column address bit 3. - Quarter
10937 * bus width mode: Selects the HIF address bit used as column address bit 4. Valid Range: 0 to 7
10938 * Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the
10939 * value of this field. Note, if DDRC_INCL_ARB=1 and MEMC_BURST_LENGTH=8, it is required to
10940 * program this to 0 unless: - in Half or Quarter bus width (MSTR.data_bus_width!=00) and -
10941 * PCCFG.bl_exp_mode==1 and either - In DDR4 and ADDRMAP8.addrmap_bg_b0==0 or - In LPDDR4 and
10942 * ADDRMAP1.addrmap_bank_b0==0 If DDRC_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to
10943 * 0 unless: - in Half or Quarter bus width (MSTR.data_bus_width!=00) and - PCCFG.bl_exp_mode==1
10944 * and - In DDR4 and ADDRMAP8.addrmap_bg_b0==0 Otherwise, if MEMC_BURST_LENGTH=8 and Full Bus
10945 * Width (MSTR.data_bus_width==00), it is recommended to program this to 0 so that HIF[2] maps to
10946 * column address bit 2. If MEMC_BURST_LENGTH=16 and Full Bus Width (MSTR.data_bus_width==00), it
10947 * is recommended to program this to 0 so that HIF[2] maps to column address bit 2. If
10948 * MEMC_BURST_LENGTH=16 and Half Bus Width (MSTR.data_bus_width==01), it is recommended to program this to 0
10949 * so that HIF[2] maps to column address bit 3.
10950 */
10951#define DDRC_ADDRMAP2_addrmap_col_b2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b2_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b2_MASK)
10952#define DDRC_ADDRMAP2_addrmap_col_b3_MASK (0xF00U)
10953#define DDRC_ADDRMAP2_addrmap_col_b3_SHIFT (8U)
10954/*! addrmap_col_b3 - - Full bus width mode: Selects the HIF address bit used as column address bit
10955 * 3. - Half bus width mode: Selects the HIF address bit used as column address bit 4. - Quarter
10956 * bus width mode: Selects the HIF address bit used as column address bit 5. Valid Range: 0 to 7
10957 * Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the
10958 * value of this field. Note, if DDRC_INCL_ARB=1, MEMC_BURST_LENGTH=16, Full bus width
10959 * (MSTR.data_bus_width=00) and BL16 (MSTR.burst_rdwr=1000), it is recommended to program this to 0.
10960 */
10961#define DDRC_ADDRMAP2_addrmap_col_b3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b3_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b3_MASK)
10962#define DDRC_ADDRMAP2_addrmap_col_b4_MASK (0xF0000U)
10963#define DDRC_ADDRMAP2_addrmap_col_b4_SHIFT (16U)
10964/*! addrmap_col_b4 - - Full bus width mode: Selects the HIF address bit used as column address bit
10965 * 4. - Half bus width mode: Selects the HIF address bit used as column address bit 5. - Quarter
10966 * bus width mode: Selects the HIF address bit used as column address bit 6. Valid Range: 0 to 7,
10967 * and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base
10968 * to the value of this field. If set to 15, this column address bit is set to 0.
10969 */
10970#define DDRC_ADDRMAP2_addrmap_col_b4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b4_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b4_MASK)
10971#define DDRC_ADDRMAP2_addrmap_col_b5_MASK (0xF000000U)
10972#define DDRC_ADDRMAP2_addrmap_col_b5_SHIFT (24U)
10973/*! addrmap_col_b5 - - Full bus width mode: Selects the HIF address bit used as column address bit
10974 * 5. - Half bus width mode: Selects the HIF address bit used as column address bit 6. - Quarter
10975 * bus width mode: Selects the HIF address bit used as column address bit 7 . Valid Range: 0 to 7,
10976 * and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal
10977 * base to the value of this field. If set to 15, this column address bit is set to 0.
10978 */
10979#define DDRC_ADDRMAP2_addrmap_col_b5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP2_addrmap_col_b5_SHIFT)) & DDRC_ADDRMAP2_addrmap_col_b5_MASK)
10980/*! @} */
10981
10982/*! @name ADDRMAP3 - Address Map Register 3 */
10983/*! @{ */
10984#define DDRC_ADDRMAP3_addrmap_col_b6_MASK (0xFU)
10985#define DDRC_ADDRMAP3_addrmap_col_b6_SHIFT (0U)
10986/*! addrmap_col_b6 - - Full bus width mode: Selects the HIF address bit used as column address bit
10987 * 6. - Half bus width mode: Selects the HIF address bit used as column address bit 7. - Quarter
10988 * bus width mode: Selects the HIF address bit used as column address bit 8. Valid Range: 0 to 7,
10989 * and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base
10990 * to the value of this field. If set to 15, this column address bit is set to 0.
10991 */
10992#define DDRC_ADDRMAP3_addrmap_col_b6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b6_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b6_MASK)
10993#define DDRC_ADDRMAP3_addrmap_col_b7_MASK (0xF00U)
10994#define DDRC_ADDRMAP3_addrmap_col_b7_SHIFT (8U)
10995/*! addrmap_col_b7 - - Full bus width mode: Selects the HIF address bit used as column address bit
10996 * 7. - Half bus width mode: Selects the HIF address bit used as column address bit 8. - Quarter
10997 * bus width mode: Selects the HIF address bit used as column address bit 9. Valid Range: 0 to 7,
10998 * and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base
10999 * to the value of this field. If set to 15, this column address bit is set to 0.
11000 */
11001#define DDRC_ADDRMAP3_addrmap_col_b7(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b7_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b7_MASK)
11002#define DDRC_ADDRMAP3_addrmap_col_b8_MASK (0xF0000U)
11003#define DDRC_ADDRMAP3_addrmap_col_b8_SHIFT (16U)
11004/*! addrmap_col_b8 - - Full bus width mode: Selects the HIF address bit used as column address bit
11005 * 8. - Half bus width mode: Selects the HIF address bit used as column address bit 9. - Quarter
11006 * bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3
11007 * mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined
11008 * by adding the internal base to the value of this field. If set to 15, this column address bit
11009 * is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for
11010 * indicating auto-precharge, and hence no source address bit can be mapped to column address
11011 * bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence
11012 * column bit 10 is used.
11013 */
11014#define DDRC_ADDRMAP3_addrmap_col_b8(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b8_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b8_MASK)
11015#define DDRC_ADDRMAP3_addrmap_col_b9_MASK (0xF000000U)
11016#define DDRC_ADDRMAP3_addrmap_col_b9_SHIFT (24U)
11017/*! addrmap_col_b9 - - Full bus width mode: Selects the HIF address bit used as column address bit
11018 * 9. - Half bus width mode: Selects the HIF address bit used as column address bit 11 (10 in
11019 * LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as column address
11020 * bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected
11021 * HIF address bit is determined by adding the internal base to the value of this field. If set to
11022 * 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column
11023 * address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be
11024 * mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for
11025 * auto-precharge in the CA bus and hence column bit 10 is used.
11026 */
11027#define DDRC_ADDRMAP3_addrmap_col_b9(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP3_addrmap_col_b9_SHIFT)) & DDRC_ADDRMAP3_addrmap_col_b9_MASK)
11028/*! @} */
11029
11030/*! @name ADDRMAP4 - Address Map Register 4 */
11031/*! @{ */
11032#define DDRC_ADDRMAP4_addrmap_col_b10_MASK (0xFU)
11033#define DDRC_ADDRMAP4_addrmap_col_b10_SHIFT (0U)
11034/*! addrmap_col_b10 - - Full bus width mode: Selects the HIF address bit used as column address bit
11035 * 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width mode: Selects the HIF address bit used as
11036 * column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED. To make it
11037 * unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF
11038 * address bit is determined by adding the internal base to the value of this field. If set to
11039 * 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column
11040 * address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be
11041 * mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge
11042 * in the CA bus and hence column bit 10 is used.
11043 */
11044#define DDRC_ADDRMAP4_addrmap_col_b10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP4_addrmap_col_b10_SHIFT)) & DDRC_ADDRMAP4_addrmap_col_b10_MASK)
11045#define DDRC_ADDRMAP4_addrmap_col_b11_MASK (0xF00U)
11046#define DDRC_ADDRMAP4_addrmap_col_b11_SHIFT (8U)
11047/*! addrmap_col_b11 - - Full bus width mode: Selects the HIF address bit used as column address bit
11048 * 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width mode: Unused. To make it unused, this should
11049 * be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must be tied to
11050 * 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by
11051 * adding the internal base to the value of this field. If set to 15, this column address bit is
11052 * set to 0. Note: Per JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for
11053 * indicating auto-precharge, and hence no source address bit can be mapped to column address bit
11054 * 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column
11055 * bit 10 is used.
11056 */
11057#define DDRC_ADDRMAP4_addrmap_col_b11(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP4_addrmap_col_b11_SHIFT)) & DDRC_ADDRMAP4_addrmap_col_b11_MASK)
11058/*! @} */
11059
11060/*! @name ADDRMAP5 - Address Map Register 5 */
11061/*! @{ */
11062#define DDRC_ADDRMAP5_addrmap_row_b0_MASK (0xFU)
11063#define DDRC_ADDRMAP5_addrmap_row_b0_SHIFT (0U)
11064/*! addrmap_row_b0 - Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11
11065 * Internal Base: 6 The selected HIF address bit for each of the row address bits is determined by
11066 * adding the internal base to the value of this field.
11067 */
11068#define DDRC_ADDRMAP5_addrmap_row_b0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b0_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b0_MASK)
11069#define DDRC_ADDRMAP5_addrmap_row_b1_MASK (0xF00U)
11070#define DDRC_ADDRMAP5_addrmap_row_b1_SHIFT (8U)
11071/*! addrmap_row_b1 - Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11
11072 * Internal Base: 7 The selected HIF address bit for each of the row address bits is determined by
11073 * adding the internal base to the value of this field.
11074 */
11075#define DDRC_ADDRMAP5_addrmap_row_b1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b1_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b1_MASK)
11076#define DDRC_ADDRMAP5_addrmap_row_b2_10_MASK (0xF0000U)
11077#define DDRC_ADDRMAP5_addrmap_row_b2_10_SHIFT (16U)
11078/*! addrmap_row_b2_10 - Selects the HIF address bits used as row address bits 2 to 10. Valid Range:
11079 * 0 to 11, and 15 Internal Base: 8 (for row address bit 2), 9 (for row address bit 3), 10 (for
11080 * row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF address bit
11081 * for each of the row address bits is determined by adding the internal base to the value of this
11082 * field. When value 15 is used the values of row address bits 2 to 10 are defined by registers
11083 * ADDRMAP9, ADDRMAP10, ADDRMAP11.
11084 */
11085#define DDRC_ADDRMAP5_addrmap_row_b2_10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b2_10_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b2_10_MASK)
11086#define DDRC_ADDRMAP5_addrmap_row_b11_MASK (0xF000000U)
11087#define DDRC_ADDRMAP5_addrmap_row_b11_SHIFT (24U)
11088/*! addrmap_row_b11 - Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11,
11089 * and 15 Internal Base: 17 The selected HIF address bit is determined by adding the internal
11090 * base to the value of this field. If set to 15, row address bit 11 is set to 0.
11091 */
11092#define DDRC_ADDRMAP5_addrmap_row_b11(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP5_addrmap_row_b11_SHIFT)) & DDRC_ADDRMAP5_addrmap_row_b11_MASK)
11093/*! @} */
11094
11095/*! @name ADDRMAP6 - Address Map Register 6 */
11096/*! @{ */
11097#define DDRC_ADDRMAP6_addrmap_row_b12_MASK (0xFU)
11098#define DDRC_ADDRMAP6_addrmap_row_b12_SHIFT (0U)
11099/*! addrmap_row_b12 - Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11,
11100 * and 15 Internal Base: 18 The selected HIF address bit is determined by adding the internal
11101 * base to the value of this field. If set to 15, row address bit 12 is set to 0.
11102 */
11103#define DDRC_ADDRMAP6_addrmap_row_b12(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b12_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b12_MASK)
11104#define DDRC_ADDRMAP6_addrmap_row_b13_MASK (0xF00U)
11105#define DDRC_ADDRMAP6_addrmap_row_b13_SHIFT (8U)
11106/*! addrmap_row_b13 - Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11,
11107 * and 15 Internal Base: 19 The selected HIF address bit is determined by adding the internal
11108 * base to the value of this field. If set to 15, row address bit 13 is set to 0.
11109 */
11110#define DDRC_ADDRMAP6_addrmap_row_b13(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b13_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b13_MASK)
11111#define DDRC_ADDRMAP6_addrmap_row_b14_MASK (0xF0000U)
11112#define DDRC_ADDRMAP6_addrmap_row_b14_SHIFT (16U)
11113/*! addrmap_row_b14 - Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11,
11114 * and 15 Internal Base: 20 The selected HIF address bit is determined by adding the internal
11115 * base to the value of this field. If set to 15, row address bit 14 is set to 0.
11116 */
11117#define DDRC_ADDRMAP6_addrmap_row_b14(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b14_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b14_MASK)
11118#define DDRC_ADDRMAP6_addrmap_row_b15_MASK (0xF000000U)
11119#define DDRC_ADDRMAP6_addrmap_row_b15_SHIFT (24U)
11120/*! addrmap_row_b15 - Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11,
11121 * and 15 Internal Base: 21 The selected HIF address bit is determined by adding the internal
11122 * base to the value of this field. If set to 15, row address bit 15 is set to 0.
11123 */
11124#define DDRC_ADDRMAP6_addrmap_row_b15(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_addrmap_row_b15_SHIFT)) & DDRC_ADDRMAP6_addrmap_row_b15_MASK)
11125#define DDRC_ADDRMAP6_lpddr3_6gb_12gb_MASK (0x80000000U)
11126#define DDRC_ADDRMAP6_lpddr3_6gb_12gb_SHIFT (31U)
11127/*! lpddr3_6gb_12gb - Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 -
11128 * LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]==2'b11 is considered as
11129 * invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present only in designs
11130 * configured to support LPDDR3.
11131 */
11132#define DDRC_ADDRMAP6_lpddr3_6gb_12gb(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP6_lpddr3_6gb_12gb_SHIFT)) & DDRC_ADDRMAP6_lpddr3_6gb_12gb_MASK)
11133/*! @} */
11134
11135/*! @name ADDRMAP7 - Address Map Register 7 */
11136/*! @{ */
11137#define DDRC_ADDRMAP7_addrmap_row_b16_MASK (0xFU)
11138#define DDRC_ADDRMAP7_addrmap_row_b16_SHIFT (0U)
11139/*! addrmap_row_b16 - Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11,
11140 * and 15 Internal Base: 22 The selected HIF address bit is determined by adding the internal
11141 * base to the value of this field. If set to 15, row address bit 16 is set to 0.
11142 */
11143#define DDRC_ADDRMAP7_addrmap_row_b16(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP7_addrmap_row_b16_SHIFT)) & DDRC_ADDRMAP7_addrmap_row_b16_MASK)
11144#define DDRC_ADDRMAP7_addrmap_row_b17_MASK (0xF00U)
11145#define DDRC_ADDRMAP7_addrmap_row_b17_SHIFT (8U)
11146/*! addrmap_row_b17 - Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 11,
11147 * and 15 Internal Base: 23 The selected HIF address bit is determined by adding the internal
11148 * base to the value of this field. If set to 15, row address bit 17 is set to 0.
11149 */
11150#define DDRC_ADDRMAP7_addrmap_row_b17(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP7_addrmap_row_b17_SHIFT)) & DDRC_ADDRMAP7_addrmap_row_b17_MASK)
11151/*! @} */
11152
11153/*! @name ADDRMAP8 - Address Map Register 8 */
11154/*! @{ */
11155#define DDRC_ADDRMAP8_addrmap_bg_b0_MASK (0x1FU)
11156#define DDRC_ADDRMAP8_addrmap_bg_b0_SHIFT (0U)
11157/*! addrmap_bg_b0 - Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to
11158 * 31 Internal Base: 2 The selected HIF address bit for each of the bank group address bits is
11159 * determined by adding the internal base to the value of this field.
11160 */
11161#define DDRC_ADDRMAP8_addrmap_bg_b0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP8_addrmap_bg_b0_SHIFT)) & DDRC_ADDRMAP8_addrmap_bg_b0_MASK)
11162#define DDRC_ADDRMAP8_addrmap_bg_b1_MASK (0x3F00U)
11163#define DDRC_ADDRMAP8_addrmap_bg_b1_SHIFT (8U)
11164/*! addrmap_bg_b1 - Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to
11165 * 31, and 63 Internal Base: 3 The selected HIF address bit for each of the bank group address
11166 * bits is determined by adding the internal base to the value of this field. If set to 63, bank
11167 * group address bit 1 is set to 0.
11168 */
11169#define DDRC_ADDRMAP8_addrmap_bg_b1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP8_addrmap_bg_b1_SHIFT)) & DDRC_ADDRMAP8_addrmap_bg_b1_MASK)
11170/*! @} */
11171
11172/*! @name ADDRMAP9 - Address Map Register 9 */
11173/*! @{ */
11174#define DDRC_ADDRMAP9_addrmap_row_b2_MASK (0xFU)
11175#define DDRC_ADDRMAP9_addrmap_row_b2_SHIFT (0U)
11176/*! addrmap_row_b2 - Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11
11177 * Internal Base: 8 The selected HIF address bit for each of the row address bits is determined by
11178 * adding the internal base to the value of this field. This register field is used only when
11179 * ADDRMAP5.addrmap_row_b2_10 is set to value 15.
11180 */
11181#define DDRC_ADDRMAP9_addrmap_row_b2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b2_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b2_MASK)
11182#define DDRC_ADDRMAP9_addrmap_row_b3_MASK (0xF00U)
11183#define DDRC_ADDRMAP9_addrmap_row_b3_SHIFT (8U)
11184/*! addrmap_row_b3 - Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11
11185 * Internal Base: 9 The selected HIF address bit for each of the row address bits is determined by
11186 * adding the internal base to the value of this field. This register field is used only when
11187 * ADDRMAP5.addrmap_row_b2_10 is set to value 15.
11188 */
11189#define DDRC_ADDRMAP9_addrmap_row_b3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b3_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b3_MASK)
11190#define DDRC_ADDRMAP9_addrmap_row_b4_MASK (0xF0000U)
11191#define DDRC_ADDRMAP9_addrmap_row_b4_SHIFT (16U)
11192/*! addrmap_row_b4 - Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11
11193 * Internal Base: 10 The selected HIF address bit for each of the row address bits is determined by
11194 * adding the internal base to the value of this field. This register field is used only when
11195 * ADDRMAP5.addrmap_row_b2_10 is set to value 15.
11196 */
11197#define DDRC_ADDRMAP9_addrmap_row_b4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b4_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b4_MASK)
11198#define DDRC_ADDRMAP9_addrmap_row_b5_MASK (0xF000000U)
11199#define DDRC_ADDRMAP9_addrmap_row_b5_SHIFT (24U)
11200/*! addrmap_row_b5 - Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11
11201 * Internal Base: 11 The selected HIF address bit for each of the row address bits is determined by
11202 * adding the internal base to the value of this field. This register field is used only when
11203 * ADDRMAP5.addrmap_row_b2_10 is set to value 15.
11204 */
11205#define DDRC_ADDRMAP9_addrmap_row_b5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP9_addrmap_row_b5_SHIFT)) & DDRC_ADDRMAP9_addrmap_row_b5_MASK)
11206/*! @} */
11207
11208/*! @name ADDRMAP10 - Address Map Register 10 */
11209/*! @{ */
11210#define DDRC_ADDRMAP10_addrmap_row_b6_MASK (0xFU)
11211#define DDRC_ADDRMAP10_addrmap_row_b6_SHIFT (0U)
11212/*! addrmap_row_b6 - Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11
11213 * Internal Base: 12 The selected HIF address bit for each of the row address bits is determined by
11214 * adding the internal base to the value of this field. This register field is used only when
11215 * ADDRMAP5.addrmap_row_b2_10 is set to value 15.
11216 */
11217#define DDRC_ADDRMAP10_addrmap_row_b6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b6_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b6_MASK)
11218#define DDRC_ADDRMAP10_addrmap_row_b7_MASK (0xF00U)
11219#define DDRC_ADDRMAP10_addrmap_row_b7_SHIFT (8U)
11220/*! addrmap_row_b7 - Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11
11221 * Internal Base: 13 The selected HIF address bit for each of the row address bits is determined by
11222 * adding the internal base to the value of this field. This register field is used only when
11223 * ADDRMAP5.addrmap_row_b2_10 is set to value 15.
11224 */
11225#define DDRC_ADDRMAP10_addrmap_row_b7(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b7_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b7_MASK)
11226#define DDRC_ADDRMAP10_addrmap_row_b8_MASK (0xF0000U)
11227#define DDRC_ADDRMAP10_addrmap_row_b8_SHIFT (16U)
11228/*! addrmap_row_b8 - Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11
11229 * Internal Base: 14 The selected HIF address bit for each of the row address bits is determined by
11230 * adding the internal base to the value of this field. This register field is used only when
11231 * ADDRMAP5.addrmap_row_b2_10 is set to value 15.
11232 */
11233#define DDRC_ADDRMAP10_addrmap_row_b8(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b8_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b8_MASK)
11234#define DDRC_ADDRMAP10_addrmap_row_b9_MASK (0xF000000U)
11235#define DDRC_ADDRMAP10_addrmap_row_b9_SHIFT (24U)
11236/*! addrmap_row_b9 - Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11
11237 * Internal Base: 15 The selected HIF address bit for each of the row address bits is determined by
11238 * adding the internal base to the value of this field. This register field is used only when
11239 * ADDRMAP5.addrmap_row_b2_10 is set to value 15.
11240 */
11241#define DDRC_ADDRMAP10_addrmap_row_b9(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP10_addrmap_row_b9_SHIFT)) & DDRC_ADDRMAP10_addrmap_row_b9_MASK)
11242/*! @} */
11243
11244/*! @name ADDRMAP11 - Address Map Register 11 */
11245/*! @{ */
11246#define DDRC_ADDRMAP11_addrmap_row_b10_MASK (0xFU)
11247#define DDRC_ADDRMAP11_addrmap_row_b10_SHIFT (0U)
11248/*! addrmap_row_b10 - Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11
11249 * Internal Base: 16 The selected HIF address bit for each of the row address bits is determined
11250 * by adding the internal base to the value of this field. This register field is used only when
11251 * ADDRMAP5.addrmap_row_b2_10 is set to value 15.
11252 */
11253#define DDRC_ADDRMAP11_addrmap_row_b10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDRMAP11_addrmap_row_b10_SHIFT)) & DDRC_ADDRMAP11_addrmap_row_b10_MASK)
11254/*! @} */
11255
11256/*! @name ODTCFG - ODT Configuration Register */
11257/*! @{ */
11258#define DDRC_ODTCFG_rd_odt_delay_MASK (0x7CU)
11259#define DDRC_ODTCFG_rd_odt_delay_SHIFT (2U)
11260/*! rd_odt_delay - The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT
11261 * values associated with that command. ODT setting must remain constant for the entire time that
11262 * DQS is driven by the DDRC. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5
11263 * (DDR2-1066) If (CL + AL - 4 < 0), DDRC does not support ODT for read operation. DDR3: - CL -
11264 * CWL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL
11265 * mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) RD_PREAMBLE = 1 (1tCK write
11266 * preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, DDRC does
11267 * not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)
11268 */
11269#define DDRC_ODTCFG_rd_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_rd_odt_delay_SHIFT)) & DDRC_ODTCFG_rd_odt_delay_MASK)
11270#define DDRC_ODTCFG_rd_odt_hold_MASK (0xF00U)
11271#define DDRC_ODTCFG_rd_odt_hold_SHIFT (8U)
11272/*! rd_odt_hold - DFI PHY clock cycles to hold ODT for a read command. The minimum supported value
11273 * is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - BL4: 0x4 (not
11274 * DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK
11275 * write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) -
11276 * RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK)
11277 */
11278#define DDRC_ODTCFG_rd_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_rd_odt_hold_SHIFT)) & DDRC_ODTCFG_rd_odt_hold_MASK)
11279#define DDRC_ODTCFG_wr_odt_delay_MASK (0x1F0000U)
11280#define DDRC_ODTCFG_wr_odt_delay_SHIFT (16U)
11281/*! wr_odt_delay - The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT
11282 * values associated with that command. ODT setting must remain constant for the entire time that
11283 * DQS is driven by the DDRC. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL +
11284 * AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), DDRC does not support ODT
11285 * for write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3:
11286 * - WL - 1 - RU(tODTon(max)/tCK))
11287 */
11288#define DDRC_ODTCFG_wr_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_wr_odt_delay_SHIFT)) & DDRC_ODTCFG_wr_odt_delay_MASK)
11289#define DDRC_ODTCFG_wr_odt_hold_MASK (0xF000000U)
11290#define DDRC_ODTCFG_wr_odt_hold_SHIFT (24U)
11291/*! wr_odt_hold - DFI PHY clock cycles to hold ODT for a write command. The minimum supported value
11292 * is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066)
11293 * - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8:
11294 * 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble)
11295 * CRC_MODE = 0 (not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
11296 */
11297#define DDRC_ODTCFG_wr_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_wr_odt_hold_SHIFT)) & DDRC_ODTCFG_wr_odt_hold_MASK)
11298/*! @} */
11299
11300/*! @name ODTMAP - ODT/Rank Map Register */
11301/*! @{ */
11302#define DDRC_ODTMAP_rank0_wr_odt_MASK (0x3U)
11303#define DDRC_ODTMAP_rank0_wr_odt_SHIFT (0U)
11304/*! rank0_wr_odt - Indicates which remote ODTs must be turned on during a write to rank 0. Each rank
11305 * has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here.
11306 * Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each
11307 * rank, set its bit to 1 to enable its ODT.
11308 */
11309#define DDRC_ODTMAP_rank0_wr_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank0_wr_odt_SHIFT)) & DDRC_ODTMAP_rank0_wr_odt_MASK)
11310#define DDRC_ODTMAP_rank0_rd_odt_MASK (0x30U)
11311#define DDRC_ODTMAP_rank0_rd_odt_SHIFT (4U)
11312/*! rank0_rd_odt - Indicates which remote ODTs must be turned on during a read from rank 0. Each
11313 * rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here.
11314 * Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each
11315 * rank, set its bit to 1 to enable its ODT.
11316 */
11317#define DDRC_ODTMAP_rank0_rd_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank0_rd_odt_SHIFT)) & DDRC_ODTMAP_rank0_rd_odt_MASK)
11318#define DDRC_ODTMAP_rank1_wr_odt_MASK (0x300U)
11319#define DDRC_ODTMAP_rank1_wr_odt_SHIFT (8U)
11320/*! rank1_wr_odt - Indicates which remote ODTs must be turned on during a write to rank 1. Each rank
11321 * has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here.
11322 * Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each
11323 * rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks
11324 */
11325#define DDRC_ODTMAP_rank1_wr_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank1_wr_odt_SHIFT)) & DDRC_ODTMAP_rank1_wr_odt_MASK)
11326#define DDRC_ODTMAP_rank1_rd_odt_MASK (0x3000U)
11327#define DDRC_ODTMAP_rank1_rd_odt_SHIFT (12U)
11328/*! rank1_rd_odt - Indicates which remote ODTs must be turned on during a read from rank 1. Each
11329 * rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here.
11330 * Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB, etc. For each
11331 * rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more
11332 * ranks
11333 */
11334#define DDRC_ODTMAP_rank1_rd_odt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTMAP_rank1_rd_odt_SHIFT)) & DDRC_ODTMAP_rank1_rd_odt_MASK)
11335/*! @} */
11336
11337/*! @name SCHED - Scheduler Control Register */
11338/*! @{ */
11339#define DDRC_SCHED_force_low_pri_n_MASK (0x1U)
11340#define DDRC_SCHED_force_low_pri_n_SHIFT (0U)
11341/*! force_low_pri_n - Active low signal. When asserted ('0'), all incoming transactions are forced
11342 * to low priority. This implies that all High Priority Read (HPR) and Variable Priority Read
11343 * commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write side, all
11344 * Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands.
11345 * Forcing the incoming transactions to low priority implicitly turns off Bypass path for read
11346 * commands. FOR PERFORMANCE ONLY.
11347 */
11348#define DDRC_SCHED_force_low_pri_n(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_force_low_pri_n_SHIFT)) & DDRC_SCHED_force_low_pri_n_MASK)
11349#define DDRC_SCHED_prefer_write_MASK (0x2U)
11350#define DDRC_SCHED_prefer_write_SHIFT (1U)
11351/*! prefer_write - If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.
11352 */
11353#define DDRC_SCHED_prefer_write(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_prefer_write_SHIFT)) & DDRC_SCHED_prefer_write_MASK)
11354#define DDRC_SCHED_pageclose_MASK (0x4U)
11355#define DDRC_SCHED_pageclose_SHIFT (2U)
11356/*! pageclose - If true, bank is kept open only while there are page hit transactions available in
11357 * the CAM to that bank. The last read or write command in the CAM with a bank and page hit will
11358 * be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and
11359 * SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued
11360 * in some cases where there is a mode switch between Write and Read or between LPR and HPR. The
11361 * Read and Write commands that are executed as part of the ECC scrub requests are also executed
11362 * without auto-precharge. If false, the bank remains open until there is a need to close it (to
11363 * open a different page, or for page timeout or refresh timeout) - also known as open page
11364 * policy. The open page policy can be overridden by setting the per-command-autopre bit on the HIF
11365 * interface (hif_cmd_autopre). The pageclose feature provids a midway between Open and Close page
11366 * policies. FOR PERFORMANCE ONLY.
11367 */
11368#define DDRC_SCHED_pageclose(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_pageclose_SHIFT)) & DDRC_SCHED_pageclose_MASK)
11369#define DDRC_SCHED_lpr_num_entries_MASK (0x1F00U)
11370#define DDRC_SCHED_lpr_num_entries_SHIFT (8U)
11371/*! lpr_num_entries - Number of entries in the low priority transaction store is this value + 1.
11372 * (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high
11373 * priority transaction store. Setting this to maximum value allocates all entries to low
11374 * priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and
11375 * the rest to high priority transaction store. Note: In ECC configurations, the numbers of
11376 * write and low priority read credits issued is one less than in the non-ECC case. One entry each is
11377 * reserved in the write and low-priority read CAMs for storing the RMW requests arising out of
11378 * single bit error correction RMW operation.
11379 */
11380#define DDRC_SCHED_lpr_num_entries(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_lpr_num_entries_SHIFT)) & DDRC_SCHED_lpr_num_entries_MASK)
11381#define DDRC_SCHED_go2critical_hysteresis_MASK (0xFF0000U)
11382#define DDRC_SCHED_go2critical_hysteresis_SHIFT (16U)
11383/*! go2critical_hysteresis - UNUSED
11384 */
11385#define DDRC_SCHED_go2critical_hysteresis(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_go2critical_hysteresis_SHIFT)) & DDRC_SCHED_go2critical_hysteresis_MASK)
11386#define DDRC_SCHED_rdwr_idle_gap_MASK (0x7F000000U)
11387#define DDRC_SCHED_rdwr_idle_gap_SHIFT (24U)
11388/*! rdwr_idle_gap - When the preferred transaction store is empty for these many clock cycles,
11389 * switch to the alternate transaction store if it is non-empty. The read transaction store (both high
11390 * and low priority) is the default preferred transaction store and the write transaction store
11391 * is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal
11392 * value for this register. When set to 0x0, the transaction store switching will happen
11393 * immediately when the switching conditions become true. FOR PERFORMANCE ONLY
11394 */
11395#define DDRC_SCHED_rdwr_idle_gap(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED_rdwr_idle_gap_SHIFT)) & DDRC_SCHED_rdwr_idle_gap_MASK)
11396/*! @} */
11397
11398/*! @name SCHED1 - Scheduler Control Register 1 */
11399/*! @{ */
11400#define DDRC_SCHED1_pageclose_timer_MASK (0xFFU)
11401#define DDRC_SCHED1_pageclose_timer_SHIFT (0U)
11402/*! pageclose_timer - This field works in conjunction with SCHED.pageclose. It only has meaning if
11403 * SCHED.pageclose==1. If SCHED.pageclose==1 and pageclose_timer==0, then an auto-precharge may be
11404 * scheduled for last read or write command in the CAM with a bank and page hit. Note, sometimes
11405 * an explicit precharge is scheduled instead of the auto-precharge. See SCHED.pageclose for
11406 * details of when this may happen. If SCHED.pageclose==1 and pageclose_timer>0, then an
11407 * auto-precharge is not scheduled for last read or write command in the CAM with a bank and page hit.
11408 * Instead, a timer is started, with pageclose_timer as the initial value. There is a timer on a per
11409 * bank basis. The timer decrements unless the next read or write in the CAM to a bank is a page
11410 * hit. It gets reset to pageclose_timer value if the next read or write in the CAM to a bank is a
11411 * page hit. Once the timer has reached zero, an explcit precharge will be attempted to be
11412 * scheduled.
11413 */
11414#define DDRC_SCHED1_pageclose_timer(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SCHED1_pageclose_timer_SHIFT)) & DDRC_SCHED1_pageclose_timer_MASK)
11415/*! @} */
11416
11417/*! @name PERFHPR1 - High Priority Read CAM Register 1 */
11418/*! @{ */
11419#define DDRC_PERFHPR1_hpr_max_starve_MASK (0xFFFFU)
11420#define DDRC_PERFHPR1_hpr_max_starve_SHIFT (0U)
11421/*! hpr_max_starve - Number of DFI clocks that the HPR queue can be starved before it goes critical.
11422 * The minimum valid functional value for this register is 0x1. Programming it to 0x0 will
11423 * disable the starvation functionality; during normal operation, this function should not be disabled
11424 * as it will cause excessive latencies. FOR PERFORMANCE ONLY.
11425 */
11426#define DDRC_PERFHPR1_hpr_max_starve(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFHPR1_hpr_max_starve_SHIFT)) & DDRC_PERFHPR1_hpr_max_starve_MASK)
11427#define DDRC_PERFHPR1_hpr_xact_run_length_MASK (0xFF000000U)
11428#define DDRC_PERFHPR1_hpr_xact_run_length_SHIFT (24U)
11429/*! hpr_xact_run_length - Number of transactions that are serviced once the HPR queue goes critical
11430 * is the smaller of: - (a) This number - (b) Number of transactions available. Unit:
11431 * Transaction. FOR PERFORMANCE ONLY.
11432 */
11433#define DDRC_PERFHPR1_hpr_xact_run_length(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFHPR1_hpr_xact_run_length_SHIFT)) & DDRC_PERFHPR1_hpr_xact_run_length_MASK)
11434/*! @} */
11435
11436/*! @name PERFLPR1 - Low Priority Read CAM Register 1 */
11437/*! @{ */
11438#define DDRC_PERFLPR1_lpr_max_starve_MASK (0xFFFFU)
11439#define DDRC_PERFLPR1_lpr_max_starve_SHIFT (0U)
11440/*! lpr_max_starve - Number of DFI clocks that the LPR queue can be starved before it goes critical.
11441 * The minimum valid functional value for this register is 0x1. Programming it to 0x0 will
11442 * disable the starvation functionality; during normal operation, this function should not be disabled
11443 * as it will cause excessive latencies. FOR PERFORMANCE ONLY.
11444 */
11445#define DDRC_PERFLPR1_lpr_max_starve(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFLPR1_lpr_max_starve_SHIFT)) & DDRC_PERFLPR1_lpr_max_starve_MASK)
11446#define DDRC_PERFLPR1_lpr_xact_run_length_MASK (0xFF000000U)
11447#define DDRC_PERFLPR1_lpr_xact_run_length_SHIFT (24U)
11448/*! lpr_xact_run_length - Number of transactions that are serviced once the LPR queue goes critical
11449 * is the smaller of: - (a) This number - (b) Number of transactions available. Unit:
11450 * Transaction. FOR PERFORMANCE ONLY.
11451 */
11452#define DDRC_PERFLPR1_lpr_xact_run_length(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFLPR1_lpr_xact_run_length_SHIFT)) & DDRC_PERFLPR1_lpr_xact_run_length_MASK)
11453/*! @} */
11454
11455/*! @name PERFWR1 - Write CAM Register 1 */
11456/*! @{ */
11457#define DDRC_PERFWR1_w_max_starve_MASK (0xFFFFU)
11458#define DDRC_PERFWR1_w_max_starve_SHIFT (0U)
11459/*! w_max_starve - Number of DFI clocks that the WR queue can be starved before it goes critical.
11460 * The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable
11461 * the starvation functionality; during normal operation, this function should not be disabled as
11462 * it will cause excessive latencies. FOR PERFORMANCE ONLY.
11463 */
11464#define DDRC_PERFWR1_w_max_starve(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFWR1_w_max_starve_SHIFT)) & DDRC_PERFWR1_w_max_starve_MASK)
11465#define DDRC_PERFWR1_w_xact_run_length_MASK (0xFF000000U)
11466#define DDRC_PERFWR1_w_xact_run_length_SHIFT (24U)
11467/*! w_xact_run_length - Number of transactions that are serviced once the WR queue goes critical is
11468 * the smaller of: - (a) This number - (b) Number of transactions available. Unit: Transaction.
11469 * FOR PERFORMANCE ONLY.
11470 */
11471#define DDRC_PERFWR1_w_xact_run_length(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PERFWR1_w_xact_run_length_SHIFT)) & DDRC_PERFWR1_w_xact_run_length_MASK)
11472/*! @} */
11473
11474/*! @name DBG0 - Debug Register 0 */
11475/*! @{ */
11476#define DDRC_DBG0_dis_wc_MASK (0x1U)
11477#define DDRC_DBG0_dis_wc_SHIFT (0U)
11478/*! dis_wc - When 1, disable write combine. FOR DEBUG ONLY
11479 */
11480#define DDRC_DBG0_dis_wc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_wc_SHIFT)) & DDRC_DBG0_dis_wc_MASK)
11481#define DDRC_DBG0_dis_rd_bypass_MASK (0x2U)
11482#define DDRC_DBG0_dis_rd_bypass_SHIFT (1U)
11483/*! dis_rd_bypass - Only present in designs supporting read bypass. When 1, disable bypass path for
11484 * high priority read page hits FOR DEBUG ONLY.
11485 */
11486#define DDRC_DBG0_dis_rd_bypass(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_rd_bypass_SHIFT)) & DDRC_DBG0_dis_rd_bypass_MASK)
11487#define DDRC_DBG0_dis_act_bypass_MASK (0x4U)
11488#define DDRC_DBG0_dis_act_bypass_SHIFT (2U)
11489/*! dis_act_bypass - Only present in designs supporting activate bypass. When 1, disable bypass path
11490 * for high priority read activates FOR DEBUG ONLY.
11491 */
11492#define DDRC_DBG0_dis_act_bypass(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_act_bypass_SHIFT)) & DDRC_DBG0_dis_act_bypass_MASK)
11493#define DDRC_DBG0_dis_collision_page_opt_MASK (0x10U)
11494#define DDRC_DBG0_dis_collision_page_opt_SHIFT (4U)
11495/*! dis_collision_page_opt - When this is set to '0', auto-precharge is disabled for the flushed
11496 * command in a collision case. Collision cases are write followed by read to same address, read
11497 * followed by write to same address, or write followed by write to same address with DBG0.dis_wc
11498 * bit = 1 (where same address comparisons exclude the two address bits representing critical
11499 * word). FOR DEBUG ONLY.
11500 */
11501#define DDRC_DBG0_dis_collision_page_opt(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG0_dis_collision_page_opt_SHIFT)) & DDRC_DBG0_dis_collision_page_opt_MASK)
11502/*! @} */
11503
11504/*! @name DBG1 - Debug Register 1 */
11505/*! @{ */
11506#define DDRC_DBG1_dis_dq_MASK (0x1U)
11507#define DDRC_DBG1_dis_dq_SHIFT (0U)
11508/*! dis_dq - When 1, DDRC will not de-queue any transactions from the CAM. Bypass is also disabled.
11509 * All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this
11510 * is asserted. This bit may be used to prevent reads or writes being issued by the DDRC, which
11511 * makes it safe to modify certain register fields associated with reads and writes (see User
11512 * Guide for details). After setting this bit, it is strongly recommended to poll
11513 * DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty, before making changes to any registers which
11514 * affect reads and writes. This will ensure that the relevant logic in the DDRC is idle. This bit
11515 * is intended to be switched on-the-fly.
11516 */
11517#define DDRC_DBG1_dis_dq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG1_dis_dq_SHIFT)) & DDRC_DBG1_dis_dq_MASK)
11518#define DDRC_DBG1_dis_hif_MASK (0x2U)
11519#define DDRC_DBG1_dis_hif_SHIFT (1U)
11520/*! dis_hif - When 1, DDRC asserts the HIF command signal hif_cmd_stall. DDRC will ignore the
11521 * hif_cmd_valid and all other associated request signals. This bit is intended to be switched
11522 * on-the-fly.
11523 */
11524#define DDRC_DBG1_dis_hif(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBG1_dis_hif_SHIFT)) & DDRC_DBG1_dis_hif_MASK)
11525/*! @} */
11526
11527/*! @name DBGCAM - CAM Debug Register */
11528/*! @{ */
11529#define DDRC_DBGCAM_dbg_hpr_q_depth_MASK (0x3FU)
11530#define DDRC_DBGCAM_dbg_hpr_q_depth_SHIFT (0U)
11531/*! dbg_hpr_q_depth - High priority read queue depth FOR DEBUG ONLY
11532 */
11533#define DDRC_DBGCAM_dbg_hpr_q_depth(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_hpr_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_hpr_q_depth_MASK)
11534#define DDRC_DBGCAM_dbg_lpr_q_depth_MASK (0x3F00U)
11535#define DDRC_DBGCAM_dbg_lpr_q_depth_SHIFT (8U)
11536/*! dbg_lpr_q_depth - Low priority read queue depth The last entry of Lpr queue is reserved for ECC
11537 * SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG
11538 * ONLY
11539 */
11540#define DDRC_DBGCAM_dbg_lpr_q_depth(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_lpr_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_lpr_q_depth_MASK)
11541#define DDRC_DBGCAM_dbg_w_q_depth_MASK (0x3F0000U)
11542#define DDRC_DBGCAM_dbg_w_q_depth_SHIFT (16U)
11543/*! dbg_w_q_depth - Write queue depth The last entry of WR queue is reserved for ECC SCRUB
11544 * operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY
11545 */
11546#define DDRC_DBGCAM_dbg_w_q_depth(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_w_q_depth_SHIFT)) & DDRC_DBGCAM_dbg_w_q_depth_MASK)
11547#define DDRC_DBGCAM_dbg_stall_MASK (0x1000000U)
11548#define DDRC_DBGCAM_dbg_stall_SHIFT (24U)
11549/*! dbg_stall - Stall FOR DEBUG ONLY
11550 */
11551#define DDRC_DBGCAM_dbg_stall(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_SHIFT)) & DDRC_DBGCAM_dbg_stall_MASK)
11552#define DDRC_DBGCAM_dbg_rd_q_empty_MASK (0x2000000U)
11553#define DDRC_DBGCAM_dbg_rd_q_empty_SHIFT (25U)
11554/*! dbg_rd_q_empty - When 1, all the Read command queues and Read data buffers inside DDRC are
11555 * empty. This register is to be used for debug purpose. An example use-case scenario: When Controller
11556 * enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have
11557 * executed all the commands in its queues and the write and read data drained. Hence this register
11558 * should be 1 at that time. FOR DEBUG ONLY
11559 */
11560#define DDRC_DBGCAM_dbg_rd_q_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_rd_q_empty_SHIFT)) & DDRC_DBGCAM_dbg_rd_q_empty_MASK)
11561#define DDRC_DBGCAM_dbg_wr_q_empty_MASK (0x4000000U)
11562#define DDRC_DBGCAM_dbg_wr_q_empty_SHIFT (26U)
11563/*! dbg_wr_q_empty - When 1, all the Write command queues and Write data buffers inside DDRC are
11564 * empty. This register is to be used for debug purpose. An example use-case scenario: When
11565 * Controller enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have
11566 * executed all the commands in its queues and the write and read data drained. Hence this register
11567 * should be 1 at that time. FOR DEBUG ONLY
11568 */
11569#define DDRC_DBGCAM_dbg_wr_q_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_wr_q_empty_SHIFT)) & DDRC_DBGCAM_dbg_wr_q_empty_MASK)
11570#define DDRC_DBGCAM_rd_data_pipeline_empty_MASK (0x10000000U)
11571#define DDRC_DBGCAM_rd_data_pipeline_empty_SHIFT (28U)
11572/*! rd_data_pipeline_empty - This bit indicates that the read data pipeline on the DFI interface is
11573 * empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to
11574 * ensure that all remaining commands/data have completed.
11575 */
11576#define DDRC_DBGCAM_rd_data_pipeline_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_rd_data_pipeline_empty_SHIFT)) & DDRC_DBGCAM_rd_data_pipeline_empty_MASK)
11577#define DDRC_DBGCAM_wr_data_pipeline_empty_MASK (0x20000000U)
11578#define DDRC_DBGCAM_wr_data_pipeline_empty_SHIFT (29U)
11579/*! wr_data_pipeline_empty - This bit indicates that the write data pipeline on the DFI interface is
11580 * empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to
11581 * ensure that all remaining commands/data have completed.
11582 */
11583#define DDRC_DBGCAM_wr_data_pipeline_empty(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_wr_data_pipeline_empty_SHIFT)) & DDRC_DBGCAM_wr_data_pipeline_empty_MASK)
11584#define DDRC_DBGCAM_dbg_stall_wr_MASK (0x40000000U)
11585#define DDRC_DBGCAM_dbg_stall_wr_SHIFT (30U)
11586/*! dbg_stall_wr - Stall for Write channel FOR DEBUG ONLY
11587 */
11588#define DDRC_DBGCAM_dbg_stall_wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_wr_SHIFT)) & DDRC_DBGCAM_dbg_stall_wr_MASK)
11589#define DDRC_DBGCAM_dbg_stall_rd_MASK (0x80000000U)
11590#define DDRC_DBGCAM_dbg_stall_rd_SHIFT (31U)
11591/*! dbg_stall_rd - Stall for Read channel FOR DEBUG ONLY
11592 */
11593#define DDRC_DBGCAM_dbg_stall_rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCAM_dbg_stall_rd_SHIFT)) & DDRC_DBGCAM_dbg_stall_rd_MASK)
11594/*! @} */
11595
11596/*! @name DBGCMD - Command Debug Register */
11597/*! @{ */
11598#define DDRC_DBGCMD_rank0_refresh_MASK (0x1U)
11599#define DDRC_DBGCMD_rank0_refresh_SHIFT (0U)
11600/*! rank0_refresh - Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank
11601 * 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When
11602 * DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in DDRC. For 3DS configuration, refresh is sent
11603 * to rank index 0. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is
11604 * recommended NOT to set this register bit if in Init or Deep power-down operating modes or
11605 * Maximum Power Saving Mode.
11606 */
11607#define DDRC_DBGCMD_rank0_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_rank0_refresh_SHIFT)) & DDRC_DBGCMD_rank0_refresh_MASK)
11608#define DDRC_DBGCMD_rank1_refresh_MASK (0x2U)
11609#define DDRC_DBGCMD_rank1_refresh_SHIFT (1U)
11610/*! rank1_refresh - Setting this register bit to 1 indicates to the DDRC to issue a refresh to rank
11611 * 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be set. When
11612 * DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in DDRC. For 3DS configuration, refresh is sent
11613 * to rank index 1. This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is
11614 * recommended NOT to set this register bit if in Init or Deep power-down operating modes or
11615 * Maximum Power Saving Mode.
11616 */
11617#define DDRC_DBGCMD_rank1_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_rank1_refresh_SHIFT)) & DDRC_DBGCMD_rank1_refresh_MASK)
11618#define DDRC_DBGCMD_zq_calib_short_MASK (0x10U)
11619#define DDRC_DBGCMD_zq_calib_short_SHIFT (4U)
11620/*! zq_calib_short - Setting this register bit to 1 indicates to the DDRC to issue a ZQCS (ZQ
11621 * calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the
11622 * DDRC, the bit is automatically cleared. This operation can be performed only when
11623 * ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register
11624 * bit is ignored when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep
11625 * power-down operating modes and Maximum Power Saving Mode.
11626 */
11627#define DDRC_DBGCMD_zq_calib_short(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_zq_calib_short_SHIFT)) & DDRC_DBGCMD_zq_calib_short_MASK)
11628#define DDRC_DBGCMD_ctrlupd_MASK (0x20U)
11629#define DDRC_DBGCMD_ctrlupd_SHIFT (5U)
11630/*! ctrlupd - Setting this register bit to 1 indicates to the DDRC to issue a dfi_ctrlupd_req to the
11631 * PHY. When this request is stored in the DDRC, the bit is automatically cleared. This
11632 * operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.
11633 */
11634#define DDRC_DBGCMD_ctrlupd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGCMD_ctrlupd_SHIFT)) & DDRC_DBGCMD_ctrlupd_MASK)
11635/*! @} */
11636
11637/*! @name DBGSTAT - Status Debug Register */
11638/*! @{ */
11639#define DDRC_DBGSTAT_rank0_refresh_busy_MASK (0x1U)
11640#define DDRC_DBGSTAT_rank0_refresh_busy_SHIFT (0U)
11641/*! rank0_refresh_busy - SoC core may initiate a rank0_refresh operation (refresh operation to rank
11642 * 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh
11643 * is set to one. It goes low when the rank0_refresh operation is stored in the DDRC. It is
11644 * recommended not to perform rank0_refresh operations when this signal is high. - 0 - Indicates that
11645 * the SoC core can initiate a rank0_refresh operation - 1 - Indicates that rank0_refresh
11646 * operation has not been stored yet in the DDRC
11647 */
11648#define DDRC_DBGSTAT_rank0_refresh_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_rank0_refresh_busy_SHIFT)) & DDRC_DBGSTAT_rank0_refresh_busy_MASK)
11649#define DDRC_DBGSTAT_rank1_refresh_busy_MASK (0x2U)
11650#define DDRC_DBGSTAT_rank1_refresh_busy_SHIFT (1U)
11651/*! rank1_refresh_busy - SoC core may initiate a rank1_refresh operation (refresh operation to rank
11652 * 1) only if this signal is low. This signal goes high in the clock after DBGCMD.rank1_refresh
11653 * is set to one. It goes low when the rank1_refresh operation is stored in the DDRC. It is
11654 * recommended not to perform rank1_refresh operations when this signal is high. - 0 - Indicates that
11655 * the SoC core can initiate a rank1_refresh operation - 1 - Indicates that rank1_refresh
11656 * operation has not been stored yet in the DDRC
11657 */
11658#define DDRC_DBGSTAT_rank1_refresh_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_rank1_refresh_busy_SHIFT)) & DDRC_DBGSTAT_rank1_refresh_busy_MASK)
11659#define DDRC_DBGSTAT_zq_calib_short_busy_MASK (0x10U)
11660#define DDRC_DBGSTAT_zq_calib_short_busy_SHIFT (4U)
11661/*! zq_calib_short_busy - SoC core may initiate a ZQCS (ZQ calibration short) operation only if this
11662 * signal is low. This signal goes high in the clock after the DDRC accepts the ZQCS request. It
11663 * goes low when the ZQCS operation is initiated in the DDRC. It is recommended not to perform
11664 * ZQCS operations when this signal is high. - 0 - Indicates that the SoC core can initiate a ZQCS
11665 * operation - 1 - Indicates that ZQCS operation has not been initiated yet in the DDRC
11666 */
11667#define DDRC_DBGSTAT_zq_calib_short_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_zq_calib_short_busy_SHIFT)) & DDRC_DBGSTAT_zq_calib_short_busy_MASK)
11668#define DDRC_DBGSTAT_ctrlupd_busy_MASK (0x20U)
11669#define DDRC_DBGSTAT_ctrlupd_busy_SHIFT (5U)
11670/*! ctrlupd_busy - SoC core may initiate a ctrlupd operation only if this signal is low. This signal
11671 * goes high in the clock after the DDRC accepts the ctrlupd request. It goes low when the
11672 * ctrlupd operation is initiated in the DDRC. It is recommended not to perform ctrlupd operations
11673 * when this signal is high. - 0 - Indicates that the SoC core can initiate a ctrlupd operation - 1
11674 * - Indicates that ctrlupd operation has not been initiated yet in the DDRC
11675 */
11676#define DDRC_DBGSTAT_ctrlupd_busy(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DBGSTAT_ctrlupd_busy_SHIFT)) & DDRC_DBGSTAT_ctrlupd_busy_MASK)
11677/*! @} */
11678
11679/*! @name SWCTL - Software Register Programming Control Enable */
11680/*! @{ */
11681#define DDRC_SWCTL_sw_done_MASK (0x1U)
11682#define DDRC_SWCTL_sw_done_SHIFT (0U)
11683/*! sw_done - Enable quasi-dynamic register programming outside reset. Program register to 0 to
11684 * enable quasi-dynamic programming. Set back register to 1 once programming is done.
11685 */
11686#define DDRC_SWCTL_sw_done(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SWCTL_sw_done_SHIFT)) & DDRC_SWCTL_sw_done_MASK)
11687/*! @} */
11688
11689/*! @name SWSTAT - Software Register Programming Control Status */
11690/*! @{ */
11691#define DDRC_SWSTAT_sw_done_ack_MASK (0x1U)
11692#define DDRC_SWSTAT_sw_done_ack_SHIFT (0U)
11693/*! sw_done_ack - Register programming done. This register is the echo of SWCTL.sw_done. Wait for
11694 * sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure
11695 * that the correct registers values are propagated to the destination clock domains.
11696 */
11697#define DDRC_SWSTAT_sw_done_ack(x) (((uint32_t)(((uint32_t)(x)) << DDRC_SWSTAT_sw_done_ack_SHIFT)) & DDRC_SWSTAT_sw_done_ack_MASK)
11698/*! @} */
11699
11700/*! @name POISONCFG - AXI Poison Configuration Register. */
11701/*! @{ */
11702#define DDRC_POISONCFG_wr_poison_slverr_en_MASK (0x1U)
11703#define DDRC_POISONCFG_wr_poison_slverr_en_SHIFT (0U)
11704/*! wr_poison_slverr_en - If set to 1, enables SLVERR response for write transaction poisoning
11705 */
11706#define DDRC_POISONCFG_wr_poison_slverr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_slverr_en_SHIFT)) & DDRC_POISONCFG_wr_poison_slverr_en_MASK)
11707#define DDRC_POISONCFG_wr_poison_intr_en_MASK (0x10U)
11708#define DDRC_POISONCFG_wr_poison_intr_en_SHIFT (4U)
11709/*! wr_poison_intr_en - If set to 1, enables interrupts for write transaction poisoning
11710 */
11711#define DDRC_POISONCFG_wr_poison_intr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_intr_en_SHIFT)) & DDRC_POISONCFG_wr_poison_intr_en_MASK)
11712#define DDRC_POISONCFG_wr_poison_intr_clr_MASK (0x100U)
11713#define DDRC_POISONCFG_wr_poison_intr_clr_SHIFT (8U)
11714/*! wr_poison_intr_clr - Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for
11715 * correct value to propagate to core logic and clear the interrupts.
11716 */
11717#define DDRC_POISONCFG_wr_poison_intr_clr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_wr_poison_intr_clr_SHIFT)) & DDRC_POISONCFG_wr_poison_intr_clr_MASK)
11718#define DDRC_POISONCFG_rd_poison_slverr_en_MASK (0x10000U)
11719#define DDRC_POISONCFG_rd_poison_slverr_en_SHIFT (16U)
11720/*! rd_poison_slverr_en - If set to 1, enables SLVERR response for read transaction poisoning
11721 */
11722#define DDRC_POISONCFG_rd_poison_slverr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_slverr_en_SHIFT)) & DDRC_POISONCFG_rd_poison_slverr_en_MASK)
11723#define DDRC_POISONCFG_rd_poison_intr_en_MASK (0x100000U)
11724#define DDRC_POISONCFG_rd_poison_intr_en_SHIFT (20U)
11725/*! rd_poison_intr_en - If set to 1, enables interrupts for read transaction poisoning
11726 */
11727#define DDRC_POISONCFG_rd_poison_intr_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_intr_en_SHIFT)) & DDRC_POISONCFG_rd_poison_intr_en_MASK)
11728#define DDRC_POISONCFG_rd_poison_intr_clr_MASK (0x1000000U)
11729#define DDRC_POISONCFG_rd_poison_intr_clr_SHIFT (24U)
11730/*! rd_poison_intr_clr - Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for
11731 * correct value to propagate to core logic and clear the interrupts.
11732 */
11733#define DDRC_POISONCFG_rd_poison_intr_clr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONCFG_rd_poison_intr_clr_SHIFT)) & DDRC_POISONCFG_rd_poison_intr_clr_MASK)
11734/*! @} */
11735
11736/*! @name POISONSTAT - AXI Poison Status Register */
11737/*! @{ */
11738#define DDRC_POISONSTAT_wr_poison_intr_0_MASK (0x1U)
11739#define DDRC_POISONSTAT_wr_poison_intr_0_SHIFT (0U)
11740/*! wr_poison_intr_0 - Write transaction poisoning error interrupt for port 0. This register is a
11741 * APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is
11742 * poisoned on the corresponding AXI port's write address channel. Bit 0 corresponds to Port 0, and
11743 * so on. Interrupt is cleared by register wr_poison_intr_clr, then value propagated to APB
11744 * clock.
11745 */
11746#define DDRC_POISONSTAT_wr_poison_intr_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONSTAT_wr_poison_intr_0_SHIFT)) & DDRC_POISONSTAT_wr_poison_intr_0_MASK)
11747#define DDRC_POISONSTAT_rd_poison_intr_0_MASK (0x10000U)
11748#define DDRC_POISONSTAT_rd_poison_intr_0_SHIFT (16U)
11749/*! rd_poison_intr_0 - Read transaction poisoning error interrupt for port 0. This register is a APB
11750 * clock copy (double register synchronizer) of the interrupt asserted when a transaction is
11751 * poisoned on the corresponding AXI port's read address channel. Bit 0 corresponds to Port 0, and
11752 * so on. Interrupt is cleared by register rd_poison_intr_clr, then value propagated to APB clock.
11753 */
11754#define DDRC_POISONSTAT_rd_poison_intr_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_POISONSTAT_rd_poison_intr_0_SHIFT)) & DDRC_POISONSTAT_rd_poison_intr_0_MASK)
11755/*! @} */
11756
11757/*! @name PSTAT - Port Status Register */
11758/*! @{ */
11759#define DDRC_PSTAT_rd_port_busy_0_MASK (0x1U)
11760#define DDRC_PSTAT_rd_port_busy_0_SHIFT (0U)
11761/*! rd_port_busy_0 - Indicates if there are outstanding reads for AXI port 0.
11762 */
11763#define DDRC_PSTAT_rd_port_busy_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PSTAT_rd_port_busy_0_SHIFT)) & DDRC_PSTAT_rd_port_busy_0_MASK)
11764#define DDRC_PSTAT_wr_port_busy_0_MASK (0x10000U)
11765#define DDRC_PSTAT_wr_port_busy_0_SHIFT (16U)
11766/*! wr_port_busy_0 - Indicates if there are outstanding writes for AXI port 0.
11767 */
11768#define DDRC_PSTAT_wr_port_busy_0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PSTAT_wr_port_busy_0_SHIFT)) & DDRC_PSTAT_wr_port_busy_0_MASK)
11769/*! @} */
11770
11771/*! @name PCCFG - Port Common Configuration Register */
11772/*! @{ */
11773#define DDRC_PCCFG_go2critical_en_MASK (0x1U)
11774#define DDRC_PCCFG_go2critical_en_SHIFT (0U)
11775/*! go2critical_en - If set to 1 (enabled), sets co_gs_go2critical_wr and
11776 * co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from
11777 * AXI master. If set to 0 (disabled), co_gs_go2critical_wr and
11778 * co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.
11779 */
11780#define DDRC_PCCFG_go2critical_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_go2critical_en_SHIFT)) & DDRC_PCCFG_go2critical_en_MASK)
11781#define DDRC_PCCFG_pagematch_limit_MASK (0x10U)
11782#define DDRC_PCCFG_pagematch_limit_SHIFT (4U)
11783/*! pagematch_limit - Page match four limit. If set to 1, limits the number of consecutive same page
11784 * DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is
11785 * enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC
11786 * transactions.
11787 */
11788#define DDRC_PCCFG_pagematch_limit(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_pagematch_limit_SHIFT)) & DDRC_PCCFG_pagematch_limit_MASK)
11789#define DDRC_PCCFG_bl_exp_mode_MASK (0x100U)
11790#define DDRC_PCCFG_bl_exp_mode_SHIFT (8U)
11791/*! bl_exp_mode - Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every
11792 * AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then
11793 * XPI will use half of the memory burst length as a unit. This applies to both reads and
11794 * writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in
11795 * cases where Partial Writes is enabled (DDRC_PARTIAL_WR=1), in order to avoid or minimize t_ccd_l
11796 * penalty in DDR4 and t_ccd_mw penalty in LPDDR4. Hence, bl_exp_mode=1 is only recommended if
11797 * DDR4 or LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the
11798 * following cases: - DDRC_PARTIAL_WR=0 - DDRC_PARTIAL_WR=1, MSTR.data_bus_width=01,
11799 * MEMC_BURST_LENGTH=8 and MSTR.burst_rdwr=1000 (LPDDR4 only) - DDRC_PARTIAL_WR=1, MSTR.data_bus_width=01,
11800 * MEMC_BURST_LENGTH=4 and MSTR.burst_rdwr=0100 (DDR4 only), with either MSTR.reg_ddrc_burstchop=0 or
11801 * CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Data Channel
11802 * Interleave is enabled
11803 */
11804#define DDRC_PCCFG_bl_exp_mode(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCCFG_bl_exp_mode_SHIFT)) & DDRC_PCCFG_bl_exp_mode_MASK)
11805/*! @} */
11806
11807/*! @name PCFGR_0 - Port n Configuration Read Register */
11808/*! @{ */
11809#define DDRC_PCFGR_0_rd_port_priority_MASK (0x3FFU)
11810#define DDRC_PCFGR_0_rd_port_priority_SHIFT (0U)
11811/*! rd_port_priority - Determines the initial load value of read aging counters. These counters will
11812 * be parallel loaded after reset, or after each grant to the corresponding port. The aging
11813 * counters down-count every clock cycle where the port is requesting but not granted. The higher
11814 * significant 5-bits of the read aging counter sets the priority of the read channel of a given
11815 * port. Port's priority will increase as the higher significant 5-bits of the counter starts to
11816 * decrease. When the aging counter becomes 0, the corresponding port channel will have the highest
11817 * priority level (timeout condition - Priority0). For multi-port configurations, the aging
11818 * counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are
11819 * enabled (timeout is still applicable). For single port configurations, the aging counters are
11820 * only used when they timeout (become 0) to force read-write direction switching. In this case,
11821 * external dynamic priority input, arqos (for reads only) can still be used to set the DDRC read
11822 * priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by
11823 * command basis. Note: The two LSBs of this register field are tied internally to 2'b00.
11824 */
11825#define DDRC_PCFGR_0_rd_port_priority(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_priority_SHIFT)) & DDRC_PCFGR_0_rd_port_priority_MASK)
11826#define DDRC_PCFGR_0_rd_port_aging_en_MASK (0x1000U)
11827#define DDRC_PCFGR_0_rd_port_aging_en_SHIFT (12U)
11828/*! rd_port_aging_en - If set to 1, enables aging function for the read channel of the port.
11829 */
11830#define DDRC_PCFGR_0_rd_port_aging_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_aging_en_SHIFT)) & DDRC_PCFGR_0_rd_port_aging_en_MASK)
11831#define DDRC_PCFGR_0_rd_port_urgent_en_MASK (0x2000U)
11832#define DDRC_PCFGR_0_rd_port_urgent_en_SHIFT (13U)
11833/*! rd_port_urgent_en - If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled
11834 * and arurgent is asserted by the master, that port becomes the highest priority and
11835 * co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in
11836 * PCCFG.go2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is
11837 * independent of address handshaking (it is not associated with any particular command).
11838 */
11839#define DDRC_PCFGR_0_rd_port_urgent_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_urgent_en_SHIFT)) & DDRC_PCFGR_0_rd_port_urgent_en_MASK)
11840#define DDRC_PCFGR_0_rd_port_pagematch_en_MASK (0x4000U)
11841#define DDRC_PCFGR_0_rd_port_pagematch_en_SHIFT (14U)
11842/*! rd_port_pagematch_en - If set to 1, enables the Page Match feature. If enabled, once a
11843 * requesting port is granted, the port is continued to be granted if the following immediate commands are
11844 * to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit
11845 * register.
11846 */
11847#define DDRC_PCFGR_0_rd_port_pagematch_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rd_port_pagematch_en_SHIFT)) & DDRC_PCFGR_0_rd_port_pagematch_en_MASK)
11848#define DDRC_PCFGR_0_rdwr_ordered_en_MASK (0x10000U)
11849#define DDRC_PCFGR_0_rdwr_ordered_en_SHIFT (16U)
11850/*! rdwr_ordered_en - Enable ordered read/writes. If set to 1, preserves the ordering between read
11851 * transaction and write transaction issued to the same address, on a given port. In other words,
11852 * the controller ensures that all same address read and write commands from the application port
11853 * interface are transported to the DFI interface in the order of acceptance. This feature is
11854 * useful in cases where software coherency is desired for masters issuing back-to-back read/write
11855 * transactions without waiting for write/read responses. Note that this register has an effect
11856 * only if necessary logic is instantiated via the DDRC_RDWR_ORDERED_n parameter.
11857 */
11858#define DDRC_PCFGR_0_rdwr_ordered_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGR_0_rdwr_ordered_en_SHIFT)) & DDRC_PCFGR_0_rdwr_ordered_en_MASK)
11859/*! @} */
11860
11861/*! @name PCFGW_0 - Port n Configuration Write Register */
11862/*! @{ */
11863#define DDRC_PCFGW_0_wr_port_priority_MASK (0x3FFU)
11864#define DDRC_PCFGW_0_wr_port_priority_SHIFT (0U)
11865/*! wr_port_priority - Determines the initial load value of write aging counters. These counters
11866 * will be parallel loaded after reset, or after each grant to the corresponding port. The aging
11867 * counters down-count every clock cycle where the port is requesting but not granted. The higher
11868 * significant 5-bits of the write aging counter sets the initial priority of the write channel of
11869 * a given port. Port's priority will increase as the higher significant 5-bits of the counter
11870 * starts to decrease. When the aging counter becomes 0, the corresponding port channel will have
11871 * the highest priority level. For multi-port configurations, the aging counters cannot be used to
11872 * set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is
11873 * still applicable). For single port configurations, the aging counters are only used when they
11874 * timeout (become 0) to force read-write direction switching. Note: The two LSBs of this register
11875 * field are tied internally to 2'b00.
11876 */
11877#define DDRC_PCFGW_0_wr_port_priority(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_priority_SHIFT)) & DDRC_PCFGW_0_wr_port_priority_MASK)
11878#define DDRC_PCFGW_0_wr_port_aging_en_MASK (0x1000U)
11879#define DDRC_PCFGW_0_wr_port_aging_en_SHIFT (12U)
11880/*! wr_port_aging_en - If set to 1, enables aging function for the write channel of the port.
11881 */
11882#define DDRC_PCFGW_0_wr_port_aging_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_aging_en_SHIFT)) & DDRC_PCFGW_0_wr_port_aging_en_MASK)
11883#define DDRC_PCFGW_0_wr_port_urgent_en_MASK (0x2000U)
11884#define DDRC_PCFGW_0_wr_port_urgent_en_SHIFT (13U)
11885/*! wr_port_urgent_en - If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled
11886 * and awurgent is asserted by the master, that port becomes the highest priority and
11887 * co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register. Note that
11888 * awurgent signal can be asserted anytime and as long as required which is independent of address
11889 * handshaking (it is not associated with any particular command).
11890 */
11891#define DDRC_PCFGW_0_wr_port_urgent_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_urgent_en_SHIFT)) & DDRC_PCFGW_0_wr_port_urgent_en_MASK)
11892#define DDRC_PCFGW_0_wr_port_pagematch_en_MASK (0x4000U)
11893#define DDRC_PCFGW_0_wr_port_pagematch_en_SHIFT (14U)
11894/*! wr_port_pagematch_en - If set to 1, enables the Page Match feature. If enabled, once a
11895 * requesting port is granted, the port is continued to be granted if the following immediate commands are
11896 * to the same memory page (same bank and same row). See also related PCCFG.pagematch_limit
11897 * register.
11898 */
11899#define DDRC_PCFGW_0_wr_port_pagematch_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGW_0_wr_port_pagematch_en_SHIFT)) & DDRC_PCFGW_0_wr_port_pagematch_en_MASK)
11900/*! @} */
11901
11902/*! @name PCTRL_0 - Port n Control Register */
11903/*! @{ */
11904#define DDRC_PCTRL_0_port_en_MASK (0x1U)
11905#define DDRC_PCTRL_0_port_en_SHIFT (0U)
11906/*! port_en - Enables AXI port n.
11907 */
11908#define DDRC_PCTRL_0_port_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCTRL_0_port_en_SHIFT)) & DDRC_PCTRL_0_port_en_MASK)
11909/*! @} */
11910
11911/*! @name PCFGQOS0_0 - Port n Read QoS Configuration Register 0 */
11912/*! @{ */
11913#define DDRC_PCFGQOS0_0_rqos_map_level1_MASK (0xFU)
11914#define DDRC_PCFGQOS0_0_rqos_map_level1_SHIFT (0U)
11915/*! rqos_map_level1 - Separation level1 indicating the end of region0 mapping; start of region0 is
11916 * 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which
11917 * corresponds to arqos. Note that for PA, arqos values are used directly as port priorities, where
11918 * the higher the value corresponds to higher port priority. All of the map_level* registers must
11919 * be set to distinct values.
11920 */
11921#define DDRC_PCFGQOS0_0_rqos_map_level1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_level1_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_level1_MASK)
11922#define DDRC_PCFGQOS0_0_rqos_map_region0_MASK (0x30000U)
11923#define DDRC_PCFGQOS0_0_rqos_map_region0_SHIFT (16U)
11924/*! rqos_map_region0 - This bitfield indicates the traffic class of region 0. Valid values are: 0:
11925 * LPR, 1: VPR, 2: HPR. For dual address queue configurations, region 0 maps to the blue address
11926 * queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support is disabled
11927 * (DDRC_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR
11928 * traffic.
11929 */
11930#define DDRC_PCFGQOS0_0_rqos_map_region0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_region0_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_region0_MASK)
11931#define DDRC_PCFGQOS0_0_rqos_map_region1_MASK (0x300000U)
11932#define DDRC_PCFGQOS0_0_rqos_map_region1_SHIFT (20U)
11933/*! rqos_map_region1 - This bitfield indicates the traffic class of region 1. Valid values are: 0 :
11934 * LPR, 1: VPR, 2: HPR. For dual address queue configurations, region1 maps to the blue address
11935 * queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is disabled
11936 * (DDRC_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR
11937 * traffic.
11938 */
11939#define DDRC_PCFGQOS0_0_rqos_map_region1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS0_0_rqos_map_region1_SHIFT)) & DDRC_PCFGQOS0_0_rqos_map_region1_MASK)
11940/*! @} */
11941
11942/*! @name PCFGQOS1_0 - Port n Read QoS Configuration Register 1 */
11943/*! @{ */
11944#define DDRC_PCFGQOS1_0_rqos_map_timeoutb_MASK (0x7FFU)
11945#define DDRC_PCFGQOS1_0_rqos_map_timeoutb_SHIFT (0U)
11946/*! rqos_map_timeoutb - Specifies the timeout value for transactions mapped to the blue address queue.
11947 */
11948#define DDRC_PCFGQOS1_0_rqos_map_timeoutb(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS1_0_rqos_map_timeoutb_SHIFT)) & DDRC_PCFGQOS1_0_rqos_map_timeoutb_MASK)
11949#define DDRC_PCFGQOS1_0_rqos_map_timeoutr_MASK (0x7FF0000U)
11950#define DDRC_PCFGQOS1_0_rqos_map_timeoutr_SHIFT (16U)
11951/*! rqos_map_timeoutr - Specifies the timeout value for transactions mapped to the red address queue.
11952 */
11953#define DDRC_PCFGQOS1_0_rqos_map_timeoutr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGQOS1_0_rqos_map_timeoutr_SHIFT)) & DDRC_PCFGQOS1_0_rqos_map_timeoutr_MASK)
11954/*! @} */
11955
11956/*! @name PCFGWQOS0_0 - Port n Write QoS Configuration Register 0 */
11957/*! @{ */
11958#define DDRC_PCFGWQOS0_0_wqos_map_level_MASK (0xFU)
11959#define DDRC_PCFGWQOS0_0_wqos_map_level_SHIFT (0U)
11960/*! wqos_map_level - Separation level indicating the end of region0 mapping; start of region0 is 0.
11961 * Possible values for level1 are 0 to 14 which corresponds to awqos. Note that for PA, awqos
11962 * values are used directly as port priorities, where the higher the value corresponds to higher
11963 * port priority.
11964 */
11965#define DDRC_PCFGWQOS0_0_wqos_map_level(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_level_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_level_MASK)
11966#define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U)
11967#define DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT (16U)
11968/*! wqos_map_region0 - This bitfield indicates the traffic class of region 0. Valid values are: 0:
11969 * NPW, 1: VPW. When VPW support is disabled (DDRC_VPW_EN = 0) and traffic class of region0 is set
11970 * to 1 (VPW), VPW traffic is aliased to NPW traffic.
11971 */
11972#define DDRC_PCFGWQOS0_0_wqos_map_region0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
11973#define DDRC_PCFGWQOS0_0_wqos_map_region1_MASK (0x300000U)
11974#define DDRC_PCFGWQOS0_0_wqos_map_region1_SHIFT (20U)
11975/*! wqos_map_region1 - This bitfield indicates the traffic class of region 1. Valid values are: 0:
11976 * NPW, 1: VPW. When VPW support is disabled (DDRC_VPW_EN = 0) and traffic class of region 1 is
11977 * set to 1 (VPW), VPW traffic is aliased to LPW traffic.
11978 */
11979#define DDRC_PCFGWQOS0_0_wqos_map_region1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region1_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region1_MASK)
11980/*! @} */
11981
11982/*! @name PCFGWQOS1_0 - Port n Write QoS Configuration Register 1 */
11983/*! @{ */
11984#define DDRC_PCFGWQOS1_0_wqos_map_timeout_MASK (0x7FFU)
11985#define DDRC_PCFGWQOS1_0_wqos_map_timeout_SHIFT (0U)
11986/*! wqos_map_timeout - Specifies the timeout value for write transactions.
11987 */
11988#define DDRC_PCFGWQOS1_0_wqos_map_timeout(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PCFGWQOS1_0_wqos_map_timeout_SHIFT)) & DDRC_PCFGWQOS1_0_wqos_map_timeout_MASK)
11989/*! @} */
11990
11991/*! @name DERATEEN_SHADOW - [SHADOW] Temperature Derate Enable Register */
11992/*! @{ */
11993#define DDRC_DERATEEN_SHADOW_derate_enable_MASK (0x1U)
11994#define DDRC_DERATEEN_SHADOW_derate_enable_SHIFT (0U)
11995/*! derate_enable - Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing
11996 * parameter derating is enabled using MR4 read value. Present only in designs configured to support
11997 * LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4 mode.
11998 */
11999#define DDRC_DERATEEN_SHADOW_derate_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_enable_SHIFT)) & DDRC_DERATEEN_SHADOW_derate_enable_MASK)
12000#define DDRC_DERATEEN_SHADOW_derate_value_MASK (0x2U)
12001#define DDRC_DERATEEN_SHADOW_derate_value_SHIFT (1U)
12002/*! derate_value - Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in
12003 * designs configured to support LPDDR2/LPDDR3/LPDDR4 Set to 0 for all LPDDR2 speed grades as
12004 * derating value of +1.875 ns is less than a core_ddrc_core_clk period. For LPDDR3/4, if the period of
12005 * core_ddrc_core_clk is less than 1.875ns, this register field should be set to 1; otherwise it
12006 * should be set to 0.
12007 */
12008#define DDRC_DERATEEN_SHADOW_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_value_SHIFT)) & DDRC_DERATEEN_SHADOW_derate_value_MASK)
12009#define DDRC_DERATEEN_SHADOW_derate_byte_MASK (0xF0U)
12010#define DDRC_DERATEEN_SHADOW_derate_byte_SHIFT (4U)
12011/*! derate_byte - Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4
12012 * Indicates which byte of the MRR data is used for derating. The maximum valid value depends on
12013 * MEMC_DRAM_TOTAL_DATA_WIDTH.
12014 */
12015#define DDRC_DERATEEN_SHADOW_derate_byte(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_derate_byte_SHIFT)) & DDRC_DERATEEN_SHADOW_derate_byte_MASK)
12016#define DDRC_DERATEEN_SHADOW_rc_derate_value_MASK (0x300U)
12017#define DDRC_DERATEEN_SHADOW_rc_derate_value_SHIFT (8U)
12018/*! rc_derate_value - Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2.
12019 * - 2 - Derating uses +3. - 3 - Derating uses +4. Present only in designs configured to support
12020 * LPDDR4. The required number of cycles for derating can be determined by dividing 3.75ns by
12021 * the core_ddrc_core_clk period, and rounding up the next integer.
12022 */
12023#define DDRC_DERATEEN_SHADOW_rc_derate_value(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEEN_SHADOW_rc_derate_value_SHIFT)) & DDRC_DERATEEN_SHADOW_rc_derate_value_MASK)
12024/*! @} */
12025
12026/*! @name DERATEINT_SHADOW - [SHADOW] Temperature Derate Interval Register */
12027/*! @{ */
12028#define DDRC_DERATEINT_SHADOW_mr4_read_interval_MASK (0xFFFFFFFFU)
12029#define DDRC_DERATEINT_SHADOW_mr4_read_interval_SHIFT (0U)
12030/*! mr4_read_interval - Interval between two MR4 reads, used to derate the timing parameters.
12031 * Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to
12032 * zero. Unit: DFI clock cycle.
12033 */
12034#define DDRC_DERATEINT_SHADOW_mr4_read_interval(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DERATEINT_SHADOW_mr4_read_interval_SHIFT)) & DDRC_DERATEINT_SHADOW_mr4_read_interval_MASK)
12035/*! @} */
12036
12037/*! @name RFSHCTL0_SHADOW - [SHADOW] Refresh Control Register 0 */
12038/*! @{ */
12039#define DDRC_RFSHCTL0_SHADOW_per_bank_refresh_MASK (0x4U)
12040#define DDRC_RFSHCTL0_SHADOW_per_bank_refresh_SHIFT (2U)
12041/*! per_bank_refresh - - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows
12042 * traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but should
12043 * be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to support
12044 * LPDDR2/LPDDR3/LPDDR4
12045 */
12046#define DDRC_RFSHCTL0_SHADOW_per_bank_refresh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_per_bank_refresh_SHIFT)) & DDRC_RFSHCTL0_SHADOW_per_bank_refresh_MASK)
12047#define DDRC_RFSHCTL0_SHADOW_refresh_burst_MASK (0x1F0U)
12048#define DDRC_RFSHCTL0_SHADOW_refresh_burst_SHIFT (4U)
12049/*! refresh_burst - The programmed value + 1 is the number of refresh timeouts that is allowed to
12050 * accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to
12051 * perform a refresh is a one-time penalty that must be paid for each group of refreshes.
12052 * Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings.
12053 * Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases
12054 * the worst-case latency associated with refreshes. - 0 - single refresh - 1 - burst-of-2
12055 * refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to section 3.9 of
12056 * DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not
12057 * per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh
12058 * feature. In DDR4 mode, according to Fine Granularity feature, 8 refreshes can be postponed in 1X
12059 * mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated updates, care
12060 * must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated
12061 * due to a PHY-initiated update occurring shortly before a refresh burst was due. In this
12062 * situation, the refresh burst will be delayed until the PHY-initiated update is complete.
12063 */
12064#define DDRC_RFSHCTL0_SHADOW_refresh_burst(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_burst_SHIFT)) & DDRC_RFSHCTL0_SHADOW_refresh_burst_MASK)
12065#define DDRC_RFSHCTL0_SHADOW_refresh_to_x32_MASK (0x1F000U)
12066#define DDRC_RFSHCTL0_SHADOW_refresh_to_x32_SHIFT (12U)
12067/*! refresh_to_x32 - If the refresh timer (tRFCnom, also known as tREFI) has expired at least once,
12068 * but it has not expired (RFSHCTL0.refresh_burst+1) times yet, then a speculative refresh may be
12069 * performed. A speculative refresh is a refresh performed at a time when refresh would be
12070 * useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time
12071 * determined by this RFSHCTL0.refresh_to_x32 and the refresh timer has expired at least once since
12072 * the last refresh, then a speculative refresh is performed. Speculative refreshes continues
12073 * successively until there are no refreshes pending or until new reads or writes are issued to the
12074 * DDRC. FOR PERFORMANCE ONLY. Unit: Multiples of 32 DFI clocks.
12075 */
12076#define DDRC_RFSHCTL0_SHADOW_refresh_to_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_to_x32_SHIFT)) & DDRC_RFSHCTL0_SHADOW_refresh_to_x32_MASK)
12077#define DDRC_RFSHCTL0_SHADOW_refresh_margin_MASK (0xF00000U)
12078#define DDRC_RFSHCTL0_SHADOW_refresh_margin_SHIFT (20U)
12079/*! refresh_margin - Threshold value in number of DFI clock cycles before the critical refresh or
12080 * page timer expires. A critical refresh is to be issued before this threshold is reached. It is
12081 * recommended that this not be changed from the default value, currently shown as 0x2. It must
12082 * always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4,
12083 * internally used t_rfc_nom_x32 may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled
12084 * (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_nom_x32 will be equal to
12085 * RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 DFI clocks.
12086 */
12087#define DDRC_RFSHCTL0_SHADOW_refresh_margin(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHCTL0_SHADOW_refresh_margin_SHIFT)) & DDRC_RFSHCTL0_SHADOW_refresh_margin_MASK)
12088/*! @} */
12089
12090/*! @name RFSHTMG_SHADOW - [SHADOW] Refresh Timing Register */
12091/*! @{ */
12092#define DDRC_RFSHTMG_SHADOW_t_rfc_min_MASK (0x3FFU)
12093#define DDRC_RFSHTMG_SHADOW_t_rfc_min_SHIFT (0U)
12094/*! t_rfc_min - tRFC (min): Minimum time from refresh to refresh or activate. When the controller is
12095 * operating in 1:1 mode, t_rfc_min should be set to RoundUp(tRFCmin/tCK). When the controller
12096 * is operating in 1:2 mode, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In
12097 * LPDDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations
12098 * is equal to tRFCab - if using per-bank refreshes, the tRFCmin value in the above equations is
12099 * equal to tRFCpb In DDR4 mode, the tRFCmin value in the above equations is different depending
12100 * on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the
12101 * appropriate value from the spec based on the 'refresh_mode' and the device density that is used.
12102 * Unit: Clocks.
12103 */
12104#define DDRC_RFSHTMG_SHADOW_t_rfc_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_t_rfc_min_SHIFT)) & DDRC_RFSHTMG_SHADOW_t_rfc_min_MASK)
12105#define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_MASK (0x8000U)
12106#define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_SHIFT (15U)
12107/*! lpddr3_trefbw_en - Used only when LPDDR3 memory type is connected. Should only be changed when
12108 * DDRC is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3
12109 * devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not: - 0 - tREFBW
12110 * parameter not used - 1 - tREFBW parameter used
12111 */
12112#define DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_SHIFT)) & DDRC_RFSHTMG_SHADOW_lpddr3_trefbw_en_MASK)
12113#define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_MASK (0xFFF0000U)
12114#define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_SHIFT (16U)
12115/*! t_rfc_nom_x32 - tREFI: Average time interval between refreshes per rank (Specification: 7.8us
12116 * for DDR2, DDR3 and DDR4. See JEDEC specification for mDDR, LPDDR2, LPDDR3 and LPDDR4). For
12117 * LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0), this register
12118 * should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this
12119 * register should be set to tREFIpb When the controller is operating in 1:2 frequency ratio mode,
12120 * program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI value is different depending
12121 * on the refresh mode. The user should program the appropriate value from the spec based on the
12122 * value programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be
12123 * greater than RFSHTMG.t_rfc_min, and RFSHTMG.t_rfc_nom_x32 must be greater than 0x1. - Non-DDR4 or
12124 * DDR4 Fixed 1x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0xFFE. - DDR4 Fixed
12125 * 2x mode: RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x7FF. - DDR4 Fixed 4x mode:
12126 * RFSHTMG.t_rfc_nom_x32 must be less than or equal to 0x3FF. Unit: Multiples of 32 clocks.
12127 */
12128#define DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_SHIFT)) & DDRC_RFSHTMG_SHADOW_t_rfc_nom_x32_MASK)
12129/*! @} */
12130
12131/*! @name INIT3_SHADOW - [SHADOW] SDRAM Initialization Register 3 */
12132/*! @{ */
12133#define DDRC_INIT3_SHADOW_emr_MASK (0xFFFFU)
12134#define DDRC_INIT3_SHADOW_emr_SHIFT (0U)
12135/*! emr - DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this
12136 * register is ignored. The DDRC sets those bits appropriately. DDR3/DDR4: Value to write to MR1
12137 * register Set bit 7 to 0. If PHY-evaluation mode training is enabled, this bit is set appropriately by
12138 * the DDRC during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 -
12139 * Value to write to MR2 register
12140 */
12141#define DDRC_INIT3_SHADOW_emr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_SHADOW_emr_SHIFT)) & DDRC_INIT3_SHADOW_emr_MASK)
12142#define DDRC_INIT3_SHADOW_mr_MASK (0xFFFF0000U)
12143#define DDRC_INIT3_SHADOW_mr_SHIFT (16U)
12144/*! mr - DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The
12145 * DDRC sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to
12146 * write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1 register
12147 */
12148#define DDRC_INIT3_SHADOW_mr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT3_SHADOW_mr_SHIFT)) & DDRC_INIT3_SHADOW_mr_MASK)
12149/*! @} */
12150
12151/*! @name INIT4_SHADOW - [SHADOW] SDRAM Initialization Register 4 */
12152/*! @{ */
12153#define DDRC_INIT4_SHADOW_emr3_MASK (0xFFFFU)
12154#define DDRC_INIT4_SHADOW_emr3_SHIFT (0U)
12155/*! emr3 - DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register
12156 * mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to write to MR13 register
12157 */
12158#define DDRC_INIT4_SHADOW_emr3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_SHADOW_emr3_SHIFT)) & DDRC_INIT4_SHADOW_emr3_MASK)
12159#define DDRC_INIT4_SHADOW_emr2_MASK (0xFFFF0000U)
12160#define DDRC_INIT4_SHADOW_emr2_SHIFT (16U)
12161/*! emr2 - DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register
12162 * LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 register mDDR: Unused
12163 */
12164#define DDRC_INIT4_SHADOW_emr2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT4_SHADOW_emr2_SHIFT)) & DDRC_INIT4_SHADOW_emr2_MASK)
12165/*! @} */
12166
12167/*! @name INIT6_SHADOW - [SHADOW] SDRAM Initialization Register 6 */
12168/*! @{ */
12169#define DDRC_INIT6_SHADOW_mr5_MASK (0xFFFFU)
12170#define DDRC_INIT6_SHADOW_mr5_SHIFT (0U)
12171/*! mr5 - DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.
12172 */
12173#define DDRC_INIT6_SHADOW_mr5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_SHADOW_mr5_SHIFT)) & DDRC_INIT6_SHADOW_mr5_MASK)
12174#define DDRC_INIT6_SHADOW_mr4_MASK (0xFFFF0000U)
12175#define DDRC_INIT6_SHADOW_mr4_SHIFT (16U)
12176/*! mr4 - DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.
12177 */
12178#define DDRC_INIT6_SHADOW_mr4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT6_SHADOW_mr4_SHIFT)) & DDRC_INIT6_SHADOW_mr4_MASK)
12179/*! @} */
12180
12181/*! @name INIT7_SHADOW - [SHADOW] SDRAM Initialization Register 7 */
12182/*! @{ */
12183#define DDRC_INIT7_SHADOW_mr6_MASK (0xFFFF0000U)
12184#define DDRC_INIT7_SHADOW_mr6_SHIFT (16U)
12185/*! mr6 - DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.
12186 */
12187#define DDRC_INIT7_SHADOW_mr6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_INIT7_SHADOW_mr6_SHIFT)) & DDRC_INIT7_SHADOW_mr6_MASK)
12188/*! @} */
12189
12190/*! @name DRAMTMG0_SHADOW - [SHADOW] SDRAM Timing Register 0 */
12191/*! @{ */
12192#define DDRC_DRAMTMG0_SHADOW_t_ras_min_MASK (0x3FU)
12193#define DDRC_DRAMTMG0_SHADOW_t_ras_min_SHIFT (0U)
12194/*! t_ras_min - tRAS(min): Minimum time between activate and precharge to the same bank. When the
12195 * controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2. No rounding
12196 * up. When the controller is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode,
12197 * program this to (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks
12198 */
12199#define DDRC_DRAMTMG0_SHADOW_t_ras_min(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_ras_min_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_ras_min_MASK)
12200#define DDRC_DRAMTMG0_SHADOW_t_ras_max_MASK (0x7F00U)
12201#define DDRC_DRAMTMG0_SHADOW_t_ras_max_SHIFT (8U)
12202/*! t_ras_max - tRAS(max): Maximum time between activate and precharge to same bank. This is the
12203 * maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid.
12204 * When the controller is operating in 1:2 frequency ratio mode, program this to (tRAS(max)-1)/2.
12205 * No rounding up. Unit: Multiples of 1024 clocks.
12206 */
12207#define DDRC_DRAMTMG0_SHADOW_t_ras_max(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_ras_max_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_ras_max_MASK)
12208#define DDRC_DRAMTMG0_SHADOW_t_faw_MASK (0x3F0000U)
12209#define DDRC_DRAMTMG0_SHADOW_t_faw_SHIFT (16U)
12210/*! t_faw - tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank
12211 * design, at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller
12212 * is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next
12213 * integer value. In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency
12214 * mode. Unit: Clocks
12215 */
12216#define DDRC_DRAMTMG0_SHADOW_t_faw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_t_faw_SHIFT)) & DDRC_DRAMTMG0_SHADOW_t_faw_MASK)
12217#define DDRC_DRAMTMG0_SHADOW_wr2pre_MASK (0x7F000000U)
12218#define DDRC_DRAMTMG0_SHADOW_wr2pre_SHIFT (24U)
12219/*! wr2pre - Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL
12220 * + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower
12221 * frequencies where: - WL = write latency - BL = burst length. This must match the value programmed in
12222 * the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present.
12223 * - tWR = Write recovery time. This comes directly from the SDRAM specification. Add one extra
12224 * cycle for LPDDR2/LPDDR3/LPDDR4 for this parameter. When the controller is operating in 1:2
12225 * frequency ratio mode, 1T mode, divide the above value by 2. No rounding up. When the controller
12226 * is operating in 1:2 frequency ratio mode, 2T mode or LPDDR4 mode, divide the above value by 2
12227 * and round it up to the next integer value. Note that, depending on the PHY, if using LRDIMM, it
12228 * may be necessary to adjust the value of this parameter to compensate for the extra cycle of
12229 * latency through the LRDIMM.
12230 */
12231#define DDRC_DRAMTMG0_SHADOW_wr2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG0_SHADOW_wr2pre_SHIFT)) & DDRC_DRAMTMG0_SHADOW_wr2pre_MASK)
12232/*! @} */
12233
12234/*! @name DRAMTMG1_SHADOW - [SHADOW] SDRAM Timing Register 1 */
12235/*! @{ */
12236#define DDRC_DRAMTMG1_SHADOW_t_rc_MASK (0x7FU)
12237#define DDRC_DRAMTMG1_SHADOW_t_rc_SHIFT (0U)
12238/*! t_rc - tRC: Minimum time between activates to same bank. When the controller is operating in 1:2
12239 * frequency ratio mode, program this to (tRC/2) and round up to next integer value. Unit:
12240 * Clocks.
12241 */
12242#define DDRC_DRAMTMG1_SHADOW_t_rc(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_t_rc_SHIFT)) & DDRC_DRAMTMG1_SHADOW_t_rc_MASK)
12243#define DDRC_DRAMTMG1_SHADOW_rd2pre_MASK (0x3F00U)
12244#define DDRC_DRAMTMG1_SHADOW_rd2pre_SHIFT (8U)
12245/*! rd2pre - tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP,
12246 * 2) - 2 - DDR3: tAL + max (tRTP, 4) - DDR4: Max of following two equations: tAL + max (tRTP, 4)
12247 * or, RL + BL/2 - tRP (*). - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4:
12248 * LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4
12249 * - LPDDR4: BL/2 + max(tRTP,8) - 8 (*) When both DDR4 SDRAM and ST-MRAM are used simultaneously,
12250 * use SDRAM's tRP value for calculation. When the controller is operating in 1:2 mode, 1T mode,
12251 * divide the above value by 2. No rounding up. When the controller is operating in 1:2 mode, 2T
12252 * mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.
12253 * Unit: Clocks.
12254 */
12255#define DDRC_DRAMTMG1_SHADOW_rd2pre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_rd2pre_SHIFT)) & DDRC_DRAMTMG1_SHADOW_rd2pre_MASK)
12256#define DDRC_DRAMTMG1_SHADOW_t_xp_MASK (0x1F0000U)
12257#define DDRC_DRAMTMG1_SHADOW_t_xp_SHIFT (16U)
12258/*! t_xp - tXP: Minimum time after power-down exit to any operation. For DDR3, this should be
12259 * programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used,
12260 * set to (tXP+PL) instead. When the controller is operating in 1:2 frequency ratio mode, program
12261 * this to (tXP/2) and round it up to the next integer value. Units: Clocks
12262 */
12263#define DDRC_DRAMTMG1_SHADOW_t_xp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG1_SHADOW_t_xp_SHIFT)) & DDRC_DRAMTMG1_SHADOW_t_xp_MASK)
12264/*! @} */
12265
12266/*! @name DRAMTMG2_SHADOW - [SHADOW] SDRAM Timing Register 2 */
12267/*! @{ */
12268#define DDRC_DRAMTMG2_SHADOW_wr2rd_MASK (0x3FU)
12269#define DDRC_DRAMTMG2_SHADOW_wr2rd_SHIFT (0U)
12270/*! wr2rd - DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from
12271 * write command to read command for same bank group. In others, minimum time from write command to
12272 * read command. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and
12273 * global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL
12274 * = burst length. This must match the value programmed in the BL bit of the mode register to
12275 * the SDRAM - tWTR_L = internal write to read command delay for same bank group. This comes
12276 * directly from the SDRAM specification. - tWTR = internal write to read command delay. This comes
12277 * directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation.
12278 * When the controller is operating in 1:2 mode, divide the value calculated using the above
12279 * equation by 2, and round it up to next integer.
12280 */
12281#define DDRC_DRAMTMG2_SHADOW_wr2rd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_wr2rd_SHIFT)) & DDRC_DRAMTMG2_SHADOW_wr2rd_MASK)
12282#define DDRC_DRAMTMG2_SHADOW_rd2wr_MASK (0x3F00U)
12283#define DDRC_DRAMTMG2_SHADOW_rd2wr_SHIFT (8U)
12284/*! rd2wr - DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL
12285 * + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK)
12286 * + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + BL/2 + RU(tDQSCKmax/tCK) +
12287 * RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command.
12288 * Include time for bus turnaround and all per-bank, per-rank, and global constraints. Please see
12289 * the relevant PHY databook for details of what should be included here. Unit: Clocks. Where: -
12290 * WL = write latency - BL = burst length. This must match the value programmed in the BL bit of
12291 * the mode register to the SDRAM - RL = read latency = CAS latency - WR_PREAMBLE = write
12292 * preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to
12293 * LPDDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated
12294 * tDQSCKmax should be used. When the controller is operating in 1:2 frequency ratio mode, divide the
12295 * value calculated using the above equation by 2, and round it up to next integer. Note that,
12296 * depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter
12297 * to compensate for the extra cycle of latency through the LRDIMM.
12298 */
12299#define DDRC_DRAMTMG2_SHADOW_rd2wr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_rd2wr_SHIFT)) & DDRC_DRAMTMG2_SHADOW_rd2wr_MASK)
12300#define DDRC_DRAMTMG2_SHADOW_read_latency_MASK (0x3F0000U)
12301#define DDRC_DRAMTMG2_SHADOW_read_latency_SHIFT (16U)
12302/*! read_latency - Set to RL Time from read command to read data on SDRAM interface. This must be
12303 * set to RL. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust
12304 * the value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM. When
12305 * the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the
12306 * above equation by 2, and round it up to next integer. This register field is not required for
12307 * DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latencies defined in
12308 * DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
12309 */
12310#define DDRC_DRAMTMG2_SHADOW_read_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_read_latency_SHIFT)) & DDRC_DRAMTMG2_SHADOW_read_latency_MASK)
12311#define DDRC_DRAMTMG2_SHADOW_write_latency_MASK (0x3F000000U)
12312#define DDRC_DRAMTMG2_SHADOW_write_latency_SHIFT (24U)
12313/*! write_latency - Set to WL Time from write command to write data on SDRAM interface. This must be
12314 * set to WL. For mDDR, it should normally be set to 1. Note that, depending on the PHY, if
12315 * using RDIMM/LRDIMM, it may be necessary to adjust the value of WL to compensate for the extra
12316 * cycle of latency through the RDIMM/LRDIMM. When the controller is operating in 1:2 frequency ratio
12317 * mode, divide the value calculated using the above equation by 2, and round it up to next
12318 * integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set),
12319 * as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those
12320 * protocols Unit: clocks
12321 */
12322#define DDRC_DRAMTMG2_SHADOW_write_latency(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG2_SHADOW_write_latency_SHIFT)) & DDRC_DRAMTMG2_SHADOW_write_latency_MASK)
12323/*! @} */
12324
12325/*! @name DRAMTMG3_SHADOW - [SHADOW] SDRAM Timing Register 3 */
12326/*! @{ */
12327#define DDRC_DRAMTMG3_SHADOW_t_mod_MASK (0x3FFU)
12328#define DDRC_DRAMTMG3_SHADOW_t_mod_SHIFT (0U)
12329/*! t_mod - tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and
12330 * following non-load mode command. If C/A parity for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead.
12331 * Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to
12332 * next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using
12333 * RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this parameter to
12334 * compensate for the extra cycle of latency applied to mode register writes by the RDIMM/LRDIMM chip.
12335 * Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller
12336 * is operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if
12337 * controller is operating in 1:2 frequency ratio mode.
12338 */
12339#define DDRC_DRAMTMG3_SHADOW_t_mod(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mod_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mod_MASK)
12340#define DDRC_DRAMTMG3_SHADOW_t_mrd_MASK (0x3F000U)
12341#define DDRC_DRAMTMG3_SHADOW_t_mrd_SHIFT (12U)
12342/*! t_mrd - tMRD: Cycles to wait after a mode register write or read. Depending on the connected
12343 * SDRAM, tMRD represents: DDR2/mDDR: Time from MRS to any command DDR3/4: Time from MRS to MRS
12344 * command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command. When the controller is
12345 * operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer
12346 * value. If C/A parity for DDR4 is used, set to tMRD_PAR(tMOD+PL) instead.
12347 */
12348#define DDRC_DRAMTMG3_SHADOW_t_mrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mrd_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mrd_MASK)
12349#define DDRC_DRAMTMG3_SHADOW_t_mrw_MASK (0x3FF00000U)
12350#define DDRC_DRAMTMG3_SHADOW_t_mrw_SHIFT (20U)
12351/*! t_mrw - Time to wait after a mode register write or read (MRW or MRR). Present only in designs
12352 * configured to support LPDDR2, LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3
12353 * typically requires value of 10. LPDDR4: Set this to the larger of tMRW and tMRWCKEL. For LPDDR2,
12354 * this register is used for the time from a MRW/MRR to all other commands. When the controller
12355 * is operating in 1:2 frequency ratio mode, program this to the above values divided by 2 and
12356 * round it up to the next integer value. For LDPDR3, this register is used for the time from a
12357 * MRW/MRR to a MRW/MRR.
12358 */
12359#define DDRC_DRAMTMG3_SHADOW_t_mrw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG3_SHADOW_t_mrw_SHIFT)) & DDRC_DRAMTMG3_SHADOW_t_mrw_MASK)
12360/*! @} */
12361
12362/*! @name DRAMTMG4_SHADOW - [SHADOW] SDRAM Timing Register 4 */
12363/*! @{ */
12364#define DDRC_DRAMTMG4_SHADOW_t_rp_MASK (0x1FU)
12365#define DDRC_DRAMTMG4_SHADOW_t_rp_SHIFT (0U)
12366/*! t_rp - tRP: Minimum time from precharge to activate of same bank. When the controller is
12367 * operating in 1:1 frequency ratio mode, t_rp should be set to RoundUp(tRP/tCK). When the controller is
12368 * operating in 1:2 frequency ratio mode, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) +
12369 * 1. When the controller is operating in 1:2 frequency ratio mode in LPDDR4, t_rp should be set
12370 * to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
12371 */
12372#define DDRC_DRAMTMG4_SHADOW_t_rp(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rp_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rp_MASK)
12373#define DDRC_DRAMTMG4_SHADOW_t_rrd_MASK (0xF00U)
12374#define DDRC_DRAMTMG4_SHADOW_t_rrd_SHIFT (8U)
12375/*! t_rrd - DDR4: tRRD_L: Minimum time between activates from bank "a" to bank "b" for same bank
12376 * group. Others: tRRD: Minimum time between activates from bank "a" to bank "b" When the controller
12377 * is operating in 1:2 frequency ratio mode, program this to (tRRD_L/2 or tRRD/2) and round it
12378 * up to the next integer value. Unit: Clocks.
12379 */
12380#define DDRC_DRAMTMG4_SHADOW_t_rrd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rrd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rrd_MASK)
12381#define DDRC_DRAMTMG4_SHADOW_t_ccd_MASK (0xF0000U)
12382#define DDRC_DRAMTMG4_SHADOW_t_ccd_SHIFT (16U)
12383/*! t_ccd - DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank
12384 * group. Others: tCCD: This is the minimum time between two reads or two writes. When the
12385 * controller is operating in 1:2 frequency ratio mode, program this to (tCCD_L/2 or tCCD/2) and round it
12386 * up to the next integer value. Unit: clocks.
12387 */
12388#define DDRC_DRAMTMG4_SHADOW_t_ccd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_ccd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_ccd_MASK)
12389#define DDRC_DRAMTMG4_SHADOW_t_rcd_MASK (0x1F000000U)
12390#define DDRC_DRAMTMG4_SHADOW_t_rcd_SHIFT (24U)
12391/*! t_rcd - tRCD - tAL: Minimum time from activate to read or write command to same bank. When the
12392 * controller is operating in 1:2 frequency ratio mode, program this to ((tRCD - tAL)/2) and round
12393 * it up to the next integer value. Minimum value allowed for this register is 1, which implies
12394 * minimum (tRCD - tAL) value to be 2 when the controller is operating in 1:2 frequency ratio
12395 * mode. Unit: Clocks.
12396 */
12397#define DDRC_DRAMTMG4_SHADOW_t_rcd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG4_SHADOW_t_rcd_SHIFT)) & DDRC_DRAMTMG4_SHADOW_t_rcd_MASK)
12398/*! @} */
12399
12400/*! @name DRAMTMG5_SHADOW - [SHADOW] SDRAM Timing Register 5 */
12401/*! @{ */
12402#define DDRC_DRAMTMG5_SHADOW_t_cke_MASK (0x1FU)
12403#define DDRC_DRAMTMG5_SHADOW_t_cke_SHIFT (0U)
12404/*! t_cke - Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. -
12405 * LPDDR2/LPDDR3 mode: Set this to the larger of tCKE or tCKESR - LPDDR4 mode: Set this to the larger of
12406 * tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set this to tCKE value. When
12407 * the controller is operating in 1:2 frequency ratio mode, program this to (value described
12408 * above)/2 and round it up to the next integer value. Unit: Clocks.
12409 */
12410#define DDRC_DRAMTMG5_SHADOW_t_cke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cke_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cke_MASK)
12411#define DDRC_DRAMTMG5_SHADOW_t_ckesr_MASK (0x3F00U)
12412#define DDRC_DRAMTMG5_SHADOW_t_ckesr_SHIFT (8U)
12413/*! t_ckesr - Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing
12414 * in memory clock cycles. Recommended settings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR
12415 * - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE + 1 (+ PL(parity
12416 * latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should be increased
12417 * by PL. When the controller is operating in 1:2 frequency ratio mode, program this to
12418 * recommended value divided by two and round it up to next integer.
12419 */
12420#define DDRC_DRAMTMG5_SHADOW_t_ckesr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_ckesr_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_ckesr_MASK)
12421#define DDRC_DRAMTMG5_SHADOW_t_cksre_MASK (0xF0000U)
12422#define DDRC_DRAMTMG5_SHADOW_t_cksre_SHIFT (16U)
12423/*! t_cksre - This is the time after Self Refresh Down Entry that CK is maintained as a valid clock.
12424 * Specifies the clock disable delay after SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 -
12425 * LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: max (10 ns, 5 tCK) (+
12426 * PL(parity latency)(*)) (*)Only if CRCPARCTL1.caparity_disable_before_sr=0, this register should
12427 * be increased by PL. When the controller is operating in 1:2 frequency ratio mode, program
12428 * this to recommended value divided by two and round it up to next integer.
12429 */
12430#define DDRC_DRAMTMG5_SHADOW_t_cksre(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cksre_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cksre_MASK)
12431#define DDRC_DRAMTMG5_SHADOW_t_cksrx_MASK (0xF000000U)
12432#define DDRC_DRAMTMG5_SHADOW_t_cksrx_SHIFT (24U)
12433/*! t_cksrx - This is the time before Self Refresh Exit that CK is maintained as a valid clock
12434 * before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR: 1 -
12435 * LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4: tCKSRX When the
12436 * controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by
12437 * two and round it up to next integer.
12438 */
12439#define DDRC_DRAMTMG5_SHADOW_t_cksrx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG5_SHADOW_t_cksrx_SHIFT)) & DDRC_DRAMTMG5_SHADOW_t_cksrx_MASK)
12440/*! @} */
12441
12442/*! @name DRAMTMG6_SHADOW - [SHADOW] SDRAM Timing Register 6 */
12443/*! @{ */
12444#define DDRC_DRAMTMG6_SHADOW_t_ckcsx_MASK (0xFU)
12445#define DDRC_DRAMTMG6_SHADOW_t_ckcsx_SHIFT (0U)
12446/*! t_ckcsx - This is the time before Clock Stop Exit that CK is maintained as a valid clock before
12447 * issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop
12448 * Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP + 2 - LPDDR4: tXP + 2
12449 * When the controller is operating in 1:2 frequency ratio mode, program this to recommended value
12450 * divided by two and round it up to next integer. This is only present for designs supporting
12451 * mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
12452 */
12453#define DDRC_DRAMTMG6_SHADOW_t_ckcsx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckcsx_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckcsx_MASK)
12454#define DDRC_DRAMTMG6_SHADOW_t_ckdpdx_MASK (0xF0000U)
12455#define DDRC_DRAMTMG6_SHADOW_t_ckdpdx_SHIFT (16U)
12456/*! t_ckdpdx - This is the time before Deep Power Down Exit that CK is maintained as a valid clock
12457 * before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR:
12458 * 1 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode,
12459 * program this to recommended value divided by two and round it up to next integer. This is only
12460 * present for designs supporting mDDR or LPDDR2 devices.
12461 */
12462#define DDRC_DRAMTMG6_SHADOW_t_ckdpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckdpdx_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckdpdx_MASK)
12463#define DDRC_DRAMTMG6_SHADOW_t_ckdpde_MASK (0xF000000U)
12464#define DDRC_DRAMTMG6_SHADOW_t_ckdpde_SHIFT (24U)
12465/*! t_ckdpde - This is the time after Deep Power Down Entry that CK is maintained as a valid clock.
12466 * Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 -
12467 * LPDDR3: 2 When the controller is operating in 1:2 frequency ratio mode, program this to
12468 * recommended value divided by two and round it up to next integer. This is only present for designs
12469 * supporting mDDR or LPDDR2/LPDDR3 devices.
12470 */
12471#define DDRC_DRAMTMG6_SHADOW_t_ckdpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG6_SHADOW_t_ckdpde_SHIFT)) & DDRC_DRAMTMG6_SHADOW_t_ckdpde_MASK)
12472/*! @} */
12473
12474/*! @name DRAMTMG7_SHADOW - [SHADOW] SDRAM Timing Register 7 */
12475/*! @{ */
12476#define DDRC_DRAMTMG7_SHADOW_t_ckpdx_MASK (0xFU)
12477#define DDRC_DRAMTMG7_SHADOW_t_ckpdx_SHIFT (0U)
12478/*! t_ckpdx - This is the time before Power Down Exit that CK is maintained as a valid clock before
12479 * issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR: 0 -
12480 * LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 When using DDR2/3/4 SDRAM, this register should be set to the
12481 * same value as DRAMTMG5.t_cksrx. When the controller is operating in 1:2 frequency ratio mode,
12482 * program this to recommended value divided by two and round it up to next integer. This is only
12483 * present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
12484 */
12485#define DDRC_DRAMTMG7_SHADOW_t_ckpdx(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_SHADOW_t_ckpdx_SHIFT)) & DDRC_DRAMTMG7_SHADOW_t_ckpdx_MASK)
12486#define DDRC_DRAMTMG7_SHADOW_t_ckpde_MASK (0xF00U)
12487#define DDRC_DRAMTMG7_SHADOW_t_ckpde_SHIFT (8U)
12488/*! t_ckpde - This is the time after Power Down Entry that CK is maintained as a valid clock.
12489 * Specifies the clock disable delay after PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2
12490 * - LPDDR4: tCKCKEL When using DDR2/3/4 SDRAM, this register should be set to the same value as
12491 * DRAMTMG5.t_cksre. When the controller is operating in 1:2 frequency ratio mode, program this
12492 * to recommended value divided by two and round it up to next integer. This is only present for
12493 * designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
12494 */
12495#define DDRC_DRAMTMG7_SHADOW_t_ckpde(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG7_SHADOW_t_ckpde_SHIFT)) & DDRC_DRAMTMG7_SHADOW_t_ckpde_MASK)
12496/*! @} */
12497
12498/*! @name DRAMTMG8_SHADOW - [SHADOW] SDRAM Timing Register 8 */
12499/*! @{ */
12500#define DDRC_DRAMTMG8_SHADOW_t_xs_x32_MASK (0x7FU)
12501#define DDRC_DRAMTMG8_SHADOW_t_xs_x32_SHIFT (0U)
12502/*! t_xs_x32 - tXS: Exit Self Refresh to commands not requiring a locked DLL. When the controller is
12503 * operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round
12504 * up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
12505 * DDR4 SDRAMs.
12506 */
12507#define DDRC_DRAMTMG8_SHADOW_t_xs_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_x32_MASK)
12508#define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_MASK (0x7F00U)
12509#define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_SHIFT (8U)
12510/*! t_xs_dll_x32 - tXSDLL: Exit Self Refresh to commands requiring a locked DLL. When the controller
12511 * is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and
12512 * round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
12513 * DDR4 SDRAMs.
12514 */
12515#define DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_dll_x32_MASK)
12516#define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_MASK (0x7F0000U)
12517#define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_SHIFT (16U)
12518/*! t_xs_abort_x32 - tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self
12519 * Refresh Abort. When the controller is operating in 1:2 frequency ratio mode, program this to the
12520 * above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks.
12521 * Note: Ensure this is less than or equal to t_xs_x32.
12522 */
12523#define DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_abort_x32_MASK)
12524#define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_MASK (0x7F000000U)
12525#define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_SHIFT (24U)
12526/*! t_xs_fast_x32 - tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown
12527 * mode). When the controller is operating in 1:2 frequency ratio mode, program this to the
12528 * above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note:
12529 * This is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to
12530 * t_xs_x32.
12531 */
12532#define DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_SHIFT)) & DDRC_DRAMTMG8_SHADOW_t_xs_fast_x32_MASK)
12533/*! @} */
12534
12535/*! @name DRAMTMG9_SHADOW - [SHADOW] SDRAM Timing Register 9 */
12536/*! @{ */
12537#define DDRC_DRAMTMG9_SHADOW_wr2rd_s_MASK (0x3FU)
12538#define DDRC_DRAMTMG9_SHADOW_wr2rd_s_SHIFT (0U)
12539/*! wr2rd_s - CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different
12540 * bank group. Includes time for bus turnaround, recovery times, and all per-bank, per-rank, and
12541 * global constraints. Present only in designs configured to support DDR4. Unit: Clocks. Where:
12542 * - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value
12543 * programmed in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read
12544 * command delay for different bank group. This comes directly from the SDRAM specification. When
12545 * the controller is operating in 1:2 mode, divide the value calculated using the above equation
12546 * by 2, and round it up to next integer.
12547 */
12548#define DDRC_DRAMTMG9_SHADOW_wr2rd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_wr2rd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_wr2rd_s_MASK)
12549#define DDRC_DRAMTMG9_SHADOW_t_rrd_s_MASK (0xF00U)
12550#define DDRC_DRAMTMG9_SHADOW_t_rrd_s_SHIFT (8U)
12551/*! t_rrd_s - tRRD_S: Minimum time between activates from bank "a" to bank "b" for different bank
12552 * group. When the controller is operating in 1:2 frequency ratio mode, program this to (tRRD_S/2)
12553 * and round it up to the next integer value. Present only in designs configured to support DDR4.
12554 * Unit: Clocks.
12555 */
12556#define DDRC_DRAMTMG9_SHADOW_t_rrd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_t_rrd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_t_rrd_s_MASK)
12557#define DDRC_DRAMTMG9_SHADOW_t_ccd_s_MASK (0x70000U)
12558#define DDRC_DRAMTMG9_SHADOW_t_ccd_s_SHIFT (16U)
12559/*! t_ccd_s - tCCD_S: This is the minimum time between two reads or two writes for different bank
12560 * group. For bank switching (from bank "a" to bank "b"), the minimum time is this value + 1. When
12561 * the controller is operating in 1:2 frequency ratio mode, program this to (tCCD_S/2) and round
12562 * it up to the next integer value. Present only in designs configured to support DDR4. Unit:
12563 * clocks.
12564 */
12565#define DDRC_DRAMTMG9_SHADOW_t_ccd_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_t_ccd_s_SHIFT)) & DDRC_DRAMTMG9_SHADOW_t_ccd_s_MASK)
12566#define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_MASK (0x40000000U)
12567#define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_SHIFT (30U)
12568/*! ddr4_wr_preamble - DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2
12569 */
12570#define DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_SHIFT)) & DDRC_DRAMTMG9_SHADOW_ddr4_wr_preamble_MASK)
12571/*! @} */
12572
12573/*! @name DRAMTMG10_SHADOW - [SHADOW] SDRAM Timing Register 10 */
12574/*! @{ */
12575#define DDRC_DRAMTMG10_SHADOW_t_gear_hold_MASK (0x3U)
12576#define DDRC_DRAMTMG10_SHADOW_t_gear_hold_SHIFT (0U)
12577/*! t_gear_hold - Geardown hold time. Minimum value of this register is 1. Zero is invalid. For
12578 * DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in
12579 * 1:2 frequency ratio mode, program this to (tGEAR_hold/2) and round it up to the next integer
12580 * value. Unit: Clocks
12581 */
12582#define DDRC_DRAMTMG10_SHADOW_t_gear_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_gear_hold_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_gear_hold_MASK)
12583#define DDRC_DRAMTMG10_SHADOW_t_gear_setup_MASK (0xCU)
12584#define DDRC_DRAMTMG10_SHADOW_t_gear_setup_SHIFT (2U)
12585/*! t_gear_setup - Geardown setup time. Minimum value of this register is 1. Zero is invalid. For
12586 * DDR4-2666 and DDR4-3200, this parameter is defined as 2 clks When the controller is operating in
12587 * 1:2 frequency ratio mode, program this to (tGEAR_setup/2) and round it up to the next integer
12588 * value. Unit: Clocks
12589 */
12590#define DDRC_DRAMTMG10_SHADOW_t_gear_setup(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_gear_setup_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_gear_setup_MASK)
12591#define DDRC_DRAMTMG10_SHADOW_t_cmd_gear_MASK (0x1F00U)
12592#define DDRC_DRAMTMG10_SHADOW_t_cmd_gear_SHIFT (8U)
12593/*! t_cmd_gear - Sync pulse to first valid command. For DDR4-2666 and DDR4-3200, this parameter is
12594 * defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for
12595 * this register is 24 When the controller is operating in 1:2 mode, program this to (tCMD_GEAR/2)
12596 * and round it up to the next integer value. Unit: Clocks
12597 */
12598#define DDRC_DRAMTMG10_SHADOW_t_cmd_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_cmd_gear_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_cmd_gear_MASK)
12599#define DDRC_DRAMTMG10_SHADOW_t_sync_gear_MASK (0x1F0000U)
12600#define DDRC_DRAMTMG10_SHADOW_t_sync_gear_SHIFT (16U)
12601/*! t_sync_gear - Indicates the time between MRS command and the sync pulse time. This must be even
12602 * number of clocks. For DDR4-2666 and DDR4-3200, this parameter is defined as tMOD(min)+4nCK
12603 * tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24+4 = 28
12604 * When the controller is operating in 1:2 mode, program this to (tSYNC_GEAR/2) and round it up
12605 * to the next integer value. Unit: Clocks
12606 */
12607#define DDRC_DRAMTMG10_SHADOW_t_sync_gear(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG10_SHADOW_t_sync_gear_SHIFT)) & DDRC_DRAMTMG10_SHADOW_t_sync_gear_MASK)
12608/*! @} */
12609
12610/*! @name DRAMTMG11_SHADOW - [SHADOW] SDRAM Timing Register 11 */
12611/*! @{ */
12612#define DDRC_DRAMTMG11_SHADOW_t_ckmpe_MASK (0x1FU)
12613#define DDRC_DRAMTMG11_SHADOW_t_ckmpe_SHIFT (0U)
12614/*! t_ckmpe - tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs
12615 * configured to support DDR4. Unit: Clocks. When the controller is operating in 1:2 frequency ratio
12616 * mode, divide the value calculated using the above equation by 2, and round it up to next
12617 * integer.
12618 */
12619#define DDRC_DRAMTMG11_SHADOW_t_ckmpe(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_ckmpe_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_ckmpe_MASK)
12620#define DDRC_DRAMTMG11_SHADOW_t_mpx_s_MASK (0x300U)
12621#define DDRC_DRAMTMG11_SHADOW_t_mpx_s_SHIFT (8U)
12622/*! t_mpx_s - tMPX_S: Minimum time CS setup time to CKE. When the controller is operating in 1:2
12623 * frequency ratio mode, program this to (tMPX_S/2) and round it up to the next integer value.
12624 * Present only in designs configured to support DDR4. Unit: Clocks.
12625 */
12626#define DDRC_DRAMTMG11_SHADOW_t_mpx_s(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_mpx_s_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_mpx_s_MASK)
12627#define DDRC_DRAMTMG11_SHADOW_t_mpx_lh_MASK (0x1F0000U)
12628#define DDRC_DRAMTMG11_SHADOW_t_mpx_lh_SHIFT (16U)
12629/*! t_mpx_lh - tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the
12630 * controller is operating in 1:2 frequency ratio mode, program this to RoundUp(tMPX_LH/2)+1. Present
12631 * only in designs configured to support DDR4. Unit: clocks.
12632 */
12633#define DDRC_DRAMTMG11_SHADOW_t_mpx_lh(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_t_mpx_lh_SHIFT)) & DDRC_DRAMTMG11_SHADOW_t_mpx_lh_MASK)
12634#define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_MASK (0x7F000000U)
12635#define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_SHIFT (24U)
12636/*! post_mpsm_gap_x32 - tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL.
12637 * When the controller is operating in 1:2 frequency ratio mode, program this to (tXMPDLL/2) and
12638 * round it up to the next integer value. Present only in designs configured to support DDR4.
12639 * Unit: Multiples of 32 clocks.
12640 */
12641#define DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_SHIFT)) & DDRC_DRAMTMG11_SHADOW_post_mpsm_gap_x32_MASK)
12642/*! @} */
12643
12644/*! @name DRAMTMG12_SHADOW - [SHADOW] SDRAM Timing Register 12 */
12645/*! @{ */
12646#define DDRC_DRAMTMG12_SHADOW_t_mrd_pda_MASK (0x1FU)
12647#define DDRC_DRAMTMG12_SHADOW_t_mrd_pda_SHIFT (0U)
12648/*! t_mrd_pda - tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the
12649 * controller is operating in 1:2 frequency ratio mode, program this to (tMRD_PDA/2) and round it up
12650 * to the next integer value.
12651 */
12652#define DDRC_DRAMTMG12_SHADOW_t_mrd_pda(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_mrd_pda_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_mrd_pda_MASK)
12653#define DDRC_DRAMTMG12_SHADOW_t_ckehcmd_MASK (0xF00U)
12654#define DDRC_DRAMTMG12_SHADOW_t_ckehcmd_SHIFT (8U)
12655/*! t_ckehcmd - tCKEHCMD: Valid command requirement after CKE input HIGH. When the controller is
12656 * operating in 1:2 frequency ratio mode, program this to (tCKEHCMD/2) and round it up to the next
12657 * integer value.
12658 */
12659#define DDRC_DRAMTMG12_SHADOW_t_ckehcmd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_ckehcmd_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_ckehcmd_MASK)
12660#define DDRC_DRAMTMG12_SHADOW_t_cmdcke_MASK (0x30000U)
12661#define DDRC_DRAMTMG12_SHADOW_t_cmdcke_SHIFT (16U)
12662/*! t_cmdcke - tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE
12663 * or tCMDCKE When the controller is operating in 1:2 frequency ratio mode, program this to
12664 * (max(tESCKE, tCMDCKE)/2) and round it up to the next integer value.
12665 */
12666#define DDRC_DRAMTMG12_SHADOW_t_cmdcke(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG12_SHADOW_t_cmdcke_SHIFT)) & DDRC_DRAMTMG12_SHADOW_t_cmdcke_MASK)
12667/*! @} */
12668
12669/*! @name DRAMTMG13_SHADOW - [SHADOW] SDRAM Timing Register 13 */
12670/*! @{ */
12671#define DDRC_DRAMTMG13_SHADOW_t_ppd_MASK (0x7U)
12672#define DDRC_DRAMTMG13_SHADOW_t_ppd_SHIFT (0U)
12673/*! t_ppd - LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the
12674 * controller is operating in 1:2 frequency ratio mode, program this to (tPPD/2) and round it up to
12675 * the next integer value. Unit: Clocks.
12676 */
12677#define DDRC_DRAMTMG13_SHADOW_t_ppd(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_t_ppd_SHIFT)) & DDRC_DRAMTMG13_SHADOW_t_ppd_MASK)
12678#define DDRC_DRAMTMG13_SHADOW_t_ccd_mw_MASK (0x3F0000U)
12679#define DDRC_DRAMTMG13_SHADOW_t_ccd_mw_SHIFT (16U)
12680/*! t_ccd_mw - LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write
12681 * command for same bank. When the controller is operating in 1:2 frequency ratio mode, program
12682 * this to (tCCDMW/2) and round it up to the next integer value. Unit: Clocks.
12683 */
12684#define DDRC_DRAMTMG13_SHADOW_t_ccd_mw(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_t_ccd_mw_SHIFT)) & DDRC_DRAMTMG13_SHADOW_t_ccd_mw_MASK)
12685#define DDRC_DRAMTMG13_SHADOW_odtloff_MASK (0x7F000000U)
12686#define DDRC_DRAMTMG13_SHADOW_odtloff_SHIFT (24U)
12687/*! odtloff - LPDDR4: tODTLoff: This is the latency from CAS-2 command to tODToff reference. When
12688 * the controller is operating in 1:2 frequency ratio mode, program this to (tODTLoff/2) and round
12689 * it up to the next integer value. Unit: Clocks.
12690 */
12691#define DDRC_DRAMTMG13_SHADOW_odtloff(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG13_SHADOW_odtloff_SHIFT)) & DDRC_DRAMTMG13_SHADOW_odtloff_MASK)
12692/*! @} */
12693
12694/*! @name DRAMTMG14_SHADOW - [SHADOW] SDRAM Timing Register 14 */
12695/*! @{ */
12696#define DDRC_DRAMTMG14_SHADOW_t_xsr_MASK (0xFFFU)
12697#define DDRC_DRAMTMG14_SHADOW_t_xsr_SHIFT (0U)
12698/*! t_xsr - tXSR: Exit Self Refresh to any command. When the controller is operating in 1:2
12699 * frequency ratio mode, program this to the above value divided by 2 and round up to next integer value.
12700 * Note: Used only for mDDR/LPDDR2/LPDDR3/LPDDR4 mode.
12701 */
12702#define DDRC_DRAMTMG14_SHADOW_t_xsr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG14_SHADOW_t_xsr_SHIFT)) & DDRC_DRAMTMG14_SHADOW_t_xsr_MASK)
12703/*! @} */
12704
12705/*! @name DRAMTMG15_SHADOW - [SHADOW] SDRAM Timing Register 15 */
12706/*! @{ */
12707#define DDRC_DRAMTMG15_SHADOW_t_stab_x32_MASK (0xFFU)
12708#define DDRC_DRAMTMG15_SHADOW_t_stab_x32_SHIFT (0U)
12709/*! t_stab_x32 - tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4
12710 * RDIMM : - when exiting power saving mode, if the clock was stopped, after re-enabling it the
12711 * clock must be stable for a time specified by tSTAB - in the case of input clock frequency
12712 * change (DDR4) - after issuing control words that refers to clock timing (Specification: 6us for
12713 * DDR3, 5us for DDR4) When the controller is operating in 1:2 frequency ratio mode, program this to
12714 * recommended value divided by two and round it up to next integer. Unit: Multiples of 32 clock
12715 * cycles.
12716 */
12717#define DDRC_DRAMTMG15_SHADOW_t_stab_x32(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_SHADOW_t_stab_x32_SHIFT)) & DDRC_DRAMTMG15_SHADOW_t_stab_x32_MASK)
12718#define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_MASK (0x80000000U)
12719#define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_SHIFT (31U)
12720/*! en_dfi_lp_t_stab - - 1 - Enable using tSTAB when exiting DFI LP. Needs to be set when the PHY is
12721 * stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when
12722 * exiting DFI LP
12723 */
12724#define DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_SHIFT)) & DDRC_DRAMTMG15_SHADOW_en_dfi_lp_t_stab_MASK)
12725/*! @} */
12726
12727/*! @name ZQCTL0_SHADOW - [SHADOW] ZQ Control Register 0 */
12728/*! @{ */
12729#define DDRC_ZQCTL0_SHADOW_t_zq_short_nop_MASK (0x3FFU)
12730#define DDRC_ZQCTL0_SHADOW_t_zq_short_nop_SHIFT (0U)
12731/*! t_zq_short_nop - tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of DFI clock cycles
12732 * of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM.
12733 * When the controller is operating in 1:2 frequency ratio mode, program this to tZQCS/2 and
12734 * round it up to the next integer value. This is only present for designs supporting DDR3/DDR4 or
12735 * LPDDR2/LPDDR3/LPDDR4 devices.
12736 */
12737#define DDRC_ZQCTL0_SHADOW_t_zq_short_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_t_zq_short_nop_SHIFT)) & DDRC_ZQCTL0_SHADOW_t_zq_short_nop_MASK)
12738#define DDRC_ZQCTL0_SHADOW_t_zq_long_nop_MASK (0x7FF0000U)
12739#define DDRC_ZQCTL0_SHADOW_t_zq_long_nop_SHIFT (16U)
12740/*! t_zq_long_nop - tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of DFI
12741 * clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is
12742 * issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode: DDR3/DDR4: program
12743 * this to tZQoper/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to
12744 * tZQCL/2 and round it up to the next integer value. LPDDR4: program this to tZQCAL/2 and round it
12745 * up to the next integer value. This is only present for designs supporting DDR3/DDR4 or
12746 * LPDDR2/LPDDR3/LPDDR4 devices.
12747 */
12748#define DDRC_ZQCTL0_SHADOW_t_zq_long_nop(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_t_zq_long_nop_SHIFT)) & DDRC_ZQCTL0_SHADOW_t_zq_long_nop_MASK)
12749#define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_MASK (0x10000000U)
12750#define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_SHIFT (28U)
12751/*! dis_mpsmx_zqcl - - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only
12752 * applicable when run in DDR4 mode. - 0 - Enable issuing of ZQCL command at Maximum Power Saving
12753 * Mode exit. Only applicable when run in DDR4 mode. This is only present for designs supporting
12754 * DDR4 devices. Note: Do not issue ZQCL command at Maximum Power Save Mode exit if the
12755 * DDRC_SHARED_AC configuration parameter is set. Program it to 1'b1. The software can send ZQCS after
12756 * exiting MPSM mode.
12757 */
12758#define DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_mpsmx_zqcl_MASK)
12759#define DDRC_ZQCTL0_SHADOW_zq_resistor_shared_MASK (0x20000000U)
12760#define DDRC_ZQCTL0_SHADOW_zq_resistor_shared_SHIFT (29U)
12761/*! zq_resistor_shared - - 1 - Denotes that ZQ resistor is shared between ranks. Means
12762 * ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with
12763 * tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not overlap. - 0 -
12764 * ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or
12765 * LPDDR2/LPDDR3/LPDDR4 devices.
12766 */
12767#define DDRC_ZQCTL0_SHADOW_zq_resistor_shared(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_zq_resistor_shared_SHIFT)) & DDRC_ZQCTL0_SHADOW_zq_resistor_shared_MASK)
12768#define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_MASK (0x40000000U)
12769#define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_SHIFT (30U)
12770/*! dis_srx_zqcl - - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at
12771 * Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 -
12772 * Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only
12773 * applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for
12774 * designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
12775 */
12776#define DDRC_ZQCTL0_SHADOW_dis_srx_zqcl(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_srx_zqcl_MASK)
12777#define DDRC_ZQCTL0_SHADOW_dis_auto_zq_MASK (0x80000000U)
12778#define DDRC_ZQCTL0_SHADOW_dis_auto_zq_SHIFT (31U)
12779/*! dis_auto_zq - - 1 - Disable DDRC generation of ZQCS/MPC(ZQ calibration) command. Register
12780 * DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module. - 0 -
12781 * Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_short_interval_x1024.
12782 * This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
12783 */
12784#define DDRC_ZQCTL0_SHADOW_dis_auto_zq(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ZQCTL0_SHADOW_dis_auto_zq_SHIFT)) & DDRC_ZQCTL0_SHADOW_dis_auto_zq_MASK)
12785/*! @} */
12786
12787/*! @name DFITMG0_SHADOW - [SHADOW] DFI Timing Register 0 */
12788/*! @{ */
12789#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_MASK (0x3FU)
12790#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_SHIFT (0U)
12791/*! dfi_tphy_wrlat - Write latency Number of clocks from the write command to write data enable
12792 * (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY
12793 * specification for correct value.Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be
12794 * necessary to use the adjusted value of CL in the calculation of tphy_wrlat. This is to compensate for
12795 * the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or DFI PHY
12796 * clock cycles, depending on DFITMG0.dfi_wrdata_use_sdr.
12797 */
12798#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_tphy_wrlat_MASK)
12799#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_MASK (0x3F00U)
12800#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_SHIFT (8U)
12801/*! dfi_tphy_wrdata - Specifies the number of clock cycles between when dfi_wrdata_en is asserted to
12802 * when the associated write data is driven on the dfi_wrdata signal. This corresponds to the
12803 * DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max
12804 * supported value is 8. Unit: DFI clock cycles or DFI PHY clock cycles, depending on
12805 * DFITMG0.dfi_wrdata_use_sdr.
12806 */
12807#define DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_tphy_wrdata_MASK)
12808#define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_MASK (0x8000U)
12809#define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_SHIFT (15U)
12810/*! dfi_wrdata_use_sdr - Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using
12811 * HDR (DFI clock) or SDR (DFI PHY clock) values Selects whether value in DFITMG0.dfi_tphy_wrlat
12812 * is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles Selects whether value in
12813 * DFITMG0.dfi_tphy_wrdata is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles - 0 in terms of
12814 * HDR (DFI clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification
12815 * for correct value.
12816 */
12817#define DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_wrdata_use_sdr_MASK)
12818#define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_MASK (0x7F0000U)
12819#define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_SHIFT (16U)
12820/*! dfi_t_rddata_en - Time from the assertion of a read command on the DFI interface to the
12821 * assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds
12822 * to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM/LRDIMM, it
12823 * may be necessary to use the adjusted value of CL in the calculation of trddata_en. This is to
12824 * compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM. Unit: DFI clock cycles or
12825 * DFI PHY clock cycles, depending on DFITMG0.dfi_rddata_use_sdr.
12826 */
12827#define DDRC_DFITMG0_SHADOW_dfi_t_rddata_en(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_t_rddata_en_MASK)
12828#define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_MASK (0x800000U)
12829#define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_SHIFT (23U)
12830/*! dfi_rddata_use_sdr - Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated
12831 * using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in
12832 * DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles: - 0 in terms of HDR (DFI
12833 * clock) cycles - 1 in terms of SDR (DFI PHY clock) cycles Refer to PHY specification for correct
12834 * value.
12835 */
12836#define DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_rddata_use_sdr_MASK)
12837#define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_MASK (0x1F000000U)
12838#define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_SHIFT (24U)
12839/*! dfi_t_ctrl_delay - Specifies the number of DFI clock cycles after an assertion or de-assertion
12840 * of the DFI control signals that the control signals at the PHY-DRAM interface reflect the
12841 * assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing
12842 * parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it
12843 * is necessary to increment this parameter by RDIMM's/LRDIMM's extra cycle of latency in terms
12844 * of DFI clock.
12845 */
12846#define DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_SHIFT)) & DDRC_DFITMG0_SHADOW_dfi_t_ctrl_delay_MASK)
12847/*! @} */
12848
12849/*! @name DFITMG1_SHADOW - [SHADOW] DFI Timing Register 1 */
12850/*! @{ */
12851#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_MASK (0x1FU)
12852#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_SHIFT (0U)
12853/*! dfi_t_dram_clk_enable - Specifies the number of DFI clock cycles from the de-assertion of the
12854 * dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the
12855 * DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are not
12856 * phase aligned, this timing parameter should be rounded up to the next integer value.
12857 */
12858#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_enable_MASK)
12859#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_MASK (0x1F00U)
12860#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_SHIFT (8U)
12861/*! dfi_t_dram_clk_disable - Specifies the number of DFI clock cycles from the assertion of the
12862 * dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices, at the PHY-DRAM
12863 * boundary, maintains a low value. If the DFI clock and the memory clock are not phase aligned,
12864 * this timing parameter should be rounded up to the next integer value.
12865 */
12866#define DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_dram_clk_disable_MASK)
12867#define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_MASK (0x1F0000U)
12868#define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_SHIFT (16U)
12869/*! dfi_t_wrdata_delay - Specifies the number of DFI clock cycles between when the dfi_wrdata_en
12870 * signal is asserted and when the corresponding write data transfer is completed on the DRAM bus.
12871 * This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification for
12872 * correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI
12873 * 3.0. For DFI 2.1 PHY, set to tphy_wrdata + (delay of DFI write data to the DRAM). Value to be
12874 * programmed is in terms of DFI clocks, not PHY clocks. In FREQ_RATIO=2, divide PHY's value by 2
12875 * and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Unit:
12876 * Clocks
12877 */
12878#define DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_wrdata_delay_MASK)
12879#define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_MASK (0x3000000U)
12880#define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_SHIFT (24U)
12881/*! dfi_t_parin_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is
12882 * asserted and when the associated dfi_parity_in signal is driven.
12883 */
12884#define DDRC_DFITMG1_SHADOW_dfi_t_parin_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_parin_lat_MASK)
12885#define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_MASK (0xF0000000U)
12886#define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_SHIFT (28U)
12887/*! dfi_t_cmd_lat - Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is
12888 * asserted and when the associated command is driven. This field is used for CAL mode, should be
12889 * set to '0' or the value which matches the CAL mode register setting in the DRAM. If the PHY
12890 * can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
12891 */
12892#define DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_SHIFT)) & DDRC_DFITMG1_SHADOW_dfi_t_cmd_lat_MASK)
12893/*! @} */
12894
12895/*! @name DFITMG2_SHADOW - [SHADOW] DFI Timing Register 2 */
12896/*! @{ */
12897#define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_MASK (0x3FU)
12898#define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_SHIFT (0U)
12899/*! dfi_tphy_wrcslat - Number of DFI PHY clock cycles between when a write command is sent on the
12900 * DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds
12901 * to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.
12902 */
12903#define DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_SHIFT)) & DDRC_DFITMG2_SHADOW_dfi_tphy_wrcslat_MASK)
12904#define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_MASK (0x7F00U)
12905#define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_SHIFT (8U)
12906/*! dfi_tphy_rdcslat - Number of DFI PHY clock cycles between when a read command is sent on the DFI
12907 * control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds
12908 * to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.
12909 */
12910#define DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_SHIFT)) & DDRC_DFITMG2_SHADOW_dfi_tphy_rdcslat_MASK)
12911/*! @} */
12912
12913/*! @name DFITMG3_SHADOW - [SHADOW] DFI Timing Register 3 */
12914/*! @{ */
12915#define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_MASK (0x1FU)
12916#define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_SHIFT (0U)
12917/*! dfi_t_geardown_delay - The delay from dfi_geardown_en assertion to the time of the PHY being
12918 * ready to receive commands. Refer to PHY specification for correct value. When the controller is
12919 * operating in 1:2 frequency ratio mode, program this to (tgeardown_delay/2) and round it up to
12920 * the next integer value. Unit: Clocks
12921 */
12922#define DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_SHIFT)) & DDRC_DFITMG3_SHADOW_dfi_t_geardown_delay_MASK)
12923/*! @} */
12924
12925/*! @name ODTCFG_SHADOW - [SHADOW] ODT Configuration Register */
12926/*! @{ */
12927#define DDRC_ODTCFG_SHADOW_rd_odt_delay_MASK (0x7CU)
12928#define DDRC_ODTCFG_SHADOW_rd_odt_delay_SHIFT (2U)
12929/*! rd_odt_delay - The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT
12930 * values associated with that command. ODT setting must remain constant for the entire time that
12931 * DQS is driven by the DDRC. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066), CL + AL - 5
12932 * (DDR2-1066) If (CL + AL - 4 < 0), DDRC does not support ODT for read operation. DDR3: - CL -
12933 * CWL DDR4: - CL - CWL - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL
12934 * mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) RD_PREAMBLE = 1 (1tCK write
12935 * preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0, DDRC does
12936 * not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)
12937 */
12938#define DDRC_ODTCFG_SHADOW_rd_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_rd_odt_delay_SHIFT)) & DDRC_ODTCFG_SHADOW_rd_odt_delay_MASK)
12939#define DDRC_ODTCFG_SHADOW_rd_odt_hold_MASK (0xF00U)
12940#define DDRC_ODTCFG_SHADOW_rd_odt_hold_SHIFT (8U)
12941/*! rd_odt_hold - DFI PHY clock cycles to hold ODT for a read command. The minimum supported value
12942 * is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066) - BL4: 0x4 (not
12943 * DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (1tCK
12944 * write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) -
12945 * RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK)
12946 */
12947#define DDRC_ODTCFG_SHADOW_rd_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_rd_odt_hold_SHIFT)) & DDRC_ODTCFG_SHADOW_rd_odt_hold_MASK)
12948#define DDRC_ODTCFG_SHADOW_wr_odt_delay_MASK (0x1F0000U)
12949#define DDRC_ODTCFG_SHADOW_wr_odt_delay_SHIFT (16U)
12950/*! wr_odt_delay - The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT
12951 * values associated with that command. ODT setting must remain constant for the entire time that
12952 * DQS is driven by the DDRC. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/667), CWL +
12953 * AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), DDRC does not support ODT
12954 * for write operation. DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3:
12955 * - WL - 1 - RU(tODTon(max)/tCK))
12956 */
12957#define DDRC_ODTCFG_SHADOW_wr_odt_delay(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_wr_odt_delay_SHIFT)) & DDRC_ODTCFG_SHADOW_wr_odt_delay_MASK)
12958#define DDRC_ODTCFG_SHADOW_wr_odt_hold_MASK (0xF000000U)
12959#define DDRC_ODTCFG_SHADOW_wr_odt_hold_SHIFT (24U)
12960/*! wr_odt_hold - DFI PHY clock cycles to hold ODT for a write command. The minimum supported value
12961 * is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066)
12962 * - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - BL8:
12963 * 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble)
12964 * CRC_MODE = 0 (not CRC mode), 1 (CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
12965 */
12966#define DDRC_ODTCFG_SHADOW_wr_odt_hold(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ODTCFG_SHADOW_wr_odt_hold_SHIFT)) & DDRC_ODTCFG_SHADOW_wr_odt_hold_MASK)
12967/*! @} */
12968
12969
12970/*!
12971 * @}
12972 */ /* end of group DDRC_Register_Masks */
12973
12974
12975/* DDRC - Peripheral instance base addresses */
12976/** Peripheral DRC__DDRC base address */
12977#define DRC__DDRC_BASE (0x5C000000u)
12978/** Peripheral DRC__DDRC base pointer */
12979#define DRC__DDRC ((DDRC_Type *)DRC__DDRC_BASE)
12980/** Array initializer of DDRC peripheral base addresses */
12981#define DDRC_BASE_ADDRS { DRC__DDRC_BASE }
12982/** Array initializer of DDRC peripheral base pointers */
12983#define DDRC_BASE_PTRS { DRC__DDRC }
12984
12985/*!
12986 * @}
12987 */ /* end of group DDRC_Peripheral_Access_Layer */
12988
12989
12990/* ----------------------------------------------------------------------------
12991 -- DDRPHY Peripheral Access Layer
12992 ---------------------------------------------------------------------------- */
12993
12994/*!
12995 * @addtogroup DDRPHY_Peripheral_Access_Layer DDRPHY Peripheral Access Layer
12996 * @{
12997 */
12998
12999/** DDRPHY - Register Layout Typedef */
13000typedef struct {
13001 __I uint32_t RIDR; /**< Revision Identification Register, offset: 0x0 */
13002 __IO uint32_t PIR; /**< PHY Initialization Register, offset: 0x4 */
13003 uint8_t RESERVED_0[8];
13004 __IO uint32_t PGCR0; /**< PHY General Configuration Register 0, offset: 0x10 */
13005 __IO uint32_t PGCR1; /**< PHY General Configuration Register 1, offset: 0x14 */
13006 __IO uint32_t PGCR2; /**< PHY General Configuration Register 2, offset: 0x18 */
13007 __IO uint32_t PGCR3; /**< PHY General Configuration Register 3, offset: 0x1C */
13008 __IO uint32_t PGCR4; /**< PHY General Configuration Register 4, offset: 0x20 */
13009 __IO uint32_t PGCR5; /**< PHY General Configuration Register 5, offset: 0x24 */
13010 __IO uint32_t PGCR6; /**< PHY General Configuration Register 6, offset: 0x28 */
13011 __IO uint32_t PGCR7; /**< PHY General Configuration Register 7, offset: 0x2C */
13012 __I uint32_t PGSR0; /**< PHY General Status Register 0, offset: 0x30 */
13013 __I uint32_t PGSR1; /**< PHY General Status Register 1, offset: 0x34 */
13014 __I uint32_t PGSR2; /**< PHY General Status Register 2, offset: 0x38 */
13015 uint8_t RESERVED_1[4];
13016 __IO uint32_t PTR0; /**< PHY Timing Register 0, offset: 0x40 */
13017 __IO uint32_t PTR1; /**< PHY Timing Register 1, offset: 0x44 */
13018 __IO uint32_t PTR2; /**< PHY Timing Register 2, offset: 0x48 */
13019 __IO uint32_t PTR3; /**< PHY Timing Register 3, offset: 0x4C */
13020 __IO uint32_t PTR4; /**< PHY Timing Register 4, offset: 0x50 */
13021 __IO uint32_t PTR5; /**< PHY Timing Register 5, offset: 0x54 */
13022 __IO uint32_t PTR6; /**< PHY Timing Register 6, offset: 0x58 */
13023 uint8_t RESERVED_2[12];
13024 __IO uint32_t PLLCR0; /**< PLL Control Register 0 (Type B PLL Only), offset: 0x68 */
13025 __IO uint32_t PLLCR1; /**< PLL Control Register 1 (Type B PLL Only), offset: 0x6C */
13026 __IO uint32_t PLLCR2; /**< PLL Control Register 2 (Type B PLL Only), offset: 0x70 */
13027 __IO uint32_t PLLCR3; /**< PLL Control Register 3 (Type B PLL Only), offset: 0x74 */
13028 __IO uint32_t PLLCR4; /**< PLL Control Register 4 (Type B PLL Only), offset: 0x78 */
13029 __IO uint32_t PLLCR5; /**< PLL Control Register 5 (Type B PLL Only), offset: 0x7C */
13030 uint8_t RESERVED_3[8];
13031 __IO uint32_t DXCCR; /**< DATX8 Common Configuration Register, offset: 0x88 */
13032 uint8_t RESERVED_4[4];
13033 __IO uint32_t DSGCR; /**< DDR System General Configuration Register, offset: 0x90 */
13034 uint8_t RESERVED_5[4];
13035 __IO uint32_t ODTCR; /**< ODT Configuration Register, offset: 0x98 */
13036 uint8_t RESERVED_6[4];
13037 __IO uint32_t AACR; /**< Anti-Aging Control Register, offset: 0xA0 */
13038 uint8_t RESERVED_7[28];
13039 __IO uint32_t GPR0; /**< General Purpose Register 0, offset: 0xC0 */
13040 __IO uint32_t GPR1; /**< General Purpose Register 1, offset: 0xC4 */
13041 uint8_t RESERVED_8[56];
13042 __IO uint32_t DCR; /**< DRAM Configuration Register, offset: 0x100 */
13043 uint8_t RESERVED_9[12];
13044 __IO uint32_t DTPR0; /**< DRAM Timing Parameters Register 0, offset: 0x110 */
13045 __IO uint32_t DTPR1; /**< DRAM Timing Parameters Register 1, offset: 0x114 */
13046 __IO uint32_t DTPR2; /**< DRAM Timing Parameters Register 2, offset: 0x118 */
13047 __IO uint32_t DTPR3; /**< DRAM Timing Parameters Register 3, offset: 0x11C */
13048 __IO uint32_t DTPR4; /**< DRAM Timing Parameters Register 4, offset: 0x120 */
13049 __IO uint32_t DTPR5; /**< DRAM Timing Parameters Register 5, offset: 0x124 */
13050 __IO uint32_t DTPR6; /**< DRAM Timing Parameters Register 6, offset: 0x128 */
13051 uint8_t RESERVED_10[20];
13052 __IO uint32_t RDIMMGCR0; /**< RDIMM General Configuration Register 0, offset: 0x140 */
13053 __IO uint32_t RDIMMGCR1; /**< RDIMM General Configuration Register 1, offset: 0x144 */
13054 __IO uint32_t RDIMMGCR2; /**< RDIMM General Configuration Register 2, offset: 0x148 */
13055 uint8_t RESERVED_11[4];
13056 __IO uint32_t RDIMMCR0; /**< RDIMM Control Register 0, offset: 0x150 */
13057 __IO uint32_t RDIMMCR1; /**< RDIMM Control Register 1, offset: 0x154 */
13058 __IO uint32_t RDIMMCR2; /**< RDIMM Control Register 2, offset: 0x158 */
13059 __IO uint32_t RDIMMCR3; /**< RDIMM Control Register 3, offset: 0x15C */
13060 __IO uint32_t RDIMMCR4; /**< RDIMM Control Register 4, offset: 0x160 */
13061 uint8_t RESERVED_12[4];
13062 __IO uint32_t SCHCR0; /**< Scheduler Command Register 0, offset: 0x168 */
13063 __IO uint32_t SCHCR1; /**< Scheduler Command Register 1, offset: 0x16C */
13064 uint8_t RESERVED_13[16];
13065 __IO uint32_t MR0; /**< LPDDR4 Mode Register 0, offset: 0x180 */
13066 __IO uint32_t MR1; /**< LPDDR4 Mode Register 1, offset: 0x184 */
13067 __IO uint32_t MR2; /**< LPDDR4 Mode Register 2, offset: 0x188 */
13068 __IO uint32_t MR3; /**< LPDDR4 Mode Register 3, offset: 0x18C */
13069 __IO uint32_t MR4; /**< LPDDR4 Mode Register 4, offset: 0x190 */
13070 __IO uint32_t MR5; /**< LPDDR4 Mode Register 5, offset: 0x194 */
13071 __IO uint32_t MR6; /**< LPDDR4 Mode Register 6, offset: 0x198 */
13072 __IO uint32_t MR7; /**< LPDDR4 Mode Register 7, offset: 0x19C */
13073 uint8_t RESERVED_14[12];
13074 __IO uint32_t MR11; /**< LPDDR4 Mode Register 11, offset: 0x1AC */
13075 __IO uint32_t MR12; /**< LPDDR4 Mode Register 12, offset: 0x1B0 */
13076 __IO uint32_t MR13; /**< LPDDR4 Mode Register 13, offset: 0x1B4 */
13077 __IO uint32_t MR14; /**< LPDDR4 Mode Register 14, offset: 0x1B8 */
13078 uint8_t RESERVED_15[28];
13079 __IO uint32_t MR22; /**< LPDDR4 Mode Register 22, offset: 0x1D8 */
13080 uint8_t RESERVED_16[36];
13081 __IO uint32_t DTCR0; /**< Data Training Configuration Register 0, offset: 0x200 */
13082 __IO uint32_t DTCR1; /**< Data Training Configuration Register 1, offset: 0x204 */
13083 __IO uint32_t DTAR0; /**< Data Training Address Register 0, offset: 0x208 */
13084 __IO uint32_t DTAR1; /**< Data Training Address Register 1, offset: 0x20C */
13085 __IO uint32_t DTAR2; /**< Data Training Address Register 2, offset: 0x210 */
13086 uint8_t RESERVED_17[4];
13087 __IO uint32_t DTDR0; /**< Data Training Data Register 0, offset: 0x218 */
13088 __IO uint32_t DTDR1; /**< Data Training Data Register 1, offset: 0x21C */
13089 uint8_t RESERVED_18[16];
13090 __I uint32_t DTEDR0; /**< Data Training Eye Data Register 0, offset: 0x230 */
13091 __I uint32_t DTEDR1; /**< Data Training Eye Data Register 1, offset: 0x234 */
13092 __I uint32_t DTEDR2; /**< Data Training Eye Data Register 2, offset: 0x238 */
13093 __I uint32_t VTDR; /**< VREF Training Data Register, offset: 0x23C */
13094 __IO uint32_t CATR0; /**< CA Training Register 0, offset: 0x240 */
13095 __IO uint32_t CATR1; /**< CA Training Register 1, offset: 0x244 */
13096 __IO uint32_t PGCR8; /**< PHY General Configuration Register 8, offset: 0x248 */
13097 uint8_t RESERVED_19[4];
13098 __IO uint32_t DQSDR0; /**< DQS Drift Register 0, offset: 0x250 */
13099 __IO uint32_t DQSDR1; /**< DQS Drift Register 1, offset: 0x254 */
13100 __IO uint32_t DQSDR2; /**< DQS Drift Register 2, offset: 0x258 */
13101 uint8_t RESERVED_20[164];
13102 __IO uint32_t DCUAR; /**< DCU Address Register, offset: 0x300 */
13103 __IO uint32_t DCUDR; /**< DCU Data Register, offset: 0x304 */
13104 __IO uint32_t DCURR; /**< DCU Run Register, offset: 0x308 */
13105 __IO uint32_t DCULR; /**< DCU Loop Register, offset: 0x30C */
13106 __IO uint32_t DCUGCR; /**< DCU General Configuration Register, offset: 0x310 */
13107 __IO uint32_t DCUTPR; /**< DCU Timing Parameters Register, offset: 0x314 */
13108 __I uint32_t DCUSR0; /**< DCU Status Register 0, offset: 0x318 */
13109 __I uint32_t DCUSR1; /**< DCU Status Register 1, offset: 0x31C */
13110 uint8_t RESERVED_21[224];
13111 __IO uint32_t BISTRR; /**< BIST Run Register, offset: 0x400 */
13112 __IO uint32_t BISTWCR; /**< BIST Word Count Register, offset: 0x404 */
13113 __IO uint32_t BISTMSKR0; /**< BIST Mask Register 0, offset: 0x408 */
13114 __IO uint32_t BISTMSKR1; /**< BIST Mask Register 1, offset: 0x40C */
13115 __IO uint32_t BISTMSKR2; /**< BIST Mask Register 2, offset: 0x410 */
13116 __IO uint32_t BISTLSR; /**< BIST LFSR Seed Register, offset: 0x414 */
13117 __IO uint32_t BISTAR0; /**< BIST Address Register 0, offset: 0x418 */
13118 __IO uint32_t BISTAR1; /**< BIST Address Register 1, offset: 0x41C */
13119 __IO uint32_t BISTAR2; /**< BIST Address Register 2, offset: 0x420 */
13120 __IO uint32_t BISTAR3; /**< BIST Address Register 3, offset: 0x424 */
13121 __IO uint32_t BISTAR4; /**< BIST Address Register 4, offset: 0x428 */
13122 __IO uint32_t BISTUDPR; /**< BIST User Data Pattern Register, offset: 0x42C */
13123 __I uint32_t BISTGSR; /**< BIST General Status Register, offset: 0x430 */
13124 __I uint32_t BISTWER0; /**< BIST Word Error Register 0, offset: 0x434 */
13125 __I uint32_t BISTWER1; /**< BIST Word Error Register 1, offset: 0x438 */
13126 __I uint32_t BISTBER0; /**< BIST Bit Error Register 0, offset: 0x43C */
13127 __I uint32_t BISTBER1; /**< BIST Bit Error Register 1, offset: 0x440 */
13128 __I uint32_t BISTBER2; /**< BIST Bit Error Register 2, offset: 0x444 */
13129 __I uint32_t BISTBER3; /**< BIST Bit Error Register 3, offset: 0x448 */
13130 __I uint32_t BISTBER4; /**< BIST Bit Error Register 4, offset: 0x44C */
13131 __I uint32_t BISTWCSR; /**< BIST Word Count Status Register, offset: 0x450 */
13132 __I uint32_t BISTFWR0; /**< BIST Fail Word Register 0, offset: 0x454 */
13133 __I uint32_t BISTFWR1; /**< BIST Fail Word Register 1, offset: 0x458 */
13134 __I uint32_t BISTFWR2; /**< BIST Fail Word Register 2, offset: 0x45C */
13135 __I uint32_t BISTBER5; /**< BIST Bit Error Register 5, offset: 0x460 */
13136 uint8_t RESERVED_22[120];
13137 __IO uint32_t RANKIDR; /**< Rank ID Register, offset: 0x4DC */
13138 __I uint32_t RIOCR0; /**< Rank I/O Configuration Register 0, offset: 0x4E0 */
13139 __I uint32_t RIOCR1; /**< Rank I/O Configuration Register 1, offset: 0x4E4 */
13140 __IO uint32_t RIOCR2; /**< Rank I/O Configuration Register 2, offset: 0x4E8 */
13141 __I uint32_t RIOCR3; /**< Rank I/O Configuration Register 3, offset: 0x4EC */
13142 __IO uint32_t RIOCR4; /**< Rank I/O Configuration Register 4, offset: 0x4F0 */
13143 __IO uint32_t RIOCR5; /**< Rank I/O Configuration Register 5, offset: 0x4F4 */
13144 uint8_t RESERVED_23[8];
13145 __IO uint32_t ACIOCR0; /**< AC I/O Configuration Register 0, offset: 0x500 */
13146 __IO uint32_t ACIOCR1; /**< AC I/O Configuration Register 1, offset: 0x504 */
13147 __IO uint32_t ACIOCR2; /**< AC I/O Configuration Register 2, offset: 0x508 */
13148 __IO uint32_t ACIOCR3; /**< AC I/O Configuration Register 3, offset: 0x50C */
13149 __IO uint32_t ACIOCR4; /**< AC I/O Configuration Register 4, offset: 0x510 */
13150 __IO uint32_t ACIOCR5; /**< AC I/O Configuration Register 5, offset: 0x514 */
13151 uint8_t RESERVED_24[8];
13152 __IO uint32_t IOVCR0; /**< IO VREF Control Register 0, offset: 0x520 */
13153 __I uint32_t IOVCR1; /**< IO VREF Control Register 1, offset: 0x524 */
13154 __IO uint32_t VTCR0; /**< VREF Training Control Register 0, offset: 0x528 */
13155 __IO uint32_t VTCR1; /**< VREF Training Control Register 1, offset: 0x52C */
13156 uint8_t RESERVED_25[16];
13157 __IO uint32_t ACBDLR0; /**< AC Bit Delay Line Register 0, offset: 0x540 */
13158 __IO uint32_t ACBDLR1; /**< AC Bit Delay Line Register 1, offset: 0x544 */
13159 __IO uint32_t ACBDLR2; /**< AC Bit Delay Line Register 2, offset: 0x548 */
13160 __IO uint32_t ACBDLR3; /**< AC Bit Delay Line Register 3, offset: 0x54C */
13161 __IO uint32_t ACBDLR4; /**< AC Bit Delay Line Register 4, offset: 0x550 */
13162 __IO uint32_t ACBDLR5; /**< AC Bit Delay Line Register 5, offset: 0x554 */
13163 __IO uint32_t ACBDLR6; /**< AC Bit Delay Line Register 6, offset: 0x558 */
13164 __IO uint32_t ACBDLR7; /**< AC Bit Delay Line Register 7, offset: 0x55C */
13165 __IO uint32_t ACBDLR8; /**< AC Bit Delay Line Register 8, offset: 0x560 */
13166 __IO uint32_t ACBDLR9; /**< AC Bit Delay Line Register 9, offset: 0x564 */
13167 __IO uint32_t ACBDLR10; /**< AC Bit Delay Line Register 10, offset: 0x568 */
13168 __I uint32_t ACBDLR11; /**< AC Bit Delay Line Register 11, offset: 0x56C */
13169 __I uint32_t ACBDLR12; /**< AC Bit Delay Line Register 12, offset: 0x570 */
13170 __I uint32_t ACBDLR13; /**< AC Bit Delay Line Register 13, offset: 0x574 */
13171 __I uint32_t ACBDLR14; /**< AC Bit Delay Line Register 14, offset: 0x578 */
13172 __IO uint32_t ACBDLR15; /**< AC Bit Delay Line Register 15, offset: 0x57C */
13173 __IO uint32_t ACBDLR16; /**< AC Bit Delay Line Register 16, offset: 0x580 */
13174 __IO uint32_t ACLCDLR; /**< AC Local Calibrated Delay Line Register, offset: 0x584 */
13175 uint8_t RESERVED_26[24];
13176 __IO uint32_t ACMDLR0; /**< AC Master Delay Line Register 0, offset: 0x5A0 */
13177 __IO uint32_t ACMDLR1; /**< AC Master Delay Line Register 1, offset: 0x5A4 */
13178 uint8_t RESERVED_27[216];
13179 __IO uint32_t ZQCR; /**< ZQ Impedance Control Register, offset: 0x680 */
13180 __IO uint32_t ZQ0PR0; /**< ZQ n Impedance Control Program Register 0, offset: 0x684 */
13181 __IO uint32_t ZQ0PR1; /**< ZQ n Impedance Control Program Register 1, offset: 0x688 */
13182 __I uint32_t ZQ0DR0; /**< ZQ n Impedance Control Data Register 0, offset: 0x68C */
13183 __I uint32_t ZQ0DR1; /**< ZQ n Impedance Control Data Register 1, offset: 0x690 */
13184 __IO uint32_t ZQ0OR0; /**< ZQ n Impedance Control Override Data Register 0, offset: 0x694 */
13185 __IO uint32_t ZQ0OR1; /**< ZQ n Impedance Control Override Data Register 1, offset: 0x698 */
13186 __I uint32_t ZQ0SR; /**< ZQ n Impedance Control Status Register, offset: 0x69C */
13187 uint8_t RESERVED_28[4];
13188 __IO uint32_t ZQ1PR0; /**< ZQ n Impedance Control Program Register 0, offset: 0x6A4 */
13189 __IO uint32_t ZQ1PR1; /**< ZQ n Impedance Control Program Register 1, offset: 0x6A8 */
13190 __I uint32_t ZQ1DR0; /**< ZQ n Impedance Control Data Register 0, offset: 0x6AC */
13191 __I uint32_t ZQ1DR1; /**< ZQ n Impedance Control Data Register 1, offset: 0x6B0 */
13192 __IO uint32_t ZQ1OR0; /**< ZQ n Impedance Control Override Data Register 0, offset: 0x6B4 */
13193 __IO uint32_t ZQ1OR1; /**< ZQ n Impedance Control Override Data Register 1, offset: 0x6B8 */
13194 __I uint32_t ZQ1SR; /**< ZQ n Impedance Control Status Register, offset: 0x6BC */
13195 uint8_t RESERVED_29[4];
13196 __IO uint32_t ZQ2PR0; /**< ZQ n Impedance Control Program Register 0, offset: 0x6C4 */
13197 __IO uint32_t ZQ2PR1; /**< ZQ n Impedance Control Program Register 1, offset: 0x6C8 */
13198 __I uint32_t ZQ2DR0; /**< ZQ n Impedance Control Data Register 0, offset: 0x6CC */
13199 __I uint32_t ZQ2DR1; /**< ZQ n Impedance Control Data Register 1, offset: 0x6D0 */
13200 __IO uint32_t ZQ2OR0; /**< ZQ n Impedance Control Override Data Register 0, offset: 0x6D4 */
13201 __IO uint32_t ZQ2OR1; /**< ZQ n Impedance Control Override Data Register 1, offset: 0x6D8 */
13202 __I uint32_t ZQ2SR; /**< ZQ n Impedance Control Status Register, offset: 0x6DC */
13203 uint8_t RESERVED_30[4];
13204 __I uint32_t ZQ3PR0; /**< ZQ n Impedance Control Program Register 0, offset: 0x6E4 */
13205 __I uint32_t ZQ3PR1; /**< ZQ n Impedance Control Program Register 1, offset: 0x6E8 */
13206 __I uint32_t ZQ3DR0; /**< ZQ n Impedance Control Data Register 0, offset: 0x6EC */
13207 __I uint32_t ZQ3DR1; /**< ZQ n Impedance Control Data Register 1, offset: 0x6F0 */
13208 __I uint32_t ZQ3OR0; /**< ZQ n Impedance Control Override Data Register 0, offset: 0x6F4 */
13209 __I uint32_t ZQ3OR1; /**< ZQ n Impedance Control Override Data Register 1, offset: 0x6F8 */
13210 __I uint32_t ZQ3SR; /**< ZQ n Impedance Control Status Register, offset: 0x6FC */
13211 __IO uint32_t DX0GCR0; /**< DATX8 n General Configuration Register 0, offset: 0x700 */
13212 __IO uint32_t DX0GCR1; /**< DATX8 n General Configuration Register 1, offset: 0x704 */
13213 __IO uint32_t DX0GCR2; /**< DATX8 n General Configuration Register 2, offset: 0x708 */
13214 __IO uint32_t DX0GCR3; /**< DATX8 n General Configuration Register 3, offset: 0x70C */
13215 __IO uint32_t DX0GCR4; /**< DATX8 n General Configuration Register 4, offset: 0x710 */
13216 __IO uint32_t DX0GCR5; /**< DATX8 n General Configuration Register 5, offset: 0x714 */
13217 __IO uint32_t DX0GCR6; /**< DATX8 n General Configuration Register 6, offset: 0x718 */
13218 __IO uint32_t DX0GCR7; /**< DATX8 n General Configuration Register 7, offset: 0x71C */
13219 __I uint32_t DX0GCR8; /**< DATX8 n General Configuration Register 8, offset: 0x720 */
13220 __I uint32_t DX0GCR9; /**< DATX8 n General Configuration Register 9, offset: 0x724 */
13221 __IO uint32_t DX0DQMAP0; /**< DATX8 n DQ/DM Mapping Register 0, offset: 0x728 */
13222 __IO uint32_t DX0DQMAP1; /**< DATX8 n DQ/DM Mapping Register 1, offset: 0x72C */
13223 uint8_t RESERVED_31[16];
13224 __IO uint32_t DX0BDLR0; /**< DATX8 n Bit Delay Line Register 0, offset: 0x740 */
13225 __IO uint32_t DX0BDLR1; /**< DATX8 n Bit Delay Line Register 1, offset: 0x744 */
13226 __IO uint32_t DX0BDLR2; /**< DATX8 n Bit Delay Line Register 2, offset: 0x748 */
13227 uint8_t RESERVED_32[4];
13228 __IO uint32_t DX0BDLR3; /**< DATX8 n Bit Delay Line Register 3, offset: 0x750 */
13229 __IO uint32_t DX0BDLR4; /**< DATX8 n Bit Delay Line Register 4, offset: 0x754 */
13230 __IO uint32_t DX0BDLR5; /**< DATX8 n Bit Delay Line Register 5, offset: 0x758 */
13231 uint8_t RESERVED_33[4];
13232 __IO uint32_t DX0BDLR6; /**< DATX8 n Bit Delay Line Register 6, offset: 0x760 */
13233 __I uint32_t DX0BDLR7; /**< DATX8 n Bit Delay Line Register 7, offset: 0x764 */
13234 __I uint32_t DX0BDLR8; /**< DATX8 n Bit Delay Line Register 8, offset: 0x768 */
13235 __I uint32_t DX0BDLR9; /**< DATX8 n Bit Delay Line Register 9, offset: 0x76C */
13236 uint8_t RESERVED_34[16];
13237 __IO uint32_t DX0LCDLR0; /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0x780 */
13238 __IO uint32_t DX0LCDLR1; /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0x784 */
13239 __IO uint32_t DX0LCDLR2; /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0x788 */
13240 __IO uint32_t DX0LCDLR3; /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0x78C */
13241 __IO uint32_t DX0LCDLR4; /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0x790 */
13242 __IO uint32_t DX0LCDLR5; /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0x794 */
13243 uint8_t RESERVED_35[8];
13244 __IO uint32_t DX0MDLR0; /**< DATX8 n Master Delay Line Register 0, offset: 0x7A0 */
13245 __IO uint32_t DX0MDLR1; /**< DATX8 n Master Delay Line Register 1, offset: 0x7A4 */
13246 uint8_t RESERVED_36[24];
13247 __IO uint32_t DX0GTR0; /**< DATX8 n General Timing Register 0, offset: 0x7C0 */
13248 uint8_t RESERVED_37[12];
13249 __I uint32_t DX0RSR0; /**< DATX8 n Rank Status Register 0, offset: 0x7D0 */
13250 __I uint32_t DX0RSR1; /**< DATX8 n Rank Status Register 1, offset: 0x7D4 */
13251 __I uint32_t DX0RSR2; /**< DATX8 n Rank Status Register 2, offset: 0x7D8 */
13252 __I uint32_t DX0RSR3; /**< DATX8 n Rank Status Register 3, offset: 0x7DC */
13253 __I uint32_t DX0GSR0; /**< DATX8 n General Status Register 0, offset: 0x7E0 */
13254 __I uint32_t DX0GSR1; /**< DATX8 n General Status Register 1, offset: 0x7E4 */
13255 __I uint32_t DX0GSR2; /**< DATX8 n General Status Register 2, offset: 0x7E8 */
13256 __I uint32_t DX0GSR3; /**< DATX8 n General Status Register 3, offset: 0x7EC */
13257 __I uint32_t DX0GSR4; /**< DATX8 n General Status Register 4, offset: 0x7F0 */
13258 __I uint32_t DX0GSR5; /**< DATX8 n General Status Register 5, offset: 0x7F4 */
13259 __I uint32_t DX0GSR6; /**< DATX8 n General Status Register 6, offset: 0x7F8 */
13260 uint8_t RESERVED_38[4];
13261 __IO uint32_t DX1GCR0; /**< DATX8 n General Configuration Register 0, offset: 0x800 */
13262 __IO uint32_t DX1GCR1; /**< DATX8 n General Configuration Register 1, offset: 0x804 */
13263 __IO uint32_t DX1GCR2; /**< DATX8 n General Configuration Register 2, offset: 0x808 */
13264 __IO uint32_t DX1GCR3; /**< DATX8 n General Configuration Register 3, offset: 0x80C */
13265 __IO uint32_t DX1GCR4; /**< DATX8 n General Configuration Register 4, offset: 0x810 */
13266 __IO uint32_t DX1GCR5; /**< DATX8 n General Configuration Register 5, offset: 0x814 */
13267 __IO uint32_t DX1GCR6; /**< DATX8 n General Configuration Register 6, offset: 0x818 */
13268 __IO uint32_t DX1GCR7; /**< DATX8 n General Configuration Register 7, offset: 0x81C */
13269 __I uint32_t DX1GCR8; /**< DATX8 n General Configuration Register 8, offset: 0x820 */
13270 __I uint32_t DX1GCR9; /**< DATX8 n General Configuration Register 9, offset: 0x824 */
13271 __IO uint32_t DX1DQMAP0; /**< DATX8 n DQ/DM Mapping Register 0, offset: 0x828 */
13272 __IO uint32_t DX1DQMAP1; /**< DATX8 n DQ/DM Mapping Register 1, offset: 0x82C */
13273 uint8_t RESERVED_39[16];
13274 __IO uint32_t DX1BDLR0; /**< DATX8 n Bit Delay Line Register 0, offset: 0x840 */
13275 __IO uint32_t DX1BDLR1; /**< DATX8 n Bit Delay Line Register 1, offset: 0x844 */
13276 __IO uint32_t DX1BDLR2; /**< DATX8 n Bit Delay Line Register 2, offset: 0x848 */
13277 uint8_t RESERVED_40[4];
13278 __IO uint32_t DX1BDLR3; /**< DATX8 n Bit Delay Line Register 3, offset: 0x850 */
13279 __IO uint32_t DX1BDLR4; /**< DATX8 n Bit Delay Line Register 4, offset: 0x854 */
13280 __IO uint32_t DX1BDLR5; /**< DATX8 n Bit Delay Line Register 5, offset: 0x858 */
13281 uint8_t RESERVED_41[4];
13282 __IO uint32_t DX1BDLR6; /**< DATX8 n Bit Delay Line Register 6, offset: 0x860 */
13283 __I uint32_t DX1BDLR7; /**< DATX8 n Bit Delay Line Register 7, offset: 0x864 */
13284 __I uint32_t DX1BDLR8; /**< DATX8 n Bit Delay Line Register 8, offset: 0x868 */
13285 __I uint32_t DX1BDLR9; /**< DATX8 n Bit Delay Line Register 9, offset: 0x86C */
13286 uint8_t RESERVED_42[16];
13287 __IO uint32_t DX1LCDLR0; /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0x880 */
13288 __IO uint32_t DX1LCDLR1; /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0x884 */
13289 __IO uint32_t DX1LCDLR2; /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0x888 */
13290 __IO uint32_t DX1LCDLR3; /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0x88C */
13291 __IO uint32_t DX1LCDLR4; /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0x890 */
13292 __IO uint32_t DX1LCDLR5; /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0x894 */
13293 uint8_t RESERVED_43[8];
13294 __IO uint32_t DX1MDLR0; /**< DATX8 n Master Delay Line Register 0, offset: 0x8A0 */
13295 __IO uint32_t DX1MDLR1; /**< DATX8 n Master Delay Line Register 1, offset: 0x8A4 */
13296 uint8_t RESERVED_44[24];
13297 __IO uint32_t DX1GTR0; /**< DATX8 n General Timing Register 0, offset: 0x8C0 */
13298 uint8_t RESERVED_45[12];
13299 __I uint32_t DX1RSR0; /**< DATX8 n Rank Status Register 0, offset: 0x8D0 */
13300 __I uint32_t DX1RSR1; /**< DATX8 n Rank Status Register 1, offset: 0x8D4 */
13301 __I uint32_t DX1RSR2; /**< DATX8 n Rank Status Register 2, offset: 0x8D8 */
13302 __I uint32_t DX1RSR3; /**< DATX8 n Rank Status Register 3, offset: 0x8DC */
13303 __I uint32_t DX1GSR0; /**< DATX8 n General Status Register 0, offset: 0x8E0 */
13304 __I uint32_t DX1GSR1; /**< DATX8 n General Status Register 1, offset: 0x8E4 */
13305 __I uint32_t DX1GSR2; /**< DATX8 n General Status Register 2, offset: 0x8E8 */
13306 __I uint32_t DX1GSR3; /**< DATX8 n General Status Register 3, offset: 0x8EC */
13307 __I uint32_t DX1GSR4; /**< DATX8 n General Status Register 4, offset: 0x8F0 */
13308 __I uint32_t DX1GSR5; /**< DATX8 n General Status Register 5, offset: 0x8F4 */
13309 __I uint32_t DX1GSR6; /**< DATX8 n General Status Register 6, offset: 0x8F8 */
13310 uint8_t RESERVED_46[4];
13311 __IO uint32_t DX2GCR0; /**< DATX8 n General Configuration Register 0, offset: 0x900 */
13312 __IO uint32_t DX2GCR1; /**< DATX8 n General Configuration Register 1, offset: 0x904 */
13313 __IO uint32_t DX2GCR2; /**< DATX8 n General Configuration Register 2, offset: 0x908 */
13314 __IO uint32_t DX2GCR3; /**< DATX8 n General Configuration Register 3, offset: 0x90C */
13315 __IO uint32_t DX2GCR4; /**< DATX8 n General Configuration Register 4, offset: 0x910 */
13316 __IO uint32_t DX2GCR5; /**< DATX8 n General Configuration Register 5, offset: 0x914 */
13317 __IO uint32_t DX2GCR6; /**< DATX8 n General Configuration Register 6, offset: 0x918 */
13318 __IO uint32_t DX2GCR7; /**< DATX8 n General Configuration Register 7, offset: 0x91C */
13319 __I uint32_t DX2GCR8; /**< DATX8 n General Configuration Register 8, offset: 0x920 */
13320 __I uint32_t DX2GCR9; /**< DATX8 n General Configuration Register 9, offset: 0x924 */
13321 __IO uint32_t DX2DQMAP0; /**< DATX8 n DQ/DM Mapping Register 0, offset: 0x928 */
13322 __IO uint32_t DX2DQMAP1; /**< DATX8 n DQ/DM Mapping Register 1, offset: 0x92C */
13323 uint8_t RESERVED_47[16];
13324 __IO uint32_t DX2BDLR0; /**< DATX8 n Bit Delay Line Register 0, offset: 0x940 */
13325 __IO uint32_t DX2BDLR1; /**< DATX8 n Bit Delay Line Register 1, offset: 0x944 */
13326 __IO uint32_t DX2BDLR2; /**< DATX8 n Bit Delay Line Register 2, offset: 0x948 */
13327 uint8_t RESERVED_48[4];
13328 __IO uint32_t DX2BDLR3; /**< DATX8 n Bit Delay Line Register 3, offset: 0x950 */
13329 __IO uint32_t DX2BDLR4; /**< DATX8 n Bit Delay Line Register 4, offset: 0x954 */
13330 __IO uint32_t DX2BDLR5; /**< DATX8 n Bit Delay Line Register 5, offset: 0x958 */
13331 uint8_t RESERVED_49[4];
13332 __IO uint32_t DX2BDLR6; /**< DATX8 n Bit Delay Line Register 6, offset: 0x960 */
13333 __I uint32_t DX2BDLR7; /**< DATX8 n Bit Delay Line Register 7, offset: 0x964 */
13334 __I uint32_t DX2BDLR8; /**< DATX8 n Bit Delay Line Register 8, offset: 0x968 */
13335 __I uint32_t DX2BDLR9; /**< DATX8 n Bit Delay Line Register 9, offset: 0x96C */
13336 uint8_t RESERVED_50[16];
13337 __IO uint32_t DX2LCDLR0; /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0x980 */
13338 __IO uint32_t DX2LCDLR1; /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0x984 */
13339 __IO uint32_t DX2LCDLR2; /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0x988 */
13340 __IO uint32_t DX2LCDLR3; /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0x98C */
13341 __IO uint32_t DX2LCDLR4; /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0x990 */
13342 __IO uint32_t DX2LCDLR5; /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0x994 */
13343 uint8_t RESERVED_51[8];
13344 __IO uint32_t DX2MDLR0; /**< DATX8 n Master Delay Line Register 0, offset: 0x9A0 */
13345 __IO uint32_t DX2MDLR1; /**< DATX8 n Master Delay Line Register 1, offset: 0x9A4 */
13346 uint8_t RESERVED_52[24];
13347 __IO uint32_t DX2GTR0; /**< DATX8 n General Timing Register 0, offset: 0x9C0 */
13348 uint8_t RESERVED_53[12];
13349 __I uint32_t DX2RSR0; /**< DATX8 n Rank Status Register 0, offset: 0x9D0 */
13350 __I uint32_t DX2RSR1; /**< DATX8 n Rank Status Register 1, offset: 0x9D4 */
13351 __I uint32_t DX2RSR2; /**< DATX8 n Rank Status Register 2, offset: 0x9D8 */
13352 __I uint32_t DX2RSR3; /**< DATX8 n Rank Status Register 3, offset: 0x9DC */
13353 __I uint32_t DX2GSR0; /**< DATX8 n General Status Register 0, offset: 0x9E0 */
13354 __I uint32_t DX2GSR1; /**< DATX8 n General Status Register 1, offset: 0x9E4 */
13355 __I uint32_t DX2GSR2; /**< DATX8 n General Status Register 2, offset: 0x9E8 */
13356 __I uint32_t DX2GSR3; /**< DATX8 n General Status Register 3, offset: 0x9EC */
13357 __I uint32_t DX2GSR4; /**< DATX8 n General Status Register 4, offset: 0x9F0 */
13358 __I uint32_t DX2GSR5; /**< DATX8 n General Status Register 5, offset: 0x9F4 */
13359 __I uint32_t DX2GSR6; /**< DATX8 n General Status Register 6, offset: 0x9F8 */
13360 uint8_t RESERVED_54[4];
13361 __IO uint32_t DX3GCR0; /**< DATX8 n General Configuration Register 0, offset: 0xA00 */
13362 __IO uint32_t DX3GCR1; /**< DATX8 n General Configuration Register 1, offset: 0xA04 */
13363 __IO uint32_t DX3GCR2; /**< DATX8 n General Configuration Register 2, offset: 0xA08 */
13364 __IO uint32_t DX3GCR3; /**< DATX8 n General Configuration Register 3, offset: 0xA0C */
13365 __IO uint32_t DX3GCR4; /**< DATX8 n General Configuration Register 4, offset: 0xA10 */
13366 __IO uint32_t DX3GCR5; /**< DATX8 n General Configuration Register 5, offset: 0xA14 */
13367 __IO uint32_t DX3GCR6; /**< DATX8 n General Configuration Register 6, offset: 0xA18 */
13368 __IO uint32_t DX3GCR7; /**< DATX8 n General Configuration Register 7, offset: 0xA1C */
13369 __I uint32_t DX3GCR8; /**< DATX8 n General Configuration Register 8, offset: 0xA20 */
13370 __I uint32_t DX3GCR9; /**< DATX8 n General Configuration Register 9, offset: 0xA24 */
13371 __IO uint32_t DX3DQMAP0; /**< DATX8 n DQ/DM Mapping Register 0, offset: 0xA28 */
13372 __IO uint32_t DX3DQMAP1; /**< DATX8 n DQ/DM Mapping Register 1, offset: 0xA2C */
13373 uint8_t RESERVED_55[16];
13374 __IO uint32_t DX3BDLR0; /**< DATX8 n Bit Delay Line Register 0, offset: 0xA40 */
13375 __IO uint32_t DX3BDLR1; /**< DATX8 n Bit Delay Line Register 1, offset: 0xA44 */
13376 __IO uint32_t DX3BDLR2; /**< DATX8 n Bit Delay Line Register 2, offset: 0xA48 */
13377 uint8_t RESERVED_56[4];
13378 __IO uint32_t DX3BDLR3; /**< DATX8 n Bit Delay Line Register 3, offset: 0xA50 */
13379 __IO uint32_t DX3BDLR4; /**< DATX8 n Bit Delay Line Register 4, offset: 0xA54 */
13380 __IO uint32_t DX3BDLR5; /**< DATX8 n Bit Delay Line Register 5, offset: 0xA58 */
13381 uint8_t RESERVED_57[4];
13382 __IO uint32_t DX3BDLR6; /**< DATX8 n Bit Delay Line Register 6, offset: 0xA60 */
13383 __I uint32_t DX3BDLR7; /**< DATX8 n Bit Delay Line Register 7, offset: 0xA64 */
13384 __I uint32_t DX3BDLR8; /**< DATX8 n Bit Delay Line Register 8, offset: 0xA68 */
13385 __I uint32_t DX3BDLR9; /**< DATX8 n Bit Delay Line Register 9, offset: 0xA6C */
13386 uint8_t RESERVED_58[16];
13387 __IO uint32_t DX3LCDLR0; /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0xA80 */
13388 __IO uint32_t DX3LCDLR1; /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0xA84 */
13389 __IO uint32_t DX3LCDLR2; /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0xA88 */
13390 __IO uint32_t DX3LCDLR3; /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0xA8C */
13391 __IO uint32_t DX3LCDLR4; /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0xA90 */
13392 __IO uint32_t DX3LCDLR5; /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0xA94 */
13393 uint8_t RESERVED_59[8];
13394 __IO uint32_t DX3MDLR0; /**< DATX8 n Master Delay Line Register 0, offset: 0xAA0 */
13395 __IO uint32_t DX3MDLR1; /**< DATX8 n Master Delay Line Register 1, offset: 0xAA4 */
13396 uint8_t RESERVED_60[24];
13397 __IO uint32_t DX3GTR0; /**< DATX8 n General Timing Register 0, offset: 0xAC0 */
13398 uint8_t RESERVED_61[12];
13399 __I uint32_t DX3RSR0; /**< DATX8 n Rank Status Register 0, offset: 0xAD0 */
13400 __I uint32_t DX3RSR1; /**< DATX8 n Rank Status Register 1, offset: 0xAD4 */
13401 __I uint32_t DX3RSR2; /**< DATX8 n Rank Status Register 2, offset: 0xAD8 */
13402 __I uint32_t DX3RSR3; /**< DATX8 n Rank Status Register 3, offset: 0xADC */
13403 __I uint32_t DX3GSR0; /**< DATX8 n General Status Register 0, offset: 0xAE0 */
13404 __I uint32_t DX3GSR1; /**< DATX8 n General Status Register 1, offset: 0xAE4 */
13405 __I uint32_t DX3GSR2; /**< DATX8 n General Status Register 2, offset: 0xAE8 */
13406 __I uint32_t DX3GSR3; /**< DATX8 n General Status Register 3, offset: 0xAEC */
13407 __I uint32_t DX3GSR4; /**< DATX8 n General Status Register 4, offset: 0xAF0 */
13408 __I uint32_t DX3GSR5; /**< DATX8 n General Status Register 5, offset: 0xAF4 */
13409 __I uint32_t DX3GSR6; /**< DATX8 n General Status Register 6, offset: 0xAF8 */
13410 uint8_t RESERVED_62[4];
13411 __I uint32_t DX4GCR0; /**< DATX8 n General Configuration Register 0, offset: 0xB00 */
13412 __I uint32_t DX4GCR1; /**< DATX8 n General Configuration Register 1, offset: 0xB04 */
13413 __I uint32_t DX4GCR2; /**< DATX8 n General Configuration Register 2, offset: 0xB08 */
13414 __I uint32_t DX4GCR3; /**< DATX8 n General Configuration Register 3, offset: 0xB0C */
13415 __I uint32_t DX4GCR4; /**< DATX8 n General Configuration Register 4, offset: 0xB10 */
13416 __I uint32_t DX4GCR5; /**< DATX8 n General Configuration Register 5, offset: 0xB14 */
13417 __I uint32_t DX4GCR6; /**< DATX8 n General Configuration Register 6, offset: 0xB18 */
13418 __I uint32_t DX4GCR7; /**< DATX8 n General Configuration Register 7, offset: 0xB1C */
13419 __I uint32_t DX4GCR8; /**< DATX8 n General Configuration Register 8, offset: 0xB20 */
13420 __I uint32_t DX4GCR9; /**< DATX8 n General Configuration Register 9, offset: 0xB24 */
13421 __I uint32_t DX4DQMAP0; /**< DATX8 n DQ/DM Mapping Register 0, offset: 0xB28 */
13422 __I uint32_t DX4DQMAP1; /**< DATX8 n DQ/DM Mapping Register 1, offset: 0xB2C */
13423 uint8_t RESERVED_63[16];
13424 __I uint32_t DX4BDLR0; /**< DATX8 n Bit Delay Line Register 0, offset: 0xB40 */
13425 __I uint32_t DX4BDLR1; /**< DATX8 n Bit Delay Line Register 1, offset: 0xB44 */
13426 __I uint32_t DX4BDLR2; /**< DATX8 n Bit Delay Line Register 2, offset: 0xB48 */
13427 uint8_t RESERVED_64[4];
13428 __I uint32_t DX4BDLR3; /**< DATX8 n Bit Delay Line Register 3, offset: 0xB50 */
13429 __I uint32_t DX4BDLR4; /**< DATX8 n Bit Delay Line Register 4, offset: 0xB54 */
13430 __I uint32_t DX4BDLR5; /**< DATX8 n Bit Delay Line Register 5, offset: 0xB58 */
13431 uint8_t RESERVED_65[4];
13432 __I uint32_t DX4BDLR6; /**< DATX8 n Bit Delay Line Register 6, offset: 0xB60 */
13433 __I uint32_t DX4BDLR7; /**< DATX8 n Bit Delay Line Register 7, offset: 0xB64 */
13434 __I uint32_t DX4BDLR8; /**< DATX8 n Bit Delay Line Register 8, offset: 0xB68 */
13435 __I uint32_t DX4BDLR9; /**< DATX8 n Bit Delay Line Register 9, offset: 0xB6C */
13436 uint8_t RESERVED_66[16];
13437 __I uint32_t DX4LCDLR0; /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0xB80 */
13438 __I uint32_t DX4LCDLR1; /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0xB84 */
13439 __I uint32_t DX4LCDLR2; /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0xB88 */
13440 __I uint32_t DX4LCDLR3; /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0xB8C */
13441 __I uint32_t DX4LCDLR4; /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0xB90 */
13442 __I uint32_t DX4LCDLR5; /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0xB94 */
13443 uint8_t RESERVED_67[8];
13444 __I uint32_t DX4MDLR0; /**< DATX8 n Master Delay Line Register 0, offset: 0xBA0 */
13445 __I uint32_t DX4MDLR1; /**< DATX8 n Master Delay Line Register 1, offset: 0xBA4 */
13446 uint8_t RESERVED_68[24];
13447 __I uint32_t DX4GTR0; /**< DATX8 n General Timing Register 0, offset: 0xBC0 */
13448 uint8_t RESERVED_69[12];
13449 __I uint32_t DX4RSR0; /**< DATX8 n Rank Status Register 0, offset: 0xBD0 */
13450 __I uint32_t DX4RSR1; /**< DATX8 n Rank Status Register 1, offset: 0xBD4 */
13451 __I uint32_t DX4RSR2; /**< DATX8 n Rank Status Register 2, offset: 0xBD8 */
13452 __I uint32_t DX4RSR3; /**< DATX8 n Rank Status Register 3, offset: 0xBDC */
13453 __I uint32_t DX4GSR0; /**< DATX8 n General Status Register 0, offset: 0xBE0 */
13454 __I uint32_t DX4GSR1; /**< DATX8 n General Status Register 1, offset: 0xBE4 */
13455 __I uint32_t DX4GSR2; /**< DATX8 n General Status Register 2, offset: 0xBE8 */
13456 __I uint32_t DX4GSR3; /**< DATX8 n General Status Register 3, offset: 0xBEC */
13457 __I uint32_t DX4GSR4; /**< DATX8 n General Status Register 4, offset: 0xBF0 */
13458 __I uint32_t DX4GSR5; /**< DATX8 n General Status Register 5, offset: 0xBF4 */
13459 __I uint32_t DX4GSR6; /**< DATX8 n General Status Register 6, offset: 0xBF8 */
13460 uint8_t RESERVED_70[4];
13461 __I uint32_t DX5GCR0; /**< DATX8 n General Configuration Register 0, offset: 0xC00 */
13462 __I uint32_t DX5GCR1; /**< DATX8 n General Configuration Register 1, offset: 0xC04 */
13463 __I uint32_t DX5GCR2; /**< DATX8 n General Configuration Register 2, offset: 0xC08 */
13464 __I uint32_t DX5GCR3; /**< DATX8 n General Configuration Register 3, offset: 0xC0C */
13465 __I uint32_t DX5GCR4; /**< DATX8 n General Configuration Register 4, offset: 0xC10 */
13466 __I uint32_t DX5GCR5; /**< DATX8 n General Configuration Register 5, offset: 0xC14 */
13467 __I uint32_t DX5GCR6; /**< DATX8 n General Configuration Register 6, offset: 0xC18 */
13468 __I uint32_t DX5GCR7; /**< DATX8 n General Configuration Register 7, offset: 0xC1C */
13469 __I uint32_t DX5GCR8; /**< DATX8 n General Configuration Register 8, offset: 0xC20 */
13470 __I uint32_t DX5GCR9; /**< DATX8 n General Configuration Register 9, offset: 0xC24 */
13471 __I uint32_t DX5DQMAP0; /**< DATX8 n DQ/DM Mapping Register 0, offset: 0xC28 */
13472 __I uint32_t DX5DQMAP1; /**< DATX8 n DQ/DM Mapping Register 1, offset: 0xC2C */
13473 uint8_t RESERVED_71[16];
13474 __I uint32_t DX5BDLR0; /**< DATX8 n Bit Delay Line Register 0, offset: 0xC40 */
13475 __I uint32_t DX5BDLR1; /**< DATX8 n Bit Delay Line Register 1, offset: 0xC44 */
13476 __I uint32_t DX5BDLR2; /**< DATX8 n Bit Delay Line Register 2, offset: 0xC48 */
13477 uint8_t RESERVED_72[4];
13478 __I uint32_t DX5BDLR3; /**< DATX8 n Bit Delay Line Register 3, offset: 0xC50 */
13479 __I uint32_t DX5BDLR4; /**< DATX8 n Bit Delay Line Register 4, offset: 0xC54 */
13480 __I uint32_t DX5BDLR5; /**< DATX8 n Bit Delay Line Register 5, offset: 0xC58 */
13481 uint8_t RESERVED_73[4];
13482 __I uint32_t DX5BDLR6; /**< DATX8 n Bit Delay Line Register 6, offset: 0xC60 */
13483 __I uint32_t DX5BDLR7; /**< DATX8 n Bit Delay Line Register 7, offset: 0xC64 */
13484 __I uint32_t DX5BDLR8; /**< DATX8 n Bit Delay Line Register 8, offset: 0xC68 */
13485 __I uint32_t DX5BDLR9; /**< DATX8 n Bit Delay Line Register 9, offset: 0xC6C */
13486 uint8_t RESERVED_74[16];
13487 __I uint32_t DX5LCDLR0; /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0xC80 */
13488 __I uint32_t DX5LCDLR1; /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0xC84 */
13489 __I uint32_t DX5LCDLR2; /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0xC88 */
13490 __I uint32_t DX5LCDLR3; /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0xC8C */
13491 __I uint32_t DX5LCDLR4; /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0xC90 */
13492 __I uint32_t DX5LCDLR5; /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0xC94 */
13493 uint8_t RESERVED_75[8];
13494 __I uint32_t DX5MDLR0; /**< DATX8 n Master Delay Line Register 0, offset: 0xCA0 */
13495 __I uint32_t DX5MDLR1; /**< DATX8 n Master Delay Line Register 1, offset: 0xCA4 */
13496 uint8_t RESERVED_76[24];
13497 __I uint32_t DX5GTR0; /**< DATX8 n General Timing Register 0, offset: 0xCC0 */
13498 uint8_t RESERVED_77[12];
13499 __I uint32_t DX5RSR0; /**< DATX8 n Rank Status Register 0, offset: 0xCD0 */
13500 __I uint32_t DX5RSR1; /**< DATX8 n Rank Status Register 1, offset: 0xCD4 */
13501 __I uint32_t DX5RSR2; /**< DATX8 n Rank Status Register 2, offset: 0xCD8 */
13502 __I uint32_t DX5RSR3; /**< DATX8 n Rank Status Register 3, offset: 0xCDC */
13503 __I uint32_t DX5GSR0; /**< DATX8 n General Status Register 0, offset: 0xCE0 */
13504 __I uint32_t DX5GSR1; /**< DATX8 n General Status Register 1, offset: 0xCE4 */
13505 __I uint32_t DX5GSR2; /**< DATX8 n General Status Register 2, offset: 0xCE8 */
13506 __I uint32_t DX5GSR3; /**< DATX8 n General Status Register 3, offset: 0xCEC */
13507 __I uint32_t DX5GSR4; /**< DATX8 n General Status Register 4, offset: 0xCF0 */
13508 __I uint32_t DX5GSR5; /**< DATX8 n General Status Register 5, offset: 0xCF4 */
13509 __I uint32_t DX5GSR6; /**< DATX8 n General Status Register 6, offset: 0xCF8 */
13510 uint8_t RESERVED_78[4];
13511 __I uint32_t DX6GCR0; /**< DATX8 n General Configuration Register 0, offset: 0xD00 */
13512 __I uint32_t DX6GCR1; /**< DATX8 n General Configuration Register 1, offset: 0xD04 */
13513 __I uint32_t DX6GCR2; /**< DATX8 n General Configuration Register 2, offset: 0xD08 */
13514 __I uint32_t DX6GCR3; /**< DATX8 n General Configuration Register 3, offset: 0xD0C */
13515 __I uint32_t DX6GCR4; /**< DATX8 n General Configuration Register 4, offset: 0xD10 */
13516 __I uint32_t DX6GCR5; /**< DATX8 n General Configuration Register 5, offset: 0xD14 */
13517 __I uint32_t DX6GCR6; /**< DATX8 n General Configuration Register 6, offset: 0xD18 */
13518 __I uint32_t DX6GCR7; /**< DATX8 n General Configuration Register 7, offset: 0xD1C */
13519 __I uint32_t DX6GCR8; /**< DATX8 n General Configuration Register 8, offset: 0xD20 */
13520 __I uint32_t DX6GCR9; /**< DATX8 n General Configuration Register 9, offset: 0xD24 */
13521 __I uint32_t DX6DQMAP0; /**< DATX8 n DQ/DM Mapping Register 0, offset: 0xD28 */
13522 __I uint32_t DX6DQMAP1; /**< DATX8 n DQ/DM Mapping Register 1, offset: 0xD2C */
13523 uint8_t RESERVED_79[16];
13524 __I uint32_t DX6BDLR0; /**< DATX8 n Bit Delay Line Register 0, offset: 0xD40 */
13525 __I uint32_t DX6BDLR1; /**< DATX8 n Bit Delay Line Register 1, offset: 0xD44 */
13526 __I uint32_t DX6BDLR2; /**< DATX8 n Bit Delay Line Register 2, offset: 0xD48 */
13527 uint8_t RESERVED_80[4];
13528 __I uint32_t DX6BDLR3; /**< DATX8 n Bit Delay Line Register 3, offset: 0xD50 */
13529 __I uint32_t DX6BDLR4; /**< DATX8 n Bit Delay Line Register 4, offset: 0xD54 */
13530 __I uint32_t DX6BDLR5; /**< DATX8 n Bit Delay Line Register 5, offset: 0xD58 */
13531 uint8_t RESERVED_81[4];
13532 __I uint32_t DX6BDLR6; /**< DATX8 n Bit Delay Line Register 6, offset: 0xD60 */
13533 __I uint32_t DX6BDLR7; /**< DATX8 n Bit Delay Line Register 7, offset: 0xD64 */
13534 __I uint32_t DX6BDLR8; /**< DATX8 n Bit Delay Line Register 8, offset: 0xD68 */
13535 __I uint32_t DX6BDLR9; /**< DATX8 n Bit Delay Line Register 9, offset: 0xD6C */
13536 uint8_t RESERVED_82[16];
13537 __I uint32_t DX6LCDLR0; /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0xD80 */
13538 __I uint32_t DX6LCDLR1; /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0xD84 */
13539 __I uint32_t DX6LCDLR2; /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0xD88 */
13540 __I uint32_t DX6LCDLR3; /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0xD8C */
13541 __I uint32_t DX6LCDLR4; /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0xD90 */
13542 __I uint32_t DX6LCDLR5; /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0xD94 */
13543 uint8_t RESERVED_83[8];
13544 __I uint32_t DX6MDLR0; /**< DATX8 n Master Delay Line Register 0, offset: 0xDA0 */
13545 __I uint32_t DX6MDLR1; /**< DATX8 n Master Delay Line Register 1, offset: 0xDA4 */
13546 uint8_t RESERVED_84[24];
13547 __I uint32_t DX6GTR0; /**< DATX8 n General Timing Register 0, offset: 0xDC0 */
13548 uint8_t RESERVED_85[12];
13549 __I uint32_t DX6RSR0; /**< DATX8 n Rank Status Register 0, offset: 0xDD0 */
13550 __I uint32_t DX6RSR1; /**< DATX8 n Rank Status Register 1, offset: 0xDD4 */
13551 __I uint32_t DX6RSR2; /**< DATX8 n Rank Status Register 2, offset: 0xDD8 */
13552 __I uint32_t DX6RSR3; /**< DATX8 n Rank Status Register 3, offset: 0xDDC */
13553 __I uint32_t DX6GSR0; /**< DATX8 n General Status Register 0, offset: 0xDE0 */
13554 __I uint32_t DX6GSR1; /**< DATX8 n General Status Register 1, offset: 0xDE4 */
13555 __I uint32_t DX6GSR2; /**< DATX8 n General Status Register 2, offset: 0xDE8 */
13556 __I uint32_t DX6GSR3; /**< DATX8 n General Status Register 3, offset: 0xDEC */
13557 __I uint32_t DX6GSR4; /**< DATX8 n General Status Register 4, offset: 0xDF0 */
13558 __I uint32_t DX6GSR5; /**< DATX8 n General Status Register 5, offset: 0xDF4 */
13559 __I uint32_t DX6GSR6; /**< DATX8 n General Status Register 6, offset: 0xDF8 */
13560 uint8_t RESERVED_86[4];
13561 __I uint32_t DX7GCR0; /**< DATX8 n General Configuration Register 0, offset: 0xE00 */
13562 __I uint32_t DX7GCR1; /**< DATX8 n General Configuration Register 1, offset: 0xE04 */
13563 __I uint32_t DX7GCR2; /**< DATX8 n General Configuration Register 2, offset: 0xE08 */
13564 __I uint32_t DX7GCR3; /**< DATX8 n General Configuration Register 3, offset: 0xE0C */
13565 __I uint32_t DX7GCR4; /**< DATX8 n General Configuration Register 4, offset: 0xE10 */
13566 __I uint32_t DX7GCR5; /**< DATX8 n General Configuration Register 5, offset: 0xE14 */
13567 __I uint32_t DX7GCR6; /**< DATX8 n General Configuration Register 6, offset: 0xE18 */
13568 __I uint32_t DX7GCR7; /**< DATX8 n General Configuration Register 7, offset: 0xE1C */
13569 __I uint32_t DX7GCR8; /**< DATX8 n General Configuration Register 8, offset: 0xE20 */
13570 __I uint32_t DX7GCR9; /**< DATX8 n General Configuration Register 9, offset: 0xE24 */
13571 __I uint32_t DX7DQMAP0; /**< DATX8 n DQ/DM Mapping Register 0, offset: 0xE28 */
13572 __I uint32_t DX7DQMAP1; /**< DATX8 n DQ/DM Mapping Register 1, offset: 0xE2C */
13573 uint8_t RESERVED_87[16];
13574 __I uint32_t DX7BDLR0; /**< DATX8 n Bit Delay Line Register 0, offset: 0xE40 */
13575 __I uint32_t DX7BDLR1; /**< DATX8 n Bit Delay Line Register 1, offset: 0xE44 */
13576 __I uint32_t DX7BDLR2; /**< DATX8 n Bit Delay Line Register 2, offset: 0xE48 */
13577 uint8_t RESERVED_88[4];
13578 __I uint32_t DX7BDLR3; /**< DATX8 n Bit Delay Line Register 3, offset: 0xE50 */
13579 __I uint32_t DX7BDLR4; /**< DATX8 n Bit Delay Line Register 4, offset: 0xE54 */
13580 __I uint32_t DX7BDLR5; /**< DATX8 n Bit Delay Line Register 5, offset: 0xE58 */
13581 uint8_t RESERVED_89[4];
13582 __I uint32_t DX7BDLR6; /**< DATX8 n Bit Delay Line Register 6, offset: 0xE60 */
13583 __I uint32_t DX7BDLR7; /**< DATX8 n Bit Delay Line Register 7, offset: 0xE64 */
13584 __I uint32_t DX7BDLR8; /**< DATX8 n Bit Delay Line Register 8, offset: 0xE68 */
13585 __I uint32_t DX7BDLR9; /**< DATX8 n Bit Delay Line Register 9, offset: 0xE6C */
13586 uint8_t RESERVED_90[16];
13587 __I uint32_t DX7LCDLR0; /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0xE80 */
13588 __I uint32_t DX7LCDLR1; /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0xE84 */
13589 __I uint32_t DX7LCDLR2; /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0xE88 */
13590 __I uint32_t DX7LCDLR3; /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0xE8C */
13591 __I uint32_t DX7LCDLR4; /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0xE90 */
13592 __I uint32_t DX7LCDLR5; /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0xE94 */
13593 uint8_t RESERVED_91[8];
13594 __I uint32_t DX7MDLR0; /**< DATX8 n Master Delay Line Register 0, offset: 0xEA0 */
13595 __I uint32_t DX7MDLR1; /**< DATX8 n Master Delay Line Register 1, offset: 0xEA4 */
13596 uint8_t RESERVED_92[24];
13597 __I uint32_t DX7GTR0; /**< DATX8 n General Timing Register 0, offset: 0xEC0 */
13598 uint8_t RESERVED_93[12];
13599 __I uint32_t DX7RSR0; /**< DATX8 n Rank Status Register 0, offset: 0xED0 */
13600 __I uint32_t DX7RSR1; /**< DATX8 n Rank Status Register 1, offset: 0xED4 */
13601 __I uint32_t DX7RSR2; /**< DATX8 n Rank Status Register 2, offset: 0xED8 */
13602 __I uint32_t DX7RSR3; /**< DATX8 n Rank Status Register 3, offset: 0xEDC */
13603 __I uint32_t DX7GSR0; /**< DATX8 n General Status Register 0, offset: 0xEE0 */
13604 __I uint32_t DX7GSR1; /**< DATX8 n General Status Register 1, offset: 0xEE4 */
13605 __I uint32_t DX7GSR2; /**< DATX8 n General Status Register 2, offset: 0xEE8 */
13606 __I uint32_t DX7GSR3; /**< DATX8 n General Status Register 3, offset: 0xEEC */
13607 __I uint32_t DX7GSR4; /**< DATX8 n General Status Register 4, offset: 0xEF0 */
13608 __I uint32_t DX7GSR5; /**< DATX8 n General Status Register 5, offset: 0xEF4 */
13609 __I uint32_t DX7GSR6; /**< DATX8 n General Status Register 6, offset: 0xEF8 */
13610 uint8_t RESERVED_94[4];
13611 __I uint32_t DX8GCR0; /**< DATX8 n General Configuration Register 0, offset: 0xF00 */
13612 __I uint32_t DX8GCR1; /**< DATX8 n General Configuration Register 1, offset: 0xF04 */
13613 __I uint32_t DX8GCR2; /**< DATX8 n General Configuration Register 2, offset: 0xF08 */
13614 __I uint32_t DX8GCR3; /**< DATX8 n General Configuration Register 3, offset: 0xF0C */
13615 __I uint32_t DX8GCR4; /**< DATX8 n General Configuration Register 4, offset: 0xF10 */
13616 __I uint32_t DX8GCR5; /**< DATX8 n General Configuration Register 5, offset: 0xF14 */
13617 __I uint32_t DX8GCR6; /**< DATX8 n General Configuration Register 6, offset: 0xF18 */
13618 __I uint32_t DX8GCR7; /**< DATX8 n General Configuration Register 7, offset: 0xF1C */
13619 __I uint32_t DX8GCR8; /**< DATX8 n General Configuration Register 8, offset: 0xF20 */
13620 __I uint32_t DX8GCR9; /**< DATX8 n General Configuration Register 9, offset: 0xF24 */
13621 __I uint32_t DX8DQMAP0; /**< DATX8 n DQ/DM Mapping Register 0, offset: 0xF28 */
13622 __I uint32_t DX8DQMAP1; /**< DATX8 n DQ/DM Mapping Register 1, offset: 0xF2C */
13623 uint8_t RESERVED_95[16];
13624 __I uint32_t DX8BDLR0; /**< DATX8 n Bit Delay Line Register 0, offset: 0xF40 */
13625 __I uint32_t DX8BDLR1; /**< DATX8 n Bit Delay Line Register 1, offset: 0xF44 */
13626 __I uint32_t DX8BDLR2; /**< DATX8 n Bit Delay Line Register 2, offset: 0xF48 */
13627 uint8_t RESERVED_96[4];
13628 __I uint32_t DX8BDLR3; /**< DATX8 n Bit Delay Line Register 3, offset: 0xF50 */
13629 __I uint32_t DX8BDLR4; /**< DATX8 n Bit Delay Line Register 4, offset: 0xF54 */
13630 __I uint32_t DX8BDLR5; /**< DATX8 n Bit Delay Line Register 5, offset: 0xF58 */
13631 uint8_t RESERVED_97[4];
13632 __I uint32_t DX8BDLR6; /**< DATX8 n Bit Delay Line Register 6, offset: 0xF60 */
13633 __I uint32_t DX8BDLR7; /**< DATX8 n Bit Delay Line Register 7, offset: 0xF64 */
13634 __I uint32_t DX8BDLR8; /**< DATX8 n Bit Delay Line Register 8, offset: 0xF68 */
13635 __I uint32_t DX8BDLR9; /**< DATX8 n Bit Delay Line Register 9, offset: 0xF6C */
13636 uint8_t RESERVED_98[16];
13637 __I uint32_t DX8LCDLR0; /**< DATX8 n Local Calibrated Delay Line Register 0, offset: 0xF80 */
13638 __I uint32_t DX8LCDLR1; /**< DATX8 n Local Calibrated Delay Line Register 1, offset: 0xF84 */
13639 __I uint32_t DX8LCDLR2; /**< DATX8 n Local Calibrated Delay Line Register 2, offset: 0xF88 */
13640 __I uint32_t DX8LCDLR3; /**< DATX8 n Local Calibrated Delay Line Register 3, offset: 0xF8C */
13641 __I uint32_t DX8LCDLR4; /**< DATX8 n Local Calibrated Delay Line Register 4, offset: 0xF90 */
13642 __I uint32_t DX8LCDLR5; /**< DATX8 n Local Calibrated Delay Line Register 5, offset: 0xF94 */
13643 uint8_t RESERVED_99[8];
13644 __I uint32_t DX8MDLR0; /**< DATX8 n Master Delay Line Register 0, offset: 0xFA0 */
13645 __I uint32_t DX8MDLR1; /**< DATX8 n Master Delay Line Register 1, offset: 0xFA4 */
13646 uint8_t RESERVED_100[24];
13647 __I uint32_t DX8GTR0; /**< DATX8 n General Timing Register 0, offset: 0xFC0 */
13648 uint8_t RESERVED_101[12];
13649 __I uint32_t DX8RSR0; /**< DATX8 n Rank Status Register 0, offset: 0xFD0 */
13650 __I uint32_t DX8RSR1; /**< DATX8 n Rank Status Register 1, offset: 0xFD4 */
13651 __I uint32_t DX8RSR2; /**< DATX8 n Rank Status Register 2, offset: 0xFD8 */
13652 __I uint32_t DX8RSR3; /**< DATX8 n Rank Status Register 3, offset: 0xFDC */
13653 __I uint32_t DX8GSR0; /**< DATX8 n General Status Register 0, offset: 0xFE0 */
13654 __I uint32_t DX8GSR1; /**< DATX8 n General Status Register 1, offset: 0xFE4 */
13655 __I uint32_t DX8GSR2; /**< DATX8 n General Status Register 2, offset: 0xFE8 */
13656 __I uint32_t DX8GSR3; /**< DATX8 n General Status Register 3, offset: 0xFEC */
13657 __I uint32_t DX8GSR4; /**< DATX8 n General Status Register 4, offset: 0xFF0 */
13658 __I uint32_t DX8GSR5; /**< DATX8 n General Status Register 5, offset: 0xFF4 */
13659 __I uint32_t DX8GSR6; /**< DATX8 n General Status Register 6, offset: 0xFF8 */
13660 uint8_t RESERVED_102[1028];
13661 __IO uint32_t DX8SL0OSC; /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1400 */
13662 __IO uint32_t DX8SL0PLLCR0; /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1404 */
13663 __IO uint32_t DX8SL0PLLCR1; /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1408 */
13664 __IO uint32_t DX8SL0PLLCR2; /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x140C */
13665 __IO uint32_t DX8SL0PLLCR3; /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1410 */
13666 __IO uint32_t DX8SL0PLLCR4; /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1414 */
13667 __IO uint32_t DX8SL0PLLCR5; /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1418 */
13668 __IO uint32_t DX8SL0DQSCTL; /**< DATX8 0-1 DQS Control Register, offset: 0x141C */
13669 __I uint32_t DX8SL0TRNCTL; /**< DATX8 0-1 Training Control Register, offset: 0x1420 */
13670 __IO uint32_t DX8SL0DDLCTL; /**< DATX8 0-1 DDL Control Register, offset: 0x1424 */
13671 __IO uint32_t DX8SL0DXCTL1; /**< DATX8 0-1 DX Control Register 1, offset: 0x1428 */
13672 __IO uint32_t DX8SL0DXCTL2; /**< DATX8 0-1 DX Control Register 2, offset: 0x142C */
13673 __IO uint32_t DX8SL0IOCR; /**< DATX8 0-1 I/O Configuration Register, offset: 0x1430 */
13674 __I uint32_t DX4SL0IOCR; /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x1434 */
13675 uint8_t RESERVED_103[8];
13676 __IO uint32_t DX8SL1OSC; /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1440 */
13677 __IO uint32_t DX8SL1PLLCR0; /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1444 */
13678 __IO uint32_t DX8SL1PLLCR1; /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1448 */
13679 __IO uint32_t DX8SL1PLLCR2; /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x144C */
13680 __IO uint32_t DX8SL1PLLCR3; /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1450 */
13681 __IO uint32_t DX8SL1PLLCR4; /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1454 */
13682 __IO uint32_t DX8SL1PLLCR5; /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1458 */
13683 __IO uint32_t DX8SL1DQSCTL; /**< DATX8 0-1 DQS Control Register, offset: 0x145C */
13684 __I uint32_t DX8SL1TRNCTL; /**< DATX8 0-1 Training Control Register, offset: 0x1460 */
13685 __IO uint32_t DX8SL1DDLCTL; /**< DATX8 0-1 DDL Control Register, offset: 0x1464 */
13686 __IO uint32_t DX8SL1DXCTL1; /**< DATX8 0-1 DX Control Register 1, offset: 0x1468 */
13687 __IO uint32_t DX8SL1DXCTL2; /**< DATX8 0-1 DX Control Register 2, offset: 0x146C */
13688 __IO uint32_t DX8SL1IOCR; /**< DATX8 0-1 I/O Configuration Register, offset: 0x1470 */
13689 __I uint32_t DX4SL1IOCR; /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x1474 */
13690 uint8_t RESERVED_104[8];
13691 __IO uint32_t DX8SL2OSC; /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1480 */
13692 __IO uint32_t DX8SL2PLLCR0; /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1484 */
13693 __IO uint32_t DX8SL2PLLCR1; /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1488 */
13694 __IO uint32_t DX8SL2PLLCR2; /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x148C */
13695 __IO uint32_t DX8SL2PLLCR3; /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1490 */
13696 __IO uint32_t DX8SL2PLLCR4; /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1494 */
13697 __IO uint32_t DX8SL2PLLCR5; /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1498 */
13698 __IO uint32_t DX8SL2DQSCTL; /**< DATX8 0-1 DQS Control Register, offset: 0x149C */
13699 __I uint32_t DX8SL2TRNCTL; /**< DATX8 0-1 Training Control Register, offset: 0x14A0 */
13700 __IO uint32_t DX8SL2DDLCTL; /**< DATX8 0-1 DDL Control Register, offset: 0x14A4 */
13701 __IO uint32_t DX8SL2DXCTL1; /**< DATX8 0-1 DX Control Register 1, offset: 0x14A8 */
13702 __IO uint32_t DX8SL2DXCTL2; /**< DATX8 0-1 DX Control Register 2, offset: 0x14AC */
13703 __IO uint32_t DX8SL2IOCR; /**< DATX8 0-1 I/O Configuration Register, offset: 0x14B0 */
13704 __I uint32_t DX4SL2IOCR; /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x14B4 */
13705 uint8_t RESERVED_105[8];
13706 __I uint32_t DX8SL3OSC; /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x14C0 */
13707 __I uint32_t DX8SL3PLLCR0; /**< DAXT8 0-1 PLL Control Register 0, offset: 0x14C4 */
13708 __I uint32_t DX8SL3PLLCR1; /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x14C8 */
13709 __I uint32_t DX8SL3PLLCR2; /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x14CC */
13710 __I uint32_t DX8SL3PLLCR3; /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x14D0 */
13711 __I uint32_t DX8SL3PLLCR4; /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x14D4 */
13712 __I uint32_t DX8SL3PLLCR5; /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x14D8 */
13713 __I uint32_t DX8SL3DQSCTL; /**< DATX8 0-1 DQS Control Register, offset: 0x14DC */
13714 __I uint32_t DX8SL3TRNCTL; /**< DATX8 0-1 Training Control Register, offset: 0x14E0 */
13715 __I uint32_t DX8SL3DDLCTL; /**< DATX8 0-1 DDL Control Register, offset: 0x14E4 */
13716 __I uint32_t DX8SL3DXCTL1; /**< DATX8 0-1 DX Control Register 1, offset: 0x14E8 */
13717 __I uint32_t DX8SL3DXCTL2; /**< DATX8 0-1 DX Control Register 2, offset: 0x14EC */
13718 __I uint32_t DX8SL3IOCR; /**< DATX8 0-1 I/O Configuration Register, offset: 0x14F0 */
13719 __I uint32_t DX4SL3IOCR; /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x14F4 */
13720 uint8_t RESERVED_106[8];
13721 __I uint32_t DX8SL4OSC; /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1500 */
13722 __I uint32_t DX8SL4PLLCR0; /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1504 */
13723 __I uint32_t DX8SL4PLLCR1; /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1508 */
13724 __I uint32_t DX8SL4PLLCR2; /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x150C */
13725 __I uint32_t DX8SL4PLLCR3; /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1510 */
13726 __I uint32_t DX8SL4PLLCR4; /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1514 */
13727 __I uint32_t DX8SL4PLLCR5; /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1518 */
13728 __I uint32_t DX8SL4DQSCTL; /**< DATX8 0-1 DQS Control Register, offset: 0x151C */
13729 __I uint32_t DX8SL4TRNCTL; /**< DATX8 0-1 Training Control Register, offset: 0x1520 */
13730 __I uint32_t DX8SL4DDLCTL; /**< DATX8 0-1 DDL Control Register, offset: 0x1524 */
13731 __I uint32_t DX8SL4DXCTL1; /**< DATX8 0-1 DX Control Register 1, offset: 0x1528 */
13732 __I uint32_t DX8SL4DXCTL2; /**< DATX8 0-1 DX Control Register 2, offset: 0x152C */
13733 __I uint32_t DX8SL4IOCR; /**< DATX8 0-1 I/O Configuration Register, offset: 0x1530 */
13734 __I uint32_t DX4SL4IOCR; /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x1534 */
13735 uint8_t RESERVED_107[8];
13736 __I uint32_t DX8SL5OSC; /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1540 */
13737 __I uint32_t DX8SL5PLLCR0; /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1544 */
13738 __I uint32_t DX8SL5PLLCR1; /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1548 */
13739 __I uint32_t DX8SL5PLLCR2; /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x154C */
13740 __I uint32_t DX8SL5PLLCR3; /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1550 */
13741 __I uint32_t DX8SL5PLLCR4; /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1554 */
13742 __I uint32_t DX8SL5PLLCR5; /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1558 */
13743 __I uint32_t DX8SL5DQSCTL; /**< DATX8 0-1 DQS Control Register, offset: 0x155C */
13744 __I uint32_t DX8SL5TRNCTL; /**< DATX8 0-1 Training Control Register, offset: 0x1560 */
13745 __I uint32_t DX8SL5DDLCTL; /**< DATX8 0-1 DDL Control Register, offset: 0x1564 */
13746 __I uint32_t DX8SL5DXCTL1; /**< DATX8 0-1 DX Control Register 1, offset: 0x1568 */
13747 __I uint32_t DX8SL5DXCTL2; /**< DATX8 0-1 DX Control Register 2, offset: 0x156C */
13748 __I uint32_t DX8SL5IOCR; /**< DATX8 0-1 I/O Configuration Register, offset: 0x1570 */
13749 __I uint32_t DX4SL5IOCR; /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x1574 */
13750 uint8_t RESERVED_108[8];
13751 __I uint32_t DX8SL6OSC; /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1580 */
13752 __I uint32_t DX8SL6PLLCR0; /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1584 */
13753 __I uint32_t DX8SL6PLLCR1; /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1588 */
13754 __I uint32_t DX8SL6PLLCR2; /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x158C */
13755 __I uint32_t DX8SL6PLLCR3; /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1590 */
13756 __I uint32_t DX8SL6PLLCR4; /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1594 */
13757 __I uint32_t DX8SL6PLLCR5; /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1598 */
13758 __I uint32_t DX8SL6DQSCTL; /**< DATX8 0-1 DQS Control Register, offset: 0x159C */
13759 __I uint32_t DX8SL6TRNCTL; /**< DATX8 0-1 Training Control Register, offset: 0x15A0 */
13760 __I uint32_t DX8SL6DDLCTL; /**< DATX8 0-1 DDL Control Register, offset: 0x15A4 */
13761 __I uint32_t DX8SL6DXCTL1; /**< DATX8 0-1 DX Control Register 1, offset: 0x15A8 */
13762 __I uint32_t DX8SL6DXCTL2; /**< DATX8 0-1 DX Control Register 2, offset: 0x15AC */
13763 __I uint32_t DX8SL6IOCR; /**< DATX8 0-1 I/O Configuration Register, offset: 0x15B0 */
13764 __I uint32_t DX4SL6IOCR; /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x15B4 */
13765 uint8_t RESERVED_109[8];
13766 __I uint32_t DX8SL7OSC; /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x15C0 */
13767 __I uint32_t DX8SL7PLLCR0; /**< DAXT8 0-1 PLL Control Register 0, offset: 0x15C4 */
13768 __I uint32_t DX8SL7PLLCR1; /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x15C8 */
13769 __I uint32_t DX8SL7PLLCR2; /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x15CC */
13770 __I uint32_t DX8SL7PLLCR3; /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x15D0 */
13771 __I uint32_t DX8SL7PLLCR4; /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x15D4 */
13772 __I uint32_t DX8SL7PLLCR5; /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x15D8 */
13773 __I uint32_t DX8SL7DQSCTL; /**< DATX8 0-1 DQS Control Register, offset: 0x15DC */
13774 __I uint32_t DX8SL7TRNCTL; /**< DATX8 0-1 Training Control Register, offset: 0x15E0 */
13775 __I uint32_t DX8SL7DDLCTL; /**< DATX8 0-1 DDL Control Register, offset: 0x15E4 */
13776 __I uint32_t DX8SL7DXCTL1; /**< DATX8 0-1 DX Control Register 1, offset: 0x15E8 */
13777 __I uint32_t DX8SL7DXCTL2; /**< DATX8 0-1 DX Control Register 2, offset: 0x15EC */
13778 __I uint32_t DX8SL7IOCR; /**< DATX8 0-1 I/O Configuration Register, offset: 0x15F0 */
13779 __I uint32_t DX4SL7IOCR; /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x15F4 */
13780 uint8_t RESERVED_110[8];
13781 __I uint32_t DX8SL8OSC; /**< DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x1600 */
13782 __I uint32_t DX8SL8PLLCR0; /**< DAXT8 0-1 PLL Control Register 0, offset: 0x1604 */
13783 __I uint32_t DX8SL8PLLCR1; /**< DAXT8 0-1 PLL Control Register 1 (Type B PLL Only), offset: 0x1608 */
13784 __I uint32_t DX8SL8PLLCR2; /**< DAXT8 0-1 PLL Control Register 2 (Type B PLL Only), offset: 0x160C */
13785 __I uint32_t DX8SL8PLLCR3; /**< DAXT8 0-1 PLL Control Register 3 (Type B PLL Only), offset: 0x1610 */
13786 __I uint32_t DX8SL8PLLCR4; /**< DAXT8 0-1 PLL Control Register 4 (Type B PLL Only), offset: 0x1614 */
13787 __I uint32_t DX8SL8PLLCR5; /**< DAXT8 0-1 PLL Control Register 5 (Type B PLL Only), offset: 0x1618 */
13788 __I uint32_t DX8SL8DQSCTL; /**< DATX8 0-1 DQS Control Register, offset: 0x161C */
13789 __I uint32_t DX8SL8TRNCTL; /**< DATX8 0-1 Training Control Register, offset: 0x1620 */
13790 __I uint32_t DX8SL8DDLCTL; /**< DATX8 0-1 DDL Control Register, offset: 0x1624 */
13791 __I uint32_t DX8SL8DXCTL1; /**< DATX8 0-1 DX Control Register 1, offset: 0x1628 */
13792 __I uint32_t DX8SL8DXCTL2; /**< DATX8 0-1 DX Control Register 2, offset: 0x162C */
13793 __I uint32_t DX8SL8IOCR; /**< DATX8 0-1 I/O Configuration Register, offset: 0x1630 */
13794 __I uint32_t DX4SL8IOCR; /**< DATX4 Slice 0-1 I/O Configuration Register, offset: 0x1634 */
13795 uint8_t RESERVED_111[392];
13796 __O uint32_t DX8SLBOSC; /**< DATX8 0-8 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register, offset: 0x17C0 */
13797 __O uint32_t DX8SLBPLLCR0; /**< DAXT8 0-8 PLL Control Register 0, offset: 0x17C4 */
13798 __O uint32_t DX8SLBPLLCR1; /**< DAXT8 0-8 PLL Control Register 1 (Type B PLL Only), offset: 0x17C8 */
13799 __O uint32_t DX8SLBPLLCR2; /**< DAXT8 0-8 PLL Control Register 2 (Type B PLL Only), offset: 0x17CC */
13800 __O uint32_t DX8SLBPLLCR3; /**< DAXT8 0-8 PLL Control Register 3 (Type B PLL Only), offset: 0x17D0 */
13801 __O uint32_t DX8SLBPLLCR4; /**< DAXT8 0-8 PLL Control Register 4 (Type B PLL Only), offset: 0x17D4 */
13802 __O uint32_t DX8SLBPLLCR5; /**< DAXT8 0-8 PLL Control Register 5 (Type B PLL Only), offset: 0x17D8 */
13803 __O uint32_t DX8SLBDQSCTL; /**< DATX8 0-8 DQS Control Register, offset: 0x17DC */
13804 __O uint32_t DX8SLBTRNCTL; /**< DATX8 0-8 Training Control Register, offset: 0x17E0 */
13805 __O uint32_t DX8SLBDDLCTL; /**< DATX8 0-8 DDL Control Register, offset: 0x17E4 */
13806 __O uint32_t DX8SLBDXCTL1; /**< DATX8 0-8 DX Control Register 1, offset: 0x17E8 */
13807 __O uint32_t DX8SLBDXCTL2; /**< DATX8 0-8 DX Control Register 2, offset: 0x17EC */
13808 __O uint32_t DX8SLBIOCR; /**< DATX8 0-8 I/O Configuration Register, offset: 0x17F0 */
13809 __O uint32_t DX4SLBIOCR; /**< DATX4 0-8 I/O Configuration Register, offset: 0x17F4 */
13810} DDRPHY_Type;
13811
13812/* ----------------------------------------------------------------------------
13813 -- DDRPHY Register Masks
13814 ---------------------------------------------------------------------------- */
13815
13816/*!
13817 * @addtogroup DDRPHY_Register_Masks DDRPHY Register Masks
13818 * @{
13819 */
13820
13821/*! @name RIDR - Revision Identification Register */
13822/*! @{ */
13823#define DDRPHY_RIDR_PUBMNR_MASK (0xFU)
13824#define DDRPHY_RIDR_PUBMNR_SHIFT (0U)
13825/*! PUBMNR - PUB Minor Revision
13826 */
13827#define DDRPHY_RIDR_PUBMNR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_PUBMNR_SHIFT)) & DDRPHY_RIDR_PUBMNR_MASK)
13828#define DDRPHY_RIDR_PUBMDR_MASK (0xF0U)
13829#define DDRPHY_RIDR_PUBMDR_SHIFT (4U)
13830/*! PUBMDR - PUB Moderate Revision
13831 */
13832#define DDRPHY_RIDR_PUBMDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_PUBMDR_SHIFT)) & DDRPHY_RIDR_PUBMDR_MASK)
13833#define DDRPHY_RIDR_PUBMJR_MASK (0xF00U)
13834#define DDRPHY_RIDR_PUBMJR_SHIFT (8U)
13835/*! PUBMJR - PUB Major Revision
13836 */
13837#define DDRPHY_RIDR_PUBMJR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_PUBMJR_SHIFT)) & DDRPHY_RIDR_PUBMJR_MASK)
13838#define DDRPHY_RIDR_PHYMNR_MASK (0xF000U)
13839#define DDRPHY_RIDR_PHYMNR_SHIFT (12U)
13840/*! PHYMNR - PHY Minor Revision
13841 */
13842#define DDRPHY_RIDR_PHYMNR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_PHYMNR_SHIFT)) & DDRPHY_RIDR_PHYMNR_MASK)
13843#define DDRPHY_RIDR_PHYMDR_MASK (0xF0000U)
13844#define DDRPHY_RIDR_PHYMDR_SHIFT (16U)
13845/*! PHYMDR - PHY Moderate Revision
13846 */
13847#define DDRPHY_RIDR_PHYMDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_PHYMDR_SHIFT)) & DDRPHY_RIDR_PHYMDR_MASK)
13848#define DDRPHY_RIDR_PHYMJR_MASK (0xF00000U)
13849#define DDRPHY_RIDR_PHYMJR_SHIFT (20U)
13850/*! PHYMJR - PHY Major Revision
13851 */
13852#define DDRPHY_RIDR_PHYMJR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_PHYMJR_SHIFT)) & DDRPHY_RIDR_PHYMJR_MASK)
13853#define DDRPHY_RIDR_UDRID_MASK (0xFF000000U)
13854#define DDRPHY_RIDR_UDRID_SHIFT (24U)
13855/*! UDRID - User-Defined Revision ID
13856 */
13857#define DDRPHY_RIDR_UDRID(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIDR_UDRID_SHIFT)) & DDRPHY_RIDR_UDRID_MASK)
13858/*! @} */
13859
13860/*! @name PIR - PHY Initialization Register */
13861/*! @{ */
13862#define DDRPHY_PIR_INIT_MASK (0x1U)
13863#define DDRPHY_PIR_INIT_SHIFT (0U)
13864/*! INIT - Initialization Trigger
13865 */
13866#define DDRPHY_PIR_INIT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_INIT_SHIFT)) & DDRPHY_PIR_INIT_MASK)
13867#define DDRPHY_PIR_ZCAL_MASK (0x2U)
13868#define DDRPHY_PIR_ZCAL_SHIFT (1U)
13869/*! ZCAL - Impedance Calibration
13870 */
13871#define DDRPHY_PIR_ZCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_ZCAL_SHIFT)) & DDRPHY_PIR_ZCAL_MASK)
13872#define DDRPHY_PIR_CA_MASK (0x4U)
13873#define DDRPHY_PIR_CA_SHIFT (2U)
13874/*! CA - CA Training
13875 */
13876#define DDRPHY_PIR_CA(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_CA_SHIFT)) & DDRPHY_PIR_CA_MASK)
13877#define DDRPHY_PIR_RESERVED_3_MASK (0x8U)
13878#define DDRPHY_PIR_RESERVED_3_SHIFT (3U)
13879/*! RESERVED_3 - Reserved. Return zeroes on reads.
13880 */
13881#define DDRPHY_PIR_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_RESERVED_3_SHIFT)) & DDRPHY_PIR_RESERVED_3_MASK)
13882#define DDRPHY_PIR_PLLINIT_MASK (0x10U)
13883#define DDRPHY_PIR_PLLINIT_SHIFT (4U)
13884/*! PLLINIT - PLL Initialiazation
13885 */
13886#define DDRPHY_PIR_PLLINIT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_PLLINIT_SHIFT)) & DDRPHY_PIR_PLLINIT_MASK)
13887#define DDRPHY_PIR_DCAL_MASK (0x20U)
13888#define DDRPHY_PIR_DCAL_SHIFT (5U)
13889/*! DCAL - Digital Delay Line (DDL) Calibration
13890 */
13891#define DDRPHY_PIR_DCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_DCAL_SHIFT)) & DDRPHY_PIR_DCAL_MASK)
13892#define DDRPHY_PIR_PHYRST_MASK (0x40U)
13893#define DDRPHY_PIR_PHYRST_SHIFT (6U)
13894/*! PHYRST - PHY Reset
13895 */
13896#define DDRPHY_PIR_PHYRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_PHYRST_SHIFT)) & DDRPHY_PIR_PHYRST_MASK)
13897#define DDRPHY_PIR_DRAMRST_MASK (0x80U)
13898#define DDRPHY_PIR_DRAMRST_SHIFT (7U)
13899/*! DRAMRST - DRAM Reset (DDR3/DDR4/LPDDR4 Only)
13900 */
13901#define DDRPHY_PIR_DRAMRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_DRAMRST_SHIFT)) & DDRPHY_PIR_DRAMRST_MASK)
13902#define DDRPHY_PIR_DRAMINIT_MASK (0x100U)
13903#define DDRPHY_PIR_DRAMINIT_SHIFT (8U)
13904/*! DRAMINIT - DRAM Initialization
13905 */
13906#define DDRPHY_PIR_DRAMINIT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_DRAMINIT_SHIFT)) & DDRPHY_PIR_DRAMINIT_MASK)
13907#define DDRPHY_PIR_WL_MASK (0x200U)
13908#define DDRPHY_PIR_WL_SHIFT (9U)
13909/*! WL - Write Leveling
13910 */
13911#define DDRPHY_PIR_WL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_WL_SHIFT)) & DDRPHY_PIR_WL_MASK)
13912#define DDRPHY_PIR_QSGATE_MASK (0x400U)
13913#define DDRPHY_PIR_QSGATE_SHIFT (10U)
13914/*! QSGATE - Read DQS Gate Training
13915 */
13916#define DDRPHY_PIR_QSGATE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_QSGATE_SHIFT)) & DDRPHY_PIR_QSGATE_MASK)
13917#define DDRPHY_PIR_WLADJ_MASK (0x800U)
13918#define DDRPHY_PIR_WLADJ_SHIFT (11U)
13919/*! WLADJ - Write Leveling Adjust
13920 */
13921#define DDRPHY_PIR_WLADJ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_WLADJ_SHIFT)) & DDRPHY_PIR_WLADJ_MASK)
13922#define DDRPHY_PIR_RDDSKW_MASK (0x1000U)
13923#define DDRPHY_PIR_RDDSKW_SHIFT (12U)
13924/*! RDDSKW - Read Data Bit Deskew
13925 */
13926#define DDRPHY_PIR_RDDSKW(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_RDDSKW_SHIFT)) & DDRPHY_PIR_RDDSKW_MASK)
13927#define DDRPHY_PIR_WRDSKW_MASK (0x2000U)
13928#define DDRPHY_PIR_WRDSKW_SHIFT (13U)
13929/*! WRDSKW - Write Data Bit Deskew
13930 */
13931#define DDRPHY_PIR_WRDSKW(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_WRDSKW_SHIFT)) & DDRPHY_PIR_WRDSKW_MASK)
13932#define DDRPHY_PIR_RDEYE_MASK (0x4000U)
13933#define DDRPHY_PIR_RDEYE_SHIFT (14U)
13934/*! RDEYE - Read Data Eye Training
13935 */
13936#define DDRPHY_PIR_RDEYE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_RDEYE_SHIFT)) & DDRPHY_PIR_RDEYE_MASK)
13937#define DDRPHY_PIR_WREYE_MASK (0x8000U)
13938#define DDRPHY_PIR_WREYE_SHIFT (15U)
13939/*! WREYE - Write Data Eye Training
13940 */
13941#define DDRPHY_PIR_WREYE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_WREYE_SHIFT)) & DDRPHY_PIR_WREYE_MASK)
13942#define DDRPHY_PIR_SRD_MASK (0x10000U)
13943#define DDRPHY_PIR_SRD_SHIFT (16U)
13944/*! SRD - Static Read Training
13945 */
13946#define DDRPHY_PIR_SRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_SRD_SHIFT)) & DDRPHY_PIR_SRD_MASK)
13947#define DDRPHY_PIR_VREF_MASK (0x20000U)
13948#define DDRPHY_PIR_VREF_SHIFT (17U)
13949/*! VREF - VREF Training
13950 */
13951#define DDRPHY_PIR_VREF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_VREF_SHIFT)) & DDRPHY_PIR_VREF_MASK)
13952#define DDRPHY_PIR_CTLDINIT_MASK (0x40000U)
13953#define DDRPHY_PIR_CTLDINIT_SHIFT (18U)
13954/*! CTLDINIT - Controller DRAM Initialization
13955 */
13956#define DDRPHY_PIR_CTLDINIT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_CTLDINIT_SHIFT)) & DDRPHY_PIR_CTLDINIT_MASK)
13957#define DDRPHY_PIR_RDIMMINIT_MASK (0x80000U)
13958#define DDRPHY_PIR_RDIMMINIT_SHIFT (19U)
13959/*! RDIMMINIT - RDIMM Initialization
13960 */
13961#define DDRPHY_PIR_RDIMMINIT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_RDIMMINIT_SHIFT)) & DDRPHY_PIR_RDIMMINIT_MASK)
13962#define DDRPHY_PIR_DQS2DQ_MASK (0x100000U)
13963#define DDRPHY_PIR_DQS2DQ_SHIFT (20U)
13964/*! DQS2DQ - Write DQS2DQ Training
13965 */
13966#define DDRPHY_PIR_DQS2DQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_DQS2DQ_SHIFT)) & DDRPHY_PIR_DQS2DQ_MASK)
13967#define DDRPHY_PIR_RESERVED_28_21_MASK (0x1FE00000U)
13968#define DDRPHY_PIR_RESERVED_28_21_SHIFT (21U)
13969/*! RESERVED_28_21 - Reserved. Return zeroes on reads.
13970 */
13971#define DDRPHY_PIR_RESERVED_28_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_RESERVED_28_21_SHIFT)) & DDRPHY_PIR_RESERVED_28_21_MASK)
13972#define DDRPHY_PIR_DCALPSE_MASK (0x20000000U)
13973#define DDRPHY_PIR_DCALPSE_SHIFT (29U)
13974/*! DCALPSE - Digital Delay Line (DDL) Calibration Pause
13975 */
13976#define DDRPHY_PIR_DCALPSE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_DCALPSE_SHIFT)) & DDRPHY_PIR_DCALPSE_MASK)
13977#define DDRPHY_PIR_ZCALBYP_MASK (0x40000000U)
13978#define DDRPHY_PIR_ZCALBYP_SHIFT (30U)
13979/*! ZCALBYP - Impedance Calibration Bypass
13980 */
13981#define DDRPHY_PIR_ZCALBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_ZCALBYP_SHIFT)) & DDRPHY_PIR_ZCALBYP_MASK)
13982#define DDRPHY_PIR_RESERVED_31_MASK (0x80000000U)
13983#define DDRPHY_PIR_RESERVED_31_SHIFT (31U)
13984/*! RESERVED_31 - Reserved. Return zeroes on reads.
13985 */
13986#define DDRPHY_PIR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PIR_RESERVED_31_SHIFT)) & DDRPHY_PIR_RESERVED_31_MASK)
13987/*! @} */
13988
13989/*! @name PGCR0 - PHY General Configuration Register 0 */
13990/*! @{ */
13991#define DDRPHY_PGCR0_RESERVED_7_0_MASK (0xFFU)
13992#define DDRPHY_PGCR0_RESERVED_7_0_SHIFT (0U)
13993/*! RESERVED_7_0 - Reserved. Returns zeroes on reads.
13994 */
13995#define DDRPHY_PGCR0_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_RESERVED_7_0_SHIFT)) & DDRPHY_PGCR0_RESERVED_7_0_MASK)
13996#define DDRPHY_PGCR0_OSCEN_MASK (0x100U)
13997#define DDRPHY_PGCR0_OSCEN_SHIFT (8U)
13998/*! OSCEN - Oscillator Enable
13999 */
14000#define DDRPHY_PGCR0_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_OSCEN_SHIFT)) & DDRPHY_PGCR0_OSCEN_MASK)
14001#define DDRPHY_PGCR0_OSCDIV_MASK (0x1E00U)
14002#define DDRPHY_PGCR0_OSCDIV_SHIFT (9U)
14003/*! OSCDIV - Oscillator Mode Division
14004 */
14005#define DDRPHY_PGCR0_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_OSCDIV_SHIFT)) & DDRPHY_PGCR0_OSCDIV_MASK)
14006#define DDRPHY_PGCR0_RESERVED_13_MASK (0x2000U)
14007#define DDRPHY_PGCR0_RESERVED_13_SHIFT (13U)
14008/*! RESERVED_13 - Reserved. Returns zeroes on reads.
14009 */
14010#define DDRPHY_PGCR0_RESERVED_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_RESERVED_13_SHIFT)) & DDRPHY_PGCR0_RESERVED_13_MASK)
14011#define DDRPHY_PGCR0_DTOSEL_MASK (0x7C000U)
14012#define DDRPHY_PGCR0_DTOSEL_SHIFT (14U)
14013/*! DTOSEL - Digital Test Output Select
14014 */
14015#define DDRPHY_PGCR0_DTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_DTOSEL_SHIFT)) & DDRPHY_PGCR0_DTOSEL_MASK)
14016#define DDRPHY_PGCR0_RESERVED_23_19_MASK (0xF80000U)
14017#define DDRPHY_PGCR0_RESERVED_23_19_SHIFT (19U)
14018/*! RESERVED_23_19 - Reserved. Returns zeroes on reads.
14019 */
14020#define DDRPHY_PGCR0_RESERVED_23_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_RESERVED_23_19_SHIFT)) & DDRPHY_PGCR0_RESERVED_23_19_MASK)
14021#define DDRPHY_PGCR0_OSCACDL_MASK (0x3000000U)
14022#define DDRPHY_PGCR0_OSCACDL_SHIFT (24U)
14023/*! OSCACDL - Oscillator Mode Address/Command Delay Line Select
14024 */
14025#define DDRPHY_PGCR0_OSCACDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_OSCACDL_SHIFT)) & DDRPHY_PGCR0_OSCACDL_MASK)
14026#define DDRPHY_PGCR0_PHYFRST_MASK (0x4000000U)
14027#define DDRPHY_PGCR0_PHYFRST_SHIFT (26U)
14028/*! PHYFRST - PHY FIFO Reset
14029 */
14030#define DDRPHY_PGCR0_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_PHYFRST_SHIFT)) & DDRPHY_PGCR0_PHYFRST_MASK)
14031#define DDRPHY_PGCR0_RESERVED_30_27_MASK (0x78000000U)
14032#define DDRPHY_PGCR0_RESERVED_30_27_SHIFT (27U)
14033/*! RESERVED_30_27 - Reserved. Returns zeroes on reads.
14034 */
14035#define DDRPHY_PGCR0_RESERVED_30_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_RESERVED_30_27_SHIFT)) & DDRPHY_PGCR0_RESERVED_30_27_MASK)
14036#define DDRPHY_PGCR0_ADCP_MASK (0x80000000U)
14037#define DDRPHY_PGCR0_ADCP_SHIFT (31U)
14038/*! ADCP - Address Copy
14039 */
14040#define DDRPHY_PGCR0_ADCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR0_ADCP_SHIFT)) & DDRPHY_PGCR0_ADCP_MASK)
14041/*! @} */
14042
14043/*! @name PGCR1 - PHY General Configuration Register 1 */
14044/*! @{ */
14045#define DDRPHY_PGCR1_DTOMODE_MASK (0x1U)
14046#define DDRPHY_PGCR1_DTOMODE_SHIFT (0U)
14047/*! DTOMODE - Digital Test Output Mode
14048 */
14049#define DDRPHY_PGCR1_DTOMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_DTOMODE_SHIFT)) & DDRPHY_PGCR1_DTOMODE_MASK)
14050#define DDRPHY_PGCR1_WLMODE_MASK (0x2U)
14051#define DDRPHY_PGCR1_WLMODE_SHIFT (1U)
14052/*! WLMODE - Write Leveling (Software) Mode
14053 */
14054#define DDRPHY_PGCR1_WLMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_WLMODE_SHIFT)) & DDRPHY_PGCR1_WLMODE_MASK)
14055#define DDRPHY_PGCR1_WLSTEP_MASK (0x4U)
14056#define DDRPHY_PGCR1_WLSTEP_SHIFT (2U)
14057/*! WLSTEP - Write Leveling Step
14058 */
14059#define DDRPHY_PGCR1_WLSTEP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_WLSTEP_SHIFT)) & DDRPHY_PGCR1_WLSTEP_MASK)
14060#define DDRPHY_PGCR1_AC_CKOUT_DIFF_MASK (0x8U)
14061#define DDRPHY_PGCR1_AC_CKOUT_DIFF_SHIFT (3U)
14062/*! AC_CKOUT_DIFF - Selects PDIFF cell for CK generation
14063 */
14064#define DDRPHY_PGCR1_AC_CKOUT_DIFF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_AC_CKOUT_DIFF_SHIFT)) & DDRPHY_PGCR1_AC_CKOUT_DIFF_MASK)
14065#define DDRPHY_PGCR1_DX_DQSOUT_DIFF_MASK (0x10U)
14066#define DDRPHY_PGCR1_DX_DQSOUT_DIFF_SHIFT (4U)
14067/*! DX_DQSOUT_DIFF - Selects PDIFF cell for DQS generation
14068 */
14069#define DDRPHY_PGCR1_DX_DQSOUT_DIFF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_DX_DQSOUT_DIFF_SHIFT)) & DDRPHY_PGCR1_DX_DQSOUT_DIFF_MASK)
14070#define DDRPHY_PGCR1_CAST_MASK (0x20U)
14071#define DDRPHY_PGCR1_CAST_SHIFT (5U)
14072/*! CAST - CA Software Training.
14073 */
14074#define DDRPHY_PGCR1_CAST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_CAST_SHIFT)) & DDRPHY_PGCR1_CAST_MASK)
14075#define DDRPHY_PGCR1_PUBMODE_MASK (0x40U)
14076#define DDRPHY_PGCR1_PUBMODE_SHIFT (6U)
14077/*! PUBMODE - Enables, if set, the PUB to control the interface to the PHY and SDRAM.
14078 */
14079#define DDRPHY_PGCR1_PUBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_PUBMODE_SHIFT)) & DDRPHY_PGCR1_PUBMODE_MASK)
14080#define DDRPHY_PGCR1_RESERVED_8_7_MASK (0x180U)
14081#define DDRPHY_PGCR1_RESERVED_8_7_SHIFT (7U)
14082/*! RESERVED_8_7 - Reserved. Returns zeroes on reads.
14083 */
14084#define DDRPHY_PGCR1_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_RESERVED_8_7_SHIFT)) & DDRPHY_PGCR1_RESERVED_8_7_MASK)
14085#define DDRPHY_PGCR1_MDLEN_MASK (0x200U)
14086#define DDRPHY_PGCR1_MDLEN_SHIFT (9U)
14087/*! MDLEN - Master Delay Line Enable
14088 */
14089#define DDRPHY_PGCR1_MDLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_MDLEN_SHIFT)) & DDRPHY_PGCR1_MDLEN_MASK)
14090#define DDRPHY_PGCR1_LPFEN_MASK (0x400U)
14091#define DDRPHY_PGCR1_LPFEN_SHIFT (10U)
14092/*! LPFEN - Low-Pass Filter Enable
14093 */
14094#define DDRPHY_PGCR1_LPFEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_LPFEN_SHIFT)) & DDRPHY_PGCR1_LPFEN_MASK)
14095#define DDRPHY_PGCR1_LPFDEPTH_MASK (0x1800U)
14096#define DDRPHY_PGCR1_LPFDEPTH_SHIFT (11U)
14097/*! LPFDEPTH - Low-Pass Filter Depth
14098 */
14099#define DDRPHY_PGCR1_LPFDEPTH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_LPFDEPTH_SHIFT)) & DDRPHY_PGCR1_LPFDEPTH_MASK)
14100#define DDRPHY_PGCR1_FDEPTH_MASK (0x6000U)
14101#define DDRPHY_PGCR1_FDEPTH_SHIFT (13U)
14102/*! FDEPTH - Filter Depth
14103 */
14104#define DDRPHY_PGCR1_FDEPTH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_FDEPTH_SHIFT)) & DDRPHY_PGCR1_FDEPTH_MASK)
14105#define DDRPHY_PGCR1_DUALCHN_MASK (0x8000U)
14106#define DDRPHY_PGCR1_DUALCHN_SHIFT (15U)
14107/*! DUALCHN - Dual Channel Configuration
14108 */
14109#define DDRPHY_PGCR1_DUALCHN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_DUALCHN_SHIFT)) & DDRPHY_PGCR1_DUALCHN_MASK)
14110#define DDRPHY_PGCR1_ACPDDC_MASK (0x10000U)
14111#define DDRPHY_PGCR1_ACPDDC_SHIFT (16U)
14112/*! ACPDDC - AC Power-Down with Dual Channels
14113 */
14114#define DDRPHY_PGCR1_ACPDDC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_ACPDDC_SHIFT)) & DDRPHY_PGCR1_ACPDDC_MASK)
14115#define DDRPHY_PGCR1_DISDIC_MASK (0x20000U)
14116#define DDRPHY_PGCR1_DISDIC_SHIFT (17U)
14117/*! DISDIC - Enable/Disable control for dfi_init_complete.
14118 */
14119#define DDRPHY_PGCR1_DISDIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_DISDIC_SHIFT)) & DDRPHY_PGCR1_DISDIC_MASK)
14120#define DDRPHY_PGCR1_UPDMSTRC0_MASK (0x40000U)
14121#define DDRPHY_PGCR1_UPDMSTRC0_SHIFT (18U)
14122/*! UPDMSTRC0 - DFI Update Master Channel 0
14123 */
14124#define DDRPHY_PGCR1_UPDMSTRC0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_UPDMSTRC0_SHIFT)) & DDRPHY_PGCR1_UPDMSTRC0_MASK)
14125#define DDRPHY_PGCR1_RESERVED_19_MASK (0x80000U)
14126#define DDRPHY_PGCR1_RESERVED_19_SHIFT (19U)
14127/*! RESERVED_19 - Reserved. Returns zeroes on reads.
14128 */
14129#define DDRPHY_PGCR1_RESERVED_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_RESERVED_19_SHIFT)) & DDRPHY_PGCR1_RESERVED_19_MASK)
14130#define DDRPHY_PGCR1_LRDIMMST_MASK (0x100000U)
14131#define DDRPHY_PGCR1_LRDIMMST_SHIFT (20U)
14132/*! LRDIMMST - LRDIMM Software Training
14133 */
14134#define DDRPHY_PGCR1_LRDIMMST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_LRDIMMST_SHIFT)) & DDRPHY_PGCR1_LRDIMMST_MASK)
14135#define DDRPHY_PGCR1_ACVLDDLY_MASK (0xE00000U)
14136#define DDRPHY_PGCR1_ACVLDDLY_SHIFT (21U)
14137/*! ACVLDDLY - AC Loopback Valid Delay
14138 */
14139#define DDRPHY_PGCR1_ACVLDDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_ACVLDDLY_SHIFT)) & DDRPHY_PGCR1_ACVLDDLY_MASK)
14140#define DDRPHY_PGCR1_ACVLDTRN_MASK (0x1000000U)
14141#define DDRPHY_PGCR1_ACVLDTRN_SHIFT (24U)
14142/*! ACVLDTRN - AC Loopback Valid Train
14143 */
14144#define DDRPHY_PGCR1_ACVLDTRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_ACVLDTRN_SHIFT)) & DDRPHY_PGCR1_ACVLDTRN_MASK)
14145#define DDRPHY_PGCR1_PHYHRST_MASK (0x2000000U)
14146#define DDRPHY_PGCR1_PHYHRST_SHIFT (25U)
14147/*! PHYHRST - PHY High-Speed Reset
14148 */
14149#define DDRPHY_PGCR1_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_PHYHRST_SHIFT)) & DDRPHY_PGCR1_PHYHRST_MASK)
14150#define DDRPHY_PGCR1_DLTMODE_MASK (0x4000000U)
14151#define DDRPHY_PGCR1_DLTMODE_SHIFT (26U)
14152/*! DLTMODE - Delay Line Test Mode
14153 */
14154#define DDRPHY_PGCR1_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_DLTMODE_SHIFT)) & DDRPHY_PGCR1_DLTMODE_MASK)
14155#define DDRPHY_PGCR1_DLTST_MASK (0x8000000U)
14156#define DDRPHY_PGCR1_DLTST_SHIFT (27U)
14157/*! DLTST - Delay Line Test Start
14158 */
14159#define DDRPHY_PGCR1_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_DLTST_SHIFT)) & DDRPHY_PGCR1_DLTST_MASK)
14160#define DDRPHY_PGCR1_LBGSDQS_MASK (0x10000000U)
14161#define DDRPHY_PGCR1_LBGSDQS_SHIFT (28U)
14162/*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value (equivalent to one CK period)
14163 */
14164#define DDRPHY_PGCR1_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_LBGSDQS_SHIFT)) & DDRPHY_PGCR1_LBGSDQS_MASK)
14165#define DDRPHY_PGCR1_RESERVED_30_29_MASK (0x60000000U)
14166#define DDRPHY_PGCR1_RESERVED_30_29_SHIFT (29U)
14167/*! RESERVED_30_29 - Reserved. Returns zeroes on reads.
14168 */
14169#define DDRPHY_PGCR1_RESERVED_30_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_RESERVED_30_29_SHIFT)) & DDRPHY_PGCR1_RESERVED_30_29_MASK)
14170#define DDRPHY_PGCR1_LBMODE_MASK (0x80000000U)
14171#define DDRPHY_PGCR1_LBMODE_SHIFT (31U)
14172/*! LBMODE - Loopback Mode
14173 */
14174#define DDRPHY_PGCR1_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR1_LBMODE_SHIFT)) & DDRPHY_PGCR1_LBMODE_MASK)
14175/*! @} */
14176
14177/*! @name PGCR2 - PHY General Configuration Register 2 */
14178/*! @{ */
14179#define DDRPHY_PGCR2_tREFPRD_MASK (0x3FFFFU)
14180#define DDRPHY_PGCR2_tREFPRD_SHIFT (0U)
14181/*! tREFPRD - Refresh Period
14182 */
14183#define DDRPHY_PGCR2_tREFPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_tREFPRD_SHIFT)) & DDRPHY_PGCR2_tREFPRD_MASK)
14184#define DDRPHY_PGCR2_PLLFSMBYP_MASK (0x40000U)
14185#define DDRPHY_PGCR2_PLLFSMBYP_SHIFT (18U)
14186/*! PLLFSMBYP - PLL FSM Bypass
14187 */
14188#define DDRPHY_PGCR2_PLLFSMBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_PLLFSMBYP_SHIFT)) & DDRPHY_PGCR2_PLLFSMBYP_MASK)
14189#define DDRPHY_PGCR2_INITFSMBYP_MASK (0x80000U)
14190#define DDRPHY_PGCR2_INITFSMBYP_SHIFT (19U)
14191/*! INITFSMBYP - Initialization Bypass
14192 */
14193#define DDRPHY_PGCR2_INITFSMBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_INITFSMBYP_SHIFT)) & DDRPHY_PGCR2_INITFSMBYP_MASK)
14194#define DDRPHY_PGCR2_DTPMXTMR_MASK (0xFF00000U)
14195#define DDRPHY_PGCR2_DTPMXTMR_SHIFT (20U)
14196/*! DTPMXTMR - Data Training PUB Mode Exit Timer
14197 */
14198#define DDRPHY_PGCR2_DTPMXTMR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_DTPMXTMR_SHIFT)) & DDRPHY_PGCR2_DTPMXTMR_MASK)
14199#define DDRPHY_PGCR2_ICPC_MASK (0x10000000U)
14200#define DDRPHY_PGCR2_ICPC_SHIFT (28U)
14201/*! ICPC - Initialization Complete Pin Configuration
14202 */
14203#define DDRPHY_PGCR2_ICPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_ICPC_SHIFT)) & DDRPHY_PGCR2_ICPC_MASK)
14204#define DDRPHY_PGCR2_CLRPERR_MASK (0x20000000U)
14205#define DDRPHY_PGCR2_CLRPERR_SHIFT (29U)
14206/*! CLRPERR - Clear Parity Error
14207 */
14208#define DDRPHY_PGCR2_CLRPERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_CLRPERR_SHIFT)) & DDRPHY_PGCR2_CLRPERR_MASK)
14209#define DDRPHY_PGCR2_CLRZCAL_MASK (0x40000000U)
14210#define DDRPHY_PGCR2_CLRZCAL_SHIFT (30U)
14211/*! CLRZCAL - Clear Impedance Calibration
14212 */
14213#define DDRPHY_PGCR2_CLRZCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_CLRZCAL_SHIFT)) & DDRPHY_PGCR2_CLRZCAL_MASK)
14214#define DDRPHY_PGCR2_CLRTSTAT_MASK (0x80000000U)
14215#define DDRPHY_PGCR2_CLRTSTAT_SHIFT (31U)
14216/*! CLRTSTAT - Clear Training Status Registers
14217 */
14218#define DDRPHY_PGCR2_CLRTSTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR2_CLRTSTAT_SHIFT)) & DDRPHY_PGCR2_CLRTSTAT_MASK)
14219/*! @} */
14220
14221/*! @name PGCR3 - PHY General Configuration Register 3 */
14222/*! @{ */
14223#define DDRPHY_PGCR3_CLKLEVEL_MASK (0x3U)
14224#define DDRPHY_PGCR3_CLKLEVEL_SHIFT (0U)
14225/*! CLKLEVEL - Clock Level when Clock Gating
14226 */
14227#define DDRPHY_PGCR3_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_CLKLEVEL_SHIFT)) & DDRPHY_PGCR3_CLKLEVEL_MASK)
14228#define DDRPHY_PGCR3_DISRST_MASK (0x4U)
14229#define DDRPHY_PGCR3_DISRST_SHIFT (2U)
14230/*! DISRST - Read FIFO Reset Disable
14231 */
14232#define DDRPHY_PGCR3_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_DISRST_SHIFT)) & DDRPHY_PGCR3_DISRST_MASK)
14233#define DDRPHY_PGCR3_RDMODE_MASK (0x18U)
14234#define DDRPHY_PGCR3_RDMODE_SHIFT (3U)
14235/*! RDMODE - AC Receive FIFO Read Mode
14236 */
14237#define DDRPHY_PGCR3_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_RDMODE_SHIFT)) & DDRPHY_PGCR3_RDMODE_MASK)
14238#define DDRPHY_PGCR3_IOLB_MASK (0x20U)
14239#define DDRPHY_PGCR3_IOLB_SHIFT (5U)
14240/*! IOLB - IO Loop-Back Select
14241 */
14242#define DDRPHY_PGCR3_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_IOLB_SHIFT)) & DDRPHY_PGCR3_IOLB_MASK)
14243#define DDRPHY_PGCR3_DDLBYPMODE_MASK (0xC0U)
14244#define DDRPHY_PGCR3_DDLBYPMODE_SHIFT (6U)
14245/*! DDLBYPMODE - Controls DDL Bypass Modes
14246 */
14247#define DDRPHY_PGCR3_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_DDLBYPMODE_SHIFT)) & DDRPHY_PGCR3_DDLBYPMODE_MASK)
14248#define DDRPHY_PGCR3_RESERVED_8_MASK (0x100U)
14249#define DDRPHY_PGCR3_RESERVED_8_SHIFT (8U)
14250/*! RESERVED_8 - Reserved. Return zeroes on reads.
14251 */
14252#define DDRPHY_PGCR3_RESERVED_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_RESERVED_8_SHIFT)) & DDRPHY_PGCR3_RESERVED_8_MASK)
14253#define DDRPHY_PGCR3_GATEACCTLCLK_MASK (0x600U)
14254#define DDRPHY_PGCR3_GATEACCTLCLK_SHIFT (9U)
14255/*! GATEACCTLCLK - Enable Clock Gating for AC [0] ctl_clk
14256 */
14257#define DDRPHY_PGCR3_GATEACCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_GATEACCTLCLK_SHIFT)) & DDRPHY_PGCR3_GATEACCTLCLK_MASK)
14258#define DDRPHY_PGCR3_GATEACDDRCLK_MASK (0x1800U)
14259#define DDRPHY_PGCR3_GATEACDDRCLK_SHIFT (11U)
14260/*! GATEACDDRCLK - Enable Clock Gating for AC [0] ddr_clk
14261 */
14262#define DDRPHY_PGCR3_GATEACDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_GATEACDDRCLK_SHIFT)) & DDRPHY_PGCR3_GATEACDDRCLK_MASK)
14263#define DDRPHY_PGCR3_GATEACRDCLK_MASK (0x6000U)
14264#define DDRPHY_PGCR3_GATEACRDCLK_SHIFT (13U)
14265/*! GATEACRDCLK - Enable Clock Gating for AC [0] ctl_rd_clk
14266 */
14267#define DDRPHY_PGCR3_GATEACRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_GATEACRDCLK_SHIFT)) & DDRPHY_PGCR3_GATEACRDCLK_MASK)
14268#define DDRPHY_PGCR3_RESERVED_15_MASK (0x8000U)
14269#define DDRPHY_PGCR3_RESERVED_15_SHIFT (15U)
14270/*! RESERVED_15 - Reserved. Return zeroes on reads.
14271 */
14272#define DDRPHY_PGCR3_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_RESERVED_15_SHIFT)) & DDRPHY_PGCR3_RESERVED_15_MASK)
14273#define DDRPHY_PGCR3_CKEN_MASK (0xFF0000U)
14274#define DDRPHY_PGCR3_CKEN_SHIFT (16U)
14275/*! CKEN - CK Enable
14276 */
14277#define DDRPHY_PGCR3_CKEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_CKEN_SHIFT)) & DDRPHY_PGCR3_CKEN_MASK)
14278#define DDRPHY_PGCR3_CKNEN_MASK (0xFF000000U)
14279#define DDRPHY_PGCR3_CKNEN_SHIFT (24U)
14280/*! CKNEN - CKN Enable
14281 */
14282#define DDRPHY_PGCR3_CKNEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR3_CKNEN_SHIFT)) & DDRPHY_PGCR3_CKNEN_MASK)
14283/*! @} */
14284
14285/*! @name PGCR4 - PHY General Configuration Register 4 */
14286/*! @{ */
14287#define DDRPHY_PGCR4_LPIOPD_MASK (0x1U)
14288#define DDRPHY_PGCR4_LPIOPD_SHIFT (0U)
14289/*! LPIOPD - AC Low Power IO Power Down
14290 */
14291#define DDRPHY_PGCR4_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_LPIOPD_SHIFT)) & DDRPHY_PGCR4_LPIOPD_MASK)
14292#define DDRPHY_PGCR4_LPPLLPD_MASK (0x2U)
14293#define DDRPHY_PGCR4_LPPLLPD_SHIFT (1U)
14294/*! LPPLLPD - AC Low Power PLL Power Down
14295 */
14296#define DDRPHY_PGCR4_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_LPPLLPD_SHIFT)) & DDRPHY_PGCR4_LPPLLPD_MASK)
14297#define DDRPHY_PGCR4_RESERVED_3_2_MASK (0xCU)
14298#define DDRPHY_PGCR4_RESERVED_3_2_SHIFT (2U)
14299/*! RESERVED_3_2 - Reserved. Return zeroes on reads.
14300 */
14301#define DDRPHY_PGCR4_RESERVED_3_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_RESERVED_3_2_SHIFT)) & DDRPHY_PGCR4_RESERVED_3_2_MASK)
14302#define DDRPHY_PGCR4_LPWAKEUP_THRSH_MASK (0xF0U)
14303#define DDRPHY_PGCR4_LPWAKEUP_THRSH_SHIFT (4U)
14304/*! LPWAKEUP_THRSH - AC Low Power Wakeup Threshold
14305 */
14306#define DDRPHY_PGCR4_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_PGCR4_LPWAKEUP_THRSH_MASK)
14307#define DDRPHY_PGCR4_DCALSVAL_MASK (0x1FF00U)
14308#define DDRPHY_PGCR4_DCALSVAL_SHIFT (8U)
14309/*! DCALSVAL - DDL Calibration Starting Value
14310 */
14311#define DDRPHY_PGCR4_DCALSVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_DCALSVAL_SHIFT)) & DDRPHY_PGCR4_DCALSVAL_MASK)
14312#define DDRPHY_PGCR4_DCALTYPE_MASK (0x20000U)
14313#define DDRPHY_PGCR4_DCALTYPE_SHIFT (17U)
14314/*! DCALTYPE - DDL Calibration Type
14315 */
14316#define DDRPHY_PGCR4_DCALTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_DCALTYPE_SHIFT)) & DDRPHY_PGCR4_DCALTYPE_MASK)
14317#define DDRPHY_PGCR4_RESERVED_18_MASK (0x40000U)
14318#define DDRPHY_PGCR4_RESERVED_18_SHIFT (18U)
14319/*! RESERVED_18 - Reserved. Return zeroes on reads.
14320 */
14321#define DDRPHY_PGCR4_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_RESERVED_18_SHIFT)) & DDRPHY_PGCR4_RESERVED_18_MASK)
14322#define DDRPHY_PGCR4_WRRMODE_MASK (0x80000U)
14323#define DDRPHY_PGCR4_WRRMODE_SHIFT (19U)
14324/*! WRRMODE - AC Macro Write Path Rise-to-Rise Mode
14325 */
14326#define DDRPHY_PGCR4_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_WRRMODE_SHIFT)) & DDRPHY_PGCR4_WRRMODE_MASK)
14327#define DDRPHY_PGCR4_RRRMODE_MASK (0x100000U)
14328#define DDRPHY_PGCR4_RRRMODE_SHIFT (20U)
14329/*! RRRMODE - AC Macro Read Path Rise-to-Rise Mode
14330 */
14331#define DDRPHY_PGCR4_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_RRRMODE_SHIFT)) & DDRPHY_PGCR4_RRRMODE_MASK)
14332#define DDRPHY_PGCR4_PDRDDLBYP_MASK (0x200000U)
14333#define DDRPHY_PGCR4_PDRDDLBYP_SHIFT (21U)
14334/*! PDRDDLBYP - AC PDR DDL Bypass
14335 */
14336#define DDRPHY_PGCR4_PDRDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_PDRDDLBYP_SHIFT)) & DDRPHY_PGCR4_PDRDDLBYP_MASK)
14337#define DDRPHY_PGCR4_TEDDLBYP_MASK (0x400000U)
14338#define DDRPHY_PGCR4_TEDDLBYP_SHIFT (22U)
14339/*! TEDDLBYP - AC ODT DDL Bypass
14340 */
14341#define DDRPHY_PGCR4_TEDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_TEDDLBYP_SHIFT)) & DDRPHY_PGCR4_TEDDLBYP_MASK)
14342#define DDRPHY_PGCR4_OEDDLBYP_MASK (0x800000U)
14343#define DDRPHY_PGCR4_OEDDLBYP_SHIFT (23U)
14344/*! OEDDLBYP - AC OE DDL Bypass
14345 */
14346#define DDRPHY_PGCR4_OEDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_OEDDLBYP_SHIFT)) & DDRPHY_PGCR4_OEDDLBYP_MASK)
14347#define DDRPHY_PGCR4_ACDDLBYP_MASK (0x1F000000U)
14348#define DDRPHY_PGCR4_ACDDLBYP_SHIFT (24U)
14349/*! ACDDLBYP - AC DDL Bypass
14350 */
14351#define DDRPHY_PGCR4_ACDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_ACDDLBYP_SHIFT)) & DDRPHY_PGCR4_ACDDLBYP_MASK)
14352#define DDRPHY_PGCR4_ACDDLLD_MASK (0x20000000U)
14353#define DDRPHY_PGCR4_ACDDLLD_SHIFT (29U)
14354/*! ACDDLLD - AC DDL Delay Select Dymainc Load
14355 */
14356#define DDRPHY_PGCR4_ACDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_ACDDLLD_SHIFT)) & DDRPHY_PGCR4_ACDDLLD_MASK)
14357#define DDRPHY_PGCR4_RESERVED_31_30_MASK (0xC0000000U)
14358#define DDRPHY_PGCR4_RESERVED_31_30_SHIFT (30U)
14359/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
14360 */
14361#define DDRPHY_PGCR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR4_RESERVED_31_30_SHIFT)) & DDRPHY_PGCR4_RESERVED_31_30_MASK)
14362/*! @} */
14363
14364/*! @name PGCR5 - PHY General Configuration Register 5 */
14365/*! @{ */
14366#define DDRPHY_PGCR5_DDLPGRW_MASK (0x1U)
14367#define DDRPHY_PGCR5_DDLPGRW_SHIFT (0U)
14368/*! DDLPGRW - DDL Page Read Write select
14369 */
14370#define DDRPHY_PGCR5_DDLPGRW(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_DDLPGRW_SHIFT)) & DDRPHY_PGCR5_DDLPGRW_MASK)
14371#define DDRPHY_PGCR5_DDLPGACT_MASK (0x2U)
14372#define DDRPHY_PGCR5_DDLPGACT_SHIFT (1U)
14373/*! DDLPGACT - DDL Page Read Write select
14374 */
14375#define DDRPHY_PGCR5_DDLPGACT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_DDLPGACT_SHIFT)) & DDRPHY_PGCR5_DDLPGACT_MASK)
14376#define DDRPHY_PGCR5_DXREFISELRANGE_MASK (0x4U)
14377#define DDRPHY_PGCR5_DXREFISELRANGE_SHIFT (2U)
14378/*! DXREFISELRANGE - Internal VREF generator REFSEL ragne select
14379 */
14380#define DDRPHY_PGCR5_DXREFISELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_DXREFISELRANGE_SHIFT)) & DDRPHY_PGCR5_DXREFISELRANGE_MASK)
14381#define DDRPHY_PGCR5_RESERVED_3_MASK (0x8U)
14382#define DDRPHY_PGCR5_RESERVED_3_SHIFT (3U)
14383/*! RESERVED_3 - Reserved. Return zeroes on reads.
14384 */
14385#define DDRPHY_PGCR5_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_RESERVED_3_SHIFT)) & DDRPHY_PGCR5_RESERVED_3_MASK)
14386#define DDRPHY_PGCR5_VREF_RBCTRL_MASK (0xF0U)
14387#define DDRPHY_PGCR5_VREF_RBCTRL_SHIFT (4U)
14388/*! VREF_RBCTRL - Receiver bias core side control
14389 */
14390#define DDRPHY_PGCR5_VREF_RBCTRL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_VREF_RBCTRL_SHIFT)) & DDRPHY_PGCR5_VREF_RBCTRL_MASK)
14391#define DDRPHY_PGCR5_DISCNPERIOD_MASK (0xFF00U)
14392#define DDRPHY_PGCR5_DISCNPERIOD_SHIFT (8U)
14393/*! DISCNPERIOD - DFI Disconnect Time Period
14394 */
14395#define DDRPHY_PGCR5_DISCNPERIOD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_DISCNPERIOD_SHIFT)) & DDRPHY_PGCR5_DISCNPERIOD_MASK)
14396#define DDRPHY_PGCR5_FRQAT_MASK (0xFF0000U)
14397#define DDRPHY_PGCR5_FRQAT_SHIFT (16U)
14398/*! FRQAT - Frequency A Ratio Term
14399 */
14400#define DDRPHY_PGCR5_FRQAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_FRQAT_SHIFT)) & DDRPHY_PGCR5_FRQAT_MASK)
14401#define DDRPHY_PGCR5_FRQBT_MASK (0xFF000000U)
14402#define DDRPHY_PGCR5_FRQBT_SHIFT (24U)
14403/*! FRQBT - Frequency B Ratio Term
14404 */
14405#define DDRPHY_PGCR5_FRQBT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR5_FRQBT_SHIFT)) & DDRPHY_PGCR5_FRQBT_MASK)
14406/*! @} */
14407
14408/*! @name PGCR6 - PHY General Configuration Register 6 */
14409/*! @{ */
14410#define DDRPHY_PGCR6_INHVT_MASK (0x1U)
14411#define DDRPHY_PGCR6_INHVT_SHIFT (0U)
14412/*! INHVT - VT Calculation Inhibit
14413 */
14414#define DDRPHY_PGCR6_INHVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_INHVT_SHIFT)) & DDRPHY_PGCR6_INHVT_MASK)
14415#define DDRPHY_PGCR6_FVT_MASK (0x2U)
14416#define DDRPHY_PGCR6_FVT_SHIFT (1U)
14417/*! FVT - Forced VT Compensation Trigger
14418 */
14419#define DDRPHY_PGCR6_FVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_FVT_SHIFT)) & DDRPHY_PGCR6_FVT_MASK)
14420#define DDRPHY_PGCR6_RESERVED_7_2_MASK (0xFCU)
14421#define DDRPHY_PGCR6_RESERVED_7_2_SHIFT (2U)
14422/*! RESERVED_7_2 - Reserved. Returns zeroes on reads.
14423 */
14424#define DDRPHY_PGCR6_RESERVED_7_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_RESERVED_7_2_SHIFT)) & DDRPHY_PGCR6_RESERVED_7_2_MASK)
14425#define DDRPHY_PGCR6_CKBVT_MASK (0x100U)
14426#define DDRPHY_PGCR6_CKBVT_SHIFT (8U)
14427/*! CKBVT - CK Bit Delay VT Compensation
14428 */
14429#define DDRPHY_PGCR6_CKBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_CKBVT_SHIFT)) & DDRPHY_PGCR6_CKBVT_MASK)
14430#define DDRPHY_PGCR6_CSNBVT_MASK (0x200U)
14431#define DDRPHY_PGCR6_CSNBVT_SHIFT (9U)
14432/*! CSNBVT - CSN Bit Delay VT Compensation
14433 */
14434#define DDRPHY_PGCR6_CSNBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_CSNBVT_SHIFT)) & DDRPHY_PGCR6_CSNBVT_MASK)
14435#define DDRPHY_PGCR6_CKEBVT_MASK (0x400U)
14436#define DDRPHY_PGCR6_CKEBVT_SHIFT (10U)
14437/*! CKEBVT - CKE Bit Delay VT Compensation
14438 */
14439#define DDRPHY_PGCR6_CKEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_CKEBVT_SHIFT)) & DDRPHY_PGCR6_CKEBVT_MASK)
14440#define DDRPHY_PGCR6_ODTBVT_MASK (0x800U)
14441#define DDRPHY_PGCR6_ODTBVT_SHIFT (11U)
14442/*! ODTBVT - ODT Bit Delay VT Compensation
14443 */
14444#define DDRPHY_PGCR6_ODTBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_ODTBVT_SHIFT)) & DDRPHY_PGCR6_ODTBVT_MASK)
14445#define DDRPHY_PGCR6_ACBVT_MASK (0x1000U)
14446#define DDRPHY_PGCR6_ACBVT_SHIFT (12U)
14447/*! ACBVT - Address/Command Bit Delay VT Compensation
14448 */
14449#define DDRPHY_PGCR6_ACBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_ACBVT_SHIFT)) & DDRPHY_PGCR6_ACBVT_MASK)
14450#define DDRPHY_PGCR6_ACDLVT_MASK (0x2000U)
14451#define DDRPHY_PGCR6_ACDLVT_SHIFT (13U)
14452/*! ACDLVT - AC Address/Command Delay LCDL VT Compensation
14453 */
14454#define DDRPHY_PGCR6_ACDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_ACDLVT_SHIFT)) & DDRPHY_PGCR6_ACDLVT_MASK)
14455#define DDRPHY_PGCR6_RESERVED_15_14_MASK (0xC000U)
14456#define DDRPHY_PGCR6_RESERVED_15_14_SHIFT (14U)
14457/*! RESERVED_15_14 - Reserved. Returns zeroes on reads.
14458 */
14459#define DDRPHY_PGCR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_RESERVED_15_14_SHIFT)) & DDRPHY_PGCR6_RESERVED_15_14_MASK)
14460#define DDRPHY_PGCR6_DLDLMT_MASK (0xFF0000U)
14461#define DDRPHY_PGCR6_DLDLMT_SHIFT (16U)
14462/*! DLDLMT - Delay Line VT Drift Limit
14463 */
14464#define DDRPHY_PGCR6_DLDLMT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_DLDLMT_SHIFT)) & DDRPHY_PGCR6_DLDLMT_MASK)
14465#define DDRPHY_PGCR6_RESERVED_31_24_MASK (0xFF000000U)
14466#define DDRPHY_PGCR6_RESERVED_31_24_SHIFT (24U)
14467/*! RESERVED_31_24 - Reserved. Returns zeroes on reads.
14468 */
14469#define DDRPHY_PGCR6_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR6_RESERVED_31_24_SHIFT)) & DDRPHY_PGCR6_RESERVED_31_24_MASK)
14470/*! @} */
14471
14472/*! @name PGCR7 - PHY General Configuration Register 7 */
14473/*! @{ */
14474#define DDRPHY_PGCR7_ACTMODE_MASK (0x1U)
14475#define DDRPHY_PGCR7_ACTMODE_SHIFT (0U)
14476/*! ACTMODE - AC Test Mode
14477 */
14478#define DDRPHY_PGCR7_ACTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACTMODE_SHIFT)) & DDRPHY_PGCR7_ACTMODE_MASK)
14479#define DDRPHY_PGCR7_ACDTOSEL_MASK (0x2U)
14480#define DDRPHY_PGCR7_ACDTOSEL_SHIFT (1U)
14481/*! ACDTOSEL - AC Digital Test Output Select
14482 */
14483#define DDRPHY_PGCR7_ACDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACDTOSEL_SHIFT)) & DDRPHY_PGCR7_ACDTOSEL_MASK)
14484#define DDRPHY_PGCR7_ACRSVD_2_MASK (0x4U)
14485#define DDRPHY_PGCR7_ACRSVD_2_SHIFT (2U)
14486/*! ACRSVD_2 - This bit is reserved for future AC special PHY modes but the register is already
14487 * connected to existing (unused) AC phy_mode bits.
14488 */
14489#define DDRPHY_PGCR7_ACRSVD_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACRSVD_2_SHIFT)) & DDRPHY_PGCR7_ACRSVD_2_MASK)
14490#define DDRPHY_PGCR7_ACDLDT_MASK (0x8U)
14491#define DDRPHY_PGCR7_ACDLDT_SHIFT (3U)
14492/*! ACDLDT - AC DDL Load Type
14493 */
14494#define DDRPHY_PGCR7_ACDLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACDLDT_SHIFT)) & DDRPHY_PGCR7_ACDLDT_MASK)
14495#define DDRPHY_PGCR7_ACRCLKMD_MASK (0x10U)
14496#define DDRPHY_PGCR7_ACRCLKMD_SHIFT (4U)
14497/*! ACRCLKMD - AC Read Clock Mode
14498 */
14499#define DDRPHY_PGCR7_ACRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACRCLKMD_SHIFT)) & DDRPHY_PGCR7_ACRCLKMD_MASK)
14500#define DDRPHY_PGCR7_ACCALCLK_MASK (0x20U)
14501#define DDRPHY_PGCR7_ACCALCLK_SHIFT (5U)
14502/*! ACCALCLK - AC Calibration Clock Select
14503 */
14504#define DDRPHY_PGCR7_ACCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACCALCLK_SHIFT)) & DDRPHY_PGCR7_ACCALCLK_MASK)
14505#define DDRPHY_PGCR7_ACRSVD_7_6_MASK (0xC0U)
14506#define DDRPHY_PGCR7_ACRSVD_7_6_SHIFT (6U)
14507/*! ACRSVD_7_6 - These bits are reserved for future AC special PHY modes but the registers are
14508 * already connected to existing (unused) AC phy_mode bits.
14509 */
14510#define DDRPHY_PGCR7_ACRSVD_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_ACRSVD_7_6_SHIFT)) & DDRPHY_PGCR7_ACRSVD_7_6_MASK)
14511#define DDRPHY_PGCR7_RESERVED_31_8_MASK (0xFFFFFF00U)
14512#define DDRPHY_PGCR7_RESERVED_31_8_SHIFT (8U)
14513/*! RESERVED_31_8 - Reserved. Returns zeroes on reads.
14514 */
14515#define DDRPHY_PGCR7_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR7_RESERVED_31_8_SHIFT)) & DDRPHY_PGCR7_RESERVED_31_8_MASK)
14516/*! @} */
14517
14518/*! @name PGSR0 - PHY General Status Register 0 */
14519/*! @{ */
14520#define DDRPHY_PGSR0_IDONE_MASK (0x1U)
14521#define DDRPHY_PGSR0_IDONE_SHIFT (0U)
14522/*! IDONE - Initialization Done
14523 */
14524#define DDRPHY_PGSR0_IDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_IDONE_SHIFT)) & DDRPHY_PGSR0_IDONE_MASK)
14525#define DDRPHY_PGSR0_PLDONE_MASK (0x2U)
14526#define DDRPHY_PGSR0_PLDONE_SHIFT (1U)
14527/*! PLDONE - PLL Lock Done
14528 */
14529#define DDRPHY_PGSR0_PLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_PLDONE_SHIFT)) & DDRPHY_PGSR0_PLDONE_MASK)
14530#define DDRPHY_PGSR0_DCDONE_MASK (0x4U)
14531#define DDRPHY_PGSR0_DCDONE_SHIFT (2U)
14532/*! DCDONE - Digital Delay Line (DDL) Calibration Done
14533 */
14534#define DDRPHY_PGSR0_DCDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_DCDONE_SHIFT)) & DDRPHY_PGSR0_DCDONE_MASK)
14535#define DDRPHY_PGSR0_ZCDONE_MASK (0x8U)
14536#define DDRPHY_PGSR0_ZCDONE_SHIFT (3U)
14537/*! ZCDONE - Impedance Calibration Done
14538 */
14539#define DDRPHY_PGSR0_ZCDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_ZCDONE_SHIFT)) & DDRPHY_PGSR0_ZCDONE_MASK)
14540#define DDRPHY_PGSR0_DIDONE_MASK (0x10U)
14541#define DDRPHY_PGSR0_DIDONE_SHIFT (4U)
14542/*! DIDONE - DRAM Initialization Done
14543 */
14544#define DDRPHY_PGSR0_DIDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_DIDONE_SHIFT)) & DDRPHY_PGSR0_DIDONE_MASK)
14545#define DDRPHY_PGSR0_WLDONE_MASK (0x20U)
14546#define DDRPHY_PGSR0_WLDONE_SHIFT (5U)
14547/*! WLDONE - Write Leveling Done
14548 */
14549#define DDRPHY_PGSR0_WLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WLDONE_SHIFT)) & DDRPHY_PGSR0_WLDONE_MASK)
14550#define DDRPHY_PGSR0_QSGDONE_MASK (0x40U)
14551#define DDRPHY_PGSR0_QSGDONE_SHIFT (6U)
14552/*! QSGDONE - DQS Gate Training Done
14553 */
14554#define DDRPHY_PGSR0_QSGDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_QSGDONE_SHIFT)) & DDRPHY_PGSR0_QSGDONE_MASK)
14555#define DDRPHY_PGSR0_WLADONE_MASK (0x80U)
14556#define DDRPHY_PGSR0_WLADONE_SHIFT (7U)
14557/*! WLADONE - Write Leveling Adjustment Done
14558 */
14559#define DDRPHY_PGSR0_WLADONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WLADONE_SHIFT)) & DDRPHY_PGSR0_WLADONE_MASK)
14560#define DDRPHY_PGSR0_RDDONE_MASK (0x100U)
14561#define DDRPHY_PGSR0_RDDONE_SHIFT (8U)
14562/*! RDDONE - Read Bit Deskew Done
14563 */
14564#define DDRPHY_PGSR0_RDDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_RDDONE_SHIFT)) & DDRPHY_PGSR0_RDDONE_MASK)
14565#define DDRPHY_PGSR0_WDDONE_MASK (0x200U)
14566#define DDRPHY_PGSR0_WDDONE_SHIFT (9U)
14567/*! WDDONE - Write Bit Deskew Done
14568 */
14569#define DDRPHY_PGSR0_WDDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WDDONE_SHIFT)) & DDRPHY_PGSR0_WDDONE_MASK)
14570#define DDRPHY_PGSR0_REDONE_MASK (0x400U)
14571#define DDRPHY_PGSR0_REDONE_SHIFT (10U)
14572/*! REDONE - Read Eye Training Done
14573 */
14574#define DDRPHY_PGSR0_REDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_REDONE_SHIFT)) & DDRPHY_PGSR0_REDONE_MASK)
14575#define DDRPHY_PGSR0_WEDONE_MASK (0x800U)
14576#define DDRPHY_PGSR0_WEDONE_SHIFT (11U)
14577/*! WEDONE - Write Eye Training Done
14578 */
14579#define DDRPHY_PGSR0_WEDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WEDONE_SHIFT)) & DDRPHY_PGSR0_WEDONE_MASK)
14580#define DDRPHY_PGSR0_CADONE_MASK (0x1000U)
14581#define DDRPHY_PGSR0_CADONE_SHIFT (12U)
14582/*! CADONE - CA Training Done
14583 */
14584#define DDRPHY_PGSR0_CADONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_CADONE_SHIFT)) & DDRPHY_PGSR0_CADONE_MASK)
14585#define DDRPHY_PGSR0_SRDDONE_MASK (0x2000U)
14586#define DDRPHY_PGSR0_SRDDONE_SHIFT (13U)
14587/*! SRDDONE - Static Read Done
14588 */
14589#define DDRPHY_PGSR0_SRDDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_SRDDONE_SHIFT)) & DDRPHY_PGSR0_SRDDONE_MASK)
14590#define DDRPHY_PGSR0_VDONE_MASK (0x4000U)
14591#define DDRPHY_PGSR0_VDONE_SHIFT (14U)
14592/*! VDONE - VREF Training Done
14593 */
14594#define DDRPHY_PGSR0_VDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_VDONE_SHIFT)) & DDRPHY_PGSR0_VDONE_MASK)
14595#define DDRPHY_PGSR0_DQS2DQDONE_MASK (0x8000U)
14596#define DDRPHY_PGSR0_DQS2DQDONE_SHIFT (15U)
14597/*! DQS2DQDONE - Write DQS2DQ Training Done
14598 */
14599#define DDRPHY_PGSR0_DQS2DQDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_DQS2DQDONE_SHIFT)) & DDRPHY_PGSR0_DQS2DQDONE_MASK)
14600#define DDRPHY_PGSR0_RESERVED_17_16_MASK (0x30000U)
14601#define DDRPHY_PGSR0_RESERVED_17_16_SHIFT (16U)
14602/*! RESERVED_17_16 - Reserved. Returns zeroes on reads.
14603 */
14604#define DDRPHY_PGSR0_RESERVED_17_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_RESERVED_17_16_SHIFT)) & DDRPHY_PGSR0_RESERVED_17_16_MASK)
14605#define DDRPHY_PGSR0_DQS2DQERR_MASK (0x40000U)
14606#define DDRPHY_PGSR0_DQS2DQERR_SHIFT (18U)
14607/*! DQS2DQERR - Write DQS2DQ Training Error
14608 */
14609#define DDRPHY_PGSR0_DQS2DQERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_DQS2DQERR_SHIFT)) & DDRPHY_PGSR0_DQS2DQERR_MASK)
14610#define DDRPHY_PGSR0_VERR_MASK (0x80000U)
14611#define DDRPHY_PGSR0_VERR_SHIFT (19U)
14612/*! VERR - VREF Training Error
14613 */
14614#define DDRPHY_PGSR0_VERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_VERR_SHIFT)) & DDRPHY_PGSR0_VERR_MASK)
14615#define DDRPHY_PGSR0_ZCERR_MASK (0x100000U)
14616#define DDRPHY_PGSR0_ZCERR_SHIFT (20U)
14617/*! ZCERR - Impedance Calibration Error
14618 */
14619#define DDRPHY_PGSR0_ZCERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_ZCERR_SHIFT)) & DDRPHY_PGSR0_ZCERR_MASK)
14620#define DDRPHY_PGSR0_WLERR_MASK (0x200000U)
14621#define DDRPHY_PGSR0_WLERR_SHIFT (21U)
14622/*! WLERR - Write Leveling Error
14623 */
14624#define DDRPHY_PGSR0_WLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WLERR_SHIFT)) & DDRPHY_PGSR0_WLERR_MASK)
14625#define DDRPHY_PGSR0_QSGERR_MASK (0x400000U)
14626#define DDRPHY_PGSR0_QSGERR_SHIFT (22U)
14627/*! QSGERR - DQS Gate Training Error
14628 */
14629#define DDRPHY_PGSR0_QSGERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_QSGERR_SHIFT)) & DDRPHY_PGSR0_QSGERR_MASK)
14630#define DDRPHY_PGSR0_WLAERR_MASK (0x800000U)
14631#define DDRPHY_PGSR0_WLAERR_SHIFT (23U)
14632/*! WLAERR - Write Leveling Adjustment Error
14633 */
14634#define DDRPHY_PGSR0_WLAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WLAERR_SHIFT)) & DDRPHY_PGSR0_WLAERR_MASK)
14635#define DDRPHY_PGSR0_RDERR_MASK (0x1000000U)
14636#define DDRPHY_PGSR0_RDERR_SHIFT (24U)
14637/*! RDERR - Read Bit Deskew Error
14638 */
14639#define DDRPHY_PGSR0_RDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_RDERR_SHIFT)) & DDRPHY_PGSR0_RDERR_MASK)
14640#define DDRPHY_PGSR0_WDERR_MASK (0x2000000U)
14641#define DDRPHY_PGSR0_WDERR_SHIFT (25U)
14642/*! WDERR - Write Bit Deskew Error
14643 */
14644#define DDRPHY_PGSR0_WDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WDERR_SHIFT)) & DDRPHY_PGSR0_WDERR_MASK)
14645#define DDRPHY_PGSR0_REERR_MASK (0x4000000U)
14646#define DDRPHY_PGSR0_REERR_SHIFT (26U)
14647/*! REERR - Read Eye Training Error
14648 */
14649#define DDRPHY_PGSR0_REERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_REERR_SHIFT)) & DDRPHY_PGSR0_REERR_MASK)
14650#define DDRPHY_PGSR0_WEERR_MASK (0x8000000U)
14651#define DDRPHY_PGSR0_WEERR_SHIFT (27U)
14652/*! WEERR - Write Eye Training Error
14653 */
14654#define DDRPHY_PGSR0_WEERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_WEERR_SHIFT)) & DDRPHY_PGSR0_WEERR_MASK)
14655#define DDRPHY_PGSR0_CAERR_MASK (0x10000000U)
14656#define DDRPHY_PGSR0_CAERR_SHIFT (28U)
14657/*! CAERR - CA Training Error
14658 */
14659#define DDRPHY_PGSR0_CAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_CAERR_SHIFT)) & DDRPHY_PGSR0_CAERR_MASK)
14660#define DDRPHY_PGSR0_CAWRN_MASK (0x20000000U)
14661#define DDRPHY_PGSR0_CAWRN_SHIFT (29U)
14662/*! CAWRN - CA Training Warning
14663 */
14664#define DDRPHY_PGSR0_CAWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_CAWRN_SHIFT)) & DDRPHY_PGSR0_CAWRN_MASK)
14665#define DDRPHY_PGSR0_SRDERR_MASK (0x40000000U)
14666#define DDRPHY_PGSR0_SRDERR_SHIFT (30U)
14667/*! SRDERR - Static Read Error
14668 */
14669#define DDRPHY_PGSR0_SRDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_SRDERR_SHIFT)) & DDRPHY_PGSR0_SRDERR_MASK)
14670#define DDRPHY_PGSR0_APLOCK_MASK (0x80000000U)
14671#define DDRPHY_PGSR0_APLOCK_SHIFT (31U)
14672/*! APLOCK - AC PLL Lock
14673 */
14674#define DDRPHY_PGSR0_APLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR0_APLOCK_SHIFT)) & DDRPHY_PGSR0_APLOCK_MASK)
14675/*! @} */
14676
14677/*! @name PGSR1 - PHY General Status Register 1 */
14678/*! @{ */
14679#define DDRPHY_PGSR1_DLTDONE_MASK (0x1U)
14680#define DDRPHY_PGSR1_DLTDONE_SHIFT (0U)
14681/*! DLTDONE - Delay Line Test Done for AC macro 0
14682 */
14683#define DDRPHY_PGSR1_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR1_DLTDONE_SHIFT)) & DDRPHY_PGSR1_DLTDONE_MASK)
14684#define DDRPHY_PGSR1_DLTCODE_MASK (0x1FFFFFEU)
14685#define DDRPHY_PGSR1_DLTCODE_SHIFT (1U)
14686/*! DLTCODE - Delay Line Test Code for AC macro 0
14687 */
14688#define DDRPHY_PGSR1_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR1_DLTCODE_SHIFT)) & DDRPHY_PGSR1_DLTCODE_MASK)
14689#define DDRPHY_PGSR1_RESERVED_29_25_MASK (0x3E000000U)
14690#define DDRPHY_PGSR1_RESERVED_29_25_SHIFT (25U)
14691/*! RESERVED_29_25 - Reserved. Returns zeroes on reads.
14692 */
14693#define DDRPHY_PGSR1_RESERVED_29_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR1_RESERVED_29_25_SHIFT)) & DDRPHY_PGSR1_RESERVED_29_25_MASK)
14694#define DDRPHY_PGSR1_VTSTOP_MASK (0x40000000U)
14695#define DDRPHY_PGSR1_VTSTOP_SHIFT (30U)
14696/*! VTSTOP - VT Stop
14697 */
14698#define DDRPHY_PGSR1_VTSTOP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR1_VTSTOP_SHIFT)) & DDRPHY_PGSR1_VTSTOP_MASK)
14699#define DDRPHY_PGSR1_PARERR_MASK (0x80000000U)
14700#define DDRPHY_PGSR1_PARERR_SHIFT (31U)
14701/*! PARERR - RDIMM Parity Error
14702 */
14703#define DDRPHY_PGSR1_PARERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR1_PARERR_SHIFT)) & DDRPHY_PGSR1_PARERR_MASK)
14704/*! @} */
14705
14706/*! @name PGSR2 - PHY General Status Register 2 */
14707/*! @{ */
14708#define DDRPHY_PGSR2_DLTDONE_MASK (0x1U)
14709#define DDRPHY_PGSR2_DLTDONE_SHIFT (0U)
14710/*! DLTDONE - Delay Line Test Done for AC macro 1
14711 */
14712#define DDRPHY_PGSR2_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR2_DLTDONE_SHIFT)) & DDRPHY_PGSR2_DLTDONE_MASK)
14713#define DDRPHY_PGSR2_DLTCODE_MASK (0x1FFFFFEU)
14714#define DDRPHY_PGSR2_DLTCODE_SHIFT (1U)
14715/*! DLTCODE - Delay Line Test Code for AC macro 1
14716 */
14717#define DDRPHY_PGSR2_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR2_DLTCODE_SHIFT)) & DDRPHY_PGSR2_DLTCODE_MASK)
14718#define DDRPHY_PGSR2_RESERVED_31_25_MASK (0xFE000000U)
14719#define DDRPHY_PGSR2_RESERVED_31_25_SHIFT (25U)
14720/*! RESERVED_31_25 - Reserved. Returns zeroes on reads.
14721 */
14722#define DDRPHY_PGSR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGSR2_RESERVED_31_25_SHIFT)) & DDRPHY_PGSR2_RESERVED_31_25_MASK)
14723/*! @} */
14724
14725/*! @name PTR0 - PHY Timing Register 0 */
14726/*! @{ */
14727#define DDRPHY_PTR0_tPHYRST_MASK (0x3FU)
14728#define DDRPHY_PTR0_tPHYRST_SHIFT (0U)
14729/*! tPHYRST - PHY Reset Time
14730 */
14731#define DDRPHY_PTR0_tPHYRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR0_tPHYRST_SHIFT)) & DDRPHY_PTR0_tPHYRST_MASK)
14732#define DDRPHY_PTR0_tPLLGS_MASK (0x1FFFC0U)
14733#define DDRPHY_PTR0_tPLLGS_SHIFT (6U)
14734/*! tPLLGS - PLL Gear Shift Time
14735 */
14736#define DDRPHY_PTR0_tPLLGS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR0_tPLLGS_SHIFT)) & DDRPHY_PTR0_tPLLGS_MASK)
14737#define DDRPHY_PTR0_tPLLPD_MASK (0xFFE00000U)
14738#define DDRPHY_PTR0_tPLLPD_SHIFT (21U)
14739/*! tPLLPD - PLL Power-Down Time
14740 */
14741#define DDRPHY_PTR0_tPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR0_tPLLPD_SHIFT)) & DDRPHY_PTR0_tPLLPD_MASK)
14742/*! @} */
14743
14744/*! @name PTR1 - PHY Timing Register 1 */
14745/*! @{ */
14746#define DDRPHY_PTR1_tPLLRST_MASK (0x1FFFU)
14747#define DDRPHY_PTR1_tPLLRST_SHIFT (0U)
14748/*! tPLLRST - PLL Reset Time
14749 */
14750#define DDRPHY_PTR1_tPLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR1_tPLLRST_SHIFT)) & DDRPHY_PTR1_tPLLRST_MASK)
14751#define DDRPHY_PTR1_RESERVED_15_13_MASK (0xE000U)
14752#define DDRPHY_PTR1_RESERVED_15_13_SHIFT (13U)
14753/*! RESERVED_15_13 - Reserved. Returns zeroes on reads.
14754 */
14755#define DDRPHY_PTR1_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR1_RESERVED_15_13_SHIFT)) & DDRPHY_PTR1_RESERVED_15_13_MASK)
14756#define DDRPHY_PTR1_tPLLLOCK_MASK (0xFFFF0000U)
14757#define DDRPHY_PTR1_tPLLLOCK_SHIFT (16U)
14758/*! tPLLLOCK - PLL Lock Time
14759 */
14760#define DDRPHY_PTR1_tPLLLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR1_tPLLLOCK_SHIFT)) & DDRPHY_PTR1_tPLLLOCK_MASK)
14761/*! @} */
14762
14763/*! @name PTR2 - PHY Timing Register 2 */
14764/*! @{ */
14765#define DDRPHY_PTR2_tCALON_MASK (0x1FU)
14766#define DDRPHY_PTR2_tCALON_SHIFT (0U)
14767/*! tCALON - Calibration On Time
14768 */
14769#define DDRPHY_PTR2_tCALON(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR2_tCALON_SHIFT)) & DDRPHY_PTR2_tCALON_MASK)
14770#define DDRPHY_PTR2_tCALS_MASK (0x3E0U)
14771#define DDRPHY_PTR2_tCALS_SHIFT (5U)
14772/*! tCALS - Calibration Setup Time
14773 */
14774#define DDRPHY_PTR2_tCALS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR2_tCALS_SHIFT)) & DDRPHY_PTR2_tCALS_MASK)
14775#define DDRPHY_PTR2_tCALH_MASK (0x7C00U)
14776#define DDRPHY_PTR2_tCALH_SHIFT (10U)
14777/*! tCALH - Calibration Hold Time
14778 */
14779#define DDRPHY_PTR2_tCALH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR2_tCALH_SHIFT)) & DDRPHY_PTR2_tCALH_MASK)
14780#define DDRPHY_PTR2_tWLDLYS_MASK (0xF8000U)
14781#define DDRPHY_PTR2_tWLDLYS_SHIFT (15U)
14782/*! tWLDLYS - Write Leveling Delay Settling Time
14783 */
14784#define DDRPHY_PTR2_tWLDLYS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR2_tWLDLYS_SHIFT)) & DDRPHY_PTR2_tWLDLYS_MASK)
14785#define DDRPHY_PTR2_RESERVED_31_20_MASK (0xFFF00000U)
14786#define DDRPHY_PTR2_RESERVED_31_20_SHIFT (20U)
14787/*! RESERVED_31_20 - Reserved. Return zeroes on reads.
14788 */
14789#define DDRPHY_PTR2_RESERVED_31_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR2_RESERVED_31_20_SHIFT)) & DDRPHY_PTR2_RESERVED_31_20_MASK)
14790/*! @} */
14791
14792/*! @name PTR3 - PHY Timing Register 3 */
14793/*! @{ */
14794#define DDRPHY_PTR3_tDINIT0_MASK (0x7FFFFFU)
14795#define DDRPHY_PTR3_tDINIT0_SHIFT (0U)
14796/*! tDINIT0 - DRAM Initialization Time 0
14797 */
14798#define DDRPHY_PTR3_tDINIT0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR3_tDINIT0_SHIFT)) & DDRPHY_PTR3_tDINIT0_MASK)
14799#define DDRPHY_PTR3_RESERVED_31_23_MASK (0xFF800000U)
14800#define DDRPHY_PTR3_RESERVED_31_23_SHIFT (23U)
14801/*! RESERVED_31_23 - Reserved. Return zeroes on reads.
14802 */
14803#define DDRPHY_PTR3_RESERVED_31_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR3_RESERVED_31_23_SHIFT)) & DDRPHY_PTR3_RESERVED_31_23_MASK)
14804/*! @} */
14805
14806/*! @name PTR4 - PHY Timing Register 4 */
14807/*! @{ */
14808#define DDRPHY_PTR4_tDINIT1_MASK (0x1FFFU)
14809#define DDRPHY_PTR4_tDINIT1_SHIFT (0U)
14810/*! tDINIT1 - DRAM Initialization Time 1
14811 */
14812#define DDRPHY_PTR4_tDINIT1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR4_tDINIT1_SHIFT)) & DDRPHY_PTR4_tDINIT1_MASK)
14813#define DDRPHY_PTR4_RESERVED_31_13_MASK (0xFFFFE000U)
14814#define DDRPHY_PTR4_RESERVED_31_13_SHIFT (13U)
14815/*! RESERVED_31_13 - Reserved. Return zeroes on reads.
14816 */
14817#define DDRPHY_PTR4_RESERVED_31_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR4_RESERVED_31_13_SHIFT)) & DDRPHY_PTR4_RESERVED_31_13_MASK)
14818/*! @} */
14819
14820/*! @name PTR5 - PHY Timing Register 5 */
14821/*! @{ */
14822#define DDRPHY_PTR5_tDINIT2_MASK (0x7FFFFU)
14823#define DDRPHY_PTR5_tDINIT2_SHIFT (0U)
14824/*! tDINIT2 - DRAM Initialization Time 1
14825 */
14826#define DDRPHY_PTR5_tDINIT2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR5_tDINIT2_SHIFT)) & DDRPHY_PTR5_tDINIT2_MASK)
14827#define DDRPHY_PTR5_RESERVED_31_19_MASK (0xFFF80000U)
14828#define DDRPHY_PTR5_RESERVED_31_19_SHIFT (19U)
14829/*! RESERVED_31_19 - Reserved. Return zeroes on reads.
14830 */
14831#define DDRPHY_PTR5_RESERVED_31_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR5_RESERVED_31_19_SHIFT)) & DDRPHY_PTR5_RESERVED_31_19_MASK)
14832/*! @} */
14833
14834/*! @name PTR6 - PHY Timing Register 6 */
14835/*! @{ */
14836#define DDRPHY_PTR6_tDINIT3_MASK (0xFFFU)
14837#define DDRPHY_PTR6_tDINIT3_SHIFT (0U)
14838/*! tDINIT3 - DRAM Initialization Time 3
14839 */
14840#define DDRPHY_PTR6_tDINIT3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR6_tDINIT3_SHIFT)) & DDRPHY_PTR6_tDINIT3_MASK)
14841#define DDRPHY_PTR6_RESERVED_19_12_MASK (0xFF000U)
14842#define DDRPHY_PTR6_RESERVED_19_12_SHIFT (12U)
14843/*! RESERVED_19_12 - Reserved. Return zeroes on reads.
14844 */
14845#define DDRPHY_PTR6_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR6_RESERVED_19_12_SHIFT)) & DDRPHY_PTR6_RESERVED_19_12_MASK)
14846#define DDRPHY_PTR6_tDINIT4_MASK (0x7F00000U)
14847#define DDRPHY_PTR6_tDINIT4_SHIFT (20U)
14848/*! tDINIT4 - DRAM Initialization Time 4
14849 */
14850#define DDRPHY_PTR6_tDINIT4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR6_tDINIT4_SHIFT)) & DDRPHY_PTR6_tDINIT4_MASK)
14851#define DDRPHY_PTR6_RESERVED_31_27_MASK (0xF8000000U)
14852#define DDRPHY_PTR6_RESERVED_31_27_SHIFT (27U)
14853/*! RESERVED_31_27 - Reserved. Return zeroes on reads.
14854 */
14855#define DDRPHY_PTR6_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PTR6_RESERVED_31_27_SHIFT)) & DDRPHY_PTR6_RESERVED_31_27_MASK)
14856/*! @} */
14857
14858/*! @name PLLCR0 - PLL Control Register 0 (Type B PLL Only) */
14859/*! @{ */
14860#define DDRPHY_PLLCR0_DTC_MASK (0xFU)
14861#define DDRPHY_PLLCR0_DTC_SHIFT (0U)
14862/*! DTC - Digital Test Control
14863 */
14864#define DDRPHY_PLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_DTC_SHIFT)) & DDRPHY_PLLCR0_DTC_MASK)
14865#define DDRPHY_PLLCR0_ATC_MASK (0xF0U)
14866#define DDRPHY_PLLCR0_ATC_SHIFT (4U)
14867/*! ATC - Analog Test Control
14868 */
14869#define DDRPHY_PLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_ATC_SHIFT)) & DDRPHY_PLLCR0_ATC_MASK)
14870#define DDRPHY_PLLCR0_ATOEN_MASK (0x100U)
14871#define DDRPHY_PLLCR0_ATOEN_SHIFT (8U)
14872/*! ATOEN - Analog Test Enable
14873 */
14874#define DDRPHY_PLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_ATOEN_SHIFT)) & DDRPHY_PLLCR0_ATOEN_MASK)
14875#define DDRPHY_PLLCR0_RESERVED_11_9_MASK (0xE00U)
14876#define DDRPHY_PLLCR0_RESERVED_11_9_SHIFT (9U)
14877/*! RESERVED_11_9 - Reserved. Return zeroes on reads.
14878 */
14879#define DDRPHY_PLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_PLLCR0_RESERVED_11_9_MASK)
14880#define DDRPHY_PLLCR0_GSHIFT_MASK (0x1000U)
14881#define DDRPHY_PLLCR0_GSHIFT_SHIFT (12U)
14882/*! GSHIFT - Gear Shift
14883 */
14884#define DDRPHY_PLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_GSHIFT_SHIFT)) & DDRPHY_PLLCR0_GSHIFT_MASK)
14885#define DDRPHY_PLLCR0_CPIC_MASK (0x1E000U)
14886#define DDRPHY_PLLCR0_CPIC_SHIFT (13U)
14887/*! CPIC - Charge Pump Integrating Current Control
14888 */
14889#define DDRPHY_PLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_CPIC_SHIFT)) & DDRPHY_PLLCR0_CPIC_MASK)
14890#define DDRPHY_PLLCR0_CPPC_MASK (0x7E0000U)
14891#define DDRPHY_PLLCR0_CPPC_SHIFT (17U)
14892/*! CPPC - Charge Pump Proportional Current Control
14893 */
14894#define DDRPHY_PLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_CPPC_SHIFT)) & DDRPHY_PLLCR0_CPPC_MASK)
14895#define DDRPHY_PLLCR0_RLOCKM_MASK (0x800000U)
14896#define DDRPHY_PLLCR0_RLOCKM_SHIFT (23U)
14897/*! RLOCKM - Relock Mode
14898 */
14899#define DDRPHY_PLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_RLOCKM_SHIFT)) & DDRPHY_PLLCR0_RLOCKM_MASK)
14900#define DDRPHY_PLLCR0_FRQSEL_MASK (0xF000000U)
14901#define DDRPHY_PLLCR0_FRQSEL_SHIFT (24U)
14902/*! FRQSEL - PLL Frequency Select
14903 */
14904#define DDRPHY_PLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_FRQSEL_SHIFT)) & DDRPHY_PLLCR0_FRQSEL_MASK)
14905#define DDRPHY_PLLCR0_RSTOPM_MASK (0x10000000U)
14906#define DDRPHY_PLLCR0_RSTOPM_SHIFT (28U)
14907/*! RSTOPM - Reference Stop Mode
14908 */
14909#define DDRPHY_PLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_RSTOPM_SHIFT)) & DDRPHY_PLLCR0_RSTOPM_MASK)
14910#define DDRPHY_PLLCR0_PLLPD_MASK (0x20000000U)
14911#define DDRPHY_PLLCR0_PLLPD_SHIFT (29U)
14912/*! PLLPD - PLL Power Down
14913 */
14914#define DDRPHY_PLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_PLLPD_SHIFT)) & DDRPHY_PLLCR0_PLLPD_MASK)
14915#define DDRPHY_PLLCR0_PLLRST_MASK (0x40000000U)
14916#define DDRPHY_PLLCR0_PLLRST_SHIFT (30U)
14917/*! PLLRST - PLL Reset
14918 */
14919#define DDRPHY_PLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_PLLRST_SHIFT)) & DDRPHY_PLLCR0_PLLRST_MASK)
14920#define DDRPHY_PLLCR0_PLLBYP_MASK (0x80000000U)
14921#define DDRPHY_PLLCR0_PLLBYP_SHIFT (31U)
14922/*! PLLBYP - PLL Bypass
14923 */
14924#define DDRPHY_PLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR0_PLLBYP_SHIFT)) & DDRPHY_PLLCR0_PLLBYP_MASK)
14925/*! @} */
14926
14927/*! @name PLLCR1 - PLL Control Register 1 (Type B PLL Only) */
14928/*! @{ */
14929#define DDRPHY_PLLCR1_LOCKDS_MASK (0x1U)
14930#define DDRPHY_PLLCR1_LOCKDS_SHIFT (0U)
14931/*! LOCKDS - Lock Detector Select
14932 */
14933#define DDRPHY_PLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_LOCKDS_SHIFT)) & DDRPHY_PLLCR1_LOCKDS_MASK)
14934#define DDRPHY_PLLCR1_LOCKCS_MASK (0x2U)
14935#define DDRPHY_PLLCR1_LOCKCS_SHIFT (1U)
14936/*! LOCKCS - Lock Detector Counter Select
14937 */
14938#define DDRPHY_PLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_LOCKCS_SHIFT)) & DDRPHY_PLLCR1_LOCKCS_MASK)
14939#define DDRPHY_PLLCR1_LOCKPS_MASK (0x4U)
14940#define DDRPHY_PLLCR1_LOCKPS_SHIFT (2U)
14941/*! LOCKPS - Lock Detector Phase Select
14942 */
14943#define DDRPHY_PLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_LOCKPS_SHIFT)) & DDRPHY_PLLCR1_LOCKPS_MASK)
14944#define DDRPHY_PLLCR1_BYPVDD_MASK (0x8U)
14945#define DDRPHY_PLLCR1_BYPVDD_SHIFT (3U)
14946/*! BYPVDD - PLL VDD voltage level control
14947 */
14948#define DDRPHY_PLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_BYPVDD_SHIFT)) & DDRPHY_PLLCR1_BYPVDD_MASK)
14949#define DDRPHY_PLLCR1_BYPVREGDIG_MASK (0x10U)
14950#define DDRPHY_PLLCR1_BYPVREGDIG_SHIFT (4U)
14951/*! BYPVREGDIG - Bypass PLL vreg_dig
14952 */
14953#define DDRPHY_PLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_PLLCR1_BYPVREGDIG_MASK)
14954#define DDRPHY_PLLCR1_BYPVREGCP_MASK (0x20U)
14955#define DDRPHY_PLLCR1_BYPVREGCP_SHIFT (5U)
14956/*! BYPVREGCP - Bypass PLL vreg_cp
14957 */
14958#define DDRPHY_PLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_PLLCR1_BYPVREGCP_MASK)
14959#define DDRPHY_PLLCR1_RESERVED_15_6_MASK (0xFFC0U)
14960#define DDRPHY_PLLCR1_RESERVED_15_6_SHIFT (6U)
14961/*! RESERVED_15_6 - Reserved. Return zeroes on reads.
14962 */
14963#define DDRPHY_PLLCR1_RESERVED_15_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_RESERVED_15_6_SHIFT)) & DDRPHY_PLLCR1_RESERVED_15_6_MASK)
14964#define DDRPHY_PLLCR1_PLLPROG_MASK (0xFFFF0000U)
14965#define DDRPHY_PLLCR1_PLLPROG_SHIFT (16U)
14966/*! PLLPROG - Connects to the PLL PLL_PROG bus.
14967 */
14968#define DDRPHY_PLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR1_PLLPROG_SHIFT)) & DDRPHY_PLLCR1_PLLPROG_MASK)
14969/*! @} */
14970
14971/*! @name PLLCR2 - PLL Control Register 2 (Type B PLL Only) */
14972/*! @{ */
14973#define DDRPHY_PLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU)
14974#define DDRPHY_PLLCR2_PLLCTRL_31_0_SHIFT (0U)
14975/*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
14976 */
14977#define DDRPHY_PLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_PLLCR2_PLLCTRL_31_0_MASK)
14978/*! @} */
14979
14980/*! @name PLLCR3 - PLL Control Register 3 (Type B PLL Only) */
14981/*! @{ */
14982#define DDRPHY_PLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU)
14983#define DDRPHY_PLLCR3_PLLCTRL_63_32_SHIFT (0U)
14984/*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
14985 */
14986#define DDRPHY_PLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_PLLCR3_PLLCTRL_63_32_MASK)
14987/*! @} */
14988
14989/*! @name PLLCR4 - PLL Control Register 4 (Type B PLL Only) */
14990/*! @{ */
14991#define DDRPHY_PLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU)
14992#define DDRPHY_PLLCR4_PLLCTRL_95_64_SHIFT (0U)
14993/*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
14994 */
14995#define DDRPHY_PLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_PLLCR4_PLLCTRL_95_64_MASK)
14996/*! @} */
14997
14998/*! @name PLLCR5 - PLL Control Register 5 (Type B PLL Only) */
14999/*! @{ */
15000#define DDRPHY_PLLCR5_PLLCTRL_103_96_MASK (0xFFU)
15001#define DDRPHY_PLLCR5_PLLCTRL_103_96_SHIFT (0U)
15002/*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
15003 */
15004#define DDRPHY_PLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_PLLCR5_PLLCTRL_103_96_MASK)
15005#define DDRPHY_PLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U)
15006#define DDRPHY_PLLCR5_RESERVED_31_8_SHIFT (8U)
15007/*! RESERVED_31_8 - Reserved. Return zeroes on reads.
15008 */
15009#define DDRPHY_PLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_PLLCR5_RESERVED_31_8_MASK)
15010/*! @} */
15011
15012/*! @name DXCCR - DATX8 Common Configuration Register */
15013/*! @{ */
15014#define DDRPHY_DXCCR_RESERVED_2_0_MASK (0x7U)
15015#define DDRPHY_DXCCR_RESERVED_2_0_SHIFT (0U)
15016/*! RESERVED_2_0 - Reserved. Return zeroes on reads
15017 */
15018#define DDRPHY_DXCCR_RESERVED_2_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DXCCR_RESERVED_2_0_SHIFT)) & DDRPHY_DXCCR_RESERVED_2_0_MASK)
15019#define DDRPHY_DXCCR_DQS2DQMPER_MASK (0x78U)
15020#define DDRPHY_DXCCR_DQS2DQMPER_SHIFT (3U)
15021/*! DQS2DQMPER - Write DQS2DQ Training Measurement Period
15022 */
15023#define DDRPHY_DXCCR_DQS2DQMPER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DXCCR_DQS2DQMPER_SHIFT)) & DDRPHY_DXCCR_DQS2DQMPER_MASK)
15024#define DDRPHY_DXCCR_RESERVED_28_7_MASK (0x1FFFFF80U)
15025#define DDRPHY_DXCCR_RESERVED_28_7_SHIFT (7U)
15026/*! RESERVED_28_7 - Reserved. Return zeroes on reads
15027 */
15028#define DDRPHY_DXCCR_RESERVED_28_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DXCCR_RESERVED_28_7_SHIFT)) & DDRPHY_DXCCR_RESERVED_28_7_MASK)
15029#define DDRPHY_DXCCR_RKLOOP_MASK (0x20000000U)
15030#define DDRPHY_DXCCR_RKLOOP_SHIFT (29U)
15031/*! RKLOOP - Rank looping (per-rank eye centering) enable
15032 */
15033#define DDRPHY_DXCCR_RKLOOP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DXCCR_RKLOOP_SHIFT)) & DDRPHY_DXCCR_RKLOOP_MASK)
15034#define DDRPHY_DXCCR_RESERVED_31_30_MASK (0xC0000000U)
15035#define DDRPHY_DXCCR_RESERVED_31_30_SHIFT (30U)
15036/*! RESERVED_31_30 - Reserved. Return zeroes on reads
15037 */
15038#define DDRPHY_DXCCR_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DXCCR_RESERVED_31_30_SHIFT)) & DDRPHY_DXCCR_RESERVED_31_30_MASK)
15039/*! @} */
15040
15041/*! @name DSGCR - DDR System General Configuration Register */
15042/*! @{ */
15043#define DDRPHY_DSGCR_PUREN_MASK (0x1U)
15044#define DDRPHY_DSGCR_PUREN_SHIFT (0U)
15045/*! PUREN - PHY Update Request Enable
15046 */
15047#define DDRPHY_DSGCR_PUREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_PUREN_SHIFT)) & DDRPHY_DSGCR_PUREN_MASK)
15048#define DDRPHY_DSGCR_MREN_MASK (0x2U)
15049#define DDRPHY_DSGCR_MREN_SHIFT (1U)
15050/*! MREN - Master Request Enable
15051 */
15052#define DDRPHY_DSGCR_MREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_MREN_SHIFT)) & DDRPHY_DSGCR_MREN_MASK)
15053#define DDRPHY_DSGCR_CTLZUEN_MASK (0x4U)
15054#define DDRPHY_DSGCR_CTLZUEN_SHIFT (2U)
15055/*! CTLZUEN - Controller Impedance Update Enable
15056 */
15057#define DDRPHY_DSGCR_CTLZUEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_CTLZUEN_SHIFT)) & DDRPHY_DSGCR_CTLZUEN_MASK)
15058#define DDRPHY_DSGCR_MSTRVER_MASK (0x8U)
15059#define DDRPHY_DSGCR_MSTRVER_SHIFT (3U)
15060/*! MSTRVER - Master Version
15061 */
15062#define DDRPHY_DSGCR_MSTRVER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_MSTRVER_SHIFT)) & DDRPHY_DSGCR_MSTRVER_MASK)
15063#define DDRPHY_DSGCR_RESERVED_4_MASK (0x10U)
15064#define DDRPHY_DSGCR_RESERVED_4_SHIFT (4U)
15065/*! RESERVED_4 - Reserved. Return zeroes on reads
15066 */
15067#define DDRPHY_DSGCR_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RESERVED_4_SHIFT)) & DDRPHY_DSGCR_RESERVED_4_MASK)
15068#define DDRPHY_DSGCR_CUAEN_MASK (0x20U)
15069#define DDRPHY_DSGCR_CUAEN_SHIFT (5U)
15070/*! CUAEN - Controller Update Acknowledge Enable
15071 */
15072#define DDRPHY_DSGCR_CUAEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_CUAEN_SHIFT)) & DDRPHY_DSGCR_CUAEN_MASK)
15073#define DDRPHY_DSGCR_PUAD_MASK (0xFC0U)
15074#define DDRPHY_DSGCR_PUAD_SHIFT (6U)
15075/*! PUAD - PHY Update Acknowledge Delay
15076 */
15077#define DDRPHY_DSGCR_PUAD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_PUAD_SHIFT)) & DDRPHY_DSGCR_PUAD_MASK)
15078#define DDRPHY_DSGCR_DTOODT_MASK (0x1000U)
15079#define DDRPHY_DSGCR_DTOODT_SHIFT (12U)
15080/*! DTOODT - DTO On-Die Termination
15081 */
15082#define DDRPHY_DSGCR_DTOODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_DTOODT_SHIFT)) & DDRPHY_DSGCR_DTOODT_MASK)
15083#define DDRPHY_DSGCR_RESERVED_13_MASK (0x2000U)
15084#define DDRPHY_DSGCR_RESERVED_13_SHIFT (13U)
15085/*! RESERVED_13 - Reserved. Return zeroes on reads
15086 */
15087#define DDRPHY_DSGCR_RESERVED_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RESERVED_13_SHIFT)) & DDRPHY_DSGCR_RESERVED_13_MASK)
15088#define DDRPHY_DSGCR_DTOPDR_MASK (0x4000U)
15089#define DDRPHY_DSGCR_DTOPDR_SHIFT (14U)
15090/*! DTOPDR - DTO Power Down Receiver
15091 */
15092#define DDRPHY_DSGCR_DTOPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_DTOPDR_SHIFT)) & DDRPHY_DSGCR_DTOPDR_MASK)
15093#define DDRPHY_DSGCR_DTOIOM_MASK (0x8000U)
15094#define DDRPHY_DSGCR_DTOIOM_SHIFT (15U)
15095/*! DTOIOM - DTO I/O Mode
15096 */
15097#define DDRPHY_DSGCR_DTOIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_DTOIOM_SHIFT)) & DDRPHY_DSGCR_DTOIOM_MASK)
15098#define DDRPHY_DSGCR_DTOOE_MASK (0x10000U)
15099#define DDRPHY_DSGCR_DTOOE_SHIFT (16U)
15100/*! DTOOE - DTO Output Enable
15101 */
15102#define DDRPHY_DSGCR_DTOOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_DTOOE_SHIFT)) & DDRPHY_DSGCR_DTOOE_MASK)
15103#define DDRPHY_DSGCR_ATOAE_MASK (0x20000U)
15104#define DDRPHY_DSGCR_ATOAE_SHIFT (17U)
15105/*! ATOAE - ATO Analog Test Enable
15106 */
15107#define DDRPHY_DSGCR_ATOAE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_ATOAE_SHIFT)) & DDRPHY_DSGCR_ATOAE_MASK)
15108#define DDRPHY_DSGCR_RESERVED_18_MASK (0x40000U)
15109#define DDRPHY_DSGCR_RESERVED_18_SHIFT (18U)
15110/*! RESERVED_18 - Reserved. Return zeroes on reads.
15111 */
15112#define DDRPHY_DSGCR_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RESERVED_18_SHIFT)) & DDRPHY_DSGCR_RESERVED_18_MASK)
15113#define DDRPHY_DSGCR_SDRMODE_MASK (0x180000U)
15114#define DDRPHY_DSGCR_SDRMODE_SHIFT (19U)
15115/*! SDRMODE - Single Data Rate Mode
15116 */
15117#define DDRPHY_DSGCR_SDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_SDRMODE_SHIFT)) & DDRPHY_DSGCR_SDRMODE_MASK)
15118#define DDRPHY_DSGCR_RSTOE_MASK (0x200000U)
15119#define DDRPHY_DSGCR_RSTOE_SHIFT (21U)
15120/*! RSTOE - SDRAM Reset Output Enable
15121 */
15122#define DDRPHY_DSGCR_RSTOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RSTOE_SHIFT)) & DDRPHY_DSGCR_RSTOE_MASK)
15123#define DDRPHY_DSGCR_RESERVED_22_MASK (0x400000U)
15124#define DDRPHY_DSGCR_RESERVED_22_SHIFT (22U)
15125/*! RESERVED_22 - Reserved. Return zeroes on reads.
15126 */
15127#define DDRPHY_DSGCR_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RESERVED_22_SHIFT)) & DDRPHY_DSGCR_RESERVED_22_MASK)
15128#define DDRPHY_DSGCR_PHYZUEN_MASK (0x800000U)
15129#define DDRPHY_DSGCR_PHYZUEN_SHIFT (23U)
15130/*! PHYZUEN - PHY Impedance Update Enable
15131 */
15132#define DDRPHY_DSGCR_PHYZUEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_PHYZUEN_SHIFT)) & DDRPHY_DSGCR_PHYZUEN_MASK)
15133#define DDRPHY_DSGCR_RDBICL_MASK (0x7000000U)
15134#define DDRPHY_DSGCR_RDBICL_SHIFT (24U)
15135/*! RDBICL - When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value.
15136 */
15137#define DDRPHY_DSGCR_RDBICL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RDBICL_SHIFT)) & DDRPHY_DSGCR_RDBICL_MASK)
15138#define DDRPHY_DSGCR_RDBICLSEL_MASK (0x8000000U)
15139#define DDRPHY_DSGCR_RDBICLSEL_SHIFT (27U)
15140/*! RDBICLSEL - When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1,
15141 * calculation will use RDBICL, otherwise use default calculation.
15142 */
15143#define DDRPHY_DSGCR_RDBICLSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RDBICLSEL_SHIFT)) & DDRPHY_DSGCR_RDBICLSEL_MASK)
15144#define DDRPHY_DSGCR_RESERVED_31_28_MASK (0xF0000000U)
15145#define DDRPHY_DSGCR_RESERVED_31_28_SHIFT (28U)
15146/*! RESERVED_31_28 - Reserved. Return zeroes on reads.
15147 */
15148#define DDRPHY_DSGCR_RESERVED_31_28(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DSGCR_RESERVED_31_28_SHIFT)) & DDRPHY_DSGCR_RESERVED_31_28_MASK)
15149/*! @} */
15150
15151/*! @name ODTCR - ODT Configuration Register */
15152/*! @{ */
15153#define DDRPHY_ODTCR_RDODT_MASK (0x1U)
15154#define DDRPHY_ODTCR_RDODT_SHIFT (0U)
15155/*! RDODT - Read ODT.
15156 */
15157#define DDRPHY_ODTCR_RDODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ODTCR_RDODT_SHIFT)) & DDRPHY_ODTCR_RDODT_MASK)
15158#define DDRPHY_ODTCR_RDODT_RSVD_MASK (0xFFEU)
15159#define DDRPHY_ODTCR_RDODT_RSVD_SHIFT (1U)
15160/*! RDODT_RSVD - Reserved. Return zeroes on reads.
15161 */
15162#define DDRPHY_ODTCR_RDODT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ODTCR_RDODT_RSVD_SHIFT)) & DDRPHY_ODTCR_RDODT_RSVD_MASK)
15163#define DDRPHY_ODTCR_RESERVED_15_12_MASK (0xF000U)
15164#define DDRPHY_ODTCR_RESERVED_15_12_SHIFT (12U)
15165/*! RESERVED_15_12 - Reserved. Return zeroes on reads.
15166 */
15167#define DDRPHY_ODTCR_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ODTCR_RESERVED_15_12_SHIFT)) & DDRPHY_ODTCR_RESERVED_15_12_MASK)
15168#define DDRPHY_ODTCR_WRODT_MASK (0x10000U)
15169#define DDRPHY_ODTCR_WRODT_SHIFT (16U)
15170/*! WRODT - Write ODT.
15171 */
15172#define DDRPHY_ODTCR_WRODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ODTCR_WRODT_SHIFT)) & DDRPHY_ODTCR_WRODT_MASK)
15173#define DDRPHY_ODTCR_WRODT_RSVD_MASK (0xFFE0000U)
15174#define DDRPHY_ODTCR_WRODT_RSVD_SHIFT (17U)
15175/*! WRODT_RSVD - Reserved. Return zeroes on reads.
15176 */
15177#define DDRPHY_ODTCR_WRODT_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ODTCR_WRODT_RSVD_SHIFT)) & DDRPHY_ODTCR_WRODT_RSVD_MASK)
15178#define DDRPHY_ODTCR_RESERVED_31_28_MASK (0xF0000000U)
15179#define DDRPHY_ODTCR_RESERVED_31_28_SHIFT (28U)
15180/*! RESERVED_31_28 - Reserved. Return zeroes on reads.
15181 */
15182#define DDRPHY_ODTCR_RESERVED_31_28(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ODTCR_RESERVED_31_28_SHIFT)) & DDRPHY_ODTCR_RESERVED_31_28_MASK)
15183/*! @} */
15184
15185/*! @name AACR - Anti-Aging Control Register */
15186/*! @{ */
15187#define DDRPHY_AACR_AATR_MASK (0x3FFFFFFFU)
15188#define DDRPHY_AACR_AATR_SHIFT (0U)
15189/*! AATR - Anti-Aging Toggle Rate
15190 */
15191#define DDRPHY_AACR_AATR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_AACR_AATR_SHIFT)) & DDRPHY_AACR_AATR_MASK)
15192#define DDRPHY_AACR_AAENC_MASK (0x40000000U)
15193#define DDRPHY_AACR_AAENC_SHIFT (30U)
15194/*! AAENC - Anti-Aging Enable Control
15195 */
15196#define DDRPHY_AACR_AAENC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_AACR_AAENC_SHIFT)) & DDRPHY_AACR_AAENC_MASK)
15197#define DDRPHY_AACR_AAOENC_MASK (0x80000000U)
15198#define DDRPHY_AACR_AAOENC_SHIFT (31U)
15199/*! AAOENC - Anti-Aging PAD Output Enable Control
15200 */
15201#define DDRPHY_AACR_AAOENC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_AACR_AAOENC_SHIFT)) & DDRPHY_AACR_AAOENC_MASK)
15202/*! @} */
15203
15204/*! @name GPR0 - General Purpose Register 0 */
15205/*! @{ */
15206#define DDRPHY_GPR0_GPR0_MASK (0xFFFFFFFFU)
15207#define DDRPHY_GPR0_GPR0_SHIFT (0U)
15208/*! GPR0 - General Purpose Register 0
15209 */
15210#define DDRPHY_GPR0_GPR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_GPR0_GPR0_SHIFT)) & DDRPHY_GPR0_GPR0_MASK)
15211/*! @} */
15212
15213/*! @name GPR1 - General Purpose Register 1 */
15214/*! @{ */
15215#define DDRPHY_GPR1_GPR1_MASK (0xFFFFFFFFU)
15216#define DDRPHY_GPR1_GPR1_SHIFT (0U)
15217/*! GPR1 - General Purpose Register 1
15218 */
15219#define DDRPHY_GPR1_GPR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_GPR1_GPR1_SHIFT)) & DDRPHY_GPR1_GPR1_MASK)
15220/*! @} */
15221
15222/*! @name DCR - DRAM Configuration Register */
15223/*! @{ */
15224#define DDRPHY_DCR_DDRMD_MASK (0x7U)
15225#define DDRPHY_DCR_DDRMD_SHIFT (0U)
15226/*! DDRMD - DDR Mode
15227 */
15228#define DDRPHY_DCR_DDRMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_DDRMD_SHIFT)) & DDRPHY_DCR_DDRMD_MASK)
15229#define DDRPHY_DCR_DDR8BNK_MASK (0x8U)
15230#define DDRPHY_DCR_DDR8BNK_SHIFT (3U)
15231/*! DDR8BNK - DDR 8-Bank
15232 */
15233#define DDRPHY_DCR_DDR8BNK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_DDR8BNK_SHIFT)) & DDRPHY_DCR_DDR8BNK_MASK)
15234#define DDRPHY_DCR_PDQ_MASK (0x70U)
15235#define DDRPHY_DCR_PDQ_SHIFT (4U)
15236/*! PDQ - Primary DQ (DDR3 Only)
15237 */
15238#define DDRPHY_DCR_PDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_PDQ_SHIFT)) & DDRPHY_DCR_PDQ_MASK)
15239#define DDRPHY_DCR_MPRDQ_MASK (0x80U)
15240#define DDRPHY_DCR_MPRDQ_SHIFT (7U)
15241/*! MPRDQ - Multi-Purpose Register (MPR) DQ (DDR3 Only)
15242 */
15243#define DDRPHY_DCR_MPRDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_MPRDQ_SHIFT)) & DDRPHY_DCR_MPRDQ_MASK)
15244#define DDRPHY_DCR_DDRTYPE_MASK (0x300U)
15245#define DDRPHY_DCR_DDRTYPE_SHIFT (8U)
15246/*! DDRTYPE - DDR Type
15247 */
15248#define DDRPHY_DCR_DDRTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_DDRTYPE_SHIFT)) & DDRPHY_DCR_DDRTYPE_MASK)
15249#define DDRPHY_DCR_BYTEMASK_MASK (0x3FC00U)
15250#define DDRPHY_DCR_BYTEMASK_SHIFT (10U)
15251/*! BYTEMASK - Byte Mask
15252 */
15253#define DDRPHY_DCR_BYTEMASK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_BYTEMASK_SHIFT)) & DDRPHY_DCR_BYTEMASK_MASK)
15254#define DDRPHY_DCR_RESERVED_26_18_MASK (0x7FC0000U)
15255#define DDRPHY_DCR_RESERVED_26_18_SHIFT (18U)
15256/*! RESERVED_26_18 - Reserved. Return zeroes on reads.
15257 */
15258#define DDRPHY_DCR_RESERVED_26_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_RESERVED_26_18_SHIFT)) & DDRPHY_DCR_RESERVED_26_18_MASK)
15259#define DDRPHY_DCR_NOSRA_MASK (0x8000000U)
15260#define DDRPHY_DCR_NOSRA_SHIFT (27U)
15261/*! NOSRA - No Simultaneous Rank Access
15262 */
15263#define DDRPHY_DCR_NOSRA(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_NOSRA_SHIFT)) & DDRPHY_DCR_NOSRA_MASK)
15264#define DDRPHY_DCR_DDR2T_MASK (0x10000000U)
15265#define DDRPHY_DCR_DDR2T_SHIFT (28U)
15266/*! DDR2T - DDR 2T Timing
15267 */
15268#define DDRPHY_DCR_DDR2T(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_DDR2T_SHIFT)) & DDRPHY_DCR_DDR2T_MASK)
15269#define DDRPHY_DCR_UDIMM_MASK (0x20000000U)
15270#define DDRPHY_DCR_UDIMM_SHIFT (29U)
15271/*! UDIMM - Un-buffered DIMM Address Mirroring
15272 */
15273#define DDRPHY_DCR_UDIMM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_UDIMM_SHIFT)) & DDRPHY_DCR_UDIMM_MASK)
15274#define DDRPHY_DCR_UBG_MASK (0x40000000U)
15275#define DDRPHY_DCR_UBG_SHIFT (30U)
15276/*! UBG - Un-used Bank Group
15277 */
15278#define DDRPHY_DCR_UBG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_UBG_SHIFT)) & DDRPHY_DCR_UBG_MASK)
15279#define DDRPHY_DCR_GEARDN_MASK (0x80000000U)
15280#define DDRPHY_DCR_GEARDN_SHIFT (31U)
15281/*! GEARDN - DDR4 Gear Down Timing.
15282 */
15283#define DDRPHY_DCR_GEARDN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCR_GEARDN_SHIFT)) & DDRPHY_DCR_GEARDN_MASK)
15284/*! @} */
15285
15286/*! @name DTPR0 - DRAM Timing Parameters Register 0 */
15287/*! @{ */
15288#define DDRPHY_DTPR0_tRTP_MASK (0x1FU)
15289#define DDRPHY_DTPR0_tRTP_SHIFT (0U)
15290/*! tRTP - Internal read to precharge command delay
15291 */
15292#define DDRPHY_DTPR0_tRTP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_tRTP_SHIFT)) & DDRPHY_DTPR0_tRTP_MASK)
15293#define DDRPHY_DTPR0_RESERVED_7_5_MASK (0xE0U)
15294#define DDRPHY_DTPR0_RESERVED_7_5_SHIFT (5U)
15295/*! RESERVED_7_5 - Reserved. Return zeroes on reads.
15296 */
15297#define DDRPHY_DTPR0_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_RESERVED_7_5_SHIFT)) & DDRPHY_DTPR0_RESERVED_7_5_MASK)
15298#define DDRPHY_DTPR0_tRP_MASK (0x7F00U)
15299#define DDRPHY_DTPR0_tRP_SHIFT (8U)
15300/*! tRP - Precharge command period
15301 */
15302#define DDRPHY_DTPR0_tRP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_tRP_SHIFT)) & DDRPHY_DTPR0_tRP_MASK)
15303#define DDRPHY_DTPR0_RESERVED_15_MASK (0x8000U)
15304#define DDRPHY_DTPR0_RESERVED_15_SHIFT (15U)
15305/*! RESERVED_15 - Reserved. Return zeroes on reads.
15306 */
15307#define DDRPHY_DTPR0_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_RESERVED_15_SHIFT)) & DDRPHY_DTPR0_RESERVED_15_MASK)
15308#define DDRPHY_DTPR0_tRAS_MASK (0x7F0000U)
15309#define DDRPHY_DTPR0_tRAS_SHIFT (16U)
15310/*! tRAS - Activate to precharge command delay
15311 */
15312#define DDRPHY_DTPR0_tRAS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_tRAS_SHIFT)) & DDRPHY_DTPR0_tRAS_MASK)
15313#define DDRPHY_DTPR0_RESERVED_23_MASK (0x800000U)
15314#define DDRPHY_DTPR0_RESERVED_23_SHIFT (23U)
15315/*! RESERVED_23 - Reserved. Return zeroes on reads.
15316 */
15317#define DDRPHY_DTPR0_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_RESERVED_23_SHIFT)) & DDRPHY_DTPR0_RESERVED_23_MASK)
15318#define DDRPHY_DTPR0_tRRD_MASK (0x1F000000U)
15319#define DDRPHY_DTPR0_tRRD_SHIFT (24U)
15320/*! tRRD - Activate to activate command delay (different banks)
15321 */
15322#define DDRPHY_DTPR0_tRRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_tRRD_SHIFT)) & DDRPHY_DTPR0_tRRD_MASK)
15323#define DDRPHY_DTPR0_RESERVED_31_29_MASK (0xE0000000U)
15324#define DDRPHY_DTPR0_RESERVED_31_29_SHIFT (29U)
15325/*! RESERVED_31_29 - Reserved. Return zeroes on reads.
15326 */
15327#define DDRPHY_DTPR0_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR0_RESERVED_31_29_SHIFT)) & DDRPHY_DTPR0_RESERVED_31_29_MASK)
15328/*! @} */
15329
15330/*! @name DTPR1 - DRAM Timing Parameters Register 1 */
15331/*! @{ */
15332#define DDRPHY_DTPR1_tMRD_MASK (0x1FU)
15333#define DDRPHY_DTPR1_tMRD_SHIFT (0U)
15334/*! tMRD - Load mode cycle time
15335 */
15336#define DDRPHY_DTPR1_tMRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_tMRD_SHIFT)) & DDRPHY_DTPR1_tMRD_MASK)
15337#define DDRPHY_DTPR1_RESERVED_7_5_MASK (0xE0U)
15338#define DDRPHY_DTPR1_RESERVED_7_5_SHIFT (5U)
15339/*! RESERVED_7_5 - Reserved. Return zeroes on reads.
15340 */
15341#define DDRPHY_DTPR1_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_RESERVED_7_5_SHIFT)) & DDRPHY_DTPR1_RESERVED_7_5_MASK)
15342#define DDRPHY_DTPR1_tMOD_MASK (0x700U)
15343#define DDRPHY_DTPR1_tMOD_SHIFT (8U)
15344/*! tMOD - Load mode update delay (DDR4 and DDR3 only)
15345 */
15346#define DDRPHY_DTPR1_tMOD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_tMOD_SHIFT)) & DDRPHY_DTPR1_tMOD_MASK)
15347#define DDRPHY_DTPR1_RESERVED_15_11_MASK (0xF800U)
15348#define DDRPHY_DTPR1_RESERVED_15_11_SHIFT (11U)
15349/*! RESERVED_15_11 - Reserved. Return zeroes on reads.
15350 */
15351#define DDRPHY_DTPR1_RESERVED_15_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_RESERVED_15_11_SHIFT)) & DDRPHY_DTPR1_RESERVED_15_11_MASK)
15352#define DDRPHY_DTPR1_tFAW_MASK (0x7F0000U)
15353#define DDRPHY_DTPR1_tFAW_SHIFT (16U)
15354/*! tFAW - 4-bank activate period
15355 */
15356#define DDRPHY_DTPR1_tFAW(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_tFAW_SHIFT)) & DDRPHY_DTPR1_tFAW_MASK)
15357#define DDRPHY_DTPR1_RESERVED_23_MASK (0x800000U)
15358#define DDRPHY_DTPR1_RESERVED_23_SHIFT (23U)
15359/*! RESERVED_23 - Reserved. Return zeroes on reads.
15360 */
15361#define DDRPHY_DTPR1_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_RESERVED_23_SHIFT)) & DDRPHY_DTPR1_RESERVED_23_MASK)
15362#define DDRPHY_DTPR1_tWLMRD_MASK (0x7F000000U)
15363#define DDRPHY_DTPR1_tWLMRD_SHIFT (24U)
15364/*! tWLMRD - Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge.
15365 */
15366#define DDRPHY_DTPR1_tWLMRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_tWLMRD_SHIFT)) & DDRPHY_DTPR1_tWLMRD_MASK)
15367#define DDRPHY_DTPR1_RESERVED_31_MASK (0x80000000U)
15368#define DDRPHY_DTPR1_RESERVED_31_SHIFT (31U)
15369/*! RESERVED_31 - Reserved. Return zeroes on reads.
15370 */
15371#define DDRPHY_DTPR1_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR1_RESERVED_31_SHIFT)) & DDRPHY_DTPR1_RESERVED_31_MASK)
15372/*! @} */
15373
15374/*! @name DTPR2 - DRAM Timing Parameters Register 2 */
15375/*! @{ */
15376#define DDRPHY_DTPR2_tXS_MASK (0x3FFU)
15377#define DDRPHY_DTPR2_tXS_SHIFT (0U)
15378/*! tXS - Self refresh exit delay
15379 */
15380#define DDRPHY_DTPR2_tXS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_tXS_SHIFT)) & DDRPHY_DTPR2_tXS_MASK)
15381#define DDRPHY_DTPR2_RESERVED_15_10_MASK (0xFC00U)
15382#define DDRPHY_DTPR2_RESERVED_15_10_SHIFT (10U)
15383/*! RESERVED_15_10 - Reserved. Return zeroes on reads.
15384 */
15385#define DDRPHY_DTPR2_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_RESERVED_15_10_SHIFT)) & DDRPHY_DTPR2_RESERVED_15_10_MASK)
15386#define DDRPHY_DTPR2_tCKE_MASK (0xF0000U)
15387#define DDRPHY_DTPR2_tCKE_SHIFT (16U)
15388/*! tCKE - CKE minimum pulse width
15389 */
15390#define DDRPHY_DTPR2_tCKE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_tCKE_SHIFT)) & DDRPHY_DTPR2_tCKE_MASK)
15391#define DDRPHY_DTPR2_tCMDCKE_MASK (0xF00000U)
15392#define DDRPHY_DTPR2_tCMDCKE_SHIFT (20U)
15393/*! tCMDCKE - Delay from Valid command to CKE Input low (LPDDR4 mode only)
15394 */
15395#define DDRPHY_DTPR2_tCMDCKE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_tCMDCKE_SHIFT)) & DDRPHY_DTPR2_tCMDCKE_MASK)
15396#define DDRPHY_DTPR2_tRTODT_MASK (0x1000000U)
15397#define DDRPHY_DTPR2_tRTODT_SHIFT (24U)
15398/*! tRTODT - Read to ODT delay (DDR3 only)
15399 */
15400#define DDRPHY_DTPR2_tRTODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_tRTODT_SHIFT)) & DDRPHY_DTPR2_tRTODT_MASK)
15401#define DDRPHY_DTPR2_RESERVED_27_25_MASK (0xE000000U)
15402#define DDRPHY_DTPR2_RESERVED_27_25_SHIFT (25U)
15403/*! RESERVED_27_25 - Reserved. Return zeroes on reads.
15404 */
15405#define DDRPHY_DTPR2_RESERVED_27_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_RESERVED_27_25_SHIFT)) & DDRPHY_DTPR2_RESERVED_27_25_MASK)
15406#define DDRPHY_DTPR2_tRTW_MASK (0x10000000U)
15407#define DDRPHY_DTPR2_tRTW_SHIFT (28U)
15408/*! tRTW - Read to Write command delay. Valid values are
15409 */
15410#define DDRPHY_DTPR2_tRTW(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_tRTW_SHIFT)) & DDRPHY_DTPR2_tRTW_MASK)
15411#define DDRPHY_DTPR2_RESERVED_31_29_MASK (0xE0000000U)
15412#define DDRPHY_DTPR2_RESERVED_31_29_SHIFT (29U)
15413/*! RESERVED_31_29 - Reserved. Return zeroes on reads.
15414 */
15415#define DDRPHY_DTPR2_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR2_RESERVED_31_29_SHIFT)) & DDRPHY_DTPR2_RESERVED_31_29_MASK)
15416/*! @} */
15417
15418/*! @name DTPR3 - DRAM Timing Parameters Register 3 */
15419/*! @{ */
15420#define DDRPHY_DTPR3_TDQSCK_MASK (0x7U)
15421#define DDRPHY_DTPR3_TDQSCK_SHIFT (0U)
15422/*! TDQSCK - DQS output access time from CK/CK# (LPDDR2/3 only)
15423 */
15424#define DDRPHY_DTPR3_TDQSCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_TDQSCK_SHIFT)) & DDRPHY_DTPR3_TDQSCK_MASK)
15425#define DDRPHY_DTPR3_RESERVED_7_3_MASK (0xF8U)
15426#define DDRPHY_DTPR3_RESERVED_7_3_SHIFT (3U)
15427/*! RESERVED_7_3 - Reserved. Return zeroes on reads.
15428 */
15429#define DDRPHY_DTPR3_RESERVED_7_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_RESERVED_7_3_SHIFT)) & DDRPHY_DTPR3_RESERVED_7_3_MASK)
15430#define DDRPHY_DTPR3_tDQSCKmax_MASK (0xF00U)
15431#define DDRPHY_DTPR3_tDQSCKmax_SHIFT (8U)
15432/*! tDQSCKmax - Maximum DQS output access time from CK/CK# (LPDDR2/3 only)
15433 */
15434#define DDRPHY_DTPR3_tDQSCKmax(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_tDQSCKmax_SHIFT)) & DDRPHY_DTPR3_tDQSCKmax_MASK)
15435#define DDRPHY_DTPR3_RESERVED_15_12_MASK (0xF000U)
15436#define DDRPHY_DTPR3_RESERVED_15_12_SHIFT (12U)
15437/*! RESERVED_15_12 - Reserved. Return zeroes on reads.
15438 */
15439#define DDRPHY_DTPR3_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_RESERVED_15_12_SHIFT)) & DDRPHY_DTPR3_RESERVED_15_12_MASK)
15440#define DDRPHY_DTPR3_tDLLK_MASK (0x3FF0000U)
15441#define DDRPHY_DTPR3_tDLLK_SHIFT (16U)
15442/*! tDLLK - DLL locking time
15443 */
15444#define DDRPHY_DTPR3_tDLLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_tDLLK_SHIFT)) & DDRPHY_DTPR3_tDLLK_MASK)
15445#define DDRPHY_DTPR3_tCCD_MASK (0x1C000000U)
15446#define DDRPHY_DTPR3_tCCD_SHIFT (26U)
15447/*! tCCD - Read to read and write to write command delay
15448 */
15449#define DDRPHY_DTPR3_tCCD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_tCCD_SHIFT)) & DDRPHY_DTPR3_tCCD_MASK)
15450#define DDRPHY_DTPR3_tOFDx_MASK (0xE0000000U)
15451#define DDRPHY_DTPR3_tOFDx_SHIFT (29U)
15452/*! tOFDx - ODT turn-off delay extension
15453 */
15454#define DDRPHY_DTPR3_tOFDx(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR3_tOFDx_SHIFT)) & DDRPHY_DTPR3_tOFDx_MASK)
15455/*! @} */
15456
15457/*! @name DTPR4 - DRAM Timing Parameters Register 4 */
15458/*! @{ */
15459#define DDRPHY_DTPR4_tXP_MASK (0x1FU)
15460#define DDRPHY_DTPR4_tXP_SHIFT (0U)
15461/*! tXP - Power down exit delay
15462 */
15463#define DDRPHY_DTPR4_tXP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_tXP_SHIFT)) & DDRPHY_DTPR4_tXP_MASK)
15464#define DDRPHY_DTPR4_RESERVED_7_5_MASK (0xE0U)
15465#define DDRPHY_DTPR4_RESERVED_7_5_SHIFT (5U)
15466/*! RESERVED_7_5 - Reserved. Return zeroes on reads.
15467 */
15468#define DDRPHY_DTPR4_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_RESERVED_7_5_SHIFT)) & DDRPHY_DTPR4_RESERVED_7_5_MASK)
15469#define DDRPHY_DTPR4_tWLO_MASK (0x3F00U)
15470#define DDRPHY_DTPR4_tWLO_SHIFT (8U)
15471/*! tWLO - Write leveling output delay
15472 */
15473#define DDRPHY_DTPR4_tWLO(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_tWLO_SHIFT)) & DDRPHY_DTPR4_tWLO_MASK)
15474#define DDRPHY_DTPR4_RESERVED_15_14_MASK (0xC000U)
15475#define DDRPHY_DTPR4_RESERVED_15_14_SHIFT (14U)
15476/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
15477 */
15478#define DDRPHY_DTPR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_RESERVED_15_14_SHIFT)) & DDRPHY_DTPR4_RESERVED_15_14_MASK)
15479#define DDRPHY_DTPR4_tRFC_MASK (0x3FF0000U)
15480#define DDRPHY_DTPR4_tRFC_SHIFT (16U)
15481/*! tRFC - Refresh-to-Refresh
15482 */
15483#define DDRPHY_DTPR4_tRFC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_tRFC_SHIFT)) & DDRPHY_DTPR4_tRFC_MASK)
15484#define DDRPHY_DTPR4_RESERVED_27_26_MASK (0xC000000U)
15485#define DDRPHY_DTPR4_RESERVED_27_26_SHIFT (26U)
15486/*! RESERVED_27_26 - Reserved. Return zeroes on reads.
15487 */
15488#define DDRPHY_DTPR4_RESERVED_27_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_RESERVED_27_26_SHIFT)) & DDRPHY_DTPR4_RESERVED_27_26_MASK)
15489#define DDRPHY_DTPR4_tAOND_tAOFD_MASK (0x30000000U)
15490#define DDRPHY_DTPR4_tAOND_tAOFD_SHIFT (28U)
15491/*! tAOND_tAOFD - ODT turn-on/turn-off delays (DDR2 only)
15492 */
15493#define DDRPHY_DTPR4_tAOND_tAOFD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_tAOND_tAOFD_SHIFT)) & DDRPHY_DTPR4_tAOND_tAOFD_MASK)
15494#define DDRPHY_DTPR4_RESERVED_31_30_MASK (0xC0000000U)
15495#define DDRPHY_DTPR4_RESERVED_31_30_SHIFT (30U)
15496/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
15497 */
15498#define DDRPHY_DTPR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR4_RESERVED_31_30_SHIFT)) & DDRPHY_DTPR4_RESERVED_31_30_MASK)
15499/*! @} */
15500
15501/*! @name DTPR5 - DRAM Timing Parameters Register 5 */
15502/*! @{ */
15503#define DDRPHY_DTPR5_tWTR_MASK (0x1FU)
15504#define DDRPHY_DTPR5_tWTR_SHIFT (0U)
15505/*! tWTR - Internal write to read command delay
15506 */
15507#define DDRPHY_DTPR5_tWTR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR5_tWTR_SHIFT)) & DDRPHY_DTPR5_tWTR_MASK)
15508#define DDRPHY_DTPR5_RESERVED_7_5_MASK (0xE0U)
15509#define DDRPHY_DTPR5_RESERVED_7_5_SHIFT (5U)
15510/*! RESERVED_7_5 - Reserved. Return zeroes on reads.
15511 */
15512#define DDRPHY_DTPR5_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR5_RESERVED_7_5_SHIFT)) & DDRPHY_DTPR5_RESERVED_7_5_MASK)
15513#define DDRPHY_DTPR5_tRCD_MASK (0x7F00U)
15514#define DDRPHY_DTPR5_tRCD_SHIFT (8U)
15515/*! tRCD - Activate to read or write delay
15516 */
15517#define DDRPHY_DTPR5_tRCD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR5_tRCD_SHIFT)) & DDRPHY_DTPR5_tRCD_MASK)
15518#define DDRPHY_DTPR5_RESERVED_15_MASK (0x8000U)
15519#define DDRPHY_DTPR5_RESERVED_15_SHIFT (15U)
15520/*! RESERVED_15 - Reserved. Return zeroes on reads.
15521 */
15522#define DDRPHY_DTPR5_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR5_RESERVED_15_SHIFT)) & DDRPHY_DTPR5_RESERVED_15_MASK)
15523#define DDRPHY_DTPR5_tRC_MASK (0xFF0000U)
15524#define DDRPHY_DTPR5_tRC_SHIFT (16U)
15525/*! tRC - Activate to activate command delay (same bank)
15526 */
15527#define DDRPHY_DTPR5_tRC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR5_tRC_SHIFT)) & DDRPHY_DTPR5_tRC_MASK)
15528#define DDRPHY_DTPR5_RESERVED_31_24_MASK (0xFF000000U)
15529#define DDRPHY_DTPR5_RESERVED_31_24_SHIFT (24U)
15530/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
15531 */
15532#define DDRPHY_DTPR5_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR5_RESERVED_31_24_SHIFT)) & DDRPHY_DTPR5_RESERVED_31_24_MASK)
15533/*! @} */
15534
15535/*! @name DTPR6 - DRAM Timing Parameters Register 6 */
15536/*! @{ */
15537#define DDRPHY_DTPR6_PUBRL_MASK (0x3FU)
15538#define DDRPHY_DTPR6_PUBRL_SHIFT (0U)
15539/*! PUBRL - Read Latency
15540 */
15541#define DDRPHY_DTPR6_PUBRL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR6_PUBRL_SHIFT)) & DDRPHY_DTPR6_PUBRL_MASK)
15542#define DDRPHY_DTPR6_RESERVED_7_6_MASK (0xC0U)
15543#define DDRPHY_DTPR6_RESERVED_7_6_SHIFT (6U)
15544/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
15545 */
15546#define DDRPHY_DTPR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR6_RESERVED_7_6_SHIFT)) & DDRPHY_DTPR6_RESERVED_7_6_MASK)
15547#define DDRPHY_DTPR6_PUBWL_MASK (0x3F00U)
15548#define DDRPHY_DTPR6_PUBWL_SHIFT (8U)
15549/*! PUBWL - Write Latency
15550 */
15551#define DDRPHY_DTPR6_PUBWL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR6_PUBWL_SHIFT)) & DDRPHY_DTPR6_PUBWL_MASK)
15552#define DDRPHY_DTPR6_RESERVED_29_14_MASK (0x3FFFC000U)
15553#define DDRPHY_DTPR6_RESERVED_29_14_SHIFT (14U)
15554/*! RESERVED_29_14 - Reserved. Return zeroes on reads.
15555 */
15556#define DDRPHY_DTPR6_RESERVED_29_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR6_RESERVED_29_14_SHIFT)) & DDRPHY_DTPR6_RESERVED_29_14_MASK)
15557#define DDRPHY_DTPR6_PUBRLEN_MASK (0x40000000U)
15558#define DDRPHY_DTPR6_PUBRLEN_SHIFT (30U)
15559/*! PUBRLEN - PUB Read Latency Enable
15560 */
15561#define DDRPHY_DTPR6_PUBRLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR6_PUBRLEN_SHIFT)) & DDRPHY_DTPR6_PUBRLEN_MASK)
15562#define DDRPHY_DTPR6_PUBWLEN_MASK (0x80000000U)
15563#define DDRPHY_DTPR6_PUBWLEN_SHIFT (31U)
15564/*! PUBWLEN - PUB Write Latency Enable
15565 */
15566#define DDRPHY_DTPR6_PUBWLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTPR6_PUBWLEN_SHIFT)) & DDRPHY_DTPR6_PUBWLEN_MASK)
15567/*! @} */
15568
15569/*! @name RDIMMGCR0 - RDIMM General Configuration Register 0 */
15570/*! @{ */
15571#define DDRPHY_RDIMMGCR0_RDIMM_MASK (0x1U)
15572#define DDRPHY_RDIMMGCR0_RDIMM_SHIFT (0U)
15573/*! RDIMM - Registered DIMM
15574 */
15575#define DDRPHY_RDIMMGCR0_RDIMM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RDIMM_SHIFT)) & DDRPHY_RDIMMGCR0_RDIMM_MASK)
15576#define DDRPHY_RDIMMGCR0_ERRNOREG_MASK (0x2U)
15577#define DDRPHY_RDIMMGCR0_ERRNOREG_SHIFT (1U)
15578/*! ERRNOREG - Parity Error No Registering
15579 */
15580#define DDRPHY_RDIMMGCR0_ERRNOREG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_ERRNOREG_SHIFT)) & DDRPHY_RDIMMGCR0_ERRNOREG_MASK)
15581#define DDRPHY_RDIMMGCR0_SOPERR_MASK (0x4U)
15582#define DDRPHY_RDIMMGCR0_SOPERR_SHIFT (2U)
15583/*! SOPERR - Stop on Parity Error
15584 */
15585#define DDRPHY_RDIMMGCR0_SOPERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_SOPERR_SHIFT)) & DDRPHY_RDIMMGCR0_SOPERR_MASK)
15586#define DDRPHY_RDIMMGCR0_RESERVED_3_MASK (0x8U)
15587#define DDRPHY_RDIMMGCR0_RESERVED_3_SHIFT (3U)
15588/*! RESERVED_3 - Reserved. Return zeroes on reads.
15589 */
15590#define DDRPHY_RDIMMGCR0_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RESERVED_3_SHIFT)) & DDRPHY_RDIMMGCR0_RESERVED_3_MASK)
15591#define DDRPHY_RDIMMGCR0_RNKMRREN_MASK (0x10U)
15592#define DDRPHY_RDIMMGCR0_RNKMRREN_SHIFT (4U)
15593/*! RNKMRREN - Rank Mirror Enable.
15594 */
15595#define DDRPHY_RDIMMGCR0_RNKMRREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RNKMRREN_SHIFT)) & DDRPHY_RDIMMGCR0_RNKMRREN_MASK)
15596#define DDRPHY_RDIMMGCR0_RNKMRREN_RSVD_MASK (0xE0U)
15597#define DDRPHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT (5U)
15598/*! RNKMRREN_RSVD - Reserved. Return zeroes on reads.
15599 */
15600#define DDRPHY_RDIMMGCR0_RNKMRREN_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT)) & DDRPHY_RDIMMGCR0_RNKMRREN_RSVD_MASK)
15601#define DDRPHY_RDIMMGCR0_RESERVED_16_8_MASK (0x1FF00U)
15602#define DDRPHY_RDIMMGCR0_RESERVED_16_8_SHIFT (8U)
15603/*! RESERVED_16_8 - Reserved. Return zeroes on reads.
15604 */
15605#define DDRPHY_RDIMMGCR0_RESERVED_16_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RESERVED_16_8_SHIFT)) & DDRPHY_RDIMMGCR0_RESERVED_16_8_MASK)
15606#define DDRPHY_RDIMMGCR0_PARINIOM_MASK (0x20000U)
15607#define DDRPHY_RDIMMGCR0_PARINIOM_SHIFT (17U)
15608/*! PARINIOM - PAR_IN I/O Mode
15609 */
15610#define DDRPHY_RDIMMGCR0_PARINIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_PARINIOM_SHIFT)) & DDRPHY_RDIMMGCR0_PARINIOM_MASK)
15611#define DDRPHY_RDIMMGCR0_LRDIMM_MASK (0x40000U)
15612#define DDRPHY_RDIMMGCR0_LRDIMM_SHIFT (18U)
15613/*! LRDIMM - Load Reduced DIMM
15614 */
15615#define DDRPHY_RDIMMGCR0_LRDIMM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_LRDIMM_SHIFT)) & DDRPHY_RDIMMGCR0_LRDIMM_MASK)
15616#define DDRPHY_RDIMMGCR0_ERROUTODT_MASK (0x80000U)
15617#define DDRPHY_RDIMMGCR0_ERROUTODT_SHIFT (19U)
15618/*! ERROUTODT - ERROUT# On-Die Termination
15619 */
15620#define DDRPHY_RDIMMGCR0_ERROUTODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_ERROUTODT_SHIFT)) & DDRPHY_RDIMMGCR0_ERROUTODT_MASK)
15621#define DDRPHY_RDIMMGCR0_RESERVED_20_MASK (0x100000U)
15622#define DDRPHY_RDIMMGCR0_RESERVED_20_SHIFT (20U)
15623/*! RESERVED_20 - Reserved. Return zeroes on reads.
15624 */
15625#define DDRPHY_RDIMMGCR0_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RESERVED_20_SHIFT)) & DDRPHY_RDIMMGCR0_RESERVED_20_MASK)
15626#define DDRPHY_RDIMMGCR0_ERROUTPDR_MASK (0x200000U)
15627#define DDRPHY_RDIMMGCR0_ERROUTPDR_SHIFT (21U)
15628/*! ERROUTPDR - ERROUT# Power Down Receiver
15629 */
15630#define DDRPHY_RDIMMGCR0_ERROUTPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_ERROUTPDR_SHIFT)) & DDRPHY_RDIMMGCR0_ERROUTPDR_MASK)
15631#define DDRPHY_RDIMMGCR0_ERROUTIOM_MASK (0x400000U)
15632#define DDRPHY_RDIMMGCR0_ERROUTIOM_SHIFT (22U)
15633/*! ERROUTIOM - ERROUT# I/O Mode
15634 */
15635#define DDRPHY_RDIMMGCR0_ERROUTIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_ERROUTIOM_SHIFT)) & DDRPHY_RDIMMGCR0_ERROUTIOM_MASK)
15636#define DDRPHY_RDIMMGCR0_ERROUTOE_MASK (0x800000U)
15637#define DDRPHY_RDIMMGCR0_ERROUTOE_SHIFT (23U)
15638/*! ERROUTOE - ERROUT# Output Enable
15639 */
15640#define DDRPHY_RDIMMGCR0_ERROUTOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_ERROUTOE_SHIFT)) & DDRPHY_RDIMMGCR0_ERROUTOE_MASK)
15641#define DDRPHY_RDIMMGCR0_RESERVED_26_24_MASK (0x7000000U)
15642#define DDRPHY_RDIMMGCR0_RESERVED_26_24_SHIFT (24U)
15643/*! RESERVED_26_24 - Reserved. Return zeroes on reads.
15644 */
15645#define DDRPHY_RDIMMGCR0_RESERVED_26_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RESERVED_26_24_SHIFT)) & DDRPHY_RDIMMGCR0_RESERVED_26_24_MASK)
15646#define DDRPHY_RDIMMGCR0_RDIMMIOM_MASK (0x8000000U)
15647#define DDRPHY_RDIMMGCR0_RDIMMIOM_SHIFT (27U)
15648/*! RDIMMIOM - RDIMM Outputs I/O Mode
15649 */
15650#define DDRPHY_RDIMMGCR0_RDIMMIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RDIMMIOM_SHIFT)) & DDRPHY_RDIMMGCR0_RDIMMIOM_MASK)
15651#define DDRPHY_RDIMMGCR0_RESERVED_29_28_MASK (0x30000000U)
15652#define DDRPHY_RDIMMGCR0_RESERVED_29_28_SHIFT (28U)
15653/*! RESERVED_29_28 - Reserved. Return zeroes on reads.
15654 */
15655#define DDRPHY_RDIMMGCR0_RESERVED_29_28(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RESERVED_29_28_SHIFT)) & DDRPHY_RDIMMGCR0_RESERVED_29_28_MASK)
15656#define DDRPHY_RDIMMGCR0_QCSEN_MASK (0x40000000U)
15657#define DDRPHY_RDIMMGCR0_QCSEN_SHIFT (30U)
15658/*! QCSEN - RDMIMM Quad CS Enable
15659 */
15660#define DDRPHY_RDIMMGCR0_QCSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_QCSEN_SHIFT)) & DDRPHY_RDIMMGCR0_QCSEN_MASK)
15661#define DDRPHY_RDIMMGCR0_RESERVED_31_MASK (0x80000000U)
15662#define DDRPHY_RDIMMGCR0_RESERVED_31_SHIFT (31U)
15663/*! RESERVED_31 - Reserved. Return zeroes on reads.
15664 */
15665#define DDRPHY_RDIMMGCR0_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR0_RESERVED_31_SHIFT)) & DDRPHY_RDIMMGCR0_RESERVED_31_MASK)
15666/*! @} */
15667
15668/*! @name RDIMMGCR1 - RDIMM General Configuration Register 1 */
15669/*! @{ */
15670#define DDRPHY_RDIMMGCR1_tBCSTAB_MASK (0x3FFFU)
15671#define DDRPHY_RDIMMGCR1_tBCSTAB_SHIFT (0U)
15672/*! tBCSTAB - Stabilization time
15673 */
15674#define DDRPHY_RDIMMGCR1_tBCSTAB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_tBCSTAB_SHIFT)) & DDRPHY_RDIMMGCR1_tBCSTAB_MASK)
15675#define DDRPHY_RDIMMGCR1_RESERVED_15_14_MASK (0xC000U)
15676#define DDRPHY_RDIMMGCR1_RESERVED_15_14_SHIFT (14U)
15677/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
15678 */
15679#define DDRPHY_RDIMMGCR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_RESERVED_15_14_SHIFT)) & DDRPHY_RDIMMGCR1_RESERVED_15_14_MASK)
15680#define DDRPHY_RDIMMGCR1_tBCMRD_MASK (0x70000U)
15681#define DDRPHY_RDIMMGCR1_tBCMRD_SHIFT (16U)
15682/*! tBCMRD - Command word to command word programming delay
15683 */
15684#define DDRPHY_RDIMMGCR1_tBCMRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_tBCMRD_SHIFT)) & DDRPHY_RDIMMGCR1_tBCMRD_MASK)
15685#define DDRPHY_RDIMMGCR1_RESERVED_19_MASK (0x80000U)
15686#define DDRPHY_RDIMMGCR1_RESERVED_19_SHIFT (19U)
15687/*! RESERVED_19 - Reserved. Return zeroes on reads.
15688 */
15689#define DDRPHY_RDIMMGCR1_RESERVED_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_RESERVED_19_SHIFT)) & DDRPHY_RDIMMGCR1_RESERVED_19_MASK)
15690#define DDRPHY_RDIMMGCR1_tBCMRD_L_MASK (0x700000U)
15691#define DDRPHY_RDIMMGCR1_tBCMRD_L_SHIFT (20U)
15692/*! tBCMRD_L - Command word to command word programming delay
15693 */
15694#define DDRPHY_RDIMMGCR1_tBCMRD_L(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_tBCMRD_L_SHIFT)) & DDRPHY_RDIMMGCR1_tBCMRD_L_MASK)
15695#define DDRPHY_RDIMMGCR1_RESERVED_23_MASK (0x800000U)
15696#define DDRPHY_RDIMMGCR1_RESERVED_23_SHIFT (23U)
15697/*! RESERVED_23 - Reserved. Return zeroes on reads.
15698 */
15699#define DDRPHY_RDIMMGCR1_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_RESERVED_23_SHIFT)) & DDRPHY_RDIMMGCR1_RESERVED_23_MASK)
15700#define DDRPHY_RDIMMGCR1_tBCMRD_L2_MASK (0x7000000U)
15701#define DDRPHY_RDIMMGCR1_tBCMRD_L2_SHIFT (24U)
15702/*! tBCMRD_L2 - Command word to command word programming delay
15703 */
15704#define DDRPHY_RDIMMGCR1_tBCMRD_L2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_tBCMRD_L2_SHIFT)) & DDRPHY_RDIMMGCR1_tBCMRD_L2_MASK)
15705#define DDRPHY_RDIMMGCR1_RESERVED_27_MASK (0x8000000U)
15706#define DDRPHY_RDIMMGCR1_RESERVED_27_SHIFT (27U)
15707/*! RESERVED_27 - Reserved. Return zeroes on reads.
15708 */
15709#define DDRPHY_RDIMMGCR1_RESERVED_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_RESERVED_27_SHIFT)) & DDRPHY_RDIMMGCR1_RESERVED_27_MASK)
15710#define DDRPHY_RDIMMGCR1_A17BID_MASK (0x10000000U)
15711#define DDRPHY_RDIMMGCR1_A17BID_SHIFT (28U)
15712/*! A17BID - Address [17] B-side Inversion Disable
15713 */
15714#define DDRPHY_RDIMMGCR1_A17BID(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_A17BID_SHIFT)) & DDRPHY_RDIMMGCR1_A17BID_MASK)
15715#define DDRPHY_RDIMMGCR1_RESERVED_31_29_MASK (0xE0000000U)
15716#define DDRPHY_RDIMMGCR1_RESERVED_31_29_SHIFT (29U)
15717/*! RESERVED_31_29 - Reserved. Return zeroes on reads.
15718 */
15719#define DDRPHY_RDIMMGCR1_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR1_RESERVED_31_29_SHIFT)) & DDRPHY_RDIMMGCR1_RESERVED_31_29_MASK)
15720/*! @} */
15721
15722/*! @name RDIMMGCR2 - RDIMM General Configuration Register 2 */
15723/*! @{ */
15724#define DDRPHY_RDIMMGCR2_CRINIT_MASK (0xFFFFFFFFU)
15725#define DDRPHY_RDIMMGCR2_CRINIT_SHIFT (0U)
15726/*! CRINIT - Control Registers Initialization Enable
15727 */
15728#define DDRPHY_RDIMMGCR2_CRINIT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMGCR2_CRINIT_SHIFT)) & DDRPHY_RDIMMGCR2_CRINIT_MASK)
15729/*! @} */
15730
15731/*! @name RDIMMCR0 - RDIMM Control Register 0 */
15732/*! @{ */
15733#define DDRPHY_RDIMMCR0_RC0_MASK (0xFU)
15734#define DDRPHY_RDIMMCR0_RC0_SHIFT (0U)
15735/*! RC0 - DDR4/DDR3 Control Word 0 (Global Features Control Word)
15736 */
15737#define DDRPHY_RDIMMCR0_RC0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC0_SHIFT)) & DDRPHY_RDIMMCR0_RC0_MASK)
15738#define DDRPHY_RDIMMCR0_RC1_MASK (0xF0U)
15739#define DDRPHY_RDIMMCR0_RC1_SHIFT (4U)
15740/*! RC1 - DDR4/DDR3 Control Word 1 (Clock Driver Enable Control Word)
15741 */
15742#define DDRPHY_RDIMMCR0_RC1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC1_SHIFT)) & DDRPHY_RDIMMCR0_RC1_MASK)
15743#define DDRPHY_RDIMMCR0_RC2_MASK (0xF00U)
15744#define DDRPHY_RDIMMCR0_RC2_SHIFT (8U)
15745/*! RC2 - DDR4 Control Word 2 (Timing and IBT Control Word) / DDR3 Control Word 2 (Timing Control Word)
15746 */
15747#define DDRPHY_RDIMMCR0_RC2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC2_SHIFT)) & DDRPHY_RDIMMCR0_RC2_MASK)
15748#define DDRPHY_RDIMMCR0_RC3_MASK (0xF000U)
15749#define DDRPHY_RDIMMCR0_RC3_SHIFT (12U)
15750/*! RC3 - DDR4 Control Word 3 (CA and CS Signals Driver Characteristics Control Word) / DDR3 Control
15751 * Word 3 (Command/Address Signals Driver Characteristrics Control Word)
15752 */
15753#define DDRPHY_RDIMMCR0_RC3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC3_SHIFT)) & DDRPHY_RDIMMCR0_RC3_MASK)
15754#define DDRPHY_RDIMMCR0_RC4_MASK (0xF0000U)
15755#define DDRPHY_RDIMMCR0_RC4_SHIFT (16U)
15756/*! RC4 - DDR4 Control Word 4 (ODT and CKE Signals Driver Characteristics Control Word) / DDR3
15757 * Control Word 4 (Control Signals Driver Characteristics Control Word)
15758 */
15759#define DDRPHY_RDIMMCR0_RC4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC4_SHIFT)) & DDRPHY_RDIMMCR0_RC4_MASK)
15760#define DDRPHY_RDIMMCR0_RC5_MASK (0xF00000U)
15761#define DDRPHY_RDIMMCR0_RC5_SHIFT (20U)
15762/*! RC5 - DDR4/DDR3 Control Word 5 (CK Driver Characteristics Control Word)
15763 */
15764#define DDRPHY_RDIMMCR0_RC5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC5_SHIFT)) & DDRPHY_RDIMMCR0_RC5_MASK)
15765#define DDRPHY_RDIMMCR0_RC6_MASK (0xF000000U)
15766#define DDRPHY_RDIMMCR0_RC6_SHIFT (24U)
15767/*! RC6 - DDR4 Control Word 6 (Comman space Control Word) / DDR3 Reserved
15768 */
15769#define DDRPHY_RDIMMCR0_RC6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC6_SHIFT)) & DDRPHY_RDIMMCR0_RC6_MASK)
15770#define DDRPHY_RDIMMCR0_RC7_MASK (0xF0000000U)
15771#define DDRPHY_RDIMMCR0_RC7_SHIFT (28U)
15772/*! RC7 - DDR4/DDR3 Control Word 7
15773 */
15774#define DDRPHY_RDIMMCR0_RC7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR0_RC7_SHIFT)) & DDRPHY_RDIMMCR0_RC7_MASK)
15775/*! @} */
15776
15777/*! @name RDIMMCR1 - RDIMM Control Register 1 */
15778/*! @{ */
15779#define DDRPHY_RDIMMCR1_RC8_MASK (0xFU)
15780#define DDRPHY_RDIMMCR1_RC8_SHIFT (0U)
15781/*! RC8 - DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8
15782 * (Additional Input Bus Termination Setting Control Word)
15783 */
15784#define DDRPHY_RDIMMCR1_RC8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC8_SHIFT)) & DDRPHY_RDIMMCR1_RC8_MASK)
15785#define DDRPHY_RDIMMCR1_RC9_MASK (0xF0U)
15786#define DDRPHY_RDIMMCR1_RC9_SHIFT (4U)
15787/*! RC9 - DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)
15788 */
15789#define DDRPHY_RDIMMCR1_RC9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC9_SHIFT)) & DDRPHY_RDIMMCR1_RC9_MASK)
15790#define DDRPHY_RDIMMCR1_RC10_MASK (0xF00U)
15791#define DDRPHY_RDIMMCR1_RC10_SHIFT (8U)
15792/*! RC10 - DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)
15793 */
15794#define DDRPHY_RDIMMCR1_RC10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC10_SHIFT)) & DDRPHY_RDIMMCR1_RC10_MASK)
15795#define DDRPHY_RDIMMCR1_RC11_MASK (0xF000U)
15796#define DDRPHY_RDIMMCR1_RC11_SHIFT (12U)
15797/*! RC11 - DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3
15798 * Control Word 11 (Operation Voltage VDD Control Word)
15799 */
15800#define DDRPHY_RDIMMCR1_RC11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC11_SHIFT)) & DDRPHY_RDIMMCR1_RC11_MASK)
15801#define DDRPHY_RDIMMCR1_RC12_MASK (0xF0000U)
15802#define DDRPHY_RDIMMCR1_RC12_SHIFT (16U)
15803/*! RC12 - DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved
15804 */
15805#define DDRPHY_RDIMMCR1_RC12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC12_SHIFT)) & DDRPHY_RDIMMCR1_RC12_MASK)
15806#define DDRPHY_RDIMMCR1_RC13_MASK (0xF00000U)
15807#define DDRPHY_RDIMMCR1_RC13_SHIFT (20U)
15808/*! RC13 - DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved
15809 */
15810#define DDRPHY_RDIMMCR1_RC13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC13_SHIFT)) & DDRPHY_RDIMMCR1_RC13_MASK)
15811#define DDRPHY_RDIMMCR1_RC14_MASK (0xF000000U)
15812#define DDRPHY_RDIMMCR1_RC14_SHIFT (24U)
15813/*! RC14 - DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved
15814 */
15815#define DDRPHY_RDIMMCR1_RC14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC14_SHIFT)) & DDRPHY_RDIMMCR1_RC14_MASK)
15816#define DDRPHY_RDIMMCR1_RC15_MASK (0xF0000000U)
15817#define DDRPHY_RDIMMCR1_RC15_SHIFT (28U)
15818/*! RC15 - Control Word 15
15819 */
15820#define DDRPHY_RDIMMCR1_RC15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR1_RC15_SHIFT)) & DDRPHY_RDIMMCR1_RC15_MASK)
15821/*! @} */
15822
15823/*! @name RDIMMCR2 - RDIMM Control Register 2 */
15824/*! @{ */
15825#define DDRPHY_RDIMMCR2_RC1X_MASK (0xFFU)
15826#define DDRPHY_RDIMMCR2_RC1X_SHIFT (0U)
15827/*! RC1X - Control Word RC1X
15828 */
15829#define DDRPHY_RDIMMCR2_RC1X(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR2_RC1X_SHIFT)) & DDRPHY_RDIMMCR2_RC1X_MASK)
15830#define DDRPHY_RDIMMCR2_RC2X_MASK (0xFF00U)
15831#define DDRPHY_RDIMMCR2_RC2X_SHIFT (8U)
15832/*! RC2X - Control Word RC2X
15833 */
15834#define DDRPHY_RDIMMCR2_RC2X(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR2_RC2X_SHIFT)) & DDRPHY_RDIMMCR2_RC2X_MASK)
15835#define DDRPHY_RDIMMCR2_RC3X_MASK (0xFF0000U)
15836#define DDRPHY_RDIMMCR2_RC3X_SHIFT (16U)
15837/*! RC3X - Control Word RC3X
15838 */
15839#define DDRPHY_RDIMMCR2_RC3X(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR2_RC3X_SHIFT)) & DDRPHY_RDIMMCR2_RC3X_MASK)
15840#define DDRPHY_RDIMMCR2_RC4X_MASK (0xFF000000U)
15841#define DDRPHY_RDIMMCR2_RC4X_SHIFT (24U)
15842/*! RC4X - Control Word RC4X
15843 */
15844#define DDRPHY_RDIMMCR2_RC4X(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR2_RC4X_SHIFT)) & DDRPHY_RDIMMCR2_RC4X_MASK)
15845/*! @} */
15846
15847/*! @name RDIMMCR3 - RDIMM Control Register 3 */
15848/*! @{ */
15849#define DDRPHY_RDIMMCR3_RC5X_MASK (0xFFU)
15850#define DDRPHY_RDIMMCR3_RC5X_SHIFT (0U)
15851/*! RC5X - Control Word RC5X
15852 */
15853#define DDRPHY_RDIMMCR3_RC5X(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR3_RC5X_SHIFT)) & DDRPHY_RDIMMCR3_RC5X_MASK)
15854#define DDRPHY_RDIMMCR3_RC6X_MASK (0xFF00U)
15855#define DDRPHY_RDIMMCR3_RC6X_SHIFT (8U)
15856/*! RC6X - Control Word RC6X
15857 */
15858#define DDRPHY_RDIMMCR3_RC6X(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR3_RC6X_SHIFT)) & DDRPHY_RDIMMCR3_RC6X_MASK)
15859#define DDRPHY_RDIMMCR3_RC7X_MASK (0xFF0000U)
15860#define DDRPHY_RDIMMCR3_RC7X_SHIFT (16U)
15861/*! RC7X - Control Word RC7X
15862 */
15863#define DDRPHY_RDIMMCR3_RC7X(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR3_RC7X_SHIFT)) & DDRPHY_RDIMMCR3_RC7X_MASK)
15864#define DDRPHY_RDIMMCR3_RC8X_MASK (0xFF000000U)
15865#define DDRPHY_RDIMMCR3_RC8X_SHIFT (24U)
15866/*! RC8X - Control Word RC8X
15867 */
15868#define DDRPHY_RDIMMCR3_RC8X(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR3_RC8X_SHIFT)) & DDRPHY_RDIMMCR3_RC8X_MASK)
15869/*! @} */
15870
15871/*! @name RDIMMCR4 - RDIMM Control Register 4 */
15872/*! @{ */
15873#define DDRPHY_RDIMMCR4_RC9X_MASK (0xFFU)
15874#define DDRPHY_RDIMMCR4_RC9X_SHIFT (0U)
15875/*! RC9X - Control Word RC9X
15876 */
15877#define DDRPHY_RDIMMCR4_RC9X(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR4_RC9X_SHIFT)) & DDRPHY_RDIMMCR4_RC9X_MASK)
15878#define DDRPHY_RDIMMCR4_RCAX_MASK (0xFF00U)
15879#define DDRPHY_RDIMMCR4_RCAX_SHIFT (8U)
15880/*! RCAX - Control Word RC10X
15881 */
15882#define DDRPHY_RDIMMCR4_RCAX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR4_RCAX_SHIFT)) & DDRPHY_RDIMMCR4_RCAX_MASK)
15883#define DDRPHY_RDIMMCR4_RCBX_MASK (0xFF0000U)
15884#define DDRPHY_RDIMMCR4_RCBX_SHIFT (16U)
15885/*! RCBX - Control Word RC11X
15886 */
15887#define DDRPHY_RDIMMCR4_RCBX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR4_RCBX_SHIFT)) & DDRPHY_RDIMMCR4_RCBX_MASK)
15888#define DDRPHY_RDIMMCR4_RCXX_MASK (0xFF000000U)
15889#define DDRPHY_RDIMMCR4_RCXX_SHIFT (24U)
15890/*! RCXX - Reserved for future use.
15891 */
15892#define DDRPHY_RDIMMCR4_RCXX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RDIMMCR4_RCXX_SHIFT)) & DDRPHY_RDIMMCR4_RCXX_MASK)
15893/*! @} */
15894
15895/*! @name SCHCR0 - Scheduler Command Register 0 */
15896/*! @{ */
15897#define DDRPHY_SCHCR0_SCHTRIG_MASK (0xFU)
15898#define DDRPHY_SCHCR0_SCHTRIG_SHIFT (0U)
15899/*! SCHTRIG - Mode Register Command Trigger
15900 */
15901#define DDRPHY_SCHCR0_SCHTRIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR0_SCHTRIG_SHIFT)) & DDRPHY_SCHCR0_SCHTRIG_MASK)
15902#define DDRPHY_SCHCR0_CMD_MASK (0xF0U)
15903#define DDRPHY_SCHCR0_CMD_SHIFT (4U)
15904/*! CMD - Specifies the Command to be issued
15905 */
15906#define DDRPHY_SCHCR0_CMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR0_CMD_SHIFT)) & DDRPHY_SCHCR0_CMD_MASK)
15907#define DDRPHY_SCHCR0_SP_CMD_MASK (0xF00U)
15908#define DDRPHY_SCHCR0_SP_CMD_SHIFT (8U)
15909/*! SP_CMD - Special Command codes
15910 */
15911#define DDRPHY_SCHCR0_SP_CMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR0_SP_CMD_SHIFT)) & DDRPHY_SCHCR0_SP_CMD_MASK)
15912#define DDRPHY_SCHCR0_RESERVED_15_12_MASK (0xF000U)
15913#define DDRPHY_SCHCR0_RESERVED_15_12_SHIFT (12U)
15914/*! RESERVED_15_12 - Reserved. Return zeroes on reads.
15915 */
15916#define DDRPHY_SCHCR0_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR0_RESERVED_15_12_SHIFT)) & DDRPHY_SCHCR0_RESERVED_15_12_MASK)
15917#define DDRPHY_SCHCR0_SCHDQV_MASK (0x1FF0000U)
15918#define DDRPHY_SCHCR0_SCHDQV_SHIFT (16U)
15919/*! SCHDQV - Scheduler Command DQ Value
15920 */
15921#define DDRPHY_SCHCR0_SCHDQV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR0_SCHDQV_SHIFT)) & DDRPHY_SCHCR0_SCHDQV_MASK)
15922#define DDRPHY_SCHCR0_RESERVED_31_25_MASK (0xFE000000U)
15923#define DDRPHY_SCHCR0_RESERVED_31_25_SHIFT (25U)
15924/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
15925 */
15926#define DDRPHY_SCHCR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR0_RESERVED_31_25_SHIFT)) & DDRPHY_SCHCR0_RESERVED_31_25_MASK)
15927/*! @} */
15928
15929/*! @name SCHCR1 - Scheduler Command Register 1 */
15930/*! @{ */
15931#define DDRPHY_SCHCR1_RESERVED_1_0_MASK (0x3U)
15932#define DDRPHY_SCHCR1_RESERVED_1_0_SHIFT (0U)
15933/*! RESERVED_1_0 - Reserved. Return zeroes on reads.
15934 */
15935#define DDRPHY_SCHCR1_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_RESERVED_1_0_SHIFT)) & DDRPHY_SCHCR1_RESERVED_1_0_MASK)
15936#define DDRPHY_SCHCR1_ALLRANK_MASK (0x4U)
15937#define DDRPHY_SCHCR1_ALLRANK_SHIFT (2U)
15938/*! ALLRANK - All Ranks enabled
15939 */
15940#define DDRPHY_SCHCR1_ALLRANK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_ALLRANK_SHIFT)) & DDRPHY_SCHCR1_ALLRANK_MASK)
15941#define DDRPHY_SCHCR1_RESERVED_3_MASK (0x8U)
15942#define DDRPHY_SCHCR1_RESERVED_3_SHIFT (3U)
15943/*! RESERVED_3 - Reserved. Return zeroes on reads.
15944 */
15945#define DDRPHY_SCHCR1_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_RESERVED_3_SHIFT)) & DDRPHY_SCHCR1_RESERVED_3_MASK)
15946#define DDRPHY_SCHCR1_SCBK_MASK (0x30U)
15947#define DDRPHY_SCHCR1_SCBK_SHIFT (4U)
15948/*! SCBK - Scheduler Command Bank Address
15949 */
15950#define DDRPHY_SCHCR1_SCBK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_SCBK_SHIFT)) & DDRPHY_SCHCR1_SCBK_MASK)
15951#define DDRPHY_SCHCR1_SCBG_MASK (0xC0U)
15952#define DDRPHY_SCHCR1_SCBG_SHIFT (6U)
15953/*! SCBG - Scheduler Command Bank Group
15954 */
15955#define DDRPHY_SCHCR1_SCBG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_SCBG_SHIFT)) & DDRPHY_SCHCR1_SCBG_MASK)
15956#define DDRPHY_SCHCR1_SCADDR_MASK (0xFFFFF00U)
15957#define DDRPHY_SCHCR1_SCADDR_SHIFT (8U)
15958/*! SCADDR - Scheduler Command Address Specifies the value to be driven on the address bus.
15959 */
15960#define DDRPHY_SCHCR1_SCADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_SCADDR_SHIFT)) & DDRPHY_SCHCR1_SCADDR_MASK)
15961#define DDRPHY_SCHCR1_SCRNK_MASK (0xF0000000U)
15962#define DDRPHY_SCHCR1_SCRNK_SHIFT (28U)
15963/*! SCRNK - Scheduler Rank Address
15964 */
15965#define DDRPHY_SCHCR1_SCRNK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_SCHCR1_SCRNK_SHIFT)) & DDRPHY_SCHCR1_SCRNK_MASK)
15966/*! @} */
15967
15968/*! @name MR0 - LPDDR4 Mode Register 0 */
15969/*! @{ */
15970#define DDRPHY_MR0_RSVD_2_0_MASK (0x7U)
15971#define DDRPHY_MR0_RSVD_2_0_SHIFT (0U)
15972/*! RSVD_2_0 - Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
15973 */
15974#define DDRPHY_MR0_RSVD_2_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR0_RSVD_2_0_SHIFT)) & DDRPHY_MR0_RSVD_2_0_MASK)
15975#define DDRPHY_MR0_RZQI_MASK (0x18U)
15976#define DDRPHY_MR0_RZQI_SHIFT (3U)
15977/*! RZQI - Built-in Self-Test for RZQ
15978 */
15979#define DDRPHY_MR0_RZQI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR0_RZQI_SHIFT)) & DDRPHY_MR0_RZQI_MASK)
15980#define DDRPHY_MR0_RSVD_6_5_MASK (0x60U)
15981#define DDRPHY_MR0_RSVD_6_5_SHIFT (5U)
15982/*! RSVD_6_5 - Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
15983 */
15984#define DDRPHY_MR0_RSVD_6_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR0_RSVD_6_5_SHIFT)) & DDRPHY_MR0_RSVD_6_5_MASK)
15985#define DDRPHY_MR0_CATR_MASK (0x80U)
15986#define DDRPHY_MR0_CATR_SHIFT (7U)
15987/*! CATR - CA Terminating Rank
15988 */
15989#define DDRPHY_MR0_CATR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR0_CATR_SHIFT)) & DDRPHY_MR0_CATR_MASK)
15990#define DDRPHY_MR0_RSVD_15_8_MASK (0xFF00U)
15991#define DDRPHY_MR0_RSVD_15_8_SHIFT (8U)
15992/*! RSVD_15_8 - Reserved. Return zeroes on reads.
15993 */
15994#define DDRPHY_MR0_RSVD_15_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR0_RSVD_15_8_SHIFT)) & DDRPHY_MR0_RSVD_15_8_MASK)
15995#define DDRPHY_MR0_RESERVED_31_16_MASK (0xFFFF0000U)
15996#define DDRPHY_MR0_RESERVED_31_16_SHIFT (16U)
15997/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
15998 */
15999#define DDRPHY_MR0_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR0_RESERVED_31_16_SHIFT)) & DDRPHY_MR0_RESERVED_31_16_MASK)
16000/*! @} */
16001
16002/*! @name MR1 - LPDDR4 Mode Register 1 */
16003/*! @{ */
16004#define DDRPHY_MR1_BL_MASK (0x3U)
16005#define DDRPHY_MR1_BL_SHIFT (0U)
16006/*! BL - Burst Length
16007 */
16008#define DDRPHY_MR1_BL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_BL_SHIFT)) & DDRPHY_MR1_BL_MASK)
16009#define DDRPHY_MR1_WRPRE_MASK (0x4U)
16010#define DDRPHY_MR1_WRPRE_SHIFT (2U)
16011/*! WRPRE - Write Preamble Length
16012 */
16013#define DDRPHY_MR1_WRPRE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_WRPRE_SHIFT)) & DDRPHY_MR1_WRPRE_MASK)
16014#define DDRPHY_MR1_RDPRE_MASK (0x8U)
16015#define DDRPHY_MR1_RDPRE_SHIFT (3U)
16016/*! RDPRE - Read Preamble Length
16017 */
16018#define DDRPHY_MR1_RDPRE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_RDPRE_SHIFT)) & DDRPHY_MR1_RDPRE_MASK)
16019#define DDRPHY_MR1_nWR_MASK (0x70U)
16020#define DDRPHY_MR1_nWR_SHIFT (4U)
16021/*! nWR - Write-recovery for auto-precharge command
16022 */
16023#define DDRPHY_MR1_nWR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_nWR_SHIFT)) & DDRPHY_MR1_nWR_MASK)
16024#define DDRPHY_MR1_RDPST_MASK (0x80U)
16025#define DDRPHY_MR1_RDPST_SHIFT (7U)
16026/*! RDPST - Read Postamble Length
16027 */
16028#define DDRPHY_MR1_RDPST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_RDPST_SHIFT)) & DDRPHY_MR1_RDPST_MASK)
16029#define DDRPHY_MR1_RSVD_MASK (0xFF00U)
16030#define DDRPHY_MR1_RSVD_SHIFT (8U)
16031/*! RSVD - Reserved. Return zeroes on reads.
16032 */
16033#define DDRPHY_MR1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_RSVD_SHIFT)) & DDRPHY_MR1_RSVD_MASK)
16034#define DDRPHY_MR1_RESERVED_31_16_MASK (0xFFFF0000U)
16035#define DDRPHY_MR1_RESERVED_31_16_SHIFT (16U)
16036/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
16037 */
16038#define DDRPHY_MR1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR1_RESERVED_31_16_SHIFT)) & DDRPHY_MR1_RESERVED_31_16_MASK)
16039/*! @} */
16040
16041/*! @name MR2 - LPDDR4 Mode Register 2 */
16042/*! @{ */
16043#define DDRPHY_MR2_RL_MASK (0x7U)
16044#define DDRPHY_MR2_RL_SHIFT (0U)
16045/*! RL - Read Latency
16046 */
16047#define DDRPHY_MR2_RL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR2_RL_SHIFT)) & DDRPHY_MR2_RL_MASK)
16048#define DDRPHY_MR2_WL_MASK (0x38U)
16049#define DDRPHY_MR2_WL_SHIFT (3U)
16050/*! WL - Write Latency
16051 */
16052#define DDRPHY_MR2_WL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR2_WL_SHIFT)) & DDRPHY_MR2_WL_MASK)
16053#define DDRPHY_MR2_WLS_MASK (0x40U)
16054#define DDRPHY_MR2_WLS_SHIFT (6U)
16055/*! WLS - Write Latency Set
16056 */
16057#define DDRPHY_MR2_WLS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR2_WLS_SHIFT)) & DDRPHY_MR2_WLS_MASK)
16058#define DDRPHY_MR2_WRL_MASK (0x80U)
16059#define DDRPHY_MR2_WRL_SHIFT (7U)
16060/*! WRL - Write Leveling
16061 */
16062#define DDRPHY_MR2_WRL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR2_WRL_SHIFT)) & DDRPHY_MR2_WRL_MASK)
16063#define DDRPHY_MR2_RSVD_MASK (0xFF00U)
16064#define DDRPHY_MR2_RSVD_SHIFT (8U)
16065/*! RSVD - Reserved. Return zeroes on reads.
16066 */
16067#define DDRPHY_MR2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR2_RSVD_SHIFT)) & DDRPHY_MR2_RSVD_MASK)
16068#define DDRPHY_MR2_RESERVED_31_16_MASK (0xFFFF0000U)
16069#define DDRPHY_MR2_RESERVED_31_16_SHIFT (16U)
16070/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
16071 */
16072#define DDRPHY_MR2_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR2_RESERVED_31_16_SHIFT)) & DDRPHY_MR2_RESERVED_31_16_MASK)
16073/*! @} */
16074
16075/*! @name MR3 - LPDDR4 Mode Register 3 */
16076/*! @{ */
16077#define DDRPHY_MR3_PUCAL_MASK (0x1U)
16078#define DDRPHY_MR3_PUCAL_SHIFT (0U)
16079/*! PUCAL - Pull-up Calibration Point
16080 */
16081#define DDRPHY_MR3_PUCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_PUCAL_SHIFT)) & DDRPHY_MR3_PUCAL_MASK)
16082#define DDRPHY_MR3_WRPST_MASK (0x2U)
16083#define DDRPHY_MR3_WRPST_SHIFT (1U)
16084/*! WRPST - Write Postamble Length
16085 */
16086#define DDRPHY_MR3_WRPST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_WRPST_SHIFT)) & DDRPHY_MR3_WRPST_MASK)
16087#define DDRPHY_MR3_RSVD_MASK (0x4U)
16088#define DDRPHY_MR3_RSVD_SHIFT (2U)
16089/*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
16090 */
16091#define DDRPHY_MR3_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_RSVD_SHIFT)) & DDRPHY_MR3_RSVD_MASK)
16092#define DDRPHY_MR3_PDDS_MASK (0x38U)
16093#define DDRPHY_MR3_PDDS_SHIFT (3U)
16094/*! PDDS - Pull-down Drive Strength
16095 */
16096#define DDRPHY_MR3_PDDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_PDDS_SHIFT)) & DDRPHY_MR3_PDDS_MASK)
16097#define DDRPHY_MR3_DBIRD_MASK (0x40U)
16098#define DDRPHY_MR3_DBIRD_SHIFT (6U)
16099/*! DBIRD - DBI-Read Enable
16100 */
16101#define DDRPHY_MR3_DBIRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_DBIRD_SHIFT)) & DDRPHY_MR3_DBIRD_MASK)
16102#define DDRPHY_MR3_DBIWR_MASK (0x80U)
16103#define DDRPHY_MR3_DBIWR_SHIFT (7U)
16104/*! DBIWR - DBI-Write Enable
16105 */
16106#define DDRPHY_MR3_DBIWR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_DBIWR_SHIFT)) & DDRPHY_MR3_DBIWR_MASK)
16107#define DDRPHY_MR3_RESERVED_31_8_MASK (0xFFFFFF00U)
16108#define DDRPHY_MR3_RESERVED_31_8_SHIFT (8U)
16109/*! RESERVED_31_8 - Reserved. Return zeroes on reads.
16110 */
16111#define DDRPHY_MR3_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR3_RESERVED_31_8_SHIFT)) & DDRPHY_MR3_RESERVED_31_8_MASK)
16112/*! @} */
16113
16114/*! @name MR4 - LPDDR4 Mode Register 4 */
16115/*! @{ */
16116#define DDRPHY_MR4_RSVD_MASK (0xFFU)
16117#define DDRPHY_MR4_RSVD_SHIFT (0U)
16118/*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
16119 */
16120#define DDRPHY_MR4_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR4_RSVD_SHIFT)) & DDRPHY_MR4_RSVD_MASK)
16121#define DDRPHY_MR4_RESERVED_31_8_MASK (0xFFFFFF00U)
16122#define DDRPHY_MR4_RESERVED_31_8_SHIFT (8U)
16123/*! RESERVED_31_8 - Reserved. Return zeroes on reads.
16124 */
16125#define DDRPHY_MR4_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR4_RESERVED_31_8_SHIFT)) & DDRPHY_MR4_RESERVED_31_8_MASK)
16126/*! @} */
16127
16128/*! @name MR5 - LPDDR4 Mode Register 5 */
16129/*! @{ */
16130#define DDRPHY_MR5_RSVD_MASK (0xFFU)
16131#define DDRPHY_MR5_RSVD_SHIFT (0U)
16132/*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
16133 */
16134#define DDRPHY_MR5_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR5_RSVD_SHIFT)) & DDRPHY_MR5_RSVD_MASK)
16135#define DDRPHY_MR5_RESERVED_31_8_MASK (0xFFFFFF00U)
16136#define DDRPHY_MR5_RESERVED_31_8_SHIFT (8U)
16137/*! RESERVED_31_8 - Reserved. Return zeroes on reads.
16138 */
16139#define DDRPHY_MR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR5_RESERVED_31_8_SHIFT)) & DDRPHY_MR5_RESERVED_31_8_MASK)
16140/*! @} */
16141
16142/*! @name MR6 - LPDDR4 Mode Register 6 */
16143/*! @{ */
16144#define DDRPHY_MR6_RSVD_MASK (0xFFU)
16145#define DDRPHY_MR6_RSVD_SHIFT (0U)
16146/*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
16147 */
16148#define DDRPHY_MR6_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR6_RSVD_SHIFT)) & DDRPHY_MR6_RSVD_MASK)
16149#define DDRPHY_MR6_RESERVED_31_8_MASK (0xFFFFFF00U)
16150#define DDRPHY_MR6_RESERVED_31_8_SHIFT (8U)
16151/*! RESERVED_31_8 - Reserved. Return zeroes on reads.
16152 */
16153#define DDRPHY_MR6_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR6_RESERVED_31_8_SHIFT)) & DDRPHY_MR6_RESERVED_31_8_MASK)
16154/*! @} */
16155
16156/*! @name MR7 - LPDDR4 Mode Register 7 */
16157/*! @{ */
16158#define DDRPHY_MR7_RSVD_MASK (0xFFU)
16159#define DDRPHY_MR7_RSVD_SHIFT (0U)
16160/*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
16161 */
16162#define DDRPHY_MR7_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR7_RSVD_SHIFT)) & DDRPHY_MR7_RSVD_MASK)
16163#define DDRPHY_MR7_RESERVED_31_8_MASK (0xFFFFFF00U)
16164#define DDRPHY_MR7_RESERVED_31_8_SHIFT (8U)
16165/*! RESERVED_31_8 - Reserved. Return zeroes on reads.
16166 */
16167#define DDRPHY_MR7_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR7_RESERVED_31_8_SHIFT)) & DDRPHY_MR7_RESERVED_31_8_MASK)
16168/*! @} */
16169
16170/*! @name MR11 - LPDDR4 Mode Register 11 */
16171/*! @{ */
16172#define DDRPHY_MR11_DQODT_MASK (0x7U)
16173#define DDRPHY_MR11_DQODT_SHIFT (0U)
16174/*! DQODT - DQ Bus Receiver On-Die-Termination
16175 */
16176#define DDRPHY_MR11_DQODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR11_DQODT_SHIFT)) & DDRPHY_MR11_DQODT_MASK)
16177#define DDRPHY_MR11_RSVD_3_MASK (0x8U)
16178#define DDRPHY_MR11_RSVD_3_SHIFT (3U)
16179/*! RSVD_3 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
16180 */
16181#define DDRPHY_MR11_RSVD_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR11_RSVD_3_SHIFT)) & DDRPHY_MR11_RSVD_3_MASK)
16182#define DDRPHY_MR11_CAODT_MASK (0x70U)
16183#define DDRPHY_MR11_CAODT_SHIFT (4U)
16184/*! CAODT - CA Bus Receiver On-Die-Termination
16185 */
16186#define DDRPHY_MR11_CAODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR11_CAODT_SHIFT)) & DDRPHY_MR11_CAODT_MASK)
16187#define DDRPHY_MR11_RSVD_7_MASK (0x80U)
16188#define DDRPHY_MR11_RSVD_7_SHIFT (7U)
16189/*! RSVD_7 - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
16190 */
16191#define DDRPHY_MR11_RSVD_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR11_RSVD_7_SHIFT)) & DDRPHY_MR11_RSVD_7_MASK)
16192#define DDRPHY_MR11_RSVD_15_8_MASK (0xFF00U)
16193#define DDRPHY_MR11_RSVD_15_8_SHIFT (8U)
16194/*! RSVD_15_8 - Reserved. Return zeroes on reads.
16195 */
16196#define DDRPHY_MR11_RSVD_15_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR11_RSVD_15_8_SHIFT)) & DDRPHY_MR11_RSVD_15_8_MASK)
16197#define DDRPHY_MR11_RESERVED_31_16_MASK (0xFFFF0000U)
16198#define DDRPHY_MR11_RESERVED_31_16_SHIFT (16U)
16199/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
16200 */
16201#define DDRPHY_MR11_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR11_RESERVED_31_16_SHIFT)) & DDRPHY_MR11_RESERVED_31_16_MASK)
16202/*! @} */
16203
16204/*! @name MR12 - LPDDR4 Mode Register 12 */
16205/*! @{ */
16206#define DDRPHY_MR12_VREF_CA_MASK (0x3FU)
16207#define DDRPHY_MR12_VREF_CA_SHIFT (0U)
16208/*! VREF_CA - Controls the VREF(ca) levels for Frequency-Set-Point[1:0].
16209 */
16210#define DDRPHY_MR12_VREF_CA(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR12_VREF_CA_SHIFT)) & DDRPHY_MR12_VREF_CA_MASK)
16211#define DDRPHY_MR12_VR_CA_MASK (0x40U)
16212#define DDRPHY_MR12_VR_CA_SHIFT (6U)
16213/*! VR_CA - VREF_CA Range Select.
16214 */
16215#define DDRPHY_MR12_VR_CA(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR12_VR_CA_SHIFT)) & DDRPHY_MR12_VR_CA_MASK)
16216#define DDRPHY_MR12_RSVD_MASK (0x80U)
16217#define DDRPHY_MR12_RSVD_SHIFT (7U)
16218/*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
16219 */
16220#define DDRPHY_MR12_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR12_RSVD_SHIFT)) & DDRPHY_MR12_RSVD_MASK)
16221#define DDRPHY_MR12_RESERVED_31_8_MASK (0xFFFFFF00U)
16222#define DDRPHY_MR12_RESERVED_31_8_SHIFT (8U)
16223/*! RESERVED_31_8 - Reserved. Return zeroes on reads.
16224 */
16225#define DDRPHY_MR12_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR12_RESERVED_31_8_SHIFT)) & DDRPHY_MR12_RESERVED_31_8_MASK)
16226/*! @} */
16227
16228/*! @name MR13 - LPDDR4 Mode Register 13 */
16229/*! @{ */
16230#define DDRPHY_MR13_CBT_MASK (0x1U)
16231#define DDRPHY_MR13_CBT_SHIFT (0U)
16232/*! CBT - Command Bus Training
16233 */
16234#define DDRPHY_MR13_CBT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_CBT_SHIFT)) & DDRPHY_MR13_CBT_MASK)
16235#define DDRPHY_MR13_RPT_MASK (0x2U)
16236#define DDRPHY_MR13_RPT_SHIFT (1U)
16237/*! RPT - Read Preamble Training Mode
16238 */
16239#define DDRPHY_MR13_RPT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_RPT_SHIFT)) & DDRPHY_MR13_RPT_MASK)
16240#define DDRPHY_MR13_VRO_MASK (0x4U)
16241#define DDRPHY_MR13_VRO_SHIFT (2U)
16242/*! VRO - VREF Output
16243 */
16244#define DDRPHY_MR13_VRO(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_VRO_SHIFT)) & DDRPHY_MR13_VRO_MASK)
16245#define DDRPHY_MR13_VRCG_MASK (0x8U)
16246#define DDRPHY_MR13_VRCG_SHIFT (3U)
16247/*! VRCG - VREF Current Generator
16248 */
16249#define DDRPHY_MR13_VRCG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_VRCG_SHIFT)) & DDRPHY_MR13_VRCG_MASK)
16250#define DDRPHY_MR13_RRO_MASK (0x10U)
16251#define DDRPHY_MR13_RRO_SHIFT (4U)
16252/*! RRO - Refresh Rate Option
16253 */
16254#define DDRPHY_MR13_RRO(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_RRO_SHIFT)) & DDRPHY_MR13_RRO_MASK)
16255#define DDRPHY_MR13_DMD_MASK (0x20U)
16256#define DDRPHY_MR13_DMD_SHIFT (5U)
16257/*! DMD - Data Mask Enable
16258 */
16259#define DDRPHY_MR13_DMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_DMD_SHIFT)) & DDRPHY_MR13_DMD_MASK)
16260#define DDRPHY_MR13_FSPWR_MASK (0x40U)
16261#define DDRPHY_MR13_FSPWR_SHIFT (6U)
16262/*! FSPWR - Frequency Set Point Write Enable
16263 */
16264#define DDRPHY_MR13_FSPWR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_FSPWR_SHIFT)) & DDRPHY_MR13_FSPWR_MASK)
16265#define DDRPHY_MR13_FSPOP_MASK (0x80U)
16266#define DDRPHY_MR13_FSPOP_SHIFT (7U)
16267/*! FSPOP - Frequency Set Point Operation Mode
16268 */
16269#define DDRPHY_MR13_FSPOP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_FSPOP_SHIFT)) & DDRPHY_MR13_FSPOP_MASK)
16270#define DDRPHY_MR13_RESERVED_31_8_MASK (0xFFFFFF00U)
16271#define DDRPHY_MR13_RESERVED_31_8_SHIFT (8U)
16272/*! RESERVED_31_8 - Reserved. Return zeroes on reads.
16273 */
16274#define DDRPHY_MR13_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR13_RESERVED_31_8_SHIFT)) & DDRPHY_MR13_RESERVED_31_8_MASK)
16275/*! @} */
16276
16277/*! @name MR14 - LPDDR4 Mode Register 14 */
16278/*! @{ */
16279#define DDRPHY_MR14_VREF_DQ_MASK (0x3FU)
16280#define DDRPHY_MR14_VREF_DQ_SHIFT (0U)
16281/*! VREF_DQ - Reserved. Return zeroes on reads.
16282 */
16283#define DDRPHY_MR14_VREF_DQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR14_VREF_DQ_SHIFT)) & DDRPHY_MR14_VREF_DQ_MASK)
16284#define DDRPHY_MR14_VR_DQ_MASK (0x40U)
16285#define DDRPHY_MR14_VR_DQ_SHIFT (6U)
16286/*! VR_DQ - VREFDQ Range Selects.
16287 */
16288#define DDRPHY_MR14_VR_DQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR14_VR_DQ_SHIFT)) & DDRPHY_MR14_VR_DQ_MASK)
16289#define DDRPHY_MR14_RSVD_MASK (0x80U)
16290#define DDRPHY_MR14_RSVD_SHIFT (7U)
16291/*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
16292 */
16293#define DDRPHY_MR14_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR14_RSVD_SHIFT)) & DDRPHY_MR14_RSVD_MASK)
16294#define DDRPHY_MR14_RESERVED_31_8_MASK (0xFFFFFF00U)
16295#define DDRPHY_MR14_RESERVED_31_8_SHIFT (8U)
16296/*! RESERVED_31_8 - Reserved. Return zeroes on reads.
16297 */
16298#define DDRPHY_MR14_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR14_RESERVED_31_8_SHIFT)) & DDRPHY_MR14_RESERVED_31_8_MASK)
16299/*! @} */
16300
16301/*! @name MR22 - LPDDR4 Mode Register 22 */
16302/*! @{ */
16303#define DDRPHY_MR22_CODT_MASK (0x7U)
16304#define DDRPHY_MR22_CODT_SHIFT (0U)
16305/*! CODT - Controller ODT value for VOH calibration.
16306 */
16307#define DDRPHY_MR22_CODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR22_CODT_SHIFT)) & DDRPHY_MR22_CODT_MASK)
16308#define DDRPHY_MR22_ODTE_CK_MASK (0x8U)
16309#define DDRPHY_MR22_ODTE_CK_SHIFT (3U)
16310/*! ODTE_CK - ODT CK override.
16311 */
16312#define DDRPHY_MR22_ODTE_CK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR22_ODTE_CK_SHIFT)) & DDRPHY_MR22_ODTE_CK_MASK)
16313#define DDRPHY_MR22_ODTE_CS_MASK (0x10U)
16314#define DDRPHY_MR22_ODTE_CS_SHIFT (4U)
16315/*! ODTE_CS - ODT CS override.
16316 */
16317#define DDRPHY_MR22_ODTE_CS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR22_ODTE_CS_SHIFT)) & DDRPHY_MR22_ODTE_CS_MASK)
16318#define DDRPHY_MR22_ODTD_CA_MASK (0x20U)
16319#define DDRPHY_MR22_ODTD_CA_SHIFT (5U)
16320/*! ODTD_CA - CA ODT termination disable.
16321 */
16322#define DDRPHY_MR22_ODTD_CA(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR22_ODTD_CA_SHIFT)) & DDRPHY_MR22_ODTD_CA_MASK)
16323#define DDRPHY_MR22_RSVD_MASK (0xC0U)
16324#define DDRPHY_MR22_RSVD_SHIFT (6U)
16325/*! RSVD - These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
16326 */
16327#define DDRPHY_MR22_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR22_RSVD_SHIFT)) & DDRPHY_MR22_RSVD_MASK)
16328#define DDRPHY_MR22_RESERVED_31_8_MASK (0xFFFFFF00U)
16329#define DDRPHY_MR22_RESERVED_31_8_SHIFT (8U)
16330/*! RESERVED_31_8 - Reserved. Return zeroes on reads.
16331 */
16332#define DDRPHY_MR22_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_MR22_RESERVED_31_8_SHIFT)) & DDRPHY_MR22_RESERVED_31_8_MASK)
16333/*! @} */
16334
16335/*! @name DTCR0 - Data Training Configuration Register 0 */
16336/*! @{ */
16337#define DDRPHY_DTCR0_DTRPTN_MASK (0xFU)
16338#define DDRPHY_DTCR0_DTRPTN_SHIFT (0U)
16339/*! DTRPTN - Data Training Repeat Number
16340 */
16341#define DDRPHY_DTCR0_DTRPTN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTRPTN_SHIFT)) & DDRPHY_DTCR0_DTRPTN_MASK)
16342#define DDRPHY_DTCR0_MPCWEYE_MASK (0x10U)
16343#define DDRPHY_DTCR0_MPCWEYE_SHIFT (4U)
16344/*! MPCWEYE - WEYE Training using MPC FIFO Commands
16345 */
16346#define DDRPHY_DTCR0_MPCWEYE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_MPCWEYE_SHIFT)) & DDRPHY_DTCR0_MPCWEYE_MASK)
16347#define DDRPHY_DTCR0_RESERVED_5_MASK (0x20U)
16348#define DDRPHY_DTCR0_RESERVED_5_SHIFT (5U)
16349/*! RESERVED_5 - Reserved. Return zeroes on reads.
16350 */
16351#define DDRPHY_DTCR0_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_RESERVED_5_SHIFT)) & DDRPHY_DTCR0_RESERVED_5_MASK)
16352#define DDRPHY_DTCR0_DTMPR_MASK (0x40U)
16353#define DDRPHY_DTCR0_DTMPR_SHIFT (6U)
16354/*! DTMPR - Data Training Using MPR
16355 */
16356#define DDRPHY_DTCR0_DTMPR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTMPR_SHIFT)) & DDRPHY_DTCR0_DTMPR_MASK)
16357#define DDRPHY_DTCR0_DTCMPD_MASK (0x80U)
16358#define DDRPHY_DTCR0_DTCMPD_SHIFT (7U)
16359/*! DTCMPD - Data Training Compare Data
16360 */
16361#define DDRPHY_DTCR0_DTCMPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTCMPD_SHIFT)) & DDRPHY_DTCR0_DTCMPD_MASK)
16362#define DDRPHY_DTCR0_RFSHEN_MASK (0xF00U)
16363#define DDRPHY_DTCR0_RFSHEN_SHIFT (8U)
16364/*! RFSHEN - Refreshes Issued During Entry to Training
16365 */
16366#define DDRPHY_DTCR0_RFSHEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_RFSHEN_SHIFT)) & DDRPHY_DTCR0_RFSHEN_MASK)
16367#define DDRPHY_DTCR0_DTWBDDM_MASK (0x1000U)
16368#define DDRPHY_DTCR0_DTWBDDM_SHIFT (12U)
16369/*! DTWBDDM - Data Training Write Bit Deskew Data Mask
16370 */
16371#define DDRPHY_DTCR0_DTWBDDM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTWBDDM_SHIFT)) & DDRPHY_DTCR0_DTWBDDM_MASK)
16372#define DDRPHY_DTCR0_DTBDC_MASK (0x2000U)
16373#define DDRPHY_DTCR0_DTBDC_SHIFT (13U)
16374/*! DTBDC - Data Training Bit Deskew Centering
16375 */
16376#define DDRPHY_DTCR0_DTBDC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTBDC_SHIFT)) & DDRPHY_DTCR0_DTBDC_MASK)
16377#define DDRPHY_DTCR0_DTRDBITR_MASK (0xC000U)
16378#define DDRPHY_DTCR0_DTRDBITR_SHIFT (14U)
16379/*! DTRDBITR - Data Training read DBI deskewing configuration
16380 */
16381#define DDRPHY_DTCR0_DTRDBITR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTRDBITR_SHIFT)) & DDRPHY_DTCR0_DTRDBITR_MASK)
16382#define DDRPHY_DTCR0_DTDBS_MASK (0xF0000U)
16383#define DDRPHY_DTCR0_DTDBS_SHIFT (16U)
16384/*! DTDBS - Data Training Debug Byte Select
16385 */
16386#define DDRPHY_DTCR0_DTDBS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTDBS_SHIFT)) & DDRPHY_DTCR0_DTDBS_MASK)
16387#define DDRPHY_DTCR0_DTDEN_MASK (0x100000U)
16388#define DDRPHY_DTCR0_DTDEN_SHIFT (20U)
16389/*! DTDEN - Data Training Debug Enable
16390 */
16391#define DDRPHY_DTCR0_DTDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTDEN_SHIFT)) & DDRPHY_DTCR0_DTDEN_MASK)
16392#define DDRPHY_DTCR0_DTDSTP_MASK (0x200000U)
16393#define DDRPHY_DTCR0_DTDSTP_SHIFT (21U)
16394/*! DTDSTP - Data Training Debug Step
16395 */
16396#define DDRPHY_DTCR0_DTDSTP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTDSTP_SHIFT)) & DDRPHY_DTCR0_DTDSTP_MASK)
16397#define DDRPHY_DTCR0_DTEXD_MASK (0x400000U)
16398#define DDRPHY_DTCR0_DTEXD_SHIFT (22U)
16399/*! DTEXD - Data Training Extended Write DQS
16400 */
16401#define DDRPHY_DTCR0_DTEXD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTEXD_SHIFT)) & DDRPHY_DTCR0_DTEXD_MASK)
16402#define DDRPHY_DTCR0_DTEXG_MASK (0x800000U)
16403#define DDRPHY_DTCR0_DTEXG_SHIFT (23U)
16404/*! DTEXG - Data Training with Early/Extended Gate
16405 */
16406#define DDRPHY_DTCR0_DTEXG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTEXG_SHIFT)) & DDRPHY_DTCR0_DTEXG_MASK)
16407#define DDRPHY_DTCR0_DTDRS_MASK (0x3000000U)
16408#define DDRPHY_DTCR0_DTDRS_SHIFT (24U)
16409/*! DTDRS - Data Training Debug Rank Select
16410 */
16411#define DDRPHY_DTCR0_DTDRS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_DTDRS_SHIFT)) & DDRPHY_DTCR0_DTDRS_MASK)
16412#define DDRPHY_DTCR0_RESERVED_27_26_MASK (0xC000000U)
16413#define DDRPHY_DTCR0_RESERVED_27_26_SHIFT (26U)
16414/*! RESERVED_27_26 - Reserved. Return zeroes on reads.
16415 */
16416#define DDRPHY_DTCR0_RESERVED_27_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_RESERVED_27_26_SHIFT)) & DDRPHY_DTCR0_RESERVED_27_26_MASK)
16417#define DDRPHY_DTCR0_RFSHDT_MASK (0xF0000000U)
16418#define DDRPHY_DTCR0_RFSHDT_SHIFT (28U)
16419/*! RFSHDT - Refresh During Training
16420 */
16421#define DDRPHY_DTCR0_RFSHDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR0_RFSHDT_SHIFT)) & DDRPHY_DTCR0_RFSHDT_MASK)
16422/*! @} */
16423
16424/*! @name DTCR1 - Data Training Configuration Register 1 */
16425/*! @{ */
16426#define DDRPHY_DTCR1_BSTEN_MASK (0x1U)
16427#define DDRPHY_DTCR1_BSTEN_SHIFT (0U)
16428/*! BSTEN - Basic Gate Training Enable
16429 */
16430#define DDRPHY_DTCR1_BSTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_BSTEN_SHIFT)) & DDRPHY_DTCR1_BSTEN_MASK)
16431#define DDRPHY_DTCR1_RDLVLEN_MASK (0x2U)
16432#define DDRPHY_DTCR1_RDLVLEN_SHIFT (1U)
16433/*! RDLVLEN - Read Leveling Enable
16434 */
16435#define DDRPHY_DTCR1_RDLVLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RDLVLEN_SHIFT)) & DDRPHY_DTCR1_RDLVLEN_MASK)
16436#define DDRPHY_DTCR1_RDPRMVL_TRN_MASK (0x4U)
16437#define DDRPHY_DTCR1_RDPRMVL_TRN_SHIFT (2U)
16438/*! RDPRMVL_TRN - Read Preamble Training enable
16439 */
16440#define DDRPHY_DTCR1_RDPRMVL_TRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RDPRMVL_TRN_SHIFT)) & DDRPHY_DTCR1_RDPRMVL_TRN_MASK)
16441#define DDRPHY_DTCR1_RESERVED_3_MASK (0x8U)
16442#define DDRPHY_DTCR1_RESERVED_3_SHIFT (3U)
16443/*! RESERVED_3 - Reserved. Return zeroes on reads.
16444 */
16445#define DDRPHY_DTCR1_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RESERVED_3_SHIFT)) & DDRPHY_DTCR1_RESERVED_3_MASK)
16446#define DDRPHY_DTCR1_RDLVLGS_MASK (0x70U)
16447#define DDRPHY_DTCR1_RDLVLGS_SHIFT (4U)
16448/*! RDLVLGS - Read Leveling Gate Shift
16449 */
16450#define DDRPHY_DTCR1_RDLVLGS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RDLVLGS_SHIFT)) & DDRPHY_DTCR1_RDLVLGS_MASK)
16451#define DDRPHY_DTCR1_RESERVED_7_MASK (0x80U)
16452#define DDRPHY_DTCR1_RESERVED_7_SHIFT (7U)
16453/*! RESERVED_7 - Reserved. Return zeroes on reads.
16454 */
16455#define DDRPHY_DTCR1_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RESERVED_7_SHIFT)) & DDRPHY_DTCR1_RESERVED_7_MASK)
16456#define DDRPHY_DTCR1_RDLVLGDIFF_MASK (0x700U)
16457#define DDRPHY_DTCR1_RDLVLGDIFF_SHIFT (8U)
16458/*! RDLVLGDIFF - Read Leveling Gate Sampling Difference
16459 */
16460#define DDRPHY_DTCR1_RDLVLGDIFF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RDLVLGDIFF_SHIFT)) & DDRPHY_DTCR1_RDLVLGDIFF_MASK)
16461#define DDRPHY_DTCR1_RESERVED_11_MASK (0x800U)
16462#define DDRPHY_DTCR1_RESERVED_11_SHIFT (11U)
16463/*! RESERVED_11 - Reserved. Return zeroes on reads.
16464 */
16465#define DDRPHY_DTCR1_RESERVED_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RESERVED_11_SHIFT)) & DDRPHY_DTCR1_RESERVED_11_MASK)
16466#define DDRPHY_DTCR1_DTRANK_MASK (0x3000U)
16467#define DDRPHY_DTCR1_DTRANK_SHIFT (12U)
16468/*! DTRANK - Data Training Rank
16469 */
16470#define DDRPHY_DTCR1_DTRANK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_DTRANK_SHIFT)) & DDRPHY_DTCR1_DTRANK_MASK)
16471#define DDRPHY_DTCR1_RESERVED_15_14_MASK (0xC000U)
16472#define DDRPHY_DTCR1_RESERVED_15_14_SHIFT (14U)
16473/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
16474 */
16475#define DDRPHY_DTCR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RESERVED_15_14_SHIFT)) & DDRPHY_DTCR1_RESERVED_15_14_MASK)
16476#define DDRPHY_DTCR1_RANKEN_MASK (0x10000U)
16477#define DDRPHY_DTCR1_RANKEN_SHIFT (16U)
16478/*! RANKEN - Rank Enable.
16479 */
16480#define DDRPHY_DTCR1_RANKEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RANKEN_SHIFT)) & DDRPHY_DTCR1_RANKEN_MASK)
16481#define DDRPHY_DTCR1_RANKEN_RSVD_MASK (0xFFFE0000U)
16482#define DDRPHY_DTCR1_RANKEN_RSVD_SHIFT (17U)
16483/*! RANKEN_RSVD - Rank Enable.
16484 */
16485#define DDRPHY_DTCR1_RANKEN_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTCR1_RANKEN_RSVD_SHIFT)) & DDRPHY_DTCR1_RANKEN_RSVD_MASK)
16486/*! @} */
16487
16488/*! @name DTAR0 - Data Training Address Register 0 */
16489/*! @{ */
16490#define DDRPHY_DTAR0_DTROW_MASK (0x3FFFFU)
16491#define DDRPHY_DTAR0_DTROW_SHIFT (0U)
16492/*! DTROW - Data Training Row Address
16493 */
16494#define DDRPHY_DTAR0_DTROW(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR0_DTROW_SHIFT)) & DDRPHY_DTAR0_DTROW_MASK)
16495#define DDRPHY_DTAR0_RESERVED_19_18_MASK (0xC0000U)
16496#define DDRPHY_DTAR0_RESERVED_19_18_SHIFT (18U)
16497/*! RESERVED_19_18 - Reserved. Return zeroes on reads.
16498 */
16499#define DDRPHY_DTAR0_RESERVED_19_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR0_RESERVED_19_18_SHIFT)) & DDRPHY_DTAR0_RESERVED_19_18_MASK)
16500#define DDRPHY_DTAR0_DTBGBK0_MASK (0xF00000U)
16501#define DDRPHY_DTAR0_DTBGBK0_SHIFT (20U)
16502/*! DTBGBK0 - Data Training Bank Group and Bank Address
16503 */
16504#define DDRPHY_DTAR0_DTBGBK0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR0_DTBGBK0_SHIFT)) & DDRPHY_DTAR0_DTBGBK0_MASK)
16505#define DDRPHY_DTAR0_DTBGBK1_MASK (0xF000000U)
16506#define DDRPHY_DTAR0_DTBGBK1_SHIFT (24U)
16507/*! DTBGBK1 - Data Training Bank Group and Bank Address
16508 */
16509#define DDRPHY_DTAR0_DTBGBK1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR0_DTBGBK1_SHIFT)) & DDRPHY_DTAR0_DTBGBK1_MASK)
16510#define DDRPHY_DTAR0_MPRLOC_MASK (0x30000000U)
16511#define DDRPHY_DTAR0_MPRLOC_SHIFT (28U)
16512/*! MPRLOC - Multi-Purpose Register (MPR) Location
16513 */
16514#define DDRPHY_DTAR0_MPRLOC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR0_MPRLOC_SHIFT)) & DDRPHY_DTAR0_MPRLOC_MASK)
16515#define DDRPHY_DTAR0_RESERVED_31_30_MASK (0xC0000000U)
16516#define DDRPHY_DTAR0_RESERVED_31_30_SHIFT (30U)
16517/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
16518 */
16519#define DDRPHY_DTAR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR0_RESERVED_31_30_SHIFT)) & DDRPHY_DTAR0_RESERVED_31_30_MASK)
16520/*! @} */
16521
16522/*! @name DTAR1 - Data Training Address Register 1 */
16523/*! @{ */
16524#define DDRPHY_DTAR1_DTCOL0_MASK (0x1FFU)
16525#define DDRPHY_DTAR1_DTCOL0_SHIFT (0U)
16526/*! DTCOL0 - Data Training Column Address
16527 */
16528#define DDRPHY_DTAR1_DTCOL0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR1_DTCOL0_SHIFT)) & DDRPHY_DTAR1_DTCOL0_MASK)
16529#define DDRPHY_DTAR1_RESERVED_15_9_MASK (0xFE00U)
16530#define DDRPHY_DTAR1_RESERVED_15_9_SHIFT (9U)
16531/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
16532 */
16533#define DDRPHY_DTAR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR1_RESERVED_15_9_SHIFT)) & DDRPHY_DTAR1_RESERVED_15_9_MASK)
16534#define DDRPHY_DTAR1_DTCOL1_MASK (0x1FF0000U)
16535#define DDRPHY_DTAR1_DTCOL1_SHIFT (16U)
16536/*! DTCOL1 - Data Training Column Address
16537 */
16538#define DDRPHY_DTAR1_DTCOL1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR1_DTCOL1_SHIFT)) & DDRPHY_DTAR1_DTCOL1_MASK)
16539#define DDRPHY_DTAR1_RESERVED_31_25_MASK (0xFE000000U)
16540#define DDRPHY_DTAR1_RESERVED_31_25_SHIFT (25U)
16541/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
16542 */
16543#define DDRPHY_DTAR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR1_RESERVED_31_25_SHIFT)) & DDRPHY_DTAR1_RESERVED_31_25_MASK)
16544/*! @} */
16545
16546/*! @name DTAR2 - Data Training Address Register 2 */
16547/*! @{ */
16548#define DDRPHY_DTAR2_DTCOL2_MASK (0x1FFU)
16549#define DDRPHY_DTAR2_DTCOL2_SHIFT (0U)
16550/*! DTCOL2 - Data Training Column Address
16551 */
16552#define DDRPHY_DTAR2_DTCOL2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR2_DTCOL2_SHIFT)) & DDRPHY_DTAR2_DTCOL2_MASK)
16553#define DDRPHY_DTAR2_RESERVED_15_9_MASK (0xFE00U)
16554#define DDRPHY_DTAR2_RESERVED_15_9_SHIFT (9U)
16555/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
16556 */
16557#define DDRPHY_DTAR2_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR2_RESERVED_15_9_SHIFT)) & DDRPHY_DTAR2_RESERVED_15_9_MASK)
16558#define DDRPHY_DTAR2_DTCOL3_MASK (0x1FF0000U)
16559#define DDRPHY_DTAR2_DTCOL3_SHIFT (16U)
16560/*! DTCOL3 - Data Training Column Address
16561 */
16562#define DDRPHY_DTAR2_DTCOL3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR2_DTCOL3_SHIFT)) & DDRPHY_DTAR2_DTCOL3_MASK)
16563#define DDRPHY_DTAR2_RESERVED_31_25_MASK (0xFE000000U)
16564#define DDRPHY_DTAR2_RESERVED_31_25_SHIFT (25U)
16565/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
16566 */
16567#define DDRPHY_DTAR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTAR2_RESERVED_31_25_SHIFT)) & DDRPHY_DTAR2_RESERVED_31_25_MASK)
16568/*! @} */
16569
16570/*! @name DTDR0 - Data Training Data Register 0 */
16571/*! @{ */
16572#define DDRPHY_DTDR0_DTBYTE0_MASK (0xFFU)
16573#define DDRPHY_DTDR0_DTBYTE0_SHIFT (0U)
16574/*! DTBYTE0 - Data Training Data
16575 */
16576#define DDRPHY_DTDR0_DTBYTE0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR0_DTBYTE0_SHIFT)) & DDRPHY_DTDR0_DTBYTE0_MASK)
16577#define DDRPHY_DTDR0_DTBYTE1_MASK (0xFF00U)
16578#define DDRPHY_DTDR0_DTBYTE1_SHIFT (8U)
16579/*! DTBYTE1 - Data Training Data
16580 */
16581#define DDRPHY_DTDR0_DTBYTE1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR0_DTBYTE1_SHIFT)) & DDRPHY_DTDR0_DTBYTE1_MASK)
16582#define DDRPHY_DTDR0_DTBYTE2_MASK (0xFF0000U)
16583#define DDRPHY_DTDR0_DTBYTE2_SHIFT (16U)
16584/*! DTBYTE2 - Data Training Data
16585 */
16586#define DDRPHY_DTDR0_DTBYTE2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR0_DTBYTE2_SHIFT)) & DDRPHY_DTDR0_DTBYTE2_MASK)
16587#define DDRPHY_DTDR0_DTBYTE3_MASK (0xFF000000U)
16588#define DDRPHY_DTDR0_DTBYTE3_SHIFT (24U)
16589/*! DTBYTE3 - Data Training Data
16590 */
16591#define DDRPHY_DTDR0_DTBYTE3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR0_DTBYTE3_SHIFT)) & DDRPHY_DTDR0_DTBYTE3_MASK)
16592/*! @} */
16593
16594/*! @name DTDR1 - Data Training Data Register 1 */
16595/*! @{ */
16596#define DDRPHY_DTDR1_DTBYTE4_MASK (0xFFU)
16597#define DDRPHY_DTDR1_DTBYTE4_SHIFT (0U)
16598/*! DTBYTE4 - Data Training Data
16599 */
16600#define DDRPHY_DTDR1_DTBYTE4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR1_DTBYTE4_SHIFT)) & DDRPHY_DTDR1_DTBYTE4_MASK)
16601#define DDRPHY_DTDR1_DTBYTE5_MASK (0xFF00U)
16602#define DDRPHY_DTDR1_DTBYTE5_SHIFT (8U)
16603/*! DTBYTE5 - Data Training Data
16604 */
16605#define DDRPHY_DTDR1_DTBYTE5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR1_DTBYTE5_SHIFT)) & DDRPHY_DTDR1_DTBYTE5_MASK)
16606#define DDRPHY_DTDR1_DTBYTE6_MASK (0xFF0000U)
16607#define DDRPHY_DTDR1_DTBYTE6_SHIFT (16U)
16608/*! DTBYTE6 - Data Training Data
16609 */
16610#define DDRPHY_DTDR1_DTBYTE6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR1_DTBYTE6_SHIFT)) & DDRPHY_DTDR1_DTBYTE6_MASK)
16611#define DDRPHY_DTDR1_DTBYTE7_MASK (0xFF000000U)
16612#define DDRPHY_DTDR1_DTBYTE7_SHIFT (24U)
16613/*! DTBYTE7 - Data Training Data
16614 */
16615#define DDRPHY_DTDR1_DTBYTE7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTDR1_DTBYTE7_SHIFT)) & DDRPHY_DTDR1_DTBYTE7_MASK)
16616/*! @} */
16617
16618/*! @name DTEDR0 - Data Training Eye Data Register 0 */
16619/*! @{ */
16620#define DDRPHY_DTEDR0_WDQLMN_MASK (0x1FFU)
16621#define DDRPHY_DTEDR0_WDQLMN_SHIFT (0U)
16622/*! WDQLMN - Data Training WDQ LCDL Minimum.
16623 */
16624#define DDRPHY_DTEDR0_WDQLMN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR0_WDQLMN_SHIFT)) & DDRPHY_DTEDR0_WDQLMN_MASK)
16625#define DDRPHY_DTEDR0_WDQLMX_MASK (0x3FE00U)
16626#define DDRPHY_DTEDR0_WDQLMX_SHIFT (9U)
16627/*! WDQLMX - Data Training WDQ LCDL Maximum.
16628 */
16629#define DDRPHY_DTEDR0_WDQLMX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR0_WDQLMX_SHIFT)) & DDRPHY_DTEDR0_WDQLMX_MASK)
16630#define DDRPHY_DTEDR0_WDQBMN_MASK (0xFC0000U)
16631#define DDRPHY_DTEDR0_WDQBMN_SHIFT (18U)
16632/*! WDQBMN - Data Training Write BDL Shift Minimum.
16633 */
16634#define DDRPHY_DTEDR0_WDQBMN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR0_WDQBMN_SHIFT)) & DDRPHY_DTEDR0_WDQBMN_MASK)
16635#define DDRPHY_DTEDR0_WDQBMX_MASK (0xFF000000U)
16636#define DDRPHY_DTEDR0_WDQBMX_SHIFT (24U)
16637/*! WDQBMX - Data Training Write BDL Shift Maximum.
16638 */
16639#define DDRPHY_DTEDR0_WDQBMX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR0_WDQBMX_SHIFT)) & DDRPHY_DTEDR0_WDQBMX_MASK)
16640/*! @} */
16641
16642/*! @name DTEDR1 - Data Training Eye Data Register 1 */
16643/*! @{ */
16644#define DDRPHY_DTEDR1_RDQSLMN_MASK (0x1FFU)
16645#define DDRPHY_DTEDR1_RDQSLMN_SHIFT (0U)
16646/*! RDQSLMN - Data Training RDQS LCDL Minimum.
16647 */
16648#define DDRPHY_DTEDR1_RDQSLMN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR1_RDQSLMN_SHIFT)) & DDRPHY_DTEDR1_RDQSLMN_MASK)
16649#define DDRPHY_DTEDR1_RDQSLMX_MASK (0x3FE00U)
16650#define DDRPHY_DTEDR1_RDQSLMX_SHIFT (9U)
16651/*! RDQSLMX - Data Training RDQS LCDL Maximum.
16652 */
16653#define DDRPHY_DTEDR1_RDQSLMX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR1_RDQSLMX_SHIFT)) & DDRPHY_DTEDR1_RDQSLMX_MASK)
16654#define DDRPHY_DTEDR1_RDQSBMN_MASK (0xFC0000U)
16655#define DDRPHY_DTEDR1_RDQSBMN_SHIFT (18U)
16656/*! RDQSBMN - Data Training Read BDL Shift Minimum.
16657 */
16658#define DDRPHY_DTEDR1_RDQSBMN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR1_RDQSBMN_SHIFT)) & DDRPHY_DTEDR1_RDQSBMN_MASK)
16659#define DDRPHY_DTEDR1_RDQSBMX_MASK (0xFF000000U)
16660#define DDRPHY_DTEDR1_RDQSBMX_SHIFT (24U)
16661/*! RDQSBMX - Data Training Read BDL Shift Maximum.
16662 */
16663#define DDRPHY_DTEDR1_RDQSBMX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR1_RDQSBMX_SHIFT)) & DDRPHY_DTEDR1_RDQSBMX_MASK)
16664/*! @} */
16665
16666/*! @name DTEDR2 - Data Training Eye Data Register 2 */
16667/*! @{ */
16668#define DDRPHY_DTEDR2_RDQSNLMN_MASK (0x1FFU)
16669#define DDRPHY_DTEDR2_RDQSNLMN_SHIFT (0U)
16670/*! RDQSNLMN - Data Training RDQSN LCDL Minimum.
16671 */
16672#define DDRPHY_DTEDR2_RDQSNLMN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR2_RDQSNLMN_SHIFT)) & DDRPHY_DTEDR2_RDQSNLMN_MASK)
16673#define DDRPHY_DTEDR2_RDQSNLMX_MASK (0x3FE00U)
16674#define DDRPHY_DTEDR2_RDQSNLMX_SHIFT (9U)
16675/*! RDQSNLMX - Data Training RDQSN LCDL Maximum.
16676 */
16677#define DDRPHY_DTEDR2_RDQSNLMX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR2_RDQSNLMX_SHIFT)) & DDRPHY_DTEDR2_RDQSNLMX_MASK)
16678#define DDRPHY_DTEDR2_RDQSNBMN_MASK (0xFC0000U)
16679#define DDRPHY_DTEDR2_RDQSNBMN_SHIFT (18U)
16680/*! RDQSNBMN - Data Training Read BDL Shift Minimum.
16681 */
16682#define DDRPHY_DTEDR2_RDQSNBMN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR2_RDQSNBMN_SHIFT)) & DDRPHY_DTEDR2_RDQSNBMN_MASK)
16683#define DDRPHY_DTEDR2_RDQSNBMX_MASK (0xFF000000U)
16684#define DDRPHY_DTEDR2_RDQSNBMX_SHIFT (24U)
16685/*! RDQSNBMX - Data Training Read BDL Shift Maximum.
16686 */
16687#define DDRPHY_DTEDR2_RDQSNBMX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DTEDR2_RDQSNBMX_SHIFT)) & DDRPHY_DTEDR2_RDQSNBMX_MASK)
16688/*! @} */
16689
16690/*! @name VTDR - VREF Training Data Register */
16691/*! @{ */
16692#define DDRPHY_VTDR_DVREFMN_MASK (0x3FU)
16693#define DDRPHY_VTDR_DVREFMN_SHIFT (0U)
16694/*! DVREFMN - DRAM DQ VREF Minimum.
16695 */
16696#define DDRPHY_VTDR_DVREFMN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_DVREFMN_SHIFT)) & DDRPHY_VTDR_DVREFMN_MASK)
16697#define DDRPHY_VTDR_RESERVED_7_6_MASK (0xC0U)
16698#define DDRPHY_VTDR_RESERVED_7_6_SHIFT (6U)
16699/*! RESERVED_7_6 - Reserved. Returns zeroes on reads.
16700 */
16701#define DDRPHY_VTDR_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_RESERVED_7_6_SHIFT)) & DDRPHY_VTDR_RESERVED_7_6_MASK)
16702#define DDRPHY_VTDR_DVREFMX_MASK (0x3F00U)
16703#define DDRPHY_VTDR_DVREFMX_SHIFT (8U)
16704/*! DVREFMX - DRAM DQ VREF Maximum.
16705 */
16706#define DDRPHY_VTDR_DVREFMX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_DVREFMX_SHIFT)) & DDRPHY_VTDR_DVREFMX_MASK)
16707#define DDRPHY_VTDR_RESERVED_15_14_MASK (0xC000U)
16708#define DDRPHY_VTDR_RESERVED_15_14_SHIFT (14U)
16709/*! RESERVED_15_14 - Reserved. Returns zeroes on reads.
16710 */
16711#define DDRPHY_VTDR_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_RESERVED_15_14_SHIFT)) & DDRPHY_VTDR_RESERVED_15_14_MASK)
16712#define DDRPHY_VTDR_HVREFMN_MASK (0x7F0000U)
16713#define DDRPHY_VTDR_HVREFMN_SHIFT (16U)
16714/*! HVREFMN - DRAM DQ VREF Minimum.
16715 */
16716#define DDRPHY_VTDR_HVREFMN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_HVREFMN_SHIFT)) & DDRPHY_VTDR_HVREFMN_MASK)
16717#define DDRPHY_VTDR_RESERVED_23_MASK (0x800000U)
16718#define DDRPHY_VTDR_RESERVED_23_SHIFT (23U)
16719/*! RESERVED_23 - Reserved. Returns zeroes on reads.
16720 */
16721#define DDRPHY_VTDR_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_RESERVED_23_SHIFT)) & DDRPHY_VTDR_RESERVED_23_MASK)
16722#define DDRPHY_VTDR_HVREFMX_MASK (0x7F000000U)
16723#define DDRPHY_VTDR_HVREFMX_SHIFT (24U)
16724/*! HVREFMX - DRAM DQ VREF Maximum.
16725 */
16726#define DDRPHY_VTDR_HVREFMX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_HVREFMX_SHIFT)) & DDRPHY_VTDR_HVREFMX_MASK)
16727#define DDRPHY_VTDR_RESERVED_31_MASK (0x80000000U)
16728#define DDRPHY_VTDR_RESERVED_31_SHIFT (31U)
16729/*! RESERVED_31 - Reserved. Returns zeroes on reads.
16730 */
16731#define DDRPHY_VTDR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTDR_RESERVED_31_SHIFT)) & DDRPHY_VTDR_RESERVED_31_MASK)
16732/*! @} */
16733
16734/*! @name CATR0 - CA Training Register 0 */
16735/*! @{ */
16736#define DDRPHY_CATR0_CA1BYTE0_MASK (0xFU)
16737#define DDRPHY_CATR0_CA1BYTE0_SHIFT (0U)
16738/*! CA1BYTE0 - CA_1 Response Byte Lane 0
16739 */
16740#define DDRPHY_CATR0_CA1BYTE0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR0_CA1BYTE0_SHIFT)) & DDRPHY_CATR0_CA1BYTE0_MASK)
16741#define DDRPHY_CATR0_CA1BYTE1_MASK (0xF0U)
16742#define DDRPHY_CATR0_CA1BYTE1_SHIFT (4U)
16743/*! CA1BYTE1 - CA_1 Response Byte Lane 1
16744 */
16745#define DDRPHY_CATR0_CA1BYTE1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR0_CA1BYTE1_SHIFT)) & DDRPHY_CATR0_CA1BYTE1_MASK)
16746#define DDRPHY_CATR0_CAADR_MASK (0x1F00U)
16747#define DDRPHY_CATR0_CAADR_SHIFT (8U)
16748/*! CAADR - Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA
16749 * response after Calibration command has been sent to the memory
16750 */
16751#define DDRPHY_CATR0_CAADR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR0_CAADR_SHIFT)) & DDRPHY_CATR0_CAADR_MASK)
16752#define DDRPHY_CATR0_RESERVED_15_13_MASK (0xE000U)
16753#define DDRPHY_CATR0_RESERVED_15_13_SHIFT (13U)
16754/*! RESERVED_15_13 - Reserved. Return zeroes on reads.
16755 */
16756#define DDRPHY_CATR0_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR0_RESERVED_15_13_SHIFT)) & DDRPHY_CATR0_RESERVED_15_13_MASK)
16757#define DDRPHY_CATR0_CACD_MASK (0x1F0000U)
16758#define DDRPHY_CATR0_CACD_SHIFT (16U)
16759/*! CACD - Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command
16760 */
16761#define DDRPHY_CATR0_CACD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR0_CACD_SHIFT)) & DDRPHY_CATR0_CACD_MASK)
16762#define DDRPHY_CATR0_RESERVED_31_21_MASK (0xFFE00000U)
16763#define DDRPHY_CATR0_RESERVED_31_21_SHIFT (21U)
16764/*! RESERVED_31_21 - Reserved. Return zeroes on reads.
16765 */
16766#define DDRPHY_CATR0_RESERVED_31_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR0_RESERVED_31_21_SHIFT)) & DDRPHY_CATR0_RESERVED_31_21_MASK)
16767/*! @} */
16768
16769/*! @name CATR1 - CA Training Register 1 */
16770/*! @{ */
16771#define DDRPHY_CATR1_CAENT_MASK (0xFU)
16772#define DDRPHY_CATR1_CAENT_SHIFT (0U)
16773/*! CAENT - Minimum time (in terms of number of dram clocks) for first CA calibration command after CKE is low
16774 */
16775#define DDRPHY_CATR1_CAENT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CAENT_SHIFT)) & DDRPHY_CATR1_CAENT_MASK)
16776#define DDRPHY_CATR1_CAEXT_MASK (0xF0U)
16777#define DDRPHY_CATR1_CAEXT_SHIFT (4U)
16778/*! CAEXT - Minimum time (in terms of number of dram clocks) for CA calibration exit command after CKE is high
16779 */
16780#define DDRPHY_CATR1_CAEXT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CAEXT_SHIFT)) & DDRPHY_CATR1_CAEXT_MASK)
16781#define DDRPHY_CATR1_CACKEL_MASK (0xF00U)
16782#define DDRPHY_CATR1_CACKEL_SHIFT (8U)
16783/*! CACKEL - Minimum time (in terms of number of dram clocks) for CKE going low after CA calibration mode is programmed
16784 */
16785#define DDRPHY_CATR1_CACKEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CACKEL_SHIFT)) & DDRPHY_CATR1_CACKEL_MASK)
16786#define DDRPHY_CATR1_CACKEH_MASK (0xF000U)
16787#define DDRPHY_CATR1_CACKEH_SHIFT (12U)
16788/*! CACKEH - Minimum time (in terms of number of dram clocks) for CKE high after last CA calibration response is driven by memory
16789 */
16790#define DDRPHY_CATR1_CACKEH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CACKEH_SHIFT)) & DDRPHY_CATR1_CACKEH_MASK)
16791#define DDRPHY_CATR1_CAMRZ_MASK (0xF0000U)
16792#define DDRPHY_CATR1_CAMRZ_SHIFT (16U)
16793/*! CAMRZ - Minimum time (in terms of number of dram clocks) for DRAM DQ going tristate after MRW CA exit calibration command
16794 */
16795#define DDRPHY_CATR1_CAMRZ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CAMRZ_SHIFT)) & DDRPHY_CATR1_CAMRZ_MASK)
16796#define DDRPHY_CATR1_CA0BYTE0_MASK (0xF00000U)
16797#define DDRPHY_CATR1_CA0BYTE0_SHIFT (20U)
16798/*! CA0BYTE0 - CA_0 Response Byte Lane 0
16799 */
16800#define DDRPHY_CATR1_CA0BYTE0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CA0BYTE0_SHIFT)) & DDRPHY_CATR1_CA0BYTE0_MASK)
16801#define DDRPHY_CATR1_CA0BYTE1_MASK (0xF000000U)
16802#define DDRPHY_CATR1_CA0BYTE1_SHIFT (24U)
16803/*! CA0BYTE1 - CA_0 Response Byte Lane 1
16804 */
16805#define DDRPHY_CATR1_CA0BYTE1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_CA0BYTE1_SHIFT)) & DDRPHY_CATR1_CA0BYTE1_MASK)
16806#define DDRPHY_CATR1_RESERVED_31_28_MASK (0xF0000000U)
16807#define DDRPHY_CATR1_RESERVED_31_28_SHIFT (28U)
16808/*! RESERVED_31_28 - Reserved. Return zeroes on reads.
16809 */
16810#define DDRPHY_CATR1_RESERVED_31_28(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_CATR1_RESERVED_31_28_SHIFT)) & DDRPHY_CATR1_RESERVED_31_28_MASK)
16811/*! @} */
16812
16813/*! @name PGCR8 - PHY General Configuration Register 8 */
16814/*! @{ */
16815#define DDRPHY_PGCR8_BSWAPMSB_MASK (0x1FFU)
16816#define DDRPHY_PGCR8_BSWAPMSB_SHIFT (0U)
16817/*! BSWAPMSB - When a bit is set, it indicates that the corresponding PHY byte lane is connected to
16818 * MSByte of the LPDDR4 DRAM 16 bit instance it is connected to.
16819 */
16820#define DDRPHY_PGCR8_BSWAPMSB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_BSWAPMSB_SHIFT)) & DDRPHY_PGCR8_BSWAPMSB_MASK)
16821#define DDRPHY_PGCR8_RESERVED_13_9_MASK (0x3E00U)
16822#define DDRPHY_PGCR8_RESERVED_13_9_SHIFT (9U)
16823/*! RESERVED_13_9 - Reserved. Return zeroes on reads.
16824 */
16825#define DDRPHY_PGCR8_RESERVED_13_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_RESERVED_13_9_SHIFT)) & DDRPHY_PGCR8_RESERVED_13_9_MASK)
16826#define DDRPHY_PGCR8_INC_DQS2DQ_EN_MASK (0x4000U)
16827#define DDRPHY_PGCR8_INC_DQS2DQ_EN_SHIFT (14U)
16828/*! INC_DQS2DQ_EN - Incremental DQS2DQ Training
16829 */
16830#define DDRPHY_PGCR8_INC_DQS2DQ_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_INC_DQS2DQ_EN_SHIFT)) & DDRPHY_PGCR8_INC_DQS2DQ_EN_MASK)
16831#define DDRPHY_PGCR8_INC_DQS2DQ_MODE_MASK (0x8000U)
16832#define DDRPHY_PGCR8_INC_DQS2DQ_MODE_SHIFT (15U)
16833/*! INC_DQS2DQ_MODE - Self Incremental DQS2DQ Training
16834 */
16835#define DDRPHY_PGCR8_INC_DQS2DQ_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_INC_DQS2DQ_MODE_SHIFT)) & DDRPHY_PGCR8_INC_DQS2DQ_MODE_MASK)
16836#define DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_MASK (0x10000U)
16837#define DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_SHIFT (16U)
16838/*! INC_DQS2DQ_RANKEN - Rank Enable
16839 */
16840#define DDRPHY_PGCR8_INC_DQS2DQ_RANKEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_SHIFT)) & DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_MASK)
16841#define DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_RSVD_MASK (0xE0000U)
16842#define DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_RSVD_SHIFT (17U)
16843/*! INC_DQS2DQ_RANKEN_RSVD - Rank Enable
16844 */
16845#define DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_RSVD_SHIFT)) & DDRPHY_PGCR8_INC_DQS2DQ_RANKEN_RSVD_MASK)
16846#define DDRPHY_PGCR8_INC_DQS2DQ_CM_MASK (0xFF00000U)
16847#define DDRPHY_PGCR8_INC_DQS2DQ_CM_SHIFT (20U)
16848/*! INC_DQS2DQ_CM - Counter Cycle Multiplier
16849 */
16850#define DDRPHY_PGCR8_INC_DQS2DQ_CM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_INC_DQS2DQ_CM_SHIFT)) & DDRPHY_PGCR8_INC_DQS2DQ_CM_MASK)
16851#define DDRPHY_PGCR8_INC_DQS2DQ_CF_MASK (0xF0000000U)
16852#define DDRPHY_PGCR8_INC_DQS2DQ_CF_SHIFT (28U)
16853/*! INC_DQS2DQ_CF - Counter Cycles Factor
16854 */
16855#define DDRPHY_PGCR8_INC_DQS2DQ_CF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_PGCR8_INC_DQS2DQ_CF_SHIFT)) & DDRPHY_PGCR8_INC_DQS2DQ_CF_MASK)
16856/*! @} */
16857
16858/*! @name DQSDR0 - DQS Drift Register 0 */
16859/*! @{ */
16860#define DDRPHY_DQSDR0_DFTDTEN_MASK (0x1U)
16861#define DDRPHY_DQSDR0_DFTDTEN_SHIFT (0U)
16862/*! DFTDTEN - DQS Drift Detection Enable
16863 */
16864#define DDRPHY_DQSDR0_DFTDTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTDTEN_SHIFT)) & DDRPHY_DQSDR0_DFTDTEN_MASK)
16865#define DDRPHY_DQSDR0_DFTDTMODE_MASK (0x2U)
16866#define DDRPHY_DQSDR0_DFTDTMODE_SHIFT (1U)
16867/*! DFTDTMODE - DQS Drift Detection Mode
16868 */
16869#define DDRPHY_DQSDR0_DFTDTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTDTMODE_SHIFT)) & DDRPHY_DQSDR0_DFTDTMODE_MASK)
16870#define DDRPHY_DQSDR0_DFTUPMODE_MASK (0xCU)
16871#define DDRPHY_DQSDR0_DFTUPMODE_SHIFT (2U)
16872/*! DFTUPMODE - DQS Drift Update Mode
16873 */
16874#define DDRPHY_DQSDR0_DFTUPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTUPMODE_SHIFT)) & DDRPHY_DQSDR0_DFTUPMODE_MASK)
16875#define DDRPHY_DQSDR0_DFTGPULSE_MASK (0xF0U)
16876#define DDRPHY_DQSDR0_DFTGPULSE_SHIFT (4U)
16877/*! DFTGPULSE - Gate Pulse Enable
16878 */
16879#define DDRPHY_DQSDR0_DFTGPULSE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTGPULSE_SHIFT)) & DDRPHY_DQSDR0_DFTGPULSE_MASK)
16880#define DDRPHY_DQSDR0_RESERVED_11_8_MASK (0xF00U)
16881#define DDRPHY_DQSDR0_RESERVED_11_8_SHIFT (8U)
16882/*! RESERVED_11_8 - Reserved. Return zeroes on reads.
16883 */
16884#define DDRPHY_DQSDR0_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_RESERVED_11_8_SHIFT)) & DDRPHY_DQSDR0_RESERVED_11_8_MASK)
16885#define DDRPHY_DQSDR0_DFTIDLRD_MASK (0xF000U)
16886#define DDRPHY_DQSDR0_DFTIDLRD_SHIFT (12U)
16887/*! DFTIDLRD - Drift Idle Reads
16888 */
16889#define DDRPHY_DQSDR0_DFTIDLRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTIDLRD_SHIFT)) & DDRPHY_DQSDR0_DFTIDLRD_MASK)
16890#define DDRPHY_DQSDR0_DFTB2BRD_MASK (0xF0000U)
16891#define DDRPHY_DQSDR0_DFTB2BRD_SHIFT (16U)
16892/*! DFTB2BRD - Drift Back-to-Back Reads
16893 */
16894#define DDRPHY_DQSDR0_DFTB2BRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTB2BRD_SHIFT)) & DDRPHY_DQSDR0_DFTB2BRD_MASK)
16895#define DDRPHY_DQSDR0_DFTRDSPC_MASK (0x300000U)
16896#define DDRPHY_DQSDR0_DFTRDSPC_SHIFT (20U)
16897/*! DFTRDSPC - Drift Read Spacing
16898 */
16899#define DDRPHY_DQSDR0_DFTRDSPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTRDSPC_SHIFT)) & DDRPHY_DQSDR0_DFTRDSPC_MASK)
16900#define DDRPHY_DQSDR0_RESERVED_25_22_MASK (0x3C00000U)
16901#define DDRPHY_DQSDR0_RESERVED_25_22_SHIFT (22U)
16902/*! RESERVED_25_22 - Reserved. Return zeroes on reads.
16903 */
16904#define DDRPHY_DQSDR0_RESERVED_25_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_RESERVED_25_22_SHIFT)) & DDRPHY_DQSDR0_RESERVED_25_22_MASK)
16905#define DDRPHY_DQSDR0_DFTDDLUP_MASK (0x4000000U)
16906#define DDRPHY_DQSDR0_DFTDDLUP_SHIFT (26U)
16907/*! DFTDDLUP - Drift DDL Update
16908 */
16909#define DDRPHY_DQSDR0_DFTDDLUP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTDDLUP_SHIFT)) & DDRPHY_DQSDR0_DFTDDLUP_MASK)
16910#define DDRPHY_DQSDR0_DFTZQUP_MASK (0x8000000U)
16911#define DDRPHY_DQSDR0_DFTZQUP_SHIFT (27U)
16912/*! DFTZQUP - Drift Impedance Update
16913 */
16914#define DDRPHY_DQSDR0_DFTZQUP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTZQUP_SHIFT)) & DDRPHY_DQSDR0_DFTZQUP_MASK)
16915#define DDRPHY_DQSDR0_DFTDLY_MASK (0xF0000000U)
16916#define DDRPHY_DQSDR0_DFTDLY_SHIFT (28U)
16917/*! DFTDLY - Number of delay taps by which the DQS gate LCDL will be updated when DQS drift is detected
16918 */
16919#define DDRPHY_DQSDR0_DFTDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR0_DFTDLY_SHIFT)) & DDRPHY_DQSDR0_DFTDLY_MASK)
16920/*! @} */
16921
16922/*! @name DQSDR1 - DQS Drift Register 1 */
16923/*! @{ */
16924#define DDRPHY_DQSDR1_DFTRDIDLC_MASK (0xFFU)
16925#define DDRPHY_DQSDR1_DFTRDIDLC_SHIFT (0U)
16926/*! DFTRDIDLC - Drift Idle Read Cycles
16927 */
16928#define DDRPHY_DQSDR1_DFTRDIDLC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR1_DFTRDIDLC_SHIFT)) & DDRPHY_DQSDR1_DFTRDIDLC_MASK)
16929#define DDRPHY_DQSDR1_DFTRDB2BC_MASK (0xFF00U)
16930#define DDRPHY_DQSDR1_DFTRDB2BC_SHIFT (8U)
16931/*! DFTRDB2BC - Drift Back-to-Back Read Cycles
16932 */
16933#define DDRPHY_DQSDR1_DFTRDB2BC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR1_DFTRDB2BC_SHIFT)) & DDRPHY_DQSDR1_DFTRDB2BC_MASK)
16934#define DDRPHY_DQSDR1_DFTRDIDLF_MASK (0xF0000U)
16935#define DDRPHY_DQSDR1_DFTRDIDLF_SHIFT (16U)
16936/*! DFTRDIDLF - Drift Idle Read Cycles Factor
16937 */
16938#define DDRPHY_DQSDR1_DFTRDIDLF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR1_DFTRDIDLF_SHIFT)) & DDRPHY_DQSDR1_DFTRDIDLF_MASK)
16939#define DDRPHY_DQSDR1_DFTRDB2BF_MASK (0xF00000U)
16940#define DDRPHY_DQSDR1_DFTRDB2BF_SHIFT (20U)
16941/*! DFTRDB2BF - Drift Back-to-Back Read Cycles Factor
16942 */
16943#define DDRPHY_DQSDR1_DFTRDB2BF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR1_DFTRDB2BF_SHIFT)) & DDRPHY_DQSDR1_DFTRDB2BF_MASK)
16944#define DDRPHY_DQSDR1_DFTUPDACKC_MASK (0x1F000000U)
16945#define DDRPHY_DQSDR1_DFTUPDACKC_SHIFT (24U)
16946/*! DFTUPDACKC - Drift DFI Update ACK to DQS Drift FSM issuing IDLE Read Cycles
16947 */
16948#define DDRPHY_DQSDR1_DFTUPDACKC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR1_DFTUPDACKC_SHIFT)) & DDRPHY_DQSDR1_DFTUPDACKC_MASK)
16949#define DDRPHY_DQSDR1_DFTUPDACKF_MASK (0xE0000000U)
16950#define DDRPHY_DQSDR1_DFTUPDACKF_SHIFT (29U)
16951/*! DFTUPDACKF - Drift DFI Update Request ACK to DQS Drift FSM issing IDLE REad Cycles Factor
16952 */
16953#define DDRPHY_DQSDR1_DFTUPDACKF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR1_DFTUPDACKF_SHIFT)) & DDRPHY_DQSDR1_DFTUPDACKF_MASK)
16954/*! @} */
16955
16956/*! @name DQSDR2 - DQS Drift Register 2 */
16957/*! @{ */
16958#define DDRPHY_DQSDR2_DFTMNTPRD_MASK (0xFFFFU)
16959#define DDRPHY_DQSDR2_DFTMNTPRD_SHIFT (0U)
16960/*! DFTMNTPRD - Drift Monitor Period
16961 */
16962#define DDRPHY_DQSDR2_DFTMNTPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR2_DFTMNTPRD_SHIFT)) & DDRPHY_DQSDR2_DFTMNTPRD_MASK)
16963#define DDRPHY_DQSDR2_DFTTHRSH_MASK (0xFF0000U)
16964#define DDRPHY_DQSDR2_DFTTHRSH_SHIFT (16U)
16965/*! DFTTHRSH - Drift Threshold
16966 */
16967#define DDRPHY_DQSDR2_DFTTHRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR2_DFTTHRSH_SHIFT)) & DDRPHY_DQSDR2_DFTTHRSH_MASK)
16968#define DDRPHY_DQSDR2_RESERVED_31_24_MASK (0xFF000000U)
16969#define DDRPHY_DQSDR2_RESERVED_31_24_SHIFT (24U)
16970/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
16971 */
16972#define DDRPHY_DQSDR2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DQSDR2_RESERVED_31_24_SHIFT)) & DDRPHY_DQSDR2_RESERVED_31_24_MASK)
16973/*! @} */
16974
16975/*! @name DCUAR - DCU Address Register */
16976/*! @{ */
16977#define DDRPHY_DCUAR_CWADDR_W_MASK (0xFU)
16978#define DDRPHY_DCUAR_CWADDR_W_SHIFT (0U)
16979/*! CWADDR_W - Cache Word Address
16980 */
16981#define DDRPHY_DCUAR_CWADDR_W(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_CWADDR_W_SHIFT)) & DDRPHY_DCUAR_CWADDR_W_MASK)
16982#define DDRPHY_DCUAR_CSADDR_W_MASK (0xF0U)
16983#define DDRPHY_DCUAR_CSADDR_W_SHIFT (4U)
16984/*! CSADDR_W - Cache Slice Address
16985 */
16986#define DDRPHY_DCUAR_CSADDR_W(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_CSADDR_W_SHIFT)) & DDRPHY_DCUAR_CSADDR_W_MASK)
16987#define DDRPHY_DCUAR_CSEL_MASK (0x300U)
16988#define DDRPHY_DCUAR_CSEL_SHIFT (8U)
16989/*! CSEL - Cache Select
16990 */
16991#define DDRPHY_DCUAR_CSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_CSEL_SHIFT)) & DDRPHY_DCUAR_CSEL_MASK)
16992#define DDRPHY_DCUAR_INCA_MASK (0x400U)
16993#define DDRPHY_DCUAR_INCA_SHIFT (10U)
16994/*! INCA - Increment Address
16995 */
16996#define DDRPHY_DCUAR_INCA(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_INCA_SHIFT)) & DDRPHY_DCUAR_INCA_MASK)
16997#define DDRPHY_DCUAR_ATYPE_MASK (0x800U)
16998#define DDRPHY_DCUAR_ATYPE_SHIFT (11U)
16999/*! ATYPE - Access Type
17000 */
17001#define DDRPHY_DCUAR_ATYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_ATYPE_SHIFT)) & DDRPHY_DCUAR_ATYPE_MASK)
17002#define DDRPHY_DCUAR_CWADDR_R_MASK (0xF000U)
17003#define DDRPHY_DCUAR_CWADDR_R_SHIFT (12U)
17004/*! CWADDR_R - Cache Word Address
17005 */
17006#define DDRPHY_DCUAR_CWADDR_R(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_CWADDR_R_SHIFT)) & DDRPHY_DCUAR_CWADDR_R_MASK)
17007#define DDRPHY_DCUAR_CSADDR_R_MASK (0xF0000U)
17008#define DDRPHY_DCUAR_CSADDR_R_SHIFT (16U)
17009/*! CSADDR_R - Cache Slice Address
17010 */
17011#define DDRPHY_DCUAR_CSADDR_R(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_CSADDR_R_SHIFT)) & DDRPHY_DCUAR_CSADDR_R_MASK)
17012#define DDRPHY_DCUAR_RESERVED_31_20_MASK (0xFFF00000U)
17013#define DDRPHY_DCUAR_RESERVED_31_20_SHIFT (20U)
17014/*! RESERVED_31_20 - Reserved. Return zeroes on reads.
17015 */
17016#define DDRPHY_DCUAR_RESERVED_31_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUAR_RESERVED_31_20_SHIFT)) & DDRPHY_DCUAR_RESERVED_31_20_MASK)
17017/*! @} */
17018
17019/*! @name DCUDR - DCU Data Register */
17020/*! @{ */
17021#define DDRPHY_DCUDR_CDATA_MASK (0xFFFFFFFFU)
17022#define DDRPHY_DCUDR_CDATA_SHIFT (0U)
17023/*! CDATA - Cache Data
17024 */
17025#define DDRPHY_DCUDR_CDATA(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUDR_CDATA_SHIFT)) & DDRPHY_DCUDR_CDATA_MASK)
17026/*! @} */
17027
17028/*! @name DCURR - DCU Run Register */
17029/*! @{ */
17030#define DDRPHY_DCURR_DINST_MASK (0xFU)
17031#define DDRPHY_DCURR_DINST_SHIFT (0U)
17032/*! DINST - DCU Instruction
17033 */
17034#define DDRPHY_DCURR_DINST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_DINST_SHIFT)) & DDRPHY_DCURR_DINST_MASK)
17035#define DDRPHY_DCURR_SADDR_MASK (0xF0U)
17036#define DDRPHY_DCURR_SADDR_SHIFT (4U)
17037/*! SADDR - Start Address
17038 */
17039#define DDRPHY_DCURR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_SADDR_SHIFT)) & DDRPHY_DCURR_SADDR_MASK)
17040#define DDRPHY_DCURR_EADDR_MASK (0xF00U)
17041#define DDRPHY_DCURR_EADDR_SHIFT (8U)
17042/*! EADDR - End Address
17043 */
17044#define DDRPHY_DCURR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_EADDR_SHIFT)) & DDRPHY_DCURR_EADDR_MASK)
17045#define DDRPHY_DCURR_NFAIL_MASK (0xFF000U)
17046#define DDRPHY_DCURR_NFAIL_SHIFT (12U)
17047/*! NFAIL - Number of Failures
17048 */
17049#define DDRPHY_DCURR_NFAIL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_NFAIL_SHIFT)) & DDRPHY_DCURR_NFAIL_MASK)
17050#define DDRPHY_DCURR_SONF_MASK (0x100000U)
17051#define DDRPHY_DCURR_SONF_SHIFT (20U)
17052/*! SONF - Stop On Nth Fail
17053 */
17054#define DDRPHY_DCURR_SONF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_SONF_SHIFT)) & DDRPHY_DCURR_SONF_MASK)
17055#define DDRPHY_DCURR_SCOF_MASK (0x200000U)
17056#define DDRPHY_DCURR_SCOF_SHIFT (21U)
17057/*! SCOF - Stop Capture On Full
17058 */
17059#define DDRPHY_DCURR_SCOF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_SCOF_SHIFT)) & DDRPHY_DCURR_SCOF_MASK)
17060#define DDRPHY_DCURR_RCEN_MASK (0x400000U)
17061#define DDRPHY_DCURR_RCEN_SHIFT (22U)
17062/*! RCEN - Read Capture Enable
17063 */
17064#define DDRPHY_DCURR_RCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_RCEN_SHIFT)) & DDRPHY_DCURR_RCEN_MASK)
17065#define DDRPHY_DCURR_XCEN_MASK (0x800000U)
17066#define DDRPHY_DCURR_XCEN_SHIFT (23U)
17067/*! XCEN - Expected Compare Enable
17068 */
17069#define DDRPHY_DCURR_XCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_XCEN_SHIFT)) & DDRPHY_DCURR_XCEN_MASK)
17070#define DDRPHY_DCURR_RESERVED_31_24_MASK (0xFF000000U)
17071#define DDRPHY_DCURR_RESERVED_31_24_SHIFT (24U)
17072/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
17073 */
17074#define DDRPHY_DCURR_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCURR_RESERVED_31_24_SHIFT)) & DDRPHY_DCURR_RESERVED_31_24_MASK)
17075/*! @} */
17076
17077/*! @name DCULR - DCU Loop Register */
17078/*! @{ */
17079#define DDRPHY_DCULR_LSADDR_MASK (0xFU)
17080#define DDRPHY_DCULR_LSADDR_SHIFT (0U)
17081/*! LSADDR - Loop Start Address
17082 */
17083#define DDRPHY_DCULR_LSADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_LSADDR_SHIFT)) & DDRPHY_DCULR_LSADDR_MASK)
17084#define DDRPHY_DCULR_LEADDR_MASK (0xF0U)
17085#define DDRPHY_DCULR_LEADDR_SHIFT (4U)
17086/*! LEADDR - Loop End Address
17087 */
17088#define DDRPHY_DCULR_LEADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_LEADDR_SHIFT)) & DDRPHY_DCULR_LEADDR_MASK)
17089#define DDRPHY_DCULR_LCNT_MASK (0xFF00U)
17090#define DDRPHY_DCULR_LCNT_SHIFT (8U)
17091/*! LCNT - Loop Count
17092 */
17093#define DDRPHY_DCULR_LCNT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_LCNT_SHIFT)) & DDRPHY_DCULR_LCNT_MASK)
17094#define DDRPHY_DCULR_LINF_MASK (0x10000U)
17095#define DDRPHY_DCULR_LINF_SHIFT (16U)
17096/*! LINF - Loop Infinite
17097 */
17098#define DDRPHY_DCULR_LINF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_LINF_SHIFT)) & DDRPHY_DCULR_LINF_MASK)
17099#define DDRPHY_DCULR_IDA_MASK (0x20000U)
17100#define DDRPHY_DCULR_IDA_SHIFT (17U)
17101/*! IDA - Increment DRAM Address
17102 */
17103#define DDRPHY_DCULR_IDA(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_IDA_SHIFT)) & DDRPHY_DCULR_IDA_MASK)
17104#define DDRPHY_DCULR_RESERVED_27_18_MASK (0xFFC0000U)
17105#define DDRPHY_DCULR_RESERVED_27_18_SHIFT (18U)
17106/*! RESERVED_27_18 - Reserved. Return zeroes on reads.
17107 */
17108#define DDRPHY_DCULR_RESERVED_27_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_RESERVED_27_18_SHIFT)) & DDRPHY_DCULR_RESERVED_27_18_MASK)
17109#define DDRPHY_DCULR_XLEADDR_MASK (0xF0000000U)
17110#define DDRPHY_DCULR_XLEADDR_SHIFT (28U)
17111/*! XLEADDR - Expected Data Loop End Address
17112 */
17113#define DDRPHY_DCULR_XLEADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCULR_XLEADDR_SHIFT)) & DDRPHY_DCULR_XLEADDR_MASK)
17114/*! @} */
17115
17116/*! @name DCUGCR - DCU General Configuration Register */
17117/*! @{ */
17118#define DDRPHY_DCUGCR_RCSW_MASK (0xFFFFU)
17119#define DDRPHY_DCUGCR_RCSW_SHIFT (0U)
17120/*! RCSW - Read Capture Start Word
17121 */
17122#define DDRPHY_DCUGCR_RCSW(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUGCR_RCSW_SHIFT)) & DDRPHY_DCUGCR_RCSW_MASK)
17123#define DDRPHY_DCUGCR_RESERVED_31_16_MASK (0xFFFF0000U)
17124#define DDRPHY_DCUGCR_RESERVED_31_16_SHIFT (16U)
17125/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
17126 */
17127#define DDRPHY_DCUGCR_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUGCR_RESERVED_31_16_SHIFT)) & DDRPHY_DCUGCR_RESERVED_31_16_MASK)
17128/*! @} */
17129
17130/*! @name DCUTPR - DCU Timing Parameters Register */
17131/*! @{ */
17132#define DDRPHY_DCUTPR_tDCUT0_MASK (0xFFU)
17133#define DDRPHY_DCUTPR_tDCUT0_SHIFT (0U)
17134/*! tDCUT0 - DCU Generic Timing Parameter 0
17135 */
17136#define DDRPHY_DCUTPR_tDCUT0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUTPR_tDCUT0_SHIFT)) & DDRPHY_DCUTPR_tDCUT0_MASK)
17137#define DDRPHY_DCUTPR_tDCUT1_MASK (0xFF00U)
17138#define DDRPHY_DCUTPR_tDCUT1_SHIFT (8U)
17139/*! tDCUT1 - DCU Generic Timing Parameter 1
17140 */
17141#define DDRPHY_DCUTPR_tDCUT1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUTPR_tDCUT1_SHIFT)) & DDRPHY_DCUTPR_tDCUT1_MASK)
17142#define DDRPHY_DCUTPR_tDCUT2_MASK (0xFFFF0000U)
17143#define DDRPHY_DCUTPR_tDCUT2_SHIFT (16U)
17144/*! tDCUT2 - DCU Generic Timing Parameter 2
17145 */
17146#define DDRPHY_DCUTPR_tDCUT2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUTPR_tDCUT2_SHIFT)) & DDRPHY_DCUTPR_tDCUT2_MASK)
17147/*! @} */
17148
17149/*! @name DCUSR0 - DCU Status Register 0 */
17150/*! @{ */
17151#define DDRPHY_DCUSR0_RDONE_MASK (0x1U)
17152#define DDRPHY_DCUSR0_RDONE_SHIFT (0U)
17153/*! RDONE - Run Done
17154 */
17155#define DDRPHY_DCUSR0_RDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR0_RDONE_SHIFT)) & DDRPHY_DCUSR0_RDONE_MASK)
17156#define DDRPHY_DCUSR0_CFAIL_MASK (0x2U)
17157#define DDRPHY_DCUSR0_CFAIL_SHIFT (1U)
17158/*! CFAIL - Capture Fail
17159 */
17160#define DDRPHY_DCUSR0_CFAIL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR0_CFAIL_SHIFT)) & DDRPHY_DCUSR0_CFAIL_MASK)
17161#define DDRPHY_DCUSR0_CFULL_MASK (0x4U)
17162#define DDRPHY_DCUSR0_CFULL_SHIFT (2U)
17163/*! CFULL - Capture Full
17164 */
17165#define DDRPHY_DCUSR0_CFULL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR0_CFULL_SHIFT)) & DDRPHY_DCUSR0_CFULL_MASK)
17166#define DDRPHY_DCUSR0_RESERVED_31_3_MASK (0xFFFFFFF8U)
17167#define DDRPHY_DCUSR0_RESERVED_31_3_SHIFT (3U)
17168/*! RESERVED_31_3 - Reserved. Return zeroes on reads.
17169 */
17170#define DDRPHY_DCUSR0_RESERVED_31_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR0_RESERVED_31_3_SHIFT)) & DDRPHY_DCUSR0_RESERVED_31_3_MASK)
17171/*! @} */
17172
17173/*! @name DCUSR1 - DCU Status Register 1 */
17174/*! @{ */
17175#define DDRPHY_DCUSR1_RDCNT_MASK (0xFFFFU)
17176#define DDRPHY_DCUSR1_RDCNT_SHIFT (0U)
17177/*! RDCNT - Read Count
17178 */
17179#define DDRPHY_DCUSR1_RDCNT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR1_RDCNT_SHIFT)) & DDRPHY_DCUSR1_RDCNT_MASK)
17180#define DDRPHY_DCUSR1_FLCNT_MASK (0xFF0000U)
17181#define DDRPHY_DCUSR1_FLCNT_SHIFT (16U)
17182/*! FLCNT - Fail Count
17183 */
17184#define DDRPHY_DCUSR1_FLCNT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR1_FLCNT_SHIFT)) & DDRPHY_DCUSR1_FLCNT_MASK)
17185#define DDRPHY_DCUSR1_LPCNT_MASK (0xFF000000U)
17186#define DDRPHY_DCUSR1_LPCNT_SHIFT (24U)
17187/*! LPCNT - Loop Count
17188 */
17189#define DDRPHY_DCUSR1_LPCNT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DCUSR1_LPCNT_SHIFT)) & DDRPHY_DCUSR1_LPCNT_MASK)
17190/*! @} */
17191
17192/*! @name BISTRR - BIST Run Register */
17193/*! @{ */
17194#define DDRPHY_BISTRR_BINST_MASK (0x7U)
17195#define DDRPHY_BISTRR_BINST_SHIFT (0U)
17196/*! BINST - BIST Instruction
17197 */
17198#define DDRPHY_BISTRR_BINST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BINST_SHIFT)) & DDRPHY_BISTRR_BINST_MASK)
17199#define DDRPHY_BISTRR_BMODE_MASK (0x8U)
17200#define DDRPHY_BISTRR_BMODE_SHIFT (3U)
17201/*! BMODE - BIST Mode
17202 */
17203#define DDRPHY_BISTRR_BMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BMODE_SHIFT)) & DDRPHY_BISTRR_BMODE_MASK)
17204#define DDRPHY_BISTRR_BINF_MASK (0x10U)
17205#define DDRPHY_BISTRR_BINF_SHIFT (4U)
17206/*! BINF - BIST Infinite Run
17207 */
17208#define DDRPHY_BISTRR_BINF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BINF_SHIFT)) & DDRPHY_BISTRR_BINF_MASK)
17209#define DDRPHY_BISTRR_NFAIL_MASK (0x1FE0U)
17210#define DDRPHY_BISTRR_NFAIL_SHIFT (5U)
17211/*! NFAIL - Number of Failures
17212 */
17213#define DDRPHY_BISTRR_NFAIL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_NFAIL_SHIFT)) & DDRPHY_BISTRR_NFAIL_MASK)
17214#define DDRPHY_BISTRR_BSONF_MASK (0x2000U)
17215#define DDRPHY_BISTRR_BSONF_SHIFT (13U)
17216/*! BSONF - BIST Stop On Nth Fail
17217 */
17218#define DDRPHY_BISTRR_BSONF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BSONF_SHIFT)) & DDRPHY_BISTRR_BSONF_MASK)
17219#define DDRPHY_BISTRR_BDXEN_MASK (0x4000U)
17220#define DDRPHY_BISTRR_BDXEN_SHIFT (14U)
17221/*! BDXEN - BIST DATX8 Enable
17222 */
17223#define DDRPHY_BISTRR_BDXEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BDXEN_SHIFT)) & DDRPHY_BISTRR_BDXEN_MASK)
17224#define DDRPHY_BISTRR_BACEN_MASK (0x8000U)
17225#define DDRPHY_BISTRR_BACEN_SHIFT (15U)
17226/*! BACEN - BIST AC Enable
17227 */
17228#define DDRPHY_BISTRR_BACEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BACEN_SHIFT)) & DDRPHY_BISTRR_BACEN_MASK)
17229#define DDRPHY_BISTRR_BDMEN_MASK (0x10000U)
17230#define DDRPHY_BISTRR_BDMEN_SHIFT (16U)
17231/*! BDMEN - BIST Data Mask Enable
17232 */
17233#define DDRPHY_BISTRR_BDMEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BDMEN_SHIFT)) & DDRPHY_BISTRR_BDMEN_MASK)
17234#define DDRPHY_BISTRR_BDXDPAT_MASK (0x60000U)
17235#define DDRPHY_BISTRR_BDXDPAT_SHIFT (17U)
17236/*! BDXDPAT - BIST Data Pattern
17237 */
17238#define DDRPHY_BISTRR_BDXDPAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BDXDPAT_SHIFT)) & DDRPHY_BISTRR_BDXDPAT_MASK)
17239#define DDRPHY_BISTRR_BDXSEL_MASK (0x780000U)
17240#define DDRPHY_BISTRR_BDXSEL_SHIFT (19U)
17241/*! BDXSEL - BIST DATX8 Select
17242 */
17243#define DDRPHY_BISTRR_BDXSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BDXSEL_SHIFT)) & DDRPHY_BISTRR_BDXSEL_MASK)
17244#define DDRPHY_BISTRR_BCKSEL_MASK (0x1800000U)
17245#define DDRPHY_BISTRR_BCKSEL_SHIFT (23U)
17246/*! BCKSEL - BIST CK Select
17247 */
17248#define DDRPHY_BISTRR_BCKSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BCKSEL_SHIFT)) & DDRPHY_BISTRR_BCKSEL_MASK)
17249#define DDRPHY_BISTRR_BCCSEL_MASK (0x2000000U)
17250#define DDRPHY_BISTRR_BCCSEL_SHIFT (25U)
17251/*! BCCSEL - BIST Clock Cycle Select
17252 */
17253#define DDRPHY_BISTRR_BCCSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BCCSEL_SHIFT)) & DDRPHY_BISTRR_BCCSEL_MASK)
17254#define DDRPHY_BISTRR_BACDPAT_MASK (0xC000000U)
17255#define DDRPHY_BISTRR_BACDPAT_SHIFT (26U)
17256/*! BACDPAT - BIST AC Data Pattern
17257 */
17258#define DDRPHY_BISTRR_BACDPAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BACDPAT_SHIFT)) & DDRPHY_BISTRR_BACDPAT_MASK)
17259#define DDRPHY_BISTRR_BSOMA_MASK (0x10000000U)
17260#define DDRPHY_BISTRR_BSOMA_SHIFT (28U)
17261/*! BSOMA - BIST Stop on Maximum Address
17262 */
17263#define DDRPHY_BISTRR_BSOMA(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BSOMA_SHIFT)) & DDRPHY_BISTRR_BSOMA_MASK)
17264#define DDRPHY_BISTRR_BPRBST_MASK (0x20000000U)
17265#define DDRPHY_BISTRR_BPRBST_SHIFT (29U)
17266/*! BPRBST - BIST PRBS Type.
17267 */
17268#define DDRPHY_BISTRR_BPRBST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_BPRBST_SHIFT)) & DDRPHY_BISTRR_BPRBST_MASK)
17269#define DDRPHY_BISTRR_RESERVED_31_30_MASK (0xC0000000U)
17270#define DDRPHY_BISTRR_RESERVED_31_30_SHIFT (30U)
17271/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
17272 */
17273#define DDRPHY_BISTRR_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTRR_RESERVED_31_30_SHIFT)) & DDRPHY_BISTRR_RESERVED_31_30_MASK)
17274/*! @} */
17275
17276/*! @name BISTWCR - BIST Word Count Register */
17277/*! @{ */
17278#define DDRPHY_BISTWCR_BDXWCNT_MASK (0xFFFFU)
17279#define DDRPHY_BISTWCR_BDXWCNT_SHIFT (0U)
17280/*! BDXWCNT - BIST DX Word Count
17281 */
17282#define DDRPHY_BISTWCR_BDXWCNT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWCR_BDXWCNT_SHIFT)) & DDRPHY_BISTWCR_BDXWCNT_MASK)
17283#define DDRPHY_BISTWCR_BACWCNT_MASK (0xFFFF0000U)
17284#define DDRPHY_BISTWCR_BACWCNT_SHIFT (16U)
17285/*! BACWCNT - BIST AC Word Count
17286 */
17287#define DDRPHY_BISTWCR_BACWCNT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWCR_BACWCNT_SHIFT)) & DDRPHY_BISTWCR_BACWCNT_MASK)
17288/*! @} */
17289
17290/*! @name BISTMSKR0 - BIST Mask Register 0 */
17291/*! @{ */
17292#define DDRPHY_BISTMSKR0_AMSK_MASK (0x3FFFFU)
17293#define DDRPHY_BISTMSKR0_AMSK_SHIFT (0U)
17294/*! AMSK - Mask bit for each of the up to 16 address bits.
17295 */
17296#define DDRPHY_BISTMSKR0_AMSK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR0_AMSK_SHIFT)) & DDRPHY_BISTMSKR0_AMSK_MASK)
17297#define DDRPHY_BISTMSKR0_RESERVED_18_MASK (0x40000U)
17298#define DDRPHY_BISTMSKR0_RESERVED_18_SHIFT (18U)
17299/*! RESERVED_18 - Reserved. Return zeros on reads.
17300 */
17301#define DDRPHY_BISTMSKR0_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR0_RESERVED_18_SHIFT)) & DDRPHY_BISTMSKR0_RESERVED_18_MASK)
17302#define DDRPHY_BISTMSKR0_ACTMSK_MASK (0x80000U)
17303#define DDRPHY_BISTMSKR0_ACTMSK_SHIFT (19U)
17304/*! ACTMSK - Mask bit for the RAS.
17305 */
17306#define DDRPHY_BISTMSKR0_ACTMSK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR0_ACTMSK_SHIFT)) & DDRPHY_BISTMSKR0_ACTMSK_MASK)
17307#define DDRPHY_BISTMSKR0_CSMSK_MASK (0x100000U)
17308#define DDRPHY_BISTMSKR0_CSMSK_SHIFT (20U)
17309/*! CSMSK - Mask bit for each of the up to 12 CS_N bits.
17310 */
17311#define DDRPHY_BISTMSKR0_CSMSK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR0_CSMSK_SHIFT)) & DDRPHY_BISTMSKR0_CSMSK_MASK)
17312#define DDRPHY_BISTMSKR0_CSMSK_RSVD_MASK (0xFFE00000U)
17313#define DDRPHY_BISTMSKR0_CSMSK_RSVD_SHIFT (21U)
17314/*! CSMSK_RSVD - Reserved. Return zeros on reads.
17315 */
17316#define DDRPHY_BISTMSKR0_CSMSK_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR0_CSMSK_RSVD_SHIFT)) & DDRPHY_BISTMSKR0_CSMSK_RSVD_MASK)
17317/*! @} */
17318
17319/*! @name BISTMSKR1 - BIST Mask Register 1 */
17320/*! @{ */
17321#define DDRPHY_BISTMSKR1_RESERVED_3_0_MASK (0xFU)
17322#define DDRPHY_BISTMSKR1_RESERVED_3_0_SHIFT (0U)
17323/*! RESERVED_3_0 - Reserved. Return zeros on reads.
17324 */
17325#define DDRPHY_BISTMSKR1_RESERVED_3_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_RESERVED_3_0_SHIFT)) & DDRPHY_BISTMSKR1_RESERVED_3_0_MASK)
17326#define DDRPHY_BISTMSKR1_BAMSK_MASK (0xF0U)
17327#define DDRPHY_BISTMSKR1_BAMSK_SHIFT (4U)
17328/*! BAMSK - Mask bit for each of the up to 4 bank address bits.
17329 */
17330#define DDRPHY_BISTMSKR1_BAMSK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_BAMSK_SHIFT)) & DDRPHY_BISTMSKR1_BAMSK_MASK)
17331#define DDRPHY_BISTMSKR1_CKEMSK_MASK (0x100U)
17332#define DDRPHY_BISTMSKR1_CKEMSK_SHIFT (8U)
17333/*! CKEMSK - Mask bit for each of the up to 8 CKE bits.
17334 */
17335#define DDRPHY_BISTMSKR1_CKEMSK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_CKEMSK_SHIFT)) & DDRPHY_BISTMSKR1_CKEMSK_MASK)
17336#define DDRPHY_BISTMSKR1_CKEMSK_RSVD_MASK (0xFE00U)
17337#define DDRPHY_BISTMSKR1_CKEMSK_RSVD_SHIFT (9U)
17338/*! CKEMSK_RSVD - Reserved. Return zeros on reads.
17339 */
17340#define DDRPHY_BISTMSKR1_CKEMSK_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_CKEMSK_RSVD_SHIFT)) & DDRPHY_BISTMSKR1_CKEMSK_RSVD_MASK)
17341#define DDRPHY_BISTMSKR1_ODTMSK_MASK (0x10000U)
17342#define DDRPHY_BISTMSKR1_ODTMSK_SHIFT (16U)
17343/*! ODTMSK - Mask bit for each of the up to 8 ODT bits.
17344 */
17345#define DDRPHY_BISTMSKR1_ODTMSK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_ODTMSK_SHIFT)) & DDRPHY_BISTMSKR1_ODTMSK_MASK)
17346#define DDRPHY_BISTMSKR1_ODTMSK_RSVD_MASK (0xFE0000U)
17347#define DDRPHY_BISTMSKR1_ODTMSK_RSVD_SHIFT (17U)
17348/*! ODTMSK_RSVD - Reserved. Return zeros on reads.
17349 */
17350#define DDRPHY_BISTMSKR1_ODTMSK_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_ODTMSK_RSVD_SHIFT)) & DDRPHY_BISTMSKR1_ODTMSK_RSVD_MASK)
17351#define DDRPHY_BISTMSKR1_CIDMSK_MASK (0x1000000U)
17352#define DDRPHY_BISTMSKR1_CIDMSK_SHIFT (24U)
17353/*! CIDMSK - Mask bits for each of the up to 3 Chip IP bits.
17354 */
17355#define DDRPHY_BISTMSKR1_CIDMSK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_CIDMSK_SHIFT)) & DDRPHY_BISTMSKR1_CIDMSK_MASK)
17356#define DDRPHY_BISTMSKR1_CIDMSK_RSVD_MASK (0x6000000U)
17357#define DDRPHY_BISTMSKR1_CIDMSK_RSVD_SHIFT (25U)
17358/*! CIDMSK_RSVD - Reserved. Return zeros on reads.
17359 */
17360#define DDRPHY_BISTMSKR1_CIDMSK_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_CIDMSK_RSVD_SHIFT)) & DDRPHY_BISTMSKR1_CIDMSK_RSVD_MASK)
17361#define DDRPHY_BISTMSKR1_PARINMSK_MASK (0x8000000U)
17362#define DDRPHY_BISTMSKR1_PARINMSK_SHIFT (27U)
17363/*! PARINMSK - Mask bit for the PAR_IN.
17364 */
17365#define DDRPHY_BISTMSKR1_PARINMSK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_PARINMSK_SHIFT)) & DDRPHY_BISTMSKR1_PARINMSK_MASK)
17366#define DDRPHY_BISTMSKR1_DMMSK_MASK (0xF0000000U)
17367#define DDRPHY_BISTMSKR1_DMMSK_SHIFT (28U)
17368/*! DMMSK - Mask bit for the data mask (DM) bit.
17369 */
17370#define DDRPHY_BISTMSKR1_DMMSK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR1_DMMSK_SHIFT)) & DDRPHY_BISTMSKR1_DMMSK_MASK)
17371/*! @} */
17372
17373/*! @name BISTMSKR2 - BIST Mask Register 2 */
17374/*! @{ */
17375#define DDRPHY_BISTMSKR2_DQMSK_MASK (0xFFFFFFFFU)
17376#define DDRPHY_BISTMSKR2_DQMSK_SHIFT (0U)
17377/*! DQMSK - Mask bit for each of the 8 data (DQ) bits
17378 */
17379#define DDRPHY_BISTMSKR2_DQMSK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTMSKR2_DQMSK_SHIFT)) & DDRPHY_BISTMSKR2_DQMSK_MASK)
17380/*! @} */
17381
17382/*! @name BISTLSR - BIST LFSR Seed Register */
17383/*! @{ */
17384#define DDRPHY_BISTLSR_SEED_MASK (0xFFFFFFFFU)
17385#define DDRPHY_BISTLSR_SEED_SHIFT (0U)
17386/*! SEED - LFSR seed for pseudo-random BIST patterns
17387 */
17388#define DDRPHY_BISTLSR_SEED(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTLSR_SEED_SHIFT)) & DDRPHY_BISTLSR_SEED_MASK)
17389/*! @} */
17390
17391/*! @name BISTAR0 - BIST Address Register 0 */
17392/*! @{ */
17393#define DDRPHY_BISTAR0_BCOL_MASK (0xFFFU)
17394#define DDRPHY_BISTAR0_BCOL_SHIFT (0U)
17395/*! BCOL - BIST Column Address
17396 */
17397#define DDRPHY_BISTAR0_BCOL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR0_BCOL_SHIFT)) & DDRPHY_BISTAR0_BCOL_MASK)
17398#define DDRPHY_BISTAR0_RESERVED_27_12_MASK (0xFFFF000U)
17399#define DDRPHY_BISTAR0_RESERVED_27_12_SHIFT (12U)
17400/*! RESERVED_27_12 - Reserved. Return zeroes on reads.
17401 */
17402#define DDRPHY_BISTAR0_RESERVED_27_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR0_RESERVED_27_12_SHIFT)) & DDRPHY_BISTAR0_RESERVED_27_12_MASK)
17403#define DDRPHY_BISTAR0_BBANK_MASK (0xF0000000U)
17404#define DDRPHY_BISTAR0_BBANK_SHIFT (28U)
17405/*! BBANK - BIST Bank Address
17406 */
17407#define DDRPHY_BISTAR0_BBANK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR0_BBANK_SHIFT)) & DDRPHY_BISTAR0_BBANK_MASK)
17408/*! @} */
17409
17410/*! @name BISTAR1 - BIST Address Register 1 */
17411/*! @{ */
17412#define DDRPHY_BISTAR1_BRANK_MASK (0xFU)
17413#define DDRPHY_BISTAR1_BRANK_SHIFT (0U)
17414/*! BRANK - BIST Rank
17415 */
17416#define DDRPHY_BISTAR1_BRANK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR1_BRANK_SHIFT)) & DDRPHY_BISTAR1_BRANK_MASK)
17417#define DDRPHY_BISTAR1_BAINC_MASK (0xFFF0U)
17418#define DDRPHY_BISTAR1_BAINC_SHIFT (4U)
17419/*! BAINC - BIST Address Increment
17420 */
17421#define DDRPHY_BISTAR1_BAINC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR1_BAINC_SHIFT)) & DDRPHY_BISTAR1_BAINC_MASK)
17422#define DDRPHY_BISTAR1_BMRANK_MASK (0xF0000U)
17423#define DDRPHY_BISTAR1_BMRANK_SHIFT (16U)
17424/*! BMRANK - BIST Maximum Rank
17425 */
17426#define DDRPHY_BISTAR1_BMRANK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR1_BMRANK_SHIFT)) & DDRPHY_BISTAR1_BMRANK_MASK)
17427#define DDRPHY_BISTAR1_RESERVED_31_20_MASK (0xFFF00000U)
17428#define DDRPHY_BISTAR1_RESERVED_31_20_SHIFT (20U)
17429/*! RESERVED_31_20 - Reserved. Return zeroes on reads.
17430 */
17431#define DDRPHY_BISTAR1_RESERVED_31_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR1_RESERVED_31_20_SHIFT)) & DDRPHY_BISTAR1_RESERVED_31_20_MASK)
17432/*! @} */
17433
17434/*! @name BISTAR2 - BIST Address Register 2 */
17435/*! @{ */
17436#define DDRPHY_BISTAR2_BMCOL_MASK (0xFFFU)
17437#define DDRPHY_BISTAR2_BMCOL_SHIFT (0U)
17438/*! BMCOL - BIST Maximum Column Address
17439 */
17440#define DDRPHY_BISTAR2_BMCOL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR2_BMCOL_SHIFT)) & DDRPHY_BISTAR2_BMCOL_MASK)
17441#define DDRPHY_BISTAR2_RESERVED_27_12_MASK (0xFFFF000U)
17442#define DDRPHY_BISTAR2_RESERVED_27_12_SHIFT (12U)
17443/*! RESERVED_27_12 - Reserved. Return zeroes on reads.
17444 */
17445#define DDRPHY_BISTAR2_RESERVED_27_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR2_RESERVED_27_12_SHIFT)) & DDRPHY_BISTAR2_RESERVED_27_12_MASK)
17446#define DDRPHY_BISTAR2_BMBANK_MASK (0xF0000000U)
17447#define DDRPHY_BISTAR2_BMBANK_SHIFT (28U)
17448/*! BMBANK - BIST Maximum Bank Address
17449 */
17450#define DDRPHY_BISTAR2_BMBANK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR2_BMBANK_SHIFT)) & DDRPHY_BISTAR2_BMBANK_MASK)
17451/*! @} */
17452
17453/*! @name BISTAR3 - BIST Address Register 3 */
17454/*! @{ */
17455#define DDRPHY_BISTAR3_BROW_MASK (0x3FFFFU)
17456#define DDRPHY_BISTAR3_BROW_SHIFT (0U)
17457/*! BROW - BIST Row Address
17458 */
17459#define DDRPHY_BISTAR3_BROW(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR3_BROW_SHIFT)) & DDRPHY_BISTAR3_BROW_MASK)
17460#define DDRPHY_BISTAR3_RESERVED_31_18_MASK (0xFFFC0000U)
17461#define DDRPHY_BISTAR3_RESERVED_31_18_SHIFT (18U)
17462/*! RESERVED_31_18 - Reserved. Return zeroes on reads.
17463 */
17464#define DDRPHY_BISTAR3_RESERVED_31_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR3_RESERVED_31_18_SHIFT)) & DDRPHY_BISTAR3_RESERVED_31_18_MASK)
17465/*! @} */
17466
17467/*! @name BISTAR4 - BIST Address Register 4 */
17468/*! @{ */
17469#define DDRPHY_BISTAR4_BMROW_MASK (0x3FFFFU)
17470#define DDRPHY_BISTAR4_BMROW_SHIFT (0U)
17471/*! BMROW - BIST Maximum Row Address
17472 */
17473#define DDRPHY_BISTAR4_BMROW(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR4_BMROW_SHIFT)) & DDRPHY_BISTAR4_BMROW_MASK)
17474#define DDRPHY_BISTAR4_RESERVED_31_18_MASK (0xFFFC0000U)
17475#define DDRPHY_BISTAR4_RESERVED_31_18_SHIFT (18U)
17476/*! RESERVED_31_18 - Reserved. Return zeroes on reads.
17477 */
17478#define DDRPHY_BISTAR4_RESERVED_31_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTAR4_RESERVED_31_18_SHIFT)) & DDRPHY_BISTAR4_RESERVED_31_18_MASK)
17479/*! @} */
17480
17481/*! @name BISTUDPR - BIST User Data Pattern Register */
17482/*! @{ */
17483#define DDRPHY_BISTUDPR_BUDP0_MASK (0xFFFFU)
17484#define DDRPHY_BISTUDPR_BUDP0_SHIFT (0U)
17485/*! BUDP0 - BIST User Data Pattern 0
17486 */
17487#define DDRPHY_BISTUDPR_BUDP0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTUDPR_BUDP0_SHIFT)) & DDRPHY_BISTUDPR_BUDP0_MASK)
17488#define DDRPHY_BISTUDPR_BUDP1_MASK (0xFFFF0000U)
17489#define DDRPHY_BISTUDPR_BUDP1_SHIFT (16U)
17490/*! BUDP1 - BIST User Data Pattern 1
17491 */
17492#define DDRPHY_BISTUDPR_BUDP1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTUDPR_BUDP1_SHIFT)) & DDRPHY_BISTUDPR_BUDP1_MASK)
17493/*! @} */
17494
17495/*! @name BISTGSR - BIST General Status Register */
17496/*! @{ */
17497#define DDRPHY_BISTGSR_BDONE_MASK (0x1U)
17498#define DDRPHY_BISTGSR_BDONE_SHIFT (0U)
17499/*! BDONE - BIST Done
17500 */
17501#define DDRPHY_BISTGSR_BDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_BDONE_SHIFT)) & DDRPHY_BISTGSR_BDONE_MASK)
17502#define DDRPHY_BISTGSR_BACERR_MASK (0x2U)
17503#define DDRPHY_BISTGSR_BACERR_SHIFT (1U)
17504/*! BACERR - BIST Address/Command Error
17505 */
17506#define DDRPHY_BISTGSR_BACERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_BACERR_SHIFT)) & DDRPHY_BISTGSR_BACERR_MASK)
17507#define DDRPHY_BISTGSR_BDXERR_MASK (0x7FCU)
17508#define DDRPHY_BISTGSR_BDXERR_SHIFT (2U)
17509/*! BDXERR - BIST Data Error
17510 */
17511#define DDRPHY_BISTGSR_BDXERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_BDXERR_SHIFT)) & DDRPHY_BISTGSR_BDXERR_MASK)
17512#define DDRPHY_BISTGSR_RESERVED_11_MASK (0x800U)
17513#define DDRPHY_BISTGSR_RESERVED_11_SHIFT (11U)
17514/*! RESERVED_11 - Reserved. Return zeros on reads.
17515 */
17516#define DDRPHY_BISTGSR_RESERVED_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_RESERVED_11_SHIFT)) & DDRPHY_BISTGSR_RESERVED_11_MASK)
17517#define DDRPHY_BISTGSR_RESERVED_19_12_MASK (0xFF000U)
17518#define DDRPHY_BISTGSR_RESERVED_19_12_SHIFT (12U)
17519/*! RESERVED_19_12 - Reserved. Return zeroes on reads.
17520 */
17521#define DDRPHY_BISTGSR_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_RESERVED_19_12_SHIFT)) & DDRPHY_BISTGSR_RESERVED_19_12_MASK)
17522#define DDRPHY_BISTGSR_DMBER_MASK (0xFF00000U)
17523#define DDRPHY_BISTGSR_DMBER_SHIFT (20U)
17524/*! DMBER - DM Bit Error
17525 */
17526#define DDRPHY_BISTGSR_DMBER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_DMBER_SHIFT)) & DDRPHY_BISTGSR_DMBER_MASK)
17527#define DDRPHY_BISTGSR_RASBER_MASK (0x30000000U)
17528#define DDRPHY_BISTGSR_RASBER_SHIFT (28U)
17529/*! RASBER - RAS_n/ACT_n Bit Error
17530 */
17531#define DDRPHY_BISTGSR_RASBER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_RASBER_SHIFT)) & DDRPHY_BISTGSR_RASBER_MASK)
17532#define DDRPHY_BISTGSR_RESERVED_31_30_MASK (0xC0000000U)
17533#define DDRPHY_BISTGSR_RESERVED_31_30_SHIFT (30U)
17534/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
17535 */
17536#define DDRPHY_BISTGSR_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTGSR_RESERVED_31_30_SHIFT)) & DDRPHY_BISTGSR_RESERVED_31_30_MASK)
17537/*! @} */
17538
17539/*! @name BISTWER0 - BIST Word Error Register 0 */
17540/*! @{ */
17541#define DDRPHY_BISTWER0_ACWER_MASK (0x3FFFFU)
17542#define DDRPHY_BISTWER0_ACWER_SHIFT (0U)
17543/*! ACWER - Address/Command Word Error
17544 */
17545#define DDRPHY_BISTWER0_ACWER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWER0_ACWER_SHIFT)) & DDRPHY_BISTWER0_ACWER_MASK)
17546#define DDRPHY_BISTWER0_RESERVED_31_18_MASK (0xFFFC0000U)
17547#define DDRPHY_BISTWER0_RESERVED_31_18_SHIFT (18U)
17548/*! RESERVED_31_18 - Reserved. Return zeroes on reads.
17549 */
17550#define DDRPHY_BISTWER0_RESERVED_31_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWER0_RESERVED_31_18_SHIFT)) & DDRPHY_BISTWER0_RESERVED_31_18_MASK)
17551/*! @} */
17552
17553/*! @name BISTWER1 - BIST Word Error Register 1 */
17554/*! @{ */
17555#define DDRPHY_BISTWER1_DXWER_MASK (0xFFFFU)
17556#define DDRPHY_BISTWER1_DXWER_SHIFT (0U)
17557/*! DXWER - Byte Word Error
17558 */
17559#define DDRPHY_BISTWER1_DXWER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWER1_DXWER_SHIFT)) & DDRPHY_BISTWER1_DXWER_MASK)
17560#define DDRPHY_BISTWER1_RESERVED_31_16_MASK (0xFFFF0000U)
17561#define DDRPHY_BISTWER1_RESERVED_31_16_SHIFT (16U)
17562/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
17563 */
17564#define DDRPHY_BISTWER1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWER1_RESERVED_31_16_SHIFT)) & DDRPHY_BISTWER1_RESERVED_31_16_MASK)
17565/*! @} */
17566
17567/*! @name BISTBER0 - BIST Bit Error Register 0 */
17568/*! @{ */
17569#define DDRPHY_BISTBER0_ABER_MASK (0xFFFFFFFFU)
17570#define DDRPHY_BISTBER0_ABER_SHIFT (0U)
17571/*! ABER - Address Bit Error
17572 */
17573#define DDRPHY_BISTBER0_ABER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER0_ABER_SHIFT)) & DDRPHY_BISTBER0_ABER_MASK)
17574/*! @} */
17575
17576/*! @name BISTBER1 - BIST Bit Error Register 1 */
17577/*! @{ */
17578#define DDRPHY_BISTBER1_BABER_MASK (0xFFU)
17579#define DDRPHY_BISTBER1_BABER_SHIFT (0U)
17580/*! BABER - Bank Address Bit Error
17581 */
17582#define DDRPHY_BISTBER1_BABER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER1_BABER_SHIFT)) & DDRPHY_BISTBER1_BABER_MASK)
17583#define DDRPHY_BISTBER1_CSBER_MASK (0x300U)
17584#define DDRPHY_BISTBER1_CSBER_SHIFT (8U)
17585/*! CSBER - CS_N Bit Error.
17586 */
17587#define DDRPHY_BISTBER1_CSBER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER1_CSBER_SHIFT)) & DDRPHY_BISTBER1_CSBER_MASK)
17588#define DDRPHY_BISTBER1_CSBER_RSVD_MASK (0xFFFFFC00U)
17589#define DDRPHY_BISTBER1_CSBER_RSVD_SHIFT (10U)
17590/*! CSBER_RSVD - Reserved. Return zeros on reads.
17591 */
17592#define DDRPHY_BISTBER1_CSBER_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER1_CSBER_RSVD_SHIFT)) & DDRPHY_BISTBER1_CSBER_RSVD_MASK)
17593/*! @} */
17594
17595/*! @name BISTBER2 - BIST Bit Error Register 2 */
17596/*! @{ */
17597#define DDRPHY_BISTBER2_DQBER0_MASK (0xFFFFFFFFU)
17598#define DDRPHY_BISTBER2_DQBER0_SHIFT (0U)
17599/*! DQBER0 - Data Bit Error
17600 */
17601#define DDRPHY_BISTBER2_DQBER0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER2_DQBER0_SHIFT)) & DDRPHY_BISTBER2_DQBER0_MASK)
17602/*! @} */
17603
17604/*! @name BISTBER3 - BIST Bit Error Register 3 */
17605/*! @{ */
17606#define DDRPHY_BISTBER3_DQBER1_MASK (0xFFFFFFFFU)
17607#define DDRPHY_BISTBER3_DQBER1_SHIFT (0U)
17608/*! DQBER1 - Data Bit Error
17609 */
17610#define DDRPHY_BISTBER3_DQBER1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER3_DQBER1_SHIFT)) & DDRPHY_BISTBER3_DQBER1_MASK)
17611/*! @} */
17612
17613/*! @name BISTBER4 - BIST Bit Error Register 4 */
17614/*! @{ */
17615#define DDRPHY_BISTBER4_ABER_MASK (0xFU)
17616#define DDRPHY_BISTBER4_ABER_SHIFT (0U)
17617/*! ABER - Address Bit Error
17618 */
17619#define DDRPHY_BISTBER4_ABER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER4_ABER_SHIFT)) & DDRPHY_BISTBER4_ABER_MASK)
17620#define DDRPHY_BISTBER4_RESERVED_7_4_MASK (0xF0U)
17621#define DDRPHY_BISTBER4_RESERVED_7_4_SHIFT (4U)
17622/*! RESERVED_7_4 - Reserved. Return zeroes on reads.
17623 */
17624#define DDRPHY_BISTBER4_RESERVED_7_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER4_RESERVED_7_4_SHIFT)) & DDRPHY_BISTBER4_RESERVED_7_4_MASK)
17625#define DDRPHY_BISTBER4_CIDBER_MASK (0x300U)
17626#define DDRPHY_BISTBER4_CIDBER_SHIFT (8U)
17627/*! CIDBER - Chip ID Bit Error.
17628 */
17629#define DDRPHY_BISTBER4_CIDBER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER4_CIDBER_SHIFT)) & DDRPHY_BISTBER4_CIDBER_MASK)
17630#define DDRPHY_BISTBER4_CIDBER_RSVD_MASK (0x3C00U)
17631#define DDRPHY_BISTBER4_CIDBER_RSVD_SHIFT (10U)
17632/*! CIDBER_RSVD - Reserved. Return zeros on reads.
17633 */
17634#define DDRPHY_BISTBER4_CIDBER_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER4_CIDBER_RSVD_SHIFT)) & DDRPHY_BISTBER4_CIDBER_RSVD_MASK)
17635#define DDRPHY_BISTBER4_RESERVED_31_14_MASK (0xFFFFC000U)
17636#define DDRPHY_BISTBER4_RESERVED_31_14_SHIFT (14U)
17637/*! RESERVED_31_14 - Reserved. Return zeroes on reads.
17638 */
17639#define DDRPHY_BISTBER4_RESERVED_31_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER4_RESERVED_31_14_SHIFT)) & DDRPHY_BISTBER4_RESERVED_31_14_MASK)
17640/*! @} */
17641
17642/*! @name BISTWCSR - BIST Word Count Status Register */
17643/*! @{ */
17644#define DDRPHY_BISTWCSR_ACWCNT_MASK (0xFFFFU)
17645#define DDRPHY_BISTWCSR_ACWCNT_SHIFT (0U)
17646/*! ACWCNT - Address/Command Word Count
17647 */
17648#define DDRPHY_BISTWCSR_ACWCNT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWCSR_ACWCNT_SHIFT)) & DDRPHY_BISTWCSR_ACWCNT_MASK)
17649#define DDRPHY_BISTWCSR_DXWCNT_MASK (0xFFFF0000U)
17650#define DDRPHY_BISTWCSR_DXWCNT_SHIFT (16U)
17651/*! DXWCNT - Byte Word Count
17652 */
17653#define DDRPHY_BISTWCSR_DXWCNT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTWCSR_DXWCNT_SHIFT)) & DDRPHY_BISTWCSR_DXWCNT_MASK)
17654/*! @} */
17655
17656/*! @name BISTFWR0 - BIST Fail Word Register 0 */
17657/*! @{ */
17658#define DDRPHY_BISTFWR0_AWEBS_MASK (0x3FFFFU)
17659#define DDRPHY_BISTFWR0_AWEBS_SHIFT (0U)
17660/*! AWEBS - Bit status during a word error for each of the up to 16 address bits
17661 */
17662#define DDRPHY_BISTFWR0_AWEBS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR0_AWEBS_SHIFT)) & DDRPHY_BISTFWR0_AWEBS_MASK)
17663#define DDRPHY_BISTFWR0_ACTWEBS_MASK (0x40000U)
17664#define DDRPHY_BISTFWR0_ACTWEBS_SHIFT (18U)
17665/*! ACTWEBS - Bit status during a word error for the RAS.
17666 */
17667#define DDRPHY_BISTFWR0_ACTWEBS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR0_ACTWEBS_SHIFT)) & DDRPHY_BISTFWR0_ACTWEBS_MASK)
17668#define DDRPHY_BISTFWR0_RESERVED_19_MASK (0x80000U)
17669#define DDRPHY_BISTFWR0_RESERVED_19_SHIFT (19U)
17670/*! RESERVED_19 - Reserved. Return zeroes on reads.
17671 */
17672#define DDRPHY_BISTFWR0_RESERVED_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR0_RESERVED_19_SHIFT)) & DDRPHY_BISTFWR0_RESERVED_19_MASK)
17673#define DDRPHY_BISTFWR0_CSWEBS_MASK (0x100000U)
17674#define DDRPHY_BISTFWR0_CSWEBS_SHIFT (20U)
17675/*! CSWEBS - Bit status during a word error for each of the up to 12 CS# bits.
17676 */
17677#define DDRPHY_BISTFWR0_CSWEBS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR0_CSWEBS_SHIFT)) & DDRPHY_BISTFWR0_CSWEBS_MASK)
17678#define DDRPHY_BISTFWR0_CSWEBS_RSVD_MASK (0xFFE00000U)
17679#define DDRPHY_BISTFWR0_CSWEBS_RSVD_SHIFT (21U)
17680/*! CSWEBS_RSVD - Reserved. Return zeros on reads.
17681 */
17682#define DDRPHY_BISTFWR0_CSWEBS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR0_CSWEBS_RSVD_SHIFT)) & DDRPHY_BISTFWR0_CSWEBS_RSVD_MASK)
17683/*! @} */
17684
17685/*! @name BISTFWR1 - BIST Fail Word Register 1 */
17686/*! @{ */
17687#define DDRPHY_BISTFWR1_CKEWEBS_MASK (0x1U)
17688#define DDRPHY_BISTFWR1_CKEWEBS_SHIFT (0U)
17689/*! CKEWEBS - Bit status during a word error for each of the up to 8 CKE bits.
17690 */
17691#define DDRPHY_BISTFWR1_CKEWEBS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_CKEWEBS_SHIFT)) & DDRPHY_BISTFWR1_CKEWEBS_MASK)
17692#define DDRPHY_BISTFWR1_CKEWEBS_RSVD_MASK (0xFEU)
17693#define DDRPHY_BISTFWR1_CKEWEBS_RSVD_SHIFT (1U)
17694/*! CKEWEBS_RSVD - Reserved. Return zeros on reads.
17695 */
17696#define DDRPHY_BISTFWR1_CKEWEBS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_CKEWEBS_RSVD_SHIFT)) & DDRPHY_BISTFWR1_CKEWEBS_RSVD_MASK)
17697#define DDRPHY_BISTFWR1_ODTWEBS_MASK (0x100U)
17698#define DDRPHY_BISTFWR1_ODTWEBS_SHIFT (8U)
17699/*! ODTWEBS - Bit status during a word error for each of the up to 8 ODT bits.
17700 */
17701#define DDRPHY_BISTFWR1_ODTWEBS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_ODTWEBS_SHIFT)) & DDRPHY_BISTFWR1_ODTWEBS_MASK)
17702#define DDRPHY_BISTFWR1_ODTWEBS_RSVD_MASK (0xFE00U)
17703#define DDRPHY_BISTFWR1_ODTWEBS_RSVD_SHIFT (9U)
17704/*! ODTWEBS_RSVD - Reserved. Return zeros on reads.
17705 */
17706#define DDRPHY_BISTFWR1_ODTWEBS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_ODTWEBS_RSVD_SHIFT)) & DDRPHY_BISTFWR1_ODTWEBS_RSVD_MASK)
17707#define DDRPHY_BISTFWR1_BAWEBS_MASK (0xF0000U)
17708#define DDRPHY_BISTFWR1_BAWEBS_SHIFT (16U)
17709/*! BAWEBS - Bit status during a word error for each of the bank address bits
17710 */
17711#define DDRPHY_BISTFWR1_BAWEBS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_BAWEBS_SHIFT)) & DDRPHY_BISTFWR1_BAWEBS_MASK)
17712#define DDRPHY_BISTFWR1_CIDWEBS_MASK (0x100000U)
17713#define DDRPHY_BISTFWR1_CIDWEBS_SHIFT (20U)
17714/*! CIDWEBS - Bit status during a word error for each of the up to 3 chip ID bits.
17715 */
17716#define DDRPHY_BISTFWR1_CIDWEBS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_CIDWEBS_SHIFT)) & DDRPHY_BISTFWR1_CIDWEBS_MASK)
17717#define DDRPHY_BISTFWR1_CIDWEBS_RSVD_MASK (0x600000U)
17718#define DDRPHY_BISTFWR1_CIDWEBS_RSVD_SHIFT (21U)
17719/*! CIDWEBS_RSVD - Reserved. Return zeros on reads.
17720 */
17721#define DDRPHY_BISTFWR1_CIDWEBS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_CIDWEBS_RSVD_SHIFT)) & DDRPHY_BISTFWR1_CIDWEBS_RSVD_MASK)
17722#define DDRPHY_BISTFWR1_RESERVED_23_22_MASK (0x800000U)
17723#define DDRPHY_BISTFWR1_RESERVED_23_22_SHIFT (23U)
17724/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
17725 */
17726#define DDRPHY_BISTFWR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_RESERVED_23_22_SHIFT)) & DDRPHY_BISTFWR1_RESERVED_23_22_MASK)
17727#define DDRPHY_BISTFWR1_RESERVED_27_24_MASK (0xF000000U)
17728#define DDRPHY_BISTFWR1_RESERVED_27_24_SHIFT (24U)
17729/*! RESERVED_27_24 - Reserved. Return zeroes on reads.
17730 */
17731#define DDRPHY_BISTFWR1_RESERVED_27_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_RESERVED_27_24_SHIFT)) & DDRPHY_BISTFWR1_RESERVED_27_24_MASK)
17732#define DDRPHY_BISTFWR1_DMWEBS_MASK (0xF0000000U)
17733#define DDRPHY_BISTFWR1_DMWEBS_SHIFT (28U)
17734/*! DMWEBS - Bit status during a word error for the data mask (DM) bit
17735 */
17736#define DDRPHY_BISTFWR1_DMWEBS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR1_DMWEBS_SHIFT)) & DDRPHY_BISTFWR1_DMWEBS_MASK)
17737/*! @} */
17738
17739/*! @name BISTFWR2 - BIST Fail Word Register 2 */
17740/*! @{ */
17741#define DDRPHY_BISTFWR2_DQWEBS_MASK (0xFFFFFFFFU)
17742#define DDRPHY_BISTFWR2_DQWEBS_SHIFT (0U)
17743/*! DQWEBS - Bit status during a word error for each of the 8 data (DQ) bits
17744 */
17745#define DDRPHY_BISTFWR2_DQWEBS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTFWR2_DQWEBS_SHIFT)) & DDRPHY_BISTFWR2_DQWEBS_MASK)
17746/*! @} */
17747
17748/*! @name BISTBER5 - BIST Bit Error Register 5 */
17749/*! @{ */
17750#define DDRPHY_BISTBER5_CKEBER_MASK (0x3U)
17751#define DDRPHY_BISTBER5_CKEBER_SHIFT (0U)
17752/*! CKEBER - CKE Bit Error.
17753 */
17754#define DDRPHY_BISTBER5_CKEBER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER5_CKEBER_SHIFT)) & DDRPHY_BISTBER5_CKEBER_MASK)
17755#define DDRPHY_BISTBER5_CKEBER_RSVD_MASK (0xFFFCU)
17756#define DDRPHY_BISTBER5_CKEBER_RSVD_SHIFT (2U)
17757/*! CKEBER_RSVD - Reserved. Return zeros on reads.
17758 */
17759#define DDRPHY_BISTBER5_CKEBER_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER5_CKEBER_RSVD_SHIFT)) & DDRPHY_BISTBER5_CKEBER_RSVD_MASK)
17760#define DDRPHY_BISTBER5_ODTBER_MASK (0x30000U)
17761#define DDRPHY_BISTBER5_ODTBER_SHIFT (16U)
17762/*! ODTBER - ODT Bit Error.
17763 */
17764#define DDRPHY_BISTBER5_ODTBER(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER5_ODTBER_SHIFT)) & DDRPHY_BISTBER5_ODTBER_MASK)
17765#define DDRPHY_BISTBER5_ODTBER_RSVD_MASK (0xFFFC0000U)
17766#define DDRPHY_BISTBER5_ODTBER_RSVD_SHIFT (18U)
17767/*! ODTBER_RSVD - Reserved. Return zeros on reads.
17768 */
17769#define DDRPHY_BISTBER5_ODTBER_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_BISTBER5_ODTBER_RSVD_SHIFT)) & DDRPHY_BISTBER5_ODTBER_RSVD_MASK)
17770/*! @} */
17771
17772/*! @name RANKIDR - Rank ID Register */
17773/*! @{ */
17774#define DDRPHY_RANKIDR_RANKWID_MASK (0xFU)
17775#define DDRPHY_RANKIDR_RANKWID_SHIFT (0U)
17776/*! RANKWID - Rank Write ID
17777 */
17778#define DDRPHY_RANKIDR_RANKWID(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RANKIDR_RANKWID_SHIFT)) & DDRPHY_RANKIDR_RANKWID_MASK)
17779#define DDRPHY_RANKIDR_RESERVED_15_4_MASK (0xFFF0U)
17780#define DDRPHY_RANKIDR_RESERVED_15_4_SHIFT (4U)
17781/*! RESERVED_15_4 - Reserved. Return zeroes on reads.
17782 */
17783#define DDRPHY_RANKIDR_RESERVED_15_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RANKIDR_RESERVED_15_4_SHIFT)) & DDRPHY_RANKIDR_RESERVED_15_4_MASK)
17784#define DDRPHY_RANKIDR_RANKRID_MASK (0xF0000U)
17785#define DDRPHY_RANKIDR_RANKRID_SHIFT (16U)
17786/*! RANKRID - Rank Read ID
17787 */
17788#define DDRPHY_RANKIDR_RANKRID(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RANKIDR_RANKRID_SHIFT)) & DDRPHY_RANKIDR_RANKRID_MASK)
17789#define DDRPHY_RANKIDR_RESERVED_31_20_MASK (0xFFF00000U)
17790#define DDRPHY_RANKIDR_RESERVED_31_20_SHIFT (20U)
17791/*! RESERVED_31_20 - Reserved. Return zeroes on reads.
17792 */
17793#define DDRPHY_RANKIDR_RESERVED_31_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RANKIDR_RESERVED_31_20_SHIFT)) & DDRPHY_RANKIDR_RESERVED_31_20_MASK)
17794/*! @} */
17795
17796/*! @name RIOCR0 - Rank I/O Configuration Register 0 */
17797/*! @{ */
17798#define DDRPHY_RIOCR0_RESERVED_31_0_MASK (0xFFFFFFFFU)
17799#define DDRPHY_RIOCR0_RESERVED_31_0_SHIFT (0U)
17800/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
17801 */
17802#define DDRPHY_RIOCR0_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR0_RESERVED_31_0_SHIFT)) & DDRPHY_RIOCR0_RESERVED_31_0_MASK)
17803/*! @} */
17804
17805/*! @name RIOCR1 - Rank I/O Configuration Register 1 */
17806/*! @{ */
17807#define DDRPHY_RIOCR1_RESERVED_31_0_MASK (0xFFFFFFFFU)
17808#define DDRPHY_RIOCR1_RESERVED_31_0_SHIFT (0U)
17809/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
17810 */
17811#define DDRPHY_RIOCR1_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR1_RESERVED_31_0_SHIFT)) & DDRPHY_RIOCR1_RESERVED_31_0_MASK)
17812/*! @} */
17813
17814/*! @name RIOCR2 - Rank I/O Configuration Register 2 */
17815/*! @{ */
17816#define DDRPHY_RIOCR2_CSOEMODE_MASK (0x3U)
17817#define DDRPHY_RIOCR2_CSOEMODE_SHIFT (0U)
17818/*! CSOEMODE - SDRAM CS_n Output Enable (OE) Mode Selection.
17819 */
17820#define DDRPHY_RIOCR2_CSOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR2_CSOEMODE_SHIFT)) & DDRPHY_RIOCR2_CSOEMODE_MASK)
17821#define DDRPHY_RIOCR2_CSOEMODE_RSVD_MASK (0xFFFFFCU)
17822#define DDRPHY_RIOCR2_CSOEMODE_RSVD_SHIFT (2U)
17823/*! CSOEMODE_RSVD - Reserved. Return zeros on reads.
17824 */
17825#define DDRPHY_RIOCR2_CSOEMODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR2_CSOEMODE_RSVD_SHIFT)) & DDRPHY_RIOCR2_CSOEMODE_RSVD_MASK)
17826#define DDRPHY_RIOCR2_COEMODE_MASK (0x3000000U)
17827#define DDRPHY_RIOCR2_COEMODE_SHIFT (24U)
17828/*! COEMODE - SDRAM C Output Enable (OE) Mode Selection.
17829 */
17830#define DDRPHY_RIOCR2_COEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR2_COEMODE_SHIFT)) & DDRPHY_RIOCR2_COEMODE_MASK)
17831#define DDRPHY_RIOCR2_COEMODE_RSVD_MASK (0x3C000000U)
17832#define DDRPHY_RIOCR2_COEMODE_RSVD_SHIFT (26U)
17833/*! COEMODE_RSVD - Reserved. Return zeros on reads.
17834 */
17835#define DDRPHY_RIOCR2_COEMODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR2_COEMODE_RSVD_SHIFT)) & DDRPHY_RIOCR2_COEMODE_RSVD_MASK)
17836#define DDRPHY_RIOCR2_RESERVED_31_30_MASK (0xC0000000U)
17837#define DDRPHY_RIOCR2_RESERVED_31_30_SHIFT (30U)
17838/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
17839 */
17840#define DDRPHY_RIOCR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR2_RESERVED_31_30_SHIFT)) & DDRPHY_RIOCR2_RESERVED_31_30_MASK)
17841/*! @} */
17842
17843/*! @name RIOCR3 - Rank I/O Configuration Register 3 */
17844/*! @{ */
17845#define DDRPHY_RIOCR3_RESERVED_31_0_MASK (0xFFFFFFFFU)
17846#define DDRPHY_RIOCR3_RESERVED_31_0_SHIFT (0U)
17847/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
17848 */
17849#define DDRPHY_RIOCR3_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR3_RESERVED_31_0_SHIFT)) & DDRPHY_RIOCR3_RESERVED_31_0_MASK)
17850/*! @} */
17851
17852/*! @name RIOCR4 - Rank I/O Configuration Register 4 */
17853/*! @{ */
17854#define DDRPHY_RIOCR4_CKEOEMODE_MASK (0x3U)
17855#define DDRPHY_RIOCR4_CKEOEMODE_SHIFT (0U)
17856/*! CKEOEMODE - SDRAM CKE Output Enable (OE) Mode Selection.
17857 */
17858#define DDRPHY_RIOCR4_CKEOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR4_CKEOEMODE_SHIFT)) & DDRPHY_RIOCR4_CKEOEMODE_MASK)
17859#define DDRPHY_RIOCR4_CKEOEMODE_RSVD_MASK (0xFFFCU)
17860#define DDRPHY_RIOCR4_CKEOEMODE_RSVD_SHIFT (2U)
17861/*! CKEOEMODE_RSVD - Reserved. Return zeros on reads.
17862 */
17863#define DDRPHY_RIOCR4_CKEOEMODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR4_CKEOEMODE_RSVD_SHIFT)) & DDRPHY_RIOCR4_CKEOEMODE_RSVD_MASK)
17864#define DDRPHY_RIOCR4_RESERVED_31_16_MASK (0xFFFF0000U)
17865#define DDRPHY_RIOCR4_RESERVED_31_16_SHIFT (16U)
17866/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
17867 */
17868#define DDRPHY_RIOCR4_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR4_RESERVED_31_16_SHIFT)) & DDRPHY_RIOCR4_RESERVED_31_16_MASK)
17869/*! @} */
17870
17871/*! @name RIOCR5 - Rank I/O Configuration Register 5 */
17872/*! @{ */
17873#define DDRPHY_RIOCR5_ODTOEMODE_MASK (0x3U)
17874#define DDRPHY_RIOCR5_ODTOEMODE_SHIFT (0U)
17875/*! ODTOEMODE - SDRAM On-die Termination Output Enable (OE) Mode Selection.
17876 */
17877#define DDRPHY_RIOCR5_ODTOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR5_ODTOEMODE_SHIFT)) & DDRPHY_RIOCR5_ODTOEMODE_MASK)
17878#define DDRPHY_RIOCR5_ODTOEMODE_RSVD_MASK (0xFFFCU)
17879#define DDRPHY_RIOCR5_ODTOEMODE_RSVD_SHIFT (2U)
17880/*! ODTOEMODE_RSVD - Reserved. Return zeros on reads.
17881 */
17882#define DDRPHY_RIOCR5_ODTOEMODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR5_ODTOEMODE_RSVD_SHIFT)) & DDRPHY_RIOCR5_ODTOEMODE_RSVD_MASK)
17883#define DDRPHY_RIOCR5_RESERVED_31_16_MASK (0xFFFF0000U)
17884#define DDRPHY_RIOCR5_RESERVED_31_16_SHIFT (16U)
17885/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
17886 */
17887#define DDRPHY_RIOCR5_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_RIOCR5_RESERVED_31_16_SHIFT)) & DDRPHY_RIOCR5_RESERVED_31_16_MASK)
17888/*! @} */
17889
17890/*! @name ACIOCR0 - AC I/O Configuration Register 0 */
17891/*! @{ */
17892#define DDRPHY_ACIOCR0_ACRANKCLKSEL_MASK (0x1U)
17893#define DDRPHY_ACIOCR0_ACRANKCLKSEL_SHIFT (0U)
17894/*! ACRANKCLKSEL - Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.
17895 */
17896#define DDRPHY_ACIOCR0_ACRANKCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_ACRANKCLKSEL_SHIFT)) & DDRPHY_ACIOCR0_ACRANKCLKSEL_MASK)
17897#define DDRPHY_ACIOCR0_RESERVED_1_MASK (0x2U)
17898#define DDRPHY_ACIOCR0_RESERVED_1_SHIFT (1U)
17899/*! RESERVED_1 - Reserved. Return zeroes on reads.
17900 */
17901#define DDRPHY_ACIOCR0_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RESERVED_1_SHIFT)) & DDRPHY_ACIOCR0_RESERVED_1_MASK)
17902#define DDRPHY_ACIOCR0_ACODTMODE_MASK (0xCU)
17903#define DDRPHY_ACIOCR0_ACODTMODE_SHIFT (2U)
17904/*! ACODTMODE - AC On-die Termination Mode
17905 */
17906#define DDRPHY_ACIOCR0_ACODTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_ACODTMODE_SHIFT)) & DDRPHY_ACIOCR0_ACODTMODE_MASK)
17907#define DDRPHY_ACIOCR0_ACPDRMODE_MASK (0x30U)
17908#define DDRPHY_ACIOCR0_ACPDRMODE_SHIFT (4U)
17909/*! ACPDRMODE - AC Power Down Receiver Mode
17910 */
17911#define DDRPHY_ACIOCR0_ACPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_ACPDRMODE_SHIFT)) & DDRPHY_ACIOCR0_ACPDRMODE_MASK)
17912#define DDRPHY_ACIOCR0_CKDCC_MASK (0x3C0U)
17913#define DDRPHY_ACIOCR0_CKDCC_SHIFT (6U)
17914/*! CKDCC - CK Duty Cycle Correction
17915 */
17916#define DDRPHY_ACIOCR0_CKDCC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_CKDCC_SHIFT)) & DDRPHY_ACIOCR0_CKDCC_MASK)
17917#define DDRPHY_ACIOCR0_ACPNUMSEL_MASK (0xC00U)
17918#define DDRPHY_ACIOCR0_ACPNUMSEL_SHIFT (10U)
17919/*! ACPNUMSEL - Address/Command custom pin mapping configuration
17920 */
17921#define DDRPHY_ACIOCR0_ACPNUMSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_ACPNUMSEL_SHIFT)) & DDRPHY_ACIOCR0_ACPNUMSEL_MASK)
17922#define DDRPHY_ACIOCR0_RESERVED_15_12_MASK (0xF000U)
17923#define DDRPHY_ACIOCR0_RESERVED_15_12_SHIFT (12U)
17924/*! RESERVED_15_12 - Reserved. Return zeroes on reads.
17925 */
17926#define DDRPHY_ACIOCR0_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RESERVED_15_12_SHIFT)) & DDRPHY_ACIOCR0_RESERVED_15_12_MASK)
17927#define DDRPHY_ACIOCR0_ESR_MASK (0xFF0000U)
17928#define DDRPHY_ACIOCR0_ESR_SHIFT (16U)
17929/*! ESR - Decoupling Capacitance ESR Control in D5M I/O ring
17930 */
17931#define DDRPHY_ACIOCR0_ESR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_ESR_SHIFT)) & DDRPHY_ACIOCR0_ESR_MASK)
17932#define DDRPHY_ACIOCR0_RESERVED_25_24_MASK (0x3000000U)
17933#define DDRPHY_ACIOCR0_RESERVED_25_24_SHIFT (24U)
17934/*! RESERVED_25_24 - Reserved. Return zeroes on reads.
17935 */
17936#define DDRPHY_ACIOCR0_RESERVED_25_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RESERVED_25_24_SHIFT)) & DDRPHY_ACIOCR0_RESERVED_25_24_MASK)
17937#define DDRPHY_ACIOCR0_RSTODT_MASK (0x4000000U)
17938#define DDRPHY_ACIOCR0_RSTODT_SHIFT (26U)
17939/*! RSTODT - SDRAM Reset On-Die Termination
17940 */
17941#define DDRPHY_ACIOCR0_RSTODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RSTODT_SHIFT)) & DDRPHY_ACIOCR0_RSTODT_MASK)
17942#define DDRPHY_ACIOCR0_RESERVED_27_MASK (0x8000000U)
17943#define DDRPHY_ACIOCR0_RESERVED_27_SHIFT (27U)
17944/*! RESERVED_27 - Reserved. Return zeroes on reads.
17945 */
17946#define DDRPHY_ACIOCR0_RESERVED_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RESERVED_27_SHIFT)) & DDRPHY_ACIOCR0_RESERVED_27_MASK)
17947#define DDRPHY_ACIOCR0_RSTPDR_MASK (0x10000000U)
17948#define DDRPHY_ACIOCR0_RSTPDR_SHIFT (28U)
17949/*! RSTPDR - SDRAM Reset Power Down Receiver
17950 */
17951#define DDRPHY_ACIOCR0_RSTPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RSTPDR_SHIFT)) & DDRPHY_ACIOCR0_RSTPDR_MASK)
17952#define DDRPHY_ACIOCR0_RSTIOM_MASK (0x20000000U)
17953#define DDRPHY_ACIOCR0_RSTIOM_SHIFT (29U)
17954/*! RSTIOM - SDRAM Reset I/O Mode
17955 */
17956#define DDRPHY_ACIOCR0_RSTIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_RSTIOM_SHIFT)) & DDRPHY_ACIOCR0_RSTIOM_MASK)
17957#define DDRPHY_ACIOCR0_ACSR_MASK (0xC0000000U)
17958#define DDRPHY_ACIOCR0_ACSR_SHIFT (30U)
17959/*! ACSR - Address/Command Slew Rate (D3F I/O Only)
17960 */
17961#define DDRPHY_ACIOCR0_ACSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR0_ACSR_SHIFT)) & DDRPHY_ACIOCR0_ACSR_MASK)
17962/*! @} */
17963
17964/*! @name ACIOCR1 - AC I/O Configuration Register 1 */
17965/*! @{ */
17966#define DDRPHY_ACIOCR1_AOEMODE_MASK (0xFFFFFFFFU)
17967#define DDRPHY_ACIOCR1_AOEMODE_SHIFT (0U)
17968/*! AOEMODE - SDRAM Address Output Enable (OE) Mode Selection
17969 */
17970#define DDRPHY_ACIOCR1_AOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR1_AOEMODE_SHIFT)) & DDRPHY_ACIOCR1_AOEMODE_MASK)
17971/*! @} */
17972
17973/*! @name ACIOCR2 - AC I/O Configuration Register 2 */
17974/*! @{ */
17975#define DDRPHY_ACIOCR2_ACCLKGATE0_MASK (0xFFFFFFU)
17976#define DDRPHY_ACIOCR2_ACCLKGATE0_SHIFT (0U)
17977/*! ACCLKGATE0 - Clock gating for AC D slices [23:0]
17978 */
17979#define DDRPHY_ACIOCR2_ACCLKGATE0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_ACCLKGATE0_SHIFT)) & DDRPHY_ACIOCR2_ACCLKGATE0_MASK)
17980#define DDRPHY_ACIOCR2_CKCLKGATE0_MASK (0x3000000U)
17981#define DDRPHY_ACIOCR2_CKCLKGATE0_SHIFT (24U)
17982/*! CKCLKGATE0 - Clock gating for CK D slices [1:0]
17983 */
17984#define DDRPHY_ACIOCR2_CKCLKGATE0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_CKCLKGATE0_SHIFT)) & DDRPHY_ACIOCR2_CKCLKGATE0_MASK)
17985#define DDRPHY_ACIOCR2_CKNCLKGATE0_MASK (0xC000000U)
17986#define DDRPHY_ACIOCR2_CKNCLKGATE0_SHIFT (26U)
17987/*! CKNCLKGATE0 - Clock gating for CK# D slices [1:0]
17988 */
17989#define DDRPHY_ACIOCR2_CKNCLKGATE0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_CKNCLKGATE0_SHIFT)) & DDRPHY_ACIOCR2_CKNCLKGATE0_MASK)
17990#define DDRPHY_ACIOCR2_ACTECLKGATE0_MASK (0x10000000U)
17991#define DDRPHY_ACIOCR2_ACTECLKGATE0_SHIFT (28U)
17992/*! ACTECLKGATE0 - Clock gating for Termination Enable D slices [0]
17993 */
17994#define DDRPHY_ACIOCR2_ACTECLKGATE0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_ACTECLKGATE0_SHIFT)) & DDRPHY_ACIOCR2_ACTECLKGATE0_MASK)
17995#define DDRPHY_ACIOCR2_ACPDRCLKGATE0_MASK (0x20000000U)
17996#define DDRPHY_ACIOCR2_ACPDRCLKGATE0_SHIFT (29U)
17997/*! ACPDRCLKGATE0 - Clock gating for Power Down Receiver D slices [0]
17998 */
17999#define DDRPHY_ACIOCR2_ACPDRCLKGATE0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_ACPDRCLKGATE0_SHIFT)) & DDRPHY_ACIOCR2_ACPDRCLKGATE0_MASK)
18000#define DDRPHY_ACIOCR2_ACOECLKGATE0_MASK (0x40000000U)
18001#define DDRPHY_ACIOCR2_ACOECLKGATE0_SHIFT (30U)
18002/*! ACOECLKGATE0 - Clock gating for Output Enable D slices [0]
18003 */
18004#define DDRPHY_ACIOCR2_ACOECLKGATE0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_ACOECLKGATE0_SHIFT)) & DDRPHY_ACIOCR2_ACOECLKGATE0_MASK)
18005#define DDRPHY_ACIOCR2_CLKGENCLKGATE_MASK (0x80000000U)
18006#define DDRPHY_ACIOCR2_CLKGENCLKGATE_SHIFT (31U)
18007/*! CLKGENCLKGATE - Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice
18008 */
18009#define DDRPHY_ACIOCR2_CLKGENCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR2_CLKGENCLKGATE_SHIFT)) & DDRPHY_ACIOCR2_CLKGENCLKGATE_MASK)
18010/*! @} */
18011
18012/*! @name ACIOCR3 - AC I/O Configuration Register 3 */
18013/*! @{ */
18014#define DDRPHY_ACIOCR3_CKOEMODE_MASK (0xFU)
18015#define DDRPHY_ACIOCR3_CKOEMODE_SHIFT (0U)
18016/*! CKOEMODE - SDRAM CK Output Enable (OE) Mode Selection.
18017 */
18018#define DDRPHY_ACIOCR3_CKOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_CKOEMODE_SHIFT)) & DDRPHY_ACIOCR3_CKOEMODE_MASK)
18019#define DDRPHY_ACIOCR3_CKOEMODE_RSVD_MASK (0xF0U)
18020#define DDRPHY_ACIOCR3_CKOEMODE_RSVD_SHIFT (4U)
18021/*! CKOEMODE_RSVD - Reserved. Return zeros on reads.
18022 */
18023#define DDRPHY_ACIOCR3_CKOEMODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_CKOEMODE_RSVD_SHIFT)) & DDRPHY_ACIOCR3_CKOEMODE_RSVD_MASK)
18024#define DDRPHY_ACIOCR3_RESERVED_15_8_MASK (0xFF00U)
18025#define DDRPHY_ACIOCR3_RESERVED_15_8_SHIFT (8U)
18026/*! RESERVED_15_8 - Reserved. Return zeroes on reads.
18027 */
18028#define DDRPHY_ACIOCR3_RESERVED_15_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_RESERVED_15_8_SHIFT)) & DDRPHY_ACIOCR3_RESERVED_15_8_MASK)
18029#define DDRPHY_ACIOCR3_ACTOEMODE_MASK (0x30000U)
18030#define DDRPHY_ACIOCR3_ACTOEMODE_SHIFT (16U)
18031/*! ACTOEMODE - SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)
18032 */
18033#define DDRPHY_ACIOCR3_ACTOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_ACTOEMODE_SHIFT)) & DDRPHY_ACIOCR3_ACTOEMODE_MASK)
18034#define DDRPHY_ACIOCR3_A16OEMODE_MASK (0xC0000U)
18035#define DDRPHY_ACIOCR3_A16OEMODE_SHIFT (18U)
18036/*! A16OEMODE - SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection
18037 */
18038#define DDRPHY_ACIOCR3_A16OEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_A16OEMODE_SHIFT)) & DDRPHY_ACIOCR3_A16OEMODE_MASK)
18039#define DDRPHY_ACIOCR3_A17OEMODE_MASK (0x300000U)
18040#define DDRPHY_ACIOCR3_A17OEMODE_SHIFT (20U)
18041/*! A17OEMODE - SDRAM A[17] Output Enable (OE) Mode Selection
18042 */
18043#define DDRPHY_ACIOCR3_A17OEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_A17OEMODE_SHIFT)) & DDRPHY_ACIOCR3_A17OEMODE_MASK)
18044#define DDRPHY_ACIOCR3_BAOEMODE_MASK (0x3C00000U)
18045#define DDRPHY_ACIOCR3_BAOEMODE_SHIFT (22U)
18046/*! BAOEMODE - SDRAM Bank Address Output Enable (OE) Mode Selection
18047 */
18048#define DDRPHY_ACIOCR3_BAOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_BAOEMODE_SHIFT)) & DDRPHY_ACIOCR3_BAOEMODE_MASK)
18049#define DDRPHY_ACIOCR3_BGOEMODE_MASK (0x3C000000U)
18050#define DDRPHY_ACIOCR3_BGOEMODE_SHIFT (26U)
18051/*! BGOEMODE - SDRAM Bank Group Output Enable (OE) Mode Selection
18052 */
18053#define DDRPHY_ACIOCR3_BGOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_BGOEMODE_SHIFT)) & DDRPHY_ACIOCR3_BGOEMODE_MASK)
18054#define DDRPHY_ACIOCR3_PAROEMODE_MASK (0xC0000000U)
18055#define DDRPHY_ACIOCR3_PAROEMODE_SHIFT (30U)
18056/*! PAROEMODE - SDRAM Parity Output Enable (OE) Mode Selection
18057 */
18058#define DDRPHY_ACIOCR3_PAROEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR3_PAROEMODE_SHIFT)) & DDRPHY_ACIOCR3_PAROEMODE_MASK)
18059/*! @} */
18060
18061/*! @name ACIOCR4 - AC I/O Configuration Register 4 */
18062/*! @{ */
18063#define DDRPHY_ACIOCR4_ACCLKGATE1_MASK (0xFFFFFFU)
18064#define DDRPHY_ACIOCR4_ACCLKGATE1_SHIFT (0U)
18065/*! ACCLKGATE1 - Clock gating for AC D slices [47:24]
18066 */
18067#define DDRPHY_ACIOCR4_ACCLKGATE1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_ACCLKGATE1_SHIFT)) & DDRPHY_ACIOCR4_ACCLKGATE1_MASK)
18068#define DDRPHY_ACIOCR4_CKCLKGATE1_MASK (0x3000000U)
18069#define DDRPHY_ACIOCR4_CKCLKGATE1_SHIFT (24U)
18070/*! CKCLKGATE1 - Clock gating for CK D slices [3:2]
18071 */
18072#define DDRPHY_ACIOCR4_CKCLKGATE1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_CKCLKGATE1_SHIFT)) & DDRPHY_ACIOCR4_CKCLKGATE1_MASK)
18073#define DDRPHY_ACIOCR4_CKNCLKGATE1_MASK (0xC000000U)
18074#define DDRPHY_ACIOCR4_CKNCLKGATE1_SHIFT (26U)
18075/*! CKNCLKGATE1 - Clock gating for CK# D slices [3:2]
18076 */
18077#define DDRPHY_ACIOCR4_CKNCLKGATE1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_CKNCLKGATE1_SHIFT)) & DDRPHY_ACIOCR4_CKNCLKGATE1_MASK)
18078#define DDRPHY_ACIOCR4_ACTECLKGATE1_MASK (0x10000000U)
18079#define DDRPHY_ACIOCR4_ACTECLKGATE1_SHIFT (28U)
18080/*! ACTECLKGATE1 - Clock gating for Termination Enable D slices [1]
18081 */
18082#define DDRPHY_ACIOCR4_ACTECLKGATE1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_ACTECLKGATE1_SHIFT)) & DDRPHY_ACIOCR4_ACTECLKGATE1_MASK)
18083#define DDRPHY_ACIOCR4_ACPDRCLKGATE1_MASK (0x20000000U)
18084#define DDRPHY_ACIOCR4_ACPDRCLKGATE1_SHIFT (29U)
18085/*! ACPDRCLKGATE1 - Clock gating for Power Down Receiver D slices [1]
18086 */
18087#define DDRPHY_ACIOCR4_ACPDRCLKGATE1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_ACPDRCLKGATE1_SHIFT)) & DDRPHY_ACIOCR4_ACPDRCLKGATE1_MASK)
18088#define DDRPHY_ACIOCR4_ACOECLKGATE1_MASK (0x40000000U)
18089#define DDRPHY_ACIOCR4_ACOECLKGATE1_SHIFT (30U)
18090/*! ACOECLKGATE1 - Clock gating for Output Enable D slices [1]
18091 */
18092#define DDRPHY_ACIOCR4_ACOECLKGATE1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_ACOECLKGATE1_SHIFT)) & DDRPHY_ACIOCR4_ACOECLKGATE1_MASK)
18093#define DDRPHY_ACIOCR4_LBCLKGATE_MASK (0x80000000U)
18094#define DDRPHY_ACIOCR4_LBCLKGATE_SHIFT (31U)
18095/*! LBCLKGATE - Clock gating for AC LB slices and loopback read valid slices
18096 */
18097#define DDRPHY_ACIOCR4_LBCLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR4_LBCLKGATE_SHIFT)) & DDRPHY_ACIOCR4_LBCLKGATE_MASK)
18098/*! @} */
18099
18100/*! @name ACIOCR5 - AC I/O Configuration Register 5 */
18101/*! @{ */
18102#define DDRPHY_ACIOCR5_ACRXM_MASK (0x7FFU)
18103#define DDRPHY_ACIOCR5_ACRXM_SHIFT (0U)
18104/*! ACRXM - AC IO Receiver Mode
18105 */
18106#define DDRPHY_ACIOCR5_ACRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR5_ACRXM_SHIFT)) & DDRPHY_ACIOCR5_ACRXM_MASK)
18107#define DDRPHY_ACIOCR5_ACTXM_MASK (0x3FF800U)
18108#define DDRPHY_ACIOCR5_ACTXM_SHIFT (11U)
18109/*! ACTXM - AC IO Transmitter Mode
18110 */
18111#define DDRPHY_ACIOCR5_ACTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR5_ACTXM_SHIFT)) & DDRPHY_ACIOCR5_ACTXM_MASK)
18112#define DDRPHY_ACIOCR5_ACXIOM_MASK (0x1C00000U)
18113#define DDRPHY_ACIOCR5_ACXIOM_SHIFT (22U)
18114/*! ACXIOM - AC IO Mode
18115 */
18116#define DDRPHY_ACIOCR5_ACXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR5_ACXIOM_SHIFT)) & DDRPHY_ACIOCR5_ACXIOM_MASK)
18117#define DDRPHY_ACIOCR5_ACVREFIOM_MASK (0xE000000U)
18118#define DDRPHY_ACIOCR5_ACVREFIOM_SHIFT (25U)
18119/*! ACVREFIOM - IOM bits for PVREF and PVREFE cells in AC IO ring
18120 */
18121#define DDRPHY_ACIOCR5_ACVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR5_ACVREFIOM_SHIFT)) & DDRPHY_ACIOCR5_ACVREFIOM_MASK)
18122#define DDRPHY_ACIOCR5_RESERVED_31_28_MASK (0xF0000000U)
18123#define DDRPHY_ACIOCR5_RESERVED_31_28_SHIFT (28U)
18124/*! RESERVED_31_28 - Reserved. Return zeroes on reads.
18125 */
18126#define DDRPHY_ACIOCR5_RESERVED_31_28(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACIOCR5_RESERVED_31_28_SHIFT)) & DDRPHY_ACIOCR5_RESERVED_31_28_MASK)
18127/*! @} */
18128
18129/*! @name IOVCR0 - IO VREF Control Register 0 */
18130/*! @{ */
18131#define DDRPHY_IOVCR0_ACVREFISEL_MASK (0x7FU)
18132#define DDRPHY_IOVCR0_ACVREFISEL_SHIFT (0U)
18133/*! ACVREFISEL - REFSEL Control for internal AC IOs
18134 */
18135#define DDRPHY_IOVCR0_ACVREFISEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACVREFISEL_SHIFT)) & DDRPHY_IOVCR0_ACVREFISEL_MASK)
18136#define DDRPHY_IOVCR0_ACVREFISELRANGE_MASK (0x80U)
18137#define DDRPHY_IOVCR0_ACVREFISELRANGE_SHIFT (7U)
18138/*! ACVREFISELRANGE - Internal VREF generator REFSEL ragne select
18139 */
18140#define DDRPHY_IOVCR0_ACVREFISELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACVREFISELRANGE_SHIFT)) & DDRPHY_IOVCR0_ACVREFISELRANGE_MASK)
18141#define DDRPHY_IOVCR0_ACREFSSEL_MASK (0x7F00U)
18142#define DDRPHY_IOVCR0_ACREFSSEL_SHIFT (8U)
18143/*! ACREFSSEL - Address/command lane Single-End VREF Select
18144 */
18145#define DDRPHY_IOVCR0_ACREFSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFSSEL_SHIFT)) & DDRPHY_IOVCR0_ACREFSSEL_MASK)
18146#define DDRPHY_IOVCR0_ACREFSSELRANGE_MASK (0x8000U)
18147#define DDRPHY_IOVCR0_ACREFSSELRANGE_SHIFT (15U)
18148/*! ACREFSSELRANGE - Single ended VREF generator REFSEL range select
18149 */
18150#define DDRPHY_IOVCR0_ACREFSSELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFSSELRANGE_SHIFT)) & DDRPHY_IOVCR0_ACREFSSELRANGE_MASK)
18151#define DDRPHY_IOVCR0_ACREFESEL_MASK (0x7F0000U)
18152#define DDRPHY_IOVCR0_ACREFESEL_SHIFT (16U)
18153/*! ACREFESEL - Address/command lane External VREF Select
18154 */
18155#define DDRPHY_IOVCR0_ACREFESEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFESEL_SHIFT)) & DDRPHY_IOVCR0_ACREFESEL_MASK)
18156#define DDRPHY_IOVCR0_ACREFESELRANGE_MASK (0x800000U)
18157#define DDRPHY_IOVCR0_ACREFESELRANGE_SHIFT (23U)
18158/*! ACREFESELRANGE - External VREF generato REFSEL range select
18159 */
18160#define DDRPHY_IOVCR0_ACREFESELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFESELRANGE_SHIFT)) & DDRPHY_IOVCR0_ACREFESELRANGE_MASK)
18161#define DDRPHY_IOVCR0_ACREFIEN_MASK (0x1000000U)
18162#define DDRPHY_IOVCR0_ACREFIEN_SHIFT (24U)
18163/*! ACREFIEN - Address/command lane Internal VREF Enable
18164 */
18165#define DDRPHY_IOVCR0_ACREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFIEN_SHIFT)) & DDRPHY_IOVCR0_ACREFIEN_MASK)
18166#define DDRPHY_IOVCR0_ACREFSEN_MASK (0x2000000U)
18167#define DDRPHY_IOVCR0_ACREFSEN_SHIFT (25U)
18168/*! ACREFSEN - Address/command lane Single-End VREF Enable
18169 */
18170#define DDRPHY_IOVCR0_ACREFSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFSEN_SHIFT)) & DDRPHY_IOVCR0_ACREFSEN_MASK)
18171#define DDRPHY_IOVCR0_ACREFEEN_MASK (0xC000000U)
18172#define DDRPHY_IOVCR0_ACREFEEN_SHIFT (26U)
18173/*! ACREFEEN - Address/command lane Internal VREF Enable
18174 */
18175#define DDRPHY_IOVCR0_ACREFEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFEEN_SHIFT)) & DDRPHY_IOVCR0_ACREFEEN_MASK)
18176#define DDRPHY_IOVCR0_ACREFPEN_MASK (0x10000000U)
18177#define DDRPHY_IOVCR0_ACREFPEN_SHIFT (28U)
18178/*! ACREFPEN - Address/command lane VREF Pad Enable
18179 */
18180#define DDRPHY_IOVCR0_ACREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_ACREFPEN_SHIFT)) & DDRPHY_IOVCR0_ACREFPEN_MASK)
18181#define DDRPHY_IOVCR0_RESERVED_31_29_MASK (0xE0000000U)
18182#define DDRPHY_IOVCR0_RESERVED_31_29_SHIFT (29U)
18183/*! RESERVED_31_29 - Reserved. Return zeroes on reads.
18184 */
18185#define DDRPHY_IOVCR0_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR0_RESERVED_31_29_SHIFT)) & DDRPHY_IOVCR0_RESERVED_31_29_MASK)
18186/*! @} */
18187
18188/*! @name IOVCR1 - IO VREF Control Register 1 */
18189/*! @{ */
18190#define DDRPHY_IOVCR1_RESERVED_31_0_MASK (0xFFFFFFFFU)
18191#define DDRPHY_IOVCR1_RESERVED_31_0_SHIFT (0U)
18192/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
18193 */
18194#define DDRPHY_IOVCR1_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_IOVCR1_RESERVED_31_0_SHIFT)) & DDRPHY_IOVCR1_RESERVED_31_0_MASK)
18195/*! @} */
18196
18197/*! @name VTCR0 - VREF Training Control Register 0 */
18198/*! @{ */
18199#define DDRPHY_VTCR0_DVINIT_MASK (0x3FU)
18200#define DDRPHY_VTCR0_DVINIT_SHIFT (0U)
18201/*! DVINIT - Initial DRAM DQ VREF value used during DRAM VREF training
18202 */
18203#define DDRPHY_VTCR0_DVINIT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_DVINIT_SHIFT)) & DDRPHY_VTCR0_DVINIT_MASK)
18204#define DDRPHY_VTCR0_DVMIN_MASK (0xFC0U)
18205#define DDRPHY_VTCR0_DVMIN_SHIFT (6U)
18206/*! DVMIN - Minimum VREF limit value used during DRAM VREF training
18207 */
18208#define DDRPHY_VTCR0_DVMIN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_DVMIN_SHIFT)) & DDRPHY_VTCR0_DVMIN_MASK)
18209#define DDRPHY_VTCR0_DVMAX_MASK (0x3F000U)
18210#define DDRPHY_VTCR0_DVMAX_SHIFT (12U)
18211/*! DVMAX - Maximum VREF limit value used during DRAM VREF training
18212 */
18213#define DDRPHY_VTCR0_DVMAX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_DVMAX_SHIFT)) & DDRPHY_VTCR0_DVMAX_MASK)
18214#define DDRPHY_VTCR0_DVSS_MASK (0x3C0000U)
18215#define DDRPHY_VTCR0_DVSS_SHIFT (18U)
18216/*! DVSS - DRAM DQ VREF step size used during DRAM VREF training
18217 */
18218#define DDRPHY_VTCR0_DVSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_DVSS_SHIFT)) & DDRPHY_VTCR0_DVSS_MASK)
18219#define DDRPHY_VTCR0_VWCR_MASK (0x3C00000U)
18220#define DDRPHY_VTCR0_VWCR_SHIFT (22U)
18221/*! VWCR - VREF Word Count
18222 */
18223#define DDRPHY_VTCR0_VWCR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_VWCR_SHIFT)) & DDRPHY_VTCR0_VWCR_MASK)
18224#define DDRPHY_VTCR0_RESERVED_26_MASK (0x4000000U)
18225#define DDRPHY_VTCR0_RESERVED_26_SHIFT (26U)
18226/*! RESERVED_26 - Reserved. Returns zeroes on reads.
18227 */
18228#define DDRPHY_VTCR0_RESERVED_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_RESERVED_26_SHIFT)) & DDRPHY_VTCR0_RESERVED_26_MASK)
18229#define DDRPHY_VTCR0_PDAEN_MASK (0x8000000U)
18230#define DDRPHY_VTCR0_PDAEN_SHIFT (27U)
18231/*! PDAEN - Per Device Addressability Enable
18232 */
18233#define DDRPHY_VTCR0_PDAEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_PDAEN_SHIFT)) & DDRPHY_VTCR0_PDAEN_MASK)
18234#define DDRPHY_VTCR0_DVEN_MASK (0x10000000U)
18235#define DDRPHY_VTCR0_DVEN_SHIFT (28U)
18236/*! DVEN - DRM DQ VREF training Enable
18237 */
18238#define DDRPHY_VTCR0_DVEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_DVEN_SHIFT)) & DDRPHY_VTCR0_DVEN_MASK)
18239#define DDRPHY_VTCR0_tVREF_MASK (0xE0000000U)
18240#define DDRPHY_VTCR0_tVREF_SHIFT (29U)
18241/*! tVREF - Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training
18242 */
18243#define DDRPHY_VTCR0_tVREF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR0_tVREF_SHIFT)) & DDRPHY_VTCR0_tVREF_MASK)
18244/*! @} */
18245
18246/*! @name VTCR1 - VREF Training Control Register 1 */
18247/*! @{ */
18248#define DDRPHY_VTCR1_HVIO_MASK (0x1U)
18249#define DDRPHY_VTCR1_HVIO_SHIFT (0U)
18250/*! HVIO - Host IO Type Control
18251 */
18252#define DDRPHY_VTCR1_HVIO(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_HVIO_SHIFT)) & DDRPHY_VTCR1_HVIO_MASK)
18253#define DDRPHY_VTCR1_HVEN_MASK (0x2U)
18254#define DDRPHY_VTCR1_HVEN_SHIFT (1U)
18255/*! HVEN - HOST (IO) internal VREF training Enable
18256 */
18257#define DDRPHY_VTCR1_HVEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_HVEN_SHIFT)) & DDRPHY_VTCR1_HVEN_MASK)
18258#define DDRPHY_VTCR1_ENUM_MASK (0x4U)
18259#define DDRPHY_VTCR1_ENUM_SHIFT (2U)
18260/*! ENUM - Number of LCDL Eye points for which VREF training is repeated
18261 */
18262#define DDRPHY_VTCR1_ENUM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_ENUM_SHIFT)) & DDRPHY_VTCR1_ENUM_MASK)
18263#define DDRPHY_VTCR1_EOFF_MASK (0x18U)
18264#define DDRPHY_VTCR1_EOFF_SHIFT (3U)
18265/*! EOFF - Eye LCDL Offset value for VREF training
18266 */
18267#define DDRPHY_VTCR1_EOFF(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_EOFF_SHIFT)) & DDRPHY_VTCR1_EOFF_MASK)
18268#define DDRPHY_VTCR1_tVREFIO_MASK (0xE0U)
18269#define DDRPHY_VTCR1_tVREFIO_SHIFT (5U)
18270/*! tVREFIO - Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training
18271 */
18272#define DDRPHY_VTCR1_tVREFIO(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_tVREFIO_SHIFT)) & DDRPHY_VTCR1_tVREFIO_MASK)
18273#define DDRPHY_VTCR1_SHREN_MASK (0x100U)
18274#define DDRPHY_VTCR1_SHREN_SHIFT (8U)
18275/*! SHREN - Static Host Vref Rank Enable
18276 */
18277#define DDRPHY_VTCR1_SHREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_SHREN_SHIFT)) & DDRPHY_VTCR1_SHREN_MASK)
18278#define DDRPHY_VTCR1_SHRNK_MASK (0x600U)
18279#define DDRPHY_VTCR1_SHRNK_SHIFT (9U)
18280/*! SHRNK - Static Host Vref Rank Value
18281 */
18282#define DDRPHY_VTCR1_SHRNK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_SHRNK_SHIFT)) & DDRPHY_VTCR1_SHRNK_MASK)
18283#define DDRPHY_VTCR1_RESERVED_11_MASK (0x800U)
18284#define DDRPHY_VTCR1_RESERVED_11_SHIFT (11U)
18285/*! RESERVED_11 - Reserved. Returns zeroes on reads.
18286 */
18287#define DDRPHY_VTCR1_RESERVED_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_11_SHIFT)) & DDRPHY_VTCR1_RESERVED_11_MASK)
18288#define DDRPHY_VTCR1_HVMIN_MASK (0x7F000U)
18289#define DDRPHY_VTCR1_HVMIN_SHIFT (12U)
18290/*! HVMIN - Minimum VREF limit value used during DRAM VREF training.
18291 */
18292#define DDRPHY_VTCR1_HVMIN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_HVMIN_SHIFT)) & DDRPHY_VTCR1_HVMIN_MASK)
18293#define DDRPHY_VTCR1_RESERVED_19_MASK (0x80000U)
18294#define DDRPHY_VTCR1_RESERVED_19_SHIFT (19U)
18295/*! RESERVED_19 - Reserved. Returns zeroes on reads.
18296 */
18297#define DDRPHY_VTCR1_RESERVED_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_19_SHIFT)) & DDRPHY_VTCR1_RESERVED_19_MASK)
18298#define DDRPHY_VTCR1_HVMAX_MASK (0x7F00000U)
18299#define DDRPHY_VTCR1_HVMAX_SHIFT (20U)
18300/*! HVMAX - Maximum VREF limit value used during DRAM VREF training.
18301 */
18302#define DDRPHY_VTCR1_HVMAX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_HVMAX_SHIFT)) & DDRPHY_VTCR1_HVMAX_MASK)
18303#define DDRPHY_VTCR1_RESERVED_27_MASK (0x8000000U)
18304#define DDRPHY_VTCR1_RESERVED_27_SHIFT (27U)
18305/*! RESERVED_27 - Reserved. Returns zeroes on reads.
18306 */
18307#define DDRPHY_VTCR1_RESERVED_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_27_SHIFT)) & DDRPHY_VTCR1_RESERVED_27_MASK)
18308#define DDRPHY_VTCR1_HVSS_MASK (0xF0000000U)
18309#define DDRPHY_VTCR1_HVSS_SHIFT (28U)
18310/*! HVSS - Host VREF step size used during VREF training. The register value of N indicates step size of (N+1)
18311 */
18312#define DDRPHY_VTCR1_HVSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_HVSS_SHIFT)) & DDRPHY_VTCR1_HVSS_MASK)
18313/*! @} */
18314
18315/*! @name ACBDLR0 - AC Bit Delay Line Register 0 */
18316/*! @{ */
18317#define DDRPHY_ACBDLR0_CK0BD_MASK (0x3FU)
18318#define DDRPHY_ACBDLR0_CK0BD_SHIFT (0U)
18319/*! CK0BD - CK0 Bit Delay
18320 */
18321#define DDRPHY_ACBDLR0_CK0BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_CK0BD_SHIFT)) & DDRPHY_ACBDLR0_CK0BD_MASK)
18322#define DDRPHY_ACBDLR0_RESERVED_7_6_MASK (0xC0U)
18323#define DDRPHY_ACBDLR0_RESERVED_7_6_SHIFT (6U)
18324/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18325 */
18326#define DDRPHY_ACBDLR0_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR0_RESERVED_7_6_MASK)
18327#define DDRPHY_ACBDLR0_CK1BD_MASK (0x3F00U)
18328#define DDRPHY_ACBDLR0_CK1BD_SHIFT (8U)
18329/*! CK1BD - CK1 Bit Delay
18330 */
18331#define DDRPHY_ACBDLR0_CK1BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_CK1BD_SHIFT)) & DDRPHY_ACBDLR0_CK1BD_MASK)
18332#define DDRPHY_ACBDLR0_RESERVED_15_14_MASK (0xC000U)
18333#define DDRPHY_ACBDLR0_RESERVED_15_14_SHIFT (14U)
18334/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18335 */
18336#define DDRPHY_ACBDLR0_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR0_RESERVED_15_14_MASK)
18337#define DDRPHY_ACBDLR0_CK2BD_MASK (0x3F0000U)
18338#define DDRPHY_ACBDLR0_CK2BD_SHIFT (16U)
18339/*! CK2BD - CK2 Bit Delay
18340 */
18341#define DDRPHY_ACBDLR0_CK2BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_CK2BD_SHIFT)) & DDRPHY_ACBDLR0_CK2BD_MASK)
18342#define DDRPHY_ACBDLR0_RESERVED_23_22_MASK (0xC00000U)
18343#define DDRPHY_ACBDLR0_RESERVED_23_22_SHIFT (22U)
18344/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18345 */
18346#define DDRPHY_ACBDLR0_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR0_RESERVED_23_22_MASK)
18347#define DDRPHY_ACBDLR0_CK3BD_MASK (0x3F000000U)
18348#define DDRPHY_ACBDLR0_CK3BD_SHIFT (24U)
18349/*! CK3BD - CK3 Bit Delay
18350 */
18351#define DDRPHY_ACBDLR0_CK3BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_CK3BD_SHIFT)) & DDRPHY_ACBDLR0_CK3BD_MASK)
18352#define DDRPHY_ACBDLR0_RESERVED_31_30_MASK (0xC0000000U)
18353#define DDRPHY_ACBDLR0_RESERVED_31_30_SHIFT (30U)
18354/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18355 */
18356#define DDRPHY_ACBDLR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR0_RESERVED_31_30_MASK)
18357/*! @} */
18358
18359/*! @name ACBDLR1 - AC Bit Delay Line Register 1 */
18360/*! @{ */
18361#define DDRPHY_ACBDLR1_ACTBD_MASK (0x3FU)
18362#define DDRPHY_ACBDLR1_ACTBD_SHIFT (0U)
18363/*! ACTBD - Delay select for the BDL on ACTN.
18364 */
18365#define DDRPHY_ACBDLR1_ACTBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_ACTBD_SHIFT)) & DDRPHY_ACBDLR1_ACTBD_MASK)
18366#define DDRPHY_ACBDLR1_RESERVED_7_6_MASK (0xC0U)
18367#define DDRPHY_ACBDLR1_RESERVED_7_6_SHIFT (6U)
18368/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18369 */
18370#define DDRPHY_ACBDLR1_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR1_RESERVED_7_6_MASK)
18371#define DDRPHY_ACBDLR1_A17BD_MASK (0x3F00U)
18372#define DDRPHY_ACBDLR1_A17BD_SHIFT (8U)
18373/*! A17BD - Delay select for the BDL on Address A[17]. When not in DDR4 modemode this pin is connected to CAS.
18374 */
18375#define DDRPHY_ACBDLR1_A17BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_A17BD_SHIFT)) & DDRPHY_ACBDLR1_A17BD_MASK)
18376#define DDRPHY_ACBDLR1_RESERVED_15_14_MASK (0xC000U)
18377#define DDRPHY_ACBDLR1_RESERVED_15_14_SHIFT (14U)
18378/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18379 */
18380#define DDRPHY_ACBDLR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR1_RESERVED_15_14_MASK)
18381#define DDRPHY_ACBDLR1_A16BD_MASK (0x3F0000U)
18382#define DDRPHY_ACBDLR1_A16BD_SHIFT (16U)
18383/*! A16BD - Delay select for the BDL on Address A[16]. In DDR3 mode this pin is connected to WE.
18384 */
18385#define DDRPHY_ACBDLR1_A16BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_A16BD_SHIFT)) & DDRPHY_ACBDLR1_A16BD_MASK)
18386#define DDRPHY_ACBDLR1_RESERVED_23_22_MASK (0xC00000U)
18387#define DDRPHY_ACBDLR1_RESERVED_23_22_SHIFT (22U)
18388/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18389 */
18390#define DDRPHY_ACBDLR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR1_RESERVED_23_22_MASK)
18391#define DDRPHY_ACBDLR1_PARBD_MASK (0x3F000000U)
18392#define DDRPHY_ACBDLR1_PARBD_SHIFT (24U)
18393/*! PARBD - Delay select for the BDL on Parity.
18394 */
18395#define DDRPHY_ACBDLR1_PARBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_PARBD_SHIFT)) & DDRPHY_ACBDLR1_PARBD_MASK)
18396#define DDRPHY_ACBDLR1_RESERVED_31_30_MASK (0xC0000000U)
18397#define DDRPHY_ACBDLR1_RESERVED_31_30_SHIFT (30U)
18398/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18399 */
18400#define DDRPHY_ACBDLR1_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR1_RESERVED_31_30_MASK)
18401/*! @} */
18402
18403/*! @name ACBDLR2 - AC Bit Delay Line Register 2 */
18404/*! @{ */
18405#define DDRPHY_ACBDLR2_BA0BD_MASK (0x3FU)
18406#define DDRPHY_ACBDLR2_BA0BD_SHIFT (0U)
18407/*! BA0BD - Delay select for the BDL on BA[0].
18408 */
18409#define DDRPHY_ACBDLR2_BA0BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_BA0BD_SHIFT)) & DDRPHY_ACBDLR2_BA0BD_MASK)
18410#define DDRPHY_ACBDLR2_RESERVED_7_6_MASK (0xC0U)
18411#define DDRPHY_ACBDLR2_RESERVED_7_6_SHIFT (6U)
18412/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18413 */
18414#define DDRPHY_ACBDLR2_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR2_RESERVED_7_6_MASK)
18415#define DDRPHY_ACBDLR2_BA1BD_MASK (0x3F00U)
18416#define DDRPHY_ACBDLR2_BA1BD_SHIFT (8U)
18417/*! BA1BD - Delay select for the BDL on BA[1].
18418 */
18419#define DDRPHY_ACBDLR2_BA1BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_BA1BD_SHIFT)) & DDRPHY_ACBDLR2_BA1BD_MASK)
18420#define DDRPHY_ACBDLR2_RESERVED_15_14_MASK (0xC000U)
18421#define DDRPHY_ACBDLR2_RESERVED_15_14_SHIFT (14U)
18422/*! RESERVED_15_14 - Reser.ved Return zeroes on reads.
18423 */
18424#define DDRPHY_ACBDLR2_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR2_RESERVED_15_14_MASK)
18425#define DDRPHY_ACBDLR2_BG0BD_MASK (0x3F0000U)
18426#define DDRPHY_ACBDLR2_BG0BD_SHIFT (16U)
18427/*! BG0BD - Delay select for the BDL on BG[0].
18428 */
18429#define DDRPHY_ACBDLR2_BG0BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_BG0BD_SHIFT)) & DDRPHY_ACBDLR2_BG0BD_MASK)
18430#define DDRPHY_ACBDLR2_RESERVED_23_22_MASK (0xC00000U)
18431#define DDRPHY_ACBDLR2_RESERVED_23_22_SHIFT (22U)
18432/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18433 */
18434#define DDRPHY_ACBDLR2_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR2_RESERVED_23_22_MASK)
18435#define DDRPHY_ACBDLR2_BG1BD_MASK (0x3F000000U)
18436#define DDRPHY_ACBDLR2_BG1BD_SHIFT (24U)
18437/*! BG1BD - Delay select for the BDL on BG[1].
18438 */
18439#define DDRPHY_ACBDLR2_BG1BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_BG1BD_SHIFT)) & DDRPHY_ACBDLR2_BG1BD_MASK)
18440#define DDRPHY_ACBDLR2_RESERVED_31_30_MASK (0xC0000000U)
18441#define DDRPHY_ACBDLR2_RESERVED_31_30_SHIFT (30U)
18442/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18443 */
18444#define DDRPHY_ACBDLR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR2_RESERVED_31_30_MASK)
18445/*! @} */
18446
18447/*! @name ACBDLR3 - AC Bit Delay Line Register 3 */
18448/*! @{ */
18449#define DDRPHY_ACBDLR3_CS0BD_MASK (0x3FU)
18450#define DDRPHY_ACBDLR3_CS0BD_SHIFT (0U)
18451/*! CS0BD - Delay select for the BDL on CS[0].
18452 */
18453#define DDRPHY_ACBDLR3_CS0BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_CS0BD_SHIFT)) & DDRPHY_ACBDLR3_CS0BD_MASK)
18454#define DDRPHY_ACBDLR3_RESERVED_7_6_MASK (0xC0U)
18455#define DDRPHY_ACBDLR3_RESERVED_7_6_SHIFT (6U)
18456/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18457 */
18458#define DDRPHY_ACBDLR3_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR3_RESERVED_7_6_MASK)
18459#define DDRPHY_ACBDLR3_CS1BD_MASK (0x3F00U)
18460#define DDRPHY_ACBDLR3_CS1BD_SHIFT (8U)
18461/*! CS1BD - Delay select for the BDL on CS[1].
18462 */
18463#define DDRPHY_ACBDLR3_CS1BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_CS1BD_SHIFT)) & DDRPHY_ACBDLR3_CS1BD_MASK)
18464#define DDRPHY_ACBDLR3_RESERVED_15_14_MASK (0xC000U)
18465#define DDRPHY_ACBDLR3_RESERVED_15_14_SHIFT (14U)
18466/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18467 */
18468#define DDRPHY_ACBDLR3_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR3_RESERVED_15_14_MASK)
18469#define DDRPHY_ACBDLR3_CS2BD_MASK (0x3F0000U)
18470#define DDRPHY_ACBDLR3_CS2BD_SHIFT (16U)
18471/*! CS2BD - Delay select for the BDL on CS[2].
18472 */
18473#define DDRPHY_ACBDLR3_CS2BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_CS2BD_SHIFT)) & DDRPHY_ACBDLR3_CS2BD_MASK)
18474#define DDRPHY_ACBDLR3_RESERVED_23_22_MASK (0xC00000U)
18475#define DDRPHY_ACBDLR3_RESERVED_23_22_SHIFT (22U)
18476/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18477 */
18478#define DDRPHY_ACBDLR3_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR3_RESERVED_23_22_MASK)
18479#define DDRPHY_ACBDLR3_CS3BD_MASK (0x3F000000U)
18480#define DDRPHY_ACBDLR3_CS3BD_SHIFT (24U)
18481/*! CS3BD - Delay select for the BDL on CS[3].
18482 */
18483#define DDRPHY_ACBDLR3_CS3BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_CS3BD_SHIFT)) & DDRPHY_ACBDLR3_CS3BD_MASK)
18484#define DDRPHY_ACBDLR3_RESERVED_31_30_MASK (0xC0000000U)
18485#define DDRPHY_ACBDLR3_RESERVED_31_30_SHIFT (30U)
18486/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18487 */
18488#define DDRPHY_ACBDLR3_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR3_RESERVED_31_30_MASK)
18489/*! @} */
18490
18491/*! @name ACBDLR4 - AC Bit Delay Line Register 4 */
18492/*! @{ */
18493#define DDRPHY_ACBDLR4_ODT0BD_MASK (0x3FU)
18494#define DDRPHY_ACBDLR4_ODT0BD_SHIFT (0U)
18495/*! ODT0BD - Delay select for the BDL on ODT[0].
18496 */
18497#define DDRPHY_ACBDLR4_ODT0BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_ODT0BD_SHIFT)) & DDRPHY_ACBDLR4_ODT0BD_MASK)
18498#define DDRPHY_ACBDLR4_RESERVED_7_6_MASK (0xC0U)
18499#define DDRPHY_ACBDLR4_RESERVED_7_6_SHIFT (6U)
18500/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18501 */
18502#define DDRPHY_ACBDLR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR4_RESERVED_7_6_MASK)
18503#define DDRPHY_ACBDLR4_ODT1BD_MASK (0x3F00U)
18504#define DDRPHY_ACBDLR4_ODT1BD_SHIFT (8U)
18505/*! ODT1BD - Delay select for the BDL on ODT[1].
18506 */
18507#define DDRPHY_ACBDLR4_ODT1BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_ODT1BD_SHIFT)) & DDRPHY_ACBDLR4_ODT1BD_MASK)
18508#define DDRPHY_ACBDLR4_RESERVED_15_14_MASK (0xC000U)
18509#define DDRPHY_ACBDLR4_RESERVED_15_14_SHIFT (14U)
18510/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18511 */
18512#define DDRPHY_ACBDLR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR4_RESERVED_15_14_MASK)
18513#define DDRPHY_ACBDLR4_ODT2BD_MASK (0x3F0000U)
18514#define DDRPHY_ACBDLR4_ODT2BD_SHIFT (16U)
18515/*! ODT2BD - Delay select for the BDL on ODT[2].
18516 */
18517#define DDRPHY_ACBDLR4_ODT2BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_ODT2BD_SHIFT)) & DDRPHY_ACBDLR4_ODT2BD_MASK)
18518#define DDRPHY_ACBDLR4_RESERVED_23_22_MASK (0xC00000U)
18519#define DDRPHY_ACBDLR4_RESERVED_23_22_SHIFT (22U)
18520/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18521 */
18522#define DDRPHY_ACBDLR4_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR4_RESERVED_23_22_MASK)
18523#define DDRPHY_ACBDLR4_ODT3BD_MASK (0x3F000000U)
18524#define DDRPHY_ACBDLR4_ODT3BD_SHIFT (24U)
18525/*! ODT3BD - Delay select for the BDL on ODT[3].
18526 */
18527#define DDRPHY_ACBDLR4_ODT3BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_ODT3BD_SHIFT)) & DDRPHY_ACBDLR4_ODT3BD_MASK)
18528#define DDRPHY_ACBDLR4_RESERVED_31_30_MASK (0xC0000000U)
18529#define DDRPHY_ACBDLR4_RESERVED_31_30_SHIFT (30U)
18530/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18531 */
18532#define DDRPHY_ACBDLR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR4_RESERVED_31_30_MASK)
18533/*! @} */
18534
18535/*! @name ACBDLR5 - AC Bit Delay Line Register 5 */
18536/*! @{ */
18537#define DDRPHY_ACBDLR5_CKE0BD_MASK (0x3FU)
18538#define DDRPHY_ACBDLR5_CKE0BD_SHIFT (0U)
18539/*! CKE0BD - Delay select for the BDL on CKE[0].
18540 */
18541#define DDRPHY_ACBDLR5_CKE0BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_CKE0BD_SHIFT)) & DDRPHY_ACBDLR5_CKE0BD_MASK)
18542#define DDRPHY_ACBDLR5_RESERVED_7_6_MASK (0xC0U)
18543#define DDRPHY_ACBDLR5_RESERVED_7_6_SHIFT (6U)
18544/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18545 */
18546#define DDRPHY_ACBDLR5_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR5_RESERVED_7_6_MASK)
18547#define DDRPHY_ACBDLR5_CKE1BD_MASK (0x3F00U)
18548#define DDRPHY_ACBDLR5_CKE1BD_SHIFT (8U)
18549/*! CKE1BD - Delay select for the BDL on CKE[1].
18550 */
18551#define DDRPHY_ACBDLR5_CKE1BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_CKE1BD_SHIFT)) & DDRPHY_ACBDLR5_CKE1BD_MASK)
18552#define DDRPHY_ACBDLR5_RESERVED_15_14_MASK (0xC000U)
18553#define DDRPHY_ACBDLR5_RESERVED_15_14_SHIFT (14U)
18554/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18555 */
18556#define DDRPHY_ACBDLR5_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR5_RESERVED_15_14_MASK)
18557#define DDRPHY_ACBDLR5_CKE2BD_MASK (0x3F0000U)
18558#define DDRPHY_ACBDLR5_CKE2BD_SHIFT (16U)
18559/*! CKE2BD - Delay select for the BDL on CKE[2].
18560 */
18561#define DDRPHY_ACBDLR5_CKE2BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_CKE2BD_SHIFT)) & DDRPHY_ACBDLR5_CKE2BD_MASK)
18562#define DDRPHY_ACBDLR5_RESERVED_23_22_MASK (0xC00000U)
18563#define DDRPHY_ACBDLR5_RESERVED_23_22_SHIFT (22U)
18564/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18565 */
18566#define DDRPHY_ACBDLR5_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR5_RESERVED_23_22_MASK)
18567#define DDRPHY_ACBDLR5_CKE3BD_MASK (0x3F000000U)
18568#define DDRPHY_ACBDLR5_CKE3BD_SHIFT (24U)
18569/*! CKE3BD - Delay select for the BDL on CKE[3].
18570 */
18571#define DDRPHY_ACBDLR5_CKE3BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_CKE3BD_SHIFT)) & DDRPHY_ACBDLR5_CKE3BD_MASK)
18572#define DDRPHY_ACBDLR5_RESERVED_31_30_MASK (0xC0000000U)
18573#define DDRPHY_ACBDLR5_RESERVED_31_30_SHIFT (30U)
18574/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18575 */
18576#define DDRPHY_ACBDLR5_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR5_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR5_RESERVED_31_30_MASK)
18577/*! @} */
18578
18579/*! @name ACBDLR6 - AC Bit Delay Line Register 6 */
18580/*! @{ */
18581#define DDRPHY_ACBDLR6_A00BD_MASK (0x3FU)
18582#define DDRPHY_ACBDLR6_A00BD_SHIFT (0U)
18583/*! A00BD - Delay select for the BDL on Address A[0].
18584 */
18585#define DDRPHY_ACBDLR6_A00BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_A00BD_SHIFT)) & DDRPHY_ACBDLR6_A00BD_MASK)
18586#define DDRPHY_ACBDLR6_RESERVED_7_6_MASK (0xC0U)
18587#define DDRPHY_ACBDLR6_RESERVED_7_6_SHIFT (6U)
18588/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18589 */
18590#define DDRPHY_ACBDLR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR6_RESERVED_7_6_MASK)
18591#define DDRPHY_ACBDLR6_A01BD_MASK (0x3F00U)
18592#define DDRPHY_ACBDLR6_A01BD_SHIFT (8U)
18593/*! A01BD - Delay select for the BDL on Address A[1].
18594 */
18595#define DDRPHY_ACBDLR6_A01BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_A01BD_SHIFT)) & DDRPHY_ACBDLR6_A01BD_MASK)
18596#define DDRPHY_ACBDLR6_RESERVED_15_14_MASK (0xC000U)
18597#define DDRPHY_ACBDLR6_RESERVED_15_14_SHIFT (14U)
18598/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18599 */
18600#define DDRPHY_ACBDLR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR6_RESERVED_15_14_MASK)
18601#define DDRPHY_ACBDLR6_A02BD_MASK (0x3F0000U)
18602#define DDRPHY_ACBDLR6_A02BD_SHIFT (16U)
18603/*! A02BD - Delay select for the BDL on Address A[2].
18604 */
18605#define DDRPHY_ACBDLR6_A02BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_A02BD_SHIFT)) & DDRPHY_ACBDLR6_A02BD_MASK)
18606#define DDRPHY_ACBDLR6_RESERVED_23_22_MASK (0xC00000U)
18607#define DDRPHY_ACBDLR6_RESERVED_23_22_SHIFT (22U)
18608/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18609 */
18610#define DDRPHY_ACBDLR6_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR6_RESERVED_23_22_MASK)
18611#define DDRPHY_ACBDLR6_A03BD_MASK (0x3F000000U)
18612#define DDRPHY_ACBDLR6_A03BD_SHIFT (24U)
18613/*! A03BD - Delay select for the BDL on Address A[3].
18614 */
18615#define DDRPHY_ACBDLR6_A03BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_A03BD_SHIFT)) & DDRPHY_ACBDLR6_A03BD_MASK)
18616#define DDRPHY_ACBDLR6_RESERVED_31_30_MASK (0xC0000000U)
18617#define DDRPHY_ACBDLR6_RESERVED_31_30_SHIFT (30U)
18618/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18619 */
18620#define DDRPHY_ACBDLR6_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR6_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR6_RESERVED_31_30_MASK)
18621/*! @} */
18622
18623/*! @name ACBDLR7 - AC Bit Delay Line Register 7 */
18624/*! @{ */
18625#define DDRPHY_ACBDLR7_A04BD_MASK (0x3FU)
18626#define DDRPHY_ACBDLR7_A04BD_SHIFT (0U)
18627/*! A04BD - Delay select for the BDL on Address A[4].
18628 */
18629#define DDRPHY_ACBDLR7_A04BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_A04BD_SHIFT)) & DDRPHY_ACBDLR7_A04BD_MASK)
18630#define DDRPHY_ACBDLR7_RESERVED_7_6_MASK (0xC0U)
18631#define DDRPHY_ACBDLR7_RESERVED_7_6_SHIFT (6U)
18632/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18633 */
18634#define DDRPHY_ACBDLR7_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR7_RESERVED_7_6_MASK)
18635#define DDRPHY_ACBDLR7_A05BD_MASK (0x3F00U)
18636#define DDRPHY_ACBDLR7_A05BD_SHIFT (8U)
18637/*! A05BD - Delay select for the BDL on Address A[5].
18638 */
18639#define DDRPHY_ACBDLR7_A05BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_A05BD_SHIFT)) & DDRPHY_ACBDLR7_A05BD_MASK)
18640#define DDRPHY_ACBDLR7_RESERVED_15_14_MASK (0xC000U)
18641#define DDRPHY_ACBDLR7_RESERVED_15_14_SHIFT (14U)
18642/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18643 */
18644#define DDRPHY_ACBDLR7_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR7_RESERVED_15_14_MASK)
18645#define DDRPHY_ACBDLR7_A06BD_MASK (0x3F0000U)
18646#define DDRPHY_ACBDLR7_A06BD_SHIFT (16U)
18647/*! A06BD - Delay select for the BDL on Address A[6].
18648 */
18649#define DDRPHY_ACBDLR7_A06BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_A06BD_SHIFT)) & DDRPHY_ACBDLR7_A06BD_MASK)
18650#define DDRPHY_ACBDLR7_RESERVED_23_22_MASK (0xC00000U)
18651#define DDRPHY_ACBDLR7_RESERVED_23_22_SHIFT (22U)
18652/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18653 */
18654#define DDRPHY_ACBDLR7_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR7_RESERVED_23_22_MASK)
18655#define DDRPHY_ACBDLR7_A07BD_MASK (0x3F000000U)
18656#define DDRPHY_ACBDLR7_A07BD_SHIFT (24U)
18657/*! A07BD - Delay select for the BDL on Address A[7].
18658 */
18659#define DDRPHY_ACBDLR7_A07BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_A07BD_SHIFT)) & DDRPHY_ACBDLR7_A07BD_MASK)
18660#define DDRPHY_ACBDLR7_RESERVED_31_30_MASK (0xC0000000U)
18661#define DDRPHY_ACBDLR7_RESERVED_31_30_SHIFT (30U)
18662/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18663 */
18664#define DDRPHY_ACBDLR7_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR7_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR7_RESERVED_31_30_MASK)
18665/*! @} */
18666
18667/*! @name ACBDLR8 - AC Bit Delay Line Register 8 */
18668/*! @{ */
18669#define DDRPHY_ACBDLR8_A08BD_MASK (0x3FU)
18670#define DDRPHY_ACBDLR8_A08BD_SHIFT (0U)
18671/*! A08BD - Delay select for the BDL on Address A[8].
18672 */
18673#define DDRPHY_ACBDLR8_A08BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_A08BD_SHIFT)) & DDRPHY_ACBDLR8_A08BD_MASK)
18674#define DDRPHY_ACBDLR8_RESERVED_7_6_MASK (0xC0U)
18675#define DDRPHY_ACBDLR8_RESERVED_7_6_SHIFT (6U)
18676/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18677 */
18678#define DDRPHY_ACBDLR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR8_RESERVED_7_6_MASK)
18679#define DDRPHY_ACBDLR8_A09BD_MASK (0x3F00U)
18680#define DDRPHY_ACBDLR8_A09BD_SHIFT (8U)
18681/*! A09BD - Delay select for the BDL on Address A[9].
18682 */
18683#define DDRPHY_ACBDLR8_A09BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_A09BD_SHIFT)) & DDRPHY_ACBDLR8_A09BD_MASK)
18684#define DDRPHY_ACBDLR8_RESERVED_15_14_MASK (0xC000U)
18685#define DDRPHY_ACBDLR8_RESERVED_15_14_SHIFT (14U)
18686/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18687 */
18688#define DDRPHY_ACBDLR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR8_RESERVED_15_14_MASK)
18689#define DDRPHY_ACBDLR8_A10BD_MASK (0x3F0000U)
18690#define DDRPHY_ACBDLR8_A10BD_SHIFT (16U)
18691/*! A10BD - Delay select for the BDL on Address A[10].
18692 */
18693#define DDRPHY_ACBDLR8_A10BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_A10BD_SHIFT)) & DDRPHY_ACBDLR8_A10BD_MASK)
18694#define DDRPHY_ACBDLR8_RESERVED_23_22_MASK (0xC00000U)
18695#define DDRPHY_ACBDLR8_RESERVED_23_22_SHIFT (22U)
18696/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18697 */
18698#define DDRPHY_ACBDLR8_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR8_RESERVED_23_22_MASK)
18699#define DDRPHY_ACBDLR8_A11BD_MASK (0x3F000000U)
18700#define DDRPHY_ACBDLR8_A11BD_SHIFT (24U)
18701/*! A11BD - Delay select for the BDL on Address A[11].
18702 */
18703#define DDRPHY_ACBDLR8_A11BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_A11BD_SHIFT)) & DDRPHY_ACBDLR8_A11BD_MASK)
18704#define DDRPHY_ACBDLR8_RESERVED_31_30_MASK (0xC0000000U)
18705#define DDRPHY_ACBDLR8_RESERVED_31_30_SHIFT (30U)
18706/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18707 */
18708#define DDRPHY_ACBDLR8_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR8_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR8_RESERVED_31_30_MASK)
18709/*! @} */
18710
18711/*! @name ACBDLR9 - AC Bit Delay Line Register 9 */
18712/*! @{ */
18713#define DDRPHY_ACBDLR9_A12BD_MASK (0x3FU)
18714#define DDRPHY_ACBDLR9_A12BD_SHIFT (0U)
18715/*! A12BD - Delay select for the BDL on Address A[12].
18716 */
18717#define DDRPHY_ACBDLR9_A12BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_A12BD_SHIFT)) & DDRPHY_ACBDLR9_A12BD_MASK)
18718#define DDRPHY_ACBDLR9_RESERVED_7_6_MASK (0xC0U)
18719#define DDRPHY_ACBDLR9_RESERVED_7_6_SHIFT (6U)
18720/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18721 */
18722#define DDRPHY_ACBDLR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR9_RESERVED_7_6_MASK)
18723#define DDRPHY_ACBDLR9_A13BD_MASK (0x3F00U)
18724#define DDRPHY_ACBDLR9_A13BD_SHIFT (8U)
18725/*! A13BD - Delay select for the BDL on Address A[13].
18726 */
18727#define DDRPHY_ACBDLR9_A13BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_A13BD_SHIFT)) & DDRPHY_ACBDLR9_A13BD_MASK)
18728#define DDRPHY_ACBDLR9_RESERVED_15_14_MASK (0xC000U)
18729#define DDRPHY_ACBDLR9_RESERVED_15_14_SHIFT (14U)
18730/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18731 */
18732#define DDRPHY_ACBDLR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR9_RESERVED_15_14_MASK)
18733#define DDRPHY_ACBDLR9_A14BD_MASK (0x3F0000U)
18734#define DDRPHY_ACBDLR9_A14BD_SHIFT (16U)
18735/*! A14BD - Delay select for the BDL on Address A[14].
18736 */
18737#define DDRPHY_ACBDLR9_A14BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_A14BD_SHIFT)) & DDRPHY_ACBDLR9_A14BD_MASK)
18738#define DDRPHY_ACBDLR9_RESERVED_23_22_MASK (0xC00000U)
18739#define DDRPHY_ACBDLR9_RESERVED_23_22_SHIFT (22U)
18740/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18741 */
18742#define DDRPHY_ACBDLR9_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR9_RESERVED_23_22_MASK)
18743#define DDRPHY_ACBDLR9_A15BD_MASK (0x3F000000U)
18744#define DDRPHY_ACBDLR9_A15BD_SHIFT (24U)
18745/*! A15BD - Delay select for the BDL on Address A[15].
18746 */
18747#define DDRPHY_ACBDLR9_A15BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_A15BD_SHIFT)) & DDRPHY_ACBDLR9_A15BD_MASK)
18748#define DDRPHY_ACBDLR9_RESERVED_31_30_MASK (0xC0000000U)
18749#define DDRPHY_ACBDLR9_RESERVED_31_30_SHIFT (30U)
18750/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18751 */
18752#define DDRPHY_ACBDLR9_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR9_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR9_RESERVED_31_30_MASK)
18753/*! @} */
18754
18755/*! @name ACBDLR10 - AC Bit Delay Line Register 10 */
18756/*! @{ */
18757#define DDRPHY_ACBDLR10_RESERVED_7_0_MASK (0xFFU)
18758#define DDRPHY_ACBDLR10_RESERVED_7_0_SHIFT (0U)
18759/*! RESERVED_7_0 - Reserved. Return zeroes on reads.
18760 */
18761#define DDRPHY_ACBDLR10_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_RESERVED_7_0_SHIFT)) & DDRPHY_ACBDLR10_RESERVED_7_0_MASK)
18762#define DDRPHY_ACBDLR10_CID0BD_MASK (0x3F00U)
18763#define DDRPHY_ACBDLR10_CID0BD_SHIFT (8U)
18764/*! CID0BD - Delay select for the BDL on Chip ID CID[0]
18765 */
18766#define DDRPHY_ACBDLR10_CID0BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_CID0BD_SHIFT)) & DDRPHY_ACBDLR10_CID0BD_MASK)
18767#define DDRPHY_ACBDLR10_RESERVED_15_14_MASK (0xC000U)
18768#define DDRPHY_ACBDLR10_RESERVED_15_14_SHIFT (14U)
18769/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18770 */
18771#define DDRPHY_ACBDLR10_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR10_RESERVED_15_14_MASK)
18772#define DDRPHY_ACBDLR10_CID1BD_MASK (0x3F0000U)
18773#define DDRPHY_ACBDLR10_CID1BD_SHIFT (16U)
18774/*! CID1BD - Delay select for the BDL on Chip ID CID[1]
18775 */
18776#define DDRPHY_ACBDLR10_CID1BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_CID1BD_SHIFT)) & DDRPHY_ACBDLR10_CID1BD_MASK)
18777#define DDRPHY_ACBDLR10_RESERVED_23_22_MASK (0xC00000U)
18778#define DDRPHY_ACBDLR10_RESERVED_23_22_SHIFT (22U)
18779/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18780 */
18781#define DDRPHY_ACBDLR10_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR10_RESERVED_23_22_MASK)
18782#define DDRPHY_ACBDLR10_CID2BD_MASK (0x3F000000U)
18783#define DDRPHY_ACBDLR10_CID2BD_SHIFT (24U)
18784/*! CID2BD - Delay select for the BDL on Chip ID CID[2]
18785 */
18786#define DDRPHY_ACBDLR10_CID2BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_CID2BD_SHIFT)) & DDRPHY_ACBDLR10_CID2BD_MASK)
18787#define DDRPHY_ACBDLR10_RESERVED_31_30_MASK (0xC0000000U)
18788#define DDRPHY_ACBDLR10_RESERVED_31_30_SHIFT (30U)
18789/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18790 */
18791#define DDRPHY_ACBDLR10_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR10_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR10_RESERVED_31_30_MASK)
18792/*! @} */
18793
18794/*! @name ACBDLR11 - AC Bit Delay Line Register 11 */
18795/*! @{ */
18796#define DDRPHY_ACBDLR11_CS4BD_MASK (0x3FU)
18797#define DDRPHY_ACBDLR11_CS4BD_SHIFT (0U)
18798/*! CS4BD - Delay select for the BDL on CS[4]
18799 */
18800#define DDRPHY_ACBDLR11_CS4BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_CS4BD_SHIFT)) & DDRPHY_ACBDLR11_CS4BD_MASK)
18801#define DDRPHY_ACBDLR11_RESERVED_7_6_MASK (0xC0U)
18802#define DDRPHY_ACBDLR11_RESERVED_7_6_SHIFT (6U)
18803/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18804 */
18805#define DDRPHY_ACBDLR11_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR11_RESERVED_7_6_MASK)
18806#define DDRPHY_ACBDLR11_CS5BD_MASK (0x3F00U)
18807#define DDRPHY_ACBDLR11_CS5BD_SHIFT (8U)
18808/*! CS5BD - Delay select for the BDL on CS[5]
18809 */
18810#define DDRPHY_ACBDLR11_CS5BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_CS5BD_SHIFT)) & DDRPHY_ACBDLR11_CS5BD_MASK)
18811#define DDRPHY_ACBDLR11_RESERVED_15_14_MASK (0xC000U)
18812#define DDRPHY_ACBDLR11_RESERVED_15_14_SHIFT (14U)
18813/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18814 */
18815#define DDRPHY_ACBDLR11_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR11_RESERVED_15_14_MASK)
18816#define DDRPHY_ACBDLR11_CS6BD_MASK (0x3F0000U)
18817#define DDRPHY_ACBDLR11_CS6BD_SHIFT (16U)
18818/*! CS6BD - Delay select for the BDL on CS[6]
18819 */
18820#define DDRPHY_ACBDLR11_CS6BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_CS6BD_SHIFT)) & DDRPHY_ACBDLR11_CS6BD_MASK)
18821#define DDRPHY_ACBDLR11_RESERVED_23_22_MASK (0xC00000U)
18822#define DDRPHY_ACBDLR11_RESERVED_23_22_SHIFT (22U)
18823/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18824 */
18825#define DDRPHY_ACBDLR11_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR11_RESERVED_23_22_MASK)
18826#define DDRPHY_ACBDLR11_CS7BD_MASK (0x3F000000U)
18827#define DDRPHY_ACBDLR11_CS7BD_SHIFT (24U)
18828/*! CS7BD - Delay select for the BDL on CS[7]
18829 */
18830#define DDRPHY_ACBDLR11_CS7BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_CS7BD_SHIFT)) & DDRPHY_ACBDLR11_CS7BD_MASK)
18831#define DDRPHY_ACBDLR11_RESERVED_31_30_MASK (0xC0000000U)
18832#define DDRPHY_ACBDLR11_RESERVED_31_30_SHIFT (30U)
18833/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18834 */
18835#define DDRPHY_ACBDLR11_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR11_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR11_RESERVED_31_30_MASK)
18836/*! @} */
18837
18838/*! @name ACBDLR12 - AC Bit Delay Line Register 12 */
18839/*! @{ */
18840#define DDRPHY_ACBDLR12_CS8BD_MASK (0x3FU)
18841#define DDRPHY_ACBDLR12_CS8BD_SHIFT (0U)
18842/*! CS8BD - Delay select for the BDL on CS[8]
18843 */
18844#define DDRPHY_ACBDLR12_CS8BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_CS8BD_SHIFT)) & DDRPHY_ACBDLR12_CS8BD_MASK)
18845#define DDRPHY_ACBDLR12_RESERVED_7_6_MASK (0xC0U)
18846#define DDRPHY_ACBDLR12_RESERVED_7_6_SHIFT (6U)
18847/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18848 */
18849#define DDRPHY_ACBDLR12_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR12_RESERVED_7_6_MASK)
18850#define DDRPHY_ACBDLR12_CS9BD_MASK (0x3F00U)
18851#define DDRPHY_ACBDLR12_CS9BD_SHIFT (8U)
18852/*! CS9BD - Delay select for the BDL on CS[9]
18853 */
18854#define DDRPHY_ACBDLR12_CS9BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_CS9BD_SHIFT)) & DDRPHY_ACBDLR12_CS9BD_MASK)
18855#define DDRPHY_ACBDLR12_RESERVED_15_14_MASK (0xC000U)
18856#define DDRPHY_ACBDLR12_RESERVED_15_14_SHIFT (14U)
18857/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18858 */
18859#define DDRPHY_ACBDLR12_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR12_RESERVED_15_14_MASK)
18860#define DDRPHY_ACBDLR12_CS10BD_MASK (0x3F0000U)
18861#define DDRPHY_ACBDLR12_CS10BD_SHIFT (16U)
18862/*! CS10BD - Delay select for the BDL on CS[10]
18863 */
18864#define DDRPHY_ACBDLR12_CS10BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_CS10BD_SHIFT)) & DDRPHY_ACBDLR12_CS10BD_MASK)
18865#define DDRPHY_ACBDLR12_RESERVED_23_22_MASK (0xC00000U)
18866#define DDRPHY_ACBDLR12_RESERVED_23_22_SHIFT (22U)
18867/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18868 */
18869#define DDRPHY_ACBDLR12_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR12_RESERVED_23_22_MASK)
18870#define DDRPHY_ACBDLR12_CS11BD_MASK (0x3F000000U)
18871#define DDRPHY_ACBDLR12_CS11BD_SHIFT (24U)
18872/*! CS11BD - Delay select for the BDL on CS[11]
18873 */
18874#define DDRPHY_ACBDLR12_CS11BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_CS11BD_SHIFT)) & DDRPHY_ACBDLR12_CS11BD_MASK)
18875#define DDRPHY_ACBDLR12_RESERVED_31_30_MASK (0xC0000000U)
18876#define DDRPHY_ACBDLR12_RESERVED_31_30_SHIFT (30U)
18877/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18878 */
18879#define DDRPHY_ACBDLR12_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR12_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR12_RESERVED_31_30_MASK)
18880/*! @} */
18881
18882/*! @name ACBDLR13 - AC Bit Delay Line Register 13 */
18883/*! @{ */
18884#define DDRPHY_ACBDLR13_ODT4BD_MASK (0x3FU)
18885#define DDRPHY_ACBDLR13_ODT4BD_SHIFT (0U)
18886/*! ODT4BD - Delay select for the BDL on ODT[4]
18887 */
18888#define DDRPHY_ACBDLR13_ODT4BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_ODT4BD_SHIFT)) & DDRPHY_ACBDLR13_ODT4BD_MASK)
18889#define DDRPHY_ACBDLR13_RESERVED_7_6_MASK (0xC0U)
18890#define DDRPHY_ACBDLR13_RESERVED_7_6_SHIFT (6U)
18891/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18892 */
18893#define DDRPHY_ACBDLR13_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR13_RESERVED_7_6_MASK)
18894#define DDRPHY_ACBDLR13_ODT5BD_MASK (0x3F00U)
18895#define DDRPHY_ACBDLR13_ODT5BD_SHIFT (8U)
18896/*! ODT5BD - Delay select for the BDL on ODT[5]
18897 */
18898#define DDRPHY_ACBDLR13_ODT5BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_ODT5BD_SHIFT)) & DDRPHY_ACBDLR13_ODT5BD_MASK)
18899#define DDRPHY_ACBDLR13_RESERVED_15_14_MASK (0xC000U)
18900#define DDRPHY_ACBDLR13_RESERVED_15_14_SHIFT (14U)
18901/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18902 */
18903#define DDRPHY_ACBDLR13_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR13_RESERVED_15_14_MASK)
18904#define DDRPHY_ACBDLR13_ODT6BD_MASK (0x3F0000U)
18905#define DDRPHY_ACBDLR13_ODT6BD_SHIFT (16U)
18906/*! ODT6BD - Delay select for the BDL on ODT[6]
18907 */
18908#define DDRPHY_ACBDLR13_ODT6BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_ODT6BD_SHIFT)) & DDRPHY_ACBDLR13_ODT6BD_MASK)
18909#define DDRPHY_ACBDLR13_RESERVED_23_22_MASK (0xC00000U)
18910#define DDRPHY_ACBDLR13_RESERVED_23_22_SHIFT (22U)
18911/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18912 */
18913#define DDRPHY_ACBDLR13_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR13_RESERVED_23_22_MASK)
18914#define DDRPHY_ACBDLR13_ODT7BD_MASK (0x3F000000U)
18915#define DDRPHY_ACBDLR13_ODT7BD_SHIFT (24U)
18916/*! ODT7BD - Delay select for the BDL on ODT[7]
18917 */
18918#define DDRPHY_ACBDLR13_ODT7BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_ODT7BD_SHIFT)) & DDRPHY_ACBDLR13_ODT7BD_MASK)
18919#define DDRPHY_ACBDLR13_RESERVED_31_30_MASK (0xC0000000U)
18920#define DDRPHY_ACBDLR13_RESERVED_31_30_SHIFT (30U)
18921/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18922 */
18923#define DDRPHY_ACBDLR13_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR13_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR13_RESERVED_31_30_MASK)
18924/*! @} */
18925
18926/*! @name ACBDLR14 - AC Bit Delay Line Register 14 */
18927/*! @{ */
18928#define DDRPHY_ACBDLR14_CKE4BD_MASK (0x3FU)
18929#define DDRPHY_ACBDLR14_CKE4BD_SHIFT (0U)
18930/*! CKE4BD - Delay select for the BDL on CKE[4]
18931 */
18932#define DDRPHY_ACBDLR14_CKE4BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_CKE4BD_SHIFT)) & DDRPHY_ACBDLR14_CKE4BD_MASK)
18933#define DDRPHY_ACBDLR14_RESERVED_7_6_MASK (0xC0U)
18934#define DDRPHY_ACBDLR14_RESERVED_7_6_SHIFT (6U)
18935/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18936 */
18937#define DDRPHY_ACBDLR14_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR14_RESERVED_7_6_MASK)
18938#define DDRPHY_ACBDLR14_CKE5BD_MASK (0x3F00U)
18939#define DDRPHY_ACBDLR14_CKE5BD_SHIFT (8U)
18940/*! CKE5BD - Delay select for the BDL on CKE[5]
18941 */
18942#define DDRPHY_ACBDLR14_CKE5BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_CKE5BD_SHIFT)) & DDRPHY_ACBDLR14_CKE5BD_MASK)
18943#define DDRPHY_ACBDLR14_RESERVED_15_14_MASK (0xC000U)
18944#define DDRPHY_ACBDLR14_RESERVED_15_14_SHIFT (14U)
18945/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18946 */
18947#define DDRPHY_ACBDLR14_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR14_RESERVED_15_14_MASK)
18948#define DDRPHY_ACBDLR14_CKE6BD_MASK (0x3F0000U)
18949#define DDRPHY_ACBDLR14_CKE6BD_SHIFT (16U)
18950/*! CKE6BD - Delay select for the BDL on CKE[6]
18951 */
18952#define DDRPHY_ACBDLR14_CKE6BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_CKE6BD_SHIFT)) & DDRPHY_ACBDLR14_CKE6BD_MASK)
18953#define DDRPHY_ACBDLR14_RESERVED_23_22_MASK (0xC00000U)
18954#define DDRPHY_ACBDLR14_RESERVED_23_22_SHIFT (22U)
18955/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
18956 */
18957#define DDRPHY_ACBDLR14_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR14_RESERVED_23_22_MASK)
18958#define DDRPHY_ACBDLR14_CKE7BD_MASK (0x3F000000U)
18959#define DDRPHY_ACBDLR14_CKE7BD_SHIFT (24U)
18960/*! CKE7BD - Delay select for the BDL on CKE[7]
18961 */
18962#define DDRPHY_ACBDLR14_CKE7BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_CKE7BD_SHIFT)) & DDRPHY_ACBDLR14_CKE7BD_MASK)
18963#define DDRPHY_ACBDLR14_RESERVED_31_30_MASK (0xC0000000U)
18964#define DDRPHY_ACBDLR14_RESERVED_31_30_SHIFT (30U)
18965/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
18966 */
18967#define DDRPHY_ACBDLR14_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR14_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR14_RESERVED_31_30_MASK)
18968/*! @} */
18969
18970/*! @name ACBDLR15 - AC Bit Delay Line Register 15 */
18971/*! @{ */
18972#define DDRPHY_ACBDLR15_PDRBD_MASK (0x3FU)
18973#define DDRPHY_ACBDLR15_PDRBD_SHIFT (0U)
18974/*! PDRBD - Delay select for the BDL on PDR
18975 */
18976#define DDRPHY_ACBDLR15_PDRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR15_PDRBD_SHIFT)) & DDRPHY_ACBDLR15_PDRBD_MASK)
18977#define DDRPHY_ACBDLR15_RESERVED_7_6_MASK (0xC0U)
18978#define DDRPHY_ACBDLR15_RESERVED_7_6_SHIFT (6U)
18979/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
18980 */
18981#define DDRPHY_ACBDLR15_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR15_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR15_RESERVED_7_6_MASK)
18982#define DDRPHY_ACBDLR15_TEBD_MASK (0x3F00U)
18983#define DDRPHY_ACBDLR15_TEBD_SHIFT (8U)
18984/*! TEBD - Delay select for the BDL on TE
18985 */
18986#define DDRPHY_ACBDLR15_TEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR15_TEBD_SHIFT)) & DDRPHY_ACBDLR15_TEBD_MASK)
18987#define DDRPHY_ACBDLR15_RESERVED_15_14_MASK (0xC000U)
18988#define DDRPHY_ACBDLR15_RESERVED_15_14_SHIFT (14U)
18989/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
18990 */
18991#define DDRPHY_ACBDLR15_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR15_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR15_RESERVED_15_14_MASK)
18992#define DDRPHY_ACBDLR15_OEBD_MASK (0x3F0000U)
18993#define DDRPHY_ACBDLR15_OEBD_SHIFT (16U)
18994/*! OEBD - Delay select for the BDL on OE
18995 */
18996#define DDRPHY_ACBDLR15_OEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR15_OEBD_SHIFT)) & DDRPHY_ACBDLR15_OEBD_MASK)
18997#define DDRPHY_ACBDLR15_RESERVED_31_22_MASK (0xFFC00000U)
18998#define DDRPHY_ACBDLR15_RESERVED_31_22_SHIFT (22U)
18999/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
19000 */
19001#define DDRPHY_ACBDLR15_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR15_RESERVED_31_22_SHIFT)) & DDRPHY_ACBDLR15_RESERVED_31_22_MASK)
19002/*! @} */
19003
19004/*! @name ACBDLR16 - AC Bit Delay Line Register 16 */
19005/*! @{ */
19006#define DDRPHY_ACBDLR16_CKN0BD_MASK (0x3FU)
19007#define DDRPHY_ACBDLR16_CKN0BD_SHIFT (0U)
19008/*! CKN0BD - Delay select for the BDL on CKN[0]
19009 */
19010#define DDRPHY_ACBDLR16_CKN0BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_CKN0BD_SHIFT)) & DDRPHY_ACBDLR16_CKN0BD_MASK)
19011#define DDRPHY_ACBDLR16_RESERVED_7_6_MASK (0xC0U)
19012#define DDRPHY_ACBDLR16_RESERVED_7_6_SHIFT (6U)
19013/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
19014 */
19015#define DDRPHY_ACBDLR16_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_RESERVED_7_6_SHIFT)) & DDRPHY_ACBDLR16_RESERVED_7_6_MASK)
19016#define DDRPHY_ACBDLR16_CKN1BD_MASK (0x3F00U)
19017#define DDRPHY_ACBDLR16_CKN1BD_SHIFT (8U)
19018/*! CKN1BD - Delay select for the BDL on CKN[1]
19019 */
19020#define DDRPHY_ACBDLR16_CKN1BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_CKN1BD_SHIFT)) & DDRPHY_ACBDLR16_CKN1BD_MASK)
19021#define DDRPHY_ACBDLR16_RESERVED_15_14_MASK (0xC000U)
19022#define DDRPHY_ACBDLR16_RESERVED_15_14_SHIFT (14U)
19023/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
19024 */
19025#define DDRPHY_ACBDLR16_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_RESERVED_15_14_SHIFT)) & DDRPHY_ACBDLR16_RESERVED_15_14_MASK)
19026#define DDRPHY_ACBDLR16_CKN2BD_MASK (0x3F0000U)
19027#define DDRPHY_ACBDLR16_CKN2BD_SHIFT (16U)
19028/*! CKN2BD - Delay select for the BDL on CKN[2]
19029 */
19030#define DDRPHY_ACBDLR16_CKN2BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_CKN2BD_SHIFT)) & DDRPHY_ACBDLR16_CKN2BD_MASK)
19031#define DDRPHY_ACBDLR16_RESERVED_23_22_MASK (0xC00000U)
19032#define DDRPHY_ACBDLR16_RESERVED_23_22_SHIFT (22U)
19033/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
19034 */
19035#define DDRPHY_ACBDLR16_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_RESERVED_23_22_SHIFT)) & DDRPHY_ACBDLR16_RESERVED_23_22_MASK)
19036#define DDRPHY_ACBDLR16_CKN3BD_MASK (0x3F000000U)
19037#define DDRPHY_ACBDLR16_CKN3BD_SHIFT (24U)
19038/*! CKN3BD - Delay select for the BDL on CKN[3]
19039 */
19040#define DDRPHY_ACBDLR16_CKN3BD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_CKN3BD_SHIFT)) & DDRPHY_ACBDLR16_CKN3BD_MASK)
19041#define DDRPHY_ACBDLR16_RESERVED_31_30_MASK (0xC0000000U)
19042#define DDRPHY_ACBDLR16_RESERVED_31_30_SHIFT (30U)
19043/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
19044 */
19045#define DDRPHY_ACBDLR16_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACBDLR16_RESERVED_31_30_SHIFT)) & DDRPHY_ACBDLR16_RESERVED_31_30_MASK)
19046/*! @} */
19047
19048/*! @name ACLCDLR - AC Local Calibrated Delay Line Register */
19049/*! @{ */
19050#define DDRPHY_ACLCDLR_ACD_MASK (0x1FFU)
19051#define DDRPHY_ACLCDLR_ACD_SHIFT (0U)
19052/*! ACD - Address/Command Delay for AC Macro 0
19053 */
19054#define DDRPHY_ACLCDLR_ACD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACLCDLR_ACD_SHIFT)) & DDRPHY_ACLCDLR_ACD_MASK)
19055#define DDRPHY_ACLCDLR_RESERVED_15_9_MASK (0xFE00U)
19056#define DDRPHY_ACLCDLR_RESERVED_15_9_SHIFT (9U)
19057/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
19058 */
19059#define DDRPHY_ACLCDLR_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACLCDLR_RESERVED_15_9_SHIFT)) & DDRPHY_ACLCDLR_RESERVED_15_9_MASK)
19060#define DDRPHY_ACLCDLR_ACD1_MASK (0x1FF0000U)
19061#define DDRPHY_ACLCDLR_ACD1_SHIFT (16U)
19062/*! ACD1 - Address/Command Delay for AC Macro 1
19063 */
19064#define DDRPHY_ACLCDLR_ACD1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACLCDLR_ACD1_SHIFT)) & DDRPHY_ACLCDLR_ACD1_MASK)
19065#define DDRPHY_ACLCDLR_RESERVED_31_25_MASK (0xFE000000U)
19066#define DDRPHY_ACLCDLR_RESERVED_31_25_SHIFT (25U)
19067/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
19068 */
19069#define DDRPHY_ACLCDLR_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACLCDLR_RESERVED_31_25_SHIFT)) & DDRPHY_ACLCDLR_RESERVED_31_25_MASK)
19070/*! @} */
19071
19072/*! @name ACMDLR0 - AC Master Delay Line Register 0 */
19073/*! @{ */
19074#define DDRPHY_ACMDLR0_IPRD_MASK (0x1FFU)
19075#define DDRPHY_ACMDLR0_IPRD_SHIFT (0U)
19076/*! IPRD - Initial Period
19077 */
19078#define DDRPHY_ACMDLR0_IPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR0_IPRD_SHIFT)) & DDRPHY_ACMDLR0_IPRD_MASK)
19079#define DDRPHY_ACMDLR0_RESERVED_15_9_MASK (0xFE00U)
19080#define DDRPHY_ACMDLR0_RESERVED_15_9_SHIFT (9U)
19081/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
19082 */
19083#define DDRPHY_ACMDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_ACMDLR0_RESERVED_15_9_MASK)
19084#define DDRPHY_ACMDLR0_TPRD_MASK (0x1FF0000U)
19085#define DDRPHY_ACMDLR0_TPRD_SHIFT (16U)
19086/*! TPRD - Target Period
19087 */
19088#define DDRPHY_ACMDLR0_TPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR0_TPRD_SHIFT)) & DDRPHY_ACMDLR0_TPRD_MASK)
19089#define DDRPHY_ACMDLR0_RESERVED_31_25_MASK (0xFE000000U)
19090#define DDRPHY_ACMDLR0_RESERVED_31_25_SHIFT (25U)
19091/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
19092 */
19093#define DDRPHY_ACMDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_ACMDLR0_RESERVED_31_25_MASK)
19094/*! @} */
19095
19096/*! @name ACMDLR1 - AC Master Delay Line Register 1 */
19097/*! @{ */
19098#define DDRPHY_ACMDLR1_MDLD_MASK (0x1FFU)
19099#define DDRPHY_ACMDLR1_MDLD_SHIFT (0U)
19100/*! MDLD - MDL Delay for AC Macro 0
19101 */
19102#define DDRPHY_ACMDLR1_MDLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR1_MDLD_SHIFT)) & DDRPHY_ACMDLR1_MDLD_MASK)
19103#define DDRPHY_ACMDLR1_RESERVED_15_9_MASK (0xFE00U)
19104#define DDRPHY_ACMDLR1_RESERVED_15_9_SHIFT (9U)
19105/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
19106 */
19107#define DDRPHY_ACMDLR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_ACMDLR1_RESERVED_15_9_MASK)
19108#define DDRPHY_ACMDLR1_MDLD1_MASK (0x1FF0000U)
19109#define DDRPHY_ACMDLR1_MDLD1_SHIFT (16U)
19110/*! MDLD1 - MDL Delay for AC Macro 1
19111 */
19112#define DDRPHY_ACMDLR1_MDLD1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR1_MDLD1_SHIFT)) & DDRPHY_ACMDLR1_MDLD1_MASK)
19113#define DDRPHY_ACMDLR1_RESERVED_31_25_MASK (0xFE000000U)
19114#define DDRPHY_ACMDLR1_RESERVED_31_25_SHIFT (25U)
19115/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
19116 */
19117#define DDRPHY_ACMDLR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ACMDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_ACMDLR1_RESERVED_31_25_MASK)
19118/*! @} */
19119
19120/*! @name ZQCR - ZQ Impedance Control Register */
19121/*! @{ */
19122#define DDRPHY_ZQCR_ZQPD_MASK (0x1U)
19123#define DDRPHY_ZQCR_ZQPD_SHIFT (0U)
19124/*! ZQPD - ZQ Power Down
19125 */
19126#define DDRPHY_ZQCR_ZQPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_ZQPD_SHIFT)) & DDRPHY_ZQCR_ZQPD_MASK)
19127#define DDRPHY_ZQCR_ZCALT_MASK (0x2U)
19128#define DDRPHY_ZQCR_ZCALT_SHIFT (1U)
19129/*! ZCALT - ZQ Calibration Type
19130 */
19131#define DDRPHY_ZQCR_ZCALT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_ZCALT_SHIFT)) & DDRPHY_ZQCR_ZCALT_MASK)
19132#define DDRPHY_ZQCR_AVGMAX_MASK (0xCU)
19133#define DDRPHY_ZQCR_AVGMAX_SHIFT (2U)
19134/*! AVGMAX - Maximum number of averaging rounds to be used by averaging algorithm
19135 */
19136#define DDRPHY_ZQCR_AVGMAX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_AVGMAX_SHIFT)) & DDRPHY_ZQCR_AVGMAX_MASK)
19137#define DDRPHY_ZQCR_AVGEN_MASK (0x10U)
19138#define DDRPHY_ZQCR_AVGEN_SHIFT (4U)
19139/*! AVGEN - Averaging algorithm enable, if set, enables averaging algorithm
19140 */
19141#define DDRPHY_ZQCR_AVGEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_AVGEN_SHIFT)) & DDRPHY_ZQCR_AVGEN_MASK)
19142#define DDRPHY_ZQCR_IODLMT_MASK (0xE0U)
19143#define DDRPHY_ZQCR_IODLMT_SHIFT (5U)
19144/*! IODLMT - IO VT Drift Limit
19145 */
19146#define DDRPHY_ZQCR_IODLMT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_IODLMT_SHIFT)) & DDRPHY_ZQCR_IODLMT_MASK)
19147#define DDRPHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK (0x100U)
19148#define DDRPHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT (8U)
19149/*! FORCE_ZCAL_VT_UPDATE - Force ZCAL VT update
19150 */
19151#define DDRPHY_ZQCR_FORCE_ZCAL_VT_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT)) & DDRPHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK)
19152#define DDRPHY_ZQCR_ODT_MODE_MASK (0x600U)
19153#define DDRPHY_ZQCR_ODT_MODE_SHIFT (9U)
19154/*! ODT_MODE - Choice of termination mode
19155 */
19156#define DDRPHY_ZQCR_ODT_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_ODT_MODE_SHIFT)) & DDRPHY_ZQCR_ODT_MODE_MASK)
19157#define DDRPHY_ZQCR_ZQREFIEN_MASK (0x800U)
19158#define DDRPHY_ZQCR_ZQREFIEN_SHIFT (11U)
19159/*! ZQREFIEN - ZQ Internal VREF Enable
19160 */
19161#define DDRPHY_ZQCR_ZQREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_ZQREFIEN_SHIFT)) & DDRPHY_ZQCR_ZQREFIEN_MASK)
19162#define DDRPHY_ZQCR_ZQREFPEN_MASK (0x1000U)
19163#define DDRPHY_ZQCR_ZQREFPEN_SHIFT (12U)
19164/*! ZQREFPEN - ZQ VREF Pad Enable
19165 */
19166#define DDRPHY_ZQCR_ZQREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_ZQREFPEN_SHIFT)) & DDRPHY_ZQCR_ZQREFPEN_MASK)
19167#define DDRPHY_ZQCR_PGWAIT_FRQA_MASK (0x7E000U)
19168#define DDRPHY_ZQCR_PGWAIT_FRQA_SHIFT (13U)
19169/*! PGWAIT_FRQA - Programmable Wait for Frequency A
19170 */
19171#define DDRPHY_ZQCR_PGWAIT_FRQA(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_PGWAIT_FRQA_SHIFT)) & DDRPHY_ZQCR_PGWAIT_FRQA_MASK)
19172#define DDRPHY_ZQCR_PGWAIT_FRQB_MASK (0x1F80000U)
19173#define DDRPHY_ZQCR_PGWAIT_FRQB_SHIFT (19U)
19174/*! PGWAIT_FRQB - Programmable Wait for Frequency B
19175 */
19176#define DDRPHY_ZQCR_PGWAIT_FRQB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_PGWAIT_FRQB_SHIFT)) & DDRPHY_ZQCR_PGWAIT_FRQB_MASK)
19177#define DDRPHY_ZQCR_ZQREFISELRANGE_MASK (0x2000000U)
19178#define DDRPHY_ZQCR_ZQREFISELRANGE_SHIFT (25U)
19179/*! ZQREFISELRANGE - ZQ VREF Range
19180 */
19181#define DDRPHY_ZQCR_ZQREFISELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_ZQREFISELRANGE_SHIFT)) & DDRPHY_ZQCR_ZQREFISELRANGE_MASK)
19182#define DDRPHY_ZQCR_RESERVED_31_26_MASK (0xFC000000U)
19183#define DDRPHY_ZQCR_RESERVED_31_26_SHIFT (26U)
19184/*! RESERVED_31_26 - Reserved. Return zeroes on reads.
19185 */
19186#define DDRPHY_ZQCR_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQCR_RESERVED_31_26_SHIFT)) & DDRPHY_ZQCR_RESERVED_31_26_MASK)
19187/*! @} */
19188
19189/*! @name ZQ0PR0 - ZQ n Impedance Control Program Register 0 */
19190/*! @{ */
19191#define DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK (0xFU)
19192#define DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT (0U)
19193/*! ZPROG_ASYM_DRV_PU - Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
19194 */
19195#define DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT)) & DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK)
19196#define DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK (0xF0U)
19197#define DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT (4U)
19198/*! ZPROG_ASYM_DRV_PD - Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
19199 */
19200#define DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT)) & DDRPHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK)
19201#define DDRPHY_ZQ0PR0_ZPROG_HOST_ODT_MASK (0xF00U)
19202#define DDRPHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT (8U)
19203/*! ZPROG_HOST_ODT - HOST Impedance Divide Ratio
19204 */
19205#define DDRPHY_ZQ0PR0_ZPROG_HOST_ODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT)) & DDRPHY_ZQ0PR0_ZPROG_HOST_ODT_MASK)
19206#define DDRPHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK (0xF000U)
19207#define DDRPHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT (12U)
19208/*! ZPROG_DRAM_ODT - DRAM Impedance Divide Ratio
19209 */
19210#define DDRPHY_ZQ0PR0_ZPROG_DRAM_ODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT)) & DDRPHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK)
19211#define DDRPHY_ZQ0PR0_PU_DRV_ADJUST_MASK (0x70000U)
19212#define DDRPHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT (16U)
19213/*! PU_DRV_ADJUST - Pullup drive strength adjustment
19214 */
19215#define DDRPHY_ZQ0PR0_PU_DRV_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ0PR0_PU_DRV_ADJUST_MASK)
19216#define DDRPHY_ZQ0PR0_PD_DRV_ADJUST_MASK (0x380000U)
19217#define DDRPHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT (19U)
19218/*! PD_DRV_ADJUST - Pulldown drive strength adjustment
19219 */
19220#define DDRPHY_ZQ0PR0_PD_DRV_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ0PR0_PD_DRV_ADJUST_MASK)
19221#define DDRPHY_ZQ0PR0_ODT_ADJUST_MASK (0x1C00000U)
19222#define DDRPHY_ZQ0PR0_ODT_ADJUST_SHIFT (22U)
19223/*! ODT_ADJUST - Termination adjustment
19224 */
19225#define DDRPHY_ZQ0PR0_ODT_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ODT_ADJUST_SHIFT)) & DDRPHY_ZQ0PR0_ODT_ADJUST_MASK)
19226#define DDRPHY_ZQ0PR0_ZLE_MODE_MASK (0x6000000U)
19227#define DDRPHY_ZQ0PR0_ZLE_MODE_SHIFT (25U)
19228/*! ZLE_MODE - VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
19229 */
19230#define DDRPHY_ZQ0PR0_ZLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ZLE_MODE_SHIFT)) & DDRPHY_ZQ0PR0_ZLE_MODE_MASK)
19231#define DDRPHY_ZQ0PR0_ZSEGBYP_MASK (0x8000000U)
19232#define DDRPHY_ZQ0PR0_ZSEGBYP_SHIFT (27U)
19233/*! ZSEGBYP - Calibration segment bypass
19234 */
19235#define DDRPHY_ZQ0PR0_ZSEGBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_ZSEGBYP_SHIFT)) & DDRPHY_ZQ0PR0_ZSEGBYP_MASK)
19236#define DDRPHY_ZQ0PR0_PU_ODT_ZDEN_MASK (0x10000000U)
19237#define DDRPHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT (28U)
19238/*! PU_ODT_ZDEN - Pull-up termination ZCTRL over-ride enable
19239 */
19240#define DDRPHY_ZQ0PR0_PU_ODT_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ0PR0_PU_ODT_ZDEN_MASK)
19241#define DDRPHY_ZQ0PR0_PD_ODT_ZDEN_MASK (0x20000000U)
19242#define DDRPHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT (29U)
19243/*! PD_ODT_ZDEN - Pull-down termination ZCTRL over-ride enable
19244 */
19245#define DDRPHY_ZQ0PR0_PD_ODT_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ0PR0_PD_ODT_ZDEN_MASK)
19246#define DDRPHY_ZQ0PR0_PU_DRV_ZDEN_MASK (0x40000000U)
19247#define DDRPHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT (30U)
19248/*! PU_DRV_ZDEN - Pull-up drive strength ZCTRL over-ride enable
19249 */
19250#define DDRPHY_ZQ0PR0_PU_DRV_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ0PR0_PU_DRV_ZDEN_MASK)
19251#define DDRPHY_ZQ0PR0_PD_DRV_ZDEN_MASK (0x80000000U)
19252#define DDRPHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT (31U)
19253/*! PD_DRV_ZDEN - Pull-down drive strength ZCTRL over-ride enable
19254 */
19255#define DDRPHY_ZQ0PR0_PD_DRV_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ0PR0_PD_DRV_ZDEN_MASK)
19256/*! @} */
19257
19258/*! @name ZQ0PR1 - ZQ n Impedance Control Program Register 1 */
19259/*! @{ */
19260#define DDRPHY_ZQ0PR1_PD_REFSEL_MASK (0x7FU)
19261#define DDRPHY_ZQ0PR1_PD_REFSEL_SHIFT (0U)
19262/*! PD_REFSEL - Pull-down REFSEL for PZCTRL cell
19263 */
19264#define DDRPHY_ZQ0PR1_PD_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR1_PD_REFSEL_SHIFT)) & DDRPHY_ZQ0PR1_PD_REFSEL_MASK)
19265#define DDRPHY_ZQ0PR1_RESERVED_7_MASK (0x80U)
19266#define DDRPHY_ZQ0PR1_RESERVED_7_SHIFT (7U)
19267/*! RESERVED_7 - Reserved. Return zeros on reads.
19268 */
19269#define DDRPHY_ZQ0PR1_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR1_RESERVED_7_SHIFT)) & DDRPHY_ZQ0PR1_RESERVED_7_MASK)
19270#define DDRPHY_ZQ0PR1_PU_REFSEL_MASK (0x7F00U)
19271#define DDRPHY_ZQ0PR1_PU_REFSEL_SHIFT (8U)
19272/*! PU_REFSEL - Pull-up REFSEL for PZCTRL cell
19273 */
19274#define DDRPHY_ZQ0PR1_PU_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR1_PU_REFSEL_SHIFT)) & DDRPHY_ZQ0PR1_PU_REFSEL_MASK)
19275#define DDRPHY_ZQ0PR1_RESERVED_31_15_MASK (0xFFFF8000U)
19276#define DDRPHY_ZQ0PR1_RESERVED_31_15_SHIFT (15U)
19277/*! RESERVED_31_15 - Reserved. Return zeros on reads.
19278 */
19279#define DDRPHY_ZQ0PR1_RESERVED_31_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0PR1_RESERVED_31_15_SHIFT)) & DDRPHY_ZQ0PR1_RESERVED_31_15_MASK)
19280/*! @} */
19281
19282/*! @name ZQ0DR0 - ZQ n Impedance Control Data Register 0 */
19283/*! @{ */
19284#define DDRPHY_ZQ0DR0_ZDATA_PD_DRV_RESULT_MASK (0x3FFU)
19285#define DDRPHY_ZQ0DR0_ZDATA_PD_DRV_RESULT_SHIFT (0U)
19286/*! ZDATA_PD_DRV_RESULT - Pull-down drive strength calibration code result
19287 */
19288#define DDRPHY_ZQ0DR0_ZDATA_PD_DRV_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR0_ZDATA_PD_DRV_RESULT_SHIFT)) & DDRPHY_ZQ0DR0_ZDATA_PD_DRV_RESULT_MASK)
19289#define DDRPHY_ZQ0DR0_RESERVED_15_10_MASK (0xFC00U)
19290#define DDRPHY_ZQ0DR0_RESERVED_15_10_SHIFT (10U)
19291/*! RESERVED_15_10 - Reserved. Return zeros on reads.
19292 */
19293#define DDRPHY_ZQ0DR0_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ0DR0_RESERVED_15_10_MASK)
19294#define DDRPHY_ZQ0DR0_ZDATA_PU_DRV_RESULT_MASK (0x3FF0000U)
19295#define DDRPHY_ZQ0DR0_ZDATA_PU_DRV_RESULT_SHIFT (16U)
19296/*! ZDATA_PU_DRV_RESULT - Pull-up drive strength calibration code result
19297 */
19298#define DDRPHY_ZQ0DR0_ZDATA_PU_DRV_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR0_ZDATA_PU_DRV_RESULT_SHIFT)) & DDRPHY_ZQ0DR0_ZDATA_PU_DRV_RESULT_MASK)
19299#define DDRPHY_ZQ0DR0_RESERVED_31_26_MASK (0xFC000000U)
19300#define DDRPHY_ZQ0DR0_RESERVED_31_26_SHIFT (26U)
19301/*! RESERVED_31_26 - Reserved. Return zeros on reads.
19302 */
19303#define DDRPHY_ZQ0DR0_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ0DR0_RESERVED_31_26_MASK)
19304/*! @} */
19305
19306/*! @name ZQ0DR1 - ZQ n Impedance Control Data Register 1 */
19307/*! @{ */
19308#define DDRPHY_ZQ0DR1_ZDATA_PD_ODT_RESULT_MASK (0x3FFU)
19309#define DDRPHY_ZQ0DR1_ZDATA_PD_ODT_RESULT_SHIFT (0U)
19310/*! ZDATA_PD_ODT_RESULT - Pull-down termination calibration code result
19311 */
19312#define DDRPHY_ZQ0DR1_ZDATA_PD_ODT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR1_ZDATA_PD_ODT_RESULT_SHIFT)) & DDRPHY_ZQ0DR1_ZDATA_PD_ODT_RESULT_MASK)
19313#define DDRPHY_ZQ0DR1_RESERVED_15_10_MASK (0xFC00U)
19314#define DDRPHY_ZQ0DR1_RESERVED_15_10_SHIFT (10U)
19315/*! RESERVED_15_10 - Reserved. Return zeros on reads.
19316 */
19317#define DDRPHY_ZQ0DR1_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ0DR1_RESERVED_15_10_MASK)
19318#define DDRPHY_ZQ0DR1_ZDATA_PU_ODT_RESULT_MASK (0x3FF0000U)
19319#define DDRPHY_ZQ0DR1_ZDATA_PU_ODT_RESULT_SHIFT (16U)
19320/*! ZDATA_PU_ODT_RESULT - Pull-up termination calibration code result
19321 */
19322#define DDRPHY_ZQ0DR1_ZDATA_PU_ODT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR1_ZDATA_PU_ODT_RESULT_SHIFT)) & DDRPHY_ZQ0DR1_ZDATA_PU_ODT_RESULT_MASK)
19323#define DDRPHY_ZQ0DR1_RESERVED_31_26_MASK (0xFC000000U)
19324#define DDRPHY_ZQ0DR1_RESERVED_31_26_SHIFT (26U)
19325/*! RESERVED_31_26 - Reserved. Return zeros on reads.
19326 */
19327#define DDRPHY_ZQ0DR1_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0DR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ0DR1_RESERVED_31_26_MASK)
19328/*! @} */
19329
19330/*! @name ZQ0OR0 - ZQ n Impedance Control Override Data Register 0 */
19331/*! @{ */
19332#define DDRPHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK (0x3FFU)
19333#define DDRPHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT (0U)
19334/*! ZDATA_PD_DRV_OVRD - Override value for the pull-down output impedance
19335 */
19336#define DDRPHY_ZQ0OR0_ZDATA_PD_DRV_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT)) & DDRPHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK)
19337#define DDRPHY_ZQ0OR0_RESERVED_15_10_MASK (0xFC00U)
19338#define DDRPHY_ZQ0OR0_RESERVED_15_10_SHIFT (10U)
19339/*! RESERVED_15_10 - Reserved. Return zeros on reads.
19340 */
19341#define DDRPHY_ZQ0OR0_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ0OR0_RESERVED_15_10_MASK)
19342#define DDRPHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK (0x3FF0000U)
19343#define DDRPHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT (16U)
19344/*! ZDATA_PU_DRV_OVRD - Override value for the pull-up output impedance
19345 */
19346#define DDRPHY_ZQ0OR0_ZDATA_PU_DRV_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT)) & DDRPHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK)
19347#define DDRPHY_ZQ0OR0_RESERVED_31_26_MASK (0xFC000000U)
19348#define DDRPHY_ZQ0OR0_RESERVED_31_26_SHIFT (26U)
19349/*! RESERVED_31_26 - Reserved. Return zeros on reads.
19350 */
19351#define DDRPHY_ZQ0OR0_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ0OR0_RESERVED_31_26_MASK)
19352/*! @} */
19353
19354/*! @name ZQ0OR1 - ZQ n Impedance Control Override Data Register 1 */
19355/*! @{ */
19356#define DDRPHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK (0x3FFU)
19357#define DDRPHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT (0U)
19358/*! ZDATA_PD_ODT_OVRD - Override value for the pull-down termination
19359 */
19360#define DDRPHY_ZQ0OR1_ZDATA_PD_ODT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT)) & DDRPHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK)
19361#define DDRPHY_ZQ0OR1_RESERVED_15_10_MASK (0xFC00U)
19362#define DDRPHY_ZQ0OR1_RESERVED_15_10_SHIFT (10U)
19363/*! RESERVED_15_10 - Reserved. Return zeros on reads.
19364 */
19365#define DDRPHY_ZQ0OR1_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ0OR1_RESERVED_15_10_MASK)
19366#define DDRPHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK (0x3FF0000U)
19367#define DDRPHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT (16U)
19368/*! ZDATA_PU_ODT_OVRD - Override value for the pull-up termination
19369 */
19370#define DDRPHY_ZQ0OR1_ZDATA_PU_ODT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT)) & DDRPHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK)
19371#define DDRPHY_ZQ0OR1_RESERVED_31_26_MASK (0xFC000000U)
19372#define DDRPHY_ZQ0OR1_RESERVED_31_26_SHIFT (26U)
19373/*! RESERVED_31_26 - Reserved. Return zeros on reads.
19374 */
19375#define DDRPHY_ZQ0OR1_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0OR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ0OR1_RESERVED_31_26_MASK)
19376/*! @} */
19377
19378/*! @name ZQ0SR - ZQ n Impedance Control Status Register */
19379/*! @{ */
19380#define DDRPHY_ZQ0SR_ZPD_MASK (0x3U)
19381#define DDRPHY_ZQ0SR_ZPD_SHIFT (0U)
19382/*! ZPD - Output impedance pull-down calibration status
19383 */
19384#define DDRPHY_ZQ0SR_ZPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_ZPD_SHIFT)) & DDRPHY_ZQ0SR_ZPD_MASK)
19385#define DDRPHY_ZQ0SR_ZPU_MASK (0xCU)
19386#define DDRPHY_ZQ0SR_ZPU_SHIFT (2U)
19387/*! ZPU - Output impedance pull-up calibration status
19388 */
19389#define DDRPHY_ZQ0SR_ZPU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_ZPU_SHIFT)) & DDRPHY_ZQ0SR_ZPU_MASK)
19390#define DDRPHY_ZQ0SR_OPD_MASK (0x30U)
19391#define DDRPHY_ZQ0SR_OPD_SHIFT (4U)
19392/*! OPD - On-die termination (ODT) pull-down calibration status
19393 */
19394#define DDRPHY_ZQ0SR_OPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_OPD_SHIFT)) & DDRPHY_ZQ0SR_OPD_MASK)
19395#define DDRPHY_ZQ0SR_OPU_MASK (0xC0U)
19396#define DDRPHY_ZQ0SR_OPU_SHIFT (6U)
19397/*! OPU - On-die termination (ODT) pull-up calibration status
19398 */
19399#define DDRPHY_ZQ0SR_OPU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_OPU_SHIFT)) & DDRPHY_ZQ0SR_OPU_MASK)
19400#define DDRPHY_ZQ0SR_ZERR_MASK (0x100U)
19401#define DDRPHY_ZQ0SR_ZERR_SHIFT (8U)
19402/*! ZERR - Impedance Calibration Error
19403 */
19404#define DDRPHY_ZQ0SR_ZERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_ZERR_SHIFT)) & DDRPHY_ZQ0SR_ZERR_MASK)
19405#define DDRPHY_ZQ0SR_ZDONE_MASK (0x200U)
19406#define DDRPHY_ZQ0SR_ZDONE_SHIFT (9U)
19407/*! ZDONE - Impedance Calibration Done
19408 */
19409#define DDRPHY_ZQ0SR_ZDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_ZDONE_SHIFT)) & DDRPHY_ZQ0SR_ZDONE_MASK)
19410#define DDRPHY_ZQ0SR_PU_DRV_SAT_MASK (0x400U)
19411#define DDRPHY_ZQ0SR_PU_DRV_SAT_SHIFT (10U)
19412/*! PU_DRV_SAT - Pullup drive strength code saturated due to drive strength adjustment setting in ZQnPR register
19413 */
19414#define DDRPHY_ZQ0SR_PU_DRV_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_PU_DRV_SAT_SHIFT)) & DDRPHY_ZQ0SR_PU_DRV_SAT_MASK)
19415#define DDRPHY_ZQ0SR_PD_DRV_SAT_MASK (0x800U)
19416#define DDRPHY_ZQ0SR_PD_DRV_SAT_SHIFT (11U)
19417/*! PD_DRV_SAT - Pulldown drive strength code saturated due to drive strength adjustment setting in ZQnPR register
19418 */
19419#define DDRPHY_ZQ0SR_PD_DRV_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_PD_DRV_SAT_SHIFT)) & DDRPHY_ZQ0SR_PD_DRV_SAT_MASK)
19420#define DDRPHY_ZQ0SR_PU_ODT_SAT_MASK (0x1000U)
19421#define DDRPHY_ZQ0SR_PU_ODT_SAT_SHIFT (12U)
19422/*! PU_ODT_SAT - Pullup drive strength code saturated due to termination strength adjustment setting in ZQnPR register
19423 */
19424#define DDRPHY_ZQ0SR_PU_ODT_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_PU_ODT_SAT_SHIFT)) & DDRPHY_ZQ0SR_PU_ODT_SAT_MASK)
19425#define DDRPHY_ZQ0SR_PD_ODT_SAT_MASK (0x2000U)
19426#define DDRPHY_ZQ0SR_PD_ODT_SAT_SHIFT (13U)
19427/*! PD_ODT_SAT - Pulldown drive strength code saturated due to termination strength adjustment setting in ZQnPR register
19428 */
19429#define DDRPHY_ZQ0SR_PD_ODT_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_PD_ODT_SAT_SHIFT)) & DDRPHY_ZQ0SR_PD_ODT_SAT_MASK)
19430#define DDRPHY_ZQ0SR_RESERVED_31_14_MASK (0xFFFFC000U)
19431#define DDRPHY_ZQ0SR_RESERVED_31_14_SHIFT (14U)
19432/*! RESERVED_31_14 - Reserved. Return zeros on reads.
19433 */
19434#define DDRPHY_ZQ0SR_RESERVED_31_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ0SR_RESERVED_31_14_SHIFT)) & DDRPHY_ZQ0SR_RESERVED_31_14_MASK)
19435/*! @} */
19436
19437/*! @name ZQ1PR0 - ZQ n Impedance Control Program Register 0 */
19438/*! @{ */
19439#define DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK (0xFU)
19440#define DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT (0U)
19441/*! ZPROG_ASYM_DRV_PU - Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
19442 */
19443#define DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT)) & DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK)
19444#define DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK (0xF0U)
19445#define DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT (4U)
19446/*! ZPROG_ASYM_DRV_PD - Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
19447 */
19448#define DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT)) & DDRPHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK)
19449#define DDRPHY_ZQ1PR0_ZPROG_HOST_ODT_MASK (0xF00U)
19450#define DDRPHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT (8U)
19451/*! ZPROG_HOST_ODT - HOST Impedance Divide Ratio
19452 */
19453#define DDRPHY_ZQ1PR0_ZPROG_HOST_ODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT)) & DDRPHY_ZQ1PR0_ZPROG_HOST_ODT_MASK)
19454#define DDRPHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK (0xF000U)
19455#define DDRPHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT (12U)
19456/*! ZPROG_DRAM_ODT - DRAM Impedance Divide Ratio
19457 */
19458#define DDRPHY_ZQ1PR0_ZPROG_DRAM_ODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT)) & DDRPHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK)
19459#define DDRPHY_ZQ1PR0_PU_DRV_ADJUST_MASK (0x70000U)
19460#define DDRPHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT (16U)
19461/*! PU_DRV_ADJUST - Pullup drive strength adjustment
19462 */
19463#define DDRPHY_ZQ1PR0_PU_DRV_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ1PR0_PU_DRV_ADJUST_MASK)
19464#define DDRPHY_ZQ1PR0_PD_DRV_ADJUST_MASK (0x380000U)
19465#define DDRPHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT (19U)
19466/*! PD_DRV_ADJUST - Pulldown drive strength adjustment
19467 */
19468#define DDRPHY_ZQ1PR0_PD_DRV_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ1PR0_PD_DRV_ADJUST_MASK)
19469#define DDRPHY_ZQ1PR0_ODT_ADJUST_MASK (0x1C00000U)
19470#define DDRPHY_ZQ1PR0_ODT_ADJUST_SHIFT (22U)
19471/*! ODT_ADJUST - Termination adjustment
19472 */
19473#define DDRPHY_ZQ1PR0_ODT_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ODT_ADJUST_SHIFT)) & DDRPHY_ZQ1PR0_ODT_ADJUST_MASK)
19474#define DDRPHY_ZQ1PR0_ZLE_MODE_MASK (0x6000000U)
19475#define DDRPHY_ZQ1PR0_ZLE_MODE_SHIFT (25U)
19476/*! ZLE_MODE - VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
19477 */
19478#define DDRPHY_ZQ1PR0_ZLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ZLE_MODE_SHIFT)) & DDRPHY_ZQ1PR0_ZLE_MODE_MASK)
19479#define DDRPHY_ZQ1PR0_ZSEGBYP_MASK (0x8000000U)
19480#define DDRPHY_ZQ1PR0_ZSEGBYP_SHIFT (27U)
19481/*! ZSEGBYP - Calibration segment bypass
19482 */
19483#define DDRPHY_ZQ1PR0_ZSEGBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_ZSEGBYP_SHIFT)) & DDRPHY_ZQ1PR0_ZSEGBYP_MASK)
19484#define DDRPHY_ZQ1PR0_PU_ODT_ZDEN_MASK (0x10000000U)
19485#define DDRPHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT (28U)
19486/*! PU_ODT_ZDEN - Pull-up termination ZCTRL over-ride enable
19487 */
19488#define DDRPHY_ZQ1PR0_PU_ODT_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ1PR0_PU_ODT_ZDEN_MASK)
19489#define DDRPHY_ZQ1PR0_PD_ODT_ZDEN_MASK (0x20000000U)
19490#define DDRPHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT (29U)
19491/*! PD_ODT_ZDEN - Pull-down termination ZCTRL over-ride enable
19492 */
19493#define DDRPHY_ZQ1PR0_PD_ODT_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ1PR0_PD_ODT_ZDEN_MASK)
19494#define DDRPHY_ZQ1PR0_PU_DRV_ZDEN_MASK (0x40000000U)
19495#define DDRPHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT (30U)
19496/*! PU_DRV_ZDEN - Pull-up drive strength ZCTRL over-ride enable
19497 */
19498#define DDRPHY_ZQ1PR0_PU_DRV_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ1PR0_PU_DRV_ZDEN_MASK)
19499#define DDRPHY_ZQ1PR0_PD_DRV_ZDEN_MASK (0x80000000U)
19500#define DDRPHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT (31U)
19501/*! PD_DRV_ZDEN - Pull-down drive strength ZCTRL over-ride enable
19502 */
19503#define DDRPHY_ZQ1PR0_PD_DRV_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ1PR0_PD_DRV_ZDEN_MASK)
19504/*! @} */
19505
19506/*! @name ZQ1PR1 - ZQ n Impedance Control Program Register 1 */
19507/*! @{ */
19508#define DDRPHY_ZQ1PR1_PD_REFSEL_MASK (0x7FU)
19509#define DDRPHY_ZQ1PR1_PD_REFSEL_SHIFT (0U)
19510/*! PD_REFSEL - Pull-down REFSEL for PZCTRL cell
19511 */
19512#define DDRPHY_ZQ1PR1_PD_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR1_PD_REFSEL_SHIFT)) & DDRPHY_ZQ1PR1_PD_REFSEL_MASK)
19513#define DDRPHY_ZQ1PR1_RESERVED_7_MASK (0x80U)
19514#define DDRPHY_ZQ1PR1_RESERVED_7_SHIFT (7U)
19515/*! RESERVED_7 - Reserved. Return zeros on reads.
19516 */
19517#define DDRPHY_ZQ1PR1_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR1_RESERVED_7_SHIFT)) & DDRPHY_ZQ1PR1_RESERVED_7_MASK)
19518#define DDRPHY_ZQ1PR1_PU_REFSEL_MASK (0x7F00U)
19519#define DDRPHY_ZQ1PR1_PU_REFSEL_SHIFT (8U)
19520/*! PU_REFSEL - Pull-up REFSEL for PZCTRL cell
19521 */
19522#define DDRPHY_ZQ1PR1_PU_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR1_PU_REFSEL_SHIFT)) & DDRPHY_ZQ1PR1_PU_REFSEL_MASK)
19523#define DDRPHY_ZQ1PR1_RESERVED_31_15_MASK (0xFFFF8000U)
19524#define DDRPHY_ZQ1PR1_RESERVED_31_15_SHIFT (15U)
19525/*! RESERVED_31_15 - Reserved. Return zeros on reads.
19526 */
19527#define DDRPHY_ZQ1PR1_RESERVED_31_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1PR1_RESERVED_31_15_SHIFT)) & DDRPHY_ZQ1PR1_RESERVED_31_15_MASK)
19528/*! @} */
19529
19530/*! @name ZQ1DR0 - ZQ n Impedance Control Data Register 0 */
19531/*! @{ */
19532#define DDRPHY_ZQ1DR0_ZDATA_PD_DRV_RESULT_MASK (0x3FFU)
19533#define DDRPHY_ZQ1DR0_ZDATA_PD_DRV_RESULT_SHIFT (0U)
19534/*! ZDATA_PD_DRV_RESULT - Pull-down drive strength calibration code result
19535 */
19536#define DDRPHY_ZQ1DR0_ZDATA_PD_DRV_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR0_ZDATA_PD_DRV_RESULT_SHIFT)) & DDRPHY_ZQ1DR0_ZDATA_PD_DRV_RESULT_MASK)
19537#define DDRPHY_ZQ1DR0_RESERVED_15_10_MASK (0xFC00U)
19538#define DDRPHY_ZQ1DR0_RESERVED_15_10_SHIFT (10U)
19539/*! RESERVED_15_10 - Reserved. Return zeros on reads.
19540 */
19541#define DDRPHY_ZQ1DR0_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ1DR0_RESERVED_15_10_MASK)
19542#define DDRPHY_ZQ1DR0_ZDATA_PU_DRV_RESULT_MASK (0x3FF0000U)
19543#define DDRPHY_ZQ1DR0_ZDATA_PU_DRV_RESULT_SHIFT (16U)
19544/*! ZDATA_PU_DRV_RESULT - Pull-up drive strength calibration code result
19545 */
19546#define DDRPHY_ZQ1DR0_ZDATA_PU_DRV_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR0_ZDATA_PU_DRV_RESULT_SHIFT)) & DDRPHY_ZQ1DR0_ZDATA_PU_DRV_RESULT_MASK)
19547#define DDRPHY_ZQ1DR0_RESERVED_31_26_MASK (0xFC000000U)
19548#define DDRPHY_ZQ1DR0_RESERVED_31_26_SHIFT (26U)
19549/*! RESERVED_31_26 - Reserved. Return zeros on reads.
19550 */
19551#define DDRPHY_ZQ1DR0_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ1DR0_RESERVED_31_26_MASK)
19552/*! @} */
19553
19554/*! @name ZQ1DR1 - ZQ n Impedance Control Data Register 1 */
19555/*! @{ */
19556#define DDRPHY_ZQ1DR1_ZDATA_PD_ODT_RESULT_MASK (0x3FFU)
19557#define DDRPHY_ZQ1DR1_ZDATA_PD_ODT_RESULT_SHIFT (0U)
19558/*! ZDATA_PD_ODT_RESULT - Pull-down termination calibration code result
19559 */
19560#define DDRPHY_ZQ1DR1_ZDATA_PD_ODT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR1_ZDATA_PD_ODT_RESULT_SHIFT)) & DDRPHY_ZQ1DR1_ZDATA_PD_ODT_RESULT_MASK)
19561#define DDRPHY_ZQ1DR1_RESERVED_15_10_MASK (0xFC00U)
19562#define DDRPHY_ZQ1DR1_RESERVED_15_10_SHIFT (10U)
19563/*! RESERVED_15_10 - Reserved. Return zeros on reads.
19564 */
19565#define DDRPHY_ZQ1DR1_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ1DR1_RESERVED_15_10_MASK)
19566#define DDRPHY_ZQ1DR1_ZDATA_PU_ODT_RESULT_MASK (0x3FF0000U)
19567#define DDRPHY_ZQ1DR1_ZDATA_PU_ODT_RESULT_SHIFT (16U)
19568/*! ZDATA_PU_ODT_RESULT - Pull-up termination calibration code result
19569 */
19570#define DDRPHY_ZQ1DR1_ZDATA_PU_ODT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR1_ZDATA_PU_ODT_RESULT_SHIFT)) & DDRPHY_ZQ1DR1_ZDATA_PU_ODT_RESULT_MASK)
19571#define DDRPHY_ZQ1DR1_RESERVED_31_26_MASK (0xFC000000U)
19572#define DDRPHY_ZQ1DR1_RESERVED_31_26_SHIFT (26U)
19573/*! RESERVED_31_26 - Reserved. Return zeros on reads.
19574 */
19575#define DDRPHY_ZQ1DR1_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1DR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ1DR1_RESERVED_31_26_MASK)
19576/*! @} */
19577
19578/*! @name ZQ1OR0 - ZQ n Impedance Control Override Data Register 0 */
19579/*! @{ */
19580#define DDRPHY_ZQ1OR0_ZDATA_PD_DRV_OVRD_MASK (0x3FFU)
19581#define DDRPHY_ZQ1OR0_ZDATA_PD_DRV_OVRD_SHIFT (0U)
19582/*! ZDATA_PD_DRV_OVRD - Override value for the pull-down output impedance
19583 */
19584#define DDRPHY_ZQ1OR0_ZDATA_PD_DRV_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR0_ZDATA_PD_DRV_OVRD_SHIFT)) & DDRPHY_ZQ1OR0_ZDATA_PD_DRV_OVRD_MASK)
19585#define DDRPHY_ZQ1OR0_RESERVED_15_10_MASK (0xFC00U)
19586#define DDRPHY_ZQ1OR0_RESERVED_15_10_SHIFT (10U)
19587/*! RESERVED_15_10 - Reserved. Return zeros on reads.
19588 */
19589#define DDRPHY_ZQ1OR0_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ1OR0_RESERVED_15_10_MASK)
19590#define DDRPHY_ZQ1OR0_ZDATA_PU_DRV_OVRD_MASK (0x3FF0000U)
19591#define DDRPHY_ZQ1OR0_ZDATA_PU_DRV_OVRD_SHIFT (16U)
19592/*! ZDATA_PU_DRV_OVRD - Override value for the pull-up output impedance
19593 */
19594#define DDRPHY_ZQ1OR0_ZDATA_PU_DRV_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR0_ZDATA_PU_DRV_OVRD_SHIFT)) & DDRPHY_ZQ1OR0_ZDATA_PU_DRV_OVRD_MASK)
19595#define DDRPHY_ZQ1OR0_RESERVED_31_26_MASK (0xFC000000U)
19596#define DDRPHY_ZQ1OR0_RESERVED_31_26_SHIFT (26U)
19597/*! RESERVED_31_26 - Reserved. Return zeros on reads.
19598 */
19599#define DDRPHY_ZQ1OR0_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ1OR0_RESERVED_31_26_MASK)
19600/*! @} */
19601
19602/*! @name ZQ1OR1 - ZQ n Impedance Control Override Data Register 1 */
19603/*! @{ */
19604#define DDRPHY_ZQ1OR1_ZDATA_PD_ODT_OVRD_MASK (0x3FFU)
19605#define DDRPHY_ZQ1OR1_ZDATA_PD_ODT_OVRD_SHIFT (0U)
19606/*! ZDATA_PD_ODT_OVRD - Override value for the pull-down termination
19607 */
19608#define DDRPHY_ZQ1OR1_ZDATA_PD_ODT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR1_ZDATA_PD_ODT_OVRD_SHIFT)) & DDRPHY_ZQ1OR1_ZDATA_PD_ODT_OVRD_MASK)
19609#define DDRPHY_ZQ1OR1_RESERVED_15_10_MASK (0xFC00U)
19610#define DDRPHY_ZQ1OR1_RESERVED_15_10_SHIFT (10U)
19611/*! RESERVED_15_10 - Reserved. Return zeros on reads.
19612 */
19613#define DDRPHY_ZQ1OR1_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ1OR1_RESERVED_15_10_MASK)
19614#define DDRPHY_ZQ1OR1_ZDATA_PU_ODT_OVRD_MASK (0x3FF0000U)
19615#define DDRPHY_ZQ1OR1_ZDATA_PU_ODT_OVRD_SHIFT (16U)
19616/*! ZDATA_PU_ODT_OVRD - Override value for the pull-up termination
19617 */
19618#define DDRPHY_ZQ1OR1_ZDATA_PU_ODT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR1_ZDATA_PU_ODT_OVRD_SHIFT)) & DDRPHY_ZQ1OR1_ZDATA_PU_ODT_OVRD_MASK)
19619#define DDRPHY_ZQ1OR1_RESERVED_31_26_MASK (0xFC000000U)
19620#define DDRPHY_ZQ1OR1_RESERVED_31_26_SHIFT (26U)
19621/*! RESERVED_31_26 - Reserved. Return zeros on reads.
19622 */
19623#define DDRPHY_ZQ1OR1_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1OR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ1OR1_RESERVED_31_26_MASK)
19624/*! @} */
19625
19626/*! @name ZQ1SR - ZQ n Impedance Control Status Register */
19627/*! @{ */
19628#define DDRPHY_ZQ1SR_ZPD_MASK (0x3U)
19629#define DDRPHY_ZQ1SR_ZPD_SHIFT (0U)
19630/*! ZPD - Output impedance pull-down calibration status
19631 */
19632#define DDRPHY_ZQ1SR_ZPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_ZPD_SHIFT)) & DDRPHY_ZQ1SR_ZPD_MASK)
19633#define DDRPHY_ZQ1SR_ZPU_MASK (0xCU)
19634#define DDRPHY_ZQ1SR_ZPU_SHIFT (2U)
19635/*! ZPU - Output impedance pull-up calibration status
19636 */
19637#define DDRPHY_ZQ1SR_ZPU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_ZPU_SHIFT)) & DDRPHY_ZQ1SR_ZPU_MASK)
19638#define DDRPHY_ZQ1SR_OPD_MASK (0x30U)
19639#define DDRPHY_ZQ1SR_OPD_SHIFT (4U)
19640/*! OPD - On-die termination (ODT) pull-down calibration status
19641 */
19642#define DDRPHY_ZQ1SR_OPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_OPD_SHIFT)) & DDRPHY_ZQ1SR_OPD_MASK)
19643#define DDRPHY_ZQ1SR_OPU_MASK (0xC0U)
19644#define DDRPHY_ZQ1SR_OPU_SHIFT (6U)
19645/*! OPU - On-die termination (ODT) pull-up calibration status
19646 */
19647#define DDRPHY_ZQ1SR_OPU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_OPU_SHIFT)) & DDRPHY_ZQ1SR_OPU_MASK)
19648#define DDRPHY_ZQ1SR_ZERR_MASK (0x100U)
19649#define DDRPHY_ZQ1SR_ZERR_SHIFT (8U)
19650/*! ZERR - Impedance Calibration Error
19651 */
19652#define DDRPHY_ZQ1SR_ZERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_ZERR_SHIFT)) & DDRPHY_ZQ1SR_ZERR_MASK)
19653#define DDRPHY_ZQ1SR_ZDONE_MASK (0x200U)
19654#define DDRPHY_ZQ1SR_ZDONE_SHIFT (9U)
19655/*! ZDONE - Impedance Calibration Done
19656 */
19657#define DDRPHY_ZQ1SR_ZDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_ZDONE_SHIFT)) & DDRPHY_ZQ1SR_ZDONE_MASK)
19658#define DDRPHY_ZQ1SR_PU_DRV_SAT_MASK (0x400U)
19659#define DDRPHY_ZQ1SR_PU_DRV_SAT_SHIFT (10U)
19660/*! PU_DRV_SAT - Pullup drive strength code saturated due to drive strength adjustment setting in ZQnPR register
19661 */
19662#define DDRPHY_ZQ1SR_PU_DRV_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_PU_DRV_SAT_SHIFT)) & DDRPHY_ZQ1SR_PU_DRV_SAT_MASK)
19663#define DDRPHY_ZQ1SR_PD_DRV_SAT_MASK (0x800U)
19664#define DDRPHY_ZQ1SR_PD_DRV_SAT_SHIFT (11U)
19665/*! PD_DRV_SAT - Pulldown drive strength code saturated due to drive strength adjustment setting in ZQnPR register
19666 */
19667#define DDRPHY_ZQ1SR_PD_DRV_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_PD_DRV_SAT_SHIFT)) & DDRPHY_ZQ1SR_PD_DRV_SAT_MASK)
19668#define DDRPHY_ZQ1SR_PU_ODT_SAT_MASK (0x1000U)
19669#define DDRPHY_ZQ1SR_PU_ODT_SAT_SHIFT (12U)
19670/*! PU_ODT_SAT - Pullup drive strength code saturated due to termination strength adjustment setting in ZQnPR register
19671 */
19672#define DDRPHY_ZQ1SR_PU_ODT_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_PU_ODT_SAT_SHIFT)) & DDRPHY_ZQ1SR_PU_ODT_SAT_MASK)
19673#define DDRPHY_ZQ1SR_PD_ODT_SAT_MASK (0x2000U)
19674#define DDRPHY_ZQ1SR_PD_ODT_SAT_SHIFT (13U)
19675/*! PD_ODT_SAT - Pulldown drive strength code saturated due to termination strength adjustment setting in ZQnPR register
19676 */
19677#define DDRPHY_ZQ1SR_PD_ODT_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_PD_ODT_SAT_SHIFT)) & DDRPHY_ZQ1SR_PD_ODT_SAT_MASK)
19678#define DDRPHY_ZQ1SR_RESERVED_31_14_MASK (0xFFFFC000U)
19679#define DDRPHY_ZQ1SR_RESERVED_31_14_SHIFT (14U)
19680/*! RESERVED_31_14 - Reserved. Return zeros on reads.
19681 */
19682#define DDRPHY_ZQ1SR_RESERVED_31_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ1SR_RESERVED_31_14_SHIFT)) & DDRPHY_ZQ1SR_RESERVED_31_14_MASK)
19683/*! @} */
19684
19685/*! @name ZQ2PR0 - ZQ n Impedance Control Program Register 0 */
19686/*! @{ */
19687#define DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PU_MASK (0xFU)
19688#define DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PU_SHIFT (0U)
19689/*! ZPROG_ASYM_DRV_PU - Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
19690 */
19691#define DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PU_SHIFT)) & DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PU_MASK)
19692#define DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PD_MASK (0xF0U)
19693#define DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PD_SHIFT (4U)
19694/*! ZPROG_ASYM_DRV_PD - Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
19695 */
19696#define DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PD_SHIFT)) & DDRPHY_ZQ2PR0_ZPROG_ASYM_DRV_PD_MASK)
19697#define DDRPHY_ZQ2PR0_ZPROG_HOST_ODT_MASK (0xF00U)
19698#define DDRPHY_ZQ2PR0_ZPROG_HOST_ODT_SHIFT (8U)
19699/*! ZPROG_HOST_ODT - HOST Impedance Divide Ratio
19700 */
19701#define DDRPHY_ZQ2PR0_ZPROG_HOST_ODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ZPROG_HOST_ODT_SHIFT)) & DDRPHY_ZQ2PR0_ZPROG_HOST_ODT_MASK)
19702#define DDRPHY_ZQ2PR0_ZPROG_DRAM_ODT_MASK (0xF000U)
19703#define DDRPHY_ZQ2PR0_ZPROG_DRAM_ODT_SHIFT (12U)
19704/*! ZPROG_DRAM_ODT - DRAM Impedance Divide Ratio
19705 */
19706#define DDRPHY_ZQ2PR0_ZPROG_DRAM_ODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ZPROG_DRAM_ODT_SHIFT)) & DDRPHY_ZQ2PR0_ZPROG_DRAM_ODT_MASK)
19707#define DDRPHY_ZQ2PR0_PU_DRV_ADJUST_MASK (0x70000U)
19708#define DDRPHY_ZQ2PR0_PU_DRV_ADJUST_SHIFT (16U)
19709/*! PU_DRV_ADJUST - Pullup drive strength adjustment
19710 */
19711#define DDRPHY_ZQ2PR0_PU_DRV_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_PU_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ2PR0_PU_DRV_ADJUST_MASK)
19712#define DDRPHY_ZQ2PR0_PD_DRV_ADJUST_MASK (0x380000U)
19713#define DDRPHY_ZQ2PR0_PD_DRV_ADJUST_SHIFT (19U)
19714/*! PD_DRV_ADJUST - Pulldown drive strength adjustment
19715 */
19716#define DDRPHY_ZQ2PR0_PD_DRV_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_PD_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ2PR0_PD_DRV_ADJUST_MASK)
19717#define DDRPHY_ZQ2PR0_ODT_ADJUST_MASK (0x1C00000U)
19718#define DDRPHY_ZQ2PR0_ODT_ADJUST_SHIFT (22U)
19719/*! ODT_ADJUST - Termination adjustment
19720 */
19721#define DDRPHY_ZQ2PR0_ODT_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ODT_ADJUST_SHIFT)) & DDRPHY_ZQ2PR0_ODT_ADJUST_MASK)
19722#define DDRPHY_ZQ2PR0_ZLE_MODE_MASK (0x6000000U)
19723#define DDRPHY_ZQ2PR0_ZLE_MODE_SHIFT (25U)
19724/*! ZLE_MODE - VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
19725 */
19726#define DDRPHY_ZQ2PR0_ZLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ZLE_MODE_SHIFT)) & DDRPHY_ZQ2PR0_ZLE_MODE_MASK)
19727#define DDRPHY_ZQ2PR0_ZSEGBYP_MASK (0x8000000U)
19728#define DDRPHY_ZQ2PR0_ZSEGBYP_SHIFT (27U)
19729/*! ZSEGBYP - Calibration segment bypass
19730 */
19731#define DDRPHY_ZQ2PR0_ZSEGBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_ZSEGBYP_SHIFT)) & DDRPHY_ZQ2PR0_ZSEGBYP_MASK)
19732#define DDRPHY_ZQ2PR0_PU_ODT_ZDEN_MASK (0x10000000U)
19733#define DDRPHY_ZQ2PR0_PU_ODT_ZDEN_SHIFT (28U)
19734/*! PU_ODT_ZDEN - Pull-up termination ZCTRL over-ride enable
19735 */
19736#define DDRPHY_ZQ2PR0_PU_ODT_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_PU_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ2PR0_PU_ODT_ZDEN_MASK)
19737#define DDRPHY_ZQ2PR0_PD_ODT_ZDEN_MASK (0x20000000U)
19738#define DDRPHY_ZQ2PR0_PD_ODT_ZDEN_SHIFT (29U)
19739/*! PD_ODT_ZDEN - Pull-down termination ZCTRL over-ride enable
19740 */
19741#define DDRPHY_ZQ2PR0_PD_ODT_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_PD_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ2PR0_PD_ODT_ZDEN_MASK)
19742#define DDRPHY_ZQ2PR0_PU_DRV_ZDEN_MASK (0x40000000U)
19743#define DDRPHY_ZQ2PR0_PU_DRV_ZDEN_SHIFT (30U)
19744/*! PU_DRV_ZDEN - Pull-up drive strength ZCTRL over-ride enable
19745 */
19746#define DDRPHY_ZQ2PR0_PU_DRV_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_PU_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ2PR0_PU_DRV_ZDEN_MASK)
19747#define DDRPHY_ZQ2PR0_PD_DRV_ZDEN_MASK (0x80000000U)
19748#define DDRPHY_ZQ2PR0_PD_DRV_ZDEN_SHIFT (31U)
19749/*! PD_DRV_ZDEN - Pull-down drive strength ZCTRL over-ride enable
19750 */
19751#define DDRPHY_ZQ2PR0_PD_DRV_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR0_PD_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ2PR0_PD_DRV_ZDEN_MASK)
19752/*! @} */
19753
19754/*! @name ZQ2PR1 - ZQ n Impedance Control Program Register 1 */
19755/*! @{ */
19756#define DDRPHY_ZQ2PR1_PD_REFSEL_MASK (0x7FU)
19757#define DDRPHY_ZQ2PR1_PD_REFSEL_SHIFT (0U)
19758/*! PD_REFSEL - Pull-down REFSEL for PZCTRL cell
19759 */
19760#define DDRPHY_ZQ2PR1_PD_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR1_PD_REFSEL_SHIFT)) & DDRPHY_ZQ2PR1_PD_REFSEL_MASK)
19761#define DDRPHY_ZQ2PR1_RESERVED_7_MASK (0x80U)
19762#define DDRPHY_ZQ2PR1_RESERVED_7_SHIFT (7U)
19763/*! RESERVED_7 - Reserved. Return zeros on reads.
19764 */
19765#define DDRPHY_ZQ2PR1_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR1_RESERVED_7_SHIFT)) & DDRPHY_ZQ2PR1_RESERVED_7_MASK)
19766#define DDRPHY_ZQ2PR1_PU_REFSEL_MASK (0x7F00U)
19767#define DDRPHY_ZQ2PR1_PU_REFSEL_SHIFT (8U)
19768/*! PU_REFSEL - Pull-up REFSEL for PZCTRL cell
19769 */
19770#define DDRPHY_ZQ2PR1_PU_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR1_PU_REFSEL_SHIFT)) & DDRPHY_ZQ2PR1_PU_REFSEL_MASK)
19771#define DDRPHY_ZQ2PR1_RESERVED_31_15_MASK (0xFFFF8000U)
19772#define DDRPHY_ZQ2PR1_RESERVED_31_15_SHIFT (15U)
19773/*! RESERVED_31_15 - Reserved. Return zeros on reads.
19774 */
19775#define DDRPHY_ZQ2PR1_RESERVED_31_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2PR1_RESERVED_31_15_SHIFT)) & DDRPHY_ZQ2PR1_RESERVED_31_15_MASK)
19776/*! @} */
19777
19778/*! @name ZQ2DR0 - ZQ n Impedance Control Data Register 0 */
19779/*! @{ */
19780#define DDRPHY_ZQ2DR0_ZDATA_PD_DRV_RESULT_MASK (0x3FFU)
19781#define DDRPHY_ZQ2DR0_ZDATA_PD_DRV_RESULT_SHIFT (0U)
19782/*! ZDATA_PD_DRV_RESULT - Pull-down drive strength calibration code result
19783 */
19784#define DDRPHY_ZQ2DR0_ZDATA_PD_DRV_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR0_ZDATA_PD_DRV_RESULT_SHIFT)) & DDRPHY_ZQ2DR0_ZDATA_PD_DRV_RESULT_MASK)
19785#define DDRPHY_ZQ2DR0_RESERVED_15_10_MASK (0xFC00U)
19786#define DDRPHY_ZQ2DR0_RESERVED_15_10_SHIFT (10U)
19787/*! RESERVED_15_10 - Reserved. Return zeros on reads.
19788 */
19789#define DDRPHY_ZQ2DR0_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ2DR0_RESERVED_15_10_MASK)
19790#define DDRPHY_ZQ2DR0_ZDATA_PU_DRV_RESULT_MASK (0x3FF0000U)
19791#define DDRPHY_ZQ2DR0_ZDATA_PU_DRV_RESULT_SHIFT (16U)
19792/*! ZDATA_PU_DRV_RESULT - Pull-up drive strength calibration code result
19793 */
19794#define DDRPHY_ZQ2DR0_ZDATA_PU_DRV_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR0_ZDATA_PU_DRV_RESULT_SHIFT)) & DDRPHY_ZQ2DR0_ZDATA_PU_DRV_RESULT_MASK)
19795#define DDRPHY_ZQ2DR0_RESERVED_31_26_MASK (0xFC000000U)
19796#define DDRPHY_ZQ2DR0_RESERVED_31_26_SHIFT (26U)
19797/*! RESERVED_31_26 - Reserved. Return zeros on reads.
19798 */
19799#define DDRPHY_ZQ2DR0_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ2DR0_RESERVED_31_26_MASK)
19800/*! @} */
19801
19802/*! @name ZQ2DR1 - ZQ n Impedance Control Data Register 1 */
19803/*! @{ */
19804#define DDRPHY_ZQ2DR1_ZDATA_PD_ODT_RESULT_MASK (0x3FFU)
19805#define DDRPHY_ZQ2DR1_ZDATA_PD_ODT_RESULT_SHIFT (0U)
19806/*! ZDATA_PD_ODT_RESULT - Pull-down termination calibration code result
19807 */
19808#define DDRPHY_ZQ2DR1_ZDATA_PD_ODT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR1_ZDATA_PD_ODT_RESULT_SHIFT)) & DDRPHY_ZQ2DR1_ZDATA_PD_ODT_RESULT_MASK)
19809#define DDRPHY_ZQ2DR1_RESERVED_15_10_MASK (0xFC00U)
19810#define DDRPHY_ZQ2DR1_RESERVED_15_10_SHIFT (10U)
19811/*! RESERVED_15_10 - Reserved. Return zeros on reads.
19812 */
19813#define DDRPHY_ZQ2DR1_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ2DR1_RESERVED_15_10_MASK)
19814#define DDRPHY_ZQ2DR1_ZDATA_PU_ODT_RESULT_MASK (0x3FF0000U)
19815#define DDRPHY_ZQ2DR1_ZDATA_PU_ODT_RESULT_SHIFT (16U)
19816/*! ZDATA_PU_ODT_RESULT - Pull-up termination calibration code result
19817 */
19818#define DDRPHY_ZQ2DR1_ZDATA_PU_ODT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR1_ZDATA_PU_ODT_RESULT_SHIFT)) & DDRPHY_ZQ2DR1_ZDATA_PU_ODT_RESULT_MASK)
19819#define DDRPHY_ZQ2DR1_RESERVED_31_26_MASK (0xFC000000U)
19820#define DDRPHY_ZQ2DR1_RESERVED_31_26_SHIFT (26U)
19821/*! RESERVED_31_26 - Reserved. Return zeros on reads.
19822 */
19823#define DDRPHY_ZQ2DR1_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2DR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ2DR1_RESERVED_31_26_MASK)
19824/*! @} */
19825
19826/*! @name ZQ2OR0 - ZQ n Impedance Control Override Data Register 0 */
19827/*! @{ */
19828#define DDRPHY_ZQ2OR0_ZDATA_PD_DRV_OVRD_MASK (0x3FFU)
19829#define DDRPHY_ZQ2OR0_ZDATA_PD_DRV_OVRD_SHIFT (0U)
19830/*! ZDATA_PD_DRV_OVRD - Override value for the pull-down output impedance
19831 */
19832#define DDRPHY_ZQ2OR0_ZDATA_PD_DRV_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR0_ZDATA_PD_DRV_OVRD_SHIFT)) & DDRPHY_ZQ2OR0_ZDATA_PD_DRV_OVRD_MASK)
19833#define DDRPHY_ZQ2OR0_RESERVED_15_10_MASK (0xFC00U)
19834#define DDRPHY_ZQ2OR0_RESERVED_15_10_SHIFT (10U)
19835/*! RESERVED_15_10 - Reserved. Return zeros on reads.
19836 */
19837#define DDRPHY_ZQ2OR0_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ2OR0_RESERVED_15_10_MASK)
19838#define DDRPHY_ZQ2OR0_ZDATA_PU_DRV_OVRD_MASK (0x3FF0000U)
19839#define DDRPHY_ZQ2OR0_ZDATA_PU_DRV_OVRD_SHIFT (16U)
19840/*! ZDATA_PU_DRV_OVRD - Override value for the pull-up output impedance
19841 */
19842#define DDRPHY_ZQ2OR0_ZDATA_PU_DRV_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR0_ZDATA_PU_DRV_OVRD_SHIFT)) & DDRPHY_ZQ2OR0_ZDATA_PU_DRV_OVRD_MASK)
19843#define DDRPHY_ZQ2OR0_RESERVED_31_26_MASK (0xFC000000U)
19844#define DDRPHY_ZQ2OR0_RESERVED_31_26_SHIFT (26U)
19845/*! RESERVED_31_26 - Reserved. Return zeros on reads.
19846 */
19847#define DDRPHY_ZQ2OR0_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ2OR0_RESERVED_31_26_MASK)
19848/*! @} */
19849
19850/*! @name ZQ2OR1 - ZQ n Impedance Control Override Data Register 1 */
19851/*! @{ */
19852#define DDRPHY_ZQ2OR1_ZDATA_PD_ODT_OVRD_MASK (0x3FFU)
19853#define DDRPHY_ZQ2OR1_ZDATA_PD_ODT_OVRD_SHIFT (0U)
19854/*! ZDATA_PD_ODT_OVRD - Override value for the pull-down termination
19855 */
19856#define DDRPHY_ZQ2OR1_ZDATA_PD_ODT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR1_ZDATA_PD_ODT_OVRD_SHIFT)) & DDRPHY_ZQ2OR1_ZDATA_PD_ODT_OVRD_MASK)
19857#define DDRPHY_ZQ2OR1_RESERVED_15_10_MASK (0xFC00U)
19858#define DDRPHY_ZQ2OR1_RESERVED_15_10_SHIFT (10U)
19859/*! RESERVED_15_10 - Reserved. Return zeros on reads.
19860 */
19861#define DDRPHY_ZQ2OR1_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ2OR1_RESERVED_15_10_MASK)
19862#define DDRPHY_ZQ2OR1_ZDATA_PU_ODT_OVRD_MASK (0x3FF0000U)
19863#define DDRPHY_ZQ2OR1_ZDATA_PU_ODT_OVRD_SHIFT (16U)
19864/*! ZDATA_PU_ODT_OVRD - Override value for the pull-up termination
19865 */
19866#define DDRPHY_ZQ2OR1_ZDATA_PU_ODT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR1_ZDATA_PU_ODT_OVRD_SHIFT)) & DDRPHY_ZQ2OR1_ZDATA_PU_ODT_OVRD_MASK)
19867#define DDRPHY_ZQ2OR1_RESERVED_31_26_MASK (0xFC000000U)
19868#define DDRPHY_ZQ2OR1_RESERVED_31_26_SHIFT (26U)
19869/*! RESERVED_31_26 - Reserved. Return zeros on reads.
19870 */
19871#define DDRPHY_ZQ2OR1_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2OR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ2OR1_RESERVED_31_26_MASK)
19872/*! @} */
19873
19874/*! @name ZQ2SR - ZQ n Impedance Control Status Register */
19875/*! @{ */
19876#define DDRPHY_ZQ2SR_ZPD_MASK (0x3U)
19877#define DDRPHY_ZQ2SR_ZPD_SHIFT (0U)
19878/*! ZPD - Output impedance pull-down calibration status
19879 */
19880#define DDRPHY_ZQ2SR_ZPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_ZPD_SHIFT)) & DDRPHY_ZQ2SR_ZPD_MASK)
19881#define DDRPHY_ZQ2SR_ZPU_MASK (0xCU)
19882#define DDRPHY_ZQ2SR_ZPU_SHIFT (2U)
19883/*! ZPU - Output impedance pull-up calibration status
19884 */
19885#define DDRPHY_ZQ2SR_ZPU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_ZPU_SHIFT)) & DDRPHY_ZQ2SR_ZPU_MASK)
19886#define DDRPHY_ZQ2SR_OPD_MASK (0x30U)
19887#define DDRPHY_ZQ2SR_OPD_SHIFT (4U)
19888/*! OPD - On-die termination (ODT) pull-down calibration status
19889 */
19890#define DDRPHY_ZQ2SR_OPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_OPD_SHIFT)) & DDRPHY_ZQ2SR_OPD_MASK)
19891#define DDRPHY_ZQ2SR_OPU_MASK (0xC0U)
19892#define DDRPHY_ZQ2SR_OPU_SHIFT (6U)
19893/*! OPU - On-die termination (ODT) pull-up calibration status
19894 */
19895#define DDRPHY_ZQ2SR_OPU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_OPU_SHIFT)) & DDRPHY_ZQ2SR_OPU_MASK)
19896#define DDRPHY_ZQ2SR_ZERR_MASK (0x100U)
19897#define DDRPHY_ZQ2SR_ZERR_SHIFT (8U)
19898/*! ZERR - Impedance Calibration Error
19899 */
19900#define DDRPHY_ZQ2SR_ZERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_ZERR_SHIFT)) & DDRPHY_ZQ2SR_ZERR_MASK)
19901#define DDRPHY_ZQ2SR_ZDONE_MASK (0x200U)
19902#define DDRPHY_ZQ2SR_ZDONE_SHIFT (9U)
19903/*! ZDONE - Impedance Calibration Done
19904 */
19905#define DDRPHY_ZQ2SR_ZDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_ZDONE_SHIFT)) & DDRPHY_ZQ2SR_ZDONE_MASK)
19906#define DDRPHY_ZQ2SR_PU_DRV_SAT_MASK (0x400U)
19907#define DDRPHY_ZQ2SR_PU_DRV_SAT_SHIFT (10U)
19908/*! PU_DRV_SAT - Pullup drive strength code saturated due to drive strength adjustment setting in ZQnPR register
19909 */
19910#define DDRPHY_ZQ2SR_PU_DRV_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_PU_DRV_SAT_SHIFT)) & DDRPHY_ZQ2SR_PU_DRV_SAT_MASK)
19911#define DDRPHY_ZQ2SR_PD_DRV_SAT_MASK (0x800U)
19912#define DDRPHY_ZQ2SR_PD_DRV_SAT_SHIFT (11U)
19913/*! PD_DRV_SAT - Pulldown drive strength code saturated due to drive strength adjustment setting in ZQnPR register
19914 */
19915#define DDRPHY_ZQ2SR_PD_DRV_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_PD_DRV_SAT_SHIFT)) & DDRPHY_ZQ2SR_PD_DRV_SAT_MASK)
19916#define DDRPHY_ZQ2SR_PU_ODT_SAT_MASK (0x1000U)
19917#define DDRPHY_ZQ2SR_PU_ODT_SAT_SHIFT (12U)
19918/*! PU_ODT_SAT - Pullup drive strength code saturated due to termination strength adjustment setting in ZQnPR register
19919 */
19920#define DDRPHY_ZQ2SR_PU_ODT_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_PU_ODT_SAT_SHIFT)) & DDRPHY_ZQ2SR_PU_ODT_SAT_MASK)
19921#define DDRPHY_ZQ2SR_PD_ODT_SAT_MASK (0x2000U)
19922#define DDRPHY_ZQ2SR_PD_ODT_SAT_SHIFT (13U)
19923/*! PD_ODT_SAT - Pulldown drive strength code saturated due to termination strength adjustment setting in ZQnPR register
19924 */
19925#define DDRPHY_ZQ2SR_PD_ODT_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_PD_ODT_SAT_SHIFT)) & DDRPHY_ZQ2SR_PD_ODT_SAT_MASK)
19926#define DDRPHY_ZQ2SR_RESERVED_31_14_MASK (0xFFFFC000U)
19927#define DDRPHY_ZQ2SR_RESERVED_31_14_SHIFT (14U)
19928/*! RESERVED_31_14 - Reserved. Return zeros on reads.
19929 */
19930#define DDRPHY_ZQ2SR_RESERVED_31_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ2SR_RESERVED_31_14_SHIFT)) & DDRPHY_ZQ2SR_RESERVED_31_14_MASK)
19931/*! @} */
19932
19933/*! @name ZQ3PR0 - ZQ n Impedance Control Program Register 0 */
19934/*! @{ */
19935#define DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PU_MASK (0xFU)
19936#define DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PU_SHIFT (0U)
19937/*! ZPROG_ASYM_DRV_PU - Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
19938 */
19939#define DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PU_SHIFT)) & DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PU_MASK)
19940#define DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PD_MASK (0xF0U)
19941#define DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PD_SHIFT (4U)
19942/*! ZPROG_ASYM_DRV_PD - Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
19943 */
19944#define DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PD_SHIFT)) & DDRPHY_ZQ3PR0_ZPROG_ASYM_DRV_PD_MASK)
19945#define DDRPHY_ZQ3PR0_ZPROG_HOST_ODT_MASK (0xF00U)
19946#define DDRPHY_ZQ3PR0_ZPROG_HOST_ODT_SHIFT (8U)
19947/*! ZPROG_HOST_ODT - HOST Impedance Divide Ratio
19948 */
19949#define DDRPHY_ZQ3PR0_ZPROG_HOST_ODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ZPROG_HOST_ODT_SHIFT)) & DDRPHY_ZQ3PR0_ZPROG_HOST_ODT_MASK)
19950#define DDRPHY_ZQ3PR0_ZPROG_DRAM_ODT_MASK (0xF000U)
19951#define DDRPHY_ZQ3PR0_ZPROG_DRAM_ODT_SHIFT (12U)
19952/*! ZPROG_DRAM_ODT - DRAM Impedance Divide Ratio
19953 */
19954#define DDRPHY_ZQ3PR0_ZPROG_DRAM_ODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ZPROG_DRAM_ODT_SHIFT)) & DDRPHY_ZQ3PR0_ZPROG_DRAM_ODT_MASK)
19955#define DDRPHY_ZQ3PR0_PU_DRV_ADJUST_MASK (0x70000U)
19956#define DDRPHY_ZQ3PR0_PU_DRV_ADJUST_SHIFT (16U)
19957/*! PU_DRV_ADJUST - Pullup drive strength adjustment
19958 */
19959#define DDRPHY_ZQ3PR0_PU_DRV_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_PU_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ3PR0_PU_DRV_ADJUST_MASK)
19960#define DDRPHY_ZQ3PR0_PD_DRV_ADJUST_MASK (0x380000U)
19961#define DDRPHY_ZQ3PR0_PD_DRV_ADJUST_SHIFT (19U)
19962/*! PD_DRV_ADJUST - Pulldown drive strength adjustment
19963 */
19964#define DDRPHY_ZQ3PR0_PD_DRV_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_PD_DRV_ADJUST_SHIFT)) & DDRPHY_ZQ3PR0_PD_DRV_ADJUST_MASK)
19965#define DDRPHY_ZQ3PR0_ODT_ADJUST_MASK (0x1C00000U)
19966#define DDRPHY_ZQ3PR0_ODT_ADJUST_SHIFT (22U)
19967/*! ODT_ADJUST - Termination adjustment
19968 */
19969#define DDRPHY_ZQ3PR0_ODT_ADJUST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ODT_ADJUST_SHIFT)) & DDRPHY_ZQ3PR0_ODT_ADJUST_MASK)
19970#define DDRPHY_ZQ3PR0_ZLE_MODE_MASK (0x6000000U)
19971#define DDRPHY_ZQ3PR0_ZLE_MODE_SHIFT (25U)
19972/*! ZLE_MODE - VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
19973 */
19974#define DDRPHY_ZQ3PR0_ZLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ZLE_MODE_SHIFT)) & DDRPHY_ZQ3PR0_ZLE_MODE_MASK)
19975#define DDRPHY_ZQ3PR0_ZSEGBYP_MASK (0x8000000U)
19976#define DDRPHY_ZQ3PR0_ZSEGBYP_SHIFT (27U)
19977/*! ZSEGBYP - Calibration segment bypass
19978 */
19979#define DDRPHY_ZQ3PR0_ZSEGBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_ZSEGBYP_SHIFT)) & DDRPHY_ZQ3PR0_ZSEGBYP_MASK)
19980#define DDRPHY_ZQ3PR0_PU_ODT_ZDEN_MASK (0x10000000U)
19981#define DDRPHY_ZQ3PR0_PU_ODT_ZDEN_SHIFT (28U)
19982/*! PU_ODT_ZDEN - Pull-up termination ZCTRL over-ride enable
19983 */
19984#define DDRPHY_ZQ3PR0_PU_ODT_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_PU_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ3PR0_PU_ODT_ZDEN_MASK)
19985#define DDRPHY_ZQ3PR0_PD_ODT_ZDEN_MASK (0x20000000U)
19986#define DDRPHY_ZQ3PR0_PD_ODT_ZDEN_SHIFT (29U)
19987/*! PD_ODT_ZDEN - Pull-down termination ZCTRL over-ride enable
19988 */
19989#define DDRPHY_ZQ3PR0_PD_ODT_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_PD_ODT_ZDEN_SHIFT)) & DDRPHY_ZQ3PR0_PD_ODT_ZDEN_MASK)
19990#define DDRPHY_ZQ3PR0_PU_DRV_ZDEN_MASK (0x40000000U)
19991#define DDRPHY_ZQ3PR0_PU_DRV_ZDEN_SHIFT (30U)
19992/*! PU_DRV_ZDEN - Pull-up drive strength ZCTRL over-ride enable
19993 */
19994#define DDRPHY_ZQ3PR0_PU_DRV_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_PU_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ3PR0_PU_DRV_ZDEN_MASK)
19995#define DDRPHY_ZQ3PR0_PD_DRV_ZDEN_MASK (0x80000000U)
19996#define DDRPHY_ZQ3PR0_PD_DRV_ZDEN_SHIFT (31U)
19997/*! PD_DRV_ZDEN - Pull-down drive strength ZCTRL over-ride enable
19998 */
19999#define DDRPHY_ZQ3PR0_PD_DRV_ZDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR0_PD_DRV_ZDEN_SHIFT)) & DDRPHY_ZQ3PR0_PD_DRV_ZDEN_MASK)
20000/*! @} */
20001
20002/*! @name ZQ3PR1 - ZQ n Impedance Control Program Register 1 */
20003/*! @{ */
20004#define DDRPHY_ZQ3PR1_PD_REFSEL_MASK (0x7FU)
20005#define DDRPHY_ZQ3PR1_PD_REFSEL_SHIFT (0U)
20006/*! PD_REFSEL - Pull-down REFSEL for PZCTRL cell
20007 */
20008#define DDRPHY_ZQ3PR1_PD_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR1_PD_REFSEL_SHIFT)) & DDRPHY_ZQ3PR1_PD_REFSEL_MASK)
20009#define DDRPHY_ZQ3PR1_RESERVED_7_MASK (0x80U)
20010#define DDRPHY_ZQ3PR1_RESERVED_7_SHIFT (7U)
20011/*! RESERVED_7 - Reserved. Return zeros on reads.
20012 */
20013#define DDRPHY_ZQ3PR1_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR1_RESERVED_7_SHIFT)) & DDRPHY_ZQ3PR1_RESERVED_7_MASK)
20014#define DDRPHY_ZQ3PR1_PU_REFSEL_MASK (0x7F00U)
20015#define DDRPHY_ZQ3PR1_PU_REFSEL_SHIFT (8U)
20016/*! PU_REFSEL - Pull-up REFSEL for PZCTRL cell
20017 */
20018#define DDRPHY_ZQ3PR1_PU_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR1_PU_REFSEL_SHIFT)) & DDRPHY_ZQ3PR1_PU_REFSEL_MASK)
20019#define DDRPHY_ZQ3PR1_RESERVED_31_15_MASK (0xFFFF8000U)
20020#define DDRPHY_ZQ3PR1_RESERVED_31_15_SHIFT (15U)
20021/*! RESERVED_31_15 - Reserved. Return zeros on reads.
20022 */
20023#define DDRPHY_ZQ3PR1_RESERVED_31_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3PR1_RESERVED_31_15_SHIFT)) & DDRPHY_ZQ3PR1_RESERVED_31_15_MASK)
20024/*! @} */
20025
20026/*! @name ZQ3DR0 - ZQ n Impedance Control Data Register 0 */
20027/*! @{ */
20028#define DDRPHY_ZQ3DR0_ZDATA_PD_DRV_RESULT_MASK (0x3FFU)
20029#define DDRPHY_ZQ3DR0_ZDATA_PD_DRV_RESULT_SHIFT (0U)
20030/*! ZDATA_PD_DRV_RESULT - Pull-down drive strength calibration code result
20031 */
20032#define DDRPHY_ZQ3DR0_ZDATA_PD_DRV_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR0_ZDATA_PD_DRV_RESULT_SHIFT)) & DDRPHY_ZQ3DR0_ZDATA_PD_DRV_RESULT_MASK)
20033#define DDRPHY_ZQ3DR0_RESERVED_15_10_MASK (0xFC00U)
20034#define DDRPHY_ZQ3DR0_RESERVED_15_10_SHIFT (10U)
20035/*! RESERVED_15_10 - Reserved. Return zeros on reads.
20036 */
20037#define DDRPHY_ZQ3DR0_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ3DR0_RESERVED_15_10_MASK)
20038#define DDRPHY_ZQ3DR0_ZDATA_PU_DRV_RESULT_MASK (0x3FF0000U)
20039#define DDRPHY_ZQ3DR0_ZDATA_PU_DRV_RESULT_SHIFT (16U)
20040/*! ZDATA_PU_DRV_RESULT - Pull-up drive strength calibration code result
20041 */
20042#define DDRPHY_ZQ3DR0_ZDATA_PU_DRV_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR0_ZDATA_PU_DRV_RESULT_SHIFT)) & DDRPHY_ZQ3DR0_ZDATA_PU_DRV_RESULT_MASK)
20043#define DDRPHY_ZQ3DR0_RESERVED_31_26_MASK (0xFC000000U)
20044#define DDRPHY_ZQ3DR0_RESERVED_31_26_SHIFT (26U)
20045/*! RESERVED_31_26 - Reserved. Return zeros on reads.
20046 */
20047#define DDRPHY_ZQ3DR0_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ3DR0_RESERVED_31_26_MASK)
20048/*! @} */
20049
20050/*! @name ZQ3DR1 - ZQ n Impedance Control Data Register 1 */
20051/*! @{ */
20052#define DDRPHY_ZQ3DR1_ZDATA_PD_ODT_RESULT_MASK (0x3FFU)
20053#define DDRPHY_ZQ3DR1_ZDATA_PD_ODT_RESULT_SHIFT (0U)
20054/*! ZDATA_PD_ODT_RESULT - Pull-down termination calibration code result
20055 */
20056#define DDRPHY_ZQ3DR1_ZDATA_PD_ODT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR1_ZDATA_PD_ODT_RESULT_SHIFT)) & DDRPHY_ZQ3DR1_ZDATA_PD_ODT_RESULT_MASK)
20057#define DDRPHY_ZQ3DR1_RESERVED_15_10_MASK (0xFC00U)
20058#define DDRPHY_ZQ3DR1_RESERVED_15_10_SHIFT (10U)
20059/*! RESERVED_15_10 - Reserved. Return zeros on reads.
20060 */
20061#define DDRPHY_ZQ3DR1_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ3DR1_RESERVED_15_10_MASK)
20062#define DDRPHY_ZQ3DR1_ZDATA_PU_ODT_RESULT_MASK (0x3FF0000U)
20063#define DDRPHY_ZQ3DR1_ZDATA_PU_ODT_RESULT_SHIFT (16U)
20064/*! ZDATA_PU_ODT_RESULT - Pull-up termination calibration code result
20065 */
20066#define DDRPHY_ZQ3DR1_ZDATA_PU_ODT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR1_ZDATA_PU_ODT_RESULT_SHIFT)) & DDRPHY_ZQ3DR1_ZDATA_PU_ODT_RESULT_MASK)
20067#define DDRPHY_ZQ3DR1_RESERVED_31_26_MASK (0xFC000000U)
20068#define DDRPHY_ZQ3DR1_RESERVED_31_26_SHIFT (26U)
20069/*! RESERVED_31_26 - Reserved. Return zeros on reads.
20070 */
20071#define DDRPHY_ZQ3DR1_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3DR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ3DR1_RESERVED_31_26_MASK)
20072/*! @} */
20073
20074/*! @name ZQ3OR0 - ZQ n Impedance Control Override Data Register 0 */
20075/*! @{ */
20076#define DDRPHY_ZQ3OR0_ZDATA_PD_DRV_OVRD_MASK (0x3FFU)
20077#define DDRPHY_ZQ3OR0_ZDATA_PD_DRV_OVRD_SHIFT (0U)
20078/*! ZDATA_PD_DRV_OVRD - Override value for the pull-down output impedance
20079 */
20080#define DDRPHY_ZQ3OR0_ZDATA_PD_DRV_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR0_ZDATA_PD_DRV_OVRD_SHIFT)) & DDRPHY_ZQ3OR0_ZDATA_PD_DRV_OVRD_MASK)
20081#define DDRPHY_ZQ3OR0_RESERVED_15_10_MASK (0xFC00U)
20082#define DDRPHY_ZQ3OR0_RESERVED_15_10_SHIFT (10U)
20083/*! RESERVED_15_10 - Reserved. Return zeros on reads.
20084 */
20085#define DDRPHY_ZQ3OR0_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR0_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ3OR0_RESERVED_15_10_MASK)
20086#define DDRPHY_ZQ3OR0_ZDATA_PU_DRV_OVRD_MASK (0x3FF0000U)
20087#define DDRPHY_ZQ3OR0_ZDATA_PU_DRV_OVRD_SHIFT (16U)
20088/*! ZDATA_PU_DRV_OVRD - Override value for the pull-up output impedance
20089 */
20090#define DDRPHY_ZQ3OR0_ZDATA_PU_DRV_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR0_ZDATA_PU_DRV_OVRD_SHIFT)) & DDRPHY_ZQ3OR0_ZDATA_PU_DRV_OVRD_MASK)
20091#define DDRPHY_ZQ3OR0_RESERVED_31_26_MASK (0xFC000000U)
20092#define DDRPHY_ZQ3OR0_RESERVED_31_26_SHIFT (26U)
20093/*! RESERVED_31_26 - Reserved. Return zeros on reads.
20094 */
20095#define DDRPHY_ZQ3OR0_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR0_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ3OR0_RESERVED_31_26_MASK)
20096/*! @} */
20097
20098/*! @name ZQ3OR1 - ZQ n Impedance Control Override Data Register 1 */
20099/*! @{ */
20100#define DDRPHY_ZQ3OR1_ZDATA_PD_ODT_OVRD_MASK (0x3FFU)
20101#define DDRPHY_ZQ3OR1_ZDATA_PD_ODT_OVRD_SHIFT (0U)
20102/*! ZDATA_PD_ODT_OVRD - Override value for the pull-down termination
20103 */
20104#define DDRPHY_ZQ3OR1_ZDATA_PD_ODT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR1_ZDATA_PD_ODT_OVRD_SHIFT)) & DDRPHY_ZQ3OR1_ZDATA_PD_ODT_OVRD_MASK)
20105#define DDRPHY_ZQ3OR1_RESERVED_15_10_MASK (0xFC00U)
20106#define DDRPHY_ZQ3OR1_RESERVED_15_10_SHIFT (10U)
20107/*! RESERVED_15_10 - Reserved. Return zeros on reads.
20108 */
20109#define DDRPHY_ZQ3OR1_RESERVED_15_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR1_RESERVED_15_10_SHIFT)) & DDRPHY_ZQ3OR1_RESERVED_15_10_MASK)
20110#define DDRPHY_ZQ3OR1_ZDATA_PU_ODT_OVRD_MASK (0x3FF0000U)
20111#define DDRPHY_ZQ3OR1_ZDATA_PU_ODT_OVRD_SHIFT (16U)
20112/*! ZDATA_PU_ODT_OVRD - Override value for the pull-up termination
20113 */
20114#define DDRPHY_ZQ3OR1_ZDATA_PU_ODT_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR1_ZDATA_PU_ODT_OVRD_SHIFT)) & DDRPHY_ZQ3OR1_ZDATA_PU_ODT_OVRD_MASK)
20115#define DDRPHY_ZQ3OR1_RESERVED_31_26_MASK (0xFC000000U)
20116#define DDRPHY_ZQ3OR1_RESERVED_31_26_SHIFT (26U)
20117/*! RESERVED_31_26 - Reserved. Return zeros on reads.
20118 */
20119#define DDRPHY_ZQ3OR1_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3OR1_RESERVED_31_26_SHIFT)) & DDRPHY_ZQ3OR1_RESERVED_31_26_MASK)
20120/*! @} */
20121
20122/*! @name ZQ3SR - ZQ n Impedance Control Status Register */
20123/*! @{ */
20124#define DDRPHY_ZQ3SR_ZPD_MASK (0x3U)
20125#define DDRPHY_ZQ3SR_ZPD_SHIFT (0U)
20126/*! ZPD - Output impedance pull-down calibration status
20127 */
20128#define DDRPHY_ZQ3SR_ZPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_ZPD_SHIFT)) & DDRPHY_ZQ3SR_ZPD_MASK)
20129#define DDRPHY_ZQ3SR_ZPU_MASK (0xCU)
20130#define DDRPHY_ZQ3SR_ZPU_SHIFT (2U)
20131/*! ZPU - Output impedance pull-up calibration status
20132 */
20133#define DDRPHY_ZQ3SR_ZPU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_ZPU_SHIFT)) & DDRPHY_ZQ3SR_ZPU_MASK)
20134#define DDRPHY_ZQ3SR_OPD_MASK (0x30U)
20135#define DDRPHY_ZQ3SR_OPD_SHIFT (4U)
20136/*! OPD - On-die termination (ODT) pull-down calibration status
20137 */
20138#define DDRPHY_ZQ3SR_OPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_OPD_SHIFT)) & DDRPHY_ZQ3SR_OPD_MASK)
20139#define DDRPHY_ZQ3SR_OPU_MASK (0xC0U)
20140#define DDRPHY_ZQ3SR_OPU_SHIFT (6U)
20141/*! OPU - On-die termination (ODT) pull-up calibration status
20142 */
20143#define DDRPHY_ZQ3SR_OPU(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_OPU_SHIFT)) & DDRPHY_ZQ3SR_OPU_MASK)
20144#define DDRPHY_ZQ3SR_ZERR_MASK (0x100U)
20145#define DDRPHY_ZQ3SR_ZERR_SHIFT (8U)
20146/*! ZERR - Impedance Calibration Error
20147 */
20148#define DDRPHY_ZQ3SR_ZERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_ZERR_SHIFT)) & DDRPHY_ZQ3SR_ZERR_MASK)
20149#define DDRPHY_ZQ3SR_ZDONE_MASK (0x200U)
20150#define DDRPHY_ZQ3SR_ZDONE_SHIFT (9U)
20151/*! ZDONE - Impedance Calibration Done
20152 */
20153#define DDRPHY_ZQ3SR_ZDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_ZDONE_SHIFT)) & DDRPHY_ZQ3SR_ZDONE_MASK)
20154#define DDRPHY_ZQ3SR_PU_DRV_SAT_MASK (0x400U)
20155#define DDRPHY_ZQ3SR_PU_DRV_SAT_SHIFT (10U)
20156/*! PU_DRV_SAT - Pullup drive strength code saturated due to drive strength adjustment setting in ZQnPR register
20157 */
20158#define DDRPHY_ZQ3SR_PU_DRV_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_PU_DRV_SAT_SHIFT)) & DDRPHY_ZQ3SR_PU_DRV_SAT_MASK)
20159#define DDRPHY_ZQ3SR_PD_DRV_SAT_MASK (0x800U)
20160#define DDRPHY_ZQ3SR_PD_DRV_SAT_SHIFT (11U)
20161/*! PD_DRV_SAT - Pulldown drive strength code saturated due to drive strength adjustment setting in ZQnPR register
20162 */
20163#define DDRPHY_ZQ3SR_PD_DRV_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_PD_DRV_SAT_SHIFT)) & DDRPHY_ZQ3SR_PD_DRV_SAT_MASK)
20164#define DDRPHY_ZQ3SR_PU_ODT_SAT_MASK (0x1000U)
20165#define DDRPHY_ZQ3SR_PU_ODT_SAT_SHIFT (12U)
20166/*! PU_ODT_SAT - Pullup drive strength code saturated due to termination strength adjustment setting in ZQnPR register
20167 */
20168#define DDRPHY_ZQ3SR_PU_ODT_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_PU_ODT_SAT_SHIFT)) & DDRPHY_ZQ3SR_PU_ODT_SAT_MASK)
20169#define DDRPHY_ZQ3SR_PD_ODT_SAT_MASK (0x2000U)
20170#define DDRPHY_ZQ3SR_PD_ODT_SAT_SHIFT (13U)
20171/*! PD_ODT_SAT - Pulldown drive strength code saturated due to termination strength adjustment setting in ZQnPR register
20172 */
20173#define DDRPHY_ZQ3SR_PD_ODT_SAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_PD_ODT_SAT_SHIFT)) & DDRPHY_ZQ3SR_PD_ODT_SAT_MASK)
20174#define DDRPHY_ZQ3SR_RESERVED_31_14_MASK (0xFFFFC000U)
20175#define DDRPHY_ZQ3SR_RESERVED_31_14_SHIFT (14U)
20176/*! RESERVED_31_14 - Reserved. Return zeros on reads.
20177 */
20178#define DDRPHY_ZQ3SR_RESERVED_31_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_ZQ3SR_RESERVED_31_14_SHIFT)) & DDRPHY_ZQ3SR_RESERVED_31_14_MASK)
20179/*! @} */
20180
20181/*! @name DX0GCR0 - DATX8 n General Configuration Register 0 */
20182/*! @{ */
20183#define DDRPHY_DX0GCR0_RESERVED_1_0_MASK (0x3U)
20184#define DDRPHY_DX0GCR0_RESERVED_1_0_SHIFT (0U)
20185/*! RESERVED_1_0 - Reserved. Return zeroes on reads.
20186 */
20187#define DDRPHY_DX0GCR0_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX0GCR0_RESERVED_1_0_MASK)
20188#define DDRPHY_DX0GCR0_DQSGOE_MASK (0x4U)
20189#define DDRPHY_DX0GCR0_DQSGOE_SHIFT (2U)
20190/*! DQSGOE - DQSG Output Enable
20191 */
20192#define DDRPHY_DX0GCR0_DQSGOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSGOE_SHIFT)) & DDRPHY_DX0GCR0_DQSGOE_MASK)
20193#define DDRPHY_DX0GCR0_DQSGODT_MASK (0x8U)
20194#define DDRPHY_DX0GCR0_DQSGODT_SHIFT (3U)
20195/*! DQSGODT - DQSG On-Die Termination
20196 */
20197#define DDRPHY_DX0GCR0_DQSGODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSGODT_SHIFT)) & DDRPHY_DX0GCR0_DQSGODT_MASK)
20198#define DDRPHY_DX0GCR0_RESERVED_4_MASK (0x10U)
20199#define DDRPHY_DX0GCR0_RESERVED_4_SHIFT (4U)
20200/*! RESERVED_4 - Reserved. Return zeroes on reads.
20201 */
20202#define DDRPHY_DX0GCR0_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX0GCR0_RESERVED_4_MASK)
20203#define DDRPHY_DX0GCR0_DQSGPDR_MASK (0x20U)
20204#define DDRPHY_DX0GCR0_DQSGPDR_SHIFT (5U)
20205/*! DQSGPDR - DQSG Power Down Receiver
20206 */
20207#define DDRPHY_DX0GCR0_DQSGPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX0GCR0_DQSGPDR_MASK)
20208#define DDRPHY_DX0GCR0_DQSRPD_MASK (0x40U)
20209#define DDRPHY_DX0GCR0_DQSRPD_SHIFT (6U)
20210/*! DQSRPD - DQSR Power Down
20211 */
20212#define DDRPHY_DX0GCR0_DQSRPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSRPD_SHIFT)) & DDRPHY_DX0GCR0_DQSRPD_MASK)
20213#define DDRPHY_DX0GCR0_CPDRSHFT_MASK (0x180U)
20214#define DDRPHY_DX0GCR0_CPDRSHFT_SHIFT (7U)
20215/*! CPDRSHFT - Configurable PDR Phase Shift
20216 */
20217#define DDRPHY_DX0GCR0_CPDRSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX0GCR0_CPDRSHFT_MASK)
20218#define DDRPHY_DX0GCR0_RTTOH_MASK (0x600U)
20219#define DDRPHY_DX0GCR0_RTTOH_SHIFT (9U)
20220/*! RTTOH - RTT Output Hold
20221 */
20222#define DDRPHY_DX0GCR0_RTTOH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_RTTOH_SHIFT)) & DDRPHY_DX0GCR0_RTTOH_MASK)
20223#define DDRPHY_DX0GCR0_RTTOAL_MASK (0x800U)
20224#define DDRPHY_DX0GCR0_RTTOAL_SHIFT (11U)
20225/*! RTTOAL - RTT On Additive Latency
20226 */
20227#define DDRPHY_DX0GCR0_RTTOAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_RTTOAL_SHIFT)) & DDRPHY_DX0GCR0_RTTOAL_MASK)
20228#define DDRPHY_DX0GCR0_DQSSEPDR_MASK (0x1000U)
20229#define DDRPHY_DX0GCR0_DQSSEPDR_SHIFT (12U)
20230/*! DQSSEPDR - DQSSE Power Down Receiver
20231 */
20232#define DDRPHY_DX0GCR0_DQSSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX0GCR0_DQSSEPDR_MASK)
20233#define DDRPHY_DX0GCR0_DQSNSEPDR_MASK (0x2000U)
20234#define DDRPHY_DX0GCR0_DQSNSEPDR_SHIFT (13U)
20235/*! DQSNSEPDR - DQSNSE Power Down Receiver
20236 */
20237#define DDRPHY_DX0GCR0_DQSNSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX0GCR0_DQSNSEPDR_MASK)
20238#define DDRPHY_DX0GCR0_RESERVED_19_14_MASK (0xFC000U)
20239#define DDRPHY_DX0GCR0_RESERVED_19_14_SHIFT (14U)
20240/*! RESERVED_19_14 - Reserved. Return zeroes on reads.
20241 */
20242#define DDRPHY_DX0GCR0_RESERVED_19_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX0GCR0_RESERVED_19_14_MASK)
20243#define DDRPHY_DX0GCR0_RDDLY_MASK (0xF00000U)
20244#define DDRPHY_DX0GCR0_RDDLY_SHIFT (20U)
20245/*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
20246 */
20247#define DDRPHY_DX0GCR0_RDDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_RDDLY_SHIFT)) & DDRPHY_DX0GCR0_RDDLY_MASK)
20248#define DDRPHY_DX0GCR0_DQSDCC_MASK (0xF000000U)
20249#define DDRPHY_DX0GCR0_DQSDCC_SHIFT (24U)
20250/*! DQSDCC - DQS Duty Cycle Correction
20251 */
20252#define DDRPHY_DX0GCR0_DQSDCC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_DQSDCC_SHIFT)) & DDRPHY_DX0GCR0_DQSDCC_MASK)
20253#define DDRPHY_DX0GCR0_CODTSHFT_MASK (0x30000000U)
20254#define DDRPHY_DX0GCR0_CODTSHFT_SHIFT (28U)
20255/*! CODTSHFT - Configurable ODT(TE) Phase Shift
20256 */
20257#define DDRPHY_DX0GCR0_CODTSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX0GCR0_CODTSHFT_MASK)
20258#define DDRPHY_DX0GCR0_MDLEN_MASK (0x40000000U)
20259#define DDRPHY_DX0GCR0_MDLEN_SHIFT (30U)
20260/*! MDLEN - Master Delay Line Enable
20261 */
20262#define DDRPHY_DX0GCR0_MDLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_MDLEN_SHIFT)) & DDRPHY_DX0GCR0_MDLEN_MASK)
20263#define DDRPHY_DX0GCR0_CALBYP_MASK (0x80000000U)
20264#define DDRPHY_DX0GCR0_CALBYP_SHIFT (31U)
20265/*! CALBYP - Calibration Bypass
20266 */
20267#define DDRPHY_DX0GCR0_CALBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR0_CALBYP_SHIFT)) & DDRPHY_DX0GCR0_CALBYP_MASK)
20268/*! @} */
20269
20270/*! @name DX0GCR1 - DATX8 n General Configuration Register 1 */
20271/*! @{ */
20272#define DDRPHY_DX0GCR1_DQEN_MASK (0xFFU)
20273#define DDRPHY_DX0GCR1_DQEN_SHIFT (0U)
20274/*! DQEN - Enables DQ corresponding to each bit in a byte
20275 */
20276#define DDRPHY_DX0GCR1_DQEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_DQEN_SHIFT)) & DDRPHY_DX0GCR1_DQEN_MASK)
20277#define DDRPHY_DX0GCR1_DMEN_MASK (0x100U)
20278#define DDRPHY_DX0GCR1_DMEN_SHIFT (8U)
20279/*! DMEN - Enables DM pin in a byte lane
20280 */
20281#define DDRPHY_DX0GCR1_DMEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_DMEN_SHIFT)) & DDRPHY_DX0GCR1_DMEN_MASK)
20282#define DDRPHY_DX0GCR1_DSEN_MASK (0x200U)
20283#define DDRPHY_DX0GCR1_DSEN_SHIFT (9U)
20284/*! DSEN - Enables Write Data strobe in a byte lane
20285 */
20286#define DDRPHY_DX0GCR1_DSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_DSEN_SHIFT)) & DDRPHY_DX0GCR1_DSEN_MASK)
20287#define DDRPHY_DX0GCR1_TEEN_MASK (0x400U)
20288#define DDRPHY_DX0GCR1_TEEN_SHIFT (10U)
20289/*! TEEN - Enables ODT/TE in a byte lane
20290 */
20291#define DDRPHY_DX0GCR1_TEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_TEEN_SHIFT)) & DDRPHY_DX0GCR1_TEEN_MASK)
20292#define DDRPHY_DX0GCR1_PDREN_MASK (0x800U)
20293#define DDRPHY_DX0GCR1_PDREN_SHIFT (11U)
20294/*! PDREN - Enables PDR in a byte lane
20295 */
20296#define DDRPHY_DX0GCR1_PDREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_PDREN_SHIFT)) & DDRPHY_DX0GCR1_PDREN_MASK)
20297#define DDRPHY_DX0GCR1_OEEN_MASK (0x1000U)
20298#define DDRPHY_DX0GCR1_OEEN_SHIFT (12U)
20299/*! OEEN - Enables Read Data Strobe in a byte lane
20300 */
20301#define DDRPHY_DX0GCR1_OEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_OEEN_SHIFT)) & DDRPHY_DX0GCR1_OEEN_MASK)
20302#define DDRPHY_DX0GCR1_QSSEL_MASK (0x2000U)
20303#define DDRPHY_DX0GCR1_QSSEL_SHIFT (13U)
20304/*! QSSEL - Select the delayed or non-delayed read data strobe
20305 */
20306#define DDRPHY_DX0GCR1_QSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_QSSEL_SHIFT)) & DDRPHY_DX0GCR1_QSSEL_MASK)
20307#define DDRPHY_DX0GCR1_QSNSEL_MASK (0x4000U)
20308#define DDRPHY_DX0GCR1_QSNSEL_SHIFT (14U)
20309/*! QSNSEL - Select the delayed or non-delayed read data strobe #
20310 */
20311#define DDRPHY_DX0GCR1_QSNSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_QSNSEL_SHIFT)) & DDRPHY_DX0GCR1_QSNSEL_MASK)
20312#define DDRPHY_DX0GCR1_RESERVED_15_MASK (0x8000U)
20313#define DDRPHY_DX0GCR1_RESERVED_15_SHIFT (15U)
20314/*! RESERVED_15 - Reserved. Returns zeroes on reads.
20315 */
20316#define DDRPHY_DX0GCR1_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX0GCR1_RESERVED_15_MASK)
20317#define DDRPHY_DX0GCR1_DXPDRMODE_MASK (0xFFFF0000U)
20318#define DDRPHY_DX0GCR1_DXPDRMODE_SHIFT (16U)
20319/*! DXPDRMODE - Enables the PDR mode for DQ[7:0]
20320 */
20321#define DDRPHY_DX0GCR1_DXPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX0GCR1_DXPDRMODE_MASK)
20322/*! @} */
20323
20324/*! @name DX0GCR2 - DATX8 n General Configuration Register 2 */
20325/*! @{ */
20326#define DDRPHY_DX0GCR2_DXTEMODE_MASK (0xFFFFU)
20327#define DDRPHY_DX0GCR2_DXTEMODE_SHIFT (0U)
20328/*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0]
20329 */
20330#define DDRPHY_DX0GCR2_DXTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX0GCR2_DXTEMODE_MASK)
20331#define DDRPHY_DX0GCR2_DXOEMODE_MASK (0xFFFF0000U)
20332#define DDRPHY_DX0GCR2_DXOEMODE_SHIFT (16U)
20333/*! DXOEMODE - Enables the OE mode values for DQ[7:0]
20334 */
20335#define DDRPHY_DX0GCR2_DXOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX0GCR2_DXOEMODE_MASK)
20336/*! @} */
20337
20338/*! @name DX0GCR3 - DATX8 n General Configuration Register 3 */
20339/*! @{ */
20340#define DDRPHY_DX0GCR3_WDMBVT_MASK (0x1U)
20341#define DDRPHY_DX0GCR3_WDMBVT_SHIFT (0U)
20342/*! WDMBVT - Write Data Mask BDL VT Compensation
20343 */
20344#define DDRPHY_DX0GCR3_WDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_WDMBVT_SHIFT)) & DDRPHY_DX0GCR3_WDMBVT_MASK)
20345#define DDRPHY_DX0GCR3_RDMBVT_MASK (0x2U)
20346#define DDRPHY_DX0GCR3_RDMBVT_SHIFT (1U)
20347/*! RDMBVT - Read Data Mask BDL VT Compensation
20348 */
20349#define DDRPHY_DX0GCR3_RDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_RDMBVT_SHIFT)) & DDRPHY_DX0GCR3_RDMBVT_MASK)
20350#define DDRPHY_DX0GCR3_DSPDRMODE_MASK (0xCU)
20351#define DDRPHY_DX0GCR3_DSPDRMODE_SHIFT (2U)
20352/*! DSPDRMODE - Enables the PDR mode values for DQS.
20353 */
20354#define DDRPHY_DX0GCR3_DSPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX0GCR3_DSPDRMODE_MASK)
20355#define DDRPHY_DX0GCR3_DSTEMODE_MASK (0x30U)
20356#define DDRPHY_DX0GCR3_DSTEMODE_SHIFT (4U)
20357/*! DSTEMODE - Enables the TE mode values for DQS.
20358 */
20359#define DDRPHY_DX0GCR3_DSTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX0GCR3_DSTEMODE_MASK)
20360#define DDRPHY_DX0GCR3_DSOEMODE_MASK (0xC0U)
20361#define DDRPHY_DX0GCR3_DSOEMODE_SHIFT (6U)
20362/*! DSOEMODE - Enables the OE mode values for DQS.
20363 */
20364#define DDRPHY_DX0GCR3_DSOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX0GCR3_DSOEMODE_MASK)
20365#define DDRPHY_DX0GCR3_WDSBVT_MASK (0x100U)
20366#define DDRPHY_DX0GCR3_WDSBVT_SHIFT (8U)
20367/*! WDSBVT - Write Data Strobe BDL VT Compensation
20368 */
20369#define DDRPHY_DX0GCR3_WDSBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_WDSBVT_SHIFT)) & DDRPHY_DX0GCR3_WDSBVT_MASK)
20370#define DDRPHY_DX0GCR3_RESERVED_9_MASK (0x200U)
20371#define DDRPHY_DX0GCR3_RESERVED_9_SHIFT (9U)
20372/*! RESERVED_9 - Reserved. Returns zeroes on reads.
20373 */
20374#define DDRPHY_DX0GCR3_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX0GCR3_RESERVED_9_MASK)
20375#define DDRPHY_DX0GCR3_DMPDRMODE_MASK (0xC00U)
20376#define DDRPHY_DX0GCR3_DMPDRMODE_SHIFT (10U)
20377/*! DMPDRMODE - Enables the PDR mode values for DM.
20378 */
20379#define DDRPHY_DX0GCR3_DMPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX0GCR3_DMPDRMODE_MASK)
20380#define DDRPHY_DX0GCR3_DMTEMODE_MASK (0x3000U)
20381#define DDRPHY_DX0GCR3_DMTEMODE_SHIFT (12U)
20382/*! DMTEMODE - Enables the TE mode values for DM.
20383 */
20384#define DDRPHY_DX0GCR3_DMTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX0GCR3_DMTEMODE_MASK)
20385#define DDRPHY_DX0GCR3_DMOEMODE_MASK (0xC000U)
20386#define DDRPHY_DX0GCR3_DMOEMODE_SHIFT (14U)
20387/*! DMOEMODE - Enables the OE mode values for DM.
20388 */
20389#define DDRPHY_DX0GCR3_DMOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX0GCR3_DMOEMODE_MASK)
20390#define DDRPHY_DX0GCR3_DSNPDRMODE_MASK (0x30000U)
20391#define DDRPHY_DX0GCR3_DSNPDRMODE_SHIFT (16U)
20392/*! DSNPDRMODE - Enables the PDR mode for DQS
20393 */
20394#define DDRPHY_DX0GCR3_DSNPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX0GCR3_DSNPDRMODE_MASK)
20395#define DDRPHY_DX0GCR3_DSNTEMODE_MASK (0xC0000U)
20396#define DDRPHY_DX0GCR3_DSNTEMODE_SHIFT (18U)
20397/*! DSNTEMODE - Enables the TE mode for DQS
20398 */
20399#define DDRPHY_DX0GCR3_DSNTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX0GCR3_DSNTEMODE_MASK)
20400#define DDRPHY_DX0GCR3_DSNOEMODE_MASK (0x300000U)
20401#define DDRPHY_DX0GCR3_DSNOEMODE_SHIFT (20U)
20402/*! DSNOEMODE - Enables the OE mode for DQs
20403 */
20404#define DDRPHY_DX0GCR3_DSNOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX0GCR3_DSNOEMODE_MASK)
20405#define DDRPHY_DX0GCR3_PDRBVT_MASK (0x400000U)
20406#define DDRPHY_DX0GCR3_PDRBVT_SHIFT (22U)
20407/*! PDRBVT - Power Down Receiver BDL VT Compensation
20408 */
20409#define DDRPHY_DX0GCR3_PDRBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_PDRBVT_SHIFT)) & DDRPHY_DX0GCR3_PDRBVT_MASK)
20410#define DDRPHY_DX0GCR3_RGSLVT_MASK (0x800000U)
20411#define DDRPHY_DX0GCR3_RGSLVT_SHIFT (23U)
20412/*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation
20413 */
20414#define DDRPHY_DX0GCR3_RGSLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_RGSLVT_SHIFT)) & DDRPHY_DX0GCR3_RGSLVT_MASK)
20415#define DDRPHY_DX0GCR3_WLLVT_MASK (0x1000000U)
20416#define DDRPHY_DX0GCR3_WLLVT_SHIFT (24U)
20417/*! WLLVT - Write Leveling LCDL Delay VT Compensation
20418 */
20419#define DDRPHY_DX0GCR3_WLLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_WLLVT_SHIFT)) & DDRPHY_DX0GCR3_WLLVT_MASK)
20420#define DDRPHY_DX0GCR3_WDLVT_MASK (0x2000000U)
20421#define DDRPHY_DX0GCR3_WDLVT_SHIFT (25U)
20422/*! WDLVT - Write DQ LCDL Delay VT Compensation
20423 */
20424#define DDRPHY_DX0GCR3_WDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_WDLVT_SHIFT)) & DDRPHY_DX0GCR3_WDLVT_MASK)
20425#define DDRPHY_DX0GCR3_RDLVT_MASK (0x4000000U)
20426#define DDRPHY_DX0GCR3_RDLVT_SHIFT (26U)
20427/*! RDLVT - Read DQS LCDL Delay VT Compensation
20428 */
20429#define DDRPHY_DX0GCR3_RDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_RDLVT_SHIFT)) & DDRPHY_DX0GCR3_RDLVT_MASK)
20430#define DDRPHY_DX0GCR3_RGLVT_MASK (0x8000000U)
20431#define DDRPHY_DX0GCR3_RGLVT_SHIFT (27U)
20432/*! RGLVT - Read DQS Gating LCDL Delay VT Compensation
20433 */
20434#define DDRPHY_DX0GCR3_RGLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_RGLVT_SHIFT)) & DDRPHY_DX0GCR3_RGLVT_MASK)
20435#define DDRPHY_DX0GCR3_WDBVT_MASK (0x10000000U)
20436#define DDRPHY_DX0GCR3_WDBVT_SHIFT (28U)
20437/*! WDBVT - Write Data BDL VT Compensation
20438 */
20439#define DDRPHY_DX0GCR3_WDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_WDBVT_SHIFT)) & DDRPHY_DX0GCR3_WDBVT_MASK)
20440#define DDRPHY_DX0GCR3_RDBVT_MASK (0x20000000U)
20441#define DDRPHY_DX0GCR3_RDBVT_SHIFT (29U)
20442/*! RDBVT - Read Data BDL VT Compensation
20443 */
20444#define DDRPHY_DX0GCR3_RDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_RDBVT_SHIFT)) & DDRPHY_DX0GCR3_RDBVT_MASK)
20445#define DDRPHY_DX0GCR3_TEBVT_MASK (0x40000000U)
20446#define DDRPHY_DX0GCR3_TEBVT_SHIFT (30U)
20447/*! TEBVT - Termination Enable BDL VT Compensation
20448 */
20449#define DDRPHY_DX0GCR3_TEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_TEBVT_SHIFT)) & DDRPHY_DX0GCR3_TEBVT_MASK)
20450#define DDRPHY_DX0GCR3_OEBVT_MASK (0x80000000U)
20451#define DDRPHY_DX0GCR3_OEBVT_SHIFT (31U)
20452/*! OEBVT - Output Enable BDL VT Compensation
20453 */
20454#define DDRPHY_DX0GCR3_OEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR3_OEBVT_SHIFT)) & DDRPHY_DX0GCR3_OEBVT_MASK)
20455/*! @} */
20456
20457/*! @name DX0GCR4 - DATX8 n General Configuration Register 4 */
20458/*! @{ */
20459#define DDRPHY_DX0GCR4_DXREFIMON_MASK (0x3U)
20460#define DDRPHY_DX0GCR4_DXREFIMON_SHIFT (0U)
20461/*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane.
20462 */
20463#define DDRPHY_DX0GCR4_DXREFIMON(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX0GCR4_DXREFIMON_MASK)
20464#define DDRPHY_DX0GCR4_DXREFIEN_MASK (0x3CU)
20465#define DDRPHY_DX0GCR4_DXREFIEN_SHIFT (2U)
20466/*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
20467 */
20468#define DDRPHY_DX0GCR4_DXREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX0GCR4_DXREFIEN_MASK)
20469#define DDRPHY_DX0GCR4_RESERVED_7_6_MASK (0xC0U)
20470#define DDRPHY_DX0GCR4_RESERVED_7_6_SHIFT (6U)
20471/*! RESERVED_7_6 - Reserved. Returns zeros on reads.
20472 */
20473#define DDRPHY_DX0GCR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX0GCR4_RESERVED_7_6_MASK)
20474#define DDRPHY_DX0GCR4_DXREFSSEL_MASK (0x7F00U)
20475#define DDRPHY_DX0GCR4_DXREFSSEL_SHIFT (8U)
20476/*! DXREFSSEL - Byte Lane Single-End VREF Select
20477 */
20478#define DDRPHY_DX0GCR4_DXREFSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX0GCR4_DXREFSSEL_MASK)
20479#define DDRPHY_DX0GCR4_DXREFSSELRANGE_MASK (0x8000U)
20480#define DDRPHY_DX0GCR4_DXREFSSELRANGE_SHIFT (15U)
20481/*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select
20482 */
20483#define DDRPHY_DX0GCR4_DXREFSSELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX0GCR4_DXREFSSELRANGE_MASK)
20484#define DDRPHY_DX0GCR4_DXREFESEL_MASK (0x7F0000U)
20485#define DDRPHY_DX0GCR4_DXREFESEL_SHIFT (16U)
20486/*! DXREFESEL - Byte Lane External VREF Select
20487 */
20488#define DDRPHY_DX0GCR4_DXREFESEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX0GCR4_DXREFESEL_MASK)
20489#define DDRPHY_DX0GCR4_DXREFESELRANGE_MASK (0x800000U)
20490#define DDRPHY_DX0GCR4_DXREFESELRANGE_SHIFT (23U)
20491/*! DXREFESELRANGE - External VREF generator REFSEL range select
20492 */
20493#define DDRPHY_DX0GCR4_DXREFESELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX0GCR4_DXREFESELRANGE_MASK)
20494#define DDRPHY_DX0GCR4_RESERVED_24_MASK (0x1000000U)
20495#define DDRPHY_DX0GCR4_RESERVED_24_SHIFT (24U)
20496/*! RESERVED_24 - Reserved. Returns zeros on reads.
20497 */
20498#define DDRPHY_DX0GCR4_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX0GCR4_RESERVED_24_MASK)
20499#define DDRPHY_DX0GCR4_DXREFSEN_MASK (0x2000000U)
20500#define DDRPHY_DX0GCR4_DXREFSEN_SHIFT (25U)
20501/*! DXREFSEN - Byte Lane Single-End VREF Enable
20502 */
20503#define DDRPHY_DX0GCR4_DXREFSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX0GCR4_DXREFSEN_MASK)
20504#define DDRPHY_DX0GCR4_DXREFEEN_MASK (0xC000000U)
20505#define DDRPHY_DX0GCR4_DXREFEEN_SHIFT (26U)
20506/*! DXREFEEN - Byte Lane Internal VREF Enable
20507 */
20508#define DDRPHY_DX0GCR4_DXREFEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX0GCR4_DXREFEEN_MASK)
20509#define DDRPHY_DX0GCR4_DXREFPEN_MASK (0x10000000U)
20510#define DDRPHY_DX0GCR4_DXREFPEN_SHIFT (28U)
20511/*! DXREFPEN - Byte Lane VREF Pad Enable
20512 */
20513#define DDRPHY_DX0GCR4_DXREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX0GCR4_DXREFPEN_MASK)
20514#define DDRPHY_DX0GCR4_RESERVED_31_29_MASK (0xE0000000U)
20515#define DDRPHY_DX0GCR4_RESERVED_31_29_SHIFT (29U)
20516/*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs)
20517 */
20518#define DDRPHY_DX0GCR4_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX0GCR4_RESERVED_31_29_MASK)
20519/*! @} */
20520
20521/*! @name DX0GCR5 - DATX8 n General Configuration Register 5 */
20522/*! @{ */
20523#define DDRPHY_DX0GCR5_DXREFISELR0_MASK (0x7FU)
20524#define DDRPHY_DX0GCR5_DXREFISELR0_SHIFT (0U)
20525/*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0
20526 */
20527#define DDRPHY_DX0GCR5_DXREFISELR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX0GCR5_DXREFISELR0_MASK)
20528#define DDRPHY_DX0GCR5_RESERVED_7_MASK (0x80U)
20529#define DDRPHY_DX0GCR5_RESERVED_7_SHIFT (7U)
20530/*! RESERVED_7 - Reserved. Returns zeros on reads.
20531 */
20532#define DDRPHY_DX0GCR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX0GCR5_RESERVED_7_MASK)
20533#define DDRPHY_DX0GCR5_DXREFISELR1_MASK (0x7F00U)
20534#define DDRPHY_DX0GCR5_DXREFISELR1_SHIFT (8U)
20535/*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1
20536 */
20537#define DDRPHY_DX0GCR5_DXREFISELR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX0GCR5_DXREFISELR1_MASK)
20538#define DDRPHY_DX0GCR5_RESERVED_15_MASK (0x8000U)
20539#define DDRPHY_DX0GCR5_RESERVED_15_SHIFT (15U)
20540/*! RESERVED_15 - Reserved. Returns zeros on reads.
20541 */
20542#define DDRPHY_DX0GCR5_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX0GCR5_RESERVED_15_MASK)
20543#define DDRPHY_DX0GCR5_DXREFISELR2_MASK (0x7F0000U)
20544#define DDRPHY_DX0GCR5_DXREFISELR2_SHIFT (16U)
20545/*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2
20546 */
20547#define DDRPHY_DX0GCR5_DXREFISELR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX0GCR5_DXREFISELR2_MASK)
20548#define DDRPHY_DX0GCR5_RESERVED_23_MASK (0x800000U)
20549#define DDRPHY_DX0GCR5_RESERVED_23_SHIFT (23U)
20550/*! RESERVED_23 - Reserved. Returns zeros on reads.
20551 */
20552#define DDRPHY_DX0GCR5_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX0GCR5_RESERVED_23_MASK)
20553#define DDRPHY_DX0GCR5_DXREFISELR3_MASK (0x7F000000U)
20554#define DDRPHY_DX0GCR5_DXREFISELR3_SHIFT (24U)
20555/*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3
20556 */
20557#define DDRPHY_DX0GCR5_DXREFISELR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX0GCR5_DXREFISELR3_MASK)
20558#define DDRPHY_DX0GCR5_RESERVED_31_MASK (0x80000000U)
20559#define DDRPHY_DX0GCR5_RESERVED_31_SHIFT (31U)
20560/*! RESERVED_31 - Reserved. Returns zeros on reads.
20561 */
20562#define DDRPHY_DX0GCR5_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX0GCR5_RESERVED_31_MASK)
20563/*! @} */
20564
20565/*! @name DX0GCR6 - DATX8 n General Configuration Register 6 */
20566/*! @{ */
20567#define DDRPHY_DX0GCR6_DXDQVREFR0_MASK (0x3FU)
20568#define DDRPHY_DX0GCR6_DXDQVREFR0_SHIFT (0U)
20569/*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0
20570 */
20571#define DDRPHY_DX0GCR6_DXDQVREFR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX0GCR6_DXDQVREFR0_MASK)
20572#define DDRPHY_DX0GCR6_RESERVED_7_6_MASK (0xC0U)
20573#define DDRPHY_DX0GCR6_RESERVED_7_6_SHIFT (6U)
20574/*! RESERVED_7_6 - Reserved. Returns zeros on reads.
20575 */
20576#define DDRPHY_DX0GCR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX0GCR6_RESERVED_7_6_MASK)
20577#define DDRPHY_DX0GCR6_DXDQVREFR1_MASK (0x3F00U)
20578#define DDRPHY_DX0GCR6_DXDQVREFR1_SHIFT (8U)
20579/*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1
20580 */
20581#define DDRPHY_DX0GCR6_DXDQVREFR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX0GCR6_DXDQVREFR1_MASK)
20582#define DDRPHY_DX0GCR6_RESERVED_15_14_MASK (0xC000U)
20583#define DDRPHY_DX0GCR6_RESERVED_15_14_SHIFT (14U)
20584/*! RESERVED_15_14 - Reserved. Returns zeros on reads.
20585 */
20586#define DDRPHY_DX0GCR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX0GCR6_RESERVED_15_14_MASK)
20587#define DDRPHY_DX0GCR6_DXDQVREFR2_MASK (0x3F0000U)
20588#define DDRPHY_DX0GCR6_DXDQVREFR2_SHIFT (16U)
20589/*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2
20590 */
20591#define DDRPHY_DX0GCR6_DXDQVREFR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX0GCR6_DXDQVREFR2_MASK)
20592#define DDRPHY_DX0GCR6_RESERVED_23_22_MASK (0xC00000U)
20593#define DDRPHY_DX0GCR6_RESERVED_23_22_SHIFT (22U)
20594/*! RESERVED_23_22 - Reserved. Returns zeros on reads.
20595 */
20596#define DDRPHY_DX0GCR6_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX0GCR6_RESERVED_23_22_MASK)
20597#define DDRPHY_DX0GCR6_DXDQVREFR3_MASK (0x3F000000U)
20598#define DDRPHY_DX0GCR6_DXDQVREFR3_SHIFT (24U)
20599/*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3
20600 */
20601#define DDRPHY_DX0GCR6_DXDQVREFR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX0GCR6_DXDQVREFR3_MASK)
20602#define DDRPHY_DX0GCR6_RESERVED_31_30_MASK (0xC0000000U)
20603#define DDRPHY_DX0GCR6_RESERVED_31_30_SHIFT (30U)
20604/*! RESERVED_31_30 - Reserved. Returns zeros on reads.
20605 */
20606#define DDRPHY_DX0GCR6_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX0GCR6_RESERVED_31_30_MASK)
20607/*! @} */
20608
20609/*! @name DX0GCR7 - DATX8 n General Configuration Register 7 */
20610/*! @{ */
20611#define DDRPHY_DX0GCR7_DCALSVAL_MASK (0x1FFU)
20612#define DDRPHY_DX0GCR7_DCALSVAL_SHIFT (0U)
20613/*! DCALSVAL - DDL Calibration Starting Value
20614 */
20615#define DDRPHY_DX0GCR7_DCALSVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX0GCR7_DCALSVAL_MASK)
20616#define DDRPHY_DX0GCR7_DCALTYPE_MASK (0x200U)
20617#define DDRPHY_DX0GCR7_DCALTYPE_SHIFT (9U)
20618/*! DCALTYPE - DDL Calibration Type
20619 */
20620#define DDRPHY_DX0GCR7_DCALTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX0GCR7_DCALTYPE_MASK)
20621#define DDRPHY_DX0GCR7_RESERVED_17_10_MASK (0x3FC00U)
20622#define DDRPHY_DX0GCR7_RESERVED_17_10_SHIFT (10U)
20623/*! RESERVED_17_10 - Reserved. Caution, do not write to this register field.
20624 */
20625#define DDRPHY_DX0GCR7_RESERVED_17_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX0GCR7_RESERVED_17_10_MASK)
20626#define DDRPHY_DX0GCR7_RESERVED_18_MASK (0x40000U)
20627#define DDRPHY_DX0GCR7_RESERVED_18_SHIFT (18U)
20628/*! RESERVED_18 - Reserved. Caution, do not write to this register field.
20629 */
20630#define DDRPHY_DX0GCR7_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX0GCR7_RESERVED_18_MASK)
20631#define DDRPHY_DX0GCR7_RESERVED_31_19_MASK (0xFFF80000U)
20632#define DDRPHY_DX0GCR7_RESERVED_31_19_SHIFT (19U)
20633/*! RESERVED_31_19 - Reserved. Caution, do not write to this register field.
20634 */
20635#define DDRPHY_DX0GCR7_RESERVED_31_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX0GCR7_RESERVED_31_19_MASK)
20636/*! @} */
20637
20638/*! @name DX0GCR8 - DATX8 n General Configuration Register 8 */
20639/*! @{ */
20640#define DDRPHY_DX0GCR8_RESERVED_5_0_MASK (0x3FU)
20641#define DDRPHY_DX0GCR8_RESERVED_5_0_SHIFT (0U)
20642/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
20643 */
20644#define DDRPHY_DX0GCR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_5_0_MASK)
20645#define DDRPHY_DX0GCR8_RESERVED_7_6_MASK (0xC0U)
20646#define DDRPHY_DX0GCR8_RESERVED_7_6_SHIFT (6U)
20647/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
20648 */
20649#define DDRPHY_DX0GCR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_7_6_MASK)
20650#define DDRPHY_DX0GCR8_RESERVED_13_8_MASK (0x3F00U)
20651#define DDRPHY_DX0GCR8_RESERVED_13_8_SHIFT (8U)
20652/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
20653 */
20654#define DDRPHY_DX0GCR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_13_8_MASK)
20655#define DDRPHY_DX0GCR8_RESERVED_15_14_MASK (0xC000U)
20656#define DDRPHY_DX0GCR8_RESERVED_15_14_SHIFT (14U)
20657/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
20658 */
20659#define DDRPHY_DX0GCR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_15_14_MASK)
20660#define DDRPHY_DX0GCR8_RESERVED_21_16_MASK (0x3F0000U)
20661#define DDRPHY_DX0GCR8_RESERVED_21_16_SHIFT (16U)
20662/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
20663 */
20664#define DDRPHY_DX0GCR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_21_16_MASK)
20665#define DDRPHY_DX0GCR8_RESERVED_23_22_MASK (0xC00000U)
20666#define DDRPHY_DX0GCR8_RESERVED_23_22_SHIFT (22U)
20667/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
20668 */
20669#define DDRPHY_DX0GCR8_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_23_22_MASK)
20670#define DDRPHY_DX0GCR8_RESERVED_29_24_MASK (0x3F000000U)
20671#define DDRPHY_DX0GCR8_RESERVED_29_24_SHIFT (24U)
20672/*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
20673 */
20674#define DDRPHY_DX0GCR8_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_29_24_MASK)
20675#define DDRPHY_DX0GCR8_RESERVED_31_30_MASK (0xC0000000U)
20676#define DDRPHY_DX0GCR8_RESERVED_31_30_SHIFT (30U)
20677/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
20678 */
20679#define DDRPHY_DX0GCR8_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX0GCR8_RESERVED_31_30_MASK)
20680/*! @} */
20681
20682/*! @name DX0GCR9 - DATX8 n General Configuration Register 9 */
20683/*! @{ */
20684#define DDRPHY_DX0GCR9_RESERVED_5_0_MASK (0x3FU)
20685#define DDRPHY_DX0GCR9_RESERVED_5_0_SHIFT (0U)
20686/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
20687 */
20688#define DDRPHY_DX0GCR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_5_0_MASK)
20689#define DDRPHY_DX0GCR9_RESERVED_7_6_MASK (0xC0U)
20690#define DDRPHY_DX0GCR9_RESERVED_7_6_SHIFT (6U)
20691/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
20692 */
20693#define DDRPHY_DX0GCR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_7_6_MASK)
20694#define DDRPHY_DX0GCR9_RESERVED_13_8_MASK (0x3F00U)
20695#define DDRPHY_DX0GCR9_RESERVED_13_8_SHIFT (8U)
20696/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
20697 */
20698#define DDRPHY_DX0GCR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_13_8_MASK)
20699#define DDRPHY_DX0GCR9_RESERVED_15_14_MASK (0xC000U)
20700#define DDRPHY_DX0GCR9_RESERVED_15_14_SHIFT (14U)
20701/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
20702 */
20703#define DDRPHY_DX0GCR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_15_14_MASK)
20704#define DDRPHY_DX0GCR9_RESERVED_21_16_MASK (0x3F0000U)
20705#define DDRPHY_DX0GCR9_RESERVED_21_16_SHIFT (16U)
20706/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
20707 */
20708#define DDRPHY_DX0GCR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_21_16_MASK)
20709#define DDRPHY_DX0GCR9_RESERVED_23_22_MASK (0xC00000U)
20710#define DDRPHY_DX0GCR9_RESERVED_23_22_SHIFT (22U)
20711/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
20712 */
20713#define DDRPHY_DX0GCR9_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_23_22_MASK)
20714#define DDRPHY_DX0GCR9_RESERVED_29_24_MASK (0x3F000000U)
20715#define DDRPHY_DX0GCR9_RESERVED_29_24_SHIFT (24U)
20716/*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
20717 */
20718#define DDRPHY_DX0GCR9_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_29_24_MASK)
20719#define DDRPHY_DX0GCR9_RESERVED_31_30_MASK (0xC0000000U)
20720#define DDRPHY_DX0GCR9_RESERVED_31_30_SHIFT (30U)
20721/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
20722 */
20723#define DDRPHY_DX0GCR9_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX0GCR9_RESERVED_31_30_MASK)
20724/*! @} */
20725
20726/*! @name DX0DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */
20727/*! @{ */
20728#define DDRPHY_DX0DQMAP0_DQ0MAP_MASK (0xFU)
20729#define DDRPHY_DX0DQMAP0_DQ0MAP_SHIFT (0U)
20730/*! DQ0MAP - DQ bit 0 DATX8 slice mapping index
20731 */
20732#define DDRPHY_DX0DQMAP0_DQ0MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX0DQMAP0_DQ0MAP_MASK)
20733#define DDRPHY_DX0DQMAP0_DQ1MAP_MASK (0xF0U)
20734#define DDRPHY_DX0DQMAP0_DQ1MAP_SHIFT (4U)
20735/*! DQ1MAP - DQ bit 1 DATX8 slice mapping index
20736 */
20737#define DDRPHY_DX0DQMAP0_DQ1MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX0DQMAP0_DQ1MAP_MASK)
20738#define DDRPHY_DX0DQMAP0_DQ2MAP_MASK (0xF00U)
20739#define DDRPHY_DX0DQMAP0_DQ2MAP_SHIFT (8U)
20740/*! DQ2MAP - DQ bit 2 DATX8 slice mapping index
20741 */
20742#define DDRPHY_DX0DQMAP0_DQ2MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX0DQMAP0_DQ2MAP_MASK)
20743#define DDRPHY_DX0DQMAP0_DQ3MAP_MASK (0xF000U)
20744#define DDRPHY_DX0DQMAP0_DQ3MAP_SHIFT (12U)
20745/*! DQ3MAP - DQ bit 3 DATX8 slice mapping index
20746 */
20747#define DDRPHY_DX0DQMAP0_DQ3MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX0DQMAP0_DQ3MAP_MASK)
20748#define DDRPHY_DX0DQMAP0_DQ4MAP_MASK (0xF0000U)
20749#define DDRPHY_DX0DQMAP0_DQ4MAP_SHIFT (16U)
20750/*! DQ4MAP - DQ bit 4 DATX8 slice mapping index
20751 */
20752#define DDRPHY_DX0DQMAP0_DQ4MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX0DQMAP0_DQ4MAP_MASK)
20753#define DDRPHY_DX0DQMAP0_RESERVED_30_20_MASK (0x7FF00000U)
20754#define DDRPHY_DX0DQMAP0_RESERVED_30_20_SHIFT (20U)
20755/*! RESERVED_30_20 - Reserved. Return zeroes on reads.
20756 */
20757#define DDRPHY_DX0DQMAP0_RESERVED_30_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX0DQMAP0_RESERVED_30_20_MASK)
20758#define DDRPHY_DX0DQMAP0_MAPOK_MASK (0x80000000U)
20759#define DDRPHY_DX0DQMAP0_MAPOK_SHIFT (31U)
20760/*! MAPOK - Checksum bit
20761 */
20762#define DDRPHY_DX0DQMAP0_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX0DQMAP0_MAPOK_MASK)
20763/*! @} */
20764
20765/*! @name DX0DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */
20766/*! @{ */
20767#define DDRPHY_DX0DQMAP1_DQ5MAP_MASK (0xFU)
20768#define DDRPHY_DX0DQMAP1_DQ5MAP_SHIFT (0U)
20769/*! DQ5MAP - DQ bit 5 DATX8 slice mapping index
20770 */
20771#define DDRPHY_DX0DQMAP1_DQ5MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX0DQMAP1_DQ5MAP_MASK)
20772#define DDRPHY_DX0DQMAP1_DQ6MAP_MASK (0xF0U)
20773#define DDRPHY_DX0DQMAP1_DQ6MAP_SHIFT (4U)
20774/*! DQ6MAP - DQ bit 6 DATX8 slice mapping index
20775 */
20776#define DDRPHY_DX0DQMAP1_DQ6MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX0DQMAP1_DQ6MAP_MASK)
20777#define DDRPHY_DX0DQMAP1_DQ7MAP_MASK (0xF00U)
20778#define DDRPHY_DX0DQMAP1_DQ7MAP_SHIFT (8U)
20779/*! DQ7MAP - DQ bit 7 DATX8 slice mapping index
20780 */
20781#define DDRPHY_DX0DQMAP1_DQ7MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX0DQMAP1_DQ7MAP_MASK)
20782#define DDRPHY_DX0DQMAP1_DMMAP_MASK (0xF000U)
20783#define DDRPHY_DX0DQMAP1_DMMAP_SHIFT (12U)
20784/*! DMMAP - DM bit DATX8 slice mapping index
20785 */
20786#define DDRPHY_DX0DQMAP1_DMMAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX0DQMAP1_DMMAP_MASK)
20787#define DDRPHY_DX0DQMAP1_RESERVED_30_16_MASK (0x7FFF0000U)
20788#define DDRPHY_DX0DQMAP1_RESERVED_30_16_SHIFT (16U)
20789/*! RESERVED_30_16 - Reserved. Return zeroes on reads.
20790 */
20791#define DDRPHY_DX0DQMAP1_RESERVED_30_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX0DQMAP1_RESERVED_30_16_MASK)
20792#define DDRPHY_DX0DQMAP1_MAPOK_MASK (0x80000000U)
20793#define DDRPHY_DX0DQMAP1_MAPOK_SHIFT (31U)
20794/*! MAPOK - Checksum bit
20795 */
20796#define DDRPHY_DX0DQMAP1_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX0DQMAP1_MAPOK_MASK)
20797/*! @} */
20798
20799/*! @name DX0BDLR0 - DATX8 n Bit Delay Line Register 0 */
20800/*! @{ */
20801#define DDRPHY_DX0BDLR0_DQ0WBD_MASK (0x3FU)
20802#define DDRPHY_DX0BDLR0_DQ0WBD_SHIFT (0U)
20803/*! DQ0WBD - DQ0 Write Bit Delay
20804 */
20805#define DDRPHY_DX0BDLR0_DQ0WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX0BDLR0_DQ0WBD_MASK)
20806#define DDRPHY_DX0BDLR0_RESERVED_7_6_MASK (0xC0U)
20807#define DDRPHY_DX0BDLR0_RESERVED_7_6_SHIFT (6U)
20808/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
20809 */
20810#define DDRPHY_DX0BDLR0_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR0_RESERVED_7_6_MASK)
20811#define DDRPHY_DX0BDLR0_DQ1WBD_MASK (0x3F00U)
20812#define DDRPHY_DX0BDLR0_DQ1WBD_SHIFT (8U)
20813/*! DQ1WBD - DQ1 Write Bit Delay
20814 */
20815#define DDRPHY_DX0BDLR0_DQ1WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX0BDLR0_DQ1WBD_MASK)
20816#define DDRPHY_DX0BDLR0_RESERVED_15_14_MASK (0xC000U)
20817#define DDRPHY_DX0BDLR0_RESERVED_15_14_SHIFT (14U)
20818/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
20819 */
20820#define DDRPHY_DX0BDLR0_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR0_RESERVED_15_14_MASK)
20821#define DDRPHY_DX0BDLR0_DQ2WBD_MASK (0x3F0000U)
20822#define DDRPHY_DX0BDLR0_DQ2WBD_SHIFT (16U)
20823/*! DQ2WBD - DQ2 Write Bit Delay
20824 */
20825#define DDRPHY_DX0BDLR0_DQ2WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX0BDLR0_DQ2WBD_MASK)
20826#define DDRPHY_DX0BDLR0_RESERVED_23_22_MASK (0xC00000U)
20827#define DDRPHY_DX0BDLR0_RESERVED_23_22_SHIFT (22U)
20828/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
20829 */
20830#define DDRPHY_DX0BDLR0_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX0BDLR0_RESERVED_23_22_MASK)
20831#define DDRPHY_DX0BDLR0_DQ3WBD_MASK (0x3F000000U)
20832#define DDRPHY_DX0BDLR0_DQ3WBD_SHIFT (24U)
20833/*! DQ3WBD - DQ3 Write Bit Delay
20834 */
20835#define DDRPHY_DX0BDLR0_DQ3WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX0BDLR0_DQ3WBD_MASK)
20836#define DDRPHY_DX0BDLR0_RESERVED_31_30_MASK (0xC0000000U)
20837#define DDRPHY_DX0BDLR0_RESERVED_31_30_SHIFT (30U)
20838/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
20839 */
20840#define DDRPHY_DX0BDLR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX0BDLR0_RESERVED_31_30_MASK)
20841/*! @} */
20842
20843/*! @name DX0BDLR1 - DATX8 n Bit Delay Line Register 1 */
20844/*! @{ */
20845#define DDRPHY_DX0BDLR1_DQ4WBD_MASK (0x3FU)
20846#define DDRPHY_DX0BDLR1_DQ4WBD_SHIFT (0U)
20847/*! DQ4WBD - DQ4 Write Bit Delay
20848 */
20849#define DDRPHY_DX0BDLR1_DQ4WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX0BDLR1_DQ4WBD_MASK)
20850#define DDRPHY_DX0BDLR1_RESERVED_7_6_MASK (0xC0U)
20851#define DDRPHY_DX0BDLR1_RESERVED_7_6_SHIFT (6U)
20852/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
20853 */
20854#define DDRPHY_DX0BDLR1_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR1_RESERVED_7_6_MASK)
20855#define DDRPHY_DX0BDLR1_DQ5WBD_MASK (0x3F00U)
20856#define DDRPHY_DX0BDLR1_DQ5WBD_SHIFT (8U)
20857/*! DQ5WBD - DQ5 Write Bit Delay
20858 */
20859#define DDRPHY_DX0BDLR1_DQ5WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX0BDLR1_DQ5WBD_MASK)
20860#define DDRPHY_DX0BDLR1_RESERVED_15_14_MASK (0xC000U)
20861#define DDRPHY_DX0BDLR1_RESERVED_15_14_SHIFT (14U)
20862/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
20863 */
20864#define DDRPHY_DX0BDLR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR1_RESERVED_15_14_MASK)
20865#define DDRPHY_DX0BDLR1_DQ6WBD_MASK (0x3F0000U)
20866#define DDRPHY_DX0BDLR1_DQ6WBD_SHIFT (16U)
20867/*! DQ6WBD - DQ6 Write Bit Delay
20868 */
20869#define DDRPHY_DX0BDLR1_DQ6WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX0BDLR1_DQ6WBD_MASK)
20870#define DDRPHY_DX0BDLR1_RESERVED_23_22_MASK (0xC00000U)
20871#define DDRPHY_DX0BDLR1_RESERVED_23_22_SHIFT (22U)
20872/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
20873 */
20874#define DDRPHY_DX0BDLR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX0BDLR1_RESERVED_23_22_MASK)
20875#define DDRPHY_DX0BDLR1_DQ7WBD_MASK (0x3F000000U)
20876#define DDRPHY_DX0BDLR1_DQ7WBD_SHIFT (24U)
20877/*! DQ7WBD - DQ7 Write Bit Delay
20878 */
20879#define DDRPHY_DX0BDLR1_DQ7WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX0BDLR1_DQ7WBD_MASK)
20880#define DDRPHY_DX0BDLR1_RESERVED_31_30_MASK (0xC0000000U)
20881#define DDRPHY_DX0BDLR1_RESERVED_31_30_SHIFT (30U)
20882/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
20883 */
20884#define DDRPHY_DX0BDLR1_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX0BDLR1_RESERVED_31_30_MASK)
20885/*! @} */
20886
20887/*! @name DX0BDLR2 - DATX8 n Bit Delay Line Register 2 */
20888/*! @{ */
20889#define DDRPHY_DX0BDLR2_DMWBD_MASK (0x3FU)
20890#define DDRPHY_DX0BDLR2_DMWBD_SHIFT (0U)
20891/*! DMWBD - DM Write Bit Delay
20892 */
20893#define DDRPHY_DX0BDLR2_DMWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_DMWBD_SHIFT)) & DDRPHY_DX0BDLR2_DMWBD_MASK)
20894#define DDRPHY_DX0BDLR2_RESERVED_7_6_MASK (0xC0U)
20895#define DDRPHY_DX0BDLR2_RESERVED_7_6_SHIFT (6U)
20896/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
20897 */
20898#define DDRPHY_DX0BDLR2_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR2_RESERVED_7_6_MASK)
20899#define DDRPHY_DX0BDLR2_DSWBD_MASK (0x3F00U)
20900#define DDRPHY_DX0BDLR2_DSWBD_SHIFT (8U)
20901/*! DSWBD - DQS Write Bit Delay
20902 */
20903#define DDRPHY_DX0BDLR2_DSWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_DSWBD_SHIFT)) & DDRPHY_DX0BDLR2_DSWBD_MASK)
20904#define DDRPHY_DX0BDLR2_RESERVED_15_14_MASK (0xC000U)
20905#define DDRPHY_DX0BDLR2_RESERVED_15_14_SHIFT (14U)
20906/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
20907 */
20908#define DDRPHY_DX0BDLR2_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR2_RESERVED_15_14_MASK)
20909#define DDRPHY_DX0BDLR2_DSOEBD_MASK (0x3F0000U)
20910#define DDRPHY_DX0BDLR2_DSOEBD_SHIFT (16U)
20911/*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay
20912 */
20913#define DDRPHY_DX0BDLR2_DSOEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX0BDLR2_DSOEBD_MASK)
20914#define DDRPHY_DX0BDLR2_RESERVED_23_22_MASK (0xC00000U)
20915#define DDRPHY_DX0BDLR2_RESERVED_23_22_SHIFT (22U)
20916/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
20917 */
20918#define DDRPHY_DX0BDLR2_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX0BDLR2_RESERVED_23_22_MASK)
20919#define DDRPHY_DX0BDLR2_DSNWBD_MASK (0x3F000000U)
20920#define DDRPHY_DX0BDLR2_DSNWBD_SHIFT (24U)
20921/*! DSNWBD - DQSN Write Bit Delay
20922 */
20923#define DDRPHY_DX0BDLR2_DSNWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX0BDLR2_DSNWBD_MASK)
20924#define DDRPHY_DX0BDLR2_RESERVED_31_30_MASK (0xC0000000U)
20925#define DDRPHY_DX0BDLR2_RESERVED_31_30_SHIFT (30U)
20926/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
20927 */
20928#define DDRPHY_DX0BDLR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX0BDLR2_RESERVED_31_30_MASK)
20929/*! @} */
20930
20931/*! @name DX0BDLR3 - DATX8 n Bit Delay Line Register 3 */
20932/*! @{ */
20933#define DDRPHY_DX0BDLR3_DQ0RBD_MASK (0x3FU)
20934#define DDRPHY_DX0BDLR3_DQ0RBD_SHIFT (0U)
20935/*! DQ0RBD - DQ0 Read Bit Delay
20936 */
20937#define DDRPHY_DX0BDLR3_DQ0RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX0BDLR3_DQ0RBD_MASK)
20938#define DDRPHY_DX0BDLR3_RESERVED_7_6_MASK (0xC0U)
20939#define DDRPHY_DX0BDLR3_RESERVED_7_6_SHIFT (6U)
20940/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
20941 */
20942#define DDRPHY_DX0BDLR3_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR3_RESERVED_7_6_MASK)
20943#define DDRPHY_DX0BDLR3_DQ1RBD_MASK (0x3F00U)
20944#define DDRPHY_DX0BDLR3_DQ1RBD_SHIFT (8U)
20945/*! DQ1RBD - DQ1 Read Bit Delay
20946 */
20947#define DDRPHY_DX0BDLR3_DQ1RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX0BDLR3_DQ1RBD_MASK)
20948#define DDRPHY_DX0BDLR3_RESERVED_15_14_MASK (0xC000U)
20949#define DDRPHY_DX0BDLR3_RESERVED_15_14_SHIFT (14U)
20950/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
20951 */
20952#define DDRPHY_DX0BDLR3_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR3_RESERVED_15_14_MASK)
20953#define DDRPHY_DX0BDLR3_DQ2RBD_MASK (0x3F0000U)
20954#define DDRPHY_DX0BDLR3_DQ2RBD_SHIFT (16U)
20955/*! DQ2RBD - DQ2 Read Bit Delay
20956 */
20957#define DDRPHY_DX0BDLR3_DQ2RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX0BDLR3_DQ2RBD_MASK)
20958#define DDRPHY_DX0BDLR3_RESERVED_23_22_MASK (0xC00000U)
20959#define DDRPHY_DX0BDLR3_RESERVED_23_22_SHIFT (22U)
20960/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
20961 */
20962#define DDRPHY_DX0BDLR3_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX0BDLR3_RESERVED_23_22_MASK)
20963#define DDRPHY_DX0BDLR3_DQ3RBD_MASK (0x3F000000U)
20964#define DDRPHY_DX0BDLR3_DQ3RBD_SHIFT (24U)
20965/*! DQ3RBD - DQ3 Read Bit Delay
20966 */
20967#define DDRPHY_DX0BDLR3_DQ3RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX0BDLR3_DQ3RBD_MASK)
20968#define DDRPHY_DX0BDLR3_RESERVED_31_30_MASK (0xC0000000U)
20969#define DDRPHY_DX0BDLR3_RESERVED_31_30_SHIFT (30U)
20970/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
20971 */
20972#define DDRPHY_DX0BDLR3_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX0BDLR3_RESERVED_31_30_MASK)
20973/*! @} */
20974
20975/*! @name DX0BDLR4 - DATX8 n Bit Delay Line Register 4 */
20976/*! @{ */
20977#define DDRPHY_DX0BDLR4_DQ4RBD_MASK (0x3FU)
20978#define DDRPHY_DX0BDLR4_DQ4RBD_SHIFT (0U)
20979/*! DQ4RBD - DQ4 Read Bit Delay
20980 */
20981#define DDRPHY_DX0BDLR4_DQ4RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX0BDLR4_DQ4RBD_MASK)
20982#define DDRPHY_DX0BDLR4_RESERVED_7_6_MASK (0xC0U)
20983#define DDRPHY_DX0BDLR4_RESERVED_7_6_SHIFT (6U)
20984/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
20985 */
20986#define DDRPHY_DX0BDLR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR4_RESERVED_7_6_MASK)
20987#define DDRPHY_DX0BDLR4_DQ5RBD_MASK (0x3F00U)
20988#define DDRPHY_DX0BDLR4_DQ5RBD_SHIFT (8U)
20989/*! DQ5RBD - DQ5 Read Bit Delay
20990 */
20991#define DDRPHY_DX0BDLR4_DQ5RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX0BDLR4_DQ5RBD_MASK)
20992#define DDRPHY_DX0BDLR4_RESERVED_15_14_MASK (0xC000U)
20993#define DDRPHY_DX0BDLR4_RESERVED_15_14_SHIFT (14U)
20994/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
20995 */
20996#define DDRPHY_DX0BDLR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR4_RESERVED_15_14_MASK)
20997#define DDRPHY_DX0BDLR4_DQ6RBD_MASK (0x3F0000U)
20998#define DDRPHY_DX0BDLR4_DQ6RBD_SHIFT (16U)
20999/*! DQ6RBD - DQ6 Read Bit Delay
21000 */
21001#define DDRPHY_DX0BDLR4_DQ6RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX0BDLR4_DQ6RBD_MASK)
21002#define DDRPHY_DX0BDLR4_RESERVED_23_22_MASK (0xC00000U)
21003#define DDRPHY_DX0BDLR4_RESERVED_23_22_SHIFT (22U)
21004/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
21005 */
21006#define DDRPHY_DX0BDLR4_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX0BDLR4_RESERVED_23_22_MASK)
21007#define DDRPHY_DX0BDLR4_DQ7RBD_MASK (0x3F000000U)
21008#define DDRPHY_DX0BDLR4_DQ7RBD_SHIFT (24U)
21009/*! DQ7RBD - DQ7 Read Bit Delay
21010 */
21011#define DDRPHY_DX0BDLR4_DQ7RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX0BDLR4_DQ7RBD_MASK)
21012#define DDRPHY_DX0BDLR4_RESERVED_31_30_MASK (0xC0000000U)
21013#define DDRPHY_DX0BDLR4_RESERVED_31_30_SHIFT (30U)
21014/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
21015 */
21016#define DDRPHY_DX0BDLR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX0BDLR4_RESERVED_31_30_MASK)
21017/*! @} */
21018
21019/*! @name DX0BDLR5 - DATX8 n Bit Delay Line Register 5 */
21020/*! @{ */
21021#define DDRPHY_DX0BDLR5_DMRBD_MASK (0x3FU)
21022#define DDRPHY_DX0BDLR5_DMRBD_SHIFT (0U)
21023/*! DMRBD - DM Read Bit Delay
21024 */
21025#define DDRPHY_DX0BDLR5_DMRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR5_DMRBD_SHIFT)) & DDRPHY_DX0BDLR5_DMRBD_MASK)
21026#define DDRPHY_DX0BDLR5_RESERVED_31_6_MASK (0xFFFFFFC0U)
21027#define DDRPHY_DX0BDLR5_RESERVED_31_6_SHIFT (6U)
21028/*! RESERVED_31_6 - Reserved. Return zeroes on reads.
21029 */
21030#define DDRPHY_DX0BDLR5_RESERVED_31_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX0BDLR5_RESERVED_31_6_MASK)
21031/*! @} */
21032
21033/*! @name DX0BDLR6 - DATX8 n Bit Delay Line Register 6 */
21034/*! @{ */
21035#define DDRPHY_DX0BDLR6_RESERVED_7_0_MASK (0xFFU)
21036#define DDRPHY_DX0BDLR6_RESERVED_7_0_SHIFT (0U)
21037/*! RESERVED_7_0 - Reserved. Return zeroes on reads.
21038 */
21039#define DDRPHY_DX0BDLR6_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX0BDLR6_RESERVED_7_0_MASK)
21040#define DDRPHY_DX0BDLR6_PDRBD_MASK (0x3F00U)
21041#define DDRPHY_DX0BDLR6_PDRBD_SHIFT (8U)
21042/*! PDRBD - Power down receiver Bit Delay
21043 */
21044#define DDRPHY_DX0BDLR6_PDRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR6_PDRBD_SHIFT)) & DDRPHY_DX0BDLR6_PDRBD_MASK)
21045#define DDRPHY_DX0BDLR6_RESERVED_15_14_MASK (0xC000U)
21046#define DDRPHY_DX0BDLR6_RESERVED_15_14_SHIFT (14U)
21047/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
21048 */
21049#define DDRPHY_DX0BDLR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR6_RESERVED_15_14_MASK)
21050#define DDRPHY_DX0BDLR6_TERBD_MASK (0x3F0000U)
21051#define DDRPHY_DX0BDLR6_TERBD_SHIFT (16U)
21052/*! TERBD - Termination Enable Bit Delay
21053 */
21054#define DDRPHY_DX0BDLR6_TERBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR6_TERBD_SHIFT)) & DDRPHY_DX0BDLR6_TERBD_MASK)
21055#define DDRPHY_DX0BDLR6_RESERVED_31_22_MASK (0xFFC00000U)
21056#define DDRPHY_DX0BDLR6_RESERVED_31_22_SHIFT (22U)
21057/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
21058 */
21059#define DDRPHY_DX0BDLR6_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX0BDLR6_RESERVED_31_22_MASK)
21060/*! @} */
21061
21062/*! @name DX0BDLR7 - DATX8 n Bit Delay Line Register 7 */
21063/*! @{ */
21064#define DDRPHY_DX0BDLR7_RESERVED_5_0_MASK (0x3FU)
21065#define DDRPHY_DX0BDLR7_RESERVED_5_0_SHIFT (0U)
21066/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
21067 */
21068#define DDRPHY_DX0BDLR7_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX0BDLR7_RESERVED_5_0_MASK)
21069#define DDRPHY_DX0BDLR7_RESERVED_7_6_MASK (0xC0U)
21070#define DDRPHY_DX0BDLR7_RESERVED_7_6_SHIFT (6U)
21071/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
21072 */
21073#define DDRPHY_DX0BDLR7_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR7_RESERVED_7_6_MASK)
21074#define DDRPHY_DX0BDLR7_RESERVED_13_8_MASK (0x3F00U)
21075#define DDRPHY_DX0BDLR7_RESERVED_13_8_SHIFT (8U)
21076/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
21077 */
21078#define DDRPHY_DX0BDLR7_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX0BDLR7_RESERVED_13_8_MASK)
21079#define DDRPHY_DX0BDLR7_RESERVED_15_14_MASK (0xC000U)
21080#define DDRPHY_DX0BDLR7_RESERVED_15_14_SHIFT (14U)
21081/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
21082 */
21083#define DDRPHY_DX0BDLR7_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR7_RESERVED_15_14_MASK)
21084#define DDRPHY_DX0BDLR7_RESERVED_21_16_MASK (0x3F0000U)
21085#define DDRPHY_DX0BDLR7_RESERVED_21_16_SHIFT (16U)
21086/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
21087 */
21088#define DDRPHY_DX0BDLR7_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX0BDLR7_RESERVED_21_16_MASK)
21089#define DDRPHY_DX0BDLR7_RESERVED_31_22_MASK (0xFFC00000U)
21090#define DDRPHY_DX0BDLR7_RESERVED_31_22_SHIFT (22U)
21091/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
21092 */
21093#define DDRPHY_DX0BDLR7_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX0BDLR7_RESERVED_31_22_MASK)
21094/*! @} */
21095
21096/*! @name DX0BDLR8 - DATX8 n Bit Delay Line Register 8 */
21097/*! @{ */
21098#define DDRPHY_DX0BDLR8_RESERVED_5_0_MASK (0x3FU)
21099#define DDRPHY_DX0BDLR8_RESERVED_5_0_SHIFT (0U)
21100/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
21101 */
21102#define DDRPHY_DX0BDLR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX0BDLR8_RESERVED_5_0_MASK)
21103#define DDRPHY_DX0BDLR8_RESERVED_7_6_MASK (0xC0U)
21104#define DDRPHY_DX0BDLR8_RESERVED_7_6_SHIFT (6U)
21105/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
21106 */
21107#define DDRPHY_DX0BDLR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR8_RESERVED_7_6_MASK)
21108#define DDRPHY_DX0BDLR8_RESERVED_13_8_MASK (0x3F00U)
21109#define DDRPHY_DX0BDLR8_RESERVED_13_8_SHIFT (8U)
21110/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
21111 */
21112#define DDRPHY_DX0BDLR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX0BDLR8_RESERVED_13_8_MASK)
21113#define DDRPHY_DX0BDLR8_RESERVED_15_14_MASK (0xC000U)
21114#define DDRPHY_DX0BDLR8_RESERVED_15_14_SHIFT (14U)
21115/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
21116 */
21117#define DDRPHY_DX0BDLR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR8_RESERVED_15_14_MASK)
21118#define DDRPHY_DX0BDLR8_RESERVED_21_16_MASK (0x3F0000U)
21119#define DDRPHY_DX0BDLR8_RESERVED_21_16_SHIFT (16U)
21120/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
21121 */
21122#define DDRPHY_DX0BDLR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX0BDLR8_RESERVED_21_16_MASK)
21123#define DDRPHY_DX0BDLR8_RESERVED_31_22_MASK (0xFFC00000U)
21124#define DDRPHY_DX0BDLR8_RESERVED_31_22_SHIFT (22U)
21125/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
21126 */
21127#define DDRPHY_DX0BDLR8_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX0BDLR8_RESERVED_31_22_MASK)
21128/*! @} */
21129
21130/*! @name DX0BDLR9 - DATX8 n Bit Delay Line Register 9 */
21131/*! @{ */
21132#define DDRPHY_DX0BDLR9_RESERVED_5_0_MASK (0x3FU)
21133#define DDRPHY_DX0BDLR9_RESERVED_5_0_SHIFT (0U)
21134/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
21135 */
21136#define DDRPHY_DX0BDLR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX0BDLR9_RESERVED_5_0_MASK)
21137#define DDRPHY_DX0BDLR9_RESERVED_7_6_MASK (0xC0U)
21138#define DDRPHY_DX0BDLR9_RESERVED_7_6_SHIFT (6U)
21139/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
21140 */
21141#define DDRPHY_DX0BDLR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX0BDLR9_RESERVED_7_6_MASK)
21142#define DDRPHY_DX0BDLR9_RESERVED_13_8_MASK (0x3F00U)
21143#define DDRPHY_DX0BDLR9_RESERVED_13_8_SHIFT (8U)
21144/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
21145 */
21146#define DDRPHY_DX0BDLR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX0BDLR9_RESERVED_13_8_MASK)
21147#define DDRPHY_DX0BDLR9_RESERVED_15_14_MASK (0xC000U)
21148#define DDRPHY_DX0BDLR9_RESERVED_15_14_SHIFT (14U)
21149/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
21150 */
21151#define DDRPHY_DX0BDLR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX0BDLR9_RESERVED_15_14_MASK)
21152#define DDRPHY_DX0BDLR9_RESERVED_21_16_MASK (0x3F0000U)
21153#define DDRPHY_DX0BDLR9_RESERVED_21_16_SHIFT (16U)
21154/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
21155 */
21156#define DDRPHY_DX0BDLR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX0BDLR9_RESERVED_21_16_MASK)
21157#define DDRPHY_DX0BDLR9_RESERVED_31_22_MASK (0xFFC00000U)
21158#define DDRPHY_DX0BDLR9_RESERVED_31_22_SHIFT (22U)
21159/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
21160 */
21161#define DDRPHY_DX0BDLR9_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX0BDLR9_RESERVED_31_22_MASK)
21162/*! @} */
21163
21164/*! @name DX0LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */
21165/*! @{ */
21166#define DDRPHY_DX0LCDLR0_WLD_MASK (0x1FFU)
21167#define DDRPHY_DX0LCDLR0_WLD_SHIFT (0U)
21168/*! WLD - Write Leveling Delay
21169 */
21170#define DDRPHY_DX0LCDLR0_WLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR0_WLD_SHIFT)) & DDRPHY_DX0LCDLR0_WLD_MASK)
21171#define DDRPHY_DX0LCDLR0_RESERVED_15_9_MASK (0xFE00U)
21172#define DDRPHY_DX0LCDLR0_RESERVED_15_9_SHIFT (9U)
21173/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
21174 */
21175#define DDRPHY_DX0LCDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX0LCDLR0_RESERVED_15_9_MASK)
21176#define DDRPHY_DX0LCDLR0_RESERVED_24_16_MASK (0x1FF0000U)
21177#define DDRPHY_DX0LCDLR0_RESERVED_24_16_SHIFT (16U)
21178/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
21179 */
21180#define DDRPHY_DX0LCDLR0_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX0LCDLR0_RESERVED_24_16_MASK)
21181#define DDRPHY_DX0LCDLR0_RESERVED_31_25_MASK (0xFE000000U)
21182#define DDRPHY_DX0LCDLR0_RESERVED_31_25_SHIFT (25U)
21183/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
21184 */
21185#define DDRPHY_DX0LCDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX0LCDLR0_RESERVED_31_25_MASK)
21186/*! @} */
21187
21188/*! @name DX0LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */
21189/*! @{ */
21190#define DDRPHY_DX0LCDLR1_WDQD_MASK (0x1FFU)
21191#define DDRPHY_DX0LCDLR1_WDQD_SHIFT (0U)
21192/*! WDQD - Write Data Delay
21193 */
21194#define DDRPHY_DX0LCDLR1_WDQD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR1_WDQD_SHIFT)) & DDRPHY_DX0LCDLR1_WDQD_MASK)
21195#define DDRPHY_DX0LCDLR1_RESERVED_15_9_MASK (0xFE00U)
21196#define DDRPHY_DX0LCDLR1_RESERVED_15_9_SHIFT (9U)
21197/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
21198 */
21199#define DDRPHY_DX0LCDLR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX0LCDLR1_RESERVED_15_9_MASK)
21200#define DDRPHY_DX0LCDLR1_RESERVED_24_16_MASK (0x1FF0000U)
21201#define DDRPHY_DX0LCDLR1_RESERVED_24_16_SHIFT (16U)
21202/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
21203 */
21204#define DDRPHY_DX0LCDLR1_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX0LCDLR1_RESERVED_24_16_MASK)
21205#define DDRPHY_DX0LCDLR1_RESERVED_31_25_MASK (0xFE000000U)
21206#define DDRPHY_DX0LCDLR1_RESERVED_31_25_SHIFT (25U)
21207/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
21208 */
21209#define DDRPHY_DX0LCDLR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX0LCDLR1_RESERVED_31_25_MASK)
21210/*! @} */
21211
21212/*! @name DX0LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */
21213/*! @{ */
21214#define DDRPHY_DX0LCDLR2_DQSGD_MASK (0x1FFU)
21215#define DDRPHY_DX0LCDLR2_DQSGD_SHIFT (0U)
21216/*! DQSGD - Read DQS Gating Delay
21217 */
21218#define DDRPHY_DX0LCDLR2_DQSGD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX0LCDLR2_DQSGD_MASK)
21219#define DDRPHY_DX0LCDLR2_RESERVED_15_9_MASK (0xFE00U)
21220#define DDRPHY_DX0LCDLR2_RESERVED_15_9_SHIFT (9U)
21221/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
21222 */
21223#define DDRPHY_DX0LCDLR2_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX0LCDLR2_RESERVED_15_9_MASK)
21224#define DDRPHY_DX0LCDLR2_RESERVED_24_16_MASK (0x1FF0000U)
21225#define DDRPHY_DX0LCDLR2_RESERVED_24_16_SHIFT (16U)
21226/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
21227 */
21228#define DDRPHY_DX0LCDLR2_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX0LCDLR2_RESERVED_24_16_MASK)
21229#define DDRPHY_DX0LCDLR2_RESERVED_31_25_MASK (0xFE000000U)
21230#define DDRPHY_DX0LCDLR2_RESERVED_31_25_SHIFT (25U)
21231/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
21232 */
21233#define DDRPHY_DX0LCDLR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX0LCDLR2_RESERVED_31_25_MASK)
21234/*! @} */
21235
21236/*! @name DX0LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */
21237/*! @{ */
21238#define DDRPHY_DX0LCDLR3_RDQSD_MASK (0x1FFU)
21239#define DDRPHY_DX0LCDLR3_RDQSD_SHIFT (0U)
21240/*! RDQSD - Read DQS Delay
21241 */
21242#define DDRPHY_DX0LCDLR3_RDQSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX0LCDLR3_RDQSD_MASK)
21243#define DDRPHY_DX0LCDLR3_RESERVED_15_9_MASK (0xFE00U)
21244#define DDRPHY_DX0LCDLR3_RESERVED_15_9_SHIFT (9U)
21245/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
21246 */
21247#define DDRPHY_DX0LCDLR3_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX0LCDLR3_RESERVED_15_9_MASK)
21248#define DDRPHY_DX0LCDLR3_RESERVED_24_16_MASK (0x1FF0000U)
21249#define DDRPHY_DX0LCDLR3_RESERVED_24_16_SHIFT (16U)
21250/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
21251 */
21252#define DDRPHY_DX0LCDLR3_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX0LCDLR3_RESERVED_24_16_MASK)
21253#define DDRPHY_DX0LCDLR3_RESERVED_31_25_MASK (0xFE000000U)
21254#define DDRPHY_DX0LCDLR3_RESERVED_31_25_SHIFT (25U)
21255/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
21256 */
21257#define DDRPHY_DX0LCDLR3_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX0LCDLR3_RESERVED_31_25_MASK)
21258/*! @} */
21259
21260/*! @name DX0LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */
21261/*! @{ */
21262#define DDRPHY_DX0LCDLR4_RDQSND_MASK (0x1FFU)
21263#define DDRPHY_DX0LCDLR4_RDQSND_SHIFT (0U)
21264/*! RDQSND - Read DQSN Delay
21265 */
21266#define DDRPHY_DX0LCDLR4_RDQSND(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX0LCDLR4_RDQSND_MASK)
21267#define DDRPHY_DX0LCDLR4_RESERVED_15_9_MASK (0xFE00U)
21268#define DDRPHY_DX0LCDLR4_RESERVED_15_9_SHIFT (9U)
21269/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
21270 */
21271#define DDRPHY_DX0LCDLR4_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX0LCDLR4_RESERVED_15_9_MASK)
21272#define DDRPHY_DX0LCDLR4_RESERVED_24_16_MASK (0x1FF0000U)
21273#define DDRPHY_DX0LCDLR4_RESERVED_24_16_SHIFT (16U)
21274/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
21275 */
21276#define DDRPHY_DX0LCDLR4_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX0LCDLR4_RESERVED_24_16_MASK)
21277#define DDRPHY_DX0LCDLR4_RESERVED_31_25_MASK (0xFE000000U)
21278#define DDRPHY_DX0LCDLR4_RESERVED_31_25_SHIFT (25U)
21279/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
21280 */
21281#define DDRPHY_DX0LCDLR4_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX0LCDLR4_RESERVED_31_25_MASK)
21282/*! @} */
21283
21284/*! @name DX0LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */
21285/*! @{ */
21286#define DDRPHY_DX0LCDLR5_DQSGSD_MASK (0x1FFU)
21287#define DDRPHY_DX0LCDLR5_DQSGSD_SHIFT (0U)
21288/*! DQSGSD - DQS Gating Status Delay
21289 */
21290#define DDRPHY_DX0LCDLR5_DQSGSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX0LCDLR5_DQSGSD_MASK)
21291#define DDRPHY_DX0LCDLR5_RESERVED_15_9_MASK (0xFE00U)
21292#define DDRPHY_DX0LCDLR5_RESERVED_15_9_SHIFT (9U)
21293/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
21294 */
21295#define DDRPHY_DX0LCDLR5_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX0LCDLR5_RESERVED_15_9_MASK)
21296#define DDRPHY_DX0LCDLR5_RESERVED_24_16_MASK (0x1FF0000U)
21297#define DDRPHY_DX0LCDLR5_RESERVED_24_16_SHIFT (16U)
21298/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
21299 */
21300#define DDRPHY_DX0LCDLR5_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX0LCDLR5_RESERVED_24_16_MASK)
21301#define DDRPHY_DX0LCDLR5_RESERVED_31_25_MASK (0xFE000000U)
21302#define DDRPHY_DX0LCDLR5_RESERVED_31_25_SHIFT (25U)
21303/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
21304 */
21305#define DDRPHY_DX0LCDLR5_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX0LCDLR5_RESERVED_31_25_MASK)
21306/*! @} */
21307
21308/*! @name DX0MDLR0 - DATX8 n Master Delay Line Register 0 */
21309/*! @{ */
21310#define DDRPHY_DX0MDLR0_IPRD_MASK (0x1FFU)
21311#define DDRPHY_DX0MDLR0_IPRD_SHIFT (0U)
21312/*! IPRD - Initial Period
21313 */
21314#define DDRPHY_DX0MDLR0_IPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0MDLR0_IPRD_SHIFT)) & DDRPHY_DX0MDLR0_IPRD_MASK)
21315#define DDRPHY_DX0MDLR0_RESERVED_15_9_MASK (0xFE00U)
21316#define DDRPHY_DX0MDLR0_RESERVED_15_9_SHIFT (9U)
21317/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
21318 */
21319#define DDRPHY_DX0MDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX0MDLR0_RESERVED_15_9_MASK)
21320#define DDRPHY_DX0MDLR0_TPRD_MASK (0x1FF0000U)
21321#define DDRPHY_DX0MDLR0_TPRD_SHIFT (16U)
21322/*! TPRD - Target Period
21323 */
21324#define DDRPHY_DX0MDLR0_TPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0MDLR0_TPRD_SHIFT)) & DDRPHY_DX0MDLR0_TPRD_MASK)
21325#define DDRPHY_DX0MDLR0_RESERVED_31_25_MASK (0xFE000000U)
21326#define DDRPHY_DX0MDLR0_RESERVED_31_25_SHIFT (25U)
21327/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
21328 */
21329#define DDRPHY_DX0MDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX0MDLR0_RESERVED_31_25_MASK)
21330/*! @} */
21331
21332/*! @name DX0MDLR1 - DATX8 n Master Delay Line Register 1 */
21333/*! @{ */
21334#define DDRPHY_DX0MDLR1_MDLD_MASK (0x1FFU)
21335#define DDRPHY_DX0MDLR1_MDLD_SHIFT (0U)
21336/*! MDLD - MDL Delay
21337 */
21338#define DDRPHY_DX0MDLR1_MDLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0MDLR1_MDLD_SHIFT)) & DDRPHY_DX0MDLR1_MDLD_MASK)
21339#define DDRPHY_DX0MDLR1_RESERVED_31_9_MASK (0xFFFFFE00U)
21340#define DDRPHY_DX0MDLR1_RESERVED_31_9_SHIFT (9U)
21341/*! RESERVED_31_9 - Reserved. Return zeroes on reads.
21342 */
21343#define DDRPHY_DX0MDLR1_RESERVED_31_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX0MDLR1_RESERVED_31_9_MASK)
21344/*! @} */
21345
21346/*! @name DX0GTR0 - DATX8 n General Timing Register 0 */
21347/*! @{ */
21348#define DDRPHY_DX0GTR0_DGSL_MASK (0x1FU)
21349#define DDRPHY_DX0GTR0_DGSL_SHIFT (0U)
21350/*! DGSL - DQS Gating System Latency
21351 */
21352#define DDRPHY_DX0GTR0_DGSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_DGSL_SHIFT)) & DDRPHY_DX0GTR0_DGSL_MASK)
21353#define DDRPHY_DX0GTR0_RESERVED_7_5_MASK (0xE0U)
21354#define DDRPHY_DX0GTR0_RESERVED_7_5_SHIFT (5U)
21355/*! RESERVED_7_5 - Reserved. Return zeroes on reads.
21356 */
21357#define DDRPHY_DX0GTR0_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX0GTR0_RESERVED_7_5_MASK)
21358#define DDRPHY_DX0GTR0_RESERVED_12_8_MASK (0x1F00U)
21359#define DDRPHY_DX0GTR0_RESERVED_12_8_SHIFT (8U)
21360/*! RESERVED_12_8 - Reserved. Caution, do not write to this register field.
21361 */
21362#define DDRPHY_DX0GTR0_RESERVED_12_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX0GTR0_RESERVED_12_8_MASK)
21363#define DDRPHY_DX0GTR0_RESERVED_15_13_MASK (0xE000U)
21364#define DDRPHY_DX0GTR0_RESERVED_15_13_SHIFT (13U)
21365/*! RESERVED_15_13 - Reserved. Return zeroes on reads.
21366 */
21367#define DDRPHY_DX0GTR0_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX0GTR0_RESERVED_15_13_MASK)
21368#define DDRPHY_DX0GTR0_WLSL_MASK (0xF0000U)
21369#define DDRPHY_DX0GTR0_WLSL_SHIFT (16U)
21370/*! WLSL - Write Leveling System Latency
21371 */
21372#define DDRPHY_DX0GTR0_WLSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_WLSL_SHIFT)) & DDRPHY_DX0GTR0_WLSL_MASK)
21373#define DDRPHY_DX0GTR0_RESERVED_23_20_MASK (0xF00000U)
21374#define DDRPHY_DX0GTR0_RESERVED_23_20_SHIFT (20U)
21375/*! RESERVED_23_20 - Reserved. Caution, do not write to this register field.
21376 */
21377#define DDRPHY_DX0GTR0_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX0GTR0_RESERVED_23_20_MASK)
21378#define DDRPHY_DX0GTR0_WDQSL_MASK (0x7000000U)
21379#define DDRPHY_DX0GTR0_WDQSL_SHIFT (24U)
21380/*! WDQSL - DQ Write Path Latency Pipeline
21381 */
21382#define DDRPHY_DX0GTR0_WDQSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_WDQSL_SHIFT)) & DDRPHY_DX0GTR0_WDQSL_MASK)
21383#define DDRPHY_DX0GTR0_RESERVED_31_24_MASK (0xF8000000U)
21384#define DDRPHY_DX0GTR0_RESERVED_31_24_SHIFT (27U)
21385/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
21386 */
21387#define DDRPHY_DX0GTR0_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX0GTR0_RESERVED_31_24_MASK)
21388/*! @} */
21389
21390/*! @name DX0RSR0 - DATX8 n Rank Status Register 0 */
21391/*! @{ */
21392#define DDRPHY_DX0RSR0_QSGERR_MASK (0xFFFFU)
21393#define DDRPHY_DX0RSR0_QSGERR_SHIFT (0U)
21394/*! QSGERR - DQS Gate Training Error
21395 */
21396#define DDRPHY_DX0RSR0_QSGERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR0_QSGERR_SHIFT)) & DDRPHY_DX0RSR0_QSGERR_MASK)
21397#define DDRPHY_DX0RSR0_RESERVED_31_16_MASK (0xFFFF0000U)
21398#define DDRPHY_DX0RSR0_RESERVED_31_16_SHIFT (16U)
21399/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
21400 */
21401#define DDRPHY_DX0RSR0_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX0RSR0_RESERVED_31_16_MASK)
21402/*! @} */
21403
21404/*! @name DX0RSR1 - DATX8 n Rank Status Register 1 */
21405/*! @{ */
21406#define DDRPHY_DX0RSR1_RDLVLERR_MASK (0xFFFFU)
21407#define DDRPHY_DX0RSR1_RDLVLERR_SHIFT (0U)
21408/*! RDLVLERR - Read Leveling Error
21409 */
21410#define DDRPHY_DX0RSR1_RDLVLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX0RSR1_RDLVLERR_MASK)
21411#define DDRPHY_DX0RSR1_RESERVED_31_16_MASK (0xFFFF0000U)
21412#define DDRPHY_DX0RSR1_RESERVED_31_16_SHIFT (16U)
21413/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
21414 */
21415#define DDRPHY_DX0RSR1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX0RSR1_RESERVED_31_16_MASK)
21416/*! @} */
21417
21418/*! @name DX0RSR2 - DATX8 n Rank Status Register 2 */
21419/*! @{ */
21420#define DDRPHY_DX0RSR2_WLAWN_MASK (0xFFFFU)
21421#define DDRPHY_DX0RSR2_WLAWN_SHIFT (0U)
21422/*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning
21423 */
21424#define DDRPHY_DX0RSR2_WLAWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR2_WLAWN_SHIFT)) & DDRPHY_DX0RSR2_WLAWN_MASK)
21425#define DDRPHY_DX0RSR2_RESERVED_31_16_MASK (0xFFFF0000U)
21426#define DDRPHY_DX0RSR2_RESERVED_31_16_SHIFT (16U)
21427/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
21428 */
21429#define DDRPHY_DX0RSR2_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX0RSR2_RESERVED_31_16_MASK)
21430/*! @} */
21431
21432/*! @name DX0RSR3 - DATX8 n Rank Status Register 3 */
21433/*! @{ */
21434#define DDRPHY_DX0RSR3_WLAERR_MASK (0xFFFFU)
21435#define DDRPHY_DX0RSR3_WLAERR_SHIFT (0U)
21436/*! WLAERR - Write Leveling Adjustment Error
21437 */
21438#define DDRPHY_DX0RSR3_WLAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR3_WLAERR_SHIFT)) & DDRPHY_DX0RSR3_WLAERR_MASK)
21439#define DDRPHY_DX0RSR3_RESERVED_31_16_MASK (0xFFFF0000U)
21440#define DDRPHY_DX0RSR3_RESERVED_31_16_SHIFT (16U)
21441/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
21442 */
21443#define DDRPHY_DX0RSR3_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX0RSR3_RESERVED_31_16_MASK)
21444/*! @} */
21445
21446/*! @name DX0GSR0 - DATX8 n General Status Register 0 */
21447/*! @{ */
21448#define DDRPHY_DX0GSR0_WDQCAL_MASK (0x1U)
21449#define DDRPHY_DX0GSR0_WDQCAL_SHIFT (0U)
21450/*! WDQCAL - Write DQ Calibration
21451 */
21452#define DDRPHY_DX0GSR0_WDQCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_WDQCAL_SHIFT)) & DDRPHY_DX0GSR0_WDQCAL_MASK)
21453#define DDRPHY_DX0GSR0_RDQSCAL_MASK (0x2U)
21454#define DDRPHY_DX0GSR0_RDQSCAL_SHIFT (1U)
21455/*! RDQSCAL - Read DQS Calibration
21456 */
21457#define DDRPHY_DX0GSR0_RDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX0GSR0_RDQSCAL_MASK)
21458#define DDRPHY_DX0GSR0_RDQSNCAL_MASK (0x4U)
21459#define DDRPHY_DX0GSR0_RDQSNCAL_SHIFT (2U)
21460/*! RDQSNCAL - Read DQS# Calibration
21461 */
21462#define DDRPHY_DX0GSR0_RDQSNCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX0GSR0_RDQSNCAL_MASK)
21463#define DDRPHY_DX0GSR0_GDQSCAL_MASK (0x8U)
21464#define DDRPHY_DX0GSR0_GDQSCAL_SHIFT (3U)
21465/*! GDQSCAL - Read DQS gating Calibration
21466 */
21467#define DDRPHY_DX0GSR0_GDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX0GSR0_GDQSCAL_MASK)
21468#define DDRPHY_DX0GSR0_WLCAL_MASK (0x10U)
21469#define DDRPHY_DX0GSR0_WLCAL_SHIFT (4U)
21470/*! WLCAL - Write Leveling Calibration
21471 */
21472#define DDRPHY_DX0GSR0_WLCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_WLCAL_SHIFT)) & DDRPHY_DX0GSR0_WLCAL_MASK)
21473#define DDRPHY_DX0GSR0_WLDONE_MASK (0x20U)
21474#define DDRPHY_DX0GSR0_WLDONE_SHIFT (5U)
21475/*! WLDONE - Write Leveling Done
21476 */
21477#define DDRPHY_DX0GSR0_WLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_WLDONE_SHIFT)) & DDRPHY_DX0GSR0_WLDONE_MASK)
21478#define DDRPHY_DX0GSR0_WLERR_MASK (0x40U)
21479#define DDRPHY_DX0GSR0_WLERR_SHIFT (6U)
21480/*! WLERR - Write Leveling Error
21481 */
21482#define DDRPHY_DX0GSR0_WLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_WLERR_SHIFT)) & DDRPHY_DX0GSR0_WLERR_MASK)
21483#define DDRPHY_DX0GSR0_WLPRD_MASK (0xFF80U)
21484#define DDRPHY_DX0GSR0_WLPRD_SHIFT (7U)
21485/*! WLPRD - Write Leveling Period
21486 */
21487#define DDRPHY_DX0GSR0_WLPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_WLPRD_SHIFT)) & DDRPHY_DX0GSR0_WLPRD_MASK)
21488#define DDRPHY_DX0GSR0_DPLOCK_MASK (0x10000U)
21489#define DDRPHY_DX0GSR0_DPLOCK_SHIFT (16U)
21490/*! DPLOCK - DATX8 PLL Lock
21491 */
21492#define DDRPHY_DX0GSR0_DPLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_DPLOCK_SHIFT)) & DDRPHY_DX0GSR0_DPLOCK_MASK)
21493#define DDRPHY_DX0GSR0_GDQSPRD_MASK (0x3FE0000U)
21494#define DDRPHY_DX0GSR0_GDQSPRD_SHIFT (17U)
21495/*! GDQSPRD - Read DQS gating Period
21496 */
21497#define DDRPHY_DX0GSR0_GDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX0GSR0_GDQSPRD_MASK)
21498#define DDRPHY_DX0GSR0_RESERVED_29_26_MASK (0x3C000000U)
21499#define DDRPHY_DX0GSR0_RESERVED_29_26_SHIFT (26U)
21500/*! RESERVED_29_26 - Reserved. Returns zeroes on reads.
21501 */
21502#define DDRPHY_DX0GSR0_RESERVED_29_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX0GSR0_RESERVED_29_26_MASK)
21503#define DDRPHY_DX0GSR0_WLDQ_MASK (0x40000000U)
21504#define DDRPHY_DX0GSR0_WLDQ_SHIFT (30U)
21505/*! WLDQ - Write Leveling DQ Status
21506 */
21507#define DDRPHY_DX0GSR0_WLDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_WLDQ_SHIFT)) & DDRPHY_DX0GSR0_WLDQ_MASK)
21508#define DDRPHY_DX0GSR0_RESERVED_31_MASK (0x80000000U)
21509#define DDRPHY_DX0GSR0_RESERVED_31_SHIFT (31U)
21510/*! RESERVED_31 - Reserved. Returns zeroes on reads.
21511 */
21512#define DDRPHY_DX0GSR0_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX0GSR0_RESERVED_31_MASK)
21513/*! @} */
21514
21515/*! @name DX0GSR1 - DATX8 n General Status Register 1 */
21516/*! @{ */
21517#define DDRPHY_DX0GSR1_DLTDONE_MASK (0x1U)
21518#define DDRPHY_DX0GSR1_DLTDONE_SHIFT (0U)
21519/*! DLTDONE - Delay Line Test Done
21520 */
21521#define DDRPHY_DX0GSR1_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR1_DLTDONE_SHIFT)) & DDRPHY_DX0GSR1_DLTDONE_MASK)
21522#define DDRPHY_DX0GSR1_DLTCODE_MASK (0x1FFFFFEU)
21523#define DDRPHY_DX0GSR1_DLTCODE_SHIFT (1U)
21524/*! DLTCODE - Delay Line Test Code
21525 */
21526#define DDRPHY_DX0GSR1_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR1_DLTCODE_SHIFT)) & DDRPHY_DX0GSR1_DLTCODE_MASK)
21527#define DDRPHY_DX0GSR1_RESERVED_31_25_MASK (0xFE000000U)
21528#define DDRPHY_DX0GSR1_RESERVED_31_25_SHIFT (25U)
21529/*! RESERVED_31_25 - Reserved. Returns zeroes on reads.
21530 */
21531#define DDRPHY_DX0GSR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX0GSR1_RESERVED_31_25_MASK)
21532/*! @} */
21533
21534/*! @name DX0GSR2 - DATX8 n General Status Register 2 */
21535/*! @{ */
21536#define DDRPHY_DX0GSR2_RDERR_MASK (0x1U)
21537#define DDRPHY_DX0GSR2_RDERR_SHIFT (0U)
21538/*! RDERR - Read Bit Deskew Error
21539 */
21540#define DDRPHY_DX0GSR2_RDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_RDERR_SHIFT)) & DDRPHY_DX0GSR2_RDERR_MASK)
21541#define DDRPHY_DX0GSR2_RDWN_MASK (0x2U)
21542#define DDRPHY_DX0GSR2_RDWN_SHIFT (1U)
21543/*! RDWN - Read Bit Deskew Warning
21544 */
21545#define DDRPHY_DX0GSR2_RDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_RDWN_SHIFT)) & DDRPHY_DX0GSR2_RDWN_MASK)
21546#define DDRPHY_DX0GSR2_WDERR_MASK (0x4U)
21547#define DDRPHY_DX0GSR2_WDERR_SHIFT (2U)
21548/*! WDERR - Write Bit Deskew Error
21549 */
21550#define DDRPHY_DX0GSR2_WDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_WDERR_SHIFT)) & DDRPHY_DX0GSR2_WDERR_MASK)
21551#define DDRPHY_DX0GSR2_WDWN_MASK (0x8U)
21552#define DDRPHY_DX0GSR2_WDWN_SHIFT (3U)
21553/*! WDWN - Write Bit Deskew Warning
21554 */
21555#define DDRPHY_DX0GSR2_WDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_WDWN_SHIFT)) & DDRPHY_DX0GSR2_WDWN_MASK)
21556#define DDRPHY_DX0GSR2_REERR_MASK (0x10U)
21557#define DDRPHY_DX0GSR2_REERR_SHIFT (4U)
21558/*! REERR - Read Eye Centering Error
21559 */
21560#define DDRPHY_DX0GSR2_REERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_REERR_SHIFT)) & DDRPHY_DX0GSR2_REERR_MASK)
21561#define DDRPHY_DX0GSR2_REWN_MASK (0x20U)
21562#define DDRPHY_DX0GSR2_REWN_SHIFT (5U)
21563/*! REWN - Read Eye Centering Warning
21564 */
21565#define DDRPHY_DX0GSR2_REWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_REWN_SHIFT)) & DDRPHY_DX0GSR2_REWN_MASK)
21566#define DDRPHY_DX0GSR2_WEERR_MASK (0x40U)
21567#define DDRPHY_DX0GSR2_WEERR_SHIFT (6U)
21568/*! WEERR - Write Eye Centering Error
21569 */
21570#define DDRPHY_DX0GSR2_WEERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_WEERR_SHIFT)) & DDRPHY_DX0GSR2_WEERR_MASK)
21571#define DDRPHY_DX0GSR2_WEWN_MASK (0x80U)
21572#define DDRPHY_DX0GSR2_WEWN_SHIFT (7U)
21573/*! WEWN - Write Eye Centering Warning
21574 */
21575#define DDRPHY_DX0GSR2_WEWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_WEWN_SHIFT)) & DDRPHY_DX0GSR2_WEWN_MASK)
21576#define DDRPHY_DX0GSR2_ESTAT_MASK (0xF00U)
21577#define DDRPHY_DX0GSR2_ESTAT_SHIFT (8U)
21578/*! ESTAT - Error Status
21579 */
21580#define DDRPHY_DX0GSR2_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_ESTAT_SHIFT)) & DDRPHY_DX0GSR2_ESTAT_MASK)
21581#define DDRPHY_DX0GSR2_DQS2DQERR_MASK (0xFF000U)
21582#define DDRPHY_DX0GSR2_DQS2DQERR_SHIFT (12U)
21583/*! DQS2DQERR - Write DQS2DQ Training Error
21584 */
21585#define DDRPHY_DX0GSR2_DQS2DQERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX0GSR2_DQS2DQERR_MASK)
21586#define DDRPHY_DX0GSR2_SRDERR_MASK (0x100000U)
21587#define DDRPHY_DX0GSR2_SRDERR_SHIFT (20U)
21588/*! SRDERR - Static Read Error
21589 */
21590#define DDRPHY_DX0GSR2_SRDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_SRDERR_SHIFT)) & DDRPHY_DX0GSR2_SRDERR_MASK)
21591#define DDRPHY_DX0GSR2_RESERVED_21_MASK (0x200000U)
21592#define DDRPHY_DX0GSR2_RESERVED_21_SHIFT (21U)
21593/*! RESERVED_21 - Reserved. Return zeroes on reads.
21594 */
21595#define DDRPHY_DX0GSR2_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX0GSR2_RESERVED_21_MASK)
21596#define DDRPHY_DX0GSR2_GSDQSCAL_MASK (0x400000U)
21597#define DDRPHY_DX0GSR2_GSDQSCAL_SHIFT (22U)
21598/*! GSDQSCAL - Read DQS Gating Status Calibration
21599 */
21600#define DDRPHY_DX0GSR2_GSDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX0GSR2_GSDQSCAL_MASK)
21601#define DDRPHY_DX0GSR2_GSDQSPRD_MASK (0xFF800000U)
21602#define DDRPHY_DX0GSR2_GSDQSPRD_SHIFT (23U)
21603/*! GSDQSPRD - Read DQS gating Status Period
21604 */
21605#define DDRPHY_DX0GSR2_GSDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX0GSR2_GSDQSPRD_MASK)
21606/*! @} */
21607
21608/*! @name DX0GSR3 - DATX8 n General Status Register 3 */
21609/*! @{ */
21610#define DDRPHY_DX0GSR3_SRDPC_MASK (0x3U)
21611#define DDRPHY_DX0GSR3_SRDPC_SHIFT (0U)
21612/*! SRDPC - Static Read Delay Pass Count
21613 */
21614#define DDRPHY_DX0GSR3_SRDPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_SRDPC_SHIFT)) & DDRPHY_DX0GSR3_SRDPC_MASK)
21615#define DDRPHY_DX0GSR3_RESERVED_7_2_MASK (0xFCU)
21616#define DDRPHY_DX0GSR3_RESERVED_7_2_SHIFT (2U)
21617/*! RESERVED_7_2 - Reserved. Return zeroes on reads.
21618 */
21619#define DDRPHY_DX0GSR3_RESERVED_7_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX0GSR3_RESERVED_7_2_MASK)
21620#define DDRPHY_DX0GSR3_HVERR_MASK (0xF00U)
21621#define DDRPHY_DX0GSR3_HVERR_SHIFT (8U)
21622/*! HVERR - Host VREF Training Error
21623 */
21624#define DDRPHY_DX0GSR3_HVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_HVERR_SHIFT)) & DDRPHY_DX0GSR3_HVERR_MASK)
21625#define DDRPHY_DX0GSR3_HVWRN_MASK (0xF000U)
21626#define DDRPHY_DX0GSR3_HVWRN_SHIFT (12U)
21627/*! HVWRN - Host VREF Training Warning
21628 */
21629#define DDRPHY_DX0GSR3_HVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_HVWRN_SHIFT)) & DDRPHY_DX0GSR3_HVWRN_MASK)
21630#define DDRPHY_DX0GSR3_DVERR_MASK (0xF0000U)
21631#define DDRPHY_DX0GSR3_DVERR_SHIFT (16U)
21632/*! DVERR - DRAM VREF Training Error
21633 */
21634#define DDRPHY_DX0GSR3_DVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_DVERR_SHIFT)) & DDRPHY_DX0GSR3_DVERR_MASK)
21635#define DDRPHY_DX0GSR3_DVWRN_MASK (0xF00000U)
21636#define DDRPHY_DX0GSR3_DVWRN_SHIFT (20U)
21637/*! DVWRN - DRAM VREF Training Warning
21638 */
21639#define DDRPHY_DX0GSR3_DVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_DVWRN_SHIFT)) & DDRPHY_DX0GSR3_DVWRN_MASK)
21640#define DDRPHY_DX0GSR3_ESTAT_MASK (0x7000000U)
21641#define DDRPHY_DX0GSR3_ESTAT_SHIFT (24U)
21642/*! ESTAT - VREF Training Error Status Code
21643 */
21644#define DDRPHY_DX0GSR3_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_ESTAT_SHIFT)) & DDRPHY_DX0GSR3_ESTAT_MASK)
21645#define DDRPHY_DX0GSR3_RESERVED_31_27_MASK (0xF8000000U)
21646#define DDRPHY_DX0GSR3_RESERVED_31_27_SHIFT (27U)
21647/*! RESERVED_31_27 - Reserved. Return zeroes on reads.
21648 */
21649#define DDRPHY_DX0GSR3_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX0GSR3_RESERVED_31_27_MASK)
21650/*! @} */
21651
21652/*! @name DX0GSR4 - DATX8 n General Status Register 4 */
21653/*! @{ */
21654#define DDRPHY_DX0GSR4_RESERVED_0_MASK (0x1U)
21655#define DDRPHY_DX0GSR4_RESERVED_0_SHIFT (0U)
21656/*! RESERVED_0 - Reserved. Return zeroes on reads.
21657 */
21658#define DDRPHY_DX0GSR4_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_0_MASK)
21659#define DDRPHY_DX0GSR4_RESERVED_1_MASK (0x2U)
21660#define DDRPHY_DX0GSR4_RESERVED_1_SHIFT (1U)
21661/*! RESERVED_1 - Reserved. Return zeroes on reads.
21662 */
21663#define DDRPHY_DX0GSR4_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_1_MASK)
21664#define DDRPHY_DX0GSR4_RESERVED_2_MASK (0x4U)
21665#define DDRPHY_DX0GSR4_RESERVED_2_SHIFT (2U)
21666/*! RESERVED_2 - Reserved. Return zeroes on reads.
21667 */
21668#define DDRPHY_DX0GSR4_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_2_MASK)
21669#define DDRPHY_DX0GSR4_RESERVED_3_MASK (0x8U)
21670#define DDRPHY_DX0GSR4_RESERVED_3_SHIFT (3U)
21671/*! RESERVED_3 - Reserved. Return zeroes on reads.
21672 */
21673#define DDRPHY_DX0GSR4_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_3_MASK)
21674#define DDRPHY_DX0GSR4_RESERVED_4_MASK (0x10U)
21675#define DDRPHY_DX0GSR4_RESERVED_4_SHIFT (4U)
21676/*! RESERVED_4 - Reserved. Return zeroes on reads.
21677 */
21678#define DDRPHY_DX0GSR4_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_4_MASK)
21679#define DDRPHY_DX0GSR4_RESERVED_5_MASK (0x20U)
21680#define DDRPHY_DX0GSR4_RESERVED_5_SHIFT (5U)
21681/*! RESERVED_5 - Reserved. Return zeroes on reads.
21682 */
21683#define DDRPHY_DX0GSR4_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_5_MASK)
21684#define DDRPHY_DX0GSR4_RESERVED_6_MASK (0x40U)
21685#define DDRPHY_DX0GSR4_RESERVED_6_SHIFT (6U)
21686/*! RESERVED_6 - Reserved. Return zeroes on reads.
21687 */
21688#define DDRPHY_DX0GSR4_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_6_MASK)
21689#define DDRPHY_DX0GSR4_RESERVED_15_7_MASK (0xFF80U)
21690#define DDRPHY_DX0GSR4_RESERVED_15_7_SHIFT (7U)
21691/*! RESERVED_15_7 - Reserved. Return zeroes on reads.
21692 */
21693#define DDRPHY_DX0GSR4_RESERVED_15_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_15_7_MASK)
21694#define DDRPHY_DX0GSR4_RESERVED_16_MASK (0x10000U)
21695#define DDRPHY_DX0GSR4_RESERVED_16_SHIFT (16U)
21696/*! RESERVED_16 - Reserved. Return zeroes on reads.
21697 */
21698#define DDRPHY_DX0GSR4_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_16_MASK)
21699#define DDRPHY_DX0GSR4_RESERVED_25_17_MASK (0x3FE0000U)
21700#define DDRPHY_DX0GSR4_RESERVED_25_17_SHIFT (17U)
21701/*! RESERVED_25_17 - Reserved. Return zeroes on reads.
21702 */
21703#define DDRPHY_DX0GSR4_RESERVED_25_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_25_17_MASK)
21704#define DDRPHY_DX0GSR4_RESERVED_31_26_MASK (0xFC000000U)
21705#define DDRPHY_DX0GSR4_RESERVED_31_26_SHIFT (26U)
21706/*! RESERVED_31_26 - Reserved. Returns zeroes on reads.
21707 */
21708#define DDRPHY_DX0GSR4_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX0GSR4_RESERVED_31_26_MASK)
21709/*! @} */
21710
21711/*! @name DX0GSR5 - DATX8 n General Status Register 5 */
21712/*! @{ */
21713#define DDRPHY_DX0GSR5_RESERVED_0_MASK (0x1U)
21714#define DDRPHY_DX0GSR5_RESERVED_0_SHIFT (0U)
21715/*! RESERVED_0 - Reserved. Return zeroes on reads.
21716 */
21717#define DDRPHY_DX0GSR5_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_0_MASK)
21718#define DDRPHY_DX0GSR5_RESERVED_1_MASK (0x2U)
21719#define DDRPHY_DX0GSR5_RESERVED_1_SHIFT (1U)
21720/*! RESERVED_1 - Reserved. Return zeroes on reads.
21721 */
21722#define DDRPHY_DX0GSR5_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_1_MASK)
21723#define DDRPHY_DX0GSR5_RESERVED_2_MASK (0x4U)
21724#define DDRPHY_DX0GSR5_RESERVED_2_SHIFT (2U)
21725/*! RESERVED_2 - Reserved. Return zeroes on reads.
21726 */
21727#define DDRPHY_DX0GSR5_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_2_MASK)
21728#define DDRPHY_DX0GSR5_RESERVED_3_MASK (0x8U)
21729#define DDRPHY_DX0GSR5_RESERVED_3_SHIFT (3U)
21730/*! RESERVED_3 - Reserved. Return zeroes on reads.
21731 */
21732#define DDRPHY_DX0GSR5_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_3_MASK)
21733#define DDRPHY_DX0GSR5_RESERVED_4_MASK (0x10U)
21734#define DDRPHY_DX0GSR5_RESERVED_4_SHIFT (4U)
21735/*! RESERVED_4 - Reserved. Return zeroes on reads.
21736 */
21737#define DDRPHY_DX0GSR5_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_4_MASK)
21738#define DDRPHY_DX0GSR5_RESERVED_5_MASK (0x20U)
21739#define DDRPHY_DX0GSR5_RESERVED_5_SHIFT (5U)
21740/*! RESERVED_5 - Reserved. Return zeroes on reads.
21741 */
21742#define DDRPHY_DX0GSR5_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_5_MASK)
21743#define DDRPHY_DX0GSR5_RESERVED_6_MASK (0x40U)
21744#define DDRPHY_DX0GSR5_RESERVED_6_SHIFT (6U)
21745/*! RESERVED_6 - Reserved. Return zeroes on reads.
21746 */
21747#define DDRPHY_DX0GSR5_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_6_MASK)
21748#define DDRPHY_DX0GSR5_RESERVED_7_MASK (0x80U)
21749#define DDRPHY_DX0GSR5_RESERVED_7_SHIFT (7U)
21750/*! RESERVED_7 - Reserved. Return zeroes on reads.
21751 */
21752#define DDRPHY_DX0GSR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_7_MASK)
21753#define DDRPHY_DX0GSR5_RESERVED_11_8_MASK (0xF00U)
21754#define DDRPHY_DX0GSR5_RESERVED_11_8_SHIFT (8U)
21755/*! RESERVED_11_8 - Reserved. Return zeroes on reads.
21756 */
21757#define DDRPHY_DX0GSR5_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_11_8_MASK)
21758#define DDRPHY_DX0GSR5_RESERVED_19_12_MASK (0xFF000U)
21759#define DDRPHY_DX0GSR5_RESERVED_19_12_SHIFT (12U)
21760/*! RESERVED_19_12 - Reserved. Return zeroes on reads.
21761 */
21762#define DDRPHY_DX0GSR5_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_19_12_MASK)
21763#define DDRPHY_DX0GSR5_RESERVED_20_MASK (0x100000U)
21764#define DDRPHY_DX0GSR5_RESERVED_20_SHIFT (20U)
21765/*! RESERVED_20 - Reserved. Return zeroes on reads.
21766 */
21767#define DDRPHY_DX0GSR5_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_20_MASK)
21768#define DDRPHY_DX0GSR5_RESERVED_21_MASK (0x200000U)
21769#define DDRPHY_DX0GSR5_RESERVED_21_SHIFT (21U)
21770/*! RESERVED_21 - Reserved. Return zeroes on reads.
21771 */
21772#define DDRPHY_DX0GSR5_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_21_MASK)
21773#define DDRPHY_DX0GSR5_RESERVED_22_MASK (0x400000U)
21774#define DDRPHY_DX0GSR5_RESERVED_22_SHIFT (22U)
21775/*! RESERVED_22 - Reserved. Return zeroes on reads.
21776 */
21777#define DDRPHY_DX0GSR5_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_22_MASK)
21778#define DDRPHY_DX0GSR5_RESERVED_31_23_MASK (0xFF800000U)
21779#define DDRPHY_DX0GSR5_RESERVED_31_23_SHIFT (23U)
21780/*! RESERVED_31_23 - Reserved. Return zeroes on reads.
21781 */
21782#define DDRPHY_DX0GSR5_RESERVED_31_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX0GSR5_RESERVED_31_23_MASK)
21783/*! @} */
21784
21785/*! @name DX0GSR6 - DATX8 n General Status Register 6 */
21786/*! @{ */
21787#define DDRPHY_DX0GSR6_RESERVED_1_0_MASK (0x3U)
21788#define DDRPHY_DX0GSR6_RESERVED_1_0_SHIFT (0U)
21789/*! RESERVED_1_0 - Reserved. Return zeroes on reads.
21790 */
21791#define DDRPHY_DX0GSR6_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_1_0_MASK)
21792#define DDRPHY_DX0GSR6_RESERVED_3_2_MASK (0xCU)
21793#define DDRPHY_DX0GSR6_RESERVED_3_2_SHIFT (2U)
21794/*! RESERVED_3_2 - Reserved. Return zeroes on reads.
21795 */
21796#define DDRPHY_DX0GSR6_RESERVED_3_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_3_2_MASK)
21797#define DDRPHY_DX0GSR6_RESERVED_7_4_MASK (0xF0U)
21798#define DDRPHY_DX0GSR6_RESERVED_7_4_SHIFT (4U)
21799/*! RESERVED_7_4 - Reserved. Return zeroes on reads.
21800 */
21801#define DDRPHY_DX0GSR6_RESERVED_7_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_7_4_MASK)
21802#define DDRPHY_DX0GSR6_RESERVED_11_8_MASK (0xF00U)
21803#define DDRPHY_DX0GSR6_RESERVED_11_8_SHIFT (8U)
21804/*! RESERVED_11_8 - Reserved. Return zeroes on reads.
21805 */
21806#define DDRPHY_DX0GSR6_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_11_8_MASK)
21807#define DDRPHY_DX0GSR6_RESERVED_15_12_MASK (0xF000U)
21808#define DDRPHY_DX0GSR6_RESERVED_15_12_SHIFT (12U)
21809/*! RESERVED_15_12 - Reserved. Return zeroes on reads.
21810 */
21811#define DDRPHY_DX0GSR6_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_15_12_MASK)
21812#define DDRPHY_DX0GSR6_RESERVED_19_15_MASK (0xF0000U)
21813#define DDRPHY_DX0GSR6_RESERVED_19_15_SHIFT (16U)
21814/*! RESERVED_19_15 - Reserved. Return zeroes on reads.
21815 */
21816#define DDRPHY_DX0GSR6_RESERVED_19_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_19_15_MASK)
21817#define DDRPHY_DX0GSR6_RESERVED_23_20_MASK (0xF00000U)
21818#define DDRPHY_DX0GSR6_RESERVED_23_20_SHIFT (20U)
21819/*! RESERVED_23_20 - Reserved. Return zeroes on reads.
21820 */
21821#define DDRPHY_DX0GSR6_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_23_20_MASK)
21822#define DDRPHY_DX0GSR6_RESERVED_31_24_MASK (0xFF000000U)
21823#define DDRPHY_DX0GSR6_RESERVED_31_24_SHIFT (24U)
21824/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
21825 */
21826#define DDRPHY_DX0GSR6_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX0GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX0GSR6_RESERVED_31_24_MASK)
21827/*! @} */
21828
21829/*! @name DX1GCR0 - DATX8 n General Configuration Register 0 */
21830/*! @{ */
21831#define DDRPHY_DX1GCR0_RESERVED_1_0_MASK (0x3U)
21832#define DDRPHY_DX1GCR0_RESERVED_1_0_SHIFT (0U)
21833/*! RESERVED_1_0 - Reserved. Return zeroes on reads.
21834 */
21835#define DDRPHY_DX1GCR0_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX1GCR0_RESERVED_1_0_MASK)
21836#define DDRPHY_DX1GCR0_DQSGOE_MASK (0x4U)
21837#define DDRPHY_DX1GCR0_DQSGOE_SHIFT (2U)
21838/*! DQSGOE - DQSG Output Enable
21839 */
21840#define DDRPHY_DX1GCR0_DQSGOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSGOE_SHIFT)) & DDRPHY_DX1GCR0_DQSGOE_MASK)
21841#define DDRPHY_DX1GCR0_DQSGODT_MASK (0x8U)
21842#define DDRPHY_DX1GCR0_DQSGODT_SHIFT (3U)
21843/*! DQSGODT - DQSG On-Die Termination
21844 */
21845#define DDRPHY_DX1GCR0_DQSGODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSGODT_SHIFT)) & DDRPHY_DX1GCR0_DQSGODT_MASK)
21846#define DDRPHY_DX1GCR0_RESERVED_4_MASK (0x10U)
21847#define DDRPHY_DX1GCR0_RESERVED_4_SHIFT (4U)
21848/*! RESERVED_4 - Reserved. Return zeroes on reads.
21849 */
21850#define DDRPHY_DX1GCR0_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX1GCR0_RESERVED_4_MASK)
21851#define DDRPHY_DX1GCR0_DQSGPDR_MASK (0x20U)
21852#define DDRPHY_DX1GCR0_DQSGPDR_SHIFT (5U)
21853/*! DQSGPDR - DQSG Power Down Receiver
21854 */
21855#define DDRPHY_DX1GCR0_DQSGPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX1GCR0_DQSGPDR_MASK)
21856#define DDRPHY_DX1GCR0_DQSRPD_MASK (0x40U)
21857#define DDRPHY_DX1GCR0_DQSRPD_SHIFT (6U)
21858/*! DQSRPD - DQSR Power Down
21859 */
21860#define DDRPHY_DX1GCR0_DQSRPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSRPD_SHIFT)) & DDRPHY_DX1GCR0_DQSRPD_MASK)
21861#define DDRPHY_DX1GCR0_CPDRSHFT_MASK (0x180U)
21862#define DDRPHY_DX1GCR0_CPDRSHFT_SHIFT (7U)
21863/*! CPDRSHFT - Configurable PDR Phase Shift
21864 */
21865#define DDRPHY_DX1GCR0_CPDRSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX1GCR0_CPDRSHFT_MASK)
21866#define DDRPHY_DX1GCR0_RTTOH_MASK (0x600U)
21867#define DDRPHY_DX1GCR0_RTTOH_SHIFT (9U)
21868/*! RTTOH - RTT Output Hold
21869 */
21870#define DDRPHY_DX1GCR0_RTTOH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_RTTOH_SHIFT)) & DDRPHY_DX1GCR0_RTTOH_MASK)
21871#define DDRPHY_DX1GCR0_RTTOAL_MASK (0x800U)
21872#define DDRPHY_DX1GCR0_RTTOAL_SHIFT (11U)
21873/*! RTTOAL - RTT On Additive Latency
21874 */
21875#define DDRPHY_DX1GCR0_RTTOAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_RTTOAL_SHIFT)) & DDRPHY_DX1GCR0_RTTOAL_MASK)
21876#define DDRPHY_DX1GCR0_DQSSEPDR_MASK (0x1000U)
21877#define DDRPHY_DX1GCR0_DQSSEPDR_SHIFT (12U)
21878/*! DQSSEPDR - DQSSE Power Down Receiver
21879 */
21880#define DDRPHY_DX1GCR0_DQSSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX1GCR0_DQSSEPDR_MASK)
21881#define DDRPHY_DX1GCR0_DQSNSEPDR_MASK (0x2000U)
21882#define DDRPHY_DX1GCR0_DQSNSEPDR_SHIFT (13U)
21883/*! DQSNSEPDR - DQSNSE Power Down Receiver
21884 */
21885#define DDRPHY_DX1GCR0_DQSNSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX1GCR0_DQSNSEPDR_MASK)
21886#define DDRPHY_DX1GCR0_RESERVED_19_14_MASK (0xFC000U)
21887#define DDRPHY_DX1GCR0_RESERVED_19_14_SHIFT (14U)
21888/*! RESERVED_19_14 - Reserved. Return zeroes on reads.
21889 */
21890#define DDRPHY_DX1GCR0_RESERVED_19_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX1GCR0_RESERVED_19_14_MASK)
21891#define DDRPHY_DX1GCR0_RDDLY_MASK (0xF00000U)
21892#define DDRPHY_DX1GCR0_RDDLY_SHIFT (20U)
21893/*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
21894 */
21895#define DDRPHY_DX1GCR0_RDDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_RDDLY_SHIFT)) & DDRPHY_DX1GCR0_RDDLY_MASK)
21896#define DDRPHY_DX1GCR0_DQSDCC_MASK (0xF000000U)
21897#define DDRPHY_DX1GCR0_DQSDCC_SHIFT (24U)
21898/*! DQSDCC - DQS Duty Cycle Correction
21899 */
21900#define DDRPHY_DX1GCR0_DQSDCC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_DQSDCC_SHIFT)) & DDRPHY_DX1GCR0_DQSDCC_MASK)
21901#define DDRPHY_DX1GCR0_CODTSHFT_MASK (0x30000000U)
21902#define DDRPHY_DX1GCR0_CODTSHFT_SHIFT (28U)
21903/*! CODTSHFT - Configurable ODT(TE) Phase Shift
21904 */
21905#define DDRPHY_DX1GCR0_CODTSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX1GCR0_CODTSHFT_MASK)
21906#define DDRPHY_DX1GCR0_MDLEN_MASK (0x40000000U)
21907#define DDRPHY_DX1GCR0_MDLEN_SHIFT (30U)
21908/*! MDLEN - Master Delay Line Enable
21909 */
21910#define DDRPHY_DX1GCR0_MDLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_MDLEN_SHIFT)) & DDRPHY_DX1GCR0_MDLEN_MASK)
21911#define DDRPHY_DX1GCR0_CALBYP_MASK (0x80000000U)
21912#define DDRPHY_DX1GCR0_CALBYP_SHIFT (31U)
21913/*! CALBYP - Calibration Bypass
21914 */
21915#define DDRPHY_DX1GCR0_CALBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR0_CALBYP_SHIFT)) & DDRPHY_DX1GCR0_CALBYP_MASK)
21916/*! @} */
21917
21918/*! @name DX1GCR1 - DATX8 n General Configuration Register 1 */
21919/*! @{ */
21920#define DDRPHY_DX1GCR1_DQEN_MASK (0xFFU)
21921#define DDRPHY_DX1GCR1_DQEN_SHIFT (0U)
21922/*! DQEN - Enables DQ corresponding to each bit in a byte
21923 */
21924#define DDRPHY_DX1GCR1_DQEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_DQEN_SHIFT)) & DDRPHY_DX1GCR1_DQEN_MASK)
21925#define DDRPHY_DX1GCR1_DMEN_MASK (0x100U)
21926#define DDRPHY_DX1GCR1_DMEN_SHIFT (8U)
21927/*! DMEN - Enables DM pin in a byte lane
21928 */
21929#define DDRPHY_DX1GCR1_DMEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_DMEN_SHIFT)) & DDRPHY_DX1GCR1_DMEN_MASK)
21930#define DDRPHY_DX1GCR1_DSEN_MASK (0x200U)
21931#define DDRPHY_DX1GCR1_DSEN_SHIFT (9U)
21932/*! DSEN - Enables Write Data strobe in a byte lane
21933 */
21934#define DDRPHY_DX1GCR1_DSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_DSEN_SHIFT)) & DDRPHY_DX1GCR1_DSEN_MASK)
21935#define DDRPHY_DX1GCR1_TEEN_MASK (0x400U)
21936#define DDRPHY_DX1GCR1_TEEN_SHIFT (10U)
21937/*! TEEN - Enables ODT/TE in a byte lane
21938 */
21939#define DDRPHY_DX1GCR1_TEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_TEEN_SHIFT)) & DDRPHY_DX1GCR1_TEEN_MASK)
21940#define DDRPHY_DX1GCR1_PDREN_MASK (0x800U)
21941#define DDRPHY_DX1GCR1_PDREN_SHIFT (11U)
21942/*! PDREN - Enables PDR in a byte lane
21943 */
21944#define DDRPHY_DX1GCR1_PDREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_PDREN_SHIFT)) & DDRPHY_DX1GCR1_PDREN_MASK)
21945#define DDRPHY_DX1GCR1_OEEN_MASK (0x1000U)
21946#define DDRPHY_DX1GCR1_OEEN_SHIFT (12U)
21947/*! OEEN - Enables Read Data Strobe in a byte lane
21948 */
21949#define DDRPHY_DX1GCR1_OEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_OEEN_SHIFT)) & DDRPHY_DX1GCR1_OEEN_MASK)
21950#define DDRPHY_DX1GCR1_QSSEL_MASK (0x2000U)
21951#define DDRPHY_DX1GCR1_QSSEL_SHIFT (13U)
21952/*! QSSEL - Select the delayed or non-delayed read data strobe
21953 */
21954#define DDRPHY_DX1GCR1_QSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_QSSEL_SHIFT)) & DDRPHY_DX1GCR1_QSSEL_MASK)
21955#define DDRPHY_DX1GCR1_QSNSEL_MASK (0x4000U)
21956#define DDRPHY_DX1GCR1_QSNSEL_SHIFT (14U)
21957/*! QSNSEL - Select the delayed or non-delayed read data strobe #
21958 */
21959#define DDRPHY_DX1GCR1_QSNSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_QSNSEL_SHIFT)) & DDRPHY_DX1GCR1_QSNSEL_MASK)
21960#define DDRPHY_DX1GCR1_RESERVED_15_MASK (0x8000U)
21961#define DDRPHY_DX1GCR1_RESERVED_15_SHIFT (15U)
21962/*! RESERVED_15 - Reserved. Returns zeroes on reads.
21963 */
21964#define DDRPHY_DX1GCR1_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX1GCR1_RESERVED_15_MASK)
21965#define DDRPHY_DX1GCR1_DXPDRMODE_MASK (0xFFFF0000U)
21966#define DDRPHY_DX1GCR1_DXPDRMODE_SHIFT (16U)
21967/*! DXPDRMODE - Enables the PDR mode for DQ[7:0]
21968 */
21969#define DDRPHY_DX1GCR1_DXPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX1GCR1_DXPDRMODE_MASK)
21970/*! @} */
21971
21972/*! @name DX1GCR2 - DATX8 n General Configuration Register 2 */
21973/*! @{ */
21974#define DDRPHY_DX1GCR2_DXTEMODE_MASK (0xFFFFU)
21975#define DDRPHY_DX1GCR2_DXTEMODE_SHIFT (0U)
21976/*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0]
21977 */
21978#define DDRPHY_DX1GCR2_DXTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX1GCR2_DXTEMODE_MASK)
21979#define DDRPHY_DX1GCR2_DXOEMODE_MASK (0xFFFF0000U)
21980#define DDRPHY_DX1GCR2_DXOEMODE_SHIFT (16U)
21981/*! DXOEMODE - Enables the OE mode values for DQ[7:0]
21982 */
21983#define DDRPHY_DX1GCR2_DXOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX1GCR2_DXOEMODE_MASK)
21984/*! @} */
21985
21986/*! @name DX1GCR3 - DATX8 n General Configuration Register 3 */
21987/*! @{ */
21988#define DDRPHY_DX1GCR3_WDMBVT_MASK (0x1U)
21989#define DDRPHY_DX1GCR3_WDMBVT_SHIFT (0U)
21990/*! WDMBVT - Write Data Mask BDL VT Compensation
21991 */
21992#define DDRPHY_DX1GCR3_WDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_WDMBVT_SHIFT)) & DDRPHY_DX1GCR3_WDMBVT_MASK)
21993#define DDRPHY_DX1GCR3_RDMBVT_MASK (0x2U)
21994#define DDRPHY_DX1GCR3_RDMBVT_SHIFT (1U)
21995/*! RDMBVT - Read Data Mask BDL VT Compensation
21996 */
21997#define DDRPHY_DX1GCR3_RDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_RDMBVT_SHIFT)) & DDRPHY_DX1GCR3_RDMBVT_MASK)
21998#define DDRPHY_DX1GCR3_DSPDRMODE_MASK (0xCU)
21999#define DDRPHY_DX1GCR3_DSPDRMODE_SHIFT (2U)
22000/*! DSPDRMODE - Enables the PDR mode values for DQS.
22001 */
22002#define DDRPHY_DX1GCR3_DSPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX1GCR3_DSPDRMODE_MASK)
22003#define DDRPHY_DX1GCR3_DSTEMODE_MASK (0x30U)
22004#define DDRPHY_DX1GCR3_DSTEMODE_SHIFT (4U)
22005/*! DSTEMODE - Enables the TE mode values for DQS.
22006 */
22007#define DDRPHY_DX1GCR3_DSTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX1GCR3_DSTEMODE_MASK)
22008#define DDRPHY_DX1GCR3_DSOEMODE_MASK (0xC0U)
22009#define DDRPHY_DX1GCR3_DSOEMODE_SHIFT (6U)
22010/*! DSOEMODE - Enables the OE mode values for DQS.
22011 */
22012#define DDRPHY_DX1GCR3_DSOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX1GCR3_DSOEMODE_MASK)
22013#define DDRPHY_DX1GCR3_WDSBVT_MASK (0x100U)
22014#define DDRPHY_DX1GCR3_WDSBVT_SHIFT (8U)
22015/*! WDSBVT - Write Data Strobe BDL VT Compensation
22016 */
22017#define DDRPHY_DX1GCR3_WDSBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_WDSBVT_SHIFT)) & DDRPHY_DX1GCR3_WDSBVT_MASK)
22018#define DDRPHY_DX1GCR3_RESERVED_9_MASK (0x200U)
22019#define DDRPHY_DX1GCR3_RESERVED_9_SHIFT (9U)
22020/*! RESERVED_9 - Reserved. Returns zeroes on reads.
22021 */
22022#define DDRPHY_DX1GCR3_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX1GCR3_RESERVED_9_MASK)
22023#define DDRPHY_DX1GCR3_DMPDRMODE_MASK (0xC00U)
22024#define DDRPHY_DX1GCR3_DMPDRMODE_SHIFT (10U)
22025/*! DMPDRMODE - Enables the PDR mode values for DM.
22026 */
22027#define DDRPHY_DX1GCR3_DMPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX1GCR3_DMPDRMODE_MASK)
22028#define DDRPHY_DX1GCR3_DMTEMODE_MASK (0x3000U)
22029#define DDRPHY_DX1GCR3_DMTEMODE_SHIFT (12U)
22030/*! DMTEMODE - Enables the TE mode values for DM.
22031 */
22032#define DDRPHY_DX1GCR3_DMTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX1GCR3_DMTEMODE_MASK)
22033#define DDRPHY_DX1GCR3_DMOEMODE_MASK (0xC000U)
22034#define DDRPHY_DX1GCR3_DMOEMODE_SHIFT (14U)
22035/*! DMOEMODE - Enables the OE mode values for DM.
22036 */
22037#define DDRPHY_DX1GCR3_DMOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX1GCR3_DMOEMODE_MASK)
22038#define DDRPHY_DX1GCR3_DSNPDRMODE_MASK (0x30000U)
22039#define DDRPHY_DX1GCR3_DSNPDRMODE_SHIFT (16U)
22040/*! DSNPDRMODE - Enables the PDR mode for DQS
22041 */
22042#define DDRPHY_DX1GCR3_DSNPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX1GCR3_DSNPDRMODE_MASK)
22043#define DDRPHY_DX1GCR3_DSNTEMODE_MASK (0xC0000U)
22044#define DDRPHY_DX1GCR3_DSNTEMODE_SHIFT (18U)
22045/*! DSNTEMODE - Enables the TE mode for DQS
22046 */
22047#define DDRPHY_DX1GCR3_DSNTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX1GCR3_DSNTEMODE_MASK)
22048#define DDRPHY_DX1GCR3_DSNOEMODE_MASK (0x300000U)
22049#define DDRPHY_DX1GCR3_DSNOEMODE_SHIFT (20U)
22050/*! DSNOEMODE - Enables the OE mode for DQs
22051 */
22052#define DDRPHY_DX1GCR3_DSNOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX1GCR3_DSNOEMODE_MASK)
22053#define DDRPHY_DX1GCR3_PDRBVT_MASK (0x400000U)
22054#define DDRPHY_DX1GCR3_PDRBVT_SHIFT (22U)
22055/*! PDRBVT - Power Down Receiver BDL VT Compensation
22056 */
22057#define DDRPHY_DX1GCR3_PDRBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_PDRBVT_SHIFT)) & DDRPHY_DX1GCR3_PDRBVT_MASK)
22058#define DDRPHY_DX1GCR3_RGSLVT_MASK (0x800000U)
22059#define DDRPHY_DX1GCR3_RGSLVT_SHIFT (23U)
22060/*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation
22061 */
22062#define DDRPHY_DX1GCR3_RGSLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_RGSLVT_SHIFT)) & DDRPHY_DX1GCR3_RGSLVT_MASK)
22063#define DDRPHY_DX1GCR3_WLLVT_MASK (0x1000000U)
22064#define DDRPHY_DX1GCR3_WLLVT_SHIFT (24U)
22065/*! WLLVT - Write Leveling LCDL Delay VT Compensation
22066 */
22067#define DDRPHY_DX1GCR3_WLLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_WLLVT_SHIFT)) & DDRPHY_DX1GCR3_WLLVT_MASK)
22068#define DDRPHY_DX1GCR3_WDLVT_MASK (0x2000000U)
22069#define DDRPHY_DX1GCR3_WDLVT_SHIFT (25U)
22070/*! WDLVT - Write DQ LCDL Delay VT Compensation
22071 */
22072#define DDRPHY_DX1GCR3_WDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_WDLVT_SHIFT)) & DDRPHY_DX1GCR3_WDLVT_MASK)
22073#define DDRPHY_DX1GCR3_RDLVT_MASK (0x4000000U)
22074#define DDRPHY_DX1GCR3_RDLVT_SHIFT (26U)
22075/*! RDLVT - Read DQS LCDL Delay VT Compensation
22076 */
22077#define DDRPHY_DX1GCR3_RDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_RDLVT_SHIFT)) & DDRPHY_DX1GCR3_RDLVT_MASK)
22078#define DDRPHY_DX1GCR3_RGLVT_MASK (0x8000000U)
22079#define DDRPHY_DX1GCR3_RGLVT_SHIFT (27U)
22080/*! RGLVT - Read DQS Gating LCDL Delay VT Compensation
22081 */
22082#define DDRPHY_DX1GCR3_RGLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_RGLVT_SHIFT)) & DDRPHY_DX1GCR3_RGLVT_MASK)
22083#define DDRPHY_DX1GCR3_WDBVT_MASK (0x10000000U)
22084#define DDRPHY_DX1GCR3_WDBVT_SHIFT (28U)
22085/*! WDBVT - Write Data BDL VT Compensation
22086 */
22087#define DDRPHY_DX1GCR3_WDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_WDBVT_SHIFT)) & DDRPHY_DX1GCR3_WDBVT_MASK)
22088#define DDRPHY_DX1GCR3_RDBVT_MASK (0x20000000U)
22089#define DDRPHY_DX1GCR3_RDBVT_SHIFT (29U)
22090/*! RDBVT - Read Data BDL VT Compensation
22091 */
22092#define DDRPHY_DX1GCR3_RDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_RDBVT_SHIFT)) & DDRPHY_DX1GCR3_RDBVT_MASK)
22093#define DDRPHY_DX1GCR3_TEBVT_MASK (0x40000000U)
22094#define DDRPHY_DX1GCR3_TEBVT_SHIFT (30U)
22095/*! TEBVT - Termination Enable BDL VT Compensation
22096 */
22097#define DDRPHY_DX1GCR3_TEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_TEBVT_SHIFT)) & DDRPHY_DX1GCR3_TEBVT_MASK)
22098#define DDRPHY_DX1GCR3_OEBVT_MASK (0x80000000U)
22099#define DDRPHY_DX1GCR3_OEBVT_SHIFT (31U)
22100/*! OEBVT - Output Enable BDL VT Compensation
22101 */
22102#define DDRPHY_DX1GCR3_OEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR3_OEBVT_SHIFT)) & DDRPHY_DX1GCR3_OEBVT_MASK)
22103/*! @} */
22104
22105/*! @name DX1GCR4 - DATX8 n General Configuration Register 4 */
22106/*! @{ */
22107#define DDRPHY_DX1GCR4_DXREFIMON_MASK (0x3U)
22108#define DDRPHY_DX1GCR4_DXREFIMON_SHIFT (0U)
22109/*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane.
22110 */
22111#define DDRPHY_DX1GCR4_DXREFIMON(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX1GCR4_DXREFIMON_MASK)
22112#define DDRPHY_DX1GCR4_DXREFIEN_MASK (0x3CU)
22113#define DDRPHY_DX1GCR4_DXREFIEN_SHIFT (2U)
22114/*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
22115 */
22116#define DDRPHY_DX1GCR4_DXREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX1GCR4_DXREFIEN_MASK)
22117#define DDRPHY_DX1GCR4_RESERVED_7_6_MASK (0xC0U)
22118#define DDRPHY_DX1GCR4_RESERVED_7_6_SHIFT (6U)
22119/*! RESERVED_7_6 - Reserved. Returns zeros on reads.
22120 */
22121#define DDRPHY_DX1GCR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX1GCR4_RESERVED_7_6_MASK)
22122#define DDRPHY_DX1GCR4_DXREFSSEL_MASK (0x7F00U)
22123#define DDRPHY_DX1GCR4_DXREFSSEL_SHIFT (8U)
22124/*! DXREFSSEL - Byte Lane Single-End VREF Select
22125 */
22126#define DDRPHY_DX1GCR4_DXREFSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX1GCR4_DXREFSSEL_MASK)
22127#define DDRPHY_DX1GCR4_DXREFSSELRANGE_MASK (0x8000U)
22128#define DDRPHY_DX1GCR4_DXREFSSELRANGE_SHIFT (15U)
22129/*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select
22130 */
22131#define DDRPHY_DX1GCR4_DXREFSSELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX1GCR4_DXREFSSELRANGE_MASK)
22132#define DDRPHY_DX1GCR4_DXREFESEL_MASK (0x7F0000U)
22133#define DDRPHY_DX1GCR4_DXREFESEL_SHIFT (16U)
22134/*! DXREFESEL - Byte Lane External VREF Select
22135 */
22136#define DDRPHY_DX1GCR4_DXREFESEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX1GCR4_DXREFESEL_MASK)
22137#define DDRPHY_DX1GCR4_DXREFESELRANGE_MASK (0x800000U)
22138#define DDRPHY_DX1GCR4_DXREFESELRANGE_SHIFT (23U)
22139/*! DXREFESELRANGE - External VREF generator REFSEL range select
22140 */
22141#define DDRPHY_DX1GCR4_DXREFESELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX1GCR4_DXREFESELRANGE_MASK)
22142#define DDRPHY_DX1GCR4_RESERVED_24_MASK (0x1000000U)
22143#define DDRPHY_DX1GCR4_RESERVED_24_SHIFT (24U)
22144/*! RESERVED_24 - Reserved. Returns zeros on reads.
22145 */
22146#define DDRPHY_DX1GCR4_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX1GCR4_RESERVED_24_MASK)
22147#define DDRPHY_DX1GCR4_DXREFSEN_MASK (0x2000000U)
22148#define DDRPHY_DX1GCR4_DXREFSEN_SHIFT (25U)
22149/*! DXREFSEN - Byte Lane Single-End VREF Enable
22150 */
22151#define DDRPHY_DX1GCR4_DXREFSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX1GCR4_DXREFSEN_MASK)
22152#define DDRPHY_DX1GCR4_DXREFEEN_MASK (0xC000000U)
22153#define DDRPHY_DX1GCR4_DXREFEEN_SHIFT (26U)
22154/*! DXREFEEN - Byte Lane Internal VREF Enable
22155 */
22156#define DDRPHY_DX1GCR4_DXREFEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX1GCR4_DXREFEEN_MASK)
22157#define DDRPHY_DX1GCR4_DXREFPEN_MASK (0x10000000U)
22158#define DDRPHY_DX1GCR4_DXREFPEN_SHIFT (28U)
22159/*! DXREFPEN - Byte Lane VREF Pad Enable
22160 */
22161#define DDRPHY_DX1GCR4_DXREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX1GCR4_DXREFPEN_MASK)
22162#define DDRPHY_DX1GCR4_RESERVED_31_29_MASK (0xE0000000U)
22163#define DDRPHY_DX1GCR4_RESERVED_31_29_SHIFT (29U)
22164/*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs)
22165 */
22166#define DDRPHY_DX1GCR4_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX1GCR4_RESERVED_31_29_MASK)
22167/*! @} */
22168
22169/*! @name DX1GCR5 - DATX8 n General Configuration Register 5 */
22170/*! @{ */
22171#define DDRPHY_DX1GCR5_DXREFISELR0_MASK (0x7FU)
22172#define DDRPHY_DX1GCR5_DXREFISELR0_SHIFT (0U)
22173/*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0
22174 */
22175#define DDRPHY_DX1GCR5_DXREFISELR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX1GCR5_DXREFISELR0_MASK)
22176#define DDRPHY_DX1GCR5_RESERVED_7_MASK (0x80U)
22177#define DDRPHY_DX1GCR5_RESERVED_7_SHIFT (7U)
22178/*! RESERVED_7 - Reserved. Returns zeros on reads.
22179 */
22180#define DDRPHY_DX1GCR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX1GCR5_RESERVED_7_MASK)
22181#define DDRPHY_DX1GCR5_DXREFISELR1_MASK (0x7F00U)
22182#define DDRPHY_DX1GCR5_DXREFISELR1_SHIFT (8U)
22183/*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1
22184 */
22185#define DDRPHY_DX1GCR5_DXREFISELR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX1GCR5_DXREFISELR1_MASK)
22186#define DDRPHY_DX1GCR5_RESERVED_15_MASK (0x8000U)
22187#define DDRPHY_DX1GCR5_RESERVED_15_SHIFT (15U)
22188/*! RESERVED_15 - Reserved. Returns zeros on reads.
22189 */
22190#define DDRPHY_DX1GCR5_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX1GCR5_RESERVED_15_MASK)
22191#define DDRPHY_DX1GCR5_DXREFISELR2_MASK (0x7F0000U)
22192#define DDRPHY_DX1GCR5_DXREFISELR2_SHIFT (16U)
22193/*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2
22194 */
22195#define DDRPHY_DX1GCR5_DXREFISELR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX1GCR5_DXREFISELR2_MASK)
22196#define DDRPHY_DX1GCR5_RESERVED_23_MASK (0x800000U)
22197#define DDRPHY_DX1GCR5_RESERVED_23_SHIFT (23U)
22198/*! RESERVED_23 - Reserved. Returns zeros on reads.
22199 */
22200#define DDRPHY_DX1GCR5_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX1GCR5_RESERVED_23_MASK)
22201#define DDRPHY_DX1GCR5_DXREFISELR3_MASK (0x7F000000U)
22202#define DDRPHY_DX1GCR5_DXREFISELR3_SHIFT (24U)
22203/*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3
22204 */
22205#define DDRPHY_DX1GCR5_DXREFISELR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX1GCR5_DXREFISELR3_MASK)
22206#define DDRPHY_DX1GCR5_RESERVED_31_MASK (0x80000000U)
22207#define DDRPHY_DX1GCR5_RESERVED_31_SHIFT (31U)
22208/*! RESERVED_31 - Reserved. Returns zeros on reads.
22209 */
22210#define DDRPHY_DX1GCR5_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX1GCR5_RESERVED_31_MASK)
22211/*! @} */
22212
22213/*! @name DX1GCR6 - DATX8 n General Configuration Register 6 */
22214/*! @{ */
22215#define DDRPHY_DX1GCR6_DXDQVREFR0_MASK (0x3FU)
22216#define DDRPHY_DX1GCR6_DXDQVREFR0_SHIFT (0U)
22217/*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0
22218 */
22219#define DDRPHY_DX1GCR6_DXDQVREFR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX1GCR6_DXDQVREFR0_MASK)
22220#define DDRPHY_DX1GCR6_RESERVED_7_6_MASK (0xC0U)
22221#define DDRPHY_DX1GCR6_RESERVED_7_6_SHIFT (6U)
22222/*! RESERVED_7_6 - Reserved. Returns zeros on reads.
22223 */
22224#define DDRPHY_DX1GCR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX1GCR6_RESERVED_7_6_MASK)
22225#define DDRPHY_DX1GCR6_DXDQVREFR1_MASK (0x3F00U)
22226#define DDRPHY_DX1GCR6_DXDQVREFR1_SHIFT (8U)
22227/*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1
22228 */
22229#define DDRPHY_DX1GCR6_DXDQVREFR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX1GCR6_DXDQVREFR1_MASK)
22230#define DDRPHY_DX1GCR6_RESERVED_15_14_MASK (0xC000U)
22231#define DDRPHY_DX1GCR6_RESERVED_15_14_SHIFT (14U)
22232/*! RESERVED_15_14 - Reserved. Returns zeros on reads.
22233 */
22234#define DDRPHY_DX1GCR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX1GCR6_RESERVED_15_14_MASK)
22235#define DDRPHY_DX1GCR6_DXDQVREFR2_MASK (0x3F0000U)
22236#define DDRPHY_DX1GCR6_DXDQVREFR2_SHIFT (16U)
22237/*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2
22238 */
22239#define DDRPHY_DX1GCR6_DXDQVREFR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX1GCR6_DXDQVREFR2_MASK)
22240#define DDRPHY_DX1GCR6_RESERVED_23_22_MASK (0xC00000U)
22241#define DDRPHY_DX1GCR6_RESERVED_23_22_SHIFT (22U)
22242/*! RESERVED_23_22 - Reserved. Returns zeros on reads.
22243 */
22244#define DDRPHY_DX1GCR6_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX1GCR6_RESERVED_23_22_MASK)
22245#define DDRPHY_DX1GCR6_DXDQVREFR3_MASK (0x3F000000U)
22246#define DDRPHY_DX1GCR6_DXDQVREFR3_SHIFT (24U)
22247/*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3
22248 */
22249#define DDRPHY_DX1GCR6_DXDQVREFR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX1GCR6_DXDQVREFR3_MASK)
22250#define DDRPHY_DX1GCR6_RESERVED_31_30_MASK (0xC0000000U)
22251#define DDRPHY_DX1GCR6_RESERVED_31_30_SHIFT (30U)
22252/*! RESERVED_31_30 - Reserved. Returns zeros on reads.
22253 */
22254#define DDRPHY_DX1GCR6_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX1GCR6_RESERVED_31_30_MASK)
22255/*! @} */
22256
22257/*! @name DX1GCR7 - DATX8 n General Configuration Register 7 */
22258/*! @{ */
22259#define DDRPHY_DX1GCR7_DCALSVAL_MASK (0x1FFU)
22260#define DDRPHY_DX1GCR7_DCALSVAL_SHIFT (0U)
22261/*! DCALSVAL - DDL Calibration Starting Value
22262 */
22263#define DDRPHY_DX1GCR7_DCALSVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX1GCR7_DCALSVAL_MASK)
22264#define DDRPHY_DX1GCR7_DCALTYPE_MASK (0x200U)
22265#define DDRPHY_DX1GCR7_DCALTYPE_SHIFT (9U)
22266/*! DCALTYPE - DDL Calibration Type
22267 */
22268#define DDRPHY_DX1GCR7_DCALTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX1GCR7_DCALTYPE_MASK)
22269#define DDRPHY_DX1GCR7_RESERVED_17_10_MASK (0x3FC00U)
22270#define DDRPHY_DX1GCR7_RESERVED_17_10_SHIFT (10U)
22271/*! RESERVED_17_10 - Reserved. Caution, do not write to this register field.
22272 */
22273#define DDRPHY_DX1GCR7_RESERVED_17_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX1GCR7_RESERVED_17_10_MASK)
22274#define DDRPHY_DX1GCR7_RESERVED_18_MASK (0x40000U)
22275#define DDRPHY_DX1GCR7_RESERVED_18_SHIFT (18U)
22276/*! RESERVED_18 - Reserved. Caution, do not write to this register field.
22277 */
22278#define DDRPHY_DX1GCR7_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX1GCR7_RESERVED_18_MASK)
22279#define DDRPHY_DX1GCR7_RESERVED_31_19_MASK (0xFFF80000U)
22280#define DDRPHY_DX1GCR7_RESERVED_31_19_SHIFT (19U)
22281/*! RESERVED_31_19 - Reserved. Caution, do not write to this register field.
22282 */
22283#define DDRPHY_DX1GCR7_RESERVED_31_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX1GCR7_RESERVED_31_19_MASK)
22284/*! @} */
22285
22286/*! @name DX1GCR8 - DATX8 n General Configuration Register 8 */
22287/*! @{ */
22288#define DDRPHY_DX1GCR8_RESERVED_5_0_MASK (0x3FU)
22289#define DDRPHY_DX1GCR8_RESERVED_5_0_SHIFT (0U)
22290/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
22291 */
22292#define DDRPHY_DX1GCR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_5_0_MASK)
22293#define DDRPHY_DX1GCR8_RESERVED_7_6_MASK (0xC0U)
22294#define DDRPHY_DX1GCR8_RESERVED_7_6_SHIFT (6U)
22295/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
22296 */
22297#define DDRPHY_DX1GCR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_7_6_MASK)
22298#define DDRPHY_DX1GCR8_RESERVED_13_8_MASK (0x3F00U)
22299#define DDRPHY_DX1GCR8_RESERVED_13_8_SHIFT (8U)
22300/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
22301 */
22302#define DDRPHY_DX1GCR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_13_8_MASK)
22303#define DDRPHY_DX1GCR8_RESERVED_15_14_MASK (0xC000U)
22304#define DDRPHY_DX1GCR8_RESERVED_15_14_SHIFT (14U)
22305/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22306 */
22307#define DDRPHY_DX1GCR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_15_14_MASK)
22308#define DDRPHY_DX1GCR8_RESERVED_21_16_MASK (0x3F0000U)
22309#define DDRPHY_DX1GCR8_RESERVED_21_16_SHIFT (16U)
22310/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
22311 */
22312#define DDRPHY_DX1GCR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_21_16_MASK)
22313#define DDRPHY_DX1GCR8_RESERVED_23_22_MASK (0xC00000U)
22314#define DDRPHY_DX1GCR8_RESERVED_23_22_SHIFT (22U)
22315/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
22316 */
22317#define DDRPHY_DX1GCR8_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_23_22_MASK)
22318#define DDRPHY_DX1GCR8_RESERVED_29_24_MASK (0x3F000000U)
22319#define DDRPHY_DX1GCR8_RESERVED_29_24_SHIFT (24U)
22320/*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
22321 */
22322#define DDRPHY_DX1GCR8_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_29_24_MASK)
22323#define DDRPHY_DX1GCR8_RESERVED_31_30_MASK (0xC0000000U)
22324#define DDRPHY_DX1GCR8_RESERVED_31_30_SHIFT (30U)
22325/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
22326 */
22327#define DDRPHY_DX1GCR8_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX1GCR8_RESERVED_31_30_MASK)
22328/*! @} */
22329
22330/*! @name DX1GCR9 - DATX8 n General Configuration Register 9 */
22331/*! @{ */
22332#define DDRPHY_DX1GCR9_RESERVED_5_0_MASK (0x3FU)
22333#define DDRPHY_DX1GCR9_RESERVED_5_0_SHIFT (0U)
22334/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
22335 */
22336#define DDRPHY_DX1GCR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_5_0_MASK)
22337#define DDRPHY_DX1GCR9_RESERVED_7_6_MASK (0xC0U)
22338#define DDRPHY_DX1GCR9_RESERVED_7_6_SHIFT (6U)
22339/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
22340 */
22341#define DDRPHY_DX1GCR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_7_6_MASK)
22342#define DDRPHY_DX1GCR9_RESERVED_13_8_MASK (0x3F00U)
22343#define DDRPHY_DX1GCR9_RESERVED_13_8_SHIFT (8U)
22344/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
22345 */
22346#define DDRPHY_DX1GCR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_13_8_MASK)
22347#define DDRPHY_DX1GCR9_RESERVED_15_14_MASK (0xC000U)
22348#define DDRPHY_DX1GCR9_RESERVED_15_14_SHIFT (14U)
22349/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22350 */
22351#define DDRPHY_DX1GCR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_15_14_MASK)
22352#define DDRPHY_DX1GCR9_RESERVED_21_16_MASK (0x3F0000U)
22353#define DDRPHY_DX1GCR9_RESERVED_21_16_SHIFT (16U)
22354/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
22355 */
22356#define DDRPHY_DX1GCR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_21_16_MASK)
22357#define DDRPHY_DX1GCR9_RESERVED_23_22_MASK (0xC00000U)
22358#define DDRPHY_DX1GCR9_RESERVED_23_22_SHIFT (22U)
22359/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
22360 */
22361#define DDRPHY_DX1GCR9_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_23_22_MASK)
22362#define DDRPHY_DX1GCR9_RESERVED_29_24_MASK (0x3F000000U)
22363#define DDRPHY_DX1GCR9_RESERVED_29_24_SHIFT (24U)
22364/*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
22365 */
22366#define DDRPHY_DX1GCR9_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_29_24_MASK)
22367#define DDRPHY_DX1GCR9_RESERVED_31_30_MASK (0xC0000000U)
22368#define DDRPHY_DX1GCR9_RESERVED_31_30_SHIFT (30U)
22369/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
22370 */
22371#define DDRPHY_DX1GCR9_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX1GCR9_RESERVED_31_30_MASK)
22372/*! @} */
22373
22374/*! @name DX1DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */
22375/*! @{ */
22376#define DDRPHY_DX1DQMAP0_DQ0MAP_MASK (0xFU)
22377#define DDRPHY_DX1DQMAP0_DQ0MAP_SHIFT (0U)
22378/*! DQ0MAP - DQ bit 0 DATX8 slice mapping index
22379 */
22380#define DDRPHY_DX1DQMAP0_DQ0MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX1DQMAP0_DQ0MAP_MASK)
22381#define DDRPHY_DX1DQMAP0_DQ1MAP_MASK (0xF0U)
22382#define DDRPHY_DX1DQMAP0_DQ1MAP_SHIFT (4U)
22383/*! DQ1MAP - DQ bit 1 DATX8 slice mapping index
22384 */
22385#define DDRPHY_DX1DQMAP0_DQ1MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX1DQMAP0_DQ1MAP_MASK)
22386#define DDRPHY_DX1DQMAP0_DQ2MAP_MASK (0xF00U)
22387#define DDRPHY_DX1DQMAP0_DQ2MAP_SHIFT (8U)
22388/*! DQ2MAP - DQ bit 2 DATX8 slice mapping index
22389 */
22390#define DDRPHY_DX1DQMAP0_DQ2MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX1DQMAP0_DQ2MAP_MASK)
22391#define DDRPHY_DX1DQMAP0_DQ3MAP_MASK (0xF000U)
22392#define DDRPHY_DX1DQMAP0_DQ3MAP_SHIFT (12U)
22393/*! DQ3MAP - DQ bit 3 DATX8 slice mapping index
22394 */
22395#define DDRPHY_DX1DQMAP0_DQ3MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX1DQMAP0_DQ3MAP_MASK)
22396#define DDRPHY_DX1DQMAP0_DQ4MAP_MASK (0xF0000U)
22397#define DDRPHY_DX1DQMAP0_DQ4MAP_SHIFT (16U)
22398/*! DQ4MAP - DQ bit 4 DATX8 slice mapping index
22399 */
22400#define DDRPHY_DX1DQMAP0_DQ4MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX1DQMAP0_DQ4MAP_MASK)
22401#define DDRPHY_DX1DQMAP0_RESERVED_30_20_MASK (0x7FF00000U)
22402#define DDRPHY_DX1DQMAP0_RESERVED_30_20_SHIFT (20U)
22403/*! RESERVED_30_20 - Reserved. Return zeroes on reads.
22404 */
22405#define DDRPHY_DX1DQMAP0_RESERVED_30_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX1DQMAP0_RESERVED_30_20_MASK)
22406#define DDRPHY_DX1DQMAP0_MAPOK_MASK (0x80000000U)
22407#define DDRPHY_DX1DQMAP0_MAPOK_SHIFT (31U)
22408/*! MAPOK - Checksum bit
22409 */
22410#define DDRPHY_DX1DQMAP0_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX1DQMAP0_MAPOK_MASK)
22411/*! @} */
22412
22413/*! @name DX1DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */
22414/*! @{ */
22415#define DDRPHY_DX1DQMAP1_DQ5MAP_MASK (0xFU)
22416#define DDRPHY_DX1DQMAP1_DQ5MAP_SHIFT (0U)
22417/*! DQ5MAP - DQ bit 5 DATX8 slice mapping index
22418 */
22419#define DDRPHY_DX1DQMAP1_DQ5MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX1DQMAP1_DQ5MAP_MASK)
22420#define DDRPHY_DX1DQMAP1_DQ6MAP_MASK (0xF0U)
22421#define DDRPHY_DX1DQMAP1_DQ6MAP_SHIFT (4U)
22422/*! DQ6MAP - DQ bit 6 DATX8 slice mapping index
22423 */
22424#define DDRPHY_DX1DQMAP1_DQ6MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX1DQMAP1_DQ6MAP_MASK)
22425#define DDRPHY_DX1DQMAP1_DQ7MAP_MASK (0xF00U)
22426#define DDRPHY_DX1DQMAP1_DQ7MAP_SHIFT (8U)
22427/*! DQ7MAP - DQ bit 7 DATX8 slice mapping index
22428 */
22429#define DDRPHY_DX1DQMAP1_DQ7MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX1DQMAP1_DQ7MAP_MASK)
22430#define DDRPHY_DX1DQMAP1_DMMAP_MASK (0xF000U)
22431#define DDRPHY_DX1DQMAP1_DMMAP_SHIFT (12U)
22432/*! DMMAP - DM bit DATX8 slice mapping index
22433 */
22434#define DDRPHY_DX1DQMAP1_DMMAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX1DQMAP1_DMMAP_MASK)
22435#define DDRPHY_DX1DQMAP1_RESERVED_30_16_MASK (0x7FFF0000U)
22436#define DDRPHY_DX1DQMAP1_RESERVED_30_16_SHIFT (16U)
22437/*! RESERVED_30_16 - Reserved. Return zeroes on reads.
22438 */
22439#define DDRPHY_DX1DQMAP1_RESERVED_30_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX1DQMAP1_RESERVED_30_16_MASK)
22440#define DDRPHY_DX1DQMAP1_MAPOK_MASK (0x80000000U)
22441#define DDRPHY_DX1DQMAP1_MAPOK_SHIFT (31U)
22442/*! MAPOK - Checksum bit
22443 */
22444#define DDRPHY_DX1DQMAP1_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX1DQMAP1_MAPOK_MASK)
22445/*! @} */
22446
22447/*! @name DX1BDLR0 - DATX8 n Bit Delay Line Register 0 */
22448/*! @{ */
22449#define DDRPHY_DX1BDLR0_DQ0WBD_MASK (0x3FU)
22450#define DDRPHY_DX1BDLR0_DQ0WBD_SHIFT (0U)
22451/*! DQ0WBD - DQ0 Write Bit Delay
22452 */
22453#define DDRPHY_DX1BDLR0_DQ0WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX1BDLR0_DQ0WBD_MASK)
22454#define DDRPHY_DX1BDLR0_RESERVED_7_6_MASK (0xC0U)
22455#define DDRPHY_DX1BDLR0_RESERVED_7_6_SHIFT (6U)
22456/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
22457 */
22458#define DDRPHY_DX1BDLR0_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR0_RESERVED_7_6_MASK)
22459#define DDRPHY_DX1BDLR0_DQ1WBD_MASK (0x3F00U)
22460#define DDRPHY_DX1BDLR0_DQ1WBD_SHIFT (8U)
22461/*! DQ1WBD - DQ1 Write Bit Delay
22462 */
22463#define DDRPHY_DX1BDLR0_DQ1WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX1BDLR0_DQ1WBD_MASK)
22464#define DDRPHY_DX1BDLR0_RESERVED_15_14_MASK (0xC000U)
22465#define DDRPHY_DX1BDLR0_RESERVED_15_14_SHIFT (14U)
22466/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22467 */
22468#define DDRPHY_DX1BDLR0_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR0_RESERVED_15_14_MASK)
22469#define DDRPHY_DX1BDLR0_DQ2WBD_MASK (0x3F0000U)
22470#define DDRPHY_DX1BDLR0_DQ2WBD_SHIFT (16U)
22471/*! DQ2WBD - DQ2 Write Bit Delay
22472 */
22473#define DDRPHY_DX1BDLR0_DQ2WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX1BDLR0_DQ2WBD_MASK)
22474#define DDRPHY_DX1BDLR0_RESERVED_23_22_MASK (0xC00000U)
22475#define DDRPHY_DX1BDLR0_RESERVED_23_22_SHIFT (22U)
22476/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
22477 */
22478#define DDRPHY_DX1BDLR0_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX1BDLR0_RESERVED_23_22_MASK)
22479#define DDRPHY_DX1BDLR0_DQ3WBD_MASK (0x3F000000U)
22480#define DDRPHY_DX1BDLR0_DQ3WBD_SHIFT (24U)
22481/*! DQ3WBD - DQ3 Write Bit Delay
22482 */
22483#define DDRPHY_DX1BDLR0_DQ3WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX1BDLR0_DQ3WBD_MASK)
22484#define DDRPHY_DX1BDLR0_RESERVED_31_30_MASK (0xC0000000U)
22485#define DDRPHY_DX1BDLR0_RESERVED_31_30_SHIFT (30U)
22486/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
22487 */
22488#define DDRPHY_DX1BDLR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX1BDLR0_RESERVED_31_30_MASK)
22489/*! @} */
22490
22491/*! @name DX1BDLR1 - DATX8 n Bit Delay Line Register 1 */
22492/*! @{ */
22493#define DDRPHY_DX1BDLR1_DQ4WBD_MASK (0x3FU)
22494#define DDRPHY_DX1BDLR1_DQ4WBD_SHIFT (0U)
22495/*! DQ4WBD - DQ4 Write Bit Delay
22496 */
22497#define DDRPHY_DX1BDLR1_DQ4WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX1BDLR1_DQ4WBD_MASK)
22498#define DDRPHY_DX1BDLR1_RESERVED_7_6_MASK (0xC0U)
22499#define DDRPHY_DX1BDLR1_RESERVED_7_6_SHIFT (6U)
22500/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
22501 */
22502#define DDRPHY_DX1BDLR1_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR1_RESERVED_7_6_MASK)
22503#define DDRPHY_DX1BDLR1_DQ5WBD_MASK (0x3F00U)
22504#define DDRPHY_DX1BDLR1_DQ5WBD_SHIFT (8U)
22505/*! DQ5WBD - DQ5 Write Bit Delay
22506 */
22507#define DDRPHY_DX1BDLR1_DQ5WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX1BDLR1_DQ5WBD_MASK)
22508#define DDRPHY_DX1BDLR1_RESERVED_15_14_MASK (0xC000U)
22509#define DDRPHY_DX1BDLR1_RESERVED_15_14_SHIFT (14U)
22510/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22511 */
22512#define DDRPHY_DX1BDLR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR1_RESERVED_15_14_MASK)
22513#define DDRPHY_DX1BDLR1_DQ6WBD_MASK (0x3F0000U)
22514#define DDRPHY_DX1BDLR1_DQ6WBD_SHIFT (16U)
22515/*! DQ6WBD - DQ6 Write Bit Delay
22516 */
22517#define DDRPHY_DX1BDLR1_DQ6WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX1BDLR1_DQ6WBD_MASK)
22518#define DDRPHY_DX1BDLR1_RESERVED_23_22_MASK (0xC00000U)
22519#define DDRPHY_DX1BDLR1_RESERVED_23_22_SHIFT (22U)
22520/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
22521 */
22522#define DDRPHY_DX1BDLR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX1BDLR1_RESERVED_23_22_MASK)
22523#define DDRPHY_DX1BDLR1_DQ7WBD_MASK (0x3F000000U)
22524#define DDRPHY_DX1BDLR1_DQ7WBD_SHIFT (24U)
22525/*! DQ7WBD - DQ7 Write Bit Delay
22526 */
22527#define DDRPHY_DX1BDLR1_DQ7WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX1BDLR1_DQ7WBD_MASK)
22528#define DDRPHY_DX1BDLR1_RESERVED_31_30_MASK (0xC0000000U)
22529#define DDRPHY_DX1BDLR1_RESERVED_31_30_SHIFT (30U)
22530/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
22531 */
22532#define DDRPHY_DX1BDLR1_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX1BDLR1_RESERVED_31_30_MASK)
22533/*! @} */
22534
22535/*! @name DX1BDLR2 - DATX8 n Bit Delay Line Register 2 */
22536/*! @{ */
22537#define DDRPHY_DX1BDLR2_DMWBD_MASK (0x3FU)
22538#define DDRPHY_DX1BDLR2_DMWBD_SHIFT (0U)
22539/*! DMWBD - DM Write Bit Delay
22540 */
22541#define DDRPHY_DX1BDLR2_DMWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_DMWBD_SHIFT)) & DDRPHY_DX1BDLR2_DMWBD_MASK)
22542#define DDRPHY_DX1BDLR2_RESERVED_7_6_MASK (0xC0U)
22543#define DDRPHY_DX1BDLR2_RESERVED_7_6_SHIFT (6U)
22544/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
22545 */
22546#define DDRPHY_DX1BDLR2_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR2_RESERVED_7_6_MASK)
22547#define DDRPHY_DX1BDLR2_DSWBD_MASK (0x3F00U)
22548#define DDRPHY_DX1BDLR2_DSWBD_SHIFT (8U)
22549/*! DSWBD - DQS Write Bit Delay
22550 */
22551#define DDRPHY_DX1BDLR2_DSWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_DSWBD_SHIFT)) & DDRPHY_DX1BDLR2_DSWBD_MASK)
22552#define DDRPHY_DX1BDLR2_RESERVED_15_14_MASK (0xC000U)
22553#define DDRPHY_DX1BDLR2_RESERVED_15_14_SHIFT (14U)
22554/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22555 */
22556#define DDRPHY_DX1BDLR2_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR2_RESERVED_15_14_MASK)
22557#define DDRPHY_DX1BDLR2_DSOEBD_MASK (0x3F0000U)
22558#define DDRPHY_DX1BDLR2_DSOEBD_SHIFT (16U)
22559/*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay
22560 */
22561#define DDRPHY_DX1BDLR2_DSOEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX1BDLR2_DSOEBD_MASK)
22562#define DDRPHY_DX1BDLR2_RESERVED_23_22_MASK (0xC00000U)
22563#define DDRPHY_DX1BDLR2_RESERVED_23_22_SHIFT (22U)
22564/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
22565 */
22566#define DDRPHY_DX1BDLR2_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX1BDLR2_RESERVED_23_22_MASK)
22567#define DDRPHY_DX1BDLR2_DSNWBD_MASK (0x3F000000U)
22568#define DDRPHY_DX1BDLR2_DSNWBD_SHIFT (24U)
22569/*! DSNWBD - DQSN Write Bit Delay
22570 */
22571#define DDRPHY_DX1BDLR2_DSNWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX1BDLR2_DSNWBD_MASK)
22572#define DDRPHY_DX1BDLR2_RESERVED_31_30_MASK (0xC0000000U)
22573#define DDRPHY_DX1BDLR2_RESERVED_31_30_SHIFT (30U)
22574/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
22575 */
22576#define DDRPHY_DX1BDLR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX1BDLR2_RESERVED_31_30_MASK)
22577/*! @} */
22578
22579/*! @name DX1BDLR3 - DATX8 n Bit Delay Line Register 3 */
22580/*! @{ */
22581#define DDRPHY_DX1BDLR3_DQ0RBD_MASK (0x3FU)
22582#define DDRPHY_DX1BDLR3_DQ0RBD_SHIFT (0U)
22583/*! DQ0RBD - DQ0 Read Bit Delay
22584 */
22585#define DDRPHY_DX1BDLR3_DQ0RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX1BDLR3_DQ0RBD_MASK)
22586#define DDRPHY_DX1BDLR3_RESERVED_7_6_MASK (0xC0U)
22587#define DDRPHY_DX1BDLR3_RESERVED_7_6_SHIFT (6U)
22588/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
22589 */
22590#define DDRPHY_DX1BDLR3_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR3_RESERVED_7_6_MASK)
22591#define DDRPHY_DX1BDLR3_DQ1RBD_MASK (0x3F00U)
22592#define DDRPHY_DX1BDLR3_DQ1RBD_SHIFT (8U)
22593/*! DQ1RBD - DQ1 Read Bit Delay
22594 */
22595#define DDRPHY_DX1BDLR3_DQ1RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX1BDLR3_DQ1RBD_MASK)
22596#define DDRPHY_DX1BDLR3_RESERVED_15_14_MASK (0xC000U)
22597#define DDRPHY_DX1BDLR3_RESERVED_15_14_SHIFT (14U)
22598/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22599 */
22600#define DDRPHY_DX1BDLR3_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR3_RESERVED_15_14_MASK)
22601#define DDRPHY_DX1BDLR3_DQ2RBD_MASK (0x3F0000U)
22602#define DDRPHY_DX1BDLR3_DQ2RBD_SHIFT (16U)
22603/*! DQ2RBD - DQ2 Read Bit Delay
22604 */
22605#define DDRPHY_DX1BDLR3_DQ2RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX1BDLR3_DQ2RBD_MASK)
22606#define DDRPHY_DX1BDLR3_RESERVED_23_22_MASK (0xC00000U)
22607#define DDRPHY_DX1BDLR3_RESERVED_23_22_SHIFT (22U)
22608/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
22609 */
22610#define DDRPHY_DX1BDLR3_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX1BDLR3_RESERVED_23_22_MASK)
22611#define DDRPHY_DX1BDLR3_DQ3RBD_MASK (0x3F000000U)
22612#define DDRPHY_DX1BDLR3_DQ3RBD_SHIFT (24U)
22613/*! DQ3RBD - DQ3 Read Bit Delay
22614 */
22615#define DDRPHY_DX1BDLR3_DQ3RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX1BDLR3_DQ3RBD_MASK)
22616#define DDRPHY_DX1BDLR3_RESERVED_31_30_MASK (0xC0000000U)
22617#define DDRPHY_DX1BDLR3_RESERVED_31_30_SHIFT (30U)
22618/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
22619 */
22620#define DDRPHY_DX1BDLR3_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX1BDLR3_RESERVED_31_30_MASK)
22621/*! @} */
22622
22623/*! @name DX1BDLR4 - DATX8 n Bit Delay Line Register 4 */
22624/*! @{ */
22625#define DDRPHY_DX1BDLR4_DQ4RBD_MASK (0x3FU)
22626#define DDRPHY_DX1BDLR4_DQ4RBD_SHIFT (0U)
22627/*! DQ4RBD - DQ4 Read Bit Delay
22628 */
22629#define DDRPHY_DX1BDLR4_DQ4RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX1BDLR4_DQ4RBD_MASK)
22630#define DDRPHY_DX1BDLR4_RESERVED_7_6_MASK (0xC0U)
22631#define DDRPHY_DX1BDLR4_RESERVED_7_6_SHIFT (6U)
22632/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
22633 */
22634#define DDRPHY_DX1BDLR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR4_RESERVED_7_6_MASK)
22635#define DDRPHY_DX1BDLR4_DQ5RBD_MASK (0x3F00U)
22636#define DDRPHY_DX1BDLR4_DQ5RBD_SHIFT (8U)
22637/*! DQ5RBD - DQ5 Read Bit Delay
22638 */
22639#define DDRPHY_DX1BDLR4_DQ5RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX1BDLR4_DQ5RBD_MASK)
22640#define DDRPHY_DX1BDLR4_RESERVED_15_14_MASK (0xC000U)
22641#define DDRPHY_DX1BDLR4_RESERVED_15_14_SHIFT (14U)
22642/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22643 */
22644#define DDRPHY_DX1BDLR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR4_RESERVED_15_14_MASK)
22645#define DDRPHY_DX1BDLR4_DQ6RBD_MASK (0x3F0000U)
22646#define DDRPHY_DX1BDLR4_DQ6RBD_SHIFT (16U)
22647/*! DQ6RBD - DQ6 Read Bit Delay
22648 */
22649#define DDRPHY_DX1BDLR4_DQ6RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX1BDLR4_DQ6RBD_MASK)
22650#define DDRPHY_DX1BDLR4_RESERVED_23_22_MASK (0xC00000U)
22651#define DDRPHY_DX1BDLR4_RESERVED_23_22_SHIFT (22U)
22652/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
22653 */
22654#define DDRPHY_DX1BDLR4_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX1BDLR4_RESERVED_23_22_MASK)
22655#define DDRPHY_DX1BDLR4_DQ7RBD_MASK (0x3F000000U)
22656#define DDRPHY_DX1BDLR4_DQ7RBD_SHIFT (24U)
22657/*! DQ7RBD - DQ7 Read Bit Delay
22658 */
22659#define DDRPHY_DX1BDLR4_DQ7RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX1BDLR4_DQ7RBD_MASK)
22660#define DDRPHY_DX1BDLR4_RESERVED_31_30_MASK (0xC0000000U)
22661#define DDRPHY_DX1BDLR4_RESERVED_31_30_SHIFT (30U)
22662/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
22663 */
22664#define DDRPHY_DX1BDLR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX1BDLR4_RESERVED_31_30_MASK)
22665/*! @} */
22666
22667/*! @name DX1BDLR5 - DATX8 n Bit Delay Line Register 5 */
22668/*! @{ */
22669#define DDRPHY_DX1BDLR5_DMRBD_MASK (0x3FU)
22670#define DDRPHY_DX1BDLR5_DMRBD_SHIFT (0U)
22671/*! DMRBD - DM Read Bit Delay
22672 */
22673#define DDRPHY_DX1BDLR5_DMRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR5_DMRBD_SHIFT)) & DDRPHY_DX1BDLR5_DMRBD_MASK)
22674#define DDRPHY_DX1BDLR5_RESERVED_31_6_MASK (0xFFFFFFC0U)
22675#define DDRPHY_DX1BDLR5_RESERVED_31_6_SHIFT (6U)
22676/*! RESERVED_31_6 - Reserved. Return zeroes on reads.
22677 */
22678#define DDRPHY_DX1BDLR5_RESERVED_31_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX1BDLR5_RESERVED_31_6_MASK)
22679/*! @} */
22680
22681/*! @name DX1BDLR6 - DATX8 n Bit Delay Line Register 6 */
22682/*! @{ */
22683#define DDRPHY_DX1BDLR6_RESERVED_7_0_MASK (0xFFU)
22684#define DDRPHY_DX1BDLR6_RESERVED_7_0_SHIFT (0U)
22685/*! RESERVED_7_0 - Reserved. Return zeroes on reads.
22686 */
22687#define DDRPHY_DX1BDLR6_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX1BDLR6_RESERVED_7_0_MASK)
22688#define DDRPHY_DX1BDLR6_PDRBD_MASK (0x3F00U)
22689#define DDRPHY_DX1BDLR6_PDRBD_SHIFT (8U)
22690/*! PDRBD - Power down receiver Bit Delay
22691 */
22692#define DDRPHY_DX1BDLR6_PDRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR6_PDRBD_SHIFT)) & DDRPHY_DX1BDLR6_PDRBD_MASK)
22693#define DDRPHY_DX1BDLR6_RESERVED_15_14_MASK (0xC000U)
22694#define DDRPHY_DX1BDLR6_RESERVED_15_14_SHIFT (14U)
22695/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22696 */
22697#define DDRPHY_DX1BDLR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR6_RESERVED_15_14_MASK)
22698#define DDRPHY_DX1BDLR6_TERBD_MASK (0x3F0000U)
22699#define DDRPHY_DX1BDLR6_TERBD_SHIFT (16U)
22700/*! TERBD - Termination Enable Bit Delay
22701 */
22702#define DDRPHY_DX1BDLR6_TERBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR6_TERBD_SHIFT)) & DDRPHY_DX1BDLR6_TERBD_MASK)
22703#define DDRPHY_DX1BDLR6_RESERVED_31_22_MASK (0xFFC00000U)
22704#define DDRPHY_DX1BDLR6_RESERVED_31_22_SHIFT (22U)
22705/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
22706 */
22707#define DDRPHY_DX1BDLR6_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX1BDLR6_RESERVED_31_22_MASK)
22708/*! @} */
22709
22710/*! @name DX1BDLR7 - DATX8 n Bit Delay Line Register 7 */
22711/*! @{ */
22712#define DDRPHY_DX1BDLR7_RESERVED_5_0_MASK (0x3FU)
22713#define DDRPHY_DX1BDLR7_RESERVED_5_0_SHIFT (0U)
22714/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
22715 */
22716#define DDRPHY_DX1BDLR7_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX1BDLR7_RESERVED_5_0_MASK)
22717#define DDRPHY_DX1BDLR7_RESERVED_7_6_MASK (0xC0U)
22718#define DDRPHY_DX1BDLR7_RESERVED_7_6_SHIFT (6U)
22719/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
22720 */
22721#define DDRPHY_DX1BDLR7_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR7_RESERVED_7_6_MASK)
22722#define DDRPHY_DX1BDLR7_RESERVED_13_8_MASK (0x3F00U)
22723#define DDRPHY_DX1BDLR7_RESERVED_13_8_SHIFT (8U)
22724/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
22725 */
22726#define DDRPHY_DX1BDLR7_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX1BDLR7_RESERVED_13_8_MASK)
22727#define DDRPHY_DX1BDLR7_RESERVED_15_14_MASK (0xC000U)
22728#define DDRPHY_DX1BDLR7_RESERVED_15_14_SHIFT (14U)
22729/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22730 */
22731#define DDRPHY_DX1BDLR7_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR7_RESERVED_15_14_MASK)
22732#define DDRPHY_DX1BDLR7_RESERVED_21_16_MASK (0x3F0000U)
22733#define DDRPHY_DX1BDLR7_RESERVED_21_16_SHIFT (16U)
22734/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
22735 */
22736#define DDRPHY_DX1BDLR7_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX1BDLR7_RESERVED_21_16_MASK)
22737#define DDRPHY_DX1BDLR7_RESERVED_31_22_MASK (0xFFC00000U)
22738#define DDRPHY_DX1BDLR7_RESERVED_31_22_SHIFT (22U)
22739/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
22740 */
22741#define DDRPHY_DX1BDLR7_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX1BDLR7_RESERVED_31_22_MASK)
22742/*! @} */
22743
22744/*! @name DX1BDLR8 - DATX8 n Bit Delay Line Register 8 */
22745/*! @{ */
22746#define DDRPHY_DX1BDLR8_RESERVED_5_0_MASK (0x3FU)
22747#define DDRPHY_DX1BDLR8_RESERVED_5_0_SHIFT (0U)
22748/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
22749 */
22750#define DDRPHY_DX1BDLR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX1BDLR8_RESERVED_5_0_MASK)
22751#define DDRPHY_DX1BDLR8_RESERVED_7_6_MASK (0xC0U)
22752#define DDRPHY_DX1BDLR8_RESERVED_7_6_SHIFT (6U)
22753/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
22754 */
22755#define DDRPHY_DX1BDLR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR8_RESERVED_7_6_MASK)
22756#define DDRPHY_DX1BDLR8_RESERVED_13_8_MASK (0x3F00U)
22757#define DDRPHY_DX1BDLR8_RESERVED_13_8_SHIFT (8U)
22758/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
22759 */
22760#define DDRPHY_DX1BDLR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX1BDLR8_RESERVED_13_8_MASK)
22761#define DDRPHY_DX1BDLR8_RESERVED_15_14_MASK (0xC000U)
22762#define DDRPHY_DX1BDLR8_RESERVED_15_14_SHIFT (14U)
22763/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22764 */
22765#define DDRPHY_DX1BDLR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR8_RESERVED_15_14_MASK)
22766#define DDRPHY_DX1BDLR8_RESERVED_21_16_MASK (0x3F0000U)
22767#define DDRPHY_DX1BDLR8_RESERVED_21_16_SHIFT (16U)
22768/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
22769 */
22770#define DDRPHY_DX1BDLR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX1BDLR8_RESERVED_21_16_MASK)
22771#define DDRPHY_DX1BDLR8_RESERVED_31_22_MASK (0xFFC00000U)
22772#define DDRPHY_DX1BDLR8_RESERVED_31_22_SHIFT (22U)
22773/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
22774 */
22775#define DDRPHY_DX1BDLR8_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX1BDLR8_RESERVED_31_22_MASK)
22776/*! @} */
22777
22778/*! @name DX1BDLR9 - DATX8 n Bit Delay Line Register 9 */
22779/*! @{ */
22780#define DDRPHY_DX1BDLR9_RESERVED_5_0_MASK (0x3FU)
22781#define DDRPHY_DX1BDLR9_RESERVED_5_0_SHIFT (0U)
22782/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
22783 */
22784#define DDRPHY_DX1BDLR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX1BDLR9_RESERVED_5_0_MASK)
22785#define DDRPHY_DX1BDLR9_RESERVED_7_6_MASK (0xC0U)
22786#define DDRPHY_DX1BDLR9_RESERVED_7_6_SHIFT (6U)
22787/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
22788 */
22789#define DDRPHY_DX1BDLR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX1BDLR9_RESERVED_7_6_MASK)
22790#define DDRPHY_DX1BDLR9_RESERVED_13_8_MASK (0x3F00U)
22791#define DDRPHY_DX1BDLR9_RESERVED_13_8_SHIFT (8U)
22792/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
22793 */
22794#define DDRPHY_DX1BDLR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX1BDLR9_RESERVED_13_8_MASK)
22795#define DDRPHY_DX1BDLR9_RESERVED_15_14_MASK (0xC000U)
22796#define DDRPHY_DX1BDLR9_RESERVED_15_14_SHIFT (14U)
22797/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
22798 */
22799#define DDRPHY_DX1BDLR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX1BDLR9_RESERVED_15_14_MASK)
22800#define DDRPHY_DX1BDLR9_RESERVED_21_16_MASK (0x3F0000U)
22801#define DDRPHY_DX1BDLR9_RESERVED_21_16_SHIFT (16U)
22802/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
22803 */
22804#define DDRPHY_DX1BDLR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX1BDLR9_RESERVED_21_16_MASK)
22805#define DDRPHY_DX1BDLR9_RESERVED_31_22_MASK (0xFFC00000U)
22806#define DDRPHY_DX1BDLR9_RESERVED_31_22_SHIFT (22U)
22807/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
22808 */
22809#define DDRPHY_DX1BDLR9_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX1BDLR9_RESERVED_31_22_MASK)
22810/*! @} */
22811
22812/*! @name DX1LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */
22813/*! @{ */
22814#define DDRPHY_DX1LCDLR0_WLD_MASK (0x1FFU)
22815#define DDRPHY_DX1LCDLR0_WLD_SHIFT (0U)
22816/*! WLD - Write Leveling Delay
22817 */
22818#define DDRPHY_DX1LCDLR0_WLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR0_WLD_SHIFT)) & DDRPHY_DX1LCDLR0_WLD_MASK)
22819#define DDRPHY_DX1LCDLR0_RESERVED_15_9_MASK (0xFE00U)
22820#define DDRPHY_DX1LCDLR0_RESERVED_15_9_SHIFT (9U)
22821/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
22822 */
22823#define DDRPHY_DX1LCDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX1LCDLR0_RESERVED_15_9_MASK)
22824#define DDRPHY_DX1LCDLR0_RESERVED_24_16_MASK (0x1FF0000U)
22825#define DDRPHY_DX1LCDLR0_RESERVED_24_16_SHIFT (16U)
22826/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
22827 */
22828#define DDRPHY_DX1LCDLR0_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX1LCDLR0_RESERVED_24_16_MASK)
22829#define DDRPHY_DX1LCDLR0_RESERVED_31_25_MASK (0xFE000000U)
22830#define DDRPHY_DX1LCDLR0_RESERVED_31_25_SHIFT (25U)
22831/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
22832 */
22833#define DDRPHY_DX1LCDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX1LCDLR0_RESERVED_31_25_MASK)
22834/*! @} */
22835
22836/*! @name DX1LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */
22837/*! @{ */
22838#define DDRPHY_DX1LCDLR1_WDQD_MASK (0x1FFU)
22839#define DDRPHY_DX1LCDLR1_WDQD_SHIFT (0U)
22840/*! WDQD - Write Data Delay
22841 */
22842#define DDRPHY_DX1LCDLR1_WDQD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR1_WDQD_SHIFT)) & DDRPHY_DX1LCDLR1_WDQD_MASK)
22843#define DDRPHY_DX1LCDLR1_RESERVED_15_9_MASK (0xFE00U)
22844#define DDRPHY_DX1LCDLR1_RESERVED_15_9_SHIFT (9U)
22845/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
22846 */
22847#define DDRPHY_DX1LCDLR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX1LCDLR1_RESERVED_15_9_MASK)
22848#define DDRPHY_DX1LCDLR1_RESERVED_24_16_MASK (0x1FF0000U)
22849#define DDRPHY_DX1LCDLR1_RESERVED_24_16_SHIFT (16U)
22850/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
22851 */
22852#define DDRPHY_DX1LCDLR1_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX1LCDLR1_RESERVED_24_16_MASK)
22853#define DDRPHY_DX1LCDLR1_RESERVED_31_25_MASK (0xFE000000U)
22854#define DDRPHY_DX1LCDLR1_RESERVED_31_25_SHIFT (25U)
22855/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
22856 */
22857#define DDRPHY_DX1LCDLR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX1LCDLR1_RESERVED_31_25_MASK)
22858/*! @} */
22859
22860/*! @name DX1LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */
22861/*! @{ */
22862#define DDRPHY_DX1LCDLR2_DQSGD_MASK (0x1FFU)
22863#define DDRPHY_DX1LCDLR2_DQSGD_SHIFT (0U)
22864/*! DQSGD - Read DQS Gating Delay
22865 */
22866#define DDRPHY_DX1LCDLR2_DQSGD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX1LCDLR2_DQSGD_MASK)
22867#define DDRPHY_DX1LCDLR2_RESERVED_15_9_MASK (0xFE00U)
22868#define DDRPHY_DX1LCDLR2_RESERVED_15_9_SHIFT (9U)
22869/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
22870 */
22871#define DDRPHY_DX1LCDLR2_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX1LCDLR2_RESERVED_15_9_MASK)
22872#define DDRPHY_DX1LCDLR2_RESERVED_24_16_MASK (0x1FF0000U)
22873#define DDRPHY_DX1LCDLR2_RESERVED_24_16_SHIFT (16U)
22874/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
22875 */
22876#define DDRPHY_DX1LCDLR2_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX1LCDLR2_RESERVED_24_16_MASK)
22877#define DDRPHY_DX1LCDLR2_RESERVED_31_25_MASK (0xFE000000U)
22878#define DDRPHY_DX1LCDLR2_RESERVED_31_25_SHIFT (25U)
22879/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
22880 */
22881#define DDRPHY_DX1LCDLR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX1LCDLR2_RESERVED_31_25_MASK)
22882/*! @} */
22883
22884/*! @name DX1LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */
22885/*! @{ */
22886#define DDRPHY_DX1LCDLR3_RDQSD_MASK (0x1FFU)
22887#define DDRPHY_DX1LCDLR3_RDQSD_SHIFT (0U)
22888/*! RDQSD - Read DQS Delay
22889 */
22890#define DDRPHY_DX1LCDLR3_RDQSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX1LCDLR3_RDQSD_MASK)
22891#define DDRPHY_DX1LCDLR3_RESERVED_15_9_MASK (0xFE00U)
22892#define DDRPHY_DX1LCDLR3_RESERVED_15_9_SHIFT (9U)
22893/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
22894 */
22895#define DDRPHY_DX1LCDLR3_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX1LCDLR3_RESERVED_15_9_MASK)
22896#define DDRPHY_DX1LCDLR3_RESERVED_24_16_MASK (0x1FF0000U)
22897#define DDRPHY_DX1LCDLR3_RESERVED_24_16_SHIFT (16U)
22898/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
22899 */
22900#define DDRPHY_DX1LCDLR3_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX1LCDLR3_RESERVED_24_16_MASK)
22901#define DDRPHY_DX1LCDLR3_RESERVED_31_25_MASK (0xFE000000U)
22902#define DDRPHY_DX1LCDLR3_RESERVED_31_25_SHIFT (25U)
22903/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
22904 */
22905#define DDRPHY_DX1LCDLR3_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX1LCDLR3_RESERVED_31_25_MASK)
22906/*! @} */
22907
22908/*! @name DX1LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */
22909/*! @{ */
22910#define DDRPHY_DX1LCDLR4_RDQSND_MASK (0x1FFU)
22911#define DDRPHY_DX1LCDLR4_RDQSND_SHIFT (0U)
22912/*! RDQSND - Read DQSN Delay
22913 */
22914#define DDRPHY_DX1LCDLR4_RDQSND(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX1LCDLR4_RDQSND_MASK)
22915#define DDRPHY_DX1LCDLR4_RESERVED_15_9_MASK (0xFE00U)
22916#define DDRPHY_DX1LCDLR4_RESERVED_15_9_SHIFT (9U)
22917/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
22918 */
22919#define DDRPHY_DX1LCDLR4_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX1LCDLR4_RESERVED_15_9_MASK)
22920#define DDRPHY_DX1LCDLR4_RESERVED_24_16_MASK (0x1FF0000U)
22921#define DDRPHY_DX1LCDLR4_RESERVED_24_16_SHIFT (16U)
22922/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
22923 */
22924#define DDRPHY_DX1LCDLR4_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX1LCDLR4_RESERVED_24_16_MASK)
22925#define DDRPHY_DX1LCDLR4_RESERVED_31_25_MASK (0xFE000000U)
22926#define DDRPHY_DX1LCDLR4_RESERVED_31_25_SHIFT (25U)
22927/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
22928 */
22929#define DDRPHY_DX1LCDLR4_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX1LCDLR4_RESERVED_31_25_MASK)
22930/*! @} */
22931
22932/*! @name DX1LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */
22933/*! @{ */
22934#define DDRPHY_DX1LCDLR5_DQSGSD_MASK (0x1FFU)
22935#define DDRPHY_DX1LCDLR5_DQSGSD_SHIFT (0U)
22936/*! DQSGSD - DQS Gating Status Delay
22937 */
22938#define DDRPHY_DX1LCDLR5_DQSGSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX1LCDLR5_DQSGSD_MASK)
22939#define DDRPHY_DX1LCDLR5_RESERVED_15_9_MASK (0xFE00U)
22940#define DDRPHY_DX1LCDLR5_RESERVED_15_9_SHIFT (9U)
22941/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
22942 */
22943#define DDRPHY_DX1LCDLR5_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX1LCDLR5_RESERVED_15_9_MASK)
22944#define DDRPHY_DX1LCDLR5_RESERVED_24_16_MASK (0x1FF0000U)
22945#define DDRPHY_DX1LCDLR5_RESERVED_24_16_SHIFT (16U)
22946/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
22947 */
22948#define DDRPHY_DX1LCDLR5_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX1LCDLR5_RESERVED_24_16_MASK)
22949#define DDRPHY_DX1LCDLR5_RESERVED_31_25_MASK (0xFE000000U)
22950#define DDRPHY_DX1LCDLR5_RESERVED_31_25_SHIFT (25U)
22951/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
22952 */
22953#define DDRPHY_DX1LCDLR5_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX1LCDLR5_RESERVED_31_25_MASK)
22954/*! @} */
22955
22956/*! @name DX1MDLR0 - DATX8 n Master Delay Line Register 0 */
22957/*! @{ */
22958#define DDRPHY_DX1MDLR0_IPRD_MASK (0x1FFU)
22959#define DDRPHY_DX1MDLR0_IPRD_SHIFT (0U)
22960/*! IPRD - Initial Period
22961 */
22962#define DDRPHY_DX1MDLR0_IPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1MDLR0_IPRD_SHIFT)) & DDRPHY_DX1MDLR0_IPRD_MASK)
22963#define DDRPHY_DX1MDLR0_RESERVED_15_9_MASK (0xFE00U)
22964#define DDRPHY_DX1MDLR0_RESERVED_15_9_SHIFT (9U)
22965/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
22966 */
22967#define DDRPHY_DX1MDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX1MDLR0_RESERVED_15_9_MASK)
22968#define DDRPHY_DX1MDLR0_TPRD_MASK (0x1FF0000U)
22969#define DDRPHY_DX1MDLR0_TPRD_SHIFT (16U)
22970/*! TPRD - Target Period
22971 */
22972#define DDRPHY_DX1MDLR0_TPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1MDLR0_TPRD_SHIFT)) & DDRPHY_DX1MDLR0_TPRD_MASK)
22973#define DDRPHY_DX1MDLR0_RESERVED_31_25_MASK (0xFE000000U)
22974#define DDRPHY_DX1MDLR0_RESERVED_31_25_SHIFT (25U)
22975/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
22976 */
22977#define DDRPHY_DX1MDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX1MDLR0_RESERVED_31_25_MASK)
22978/*! @} */
22979
22980/*! @name DX1MDLR1 - DATX8 n Master Delay Line Register 1 */
22981/*! @{ */
22982#define DDRPHY_DX1MDLR1_MDLD_MASK (0x1FFU)
22983#define DDRPHY_DX1MDLR1_MDLD_SHIFT (0U)
22984/*! MDLD - MDL Delay
22985 */
22986#define DDRPHY_DX1MDLR1_MDLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1MDLR1_MDLD_SHIFT)) & DDRPHY_DX1MDLR1_MDLD_MASK)
22987#define DDRPHY_DX1MDLR1_RESERVED_31_9_MASK (0xFFFFFE00U)
22988#define DDRPHY_DX1MDLR1_RESERVED_31_9_SHIFT (9U)
22989/*! RESERVED_31_9 - Reserved. Return zeroes on reads.
22990 */
22991#define DDRPHY_DX1MDLR1_RESERVED_31_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX1MDLR1_RESERVED_31_9_MASK)
22992/*! @} */
22993
22994/*! @name DX1GTR0 - DATX8 n General Timing Register 0 */
22995/*! @{ */
22996#define DDRPHY_DX1GTR0_DGSL_MASK (0x1FU)
22997#define DDRPHY_DX1GTR0_DGSL_SHIFT (0U)
22998/*! DGSL - DQS Gating System Latency
22999 */
23000#define DDRPHY_DX1GTR0_DGSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_DGSL_SHIFT)) & DDRPHY_DX1GTR0_DGSL_MASK)
23001#define DDRPHY_DX1GTR0_RESERVED_7_5_MASK (0xE0U)
23002#define DDRPHY_DX1GTR0_RESERVED_7_5_SHIFT (5U)
23003/*! RESERVED_7_5 - Reserved. Return zeroes on reads.
23004 */
23005#define DDRPHY_DX1GTR0_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX1GTR0_RESERVED_7_5_MASK)
23006#define DDRPHY_DX1GTR0_RESERVED_12_8_MASK (0x1F00U)
23007#define DDRPHY_DX1GTR0_RESERVED_12_8_SHIFT (8U)
23008/*! RESERVED_12_8 - Reserved. Caution, do not write to this register field.
23009 */
23010#define DDRPHY_DX1GTR0_RESERVED_12_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX1GTR0_RESERVED_12_8_MASK)
23011#define DDRPHY_DX1GTR0_RESERVED_15_13_MASK (0xE000U)
23012#define DDRPHY_DX1GTR0_RESERVED_15_13_SHIFT (13U)
23013/*! RESERVED_15_13 - Reserved. Return zeroes on reads.
23014 */
23015#define DDRPHY_DX1GTR0_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX1GTR0_RESERVED_15_13_MASK)
23016#define DDRPHY_DX1GTR0_WLSL_MASK (0xF0000U)
23017#define DDRPHY_DX1GTR0_WLSL_SHIFT (16U)
23018/*! WLSL - Write Leveling System Latency
23019 */
23020#define DDRPHY_DX1GTR0_WLSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_WLSL_SHIFT)) & DDRPHY_DX1GTR0_WLSL_MASK)
23021#define DDRPHY_DX1GTR0_RESERVED_23_20_MASK (0xF00000U)
23022#define DDRPHY_DX1GTR0_RESERVED_23_20_SHIFT (20U)
23023/*! RESERVED_23_20 - Reserved. Caution, do not write to this register field.
23024 */
23025#define DDRPHY_DX1GTR0_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX1GTR0_RESERVED_23_20_MASK)
23026#define DDRPHY_DX1GTR0_WDQSL_MASK (0x7000000U)
23027#define DDRPHY_DX1GTR0_WDQSL_SHIFT (24U)
23028/*! WDQSL - DQ Write Path Latency Pipeline
23029 */
23030#define DDRPHY_DX1GTR0_WDQSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_WDQSL_SHIFT)) & DDRPHY_DX1GTR0_WDQSL_MASK)
23031#define DDRPHY_DX1GTR0_RESERVED_31_24_MASK (0xF8000000U)
23032#define DDRPHY_DX1GTR0_RESERVED_31_24_SHIFT (27U)
23033/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
23034 */
23035#define DDRPHY_DX1GTR0_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX1GTR0_RESERVED_31_24_MASK)
23036/*! @} */
23037
23038/*! @name DX1RSR0 - DATX8 n Rank Status Register 0 */
23039/*! @{ */
23040#define DDRPHY_DX1RSR0_QSGERR_MASK (0xFFFFU)
23041#define DDRPHY_DX1RSR0_QSGERR_SHIFT (0U)
23042/*! QSGERR - DQS Gate Training Error
23043 */
23044#define DDRPHY_DX1RSR0_QSGERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR0_QSGERR_SHIFT)) & DDRPHY_DX1RSR0_QSGERR_MASK)
23045#define DDRPHY_DX1RSR0_RESERVED_31_16_MASK (0xFFFF0000U)
23046#define DDRPHY_DX1RSR0_RESERVED_31_16_SHIFT (16U)
23047/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
23048 */
23049#define DDRPHY_DX1RSR0_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX1RSR0_RESERVED_31_16_MASK)
23050/*! @} */
23051
23052/*! @name DX1RSR1 - DATX8 n Rank Status Register 1 */
23053/*! @{ */
23054#define DDRPHY_DX1RSR1_RDLVLERR_MASK (0xFFFFU)
23055#define DDRPHY_DX1RSR1_RDLVLERR_SHIFT (0U)
23056/*! RDLVLERR - Read Leveling Error
23057 */
23058#define DDRPHY_DX1RSR1_RDLVLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX1RSR1_RDLVLERR_MASK)
23059#define DDRPHY_DX1RSR1_RESERVED_31_16_MASK (0xFFFF0000U)
23060#define DDRPHY_DX1RSR1_RESERVED_31_16_SHIFT (16U)
23061/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
23062 */
23063#define DDRPHY_DX1RSR1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX1RSR1_RESERVED_31_16_MASK)
23064/*! @} */
23065
23066/*! @name DX1RSR2 - DATX8 n Rank Status Register 2 */
23067/*! @{ */
23068#define DDRPHY_DX1RSR2_WLAWN_MASK (0xFFFFU)
23069#define DDRPHY_DX1RSR2_WLAWN_SHIFT (0U)
23070/*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning
23071 */
23072#define DDRPHY_DX1RSR2_WLAWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR2_WLAWN_SHIFT)) & DDRPHY_DX1RSR2_WLAWN_MASK)
23073#define DDRPHY_DX1RSR2_RESERVED_31_16_MASK (0xFFFF0000U)
23074#define DDRPHY_DX1RSR2_RESERVED_31_16_SHIFT (16U)
23075/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
23076 */
23077#define DDRPHY_DX1RSR2_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX1RSR2_RESERVED_31_16_MASK)
23078/*! @} */
23079
23080/*! @name DX1RSR3 - DATX8 n Rank Status Register 3 */
23081/*! @{ */
23082#define DDRPHY_DX1RSR3_WLAERR_MASK (0xFFFFU)
23083#define DDRPHY_DX1RSR3_WLAERR_SHIFT (0U)
23084/*! WLAERR - Write Leveling Adjustment Error
23085 */
23086#define DDRPHY_DX1RSR3_WLAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR3_WLAERR_SHIFT)) & DDRPHY_DX1RSR3_WLAERR_MASK)
23087#define DDRPHY_DX1RSR3_RESERVED_31_16_MASK (0xFFFF0000U)
23088#define DDRPHY_DX1RSR3_RESERVED_31_16_SHIFT (16U)
23089/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
23090 */
23091#define DDRPHY_DX1RSR3_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX1RSR3_RESERVED_31_16_MASK)
23092/*! @} */
23093
23094/*! @name DX1GSR0 - DATX8 n General Status Register 0 */
23095/*! @{ */
23096#define DDRPHY_DX1GSR0_WDQCAL_MASK (0x1U)
23097#define DDRPHY_DX1GSR0_WDQCAL_SHIFT (0U)
23098/*! WDQCAL - Write DQ Calibration
23099 */
23100#define DDRPHY_DX1GSR0_WDQCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_WDQCAL_SHIFT)) & DDRPHY_DX1GSR0_WDQCAL_MASK)
23101#define DDRPHY_DX1GSR0_RDQSCAL_MASK (0x2U)
23102#define DDRPHY_DX1GSR0_RDQSCAL_SHIFT (1U)
23103/*! RDQSCAL - Read DQS Calibration
23104 */
23105#define DDRPHY_DX1GSR0_RDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX1GSR0_RDQSCAL_MASK)
23106#define DDRPHY_DX1GSR0_RDQSNCAL_MASK (0x4U)
23107#define DDRPHY_DX1GSR0_RDQSNCAL_SHIFT (2U)
23108/*! RDQSNCAL - Read DQS# Calibration
23109 */
23110#define DDRPHY_DX1GSR0_RDQSNCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX1GSR0_RDQSNCAL_MASK)
23111#define DDRPHY_DX1GSR0_GDQSCAL_MASK (0x8U)
23112#define DDRPHY_DX1GSR0_GDQSCAL_SHIFT (3U)
23113/*! GDQSCAL - Read DQS gating Calibration
23114 */
23115#define DDRPHY_DX1GSR0_GDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX1GSR0_GDQSCAL_MASK)
23116#define DDRPHY_DX1GSR0_WLCAL_MASK (0x10U)
23117#define DDRPHY_DX1GSR0_WLCAL_SHIFT (4U)
23118/*! WLCAL - Write Leveling Calibration
23119 */
23120#define DDRPHY_DX1GSR0_WLCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_WLCAL_SHIFT)) & DDRPHY_DX1GSR0_WLCAL_MASK)
23121#define DDRPHY_DX1GSR0_WLDONE_MASK (0x20U)
23122#define DDRPHY_DX1GSR0_WLDONE_SHIFT (5U)
23123/*! WLDONE - Write Leveling Done
23124 */
23125#define DDRPHY_DX1GSR0_WLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_WLDONE_SHIFT)) & DDRPHY_DX1GSR0_WLDONE_MASK)
23126#define DDRPHY_DX1GSR0_WLERR_MASK (0x40U)
23127#define DDRPHY_DX1GSR0_WLERR_SHIFT (6U)
23128/*! WLERR - Write Leveling Error
23129 */
23130#define DDRPHY_DX1GSR0_WLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_WLERR_SHIFT)) & DDRPHY_DX1GSR0_WLERR_MASK)
23131#define DDRPHY_DX1GSR0_WLPRD_MASK (0xFF80U)
23132#define DDRPHY_DX1GSR0_WLPRD_SHIFT (7U)
23133/*! WLPRD - Write Leveling Period
23134 */
23135#define DDRPHY_DX1GSR0_WLPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_WLPRD_SHIFT)) & DDRPHY_DX1GSR0_WLPRD_MASK)
23136#define DDRPHY_DX1GSR0_DPLOCK_MASK (0x10000U)
23137#define DDRPHY_DX1GSR0_DPLOCK_SHIFT (16U)
23138/*! DPLOCK - DATX8 PLL Lock
23139 */
23140#define DDRPHY_DX1GSR0_DPLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_DPLOCK_SHIFT)) & DDRPHY_DX1GSR0_DPLOCK_MASK)
23141#define DDRPHY_DX1GSR0_GDQSPRD_MASK (0x3FE0000U)
23142#define DDRPHY_DX1GSR0_GDQSPRD_SHIFT (17U)
23143/*! GDQSPRD - Read DQS gating Period
23144 */
23145#define DDRPHY_DX1GSR0_GDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX1GSR0_GDQSPRD_MASK)
23146#define DDRPHY_DX1GSR0_RESERVED_29_26_MASK (0x3C000000U)
23147#define DDRPHY_DX1GSR0_RESERVED_29_26_SHIFT (26U)
23148/*! RESERVED_29_26 - Reserved. Returns zeroes on reads.
23149 */
23150#define DDRPHY_DX1GSR0_RESERVED_29_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX1GSR0_RESERVED_29_26_MASK)
23151#define DDRPHY_DX1GSR0_WLDQ_MASK (0x40000000U)
23152#define DDRPHY_DX1GSR0_WLDQ_SHIFT (30U)
23153/*! WLDQ - Write Leveling DQ Status
23154 */
23155#define DDRPHY_DX1GSR0_WLDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_WLDQ_SHIFT)) & DDRPHY_DX1GSR0_WLDQ_MASK)
23156#define DDRPHY_DX1GSR0_RESERVED_31_MASK (0x80000000U)
23157#define DDRPHY_DX1GSR0_RESERVED_31_SHIFT (31U)
23158/*! RESERVED_31 - Reserved. Returns zeroes on reads.
23159 */
23160#define DDRPHY_DX1GSR0_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX1GSR0_RESERVED_31_MASK)
23161/*! @} */
23162
23163/*! @name DX1GSR1 - DATX8 n General Status Register 1 */
23164/*! @{ */
23165#define DDRPHY_DX1GSR1_DLTDONE_MASK (0x1U)
23166#define DDRPHY_DX1GSR1_DLTDONE_SHIFT (0U)
23167/*! DLTDONE - Delay Line Test Done
23168 */
23169#define DDRPHY_DX1GSR1_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR1_DLTDONE_SHIFT)) & DDRPHY_DX1GSR1_DLTDONE_MASK)
23170#define DDRPHY_DX1GSR1_DLTCODE_MASK (0x1FFFFFEU)
23171#define DDRPHY_DX1GSR1_DLTCODE_SHIFT (1U)
23172/*! DLTCODE - Delay Line Test Code
23173 */
23174#define DDRPHY_DX1GSR1_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR1_DLTCODE_SHIFT)) & DDRPHY_DX1GSR1_DLTCODE_MASK)
23175#define DDRPHY_DX1GSR1_RESERVED_31_25_MASK (0xFE000000U)
23176#define DDRPHY_DX1GSR1_RESERVED_31_25_SHIFT (25U)
23177/*! RESERVED_31_25 - Reserved. Returns zeroes on reads.
23178 */
23179#define DDRPHY_DX1GSR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX1GSR1_RESERVED_31_25_MASK)
23180/*! @} */
23181
23182/*! @name DX1GSR2 - DATX8 n General Status Register 2 */
23183/*! @{ */
23184#define DDRPHY_DX1GSR2_RDERR_MASK (0x1U)
23185#define DDRPHY_DX1GSR2_RDERR_SHIFT (0U)
23186/*! RDERR - Read Bit Deskew Error
23187 */
23188#define DDRPHY_DX1GSR2_RDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_RDERR_SHIFT)) & DDRPHY_DX1GSR2_RDERR_MASK)
23189#define DDRPHY_DX1GSR2_RDWN_MASK (0x2U)
23190#define DDRPHY_DX1GSR2_RDWN_SHIFT (1U)
23191/*! RDWN - Read Bit Deskew Warning
23192 */
23193#define DDRPHY_DX1GSR2_RDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_RDWN_SHIFT)) & DDRPHY_DX1GSR2_RDWN_MASK)
23194#define DDRPHY_DX1GSR2_WDERR_MASK (0x4U)
23195#define DDRPHY_DX1GSR2_WDERR_SHIFT (2U)
23196/*! WDERR - Write Bit Deskew Error
23197 */
23198#define DDRPHY_DX1GSR2_WDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_WDERR_SHIFT)) & DDRPHY_DX1GSR2_WDERR_MASK)
23199#define DDRPHY_DX1GSR2_WDWN_MASK (0x8U)
23200#define DDRPHY_DX1GSR2_WDWN_SHIFT (3U)
23201/*! WDWN - Write Bit Deskew Warning
23202 */
23203#define DDRPHY_DX1GSR2_WDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_WDWN_SHIFT)) & DDRPHY_DX1GSR2_WDWN_MASK)
23204#define DDRPHY_DX1GSR2_REERR_MASK (0x10U)
23205#define DDRPHY_DX1GSR2_REERR_SHIFT (4U)
23206/*! REERR - Read Eye Centering Error
23207 */
23208#define DDRPHY_DX1GSR2_REERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_REERR_SHIFT)) & DDRPHY_DX1GSR2_REERR_MASK)
23209#define DDRPHY_DX1GSR2_REWN_MASK (0x20U)
23210#define DDRPHY_DX1GSR2_REWN_SHIFT (5U)
23211/*! REWN - Read Eye Centering Warning
23212 */
23213#define DDRPHY_DX1GSR2_REWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_REWN_SHIFT)) & DDRPHY_DX1GSR2_REWN_MASK)
23214#define DDRPHY_DX1GSR2_WEERR_MASK (0x40U)
23215#define DDRPHY_DX1GSR2_WEERR_SHIFT (6U)
23216/*! WEERR - Write Eye Centering Error
23217 */
23218#define DDRPHY_DX1GSR2_WEERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_WEERR_SHIFT)) & DDRPHY_DX1GSR2_WEERR_MASK)
23219#define DDRPHY_DX1GSR2_WEWN_MASK (0x80U)
23220#define DDRPHY_DX1GSR2_WEWN_SHIFT (7U)
23221/*! WEWN - Write Eye Centering Warning
23222 */
23223#define DDRPHY_DX1GSR2_WEWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_WEWN_SHIFT)) & DDRPHY_DX1GSR2_WEWN_MASK)
23224#define DDRPHY_DX1GSR2_ESTAT_MASK (0xF00U)
23225#define DDRPHY_DX1GSR2_ESTAT_SHIFT (8U)
23226/*! ESTAT - Error Status
23227 */
23228#define DDRPHY_DX1GSR2_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_ESTAT_SHIFT)) & DDRPHY_DX1GSR2_ESTAT_MASK)
23229#define DDRPHY_DX1GSR2_DQS2DQERR_MASK (0xFF000U)
23230#define DDRPHY_DX1GSR2_DQS2DQERR_SHIFT (12U)
23231/*! DQS2DQERR - Write DQS2DQ Training Error
23232 */
23233#define DDRPHY_DX1GSR2_DQS2DQERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX1GSR2_DQS2DQERR_MASK)
23234#define DDRPHY_DX1GSR2_SRDERR_MASK (0x100000U)
23235#define DDRPHY_DX1GSR2_SRDERR_SHIFT (20U)
23236/*! SRDERR - Static Read Error
23237 */
23238#define DDRPHY_DX1GSR2_SRDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_SRDERR_SHIFT)) & DDRPHY_DX1GSR2_SRDERR_MASK)
23239#define DDRPHY_DX1GSR2_RESERVED_21_MASK (0x200000U)
23240#define DDRPHY_DX1GSR2_RESERVED_21_SHIFT (21U)
23241/*! RESERVED_21 - Reserved. Return zeroes on reads.
23242 */
23243#define DDRPHY_DX1GSR2_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX1GSR2_RESERVED_21_MASK)
23244#define DDRPHY_DX1GSR2_GSDQSCAL_MASK (0x400000U)
23245#define DDRPHY_DX1GSR2_GSDQSCAL_SHIFT (22U)
23246/*! GSDQSCAL - Read DQS Gating Status Calibration
23247 */
23248#define DDRPHY_DX1GSR2_GSDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX1GSR2_GSDQSCAL_MASK)
23249#define DDRPHY_DX1GSR2_GSDQSPRD_MASK (0xFF800000U)
23250#define DDRPHY_DX1GSR2_GSDQSPRD_SHIFT (23U)
23251/*! GSDQSPRD - Read DQS gating Status Period
23252 */
23253#define DDRPHY_DX1GSR2_GSDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX1GSR2_GSDQSPRD_MASK)
23254/*! @} */
23255
23256/*! @name DX1GSR3 - DATX8 n General Status Register 3 */
23257/*! @{ */
23258#define DDRPHY_DX1GSR3_SRDPC_MASK (0x3U)
23259#define DDRPHY_DX1GSR3_SRDPC_SHIFT (0U)
23260/*! SRDPC - Static Read Delay Pass Count
23261 */
23262#define DDRPHY_DX1GSR3_SRDPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_SRDPC_SHIFT)) & DDRPHY_DX1GSR3_SRDPC_MASK)
23263#define DDRPHY_DX1GSR3_RESERVED_7_2_MASK (0xFCU)
23264#define DDRPHY_DX1GSR3_RESERVED_7_2_SHIFT (2U)
23265/*! RESERVED_7_2 - Reserved. Return zeroes on reads.
23266 */
23267#define DDRPHY_DX1GSR3_RESERVED_7_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX1GSR3_RESERVED_7_2_MASK)
23268#define DDRPHY_DX1GSR3_HVERR_MASK (0xF00U)
23269#define DDRPHY_DX1GSR3_HVERR_SHIFT (8U)
23270/*! HVERR - Host VREF Training Error
23271 */
23272#define DDRPHY_DX1GSR3_HVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_HVERR_SHIFT)) & DDRPHY_DX1GSR3_HVERR_MASK)
23273#define DDRPHY_DX1GSR3_HVWRN_MASK (0xF000U)
23274#define DDRPHY_DX1GSR3_HVWRN_SHIFT (12U)
23275/*! HVWRN - Host VREF Training Warning
23276 */
23277#define DDRPHY_DX1GSR3_HVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_HVWRN_SHIFT)) & DDRPHY_DX1GSR3_HVWRN_MASK)
23278#define DDRPHY_DX1GSR3_DVERR_MASK (0xF0000U)
23279#define DDRPHY_DX1GSR3_DVERR_SHIFT (16U)
23280/*! DVERR - DRAM VREF Training Error
23281 */
23282#define DDRPHY_DX1GSR3_DVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_DVERR_SHIFT)) & DDRPHY_DX1GSR3_DVERR_MASK)
23283#define DDRPHY_DX1GSR3_DVWRN_MASK (0xF00000U)
23284#define DDRPHY_DX1GSR3_DVWRN_SHIFT (20U)
23285/*! DVWRN - DRAM VREF Training Warning
23286 */
23287#define DDRPHY_DX1GSR3_DVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_DVWRN_SHIFT)) & DDRPHY_DX1GSR3_DVWRN_MASK)
23288#define DDRPHY_DX1GSR3_ESTAT_MASK (0x7000000U)
23289#define DDRPHY_DX1GSR3_ESTAT_SHIFT (24U)
23290/*! ESTAT - VREF Training Error Status Code
23291 */
23292#define DDRPHY_DX1GSR3_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_ESTAT_SHIFT)) & DDRPHY_DX1GSR3_ESTAT_MASK)
23293#define DDRPHY_DX1GSR3_RESERVED_31_27_MASK (0xF8000000U)
23294#define DDRPHY_DX1GSR3_RESERVED_31_27_SHIFT (27U)
23295/*! RESERVED_31_27 - Reserved. Return zeroes on reads.
23296 */
23297#define DDRPHY_DX1GSR3_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX1GSR3_RESERVED_31_27_MASK)
23298/*! @} */
23299
23300/*! @name DX1GSR4 - DATX8 n General Status Register 4 */
23301/*! @{ */
23302#define DDRPHY_DX1GSR4_RESERVED_0_MASK (0x1U)
23303#define DDRPHY_DX1GSR4_RESERVED_0_SHIFT (0U)
23304/*! RESERVED_0 - Reserved. Return zeroes on reads.
23305 */
23306#define DDRPHY_DX1GSR4_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_0_MASK)
23307#define DDRPHY_DX1GSR4_RESERVED_1_MASK (0x2U)
23308#define DDRPHY_DX1GSR4_RESERVED_1_SHIFT (1U)
23309/*! RESERVED_1 - Reserved. Return zeroes on reads.
23310 */
23311#define DDRPHY_DX1GSR4_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_1_MASK)
23312#define DDRPHY_DX1GSR4_RESERVED_2_MASK (0x4U)
23313#define DDRPHY_DX1GSR4_RESERVED_2_SHIFT (2U)
23314/*! RESERVED_2 - Reserved. Return zeroes on reads.
23315 */
23316#define DDRPHY_DX1GSR4_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_2_MASK)
23317#define DDRPHY_DX1GSR4_RESERVED_3_MASK (0x8U)
23318#define DDRPHY_DX1GSR4_RESERVED_3_SHIFT (3U)
23319/*! RESERVED_3 - Reserved. Return zeroes on reads.
23320 */
23321#define DDRPHY_DX1GSR4_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_3_MASK)
23322#define DDRPHY_DX1GSR4_RESERVED_4_MASK (0x10U)
23323#define DDRPHY_DX1GSR4_RESERVED_4_SHIFT (4U)
23324/*! RESERVED_4 - Reserved. Return zeroes on reads.
23325 */
23326#define DDRPHY_DX1GSR4_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_4_MASK)
23327#define DDRPHY_DX1GSR4_RESERVED_5_MASK (0x20U)
23328#define DDRPHY_DX1GSR4_RESERVED_5_SHIFT (5U)
23329/*! RESERVED_5 - Reserved. Return zeroes on reads.
23330 */
23331#define DDRPHY_DX1GSR4_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_5_MASK)
23332#define DDRPHY_DX1GSR4_RESERVED_6_MASK (0x40U)
23333#define DDRPHY_DX1GSR4_RESERVED_6_SHIFT (6U)
23334/*! RESERVED_6 - Reserved. Return zeroes on reads.
23335 */
23336#define DDRPHY_DX1GSR4_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_6_MASK)
23337#define DDRPHY_DX1GSR4_RESERVED_15_7_MASK (0xFF80U)
23338#define DDRPHY_DX1GSR4_RESERVED_15_7_SHIFT (7U)
23339/*! RESERVED_15_7 - Reserved. Return zeroes on reads.
23340 */
23341#define DDRPHY_DX1GSR4_RESERVED_15_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_15_7_MASK)
23342#define DDRPHY_DX1GSR4_RESERVED_16_MASK (0x10000U)
23343#define DDRPHY_DX1GSR4_RESERVED_16_SHIFT (16U)
23344/*! RESERVED_16 - Reserved. Return zeroes on reads.
23345 */
23346#define DDRPHY_DX1GSR4_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_16_MASK)
23347#define DDRPHY_DX1GSR4_RESERVED_25_17_MASK (0x3FE0000U)
23348#define DDRPHY_DX1GSR4_RESERVED_25_17_SHIFT (17U)
23349/*! RESERVED_25_17 - Reserved. Return zeroes on reads.
23350 */
23351#define DDRPHY_DX1GSR4_RESERVED_25_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_25_17_MASK)
23352#define DDRPHY_DX1GSR4_RESERVED_31_26_MASK (0xFC000000U)
23353#define DDRPHY_DX1GSR4_RESERVED_31_26_SHIFT (26U)
23354/*! RESERVED_31_26 - Reserved. Returns zeroes on reads.
23355 */
23356#define DDRPHY_DX1GSR4_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX1GSR4_RESERVED_31_26_MASK)
23357/*! @} */
23358
23359/*! @name DX1GSR5 - DATX8 n General Status Register 5 */
23360/*! @{ */
23361#define DDRPHY_DX1GSR5_RESERVED_0_MASK (0x1U)
23362#define DDRPHY_DX1GSR5_RESERVED_0_SHIFT (0U)
23363/*! RESERVED_0 - Reserved. Return zeroes on reads.
23364 */
23365#define DDRPHY_DX1GSR5_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_0_MASK)
23366#define DDRPHY_DX1GSR5_RESERVED_1_MASK (0x2U)
23367#define DDRPHY_DX1GSR5_RESERVED_1_SHIFT (1U)
23368/*! RESERVED_1 - Reserved. Return zeroes on reads.
23369 */
23370#define DDRPHY_DX1GSR5_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_1_MASK)
23371#define DDRPHY_DX1GSR5_RESERVED_2_MASK (0x4U)
23372#define DDRPHY_DX1GSR5_RESERVED_2_SHIFT (2U)
23373/*! RESERVED_2 - Reserved. Return zeroes on reads.
23374 */
23375#define DDRPHY_DX1GSR5_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_2_MASK)
23376#define DDRPHY_DX1GSR5_RESERVED_3_MASK (0x8U)
23377#define DDRPHY_DX1GSR5_RESERVED_3_SHIFT (3U)
23378/*! RESERVED_3 - Reserved. Return zeroes on reads.
23379 */
23380#define DDRPHY_DX1GSR5_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_3_MASK)
23381#define DDRPHY_DX1GSR5_RESERVED_4_MASK (0x10U)
23382#define DDRPHY_DX1GSR5_RESERVED_4_SHIFT (4U)
23383/*! RESERVED_4 - Reserved. Return zeroes on reads.
23384 */
23385#define DDRPHY_DX1GSR5_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_4_MASK)
23386#define DDRPHY_DX1GSR5_RESERVED_5_MASK (0x20U)
23387#define DDRPHY_DX1GSR5_RESERVED_5_SHIFT (5U)
23388/*! RESERVED_5 - Reserved. Return zeroes on reads.
23389 */
23390#define DDRPHY_DX1GSR5_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_5_MASK)
23391#define DDRPHY_DX1GSR5_RESERVED_6_MASK (0x40U)
23392#define DDRPHY_DX1GSR5_RESERVED_6_SHIFT (6U)
23393/*! RESERVED_6 - Reserved. Return zeroes on reads.
23394 */
23395#define DDRPHY_DX1GSR5_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_6_MASK)
23396#define DDRPHY_DX1GSR5_RESERVED_7_MASK (0x80U)
23397#define DDRPHY_DX1GSR5_RESERVED_7_SHIFT (7U)
23398/*! RESERVED_7 - Reserved. Return zeroes on reads.
23399 */
23400#define DDRPHY_DX1GSR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_7_MASK)
23401#define DDRPHY_DX1GSR5_RESERVED_11_8_MASK (0xF00U)
23402#define DDRPHY_DX1GSR5_RESERVED_11_8_SHIFT (8U)
23403/*! RESERVED_11_8 - Reserved. Return zeroes on reads.
23404 */
23405#define DDRPHY_DX1GSR5_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_11_8_MASK)
23406#define DDRPHY_DX1GSR5_RESERVED_19_12_MASK (0xFF000U)
23407#define DDRPHY_DX1GSR5_RESERVED_19_12_SHIFT (12U)
23408/*! RESERVED_19_12 - Reserved. Return zeroes on reads.
23409 */
23410#define DDRPHY_DX1GSR5_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_19_12_MASK)
23411#define DDRPHY_DX1GSR5_RESERVED_20_MASK (0x100000U)
23412#define DDRPHY_DX1GSR5_RESERVED_20_SHIFT (20U)
23413/*! RESERVED_20 - Reserved. Return zeroes on reads.
23414 */
23415#define DDRPHY_DX1GSR5_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_20_MASK)
23416#define DDRPHY_DX1GSR5_RESERVED_21_MASK (0x200000U)
23417#define DDRPHY_DX1GSR5_RESERVED_21_SHIFT (21U)
23418/*! RESERVED_21 - Reserved. Return zeroes on reads.
23419 */
23420#define DDRPHY_DX1GSR5_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_21_MASK)
23421#define DDRPHY_DX1GSR5_RESERVED_22_MASK (0x400000U)
23422#define DDRPHY_DX1GSR5_RESERVED_22_SHIFT (22U)
23423/*! RESERVED_22 - Reserved. Return zeroes on reads.
23424 */
23425#define DDRPHY_DX1GSR5_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_22_MASK)
23426#define DDRPHY_DX1GSR5_RESERVED_31_23_MASK (0xFF800000U)
23427#define DDRPHY_DX1GSR5_RESERVED_31_23_SHIFT (23U)
23428/*! RESERVED_31_23 - Reserved. Return zeroes on reads.
23429 */
23430#define DDRPHY_DX1GSR5_RESERVED_31_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX1GSR5_RESERVED_31_23_MASK)
23431/*! @} */
23432
23433/*! @name DX1GSR6 - DATX8 n General Status Register 6 */
23434/*! @{ */
23435#define DDRPHY_DX1GSR6_RESERVED_1_0_MASK (0x3U)
23436#define DDRPHY_DX1GSR6_RESERVED_1_0_SHIFT (0U)
23437/*! RESERVED_1_0 - Reserved. Return zeroes on reads.
23438 */
23439#define DDRPHY_DX1GSR6_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_1_0_MASK)
23440#define DDRPHY_DX1GSR6_RESERVED_3_2_MASK (0xCU)
23441#define DDRPHY_DX1GSR6_RESERVED_3_2_SHIFT (2U)
23442/*! RESERVED_3_2 - Reserved. Return zeroes on reads.
23443 */
23444#define DDRPHY_DX1GSR6_RESERVED_3_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_3_2_MASK)
23445#define DDRPHY_DX1GSR6_RESERVED_7_4_MASK (0xF0U)
23446#define DDRPHY_DX1GSR6_RESERVED_7_4_SHIFT (4U)
23447/*! RESERVED_7_4 - Reserved. Return zeroes on reads.
23448 */
23449#define DDRPHY_DX1GSR6_RESERVED_7_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_7_4_MASK)
23450#define DDRPHY_DX1GSR6_RESERVED_11_8_MASK (0xF00U)
23451#define DDRPHY_DX1GSR6_RESERVED_11_8_SHIFT (8U)
23452/*! RESERVED_11_8 - Reserved. Return zeroes on reads.
23453 */
23454#define DDRPHY_DX1GSR6_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_11_8_MASK)
23455#define DDRPHY_DX1GSR6_RESERVED_15_12_MASK (0xF000U)
23456#define DDRPHY_DX1GSR6_RESERVED_15_12_SHIFT (12U)
23457/*! RESERVED_15_12 - Reserved. Return zeroes on reads.
23458 */
23459#define DDRPHY_DX1GSR6_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_15_12_MASK)
23460#define DDRPHY_DX1GSR6_RESERVED_19_15_MASK (0xF0000U)
23461#define DDRPHY_DX1GSR6_RESERVED_19_15_SHIFT (16U)
23462/*! RESERVED_19_15 - Reserved. Return zeroes on reads.
23463 */
23464#define DDRPHY_DX1GSR6_RESERVED_19_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_19_15_MASK)
23465#define DDRPHY_DX1GSR6_RESERVED_23_20_MASK (0xF00000U)
23466#define DDRPHY_DX1GSR6_RESERVED_23_20_SHIFT (20U)
23467/*! RESERVED_23_20 - Reserved. Return zeroes on reads.
23468 */
23469#define DDRPHY_DX1GSR6_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_23_20_MASK)
23470#define DDRPHY_DX1GSR6_RESERVED_31_24_MASK (0xFF000000U)
23471#define DDRPHY_DX1GSR6_RESERVED_31_24_SHIFT (24U)
23472/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
23473 */
23474#define DDRPHY_DX1GSR6_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX1GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX1GSR6_RESERVED_31_24_MASK)
23475/*! @} */
23476
23477/*! @name DX2GCR0 - DATX8 n General Configuration Register 0 */
23478/*! @{ */
23479#define DDRPHY_DX2GCR0_RESERVED_1_0_MASK (0x3U)
23480#define DDRPHY_DX2GCR0_RESERVED_1_0_SHIFT (0U)
23481/*! RESERVED_1_0 - Reserved. Return zeroes on reads.
23482 */
23483#define DDRPHY_DX2GCR0_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX2GCR0_RESERVED_1_0_MASK)
23484#define DDRPHY_DX2GCR0_DQSGOE_MASK (0x4U)
23485#define DDRPHY_DX2GCR0_DQSGOE_SHIFT (2U)
23486/*! DQSGOE - DQSG Output Enable
23487 */
23488#define DDRPHY_DX2GCR0_DQSGOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSGOE_SHIFT)) & DDRPHY_DX2GCR0_DQSGOE_MASK)
23489#define DDRPHY_DX2GCR0_DQSGODT_MASK (0x8U)
23490#define DDRPHY_DX2GCR0_DQSGODT_SHIFT (3U)
23491/*! DQSGODT - DQSG On-Die Termination
23492 */
23493#define DDRPHY_DX2GCR0_DQSGODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSGODT_SHIFT)) & DDRPHY_DX2GCR0_DQSGODT_MASK)
23494#define DDRPHY_DX2GCR0_RESERVED_4_MASK (0x10U)
23495#define DDRPHY_DX2GCR0_RESERVED_4_SHIFT (4U)
23496/*! RESERVED_4 - Reserved. Return zeroes on reads.
23497 */
23498#define DDRPHY_DX2GCR0_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX2GCR0_RESERVED_4_MASK)
23499#define DDRPHY_DX2GCR0_DQSGPDR_MASK (0x20U)
23500#define DDRPHY_DX2GCR0_DQSGPDR_SHIFT (5U)
23501/*! DQSGPDR - DQSG Power Down Receiver
23502 */
23503#define DDRPHY_DX2GCR0_DQSGPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX2GCR0_DQSGPDR_MASK)
23504#define DDRPHY_DX2GCR0_DQSRPD_MASK (0x40U)
23505#define DDRPHY_DX2GCR0_DQSRPD_SHIFT (6U)
23506/*! DQSRPD - DQSR Power Down
23507 */
23508#define DDRPHY_DX2GCR0_DQSRPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSRPD_SHIFT)) & DDRPHY_DX2GCR0_DQSRPD_MASK)
23509#define DDRPHY_DX2GCR0_CPDRSHFT_MASK (0x180U)
23510#define DDRPHY_DX2GCR0_CPDRSHFT_SHIFT (7U)
23511/*! CPDRSHFT - Configurable PDR Phase Shift
23512 */
23513#define DDRPHY_DX2GCR0_CPDRSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX2GCR0_CPDRSHFT_MASK)
23514#define DDRPHY_DX2GCR0_RTTOH_MASK (0x600U)
23515#define DDRPHY_DX2GCR0_RTTOH_SHIFT (9U)
23516/*! RTTOH - RTT Output Hold
23517 */
23518#define DDRPHY_DX2GCR0_RTTOH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_RTTOH_SHIFT)) & DDRPHY_DX2GCR0_RTTOH_MASK)
23519#define DDRPHY_DX2GCR0_RTTOAL_MASK (0x800U)
23520#define DDRPHY_DX2GCR0_RTTOAL_SHIFT (11U)
23521/*! RTTOAL - RTT On Additive Latency
23522 */
23523#define DDRPHY_DX2GCR0_RTTOAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_RTTOAL_SHIFT)) & DDRPHY_DX2GCR0_RTTOAL_MASK)
23524#define DDRPHY_DX2GCR0_DQSSEPDR_MASK (0x1000U)
23525#define DDRPHY_DX2GCR0_DQSSEPDR_SHIFT (12U)
23526/*! DQSSEPDR - DQSSE Power Down Receiver
23527 */
23528#define DDRPHY_DX2GCR0_DQSSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX2GCR0_DQSSEPDR_MASK)
23529#define DDRPHY_DX2GCR0_DQSNSEPDR_MASK (0x2000U)
23530#define DDRPHY_DX2GCR0_DQSNSEPDR_SHIFT (13U)
23531/*! DQSNSEPDR - DQSNSE Power Down Receiver
23532 */
23533#define DDRPHY_DX2GCR0_DQSNSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX2GCR0_DQSNSEPDR_MASK)
23534#define DDRPHY_DX2GCR0_RESERVED_19_14_MASK (0xFC000U)
23535#define DDRPHY_DX2GCR0_RESERVED_19_14_SHIFT (14U)
23536/*! RESERVED_19_14 - Reserved. Return zeroes on reads.
23537 */
23538#define DDRPHY_DX2GCR0_RESERVED_19_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX2GCR0_RESERVED_19_14_MASK)
23539#define DDRPHY_DX2GCR0_RDDLY_MASK (0xF00000U)
23540#define DDRPHY_DX2GCR0_RDDLY_SHIFT (20U)
23541/*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
23542 */
23543#define DDRPHY_DX2GCR0_RDDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_RDDLY_SHIFT)) & DDRPHY_DX2GCR0_RDDLY_MASK)
23544#define DDRPHY_DX2GCR0_DQSDCC_MASK (0xF000000U)
23545#define DDRPHY_DX2GCR0_DQSDCC_SHIFT (24U)
23546/*! DQSDCC - DQS Duty Cycle Correction
23547 */
23548#define DDRPHY_DX2GCR0_DQSDCC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_DQSDCC_SHIFT)) & DDRPHY_DX2GCR0_DQSDCC_MASK)
23549#define DDRPHY_DX2GCR0_CODTSHFT_MASK (0x30000000U)
23550#define DDRPHY_DX2GCR0_CODTSHFT_SHIFT (28U)
23551/*! CODTSHFT - Configurable ODT(TE) Phase Shift
23552 */
23553#define DDRPHY_DX2GCR0_CODTSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX2GCR0_CODTSHFT_MASK)
23554#define DDRPHY_DX2GCR0_MDLEN_MASK (0x40000000U)
23555#define DDRPHY_DX2GCR0_MDLEN_SHIFT (30U)
23556/*! MDLEN - Master Delay Line Enable
23557 */
23558#define DDRPHY_DX2GCR0_MDLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_MDLEN_SHIFT)) & DDRPHY_DX2GCR0_MDLEN_MASK)
23559#define DDRPHY_DX2GCR0_CALBYP_MASK (0x80000000U)
23560#define DDRPHY_DX2GCR0_CALBYP_SHIFT (31U)
23561/*! CALBYP - Calibration Bypass
23562 */
23563#define DDRPHY_DX2GCR0_CALBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR0_CALBYP_SHIFT)) & DDRPHY_DX2GCR0_CALBYP_MASK)
23564/*! @} */
23565
23566/*! @name DX2GCR1 - DATX8 n General Configuration Register 1 */
23567/*! @{ */
23568#define DDRPHY_DX2GCR1_DQEN_MASK (0xFFU)
23569#define DDRPHY_DX2GCR1_DQEN_SHIFT (0U)
23570/*! DQEN - Enables DQ corresponding to each bit in a byte
23571 */
23572#define DDRPHY_DX2GCR1_DQEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_DQEN_SHIFT)) & DDRPHY_DX2GCR1_DQEN_MASK)
23573#define DDRPHY_DX2GCR1_DMEN_MASK (0x100U)
23574#define DDRPHY_DX2GCR1_DMEN_SHIFT (8U)
23575/*! DMEN - Enables DM pin in a byte lane
23576 */
23577#define DDRPHY_DX2GCR1_DMEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_DMEN_SHIFT)) & DDRPHY_DX2GCR1_DMEN_MASK)
23578#define DDRPHY_DX2GCR1_DSEN_MASK (0x200U)
23579#define DDRPHY_DX2GCR1_DSEN_SHIFT (9U)
23580/*! DSEN - Enables Write Data strobe in a byte lane
23581 */
23582#define DDRPHY_DX2GCR1_DSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_DSEN_SHIFT)) & DDRPHY_DX2GCR1_DSEN_MASK)
23583#define DDRPHY_DX2GCR1_TEEN_MASK (0x400U)
23584#define DDRPHY_DX2GCR1_TEEN_SHIFT (10U)
23585/*! TEEN - Enables ODT/TE in a byte lane
23586 */
23587#define DDRPHY_DX2GCR1_TEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_TEEN_SHIFT)) & DDRPHY_DX2GCR1_TEEN_MASK)
23588#define DDRPHY_DX2GCR1_PDREN_MASK (0x800U)
23589#define DDRPHY_DX2GCR1_PDREN_SHIFT (11U)
23590/*! PDREN - Enables PDR in a byte lane
23591 */
23592#define DDRPHY_DX2GCR1_PDREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_PDREN_SHIFT)) & DDRPHY_DX2GCR1_PDREN_MASK)
23593#define DDRPHY_DX2GCR1_OEEN_MASK (0x1000U)
23594#define DDRPHY_DX2GCR1_OEEN_SHIFT (12U)
23595/*! OEEN - Enables Read Data Strobe in a byte lane
23596 */
23597#define DDRPHY_DX2GCR1_OEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_OEEN_SHIFT)) & DDRPHY_DX2GCR1_OEEN_MASK)
23598#define DDRPHY_DX2GCR1_QSSEL_MASK (0x2000U)
23599#define DDRPHY_DX2GCR1_QSSEL_SHIFT (13U)
23600/*! QSSEL - Select the delayed or non-delayed read data strobe
23601 */
23602#define DDRPHY_DX2GCR1_QSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_QSSEL_SHIFT)) & DDRPHY_DX2GCR1_QSSEL_MASK)
23603#define DDRPHY_DX2GCR1_QSNSEL_MASK (0x4000U)
23604#define DDRPHY_DX2GCR1_QSNSEL_SHIFT (14U)
23605/*! QSNSEL - Select the delayed or non-delayed read data strobe #
23606 */
23607#define DDRPHY_DX2GCR1_QSNSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_QSNSEL_SHIFT)) & DDRPHY_DX2GCR1_QSNSEL_MASK)
23608#define DDRPHY_DX2GCR1_RESERVED_15_MASK (0x8000U)
23609#define DDRPHY_DX2GCR1_RESERVED_15_SHIFT (15U)
23610/*! RESERVED_15 - Reserved. Returns zeroes on reads.
23611 */
23612#define DDRPHY_DX2GCR1_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX2GCR1_RESERVED_15_MASK)
23613#define DDRPHY_DX2GCR1_DXPDRMODE_MASK (0xFFFF0000U)
23614#define DDRPHY_DX2GCR1_DXPDRMODE_SHIFT (16U)
23615/*! DXPDRMODE - Enables the PDR mode for DQ[7:0]
23616 */
23617#define DDRPHY_DX2GCR1_DXPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX2GCR1_DXPDRMODE_MASK)
23618/*! @} */
23619
23620/*! @name DX2GCR2 - DATX8 n General Configuration Register 2 */
23621/*! @{ */
23622#define DDRPHY_DX2GCR2_DXTEMODE_MASK (0xFFFFU)
23623#define DDRPHY_DX2GCR2_DXTEMODE_SHIFT (0U)
23624/*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0]
23625 */
23626#define DDRPHY_DX2GCR2_DXTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX2GCR2_DXTEMODE_MASK)
23627#define DDRPHY_DX2GCR2_DXOEMODE_MASK (0xFFFF0000U)
23628#define DDRPHY_DX2GCR2_DXOEMODE_SHIFT (16U)
23629/*! DXOEMODE - Enables the OE mode values for DQ[7:0]
23630 */
23631#define DDRPHY_DX2GCR2_DXOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX2GCR2_DXOEMODE_MASK)
23632/*! @} */
23633
23634/*! @name DX2GCR3 - DATX8 n General Configuration Register 3 */
23635/*! @{ */
23636#define DDRPHY_DX2GCR3_WDMBVT_MASK (0x1U)
23637#define DDRPHY_DX2GCR3_WDMBVT_SHIFT (0U)
23638/*! WDMBVT - Write Data Mask BDL VT Compensation
23639 */
23640#define DDRPHY_DX2GCR3_WDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_WDMBVT_SHIFT)) & DDRPHY_DX2GCR3_WDMBVT_MASK)
23641#define DDRPHY_DX2GCR3_RDMBVT_MASK (0x2U)
23642#define DDRPHY_DX2GCR3_RDMBVT_SHIFT (1U)
23643/*! RDMBVT - Read Data Mask BDL VT Compensation
23644 */
23645#define DDRPHY_DX2GCR3_RDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_RDMBVT_SHIFT)) & DDRPHY_DX2GCR3_RDMBVT_MASK)
23646#define DDRPHY_DX2GCR3_DSPDRMODE_MASK (0xCU)
23647#define DDRPHY_DX2GCR3_DSPDRMODE_SHIFT (2U)
23648/*! DSPDRMODE - Enables the PDR mode values for DQS.
23649 */
23650#define DDRPHY_DX2GCR3_DSPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX2GCR3_DSPDRMODE_MASK)
23651#define DDRPHY_DX2GCR3_DSTEMODE_MASK (0x30U)
23652#define DDRPHY_DX2GCR3_DSTEMODE_SHIFT (4U)
23653/*! DSTEMODE - Enables the TE mode values for DQS.
23654 */
23655#define DDRPHY_DX2GCR3_DSTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX2GCR3_DSTEMODE_MASK)
23656#define DDRPHY_DX2GCR3_DSOEMODE_MASK (0xC0U)
23657#define DDRPHY_DX2GCR3_DSOEMODE_SHIFT (6U)
23658/*! DSOEMODE - Enables the OE mode values for DQS.
23659 */
23660#define DDRPHY_DX2GCR3_DSOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX2GCR3_DSOEMODE_MASK)
23661#define DDRPHY_DX2GCR3_WDSBVT_MASK (0x100U)
23662#define DDRPHY_DX2GCR3_WDSBVT_SHIFT (8U)
23663/*! WDSBVT - Write Data Strobe BDL VT Compensation
23664 */
23665#define DDRPHY_DX2GCR3_WDSBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_WDSBVT_SHIFT)) & DDRPHY_DX2GCR3_WDSBVT_MASK)
23666#define DDRPHY_DX2GCR3_RESERVED_9_MASK (0x200U)
23667#define DDRPHY_DX2GCR3_RESERVED_9_SHIFT (9U)
23668/*! RESERVED_9 - Reserved. Returns zeroes on reads.
23669 */
23670#define DDRPHY_DX2GCR3_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX2GCR3_RESERVED_9_MASK)
23671#define DDRPHY_DX2GCR3_DMPDRMODE_MASK (0xC00U)
23672#define DDRPHY_DX2GCR3_DMPDRMODE_SHIFT (10U)
23673/*! DMPDRMODE - Enables the PDR mode values for DM.
23674 */
23675#define DDRPHY_DX2GCR3_DMPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX2GCR3_DMPDRMODE_MASK)
23676#define DDRPHY_DX2GCR3_DMTEMODE_MASK (0x3000U)
23677#define DDRPHY_DX2GCR3_DMTEMODE_SHIFT (12U)
23678/*! DMTEMODE - Enables the TE mode values for DM.
23679 */
23680#define DDRPHY_DX2GCR3_DMTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX2GCR3_DMTEMODE_MASK)
23681#define DDRPHY_DX2GCR3_DMOEMODE_MASK (0xC000U)
23682#define DDRPHY_DX2GCR3_DMOEMODE_SHIFT (14U)
23683/*! DMOEMODE - Enables the OE mode values for DM.
23684 */
23685#define DDRPHY_DX2GCR3_DMOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX2GCR3_DMOEMODE_MASK)
23686#define DDRPHY_DX2GCR3_DSNPDRMODE_MASK (0x30000U)
23687#define DDRPHY_DX2GCR3_DSNPDRMODE_SHIFT (16U)
23688/*! DSNPDRMODE - Enables the PDR mode for DQS
23689 */
23690#define DDRPHY_DX2GCR3_DSNPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX2GCR3_DSNPDRMODE_MASK)
23691#define DDRPHY_DX2GCR3_DSNTEMODE_MASK (0xC0000U)
23692#define DDRPHY_DX2GCR3_DSNTEMODE_SHIFT (18U)
23693/*! DSNTEMODE - Enables the TE mode for DQS
23694 */
23695#define DDRPHY_DX2GCR3_DSNTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX2GCR3_DSNTEMODE_MASK)
23696#define DDRPHY_DX2GCR3_DSNOEMODE_MASK (0x300000U)
23697#define DDRPHY_DX2GCR3_DSNOEMODE_SHIFT (20U)
23698/*! DSNOEMODE - Enables the OE mode for DQs
23699 */
23700#define DDRPHY_DX2GCR3_DSNOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX2GCR3_DSNOEMODE_MASK)
23701#define DDRPHY_DX2GCR3_PDRBVT_MASK (0x400000U)
23702#define DDRPHY_DX2GCR3_PDRBVT_SHIFT (22U)
23703/*! PDRBVT - Power Down Receiver BDL VT Compensation
23704 */
23705#define DDRPHY_DX2GCR3_PDRBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_PDRBVT_SHIFT)) & DDRPHY_DX2GCR3_PDRBVT_MASK)
23706#define DDRPHY_DX2GCR3_RGSLVT_MASK (0x800000U)
23707#define DDRPHY_DX2GCR3_RGSLVT_SHIFT (23U)
23708/*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation
23709 */
23710#define DDRPHY_DX2GCR3_RGSLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_RGSLVT_SHIFT)) & DDRPHY_DX2GCR3_RGSLVT_MASK)
23711#define DDRPHY_DX2GCR3_WLLVT_MASK (0x1000000U)
23712#define DDRPHY_DX2GCR3_WLLVT_SHIFT (24U)
23713/*! WLLVT - Write Leveling LCDL Delay VT Compensation
23714 */
23715#define DDRPHY_DX2GCR3_WLLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_WLLVT_SHIFT)) & DDRPHY_DX2GCR3_WLLVT_MASK)
23716#define DDRPHY_DX2GCR3_WDLVT_MASK (0x2000000U)
23717#define DDRPHY_DX2GCR3_WDLVT_SHIFT (25U)
23718/*! WDLVT - Write DQ LCDL Delay VT Compensation
23719 */
23720#define DDRPHY_DX2GCR3_WDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_WDLVT_SHIFT)) & DDRPHY_DX2GCR3_WDLVT_MASK)
23721#define DDRPHY_DX2GCR3_RDLVT_MASK (0x4000000U)
23722#define DDRPHY_DX2GCR3_RDLVT_SHIFT (26U)
23723/*! RDLVT - Read DQS LCDL Delay VT Compensation
23724 */
23725#define DDRPHY_DX2GCR3_RDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_RDLVT_SHIFT)) & DDRPHY_DX2GCR3_RDLVT_MASK)
23726#define DDRPHY_DX2GCR3_RGLVT_MASK (0x8000000U)
23727#define DDRPHY_DX2GCR3_RGLVT_SHIFT (27U)
23728/*! RGLVT - Read DQS Gating LCDL Delay VT Compensation
23729 */
23730#define DDRPHY_DX2GCR3_RGLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_RGLVT_SHIFT)) & DDRPHY_DX2GCR3_RGLVT_MASK)
23731#define DDRPHY_DX2GCR3_WDBVT_MASK (0x10000000U)
23732#define DDRPHY_DX2GCR3_WDBVT_SHIFT (28U)
23733/*! WDBVT - Write Data BDL VT Compensation
23734 */
23735#define DDRPHY_DX2GCR3_WDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_WDBVT_SHIFT)) & DDRPHY_DX2GCR3_WDBVT_MASK)
23736#define DDRPHY_DX2GCR3_RDBVT_MASK (0x20000000U)
23737#define DDRPHY_DX2GCR3_RDBVT_SHIFT (29U)
23738/*! RDBVT - Read Data BDL VT Compensation
23739 */
23740#define DDRPHY_DX2GCR3_RDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_RDBVT_SHIFT)) & DDRPHY_DX2GCR3_RDBVT_MASK)
23741#define DDRPHY_DX2GCR3_TEBVT_MASK (0x40000000U)
23742#define DDRPHY_DX2GCR3_TEBVT_SHIFT (30U)
23743/*! TEBVT - Termination Enable BDL VT Compensation
23744 */
23745#define DDRPHY_DX2GCR3_TEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_TEBVT_SHIFT)) & DDRPHY_DX2GCR3_TEBVT_MASK)
23746#define DDRPHY_DX2GCR3_OEBVT_MASK (0x80000000U)
23747#define DDRPHY_DX2GCR3_OEBVT_SHIFT (31U)
23748/*! OEBVT - Output Enable BDL VT Compensation
23749 */
23750#define DDRPHY_DX2GCR3_OEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR3_OEBVT_SHIFT)) & DDRPHY_DX2GCR3_OEBVT_MASK)
23751/*! @} */
23752
23753/*! @name DX2GCR4 - DATX8 n General Configuration Register 4 */
23754/*! @{ */
23755#define DDRPHY_DX2GCR4_DXREFIMON_MASK (0x3U)
23756#define DDRPHY_DX2GCR4_DXREFIMON_SHIFT (0U)
23757/*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane.
23758 */
23759#define DDRPHY_DX2GCR4_DXREFIMON(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX2GCR4_DXREFIMON_MASK)
23760#define DDRPHY_DX2GCR4_DXREFIEN_MASK (0x3CU)
23761#define DDRPHY_DX2GCR4_DXREFIEN_SHIFT (2U)
23762/*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
23763 */
23764#define DDRPHY_DX2GCR4_DXREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX2GCR4_DXREFIEN_MASK)
23765#define DDRPHY_DX2GCR4_RESERVED_7_6_MASK (0xC0U)
23766#define DDRPHY_DX2GCR4_RESERVED_7_6_SHIFT (6U)
23767/*! RESERVED_7_6 - Reserved. Returns zeros on reads.
23768 */
23769#define DDRPHY_DX2GCR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX2GCR4_RESERVED_7_6_MASK)
23770#define DDRPHY_DX2GCR4_DXREFSSEL_MASK (0x7F00U)
23771#define DDRPHY_DX2GCR4_DXREFSSEL_SHIFT (8U)
23772/*! DXREFSSEL - Byte Lane Single-End VREF Select
23773 */
23774#define DDRPHY_DX2GCR4_DXREFSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX2GCR4_DXREFSSEL_MASK)
23775#define DDRPHY_DX2GCR4_DXREFSSELRANGE_MASK (0x8000U)
23776#define DDRPHY_DX2GCR4_DXREFSSELRANGE_SHIFT (15U)
23777/*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select
23778 */
23779#define DDRPHY_DX2GCR4_DXREFSSELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX2GCR4_DXREFSSELRANGE_MASK)
23780#define DDRPHY_DX2GCR4_DXREFESEL_MASK (0x7F0000U)
23781#define DDRPHY_DX2GCR4_DXREFESEL_SHIFT (16U)
23782/*! DXREFESEL - Byte Lane External VREF Select
23783 */
23784#define DDRPHY_DX2GCR4_DXREFESEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX2GCR4_DXREFESEL_MASK)
23785#define DDRPHY_DX2GCR4_DXREFESELRANGE_MASK (0x800000U)
23786#define DDRPHY_DX2GCR4_DXREFESELRANGE_SHIFT (23U)
23787/*! DXREFESELRANGE - External VREF generator REFSEL range select
23788 */
23789#define DDRPHY_DX2GCR4_DXREFESELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX2GCR4_DXREFESELRANGE_MASK)
23790#define DDRPHY_DX2GCR4_RESERVED_24_MASK (0x1000000U)
23791#define DDRPHY_DX2GCR4_RESERVED_24_SHIFT (24U)
23792/*! RESERVED_24 - Reserved. Returns zeros on reads.
23793 */
23794#define DDRPHY_DX2GCR4_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX2GCR4_RESERVED_24_MASK)
23795#define DDRPHY_DX2GCR4_DXREFSEN_MASK (0x2000000U)
23796#define DDRPHY_DX2GCR4_DXREFSEN_SHIFT (25U)
23797/*! DXREFSEN - Byte Lane Single-End VREF Enable
23798 */
23799#define DDRPHY_DX2GCR4_DXREFSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX2GCR4_DXREFSEN_MASK)
23800#define DDRPHY_DX2GCR4_DXREFEEN_MASK (0xC000000U)
23801#define DDRPHY_DX2GCR4_DXREFEEN_SHIFT (26U)
23802/*! DXREFEEN - Byte Lane Internal VREF Enable
23803 */
23804#define DDRPHY_DX2GCR4_DXREFEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX2GCR4_DXREFEEN_MASK)
23805#define DDRPHY_DX2GCR4_DXREFPEN_MASK (0x10000000U)
23806#define DDRPHY_DX2GCR4_DXREFPEN_SHIFT (28U)
23807/*! DXREFPEN - Byte Lane VREF Pad Enable
23808 */
23809#define DDRPHY_DX2GCR4_DXREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX2GCR4_DXREFPEN_MASK)
23810#define DDRPHY_DX2GCR4_RESERVED_31_29_MASK (0xE0000000U)
23811#define DDRPHY_DX2GCR4_RESERVED_31_29_SHIFT (29U)
23812/*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs)
23813 */
23814#define DDRPHY_DX2GCR4_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX2GCR4_RESERVED_31_29_MASK)
23815/*! @} */
23816
23817/*! @name DX2GCR5 - DATX8 n General Configuration Register 5 */
23818/*! @{ */
23819#define DDRPHY_DX2GCR5_DXREFISELR0_MASK (0x7FU)
23820#define DDRPHY_DX2GCR5_DXREFISELR0_SHIFT (0U)
23821/*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0
23822 */
23823#define DDRPHY_DX2GCR5_DXREFISELR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX2GCR5_DXREFISELR0_MASK)
23824#define DDRPHY_DX2GCR5_RESERVED_7_MASK (0x80U)
23825#define DDRPHY_DX2GCR5_RESERVED_7_SHIFT (7U)
23826/*! RESERVED_7 - Reserved. Returns zeros on reads.
23827 */
23828#define DDRPHY_DX2GCR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX2GCR5_RESERVED_7_MASK)
23829#define DDRPHY_DX2GCR5_DXREFISELR1_MASK (0x7F00U)
23830#define DDRPHY_DX2GCR5_DXREFISELR1_SHIFT (8U)
23831/*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1
23832 */
23833#define DDRPHY_DX2GCR5_DXREFISELR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX2GCR5_DXREFISELR1_MASK)
23834#define DDRPHY_DX2GCR5_RESERVED_15_MASK (0x8000U)
23835#define DDRPHY_DX2GCR5_RESERVED_15_SHIFT (15U)
23836/*! RESERVED_15 - Reserved. Returns zeros on reads.
23837 */
23838#define DDRPHY_DX2GCR5_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX2GCR5_RESERVED_15_MASK)
23839#define DDRPHY_DX2GCR5_DXREFISELR2_MASK (0x7F0000U)
23840#define DDRPHY_DX2GCR5_DXREFISELR2_SHIFT (16U)
23841/*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2
23842 */
23843#define DDRPHY_DX2GCR5_DXREFISELR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX2GCR5_DXREFISELR2_MASK)
23844#define DDRPHY_DX2GCR5_RESERVED_23_MASK (0x800000U)
23845#define DDRPHY_DX2GCR5_RESERVED_23_SHIFT (23U)
23846/*! RESERVED_23 - Reserved. Returns zeros on reads.
23847 */
23848#define DDRPHY_DX2GCR5_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX2GCR5_RESERVED_23_MASK)
23849#define DDRPHY_DX2GCR5_DXREFISELR3_MASK (0x7F000000U)
23850#define DDRPHY_DX2GCR5_DXREFISELR3_SHIFT (24U)
23851/*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3
23852 */
23853#define DDRPHY_DX2GCR5_DXREFISELR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX2GCR5_DXREFISELR3_MASK)
23854#define DDRPHY_DX2GCR5_RESERVED_31_MASK (0x80000000U)
23855#define DDRPHY_DX2GCR5_RESERVED_31_SHIFT (31U)
23856/*! RESERVED_31 - Reserved. Returns zeros on reads.
23857 */
23858#define DDRPHY_DX2GCR5_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX2GCR5_RESERVED_31_MASK)
23859/*! @} */
23860
23861/*! @name DX2GCR6 - DATX8 n General Configuration Register 6 */
23862/*! @{ */
23863#define DDRPHY_DX2GCR6_DXDQVREFR0_MASK (0x3FU)
23864#define DDRPHY_DX2GCR6_DXDQVREFR0_SHIFT (0U)
23865/*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0
23866 */
23867#define DDRPHY_DX2GCR6_DXDQVREFR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX2GCR6_DXDQVREFR0_MASK)
23868#define DDRPHY_DX2GCR6_RESERVED_7_6_MASK (0xC0U)
23869#define DDRPHY_DX2GCR6_RESERVED_7_6_SHIFT (6U)
23870/*! RESERVED_7_6 - Reserved. Returns zeros on reads.
23871 */
23872#define DDRPHY_DX2GCR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX2GCR6_RESERVED_7_6_MASK)
23873#define DDRPHY_DX2GCR6_DXDQVREFR1_MASK (0x3F00U)
23874#define DDRPHY_DX2GCR6_DXDQVREFR1_SHIFT (8U)
23875/*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1
23876 */
23877#define DDRPHY_DX2GCR6_DXDQVREFR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX2GCR6_DXDQVREFR1_MASK)
23878#define DDRPHY_DX2GCR6_RESERVED_15_14_MASK (0xC000U)
23879#define DDRPHY_DX2GCR6_RESERVED_15_14_SHIFT (14U)
23880/*! RESERVED_15_14 - Reserved. Returns zeros on reads.
23881 */
23882#define DDRPHY_DX2GCR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX2GCR6_RESERVED_15_14_MASK)
23883#define DDRPHY_DX2GCR6_DXDQVREFR2_MASK (0x3F0000U)
23884#define DDRPHY_DX2GCR6_DXDQVREFR2_SHIFT (16U)
23885/*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2
23886 */
23887#define DDRPHY_DX2GCR6_DXDQVREFR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX2GCR6_DXDQVREFR2_MASK)
23888#define DDRPHY_DX2GCR6_RESERVED_23_22_MASK (0xC00000U)
23889#define DDRPHY_DX2GCR6_RESERVED_23_22_SHIFT (22U)
23890/*! RESERVED_23_22 - Reserved. Returns zeros on reads.
23891 */
23892#define DDRPHY_DX2GCR6_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX2GCR6_RESERVED_23_22_MASK)
23893#define DDRPHY_DX2GCR6_DXDQVREFR3_MASK (0x3F000000U)
23894#define DDRPHY_DX2GCR6_DXDQVREFR3_SHIFT (24U)
23895/*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3
23896 */
23897#define DDRPHY_DX2GCR6_DXDQVREFR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX2GCR6_DXDQVREFR3_MASK)
23898#define DDRPHY_DX2GCR6_RESERVED_31_30_MASK (0xC0000000U)
23899#define DDRPHY_DX2GCR6_RESERVED_31_30_SHIFT (30U)
23900/*! RESERVED_31_30 - Reserved. Returns zeros on reads.
23901 */
23902#define DDRPHY_DX2GCR6_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX2GCR6_RESERVED_31_30_MASK)
23903/*! @} */
23904
23905/*! @name DX2GCR7 - DATX8 n General Configuration Register 7 */
23906/*! @{ */
23907#define DDRPHY_DX2GCR7_DCALSVAL_MASK (0x1FFU)
23908#define DDRPHY_DX2GCR7_DCALSVAL_SHIFT (0U)
23909/*! DCALSVAL - DDL Calibration Starting Value
23910 */
23911#define DDRPHY_DX2GCR7_DCALSVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX2GCR7_DCALSVAL_MASK)
23912#define DDRPHY_DX2GCR7_DCALTYPE_MASK (0x200U)
23913#define DDRPHY_DX2GCR7_DCALTYPE_SHIFT (9U)
23914/*! DCALTYPE - DDL Calibration Type
23915 */
23916#define DDRPHY_DX2GCR7_DCALTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX2GCR7_DCALTYPE_MASK)
23917#define DDRPHY_DX2GCR7_RESERVED_17_10_MASK (0x3FC00U)
23918#define DDRPHY_DX2GCR7_RESERVED_17_10_SHIFT (10U)
23919/*! RESERVED_17_10 - Reserved. Caution, do not write to this register field.
23920 */
23921#define DDRPHY_DX2GCR7_RESERVED_17_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX2GCR7_RESERVED_17_10_MASK)
23922#define DDRPHY_DX2GCR7_RESERVED_18_MASK (0x40000U)
23923#define DDRPHY_DX2GCR7_RESERVED_18_SHIFT (18U)
23924/*! RESERVED_18 - Reserved. Caution, do not write to this register field.
23925 */
23926#define DDRPHY_DX2GCR7_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX2GCR7_RESERVED_18_MASK)
23927#define DDRPHY_DX2GCR7_RESERVED_31_19_MASK (0xFFF80000U)
23928#define DDRPHY_DX2GCR7_RESERVED_31_19_SHIFT (19U)
23929/*! RESERVED_31_19 - Reserved. Caution, do not write to this register field.
23930 */
23931#define DDRPHY_DX2GCR7_RESERVED_31_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX2GCR7_RESERVED_31_19_MASK)
23932/*! @} */
23933
23934/*! @name DX2GCR8 - DATX8 n General Configuration Register 8 */
23935/*! @{ */
23936#define DDRPHY_DX2GCR8_RESERVED_5_0_MASK (0x3FU)
23937#define DDRPHY_DX2GCR8_RESERVED_5_0_SHIFT (0U)
23938/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
23939 */
23940#define DDRPHY_DX2GCR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_5_0_MASK)
23941#define DDRPHY_DX2GCR8_RESERVED_7_6_MASK (0xC0U)
23942#define DDRPHY_DX2GCR8_RESERVED_7_6_SHIFT (6U)
23943/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
23944 */
23945#define DDRPHY_DX2GCR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_7_6_MASK)
23946#define DDRPHY_DX2GCR8_RESERVED_13_8_MASK (0x3F00U)
23947#define DDRPHY_DX2GCR8_RESERVED_13_8_SHIFT (8U)
23948/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
23949 */
23950#define DDRPHY_DX2GCR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_13_8_MASK)
23951#define DDRPHY_DX2GCR8_RESERVED_15_14_MASK (0xC000U)
23952#define DDRPHY_DX2GCR8_RESERVED_15_14_SHIFT (14U)
23953/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
23954 */
23955#define DDRPHY_DX2GCR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_15_14_MASK)
23956#define DDRPHY_DX2GCR8_RESERVED_21_16_MASK (0x3F0000U)
23957#define DDRPHY_DX2GCR8_RESERVED_21_16_SHIFT (16U)
23958/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
23959 */
23960#define DDRPHY_DX2GCR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_21_16_MASK)
23961#define DDRPHY_DX2GCR8_RESERVED_23_22_MASK (0xC00000U)
23962#define DDRPHY_DX2GCR8_RESERVED_23_22_SHIFT (22U)
23963/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
23964 */
23965#define DDRPHY_DX2GCR8_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_23_22_MASK)
23966#define DDRPHY_DX2GCR8_RESERVED_29_24_MASK (0x3F000000U)
23967#define DDRPHY_DX2GCR8_RESERVED_29_24_SHIFT (24U)
23968/*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
23969 */
23970#define DDRPHY_DX2GCR8_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_29_24_MASK)
23971#define DDRPHY_DX2GCR8_RESERVED_31_30_MASK (0xC0000000U)
23972#define DDRPHY_DX2GCR8_RESERVED_31_30_SHIFT (30U)
23973/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
23974 */
23975#define DDRPHY_DX2GCR8_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX2GCR8_RESERVED_31_30_MASK)
23976/*! @} */
23977
23978/*! @name DX2GCR9 - DATX8 n General Configuration Register 9 */
23979/*! @{ */
23980#define DDRPHY_DX2GCR9_RESERVED_5_0_MASK (0x3FU)
23981#define DDRPHY_DX2GCR9_RESERVED_5_0_SHIFT (0U)
23982/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
23983 */
23984#define DDRPHY_DX2GCR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_5_0_MASK)
23985#define DDRPHY_DX2GCR9_RESERVED_7_6_MASK (0xC0U)
23986#define DDRPHY_DX2GCR9_RESERVED_7_6_SHIFT (6U)
23987/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
23988 */
23989#define DDRPHY_DX2GCR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_7_6_MASK)
23990#define DDRPHY_DX2GCR9_RESERVED_13_8_MASK (0x3F00U)
23991#define DDRPHY_DX2GCR9_RESERVED_13_8_SHIFT (8U)
23992/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
23993 */
23994#define DDRPHY_DX2GCR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_13_8_MASK)
23995#define DDRPHY_DX2GCR9_RESERVED_15_14_MASK (0xC000U)
23996#define DDRPHY_DX2GCR9_RESERVED_15_14_SHIFT (14U)
23997/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
23998 */
23999#define DDRPHY_DX2GCR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_15_14_MASK)
24000#define DDRPHY_DX2GCR9_RESERVED_21_16_MASK (0x3F0000U)
24001#define DDRPHY_DX2GCR9_RESERVED_21_16_SHIFT (16U)
24002/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
24003 */
24004#define DDRPHY_DX2GCR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_21_16_MASK)
24005#define DDRPHY_DX2GCR9_RESERVED_23_22_MASK (0xC00000U)
24006#define DDRPHY_DX2GCR9_RESERVED_23_22_SHIFT (22U)
24007/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
24008 */
24009#define DDRPHY_DX2GCR9_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_23_22_MASK)
24010#define DDRPHY_DX2GCR9_RESERVED_29_24_MASK (0x3F000000U)
24011#define DDRPHY_DX2GCR9_RESERVED_29_24_SHIFT (24U)
24012/*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
24013 */
24014#define DDRPHY_DX2GCR9_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_29_24_MASK)
24015#define DDRPHY_DX2GCR9_RESERVED_31_30_MASK (0xC0000000U)
24016#define DDRPHY_DX2GCR9_RESERVED_31_30_SHIFT (30U)
24017/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
24018 */
24019#define DDRPHY_DX2GCR9_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX2GCR9_RESERVED_31_30_MASK)
24020/*! @} */
24021
24022/*! @name DX2DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */
24023/*! @{ */
24024#define DDRPHY_DX2DQMAP0_DQ0MAP_MASK (0xFU)
24025#define DDRPHY_DX2DQMAP0_DQ0MAP_SHIFT (0U)
24026/*! DQ0MAP - DQ bit 0 DATX8 slice mapping index
24027 */
24028#define DDRPHY_DX2DQMAP0_DQ0MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX2DQMAP0_DQ0MAP_MASK)
24029#define DDRPHY_DX2DQMAP0_DQ1MAP_MASK (0xF0U)
24030#define DDRPHY_DX2DQMAP0_DQ1MAP_SHIFT (4U)
24031/*! DQ1MAP - DQ bit 1 DATX8 slice mapping index
24032 */
24033#define DDRPHY_DX2DQMAP0_DQ1MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX2DQMAP0_DQ1MAP_MASK)
24034#define DDRPHY_DX2DQMAP0_DQ2MAP_MASK (0xF00U)
24035#define DDRPHY_DX2DQMAP0_DQ2MAP_SHIFT (8U)
24036/*! DQ2MAP - DQ bit 2 DATX8 slice mapping index
24037 */
24038#define DDRPHY_DX2DQMAP0_DQ2MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX2DQMAP0_DQ2MAP_MASK)
24039#define DDRPHY_DX2DQMAP0_DQ3MAP_MASK (0xF000U)
24040#define DDRPHY_DX2DQMAP0_DQ3MAP_SHIFT (12U)
24041/*! DQ3MAP - DQ bit 3 DATX8 slice mapping index
24042 */
24043#define DDRPHY_DX2DQMAP0_DQ3MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX2DQMAP0_DQ3MAP_MASK)
24044#define DDRPHY_DX2DQMAP0_DQ4MAP_MASK (0xF0000U)
24045#define DDRPHY_DX2DQMAP0_DQ4MAP_SHIFT (16U)
24046/*! DQ4MAP - DQ bit 4 DATX8 slice mapping index
24047 */
24048#define DDRPHY_DX2DQMAP0_DQ4MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX2DQMAP0_DQ4MAP_MASK)
24049#define DDRPHY_DX2DQMAP0_RESERVED_30_20_MASK (0x7FF00000U)
24050#define DDRPHY_DX2DQMAP0_RESERVED_30_20_SHIFT (20U)
24051/*! RESERVED_30_20 - Reserved. Return zeroes on reads.
24052 */
24053#define DDRPHY_DX2DQMAP0_RESERVED_30_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX2DQMAP0_RESERVED_30_20_MASK)
24054#define DDRPHY_DX2DQMAP0_MAPOK_MASK (0x80000000U)
24055#define DDRPHY_DX2DQMAP0_MAPOK_SHIFT (31U)
24056/*! MAPOK - Checksum bit
24057 */
24058#define DDRPHY_DX2DQMAP0_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX2DQMAP0_MAPOK_MASK)
24059/*! @} */
24060
24061/*! @name DX2DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */
24062/*! @{ */
24063#define DDRPHY_DX2DQMAP1_DQ5MAP_MASK (0xFU)
24064#define DDRPHY_DX2DQMAP1_DQ5MAP_SHIFT (0U)
24065/*! DQ5MAP - DQ bit 5 DATX8 slice mapping index
24066 */
24067#define DDRPHY_DX2DQMAP1_DQ5MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX2DQMAP1_DQ5MAP_MASK)
24068#define DDRPHY_DX2DQMAP1_DQ6MAP_MASK (0xF0U)
24069#define DDRPHY_DX2DQMAP1_DQ6MAP_SHIFT (4U)
24070/*! DQ6MAP - DQ bit 6 DATX8 slice mapping index
24071 */
24072#define DDRPHY_DX2DQMAP1_DQ6MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX2DQMAP1_DQ6MAP_MASK)
24073#define DDRPHY_DX2DQMAP1_DQ7MAP_MASK (0xF00U)
24074#define DDRPHY_DX2DQMAP1_DQ7MAP_SHIFT (8U)
24075/*! DQ7MAP - DQ bit 7 DATX8 slice mapping index
24076 */
24077#define DDRPHY_DX2DQMAP1_DQ7MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX2DQMAP1_DQ7MAP_MASK)
24078#define DDRPHY_DX2DQMAP1_DMMAP_MASK (0xF000U)
24079#define DDRPHY_DX2DQMAP1_DMMAP_SHIFT (12U)
24080/*! DMMAP - DM bit DATX8 slice mapping index
24081 */
24082#define DDRPHY_DX2DQMAP1_DMMAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX2DQMAP1_DMMAP_MASK)
24083#define DDRPHY_DX2DQMAP1_RESERVED_30_16_MASK (0x7FFF0000U)
24084#define DDRPHY_DX2DQMAP1_RESERVED_30_16_SHIFT (16U)
24085/*! RESERVED_30_16 - Reserved. Return zeroes on reads.
24086 */
24087#define DDRPHY_DX2DQMAP1_RESERVED_30_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX2DQMAP1_RESERVED_30_16_MASK)
24088#define DDRPHY_DX2DQMAP1_MAPOK_MASK (0x80000000U)
24089#define DDRPHY_DX2DQMAP1_MAPOK_SHIFT (31U)
24090/*! MAPOK - Checksum bit
24091 */
24092#define DDRPHY_DX2DQMAP1_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX2DQMAP1_MAPOK_MASK)
24093/*! @} */
24094
24095/*! @name DX2BDLR0 - DATX8 n Bit Delay Line Register 0 */
24096/*! @{ */
24097#define DDRPHY_DX2BDLR0_DQ0WBD_MASK (0x3FU)
24098#define DDRPHY_DX2BDLR0_DQ0WBD_SHIFT (0U)
24099/*! DQ0WBD - DQ0 Write Bit Delay
24100 */
24101#define DDRPHY_DX2BDLR0_DQ0WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX2BDLR0_DQ0WBD_MASK)
24102#define DDRPHY_DX2BDLR0_RESERVED_7_6_MASK (0xC0U)
24103#define DDRPHY_DX2BDLR0_RESERVED_7_6_SHIFT (6U)
24104/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
24105 */
24106#define DDRPHY_DX2BDLR0_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR0_RESERVED_7_6_MASK)
24107#define DDRPHY_DX2BDLR0_DQ1WBD_MASK (0x3F00U)
24108#define DDRPHY_DX2BDLR0_DQ1WBD_SHIFT (8U)
24109/*! DQ1WBD - DQ1 Write Bit Delay
24110 */
24111#define DDRPHY_DX2BDLR0_DQ1WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX2BDLR0_DQ1WBD_MASK)
24112#define DDRPHY_DX2BDLR0_RESERVED_15_14_MASK (0xC000U)
24113#define DDRPHY_DX2BDLR0_RESERVED_15_14_SHIFT (14U)
24114/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
24115 */
24116#define DDRPHY_DX2BDLR0_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR0_RESERVED_15_14_MASK)
24117#define DDRPHY_DX2BDLR0_DQ2WBD_MASK (0x3F0000U)
24118#define DDRPHY_DX2BDLR0_DQ2WBD_SHIFT (16U)
24119/*! DQ2WBD - DQ2 Write Bit Delay
24120 */
24121#define DDRPHY_DX2BDLR0_DQ2WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX2BDLR0_DQ2WBD_MASK)
24122#define DDRPHY_DX2BDLR0_RESERVED_23_22_MASK (0xC00000U)
24123#define DDRPHY_DX2BDLR0_RESERVED_23_22_SHIFT (22U)
24124/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
24125 */
24126#define DDRPHY_DX2BDLR0_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX2BDLR0_RESERVED_23_22_MASK)
24127#define DDRPHY_DX2BDLR0_DQ3WBD_MASK (0x3F000000U)
24128#define DDRPHY_DX2BDLR0_DQ3WBD_SHIFT (24U)
24129/*! DQ3WBD - DQ3 Write Bit Delay
24130 */
24131#define DDRPHY_DX2BDLR0_DQ3WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX2BDLR0_DQ3WBD_MASK)
24132#define DDRPHY_DX2BDLR0_RESERVED_31_30_MASK (0xC0000000U)
24133#define DDRPHY_DX2BDLR0_RESERVED_31_30_SHIFT (30U)
24134/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
24135 */
24136#define DDRPHY_DX2BDLR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX2BDLR0_RESERVED_31_30_MASK)
24137/*! @} */
24138
24139/*! @name DX2BDLR1 - DATX8 n Bit Delay Line Register 1 */
24140/*! @{ */
24141#define DDRPHY_DX2BDLR1_DQ4WBD_MASK (0x3FU)
24142#define DDRPHY_DX2BDLR1_DQ4WBD_SHIFT (0U)
24143/*! DQ4WBD - DQ4 Write Bit Delay
24144 */
24145#define DDRPHY_DX2BDLR1_DQ4WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX2BDLR1_DQ4WBD_MASK)
24146#define DDRPHY_DX2BDLR1_RESERVED_7_6_MASK (0xC0U)
24147#define DDRPHY_DX2BDLR1_RESERVED_7_6_SHIFT (6U)
24148/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
24149 */
24150#define DDRPHY_DX2BDLR1_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR1_RESERVED_7_6_MASK)
24151#define DDRPHY_DX2BDLR1_DQ5WBD_MASK (0x3F00U)
24152#define DDRPHY_DX2BDLR1_DQ5WBD_SHIFT (8U)
24153/*! DQ5WBD - DQ5 Write Bit Delay
24154 */
24155#define DDRPHY_DX2BDLR1_DQ5WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX2BDLR1_DQ5WBD_MASK)
24156#define DDRPHY_DX2BDLR1_RESERVED_15_14_MASK (0xC000U)
24157#define DDRPHY_DX2BDLR1_RESERVED_15_14_SHIFT (14U)
24158/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
24159 */
24160#define DDRPHY_DX2BDLR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR1_RESERVED_15_14_MASK)
24161#define DDRPHY_DX2BDLR1_DQ6WBD_MASK (0x3F0000U)
24162#define DDRPHY_DX2BDLR1_DQ6WBD_SHIFT (16U)
24163/*! DQ6WBD - DQ6 Write Bit Delay
24164 */
24165#define DDRPHY_DX2BDLR1_DQ6WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX2BDLR1_DQ6WBD_MASK)
24166#define DDRPHY_DX2BDLR1_RESERVED_23_22_MASK (0xC00000U)
24167#define DDRPHY_DX2BDLR1_RESERVED_23_22_SHIFT (22U)
24168/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
24169 */
24170#define DDRPHY_DX2BDLR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX2BDLR1_RESERVED_23_22_MASK)
24171#define DDRPHY_DX2BDLR1_DQ7WBD_MASK (0x3F000000U)
24172#define DDRPHY_DX2BDLR1_DQ7WBD_SHIFT (24U)
24173/*! DQ7WBD - DQ7 Write Bit Delay
24174 */
24175#define DDRPHY_DX2BDLR1_DQ7WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX2BDLR1_DQ7WBD_MASK)
24176#define DDRPHY_DX2BDLR1_RESERVED_31_30_MASK (0xC0000000U)
24177#define DDRPHY_DX2BDLR1_RESERVED_31_30_SHIFT (30U)
24178/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
24179 */
24180#define DDRPHY_DX2BDLR1_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX2BDLR1_RESERVED_31_30_MASK)
24181/*! @} */
24182
24183/*! @name DX2BDLR2 - DATX8 n Bit Delay Line Register 2 */
24184/*! @{ */
24185#define DDRPHY_DX2BDLR2_DMWBD_MASK (0x3FU)
24186#define DDRPHY_DX2BDLR2_DMWBD_SHIFT (0U)
24187/*! DMWBD - DM Write Bit Delay
24188 */
24189#define DDRPHY_DX2BDLR2_DMWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_DMWBD_SHIFT)) & DDRPHY_DX2BDLR2_DMWBD_MASK)
24190#define DDRPHY_DX2BDLR2_RESERVED_7_6_MASK (0xC0U)
24191#define DDRPHY_DX2BDLR2_RESERVED_7_6_SHIFT (6U)
24192/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
24193 */
24194#define DDRPHY_DX2BDLR2_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR2_RESERVED_7_6_MASK)
24195#define DDRPHY_DX2BDLR2_DSWBD_MASK (0x3F00U)
24196#define DDRPHY_DX2BDLR2_DSWBD_SHIFT (8U)
24197/*! DSWBD - DQS Write Bit Delay
24198 */
24199#define DDRPHY_DX2BDLR2_DSWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_DSWBD_SHIFT)) & DDRPHY_DX2BDLR2_DSWBD_MASK)
24200#define DDRPHY_DX2BDLR2_RESERVED_15_14_MASK (0xC000U)
24201#define DDRPHY_DX2BDLR2_RESERVED_15_14_SHIFT (14U)
24202/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
24203 */
24204#define DDRPHY_DX2BDLR2_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR2_RESERVED_15_14_MASK)
24205#define DDRPHY_DX2BDLR2_DSOEBD_MASK (0x3F0000U)
24206#define DDRPHY_DX2BDLR2_DSOEBD_SHIFT (16U)
24207/*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay
24208 */
24209#define DDRPHY_DX2BDLR2_DSOEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX2BDLR2_DSOEBD_MASK)
24210#define DDRPHY_DX2BDLR2_RESERVED_23_22_MASK (0xC00000U)
24211#define DDRPHY_DX2BDLR2_RESERVED_23_22_SHIFT (22U)
24212/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
24213 */
24214#define DDRPHY_DX2BDLR2_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX2BDLR2_RESERVED_23_22_MASK)
24215#define DDRPHY_DX2BDLR2_DSNWBD_MASK (0x3F000000U)
24216#define DDRPHY_DX2BDLR2_DSNWBD_SHIFT (24U)
24217/*! DSNWBD - DQSN Write Bit Delay
24218 */
24219#define DDRPHY_DX2BDLR2_DSNWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX2BDLR2_DSNWBD_MASK)
24220#define DDRPHY_DX2BDLR2_RESERVED_31_30_MASK (0xC0000000U)
24221#define DDRPHY_DX2BDLR2_RESERVED_31_30_SHIFT (30U)
24222/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
24223 */
24224#define DDRPHY_DX2BDLR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX2BDLR2_RESERVED_31_30_MASK)
24225/*! @} */
24226
24227/*! @name DX2BDLR3 - DATX8 n Bit Delay Line Register 3 */
24228/*! @{ */
24229#define DDRPHY_DX2BDLR3_DQ0RBD_MASK (0x3FU)
24230#define DDRPHY_DX2BDLR3_DQ0RBD_SHIFT (0U)
24231/*! DQ0RBD - DQ0 Read Bit Delay
24232 */
24233#define DDRPHY_DX2BDLR3_DQ0RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX2BDLR3_DQ0RBD_MASK)
24234#define DDRPHY_DX2BDLR3_RESERVED_7_6_MASK (0xC0U)
24235#define DDRPHY_DX2BDLR3_RESERVED_7_6_SHIFT (6U)
24236/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
24237 */
24238#define DDRPHY_DX2BDLR3_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR3_RESERVED_7_6_MASK)
24239#define DDRPHY_DX2BDLR3_DQ1RBD_MASK (0x3F00U)
24240#define DDRPHY_DX2BDLR3_DQ1RBD_SHIFT (8U)
24241/*! DQ1RBD - DQ1 Read Bit Delay
24242 */
24243#define DDRPHY_DX2BDLR3_DQ1RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX2BDLR3_DQ1RBD_MASK)
24244#define DDRPHY_DX2BDLR3_RESERVED_15_14_MASK (0xC000U)
24245#define DDRPHY_DX2BDLR3_RESERVED_15_14_SHIFT (14U)
24246/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
24247 */
24248#define DDRPHY_DX2BDLR3_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR3_RESERVED_15_14_MASK)
24249#define DDRPHY_DX2BDLR3_DQ2RBD_MASK (0x3F0000U)
24250#define DDRPHY_DX2BDLR3_DQ2RBD_SHIFT (16U)
24251/*! DQ2RBD - DQ2 Read Bit Delay
24252 */
24253#define DDRPHY_DX2BDLR3_DQ2RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX2BDLR3_DQ2RBD_MASK)
24254#define DDRPHY_DX2BDLR3_RESERVED_23_22_MASK (0xC00000U)
24255#define DDRPHY_DX2BDLR3_RESERVED_23_22_SHIFT (22U)
24256/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
24257 */
24258#define DDRPHY_DX2BDLR3_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX2BDLR3_RESERVED_23_22_MASK)
24259#define DDRPHY_DX2BDLR3_DQ3RBD_MASK (0x3F000000U)
24260#define DDRPHY_DX2BDLR3_DQ3RBD_SHIFT (24U)
24261/*! DQ3RBD - DQ3 Read Bit Delay
24262 */
24263#define DDRPHY_DX2BDLR3_DQ3RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX2BDLR3_DQ3RBD_MASK)
24264#define DDRPHY_DX2BDLR3_RESERVED_31_30_MASK (0xC0000000U)
24265#define DDRPHY_DX2BDLR3_RESERVED_31_30_SHIFT (30U)
24266/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
24267 */
24268#define DDRPHY_DX2BDLR3_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX2BDLR3_RESERVED_31_30_MASK)
24269/*! @} */
24270
24271/*! @name DX2BDLR4 - DATX8 n Bit Delay Line Register 4 */
24272/*! @{ */
24273#define DDRPHY_DX2BDLR4_DQ4RBD_MASK (0x3FU)
24274#define DDRPHY_DX2BDLR4_DQ4RBD_SHIFT (0U)
24275/*! DQ4RBD - DQ4 Read Bit Delay
24276 */
24277#define DDRPHY_DX2BDLR4_DQ4RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX2BDLR4_DQ4RBD_MASK)
24278#define DDRPHY_DX2BDLR4_RESERVED_7_6_MASK (0xC0U)
24279#define DDRPHY_DX2BDLR4_RESERVED_7_6_SHIFT (6U)
24280/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
24281 */
24282#define DDRPHY_DX2BDLR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR4_RESERVED_7_6_MASK)
24283#define DDRPHY_DX2BDLR4_DQ5RBD_MASK (0x3F00U)
24284#define DDRPHY_DX2BDLR4_DQ5RBD_SHIFT (8U)
24285/*! DQ5RBD - DQ5 Read Bit Delay
24286 */
24287#define DDRPHY_DX2BDLR4_DQ5RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX2BDLR4_DQ5RBD_MASK)
24288#define DDRPHY_DX2BDLR4_RESERVED_15_14_MASK (0xC000U)
24289#define DDRPHY_DX2BDLR4_RESERVED_15_14_SHIFT (14U)
24290/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
24291 */
24292#define DDRPHY_DX2BDLR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR4_RESERVED_15_14_MASK)
24293#define DDRPHY_DX2BDLR4_DQ6RBD_MASK (0x3F0000U)
24294#define DDRPHY_DX2BDLR4_DQ6RBD_SHIFT (16U)
24295/*! DQ6RBD - DQ6 Read Bit Delay
24296 */
24297#define DDRPHY_DX2BDLR4_DQ6RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX2BDLR4_DQ6RBD_MASK)
24298#define DDRPHY_DX2BDLR4_RESERVED_23_22_MASK (0xC00000U)
24299#define DDRPHY_DX2BDLR4_RESERVED_23_22_SHIFT (22U)
24300/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
24301 */
24302#define DDRPHY_DX2BDLR4_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX2BDLR4_RESERVED_23_22_MASK)
24303#define DDRPHY_DX2BDLR4_DQ7RBD_MASK (0x3F000000U)
24304#define DDRPHY_DX2BDLR4_DQ7RBD_SHIFT (24U)
24305/*! DQ7RBD - DQ7 Read Bit Delay
24306 */
24307#define DDRPHY_DX2BDLR4_DQ7RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX2BDLR4_DQ7RBD_MASK)
24308#define DDRPHY_DX2BDLR4_RESERVED_31_30_MASK (0xC0000000U)
24309#define DDRPHY_DX2BDLR4_RESERVED_31_30_SHIFT (30U)
24310/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
24311 */
24312#define DDRPHY_DX2BDLR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX2BDLR4_RESERVED_31_30_MASK)
24313/*! @} */
24314
24315/*! @name DX2BDLR5 - DATX8 n Bit Delay Line Register 5 */
24316/*! @{ */
24317#define DDRPHY_DX2BDLR5_DMRBD_MASK (0x3FU)
24318#define DDRPHY_DX2BDLR5_DMRBD_SHIFT (0U)
24319/*! DMRBD - DM Read Bit Delay
24320 */
24321#define DDRPHY_DX2BDLR5_DMRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR5_DMRBD_SHIFT)) & DDRPHY_DX2BDLR5_DMRBD_MASK)
24322#define DDRPHY_DX2BDLR5_RESERVED_31_6_MASK (0xFFFFFFC0U)
24323#define DDRPHY_DX2BDLR5_RESERVED_31_6_SHIFT (6U)
24324/*! RESERVED_31_6 - Reserved. Return zeroes on reads.
24325 */
24326#define DDRPHY_DX2BDLR5_RESERVED_31_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX2BDLR5_RESERVED_31_6_MASK)
24327/*! @} */
24328
24329/*! @name DX2BDLR6 - DATX8 n Bit Delay Line Register 6 */
24330/*! @{ */
24331#define DDRPHY_DX2BDLR6_RESERVED_7_0_MASK (0xFFU)
24332#define DDRPHY_DX2BDLR6_RESERVED_7_0_SHIFT (0U)
24333/*! RESERVED_7_0 - Reserved. Return zeroes on reads.
24334 */
24335#define DDRPHY_DX2BDLR6_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX2BDLR6_RESERVED_7_0_MASK)
24336#define DDRPHY_DX2BDLR6_PDRBD_MASK (0x3F00U)
24337#define DDRPHY_DX2BDLR6_PDRBD_SHIFT (8U)
24338/*! PDRBD - Power down receiver Bit Delay
24339 */
24340#define DDRPHY_DX2BDLR6_PDRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR6_PDRBD_SHIFT)) & DDRPHY_DX2BDLR6_PDRBD_MASK)
24341#define DDRPHY_DX2BDLR6_RESERVED_15_14_MASK (0xC000U)
24342#define DDRPHY_DX2BDLR6_RESERVED_15_14_SHIFT (14U)
24343/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
24344 */
24345#define DDRPHY_DX2BDLR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR6_RESERVED_15_14_MASK)
24346#define DDRPHY_DX2BDLR6_TERBD_MASK (0x3F0000U)
24347#define DDRPHY_DX2BDLR6_TERBD_SHIFT (16U)
24348/*! TERBD - Termination Enable Bit Delay
24349 */
24350#define DDRPHY_DX2BDLR6_TERBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR6_TERBD_SHIFT)) & DDRPHY_DX2BDLR6_TERBD_MASK)
24351#define DDRPHY_DX2BDLR6_RESERVED_31_22_MASK (0xFFC00000U)
24352#define DDRPHY_DX2BDLR6_RESERVED_31_22_SHIFT (22U)
24353/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
24354 */
24355#define DDRPHY_DX2BDLR6_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX2BDLR6_RESERVED_31_22_MASK)
24356/*! @} */
24357
24358/*! @name DX2BDLR7 - DATX8 n Bit Delay Line Register 7 */
24359/*! @{ */
24360#define DDRPHY_DX2BDLR7_RESERVED_5_0_MASK (0x3FU)
24361#define DDRPHY_DX2BDLR7_RESERVED_5_0_SHIFT (0U)
24362/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
24363 */
24364#define DDRPHY_DX2BDLR7_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX2BDLR7_RESERVED_5_0_MASK)
24365#define DDRPHY_DX2BDLR7_RESERVED_7_6_MASK (0xC0U)
24366#define DDRPHY_DX2BDLR7_RESERVED_7_6_SHIFT (6U)
24367/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
24368 */
24369#define DDRPHY_DX2BDLR7_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR7_RESERVED_7_6_MASK)
24370#define DDRPHY_DX2BDLR7_RESERVED_13_8_MASK (0x3F00U)
24371#define DDRPHY_DX2BDLR7_RESERVED_13_8_SHIFT (8U)
24372/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
24373 */
24374#define DDRPHY_DX2BDLR7_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX2BDLR7_RESERVED_13_8_MASK)
24375#define DDRPHY_DX2BDLR7_RESERVED_15_14_MASK (0xC000U)
24376#define DDRPHY_DX2BDLR7_RESERVED_15_14_SHIFT (14U)
24377/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
24378 */
24379#define DDRPHY_DX2BDLR7_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR7_RESERVED_15_14_MASK)
24380#define DDRPHY_DX2BDLR7_RESERVED_21_16_MASK (0x3F0000U)
24381#define DDRPHY_DX2BDLR7_RESERVED_21_16_SHIFT (16U)
24382/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
24383 */
24384#define DDRPHY_DX2BDLR7_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX2BDLR7_RESERVED_21_16_MASK)
24385#define DDRPHY_DX2BDLR7_RESERVED_31_22_MASK (0xFFC00000U)
24386#define DDRPHY_DX2BDLR7_RESERVED_31_22_SHIFT (22U)
24387/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
24388 */
24389#define DDRPHY_DX2BDLR7_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX2BDLR7_RESERVED_31_22_MASK)
24390/*! @} */
24391
24392/*! @name DX2BDLR8 - DATX8 n Bit Delay Line Register 8 */
24393/*! @{ */
24394#define DDRPHY_DX2BDLR8_RESERVED_5_0_MASK (0x3FU)
24395#define DDRPHY_DX2BDLR8_RESERVED_5_0_SHIFT (0U)
24396/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
24397 */
24398#define DDRPHY_DX2BDLR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX2BDLR8_RESERVED_5_0_MASK)
24399#define DDRPHY_DX2BDLR8_RESERVED_7_6_MASK (0xC0U)
24400#define DDRPHY_DX2BDLR8_RESERVED_7_6_SHIFT (6U)
24401/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
24402 */
24403#define DDRPHY_DX2BDLR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR8_RESERVED_7_6_MASK)
24404#define DDRPHY_DX2BDLR8_RESERVED_13_8_MASK (0x3F00U)
24405#define DDRPHY_DX2BDLR8_RESERVED_13_8_SHIFT (8U)
24406/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
24407 */
24408#define DDRPHY_DX2BDLR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX2BDLR8_RESERVED_13_8_MASK)
24409#define DDRPHY_DX2BDLR8_RESERVED_15_14_MASK (0xC000U)
24410#define DDRPHY_DX2BDLR8_RESERVED_15_14_SHIFT (14U)
24411/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
24412 */
24413#define DDRPHY_DX2BDLR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR8_RESERVED_15_14_MASK)
24414#define DDRPHY_DX2BDLR8_RESERVED_21_16_MASK (0x3F0000U)
24415#define DDRPHY_DX2BDLR8_RESERVED_21_16_SHIFT (16U)
24416/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
24417 */
24418#define DDRPHY_DX2BDLR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX2BDLR8_RESERVED_21_16_MASK)
24419#define DDRPHY_DX2BDLR8_RESERVED_31_22_MASK (0xFFC00000U)
24420#define DDRPHY_DX2BDLR8_RESERVED_31_22_SHIFT (22U)
24421/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
24422 */
24423#define DDRPHY_DX2BDLR8_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX2BDLR8_RESERVED_31_22_MASK)
24424/*! @} */
24425
24426/*! @name DX2BDLR9 - DATX8 n Bit Delay Line Register 9 */
24427/*! @{ */
24428#define DDRPHY_DX2BDLR9_RESERVED_5_0_MASK (0x3FU)
24429#define DDRPHY_DX2BDLR9_RESERVED_5_0_SHIFT (0U)
24430/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
24431 */
24432#define DDRPHY_DX2BDLR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX2BDLR9_RESERVED_5_0_MASK)
24433#define DDRPHY_DX2BDLR9_RESERVED_7_6_MASK (0xC0U)
24434#define DDRPHY_DX2BDLR9_RESERVED_7_6_SHIFT (6U)
24435/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
24436 */
24437#define DDRPHY_DX2BDLR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX2BDLR9_RESERVED_7_6_MASK)
24438#define DDRPHY_DX2BDLR9_RESERVED_13_8_MASK (0x3F00U)
24439#define DDRPHY_DX2BDLR9_RESERVED_13_8_SHIFT (8U)
24440/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
24441 */
24442#define DDRPHY_DX2BDLR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX2BDLR9_RESERVED_13_8_MASK)
24443#define DDRPHY_DX2BDLR9_RESERVED_15_14_MASK (0xC000U)
24444#define DDRPHY_DX2BDLR9_RESERVED_15_14_SHIFT (14U)
24445/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
24446 */
24447#define DDRPHY_DX2BDLR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX2BDLR9_RESERVED_15_14_MASK)
24448#define DDRPHY_DX2BDLR9_RESERVED_21_16_MASK (0x3F0000U)
24449#define DDRPHY_DX2BDLR9_RESERVED_21_16_SHIFT (16U)
24450/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
24451 */
24452#define DDRPHY_DX2BDLR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX2BDLR9_RESERVED_21_16_MASK)
24453#define DDRPHY_DX2BDLR9_RESERVED_31_22_MASK (0xFFC00000U)
24454#define DDRPHY_DX2BDLR9_RESERVED_31_22_SHIFT (22U)
24455/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
24456 */
24457#define DDRPHY_DX2BDLR9_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX2BDLR9_RESERVED_31_22_MASK)
24458/*! @} */
24459
24460/*! @name DX2LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */
24461/*! @{ */
24462#define DDRPHY_DX2LCDLR0_WLD_MASK (0x1FFU)
24463#define DDRPHY_DX2LCDLR0_WLD_SHIFT (0U)
24464/*! WLD - Write Leveling Delay
24465 */
24466#define DDRPHY_DX2LCDLR0_WLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR0_WLD_SHIFT)) & DDRPHY_DX2LCDLR0_WLD_MASK)
24467#define DDRPHY_DX2LCDLR0_RESERVED_15_9_MASK (0xFE00U)
24468#define DDRPHY_DX2LCDLR0_RESERVED_15_9_SHIFT (9U)
24469/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
24470 */
24471#define DDRPHY_DX2LCDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX2LCDLR0_RESERVED_15_9_MASK)
24472#define DDRPHY_DX2LCDLR0_RESERVED_24_16_MASK (0x1FF0000U)
24473#define DDRPHY_DX2LCDLR0_RESERVED_24_16_SHIFT (16U)
24474/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
24475 */
24476#define DDRPHY_DX2LCDLR0_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX2LCDLR0_RESERVED_24_16_MASK)
24477#define DDRPHY_DX2LCDLR0_RESERVED_31_25_MASK (0xFE000000U)
24478#define DDRPHY_DX2LCDLR0_RESERVED_31_25_SHIFT (25U)
24479/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
24480 */
24481#define DDRPHY_DX2LCDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX2LCDLR0_RESERVED_31_25_MASK)
24482/*! @} */
24483
24484/*! @name DX2LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */
24485/*! @{ */
24486#define DDRPHY_DX2LCDLR1_WDQD_MASK (0x1FFU)
24487#define DDRPHY_DX2LCDLR1_WDQD_SHIFT (0U)
24488/*! WDQD - Write Data Delay
24489 */
24490#define DDRPHY_DX2LCDLR1_WDQD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR1_WDQD_SHIFT)) & DDRPHY_DX2LCDLR1_WDQD_MASK)
24491#define DDRPHY_DX2LCDLR1_RESERVED_15_9_MASK (0xFE00U)
24492#define DDRPHY_DX2LCDLR1_RESERVED_15_9_SHIFT (9U)
24493/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
24494 */
24495#define DDRPHY_DX2LCDLR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX2LCDLR1_RESERVED_15_9_MASK)
24496#define DDRPHY_DX2LCDLR1_RESERVED_24_16_MASK (0x1FF0000U)
24497#define DDRPHY_DX2LCDLR1_RESERVED_24_16_SHIFT (16U)
24498/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
24499 */
24500#define DDRPHY_DX2LCDLR1_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX2LCDLR1_RESERVED_24_16_MASK)
24501#define DDRPHY_DX2LCDLR1_RESERVED_31_25_MASK (0xFE000000U)
24502#define DDRPHY_DX2LCDLR1_RESERVED_31_25_SHIFT (25U)
24503/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
24504 */
24505#define DDRPHY_DX2LCDLR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX2LCDLR1_RESERVED_31_25_MASK)
24506/*! @} */
24507
24508/*! @name DX2LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */
24509/*! @{ */
24510#define DDRPHY_DX2LCDLR2_DQSGD_MASK (0x1FFU)
24511#define DDRPHY_DX2LCDLR2_DQSGD_SHIFT (0U)
24512/*! DQSGD - Read DQS Gating Delay
24513 */
24514#define DDRPHY_DX2LCDLR2_DQSGD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX2LCDLR2_DQSGD_MASK)
24515#define DDRPHY_DX2LCDLR2_RESERVED_15_9_MASK (0xFE00U)
24516#define DDRPHY_DX2LCDLR2_RESERVED_15_9_SHIFT (9U)
24517/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
24518 */
24519#define DDRPHY_DX2LCDLR2_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX2LCDLR2_RESERVED_15_9_MASK)
24520#define DDRPHY_DX2LCDLR2_RESERVED_24_16_MASK (0x1FF0000U)
24521#define DDRPHY_DX2LCDLR2_RESERVED_24_16_SHIFT (16U)
24522/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
24523 */
24524#define DDRPHY_DX2LCDLR2_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX2LCDLR2_RESERVED_24_16_MASK)
24525#define DDRPHY_DX2LCDLR2_RESERVED_31_25_MASK (0xFE000000U)
24526#define DDRPHY_DX2LCDLR2_RESERVED_31_25_SHIFT (25U)
24527/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
24528 */
24529#define DDRPHY_DX2LCDLR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX2LCDLR2_RESERVED_31_25_MASK)
24530/*! @} */
24531
24532/*! @name DX2LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */
24533/*! @{ */
24534#define DDRPHY_DX2LCDLR3_RDQSD_MASK (0x1FFU)
24535#define DDRPHY_DX2LCDLR3_RDQSD_SHIFT (0U)
24536/*! RDQSD - Read DQS Delay
24537 */
24538#define DDRPHY_DX2LCDLR3_RDQSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX2LCDLR3_RDQSD_MASK)
24539#define DDRPHY_DX2LCDLR3_RESERVED_15_9_MASK (0xFE00U)
24540#define DDRPHY_DX2LCDLR3_RESERVED_15_9_SHIFT (9U)
24541/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
24542 */
24543#define DDRPHY_DX2LCDLR3_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX2LCDLR3_RESERVED_15_9_MASK)
24544#define DDRPHY_DX2LCDLR3_RESERVED_24_16_MASK (0x1FF0000U)
24545#define DDRPHY_DX2LCDLR3_RESERVED_24_16_SHIFT (16U)
24546/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
24547 */
24548#define DDRPHY_DX2LCDLR3_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX2LCDLR3_RESERVED_24_16_MASK)
24549#define DDRPHY_DX2LCDLR3_RESERVED_31_25_MASK (0xFE000000U)
24550#define DDRPHY_DX2LCDLR3_RESERVED_31_25_SHIFT (25U)
24551/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
24552 */
24553#define DDRPHY_DX2LCDLR3_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX2LCDLR3_RESERVED_31_25_MASK)
24554/*! @} */
24555
24556/*! @name DX2LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */
24557/*! @{ */
24558#define DDRPHY_DX2LCDLR4_RDQSND_MASK (0x1FFU)
24559#define DDRPHY_DX2LCDLR4_RDQSND_SHIFT (0U)
24560/*! RDQSND - Read DQSN Delay
24561 */
24562#define DDRPHY_DX2LCDLR4_RDQSND(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX2LCDLR4_RDQSND_MASK)
24563#define DDRPHY_DX2LCDLR4_RESERVED_15_9_MASK (0xFE00U)
24564#define DDRPHY_DX2LCDLR4_RESERVED_15_9_SHIFT (9U)
24565/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
24566 */
24567#define DDRPHY_DX2LCDLR4_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX2LCDLR4_RESERVED_15_9_MASK)
24568#define DDRPHY_DX2LCDLR4_RESERVED_24_16_MASK (0x1FF0000U)
24569#define DDRPHY_DX2LCDLR4_RESERVED_24_16_SHIFT (16U)
24570/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
24571 */
24572#define DDRPHY_DX2LCDLR4_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX2LCDLR4_RESERVED_24_16_MASK)
24573#define DDRPHY_DX2LCDLR4_RESERVED_31_25_MASK (0xFE000000U)
24574#define DDRPHY_DX2LCDLR4_RESERVED_31_25_SHIFT (25U)
24575/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
24576 */
24577#define DDRPHY_DX2LCDLR4_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX2LCDLR4_RESERVED_31_25_MASK)
24578/*! @} */
24579
24580/*! @name DX2LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */
24581/*! @{ */
24582#define DDRPHY_DX2LCDLR5_DQSGSD_MASK (0x1FFU)
24583#define DDRPHY_DX2LCDLR5_DQSGSD_SHIFT (0U)
24584/*! DQSGSD - DQS Gating Status Delay
24585 */
24586#define DDRPHY_DX2LCDLR5_DQSGSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX2LCDLR5_DQSGSD_MASK)
24587#define DDRPHY_DX2LCDLR5_RESERVED_15_9_MASK (0xFE00U)
24588#define DDRPHY_DX2LCDLR5_RESERVED_15_9_SHIFT (9U)
24589/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
24590 */
24591#define DDRPHY_DX2LCDLR5_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX2LCDLR5_RESERVED_15_9_MASK)
24592#define DDRPHY_DX2LCDLR5_RESERVED_24_16_MASK (0x1FF0000U)
24593#define DDRPHY_DX2LCDLR5_RESERVED_24_16_SHIFT (16U)
24594/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
24595 */
24596#define DDRPHY_DX2LCDLR5_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX2LCDLR5_RESERVED_24_16_MASK)
24597#define DDRPHY_DX2LCDLR5_RESERVED_31_25_MASK (0xFE000000U)
24598#define DDRPHY_DX2LCDLR5_RESERVED_31_25_SHIFT (25U)
24599/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
24600 */
24601#define DDRPHY_DX2LCDLR5_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX2LCDLR5_RESERVED_31_25_MASK)
24602/*! @} */
24603
24604/*! @name DX2MDLR0 - DATX8 n Master Delay Line Register 0 */
24605/*! @{ */
24606#define DDRPHY_DX2MDLR0_IPRD_MASK (0x1FFU)
24607#define DDRPHY_DX2MDLR0_IPRD_SHIFT (0U)
24608/*! IPRD - Initial Period
24609 */
24610#define DDRPHY_DX2MDLR0_IPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2MDLR0_IPRD_SHIFT)) & DDRPHY_DX2MDLR0_IPRD_MASK)
24611#define DDRPHY_DX2MDLR0_RESERVED_15_9_MASK (0xFE00U)
24612#define DDRPHY_DX2MDLR0_RESERVED_15_9_SHIFT (9U)
24613/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
24614 */
24615#define DDRPHY_DX2MDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX2MDLR0_RESERVED_15_9_MASK)
24616#define DDRPHY_DX2MDLR0_TPRD_MASK (0x1FF0000U)
24617#define DDRPHY_DX2MDLR0_TPRD_SHIFT (16U)
24618/*! TPRD - Target Period
24619 */
24620#define DDRPHY_DX2MDLR0_TPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2MDLR0_TPRD_SHIFT)) & DDRPHY_DX2MDLR0_TPRD_MASK)
24621#define DDRPHY_DX2MDLR0_RESERVED_31_25_MASK (0xFE000000U)
24622#define DDRPHY_DX2MDLR0_RESERVED_31_25_SHIFT (25U)
24623/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
24624 */
24625#define DDRPHY_DX2MDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX2MDLR0_RESERVED_31_25_MASK)
24626/*! @} */
24627
24628/*! @name DX2MDLR1 - DATX8 n Master Delay Line Register 1 */
24629/*! @{ */
24630#define DDRPHY_DX2MDLR1_MDLD_MASK (0x1FFU)
24631#define DDRPHY_DX2MDLR1_MDLD_SHIFT (0U)
24632/*! MDLD - MDL Delay
24633 */
24634#define DDRPHY_DX2MDLR1_MDLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2MDLR1_MDLD_SHIFT)) & DDRPHY_DX2MDLR1_MDLD_MASK)
24635#define DDRPHY_DX2MDLR1_RESERVED_31_9_MASK (0xFFFFFE00U)
24636#define DDRPHY_DX2MDLR1_RESERVED_31_9_SHIFT (9U)
24637/*! RESERVED_31_9 - Reserved. Return zeroes on reads.
24638 */
24639#define DDRPHY_DX2MDLR1_RESERVED_31_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX2MDLR1_RESERVED_31_9_MASK)
24640/*! @} */
24641
24642/*! @name DX2GTR0 - DATX8 n General Timing Register 0 */
24643/*! @{ */
24644#define DDRPHY_DX2GTR0_DGSL_MASK (0x1FU)
24645#define DDRPHY_DX2GTR0_DGSL_SHIFT (0U)
24646/*! DGSL - DQS Gating System Latency
24647 */
24648#define DDRPHY_DX2GTR0_DGSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_DGSL_SHIFT)) & DDRPHY_DX2GTR0_DGSL_MASK)
24649#define DDRPHY_DX2GTR0_RESERVED_7_5_MASK (0xE0U)
24650#define DDRPHY_DX2GTR0_RESERVED_7_5_SHIFT (5U)
24651/*! RESERVED_7_5 - Reserved. Return zeroes on reads.
24652 */
24653#define DDRPHY_DX2GTR0_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX2GTR0_RESERVED_7_5_MASK)
24654#define DDRPHY_DX2GTR0_RESERVED_12_8_MASK (0x1F00U)
24655#define DDRPHY_DX2GTR0_RESERVED_12_8_SHIFT (8U)
24656/*! RESERVED_12_8 - Reserved. Caution, do not write to this register field.
24657 */
24658#define DDRPHY_DX2GTR0_RESERVED_12_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX2GTR0_RESERVED_12_8_MASK)
24659#define DDRPHY_DX2GTR0_RESERVED_15_13_MASK (0xE000U)
24660#define DDRPHY_DX2GTR0_RESERVED_15_13_SHIFT (13U)
24661/*! RESERVED_15_13 - Reserved. Return zeroes on reads.
24662 */
24663#define DDRPHY_DX2GTR0_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX2GTR0_RESERVED_15_13_MASK)
24664#define DDRPHY_DX2GTR0_WLSL_MASK (0xF0000U)
24665#define DDRPHY_DX2GTR0_WLSL_SHIFT (16U)
24666/*! WLSL - Write Leveling System Latency
24667 */
24668#define DDRPHY_DX2GTR0_WLSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_WLSL_SHIFT)) & DDRPHY_DX2GTR0_WLSL_MASK)
24669#define DDRPHY_DX2GTR0_RESERVED_23_20_MASK (0xF00000U)
24670#define DDRPHY_DX2GTR0_RESERVED_23_20_SHIFT (20U)
24671/*! RESERVED_23_20 - Reserved. Caution, do not write to this register field.
24672 */
24673#define DDRPHY_DX2GTR0_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX2GTR0_RESERVED_23_20_MASK)
24674#define DDRPHY_DX2GTR0_WDQSL_MASK (0x7000000U)
24675#define DDRPHY_DX2GTR0_WDQSL_SHIFT (24U)
24676/*! WDQSL - DQ Write Path Latency Pipeline
24677 */
24678#define DDRPHY_DX2GTR0_WDQSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_WDQSL_SHIFT)) & DDRPHY_DX2GTR0_WDQSL_MASK)
24679#define DDRPHY_DX2GTR0_RESERVED_31_24_MASK (0xF8000000U)
24680#define DDRPHY_DX2GTR0_RESERVED_31_24_SHIFT (27U)
24681/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
24682 */
24683#define DDRPHY_DX2GTR0_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX2GTR0_RESERVED_31_24_MASK)
24684/*! @} */
24685
24686/*! @name DX2RSR0 - DATX8 n Rank Status Register 0 */
24687/*! @{ */
24688#define DDRPHY_DX2RSR0_QSGERR_MASK (0xFFFFU)
24689#define DDRPHY_DX2RSR0_QSGERR_SHIFT (0U)
24690/*! QSGERR - DQS Gate Training Error
24691 */
24692#define DDRPHY_DX2RSR0_QSGERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR0_QSGERR_SHIFT)) & DDRPHY_DX2RSR0_QSGERR_MASK)
24693#define DDRPHY_DX2RSR0_RESERVED_31_16_MASK (0xFFFF0000U)
24694#define DDRPHY_DX2RSR0_RESERVED_31_16_SHIFT (16U)
24695/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
24696 */
24697#define DDRPHY_DX2RSR0_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX2RSR0_RESERVED_31_16_MASK)
24698/*! @} */
24699
24700/*! @name DX2RSR1 - DATX8 n Rank Status Register 1 */
24701/*! @{ */
24702#define DDRPHY_DX2RSR1_RDLVLERR_MASK (0xFFFFU)
24703#define DDRPHY_DX2RSR1_RDLVLERR_SHIFT (0U)
24704/*! RDLVLERR - Read Leveling Error
24705 */
24706#define DDRPHY_DX2RSR1_RDLVLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX2RSR1_RDLVLERR_MASK)
24707#define DDRPHY_DX2RSR1_RESERVED_31_16_MASK (0xFFFF0000U)
24708#define DDRPHY_DX2RSR1_RESERVED_31_16_SHIFT (16U)
24709/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
24710 */
24711#define DDRPHY_DX2RSR1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX2RSR1_RESERVED_31_16_MASK)
24712/*! @} */
24713
24714/*! @name DX2RSR2 - DATX8 n Rank Status Register 2 */
24715/*! @{ */
24716#define DDRPHY_DX2RSR2_WLAWN_MASK (0xFFFFU)
24717#define DDRPHY_DX2RSR2_WLAWN_SHIFT (0U)
24718/*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning
24719 */
24720#define DDRPHY_DX2RSR2_WLAWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR2_WLAWN_SHIFT)) & DDRPHY_DX2RSR2_WLAWN_MASK)
24721#define DDRPHY_DX2RSR2_RESERVED_31_16_MASK (0xFFFF0000U)
24722#define DDRPHY_DX2RSR2_RESERVED_31_16_SHIFT (16U)
24723/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
24724 */
24725#define DDRPHY_DX2RSR2_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX2RSR2_RESERVED_31_16_MASK)
24726/*! @} */
24727
24728/*! @name DX2RSR3 - DATX8 n Rank Status Register 3 */
24729/*! @{ */
24730#define DDRPHY_DX2RSR3_WLAERR_MASK (0xFFFFU)
24731#define DDRPHY_DX2RSR3_WLAERR_SHIFT (0U)
24732/*! WLAERR - Write Leveling Adjustment Error
24733 */
24734#define DDRPHY_DX2RSR3_WLAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR3_WLAERR_SHIFT)) & DDRPHY_DX2RSR3_WLAERR_MASK)
24735#define DDRPHY_DX2RSR3_RESERVED_31_16_MASK (0xFFFF0000U)
24736#define DDRPHY_DX2RSR3_RESERVED_31_16_SHIFT (16U)
24737/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
24738 */
24739#define DDRPHY_DX2RSR3_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX2RSR3_RESERVED_31_16_MASK)
24740/*! @} */
24741
24742/*! @name DX2GSR0 - DATX8 n General Status Register 0 */
24743/*! @{ */
24744#define DDRPHY_DX2GSR0_WDQCAL_MASK (0x1U)
24745#define DDRPHY_DX2GSR0_WDQCAL_SHIFT (0U)
24746/*! WDQCAL - Write DQ Calibration
24747 */
24748#define DDRPHY_DX2GSR0_WDQCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_WDQCAL_SHIFT)) & DDRPHY_DX2GSR0_WDQCAL_MASK)
24749#define DDRPHY_DX2GSR0_RDQSCAL_MASK (0x2U)
24750#define DDRPHY_DX2GSR0_RDQSCAL_SHIFT (1U)
24751/*! RDQSCAL - Read DQS Calibration
24752 */
24753#define DDRPHY_DX2GSR0_RDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX2GSR0_RDQSCAL_MASK)
24754#define DDRPHY_DX2GSR0_RDQSNCAL_MASK (0x4U)
24755#define DDRPHY_DX2GSR0_RDQSNCAL_SHIFT (2U)
24756/*! RDQSNCAL - Read DQS# Calibration
24757 */
24758#define DDRPHY_DX2GSR0_RDQSNCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX2GSR0_RDQSNCAL_MASK)
24759#define DDRPHY_DX2GSR0_GDQSCAL_MASK (0x8U)
24760#define DDRPHY_DX2GSR0_GDQSCAL_SHIFT (3U)
24761/*! GDQSCAL - Read DQS gating Calibration
24762 */
24763#define DDRPHY_DX2GSR0_GDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX2GSR0_GDQSCAL_MASK)
24764#define DDRPHY_DX2GSR0_WLCAL_MASK (0x10U)
24765#define DDRPHY_DX2GSR0_WLCAL_SHIFT (4U)
24766/*! WLCAL - Write Leveling Calibration
24767 */
24768#define DDRPHY_DX2GSR0_WLCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_WLCAL_SHIFT)) & DDRPHY_DX2GSR0_WLCAL_MASK)
24769#define DDRPHY_DX2GSR0_WLDONE_MASK (0x20U)
24770#define DDRPHY_DX2GSR0_WLDONE_SHIFT (5U)
24771/*! WLDONE - Write Leveling Done
24772 */
24773#define DDRPHY_DX2GSR0_WLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_WLDONE_SHIFT)) & DDRPHY_DX2GSR0_WLDONE_MASK)
24774#define DDRPHY_DX2GSR0_WLERR_MASK (0x40U)
24775#define DDRPHY_DX2GSR0_WLERR_SHIFT (6U)
24776/*! WLERR - Write Leveling Error
24777 */
24778#define DDRPHY_DX2GSR0_WLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_WLERR_SHIFT)) & DDRPHY_DX2GSR0_WLERR_MASK)
24779#define DDRPHY_DX2GSR0_WLPRD_MASK (0xFF80U)
24780#define DDRPHY_DX2GSR0_WLPRD_SHIFT (7U)
24781/*! WLPRD - Write Leveling Period
24782 */
24783#define DDRPHY_DX2GSR0_WLPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_WLPRD_SHIFT)) & DDRPHY_DX2GSR0_WLPRD_MASK)
24784#define DDRPHY_DX2GSR0_DPLOCK_MASK (0x10000U)
24785#define DDRPHY_DX2GSR0_DPLOCK_SHIFT (16U)
24786/*! DPLOCK - DATX8 PLL Lock
24787 */
24788#define DDRPHY_DX2GSR0_DPLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_DPLOCK_SHIFT)) & DDRPHY_DX2GSR0_DPLOCK_MASK)
24789#define DDRPHY_DX2GSR0_GDQSPRD_MASK (0x3FE0000U)
24790#define DDRPHY_DX2GSR0_GDQSPRD_SHIFT (17U)
24791/*! GDQSPRD - Read DQS gating Period
24792 */
24793#define DDRPHY_DX2GSR0_GDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX2GSR0_GDQSPRD_MASK)
24794#define DDRPHY_DX2GSR0_RESERVED_29_26_MASK (0x3C000000U)
24795#define DDRPHY_DX2GSR0_RESERVED_29_26_SHIFT (26U)
24796/*! RESERVED_29_26 - Reserved. Returns zeroes on reads.
24797 */
24798#define DDRPHY_DX2GSR0_RESERVED_29_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX2GSR0_RESERVED_29_26_MASK)
24799#define DDRPHY_DX2GSR0_WLDQ_MASK (0x40000000U)
24800#define DDRPHY_DX2GSR0_WLDQ_SHIFT (30U)
24801/*! WLDQ - Write Leveling DQ Status
24802 */
24803#define DDRPHY_DX2GSR0_WLDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_WLDQ_SHIFT)) & DDRPHY_DX2GSR0_WLDQ_MASK)
24804#define DDRPHY_DX2GSR0_RESERVED_31_MASK (0x80000000U)
24805#define DDRPHY_DX2GSR0_RESERVED_31_SHIFT (31U)
24806/*! RESERVED_31 - Reserved. Returns zeroes on reads.
24807 */
24808#define DDRPHY_DX2GSR0_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX2GSR0_RESERVED_31_MASK)
24809/*! @} */
24810
24811/*! @name DX2GSR1 - DATX8 n General Status Register 1 */
24812/*! @{ */
24813#define DDRPHY_DX2GSR1_DLTDONE_MASK (0x1U)
24814#define DDRPHY_DX2GSR1_DLTDONE_SHIFT (0U)
24815/*! DLTDONE - Delay Line Test Done
24816 */
24817#define DDRPHY_DX2GSR1_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR1_DLTDONE_SHIFT)) & DDRPHY_DX2GSR1_DLTDONE_MASK)
24818#define DDRPHY_DX2GSR1_DLTCODE_MASK (0x1FFFFFEU)
24819#define DDRPHY_DX2GSR1_DLTCODE_SHIFT (1U)
24820/*! DLTCODE - Delay Line Test Code
24821 */
24822#define DDRPHY_DX2GSR1_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR1_DLTCODE_SHIFT)) & DDRPHY_DX2GSR1_DLTCODE_MASK)
24823#define DDRPHY_DX2GSR1_RESERVED_31_25_MASK (0xFE000000U)
24824#define DDRPHY_DX2GSR1_RESERVED_31_25_SHIFT (25U)
24825/*! RESERVED_31_25 - Reserved. Returns zeroes on reads.
24826 */
24827#define DDRPHY_DX2GSR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX2GSR1_RESERVED_31_25_MASK)
24828/*! @} */
24829
24830/*! @name DX2GSR2 - DATX8 n General Status Register 2 */
24831/*! @{ */
24832#define DDRPHY_DX2GSR2_RDERR_MASK (0x1U)
24833#define DDRPHY_DX2GSR2_RDERR_SHIFT (0U)
24834/*! RDERR - Read Bit Deskew Error
24835 */
24836#define DDRPHY_DX2GSR2_RDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_RDERR_SHIFT)) & DDRPHY_DX2GSR2_RDERR_MASK)
24837#define DDRPHY_DX2GSR2_RDWN_MASK (0x2U)
24838#define DDRPHY_DX2GSR2_RDWN_SHIFT (1U)
24839/*! RDWN - Read Bit Deskew Warning
24840 */
24841#define DDRPHY_DX2GSR2_RDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_RDWN_SHIFT)) & DDRPHY_DX2GSR2_RDWN_MASK)
24842#define DDRPHY_DX2GSR2_WDERR_MASK (0x4U)
24843#define DDRPHY_DX2GSR2_WDERR_SHIFT (2U)
24844/*! WDERR - Write Bit Deskew Error
24845 */
24846#define DDRPHY_DX2GSR2_WDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_WDERR_SHIFT)) & DDRPHY_DX2GSR2_WDERR_MASK)
24847#define DDRPHY_DX2GSR2_WDWN_MASK (0x8U)
24848#define DDRPHY_DX2GSR2_WDWN_SHIFT (3U)
24849/*! WDWN - Write Bit Deskew Warning
24850 */
24851#define DDRPHY_DX2GSR2_WDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_WDWN_SHIFT)) & DDRPHY_DX2GSR2_WDWN_MASK)
24852#define DDRPHY_DX2GSR2_REERR_MASK (0x10U)
24853#define DDRPHY_DX2GSR2_REERR_SHIFT (4U)
24854/*! REERR - Read Eye Centering Error
24855 */
24856#define DDRPHY_DX2GSR2_REERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_REERR_SHIFT)) & DDRPHY_DX2GSR2_REERR_MASK)
24857#define DDRPHY_DX2GSR2_REWN_MASK (0x20U)
24858#define DDRPHY_DX2GSR2_REWN_SHIFT (5U)
24859/*! REWN - Read Eye Centering Warning
24860 */
24861#define DDRPHY_DX2GSR2_REWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_REWN_SHIFT)) & DDRPHY_DX2GSR2_REWN_MASK)
24862#define DDRPHY_DX2GSR2_WEERR_MASK (0x40U)
24863#define DDRPHY_DX2GSR2_WEERR_SHIFT (6U)
24864/*! WEERR - Write Eye Centering Error
24865 */
24866#define DDRPHY_DX2GSR2_WEERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_WEERR_SHIFT)) & DDRPHY_DX2GSR2_WEERR_MASK)
24867#define DDRPHY_DX2GSR2_WEWN_MASK (0x80U)
24868#define DDRPHY_DX2GSR2_WEWN_SHIFT (7U)
24869/*! WEWN - Write Eye Centering Warning
24870 */
24871#define DDRPHY_DX2GSR2_WEWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_WEWN_SHIFT)) & DDRPHY_DX2GSR2_WEWN_MASK)
24872#define DDRPHY_DX2GSR2_ESTAT_MASK (0xF00U)
24873#define DDRPHY_DX2GSR2_ESTAT_SHIFT (8U)
24874/*! ESTAT - Error Status
24875 */
24876#define DDRPHY_DX2GSR2_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_ESTAT_SHIFT)) & DDRPHY_DX2GSR2_ESTAT_MASK)
24877#define DDRPHY_DX2GSR2_DQS2DQERR_MASK (0xFF000U)
24878#define DDRPHY_DX2GSR2_DQS2DQERR_SHIFT (12U)
24879/*! DQS2DQERR - Write DQS2DQ Training Error
24880 */
24881#define DDRPHY_DX2GSR2_DQS2DQERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX2GSR2_DQS2DQERR_MASK)
24882#define DDRPHY_DX2GSR2_SRDERR_MASK (0x100000U)
24883#define DDRPHY_DX2GSR2_SRDERR_SHIFT (20U)
24884/*! SRDERR - Static Read Error
24885 */
24886#define DDRPHY_DX2GSR2_SRDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_SRDERR_SHIFT)) & DDRPHY_DX2GSR2_SRDERR_MASK)
24887#define DDRPHY_DX2GSR2_RESERVED_21_MASK (0x200000U)
24888#define DDRPHY_DX2GSR2_RESERVED_21_SHIFT (21U)
24889/*! RESERVED_21 - Reserved. Return zeroes on reads.
24890 */
24891#define DDRPHY_DX2GSR2_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX2GSR2_RESERVED_21_MASK)
24892#define DDRPHY_DX2GSR2_GSDQSCAL_MASK (0x400000U)
24893#define DDRPHY_DX2GSR2_GSDQSCAL_SHIFT (22U)
24894/*! GSDQSCAL - Read DQS Gating Status Calibration
24895 */
24896#define DDRPHY_DX2GSR2_GSDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX2GSR2_GSDQSCAL_MASK)
24897#define DDRPHY_DX2GSR2_GSDQSPRD_MASK (0xFF800000U)
24898#define DDRPHY_DX2GSR2_GSDQSPRD_SHIFT (23U)
24899/*! GSDQSPRD - Read DQS gating Status Period
24900 */
24901#define DDRPHY_DX2GSR2_GSDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX2GSR2_GSDQSPRD_MASK)
24902/*! @} */
24903
24904/*! @name DX2GSR3 - DATX8 n General Status Register 3 */
24905/*! @{ */
24906#define DDRPHY_DX2GSR3_SRDPC_MASK (0x3U)
24907#define DDRPHY_DX2GSR3_SRDPC_SHIFT (0U)
24908/*! SRDPC - Static Read Delay Pass Count
24909 */
24910#define DDRPHY_DX2GSR3_SRDPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_SRDPC_SHIFT)) & DDRPHY_DX2GSR3_SRDPC_MASK)
24911#define DDRPHY_DX2GSR3_RESERVED_7_2_MASK (0xFCU)
24912#define DDRPHY_DX2GSR3_RESERVED_7_2_SHIFT (2U)
24913/*! RESERVED_7_2 - Reserved. Return zeroes on reads.
24914 */
24915#define DDRPHY_DX2GSR3_RESERVED_7_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX2GSR3_RESERVED_7_2_MASK)
24916#define DDRPHY_DX2GSR3_HVERR_MASK (0xF00U)
24917#define DDRPHY_DX2GSR3_HVERR_SHIFT (8U)
24918/*! HVERR - Host VREF Training Error
24919 */
24920#define DDRPHY_DX2GSR3_HVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_HVERR_SHIFT)) & DDRPHY_DX2GSR3_HVERR_MASK)
24921#define DDRPHY_DX2GSR3_HVWRN_MASK (0xF000U)
24922#define DDRPHY_DX2GSR3_HVWRN_SHIFT (12U)
24923/*! HVWRN - Host VREF Training Warning
24924 */
24925#define DDRPHY_DX2GSR3_HVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_HVWRN_SHIFT)) & DDRPHY_DX2GSR3_HVWRN_MASK)
24926#define DDRPHY_DX2GSR3_DVERR_MASK (0xF0000U)
24927#define DDRPHY_DX2GSR3_DVERR_SHIFT (16U)
24928/*! DVERR - DRAM VREF Training Error
24929 */
24930#define DDRPHY_DX2GSR3_DVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_DVERR_SHIFT)) & DDRPHY_DX2GSR3_DVERR_MASK)
24931#define DDRPHY_DX2GSR3_DVWRN_MASK (0xF00000U)
24932#define DDRPHY_DX2GSR3_DVWRN_SHIFT (20U)
24933/*! DVWRN - DRAM VREF Training Warning
24934 */
24935#define DDRPHY_DX2GSR3_DVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_DVWRN_SHIFT)) & DDRPHY_DX2GSR3_DVWRN_MASK)
24936#define DDRPHY_DX2GSR3_ESTAT_MASK (0x7000000U)
24937#define DDRPHY_DX2GSR3_ESTAT_SHIFT (24U)
24938/*! ESTAT - VREF Training Error Status Code
24939 */
24940#define DDRPHY_DX2GSR3_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_ESTAT_SHIFT)) & DDRPHY_DX2GSR3_ESTAT_MASK)
24941#define DDRPHY_DX2GSR3_RESERVED_31_27_MASK (0xF8000000U)
24942#define DDRPHY_DX2GSR3_RESERVED_31_27_SHIFT (27U)
24943/*! RESERVED_31_27 - Reserved. Return zeroes on reads.
24944 */
24945#define DDRPHY_DX2GSR3_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX2GSR3_RESERVED_31_27_MASK)
24946/*! @} */
24947
24948/*! @name DX2GSR4 - DATX8 n General Status Register 4 */
24949/*! @{ */
24950#define DDRPHY_DX2GSR4_RESERVED_0_MASK (0x1U)
24951#define DDRPHY_DX2GSR4_RESERVED_0_SHIFT (0U)
24952/*! RESERVED_0 - Reserved. Return zeroes on reads.
24953 */
24954#define DDRPHY_DX2GSR4_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_0_MASK)
24955#define DDRPHY_DX2GSR4_RESERVED_1_MASK (0x2U)
24956#define DDRPHY_DX2GSR4_RESERVED_1_SHIFT (1U)
24957/*! RESERVED_1 - Reserved. Return zeroes on reads.
24958 */
24959#define DDRPHY_DX2GSR4_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_1_MASK)
24960#define DDRPHY_DX2GSR4_RESERVED_2_MASK (0x4U)
24961#define DDRPHY_DX2GSR4_RESERVED_2_SHIFT (2U)
24962/*! RESERVED_2 - Reserved. Return zeroes on reads.
24963 */
24964#define DDRPHY_DX2GSR4_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_2_MASK)
24965#define DDRPHY_DX2GSR4_RESERVED_3_MASK (0x8U)
24966#define DDRPHY_DX2GSR4_RESERVED_3_SHIFT (3U)
24967/*! RESERVED_3 - Reserved. Return zeroes on reads.
24968 */
24969#define DDRPHY_DX2GSR4_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_3_MASK)
24970#define DDRPHY_DX2GSR4_RESERVED_4_MASK (0x10U)
24971#define DDRPHY_DX2GSR4_RESERVED_4_SHIFT (4U)
24972/*! RESERVED_4 - Reserved. Return zeroes on reads.
24973 */
24974#define DDRPHY_DX2GSR4_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_4_MASK)
24975#define DDRPHY_DX2GSR4_RESERVED_5_MASK (0x20U)
24976#define DDRPHY_DX2GSR4_RESERVED_5_SHIFT (5U)
24977/*! RESERVED_5 - Reserved. Return zeroes on reads.
24978 */
24979#define DDRPHY_DX2GSR4_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_5_MASK)
24980#define DDRPHY_DX2GSR4_RESERVED_6_MASK (0x40U)
24981#define DDRPHY_DX2GSR4_RESERVED_6_SHIFT (6U)
24982/*! RESERVED_6 - Reserved. Return zeroes on reads.
24983 */
24984#define DDRPHY_DX2GSR4_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_6_MASK)
24985#define DDRPHY_DX2GSR4_RESERVED_15_7_MASK (0xFF80U)
24986#define DDRPHY_DX2GSR4_RESERVED_15_7_SHIFT (7U)
24987/*! RESERVED_15_7 - Reserved. Return zeroes on reads.
24988 */
24989#define DDRPHY_DX2GSR4_RESERVED_15_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_15_7_MASK)
24990#define DDRPHY_DX2GSR4_RESERVED_16_MASK (0x10000U)
24991#define DDRPHY_DX2GSR4_RESERVED_16_SHIFT (16U)
24992/*! RESERVED_16 - Reserved. Return zeroes on reads.
24993 */
24994#define DDRPHY_DX2GSR4_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_16_MASK)
24995#define DDRPHY_DX2GSR4_RESERVED_25_17_MASK (0x3FE0000U)
24996#define DDRPHY_DX2GSR4_RESERVED_25_17_SHIFT (17U)
24997/*! RESERVED_25_17 - Reserved. Return zeroes on reads.
24998 */
24999#define DDRPHY_DX2GSR4_RESERVED_25_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_25_17_MASK)
25000#define DDRPHY_DX2GSR4_RESERVED_31_26_MASK (0xFC000000U)
25001#define DDRPHY_DX2GSR4_RESERVED_31_26_SHIFT (26U)
25002/*! RESERVED_31_26 - Reserved. Returns zeroes on reads.
25003 */
25004#define DDRPHY_DX2GSR4_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX2GSR4_RESERVED_31_26_MASK)
25005/*! @} */
25006
25007/*! @name DX2GSR5 - DATX8 n General Status Register 5 */
25008/*! @{ */
25009#define DDRPHY_DX2GSR5_RESERVED_0_MASK (0x1U)
25010#define DDRPHY_DX2GSR5_RESERVED_0_SHIFT (0U)
25011/*! RESERVED_0 - Reserved. Return zeroes on reads.
25012 */
25013#define DDRPHY_DX2GSR5_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_0_MASK)
25014#define DDRPHY_DX2GSR5_RESERVED_1_MASK (0x2U)
25015#define DDRPHY_DX2GSR5_RESERVED_1_SHIFT (1U)
25016/*! RESERVED_1 - Reserved. Return zeroes on reads.
25017 */
25018#define DDRPHY_DX2GSR5_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_1_MASK)
25019#define DDRPHY_DX2GSR5_RESERVED_2_MASK (0x4U)
25020#define DDRPHY_DX2GSR5_RESERVED_2_SHIFT (2U)
25021/*! RESERVED_2 - Reserved. Return zeroes on reads.
25022 */
25023#define DDRPHY_DX2GSR5_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_2_MASK)
25024#define DDRPHY_DX2GSR5_RESERVED_3_MASK (0x8U)
25025#define DDRPHY_DX2GSR5_RESERVED_3_SHIFT (3U)
25026/*! RESERVED_3 - Reserved. Return zeroes on reads.
25027 */
25028#define DDRPHY_DX2GSR5_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_3_MASK)
25029#define DDRPHY_DX2GSR5_RESERVED_4_MASK (0x10U)
25030#define DDRPHY_DX2GSR5_RESERVED_4_SHIFT (4U)
25031/*! RESERVED_4 - Reserved. Return zeroes on reads.
25032 */
25033#define DDRPHY_DX2GSR5_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_4_MASK)
25034#define DDRPHY_DX2GSR5_RESERVED_5_MASK (0x20U)
25035#define DDRPHY_DX2GSR5_RESERVED_5_SHIFT (5U)
25036/*! RESERVED_5 - Reserved. Return zeroes on reads.
25037 */
25038#define DDRPHY_DX2GSR5_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_5_MASK)
25039#define DDRPHY_DX2GSR5_RESERVED_6_MASK (0x40U)
25040#define DDRPHY_DX2GSR5_RESERVED_6_SHIFT (6U)
25041/*! RESERVED_6 - Reserved. Return zeroes on reads.
25042 */
25043#define DDRPHY_DX2GSR5_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_6_MASK)
25044#define DDRPHY_DX2GSR5_RESERVED_7_MASK (0x80U)
25045#define DDRPHY_DX2GSR5_RESERVED_7_SHIFT (7U)
25046/*! RESERVED_7 - Reserved. Return zeroes on reads.
25047 */
25048#define DDRPHY_DX2GSR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_7_MASK)
25049#define DDRPHY_DX2GSR5_RESERVED_11_8_MASK (0xF00U)
25050#define DDRPHY_DX2GSR5_RESERVED_11_8_SHIFT (8U)
25051/*! RESERVED_11_8 - Reserved. Return zeroes on reads.
25052 */
25053#define DDRPHY_DX2GSR5_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_11_8_MASK)
25054#define DDRPHY_DX2GSR5_RESERVED_19_12_MASK (0xFF000U)
25055#define DDRPHY_DX2GSR5_RESERVED_19_12_SHIFT (12U)
25056/*! RESERVED_19_12 - Reserved. Return zeroes on reads.
25057 */
25058#define DDRPHY_DX2GSR5_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_19_12_MASK)
25059#define DDRPHY_DX2GSR5_RESERVED_20_MASK (0x100000U)
25060#define DDRPHY_DX2GSR5_RESERVED_20_SHIFT (20U)
25061/*! RESERVED_20 - Reserved. Return zeroes on reads.
25062 */
25063#define DDRPHY_DX2GSR5_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_20_MASK)
25064#define DDRPHY_DX2GSR5_RESERVED_21_MASK (0x200000U)
25065#define DDRPHY_DX2GSR5_RESERVED_21_SHIFT (21U)
25066/*! RESERVED_21 - Reserved. Return zeroes on reads.
25067 */
25068#define DDRPHY_DX2GSR5_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_21_MASK)
25069#define DDRPHY_DX2GSR5_RESERVED_22_MASK (0x400000U)
25070#define DDRPHY_DX2GSR5_RESERVED_22_SHIFT (22U)
25071/*! RESERVED_22 - Reserved. Return zeroes on reads.
25072 */
25073#define DDRPHY_DX2GSR5_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_22_MASK)
25074#define DDRPHY_DX2GSR5_RESERVED_31_23_MASK (0xFF800000U)
25075#define DDRPHY_DX2GSR5_RESERVED_31_23_SHIFT (23U)
25076/*! RESERVED_31_23 - Reserved. Return zeroes on reads.
25077 */
25078#define DDRPHY_DX2GSR5_RESERVED_31_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX2GSR5_RESERVED_31_23_MASK)
25079/*! @} */
25080
25081/*! @name DX2GSR6 - DATX8 n General Status Register 6 */
25082/*! @{ */
25083#define DDRPHY_DX2GSR6_RESERVED_1_0_MASK (0x3U)
25084#define DDRPHY_DX2GSR6_RESERVED_1_0_SHIFT (0U)
25085/*! RESERVED_1_0 - Reserved. Return zeroes on reads.
25086 */
25087#define DDRPHY_DX2GSR6_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_1_0_MASK)
25088#define DDRPHY_DX2GSR6_RESERVED_3_2_MASK (0xCU)
25089#define DDRPHY_DX2GSR6_RESERVED_3_2_SHIFT (2U)
25090/*! RESERVED_3_2 - Reserved. Return zeroes on reads.
25091 */
25092#define DDRPHY_DX2GSR6_RESERVED_3_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_3_2_MASK)
25093#define DDRPHY_DX2GSR6_RESERVED_7_4_MASK (0xF0U)
25094#define DDRPHY_DX2GSR6_RESERVED_7_4_SHIFT (4U)
25095/*! RESERVED_7_4 - Reserved. Return zeroes on reads.
25096 */
25097#define DDRPHY_DX2GSR6_RESERVED_7_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_7_4_MASK)
25098#define DDRPHY_DX2GSR6_RESERVED_11_8_MASK (0xF00U)
25099#define DDRPHY_DX2GSR6_RESERVED_11_8_SHIFT (8U)
25100/*! RESERVED_11_8 - Reserved. Return zeroes on reads.
25101 */
25102#define DDRPHY_DX2GSR6_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_11_8_MASK)
25103#define DDRPHY_DX2GSR6_RESERVED_15_12_MASK (0xF000U)
25104#define DDRPHY_DX2GSR6_RESERVED_15_12_SHIFT (12U)
25105/*! RESERVED_15_12 - Reserved. Return zeroes on reads.
25106 */
25107#define DDRPHY_DX2GSR6_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_15_12_MASK)
25108#define DDRPHY_DX2GSR6_RESERVED_19_15_MASK (0xF0000U)
25109#define DDRPHY_DX2GSR6_RESERVED_19_15_SHIFT (16U)
25110/*! RESERVED_19_15 - Reserved. Return zeroes on reads.
25111 */
25112#define DDRPHY_DX2GSR6_RESERVED_19_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_19_15_MASK)
25113#define DDRPHY_DX2GSR6_RESERVED_23_20_MASK (0xF00000U)
25114#define DDRPHY_DX2GSR6_RESERVED_23_20_SHIFT (20U)
25115/*! RESERVED_23_20 - Reserved. Return zeroes on reads.
25116 */
25117#define DDRPHY_DX2GSR6_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_23_20_MASK)
25118#define DDRPHY_DX2GSR6_RESERVED_31_24_MASK (0xFF000000U)
25119#define DDRPHY_DX2GSR6_RESERVED_31_24_SHIFT (24U)
25120/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
25121 */
25122#define DDRPHY_DX2GSR6_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX2GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX2GSR6_RESERVED_31_24_MASK)
25123/*! @} */
25124
25125/*! @name DX3GCR0 - DATX8 n General Configuration Register 0 */
25126/*! @{ */
25127#define DDRPHY_DX3GCR0_RESERVED_1_0_MASK (0x3U)
25128#define DDRPHY_DX3GCR0_RESERVED_1_0_SHIFT (0U)
25129/*! RESERVED_1_0 - Reserved. Return zeroes on reads.
25130 */
25131#define DDRPHY_DX3GCR0_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX3GCR0_RESERVED_1_0_MASK)
25132#define DDRPHY_DX3GCR0_DQSGOE_MASK (0x4U)
25133#define DDRPHY_DX3GCR0_DQSGOE_SHIFT (2U)
25134/*! DQSGOE - DQSG Output Enable
25135 */
25136#define DDRPHY_DX3GCR0_DQSGOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSGOE_SHIFT)) & DDRPHY_DX3GCR0_DQSGOE_MASK)
25137#define DDRPHY_DX3GCR0_DQSGODT_MASK (0x8U)
25138#define DDRPHY_DX3GCR0_DQSGODT_SHIFT (3U)
25139/*! DQSGODT - DQSG On-Die Termination
25140 */
25141#define DDRPHY_DX3GCR0_DQSGODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSGODT_SHIFT)) & DDRPHY_DX3GCR0_DQSGODT_MASK)
25142#define DDRPHY_DX3GCR0_RESERVED_4_MASK (0x10U)
25143#define DDRPHY_DX3GCR0_RESERVED_4_SHIFT (4U)
25144/*! RESERVED_4 - Reserved. Return zeroes on reads.
25145 */
25146#define DDRPHY_DX3GCR0_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX3GCR0_RESERVED_4_MASK)
25147#define DDRPHY_DX3GCR0_DQSGPDR_MASK (0x20U)
25148#define DDRPHY_DX3GCR0_DQSGPDR_SHIFT (5U)
25149/*! DQSGPDR - DQSG Power Down Receiver
25150 */
25151#define DDRPHY_DX3GCR0_DQSGPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX3GCR0_DQSGPDR_MASK)
25152#define DDRPHY_DX3GCR0_DQSRPD_MASK (0x40U)
25153#define DDRPHY_DX3GCR0_DQSRPD_SHIFT (6U)
25154/*! DQSRPD - DQSR Power Down
25155 */
25156#define DDRPHY_DX3GCR0_DQSRPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSRPD_SHIFT)) & DDRPHY_DX3GCR0_DQSRPD_MASK)
25157#define DDRPHY_DX3GCR0_CPDRSHFT_MASK (0x180U)
25158#define DDRPHY_DX3GCR0_CPDRSHFT_SHIFT (7U)
25159/*! CPDRSHFT - Configurable PDR Phase Shift
25160 */
25161#define DDRPHY_DX3GCR0_CPDRSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX3GCR0_CPDRSHFT_MASK)
25162#define DDRPHY_DX3GCR0_RTTOH_MASK (0x600U)
25163#define DDRPHY_DX3GCR0_RTTOH_SHIFT (9U)
25164/*! RTTOH - RTT Output Hold
25165 */
25166#define DDRPHY_DX3GCR0_RTTOH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_RTTOH_SHIFT)) & DDRPHY_DX3GCR0_RTTOH_MASK)
25167#define DDRPHY_DX3GCR0_RTTOAL_MASK (0x800U)
25168#define DDRPHY_DX3GCR0_RTTOAL_SHIFT (11U)
25169/*! RTTOAL - RTT On Additive Latency
25170 */
25171#define DDRPHY_DX3GCR0_RTTOAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_RTTOAL_SHIFT)) & DDRPHY_DX3GCR0_RTTOAL_MASK)
25172#define DDRPHY_DX3GCR0_DQSSEPDR_MASK (0x1000U)
25173#define DDRPHY_DX3GCR0_DQSSEPDR_SHIFT (12U)
25174/*! DQSSEPDR - DQSSE Power Down Receiver
25175 */
25176#define DDRPHY_DX3GCR0_DQSSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX3GCR0_DQSSEPDR_MASK)
25177#define DDRPHY_DX3GCR0_DQSNSEPDR_MASK (0x2000U)
25178#define DDRPHY_DX3GCR0_DQSNSEPDR_SHIFT (13U)
25179/*! DQSNSEPDR - DQSNSE Power Down Receiver
25180 */
25181#define DDRPHY_DX3GCR0_DQSNSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX3GCR0_DQSNSEPDR_MASK)
25182#define DDRPHY_DX3GCR0_RESERVED_19_14_MASK (0xFC000U)
25183#define DDRPHY_DX3GCR0_RESERVED_19_14_SHIFT (14U)
25184/*! RESERVED_19_14 - Reserved. Return zeroes on reads.
25185 */
25186#define DDRPHY_DX3GCR0_RESERVED_19_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX3GCR0_RESERVED_19_14_MASK)
25187#define DDRPHY_DX3GCR0_RDDLY_MASK (0xF00000U)
25188#define DDRPHY_DX3GCR0_RDDLY_SHIFT (20U)
25189/*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
25190 */
25191#define DDRPHY_DX3GCR0_RDDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_RDDLY_SHIFT)) & DDRPHY_DX3GCR0_RDDLY_MASK)
25192#define DDRPHY_DX3GCR0_DQSDCC_MASK (0xF000000U)
25193#define DDRPHY_DX3GCR0_DQSDCC_SHIFT (24U)
25194/*! DQSDCC - DQS Duty Cycle Correction
25195 */
25196#define DDRPHY_DX3GCR0_DQSDCC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_DQSDCC_SHIFT)) & DDRPHY_DX3GCR0_DQSDCC_MASK)
25197#define DDRPHY_DX3GCR0_CODTSHFT_MASK (0x30000000U)
25198#define DDRPHY_DX3GCR0_CODTSHFT_SHIFT (28U)
25199/*! CODTSHFT - Configurable ODT(TE) Phase Shift
25200 */
25201#define DDRPHY_DX3GCR0_CODTSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX3GCR0_CODTSHFT_MASK)
25202#define DDRPHY_DX3GCR0_MDLEN_MASK (0x40000000U)
25203#define DDRPHY_DX3GCR0_MDLEN_SHIFT (30U)
25204/*! MDLEN - Master Delay Line Enable
25205 */
25206#define DDRPHY_DX3GCR0_MDLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_MDLEN_SHIFT)) & DDRPHY_DX3GCR0_MDLEN_MASK)
25207#define DDRPHY_DX3GCR0_CALBYP_MASK (0x80000000U)
25208#define DDRPHY_DX3GCR0_CALBYP_SHIFT (31U)
25209/*! CALBYP - Calibration Bypass
25210 */
25211#define DDRPHY_DX3GCR0_CALBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR0_CALBYP_SHIFT)) & DDRPHY_DX3GCR0_CALBYP_MASK)
25212/*! @} */
25213
25214/*! @name DX3GCR1 - DATX8 n General Configuration Register 1 */
25215/*! @{ */
25216#define DDRPHY_DX3GCR1_DQEN_MASK (0xFFU)
25217#define DDRPHY_DX3GCR1_DQEN_SHIFT (0U)
25218/*! DQEN - Enables DQ corresponding to each bit in a byte
25219 */
25220#define DDRPHY_DX3GCR1_DQEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_DQEN_SHIFT)) & DDRPHY_DX3GCR1_DQEN_MASK)
25221#define DDRPHY_DX3GCR1_DMEN_MASK (0x100U)
25222#define DDRPHY_DX3GCR1_DMEN_SHIFT (8U)
25223/*! DMEN - Enables DM pin in a byte lane
25224 */
25225#define DDRPHY_DX3GCR1_DMEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_DMEN_SHIFT)) & DDRPHY_DX3GCR1_DMEN_MASK)
25226#define DDRPHY_DX3GCR1_DSEN_MASK (0x200U)
25227#define DDRPHY_DX3GCR1_DSEN_SHIFT (9U)
25228/*! DSEN - Enables Write Data strobe in a byte lane
25229 */
25230#define DDRPHY_DX3GCR1_DSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_DSEN_SHIFT)) & DDRPHY_DX3GCR1_DSEN_MASK)
25231#define DDRPHY_DX3GCR1_TEEN_MASK (0x400U)
25232#define DDRPHY_DX3GCR1_TEEN_SHIFT (10U)
25233/*! TEEN - Enables ODT/TE in a byte lane
25234 */
25235#define DDRPHY_DX3GCR1_TEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_TEEN_SHIFT)) & DDRPHY_DX3GCR1_TEEN_MASK)
25236#define DDRPHY_DX3GCR1_PDREN_MASK (0x800U)
25237#define DDRPHY_DX3GCR1_PDREN_SHIFT (11U)
25238/*! PDREN - Enables PDR in a byte lane
25239 */
25240#define DDRPHY_DX3GCR1_PDREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_PDREN_SHIFT)) & DDRPHY_DX3GCR1_PDREN_MASK)
25241#define DDRPHY_DX3GCR1_OEEN_MASK (0x1000U)
25242#define DDRPHY_DX3GCR1_OEEN_SHIFT (12U)
25243/*! OEEN - Enables Read Data Strobe in a byte lane
25244 */
25245#define DDRPHY_DX3GCR1_OEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_OEEN_SHIFT)) & DDRPHY_DX3GCR1_OEEN_MASK)
25246#define DDRPHY_DX3GCR1_QSSEL_MASK (0x2000U)
25247#define DDRPHY_DX3GCR1_QSSEL_SHIFT (13U)
25248/*! QSSEL - Select the delayed or non-delayed read data strobe
25249 */
25250#define DDRPHY_DX3GCR1_QSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_QSSEL_SHIFT)) & DDRPHY_DX3GCR1_QSSEL_MASK)
25251#define DDRPHY_DX3GCR1_QSNSEL_MASK (0x4000U)
25252#define DDRPHY_DX3GCR1_QSNSEL_SHIFT (14U)
25253/*! QSNSEL - Select the delayed or non-delayed read data strobe #
25254 */
25255#define DDRPHY_DX3GCR1_QSNSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_QSNSEL_SHIFT)) & DDRPHY_DX3GCR1_QSNSEL_MASK)
25256#define DDRPHY_DX3GCR1_RESERVED_15_MASK (0x8000U)
25257#define DDRPHY_DX3GCR1_RESERVED_15_SHIFT (15U)
25258/*! RESERVED_15 - Reserved. Returns zeroes on reads.
25259 */
25260#define DDRPHY_DX3GCR1_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX3GCR1_RESERVED_15_MASK)
25261#define DDRPHY_DX3GCR1_DXPDRMODE_MASK (0xFFFF0000U)
25262#define DDRPHY_DX3GCR1_DXPDRMODE_SHIFT (16U)
25263/*! DXPDRMODE - Enables the PDR mode for DQ[7:0]
25264 */
25265#define DDRPHY_DX3GCR1_DXPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX3GCR1_DXPDRMODE_MASK)
25266/*! @} */
25267
25268/*! @name DX3GCR2 - DATX8 n General Configuration Register 2 */
25269/*! @{ */
25270#define DDRPHY_DX3GCR2_DXTEMODE_MASK (0xFFFFU)
25271#define DDRPHY_DX3GCR2_DXTEMODE_SHIFT (0U)
25272/*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0]
25273 */
25274#define DDRPHY_DX3GCR2_DXTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX3GCR2_DXTEMODE_MASK)
25275#define DDRPHY_DX3GCR2_DXOEMODE_MASK (0xFFFF0000U)
25276#define DDRPHY_DX3GCR2_DXOEMODE_SHIFT (16U)
25277/*! DXOEMODE - Enables the OE mode values for DQ[7:0]
25278 */
25279#define DDRPHY_DX3GCR2_DXOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX3GCR2_DXOEMODE_MASK)
25280/*! @} */
25281
25282/*! @name DX3GCR3 - DATX8 n General Configuration Register 3 */
25283/*! @{ */
25284#define DDRPHY_DX3GCR3_WDMBVT_MASK (0x1U)
25285#define DDRPHY_DX3GCR3_WDMBVT_SHIFT (0U)
25286/*! WDMBVT - Write Data Mask BDL VT Compensation
25287 */
25288#define DDRPHY_DX3GCR3_WDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_WDMBVT_SHIFT)) & DDRPHY_DX3GCR3_WDMBVT_MASK)
25289#define DDRPHY_DX3GCR3_RDMBVT_MASK (0x2U)
25290#define DDRPHY_DX3GCR3_RDMBVT_SHIFT (1U)
25291/*! RDMBVT - Read Data Mask BDL VT Compensation
25292 */
25293#define DDRPHY_DX3GCR3_RDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_RDMBVT_SHIFT)) & DDRPHY_DX3GCR3_RDMBVT_MASK)
25294#define DDRPHY_DX3GCR3_DSPDRMODE_MASK (0xCU)
25295#define DDRPHY_DX3GCR3_DSPDRMODE_SHIFT (2U)
25296/*! DSPDRMODE - Enables the PDR mode values for DQS.
25297 */
25298#define DDRPHY_DX3GCR3_DSPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX3GCR3_DSPDRMODE_MASK)
25299#define DDRPHY_DX3GCR3_DSTEMODE_MASK (0x30U)
25300#define DDRPHY_DX3GCR3_DSTEMODE_SHIFT (4U)
25301/*! DSTEMODE - Enables the TE mode values for DQS.
25302 */
25303#define DDRPHY_DX3GCR3_DSTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX3GCR3_DSTEMODE_MASK)
25304#define DDRPHY_DX3GCR3_DSOEMODE_MASK (0xC0U)
25305#define DDRPHY_DX3GCR3_DSOEMODE_SHIFT (6U)
25306/*! DSOEMODE - Enables the OE mode values for DQS.
25307 */
25308#define DDRPHY_DX3GCR3_DSOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX3GCR3_DSOEMODE_MASK)
25309#define DDRPHY_DX3GCR3_WDSBVT_MASK (0x100U)
25310#define DDRPHY_DX3GCR3_WDSBVT_SHIFT (8U)
25311/*! WDSBVT - Write Data Strobe BDL VT Compensation
25312 */
25313#define DDRPHY_DX3GCR3_WDSBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_WDSBVT_SHIFT)) & DDRPHY_DX3GCR3_WDSBVT_MASK)
25314#define DDRPHY_DX3GCR3_RESERVED_9_MASK (0x200U)
25315#define DDRPHY_DX3GCR3_RESERVED_9_SHIFT (9U)
25316/*! RESERVED_9 - Reserved. Returns zeroes on reads.
25317 */
25318#define DDRPHY_DX3GCR3_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX3GCR3_RESERVED_9_MASK)
25319#define DDRPHY_DX3GCR3_DMPDRMODE_MASK (0xC00U)
25320#define DDRPHY_DX3GCR3_DMPDRMODE_SHIFT (10U)
25321/*! DMPDRMODE - Enables the PDR mode values for DM.
25322 */
25323#define DDRPHY_DX3GCR3_DMPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX3GCR3_DMPDRMODE_MASK)
25324#define DDRPHY_DX3GCR3_DMTEMODE_MASK (0x3000U)
25325#define DDRPHY_DX3GCR3_DMTEMODE_SHIFT (12U)
25326/*! DMTEMODE - Enables the TE mode values for DM.
25327 */
25328#define DDRPHY_DX3GCR3_DMTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX3GCR3_DMTEMODE_MASK)
25329#define DDRPHY_DX3GCR3_DMOEMODE_MASK (0xC000U)
25330#define DDRPHY_DX3GCR3_DMOEMODE_SHIFT (14U)
25331/*! DMOEMODE - Enables the OE mode values for DM.
25332 */
25333#define DDRPHY_DX3GCR3_DMOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX3GCR3_DMOEMODE_MASK)
25334#define DDRPHY_DX3GCR3_DSNPDRMODE_MASK (0x30000U)
25335#define DDRPHY_DX3GCR3_DSNPDRMODE_SHIFT (16U)
25336/*! DSNPDRMODE - Enables the PDR mode for DQS
25337 */
25338#define DDRPHY_DX3GCR3_DSNPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX3GCR3_DSNPDRMODE_MASK)
25339#define DDRPHY_DX3GCR3_DSNTEMODE_MASK (0xC0000U)
25340#define DDRPHY_DX3GCR3_DSNTEMODE_SHIFT (18U)
25341/*! DSNTEMODE - Enables the TE mode for DQS
25342 */
25343#define DDRPHY_DX3GCR3_DSNTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX3GCR3_DSNTEMODE_MASK)
25344#define DDRPHY_DX3GCR3_DSNOEMODE_MASK (0x300000U)
25345#define DDRPHY_DX3GCR3_DSNOEMODE_SHIFT (20U)
25346/*! DSNOEMODE - Enables the OE mode for DQs
25347 */
25348#define DDRPHY_DX3GCR3_DSNOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX3GCR3_DSNOEMODE_MASK)
25349#define DDRPHY_DX3GCR3_PDRBVT_MASK (0x400000U)
25350#define DDRPHY_DX3GCR3_PDRBVT_SHIFT (22U)
25351/*! PDRBVT - Power Down Receiver BDL VT Compensation
25352 */
25353#define DDRPHY_DX3GCR3_PDRBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_PDRBVT_SHIFT)) & DDRPHY_DX3GCR3_PDRBVT_MASK)
25354#define DDRPHY_DX3GCR3_RGSLVT_MASK (0x800000U)
25355#define DDRPHY_DX3GCR3_RGSLVT_SHIFT (23U)
25356/*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation
25357 */
25358#define DDRPHY_DX3GCR3_RGSLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_RGSLVT_SHIFT)) & DDRPHY_DX3GCR3_RGSLVT_MASK)
25359#define DDRPHY_DX3GCR3_WLLVT_MASK (0x1000000U)
25360#define DDRPHY_DX3GCR3_WLLVT_SHIFT (24U)
25361/*! WLLVT - Write Leveling LCDL Delay VT Compensation
25362 */
25363#define DDRPHY_DX3GCR3_WLLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_WLLVT_SHIFT)) & DDRPHY_DX3GCR3_WLLVT_MASK)
25364#define DDRPHY_DX3GCR3_WDLVT_MASK (0x2000000U)
25365#define DDRPHY_DX3GCR3_WDLVT_SHIFT (25U)
25366/*! WDLVT - Write DQ LCDL Delay VT Compensation
25367 */
25368#define DDRPHY_DX3GCR3_WDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_WDLVT_SHIFT)) & DDRPHY_DX3GCR3_WDLVT_MASK)
25369#define DDRPHY_DX3GCR3_RDLVT_MASK (0x4000000U)
25370#define DDRPHY_DX3GCR3_RDLVT_SHIFT (26U)
25371/*! RDLVT - Read DQS LCDL Delay VT Compensation
25372 */
25373#define DDRPHY_DX3GCR3_RDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_RDLVT_SHIFT)) & DDRPHY_DX3GCR3_RDLVT_MASK)
25374#define DDRPHY_DX3GCR3_RGLVT_MASK (0x8000000U)
25375#define DDRPHY_DX3GCR3_RGLVT_SHIFT (27U)
25376/*! RGLVT - Read DQS Gating LCDL Delay VT Compensation
25377 */
25378#define DDRPHY_DX3GCR3_RGLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_RGLVT_SHIFT)) & DDRPHY_DX3GCR3_RGLVT_MASK)
25379#define DDRPHY_DX3GCR3_WDBVT_MASK (0x10000000U)
25380#define DDRPHY_DX3GCR3_WDBVT_SHIFT (28U)
25381/*! WDBVT - Write Data BDL VT Compensation
25382 */
25383#define DDRPHY_DX3GCR3_WDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_WDBVT_SHIFT)) & DDRPHY_DX3GCR3_WDBVT_MASK)
25384#define DDRPHY_DX3GCR3_RDBVT_MASK (0x20000000U)
25385#define DDRPHY_DX3GCR3_RDBVT_SHIFT (29U)
25386/*! RDBVT - Read Data BDL VT Compensation
25387 */
25388#define DDRPHY_DX3GCR3_RDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_RDBVT_SHIFT)) & DDRPHY_DX3GCR3_RDBVT_MASK)
25389#define DDRPHY_DX3GCR3_TEBVT_MASK (0x40000000U)
25390#define DDRPHY_DX3GCR3_TEBVT_SHIFT (30U)
25391/*! TEBVT - Termination Enable BDL VT Compensation
25392 */
25393#define DDRPHY_DX3GCR3_TEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_TEBVT_SHIFT)) & DDRPHY_DX3GCR3_TEBVT_MASK)
25394#define DDRPHY_DX3GCR3_OEBVT_MASK (0x80000000U)
25395#define DDRPHY_DX3GCR3_OEBVT_SHIFT (31U)
25396/*! OEBVT - Output Enable BDL VT Compensation
25397 */
25398#define DDRPHY_DX3GCR3_OEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR3_OEBVT_SHIFT)) & DDRPHY_DX3GCR3_OEBVT_MASK)
25399/*! @} */
25400
25401/*! @name DX3GCR4 - DATX8 n General Configuration Register 4 */
25402/*! @{ */
25403#define DDRPHY_DX3GCR4_DXREFIMON_MASK (0x3U)
25404#define DDRPHY_DX3GCR4_DXREFIMON_SHIFT (0U)
25405/*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane.
25406 */
25407#define DDRPHY_DX3GCR4_DXREFIMON(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX3GCR4_DXREFIMON_MASK)
25408#define DDRPHY_DX3GCR4_DXREFIEN_MASK (0x3CU)
25409#define DDRPHY_DX3GCR4_DXREFIEN_SHIFT (2U)
25410/*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
25411 */
25412#define DDRPHY_DX3GCR4_DXREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX3GCR4_DXREFIEN_MASK)
25413#define DDRPHY_DX3GCR4_RESERVED_7_6_MASK (0xC0U)
25414#define DDRPHY_DX3GCR4_RESERVED_7_6_SHIFT (6U)
25415/*! RESERVED_7_6 - Reserved. Returns zeros on reads.
25416 */
25417#define DDRPHY_DX3GCR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX3GCR4_RESERVED_7_6_MASK)
25418#define DDRPHY_DX3GCR4_DXREFSSEL_MASK (0x7F00U)
25419#define DDRPHY_DX3GCR4_DXREFSSEL_SHIFT (8U)
25420/*! DXREFSSEL - Byte Lane Single-End VREF Select
25421 */
25422#define DDRPHY_DX3GCR4_DXREFSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX3GCR4_DXREFSSEL_MASK)
25423#define DDRPHY_DX3GCR4_DXREFSSELRANGE_MASK (0x8000U)
25424#define DDRPHY_DX3GCR4_DXREFSSELRANGE_SHIFT (15U)
25425/*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select
25426 */
25427#define DDRPHY_DX3GCR4_DXREFSSELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX3GCR4_DXREFSSELRANGE_MASK)
25428#define DDRPHY_DX3GCR4_DXREFESEL_MASK (0x7F0000U)
25429#define DDRPHY_DX3GCR4_DXREFESEL_SHIFT (16U)
25430/*! DXREFESEL - Byte Lane External VREF Select
25431 */
25432#define DDRPHY_DX3GCR4_DXREFESEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX3GCR4_DXREFESEL_MASK)
25433#define DDRPHY_DX3GCR4_DXREFESELRANGE_MASK (0x800000U)
25434#define DDRPHY_DX3GCR4_DXREFESELRANGE_SHIFT (23U)
25435/*! DXREFESELRANGE - External VREF generator REFSEL range select
25436 */
25437#define DDRPHY_DX3GCR4_DXREFESELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX3GCR4_DXREFESELRANGE_MASK)
25438#define DDRPHY_DX3GCR4_RESERVED_24_MASK (0x1000000U)
25439#define DDRPHY_DX3GCR4_RESERVED_24_SHIFT (24U)
25440/*! RESERVED_24 - Reserved. Returns zeros on reads.
25441 */
25442#define DDRPHY_DX3GCR4_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX3GCR4_RESERVED_24_MASK)
25443#define DDRPHY_DX3GCR4_DXREFSEN_MASK (0x2000000U)
25444#define DDRPHY_DX3GCR4_DXREFSEN_SHIFT (25U)
25445/*! DXREFSEN - Byte Lane Single-End VREF Enable
25446 */
25447#define DDRPHY_DX3GCR4_DXREFSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX3GCR4_DXREFSEN_MASK)
25448#define DDRPHY_DX3GCR4_DXREFEEN_MASK (0xC000000U)
25449#define DDRPHY_DX3GCR4_DXREFEEN_SHIFT (26U)
25450/*! DXREFEEN - Byte Lane Internal VREF Enable
25451 */
25452#define DDRPHY_DX3GCR4_DXREFEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX3GCR4_DXREFEEN_MASK)
25453#define DDRPHY_DX3GCR4_DXREFPEN_MASK (0x10000000U)
25454#define DDRPHY_DX3GCR4_DXREFPEN_SHIFT (28U)
25455/*! DXREFPEN - Byte Lane VREF Pad Enable
25456 */
25457#define DDRPHY_DX3GCR4_DXREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX3GCR4_DXREFPEN_MASK)
25458#define DDRPHY_DX3GCR4_RESERVED_31_29_MASK (0xE0000000U)
25459#define DDRPHY_DX3GCR4_RESERVED_31_29_SHIFT (29U)
25460/*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs)
25461 */
25462#define DDRPHY_DX3GCR4_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX3GCR4_RESERVED_31_29_MASK)
25463/*! @} */
25464
25465/*! @name DX3GCR5 - DATX8 n General Configuration Register 5 */
25466/*! @{ */
25467#define DDRPHY_DX3GCR5_DXREFISELR0_MASK (0x7FU)
25468#define DDRPHY_DX3GCR5_DXREFISELR0_SHIFT (0U)
25469/*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0
25470 */
25471#define DDRPHY_DX3GCR5_DXREFISELR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX3GCR5_DXREFISELR0_MASK)
25472#define DDRPHY_DX3GCR5_RESERVED_7_MASK (0x80U)
25473#define DDRPHY_DX3GCR5_RESERVED_7_SHIFT (7U)
25474/*! RESERVED_7 - Reserved. Returns zeros on reads.
25475 */
25476#define DDRPHY_DX3GCR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX3GCR5_RESERVED_7_MASK)
25477#define DDRPHY_DX3GCR5_DXREFISELR1_MASK (0x7F00U)
25478#define DDRPHY_DX3GCR5_DXREFISELR1_SHIFT (8U)
25479/*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1
25480 */
25481#define DDRPHY_DX3GCR5_DXREFISELR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX3GCR5_DXREFISELR1_MASK)
25482#define DDRPHY_DX3GCR5_RESERVED_15_MASK (0x8000U)
25483#define DDRPHY_DX3GCR5_RESERVED_15_SHIFT (15U)
25484/*! RESERVED_15 - Reserved. Returns zeros on reads.
25485 */
25486#define DDRPHY_DX3GCR5_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX3GCR5_RESERVED_15_MASK)
25487#define DDRPHY_DX3GCR5_DXREFISELR2_MASK (0x7F0000U)
25488#define DDRPHY_DX3GCR5_DXREFISELR2_SHIFT (16U)
25489/*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2
25490 */
25491#define DDRPHY_DX3GCR5_DXREFISELR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX3GCR5_DXREFISELR2_MASK)
25492#define DDRPHY_DX3GCR5_RESERVED_23_MASK (0x800000U)
25493#define DDRPHY_DX3GCR5_RESERVED_23_SHIFT (23U)
25494/*! RESERVED_23 - Reserved. Returns zeros on reads.
25495 */
25496#define DDRPHY_DX3GCR5_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX3GCR5_RESERVED_23_MASK)
25497#define DDRPHY_DX3GCR5_DXREFISELR3_MASK (0x7F000000U)
25498#define DDRPHY_DX3GCR5_DXREFISELR3_SHIFT (24U)
25499/*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3
25500 */
25501#define DDRPHY_DX3GCR5_DXREFISELR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX3GCR5_DXREFISELR3_MASK)
25502#define DDRPHY_DX3GCR5_RESERVED_31_MASK (0x80000000U)
25503#define DDRPHY_DX3GCR5_RESERVED_31_SHIFT (31U)
25504/*! RESERVED_31 - Reserved. Returns zeros on reads.
25505 */
25506#define DDRPHY_DX3GCR5_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX3GCR5_RESERVED_31_MASK)
25507/*! @} */
25508
25509/*! @name DX3GCR6 - DATX8 n General Configuration Register 6 */
25510/*! @{ */
25511#define DDRPHY_DX3GCR6_DXDQVREFR0_MASK (0x3FU)
25512#define DDRPHY_DX3GCR6_DXDQVREFR0_SHIFT (0U)
25513/*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0
25514 */
25515#define DDRPHY_DX3GCR6_DXDQVREFR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX3GCR6_DXDQVREFR0_MASK)
25516#define DDRPHY_DX3GCR6_RESERVED_7_6_MASK (0xC0U)
25517#define DDRPHY_DX3GCR6_RESERVED_7_6_SHIFT (6U)
25518/*! RESERVED_7_6 - Reserved. Returns zeros on reads.
25519 */
25520#define DDRPHY_DX3GCR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX3GCR6_RESERVED_7_6_MASK)
25521#define DDRPHY_DX3GCR6_DXDQVREFR1_MASK (0x3F00U)
25522#define DDRPHY_DX3GCR6_DXDQVREFR1_SHIFT (8U)
25523/*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1
25524 */
25525#define DDRPHY_DX3GCR6_DXDQVREFR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX3GCR6_DXDQVREFR1_MASK)
25526#define DDRPHY_DX3GCR6_RESERVED_15_14_MASK (0xC000U)
25527#define DDRPHY_DX3GCR6_RESERVED_15_14_SHIFT (14U)
25528/*! RESERVED_15_14 - Reserved. Returns zeros on reads.
25529 */
25530#define DDRPHY_DX3GCR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX3GCR6_RESERVED_15_14_MASK)
25531#define DDRPHY_DX3GCR6_DXDQVREFR2_MASK (0x3F0000U)
25532#define DDRPHY_DX3GCR6_DXDQVREFR2_SHIFT (16U)
25533/*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2
25534 */
25535#define DDRPHY_DX3GCR6_DXDQVREFR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX3GCR6_DXDQVREFR2_MASK)
25536#define DDRPHY_DX3GCR6_RESERVED_23_22_MASK (0xC00000U)
25537#define DDRPHY_DX3GCR6_RESERVED_23_22_SHIFT (22U)
25538/*! RESERVED_23_22 - Reserved. Returns zeros on reads.
25539 */
25540#define DDRPHY_DX3GCR6_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX3GCR6_RESERVED_23_22_MASK)
25541#define DDRPHY_DX3GCR6_DXDQVREFR3_MASK (0x3F000000U)
25542#define DDRPHY_DX3GCR6_DXDQVREFR3_SHIFT (24U)
25543/*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3
25544 */
25545#define DDRPHY_DX3GCR6_DXDQVREFR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX3GCR6_DXDQVREFR3_MASK)
25546#define DDRPHY_DX3GCR6_RESERVED_31_30_MASK (0xC0000000U)
25547#define DDRPHY_DX3GCR6_RESERVED_31_30_SHIFT (30U)
25548/*! RESERVED_31_30 - Reserved. Returns zeros on reads.
25549 */
25550#define DDRPHY_DX3GCR6_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX3GCR6_RESERVED_31_30_MASK)
25551/*! @} */
25552
25553/*! @name DX3GCR7 - DATX8 n General Configuration Register 7 */
25554/*! @{ */
25555#define DDRPHY_DX3GCR7_DCALSVAL_MASK (0x1FFU)
25556#define DDRPHY_DX3GCR7_DCALSVAL_SHIFT (0U)
25557/*! DCALSVAL - DDL Calibration Starting Value
25558 */
25559#define DDRPHY_DX3GCR7_DCALSVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX3GCR7_DCALSVAL_MASK)
25560#define DDRPHY_DX3GCR7_DCALTYPE_MASK (0x200U)
25561#define DDRPHY_DX3GCR7_DCALTYPE_SHIFT (9U)
25562/*! DCALTYPE - DDL Calibration Type
25563 */
25564#define DDRPHY_DX3GCR7_DCALTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX3GCR7_DCALTYPE_MASK)
25565#define DDRPHY_DX3GCR7_RESERVED_17_10_MASK (0x3FC00U)
25566#define DDRPHY_DX3GCR7_RESERVED_17_10_SHIFT (10U)
25567/*! RESERVED_17_10 - Reserved. Caution, do not write to this register field.
25568 */
25569#define DDRPHY_DX3GCR7_RESERVED_17_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX3GCR7_RESERVED_17_10_MASK)
25570#define DDRPHY_DX3GCR7_RESERVED_18_MASK (0x40000U)
25571#define DDRPHY_DX3GCR7_RESERVED_18_SHIFT (18U)
25572/*! RESERVED_18 - Reserved. Caution, do not write to this register field.
25573 */
25574#define DDRPHY_DX3GCR7_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX3GCR7_RESERVED_18_MASK)
25575#define DDRPHY_DX3GCR7_RESERVED_31_19_MASK (0xFFF80000U)
25576#define DDRPHY_DX3GCR7_RESERVED_31_19_SHIFT (19U)
25577/*! RESERVED_31_19 - Reserved. Caution, do not write to this register field.
25578 */
25579#define DDRPHY_DX3GCR7_RESERVED_31_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX3GCR7_RESERVED_31_19_MASK)
25580/*! @} */
25581
25582/*! @name DX3GCR8 - DATX8 n General Configuration Register 8 */
25583/*! @{ */
25584#define DDRPHY_DX3GCR8_RESERVED_5_0_MASK (0x3FU)
25585#define DDRPHY_DX3GCR8_RESERVED_5_0_SHIFT (0U)
25586/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
25587 */
25588#define DDRPHY_DX3GCR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_5_0_MASK)
25589#define DDRPHY_DX3GCR8_RESERVED_7_6_MASK (0xC0U)
25590#define DDRPHY_DX3GCR8_RESERVED_7_6_SHIFT (6U)
25591/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
25592 */
25593#define DDRPHY_DX3GCR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_7_6_MASK)
25594#define DDRPHY_DX3GCR8_RESERVED_13_8_MASK (0x3F00U)
25595#define DDRPHY_DX3GCR8_RESERVED_13_8_SHIFT (8U)
25596/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
25597 */
25598#define DDRPHY_DX3GCR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_13_8_MASK)
25599#define DDRPHY_DX3GCR8_RESERVED_15_14_MASK (0xC000U)
25600#define DDRPHY_DX3GCR8_RESERVED_15_14_SHIFT (14U)
25601/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
25602 */
25603#define DDRPHY_DX3GCR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_15_14_MASK)
25604#define DDRPHY_DX3GCR8_RESERVED_21_16_MASK (0x3F0000U)
25605#define DDRPHY_DX3GCR8_RESERVED_21_16_SHIFT (16U)
25606/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
25607 */
25608#define DDRPHY_DX3GCR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_21_16_MASK)
25609#define DDRPHY_DX3GCR8_RESERVED_23_22_MASK (0xC00000U)
25610#define DDRPHY_DX3GCR8_RESERVED_23_22_SHIFT (22U)
25611/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
25612 */
25613#define DDRPHY_DX3GCR8_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_23_22_MASK)
25614#define DDRPHY_DX3GCR8_RESERVED_29_24_MASK (0x3F000000U)
25615#define DDRPHY_DX3GCR8_RESERVED_29_24_SHIFT (24U)
25616/*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
25617 */
25618#define DDRPHY_DX3GCR8_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_29_24_MASK)
25619#define DDRPHY_DX3GCR8_RESERVED_31_30_MASK (0xC0000000U)
25620#define DDRPHY_DX3GCR8_RESERVED_31_30_SHIFT (30U)
25621/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
25622 */
25623#define DDRPHY_DX3GCR8_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX3GCR8_RESERVED_31_30_MASK)
25624/*! @} */
25625
25626/*! @name DX3GCR9 - DATX8 n General Configuration Register 9 */
25627/*! @{ */
25628#define DDRPHY_DX3GCR9_RESERVED_5_0_MASK (0x3FU)
25629#define DDRPHY_DX3GCR9_RESERVED_5_0_SHIFT (0U)
25630/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
25631 */
25632#define DDRPHY_DX3GCR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_5_0_MASK)
25633#define DDRPHY_DX3GCR9_RESERVED_7_6_MASK (0xC0U)
25634#define DDRPHY_DX3GCR9_RESERVED_7_6_SHIFT (6U)
25635/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
25636 */
25637#define DDRPHY_DX3GCR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_7_6_MASK)
25638#define DDRPHY_DX3GCR9_RESERVED_13_8_MASK (0x3F00U)
25639#define DDRPHY_DX3GCR9_RESERVED_13_8_SHIFT (8U)
25640/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
25641 */
25642#define DDRPHY_DX3GCR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_13_8_MASK)
25643#define DDRPHY_DX3GCR9_RESERVED_15_14_MASK (0xC000U)
25644#define DDRPHY_DX3GCR9_RESERVED_15_14_SHIFT (14U)
25645/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
25646 */
25647#define DDRPHY_DX3GCR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_15_14_MASK)
25648#define DDRPHY_DX3GCR9_RESERVED_21_16_MASK (0x3F0000U)
25649#define DDRPHY_DX3GCR9_RESERVED_21_16_SHIFT (16U)
25650/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
25651 */
25652#define DDRPHY_DX3GCR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_21_16_MASK)
25653#define DDRPHY_DX3GCR9_RESERVED_23_22_MASK (0xC00000U)
25654#define DDRPHY_DX3GCR9_RESERVED_23_22_SHIFT (22U)
25655/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
25656 */
25657#define DDRPHY_DX3GCR9_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_23_22_MASK)
25658#define DDRPHY_DX3GCR9_RESERVED_29_24_MASK (0x3F000000U)
25659#define DDRPHY_DX3GCR9_RESERVED_29_24_SHIFT (24U)
25660/*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
25661 */
25662#define DDRPHY_DX3GCR9_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_29_24_MASK)
25663#define DDRPHY_DX3GCR9_RESERVED_31_30_MASK (0xC0000000U)
25664#define DDRPHY_DX3GCR9_RESERVED_31_30_SHIFT (30U)
25665/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
25666 */
25667#define DDRPHY_DX3GCR9_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX3GCR9_RESERVED_31_30_MASK)
25668/*! @} */
25669
25670/*! @name DX3DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */
25671/*! @{ */
25672#define DDRPHY_DX3DQMAP0_DQ0MAP_MASK (0xFU)
25673#define DDRPHY_DX3DQMAP0_DQ0MAP_SHIFT (0U)
25674/*! DQ0MAP - DQ bit 0 DATX8 slice mapping index
25675 */
25676#define DDRPHY_DX3DQMAP0_DQ0MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX3DQMAP0_DQ0MAP_MASK)
25677#define DDRPHY_DX3DQMAP0_DQ1MAP_MASK (0xF0U)
25678#define DDRPHY_DX3DQMAP0_DQ1MAP_SHIFT (4U)
25679/*! DQ1MAP - DQ bit 1 DATX8 slice mapping index
25680 */
25681#define DDRPHY_DX3DQMAP0_DQ1MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX3DQMAP0_DQ1MAP_MASK)
25682#define DDRPHY_DX3DQMAP0_DQ2MAP_MASK (0xF00U)
25683#define DDRPHY_DX3DQMAP0_DQ2MAP_SHIFT (8U)
25684/*! DQ2MAP - DQ bit 2 DATX8 slice mapping index
25685 */
25686#define DDRPHY_DX3DQMAP0_DQ2MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX3DQMAP0_DQ2MAP_MASK)
25687#define DDRPHY_DX3DQMAP0_DQ3MAP_MASK (0xF000U)
25688#define DDRPHY_DX3DQMAP0_DQ3MAP_SHIFT (12U)
25689/*! DQ3MAP - DQ bit 3 DATX8 slice mapping index
25690 */
25691#define DDRPHY_DX3DQMAP0_DQ3MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX3DQMAP0_DQ3MAP_MASK)
25692#define DDRPHY_DX3DQMAP0_DQ4MAP_MASK (0xF0000U)
25693#define DDRPHY_DX3DQMAP0_DQ4MAP_SHIFT (16U)
25694/*! DQ4MAP - DQ bit 4 DATX8 slice mapping index
25695 */
25696#define DDRPHY_DX3DQMAP0_DQ4MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX3DQMAP0_DQ4MAP_MASK)
25697#define DDRPHY_DX3DQMAP0_RESERVED_30_20_MASK (0x7FF00000U)
25698#define DDRPHY_DX3DQMAP0_RESERVED_30_20_SHIFT (20U)
25699/*! RESERVED_30_20 - Reserved. Return zeroes on reads.
25700 */
25701#define DDRPHY_DX3DQMAP0_RESERVED_30_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX3DQMAP0_RESERVED_30_20_MASK)
25702#define DDRPHY_DX3DQMAP0_MAPOK_MASK (0x80000000U)
25703#define DDRPHY_DX3DQMAP0_MAPOK_SHIFT (31U)
25704/*! MAPOK - Checksum bit
25705 */
25706#define DDRPHY_DX3DQMAP0_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX3DQMAP0_MAPOK_MASK)
25707/*! @} */
25708
25709/*! @name DX3DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */
25710/*! @{ */
25711#define DDRPHY_DX3DQMAP1_DQ5MAP_MASK (0xFU)
25712#define DDRPHY_DX3DQMAP1_DQ5MAP_SHIFT (0U)
25713/*! DQ5MAP - DQ bit 5 DATX8 slice mapping index
25714 */
25715#define DDRPHY_DX3DQMAP1_DQ5MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX3DQMAP1_DQ5MAP_MASK)
25716#define DDRPHY_DX3DQMAP1_DQ6MAP_MASK (0xF0U)
25717#define DDRPHY_DX3DQMAP1_DQ6MAP_SHIFT (4U)
25718/*! DQ6MAP - DQ bit 6 DATX8 slice mapping index
25719 */
25720#define DDRPHY_DX3DQMAP1_DQ6MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX3DQMAP1_DQ6MAP_MASK)
25721#define DDRPHY_DX3DQMAP1_DQ7MAP_MASK (0xF00U)
25722#define DDRPHY_DX3DQMAP1_DQ7MAP_SHIFT (8U)
25723/*! DQ7MAP - DQ bit 7 DATX8 slice mapping index
25724 */
25725#define DDRPHY_DX3DQMAP1_DQ7MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX3DQMAP1_DQ7MAP_MASK)
25726#define DDRPHY_DX3DQMAP1_DMMAP_MASK (0xF000U)
25727#define DDRPHY_DX3DQMAP1_DMMAP_SHIFT (12U)
25728/*! DMMAP - DM bit DATX8 slice mapping index
25729 */
25730#define DDRPHY_DX3DQMAP1_DMMAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX3DQMAP1_DMMAP_MASK)
25731#define DDRPHY_DX3DQMAP1_RESERVED_30_16_MASK (0x7FFF0000U)
25732#define DDRPHY_DX3DQMAP1_RESERVED_30_16_SHIFT (16U)
25733/*! RESERVED_30_16 - Reserved. Return zeroes on reads.
25734 */
25735#define DDRPHY_DX3DQMAP1_RESERVED_30_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX3DQMAP1_RESERVED_30_16_MASK)
25736#define DDRPHY_DX3DQMAP1_MAPOK_MASK (0x80000000U)
25737#define DDRPHY_DX3DQMAP1_MAPOK_SHIFT (31U)
25738/*! MAPOK - Checksum bit
25739 */
25740#define DDRPHY_DX3DQMAP1_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX3DQMAP1_MAPOK_MASK)
25741/*! @} */
25742
25743/*! @name DX3BDLR0 - DATX8 n Bit Delay Line Register 0 */
25744/*! @{ */
25745#define DDRPHY_DX3BDLR0_DQ0WBD_MASK (0x3FU)
25746#define DDRPHY_DX3BDLR0_DQ0WBD_SHIFT (0U)
25747/*! DQ0WBD - DQ0 Write Bit Delay
25748 */
25749#define DDRPHY_DX3BDLR0_DQ0WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX3BDLR0_DQ0WBD_MASK)
25750#define DDRPHY_DX3BDLR0_RESERVED_7_6_MASK (0xC0U)
25751#define DDRPHY_DX3BDLR0_RESERVED_7_6_SHIFT (6U)
25752/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
25753 */
25754#define DDRPHY_DX3BDLR0_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR0_RESERVED_7_6_MASK)
25755#define DDRPHY_DX3BDLR0_DQ1WBD_MASK (0x3F00U)
25756#define DDRPHY_DX3BDLR0_DQ1WBD_SHIFT (8U)
25757/*! DQ1WBD - DQ1 Write Bit Delay
25758 */
25759#define DDRPHY_DX3BDLR0_DQ1WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX3BDLR0_DQ1WBD_MASK)
25760#define DDRPHY_DX3BDLR0_RESERVED_15_14_MASK (0xC000U)
25761#define DDRPHY_DX3BDLR0_RESERVED_15_14_SHIFT (14U)
25762/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
25763 */
25764#define DDRPHY_DX3BDLR0_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR0_RESERVED_15_14_MASK)
25765#define DDRPHY_DX3BDLR0_DQ2WBD_MASK (0x3F0000U)
25766#define DDRPHY_DX3BDLR0_DQ2WBD_SHIFT (16U)
25767/*! DQ2WBD - DQ2 Write Bit Delay
25768 */
25769#define DDRPHY_DX3BDLR0_DQ2WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX3BDLR0_DQ2WBD_MASK)
25770#define DDRPHY_DX3BDLR0_RESERVED_23_22_MASK (0xC00000U)
25771#define DDRPHY_DX3BDLR0_RESERVED_23_22_SHIFT (22U)
25772/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
25773 */
25774#define DDRPHY_DX3BDLR0_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX3BDLR0_RESERVED_23_22_MASK)
25775#define DDRPHY_DX3BDLR0_DQ3WBD_MASK (0x3F000000U)
25776#define DDRPHY_DX3BDLR0_DQ3WBD_SHIFT (24U)
25777/*! DQ3WBD - DQ3 Write Bit Delay
25778 */
25779#define DDRPHY_DX3BDLR0_DQ3WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX3BDLR0_DQ3WBD_MASK)
25780#define DDRPHY_DX3BDLR0_RESERVED_31_30_MASK (0xC0000000U)
25781#define DDRPHY_DX3BDLR0_RESERVED_31_30_SHIFT (30U)
25782/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
25783 */
25784#define DDRPHY_DX3BDLR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX3BDLR0_RESERVED_31_30_MASK)
25785/*! @} */
25786
25787/*! @name DX3BDLR1 - DATX8 n Bit Delay Line Register 1 */
25788/*! @{ */
25789#define DDRPHY_DX3BDLR1_DQ4WBD_MASK (0x3FU)
25790#define DDRPHY_DX3BDLR1_DQ4WBD_SHIFT (0U)
25791/*! DQ4WBD - DQ4 Write Bit Delay
25792 */
25793#define DDRPHY_DX3BDLR1_DQ4WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX3BDLR1_DQ4WBD_MASK)
25794#define DDRPHY_DX3BDLR1_RESERVED_7_6_MASK (0xC0U)
25795#define DDRPHY_DX3BDLR1_RESERVED_7_6_SHIFT (6U)
25796/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
25797 */
25798#define DDRPHY_DX3BDLR1_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR1_RESERVED_7_6_MASK)
25799#define DDRPHY_DX3BDLR1_DQ5WBD_MASK (0x3F00U)
25800#define DDRPHY_DX3BDLR1_DQ5WBD_SHIFT (8U)
25801/*! DQ5WBD - DQ5 Write Bit Delay
25802 */
25803#define DDRPHY_DX3BDLR1_DQ5WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX3BDLR1_DQ5WBD_MASK)
25804#define DDRPHY_DX3BDLR1_RESERVED_15_14_MASK (0xC000U)
25805#define DDRPHY_DX3BDLR1_RESERVED_15_14_SHIFT (14U)
25806/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
25807 */
25808#define DDRPHY_DX3BDLR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR1_RESERVED_15_14_MASK)
25809#define DDRPHY_DX3BDLR1_DQ6WBD_MASK (0x3F0000U)
25810#define DDRPHY_DX3BDLR1_DQ6WBD_SHIFT (16U)
25811/*! DQ6WBD - DQ6 Write Bit Delay
25812 */
25813#define DDRPHY_DX3BDLR1_DQ6WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX3BDLR1_DQ6WBD_MASK)
25814#define DDRPHY_DX3BDLR1_RESERVED_23_22_MASK (0xC00000U)
25815#define DDRPHY_DX3BDLR1_RESERVED_23_22_SHIFT (22U)
25816/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
25817 */
25818#define DDRPHY_DX3BDLR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX3BDLR1_RESERVED_23_22_MASK)
25819#define DDRPHY_DX3BDLR1_DQ7WBD_MASK (0x3F000000U)
25820#define DDRPHY_DX3BDLR1_DQ7WBD_SHIFT (24U)
25821/*! DQ7WBD - DQ7 Write Bit Delay
25822 */
25823#define DDRPHY_DX3BDLR1_DQ7WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX3BDLR1_DQ7WBD_MASK)
25824#define DDRPHY_DX3BDLR1_RESERVED_31_30_MASK (0xC0000000U)
25825#define DDRPHY_DX3BDLR1_RESERVED_31_30_SHIFT (30U)
25826/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
25827 */
25828#define DDRPHY_DX3BDLR1_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX3BDLR1_RESERVED_31_30_MASK)
25829/*! @} */
25830
25831/*! @name DX3BDLR2 - DATX8 n Bit Delay Line Register 2 */
25832/*! @{ */
25833#define DDRPHY_DX3BDLR2_DMWBD_MASK (0x3FU)
25834#define DDRPHY_DX3BDLR2_DMWBD_SHIFT (0U)
25835/*! DMWBD - DM Write Bit Delay
25836 */
25837#define DDRPHY_DX3BDLR2_DMWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_DMWBD_SHIFT)) & DDRPHY_DX3BDLR2_DMWBD_MASK)
25838#define DDRPHY_DX3BDLR2_RESERVED_7_6_MASK (0xC0U)
25839#define DDRPHY_DX3BDLR2_RESERVED_7_6_SHIFT (6U)
25840/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
25841 */
25842#define DDRPHY_DX3BDLR2_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR2_RESERVED_7_6_MASK)
25843#define DDRPHY_DX3BDLR2_DSWBD_MASK (0x3F00U)
25844#define DDRPHY_DX3BDLR2_DSWBD_SHIFT (8U)
25845/*! DSWBD - DQS Write Bit Delay
25846 */
25847#define DDRPHY_DX3BDLR2_DSWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_DSWBD_SHIFT)) & DDRPHY_DX3BDLR2_DSWBD_MASK)
25848#define DDRPHY_DX3BDLR2_RESERVED_15_14_MASK (0xC000U)
25849#define DDRPHY_DX3BDLR2_RESERVED_15_14_SHIFT (14U)
25850/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
25851 */
25852#define DDRPHY_DX3BDLR2_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR2_RESERVED_15_14_MASK)
25853#define DDRPHY_DX3BDLR2_DSOEBD_MASK (0x3F0000U)
25854#define DDRPHY_DX3BDLR2_DSOEBD_SHIFT (16U)
25855/*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay
25856 */
25857#define DDRPHY_DX3BDLR2_DSOEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX3BDLR2_DSOEBD_MASK)
25858#define DDRPHY_DX3BDLR2_RESERVED_23_22_MASK (0xC00000U)
25859#define DDRPHY_DX3BDLR2_RESERVED_23_22_SHIFT (22U)
25860/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
25861 */
25862#define DDRPHY_DX3BDLR2_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX3BDLR2_RESERVED_23_22_MASK)
25863#define DDRPHY_DX3BDLR2_DSNWBD_MASK (0x3F000000U)
25864#define DDRPHY_DX3BDLR2_DSNWBD_SHIFT (24U)
25865/*! DSNWBD - DQSN Write Bit Delay
25866 */
25867#define DDRPHY_DX3BDLR2_DSNWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX3BDLR2_DSNWBD_MASK)
25868#define DDRPHY_DX3BDLR2_RESERVED_31_30_MASK (0xC0000000U)
25869#define DDRPHY_DX3BDLR2_RESERVED_31_30_SHIFT (30U)
25870/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
25871 */
25872#define DDRPHY_DX3BDLR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX3BDLR2_RESERVED_31_30_MASK)
25873/*! @} */
25874
25875/*! @name DX3BDLR3 - DATX8 n Bit Delay Line Register 3 */
25876/*! @{ */
25877#define DDRPHY_DX3BDLR3_DQ0RBD_MASK (0x3FU)
25878#define DDRPHY_DX3BDLR3_DQ0RBD_SHIFT (0U)
25879/*! DQ0RBD - DQ0 Read Bit Delay
25880 */
25881#define DDRPHY_DX3BDLR3_DQ0RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX3BDLR3_DQ0RBD_MASK)
25882#define DDRPHY_DX3BDLR3_RESERVED_7_6_MASK (0xC0U)
25883#define DDRPHY_DX3BDLR3_RESERVED_7_6_SHIFT (6U)
25884/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
25885 */
25886#define DDRPHY_DX3BDLR3_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR3_RESERVED_7_6_MASK)
25887#define DDRPHY_DX3BDLR3_DQ1RBD_MASK (0x3F00U)
25888#define DDRPHY_DX3BDLR3_DQ1RBD_SHIFT (8U)
25889/*! DQ1RBD - DQ1 Read Bit Delay
25890 */
25891#define DDRPHY_DX3BDLR3_DQ1RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX3BDLR3_DQ1RBD_MASK)
25892#define DDRPHY_DX3BDLR3_RESERVED_15_14_MASK (0xC000U)
25893#define DDRPHY_DX3BDLR3_RESERVED_15_14_SHIFT (14U)
25894/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
25895 */
25896#define DDRPHY_DX3BDLR3_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR3_RESERVED_15_14_MASK)
25897#define DDRPHY_DX3BDLR3_DQ2RBD_MASK (0x3F0000U)
25898#define DDRPHY_DX3BDLR3_DQ2RBD_SHIFT (16U)
25899/*! DQ2RBD - DQ2 Read Bit Delay
25900 */
25901#define DDRPHY_DX3BDLR3_DQ2RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX3BDLR3_DQ2RBD_MASK)
25902#define DDRPHY_DX3BDLR3_RESERVED_23_22_MASK (0xC00000U)
25903#define DDRPHY_DX3BDLR3_RESERVED_23_22_SHIFT (22U)
25904/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
25905 */
25906#define DDRPHY_DX3BDLR3_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX3BDLR3_RESERVED_23_22_MASK)
25907#define DDRPHY_DX3BDLR3_DQ3RBD_MASK (0x3F000000U)
25908#define DDRPHY_DX3BDLR3_DQ3RBD_SHIFT (24U)
25909/*! DQ3RBD - DQ3 Read Bit Delay
25910 */
25911#define DDRPHY_DX3BDLR3_DQ3RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX3BDLR3_DQ3RBD_MASK)
25912#define DDRPHY_DX3BDLR3_RESERVED_31_30_MASK (0xC0000000U)
25913#define DDRPHY_DX3BDLR3_RESERVED_31_30_SHIFT (30U)
25914/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
25915 */
25916#define DDRPHY_DX3BDLR3_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX3BDLR3_RESERVED_31_30_MASK)
25917/*! @} */
25918
25919/*! @name DX3BDLR4 - DATX8 n Bit Delay Line Register 4 */
25920/*! @{ */
25921#define DDRPHY_DX3BDLR4_DQ4RBD_MASK (0x3FU)
25922#define DDRPHY_DX3BDLR4_DQ4RBD_SHIFT (0U)
25923/*! DQ4RBD - DQ4 Read Bit Delay
25924 */
25925#define DDRPHY_DX3BDLR4_DQ4RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX3BDLR4_DQ4RBD_MASK)
25926#define DDRPHY_DX3BDLR4_RESERVED_7_6_MASK (0xC0U)
25927#define DDRPHY_DX3BDLR4_RESERVED_7_6_SHIFT (6U)
25928/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
25929 */
25930#define DDRPHY_DX3BDLR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR4_RESERVED_7_6_MASK)
25931#define DDRPHY_DX3BDLR4_DQ5RBD_MASK (0x3F00U)
25932#define DDRPHY_DX3BDLR4_DQ5RBD_SHIFT (8U)
25933/*! DQ5RBD - DQ5 Read Bit Delay
25934 */
25935#define DDRPHY_DX3BDLR4_DQ5RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX3BDLR4_DQ5RBD_MASK)
25936#define DDRPHY_DX3BDLR4_RESERVED_15_14_MASK (0xC000U)
25937#define DDRPHY_DX3BDLR4_RESERVED_15_14_SHIFT (14U)
25938/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
25939 */
25940#define DDRPHY_DX3BDLR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR4_RESERVED_15_14_MASK)
25941#define DDRPHY_DX3BDLR4_DQ6RBD_MASK (0x3F0000U)
25942#define DDRPHY_DX3BDLR4_DQ6RBD_SHIFT (16U)
25943/*! DQ6RBD - DQ6 Read Bit Delay
25944 */
25945#define DDRPHY_DX3BDLR4_DQ6RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX3BDLR4_DQ6RBD_MASK)
25946#define DDRPHY_DX3BDLR4_RESERVED_23_22_MASK (0xC00000U)
25947#define DDRPHY_DX3BDLR4_RESERVED_23_22_SHIFT (22U)
25948/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
25949 */
25950#define DDRPHY_DX3BDLR4_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX3BDLR4_RESERVED_23_22_MASK)
25951#define DDRPHY_DX3BDLR4_DQ7RBD_MASK (0x3F000000U)
25952#define DDRPHY_DX3BDLR4_DQ7RBD_SHIFT (24U)
25953/*! DQ7RBD - DQ7 Read Bit Delay
25954 */
25955#define DDRPHY_DX3BDLR4_DQ7RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX3BDLR4_DQ7RBD_MASK)
25956#define DDRPHY_DX3BDLR4_RESERVED_31_30_MASK (0xC0000000U)
25957#define DDRPHY_DX3BDLR4_RESERVED_31_30_SHIFT (30U)
25958/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
25959 */
25960#define DDRPHY_DX3BDLR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX3BDLR4_RESERVED_31_30_MASK)
25961/*! @} */
25962
25963/*! @name DX3BDLR5 - DATX8 n Bit Delay Line Register 5 */
25964/*! @{ */
25965#define DDRPHY_DX3BDLR5_DMRBD_MASK (0x3FU)
25966#define DDRPHY_DX3BDLR5_DMRBD_SHIFT (0U)
25967/*! DMRBD - DM Read Bit Delay
25968 */
25969#define DDRPHY_DX3BDLR5_DMRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR5_DMRBD_SHIFT)) & DDRPHY_DX3BDLR5_DMRBD_MASK)
25970#define DDRPHY_DX3BDLR5_RESERVED_31_6_MASK (0xFFFFFFC0U)
25971#define DDRPHY_DX3BDLR5_RESERVED_31_6_SHIFT (6U)
25972/*! RESERVED_31_6 - Reserved. Return zeroes on reads.
25973 */
25974#define DDRPHY_DX3BDLR5_RESERVED_31_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX3BDLR5_RESERVED_31_6_MASK)
25975/*! @} */
25976
25977/*! @name DX3BDLR6 - DATX8 n Bit Delay Line Register 6 */
25978/*! @{ */
25979#define DDRPHY_DX3BDLR6_RESERVED_7_0_MASK (0xFFU)
25980#define DDRPHY_DX3BDLR6_RESERVED_7_0_SHIFT (0U)
25981/*! RESERVED_7_0 - Reserved. Return zeroes on reads.
25982 */
25983#define DDRPHY_DX3BDLR6_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX3BDLR6_RESERVED_7_0_MASK)
25984#define DDRPHY_DX3BDLR6_PDRBD_MASK (0x3F00U)
25985#define DDRPHY_DX3BDLR6_PDRBD_SHIFT (8U)
25986/*! PDRBD - Power down receiver Bit Delay
25987 */
25988#define DDRPHY_DX3BDLR6_PDRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR6_PDRBD_SHIFT)) & DDRPHY_DX3BDLR6_PDRBD_MASK)
25989#define DDRPHY_DX3BDLR6_RESERVED_15_14_MASK (0xC000U)
25990#define DDRPHY_DX3BDLR6_RESERVED_15_14_SHIFT (14U)
25991/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
25992 */
25993#define DDRPHY_DX3BDLR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR6_RESERVED_15_14_MASK)
25994#define DDRPHY_DX3BDLR6_TERBD_MASK (0x3F0000U)
25995#define DDRPHY_DX3BDLR6_TERBD_SHIFT (16U)
25996/*! TERBD - Termination Enable Bit Delay
25997 */
25998#define DDRPHY_DX3BDLR6_TERBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR6_TERBD_SHIFT)) & DDRPHY_DX3BDLR6_TERBD_MASK)
25999#define DDRPHY_DX3BDLR6_RESERVED_31_22_MASK (0xFFC00000U)
26000#define DDRPHY_DX3BDLR6_RESERVED_31_22_SHIFT (22U)
26001/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
26002 */
26003#define DDRPHY_DX3BDLR6_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX3BDLR6_RESERVED_31_22_MASK)
26004/*! @} */
26005
26006/*! @name DX3BDLR7 - DATX8 n Bit Delay Line Register 7 */
26007/*! @{ */
26008#define DDRPHY_DX3BDLR7_RESERVED_5_0_MASK (0x3FU)
26009#define DDRPHY_DX3BDLR7_RESERVED_5_0_SHIFT (0U)
26010/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
26011 */
26012#define DDRPHY_DX3BDLR7_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX3BDLR7_RESERVED_5_0_MASK)
26013#define DDRPHY_DX3BDLR7_RESERVED_7_6_MASK (0xC0U)
26014#define DDRPHY_DX3BDLR7_RESERVED_7_6_SHIFT (6U)
26015/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
26016 */
26017#define DDRPHY_DX3BDLR7_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR7_RESERVED_7_6_MASK)
26018#define DDRPHY_DX3BDLR7_RESERVED_13_8_MASK (0x3F00U)
26019#define DDRPHY_DX3BDLR7_RESERVED_13_8_SHIFT (8U)
26020/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
26021 */
26022#define DDRPHY_DX3BDLR7_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX3BDLR7_RESERVED_13_8_MASK)
26023#define DDRPHY_DX3BDLR7_RESERVED_15_14_MASK (0xC000U)
26024#define DDRPHY_DX3BDLR7_RESERVED_15_14_SHIFT (14U)
26025/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
26026 */
26027#define DDRPHY_DX3BDLR7_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR7_RESERVED_15_14_MASK)
26028#define DDRPHY_DX3BDLR7_RESERVED_21_16_MASK (0x3F0000U)
26029#define DDRPHY_DX3BDLR7_RESERVED_21_16_SHIFT (16U)
26030/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
26031 */
26032#define DDRPHY_DX3BDLR7_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX3BDLR7_RESERVED_21_16_MASK)
26033#define DDRPHY_DX3BDLR7_RESERVED_31_22_MASK (0xFFC00000U)
26034#define DDRPHY_DX3BDLR7_RESERVED_31_22_SHIFT (22U)
26035/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
26036 */
26037#define DDRPHY_DX3BDLR7_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX3BDLR7_RESERVED_31_22_MASK)
26038/*! @} */
26039
26040/*! @name DX3BDLR8 - DATX8 n Bit Delay Line Register 8 */
26041/*! @{ */
26042#define DDRPHY_DX3BDLR8_RESERVED_5_0_MASK (0x3FU)
26043#define DDRPHY_DX3BDLR8_RESERVED_5_0_SHIFT (0U)
26044/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
26045 */
26046#define DDRPHY_DX3BDLR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX3BDLR8_RESERVED_5_0_MASK)
26047#define DDRPHY_DX3BDLR8_RESERVED_7_6_MASK (0xC0U)
26048#define DDRPHY_DX3BDLR8_RESERVED_7_6_SHIFT (6U)
26049/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
26050 */
26051#define DDRPHY_DX3BDLR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR8_RESERVED_7_6_MASK)
26052#define DDRPHY_DX3BDLR8_RESERVED_13_8_MASK (0x3F00U)
26053#define DDRPHY_DX3BDLR8_RESERVED_13_8_SHIFT (8U)
26054/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
26055 */
26056#define DDRPHY_DX3BDLR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX3BDLR8_RESERVED_13_8_MASK)
26057#define DDRPHY_DX3BDLR8_RESERVED_15_14_MASK (0xC000U)
26058#define DDRPHY_DX3BDLR8_RESERVED_15_14_SHIFT (14U)
26059/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
26060 */
26061#define DDRPHY_DX3BDLR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR8_RESERVED_15_14_MASK)
26062#define DDRPHY_DX3BDLR8_RESERVED_21_16_MASK (0x3F0000U)
26063#define DDRPHY_DX3BDLR8_RESERVED_21_16_SHIFT (16U)
26064/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
26065 */
26066#define DDRPHY_DX3BDLR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX3BDLR8_RESERVED_21_16_MASK)
26067#define DDRPHY_DX3BDLR8_RESERVED_31_22_MASK (0xFFC00000U)
26068#define DDRPHY_DX3BDLR8_RESERVED_31_22_SHIFT (22U)
26069/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
26070 */
26071#define DDRPHY_DX3BDLR8_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX3BDLR8_RESERVED_31_22_MASK)
26072/*! @} */
26073
26074/*! @name DX3BDLR9 - DATX8 n Bit Delay Line Register 9 */
26075/*! @{ */
26076#define DDRPHY_DX3BDLR9_RESERVED_5_0_MASK (0x3FU)
26077#define DDRPHY_DX3BDLR9_RESERVED_5_0_SHIFT (0U)
26078/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
26079 */
26080#define DDRPHY_DX3BDLR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX3BDLR9_RESERVED_5_0_MASK)
26081#define DDRPHY_DX3BDLR9_RESERVED_7_6_MASK (0xC0U)
26082#define DDRPHY_DX3BDLR9_RESERVED_7_6_SHIFT (6U)
26083/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
26084 */
26085#define DDRPHY_DX3BDLR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX3BDLR9_RESERVED_7_6_MASK)
26086#define DDRPHY_DX3BDLR9_RESERVED_13_8_MASK (0x3F00U)
26087#define DDRPHY_DX3BDLR9_RESERVED_13_8_SHIFT (8U)
26088/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
26089 */
26090#define DDRPHY_DX3BDLR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX3BDLR9_RESERVED_13_8_MASK)
26091#define DDRPHY_DX3BDLR9_RESERVED_15_14_MASK (0xC000U)
26092#define DDRPHY_DX3BDLR9_RESERVED_15_14_SHIFT (14U)
26093/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
26094 */
26095#define DDRPHY_DX3BDLR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX3BDLR9_RESERVED_15_14_MASK)
26096#define DDRPHY_DX3BDLR9_RESERVED_21_16_MASK (0x3F0000U)
26097#define DDRPHY_DX3BDLR9_RESERVED_21_16_SHIFT (16U)
26098/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
26099 */
26100#define DDRPHY_DX3BDLR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX3BDLR9_RESERVED_21_16_MASK)
26101#define DDRPHY_DX3BDLR9_RESERVED_31_22_MASK (0xFFC00000U)
26102#define DDRPHY_DX3BDLR9_RESERVED_31_22_SHIFT (22U)
26103/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
26104 */
26105#define DDRPHY_DX3BDLR9_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX3BDLR9_RESERVED_31_22_MASK)
26106/*! @} */
26107
26108/*! @name DX3LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */
26109/*! @{ */
26110#define DDRPHY_DX3LCDLR0_WLD_MASK (0x1FFU)
26111#define DDRPHY_DX3LCDLR0_WLD_SHIFT (0U)
26112/*! WLD - Write Leveling Delay
26113 */
26114#define DDRPHY_DX3LCDLR0_WLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR0_WLD_SHIFT)) & DDRPHY_DX3LCDLR0_WLD_MASK)
26115#define DDRPHY_DX3LCDLR0_RESERVED_15_9_MASK (0xFE00U)
26116#define DDRPHY_DX3LCDLR0_RESERVED_15_9_SHIFT (9U)
26117/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
26118 */
26119#define DDRPHY_DX3LCDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX3LCDLR0_RESERVED_15_9_MASK)
26120#define DDRPHY_DX3LCDLR0_RESERVED_24_16_MASK (0x1FF0000U)
26121#define DDRPHY_DX3LCDLR0_RESERVED_24_16_SHIFT (16U)
26122/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
26123 */
26124#define DDRPHY_DX3LCDLR0_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX3LCDLR0_RESERVED_24_16_MASK)
26125#define DDRPHY_DX3LCDLR0_RESERVED_31_25_MASK (0xFE000000U)
26126#define DDRPHY_DX3LCDLR0_RESERVED_31_25_SHIFT (25U)
26127/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
26128 */
26129#define DDRPHY_DX3LCDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX3LCDLR0_RESERVED_31_25_MASK)
26130/*! @} */
26131
26132/*! @name DX3LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */
26133/*! @{ */
26134#define DDRPHY_DX3LCDLR1_WDQD_MASK (0x1FFU)
26135#define DDRPHY_DX3LCDLR1_WDQD_SHIFT (0U)
26136/*! WDQD - Write Data Delay
26137 */
26138#define DDRPHY_DX3LCDLR1_WDQD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR1_WDQD_SHIFT)) & DDRPHY_DX3LCDLR1_WDQD_MASK)
26139#define DDRPHY_DX3LCDLR1_RESERVED_15_9_MASK (0xFE00U)
26140#define DDRPHY_DX3LCDLR1_RESERVED_15_9_SHIFT (9U)
26141/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
26142 */
26143#define DDRPHY_DX3LCDLR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX3LCDLR1_RESERVED_15_9_MASK)
26144#define DDRPHY_DX3LCDLR1_RESERVED_24_16_MASK (0x1FF0000U)
26145#define DDRPHY_DX3LCDLR1_RESERVED_24_16_SHIFT (16U)
26146/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
26147 */
26148#define DDRPHY_DX3LCDLR1_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX3LCDLR1_RESERVED_24_16_MASK)
26149#define DDRPHY_DX3LCDLR1_RESERVED_31_25_MASK (0xFE000000U)
26150#define DDRPHY_DX3LCDLR1_RESERVED_31_25_SHIFT (25U)
26151/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
26152 */
26153#define DDRPHY_DX3LCDLR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX3LCDLR1_RESERVED_31_25_MASK)
26154/*! @} */
26155
26156/*! @name DX3LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */
26157/*! @{ */
26158#define DDRPHY_DX3LCDLR2_DQSGD_MASK (0x1FFU)
26159#define DDRPHY_DX3LCDLR2_DQSGD_SHIFT (0U)
26160/*! DQSGD - Read DQS Gating Delay
26161 */
26162#define DDRPHY_DX3LCDLR2_DQSGD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX3LCDLR2_DQSGD_MASK)
26163#define DDRPHY_DX3LCDLR2_RESERVED_15_9_MASK (0xFE00U)
26164#define DDRPHY_DX3LCDLR2_RESERVED_15_9_SHIFT (9U)
26165/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
26166 */
26167#define DDRPHY_DX3LCDLR2_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX3LCDLR2_RESERVED_15_9_MASK)
26168#define DDRPHY_DX3LCDLR2_RESERVED_24_16_MASK (0x1FF0000U)
26169#define DDRPHY_DX3LCDLR2_RESERVED_24_16_SHIFT (16U)
26170/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
26171 */
26172#define DDRPHY_DX3LCDLR2_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX3LCDLR2_RESERVED_24_16_MASK)
26173#define DDRPHY_DX3LCDLR2_RESERVED_31_25_MASK (0xFE000000U)
26174#define DDRPHY_DX3LCDLR2_RESERVED_31_25_SHIFT (25U)
26175/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
26176 */
26177#define DDRPHY_DX3LCDLR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX3LCDLR2_RESERVED_31_25_MASK)
26178/*! @} */
26179
26180/*! @name DX3LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */
26181/*! @{ */
26182#define DDRPHY_DX3LCDLR3_RDQSD_MASK (0x1FFU)
26183#define DDRPHY_DX3LCDLR3_RDQSD_SHIFT (0U)
26184/*! RDQSD - Read DQS Delay
26185 */
26186#define DDRPHY_DX3LCDLR3_RDQSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX3LCDLR3_RDQSD_MASK)
26187#define DDRPHY_DX3LCDLR3_RESERVED_15_9_MASK (0xFE00U)
26188#define DDRPHY_DX3LCDLR3_RESERVED_15_9_SHIFT (9U)
26189/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
26190 */
26191#define DDRPHY_DX3LCDLR3_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX3LCDLR3_RESERVED_15_9_MASK)
26192#define DDRPHY_DX3LCDLR3_RESERVED_24_16_MASK (0x1FF0000U)
26193#define DDRPHY_DX3LCDLR3_RESERVED_24_16_SHIFT (16U)
26194/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
26195 */
26196#define DDRPHY_DX3LCDLR3_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX3LCDLR3_RESERVED_24_16_MASK)
26197#define DDRPHY_DX3LCDLR3_RESERVED_31_25_MASK (0xFE000000U)
26198#define DDRPHY_DX3LCDLR3_RESERVED_31_25_SHIFT (25U)
26199/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
26200 */
26201#define DDRPHY_DX3LCDLR3_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX3LCDLR3_RESERVED_31_25_MASK)
26202/*! @} */
26203
26204/*! @name DX3LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */
26205/*! @{ */
26206#define DDRPHY_DX3LCDLR4_RDQSND_MASK (0x1FFU)
26207#define DDRPHY_DX3LCDLR4_RDQSND_SHIFT (0U)
26208/*! RDQSND - Read DQSN Delay
26209 */
26210#define DDRPHY_DX3LCDLR4_RDQSND(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX3LCDLR4_RDQSND_MASK)
26211#define DDRPHY_DX3LCDLR4_RESERVED_15_9_MASK (0xFE00U)
26212#define DDRPHY_DX3LCDLR4_RESERVED_15_9_SHIFT (9U)
26213/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
26214 */
26215#define DDRPHY_DX3LCDLR4_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX3LCDLR4_RESERVED_15_9_MASK)
26216#define DDRPHY_DX3LCDLR4_RESERVED_24_16_MASK (0x1FF0000U)
26217#define DDRPHY_DX3LCDLR4_RESERVED_24_16_SHIFT (16U)
26218/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
26219 */
26220#define DDRPHY_DX3LCDLR4_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX3LCDLR4_RESERVED_24_16_MASK)
26221#define DDRPHY_DX3LCDLR4_RESERVED_31_25_MASK (0xFE000000U)
26222#define DDRPHY_DX3LCDLR4_RESERVED_31_25_SHIFT (25U)
26223/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
26224 */
26225#define DDRPHY_DX3LCDLR4_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX3LCDLR4_RESERVED_31_25_MASK)
26226/*! @} */
26227
26228/*! @name DX3LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */
26229/*! @{ */
26230#define DDRPHY_DX3LCDLR5_DQSGSD_MASK (0x1FFU)
26231#define DDRPHY_DX3LCDLR5_DQSGSD_SHIFT (0U)
26232/*! DQSGSD - DQS Gating Status Delay
26233 */
26234#define DDRPHY_DX3LCDLR5_DQSGSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX3LCDLR5_DQSGSD_MASK)
26235#define DDRPHY_DX3LCDLR5_RESERVED_15_9_MASK (0xFE00U)
26236#define DDRPHY_DX3LCDLR5_RESERVED_15_9_SHIFT (9U)
26237/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
26238 */
26239#define DDRPHY_DX3LCDLR5_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX3LCDLR5_RESERVED_15_9_MASK)
26240#define DDRPHY_DX3LCDLR5_RESERVED_24_16_MASK (0x1FF0000U)
26241#define DDRPHY_DX3LCDLR5_RESERVED_24_16_SHIFT (16U)
26242/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
26243 */
26244#define DDRPHY_DX3LCDLR5_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX3LCDLR5_RESERVED_24_16_MASK)
26245#define DDRPHY_DX3LCDLR5_RESERVED_31_25_MASK (0xFE000000U)
26246#define DDRPHY_DX3LCDLR5_RESERVED_31_25_SHIFT (25U)
26247/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
26248 */
26249#define DDRPHY_DX3LCDLR5_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX3LCDLR5_RESERVED_31_25_MASK)
26250/*! @} */
26251
26252/*! @name DX3MDLR0 - DATX8 n Master Delay Line Register 0 */
26253/*! @{ */
26254#define DDRPHY_DX3MDLR0_IPRD_MASK (0x1FFU)
26255#define DDRPHY_DX3MDLR0_IPRD_SHIFT (0U)
26256/*! IPRD - Initial Period
26257 */
26258#define DDRPHY_DX3MDLR0_IPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3MDLR0_IPRD_SHIFT)) & DDRPHY_DX3MDLR0_IPRD_MASK)
26259#define DDRPHY_DX3MDLR0_RESERVED_15_9_MASK (0xFE00U)
26260#define DDRPHY_DX3MDLR0_RESERVED_15_9_SHIFT (9U)
26261/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
26262 */
26263#define DDRPHY_DX3MDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX3MDLR0_RESERVED_15_9_MASK)
26264#define DDRPHY_DX3MDLR0_TPRD_MASK (0x1FF0000U)
26265#define DDRPHY_DX3MDLR0_TPRD_SHIFT (16U)
26266/*! TPRD - Target Period
26267 */
26268#define DDRPHY_DX3MDLR0_TPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3MDLR0_TPRD_SHIFT)) & DDRPHY_DX3MDLR0_TPRD_MASK)
26269#define DDRPHY_DX3MDLR0_RESERVED_31_25_MASK (0xFE000000U)
26270#define DDRPHY_DX3MDLR0_RESERVED_31_25_SHIFT (25U)
26271/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
26272 */
26273#define DDRPHY_DX3MDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX3MDLR0_RESERVED_31_25_MASK)
26274/*! @} */
26275
26276/*! @name DX3MDLR1 - DATX8 n Master Delay Line Register 1 */
26277/*! @{ */
26278#define DDRPHY_DX3MDLR1_MDLD_MASK (0x1FFU)
26279#define DDRPHY_DX3MDLR1_MDLD_SHIFT (0U)
26280/*! MDLD - MDL Delay
26281 */
26282#define DDRPHY_DX3MDLR1_MDLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3MDLR1_MDLD_SHIFT)) & DDRPHY_DX3MDLR1_MDLD_MASK)
26283#define DDRPHY_DX3MDLR1_RESERVED_31_9_MASK (0xFFFFFE00U)
26284#define DDRPHY_DX3MDLR1_RESERVED_31_9_SHIFT (9U)
26285/*! RESERVED_31_9 - Reserved. Return zeroes on reads.
26286 */
26287#define DDRPHY_DX3MDLR1_RESERVED_31_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX3MDLR1_RESERVED_31_9_MASK)
26288/*! @} */
26289
26290/*! @name DX3GTR0 - DATX8 n General Timing Register 0 */
26291/*! @{ */
26292#define DDRPHY_DX3GTR0_DGSL_MASK (0x1FU)
26293#define DDRPHY_DX3GTR0_DGSL_SHIFT (0U)
26294/*! DGSL - DQS Gating System Latency
26295 */
26296#define DDRPHY_DX3GTR0_DGSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_DGSL_SHIFT)) & DDRPHY_DX3GTR0_DGSL_MASK)
26297#define DDRPHY_DX3GTR0_RESERVED_7_5_MASK (0xE0U)
26298#define DDRPHY_DX3GTR0_RESERVED_7_5_SHIFT (5U)
26299/*! RESERVED_7_5 - Reserved. Return zeroes on reads.
26300 */
26301#define DDRPHY_DX3GTR0_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX3GTR0_RESERVED_7_5_MASK)
26302#define DDRPHY_DX3GTR0_RESERVED_12_8_MASK (0x1F00U)
26303#define DDRPHY_DX3GTR0_RESERVED_12_8_SHIFT (8U)
26304/*! RESERVED_12_8 - Reserved. Caution, do not write to this register field.
26305 */
26306#define DDRPHY_DX3GTR0_RESERVED_12_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX3GTR0_RESERVED_12_8_MASK)
26307#define DDRPHY_DX3GTR0_RESERVED_15_13_MASK (0xE000U)
26308#define DDRPHY_DX3GTR0_RESERVED_15_13_SHIFT (13U)
26309/*! RESERVED_15_13 - Reserved. Return zeroes on reads.
26310 */
26311#define DDRPHY_DX3GTR0_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX3GTR0_RESERVED_15_13_MASK)
26312#define DDRPHY_DX3GTR0_WLSL_MASK (0xF0000U)
26313#define DDRPHY_DX3GTR0_WLSL_SHIFT (16U)
26314/*! WLSL - Write Leveling System Latency
26315 */
26316#define DDRPHY_DX3GTR0_WLSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_WLSL_SHIFT)) & DDRPHY_DX3GTR0_WLSL_MASK)
26317#define DDRPHY_DX3GTR0_RESERVED_23_20_MASK (0xF00000U)
26318#define DDRPHY_DX3GTR0_RESERVED_23_20_SHIFT (20U)
26319/*! RESERVED_23_20 - Reserved. Caution, do not write to this register field.
26320 */
26321#define DDRPHY_DX3GTR0_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX3GTR0_RESERVED_23_20_MASK)
26322#define DDRPHY_DX3GTR0_WDQSL_MASK (0x7000000U)
26323#define DDRPHY_DX3GTR0_WDQSL_SHIFT (24U)
26324/*! WDQSL - DQ Write Path Latency Pipeline
26325 */
26326#define DDRPHY_DX3GTR0_WDQSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_WDQSL_SHIFT)) & DDRPHY_DX3GTR0_WDQSL_MASK)
26327#define DDRPHY_DX3GTR0_RESERVED_31_24_MASK (0xF8000000U)
26328#define DDRPHY_DX3GTR0_RESERVED_31_24_SHIFT (27U)
26329/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
26330 */
26331#define DDRPHY_DX3GTR0_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX3GTR0_RESERVED_31_24_MASK)
26332/*! @} */
26333
26334/*! @name DX3RSR0 - DATX8 n Rank Status Register 0 */
26335/*! @{ */
26336#define DDRPHY_DX3RSR0_QSGERR_MASK (0xFFFFU)
26337#define DDRPHY_DX3RSR0_QSGERR_SHIFT (0U)
26338/*! QSGERR - DQS Gate Training Error
26339 */
26340#define DDRPHY_DX3RSR0_QSGERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR0_QSGERR_SHIFT)) & DDRPHY_DX3RSR0_QSGERR_MASK)
26341#define DDRPHY_DX3RSR0_RESERVED_31_16_MASK (0xFFFF0000U)
26342#define DDRPHY_DX3RSR0_RESERVED_31_16_SHIFT (16U)
26343/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
26344 */
26345#define DDRPHY_DX3RSR0_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX3RSR0_RESERVED_31_16_MASK)
26346/*! @} */
26347
26348/*! @name DX3RSR1 - DATX8 n Rank Status Register 1 */
26349/*! @{ */
26350#define DDRPHY_DX3RSR1_RDLVLERR_MASK (0xFFFFU)
26351#define DDRPHY_DX3RSR1_RDLVLERR_SHIFT (0U)
26352/*! RDLVLERR - Read Leveling Error
26353 */
26354#define DDRPHY_DX3RSR1_RDLVLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX3RSR1_RDLVLERR_MASK)
26355#define DDRPHY_DX3RSR1_RESERVED_31_16_MASK (0xFFFF0000U)
26356#define DDRPHY_DX3RSR1_RESERVED_31_16_SHIFT (16U)
26357/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
26358 */
26359#define DDRPHY_DX3RSR1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX3RSR1_RESERVED_31_16_MASK)
26360/*! @} */
26361
26362/*! @name DX3RSR2 - DATX8 n Rank Status Register 2 */
26363/*! @{ */
26364#define DDRPHY_DX3RSR2_WLAWN_MASK (0xFFFFU)
26365#define DDRPHY_DX3RSR2_WLAWN_SHIFT (0U)
26366/*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning
26367 */
26368#define DDRPHY_DX3RSR2_WLAWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR2_WLAWN_SHIFT)) & DDRPHY_DX3RSR2_WLAWN_MASK)
26369#define DDRPHY_DX3RSR2_RESERVED_31_16_MASK (0xFFFF0000U)
26370#define DDRPHY_DX3RSR2_RESERVED_31_16_SHIFT (16U)
26371/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
26372 */
26373#define DDRPHY_DX3RSR2_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX3RSR2_RESERVED_31_16_MASK)
26374/*! @} */
26375
26376/*! @name DX3RSR3 - DATX8 n Rank Status Register 3 */
26377/*! @{ */
26378#define DDRPHY_DX3RSR3_WLAERR_MASK (0xFFFFU)
26379#define DDRPHY_DX3RSR3_WLAERR_SHIFT (0U)
26380/*! WLAERR - Write Leveling Adjustment Error
26381 */
26382#define DDRPHY_DX3RSR3_WLAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR3_WLAERR_SHIFT)) & DDRPHY_DX3RSR3_WLAERR_MASK)
26383#define DDRPHY_DX3RSR3_RESERVED_31_16_MASK (0xFFFF0000U)
26384#define DDRPHY_DX3RSR3_RESERVED_31_16_SHIFT (16U)
26385/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
26386 */
26387#define DDRPHY_DX3RSR3_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX3RSR3_RESERVED_31_16_MASK)
26388/*! @} */
26389
26390/*! @name DX3GSR0 - DATX8 n General Status Register 0 */
26391/*! @{ */
26392#define DDRPHY_DX3GSR0_WDQCAL_MASK (0x1U)
26393#define DDRPHY_DX3GSR0_WDQCAL_SHIFT (0U)
26394/*! WDQCAL - Write DQ Calibration
26395 */
26396#define DDRPHY_DX3GSR0_WDQCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_WDQCAL_SHIFT)) & DDRPHY_DX3GSR0_WDQCAL_MASK)
26397#define DDRPHY_DX3GSR0_RDQSCAL_MASK (0x2U)
26398#define DDRPHY_DX3GSR0_RDQSCAL_SHIFT (1U)
26399/*! RDQSCAL - Read DQS Calibration
26400 */
26401#define DDRPHY_DX3GSR0_RDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX3GSR0_RDQSCAL_MASK)
26402#define DDRPHY_DX3GSR0_RDQSNCAL_MASK (0x4U)
26403#define DDRPHY_DX3GSR0_RDQSNCAL_SHIFT (2U)
26404/*! RDQSNCAL - Read DQS# Calibration
26405 */
26406#define DDRPHY_DX3GSR0_RDQSNCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX3GSR0_RDQSNCAL_MASK)
26407#define DDRPHY_DX3GSR0_GDQSCAL_MASK (0x8U)
26408#define DDRPHY_DX3GSR0_GDQSCAL_SHIFT (3U)
26409/*! GDQSCAL - Read DQS gating Calibration
26410 */
26411#define DDRPHY_DX3GSR0_GDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX3GSR0_GDQSCAL_MASK)
26412#define DDRPHY_DX3GSR0_WLCAL_MASK (0x10U)
26413#define DDRPHY_DX3GSR0_WLCAL_SHIFT (4U)
26414/*! WLCAL - Write Leveling Calibration
26415 */
26416#define DDRPHY_DX3GSR0_WLCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_WLCAL_SHIFT)) & DDRPHY_DX3GSR0_WLCAL_MASK)
26417#define DDRPHY_DX3GSR0_WLDONE_MASK (0x20U)
26418#define DDRPHY_DX3GSR0_WLDONE_SHIFT (5U)
26419/*! WLDONE - Write Leveling Done
26420 */
26421#define DDRPHY_DX3GSR0_WLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_WLDONE_SHIFT)) & DDRPHY_DX3GSR0_WLDONE_MASK)
26422#define DDRPHY_DX3GSR0_WLERR_MASK (0x40U)
26423#define DDRPHY_DX3GSR0_WLERR_SHIFT (6U)
26424/*! WLERR - Write Leveling Error
26425 */
26426#define DDRPHY_DX3GSR0_WLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_WLERR_SHIFT)) & DDRPHY_DX3GSR0_WLERR_MASK)
26427#define DDRPHY_DX3GSR0_WLPRD_MASK (0xFF80U)
26428#define DDRPHY_DX3GSR0_WLPRD_SHIFT (7U)
26429/*! WLPRD - Write Leveling Period
26430 */
26431#define DDRPHY_DX3GSR0_WLPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_WLPRD_SHIFT)) & DDRPHY_DX3GSR0_WLPRD_MASK)
26432#define DDRPHY_DX3GSR0_DPLOCK_MASK (0x10000U)
26433#define DDRPHY_DX3GSR0_DPLOCK_SHIFT (16U)
26434/*! DPLOCK - DATX8 PLL Lock
26435 */
26436#define DDRPHY_DX3GSR0_DPLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_DPLOCK_SHIFT)) & DDRPHY_DX3GSR0_DPLOCK_MASK)
26437#define DDRPHY_DX3GSR0_GDQSPRD_MASK (0x3FE0000U)
26438#define DDRPHY_DX3GSR0_GDQSPRD_SHIFT (17U)
26439/*! GDQSPRD - Read DQS gating Period
26440 */
26441#define DDRPHY_DX3GSR0_GDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX3GSR0_GDQSPRD_MASK)
26442#define DDRPHY_DX3GSR0_RESERVED_29_26_MASK (0x3C000000U)
26443#define DDRPHY_DX3GSR0_RESERVED_29_26_SHIFT (26U)
26444/*! RESERVED_29_26 - Reserved. Returns zeroes on reads.
26445 */
26446#define DDRPHY_DX3GSR0_RESERVED_29_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX3GSR0_RESERVED_29_26_MASK)
26447#define DDRPHY_DX3GSR0_WLDQ_MASK (0x40000000U)
26448#define DDRPHY_DX3GSR0_WLDQ_SHIFT (30U)
26449/*! WLDQ - Write Leveling DQ Status
26450 */
26451#define DDRPHY_DX3GSR0_WLDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_WLDQ_SHIFT)) & DDRPHY_DX3GSR0_WLDQ_MASK)
26452#define DDRPHY_DX3GSR0_RESERVED_31_MASK (0x80000000U)
26453#define DDRPHY_DX3GSR0_RESERVED_31_SHIFT (31U)
26454/*! RESERVED_31 - Reserved. Returns zeroes on reads.
26455 */
26456#define DDRPHY_DX3GSR0_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX3GSR0_RESERVED_31_MASK)
26457/*! @} */
26458
26459/*! @name DX3GSR1 - DATX8 n General Status Register 1 */
26460/*! @{ */
26461#define DDRPHY_DX3GSR1_DLTDONE_MASK (0x1U)
26462#define DDRPHY_DX3GSR1_DLTDONE_SHIFT (0U)
26463/*! DLTDONE - Delay Line Test Done
26464 */
26465#define DDRPHY_DX3GSR1_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR1_DLTDONE_SHIFT)) & DDRPHY_DX3GSR1_DLTDONE_MASK)
26466#define DDRPHY_DX3GSR1_DLTCODE_MASK (0x1FFFFFEU)
26467#define DDRPHY_DX3GSR1_DLTCODE_SHIFT (1U)
26468/*! DLTCODE - Delay Line Test Code
26469 */
26470#define DDRPHY_DX3GSR1_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR1_DLTCODE_SHIFT)) & DDRPHY_DX3GSR1_DLTCODE_MASK)
26471#define DDRPHY_DX3GSR1_RESERVED_31_25_MASK (0xFE000000U)
26472#define DDRPHY_DX3GSR1_RESERVED_31_25_SHIFT (25U)
26473/*! RESERVED_31_25 - Reserved. Returns zeroes on reads.
26474 */
26475#define DDRPHY_DX3GSR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX3GSR1_RESERVED_31_25_MASK)
26476/*! @} */
26477
26478/*! @name DX3GSR2 - DATX8 n General Status Register 2 */
26479/*! @{ */
26480#define DDRPHY_DX3GSR2_RDERR_MASK (0x1U)
26481#define DDRPHY_DX3GSR2_RDERR_SHIFT (0U)
26482/*! RDERR - Read Bit Deskew Error
26483 */
26484#define DDRPHY_DX3GSR2_RDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_RDERR_SHIFT)) & DDRPHY_DX3GSR2_RDERR_MASK)
26485#define DDRPHY_DX3GSR2_RDWN_MASK (0x2U)
26486#define DDRPHY_DX3GSR2_RDWN_SHIFT (1U)
26487/*! RDWN - Read Bit Deskew Warning
26488 */
26489#define DDRPHY_DX3GSR2_RDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_RDWN_SHIFT)) & DDRPHY_DX3GSR2_RDWN_MASK)
26490#define DDRPHY_DX3GSR2_WDERR_MASK (0x4U)
26491#define DDRPHY_DX3GSR2_WDERR_SHIFT (2U)
26492/*! WDERR - Write Bit Deskew Error
26493 */
26494#define DDRPHY_DX3GSR2_WDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_WDERR_SHIFT)) & DDRPHY_DX3GSR2_WDERR_MASK)
26495#define DDRPHY_DX3GSR2_WDWN_MASK (0x8U)
26496#define DDRPHY_DX3GSR2_WDWN_SHIFT (3U)
26497/*! WDWN - Write Bit Deskew Warning
26498 */
26499#define DDRPHY_DX3GSR2_WDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_WDWN_SHIFT)) & DDRPHY_DX3GSR2_WDWN_MASK)
26500#define DDRPHY_DX3GSR2_REERR_MASK (0x10U)
26501#define DDRPHY_DX3GSR2_REERR_SHIFT (4U)
26502/*! REERR - Read Eye Centering Error
26503 */
26504#define DDRPHY_DX3GSR2_REERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_REERR_SHIFT)) & DDRPHY_DX3GSR2_REERR_MASK)
26505#define DDRPHY_DX3GSR2_REWN_MASK (0x20U)
26506#define DDRPHY_DX3GSR2_REWN_SHIFT (5U)
26507/*! REWN - Read Eye Centering Warning
26508 */
26509#define DDRPHY_DX3GSR2_REWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_REWN_SHIFT)) & DDRPHY_DX3GSR2_REWN_MASK)
26510#define DDRPHY_DX3GSR2_WEERR_MASK (0x40U)
26511#define DDRPHY_DX3GSR2_WEERR_SHIFT (6U)
26512/*! WEERR - Write Eye Centering Error
26513 */
26514#define DDRPHY_DX3GSR2_WEERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_WEERR_SHIFT)) & DDRPHY_DX3GSR2_WEERR_MASK)
26515#define DDRPHY_DX3GSR2_WEWN_MASK (0x80U)
26516#define DDRPHY_DX3GSR2_WEWN_SHIFT (7U)
26517/*! WEWN - Write Eye Centering Warning
26518 */
26519#define DDRPHY_DX3GSR2_WEWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_WEWN_SHIFT)) & DDRPHY_DX3GSR2_WEWN_MASK)
26520#define DDRPHY_DX3GSR2_ESTAT_MASK (0xF00U)
26521#define DDRPHY_DX3GSR2_ESTAT_SHIFT (8U)
26522/*! ESTAT - Error Status
26523 */
26524#define DDRPHY_DX3GSR2_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_ESTAT_SHIFT)) & DDRPHY_DX3GSR2_ESTAT_MASK)
26525#define DDRPHY_DX3GSR2_DQS2DQERR_MASK (0xFF000U)
26526#define DDRPHY_DX3GSR2_DQS2DQERR_SHIFT (12U)
26527/*! DQS2DQERR - Write DQS2DQ Training Error
26528 */
26529#define DDRPHY_DX3GSR2_DQS2DQERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX3GSR2_DQS2DQERR_MASK)
26530#define DDRPHY_DX3GSR2_SRDERR_MASK (0x100000U)
26531#define DDRPHY_DX3GSR2_SRDERR_SHIFT (20U)
26532/*! SRDERR - Static Read Error
26533 */
26534#define DDRPHY_DX3GSR2_SRDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_SRDERR_SHIFT)) & DDRPHY_DX3GSR2_SRDERR_MASK)
26535#define DDRPHY_DX3GSR2_RESERVED_21_MASK (0x200000U)
26536#define DDRPHY_DX3GSR2_RESERVED_21_SHIFT (21U)
26537/*! RESERVED_21 - Reserved. Return zeroes on reads.
26538 */
26539#define DDRPHY_DX3GSR2_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX3GSR2_RESERVED_21_MASK)
26540#define DDRPHY_DX3GSR2_GSDQSCAL_MASK (0x400000U)
26541#define DDRPHY_DX3GSR2_GSDQSCAL_SHIFT (22U)
26542/*! GSDQSCAL - Read DQS Gating Status Calibration
26543 */
26544#define DDRPHY_DX3GSR2_GSDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX3GSR2_GSDQSCAL_MASK)
26545#define DDRPHY_DX3GSR2_GSDQSPRD_MASK (0xFF800000U)
26546#define DDRPHY_DX3GSR2_GSDQSPRD_SHIFT (23U)
26547/*! GSDQSPRD - Read DQS gating Status Period
26548 */
26549#define DDRPHY_DX3GSR2_GSDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX3GSR2_GSDQSPRD_MASK)
26550/*! @} */
26551
26552/*! @name DX3GSR3 - DATX8 n General Status Register 3 */
26553/*! @{ */
26554#define DDRPHY_DX3GSR3_SRDPC_MASK (0x3U)
26555#define DDRPHY_DX3GSR3_SRDPC_SHIFT (0U)
26556/*! SRDPC - Static Read Delay Pass Count
26557 */
26558#define DDRPHY_DX3GSR3_SRDPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_SRDPC_SHIFT)) & DDRPHY_DX3GSR3_SRDPC_MASK)
26559#define DDRPHY_DX3GSR3_RESERVED_7_2_MASK (0xFCU)
26560#define DDRPHY_DX3GSR3_RESERVED_7_2_SHIFT (2U)
26561/*! RESERVED_7_2 - Reserved. Return zeroes on reads.
26562 */
26563#define DDRPHY_DX3GSR3_RESERVED_7_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX3GSR3_RESERVED_7_2_MASK)
26564#define DDRPHY_DX3GSR3_HVERR_MASK (0xF00U)
26565#define DDRPHY_DX3GSR3_HVERR_SHIFT (8U)
26566/*! HVERR - Host VREF Training Error
26567 */
26568#define DDRPHY_DX3GSR3_HVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_HVERR_SHIFT)) & DDRPHY_DX3GSR3_HVERR_MASK)
26569#define DDRPHY_DX3GSR3_HVWRN_MASK (0xF000U)
26570#define DDRPHY_DX3GSR3_HVWRN_SHIFT (12U)
26571/*! HVWRN - Host VREF Training Warning
26572 */
26573#define DDRPHY_DX3GSR3_HVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_HVWRN_SHIFT)) & DDRPHY_DX3GSR3_HVWRN_MASK)
26574#define DDRPHY_DX3GSR3_DVERR_MASK (0xF0000U)
26575#define DDRPHY_DX3GSR3_DVERR_SHIFT (16U)
26576/*! DVERR - DRAM VREF Training Error
26577 */
26578#define DDRPHY_DX3GSR3_DVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_DVERR_SHIFT)) & DDRPHY_DX3GSR3_DVERR_MASK)
26579#define DDRPHY_DX3GSR3_DVWRN_MASK (0xF00000U)
26580#define DDRPHY_DX3GSR3_DVWRN_SHIFT (20U)
26581/*! DVWRN - DRAM VREF Training Warning
26582 */
26583#define DDRPHY_DX3GSR3_DVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_DVWRN_SHIFT)) & DDRPHY_DX3GSR3_DVWRN_MASK)
26584#define DDRPHY_DX3GSR3_ESTAT_MASK (0x7000000U)
26585#define DDRPHY_DX3GSR3_ESTAT_SHIFT (24U)
26586/*! ESTAT - VREF Training Error Status Code
26587 */
26588#define DDRPHY_DX3GSR3_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_ESTAT_SHIFT)) & DDRPHY_DX3GSR3_ESTAT_MASK)
26589#define DDRPHY_DX3GSR3_RESERVED_31_27_MASK (0xF8000000U)
26590#define DDRPHY_DX3GSR3_RESERVED_31_27_SHIFT (27U)
26591/*! RESERVED_31_27 - Reserved. Return zeroes on reads.
26592 */
26593#define DDRPHY_DX3GSR3_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX3GSR3_RESERVED_31_27_MASK)
26594/*! @} */
26595
26596/*! @name DX3GSR4 - DATX8 n General Status Register 4 */
26597/*! @{ */
26598#define DDRPHY_DX3GSR4_RESERVED_0_MASK (0x1U)
26599#define DDRPHY_DX3GSR4_RESERVED_0_SHIFT (0U)
26600/*! RESERVED_0 - Reserved. Return zeroes on reads.
26601 */
26602#define DDRPHY_DX3GSR4_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_0_MASK)
26603#define DDRPHY_DX3GSR4_RESERVED_1_MASK (0x2U)
26604#define DDRPHY_DX3GSR4_RESERVED_1_SHIFT (1U)
26605/*! RESERVED_1 - Reserved. Return zeroes on reads.
26606 */
26607#define DDRPHY_DX3GSR4_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_1_MASK)
26608#define DDRPHY_DX3GSR4_RESERVED_2_MASK (0x4U)
26609#define DDRPHY_DX3GSR4_RESERVED_2_SHIFT (2U)
26610/*! RESERVED_2 - Reserved. Return zeroes on reads.
26611 */
26612#define DDRPHY_DX3GSR4_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_2_MASK)
26613#define DDRPHY_DX3GSR4_RESERVED_3_MASK (0x8U)
26614#define DDRPHY_DX3GSR4_RESERVED_3_SHIFT (3U)
26615/*! RESERVED_3 - Reserved. Return zeroes on reads.
26616 */
26617#define DDRPHY_DX3GSR4_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_3_MASK)
26618#define DDRPHY_DX3GSR4_RESERVED_4_MASK (0x10U)
26619#define DDRPHY_DX3GSR4_RESERVED_4_SHIFT (4U)
26620/*! RESERVED_4 - Reserved. Return zeroes on reads.
26621 */
26622#define DDRPHY_DX3GSR4_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_4_MASK)
26623#define DDRPHY_DX3GSR4_RESERVED_5_MASK (0x20U)
26624#define DDRPHY_DX3GSR4_RESERVED_5_SHIFT (5U)
26625/*! RESERVED_5 - Reserved. Return zeroes on reads.
26626 */
26627#define DDRPHY_DX3GSR4_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_5_MASK)
26628#define DDRPHY_DX3GSR4_RESERVED_6_MASK (0x40U)
26629#define DDRPHY_DX3GSR4_RESERVED_6_SHIFT (6U)
26630/*! RESERVED_6 - Reserved. Return zeroes on reads.
26631 */
26632#define DDRPHY_DX3GSR4_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_6_MASK)
26633#define DDRPHY_DX3GSR4_RESERVED_15_7_MASK (0xFF80U)
26634#define DDRPHY_DX3GSR4_RESERVED_15_7_SHIFT (7U)
26635/*! RESERVED_15_7 - Reserved. Return zeroes on reads.
26636 */
26637#define DDRPHY_DX3GSR4_RESERVED_15_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_15_7_MASK)
26638#define DDRPHY_DX3GSR4_RESERVED_16_MASK (0x10000U)
26639#define DDRPHY_DX3GSR4_RESERVED_16_SHIFT (16U)
26640/*! RESERVED_16 - Reserved. Return zeroes on reads.
26641 */
26642#define DDRPHY_DX3GSR4_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_16_MASK)
26643#define DDRPHY_DX3GSR4_RESERVED_25_17_MASK (0x3FE0000U)
26644#define DDRPHY_DX3GSR4_RESERVED_25_17_SHIFT (17U)
26645/*! RESERVED_25_17 - Reserved. Return zeroes on reads.
26646 */
26647#define DDRPHY_DX3GSR4_RESERVED_25_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_25_17_MASK)
26648#define DDRPHY_DX3GSR4_RESERVED_31_26_MASK (0xFC000000U)
26649#define DDRPHY_DX3GSR4_RESERVED_31_26_SHIFT (26U)
26650/*! RESERVED_31_26 - Reserved. Returns zeroes on reads.
26651 */
26652#define DDRPHY_DX3GSR4_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX3GSR4_RESERVED_31_26_MASK)
26653/*! @} */
26654
26655/*! @name DX3GSR5 - DATX8 n General Status Register 5 */
26656/*! @{ */
26657#define DDRPHY_DX3GSR5_RESERVED_0_MASK (0x1U)
26658#define DDRPHY_DX3GSR5_RESERVED_0_SHIFT (0U)
26659/*! RESERVED_0 - Reserved. Return zeroes on reads.
26660 */
26661#define DDRPHY_DX3GSR5_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_0_MASK)
26662#define DDRPHY_DX3GSR5_RESERVED_1_MASK (0x2U)
26663#define DDRPHY_DX3GSR5_RESERVED_1_SHIFT (1U)
26664/*! RESERVED_1 - Reserved. Return zeroes on reads.
26665 */
26666#define DDRPHY_DX3GSR5_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_1_MASK)
26667#define DDRPHY_DX3GSR5_RESERVED_2_MASK (0x4U)
26668#define DDRPHY_DX3GSR5_RESERVED_2_SHIFT (2U)
26669/*! RESERVED_2 - Reserved. Return zeroes on reads.
26670 */
26671#define DDRPHY_DX3GSR5_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_2_MASK)
26672#define DDRPHY_DX3GSR5_RESERVED_3_MASK (0x8U)
26673#define DDRPHY_DX3GSR5_RESERVED_3_SHIFT (3U)
26674/*! RESERVED_3 - Reserved. Return zeroes on reads.
26675 */
26676#define DDRPHY_DX3GSR5_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_3_MASK)
26677#define DDRPHY_DX3GSR5_RESERVED_4_MASK (0x10U)
26678#define DDRPHY_DX3GSR5_RESERVED_4_SHIFT (4U)
26679/*! RESERVED_4 - Reserved. Return zeroes on reads.
26680 */
26681#define DDRPHY_DX3GSR5_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_4_MASK)
26682#define DDRPHY_DX3GSR5_RESERVED_5_MASK (0x20U)
26683#define DDRPHY_DX3GSR5_RESERVED_5_SHIFT (5U)
26684/*! RESERVED_5 - Reserved. Return zeroes on reads.
26685 */
26686#define DDRPHY_DX3GSR5_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_5_MASK)
26687#define DDRPHY_DX3GSR5_RESERVED_6_MASK (0x40U)
26688#define DDRPHY_DX3GSR5_RESERVED_6_SHIFT (6U)
26689/*! RESERVED_6 - Reserved. Return zeroes on reads.
26690 */
26691#define DDRPHY_DX3GSR5_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_6_MASK)
26692#define DDRPHY_DX3GSR5_RESERVED_7_MASK (0x80U)
26693#define DDRPHY_DX3GSR5_RESERVED_7_SHIFT (7U)
26694/*! RESERVED_7 - Reserved. Return zeroes on reads.
26695 */
26696#define DDRPHY_DX3GSR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_7_MASK)
26697#define DDRPHY_DX3GSR5_RESERVED_11_8_MASK (0xF00U)
26698#define DDRPHY_DX3GSR5_RESERVED_11_8_SHIFT (8U)
26699/*! RESERVED_11_8 - Reserved. Return zeroes on reads.
26700 */
26701#define DDRPHY_DX3GSR5_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_11_8_MASK)
26702#define DDRPHY_DX3GSR5_RESERVED_19_12_MASK (0xFF000U)
26703#define DDRPHY_DX3GSR5_RESERVED_19_12_SHIFT (12U)
26704/*! RESERVED_19_12 - Reserved. Return zeroes on reads.
26705 */
26706#define DDRPHY_DX3GSR5_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_19_12_MASK)
26707#define DDRPHY_DX3GSR5_RESERVED_20_MASK (0x100000U)
26708#define DDRPHY_DX3GSR5_RESERVED_20_SHIFT (20U)
26709/*! RESERVED_20 - Reserved. Return zeroes on reads.
26710 */
26711#define DDRPHY_DX3GSR5_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_20_MASK)
26712#define DDRPHY_DX3GSR5_RESERVED_21_MASK (0x200000U)
26713#define DDRPHY_DX3GSR5_RESERVED_21_SHIFT (21U)
26714/*! RESERVED_21 - Reserved. Return zeroes on reads.
26715 */
26716#define DDRPHY_DX3GSR5_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_21_MASK)
26717#define DDRPHY_DX3GSR5_RESERVED_22_MASK (0x400000U)
26718#define DDRPHY_DX3GSR5_RESERVED_22_SHIFT (22U)
26719/*! RESERVED_22 - Reserved. Return zeroes on reads.
26720 */
26721#define DDRPHY_DX3GSR5_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_22_MASK)
26722#define DDRPHY_DX3GSR5_RESERVED_31_23_MASK (0xFF800000U)
26723#define DDRPHY_DX3GSR5_RESERVED_31_23_SHIFT (23U)
26724/*! RESERVED_31_23 - Reserved. Return zeroes on reads.
26725 */
26726#define DDRPHY_DX3GSR5_RESERVED_31_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX3GSR5_RESERVED_31_23_MASK)
26727/*! @} */
26728
26729/*! @name DX3GSR6 - DATX8 n General Status Register 6 */
26730/*! @{ */
26731#define DDRPHY_DX3GSR6_RESERVED_1_0_MASK (0x3U)
26732#define DDRPHY_DX3GSR6_RESERVED_1_0_SHIFT (0U)
26733/*! RESERVED_1_0 - Reserved. Return zeroes on reads.
26734 */
26735#define DDRPHY_DX3GSR6_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_1_0_MASK)
26736#define DDRPHY_DX3GSR6_RESERVED_3_2_MASK (0xCU)
26737#define DDRPHY_DX3GSR6_RESERVED_3_2_SHIFT (2U)
26738/*! RESERVED_3_2 - Reserved. Return zeroes on reads.
26739 */
26740#define DDRPHY_DX3GSR6_RESERVED_3_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_3_2_MASK)
26741#define DDRPHY_DX3GSR6_RESERVED_7_4_MASK (0xF0U)
26742#define DDRPHY_DX3GSR6_RESERVED_7_4_SHIFT (4U)
26743/*! RESERVED_7_4 - Reserved. Return zeroes on reads.
26744 */
26745#define DDRPHY_DX3GSR6_RESERVED_7_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_7_4_MASK)
26746#define DDRPHY_DX3GSR6_RESERVED_11_8_MASK (0xF00U)
26747#define DDRPHY_DX3GSR6_RESERVED_11_8_SHIFT (8U)
26748/*! RESERVED_11_8 - Reserved. Return zeroes on reads.
26749 */
26750#define DDRPHY_DX3GSR6_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_11_8_MASK)
26751#define DDRPHY_DX3GSR6_RESERVED_15_12_MASK (0xF000U)
26752#define DDRPHY_DX3GSR6_RESERVED_15_12_SHIFT (12U)
26753/*! RESERVED_15_12 - Reserved. Return zeroes on reads.
26754 */
26755#define DDRPHY_DX3GSR6_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_15_12_MASK)
26756#define DDRPHY_DX3GSR6_RESERVED_19_15_MASK (0xF0000U)
26757#define DDRPHY_DX3GSR6_RESERVED_19_15_SHIFT (16U)
26758/*! RESERVED_19_15 - Reserved. Return zeroes on reads.
26759 */
26760#define DDRPHY_DX3GSR6_RESERVED_19_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_19_15_MASK)
26761#define DDRPHY_DX3GSR6_RESERVED_23_20_MASK (0xF00000U)
26762#define DDRPHY_DX3GSR6_RESERVED_23_20_SHIFT (20U)
26763/*! RESERVED_23_20 - Reserved. Return zeroes on reads.
26764 */
26765#define DDRPHY_DX3GSR6_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_23_20_MASK)
26766#define DDRPHY_DX3GSR6_RESERVED_31_24_MASK (0xFF000000U)
26767#define DDRPHY_DX3GSR6_RESERVED_31_24_SHIFT (24U)
26768/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
26769 */
26770#define DDRPHY_DX3GSR6_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX3GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX3GSR6_RESERVED_31_24_MASK)
26771/*! @} */
26772
26773/*! @name DX4GCR0 - DATX8 n General Configuration Register 0 */
26774/*! @{ */
26775#define DDRPHY_DX4GCR0_RESERVED_1_0_MASK (0x3U)
26776#define DDRPHY_DX4GCR0_RESERVED_1_0_SHIFT (0U)
26777/*! RESERVED_1_0 - Reserved. Return zeroes on reads.
26778 */
26779#define DDRPHY_DX4GCR0_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX4GCR0_RESERVED_1_0_MASK)
26780#define DDRPHY_DX4GCR0_DQSGOE_MASK (0x4U)
26781#define DDRPHY_DX4GCR0_DQSGOE_SHIFT (2U)
26782/*! DQSGOE - DQSG Output Enable
26783 */
26784#define DDRPHY_DX4GCR0_DQSGOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSGOE_SHIFT)) & DDRPHY_DX4GCR0_DQSGOE_MASK)
26785#define DDRPHY_DX4GCR0_DQSGODT_MASK (0x8U)
26786#define DDRPHY_DX4GCR0_DQSGODT_SHIFT (3U)
26787/*! DQSGODT - DQSG On-Die Termination
26788 */
26789#define DDRPHY_DX4GCR0_DQSGODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSGODT_SHIFT)) & DDRPHY_DX4GCR0_DQSGODT_MASK)
26790#define DDRPHY_DX4GCR0_RESERVED_4_MASK (0x10U)
26791#define DDRPHY_DX4GCR0_RESERVED_4_SHIFT (4U)
26792/*! RESERVED_4 - Reserved. Return zeroes on reads.
26793 */
26794#define DDRPHY_DX4GCR0_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX4GCR0_RESERVED_4_MASK)
26795#define DDRPHY_DX4GCR0_DQSGPDR_MASK (0x20U)
26796#define DDRPHY_DX4GCR0_DQSGPDR_SHIFT (5U)
26797/*! DQSGPDR - DQSG Power Down Receiver
26798 */
26799#define DDRPHY_DX4GCR0_DQSGPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX4GCR0_DQSGPDR_MASK)
26800#define DDRPHY_DX4GCR0_DQSRPD_MASK (0x40U)
26801#define DDRPHY_DX4GCR0_DQSRPD_SHIFT (6U)
26802/*! DQSRPD - DQSR Power Down
26803 */
26804#define DDRPHY_DX4GCR0_DQSRPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSRPD_SHIFT)) & DDRPHY_DX4GCR0_DQSRPD_MASK)
26805#define DDRPHY_DX4GCR0_CPDRSHFT_MASK (0x180U)
26806#define DDRPHY_DX4GCR0_CPDRSHFT_SHIFT (7U)
26807/*! CPDRSHFT - Configurable PDR Phase Shift
26808 */
26809#define DDRPHY_DX4GCR0_CPDRSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX4GCR0_CPDRSHFT_MASK)
26810#define DDRPHY_DX4GCR0_RTTOH_MASK (0x600U)
26811#define DDRPHY_DX4GCR0_RTTOH_SHIFT (9U)
26812/*! RTTOH - RTT Output Hold
26813 */
26814#define DDRPHY_DX4GCR0_RTTOH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_RTTOH_SHIFT)) & DDRPHY_DX4GCR0_RTTOH_MASK)
26815#define DDRPHY_DX4GCR0_RTTOAL_MASK (0x800U)
26816#define DDRPHY_DX4GCR0_RTTOAL_SHIFT (11U)
26817/*! RTTOAL - RTT On Additive Latency
26818 */
26819#define DDRPHY_DX4GCR0_RTTOAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_RTTOAL_SHIFT)) & DDRPHY_DX4GCR0_RTTOAL_MASK)
26820#define DDRPHY_DX4GCR0_DQSSEPDR_MASK (0x1000U)
26821#define DDRPHY_DX4GCR0_DQSSEPDR_SHIFT (12U)
26822/*! DQSSEPDR - DQSSE Power Down Receiver
26823 */
26824#define DDRPHY_DX4GCR0_DQSSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX4GCR0_DQSSEPDR_MASK)
26825#define DDRPHY_DX4GCR0_DQSNSEPDR_MASK (0x2000U)
26826#define DDRPHY_DX4GCR0_DQSNSEPDR_SHIFT (13U)
26827/*! DQSNSEPDR - DQSNSE Power Down Receiver
26828 */
26829#define DDRPHY_DX4GCR0_DQSNSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX4GCR0_DQSNSEPDR_MASK)
26830#define DDRPHY_DX4GCR0_RESERVED_19_14_MASK (0xFC000U)
26831#define DDRPHY_DX4GCR0_RESERVED_19_14_SHIFT (14U)
26832/*! RESERVED_19_14 - Reserved. Return zeroes on reads.
26833 */
26834#define DDRPHY_DX4GCR0_RESERVED_19_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX4GCR0_RESERVED_19_14_MASK)
26835#define DDRPHY_DX4GCR0_RDDLY_MASK (0xF00000U)
26836#define DDRPHY_DX4GCR0_RDDLY_SHIFT (20U)
26837/*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
26838 */
26839#define DDRPHY_DX4GCR0_RDDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_RDDLY_SHIFT)) & DDRPHY_DX4GCR0_RDDLY_MASK)
26840#define DDRPHY_DX4GCR0_DQSDCC_MASK (0xF000000U)
26841#define DDRPHY_DX4GCR0_DQSDCC_SHIFT (24U)
26842/*! DQSDCC - DQS Duty Cycle Correction
26843 */
26844#define DDRPHY_DX4GCR0_DQSDCC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_DQSDCC_SHIFT)) & DDRPHY_DX4GCR0_DQSDCC_MASK)
26845#define DDRPHY_DX4GCR0_CODTSHFT_MASK (0x30000000U)
26846#define DDRPHY_DX4GCR0_CODTSHFT_SHIFT (28U)
26847/*! CODTSHFT - Configurable ODT(TE) Phase Shift
26848 */
26849#define DDRPHY_DX4GCR0_CODTSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX4GCR0_CODTSHFT_MASK)
26850#define DDRPHY_DX4GCR0_MDLEN_MASK (0x40000000U)
26851#define DDRPHY_DX4GCR0_MDLEN_SHIFT (30U)
26852/*! MDLEN - Master Delay Line Enable
26853 */
26854#define DDRPHY_DX4GCR0_MDLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_MDLEN_SHIFT)) & DDRPHY_DX4GCR0_MDLEN_MASK)
26855#define DDRPHY_DX4GCR0_CALBYP_MASK (0x80000000U)
26856#define DDRPHY_DX4GCR0_CALBYP_SHIFT (31U)
26857/*! CALBYP - Calibration Bypass
26858 */
26859#define DDRPHY_DX4GCR0_CALBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR0_CALBYP_SHIFT)) & DDRPHY_DX4GCR0_CALBYP_MASK)
26860/*! @} */
26861
26862/*! @name DX4GCR1 - DATX8 n General Configuration Register 1 */
26863/*! @{ */
26864#define DDRPHY_DX4GCR1_DQEN_MASK (0xFFU)
26865#define DDRPHY_DX4GCR1_DQEN_SHIFT (0U)
26866/*! DQEN - Enables DQ corresponding to each bit in a byte
26867 */
26868#define DDRPHY_DX4GCR1_DQEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_DQEN_SHIFT)) & DDRPHY_DX4GCR1_DQEN_MASK)
26869#define DDRPHY_DX4GCR1_DMEN_MASK (0x100U)
26870#define DDRPHY_DX4GCR1_DMEN_SHIFT (8U)
26871/*! DMEN - Enables DM pin in a byte lane
26872 */
26873#define DDRPHY_DX4GCR1_DMEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_DMEN_SHIFT)) & DDRPHY_DX4GCR1_DMEN_MASK)
26874#define DDRPHY_DX4GCR1_DSEN_MASK (0x200U)
26875#define DDRPHY_DX4GCR1_DSEN_SHIFT (9U)
26876/*! DSEN - Enables Write Data strobe in a byte lane
26877 */
26878#define DDRPHY_DX4GCR1_DSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_DSEN_SHIFT)) & DDRPHY_DX4GCR1_DSEN_MASK)
26879#define DDRPHY_DX4GCR1_TEEN_MASK (0x400U)
26880#define DDRPHY_DX4GCR1_TEEN_SHIFT (10U)
26881/*! TEEN - Enables ODT/TE in a byte lane
26882 */
26883#define DDRPHY_DX4GCR1_TEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_TEEN_SHIFT)) & DDRPHY_DX4GCR1_TEEN_MASK)
26884#define DDRPHY_DX4GCR1_PDREN_MASK (0x800U)
26885#define DDRPHY_DX4GCR1_PDREN_SHIFT (11U)
26886/*! PDREN - Enables PDR in a byte lane
26887 */
26888#define DDRPHY_DX4GCR1_PDREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_PDREN_SHIFT)) & DDRPHY_DX4GCR1_PDREN_MASK)
26889#define DDRPHY_DX4GCR1_OEEN_MASK (0x1000U)
26890#define DDRPHY_DX4GCR1_OEEN_SHIFT (12U)
26891/*! OEEN - Enables Read Data Strobe in a byte lane
26892 */
26893#define DDRPHY_DX4GCR1_OEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_OEEN_SHIFT)) & DDRPHY_DX4GCR1_OEEN_MASK)
26894#define DDRPHY_DX4GCR1_QSSEL_MASK (0x2000U)
26895#define DDRPHY_DX4GCR1_QSSEL_SHIFT (13U)
26896/*! QSSEL - Select the delayed or non-delayed read data strobe
26897 */
26898#define DDRPHY_DX4GCR1_QSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_QSSEL_SHIFT)) & DDRPHY_DX4GCR1_QSSEL_MASK)
26899#define DDRPHY_DX4GCR1_QSNSEL_MASK (0x4000U)
26900#define DDRPHY_DX4GCR1_QSNSEL_SHIFT (14U)
26901/*! QSNSEL - Select the delayed or non-delayed read data strobe #
26902 */
26903#define DDRPHY_DX4GCR1_QSNSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_QSNSEL_SHIFT)) & DDRPHY_DX4GCR1_QSNSEL_MASK)
26904#define DDRPHY_DX4GCR1_RESERVED_15_MASK (0x8000U)
26905#define DDRPHY_DX4GCR1_RESERVED_15_SHIFT (15U)
26906/*! RESERVED_15 - Reserved. Returns zeroes on reads.
26907 */
26908#define DDRPHY_DX4GCR1_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX4GCR1_RESERVED_15_MASK)
26909#define DDRPHY_DX4GCR1_DXPDRMODE_MASK (0xFFFF0000U)
26910#define DDRPHY_DX4GCR1_DXPDRMODE_SHIFT (16U)
26911/*! DXPDRMODE - Enables the PDR mode for DQ[7:0]
26912 */
26913#define DDRPHY_DX4GCR1_DXPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX4GCR1_DXPDRMODE_MASK)
26914/*! @} */
26915
26916/*! @name DX4GCR2 - DATX8 n General Configuration Register 2 */
26917/*! @{ */
26918#define DDRPHY_DX4GCR2_DXTEMODE_MASK (0xFFFFU)
26919#define DDRPHY_DX4GCR2_DXTEMODE_SHIFT (0U)
26920/*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0]
26921 */
26922#define DDRPHY_DX4GCR2_DXTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX4GCR2_DXTEMODE_MASK)
26923#define DDRPHY_DX4GCR2_DXOEMODE_MASK (0xFFFF0000U)
26924#define DDRPHY_DX4GCR2_DXOEMODE_SHIFT (16U)
26925/*! DXOEMODE - Enables the OE mode values for DQ[7:0]
26926 */
26927#define DDRPHY_DX4GCR2_DXOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX4GCR2_DXOEMODE_MASK)
26928/*! @} */
26929
26930/*! @name DX4GCR3 - DATX8 n General Configuration Register 3 */
26931/*! @{ */
26932#define DDRPHY_DX4GCR3_WDMBVT_MASK (0x1U)
26933#define DDRPHY_DX4GCR3_WDMBVT_SHIFT (0U)
26934/*! WDMBVT - Write Data Mask BDL VT Compensation
26935 */
26936#define DDRPHY_DX4GCR3_WDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_WDMBVT_SHIFT)) & DDRPHY_DX4GCR3_WDMBVT_MASK)
26937#define DDRPHY_DX4GCR3_RDMBVT_MASK (0x2U)
26938#define DDRPHY_DX4GCR3_RDMBVT_SHIFT (1U)
26939/*! RDMBVT - Read Data Mask BDL VT Compensation
26940 */
26941#define DDRPHY_DX4GCR3_RDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_RDMBVT_SHIFT)) & DDRPHY_DX4GCR3_RDMBVT_MASK)
26942#define DDRPHY_DX4GCR3_DSPDRMODE_MASK (0xCU)
26943#define DDRPHY_DX4GCR3_DSPDRMODE_SHIFT (2U)
26944/*! DSPDRMODE - Enables the PDR mode values for DQS.
26945 */
26946#define DDRPHY_DX4GCR3_DSPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX4GCR3_DSPDRMODE_MASK)
26947#define DDRPHY_DX4GCR3_DSTEMODE_MASK (0x30U)
26948#define DDRPHY_DX4GCR3_DSTEMODE_SHIFT (4U)
26949/*! DSTEMODE - Enables the TE mode values for DQS.
26950 */
26951#define DDRPHY_DX4GCR3_DSTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX4GCR3_DSTEMODE_MASK)
26952#define DDRPHY_DX4GCR3_DSOEMODE_MASK (0xC0U)
26953#define DDRPHY_DX4GCR3_DSOEMODE_SHIFT (6U)
26954/*! DSOEMODE - Enables the OE mode values for DQS.
26955 */
26956#define DDRPHY_DX4GCR3_DSOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX4GCR3_DSOEMODE_MASK)
26957#define DDRPHY_DX4GCR3_WDSBVT_MASK (0x100U)
26958#define DDRPHY_DX4GCR3_WDSBVT_SHIFT (8U)
26959/*! WDSBVT - Write Data Strobe BDL VT Compensation
26960 */
26961#define DDRPHY_DX4GCR3_WDSBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_WDSBVT_SHIFT)) & DDRPHY_DX4GCR3_WDSBVT_MASK)
26962#define DDRPHY_DX4GCR3_RESERVED_9_MASK (0x200U)
26963#define DDRPHY_DX4GCR3_RESERVED_9_SHIFT (9U)
26964/*! RESERVED_9 - Reserved. Returns zeroes on reads.
26965 */
26966#define DDRPHY_DX4GCR3_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX4GCR3_RESERVED_9_MASK)
26967#define DDRPHY_DX4GCR3_DMPDRMODE_MASK (0xC00U)
26968#define DDRPHY_DX4GCR3_DMPDRMODE_SHIFT (10U)
26969/*! DMPDRMODE - Enables the PDR mode values for DM.
26970 */
26971#define DDRPHY_DX4GCR3_DMPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX4GCR3_DMPDRMODE_MASK)
26972#define DDRPHY_DX4GCR3_DMTEMODE_MASK (0x3000U)
26973#define DDRPHY_DX4GCR3_DMTEMODE_SHIFT (12U)
26974/*! DMTEMODE - Enables the TE mode values for DM.
26975 */
26976#define DDRPHY_DX4GCR3_DMTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX4GCR3_DMTEMODE_MASK)
26977#define DDRPHY_DX4GCR3_DMOEMODE_MASK (0xC000U)
26978#define DDRPHY_DX4GCR3_DMOEMODE_SHIFT (14U)
26979/*! DMOEMODE - Enables the OE mode values for DM.
26980 */
26981#define DDRPHY_DX4GCR3_DMOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX4GCR3_DMOEMODE_MASK)
26982#define DDRPHY_DX4GCR3_DSNPDRMODE_MASK (0x30000U)
26983#define DDRPHY_DX4GCR3_DSNPDRMODE_SHIFT (16U)
26984/*! DSNPDRMODE - Enables the PDR mode for DQS
26985 */
26986#define DDRPHY_DX4GCR3_DSNPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX4GCR3_DSNPDRMODE_MASK)
26987#define DDRPHY_DX4GCR3_DSNTEMODE_MASK (0xC0000U)
26988#define DDRPHY_DX4GCR3_DSNTEMODE_SHIFT (18U)
26989/*! DSNTEMODE - Enables the TE mode for DQS
26990 */
26991#define DDRPHY_DX4GCR3_DSNTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX4GCR3_DSNTEMODE_MASK)
26992#define DDRPHY_DX4GCR3_DSNOEMODE_MASK (0x300000U)
26993#define DDRPHY_DX4GCR3_DSNOEMODE_SHIFT (20U)
26994/*! DSNOEMODE - Enables the OE mode for DQs
26995 */
26996#define DDRPHY_DX4GCR3_DSNOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX4GCR3_DSNOEMODE_MASK)
26997#define DDRPHY_DX4GCR3_PDRBVT_MASK (0x400000U)
26998#define DDRPHY_DX4GCR3_PDRBVT_SHIFT (22U)
26999/*! PDRBVT - Power Down Receiver BDL VT Compensation
27000 */
27001#define DDRPHY_DX4GCR3_PDRBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_PDRBVT_SHIFT)) & DDRPHY_DX4GCR3_PDRBVT_MASK)
27002#define DDRPHY_DX4GCR3_RGSLVT_MASK (0x800000U)
27003#define DDRPHY_DX4GCR3_RGSLVT_SHIFT (23U)
27004/*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation
27005 */
27006#define DDRPHY_DX4GCR3_RGSLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_RGSLVT_SHIFT)) & DDRPHY_DX4GCR3_RGSLVT_MASK)
27007#define DDRPHY_DX4GCR3_WLLVT_MASK (0x1000000U)
27008#define DDRPHY_DX4GCR3_WLLVT_SHIFT (24U)
27009/*! WLLVT - Write Leveling LCDL Delay VT Compensation
27010 */
27011#define DDRPHY_DX4GCR3_WLLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_WLLVT_SHIFT)) & DDRPHY_DX4GCR3_WLLVT_MASK)
27012#define DDRPHY_DX4GCR3_WDLVT_MASK (0x2000000U)
27013#define DDRPHY_DX4GCR3_WDLVT_SHIFT (25U)
27014/*! WDLVT - Write DQ LCDL Delay VT Compensation
27015 */
27016#define DDRPHY_DX4GCR3_WDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_WDLVT_SHIFT)) & DDRPHY_DX4GCR3_WDLVT_MASK)
27017#define DDRPHY_DX4GCR3_RDLVT_MASK (0x4000000U)
27018#define DDRPHY_DX4GCR3_RDLVT_SHIFT (26U)
27019/*! RDLVT - Read DQS LCDL Delay VT Compensation
27020 */
27021#define DDRPHY_DX4GCR3_RDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_RDLVT_SHIFT)) & DDRPHY_DX4GCR3_RDLVT_MASK)
27022#define DDRPHY_DX4GCR3_RGLVT_MASK (0x8000000U)
27023#define DDRPHY_DX4GCR3_RGLVT_SHIFT (27U)
27024/*! RGLVT - Read DQS Gating LCDL Delay VT Compensation
27025 */
27026#define DDRPHY_DX4GCR3_RGLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_RGLVT_SHIFT)) & DDRPHY_DX4GCR3_RGLVT_MASK)
27027#define DDRPHY_DX4GCR3_WDBVT_MASK (0x10000000U)
27028#define DDRPHY_DX4GCR3_WDBVT_SHIFT (28U)
27029/*! WDBVT - Write Data BDL VT Compensation
27030 */
27031#define DDRPHY_DX4GCR3_WDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_WDBVT_SHIFT)) & DDRPHY_DX4GCR3_WDBVT_MASK)
27032#define DDRPHY_DX4GCR3_RDBVT_MASK (0x20000000U)
27033#define DDRPHY_DX4GCR3_RDBVT_SHIFT (29U)
27034/*! RDBVT - Read Data BDL VT Compensation
27035 */
27036#define DDRPHY_DX4GCR3_RDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_RDBVT_SHIFT)) & DDRPHY_DX4GCR3_RDBVT_MASK)
27037#define DDRPHY_DX4GCR3_TEBVT_MASK (0x40000000U)
27038#define DDRPHY_DX4GCR3_TEBVT_SHIFT (30U)
27039/*! TEBVT - Termination Enable BDL VT Compensation
27040 */
27041#define DDRPHY_DX4GCR3_TEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_TEBVT_SHIFT)) & DDRPHY_DX4GCR3_TEBVT_MASK)
27042#define DDRPHY_DX4GCR3_OEBVT_MASK (0x80000000U)
27043#define DDRPHY_DX4GCR3_OEBVT_SHIFT (31U)
27044/*! OEBVT - Output Enable BDL VT Compensation
27045 */
27046#define DDRPHY_DX4GCR3_OEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR3_OEBVT_SHIFT)) & DDRPHY_DX4GCR3_OEBVT_MASK)
27047/*! @} */
27048
27049/*! @name DX4GCR4 - DATX8 n General Configuration Register 4 */
27050/*! @{ */
27051#define DDRPHY_DX4GCR4_DXREFIMON_MASK (0x3U)
27052#define DDRPHY_DX4GCR4_DXREFIMON_SHIFT (0U)
27053/*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane.
27054 */
27055#define DDRPHY_DX4GCR4_DXREFIMON(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX4GCR4_DXREFIMON_MASK)
27056#define DDRPHY_DX4GCR4_DXREFIEN_MASK (0x3CU)
27057#define DDRPHY_DX4GCR4_DXREFIEN_SHIFT (2U)
27058/*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
27059 */
27060#define DDRPHY_DX4GCR4_DXREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX4GCR4_DXREFIEN_MASK)
27061#define DDRPHY_DX4GCR4_RESERVED_7_6_MASK (0xC0U)
27062#define DDRPHY_DX4GCR4_RESERVED_7_6_SHIFT (6U)
27063/*! RESERVED_7_6 - Reserved. Returns zeros on reads.
27064 */
27065#define DDRPHY_DX4GCR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX4GCR4_RESERVED_7_6_MASK)
27066#define DDRPHY_DX4GCR4_DXREFSSEL_MASK (0x7F00U)
27067#define DDRPHY_DX4GCR4_DXREFSSEL_SHIFT (8U)
27068/*! DXREFSSEL - Byte Lane Single-End VREF Select
27069 */
27070#define DDRPHY_DX4GCR4_DXREFSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX4GCR4_DXREFSSEL_MASK)
27071#define DDRPHY_DX4GCR4_DXREFSSELRANGE_MASK (0x8000U)
27072#define DDRPHY_DX4GCR4_DXREFSSELRANGE_SHIFT (15U)
27073/*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select
27074 */
27075#define DDRPHY_DX4GCR4_DXREFSSELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX4GCR4_DXREFSSELRANGE_MASK)
27076#define DDRPHY_DX4GCR4_DXREFESEL_MASK (0x7F0000U)
27077#define DDRPHY_DX4GCR4_DXREFESEL_SHIFT (16U)
27078/*! DXREFESEL - Byte Lane External VREF Select
27079 */
27080#define DDRPHY_DX4GCR4_DXREFESEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX4GCR4_DXREFESEL_MASK)
27081#define DDRPHY_DX4GCR4_DXREFESELRANGE_MASK (0x800000U)
27082#define DDRPHY_DX4GCR4_DXREFESELRANGE_SHIFT (23U)
27083/*! DXREFESELRANGE - External VREF generator REFSEL range select
27084 */
27085#define DDRPHY_DX4GCR4_DXREFESELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX4GCR4_DXREFESELRANGE_MASK)
27086#define DDRPHY_DX4GCR4_RESERVED_24_MASK (0x1000000U)
27087#define DDRPHY_DX4GCR4_RESERVED_24_SHIFT (24U)
27088/*! RESERVED_24 - Reserved. Returns zeros on reads.
27089 */
27090#define DDRPHY_DX4GCR4_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX4GCR4_RESERVED_24_MASK)
27091#define DDRPHY_DX4GCR4_DXREFSEN_MASK (0x2000000U)
27092#define DDRPHY_DX4GCR4_DXREFSEN_SHIFT (25U)
27093/*! DXREFSEN - Byte Lane Single-End VREF Enable
27094 */
27095#define DDRPHY_DX4GCR4_DXREFSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX4GCR4_DXREFSEN_MASK)
27096#define DDRPHY_DX4GCR4_DXREFEEN_MASK (0xC000000U)
27097#define DDRPHY_DX4GCR4_DXREFEEN_SHIFT (26U)
27098/*! DXREFEEN - Byte Lane Internal VREF Enable
27099 */
27100#define DDRPHY_DX4GCR4_DXREFEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX4GCR4_DXREFEEN_MASK)
27101#define DDRPHY_DX4GCR4_DXREFPEN_MASK (0x10000000U)
27102#define DDRPHY_DX4GCR4_DXREFPEN_SHIFT (28U)
27103/*! DXREFPEN - Byte Lane VREF Pad Enable
27104 */
27105#define DDRPHY_DX4GCR4_DXREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX4GCR4_DXREFPEN_MASK)
27106#define DDRPHY_DX4GCR4_RESERVED_31_29_MASK (0xE0000000U)
27107#define DDRPHY_DX4GCR4_RESERVED_31_29_SHIFT (29U)
27108/*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs)
27109 */
27110#define DDRPHY_DX4GCR4_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX4GCR4_RESERVED_31_29_MASK)
27111/*! @} */
27112
27113/*! @name DX4GCR5 - DATX8 n General Configuration Register 5 */
27114/*! @{ */
27115#define DDRPHY_DX4GCR5_DXREFISELR0_MASK (0x7FU)
27116#define DDRPHY_DX4GCR5_DXREFISELR0_SHIFT (0U)
27117/*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0
27118 */
27119#define DDRPHY_DX4GCR5_DXREFISELR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX4GCR5_DXREFISELR0_MASK)
27120#define DDRPHY_DX4GCR5_RESERVED_7_MASK (0x80U)
27121#define DDRPHY_DX4GCR5_RESERVED_7_SHIFT (7U)
27122/*! RESERVED_7 - Reserved. Returns zeros on reads.
27123 */
27124#define DDRPHY_DX4GCR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX4GCR5_RESERVED_7_MASK)
27125#define DDRPHY_DX4GCR5_DXREFISELR1_MASK (0x7F00U)
27126#define DDRPHY_DX4GCR5_DXREFISELR1_SHIFT (8U)
27127/*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1
27128 */
27129#define DDRPHY_DX4GCR5_DXREFISELR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX4GCR5_DXREFISELR1_MASK)
27130#define DDRPHY_DX4GCR5_RESERVED_15_MASK (0x8000U)
27131#define DDRPHY_DX4GCR5_RESERVED_15_SHIFT (15U)
27132/*! RESERVED_15 - Reserved. Returns zeros on reads.
27133 */
27134#define DDRPHY_DX4GCR5_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX4GCR5_RESERVED_15_MASK)
27135#define DDRPHY_DX4GCR5_DXREFISELR2_MASK (0x7F0000U)
27136#define DDRPHY_DX4GCR5_DXREFISELR2_SHIFT (16U)
27137/*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2
27138 */
27139#define DDRPHY_DX4GCR5_DXREFISELR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX4GCR5_DXREFISELR2_MASK)
27140#define DDRPHY_DX4GCR5_RESERVED_23_MASK (0x800000U)
27141#define DDRPHY_DX4GCR5_RESERVED_23_SHIFT (23U)
27142/*! RESERVED_23 - Reserved. Returns zeros on reads.
27143 */
27144#define DDRPHY_DX4GCR5_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX4GCR5_RESERVED_23_MASK)
27145#define DDRPHY_DX4GCR5_DXREFISELR3_MASK (0x7F000000U)
27146#define DDRPHY_DX4GCR5_DXREFISELR3_SHIFT (24U)
27147/*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3
27148 */
27149#define DDRPHY_DX4GCR5_DXREFISELR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX4GCR5_DXREFISELR3_MASK)
27150#define DDRPHY_DX4GCR5_RESERVED_31_MASK (0x80000000U)
27151#define DDRPHY_DX4GCR5_RESERVED_31_SHIFT (31U)
27152/*! RESERVED_31 - Reserved. Returns zeros on reads.
27153 */
27154#define DDRPHY_DX4GCR5_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX4GCR5_RESERVED_31_MASK)
27155/*! @} */
27156
27157/*! @name DX4GCR6 - DATX8 n General Configuration Register 6 */
27158/*! @{ */
27159#define DDRPHY_DX4GCR6_DXDQVREFR0_MASK (0x3FU)
27160#define DDRPHY_DX4GCR6_DXDQVREFR0_SHIFT (0U)
27161/*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0
27162 */
27163#define DDRPHY_DX4GCR6_DXDQVREFR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX4GCR6_DXDQVREFR0_MASK)
27164#define DDRPHY_DX4GCR6_RESERVED_7_6_MASK (0xC0U)
27165#define DDRPHY_DX4GCR6_RESERVED_7_6_SHIFT (6U)
27166/*! RESERVED_7_6 - Reserved. Returns zeros on reads.
27167 */
27168#define DDRPHY_DX4GCR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX4GCR6_RESERVED_7_6_MASK)
27169#define DDRPHY_DX4GCR6_DXDQVREFR1_MASK (0x3F00U)
27170#define DDRPHY_DX4GCR6_DXDQVREFR1_SHIFT (8U)
27171/*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1
27172 */
27173#define DDRPHY_DX4GCR6_DXDQVREFR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX4GCR6_DXDQVREFR1_MASK)
27174#define DDRPHY_DX4GCR6_RESERVED_15_14_MASK (0xC000U)
27175#define DDRPHY_DX4GCR6_RESERVED_15_14_SHIFT (14U)
27176/*! RESERVED_15_14 - Reserved. Returns zeros on reads.
27177 */
27178#define DDRPHY_DX4GCR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX4GCR6_RESERVED_15_14_MASK)
27179#define DDRPHY_DX4GCR6_DXDQVREFR2_MASK (0x3F0000U)
27180#define DDRPHY_DX4GCR6_DXDQVREFR2_SHIFT (16U)
27181/*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2
27182 */
27183#define DDRPHY_DX4GCR6_DXDQVREFR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX4GCR6_DXDQVREFR2_MASK)
27184#define DDRPHY_DX4GCR6_RESERVED_23_22_MASK (0xC00000U)
27185#define DDRPHY_DX4GCR6_RESERVED_23_22_SHIFT (22U)
27186/*! RESERVED_23_22 - Reserved. Returns zeros on reads.
27187 */
27188#define DDRPHY_DX4GCR6_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX4GCR6_RESERVED_23_22_MASK)
27189#define DDRPHY_DX4GCR6_DXDQVREFR3_MASK (0x3F000000U)
27190#define DDRPHY_DX4GCR6_DXDQVREFR3_SHIFT (24U)
27191/*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3
27192 */
27193#define DDRPHY_DX4GCR6_DXDQVREFR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX4GCR6_DXDQVREFR3_MASK)
27194#define DDRPHY_DX4GCR6_RESERVED_31_30_MASK (0xC0000000U)
27195#define DDRPHY_DX4GCR6_RESERVED_31_30_SHIFT (30U)
27196/*! RESERVED_31_30 - Reserved. Returns zeros on reads.
27197 */
27198#define DDRPHY_DX4GCR6_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX4GCR6_RESERVED_31_30_MASK)
27199/*! @} */
27200
27201/*! @name DX4GCR7 - DATX8 n General Configuration Register 7 */
27202/*! @{ */
27203#define DDRPHY_DX4GCR7_DCALSVAL_MASK (0x1FFU)
27204#define DDRPHY_DX4GCR7_DCALSVAL_SHIFT (0U)
27205/*! DCALSVAL - DDL Calibration Starting Value
27206 */
27207#define DDRPHY_DX4GCR7_DCALSVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX4GCR7_DCALSVAL_MASK)
27208#define DDRPHY_DX4GCR7_DCALTYPE_MASK (0x200U)
27209#define DDRPHY_DX4GCR7_DCALTYPE_SHIFT (9U)
27210/*! DCALTYPE - DDL Calibration Type
27211 */
27212#define DDRPHY_DX4GCR7_DCALTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX4GCR7_DCALTYPE_MASK)
27213#define DDRPHY_DX4GCR7_RESERVED_17_10_MASK (0x3FC00U)
27214#define DDRPHY_DX4GCR7_RESERVED_17_10_SHIFT (10U)
27215/*! RESERVED_17_10 - Reserved. Caution, do not write to this register field.
27216 */
27217#define DDRPHY_DX4GCR7_RESERVED_17_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX4GCR7_RESERVED_17_10_MASK)
27218#define DDRPHY_DX4GCR7_RESERVED_18_MASK (0x40000U)
27219#define DDRPHY_DX4GCR7_RESERVED_18_SHIFT (18U)
27220/*! RESERVED_18 - Reserved. Caution, do not write to this register field.
27221 */
27222#define DDRPHY_DX4GCR7_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX4GCR7_RESERVED_18_MASK)
27223#define DDRPHY_DX4GCR7_RESERVED_31_19_MASK (0xFFF80000U)
27224#define DDRPHY_DX4GCR7_RESERVED_31_19_SHIFT (19U)
27225/*! RESERVED_31_19 - Reserved. Caution, do not write to this register field.
27226 */
27227#define DDRPHY_DX4GCR7_RESERVED_31_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX4GCR7_RESERVED_31_19_MASK)
27228/*! @} */
27229
27230/*! @name DX4GCR8 - DATX8 n General Configuration Register 8 */
27231/*! @{ */
27232#define DDRPHY_DX4GCR8_RESERVED_5_0_MASK (0x3FU)
27233#define DDRPHY_DX4GCR8_RESERVED_5_0_SHIFT (0U)
27234/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
27235 */
27236#define DDRPHY_DX4GCR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_5_0_MASK)
27237#define DDRPHY_DX4GCR8_RESERVED_7_6_MASK (0xC0U)
27238#define DDRPHY_DX4GCR8_RESERVED_7_6_SHIFT (6U)
27239/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
27240 */
27241#define DDRPHY_DX4GCR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_7_6_MASK)
27242#define DDRPHY_DX4GCR8_RESERVED_13_8_MASK (0x3F00U)
27243#define DDRPHY_DX4GCR8_RESERVED_13_8_SHIFT (8U)
27244/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
27245 */
27246#define DDRPHY_DX4GCR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_13_8_MASK)
27247#define DDRPHY_DX4GCR8_RESERVED_15_14_MASK (0xC000U)
27248#define DDRPHY_DX4GCR8_RESERVED_15_14_SHIFT (14U)
27249/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27250 */
27251#define DDRPHY_DX4GCR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_15_14_MASK)
27252#define DDRPHY_DX4GCR8_RESERVED_21_16_MASK (0x3F0000U)
27253#define DDRPHY_DX4GCR8_RESERVED_21_16_SHIFT (16U)
27254/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
27255 */
27256#define DDRPHY_DX4GCR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_21_16_MASK)
27257#define DDRPHY_DX4GCR8_RESERVED_23_22_MASK (0xC00000U)
27258#define DDRPHY_DX4GCR8_RESERVED_23_22_SHIFT (22U)
27259/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
27260 */
27261#define DDRPHY_DX4GCR8_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_23_22_MASK)
27262#define DDRPHY_DX4GCR8_RESERVED_29_24_MASK (0x3F000000U)
27263#define DDRPHY_DX4GCR8_RESERVED_29_24_SHIFT (24U)
27264/*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
27265 */
27266#define DDRPHY_DX4GCR8_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_29_24_MASK)
27267#define DDRPHY_DX4GCR8_RESERVED_31_30_MASK (0xC0000000U)
27268#define DDRPHY_DX4GCR8_RESERVED_31_30_SHIFT (30U)
27269/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
27270 */
27271#define DDRPHY_DX4GCR8_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX4GCR8_RESERVED_31_30_MASK)
27272/*! @} */
27273
27274/*! @name DX4GCR9 - DATX8 n General Configuration Register 9 */
27275/*! @{ */
27276#define DDRPHY_DX4GCR9_RESERVED_5_0_MASK (0x3FU)
27277#define DDRPHY_DX4GCR9_RESERVED_5_0_SHIFT (0U)
27278/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
27279 */
27280#define DDRPHY_DX4GCR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_5_0_MASK)
27281#define DDRPHY_DX4GCR9_RESERVED_7_6_MASK (0xC0U)
27282#define DDRPHY_DX4GCR9_RESERVED_7_6_SHIFT (6U)
27283/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
27284 */
27285#define DDRPHY_DX4GCR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_7_6_MASK)
27286#define DDRPHY_DX4GCR9_RESERVED_13_8_MASK (0x3F00U)
27287#define DDRPHY_DX4GCR9_RESERVED_13_8_SHIFT (8U)
27288/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
27289 */
27290#define DDRPHY_DX4GCR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_13_8_MASK)
27291#define DDRPHY_DX4GCR9_RESERVED_15_14_MASK (0xC000U)
27292#define DDRPHY_DX4GCR9_RESERVED_15_14_SHIFT (14U)
27293/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27294 */
27295#define DDRPHY_DX4GCR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_15_14_MASK)
27296#define DDRPHY_DX4GCR9_RESERVED_21_16_MASK (0x3F0000U)
27297#define DDRPHY_DX4GCR9_RESERVED_21_16_SHIFT (16U)
27298/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
27299 */
27300#define DDRPHY_DX4GCR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_21_16_MASK)
27301#define DDRPHY_DX4GCR9_RESERVED_23_22_MASK (0xC00000U)
27302#define DDRPHY_DX4GCR9_RESERVED_23_22_SHIFT (22U)
27303/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
27304 */
27305#define DDRPHY_DX4GCR9_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_23_22_MASK)
27306#define DDRPHY_DX4GCR9_RESERVED_29_24_MASK (0x3F000000U)
27307#define DDRPHY_DX4GCR9_RESERVED_29_24_SHIFT (24U)
27308/*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
27309 */
27310#define DDRPHY_DX4GCR9_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_29_24_MASK)
27311#define DDRPHY_DX4GCR9_RESERVED_31_30_MASK (0xC0000000U)
27312#define DDRPHY_DX4GCR9_RESERVED_31_30_SHIFT (30U)
27313/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
27314 */
27315#define DDRPHY_DX4GCR9_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX4GCR9_RESERVED_31_30_MASK)
27316/*! @} */
27317
27318/*! @name DX4DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */
27319/*! @{ */
27320#define DDRPHY_DX4DQMAP0_DQ0MAP_MASK (0xFU)
27321#define DDRPHY_DX4DQMAP0_DQ0MAP_SHIFT (0U)
27322/*! DQ0MAP - DQ bit 0 DATX8 slice mapping index
27323 */
27324#define DDRPHY_DX4DQMAP0_DQ0MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX4DQMAP0_DQ0MAP_MASK)
27325#define DDRPHY_DX4DQMAP0_DQ1MAP_MASK (0xF0U)
27326#define DDRPHY_DX4DQMAP0_DQ1MAP_SHIFT (4U)
27327/*! DQ1MAP - DQ bit 1 DATX8 slice mapping index
27328 */
27329#define DDRPHY_DX4DQMAP0_DQ1MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX4DQMAP0_DQ1MAP_MASK)
27330#define DDRPHY_DX4DQMAP0_DQ2MAP_MASK (0xF00U)
27331#define DDRPHY_DX4DQMAP0_DQ2MAP_SHIFT (8U)
27332/*! DQ2MAP - DQ bit 2 DATX8 slice mapping index
27333 */
27334#define DDRPHY_DX4DQMAP0_DQ2MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX4DQMAP0_DQ2MAP_MASK)
27335#define DDRPHY_DX4DQMAP0_DQ3MAP_MASK (0xF000U)
27336#define DDRPHY_DX4DQMAP0_DQ3MAP_SHIFT (12U)
27337/*! DQ3MAP - DQ bit 3 DATX8 slice mapping index
27338 */
27339#define DDRPHY_DX4DQMAP0_DQ3MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX4DQMAP0_DQ3MAP_MASK)
27340#define DDRPHY_DX4DQMAP0_DQ4MAP_MASK (0xF0000U)
27341#define DDRPHY_DX4DQMAP0_DQ4MAP_SHIFT (16U)
27342/*! DQ4MAP - DQ bit 4 DATX8 slice mapping index
27343 */
27344#define DDRPHY_DX4DQMAP0_DQ4MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX4DQMAP0_DQ4MAP_MASK)
27345#define DDRPHY_DX4DQMAP0_RESERVED_30_20_MASK (0x7FF00000U)
27346#define DDRPHY_DX4DQMAP0_RESERVED_30_20_SHIFT (20U)
27347/*! RESERVED_30_20 - Reserved. Return zeroes on reads.
27348 */
27349#define DDRPHY_DX4DQMAP0_RESERVED_30_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX4DQMAP0_RESERVED_30_20_MASK)
27350#define DDRPHY_DX4DQMAP0_MAPOK_MASK (0x80000000U)
27351#define DDRPHY_DX4DQMAP0_MAPOK_SHIFT (31U)
27352/*! MAPOK - Checksum bit
27353 */
27354#define DDRPHY_DX4DQMAP0_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX4DQMAP0_MAPOK_MASK)
27355/*! @} */
27356
27357/*! @name DX4DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */
27358/*! @{ */
27359#define DDRPHY_DX4DQMAP1_DQ5MAP_MASK (0xFU)
27360#define DDRPHY_DX4DQMAP1_DQ5MAP_SHIFT (0U)
27361/*! DQ5MAP - DQ bit 5 DATX8 slice mapping index
27362 */
27363#define DDRPHY_DX4DQMAP1_DQ5MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX4DQMAP1_DQ5MAP_MASK)
27364#define DDRPHY_DX4DQMAP1_DQ6MAP_MASK (0xF0U)
27365#define DDRPHY_DX4DQMAP1_DQ6MAP_SHIFT (4U)
27366/*! DQ6MAP - DQ bit 6 DATX8 slice mapping index
27367 */
27368#define DDRPHY_DX4DQMAP1_DQ6MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX4DQMAP1_DQ6MAP_MASK)
27369#define DDRPHY_DX4DQMAP1_DQ7MAP_MASK (0xF00U)
27370#define DDRPHY_DX4DQMAP1_DQ7MAP_SHIFT (8U)
27371/*! DQ7MAP - DQ bit 7 DATX8 slice mapping index
27372 */
27373#define DDRPHY_DX4DQMAP1_DQ7MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX4DQMAP1_DQ7MAP_MASK)
27374#define DDRPHY_DX4DQMAP1_DMMAP_MASK (0xF000U)
27375#define DDRPHY_DX4DQMAP1_DMMAP_SHIFT (12U)
27376/*! DMMAP - DM bit DATX8 slice mapping index
27377 */
27378#define DDRPHY_DX4DQMAP1_DMMAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX4DQMAP1_DMMAP_MASK)
27379#define DDRPHY_DX4DQMAP1_RESERVED_30_16_MASK (0x7FFF0000U)
27380#define DDRPHY_DX4DQMAP1_RESERVED_30_16_SHIFT (16U)
27381/*! RESERVED_30_16 - Reserved. Return zeroes on reads.
27382 */
27383#define DDRPHY_DX4DQMAP1_RESERVED_30_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX4DQMAP1_RESERVED_30_16_MASK)
27384#define DDRPHY_DX4DQMAP1_MAPOK_MASK (0x80000000U)
27385#define DDRPHY_DX4DQMAP1_MAPOK_SHIFT (31U)
27386/*! MAPOK - Checksum bit
27387 */
27388#define DDRPHY_DX4DQMAP1_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX4DQMAP1_MAPOK_MASK)
27389/*! @} */
27390
27391/*! @name DX4BDLR0 - DATX8 n Bit Delay Line Register 0 */
27392/*! @{ */
27393#define DDRPHY_DX4BDLR0_DQ0WBD_MASK (0x3FU)
27394#define DDRPHY_DX4BDLR0_DQ0WBD_SHIFT (0U)
27395/*! DQ0WBD - DQ0 Write Bit Delay
27396 */
27397#define DDRPHY_DX4BDLR0_DQ0WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX4BDLR0_DQ0WBD_MASK)
27398#define DDRPHY_DX4BDLR0_RESERVED_7_6_MASK (0xC0U)
27399#define DDRPHY_DX4BDLR0_RESERVED_7_6_SHIFT (6U)
27400/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
27401 */
27402#define DDRPHY_DX4BDLR0_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR0_RESERVED_7_6_MASK)
27403#define DDRPHY_DX4BDLR0_DQ1WBD_MASK (0x3F00U)
27404#define DDRPHY_DX4BDLR0_DQ1WBD_SHIFT (8U)
27405/*! DQ1WBD - DQ1 Write Bit Delay
27406 */
27407#define DDRPHY_DX4BDLR0_DQ1WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX4BDLR0_DQ1WBD_MASK)
27408#define DDRPHY_DX4BDLR0_RESERVED_15_14_MASK (0xC000U)
27409#define DDRPHY_DX4BDLR0_RESERVED_15_14_SHIFT (14U)
27410/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27411 */
27412#define DDRPHY_DX4BDLR0_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR0_RESERVED_15_14_MASK)
27413#define DDRPHY_DX4BDLR0_DQ2WBD_MASK (0x3F0000U)
27414#define DDRPHY_DX4BDLR0_DQ2WBD_SHIFT (16U)
27415/*! DQ2WBD - DQ2 Write Bit Delay
27416 */
27417#define DDRPHY_DX4BDLR0_DQ2WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX4BDLR0_DQ2WBD_MASK)
27418#define DDRPHY_DX4BDLR0_RESERVED_23_22_MASK (0xC00000U)
27419#define DDRPHY_DX4BDLR0_RESERVED_23_22_SHIFT (22U)
27420/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
27421 */
27422#define DDRPHY_DX4BDLR0_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX4BDLR0_RESERVED_23_22_MASK)
27423#define DDRPHY_DX4BDLR0_DQ3WBD_MASK (0x3F000000U)
27424#define DDRPHY_DX4BDLR0_DQ3WBD_SHIFT (24U)
27425/*! DQ3WBD - DQ3 Write Bit Delay
27426 */
27427#define DDRPHY_DX4BDLR0_DQ3WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX4BDLR0_DQ3WBD_MASK)
27428#define DDRPHY_DX4BDLR0_RESERVED_31_30_MASK (0xC0000000U)
27429#define DDRPHY_DX4BDLR0_RESERVED_31_30_SHIFT (30U)
27430/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
27431 */
27432#define DDRPHY_DX4BDLR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX4BDLR0_RESERVED_31_30_MASK)
27433/*! @} */
27434
27435/*! @name DX4BDLR1 - DATX8 n Bit Delay Line Register 1 */
27436/*! @{ */
27437#define DDRPHY_DX4BDLR1_DQ4WBD_MASK (0x3FU)
27438#define DDRPHY_DX4BDLR1_DQ4WBD_SHIFT (0U)
27439/*! DQ4WBD - DQ4 Write Bit Delay
27440 */
27441#define DDRPHY_DX4BDLR1_DQ4WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX4BDLR1_DQ4WBD_MASK)
27442#define DDRPHY_DX4BDLR1_RESERVED_7_6_MASK (0xC0U)
27443#define DDRPHY_DX4BDLR1_RESERVED_7_6_SHIFT (6U)
27444/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
27445 */
27446#define DDRPHY_DX4BDLR1_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR1_RESERVED_7_6_MASK)
27447#define DDRPHY_DX4BDLR1_DQ5WBD_MASK (0x3F00U)
27448#define DDRPHY_DX4BDLR1_DQ5WBD_SHIFT (8U)
27449/*! DQ5WBD - DQ5 Write Bit Delay
27450 */
27451#define DDRPHY_DX4BDLR1_DQ5WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX4BDLR1_DQ5WBD_MASK)
27452#define DDRPHY_DX4BDLR1_RESERVED_15_14_MASK (0xC000U)
27453#define DDRPHY_DX4BDLR1_RESERVED_15_14_SHIFT (14U)
27454/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27455 */
27456#define DDRPHY_DX4BDLR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR1_RESERVED_15_14_MASK)
27457#define DDRPHY_DX4BDLR1_DQ6WBD_MASK (0x3F0000U)
27458#define DDRPHY_DX4BDLR1_DQ6WBD_SHIFT (16U)
27459/*! DQ6WBD - DQ6 Write Bit Delay
27460 */
27461#define DDRPHY_DX4BDLR1_DQ6WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX4BDLR1_DQ6WBD_MASK)
27462#define DDRPHY_DX4BDLR1_RESERVED_23_22_MASK (0xC00000U)
27463#define DDRPHY_DX4BDLR1_RESERVED_23_22_SHIFT (22U)
27464/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
27465 */
27466#define DDRPHY_DX4BDLR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX4BDLR1_RESERVED_23_22_MASK)
27467#define DDRPHY_DX4BDLR1_DQ7WBD_MASK (0x3F000000U)
27468#define DDRPHY_DX4BDLR1_DQ7WBD_SHIFT (24U)
27469/*! DQ7WBD - DQ7 Write Bit Delay
27470 */
27471#define DDRPHY_DX4BDLR1_DQ7WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX4BDLR1_DQ7WBD_MASK)
27472#define DDRPHY_DX4BDLR1_RESERVED_31_30_MASK (0xC0000000U)
27473#define DDRPHY_DX4BDLR1_RESERVED_31_30_SHIFT (30U)
27474/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
27475 */
27476#define DDRPHY_DX4BDLR1_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX4BDLR1_RESERVED_31_30_MASK)
27477/*! @} */
27478
27479/*! @name DX4BDLR2 - DATX8 n Bit Delay Line Register 2 */
27480/*! @{ */
27481#define DDRPHY_DX4BDLR2_DMWBD_MASK (0x3FU)
27482#define DDRPHY_DX4BDLR2_DMWBD_SHIFT (0U)
27483/*! DMWBD - DM Write Bit Delay
27484 */
27485#define DDRPHY_DX4BDLR2_DMWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_DMWBD_SHIFT)) & DDRPHY_DX4BDLR2_DMWBD_MASK)
27486#define DDRPHY_DX4BDLR2_RESERVED_7_6_MASK (0xC0U)
27487#define DDRPHY_DX4BDLR2_RESERVED_7_6_SHIFT (6U)
27488/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
27489 */
27490#define DDRPHY_DX4BDLR2_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR2_RESERVED_7_6_MASK)
27491#define DDRPHY_DX4BDLR2_DSWBD_MASK (0x3F00U)
27492#define DDRPHY_DX4BDLR2_DSWBD_SHIFT (8U)
27493/*! DSWBD - DQS Write Bit Delay
27494 */
27495#define DDRPHY_DX4BDLR2_DSWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_DSWBD_SHIFT)) & DDRPHY_DX4BDLR2_DSWBD_MASK)
27496#define DDRPHY_DX4BDLR2_RESERVED_15_14_MASK (0xC000U)
27497#define DDRPHY_DX4BDLR2_RESERVED_15_14_SHIFT (14U)
27498/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27499 */
27500#define DDRPHY_DX4BDLR2_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR2_RESERVED_15_14_MASK)
27501#define DDRPHY_DX4BDLR2_DSOEBD_MASK (0x3F0000U)
27502#define DDRPHY_DX4BDLR2_DSOEBD_SHIFT (16U)
27503/*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay
27504 */
27505#define DDRPHY_DX4BDLR2_DSOEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX4BDLR2_DSOEBD_MASK)
27506#define DDRPHY_DX4BDLR2_RESERVED_23_22_MASK (0xC00000U)
27507#define DDRPHY_DX4BDLR2_RESERVED_23_22_SHIFT (22U)
27508/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
27509 */
27510#define DDRPHY_DX4BDLR2_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX4BDLR2_RESERVED_23_22_MASK)
27511#define DDRPHY_DX4BDLR2_DSNWBD_MASK (0x3F000000U)
27512#define DDRPHY_DX4BDLR2_DSNWBD_SHIFT (24U)
27513/*! DSNWBD - DQSN Write Bit Delay
27514 */
27515#define DDRPHY_DX4BDLR2_DSNWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX4BDLR2_DSNWBD_MASK)
27516#define DDRPHY_DX4BDLR2_RESERVED_31_30_MASK (0xC0000000U)
27517#define DDRPHY_DX4BDLR2_RESERVED_31_30_SHIFT (30U)
27518/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
27519 */
27520#define DDRPHY_DX4BDLR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX4BDLR2_RESERVED_31_30_MASK)
27521/*! @} */
27522
27523/*! @name DX4BDLR3 - DATX8 n Bit Delay Line Register 3 */
27524/*! @{ */
27525#define DDRPHY_DX4BDLR3_DQ0RBD_MASK (0x3FU)
27526#define DDRPHY_DX4BDLR3_DQ0RBD_SHIFT (0U)
27527/*! DQ0RBD - DQ0 Read Bit Delay
27528 */
27529#define DDRPHY_DX4BDLR3_DQ0RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX4BDLR3_DQ0RBD_MASK)
27530#define DDRPHY_DX4BDLR3_RESERVED_7_6_MASK (0xC0U)
27531#define DDRPHY_DX4BDLR3_RESERVED_7_6_SHIFT (6U)
27532/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
27533 */
27534#define DDRPHY_DX4BDLR3_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR3_RESERVED_7_6_MASK)
27535#define DDRPHY_DX4BDLR3_DQ1RBD_MASK (0x3F00U)
27536#define DDRPHY_DX4BDLR3_DQ1RBD_SHIFT (8U)
27537/*! DQ1RBD - DQ1 Read Bit Delay
27538 */
27539#define DDRPHY_DX4BDLR3_DQ1RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX4BDLR3_DQ1RBD_MASK)
27540#define DDRPHY_DX4BDLR3_RESERVED_15_14_MASK (0xC000U)
27541#define DDRPHY_DX4BDLR3_RESERVED_15_14_SHIFT (14U)
27542/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27543 */
27544#define DDRPHY_DX4BDLR3_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR3_RESERVED_15_14_MASK)
27545#define DDRPHY_DX4BDLR3_DQ2RBD_MASK (0x3F0000U)
27546#define DDRPHY_DX4BDLR3_DQ2RBD_SHIFT (16U)
27547/*! DQ2RBD - DQ2 Read Bit Delay
27548 */
27549#define DDRPHY_DX4BDLR3_DQ2RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX4BDLR3_DQ2RBD_MASK)
27550#define DDRPHY_DX4BDLR3_RESERVED_23_22_MASK (0xC00000U)
27551#define DDRPHY_DX4BDLR3_RESERVED_23_22_SHIFT (22U)
27552/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
27553 */
27554#define DDRPHY_DX4BDLR3_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX4BDLR3_RESERVED_23_22_MASK)
27555#define DDRPHY_DX4BDLR3_DQ3RBD_MASK (0x3F000000U)
27556#define DDRPHY_DX4BDLR3_DQ3RBD_SHIFT (24U)
27557/*! DQ3RBD - DQ3 Read Bit Delay
27558 */
27559#define DDRPHY_DX4BDLR3_DQ3RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX4BDLR3_DQ3RBD_MASK)
27560#define DDRPHY_DX4BDLR3_RESERVED_31_30_MASK (0xC0000000U)
27561#define DDRPHY_DX4BDLR3_RESERVED_31_30_SHIFT (30U)
27562/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
27563 */
27564#define DDRPHY_DX4BDLR3_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX4BDLR3_RESERVED_31_30_MASK)
27565/*! @} */
27566
27567/*! @name DX4BDLR4 - DATX8 n Bit Delay Line Register 4 */
27568/*! @{ */
27569#define DDRPHY_DX4BDLR4_DQ4RBD_MASK (0x3FU)
27570#define DDRPHY_DX4BDLR4_DQ4RBD_SHIFT (0U)
27571/*! DQ4RBD - DQ4 Read Bit Delay
27572 */
27573#define DDRPHY_DX4BDLR4_DQ4RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX4BDLR4_DQ4RBD_MASK)
27574#define DDRPHY_DX4BDLR4_RESERVED_7_6_MASK (0xC0U)
27575#define DDRPHY_DX4BDLR4_RESERVED_7_6_SHIFT (6U)
27576/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
27577 */
27578#define DDRPHY_DX4BDLR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR4_RESERVED_7_6_MASK)
27579#define DDRPHY_DX4BDLR4_DQ5RBD_MASK (0x3F00U)
27580#define DDRPHY_DX4BDLR4_DQ5RBD_SHIFT (8U)
27581/*! DQ5RBD - DQ5 Read Bit Delay
27582 */
27583#define DDRPHY_DX4BDLR4_DQ5RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX4BDLR4_DQ5RBD_MASK)
27584#define DDRPHY_DX4BDLR4_RESERVED_15_14_MASK (0xC000U)
27585#define DDRPHY_DX4BDLR4_RESERVED_15_14_SHIFT (14U)
27586/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27587 */
27588#define DDRPHY_DX4BDLR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR4_RESERVED_15_14_MASK)
27589#define DDRPHY_DX4BDLR4_DQ6RBD_MASK (0x3F0000U)
27590#define DDRPHY_DX4BDLR4_DQ6RBD_SHIFT (16U)
27591/*! DQ6RBD - DQ6 Read Bit Delay
27592 */
27593#define DDRPHY_DX4BDLR4_DQ6RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX4BDLR4_DQ6RBD_MASK)
27594#define DDRPHY_DX4BDLR4_RESERVED_23_22_MASK (0xC00000U)
27595#define DDRPHY_DX4BDLR4_RESERVED_23_22_SHIFT (22U)
27596/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
27597 */
27598#define DDRPHY_DX4BDLR4_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX4BDLR4_RESERVED_23_22_MASK)
27599#define DDRPHY_DX4BDLR4_DQ7RBD_MASK (0x3F000000U)
27600#define DDRPHY_DX4BDLR4_DQ7RBD_SHIFT (24U)
27601/*! DQ7RBD - DQ7 Read Bit Delay
27602 */
27603#define DDRPHY_DX4BDLR4_DQ7RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX4BDLR4_DQ7RBD_MASK)
27604#define DDRPHY_DX4BDLR4_RESERVED_31_30_MASK (0xC0000000U)
27605#define DDRPHY_DX4BDLR4_RESERVED_31_30_SHIFT (30U)
27606/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
27607 */
27608#define DDRPHY_DX4BDLR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX4BDLR4_RESERVED_31_30_MASK)
27609/*! @} */
27610
27611/*! @name DX4BDLR5 - DATX8 n Bit Delay Line Register 5 */
27612/*! @{ */
27613#define DDRPHY_DX4BDLR5_DMRBD_MASK (0x3FU)
27614#define DDRPHY_DX4BDLR5_DMRBD_SHIFT (0U)
27615/*! DMRBD - DM Read Bit Delay
27616 */
27617#define DDRPHY_DX4BDLR5_DMRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR5_DMRBD_SHIFT)) & DDRPHY_DX4BDLR5_DMRBD_MASK)
27618#define DDRPHY_DX4BDLR5_RESERVED_31_6_MASK (0xFFFFFFC0U)
27619#define DDRPHY_DX4BDLR5_RESERVED_31_6_SHIFT (6U)
27620/*! RESERVED_31_6 - Reserved. Return zeroes on reads.
27621 */
27622#define DDRPHY_DX4BDLR5_RESERVED_31_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX4BDLR5_RESERVED_31_6_MASK)
27623/*! @} */
27624
27625/*! @name DX4BDLR6 - DATX8 n Bit Delay Line Register 6 */
27626/*! @{ */
27627#define DDRPHY_DX4BDLR6_RESERVED_7_0_MASK (0xFFU)
27628#define DDRPHY_DX4BDLR6_RESERVED_7_0_SHIFT (0U)
27629/*! RESERVED_7_0 - Reserved. Return zeroes on reads.
27630 */
27631#define DDRPHY_DX4BDLR6_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX4BDLR6_RESERVED_7_0_MASK)
27632#define DDRPHY_DX4BDLR6_PDRBD_MASK (0x3F00U)
27633#define DDRPHY_DX4BDLR6_PDRBD_SHIFT (8U)
27634/*! PDRBD - Power down receiver Bit Delay
27635 */
27636#define DDRPHY_DX4BDLR6_PDRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR6_PDRBD_SHIFT)) & DDRPHY_DX4BDLR6_PDRBD_MASK)
27637#define DDRPHY_DX4BDLR6_RESERVED_15_14_MASK (0xC000U)
27638#define DDRPHY_DX4BDLR6_RESERVED_15_14_SHIFT (14U)
27639/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27640 */
27641#define DDRPHY_DX4BDLR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR6_RESERVED_15_14_MASK)
27642#define DDRPHY_DX4BDLR6_TERBD_MASK (0x3F0000U)
27643#define DDRPHY_DX4BDLR6_TERBD_SHIFT (16U)
27644/*! TERBD - Termination Enable Bit Delay
27645 */
27646#define DDRPHY_DX4BDLR6_TERBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR6_TERBD_SHIFT)) & DDRPHY_DX4BDLR6_TERBD_MASK)
27647#define DDRPHY_DX4BDLR6_RESERVED_31_22_MASK (0xFFC00000U)
27648#define DDRPHY_DX4BDLR6_RESERVED_31_22_SHIFT (22U)
27649/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
27650 */
27651#define DDRPHY_DX4BDLR6_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX4BDLR6_RESERVED_31_22_MASK)
27652/*! @} */
27653
27654/*! @name DX4BDLR7 - DATX8 n Bit Delay Line Register 7 */
27655/*! @{ */
27656#define DDRPHY_DX4BDLR7_RESERVED_5_0_MASK (0x3FU)
27657#define DDRPHY_DX4BDLR7_RESERVED_5_0_SHIFT (0U)
27658/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
27659 */
27660#define DDRPHY_DX4BDLR7_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX4BDLR7_RESERVED_5_0_MASK)
27661#define DDRPHY_DX4BDLR7_RESERVED_7_6_MASK (0xC0U)
27662#define DDRPHY_DX4BDLR7_RESERVED_7_6_SHIFT (6U)
27663/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
27664 */
27665#define DDRPHY_DX4BDLR7_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR7_RESERVED_7_6_MASK)
27666#define DDRPHY_DX4BDLR7_RESERVED_13_8_MASK (0x3F00U)
27667#define DDRPHY_DX4BDLR7_RESERVED_13_8_SHIFT (8U)
27668/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
27669 */
27670#define DDRPHY_DX4BDLR7_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX4BDLR7_RESERVED_13_8_MASK)
27671#define DDRPHY_DX4BDLR7_RESERVED_15_14_MASK (0xC000U)
27672#define DDRPHY_DX4BDLR7_RESERVED_15_14_SHIFT (14U)
27673/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27674 */
27675#define DDRPHY_DX4BDLR7_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR7_RESERVED_15_14_MASK)
27676#define DDRPHY_DX4BDLR7_RESERVED_21_16_MASK (0x3F0000U)
27677#define DDRPHY_DX4BDLR7_RESERVED_21_16_SHIFT (16U)
27678/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
27679 */
27680#define DDRPHY_DX4BDLR7_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX4BDLR7_RESERVED_21_16_MASK)
27681#define DDRPHY_DX4BDLR7_RESERVED_31_22_MASK (0xFFC00000U)
27682#define DDRPHY_DX4BDLR7_RESERVED_31_22_SHIFT (22U)
27683/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
27684 */
27685#define DDRPHY_DX4BDLR7_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX4BDLR7_RESERVED_31_22_MASK)
27686/*! @} */
27687
27688/*! @name DX4BDLR8 - DATX8 n Bit Delay Line Register 8 */
27689/*! @{ */
27690#define DDRPHY_DX4BDLR8_RESERVED_5_0_MASK (0x3FU)
27691#define DDRPHY_DX4BDLR8_RESERVED_5_0_SHIFT (0U)
27692/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
27693 */
27694#define DDRPHY_DX4BDLR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX4BDLR8_RESERVED_5_0_MASK)
27695#define DDRPHY_DX4BDLR8_RESERVED_7_6_MASK (0xC0U)
27696#define DDRPHY_DX4BDLR8_RESERVED_7_6_SHIFT (6U)
27697/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
27698 */
27699#define DDRPHY_DX4BDLR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR8_RESERVED_7_6_MASK)
27700#define DDRPHY_DX4BDLR8_RESERVED_13_8_MASK (0x3F00U)
27701#define DDRPHY_DX4BDLR8_RESERVED_13_8_SHIFT (8U)
27702/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
27703 */
27704#define DDRPHY_DX4BDLR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX4BDLR8_RESERVED_13_8_MASK)
27705#define DDRPHY_DX4BDLR8_RESERVED_15_14_MASK (0xC000U)
27706#define DDRPHY_DX4BDLR8_RESERVED_15_14_SHIFT (14U)
27707/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27708 */
27709#define DDRPHY_DX4BDLR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR8_RESERVED_15_14_MASK)
27710#define DDRPHY_DX4BDLR8_RESERVED_21_16_MASK (0x3F0000U)
27711#define DDRPHY_DX4BDLR8_RESERVED_21_16_SHIFT (16U)
27712/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
27713 */
27714#define DDRPHY_DX4BDLR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX4BDLR8_RESERVED_21_16_MASK)
27715#define DDRPHY_DX4BDLR8_RESERVED_31_22_MASK (0xFFC00000U)
27716#define DDRPHY_DX4BDLR8_RESERVED_31_22_SHIFT (22U)
27717/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
27718 */
27719#define DDRPHY_DX4BDLR8_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX4BDLR8_RESERVED_31_22_MASK)
27720/*! @} */
27721
27722/*! @name DX4BDLR9 - DATX8 n Bit Delay Line Register 9 */
27723/*! @{ */
27724#define DDRPHY_DX4BDLR9_RESERVED_5_0_MASK (0x3FU)
27725#define DDRPHY_DX4BDLR9_RESERVED_5_0_SHIFT (0U)
27726/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
27727 */
27728#define DDRPHY_DX4BDLR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX4BDLR9_RESERVED_5_0_MASK)
27729#define DDRPHY_DX4BDLR9_RESERVED_7_6_MASK (0xC0U)
27730#define DDRPHY_DX4BDLR9_RESERVED_7_6_SHIFT (6U)
27731/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
27732 */
27733#define DDRPHY_DX4BDLR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX4BDLR9_RESERVED_7_6_MASK)
27734#define DDRPHY_DX4BDLR9_RESERVED_13_8_MASK (0x3F00U)
27735#define DDRPHY_DX4BDLR9_RESERVED_13_8_SHIFT (8U)
27736/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
27737 */
27738#define DDRPHY_DX4BDLR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX4BDLR9_RESERVED_13_8_MASK)
27739#define DDRPHY_DX4BDLR9_RESERVED_15_14_MASK (0xC000U)
27740#define DDRPHY_DX4BDLR9_RESERVED_15_14_SHIFT (14U)
27741/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
27742 */
27743#define DDRPHY_DX4BDLR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX4BDLR9_RESERVED_15_14_MASK)
27744#define DDRPHY_DX4BDLR9_RESERVED_21_16_MASK (0x3F0000U)
27745#define DDRPHY_DX4BDLR9_RESERVED_21_16_SHIFT (16U)
27746/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
27747 */
27748#define DDRPHY_DX4BDLR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX4BDLR9_RESERVED_21_16_MASK)
27749#define DDRPHY_DX4BDLR9_RESERVED_31_22_MASK (0xFFC00000U)
27750#define DDRPHY_DX4BDLR9_RESERVED_31_22_SHIFT (22U)
27751/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
27752 */
27753#define DDRPHY_DX4BDLR9_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX4BDLR9_RESERVED_31_22_MASK)
27754/*! @} */
27755
27756/*! @name DX4LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */
27757/*! @{ */
27758#define DDRPHY_DX4LCDLR0_WLD_MASK (0x1FFU)
27759#define DDRPHY_DX4LCDLR0_WLD_SHIFT (0U)
27760/*! WLD - Write Leveling Delay
27761 */
27762#define DDRPHY_DX4LCDLR0_WLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR0_WLD_SHIFT)) & DDRPHY_DX4LCDLR0_WLD_MASK)
27763#define DDRPHY_DX4LCDLR0_RESERVED_15_9_MASK (0xFE00U)
27764#define DDRPHY_DX4LCDLR0_RESERVED_15_9_SHIFT (9U)
27765/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
27766 */
27767#define DDRPHY_DX4LCDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX4LCDLR0_RESERVED_15_9_MASK)
27768#define DDRPHY_DX4LCDLR0_RESERVED_24_16_MASK (0x1FF0000U)
27769#define DDRPHY_DX4LCDLR0_RESERVED_24_16_SHIFT (16U)
27770/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
27771 */
27772#define DDRPHY_DX4LCDLR0_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX4LCDLR0_RESERVED_24_16_MASK)
27773#define DDRPHY_DX4LCDLR0_RESERVED_31_25_MASK (0xFE000000U)
27774#define DDRPHY_DX4LCDLR0_RESERVED_31_25_SHIFT (25U)
27775/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
27776 */
27777#define DDRPHY_DX4LCDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX4LCDLR0_RESERVED_31_25_MASK)
27778/*! @} */
27779
27780/*! @name DX4LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */
27781/*! @{ */
27782#define DDRPHY_DX4LCDLR1_WDQD_MASK (0x1FFU)
27783#define DDRPHY_DX4LCDLR1_WDQD_SHIFT (0U)
27784/*! WDQD - Write Data Delay
27785 */
27786#define DDRPHY_DX4LCDLR1_WDQD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR1_WDQD_SHIFT)) & DDRPHY_DX4LCDLR1_WDQD_MASK)
27787#define DDRPHY_DX4LCDLR1_RESERVED_15_9_MASK (0xFE00U)
27788#define DDRPHY_DX4LCDLR1_RESERVED_15_9_SHIFT (9U)
27789/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
27790 */
27791#define DDRPHY_DX4LCDLR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX4LCDLR1_RESERVED_15_9_MASK)
27792#define DDRPHY_DX4LCDLR1_RESERVED_24_16_MASK (0x1FF0000U)
27793#define DDRPHY_DX4LCDLR1_RESERVED_24_16_SHIFT (16U)
27794/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
27795 */
27796#define DDRPHY_DX4LCDLR1_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX4LCDLR1_RESERVED_24_16_MASK)
27797#define DDRPHY_DX4LCDLR1_RESERVED_31_25_MASK (0xFE000000U)
27798#define DDRPHY_DX4LCDLR1_RESERVED_31_25_SHIFT (25U)
27799/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
27800 */
27801#define DDRPHY_DX4LCDLR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX4LCDLR1_RESERVED_31_25_MASK)
27802/*! @} */
27803
27804/*! @name DX4LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */
27805/*! @{ */
27806#define DDRPHY_DX4LCDLR2_DQSGD_MASK (0x1FFU)
27807#define DDRPHY_DX4LCDLR2_DQSGD_SHIFT (0U)
27808/*! DQSGD - Read DQS Gating Delay
27809 */
27810#define DDRPHY_DX4LCDLR2_DQSGD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX4LCDLR2_DQSGD_MASK)
27811#define DDRPHY_DX4LCDLR2_RESERVED_15_9_MASK (0xFE00U)
27812#define DDRPHY_DX4LCDLR2_RESERVED_15_9_SHIFT (9U)
27813/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
27814 */
27815#define DDRPHY_DX4LCDLR2_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX4LCDLR2_RESERVED_15_9_MASK)
27816#define DDRPHY_DX4LCDLR2_RESERVED_24_16_MASK (0x1FF0000U)
27817#define DDRPHY_DX4LCDLR2_RESERVED_24_16_SHIFT (16U)
27818/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
27819 */
27820#define DDRPHY_DX4LCDLR2_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX4LCDLR2_RESERVED_24_16_MASK)
27821#define DDRPHY_DX4LCDLR2_RESERVED_31_25_MASK (0xFE000000U)
27822#define DDRPHY_DX4LCDLR2_RESERVED_31_25_SHIFT (25U)
27823/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
27824 */
27825#define DDRPHY_DX4LCDLR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX4LCDLR2_RESERVED_31_25_MASK)
27826/*! @} */
27827
27828/*! @name DX4LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */
27829/*! @{ */
27830#define DDRPHY_DX4LCDLR3_RDQSD_MASK (0x1FFU)
27831#define DDRPHY_DX4LCDLR3_RDQSD_SHIFT (0U)
27832/*! RDQSD - Read DQS Delay
27833 */
27834#define DDRPHY_DX4LCDLR3_RDQSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX4LCDLR3_RDQSD_MASK)
27835#define DDRPHY_DX4LCDLR3_RESERVED_15_9_MASK (0xFE00U)
27836#define DDRPHY_DX4LCDLR3_RESERVED_15_9_SHIFT (9U)
27837/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
27838 */
27839#define DDRPHY_DX4LCDLR3_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX4LCDLR3_RESERVED_15_9_MASK)
27840#define DDRPHY_DX4LCDLR3_RESERVED_24_16_MASK (0x1FF0000U)
27841#define DDRPHY_DX4LCDLR3_RESERVED_24_16_SHIFT (16U)
27842/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
27843 */
27844#define DDRPHY_DX4LCDLR3_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX4LCDLR3_RESERVED_24_16_MASK)
27845#define DDRPHY_DX4LCDLR3_RESERVED_31_25_MASK (0xFE000000U)
27846#define DDRPHY_DX4LCDLR3_RESERVED_31_25_SHIFT (25U)
27847/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
27848 */
27849#define DDRPHY_DX4LCDLR3_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX4LCDLR3_RESERVED_31_25_MASK)
27850/*! @} */
27851
27852/*! @name DX4LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */
27853/*! @{ */
27854#define DDRPHY_DX4LCDLR4_RDQSND_MASK (0x1FFU)
27855#define DDRPHY_DX4LCDLR4_RDQSND_SHIFT (0U)
27856/*! RDQSND - Read DQSN Delay
27857 */
27858#define DDRPHY_DX4LCDLR4_RDQSND(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX4LCDLR4_RDQSND_MASK)
27859#define DDRPHY_DX4LCDLR4_RESERVED_15_9_MASK (0xFE00U)
27860#define DDRPHY_DX4LCDLR4_RESERVED_15_9_SHIFT (9U)
27861/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
27862 */
27863#define DDRPHY_DX4LCDLR4_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX4LCDLR4_RESERVED_15_9_MASK)
27864#define DDRPHY_DX4LCDLR4_RESERVED_24_16_MASK (0x1FF0000U)
27865#define DDRPHY_DX4LCDLR4_RESERVED_24_16_SHIFT (16U)
27866/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
27867 */
27868#define DDRPHY_DX4LCDLR4_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX4LCDLR4_RESERVED_24_16_MASK)
27869#define DDRPHY_DX4LCDLR4_RESERVED_31_25_MASK (0xFE000000U)
27870#define DDRPHY_DX4LCDLR4_RESERVED_31_25_SHIFT (25U)
27871/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
27872 */
27873#define DDRPHY_DX4LCDLR4_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX4LCDLR4_RESERVED_31_25_MASK)
27874/*! @} */
27875
27876/*! @name DX4LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */
27877/*! @{ */
27878#define DDRPHY_DX4LCDLR5_DQSGSD_MASK (0x1FFU)
27879#define DDRPHY_DX4LCDLR5_DQSGSD_SHIFT (0U)
27880/*! DQSGSD - DQS Gating Status Delay
27881 */
27882#define DDRPHY_DX4LCDLR5_DQSGSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX4LCDLR5_DQSGSD_MASK)
27883#define DDRPHY_DX4LCDLR5_RESERVED_15_9_MASK (0xFE00U)
27884#define DDRPHY_DX4LCDLR5_RESERVED_15_9_SHIFT (9U)
27885/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
27886 */
27887#define DDRPHY_DX4LCDLR5_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX4LCDLR5_RESERVED_15_9_MASK)
27888#define DDRPHY_DX4LCDLR5_RESERVED_24_16_MASK (0x1FF0000U)
27889#define DDRPHY_DX4LCDLR5_RESERVED_24_16_SHIFT (16U)
27890/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
27891 */
27892#define DDRPHY_DX4LCDLR5_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX4LCDLR5_RESERVED_24_16_MASK)
27893#define DDRPHY_DX4LCDLR5_RESERVED_31_25_MASK (0xFE000000U)
27894#define DDRPHY_DX4LCDLR5_RESERVED_31_25_SHIFT (25U)
27895/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
27896 */
27897#define DDRPHY_DX4LCDLR5_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX4LCDLR5_RESERVED_31_25_MASK)
27898/*! @} */
27899
27900/*! @name DX4MDLR0 - DATX8 n Master Delay Line Register 0 */
27901/*! @{ */
27902#define DDRPHY_DX4MDLR0_IPRD_MASK (0x1FFU)
27903#define DDRPHY_DX4MDLR0_IPRD_SHIFT (0U)
27904/*! IPRD - Initial Period
27905 */
27906#define DDRPHY_DX4MDLR0_IPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4MDLR0_IPRD_SHIFT)) & DDRPHY_DX4MDLR0_IPRD_MASK)
27907#define DDRPHY_DX4MDLR0_RESERVED_15_9_MASK (0xFE00U)
27908#define DDRPHY_DX4MDLR0_RESERVED_15_9_SHIFT (9U)
27909/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
27910 */
27911#define DDRPHY_DX4MDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX4MDLR0_RESERVED_15_9_MASK)
27912#define DDRPHY_DX4MDLR0_TPRD_MASK (0x1FF0000U)
27913#define DDRPHY_DX4MDLR0_TPRD_SHIFT (16U)
27914/*! TPRD - Target Period
27915 */
27916#define DDRPHY_DX4MDLR0_TPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4MDLR0_TPRD_SHIFT)) & DDRPHY_DX4MDLR0_TPRD_MASK)
27917#define DDRPHY_DX4MDLR0_RESERVED_31_25_MASK (0xFE000000U)
27918#define DDRPHY_DX4MDLR0_RESERVED_31_25_SHIFT (25U)
27919/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
27920 */
27921#define DDRPHY_DX4MDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX4MDLR0_RESERVED_31_25_MASK)
27922/*! @} */
27923
27924/*! @name DX4MDLR1 - DATX8 n Master Delay Line Register 1 */
27925/*! @{ */
27926#define DDRPHY_DX4MDLR1_MDLD_MASK (0x1FFU)
27927#define DDRPHY_DX4MDLR1_MDLD_SHIFT (0U)
27928/*! MDLD - MDL Delay
27929 */
27930#define DDRPHY_DX4MDLR1_MDLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4MDLR1_MDLD_SHIFT)) & DDRPHY_DX4MDLR1_MDLD_MASK)
27931#define DDRPHY_DX4MDLR1_RESERVED_31_9_MASK (0xFFFFFE00U)
27932#define DDRPHY_DX4MDLR1_RESERVED_31_9_SHIFT (9U)
27933/*! RESERVED_31_9 - Reserved. Return zeroes on reads.
27934 */
27935#define DDRPHY_DX4MDLR1_RESERVED_31_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX4MDLR1_RESERVED_31_9_MASK)
27936/*! @} */
27937
27938/*! @name DX4GTR0 - DATX8 n General Timing Register 0 */
27939/*! @{ */
27940#define DDRPHY_DX4GTR0_DGSL_MASK (0x1FU)
27941#define DDRPHY_DX4GTR0_DGSL_SHIFT (0U)
27942/*! DGSL - DQS Gating System Latency
27943 */
27944#define DDRPHY_DX4GTR0_DGSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_DGSL_SHIFT)) & DDRPHY_DX4GTR0_DGSL_MASK)
27945#define DDRPHY_DX4GTR0_RESERVED_7_5_MASK (0xE0U)
27946#define DDRPHY_DX4GTR0_RESERVED_7_5_SHIFT (5U)
27947/*! RESERVED_7_5 - Reserved. Return zeroes on reads.
27948 */
27949#define DDRPHY_DX4GTR0_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX4GTR0_RESERVED_7_5_MASK)
27950#define DDRPHY_DX4GTR0_RESERVED_12_8_MASK (0x1F00U)
27951#define DDRPHY_DX4GTR0_RESERVED_12_8_SHIFT (8U)
27952/*! RESERVED_12_8 - Reserved. Caution, do not write to this register field.
27953 */
27954#define DDRPHY_DX4GTR0_RESERVED_12_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX4GTR0_RESERVED_12_8_MASK)
27955#define DDRPHY_DX4GTR0_RESERVED_15_13_MASK (0xE000U)
27956#define DDRPHY_DX4GTR0_RESERVED_15_13_SHIFT (13U)
27957/*! RESERVED_15_13 - Reserved. Return zeroes on reads.
27958 */
27959#define DDRPHY_DX4GTR0_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX4GTR0_RESERVED_15_13_MASK)
27960#define DDRPHY_DX4GTR0_WLSL_MASK (0xF0000U)
27961#define DDRPHY_DX4GTR0_WLSL_SHIFT (16U)
27962/*! WLSL - Write Leveling System Latency
27963 */
27964#define DDRPHY_DX4GTR0_WLSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_WLSL_SHIFT)) & DDRPHY_DX4GTR0_WLSL_MASK)
27965#define DDRPHY_DX4GTR0_RESERVED_23_20_MASK (0xF00000U)
27966#define DDRPHY_DX4GTR0_RESERVED_23_20_SHIFT (20U)
27967/*! RESERVED_23_20 - Reserved. Caution, do not write to this register field.
27968 */
27969#define DDRPHY_DX4GTR0_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX4GTR0_RESERVED_23_20_MASK)
27970#define DDRPHY_DX4GTR0_WDQSL_MASK (0x7000000U)
27971#define DDRPHY_DX4GTR0_WDQSL_SHIFT (24U)
27972/*! WDQSL - DQ Write Path Latency Pipeline
27973 */
27974#define DDRPHY_DX4GTR0_WDQSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_WDQSL_SHIFT)) & DDRPHY_DX4GTR0_WDQSL_MASK)
27975#define DDRPHY_DX4GTR0_RESERVED_31_24_MASK (0xF8000000U)
27976#define DDRPHY_DX4GTR0_RESERVED_31_24_SHIFT (27U)
27977/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
27978 */
27979#define DDRPHY_DX4GTR0_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX4GTR0_RESERVED_31_24_MASK)
27980/*! @} */
27981
27982/*! @name DX4RSR0 - DATX8 n Rank Status Register 0 */
27983/*! @{ */
27984#define DDRPHY_DX4RSR0_QSGERR_MASK (0xFFFFU)
27985#define DDRPHY_DX4RSR0_QSGERR_SHIFT (0U)
27986/*! QSGERR - DQS Gate Training Error
27987 */
27988#define DDRPHY_DX4RSR0_QSGERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR0_QSGERR_SHIFT)) & DDRPHY_DX4RSR0_QSGERR_MASK)
27989#define DDRPHY_DX4RSR0_RESERVED_31_16_MASK (0xFFFF0000U)
27990#define DDRPHY_DX4RSR0_RESERVED_31_16_SHIFT (16U)
27991/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
27992 */
27993#define DDRPHY_DX4RSR0_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX4RSR0_RESERVED_31_16_MASK)
27994/*! @} */
27995
27996/*! @name DX4RSR1 - DATX8 n Rank Status Register 1 */
27997/*! @{ */
27998#define DDRPHY_DX4RSR1_RDLVLERR_MASK (0xFFFFU)
27999#define DDRPHY_DX4RSR1_RDLVLERR_SHIFT (0U)
28000/*! RDLVLERR - Read Leveling Error
28001 */
28002#define DDRPHY_DX4RSR1_RDLVLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX4RSR1_RDLVLERR_MASK)
28003#define DDRPHY_DX4RSR1_RESERVED_31_16_MASK (0xFFFF0000U)
28004#define DDRPHY_DX4RSR1_RESERVED_31_16_SHIFT (16U)
28005/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
28006 */
28007#define DDRPHY_DX4RSR1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX4RSR1_RESERVED_31_16_MASK)
28008/*! @} */
28009
28010/*! @name DX4RSR2 - DATX8 n Rank Status Register 2 */
28011/*! @{ */
28012#define DDRPHY_DX4RSR2_WLAWN_MASK (0xFFFFU)
28013#define DDRPHY_DX4RSR2_WLAWN_SHIFT (0U)
28014/*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning
28015 */
28016#define DDRPHY_DX4RSR2_WLAWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR2_WLAWN_SHIFT)) & DDRPHY_DX4RSR2_WLAWN_MASK)
28017#define DDRPHY_DX4RSR2_RESERVED_31_16_MASK (0xFFFF0000U)
28018#define DDRPHY_DX4RSR2_RESERVED_31_16_SHIFT (16U)
28019/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
28020 */
28021#define DDRPHY_DX4RSR2_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX4RSR2_RESERVED_31_16_MASK)
28022/*! @} */
28023
28024/*! @name DX4RSR3 - DATX8 n Rank Status Register 3 */
28025/*! @{ */
28026#define DDRPHY_DX4RSR3_WLAERR_MASK (0xFFFFU)
28027#define DDRPHY_DX4RSR3_WLAERR_SHIFT (0U)
28028/*! WLAERR - Write Leveling Adjustment Error
28029 */
28030#define DDRPHY_DX4RSR3_WLAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR3_WLAERR_SHIFT)) & DDRPHY_DX4RSR3_WLAERR_MASK)
28031#define DDRPHY_DX4RSR3_RESERVED_31_16_MASK (0xFFFF0000U)
28032#define DDRPHY_DX4RSR3_RESERVED_31_16_SHIFT (16U)
28033/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
28034 */
28035#define DDRPHY_DX4RSR3_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX4RSR3_RESERVED_31_16_MASK)
28036/*! @} */
28037
28038/*! @name DX4GSR0 - DATX8 n General Status Register 0 */
28039/*! @{ */
28040#define DDRPHY_DX4GSR0_WDQCAL_MASK (0x1U)
28041#define DDRPHY_DX4GSR0_WDQCAL_SHIFT (0U)
28042/*! WDQCAL - Write DQ Calibration
28043 */
28044#define DDRPHY_DX4GSR0_WDQCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_WDQCAL_SHIFT)) & DDRPHY_DX4GSR0_WDQCAL_MASK)
28045#define DDRPHY_DX4GSR0_RDQSCAL_MASK (0x2U)
28046#define DDRPHY_DX4GSR0_RDQSCAL_SHIFT (1U)
28047/*! RDQSCAL - Read DQS Calibration
28048 */
28049#define DDRPHY_DX4GSR0_RDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX4GSR0_RDQSCAL_MASK)
28050#define DDRPHY_DX4GSR0_RDQSNCAL_MASK (0x4U)
28051#define DDRPHY_DX4GSR0_RDQSNCAL_SHIFT (2U)
28052/*! RDQSNCAL - Read DQS# Calibration
28053 */
28054#define DDRPHY_DX4GSR0_RDQSNCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX4GSR0_RDQSNCAL_MASK)
28055#define DDRPHY_DX4GSR0_GDQSCAL_MASK (0x8U)
28056#define DDRPHY_DX4GSR0_GDQSCAL_SHIFT (3U)
28057/*! GDQSCAL - Read DQS gating Calibration
28058 */
28059#define DDRPHY_DX4GSR0_GDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX4GSR0_GDQSCAL_MASK)
28060#define DDRPHY_DX4GSR0_WLCAL_MASK (0x10U)
28061#define DDRPHY_DX4GSR0_WLCAL_SHIFT (4U)
28062/*! WLCAL - Write Leveling Calibration
28063 */
28064#define DDRPHY_DX4GSR0_WLCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_WLCAL_SHIFT)) & DDRPHY_DX4GSR0_WLCAL_MASK)
28065#define DDRPHY_DX4GSR0_WLDONE_MASK (0x20U)
28066#define DDRPHY_DX4GSR0_WLDONE_SHIFT (5U)
28067/*! WLDONE - Write Leveling Done
28068 */
28069#define DDRPHY_DX4GSR0_WLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_WLDONE_SHIFT)) & DDRPHY_DX4GSR0_WLDONE_MASK)
28070#define DDRPHY_DX4GSR0_WLERR_MASK (0x40U)
28071#define DDRPHY_DX4GSR0_WLERR_SHIFT (6U)
28072/*! WLERR - Write Leveling Error
28073 */
28074#define DDRPHY_DX4GSR0_WLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_WLERR_SHIFT)) & DDRPHY_DX4GSR0_WLERR_MASK)
28075#define DDRPHY_DX4GSR0_WLPRD_MASK (0xFF80U)
28076#define DDRPHY_DX4GSR0_WLPRD_SHIFT (7U)
28077/*! WLPRD - Write Leveling Period
28078 */
28079#define DDRPHY_DX4GSR0_WLPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_WLPRD_SHIFT)) & DDRPHY_DX4GSR0_WLPRD_MASK)
28080#define DDRPHY_DX4GSR0_DPLOCK_MASK (0x10000U)
28081#define DDRPHY_DX4GSR0_DPLOCK_SHIFT (16U)
28082/*! DPLOCK - DATX8 PLL Lock
28083 */
28084#define DDRPHY_DX4GSR0_DPLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_DPLOCK_SHIFT)) & DDRPHY_DX4GSR0_DPLOCK_MASK)
28085#define DDRPHY_DX4GSR0_GDQSPRD_MASK (0x3FE0000U)
28086#define DDRPHY_DX4GSR0_GDQSPRD_SHIFT (17U)
28087/*! GDQSPRD - Read DQS gating Period
28088 */
28089#define DDRPHY_DX4GSR0_GDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX4GSR0_GDQSPRD_MASK)
28090#define DDRPHY_DX4GSR0_RESERVED_29_26_MASK (0x3C000000U)
28091#define DDRPHY_DX4GSR0_RESERVED_29_26_SHIFT (26U)
28092/*! RESERVED_29_26 - Reserved. Returns zeroes on reads.
28093 */
28094#define DDRPHY_DX4GSR0_RESERVED_29_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX4GSR0_RESERVED_29_26_MASK)
28095#define DDRPHY_DX4GSR0_WLDQ_MASK (0x40000000U)
28096#define DDRPHY_DX4GSR0_WLDQ_SHIFT (30U)
28097/*! WLDQ - Write Leveling DQ Status
28098 */
28099#define DDRPHY_DX4GSR0_WLDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_WLDQ_SHIFT)) & DDRPHY_DX4GSR0_WLDQ_MASK)
28100#define DDRPHY_DX4GSR0_RESERVED_31_MASK (0x80000000U)
28101#define DDRPHY_DX4GSR0_RESERVED_31_SHIFT (31U)
28102/*! RESERVED_31 - Reserved. Returns zeroes on reads.
28103 */
28104#define DDRPHY_DX4GSR0_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX4GSR0_RESERVED_31_MASK)
28105/*! @} */
28106
28107/*! @name DX4GSR1 - DATX8 n General Status Register 1 */
28108/*! @{ */
28109#define DDRPHY_DX4GSR1_DLTDONE_MASK (0x1U)
28110#define DDRPHY_DX4GSR1_DLTDONE_SHIFT (0U)
28111/*! DLTDONE - Delay Line Test Done
28112 */
28113#define DDRPHY_DX4GSR1_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR1_DLTDONE_SHIFT)) & DDRPHY_DX4GSR1_DLTDONE_MASK)
28114#define DDRPHY_DX4GSR1_DLTCODE_MASK (0x1FFFFFEU)
28115#define DDRPHY_DX4GSR1_DLTCODE_SHIFT (1U)
28116/*! DLTCODE - Delay Line Test Code
28117 */
28118#define DDRPHY_DX4GSR1_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR1_DLTCODE_SHIFT)) & DDRPHY_DX4GSR1_DLTCODE_MASK)
28119#define DDRPHY_DX4GSR1_RESERVED_31_25_MASK (0xFE000000U)
28120#define DDRPHY_DX4GSR1_RESERVED_31_25_SHIFT (25U)
28121/*! RESERVED_31_25 - Reserved. Returns zeroes on reads.
28122 */
28123#define DDRPHY_DX4GSR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX4GSR1_RESERVED_31_25_MASK)
28124/*! @} */
28125
28126/*! @name DX4GSR2 - DATX8 n General Status Register 2 */
28127/*! @{ */
28128#define DDRPHY_DX4GSR2_RDERR_MASK (0x1U)
28129#define DDRPHY_DX4GSR2_RDERR_SHIFT (0U)
28130/*! RDERR - Read Bit Deskew Error
28131 */
28132#define DDRPHY_DX4GSR2_RDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_RDERR_SHIFT)) & DDRPHY_DX4GSR2_RDERR_MASK)
28133#define DDRPHY_DX4GSR2_RDWN_MASK (0x2U)
28134#define DDRPHY_DX4GSR2_RDWN_SHIFT (1U)
28135/*! RDWN - Read Bit Deskew Warning
28136 */
28137#define DDRPHY_DX4GSR2_RDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_RDWN_SHIFT)) & DDRPHY_DX4GSR2_RDWN_MASK)
28138#define DDRPHY_DX4GSR2_WDERR_MASK (0x4U)
28139#define DDRPHY_DX4GSR2_WDERR_SHIFT (2U)
28140/*! WDERR - Write Bit Deskew Error
28141 */
28142#define DDRPHY_DX4GSR2_WDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_WDERR_SHIFT)) & DDRPHY_DX4GSR2_WDERR_MASK)
28143#define DDRPHY_DX4GSR2_WDWN_MASK (0x8U)
28144#define DDRPHY_DX4GSR2_WDWN_SHIFT (3U)
28145/*! WDWN - Write Bit Deskew Warning
28146 */
28147#define DDRPHY_DX4GSR2_WDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_WDWN_SHIFT)) & DDRPHY_DX4GSR2_WDWN_MASK)
28148#define DDRPHY_DX4GSR2_REERR_MASK (0x10U)
28149#define DDRPHY_DX4GSR2_REERR_SHIFT (4U)
28150/*! REERR - Read Eye Centering Error
28151 */
28152#define DDRPHY_DX4GSR2_REERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_REERR_SHIFT)) & DDRPHY_DX4GSR2_REERR_MASK)
28153#define DDRPHY_DX4GSR2_REWN_MASK (0x20U)
28154#define DDRPHY_DX4GSR2_REWN_SHIFT (5U)
28155/*! REWN - Read Eye Centering Warning
28156 */
28157#define DDRPHY_DX4GSR2_REWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_REWN_SHIFT)) & DDRPHY_DX4GSR2_REWN_MASK)
28158#define DDRPHY_DX4GSR2_WEERR_MASK (0x40U)
28159#define DDRPHY_DX4GSR2_WEERR_SHIFT (6U)
28160/*! WEERR - Write Eye Centering Error
28161 */
28162#define DDRPHY_DX4GSR2_WEERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_WEERR_SHIFT)) & DDRPHY_DX4GSR2_WEERR_MASK)
28163#define DDRPHY_DX4GSR2_WEWN_MASK (0x80U)
28164#define DDRPHY_DX4GSR2_WEWN_SHIFT (7U)
28165/*! WEWN - Write Eye Centering Warning
28166 */
28167#define DDRPHY_DX4GSR2_WEWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_WEWN_SHIFT)) & DDRPHY_DX4GSR2_WEWN_MASK)
28168#define DDRPHY_DX4GSR2_ESTAT_MASK (0xF00U)
28169#define DDRPHY_DX4GSR2_ESTAT_SHIFT (8U)
28170/*! ESTAT - Error Status
28171 */
28172#define DDRPHY_DX4GSR2_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_ESTAT_SHIFT)) & DDRPHY_DX4GSR2_ESTAT_MASK)
28173#define DDRPHY_DX4GSR2_DQS2DQERR_MASK (0xFF000U)
28174#define DDRPHY_DX4GSR2_DQS2DQERR_SHIFT (12U)
28175/*! DQS2DQERR - Write DQS2DQ Training Error
28176 */
28177#define DDRPHY_DX4GSR2_DQS2DQERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX4GSR2_DQS2DQERR_MASK)
28178#define DDRPHY_DX4GSR2_SRDERR_MASK (0x100000U)
28179#define DDRPHY_DX4GSR2_SRDERR_SHIFT (20U)
28180/*! SRDERR - Static Read Error
28181 */
28182#define DDRPHY_DX4GSR2_SRDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_SRDERR_SHIFT)) & DDRPHY_DX4GSR2_SRDERR_MASK)
28183#define DDRPHY_DX4GSR2_RESERVED_21_MASK (0x200000U)
28184#define DDRPHY_DX4GSR2_RESERVED_21_SHIFT (21U)
28185/*! RESERVED_21 - Reserved. Return zeroes on reads.
28186 */
28187#define DDRPHY_DX4GSR2_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX4GSR2_RESERVED_21_MASK)
28188#define DDRPHY_DX4GSR2_GSDQSCAL_MASK (0x400000U)
28189#define DDRPHY_DX4GSR2_GSDQSCAL_SHIFT (22U)
28190/*! GSDQSCAL - Read DQS Gating Status Calibration
28191 */
28192#define DDRPHY_DX4GSR2_GSDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX4GSR2_GSDQSCAL_MASK)
28193#define DDRPHY_DX4GSR2_GSDQSPRD_MASK (0xFF800000U)
28194#define DDRPHY_DX4GSR2_GSDQSPRD_SHIFT (23U)
28195/*! GSDQSPRD - Read DQS gating Status Period
28196 */
28197#define DDRPHY_DX4GSR2_GSDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX4GSR2_GSDQSPRD_MASK)
28198/*! @} */
28199
28200/*! @name DX4GSR3 - DATX8 n General Status Register 3 */
28201/*! @{ */
28202#define DDRPHY_DX4GSR3_SRDPC_MASK (0x3U)
28203#define DDRPHY_DX4GSR3_SRDPC_SHIFT (0U)
28204/*! SRDPC - Static Read Delay Pass Count
28205 */
28206#define DDRPHY_DX4GSR3_SRDPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_SRDPC_SHIFT)) & DDRPHY_DX4GSR3_SRDPC_MASK)
28207#define DDRPHY_DX4GSR3_RESERVED_7_2_MASK (0xFCU)
28208#define DDRPHY_DX4GSR3_RESERVED_7_2_SHIFT (2U)
28209/*! RESERVED_7_2 - Reserved. Return zeroes on reads.
28210 */
28211#define DDRPHY_DX4GSR3_RESERVED_7_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX4GSR3_RESERVED_7_2_MASK)
28212#define DDRPHY_DX4GSR3_HVERR_MASK (0xF00U)
28213#define DDRPHY_DX4GSR3_HVERR_SHIFT (8U)
28214/*! HVERR - Host VREF Training Error
28215 */
28216#define DDRPHY_DX4GSR3_HVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_HVERR_SHIFT)) & DDRPHY_DX4GSR3_HVERR_MASK)
28217#define DDRPHY_DX4GSR3_HVWRN_MASK (0xF000U)
28218#define DDRPHY_DX4GSR3_HVWRN_SHIFT (12U)
28219/*! HVWRN - Host VREF Training Warning
28220 */
28221#define DDRPHY_DX4GSR3_HVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_HVWRN_SHIFT)) & DDRPHY_DX4GSR3_HVWRN_MASK)
28222#define DDRPHY_DX4GSR3_DVERR_MASK (0xF0000U)
28223#define DDRPHY_DX4GSR3_DVERR_SHIFT (16U)
28224/*! DVERR - DRAM VREF Training Error
28225 */
28226#define DDRPHY_DX4GSR3_DVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_DVERR_SHIFT)) & DDRPHY_DX4GSR3_DVERR_MASK)
28227#define DDRPHY_DX4GSR3_DVWRN_MASK (0xF00000U)
28228#define DDRPHY_DX4GSR3_DVWRN_SHIFT (20U)
28229/*! DVWRN - DRAM VREF Training Warning
28230 */
28231#define DDRPHY_DX4GSR3_DVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_DVWRN_SHIFT)) & DDRPHY_DX4GSR3_DVWRN_MASK)
28232#define DDRPHY_DX4GSR3_ESTAT_MASK (0x7000000U)
28233#define DDRPHY_DX4GSR3_ESTAT_SHIFT (24U)
28234/*! ESTAT - VREF Training Error Status Code
28235 */
28236#define DDRPHY_DX4GSR3_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_ESTAT_SHIFT)) & DDRPHY_DX4GSR3_ESTAT_MASK)
28237#define DDRPHY_DX4GSR3_RESERVED_31_27_MASK (0xF8000000U)
28238#define DDRPHY_DX4GSR3_RESERVED_31_27_SHIFT (27U)
28239/*! RESERVED_31_27 - Reserved. Return zeroes on reads.
28240 */
28241#define DDRPHY_DX4GSR3_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX4GSR3_RESERVED_31_27_MASK)
28242/*! @} */
28243
28244/*! @name DX4GSR4 - DATX8 n General Status Register 4 */
28245/*! @{ */
28246#define DDRPHY_DX4GSR4_RESERVED_0_MASK (0x1U)
28247#define DDRPHY_DX4GSR4_RESERVED_0_SHIFT (0U)
28248/*! RESERVED_0 - Reserved. Return zeroes on reads.
28249 */
28250#define DDRPHY_DX4GSR4_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_0_MASK)
28251#define DDRPHY_DX4GSR4_RESERVED_1_MASK (0x2U)
28252#define DDRPHY_DX4GSR4_RESERVED_1_SHIFT (1U)
28253/*! RESERVED_1 - Reserved. Return zeroes on reads.
28254 */
28255#define DDRPHY_DX4GSR4_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_1_MASK)
28256#define DDRPHY_DX4GSR4_RESERVED_2_MASK (0x4U)
28257#define DDRPHY_DX4GSR4_RESERVED_2_SHIFT (2U)
28258/*! RESERVED_2 - Reserved. Return zeroes on reads.
28259 */
28260#define DDRPHY_DX4GSR4_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_2_MASK)
28261#define DDRPHY_DX4GSR4_RESERVED_3_MASK (0x8U)
28262#define DDRPHY_DX4GSR4_RESERVED_3_SHIFT (3U)
28263/*! RESERVED_3 - Reserved. Return zeroes on reads.
28264 */
28265#define DDRPHY_DX4GSR4_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_3_MASK)
28266#define DDRPHY_DX4GSR4_RESERVED_4_MASK (0x10U)
28267#define DDRPHY_DX4GSR4_RESERVED_4_SHIFT (4U)
28268/*! RESERVED_4 - Reserved. Return zeroes on reads.
28269 */
28270#define DDRPHY_DX4GSR4_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_4_MASK)
28271#define DDRPHY_DX4GSR4_RESERVED_5_MASK (0x20U)
28272#define DDRPHY_DX4GSR4_RESERVED_5_SHIFT (5U)
28273/*! RESERVED_5 - Reserved. Return zeroes on reads.
28274 */
28275#define DDRPHY_DX4GSR4_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_5_MASK)
28276#define DDRPHY_DX4GSR4_RESERVED_6_MASK (0x40U)
28277#define DDRPHY_DX4GSR4_RESERVED_6_SHIFT (6U)
28278/*! RESERVED_6 - Reserved. Return zeroes on reads.
28279 */
28280#define DDRPHY_DX4GSR4_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_6_MASK)
28281#define DDRPHY_DX4GSR4_RESERVED_15_7_MASK (0xFF80U)
28282#define DDRPHY_DX4GSR4_RESERVED_15_7_SHIFT (7U)
28283/*! RESERVED_15_7 - Reserved. Return zeroes on reads.
28284 */
28285#define DDRPHY_DX4GSR4_RESERVED_15_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_15_7_MASK)
28286#define DDRPHY_DX4GSR4_RESERVED_16_MASK (0x10000U)
28287#define DDRPHY_DX4GSR4_RESERVED_16_SHIFT (16U)
28288/*! RESERVED_16 - Reserved. Return zeroes on reads.
28289 */
28290#define DDRPHY_DX4GSR4_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_16_MASK)
28291#define DDRPHY_DX4GSR4_RESERVED_25_17_MASK (0x3FE0000U)
28292#define DDRPHY_DX4GSR4_RESERVED_25_17_SHIFT (17U)
28293/*! RESERVED_25_17 - Reserved. Return zeroes on reads.
28294 */
28295#define DDRPHY_DX4GSR4_RESERVED_25_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_25_17_MASK)
28296#define DDRPHY_DX4GSR4_RESERVED_31_26_MASK (0xFC000000U)
28297#define DDRPHY_DX4GSR4_RESERVED_31_26_SHIFT (26U)
28298/*! RESERVED_31_26 - Reserved. Returns zeroes on reads.
28299 */
28300#define DDRPHY_DX4GSR4_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX4GSR4_RESERVED_31_26_MASK)
28301/*! @} */
28302
28303/*! @name DX4GSR5 - DATX8 n General Status Register 5 */
28304/*! @{ */
28305#define DDRPHY_DX4GSR5_RESERVED_0_MASK (0x1U)
28306#define DDRPHY_DX4GSR5_RESERVED_0_SHIFT (0U)
28307/*! RESERVED_0 - Reserved. Return zeroes on reads.
28308 */
28309#define DDRPHY_DX4GSR5_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_0_MASK)
28310#define DDRPHY_DX4GSR5_RESERVED_1_MASK (0x2U)
28311#define DDRPHY_DX4GSR5_RESERVED_1_SHIFT (1U)
28312/*! RESERVED_1 - Reserved. Return zeroes on reads.
28313 */
28314#define DDRPHY_DX4GSR5_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_1_MASK)
28315#define DDRPHY_DX4GSR5_RESERVED_2_MASK (0x4U)
28316#define DDRPHY_DX4GSR5_RESERVED_2_SHIFT (2U)
28317/*! RESERVED_2 - Reserved. Return zeroes on reads.
28318 */
28319#define DDRPHY_DX4GSR5_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_2_MASK)
28320#define DDRPHY_DX4GSR5_RESERVED_3_MASK (0x8U)
28321#define DDRPHY_DX4GSR5_RESERVED_3_SHIFT (3U)
28322/*! RESERVED_3 - Reserved. Return zeroes on reads.
28323 */
28324#define DDRPHY_DX4GSR5_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_3_MASK)
28325#define DDRPHY_DX4GSR5_RESERVED_4_MASK (0x10U)
28326#define DDRPHY_DX4GSR5_RESERVED_4_SHIFT (4U)
28327/*! RESERVED_4 - Reserved. Return zeroes on reads.
28328 */
28329#define DDRPHY_DX4GSR5_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_4_MASK)
28330#define DDRPHY_DX4GSR5_RESERVED_5_MASK (0x20U)
28331#define DDRPHY_DX4GSR5_RESERVED_5_SHIFT (5U)
28332/*! RESERVED_5 - Reserved. Return zeroes on reads.
28333 */
28334#define DDRPHY_DX4GSR5_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_5_MASK)
28335#define DDRPHY_DX4GSR5_RESERVED_6_MASK (0x40U)
28336#define DDRPHY_DX4GSR5_RESERVED_6_SHIFT (6U)
28337/*! RESERVED_6 - Reserved. Return zeroes on reads.
28338 */
28339#define DDRPHY_DX4GSR5_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_6_MASK)
28340#define DDRPHY_DX4GSR5_RESERVED_7_MASK (0x80U)
28341#define DDRPHY_DX4GSR5_RESERVED_7_SHIFT (7U)
28342/*! RESERVED_7 - Reserved. Return zeroes on reads.
28343 */
28344#define DDRPHY_DX4GSR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_7_MASK)
28345#define DDRPHY_DX4GSR5_RESERVED_11_8_MASK (0xF00U)
28346#define DDRPHY_DX4GSR5_RESERVED_11_8_SHIFT (8U)
28347/*! RESERVED_11_8 - Reserved. Return zeroes on reads.
28348 */
28349#define DDRPHY_DX4GSR5_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_11_8_MASK)
28350#define DDRPHY_DX4GSR5_RESERVED_19_12_MASK (0xFF000U)
28351#define DDRPHY_DX4GSR5_RESERVED_19_12_SHIFT (12U)
28352/*! RESERVED_19_12 - Reserved. Return zeroes on reads.
28353 */
28354#define DDRPHY_DX4GSR5_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_19_12_MASK)
28355#define DDRPHY_DX4GSR5_RESERVED_20_MASK (0x100000U)
28356#define DDRPHY_DX4GSR5_RESERVED_20_SHIFT (20U)
28357/*! RESERVED_20 - Reserved. Return zeroes on reads.
28358 */
28359#define DDRPHY_DX4GSR5_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_20_MASK)
28360#define DDRPHY_DX4GSR5_RESERVED_21_MASK (0x200000U)
28361#define DDRPHY_DX4GSR5_RESERVED_21_SHIFT (21U)
28362/*! RESERVED_21 - Reserved. Return zeroes on reads.
28363 */
28364#define DDRPHY_DX4GSR5_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_21_MASK)
28365#define DDRPHY_DX4GSR5_RESERVED_22_MASK (0x400000U)
28366#define DDRPHY_DX4GSR5_RESERVED_22_SHIFT (22U)
28367/*! RESERVED_22 - Reserved. Return zeroes on reads.
28368 */
28369#define DDRPHY_DX4GSR5_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_22_MASK)
28370#define DDRPHY_DX4GSR5_RESERVED_31_23_MASK (0xFF800000U)
28371#define DDRPHY_DX4GSR5_RESERVED_31_23_SHIFT (23U)
28372/*! RESERVED_31_23 - Reserved. Return zeroes on reads.
28373 */
28374#define DDRPHY_DX4GSR5_RESERVED_31_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX4GSR5_RESERVED_31_23_MASK)
28375/*! @} */
28376
28377/*! @name DX4GSR6 - DATX8 n General Status Register 6 */
28378/*! @{ */
28379#define DDRPHY_DX4GSR6_RESERVED_1_0_MASK (0x3U)
28380#define DDRPHY_DX4GSR6_RESERVED_1_0_SHIFT (0U)
28381/*! RESERVED_1_0 - Reserved. Return zeroes on reads.
28382 */
28383#define DDRPHY_DX4GSR6_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_1_0_MASK)
28384#define DDRPHY_DX4GSR6_RESERVED_3_2_MASK (0xCU)
28385#define DDRPHY_DX4GSR6_RESERVED_3_2_SHIFT (2U)
28386/*! RESERVED_3_2 - Reserved. Return zeroes on reads.
28387 */
28388#define DDRPHY_DX4GSR6_RESERVED_3_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_3_2_MASK)
28389#define DDRPHY_DX4GSR6_RESERVED_7_4_MASK (0xF0U)
28390#define DDRPHY_DX4GSR6_RESERVED_7_4_SHIFT (4U)
28391/*! RESERVED_7_4 - Reserved. Return zeroes on reads.
28392 */
28393#define DDRPHY_DX4GSR6_RESERVED_7_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_7_4_MASK)
28394#define DDRPHY_DX4GSR6_RESERVED_11_8_MASK (0xF00U)
28395#define DDRPHY_DX4GSR6_RESERVED_11_8_SHIFT (8U)
28396/*! RESERVED_11_8 - Reserved. Return zeroes on reads.
28397 */
28398#define DDRPHY_DX4GSR6_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_11_8_MASK)
28399#define DDRPHY_DX4GSR6_RESERVED_15_12_MASK (0xF000U)
28400#define DDRPHY_DX4GSR6_RESERVED_15_12_SHIFT (12U)
28401/*! RESERVED_15_12 - Reserved. Return zeroes on reads.
28402 */
28403#define DDRPHY_DX4GSR6_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_15_12_MASK)
28404#define DDRPHY_DX4GSR6_RESERVED_19_15_MASK (0xF0000U)
28405#define DDRPHY_DX4GSR6_RESERVED_19_15_SHIFT (16U)
28406/*! RESERVED_19_15 - Reserved. Return zeroes on reads.
28407 */
28408#define DDRPHY_DX4GSR6_RESERVED_19_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_19_15_MASK)
28409#define DDRPHY_DX4GSR6_RESERVED_23_20_MASK (0xF00000U)
28410#define DDRPHY_DX4GSR6_RESERVED_23_20_SHIFT (20U)
28411/*! RESERVED_23_20 - Reserved. Return zeroes on reads.
28412 */
28413#define DDRPHY_DX4GSR6_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_23_20_MASK)
28414#define DDRPHY_DX4GSR6_RESERVED_31_24_MASK (0xFF000000U)
28415#define DDRPHY_DX4GSR6_RESERVED_31_24_SHIFT (24U)
28416/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
28417 */
28418#define DDRPHY_DX4GSR6_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX4GSR6_RESERVED_31_24_MASK)
28419/*! @} */
28420
28421/*! @name DX5GCR0 - DATX8 n General Configuration Register 0 */
28422/*! @{ */
28423#define DDRPHY_DX5GCR0_RESERVED_1_0_MASK (0x3U)
28424#define DDRPHY_DX5GCR0_RESERVED_1_0_SHIFT (0U)
28425/*! RESERVED_1_0 - Reserved. Return zeroes on reads.
28426 */
28427#define DDRPHY_DX5GCR0_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX5GCR0_RESERVED_1_0_MASK)
28428#define DDRPHY_DX5GCR0_DQSGOE_MASK (0x4U)
28429#define DDRPHY_DX5GCR0_DQSGOE_SHIFT (2U)
28430/*! DQSGOE - DQSG Output Enable
28431 */
28432#define DDRPHY_DX5GCR0_DQSGOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSGOE_SHIFT)) & DDRPHY_DX5GCR0_DQSGOE_MASK)
28433#define DDRPHY_DX5GCR0_DQSGODT_MASK (0x8U)
28434#define DDRPHY_DX5GCR0_DQSGODT_SHIFT (3U)
28435/*! DQSGODT - DQSG On-Die Termination
28436 */
28437#define DDRPHY_DX5GCR0_DQSGODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSGODT_SHIFT)) & DDRPHY_DX5GCR0_DQSGODT_MASK)
28438#define DDRPHY_DX5GCR0_RESERVED_4_MASK (0x10U)
28439#define DDRPHY_DX5GCR0_RESERVED_4_SHIFT (4U)
28440/*! RESERVED_4 - Reserved. Return zeroes on reads.
28441 */
28442#define DDRPHY_DX5GCR0_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX5GCR0_RESERVED_4_MASK)
28443#define DDRPHY_DX5GCR0_DQSGPDR_MASK (0x20U)
28444#define DDRPHY_DX5GCR0_DQSGPDR_SHIFT (5U)
28445/*! DQSGPDR - DQSG Power Down Receiver
28446 */
28447#define DDRPHY_DX5GCR0_DQSGPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX5GCR0_DQSGPDR_MASK)
28448#define DDRPHY_DX5GCR0_DQSRPD_MASK (0x40U)
28449#define DDRPHY_DX5GCR0_DQSRPD_SHIFT (6U)
28450/*! DQSRPD - DQSR Power Down
28451 */
28452#define DDRPHY_DX5GCR0_DQSRPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSRPD_SHIFT)) & DDRPHY_DX5GCR0_DQSRPD_MASK)
28453#define DDRPHY_DX5GCR0_CPDRSHFT_MASK (0x180U)
28454#define DDRPHY_DX5GCR0_CPDRSHFT_SHIFT (7U)
28455/*! CPDRSHFT - Configurable PDR Phase Shift
28456 */
28457#define DDRPHY_DX5GCR0_CPDRSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX5GCR0_CPDRSHFT_MASK)
28458#define DDRPHY_DX5GCR0_RTTOH_MASK (0x600U)
28459#define DDRPHY_DX5GCR0_RTTOH_SHIFT (9U)
28460/*! RTTOH - RTT Output Hold
28461 */
28462#define DDRPHY_DX5GCR0_RTTOH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_RTTOH_SHIFT)) & DDRPHY_DX5GCR0_RTTOH_MASK)
28463#define DDRPHY_DX5GCR0_RTTOAL_MASK (0x800U)
28464#define DDRPHY_DX5GCR0_RTTOAL_SHIFT (11U)
28465/*! RTTOAL - RTT On Additive Latency
28466 */
28467#define DDRPHY_DX5GCR0_RTTOAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_RTTOAL_SHIFT)) & DDRPHY_DX5GCR0_RTTOAL_MASK)
28468#define DDRPHY_DX5GCR0_DQSSEPDR_MASK (0x1000U)
28469#define DDRPHY_DX5GCR0_DQSSEPDR_SHIFT (12U)
28470/*! DQSSEPDR - DQSSE Power Down Receiver
28471 */
28472#define DDRPHY_DX5GCR0_DQSSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX5GCR0_DQSSEPDR_MASK)
28473#define DDRPHY_DX5GCR0_DQSNSEPDR_MASK (0x2000U)
28474#define DDRPHY_DX5GCR0_DQSNSEPDR_SHIFT (13U)
28475/*! DQSNSEPDR - DQSNSE Power Down Receiver
28476 */
28477#define DDRPHY_DX5GCR0_DQSNSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX5GCR0_DQSNSEPDR_MASK)
28478#define DDRPHY_DX5GCR0_RESERVED_19_14_MASK (0xFC000U)
28479#define DDRPHY_DX5GCR0_RESERVED_19_14_SHIFT (14U)
28480/*! RESERVED_19_14 - Reserved. Return zeroes on reads.
28481 */
28482#define DDRPHY_DX5GCR0_RESERVED_19_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX5GCR0_RESERVED_19_14_MASK)
28483#define DDRPHY_DX5GCR0_RDDLY_MASK (0xF00000U)
28484#define DDRPHY_DX5GCR0_RDDLY_SHIFT (20U)
28485/*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
28486 */
28487#define DDRPHY_DX5GCR0_RDDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_RDDLY_SHIFT)) & DDRPHY_DX5GCR0_RDDLY_MASK)
28488#define DDRPHY_DX5GCR0_DQSDCC_MASK (0xF000000U)
28489#define DDRPHY_DX5GCR0_DQSDCC_SHIFT (24U)
28490/*! DQSDCC - DQS Duty Cycle Correction
28491 */
28492#define DDRPHY_DX5GCR0_DQSDCC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_DQSDCC_SHIFT)) & DDRPHY_DX5GCR0_DQSDCC_MASK)
28493#define DDRPHY_DX5GCR0_CODTSHFT_MASK (0x30000000U)
28494#define DDRPHY_DX5GCR0_CODTSHFT_SHIFT (28U)
28495/*! CODTSHFT - Configurable ODT(TE) Phase Shift
28496 */
28497#define DDRPHY_DX5GCR0_CODTSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX5GCR0_CODTSHFT_MASK)
28498#define DDRPHY_DX5GCR0_MDLEN_MASK (0x40000000U)
28499#define DDRPHY_DX5GCR0_MDLEN_SHIFT (30U)
28500/*! MDLEN - Master Delay Line Enable
28501 */
28502#define DDRPHY_DX5GCR0_MDLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_MDLEN_SHIFT)) & DDRPHY_DX5GCR0_MDLEN_MASK)
28503#define DDRPHY_DX5GCR0_CALBYP_MASK (0x80000000U)
28504#define DDRPHY_DX5GCR0_CALBYP_SHIFT (31U)
28505/*! CALBYP - Calibration Bypass
28506 */
28507#define DDRPHY_DX5GCR0_CALBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR0_CALBYP_SHIFT)) & DDRPHY_DX5GCR0_CALBYP_MASK)
28508/*! @} */
28509
28510/*! @name DX5GCR1 - DATX8 n General Configuration Register 1 */
28511/*! @{ */
28512#define DDRPHY_DX5GCR1_DQEN_MASK (0xFFU)
28513#define DDRPHY_DX5GCR1_DQEN_SHIFT (0U)
28514/*! DQEN - Enables DQ corresponding to each bit in a byte
28515 */
28516#define DDRPHY_DX5GCR1_DQEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_DQEN_SHIFT)) & DDRPHY_DX5GCR1_DQEN_MASK)
28517#define DDRPHY_DX5GCR1_DMEN_MASK (0x100U)
28518#define DDRPHY_DX5GCR1_DMEN_SHIFT (8U)
28519/*! DMEN - Enables DM pin in a byte lane
28520 */
28521#define DDRPHY_DX5GCR1_DMEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_DMEN_SHIFT)) & DDRPHY_DX5GCR1_DMEN_MASK)
28522#define DDRPHY_DX5GCR1_DSEN_MASK (0x200U)
28523#define DDRPHY_DX5GCR1_DSEN_SHIFT (9U)
28524/*! DSEN - Enables Write Data strobe in a byte lane
28525 */
28526#define DDRPHY_DX5GCR1_DSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_DSEN_SHIFT)) & DDRPHY_DX5GCR1_DSEN_MASK)
28527#define DDRPHY_DX5GCR1_TEEN_MASK (0x400U)
28528#define DDRPHY_DX5GCR1_TEEN_SHIFT (10U)
28529/*! TEEN - Enables ODT/TE in a byte lane
28530 */
28531#define DDRPHY_DX5GCR1_TEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_TEEN_SHIFT)) & DDRPHY_DX5GCR1_TEEN_MASK)
28532#define DDRPHY_DX5GCR1_PDREN_MASK (0x800U)
28533#define DDRPHY_DX5GCR1_PDREN_SHIFT (11U)
28534/*! PDREN - Enables PDR in a byte lane
28535 */
28536#define DDRPHY_DX5GCR1_PDREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_PDREN_SHIFT)) & DDRPHY_DX5GCR1_PDREN_MASK)
28537#define DDRPHY_DX5GCR1_OEEN_MASK (0x1000U)
28538#define DDRPHY_DX5GCR1_OEEN_SHIFT (12U)
28539/*! OEEN - Enables Read Data Strobe in a byte lane
28540 */
28541#define DDRPHY_DX5GCR1_OEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_OEEN_SHIFT)) & DDRPHY_DX5GCR1_OEEN_MASK)
28542#define DDRPHY_DX5GCR1_QSSEL_MASK (0x2000U)
28543#define DDRPHY_DX5GCR1_QSSEL_SHIFT (13U)
28544/*! QSSEL - Select the delayed or non-delayed read data strobe
28545 */
28546#define DDRPHY_DX5GCR1_QSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_QSSEL_SHIFT)) & DDRPHY_DX5GCR1_QSSEL_MASK)
28547#define DDRPHY_DX5GCR1_QSNSEL_MASK (0x4000U)
28548#define DDRPHY_DX5GCR1_QSNSEL_SHIFT (14U)
28549/*! QSNSEL - Select the delayed or non-delayed read data strobe #
28550 */
28551#define DDRPHY_DX5GCR1_QSNSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_QSNSEL_SHIFT)) & DDRPHY_DX5GCR1_QSNSEL_MASK)
28552#define DDRPHY_DX5GCR1_RESERVED_15_MASK (0x8000U)
28553#define DDRPHY_DX5GCR1_RESERVED_15_SHIFT (15U)
28554/*! RESERVED_15 - Reserved. Returns zeroes on reads.
28555 */
28556#define DDRPHY_DX5GCR1_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX5GCR1_RESERVED_15_MASK)
28557#define DDRPHY_DX5GCR1_DXPDRMODE_MASK (0xFFFF0000U)
28558#define DDRPHY_DX5GCR1_DXPDRMODE_SHIFT (16U)
28559/*! DXPDRMODE - Enables the PDR mode for DQ[7:0]
28560 */
28561#define DDRPHY_DX5GCR1_DXPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX5GCR1_DXPDRMODE_MASK)
28562/*! @} */
28563
28564/*! @name DX5GCR2 - DATX8 n General Configuration Register 2 */
28565/*! @{ */
28566#define DDRPHY_DX5GCR2_DXTEMODE_MASK (0xFFFFU)
28567#define DDRPHY_DX5GCR2_DXTEMODE_SHIFT (0U)
28568/*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0]
28569 */
28570#define DDRPHY_DX5GCR2_DXTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX5GCR2_DXTEMODE_MASK)
28571#define DDRPHY_DX5GCR2_DXOEMODE_MASK (0xFFFF0000U)
28572#define DDRPHY_DX5GCR2_DXOEMODE_SHIFT (16U)
28573/*! DXOEMODE - Enables the OE mode values for DQ[7:0]
28574 */
28575#define DDRPHY_DX5GCR2_DXOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX5GCR2_DXOEMODE_MASK)
28576/*! @} */
28577
28578/*! @name DX5GCR3 - DATX8 n General Configuration Register 3 */
28579/*! @{ */
28580#define DDRPHY_DX5GCR3_WDMBVT_MASK (0x1U)
28581#define DDRPHY_DX5GCR3_WDMBVT_SHIFT (0U)
28582/*! WDMBVT - Write Data Mask BDL VT Compensation
28583 */
28584#define DDRPHY_DX5GCR3_WDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_WDMBVT_SHIFT)) & DDRPHY_DX5GCR3_WDMBVT_MASK)
28585#define DDRPHY_DX5GCR3_RDMBVT_MASK (0x2U)
28586#define DDRPHY_DX5GCR3_RDMBVT_SHIFT (1U)
28587/*! RDMBVT - Read Data Mask BDL VT Compensation
28588 */
28589#define DDRPHY_DX5GCR3_RDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_RDMBVT_SHIFT)) & DDRPHY_DX5GCR3_RDMBVT_MASK)
28590#define DDRPHY_DX5GCR3_DSPDRMODE_MASK (0xCU)
28591#define DDRPHY_DX5GCR3_DSPDRMODE_SHIFT (2U)
28592/*! DSPDRMODE - Enables the PDR mode values for DQS.
28593 */
28594#define DDRPHY_DX5GCR3_DSPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX5GCR3_DSPDRMODE_MASK)
28595#define DDRPHY_DX5GCR3_DSTEMODE_MASK (0x30U)
28596#define DDRPHY_DX5GCR3_DSTEMODE_SHIFT (4U)
28597/*! DSTEMODE - Enables the TE mode values for DQS.
28598 */
28599#define DDRPHY_DX5GCR3_DSTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX5GCR3_DSTEMODE_MASK)
28600#define DDRPHY_DX5GCR3_DSOEMODE_MASK (0xC0U)
28601#define DDRPHY_DX5GCR3_DSOEMODE_SHIFT (6U)
28602/*! DSOEMODE - Enables the OE mode values for DQS.
28603 */
28604#define DDRPHY_DX5GCR3_DSOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX5GCR3_DSOEMODE_MASK)
28605#define DDRPHY_DX5GCR3_WDSBVT_MASK (0x100U)
28606#define DDRPHY_DX5GCR3_WDSBVT_SHIFT (8U)
28607/*! WDSBVT - Write Data Strobe BDL VT Compensation
28608 */
28609#define DDRPHY_DX5GCR3_WDSBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_WDSBVT_SHIFT)) & DDRPHY_DX5GCR3_WDSBVT_MASK)
28610#define DDRPHY_DX5GCR3_RESERVED_9_MASK (0x200U)
28611#define DDRPHY_DX5GCR3_RESERVED_9_SHIFT (9U)
28612/*! RESERVED_9 - Reserved. Returns zeroes on reads.
28613 */
28614#define DDRPHY_DX5GCR3_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX5GCR3_RESERVED_9_MASK)
28615#define DDRPHY_DX5GCR3_DMPDRMODE_MASK (0xC00U)
28616#define DDRPHY_DX5GCR3_DMPDRMODE_SHIFT (10U)
28617/*! DMPDRMODE - Enables the PDR mode values for DM.
28618 */
28619#define DDRPHY_DX5GCR3_DMPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX5GCR3_DMPDRMODE_MASK)
28620#define DDRPHY_DX5GCR3_DMTEMODE_MASK (0x3000U)
28621#define DDRPHY_DX5GCR3_DMTEMODE_SHIFT (12U)
28622/*! DMTEMODE - Enables the TE mode values for DM.
28623 */
28624#define DDRPHY_DX5GCR3_DMTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX5GCR3_DMTEMODE_MASK)
28625#define DDRPHY_DX5GCR3_DMOEMODE_MASK (0xC000U)
28626#define DDRPHY_DX5GCR3_DMOEMODE_SHIFT (14U)
28627/*! DMOEMODE - Enables the OE mode values for DM.
28628 */
28629#define DDRPHY_DX5GCR3_DMOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX5GCR3_DMOEMODE_MASK)
28630#define DDRPHY_DX5GCR3_DSNPDRMODE_MASK (0x30000U)
28631#define DDRPHY_DX5GCR3_DSNPDRMODE_SHIFT (16U)
28632/*! DSNPDRMODE - Enables the PDR mode for DQS
28633 */
28634#define DDRPHY_DX5GCR3_DSNPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX5GCR3_DSNPDRMODE_MASK)
28635#define DDRPHY_DX5GCR3_DSNTEMODE_MASK (0xC0000U)
28636#define DDRPHY_DX5GCR3_DSNTEMODE_SHIFT (18U)
28637/*! DSNTEMODE - Enables the TE mode for DQS
28638 */
28639#define DDRPHY_DX5GCR3_DSNTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX5GCR3_DSNTEMODE_MASK)
28640#define DDRPHY_DX5GCR3_DSNOEMODE_MASK (0x300000U)
28641#define DDRPHY_DX5GCR3_DSNOEMODE_SHIFT (20U)
28642/*! DSNOEMODE - Enables the OE mode for DQs
28643 */
28644#define DDRPHY_DX5GCR3_DSNOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX5GCR3_DSNOEMODE_MASK)
28645#define DDRPHY_DX5GCR3_PDRBVT_MASK (0x400000U)
28646#define DDRPHY_DX5GCR3_PDRBVT_SHIFT (22U)
28647/*! PDRBVT - Power Down Receiver BDL VT Compensation
28648 */
28649#define DDRPHY_DX5GCR3_PDRBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_PDRBVT_SHIFT)) & DDRPHY_DX5GCR3_PDRBVT_MASK)
28650#define DDRPHY_DX5GCR3_RGSLVT_MASK (0x800000U)
28651#define DDRPHY_DX5GCR3_RGSLVT_SHIFT (23U)
28652/*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation
28653 */
28654#define DDRPHY_DX5GCR3_RGSLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_RGSLVT_SHIFT)) & DDRPHY_DX5GCR3_RGSLVT_MASK)
28655#define DDRPHY_DX5GCR3_WLLVT_MASK (0x1000000U)
28656#define DDRPHY_DX5GCR3_WLLVT_SHIFT (24U)
28657/*! WLLVT - Write Leveling LCDL Delay VT Compensation
28658 */
28659#define DDRPHY_DX5GCR3_WLLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_WLLVT_SHIFT)) & DDRPHY_DX5GCR3_WLLVT_MASK)
28660#define DDRPHY_DX5GCR3_WDLVT_MASK (0x2000000U)
28661#define DDRPHY_DX5GCR3_WDLVT_SHIFT (25U)
28662/*! WDLVT - Write DQ LCDL Delay VT Compensation
28663 */
28664#define DDRPHY_DX5GCR3_WDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_WDLVT_SHIFT)) & DDRPHY_DX5GCR3_WDLVT_MASK)
28665#define DDRPHY_DX5GCR3_RDLVT_MASK (0x4000000U)
28666#define DDRPHY_DX5GCR3_RDLVT_SHIFT (26U)
28667/*! RDLVT - Read DQS LCDL Delay VT Compensation
28668 */
28669#define DDRPHY_DX5GCR3_RDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_RDLVT_SHIFT)) & DDRPHY_DX5GCR3_RDLVT_MASK)
28670#define DDRPHY_DX5GCR3_RGLVT_MASK (0x8000000U)
28671#define DDRPHY_DX5GCR3_RGLVT_SHIFT (27U)
28672/*! RGLVT - Read DQS Gating LCDL Delay VT Compensation
28673 */
28674#define DDRPHY_DX5GCR3_RGLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_RGLVT_SHIFT)) & DDRPHY_DX5GCR3_RGLVT_MASK)
28675#define DDRPHY_DX5GCR3_WDBVT_MASK (0x10000000U)
28676#define DDRPHY_DX5GCR3_WDBVT_SHIFT (28U)
28677/*! WDBVT - Write Data BDL VT Compensation
28678 */
28679#define DDRPHY_DX5GCR3_WDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_WDBVT_SHIFT)) & DDRPHY_DX5GCR3_WDBVT_MASK)
28680#define DDRPHY_DX5GCR3_RDBVT_MASK (0x20000000U)
28681#define DDRPHY_DX5GCR3_RDBVT_SHIFT (29U)
28682/*! RDBVT - Read Data BDL VT Compensation
28683 */
28684#define DDRPHY_DX5GCR3_RDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_RDBVT_SHIFT)) & DDRPHY_DX5GCR3_RDBVT_MASK)
28685#define DDRPHY_DX5GCR3_TEBVT_MASK (0x40000000U)
28686#define DDRPHY_DX5GCR3_TEBVT_SHIFT (30U)
28687/*! TEBVT - Termination Enable BDL VT Compensation
28688 */
28689#define DDRPHY_DX5GCR3_TEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_TEBVT_SHIFT)) & DDRPHY_DX5GCR3_TEBVT_MASK)
28690#define DDRPHY_DX5GCR3_OEBVT_MASK (0x80000000U)
28691#define DDRPHY_DX5GCR3_OEBVT_SHIFT (31U)
28692/*! OEBVT - Output Enable BDL VT Compensation
28693 */
28694#define DDRPHY_DX5GCR3_OEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR3_OEBVT_SHIFT)) & DDRPHY_DX5GCR3_OEBVT_MASK)
28695/*! @} */
28696
28697/*! @name DX5GCR4 - DATX8 n General Configuration Register 4 */
28698/*! @{ */
28699#define DDRPHY_DX5GCR4_DXREFIMON_MASK (0x3U)
28700#define DDRPHY_DX5GCR4_DXREFIMON_SHIFT (0U)
28701/*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane.
28702 */
28703#define DDRPHY_DX5GCR4_DXREFIMON(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX5GCR4_DXREFIMON_MASK)
28704#define DDRPHY_DX5GCR4_DXREFIEN_MASK (0x3CU)
28705#define DDRPHY_DX5GCR4_DXREFIEN_SHIFT (2U)
28706/*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
28707 */
28708#define DDRPHY_DX5GCR4_DXREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX5GCR4_DXREFIEN_MASK)
28709#define DDRPHY_DX5GCR4_RESERVED_7_6_MASK (0xC0U)
28710#define DDRPHY_DX5GCR4_RESERVED_7_6_SHIFT (6U)
28711/*! RESERVED_7_6 - Reserved. Returns zeros on reads.
28712 */
28713#define DDRPHY_DX5GCR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX5GCR4_RESERVED_7_6_MASK)
28714#define DDRPHY_DX5GCR4_DXREFSSEL_MASK (0x7F00U)
28715#define DDRPHY_DX5GCR4_DXREFSSEL_SHIFT (8U)
28716/*! DXREFSSEL - Byte Lane Single-End VREF Select
28717 */
28718#define DDRPHY_DX5GCR4_DXREFSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX5GCR4_DXREFSSEL_MASK)
28719#define DDRPHY_DX5GCR4_DXREFSSELRANGE_MASK (0x8000U)
28720#define DDRPHY_DX5GCR4_DXREFSSELRANGE_SHIFT (15U)
28721/*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select
28722 */
28723#define DDRPHY_DX5GCR4_DXREFSSELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX5GCR4_DXREFSSELRANGE_MASK)
28724#define DDRPHY_DX5GCR4_DXREFESEL_MASK (0x7F0000U)
28725#define DDRPHY_DX5GCR4_DXREFESEL_SHIFT (16U)
28726/*! DXREFESEL - Byte Lane External VREF Select
28727 */
28728#define DDRPHY_DX5GCR4_DXREFESEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX5GCR4_DXREFESEL_MASK)
28729#define DDRPHY_DX5GCR4_DXREFESELRANGE_MASK (0x800000U)
28730#define DDRPHY_DX5GCR4_DXREFESELRANGE_SHIFT (23U)
28731/*! DXREFESELRANGE - External VREF generator REFSEL range select
28732 */
28733#define DDRPHY_DX5GCR4_DXREFESELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX5GCR4_DXREFESELRANGE_MASK)
28734#define DDRPHY_DX5GCR4_RESERVED_24_MASK (0x1000000U)
28735#define DDRPHY_DX5GCR4_RESERVED_24_SHIFT (24U)
28736/*! RESERVED_24 - Reserved. Returns zeros on reads.
28737 */
28738#define DDRPHY_DX5GCR4_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX5GCR4_RESERVED_24_MASK)
28739#define DDRPHY_DX5GCR4_DXREFSEN_MASK (0x2000000U)
28740#define DDRPHY_DX5GCR4_DXREFSEN_SHIFT (25U)
28741/*! DXREFSEN - Byte Lane Single-End VREF Enable
28742 */
28743#define DDRPHY_DX5GCR4_DXREFSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX5GCR4_DXREFSEN_MASK)
28744#define DDRPHY_DX5GCR4_DXREFEEN_MASK (0xC000000U)
28745#define DDRPHY_DX5GCR4_DXREFEEN_SHIFT (26U)
28746/*! DXREFEEN - Byte Lane Internal VREF Enable
28747 */
28748#define DDRPHY_DX5GCR4_DXREFEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX5GCR4_DXREFEEN_MASK)
28749#define DDRPHY_DX5GCR4_DXREFPEN_MASK (0x10000000U)
28750#define DDRPHY_DX5GCR4_DXREFPEN_SHIFT (28U)
28751/*! DXREFPEN - Byte Lane VREF Pad Enable
28752 */
28753#define DDRPHY_DX5GCR4_DXREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX5GCR4_DXREFPEN_MASK)
28754#define DDRPHY_DX5GCR4_RESERVED_31_29_MASK (0xE0000000U)
28755#define DDRPHY_DX5GCR4_RESERVED_31_29_SHIFT (29U)
28756/*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs)
28757 */
28758#define DDRPHY_DX5GCR4_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX5GCR4_RESERVED_31_29_MASK)
28759/*! @} */
28760
28761/*! @name DX5GCR5 - DATX8 n General Configuration Register 5 */
28762/*! @{ */
28763#define DDRPHY_DX5GCR5_DXREFISELR0_MASK (0x7FU)
28764#define DDRPHY_DX5GCR5_DXREFISELR0_SHIFT (0U)
28765/*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0
28766 */
28767#define DDRPHY_DX5GCR5_DXREFISELR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX5GCR5_DXREFISELR0_MASK)
28768#define DDRPHY_DX5GCR5_RESERVED_7_MASK (0x80U)
28769#define DDRPHY_DX5GCR5_RESERVED_7_SHIFT (7U)
28770/*! RESERVED_7 - Reserved. Returns zeros on reads.
28771 */
28772#define DDRPHY_DX5GCR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX5GCR5_RESERVED_7_MASK)
28773#define DDRPHY_DX5GCR5_DXREFISELR1_MASK (0x7F00U)
28774#define DDRPHY_DX5GCR5_DXREFISELR1_SHIFT (8U)
28775/*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1
28776 */
28777#define DDRPHY_DX5GCR5_DXREFISELR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX5GCR5_DXREFISELR1_MASK)
28778#define DDRPHY_DX5GCR5_RESERVED_15_MASK (0x8000U)
28779#define DDRPHY_DX5GCR5_RESERVED_15_SHIFT (15U)
28780/*! RESERVED_15 - Reserved. Returns zeros on reads.
28781 */
28782#define DDRPHY_DX5GCR5_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX5GCR5_RESERVED_15_MASK)
28783#define DDRPHY_DX5GCR5_DXREFISELR2_MASK (0x7F0000U)
28784#define DDRPHY_DX5GCR5_DXREFISELR2_SHIFT (16U)
28785/*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2
28786 */
28787#define DDRPHY_DX5GCR5_DXREFISELR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX5GCR5_DXREFISELR2_MASK)
28788#define DDRPHY_DX5GCR5_RESERVED_23_MASK (0x800000U)
28789#define DDRPHY_DX5GCR5_RESERVED_23_SHIFT (23U)
28790/*! RESERVED_23 - Reserved. Returns zeros on reads.
28791 */
28792#define DDRPHY_DX5GCR5_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX5GCR5_RESERVED_23_MASK)
28793#define DDRPHY_DX5GCR5_DXREFISELR3_MASK (0x7F000000U)
28794#define DDRPHY_DX5GCR5_DXREFISELR3_SHIFT (24U)
28795/*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3
28796 */
28797#define DDRPHY_DX5GCR5_DXREFISELR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX5GCR5_DXREFISELR3_MASK)
28798#define DDRPHY_DX5GCR5_RESERVED_31_MASK (0x80000000U)
28799#define DDRPHY_DX5GCR5_RESERVED_31_SHIFT (31U)
28800/*! RESERVED_31 - Reserved. Returns zeros on reads.
28801 */
28802#define DDRPHY_DX5GCR5_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX5GCR5_RESERVED_31_MASK)
28803/*! @} */
28804
28805/*! @name DX5GCR6 - DATX8 n General Configuration Register 6 */
28806/*! @{ */
28807#define DDRPHY_DX5GCR6_DXDQVREFR0_MASK (0x3FU)
28808#define DDRPHY_DX5GCR6_DXDQVREFR0_SHIFT (0U)
28809/*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0
28810 */
28811#define DDRPHY_DX5GCR6_DXDQVREFR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX5GCR6_DXDQVREFR0_MASK)
28812#define DDRPHY_DX5GCR6_RESERVED_7_6_MASK (0xC0U)
28813#define DDRPHY_DX5GCR6_RESERVED_7_6_SHIFT (6U)
28814/*! RESERVED_7_6 - Reserved. Returns zeros on reads.
28815 */
28816#define DDRPHY_DX5GCR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX5GCR6_RESERVED_7_6_MASK)
28817#define DDRPHY_DX5GCR6_DXDQVREFR1_MASK (0x3F00U)
28818#define DDRPHY_DX5GCR6_DXDQVREFR1_SHIFT (8U)
28819/*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1
28820 */
28821#define DDRPHY_DX5GCR6_DXDQVREFR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX5GCR6_DXDQVREFR1_MASK)
28822#define DDRPHY_DX5GCR6_RESERVED_15_14_MASK (0xC000U)
28823#define DDRPHY_DX5GCR6_RESERVED_15_14_SHIFT (14U)
28824/*! RESERVED_15_14 - Reserved. Returns zeros on reads.
28825 */
28826#define DDRPHY_DX5GCR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX5GCR6_RESERVED_15_14_MASK)
28827#define DDRPHY_DX5GCR6_DXDQVREFR2_MASK (0x3F0000U)
28828#define DDRPHY_DX5GCR6_DXDQVREFR2_SHIFT (16U)
28829/*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2
28830 */
28831#define DDRPHY_DX5GCR6_DXDQVREFR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX5GCR6_DXDQVREFR2_MASK)
28832#define DDRPHY_DX5GCR6_RESERVED_23_22_MASK (0xC00000U)
28833#define DDRPHY_DX5GCR6_RESERVED_23_22_SHIFT (22U)
28834/*! RESERVED_23_22 - Reserved. Returns zeros on reads.
28835 */
28836#define DDRPHY_DX5GCR6_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX5GCR6_RESERVED_23_22_MASK)
28837#define DDRPHY_DX5GCR6_DXDQVREFR3_MASK (0x3F000000U)
28838#define DDRPHY_DX5GCR6_DXDQVREFR3_SHIFT (24U)
28839/*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3
28840 */
28841#define DDRPHY_DX5GCR6_DXDQVREFR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX5GCR6_DXDQVREFR3_MASK)
28842#define DDRPHY_DX5GCR6_RESERVED_31_30_MASK (0xC0000000U)
28843#define DDRPHY_DX5GCR6_RESERVED_31_30_SHIFT (30U)
28844/*! RESERVED_31_30 - Reserved. Returns zeros on reads.
28845 */
28846#define DDRPHY_DX5GCR6_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX5GCR6_RESERVED_31_30_MASK)
28847/*! @} */
28848
28849/*! @name DX5GCR7 - DATX8 n General Configuration Register 7 */
28850/*! @{ */
28851#define DDRPHY_DX5GCR7_DCALSVAL_MASK (0x1FFU)
28852#define DDRPHY_DX5GCR7_DCALSVAL_SHIFT (0U)
28853/*! DCALSVAL - DDL Calibration Starting Value
28854 */
28855#define DDRPHY_DX5GCR7_DCALSVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX5GCR7_DCALSVAL_MASK)
28856#define DDRPHY_DX5GCR7_DCALTYPE_MASK (0x200U)
28857#define DDRPHY_DX5GCR7_DCALTYPE_SHIFT (9U)
28858/*! DCALTYPE - DDL Calibration Type
28859 */
28860#define DDRPHY_DX5GCR7_DCALTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX5GCR7_DCALTYPE_MASK)
28861#define DDRPHY_DX5GCR7_RESERVED_17_10_MASK (0x3FC00U)
28862#define DDRPHY_DX5GCR7_RESERVED_17_10_SHIFT (10U)
28863/*! RESERVED_17_10 - Reserved. Caution, do not write to this register field.
28864 */
28865#define DDRPHY_DX5GCR7_RESERVED_17_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX5GCR7_RESERVED_17_10_MASK)
28866#define DDRPHY_DX5GCR7_RESERVED_18_MASK (0x40000U)
28867#define DDRPHY_DX5GCR7_RESERVED_18_SHIFT (18U)
28868/*! RESERVED_18 - Reserved. Caution, do not write to this register field.
28869 */
28870#define DDRPHY_DX5GCR7_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX5GCR7_RESERVED_18_MASK)
28871#define DDRPHY_DX5GCR7_RESERVED_31_19_MASK (0xFFF80000U)
28872#define DDRPHY_DX5GCR7_RESERVED_31_19_SHIFT (19U)
28873/*! RESERVED_31_19 - Reserved. Caution, do not write to this register field.
28874 */
28875#define DDRPHY_DX5GCR7_RESERVED_31_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX5GCR7_RESERVED_31_19_MASK)
28876/*! @} */
28877
28878/*! @name DX5GCR8 - DATX8 n General Configuration Register 8 */
28879/*! @{ */
28880#define DDRPHY_DX5GCR8_RESERVED_5_0_MASK (0x3FU)
28881#define DDRPHY_DX5GCR8_RESERVED_5_0_SHIFT (0U)
28882/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
28883 */
28884#define DDRPHY_DX5GCR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_5_0_MASK)
28885#define DDRPHY_DX5GCR8_RESERVED_7_6_MASK (0xC0U)
28886#define DDRPHY_DX5GCR8_RESERVED_7_6_SHIFT (6U)
28887/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
28888 */
28889#define DDRPHY_DX5GCR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_7_6_MASK)
28890#define DDRPHY_DX5GCR8_RESERVED_13_8_MASK (0x3F00U)
28891#define DDRPHY_DX5GCR8_RESERVED_13_8_SHIFT (8U)
28892/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
28893 */
28894#define DDRPHY_DX5GCR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_13_8_MASK)
28895#define DDRPHY_DX5GCR8_RESERVED_15_14_MASK (0xC000U)
28896#define DDRPHY_DX5GCR8_RESERVED_15_14_SHIFT (14U)
28897/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
28898 */
28899#define DDRPHY_DX5GCR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_15_14_MASK)
28900#define DDRPHY_DX5GCR8_RESERVED_21_16_MASK (0x3F0000U)
28901#define DDRPHY_DX5GCR8_RESERVED_21_16_SHIFT (16U)
28902/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
28903 */
28904#define DDRPHY_DX5GCR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_21_16_MASK)
28905#define DDRPHY_DX5GCR8_RESERVED_23_22_MASK (0xC00000U)
28906#define DDRPHY_DX5GCR8_RESERVED_23_22_SHIFT (22U)
28907/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
28908 */
28909#define DDRPHY_DX5GCR8_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_23_22_MASK)
28910#define DDRPHY_DX5GCR8_RESERVED_29_24_MASK (0x3F000000U)
28911#define DDRPHY_DX5GCR8_RESERVED_29_24_SHIFT (24U)
28912/*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
28913 */
28914#define DDRPHY_DX5GCR8_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_29_24_MASK)
28915#define DDRPHY_DX5GCR8_RESERVED_31_30_MASK (0xC0000000U)
28916#define DDRPHY_DX5GCR8_RESERVED_31_30_SHIFT (30U)
28917/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
28918 */
28919#define DDRPHY_DX5GCR8_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX5GCR8_RESERVED_31_30_MASK)
28920/*! @} */
28921
28922/*! @name DX5GCR9 - DATX8 n General Configuration Register 9 */
28923/*! @{ */
28924#define DDRPHY_DX5GCR9_RESERVED_5_0_MASK (0x3FU)
28925#define DDRPHY_DX5GCR9_RESERVED_5_0_SHIFT (0U)
28926/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
28927 */
28928#define DDRPHY_DX5GCR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_5_0_MASK)
28929#define DDRPHY_DX5GCR9_RESERVED_7_6_MASK (0xC0U)
28930#define DDRPHY_DX5GCR9_RESERVED_7_6_SHIFT (6U)
28931/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
28932 */
28933#define DDRPHY_DX5GCR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_7_6_MASK)
28934#define DDRPHY_DX5GCR9_RESERVED_13_8_MASK (0x3F00U)
28935#define DDRPHY_DX5GCR9_RESERVED_13_8_SHIFT (8U)
28936/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
28937 */
28938#define DDRPHY_DX5GCR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_13_8_MASK)
28939#define DDRPHY_DX5GCR9_RESERVED_15_14_MASK (0xC000U)
28940#define DDRPHY_DX5GCR9_RESERVED_15_14_SHIFT (14U)
28941/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
28942 */
28943#define DDRPHY_DX5GCR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_15_14_MASK)
28944#define DDRPHY_DX5GCR9_RESERVED_21_16_MASK (0x3F0000U)
28945#define DDRPHY_DX5GCR9_RESERVED_21_16_SHIFT (16U)
28946/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
28947 */
28948#define DDRPHY_DX5GCR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_21_16_MASK)
28949#define DDRPHY_DX5GCR9_RESERVED_23_22_MASK (0xC00000U)
28950#define DDRPHY_DX5GCR9_RESERVED_23_22_SHIFT (22U)
28951/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
28952 */
28953#define DDRPHY_DX5GCR9_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_23_22_MASK)
28954#define DDRPHY_DX5GCR9_RESERVED_29_24_MASK (0x3F000000U)
28955#define DDRPHY_DX5GCR9_RESERVED_29_24_SHIFT (24U)
28956/*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
28957 */
28958#define DDRPHY_DX5GCR9_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_29_24_MASK)
28959#define DDRPHY_DX5GCR9_RESERVED_31_30_MASK (0xC0000000U)
28960#define DDRPHY_DX5GCR9_RESERVED_31_30_SHIFT (30U)
28961/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
28962 */
28963#define DDRPHY_DX5GCR9_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX5GCR9_RESERVED_31_30_MASK)
28964/*! @} */
28965
28966/*! @name DX5DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */
28967/*! @{ */
28968#define DDRPHY_DX5DQMAP0_DQ0MAP_MASK (0xFU)
28969#define DDRPHY_DX5DQMAP0_DQ0MAP_SHIFT (0U)
28970/*! DQ0MAP - DQ bit 0 DATX8 slice mapping index
28971 */
28972#define DDRPHY_DX5DQMAP0_DQ0MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX5DQMAP0_DQ0MAP_MASK)
28973#define DDRPHY_DX5DQMAP0_DQ1MAP_MASK (0xF0U)
28974#define DDRPHY_DX5DQMAP0_DQ1MAP_SHIFT (4U)
28975/*! DQ1MAP - DQ bit 1 DATX8 slice mapping index
28976 */
28977#define DDRPHY_DX5DQMAP0_DQ1MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX5DQMAP0_DQ1MAP_MASK)
28978#define DDRPHY_DX5DQMAP0_DQ2MAP_MASK (0xF00U)
28979#define DDRPHY_DX5DQMAP0_DQ2MAP_SHIFT (8U)
28980/*! DQ2MAP - DQ bit 2 DATX8 slice mapping index
28981 */
28982#define DDRPHY_DX5DQMAP0_DQ2MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX5DQMAP0_DQ2MAP_MASK)
28983#define DDRPHY_DX5DQMAP0_DQ3MAP_MASK (0xF000U)
28984#define DDRPHY_DX5DQMAP0_DQ3MAP_SHIFT (12U)
28985/*! DQ3MAP - DQ bit 3 DATX8 slice mapping index
28986 */
28987#define DDRPHY_DX5DQMAP0_DQ3MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX5DQMAP0_DQ3MAP_MASK)
28988#define DDRPHY_DX5DQMAP0_DQ4MAP_MASK (0xF0000U)
28989#define DDRPHY_DX5DQMAP0_DQ4MAP_SHIFT (16U)
28990/*! DQ4MAP - DQ bit 4 DATX8 slice mapping index
28991 */
28992#define DDRPHY_DX5DQMAP0_DQ4MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX5DQMAP0_DQ4MAP_MASK)
28993#define DDRPHY_DX5DQMAP0_RESERVED_30_20_MASK (0x7FF00000U)
28994#define DDRPHY_DX5DQMAP0_RESERVED_30_20_SHIFT (20U)
28995/*! RESERVED_30_20 - Reserved. Return zeroes on reads.
28996 */
28997#define DDRPHY_DX5DQMAP0_RESERVED_30_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX5DQMAP0_RESERVED_30_20_MASK)
28998#define DDRPHY_DX5DQMAP0_MAPOK_MASK (0x80000000U)
28999#define DDRPHY_DX5DQMAP0_MAPOK_SHIFT (31U)
29000/*! MAPOK - Checksum bit
29001 */
29002#define DDRPHY_DX5DQMAP0_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX5DQMAP0_MAPOK_MASK)
29003/*! @} */
29004
29005/*! @name DX5DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */
29006/*! @{ */
29007#define DDRPHY_DX5DQMAP1_DQ5MAP_MASK (0xFU)
29008#define DDRPHY_DX5DQMAP1_DQ5MAP_SHIFT (0U)
29009/*! DQ5MAP - DQ bit 5 DATX8 slice mapping index
29010 */
29011#define DDRPHY_DX5DQMAP1_DQ5MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX5DQMAP1_DQ5MAP_MASK)
29012#define DDRPHY_DX5DQMAP1_DQ6MAP_MASK (0xF0U)
29013#define DDRPHY_DX5DQMAP1_DQ6MAP_SHIFT (4U)
29014/*! DQ6MAP - DQ bit 6 DATX8 slice mapping index
29015 */
29016#define DDRPHY_DX5DQMAP1_DQ6MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX5DQMAP1_DQ6MAP_MASK)
29017#define DDRPHY_DX5DQMAP1_DQ7MAP_MASK (0xF00U)
29018#define DDRPHY_DX5DQMAP1_DQ7MAP_SHIFT (8U)
29019/*! DQ7MAP - DQ bit 7 DATX8 slice mapping index
29020 */
29021#define DDRPHY_DX5DQMAP1_DQ7MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX5DQMAP1_DQ7MAP_MASK)
29022#define DDRPHY_DX5DQMAP1_DMMAP_MASK (0xF000U)
29023#define DDRPHY_DX5DQMAP1_DMMAP_SHIFT (12U)
29024/*! DMMAP - DM bit DATX8 slice mapping index
29025 */
29026#define DDRPHY_DX5DQMAP1_DMMAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX5DQMAP1_DMMAP_MASK)
29027#define DDRPHY_DX5DQMAP1_RESERVED_30_16_MASK (0x7FFF0000U)
29028#define DDRPHY_DX5DQMAP1_RESERVED_30_16_SHIFT (16U)
29029/*! RESERVED_30_16 - Reserved. Return zeroes on reads.
29030 */
29031#define DDRPHY_DX5DQMAP1_RESERVED_30_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX5DQMAP1_RESERVED_30_16_MASK)
29032#define DDRPHY_DX5DQMAP1_MAPOK_MASK (0x80000000U)
29033#define DDRPHY_DX5DQMAP1_MAPOK_SHIFT (31U)
29034/*! MAPOK - Checksum bit
29035 */
29036#define DDRPHY_DX5DQMAP1_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX5DQMAP1_MAPOK_MASK)
29037/*! @} */
29038
29039/*! @name DX5BDLR0 - DATX8 n Bit Delay Line Register 0 */
29040/*! @{ */
29041#define DDRPHY_DX5BDLR0_DQ0WBD_MASK (0x3FU)
29042#define DDRPHY_DX5BDLR0_DQ0WBD_SHIFT (0U)
29043/*! DQ0WBD - DQ0 Write Bit Delay
29044 */
29045#define DDRPHY_DX5BDLR0_DQ0WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX5BDLR0_DQ0WBD_MASK)
29046#define DDRPHY_DX5BDLR0_RESERVED_7_6_MASK (0xC0U)
29047#define DDRPHY_DX5BDLR0_RESERVED_7_6_SHIFT (6U)
29048/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
29049 */
29050#define DDRPHY_DX5BDLR0_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR0_RESERVED_7_6_MASK)
29051#define DDRPHY_DX5BDLR0_DQ1WBD_MASK (0x3F00U)
29052#define DDRPHY_DX5BDLR0_DQ1WBD_SHIFT (8U)
29053/*! DQ1WBD - DQ1 Write Bit Delay
29054 */
29055#define DDRPHY_DX5BDLR0_DQ1WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX5BDLR0_DQ1WBD_MASK)
29056#define DDRPHY_DX5BDLR0_RESERVED_15_14_MASK (0xC000U)
29057#define DDRPHY_DX5BDLR0_RESERVED_15_14_SHIFT (14U)
29058/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
29059 */
29060#define DDRPHY_DX5BDLR0_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR0_RESERVED_15_14_MASK)
29061#define DDRPHY_DX5BDLR0_DQ2WBD_MASK (0x3F0000U)
29062#define DDRPHY_DX5BDLR0_DQ2WBD_SHIFT (16U)
29063/*! DQ2WBD - DQ2 Write Bit Delay
29064 */
29065#define DDRPHY_DX5BDLR0_DQ2WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX5BDLR0_DQ2WBD_MASK)
29066#define DDRPHY_DX5BDLR0_RESERVED_23_22_MASK (0xC00000U)
29067#define DDRPHY_DX5BDLR0_RESERVED_23_22_SHIFT (22U)
29068/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
29069 */
29070#define DDRPHY_DX5BDLR0_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX5BDLR0_RESERVED_23_22_MASK)
29071#define DDRPHY_DX5BDLR0_DQ3WBD_MASK (0x3F000000U)
29072#define DDRPHY_DX5BDLR0_DQ3WBD_SHIFT (24U)
29073/*! DQ3WBD - DQ3 Write Bit Delay
29074 */
29075#define DDRPHY_DX5BDLR0_DQ3WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX5BDLR0_DQ3WBD_MASK)
29076#define DDRPHY_DX5BDLR0_RESERVED_31_30_MASK (0xC0000000U)
29077#define DDRPHY_DX5BDLR0_RESERVED_31_30_SHIFT (30U)
29078/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
29079 */
29080#define DDRPHY_DX5BDLR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX5BDLR0_RESERVED_31_30_MASK)
29081/*! @} */
29082
29083/*! @name DX5BDLR1 - DATX8 n Bit Delay Line Register 1 */
29084/*! @{ */
29085#define DDRPHY_DX5BDLR1_DQ4WBD_MASK (0x3FU)
29086#define DDRPHY_DX5BDLR1_DQ4WBD_SHIFT (0U)
29087/*! DQ4WBD - DQ4 Write Bit Delay
29088 */
29089#define DDRPHY_DX5BDLR1_DQ4WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX5BDLR1_DQ4WBD_MASK)
29090#define DDRPHY_DX5BDLR1_RESERVED_7_6_MASK (0xC0U)
29091#define DDRPHY_DX5BDLR1_RESERVED_7_6_SHIFT (6U)
29092/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
29093 */
29094#define DDRPHY_DX5BDLR1_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR1_RESERVED_7_6_MASK)
29095#define DDRPHY_DX5BDLR1_DQ5WBD_MASK (0x3F00U)
29096#define DDRPHY_DX5BDLR1_DQ5WBD_SHIFT (8U)
29097/*! DQ5WBD - DQ5 Write Bit Delay
29098 */
29099#define DDRPHY_DX5BDLR1_DQ5WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX5BDLR1_DQ5WBD_MASK)
29100#define DDRPHY_DX5BDLR1_RESERVED_15_14_MASK (0xC000U)
29101#define DDRPHY_DX5BDLR1_RESERVED_15_14_SHIFT (14U)
29102/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
29103 */
29104#define DDRPHY_DX5BDLR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR1_RESERVED_15_14_MASK)
29105#define DDRPHY_DX5BDLR1_DQ6WBD_MASK (0x3F0000U)
29106#define DDRPHY_DX5BDLR1_DQ6WBD_SHIFT (16U)
29107/*! DQ6WBD - DQ6 Write Bit Delay
29108 */
29109#define DDRPHY_DX5BDLR1_DQ6WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX5BDLR1_DQ6WBD_MASK)
29110#define DDRPHY_DX5BDLR1_RESERVED_23_22_MASK (0xC00000U)
29111#define DDRPHY_DX5BDLR1_RESERVED_23_22_SHIFT (22U)
29112/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
29113 */
29114#define DDRPHY_DX5BDLR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX5BDLR1_RESERVED_23_22_MASK)
29115#define DDRPHY_DX5BDLR1_DQ7WBD_MASK (0x3F000000U)
29116#define DDRPHY_DX5BDLR1_DQ7WBD_SHIFT (24U)
29117/*! DQ7WBD - DQ7 Write Bit Delay
29118 */
29119#define DDRPHY_DX5BDLR1_DQ7WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX5BDLR1_DQ7WBD_MASK)
29120#define DDRPHY_DX5BDLR1_RESERVED_31_30_MASK (0xC0000000U)
29121#define DDRPHY_DX5BDLR1_RESERVED_31_30_SHIFT (30U)
29122/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
29123 */
29124#define DDRPHY_DX5BDLR1_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX5BDLR1_RESERVED_31_30_MASK)
29125/*! @} */
29126
29127/*! @name DX5BDLR2 - DATX8 n Bit Delay Line Register 2 */
29128/*! @{ */
29129#define DDRPHY_DX5BDLR2_DMWBD_MASK (0x3FU)
29130#define DDRPHY_DX5BDLR2_DMWBD_SHIFT (0U)
29131/*! DMWBD - DM Write Bit Delay
29132 */
29133#define DDRPHY_DX5BDLR2_DMWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_DMWBD_SHIFT)) & DDRPHY_DX5BDLR2_DMWBD_MASK)
29134#define DDRPHY_DX5BDLR2_RESERVED_7_6_MASK (0xC0U)
29135#define DDRPHY_DX5BDLR2_RESERVED_7_6_SHIFT (6U)
29136/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
29137 */
29138#define DDRPHY_DX5BDLR2_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR2_RESERVED_7_6_MASK)
29139#define DDRPHY_DX5BDLR2_DSWBD_MASK (0x3F00U)
29140#define DDRPHY_DX5BDLR2_DSWBD_SHIFT (8U)
29141/*! DSWBD - DQS Write Bit Delay
29142 */
29143#define DDRPHY_DX5BDLR2_DSWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_DSWBD_SHIFT)) & DDRPHY_DX5BDLR2_DSWBD_MASK)
29144#define DDRPHY_DX5BDLR2_RESERVED_15_14_MASK (0xC000U)
29145#define DDRPHY_DX5BDLR2_RESERVED_15_14_SHIFT (14U)
29146/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
29147 */
29148#define DDRPHY_DX5BDLR2_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR2_RESERVED_15_14_MASK)
29149#define DDRPHY_DX5BDLR2_DSOEBD_MASK (0x3F0000U)
29150#define DDRPHY_DX5BDLR2_DSOEBD_SHIFT (16U)
29151/*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay
29152 */
29153#define DDRPHY_DX5BDLR2_DSOEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX5BDLR2_DSOEBD_MASK)
29154#define DDRPHY_DX5BDLR2_RESERVED_23_22_MASK (0xC00000U)
29155#define DDRPHY_DX5BDLR2_RESERVED_23_22_SHIFT (22U)
29156/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
29157 */
29158#define DDRPHY_DX5BDLR2_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX5BDLR2_RESERVED_23_22_MASK)
29159#define DDRPHY_DX5BDLR2_DSNWBD_MASK (0x3F000000U)
29160#define DDRPHY_DX5BDLR2_DSNWBD_SHIFT (24U)
29161/*! DSNWBD - DQSN Write Bit Delay
29162 */
29163#define DDRPHY_DX5BDLR2_DSNWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX5BDLR2_DSNWBD_MASK)
29164#define DDRPHY_DX5BDLR2_RESERVED_31_30_MASK (0xC0000000U)
29165#define DDRPHY_DX5BDLR2_RESERVED_31_30_SHIFT (30U)
29166/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
29167 */
29168#define DDRPHY_DX5BDLR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX5BDLR2_RESERVED_31_30_MASK)
29169/*! @} */
29170
29171/*! @name DX5BDLR3 - DATX8 n Bit Delay Line Register 3 */
29172/*! @{ */
29173#define DDRPHY_DX5BDLR3_DQ0RBD_MASK (0x3FU)
29174#define DDRPHY_DX5BDLR3_DQ0RBD_SHIFT (0U)
29175/*! DQ0RBD - DQ0 Read Bit Delay
29176 */
29177#define DDRPHY_DX5BDLR3_DQ0RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX5BDLR3_DQ0RBD_MASK)
29178#define DDRPHY_DX5BDLR3_RESERVED_7_6_MASK (0xC0U)
29179#define DDRPHY_DX5BDLR3_RESERVED_7_6_SHIFT (6U)
29180/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
29181 */
29182#define DDRPHY_DX5BDLR3_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR3_RESERVED_7_6_MASK)
29183#define DDRPHY_DX5BDLR3_DQ1RBD_MASK (0x3F00U)
29184#define DDRPHY_DX5BDLR3_DQ1RBD_SHIFT (8U)
29185/*! DQ1RBD - DQ1 Read Bit Delay
29186 */
29187#define DDRPHY_DX5BDLR3_DQ1RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX5BDLR3_DQ1RBD_MASK)
29188#define DDRPHY_DX5BDLR3_RESERVED_15_14_MASK (0xC000U)
29189#define DDRPHY_DX5BDLR3_RESERVED_15_14_SHIFT (14U)
29190/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
29191 */
29192#define DDRPHY_DX5BDLR3_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR3_RESERVED_15_14_MASK)
29193#define DDRPHY_DX5BDLR3_DQ2RBD_MASK (0x3F0000U)
29194#define DDRPHY_DX5BDLR3_DQ2RBD_SHIFT (16U)
29195/*! DQ2RBD - DQ2 Read Bit Delay
29196 */
29197#define DDRPHY_DX5BDLR3_DQ2RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX5BDLR3_DQ2RBD_MASK)
29198#define DDRPHY_DX5BDLR3_RESERVED_23_22_MASK (0xC00000U)
29199#define DDRPHY_DX5BDLR3_RESERVED_23_22_SHIFT (22U)
29200/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
29201 */
29202#define DDRPHY_DX5BDLR3_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX5BDLR3_RESERVED_23_22_MASK)
29203#define DDRPHY_DX5BDLR3_DQ3RBD_MASK (0x3F000000U)
29204#define DDRPHY_DX5BDLR3_DQ3RBD_SHIFT (24U)
29205/*! DQ3RBD - DQ3 Read Bit Delay
29206 */
29207#define DDRPHY_DX5BDLR3_DQ3RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX5BDLR3_DQ3RBD_MASK)
29208#define DDRPHY_DX5BDLR3_RESERVED_31_30_MASK (0xC0000000U)
29209#define DDRPHY_DX5BDLR3_RESERVED_31_30_SHIFT (30U)
29210/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
29211 */
29212#define DDRPHY_DX5BDLR3_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX5BDLR3_RESERVED_31_30_MASK)
29213/*! @} */
29214
29215/*! @name DX5BDLR4 - DATX8 n Bit Delay Line Register 4 */
29216/*! @{ */
29217#define DDRPHY_DX5BDLR4_DQ4RBD_MASK (0x3FU)
29218#define DDRPHY_DX5BDLR4_DQ4RBD_SHIFT (0U)
29219/*! DQ4RBD - DQ4 Read Bit Delay
29220 */
29221#define DDRPHY_DX5BDLR4_DQ4RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX5BDLR4_DQ4RBD_MASK)
29222#define DDRPHY_DX5BDLR4_RESERVED_7_6_MASK (0xC0U)
29223#define DDRPHY_DX5BDLR4_RESERVED_7_6_SHIFT (6U)
29224/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
29225 */
29226#define DDRPHY_DX5BDLR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR4_RESERVED_7_6_MASK)
29227#define DDRPHY_DX5BDLR4_DQ5RBD_MASK (0x3F00U)
29228#define DDRPHY_DX5BDLR4_DQ5RBD_SHIFT (8U)
29229/*! DQ5RBD - DQ5 Read Bit Delay
29230 */
29231#define DDRPHY_DX5BDLR4_DQ5RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX5BDLR4_DQ5RBD_MASK)
29232#define DDRPHY_DX5BDLR4_RESERVED_15_14_MASK (0xC000U)
29233#define DDRPHY_DX5BDLR4_RESERVED_15_14_SHIFT (14U)
29234/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
29235 */
29236#define DDRPHY_DX5BDLR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR4_RESERVED_15_14_MASK)
29237#define DDRPHY_DX5BDLR4_DQ6RBD_MASK (0x3F0000U)
29238#define DDRPHY_DX5BDLR4_DQ6RBD_SHIFT (16U)
29239/*! DQ6RBD - DQ6 Read Bit Delay
29240 */
29241#define DDRPHY_DX5BDLR4_DQ6RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX5BDLR4_DQ6RBD_MASK)
29242#define DDRPHY_DX5BDLR4_RESERVED_23_22_MASK (0xC00000U)
29243#define DDRPHY_DX5BDLR4_RESERVED_23_22_SHIFT (22U)
29244/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
29245 */
29246#define DDRPHY_DX5BDLR4_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX5BDLR4_RESERVED_23_22_MASK)
29247#define DDRPHY_DX5BDLR4_DQ7RBD_MASK (0x3F000000U)
29248#define DDRPHY_DX5BDLR4_DQ7RBD_SHIFT (24U)
29249/*! DQ7RBD - DQ7 Read Bit Delay
29250 */
29251#define DDRPHY_DX5BDLR4_DQ7RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX5BDLR4_DQ7RBD_MASK)
29252#define DDRPHY_DX5BDLR4_RESERVED_31_30_MASK (0xC0000000U)
29253#define DDRPHY_DX5BDLR4_RESERVED_31_30_SHIFT (30U)
29254/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
29255 */
29256#define DDRPHY_DX5BDLR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX5BDLR4_RESERVED_31_30_MASK)
29257/*! @} */
29258
29259/*! @name DX5BDLR5 - DATX8 n Bit Delay Line Register 5 */
29260/*! @{ */
29261#define DDRPHY_DX5BDLR5_DMRBD_MASK (0x3FU)
29262#define DDRPHY_DX5BDLR5_DMRBD_SHIFT (0U)
29263/*! DMRBD - DM Read Bit Delay
29264 */
29265#define DDRPHY_DX5BDLR5_DMRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR5_DMRBD_SHIFT)) & DDRPHY_DX5BDLR5_DMRBD_MASK)
29266#define DDRPHY_DX5BDLR5_RESERVED_31_6_MASK (0xFFFFFFC0U)
29267#define DDRPHY_DX5BDLR5_RESERVED_31_6_SHIFT (6U)
29268/*! RESERVED_31_6 - Reserved. Return zeroes on reads.
29269 */
29270#define DDRPHY_DX5BDLR5_RESERVED_31_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX5BDLR5_RESERVED_31_6_MASK)
29271/*! @} */
29272
29273/*! @name DX5BDLR6 - DATX8 n Bit Delay Line Register 6 */
29274/*! @{ */
29275#define DDRPHY_DX5BDLR6_RESERVED_7_0_MASK (0xFFU)
29276#define DDRPHY_DX5BDLR6_RESERVED_7_0_SHIFT (0U)
29277/*! RESERVED_7_0 - Reserved. Return zeroes on reads.
29278 */
29279#define DDRPHY_DX5BDLR6_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX5BDLR6_RESERVED_7_0_MASK)
29280#define DDRPHY_DX5BDLR6_PDRBD_MASK (0x3F00U)
29281#define DDRPHY_DX5BDLR6_PDRBD_SHIFT (8U)
29282/*! PDRBD - Power down receiver Bit Delay
29283 */
29284#define DDRPHY_DX5BDLR6_PDRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR6_PDRBD_SHIFT)) & DDRPHY_DX5BDLR6_PDRBD_MASK)
29285#define DDRPHY_DX5BDLR6_RESERVED_15_14_MASK (0xC000U)
29286#define DDRPHY_DX5BDLR6_RESERVED_15_14_SHIFT (14U)
29287/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
29288 */
29289#define DDRPHY_DX5BDLR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR6_RESERVED_15_14_MASK)
29290#define DDRPHY_DX5BDLR6_TERBD_MASK (0x3F0000U)
29291#define DDRPHY_DX5BDLR6_TERBD_SHIFT (16U)
29292/*! TERBD - Termination Enable Bit Delay
29293 */
29294#define DDRPHY_DX5BDLR6_TERBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR6_TERBD_SHIFT)) & DDRPHY_DX5BDLR6_TERBD_MASK)
29295#define DDRPHY_DX5BDLR6_RESERVED_31_22_MASK (0xFFC00000U)
29296#define DDRPHY_DX5BDLR6_RESERVED_31_22_SHIFT (22U)
29297/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
29298 */
29299#define DDRPHY_DX5BDLR6_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX5BDLR6_RESERVED_31_22_MASK)
29300/*! @} */
29301
29302/*! @name DX5BDLR7 - DATX8 n Bit Delay Line Register 7 */
29303/*! @{ */
29304#define DDRPHY_DX5BDLR7_RESERVED_5_0_MASK (0x3FU)
29305#define DDRPHY_DX5BDLR7_RESERVED_5_0_SHIFT (0U)
29306/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
29307 */
29308#define DDRPHY_DX5BDLR7_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX5BDLR7_RESERVED_5_0_MASK)
29309#define DDRPHY_DX5BDLR7_RESERVED_7_6_MASK (0xC0U)
29310#define DDRPHY_DX5BDLR7_RESERVED_7_6_SHIFT (6U)
29311/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
29312 */
29313#define DDRPHY_DX5BDLR7_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR7_RESERVED_7_6_MASK)
29314#define DDRPHY_DX5BDLR7_RESERVED_13_8_MASK (0x3F00U)
29315#define DDRPHY_DX5BDLR7_RESERVED_13_8_SHIFT (8U)
29316/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
29317 */
29318#define DDRPHY_DX5BDLR7_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX5BDLR7_RESERVED_13_8_MASK)
29319#define DDRPHY_DX5BDLR7_RESERVED_15_14_MASK (0xC000U)
29320#define DDRPHY_DX5BDLR7_RESERVED_15_14_SHIFT (14U)
29321/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
29322 */
29323#define DDRPHY_DX5BDLR7_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR7_RESERVED_15_14_MASK)
29324#define DDRPHY_DX5BDLR7_RESERVED_21_16_MASK (0x3F0000U)
29325#define DDRPHY_DX5BDLR7_RESERVED_21_16_SHIFT (16U)
29326/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
29327 */
29328#define DDRPHY_DX5BDLR7_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX5BDLR7_RESERVED_21_16_MASK)
29329#define DDRPHY_DX5BDLR7_RESERVED_31_22_MASK (0xFFC00000U)
29330#define DDRPHY_DX5BDLR7_RESERVED_31_22_SHIFT (22U)
29331/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
29332 */
29333#define DDRPHY_DX5BDLR7_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX5BDLR7_RESERVED_31_22_MASK)
29334/*! @} */
29335
29336/*! @name DX5BDLR8 - DATX8 n Bit Delay Line Register 8 */
29337/*! @{ */
29338#define DDRPHY_DX5BDLR8_RESERVED_5_0_MASK (0x3FU)
29339#define DDRPHY_DX5BDLR8_RESERVED_5_0_SHIFT (0U)
29340/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
29341 */
29342#define DDRPHY_DX5BDLR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX5BDLR8_RESERVED_5_0_MASK)
29343#define DDRPHY_DX5BDLR8_RESERVED_7_6_MASK (0xC0U)
29344#define DDRPHY_DX5BDLR8_RESERVED_7_6_SHIFT (6U)
29345/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
29346 */
29347#define DDRPHY_DX5BDLR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR8_RESERVED_7_6_MASK)
29348#define DDRPHY_DX5BDLR8_RESERVED_13_8_MASK (0x3F00U)
29349#define DDRPHY_DX5BDLR8_RESERVED_13_8_SHIFT (8U)
29350/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
29351 */
29352#define DDRPHY_DX5BDLR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX5BDLR8_RESERVED_13_8_MASK)
29353#define DDRPHY_DX5BDLR8_RESERVED_15_14_MASK (0xC000U)
29354#define DDRPHY_DX5BDLR8_RESERVED_15_14_SHIFT (14U)
29355/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
29356 */
29357#define DDRPHY_DX5BDLR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR8_RESERVED_15_14_MASK)
29358#define DDRPHY_DX5BDLR8_RESERVED_21_16_MASK (0x3F0000U)
29359#define DDRPHY_DX5BDLR8_RESERVED_21_16_SHIFT (16U)
29360/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
29361 */
29362#define DDRPHY_DX5BDLR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX5BDLR8_RESERVED_21_16_MASK)
29363#define DDRPHY_DX5BDLR8_RESERVED_31_22_MASK (0xFFC00000U)
29364#define DDRPHY_DX5BDLR8_RESERVED_31_22_SHIFT (22U)
29365/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
29366 */
29367#define DDRPHY_DX5BDLR8_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX5BDLR8_RESERVED_31_22_MASK)
29368/*! @} */
29369
29370/*! @name DX5BDLR9 - DATX8 n Bit Delay Line Register 9 */
29371/*! @{ */
29372#define DDRPHY_DX5BDLR9_RESERVED_5_0_MASK (0x3FU)
29373#define DDRPHY_DX5BDLR9_RESERVED_5_0_SHIFT (0U)
29374/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
29375 */
29376#define DDRPHY_DX5BDLR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX5BDLR9_RESERVED_5_0_MASK)
29377#define DDRPHY_DX5BDLR9_RESERVED_7_6_MASK (0xC0U)
29378#define DDRPHY_DX5BDLR9_RESERVED_7_6_SHIFT (6U)
29379/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
29380 */
29381#define DDRPHY_DX5BDLR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX5BDLR9_RESERVED_7_6_MASK)
29382#define DDRPHY_DX5BDLR9_RESERVED_13_8_MASK (0x3F00U)
29383#define DDRPHY_DX5BDLR9_RESERVED_13_8_SHIFT (8U)
29384/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
29385 */
29386#define DDRPHY_DX5BDLR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX5BDLR9_RESERVED_13_8_MASK)
29387#define DDRPHY_DX5BDLR9_RESERVED_15_14_MASK (0xC000U)
29388#define DDRPHY_DX5BDLR9_RESERVED_15_14_SHIFT (14U)
29389/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
29390 */
29391#define DDRPHY_DX5BDLR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX5BDLR9_RESERVED_15_14_MASK)
29392#define DDRPHY_DX5BDLR9_RESERVED_21_16_MASK (0x3F0000U)
29393#define DDRPHY_DX5BDLR9_RESERVED_21_16_SHIFT (16U)
29394/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
29395 */
29396#define DDRPHY_DX5BDLR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX5BDLR9_RESERVED_21_16_MASK)
29397#define DDRPHY_DX5BDLR9_RESERVED_31_22_MASK (0xFFC00000U)
29398#define DDRPHY_DX5BDLR9_RESERVED_31_22_SHIFT (22U)
29399/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
29400 */
29401#define DDRPHY_DX5BDLR9_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX5BDLR9_RESERVED_31_22_MASK)
29402/*! @} */
29403
29404/*! @name DX5LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */
29405/*! @{ */
29406#define DDRPHY_DX5LCDLR0_WLD_MASK (0x1FFU)
29407#define DDRPHY_DX5LCDLR0_WLD_SHIFT (0U)
29408/*! WLD - Write Leveling Delay
29409 */
29410#define DDRPHY_DX5LCDLR0_WLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR0_WLD_SHIFT)) & DDRPHY_DX5LCDLR0_WLD_MASK)
29411#define DDRPHY_DX5LCDLR0_RESERVED_15_9_MASK (0xFE00U)
29412#define DDRPHY_DX5LCDLR0_RESERVED_15_9_SHIFT (9U)
29413/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
29414 */
29415#define DDRPHY_DX5LCDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX5LCDLR0_RESERVED_15_9_MASK)
29416#define DDRPHY_DX5LCDLR0_RESERVED_24_16_MASK (0x1FF0000U)
29417#define DDRPHY_DX5LCDLR0_RESERVED_24_16_SHIFT (16U)
29418/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
29419 */
29420#define DDRPHY_DX5LCDLR0_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX5LCDLR0_RESERVED_24_16_MASK)
29421#define DDRPHY_DX5LCDLR0_RESERVED_31_25_MASK (0xFE000000U)
29422#define DDRPHY_DX5LCDLR0_RESERVED_31_25_SHIFT (25U)
29423/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
29424 */
29425#define DDRPHY_DX5LCDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX5LCDLR0_RESERVED_31_25_MASK)
29426/*! @} */
29427
29428/*! @name DX5LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */
29429/*! @{ */
29430#define DDRPHY_DX5LCDLR1_WDQD_MASK (0x1FFU)
29431#define DDRPHY_DX5LCDLR1_WDQD_SHIFT (0U)
29432/*! WDQD - Write Data Delay
29433 */
29434#define DDRPHY_DX5LCDLR1_WDQD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR1_WDQD_SHIFT)) & DDRPHY_DX5LCDLR1_WDQD_MASK)
29435#define DDRPHY_DX5LCDLR1_RESERVED_15_9_MASK (0xFE00U)
29436#define DDRPHY_DX5LCDLR1_RESERVED_15_9_SHIFT (9U)
29437/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
29438 */
29439#define DDRPHY_DX5LCDLR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX5LCDLR1_RESERVED_15_9_MASK)
29440#define DDRPHY_DX5LCDLR1_RESERVED_24_16_MASK (0x1FF0000U)
29441#define DDRPHY_DX5LCDLR1_RESERVED_24_16_SHIFT (16U)
29442/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
29443 */
29444#define DDRPHY_DX5LCDLR1_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX5LCDLR1_RESERVED_24_16_MASK)
29445#define DDRPHY_DX5LCDLR1_RESERVED_31_25_MASK (0xFE000000U)
29446#define DDRPHY_DX5LCDLR1_RESERVED_31_25_SHIFT (25U)
29447/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
29448 */
29449#define DDRPHY_DX5LCDLR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX5LCDLR1_RESERVED_31_25_MASK)
29450/*! @} */
29451
29452/*! @name DX5LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */
29453/*! @{ */
29454#define DDRPHY_DX5LCDLR2_DQSGD_MASK (0x1FFU)
29455#define DDRPHY_DX5LCDLR2_DQSGD_SHIFT (0U)
29456/*! DQSGD - Read DQS Gating Delay
29457 */
29458#define DDRPHY_DX5LCDLR2_DQSGD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX5LCDLR2_DQSGD_MASK)
29459#define DDRPHY_DX5LCDLR2_RESERVED_15_9_MASK (0xFE00U)
29460#define DDRPHY_DX5LCDLR2_RESERVED_15_9_SHIFT (9U)
29461/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
29462 */
29463#define DDRPHY_DX5LCDLR2_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX5LCDLR2_RESERVED_15_9_MASK)
29464#define DDRPHY_DX5LCDLR2_RESERVED_24_16_MASK (0x1FF0000U)
29465#define DDRPHY_DX5LCDLR2_RESERVED_24_16_SHIFT (16U)
29466/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
29467 */
29468#define DDRPHY_DX5LCDLR2_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX5LCDLR2_RESERVED_24_16_MASK)
29469#define DDRPHY_DX5LCDLR2_RESERVED_31_25_MASK (0xFE000000U)
29470#define DDRPHY_DX5LCDLR2_RESERVED_31_25_SHIFT (25U)
29471/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
29472 */
29473#define DDRPHY_DX5LCDLR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX5LCDLR2_RESERVED_31_25_MASK)
29474/*! @} */
29475
29476/*! @name DX5LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */
29477/*! @{ */
29478#define DDRPHY_DX5LCDLR3_RDQSD_MASK (0x1FFU)
29479#define DDRPHY_DX5LCDLR3_RDQSD_SHIFT (0U)
29480/*! RDQSD - Read DQS Delay
29481 */
29482#define DDRPHY_DX5LCDLR3_RDQSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX5LCDLR3_RDQSD_MASK)
29483#define DDRPHY_DX5LCDLR3_RESERVED_15_9_MASK (0xFE00U)
29484#define DDRPHY_DX5LCDLR3_RESERVED_15_9_SHIFT (9U)
29485/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
29486 */
29487#define DDRPHY_DX5LCDLR3_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX5LCDLR3_RESERVED_15_9_MASK)
29488#define DDRPHY_DX5LCDLR3_RESERVED_24_16_MASK (0x1FF0000U)
29489#define DDRPHY_DX5LCDLR3_RESERVED_24_16_SHIFT (16U)
29490/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
29491 */
29492#define DDRPHY_DX5LCDLR3_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX5LCDLR3_RESERVED_24_16_MASK)
29493#define DDRPHY_DX5LCDLR3_RESERVED_31_25_MASK (0xFE000000U)
29494#define DDRPHY_DX5LCDLR3_RESERVED_31_25_SHIFT (25U)
29495/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
29496 */
29497#define DDRPHY_DX5LCDLR3_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX5LCDLR3_RESERVED_31_25_MASK)
29498/*! @} */
29499
29500/*! @name DX5LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */
29501/*! @{ */
29502#define DDRPHY_DX5LCDLR4_RDQSND_MASK (0x1FFU)
29503#define DDRPHY_DX5LCDLR4_RDQSND_SHIFT (0U)
29504/*! RDQSND - Read DQSN Delay
29505 */
29506#define DDRPHY_DX5LCDLR4_RDQSND(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX5LCDLR4_RDQSND_MASK)
29507#define DDRPHY_DX5LCDLR4_RESERVED_15_9_MASK (0xFE00U)
29508#define DDRPHY_DX5LCDLR4_RESERVED_15_9_SHIFT (9U)
29509/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
29510 */
29511#define DDRPHY_DX5LCDLR4_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX5LCDLR4_RESERVED_15_9_MASK)
29512#define DDRPHY_DX5LCDLR4_RESERVED_24_16_MASK (0x1FF0000U)
29513#define DDRPHY_DX5LCDLR4_RESERVED_24_16_SHIFT (16U)
29514/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
29515 */
29516#define DDRPHY_DX5LCDLR4_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX5LCDLR4_RESERVED_24_16_MASK)
29517#define DDRPHY_DX5LCDLR4_RESERVED_31_25_MASK (0xFE000000U)
29518#define DDRPHY_DX5LCDLR4_RESERVED_31_25_SHIFT (25U)
29519/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
29520 */
29521#define DDRPHY_DX5LCDLR4_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX5LCDLR4_RESERVED_31_25_MASK)
29522/*! @} */
29523
29524/*! @name DX5LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */
29525/*! @{ */
29526#define DDRPHY_DX5LCDLR5_DQSGSD_MASK (0x1FFU)
29527#define DDRPHY_DX5LCDLR5_DQSGSD_SHIFT (0U)
29528/*! DQSGSD - DQS Gating Status Delay
29529 */
29530#define DDRPHY_DX5LCDLR5_DQSGSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX5LCDLR5_DQSGSD_MASK)
29531#define DDRPHY_DX5LCDLR5_RESERVED_15_9_MASK (0xFE00U)
29532#define DDRPHY_DX5LCDLR5_RESERVED_15_9_SHIFT (9U)
29533/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
29534 */
29535#define DDRPHY_DX5LCDLR5_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX5LCDLR5_RESERVED_15_9_MASK)
29536#define DDRPHY_DX5LCDLR5_RESERVED_24_16_MASK (0x1FF0000U)
29537#define DDRPHY_DX5LCDLR5_RESERVED_24_16_SHIFT (16U)
29538/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
29539 */
29540#define DDRPHY_DX5LCDLR5_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX5LCDLR5_RESERVED_24_16_MASK)
29541#define DDRPHY_DX5LCDLR5_RESERVED_31_25_MASK (0xFE000000U)
29542#define DDRPHY_DX5LCDLR5_RESERVED_31_25_SHIFT (25U)
29543/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
29544 */
29545#define DDRPHY_DX5LCDLR5_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX5LCDLR5_RESERVED_31_25_MASK)
29546/*! @} */
29547
29548/*! @name DX5MDLR0 - DATX8 n Master Delay Line Register 0 */
29549/*! @{ */
29550#define DDRPHY_DX5MDLR0_IPRD_MASK (0x1FFU)
29551#define DDRPHY_DX5MDLR0_IPRD_SHIFT (0U)
29552/*! IPRD - Initial Period
29553 */
29554#define DDRPHY_DX5MDLR0_IPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5MDLR0_IPRD_SHIFT)) & DDRPHY_DX5MDLR0_IPRD_MASK)
29555#define DDRPHY_DX5MDLR0_RESERVED_15_9_MASK (0xFE00U)
29556#define DDRPHY_DX5MDLR0_RESERVED_15_9_SHIFT (9U)
29557/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
29558 */
29559#define DDRPHY_DX5MDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX5MDLR0_RESERVED_15_9_MASK)
29560#define DDRPHY_DX5MDLR0_TPRD_MASK (0x1FF0000U)
29561#define DDRPHY_DX5MDLR0_TPRD_SHIFT (16U)
29562/*! TPRD - Target Period
29563 */
29564#define DDRPHY_DX5MDLR0_TPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5MDLR0_TPRD_SHIFT)) & DDRPHY_DX5MDLR0_TPRD_MASK)
29565#define DDRPHY_DX5MDLR0_RESERVED_31_25_MASK (0xFE000000U)
29566#define DDRPHY_DX5MDLR0_RESERVED_31_25_SHIFT (25U)
29567/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
29568 */
29569#define DDRPHY_DX5MDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX5MDLR0_RESERVED_31_25_MASK)
29570/*! @} */
29571
29572/*! @name DX5MDLR1 - DATX8 n Master Delay Line Register 1 */
29573/*! @{ */
29574#define DDRPHY_DX5MDLR1_MDLD_MASK (0x1FFU)
29575#define DDRPHY_DX5MDLR1_MDLD_SHIFT (0U)
29576/*! MDLD - MDL Delay
29577 */
29578#define DDRPHY_DX5MDLR1_MDLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5MDLR1_MDLD_SHIFT)) & DDRPHY_DX5MDLR1_MDLD_MASK)
29579#define DDRPHY_DX5MDLR1_RESERVED_31_9_MASK (0xFFFFFE00U)
29580#define DDRPHY_DX5MDLR1_RESERVED_31_9_SHIFT (9U)
29581/*! RESERVED_31_9 - Reserved. Return zeroes on reads.
29582 */
29583#define DDRPHY_DX5MDLR1_RESERVED_31_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX5MDLR1_RESERVED_31_9_MASK)
29584/*! @} */
29585
29586/*! @name DX5GTR0 - DATX8 n General Timing Register 0 */
29587/*! @{ */
29588#define DDRPHY_DX5GTR0_DGSL_MASK (0x1FU)
29589#define DDRPHY_DX5GTR0_DGSL_SHIFT (0U)
29590/*! DGSL - DQS Gating System Latency
29591 */
29592#define DDRPHY_DX5GTR0_DGSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_DGSL_SHIFT)) & DDRPHY_DX5GTR0_DGSL_MASK)
29593#define DDRPHY_DX5GTR0_RESERVED_7_5_MASK (0xE0U)
29594#define DDRPHY_DX5GTR0_RESERVED_7_5_SHIFT (5U)
29595/*! RESERVED_7_5 - Reserved. Return zeroes on reads.
29596 */
29597#define DDRPHY_DX5GTR0_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX5GTR0_RESERVED_7_5_MASK)
29598#define DDRPHY_DX5GTR0_RESERVED_12_8_MASK (0x1F00U)
29599#define DDRPHY_DX5GTR0_RESERVED_12_8_SHIFT (8U)
29600/*! RESERVED_12_8 - Reserved. Caution, do not write to this register field.
29601 */
29602#define DDRPHY_DX5GTR0_RESERVED_12_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX5GTR0_RESERVED_12_8_MASK)
29603#define DDRPHY_DX5GTR0_RESERVED_15_13_MASK (0xE000U)
29604#define DDRPHY_DX5GTR0_RESERVED_15_13_SHIFT (13U)
29605/*! RESERVED_15_13 - Reserved. Return zeroes on reads.
29606 */
29607#define DDRPHY_DX5GTR0_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX5GTR0_RESERVED_15_13_MASK)
29608#define DDRPHY_DX5GTR0_WLSL_MASK (0xF0000U)
29609#define DDRPHY_DX5GTR0_WLSL_SHIFT (16U)
29610/*! WLSL - Write Leveling System Latency
29611 */
29612#define DDRPHY_DX5GTR0_WLSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_WLSL_SHIFT)) & DDRPHY_DX5GTR0_WLSL_MASK)
29613#define DDRPHY_DX5GTR0_RESERVED_23_20_MASK (0xF00000U)
29614#define DDRPHY_DX5GTR0_RESERVED_23_20_SHIFT (20U)
29615/*! RESERVED_23_20 - Reserved. Caution, do not write to this register field.
29616 */
29617#define DDRPHY_DX5GTR0_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX5GTR0_RESERVED_23_20_MASK)
29618#define DDRPHY_DX5GTR0_WDQSL_MASK (0x7000000U)
29619#define DDRPHY_DX5GTR0_WDQSL_SHIFT (24U)
29620/*! WDQSL - DQ Write Path Latency Pipeline
29621 */
29622#define DDRPHY_DX5GTR0_WDQSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_WDQSL_SHIFT)) & DDRPHY_DX5GTR0_WDQSL_MASK)
29623#define DDRPHY_DX5GTR0_RESERVED_31_24_MASK (0xF8000000U)
29624#define DDRPHY_DX5GTR0_RESERVED_31_24_SHIFT (27U)
29625/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
29626 */
29627#define DDRPHY_DX5GTR0_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX5GTR0_RESERVED_31_24_MASK)
29628/*! @} */
29629
29630/*! @name DX5RSR0 - DATX8 n Rank Status Register 0 */
29631/*! @{ */
29632#define DDRPHY_DX5RSR0_QSGERR_MASK (0xFFFFU)
29633#define DDRPHY_DX5RSR0_QSGERR_SHIFT (0U)
29634/*! QSGERR - DQS Gate Training Error
29635 */
29636#define DDRPHY_DX5RSR0_QSGERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR0_QSGERR_SHIFT)) & DDRPHY_DX5RSR0_QSGERR_MASK)
29637#define DDRPHY_DX5RSR0_RESERVED_31_16_MASK (0xFFFF0000U)
29638#define DDRPHY_DX5RSR0_RESERVED_31_16_SHIFT (16U)
29639/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
29640 */
29641#define DDRPHY_DX5RSR0_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX5RSR0_RESERVED_31_16_MASK)
29642/*! @} */
29643
29644/*! @name DX5RSR1 - DATX8 n Rank Status Register 1 */
29645/*! @{ */
29646#define DDRPHY_DX5RSR1_RDLVLERR_MASK (0xFFFFU)
29647#define DDRPHY_DX5RSR1_RDLVLERR_SHIFT (0U)
29648/*! RDLVLERR - Read Leveling Error
29649 */
29650#define DDRPHY_DX5RSR1_RDLVLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX5RSR1_RDLVLERR_MASK)
29651#define DDRPHY_DX5RSR1_RESERVED_31_16_MASK (0xFFFF0000U)
29652#define DDRPHY_DX5RSR1_RESERVED_31_16_SHIFT (16U)
29653/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
29654 */
29655#define DDRPHY_DX5RSR1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX5RSR1_RESERVED_31_16_MASK)
29656/*! @} */
29657
29658/*! @name DX5RSR2 - DATX8 n Rank Status Register 2 */
29659/*! @{ */
29660#define DDRPHY_DX5RSR2_WLAWN_MASK (0xFFFFU)
29661#define DDRPHY_DX5RSR2_WLAWN_SHIFT (0U)
29662/*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning
29663 */
29664#define DDRPHY_DX5RSR2_WLAWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR2_WLAWN_SHIFT)) & DDRPHY_DX5RSR2_WLAWN_MASK)
29665#define DDRPHY_DX5RSR2_RESERVED_31_16_MASK (0xFFFF0000U)
29666#define DDRPHY_DX5RSR2_RESERVED_31_16_SHIFT (16U)
29667/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
29668 */
29669#define DDRPHY_DX5RSR2_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX5RSR2_RESERVED_31_16_MASK)
29670/*! @} */
29671
29672/*! @name DX5RSR3 - DATX8 n Rank Status Register 3 */
29673/*! @{ */
29674#define DDRPHY_DX5RSR3_WLAERR_MASK (0xFFFFU)
29675#define DDRPHY_DX5RSR3_WLAERR_SHIFT (0U)
29676/*! WLAERR - Write Leveling Adjustment Error
29677 */
29678#define DDRPHY_DX5RSR3_WLAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR3_WLAERR_SHIFT)) & DDRPHY_DX5RSR3_WLAERR_MASK)
29679#define DDRPHY_DX5RSR3_RESERVED_31_16_MASK (0xFFFF0000U)
29680#define DDRPHY_DX5RSR3_RESERVED_31_16_SHIFT (16U)
29681/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
29682 */
29683#define DDRPHY_DX5RSR3_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX5RSR3_RESERVED_31_16_MASK)
29684/*! @} */
29685
29686/*! @name DX5GSR0 - DATX8 n General Status Register 0 */
29687/*! @{ */
29688#define DDRPHY_DX5GSR0_WDQCAL_MASK (0x1U)
29689#define DDRPHY_DX5GSR0_WDQCAL_SHIFT (0U)
29690/*! WDQCAL - Write DQ Calibration
29691 */
29692#define DDRPHY_DX5GSR0_WDQCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_WDQCAL_SHIFT)) & DDRPHY_DX5GSR0_WDQCAL_MASK)
29693#define DDRPHY_DX5GSR0_RDQSCAL_MASK (0x2U)
29694#define DDRPHY_DX5GSR0_RDQSCAL_SHIFT (1U)
29695/*! RDQSCAL - Read DQS Calibration
29696 */
29697#define DDRPHY_DX5GSR0_RDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX5GSR0_RDQSCAL_MASK)
29698#define DDRPHY_DX5GSR0_RDQSNCAL_MASK (0x4U)
29699#define DDRPHY_DX5GSR0_RDQSNCAL_SHIFT (2U)
29700/*! RDQSNCAL - Read DQS# Calibration
29701 */
29702#define DDRPHY_DX5GSR0_RDQSNCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX5GSR0_RDQSNCAL_MASK)
29703#define DDRPHY_DX5GSR0_GDQSCAL_MASK (0x8U)
29704#define DDRPHY_DX5GSR0_GDQSCAL_SHIFT (3U)
29705/*! GDQSCAL - Read DQS gating Calibration
29706 */
29707#define DDRPHY_DX5GSR0_GDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX5GSR0_GDQSCAL_MASK)
29708#define DDRPHY_DX5GSR0_WLCAL_MASK (0x10U)
29709#define DDRPHY_DX5GSR0_WLCAL_SHIFT (4U)
29710/*! WLCAL - Write Leveling Calibration
29711 */
29712#define DDRPHY_DX5GSR0_WLCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_WLCAL_SHIFT)) & DDRPHY_DX5GSR0_WLCAL_MASK)
29713#define DDRPHY_DX5GSR0_WLDONE_MASK (0x20U)
29714#define DDRPHY_DX5GSR0_WLDONE_SHIFT (5U)
29715/*! WLDONE - Write Leveling Done
29716 */
29717#define DDRPHY_DX5GSR0_WLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_WLDONE_SHIFT)) & DDRPHY_DX5GSR0_WLDONE_MASK)
29718#define DDRPHY_DX5GSR0_WLERR_MASK (0x40U)
29719#define DDRPHY_DX5GSR0_WLERR_SHIFT (6U)
29720/*! WLERR - Write Leveling Error
29721 */
29722#define DDRPHY_DX5GSR0_WLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_WLERR_SHIFT)) & DDRPHY_DX5GSR0_WLERR_MASK)
29723#define DDRPHY_DX5GSR0_WLPRD_MASK (0xFF80U)
29724#define DDRPHY_DX5GSR0_WLPRD_SHIFT (7U)
29725/*! WLPRD - Write Leveling Period
29726 */
29727#define DDRPHY_DX5GSR0_WLPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_WLPRD_SHIFT)) & DDRPHY_DX5GSR0_WLPRD_MASK)
29728#define DDRPHY_DX5GSR0_DPLOCK_MASK (0x10000U)
29729#define DDRPHY_DX5GSR0_DPLOCK_SHIFT (16U)
29730/*! DPLOCK - DATX8 PLL Lock
29731 */
29732#define DDRPHY_DX5GSR0_DPLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_DPLOCK_SHIFT)) & DDRPHY_DX5GSR0_DPLOCK_MASK)
29733#define DDRPHY_DX5GSR0_GDQSPRD_MASK (0x3FE0000U)
29734#define DDRPHY_DX5GSR0_GDQSPRD_SHIFT (17U)
29735/*! GDQSPRD - Read DQS gating Period
29736 */
29737#define DDRPHY_DX5GSR0_GDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX5GSR0_GDQSPRD_MASK)
29738#define DDRPHY_DX5GSR0_RESERVED_29_26_MASK (0x3C000000U)
29739#define DDRPHY_DX5GSR0_RESERVED_29_26_SHIFT (26U)
29740/*! RESERVED_29_26 - Reserved. Returns zeroes on reads.
29741 */
29742#define DDRPHY_DX5GSR0_RESERVED_29_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX5GSR0_RESERVED_29_26_MASK)
29743#define DDRPHY_DX5GSR0_WLDQ_MASK (0x40000000U)
29744#define DDRPHY_DX5GSR0_WLDQ_SHIFT (30U)
29745/*! WLDQ - Write Leveling DQ Status
29746 */
29747#define DDRPHY_DX5GSR0_WLDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_WLDQ_SHIFT)) & DDRPHY_DX5GSR0_WLDQ_MASK)
29748#define DDRPHY_DX5GSR0_RESERVED_31_MASK (0x80000000U)
29749#define DDRPHY_DX5GSR0_RESERVED_31_SHIFT (31U)
29750/*! RESERVED_31 - Reserved. Returns zeroes on reads.
29751 */
29752#define DDRPHY_DX5GSR0_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX5GSR0_RESERVED_31_MASK)
29753/*! @} */
29754
29755/*! @name DX5GSR1 - DATX8 n General Status Register 1 */
29756/*! @{ */
29757#define DDRPHY_DX5GSR1_DLTDONE_MASK (0x1U)
29758#define DDRPHY_DX5GSR1_DLTDONE_SHIFT (0U)
29759/*! DLTDONE - Delay Line Test Done
29760 */
29761#define DDRPHY_DX5GSR1_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR1_DLTDONE_SHIFT)) & DDRPHY_DX5GSR1_DLTDONE_MASK)
29762#define DDRPHY_DX5GSR1_DLTCODE_MASK (0x1FFFFFEU)
29763#define DDRPHY_DX5GSR1_DLTCODE_SHIFT (1U)
29764/*! DLTCODE - Delay Line Test Code
29765 */
29766#define DDRPHY_DX5GSR1_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR1_DLTCODE_SHIFT)) & DDRPHY_DX5GSR1_DLTCODE_MASK)
29767#define DDRPHY_DX5GSR1_RESERVED_31_25_MASK (0xFE000000U)
29768#define DDRPHY_DX5GSR1_RESERVED_31_25_SHIFT (25U)
29769/*! RESERVED_31_25 - Reserved. Returns zeroes on reads.
29770 */
29771#define DDRPHY_DX5GSR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX5GSR1_RESERVED_31_25_MASK)
29772/*! @} */
29773
29774/*! @name DX5GSR2 - DATX8 n General Status Register 2 */
29775/*! @{ */
29776#define DDRPHY_DX5GSR2_RDERR_MASK (0x1U)
29777#define DDRPHY_DX5GSR2_RDERR_SHIFT (0U)
29778/*! RDERR - Read Bit Deskew Error
29779 */
29780#define DDRPHY_DX5GSR2_RDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_RDERR_SHIFT)) & DDRPHY_DX5GSR2_RDERR_MASK)
29781#define DDRPHY_DX5GSR2_RDWN_MASK (0x2U)
29782#define DDRPHY_DX5GSR2_RDWN_SHIFT (1U)
29783/*! RDWN - Read Bit Deskew Warning
29784 */
29785#define DDRPHY_DX5GSR2_RDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_RDWN_SHIFT)) & DDRPHY_DX5GSR2_RDWN_MASK)
29786#define DDRPHY_DX5GSR2_WDERR_MASK (0x4U)
29787#define DDRPHY_DX5GSR2_WDERR_SHIFT (2U)
29788/*! WDERR - Write Bit Deskew Error
29789 */
29790#define DDRPHY_DX5GSR2_WDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_WDERR_SHIFT)) & DDRPHY_DX5GSR2_WDERR_MASK)
29791#define DDRPHY_DX5GSR2_WDWN_MASK (0x8U)
29792#define DDRPHY_DX5GSR2_WDWN_SHIFT (3U)
29793/*! WDWN - Write Bit Deskew Warning
29794 */
29795#define DDRPHY_DX5GSR2_WDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_WDWN_SHIFT)) & DDRPHY_DX5GSR2_WDWN_MASK)
29796#define DDRPHY_DX5GSR2_REERR_MASK (0x10U)
29797#define DDRPHY_DX5GSR2_REERR_SHIFT (4U)
29798/*! REERR - Read Eye Centering Error
29799 */
29800#define DDRPHY_DX5GSR2_REERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_REERR_SHIFT)) & DDRPHY_DX5GSR2_REERR_MASK)
29801#define DDRPHY_DX5GSR2_REWN_MASK (0x20U)
29802#define DDRPHY_DX5GSR2_REWN_SHIFT (5U)
29803/*! REWN - Read Eye Centering Warning
29804 */
29805#define DDRPHY_DX5GSR2_REWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_REWN_SHIFT)) & DDRPHY_DX5GSR2_REWN_MASK)
29806#define DDRPHY_DX5GSR2_WEERR_MASK (0x40U)
29807#define DDRPHY_DX5GSR2_WEERR_SHIFT (6U)
29808/*! WEERR - Write Eye Centering Error
29809 */
29810#define DDRPHY_DX5GSR2_WEERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_WEERR_SHIFT)) & DDRPHY_DX5GSR2_WEERR_MASK)
29811#define DDRPHY_DX5GSR2_WEWN_MASK (0x80U)
29812#define DDRPHY_DX5GSR2_WEWN_SHIFT (7U)
29813/*! WEWN - Write Eye Centering Warning
29814 */
29815#define DDRPHY_DX5GSR2_WEWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_WEWN_SHIFT)) & DDRPHY_DX5GSR2_WEWN_MASK)
29816#define DDRPHY_DX5GSR2_ESTAT_MASK (0xF00U)
29817#define DDRPHY_DX5GSR2_ESTAT_SHIFT (8U)
29818/*! ESTAT - Error Status
29819 */
29820#define DDRPHY_DX5GSR2_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_ESTAT_SHIFT)) & DDRPHY_DX5GSR2_ESTAT_MASK)
29821#define DDRPHY_DX5GSR2_DQS2DQERR_MASK (0xFF000U)
29822#define DDRPHY_DX5GSR2_DQS2DQERR_SHIFT (12U)
29823/*! DQS2DQERR - Write DQS2DQ Training Error
29824 */
29825#define DDRPHY_DX5GSR2_DQS2DQERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX5GSR2_DQS2DQERR_MASK)
29826#define DDRPHY_DX5GSR2_SRDERR_MASK (0x100000U)
29827#define DDRPHY_DX5GSR2_SRDERR_SHIFT (20U)
29828/*! SRDERR - Static Read Error
29829 */
29830#define DDRPHY_DX5GSR2_SRDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_SRDERR_SHIFT)) & DDRPHY_DX5GSR2_SRDERR_MASK)
29831#define DDRPHY_DX5GSR2_RESERVED_21_MASK (0x200000U)
29832#define DDRPHY_DX5GSR2_RESERVED_21_SHIFT (21U)
29833/*! RESERVED_21 - Reserved. Return zeroes on reads.
29834 */
29835#define DDRPHY_DX5GSR2_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX5GSR2_RESERVED_21_MASK)
29836#define DDRPHY_DX5GSR2_GSDQSCAL_MASK (0x400000U)
29837#define DDRPHY_DX5GSR2_GSDQSCAL_SHIFT (22U)
29838/*! GSDQSCAL - Read DQS Gating Status Calibration
29839 */
29840#define DDRPHY_DX5GSR2_GSDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX5GSR2_GSDQSCAL_MASK)
29841#define DDRPHY_DX5GSR2_GSDQSPRD_MASK (0xFF800000U)
29842#define DDRPHY_DX5GSR2_GSDQSPRD_SHIFT (23U)
29843/*! GSDQSPRD - Read DQS gating Status Period
29844 */
29845#define DDRPHY_DX5GSR2_GSDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX5GSR2_GSDQSPRD_MASK)
29846/*! @} */
29847
29848/*! @name DX5GSR3 - DATX8 n General Status Register 3 */
29849/*! @{ */
29850#define DDRPHY_DX5GSR3_SRDPC_MASK (0x3U)
29851#define DDRPHY_DX5GSR3_SRDPC_SHIFT (0U)
29852/*! SRDPC - Static Read Delay Pass Count
29853 */
29854#define DDRPHY_DX5GSR3_SRDPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_SRDPC_SHIFT)) & DDRPHY_DX5GSR3_SRDPC_MASK)
29855#define DDRPHY_DX5GSR3_RESERVED_7_2_MASK (0xFCU)
29856#define DDRPHY_DX5GSR3_RESERVED_7_2_SHIFT (2U)
29857/*! RESERVED_7_2 - Reserved. Return zeroes on reads.
29858 */
29859#define DDRPHY_DX5GSR3_RESERVED_7_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX5GSR3_RESERVED_7_2_MASK)
29860#define DDRPHY_DX5GSR3_HVERR_MASK (0xF00U)
29861#define DDRPHY_DX5GSR3_HVERR_SHIFT (8U)
29862/*! HVERR - Host VREF Training Error
29863 */
29864#define DDRPHY_DX5GSR3_HVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_HVERR_SHIFT)) & DDRPHY_DX5GSR3_HVERR_MASK)
29865#define DDRPHY_DX5GSR3_HVWRN_MASK (0xF000U)
29866#define DDRPHY_DX5GSR3_HVWRN_SHIFT (12U)
29867/*! HVWRN - Host VREF Training Warning
29868 */
29869#define DDRPHY_DX5GSR3_HVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_HVWRN_SHIFT)) & DDRPHY_DX5GSR3_HVWRN_MASK)
29870#define DDRPHY_DX5GSR3_DVERR_MASK (0xF0000U)
29871#define DDRPHY_DX5GSR3_DVERR_SHIFT (16U)
29872/*! DVERR - DRAM VREF Training Error
29873 */
29874#define DDRPHY_DX5GSR3_DVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_DVERR_SHIFT)) & DDRPHY_DX5GSR3_DVERR_MASK)
29875#define DDRPHY_DX5GSR3_DVWRN_MASK (0xF00000U)
29876#define DDRPHY_DX5GSR3_DVWRN_SHIFT (20U)
29877/*! DVWRN - DRAM VREF Training Warning
29878 */
29879#define DDRPHY_DX5GSR3_DVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_DVWRN_SHIFT)) & DDRPHY_DX5GSR3_DVWRN_MASK)
29880#define DDRPHY_DX5GSR3_ESTAT_MASK (0x7000000U)
29881#define DDRPHY_DX5GSR3_ESTAT_SHIFT (24U)
29882/*! ESTAT - VREF Training Error Status Code
29883 */
29884#define DDRPHY_DX5GSR3_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_ESTAT_SHIFT)) & DDRPHY_DX5GSR3_ESTAT_MASK)
29885#define DDRPHY_DX5GSR3_RESERVED_31_27_MASK (0xF8000000U)
29886#define DDRPHY_DX5GSR3_RESERVED_31_27_SHIFT (27U)
29887/*! RESERVED_31_27 - Reserved. Return zeroes on reads.
29888 */
29889#define DDRPHY_DX5GSR3_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX5GSR3_RESERVED_31_27_MASK)
29890/*! @} */
29891
29892/*! @name DX5GSR4 - DATX8 n General Status Register 4 */
29893/*! @{ */
29894#define DDRPHY_DX5GSR4_RESERVED_0_MASK (0x1U)
29895#define DDRPHY_DX5GSR4_RESERVED_0_SHIFT (0U)
29896/*! RESERVED_0 - Reserved. Return zeroes on reads.
29897 */
29898#define DDRPHY_DX5GSR4_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_0_MASK)
29899#define DDRPHY_DX5GSR4_RESERVED_1_MASK (0x2U)
29900#define DDRPHY_DX5GSR4_RESERVED_1_SHIFT (1U)
29901/*! RESERVED_1 - Reserved. Return zeroes on reads.
29902 */
29903#define DDRPHY_DX5GSR4_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_1_MASK)
29904#define DDRPHY_DX5GSR4_RESERVED_2_MASK (0x4U)
29905#define DDRPHY_DX5GSR4_RESERVED_2_SHIFT (2U)
29906/*! RESERVED_2 - Reserved. Return zeroes on reads.
29907 */
29908#define DDRPHY_DX5GSR4_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_2_MASK)
29909#define DDRPHY_DX5GSR4_RESERVED_3_MASK (0x8U)
29910#define DDRPHY_DX5GSR4_RESERVED_3_SHIFT (3U)
29911/*! RESERVED_3 - Reserved. Return zeroes on reads.
29912 */
29913#define DDRPHY_DX5GSR4_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_3_MASK)
29914#define DDRPHY_DX5GSR4_RESERVED_4_MASK (0x10U)
29915#define DDRPHY_DX5GSR4_RESERVED_4_SHIFT (4U)
29916/*! RESERVED_4 - Reserved. Return zeroes on reads.
29917 */
29918#define DDRPHY_DX5GSR4_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_4_MASK)
29919#define DDRPHY_DX5GSR4_RESERVED_5_MASK (0x20U)
29920#define DDRPHY_DX5GSR4_RESERVED_5_SHIFT (5U)
29921/*! RESERVED_5 - Reserved. Return zeroes on reads.
29922 */
29923#define DDRPHY_DX5GSR4_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_5_MASK)
29924#define DDRPHY_DX5GSR4_RESERVED_6_MASK (0x40U)
29925#define DDRPHY_DX5GSR4_RESERVED_6_SHIFT (6U)
29926/*! RESERVED_6 - Reserved. Return zeroes on reads.
29927 */
29928#define DDRPHY_DX5GSR4_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_6_MASK)
29929#define DDRPHY_DX5GSR4_RESERVED_15_7_MASK (0xFF80U)
29930#define DDRPHY_DX5GSR4_RESERVED_15_7_SHIFT (7U)
29931/*! RESERVED_15_7 - Reserved. Return zeroes on reads.
29932 */
29933#define DDRPHY_DX5GSR4_RESERVED_15_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_15_7_MASK)
29934#define DDRPHY_DX5GSR4_RESERVED_16_MASK (0x10000U)
29935#define DDRPHY_DX5GSR4_RESERVED_16_SHIFT (16U)
29936/*! RESERVED_16 - Reserved. Return zeroes on reads.
29937 */
29938#define DDRPHY_DX5GSR4_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_16_MASK)
29939#define DDRPHY_DX5GSR4_RESERVED_25_17_MASK (0x3FE0000U)
29940#define DDRPHY_DX5GSR4_RESERVED_25_17_SHIFT (17U)
29941/*! RESERVED_25_17 - Reserved. Return zeroes on reads.
29942 */
29943#define DDRPHY_DX5GSR4_RESERVED_25_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_25_17_MASK)
29944#define DDRPHY_DX5GSR4_RESERVED_31_26_MASK (0xFC000000U)
29945#define DDRPHY_DX5GSR4_RESERVED_31_26_SHIFT (26U)
29946/*! RESERVED_31_26 - Reserved. Returns zeroes on reads.
29947 */
29948#define DDRPHY_DX5GSR4_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX5GSR4_RESERVED_31_26_MASK)
29949/*! @} */
29950
29951/*! @name DX5GSR5 - DATX8 n General Status Register 5 */
29952/*! @{ */
29953#define DDRPHY_DX5GSR5_RESERVED_0_MASK (0x1U)
29954#define DDRPHY_DX5GSR5_RESERVED_0_SHIFT (0U)
29955/*! RESERVED_0 - Reserved. Return zeroes on reads.
29956 */
29957#define DDRPHY_DX5GSR5_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_0_MASK)
29958#define DDRPHY_DX5GSR5_RESERVED_1_MASK (0x2U)
29959#define DDRPHY_DX5GSR5_RESERVED_1_SHIFT (1U)
29960/*! RESERVED_1 - Reserved. Return zeroes on reads.
29961 */
29962#define DDRPHY_DX5GSR5_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_1_MASK)
29963#define DDRPHY_DX5GSR5_RESERVED_2_MASK (0x4U)
29964#define DDRPHY_DX5GSR5_RESERVED_2_SHIFT (2U)
29965/*! RESERVED_2 - Reserved. Return zeroes on reads.
29966 */
29967#define DDRPHY_DX5GSR5_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_2_MASK)
29968#define DDRPHY_DX5GSR5_RESERVED_3_MASK (0x8U)
29969#define DDRPHY_DX5GSR5_RESERVED_3_SHIFT (3U)
29970/*! RESERVED_3 - Reserved. Return zeroes on reads.
29971 */
29972#define DDRPHY_DX5GSR5_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_3_MASK)
29973#define DDRPHY_DX5GSR5_RESERVED_4_MASK (0x10U)
29974#define DDRPHY_DX5GSR5_RESERVED_4_SHIFT (4U)
29975/*! RESERVED_4 - Reserved. Return zeroes on reads.
29976 */
29977#define DDRPHY_DX5GSR5_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_4_MASK)
29978#define DDRPHY_DX5GSR5_RESERVED_5_MASK (0x20U)
29979#define DDRPHY_DX5GSR5_RESERVED_5_SHIFT (5U)
29980/*! RESERVED_5 - Reserved. Return zeroes on reads.
29981 */
29982#define DDRPHY_DX5GSR5_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_5_MASK)
29983#define DDRPHY_DX5GSR5_RESERVED_6_MASK (0x40U)
29984#define DDRPHY_DX5GSR5_RESERVED_6_SHIFT (6U)
29985/*! RESERVED_6 - Reserved. Return zeroes on reads.
29986 */
29987#define DDRPHY_DX5GSR5_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_6_MASK)
29988#define DDRPHY_DX5GSR5_RESERVED_7_MASK (0x80U)
29989#define DDRPHY_DX5GSR5_RESERVED_7_SHIFT (7U)
29990/*! RESERVED_7 - Reserved. Return zeroes on reads.
29991 */
29992#define DDRPHY_DX5GSR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_7_MASK)
29993#define DDRPHY_DX5GSR5_RESERVED_11_8_MASK (0xF00U)
29994#define DDRPHY_DX5GSR5_RESERVED_11_8_SHIFT (8U)
29995/*! RESERVED_11_8 - Reserved. Return zeroes on reads.
29996 */
29997#define DDRPHY_DX5GSR5_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_11_8_MASK)
29998#define DDRPHY_DX5GSR5_RESERVED_19_12_MASK (0xFF000U)
29999#define DDRPHY_DX5GSR5_RESERVED_19_12_SHIFT (12U)
30000/*! RESERVED_19_12 - Reserved. Return zeroes on reads.
30001 */
30002#define DDRPHY_DX5GSR5_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_19_12_MASK)
30003#define DDRPHY_DX5GSR5_RESERVED_20_MASK (0x100000U)
30004#define DDRPHY_DX5GSR5_RESERVED_20_SHIFT (20U)
30005/*! RESERVED_20 - Reserved. Return zeroes on reads.
30006 */
30007#define DDRPHY_DX5GSR5_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_20_MASK)
30008#define DDRPHY_DX5GSR5_RESERVED_21_MASK (0x200000U)
30009#define DDRPHY_DX5GSR5_RESERVED_21_SHIFT (21U)
30010/*! RESERVED_21 - Reserved. Return zeroes on reads.
30011 */
30012#define DDRPHY_DX5GSR5_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_21_MASK)
30013#define DDRPHY_DX5GSR5_RESERVED_22_MASK (0x400000U)
30014#define DDRPHY_DX5GSR5_RESERVED_22_SHIFT (22U)
30015/*! RESERVED_22 - Reserved. Return zeroes on reads.
30016 */
30017#define DDRPHY_DX5GSR5_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_22_MASK)
30018#define DDRPHY_DX5GSR5_RESERVED_31_23_MASK (0xFF800000U)
30019#define DDRPHY_DX5GSR5_RESERVED_31_23_SHIFT (23U)
30020/*! RESERVED_31_23 - Reserved. Return zeroes on reads.
30021 */
30022#define DDRPHY_DX5GSR5_RESERVED_31_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX5GSR5_RESERVED_31_23_MASK)
30023/*! @} */
30024
30025/*! @name DX5GSR6 - DATX8 n General Status Register 6 */
30026/*! @{ */
30027#define DDRPHY_DX5GSR6_RESERVED_1_0_MASK (0x3U)
30028#define DDRPHY_DX5GSR6_RESERVED_1_0_SHIFT (0U)
30029/*! RESERVED_1_0 - Reserved. Return zeroes on reads.
30030 */
30031#define DDRPHY_DX5GSR6_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_1_0_MASK)
30032#define DDRPHY_DX5GSR6_RESERVED_3_2_MASK (0xCU)
30033#define DDRPHY_DX5GSR6_RESERVED_3_2_SHIFT (2U)
30034/*! RESERVED_3_2 - Reserved. Return zeroes on reads.
30035 */
30036#define DDRPHY_DX5GSR6_RESERVED_3_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_3_2_MASK)
30037#define DDRPHY_DX5GSR6_RESERVED_7_4_MASK (0xF0U)
30038#define DDRPHY_DX5GSR6_RESERVED_7_4_SHIFT (4U)
30039/*! RESERVED_7_4 - Reserved. Return zeroes on reads.
30040 */
30041#define DDRPHY_DX5GSR6_RESERVED_7_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_7_4_MASK)
30042#define DDRPHY_DX5GSR6_RESERVED_11_8_MASK (0xF00U)
30043#define DDRPHY_DX5GSR6_RESERVED_11_8_SHIFT (8U)
30044/*! RESERVED_11_8 - Reserved. Return zeroes on reads.
30045 */
30046#define DDRPHY_DX5GSR6_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_11_8_MASK)
30047#define DDRPHY_DX5GSR6_RESERVED_15_12_MASK (0xF000U)
30048#define DDRPHY_DX5GSR6_RESERVED_15_12_SHIFT (12U)
30049/*! RESERVED_15_12 - Reserved. Return zeroes on reads.
30050 */
30051#define DDRPHY_DX5GSR6_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_15_12_MASK)
30052#define DDRPHY_DX5GSR6_RESERVED_19_15_MASK (0xF0000U)
30053#define DDRPHY_DX5GSR6_RESERVED_19_15_SHIFT (16U)
30054/*! RESERVED_19_15 - Reserved. Return zeroes on reads.
30055 */
30056#define DDRPHY_DX5GSR6_RESERVED_19_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_19_15_MASK)
30057#define DDRPHY_DX5GSR6_RESERVED_23_20_MASK (0xF00000U)
30058#define DDRPHY_DX5GSR6_RESERVED_23_20_SHIFT (20U)
30059/*! RESERVED_23_20 - Reserved. Return zeroes on reads.
30060 */
30061#define DDRPHY_DX5GSR6_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_23_20_MASK)
30062#define DDRPHY_DX5GSR6_RESERVED_31_24_MASK (0xFF000000U)
30063#define DDRPHY_DX5GSR6_RESERVED_31_24_SHIFT (24U)
30064/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
30065 */
30066#define DDRPHY_DX5GSR6_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX5GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX5GSR6_RESERVED_31_24_MASK)
30067/*! @} */
30068
30069/*! @name DX6GCR0 - DATX8 n General Configuration Register 0 */
30070/*! @{ */
30071#define DDRPHY_DX6GCR0_RESERVED_1_0_MASK (0x3U)
30072#define DDRPHY_DX6GCR0_RESERVED_1_0_SHIFT (0U)
30073/*! RESERVED_1_0 - Reserved. Return zeroes on reads.
30074 */
30075#define DDRPHY_DX6GCR0_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX6GCR0_RESERVED_1_0_MASK)
30076#define DDRPHY_DX6GCR0_DQSGOE_MASK (0x4U)
30077#define DDRPHY_DX6GCR0_DQSGOE_SHIFT (2U)
30078/*! DQSGOE - DQSG Output Enable
30079 */
30080#define DDRPHY_DX6GCR0_DQSGOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSGOE_SHIFT)) & DDRPHY_DX6GCR0_DQSGOE_MASK)
30081#define DDRPHY_DX6GCR0_DQSGODT_MASK (0x8U)
30082#define DDRPHY_DX6GCR0_DQSGODT_SHIFT (3U)
30083/*! DQSGODT - DQSG On-Die Termination
30084 */
30085#define DDRPHY_DX6GCR0_DQSGODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSGODT_SHIFT)) & DDRPHY_DX6GCR0_DQSGODT_MASK)
30086#define DDRPHY_DX6GCR0_RESERVED_4_MASK (0x10U)
30087#define DDRPHY_DX6GCR0_RESERVED_4_SHIFT (4U)
30088/*! RESERVED_4 - Reserved. Return zeroes on reads.
30089 */
30090#define DDRPHY_DX6GCR0_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX6GCR0_RESERVED_4_MASK)
30091#define DDRPHY_DX6GCR0_DQSGPDR_MASK (0x20U)
30092#define DDRPHY_DX6GCR0_DQSGPDR_SHIFT (5U)
30093/*! DQSGPDR - DQSG Power Down Receiver
30094 */
30095#define DDRPHY_DX6GCR0_DQSGPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX6GCR0_DQSGPDR_MASK)
30096#define DDRPHY_DX6GCR0_DQSRPD_MASK (0x40U)
30097#define DDRPHY_DX6GCR0_DQSRPD_SHIFT (6U)
30098/*! DQSRPD - DQSR Power Down
30099 */
30100#define DDRPHY_DX6GCR0_DQSRPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSRPD_SHIFT)) & DDRPHY_DX6GCR0_DQSRPD_MASK)
30101#define DDRPHY_DX6GCR0_CPDRSHFT_MASK (0x180U)
30102#define DDRPHY_DX6GCR0_CPDRSHFT_SHIFT (7U)
30103/*! CPDRSHFT - Configurable PDR Phase Shift
30104 */
30105#define DDRPHY_DX6GCR0_CPDRSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX6GCR0_CPDRSHFT_MASK)
30106#define DDRPHY_DX6GCR0_RTTOH_MASK (0x600U)
30107#define DDRPHY_DX6GCR0_RTTOH_SHIFT (9U)
30108/*! RTTOH - RTT Output Hold
30109 */
30110#define DDRPHY_DX6GCR0_RTTOH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_RTTOH_SHIFT)) & DDRPHY_DX6GCR0_RTTOH_MASK)
30111#define DDRPHY_DX6GCR0_RTTOAL_MASK (0x800U)
30112#define DDRPHY_DX6GCR0_RTTOAL_SHIFT (11U)
30113/*! RTTOAL - RTT On Additive Latency
30114 */
30115#define DDRPHY_DX6GCR0_RTTOAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_RTTOAL_SHIFT)) & DDRPHY_DX6GCR0_RTTOAL_MASK)
30116#define DDRPHY_DX6GCR0_DQSSEPDR_MASK (0x1000U)
30117#define DDRPHY_DX6GCR0_DQSSEPDR_SHIFT (12U)
30118/*! DQSSEPDR - DQSSE Power Down Receiver
30119 */
30120#define DDRPHY_DX6GCR0_DQSSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX6GCR0_DQSSEPDR_MASK)
30121#define DDRPHY_DX6GCR0_DQSNSEPDR_MASK (0x2000U)
30122#define DDRPHY_DX6GCR0_DQSNSEPDR_SHIFT (13U)
30123/*! DQSNSEPDR - DQSNSE Power Down Receiver
30124 */
30125#define DDRPHY_DX6GCR0_DQSNSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX6GCR0_DQSNSEPDR_MASK)
30126#define DDRPHY_DX6GCR0_RESERVED_19_14_MASK (0xFC000U)
30127#define DDRPHY_DX6GCR0_RESERVED_19_14_SHIFT (14U)
30128/*! RESERVED_19_14 - Reserved. Return zeroes on reads.
30129 */
30130#define DDRPHY_DX6GCR0_RESERVED_19_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX6GCR0_RESERVED_19_14_MASK)
30131#define DDRPHY_DX6GCR0_RDDLY_MASK (0xF00000U)
30132#define DDRPHY_DX6GCR0_RDDLY_SHIFT (20U)
30133/*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
30134 */
30135#define DDRPHY_DX6GCR0_RDDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_RDDLY_SHIFT)) & DDRPHY_DX6GCR0_RDDLY_MASK)
30136#define DDRPHY_DX6GCR0_DQSDCC_MASK (0xF000000U)
30137#define DDRPHY_DX6GCR0_DQSDCC_SHIFT (24U)
30138/*! DQSDCC - DQS Duty Cycle Correction
30139 */
30140#define DDRPHY_DX6GCR0_DQSDCC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_DQSDCC_SHIFT)) & DDRPHY_DX6GCR0_DQSDCC_MASK)
30141#define DDRPHY_DX6GCR0_CODTSHFT_MASK (0x30000000U)
30142#define DDRPHY_DX6GCR0_CODTSHFT_SHIFT (28U)
30143/*! CODTSHFT - Configurable ODT(TE) Phase Shift
30144 */
30145#define DDRPHY_DX6GCR0_CODTSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX6GCR0_CODTSHFT_MASK)
30146#define DDRPHY_DX6GCR0_MDLEN_MASK (0x40000000U)
30147#define DDRPHY_DX6GCR0_MDLEN_SHIFT (30U)
30148/*! MDLEN - Master Delay Line Enable
30149 */
30150#define DDRPHY_DX6GCR0_MDLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_MDLEN_SHIFT)) & DDRPHY_DX6GCR0_MDLEN_MASK)
30151#define DDRPHY_DX6GCR0_CALBYP_MASK (0x80000000U)
30152#define DDRPHY_DX6GCR0_CALBYP_SHIFT (31U)
30153/*! CALBYP - Calibration Bypass
30154 */
30155#define DDRPHY_DX6GCR0_CALBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR0_CALBYP_SHIFT)) & DDRPHY_DX6GCR0_CALBYP_MASK)
30156/*! @} */
30157
30158/*! @name DX6GCR1 - DATX8 n General Configuration Register 1 */
30159/*! @{ */
30160#define DDRPHY_DX6GCR1_DQEN_MASK (0xFFU)
30161#define DDRPHY_DX6GCR1_DQEN_SHIFT (0U)
30162/*! DQEN - Enables DQ corresponding to each bit in a byte
30163 */
30164#define DDRPHY_DX6GCR1_DQEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_DQEN_SHIFT)) & DDRPHY_DX6GCR1_DQEN_MASK)
30165#define DDRPHY_DX6GCR1_DMEN_MASK (0x100U)
30166#define DDRPHY_DX6GCR1_DMEN_SHIFT (8U)
30167/*! DMEN - Enables DM pin in a byte lane
30168 */
30169#define DDRPHY_DX6GCR1_DMEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_DMEN_SHIFT)) & DDRPHY_DX6GCR1_DMEN_MASK)
30170#define DDRPHY_DX6GCR1_DSEN_MASK (0x200U)
30171#define DDRPHY_DX6GCR1_DSEN_SHIFT (9U)
30172/*! DSEN - Enables Write Data strobe in a byte lane
30173 */
30174#define DDRPHY_DX6GCR1_DSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_DSEN_SHIFT)) & DDRPHY_DX6GCR1_DSEN_MASK)
30175#define DDRPHY_DX6GCR1_TEEN_MASK (0x400U)
30176#define DDRPHY_DX6GCR1_TEEN_SHIFT (10U)
30177/*! TEEN - Enables ODT/TE in a byte lane
30178 */
30179#define DDRPHY_DX6GCR1_TEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_TEEN_SHIFT)) & DDRPHY_DX6GCR1_TEEN_MASK)
30180#define DDRPHY_DX6GCR1_PDREN_MASK (0x800U)
30181#define DDRPHY_DX6GCR1_PDREN_SHIFT (11U)
30182/*! PDREN - Enables PDR in a byte lane
30183 */
30184#define DDRPHY_DX6GCR1_PDREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_PDREN_SHIFT)) & DDRPHY_DX6GCR1_PDREN_MASK)
30185#define DDRPHY_DX6GCR1_OEEN_MASK (0x1000U)
30186#define DDRPHY_DX6GCR1_OEEN_SHIFT (12U)
30187/*! OEEN - Enables Read Data Strobe in a byte lane
30188 */
30189#define DDRPHY_DX6GCR1_OEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_OEEN_SHIFT)) & DDRPHY_DX6GCR1_OEEN_MASK)
30190#define DDRPHY_DX6GCR1_QSSEL_MASK (0x2000U)
30191#define DDRPHY_DX6GCR1_QSSEL_SHIFT (13U)
30192/*! QSSEL - Select the delayed or non-delayed read data strobe
30193 */
30194#define DDRPHY_DX6GCR1_QSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_QSSEL_SHIFT)) & DDRPHY_DX6GCR1_QSSEL_MASK)
30195#define DDRPHY_DX6GCR1_QSNSEL_MASK (0x4000U)
30196#define DDRPHY_DX6GCR1_QSNSEL_SHIFT (14U)
30197/*! QSNSEL - Select the delayed or non-delayed read data strobe #
30198 */
30199#define DDRPHY_DX6GCR1_QSNSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_QSNSEL_SHIFT)) & DDRPHY_DX6GCR1_QSNSEL_MASK)
30200#define DDRPHY_DX6GCR1_RESERVED_15_MASK (0x8000U)
30201#define DDRPHY_DX6GCR1_RESERVED_15_SHIFT (15U)
30202/*! RESERVED_15 - Reserved. Returns zeroes on reads.
30203 */
30204#define DDRPHY_DX6GCR1_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX6GCR1_RESERVED_15_MASK)
30205#define DDRPHY_DX6GCR1_DXPDRMODE_MASK (0xFFFF0000U)
30206#define DDRPHY_DX6GCR1_DXPDRMODE_SHIFT (16U)
30207/*! DXPDRMODE - Enables the PDR mode for DQ[7:0]
30208 */
30209#define DDRPHY_DX6GCR1_DXPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX6GCR1_DXPDRMODE_MASK)
30210/*! @} */
30211
30212/*! @name DX6GCR2 - DATX8 n General Configuration Register 2 */
30213/*! @{ */
30214#define DDRPHY_DX6GCR2_DXTEMODE_MASK (0xFFFFU)
30215#define DDRPHY_DX6GCR2_DXTEMODE_SHIFT (0U)
30216/*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0]
30217 */
30218#define DDRPHY_DX6GCR2_DXTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX6GCR2_DXTEMODE_MASK)
30219#define DDRPHY_DX6GCR2_DXOEMODE_MASK (0xFFFF0000U)
30220#define DDRPHY_DX6GCR2_DXOEMODE_SHIFT (16U)
30221/*! DXOEMODE - Enables the OE mode values for DQ[7:0]
30222 */
30223#define DDRPHY_DX6GCR2_DXOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX6GCR2_DXOEMODE_MASK)
30224/*! @} */
30225
30226/*! @name DX6GCR3 - DATX8 n General Configuration Register 3 */
30227/*! @{ */
30228#define DDRPHY_DX6GCR3_WDMBVT_MASK (0x1U)
30229#define DDRPHY_DX6GCR3_WDMBVT_SHIFT (0U)
30230/*! WDMBVT - Write Data Mask BDL VT Compensation
30231 */
30232#define DDRPHY_DX6GCR3_WDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_WDMBVT_SHIFT)) & DDRPHY_DX6GCR3_WDMBVT_MASK)
30233#define DDRPHY_DX6GCR3_RDMBVT_MASK (0x2U)
30234#define DDRPHY_DX6GCR3_RDMBVT_SHIFT (1U)
30235/*! RDMBVT - Read Data Mask BDL VT Compensation
30236 */
30237#define DDRPHY_DX6GCR3_RDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_RDMBVT_SHIFT)) & DDRPHY_DX6GCR3_RDMBVT_MASK)
30238#define DDRPHY_DX6GCR3_DSPDRMODE_MASK (0xCU)
30239#define DDRPHY_DX6GCR3_DSPDRMODE_SHIFT (2U)
30240/*! DSPDRMODE - Enables the PDR mode values for DQS.
30241 */
30242#define DDRPHY_DX6GCR3_DSPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX6GCR3_DSPDRMODE_MASK)
30243#define DDRPHY_DX6GCR3_DSTEMODE_MASK (0x30U)
30244#define DDRPHY_DX6GCR3_DSTEMODE_SHIFT (4U)
30245/*! DSTEMODE - Enables the TE mode values for DQS.
30246 */
30247#define DDRPHY_DX6GCR3_DSTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX6GCR3_DSTEMODE_MASK)
30248#define DDRPHY_DX6GCR3_DSOEMODE_MASK (0xC0U)
30249#define DDRPHY_DX6GCR3_DSOEMODE_SHIFT (6U)
30250/*! DSOEMODE - Enables the OE mode values for DQS.
30251 */
30252#define DDRPHY_DX6GCR3_DSOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX6GCR3_DSOEMODE_MASK)
30253#define DDRPHY_DX6GCR3_WDSBVT_MASK (0x100U)
30254#define DDRPHY_DX6GCR3_WDSBVT_SHIFT (8U)
30255/*! WDSBVT - Write Data Strobe BDL VT Compensation
30256 */
30257#define DDRPHY_DX6GCR3_WDSBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_WDSBVT_SHIFT)) & DDRPHY_DX6GCR3_WDSBVT_MASK)
30258#define DDRPHY_DX6GCR3_RESERVED_9_MASK (0x200U)
30259#define DDRPHY_DX6GCR3_RESERVED_9_SHIFT (9U)
30260/*! RESERVED_9 - Reserved. Returns zeroes on reads.
30261 */
30262#define DDRPHY_DX6GCR3_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX6GCR3_RESERVED_9_MASK)
30263#define DDRPHY_DX6GCR3_DMPDRMODE_MASK (0xC00U)
30264#define DDRPHY_DX6GCR3_DMPDRMODE_SHIFT (10U)
30265/*! DMPDRMODE - Enables the PDR mode values for DM.
30266 */
30267#define DDRPHY_DX6GCR3_DMPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX6GCR3_DMPDRMODE_MASK)
30268#define DDRPHY_DX6GCR3_DMTEMODE_MASK (0x3000U)
30269#define DDRPHY_DX6GCR3_DMTEMODE_SHIFT (12U)
30270/*! DMTEMODE - Enables the TE mode values for DM.
30271 */
30272#define DDRPHY_DX6GCR3_DMTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX6GCR3_DMTEMODE_MASK)
30273#define DDRPHY_DX6GCR3_DMOEMODE_MASK (0xC000U)
30274#define DDRPHY_DX6GCR3_DMOEMODE_SHIFT (14U)
30275/*! DMOEMODE - Enables the OE mode values for DM.
30276 */
30277#define DDRPHY_DX6GCR3_DMOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX6GCR3_DMOEMODE_MASK)
30278#define DDRPHY_DX6GCR3_DSNPDRMODE_MASK (0x30000U)
30279#define DDRPHY_DX6GCR3_DSNPDRMODE_SHIFT (16U)
30280/*! DSNPDRMODE - Enables the PDR mode for DQS
30281 */
30282#define DDRPHY_DX6GCR3_DSNPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX6GCR3_DSNPDRMODE_MASK)
30283#define DDRPHY_DX6GCR3_DSNTEMODE_MASK (0xC0000U)
30284#define DDRPHY_DX6GCR3_DSNTEMODE_SHIFT (18U)
30285/*! DSNTEMODE - Enables the TE mode for DQS
30286 */
30287#define DDRPHY_DX6GCR3_DSNTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX6GCR3_DSNTEMODE_MASK)
30288#define DDRPHY_DX6GCR3_DSNOEMODE_MASK (0x300000U)
30289#define DDRPHY_DX6GCR3_DSNOEMODE_SHIFT (20U)
30290/*! DSNOEMODE - Enables the OE mode for DQs
30291 */
30292#define DDRPHY_DX6GCR3_DSNOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX6GCR3_DSNOEMODE_MASK)
30293#define DDRPHY_DX6GCR3_PDRBVT_MASK (0x400000U)
30294#define DDRPHY_DX6GCR3_PDRBVT_SHIFT (22U)
30295/*! PDRBVT - Power Down Receiver BDL VT Compensation
30296 */
30297#define DDRPHY_DX6GCR3_PDRBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_PDRBVT_SHIFT)) & DDRPHY_DX6GCR3_PDRBVT_MASK)
30298#define DDRPHY_DX6GCR3_RGSLVT_MASK (0x800000U)
30299#define DDRPHY_DX6GCR3_RGSLVT_SHIFT (23U)
30300/*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation
30301 */
30302#define DDRPHY_DX6GCR3_RGSLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_RGSLVT_SHIFT)) & DDRPHY_DX6GCR3_RGSLVT_MASK)
30303#define DDRPHY_DX6GCR3_WLLVT_MASK (0x1000000U)
30304#define DDRPHY_DX6GCR3_WLLVT_SHIFT (24U)
30305/*! WLLVT - Write Leveling LCDL Delay VT Compensation
30306 */
30307#define DDRPHY_DX6GCR3_WLLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_WLLVT_SHIFT)) & DDRPHY_DX6GCR3_WLLVT_MASK)
30308#define DDRPHY_DX6GCR3_WDLVT_MASK (0x2000000U)
30309#define DDRPHY_DX6GCR3_WDLVT_SHIFT (25U)
30310/*! WDLVT - Write DQ LCDL Delay VT Compensation
30311 */
30312#define DDRPHY_DX6GCR3_WDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_WDLVT_SHIFT)) & DDRPHY_DX6GCR3_WDLVT_MASK)
30313#define DDRPHY_DX6GCR3_RDLVT_MASK (0x4000000U)
30314#define DDRPHY_DX6GCR3_RDLVT_SHIFT (26U)
30315/*! RDLVT - Read DQS LCDL Delay VT Compensation
30316 */
30317#define DDRPHY_DX6GCR3_RDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_RDLVT_SHIFT)) & DDRPHY_DX6GCR3_RDLVT_MASK)
30318#define DDRPHY_DX6GCR3_RGLVT_MASK (0x8000000U)
30319#define DDRPHY_DX6GCR3_RGLVT_SHIFT (27U)
30320/*! RGLVT - Read DQS Gating LCDL Delay VT Compensation
30321 */
30322#define DDRPHY_DX6GCR3_RGLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_RGLVT_SHIFT)) & DDRPHY_DX6GCR3_RGLVT_MASK)
30323#define DDRPHY_DX6GCR3_WDBVT_MASK (0x10000000U)
30324#define DDRPHY_DX6GCR3_WDBVT_SHIFT (28U)
30325/*! WDBVT - Write Data BDL VT Compensation
30326 */
30327#define DDRPHY_DX6GCR3_WDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_WDBVT_SHIFT)) & DDRPHY_DX6GCR3_WDBVT_MASK)
30328#define DDRPHY_DX6GCR3_RDBVT_MASK (0x20000000U)
30329#define DDRPHY_DX6GCR3_RDBVT_SHIFT (29U)
30330/*! RDBVT - Read Data BDL VT Compensation
30331 */
30332#define DDRPHY_DX6GCR3_RDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_RDBVT_SHIFT)) & DDRPHY_DX6GCR3_RDBVT_MASK)
30333#define DDRPHY_DX6GCR3_TEBVT_MASK (0x40000000U)
30334#define DDRPHY_DX6GCR3_TEBVT_SHIFT (30U)
30335/*! TEBVT - Termination Enable BDL VT Compensation
30336 */
30337#define DDRPHY_DX6GCR3_TEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_TEBVT_SHIFT)) & DDRPHY_DX6GCR3_TEBVT_MASK)
30338#define DDRPHY_DX6GCR3_OEBVT_MASK (0x80000000U)
30339#define DDRPHY_DX6GCR3_OEBVT_SHIFT (31U)
30340/*! OEBVT - Output Enable BDL VT Compensation
30341 */
30342#define DDRPHY_DX6GCR3_OEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR3_OEBVT_SHIFT)) & DDRPHY_DX6GCR3_OEBVT_MASK)
30343/*! @} */
30344
30345/*! @name DX6GCR4 - DATX8 n General Configuration Register 4 */
30346/*! @{ */
30347#define DDRPHY_DX6GCR4_DXREFIMON_MASK (0x3U)
30348#define DDRPHY_DX6GCR4_DXREFIMON_SHIFT (0U)
30349/*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane.
30350 */
30351#define DDRPHY_DX6GCR4_DXREFIMON(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX6GCR4_DXREFIMON_MASK)
30352#define DDRPHY_DX6GCR4_DXREFIEN_MASK (0x3CU)
30353#define DDRPHY_DX6GCR4_DXREFIEN_SHIFT (2U)
30354/*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
30355 */
30356#define DDRPHY_DX6GCR4_DXREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX6GCR4_DXREFIEN_MASK)
30357#define DDRPHY_DX6GCR4_RESERVED_7_6_MASK (0xC0U)
30358#define DDRPHY_DX6GCR4_RESERVED_7_6_SHIFT (6U)
30359/*! RESERVED_7_6 - Reserved. Returns zeros on reads.
30360 */
30361#define DDRPHY_DX6GCR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX6GCR4_RESERVED_7_6_MASK)
30362#define DDRPHY_DX6GCR4_DXREFSSEL_MASK (0x7F00U)
30363#define DDRPHY_DX6GCR4_DXREFSSEL_SHIFT (8U)
30364/*! DXREFSSEL - Byte Lane Single-End VREF Select
30365 */
30366#define DDRPHY_DX6GCR4_DXREFSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX6GCR4_DXREFSSEL_MASK)
30367#define DDRPHY_DX6GCR4_DXREFSSELRANGE_MASK (0x8000U)
30368#define DDRPHY_DX6GCR4_DXREFSSELRANGE_SHIFT (15U)
30369/*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select
30370 */
30371#define DDRPHY_DX6GCR4_DXREFSSELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX6GCR4_DXREFSSELRANGE_MASK)
30372#define DDRPHY_DX6GCR4_DXREFESEL_MASK (0x7F0000U)
30373#define DDRPHY_DX6GCR4_DXREFESEL_SHIFT (16U)
30374/*! DXREFESEL - Byte Lane External VREF Select
30375 */
30376#define DDRPHY_DX6GCR4_DXREFESEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX6GCR4_DXREFESEL_MASK)
30377#define DDRPHY_DX6GCR4_DXREFESELRANGE_MASK (0x800000U)
30378#define DDRPHY_DX6GCR4_DXREFESELRANGE_SHIFT (23U)
30379/*! DXREFESELRANGE - External VREF generator REFSEL range select
30380 */
30381#define DDRPHY_DX6GCR4_DXREFESELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX6GCR4_DXREFESELRANGE_MASK)
30382#define DDRPHY_DX6GCR4_RESERVED_24_MASK (0x1000000U)
30383#define DDRPHY_DX6GCR4_RESERVED_24_SHIFT (24U)
30384/*! RESERVED_24 - Reserved. Returns zeros on reads.
30385 */
30386#define DDRPHY_DX6GCR4_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX6GCR4_RESERVED_24_MASK)
30387#define DDRPHY_DX6GCR4_DXREFSEN_MASK (0x2000000U)
30388#define DDRPHY_DX6GCR4_DXREFSEN_SHIFT (25U)
30389/*! DXREFSEN - Byte Lane Single-End VREF Enable
30390 */
30391#define DDRPHY_DX6GCR4_DXREFSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX6GCR4_DXREFSEN_MASK)
30392#define DDRPHY_DX6GCR4_DXREFEEN_MASK (0xC000000U)
30393#define DDRPHY_DX6GCR4_DXREFEEN_SHIFT (26U)
30394/*! DXREFEEN - Byte Lane Internal VREF Enable
30395 */
30396#define DDRPHY_DX6GCR4_DXREFEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX6GCR4_DXREFEEN_MASK)
30397#define DDRPHY_DX6GCR4_DXREFPEN_MASK (0x10000000U)
30398#define DDRPHY_DX6GCR4_DXREFPEN_SHIFT (28U)
30399/*! DXREFPEN - Byte Lane VREF Pad Enable
30400 */
30401#define DDRPHY_DX6GCR4_DXREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX6GCR4_DXREFPEN_MASK)
30402#define DDRPHY_DX6GCR4_RESERVED_31_29_MASK (0xE0000000U)
30403#define DDRPHY_DX6GCR4_RESERVED_31_29_SHIFT (29U)
30404/*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs)
30405 */
30406#define DDRPHY_DX6GCR4_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX6GCR4_RESERVED_31_29_MASK)
30407/*! @} */
30408
30409/*! @name DX6GCR5 - DATX8 n General Configuration Register 5 */
30410/*! @{ */
30411#define DDRPHY_DX6GCR5_DXREFISELR0_MASK (0x7FU)
30412#define DDRPHY_DX6GCR5_DXREFISELR0_SHIFT (0U)
30413/*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0
30414 */
30415#define DDRPHY_DX6GCR5_DXREFISELR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX6GCR5_DXREFISELR0_MASK)
30416#define DDRPHY_DX6GCR5_RESERVED_7_MASK (0x80U)
30417#define DDRPHY_DX6GCR5_RESERVED_7_SHIFT (7U)
30418/*! RESERVED_7 - Reserved. Returns zeros on reads.
30419 */
30420#define DDRPHY_DX6GCR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX6GCR5_RESERVED_7_MASK)
30421#define DDRPHY_DX6GCR5_DXREFISELR1_MASK (0x7F00U)
30422#define DDRPHY_DX6GCR5_DXREFISELR1_SHIFT (8U)
30423/*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1
30424 */
30425#define DDRPHY_DX6GCR5_DXREFISELR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX6GCR5_DXREFISELR1_MASK)
30426#define DDRPHY_DX6GCR5_RESERVED_15_MASK (0x8000U)
30427#define DDRPHY_DX6GCR5_RESERVED_15_SHIFT (15U)
30428/*! RESERVED_15 - Reserved. Returns zeros on reads.
30429 */
30430#define DDRPHY_DX6GCR5_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX6GCR5_RESERVED_15_MASK)
30431#define DDRPHY_DX6GCR5_DXREFISELR2_MASK (0x7F0000U)
30432#define DDRPHY_DX6GCR5_DXREFISELR2_SHIFT (16U)
30433/*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2
30434 */
30435#define DDRPHY_DX6GCR5_DXREFISELR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX6GCR5_DXREFISELR2_MASK)
30436#define DDRPHY_DX6GCR5_RESERVED_23_MASK (0x800000U)
30437#define DDRPHY_DX6GCR5_RESERVED_23_SHIFT (23U)
30438/*! RESERVED_23 - Reserved. Returns zeros on reads.
30439 */
30440#define DDRPHY_DX6GCR5_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX6GCR5_RESERVED_23_MASK)
30441#define DDRPHY_DX6GCR5_DXREFISELR3_MASK (0x7F000000U)
30442#define DDRPHY_DX6GCR5_DXREFISELR3_SHIFT (24U)
30443/*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3
30444 */
30445#define DDRPHY_DX6GCR5_DXREFISELR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX6GCR5_DXREFISELR3_MASK)
30446#define DDRPHY_DX6GCR5_RESERVED_31_MASK (0x80000000U)
30447#define DDRPHY_DX6GCR5_RESERVED_31_SHIFT (31U)
30448/*! RESERVED_31 - Reserved. Returns zeros on reads.
30449 */
30450#define DDRPHY_DX6GCR5_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX6GCR5_RESERVED_31_MASK)
30451/*! @} */
30452
30453/*! @name DX6GCR6 - DATX8 n General Configuration Register 6 */
30454/*! @{ */
30455#define DDRPHY_DX6GCR6_DXDQVREFR0_MASK (0x3FU)
30456#define DDRPHY_DX6GCR6_DXDQVREFR0_SHIFT (0U)
30457/*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0
30458 */
30459#define DDRPHY_DX6GCR6_DXDQVREFR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX6GCR6_DXDQVREFR0_MASK)
30460#define DDRPHY_DX6GCR6_RESERVED_7_6_MASK (0xC0U)
30461#define DDRPHY_DX6GCR6_RESERVED_7_6_SHIFT (6U)
30462/*! RESERVED_7_6 - Reserved. Returns zeros on reads.
30463 */
30464#define DDRPHY_DX6GCR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX6GCR6_RESERVED_7_6_MASK)
30465#define DDRPHY_DX6GCR6_DXDQVREFR1_MASK (0x3F00U)
30466#define DDRPHY_DX6GCR6_DXDQVREFR1_SHIFT (8U)
30467/*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1
30468 */
30469#define DDRPHY_DX6GCR6_DXDQVREFR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX6GCR6_DXDQVREFR1_MASK)
30470#define DDRPHY_DX6GCR6_RESERVED_15_14_MASK (0xC000U)
30471#define DDRPHY_DX6GCR6_RESERVED_15_14_SHIFT (14U)
30472/*! RESERVED_15_14 - Reserved. Returns zeros on reads.
30473 */
30474#define DDRPHY_DX6GCR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX6GCR6_RESERVED_15_14_MASK)
30475#define DDRPHY_DX6GCR6_DXDQVREFR2_MASK (0x3F0000U)
30476#define DDRPHY_DX6GCR6_DXDQVREFR2_SHIFT (16U)
30477/*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2
30478 */
30479#define DDRPHY_DX6GCR6_DXDQVREFR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX6GCR6_DXDQVREFR2_MASK)
30480#define DDRPHY_DX6GCR6_RESERVED_23_22_MASK (0xC00000U)
30481#define DDRPHY_DX6GCR6_RESERVED_23_22_SHIFT (22U)
30482/*! RESERVED_23_22 - Reserved. Returns zeros on reads.
30483 */
30484#define DDRPHY_DX6GCR6_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX6GCR6_RESERVED_23_22_MASK)
30485#define DDRPHY_DX6GCR6_DXDQVREFR3_MASK (0x3F000000U)
30486#define DDRPHY_DX6GCR6_DXDQVREFR3_SHIFT (24U)
30487/*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3
30488 */
30489#define DDRPHY_DX6GCR6_DXDQVREFR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX6GCR6_DXDQVREFR3_MASK)
30490#define DDRPHY_DX6GCR6_RESERVED_31_30_MASK (0xC0000000U)
30491#define DDRPHY_DX6GCR6_RESERVED_31_30_SHIFT (30U)
30492/*! RESERVED_31_30 - Reserved. Returns zeros on reads.
30493 */
30494#define DDRPHY_DX6GCR6_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX6GCR6_RESERVED_31_30_MASK)
30495/*! @} */
30496
30497/*! @name DX6GCR7 - DATX8 n General Configuration Register 7 */
30498/*! @{ */
30499#define DDRPHY_DX6GCR7_DCALSVAL_MASK (0x1FFU)
30500#define DDRPHY_DX6GCR7_DCALSVAL_SHIFT (0U)
30501/*! DCALSVAL - DDL Calibration Starting Value
30502 */
30503#define DDRPHY_DX6GCR7_DCALSVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX6GCR7_DCALSVAL_MASK)
30504#define DDRPHY_DX6GCR7_DCALTYPE_MASK (0x200U)
30505#define DDRPHY_DX6GCR7_DCALTYPE_SHIFT (9U)
30506/*! DCALTYPE - DDL Calibration Type
30507 */
30508#define DDRPHY_DX6GCR7_DCALTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX6GCR7_DCALTYPE_MASK)
30509#define DDRPHY_DX6GCR7_RESERVED_17_10_MASK (0x3FC00U)
30510#define DDRPHY_DX6GCR7_RESERVED_17_10_SHIFT (10U)
30511/*! RESERVED_17_10 - Reserved. Caution, do not write to this register field.
30512 */
30513#define DDRPHY_DX6GCR7_RESERVED_17_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX6GCR7_RESERVED_17_10_MASK)
30514#define DDRPHY_DX6GCR7_RESERVED_18_MASK (0x40000U)
30515#define DDRPHY_DX6GCR7_RESERVED_18_SHIFT (18U)
30516/*! RESERVED_18 - Reserved. Caution, do not write to this register field.
30517 */
30518#define DDRPHY_DX6GCR7_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX6GCR7_RESERVED_18_MASK)
30519#define DDRPHY_DX6GCR7_RESERVED_31_19_MASK (0xFFF80000U)
30520#define DDRPHY_DX6GCR7_RESERVED_31_19_SHIFT (19U)
30521/*! RESERVED_31_19 - Reserved. Caution, do not write to this register field.
30522 */
30523#define DDRPHY_DX6GCR7_RESERVED_31_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX6GCR7_RESERVED_31_19_MASK)
30524/*! @} */
30525
30526/*! @name DX6GCR8 - DATX8 n General Configuration Register 8 */
30527/*! @{ */
30528#define DDRPHY_DX6GCR8_RESERVED_5_0_MASK (0x3FU)
30529#define DDRPHY_DX6GCR8_RESERVED_5_0_SHIFT (0U)
30530/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
30531 */
30532#define DDRPHY_DX6GCR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_5_0_MASK)
30533#define DDRPHY_DX6GCR8_RESERVED_7_6_MASK (0xC0U)
30534#define DDRPHY_DX6GCR8_RESERVED_7_6_SHIFT (6U)
30535/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
30536 */
30537#define DDRPHY_DX6GCR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_7_6_MASK)
30538#define DDRPHY_DX6GCR8_RESERVED_13_8_MASK (0x3F00U)
30539#define DDRPHY_DX6GCR8_RESERVED_13_8_SHIFT (8U)
30540/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
30541 */
30542#define DDRPHY_DX6GCR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_13_8_MASK)
30543#define DDRPHY_DX6GCR8_RESERVED_15_14_MASK (0xC000U)
30544#define DDRPHY_DX6GCR8_RESERVED_15_14_SHIFT (14U)
30545/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
30546 */
30547#define DDRPHY_DX6GCR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_15_14_MASK)
30548#define DDRPHY_DX6GCR8_RESERVED_21_16_MASK (0x3F0000U)
30549#define DDRPHY_DX6GCR8_RESERVED_21_16_SHIFT (16U)
30550/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
30551 */
30552#define DDRPHY_DX6GCR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_21_16_MASK)
30553#define DDRPHY_DX6GCR8_RESERVED_23_22_MASK (0xC00000U)
30554#define DDRPHY_DX6GCR8_RESERVED_23_22_SHIFT (22U)
30555/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
30556 */
30557#define DDRPHY_DX6GCR8_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_23_22_MASK)
30558#define DDRPHY_DX6GCR8_RESERVED_29_24_MASK (0x3F000000U)
30559#define DDRPHY_DX6GCR8_RESERVED_29_24_SHIFT (24U)
30560/*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
30561 */
30562#define DDRPHY_DX6GCR8_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_29_24_MASK)
30563#define DDRPHY_DX6GCR8_RESERVED_31_30_MASK (0xC0000000U)
30564#define DDRPHY_DX6GCR8_RESERVED_31_30_SHIFT (30U)
30565/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
30566 */
30567#define DDRPHY_DX6GCR8_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX6GCR8_RESERVED_31_30_MASK)
30568/*! @} */
30569
30570/*! @name DX6GCR9 - DATX8 n General Configuration Register 9 */
30571/*! @{ */
30572#define DDRPHY_DX6GCR9_RESERVED_5_0_MASK (0x3FU)
30573#define DDRPHY_DX6GCR9_RESERVED_5_0_SHIFT (0U)
30574/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
30575 */
30576#define DDRPHY_DX6GCR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_5_0_MASK)
30577#define DDRPHY_DX6GCR9_RESERVED_7_6_MASK (0xC0U)
30578#define DDRPHY_DX6GCR9_RESERVED_7_6_SHIFT (6U)
30579/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
30580 */
30581#define DDRPHY_DX6GCR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_7_6_MASK)
30582#define DDRPHY_DX6GCR9_RESERVED_13_8_MASK (0x3F00U)
30583#define DDRPHY_DX6GCR9_RESERVED_13_8_SHIFT (8U)
30584/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
30585 */
30586#define DDRPHY_DX6GCR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_13_8_MASK)
30587#define DDRPHY_DX6GCR9_RESERVED_15_14_MASK (0xC000U)
30588#define DDRPHY_DX6GCR9_RESERVED_15_14_SHIFT (14U)
30589/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
30590 */
30591#define DDRPHY_DX6GCR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_15_14_MASK)
30592#define DDRPHY_DX6GCR9_RESERVED_21_16_MASK (0x3F0000U)
30593#define DDRPHY_DX6GCR9_RESERVED_21_16_SHIFT (16U)
30594/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
30595 */
30596#define DDRPHY_DX6GCR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_21_16_MASK)
30597#define DDRPHY_DX6GCR9_RESERVED_23_22_MASK (0xC00000U)
30598#define DDRPHY_DX6GCR9_RESERVED_23_22_SHIFT (22U)
30599/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
30600 */
30601#define DDRPHY_DX6GCR9_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_23_22_MASK)
30602#define DDRPHY_DX6GCR9_RESERVED_29_24_MASK (0x3F000000U)
30603#define DDRPHY_DX6GCR9_RESERVED_29_24_SHIFT (24U)
30604/*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
30605 */
30606#define DDRPHY_DX6GCR9_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_29_24_MASK)
30607#define DDRPHY_DX6GCR9_RESERVED_31_30_MASK (0xC0000000U)
30608#define DDRPHY_DX6GCR9_RESERVED_31_30_SHIFT (30U)
30609/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
30610 */
30611#define DDRPHY_DX6GCR9_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX6GCR9_RESERVED_31_30_MASK)
30612/*! @} */
30613
30614/*! @name DX6DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */
30615/*! @{ */
30616#define DDRPHY_DX6DQMAP0_DQ0MAP_MASK (0xFU)
30617#define DDRPHY_DX6DQMAP0_DQ0MAP_SHIFT (0U)
30618/*! DQ0MAP - DQ bit 0 DATX8 slice mapping index
30619 */
30620#define DDRPHY_DX6DQMAP0_DQ0MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX6DQMAP0_DQ0MAP_MASK)
30621#define DDRPHY_DX6DQMAP0_DQ1MAP_MASK (0xF0U)
30622#define DDRPHY_DX6DQMAP0_DQ1MAP_SHIFT (4U)
30623/*! DQ1MAP - DQ bit 1 DATX8 slice mapping index
30624 */
30625#define DDRPHY_DX6DQMAP0_DQ1MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX6DQMAP0_DQ1MAP_MASK)
30626#define DDRPHY_DX6DQMAP0_DQ2MAP_MASK (0xF00U)
30627#define DDRPHY_DX6DQMAP0_DQ2MAP_SHIFT (8U)
30628/*! DQ2MAP - DQ bit 2 DATX8 slice mapping index
30629 */
30630#define DDRPHY_DX6DQMAP0_DQ2MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX6DQMAP0_DQ2MAP_MASK)
30631#define DDRPHY_DX6DQMAP0_DQ3MAP_MASK (0xF000U)
30632#define DDRPHY_DX6DQMAP0_DQ3MAP_SHIFT (12U)
30633/*! DQ3MAP - DQ bit 3 DATX8 slice mapping index
30634 */
30635#define DDRPHY_DX6DQMAP0_DQ3MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX6DQMAP0_DQ3MAP_MASK)
30636#define DDRPHY_DX6DQMAP0_DQ4MAP_MASK (0xF0000U)
30637#define DDRPHY_DX6DQMAP0_DQ4MAP_SHIFT (16U)
30638/*! DQ4MAP - DQ bit 4 DATX8 slice mapping index
30639 */
30640#define DDRPHY_DX6DQMAP0_DQ4MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX6DQMAP0_DQ4MAP_MASK)
30641#define DDRPHY_DX6DQMAP0_RESERVED_30_20_MASK (0x7FF00000U)
30642#define DDRPHY_DX6DQMAP0_RESERVED_30_20_SHIFT (20U)
30643/*! RESERVED_30_20 - Reserved. Return zeroes on reads.
30644 */
30645#define DDRPHY_DX6DQMAP0_RESERVED_30_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX6DQMAP0_RESERVED_30_20_MASK)
30646#define DDRPHY_DX6DQMAP0_MAPOK_MASK (0x80000000U)
30647#define DDRPHY_DX6DQMAP0_MAPOK_SHIFT (31U)
30648/*! MAPOK - Checksum bit
30649 */
30650#define DDRPHY_DX6DQMAP0_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX6DQMAP0_MAPOK_MASK)
30651/*! @} */
30652
30653/*! @name DX6DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */
30654/*! @{ */
30655#define DDRPHY_DX6DQMAP1_DQ5MAP_MASK (0xFU)
30656#define DDRPHY_DX6DQMAP1_DQ5MAP_SHIFT (0U)
30657/*! DQ5MAP - DQ bit 5 DATX8 slice mapping index
30658 */
30659#define DDRPHY_DX6DQMAP1_DQ5MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX6DQMAP1_DQ5MAP_MASK)
30660#define DDRPHY_DX6DQMAP1_DQ6MAP_MASK (0xF0U)
30661#define DDRPHY_DX6DQMAP1_DQ6MAP_SHIFT (4U)
30662/*! DQ6MAP - DQ bit 6 DATX8 slice mapping index
30663 */
30664#define DDRPHY_DX6DQMAP1_DQ6MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX6DQMAP1_DQ6MAP_MASK)
30665#define DDRPHY_DX6DQMAP1_DQ7MAP_MASK (0xF00U)
30666#define DDRPHY_DX6DQMAP1_DQ7MAP_SHIFT (8U)
30667/*! DQ7MAP - DQ bit 7 DATX8 slice mapping index
30668 */
30669#define DDRPHY_DX6DQMAP1_DQ7MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX6DQMAP1_DQ7MAP_MASK)
30670#define DDRPHY_DX6DQMAP1_DMMAP_MASK (0xF000U)
30671#define DDRPHY_DX6DQMAP1_DMMAP_SHIFT (12U)
30672/*! DMMAP - DM bit DATX8 slice mapping index
30673 */
30674#define DDRPHY_DX6DQMAP1_DMMAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX6DQMAP1_DMMAP_MASK)
30675#define DDRPHY_DX6DQMAP1_RESERVED_30_16_MASK (0x7FFF0000U)
30676#define DDRPHY_DX6DQMAP1_RESERVED_30_16_SHIFT (16U)
30677/*! RESERVED_30_16 - Reserved. Return zeroes on reads.
30678 */
30679#define DDRPHY_DX6DQMAP1_RESERVED_30_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX6DQMAP1_RESERVED_30_16_MASK)
30680#define DDRPHY_DX6DQMAP1_MAPOK_MASK (0x80000000U)
30681#define DDRPHY_DX6DQMAP1_MAPOK_SHIFT (31U)
30682/*! MAPOK - Checksum bit
30683 */
30684#define DDRPHY_DX6DQMAP1_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX6DQMAP1_MAPOK_MASK)
30685/*! @} */
30686
30687/*! @name DX6BDLR0 - DATX8 n Bit Delay Line Register 0 */
30688/*! @{ */
30689#define DDRPHY_DX6BDLR0_DQ0WBD_MASK (0x3FU)
30690#define DDRPHY_DX6BDLR0_DQ0WBD_SHIFT (0U)
30691/*! DQ0WBD - DQ0 Write Bit Delay
30692 */
30693#define DDRPHY_DX6BDLR0_DQ0WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX6BDLR0_DQ0WBD_MASK)
30694#define DDRPHY_DX6BDLR0_RESERVED_7_6_MASK (0xC0U)
30695#define DDRPHY_DX6BDLR0_RESERVED_7_6_SHIFT (6U)
30696/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
30697 */
30698#define DDRPHY_DX6BDLR0_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR0_RESERVED_7_6_MASK)
30699#define DDRPHY_DX6BDLR0_DQ1WBD_MASK (0x3F00U)
30700#define DDRPHY_DX6BDLR0_DQ1WBD_SHIFT (8U)
30701/*! DQ1WBD - DQ1 Write Bit Delay
30702 */
30703#define DDRPHY_DX6BDLR0_DQ1WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX6BDLR0_DQ1WBD_MASK)
30704#define DDRPHY_DX6BDLR0_RESERVED_15_14_MASK (0xC000U)
30705#define DDRPHY_DX6BDLR0_RESERVED_15_14_SHIFT (14U)
30706/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
30707 */
30708#define DDRPHY_DX6BDLR0_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR0_RESERVED_15_14_MASK)
30709#define DDRPHY_DX6BDLR0_DQ2WBD_MASK (0x3F0000U)
30710#define DDRPHY_DX6BDLR0_DQ2WBD_SHIFT (16U)
30711/*! DQ2WBD - DQ2 Write Bit Delay
30712 */
30713#define DDRPHY_DX6BDLR0_DQ2WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX6BDLR0_DQ2WBD_MASK)
30714#define DDRPHY_DX6BDLR0_RESERVED_23_22_MASK (0xC00000U)
30715#define DDRPHY_DX6BDLR0_RESERVED_23_22_SHIFT (22U)
30716/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
30717 */
30718#define DDRPHY_DX6BDLR0_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX6BDLR0_RESERVED_23_22_MASK)
30719#define DDRPHY_DX6BDLR0_DQ3WBD_MASK (0x3F000000U)
30720#define DDRPHY_DX6BDLR0_DQ3WBD_SHIFT (24U)
30721/*! DQ3WBD - DQ3 Write Bit Delay
30722 */
30723#define DDRPHY_DX6BDLR0_DQ3WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX6BDLR0_DQ3WBD_MASK)
30724#define DDRPHY_DX6BDLR0_RESERVED_31_30_MASK (0xC0000000U)
30725#define DDRPHY_DX6BDLR0_RESERVED_31_30_SHIFT (30U)
30726/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
30727 */
30728#define DDRPHY_DX6BDLR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX6BDLR0_RESERVED_31_30_MASK)
30729/*! @} */
30730
30731/*! @name DX6BDLR1 - DATX8 n Bit Delay Line Register 1 */
30732/*! @{ */
30733#define DDRPHY_DX6BDLR1_DQ4WBD_MASK (0x3FU)
30734#define DDRPHY_DX6BDLR1_DQ4WBD_SHIFT (0U)
30735/*! DQ4WBD - DQ4 Write Bit Delay
30736 */
30737#define DDRPHY_DX6BDLR1_DQ4WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX6BDLR1_DQ4WBD_MASK)
30738#define DDRPHY_DX6BDLR1_RESERVED_7_6_MASK (0xC0U)
30739#define DDRPHY_DX6BDLR1_RESERVED_7_6_SHIFT (6U)
30740/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
30741 */
30742#define DDRPHY_DX6BDLR1_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR1_RESERVED_7_6_MASK)
30743#define DDRPHY_DX6BDLR1_DQ5WBD_MASK (0x3F00U)
30744#define DDRPHY_DX6BDLR1_DQ5WBD_SHIFT (8U)
30745/*! DQ5WBD - DQ5 Write Bit Delay
30746 */
30747#define DDRPHY_DX6BDLR1_DQ5WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX6BDLR1_DQ5WBD_MASK)
30748#define DDRPHY_DX6BDLR1_RESERVED_15_14_MASK (0xC000U)
30749#define DDRPHY_DX6BDLR1_RESERVED_15_14_SHIFT (14U)
30750/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
30751 */
30752#define DDRPHY_DX6BDLR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR1_RESERVED_15_14_MASK)
30753#define DDRPHY_DX6BDLR1_DQ6WBD_MASK (0x3F0000U)
30754#define DDRPHY_DX6BDLR1_DQ6WBD_SHIFT (16U)
30755/*! DQ6WBD - DQ6 Write Bit Delay
30756 */
30757#define DDRPHY_DX6BDLR1_DQ6WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX6BDLR1_DQ6WBD_MASK)
30758#define DDRPHY_DX6BDLR1_RESERVED_23_22_MASK (0xC00000U)
30759#define DDRPHY_DX6BDLR1_RESERVED_23_22_SHIFT (22U)
30760/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
30761 */
30762#define DDRPHY_DX6BDLR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX6BDLR1_RESERVED_23_22_MASK)
30763#define DDRPHY_DX6BDLR1_DQ7WBD_MASK (0x3F000000U)
30764#define DDRPHY_DX6BDLR1_DQ7WBD_SHIFT (24U)
30765/*! DQ7WBD - DQ7 Write Bit Delay
30766 */
30767#define DDRPHY_DX6BDLR1_DQ7WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX6BDLR1_DQ7WBD_MASK)
30768#define DDRPHY_DX6BDLR1_RESERVED_31_30_MASK (0xC0000000U)
30769#define DDRPHY_DX6BDLR1_RESERVED_31_30_SHIFT (30U)
30770/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
30771 */
30772#define DDRPHY_DX6BDLR1_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX6BDLR1_RESERVED_31_30_MASK)
30773/*! @} */
30774
30775/*! @name DX6BDLR2 - DATX8 n Bit Delay Line Register 2 */
30776/*! @{ */
30777#define DDRPHY_DX6BDLR2_DMWBD_MASK (0x3FU)
30778#define DDRPHY_DX6BDLR2_DMWBD_SHIFT (0U)
30779/*! DMWBD - DM Write Bit Delay
30780 */
30781#define DDRPHY_DX6BDLR2_DMWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_DMWBD_SHIFT)) & DDRPHY_DX6BDLR2_DMWBD_MASK)
30782#define DDRPHY_DX6BDLR2_RESERVED_7_6_MASK (0xC0U)
30783#define DDRPHY_DX6BDLR2_RESERVED_7_6_SHIFT (6U)
30784/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
30785 */
30786#define DDRPHY_DX6BDLR2_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR2_RESERVED_7_6_MASK)
30787#define DDRPHY_DX6BDLR2_DSWBD_MASK (0x3F00U)
30788#define DDRPHY_DX6BDLR2_DSWBD_SHIFT (8U)
30789/*! DSWBD - DQS Write Bit Delay
30790 */
30791#define DDRPHY_DX6BDLR2_DSWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_DSWBD_SHIFT)) & DDRPHY_DX6BDLR2_DSWBD_MASK)
30792#define DDRPHY_DX6BDLR2_RESERVED_15_14_MASK (0xC000U)
30793#define DDRPHY_DX6BDLR2_RESERVED_15_14_SHIFT (14U)
30794/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
30795 */
30796#define DDRPHY_DX6BDLR2_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR2_RESERVED_15_14_MASK)
30797#define DDRPHY_DX6BDLR2_DSOEBD_MASK (0x3F0000U)
30798#define DDRPHY_DX6BDLR2_DSOEBD_SHIFT (16U)
30799/*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay
30800 */
30801#define DDRPHY_DX6BDLR2_DSOEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX6BDLR2_DSOEBD_MASK)
30802#define DDRPHY_DX6BDLR2_RESERVED_23_22_MASK (0xC00000U)
30803#define DDRPHY_DX6BDLR2_RESERVED_23_22_SHIFT (22U)
30804/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
30805 */
30806#define DDRPHY_DX6BDLR2_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX6BDLR2_RESERVED_23_22_MASK)
30807#define DDRPHY_DX6BDLR2_DSNWBD_MASK (0x3F000000U)
30808#define DDRPHY_DX6BDLR2_DSNWBD_SHIFT (24U)
30809/*! DSNWBD - DQSN Write Bit Delay
30810 */
30811#define DDRPHY_DX6BDLR2_DSNWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX6BDLR2_DSNWBD_MASK)
30812#define DDRPHY_DX6BDLR2_RESERVED_31_30_MASK (0xC0000000U)
30813#define DDRPHY_DX6BDLR2_RESERVED_31_30_SHIFT (30U)
30814/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
30815 */
30816#define DDRPHY_DX6BDLR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX6BDLR2_RESERVED_31_30_MASK)
30817/*! @} */
30818
30819/*! @name DX6BDLR3 - DATX8 n Bit Delay Line Register 3 */
30820/*! @{ */
30821#define DDRPHY_DX6BDLR3_DQ0RBD_MASK (0x3FU)
30822#define DDRPHY_DX6BDLR3_DQ0RBD_SHIFT (0U)
30823/*! DQ0RBD - DQ0 Read Bit Delay
30824 */
30825#define DDRPHY_DX6BDLR3_DQ0RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX6BDLR3_DQ0RBD_MASK)
30826#define DDRPHY_DX6BDLR3_RESERVED_7_6_MASK (0xC0U)
30827#define DDRPHY_DX6BDLR3_RESERVED_7_6_SHIFT (6U)
30828/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
30829 */
30830#define DDRPHY_DX6BDLR3_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR3_RESERVED_7_6_MASK)
30831#define DDRPHY_DX6BDLR3_DQ1RBD_MASK (0x3F00U)
30832#define DDRPHY_DX6BDLR3_DQ1RBD_SHIFT (8U)
30833/*! DQ1RBD - DQ1 Read Bit Delay
30834 */
30835#define DDRPHY_DX6BDLR3_DQ1RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX6BDLR3_DQ1RBD_MASK)
30836#define DDRPHY_DX6BDLR3_RESERVED_15_14_MASK (0xC000U)
30837#define DDRPHY_DX6BDLR3_RESERVED_15_14_SHIFT (14U)
30838/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
30839 */
30840#define DDRPHY_DX6BDLR3_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR3_RESERVED_15_14_MASK)
30841#define DDRPHY_DX6BDLR3_DQ2RBD_MASK (0x3F0000U)
30842#define DDRPHY_DX6BDLR3_DQ2RBD_SHIFT (16U)
30843/*! DQ2RBD - DQ2 Read Bit Delay
30844 */
30845#define DDRPHY_DX6BDLR3_DQ2RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX6BDLR3_DQ2RBD_MASK)
30846#define DDRPHY_DX6BDLR3_RESERVED_23_22_MASK (0xC00000U)
30847#define DDRPHY_DX6BDLR3_RESERVED_23_22_SHIFT (22U)
30848/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
30849 */
30850#define DDRPHY_DX6BDLR3_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX6BDLR3_RESERVED_23_22_MASK)
30851#define DDRPHY_DX6BDLR3_DQ3RBD_MASK (0x3F000000U)
30852#define DDRPHY_DX6BDLR3_DQ3RBD_SHIFT (24U)
30853/*! DQ3RBD - DQ3 Read Bit Delay
30854 */
30855#define DDRPHY_DX6BDLR3_DQ3RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX6BDLR3_DQ3RBD_MASK)
30856#define DDRPHY_DX6BDLR3_RESERVED_31_30_MASK (0xC0000000U)
30857#define DDRPHY_DX6BDLR3_RESERVED_31_30_SHIFT (30U)
30858/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
30859 */
30860#define DDRPHY_DX6BDLR3_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX6BDLR3_RESERVED_31_30_MASK)
30861/*! @} */
30862
30863/*! @name DX6BDLR4 - DATX8 n Bit Delay Line Register 4 */
30864/*! @{ */
30865#define DDRPHY_DX6BDLR4_DQ4RBD_MASK (0x3FU)
30866#define DDRPHY_DX6BDLR4_DQ4RBD_SHIFT (0U)
30867/*! DQ4RBD - DQ4 Read Bit Delay
30868 */
30869#define DDRPHY_DX6BDLR4_DQ4RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX6BDLR4_DQ4RBD_MASK)
30870#define DDRPHY_DX6BDLR4_RESERVED_7_6_MASK (0xC0U)
30871#define DDRPHY_DX6BDLR4_RESERVED_7_6_SHIFT (6U)
30872/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
30873 */
30874#define DDRPHY_DX6BDLR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR4_RESERVED_7_6_MASK)
30875#define DDRPHY_DX6BDLR4_DQ5RBD_MASK (0x3F00U)
30876#define DDRPHY_DX6BDLR4_DQ5RBD_SHIFT (8U)
30877/*! DQ5RBD - DQ5 Read Bit Delay
30878 */
30879#define DDRPHY_DX6BDLR4_DQ5RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX6BDLR4_DQ5RBD_MASK)
30880#define DDRPHY_DX6BDLR4_RESERVED_15_14_MASK (0xC000U)
30881#define DDRPHY_DX6BDLR4_RESERVED_15_14_SHIFT (14U)
30882/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
30883 */
30884#define DDRPHY_DX6BDLR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR4_RESERVED_15_14_MASK)
30885#define DDRPHY_DX6BDLR4_DQ6RBD_MASK (0x3F0000U)
30886#define DDRPHY_DX6BDLR4_DQ6RBD_SHIFT (16U)
30887/*! DQ6RBD - DQ6 Read Bit Delay
30888 */
30889#define DDRPHY_DX6BDLR4_DQ6RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX6BDLR4_DQ6RBD_MASK)
30890#define DDRPHY_DX6BDLR4_RESERVED_23_22_MASK (0xC00000U)
30891#define DDRPHY_DX6BDLR4_RESERVED_23_22_SHIFT (22U)
30892/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
30893 */
30894#define DDRPHY_DX6BDLR4_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX6BDLR4_RESERVED_23_22_MASK)
30895#define DDRPHY_DX6BDLR4_DQ7RBD_MASK (0x3F000000U)
30896#define DDRPHY_DX6BDLR4_DQ7RBD_SHIFT (24U)
30897/*! DQ7RBD - DQ7 Read Bit Delay
30898 */
30899#define DDRPHY_DX6BDLR4_DQ7RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX6BDLR4_DQ7RBD_MASK)
30900#define DDRPHY_DX6BDLR4_RESERVED_31_30_MASK (0xC0000000U)
30901#define DDRPHY_DX6BDLR4_RESERVED_31_30_SHIFT (30U)
30902/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
30903 */
30904#define DDRPHY_DX6BDLR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX6BDLR4_RESERVED_31_30_MASK)
30905/*! @} */
30906
30907/*! @name DX6BDLR5 - DATX8 n Bit Delay Line Register 5 */
30908/*! @{ */
30909#define DDRPHY_DX6BDLR5_DMRBD_MASK (0x3FU)
30910#define DDRPHY_DX6BDLR5_DMRBD_SHIFT (0U)
30911/*! DMRBD - DM Read Bit Delay
30912 */
30913#define DDRPHY_DX6BDLR5_DMRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR5_DMRBD_SHIFT)) & DDRPHY_DX6BDLR5_DMRBD_MASK)
30914#define DDRPHY_DX6BDLR5_RESERVED_31_6_MASK (0xFFFFFFC0U)
30915#define DDRPHY_DX6BDLR5_RESERVED_31_6_SHIFT (6U)
30916/*! RESERVED_31_6 - Reserved. Return zeroes on reads.
30917 */
30918#define DDRPHY_DX6BDLR5_RESERVED_31_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX6BDLR5_RESERVED_31_6_MASK)
30919/*! @} */
30920
30921/*! @name DX6BDLR6 - DATX8 n Bit Delay Line Register 6 */
30922/*! @{ */
30923#define DDRPHY_DX6BDLR6_RESERVED_7_0_MASK (0xFFU)
30924#define DDRPHY_DX6BDLR6_RESERVED_7_0_SHIFT (0U)
30925/*! RESERVED_7_0 - Reserved. Return zeroes on reads.
30926 */
30927#define DDRPHY_DX6BDLR6_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX6BDLR6_RESERVED_7_0_MASK)
30928#define DDRPHY_DX6BDLR6_PDRBD_MASK (0x3F00U)
30929#define DDRPHY_DX6BDLR6_PDRBD_SHIFT (8U)
30930/*! PDRBD - Power down receiver Bit Delay
30931 */
30932#define DDRPHY_DX6BDLR6_PDRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR6_PDRBD_SHIFT)) & DDRPHY_DX6BDLR6_PDRBD_MASK)
30933#define DDRPHY_DX6BDLR6_RESERVED_15_14_MASK (0xC000U)
30934#define DDRPHY_DX6BDLR6_RESERVED_15_14_SHIFT (14U)
30935/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
30936 */
30937#define DDRPHY_DX6BDLR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR6_RESERVED_15_14_MASK)
30938#define DDRPHY_DX6BDLR6_TERBD_MASK (0x3F0000U)
30939#define DDRPHY_DX6BDLR6_TERBD_SHIFT (16U)
30940/*! TERBD - Termination Enable Bit Delay
30941 */
30942#define DDRPHY_DX6BDLR6_TERBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR6_TERBD_SHIFT)) & DDRPHY_DX6BDLR6_TERBD_MASK)
30943#define DDRPHY_DX6BDLR6_RESERVED_31_22_MASK (0xFFC00000U)
30944#define DDRPHY_DX6BDLR6_RESERVED_31_22_SHIFT (22U)
30945/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
30946 */
30947#define DDRPHY_DX6BDLR6_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX6BDLR6_RESERVED_31_22_MASK)
30948/*! @} */
30949
30950/*! @name DX6BDLR7 - DATX8 n Bit Delay Line Register 7 */
30951/*! @{ */
30952#define DDRPHY_DX6BDLR7_RESERVED_5_0_MASK (0x3FU)
30953#define DDRPHY_DX6BDLR7_RESERVED_5_0_SHIFT (0U)
30954/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
30955 */
30956#define DDRPHY_DX6BDLR7_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX6BDLR7_RESERVED_5_0_MASK)
30957#define DDRPHY_DX6BDLR7_RESERVED_7_6_MASK (0xC0U)
30958#define DDRPHY_DX6BDLR7_RESERVED_7_6_SHIFT (6U)
30959/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
30960 */
30961#define DDRPHY_DX6BDLR7_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR7_RESERVED_7_6_MASK)
30962#define DDRPHY_DX6BDLR7_RESERVED_13_8_MASK (0x3F00U)
30963#define DDRPHY_DX6BDLR7_RESERVED_13_8_SHIFT (8U)
30964/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
30965 */
30966#define DDRPHY_DX6BDLR7_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX6BDLR7_RESERVED_13_8_MASK)
30967#define DDRPHY_DX6BDLR7_RESERVED_15_14_MASK (0xC000U)
30968#define DDRPHY_DX6BDLR7_RESERVED_15_14_SHIFT (14U)
30969/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
30970 */
30971#define DDRPHY_DX6BDLR7_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR7_RESERVED_15_14_MASK)
30972#define DDRPHY_DX6BDLR7_RESERVED_21_16_MASK (0x3F0000U)
30973#define DDRPHY_DX6BDLR7_RESERVED_21_16_SHIFT (16U)
30974/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
30975 */
30976#define DDRPHY_DX6BDLR7_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX6BDLR7_RESERVED_21_16_MASK)
30977#define DDRPHY_DX6BDLR7_RESERVED_31_22_MASK (0xFFC00000U)
30978#define DDRPHY_DX6BDLR7_RESERVED_31_22_SHIFT (22U)
30979/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
30980 */
30981#define DDRPHY_DX6BDLR7_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX6BDLR7_RESERVED_31_22_MASK)
30982/*! @} */
30983
30984/*! @name DX6BDLR8 - DATX8 n Bit Delay Line Register 8 */
30985/*! @{ */
30986#define DDRPHY_DX6BDLR8_RESERVED_5_0_MASK (0x3FU)
30987#define DDRPHY_DX6BDLR8_RESERVED_5_0_SHIFT (0U)
30988/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
30989 */
30990#define DDRPHY_DX6BDLR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX6BDLR8_RESERVED_5_0_MASK)
30991#define DDRPHY_DX6BDLR8_RESERVED_7_6_MASK (0xC0U)
30992#define DDRPHY_DX6BDLR8_RESERVED_7_6_SHIFT (6U)
30993/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
30994 */
30995#define DDRPHY_DX6BDLR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR8_RESERVED_7_6_MASK)
30996#define DDRPHY_DX6BDLR8_RESERVED_13_8_MASK (0x3F00U)
30997#define DDRPHY_DX6BDLR8_RESERVED_13_8_SHIFT (8U)
30998/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
30999 */
31000#define DDRPHY_DX6BDLR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX6BDLR8_RESERVED_13_8_MASK)
31001#define DDRPHY_DX6BDLR8_RESERVED_15_14_MASK (0xC000U)
31002#define DDRPHY_DX6BDLR8_RESERVED_15_14_SHIFT (14U)
31003/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
31004 */
31005#define DDRPHY_DX6BDLR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR8_RESERVED_15_14_MASK)
31006#define DDRPHY_DX6BDLR8_RESERVED_21_16_MASK (0x3F0000U)
31007#define DDRPHY_DX6BDLR8_RESERVED_21_16_SHIFT (16U)
31008/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
31009 */
31010#define DDRPHY_DX6BDLR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX6BDLR8_RESERVED_21_16_MASK)
31011#define DDRPHY_DX6BDLR8_RESERVED_31_22_MASK (0xFFC00000U)
31012#define DDRPHY_DX6BDLR8_RESERVED_31_22_SHIFT (22U)
31013/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
31014 */
31015#define DDRPHY_DX6BDLR8_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX6BDLR8_RESERVED_31_22_MASK)
31016/*! @} */
31017
31018/*! @name DX6BDLR9 - DATX8 n Bit Delay Line Register 9 */
31019/*! @{ */
31020#define DDRPHY_DX6BDLR9_RESERVED_5_0_MASK (0x3FU)
31021#define DDRPHY_DX6BDLR9_RESERVED_5_0_SHIFT (0U)
31022/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
31023 */
31024#define DDRPHY_DX6BDLR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX6BDLR9_RESERVED_5_0_MASK)
31025#define DDRPHY_DX6BDLR9_RESERVED_7_6_MASK (0xC0U)
31026#define DDRPHY_DX6BDLR9_RESERVED_7_6_SHIFT (6U)
31027/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
31028 */
31029#define DDRPHY_DX6BDLR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX6BDLR9_RESERVED_7_6_MASK)
31030#define DDRPHY_DX6BDLR9_RESERVED_13_8_MASK (0x3F00U)
31031#define DDRPHY_DX6BDLR9_RESERVED_13_8_SHIFT (8U)
31032/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
31033 */
31034#define DDRPHY_DX6BDLR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX6BDLR9_RESERVED_13_8_MASK)
31035#define DDRPHY_DX6BDLR9_RESERVED_15_14_MASK (0xC000U)
31036#define DDRPHY_DX6BDLR9_RESERVED_15_14_SHIFT (14U)
31037/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
31038 */
31039#define DDRPHY_DX6BDLR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX6BDLR9_RESERVED_15_14_MASK)
31040#define DDRPHY_DX6BDLR9_RESERVED_21_16_MASK (0x3F0000U)
31041#define DDRPHY_DX6BDLR9_RESERVED_21_16_SHIFT (16U)
31042/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
31043 */
31044#define DDRPHY_DX6BDLR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX6BDLR9_RESERVED_21_16_MASK)
31045#define DDRPHY_DX6BDLR9_RESERVED_31_22_MASK (0xFFC00000U)
31046#define DDRPHY_DX6BDLR9_RESERVED_31_22_SHIFT (22U)
31047/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
31048 */
31049#define DDRPHY_DX6BDLR9_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX6BDLR9_RESERVED_31_22_MASK)
31050/*! @} */
31051
31052/*! @name DX6LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */
31053/*! @{ */
31054#define DDRPHY_DX6LCDLR0_WLD_MASK (0x1FFU)
31055#define DDRPHY_DX6LCDLR0_WLD_SHIFT (0U)
31056/*! WLD - Write Leveling Delay
31057 */
31058#define DDRPHY_DX6LCDLR0_WLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR0_WLD_SHIFT)) & DDRPHY_DX6LCDLR0_WLD_MASK)
31059#define DDRPHY_DX6LCDLR0_RESERVED_15_9_MASK (0xFE00U)
31060#define DDRPHY_DX6LCDLR0_RESERVED_15_9_SHIFT (9U)
31061/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
31062 */
31063#define DDRPHY_DX6LCDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX6LCDLR0_RESERVED_15_9_MASK)
31064#define DDRPHY_DX6LCDLR0_RESERVED_24_16_MASK (0x1FF0000U)
31065#define DDRPHY_DX6LCDLR0_RESERVED_24_16_SHIFT (16U)
31066/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
31067 */
31068#define DDRPHY_DX6LCDLR0_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX6LCDLR0_RESERVED_24_16_MASK)
31069#define DDRPHY_DX6LCDLR0_RESERVED_31_25_MASK (0xFE000000U)
31070#define DDRPHY_DX6LCDLR0_RESERVED_31_25_SHIFT (25U)
31071/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
31072 */
31073#define DDRPHY_DX6LCDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX6LCDLR0_RESERVED_31_25_MASK)
31074/*! @} */
31075
31076/*! @name DX6LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */
31077/*! @{ */
31078#define DDRPHY_DX6LCDLR1_WDQD_MASK (0x1FFU)
31079#define DDRPHY_DX6LCDLR1_WDQD_SHIFT (0U)
31080/*! WDQD - Write Data Delay
31081 */
31082#define DDRPHY_DX6LCDLR1_WDQD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR1_WDQD_SHIFT)) & DDRPHY_DX6LCDLR1_WDQD_MASK)
31083#define DDRPHY_DX6LCDLR1_RESERVED_15_9_MASK (0xFE00U)
31084#define DDRPHY_DX6LCDLR1_RESERVED_15_9_SHIFT (9U)
31085/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
31086 */
31087#define DDRPHY_DX6LCDLR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX6LCDLR1_RESERVED_15_9_MASK)
31088#define DDRPHY_DX6LCDLR1_RESERVED_24_16_MASK (0x1FF0000U)
31089#define DDRPHY_DX6LCDLR1_RESERVED_24_16_SHIFT (16U)
31090/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
31091 */
31092#define DDRPHY_DX6LCDLR1_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX6LCDLR1_RESERVED_24_16_MASK)
31093#define DDRPHY_DX6LCDLR1_RESERVED_31_25_MASK (0xFE000000U)
31094#define DDRPHY_DX6LCDLR1_RESERVED_31_25_SHIFT (25U)
31095/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
31096 */
31097#define DDRPHY_DX6LCDLR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX6LCDLR1_RESERVED_31_25_MASK)
31098/*! @} */
31099
31100/*! @name DX6LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */
31101/*! @{ */
31102#define DDRPHY_DX6LCDLR2_DQSGD_MASK (0x1FFU)
31103#define DDRPHY_DX6LCDLR2_DQSGD_SHIFT (0U)
31104/*! DQSGD - Read DQS Gating Delay
31105 */
31106#define DDRPHY_DX6LCDLR2_DQSGD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX6LCDLR2_DQSGD_MASK)
31107#define DDRPHY_DX6LCDLR2_RESERVED_15_9_MASK (0xFE00U)
31108#define DDRPHY_DX6LCDLR2_RESERVED_15_9_SHIFT (9U)
31109/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
31110 */
31111#define DDRPHY_DX6LCDLR2_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX6LCDLR2_RESERVED_15_9_MASK)
31112#define DDRPHY_DX6LCDLR2_RESERVED_24_16_MASK (0x1FF0000U)
31113#define DDRPHY_DX6LCDLR2_RESERVED_24_16_SHIFT (16U)
31114/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
31115 */
31116#define DDRPHY_DX6LCDLR2_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX6LCDLR2_RESERVED_24_16_MASK)
31117#define DDRPHY_DX6LCDLR2_RESERVED_31_25_MASK (0xFE000000U)
31118#define DDRPHY_DX6LCDLR2_RESERVED_31_25_SHIFT (25U)
31119/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
31120 */
31121#define DDRPHY_DX6LCDLR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX6LCDLR2_RESERVED_31_25_MASK)
31122/*! @} */
31123
31124/*! @name DX6LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */
31125/*! @{ */
31126#define DDRPHY_DX6LCDLR3_RDQSD_MASK (0x1FFU)
31127#define DDRPHY_DX6LCDLR3_RDQSD_SHIFT (0U)
31128/*! RDQSD - Read DQS Delay
31129 */
31130#define DDRPHY_DX6LCDLR3_RDQSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX6LCDLR3_RDQSD_MASK)
31131#define DDRPHY_DX6LCDLR3_RESERVED_15_9_MASK (0xFE00U)
31132#define DDRPHY_DX6LCDLR3_RESERVED_15_9_SHIFT (9U)
31133/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
31134 */
31135#define DDRPHY_DX6LCDLR3_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX6LCDLR3_RESERVED_15_9_MASK)
31136#define DDRPHY_DX6LCDLR3_RESERVED_24_16_MASK (0x1FF0000U)
31137#define DDRPHY_DX6LCDLR3_RESERVED_24_16_SHIFT (16U)
31138/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
31139 */
31140#define DDRPHY_DX6LCDLR3_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX6LCDLR3_RESERVED_24_16_MASK)
31141#define DDRPHY_DX6LCDLR3_RESERVED_31_25_MASK (0xFE000000U)
31142#define DDRPHY_DX6LCDLR3_RESERVED_31_25_SHIFT (25U)
31143/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
31144 */
31145#define DDRPHY_DX6LCDLR3_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX6LCDLR3_RESERVED_31_25_MASK)
31146/*! @} */
31147
31148/*! @name DX6LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */
31149/*! @{ */
31150#define DDRPHY_DX6LCDLR4_RDQSND_MASK (0x1FFU)
31151#define DDRPHY_DX6LCDLR4_RDQSND_SHIFT (0U)
31152/*! RDQSND - Read DQSN Delay
31153 */
31154#define DDRPHY_DX6LCDLR4_RDQSND(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX6LCDLR4_RDQSND_MASK)
31155#define DDRPHY_DX6LCDLR4_RESERVED_15_9_MASK (0xFE00U)
31156#define DDRPHY_DX6LCDLR4_RESERVED_15_9_SHIFT (9U)
31157/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
31158 */
31159#define DDRPHY_DX6LCDLR4_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX6LCDLR4_RESERVED_15_9_MASK)
31160#define DDRPHY_DX6LCDLR4_RESERVED_24_16_MASK (0x1FF0000U)
31161#define DDRPHY_DX6LCDLR4_RESERVED_24_16_SHIFT (16U)
31162/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
31163 */
31164#define DDRPHY_DX6LCDLR4_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX6LCDLR4_RESERVED_24_16_MASK)
31165#define DDRPHY_DX6LCDLR4_RESERVED_31_25_MASK (0xFE000000U)
31166#define DDRPHY_DX6LCDLR4_RESERVED_31_25_SHIFT (25U)
31167/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
31168 */
31169#define DDRPHY_DX6LCDLR4_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX6LCDLR4_RESERVED_31_25_MASK)
31170/*! @} */
31171
31172/*! @name DX6LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */
31173/*! @{ */
31174#define DDRPHY_DX6LCDLR5_DQSGSD_MASK (0x1FFU)
31175#define DDRPHY_DX6LCDLR5_DQSGSD_SHIFT (0U)
31176/*! DQSGSD - DQS Gating Status Delay
31177 */
31178#define DDRPHY_DX6LCDLR5_DQSGSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX6LCDLR5_DQSGSD_MASK)
31179#define DDRPHY_DX6LCDLR5_RESERVED_15_9_MASK (0xFE00U)
31180#define DDRPHY_DX6LCDLR5_RESERVED_15_9_SHIFT (9U)
31181/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
31182 */
31183#define DDRPHY_DX6LCDLR5_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX6LCDLR5_RESERVED_15_9_MASK)
31184#define DDRPHY_DX6LCDLR5_RESERVED_24_16_MASK (0x1FF0000U)
31185#define DDRPHY_DX6LCDLR5_RESERVED_24_16_SHIFT (16U)
31186/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
31187 */
31188#define DDRPHY_DX6LCDLR5_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX6LCDLR5_RESERVED_24_16_MASK)
31189#define DDRPHY_DX6LCDLR5_RESERVED_31_25_MASK (0xFE000000U)
31190#define DDRPHY_DX6LCDLR5_RESERVED_31_25_SHIFT (25U)
31191/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
31192 */
31193#define DDRPHY_DX6LCDLR5_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX6LCDLR5_RESERVED_31_25_MASK)
31194/*! @} */
31195
31196/*! @name DX6MDLR0 - DATX8 n Master Delay Line Register 0 */
31197/*! @{ */
31198#define DDRPHY_DX6MDLR0_IPRD_MASK (0x1FFU)
31199#define DDRPHY_DX6MDLR0_IPRD_SHIFT (0U)
31200/*! IPRD - Initial Period
31201 */
31202#define DDRPHY_DX6MDLR0_IPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6MDLR0_IPRD_SHIFT)) & DDRPHY_DX6MDLR0_IPRD_MASK)
31203#define DDRPHY_DX6MDLR0_RESERVED_15_9_MASK (0xFE00U)
31204#define DDRPHY_DX6MDLR0_RESERVED_15_9_SHIFT (9U)
31205/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
31206 */
31207#define DDRPHY_DX6MDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX6MDLR0_RESERVED_15_9_MASK)
31208#define DDRPHY_DX6MDLR0_TPRD_MASK (0x1FF0000U)
31209#define DDRPHY_DX6MDLR0_TPRD_SHIFT (16U)
31210/*! TPRD - Target Period
31211 */
31212#define DDRPHY_DX6MDLR0_TPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6MDLR0_TPRD_SHIFT)) & DDRPHY_DX6MDLR0_TPRD_MASK)
31213#define DDRPHY_DX6MDLR0_RESERVED_31_25_MASK (0xFE000000U)
31214#define DDRPHY_DX6MDLR0_RESERVED_31_25_SHIFT (25U)
31215/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
31216 */
31217#define DDRPHY_DX6MDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX6MDLR0_RESERVED_31_25_MASK)
31218/*! @} */
31219
31220/*! @name DX6MDLR1 - DATX8 n Master Delay Line Register 1 */
31221/*! @{ */
31222#define DDRPHY_DX6MDLR1_MDLD_MASK (0x1FFU)
31223#define DDRPHY_DX6MDLR1_MDLD_SHIFT (0U)
31224/*! MDLD - MDL Delay
31225 */
31226#define DDRPHY_DX6MDLR1_MDLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6MDLR1_MDLD_SHIFT)) & DDRPHY_DX6MDLR1_MDLD_MASK)
31227#define DDRPHY_DX6MDLR1_RESERVED_31_9_MASK (0xFFFFFE00U)
31228#define DDRPHY_DX6MDLR1_RESERVED_31_9_SHIFT (9U)
31229/*! RESERVED_31_9 - Reserved. Return zeroes on reads.
31230 */
31231#define DDRPHY_DX6MDLR1_RESERVED_31_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX6MDLR1_RESERVED_31_9_MASK)
31232/*! @} */
31233
31234/*! @name DX6GTR0 - DATX8 n General Timing Register 0 */
31235/*! @{ */
31236#define DDRPHY_DX6GTR0_DGSL_MASK (0x1FU)
31237#define DDRPHY_DX6GTR0_DGSL_SHIFT (0U)
31238/*! DGSL - DQS Gating System Latency
31239 */
31240#define DDRPHY_DX6GTR0_DGSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_DGSL_SHIFT)) & DDRPHY_DX6GTR0_DGSL_MASK)
31241#define DDRPHY_DX6GTR0_RESERVED_7_5_MASK (0xE0U)
31242#define DDRPHY_DX6GTR0_RESERVED_7_5_SHIFT (5U)
31243/*! RESERVED_7_5 - Reserved. Return zeroes on reads.
31244 */
31245#define DDRPHY_DX6GTR0_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX6GTR0_RESERVED_7_5_MASK)
31246#define DDRPHY_DX6GTR0_RESERVED_12_8_MASK (0x1F00U)
31247#define DDRPHY_DX6GTR0_RESERVED_12_8_SHIFT (8U)
31248/*! RESERVED_12_8 - Reserved. Caution, do not write to this register field.
31249 */
31250#define DDRPHY_DX6GTR0_RESERVED_12_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX6GTR0_RESERVED_12_8_MASK)
31251#define DDRPHY_DX6GTR0_RESERVED_15_13_MASK (0xE000U)
31252#define DDRPHY_DX6GTR0_RESERVED_15_13_SHIFT (13U)
31253/*! RESERVED_15_13 - Reserved. Return zeroes on reads.
31254 */
31255#define DDRPHY_DX6GTR0_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX6GTR0_RESERVED_15_13_MASK)
31256#define DDRPHY_DX6GTR0_WLSL_MASK (0xF0000U)
31257#define DDRPHY_DX6GTR0_WLSL_SHIFT (16U)
31258/*! WLSL - Write Leveling System Latency
31259 */
31260#define DDRPHY_DX6GTR0_WLSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_WLSL_SHIFT)) & DDRPHY_DX6GTR0_WLSL_MASK)
31261#define DDRPHY_DX6GTR0_RESERVED_23_20_MASK (0xF00000U)
31262#define DDRPHY_DX6GTR0_RESERVED_23_20_SHIFT (20U)
31263/*! RESERVED_23_20 - Reserved. Caution, do not write to this register field.
31264 */
31265#define DDRPHY_DX6GTR0_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX6GTR0_RESERVED_23_20_MASK)
31266#define DDRPHY_DX6GTR0_WDQSL_MASK (0x7000000U)
31267#define DDRPHY_DX6GTR0_WDQSL_SHIFT (24U)
31268/*! WDQSL - DQ Write Path Latency Pipeline
31269 */
31270#define DDRPHY_DX6GTR0_WDQSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_WDQSL_SHIFT)) & DDRPHY_DX6GTR0_WDQSL_MASK)
31271#define DDRPHY_DX6GTR0_RESERVED_31_24_MASK (0xF8000000U)
31272#define DDRPHY_DX6GTR0_RESERVED_31_24_SHIFT (27U)
31273/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
31274 */
31275#define DDRPHY_DX6GTR0_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX6GTR0_RESERVED_31_24_MASK)
31276/*! @} */
31277
31278/*! @name DX6RSR0 - DATX8 n Rank Status Register 0 */
31279/*! @{ */
31280#define DDRPHY_DX6RSR0_QSGERR_MASK (0xFFFFU)
31281#define DDRPHY_DX6RSR0_QSGERR_SHIFT (0U)
31282/*! QSGERR - DQS Gate Training Error
31283 */
31284#define DDRPHY_DX6RSR0_QSGERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR0_QSGERR_SHIFT)) & DDRPHY_DX6RSR0_QSGERR_MASK)
31285#define DDRPHY_DX6RSR0_RESERVED_31_16_MASK (0xFFFF0000U)
31286#define DDRPHY_DX6RSR0_RESERVED_31_16_SHIFT (16U)
31287/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
31288 */
31289#define DDRPHY_DX6RSR0_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX6RSR0_RESERVED_31_16_MASK)
31290/*! @} */
31291
31292/*! @name DX6RSR1 - DATX8 n Rank Status Register 1 */
31293/*! @{ */
31294#define DDRPHY_DX6RSR1_RDLVLERR_MASK (0xFFFFU)
31295#define DDRPHY_DX6RSR1_RDLVLERR_SHIFT (0U)
31296/*! RDLVLERR - Read Leveling Error
31297 */
31298#define DDRPHY_DX6RSR1_RDLVLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX6RSR1_RDLVLERR_MASK)
31299#define DDRPHY_DX6RSR1_RESERVED_31_16_MASK (0xFFFF0000U)
31300#define DDRPHY_DX6RSR1_RESERVED_31_16_SHIFT (16U)
31301/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
31302 */
31303#define DDRPHY_DX6RSR1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX6RSR1_RESERVED_31_16_MASK)
31304/*! @} */
31305
31306/*! @name DX6RSR2 - DATX8 n Rank Status Register 2 */
31307/*! @{ */
31308#define DDRPHY_DX6RSR2_WLAWN_MASK (0xFFFFU)
31309#define DDRPHY_DX6RSR2_WLAWN_SHIFT (0U)
31310/*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning
31311 */
31312#define DDRPHY_DX6RSR2_WLAWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR2_WLAWN_SHIFT)) & DDRPHY_DX6RSR2_WLAWN_MASK)
31313#define DDRPHY_DX6RSR2_RESERVED_31_16_MASK (0xFFFF0000U)
31314#define DDRPHY_DX6RSR2_RESERVED_31_16_SHIFT (16U)
31315/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
31316 */
31317#define DDRPHY_DX6RSR2_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX6RSR2_RESERVED_31_16_MASK)
31318/*! @} */
31319
31320/*! @name DX6RSR3 - DATX8 n Rank Status Register 3 */
31321/*! @{ */
31322#define DDRPHY_DX6RSR3_WLAERR_MASK (0xFFFFU)
31323#define DDRPHY_DX6RSR3_WLAERR_SHIFT (0U)
31324/*! WLAERR - Write Leveling Adjustment Error
31325 */
31326#define DDRPHY_DX6RSR3_WLAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR3_WLAERR_SHIFT)) & DDRPHY_DX6RSR3_WLAERR_MASK)
31327#define DDRPHY_DX6RSR3_RESERVED_31_16_MASK (0xFFFF0000U)
31328#define DDRPHY_DX6RSR3_RESERVED_31_16_SHIFT (16U)
31329/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
31330 */
31331#define DDRPHY_DX6RSR3_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX6RSR3_RESERVED_31_16_MASK)
31332/*! @} */
31333
31334/*! @name DX6GSR0 - DATX8 n General Status Register 0 */
31335/*! @{ */
31336#define DDRPHY_DX6GSR0_WDQCAL_MASK (0x1U)
31337#define DDRPHY_DX6GSR0_WDQCAL_SHIFT (0U)
31338/*! WDQCAL - Write DQ Calibration
31339 */
31340#define DDRPHY_DX6GSR0_WDQCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_WDQCAL_SHIFT)) & DDRPHY_DX6GSR0_WDQCAL_MASK)
31341#define DDRPHY_DX6GSR0_RDQSCAL_MASK (0x2U)
31342#define DDRPHY_DX6GSR0_RDQSCAL_SHIFT (1U)
31343/*! RDQSCAL - Read DQS Calibration
31344 */
31345#define DDRPHY_DX6GSR0_RDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX6GSR0_RDQSCAL_MASK)
31346#define DDRPHY_DX6GSR0_RDQSNCAL_MASK (0x4U)
31347#define DDRPHY_DX6GSR0_RDQSNCAL_SHIFT (2U)
31348/*! RDQSNCAL - Read DQS# Calibration
31349 */
31350#define DDRPHY_DX6GSR0_RDQSNCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX6GSR0_RDQSNCAL_MASK)
31351#define DDRPHY_DX6GSR0_GDQSCAL_MASK (0x8U)
31352#define DDRPHY_DX6GSR0_GDQSCAL_SHIFT (3U)
31353/*! GDQSCAL - Read DQS gating Calibration
31354 */
31355#define DDRPHY_DX6GSR0_GDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX6GSR0_GDQSCAL_MASK)
31356#define DDRPHY_DX6GSR0_WLCAL_MASK (0x10U)
31357#define DDRPHY_DX6GSR0_WLCAL_SHIFT (4U)
31358/*! WLCAL - Write Leveling Calibration
31359 */
31360#define DDRPHY_DX6GSR0_WLCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_WLCAL_SHIFT)) & DDRPHY_DX6GSR0_WLCAL_MASK)
31361#define DDRPHY_DX6GSR0_WLDONE_MASK (0x20U)
31362#define DDRPHY_DX6GSR0_WLDONE_SHIFT (5U)
31363/*! WLDONE - Write Leveling Done
31364 */
31365#define DDRPHY_DX6GSR0_WLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_WLDONE_SHIFT)) & DDRPHY_DX6GSR0_WLDONE_MASK)
31366#define DDRPHY_DX6GSR0_WLERR_MASK (0x40U)
31367#define DDRPHY_DX6GSR0_WLERR_SHIFT (6U)
31368/*! WLERR - Write Leveling Error
31369 */
31370#define DDRPHY_DX6GSR0_WLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_WLERR_SHIFT)) & DDRPHY_DX6GSR0_WLERR_MASK)
31371#define DDRPHY_DX6GSR0_WLPRD_MASK (0xFF80U)
31372#define DDRPHY_DX6GSR0_WLPRD_SHIFT (7U)
31373/*! WLPRD - Write Leveling Period
31374 */
31375#define DDRPHY_DX6GSR0_WLPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_WLPRD_SHIFT)) & DDRPHY_DX6GSR0_WLPRD_MASK)
31376#define DDRPHY_DX6GSR0_DPLOCK_MASK (0x10000U)
31377#define DDRPHY_DX6GSR0_DPLOCK_SHIFT (16U)
31378/*! DPLOCK - DATX8 PLL Lock
31379 */
31380#define DDRPHY_DX6GSR0_DPLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_DPLOCK_SHIFT)) & DDRPHY_DX6GSR0_DPLOCK_MASK)
31381#define DDRPHY_DX6GSR0_GDQSPRD_MASK (0x3FE0000U)
31382#define DDRPHY_DX6GSR0_GDQSPRD_SHIFT (17U)
31383/*! GDQSPRD - Read DQS gating Period
31384 */
31385#define DDRPHY_DX6GSR0_GDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX6GSR0_GDQSPRD_MASK)
31386#define DDRPHY_DX6GSR0_RESERVED_29_26_MASK (0x3C000000U)
31387#define DDRPHY_DX6GSR0_RESERVED_29_26_SHIFT (26U)
31388/*! RESERVED_29_26 - Reserved. Returns zeroes on reads.
31389 */
31390#define DDRPHY_DX6GSR0_RESERVED_29_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX6GSR0_RESERVED_29_26_MASK)
31391#define DDRPHY_DX6GSR0_WLDQ_MASK (0x40000000U)
31392#define DDRPHY_DX6GSR0_WLDQ_SHIFT (30U)
31393/*! WLDQ - Write Leveling DQ Status
31394 */
31395#define DDRPHY_DX6GSR0_WLDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_WLDQ_SHIFT)) & DDRPHY_DX6GSR0_WLDQ_MASK)
31396#define DDRPHY_DX6GSR0_RESERVED_31_MASK (0x80000000U)
31397#define DDRPHY_DX6GSR0_RESERVED_31_SHIFT (31U)
31398/*! RESERVED_31 - Reserved. Returns zeroes on reads.
31399 */
31400#define DDRPHY_DX6GSR0_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX6GSR0_RESERVED_31_MASK)
31401/*! @} */
31402
31403/*! @name DX6GSR1 - DATX8 n General Status Register 1 */
31404/*! @{ */
31405#define DDRPHY_DX6GSR1_DLTDONE_MASK (0x1U)
31406#define DDRPHY_DX6GSR1_DLTDONE_SHIFT (0U)
31407/*! DLTDONE - Delay Line Test Done
31408 */
31409#define DDRPHY_DX6GSR1_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR1_DLTDONE_SHIFT)) & DDRPHY_DX6GSR1_DLTDONE_MASK)
31410#define DDRPHY_DX6GSR1_DLTCODE_MASK (0x1FFFFFEU)
31411#define DDRPHY_DX6GSR1_DLTCODE_SHIFT (1U)
31412/*! DLTCODE - Delay Line Test Code
31413 */
31414#define DDRPHY_DX6GSR1_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR1_DLTCODE_SHIFT)) & DDRPHY_DX6GSR1_DLTCODE_MASK)
31415#define DDRPHY_DX6GSR1_RESERVED_31_25_MASK (0xFE000000U)
31416#define DDRPHY_DX6GSR1_RESERVED_31_25_SHIFT (25U)
31417/*! RESERVED_31_25 - Reserved. Returns zeroes on reads.
31418 */
31419#define DDRPHY_DX6GSR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX6GSR1_RESERVED_31_25_MASK)
31420/*! @} */
31421
31422/*! @name DX6GSR2 - DATX8 n General Status Register 2 */
31423/*! @{ */
31424#define DDRPHY_DX6GSR2_RDERR_MASK (0x1U)
31425#define DDRPHY_DX6GSR2_RDERR_SHIFT (0U)
31426/*! RDERR - Read Bit Deskew Error
31427 */
31428#define DDRPHY_DX6GSR2_RDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_RDERR_SHIFT)) & DDRPHY_DX6GSR2_RDERR_MASK)
31429#define DDRPHY_DX6GSR2_RDWN_MASK (0x2U)
31430#define DDRPHY_DX6GSR2_RDWN_SHIFT (1U)
31431/*! RDWN - Read Bit Deskew Warning
31432 */
31433#define DDRPHY_DX6GSR2_RDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_RDWN_SHIFT)) & DDRPHY_DX6GSR2_RDWN_MASK)
31434#define DDRPHY_DX6GSR2_WDERR_MASK (0x4U)
31435#define DDRPHY_DX6GSR2_WDERR_SHIFT (2U)
31436/*! WDERR - Write Bit Deskew Error
31437 */
31438#define DDRPHY_DX6GSR2_WDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_WDERR_SHIFT)) & DDRPHY_DX6GSR2_WDERR_MASK)
31439#define DDRPHY_DX6GSR2_WDWN_MASK (0x8U)
31440#define DDRPHY_DX6GSR2_WDWN_SHIFT (3U)
31441/*! WDWN - Write Bit Deskew Warning
31442 */
31443#define DDRPHY_DX6GSR2_WDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_WDWN_SHIFT)) & DDRPHY_DX6GSR2_WDWN_MASK)
31444#define DDRPHY_DX6GSR2_REERR_MASK (0x10U)
31445#define DDRPHY_DX6GSR2_REERR_SHIFT (4U)
31446/*! REERR - Read Eye Centering Error
31447 */
31448#define DDRPHY_DX6GSR2_REERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_REERR_SHIFT)) & DDRPHY_DX6GSR2_REERR_MASK)
31449#define DDRPHY_DX6GSR2_REWN_MASK (0x20U)
31450#define DDRPHY_DX6GSR2_REWN_SHIFT (5U)
31451/*! REWN - Read Eye Centering Warning
31452 */
31453#define DDRPHY_DX6GSR2_REWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_REWN_SHIFT)) & DDRPHY_DX6GSR2_REWN_MASK)
31454#define DDRPHY_DX6GSR2_WEERR_MASK (0x40U)
31455#define DDRPHY_DX6GSR2_WEERR_SHIFT (6U)
31456/*! WEERR - Write Eye Centering Error
31457 */
31458#define DDRPHY_DX6GSR2_WEERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_WEERR_SHIFT)) & DDRPHY_DX6GSR2_WEERR_MASK)
31459#define DDRPHY_DX6GSR2_WEWN_MASK (0x80U)
31460#define DDRPHY_DX6GSR2_WEWN_SHIFT (7U)
31461/*! WEWN - Write Eye Centering Warning
31462 */
31463#define DDRPHY_DX6GSR2_WEWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_WEWN_SHIFT)) & DDRPHY_DX6GSR2_WEWN_MASK)
31464#define DDRPHY_DX6GSR2_ESTAT_MASK (0xF00U)
31465#define DDRPHY_DX6GSR2_ESTAT_SHIFT (8U)
31466/*! ESTAT - Error Status
31467 */
31468#define DDRPHY_DX6GSR2_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_ESTAT_SHIFT)) & DDRPHY_DX6GSR2_ESTAT_MASK)
31469#define DDRPHY_DX6GSR2_DQS2DQERR_MASK (0xFF000U)
31470#define DDRPHY_DX6GSR2_DQS2DQERR_SHIFT (12U)
31471/*! DQS2DQERR - Write DQS2DQ Training Error
31472 */
31473#define DDRPHY_DX6GSR2_DQS2DQERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX6GSR2_DQS2DQERR_MASK)
31474#define DDRPHY_DX6GSR2_SRDERR_MASK (0x100000U)
31475#define DDRPHY_DX6GSR2_SRDERR_SHIFT (20U)
31476/*! SRDERR - Static Read Error
31477 */
31478#define DDRPHY_DX6GSR2_SRDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_SRDERR_SHIFT)) & DDRPHY_DX6GSR2_SRDERR_MASK)
31479#define DDRPHY_DX6GSR2_RESERVED_21_MASK (0x200000U)
31480#define DDRPHY_DX6GSR2_RESERVED_21_SHIFT (21U)
31481/*! RESERVED_21 - Reserved. Return zeroes on reads.
31482 */
31483#define DDRPHY_DX6GSR2_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX6GSR2_RESERVED_21_MASK)
31484#define DDRPHY_DX6GSR2_GSDQSCAL_MASK (0x400000U)
31485#define DDRPHY_DX6GSR2_GSDQSCAL_SHIFT (22U)
31486/*! GSDQSCAL - Read DQS Gating Status Calibration
31487 */
31488#define DDRPHY_DX6GSR2_GSDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX6GSR2_GSDQSCAL_MASK)
31489#define DDRPHY_DX6GSR2_GSDQSPRD_MASK (0xFF800000U)
31490#define DDRPHY_DX6GSR2_GSDQSPRD_SHIFT (23U)
31491/*! GSDQSPRD - Read DQS gating Status Period
31492 */
31493#define DDRPHY_DX6GSR2_GSDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX6GSR2_GSDQSPRD_MASK)
31494/*! @} */
31495
31496/*! @name DX6GSR3 - DATX8 n General Status Register 3 */
31497/*! @{ */
31498#define DDRPHY_DX6GSR3_SRDPC_MASK (0x3U)
31499#define DDRPHY_DX6GSR3_SRDPC_SHIFT (0U)
31500/*! SRDPC - Static Read Delay Pass Count
31501 */
31502#define DDRPHY_DX6GSR3_SRDPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_SRDPC_SHIFT)) & DDRPHY_DX6GSR3_SRDPC_MASK)
31503#define DDRPHY_DX6GSR3_RESERVED_7_2_MASK (0xFCU)
31504#define DDRPHY_DX6GSR3_RESERVED_7_2_SHIFT (2U)
31505/*! RESERVED_7_2 - Reserved. Return zeroes on reads.
31506 */
31507#define DDRPHY_DX6GSR3_RESERVED_7_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX6GSR3_RESERVED_7_2_MASK)
31508#define DDRPHY_DX6GSR3_HVERR_MASK (0xF00U)
31509#define DDRPHY_DX6GSR3_HVERR_SHIFT (8U)
31510/*! HVERR - Host VREF Training Error
31511 */
31512#define DDRPHY_DX6GSR3_HVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_HVERR_SHIFT)) & DDRPHY_DX6GSR3_HVERR_MASK)
31513#define DDRPHY_DX6GSR3_HVWRN_MASK (0xF000U)
31514#define DDRPHY_DX6GSR3_HVWRN_SHIFT (12U)
31515/*! HVWRN - Host VREF Training Warning
31516 */
31517#define DDRPHY_DX6GSR3_HVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_HVWRN_SHIFT)) & DDRPHY_DX6GSR3_HVWRN_MASK)
31518#define DDRPHY_DX6GSR3_DVERR_MASK (0xF0000U)
31519#define DDRPHY_DX6GSR3_DVERR_SHIFT (16U)
31520/*! DVERR - DRAM VREF Training Error
31521 */
31522#define DDRPHY_DX6GSR3_DVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_DVERR_SHIFT)) & DDRPHY_DX6GSR3_DVERR_MASK)
31523#define DDRPHY_DX6GSR3_DVWRN_MASK (0xF00000U)
31524#define DDRPHY_DX6GSR3_DVWRN_SHIFT (20U)
31525/*! DVWRN - DRAM VREF Training Warning
31526 */
31527#define DDRPHY_DX6GSR3_DVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_DVWRN_SHIFT)) & DDRPHY_DX6GSR3_DVWRN_MASK)
31528#define DDRPHY_DX6GSR3_ESTAT_MASK (0x7000000U)
31529#define DDRPHY_DX6GSR3_ESTAT_SHIFT (24U)
31530/*! ESTAT - VREF Training Error Status Code
31531 */
31532#define DDRPHY_DX6GSR3_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_ESTAT_SHIFT)) & DDRPHY_DX6GSR3_ESTAT_MASK)
31533#define DDRPHY_DX6GSR3_RESERVED_31_27_MASK (0xF8000000U)
31534#define DDRPHY_DX6GSR3_RESERVED_31_27_SHIFT (27U)
31535/*! RESERVED_31_27 - Reserved. Return zeroes on reads.
31536 */
31537#define DDRPHY_DX6GSR3_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX6GSR3_RESERVED_31_27_MASK)
31538/*! @} */
31539
31540/*! @name DX6GSR4 - DATX8 n General Status Register 4 */
31541/*! @{ */
31542#define DDRPHY_DX6GSR4_RESERVED_0_MASK (0x1U)
31543#define DDRPHY_DX6GSR4_RESERVED_0_SHIFT (0U)
31544/*! RESERVED_0 - Reserved. Return zeroes on reads.
31545 */
31546#define DDRPHY_DX6GSR4_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_0_MASK)
31547#define DDRPHY_DX6GSR4_RESERVED_1_MASK (0x2U)
31548#define DDRPHY_DX6GSR4_RESERVED_1_SHIFT (1U)
31549/*! RESERVED_1 - Reserved. Return zeroes on reads.
31550 */
31551#define DDRPHY_DX6GSR4_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_1_MASK)
31552#define DDRPHY_DX6GSR4_RESERVED_2_MASK (0x4U)
31553#define DDRPHY_DX6GSR4_RESERVED_2_SHIFT (2U)
31554/*! RESERVED_2 - Reserved. Return zeroes on reads.
31555 */
31556#define DDRPHY_DX6GSR4_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_2_MASK)
31557#define DDRPHY_DX6GSR4_RESERVED_3_MASK (0x8U)
31558#define DDRPHY_DX6GSR4_RESERVED_3_SHIFT (3U)
31559/*! RESERVED_3 - Reserved. Return zeroes on reads.
31560 */
31561#define DDRPHY_DX6GSR4_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_3_MASK)
31562#define DDRPHY_DX6GSR4_RESERVED_4_MASK (0x10U)
31563#define DDRPHY_DX6GSR4_RESERVED_4_SHIFT (4U)
31564/*! RESERVED_4 - Reserved. Return zeroes on reads.
31565 */
31566#define DDRPHY_DX6GSR4_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_4_MASK)
31567#define DDRPHY_DX6GSR4_RESERVED_5_MASK (0x20U)
31568#define DDRPHY_DX6GSR4_RESERVED_5_SHIFT (5U)
31569/*! RESERVED_5 - Reserved. Return zeroes on reads.
31570 */
31571#define DDRPHY_DX6GSR4_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_5_MASK)
31572#define DDRPHY_DX6GSR4_RESERVED_6_MASK (0x40U)
31573#define DDRPHY_DX6GSR4_RESERVED_6_SHIFT (6U)
31574/*! RESERVED_6 - Reserved. Return zeroes on reads.
31575 */
31576#define DDRPHY_DX6GSR4_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_6_MASK)
31577#define DDRPHY_DX6GSR4_RESERVED_15_7_MASK (0xFF80U)
31578#define DDRPHY_DX6GSR4_RESERVED_15_7_SHIFT (7U)
31579/*! RESERVED_15_7 - Reserved. Return zeroes on reads.
31580 */
31581#define DDRPHY_DX6GSR4_RESERVED_15_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_15_7_MASK)
31582#define DDRPHY_DX6GSR4_RESERVED_16_MASK (0x10000U)
31583#define DDRPHY_DX6GSR4_RESERVED_16_SHIFT (16U)
31584/*! RESERVED_16 - Reserved. Return zeroes on reads.
31585 */
31586#define DDRPHY_DX6GSR4_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_16_MASK)
31587#define DDRPHY_DX6GSR4_RESERVED_25_17_MASK (0x3FE0000U)
31588#define DDRPHY_DX6GSR4_RESERVED_25_17_SHIFT (17U)
31589/*! RESERVED_25_17 - Reserved. Return zeroes on reads.
31590 */
31591#define DDRPHY_DX6GSR4_RESERVED_25_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_25_17_MASK)
31592#define DDRPHY_DX6GSR4_RESERVED_31_26_MASK (0xFC000000U)
31593#define DDRPHY_DX6GSR4_RESERVED_31_26_SHIFT (26U)
31594/*! RESERVED_31_26 - Reserved. Returns zeroes on reads.
31595 */
31596#define DDRPHY_DX6GSR4_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX6GSR4_RESERVED_31_26_MASK)
31597/*! @} */
31598
31599/*! @name DX6GSR5 - DATX8 n General Status Register 5 */
31600/*! @{ */
31601#define DDRPHY_DX6GSR5_RESERVED_0_MASK (0x1U)
31602#define DDRPHY_DX6GSR5_RESERVED_0_SHIFT (0U)
31603/*! RESERVED_0 - Reserved. Return zeroes on reads.
31604 */
31605#define DDRPHY_DX6GSR5_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_0_MASK)
31606#define DDRPHY_DX6GSR5_RESERVED_1_MASK (0x2U)
31607#define DDRPHY_DX6GSR5_RESERVED_1_SHIFT (1U)
31608/*! RESERVED_1 - Reserved. Return zeroes on reads.
31609 */
31610#define DDRPHY_DX6GSR5_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_1_MASK)
31611#define DDRPHY_DX6GSR5_RESERVED_2_MASK (0x4U)
31612#define DDRPHY_DX6GSR5_RESERVED_2_SHIFT (2U)
31613/*! RESERVED_2 - Reserved. Return zeroes on reads.
31614 */
31615#define DDRPHY_DX6GSR5_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_2_MASK)
31616#define DDRPHY_DX6GSR5_RESERVED_3_MASK (0x8U)
31617#define DDRPHY_DX6GSR5_RESERVED_3_SHIFT (3U)
31618/*! RESERVED_3 - Reserved. Return zeroes on reads.
31619 */
31620#define DDRPHY_DX6GSR5_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_3_MASK)
31621#define DDRPHY_DX6GSR5_RESERVED_4_MASK (0x10U)
31622#define DDRPHY_DX6GSR5_RESERVED_4_SHIFT (4U)
31623/*! RESERVED_4 - Reserved. Return zeroes on reads.
31624 */
31625#define DDRPHY_DX6GSR5_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_4_MASK)
31626#define DDRPHY_DX6GSR5_RESERVED_5_MASK (0x20U)
31627#define DDRPHY_DX6GSR5_RESERVED_5_SHIFT (5U)
31628/*! RESERVED_5 - Reserved. Return zeroes on reads.
31629 */
31630#define DDRPHY_DX6GSR5_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_5_MASK)
31631#define DDRPHY_DX6GSR5_RESERVED_6_MASK (0x40U)
31632#define DDRPHY_DX6GSR5_RESERVED_6_SHIFT (6U)
31633/*! RESERVED_6 - Reserved. Return zeroes on reads.
31634 */
31635#define DDRPHY_DX6GSR5_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_6_MASK)
31636#define DDRPHY_DX6GSR5_RESERVED_7_MASK (0x80U)
31637#define DDRPHY_DX6GSR5_RESERVED_7_SHIFT (7U)
31638/*! RESERVED_7 - Reserved. Return zeroes on reads.
31639 */
31640#define DDRPHY_DX6GSR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_7_MASK)
31641#define DDRPHY_DX6GSR5_RESERVED_11_8_MASK (0xF00U)
31642#define DDRPHY_DX6GSR5_RESERVED_11_8_SHIFT (8U)
31643/*! RESERVED_11_8 - Reserved. Return zeroes on reads.
31644 */
31645#define DDRPHY_DX6GSR5_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_11_8_MASK)
31646#define DDRPHY_DX6GSR5_RESERVED_19_12_MASK (0xFF000U)
31647#define DDRPHY_DX6GSR5_RESERVED_19_12_SHIFT (12U)
31648/*! RESERVED_19_12 - Reserved. Return zeroes on reads.
31649 */
31650#define DDRPHY_DX6GSR5_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_19_12_MASK)
31651#define DDRPHY_DX6GSR5_RESERVED_20_MASK (0x100000U)
31652#define DDRPHY_DX6GSR5_RESERVED_20_SHIFT (20U)
31653/*! RESERVED_20 - Reserved. Return zeroes on reads.
31654 */
31655#define DDRPHY_DX6GSR5_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_20_MASK)
31656#define DDRPHY_DX6GSR5_RESERVED_21_MASK (0x200000U)
31657#define DDRPHY_DX6GSR5_RESERVED_21_SHIFT (21U)
31658/*! RESERVED_21 - Reserved. Return zeroes on reads.
31659 */
31660#define DDRPHY_DX6GSR5_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_21_MASK)
31661#define DDRPHY_DX6GSR5_RESERVED_22_MASK (0x400000U)
31662#define DDRPHY_DX6GSR5_RESERVED_22_SHIFT (22U)
31663/*! RESERVED_22 - Reserved. Return zeroes on reads.
31664 */
31665#define DDRPHY_DX6GSR5_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_22_MASK)
31666#define DDRPHY_DX6GSR5_RESERVED_31_23_MASK (0xFF800000U)
31667#define DDRPHY_DX6GSR5_RESERVED_31_23_SHIFT (23U)
31668/*! RESERVED_31_23 - Reserved. Return zeroes on reads.
31669 */
31670#define DDRPHY_DX6GSR5_RESERVED_31_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX6GSR5_RESERVED_31_23_MASK)
31671/*! @} */
31672
31673/*! @name DX6GSR6 - DATX8 n General Status Register 6 */
31674/*! @{ */
31675#define DDRPHY_DX6GSR6_RESERVED_1_0_MASK (0x3U)
31676#define DDRPHY_DX6GSR6_RESERVED_1_0_SHIFT (0U)
31677/*! RESERVED_1_0 - Reserved. Return zeroes on reads.
31678 */
31679#define DDRPHY_DX6GSR6_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_1_0_MASK)
31680#define DDRPHY_DX6GSR6_RESERVED_3_2_MASK (0xCU)
31681#define DDRPHY_DX6GSR6_RESERVED_3_2_SHIFT (2U)
31682/*! RESERVED_3_2 - Reserved. Return zeroes on reads.
31683 */
31684#define DDRPHY_DX6GSR6_RESERVED_3_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_3_2_MASK)
31685#define DDRPHY_DX6GSR6_RESERVED_7_4_MASK (0xF0U)
31686#define DDRPHY_DX6GSR6_RESERVED_7_4_SHIFT (4U)
31687/*! RESERVED_7_4 - Reserved. Return zeroes on reads.
31688 */
31689#define DDRPHY_DX6GSR6_RESERVED_7_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_7_4_MASK)
31690#define DDRPHY_DX6GSR6_RESERVED_11_8_MASK (0xF00U)
31691#define DDRPHY_DX6GSR6_RESERVED_11_8_SHIFT (8U)
31692/*! RESERVED_11_8 - Reserved. Return zeroes on reads.
31693 */
31694#define DDRPHY_DX6GSR6_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_11_8_MASK)
31695#define DDRPHY_DX6GSR6_RESERVED_15_12_MASK (0xF000U)
31696#define DDRPHY_DX6GSR6_RESERVED_15_12_SHIFT (12U)
31697/*! RESERVED_15_12 - Reserved. Return zeroes on reads.
31698 */
31699#define DDRPHY_DX6GSR6_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_15_12_MASK)
31700#define DDRPHY_DX6GSR6_RESERVED_19_15_MASK (0xF0000U)
31701#define DDRPHY_DX6GSR6_RESERVED_19_15_SHIFT (16U)
31702/*! RESERVED_19_15 - Reserved. Return zeroes on reads.
31703 */
31704#define DDRPHY_DX6GSR6_RESERVED_19_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_19_15_MASK)
31705#define DDRPHY_DX6GSR6_RESERVED_23_20_MASK (0xF00000U)
31706#define DDRPHY_DX6GSR6_RESERVED_23_20_SHIFT (20U)
31707/*! RESERVED_23_20 - Reserved. Return zeroes on reads.
31708 */
31709#define DDRPHY_DX6GSR6_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_23_20_MASK)
31710#define DDRPHY_DX6GSR6_RESERVED_31_24_MASK (0xFF000000U)
31711#define DDRPHY_DX6GSR6_RESERVED_31_24_SHIFT (24U)
31712/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
31713 */
31714#define DDRPHY_DX6GSR6_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX6GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX6GSR6_RESERVED_31_24_MASK)
31715/*! @} */
31716
31717/*! @name DX7GCR0 - DATX8 n General Configuration Register 0 */
31718/*! @{ */
31719#define DDRPHY_DX7GCR0_RESERVED_1_0_MASK (0x3U)
31720#define DDRPHY_DX7GCR0_RESERVED_1_0_SHIFT (0U)
31721/*! RESERVED_1_0 - Reserved. Return zeroes on reads.
31722 */
31723#define DDRPHY_DX7GCR0_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX7GCR0_RESERVED_1_0_MASK)
31724#define DDRPHY_DX7GCR0_DQSGOE_MASK (0x4U)
31725#define DDRPHY_DX7GCR0_DQSGOE_SHIFT (2U)
31726/*! DQSGOE - DQSG Output Enable
31727 */
31728#define DDRPHY_DX7GCR0_DQSGOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSGOE_SHIFT)) & DDRPHY_DX7GCR0_DQSGOE_MASK)
31729#define DDRPHY_DX7GCR0_DQSGODT_MASK (0x8U)
31730#define DDRPHY_DX7GCR0_DQSGODT_SHIFT (3U)
31731/*! DQSGODT - DQSG On-Die Termination
31732 */
31733#define DDRPHY_DX7GCR0_DQSGODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSGODT_SHIFT)) & DDRPHY_DX7GCR0_DQSGODT_MASK)
31734#define DDRPHY_DX7GCR0_RESERVED_4_MASK (0x10U)
31735#define DDRPHY_DX7GCR0_RESERVED_4_SHIFT (4U)
31736/*! RESERVED_4 - Reserved. Return zeroes on reads.
31737 */
31738#define DDRPHY_DX7GCR0_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX7GCR0_RESERVED_4_MASK)
31739#define DDRPHY_DX7GCR0_DQSGPDR_MASK (0x20U)
31740#define DDRPHY_DX7GCR0_DQSGPDR_SHIFT (5U)
31741/*! DQSGPDR - DQSG Power Down Receiver
31742 */
31743#define DDRPHY_DX7GCR0_DQSGPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX7GCR0_DQSGPDR_MASK)
31744#define DDRPHY_DX7GCR0_DQSRPD_MASK (0x40U)
31745#define DDRPHY_DX7GCR0_DQSRPD_SHIFT (6U)
31746/*! DQSRPD - DQSR Power Down
31747 */
31748#define DDRPHY_DX7GCR0_DQSRPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSRPD_SHIFT)) & DDRPHY_DX7GCR0_DQSRPD_MASK)
31749#define DDRPHY_DX7GCR0_CPDRSHFT_MASK (0x180U)
31750#define DDRPHY_DX7GCR0_CPDRSHFT_SHIFT (7U)
31751/*! CPDRSHFT - Configurable PDR Phase Shift
31752 */
31753#define DDRPHY_DX7GCR0_CPDRSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX7GCR0_CPDRSHFT_MASK)
31754#define DDRPHY_DX7GCR0_RTTOH_MASK (0x600U)
31755#define DDRPHY_DX7GCR0_RTTOH_SHIFT (9U)
31756/*! RTTOH - RTT Output Hold
31757 */
31758#define DDRPHY_DX7GCR0_RTTOH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_RTTOH_SHIFT)) & DDRPHY_DX7GCR0_RTTOH_MASK)
31759#define DDRPHY_DX7GCR0_RTTOAL_MASK (0x800U)
31760#define DDRPHY_DX7GCR0_RTTOAL_SHIFT (11U)
31761/*! RTTOAL - RTT On Additive Latency
31762 */
31763#define DDRPHY_DX7GCR0_RTTOAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_RTTOAL_SHIFT)) & DDRPHY_DX7GCR0_RTTOAL_MASK)
31764#define DDRPHY_DX7GCR0_DQSSEPDR_MASK (0x1000U)
31765#define DDRPHY_DX7GCR0_DQSSEPDR_SHIFT (12U)
31766/*! DQSSEPDR - DQSSE Power Down Receiver
31767 */
31768#define DDRPHY_DX7GCR0_DQSSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX7GCR0_DQSSEPDR_MASK)
31769#define DDRPHY_DX7GCR0_DQSNSEPDR_MASK (0x2000U)
31770#define DDRPHY_DX7GCR0_DQSNSEPDR_SHIFT (13U)
31771/*! DQSNSEPDR - DQSNSE Power Down Receiver
31772 */
31773#define DDRPHY_DX7GCR0_DQSNSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX7GCR0_DQSNSEPDR_MASK)
31774#define DDRPHY_DX7GCR0_RESERVED_19_14_MASK (0xFC000U)
31775#define DDRPHY_DX7GCR0_RESERVED_19_14_SHIFT (14U)
31776/*! RESERVED_19_14 - Reserved. Return zeroes on reads.
31777 */
31778#define DDRPHY_DX7GCR0_RESERVED_19_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX7GCR0_RESERVED_19_14_MASK)
31779#define DDRPHY_DX7GCR0_RDDLY_MASK (0xF00000U)
31780#define DDRPHY_DX7GCR0_RDDLY_SHIFT (20U)
31781/*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
31782 */
31783#define DDRPHY_DX7GCR0_RDDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_RDDLY_SHIFT)) & DDRPHY_DX7GCR0_RDDLY_MASK)
31784#define DDRPHY_DX7GCR0_DQSDCC_MASK (0xF000000U)
31785#define DDRPHY_DX7GCR0_DQSDCC_SHIFT (24U)
31786/*! DQSDCC - DQS Duty Cycle Correction
31787 */
31788#define DDRPHY_DX7GCR0_DQSDCC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_DQSDCC_SHIFT)) & DDRPHY_DX7GCR0_DQSDCC_MASK)
31789#define DDRPHY_DX7GCR0_CODTSHFT_MASK (0x30000000U)
31790#define DDRPHY_DX7GCR0_CODTSHFT_SHIFT (28U)
31791/*! CODTSHFT - Configurable ODT(TE) Phase Shift
31792 */
31793#define DDRPHY_DX7GCR0_CODTSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX7GCR0_CODTSHFT_MASK)
31794#define DDRPHY_DX7GCR0_MDLEN_MASK (0x40000000U)
31795#define DDRPHY_DX7GCR0_MDLEN_SHIFT (30U)
31796/*! MDLEN - Master Delay Line Enable
31797 */
31798#define DDRPHY_DX7GCR0_MDLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_MDLEN_SHIFT)) & DDRPHY_DX7GCR0_MDLEN_MASK)
31799#define DDRPHY_DX7GCR0_CALBYP_MASK (0x80000000U)
31800#define DDRPHY_DX7GCR0_CALBYP_SHIFT (31U)
31801/*! CALBYP - Calibration Bypass
31802 */
31803#define DDRPHY_DX7GCR0_CALBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR0_CALBYP_SHIFT)) & DDRPHY_DX7GCR0_CALBYP_MASK)
31804/*! @} */
31805
31806/*! @name DX7GCR1 - DATX8 n General Configuration Register 1 */
31807/*! @{ */
31808#define DDRPHY_DX7GCR1_DQEN_MASK (0xFFU)
31809#define DDRPHY_DX7GCR1_DQEN_SHIFT (0U)
31810/*! DQEN - Enables DQ corresponding to each bit in a byte
31811 */
31812#define DDRPHY_DX7GCR1_DQEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_DQEN_SHIFT)) & DDRPHY_DX7GCR1_DQEN_MASK)
31813#define DDRPHY_DX7GCR1_DMEN_MASK (0x100U)
31814#define DDRPHY_DX7GCR1_DMEN_SHIFT (8U)
31815/*! DMEN - Enables DM pin in a byte lane
31816 */
31817#define DDRPHY_DX7GCR1_DMEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_DMEN_SHIFT)) & DDRPHY_DX7GCR1_DMEN_MASK)
31818#define DDRPHY_DX7GCR1_DSEN_MASK (0x200U)
31819#define DDRPHY_DX7GCR1_DSEN_SHIFT (9U)
31820/*! DSEN - Enables Write Data strobe in a byte lane
31821 */
31822#define DDRPHY_DX7GCR1_DSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_DSEN_SHIFT)) & DDRPHY_DX7GCR1_DSEN_MASK)
31823#define DDRPHY_DX7GCR1_TEEN_MASK (0x400U)
31824#define DDRPHY_DX7GCR1_TEEN_SHIFT (10U)
31825/*! TEEN - Enables ODT/TE in a byte lane
31826 */
31827#define DDRPHY_DX7GCR1_TEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_TEEN_SHIFT)) & DDRPHY_DX7GCR1_TEEN_MASK)
31828#define DDRPHY_DX7GCR1_PDREN_MASK (0x800U)
31829#define DDRPHY_DX7GCR1_PDREN_SHIFT (11U)
31830/*! PDREN - Enables PDR in a byte lane
31831 */
31832#define DDRPHY_DX7GCR1_PDREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_PDREN_SHIFT)) & DDRPHY_DX7GCR1_PDREN_MASK)
31833#define DDRPHY_DX7GCR1_OEEN_MASK (0x1000U)
31834#define DDRPHY_DX7GCR1_OEEN_SHIFT (12U)
31835/*! OEEN - Enables Read Data Strobe in a byte lane
31836 */
31837#define DDRPHY_DX7GCR1_OEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_OEEN_SHIFT)) & DDRPHY_DX7GCR1_OEEN_MASK)
31838#define DDRPHY_DX7GCR1_QSSEL_MASK (0x2000U)
31839#define DDRPHY_DX7GCR1_QSSEL_SHIFT (13U)
31840/*! QSSEL - Select the delayed or non-delayed read data strobe
31841 */
31842#define DDRPHY_DX7GCR1_QSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_QSSEL_SHIFT)) & DDRPHY_DX7GCR1_QSSEL_MASK)
31843#define DDRPHY_DX7GCR1_QSNSEL_MASK (0x4000U)
31844#define DDRPHY_DX7GCR1_QSNSEL_SHIFT (14U)
31845/*! QSNSEL - Select the delayed or non-delayed read data strobe #
31846 */
31847#define DDRPHY_DX7GCR1_QSNSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_QSNSEL_SHIFT)) & DDRPHY_DX7GCR1_QSNSEL_MASK)
31848#define DDRPHY_DX7GCR1_RESERVED_15_MASK (0x8000U)
31849#define DDRPHY_DX7GCR1_RESERVED_15_SHIFT (15U)
31850/*! RESERVED_15 - Reserved. Returns zeroes on reads.
31851 */
31852#define DDRPHY_DX7GCR1_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX7GCR1_RESERVED_15_MASK)
31853#define DDRPHY_DX7GCR1_DXPDRMODE_MASK (0xFFFF0000U)
31854#define DDRPHY_DX7GCR1_DXPDRMODE_SHIFT (16U)
31855/*! DXPDRMODE - Enables the PDR mode for DQ[7:0]
31856 */
31857#define DDRPHY_DX7GCR1_DXPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX7GCR1_DXPDRMODE_MASK)
31858/*! @} */
31859
31860/*! @name DX7GCR2 - DATX8 n General Configuration Register 2 */
31861/*! @{ */
31862#define DDRPHY_DX7GCR2_DXTEMODE_MASK (0xFFFFU)
31863#define DDRPHY_DX7GCR2_DXTEMODE_SHIFT (0U)
31864/*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0]
31865 */
31866#define DDRPHY_DX7GCR2_DXTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX7GCR2_DXTEMODE_MASK)
31867#define DDRPHY_DX7GCR2_DXOEMODE_MASK (0xFFFF0000U)
31868#define DDRPHY_DX7GCR2_DXOEMODE_SHIFT (16U)
31869/*! DXOEMODE - Enables the OE mode values for DQ[7:0]
31870 */
31871#define DDRPHY_DX7GCR2_DXOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX7GCR2_DXOEMODE_MASK)
31872/*! @} */
31873
31874/*! @name DX7GCR3 - DATX8 n General Configuration Register 3 */
31875/*! @{ */
31876#define DDRPHY_DX7GCR3_WDMBVT_MASK (0x1U)
31877#define DDRPHY_DX7GCR3_WDMBVT_SHIFT (0U)
31878/*! WDMBVT - Write Data Mask BDL VT Compensation
31879 */
31880#define DDRPHY_DX7GCR3_WDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_WDMBVT_SHIFT)) & DDRPHY_DX7GCR3_WDMBVT_MASK)
31881#define DDRPHY_DX7GCR3_RDMBVT_MASK (0x2U)
31882#define DDRPHY_DX7GCR3_RDMBVT_SHIFT (1U)
31883/*! RDMBVT - Read Data Mask BDL VT Compensation
31884 */
31885#define DDRPHY_DX7GCR3_RDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_RDMBVT_SHIFT)) & DDRPHY_DX7GCR3_RDMBVT_MASK)
31886#define DDRPHY_DX7GCR3_DSPDRMODE_MASK (0xCU)
31887#define DDRPHY_DX7GCR3_DSPDRMODE_SHIFT (2U)
31888/*! DSPDRMODE - Enables the PDR mode values for DQS.
31889 */
31890#define DDRPHY_DX7GCR3_DSPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX7GCR3_DSPDRMODE_MASK)
31891#define DDRPHY_DX7GCR3_DSTEMODE_MASK (0x30U)
31892#define DDRPHY_DX7GCR3_DSTEMODE_SHIFT (4U)
31893/*! DSTEMODE - Enables the TE mode values for DQS.
31894 */
31895#define DDRPHY_DX7GCR3_DSTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX7GCR3_DSTEMODE_MASK)
31896#define DDRPHY_DX7GCR3_DSOEMODE_MASK (0xC0U)
31897#define DDRPHY_DX7GCR3_DSOEMODE_SHIFT (6U)
31898/*! DSOEMODE - Enables the OE mode values for DQS.
31899 */
31900#define DDRPHY_DX7GCR3_DSOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX7GCR3_DSOEMODE_MASK)
31901#define DDRPHY_DX7GCR3_WDSBVT_MASK (0x100U)
31902#define DDRPHY_DX7GCR3_WDSBVT_SHIFT (8U)
31903/*! WDSBVT - Write Data Strobe BDL VT Compensation
31904 */
31905#define DDRPHY_DX7GCR3_WDSBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_WDSBVT_SHIFT)) & DDRPHY_DX7GCR3_WDSBVT_MASK)
31906#define DDRPHY_DX7GCR3_RESERVED_9_MASK (0x200U)
31907#define DDRPHY_DX7GCR3_RESERVED_9_SHIFT (9U)
31908/*! RESERVED_9 - Reserved. Returns zeroes on reads.
31909 */
31910#define DDRPHY_DX7GCR3_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX7GCR3_RESERVED_9_MASK)
31911#define DDRPHY_DX7GCR3_DMPDRMODE_MASK (0xC00U)
31912#define DDRPHY_DX7GCR3_DMPDRMODE_SHIFT (10U)
31913/*! DMPDRMODE - Enables the PDR mode values for DM.
31914 */
31915#define DDRPHY_DX7GCR3_DMPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX7GCR3_DMPDRMODE_MASK)
31916#define DDRPHY_DX7GCR3_DMTEMODE_MASK (0x3000U)
31917#define DDRPHY_DX7GCR3_DMTEMODE_SHIFT (12U)
31918/*! DMTEMODE - Enables the TE mode values for DM.
31919 */
31920#define DDRPHY_DX7GCR3_DMTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX7GCR3_DMTEMODE_MASK)
31921#define DDRPHY_DX7GCR3_DMOEMODE_MASK (0xC000U)
31922#define DDRPHY_DX7GCR3_DMOEMODE_SHIFT (14U)
31923/*! DMOEMODE - Enables the OE mode values for DM.
31924 */
31925#define DDRPHY_DX7GCR3_DMOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX7GCR3_DMOEMODE_MASK)
31926#define DDRPHY_DX7GCR3_DSNPDRMODE_MASK (0x30000U)
31927#define DDRPHY_DX7GCR3_DSNPDRMODE_SHIFT (16U)
31928/*! DSNPDRMODE - Enables the PDR mode for DQS
31929 */
31930#define DDRPHY_DX7GCR3_DSNPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX7GCR3_DSNPDRMODE_MASK)
31931#define DDRPHY_DX7GCR3_DSNTEMODE_MASK (0xC0000U)
31932#define DDRPHY_DX7GCR3_DSNTEMODE_SHIFT (18U)
31933/*! DSNTEMODE - Enables the TE mode for DQS
31934 */
31935#define DDRPHY_DX7GCR3_DSNTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX7GCR3_DSNTEMODE_MASK)
31936#define DDRPHY_DX7GCR3_DSNOEMODE_MASK (0x300000U)
31937#define DDRPHY_DX7GCR3_DSNOEMODE_SHIFT (20U)
31938/*! DSNOEMODE - Enables the OE mode for DQs
31939 */
31940#define DDRPHY_DX7GCR3_DSNOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX7GCR3_DSNOEMODE_MASK)
31941#define DDRPHY_DX7GCR3_PDRBVT_MASK (0x400000U)
31942#define DDRPHY_DX7GCR3_PDRBVT_SHIFT (22U)
31943/*! PDRBVT - Power Down Receiver BDL VT Compensation
31944 */
31945#define DDRPHY_DX7GCR3_PDRBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_PDRBVT_SHIFT)) & DDRPHY_DX7GCR3_PDRBVT_MASK)
31946#define DDRPHY_DX7GCR3_RGSLVT_MASK (0x800000U)
31947#define DDRPHY_DX7GCR3_RGSLVT_SHIFT (23U)
31948/*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation
31949 */
31950#define DDRPHY_DX7GCR3_RGSLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_RGSLVT_SHIFT)) & DDRPHY_DX7GCR3_RGSLVT_MASK)
31951#define DDRPHY_DX7GCR3_WLLVT_MASK (0x1000000U)
31952#define DDRPHY_DX7GCR3_WLLVT_SHIFT (24U)
31953/*! WLLVT - Write Leveling LCDL Delay VT Compensation
31954 */
31955#define DDRPHY_DX7GCR3_WLLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_WLLVT_SHIFT)) & DDRPHY_DX7GCR3_WLLVT_MASK)
31956#define DDRPHY_DX7GCR3_WDLVT_MASK (0x2000000U)
31957#define DDRPHY_DX7GCR3_WDLVT_SHIFT (25U)
31958/*! WDLVT - Write DQ LCDL Delay VT Compensation
31959 */
31960#define DDRPHY_DX7GCR3_WDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_WDLVT_SHIFT)) & DDRPHY_DX7GCR3_WDLVT_MASK)
31961#define DDRPHY_DX7GCR3_RDLVT_MASK (0x4000000U)
31962#define DDRPHY_DX7GCR3_RDLVT_SHIFT (26U)
31963/*! RDLVT - Read DQS LCDL Delay VT Compensation
31964 */
31965#define DDRPHY_DX7GCR3_RDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_RDLVT_SHIFT)) & DDRPHY_DX7GCR3_RDLVT_MASK)
31966#define DDRPHY_DX7GCR3_RGLVT_MASK (0x8000000U)
31967#define DDRPHY_DX7GCR3_RGLVT_SHIFT (27U)
31968/*! RGLVT - Read DQS Gating LCDL Delay VT Compensation
31969 */
31970#define DDRPHY_DX7GCR3_RGLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_RGLVT_SHIFT)) & DDRPHY_DX7GCR3_RGLVT_MASK)
31971#define DDRPHY_DX7GCR3_WDBVT_MASK (0x10000000U)
31972#define DDRPHY_DX7GCR3_WDBVT_SHIFT (28U)
31973/*! WDBVT - Write Data BDL VT Compensation
31974 */
31975#define DDRPHY_DX7GCR3_WDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_WDBVT_SHIFT)) & DDRPHY_DX7GCR3_WDBVT_MASK)
31976#define DDRPHY_DX7GCR3_RDBVT_MASK (0x20000000U)
31977#define DDRPHY_DX7GCR3_RDBVT_SHIFT (29U)
31978/*! RDBVT - Read Data BDL VT Compensation
31979 */
31980#define DDRPHY_DX7GCR3_RDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_RDBVT_SHIFT)) & DDRPHY_DX7GCR3_RDBVT_MASK)
31981#define DDRPHY_DX7GCR3_TEBVT_MASK (0x40000000U)
31982#define DDRPHY_DX7GCR3_TEBVT_SHIFT (30U)
31983/*! TEBVT - Termination Enable BDL VT Compensation
31984 */
31985#define DDRPHY_DX7GCR3_TEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_TEBVT_SHIFT)) & DDRPHY_DX7GCR3_TEBVT_MASK)
31986#define DDRPHY_DX7GCR3_OEBVT_MASK (0x80000000U)
31987#define DDRPHY_DX7GCR3_OEBVT_SHIFT (31U)
31988/*! OEBVT - Output Enable BDL VT Compensation
31989 */
31990#define DDRPHY_DX7GCR3_OEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR3_OEBVT_SHIFT)) & DDRPHY_DX7GCR3_OEBVT_MASK)
31991/*! @} */
31992
31993/*! @name DX7GCR4 - DATX8 n General Configuration Register 4 */
31994/*! @{ */
31995#define DDRPHY_DX7GCR4_DXREFIMON_MASK (0x3U)
31996#define DDRPHY_DX7GCR4_DXREFIMON_SHIFT (0U)
31997/*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane.
31998 */
31999#define DDRPHY_DX7GCR4_DXREFIMON(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX7GCR4_DXREFIMON_MASK)
32000#define DDRPHY_DX7GCR4_DXREFIEN_MASK (0x3CU)
32001#define DDRPHY_DX7GCR4_DXREFIEN_SHIFT (2U)
32002/*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
32003 */
32004#define DDRPHY_DX7GCR4_DXREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX7GCR4_DXREFIEN_MASK)
32005#define DDRPHY_DX7GCR4_RESERVED_7_6_MASK (0xC0U)
32006#define DDRPHY_DX7GCR4_RESERVED_7_6_SHIFT (6U)
32007/*! RESERVED_7_6 - Reserved. Returns zeros on reads.
32008 */
32009#define DDRPHY_DX7GCR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX7GCR4_RESERVED_7_6_MASK)
32010#define DDRPHY_DX7GCR4_DXREFSSEL_MASK (0x7F00U)
32011#define DDRPHY_DX7GCR4_DXREFSSEL_SHIFT (8U)
32012/*! DXREFSSEL - Byte Lane Single-End VREF Select
32013 */
32014#define DDRPHY_DX7GCR4_DXREFSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX7GCR4_DXREFSSEL_MASK)
32015#define DDRPHY_DX7GCR4_DXREFSSELRANGE_MASK (0x8000U)
32016#define DDRPHY_DX7GCR4_DXREFSSELRANGE_SHIFT (15U)
32017/*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select
32018 */
32019#define DDRPHY_DX7GCR4_DXREFSSELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX7GCR4_DXREFSSELRANGE_MASK)
32020#define DDRPHY_DX7GCR4_DXREFESEL_MASK (0x7F0000U)
32021#define DDRPHY_DX7GCR4_DXREFESEL_SHIFT (16U)
32022/*! DXREFESEL - Byte Lane External VREF Select
32023 */
32024#define DDRPHY_DX7GCR4_DXREFESEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX7GCR4_DXREFESEL_MASK)
32025#define DDRPHY_DX7GCR4_DXREFESELRANGE_MASK (0x800000U)
32026#define DDRPHY_DX7GCR4_DXREFESELRANGE_SHIFT (23U)
32027/*! DXREFESELRANGE - External VREF generator REFSEL range select
32028 */
32029#define DDRPHY_DX7GCR4_DXREFESELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX7GCR4_DXREFESELRANGE_MASK)
32030#define DDRPHY_DX7GCR4_RESERVED_24_MASK (0x1000000U)
32031#define DDRPHY_DX7GCR4_RESERVED_24_SHIFT (24U)
32032/*! RESERVED_24 - Reserved. Returns zeros on reads.
32033 */
32034#define DDRPHY_DX7GCR4_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX7GCR4_RESERVED_24_MASK)
32035#define DDRPHY_DX7GCR4_DXREFSEN_MASK (0x2000000U)
32036#define DDRPHY_DX7GCR4_DXREFSEN_SHIFT (25U)
32037/*! DXREFSEN - Byte Lane Single-End VREF Enable
32038 */
32039#define DDRPHY_DX7GCR4_DXREFSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX7GCR4_DXREFSEN_MASK)
32040#define DDRPHY_DX7GCR4_DXREFEEN_MASK (0xC000000U)
32041#define DDRPHY_DX7GCR4_DXREFEEN_SHIFT (26U)
32042/*! DXREFEEN - Byte Lane Internal VREF Enable
32043 */
32044#define DDRPHY_DX7GCR4_DXREFEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX7GCR4_DXREFEEN_MASK)
32045#define DDRPHY_DX7GCR4_DXREFPEN_MASK (0x10000000U)
32046#define DDRPHY_DX7GCR4_DXREFPEN_SHIFT (28U)
32047/*! DXREFPEN - Byte Lane VREF Pad Enable
32048 */
32049#define DDRPHY_DX7GCR4_DXREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX7GCR4_DXREFPEN_MASK)
32050#define DDRPHY_DX7GCR4_RESERVED_31_29_MASK (0xE0000000U)
32051#define DDRPHY_DX7GCR4_RESERVED_31_29_SHIFT (29U)
32052/*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs)
32053 */
32054#define DDRPHY_DX7GCR4_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX7GCR4_RESERVED_31_29_MASK)
32055/*! @} */
32056
32057/*! @name DX7GCR5 - DATX8 n General Configuration Register 5 */
32058/*! @{ */
32059#define DDRPHY_DX7GCR5_DXREFISELR0_MASK (0x7FU)
32060#define DDRPHY_DX7GCR5_DXREFISELR0_SHIFT (0U)
32061/*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0
32062 */
32063#define DDRPHY_DX7GCR5_DXREFISELR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX7GCR5_DXREFISELR0_MASK)
32064#define DDRPHY_DX7GCR5_RESERVED_7_MASK (0x80U)
32065#define DDRPHY_DX7GCR5_RESERVED_7_SHIFT (7U)
32066/*! RESERVED_7 - Reserved. Returns zeros on reads.
32067 */
32068#define DDRPHY_DX7GCR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX7GCR5_RESERVED_7_MASK)
32069#define DDRPHY_DX7GCR5_DXREFISELR1_MASK (0x7F00U)
32070#define DDRPHY_DX7GCR5_DXREFISELR1_SHIFT (8U)
32071/*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1
32072 */
32073#define DDRPHY_DX7GCR5_DXREFISELR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX7GCR5_DXREFISELR1_MASK)
32074#define DDRPHY_DX7GCR5_RESERVED_15_MASK (0x8000U)
32075#define DDRPHY_DX7GCR5_RESERVED_15_SHIFT (15U)
32076/*! RESERVED_15 - Reserved. Returns zeros on reads.
32077 */
32078#define DDRPHY_DX7GCR5_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX7GCR5_RESERVED_15_MASK)
32079#define DDRPHY_DX7GCR5_DXREFISELR2_MASK (0x7F0000U)
32080#define DDRPHY_DX7GCR5_DXREFISELR2_SHIFT (16U)
32081/*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2
32082 */
32083#define DDRPHY_DX7GCR5_DXREFISELR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX7GCR5_DXREFISELR2_MASK)
32084#define DDRPHY_DX7GCR5_RESERVED_23_MASK (0x800000U)
32085#define DDRPHY_DX7GCR5_RESERVED_23_SHIFT (23U)
32086/*! RESERVED_23 - Reserved. Returns zeros on reads.
32087 */
32088#define DDRPHY_DX7GCR5_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX7GCR5_RESERVED_23_MASK)
32089#define DDRPHY_DX7GCR5_DXREFISELR3_MASK (0x7F000000U)
32090#define DDRPHY_DX7GCR5_DXREFISELR3_SHIFT (24U)
32091/*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3
32092 */
32093#define DDRPHY_DX7GCR5_DXREFISELR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX7GCR5_DXREFISELR3_MASK)
32094#define DDRPHY_DX7GCR5_RESERVED_31_MASK (0x80000000U)
32095#define DDRPHY_DX7GCR5_RESERVED_31_SHIFT (31U)
32096/*! RESERVED_31 - Reserved. Returns zeros on reads.
32097 */
32098#define DDRPHY_DX7GCR5_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX7GCR5_RESERVED_31_MASK)
32099/*! @} */
32100
32101/*! @name DX7GCR6 - DATX8 n General Configuration Register 6 */
32102/*! @{ */
32103#define DDRPHY_DX7GCR6_DXDQVREFR0_MASK (0x3FU)
32104#define DDRPHY_DX7GCR6_DXDQVREFR0_SHIFT (0U)
32105/*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0
32106 */
32107#define DDRPHY_DX7GCR6_DXDQVREFR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX7GCR6_DXDQVREFR0_MASK)
32108#define DDRPHY_DX7GCR6_RESERVED_7_6_MASK (0xC0U)
32109#define DDRPHY_DX7GCR6_RESERVED_7_6_SHIFT (6U)
32110/*! RESERVED_7_6 - Reserved. Returns zeros on reads.
32111 */
32112#define DDRPHY_DX7GCR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX7GCR6_RESERVED_7_6_MASK)
32113#define DDRPHY_DX7GCR6_DXDQVREFR1_MASK (0x3F00U)
32114#define DDRPHY_DX7GCR6_DXDQVREFR1_SHIFT (8U)
32115/*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1
32116 */
32117#define DDRPHY_DX7GCR6_DXDQVREFR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX7GCR6_DXDQVREFR1_MASK)
32118#define DDRPHY_DX7GCR6_RESERVED_15_14_MASK (0xC000U)
32119#define DDRPHY_DX7GCR6_RESERVED_15_14_SHIFT (14U)
32120/*! RESERVED_15_14 - Reserved. Returns zeros on reads.
32121 */
32122#define DDRPHY_DX7GCR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX7GCR6_RESERVED_15_14_MASK)
32123#define DDRPHY_DX7GCR6_DXDQVREFR2_MASK (0x3F0000U)
32124#define DDRPHY_DX7GCR6_DXDQVREFR2_SHIFT (16U)
32125/*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2
32126 */
32127#define DDRPHY_DX7GCR6_DXDQVREFR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX7GCR6_DXDQVREFR2_MASK)
32128#define DDRPHY_DX7GCR6_RESERVED_23_22_MASK (0xC00000U)
32129#define DDRPHY_DX7GCR6_RESERVED_23_22_SHIFT (22U)
32130/*! RESERVED_23_22 - Reserved. Returns zeros on reads.
32131 */
32132#define DDRPHY_DX7GCR6_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX7GCR6_RESERVED_23_22_MASK)
32133#define DDRPHY_DX7GCR6_DXDQVREFR3_MASK (0x3F000000U)
32134#define DDRPHY_DX7GCR6_DXDQVREFR3_SHIFT (24U)
32135/*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3
32136 */
32137#define DDRPHY_DX7GCR6_DXDQVREFR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX7GCR6_DXDQVREFR3_MASK)
32138#define DDRPHY_DX7GCR6_RESERVED_31_30_MASK (0xC0000000U)
32139#define DDRPHY_DX7GCR6_RESERVED_31_30_SHIFT (30U)
32140/*! RESERVED_31_30 - Reserved. Returns zeros on reads.
32141 */
32142#define DDRPHY_DX7GCR6_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX7GCR6_RESERVED_31_30_MASK)
32143/*! @} */
32144
32145/*! @name DX7GCR7 - DATX8 n General Configuration Register 7 */
32146/*! @{ */
32147#define DDRPHY_DX7GCR7_DCALSVAL_MASK (0x1FFU)
32148#define DDRPHY_DX7GCR7_DCALSVAL_SHIFT (0U)
32149/*! DCALSVAL - DDL Calibration Starting Value
32150 */
32151#define DDRPHY_DX7GCR7_DCALSVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX7GCR7_DCALSVAL_MASK)
32152#define DDRPHY_DX7GCR7_DCALTYPE_MASK (0x200U)
32153#define DDRPHY_DX7GCR7_DCALTYPE_SHIFT (9U)
32154/*! DCALTYPE - DDL Calibration Type
32155 */
32156#define DDRPHY_DX7GCR7_DCALTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX7GCR7_DCALTYPE_MASK)
32157#define DDRPHY_DX7GCR7_RESERVED_17_10_MASK (0x3FC00U)
32158#define DDRPHY_DX7GCR7_RESERVED_17_10_SHIFT (10U)
32159/*! RESERVED_17_10 - Reserved. Caution, do not write to this register field.
32160 */
32161#define DDRPHY_DX7GCR7_RESERVED_17_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX7GCR7_RESERVED_17_10_MASK)
32162#define DDRPHY_DX7GCR7_RESERVED_18_MASK (0x40000U)
32163#define DDRPHY_DX7GCR7_RESERVED_18_SHIFT (18U)
32164/*! RESERVED_18 - Reserved. Caution, do not write to this register field.
32165 */
32166#define DDRPHY_DX7GCR7_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX7GCR7_RESERVED_18_MASK)
32167#define DDRPHY_DX7GCR7_RESERVED_31_19_MASK (0xFFF80000U)
32168#define DDRPHY_DX7GCR7_RESERVED_31_19_SHIFT (19U)
32169/*! RESERVED_31_19 - Reserved. Caution, do not write to this register field.
32170 */
32171#define DDRPHY_DX7GCR7_RESERVED_31_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX7GCR7_RESERVED_31_19_MASK)
32172/*! @} */
32173
32174/*! @name DX7GCR8 - DATX8 n General Configuration Register 8 */
32175/*! @{ */
32176#define DDRPHY_DX7GCR8_RESERVED_5_0_MASK (0x3FU)
32177#define DDRPHY_DX7GCR8_RESERVED_5_0_SHIFT (0U)
32178/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
32179 */
32180#define DDRPHY_DX7GCR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_5_0_MASK)
32181#define DDRPHY_DX7GCR8_RESERVED_7_6_MASK (0xC0U)
32182#define DDRPHY_DX7GCR8_RESERVED_7_6_SHIFT (6U)
32183/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
32184 */
32185#define DDRPHY_DX7GCR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_7_6_MASK)
32186#define DDRPHY_DX7GCR8_RESERVED_13_8_MASK (0x3F00U)
32187#define DDRPHY_DX7GCR8_RESERVED_13_8_SHIFT (8U)
32188/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
32189 */
32190#define DDRPHY_DX7GCR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_13_8_MASK)
32191#define DDRPHY_DX7GCR8_RESERVED_15_14_MASK (0xC000U)
32192#define DDRPHY_DX7GCR8_RESERVED_15_14_SHIFT (14U)
32193/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32194 */
32195#define DDRPHY_DX7GCR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_15_14_MASK)
32196#define DDRPHY_DX7GCR8_RESERVED_21_16_MASK (0x3F0000U)
32197#define DDRPHY_DX7GCR8_RESERVED_21_16_SHIFT (16U)
32198/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
32199 */
32200#define DDRPHY_DX7GCR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_21_16_MASK)
32201#define DDRPHY_DX7GCR8_RESERVED_23_22_MASK (0xC00000U)
32202#define DDRPHY_DX7GCR8_RESERVED_23_22_SHIFT (22U)
32203/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
32204 */
32205#define DDRPHY_DX7GCR8_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_23_22_MASK)
32206#define DDRPHY_DX7GCR8_RESERVED_29_24_MASK (0x3F000000U)
32207#define DDRPHY_DX7GCR8_RESERVED_29_24_SHIFT (24U)
32208/*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
32209 */
32210#define DDRPHY_DX7GCR8_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_29_24_MASK)
32211#define DDRPHY_DX7GCR8_RESERVED_31_30_MASK (0xC0000000U)
32212#define DDRPHY_DX7GCR8_RESERVED_31_30_SHIFT (30U)
32213/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
32214 */
32215#define DDRPHY_DX7GCR8_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX7GCR8_RESERVED_31_30_MASK)
32216/*! @} */
32217
32218/*! @name DX7GCR9 - DATX8 n General Configuration Register 9 */
32219/*! @{ */
32220#define DDRPHY_DX7GCR9_RESERVED_5_0_MASK (0x3FU)
32221#define DDRPHY_DX7GCR9_RESERVED_5_0_SHIFT (0U)
32222/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
32223 */
32224#define DDRPHY_DX7GCR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_5_0_MASK)
32225#define DDRPHY_DX7GCR9_RESERVED_7_6_MASK (0xC0U)
32226#define DDRPHY_DX7GCR9_RESERVED_7_6_SHIFT (6U)
32227/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
32228 */
32229#define DDRPHY_DX7GCR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_7_6_MASK)
32230#define DDRPHY_DX7GCR9_RESERVED_13_8_MASK (0x3F00U)
32231#define DDRPHY_DX7GCR9_RESERVED_13_8_SHIFT (8U)
32232/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
32233 */
32234#define DDRPHY_DX7GCR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_13_8_MASK)
32235#define DDRPHY_DX7GCR9_RESERVED_15_14_MASK (0xC000U)
32236#define DDRPHY_DX7GCR9_RESERVED_15_14_SHIFT (14U)
32237/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32238 */
32239#define DDRPHY_DX7GCR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_15_14_MASK)
32240#define DDRPHY_DX7GCR9_RESERVED_21_16_MASK (0x3F0000U)
32241#define DDRPHY_DX7GCR9_RESERVED_21_16_SHIFT (16U)
32242/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
32243 */
32244#define DDRPHY_DX7GCR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_21_16_MASK)
32245#define DDRPHY_DX7GCR9_RESERVED_23_22_MASK (0xC00000U)
32246#define DDRPHY_DX7GCR9_RESERVED_23_22_SHIFT (22U)
32247/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
32248 */
32249#define DDRPHY_DX7GCR9_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_23_22_MASK)
32250#define DDRPHY_DX7GCR9_RESERVED_29_24_MASK (0x3F000000U)
32251#define DDRPHY_DX7GCR9_RESERVED_29_24_SHIFT (24U)
32252/*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
32253 */
32254#define DDRPHY_DX7GCR9_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_29_24_MASK)
32255#define DDRPHY_DX7GCR9_RESERVED_31_30_MASK (0xC0000000U)
32256#define DDRPHY_DX7GCR9_RESERVED_31_30_SHIFT (30U)
32257/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
32258 */
32259#define DDRPHY_DX7GCR9_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX7GCR9_RESERVED_31_30_MASK)
32260/*! @} */
32261
32262/*! @name DX7DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */
32263/*! @{ */
32264#define DDRPHY_DX7DQMAP0_DQ0MAP_MASK (0xFU)
32265#define DDRPHY_DX7DQMAP0_DQ0MAP_SHIFT (0U)
32266/*! DQ0MAP - DQ bit 0 DATX8 slice mapping index
32267 */
32268#define DDRPHY_DX7DQMAP0_DQ0MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX7DQMAP0_DQ0MAP_MASK)
32269#define DDRPHY_DX7DQMAP0_DQ1MAP_MASK (0xF0U)
32270#define DDRPHY_DX7DQMAP0_DQ1MAP_SHIFT (4U)
32271/*! DQ1MAP - DQ bit 1 DATX8 slice mapping index
32272 */
32273#define DDRPHY_DX7DQMAP0_DQ1MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX7DQMAP0_DQ1MAP_MASK)
32274#define DDRPHY_DX7DQMAP0_DQ2MAP_MASK (0xF00U)
32275#define DDRPHY_DX7DQMAP0_DQ2MAP_SHIFT (8U)
32276/*! DQ2MAP - DQ bit 2 DATX8 slice mapping index
32277 */
32278#define DDRPHY_DX7DQMAP0_DQ2MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX7DQMAP0_DQ2MAP_MASK)
32279#define DDRPHY_DX7DQMAP0_DQ3MAP_MASK (0xF000U)
32280#define DDRPHY_DX7DQMAP0_DQ3MAP_SHIFT (12U)
32281/*! DQ3MAP - DQ bit 3 DATX8 slice mapping index
32282 */
32283#define DDRPHY_DX7DQMAP0_DQ3MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX7DQMAP0_DQ3MAP_MASK)
32284#define DDRPHY_DX7DQMAP0_DQ4MAP_MASK (0xF0000U)
32285#define DDRPHY_DX7DQMAP0_DQ4MAP_SHIFT (16U)
32286/*! DQ4MAP - DQ bit 4 DATX8 slice mapping index
32287 */
32288#define DDRPHY_DX7DQMAP0_DQ4MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX7DQMAP0_DQ4MAP_MASK)
32289#define DDRPHY_DX7DQMAP0_RESERVED_30_20_MASK (0x7FF00000U)
32290#define DDRPHY_DX7DQMAP0_RESERVED_30_20_SHIFT (20U)
32291/*! RESERVED_30_20 - Reserved. Return zeroes on reads.
32292 */
32293#define DDRPHY_DX7DQMAP0_RESERVED_30_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX7DQMAP0_RESERVED_30_20_MASK)
32294#define DDRPHY_DX7DQMAP0_MAPOK_MASK (0x80000000U)
32295#define DDRPHY_DX7DQMAP0_MAPOK_SHIFT (31U)
32296/*! MAPOK - Checksum bit
32297 */
32298#define DDRPHY_DX7DQMAP0_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX7DQMAP0_MAPOK_MASK)
32299/*! @} */
32300
32301/*! @name DX7DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */
32302/*! @{ */
32303#define DDRPHY_DX7DQMAP1_DQ5MAP_MASK (0xFU)
32304#define DDRPHY_DX7DQMAP1_DQ5MAP_SHIFT (0U)
32305/*! DQ5MAP - DQ bit 5 DATX8 slice mapping index
32306 */
32307#define DDRPHY_DX7DQMAP1_DQ5MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX7DQMAP1_DQ5MAP_MASK)
32308#define DDRPHY_DX7DQMAP1_DQ6MAP_MASK (0xF0U)
32309#define DDRPHY_DX7DQMAP1_DQ6MAP_SHIFT (4U)
32310/*! DQ6MAP - DQ bit 6 DATX8 slice mapping index
32311 */
32312#define DDRPHY_DX7DQMAP1_DQ6MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX7DQMAP1_DQ6MAP_MASK)
32313#define DDRPHY_DX7DQMAP1_DQ7MAP_MASK (0xF00U)
32314#define DDRPHY_DX7DQMAP1_DQ7MAP_SHIFT (8U)
32315/*! DQ7MAP - DQ bit 7 DATX8 slice mapping index
32316 */
32317#define DDRPHY_DX7DQMAP1_DQ7MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX7DQMAP1_DQ7MAP_MASK)
32318#define DDRPHY_DX7DQMAP1_DMMAP_MASK (0xF000U)
32319#define DDRPHY_DX7DQMAP1_DMMAP_SHIFT (12U)
32320/*! DMMAP - DM bit DATX8 slice mapping index
32321 */
32322#define DDRPHY_DX7DQMAP1_DMMAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX7DQMAP1_DMMAP_MASK)
32323#define DDRPHY_DX7DQMAP1_RESERVED_30_16_MASK (0x7FFF0000U)
32324#define DDRPHY_DX7DQMAP1_RESERVED_30_16_SHIFT (16U)
32325/*! RESERVED_30_16 - Reserved. Return zeroes on reads.
32326 */
32327#define DDRPHY_DX7DQMAP1_RESERVED_30_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX7DQMAP1_RESERVED_30_16_MASK)
32328#define DDRPHY_DX7DQMAP1_MAPOK_MASK (0x80000000U)
32329#define DDRPHY_DX7DQMAP1_MAPOK_SHIFT (31U)
32330/*! MAPOK - Checksum bit
32331 */
32332#define DDRPHY_DX7DQMAP1_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX7DQMAP1_MAPOK_MASK)
32333/*! @} */
32334
32335/*! @name DX7BDLR0 - DATX8 n Bit Delay Line Register 0 */
32336/*! @{ */
32337#define DDRPHY_DX7BDLR0_DQ0WBD_MASK (0x3FU)
32338#define DDRPHY_DX7BDLR0_DQ0WBD_SHIFT (0U)
32339/*! DQ0WBD - DQ0 Write Bit Delay
32340 */
32341#define DDRPHY_DX7BDLR0_DQ0WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX7BDLR0_DQ0WBD_MASK)
32342#define DDRPHY_DX7BDLR0_RESERVED_7_6_MASK (0xC0U)
32343#define DDRPHY_DX7BDLR0_RESERVED_7_6_SHIFT (6U)
32344/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
32345 */
32346#define DDRPHY_DX7BDLR0_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR0_RESERVED_7_6_MASK)
32347#define DDRPHY_DX7BDLR0_DQ1WBD_MASK (0x3F00U)
32348#define DDRPHY_DX7BDLR0_DQ1WBD_SHIFT (8U)
32349/*! DQ1WBD - DQ1 Write Bit Delay
32350 */
32351#define DDRPHY_DX7BDLR0_DQ1WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX7BDLR0_DQ1WBD_MASK)
32352#define DDRPHY_DX7BDLR0_RESERVED_15_14_MASK (0xC000U)
32353#define DDRPHY_DX7BDLR0_RESERVED_15_14_SHIFT (14U)
32354/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32355 */
32356#define DDRPHY_DX7BDLR0_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR0_RESERVED_15_14_MASK)
32357#define DDRPHY_DX7BDLR0_DQ2WBD_MASK (0x3F0000U)
32358#define DDRPHY_DX7BDLR0_DQ2WBD_SHIFT (16U)
32359/*! DQ2WBD - DQ2 Write Bit Delay
32360 */
32361#define DDRPHY_DX7BDLR0_DQ2WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX7BDLR0_DQ2WBD_MASK)
32362#define DDRPHY_DX7BDLR0_RESERVED_23_22_MASK (0xC00000U)
32363#define DDRPHY_DX7BDLR0_RESERVED_23_22_SHIFT (22U)
32364/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
32365 */
32366#define DDRPHY_DX7BDLR0_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX7BDLR0_RESERVED_23_22_MASK)
32367#define DDRPHY_DX7BDLR0_DQ3WBD_MASK (0x3F000000U)
32368#define DDRPHY_DX7BDLR0_DQ3WBD_SHIFT (24U)
32369/*! DQ3WBD - DQ3 Write Bit Delay
32370 */
32371#define DDRPHY_DX7BDLR0_DQ3WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX7BDLR0_DQ3WBD_MASK)
32372#define DDRPHY_DX7BDLR0_RESERVED_31_30_MASK (0xC0000000U)
32373#define DDRPHY_DX7BDLR0_RESERVED_31_30_SHIFT (30U)
32374/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
32375 */
32376#define DDRPHY_DX7BDLR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX7BDLR0_RESERVED_31_30_MASK)
32377/*! @} */
32378
32379/*! @name DX7BDLR1 - DATX8 n Bit Delay Line Register 1 */
32380/*! @{ */
32381#define DDRPHY_DX7BDLR1_DQ4WBD_MASK (0x3FU)
32382#define DDRPHY_DX7BDLR1_DQ4WBD_SHIFT (0U)
32383/*! DQ4WBD - DQ4 Write Bit Delay
32384 */
32385#define DDRPHY_DX7BDLR1_DQ4WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX7BDLR1_DQ4WBD_MASK)
32386#define DDRPHY_DX7BDLR1_RESERVED_7_6_MASK (0xC0U)
32387#define DDRPHY_DX7BDLR1_RESERVED_7_6_SHIFT (6U)
32388/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
32389 */
32390#define DDRPHY_DX7BDLR1_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR1_RESERVED_7_6_MASK)
32391#define DDRPHY_DX7BDLR1_DQ5WBD_MASK (0x3F00U)
32392#define DDRPHY_DX7BDLR1_DQ5WBD_SHIFT (8U)
32393/*! DQ5WBD - DQ5 Write Bit Delay
32394 */
32395#define DDRPHY_DX7BDLR1_DQ5WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX7BDLR1_DQ5WBD_MASK)
32396#define DDRPHY_DX7BDLR1_RESERVED_15_14_MASK (0xC000U)
32397#define DDRPHY_DX7BDLR1_RESERVED_15_14_SHIFT (14U)
32398/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32399 */
32400#define DDRPHY_DX7BDLR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR1_RESERVED_15_14_MASK)
32401#define DDRPHY_DX7BDLR1_DQ6WBD_MASK (0x3F0000U)
32402#define DDRPHY_DX7BDLR1_DQ6WBD_SHIFT (16U)
32403/*! DQ6WBD - DQ6 Write Bit Delay
32404 */
32405#define DDRPHY_DX7BDLR1_DQ6WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX7BDLR1_DQ6WBD_MASK)
32406#define DDRPHY_DX7BDLR1_RESERVED_23_22_MASK (0xC00000U)
32407#define DDRPHY_DX7BDLR1_RESERVED_23_22_SHIFT (22U)
32408/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
32409 */
32410#define DDRPHY_DX7BDLR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX7BDLR1_RESERVED_23_22_MASK)
32411#define DDRPHY_DX7BDLR1_DQ7WBD_MASK (0x3F000000U)
32412#define DDRPHY_DX7BDLR1_DQ7WBD_SHIFT (24U)
32413/*! DQ7WBD - DQ7 Write Bit Delay
32414 */
32415#define DDRPHY_DX7BDLR1_DQ7WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX7BDLR1_DQ7WBD_MASK)
32416#define DDRPHY_DX7BDLR1_RESERVED_31_30_MASK (0xC0000000U)
32417#define DDRPHY_DX7BDLR1_RESERVED_31_30_SHIFT (30U)
32418/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
32419 */
32420#define DDRPHY_DX7BDLR1_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX7BDLR1_RESERVED_31_30_MASK)
32421/*! @} */
32422
32423/*! @name DX7BDLR2 - DATX8 n Bit Delay Line Register 2 */
32424/*! @{ */
32425#define DDRPHY_DX7BDLR2_DMWBD_MASK (0x3FU)
32426#define DDRPHY_DX7BDLR2_DMWBD_SHIFT (0U)
32427/*! DMWBD - DM Write Bit Delay
32428 */
32429#define DDRPHY_DX7BDLR2_DMWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_DMWBD_SHIFT)) & DDRPHY_DX7BDLR2_DMWBD_MASK)
32430#define DDRPHY_DX7BDLR2_RESERVED_7_6_MASK (0xC0U)
32431#define DDRPHY_DX7BDLR2_RESERVED_7_6_SHIFT (6U)
32432/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
32433 */
32434#define DDRPHY_DX7BDLR2_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR2_RESERVED_7_6_MASK)
32435#define DDRPHY_DX7BDLR2_DSWBD_MASK (0x3F00U)
32436#define DDRPHY_DX7BDLR2_DSWBD_SHIFT (8U)
32437/*! DSWBD - DQS Write Bit Delay
32438 */
32439#define DDRPHY_DX7BDLR2_DSWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_DSWBD_SHIFT)) & DDRPHY_DX7BDLR2_DSWBD_MASK)
32440#define DDRPHY_DX7BDLR2_RESERVED_15_14_MASK (0xC000U)
32441#define DDRPHY_DX7BDLR2_RESERVED_15_14_SHIFT (14U)
32442/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32443 */
32444#define DDRPHY_DX7BDLR2_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR2_RESERVED_15_14_MASK)
32445#define DDRPHY_DX7BDLR2_DSOEBD_MASK (0x3F0000U)
32446#define DDRPHY_DX7BDLR2_DSOEBD_SHIFT (16U)
32447/*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay
32448 */
32449#define DDRPHY_DX7BDLR2_DSOEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX7BDLR2_DSOEBD_MASK)
32450#define DDRPHY_DX7BDLR2_RESERVED_23_22_MASK (0xC00000U)
32451#define DDRPHY_DX7BDLR2_RESERVED_23_22_SHIFT (22U)
32452/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
32453 */
32454#define DDRPHY_DX7BDLR2_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX7BDLR2_RESERVED_23_22_MASK)
32455#define DDRPHY_DX7BDLR2_DSNWBD_MASK (0x3F000000U)
32456#define DDRPHY_DX7BDLR2_DSNWBD_SHIFT (24U)
32457/*! DSNWBD - DQSN Write Bit Delay
32458 */
32459#define DDRPHY_DX7BDLR2_DSNWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX7BDLR2_DSNWBD_MASK)
32460#define DDRPHY_DX7BDLR2_RESERVED_31_30_MASK (0xC0000000U)
32461#define DDRPHY_DX7BDLR2_RESERVED_31_30_SHIFT (30U)
32462/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
32463 */
32464#define DDRPHY_DX7BDLR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX7BDLR2_RESERVED_31_30_MASK)
32465/*! @} */
32466
32467/*! @name DX7BDLR3 - DATX8 n Bit Delay Line Register 3 */
32468/*! @{ */
32469#define DDRPHY_DX7BDLR3_DQ0RBD_MASK (0x3FU)
32470#define DDRPHY_DX7BDLR3_DQ0RBD_SHIFT (0U)
32471/*! DQ0RBD - DQ0 Read Bit Delay
32472 */
32473#define DDRPHY_DX7BDLR3_DQ0RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX7BDLR3_DQ0RBD_MASK)
32474#define DDRPHY_DX7BDLR3_RESERVED_7_6_MASK (0xC0U)
32475#define DDRPHY_DX7BDLR3_RESERVED_7_6_SHIFT (6U)
32476/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
32477 */
32478#define DDRPHY_DX7BDLR3_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR3_RESERVED_7_6_MASK)
32479#define DDRPHY_DX7BDLR3_DQ1RBD_MASK (0x3F00U)
32480#define DDRPHY_DX7BDLR3_DQ1RBD_SHIFT (8U)
32481/*! DQ1RBD - DQ1 Read Bit Delay
32482 */
32483#define DDRPHY_DX7BDLR3_DQ1RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX7BDLR3_DQ1RBD_MASK)
32484#define DDRPHY_DX7BDLR3_RESERVED_15_14_MASK (0xC000U)
32485#define DDRPHY_DX7BDLR3_RESERVED_15_14_SHIFT (14U)
32486/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32487 */
32488#define DDRPHY_DX7BDLR3_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR3_RESERVED_15_14_MASK)
32489#define DDRPHY_DX7BDLR3_DQ2RBD_MASK (0x3F0000U)
32490#define DDRPHY_DX7BDLR3_DQ2RBD_SHIFT (16U)
32491/*! DQ2RBD - DQ2 Read Bit Delay
32492 */
32493#define DDRPHY_DX7BDLR3_DQ2RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX7BDLR3_DQ2RBD_MASK)
32494#define DDRPHY_DX7BDLR3_RESERVED_23_22_MASK (0xC00000U)
32495#define DDRPHY_DX7BDLR3_RESERVED_23_22_SHIFT (22U)
32496/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
32497 */
32498#define DDRPHY_DX7BDLR3_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX7BDLR3_RESERVED_23_22_MASK)
32499#define DDRPHY_DX7BDLR3_DQ3RBD_MASK (0x3F000000U)
32500#define DDRPHY_DX7BDLR3_DQ3RBD_SHIFT (24U)
32501/*! DQ3RBD - DQ3 Read Bit Delay
32502 */
32503#define DDRPHY_DX7BDLR3_DQ3RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX7BDLR3_DQ3RBD_MASK)
32504#define DDRPHY_DX7BDLR3_RESERVED_31_30_MASK (0xC0000000U)
32505#define DDRPHY_DX7BDLR3_RESERVED_31_30_SHIFT (30U)
32506/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
32507 */
32508#define DDRPHY_DX7BDLR3_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX7BDLR3_RESERVED_31_30_MASK)
32509/*! @} */
32510
32511/*! @name DX7BDLR4 - DATX8 n Bit Delay Line Register 4 */
32512/*! @{ */
32513#define DDRPHY_DX7BDLR4_DQ4RBD_MASK (0x3FU)
32514#define DDRPHY_DX7BDLR4_DQ4RBD_SHIFT (0U)
32515/*! DQ4RBD - DQ4 Read Bit Delay
32516 */
32517#define DDRPHY_DX7BDLR4_DQ4RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX7BDLR4_DQ4RBD_MASK)
32518#define DDRPHY_DX7BDLR4_RESERVED_7_6_MASK (0xC0U)
32519#define DDRPHY_DX7BDLR4_RESERVED_7_6_SHIFT (6U)
32520/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
32521 */
32522#define DDRPHY_DX7BDLR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR4_RESERVED_7_6_MASK)
32523#define DDRPHY_DX7BDLR4_DQ5RBD_MASK (0x3F00U)
32524#define DDRPHY_DX7BDLR4_DQ5RBD_SHIFT (8U)
32525/*! DQ5RBD - DQ5 Read Bit Delay
32526 */
32527#define DDRPHY_DX7BDLR4_DQ5RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX7BDLR4_DQ5RBD_MASK)
32528#define DDRPHY_DX7BDLR4_RESERVED_15_14_MASK (0xC000U)
32529#define DDRPHY_DX7BDLR4_RESERVED_15_14_SHIFT (14U)
32530/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32531 */
32532#define DDRPHY_DX7BDLR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR4_RESERVED_15_14_MASK)
32533#define DDRPHY_DX7BDLR4_DQ6RBD_MASK (0x3F0000U)
32534#define DDRPHY_DX7BDLR4_DQ6RBD_SHIFT (16U)
32535/*! DQ6RBD - DQ6 Read Bit Delay
32536 */
32537#define DDRPHY_DX7BDLR4_DQ6RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX7BDLR4_DQ6RBD_MASK)
32538#define DDRPHY_DX7BDLR4_RESERVED_23_22_MASK (0xC00000U)
32539#define DDRPHY_DX7BDLR4_RESERVED_23_22_SHIFT (22U)
32540/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
32541 */
32542#define DDRPHY_DX7BDLR4_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX7BDLR4_RESERVED_23_22_MASK)
32543#define DDRPHY_DX7BDLR4_DQ7RBD_MASK (0x3F000000U)
32544#define DDRPHY_DX7BDLR4_DQ7RBD_SHIFT (24U)
32545/*! DQ7RBD - DQ7 Read Bit Delay
32546 */
32547#define DDRPHY_DX7BDLR4_DQ7RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX7BDLR4_DQ7RBD_MASK)
32548#define DDRPHY_DX7BDLR4_RESERVED_31_30_MASK (0xC0000000U)
32549#define DDRPHY_DX7BDLR4_RESERVED_31_30_SHIFT (30U)
32550/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
32551 */
32552#define DDRPHY_DX7BDLR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX7BDLR4_RESERVED_31_30_MASK)
32553/*! @} */
32554
32555/*! @name DX7BDLR5 - DATX8 n Bit Delay Line Register 5 */
32556/*! @{ */
32557#define DDRPHY_DX7BDLR5_DMRBD_MASK (0x3FU)
32558#define DDRPHY_DX7BDLR5_DMRBD_SHIFT (0U)
32559/*! DMRBD - DM Read Bit Delay
32560 */
32561#define DDRPHY_DX7BDLR5_DMRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR5_DMRBD_SHIFT)) & DDRPHY_DX7BDLR5_DMRBD_MASK)
32562#define DDRPHY_DX7BDLR5_RESERVED_31_6_MASK (0xFFFFFFC0U)
32563#define DDRPHY_DX7BDLR5_RESERVED_31_6_SHIFT (6U)
32564/*! RESERVED_31_6 - Reserved. Return zeroes on reads.
32565 */
32566#define DDRPHY_DX7BDLR5_RESERVED_31_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX7BDLR5_RESERVED_31_6_MASK)
32567/*! @} */
32568
32569/*! @name DX7BDLR6 - DATX8 n Bit Delay Line Register 6 */
32570/*! @{ */
32571#define DDRPHY_DX7BDLR6_RESERVED_7_0_MASK (0xFFU)
32572#define DDRPHY_DX7BDLR6_RESERVED_7_0_SHIFT (0U)
32573/*! RESERVED_7_0 - Reserved. Return zeroes on reads.
32574 */
32575#define DDRPHY_DX7BDLR6_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX7BDLR6_RESERVED_7_0_MASK)
32576#define DDRPHY_DX7BDLR6_PDRBD_MASK (0x3F00U)
32577#define DDRPHY_DX7BDLR6_PDRBD_SHIFT (8U)
32578/*! PDRBD - Power down receiver Bit Delay
32579 */
32580#define DDRPHY_DX7BDLR6_PDRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR6_PDRBD_SHIFT)) & DDRPHY_DX7BDLR6_PDRBD_MASK)
32581#define DDRPHY_DX7BDLR6_RESERVED_15_14_MASK (0xC000U)
32582#define DDRPHY_DX7BDLR6_RESERVED_15_14_SHIFT (14U)
32583/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32584 */
32585#define DDRPHY_DX7BDLR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR6_RESERVED_15_14_MASK)
32586#define DDRPHY_DX7BDLR6_TERBD_MASK (0x3F0000U)
32587#define DDRPHY_DX7BDLR6_TERBD_SHIFT (16U)
32588/*! TERBD - Termination Enable Bit Delay
32589 */
32590#define DDRPHY_DX7BDLR6_TERBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR6_TERBD_SHIFT)) & DDRPHY_DX7BDLR6_TERBD_MASK)
32591#define DDRPHY_DX7BDLR6_RESERVED_31_22_MASK (0xFFC00000U)
32592#define DDRPHY_DX7BDLR6_RESERVED_31_22_SHIFT (22U)
32593/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
32594 */
32595#define DDRPHY_DX7BDLR6_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX7BDLR6_RESERVED_31_22_MASK)
32596/*! @} */
32597
32598/*! @name DX7BDLR7 - DATX8 n Bit Delay Line Register 7 */
32599/*! @{ */
32600#define DDRPHY_DX7BDLR7_RESERVED_5_0_MASK (0x3FU)
32601#define DDRPHY_DX7BDLR7_RESERVED_5_0_SHIFT (0U)
32602/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
32603 */
32604#define DDRPHY_DX7BDLR7_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX7BDLR7_RESERVED_5_0_MASK)
32605#define DDRPHY_DX7BDLR7_RESERVED_7_6_MASK (0xC0U)
32606#define DDRPHY_DX7BDLR7_RESERVED_7_6_SHIFT (6U)
32607/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
32608 */
32609#define DDRPHY_DX7BDLR7_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR7_RESERVED_7_6_MASK)
32610#define DDRPHY_DX7BDLR7_RESERVED_13_8_MASK (0x3F00U)
32611#define DDRPHY_DX7BDLR7_RESERVED_13_8_SHIFT (8U)
32612/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
32613 */
32614#define DDRPHY_DX7BDLR7_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX7BDLR7_RESERVED_13_8_MASK)
32615#define DDRPHY_DX7BDLR7_RESERVED_15_14_MASK (0xC000U)
32616#define DDRPHY_DX7BDLR7_RESERVED_15_14_SHIFT (14U)
32617/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32618 */
32619#define DDRPHY_DX7BDLR7_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR7_RESERVED_15_14_MASK)
32620#define DDRPHY_DX7BDLR7_RESERVED_21_16_MASK (0x3F0000U)
32621#define DDRPHY_DX7BDLR7_RESERVED_21_16_SHIFT (16U)
32622/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
32623 */
32624#define DDRPHY_DX7BDLR7_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX7BDLR7_RESERVED_21_16_MASK)
32625#define DDRPHY_DX7BDLR7_RESERVED_31_22_MASK (0xFFC00000U)
32626#define DDRPHY_DX7BDLR7_RESERVED_31_22_SHIFT (22U)
32627/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
32628 */
32629#define DDRPHY_DX7BDLR7_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX7BDLR7_RESERVED_31_22_MASK)
32630/*! @} */
32631
32632/*! @name DX7BDLR8 - DATX8 n Bit Delay Line Register 8 */
32633/*! @{ */
32634#define DDRPHY_DX7BDLR8_RESERVED_5_0_MASK (0x3FU)
32635#define DDRPHY_DX7BDLR8_RESERVED_5_0_SHIFT (0U)
32636/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
32637 */
32638#define DDRPHY_DX7BDLR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX7BDLR8_RESERVED_5_0_MASK)
32639#define DDRPHY_DX7BDLR8_RESERVED_7_6_MASK (0xC0U)
32640#define DDRPHY_DX7BDLR8_RESERVED_7_6_SHIFT (6U)
32641/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
32642 */
32643#define DDRPHY_DX7BDLR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR8_RESERVED_7_6_MASK)
32644#define DDRPHY_DX7BDLR8_RESERVED_13_8_MASK (0x3F00U)
32645#define DDRPHY_DX7BDLR8_RESERVED_13_8_SHIFT (8U)
32646/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
32647 */
32648#define DDRPHY_DX7BDLR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX7BDLR8_RESERVED_13_8_MASK)
32649#define DDRPHY_DX7BDLR8_RESERVED_15_14_MASK (0xC000U)
32650#define DDRPHY_DX7BDLR8_RESERVED_15_14_SHIFT (14U)
32651/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32652 */
32653#define DDRPHY_DX7BDLR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR8_RESERVED_15_14_MASK)
32654#define DDRPHY_DX7BDLR8_RESERVED_21_16_MASK (0x3F0000U)
32655#define DDRPHY_DX7BDLR8_RESERVED_21_16_SHIFT (16U)
32656/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
32657 */
32658#define DDRPHY_DX7BDLR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX7BDLR8_RESERVED_21_16_MASK)
32659#define DDRPHY_DX7BDLR8_RESERVED_31_22_MASK (0xFFC00000U)
32660#define DDRPHY_DX7BDLR8_RESERVED_31_22_SHIFT (22U)
32661/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
32662 */
32663#define DDRPHY_DX7BDLR8_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX7BDLR8_RESERVED_31_22_MASK)
32664/*! @} */
32665
32666/*! @name DX7BDLR9 - DATX8 n Bit Delay Line Register 9 */
32667/*! @{ */
32668#define DDRPHY_DX7BDLR9_RESERVED_5_0_MASK (0x3FU)
32669#define DDRPHY_DX7BDLR9_RESERVED_5_0_SHIFT (0U)
32670/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
32671 */
32672#define DDRPHY_DX7BDLR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX7BDLR9_RESERVED_5_0_MASK)
32673#define DDRPHY_DX7BDLR9_RESERVED_7_6_MASK (0xC0U)
32674#define DDRPHY_DX7BDLR9_RESERVED_7_6_SHIFT (6U)
32675/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
32676 */
32677#define DDRPHY_DX7BDLR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX7BDLR9_RESERVED_7_6_MASK)
32678#define DDRPHY_DX7BDLR9_RESERVED_13_8_MASK (0x3F00U)
32679#define DDRPHY_DX7BDLR9_RESERVED_13_8_SHIFT (8U)
32680/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
32681 */
32682#define DDRPHY_DX7BDLR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX7BDLR9_RESERVED_13_8_MASK)
32683#define DDRPHY_DX7BDLR9_RESERVED_15_14_MASK (0xC000U)
32684#define DDRPHY_DX7BDLR9_RESERVED_15_14_SHIFT (14U)
32685/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
32686 */
32687#define DDRPHY_DX7BDLR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX7BDLR9_RESERVED_15_14_MASK)
32688#define DDRPHY_DX7BDLR9_RESERVED_21_16_MASK (0x3F0000U)
32689#define DDRPHY_DX7BDLR9_RESERVED_21_16_SHIFT (16U)
32690/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
32691 */
32692#define DDRPHY_DX7BDLR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX7BDLR9_RESERVED_21_16_MASK)
32693#define DDRPHY_DX7BDLR9_RESERVED_31_22_MASK (0xFFC00000U)
32694#define DDRPHY_DX7BDLR9_RESERVED_31_22_SHIFT (22U)
32695/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
32696 */
32697#define DDRPHY_DX7BDLR9_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX7BDLR9_RESERVED_31_22_MASK)
32698/*! @} */
32699
32700/*! @name DX7LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */
32701/*! @{ */
32702#define DDRPHY_DX7LCDLR0_WLD_MASK (0x1FFU)
32703#define DDRPHY_DX7LCDLR0_WLD_SHIFT (0U)
32704/*! WLD - Write Leveling Delay
32705 */
32706#define DDRPHY_DX7LCDLR0_WLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR0_WLD_SHIFT)) & DDRPHY_DX7LCDLR0_WLD_MASK)
32707#define DDRPHY_DX7LCDLR0_RESERVED_15_9_MASK (0xFE00U)
32708#define DDRPHY_DX7LCDLR0_RESERVED_15_9_SHIFT (9U)
32709/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
32710 */
32711#define DDRPHY_DX7LCDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX7LCDLR0_RESERVED_15_9_MASK)
32712#define DDRPHY_DX7LCDLR0_RESERVED_24_16_MASK (0x1FF0000U)
32713#define DDRPHY_DX7LCDLR0_RESERVED_24_16_SHIFT (16U)
32714/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
32715 */
32716#define DDRPHY_DX7LCDLR0_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX7LCDLR0_RESERVED_24_16_MASK)
32717#define DDRPHY_DX7LCDLR0_RESERVED_31_25_MASK (0xFE000000U)
32718#define DDRPHY_DX7LCDLR0_RESERVED_31_25_SHIFT (25U)
32719/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
32720 */
32721#define DDRPHY_DX7LCDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX7LCDLR0_RESERVED_31_25_MASK)
32722/*! @} */
32723
32724/*! @name DX7LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */
32725/*! @{ */
32726#define DDRPHY_DX7LCDLR1_WDQD_MASK (0x1FFU)
32727#define DDRPHY_DX7LCDLR1_WDQD_SHIFT (0U)
32728/*! WDQD - Write Data Delay
32729 */
32730#define DDRPHY_DX7LCDLR1_WDQD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR1_WDQD_SHIFT)) & DDRPHY_DX7LCDLR1_WDQD_MASK)
32731#define DDRPHY_DX7LCDLR1_RESERVED_15_9_MASK (0xFE00U)
32732#define DDRPHY_DX7LCDLR1_RESERVED_15_9_SHIFT (9U)
32733/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
32734 */
32735#define DDRPHY_DX7LCDLR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX7LCDLR1_RESERVED_15_9_MASK)
32736#define DDRPHY_DX7LCDLR1_RESERVED_24_16_MASK (0x1FF0000U)
32737#define DDRPHY_DX7LCDLR1_RESERVED_24_16_SHIFT (16U)
32738/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
32739 */
32740#define DDRPHY_DX7LCDLR1_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX7LCDLR1_RESERVED_24_16_MASK)
32741#define DDRPHY_DX7LCDLR1_RESERVED_31_25_MASK (0xFE000000U)
32742#define DDRPHY_DX7LCDLR1_RESERVED_31_25_SHIFT (25U)
32743/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
32744 */
32745#define DDRPHY_DX7LCDLR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX7LCDLR1_RESERVED_31_25_MASK)
32746/*! @} */
32747
32748/*! @name DX7LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */
32749/*! @{ */
32750#define DDRPHY_DX7LCDLR2_DQSGD_MASK (0x1FFU)
32751#define DDRPHY_DX7LCDLR2_DQSGD_SHIFT (0U)
32752/*! DQSGD - Read DQS Gating Delay
32753 */
32754#define DDRPHY_DX7LCDLR2_DQSGD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX7LCDLR2_DQSGD_MASK)
32755#define DDRPHY_DX7LCDLR2_RESERVED_15_9_MASK (0xFE00U)
32756#define DDRPHY_DX7LCDLR2_RESERVED_15_9_SHIFT (9U)
32757/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
32758 */
32759#define DDRPHY_DX7LCDLR2_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX7LCDLR2_RESERVED_15_9_MASK)
32760#define DDRPHY_DX7LCDLR2_RESERVED_24_16_MASK (0x1FF0000U)
32761#define DDRPHY_DX7LCDLR2_RESERVED_24_16_SHIFT (16U)
32762/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
32763 */
32764#define DDRPHY_DX7LCDLR2_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX7LCDLR2_RESERVED_24_16_MASK)
32765#define DDRPHY_DX7LCDLR2_RESERVED_31_25_MASK (0xFE000000U)
32766#define DDRPHY_DX7LCDLR2_RESERVED_31_25_SHIFT (25U)
32767/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
32768 */
32769#define DDRPHY_DX7LCDLR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX7LCDLR2_RESERVED_31_25_MASK)
32770/*! @} */
32771
32772/*! @name DX7LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */
32773/*! @{ */
32774#define DDRPHY_DX7LCDLR3_RDQSD_MASK (0x1FFU)
32775#define DDRPHY_DX7LCDLR3_RDQSD_SHIFT (0U)
32776/*! RDQSD - Read DQS Delay
32777 */
32778#define DDRPHY_DX7LCDLR3_RDQSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX7LCDLR3_RDQSD_MASK)
32779#define DDRPHY_DX7LCDLR3_RESERVED_15_9_MASK (0xFE00U)
32780#define DDRPHY_DX7LCDLR3_RESERVED_15_9_SHIFT (9U)
32781/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
32782 */
32783#define DDRPHY_DX7LCDLR3_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX7LCDLR3_RESERVED_15_9_MASK)
32784#define DDRPHY_DX7LCDLR3_RESERVED_24_16_MASK (0x1FF0000U)
32785#define DDRPHY_DX7LCDLR3_RESERVED_24_16_SHIFT (16U)
32786/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
32787 */
32788#define DDRPHY_DX7LCDLR3_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX7LCDLR3_RESERVED_24_16_MASK)
32789#define DDRPHY_DX7LCDLR3_RESERVED_31_25_MASK (0xFE000000U)
32790#define DDRPHY_DX7LCDLR3_RESERVED_31_25_SHIFT (25U)
32791/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
32792 */
32793#define DDRPHY_DX7LCDLR3_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX7LCDLR3_RESERVED_31_25_MASK)
32794/*! @} */
32795
32796/*! @name DX7LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */
32797/*! @{ */
32798#define DDRPHY_DX7LCDLR4_RDQSND_MASK (0x1FFU)
32799#define DDRPHY_DX7LCDLR4_RDQSND_SHIFT (0U)
32800/*! RDQSND - Read DQSN Delay
32801 */
32802#define DDRPHY_DX7LCDLR4_RDQSND(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX7LCDLR4_RDQSND_MASK)
32803#define DDRPHY_DX7LCDLR4_RESERVED_15_9_MASK (0xFE00U)
32804#define DDRPHY_DX7LCDLR4_RESERVED_15_9_SHIFT (9U)
32805/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
32806 */
32807#define DDRPHY_DX7LCDLR4_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX7LCDLR4_RESERVED_15_9_MASK)
32808#define DDRPHY_DX7LCDLR4_RESERVED_24_16_MASK (0x1FF0000U)
32809#define DDRPHY_DX7LCDLR4_RESERVED_24_16_SHIFT (16U)
32810/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
32811 */
32812#define DDRPHY_DX7LCDLR4_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX7LCDLR4_RESERVED_24_16_MASK)
32813#define DDRPHY_DX7LCDLR4_RESERVED_31_25_MASK (0xFE000000U)
32814#define DDRPHY_DX7LCDLR4_RESERVED_31_25_SHIFT (25U)
32815/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
32816 */
32817#define DDRPHY_DX7LCDLR4_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX7LCDLR4_RESERVED_31_25_MASK)
32818/*! @} */
32819
32820/*! @name DX7LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */
32821/*! @{ */
32822#define DDRPHY_DX7LCDLR5_DQSGSD_MASK (0x1FFU)
32823#define DDRPHY_DX7LCDLR5_DQSGSD_SHIFT (0U)
32824/*! DQSGSD - DQS Gating Status Delay
32825 */
32826#define DDRPHY_DX7LCDLR5_DQSGSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX7LCDLR5_DQSGSD_MASK)
32827#define DDRPHY_DX7LCDLR5_RESERVED_15_9_MASK (0xFE00U)
32828#define DDRPHY_DX7LCDLR5_RESERVED_15_9_SHIFT (9U)
32829/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
32830 */
32831#define DDRPHY_DX7LCDLR5_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX7LCDLR5_RESERVED_15_9_MASK)
32832#define DDRPHY_DX7LCDLR5_RESERVED_24_16_MASK (0x1FF0000U)
32833#define DDRPHY_DX7LCDLR5_RESERVED_24_16_SHIFT (16U)
32834/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
32835 */
32836#define DDRPHY_DX7LCDLR5_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX7LCDLR5_RESERVED_24_16_MASK)
32837#define DDRPHY_DX7LCDLR5_RESERVED_31_25_MASK (0xFE000000U)
32838#define DDRPHY_DX7LCDLR5_RESERVED_31_25_SHIFT (25U)
32839/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
32840 */
32841#define DDRPHY_DX7LCDLR5_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX7LCDLR5_RESERVED_31_25_MASK)
32842/*! @} */
32843
32844/*! @name DX7MDLR0 - DATX8 n Master Delay Line Register 0 */
32845/*! @{ */
32846#define DDRPHY_DX7MDLR0_IPRD_MASK (0x1FFU)
32847#define DDRPHY_DX7MDLR0_IPRD_SHIFT (0U)
32848/*! IPRD - Initial Period
32849 */
32850#define DDRPHY_DX7MDLR0_IPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7MDLR0_IPRD_SHIFT)) & DDRPHY_DX7MDLR0_IPRD_MASK)
32851#define DDRPHY_DX7MDLR0_RESERVED_15_9_MASK (0xFE00U)
32852#define DDRPHY_DX7MDLR0_RESERVED_15_9_SHIFT (9U)
32853/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
32854 */
32855#define DDRPHY_DX7MDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX7MDLR0_RESERVED_15_9_MASK)
32856#define DDRPHY_DX7MDLR0_TPRD_MASK (0x1FF0000U)
32857#define DDRPHY_DX7MDLR0_TPRD_SHIFT (16U)
32858/*! TPRD - Target Period
32859 */
32860#define DDRPHY_DX7MDLR0_TPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7MDLR0_TPRD_SHIFT)) & DDRPHY_DX7MDLR0_TPRD_MASK)
32861#define DDRPHY_DX7MDLR0_RESERVED_31_25_MASK (0xFE000000U)
32862#define DDRPHY_DX7MDLR0_RESERVED_31_25_SHIFT (25U)
32863/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
32864 */
32865#define DDRPHY_DX7MDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX7MDLR0_RESERVED_31_25_MASK)
32866/*! @} */
32867
32868/*! @name DX7MDLR1 - DATX8 n Master Delay Line Register 1 */
32869/*! @{ */
32870#define DDRPHY_DX7MDLR1_MDLD_MASK (0x1FFU)
32871#define DDRPHY_DX7MDLR1_MDLD_SHIFT (0U)
32872/*! MDLD - MDL Delay
32873 */
32874#define DDRPHY_DX7MDLR1_MDLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7MDLR1_MDLD_SHIFT)) & DDRPHY_DX7MDLR1_MDLD_MASK)
32875#define DDRPHY_DX7MDLR1_RESERVED_31_9_MASK (0xFFFFFE00U)
32876#define DDRPHY_DX7MDLR1_RESERVED_31_9_SHIFT (9U)
32877/*! RESERVED_31_9 - Reserved. Return zeroes on reads.
32878 */
32879#define DDRPHY_DX7MDLR1_RESERVED_31_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX7MDLR1_RESERVED_31_9_MASK)
32880/*! @} */
32881
32882/*! @name DX7GTR0 - DATX8 n General Timing Register 0 */
32883/*! @{ */
32884#define DDRPHY_DX7GTR0_DGSL_MASK (0x1FU)
32885#define DDRPHY_DX7GTR0_DGSL_SHIFT (0U)
32886/*! DGSL - DQS Gating System Latency
32887 */
32888#define DDRPHY_DX7GTR0_DGSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_DGSL_SHIFT)) & DDRPHY_DX7GTR0_DGSL_MASK)
32889#define DDRPHY_DX7GTR0_RESERVED_7_5_MASK (0xE0U)
32890#define DDRPHY_DX7GTR0_RESERVED_7_5_SHIFT (5U)
32891/*! RESERVED_7_5 - Reserved. Return zeroes on reads.
32892 */
32893#define DDRPHY_DX7GTR0_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX7GTR0_RESERVED_7_5_MASK)
32894#define DDRPHY_DX7GTR0_RESERVED_12_8_MASK (0x1F00U)
32895#define DDRPHY_DX7GTR0_RESERVED_12_8_SHIFT (8U)
32896/*! RESERVED_12_8 - Reserved. Caution, do not write to this register field.
32897 */
32898#define DDRPHY_DX7GTR0_RESERVED_12_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX7GTR0_RESERVED_12_8_MASK)
32899#define DDRPHY_DX7GTR0_RESERVED_15_13_MASK (0xE000U)
32900#define DDRPHY_DX7GTR0_RESERVED_15_13_SHIFT (13U)
32901/*! RESERVED_15_13 - Reserved. Return zeroes on reads.
32902 */
32903#define DDRPHY_DX7GTR0_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX7GTR0_RESERVED_15_13_MASK)
32904#define DDRPHY_DX7GTR0_WLSL_MASK (0xF0000U)
32905#define DDRPHY_DX7GTR0_WLSL_SHIFT (16U)
32906/*! WLSL - Write Leveling System Latency
32907 */
32908#define DDRPHY_DX7GTR0_WLSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_WLSL_SHIFT)) & DDRPHY_DX7GTR0_WLSL_MASK)
32909#define DDRPHY_DX7GTR0_RESERVED_23_20_MASK (0xF00000U)
32910#define DDRPHY_DX7GTR0_RESERVED_23_20_SHIFT (20U)
32911/*! RESERVED_23_20 - Reserved. Caution, do not write to this register field.
32912 */
32913#define DDRPHY_DX7GTR0_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX7GTR0_RESERVED_23_20_MASK)
32914#define DDRPHY_DX7GTR0_WDQSL_MASK (0x7000000U)
32915#define DDRPHY_DX7GTR0_WDQSL_SHIFT (24U)
32916/*! WDQSL - DQ Write Path Latency Pipeline
32917 */
32918#define DDRPHY_DX7GTR0_WDQSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_WDQSL_SHIFT)) & DDRPHY_DX7GTR0_WDQSL_MASK)
32919#define DDRPHY_DX7GTR0_RESERVED_31_24_MASK (0xF8000000U)
32920#define DDRPHY_DX7GTR0_RESERVED_31_24_SHIFT (27U)
32921/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
32922 */
32923#define DDRPHY_DX7GTR0_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX7GTR0_RESERVED_31_24_MASK)
32924/*! @} */
32925
32926/*! @name DX7RSR0 - DATX8 n Rank Status Register 0 */
32927/*! @{ */
32928#define DDRPHY_DX7RSR0_QSGERR_MASK (0xFFFFU)
32929#define DDRPHY_DX7RSR0_QSGERR_SHIFT (0U)
32930/*! QSGERR - DQS Gate Training Error
32931 */
32932#define DDRPHY_DX7RSR0_QSGERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR0_QSGERR_SHIFT)) & DDRPHY_DX7RSR0_QSGERR_MASK)
32933#define DDRPHY_DX7RSR0_RESERVED_31_16_MASK (0xFFFF0000U)
32934#define DDRPHY_DX7RSR0_RESERVED_31_16_SHIFT (16U)
32935/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
32936 */
32937#define DDRPHY_DX7RSR0_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX7RSR0_RESERVED_31_16_MASK)
32938/*! @} */
32939
32940/*! @name DX7RSR1 - DATX8 n Rank Status Register 1 */
32941/*! @{ */
32942#define DDRPHY_DX7RSR1_RDLVLERR_MASK (0xFFFFU)
32943#define DDRPHY_DX7RSR1_RDLVLERR_SHIFT (0U)
32944/*! RDLVLERR - Read Leveling Error
32945 */
32946#define DDRPHY_DX7RSR1_RDLVLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX7RSR1_RDLVLERR_MASK)
32947#define DDRPHY_DX7RSR1_RESERVED_31_16_MASK (0xFFFF0000U)
32948#define DDRPHY_DX7RSR1_RESERVED_31_16_SHIFT (16U)
32949/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
32950 */
32951#define DDRPHY_DX7RSR1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX7RSR1_RESERVED_31_16_MASK)
32952/*! @} */
32953
32954/*! @name DX7RSR2 - DATX8 n Rank Status Register 2 */
32955/*! @{ */
32956#define DDRPHY_DX7RSR2_WLAWN_MASK (0xFFFFU)
32957#define DDRPHY_DX7RSR2_WLAWN_SHIFT (0U)
32958/*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning
32959 */
32960#define DDRPHY_DX7RSR2_WLAWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR2_WLAWN_SHIFT)) & DDRPHY_DX7RSR2_WLAWN_MASK)
32961#define DDRPHY_DX7RSR2_RESERVED_31_16_MASK (0xFFFF0000U)
32962#define DDRPHY_DX7RSR2_RESERVED_31_16_SHIFT (16U)
32963/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
32964 */
32965#define DDRPHY_DX7RSR2_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX7RSR2_RESERVED_31_16_MASK)
32966/*! @} */
32967
32968/*! @name DX7RSR3 - DATX8 n Rank Status Register 3 */
32969/*! @{ */
32970#define DDRPHY_DX7RSR3_WLAERR_MASK (0xFFFFU)
32971#define DDRPHY_DX7RSR3_WLAERR_SHIFT (0U)
32972/*! WLAERR - Write Leveling Adjustment Error
32973 */
32974#define DDRPHY_DX7RSR3_WLAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR3_WLAERR_SHIFT)) & DDRPHY_DX7RSR3_WLAERR_MASK)
32975#define DDRPHY_DX7RSR3_RESERVED_31_16_MASK (0xFFFF0000U)
32976#define DDRPHY_DX7RSR3_RESERVED_31_16_SHIFT (16U)
32977/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
32978 */
32979#define DDRPHY_DX7RSR3_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX7RSR3_RESERVED_31_16_MASK)
32980/*! @} */
32981
32982/*! @name DX7GSR0 - DATX8 n General Status Register 0 */
32983/*! @{ */
32984#define DDRPHY_DX7GSR0_WDQCAL_MASK (0x1U)
32985#define DDRPHY_DX7GSR0_WDQCAL_SHIFT (0U)
32986/*! WDQCAL - Write DQ Calibration
32987 */
32988#define DDRPHY_DX7GSR0_WDQCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_WDQCAL_SHIFT)) & DDRPHY_DX7GSR0_WDQCAL_MASK)
32989#define DDRPHY_DX7GSR0_RDQSCAL_MASK (0x2U)
32990#define DDRPHY_DX7GSR0_RDQSCAL_SHIFT (1U)
32991/*! RDQSCAL - Read DQS Calibration
32992 */
32993#define DDRPHY_DX7GSR0_RDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX7GSR0_RDQSCAL_MASK)
32994#define DDRPHY_DX7GSR0_RDQSNCAL_MASK (0x4U)
32995#define DDRPHY_DX7GSR0_RDQSNCAL_SHIFT (2U)
32996/*! RDQSNCAL - Read DQS# Calibration
32997 */
32998#define DDRPHY_DX7GSR0_RDQSNCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX7GSR0_RDQSNCAL_MASK)
32999#define DDRPHY_DX7GSR0_GDQSCAL_MASK (0x8U)
33000#define DDRPHY_DX7GSR0_GDQSCAL_SHIFT (3U)
33001/*! GDQSCAL - Read DQS gating Calibration
33002 */
33003#define DDRPHY_DX7GSR0_GDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX7GSR0_GDQSCAL_MASK)
33004#define DDRPHY_DX7GSR0_WLCAL_MASK (0x10U)
33005#define DDRPHY_DX7GSR0_WLCAL_SHIFT (4U)
33006/*! WLCAL - Write Leveling Calibration
33007 */
33008#define DDRPHY_DX7GSR0_WLCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_WLCAL_SHIFT)) & DDRPHY_DX7GSR0_WLCAL_MASK)
33009#define DDRPHY_DX7GSR0_WLDONE_MASK (0x20U)
33010#define DDRPHY_DX7GSR0_WLDONE_SHIFT (5U)
33011/*! WLDONE - Write Leveling Done
33012 */
33013#define DDRPHY_DX7GSR0_WLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_WLDONE_SHIFT)) & DDRPHY_DX7GSR0_WLDONE_MASK)
33014#define DDRPHY_DX7GSR0_WLERR_MASK (0x40U)
33015#define DDRPHY_DX7GSR0_WLERR_SHIFT (6U)
33016/*! WLERR - Write Leveling Error
33017 */
33018#define DDRPHY_DX7GSR0_WLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_WLERR_SHIFT)) & DDRPHY_DX7GSR0_WLERR_MASK)
33019#define DDRPHY_DX7GSR0_WLPRD_MASK (0xFF80U)
33020#define DDRPHY_DX7GSR0_WLPRD_SHIFT (7U)
33021/*! WLPRD - Write Leveling Period
33022 */
33023#define DDRPHY_DX7GSR0_WLPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_WLPRD_SHIFT)) & DDRPHY_DX7GSR0_WLPRD_MASK)
33024#define DDRPHY_DX7GSR0_DPLOCK_MASK (0x10000U)
33025#define DDRPHY_DX7GSR0_DPLOCK_SHIFT (16U)
33026/*! DPLOCK - DATX8 PLL Lock
33027 */
33028#define DDRPHY_DX7GSR0_DPLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_DPLOCK_SHIFT)) & DDRPHY_DX7GSR0_DPLOCK_MASK)
33029#define DDRPHY_DX7GSR0_GDQSPRD_MASK (0x3FE0000U)
33030#define DDRPHY_DX7GSR0_GDQSPRD_SHIFT (17U)
33031/*! GDQSPRD - Read DQS gating Period
33032 */
33033#define DDRPHY_DX7GSR0_GDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX7GSR0_GDQSPRD_MASK)
33034#define DDRPHY_DX7GSR0_RESERVED_29_26_MASK (0x3C000000U)
33035#define DDRPHY_DX7GSR0_RESERVED_29_26_SHIFT (26U)
33036/*! RESERVED_29_26 - Reserved. Returns zeroes on reads.
33037 */
33038#define DDRPHY_DX7GSR0_RESERVED_29_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX7GSR0_RESERVED_29_26_MASK)
33039#define DDRPHY_DX7GSR0_WLDQ_MASK (0x40000000U)
33040#define DDRPHY_DX7GSR0_WLDQ_SHIFT (30U)
33041/*! WLDQ - Write Leveling DQ Status
33042 */
33043#define DDRPHY_DX7GSR0_WLDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_WLDQ_SHIFT)) & DDRPHY_DX7GSR0_WLDQ_MASK)
33044#define DDRPHY_DX7GSR0_RESERVED_31_MASK (0x80000000U)
33045#define DDRPHY_DX7GSR0_RESERVED_31_SHIFT (31U)
33046/*! RESERVED_31 - Reserved. Returns zeroes on reads.
33047 */
33048#define DDRPHY_DX7GSR0_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX7GSR0_RESERVED_31_MASK)
33049/*! @} */
33050
33051/*! @name DX7GSR1 - DATX8 n General Status Register 1 */
33052/*! @{ */
33053#define DDRPHY_DX7GSR1_DLTDONE_MASK (0x1U)
33054#define DDRPHY_DX7GSR1_DLTDONE_SHIFT (0U)
33055/*! DLTDONE - Delay Line Test Done
33056 */
33057#define DDRPHY_DX7GSR1_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR1_DLTDONE_SHIFT)) & DDRPHY_DX7GSR1_DLTDONE_MASK)
33058#define DDRPHY_DX7GSR1_DLTCODE_MASK (0x1FFFFFEU)
33059#define DDRPHY_DX7GSR1_DLTCODE_SHIFT (1U)
33060/*! DLTCODE - Delay Line Test Code
33061 */
33062#define DDRPHY_DX7GSR1_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR1_DLTCODE_SHIFT)) & DDRPHY_DX7GSR1_DLTCODE_MASK)
33063#define DDRPHY_DX7GSR1_RESERVED_31_25_MASK (0xFE000000U)
33064#define DDRPHY_DX7GSR1_RESERVED_31_25_SHIFT (25U)
33065/*! RESERVED_31_25 - Reserved. Returns zeroes on reads.
33066 */
33067#define DDRPHY_DX7GSR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX7GSR1_RESERVED_31_25_MASK)
33068/*! @} */
33069
33070/*! @name DX7GSR2 - DATX8 n General Status Register 2 */
33071/*! @{ */
33072#define DDRPHY_DX7GSR2_RDERR_MASK (0x1U)
33073#define DDRPHY_DX7GSR2_RDERR_SHIFT (0U)
33074/*! RDERR - Read Bit Deskew Error
33075 */
33076#define DDRPHY_DX7GSR2_RDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_RDERR_SHIFT)) & DDRPHY_DX7GSR2_RDERR_MASK)
33077#define DDRPHY_DX7GSR2_RDWN_MASK (0x2U)
33078#define DDRPHY_DX7GSR2_RDWN_SHIFT (1U)
33079/*! RDWN - Read Bit Deskew Warning
33080 */
33081#define DDRPHY_DX7GSR2_RDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_RDWN_SHIFT)) & DDRPHY_DX7GSR2_RDWN_MASK)
33082#define DDRPHY_DX7GSR2_WDERR_MASK (0x4U)
33083#define DDRPHY_DX7GSR2_WDERR_SHIFT (2U)
33084/*! WDERR - Write Bit Deskew Error
33085 */
33086#define DDRPHY_DX7GSR2_WDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_WDERR_SHIFT)) & DDRPHY_DX7GSR2_WDERR_MASK)
33087#define DDRPHY_DX7GSR2_WDWN_MASK (0x8U)
33088#define DDRPHY_DX7GSR2_WDWN_SHIFT (3U)
33089/*! WDWN - Write Bit Deskew Warning
33090 */
33091#define DDRPHY_DX7GSR2_WDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_WDWN_SHIFT)) & DDRPHY_DX7GSR2_WDWN_MASK)
33092#define DDRPHY_DX7GSR2_REERR_MASK (0x10U)
33093#define DDRPHY_DX7GSR2_REERR_SHIFT (4U)
33094/*! REERR - Read Eye Centering Error
33095 */
33096#define DDRPHY_DX7GSR2_REERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_REERR_SHIFT)) & DDRPHY_DX7GSR2_REERR_MASK)
33097#define DDRPHY_DX7GSR2_REWN_MASK (0x20U)
33098#define DDRPHY_DX7GSR2_REWN_SHIFT (5U)
33099/*! REWN - Read Eye Centering Warning
33100 */
33101#define DDRPHY_DX7GSR2_REWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_REWN_SHIFT)) & DDRPHY_DX7GSR2_REWN_MASK)
33102#define DDRPHY_DX7GSR2_WEERR_MASK (0x40U)
33103#define DDRPHY_DX7GSR2_WEERR_SHIFT (6U)
33104/*! WEERR - Write Eye Centering Error
33105 */
33106#define DDRPHY_DX7GSR2_WEERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_WEERR_SHIFT)) & DDRPHY_DX7GSR2_WEERR_MASK)
33107#define DDRPHY_DX7GSR2_WEWN_MASK (0x80U)
33108#define DDRPHY_DX7GSR2_WEWN_SHIFT (7U)
33109/*! WEWN - Write Eye Centering Warning
33110 */
33111#define DDRPHY_DX7GSR2_WEWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_WEWN_SHIFT)) & DDRPHY_DX7GSR2_WEWN_MASK)
33112#define DDRPHY_DX7GSR2_ESTAT_MASK (0xF00U)
33113#define DDRPHY_DX7GSR2_ESTAT_SHIFT (8U)
33114/*! ESTAT - Error Status
33115 */
33116#define DDRPHY_DX7GSR2_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_ESTAT_SHIFT)) & DDRPHY_DX7GSR2_ESTAT_MASK)
33117#define DDRPHY_DX7GSR2_DQS2DQERR_MASK (0xFF000U)
33118#define DDRPHY_DX7GSR2_DQS2DQERR_SHIFT (12U)
33119/*! DQS2DQERR - Write DQS2DQ Training Error
33120 */
33121#define DDRPHY_DX7GSR2_DQS2DQERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX7GSR2_DQS2DQERR_MASK)
33122#define DDRPHY_DX7GSR2_SRDERR_MASK (0x100000U)
33123#define DDRPHY_DX7GSR2_SRDERR_SHIFT (20U)
33124/*! SRDERR - Static Read Error
33125 */
33126#define DDRPHY_DX7GSR2_SRDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_SRDERR_SHIFT)) & DDRPHY_DX7GSR2_SRDERR_MASK)
33127#define DDRPHY_DX7GSR2_RESERVED_21_MASK (0x200000U)
33128#define DDRPHY_DX7GSR2_RESERVED_21_SHIFT (21U)
33129/*! RESERVED_21 - Reserved. Return zeroes on reads.
33130 */
33131#define DDRPHY_DX7GSR2_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX7GSR2_RESERVED_21_MASK)
33132#define DDRPHY_DX7GSR2_GSDQSCAL_MASK (0x400000U)
33133#define DDRPHY_DX7GSR2_GSDQSCAL_SHIFT (22U)
33134/*! GSDQSCAL - Read DQS Gating Status Calibration
33135 */
33136#define DDRPHY_DX7GSR2_GSDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX7GSR2_GSDQSCAL_MASK)
33137#define DDRPHY_DX7GSR2_GSDQSPRD_MASK (0xFF800000U)
33138#define DDRPHY_DX7GSR2_GSDQSPRD_SHIFT (23U)
33139/*! GSDQSPRD - Read DQS gating Status Period
33140 */
33141#define DDRPHY_DX7GSR2_GSDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX7GSR2_GSDQSPRD_MASK)
33142/*! @} */
33143
33144/*! @name DX7GSR3 - DATX8 n General Status Register 3 */
33145/*! @{ */
33146#define DDRPHY_DX7GSR3_SRDPC_MASK (0x3U)
33147#define DDRPHY_DX7GSR3_SRDPC_SHIFT (0U)
33148/*! SRDPC - Static Read Delay Pass Count
33149 */
33150#define DDRPHY_DX7GSR3_SRDPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_SRDPC_SHIFT)) & DDRPHY_DX7GSR3_SRDPC_MASK)
33151#define DDRPHY_DX7GSR3_RESERVED_7_2_MASK (0xFCU)
33152#define DDRPHY_DX7GSR3_RESERVED_7_2_SHIFT (2U)
33153/*! RESERVED_7_2 - Reserved. Return zeroes on reads.
33154 */
33155#define DDRPHY_DX7GSR3_RESERVED_7_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX7GSR3_RESERVED_7_2_MASK)
33156#define DDRPHY_DX7GSR3_HVERR_MASK (0xF00U)
33157#define DDRPHY_DX7GSR3_HVERR_SHIFT (8U)
33158/*! HVERR - Host VREF Training Error
33159 */
33160#define DDRPHY_DX7GSR3_HVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_HVERR_SHIFT)) & DDRPHY_DX7GSR3_HVERR_MASK)
33161#define DDRPHY_DX7GSR3_HVWRN_MASK (0xF000U)
33162#define DDRPHY_DX7GSR3_HVWRN_SHIFT (12U)
33163/*! HVWRN - Host VREF Training Warning
33164 */
33165#define DDRPHY_DX7GSR3_HVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_HVWRN_SHIFT)) & DDRPHY_DX7GSR3_HVWRN_MASK)
33166#define DDRPHY_DX7GSR3_DVERR_MASK (0xF0000U)
33167#define DDRPHY_DX7GSR3_DVERR_SHIFT (16U)
33168/*! DVERR - DRAM VREF Training Error
33169 */
33170#define DDRPHY_DX7GSR3_DVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_DVERR_SHIFT)) & DDRPHY_DX7GSR3_DVERR_MASK)
33171#define DDRPHY_DX7GSR3_DVWRN_MASK (0xF00000U)
33172#define DDRPHY_DX7GSR3_DVWRN_SHIFT (20U)
33173/*! DVWRN - DRAM VREF Training Warning
33174 */
33175#define DDRPHY_DX7GSR3_DVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_DVWRN_SHIFT)) & DDRPHY_DX7GSR3_DVWRN_MASK)
33176#define DDRPHY_DX7GSR3_ESTAT_MASK (0x7000000U)
33177#define DDRPHY_DX7GSR3_ESTAT_SHIFT (24U)
33178/*! ESTAT - VREF Training Error Status Code
33179 */
33180#define DDRPHY_DX7GSR3_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_ESTAT_SHIFT)) & DDRPHY_DX7GSR3_ESTAT_MASK)
33181#define DDRPHY_DX7GSR3_RESERVED_31_27_MASK (0xF8000000U)
33182#define DDRPHY_DX7GSR3_RESERVED_31_27_SHIFT (27U)
33183/*! RESERVED_31_27 - Reserved. Return zeroes on reads.
33184 */
33185#define DDRPHY_DX7GSR3_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX7GSR3_RESERVED_31_27_MASK)
33186/*! @} */
33187
33188/*! @name DX7GSR4 - DATX8 n General Status Register 4 */
33189/*! @{ */
33190#define DDRPHY_DX7GSR4_RESERVED_0_MASK (0x1U)
33191#define DDRPHY_DX7GSR4_RESERVED_0_SHIFT (0U)
33192/*! RESERVED_0 - Reserved. Return zeroes on reads.
33193 */
33194#define DDRPHY_DX7GSR4_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_0_MASK)
33195#define DDRPHY_DX7GSR4_RESERVED_1_MASK (0x2U)
33196#define DDRPHY_DX7GSR4_RESERVED_1_SHIFT (1U)
33197/*! RESERVED_1 - Reserved. Return zeroes on reads.
33198 */
33199#define DDRPHY_DX7GSR4_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_1_MASK)
33200#define DDRPHY_DX7GSR4_RESERVED_2_MASK (0x4U)
33201#define DDRPHY_DX7GSR4_RESERVED_2_SHIFT (2U)
33202/*! RESERVED_2 - Reserved. Return zeroes on reads.
33203 */
33204#define DDRPHY_DX7GSR4_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_2_MASK)
33205#define DDRPHY_DX7GSR4_RESERVED_3_MASK (0x8U)
33206#define DDRPHY_DX7GSR4_RESERVED_3_SHIFT (3U)
33207/*! RESERVED_3 - Reserved. Return zeroes on reads.
33208 */
33209#define DDRPHY_DX7GSR4_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_3_MASK)
33210#define DDRPHY_DX7GSR4_RESERVED_4_MASK (0x10U)
33211#define DDRPHY_DX7GSR4_RESERVED_4_SHIFT (4U)
33212/*! RESERVED_4 - Reserved. Return zeroes on reads.
33213 */
33214#define DDRPHY_DX7GSR4_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_4_MASK)
33215#define DDRPHY_DX7GSR4_RESERVED_5_MASK (0x20U)
33216#define DDRPHY_DX7GSR4_RESERVED_5_SHIFT (5U)
33217/*! RESERVED_5 - Reserved. Return zeroes on reads.
33218 */
33219#define DDRPHY_DX7GSR4_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_5_MASK)
33220#define DDRPHY_DX7GSR4_RESERVED_6_MASK (0x40U)
33221#define DDRPHY_DX7GSR4_RESERVED_6_SHIFT (6U)
33222/*! RESERVED_6 - Reserved. Return zeroes on reads.
33223 */
33224#define DDRPHY_DX7GSR4_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_6_MASK)
33225#define DDRPHY_DX7GSR4_RESERVED_15_7_MASK (0xFF80U)
33226#define DDRPHY_DX7GSR4_RESERVED_15_7_SHIFT (7U)
33227/*! RESERVED_15_7 - Reserved. Return zeroes on reads.
33228 */
33229#define DDRPHY_DX7GSR4_RESERVED_15_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_15_7_MASK)
33230#define DDRPHY_DX7GSR4_RESERVED_16_MASK (0x10000U)
33231#define DDRPHY_DX7GSR4_RESERVED_16_SHIFT (16U)
33232/*! RESERVED_16 - Reserved. Return zeroes on reads.
33233 */
33234#define DDRPHY_DX7GSR4_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_16_MASK)
33235#define DDRPHY_DX7GSR4_RESERVED_25_17_MASK (0x3FE0000U)
33236#define DDRPHY_DX7GSR4_RESERVED_25_17_SHIFT (17U)
33237/*! RESERVED_25_17 - Reserved. Return zeroes on reads.
33238 */
33239#define DDRPHY_DX7GSR4_RESERVED_25_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_25_17_MASK)
33240#define DDRPHY_DX7GSR4_RESERVED_31_26_MASK (0xFC000000U)
33241#define DDRPHY_DX7GSR4_RESERVED_31_26_SHIFT (26U)
33242/*! RESERVED_31_26 - Reserved. Returns zeroes on reads.
33243 */
33244#define DDRPHY_DX7GSR4_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX7GSR4_RESERVED_31_26_MASK)
33245/*! @} */
33246
33247/*! @name DX7GSR5 - DATX8 n General Status Register 5 */
33248/*! @{ */
33249#define DDRPHY_DX7GSR5_RESERVED_0_MASK (0x1U)
33250#define DDRPHY_DX7GSR5_RESERVED_0_SHIFT (0U)
33251/*! RESERVED_0 - Reserved. Return zeroes on reads.
33252 */
33253#define DDRPHY_DX7GSR5_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_0_MASK)
33254#define DDRPHY_DX7GSR5_RESERVED_1_MASK (0x2U)
33255#define DDRPHY_DX7GSR5_RESERVED_1_SHIFT (1U)
33256/*! RESERVED_1 - Reserved. Return zeroes on reads.
33257 */
33258#define DDRPHY_DX7GSR5_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_1_MASK)
33259#define DDRPHY_DX7GSR5_RESERVED_2_MASK (0x4U)
33260#define DDRPHY_DX7GSR5_RESERVED_2_SHIFT (2U)
33261/*! RESERVED_2 - Reserved. Return zeroes on reads.
33262 */
33263#define DDRPHY_DX7GSR5_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_2_MASK)
33264#define DDRPHY_DX7GSR5_RESERVED_3_MASK (0x8U)
33265#define DDRPHY_DX7GSR5_RESERVED_3_SHIFT (3U)
33266/*! RESERVED_3 - Reserved. Return zeroes on reads.
33267 */
33268#define DDRPHY_DX7GSR5_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_3_MASK)
33269#define DDRPHY_DX7GSR5_RESERVED_4_MASK (0x10U)
33270#define DDRPHY_DX7GSR5_RESERVED_4_SHIFT (4U)
33271/*! RESERVED_4 - Reserved. Return zeroes on reads.
33272 */
33273#define DDRPHY_DX7GSR5_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_4_MASK)
33274#define DDRPHY_DX7GSR5_RESERVED_5_MASK (0x20U)
33275#define DDRPHY_DX7GSR5_RESERVED_5_SHIFT (5U)
33276/*! RESERVED_5 - Reserved. Return zeroes on reads.
33277 */
33278#define DDRPHY_DX7GSR5_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_5_MASK)
33279#define DDRPHY_DX7GSR5_RESERVED_6_MASK (0x40U)
33280#define DDRPHY_DX7GSR5_RESERVED_6_SHIFT (6U)
33281/*! RESERVED_6 - Reserved. Return zeroes on reads.
33282 */
33283#define DDRPHY_DX7GSR5_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_6_MASK)
33284#define DDRPHY_DX7GSR5_RESERVED_7_MASK (0x80U)
33285#define DDRPHY_DX7GSR5_RESERVED_7_SHIFT (7U)
33286/*! RESERVED_7 - Reserved. Return zeroes on reads.
33287 */
33288#define DDRPHY_DX7GSR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_7_MASK)
33289#define DDRPHY_DX7GSR5_RESERVED_11_8_MASK (0xF00U)
33290#define DDRPHY_DX7GSR5_RESERVED_11_8_SHIFT (8U)
33291/*! RESERVED_11_8 - Reserved. Return zeroes on reads.
33292 */
33293#define DDRPHY_DX7GSR5_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_11_8_MASK)
33294#define DDRPHY_DX7GSR5_RESERVED_19_12_MASK (0xFF000U)
33295#define DDRPHY_DX7GSR5_RESERVED_19_12_SHIFT (12U)
33296/*! RESERVED_19_12 - Reserved. Return zeroes on reads.
33297 */
33298#define DDRPHY_DX7GSR5_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_19_12_MASK)
33299#define DDRPHY_DX7GSR5_RESERVED_20_MASK (0x100000U)
33300#define DDRPHY_DX7GSR5_RESERVED_20_SHIFT (20U)
33301/*! RESERVED_20 - Reserved. Return zeroes on reads.
33302 */
33303#define DDRPHY_DX7GSR5_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_20_MASK)
33304#define DDRPHY_DX7GSR5_RESERVED_21_MASK (0x200000U)
33305#define DDRPHY_DX7GSR5_RESERVED_21_SHIFT (21U)
33306/*! RESERVED_21 - Reserved. Return zeroes on reads.
33307 */
33308#define DDRPHY_DX7GSR5_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_21_MASK)
33309#define DDRPHY_DX7GSR5_RESERVED_22_MASK (0x400000U)
33310#define DDRPHY_DX7GSR5_RESERVED_22_SHIFT (22U)
33311/*! RESERVED_22 - Reserved. Return zeroes on reads.
33312 */
33313#define DDRPHY_DX7GSR5_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_22_MASK)
33314#define DDRPHY_DX7GSR5_RESERVED_31_23_MASK (0xFF800000U)
33315#define DDRPHY_DX7GSR5_RESERVED_31_23_SHIFT (23U)
33316/*! RESERVED_31_23 - Reserved. Return zeroes on reads.
33317 */
33318#define DDRPHY_DX7GSR5_RESERVED_31_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX7GSR5_RESERVED_31_23_MASK)
33319/*! @} */
33320
33321/*! @name DX7GSR6 - DATX8 n General Status Register 6 */
33322/*! @{ */
33323#define DDRPHY_DX7GSR6_RESERVED_1_0_MASK (0x3U)
33324#define DDRPHY_DX7GSR6_RESERVED_1_0_SHIFT (0U)
33325/*! RESERVED_1_0 - Reserved. Return zeroes on reads.
33326 */
33327#define DDRPHY_DX7GSR6_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_1_0_MASK)
33328#define DDRPHY_DX7GSR6_RESERVED_3_2_MASK (0xCU)
33329#define DDRPHY_DX7GSR6_RESERVED_3_2_SHIFT (2U)
33330/*! RESERVED_3_2 - Reserved. Return zeroes on reads.
33331 */
33332#define DDRPHY_DX7GSR6_RESERVED_3_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_3_2_MASK)
33333#define DDRPHY_DX7GSR6_RESERVED_7_4_MASK (0xF0U)
33334#define DDRPHY_DX7GSR6_RESERVED_7_4_SHIFT (4U)
33335/*! RESERVED_7_4 - Reserved. Return zeroes on reads.
33336 */
33337#define DDRPHY_DX7GSR6_RESERVED_7_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_7_4_MASK)
33338#define DDRPHY_DX7GSR6_RESERVED_11_8_MASK (0xF00U)
33339#define DDRPHY_DX7GSR6_RESERVED_11_8_SHIFT (8U)
33340/*! RESERVED_11_8 - Reserved. Return zeroes on reads.
33341 */
33342#define DDRPHY_DX7GSR6_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_11_8_MASK)
33343#define DDRPHY_DX7GSR6_RESERVED_15_12_MASK (0xF000U)
33344#define DDRPHY_DX7GSR6_RESERVED_15_12_SHIFT (12U)
33345/*! RESERVED_15_12 - Reserved. Return zeroes on reads.
33346 */
33347#define DDRPHY_DX7GSR6_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_15_12_MASK)
33348#define DDRPHY_DX7GSR6_RESERVED_19_15_MASK (0xF0000U)
33349#define DDRPHY_DX7GSR6_RESERVED_19_15_SHIFT (16U)
33350/*! RESERVED_19_15 - Reserved. Return zeroes on reads.
33351 */
33352#define DDRPHY_DX7GSR6_RESERVED_19_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_19_15_MASK)
33353#define DDRPHY_DX7GSR6_RESERVED_23_20_MASK (0xF00000U)
33354#define DDRPHY_DX7GSR6_RESERVED_23_20_SHIFT (20U)
33355/*! RESERVED_23_20 - Reserved. Return zeroes on reads.
33356 */
33357#define DDRPHY_DX7GSR6_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_23_20_MASK)
33358#define DDRPHY_DX7GSR6_RESERVED_31_24_MASK (0xFF000000U)
33359#define DDRPHY_DX7GSR6_RESERVED_31_24_SHIFT (24U)
33360/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
33361 */
33362#define DDRPHY_DX7GSR6_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX7GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX7GSR6_RESERVED_31_24_MASK)
33363/*! @} */
33364
33365/*! @name DX8GCR0 - DATX8 n General Configuration Register 0 */
33366/*! @{ */
33367#define DDRPHY_DX8GCR0_RESERVED_1_0_MASK (0x3U)
33368#define DDRPHY_DX8GCR0_RESERVED_1_0_SHIFT (0U)
33369/*! RESERVED_1_0 - Reserved. Return zeroes on reads.
33370 */
33371#define DDRPHY_DX8GCR0_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_RESERVED_1_0_SHIFT)) & DDRPHY_DX8GCR0_RESERVED_1_0_MASK)
33372#define DDRPHY_DX8GCR0_DQSGOE_MASK (0x4U)
33373#define DDRPHY_DX8GCR0_DQSGOE_SHIFT (2U)
33374/*! DQSGOE - DQSG Output Enable
33375 */
33376#define DDRPHY_DX8GCR0_DQSGOE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSGOE_SHIFT)) & DDRPHY_DX8GCR0_DQSGOE_MASK)
33377#define DDRPHY_DX8GCR0_DQSGODT_MASK (0x8U)
33378#define DDRPHY_DX8GCR0_DQSGODT_SHIFT (3U)
33379/*! DQSGODT - DQSG On-Die Termination
33380 */
33381#define DDRPHY_DX8GCR0_DQSGODT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSGODT_SHIFT)) & DDRPHY_DX8GCR0_DQSGODT_MASK)
33382#define DDRPHY_DX8GCR0_RESERVED_4_MASK (0x10U)
33383#define DDRPHY_DX8GCR0_RESERVED_4_SHIFT (4U)
33384/*! RESERVED_4 - Reserved. Return zeroes on reads.
33385 */
33386#define DDRPHY_DX8GCR0_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_RESERVED_4_SHIFT)) & DDRPHY_DX8GCR0_RESERVED_4_MASK)
33387#define DDRPHY_DX8GCR0_DQSGPDR_MASK (0x20U)
33388#define DDRPHY_DX8GCR0_DQSGPDR_SHIFT (5U)
33389/*! DQSGPDR - DQSG Power Down Receiver
33390 */
33391#define DDRPHY_DX8GCR0_DQSGPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSGPDR_SHIFT)) & DDRPHY_DX8GCR0_DQSGPDR_MASK)
33392#define DDRPHY_DX8GCR0_DQSRPD_MASK (0x40U)
33393#define DDRPHY_DX8GCR0_DQSRPD_SHIFT (6U)
33394/*! DQSRPD - DQSR Power Down
33395 */
33396#define DDRPHY_DX8GCR0_DQSRPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSRPD_SHIFT)) & DDRPHY_DX8GCR0_DQSRPD_MASK)
33397#define DDRPHY_DX8GCR0_CPDRSHFT_MASK (0x180U)
33398#define DDRPHY_DX8GCR0_CPDRSHFT_SHIFT (7U)
33399/*! CPDRSHFT - Configurable PDR Phase Shift
33400 */
33401#define DDRPHY_DX8GCR0_CPDRSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_CPDRSHFT_SHIFT)) & DDRPHY_DX8GCR0_CPDRSHFT_MASK)
33402#define DDRPHY_DX8GCR0_RTTOH_MASK (0x600U)
33403#define DDRPHY_DX8GCR0_RTTOH_SHIFT (9U)
33404/*! RTTOH - RTT Output Hold
33405 */
33406#define DDRPHY_DX8GCR0_RTTOH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_RTTOH_SHIFT)) & DDRPHY_DX8GCR0_RTTOH_MASK)
33407#define DDRPHY_DX8GCR0_RTTOAL_MASK (0x800U)
33408#define DDRPHY_DX8GCR0_RTTOAL_SHIFT (11U)
33409/*! RTTOAL - RTT On Additive Latency
33410 */
33411#define DDRPHY_DX8GCR0_RTTOAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_RTTOAL_SHIFT)) & DDRPHY_DX8GCR0_RTTOAL_MASK)
33412#define DDRPHY_DX8GCR0_DQSSEPDR_MASK (0x1000U)
33413#define DDRPHY_DX8GCR0_DQSSEPDR_SHIFT (12U)
33414/*! DQSSEPDR - DQSSE Power Down Receiver
33415 */
33416#define DDRPHY_DX8GCR0_DQSSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSSEPDR_SHIFT)) & DDRPHY_DX8GCR0_DQSSEPDR_MASK)
33417#define DDRPHY_DX8GCR0_DQSNSEPDR_MASK (0x2000U)
33418#define DDRPHY_DX8GCR0_DQSNSEPDR_SHIFT (13U)
33419/*! DQSNSEPDR - DQSNSE Power Down Receiver
33420 */
33421#define DDRPHY_DX8GCR0_DQSNSEPDR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSNSEPDR_SHIFT)) & DDRPHY_DX8GCR0_DQSNSEPDR_MASK)
33422#define DDRPHY_DX8GCR0_RESERVED_19_14_MASK (0xFC000U)
33423#define DDRPHY_DX8GCR0_RESERVED_19_14_SHIFT (14U)
33424/*! RESERVED_19_14 - Reserved. Return zeroes on reads.
33425 */
33426#define DDRPHY_DX8GCR0_RESERVED_19_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_RESERVED_19_14_SHIFT)) & DDRPHY_DX8GCR0_RESERVED_19_14_MASK)
33427#define DDRPHY_DX8GCR0_RDDLY_MASK (0xF00000U)
33428#define DDRPHY_DX8GCR0_RDDLY_SHIFT (20U)
33429/*! RDDLY - Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
33430 */
33431#define DDRPHY_DX8GCR0_RDDLY(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_RDDLY_SHIFT)) & DDRPHY_DX8GCR0_RDDLY_MASK)
33432#define DDRPHY_DX8GCR0_DQSDCC_MASK (0xF000000U)
33433#define DDRPHY_DX8GCR0_DQSDCC_SHIFT (24U)
33434/*! DQSDCC - DQS Duty Cycle Correction
33435 */
33436#define DDRPHY_DX8GCR0_DQSDCC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_DQSDCC_SHIFT)) & DDRPHY_DX8GCR0_DQSDCC_MASK)
33437#define DDRPHY_DX8GCR0_CODTSHFT_MASK (0x30000000U)
33438#define DDRPHY_DX8GCR0_CODTSHFT_SHIFT (28U)
33439/*! CODTSHFT - Configurable ODT(TE) Phase Shift
33440 */
33441#define DDRPHY_DX8GCR0_CODTSHFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_CODTSHFT_SHIFT)) & DDRPHY_DX8GCR0_CODTSHFT_MASK)
33442#define DDRPHY_DX8GCR0_MDLEN_MASK (0x40000000U)
33443#define DDRPHY_DX8GCR0_MDLEN_SHIFT (30U)
33444/*! MDLEN - Master Delay Line Enable
33445 */
33446#define DDRPHY_DX8GCR0_MDLEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_MDLEN_SHIFT)) & DDRPHY_DX8GCR0_MDLEN_MASK)
33447#define DDRPHY_DX8GCR0_CALBYP_MASK (0x80000000U)
33448#define DDRPHY_DX8GCR0_CALBYP_SHIFT (31U)
33449/*! CALBYP - Calibration Bypass
33450 */
33451#define DDRPHY_DX8GCR0_CALBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR0_CALBYP_SHIFT)) & DDRPHY_DX8GCR0_CALBYP_MASK)
33452/*! @} */
33453
33454/*! @name DX8GCR1 - DATX8 n General Configuration Register 1 */
33455/*! @{ */
33456#define DDRPHY_DX8GCR1_DQEN_MASK (0xFFU)
33457#define DDRPHY_DX8GCR1_DQEN_SHIFT (0U)
33458/*! DQEN - Enables DQ corresponding to each bit in a byte
33459 */
33460#define DDRPHY_DX8GCR1_DQEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_DQEN_SHIFT)) & DDRPHY_DX8GCR1_DQEN_MASK)
33461#define DDRPHY_DX8GCR1_DMEN_MASK (0x100U)
33462#define DDRPHY_DX8GCR1_DMEN_SHIFT (8U)
33463/*! DMEN - Enables DM pin in a byte lane
33464 */
33465#define DDRPHY_DX8GCR1_DMEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_DMEN_SHIFT)) & DDRPHY_DX8GCR1_DMEN_MASK)
33466#define DDRPHY_DX8GCR1_DSEN_MASK (0x200U)
33467#define DDRPHY_DX8GCR1_DSEN_SHIFT (9U)
33468/*! DSEN - Enables Write Data strobe in a byte lane
33469 */
33470#define DDRPHY_DX8GCR1_DSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_DSEN_SHIFT)) & DDRPHY_DX8GCR1_DSEN_MASK)
33471#define DDRPHY_DX8GCR1_TEEN_MASK (0x400U)
33472#define DDRPHY_DX8GCR1_TEEN_SHIFT (10U)
33473/*! TEEN - Enables ODT/TE in a byte lane
33474 */
33475#define DDRPHY_DX8GCR1_TEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_TEEN_SHIFT)) & DDRPHY_DX8GCR1_TEEN_MASK)
33476#define DDRPHY_DX8GCR1_PDREN_MASK (0x800U)
33477#define DDRPHY_DX8GCR1_PDREN_SHIFT (11U)
33478/*! PDREN - Enables PDR in a byte lane
33479 */
33480#define DDRPHY_DX8GCR1_PDREN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_PDREN_SHIFT)) & DDRPHY_DX8GCR1_PDREN_MASK)
33481#define DDRPHY_DX8GCR1_OEEN_MASK (0x1000U)
33482#define DDRPHY_DX8GCR1_OEEN_SHIFT (12U)
33483/*! OEEN - Enables Read Data Strobe in a byte lane
33484 */
33485#define DDRPHY_DX8GCR1_OEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_OEEN_SHIFT)) & DDRPHY_DX8GCR1_OEEN_MASK)
33486#define DDRPHY_DX8GCR1_QSSEL_MASK (0x2000U)
33487#define DDRPHY_DX8GCR1_QSSEL_SHIFT (13U)
33488/*! QSSEL - Select the delayed or non-delayed read data strobe
33489 */
33490#define DDRPHY_DX8GCR1_QSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_QSSEL_SHIFT)) & DDRPHY_DX8GCR1_QSSEL_MASK)
33491#define DDRPHY_DX8GCR1_QSNSEL_MASK (0x4000U)
33492#define DDRPHY_DX8GCR1_QSNSEL_SHIFT (14U)
33493/*! QSNSEL - Select the delayed or non-delayed read data strobe #
33494 */
33495#define DDRPHY_DX8GCR1_QSNSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_QSNSEL_SHIFT)) & DDRPHY_DX8GCR1_QSNSEL_MASK)
33496#define DDRPHY_DX8GCR1_RESERVED_15_MASK (0x8000U)
33497#define DDRPHY_DX8GCR1_RESERVED_15_SHIFT (15U)
33498/*! RESERVED_15 - Reserved. Returns zeroes on reads.
33499 */
33500#define DDRPHY_DX8GCR1_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_RESERVED_15_SHIFT)) & DDRPHY_DX8GCR1_RESERVED_15_MASK)
33501#define DDRPHY_DX8GCR1_DXPDRMODE_MASK (0xFFFF0000U)
33502#define DDRPHY_DX8GCR1_DXPDRMODE_SHIFT (16U)
33503/*! DXPDRMODE - Enables the PDR mode for DQ[7:0]
33504 */
33505#define DDRPHY_DX8GCR1_DXPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR1_DXPDRMODE_SHIFT)) & DDRPHY_DX8GCR1_DXPDRMODE_MASK)
33506/*! @} */
33507
33508/*! @name DX8GCR2 - DATX8 n General Configuration Register 2 */
33509/*! @{ */
33510#define DDRPHY_DX8GCR2_DXTEMODE_MASK (0xFFFFU)
33511#define DDRPHY_DX8GCR2_DXTEMODE_SHIFT (0U)
33512/*! DXTEMODE - Enables the TE (ODT) mode values for DQ[7:0]
33513 */
33514#define DDRPHY_DX8GCR2_DXTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR2_DXTEMODE_SHIFT)) & DDRPHY_DX8GCR2_DXTEMODE_MASK)
33515#define DDRPHY_DX8GCR2_DXOEMODE_MASK (0xFFFF0000U)
33516#define DDRPHY_DX8GCR2_DXOEMODE_SHIFT (16U)
33517/*! DXOEMODE - Enables the OE mode values for DQ[7:0]
33518 */
33519#define DDRPHY_DX8GCR2_DXOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR2_DXOEMODE_SHIFT)) & DDRPHY_DX8GCR2_DXOEMODE_MASK)
33520/*! @} */
33521
33522/*! @name DX8GCR3 - DATX8 n General Configuration Register 3 */
33523/*! @{ */
33524#define DDRPHY_DX8GCR3_WDMBVT_MASK (0x1U)
33525#define DDRPHY_DX8GCR3_WDMBVT_SHIFT (0U)
33526/*! WDMBVT - Write Data Mask BDL VT Compensation
33527 */
33528#define DDRPHY_DX8GCR3_WDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_WDMBVT_SHIFT)) & DDRPHY_DX8GCR3_WDMBVT_MASK)
33529#define DDRPHY_DX8GCR3_RDMBVT_MASK (0x2U)
33530#define DDRPHY_DX8GCR3_RDMBVT_SHIFT (1U)
33531/*! RDMBVT - Read Data Mask BDL VT Compensation
33532 */
33533#define DDRPHY_DX8GCR3_RDMBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_RDMBVT_SHIFT)) & DDRPHY_DX8GCR3_RDMBVT_MASK)
33534#define DDRPHY_DX8GCR3_DSPDRMODE_MASK (0xCU)
33535#define DDRPHY_DX8GCR3_DSPDRMODE_SHIFT (2U)
33536/*! DSPDRMODE - Enables the PDR mode values for DQS.
33537 */
33538#define DDRPHY_DX8GCR3_DSPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DSPDRMODE_SHIFT)) & DDRPHY_DX8GCR3_DSPDRMODE_MASK)
33539#define DDRPHY_DX8GCR3_DSTEMODE_MASK (0x30U)
33540#define DDRPHY_DX8GCR3_DSTEMODE_SHIFT (4U)
33541/*! DSTEMODE - Enables the TE mode values for DQS.
33542 */
33543#define DDRPHY_DX8GCR3_DSTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DSTEMODE_SHIFT)) & DDRPHY_DX8GCR3_DSTEMODE_MASK)
33544#define DDRPHY_DX8GCR3_DSOEMODE_MASK (0xC0U)
33545#define DDRPHY_DX8GCR3_DSOEMODE_SHIFT (6U)
33546/*! DSOEMODE - Enables the OE mode values for DQS.
33547 */
33548#define DDRPHY_DX8GCR3_DSOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DSOEMODE_SHIFT)) & DDRPHY_DX8GCR3_DSOEMODE_MASK)
33549#define DDRPHY_DX8GCR3_WDSBVT_MASK (0x100U)
33550#define DDRPHY_DX8GCR3_WDSBVT_SHIFT (8U)
33551/*! WDSBVT - Write Data Strobe BDL VT Compensation
33552 */
33553#define DDRPHY_DX8GCR3_WDSBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_WDSBVT_SHIFT)) & DDRPHY_DX8GCR3_WDSBVT_MASK)
33554#define DDRPHY_DX8GCR3_RESERVED_9_MASK (0x200U)
33555#define DDRPHY_DX8GCR3_RESERVED_9_SHIFT (9U)
33556/*! RESERVED_9 - Reserved. Returns zeroes on reads.
33557 */
33558#define DDRPHY_DX8GCR3_RESERVED_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_RESERVED_9_SHIFT)) & DDRPHY_DX8GCR3_RESERVED_9_MASK)
33559#define DDRPHY_DX8GCR3_DMPDRMODE_MASK (0xC00U)
33560#define DDRPHY_DX8GCR3_DMPDRMODE_SHIFT (10U)
33561/*! DMPDRMODE - Enables the PDR mode values for DM.
33562 */
33563#define DDRPHY_DX8GCR3_DMPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DMPDRMODE_SHIFT)) & DDRPHY_DX8GCR3_DMPDRMODE_MASK)
33564#define DDRPHY_DX8GCR3_DMTEMODE_MASK (0x3000U)
33565#define DDRPHY_DX8GCR3_DMTEMODE_SHIFT (12U)
33566/*! DMTEMODE - Enables the TE mode values for DM.
33567 */
33568#define DDRPHY_DX8GCR3_DMTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DMTEMODE_SHIFT)) & DDRPHY_DX8GCR3_DMTEMODE_MASK)
33569#define DDRPHY_DX8GCR3_DMOEMODE_MASK (0xC000U)
33570#define DDRPHY_DX8GCR3_DMOEMODE_SHIFT (14U)
33571/*! DMOEMODE - Enables the OE mode values for DM.
33572 */
33573#define DDRPHY_DX8GCR3_DMOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DMOEMODE_SHIFT)) & DDRPHY_DX8GCR3_DMOEMODE_MASK)
33574#define DDRPHY_DX8GCR3_DSNPDRMODE_MASK (0x30000U)
33575#define DDRPHY_DX8GCR3_DSNPDRMODE_SHIFT (16U)
33576/*! DSNPDRMODE - Enables the PDR mode for DQS
33577 */
33578#define DDRPHY_DX8GCR3_DSNPDRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DSNPDRMODE_SHIFT)) & DDRPHY_DX8GCR3_DSNPDRMODE_MASK)
33579#define DDRPHY_DX8GCR3_DSNTEMODE_MASK (0xC0000U)
33580#define DDRPHY_DX8GCR3_DSNTEMODE_SHIFT (18U)
33581/*! DSNTEMODE - Enables the TE mode for DQS
33582 */
33583#define DDRPHY_DX8GCR3_DSNTEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DSNTEMODE_SHIFT)) & DDRPHY_DX8GCR3_DSNTEMODE_MASK)
33584#define DDRPHY_DX8GCR3_DSNOEMODE_MASK (0x300000U)
33585#define DDRPHY_DX8GCR3_DSNOEMODE_SHIFT (20U)
33586/*! DSNOEMODE - Enables the OE mode for DQs
33587 */
33588#define DDRPHY_DX8GCR3_DSNOEMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_DSNOEMODE_SHIFT)) & DDRPHY_DX8GCR3_DSNOEMODE_MASK)
33589#define DDRPHY_DX8GCR3_PDRBVT_MASK (0x400000U)
33590#define DDRPHY_DX8GCR3_PDRBVT_SHIFT (22U)
33591/*! PDRBVT - Power Down Receiver BDL VT Compensation
33592 */
33593#define DDRPHY_DX8GCR3_PDRBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_PDRBVT_SHIFT)) & DDRPHY_DX8GCR3_PDRBVT_MASK)
33594#define DDRPHY_DX8GCR3_RGSLVT_MASK (0x800000U)
33595#define DDRPHY_DX8GCR3_RGSLVT_SHIFT (23U)
33596/*! RGSLVT - Read DQS Gating Status LCDL Delay VT Compensation
33597 */
33598#define DDRPHY_DX8GCR3_RGSLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_RGSLVT_SHIFT)) & DDRPHY_DX8GCR3_RGSLVT_MASK)
33599#define DDRPHY_DX8GCR3_WLLVT_MASK (0x1000000U)
33600#define DDRPHY_DX8GCR3_WLLVT_SHIFT (24U)
33601/*! WLLVT - Write Leveling LCDL Delay VT Compensation
33602 */
33603#define DDRPHY_DX8GCR3_WLLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_WLLVT_SHIFT)) & DDRPHY_DX8GCR3_WLLVT_MASK)
33604#define DDRPHY_DX8GCR3_WDLVT_MASK (0x2000000U)
33605#define DDRPHY_DX8GCR3_WDLVT_SHIFT (25U)
33606/*! WDLVT - Write DQ LCDL Delay VT Compensation
33607 */
33608#define DDRPHY_DX8GCR3_WDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_WDLVT_SHIFT)) & DDRPHY_DX8GCR3_WDLVT_MASK)
33609#define DDRPHY_DX8GCR3_RDLVT_MASK (0x4000000U)
33610#define DDRPHY_DX8GCR3_RDLVT_SHIFT (26U)
33611/*! RDLVT - Read DQS LCDL Delay VT Compensation
33612 */
33613#define DDRPHY_DX8GCR3_RDLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_RDLVT_SHIFT)) & DDRPHY_DX8GCR3_RDLVT_MASK)
33614#define DDRPHY_DX8GCR3_RGLVT_MASK (0x8000000U)
33615#define DDRPHY_DX8GCR3_RGLVT_SHIFT (27U)
33616/*! RGLVT - Read DQS Gating LCDL Delay VT Compensation
33617 */
33618#define DDRPHY_DX8GCR3_RGLVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_RGLVT_SHIFT)) & DDRPHY_DX8GCR3_RGLVT_MASK)
33619#define DDRPHY_DX8GCR3_WDBVT_MASK (0x10000000U)
33620#define DDRPHY_DX8GCR3_WDBVT_SHIFT (28U)
33621/*! WDBVT - Write Data BDL VT Compensation
33622 */
33623#define DDRPHY_DX8GCR3_WDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_WDBVT_SHIFT)) & DDRPHY_DX8GCR3_WDBVT_MASK)
33624#define DDRPHY_DX8GCR3_RDBVT_MASK (0x20000000U)
33625#define DDRPHY_DX8GCR3_RDBVT_SHIFT (29U)
33626/*! RDBVT - Read Data BDL VT Compensation
33627 */
33628#define DDRPHY_DX8GCR3_RDBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_RDBVT_SHIFT)) & DDRPHY_DX8GCR3_RDBVT_MASK)
33629#define DDRPHY_DX8GCR3_TEBVT_MASK (0x40000000U)
33630#define DDRPHY_DX8GCR3_TEBVT_SHIFT (30U)
33631/*! TEBVT - Termination Enable BDL VT Compensation
33632 */
33633#define DDRPHY_DX8GCR3_TEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_TEBVT_SHIFT)) & DDRPHY_DX8GCR3_TEBVT_MASK)
33634#define DDRPHY_DX8GCR3_OEBVT_MASK (0x80000000U)
33635#define DDRPHY_DX8GCR3_OEBVT_SHIFT (31U)
33636/*! OEBVT - Output Enable BDL VT Compensation
33637 */
33638#define DDRPHY_DX8GCR3_OEBVT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR3_OEBVT_SHIFT)) & DDRPHY_DX8GCR3_OEBVT_MASK)
33639/*! @} */
33640
33641/*! @name DX8GCR4 - DATX8 n General Configuration Register 4 */
33642/*! @{ */
33643#define DDRPHY_DX8GCR4_DXREFIMON_MASK (0x3U)
33644#define DDRPHY_DX8GCR4_DXREFIMON_SHIFT (0U)
33645/*! DXREFIMON - VRMON control for DQ IO (Single Ended) buffers of a byte lane.
33646 */
33647#define DDRPHY_DX8GCR4_DXREFIMON(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFIMON_SHIFT)) & DDRPHY_DX8GCR4_DXREFIMON_MASK)
33648#define DDRPHY_DX8GCR4_DXREFIEN_MASK (0x3CU)
33649#define DDRPHY_DX8GCR4_DXREFIEN_SHIFT (2U)
33650/*! DXREFIEN - VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
33651 */
33652#define DDRPHY_DX8GCR4_DXREFIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFIEN_SHIFT)) & DDRPHY_DX8GCR4_DXREFIEN_MASK)
33653#define DDRPHY_DX8GCR4_RESERVED_7_6_MASK (0xC0U)
33654#define DDRPHY_DX8GCR4_RESERVED_7_6_SHIFT (6U)
33655/*! RESERVED_7_6 - Reserved. Returns zeros on reads.
33656 */
33657#define DDRPHY_DX8GCR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX8GCR4_RESERVED_7_6_MASK)
33658#define DDRPHY_DX8GCR4_DXREFSSEL_MASK (0x7F00U)
33659#define DDRPHY_DX8GCR4_DXREFSSEL_SHIFT (8U)
33660/*! DXREFSSEL - Byte Lane Single-End VREF Select
33661 */
33662#define DDRPHY_DX8GCR4_DXREFSSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFSSEL_SHIFT)) & DDRPHY_DX8GCR4_DXREFSSEL_MASK)
33663#define DDRPHY_DX8GCR4_DXREFSSELRANGE_MASK (0x8000U)
33664#define DDRPHY_DX8GCR4_DXREFSSELRANGE_SHIFT (15U)
33665/*! DXREFSSELRANGE - Single ended VREF generator REFSEL range select
33666 */
33667#define DDRPHY_DX8GCR4_DXREFSSELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFSSELRANGE_SHIFT)) & DDRPHY_DX8GCR4_DXREFSSELRANGE_MASK)
33668#define DDRPHY_DX8GCR4_DXREFESEL_MASK (0x7F0000U)
33669#define DDRPHY_DX8GCR4_DXREFESEL_SHIFT (16U)
33670/*! DXREFESEL - Byte Lane External VREF Select
33671 */
33672#define DDRPHY_DX8GCR4_DXREFESEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFESEL_SHIFT)) & DDRPHY_DX8GCR4_DXREFESEL_MASK)
33673#define DDRPHY_DX8GCR4_DXREFESELRANGE_MASK (0x800000U)
33674#define DDRPHY_DX8GCR4_DXREFESELRANGE_SHIFT (23U)
33675/*! DXREFESELRANGE - External VREF generator REFSEL range select
33676 */
33677#define DDRPHY_DX8GCR4_DXREFESELRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFESELRANGE_SHIFT)) & DDRPHY_DX8GCR4_DXREFESELRANGE_MASK)
33678#define DDRPHY_DX8GCR4_RESERVED_24_MASK (0x1000000U)
33679#define DDRPHY_DX8GCR4_RESERVED_24_SHIFT (24U)
33680/*! RESERVED_24 - Reserved. Returns zeros on reads.
33681 */
33682#define DDRPHY_DX8GCR4_RESERVED_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_RESERVED_24_SHIFT)) & DDRPHY_DX8GCR4_RESERVED_24_MASK)
33683#define DDRPHY_DX8GCR4_DXREFSEN_MASK (0x2000000U)
33684#define DDRPHY_DX8GCR4_DXREFSEN_SHIFT (25U)
33685/*! DXREFSEN - Byte Lane Single-End VREF Enable
33686 */
33687#define DDRPHY_DX8GCR4_DXREFSEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFSEN_SHIFT)) & DDRPHY_DX8GCR4_DXREFSEN_MASK)
33688#define DDRPHY_DX8GCR4_DXREFEEN_MASK (0xC000000U)
33689#define DDRPHY_DX8GCR4_DXREFEEN_SHIFT (26U)
33690/*! DXREFEEN - Byte Lane Internal VREF Enable
33691 */
33692#define DDRPHY_DX8GCR4_DXREFEEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFEEN_SHIFT)) & DDRPHY_DX8GCR4_DXREFEEN_MASK)
33693#define DDRPHY_DX8GCR4_DXREFPEN_MASK (0x10000000U)
33694#define DDRPHY_DX8GCR4_DXREFPEN_SHIFT (28U)
33695/*! DXREFPEN - Byte Lane VREF Pad Enable
33696 */
33697#define DDRPHY_DX8GCR4_DXREFPEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_DXREFPEN_SHIFT)) & DDRPHY_DX8GCR4_DXREFPEN_MASK)
33698#define DDRPHY_DX8GCR4_RESERVED_31_29_MASK (0xE0000000U)
33699#define DDRPHY_DX8GCR4_RESERVED_31_29_SHIFT (29U)
33700/*! RESERVED_31_29 - Byte lane VREF IOM (Used only by D4MU IOs)
33701 */
33702#define DDRPHY_DX8GCR4_RESERVED_31_29(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR4_RESERVED_31_29_SHIFT)) & DDRPHY_DX8GCR4_RESERVED_31_29_MASK)
33703/*! @} */
33704
33705/*! @name DX8GCR5 - DATX8 n General Configuration Register 5 */
33706/*! @{ */
33707#define DDRPHY_DX8GCR5_DXREFISELR0_MASK (0x7FU)
33708#define DDRPHY_DX8GCR5_DXREFISELR0_SHIFT (0U)
33709/*! DXREFISELR0 - Byte Lane internal VREF Select for Rank 0
33710 */
33711#define DDRPHY_DX8GCR5_DXREFISELR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_DXREFISELR0_SHIFT)) & DDRPHY_DX8GCR5_DXREFISELR0_MASK)
33712#define DDRPHY_DX8GCR5_RESERVED_7_MASK (0x80U)
33713#define DDRPHY_DX8GCR5_RESERVED_7_SHIFT (7U)
33714/*! RESERVED_7 - Reserved. Returns zeros on reads.
33715 */
33716#define DDRPHY_DX8GCR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_RESERVED_7_SHIFT)) & DDRPHY_DX8GCR5_RESERVED_7_MASK)
33717#define DDRPHY_DX8GCR5_DXREFISELR1_MASK (0x7F00U)
33718#define DDRPHY_DX8GCR5_DXREFISELR1_SHIFT (8U)
33719/*! DXREFISELR1 - Byte Lane internal VREF Select for Rank 1
33720 */
33721#define DDRPHY_DX8GCR5_DXREFISELR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_DXREFISELR1_SHIFT)) & DDRPHY_DX8GCR5_DXREFISELR1_MASK)
33722#define DDRPHY_DX8GCR5_RESERVED_15_MASK (0x8000U)
33723#define DDRPHY_DX8GCR5_RESERVED_15_SHIFT (15U)
33724/*! RESERVED_15 - Reserved. Returns zeros on reads.
33725 */
33726#define DDRPHY_DX8GCR5_RESERVED_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_RESERVED_15_SHIFT)) & DDRPHY_DX8GCR5_RESERVED_15_MASK)
33727#define DDRPHY_DX8GCR5_DXREFISELR2_MASK (0x7F0000U)
33728#define DDRPHY_DX8GCR5_DXREFISELR2_SHIFT (16U)
33729/*! DXREFISELR2 - Byte Lane internal VREF Select for Rank 2
33730 */
33731#define DDRPHY_DX8GCR5_DXREFISELR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_DXREFISELR2_SHIFT)) & DDRPHY_DX8GCR5_DXREFISELR2_MASK)
33732#define DDRPHY_DX8GCR5_RESERVED_23_MASK (0x800000U)
33733#define DDRPHY_DX8GCR5_RESERVED_23_SHIFT (23U)
33734/*! RESERVED_23 - Reserved. Returns zeros on reads.
33735 */
33736#define DDRPHY_DX8GCR5_RESERVED_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_RESERVED_23_SHIFT)) & DDRPHY_DX8GCR5_RESERVED_23_MASK)
33737#define DDRPHY_DX8GCR5_DXREFISELR3_MASK (0x7F000000U)
33738#define DDRPHY_DX8GCR5_DXREFISELR3_SHIFT (24U)
33739/*! DXREFISELR3 - Byte Lane internal VREF Select for Rank 3
33740 */
33741#define DDRPHY_DX8GCR5_DXREFISELR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_DXREFISELR3_SHIFT)) & DDRPHY_DX8GCR5_DXREFISELR3_MASK)
33742#define DDRPHY_DX8GCR5_RESERVED_31_MASK (0x80000000U)
33743#define DDRPHY_DX8GCR5_RESERVED_31_SHIFT (31U)
33744/*! RESERVED_31 - Reserved. Returns zeros on reads.
33745 */
33746#define DDRPHY_DX8GCR5_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR5_RESERVED_31_SHIFT)) & DDRPHY_DX8GCR5_RESERVED_31_MASK)
33747/*! @} */
33748
33749/*! @name DX8GCR6 - DATX8 n General Configuration Register 6 */
33750/*! @{ */
33751#define DDRPHY_DX8GCR6_DXDQVREFR0_MASK (0x3FU)
33752#define DDRPHY_DX8GCR6_DXDQVREFR0_SHIFT (0U)
33753/*! DXDQVREFR0 - DRAM DQ VREF Select for Rank0
33754 */
33755#define DDRPHY_DX8GCR6_DXDQVREFR0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_DXDQVREFR0_SHIFT)) & DDRPHY_DX8GCR6_DXDQVREFR0_MASK)
33756#define DDRPHY_DX8GCR6_RESERVED_7_6_MASK (0xC0U)
33757#define DDRPHY_DX8GCR6_RESERVED_7_6_SHIFT (6U)
33758/*! RESERVED_7_6 - Reserved. Returns zeros on reads.
33759 */
33760#define DDRPHY_DX8GCR6_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_RESERVED_7_6_SHIFT)) & DDRPHY_DX8GCR6_RESERVED_7_6_MASK)
33761#define DDRPHY_DX8GCR6_DXDQVREFR1_MASK (0x3F00U)
33762#define DDRPHY_DX8GCR6_DXDQVREFR1_SHIFT (8U)
33763/*! DXDQVREFR1 - DRAM DQ VREF Select for Rank1
33764 */
33765#define DDRPHY_DX8GCR6_DXDQVREFR1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_DXDQVREFR1_SHIFT)) & DDRPHY_DX8GCR6_DXDQVREFR1_MASK)
33766#define DDRPHY_DX8GCR6_RESERVED_15_14_MASK (0xC000U)
33767#define DDRPHY_DX8GCR6_RESERVED_15_14_SHIFT (14U)
33768/*! RESERVED_15_14 - Reserved. Returns zeros on reads.
33769 */
33770#define DDRPHY_DX8GCR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX8GCR6_RESERVED_15_14_MASK)
33771#define DDRPHY_DX8GCR6_DXDQVREFR2_MASK (0x3F0000U)
33772#define DDRPHY_DX8GCR6_DXDQVREFR2_SHIFT (16U)
33773/*! DXDQVREFR2 - DRAM DQ VREF Select for Rank2
33774 */
33775#define DDRPHY_DX8GCR6_DXDQVREFR2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_DXDQVREFR2_SHIFT)) & DDRPHY_DX8GCR6_DXDQVREFR2_MASK)
33776#define DDRPHY_DX8GCR6_RESERVED_23_22_MASK (0xC00000U)
33777#define DDRPHY_DX8GCR6_RESERVED_23_22_SHIFT (22U)
33778/*! RESERVED_23_22 - Reserved. Returns zeros on reads.
33779 */
33780#define DDRPHY_DX8GCR6_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_RESERVED_23_22_SHIFT)) & DDRPHY_DX8GCR6_RESERVED_23_22_MASK)
33781#define DDRPHY_DX8GCR6_DXDQVREFR3_MASK (0x3F000000U)
33782#define DDRPHY_DX8GCR6_DXDQVREFR3_SHIFT (24U)
33783/*! DXDQVREFR3 - DRAM DQ VREF Select for Rank3
33784 */
33785#define DDRPHY_DX8GCR6_DXDQVREFR3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_DXDQVREFR3_SHIFT)) & DDRPHY_DX8GCR6_DXDQVREFR3_MASK)
33786#define DDRPHY_DX8GCR6_RESERVED_31_30_MASK (0xC0000000U)
33787#define DDRPHY_DX8GCR6_RESERVED_31_30_SHIFT (30U)
33788/*! RESERVED_31_30 - Reserved. Returns zeros on reads.
33789 */
33790#define DDRPHY_DX8GCR6_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR6_RESERVED_31_30_SHIFT)) & DDRPHY_DX8GCR6_RESERVED_31_30_MASK)
33791/*! @} */
33792
33793/*! @name DX8GCR7 - DATX8 n General Configuration Register 7 */
33794/*! @{ */
33795#define DDRPHY_DX8GCR7_DCALSVAL_MASK (0x1FFU)
33796#define DDRPHY_DX8GCR7_DCALSVAL_SHIFT (0U)
33797/*! DCALSVAL - DDL Calibration Starting Value
33798 */
33799#define DDRPHY_DX8GCR7_DCALSVAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR7_DCALSVAL_SHIFT)) & DDRPHY_DX8GCR7_DCALSVAL_MASK)
33800#define DDRPHY_DX8GCR7_DCALTYPE_MASK (0x200U)
33801#define DDRPHY_DX8GCR7_DCALTYPE_SHIFT (9U)
33802/*! DCALTYPE - DDL Calibration Type
33803 */
33804#define DDRPHY_DX8GCR7_DCALTYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR7_DCALTYPE_SHIFT)) & DDRPHY_DX8GCR7_DCALTYPE_MASK)
33805#define DDRPHY_DX8GCR7_RESERVED_17_10_MASK (0x3FC00U)
33806#define DDRPHY_DX8GCR7_RESERVED_17_10_SHIFT (10U)
33807/*! RESERVED_17_10 - Reserved. Caution, do not write to this register field.
33808 */
33809#define DDRPHY_DX8GCR7_RESERVED_17_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR7_RESERVED_17_10_SHIFT)) & DDRPHY_DX8GCR7_RESERVED_17_10_MASK)
33810#define DDRPHY_DX8GCR7_RESERVED_18_MASK (0x40000U)
33811#define DDRPHY_DX8GCR7_RESERVED_18_SHIFT (18U)
33812/*! RESERVED_18 - Reserved. Caution, do not write to this register field.
33813 */
33814#define DDRPHY_DX8GCR7_RESERVED_18(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR7_RESERVED_18_SHIFT)) & DDRPHY_DX8GCR7_RESERVED_18_MASK)
33815#define DDRPHY_DX8GCR7_RESERVED_31_19_MASK (0xFFF80000U)
33816#define DDRPHY_DX8GCR7_RESERVED_31_19_SHIFT (19U)
33817/*! RESERVED_31_19 - Reserved. Caution, do not write to this register field.
33818 */
33819#define DDRPHY_DX8GCR7_RESERVED_31_19(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR7_RESERVED_31_19_SHIFT)) & DDRPHY_DX8GCR7_RESERVED_31_19_MASK)
33820/*! @} */
33821
33822/*! @name DX8GCR8 - DATX8 n General Configuration Register 8 */
33823/*! @{ */
33824#define DDRPHY_DX8GCR8_RESERVED_5_0_MASK (0x3FU)
33825#define DDRPHY_DX8GCR8_RESERVED_5_0_SHIFT (0U)
33826/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
33827 */
33828#define DDRPHY_DX8GCR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_5_0_MASK)
33829#define DDRPHY_DX8GCR8_RESERVED_7_6_MASK (0xC0U)
33830#define DDRPHY_DX8GCR8_RESERVED_7_6_SHIFT (6U)
33831/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
33832 */
33833#define DDRPHY_DX8GCR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_7_6_MASK)
33834#define DDRPHY_DX8GCR8_RESERVED_13_8_MASK (0x3F00U)
33835#define DDRPHY_DX8GCR8_RESERVED_13_8_SHIFT (8U)
33836/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
33837 */
33838#define DDRPHY_DX8GCR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_13_8_MASK)
33839#define DDRPHY_DX8GCR8_RESERVED_15_14_MASK (0xC000U)
33840#define DDRPHY_DX8GCR8_RESERVED_15_14_SHIFT (14U)
33841/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
33842 */
33843#define DDRPHY_DX8GCR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_15_14_MASK)
33844#define DDRPHY_DX8GCR8_RESERVED_21_16_MASK (0x3F0000U)
33845#define DDRPHY_DX8GCR8_RESERVED_21_16_SHIFT (16U)
33846/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
33847 */
33848#define DDRPHY_DX8GCR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_21_16_MASK)
33849#define DDRPHY_DX8GCR8_RESERVED_23_22_MASK (0xC00000U)
33850#define DDRPHY_DX8GCR8_RESERVED_23_22_SHIFT (22U)
33851/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
33852 */
33853#define DDRPHY_DX8GCR8_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_23_22_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_23_22_MASK)
33854#define DDRPHY_DX8GCR8_RESERVED_29_24_MASK (0x3F000000U)
33855#define DDRPHY_DX8GCR8_RESERVED_29_24_SHIFT (24U)
33856/*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
33857 */
33858#define DDRPHY_DX8GCR8_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_29_24_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_29_24_MASK)
33859#define DDRPHY_DX8GCR8_RESERVED_31_30_MASK (0xC0000000U)
33860#define DDRPHY_DX8GCR8_RESERVED_31_30_SHIFT (30U)
33861/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
33862 */
33863#define DDRPHY_DX8GCR8_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR8_RESERVED_31_30_SHIFT)) & DDRPHY_DX8GCR8_RESERVED_31_30_MASK)
33864/*! @} */
33865
33866/*! @name DX8GCR9 - DATX8 n General Configuration Register 9 */
33867/*! @{ */
33868#define DDRPHY_DX8GCR9_RESERVED_5_0_MASK (0x3FU)
33869#define DDRPHY_DX8GCR9_RESERVED_5_0_SHIFT (0U)
33870/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
33871 */
33872#define DDRPHY_DX8GCR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_5_0_MASK)
33873#define DDRPHY_DX8GCR9_RESERVED_7_6_MASK (0xC0U)
33874#define DDRPHY_DX8GCR9_RESERVED_7_6_SHIFT (6U)
33875/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
33876 */
33877#define DDRPHY_DX8GCR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_7_6_MASK)
33878#define DDRPHY_DX8GCR9_RESERVED_13_8_MASK (0x3F00U)
33879#define DDRPHY_DX8GCR9_RESERVED_13_8_SHIFT (8U)
33880/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
33881 */
33882#define DDRPHY_DX8GCR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_13_8_MASK)
33883#define DDRPHY_DX8GCR9_RESERVED_15_14_MASK (0xC000U)
33884#define DDRPHY_DX8GCR9_RESERVED_15_14_SHIFT (14U)
33885/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
33886 */
33887#define DDRPHY_DX8GCR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_15_14_MASK)
33888#define DDRPHY_DX8GCR9_RESERVED_21_16_MASK (0x3F0000U)
33889#define DDRPHY_DX8GCR9_RESERVED_21_16_SHIFT (16U)
33890/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
33891 */
33892#define DDRPHY_DX8GCR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_21_16_MASK)
33893#define DDRPHY_DX8GCR9_RESERVED_23_22_MASK (0xC00000U)
33894#define DDRPHY_DX8GCR9_RESERVED_23_22_SHIFT (22U)
33895/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
33896 */
33897#define DDRPHY_DX8GCR9_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_23_22_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_23_22_MASK)
33898#define DDRPHY_DX8GCR9_RESERVED_29_24_MASK (0x3F000000U)
33899#define DDRPHY_DX8GCR9_RESERVED_29_24_SHIFT (24U)
33900/*! RESERVED_29_24 - Reserved. Caution, do not write to this register field.
33901 */
33902#define DDRPHY_DX8GCR9_RESERVED_29_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_29_24_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_29_24_MASK)
33903#define DDRPHY_DX8GCR9_RESERVED_31_30_MASK (0xC0000000U)
33904#define DDRPHY_DX8GCR9_RESERVED_31_30_SHIFT (30U)
33905/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
33906 */
33907#define DDRPHY_DX8GCR9_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GCR9_RESERVED_31_30_SHIFT)) & DDRPHY_DX8GCR9_RESERVED_31_30_MASK)
33908/*! @} */
33909
33910/*! @name DX8DQMAP0 - DATX8 n DQ/DM Mapping Register 0 */
33911/*! @{ */
33912#define DDRPHY_DX8DQMAP0_DQ0MAP_MASK (0xFU)
33913#define DDRPHY_DX8DQMAP0_DQ0MAP_SHIFT (0U)
33914/*! DQ0MAP - DQ bit 0 DATX8 slice mapping index
33915 */
33916#define DDRPHY_DX8DQMAP0_DQ0MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_DQ0MAP_SHIFT)) & DDRPHY_DX8DQMAP0_DQ0MAP_MASK)
33917#define DDRPHY_DX8DQMAP0_DQ1MAP_MASK (0xF0U)
33918#define DDRPHY_DX8DQMAP0_DQ1MAP_SHIFT (4U)
33919/*! DQ1MAP - DQ bit 1 DATX8 slice mapping index
33920 */
33921#define DDRPHY_DX8DQMAP0_DQ1MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_DQ1MAP_SHIFT)) & DDRPHY_DX8DQMAP0_DQ1MAP_MASK)
33922#define DDRPHY_DX8DQMAP0_DQ2MAP_MASK (0xF00U)
33923#define DDRPHY_DX8DQMAP0_DQ2MAP_SHIFT (8U)
33924/*! DQ2MAP - DQ bit 2 DATX8 slice mapping index
33925 */
33926#define DDRPHY_DX8DQMAP0_DQ2MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_DQ2MAP_SHIFT)) & DDRPHY_DX8DQMAP0_DQ2MAP_MASK)
33927#define DDRPHY_DX8DQMAP0_DQ3MAP_MASK (0xF000U)
33928#define DDRPHY_DX8DQMAP0_DQ3MAP_SHIFT (12U)
33929/*! DQ3MAP - DQ bit 3 DATX8 slice mapping index
33930 */
33931#define DDRPHY_DX8DQMAP0_DQ3MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_DQ3MAP_SHIFT)) & DDRPHY_DX8DQMAP0_DQ3MAP_MASK)
33932#define DDRPHY_DX8DQMAP0_DQ4MAP_MASK (0xF0000U)
33933#define DDRPHY_DX8DQMAP0_DQ4MAP_SHIFT (16U)
33934/*! DQ4MAP - DQ bit 4 DATX8 slice mapping index
33935 */
33936#define DDRPHY_DX8DQMAP0_DQ4MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_DQ4MAP_SHIFT)) & DDRPHY_DX8DQMAP0_DQ4MAP_MASK)
33937#define DDRPHY_DX8DQMAP0_RESERVED_30_20_MASK (0x7FF00000U)
33938#define DDRPHY_DX8DQMAP0_RESERVED_30_20_SHIFT (20U)
33939/*! RESERVED_30_20 - Reserved. Return zeroes on reads.
33940 */
33941#define DDRPHY_DX8DQMAP0_RESERVED_30_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_RESERVED_30_20_SHIFT)) & DDRPHY_DX8DQMAP0_RESERVED_30_20_MASK)
33942#define DDRPHY_DX8DQMAP0_MAPOK_MASK (0x80000000U)
33943#define DDRPHY_DX8DQMAP0_MAPOK_SHIFT (31U)
33944/*! MAPOK - Checksum bit
33945 */
33946#define DDRPHY_DX8DQMAP0_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP0_MAPOK_SHIFT)) & DDRPHY_DX8DQMAP0_MAPOK_MASK)
33947/*! @} */
33948
33949/*! @name DX8DQMAP1 - DATX8 n DQ/DM Mapping Register 1 */
33950/*! @{ */
33951#define DDRPHY_DX8DQMAP1_DQ5MAP_MASK (0xFU)
33952#define DDRPHY_DX8DQMAP1_DQ5MAP_SHIFT (0U)
33953/*! DQ5MAP - DQ bit 5 DATX8 slice mapping index
33954 */
33955#define DDRPHY_DX8DQMAP1_DQ5MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP1_DQ5MAP_SHIFT)) & DDRPHY_DX8DQMAP1_DQ5MAP_MASK)
33956#define DDRPHY_DX8DQMAP1_DQ6MAP_MASK (0xF0U)
33957#define DDRPHY_DX8DQMAP1_DQ6MAP_SHIFT (4U)
33958/*! DQ6MAP - DQ bit 6 DATX8 slice mapping index
33959 */
33960#define DDRPHY_DX8DQMAP1_DQ6MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP1_DQ6MAP_SHIFT)) & DDRPHY_DX8DQMAP1_DQ6MAP_MASK)
33961#define DDRPHY_DX8DQMAP1_DQ7MAP_MASK (0xF00U)
33962#define DDRPHY_DX8DQMAP1_DQ7MAP_SHIFT (8U)
33963/*! DQ7MAP - DQ bit 7 DATX8 slice mapping index
33964 */
33965#define DDRPHY_DX8DQMAP1_DQ7MAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP1_DQ7MAP_SHIFT)) & DDRPHY_DX8DQMAP1_DQ7MAP_MASK)
33966#define DDRPHY_DX8DQMAP1_DMMAP_MASK (0xF000U)
33967#define DDRPHY_DX8DQMAP1_DMMAP_SHIFT (12U)
33968/*! DMMAP - DM bit DATX8 slice mapping index
33969 */
33970#define DDRPHY_DX8DQMAP1_DMMAP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP1_DMMAP_SHIFT)) & DDRPHY_DX8DQMAP1_DMMAP_MASK)
33971#define DDRPHY_DX8DQMAP1_RESERVED_30_16_MASK (0x7FFF0000U)
33972#define DDRPHY_DX8DQMAP1_RESERVED_30_16_SHIFT (16U)
33973/*! RESERVED_30_16 - Reserved. Return zeroes on reads.
33974 */
33975#define DDRPHY_DX8DQMAP1_RESERVED_30_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP1_RESERVED_30_16_SHIFT)) & DDRPHY_DX8DQMAP1_RESERVED_30_16_MASK)
33976#define DDRPHY_DX8DQMAP1_MAPOK_MASK (0x80000000U)
33977#define DDRPHY_DX8DQMAP1_MAPOK_SHIFT (31U)
33978/*! MAPOK - Checksum bit
33979 */
33980#define DDRPHY_DX8DQMAP1_MAPOK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8DQMAP1_MAPOK_SHIFT)) & DDRPHY_DX8DQMAP1_MAPOK_MASK)
33981/*! @} */
33982
33983/*! @name DX8BDLR0 - DATX8 n Bit Delay Line Register 0 */
33984/*! @{ */
33985#define DDRPHY_DX8BDLR0_DQ0WBD_MASK (0x3FU)
33986#define DDRPHY_DX8BDLR0_DQ0WBD_SHIFT (0U)
33987/*! DQ0WBD - DQ0 Write Bit Delay
33988 */
33989#define DDRPHY_DX8BDLR0_DQ0WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_DQ0WBD_SHIFT)) & DDRPHY_DX8BDLR0_DQ0WBD_MASK)
33990#define DDRPHY_DX8BDLR0_RESERVED_7_6_MASK (0xC0U)
33991#define DDRPHY_DX8BDLR0_RESERVED_7_6_SHIFT (6U)
33992/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
33993 */
33994#define DDRPHY_DX8BDLR0_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR0_RESERVED_7_6_MASK)
33995#define DDRPHY_DX8BDLR0_DQ1WBD_MASK (0x3F00U)
33996#define DDRPHY_DX8BDLR0_DQ1WBD_SHIFT (8U)
33997/*! DQ1WBD - DQ1 Write Bit Delay
33998 */
33999#define DDRPHY_DX8BDLR0_DQ1WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_DQ1WBD_SHIFT)) & DDRPHY_DX8BDLR0_DQ1WBD_MASK)
34000#define DDRPHY_DX8BDLR0_RESERVED_15_14_MASK (0xC000U)
34001#define DDRPHY_DX8BDLR0_RESERVED_15_14_SHIFT (14U)
34002/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
34003 */
34004#define DDRPHY_DX8BDLR0_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR0_RESERVED_15_14_MASK)
34005#define DDRPHY_DX8BDLR0_DQ2WBD_MASK (0x3F0000U)
34006#define DDRPHY_DX8BDLR0_DQ2WBD_SHIFT (16U)
34007/*! DQ2WBD - DQ2 Write Bit Delay
34008 */
34009#define DDRPHY_DX8BDLR0_DQ2WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_DQ2WBD_SHIFT)) & DDRPHY_DX8BDLR0_DQ2WBD_MASK)
34010#define DDRPHY_DX8BDLR0_RESERVED_23_22_MASK (0xC00000U)
34011#define DDRPHY_DX8BDLR0_RESERVED_23_22_SHIFT (22U)
34012/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
34013 */
34014#define DDRPHY_DX8BDLR0_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_RESERVED_23_22_SHIFT)) & DDRPHY_DX8BDLR0_RESERVED_23_22_MASK)
34015#define DDRPHY_DX8BDLR0_DQ3WBD_MASK (0x3F000000U)
34016#define DDRPHY_DX8BDLR0_DQ3WBD_SHIFT (24U)
34017/*! DQ3WBD - DQ3 Write Bit Delay
34018 */
34019#define DDRPHY_DX8BDLR0_DQ3WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_DQ3WBD_SHIFT)) & DDRPHY_DX8BDLR0_DQ3WBD_MASK)
34020#define DDRPHY_DX8BDLR0_RESERVED_31_30_MASK (0xC0000000U)
34021#define DDRPHY_DX8BDLR0_RESERVED_31_30_SHIFT (30U)
34022/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
34023 */
34024#define DDRPHY_DX8BDLR0_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR0_RESERVED_31_30_SHIFT)) & DDRPHY_DX8BDLR0_RESERVED_31_30_MASK)
34025/*! @} */
34026
34027/*! @name DX8BDLR1 - DATX8 n Bit Delay Line Register 1 */
34028/*! @{ */
34029#define DDRPHY_DX8BDLR1_DQ4WBD_MASK (0x3FU)
34030#define DDRPHY_DX8BDLR1_DQ4WBD_SHIFT (0U)
34031/*! DQ4WBD - DQ4 Write Bit Delay
34032 */
34033#define DDRPHY_DX8BDLR1_DQ4WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_DQ4WBD_SHIFT)) & DDRPHY_DX8BDLR1_DQ4WBD_MASK)
34034#define DDRPHY_DX8BDLR1_RESERVED_7_6_MASK (0xC0U)
34035#define DDRPHY_DX8BDLR1_RESERVED_7_6_SHIFT (6U)
34036/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
34037 */
34038#define DDRPHY_DX8BDLR1_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR1_RESERVED_7_6_MASK)
34039#define DDRPHY_DX8BDLR1_DQ5WBD_MASK (0x3F00U)
34040#define DDRPHY_DX8BDLR1_DQ5WBD_SHIFT (8U)
34041/*! DQ5WBD - DQ5 Write Bit Delay
34042 */
34043#define DDRPHY_DX8BDLR1_DQ5WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_DQ5WBD_SHIFT)) & DDRPHY_DX8BDLR1_DQ5WBD_MASK)
34044#define DDRPHY_DX8BDLR1_RESERVED_15_14_MASK (0xC000U)
34045#define DDRPHY_DX8BDLR1_RESERVED_15_14_SHIFT (14U)
34046/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
34047 */
34048#define DDRPHY_DX8BDLR1_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR1_RESERVED_15_14_MASK)
34049#define DDRPHY_DX8BDLR1_DQ6WBD_MASK (0x3F0000U)
34050#define DDRPHY_DX8BDLR1_DQ6WBD_SHIFT (16U)
34051/*! DQ6WBD - DQ6 Write Bit Delay
34052 */
34053#define DDRPHY_DX8BDLR1_DQ6WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_DQ6WBD_SHIFT)) & DDRPHY_DX8BDLR1_DQ6WBD_MASK)
34054#define DDRPHY_DX8BDLR1_RESERVED_23_22_MASK (0xC00000U)
34055#define DDRPHY_DX8BDLR1_RESERVED_23_22_SHIFT (22U)
34056/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
34057 */
34058#define DDRPHY_DX8BDLR1_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_RESERVED_23_22_SHIFT)) & DDRPHY_DX8BDLR1_RESERVED_23_22_MASK)
34059#define DDRPHY_DX8BDLR1_DQ7WBD_MASK (0x3F000000U)
34060#define DDRPHY_DX8BDLR1_DQ7WBD_SHIFT (24U)
34061/*! DQ7WBD - DQ7 Write Bit Delay
34062 */
34063#define DDRPHY_DX8BDLR1_DQ7WBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_DQ7WBD_SHIFT)) & DDRPHY_DX8BDLR1_DQ7WBD_MASK)
34064#define DDRPHY_DX8BDLR1_RESERVED_31_30_MASK (0xC0000000U)
34065#define DDRPHY_DX8BDLR1_RESERVED_31_30_SHIFT (30U)
34066/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
34067 */
34068#define DDRPHY_DX8BDLR1_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR1_RESERVED_31_30_SHIFT)) & DDRPHY_DX8BDLR1_RESERVED_31_30_MASK)
34069/*! @} */
34070
34071/*! @name DX8BDLR2 - DATX8 n Bit Delay Line Register 2 */
34072/*! @{ */
34073#define DDRPHY_DX8BDLR2_DMWBD_MASK (0x3FU)
34074#define DDRPHY_DX8BDLR2_DMWBD_SHIFT (0U)
34075/*! DMWBD - DM Write Bit Delay
34076 */
34077#define DDRPHY_DX8BDLR2_DMWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_DMWBD_SHIFT)) & DDRPHY_DX8BDLR2_DMWBD_MASK)
34078#define DDRPHY_DX8BDLR2_RESERVED_7_6_MASK (0xC0U)
34079#define DDRPHY_DX8BDLR2_RESERVED_7_6_SHIFT (6U)
34080/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
34081 */
34082#define DDRPHY_DX8BDLR2_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR2_RESERVED_7_6_MASK)
34083#define DDRPHY_DX8BDLR2_DSWBD_MASK (0x3F00U)
34084#define DDRPHY_DX8BDLR2_DSWBD_SHIFT (8U)
34085/*! DSWBD - DQS Write Bit Delay
34086 */
34087#define DDRPHY_DX8BDLR2_DSWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_DSWBD_SHIFT)) & DDRPHY_DX8BDLR2_DSWBD_MASK)
34088#define DDRPHY_DX8BDLR2_RESERVED_15_14_MASK (0xC000U)
34089#define DDRPHY_DX8BDLR2_RESERVED_15_14_SHIFT (14U)
34090/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
34091 */
34092#define DDRPHY_DX8BDLR2_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR2_RESERVED_15_14_MASK)
34093#define DDRPHY_DX8BDLR2_DSOEBD_MASK (0x3F0000U)
34094#define DDRPHY_DX8BDLR2_DSOEBD_SHIFT (16U)
34095/*! DSOEBD - DQS/DM/DQ Output Enable Bit Delay
34096 */
34097#define DDRPHY_DX8BDLR2_DSOEBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_DSOEBD_SHIFT)) & DDRPHY_DX8BDLR2_DSOEBD_MASK)
34098#define DDRPHY_DX8BDLR2_RESERVED_23_22_MASK (0xC00000U)
34099#define DDRPHY_DX8BDLR2_RESERVED_23_22_SHIFT (22U)
34100/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
34101 */
34102#define DDRPHY_DX8BDLR2_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_RESERVED_23_22_SHIFT)) & DDRPHY_DX8BDLR2_RESERVED_23_22_MASK)
34103#define DDRPHY_DX8BDLR2_DSNWBD_MASK (0x3F000000U)
34104#define DDRPHY_DX8BDLR2_DSNWBD_SHIFT (24U)
34105/*! DSNWBD - DQSN Write Bit Delay
34106 */
34107#define DDRPHY_DX8BDLR2_DSNWBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_DSNWBD_SHIFT)) & DDRPHY_DX8BDLR2_DSNWBD_MASK)
34108#define DDRPHY_DX8BDLR2_RESERVED_31_30_MASK (0xC0000000U)
34109#define DDRPHY_DX8BDLR2_RESERVED_31_30_SHIFT (30U)
34110/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
34111 */
34112#define DDRPHY_DX8BDLR2_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR2_RESERVED_31_30_SHIFT)) & DDRPHY_DX8BDLR2_RESERVED_31_30_MASK)
34113/*! @} */
34114
34115/*! @name DX8BDLR3 - DATX8 n Bit Delay Line Register 3 */
34116/*! @{ */
34117#define DDRPHY_DX8BDLR3_DQ0RBD_MASK (0x3FU)
34118#define DDRPHY_DX8BDLR3_DQ0RBD_SHIFT (0U)
34119/*! DQ0RBD - DQ0 Read Bit Delay
34120 */
34121#define DDRPHY_DX8BDLR3_DQ0RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_DQ0RBD_SHIFT)) & DDRPHY_DX8BDLR3_DQ0RBD_MASK)
34122#define DDRPHY_DX8BDLR3_RESERVED_7_6_MASK (0xC0U)
34123#define DDRPHY_DX8BDLR3_RESERVED_7_6_SHIFT (6U)
34124/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
34125 */
34126#define DDRPHY_DX8BDLR3_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR3_RESERVED_7_6_MASK)
34127#define DDRPHY_DX8BDLR3_DQ1RBD_MASK (0x3F00U)
34128#define DDRPHY_DX8BDLR3_DQ1RBD_SHIFT (8U)
34129/*! DQ1RBD - DQ1 Read Bit Delay
34130 */
34131#define DDRPHY_DX8BDLR3_DQ1RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_DQ1RBD_SHIFT)) & DDRPHY_DX8BDLR3_DQ1RBD_MASK)
34132#define DDRPHY_DX8BDLR3_RESERVED_15_14_MASK (0xC000U)
34133#define DDRPHY_DX8BDLR3_RESERVED_15_14_SHIFT (14U)
34134/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
34135 */
34136#define DDRPHY_DX8BDLR3_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR3_RESERVED_15_14_MASK)
34137#define DDRPHY_DX8BDLR3_DQ2RBD_MASK (0x3F0000U)
34138#define DDRPHY_DX8BDLR3_DQ2RBD_SHIFT (16U)
34139/*! DQ2RBD - DQ2 Read Bit Delay
34140 */
34141#define DDRPHY_DX8BDLR3_DQ2RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_DQ2RBD_SHIFT)) & DDRPHY_DX8BDLR3_DQ2RBD_MASK)
34142#define DDRPHY_DX8BDLR3_RESERVED_23_22_MASK (0xC00000U)
34143#define DDRPHY_DX8BDLR3_RESERVED_23_22_SHIFT (22U)
34144/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
34145 */
34146#define DDRPHY_DX8BDLR3_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_RESERVED_23_22_SHIFT)) & DDRPHY_DX8BDLR3_RESERVED_23_22_MASK)
34147#define DDRPHY_DX8BDLR3_DQ3RBD_MASK (0x3F000000U)
34148#define DDRPHY_DX8BDLR3_DQ3RBD_SHIFT (24U)
34149/*! DQ3RBD - DQ3 Read Bit Delay
34150 */
34151#define DDRPHY_DX8BDLR3_DQ3RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_DQ3RBD_SHIFT)) & DDRPHY_DX8BDLR3_DQ3RBD_MASK)
34152#define DDRPHY_DX8BDLR3_RESERVED_31_30_MASK (0xC0000000U)
34153#define DDRPHY_DX8BDLR3_RESERVED_31_30_SHIFT (30U)
34154/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
34155 */
34156#define DDRPHY_DX8BDLR3_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR3_RESERVED_31_30_SHIFT)) & DDRPHY_DX8BDLR3_RESERVED_31_30_MASK)
34157/*! @} */
34158
34159/*! @name DX8BDLR4 - DATX8 n Bit Delay Line Register 4 */
34160/*! @{ */
34161#define DDRPHY_DX8BDLR4_DQ4RBD_MASK (0x3FU)
34162#define DDRPHY_DX8BDLR4_DQ4RBD_SHIFT (0U)
34163/*! DQ4RBD - DQ4 Read Bit Delay
34164 */
34165#define DDRPHY_DX8BDLR4_DQ4RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_DQ4RBD_SHIFT)) & DDRPHY_DX8BDLR4_DQ4RBD_MASK)
34166#define DDRPHY_DX8BDLR4_RESERVED_7_6_MASK (0xC0U)
34167#define DDRPHY_DX8BDLR4_RESERVED_7_6_SHIFT (6U)
34168/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
34169 */
34170#define DDRPHY_DX8BDLR4_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR4_RESERVED_7_6_MASK)
34171#define DDRPHY_DX8BDLR4_DQ5RBD_MASK (0x3F00U)
34172#define DDRPHY_DX8BDLR4_DQ5RBD_SHIFT (8U)
34173/*! DQ5RBD - DQ5 Read Bit Delay
34174 */
34175#define DDRPHY_DX8BDLR4_DQ5RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_DQ5RBD_SHIFT)) & DDRPHY_DX8BDLR4_DQ5RBD_MASK)
34176#define DDRPHY_DX8BDLR4_RESERVED_15_14_MASK (0xC000U)
34177#define DDRPHY_DX8BDLR4_RESERVED_15_14_SHIFT (14U)
34178/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
34179 */
34180#define DDRPHY_DX8BDLR4_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR4_RESERVED_15_14_MASK)
34181#define DDRPHY_DX8BDLR4_DQ6RBD_MASK (0x3F0000U)
34182#define DDRPHY_DX8BDLR4_DQ6RBD_SHIFT (16U)
34183/*! DQ6RBD - DQ6 Read Bit Delay
34184 */
34185#define DDRPHY_DX8BDLR4_DQ6RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_DQ6RBD_SHIFT)) & DDRPHY_DX8BDLR4_DQ6RBD_MASK)
34186#define DDRPHY_DX8BDLR4_RESERVED_23_22_MASK (0xC00000U)
34187#define DDRPHY_DX8BDLR4_RESERVED_23_22_SHIFT (22U)
34188/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
34189 */
34190#define DDRPHY_DX8BDLR4_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_RESERVED_23_22_SHIFT)) & DDRPHY_DX8BDLR4_RESERVED_23_22_MASK)
34191#define DDRPHY_DX8BDLR4_DQ7RBD_MASK (0x3F000000U)
34192#define DDRPHY_DX8BDLR4_DQ7RBD_SHIFT (24U)
34193/*! DQ7RBD - DQ7 Read Bit Delay
34194 */
34195#define DDRPHY_DX8BDLR4_DQ7RBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_DQ7RBD_SHIFT)) & DDRPHY_DX8BDLR4_DQ7RBD_MASK)
34196#define DDRPHY_DX8BDLR4_RESERVED_31_30_MASK (0xC0000000U)
34197#define DDRPHY_DX8BDLR4_RESERVED_31_30_SHIFT (30U)
34198/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
34199 */
34200#define DDRPHY_DX8BDLR4_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR4_RESERVED_31_30_SHIFT)) & DDRPHY_DX8BDLR4_RESERVED_31_30_MASK)
34201/*! @} */
34202
34203/*! @name DX8BDLR5 - DATX8 n Bit Delay Line Register 5 */
34204/*! @{ */
34205#define DDRPHY_DX8BDLR5_DMRBD_MASK (0x3FU)
34206#define DDRPHY_DX8BDLR5_DMRBD_SHIFT (0U)
34207/*! DMRBD - DM Read Bit Delay
34208 */
34209#define DDRPHY_DX8BDLR5_DMRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR5_DMRBD_SHIFT)) & DDRPHY_DX8BDLR5_DMRBD_MASK)
34210#define DDRPHY_DX8BDLR5_RESERVED_31_6_MASK (0xFFFFFFC0U)
34211#define DDRPHY_DX8BDLR5_RESERVED_31_6_SHIFT (6U)
34212/*! RESERVED_31_6 - Reserved. Return zeroes on reads.
34213 */
34214#define DDRPHY_DX8BDLR5_RESERVED_31_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR5_RESERVED_31_6_SHIFT)) & DDRPHY_DX8BDLR5_RESERVED_31_6_MASK)
34215/*! @} */
34216
34217/*! @name DX8BDLR6 - DATX8 n Bit Delay Line Register 6 */
34218/*! @{ */
34219#define DDRPHY_DX8BDLR6_RESERVED_7_0_MASK (0xFFU)
34220#define DDRPHY_DX8BDLR6_RESERVED_7_0_SHIFT (0U)
34221/*! RESERVED_7_0 - Reserved. Return zeroes on reads.
34222 */
34223#define DDRPHY_DX8BDLR6_RESERVED_7_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR6_RESERVED_7_0_SHIFT)) & DDRPHY_DX8BDLR6_RESERVED_7_0_MASK)
34224#define DDRPHY_DX8BDLR6_PDRBD_MASK (0x3F00U)
34225#define DDRPHY_DX8BDLR6_PDRBD_SHIFT (8U)
34226/*! PDRBD - Power down receiver Bit Delay
34227 */
34228#define DDRPHY_DX8BDLR6_PDRBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR6_PDRBD_SHIFT)) & DDRPHY_DX8BDLR6_PDRBD_MASK)
34229#define DDRPHY_DX8BDLR6_RESERVED_15_14_MASK (0xC000U)
34230#define DDRPHY_DX8BDLR6_RESERVED_15_14_SHIFT (14U)
34231/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
34232 */
34233#define DDRPHY_DX8BDLR6_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR6_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR6_RESERVED_15_14_MASK)
34234#define DDRPHY_DX8BDLR6_TERBD_MASK (0x3F0000U)
34235#define DDRPHY_DX8BDLR6_TERBD_SHIFT (16U)
34236/*! TERBD - Termination Enable Bit Delay
34237 */
34238#define DDRPHY_DX8BDLR6_TERBD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR6_TERBD_SHIFT)) & DDRPHY_DX8BDLR6_TERBD_MASK)
34239#define DDRPHY_DX8BDLR6_RESERVED_31_22_MASK (0xFFC00000U)
34240#define DDRPHY_DX8BDLR6_RESERVED_31_22_SHIFT (22U)
34241/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
34242 */
34243#define DDRPHY_DX8BDLR6_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR6_RESERVED_31_22_SHIFT)) & DDRPHY_DX8BDLR6_RESERVED_31_22_MASK)
34244/*! @} */
34245
34246/*! @name DX8BDLR7 - DATX8 n Bit Delay Line Register 7 */
34247/*! @{ */
34248#define DDRPHY_DX8BDLR7_RESERVED_5_0_MASK (0x3FU)
34249#define DDRPHY_DX8BDLR7_RESERVED_5_0_SHIFT (0U)
34250/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
34251 */
34252#define DDRPHY_DX8BDLR7_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR7_RESERVED_5_0_SHIFT)) & DDRPHY_DX8BDLR7_RESERVED_5_0_MASK)
34253#define DDRPHY_DX8BDLR7_RESERVED_7_6_MASK (0xC0U)
34254#define DDRPHY_DX8BDLR7_RESERVED_7_6_SHIFT (6U)
34255/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
34256 */
34257#define DDRPHY_DX8BDLR7_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR7_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR7_RESERVED_7_6_MASK)
34258#define DDRPHY_DX8BDLR7_RESERVED_13_8_MASK (0x3F00U)
34259#define DDRPHY_DX8BDLR7_RESERVED_13_8_SHIFT (8U)
34260/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
34261 */
34262#define DDRPHY_DX8BDLR7_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR7_RESERVED_13_8_SHIFT)) & DDRPHY_DX8BDLR7_RESERVED_13_8_MASK)
34263#define DDRPHY_DX8BDLR7_RESERVED_15_14_MASK (0xC000U)
34264#define DDRPHY_DX8BDLR7_RESERVED_15_14_SHIFT (14U)
34265/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
34266 */
34267#define DDRPHY_DX8BDLR7_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR7_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR7_RESERVED_15_14_MASK)
34268#define DDRPHY_DX8BDLR7_RESERVED_21_16_MASK (0x3F0000U)
34269#define DDRPHY_DX8BDLR7_RESERVED_21_16_SHIFT (16U)
34270/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
34271 */
34272#define DDRPHY_DX8BDLR7_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR7_RESERVED_21_16_SHIFT)) & DDRPHY_DX8BDLR7_RESERVED_21_16_MASK)
34273#define DDRPHY_DX8BDLR7_RESERVED_31_22_MASK (0xFFC00000U)
34274#define DDRPHY_DX8BDLR7_RESERVED_31_22_SHIFT (22U)
34275/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
34276 */
34277#define DDRPHY_DX8BDLR7_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR7_RESERVED_31_22_SHIFT)) & DDRPHY_DX8BDLR7_RESERVED_31_22_MASK)
34278/*! @} */
34279
34280/*! @name DX8BDLR8 - DATX8 n Bit Delay Line Register 8 */
34281/*! @{ */
34282#define DDRPHY_DX8BDLR8_RESERVED_5_0_MASK (0x3FU)
34283#define DDRPHY_DX8BDLR8_RESERVED_5_0_SHIFT (0U)
34284/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
34285 */
34286#define DDRPHY_DX8BDLR8_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR8_RESERVED_5_0_SHIFT)) & DDRPHY_DX8BDLR8_RESERVED_5_0_MASK)
34287#define DDRPHY_DX8BDLR8_RESERVED_7_6_MASK (0xC0U)
34288#define DDRPHY_DX8BDLR8_RESERVED_7_6_SHIFT (6U)
34289/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
34290 */
34291#define DDRPHY_DX8BDLR8_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR8_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR8_RESERVED_7_6_MASK)
34292#define DDRPHY_DX8BDLR8_RESERVED_13_8_MASK (0x3F00U)
34293#define DDRPHY_DX8BDLR8_RESERVED_13_8_SHIFT (8U)
34294/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
34295 */
34296#define DDRPHY_DX8BDLR8_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR8_RESERVED_13_8_SHIFT)) & DDRPHY_DX8BDLR8_RESERVED_13_8_MASK)
34297#define DDRPHY_DX8BDLR8_RESERVED_15_14_MASK (0xC000U)
34298#define DDRPHY_DX8BDLR8_RESERVED_15_14_SHIFT (14U)
34299/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
34300 */
34301#define DDRPHY_DX8BDLR8_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR8_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR8_RESERVED_15_14_MASK)
34302#define DDRPHY_DX8BDLR8_RESERVED_21_16_MASK (0x3F0000U)
34303#define DDRPHY_DX8BDLR8_RESERVED_21_16_SHIFT (16U)
34304/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
34305 */
34306#define DDRPHY_DX8BDLR8_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR8_RESERVED_21_16_SHIFT)) & DDRPHY_DX8BDLR8_RESERVED_21_16_MASK)
34307#define DDRPHY_DX8BDLR8_RESERVED_31_22_MASK (0xFFC00000U)
34308#define DDRPHY_DX8BDLR8_RESERVED_31_22_SHIFT (22U)
34309/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
34310 */
34311#define DDRPHY_DX8BDLR8_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR8_RESERVED_31_22_SHIFT)) & DDRPHY_DX8BDLR8_RESERVED_31_22_MASK)
34312/*! @} */
34313
34314/*! @name DX8BDLR9 - DATX8 n Bit Delay Line Register 9 */
34315/*! @{ */
34316#define DDRPHY_DX8BDLR9_RESERVED_5_0_MASK (0x3FU)
34317#define DDRPHY_DX8BDLR9_RESERVED_5_0_SHIFT (0U)
34318/*! RESERVED_5_0 - Reserved. Caution, do not write to this register field.
34319 */
34320#define DDRPHY_DX8BDLR9_RESERVED_5_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR9_RESERVED_5_0_SHIFT)) & DDRPHY_DX8BDLR9_RESERVED_5_0_MASK)
34321#define DDRPHY_DX8BDLR9_RESERVED_7_6_MASK (0xC0U)
34322#define DDRPHY_DX8BDLR9_RESERVED_7_6_SHIFT (6U)
34323/*! RESERVED_7_6 - Reserved. Return zeroes on reads.
34324 */
34325#define DDRPHY_DX8BDLR9_RESERVED_7_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR9_RESERVED_7_6_SHIFT)) & DDRPHY_DX8BDLR9_RESERVED_7_6_MASK)
34326#define DDRPHY_DX8BDLR9_RESERVED_13_8_MASK (0x3F00U)
34327#define DDRPHY_DX8BDLR9_RESERVED_13_8_SHIFT (8U)
34328/*! RESERVED_13_8 - Reserved. Caution, do not write to this register field.
34329 */
34330#define DDRPHY_DX8BDLR9_RESERVED_13_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR9_RESERVED_13_8_SHIFT)) & DDRPHY_DX8BDLR9_RESERVED_13_8_MASK)
34331#define DDRPHY_DX8BDLR9_RESERVED_15_14_MASK (0xC000U)
34332#define DDRPHY_DX8BDLR9_RESERVED_15_14_SHIFT (14U)
34333/*! RESERVED_15_14 - Reserved. Return zeroes on reads.
34334 */
34335#define DDRPHY_DX8BDLR9_RESERVED_15_14(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR9_RESERVED_15_14_SHIFT)) & DDRPHY_DX8BDLR9_RESERVED_15_14_MASK)
34336#define DDRPHY_DX8BDLR9_RESERVED_21_16_MASK (0x3F0000U)
34337#define DDRPHY_DX8BDLR9_RESERVED_21_16_SHIFT (16U)
34338/*! RESERVED_21_16 - Reserved. Caution, do not write to this register field.
34339 */
34340#define DDRPHY_DX8BDLR9_RESERVED_21_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR9_RESERVED_21_16_SHIFT)) & DDRPHY_DX8BDLR9_RESERVED_21_16_MASK)
34341#define DDRPHY_DX8BDLR9_RESERVED_31_22_MASK (0xFFC00000U)
34342#define DDRPHY_DX8BDLR9_RESERVED_31_22_SHIFT (22U)
34343/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
34344 */
34345#define DDRPHY_DX8BDLR9_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8BDLR9_RESERVED_31_22_SHIFT)) & DDRPHY_DX8BDLR9_RESERVED_31_22_MASK)
34346/*! @} */
34347
34348/*! @name DX8LCDLR0 - DATX8 n Local Calibrated Delay Line Register 0 */
34349/*! @{ */
34350#define DDRPHY_DX8LCDLR0_WLD_MASK (0x1FFU)
34351#define DDRPHY_DX8LCDLR0_WLD_SHIFT (0U)
34352/*! WLD - Write Leveling Delay
34353 */
34354#define DDRPHY_DX8LCDLR0_WLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR0_WLD_SHIFT)) & DDRPHY_DX8LCDLR0_WLD_MASK)
34355#define DDRPHY_DX8LCDLR0_RESERVED_15_9_MASK (0xFE00U)
34356#define DDRPHY_DX8LCDLR0_RESERVED_15_9_SHIFT (9U)
34357/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
34358 */
34359#define DDRPHY_DX8LCDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX8LCDLR0_RESERVED_15_9_MASK)
34360#define DDRPHY_DX8LCDLR0_RESERVED_24_16_MASK (0x1FF0000U)
34361#define DDRPHY_DX8LCDLR0_RESERVED_24_16_SHIFT (16U)
34362/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
34363 */
34364#define DDRPHY_DX8LCDLR0_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR0_RESERVED_24_16_SHIFT)) & DDRPHY_DX8LCDLR0_RESERVED_24_16_MASK)
34365#define DDRPHY_DX8LCDLR0_RESERVED_31_25_MASK (0xFE000000U)
34366#define DDRPHY_DX8LCDLR0_RESERVED_31_25_SHIFT (25U)
34367/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
34368 */
34369#define DDRPHY_DX8LCDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX8LCDLR0_RESERVED_31_25_MASK)
34370/*! @} */
34371
34372/*! @name DX8LCDLR1 - DATX8 n Local Calibrated Delay Line Register 1 */
34373/*! @{ */
34374#define DDRPHY_DX8LCDLR1_WDQD_MASK (0x1FFU)
34375#define DDRPHY_DX8LCDLR1_WDQD_SHIFT (0U)
34376/*! WDQD - Write Data Delay
34377 */
34378#define DDRPHY_DX8LCDLR1_WDQD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR1_WDQD_SHIFT)) & DDRPHY_DX8LCDLR1_WDQD_MASK)
34379#define DDRPHY_DX8LCDLR1_RESERVED_15_9_MASK (0xFE00U)
34380#define DDRPHY_DX8LCDLR1_RESERVED_15_9_SHIFT (9U)
34381/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
34382 */
34383#define DDRPHY_DX8LCDLR1_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR1_RESERVED_15_9_SHIFT)) & DDRPHY_DX8LCDLR1_RESERVED_15_9_MASK)
34384#define DDRPHY_DX8LCDLR1_RESERVED_24_16_MASK (0x1FF0000U)
34385#define DDRPHY_DX8LCDLR1_RESERVED_24_16_SHIFT (16U)
34386/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
34387 */
34388#define DDRPHY_DX8LCDLR1_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR1_RESERVED_24_16_SHIFT)) & DDRPHY_DX8LCDLR1_RESERVED_24_16_MASK)
34389#define DDRPHY_DX8LCDLR1_RESERVED_31_25_MASK (0xFE000000U)
34390#define DDRPHY_DX8LCDLR1_RESERVED_31_25_SHIFT (25U)
34391/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
34392 */
34393#define DDRPHY_DX8LCDLR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8LCDLR1_RESERVED_31_25_MASK)
34394/*! @} */
34395
34396/*! @name DX8LCDLR2 - DATX8 n Local Calibrated Delay Line Register 2 */
34397/*! @{ */
34398#define DDRPHY_DX8LCDLR2_DQSGD_MASK (0x1FFU)
34399#define DDRPHY_DX8LCDLR2_DQSGD_SHIFT (0U)
34400/*! DQSGD - Read DQS Gating Delay
34401 */
34402#define DDRPHY_DX8LCDLR2_DQSGD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR2_DQSGD_SHIFT)) & DDRPHY_DX8LCDLR2_DQSGD_MASK)
34403#define DDRPHY_DX8LCDLR2_RESERVED_15_9_MASK (0xFE00U)
34404#define DDRPHY_DX8LCDLR2_RESERVED_15_9_SHIFT (9U)
34405/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
34406 */
34407#define DDRPHY_DX8LCDLR2_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR2_RESERVED_15_9_SHIFT)) & DDRPHY_DX8LCDLR2_RESERVED_15_9_MASK)
34408#define DDRPHY_DX8LCDLR2_RESERVED_24_16_MASK (0x1FF0000U)
34409#define DDRPHY_DX8LCDLR2_RESERVED_24_16_SHIFT (16U)
34410/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
34411 */
34412#define DDRPHY_DX8LCDLR2_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR2_RESERVED_24_16_SHIFT)) & DDRPHY_DX8LCDLR2_RESERVED_24_16_MASK)
34413#define DDRPHY_DX8LCDLR2_RESERVED_31_25_MASK (0xFE000000U)
34414#define DDRPHY_DX8LCDLR2_RESERVED_31_25_SHIFT (25U)
34415/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
34416 */
34417#define DDRPHY_DX8LCDLR2_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR2_RESERVED_31_25_SHIFT)) & DDRPHY_DX8LCDLR2_RESERVED_31_25_MASK)
34418/*! @} */
34419
34420/*! @name DX8LCDLR3 - DATX8 n Local Calibrated Delay Line Register 3 */
34421/*! @{ */
34422#define DDRPHY_DX8LCDLR3_RDQSD_MASK (0x1FFU)
34423#define DDRPHY_DX8LCDLR3_RDQSD_SHIFT (0U)
34424/*! RDQSD - Read DQS Delay
34425 */
34426#define DDRPHY_DX8LCDLR3_RDQSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR3_RDQSD_SHIFT)) & DDRPHY_DX8LCDLR3_RDQSD_MASK)
34427#define DDRPHY_DX8LCDLR3_RESERVED_15_9_MASK (0xFE00U)
34428#define DDRPHY_DX8LCDLR3_RESERVED_15_9_SHIFT (9U)
34429/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
34430 */
34431#define DDRPHY_DX8LCDLR3_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR3_RESERVED_15_9_SHIFT)) & DDRPHY_DX8LCDLR3_RESERVED_15_9_MASK)
34432#define DDRPHY_DX8LCDLR3_RESERVED_24_16_MASK (0x1FF0000U)
34433#define DDRPHY_DX8LCDLR3_RESERVED_24_16_SHIFT (16U)
34434/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
34435 */
34436#define DDRPHY_DX8LCDLR3_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR3_RESERVED_24_16_SHIFT)) & DDRPHY_DX8LCDLR3_RESERVED_24_16_MASK)
34437#define DDRPHY_DX8LCDLR3_RESERVED_31_25_MASK (0xFE000000U)
34438#define DDRPHY_DX8LCDLR3_RESERVED_31_25_SHIFT (25U)
34439/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
34440 */
34441#define DDRPHY_DX8LCDLR3_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR3_RESERVED_31_25_SHIFT)) & DDRPHY_DX8LCDLR3_RESERVED_31_25_MASK)
34442/*! @} */
34443
34444/*! @name DX8LCDLR4 - DATX8 n Local Calibrated Delay Line Register 4 */
34445/*! @{ */
34446#define DDRPHY_DX8LCDLR4_RDQSND_MASK (0x1FFU)
34447#define DDRPHY_DX8LCDLR4_RDQSND_SHIFT (0U)
34448/*! RDQSND - Read DQSN Delay
34449 */
34450#define DDRPHY_DX8LCDLR4_RDQSND(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR4_RDQSND_SHIFT)) & DDRPHY_DX8LCDLR4_RDQSND_MASK)
34451#define DDRPHY_DX8LCDLR4_RESERVED_15_9_MASK (0xFE00U)
34452#define DDRPHY_DX8LCDLR4_RESERVED_15_9_SHIFT (9U)
34453/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
34454 */
34455#define DDRPHY_DX8LCDLR4_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR4_RESERVED_15_9_SHIFT)) & DDRPHY_DX8LCDLR4_RESERVED_15_9_MASK)
34456#define DDRPHY_DX8LCDLR4_RESERVED_24_16_MASK (0x1FF0000U)
34457#define DDRPHY_DX8LCDLR4_RESERVED_24_16_SHIFT (16U)
34458/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
34459 */
34460#define DDRPHY_DX8LCDLR4_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR4_RESERVED_24_16_SHIFT)) & DDRPHY_DX8LCDLR4_RESERVED_24_16_MASK)
34461#define DDRPHY_DX8LCDLR4_RESERVED_31_25_MASK (0xFE000000U)
34462#define DDRPHY_DX8LCDLR4_RESERVED_31_25_SHIFT (25U)
34463/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
34464 */
34465#define DDRPHY_DX8LCDLR4_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR4_RESERVED_31_25_SHIFT)) & DDRPHY_DX8LCDLR4_RESERVED_31_25_MASK)
34466/*! @} */
34467
34468/*! @name DX8LCDLR5 - DATX8 n Local Calibrated Delay Line Register 5 */
34469/*! @{ */
34470#define DDRPHY_DX8LCDLR5_DQSGSD_MASK (0x1FFU)
34471#define DDRPHY_DX8LCDLR5_DQSGSD_SHIFT (0U)
34472/*! DQSGSD - DQS Gating Status Delay
34473 */
34474#define DDRPHY_DX8LCDLR5_DQSGSD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR5_DQSGSD_SHIFT)) & DDRPHY_DX8LCDLR5_DQSGSD_MASK)
34475#define DDRPHY_DX8LCDLR5_RESERVED_15_9_MASK (0xFE00U)
34476#define DDRPHY_DX8LCDLR5_RESERVED_15_9_SHIFT (9U)
34477/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
34478 */
34479#define DDRPHY_DX8LCDLR5_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR5_RESERVED_15_9_SHIFT)) & DDRPHY_DX8LCDLR5_RESERVED_15_9_MASK)
34480#define DDRPHY_DX8LCDLR5_RESERVED_24_16_MASK (0x1FF0000U)
34481#define DDRPHY_DX8LCDLR5_RESERVED_24_16_SHIFT (16U)
34482/*! RESERVED_24_16 - Reserved. Caution, do not write to this register field.
34483 */
34484#define DDRPHY_DX8LCDLR5_RESERVED_24_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR5_RESERVED_24_16_SHIFT)) & DDRPHY_DX8LCDLR5_RESERVED_24_16_MASK)
34485#define DDRPHY_DX8LCDLR5_RESERVED_31_25_MASK (0xFE000000U)
34486#define DDRPHY_DX8LCDLR5_RESERVED_31_25_SHIFT (25U)
34487/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
34488 */
34489#define DDRPHY_DX8LCDLR5_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8LCDLR5_RESERVED_31_25_SHIFT)) & DDRPHY_DX8LCDLR5_RESERVED_31_25_MASK)
34490/*! @} */
34491
34492/*! @name DX8MDLR0 - DATX8 n Master Delay Line Register 0 */
34493/*! @{ */
34494#define DDRPHY_DX8MDLR0_IPRD_MASK (0x1FFU)
34495#define DDRPHY_DX8MDLR0_IPRD_SHIFT (0U)
34496/*! IPRD - Initial Period
34497 */
34498#define DDRPHY_DX8MDLR0_IPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8MDLR0_IPRD_SHIFT)) & DDRPHY_DX8MDLR0_IPRD_MASK)
34499#define DDRPHY_DX8MDLR0_RESERVED_15_9_MASK (0xFE00U)
34500#define DDRPHY_DX8MDLR0_RESERVED_15_9_SHIFT (9U)
34501/*! RESERVED_15_9 - Reserved. Return zeroes on reads.
34502 */
34503#define DDRPHY_DX8MDLR0_RESERVED_15_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8MDLR0_RESERVED_15_9_SHIFT)) & DDRPHY_DX8MDLR0_RESERVED_15_9_MASK)
34504#define DDRPHY_DX8MDLR0_TPRD_MASK (0x1FF0000U)
34505#define DDRPHY_DX8MDLR0_TPRD_SHIFT (16U)
34506/*! TPRD - Target Period
34507 */
34508#define DDRPHY_DX8MDLR0_TPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8MDLR0_TPRD_SHIFT)) & DDRPHY_DX8MDLR0_TPRD_MASK)
34509#define DDRPHY_DX8MDLR0_RESERVED_31_25_MASK (0xFE000000U)
34510#define DDRPHY_DX8MDLR0_RESERVED_31_25_SHIFT (25U)
34511/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
34512 */
34513#define DDRPHY_DX8MDLR0_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8MDLR0_RESERVED_31_25_SHIFT)) & DDRPHY_DX8MDLR0_RESERVED_31_25_MASK)
34514/*! @} */
34515
34516/*! @name DX8MDLR1 - DATX8 n Master Delay Line Register 1 */
34517/*! @{ */
34518#define DDRPHY_DX8MDLR1_MDLD_MASK (0x1FFU)
34519#define DDRPHY_DX8MDLR1_MDLD_SHIFT (0U)
34520/*! MDLD - MDL Delay
34521 */
34522#define DDRPHY_DX8MDLR1_MDLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8MDLR1_MDLD_SHIFT)) & DDRPHY_DX8MDLR1_MDLD_MASK)
34523#define DDRPHY_DX8MDLR1_RESERVED_31_9_MASK (0xFFFFFE00U)
34524#define DDRPHY_DX8MDLR1_RESERVED_31_9_SHIFT (9U)
34525/*! RESERVED_31_9 - Reserved. Return zeroes on reads.
34526 */
34527#define DDRPHY_DX8MDLR1_RESERVED_31_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8MDLR1_RESERVED_31_9_SHIFT)) & DDRPHY_DX8MDLR1_RESERVED_31_9_MASK)
34528/*! @} */
34529
34530/*! @name DX8GTR0 - DATX8 n General Timing Register 0 */
34531/*! @{ */
34532#define DDRPHY_DX8GTR0_DGSL_MASK (0x1FU)
34533#define DDRPHY_DX8GTR0_DGSL_SHIFT (0U)
34534/*! DGSL - DQS Gating System Latency
34535 */
34536#define DDRPHY_DX8GTR0_DGSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_DGSL_SHIFT)) & DDRPHY_DX8GTR0_DGSL_MASK)
34537#define DDRPHY_DX8GTR0_RESERVED_7_5_MASK (0xE0U)
34538#define DDRPHY_DX8GTR0_RESERVED_7_5_SHIFT (5U)
34539/*! RESERVED_7_5 - Reserved. Return zeroes on reads.
34540 */
34541#define DDRPHY_DX8GTR0_RESERVED_7_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_RESERVED_7_5_SHIFT)) & DDRPHY_DX8GTR0_RESERVED_7_5_MASK)
34542#define DDRPHY_DX8GTR0_RESERVED_12_8_MASK (0x1F00U)
34543#define DDRPHY_DX8GTR0_RESERVED_12_8_SHIFT (8U)
34544/*! RESERVED_12_8 - Reserved. Caution, do not write to this register field.
34545 */
34546#define DDRPHY_DX8GTR0_RESERVED_12_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_RESERVED_12_8_SHIFT)) & DDRPHY_DX8GTR0_RESERVED_12_8_MASK)
34547#define DDRPHY_DX8GTR0_RESERVED_15_13_MASK (0xE000U)
34548#define DDRPHY_DX8GTR0_RESERVED_15_13_SHIFT (13U)
34549/*! RESERVED_15_13 - Reserved. Return zeroes on reads.
34550 */
34551#define DDRPHY_DX8GTR0_RESERVED_15_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_RESERVED_15_13_SHIFT)) & DDRPHY_DX8GTR0_RESERVED_15_13_MASK)
34552#define DDRPHY_DX8GTR0_WLSL_MASK (0xF0000U)
34553#define DDRPHY_DX8GTR0_WLSL_SHIFT (16U)
34554/*! WLSL - Write Leveling System Latency
34555 */
34556#define DDRPHY_DX8GTR0_WLSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_WLSL_SHIFT)) & DDRPHY_DX8GTR0_WLSL_MASK)
34557#define DDRPHY_DX8GTR0_RESERVED_23_20_MASK (0xF00000U)
34558#define DDRPHY_DX8GTR0_RESERVED_23_20_SHIFT (20U)
34559/*! RESERVED_23_20 - Reserved. Caution, do not write to this register field.
34560 */
34561#define DDRPHY_DX8GTR0_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_RESERVED_23_20_SHIFT)) & DDRPHY_DX8GTR0_RESERVED_23_20_MASK)
34562#define DDRPHY_DX8GTR0_WDQSL_MASK (0x7000000U)
34563#define DDRPHY_DX8GTR0_WDQSL_SHIFT (24U)
34564/*! WDQSL - DQ Write Path Latency Pipeline
34565 */
34566#define DDRPHY_DX8GTR0_WDQSL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_WDQSL_SHIFT)) & DDRPHY_DX8GTR0_WDQSL_MASK)
34567#define DDRPHY_DX8GTR0_RESERVED_31_24_MASK (0xF8000000U)
34568#define DDRPHY_DX8GTR0_RESERVED_31_24_SHIFT (27U)
34569/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
34570 */
34571#define DDRPHY_DX8GTR0_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GTR0_RESERVED_31_24_SHIFT)) & DDRPHY_DX8GTR0_RESERVED_31_24_MASK)
34572/*! @} */
34573
34574/*! @name DX8RSR0 - DATX8 n Rank Status Register 0 */
34575/*! @{ */
34576#define DDRPHY_DX8RSR0_QSGERR_MASK (0xFFFFU)
34577#define DDRPHY_DX8RSR0_QSGERR_SHIFT (0U)
34578/*! QSGERR - DQS Gate Training Error
34579 */
34580#define DDRPHY_DX8RSR0_QSGERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR0_QSGERR_SHIFT)) & DDRPHY_DX8RSR0_QSGERR_MASK)
34581#define DDRPHY_DX8RSR0_RESERVED_31_16_MASK (0xFFFF0000U)
34582#define DDRPHY_DX8RSR0_RESERVED_31_16_SHIFT (16U)
34583/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
34584 */
34585#define DDRPHY_DX8RSR0_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR0_RESERVED_31_16_SHIFT)) & DDRPHY_DX8RSR0_RESERVED_31_16_MASK)
34586/*! @} */
34587
34588/*! @name DX8RSR1 - DATX8 n Rank Status Register 1 */
34589/*! @{ */
34590#define DDRPHY_DX8RSR1_RDLVLERR_MASK (0xFFFFU)
34591#define DDRPHY_DX8RSR1_RDLVLERR_SHIFT (0U)
34592/*! RDLVLERR - Read Leveling Error
34593 */
34594#define DDRPHY_DX8RSR1_RDLVLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR1_RDLVLERR_SHIFT)) & DDRPHY_DX8RSR1_RDLVLERR_MASK)
34595#define DDRPHY_DX8RSR1_RESERVED_31_16_MASK (0xFFFF0000U)
34596#define DDRPHY_DX8RSR1_RESERVED_31_16_SHIFT (16U)
34597/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
34598 */
34599#define DDRPHY_DX8RSR1_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR1_RESERVED_31_16_SHIFT)) & DDRPHY_DX8RSR1_RESERVED_31_16_MASK)
34600/*! @} */
34601
34602/*! @name DX8RSR2 - DATX8 n Rank Status Register 2 */
34603/*! @{ */
34604#define DDRPHY_DX8RSR2_WLAWN_MASK (0xFFFFU)
34605#define DDRPHY_DX8RSR2_WLAWN_SHIFT (0U)
34606/*! WLAWN - Write Latency Adjustment (DQS off on some DQ lines) Warning
34607 */
34608#define DDRPHY_DX8RSR2_WLAWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR2_WLAWN_SHIFT)) & DDRPHY_DX8RSR2_WLAWN_MASK)
34609#define DDRPHY_DX8RSR2_RESERVED_31_16_MASK (0xFFFF0000U)
34610#define DDRPHY_DX8RSR2_RESERVED_31_16_SHIFT (16U)
34611/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
34612 */
34613#define DDRPHY_DX8RSR2_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR2_RESERVED_31_16_SHIFT)) & DDRPHY_DX8RSR2_RESERVED_31_16_MASK)
34614/*! @} */
34615
34616/*! @name DX8RSR3 - DATX8 n Rank Status Register 3 */
34617/*! @{ */
34618#define DDRPHY_DX8RSR3_WLAERR_MASK (0xFFFFU)
34619#define DDRPHY_DX8RSR3_WLAERR_SHIFT (0U)
34620/*! WLAERR - Write Leveling Adjustment Error
34621 */
34622#define DDRPHY_DX8RSR3_WLAERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR3_WLAERR_SHIFT)) & DDRPHY_DX8RSR3_WLAERR_MASK)
34623#define DDRPHY_DX8RSR3_RESERVED_31_16_MASK (0xFFFF0000U)
34624#define DDRPHY_DX8RSR3_RESERVED_31_16_SHIFT (16U)
34625/*! RESERVED_31_16 - Reserved. Return zeroes on reads.
34626 */
34627#define DDRPHY_DX8RSR3_RESERVED_31_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8RSR3_RESERVED_31_16_SHIFT)) & DDRPHY_DX8RSR3_RESERVED_31_16_MASK)
34628/*! @} */
34629
34630/*! @name DX8GSR0 - DATX8 n General Status Register 0 */
34631/*! @{ */
34632#define DDRPHY_DX8GSR0_WDQCAL_MASK (0x1U)
34633#define DDRPHY_DX8GSR0_WDQCAL_SHIFT (0U)
34634/*! WDQCAL - Write DQ Calibration
34635 */
34636#define DDRPHY_DX8GSR0_WDQCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_WDQCAL_SHIFT)) & DDRPHY_DX8GSR0_WDQCAL_MASK)
34637#define DDRPHY_DX8GSR0_RDQSCAL_MASK (0x2U)
34638#define DDRPHY_DX8GSR0_RDQSCAL_SHIFT (1U)
34639/*! RDQSCAL - Read DQS Calibration
34640 */
34641#define DDRPHY_DX8GSR0_RDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_RDQSCAL_SHIFT)) & DDRPHY_DX8GSR0_RDQSCAL_MASK)
34642#define DDRPHY_DX8GSR0_RDQSNCAL_MASK (0x4U)
34643#define DDRPHY_DX8GSR0_RDQSNCAL_SHIFT (2U)
34644/*! RDQSNCAL - Read DQS# Calibration
34645 */
34646#define DDRPHY_DX8GSR0_RDQSNCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_RDQSNCAL_SHIFT)) & DDRPHY_DX8GSR0_RDQSNCAL_MASK)
34647#define DDRPHY_DX8GSR0_GDQSCAL_MASK (0x8U)
34648#define DDRPHY_DX8GSR0_GDQSCAL_SHIFT (3U)
34649/*! GDQSCAL - Read DQS gating Calibration
34650 */
34651#define DDRPHY_DX8GSR0_GDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_GDQSCAL_SHIFT)) & DDRPHY_DX8GSR0_GDQSCAL_MASK)
34652#define DDRPHY_DX8GSR0_WLCAL_MASK (0x10U)
34653#define DDRPHY_DX8GSR0_WLCAL_SHIFT (4U)
34654/*! WLCAL - Write Leveling Calibration
34655 */
34656#define DDRPHY_DX8GSR0_WLCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_WLCAL_SHIFT)) & DDRPHY_DX8GSR0_WLCAL_MASK)
34657#define DDRPHY_DX8GSR0_WLDONE_MASK (0x20U)
34658#define DDRPHY_DX8GSR0_WLDONE_SHIFT (5U)
34659/*! WLDONE - Write Leveling Done
34660 */
34661#define DDRPHY_DX8GSR0_WLDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_WLDONE_SHIFT)) & DDRPHY_DX8GSR0_WLDONE_MASK)
34662#define DDRPHY_DX8GSR0_WLERR_MASK (0x40U)
34663#define DDRPHY_DX8GSR0_WLERR_SHIFT (6U)
34664/*! WLERR - Write Leveling Error
34665 */
34666#define DDRPHY_DX8GSR0_WLERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_WLERR_SHIFT)) & DDRPHY_DX8GSR0_WLERR_MASK)
34667#define DDRPHY_DX8GSR0_WLPRD_MASK (0xFF80U)
34668#define DDRPHY_DX8GSR0_WLPRD_SHIFT (7U)
34669/*! WLPRD - Write Leveling Period
34670 */
34671#define DDRPHY_DX8GSR0_WLPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_WLPRD_SHIFT)) & DDRPHY_DX8GSR0_WLPRD_MASK)
34672#define DDRPHY_DX8GSR0_DPLOCK_MASK (0x10000U)
34673#define DDRPHY_DX8GSR0_DPLOCK_SHIFT (16U)
34674/*! DPLOCK - DATX8 PLL Lock
34675 */
34676#define DDRPHY_DX8GSR0_DPLOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_DPLOCK_SHIFT)) & DDRPHY_DX8GSR0_DPLOCK_MASK)
34677#define DDRPHY_DX8GSR0_GDQSPRD_MASK (0x3FE0000U)
34678#define DDRPHY_DX8GSR0_GDQSPRD_SHIFT (17U)
34679/*! GDQSPRD - Read DQS gating Period
34680 */
34681#define DDRPHY_DX8GSR0_GDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_GDQSPRD_SHIFT)) & DDRPHY_DX8GSR0_GDQSPRD_MASK)
34682#define DDRPHY_DX8GSR0_RESERVED_29_26_MASK (0x3C000000U)
34683#define DDRPHY_DX8GSR0_RESERVED_29_26_SHIFT (26U)
34684/*! RESERVED_29_26 - Reserved. Returns zeroes on reads.
34685 */
34686#define DDRPHY_DX8GSR0_RESERVED_29_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_RESERVED_29_26_SHIFT)) & DDRPHY_DX8GSR0_RESERVED_29_26_MASK)
34687#define DDRPHY_DX8GSR0_WLDQ_MASK (0x40000000U)
34688#define DDRPHY_DX8GSR0_WLDQ_SHIFT (30U)
34689/*! WLDQ - Write Leveling DQ Status
34690 */
34691#define DDRPHY_DX8GSR0_WLDQ(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_WLDQ_SHIFT)) & DDRPHY_DX8GSR0_WLDQ_MASK)
34692#define DDRPHY_DX8GSR0_RESERVED_31_MASK (0x80000000U)
34693#define DDRPHY_DX8GSR0_RESERVED_31_SHIFT (31U)
34694/*! RESERVED_31 - Reserved. Returns zeroes on reads.
34695 */
34696#define DDRPHY_DX8GSR0_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR0_RESERVED_31_SHIFT)) & DDRPHY_DX8GSR0_RESERVED_31_MASK)
34697/*! @} */
34698
34699/*! @name DX8GSR1 - DATX8 n General Status Register 1 */
34700/*! @{ */
34701#define DDRPHY_DX8GSR1_DLTDONE_MASK (0x1U)
34702#define DDRPHY_DX8GSR1_DLTDONE_SHIFT (0U)
34703/*! DLTDONE - Delay Line Test Done
34704 */
34705#define DDRPHY_DX8GSR1_DLTDONE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR1_DLTDONE_SHIFT)) & DDRPHY_DX8GSR1_DLTDONE_MASK)
34706#define DDRPHY_DX8GSR1_DLTCODE_MASK (0x1FFFFFEU)
34707#define DDRPHY_DX8GSR1_DLTCODE_SHIFT (1U)
34708/*! DLTCODE - Delay Line Test Code
34709 */
34710#define DDRPHY_DX8GSR1_DLTCODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR1_DLTCODE_SHIFT)) & DDRPHY_DX8GSR1_DLTCODE_MASK)
34711#define DDRPHY_DX8GSR1_RESERVED_31_25_MASK (0xFE000000U)
34712#define DDRPHY_DX8GSR1_RESERVED_31_25_SHIFT (25U)
34713/*! RESERVED_31_25 - Reserved. Returns zeroes on reads.
34714 */
34715#define DDRPHY_DX8GSR1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8GSR1_RESERVED_31_25_MASK)
34716/*! @} */
34717
34718/*! @name DX8GSR2 - DATX8 n General Status Register 2 */
34719/*! @{ */
34720#define DDRPHY_DX8GSR2_RDERR_MASK (0x1U)
34721#define DDRPHY_DX8GSR2_RDERR_SHIFT (0U)
34722/*! RDERR - Read Bit Deskew Error
34723 */
34724#define DDRPHY_DX8GSR2_RDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_RDERR_SHIFT)) & DDRPHY_DX8GSR2_RDERR_MASK)
34725#define DDRPHY_DX8GSR2_RDWN_MASK (0x2U)
34726#define DDRPHY_DX8GSR2_RDWN_SHIFT (1U)
34727/*! RDWN - Read Bit Deskew Warning
34728 */
34729#define DDRPHY_DX8GSR2_RDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_RDWN_SHIFT)) & DDRPHY_DX8GSR2_RDWN_MASK)
34730#define DDRPHY_DX8GSR2_WDERR_MASK (0x4U)
34731#define DDRPHY_DX8GSR2_WDERR_SHIFT (2U)
34732/*! WDERR - Write Bit Deskew Error
34733 */
34734#define DDRPHY_DX8GSR2_WDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_WDERR_SHIFT)) & DDRPHY_DX8GSR2_WDERR_MASK)
34735#define DDRPHY_DX8GSR2_WDWN_MASK (0x8U)
34736#define DDRPHY_DX8GSR2_WDWN_SHIFT (3U)
34737/*! WDWN - Write Bit Deskew Warning
34738 */
34739#define DDRPHY_DX8GSR2_WDWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_WDWN_SHIFT)) & DDRPHY_DX8GSR2_WDWN_MASK)
34740#define DDRPHY_DX8GSR2_REERR_MASK (0x10U)
34741#define DDRPHY_DX8GSR2_REERR_SHIFT (4U)
34742/*! REERR - Read Eye Centering Error
34743 */
34744#define DDRPHY_DX8GSR2_REERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_REERR_SHIFT)) & DDRPHY_DX8GSR2_REERR_MASK)
34745#define DDRPHY_DX8GSR2_REWN_MASK (0x20U)
34746#define DDRPHY_DX8GSR2_REWN_SHIFT (5U)
34747/*! REWN - Read Eye Centering Warning
34748 */
34749#define DDRPHY_DX8GSR2_REWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_REWN_SHIFT)) & DDRPHY_DX8GSR2_REWN_MASK)
34750#define DDRPHY_DX8GSR2_WEERR_MASK (0x40U)
34751#define DDRPHY_DX8GSR2_WEERR_SHIFT (6U)
34752/*! WEERR - Write Eye Centering Error
34753 */
34754#define DDRPHY_DX8GSR2_WEERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_WEERR_SHIFT)) & DDRPHY_DX8GSR2_WEERR_MASK)
34755#define DDRPHY_DX8GSR2_WEWN_MASK (0x80U)
34756#define DDRPHY_DX8GSR2_WEWN_SHIFT (7U)
34757/*! WEWN - Write Eye Centering Warning
34758 */
34759#define DDRPHY_DX8GSR2_WEWN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_WEWN_SHIFT)) & DDRPHY_DX8GSR2_WEWN_MASK)
34760#define DDRPHY_DX8GSR2_ESTAT_MASK (0xF00U)
34761#define DDRPHY_DX8GSR2_ESTAT_SHIFT (8U)
34762/*! ESTAT - Error Status
34763 */
34764#define DDRPHY_DX8GSR2_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_ESTAT_SHIFT)) & DDRPHY_DX8GSR2_ESTAT_MASK)
34765#define DDRPHY_DX8GSR2_DQS2DQERR_MASK (0xFF000U)
34766#define DDRPHY_DX8GSR2_DQS2DQERR_SHIFT (12U)
34767/*! DQS2DQERR - Write DQS2DQ Training Error
34768 */
34769#define DDRPHY_DX8GSR2_DQS2DQERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_DQS2DQERR_SHIFT)) & DDRPHY_DX8GSR2_DQS2DQERR_MASK)
34770#define DDRPHY_DX8GSR2_SRDERR_MASK (0x100000U)
34771#define DDRPHY_DX8GSR2_SRDERR_SHIFT (20U)
34772/*! SRDERR - Static Read Error
34773 */
34774#define DDRPHY_DX8GSR2_SRDERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_SRDERR_SHIFT)) & DDRPHY_DX8GSR2_SRDERR_MASK)
34775#define DDRPHY_DX8GSR2_RESERVED_21_MASK (0x200000U)
34776#define DDRPHY_DX8GSR2_RESERVED_21_SHIFT (21U)
34777/*! RESERVED_21 - Reserved. Return zeroes on reads.
34778 */
34779#define DDRPHY_DX8GSR2_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_RESERVED_21_SHIFT)) & DDRPHY_DX8GSR2_RESERVED_21_MASK)
34780#define DDRPHY_DX8GSR2_GSDQSCAL_MASK (0x400000U)
34781#define DDRPHY_DX8GSR2_GSDQSCAL_SHIFT (22U)
34782/*! GSDQSCAL - Read DQS Gating Status Calibration
34783 */
34784#define DDRPHY_DX8GSR2_GSDQSCAL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_GSDQSCAL_SHIFT)) & DDRPHY_DX8GSR2_GSDQSCAL_MASK)
34785#define DDRPHY_DX8GSR2_GSDQSPRD_MASK (0xFF800000U)
34786#define DDRPHY_DX8GSR2_GSDQSPRD_SHIFT (23U)
34787/*! GSDQSPRD - Read DQS gating Status Period
34788 */
34789#define DDRPHY_DX8GSR2_GSDQSPRD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR2_GSDQSPRD_SHIFT)) & DDRPHY_DX8GSR2_GSDQSPRD_MASK)
34790/*! @} */
34791
34792/*! @name DX8GSR3 - DATX8 n General Status Register 3 */
34793/*! @{ */
34794#define DDRPHY_DX8GSR3_SRDPC_MASK (0x3U)
34795#define DDRPHY_DX8GSR3_SRDPC_SHIFT (0U)
34796/*! SRDPC - Static Read Delay Pass Count
34797 */
34798#define DDRPHY_DX8GSR3_SRDPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_SRDPC_SHIFT)) & DDRPHY_DX8GSR3_SRDPC_MASK)
34799#define DDRPHY_DX8GSR3_RESERVED_7_2_MASK (0xFCU)
34800#define DDRPHY_DX8GSR3_RESERVED_7_2_SHIFT (2U)
34801/*! RESERVED_7_2 - Reserved. Return zeroes on reads.
34802 */
34803#define DDRPHY_DX8GSR3_RESERVED_7_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_RESERVED_7_2_SHIFT)) & DDRPHY_DX8GSR3_RESERVED_7_2_MASK)
34804#define DDRPHY_DX8GSR3_HVERR_MASK (0xF00U)
34805#define DDRPHY_DX8GSR3_HVERR_SHIFT (8U)
34806/*! HVERR - Host VREF Training Error
34807 */
34808#define DDRPHY_DX8GSR3_HVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_HVERR_SHIFT)) & DDRPHY_DX8GSR3_HVERR_MASK)
34809#define DDRPHY_DX8GSR3_HVWRN_MASK (0xF000U)
34810#define DDRPHY_DX8GSR3_HVWRN_SHIFT (12U)
34811/*! HVWRN - Host VREF Training Warning
34812 */
34813#define DDRPHY_DX8GSR3_HVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_HVWRN_SHIFT)) & DDRPHY_DX8GSR3_HVWRN_MASK)
34814#define DDRPHY_DX8GSR3_DVERR_MASK (0xF0000U)
34815#define DDRPHY_DX8GSR3_DVERR_SHIFT (16U)
34816/*! DVERR - DRAM VREF Training Error
34817 */
34818#define DDRPHY_DX8GSR3_DVERR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_DVERR_SHIFT)) & DDRPHY_DX8GSR3_DVERR_MASK)
34819#define DDRPHY_DX8GSR3_DVWRN_MASK (0xF00000U)
34820#define DDRPHY_DX8GSR3_DVWRN_SHIFT (20U)
34821/*! DVWRN - DRAM VREF Training Warning
34822 */
34823#define DDRPHY_DX8GSR3_DVWRN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_DVWRN_SHIFT)) & DDRPHY_DX8GSR3_DVWRN_MASK)
34824#define DDRPHY_DX8GSR3_ESTAT_MASK (0x7000000U)
34825#define DDRPHY_DX8GSR3_ESTAT_SHIFT (24U)
34826/*! ESTAT - VREF Training Error Status Code
34827 */
34828#define DDRPHY_DX8GSR3_ESTAT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_ESTAT_SHIFT)) & DDRPHY_DX8GSR3_ESTAT_MASK)
34829#define DDRPHY_DX8GSR3_RESERVED_31_27_MASK (0xF8000000U)
34830#define DDRPHY_DX8GSR3_RESERVED_31_27_SHIFT (27U)
34831/*! RESERVED_31_27 - Reserved. Return zeroes on reads.
34832 */
34833#define DDRPHY_DX8GSR3_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR3_RESERVED_31_27_SHIFT)) & DDRPHY_DX8GSR3_RESERVED_31_27_MASK)
34834/*! @} */
34835
34836/*! @name DX8GSR4 - DATX8 n General Status Register 4 */
34837/*! @{ */
34838#define DDRPHY_DX8GSR4_RESERVED_0_MASK (0x1U)
34839#define DDRPHY_DX8GSR4_RESERVED_0_SHIFT (0U)
34840/*! RESERVED_0 - Reserved. Return zeroes on reads.
34841 */
34842#define DDRPHY_DX8GSR4_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_0_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_0_MASK)
34843#define DDRPHY_DX8GSR4_RESERVED_1_MASK (0x2U)
34844#define DDRPHY_DX8GSR4_RESERVED_1_SHIFT (1U)
34845/*! RESERVED_1 - Reserved. Return zeroes on reads.
34846 */
34847#define DDRPHY_DX8GSR4_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_1_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_1_MASK)
34848#define DDRPHY_DX8GSR4_RESERVED_2_MASK (0x4U)
34849#define DDRPHY_DX8GSR4_RESERVED_2_SHIFT (2U)
34850/*! RESERVED_2 - Reserved. Return zeroes on reads.
34851 */
34852#define DDRPHY_DX8GSR4_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_2_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_2_MASK)
34853#define DDRPHY_DX8GSR4_RESERVED_3_MASK (0x8U)
34854#define DDRPHY_DX8GSR4_RESERVED_3_SHIFT (3U)
34855/*! RESERVED_3 - Reserved. Return zeroes on reads.
34856 */
34857#define DDRPHY_DX8GSR4_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_3_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_3_MASK)
34858#define DDRPHY_DX8GSR4_RESERVED_4_MASK (0x10U)
34859#define DDRPHY_DX8GSR4_RESERVED_4_SHIFT (4U)
34860/*! RESERVED_4 - Reserved. Return zeroes on reads.
34861 */
34862#define DDRPHY_DX8GSR4_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_4_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_4_MASK)
34863#define DDRPHY_DX8GSR4_RESERVED_5_MASK (0x20U)
34864#define DDRPHY_DX8GSR4_RESERVED_5_SHIFT (5U)
34865/*! RESERVED_5 - Reserved. Return zeroes on reads.
34866 */
34867#define DDRPHY_DX8GSR4_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_5_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_5_MASK)
34868#define DDRPHY_DX8GSR4_RESERVED_6_MASK (0x40U)
34869#define DDRPHY_DX8GSR4_RESERVED_6_SHIFT (6U)
34870/*! RESERVED_6 - Reserved. Return zeroes on reads.
34871 */
34872#define DDRPHY_DX8GSR4_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_6_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_6_MASK)
34873#define DDRPHY_DX8GSR4_RESERVED_15_7_MASK (0xFF80U)
34874#define DDRPHY_DX8GSR4_RESERVED_15_7_SHIFT (7U)
34875/*! RESERVED_15_7 - Reserved. Return zeroes on reads.
34876 */
34877#define DDRPHY_DX8GSR4_RESERVED_15_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_15_7_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_15_7_MASK)
34878#define DDRPHY_DX8GSR4_RESERVED_16_MASK (0x10000U)
34879#define DDRPHY_DX8GSR4_RESERVED_16_SHIFT (16U)
34880/*! RESERVED_16 - Reserved. Return zeroes on reads.
34881 */
34882#define DDRPHY_DX8GSR4_RESERVED_16(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_16_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_16_MASK)
34883#define DDRPHY_DX8GSR4_RESERVED_25_17_MASK (0x3FE0000U)
34884#define DDRPHY_DX8GSR4_RESERVED_25_17_SHIFT (17U)
34885/*! RESERVED_25_17 - Reserved. Return zeroes on reads.
34886 */
34887#define DDRPHY_DX8GSR4_RESERVED_25_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_25_17_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_25_17_MASK)
34888#define DDRPHY_DX8GSR4_RESERVED_31_26_MASK (0xFC000000U)
34889#define DDRPHY_DX8GSR4_RESERVED_31_26_SHIFT (26U)
34890/*! RESERVED_31_26 - Reserved. Returns zeroes on reads.
34891 */
34892#define DDRPHY_DX8GSR4_RESERVED_31_26(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR4_RESERVED_31_26_SHIFT)) & DDRPHY_DX8GSR4_RESERVED_31_26_MASK)
34893/*! @} */
34894
34895/*! @name DX8GSR5 - DATX8 n General Status Register 5 */
34896/*! @{ */
34897#define DDRPHY_DX8GSR5_RESERVED_0_MASK (0x1U)
34898#define DDRPHY_DX8GSR5_RESERVED_0_SHIFT (0U)
34899/*! RESERVED_0 - Reserved. Return zeroes on reads.
34900 */
34901#define DDRPHY_DX8GSR5_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_0_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_0_MASK)
34902#define DDRPHY_DX8GSR5_RESERVED_1_MASK (0x2U)
34903#define DDRPHY_DX8GSR5_RESERVED_1_SHIFT (1U)
34904/*! RESERVED_1 - Reserved. Return zeroes on reads.
34905 */
34906#define DDRPHY_DX8GSR5_RESERVED_1(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_1_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_1_MASK)
34907#define DDRPHY_DX8GSR5_RESERVED_2_MASK (0x4U)
34908#define DDRPHY_DX8GSR5_RESERVED_2_SHIFT (2U)
34909/*! RESERVED_2 - Reserved. Return zeroes on reads.
34910 */
34911#define DDRPHY_DX8GSR5_RESERVED_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_2_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_2_MASK)
34912#define DDRPHY_DX8GSR5_RESERVED_3_MASK (0x8U)
34913#define DDRPHY_DX8GSR5_RESERVED_3_SHIFT (3U)
34914/*! RESERVED_3 - Reserved. Return zeroes on reads.
34915 */
34916#define DDRPHY_DX8GSR5_RESERVED_3(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_3_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_3_MASK)
34917#define DDRPHY_DX8GSR5_RESERVED_4_MASK (0x10U)
34918#define DDRPHY_DX8GSR5_RESERVED_4_SHIFT (4U)
34919/*! RESERVED_4 - Reserved. Return zeroes on reads.
34920 */
34921#define DDRPHY_DX8GSR5_RESERVED_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_4_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_4_MASK)
34922#define DDRPHY_DX8GSR5_RESERVED_5_MASK (0x20U)
34923#define DDRPHY_DX8GSR5_RESERVED_5_SHIFT (5U)
34924/*! RESERVED_5 - Reserved. Return zeroes on reads.
34925 */
34926#define DDRPHY_DX8GSR5_RESERVED_5(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_5_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_5_MASK)
34927#define DDRPHY_DX8GSR5_RESERVED_6_MASK (0x40U)
34928#define DDRPHY_DX8GSR5_RESERVED_6_SHIFT (6U)
34929/*! RESERVED_6 - Reserved. Return zeroes on reads.
34930 */
34931#define DDRPHY_DX8GSR5_RESERVED_6(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_6_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_6_MASK)
34932#define DDRPHY_DX8GSR5_RESERVED_7_MASK (0x80U)
34933#define DDRPHY_DX8GSR5_RESERVED_7_SHIFT (7U)
34934/*! RESERVED_7 - Reserved. Return zeroes on reads.
34935 */
34936#define DDRPHY_DX8GSR5_RESERVED_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_7_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_7_MASK)
34937#define DDRPHY_DX8GSR5_RESERVED_11_8_MASK (0xF00U)
34938#define DDRPHY_DX8GSR5_RESERVED_11_8_SHIFT (8U)
34939/*! RESERVED_11_8 - Reserved. Return zeroes on reads.
34940 */
34941#define DDRPHY_DX8GSR5_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_11_8_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_11_8_MASK)
34942#define DDRPHY_DX8GSR5_RESERVED_19_12_MASK (0xFF000U)
34943#define DDRPHY_DX8GSR5_RESERVED_19_12_SHIFT (12U)
34944/*! RESERVED_19_12 - Reserved. Return zeroes on reads.
34945 */
34946#define DDRPHY_DX8GSR5_RESERVED_19_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_19_12_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_19_12_MASK)
34947#define DDRPHY_DX8GSR5_RESERVED_20_MASK (0x100000U)
34948#define DDRPHY_DX8GSR5_RESERVED_20_SHIFT (20U)
34949/*! RESERVED_20 - Reserved. Return zeroes on reads.
34950 */
34951#define DDRPHY_DX8GSR5_RESERVED_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_20_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_20_MASK)
34952#define DDRPHY_DX8GSR5_RESERVED_21_MASK (0x200000U)
34953#define DDRPHY_DX8GSR5_RESERVED_21_SHIFT (21U)
34954/*! RESERVED_21 - Reserved. Return zeroes on reads.
34955 */
34956#define DDRPHY_DX8GSR5_RESERVED_21(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_21_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_21_MASK)
34957#define DDRPHY_DX8GSR5_RESERVED_22_MASK (0x400000U)
34958#define DDRPHY_DX8GSR5_RESERVED_22_SHIFT (22U)
34959/*! RESERVED_22 - Reserved. Return zeroes on reads.
34960 */
34961#define DDRPHY_DX8GSR5_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_22_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_22_MASK)
34962#define DDRPHY_DX8GSR5_RESERVED_31_23_MASK (0xFF800000U)
34963#define DDRPHY_DX8GSR5_RESERVED_31_23_SHIFT (23U)
34964/*! RESERVED_31_23 - Reserved. Return zeroes on reads.
34965 */
34966#define DDRPHY_DX8GSR5_RESERVED_31_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR5_RESERVED_31_23_SHIFT)) & DDRPHY_DX8GSR5_RESERVED_31_23_MASK)
34967/*! @} */
34968
34969/*! @name DX8GSR6 - DATX8 n General Status Register 6 */
34970/*! @{ */
34971#define DDRPHY_DX8GSR6_RESERVED_1_0_MASK (0x3U)
34972#define DDRPHY_DX8GSR6_RESERVED_1_0_SHIFT (0U)
34973/*! RESERVED_1_0 - Reserved. Return zeroes on reads.
34974 */
34975#define DDRPHY_DX8GSR6_RESERVED_1_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_1_0_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_1_0_MASK)
34976#define DDRPHY_DX8GSR6_RESERVED_3_2_MASK (0xCU)
34977#define DDRPHY_DX8GSR6_RESERVED_3_2_SHIFT (2U)
34978/*! RESERVED_3_2 - Reserved. Return zeroes on reads.
34979 */
34980#define DDRPHY_DX8GSR6_RESERVED_3_2(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_3_2_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_3_2_MASK)
34981#define DDRPHY_DX8GSR6_RESERVED_7_4_MASK (0xF0U)
34982#define DDRPHY_DX8GSR6_RESERVED_7_4_SHIFT (4U)
34983/*! RESERVED_7_4 - Reserved. Return zeroes on reads.
34984 */
34985#define DDRPHY_DX8GSR6_RESERVED_7_4(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_7_4_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_7_4_MASK)
34986#define DDRPHY_DX8GSR6_RESERVED_11_8_MASK (0xF00U)
34987#define DDRPHY_DX8GSR6_RESERVED_11_8_SHIFT (8U)
34988/*! RESERVED_11_8 - Reserved. Return zeroes on reads.
34989 */
34990#define DDRPHY_DX8GSR6_RESERVED_11_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_11_8_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_11_8_MASK)
34991#define DDRPHY_DX8GSR6_RESERVED_15_12_MASK (0xF000U)
34992#define DDRPHY_DX8GSR6_RESERVED_15_12_SHIFT (12U)
34993/*! RESERVED_15_12 - Reserved. Return zeroes on reads.
34994 */
34995#define DDRPHY_DX8GSR6_RESERVED_15_12(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_15_12_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_15_12_MASK)
34996#define DDRPHY_DX8GSR6_RESERVED_19_15_MASK (0xF0000U)
34997#define DDRPHY_DX8GSR6_RESERVED_19_15_SHIFT (16U)
34998/*! RESERVED_19_15 - Reserved. Return zeroes on reads.
34999 */
35000#define DDRPHY_DX8GSR6_RESERVED_19_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_19_15_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_19_15_MASK)
35001#define DDRPHY_DX8GSR6_RESERVED_23_20_MASK (0xF00000U)
35002#define DDRPHY_DX8GSR6_RESERVED_23_20_SHIFT (20U)
35003/*! RESERVED_23_20 - Reserved. Return zeroes on reads.
35004 */
35005#define DDRPHY_DX8GSR6_RESERVED_23_20(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_23_20_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_23_20_MASK)
35006#define DDRPHY_DX8GSR6_RESERVED_31_24_MASK (0xFF000000U)
35007#define DDRPHY_DX8GSR6_RESERVED_31_24_SHIFT (24U)
35008/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
35009 */
35010#define DDRPHY_DX8GSR6_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8GSR6_RESERVED_31_24_SHIFT)) & DDRPHY_DX8GSR6_RESERVED_31_24_MASK)
35011/*! @} */
35012
35013/*! @name DX8SL0OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */
35014/*! @{ */
35015#define DDRPHY_DX8SL0OSC_OSCEN_MASK (0x1U)
35016#define DDRPHY_DX8SL0OSC_OSCEN_SHIFT (0U)
35017/*! OSCEN - Oscillator Enable
35018 */
35019#define DDRPHY_DX8SL0OSC_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL0OSC_OSCEN_MASK)
35020#define DDRPHY_DX8SL0OSC_OSCDIV_MASK (0x1EU)
35021#define DDRPHY_DX8SL0OSC_OSCDIV_SHIFT (1U)
35022/*! OSCDIV - Oscillator Mode Division
35023 */
35024#define DDRPHY_DX8SL0OSC_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL0OSC_OSCDIV_MASK)
35025#define DDRPHY_DX8SL0OSC_OSCWDL_MASK (0x60U)
35026#define DDRPHY_DX8SL0OSC_OSCWDL_SHIFT (5U)
35027/*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select
35028 */
35029#define DDRPHY_DX8SL0OSC_OSCWDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL0OSC_OSCWDL_MASK)
35030#define DDRPHY_DX8SL0OSC_RESERVED_8_7_MASK (0x180U)
35031#define DDRPHY_DX8SL0OSC_RESERVED_8_7_SHIFT (7U)
35032/*! RESERVED_8_7 - Reserved. Caution, do not write to this register field.
35033 */
35034#define DDRPHY_DX8SL0OSC_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL0OSC_RESERVED_8_7_MASK)
35035#define DDRPHY_DX8SL0OSC_OSCWDDL_MASK (0x600U)
35036#define DDRPHY_DX8SL0OSC_OSCWDDL_SHIFT (9U)
35037/*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select
35038 */
35039#define DDRPHY_DX8SL0OSC_OSCWDDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL0OSC_OSCWDDL_MASK)
35040#define DDRPHY_DX8SL0OSC_RESERVED_12_11_MASK (0x1800U)
35041#define DDRPHY_DX8SL0OSC_RESERVED_12_11_SHIFT (11U)
35042/*! RESERVED_12_11 - Reserved. Caution, do not write to this register field.
35043 */
35044#define DDRPHY_DX8SL0OSC_RESERVED_12_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL0OSC_RESERVED_12_11_MASK)
35045#define DDRPHY_DX8SL0OSC_DLTMODE_MASK (0x2000U)
35046#define DDRPHY_DX8SL0OSC_DLTMODE_SHIFT (13U)
35047/*! DLTMODE - Delay Line Test Mode
35048 */
35049#define DDRPHY_DX8SL0OSC_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL0OSC_DLTMODE_MASK)
35050#define DDRPHY_DX8SL0OSC_DLTST_MASK (0x4000U)
35051#define DDRPHY_DX8SL0OSC_DLTST_SHIFT (14U)
35052/*! DLTST - Delay Line Test Start
35053 */
35054#define DDRPHY_DX8SL0OSC_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_DLTST_SHIFT)) & DDRPHY_DX8SL0OSC_DLTST_MASK)
35055#define DDRPHY_DX8SL0OSC_PHYFRST_MASK (0x8000U)
35056#define DDRPHY_DX8SL0OSC_PHYFRST_SHIFT (15U)
35057/*! PHYFRST - PHY FIFO Reset
35058 */
35059#define DDRPHY_DX8SL0OSC_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL0OSC_PHYFRST_MASK)
35060#define DDRPHY_DX8SL0OSC_PHYHRST_MASK (0x10000U)
35061#define DDRPHY_DX8SL0OSC_PHYHRST_SHIFT (16U)
35062/*! PHYHRST - PHY High-Speed Reset
35063 */
35064#define DDRPHY_DX8SL0OSC_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL0OSC_PHYHRST_MASK)
35065#define DDRPHY_DX8SL0OSC_LBDQSS_MASK (0x20000U)
35066#define DDRPHY_DX8SL0OSC_LBDQSS_SHIFT (17U)
35067/*! LBDQSS - Loopback DQS Shift
35068 */
35069#define DDRPHY_DX8SL0OSC_LBDQSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL0OSC_LBDQSS_MASK)
35070#define DDRPHY_DX8SL0OSC_LBGDQS_MASK (0xC0000U)
35071#define DDRPHY_DX8SL0OSC_LBGDQS_SHIFT (18U)
35072/*! LBGDQS - Loopback DQS Gating
35073 */
35074#define DDRPHY_DX8SL0OSC_LBGDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL0OSC_LBGDQS_MASK)
35075#define DDRPHY_DX8SL0OSC_LBGSDQS_MASK (0x100000U)
35076#define DDRPHY_DX8SL0OSC_LBGSDQS_SHIFT (20U)
35077/*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
35078 */
35079#define DDRPHY_DX8SL0OSC_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL0OSC_LBGSDQS_MASK)
35080#define DDRPHY_DX8SL0OSC_LBMODE_MASK (0x200000U)
35081#define DDRPHY_DX8SL0OSC_LBMODE_SHIFT (21U)
35082/*! LBMODE - Loopback Mode
35083 */
35084#define DDRPHY_DX8SL0OSC_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL0OSC_LBMODE_MASK)
35085#define DDRPHY_DX8SL0OSC_CLKLEVEL_MASK (0xC00000U)
35086#define DDRPHY_DX8SL0OSC_CLKLEVEL_SHIFT (22U)
35087/*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled.
35088 */
35089#define DDRPHY_DX8SL0OSC_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL0OSC_CLKLEVEL_MASK)
35090#define DDRPHY_DX8SL0OSC_GATEDXCTLCLK_MASK (0x3000000U)
35091#define DDRPHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT (24U)
35092/*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk
35093 */
35094#define DDRPHY_DX8SL0OSC_GATEDXCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL0OSC_GATEDXCTLCLK_MASK)
35095#define DDRPHY_DX8SL0OSC_GATEDXDDRCLK_MASK (0xC000000U)
35096#define DDRPHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT (26U)
35097/*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk
35098 */
35099#define DDRPHY_DX8SL0OSC_GATEDXDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL0OSC_GATEDXDDRCLK_MASK)
35100#define DDRPHY_DX8SL0OSC_GATEDXRDCLK_MASK (0x30000000U)
35101#define DDRPHY_DX8SL0OSC_GATEDXRDCLK_SHIFT (28U)
35102/*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk
35103 */
35104#define DDRPHY_DX8SL0OSC_GATEDXRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL0OSC_GATEDXRDCLK_MASK)
35105#define DDRPHY_DX8SL0OSC_RESERVED_31_30_MASK (0xC0000000U)
35106#define DDRPHY_DX8SL0OSC_RESERVED_31_30_SHIFT (30U)
35107/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
35108 */
35109#define DDRPHY_DX8SL0OSC_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL0OSC_RESERVED_31_30_MASK)
35110/*! @} */
35111
35112/*! @name DX8SL0PLLCR0 - DAXT8 0-1 PLL Control Register 0 */
35113/*! @{ */
35114#define DDRPHY_DX8SL0PLLCR0_DTC_MASK (0xFU)
35115#define DDRPHY_DX8SL0PLLCR0_DTC_SHIFT (0U)
35116/*! DTC - Digital Test Control
35117 */
35118#define DDRPHY_DX8SL0PLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL0PLLCR0_DTC_MASK)
35119#define DDRPHY_DX8SL0PLLCR0_ATC_MASK (0xF0U)
35120#define DDRPHY_DX8SL0PLLCR0_ATC_SHIFT (4U)
35121/*! ATC - Analog Test Control
35122 */
35123#define DDRPHY_DX8SL0PLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL0PLLCR0_ATC_MASK)
35124#define DDRPHY_DX8SL0PLLCR0_ATOEN_MASK (0x100U)
35125#define DDRPHY_DX8SL0PLLCR0_ATOEN_SHIFT (8U)
35126/*! ATOEN - Analog Test Enable (ATOEN)
35127 */
35128#define DDRPHY_DX8SL0PLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL0PLLCR0_ATOEN_MASK)
35129#define DDRPHY_DX8SL0PLLCR0_RESERVED_11_9_MASK (0xE00U)
35130#define DDRPHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT (9U)
35131/*! RESERVED_11_9 - Reserved. Return zeroes on reads.
35132 */
35133#define DDRPHY_DX8SL0PLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL0PLLCR0_RESERVED_11_9_MASK)
35134#define DDRPHY_DX8SL0PLLCR0_GSHIFT_MASK (0x1000U)
35135#define DDRPHY_DX8SL0PLLCR0_GSHIFT_SHIFT (12U)
35136/*! GSHIFT - Gear Shift
35137 */
35138#define DDRPHY_DX8SL0PLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL0PLLCR0_GSHIFT_MASK)
35139#define DDRPHY_DX8SL0PLLCR0_CPIC_MASK (0x1E000U)
35140#define DDRPHY_DX8SL0PLLCR0_CPIC_SHIFT (13U)
35141/*! CPIC - Charge Pump Integrating Current Control
35142 */
35143#define DDRPHY_DX8SL0PLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL0PLLCR0_CPIC_MASK)
35144#define DDRPHY_DX8SL0PLLCR0_CPPC_MASK (0x7E0000U)
35145#define DDRPHY_DX8SL0PLLCR0_CPPC_SHIFT (17U)
35146/*! CPPC - Charge Pump Proportional Current Control
35147 */
35148#define DDRPHY_DX8SL0PLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL0PLLCR0_CPPC_MASK)
35149#define DDRPHY_DX8SL0PLLCR0_RLOCKM_MASK (0x800000U)
35150#define DDRPHY_DX8SL0PLLCR0_RLOCKM_SHIFT (23U)
35151/*! RLOCKM - Relock Mode
35152 */
35153#define DDRPHY_DX8SL0PLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL0PLLCR0_RLOCKM_MASK)
35154#define DDRPHY_DX8SL0PLLCR0_FRQSEL_MASK (0xF000000U)
35155#define DDRPHY_DX8SL0PLLCR0_FRQSEL_SHIFT (24U)
35156/*! FRQSEL - PLL Frequency Select
35157 */
35158#define DDRPHY_DX8SL0PLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL0PLLCR0_FRQSEL_MASK)
35159#define DDRPHY_DX8SL0PLLCR0_RSTOPM_MASK (0x10000000U)
35160#define DDRPHY_DX8SL0PLLCR0_RSTOPM_SHIFT (28U)
35161/*! RSTOPM - Reference Stop Mode
35162 */
35163#define DDRPHY_DX8SL0PLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL0PLLCR0_RSTOPM_MASK)
35164#define DDRPHY_DX8SL0PLLCR0_PLLPD_MASK (0x20000000U)
35165#define DDRPHY_DX8SL0PLLCR0_PLLPD_SHIFT (29U)
35166/*! PLLPD - PLL Power Down
35167 */
35168#define DDRPHY_DX8SL0PLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL0PLLCR0_PLLPD_MASK)
35169#define DDRPHY_DX8SL0PLLCR0_PLLRST_MASK (0x40000000U)
35170#define DDRPHY_DX8SL0PLLCR0_PLLRST_SHIFT (30U)
35171/*! PLLRST - PLL Reset
35172 */
35173#define DDRPHY_DX8SL0PLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL0PLLCR0_PLLRST_MASK)
35174#define DDRPHY_DX8SL0PLLCR0_PLLBYP_MASK (0x80000000U)
35175#define DDRPHY_DX8SL0PLLCR0_PLLBYP_SHIFT (31U)
35176/*! PLLBYP - PLL Bypass
35177 */
35178#define DDRPHY_DX8SL0PLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL0PLLCR0_PLLBYP_MASK)
35179/*! @} */
35180
35181/*! @name DX8SL0PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */
35182/*! @{ */
35183#define DDRPHY_DX8SL0PLLCR1_LOCKDS_MASK (0x1U)
35184#define DDRPHY_DX8SL0PLLCR1_LOCKDS_SHIFT (0U)
35185/*! LOCKDS - Lock Detector Select
35186 */
35187#define DDRPHY_DX8SL0PLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL0PLLCR1_LOCKDS_MASK)
35188#define DDRPHY_DX8SL0PLLCR1_LOCKCS_MASK (0x2U)
35189#define DDRPHY_DX8SL0PLLCR1_LOCKCS_SHIFT (1U)
35190/*! LOCKCS - Lock Detector Counter Select
35191 */
35192#define DDRPHY_DX8SL0PLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL0PLLCR1_LOCKCS_MASK)
35193#define DDRPHY_DX8SL0PLLCR1_LOCKPS_MASK (0x4U)
35194#define DDRPHY_DX8SL0PLLCR1_LOCKPS_SHIFT (2U)
35195/*! LOCKPS - Lock Detector Phase Select
35196 */
35197#define DDRPHY_DX8SL0PLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL0PLLCR1_LOCKPS_MASK)
35198#define DDRPHY_DX8SL0PLLCR1_BYPVDD_MASK (0x8U)
35199#define DDRPHY_DX8SL0PLLCR1_BYPVDD_SHIFT (3U)
35200/*! BYPVDD - PLL VDD voltage level control
35201 */
35202#define DDRPHY_DX8SL0PLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL0PLLCR1_BYPVDD_MASK)
35203#define DDRPHY_DX8SL0PLLCR1_BYPVREGDIG_MASK (0x10U)
35204#define DDRPHY_DX8SL0PLLCR1_BYPVREGDIG_SHIFT (4U)
35205/*! BYPVREGDIG - Bypass PLL vreg_dig
35206 */
35207#define DDRPHY_DX8SL0PLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL0PLLCR1_BYPVREGDIG_MASK)
35208#define DDRPHY_DX8SL0PLLCR1_BYPVREGCP_MASK (0x20U)
35209#define DDRPHY_DX8SL0PLLCR1_BYPVREGCP_SHIFT (5U)
35210/*! BYPVREGCP - Bypass PLL vreg_cp
35211 */
35212#define DDRPHY_DX8SL0PLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL0PLLCR1_BYPVREGCP_MASK)
35213#define DDRPHY_DX8SL0PLLCR1_PLLPROG_MASK (0x3FFFC0U)
35214#define DDRPHY_DX8SL0PLLCR1_PLLPROG_SHIFT (6U)
35215/*! PLLPROG - Connects to the PLL PLL_PROG bus.
35216 */
35217#define DDRPHY_DX8SL0PLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL0PLLCR1_PLLPROG_MASK)
35218#define DDRPHY_DX8SL0PLLCR1_RESERVED_31_22_MASK (0xFFC00000U)
35219#define DDRPHY_DX8SL0PLLCR1_RESERVED_31_22_SHIFT (22U)
35220/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
35221 */
35222#define DDRPHY_DX8SL0PLLCR1_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL0PLLCR1_RESERVED_31_22_MASK)
35223/*! @} */
35224
35225/*! @name DX8SL0PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */
35226/*! @{ */
35227#define DDRPHY_DX8SL0PLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU)
35228#define DDRPHY_DX8SL0PLLCR2_PLLCTRL_31_0_SHIFT (0U)
35229/*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
35230 */
35231#define DDRPHY_DX8SL0PLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL0PLLCR2_PLLCTRL_31_0_MASK)
35232/*! @} */
35233
35234/*! @name DX8SL0PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */
35235/*! @{ */
35236#define DDRPHY_DX8SL0PLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU)
35237#define DDRPHY_DX8SL0PLLCR3_PLLCTRL_63_32_SHIFT (0U)
35238/*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
35239 */
35240#define DDRPHY_DX8SL0PLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL0PLLCR3_PLLCTRL_63_32_MASK)
35241/*! @} */
35242
35243/*! @name DX8SL0PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */
35244/*! @{ */
35245#define DDRPHY_DX8SL0PLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU)
35246#define DDRPHY_DX8SL0PLLCR4_PLLCTRL_95_64_SHIFT (0U)
35247/*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
35248 */
35249#define DDRPHY_DX8SL0PLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL0PLLCR4_PLLCTRL_95_64_MASK)
35250/*! @} */
35251
35252/*! @name DX8SL0PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */
35253/*! @{ */
35254#define DDRPHY_DX8SL0PLLCR5_PLLCTRL_103_96_MASK (0xFFU)
35255#define DDRPHY_DX8SL0PLLCR5_PLLCTRL_103_96_SHIFT (0U)
35256/*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
35257 */
35258#define DDRPHY_DX8SL0PLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL0PLLCR5_PLLCTRL_103_96_MASK)
35259#define DDRPHY_DX8SL0PLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U)
35260#define DDRPHY_DX8SL0PLLCR5_RESERVED_31_8_SHIFT (8U)
35261/*! RESERVED_31_8 - Reserved. Return zeroes on reads.
35262 */
35263#define DDRPHY_DX8SL0PLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL0PLLCR5_RESERVED_31_8_MASK)
35264/*! @} */
35265
35266/*! @name DX8SL0DQSCTL - DATX8 0-1 DQS Control Register */
35267/*! @{ */
35268#define DDRPHY_DX8SL0DQSCTL_DQSRES_MASK (0xFU)
35269#define DDRPHY_DX8SL0DQSCTL_DQSRES_SHIFT (0U)
35270/*! DQSRES - DQS Resistor
35271 */
35272#define DDRPHY_DX8SL0DQSCTL_DQSRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL0DQSCTL_DQSRES_MASK)
35273#define DDRPHY_DX8SL0DQSCTL_DQSNRES_MASK (0xF0U)
35274#define DDRPHY_DX8SL0DQSCTL_DQSNRES_SHIFT (4U)
35275/*! DQSNRES - DQS_N Resistor
35276 */
35277#define DDRPHY_DX8SL0DQSCTL_DQSNRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL0DQSCTL_DQSNRES_MASK)
35278#define DDRPHY_DX8SL0DQSCTL_DXSR_MASK (0x300U)
35279#define DDRPHY_DX8SL0DQSCTL_DXSR_SHIFT (8U)
35280/*! DXSR - Data Slew Rate
35281 */
35282#define DDRPHY_DX8SL0DQSCTL_DXSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL0DQSCTL_DXSR_MASK)
35283#define DDRPHY_DX8SL0DQSCTL_RESERVED_12_10_MASK (0x1C00U)
35284#define DDRPHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT (10U)
35285/*! RESERVED_12_10 - Reserved. Return zeroes on reads.
35286 */
35287#define DDRPHY_DX8SL0DQSCTL_RESERVED_12_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL0DQSCTL_RESERVED_12_10_MASK)
35288#define DDRPHY_DX8SL0DQSCTL_UDQIOM_MASK (0x2000U)
35289#define DDRPHY_DX8SL0DQSCTL_UDQIOM_SHIFT (13U)
35290/*! UDQIOM - Unused DQ I/O Mode
35291 */
35292#define DDRPHY_DX8SL0DQSCTL_UDQIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL0DQSCTL_UDQIOM_MASK)
35293#define DDRPHY_DX8SL0DQSCTL_QSCNTEN_MASK (0x4000U)
35294#define DDRPHY_DX8SL0DQSCTL_QSCNTEN_SHIFT (14U)
35295/*! QSCNTEN - QS Counter Enable
35296 */
35297#define DDRPHY_DX8SL0DQSCTL_QSCNTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL0DQSCTL_QSCNTEN_MASK)
35298#define DDRPHY_DX8SL0DQSCTL_RESERVED_16_15_MASK (0x18000U)
35299#define DDRPHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT (15U)
35300/*! RESERVED_16_15 - Reserved. Return zeroes on reads.
35301 */
35302#define DDRPHY_DX8SL0DQSCTL_RESERVED_16_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL0DQSCTL_RESERVED_16_15_MASK)
35303#define DDRPHY_DX8SL0DQSCTL_LPIOPD_MASK (0x20000U)
35304#define DDRPHY_DX8SL0DQSCTL_LPIOPD_SHIFT (17U)
35305/*! LPIOPD - Low Power I/O Power Down
35306 */
35307#define DDRPHY_DX8SL0DQSCTL_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL0DQSCTL_LPIOPD_MASK)
35308#define DDRPHY_DX8SL0DQSCTL_LPPLLPD_MASK (0x40000U)
35309#define DDRPHY_DX8SL0DQSCTL_LPPLLPD_SHIFT (18U)
35310/*! LPPLLPD - Low Power PLL Power Down
35311 */
35312#define DDRPHY_DX8SL0DQSCTL_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL0DQSCTL_LPPLLPD_MASK)
35313#define DDRPHY_DX8SL0DQSCTL_DQSGX_MASK (0x180000U)
35314#define DDRPHY_DX8SL0DQSCTL_DQSGX_SHIFT (19U)
35315/*! DQSGX - DQS Gate Extension
35316 */
35317#define DDRPHY_DX8SL0DQSCTL_DQSGX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL0DQSCTL_DQSGX_MASK)
35318#define DDRPHY_DX8SL0DQSCTL_WRRMODE_MASK (0x200000U)
35319#define DDRPHY_DX8SL0DQSCTL_WRRMODE_SHIFT (21U)
35320/*! WRRMODE - Write Path Rise-to-Rise Mode
35321 */
35322#define DDRPHY_DX8SL0DQSCTL_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL0DQSCTL_WRRMODE_MASK)
35323#define DDRPHY_DX8SL0DQSCTL_RESERVED_23_22_MASK (0xC00000U)
35324#define DDRPHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT (22U)
35325/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
35326 */
35327#define DDRPHY_DX8SL0DQSCTL_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL0DQSCTL_RESERVED_23_22_MASK)
35328#define DDRPHY_DX8SL0DQSCTL_RRRMODE_MASK (0x1000000U)
35329#define DDRPHY_DX8SL0DQSCTL_RRRMODE_SHIFT (24U)
35330/*! RRRMODE - Read Path Rise-to-Rise Mode
35331 */
35332#define DDRPHY_DX8SL0DQSCTL_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL0DQSCTL_RRRMODE_MASK)
35333#define DDRPHY_DX8SL0DQSCTL_RESERVED_31_25_MASK (0xFE000000U)
35334#define DDRPHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT (25U)
35335/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
35336 */
35337#define DDRPHY_DX8SL0DQSCTL_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL0DQSCTL_RESERVED_31_25_MASK)
35338/*! @} */
35339
35340/*! @name DX8SL0TRNCTL - DATX8 0-1 Training Control Register */
35341/*! @{ */
35342#define DDRPHY_DX8SL0TRNCTL_RESERVED_31_0_MASK (0xFFFFFFFFU)
35343#define DDRPHY_DX8SL0TRNCTL_RESERVED_31_0_SHIFT (0U)
35344/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
35345 */
35346#define DDRPHY_DX8SL0TRNCTL_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL0TRNCTL_RESERVED_31_0_MASK)
35347/*! @} */
35348
35349/*! @name DX8SL0DDLCTL - DATX8 0-1 DDL Control Register */
35350/*! @{ */
35351#define DDRPHY_DX8SL0DDLCTL_DDLBYPMODE_MASK (0x3U)
35352#define DDRPHY_DX8SL0DDLCTL_DDLBYPMODE_SHIFT (0U)
35353/*! DDLBYPMODE - Controls DDL Bypass Mode
35354 */
35355#define DDRPHY_DX8SL0DDLCTL_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL0DDLCTL_DDLBYPMODE_MASK)
35356#define DDRPHY_DX8SL0DDLCTL_DXDDLBYP_MASK (0x3FFFCU)
35357#define DDRPHY_DX8SL0DDLCTL_DXDDLBYP_SHIFT (2U)
35358/*! DXDDLBYP - DATX8 DDL Bypass
35359 */
35360#define DDRPHY_DX8SL0DDLCTL_DXDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL0DDLCTL_DXDDLBYP_MASK)
35361#define DDRPHY_DX8SL0DDLCTL_DXDDLLD_MASK (0x7C0000U)
35362#define DDRPHY_DX8SL0DDLCTL_DXDDLLD_SHIFT (18U)
35363/*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load
35364 */
35365#define DDRPHY_DX8SL0DDLCTL_DXDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL0DDLCTL_DXDDLLD_MASK)
35366#define DDRPHY_DX8SL0DDLCTL_RESERVED_24_23_MASK (0x1800000U)
35367#define DDRPHY_DX8SL0DDLCTL_RESERVED_24_23_SHIFT (23U)
35368/*! RESERVED_24_23 - Reserved. Return zeroes on reads.
35369 */
35370#define DDRPHY_DX8SL0DDLCTL_RESERVED_24_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL0DDLCTL_RESERVED_24_23_MASK)
35371#define DDRPHY_DX8SL0DDLCTL_DXDDLLDT_MASK (0x2000000U)
35372#define DDRPHY_DX8SL0DDLCTL_DXDDLLDT_SHIFT (25U)
35373/*! DXDDLLDT - DX DDL Load Type
35374 */
35375#define DDRPHY_DX8SL0DDLCTL_DXDDLLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL0DDLCTL_DXDDLLDT_MASK)
35376#define DDRPHY_DX8SL0DDLCTL_DLYLDTM_MASK (0x4000000U)
35377#define DDRPHY_DX8SL0DDLCTL_DLYLDTM_SHIFT (26U)
35378/*! DLYLDTM - Delay Load Timing
35379 */
35380#define DDRPHY_DX8SL0DDLCTL_DLYLDTM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL0DDLCTL_DLYLDTM_MASK)
35381#define DDRPHY_DX8SL0DDLCTL_RESERVED_31_27_MASK (0xF8000000U)
35382#define DDRPHY_DX8SL0DDLCTL_RESERVED_31_27_SHIFT (27U)
35383/*! RESERVED_31_27 - Reserved. Return zeroes on reads.
35384 */
35385#define DDRPHY_DX8SL0DDLCTL_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL0DDLCTL_RESERVED_31_27_MASK)
35386/*! @} */
35387
35388/*! @name DX8SL0DXCTL1 - DATX8 0-1 DX Control Register 1 */
35389/*! @{ */
35390#define DDRPHY_DX8SL0DXCTL1_RESERVED_15_0_MASK (0xFFFFU)
35391#define DDRPHY_DX8SL0DXCTL1_RESERVED_15_0_SHIFT (0U)
35392/*! RESERVED_15_0 - Reserved. Return zeroes on reads.
35393 */
35394#define DDRPHY_DX8SL0DXCTL1_RESERVED_15_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL0DXCTL1_RESERVED_15_0_MASK)
35395#define DDRPHY_DX8SL0DXCTL1_DXTMODE_MASK (0x10000U)
35396#define DDRPHY_DX8SL0DXCTL1_DXTMODE_SHIFT (16U)
35397/*! DXTMODE - DATX8 Test Mode
35398 */
35399#define DDRPHY_DX8SL0DXCTL1_DXTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXTMODE_MASK)
35400#define DDRPHY_DX8SL0DXCTL1_DXGDBYP_MASK (0x20000U)
35401#define DDRPHY_DX8SL0DXCTL1_DXGDBYP_SHIFT (17U)
35402/*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode
35403 */
35404#define DDRPHY_DX8SL0DXCTL1_DXGDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXGDBYP_MASK)
35405#define DDRPHY_DX8SL0DXCTL1_DXQSDBYP_MASK (0x40000U)
35406#define DDRPHY_DX8SL0DXCTL1_DXQSDBYP_SHIFT (18U)
35407/*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode
35408 */
35409#define DDRPHY_DX8SL0DXCTL1_DXQSDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXQSDBYP_MASK)
35410#define DDRPHY_DX8SL0DXCTL1_DXGSMD_MASK (0x80000U)
35411#define DDRPHY_DX8SL0DXCTL1_DXGSMD_SHIFT (19U)
35412/*! DXGSMD - Read DQS Gating Status Mode
35413 */
35414#define DDRPHY_DX8SL0DXCTL1_DXGSMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXGSMD_MASK)
35415#define DDRPHY_DX8SL0DXCTL1_DXDTOSEL_MASK (0x300000U)
35416#define DDRPHY_DX8SL0DXCTL1_DXDTOSEL_SHIFT (20U)
35417/*! DXDTOSEL - DATX8 Digital Test Output Select
35418 */
35419#define DDRPHY_DX8SL0DXCTL1_DXDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXDTOSEL_MASK)
35420#define DDRPHY_DX8SL0DXCTL1_RESERVED_22_MASK (0x400000U)
35421#define DDRPHY_DX8SL0DXCTL1_RESERVED_22_SHIFT (22U)
35422/*! RESERVED_22 - Reserved. Return zeroes on reads.
35423 */
35424#define DDRPHY_DX8SL0DXCTL1_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL0DXCTL1_RESERVED_22_MASK)
35425#define DDRPHY_DX8SL0DXCTL1_DXRCLKMD_MASK (0x800000U)
35426#define DDRPHY_DX8SL0DXCTL1_DXRCLKMD_SHIFT (23U)
35427/*! DXRCLKMD - DATX8 Read Clock Mode
35428 */
35429#define DDRPHY_DX8SL0DXCTL1_DXRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXRCLKMD_MASK)
35430#define DDRPHY_DX8SL0DXCTL1_DXCALCLK_MASK (0x1000000U)
35431#define DDRPHY_DX8SL0DXCTL1_DXCALCLK_SHIFT (24U)
35432/*! DXCALCLK - DATX Calibration Clock Select
35433 */
35434#define DDRPHY_DX8SL0DXCTL1_DXCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL0DXCTL1_DXCALCLK_MASK)
35435#define DDRPHY_DX8SL0DXCTL1_RESERVED_31_25_MASK (0xFE000000U)
35436#define DDRPHY_DX8SL0DXCTL1_RESERVED_31_25_SHIFT (25U)
35437/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
35438 */
35439#define DDRPHY_DX8SL0DXCTL1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL0DXCTL1_RESERVED_31_25_MASK)
35440/*! @} */
35441
35442/*! @name DX8SL0DXCTL2 - DATX8 0-1 DX Control Register 2 */
35443/*! @{ */
35444#define DDRPHY_DX8SL0DXCTL2_RESERVED_0_MASK (0x1U)
35445#define DDRPHY_DX8SL0DXCTL2_RESERVED_0_SHIFT (0U)
35446/*! RESERVED_0 - Reserved. Return zeroes on reads.
35447 */
35448#define DDRPHY_DX8SL0DXCTL2_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL0DXCTL2_RESERVED_0_MASK)
35449#define DDRPHY_DX8SL0DXCTL2_DQSGLB_MASK (0x6U)
35450#define DDRPHY_DX8SL0DXCTL2_DQSGLB_SHIFT (1U)
35451/*! DQSGLB - Read DQS Gate I/O Loopback
35452 */
35453#define DDRPHY_DX8SL0DXCTL2_DQSGLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL0DXCTL2_DQSGLB_MASK)
35454#define DDRPHY_DX8SL0DXCTL2_DISRST_MASK (0x8U)
35455#define DDRPHY_DX8SL0DXCTL2_DISRST_SHIFT (3U)
35456/*! DISRST - Disables the Read FIFO Reset
35457 */
35458#define DDRPHY_DX8SL0DXCTL2_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL0DXCTL2_DISRST_MASK)
35459#define DDRPHY_DX8SL0DXCTL2_RDMODE_MASK (0x30U)
35460#define DDRPHY_DX8SL0DXCTL2_RDMODE_SHIFT (4U)
35461/*! RDMODE - DATX8 Receive FIFO Read Mode
35462 */
35463#define DDRPHY_DX8SL0DXCTL2_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL0DXCTL2_RDMODE_MASK)
35464#define DDRPHY_DX8SL0DXCTL2_PRFBYP_MASK (0x40U)
35465#define DDRPHY_DX8SL0DXCTL2_PRFBYP_SHIFT (6U)
35466/*! PRFBYP - PUB Read FIFO Bypass
35467 */
35468#define DDRPHY_DX8SL0DXCTL2_PRFBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL0DXCTL2_PRFBYP_MASK)
35469#define DDRPHY_DX8SL0DXCTL2_WDBI_MASK (0x80U)
35470#define DDRPHY_DX8SL0DXCTL2_WDBI_SHIFT (7U)
35471/*! WDBI - Write Data Bus Inversion Enable
35472 */
35473#define DDRPHY_DX8SL0DXCTL2_WDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL0DXCTL2_WDBI_MASK)
35474#define DDRPHY_DX8SL0DXCTL2_RDBI_MASK (0x100U)
35475#define DDRPHY_DX8SL0DXCTL2_RDBI_SHIFT (8U)
35476/*! RDBI - Read Data Bus Inversion Enable
35477 */
35478#define DDRPHY_DX8SL0DXCTL2_RDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL0DXCTL2_RDBI_MASK)
35479#define DDRPHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK (0x1E00U)
35480#define DDRPHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT (9U)
35481/*! LPWAKEUP_THRSH - Low Power Wakeup Threshold
35482 */
35483#define DDRPHY_DX8SL0DXCTL2_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK)
35484#define DDRPHY_DX8SL0DXCTL2_RESERVED_14_13_MASK (0x6000U)
35485#define DDRPHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT (13U)
35486/*! RESERVED_14_13 - Reserved. Return zeroes on reads.
35487 */
35488#define DDRPHY_DX8SL0DXCTL2_RESERVED_14_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL0DXCTL2_RESERVED_14_13_MASK)
35489#define DDRPHY_DX8SL0DXCTL2_IOLB_MASK (0x8000U)
35490#define DDRPHY_DX8SL0DXCTL2_IOLB_SHIFT (15U)
35491/*! IOLB - I/O Loopback Select
35492 */
35493#define DDRPHY_DX8SL0DXCTL2_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL0DXCTL2_IOLB_MASK)
35494#define DDRPHY_DX8SL0DXCTL2_IOAG_MASK (0x10000U)
35495#define DDRPHY_DX8SL0DXCTL2_IOAG_SHIFT (16U)
35496/*! IOAG - I/O Assisted Gate Select
35497 */
35498#define DDRPHY_DX8SL0DXCTL2_IOAG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL0DXCTL2_IOAG_MASK)
35499#define DDRPHY_DX8SL0DXCTL2_RESERVED_17_MASK (0x20000U)
35500#define DDRPHY_DX8SL0DXCTL2_RESERVED_17_SHIFT (17U)
35501/*! RESERVED_17 - Reserved. Return zeroes on reads.
35502 */
35503#define DDRPHY_DX8SL0DXCTL2_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL0DXCTL2_RESERVED_17_MASK)
35504#define DDRPHY_DX8SL0DXCTL2_PREOEX_MASK (0xC0000U)
35505#define DDRPHY_DX8SL0DXCTL2_PREOEX_SHIFT (18U)
35506/*! PREOEX - OE Extension during Pre-amble
35507 */
35508#define DDRPHY_DX8SL0DXCTL2_PREOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL0DXCTL2_PREOEX_MASK)
35509#define DDRPHY_DX8SL0DXCTL2_POSOEX_MASK (0x700000U)
35510#define DDRPHY_DX8SL0DXCTL2_POSOEX_SHIFT (20U)
35511/*! POSOEX - OX Extension during Post-amble
35512 */
35513#define DDRPHY_DX8SL0DXCTL2_POSOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL0DXCTL2_POSOEX_MASK)
35514#define DDRPHY_DX8SL0DXCTL2_CRDEN_MASK (0x800000U)
35515#define DDRPHY_DX8SL0DXCTL2_CRDEN_SHIFT (23U)
35516/*! CRDEN - Configurable Read Data Enable
35517 */
35518#define DDRPHY_DX8SL0DXCTL2_CRDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL0DXCTL2_CRDEN_MASK)
35519#define DDRPHY_DX8SL0DXCTL2_RESERVED_31_24_MASK (0xFF000000U)
35520#define DDRPHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT (24U)
35521/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
35522 */
35523#define DDRPHY_DX8SL0DXCTL2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL0DXCTL2_RESERVED_31_24_MASK)
35524/*! @} */
35525
35526/*! @name DX8SL0IOCR - DATX8 0-1 I/O Configuration Register */
35527/*! @{ */
35528#define DDRPHY_DX8SL0IOCR_DXRXM_MASK (0x7FFU)
35529#define DDRPHY_DX8SL0IOCR_DXRXM_SHIFT (0U)
35530/*! DXRXM - DX IO Receiver Mode
35531 */
35532#define DDRPHY_DX8SL0IOCR_DXRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL0IOCR_DXRXM_MASK)
35533#define DDRPHY_DX8SL0IOCR_DXTXM_MASK (0x3FF800U)
35534#define DDRPHY_DX8SL0IOCR_DXTXM_SHIFT (11U)
35535/*! DXTXM - DX IO Transmitter Mode
35536 */
35537#define DDRPHY_DX8SL0IOCR_DXTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL0IOCR_DXTXM_MASK)
35538#define DDRPHY_DX8SL0IOCR_DXIOM_MASK (0x1C00000U)
35539#define DDRPHY_DX8SL0IOCR_DXIOM_SHIFT (22U)
35540/*! DXIOM - DX IO Mode
35541 */
35542#define DDRPHY_DX8SL0IOCR_DXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL0IOCR_DXIOM_MASK)
35543#define DDRPHY_DX8SL0IOCR_DXVREFIOM_MASK (0xE000000U)
35544#define DDRPHY_DX8SL0IOCR_DXVREFIOM_SHIFT (25U)
35545/*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
35546 */
35547#define DDRPHY_DX8SL0IOCR_DXVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL0IOCR_DXVREFIOM_MASK)
35548#define DDRPHY_DX8SL0IOCR_DXDACRANGE_MASK (0x70000000U)
35549#define DDRPHY_DX8SL0IOCR_DXDACRANGE_SHIFT (28U)
35550/*! DXDACRANGE - PVREF_DAC REFSEL range select
35551 */
35552#define DDRPHY_DX8SL0IOCR_DXDACRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL0IOCR_DXDACRANGE_MASK)
35553#define DDRPHY_DX8SL0IOCR_RESERVED_31_MASK (0x80000000U)
35554#define DDRPHY_DX8SL0IOCR_RESERVED_31_SHIFT (31U)
35555/*! RESERVED_31 - Reserved. Return zeroes on reads.
35556 */
35557#define DDRPHY_DX8SL0IOCR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL0IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL0IOCR_RESERVED_31_MASK)
35558/*! @} */
35559
35560/*! @name DX4SL0IOCR - DATX4 Slice 0-1 I/O Configuration Register */
35561/*! @{ */
35562#define DDRPHY_DX4SL0IOCR_RESERVED_31_0_MASK (0xFFFFFFFFU)
35563#define DDRPHY_DX4SL0IOCR_RESERVED_31_0_SHIFT (0U)
35564/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
35565 */
35566#define DDRPHY_DX4SL0IOCR_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL0IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL0IOCR_RESERVED_31_0_MASK)
35567/*! @} */
35568
35569/*! @name DX8SL1OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */
35570/*! @{ */
35571#define DDRPHY_DX8SL1OSC_OSCEN_MASK (0x1U)
35572#define DDRPHY_DX8SL1OSC_OSCEN_SHIFT (0U)
35573/*! OSCEN - Oscillator Enable
35574 */
35575#define DDRPHY_DX8SL1OSC_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL1OSC_OSCEN_MASK)
35576#define DDRPHY_DX8SL1OSC_OSCDIV_MASK (0x1EU)
35577#define DDRPHY_DX8SL1OSC_OSCDIV_SHIFT (1U)
35578/*! OSCDIV - Oscillator Mode Division
35579 */
35580#define DDRPHY_DX8SL1OSC_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL1OSC_OSCDIV_MASK)
35581#define DDRPHY_DX8SL1OSC_OSCWDL_MASK (0x60U)
35582#define DDRPHY_DX8SL1OSC_OSCWDL_SHIFT (5U)
35583/*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select
35584 */
35585#define DDRPHY_DX8SL1OSC_OSCWDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL1OSC_OSCWDL_MASK)
35586#define DDRPHY_DX8SL1OSC_RESERVED_8_7_MASK (0x180U)
35587#define DDRPHY_DX8SL1OSC_RESERVED_8_7_SHIFT (7U)
35588/*! RESERVED_8_7 - Reserved. Caution, do not write to this register field.
35589 */
35590#define DDRPHY_DX8SL1OSC_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL1OSC_RESERVED_8_7_MASK)
35591#define DDRPHY_DX8SL1OSC_OSCWDDL_MASK (0x600U)
35592#define DDRPHY_DX8SL1OSC_OSCWDDL_SHIFT (9U)
35593/*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select
35594 */
35595#define DDRPHY_DX8SL1OSC_OSCWDDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL1OSC_OSCWDDL_MASK)
35596#define DDRPHY_DX8SL1OSC_RESERVED_12_11_MASK (0x1800U)
35597#define DDRPHY_DX8SL1OSC_RESERVED_12_11_SHIFT (11U)
35598/*! RESERVED_12_11 - Reserved. Caution, do not write to this register field.
35599 */
35600#define DDRPHY_DX8SL1OSC_RESERVED_12_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL1OSC_RESERVED_12_11_MASK)
35601#define DDRPHY_DX8SL1OSC_DLTMODE_MASK (0x2000U)
35602#define DDRPHY_DX8SL1OSC_DLTMODE_SHIFT (13U)
35603/*! DLTMODE - Delay Line Test Mode
35604 */
35605#define DDRPHY_DX8SL1OSC_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL1OSC_DLTMODE_MASK)
35606#define DDRPHY_DX8SL1OSC_DLTST_MASK (0x4000U)
35607#define DDRPHY_DX8SL1OSC_DLTST_SHIFT (14U)
35608/*! DLTST - Delay Line Test Start
35609 */
35610#define DDRPHY_DX8SL1OSC_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_DLTST_SHIFT)) & DDRPHY_DX8SL1OSC_DLTST_MASK)
35611#define DDRPHY_DX8SL1OSC_PHYFRST_MASK (0x8000U)
35612#define DDRPHY_DX8SL1OSC_PHYFRST_SHIFT (15U)
35613/*! PHYFRST - PHY FIFO Reset
35614 */
35615#define DDRPHY_DX8SL1OSC_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL1OSC_PHYFRST_MASK)
35616#define DDRPHY_DX8SL1OSC_PHYHRST_MASK (0x10000U)
35617#define DDRPHY_DX8SL1OSC_PHYHRST_SHIFT (16U)
35618/*! PHYHRST - PHY High-Speed Reset
35619 */
35620#define DDRPHY_DX8SL1OSC_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL1OSC_PHYHRST_MASK)
35621#define DDRPHY_DX8SL1OSC_LBDQSS_MASK (0x20000U)
35622#define DDRPHY_DX8SL1OSC_LBDQSS_SHIFT (17U)
35623/*! LBDQSS - Loopback DQS Shift
35624 */
35625#define DDRPHY_DX8SL1OSC_LBDQSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL1OSC_LBDQSS_MASK)
35626#define DDRPHY_DX8SL1OSC_LBGDQS_MASK (0xC0000U)
35627#define DDRPHY_DX8SL1OSC_LBGDQS_SHIFT (18U)
35628/*! LBGDQS - Loopback DQS Gating
35629 */
35630#define DDRPHY_DX8SL1OSC_LBGDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL1OSC_LBGDQS_MASK)
35631#define DDRPHY_DX8SL1OSC_LBGSDQS_MASK (0x100000U)
35632#define DDRPHY_DX8SL1OSC_LBGSDQS_SHIFT (20U)
35633/*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
35634 */
35635#define DDRPHY_DX8SL1OSC_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL1OSC_LBGSDQS_MASK)
35636#define DDRPHY_DX8SL1OSC_LBMODE_MASK (0x200000U)
35637#define DDRPHY_DX8SL1OSC_LBMODE_SHIFT (21U)
35638/*! LBMODE - Loopback Mode
35639 */
35640#define DDRPHY_DX8SL1OSC_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL1OSC_LBMODE_MASK)
35641#define DDRPHY_DX8SL1OSC_CLKLEVEL_MASK (0xC00000U)
35642#define DDRPHY_DX8SL1OSC_CLKLEVEL_SHIFT (22U)
35643/*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled.
35644 */
35645#define DDRPHY_DX8SL1OSC_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL1OSC_CLKLEVEL_MASK)
35646#define DDRPHY_DX8SL1OSC_GATEDXCTLCLK_MASK (0x3000000U)
35647#define DDRPHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT (24U)
35648/*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk
35649 */
35650#define DDRPHY_DX8SL1OSC_GATEDXCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL1OSC_GATEDXCTLCLK_MASK)
35651#define DDRPHY_DX8SL1OSC_GATEDXDDRCLK_MASK (0xC000000U)
35652#define DDRPHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT (26U)
35653/*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk
35654 */
35655#define DDRPHY_DX8SL1OSC_GATEDXDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL1OSC_GATEDXDDRCLK_MASK)
35656#define DDRPHY_DX8SL1OSC_GATEDXRDCLK_MASK (0x30000000U)
35657#define DDRPHY_DX8SL1OSC_GATEDXRDCLK_SHIFT (28U)
35658/*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk
35659 */
35660#define DDRPHY_DX8SL1OSC_GATEDXRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL1OSC_GATEDXRDCLK_MASK)
35661#define DDRPHY_DX8SL1OSC_RESERVED_31_30_MASK (0xC0000000U)
35662#define DDRPHY_DX8SL1OSC_RESERVED_31_30_SHIFT (30U)
35663/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
35664 */
35665#define DDRPHY_DX8SL1OSC_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL1OSC_RESERVED_31_30_MASK)
35666/*! @} */
35667
35668/*! @name DX8SL1PLLCR0 - DAXT8 0-1 PLL Control Register 0 */
35669/*! @{ */
35670#define DDRPHY_DX8SL1PLLCR0_DTC_MASK (0xFU)
35671#define DDRPHY_DX8SL1PLLCR0_DTC_SHIFT (0U)
35672/*! DTC - Digital Test Control
35673 */
35674#define DDRPHY_DX8SL1PLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL1PLLCR0_DTC_MASK)
35675#define DDRPHY_DX8SL1PLLCR0_ATC_MASK (0xF0U)
35676#define DDRPHY_DX8SL1PLLCR0_ATC_SHIFT (4U)
35677/*! ATC - Analog Test Control
35678 */
35679#define DDRPHY_DX8SL1PLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL1PLLCR0_ATC_MASK)
35680#define DDRPHY_DX8SL1PLLCR0_ATOEN_MASK (0x100U)
35681#define DDRPHY_DX8SL1PLLCR0_ATOEN_SHIFT (8U)
35682/*! ATOEN - Analog Test Enable (ATOEN)
35683 */
35684#define DDRPHY_DX8SL1PLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL1PLLCR0_ATOEN_MASK)
35685#define DDRPHY_DX8SL1PLLCR0_RESERVED_11_9_MASK (0xE00U)
35686#define DDRPHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT (9U)
35687/*! RESERVED_11_9 - Reserved. Return zeroes on reads.
35688 */
35689#define DDRPHY_DX8SL1PLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL1PLLCR0_RESERVED_11_9_MASK)
35690#define DDRPHY_DX8SL1PLLCR0_GSHIFT_MASK (0x1000U)
35691#define DDRPHY_DX8SL1PLLCR0_GSHIFT_SHIFT (12U)
35692/*! GSHIFT - Gear Shift
35693 */
35694#define DDRPHY_DX8SL1PLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL1PLLCR0_GSHIFT_MASK)
35695#define DDRPHY_DX8SL1PLLCR0_CPIC_MASK (0x1E000U)
35696#define DDRPHY_DX8SL1PLLCR0_CPIC_SHIFT (13U)
35697/*! CPIC - Charge Pump Integrating Current Control
35698 */
35699#define DDRPHY_DX8SL1PLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL1PLLCR0_CPIC_MASK)
35700#define DDRPHY_DX8SL1PLLCR0_CPPC_MASK (0x7E0000U)
35701#define DDRPHY_DX8SL1PLLCR0_CPPC_SHIFT (17U)
35702/*! CPPC - Charge Pump Proportional Current Control
35703 */
35704#define DDRPHY_DX8SL1PLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL1PLLCR0_CPPC_MASK)
35705#define DDRPHY_DX8SL1PLLCR0_RLOCKM_MASK (0x800000U)
35706#define DDRPHY_DX8SL1PLLCR0_RLOCKM_SHIFT (23U)
35707/*! RLOCKM - Relock Mode
35708 */
35709#define DDRPHY_DX8SL1PLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL1PLLCR0_RLOCKM_MASK)
35710#define DDRPHY_DX8SL1PLLCR0_FRQSEL_MASK (0xF000000U)
35711#define DDRPHY_DX8SL1PLLCR0_FRQSEL_SHIFT (24U)
35712/*! FRQSEL - PLL Frequency Select
35713 */
35714#define DDRPHY_DX8SL1PLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL1PLLCR0_FRQSEL_MASK)
35715#define DDRPHY_DX8SL1PLLCR0_RSTOPM_MASK (0x10000000U)
35716#define DDRPHY_DX8SL1PLLCR0_RSTOPM_SHIFT (28U)
35717/*! RSTOPM - Reference Stop Mode
35718 */
35719#define DDRPHY_DX8SL1PLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL1PLLCR0_RSTOPM_MASK)
35720#define DDRPHY_DX8SL1PLLCR0_PLLPD_MASK (0x20000000U)
35721#define DDRPHY_DX8SL1PLLCR0_PLLPD_SHIFT (29U)
35722/*! PLLPD - PLL Power Down
35723 */
35724#define DDRPHY_DX8SL1PLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL1PLLCR0_PLLPD_MASK)
35725#define DDRPHY_DX8SL1PLLCR0_PLLRST_MASK (0x40000000U)
35726#define DDRPHY_DX8SL1PLLCR0_PLLRST_SHIFT (30U)
35727/*! PLLRST - PLL Reset
35728 */
35729#define DDRPHY_DX8SL1PLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL1PLLCR0_PLLRST_MASK)
35730#define DDRPHY_DX8SL1PLLCR0_PLLBYP_MASK (0x80000000U)
35731#define DDRPHY_DX8SL1PLLCR0_PLLBYP_SHIFT (31U)
35732/*! PLLBYP - PLL Bypass
35733 */
35734#define DDRPHY_DX8SL1PLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL1PLLCR0_PLLBYP_MASK)
35735/*! @} */
35736
35737/*! @name DX8SL1PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */
35738/*! @{ */
35739#define DDRPHY_DX8SL1PLLCR1_LOCKDS_MASK (0x1U)
35740#define DDRPHY_DX8SL1PLLCR1_LOCKDS_SHIFT (0U)
35741/*! LOCKDS - Lock Detector Select
35742 */
35743#define DDRPHY_DX8SL1PLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL1PLLCR1_LOCKDS_MASK)
35744#define DDRPHY_DX8SL1PLLCR1_LOCKCS_MASK (0x2U)
35745#define DDRPHY_DX8SL1PLLCR1_LOCKCS_SHIFT (1U)
35746/*! LOCKCS - Lock Detector Counter Select
35747 */
35748#define DDRPHY_DX8SL1PLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL1PLLCR1_LOCKCS_MASK)
35749#define DDRPHY_DX8SL1PLLCR1_LOCKPS_MASK (0x4U)
35750#define DDRPHY_DX8SL1PLLCR1_LOCKPS_SHIFT (2U)
35751/*! LOCKPS - Lock Detector Phase Select
35752 */
35753#define DDRPHY_DX8SL1PLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL1PLLCR1_LOCKPS_MASK)
35754#define DDRPHY_DX8SL1PLLCR1_BYPVDD_MASK (0x8U)
35755#define DDRPHY_DX8SL1PLLCR1_BYPVDD_SHIFT (3U)
35756/*! BYPVDD - PLL VDD voltage level control
35757 */
35758#define DDRPHY_DX8SL1PLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL1PLLCR1_BYPVDD_MASK)
35759#define DDRPHY_DX8SL1PLLCR1_BYPVREGDIG_MASK (0x10U)
35760#define DDRPHY_DX8SL1PLLCR1_BYPVREGDIG_SHIFT (4U)
35761/*! BYPVREGDIG - Bypass PLL vreg_dig
35762 */
35763#define DDRPHY_DX8SL1PLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL1PLLCR1_BYPVREGDIG_MASK)
35764#define DDRPHY_DX8SL1PLLCR1_BYPVREGCP_MASK (0x20U)
35765#define DDRPHY_DX8SL1PLLCR1_BYPVREGCP_SHIFT (5U)
35766/*! BYPVREGCP - Bypass PLL vreg_cp
35767 */
35768#define DDRPHY_DX8SL1PLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL1PLLCR1_BYPVREGCP_MASK)
35769#define DDRPHY_DX8SL1PLLCR1_PLLPROG_MASK (0x3FFFC0U)
35770#define DDRPHY_DX8SL1PLLCR1_PLLPROG_SHIFT (6U)
35771/*! PLLPROG - Connects to the PLL PLL_PROG bus.
35772 */
35773#define DDRPHY_DX8SL1PLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL1PLLCR1_PLLPROG_MASK)
35774#define DDRPHY_DX8SL1PLLCR1_RESERVED_31_22_MASK (0xFFC00000U)
35775#define DDRPHY_DX8SL1PLLCR1_RESERVED_31_22_SHIFT (22U)
35776/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
35777 */
35778#define DDRPHY_DX8SL1PLLCR1_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL1PLLCR1_RESERVED_31_22_MASK)
35779/*! @} */
35780
35781/*! @name DX8SL1PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */
35782/*! @{ */
35783#define DDRPHY_DX8SL1PLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU)
35784#define DDRPHY_DX8SL1PLLCR2_PLLCTRL_31_0_SHIFT (0U)
35785/*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
35786 */
35787#define DDRPHY_DX8SL1PLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL1PLLCR2_PLLCTRL_31_0_MASK)
35788/*! @} */
35789
35790/*! @name DX8SL1PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */
35791/*! @{ */
35792#define DDRPHY_DX8SL1PLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU)
35793#define DDRPHY_DX8SL1PLLCR3_PLLCTRL_63_32_SHIFT (0U)
35794/*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
35795 */
35796#define DDRPHY_DX8SL1PLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL1PLLCR3_PLLCTRL_63_32_MASK)
35797/*! @} */
35798
35799/*! @name DX8SL1PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */
35800/*! @{ */
35801#define DDRPHY_DX8SL1PLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU)
35802#define DDRPHY_DX8SL1PLLCR4_PLLCTRL_95_64_SHIFT (0U)
35803/*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
35804 */
35805#define DDRPHY_DX8SL1PLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL1PLLCR4_PLLCTRL_95_64_MASK)
35806/*! @} */
35807
35808/*! @name DX8SL1PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */
35809/*! @{ */
35810#define DDRPHY_DX8SL1PLLCR5_PLLCTRL_103_96_MASK (0xFFU)
35811#define DDRPHY_DX8SL1PLLCR5_PLLCTRL_103_96_SHIFT (0U)
35812/*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
35813 */
35814#define DDRPHY_DX8SL1PLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL1PLLCR5_PLLCTRL_103_96_MASK)
35815#define DDRPHY_DX8SL1PLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U)
35816#define DDRPHY_DX8SL1PLLCR5_RESERVED_31_8_SHIFT (8U)
35817/*! RESERVED_31_8 - Reserved. Return zeroes on reads.
35818 */
35819#define DDRPHY_DX8SL1PLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL1PLLCR5_RESERVED_31_8_MASK)
35820/*! @} */
35821
35822/*! @name DX8SL1DQSCTL - DATX8 0-1 DQS Control Register */
35823/*! @{ */
35824#define DDRPHY_DX8SL1DQSCTL_DQSRES_MASK (0xFU)
35825#define DDRPHY_DX8SL1DQSCTL_DQSRES_SHIFT (0U)
35826/*! DQSRES - DQS Resistor
35827 */
35828#define DDRPHY_DX8SL1DQSCTL_DQSRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL1DQSCTL_DQSRES_MASK)
35829#define DDRPHY_DX8SL1DQSCTL_DQSNRES_MASK (0xF0U)
35830#define DDRPHY_DX8SL1DQSCTL_DQSNRES_SHIFT (4U)
35831/*! DQSNRES - DQS_N Resistor
35832 */
35833#define DDRPHY_DX8SL1DQSCTL_DQSNRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL1DQSCTL_DQSNRES_MASK)
35834#define DDRPHY_DX8SL1DQSCTL_DXSR_MASK (0x300U)
35835#define DDRPHY_DX8SL1DQSCTL_DXSR_SHIFT (8U)
35836/*! DXSR - Data Slew Rate
35837 */
35838#define DDRPHY_DX8SL1DQSCTL_DXSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL1DQSCTL_DXSR_MASK)
35839#define DDRPHY_DX8SL1DQSCTL_RESERVED_12_10_MASK (0x1C00U)
35840#define DDRPHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT (10U)
35841/*! RESERVED_12_10 - Reserved. Return zeroes on reads.
35842 */
35843#define DDRPHY_DX8SL1DQSCTL_RESERVED_12_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL1DQSCTL_RESERVED_12_10_MASK)
35844#define DDRPHY_DX8SL1DQSCTL_UDQIOM_MASK (0x2000U)
35845#define DDRPHY_DX8SL1DQSCTL_UDQIOM_SHIFT (13U)
35846/*! UDQIOM - Unused DQ I/O Mode
35847 */
35848#define DDRPHY_DX8SL1DQSCTL_UDQIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL1DQSCTL_UDQIOM_MASK)
35849#define DDRPHY_DX8SL1DQSCTL_QSCNTEN_MASK (0x4000U)
35850#define DDRPHY_DX8SL1DQSCTL_QSCNTEN_SHIFT (14U)
35851/*! QSCNTEN - QS Counter Enable
35852 */
35853#define DDRPHY_DX8SL1DQSCTL_QSCNTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL1DQSCTL_QSCNTEN_MASK)
35854#define DDRPHY_DX8SL1DQSCTL_RESERVED_16_15_MASK (0x18000U)
35855#define DDRPHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT (15U)
35856/*! RESERVED_16_15 - Reserved. Return zeroes on reads.
35857 */
35858#define DDRPHY_DX8SL1DQSCTL_RESERVED_16_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL1DQSCTL_RESERVED_16_15_MASK)
35859#define DDRPHY_DX8SL1DQSCTL_LPIOPD_MASK (0x20000U)
35860#define DDRPHY_DX8SL1DQSCTL_LPIOPD_SHIFT (17U)
35861/*! LPIOPD - Low Power I/O Power Down
35862 */
35863#define DDRPHY_DX8SL1DQSCTL_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL1DQSCTL_LPIOPD_MASK)
35864#define DDRPHY_DX8SL1DQSCTL_LPPLLPD_MASK (0x40000U)
35865#define DDRPHY_DX8SL1DQSCTL_LPPLLPD_SHIFT (18U)
35866/*! LPPLLPD - Low Power PLL Power Down
35867 */
35868#define DDRPHY_DX8SL1DQSCTL_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL1DQSCTL_LPPLLPD_MASK)
35869#define DDRPHY_DX8SL1DQSCTL_DQSGX_MASK (0x180000U)
35870#define DDRPHY_DX8SL1DQSCTL_DQSGX_SHIFT (19U)
35871/*! DQSGX - DQS Gate Extension
35872 */
35873#define DDRPHY_DX8SL1DQSCTL_DQSGX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL1DQSCTL_DQSGX_MASK)
35874#define DDRPHY_DX8SL1DQSCTL_WRRMODE_MASK (0x200000U)
35875#define DDRPHY_DX8SL1DQSCTL_WRRMODE_SHIFT (21U)
35876/*! WRRMODE - Write Path Rise-to-Rise Mode
35877 */
35878#define DDRPHY_DX8SL1DQSCTL_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL1DQSCTL_WRRMODE_MASK)
35879#define DDRPHY_DX8SL1DQSCTL_RESERVED_23_22_MASK (0xC00000U)
35880#define DDRPHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT (22U)
35881/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
35882 */
35883#define DDRPHY_DX8SL1DQSCTL_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL1DQSCTL_RESERVED_23_22_MASK)
35884#define DDRPHY_DX8SL1DQSCTL_RRRMODE_MASK (0x1000000U)
35885#define DDRPHY_DX8SL1DQSCTL_RRRMODE_SHIFT (24U)
35886/*! RRRMODE - Read Path Rise-to-Rise Mode
35887 */
35888#define DDRPHY_DX8SL1DQSCTL_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL1DQSCTL_RRRMODE_MASK)
35889#define DDRPHY_DX8SL1DQSCTL_RESERVED_31_25_MASK (0xFE000000U)
35890#define DDRPHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT (25U)
35891/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
35892 */
35893#define DDRPHY_DX8SL1DQSCTL_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL1DQSCTL_RESERVED_31_25_MASK)
35894/*! @} */
35895
35896/*! @name DX8SL1TRNCTL - DATX8 0-1 Training Control Register */
35897/*! @{ */
35898#define DDRPHY_DX8SL1TRNCTL_RESERVED_31_0_MASK (0xFFFFFFFFU)
35899#define DDRPHY_DX8SL1TRNCTL_RESERVED_31_0_SHIFT (0U)
35900/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
35901 */
35902#define DDRPHY_DX8SL1TRNCTL_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL1TRNCTL_RESERVED_31_0_MASK)
35903/*! @} */
35904
35905/*! @name DX8SL1DDLCTL - DATX8 0-1 DDL Control Register */
35906/*! @{ */
35907#define DDRPHY_DX8SL1DDLCTL_DDLBYPMODE_MASK (0x3U)
35908#define DDRPHY_DX8SL1DDLCTL_DDLBYPMODE_SHIFT (0U)
35909/*! DDLBYPMODE - Controls DDL Bypass Mode
35910 */
35911#define DDRPHY_DX8SL1DDLCTL_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL1DDLCTL_DDLBYPMODE_MASK)
35912#define DDRPHY_DX8SL1DDLCTL_DXDDLBYP_MASK (0x3FFFCU)
35913#define DDRPHY_DX8SL1DDLCTL_DXDDLBYP_SHIFT (2U)
35914/*! DXDDLBYP - DATX8 DDL Bypass
35915 */
35916#define DDRPHY_DX8SL1DDLCTL_DXDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL1DDLCTL_DXDDLBYP_MASK)
35917#define DDRPHY_DX8SL1DDLCTL_DXDDLLD_MASK (0x7C0000U)
35918#define DDRPHY_DX8SL1DDLCTL_DXDDLLD_SHIFT (18U)
35919/*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load
35920 */
35921#define DDRPHY_DX8SL1DDLCTL_DXDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL1DDLCTL_DXDDLLD_MASK)
35922#define DDRPHY_DX8SL1DDLCTL_RESERVED_24_23_MASK (0x1800000U)
35923#define DDRPHY_DX8SL1DDLCTL_RESERVED_24_23_SHIFT (23U)
35924/*! RESERVED_24_23 - Reserved. Return zeroes on reads.
35925 */
35926#define DDRPHY_DX8SL1DDLCTL_RESERVED_24_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL1DDLCTL_RESERVED_24_23_MASK)
35927#define DDRPHY_DX8SL1DDLCTL_DXDDLLDT_MASK (0x2000000U)
35928#define DDRPHY_DX8SL1DDLCTL_DXDDLLDT_SHIFT (25U)
35929/*! DXDDLLDT - DX DDL Load Type
35930 */
35931#define DDRPHY_DX8SL1DDLCTL_DXDDLLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL1DDLCTL_DXDDLLDT_MASK)
35932#define DDRPHY_DX8SL1DDLCTL_DLYLDTM_MASK (0x4000000U)
35933#define DDRPHY_DX8SL1DDLCTL_DLYLDTM_SHIFT (26U)
35934/*! DLYLDTM - Delay Load Timing
35935 */
35936#define DDRPHY_DX8SL1DDLCTL_DLYLDTM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL1DDLCTL_DLYLDTM_MASK)
35937#define DDRPHY_DX8SL1DDLCTL_RESERVED_31_27_MASK (0xF8000000U)
35938#define DDRPHY_DX8SL1DDLCTL_RESERVED_31_27_SHIFT (27U)
35939/*! RESERVED_31_27 - Reserved. Return zeroes on reads.
35940 */
35941#define DDRPHY_DX8SL1DDLCTL_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL1DDLCTL_RESERVED_31_27_MASK)
35942/*! @} */
35943
35944/*! @name DX8SL1DXCTL1 - DATX8 0-1 DX Control Register 1 */
35945/*! @{ */
35946#define DDRPHY_DX8SL1DXCTL1_RESERVED_15_0_MASK (0xFFFFU)
35947#define DDRPHY_DX8SL1DXCTL1_RESERVED_15_0_SHIFT (0U)
35948/*! RESERVED_15_0 - Reserved. Return zeroes on reads.
35949 */
35950#define DDRPHY_DX8SL1DXCTL1_RESERVED_15_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL1DXCTL1_RESERVED_15_0_MASK)
35951#define DDRPHY_DX8SL1DXCTL1_DXTMODE_MASK (0x10000U)
35952#define DDRPHY_DX8SL1DXCTL1_DXTMODE_SHIFT (16U)
35953/*! DXTMODE - DATX8 Test Mode
35954 */
35955#define DDRPHY_DX8SL1DXCTL1_DXTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXTMODE_MASK)
35956#define DDRPHY_DX8SL1DXCTL1_DXGDBYP_MASK (0x20000U)
35957#define DDRPHY_DX8SL1DXCTL1_DXGDBYP_SHIFT (17U)
35958/*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode
35959 */
35960#define DDRPHY_DX8SL1DXCTL1_DXGDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXGDBYP_MASK)
35961#define DDRPHY_DX8SL1DXCTL1_DXQSDBYP_MASK (0x40000U)
35962#define DDRPHY_DX8SL1DXCTL1_DXQSDBYP_SHIFT (18U)
35963/*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode
35964 */
35965#define DDRPHY_DX8SL1DXCTL1_DXQSDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXQSDBYP_MASK)
35966#define DDRPHY_DX8SL1DXCTL1_DXGSMD_MASK (0x80000U)
35967#define DDRPHY_DX8SL1DXCTL1_DXGSMD_SHIFT (19U)
35968/*! DXGSMD - Read DQS Gating Status Mode
35969 */
35970#define DDRPHY_DX8SL1DXCTL1_DXGSMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXGSMD_MASK)
35971#define DDRPHY_DX8SL1DXCTL1_DXDTOSEL_MASK (0x300000U)
35972#define DDRPHY_DX8SL1DXCTL1_DXDTOSEL_SHIFT (20U)
35973/*! DXDTOSEL - DATX8 Digital Test Output Select
35974 */
35975#define DDRPHY_DX8SL1DXCTL1_DXDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXDTOSEL_MASK)
35976#define DDRPHY_DX8SL1DXCTL1_RESERVED_22_MASK (0x400000U)
35977#define DDRPHY_DX8SL1DXCTL1_RESERVED_22_SHIFT (22U)
35978/*! RESERVED_22 - Reserved. Return zeroes on reads.
35979 */
35980#define DDRPHY_DX8SL1DXCTL1_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL1DXCTL1_RESERVED_22_MASK)
35981#define DDRPHY_DX8SL1DXCTL1_DXRCLKMD_MASK (0x800000U)
35982#define DDRPHY_DX8SL1DXCTL1_DXRCLKMD_SHIFT (23U)
35983/*! DXRCLKMD - DATX8 Read Clock Mode
35984 */
35985#define DDRPHY_DX8SL1DXCTL1_DXRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXRCLKMD_MASK)
35986#define DDRPHY_DX8SL1DXCTL1_DXCALCLK_MASK (0x1000000U)
35987#define DDRPHY_DX8SL1DXCTL1_DXCALCLK_SHIFT (24U)
35988/*! DXCALCLK - DATX Calibration Clock Select
35989 */
35990#define DDRPHY_DX8SL1DXCTL1_DXCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL1DXCTL1_DXCALCLK_MASK)
35991#define DDRPHY_DX8SL1DXCTL1_RESERVED_31_25_MASK (0xFE000000U)
35992#define DDRPHY_DX8SL1DXCTL1_RESERVED_31_25_SHIFT (25U)
35993/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
35994 */
35995#define DDRPHY_DX8SL1DXCTL1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL1DXCTL1_RESERVED_31_25_MASK)
35996/*! @} */
35997
35998/*! @name DX8SL1DXCTL2 - DATX8 0-1 DX Control Register 2 */
35999/*! @{ */
36000#define DDRPHY_DX8SL1DXCTL2_RESERVED_0_MASK (0x1U)
36001#define DDRPHY_DX8SL1DXCTL2_RESERVED_0_SHIFT (0U)
36002/*! RESERVED_0 - Reserved. Return zeroes on reads.
36003 */
36004#define DDRPHY_DX8SL1DXCTL2_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL1DXCTL2_RESERVED_0_MASK)
36005#define DDRPHY_DX8SL1DXCTL2_DQSGLB_MASK (0x6U)
36006#define DDRPHY_DX8SL1DXCTL2_DQSGLB_SHIFT (1U)
36007/*! DQSGLB - Read DQS Gate I/O Loopback
36008 */
36009#define DDRPHY_DX8SL1DXCTL2_DQSGLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL1DXCTL2_DQSGLB_MASK)
36010#define DDRPHY_DX8SL1DXCTL2_DISRST_MASK (0x8U)
36011#define DDRPHY_DX8SL1DXCTL2_DISRST_SHIFT (3U)
36012/*! DISRST - Disables the Read FIFO Reset
36013 */
36014#define DDRPHY_DX8SL1DXCTL2_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL1DXCTL2_DISRST_MASK)
36015#define DDRPHY_DX8SL1DXCTL2_RDMODE_MASK (0x30U)
36016#define DDRPHY_DX8SL1DXCTL2_RDMODE_SHIFT (4U)
36017/*! RDMODE - DATX8 Receive FIFO Read Mode
36018 */
36019#define DDRPHY_DX8SL1DXCTL2_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL1DXCTL2_RDMODE_MASK)
36020#define DDRPHY_DX8SL1DXCTL2_PRFBYP_MASK (0x40U)
36021#define DDRPHY_DX8SL1DXCTL2_PRFBYP_SHIFT (6U)
36022/*! PRFBYP - PUB Read FIFO Bypass
36023 */
36024#define DDRPHY_DX8SL1DXCTL2_PRFBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL1DXCTL2_PRFBYP_MASK)
36025#define DDRPHY_DX8SL1DXCTL2_WDBI_MASK (0x80U)
36026#define DDRPHY_DX8SL1DXCTL2_WDBI_SHIFT (7U)
36027/*! WDBI - Write Data Bus Inversion Enable
36028 */
36029#define DDRPHY_DX8SL1DXCTL2_WDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL1DXCTL2_WDBI_MASK)
36030#define DDRPHY_DX8SL1DXCTL2_RDBI_MASK (0x100U)
36031#define DDRPHY_DX8SL1DXCTL2_RDBI_SHIFT (8U)
36032/*! RDBI - Read Data Bus Inversion Enable
36033 */
36034#define DDRPHY_DX8SL1DXCTL2_RDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL1DXCTL2_RDBI_MASK)
36035#define DDRPHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK (0x1E00U)
36036#define DDRPHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT (9U)
36037/*! LPWAKEUP_THRSH - Low Power Wakeup Threshold
36038 */
36039#define DDRPHY_DX8SL1DXCTL2_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK)
36040#define DDRPHY_DX8SL1DXCTL2_RESERVED_14_13_MASK (0x6000U)
36041#define DDRPHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT (13U)
36042/*! RESERVED_14_13 - Reserved. Return zeroes on reads.
36043 */
36044#define DDRPHY_DX8SL1DXCTL2_RESERVED_14_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL1DXCTL2_RESERVED_14_13_MASK)
36045#define DDRPHY_DX8SL1DXCTL2_IOLB_MASK (0x8000U)
36046#define DDRPHY_DX8SL1DXCTL2_IOLB_SHIFT (15U)
36047/*! IOLB - I/O Loopback Select
36048 */
36049#define DDRPHY_DX8SL1DXCTL2_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL1DXCTL2_IOLB_MASK)
36050#define DDRPHY_DX8SL1DXCTL2_IOAG_MASK (0x10000U)
36051#define DDRPHY_DX8SL1DXCTL2_IOAG_SHIFT (16U)
36052/*! IOAG - I/O Assisted Gate Select
36053 */
36054#define DDRPHY_DX8SL1DXCTL2_IOAG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL1DXCTL2_IOAG_MASK)
36055#define DDRPHY_DX8SL1DXCTL2_RESERVED_17_MASK (0x20000U)
36056#define DDRPHY_DX8SL1DXCTL2_RESERVED_17_SHIFT (17U)
36057/*! RESERVED_17 - Reserved. Return zeroes on reads.
36058 */
36059#define DDRPHY_DX8SL1DXCTL2_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL1DXCTL2_RESERVED_17_MASK)
36060#define DDRPHY_DX8SL1DXCTL2_PREOEX_MASK (0xC0000U)
36061#define DDRPHY_DX8SL1DXCTL2_PREOEX_SHIFT (18U)
36062/*! PREOEX - OE Extension during Pre-amble
36063 */
36064#define DDRPHY_DX8SL1DXCTL2_PREOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL1DXCTL2_PREOEX_MASK)
36065#define DDRPHY_DX8SL1DXCTL2_POSOEX_MASK (0x700000U)
36066#define DDRPHY_DX8SL1DXCTL2_POSOEX_SHIFT (20U)
36067/*! POSOEX - OX Extension during Post-amble
36068 */
36069#define DDRPHY_DX8SL1DXCTL2_POSOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL1DXCTL2_POSOEX_MASK)
36070#define DDRPHY_DX8SL1DXCTL2_CRDEN_MASK (0x800000U)
36071#define DDRPHY_DX8SL1DXCTL2_CRDEN_SHIFT (23U)
36072/*! CRDEN - Configurable Read Data Enable
36073 */
36074#define DDRPHY_DX8SL1DXCTL2_CRDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL1DXCTL2_CRDEN_MASK)
36075#define DDRPHY_DX8SL1DXCTL2_RESERVED_31_24_MASK (0xFF000000U)
36076#define DDRPHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT (24U)
36077/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
36078 */
36079#define DDRPHY_DX8SL1DXCTL2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL1DXCTL2_RESERVED_31_24_MASK)
36080/*! @} */
36081
36082/*! @name DX8SL1IOCR - DATX8 0-1 I/O Configuration Register */
36083/*! @{ */
36084#define DDRPHY_DX8SL1IOCR_DXRXM_MASK (0x7FFU)
36085#define DDRPHY_DX8SL1IOCR_DXRXM_SHIFT (0U)
36086/*! DXRXM - DX IO Receiver Mode
36087 */
36088#define DDRPHY_DX8SL1IOCR_DXRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL1IOCR_DXRXM_MASK)
36089#define DDRPHY_DX8SL1IOCR_DXTXM_MASK (0x3FF800U)
36090#define DDRPHY_DX8SL1IOCR_DXTXM_SHIFT (11U)
36091/*! DXTXM - DX IO Transmitter Mode
36092 */
36093#define DDRPHY_DX8SL1IOCR_DXTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL1IOCR_DXTXM_MASK)
36094#define DDRPHY_DX8SL1IOCR_DXIOM_MASK (0x1C00000U)
36095#define DDRPHY_DX8SL1IOCR_DXIOM_SHIFT (22U)
36096/*! DXIOM - DX IO Mode
36097 */
36098#define DDRPHY_DX8SL1IOCR_DXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL1IOCR_DXIOM_MASK)
36099#define DDRPHY_DX8SL1IOCR_DXVREFIOM_MASK (0xE000000U)
36100#define DDRPHY_DX8SL1IOCR_DXVREFIOM_SHIFT (25U)
36101/*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
36102 */
36103#define DDRPHY_DX8SL1IOCR_DXVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL1IOCR_DXVREFIOM_MASK)
36104#define DDRPHY_DX8SL1IOCR_DXDACRANGE_MASK (0x70000000U)
36105#define DDRPHY_DX8SL1IOCR_DXDACRANGE_SHIFT (28U)
36106/*! DXDACRANGE - PVREF_DAC REFSEL range select
36107 */
36108#define DDRPHY_DX8SL1IOCR_DXDACRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL1IOCR_DXDACRANGE_MASK)
36109#define DDRPHY_DX8SL1IOCR_RESERVED_31_MASK (0x80000000U)
36110#define DDRPHY_DX8SL1IOCR_RESERVED_31_SHIFT (31U)
36111/*! RESERVED_31 - Reserved. Return zeroes on reads.
36112 */
36113#define DDRPHY_DX8SL1IOCR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL1IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL1IOCR_RESERVED_31_MASK)
36114/*! @} */
36115
36116/*! @name DX4SL1IOCR - DATX4 Slice 0-1 I/O Configuration Register */
36117/*! @{ */
36118#define DDRPHY_DX4SL1IOCR_RESERVED_31_0_MASK (0xFFFFFFFFU)
36119#define DDRPHY_DX4SL1IOCR_RESERVED_31_0_SHIFT (0U)
36120/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
36121 */
36122#define DDRPHY_DX4SL1IOCR_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL1IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL1IOCR_RESERVED_31_0_MASK)
36123/*! @} */
36124
36125/*! @name DX8SL2OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */
36126/*! @{ */
36127#define DDRPHY_DX8SL2OSC_OSCEN_MASK (0x1U)
36128#define DDRPHY_DX8SL2OSC_OSCEN_SHIFT (0U)
36129/*! OSCEN - Oscillator Enable
36130 */
36131#define DDRPHY_DX8SL2OSC_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL2OSC_OSCEN_MASK)
36132#define DDRPHY_DX8SL2OSC_OSCDIV_MASK (0x1EU)
36133#define DDRPHY_DX8SL2OSC_OSCDIV_SHIFT (1U)
36134/*! OSCDIV - Oscillator Mode Division
36135 */
36136#define DDRPHY_DX8SL2OSC_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL2OSC_OSCDIV_MASK)
36137#define DDRPHY_DX8SL2OSC_OSCWDL_MASK (0x60U)
36138#define DDRPHY_DX8SL2OSC_OSCWDL_SHIFT (5U)
36139/*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select
36140 */
36141#define DDRPHY_DX8SL2OSC_OSCWDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL2OSC_OSCWDL_MASK)
36142#define DDRPHY_DX8SL2OSC_RESERVED_8_7_MASK (0x180U)
36143#define DDRPHY_DX8SL2OSC_RESERVED_8_7_SHIFT (7U)
36144/*! RESERVED_8_7 - Reserved. Caution, do not write to this register field.
36145 */
36146#define DDRPHY_DX8SL2OSC_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL2OSC_RESERVED_8_7_MASK)
36147#define DDRPHY_DX8SL2OSC_OSCWDDL_MASK (0x600U)
36148#define DDRPHY_DX8SL2OSC_OSCWDDL_SHIFT (9U)
36149/*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select
36150 */
36151#define DDRPHY_DX8SL2OSC_OSCWDDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL2OSC_OSCWDDL_MASK)
36152#define DDRPHY_DX8SL2OSC_RESERVED_12_11_MASK (0x1800U)
36153#define DDRPHY_DX8SL2OSC_RESERVED_12_11_SHIFT (11U)
36154/*! RESERVED_12_11 - Reserved. Caution, do not write to this register field.
36155 */
36156#define DDRPHY_DX8SL2OSC_RESERVED_12_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL2OSC_RESERVED_12_11_MASK)
36157#define DDRPHY_DX8SL2OSC_DLTMODE_MASK (0x2000U)
36158#define DDRPHY_DX8SL2OSC_DLTMODE_SHIFT (13U)
36159/*! DLTMODE - Delay Line Test Mode
36160 */
36161#define DDRPHY_DX8SL2OSC_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL2OSC_DLTMODE_MASK)
36162#define DDRPHY_DX8SL2OSC_DLTST_MASK (0x4000U)
36163#define DDRPHY_DX8SL2OSC_DLTST_SHIFT (14U)
36164/*! DLTST - Delay Line Test Start
36165 */
36166#define DDRPHY_DX8SL2OSC_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_DLTST_SHIFT)) & DDRPHY_DX8SL2OSC_DLTST_MASK)
36167#define DDRPHY_DX8SL2OSC_PHYFRST_MASK (0x8000U)
36168#define DDRPHY_DX8SL2OSC_PHYFRST_SHIFT (15U)
36169/*! PHYFRST - PHY FIFO Reset
36170 */
36171#define DDRPHY_DX8SL2OSC_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL2OSC_PHYFRST_MASK)
36172#define DDRPHY_DX8SL2OSC_PHYHRST_MASK (0x10000U)
36173#define DDRPHY_DX8SL2OSC_PHYHRST_SHIFT (16U)
36174/*! PHYHRST - PHY High-Speed Reset
36175 */
36176#define DDRPHY_DX8SL2OSC_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL2OSC_PHYHRST_MASK)
36177#define DDRPHY_DX8SL2OSC_LBDQSS_MASK (0x20000U)
36178#define DDRPHY_DX8SL2OSC_LBDQSS_SHIFT (17U)
36179/*! LBDQSS - Loopback DQS Shift
36180 */
36181#define DDRPHY_DX8SL2OSC_LBDQSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL2OSC_LBDQSS_MASK)
36182#define DDRPHY_DX8SL2OSC_LBGDQS_MASK (0xC0000U)
36183#define DDRPHY_DX8SL2OSC_LBGDQS_SHIFT (18U)
36184/*! LBGDQS - Loopback DQS Gating
36185 */
36186#define DDRPHY_DX8SL2OSC_LBGDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL2OSC_LBGDQS_MASK)
36187#define DDRPHY_DX8SL2OSC_LBGSDQS_MASK (0x100000U)
36188#define DDRPHY_DX8SL2OSC_LBGSDQS_SHIFT (20U)
36189/*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
36190 */
36191#define DDRPHY_DX8SL2OSC_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL2OSC_LBGSDQS_MASK)
36192#define DDRPHY_DX8SL2OSC_LBMODE_MASK (0x200000U)
36193#define DDRPHY_DX8SL2OSC_LBMODE_SHIFT (21U)
36194/*! LBMODE - Loopback Mode
36195 */
36196#define DDRPHY_DX8SL2OSC_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL2OSC_LBMODE_MASK)
36197#define DDRPHY_DX8SL2OSC_CLKLEVEL_MASK (0xC00000U)
36198#define DDRPHY_DX8SL2OSC_CLKLEVEL_SHIFT (22U)
36199/*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled.
36200 */
36201#define DDRPHY_DX8SL2OSC_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL2OSC_CLKLEVEL_MASK)
36202#define DDRPHY_DX8SL2OSC_GATEDXCTLCLK_MASK (0x3000000U)
36203#define DDRPHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT (24U)
36204/*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk
36205 */
36206#define DDRPHY_DX8SL2OSC_GATEDXCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL2OSC_GATEDXCTLCLK_MASK)
36207#define DDRPHY_DX8SL2OSC_GATEDXDDRCLK_MASK (0xC000000U)
36208#define DDRPHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT (26U)
36209/*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk
36210 */
36211#define DDRPHY_DX8SL2OSC_GATEDXDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL2OSC_GATEDXDDRCLK_MASK)
36212#define DDRPHY_DX8SL2OSC_GATEDXRDCLK_MASK (0x30000000U)
36213#define DDRPHY_DX8SL2OSC_GATEDXRDCLK_SHIFT (28U)
36214/*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk
36215 */
36216#define DDRPHY_DX8SL2OSC_GATEDXRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL2OSC_GATEDXRDCLK_MASK)
36217#define DDRPHY_DX8SL2OSC_RESERVED_31_30_MASK (0xC0000000U)
36218#define DDRPHY_DX8SL2OSC_RESERVED_31_30_SHIFT (30U)
36219/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
36220 */
36221#define DDRPHY_DX8SL2OSC_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL2OSC_RESERVED_31_30_MASK)
36222/*! @} */
36223
36224/*! @name DX8SL2PLLCR0 - DAXT8 0-1 PLL Control Register 0 */
36225/*! @{ */
36226#define DDRPHY_DX8SL2PLLCR0_DTC_MASK (0xFU)
36227#define DDRPHY_DX8SL2PLLCR0_DTC_SHIFT (0U)
36228/*! DTC - Digital Test Control
36229 */
36230#define DDRPHY_DX8SL2PLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL2PLLCR0_DTC_MASK)
36231#define DDRPHY_DX8SL2PLLCR0_ATC_MASK (0xF0U)
36232#define DDRPHY_DX8SL2PLLCR0_ATC_SHIFT (4U)
36233/*! ATC - Analog Test Control
36234 */
36235#define DDRPHY_DX8SL2PLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL2PLLCR0_ATC_MASK)
36236#define DDRPHY_DX8SL2PLLCR0_ATOEN_MASK (0x100U)
36237#define DDRPHY_DX8SL2PLLCR0_ATOEN_SHIFT (8U)
36238/*! ATOEN - Analog Test Enable (ATOEN)
36239 */
36240#define DDRPHY_DX8SL2PLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL2PLLCR0_ATOEN_MASK)
36241#define DDRPHY_DX8SL2PLLCR0_RESERVED_11_9_MASK (0xE00U)
36242#define DDRPHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT (9U)
36243/*! RESERVED_11_9 - Reserved. Return zeroes on reads.
36244 */
36245#define DDRPHY_DX8SL2PLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL2PLLCR0_RESERVED_11_9_MASK)
36246#define DDRPHY_DX8SL2PLLCR0_GSHIFT_MASK (0x1000U)
36247#define DDRPHY_DX8SL2PLLCR0_GSHIFT_SHIFT (12U)
36248/*! GSHIFT - Gear Shift
36249 */
36250#define DDRPHY_DX8SL2PLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL2PLLCR0_GSHIFT_MASK)
36251#define DDRPHY_DX8SL2PLLCR0_CPIC_MASK (0x1E000U)
36252#define DDRPHY_DX8SL2PLLCR0_CPIC_SHIFT (13U)
36253/*! CPIC - Charge Pump Integrating Current Control
36254 */
36255#define DDRPHY_DX8SL2PLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL2PLLCR0_CPIC_MASK)
36256#define DDRPHY_DX8SL2PLLCR0_CPPC_MASK (0x7E0000U)
36257#define DDRPHY_DX8SL2PLLCR0_CPPC_SHIFT (17U)
36258/*! CPPC - Charge Pump Proportional Current Control
36259 */
36260#define DDRPHY_DX8SL2PLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL2PLLCR0_CPPC_MASK)
36261#define DDRPHY_DX8SL2PLLCR0_RLOCKM_MASK (0x800000U)
36262#define DDRPHY_DX8SL2PLLCR0_RLOCKM_SHIFT (23U)
36263/*! RLOCKM - Relock Mode
36264 */
36265#define DDRPHY_DX8SL2PLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL2PLLCR0_RLOCKM_MASK)
36266#define DDRPHY_DX8SL2PLLCR0_FRQSEL_MASK (0xF000000U)
36267#define DDRPHY_DX8SL2PLLCR0_FRQSEL_SHIFT (24U)
36268/*! FRQSEL - PLL Frequency Select
36269 */
36270#define DDRPHY_DX8SL2PLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL2PLLCR0_FRQSEL_MASK)
36271#define DDRPHY_DX8SL2PLLCR0_RSTOPM_MASK (0x10000000U)
36272#define DDRPHY_DX8SL2PLLCR0_RSTOPM_SHIFT (28U)
36273/*! RSTOPM - Reference Stop Mode
36274 */
36275#define DDRPHY_DX8SL2PLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL2PLLCR0_RSTOPM_MASK)
36276#define DDRPHY_DX8SL2PLLCR0_PLLPD_MASK (0x20000000U)
36277#define DDRPHY_DX8SL2PLLCR0_PLLPD_SHIFT (29U)
36278/*! PLLPD - PLL Power Down
36279 */
36280#define DDRPHY_DX8SL2PLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL2PLLCR0_PLLPD_MASK)
36281#define DDRPHY_DX8SL2PLLCR0_PLLRST_MASK (0x40000000U)
36282#define DDRPHY_DX8SL2PLLCR0_PLLRST_SHIFT (30U)
36283/*! PLLRST - PLL Reset
36284 */
36285#define DDRPHY_DX8SL2PLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL2PLLCR0_PLLRST_MASK)
36286#define DDRPHY_DX8SL2PLLCR0_PLLBYP_MASK (0x80000000U)
36287#define DDRPHY_DX8SL2PLLCR0_PLLBYP_SHIFT (31U)
36288/*! PLLBYP - PLL Bypass
36289 */
36290#define DDRPHY_DX8SL2PLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL2PLLCR0_PLLBYP_MASK)
36291/*! @} */
36292
36293/*! @name DX8SL2PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */
36294/*! @{ */
36295#define DDRPHY_DX8SL2PLLCR1_LOCKDS_MASK (0x1U)
36296#define DDRPHY_DX8SL2PLLCR1_LOCKDS_SHIFT (0U)
36297/*! LOCKDS - Lock Detector Select
36298 */
36299#define DDRPHY_DX8SL2PLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL2PLLCR1_LOCKDS_MASK)
36300#define DDRPHY_DX8SL2PLLCR1_LOCKCS_MASK (0x2U)
36301#define DDRPHY_DX8SL2PLLCR1_LOCKCS_SHIFT (1U)
36302/*! LOCKCS - Lock Detector Counter Select
36303 */
36304#define DDRPHY_DX8SL2PLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL2PLLCR1_LOCKCS_MASK)
36305#define DDRPHY_DX8SL2PLLCR1_LOCKPS_MASK (0x4U)
36306#define DDRPHY_DX8SL2PLLCR1_LOCKPS_SHIFT (2U)
36307/*! LOCKPS - Lock Detector Phase Select
36308 */
36309#define DDRPHY_DX8SL2PLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL2PLLCR1_LOCKPS_MASK)
36310#define DDRPHY_DX8SL2PLLCR1_BYPVDD_MASK (0x8U)
36311#define DDRPHY_DX8SL2PLLCR1_BYPVDD_SHIFT (3U)
36312/*! BYPVDD - PLL VDD voltage level control
36313 */
36314#define DDRPHY_DX8SL2PLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL2PLLCR1_BYPVDD_MASK)
36315#define DDRPHY_DX8SL2PLLCR1_BYPVREGDIG_MASK (0x10U)
36316#define DDRPHY_DX8SL2PLLCR1_BYPVREGDIG_SHIFT (4U)
36317/*! BYPVREGDIG - Bypass PLL vreg_dig
36318 */
36319#define DDRPHY_DX8SL2PLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL2PLLCR1_BYPVREGDIG_MASK)
36320#define DDRPHY_DX8SL2PLLCR1_BYPVREGCP_MASK (0x20U)
36321#define DDRPHY_DX8SL2PLLCR1_BYPVREGCP_SHIFT (5U)
36322/*! BYPVREGCP - Bypass PLL vreg_cp
36323 */
36324#define DDRPHY_DX8SL2PLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL2PLLCR1_BYPVREGCP_MASK)
36325#define DDRPHY_DX8SL2PLLCR1_PLLPROG_MASK (0x3FFFC0U)
36326#define DDRPHY_DX8SL2PLLCR1_PLLPROG_SHIFT (6U)
36327/*! PLLPROG - Connects to the PLL PLL_PROG bus.
36328 */
36329#define DDRPHY_DX8SL2PLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL2PLLCR1_PLLPROG_MASK)
36330#define DDRPHY_DX8SL2PLLCR1_RESERVED_31_22_MASK (0xFFC00000U)
36331#define DDRPHY_DX8SL2PLLCR1_RESERVED_31_22_SHIFT (22U)
36332/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
36333 */
36334#define DDRPHY_DX8SL2PLLCR1_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL2PLLCR1_RESERVED_31_22_MASK)
36335/*! @} */
36336
36337/*! @name DX8SL2PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */
36338/*! @{ */
36339#define DDRPHY_DX8SL2PLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU)
36340#define DDRPHY_DX8SL2PLLCR2_PLLCTRL_31_0_SHIFT (0U)
36341/*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
36342 */
36343#define DDRPHY_DX8SL2PLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL2PLLCR2_PLLCTRL_31_0_MASK)
36344/*! @} */
36345
36346/*! @name DX8SL2PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */
36347/*! @{ */
36348#define DDRPHY_DX8SL2PLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU)
36349#define DDRPHY_DX8SL2PLLCR3_PLLCTRL_63_32_SHIFT (0U)
36350/*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
36351 */
36352#define DDRPHY_DX8SL2PLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL2PLLCR3_PLLCTRL_63_32_MASK)
36353/*! @} */
36354
36355/*! @name DX8SL2PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */
36356/*! @{ */
36357#define DDRPHY_DX8SL2PLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU)
36358#define DDRPHY_DX8SL2PLLCR4_PLLCTRL_95_64_SHIFT (0U)
36359/*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
36360 */
36361#define DDRPHY_DX8SL2PLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL2PLLCR4_PLLCTRL_95_64_MASK)
36362/*! @} */
36363
36364/*! @name DX8SL2PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */
36365/*! @{ */
36366#define DDRPHY_DX8SL2PLLCR5_PLLCTRL_103_96_MASK (0xFFU)
36367#define DDRPHY_DX8SL2PLLCR5_PLLCTRL_103_96_SHIFT (0U)
36368/*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
36369 */
36370#define DDRPHY_DX8SL2PLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL2PLLCR5_PLLCTRL_103_96_MASK)
36371#define DDRPHY_DX8SL2PLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U)
36372#define DDRPHY_DX8SL2PLLCR5_RESERVED_31_8_SHIFT (8U)
36373/*! RESERVED_31_8 - Reserved. Return zeroes on reads.
36374 */
36375#define DDRPHY_DX8SL2PLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL2PLLCR5_RESERVED_31_8_MASK)
36376/*! @} */
36377
36378/*! @name DX8SL2DQSCTL - DATX8 0-1 DQS Control Register */
36379/*! @{ */
36380#define DDRPHY_DX8SL2DQSCTL_DQSRES_MASK (0xFU)
36381#define DDRPHY_DX8SL2DQSCTL_DQSRES_SHIFT (0U)
36382/*! DQSRES - DQS Resistor
36383 */
36384#define DDRPHY_DX8SL2DQSCTL_DQSRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL2DQSCTL_DQSRES_MASK)
36385#define DDRPHY_DX8SL2DQSCTL_DQSNRES_MASK (0xF0U)
36386#define DDRPHY_DX8SL2DQSCTL_DQSNRES_SHIFT (4U)
36387/*! DQSNRES - DQS_N Resistor
36388 */
36389#define DDRPHY_DX8SL2DQSCTL_DQSNRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL2DQSCTL_DQSNRES_MASK)
36390#define DDRPHY_DX8SL2DQSCTL_DXSR_MASK (0x300U)
36391#define DDRPHY_DX8SL2DQSCTL_DXSR_SHIFT (8U)
36392/*! DXSR - Data Slew Rate
36393 */
36394#define DDRPHY_DX8SL2DQSCTL_DXSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL2DQSCTL_DXSR_MASK)
36395#define DDRPHY_DX8SL2DQSCTL_RESERVED_12_10_MASK (0x1C00U)
36396#define DDRPHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT (10U)
36397/*! RESERVED_12_10 - Reserved. Return zeroes on reads.
36398 */
36399#define DDRPHY_DX8SL2DQSCTL_RESERVED_12_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL2DQSCTL_RESERVED_12_10_MASK)
36400#define DDRPHY_DX8SL2DQSCTL_UDQIOM_MASK (0x2000U)
36401#define DDRPHY_DX8SL2DQSCTL_UDQIOM_SHIFT (13U)
36402/*! UDQIOM - Unused DQ I/O Mode
36403 */
36404#define DDRPHY_DX8SL2DQSCTL_UDQIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL2DQSCTL_UDQIOM_MASK)
36405#define DDRPHY_DX8SL2DQSCTL_QSCNTEN_MASK (0x4000U)
36406#define DDRPHY_DX8SL2DQSCTL_QSCNTEN_SHIFT (14U)
36407/*! QSCNTEN - QS Counter Enable
36408 */
36409#define DDRPHY_DX8SL2DQSCTL_QSCNTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL2DQSCTL_QSCNTEN_MASK)
36410#define DDRPHY_DX8SL2DQSCTL_RESERVED_16_15_MASK (0x18000U)
36411#define DDRPHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT (15U)
36412/*! RESERVED_16_15 - Reserved. Return zeroes on reads.
36413 */
36414#define DDRPHY_DX8SL2DQSCTL_RESERVED_16_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL2DQSCTL_RESERVED_16_15_MASK)
36415#define DDRPHY_DX8SL2DQSCTL_LPIOPD_MASK (0x20000U)
36416#define DDRPHY_DX8SL2DQSCTL_LPIOPD_SHIFT (17U)
36417/*! LPIOPD - Low Power I/O Power Down
36418 */
36419#define DDRPHY_DX8SL2DQSCTL_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL2DQSCTL_LPIOPD_MASK)
36420#define DDRPHY_DX8SL2DQSCTL_LPPLLPD_MASK (0x40000U)
36421#define DDRPHY_DX8SL2DQSCTL_LPPLLPD_SHIFT (18U)
36422/*! LPPLLPD - Low Power PLL Power Down
36423 */
36424#define DDRPHY_DX8SL2DQSCTL_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL2DQSCTL_LPPLLPD_MASK)
36425#define DDRPHY_DX8SL2DQSCTL_DQSGX_MASK (0x180000U)
36426#define DDRPHY_DX8SL2DQSCTL_DQSGX_SHIFT (19U)
36427/*! DQSGX - DQS Gate Extension
36428 */
36429#define DDRPHY_DX8SL2DQSCTL_DQSGX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL2DQSCTL_DQSGX_MASK)
36430#define DDRPHY_DX8SL2DQSCTL_WRRMODE_MASK (0x200000U)
36431#define DDRPHY_DX8SL2DQSCTL_WRRMODE_SHIFT (21U)
36432/*! WRRMODE - Write Path Rise-to-Rise Mode
36433 */
36434#define DDRPHY_DX8SL2DQSCTL_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL2DQSCTL_WRRMODE_MASK)
36435#define DDRPHY_DX8SL2DQSCTL_RESERVED_23_22_MASK (0xC00000U)
36436#define DDRPHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT (22U)
36437/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
36438 */
36439#define DDRPHY_DX8SL2DQSCTL_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL2DQSCTL_RESERVED_23_22_MASK)
36440#define DDRPHY_DX8SL2DQSCTL_RRRMODE_MASK (0x1000000U)
36441#define DDRPHY_DX8SL2DQSCTL_RRRMODE_SHIFT (24U)
36442/*! RRRMODE - Read Path Rise-to-Rise Mode
36443 */
36444#define DDRPHY_DX8SL2DQSCTL_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL2DQSCTL_RRRMODE_MASK)
36445#define DDRPHY_DX8SL2DQSCTL_RESERVED_31_25_MASK (0xFE000000U)
36446#define DDRPHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT (25U)
36447/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
36448 */
36449#define DDRPHY_DX8SL2DQSCTL_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL2DQSCTL_RESERVED_31_25_MASK)
36450/*! @} */
36451
36452/*! @name DX8SL2TRNCTL - DATX8 0-1 Training Control Register */
36453/*! @{ */
36454#define DDRPHY_DX8SL2TRNCTL_RESERVED_31_0_MASK (0xFFFFFFFFU)
36455#define DDRPHY_DX8SL2TRNCTL_RESERVED_31_0_SHIFT (0U)
36456/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
36457 */
36458#define DDRPHY_DX8SL2TRNCTL_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL2TRNCTL_RESERVED_31_0_MASK)
36459/*! @} */
36460
36461/*! @name DX8SL2DDLCTL - DATX8 0-1 DDL Control Register */
36462/*! @{ */
36463#define DDRPHY_DX8SL2DDLCTL_DDLBYPMODE_MASK (0x3U)
36464#define DDRPHY_DX8SL2DDLCTL_DDLBYPMODE_SHIFT (0U)
36465/*! DDLBYPMODE - Controls DDL Bypass Mode
36466 */
36467#define DDRPHY_DX8SL2DDLCTL_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL2DDLCTL_DDLBYPMODE_MASK)
36468#define DDRPHY_DX8SL2DDLCTL_DXDDLBYP_MASK (0x3FFFCU)
36469#define DDRPHY_DX8SL2DDLCTL_DXDDLBYP_SHIFT (2U)
36470/*! DXDDLBYP - DATX8 DDL Bypass
36471 */
36472#define DDRPHY_DX8SL2DDLCTL_DXDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL2DDLCTL_DXDDLBYP_MASK)
36473#define DDRPHY_DX8SL2DDLCTL_DXDDLLD_MASK (0x7C0000U)
36474#define DDRPHY_DX8SL2DDLCTL_DXDDLLD_SHIFT (18U)
36475/*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load
36476 */
36477#define DDRPHY_DX8SL2DDLCTL_DXDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL2DDLCTL_DXDDLLD_MASK)
36478#define DDRPHY_DX8SL2DDLCTL_RESERVED_24_23_MASK (0x1800000U)
36479#define DDRPHY_DX8SL2DDLCTL_RESERVED_24_23_SHIFT (23U)
36480/*! RESERVED_24_23 - Reserved. Return zeroes on reads.
36481 */
36482#define DDRPHY_DX8SL2DDLCTL_RESERVED_24_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL2DDLCTL_RESERVED_24_23_MASK)
36483#define DDRPHY_DX8SL2DDLCTL_DXDDLLDT_MASK (0x2000000U)
36484#define DDRPHY_DX8SL2DDLCTL_DXDDLLDT_SHIFT (25U)
36485/*! DXDDLLDT - DX DDL Load Type
36486 */
36487#define DDRPHY_DX8SL2DDLCTL_DXDDLLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL2DDLCTL_DXDDLLDT_MASK)
36488#define DDRPHY_DX8SL2DDLCTL_DLYLDTM_MASK (0x4000000U)
36489#define DDRPHY_DX8SL2DDLCTL_DLYLDTM_SHIFT (26U)
36490/*! DLYLDTM - Delay Load Timing
36491 */
36492#define DDRPHY_DX8SL2DDLCTL_DLYLDTM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL2DDLCTL_DLYLDTM_MASK)
36493#define DDRPHY_DX8SL2DDLCTL_RESERVED_31_27_MASK (0xF8000000U)
36494#define DDRPHY_DX8SL2DDLCTL_RESERVED_31_27_SHIFT (27U)
36495/*! RESERVED_31_27 - Reserved. Return zeroes on reads.
36496 */
36497#define DDRPHY_DX8SL2DDLCTL_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL2DDLCTL_RESERVED_31_27_MASK)
36498/*! @} */
36499
36500/*! @name DX8SL2DXCTL1 - DATX8 0-1 DX Control Register 1 */
36501/*! @{ */
36502#define DDRPHY_DX8SL2DXCTL1_RESERVED_15_0_MASK (0xFFFFU)
36503#define DDRPHY_DX8SL2DXCTL1_RESERVED_15_0_SHIFT (0U)
36504/*! RESERVED_15_0 - Reserved. Return zeroes on reads.
36505 */
36506#define DDRPHY_DX8SL2DXCTL1_RESERVED_15_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL2DXCTL1_RESERVED_15_0_MASK)
36507#define DDRPHY_DX8SL2DXCTL1_DXTMODE_MASK (0x10000U)
36508#define DDRPHY_DX8SL2DXCTL1_DXTMODE_SHIFT (16U)
36509/*! DXTMODE - DATX8 Test Mode
36510 */
36511#define DDRPHY_DX8SL2DXCTL1_DXTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXTMODE_MASK)
36512#define DDRPHY_DX8SL2DXCTL1_DXGDBYP_MASK (0x20000U)
36513#define DDRPHY_DX8SL2DXCTL1_DXGDBYP_SHIFT (17U)
36514/*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode
36515 */
36516#define DDRPHY_DX8SL2DXCTL1_DXGDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXGDBYP_MASK)
36517#define DDRPHY_DX8SL2DXCTL1_DXQSDBYP_MASK (0x40000U)
36518#define DDRPHY_DX8SL2DXCTL1_DXQSDBYP_SHIFT (18U)
36519/*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode
36520 */
36521#define DDRPHY_DX8SL2DXCTL1_DXQSDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXQSDBYP_MASK)
36522#define DDRPHY_DX8SL2DXCTL1_DXGSMD_MASK (0x80000U)
36523#define DDRPHY_DX8SL2DXCTL1_DXGSMD_SHIFT (19U)
36524/*! DXGSMD - Read DQS Gating Status Mode
36525 */
36526#define DDRPHY_DX8SL2DXCTL1_DXGSMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXGSMD_MASK)
36527#define DDRPHY_DX8SL2DXCTL1_DXDTOSEL_MASK (0x300000U)
36528#define DDRPHY_DX8SL2DXCTL1_DXDTOSEL_SHIFT (20U)
36529/*! DXDTOSEL - DATX8 Digital Test Output Select
36530 */
36531#define DDRPHY_DX8SL2DXCTL1_DXDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXDTOSEL_MASK)
36532#define DDRPHY_DX8SL2DXCTL1_RESERVED_22_MASK (0x400000U)
36533#define DDRPHY_DX8SL2DXCTL1_RESERVED_22_SHIFT (22U)
36534/*! RESERVED_22 - Reserved. Return zeroes on reads.
36535 */
36536#define DDRPHY_DX8SL2DXCTL1_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL2DXCTL1_RESERVED_22_MASK)
36537#define DDRPHY_DX8SL2DXCTL1_DXRCLKMD_MASK (0x800000U)
36538#define DDRPHY_DX8SL2DXCTL1_DXRCLKMD_SHIFT (23U)
36539/*! DXRCLKMD - DATX8 Read Clock Mode
36540 */
36541#define DDRPHY_DX8SL2DXCTL1_DXRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXRCLKMD_MASK)
36542#define DDRPHY_DX8SL2DXCTL1_DXCALCLK_MASK (0x1000000U)
36543#define DDRPHY_DX8SL2DXCTL1_DXCALCLK_SHIFT (24U)
36544/*! DXCALCLK - DATX Calibration Clock Select
36545 */
36546#define DDRPHY_DX8SL2DXCTL1_DXCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL2DXCTL1_DXCALCLK_MASK)
36547#define DDRPHY_DX8SL2DXCTL1_RESERVED_31_25_MASK (0xFE000000U)
36548#define DDRPHY_DX8SL2DXCTL1_RESERVED_31_25_SHIFT (25U)
36549/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
36550 */
36551#define DDRPHY_DX8SL2DXCTL1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL2DXCTL1_RESERVED_31_25_MASK)
36552/*! @} */
36553
36554/*! @name DX8SL2DXCTL2 - DATX8 0-1 DX Control Register 2 */
36555/*! @{ */
36556#define DDRPHY_DX8SL2DXCTL2_RESERVED_0_MASK (0x1U)
36557#define DDRPHY_DX8SL2DXCTL2_RESERVED_0_SHIFT (0U)
36558/*! RESERVED_0 - Reserved. Return zeroes on reads.
36559 */
36560#define DDRPHY_DX8SL2DXCTL2_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL2DXCTL2_RESERVED_0_MASK)
36561#define DDRPHY_DX8SL2DXCTL2_DQSGLB_MASK (0x6U)
36562#define DDRPHY_DX8SL2DXCTL2_DQSGLB_SHIFT (1U)
36563/*! DQSGLB - Read DQS Gate I/O Loopback
36564 */
36565#define DDRPHY_DX8SL2DXCTL2_DQSGLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL2DXCTL2_DQSGLB_MASK)
36566#define DDRPHY_DX8SL2DXCTL2_DISRST_MASK (0x8U)
36567#define DDRPHY_DX8SL2DXCTL2_DISRST_SHIFT (3U)
36568/*! DISRST - Disables the Read FIFO Reset
36569 */
36570#define DDRPHY_DX8SL2DXCTL2_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL2DXCTL2_DISRST_MASK)
36571#define DDRPHY_DX8SL2DXCTL2_RDMODE_MASK (0x30U)
36572#define DDRPHY_DX8SL2DXCTL2_RDMODE_SHIFT (4U)
36573/*! RDMODE - DATX8 Receive FIFO Read Mode
36574 */
36575#define DDRPHY_DX8SL2DXCTL2_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL2DXCTL2_RDMODE_MASK)
36576#define DDRPHY_DX8SL2DXCTL2_PRFBYP_MASK (0x40U)
36577#define DDRPHY_DX8SL2DXCTL2_PRFBYP_SHIFT (6U)
36578/*! PRFBYP - PUB Read FIFO Bypass
36579 */
36580#define DDRPHY_DX8SL2DXCTL2_PRFBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL2DXCTL2_PRFBYP_MASK)
36581#define DDRPHY_DX8SL2DXCTL2_WDBI_MASK (0x80U)
36582#define DDRPHY_DX8SL2DXCTL2_WDBI_SHIFT (7U)
36583/*! WDBI - Write Data Bus Inversion Enable
36584 */
36585#define DDRPHY_DX8SL2DXCTL2_WDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL2DXCTL2_WDBI_MASK)
36586#define DDRPHY_DX8SL2DXCTL2_RDBI_MASK (0x100U)
36587#define DDRPHY_DX8SL2DXCTL2_RDBI_SHIFT (8U)
36588/*! RDBI - Read Data Bus Inversion Enable
36589 */
36590#define DDRPHY_DX8SL2DXCTL2_RDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL2DXCTL2_RDBI_MASK)
36591#define DDRPHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK (0x1E00U)
36592#define DDRPHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT (9U)
36593/*! LPWAKEUP_THRSH - Low Power Wakeup Threshold
36594 */
36595#define DDRPHY_DX8SL2DXCTL2_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK)
36596#define DDRPHY_DX8SL2DXCTL2_RESERVED_14_13_MASK (0x6000U)
36597#define DDRPHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT (13U)
36598/*! RESERVED_14_13 - Reserved. Return zeroes on reads.
36599 */
36600#define DDRPHY_DX8SL2DXCTL2_RESERVED_14_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL2DXCTL2_RESERVED_14_13_MASK)
36601#define DDRPHY_DX8SL2DXCTL2_IOLB_MASK (0x8000U)
36602#define DDRPHY_DX8SL2DXCTL2_IOLB_SHIFT (15U)
36603/*! IOLB - I/O Loopback Select
36604 */
36605#define DDRPHY_DX8SL2DXCTL2_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL2DXCTL2_IOLB_MASK)
36606#define DDRPHY_DX8SL2DXCTL2_IOAG_MASK (0x10000U)
36607#define DDRPHY_DX8SL2DXCTL2_IOAG_SHIFT (16U)
36608/*! IOAG - I/O Assisted Gate Select
36609 */
36610#define DDRPHY_DX8SL2DXCTL2_IOAG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL2DXCTL2_IOAG_MASK)
36611#define DDRPHY_DX8SL2DXCTL2_RESERVED_17_MASK (0x20000U)
36612#define DDRPHY_DX8SL2DXCTL2_RESERVED_17_SHIFT (17U)
36613/*! RESERVED_17 - Reserved. Return zeroes on reads.
36614 */
36615#define DDRPHY_DX8SL2DXCTL2_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL2DXCTL2_RESERVED_17_MASK)
36616#define DDRPHY_DX8SL2DXCTL2_PREOEX_MASK (0xC0000U)
36617#define DDRPHY_DX8SL2DXCTL2_PREOEX_SHIFT (18U)
36618/*! PREOEX - OE Extension during Pre-amble
36619 */
36620#define DDRPHY_DX8SL2DXCTL2_PREOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL2DXCTL2_PREOEX_MASK)
36621#define DDRPHY_DX8SL2DXCTL2_POSOEX_MASK (0x700000U)
36622#define DDRPHY_DX8SL2DXCTL2_POSOEX_SHIFT (20U)
36623/*! POSOEX - OX Extension during Post-amble
36624 */
36625#define DDRPHY_DX8SL2DXCTL2_POSOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL2DXCTL2_POSOEX_MASK)
36626#define DDRPHY_DX8SL2DXCTL2_CRDEN_MASK (0x800000U)
36627#define DDRPHY_DX8SL2DXCTL2_CRDEN_SHIFT (23U)
36628/*! CRDEN - Configurable Read Data Enable
36629 */
36630#define DDRPHY_DX8SL2DXCTL2_CRDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL2DXCTL2_CRDEN_MASK)
36631#define DDRPHY_DX8SL2DXCTL2_RESERVED_31_24_MASK (0xFF000000U)
36632#define DDRPHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT (24U)
36633/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
36634 */
36635#define DDRPHY_DX8SL2DXCTL2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL2DXCTL2_RESERVED_31_24_MASK)
36636/*! @} */
36637
36638/*! @name DX8SL2IOCR - DATX8 0-1 I/O Configuration Register */
36639/*! @{ */
36640#define DDRPHY_DX8SL2IOCR_DXRXM_MASK (0x7FFU)
36641#define DDRPHY_DX8SL2IOCR_DXRXM_SHIFT (0U)
36642/*! DXRXM - DX IO Receiver Mode
36643 */
36644#define DDRPHY_DX8SL2IOCR_DXRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL2IOCR_DXRXM_MASK)
36645#define DDRPHY_DX8SL2IOCR_DXTXM_MASK (0x3FF800U)
36646#define DDRPHY_DX8SL2IOCR_DXTXM_SHIFT (11U)
36647/*! DXTXM - DX IO Transmitter Mode
36648 */
36649#define DDRPHY_DX8SL2IOCR_DXTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL2IOCR_DXTXM_MASK)
36650#define DDRPHY_DX8SL2IOCR_DXIOM_MASK (0x1C00000U)
36651#define DDRPHY_DX8SL2IOCR_DXIOM_SHIFT (22U)
36652/*! DXIOM - DX IO Mode
36653 */
36654#define DDRPHY_DX8SL2IOCR_DXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL2IOCR_DXIOM_MASK)
36655#define DDRPHY_DX8SL2IOCR_DXVREFIOM_MASK (0xE000000U)
36656#define DDRPHY_DX8SL2IOCR_DXVREFIOM_SHIFT (25U)
36657/*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
36658 */
36659#define DDRPHY_DX8SL2IOCR_DXVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL2IOCR_DXVREFIOM_MASK)
36660#define DDRPHY_DX8SL2IOCR_DXDACRANGE_MASK (0x70000000U)
36661#define DDRPHY_DX8SL2IOCR_DXDACRANGE_SHIFT (28U)
36662/*! DXDACRANGE - PVREF_DAC REFSEL range select
36663 */
36664#define DDRPHY_DX8SL2IOCR_DXDACRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL2IOCR_DXDACRANGE_MASK)
36665#define DDRPHY_DX8SL2IOCR_RESERVED_31_MASK (0x80000000U)
36666#define DDRPHY_DX8SL2IOCR_RESERVED_31_SHIFT (31U)
36667/*! RESERVED_31 - Reserved. Return zeroes on reads.
36668 */
36669#define DDRPHY_DX8SL2IOCR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL2IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL2IOCR_RESERVED_31_MASK)
36670/*! @} */
36671
36672/*! @name DX4SL2IOCR - DATX4 Slice 0-1 I/O Configuration Register */
36673/*! @{ */
36674#define DDRPHY_DX4SL2IOCR_RESERVED_31_0_MASK (0xFFFFFFFFU)
36675#define DDRPHY_DX4SL2IOCR_RESERVED_31_0_SHIFT (0U)
36676/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
36677 */
36678#define DDRPHY_DX4SL2IOCR_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL2IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL2IOCR_RESERVED_31_0_MASK)
36679/*! @} */
36680
36681/*! @name DX8SL3OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */
36682/*! @{ */
36683#define DDRPHY_DX8SL3OSC_OSCEN_MASK (0x1U)
36684#define DDRPHY_DX8SL3OSC_OSCEN_SHIFT (0U)
36685/*! OSCEN - Oscillator Enable
36686 */
36687#define DDRPHY_DX8SL3OSC_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL3OSC_OSCEN_MASK)
36688#define DDRPHY_DX8SL3OSC_OSCDIV_MASK (0x1EU)
36689#define DDRPHY_DX8SL3OSC_OSCDIV_SHIFT (1U)
36690/*! OSCDIV - Oscillator Mode Division
36691 */
36692#define DDRPHY_DX8SL3OSC_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL3OSC_OSCDIV_MASK)
36693#define DDRPHY_DX8SL3OSC_OSCWDL_MASK (0x60U)
36694#define DDRPHY_DX8SL3OSC_OSCWDL_SHIFT (5U)
36695/*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select
36696 */
36697#define DDRPHY_DX8SL3OSC_OSCWDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL3OSC_OSCWDL_MASK)
36698#define DDRPHY_DX8SL3OSC_RESERVED_8_7_MASK (0x180U)
36699#define DDRPHY_DX8SL3OSC_RESERVED_8_7_SHIFT (7U)
36700/*! RESERVED_8_7 - Reserved. Caution, do not write to this register field.
36701 */
36702#define DDRPHY_DX8SL3OSC_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL3OSC_RESERVED_8_7_MASK)
36703#define DDRPHY_DX8SL3OSC_OSCWDDL_MASK (0x600U)
36704#define DDRPHY_DX8SL3OSC_OSCWDDL_SHIFT (9U)
36705/*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select
36706 */
36707#define DDRPHY_DX8SL3OSC_OSCWDDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL3OSC_OSCWDDL_MASK)
36708#define DDRPHY_DX8SL3OSC_RESERVED_12_11_MASK (0x1800U)
36709#define DDRPHY_DX8SL3OSC_RESERVED_12_11_SHIFT (11U)
36710/*! RESERVED_12_11 - Reserved. Caution, do not write to this register field.
36711 */
36712#define DDRPHY_DX8SL3OSC_RESERVED_12_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL3OSC_RESERVED_12_11_MASK)
36713#define DDRPHY_DX8SL3OSC_DLTMODE_MASK (0x2000U)
36714#define DDRPHY_DX8SL3OSC_DLTMODE_SHIFT (13U)
36715/*! DLTMODE - Delay Line Test Mode
36716 */
36717#define DDRPHY_DX8SL3OSC_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL3OSC_DLTMODE_MASK)
36718#define DDRPHY_DX8SL3OSC_DLTST_MASK (0x4000U)
36719#define DDRPHY_DX8SL3OSC_DLTST_SHIFT (14U)
36720/*! DLTST - Delay Line Test Start
36721 */
36722#define DDRPHY_DX8SL3OSC_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_DLTST_SHIFT)) & DDRPHY_DX8SL3OSC_DLTST_MASK)
36723#define DDRPHY_DX8SL3OSC_PHYFRST_MASK (0x8000U)
36724#define DDRPHY_DX8SL3OSC_PHYFRST_SHIFT (15U)
36725/*! PHYFRST - PHY FIFO Reset
36726 */
36727#define DDRPHY_DX8SL3OSC_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL3OSC_PHYFRST_MASK)
36728#define DDRPHY_DX8SL3OSC_PHYHRST_MASK (0x10000U)
36729#define DDRPHY_DX8SL3OSC_PHYHRST_SHIFT (16U)
36730/*! PHYHRST - PHY High-Speed Reset
36731 */
36732#define DDRPHY_DX8SL3OSC_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL3OSC_PHYHRST_MASK)
36733#define DDRPHY_DX8SL3OSC_LBDQSS_MASK (0x20000U)
36734#define DDRPHY_DX8SL3OSC_LBDQSS_SHIFT (17U)
36735/*! LBDQSS - Loopback DQS Shift
36736 */
36737#define DDRPHY_DX8SL3OSC_LBDQSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL3OSC_LBDQSS_MASK)
36738#define DDRPHY_DX8SL3OSC_LBGDQS_MASK (0xC0000U)
36739#define DDRPHY_DX8SL3OSC_LBGDQS_SHIFT (18U)
36740/*! LBGDQS - Loopback DQS Gating
36741 */
36742#define DDRPHY_DX8SL3OSC_LBGDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL3OSC_LBGDQS_MASK)
36743#define DDRPHY_DX8SL3OSC_LBGSDQS_MASK (0x100000U)
36744#define DDRPHY_DX8SL3OSC_LBGSDQS_SHIFT (20U)
36745/*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
36746 */
36747#define DDRPHY_DX8SL3OSC_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL3OSC_LBGSDQS_MASK)
36748#define DDRPHY_DX8SL3OSC_LBMODE_MASK (0x200000U)
36749#define DDRPHY_DX8SL3OSC_LBMODE_SHIFT (21U)
36750/*! LBMODE - Loopback Mode
36751 */
36752#define DDRPHY_DX8SL3OSC_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL3OSC_LBMODE_MASK)
36753#define DDRPHY_DX8SL3OSC_CLKLEVEL_MASK (0xC00000U)
36754#define DDRPHY_DX8SL3OSC_CLKLEVEL_SHIFT (22U)
36755/*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled.
36756 */
36757#define DDRPHY_DX8SL3OSC_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL3OSC_CLKLEVEL_MASK)
36758#define DDRPHY_DX8SL3OSC_GATEDXCTLCLK_MASK (0x3000000U)
36759#define DDRPHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT (24U)
36760/*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk
36761 */
36762#define DDRPHY_DX8SL3OSC_GATEDXCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL3OSC_GATEDXCTLCLK_MASK)
36763#define DDRPHY_DX8SL3OSC_GATEDXDDRCLK_MASK (0xC000000U)
36764#define DDRPHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT (26U)
36765/*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk
36766 */
36767#define DDRPHY_DX8SL3OSC_GATEDXDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL3OSC_GATEDXDDRCLK_MASK)
36768#define DDRPHY_DX8SL3OSC_GATEDXRDCLK_MASK (0x30000000U)
36769#define DDRPHY_DX8SL3OSC_GATEDXRDCLK_SHIFT (28U)
36770/*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk
36771 */
36772#define DDRPHY_DX8SL3OSC_GATEDXRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL3OSC_GATEDXRDCLK_MASK)
36773#define DDRPHY_DX8SL3OSC_RESERVED_31_30_MASK (0xC0000000U)
36774#define DDRPHY_DX8SL3OSC_RESERVED_31_30_SHIFT (30U)
36775/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
36776 */
36777#define DDRPHY_DX8SL3OSC_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL3OSC_RESERVED_31_30_MASK)
36778/*! @} */
36779
36780/*! @name DX8SL3PLLCR0 - DAXT8 0-1 PLL Control Register 0 */
36781/*! @{ */
36782#define DDRPHY_DX8SL3PLLCR0_DTC_MASK (0xFU)
36783#define DDRPHY_DX8SL3PLLCR0_DTC_SHIFT (0U)
36784/*! DTC - Digital Test Control
36785 */
36786#define DDRPHY_DX8SL3PLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL3PLLCR0_DTC_MASK)
36787#define DDRPHY_DX8SL3PLLCR0_ATC_MASK (0xF0U)
36788#define DDRPHY_DX8SL3PLLCR0_ATC_SHIFT (4U)
36789/*! ATC - Analog Test Control
36790 */
36791#define DDRPHY_DX8SL3PLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL3PLLCR0_ATC_MASK)
36792#define DDRPHY_DX8SL3PLLCR0_ATOEN_MASK (0x100U)
36793#define DDRPHY_DX8SL3PLLCR0_ATOEN_SHIFT (8U)
36794/*! ATOEN - Analog Test Enable (ATOEN)
36795 */
36796#define DDRPHY_DX8SL3PLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL3PLLCR0_ATOEN_MASK)
36797#define DDRPHY_DX8SL3PLLCR0_RESERVED_11_9_MASK (0xE00U)
36798#define DDRPHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT (9U)
36799/*! RESERVED_11_9 - Reserved. Return zeroes on reads.
36800 */
36801#define DDRPHY_DX8SL3PLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL3PLLCR0_RESERVED_11_9_MASK)
36802#define DDRPHY_DX8SL3PLLCR0_GSHIFT_MASK (0x1000U)
36803#define DDRPHY_DX8SL3PLLCR0_GSHIFT_SHIFT (12U)
36804/*! GSHIFT - Gear Shift
36805 */
36806#define DDRPHY_DX8SL3PLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL3PLLCR0_GSHIFT_MASK)
36807#define DDRPHY_DX8SL3PLLCR0_CPIC_MASK (0x1E000U)
36808#define DDRPHY_DX8SL3PLLCR0_CPIC_SHIFT (13U)
36809/*! CPIC - Charge Pump Integrating Current Control
36810 */
36811#define DDRPHY_DX8SL3PLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL3PLLCR0_CPIC_MASK)
36812#define DDRPHY_DX8SL3PLLCR0_CPPC_MASK (0x7E0000U)
36813#define DDRPHY_DX8SL3PLLCR0_CPPC_SHIFT (17U)
36814/*! CPPC - Charge Pump Proportional Current Control
36815 */
36816#define DDRPHY_DX8SL3PLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL3PLLCR0_CPPC_MASK)
36817#define DDRPHY_DX8SL3PLLCR0_RLOCKM_MASK (0x800000U)
36818#define DDRPHY_DX8SL3PLLCR0_RLOCKM_SHIFT (23U)
36819/*! RLOCKM - Relock Mode
36820 */
36821#define DDRPHY_DX8SL3PLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL3PLLCR0_RLOCKM_MASK)
36822#define DDRPHY_DX8SL3PLLCR0_FRQSEL_MASK (0xF000000U)
36823#define DDRPHY_DX8SL3PLLCR0_FRQSEL_SHIFT (24U)
36824/*! FRQSEL - PLL Frequency Select
36825 */
36826#define DDRPHY_DX8SL3PLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL3PLLCR0_FRQSEL_MASK)
36827#define DDRPHY_DX8SL3PLLCR0_RSTOPM_MASK (0x10000000U)
36828#define DDRPHY_DX8SL3PLLCR0_RSTOPM_SHIFT (28U)
36829/*! RSTOPM - Reference Stop Mode
36830 */
36831#define DDRPHY_DX8SL3PLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL3PLLCR0_RSTOPM_MASK)
36832#define DDRPHY_DX8SL3PLLCR0_PLLPD_MASK (0x20000000U)
36833#define DDRPHY_DX8SL3PLLCR0_PLLPD_SHIFT (29U)
36834/*! PLLPD - PLL Power Down
36835 */
36836#define DDRPHY_DX8SL3PLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL3PLLCR0_PLLPD_MASK)
36837#define DDRPHY_DX8SL3PLLCR0_PLLRST_MASK (0x40000000U)
36838#define DDRPHY_DX8SL3PLLCR0_PLLRST_SHIFT (30U)
36839/*! PLLRST - PLL Reset
36840 */
36841#define DDRPHY_DX8SL3PLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL3PLLCR0_PLLRST_MASK)
36842#define DDRPHY_DX8SL3PLLCR0_PLLBYP_MASK (0x80000000U)
36843#define DDRPHY_DX8SL3PLLCR0_PLLBYP_SHIFT (31U)
36844/*! PLLBYP - PLL Bypass
36845 */
36846#define DDRPHY_DX8SL3PLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL3PLLCR0_PLLBYP_MASK)
36847/*! @} */
36848
36849/*! @name DX8SL3PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */
36850/*! @{ */
36851#define DDRPHY_DX8SL3PLLCR1_LOCKDS_MASK (0x1U)
36852#define DDRPHY_DX8SL3PLLCR1_LOCKDS_SHIFT (0U)
36853/*! LOCKDS - Lock Detector Select
36854 */
36855#define DDRPHY_DX8SL3PLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL3PLLCR1_LOCKDS_MASK)
36856#define DDRPHY_DX8SL3PLLCR1_LOCKCS_MASK (0x2U)
36857#define DDRPHY_DX8SL3PLLCR1_LOCKCS_SHIFT (1U)
36858/*! LOCKCS - Lock Detector Counter Select
36859 */
36860#define DDRPHY_DX8SL3PLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL3PLLCR1_LOCKCS_MASK)
36861#define DDRPHY_DX8SL3PLLCR1_LOCKPS_MASK (0x4U)
36862#define DDRPHY_DX8SL3PLLCR1_LOCKPS_SHIFT (2U)
36863/*! LOCKPS - Lock Detector Phase Select
36864 */
36865#define DDRPHY_DX8SL3PLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL3PLLCR1_LOCKPS_MASK)
36866#define DDRPHY_DX8SL3PLLCR1_BYPVDD_MASK (0x8U)
36867#define DDRPHY_DX8SL3PLLCR1_BYPVDD_SHIFT (3U)
36868/*! BYPVDD - PLL VDD voltage level control
36869 */
36870#define DDRPHY_DX8SL3PLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL3PLLCR1_BYPVDD_MASK)
36871#define DDRPHY_DX8SL3PLLCR1_BYPVREGDIG_MASK (0x10U)
36872#define DDRPHY_DX8SL3PLLCR1_BYPVREGDIG_SHIFT (4U)
36873/*! BYPVREGDIG - Bypass PLL vreg_dig
36874 */
36875#define DDRPHY_DX8SL3PLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL3PLLCR1_BYPVREGDIG_MASK)
36876#define DDRPHY_DX8SL3PLLCR1_BYPVREGCP_MASK (0x20U)
36877#define DDRPHY_DX8SL3PLLCR1_BYPVREGCP_SHIFT (5U)
36878/*! BYPVREGCP - Bypass PLL vreg_cp
36879 */
36880#define DDRPHY_DX8SL3PLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL3PLLCR1_BYPVREGCP_MASK)
36881#define DDRPHY_DX8SL3PLLCR1_PLLPROG_MASK (0x3FFFC0U)
36882#define DDRPHY_DX8SL3PLLCR1_PLLPROG_SHIFT (6U)
36883/*! PLLPROG - Connects to the PLL PLL_PROG bus.
36884 */
36885#define DDRPHY_DX8SL3PLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL3PLLCR1_PLLPROG_MASK)
36886#define DDRPHY_DX8SL3PLLCR1_RESERVED_31_22_MASK (0xFFC00000U)
36887#define DDRPHY_DX8SL3PLLCR1_RESERVED_31_22_SHIFT (22U)
36888/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
36889 */
36890#define DDRPHY_DX8SL3PLLCR1_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL3PLLCR1_RESERVED_31_22_MASK)
36891/*! @} */
36892
36893/*! @name DX8SL3PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */
36894/*! @{ */
36895#define DDRPHY_DX8SL3PLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU)
36896#define DDRPHY_DX8SL3PLLCR2_PLLCTRL_31_0_SHIFT (0U)
36897/*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
36898 */
36899#define DDRPHY_DX8SL3PLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL3PLLCR2_PLLCTRL_31_0_MASK)
36900/*! @} */
36901
36902/*! @name DX8SL3PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */
36903/*! @{ */
36904#define DDRPHY_DX8SL3PLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU)
36905#define DDRPHY_DX8SL3PLLCR3_PLLCTRL_63_32_SHIFT (0U)
36906/*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
36907 */
36908#define DDRPHY_DX8SL3PLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL3PLLCR3_PLLCTRL_63_32_MASK)
36909/*! @} */
36910
36911/*! @name DX8SL3PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */
36912/*! @{ */
36913#define DDRPHY_DX8SL3PLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU)
36914#define DDRPHY_DX8SL3PLLCR4_PLLCTRL_95_64_SHIFT (0U)
36915/*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
36916 */
36917#define DDRPHY_DX8SL3PLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL3PLLCR4_PLLCTRL_95_64_MASK)
36918/*! @} */
36919
36920/*! @name DX8SL3PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */
36921/*! @{ */
36922#define DDRPHY_DX8SL3PLLCR5_PLLCTRL_103_96_MASK (0xFFU)
36923#define DDRPHY_DX8SL3PLLCR5_PLLCTRL_103_96_SHIFT (0U)
36924/*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
36925 */
36926#define DDRPHY_DX8SL3PLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL3PLLCR5_PLLCTRL_103_96_MASK)
36927#define DDRPHY_DX8SL3PLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U)
36928#define DDRPHY_DX8SL3PLLCR5_RESERVED_31_8_SHIFT (8U)
36929/*! RESERVED_31_8 - Reserved. Return zeroes on reads.
36930 */
36931#define DDRPHY_DX8SL3PLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL3PLLCR5_RESERVED_31_8_MASK)
36932/*! @} */
36933
36934/*! @name DX8SL3DQSCTL - DATX8 0-1 DQS Control Register */
36935/*! @{ */
36936#define DDRPHY_DX8SL3DQSCTL_DQSRES_MASK (0xFU)
36937#define DDRPHY_DX8SL3DQSCTL_DQSRES_SHIFT (0U)
36938/*! DQSRES - DQS Resistor
36939 */
36940#define DDRPHY_DX8SL3DQSCTL_DQSRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL3DQSCTL_DQSRES_MASK)
36941#define DDRPHY_DX8SL3DQSCTL_DQSNRES_MASK (0xF0U)
36942#define DDRPHY_DX8SL3DQSCTL_DQSNRES_SHIFT (4U)
36943/*! DQSNRES - DQS_N Resistor
36944 */
36945#define DDRPHY_DX8SL3DQSCTL_DQSNRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL3DQSCTL_DQSNRES_MASK)
36946#define DDRPHY_DX8SL3DQSCTL_DXSR_MASK (0x300U)
36947#define DDRPHY_DX8SL3DQSCTL_DXSR_SHIFT (8U)
36948/*! DXSR - Data Slew Rate
36949 */
36950#define DDRPHY_DX8SL3DQSCTL_DXSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL3DQSCTL_DXSR_MASK)
36951#define DDRPHY_DX8SL3DQSCTL_RESERVED_12_10_MASK (0x1C00U)
36952#define DDRPHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT (10U)
36953/*! RESERVED_12_10 - Reserved. Return zeroes on reads.
36954 */
36955#define DDRPHY_DX8SL3DQSCTL_RESERVED_12_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL3DQSCTL_RESERVED_12_10_MASK)
36956#define DDRPHY_DX8SL3DQSCTL_UDQIOM_MASK (0x2000U)
36957#define DDRPHY_DX8SL3DQSCTL_UDQIOM_SHIFT (13U)
36958/*! UDQIOM - Unused DQ I/O Mode
36959 */
36960#define DDRPHY_DX8SL3DQSCTL_UDQIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL3DQSCTL_UDQIOM_MASK)
36961#define DDRPHY_DX8SL3DQSCTL_QSCNTEN_MASK (0x4000U)
36962#define DDRPHY_DX8SL3DQSCTL_QSCNTEN_SHIFT (14U)
36963/*! QSCNTEN - QS Counter Enable
36964 */
36965#define DDRPHY_DX8SL3DQSCTL_QSCNTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL3DQSCTL_QSCNTEN_MASK)
36966#define DDRPHY_DX8SL3DQSCTL_RESERVED_16_15_MASK (0x18000U)
36967#define DDRPHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT (15U)
36968/*! RESERVED_16_15 - Reserved. Return zeroes on reads.
36969 */
36970#define DDRPHY_DX8SL3DQSCTL_RESERVED_16_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL3DQSCTL_RESERVED_16_15_MASK)
36971#define DDRPHY_DX8SL3DQSCTL_LPIOPD_MASK (0x20000U)
36972#define DDRPHY_DX8SL3DQSCTL_LPIOPD_SHIFT (17U)
36973/*! LPIOPD - Low Power I/O Power Down
36974 */
36975#define DDRPHY_DX8SL3DQSCTL_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL3DQSCTL_LPIOPD_MASK)
36976#define DDRPHY_DX8SL3DQSCTL_LPPLLPD_MASK (0x40000U)
36977#define DDRPHY_DX8SL3DQSCTL_LPPLLPD_SHIFT (18U)
36978/*! LPPLLPD - Low Power PLL Power Down
36979 */
36980#define DDRPHY_DX8SL3DQSCTL_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL3DQSCTL_LPPLLPD_MASK)
36981#define DDRPHY_DX8SL3DQSCTL_DQSGX_MASK (0x180000U)
36982#define DDRPHY_DX8SL3DQSCTL_DQSGX_SHIFT (19U)
36983/*! DQSGX - DQS Gate Extension
36984 */
36985#define DDRPHY_DX8SL3DQSCTL_DQSGX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL3DQSCTL_DQSGX_MASK)
36986#define DDRPHY_DX8SL3DQSCTL_WRRMODE_MASK (0x200000U)
36987#define DDRPHY_DX8SL3DQSCTL_WRRMODE_SHIFT (21U)
36988/*! WRRMODE - Write Path Rise-to-Rise Mode
36989 */
36990#define DDRPHY_DX8SL3DQSCTL_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL3DQSCTL_WRRMODE_MASK)
36991#define DDRPHY_DX8SL3DQSCTL_RESERVED_23_22_MASK (0xC00000U)
36992#define DDRPHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT (22U)
36993/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
36994 */
36995#define DDRPHY_DX8SL3DQSCTL_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL3DQSCTL_RESERVED_23_22_MASK)
36996#define DDRPHY_DX8SL3DQSCTL_RRRMODE_MASK (0x1000000U)
36997#define DDRPHY_DX8SL3DQSCTL_RRRMODE_SHIFT (24U)
36998/*! RRRMODE - Read Path Rise-to-Rise Mode
36999 */
37000#define DDRPHY_DX8SL3DQSCTL_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL3DQSCTL_RRRMODE_MASK)
37001#define DDRPHY_DX8SL3DQSCTL_RESERVED_31_25_MASK (0xFE000000U)
37002#define DDRPHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT (25U)
37003/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
37004 */
37005#define DDRPHY_DX8SL3DQSCTL_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL3DQSCTL_RESERVED_31_25_MASK)
37006/*! @} */
37007
37008/*! @name DX8SL3TRNCTL - DATX8 0-1 Training Control Register */
37009/*! @{ */
37010#define DDRPHY_DX8SL3TRNCTL_RESERVED_31_0_MASK (0xFFFFFFFFU)
37011#define DDRPHY_DX8SL3TRNCTL_RESERVED_31_0_SHIFT (0U)
37012/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
37013 */
37014#define DDRPHY_DX8SL3TRNCTL_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL3TRNCTL_RESERVED_31_0_MASK)
37015/*! @} */
37016
37017/*! @name DX8SL3DDLCTL - DATX8 0-1 DDL Control Register */
37018/*! @{ */
37019#define DDRPHY_DX8SL3DDLCTL_DDLBYPMODE_MASK (0x3U)
37020#define DDRPHY_DX8SL3DDLCTL_DDLBYPMODE_SHIFT (0U)
37021/*! DDLBYPMODE - Controls DDL Bypass Mode
37022 */
37023#define DDRPHY_DX8SL3DDLCTL_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL3DDLCTL_DDLBYPMODE_MASK)
37024#define DDRPHY_DX8SL3DDLCTL_DXDDLBYP_MASK (0x3FFFCU)
37025#define DDRPHY_DX8SL3DDLCTL_DXDDLBYP_SHIFT (2U)
37026/*! DXDDLBYP - DATX8 DDL Bypass
37027 */
37028#define DDRPHY_DX8SL3DDLCTL_DXDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL3DDLCTL_DXDDLBYP_MASK)
37029#define DDRPHY_DX8SL3DDLCTL_DXDDLLD_MASK (0x7C0000U)
37030#define DDRPHY_DX8SL3DDLCTL_DXDDLLD_SHIFT (18U)
37031/*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load
37032 */
37033#define DDRPHY_DX8SL3DDLCTL_DXDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL3DDLCTL_DXDDLLD_MASK)
37034#define DDRPHY_DX8SL3DDLCTL_RESERVED_24_23_MASK (0x1800000U)
37035#define DDRPHY_DX8SL3DDLCTL_RESERVED_24_23_SHIFT (23U)
37036/*! RESERVED_24_23 - Reserved. Return zeroes on reads.
37037 */
37038#define DDRPHY_DX8SL3DDLCTL_RESERVED_24_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL3DDLCTL_RESERVED_24_23_MASK)
37039#define DDRPHY_DX8SL3DDLCTL_DXDDLLDT_MASK (0x2000000U)
37040#define DDRPHY_DX8SL3DDLCTL_DXDDLLDT_SHIFT (25U)
37041/*! DXDDLLDT - DX DDL Load Type
37042 */
37043#define DDRPHY_DX8SL3DDLCTL_DXDDLLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL3DDLCTL_DXDDLLDT_MASK)
37044#define DDRPHY_DX8SL3DDLCTL_DLYLDTM_MASK (0x4000000U)
37045#define DDRPHY_DX8SL3DDLCTL_DLYLDTM_SHIFT (26U)
37046/*! DLYLDTM - Delay Load Timing
37047 */
37048#define DDRPHY_DX8SL3DDLCTL_DLYLDTM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL3DDLCTL_DLYLDTM_MASK)
37049#define DDRPHY_DX8SL3DDLCTL_RESERVED_31_27_MASK (0xF8000000U)
37050#define DDRPHY_DX8SL3DDLCTL_RESERVED_31_27_SHIFT (27U)
37051/*! RESERVED_31_27 - Reserved. Return zeroes on reads.
37052 */
37053#define DDRPHY_DX8SL3DDLCTL_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL3DDLCTL_RESERVED_31_27_MASK)
37054/*! @} */
37055
37056/*! @name DX8SL3DXCTL1 - DATX8 0-1 DX Control Register 1 */
37057/*! @{ */
37058#define DDRPHY_DX8SL3DXCTL1_RESERVED_15_0_MASK (0xFFFFU)
37059#define DDRPHY_DX8SL3DXCTL1_RESERVED_15_0_SHIFT (0U)
37060/*! RESERVED_15_0 - Reserved. Return zeroes on reads.
37061 */
37062#define DDRPHY_DX8SL3DXCTL1_RESERVED_15_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL3DXCTL1_RESERVED_15_0_MASK)
37063#define DDRPHY_DX8SL3DXCTL1_DXTMODE_MASK (0x10000U)
37064#define DDRPHY_DX8SL3DXCTL1_DXTMODE_SHIFT (16U)
37065/*! DXTMODE - DATX8 Test Mode
37066 */
37067#define DDRPHY_DX8SL3DXCTL1_DXTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXTMODE_MASK)
37068#define DDRPHY_DX8SL3DXCTL1_DXGDBYP_MASK (0x20000U)
37069#define DDRPHY_DX8SL3DXCTL1_DXGDBYP_SHIFT (17U)
37070/*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode
37071 */
37072#define DDRPHY_DX8SL3DXCTL1_DXGDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXGDBYP_MASK)
37073#define DDRPHY_DX8SL3DXCTL1_DXQSDBYP_MASK (0x40000U)
37074#define DDRPHY_DX8SL3DXCTL1_DXQSDBYP_SHIFT (18U)
37075/*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode
37076 */
37077#define DDRPHY_DX8SL3DXCTL1_DXQSDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXQSDBYP_MASK)
37078#define DDRPHY_DX8SL3DXCTL1_DXGSMD_MASK (0x80000U)
37079#define DDRPHY_DX8SL3DXCTL1_DXGSMD_SHIFT (19U)
37080/*! DXGSMD - Read DQS Gating Status Mode
37081 */
37082#define DDRPHY_DX8SL3DXCTL1_DXGSMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXGSMD_MASK)
37083#define DDRPHY_DX8SL3DXCTL1_DXDTOSEL_MASK (0x300000U)
37084#define DDRPHY_DX8SL3DXCTL1_DXDTOSEL_SHIFT (20U)
37085/*! DXDTOSEL - DATX8 Digital Test Output Select
37086 */
37087#define DDRPHY_DX8SL3DXCTL1_DXDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXDTOSEL_MASK)
37088#define DDRPHY_DX8SL3DXCTL1_RESERVED_22_MASK (0x400000U)
37089#define DDRPHY_DX8SL3DXCTL1_RESERVED_22_SHIFT (22U)
37090/*! RESERVED_22 - Reserved. Return zeroes on reads.
37091 */
37092#define DDRPHY_DX8SL3DXCTL1_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL3DXCTL1_RESERVED_22_MASK)
37093#define DDRPHY_DX8SL3DXCTL1_DXRCLKMD_MASK (0x800000U)
37094#define DDRPHY_DX8SL3DXCTL1_DXRCLKMD_SHIFT (23U)
37095/*! DXRCLKMD - DATX8 Read Clock Mode
37096 */
37097#define DDRPHY_DX8SL3DXCTL1_DXRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXRCLKMD_MASK)
37098#define DDRPHY_DX8SL3DXCTL1_DXCALCLK_MASK (0x1000000U)
37099#define DDRPHY_DX8SL3DXCTL1_DXCALCLK_SHIFT (24U)
37100/*! DXCALCLK - DATX Calibration Clock Select
37101 */
37102#define DDRPHY_DX8SL3DXCTL1_DXCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL3DXCTL1_DXCALCLK_MASK)
37103#define DDRPHY_DX8SL3DXCTL1_RESERVED_31_25_MASK (0xFE000000U)
37104#define DDRPHY_DX8SL3DXCTL1_RESERVED_31_25_SHIFT (25U)
37105/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
37106 */
37107#define DDRPHY_DX8SL3DXCTL1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL3DXCTL1_RESERVED_31_25_MASK)
37108/*! @} */
37109
37110/*! @name DX8SL3DXCTL2 - DATX8 0-1 DX Control Register 2 */
37111/*! @{ */
37112#define DDRPHY_DX8SL3DXCTL2_RESERVED_0_MASK (0x1U)
37113#define DDRPHY_DX8SL3DXCTL2_RESERVED_0_SHIFT (0U)
37114/*! RESERVED_0 - Reserved. Return zeroes on reads.
37115 */
37116#define DDRPHY_DX8SL3DXCTL2_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL3DXCTL2_RESERVED_0_MASK)
37117#define DDRPHY_DX8SL3DXCTL2_DQSGLB_MASK (0x6U)
37118#define DDRPHY_DX8SL3DXCTL2_DQSGLB_SHIFT (1U)
37119/*! DQSGLB - Read DQS Gate I/O Loopback
37120 */
37121#define DDRPHY_DX8SL3DXCTL2_DQSGLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL3DXCTL2_DQSGLB_MASK)
37122#define DDRPHY_DX8SL3DXCTL2_DISRST_MASK (0x8U)
37123#define DDRPHY_DX8SL3DXCTL2_DISRST_SHIFT (3U)
37124/*! DISRST - Disables the Read FIFO Reset
37125 */
37126#define DDRPHY_DX8SL3DXCTL2_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL3DXCTL2_DISRST_MASK)
37127#define DDRPHY_DX8SL3DXCTL2_RDMODE_MASK (0x30U)
37128#define DDRPHY_DX8SL3DXCTL2_RDMODE_SHIFT (4U)
37129/*! RDMODE - DATX8 Receive FIFO Read Mode
37130 */
37131#define DDRPHY_DX8SL3DXCTL2_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL3DXCTL2_RDMODE_MASK)
37132#define DDRPHY_DX8SL3DXCTL2_PRFBYP_MASK (0x40U)
37133#define DDRPHY_DX8SL3DXCTL2_PRFBYP_SHIFT (6U)
37134/*! PRFBYP - PUB Read FIFO Bypass
37135 */
37136#define DDRPHY_DX8SL3DXCTL2_PRFBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL3DXCTL2_PRFBYP_MASK)
37137#define DDRPHY_DX8SL3DXCTL2_WDBI_MASK (0x80U)
37138#define DDRPHY_DX8SL3DXCTL2_WDBI_SHIFT (7U)
37139/*! WDBI - Write Data Bus Inversion Enable
37140 */
37141#define DDRPHY_DX8SL3DXCTL2_WDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL3DXCTL2_WDBI_MASK)
37142#define DDRPHY_DX8SL3DXCTL2_RDBI_MASK (0x100U)
37143#define DDRPHY_DX8SL3DXCTL2_RDBI_SHIFT (8U)
37144/*! RDBI - Read Data Bus Inversion Enable
37145 */
37146#define DDRPHY_DX8SL3DXCTL2_RDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL3DXCTL2_RDBI_MASK)
37147#define DDRPHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK (0x1E00U)
37148#define DDRPHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT (9U)
37149/*! LPWAKEUP_THRSH - Low Power Wakeup Threshold
37150 */
37151#define DDRPHY_DX8SL3DXCTL2_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK)
37152#define DDRPHY_DX8SL3DXCTL2_RESERVED_14_13_MASK (0x6000U)
37153#define DDRPHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT (13U)
37154/*! RESERVED_14_13 - Reserved. Return zeroes on reads.
37155 */
37156#define DDRPHY_DX8SL3DXCTL2_RESERVED_14_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL3DXCTL2_RESERVED_14_13_MASK)
37157#define DDRPHY_DX8SL3DXCTL2_IOLB_MASK (0x8000U)
37158#define DDRPHY_DX8SL3DXCTL2_IOLB_SHIFT (15U)
37159/*! IOLB - I/O Loopback Select
37160 */
37161#define DDRPHY_DX8SL3DXCTL2_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL3DXCTL2_IOLB_MASK)
37162#define DDRPHY_DX8SL3DXCTL2_IOAG_MASK (0x10000U)
37163#define DDRPHY_DX8SL3DXCTL2_IOAG_SHIFT (16U)
37164/*! IOAG - I/O Assisted Gate Select
37165 */
37166#define DDRPHY_DX8SL3DXCTL2_IOAG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL3DXCTL2_IOAG_MASK)
37167#define DDRPHY_DX8SL3DXCTL2_RESERVED_17_MASK (0x20000U)
37168#define DDRPHY_DX8SL3DXCTL2_RESERVED_17_SHIFT (17U)
37169/*! RESERVED_17 - Reserved. Return zeroes on reads.
37170 */
37171#define DDRPHY_DX8SL3DXCTL2_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL3DXCTL2_RESERVED_17_MASK)
37172#define DDRPHY_DX8SL3DXCTL2_PREOEX_MASK (0xC0000U)
37173#define DDRPHY_DX8SL3DXCTL2_PREOEX_SHIFT (18U)
37174/*! PREOEX - OE Extension during Pre-amble
37175 */
37176#define DDRPHY_DX8SL3DXCTL2_PREOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL3DXCTL2_PREOEX_MASK)
37177#define DDRPHY_DX8SL3DXCTL2_POSOEX_MASK (0x700000U)
37178#define DDRPHY_DX8SL3DXCTL2_POSOEX_SHIFT (20U)
37179/*! POSOEX - OX Extension during Post-amble
37180 */
37181#define DDRPHY_DX8SL3DXCTL2_POSOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL3DXCTL2_POSOEX_MASK)
37182#define DDRPHY_DX8SL3DXCTL2_CRDEN_MASK (0x800000U)
37183#define DDRPHY_DX8SL3DXCTL2_CRDEN_SHIFT (23U)
37184/*! CRDEN - Configurable Read Data Enable
37185 */
37186#define DDRPHY_DX8SL3DXCTL2_CRDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL3DXCTL2_CRDEN_MASK)
37187#define DDRPHY_DX8SL3DXCTL2_RESERVED_31_24_MASK (0xFF000000U)
37188#define DDRPHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT (24U)
37189/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
37190 */
37191#define DDRPHY_DX8SL3DXCTL2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL3DXCTL2_RESERVED_31_24_MASK)
37192/*! @} */
37193
37194/*! @name DX8SL3IOCR - DATX8 0-1 I/O Configuration Register */
37195/*! @{ */
37196#define DDRPHY_DX8SL3IOCR_DXRXM_MASK (0x7FFU)
37197#define DDRPHY_DX8SL3IOCR_DXRXM_SHIFT (0U)
37198/*! DXRXM - DX IO Receiver Mode
37199 */
37200#define DDRPHY_DX8SL3IOCR_DXRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL3IOCR_DXRXM_MASK)
37201#define DDRPHY_DX8SL3IOCR_DXTXM_MASK (0x3FF800U)
37202#define DDRPHY_DX8SL3IOCR_DXTXM_SHIFT (11U)
37203/*! DXTXM - DX IO Transmitter Mode
37204 */
37205#define DDRPHY_DX8SL3IOCR_DXTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL3IOCR_DXTXM_MASK)
37206#define DDRPHY_DX8SL3IOCR_DXIOM_MASK (0x1C00000U)
37207#define DDRPHY_DX8SL3IOCR_DXIOM_SHIFT (22U)
37208/*! DXIOM - DX IO Mode
37209 */
37210#define DDRPHY_DX8SL3IOCR_DXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL3IOCR_DXIOM_MASK)
37211#define DDRPHY_DX8SL3IOCR_DXVREFIOM_MASK (0xE000000U)
37212#define DDRPHY_DX8SL3IOCR_DXVREFIOM_SHIFT (25U)
37213/*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
37214 */
37215#define DDRPHY_DX8SL3IOCR_DXVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL3IOCR_DXVREFIOM_MASK)
37216#define DDRPHY_DX8SL3IOCR_DXDACRANGE_MASK (0x70000000U)
37217#define DDRPHY_DX8SL3IOCR_DXDACRANGE_SHIFT (28U)
37218/*! DXDACRANGE - PVREF_DAC REFSEL range select
37219 */
37220#define DDRPHY_DX8SL3IOCR_DXDACRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL3IOCR_DXDACRANGE_MASK)
37221#define DDRPHY_DX8SL3IOCR_RESERVED_31_MASK (0x80000000U)
37222#define DDRPHY_DX8SL3IOCR_RESERVED_31_SHIFT (31U)
37223/*! RESERVED_31 - Reserved. Return zeroes on reads.
37224 */
37225#define DDRPHY_DX8SL3IOCR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL3IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL3IOCR_RESERVED_31_MASK)
37226/*! @} */
37227
37228/*! @name DX4SL3IOCR - DATX4 Slice 0-1 I/O Configuration Register */
37229/*! @{ */
37230#define DDRPHY_DX4SL3IOCR_RESERVED_31_0_MASK (0xFFFFFFFFU)
37231#define DDRPHY_DX4SL3IOCR_RESERVED_31_0_SHIFT (0U)
37232/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
37233 */
37234#define DDRPHY_DX4SL3IOCR_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL3IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL3IOCR_RESERVED_31_0_MASK)
37235/*! @} */
37236
37237/*! @name DX8SL4OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */
37238/*! @{ */
37239#define DDRPHY_DX8SL4OSC_OSCEN_MASK (0x1U)
37240#define DDRPHY_DX8SL4OSC_OSCEN_SHIFT (0U)
37241/*! OSCEN - Oscillator Enable
37242 */
37243#define DDRPHY_DX8SL4OSC_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL4OSC_OSCEN_MASK)
37244#define DDRPHY_DX8SL4OSC_OSCDIV_MASK (0x1EU)
37245#define DDRPHY_DX8SL4OSC_OSCDIV_SHIFT (1U)
37246/*! OSCDIV - Oscillator Mode Division
37247 */
37248#define DDRPHY_DX8SL4OSC_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL4OSC_OSCDIV_MASK)
37249#define DDRPHY_DX8SL4OSC_OSCWDL_MASK (0x60U)
37250#define DDRPHY_DX8SL4OSC_OSCWDL_SHIFT (5U)
37251/*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select
37252 */
37253#define DDRPHY_DX8SL4OSC_OSCWDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL4OSC_OSCWDL_MASK)
37254#define DDRPHY_DX8SL4OSC_RESERVED_8_7_MASK (0x180U)
37255#define DDRPHY_DX8SL4OSC_RESERVED_8_7_SHIFT (7U)
37256/*! RESERVED_8_7 - Reserved. Caution, do not write to this register field.
37257 */
37258#define DDRPHY_DX8SL4OSC_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL4OSC_RESERVED_8_7_MASK)
37259#define DDRPHY_DX8SL4OSC_OSCWDDL_MASK (0x600U)
37260#define DDRPHY_DX8SL4OSC_OSCWDDL_SHIFT (9U)
37261/*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select
37262 */
37263#define DDRPHY_DX8SL4OSC_OSCWDDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL4OSC_OSCWDDL_MASK)
37264#define DDRPHY_DX8SL4OSC_RESERVED_12_11_MASK (0x1800U)
37265#define DDRPHY_DX8SL4OSC_RESERVED_12_11_SHIFT (11U)
37266/*! RESERVED_12_11 - Reserved. Caution, do not write to this register field.
37267 */
37268#define DDRPHY_DX8SL4OSC_RESERVED_12_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL4OSC_RESERVED_12_11_MASK)
37269#define DDRPHY_DX8SL4OSC_DLTMODE_MASK (0x2000U)
37270#define DDRPHY_DX8SL4OSC_DLTMODE_SHIFT (13U)
37271/*! DLTMODE - Delay Line Test Mode
37272 */
37273#define DDRPHY_DX8SL4OSC_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL4OSC_DLTMODE_MASK)
37274#define DDRPHY_DX8SL4OSC_DLTST_MASK (0x4000U)
37275#define DDRPHY_DX8SL4OSC_DLTST_SHIFT (14U)
37276/*! DLTST - Delay Line Test Start
37277 */
37278#define DDRPHY_DX8SL4OSC_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_DLTST_SHIFT)) & DDRPHY_DX8SL4OSC_DLTST_MASK)
37279#define DDRPHY_DX8SL4OSC_PHYFRST_MASK (0x8000U)
37280#define DDRPHY_DX8SL4OSC_PHYFRST_SHIFT (15U)
37281/*! PHYFRST - PHY FIFO Reset
37282 */
37283#define DDRPHY_DX8SL4OSC_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL4OSC_PHYFRST_MASK)
37284#define DDRPHY_DX8SL4OSC_PHYHRST_MASK (0x10000U)
37285#define DDRPHY_DX8SL4OSC_PHYHRST_SHIFT (16U)
37286/*! PHYHRST - PHY High-Speed Reset
37287 */
37288#define DDRPHY_DX8SL4OSC_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL4OSC_PHYHRST_MASK)
37289#define DDRPHY_DX8SL4OSC_LBDQSS_MASK (0x20000U)
37290#define DDRPHY_DX8SL4OSC_LBDQSS_SHIFT (17U)
37291/*! LBDQSS - Loopback DQS Shift
37292 */
37293#define DDRPHY_DX8SL4OSC_LBDQSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL4OSC_LBDQSS_MASK)
37294#define DDRPHY_DX8SL4OSC_LBGDQS_MASK (0xC0000U)
37295#define DDRPHY_DX8SL4OSC_LBGDQS_SHIFT (18U)
37296/*! LBGDQS - Loopback DQS Gating
37297 */
37298#define DDRPHY_DX8SL4OSC_LBGDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL4OSC_LBGDQS_MASK)
37299#define DDRPHY_DX8SL4OSC_LBGSDQS_MASK (0x100000U)
37300#define DDRPHY_DX8SL4OSC_LBGSDQS_SHIFT (20U)
37301/*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
37302 */
37303#define DDRPHY_DX8SL4OSC_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL4OSC_LBGSDQS_MASK)
37304#define DDRPHY_DX8SL4OSC_LBMODE_MASK (0x200000U)
37305#define DDRPHY_DX8SL4OSC_LBMODE_SHIFT (21U)
37306/*! LBMODE - Loopback Mode
37307 */
37308#define DDRPHY_DX8SL4OSC_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL4OSC_LBMODE_MASK)
37309#define DDRPHY_DX8SL4OSC_CLKLEVEL_MASK (0xC00000U)
37310#define DDRPHY_DX8SL4OSC_CLKLEVEL_SHIFT (22U)
37311/*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled.
37312 */
37313#define DDRPHY_DX8SL4OSC_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL4OSC_CLKLEVEL_MASK)
37314#define DDRPHY_DX8SL4OSC_GATEDXCTLCLK_MASK (0x3000000U)
37315#define DDRPHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT (24U)
37316/*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk
37317 */
37318#define DDRPHY_DX8SL4OSC_GATEDXCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL4OSC_GATEDXCTLCLK_MASK)
37319#define DDRPHY_DX8SL4OSC_GATEDXDDRCLK_MASK (0xC000000U)
37320#define DDRPHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT (26U)
37321/*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk
37322 */
37323#define DDRPHY_DX8SL4OSC_GATEDXDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL4OSC_GATEDXDDRCLK_MASK)
37324#define DDRPHY_DX8SL4OSC_GATEDXRDCLK_MASK (0x30000000U)
37325#define DDRPHY_DX8SL4OSC_GATEDXRDCLK_SHIFT (28U)
37326/*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk
37327 */
37328#define DDRPHY_DX8SL4OSC_GATEDXRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL4OSC_GATEDXRDCLK_MASK)
37329#define DDRPHY_DX8SL4OSC_RESERVED_31_30_MASK (0xC0000000U)
37330#define DDRPHY_DX8SL4OSC_RESERVED_31_30_SHIFT (30U)
37331/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
37332 */
37333#define DDRPHY_DX8SL4OSC_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL4OSC_RESERVED_31_30_MASK)
37334/*! @} */
37335
37336/*! @name DX8SL4PLLCR0 - DAXT8 0-1 PLL Control Register 0 */
37337/*! @{ */
37338#define DDRPHY_DX8SL4PLLCR0_DTC_MASK (0xFU)
37339#define DDRPHY_DX8SL4PLLCR0_DTC_SHIFT (0U)
37340/*! DTC - Digital Test Control
37341 */
37342#define DDRPHY_DX8SL4PLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL4PLLCR0_DTC_MASK)
37343#define DDRPHY_DX8SL4PLLCR0_ATC_MASK (0xF0U)
37344#define DDRPHY_DX8SL4PLLCR0_ATC_SHIFT (4U)
37345/*! ATC - Analog Test Control
37346 */
37347#define DDRPHY_DX8SL4PLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL4PLLCR0_ATC_MASK)
37348#define DDRPHY_DX8SL4PLLCR0_ATOEN_MASK (0x100U)
37349#define DDRPHY_DX8SL4PLLCR0_ATOEN_SHIFT (8U)
37350/*! ATOEN - Analog Test Enable (ATOEN)
37351 */
37352#define DDRPHY_DX8SL4PLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL4PLLCR0_ATOEN_MASK)
37353#define DDRPHY_DX8SL4PLLCR0_RESERVED_11_9_MASK (0xE00U)
37354#define DDRPHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT (9U)
37355/*! RESERVED_11_9 - Reserved. Return zeroes on reads.
37356 */
37357#define DDRPHY_DX8SL4PLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL4PLLCR0_RESERVED_11_9_MASK)
37358#define DDRPHY_DX8SL4PLLCR0_GSHIFT_MASK (0x1000U)
37359#define DDRPHY_DX8SL4PLLCR0_GSHIFT_SHIFT (12U)
37360/*! GSHIFT - Gear Shift
37361 */
37362#define DDRPHY_DX8SL4PLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL4PLLCR0_GSHIFT_MASK)
37363#define DDRPHY_DX8SL4PLLCR0_CPIC_MASK (0x1E000U)
37364#define DDRPHY_DX8SL4PLLCR0_CPIC_SHIFT (13U)
37365/*! CPIC - Charge Pump Integrating Current Control
37366 */
37367#define DDRPHY_DX8SL4PLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL4PLLCR0_CPIC_MASK)
37368#define DDRPHY_DX8SL4PLLCR0_CPPC_MASK (0x7E0000U)
37369#define DDRPHY_DX8SL4PLLCR0_CPPC_SHIFT (17U)
37370/*! CPPC - Charge Pump Proportional Current Control
37371 */
37372#define DDRPHY_DX8SL4PLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL4PLLCR0_CPPC_MASK)
37373#define DDRPHY_DX8SL4PLLCR0_RLOCKM_MASK (0x800000U)
37374#define DDRPHY_DX8SL4PLLCR0_RLOCKM_SHIFT (23U)
37375/*! RLOCKM - Relock Mode
37376 */
37377#define DDRPHY_DX8SL4PLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL4PLLCR0_RLOCKM_MASK)
37378#define DDRPHY_DX8SL4PLLCR0_FRQSEL_MASK (0xF000000U)
37379#define DDRPHY_DX8SL4PLLCR0_FRQSEL_SHIFT (24U)
37380/*! FRQSEL - PLL Frequency Select
37381 */
37382#define DDRPHY_DX8SL4PLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL4PLLCR0_FRQSEL_MASK)
37383#define DDRPHY_DX8SL4PLLCR0_RSTOPM_MASK (0x10000000U)
37384#define DDRPHY_DX8SL4PLLCR0_RSTOPM_SHIFT (28U)
37385/*! RSTOPM - Reference Stop Mode
37386 */
37387#define DDRPHY_DX8SL4PLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL4PLLCR0_RSTOPM_MASK)
37388#define DDRPHY_DX8SL4PLLCR0_PLLPD_MASK (0x20000000U)
37389#define DDRPHY_DX8SL4PLLCR0_PLLPD_SHIFT (29U)
37390/*! PLLPD - PLL Power Down
37391 */
37392#define DDRPHY_DX8SL4PLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL4PLLCR0_PLLPD_MASK)
37393#define DDRPHY_DX8SL4PLLCR0_PLLRST_MASK (0x40000000U)
37394#define DDRPHY_DX8SL4PLLCR0_PLLRST_SHIFT (30U)
37395/*! PLLRST - PLL Reset
37396 */
37397#define DDRPHY_DX8SL4PLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL4PLLCR0_PLLRST_MASK)
37398#define DDRPHY_DX8SL4PLLCR0_PLLBYP_MASK (0x80000000U)
37399#define DDRPHY_DX8SL4PLLCR0_PLLBYP_SHIFT (31U)
37400/*! PLLBYP - PLL Bypass
37401 */
37402#define DDRPHY_DX8SL4PLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL4PLLCR0_PLLBYP_MASK)
37403/*! @} */
37404
37405/*! @name DX8SL4PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */
37406/*! @{ */
37407#define DDRPHY_DX8SL4PLLCR1_LOCKDS_MASK (0x1U)
37408#define DDRPHY_DX8SL4PLLCR1_LOCKDS_SHIFT (0U)
37409/*! LOCKDS - Lock Detector Select
37410 */
37411#define DDRPHY_DX8SL4PLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL4PLLCR1_LOCKDS_MASK)
37412#define DDRPHY_DX8SL4PLLCR1_LOCKCS_MASK (0x2U)
37413#define DDRPHY_DX8SL4PLLCR1_LOCKCS_SHIFT (1U)
37414/*! LOCKCS - Lock Detector Counter Select
37415 */
37416#define DDRPHY_DX8SL4PLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL4PLLCR1_LOCKCS_MASK)
37417#define DDRPHY_DX8SL4PLLCR1_LOCKPS_MASK (0x4U)
37418#define DDRPHY_DX8SL4PLLCR1_LOCKPS_SHIFT (2U)
37419/*! LOCKPS - Lock Detector Phase Select
37420 */
37421#define DDRPHY_DX8SL4PLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL4PLLCR1_LOCKPS_MASK)
37422#define DDRPHY_DX8SL4PLLCR1_BYPVDD_MASK (0x8U)
37423#define DDRPHY_DX8SL4PLLCR1_BYPVDD_SHIFT (3U)
37424/*! BYPVDD - PLL VDD voltage level control
37425 */
37426#define DDRPHY_DX8SL4PLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL4PLLCR1_BYPVDD_MASK)
37427#define DDRPHY_DX8SL4PLLCR1_BYPVREGDIG_MASK (0x10U)
37428#define DDRPHY_DX8SL4PLLCR1_BYPVREGDIG_SHIFT (4U)
37429/*! BYPVREGDIG - Bypass PLL vreg_dig
37430 */
37431#define DDRPHY_DX8SL4PLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL4PLLCR1_BYPVREGDIG_MASK)
37432#define DDRPHY_DX8SL4PLLCR1_BYPVREGCP_MASK (0x20U)
37433#define DDRPHY_DX8SL4PLLCR1_BYPVREGCP_SHIFT (5U)
37434/*! BYPVREGCP - Bypass PLL vreg_cp
37435 */
37436#define DDRPHY_DX8SL4PLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL4PLLCR1_BYPVREGCP_MASK)
37437#define DDRPHY_DX8SL4PLLCR1_PLLPROG_MASK (0x3FFFC0U)
37438#define DDRPHY_DX8SL4PLLCR1_PLLPROG_SHIFT (6U)
37439/*! PLLPROG - Connects to the PLL PLL_PROG bus.
37440 */
37441#define DDRPHY_DX8SL4PLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL4PLLCR1_PLLPROG_MASK)
37442#define DDRPHY_DX8SL4PLLCR1_RESERVED_31_22_MASK (0xFFC00000U)
37443#define DDRPHY_DX8SL4PLLCR1_RESERVED_31_22_SHIFT (22U)
37444/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
37445 */
37446#define DDRPHY_DX8SL4PLLCR1_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL4PLLCR1_RESERVED_31_22_MASK)
37447/*! @} */
37448
37449/*! @name DX8SL4PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */
37450/*! @{ */
37451#define DDRPHY_DX8SL4PLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU)
37452#define DDRPHY_DX8SL4PLLCR2_PLLCTRL_31_0_SHIFT (0U)
37453/*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
37454 */
37455#define DDRPHY_DX8SL4PLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL4PLLCR2_PLLCTRL_31_0_MASK)
37456/*! @} */
37457
37458/*! @name DX8SL4PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */
37459/*! @{ */
37460#define DDRPHY_DX8SL4PLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU)
37461#define DDRPHY_DX8SL4PLLCR3_PLLCTRL_63_32_SHIFT (0U)
37462/*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
37463 */
37464#define DDRPHY_DX8SL4PLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL4PLLCR3_PLLCTRL_63_32_MASK)
37465/*! @} */
37466
37467/*! @name DX8SL4PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */
37468/*! @{ */
37469#define DDRPHY_DX8SL4PLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU)
37470#define DDRPHY_DX8SL4PLLCR4_PLLCTRL_95_64_SHIFT (0U)
37471/*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
37472 */
37473#define DDRPHY_DX8SL4PLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL4PLLCR4_PLLCTRL_95_64_MASK)
37474/*! @} */
37475
37476/*! @name DX8SL4PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */
37477/*! @{ */
37478#define DDRPHY_DX8SL4PLLCR5_PLLCTRL_103_96_MASK (0xFFU)
37479#define DDRPHY_DX8SL4PLLCR5_PLLCTRL_103_96_SHIFT (0U)
37480/*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
37481 */
37482#define DDRPHY_DX8SL4PLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL4PLLCR5_PLLCTRL_103_96_MASK)
37483#define DDRPHY_DX8SL4PLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U)
37484#define DDRPHY_DX8SL4PLLCR5_RESERVED_31_8_SHIFT (8U)
37485/*! RESERVED_31_8 - Reserved. Return zeroes on reads.
37486 */
37487#define DDRPHY_DX8SL4PLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL4PLLCR5_RESERVED_31_8_MASK)
37488/*! @} */
37489
37490/*! @name DX8SL4DQSCTL - DATX8 0-1 DQS Control Register */
37491/*! @{ */
37492#define DDRPHY_DX8SL4DQSCTL_DQSRES_MASK (0xFU)
37493#define DDRPHY_DX8SL4DQSCTL_DQSRES_SHIFT (0U)
37494/*! DQSRES - DQS Resistor
37495 */
37496#define DDRPHY_DX8SL4DQSCTL_DQSRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL4DQSCTL_DQSRES_MASK)
37497#define DDRPHY_DX8SL4DQSCTL_DQSNRES_MASK (0xF0U)
37498#define DDRPHY_DX8SL4DQSCTL_DQSNRES_SHIFT (4U)
37499/*! DQSNRES - DQS_N Resistor
37500 */
37501#define DDRPHY_DX8SL4DQSCTL_DQSNRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL4DQSCTL_DQSNRES_MASK)
37502#define DDRPHY_DX8SL4DQSCTL_DXSR_MASK (0x300U)
37503#define DDRPHY_DX8SL4DQSCTL_DXSR_SHIFT (8U)
37504/*! DXSR - Data Slew Rate
37505 */
37506#define DDRPHY_DX8SL4DQSCTL_DXSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL4DQSCTL_DXSR_MASK)
37507#define DDRPHY_DX8SL4DQSCTL_RESERVED_12_10_MASK (0x1C00U)
37508#define DDRPHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT (10U)
37509/*! RESERVED_12_10 - Reserved. Return zeroes on reads.
37510 */
37511#define DDRPHY_DX8SL4DQSCTL_RESERVED_12_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL4DQSCTL_RESERVED_12_10_MASK)
37512#define DDRPHY_DX8SL4DQSCTL_UDQIOM_MASK (0x2000U)
37513#define DDRPHY_DX8SL4DQSCTL_UDQIOM_SHIFT (13U)
37514/*! UDQIOM - Unused DQ I/O Mode
37515 */
37516#define DDRPHY_DX8SL4DQSCTL_UDQIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL4DQSCTL_UDQIOM_MASK)
37517#define DDRPHY_DX8SL4DQSCTL_QSCNTEN_MASK (0x4000U)
37518#define DDRPHY_DX8SL4DQSCTL_QSCNTEN_SHIFT (14U)
37519/*! QSCNTEN - QS Counter Enable
37520 */
37521#define DDRPHY_DX8SL4DQSCTL_QSCNTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL4DQSCTL_QSCNTEN_MASK)
37522#define DDRPHY_DX8SL4DQSCTL_RESERVED_16_15_MASK (0x18000U)
37523#define DDRPHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT (15U)
37524/*! RESERVED_16_15 - Reserved. Return zeroes on reads.
37525 */
37526#define DDRPHY_DX8SL4DQSCTL_RESERVED_16_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL4DQSCTL_RESERVED_16_15_MASK)
37527#define DDRPHY_DX8SL4DQSCTL_LPIOPD_MASK (0x20000U)
37528#define DDRPHY_DX8SL4DQSCTL_LPIOPD_SHIFT (17U)
37529/*! LPIOPD - Low Power I/O Power Down
37530 */
37531#define DDRPHY_DX8SL4DQSCTL_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL4DQSCTL_LPIOPD_MASK)
37532#define DDRPHY_DX8SL4DQSCTL_LPPLLPD_MASK (0x40000U)
37533#define DDRPHY_DX8SL4DQSCTL_LPPLLPD_SHIFT (18U)
37534/*! LPPLLPD - Low Power PLL Power Down
37535 */
37536#define DDRPHY_DX8SL4DQSCTL_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL4DQSCTL_LPPLLPD_MASK)
37537#define DDRPHY_DX8SL4DQSCTL_DQSGX_MASK (0x180000U)
37538#define DDRPHY_DX8SL4DQSCTL_DQSGX_SHIFT (19U)
37539/*! DQSGX - DQS Gate Extension
37540 */
37541#define DDRPHY_DX8SL4DQSCTL_DQSGX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL4DQSCTL_DQSGX_MASK)
37542#define DDRPHY_DX8SL4DQSCTL_WRRMODE_MASK (0x200000U)
37543#define DDRPHY_DX8SL4DQSCTL_WRRMODE_SHIFT (21U)
37544/*! WRRMODE - Write Path Rise-to-Rise Mode
37545 */
37546#define DDRPHY_DX8SL4DQSCTL_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL4DQSCTL_WRRMODE_MASK)
37547#define DDRPHY_DX8SL4DQSCTL_RESERVED_23_22_MASK (0xC00000U)
37548#define DDRPHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT (22U)
37549/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
37550 */
37551#define DDRPHY_DX8SL4DQSCTL_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL4DQSCTL_RESERVED_23_22_MASK)
37552#define DDRPHY_DX8SL4DQSCTL_RRRMODE_MASK (0x1000000U)
37553#define DDRPHY_DX8SL4DQSCTL_RRRMODE_SHIFT (24U)
37554/*! RRRMODE - Read Path Rise-to-Rise Mode
37555 */
37556#define DDRPHY_DX8SL4DQSCTL_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL4DQSCTL_RRRMODE_MASK)
37557#define DDRPHY_DX8SL4DQSCTL_RESERVED_31_25_MASK (0xFE000000U)
37558#define DDRPHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT (25U)
37559/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
37560 */
37561#define DDRPHY_DX8SL4DQSCTL_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL4DQSCTL_RESERVED_31_25_MASK)
37562/*! @} */
37563
37564/*! @name DX8SL4TRNCTL - DATX8 0-1 Training Control Register */
37565/*! @{ */
37566#define DDRPHY_DX8SL4TRNCTL_RESERVED_31_0_MASK (0xFFFFFFFFU)
37567#define DDRPHY_DX8SL4TRNCTL_RESERVED_31_0_SHIFT (0U)
37568/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
37569 */
37570#define DDRPHY_DX8SL4TRNCTL_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL4TRNCTL_RESERVED_31_0_MASK)
37571/*! @} */
37572
37573/*! @name DX8SL4DDLCTL - DATX8 0-1 DDL Control Register */
37574/*! @{ */
37575#define DDRPHY_DX8SL4DDLCTL_DDLBYPMODE_MASK (0x3U)
37576#define DDRPHY_DX8SL4DDLCTL_DDLBYPMODE_SHIFT (0U)
37577/*! DDLBYPMODE - Controls DDL Bypass Mode
37578 */
37579#define DDRPHY_DX8SL4DDLCTL_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL4DDLCTL_DDLBYPMODE_MASK)
37580#define DDRPHY_DX8SL4DDLCTL_DXDDLBYP_MASK (0x3FFFCU)
37581#define DDRPHY_DX8SL4DDLCTL_DXDDLBYP_SHIFT (2U)
37582/*! DXDDLBYP - DATX8 DDL Bypass
37583 */
37584#define DDRPHY_DX8SL4DDLCTL_DXDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL4DDLCTL_DXDDLBYP_MASK)
37585#define DDRPHY_DX8SL4DDLCTL_DXDDLLD_MASK (0x7C0000U)
37586#define DDRPHY_DX8SL4DDLCTL_DXDDLLD_SHIFT (18U)
37587/*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load
37588 */
37589#define DDRPHY_DX8SL4DDLCTL_DXDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL4DDLCTL_DXDDLLD_MASK)
37590#define DDRPHY_DX8SL4DDLCTL_RESERVED_24_23_MASK (0x1800000U)
37591#define DDRPHY_DX8SL4DDLCTL_RESERVED_24_23_SHIFT (23U)
37592/*! RESERVED_24_23 - Reserved. Return zeroes on reads.
37593 */
37594#define DDRPHY_DX8SL4DDLCTL_RESERVED_24_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL4DDLCTL_RESERVED_24_23_MASK)
37595#define DDRPHY_DX8SL4DDLCTL_DXDDLLDT_MASK (0x2000000U)
37596#define DDRPHY_DX8SL4DDLCTL_DXDDLLDT_SHIFT (25U)
37597/*! DXDDLLDT - DX DDL Load Type
37598 */
37599#define DDRPHY_DX8SL4DDLCTL_DXDDLLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL4DDLCTL_DXDDLLDT_MASK)
37600#define DDRPHY_DX8SL4DDLCTL_DLYLDTM_MASK (0x4000000U)
37601#define DDRPHY_DX8SL4DDLCTL_DLYLDTM_SHIFT (26U)
37602/*! DLYLDTM - Delay Load Timing
37603 */
37604#define DDRPHY_DX8SL4DDLCTL_DLYLDTM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL4DDLCTL_DLYLDTM_MASK)
37605#define DDRPHY_DX8SL4DDLCTL_RESERVED_31_27_MASK (0xF8000000U)
37606#define DDRPHY_DX8SL4DDLCTL_RESERVED_31_27_SHIFT (27U)
37607/*! RESERVED_31_27 - Reserved. Return zeroes on reads.
37608 */
37609#define DDRPHY_DX8SL4DDLCTL_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL4DDLCTL_RESERVED_31_27_MASK)
37610/*! @} */
37611
37612/*! @name DX8SL4DXCTL1 - DATX8 0-1 DX Control Register 1 */
37613/*! @{ */
37614#define DDRPHY_DX8SL4DXCTL1_RESERVED_15_0_MASK (0xFFFFU)
37615#define DDRPHY_DX8SL4DXCTL1_RESERVED_15_0_SHIFT (0U)
37616/*! RESERVED_15_0 - Reserved. Return zeroes on reads.
37617 */
37618#define DDRPHY_DX8SL4DXCTL1_RESERVED_15_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL4DXCTL1_RESERVED_15_0_MASK)
37619#define DDRPHY_DX8SL4DXCTL1_DXTMODE_MASK (0x10000U)
37620#define DDRPHY_DX8SL4DXCTL1_DXTMODE_SHIFT (16U)
37621/*! DXTMODE - DATX8 Test Mode
37622 */
37623#define DDRPHY_DX8SL4DXCTL1_DXTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXTMODE_MASK)
37624#define DDRPHY_DX8SL4DXCTL1_DXGDBYP_MASK (0x20000U)
37625#define DDRPHY_DX8SL4DXCTL1_DXGDBYP_SHIFT (17U)
37626/*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode
37627 */
37628#define DDRPHY_DX8SL4DXCTL1_DXGDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXGDBYP_MASK)
37629#define DDRPHY_DX8SL4DXCTL1_DXQSDBYP_MASK (0x40000U)
37630#define DDRPHY_DX8SL4DXCTL1_DXQSDBYP_SHIFT (18U)
37631/*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode
37632 */
37633#define DDRPHY_DX8SL4DXCTL1_DXQSDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXQSDBYP_MASK)
37634#define DDRPHY_DX8SL4DXCTL1_DXGSMD_MASK (0x80000U)
37635#define DDRPHY_DX8SL4DXCTL1_DXGSMD_SHIFT (19U)
37636/*! DXGSMD - Read DQS Gating Status Mode
37637 */
37638#define DDRPHY_DX8SL4DXCTL1_DXGSMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXGSMD_MASK)
37639#define DDRPHY_DX8SL4DXCTL1_DXDTOSEL_MASK (0x300000U)
37640#define DDRPHY_DX8SL4DXCTL1_DXDTOSEL_SHIFT (20U)
37641/*! DXDTOSEL - DATX8 Digital Test Output Select
37642 */
37643#define DDRPHY_DX8SL4DXCTL1_DXDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXDTOSEL_MASK)
37644#define DDRPHY_DX8SL4DXCTL1_RESERVED_22_MASK (0x400000U)
37645#define DDRPHY_DX8SL4DXCTL1_RESERVED_22_SHIFT (22U)
37646/*! RESERVED_22 - Reserved. Return zeroes on reads.
37647 */
37648#define DDRPHY_DX8SL4DXCTL1_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL4DXCTL1_RESERVED_22_MASK)
37649#define DDRPHY_DX8SL4DXCTL1_DXRCLKMD_MASK (0x800000U)
37650#define DDRPHY_DX8SL4DXCTL1_DXRCLKMD_SHIFT (23U)
37651/*! DXRCLKMD - DATX8 Read Clock Mode
37652 */
37653#define DDRPHY_DX8SL4DXCTL1_DXRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXRCLKMD_MASK)
37654#define DDRPHY_DX8SL4DXCTL1_DXCALCLK_MASK (0x1000000U)
37655#define DDRPHY_DX8SL4DXCTL1_DXCALCLK_SHIFT (24U)
37656/*! DXCALCLK - DATX Calibration Clock Select
37657 */
37658#define DDRPHY_DX8SL4DXCTL1_DXCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL4DXCTL1_DXCALCLK_MASK)
37659#define DDRPHY_DX8SL4DXCTL1_RESERVED_31_25_MASK (0xFE000000U)
37660#define DDRPHY_DX8SL4DXCTL1_RESERVED_31_25_SHIFT (25U)
37661/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
37662 */
37663#define DDRPHY_DX8SL4DXCTL1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL4DXCTL1_RESERVED_31_25_MASK)
37664/*! @} */
37665
37666/*! @name DX8SL4DXCTL2 - DATX8 0-1 DX Control Register 2 */
37667/*! @{ */
37668#define DDRPHY_DX8SL4DXCTL2_RESERVED_0_MASK (0x1U)
37669#define DDRPHY_DX8SL4DXCTL2_RESERVED_0_SHIFT (0U)
37670/*! RESERVED_0 - Reserved. Return zeroes on reads.
37671 */
37672#define DDRPHY_DX8SL4DXCTL2_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL4DXCTL2_RESERVED_0_MASK)
37673#define DDRPHY_DX8SL4DXCTL2_DQSGLB_MASK (0x6U)
37674#define DDRPHY_DX8SL4DXCTL2_DQSGLB_SHIFT (1U)
37675/*! DQSGLB - Read DQS Gate I/O Loopback
37676 */
37677#define DDRPHY_DX8SL4DXCTL2_DQSGLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL4DXCTL2_DQSGLB_MASK)
37678#define DDRPHY_DX8SL4DXCTL2_DISRST_MASK (0x8U)
37679#define DDRPHY_DX8SL4DXCTL2_DISRST_SHIFT (3U)
37680/*! DISRST - Disables the Read FIFO Reset
37681 */
37682#define DDRPHY_DX8SL4DXCTL2_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL4DXCTL2_DISRST_MASK)
37683#define DDRPHY_DX8SL4DXCTL2_RDMODE_MASK (0x30U)
37684#define DDRPHY_DX8SL4DXCTL2_RDMODE_SHIFT (4U)
37685/*! RDMODE - DATX8 Receive FIFO Read Mode
37686 */
37687#define DDRPHY_DX8SL4DXCTL2_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL4DXCTL2_RDMODE_MASK)
37688#define DDRPHY_DX8SL4DXCTL2_PRFBYP_MASK (0x40U)
37689#define DDRPHY_DX8SL4DXCTL2_PRFBYP_SHIFT (6U)
37690/*! PRFBYP - PUB Read FIFO Bypass
37691 */
37692#define DDRPHY_DX8SL4DXCTL2_PRFBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL4DXCTL2_PRFBYP_MASK)
37693#define DDRPHY_DX8SL4DXCTL2_WDBI_MASK (0x80U)
37694#define DDRPHY_DX8SL4DXCTL2_WDBI_SHIFT (7U)
37695/*! WDBI - Write Data Bus Inversion Enable
37696 */
37697#define DDRPHY_DX8SL4DXCTL2_WDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL4DXCTL2_WDBI_MASK)
37698#define DDRPHY_DX8SL4DXCTL2_RDBI_MASK (0x100U)
37699#define DDRPHY_DX8SL4DXCTL2_RDBI_SHIFT (8U)
37700/*! RDBI - Read Data Bus Inversion Enable
37701 */
37702#define DDRPHY_DX8SL4DXCTL2_RDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL4DXCTL2_RDBI_MASK)
37703#define DDRPHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK (0x1E00U)
37704#define DDRPHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT (9U)
37705/*! LPWAKEUP_THRSH - Low Power Wakeup Threshold
37706 */
37707#define DDRPHY_DX8SL4DXCTL2_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK)
37708#define DDRPHY_DX8SL4DXCTL2_RESERVED_14_13_MASK (0x6000U)
37709#define DDRPHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT (13U)
37710/*! RESERVED_14_13 - Reserved. Return zeroes on reads.
37711 */
37712#define DDRPHY_DX8SL4DXCTL2_RESERVED_14_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL4DXCTL2_RESERVED_14_13_MASK)
37713#define DDRPHY_DX8SL4DXCTL2_IOLB_MASK (0x8000U)
37714#define DDRPHY_DX8SL4DXCTL2_IOLB_SHIFT (15U)
37715/*! IOLB - I/O Loopback Select
37716 */
37717#define DDRPHY_DX8SL4DXCTL2_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL4DXCTL2_IOLB_MASK)
37718#define DDRPHY_DX8SL4DXCTL2_IOAG_MASK (0x10000U)
37719#define DDRPHY_DX8SL4DXCTL2_IOAG_SHIFT (16U)
37720/*! IOAG - I/O Assisted Gate Select
37721 */
37722#define DDRPHY_DX8SL4DXCTL2_IOAG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL4DXCTL2_IOAG_MASK)
37723#define DDRPHY_DX8SL4DXCTL2_RESERVED_17_MASK (0x20000U)
37724#define DDRPHY_DX8SL4DXCTL2_RESERVED_17_SHIFT (17U)
37725/*! RESERVED_17 - Reserved. Return zeroes on reads.
37726 */
37727#define DDRPHY_DX8SL4DXCTL2_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL4DXCTL2_RESERVED_17_MASK)
37728#define DDRPHY_DX8SL4DXCTL2_PREOEX_MASK (0xC0000U)
37729#define DDRPHY_DX8SL4DXCTL2_PREOEX_SHIFT (18U)
37730/*! PREOEX - OE Extension during Pre-amble
37731 */
37732#define DDRPHY_DX8SL4DXCTL2_PREOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL4DXCTL2_PREOEX_MASK)
37733#define DDRPHY_DX8SL4DXCTL2_POSOEX_MASK (0x700000U)
37734#define DDRPHY_DX8SL4DXCTL2_POSOEX_SHIFT (20U)
37735/*! POSOEX - OX Extension during Post-amble
37736 */
37737#define DDRPHY_DX8SL4DXCTL2_POSOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL4DXCTL2_POSOEX_MASK)
37738#define DDRPHY_DX8SL4DXCTL2_CRDEN_MASK (0x800000U)
37739#define DDRPHY_DX8SL4DXCTL2_CRDEN_SHIFT (23U)
37740/*! CRDEN - Configurable Read Data Enable
37741 */
37742#define DDRPHY_DX8SL4DXCTL2_CRDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL4DXCTL2_CRDEN_MASK)
37743#define DDRPHY_DX8SL4DXCTL2_RESERVED_31_24_MASK (0xFF000000U)
37744#define DDRPHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT (24U)
37745/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
37746 */
37747#define DDRPHY_DX8SL4DXCTL2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL4DXCTL2_RESERVED_31_24_MASK)
37748/*! @} */
37749
37750/*! @name DX8SL4IOCR - DATX8 0-1 I/O Configuration Register */
37751/*! @{ */
37752#define DDRPHY_DX8SL4IOCR_DXRXM_MASK (0x7FFU)
37753#define DDRPHY_DX8SL4IOCR_DXRXM_SHIFT (0U)
37754/*! DXRXM - DX IO Receiver Mode
37755 */
37756#define DDRPHY_DX8SL4IOCR_DXRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL4IOCR_DXRXM_MASK)
37757#define DDRPHY_DX8SL4IOCR_DXTXM_MASK (0x3FF800U)
37758#define DDRPHY_DX8SL4IOCR_DXTXM_SHIFT (11U)
37759/*! DXTXM - DX IO Transmitter Mode
37760 */
37761#define DDRPHY_DX8SL4IOCR_DXTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL4IOCR_DXTXM_MASK)
37762#define DDRPHY_DX8SL4IOCR_DXIOM_MASK (0x1C00000U)
37763#define DDRPHY_DX8SL4IOCR_DXIOM_SHIFT (22U)
37764/*! DXIOM - DX IO Mode
37765 */
37766#define DDRPHY_DX8SL4IOCR_DXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL4IOCR_DXIOM_MASK)
37767#define DDRPHY_DX8SL4IOCR_DXVREFIOM_MASK (0xE000000U)
37768#define DDRPHY_DX8SL4IOCR_DXVREFIOM_SHIFT (25U)
37769/*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
37770 */
37771#define DDRPHY_DX8SL4IOCR_DXVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL4IOCR_DXVREFIOM_MASK)
37772#define DDRPHY_DX8SL4IOCR_DXDACRANGE_MASK (0x70000000U)
37773#define DDRPHY_DX8SL4IOCR_DXDACRANGE_SHIFT (28U)
37774/*! DXDACRANGE - PVREF_DAC REFSEL range select
37775 */
37776#define DDRPHY_DX8SL4IOCR_DXDACRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL4IOCR_DXDACRANGE_MASK)
37777#define DDRPHY_DX8SL4IOCR_RESERVED_31_MASK (0x80000000U)
37778#define DDRPHY_DX8SL4IOCR_RESERVED_31_SHIFT (31U)
37779/*! RESERVED_31 - Reserved. Return zeroes on reads.
37780 */
37781#define DDRPHY_DX8SL4IOCR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL4IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL4IOCR_RESERVED_31_MASK)
37782/*! @} */
37783
37784/*! @name DX4SL4IOCR - DATX4 Slice 0-1 I/O Configuration Register */
37785/*! @{ */
37786#define DDRPHY_DX4SL4IOCR_RESERVED_31_0_MASK (0xFFFFFFFFU)
37787#define DDRPHY_DX4SL4IOCR_RESERVED_31_0_SHIFT (0U)
37788/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
37789 */
37790#define DDRPHY_DX4SL4IOCR_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL4IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL4IOCR_RESERVED_31_0_MASK)
37791/*! @} */
37792
37793/*! @name DX8SL5OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */
37794/*! @{ */
37795#define DDRPHY_DX8SL5OSC_OSCEN_MASK (0x1U)
37796#define DDRPHY_DX8SL5OSC_OSCEN_SHIFT (0U)
37797/*! OSCEN - Oscillator Enable
37798 */
37799#define DDRPHY_DX8SL5OSC_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL5OSC_OSCEN_MASK)
37800#define DDRPHY_DX8SL5OSC_OSCDIV_MASK (0x1EU)
37801#define DDRPHY_DX8SL5OSC_OSCDIV_SHIFT (1U)
37802/*! OSCDIV - Oscillator Mode Division
37803 */
37804#define DDRPHY_DX8SL5OSC_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL5OSC_OSCDIV_MASK)
37805#define DDRPHY_DX8SL5OSC_OSCWDL_MASK (0x60U)
37806#define DDRPHY_DX8SL5OSC_OSCWDL_SHIFT (5U)
37807/*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select
37808 */
37809#define DDRPHY_DX8SL5OSC_OSCWDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL5OSC_OSCWDL_MASK)
37810#define DDRPHY_DX8SL5OSC_RESERVED_8_7_MASK (0x180U)
37811#define DDRPHY_DX8SL5OSC_RESERVED_8_7_SHIFT (7U)
37812/*! RESERVED_8_7 - Reserved. Caution, do not write to this register field.
37813 */
37814#define DDRPHY_DX8SL5OSC_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL5OSC_RESERVED_8_7_MASK)
37815#define DDRPHY_DX8SL5OSC_OSCWDDL_MASK (0x600U)
37816#define DDRPHY_DX8SL5OSC_OSCWDDL_SHIFT (9U)
37817/*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select
37818 */
37819#define DDRPHY_DX8SL5OSC_OSCWDDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL5OSC_OSCWDDL_MASK)
37820#define DDRPHY_DX8SL5OSC_RESERVED_12_11_MASK (0x1800U)
37821#define DDRPHY_DX8SL5OSC_RESERVED_12_11_SHIFT (11U)
37822/*! RESERVED_12_11 - Reserved. Caution, do not write to this register field.
37823 */
37824#define DDRPHY_DX8SL5OSC_RESERVED_12_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL5OSC_RESERVED_12_11_MASK)
37825#define DDRPHY_DX8SL5OSC_DLTMODE_MASK (0x2000U)
37826#define DDRPHY_DX8SL5OSC_DLTMODE_SHIFT (13U)
37827/*! DLTMODE - Delay Line Test Mode
37828 */
37829#define DDRPHY_DX8SL5OSC_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL5OSC_DLTMODE_MASK)
37830#define DDRPHY_DX8SL5OSC_DLTST_MASK (0x4000U)
37831#define DDRPHY_DX8SL5OSC_DLTST_SHIFT (14U)
37832/*! DLTST - Delay Line Test Start
37833 */
37834#define DDRPHY_DX8SL5OSC_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_DLTST_SHIFT)) & DDRPHY_DX8SL5OSC_DLTST_MASK)
37835#define DDRPHY_DX8SL5OSC_PHYFRST_MASK (0x8000U)
37836#define DDRPHY_DX8SL5OSC_PHYFRST_SHIFT (15U)
37837/*! PHYFRST - PHY FIFO Reset
37838 */
37839#define DDRPHY_DX8SL5OSC_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL5OSC_PHYFRST_MASK)
37840#define DDRPHY_DX8SL5OSC_PHYHRST_MASK (0x10000U)
37841#define DDRPHY_DX8SL5OSC_PHYHRST_SHIFT (16U)
37842/*! PHYHRST - PHY High-Speed Reset
37843 */
37844#define DDRPHY_DX8SL5OSC_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL5OSC_PHYHRST_MASK)
37845#define DDRPHY_DX8SL5OSC_LBDQSS_MASK (0x20000U)
37846#define DDRPHY_DX8SL5OSC_LBDQSS_SHIFT (17U)
37847/*! LBDQSS - Loopback DQS Shift
37848 */
37849#define DDRPHY_DX8SL5OSC_LBDQSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL5OSC_LBDQSS_MASK)
37850#define DDRPHY_DX8SL5OSC_LBGDQS_MASK (0xC0000U)
37851#define DDRPHY_DX8SL5OSC_LBGDQS_SHIFT (18U)
37852/*! LBGDQS - Loopback DQS Gating
37853 */
37854#define DDRPHY_DX8SL5OSC_LBGDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL5OSC_LBGDQS_MASK)
37855#define DDRPHY_DX8SL5OSC_LBGSDQS_MASK (0x100000U)
37856#define DDRPHY_DX8SL5OSC_LBGSDQS_SHIFT (20U)
37857/*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
37858 */
37859#define DDRPHY_DX8SL5OSC_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL5OSC_LBGSDQS_MASK)
37860#define DDRPHY_DX8SL5OSC_LBMODE_MASK (0x200000U)
37861#define DDRPHY_DX8SL5OSC_LBMODE_SHIFT (21U)
37862/*! LBMODE - Loopback Mode
37863 */
37864#define DDRPHY_DX8SL5OSC_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL5OSC_LBMODE_MASK)
37865#define DDRPHY_DX8SL5OSC_CLKLEVEL_MASK (0xC00000U)
37866#define DDRPHY_DX8SL5OSC_CLKLEVEL_SHIFT (22U)
37867/*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled.
37868 */
37869#define DDRPHY_DX8SL5OSC_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL5OSC_CLKLEVEL_MASK)
37870#define DDRPHY_DX8SL5OSC_GATEDXCTLCLK_MASK (0x3000000U)
37871#define DDRPHY_DX8SL5OSC_GATEDXCTLCLK_SHIFT (24U)
37872/*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk
37873 */
37874#define DDRPHY_DX8SL5OSC_GATEDXCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL5OSC_GATEDXCTLCLK_MASK)
37875#define DDRPHY_DX8SL5OSC_GATEDXDDRCLK_MASK (0xC000000U)
37876#define DDRPHY_DX8SL5OSC_GATEDXDDRCLK_SHIFT (26U)
37877/*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk
37878 */
37879#define DDRPHY_DX8SL5OSC_GATEDXDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL5OSC_GATEDXDDRCLK_MASK)
37880#define DDRPHY_DX8SL5OSC_GATEDXRDCLK_MASK (0x30000000U)
37881#define DDRPHY_DX8SL5OSC_GATEDXRDCLK_SHIFT (28U)
37882/*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk
37883 */
37884#define DDRPHY_DX8SL5OSC_GATEDXRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL5OSC_GATEDXRDCLK_MASK)
37885#define DDRPHY_DX8SL5OSC_RESERVED_31_30_MASK (0xC0000000U)
37886#define DDRPHY_DX8SL5OSC_RESERVED_31_30_SHIFT (30U)
37887/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
37888 */
37889#define DDRPHY_DX8SL5OSC_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL5OSC_RESERVED_31_30_MASK)
37890/*! @} */
37891
37892/*! @name DX8SL5PLLCR0 - DAXT8 0-1 PLL Control Register 0 */
37893/*! @{ */
37894#define DDRPHY_DX8SL5PLLCR0_DTC_MASK (0xFU)
37895#define DDRPHY_DX8SL5PLLCR0_DTC_SHIFT (0U)
37896/*! DTC - Digital Test Control
37897 */
37898#define DDRPHY_DX8SL5PLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL5PLLCR0_DTC_MASK)
37899#define DDRPHY_DX8SL5PLLCR0_ATC_MASK (0xF0U)
37900#define DDRPHY_DX8SL5PLLCR0_ATC_SHIFT (4U)
37901/*! ATC - Analog Test Control
37902 */
37903#define DDRPHY_DX8SL5PLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL5PLLCR0_ATC_MASK)
37904#define DDRPHY_DX8SL5PLLCR0_ATOEN_MASK (0x100U)
37905#define DDRPHY_DX8SL5PLLCR0_ATOEN_SHIFT (8U)
37906/*! ATOEN - Analog Test Enable (ATOEN)
37907 */
37908#define DDRPHY_DX8SL5PLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL5PLLCR0_ATOEN_MASK)
37909#define DDRPHY_DX8SL5PLLCR0_RESERVED_11_9_MASK (0xE00U)
37910#define DDRPHY_DX8SL5PLLCR0_RESERVED_11_9_SHIFT (9U)
37911/*! RESERVED_11_9 - Reserved. Return zeroes on reads.
37912 */
37913#define DDRPHY_DX8SL5PLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL5PLLCR0_RESERVED_11_9_MASK)
37914#define DDRPHY_DX8SL5PLLCR0_GSHIFT_MASK (0x1000U)
37915#define DDRPHY_DX8SL5PLLCR0_GSHIFT_SHIFT (12U)
37916/*! GSHIFT - Gear Shift
37917 */
37918#define DDRPHY_DX8SL5PLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL5PLLCR0_GSHIFT_MASK)
37919#define DDRPHY_DX8SL5PLLCR0_CPIC_MASK (0x1E000U)
37920#define DDRPHY_DX8SL5PLLCR0_CPIC_SHIFT (13U)
37921/*! CPIC - Charge Pump Integrating Current Control
37922 */
37923#define DDRPHY_DX8SL5PLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL5PLLCR0_CPIC_MASK)
37924#define DDRPHY_DX8SL5PLLCR0_CPPC_MASK (0x7E0000U)
37925#define DDRPHY_DX8SL5PLLCR0_CPPC_SHIFT (17U)
37926/*! CPPC - Charge Pump Proportional Current Control
37927 */
37928#define DDRPHY_DX8SL5PLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL5PLLCR0_CPPC_MASK)
37929#define DDRPHY_DX8SL5PLLCR0_RLOCKM_MASK (0x800000U)
37930#define DDRPHY_DX8SL5PLLCR0_RLOCKM_SHIFT (23U)
37931/*! RLOCKM - Relock Mode
37932 */
37933#define DDRPHY_DX8SL5PLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL5PLLCR0_RLOCKM_MASK)
37934#define DDRPHY_DX8SL5PLLCR0_FRQSEL_MASK (0xF000000U)
37935#define DDRPHY_DX8SL5PLLCR0_FRQSEL_SHIFT (24U)
37936/*! FRQSEL - PLL Frequency Select
37937 */
37938#define DDRPHY_DX8SL5PLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL5PLLCR0_FRQSEL_MASK)
37939#define DDRPHY_DX8SL5PLLCR0_RSTOPM_MASK (0x10000000U)
37940#define DDRPHY_DX8SL5PLLCR0_RSTOPM_SHIFT (28U)
37941/*! RSTOPM - Reference Stop Mode
37942 */
37943#define DDRPHY_DX8SL5PLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL5PLLCR0_RSTOPM_MASK)
37944#define DDRPHY_DX8SL5PLLCR0_PLLPD_MASK (0x20000000U)
37945#define DDRPHY_DX8SL5PLLCR0_PLLPD_SHIFT (29U)
37946/*! PLLPD - PLL Power Down
37947 */
37948#define DDRPHY_DX8SL5PLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL5PLLCR0_PLLPD_MASK)
37949#define DDRPHY_DX8SL5PLLCR0_PLLRST_MASK (0x40000000U)
37950#define DDRPHY_DX8SL5PLLCR0_PLLRST_SHIFT (30U)
37951/*! PLLRST - PLL Reset
37952 */
37953#define DDRPHY_DX8SL5PLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL5PLLCR0_PLLRST_MASK)
37954#define DDRPHY_DX8SL5PLLCR0_PLLBYP_MASK (0x80000000U)
37955#define DDRPHY_DX8SL5PLLCR0_PLLBYP_SHIFT (31U)
37956/*! PLLBYP - PLL Bypass
37957 */
37958#define DDRPHY_DX8SL5PLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL5PLLCR0_PLLBYP_MASK)
37959/*! @} */
37960
37961/*! @name DX8SL5PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */
37962/*! @{ */
37963#define DDRPHY_DX8SL5PLLCR1_LOCKDS_MASK (0x1U)
37964#define DDRPHY_DX8SL5PLLCR1_LOCKDS_SHIFT (0U)
37965/*! LOCKDS - Lock Detector Select
37966 */
37967#define DDRPHY_DX8SL5PLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL5PLLCR1_LOCKDS_MASK)
37968#define DDRPHY_DX8SL5PLLCR1_LOCKCS_MASK (0x2U)
37969#define DDRPHY_DX8SL5PLLCR1_LOCKCS_SHIFT (1U)
37970/*! LOCKCS - Lock Detector Counter Select
37971 */
37972#define DDRPHY_DX8SL5PLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL5PLLCR1_LOCKCS_MASK)
37973#define DDRPHY_DX8SL5PLLCR1_LOCKPS_MASK (0x4U)
37974#define DDRPHY_DX8SL5PLLCR1_LOCKPS_SHIFT (2U)
37975/*! LOCKPS - Lock Detector Phase Select
37976 */
37977#define DDRPHY_DX8SL5PLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL5PLLCR1_LOCKPS_MASK)
37978#define DDRPHY_DX8SL5PLLCR1_BYPVDD_MASK (0x8U)
37979#define DDRPHY_DX8SL5PLLCR1_BYPVDD_SHIFT (3U)
37980/*! BYPVDD - PLL VDD voltage level control
37981 */
37982#define DDRPHY_DX8SL5PLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL5PLLCR1_BYPVDD_MASK)
37983#define DDRPHY_DX8SL5PLLCR1_BYPVREGDIG_MASK (0x10U)
37984#define DDRPHY_DX8SL5PLLCR1_BYPVREGDIG_SHIFT (4U)
37985/*! BYPVREGDIG - Bypass PLL vreg_dig
37986 */
37987#define DDRPHY_DX8SL5PLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL5PLLCR1_BYPVREGDIG_MASK)
37988#define DDRPHY_DX8SL5PLLCR1_BYPVREGCP_MASK (0x20U)
37989#define DDRPHY_DX8SL5PLLCR1_BYPVREGCP_SHIFT (5U)
37990/*! BYPVREGCP - Bypass PLL vreg_cp
37991 */
37992#define DDRPHY_DX8SL5PLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL5PLLCR1_BYPVREGCP_MASK)
37993#define DDRPHY_DX8SL5PLLCR1_PLLPROG_MASK (0x3FFFC0U)
37994#define DDRPHY_DX8SL5PLLCR1_PLLPROG_SHIFT (6U)
37995/*! PLLPROG - Connects to the PLL PLL_PROG bus.
37996 */
37997#define DDRPHY_DX8SL5PLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL5PLLCR1_PLLPROG_MASK)
37998#define DDRPHY_DX8SL5PLLCR1_RESERVED_31_22_MASK (0xFFC00000U)
37999#define DDRPHY_DX8SL5PLLCR1_RESERVED_31_22_SHIFT (22U)
38000/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
38001 */
38002#define DDRPHY_DX8SL5PLLCR1_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL5PLLCR1_RESERVED_31_22_MASK)
38003/*! @} */
38004
38005/*! @name DX8SL5PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */
38006/*! @{ */
38007#define DDRPHY_DX8SL5PLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU)
38008#define DDRPHY_DX8SL5PLLCR2_PLLCTRL_31_0_SHIFT (0U)
38009/*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
38010 */
38011#define DDRPHY_DX8SL5PLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL5PLLCR2_PLLCTRL_31_0_MASK)
38012/*! @} */
38013
38014/*! @name DX8SL5PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */
38015/*! @{ */
38016#define DDRPHY_DX8SL5PLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU)
38017#define DDRPHY_DX8SL5PLLCR3_PLLCTRL_63_32_SHIFT (0U)
38018/*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
38019 */
38020#define DDRPHY_DX8SL5PLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL5PLLCR3_PLLCTRL_63_32_MASK)
38021/*! @} */
38022
38023/*! @name DX8SL5PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */
38024/*! @{ */
38025#define DDRPHY_DX8SL5PLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU)
38026#define DDRPHY_DX8SL5PLLCR4_PLLCTRL_95_64_SHIFT (0U)
38027/*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
38028 */
38029#define DDRPHY_DX8SL5PLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL5PLLCR4_PLLCTRL_95_64_MASK)
38030/*! @} */
38031
38032/*! @name DX8SL5PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */
38033/*! @{ */
38034#define DDRPHY_DX8SL5PLLCR5_PLLCTRL_103_96_MASK (0xFFU)
38035#define DDRPHY_DX8SL5PLLCR5_PLLCTRL_103_96_SHIFT (0U)
38036/*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
38037 */
38038#define DDRPHY_DX8SL5PLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL5PLLCR5_PLLCTRL_103_96_MASK)
38039#define DDRPHY_DX8SL5PLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U)
38040#define DDRPHY_DX8SL5PLLCR5_RESERVED_31_8_SHIFT (8U)
38041/*! RESERVED_31_8 - Reserved. Return zeroes on reads.
38042 */
38043#define DDRPHY_DX8SL5PLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL5PLLCR5_RESERVED_31_8_MASK)
38044/*! @} */
38045
38046/*! @name DX8SL5DQSCTL - DATX8 0-1 DQS Control Register */
38047/*! @{ */
38048#define DDRPHY_DX8SL5DQSCTL_DQSRES_MASK (0xFU)
38049#define DDRPHY_DX8SL5DQSCTL_DQSRES_SHIFT (0U)
38050/*! DQSRES - DQS Resistor
38051 */
38052#define DDRPHY_DX8SL5DQSCTL_DQSRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL5DQSCTL_DQSRES_MASK)
38053#define DDRPHY_DX8SL5DQSCTL_DQSNRES_MASK (0xF0U)
38054#define DDRPHY_DX8SL5DQSCTL_DQSNRES_SHIFT (4U)
38055/*! DQSNRES - DQS_N Resistor
38056 */
38057#define DDRPHY_DX8SL5DQSCTL_DQSNRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL5DQSCTL_DQSNRES_MASK)
38058#define DDRPHY_DX8SL5DQSCTL_DXSR_MASK (0x300U)
38059#define DDRPHY_DX8SL5DQSCTL_DXSR_SHIFT (8U)
38060/*! DXSR - Data Slew Rate
38061 */
38062#define DDRPHY_DX8SL5DQSCTL_DXSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL5DQSCTL_DXSR_MASK)
38063#define DDRPHY_DX8SL5DQSCTL_RESERVED_12_10_MASK (0x1C00U)
38064#define DDRPHY_DX8SL5DQSCTL_RESERVED_12_10_SHIFT (10U)
38065/*! RESERVED_12_10 - Reserved. Return zeroes on reads.
38066 */
38067#define DDRPHY_DX8SL5DQSCTL_RESERVED_12_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL5DQSCTL_RESERVED_12_10_MASK)
38068#define DDRPHY_DX8SL5DQSCTL_UDQIOM_MASK (0x2000U)
38069#define DDRPHY_DX8SL5DQSCTL_UDQIOM_SHIFT (13U)
38070/*! UDQIOM - Unused DQ I/O Mode
38071 */
38072#define DDRPHY_DX8SL5DQSCTL_UDQIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL5DQSCTL_UDQIOM_MASK)
38073#define DDRPHY_DX8SL5DQSCTL_QSCNTEN_MASK (0x4000U)
38074#define DDRPHY_DX8SL5DQSCTL_QSCNTEN_SHIFT (14U)
38075/*! QSCNTEN - QS Counter Enable
38076 */
38077#define DDRPHY_DX8SL5DQSCTL_QSCNTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL5DQSCTL_QSCNTEN_MASK)
38078#define DDRPHY_DX8SL5DQSCTL_RESERVED_16_15_MASK (0x18000U)
38079#define DDRPHY_DX8SL5DQSCTL_RESERVED_16_15_SHIFT (15U)
38080/*! RESERVED_16_15 - Reserved. Return zeroes on reads.
38081 */
38082#define DDRPHY_DX8SL5DQSCTL_RESERVED_16_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL5DQSCTL_RESERVED_16_15_MASK)
38083#define DDRPHY_DX8SL5DQSCTL_LPIOPD_MASK (0x20000U)
38084#define DDRPHY_DX8SL5DQSCTL_LPIOPD_SHIFT (17U)
38085/*! LPIOPD - Low Power I/O Power Down
38086 */
38087#define DDRPHY_DX8SL5DQSCTL_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL5DQSCTL_LPIOPD_MASK)
38088#define DDRPHY_DX8SL5DQSCTL_LPPLLPD_MASK (0x40000U)
38089#define DDRPHY_DX8SL5DQSCTL_LPPLLPD_SHIFT (18U)
38090/*! LPPLLPD - Low Power PLL Power Down
38091 */
38092#define DDRPHY_DX8SL5DQSCTL_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL5DQSCTL_LPPLLPD_MASK)
38093#define DDRPHY_DX8SL5DQSCTL_DQSGX_MASK (0x180000U)
38094#define DDRPHY_DX8SL5DQSCTL_DQSGX_SHIFT (19U)
38095/*! DQSGX - DQS Gate Extension
38096 */
38097#define DDRPHY_DX8SL5DQSCTL_DQSGX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL5DQSCTL_DQSGX_MASK)
38098#define DDRPHY_DX8SL5DQSCTL_WRRMODE_MASK (0x200000U)
38099#define DDRPHY_DX8SL5DQSCTL_WRRMODE_SHIFT (21U)
38100/*! WRRMODE - Write Path Rise-to-Rise Mode
38101 */
38102#define DDRPHY_DX8SL5DQSCTL_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL5DQSCTL_WRRMODE_MASK)
38103#define DDRPHY_DX8SL5DQSCTL_RESERVED_23_22_MASK (0xC00000U)
38104#define DDRPHY_DX8SL5DQSCTL_RESERVED_23_22_SHIFT (22U)
38105/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
38106 */
38107#define DDRPHY_DX8SL5DQSCTL_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL5DQSCTL_RESERVED_23_22_MASK)
38108#define DDRPHY_DX8SL5DQSCTL_RRRMODE_MASK (0x1000000U)
38109#define DDRPHY_DX8SL5DQSCTL_RRRMODE_SHIFT (24U)
38110/*! RRRMODE - Read Path Rise-to-Rise Mode
38111 */
38112#define DDRPHY_DX8SL5DQSCTL_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL5DQSCTL_RRRMODE_MASK)
38113#define DDRPHY_DX8SL5DQSCTL_RESERVED_31_25_MASK (0xFE000000U)
38114#define DDRPHY_DX8SL5DQSCTL_RESERVED_31_25_SHIFT (25U)
38115/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
38116 */
38117#define DDRPHY_DX8SL5DQSCTL_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL5DQSCTL_RESERVED_31_25_MASK)
38118/*! @} */
38119
38120/*! @name DX8SL5TRNCTL - DATX8 0-1 Training Control Register */
38121/*! @{ */
38122#define DDRPHY_DX8SL5TRNCTL_RESERVED_31_0_MASK (0xFFFFFFFFU)
38123#define DDRPHY_DX8SL5TRNCTL_RESERVED_31_0_SHIFT (0U)
38124/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
38125 */
38126#define DDRPHY_DX8SL5TRNCTL_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL5TRNCTL_RESERVED_31_0_MASK)
38127/*! @} */
38128
38129/*! @name DX8SL5DDLCTL - DATX8 0-1 DDL Control Register */
38130/*! @{ */
38131#define DDRPHY_DX8SL5DDLCTL_DDLBYPMODE_MASK (0x3U)
38132#define DDRPHY_DX8SL5DDLCTL_DDLBYPMODE_SHIFT (0U)
38133/*! DDLBYPMODE - Controls DDL Bypass Mode
38134 */
38135#define DDRPHY_DX8SL5DDLCTL_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL5DDLCTL_DDLBYPMODE_MASK)
38136#define DDRPHY_DX8SL5DDLCTL_DXDDLBYP_MASK (0x3FFFCU)
38137#define DDRPHY_DX8SL5DDLCTL_DXDDLBYP_SHIFT (2U)
38138/*! DXDDLBYP - DATX8 DDL Bypass
38139 */
38140#define DDRPHY_DX8SL5DDLCTL_DXDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL5DDLCTL_DXDDLBYP_MASK)
38141#define DDRPHY_DX8SL5DDLCTL_DXDDLLD_MASK (0x7C0000U)
38142#define DDRPHY_DX8SL5DDLCTL_DXDDLLD_SHIFT (18U)
38143/*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load
38144 */
38145#define DDRPHY_DX8SL5DDLCTL_DXDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL5DDLCTL_DXDDLLD_MASK)
38146#define DDRPHY_DX8SL5DDLCTL_RESERVED_24_23_MASK (0x1800000U)
38147#define DDRPHY_DX8SL5DDLCTL_RESERVED_24_23_SHIFT (23U)
38148/*! RESERVED_24_23 - Reserved. Return zeroes on reads.
38149 */
38150#define DDRPHY_DX8SL5DDLCTL_RESERVED_24_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL5DDLCTL_RESERVED_24_23_MASK)
38151#define DDRPHY_DX8SL5DDLCTL_DXDDLLDT_MASK (0x2000000U)
38152#define DDRPHY_DX8SL5DDLCTL_DXDDLLDT_SHIFT (25U)
38153/*! DXDDLLDT - DX DDL Load Type
38154 */
38155#define DDRPHY_DX8SL5DDLCTL_DXDDLLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL5DDLCTL_DXDDLLDT_MASK)
38156#define DDRPHY_DX8SL5DDLCTL_DLYLDTM_MASK (0x4000000U)
38157#define DDRPHY_DX8SL5DDLCTL_DLYLDTM_SHIFT (26U)
38158/*! DLYLDTM - Delay Load Timing
38159 */
38160#define DDRPHY_DX8SL5DDLCTL_DLYLDTM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL5DDLCTL_DLYLDTM_MASK)
38161#define DDRPHY_DX8SL5DDLCTL_RESERVED_31_27_MASK (0xF8000000U)
38162#define DDRPHY_DX8SL5DDLCTL_RESERVED_31_27_SHIFT (27U)
38163/*! RESERVED_31_27 - Reserved. Return zeroes on reads.
38164 */
38165#define DDRPHY_DX8SL5DDLCTL_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL5DDLCTL_RESERVED_31_27_MASK)
38166/*! @} */
38167
38168/*! @name DX8SL5DXCTL1 - DATX8 0-1 DX Control Register 1 */
38169/*! @{ */
38170#define DDRPHY_DX8SL5DXCTL1_RESERVED_15_0_MASK (0xFFFFU)
38171#define DDRPHY_DX8SL5DXCTL1_RESERVED_15_0_SHIFT (0U)
38172/*! RESERVED_15_0 - Reserved. Return zeroes on reads.
38173 */
38174#define DDRPHY_DX8SL5DXCTL1_RESERVED_15_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL5DXCTL1_RESERVED_15_0_MASK)
38175#define DDRPHY_DX8SL5DXCTL1_DXTMODE_MASK (0x10000U)
38176#define DDRPHY_DX8SL5DXCTL1_DXTMODE_SHIFT (16U)
38177/*! DXTMODE - DATX8 Test Mode
38178 */
38179#define DDRPHY_DX8SL5DXCTL1_DXTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXTMODE_MASK)
38180#define DDRPHY_DX8SL5DXCTL1_DXGDBYP_MASK (0x20000U)
38181#define DDRPHY_DX8SL5DXCTL1_DXGDBYP_SHIFT (17U)
38182/*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode
38183 */
38184#define DDRPHY_DX8SL5DXCTL1_DXGDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXGDBYP_MASK)
38185#define DDRPHY_DX8SL5DXCTL1_DXQSDBYP_MASK (0x40000U)
38186#define DDRPHY_DX8SL5DXCTL1_DXQSDBYP_SHIFT (18U)
38187/*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode
38188 */
38189#define DDRPHY_DX8SL5DXCTL1_DXQSDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXQSDBYP_MASK)
38190#define DDRPHY_DX8SL5DXCTL1_DXGSMD_MASK (0x80000U)
38191#define DDRPHY_DX8SL5DXCTL1_DXGSMD_SHIFT (19U)
38192/*! DXGSMD - Read DQS Gating Status Mode
38193 */
38194#define DDRPHY_DX8SL5DXCTL1_DXGSMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXGSMD_MASK)
38195#define DDRPHY_DX8SL5DXCTL1_DXDTOSEL_MASK (0x300000U)
38196#define DDRPHY_DX8SL5DXCTL1_DXDTOSEL_SHIFT (20U)
38197/*! DXDTOSEL - DATX8 Digital Test Output Select
38198 */
38199#define DDRPHY_DX8SL5DXCTL1_DXDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXDTOSEL_MASK)
38200#define DDRPHY_DX8SL5DXCTL1_RESERVED_22_MASK (0x400000U)
38201#define DDRPHY_DX8SL5DXCTL1_RESERVED_22_SHIFT (22U)
38202/*! RESERVED_22 - Reserved. Return zeroes on reads.
38203 */
38204#define DDRPHY_DX8SL5DXCTL1_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL5DXCTL1_RESERVED_22_MASK)
38205#define DDRPHY_DX8SL5DXCTL1_DXRCLKMD_MASK (0x800000U)
38206#define DDRPHY_DX8SL5DXCTL1_DXRCLKMD_SHIFT (23U)
38207/*! DXRCLKMD - DATX8 Read Clock Mode
38208 */
38209#define DDRPHY_DX8SL5DXCTL1_DXRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXRCLKMD_MASK)
38210#define DDRPHY_DX8SL5DXCTL1_DXCALCLK_MASK (0x1000000U)
38211#define DDRPHY_DX8SL5DXCTL1_DXCALCLK_SHIFT (24U)
38212/*! DXCALCLK - DATX Calibration Clock Select
38213 */
38214#define DDRPHY_DX8SL5DXCTL1_DXCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL5DXCTL1_DXCALCLK_MASK)
38215#define DDRPHY_DX8SL5DXCTL1_RESERVED_31_25_MASK (0xFE000000U)
38216#define DDRPHY_DX8SL5DXCTL1_RESERVED_31_25_SHIFT (25U)
38217/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
38218 */
38219#define DDRPHY_DX8SL5DXCTL1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL5DXCTL1_RESERVED_31_25_MASK)
38220/*! @} */
38221
38222/*! @name DX8SL5DXCTL2 - DATX8 0-1 DX Control Register 2 */
38223/*! @{ */
38224#define DDRPHY_DX8SL5DXCTL2_RESERVED_0_MASK (0x1U)
38225#define DDRPHY_DX8SL5DXCTL2_RESERVED_0_SHIFT (0U)
38226/*! RESERVED_0 - Reserved. Return zeroes on reads.
38227 */
38228#define DDRPHY_DX8SL5DXCTL2_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL5DXCTL2_RESERVED_0_MASK)
38229#define DDRPHY_DX8SL5DXCTL2_DQSGLB_MASK (0x6U)
38230#define DDRPHY_DX8SL5DXCTL2_DQSGLB_SHIFT (1U)
38231/*! DQSGLB - Read DQS Gate I/O Loopback
38232 */
38233#define DDRPHY_DX8SL5DXCTL2_DQSGLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL5DXCTL2_DQSGLB_MASK)
38234#define DDRPHY_DX8SL5DXCTL2_DISRST_MASK (0x8U)
38235#define DDRPHY_DX8SL5DXCTL2_DISRST_SHIFT (3U)
38236/*! DISRST - Disables the Read FIFO Reset
38237 */
38238#define DDRPHY_DX8SL5DXCTL2_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL5DXCTL2_DISRST_MASK)
38239#define DDRPHY_DX8SL5DXCTL2_RDMODE_MASK (0x30U)
38240#define DDRPHY_DX8SL5DXCTL2_RDMODE_SHIFT (4U)
38241/*! RDMODE - DATX8 Receive FIFO Read Mode
38242 */
38243#define DDRPHY_DX8SL5DXCTL2_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL5DXCTL2_RDMODE_MASK)
38244#define DDRPHY_DX8SL5DXCTL2_PRFBYP_MASK (0x40U)
38245#define DDRPHY_DX8SL5DXCTL2_PRFBYP_SHIFT (6U)
38246/*! PRFBYP - PUB Read FIFO Bypass
38247 */
38248#define DDRPHY_DX8SL5DXCTL2_PRFBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL5DXCTL2_PRFBYP_MASK)
38249#define DDRPHY_DX8SL5DXCTL2_WDBI_MASK (0x80U)
38250#define DDRPHY_DX8SL5DXCTL2_WDBI_SHIFT (7U)
38251/*! WDBI - Write Data Bus Inversion Enable
38252 */
38253#define DDRPHY_DX8SL5DXCTL2_WDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL5DXCTL2_WDBI_MASK)
38254#define DDRPHY_DX8SL5DXCTL2_RDBI_MASK (0x100U)
38255#define DDRPHY_DX8SL5DXCTL2_RDBI_SHIFT (8U)
38256/*! RDBI - Read Data Bus Inversion Enable
38257 */
38258#define DDRPHY_DX8SL5DXCTL2_RDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL5DXCTL2_RDBI_MASK)
38259#define DDRPHY_DX8SL5DXCTL2_LPWAKEUP_THRSH_MASK (0x1E00U)
38260#define DDRPHY_DX8SL5DXCTL2_LPWAKEUP_THRSH_SHIFT (9U)
38261/*! LPWAKEUP_THRSH - Low Power Wakeup Threshold
38262 */
38263#define DDRPHY_DX8SL5DXCTL2_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL5DXCTL2_LPWAKEUP_THRSH_MASK)
38264#define DDRPHY_DX8SL5DXCTL2_RESERVED_14_13_MASK (0x6000U)
38265#define DDRPHY_DX8SL5DXCTL2_RESERVED_14_13_SHIFT (13U)
38266/*! RESERVED_14_13 - Reserved. Return zeroes on reads.
38267 */
38268#define DDRPHY_DX8SL5DXCTL2_RESERVED_14_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL5DXCTL2_RESERVED_14_13_MASK)
38269#define DDRPHY_DX8SL5DXCTL2_IOLB_MASK (0x8000U)
38270#define DDRPHY_DX8SL5DXCTL2_IOLB_SHIFT (15U)
38271/*! IOLB - I/O Loopback Select
38272 */
38273#define DDRPHY_DX8SL5DXCTL2_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL5DXCTL2_IOLB_MASK)
38274#define DDRPHY_DX8SL5DXCTL2_IOAG_MASK (0x10000U)
38275#define DDRPHY_DX8SL5DXCTL2_IOAG_SHIFT (16U)
38276/*! IOAG - I/O Assisted Gate Select
38277 */
38278#define DDRPHY_DX8SL5DXCTL2_IOAG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL5DXCTL2_IOAG_MASK)
38279#define DDRPHY_DX8SL5DXCTL2_RESERVED_17_MASK (0x20000U)
38280#define DDRPHY_DX8SL5DXCTL2_RESERVED_17_SHIFT (17U)
38281/*! RESERVED_17 - Reserved. Return zeroes on reads.
38282 */
38283#define DDRPHY_DX8SL5DXCTL2_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL5DXCTL2_RESERVED_17_MASK)
38284#define DDRPHY_DX8SL5DXCTL2_PREOEX_MASK (0xC0000U)
38285#define DDRPHY_DX8SL5DXCTL2_PREOEX_SHIFT (18U)
38286/*! PREOEX - OE Extension during Pre-amble
38287 */
38288#define DDRPHY_DX8SL5DXCTL2_PREOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL5DXCTL2_PREOEX_MASK)
38289#define DDRPHY_DX8SL5DXCTL2_POSOEX_MASK (0x700000U)
38290#define DDRPHY_DX8SL5DXCTL2_POSOEX_SHIFT (20U)
38291/*! POSOEX - OX Extension during Post-amble
38292 */
38293#define DDRPHY_DX8SL5DXCTL2_POSOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL5DXCTL2_POSOEX_MASK)
38294#define DDRPHY_DX8SL5DXCTL2_CRDEN_MASK (0x800000U)
38295#define DDRPHY_DX8SL5DXCTL2_CRDEN_SHIFT (23U)
38296/*! CRDEN - Configurable Read Data Enable
38297 */
38298#define DDRPHY_DX8SL5DXCTL2_CRDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL5DXCTL2_CRDEN_MASK)
38299#define DDRPHY_DX8SL5DXCTL2_RESERVED_31_24_MASK (0xFF000000U)
38300#define DDRPHY_DX8SL5DXCTL2_RESERVED_31_24_SHIFT (24U)
38301/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
38302 */
38303#define DDRPHY_DX8SL5DXCTL2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL5DXCTL2_RESERVED_31_24_MASK)
38304/*! @} */
38305
38306/*! @name DX8SL5IOCR - DATX8 0-1 I/O Configuration Register */
38307/*! @{ */
38308#define DDRPHY_DX8SL5IOCR_DXRXM_MASK (0x7FFU)
38309#define DDRPHY_DX8SL5IOCR_DXRXM_SHIFT (0U)
38310/*! DXRXM - DX IO Receiver Mode
38311 */
38312#define DDRPHY_DX8SL5IOCR_DXRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL5IOCR_DXRXM_MASK)
38313#define DDRPHY_DX8SL5IOCR_DXTXM_MASK (0x3FF800U)
38314#define DDRPHY_DX8SL5IOCR_DXTXM_SHIFT (11U)
38315/*! DXTXM - DX IO Transmitter Mode
38316 */
38317#define DDRPHY_DX8SL5IOCR_DXTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL5IOCR_DXTXM_MASK)
38318#define DDRPHY_DX8SL5IOCR_DXIOM_MASK (0x1C00000U)
38319#define DDRPHY_DX8SL5IOCR_DXIOM_SHIFT (22U)
38320/*! DXIOM - DX IO Mode
38321 */
38322#define DDRPHY_DX8SL5IOCR_DXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL5IOCR_DXIOM_MASK)
38323#define DDRPHY_DX8SL5IOCR_DXVREFIOM_MASK (0xE000000U)
38324#define DDRPHY_DX8SL5IOCR_DXVREFIOM_SHIFT (25U)
38325/*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
38326 */
38327#define DDRPHY_DX8SL5IOCR_DXVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL5IOCR_DXVREFIOM_MASK)
38328#define DDRPHY_DX8SL5IOCR_DXDACRANGE_MASK (0x70000000U)
38329#define DDRPHY_DX8SL5IOCR_DXDACRANGE_SHIFT (28U)
38330/*! DXDACRANGE - PVREF_DAC REFSEL range select
38331 */
38332#define DDRPHY_DX8SL5IOCR_DXDACRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL5IOCR_DXDACRANGE_MASK)
38333#define DDRPHY_DX8SL5IOCR_RESERVED_31_MASK (0x80000000U)
38334#define DDRPHY_DX8SL5IOCR_RESERVED_31_SHIFT (31U)
38335/*! RESERVED_31 - Reserved. Return zeroes on reads.
38336 */
38337#define DDRPHY_DX8SL5IOCR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL5IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL5IOCR_RESERVED_31_MASK)
38338/*! @} */
38339
38340/*! @name DX4SL5IOCR - DATX4 Slice 0-1 I/O Configuration Register */
38341/*! @{ */
38342#define DDRPHY_DX4SL5IOCR_RESERVED_31_0_MASK (0xFFFFFFFFU)
38343#define DDRPHY_DX4SL5IOCR_RESERVED_31_0_SHIFT (0U)
38344/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
38345 */
38346#define DDRPHY_DX4SL5IOCR_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL5IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL5IOCR_RESERVED_31_0_MASK)
38347/*! @} */
38348
38349/*! @name DX8SL6OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */
38350/*! @{ */
38351#define DDRPHY_DX8SL6OSC_OSCEN_MASK (0x1U)
38352#define DDRPHY_DX8SL6OSC_OSCEN_SHIFT (0U)
38353/*! OSCEN - Oscillator Enable
38354 */
38355#define DDRPHY_DX8SL6OSC_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL6OSC_OSCEN_MASK)
38356#define DDRPHY_DX8SL6OSC_OSCDIV_MASK (0x1EU)
38357#define DDRPHY_DX8SL6OSC_OSCDIV_SHIFT (1U)
38358/*! OSCDIV - Oscillator Mode Division
38359 */
38360#define DDRPHY_DX8SL6OSC_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL6OSC_OSCDIV_MASK)
38361#define DDRPHY_DX8SL6OSC_OSCWDL_MASK (0x60U)
38362#define DDRPHY_DX8SL6OSC_OSCWDL_SHIFT (5U)
38363/*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select
38364 */
38365#define DDRPHY_DX8SL6OSC_OSCWDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL6OSC_OSCWDL_MASK)
38366#define DDRPHY_DX8SL6OSC_RESERVED_8_7_MASK (0x180U)
38367#define DDRPHY_DX8SL6OSC_RESERVED_8_7_SHIFT (7U)
38368/*! RESERVED_8_7 - Reserved. Caution, do not write to this register field.
38369 */
38370#define DDRPHY_DX8SL6OSC_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL6OSC_RESERVED_8_7_MASK)
38371#define DDRPHY_DX8SL6OSC_OSCWDDL_MASK (0x600U)
38372#define DDRPHY_DX8SL6OSC_OSCWDDL_SHIFT (9U)
38373/*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select
38374 */
38375#define DDRPHY_DX8SL6OSC_OSCWDDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL6OSC_OSCWDDL_MASK)
38376#define DDRPHY_DX8SL6OSC_RESERVED_12_11_MASK (0x1800U)
38377#define DDRPHY_DX8SL6OSC_RESERVED_12_11_SHIFT (11U)
38378/*! RESERVED_12_11 - Reserved. Caution, do not write to this register field.
38379 */
38380#define DDRPHY_DX8SL6OSC_RESERVED_12_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL6OSC_RESERVED_12_11_MASK)
38381#define DDRPHY_DX8SL6OSC_DLTMODE_MASK (0x2000U)
38382#define DDRPHY_DX8SL6OSC_DLTMODE_SHIFT (13U)
38383/*! DLTMODE - Delay Line Test Mode
38384 */
38385#define DDRPHY_DX8SL6OSC_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL6OSC_DLTMODE_MASK)
38386#define DDRPHY_DX8SL6OSC_DLTST_MASK (0x4000U)
38387#define DDRPHY_DX8SL6OSC_DLTST_SHIFT (14U)
38388/*! DLTST - Delay Line Test Start
38389 */
38390#define DDRPHY_DX8SL6OSC_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_DLTST_SHIFT)) & DDRPHY_DX8SL6OSC_DLTST_MASK)
38391#define DDRPHY_DX8SL6OSC_PHYFRST_MASK (0x8000U)
38392#define DDRPHY_DX8SL6OSC_PHYFRST_SHIFT (15U)
38393/*! PHYFRST - PHY FIFO Reset
38394 */
38395#define DDRPHY_DX8SL6OSC_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL6OSC_PHYFRST_MASK)
38396#define DDRPHY_DX8SL6OSC_PHYHRST_MASK (0x10000U)
38397#define DDRPHY_DX8SL6OSC_PHYHRST_SHIFT (16U)
38398/*! PHYHRST - PHY High-Speed Reset
38399 */
38400#define DDRPHY_DX8SL6OSC_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL6OSC_PHYHRST_MASK)
38401#define DDRPHY_DX8SL6OSC_LBDQSS_MASK (0x20000U)
38402#define DDRPHY_DX8SL6OSC_LBDQSS_SHIFT (17U)
38403/*! LBDQSS - Loopback DQS Shift
38404 */
38405#define DDRPHY_DX8SL6OSC_LBDQSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL6OSC_LBDQSS_MASK)
38406#define DDRPHY_DX8SL6OSC_LBGDQS_MASK (0xC0000U)
38407#define DDRPHY_DX8SL6OSC_LBGDQS_SHIFT (18U)
38408/*! LBGDQS - Loopback DQS Gating
38409 */
38410#define DDRPHY_DX8SL6OSC_LBGDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL6OSC_LBGDQS_MASK)
38411#define DDRPHY_DX8SL6OSC_LBGSDQS_MASK (0x100000U)
38412#define DDRPHY_DX8SL6OSC_LBGSDQS_SHIFT (20U)
38413/*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
38414 */
38415#define DDRPHY_DX8SL6OSC_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL6OSC_LBGSDQS_MASK)
38416#define DDRPHY_DX8SL6OSC_LBMODE_MASK (0x200000U)
38417#define DDRPHY_DX8SL6OSC_LBMODE_SHIFT (21U)
38418/*! LBMODE - Loopback Mode
38419 */
38420#define DDRPHY_DX8SL6OSC_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL6OSC_LBMODE_MASK)
38421#define DDRPHY_DX8SL6OSC_CLKLEVEL_MASK (0xC00000U)
38422#define DDRPHY_DX8SL6OSC_CLKLEVEL_SHIFT (22U)
38423/*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled.
38424 */
38425#define DDRPHY_DX8SL6OSC_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL6OSC_CLKLEVEL_MASK)
38426#define DDRPHY_DX8SL6OSC_GATEDXCTLCLK_MASK (0x3000000U)
38427#define DDRPHY_DX8SL6OSC_GATEDXCTLCLK_SHIFT (24U)
38428/*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk
38429 */
38430#define DDRPHY_DX8SL6OSC_GATEDXCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL6OSC_GATEDXCTLCLK_MASK)
38431#define DDRPHY_DX8SL6OSC_GATEDXDDRCLK_MASK (0xC000000U)
38432#define DDRPHY_DX8SL6OSC_GATEDXDDRCLK_SHIFT (26U)
38433/*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk
38434 */
38435#define DDRPHY_DX8SL6OSC_GATEDXDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL6OSC_GATEDXDDRCLK_MASK)
38436#define DDRPHY_DX8SL6OSC_GATEDXRDCLK_MASK (0x30000000U)
38437#define DDRPHY_DX8SL6OSC_GATEDXRDCLK_SHIFT (28U)
38438/*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk
38439 */
38440#define DDRPHY_DX8SL6OSC_GATEDXRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL6OSC_GATEDXRDCLK_MASK)
38441#define DDRPHY_DX8SL6OSC_RESERVED_31_30_MASK (0xC0000000U)
38442#define DDRPHY_DX8SL6OSC_RESERVED_31_30_SHIFT (30U)
38443/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
38444 */
38445#define DDRPHY_DX8SL6OSC_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL6OSC_RESERVED_31_30_MASK)
38446/*! @} */
38447
38448/*! @name DX8SL6PLLCR0 - DAXT8 0-1 PLL Control Register 0 */
38449/*! @{ */
38450#define DDRPHY_DX8SL6PLLCR0_DTC_MASK (0xFU)
38451#define DDRPHY_DX8SL6PLLCR0_DTC_SHIFT (0U)
38452/*! DTC - Digital Test Control
38453 */
38454#define DDRPHY_DX8SL6PLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL6PLLCR0_DTC_MASK)
38455#define DDRPHY_DX8SL6PLLCR0_ATC_MASK (0xF0U)
38456#define DDRPHY_DX8SL6PLLCR0_ATC_SHIFT (4U)
38457/*! ATC - Analog Test Control
38458 */
38459#define DDRPHY_DX8SL6PLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL6PLLCR0_ATC_MASK)
38460#define DDRPHY_DX8SL6PLLCR0_ATOEN_MASK (0x100U)
38461#define DDRPHY_DX8SL6PLLCR0_ATOEN_SHIFT (8U)
38462/*! ATOEN - Analog Test Enable (ATOEN)
38463 */
38464#define DDRPHY_DX8SL6PLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL6PLLCR0_ATOEN_MASK)
38465#define DDRPHY_DX8SL6PLLCR0_RESERVED_11_9_MASK (0xE00U)
38466#define DDRPHY_DX8SL6PLLCR0_RESERVED_11_9_SHIFT (9U)
38467/*! RESERVED_11_9 - Reserved. Return zeroes on reads.
38468 */
38469#define DDRPHY_DX8SL6PLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL6PLLCR0_RESERVED_11_9_MASK)
38470#define DDRPHY_DX8SL6PLLCR0_GSHIFT_MASK (0x1000U)
38471#define DDRPHY_DX8SL6PLLCR0_GSHIFT_SHIFT (12U)
38472/*! GSHIFT - Gear Shift
38473 */
38474#define DDRPHY_DX8SL6PLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL6PLLCR0_GSHIFT_MASK)
38475#define DDRPHY_DX8SL6PLLCR0_CPIC_MASK (0x1E000U)
38476#define DDRPHY_DX8SL6PLLCR0_CPIC_SHIFT (13U)
38477/*! CPIC - Charge Pump Integrating Current Control
38478 */
38479#define DDRPHY_DX8SL6PLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL6PLLCR0_CPIC_MASK)
38480#define DDRPHY_DX8SL6PLLCR0_CPPC_MASK (0x7E0000U)
38481#define DDRPHY_DX8SL6PLLCR0_CPPC_SHIFT (17U)
38482/*! CPPC - Charge Pump Proportional Current Control
38483 */
38484#define DDRPHY_DX8SL6PLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL6PLLCR0_CPPC_MASK)
38485#define DDRPHY_DX8SL6PLLCR0_RLOCKM_MASK (0x800000U)
38486#define DDRPHY_DX8SL6PLLCR0_RLOCKM_SHIFT (23U)
38487/*! RLOCKM - Relock Mode
38488 */
38489#define DDRPHY_DX8SL6PLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL6PLLCR0_RLOCKM_MASK)
38490#define DDRPHY_DX8SL6PLLCR0_FRQSEL_MASK (0xF000000U)
38491#define DDRPHY_DX8SL6PLLCR0_FRQSEL_SHIFT (24U)
38492/*! FRQSEL - PLL Frequency Select
38493 */
38494#define DDRPHY_DX8SL6PLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL6PLLCR0_FRQSEL_MASK)
38495#define DDRPHY_DX8SL6PLLCR0_RSTOPM_MASK (0x10000000U)
38496#define DDRPHY_DX8SL6PLLCR0_RSTOPM_SHIFT (28U)
38497/*! RSTOPM - Reference Stop Mode
38498 */
38499#define DDRPHY_DX8SL6PLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL6PLLCR0_RSTOPM_MASK)
38500#define DDRPHY_DX8SL6PLLCR0_PLLPD_MASK (0x20000000U)
38501#define DDRPHY_DX8SL6PLLCR0_PLLPD_SHIFT (29U)
38502/*! PLLPD - PLL Power Down
38503 */
38504#define DDRPHY_DX8SL6PLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL6PLLCR0_PLLPD_MASK)
38505#define DDRPHY_DX8SL6PLLCR0_PLLRST_MASK (0x40000000U)
38506#define DDRPHY_DX8SL6PLLCR0_PLLRST_SHIFT (30U)
38507/*! PLLRST - PLL Reset
38508 */
38509#define DDRPHY_DX8SL6PLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL6PLLCR0_PLLRST_MASK)
38510#define DDRPHY_DX8SL6PLLCR0_PLLBYP_MASK (0x80000000U)
38511#define DDRPHY_DX8SL6PLLCR0_PLLBYP_SHIFT (31U)
38512/*! PLLBYP - PLL Bypass
38513 */
38514#define DDRPHY_DX8SL6PLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL6PLLCR0_PLLBYP_MASK)
38515/*! @} */
38516
38517/*! @name DX8SL6PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */
38518/*! @{ */
38519#define DDRPHY_DX8SL6PLLCR1_LOCKDS_MASK (0x1U)
38520#define DDRPHY_DX8SL6PLLCR1_LOCKDS_SHIFT (0U)
38521/*! LOCKDS - Lock Detector Select
38522 */
38523#define DDRPHY_DX8SL6PLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL6PLLCR1_LOCKDS_MASK)
38524#define DDRPHY_DX8SL6PLLCR1_LOCKCS_MASK (0x2U)
38525#define DDRPHY_DX8SL6PLLCR1_LOCKCS_SHIFT (1U)
38526/*! LOCKCS - Lock Detector Counter Select
38527 */
38528#define DDRPHY_DX8SL6PLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL6PLLCR1_LOCKCS_MASK)
38529#define DDRPHY_DX8SL6PLLCR1_LOCKPS_MASK (0x4U)
38530#define DDRPHY_DX8SL6PLLCR1_LOCKPS_SHIFT (2U)
38531/*! LOCKPS - Lock Detector Phase Select
38532 */
38533#define DDRPHY_DX8SL6PLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL6PLLCR1_LOCKPS_MASK)
38534#define DDRPHY_DX8SL6PLLCR1_BYPVDD_MASK (0x8U)
38535#define DDRPHY_DX8SL6PLLCR1_BYPVDD_SHIFT (3U)
38536/*! BYPVDD - PLL VDD voltage level control
38537 */
38538#define DDRPHY_DX8SL6PLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL6PLLCR1_BYPVDD_MASK)
38539#define DDRPHY_DX8SL6PLLCR1_BYPVREGDIG_MASK (0x10U)
38540#define DDRPHY_DX8SL6PLLCR1_BYPVREGDIG_SHIFT (4U)
38541/*! BYPVREGDIG - Bypass PLL vreg_dig
38542 */
38543#define DDRPHY_DX8SL6PLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL6PLLCR1_BYPVREGDIG_MASK)
38544#define DDRPHY_DX8SL6PLLCR1_BYPVREGCP_MASK (0x20U)
38545#define DDRPHY_DX8SL6PLLCR1_BYPVREGCP_SHIFT (5U)
38546/*! BYPVREGCP - Bypass PLL vreg_cp
38547 */
38548#define DDRPHY_DX8SL6PLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL6PLLCR1_BYPVREGCP_MASK)
38549#define DDRPHY_DX8SL6PLLCR1_PLLPROG_MASK (0x3FFFC0U)
38550#define DDRPHY_DX8SL6PLLCR1_PLLPROG_SHIFT (6U)
38551/*! PLLPROG - Connects to the PLL PLL_PROG bus.
38552 */
38553#define DDRPHY_DX8SL6PLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL6PLLCR1_PLLPROG_MASK)
38554#define DDRPHY_DX8SL6PLLCR1_RESERVED_31_22_MASK (0xFFC00000U)
38555#define DDRPHY_DX8SL6PLLCR1_RESERVED_31_22_SHIFT (22U)
38556/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
38557 */
38558#define DDRPHY_DX8SL6PLLCR1_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL6PLLCR1_RESERVED_31_22_MASK)
38559/*! @} */
38560
38561/*! @name DX8SL6PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */
38562/*! @{ */
38563#define DDRPHY_DX8SL6PLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU)
38564#define DDRPHY_DX8SL6PLLCR2_PLLCTRL_31_0_SHIFT (0U)
38565/*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
38566 */
38567#define DDRPHY_DX8SL6PLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL6PLLCR2_PLLCTRL_31_0_MASK)
38568/*! @} */
38569
38570/*! @name DX8SL6PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */
38571/*! @{ */
38572#define DDRPHY_DX8SL6PLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU)
38573#define DDRPHY_DX8SL6PLLCR3_PLLCTRL_63_32_SHIFT (0U)
38574/*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
38575 */
38576#define DDRPHY_DX8SL6PLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL6PLLCR3_PLLCTRL_63_32_MASK)
38577/*! @} */
38578
38579/*! @name DX8SL6PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */
38580/*! @{ */
38581#define DDRPHY_DX8SL6PLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU)
38582#define DDRPHY_DX8SL6PLLCR4_PLLCTRL_95_64_SHIFT (0U)
38583/*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
38584 */
38585#define DDRPHY_DX8SL6PLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL6PLLCR4_PLLCTRL_95_64_MASK)
38586/*! @} */
38587
38588/*! @name DX8SL6PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */
38589/*! @{ */
38590#define DDRPHY_DX8SL6PLLCR5_PLLCTRL_103_96_MASK (0xFFU)
38591#define DDRPHY_DX8SL6PLLCR5_PLLCTRL_103_96_SHIFT (0U)
38592/*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
38593 */
38594#define DDRPHY_DX8SL6PLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL6PLLCR5_PLLCTRL_103_96_MASK)
38595#define DDRPHY_DX8SL6PLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U)
38596#define DDRPHY_DX8SL6PLLCR5_RESERVED_31_8_SHIFT (8U)
38597/*! RESERVED_31_8 - Reserved. Return zeroes on reads.
38598 */
38599#define DDRPHY_DX8SL6PLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL6PLLCR5_RESERVED_31_8_MASK)
38600/*! @} */
38601
38602/*! @name DX8SL6DQSCTL - DATX8 0-1 DQS Control Register */
38603/*! @{ */
38604#define DDRPHY_DX8SL6DQSCTL_DQSRES_MASK (0xFU)
38605#define DDRPHY_DX8SL6DQSCTL_DQSRES_SHIFT (0U)
38606/*! DQSRES - DQS Resistor
38607 */
38608#define DDRPHY_DX8SL6DQSCTL_DQSRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL6DQSCTL_DQSRES_MASK)
38609#define DDRPHY_DX8SL6DQSCTL_DQSNRES_MASK (0xF0U)
38610#define DDRPHY_DX8SL6DQSCTL_DQSNRES_SHIFT (4U)
38611/*! DQSNRES - DQS_N Resistor
38612 */
38613#define DDRPHY_DX8SL6DQSCTL_DQSNRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL6DQSCTL_DQSNRES_MASK)
38614#define DDRPHY_DX8SL6DQSCTL_DXSR_MASK (0x300U)
38615#define DDRPHY_DX8SL6DQSCTL_DXSR_SHIFT (8U)
38616/*! DXSR - Data Slew Rate
38617 */
38618#define DDRPHY_DX8SL6DQSCTL_DXSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL6DQSCTL_DXSR_MASK)
38619#define DDRPHY_DX8SL6DQSCTL_RESERVED_12_10_MASK (0x1C00U)
38620#define DDRPHY_DX8SL6DQSCTL_RESERVED_12_10_SHIFT (10U)
38621/*! RESERVED_12_10 - Reserved. Return zeroes on reads.
38622 */
38623#define DDRPHY_DX8SL6DQSCTL_RESERVED_12_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL6DQSCTL_RESERVED_12_10_MASK)
38624#define DDRPHY_DX8SL6DQSCTL_UDQIOM_MASK (0x2000U)
38625#define DDRPHY_DX8SL6DQSCTL_UDQIOM_SHIFT (13U)
38626/*! UDQIOM - Unused DQ I/O Mode
38627 */
38628#define DDRPHY_DX8SL6DQSCTL_UDQIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL6DQSCTL_UDQIOM_MASK)
38629#define DDRPHY_DX8SL6DQSCTL_QSCNTEN_MASK (0x4000U)
38630#define DDRPHY_DX8SL6DQSCTL_QSCNTEN_SHIFT (14U)
38631/*! QSCNTEN - QS Counter Enable
38632 */
38633#define DDRPHY_DX8SL6DQSCTL_QSCNTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL6DQSCTL_QSCNTEN_MASK)
38634#define DDRPHY_DX8SL6DQSCTL_RESERVED_16_15_MASK (0x18000U)
38635#define DDRPHY_DX8SL6DQSCTL_RESERVED_16_15_SHIFT (15U)
38636/*! RESERVED_16_15 - Reserved. Return zeroes on reads.
38637 */
38638#define DDRPHY_DX8SL6DQSCTL_RESERVED_16_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL6DQSCTL_RESERVED_16_15_MASK)
38639#define DDRPHY_DX8SL6DQSCTL_LPIOPD_MASK (0x20000U)
38640#define DDRPHY_DX8SL6DQSCTL_LPIOPD_SHIFT (17U)
38641/*! LPIOPD - Low Power I/O Power Down
38642 */
38643#define DDRPHY_DX8SL6DQSCTL_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL6DQSCTL_LPIOPD_MASK)
38644#define DDRPHY_DX8SL6DQSCTL_LPPLLPD_MASK (0x40000U)
38645#define DDRPHY_DX8SL6DQSCTL_LPPLLPD_SHIFT (18U)
38646/*! LPPLLPD - Low Power PLL Power Down
38647 */
38648#define DDRPHY_DX8SL6DQSCTL_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL6DQSCTL_LPPLLPD_MASK)
38649#define DDRPHY_DX8SL6DQSCTL_DQSGX_MASK (0x180000U)
38650#define DDRPHY_DX8SL6DQSCTL_DQSGX_SHIFT (19U)
38651/*! DQSGX - DQS Gate Extension
38652 */
38653#define DDRPHY_DX8SL6DQSCTL_DQSGX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL6DQSCTL_DQSGX_MASK)
38654#define DDRPHY_DX8SL6DQSCTL_WRRMODE_MASK (0x200000U)
38655#define DDRPHY_DX8SL6DQSCTL_WRRMODE_SHIFT (21U)
38656/*! WRRMODE - Write Path Rise-to-Rise Mode
38657 */
38658#define DDRPHY_DX8SL6DQSCTL_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL6DQSCTL_WRRMODE_MASK)
38659#define DDRPHY_DX8SL6DQSCTL_RESERVED_23_22_MASK (0xC00000U)
38660#define DDRPHY_DX8SL6DQSCTL_RESERVED_23_22_SHIFT (22U)
38661/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
38662 */
38663#define DDRPHY_DX8SL6DQSCTL_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL6DQSCTL_RESERVED_23_22_MASK)
38664#define DDRPHY_DX8SL6DQSCTL_RRRMODE_MASK (0x1000000U)
38665#define DDRPHY_DX8SL6DQSCTL_RRRMODE_SHIFT (24U)
38666/*! RRRMODE - Read Path Rise-to-Rise Mode
38667 */
38668#define DDRPHY_DX8SL6DQSCTL_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL6DQSCTL_RRRMODE_MASK)
38669#define DDRPHY_DX8SL6DQSCTL_RESERVED_31_25_MASK (0xFE000000U)
38670#define DDRPHY_DX8SL6DQSCTL_RESERVED_31_25_SHIFT (25U)
38671/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
38672 */
38673#define DDRPHY_DX8SL6DQSCTL_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL6DQSCTL_RESERVED_31_25_MASK)
38674/*! @} */
38675
38676/*! @name DX8SL6TRNCTL - DATX8 0-1 Training Control Register */
38677/*! @{ */
38678#define DDRPHY_DX8SL6TRNCTL_RESERVED_31_0_MASK (0xFFFFFFFFU)
38679#define DDRPHY_DX8SL6TRNCTL_RESERVED_31_0_SHIFT (0U)
38680/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
38681 */
38682#define DDRPHY_DX8SL6TRNCTL_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL6TRNCTL_RESERVED_31_0_MASK)
38683/*! @} */
38684
38685/*! @name DX8SL6DDLCTL - DATX8 0-1 DDL Control Register */
38686/*! @{ */
38687#define DDRPHY_DX8SL6DDLCTL_DDLBYPMODE_MASK (0x3U)
38688#define DDRPHY_DX8SL6DDLCTL_DDLBYPMODE_SHIFT (0U)
38689/*! DDLBYPMODE - Controls DDL Bypass Mode
38690 */
38691#define DDRPHY_DX8SL6DDLCTL_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL6DDLCTL_DDLBYPMODE_MASK)
38692#define DDRPHY_DX8SL6DDLCTL_DXDDLBYP_MASK (0x3FFFCU)
38693#define DDRPHY_DX8SL6DDLCTL_DXDDLBYP_SHIFT (2U)
38694/*! DXDDLBYP - DATX8 DDL Bypass
38695 */
38696#define DDRPHY_DX8SL6DDLCTL_DXDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL6DDLCTL_DXDDLBYP_MASK)
38697#define DDRPHY_DX8SL6DDLCTL_DXDDLLD_MASK (0x7C0000U)
38698#define DDRPHY_DX8SL6DDLCTL_DXDDLLD_SHIFT (18U)
38699/*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load
38700 */
38701#define DDRPHY_DX8SL6DDLCTL_DXDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL6DDLCTL_DXDDLLD_MASK)
38702#define DDRPHY_DX8SL6DDLCTL_RESERVED_24_23_MASK (0x1800000U)
38703#define DDRPHY_DX8SL6DDLCTL_RESERVED_24_23_SHIFT (23U)
38704/*! RESERVED_24_23 - Reserved. Return zeroes on reads.
38705 */
38706#define DDRPHY_DX8SL6DDLCTL_RESERVED_24_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL6DDLCTL_RESERVED_24_23_MASK)
38707#define DDRPHY_DX8SL6DDLCTL_DXDDLLDT_MASK (0x2000000U)
38708#define DDRPHY_DX8SL6DDLCTL_DXDDLLDT_SHIFT (25U)
38709/*! DXDDLLDT - DX DDL Load Type
38710 */
38711#define DDRPHY_DX8SL6DDLCTL_DXDDLLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL6DDLCTL_DXDDLLDT_MASK)
38712#define DDRPHY_DX8SL6DDLCTL_DLYLDTM_MASK (0x4000000U)
38713#define DDRPHY_DX8SL6DDLCTL_DLYLDTM_SHIFT (26U)
38714/*! DLYLDTM - Delay Load Timing
38715 */
38716#define DDRPHY_DX8SL6DDLCTL_DLYLDTM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL6DDLCTL_DLYLDTM_MASK)
38717#define DDRPHY_DX8SL6DDLCTL_RESERVED_31_27_MASK (0xF8000000U)
38718#define DDRPHY_DX8SL6DDLCTL_RESERVED_31_27_SHIFT (27U)
38719/*! RESERVED_31_27 - Reserved. Return zeroes on reads.
38720 */
38721#define DDRPHY_DX8SL6DDLCTL_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL6DDLCTL_RESERVED_31_27_MASK)
38722/*! @} */
38723
38724/*! @name DX8SL6DXCTL1 - DATX8 0-1 DX Control Register 1 */
38725/*! @{ */
38726#define DDRPHY_DX8SL6DXCTL1_RESERVED_15_0_MASK (0xFFFFU)
38727#define DDRPHY_DX8SL6DXCTL1_RESERVED_15_0_SHIFT (0U)
38728/*! RESERVED_15_0 - Reserved. Return zeroes on reads.
38729 */
38730#define DDRPHY_DX8SL6DXCTL1_RESERVED_15_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL6DXCTL1_RESERVED_15_0_MASK)
38731#define DDRPHY_DX8SL6DXCTL1_DXTMODE_MASK (0x10000U)
38732#define DDRPHY_DX8SL6DXCTL1_DXTMODE_SHIFT (16U)
38733/*! DXTMODE - DATX8 Test Mode
38734 */
38735#define DDRPHY_DX8SL6DXCTL1_DXTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXTMODE_MASK)
38736#define DDRPHY_DX8SL6DXCTL1_DXGDBYP_MASK (0x20000U)
38737#define DDRPHY_DX8SL6DXCTL1_DXGDBYP_SHIFT (17U)
38738/*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode
38739 */
38740#define DDRPHY_DX8SL6DXCTL1_DXGDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXGDBYP_MASK)
38741#define DDRPHY_DX8SL6DXCTL1_DXQSDBYP_MASK (0x40000U)
38742#define DDRPHY_DX8SL6DXCTL1_DXQSDBYP_SHIFT (18U)
38743/*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode
38744 */
38745#define DDRPHY_DX8SL6DXCTL1_DXQSDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXQSDBYP_MASK)
38746#define DDRPHY_DX8SL6DXCTL1_DXGSMD_MASK (0x80000U)
38747#define DDRPHY_DX8SL6DXCTL1_DXGSMD_SHIFT (19U)
38748/*! DXGSMD - Read DQS Gating Status Mode
38749 */
38750#define DDRPHY_DX8SL6DXCTL1_DXGSMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXGSMD_MASK)
38751#define DDRPHY_DX8SL6DXCTL1_DXDTOSEL_MASK (0x300000U)
38752#define DDRPHY_DX8SL6DXCTL1_DXDTOSEL_SHIFT (20U)
38753/*! DXDTOSEL - DATX8 Digital Test Output Select
38754 */
38755#define DDRPHY_DX8SL6DXCTL1_DXDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXDTOSEL_MASK)
38756#define DDRPHY_DX8SL6DXCTL1_RESERVED_22_MASK (0x400000U)
38757#define DDRPHY_DX8SL6DXCTL1_RESERVED_22_SHIFT (22U)
38758/*! RESERVED_22 - Reserved. Return zeroes on reads.
38759 */
38760#define DDRPHY_DX8SL6DXCTL1_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL6DXCTL1_RESERVED_22_MASK)
38761#define DDRPHY_DX8SL6DXCTL1_DXRCLKMD_MASK (0x800000U)
38762#define DDRPHY_DX8SL6DXCTL1_DXRCLKMD_SHIFT (23U)
38763/*! DXRCLKMD - DATX8 Read Clock Mode
38764 */
38765#define DDRPHY_DX8SL6DXCTL1_DXRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXRCLKMD_MASK)
38766#define DDRPHY_DX8SL6DXCTL1_DXCALCLK_MASK (0x1000000U)
38767#define DDRPHY_DX8SL6DXCTL1_DXCALCLK_SHIFT (24U)
38768/*! DXCALCLK - DATX Calibration Clock Select
38769 */
38770#define DDRPHY_DX8SL6DXCTL1_DXCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL6DXCTL1_DXCALCLK_MASK)
38771#define DDRPHY_DX8SL6DXCTL1_RESERVED_31_25_MASK (0xFE000000U)
38772#define DDRPHY_DX8SL6DXCTL1_RESERVED_31_25_SHIFT (25U)
38773/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
38774 */
38775#define DDRPHY_DX8SL6DXCTL1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL6DXCTL1_RESERVED_31_25_MASK)
38776/*! @} */
38777
38778/*! @name DX8SL6DXCTL2 - DATX8 0-1 DX Control Register 2 */
38779/*! @{ */
38780#define DDRPHY_DX8SL6DXCTL2_RESERVED_0_MASK (0x1U)
38781#define DDRPHY_DX8SL6DXCTL2_RESERVED_0_SHIFT (0U)
38782/*! RESERVED_0 - Reserved. Return zeroes on reads.
38783 */
38784#define DDRPHY_DX8SL6DXCTL2_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL6DXCTL2_RESERVED_0_MASK)
38785#define DDRPHY_DX8SL6DXCTL2_DQSGLB_MASK (0x6U)
38786#define DDRPHY_DX8SL6DXCTL2_DQSGLB_SHIFT (1U)
38787/*! DQSGLB - Read DQS Gate I/O Loopback
38788 */
38789#define DDRPHY_DX8SL6DXCTL2_DQSGLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL6DXCTL2_DQSGLB_MASK)
38790#define DDRPHY_DX8SL6DXCTL2_DISRST_MASK (0x8U)
38791#define DDRPHY_DX8SL6DXCTL2_DISRST_SHIFT (3U)
38792/*! DISRST - Disables the Read FIFO Reset
38793 */
38794#define DDRPHY_DX8SL6DXCTL2_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL6DXCTL2_DISRST_MASK)
38795#define DDRPHY_DX8SL6DXCTL2_RDMODE_MASK (0x30U)
38796#define DDRPHY_DX8SL6DXCTL2_RDMODE_SHIFT (4U)
38797/*! RDMODE - DATX8 Receive FIFO Read Mode
38798 */
38799#define DDRPHY_DX8SL6DXCTL2_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL6DXCTL2_RDMODE_MASK)
38800#define DDRPHY_DX8SL6DXCTL2_PRFBYP_MASK (0x40U)
38801#define DDRPHY_DX8SL6DXCTL2_PRFBYP_SHIFT (6U)
38802/*! PRFBYP - PUB Read FIFO Bypass
38803 */
38804#define DDRPHY_DX8SL6DXCTL2_PRFBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL6DXCTL2_PRFBYP_MASK)
38805#define DDRPHY_DX8SL6DXCTL2_WDBI_MASK (0x80U)
38806#define DDRPHY_DX8SL6DXCTL2_WDBI_SHIFT (7U)
38807/*! WDBI - Write Data Bus Inversion Enable
38808 */
38809#define DDRPHY_DX8SL6DXCTL2_WDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL6DXCTL2_WDBI_MASK)
38810#define DDRPHY_DX8SL6DXCTL2_RDBI_MASK (0x100U)
38811#define DDRPHY_DX8SL6DXCTL2_RDBI_SHIFT (8U)
38812/*! RDBI - Read Data Bus Inversion Enable
38813 */
38814#define DDRPHY_DX8SL6DXCTL2_RDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL6DXCTL2_RDBI_MASK)
38815#define DDRPHY_DX8SL6DXCTL2_LPWAKEUP_THRSH_MASK (0x1E00U)
38816#define DDRPHY_DX8SL6DXCTL2_LPWAKEUP_THRSH_SHIFT (9U)
38817/*! LPWAKEUP_THRSH - Low Power Wakeup Threshold
38818 */
38819#define DDRPHY_DX8SL6DXCTL2_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL6DXCTL2_LPWAKEUP_THRSH_MASK)
38820#define DDRPHY_DX8SL6DXCTL2_RESERVED_14_13_MASK (0x6000U)
38821#define DDRPHY_DX8SL6DXCTL2_RESERVED_14_13_SHIFT (13U)
38822/*! RESERVED_14_13 - Reserved. Return zeroes on reads.
38823 */
38824#define DDRPHY_DX8SL6DXCTL2_RESERVED_14_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL6DXCTL2_RESERVED_14_13_MASK)
38825#define DDRPHY_DX8SL6DXCTL2_IOLB_MASK (0x8000U)
38826#define DDRPHY_DX8SL6DXCTL2_IOLB_SHIFT (15U)
38827/*! IOLB - I/O Loopback Select
38828 */
38829#define DDRPHY_DX8SL6DXCTL2_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL6DXCTL2_IOLB_MASK)
38830#define DDRPHY_DX8SL6DXCTL2_IOAG_MASK (0x10000U)
38831#define DDRPHY_DX8SL6DXCTL2_IOAG_SHIFT (16U)
38832/*! IOAG - I/O Assisted Gate Select
38833 */
38834#define DDRPHY_DX8SL6DXCTL2_IOAG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL6DXCTL2_IOAG_MASK)
38835#define DDRPHY_DX8SL6DXCTL2_RESERVED_17_MASK (0x20000U)
38836#define DDRPHY_DX8SL6DXCTL2_RESERVED_17_SHIFT (17U)
38837/*! RESERVED_17 - Reserved. Return zeroes on reads.
38838 */
38839#define DDRPHY_DX8SL6DXCTL2_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL6DXCTL2_RESERVED_17_MASK)
38840#define DDRPHY_DX8SL6DXCTL2_PREOEX_MASK (0xC0000U)
38841#define DDRPHY_DX8SL6DXCTL2_PREOEX_SHIFT (18U)
38842/*! PREOEX - OE Extension during Pre-amble
38843 */
38844#define DDRPHY_DX8SL6DXCTL2_PREOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL6DXCTL2_PREOEX_MASK)
38845#define DDRPHY_DX8SL6DXCTL2_POSOEX_MASK (0x700000U)
38846#define DDRPHY_DX8SL6DXCTL2_POSOEX_SHIFT (20U)
38847/*! POSOEX - OX Extension during Post-amble
38848 */
38849#define DDRPHY_DX8SL6DXCTL2_POSOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL6DXCTL2_POSOEX_MASK)
38850#define DDRPHY_DX8SL6DXCTL2_CRDEN_MASK (0x800000U)
38851#define DDRPHY_DX8SL6DXCTL2_CRDEN_SHIFT (23U)
38852/*! CRDEN - Configurable Read Data Enable
38853 */
38854#define DDRPHY_DX8SL6DXCTL2_CRDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL6DXCTL2_CRDEN_MASK)
38855#define DDRPHY_DX8SL6DXCTL2_RESERVED_31_24_MASK (0xFF000000U)
38856#define DDRPHY_DX8SL6DXCTL2_RESERVED_31_24_SHIFT (24U)
38857/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
38858 */
38859#define DDRPHY_DX8SL6DXCTL2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL6DXCTL2_RESERVED_31_24_MASK)
38860/*! @} */
38861
38862/*! @name DX8SL6IOCR - DATX8 0-1 I/O Configuration Register */
38863/*! @{ */
38864#define DDRPHY_DX8SL6IOCR_DXRXM_MASK (0x7FFU)
38865#define DDRPHY_DX8SL6IOCR_DXRXM_SHIFT (0U)
38866/*! DXRXM - DX IO Receiver Mode
38867 */
38868#define DDRPHY_DX8SL6IOCR_DXRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL6IOCR_DXRXM_MASK)
38869#define DDRPHY_DX8SL6IOCR_DXTXM_MASK (0x3FF800U)
38870#define DDRPHY_DX8SL6IOCR_DXTXM_SHIFT (11U)
38871/*! DXTXM - DX IO Transmitter Mode
38872 */
38873#define DDRPHY_DX8SL6IOCR_DXTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL6IOCR_DXTXM_MASK)
38874#define DDRPHY_DX8SL6IOCR_DXIOM_MASK (0x1C00000U)
38875#define DDRPHY_DX8SL6IOCR_DXIOM_SHIFT (22U)
38876/*! DXIOM - DX IO Mode
38877 */
38878#define DDRPHY_DX8SL6IOCR_DXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL6IOCR_DXIOM_MASK)
38879#define DDRPHY_DX8SL6IOCR_DXVREFIOM_MASK (0xE000000U)
38880#define DDRPHY_DX8SL6IOCR_DXVREFIOM_SHIFT (25U)
38881/*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
38882 */
38883#define DDRPHY_DX8SL6IOCR_DXVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL6IOCR_DXVREFIOM_MASK)
38884#define DDRPHY_DX8SL6IOCR_DXDACRANGE_MASK (0x70000000U)
38885#define DDRPHY_DX8SL6IOCR_DXDACRANGE_SHIFT (28U)
38886/*! DXDACRANGE - PVREF_DAC REFSEL range select
38887 */
38888#define DDRPHY_DX8SL6IOCR_DXDACRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL6IOCR_DXDACRANGE_MASK)
38889#define DDRPHY_DX8SL6IOCR_RESERVED_31_MASK (0x80000000U)
38890#define DDRPHY_DX8SL6IOCR_RESERVED_31_SHIFT (31U)
38891/*! RESERVED_31 - Reserved. Return zeroes on reads.
38892 */
38893#define DDRPHY_DX8SL6IOCR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL6IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL6IOCR_RESERVED_31_MASK)
38894/*! @} */
38895
38896/*! @name DX4SL6IOCR - DATX4 Slice 0-1 I/O Configuration Register */
38897/*! @{ */
38898#define DDRPHY_DX4SL6IOCR_RESERVED_31_0_MASK (0xFFFFFFFFU)
38899#define DDRPHY_DX4SL6IOCR_RESERVED_31_0_SHIFT (0U)
38900/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
38901 */
38902#define DDRPHY_DX4SL6IOCR_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL6IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL6IOCR_RESERVED_31_0_MASK)
38903/*! @} */
38904
38905/*! @name DX8SL7OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */
38906/*! @{ */
38907#define DDRPHY_DX8SL7OSC_OSCEN_MASK (0x1U)
38908#define DDRPHY_DX8SL7OSC_OSCEN_SHIFT (0U)
38909/*! OSCEN - Oscillator Enable
38910 */
38911#define DDRPHY_DX8SL7OSC_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL7OSC_OSCEN_MASK)
38912#define DDRPHY_DX8SL7OSC_OSCDIV_MASK (0x1EU)
38913#define DDRPHY_DX8SL7OSC_OSCDIV_SHIFT (1U)
38914/*! OSCDIV - Oscillator Mode Division
38915 */
38916#define DDRPHY_DX8SL7OSC_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL7OSC_OSCDIV_MASK)
38917#define DDRPHY_DX8SL7OSC_OSCWDL_MASK (0x60U)
38918#define DDRPHY_DX8SL7OSC_OSCWDL_SHIFT (5U)
38919/*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select
38920 */
38921#define DDRPHY_DX8SL7OSC_OSCWDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL7OSC_OSCWDL_MASK)
38922#define DDRPHY_DX8SL7OSC_RESERVED_8_7_MASK (0x180U)
38923#define DDRPHY_DX8SL7OSC_RESERVED_8_7_SHIFT (7U)
38924/*! RESERVED_8_7 - Reserved. Caution, do not write to this register field.
38925 */
38926#define DDRPHY_DX8SL7OSC_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL7OSC_RESERVED_8_7_MASK)
38927#define DDRPHY_DX8SL7OSC_OSCWDDL_MASK (0x600U)
38928#define DDRPHY_DX8SL7OSC_OSCWDDL_SHIFT (9U)
38929/*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select
38930 */
38931#define DDRPHY_DX8SL7OSC_OSCWDDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL7OSC_OSCWDDL_MASK)
38932#define DDRPHY_DX8SL7OSC_RESERVED_12_11_MASK (0x1800U)
38933#define DDRPHY_DX8SL7OSC_RESERVED_12_11_SHIFT (11U)
38934/*! RESERVED_12_11 - Reserved. Caution, do not write to this register field.
38935 */
38936#define DDRPHY_DX8SL7OSC_RESERVED_12_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL7OSC_RESERVED_12_11_MASK)
38937#define DDRPHY_DX8SL7OSC_DLTMODE_MASK (0x2000U)
38938#define DDRPHY_DX8SL7OSC_DLTMODE_SHIFT (13U)
38939/*! DLTMODE - Delay Line Test Mode
38940 */
38941#define DDRPHY_DX8SL7OSC_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL7OSC_DLTMODE_MASK)
38942#define DDRPHY_DX8SL7OSC_DLTST_MASK (0x4000U)
38943#define DDRPHY_DX8SL7OSC_DLTST_SHIFT (14U)
38944/*! DLTST - Delay Line Test Start
38945 */
38946#define DDRPHY_DX8SL7OSC_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_DLTST_SHIFT)) & DDRPHY_DX8SL7OSC_DLTST_MASK)
38947#define DDRPHY_DX8SL7OSC_PHYFRST_MASK (0x8000U)
38948#define DDRPHY_DX8SL7OSC_PHYFRST_SHIFT (15U)
38949/*! PHYFRST - PHY FIFO Reset
38950 */
38951#define DDRPHY_DX8SL7OSC_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL7OSC_PHYFRST_MASK)
38952#define DDRPHY_DX8SL7OSC_PHYHRST_MASK (0x10000U)
38953#define DDRPHY_DX8SL7OSC_PHYHRST_SHIFT (16U)
38954/*! PHYHRST - PHY High-Speed Reset
38955 */
38956#define DDRPHY_DX8SL7OSC_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL7OSC_PHYHRST_MASK)
38957#define DDRPHY_DX8SL7OSC_LBDQSS_MASK (0x20000U)
38958#define DDRPHY_DX8SL7OSC_LBDQSS_SHIFT (17U)
38959/*! LBDQSS - Loopback DQS Shift
38960 */
38961#define DDRPHY_DX8SL7OSC_LBDQSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL7OSC_LBDQSS_MASK)
38962#define DDRPHY_DX8SL7OSC_LBGDQS_MASK (0xC0000U)
38963#define DDRPHY_DX8SL7OSC_LBGDQS_SHIFT (18U)
38964/*! LBGDQS - Loopback DQS Gating
38965 */
38966#define DDRPHY_DX8SL7OSC_LBGDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL7OSC_LBGDQS_MASK)
38967#define DDRPHY_DX8SL7OSC_LBGSDQS_MASK (0x100000U)
38968#define DDRPHY_DX8SL7OSC_LBGSDQS_SHIFT (20U)
38969/*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
38970 */
38971#define DDRPHY_DX8SL7OSC_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL7OSC_LBGSDQS_MASK)
38972#define DDRPHY_DX8SL7OSC_LBMODE_MASK (0x200000U)
38973#define DDRPHY_DX8SL7OSC_LBMODE_SHIFT (21U)
38974/*! LBMODE - Loopback Mode
38975 */
38976#define DDRPHY_DX8SL7OSC_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL7OSC_LBMODE_MASK)
38977#define DDRPHY_DX8SL7OSC_CLKLEVEL_MASK (0xC00000U)
38978#define DDRPHY_DX8SL7OSC_CLKLEVEL_SHIFT (22U)
38979/*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled.
38980 */
38981#define DDRPHY_DX8SL7OSC_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL7OSC_CLKLEVEL_MASK)
38982#define DDRPHY_DX8SL7OSC_GATEDXCTLCLK_MASK (0x3000000U)
38983#define DDRPHY_DX8SL7OSC_GATEDXCTLCLK_SHIFT (24U)
38984/*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk
38985 */
38986#define DDRPHY_DX8SL7OSC_GATEDXCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL7OSC_GATEDXCTLCLK_MASK)
38987#define DDRPHY_DX8SL7OSC_GATEDXDDRCLK_MASK (0xC000000U)
38988#define DDRPHY_DX8SL7OSC_GATEDXDDRCLK_SHIFT (26U)
38989/*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk
38990 */
38991#define DDRPHY_DX8SL7OSC_GATEDXDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL7OSC_GATEDXDDRCLK_MASK)
38992#define DDRPHY_DX8SL7OSC_GATEDXRDCLK_MASK (0x30000000U)
38993#define DDRPHY_DX8SL7OSC_GATEDXRDCLK_SHIFT (28U)
38994/*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk
38995 */
38996#define DDRPHY_DX8SL7OSC_GATEDXRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL7OSC_GATEDXRDCLK_MASK)
38997#define DDRPHY_DX8SL7OSC_RESERVED_31_30_MASK (0xC0000000U)
38998#define DDRPHY_DX8SL7OSC_RESERVED_31_30_SHIFT (30U)
38999/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
39000 */
39001#define DDRPHY_DX8SL7OSC_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL7OSC_RESERVED_31_30_MASK)
39002/*! @} */
39003
39004/*! @name DX8SL7PLLCR0 - DAXT8 0-1 PLL Control Register 0 */
39005/*! @{ */
39006#define DDRPHY_DX8SL7PLLCR0_DTC_MASK (0xFU)
39007#define DDRPHY_DX8SL7PLLCR0_DTC_SHIFT (0U)
39008/*! DTC - Digital Test Control
39009 */
39010#define DDRPHY_DX8SL7PLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL7PLLCR0_DTC_MASK)
39011#define DDRPHY_DX8SL7PLLCR0_ATC_MASK (0xF0U)
39012#define DDRPHY_DX8SL7PLLCR0_ATC_SHIFT (4U)
39013/*! ATC - Analog Test Control
39014 */
39015#define DDRPHY_DX8SL7PLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL7PLLCR0_ATC_MASK)
39016#define DDRPHY_DX8SL7PLLCR0_ATOEN_MASK (0x100U)
39017#define DDRPHY_DX8SL7PLLCR0_ATOEN_SHIFT (8U)
39018/*! ATOEN - Analog Test Enable (ATOEN)
39019 */
39020#define DDRPHY_DX8SL7PLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL7PLLCR0_ATOEN_MASK)
39021#define DDRPHY_DX8SL7PLLCR0_RESERVED_11_9_MASK (0xE00U)
39022#define DDRPHY_DX8SL7PLLCR0_RESERVED_11_9_SHIFT (9U)
39023/*! RESERVED_11_9 - Reserved. Return zeroes on reads.
39024 */
39025#define DDRPHY_DX8SL7PLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL7PLLCR0_RESERVED_11_9_MASK)
39026#define DDRPHY_DX8SL7PLLCR0_GSHIFT_MASK (0x1000U)
39027#define DDRPHY_DX8SL7PLLCR0_GSHIFT_SHIFT (12U)
39028/*! GSHIFT - Gear Shift
39029 */
39030#define DDRPHY_DX8SL7PLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL7PLLCR0_GSHIFT_MASK)
39031#define DDRPHY_DX8SL7PLLCR0_CPIC_MASK (0x1E000U)
39032#define DDRPHY_DX8SL7PLLCR0_CPIC_SHIFT (13U)
39033/*! CPIC - Charge Pump Integrating Current Control
39034 */
39035#define DDRPHY_DX8SL7PLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL7PLLCR0_CPIC_MASK)
39036#define DDRPHY_DX8SL7PLLCR0_CPPC_MASK (0x7E0000U)
39037#define DDRPHY_DX8SL7PLLCR0_CPPC_SHIFT (17U)
39038/*! CPPC - Charge Pump Proportional Current Control
39039 */
39040#define DDRPHY_DX8SL7PLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL7PLLCR0_CPPC_MASK)
39041#define DDRPHY_DX8SL7PLLCR0_RLOCKM_MASK (0x800000U)
39042#define DDRPHY_DX8SL7PLLCR0_RLOCKM_SHIFT (23U)
39043/*! RLOCKM - Relock Mode
39044 */
39045#define DDRPHY_DX8SL7PLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL7PLLCR0_RLOCKM_MASK)
39046#define DDRPHY_DX8SL7PLLCR0_FRQSEL_MASK (0xF000000U)
39047#define DDRPHY_DX8SL7PLLCR0_FRQSEL_SHIFT (24U)
39048/*! FRQSEL - PLL Frequency Select
39049 */
39050#define DDRPHY_DX8SL7PLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL7PLLCR0_FRQSEL_MASK)
39051#define DDRPHY_DX8SL7PLLCR0_RSTOPM_MASK (0x10000000U)
39052#define DDRPHY_DX8SL7PLLCR0_RSTOPM_SHIFT (28U)
39053/*! RSTOPM - Reference Stop Mode
39054 */
39055#define DDRPHY_DX8SL7PLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL7PLLCR0_RSTOPM_MASK)
39056#define DDRPHY_DX8SL7PLLCR0_PLLPD_MASK (0x20000000U)
39057#define DDRPHY_DX8SL7PLLCR0_PLLPD_SHIFT (29U)
39058/*! PLLPD - PLL Power Down
39059 */
39060#define DDRPHY_DX8SL7PLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL7PLLCR0_PLLPD_MASK)
39061#define DDRPHY_DX8SL7PLLCR0_PLLRST_MASK (0x40000000U)
39062#define DDRPHY_DX8SL7PLLCR0_PLLRST_SHIFT (30U)
39063/*! PLLRST - PLL Reset
39064 */
39065#define DDRPHY_DX8SL7PLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL7PLLCR0_PLLRST_MASK)
39066#define DDRPHY_DX8SL7PLLCR0_PLLBYP_MASK (0x80000000U)
39067#define DDRPHY_DX8SL7PLLCR0_PLLBYP_SHIFT (31U)
39068/*! PLLBYP - PLL Bypass
39069 */
39070#define DDRPHY_DX8SL7PLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL7PLLCR0_PLLBYP_MASK)
39071/*! @} */
39072
39073/*! @name DX8SL7PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */
39074/*! @{ */
39075#define DDRPHY_DX8SL7PLLCR1_LOCKDS_MASK (0x1U)
39076#define DDRPHY_DX8SL7PLLCR1_LOCKDS_SHIFT (0U)
39077/*! LOCKDS - Lock Detector Select
39078 */
39079#define DDRPHY_DX8SL7PLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL7PLLCR1_LOCKDS_MASK)
39080#define DDRPHY_DX8SL7PLLCR1_LOCKCS_MASK (0x2U)
39081#define DDRPHY_DX8SL7PLLCR1_LOCKCS_SHIFT (1U)
39082/*! LOCKCS - Lock Detector Counter Select
39083 */
39084#define DDRPHY_DX8SL7PLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL7PLLCR1_LOCKCS_MASK)
39085#define DDRPHY_DX8SL7PLLCR1_LOCKPS_MASK (0x4U)
39086#define DDRPHY_DX8SL7PLLCR1_LOCKPS_SHIFT (2U)
39087/*! LOCKPS - Lock Detector Phase Select
39088 */
39089#define DDRPHY_DX8SL7PLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL7PLLCR1_LOCKPS_MASK)
39090#define DDRPHY_DX8SL7PLLCR1_BYPVDD_MASK (0x8U)
39091#define DDRPHY_DX8SL7PLLCR1_BYPVDD_SHIFT (3U)
39092/*! BYPVDD - PLL VDD voltage level control
39093 */
39094#define DDRPHY_DX8SL7PLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL7PLLCR1_BYPVDD_MASK)
39095#define DDRPHY_DX8SL7PLLCR1_BYPVREGDIG_MASK (0x10U)
39096#define DDRPHY_DX8SL7PLLCR1_BYPVREGDIG_SHIFT (4U)
39097/*! BYPVREGDIG - Bypass PLL vreg_dig
39098 */
39099#define DDRPHY_DX8SL7PLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL7PLLCR1_BYPVREGDIG_MASK)
39100#define DDRPHY_DX8SL7PLLCR1_BYPVREGCP_MASK (0x20U)
39101#define DDRPHY_DX8SL7PLLCR1_BYPVREGCP_SHIFT (5U)
39102/*! BYPVREGCP - Bypass PLL vreg_cp
39103 */
39104#define DDRPHY_DX8SL7PLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL7PLLCR1_BYPVREGCP_MASK)
39105#define DDRPHY_DX8SL7PLLCR1_PLLPROG_MASK (0x3FFFC0U)
39106#define DDRPHY_DX8SL7PLLCR1_PLLPROG_SHIFT (6U)
39107/*! PLLPROG - Connects to the PLL PLL_PROG bus.
39108 */
39109#define DDRPHY_DX8SL7PLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL7PLLCR1_PLLPROG_MASK)
39110#define DDRPHY_DX8SL7PLLCR1_RESERVED_31_22_MASK (0xFFC00000U)
39111#define DDRPHY_DX8SL7PLLCR1_RESERVED_31_22_SHIFT (22U)
39112/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
39113 */
39114#define DDRPHY_DX8SL7PLLCR1_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL7PLLCR1_RESERVED_31_22_MASK)
39115/*! @} */
39116
39117/*! @name DX8SL7PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */
39118/*! @{ */
39119#define DDRPHY_DX8SL7PLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU)
39120#define DDRPHY_DX8SL7PLLCR2_PLLCTRL_31_0_SHIFT (0U)
39121/*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
39122 */
39123#define DDRPHY_DX8SL7PLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL7PLLCR2_PLLCTRL_31_0_MASK)
39124/*! @} */
39125
39126/*! @name DX8SL7PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */
39127/*! @{ */
39128#define DDRPHY_DX8SL7PLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU)
39129#define DDRPHY_DX8SL7PLLCR3_PLLCTRL_63_32_SHIFT (0U)
39130/*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
39131 */
39132#define DDRPHY_DX8SL7PLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL7PLLCR3_PLLCTRL_63_32_MASK)
39133/*! @} */
39134
39135/*! @name DX8SL7PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */
39136/*! @{ */
39137#define DDRPHY_DX8SL7PLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU)
39138#define DDRPHY_DX8SL7PLLCR4_PLLCTRL_95_64_SHIFT (0U)
39139/*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
39140 */
39141#define DDRPHY_DX8SL7PLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL7PLLCR4_PLLCTRL_95_64_MASK)
39142/*! @} */
39143
39144/*! @name DX8SL7PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */
39145/*! @{ */
39146#define DDRPHY_DX8SL7PLLCR5_PLLCTRL_103_96_MASK (0xFFU)
39147#define DDRPHY_DX8SL7PLLCR5_PLLCTRL_103_96_SHIFT (0U)
39148/*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
39149 */
39150#define DDRPHY_DX8SL7PLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL7PLLCR5_PLLCTRL_103_96_MASK)
39151#define DDRPHY_DX8SL7PLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U)
39152#define DDRPHY_DX8SL7PLLCR5_RESERVED_31_8_SHIFT (8U)
39153/*! RESERVED_31_8 - Reserved. Return zeroes on reads.
39154 */
39155#define DDRPHY_DX8SL7PLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL7PLLCR5_RESERVED_31_8_MASK)
39156/*! @} */
39157
39158/*! @name DX8SL7DQSCTL - DATX8 0-1 DQS Control Register */
39159/*! @{ */
39160#define DDRPHY_DX8SL7DQSCTL_DQSRES_MASK (0xFU)
39161#define DDRPHY_DX8SL7DQSCTL_DQSRES_SHIFT (0U)
39162/*! DQSRES - DQS Resistor
39163 */
39164#define DDRPHY_DX8SL7DQSCTL_DQSRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL7DQSCTL_DQSRES_MASK)
39165#define DDRPHY_DX8SL7DQSCTL_DQSNRES_MASK (0xF0U)
39166#define DDRPHY_DX8SL7DQSCTL_DQSNRES_SHIFT (4U)
39167/*! DQSNRES - DQS_N Resistor
39168 */
39169#define DDRPHY_DX8SL7DQSCTL_DQSNRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL7DQSCTL_DQSNRES_MASK)
39170#define DDRPHY_DX8SL7DQSCTL_DXSR_MASK (0x300U)
39171#define DDRPHY_DX8SL7DQSCTL_DXSR_SHIFT (8U)
39172/*! DXSR - Data Slew Rate
39173 */
39174#define DDRPHY_DX8SL7DQSCTL_DXSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL7DQSCTL_DXSR_MASK)
39175#define DDRPHY_DX8SL7DQSCTL_RESERVED_12_10_MASK (0x1C00U)
39176#define DDRPHY_DX8SL7DQSCTL_RESERVED_12_10_SHIFT (10U)
39177/*! RESERVED_12_10 - Reserved. Return zeroes on reads.
39178 */
39179#define DDRPHY_DX8SL7DQSCTL_RESERVED_12_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL7DQSCTL_RESERVED_12_10_MASK)
39180#define DDRPHY_DX8SL7DQSCTL_UDQIOM_MASK (0x2000U)
39181#define DDRPHY_DX8SL7DQSCTL_UDQIOM_SHIFT (13U)
39182/*! UDQIOM - Unused DQ I/O Mode
39183 */
39184#define DDRPHY_DX8SL7DQSCTL_UDQIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL7DQSCTL_UDQIOM_MASK)
39185#define DDRPHY_DX8SL7DQSCTL_QSCNTEN_MASK (0x4000U)
39186#define DDRPHY_DX8SL7DQSCTL_QSCNTEN_SHIFT (14U)
39187/*! QSCNTEN - QS Counter Enable
39188 */
39189#define DDRPHY_DX8SL7DQSCTL_QSCNTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL7DQSCTL_QSCNTEN_MASK)
39190#define DDRPHY_DX8SL7DQSCTL_RESERVED_16_15_MASK (0x18000U)
39191#define DDRPHY_DX8SL7DQSCTL_RESERVED_16_15_SHIFT (15U)
39192/*! RESERVED_16_15 - Reserved. Return zeroes on reads.
39193 */
39194#define DDRPHY_DX8SL7DQSCTL_RESERVED_16_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL7DQSCTL_RESERVED_16_15_MASK)
39195#define DDRPHY_DX8SL7DQSCTL_LPIOPD_MASK (0x20000U)
39196#define DDRPHY_DX8SL7DQSCTL_LPIOPD_SHIFT (17U)
39197/*! LPIOPD - Low Power I/O Power Down
39198 */
39199#define DDRPHY_DX8SL7DQSCTL_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL7DQSCTL_LPIOPD_MASK)
39200#define DDRPHY_DX8SL7DQSCTL_LPPLLPD_MASK (0x40000U)
39201#define DDRPHY_DX8SL7DQSCTL_LPPLLPD_SHIFT (18U)
39202/*! LPPLLPD - Low Power PLL Power Down
39203 */
39204#define DDRPHY_DX8SL7DQSCTL_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL7DQSCTL_LPPLLPD_MASK)
39205#define DDRPHY_DX8SL7DQSCTL_DQSGX_MASK (0x180000U)
39206#define DDRPHY_DX8SL7DQSCTL_DQSGX_SHIFT (19U)
39207/*! DQSGX - DQS Gate Extension
39208 */
39209#define DDRPHY_DX8SL7DQSCTL_DQSGX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL7DQSCTL_DQSGX_MASK)
39210#define DDRPHY_DX8SL7DQSCTL_WRRMODE_MASK (0x200000U)
39211#define DDRPHY_DX8SL7DQSCTL_WRRMODE_SHIFT (21U)
39212/*! WRRMODE - Write Path Rise-to-Rise Mode
39213 */
39214#define DDRPHY_DX8SL7DQSCTL_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL7DQSCTL_WRRMODE_MASK)
39215#define DDRPHY_DX8SL7DQSCTL_RESERVED_23_22_MASK (0xC00000U)
39216#define DDRPHY_DX8SL7DQSCTL_RESERVED_23_22_SHIFT (22U)
39217/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
39218 */
39219#define DDRPHY_DX8SL7DQSCTL_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL7DQSCTL_RESERVED_23_22_MASK)
39220#define DDRPHY_DX8SL7DQSCTL_RRRMODE_MASK (0x1000000U)
39221#define DDRPHY_DX8SL7DQSCTL_RRRMODE_SHIFT (24U)
39222/*! RRRMODE - Read Path Rise-to-Rise Mode
39223 */
39224#define DDRPHY_DX8SL7DQSCTL_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL7DQSCTL_RRRMODE_MASK)
39225#define DDRPHY_DX8SL7DQSCTL_RESERVED_31_25_MASK (0xFE000000U)
39226#define DDRPHY_DX8SL7DQSCTL_RESERVED_31_25_SHIFT (25U)
39227/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
39228 */
39229#define DDRPHY_DX8SL7DQSCTL_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL7DQSCTL_RESERVED_31_25_MASK)
39230/*! @} */
39231
39232/*! @name DX8SL7TRNCTL - DATX8 0-1 Training Control Register */
39233/*! @{ */
39234#define DDRPHY_DX8SL7TRNCTL_RESERVED_31_0_MASK (0xFFFFFFFFU)
39235#define DDRPHY_DX8SL7TRNCTL_RESERVED_31_0_SHIFT (0U)
39236/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
39237 */
39238#define DDRPHY_DX8SL7TRNCTL_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL7TRNCTL_RESERVED_31_0_MASK)
39239/*! @} */
39240
39241/*! @name DX8SL7DDLCTL - DATX8 0-1 DDL Control Register */
39242/*! @{ */
39243#define DDRPHY_DX8SL7DDLCTL_DDLBYPMODE_MASK (0x3U)
39244#define DDRPHY_DX8SL7DDLCTL_DDLBYPMODE_SHIFT (0U)
39245/*! DDLBYPMODE - Controls DDL Bypass Mode
39246 */
39247#define DDRPHY_DX8SL7DDLCTL_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL7DDLCTL_DDLBYPMODE_MASK)
39248#define DDRPHY_DX8SL7DDLCTL_DXDDLBYP_MASK (0x3FFFCU)
39249#define DDRPHY_DX8SL7DDLCTL_DXDDLBYP_SHIFT (2U)
39250/*! DXDDLBYP - DATX8 DDL Bypass
39251 */
39252#define DDRPHY_DX8SL7DDLCTL_DXDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL7DDLCTL_DXDDLBYP_MASK)
39253#define DDRPHY_DX8SL7DDLCTL_DXDDLLD_MASK (0x7C0000U)
39254#define DDRPHY_DX8SL7DDLCTL_DXDDLLD_SHIFT (18U)
39255/*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load
39256 */
39257#define DDRPHY_DX8SL7DDLCTL_DXDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL7DDLCTL_DXDDLLD_MASK)
39258#define DDRPHY_DX8SL7DDLCTL_RESERVED_24_23_MASK (0x1800000U)
39259#define DDRPHY_DX8SL7DDLCTL_RESERVED_24_23_SHIFT (23U)
39260/*! RESERVED_24_23 - Reserved. Return zeroes on reads.
39261 */
39262#define DDRPHY_DX8SL7DDLCTL_RESERVED_24_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL7DDLCTL_RESERVED_24_23_MASK)
39263#define DDRPHY_DX8SL7DDLCTL_DXDDLLDT_MASK (0x2000000U)
39264#define DDRPHY_DX8SL7DDLCTL_DXDDLLDT_SHIFT (25U)
39265/*! DXDDLLDT - DX DDL Load Type
39266 */
39267#define DDRPHY_DX8SL7DDLCTL_DXDDLLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL7DDLCTL_DXDDLLDT_MASK)
39268#define DDRPHY_DX8SL7DDLCTL_DLYLDTM_MASK (0x4000000U)
39269#define DDRPHY_DX8SL7DDLCTL_DLYLDTM_SHIFT (26U)
39270/*! DLYLDTM - Delay Load Timing
39271 */
39272#define DDRPHY_DX8SL7DDLCTL_DLYLDTM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL7DDLCTL_DLYLDTM_MASK)
39273#define DDRPHY_DX8SL7DDLCTL_RESERVED_31_27_MASK (0xF8000000U)
39274#define DDRPHY_DX8SL7DDLCTL_RESERVED_31_27_SHIFT (27U)
39275/*! RESERVED_31_27 - Reserved. Return zeroes on reads.
39276 */
39277#define DDRPHY_DX8SL7DDLCTL_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL7DDLCTL_RESERVED_31_27_MASK)
39278/*! @} */
39279
39280/*! @name DX8SL7DXCTL1 - DATX8 0-1 DX Control Register 1 */
39281/*! @{ */
39282#define DDRPHY_DX8SL7DXCTL1_RESERVED_15_0_MASK (0xFFFFU)
39283#define DDRPHY_DX8SL7DXCTL1_RESERVED_15_0_SHIFT (0U)
39284/*! RESERVED_15_0 - Reserved. Return zeroes on reads.
39285 */
39286#define DDRPHY_DX8SL7DXCTL1_RESERVED_15_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL7DXCTL1_RESERVED_15_0_MASK)
39287#define DDRPHY_DX8SL7DXCTL1_DXTMODE_MASK (0x10000U)
39288#define DDRPHY_DX8SL7DXCTL1_DXTMODE_SHIFT (16U)
39289/*! DXTMODE - DATX8 Test Mode
39290 */
39291#define DDRPHY_DX8SL7DXCTL1_DXTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXTMODE_MASK)
39292#define DDRPHY_DX8SL7DXCTL1_DXGDBYP_MASK (0x20000U)
39293#define DDRPHY_DX8SL7DXCTL1_DXGDBYP_SHIFT (17U)
39294/*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode
39295 */
39296#define DDRPHY_DX8SL7DXCTL1_DXGDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXGDBYP_MASK)
39297#define DDRPHY_DX8SL7DXCTL1_DXQSDBYP_MASK (0x40000U)
39298#define DDRPHY_DX8SL7DXCTL1_DXQSDBYP_SHIFT (18U)
39299/*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode
39300 */
39301#define DDRPHY_DX8SL7DXCTL1_DXQSDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXQSDBYP_MASK)
39302#define DDRPHY_DX8SL7DXCTL1_DXGSMD_MASK (0x80000U)
39303#define DDRPHY_DX8SL7DXCTL1_DXGSMD_SHIFT (19U)
39304/*! DXGSMD - Read DQS Gating Status Mode
39305 */
39306#define DDRPHY_DX8SL7DXCTL1_DXGSMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXGSMD_MASK)
39307#define DDRPHY_DX8SL7DXCTL1_DXDTOSEL_MASK (0x300000U)
39308#define DDRPHY_DX8SL7DXCTL1_DXDTOSEL_SHIFT (20U)
39309/*! DXDTOSEL - DATX8 Digital Test Output Select
39310 */
39311#define DDRPHY_DX8SL7DXCTL1_DXDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXDTOSEL_MASK)
39312#define DDRPHY_DX8SL7DXCTL1_RESERVED_22_MASK (0x400000U)
39313#define DDRPHY_DX8SL7DXCTL1_RESERVED_22_SHIFT (22U)
39314/*! RESERVED_22 - Reserved. Return zeroes on reads.
39315 */
39316#define DDRPHY_DX8SL7DXCTL1_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL7DXCTL1_RESERVED_22_MASK)
39317#define DDRPHY_DX8SL7DXCTL1_DXRCLKMD_MASK (0x800000U)
39318#define DDRPHY_DX8SL7DXCTL1_DXRCLKMD_SHIFT (23U)
39319/*! DXRCLKMD - DATX8 Read Clock Mode
39320 */
39321#define DDRPHY_DX8SL7DXCTL1_DXRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXRCLKMD_MASK)
39322#define DDRPHY_DX8SL7DXCTL1_DXCALCLK_MASK (0x1000000U)
39323#define DDRPHY_DX8SL7DXCTL1_DXCALCLK_SHIFT (24U)
39324/*! DXCALCLK - DATX Calibration Clock Select
39325 */
39326#define DDRPHY_DX8SL7DXCTL1_DXCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL7DXCTL1_DXCALCLK_MASK)
39327#define DDRPHY_DX8SL7DXCTL1_RESERVED_31_25_MASK (0xFE000000U)
39328#define DDRPHY_DX8SL7DXCTL1_RESERVED_31_25_SHIFT (25U)
39329/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
39330 */
39331#define DDRPHY_DX8SL7DXCTL1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL7DXCTL1_RESERVED_31_25_MASK)
39332/*! @} */
39333
39334/*! @name DX8SL7DXCTL2 - DATX8 0-1 DX Control Register 2 */
39335/*! @{ */
39336#define DDRPHY_DX8SL7DXCTL2_RESERVED_0_MASK (0x1U)
39337#define DDRPHY_DX8SL7DXCTL2_RESERVED_0_SHIFT (0U)
39338/*! RESERVED_0 - Reserved. Return zeroes on reads.
39339 */
39340#define DDRPHY_DX8SL7DXCTL2_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL7DXCTL2_RESERVED_0_MASK)
39341#define DDRPHY_DX8SL7DXCTL2_DQSGLB_MASK (0x6U)
39342#define DDRPHY_DX8SL7DXCTL2_DQSGLB_SHIFT (1U)
39343/*! DQSGLB - Read DQS Gate I/O Loopback
39344 */
39345#define DDRPHY_DX8SL7DXCTL2_DQSGLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL7DXCTL2_DQSGLB_MASK)
39346#define DDRPHY_DX8SL7DXCTL2_DISRST_MASK (0x8U)
39347#define DDRPHY_DX8SL7DXCTL2_DISRST_SHIFT (3U)
39348/*! DISRST - Disables the Read FIFO Reset
39349 */
39350#define DDRPHY_DX8SL7DXCTL2_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL7DXCTL2_DISRST_MASK)
39351#define DDRPHY_DX8SL7DXCTL2_RDMODE_MASK (0x30U)
39352#define DDRPHY_DX8SL7DXCTL2_RDMODE_SHIFT (4U)
39353/*! RDMODE - DATX8 Receive FIFO Read Mode
39354 */
39355#define DDRPHY_DX8SL7DXCTL2_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL7DXCTL2_RDMODE_MASK)
39356#define DDRPHY_DX8SL7DXCTL2_PRFBYP_MASK (0x40U)
39357#define DDRPHY_DX8SL7DXCTL2_PRFBYP_SHIFT (6U)
39358/*! PRFBYP - PUB Read FIFO Bypass
39359 */
39360#define DDRPHY_DX8SL7DXCTL2_PRFBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL7DXCTL2_PRFBYP_MASK)
39361#define DDRPHY_DX8SL7DXCTL2_WDBI_MASK (0x80U)
39362#define DDRPHY_DX8SL7DXCTL2_WDBI_SHIFT (7U)
39363/*! WDBI - Write Data Bus Inversion Enable
39364 */
39365#define DDRPHY_DX8SL7DXCTL2_WDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL7DXCTL2_WDBI_MASK)
39366#define DDRPHY_DX8SL7DXCTL2_RDBI_MASK (0x100U)
39367#define DDRPHY_DX8SL7DXCTL2_RDBI_SHIFT (8U)
39368/*! RDBI - Read Data Bus Inversion Enable
39369 */
39370#define DDRPHY_DX8SL7DXCTL2_RDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL7DXCTL2_RDBI_MASK)
39371#define DDRPHY_DX8SL7DXCTL2_LPWAKEUP_THRSH_MASK (0x1E00U)
39372#define DDRPHY_DX8SL7DXCTL2_LPWAKEUP_THRSH_SHIFT (9U)
39373/*! LPWAKEUP_THRSH - Low Power Wakeup Threshold
39374 */
39375#define DDRPHY_DX8SL7DXCTL2_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL7DXCTL2_LPWAKEUP_THRSH_MASK)
39376#define DDRPHY_DX8SL7DXCTL2_RESERVED_14_13_MASK (0x6000U)
39377#define DDRPHY_DX8SL7DXCTL2_RESERVED_14_13_SHIFT (13U)
39378/*! RESERVED_14_13 - Reserved. Return zeroes on reads.
39379 */
39380#define DDRPHY_DX8SL7DXCTL2_RESERVED_14_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL7DXCTL2_RESERVED_14_13_MASK)
39381#define DDRPHY_DX8SL7DXCTL2_IOLB_MASK (0x8000U)
39382#define DDRPHY_DX8SL7DXCTL2_IOLB_SHIFT (15U)
39383/*! IOLB - I/O Loopback Select
39384 */
39385#define DDRPHY_DX8SL7DXCTL2_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL7DXCTL2_IOLB_MASK)
39386#define DDRPHY_DX8SL7DXCTL2_IOAG_MASK (0x10000U)
39387#define DDRPHY_DX8SL7DXCTL2_IOAG_SHIFT (16U)
39388/*! IOAG - I/O Assisted Gate Select
39389 */
39390#define DDRPHY_DX8SL7DXCTL2_IOAG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL7DXCTL2_IOAG_MASK)
39391#define DDRPHY_DX8SL7DXCTL2_RESERVED_17_MASK (0x20000U)
39392#define DDRPHY_DX8SL7DXCTL2_RESERVED_17_SHIFT (17U)
39393/*! RESERVED_17 - Reserved. Return zeroes on reads.
39394 */
39395#define DDRPHY_DX8SL7DXCTL2_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL7DXCTL2_RESERVED_17_MASK)
39396#define DDRPHY_DX8SL7DXCTL2_PREOEX_MASK (0xC0000U)
39397#define DDRPHY_DX8SL7DXCTL2_PREOEX_SHIFT (18U)
39398/*! PREOEX - OE Extension during Pre-amble
39399 */
39400#define DDRPHY_DX8SL7DXCTL2_PREOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL7DXCTL2_PREOEX_MASK)
39401#define DDRPHY_DX8SL7DXCTL2_POSOEX_MASK (0x700000U)
39402#define DDRPHY_DX8SL7DXCTL2_POSOEX_SHIFT (20U)
39403/*! POSOEX - OX Extension during Post-amble
39404 */
39405#define DDRPHY_DX8SL7DXCTL2_POSOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL7DXCTL2_POSOEX_MASK)
39406#define DDRPHY_DX8SL7DXCTL2_CRDEN_MASK (0x800000U)
39407#define DDRPHY_DX8SL7DXCTL2_CRDEN_SHIFT (23U)
39408/*! CRDEN - Configurable Read Data Enable
39409 */
39410#define DDRPHY_DX8SL7DXCTL2_CRDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL7DXCTL2_CRDEN_MASK)
39411#define DDRPHY_DX8SL7DXCTL2_RESERVED_31_24_MASK (0xFF000000U)
39412#define DDRPHY_DX8SL7DXCTL2_RESERVED_31_24_SHIFT (24U)
39413/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
39414 */
39415#define DDRPHY_DX8SL7DXCTL2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL7DXCTL2_RESERVED_31_24_MASK)
39416/*! @} */
39417
39418/*! @name DX8SL7IOCR - DATX8 0-1 I/O Configuration Register */
39419/*! @{ */
39420#define DDRPHY_DX8SL7IOCR_DXRXM_MASK (0x7FFU)
39421#define DDRPHY_DX8SL7IOCR_DXRXM_SHIFT (0U)
39422/*! DXRXM - DX IO Receiver Mode
39423 */
39424#define DDRPHY_DX8SL7IOCR_DXRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL7IOCR_DXRXM_MASK)
39425#define DDRPHY_DX8SL7IOCR_DXTXM_MASK (0x3FF800U)
39426#define DDRPHY_DX8SL7IOCR_DXTXM_SHIFT (11U)
39427/*! DXTXM - DX IO Transmitter Mode
39428 */
39429#define DDRPHY_DX8SL7IOCR_DXTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL7IOCR_DXTXM_MASK)
39430#define DDRPHY_DX8SL7IOCR_DXIOM_MASK (0x1C00000U)
39431#define DDRPHY_DX8SL7IOCR_DXIOM_SHIFT (22U)
39432/*! DXIOM - DX IO Mode
39433 */
39434#define DDRPHY_DX8SL7IOCR_DXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL7IOCR_DXIOM_MASK)
39435#define DDRPHY_DX8SL7IOCR_DXVREFIOM_MASK (0xE000000U)
39436#define DDRPHY_DX8SL7IOCR_DXVREFIOM_SHIFT (25U)
39437/*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
39438 */
39439#define DDRPHY_DX8SL7IOCR_DXVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL7IOCR_DXVREFIOM_MASK)
39440#define DDRPHY_DX8SL7IOCR_DXDACRANGE_MASK (0x70000000U)
39441#define DDRPHY_DX8SL7IOCR_DXDACRANGE_SHIFT (28U)
39442/*! DXDACRANGE - PVREF_DAC REFSEL range select
39443 */
39444#define DDRPHY_DX8SL7IOCR_DXDACRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL7IOCR_DXDACRANGE_MASK)
39445#define DDRPHY_DX8SL7IOCR_RESERVED_31_MASK (0x80000000U)
39446#define DDRPHY_DX8SL7IOCR_RESERVED_31_SHIFT (31U)
39447/*! RESERVED_31 - Reserved. Return zeroes on reads.
39448 */
39449#define DDRPHY_DX8SL7IOCR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL7IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL7IOCR_RESERVED_31_MASK)
39450/*! @} */
39451
39452/*! @name DX4SL7IOCR - DATX4 Slice 0-1 I/O Configuration Register */
39453/*! @{ */
39454#define DDRPHY_DX4SL7IOCR_RESERVED_31_0_MASK (0xFFFFFFFFU)
39455#define DDRPHY_DX4SL7IOCR_RESERVED_31_0_SHIFT (0U)
39456/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
39457 */
39458#define DDRPHY_DX4SL7IOCR_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL7IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL7IOCR_RESERVED_31_0_MASK)
39459/*! @} */
39460
39461/*! @name DX8SL8OSC - DATX8 0-1 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */
39462/*! @{ */
39463#define DDRPHY_DX8SL8OSC_OSCEN_MASK (0x1U)
39464#define DDRPHY_DX8SL8OSC_OSCEN_SHIFT (0U)
39465/*! OSCEN - Oscillator Enable
39466 */
39467#define DDRPHY_DX8SL8OSC_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_OSCEN_SHIFT)) & DDRPHY_DX8SL8OSC_OSCEN_MASK)
39468#define DDRPHY_DX8SL8OSC_OSCDIV_MASK (0x1EU)
39469#define DDRPHY_DX8SL8OSC_OSCDIV_SHIFT (1U)
39470/*! OSCDIV - Oscillator Mode Division
39471 */
39472#define DDRPHY_DX8SL8OSC_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_OSCDIV_SHIFT)) & DDRPHY_DX8SL8OSC_OSCDIV_MASK)
39473#define DDRPHY_DX8SL8OSC_OSCWDL_MASK (0x60U)
39474#define DDRPHY_DX8SL8OSC_OSCWDL_SHIFT (5U)
39475/*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select
39476 */
39477#define DDRPHY_DX8SL8OSC_OSCWDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_OSCWDL_SHIFT)) & DDRPHY_DX8SL8OSC_OSCWDL_MASK)
39478#define DDRPHY_DX8SL8OSC_RESERVED_8_7_MASK (0x180U)
39479#define DDRPHY_DX8SL8OSC_RESERVED_8_7_SHIFT (7U)
39480/*! RESERVED_8_7 - Reserved. Caution, do not write to this register field.
39481 */
39482#define DDRPHY_DX8SL8OSC_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SL8OSC_RESERVED_8_7_MASK)
39483#define DDRPHY_DX8SL8OSC_OSCWDDL_MASK (0x600U)
39484#define DDRPHY_DX8SL8OSC_OSCWDDL_SHIFT (9U)
39485/*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select
39486 */
39487#define DDRPHY_DX8SL8OSC_OSCWDDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SL8OSC_OSCWDDL_MASK)
39488#define DDRPHY_DX8SL8OSC_RESERVED_12_11_MASK (0x1800U)
39489#define DDRPHY_DX8SL8OSC_RESERVED_12_11_SHIFT (11U)
39490/*! RESERVED_12_11 - Reserved. Caution, do not write to this register field.
39491 */
39492#define DDRPHY_DX8SL8OSC_RESERVED_12_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SL8OSC_RESERVED_12_11_MASK)
39493#define DDRPHY_DX8SL8OSC_DLTMODE_MASK (0x2000U)
39494#define DDRPHY_DX8SL8OSC_DLTMODE_SHIFT (13U)
39495/*! DLTMODE - Delay Line Test Mode
39496 */
39497#define DDRPHY_DX8SL8OSC_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_DLTMODE_SHIFT)) & DDRPHY_DX8SL8OSC_DLTMODE_MASK)
39498#define DDRPHY_DX8SL8OSC_DLTST_MASK (0x4000U)
39499#define DDRPHY_DX8SL8OSC_DLTST_SHIFT (14U)
39500/*! DLTST - Delay Line Test Start
39501 */
39502#define DDRPHY_DX8SL8OSC_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_DLTST_SHIFT)) & DDRPHY_DX8SL8OSC_DLTST_MASK)
39503#define DDRPHY_DX8SL8OSC_PHYFRST_MASK (0x8000U)
39504#define DDRPHY_DX8SL8OSC_PHYFRST_SHIFT (15U)
39505/*! PHYFRST - PHY FIFO Reset
39506 */
39507#define DDRPHY_DX8SL8OSC_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_PHYFRST_SHIFT)) & DDRPHY_DX8SL8OSC_PHYFRST_MASK)
39508#define DDRPHY_DX8SL8OSC_PHYHRST_MASK (0x10000U)
39509#define DDRPHY_DX8SL8OSC_PHYHRST_SHIFT (16U)
39510/*! PHYHRST - PHY High-Speed Reset
39511 */
39512#define DDRPHY_DX8SL8OSC_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_PHYHRST_SHIFT)) & DDRPHY_DX8SL8OSC_PHYHRST_MASK)
39513#define DDRPHY_DX8SL8OSC_LBDQSS_MASK (0x20000U)
39514#define DDRPHY_DX8SL8OSC_LBDQSS_SHIFT (17U)
39515/*! LBDQSS - Loopback DQS Shift
39516 */
39517#define DDRPHY_DX8SL8OSC_LBDQSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_LBDQSS_SHIFT)) & DDRPHY_DX8SL8OSC_LBDQSS_MASK)
39518#define DDRPHY_DX8SL8OSC_LBGDQS_MASK (0xC0000U)
39519#define DDRPHY_DX8SL8OSC_LBGDQS_SHIFT (18U)
39520/*! LBGDQS - Loopback DQS Gating
39521 */
39522#define DDRPHY_DX8SL8OSC_LBGDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_LBGDQS_SHIFT)) & DDRPHY_DX8SL8OSC_LBGDQS_MASK)
39523#define DDRPHY_DX8SL8OSC_LBGSDQS_MASK (0x100000U)
39524#define DDRPHY_DX8SL8OSC_LBGSDQS_SHIFT (20U)
39525/*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
39526 */
39527#define DDRPHY_DX8SL8OSC_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SL8OSC_LBGSDQS_MASK)
39528#define DDRPHY_DX8SL8OSC_LBMODE_MASK (0x200000U)
39529#define DDRPHY_DX8SL8OSC_LBMODE_SHIFT (21U)
39530/*! LBMODE - Loopback Mode
39531 */
39532#define DDRPHY_DX8SL8OSC_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_LBMODE_SHIFT)) & DDRPHY_DX8SL8OSC_LBMODE_MASK)
39533#define DDRPHY_DX8SL8OSC_CLKLEVEL_MASK (0xC00000U)
39534#define DDRPHY_DX8SL8OSC_CLKLEVEL_SHIFT (22U)
39535/*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled.
39536 */
39537#define DDRPHY_DX8SL8OSC_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SL8OSC_CLKLEVEL_MASK)
39538#define DDRPHY_DX8SL8OSC_GATEDXCTLCLK_MASK (0x3000000U)
39539#define DDRPHY_DX8SL8OSC_GATEDXCTLCLK_SHIFT (24U)
39540/*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk
39541 */
39542#define DDRPHY_DX8SL8OSC_GATEDXCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SL8OSC_GATEDXCTLCLK_MASK)
39543#define DDRPHY_DX8SL8OSC_GATEDXDDRCLK_MASK (0xC000000U)
39544#define DDRPHY_DX8SL8OSC_GATEDXDDRCLK_SHIFT (26U)
39545/*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk
39546 */
39547#define DDRPHY_DX8SL8OSC_GATEDXDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SL8OSC_GATEDXDDRCLK_MASK)
39548#define DDRPHY_DX8SL8OSC_GATEDXRDCLK_MASK (0x30000000U)
39549#define DDRPHY_DX8SL8OSC_GATEDXRDCLK_SHIFT (28U)
39550/*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk
39551 */
39552#define DDRPHY_DX8SL8OSC_GATEDXRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SL8OSC_GATEDXRDCLK_MASK)
39553#define DDRPHY_DX8SL8OSC_RESERVED_31_30_MASK (0xC0000000U)
39554#define DDRPHY_DX8SL8OSC_RESERVED_31_30_SHIFT (30U)
39555/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
39556 */
39557#define DDRPHY_DX8SL8OSC_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8OSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SL8OSC_RESERVED_31_30_MASK)
39558/*! @} */
39559
39560/*! @name DX8SL8PLLCR0 - DAXT8 0-1 PLL Control Register 0 */
39561/*! @{ */
39562#define DDRPHY_DX8SL8PLLCR0_DTC_MASK (0xFU)
39563#define DDRPHY_DX8SL8PLLCR0_DTC_SHIFT (0U)
39564/*! DTC - Digital Test Control
39565 */
39566#define DDRPHY_DX8SL8PLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_DTC_SHIFT)) & DDRPHY_DX8SL8PLLCR0_DTC_MASK)
39567#define DDRPHY_DX8SL8PLLCR0_ATC_MASK (0xF0U)
39568#define DDRPHY_DX8SL8PLLCR0_ATC_SHIFT (4U)
39569/*! ATC - Analog Test Control
39570 */
39571#define DDRPHY_DX8SL8PLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_ATC_SHIFT)) & DDRPHY_DX8SL8PLLCR0_ATC_MASK)
39572#define DDRPHY_DX8SL8PLLCR0_ATOEN_MASK (0x100U)
39573#define DDRPHY_DX8SL8PLLCR0_ATOEN_SHIFT (8U)
39574/*! ATOEN - Analog Test Enable (ATOEN)
39575 */
39576#define DDRPHY_DX8SL8PLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SL8PLLCR0_ATOEN_MASK)
39577#define DDRPHY_DX8SL8PLLCR0_RESERVED_11_9_MASK (0xE00U)
39578#define DDRPHY_DX8SL8PLLCR0_RESERVED_11_9_SHIFT (9U)
39579/*! RESERVED_11_9 - Reserved. Return zeroes on reads.
39580 */
39581#define DDRPHY_DX8SL8PLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SL8PLLCR0_RESERVED_11_9_MASK)
39582#define DDRPHY_DX8SL8PLLCR0_GSHIFT_MASK (0x1000U)
39583#define DDRPHY_DX8SL8PLLCR0_GSHIFT_SHIFT (12U)
39584/*! GSHIFT - Gear Shift
39585 */
39586#define DDRPHY_DX8SL8PLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SL8PLLCR0_GSHIFT_MASK)
39587#define DDRPHY_DX8SL8PLLCR0_CPIC_MASK (0x1E000U)
39588#define DDRPHY_DX8SL8PLLCR0_CPIC_SHIFT (13U)
39589/*! CPIC - Charge Pump Integrating Current Control
39590 */
39591#define DDRPHY_DX8SL8PLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SL8PLLCR0_CPIC_MASK)
39592#define DDRPHY_DX8SL8PLLCR0_CPPC_MASK (0x7E0000U)
39593#define DDRPHY_DX8SL8PLLCR0_CPPC_SHIFT (17U)
39594/*! CPPC - Charge Pump Proportional Current Control
39595 */
39596#define DDRPHY_DX8SL8PLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SL8PLLCR0_CPPC_MASK)
39597#define DDRPHY_DX8SL8PLLCR0_RLOCKM_MASK (0x800000U)
39598#define DDRPHY_DX8SL8PLLCR0_RLOCKM_SHIFT (23U)
39599/*! RLOCKM - Relock Mode
39600 */
39601#define DDRPHY_DX8SL8PLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SL8PLLCR0_RLOCKM_MASK)
39602#define DDRPHY_DX8SL8PLLCR0_FRQSEL_MASK (0xF000000U)
39603#define DDRPHY_DX8SL8PLLCR0_FRQSEL_SHIFT (24U)
39604/*! FRQSEL - PLL Frequency Select
39605 */
39606#define DDRPHY_DX8SL8PLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SL8PLLCR0_FRQSEL_MASK)
39607#define DDRPHY_DX8SL8PLLCR0_RSTOPM_MASK (0x10000000U)
39608#define DDRPHY_DX8SL8PLLCR0_RSTOPM_SHIFT (28U)
39609/*! RSTOPM - Reference Stop Mode
39610 */
39611#define DDRPHY_DX8SL8PLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SL8PLLCR0_RSTOPM_MASK)
39612#define DDRPHY_DX8SL8PLLCR0_PLLPD_MASK (0x20000000U)
39613#define DDRPHY_DX8SL8PLLCR0_PLLPD_SHIFT (29U)
39614/*! PLLPD - PLL Power Down
39615 */
39616#define DDRPHY_DX8SL8PLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SL8PLLCR0_PLLPD_MASK)
39617#define DDRPHY_DX8SL8PLLCR0_PLLRST_MASK (0x40000000U)
39618#define DDRPHY_DX8SL8PLLCR0_PLLRST_SHIFT (30U)
39619/*! PLLRST - PLL Reset
39620 */
39621#define DDRPHY_DX8SL8PLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SL8PLLCR0_PLLRST_MASK)
39622#define DDRPHY_DX8SL8PLLCR0_PLLBYP_MASK (0x80000000U)
39623#define DDRPHY_DX8SL8PLLCR0_PLLBYP_SHIFT (31U)
39624/*! PLLBYP - PLL Bypass
39625 */
39626#define DDRPHY_DX8SL8PLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SL8PLLCR0_PLLBYP_MASK)
39627/*! @} */
39628
39629/*! @name DX8SL8PLLCR1 - DAXT8 0-1 PLL Control Register 1 (Type B PLL Only) */
39630/*! @{ */
39631#define DDRPHY_DX8SL8PLLCR1_LOCKDS_MASK (0x1U)
39632#define DDRPHY_DX8SL8PLLCR1_LOCKDS_SHIFT (0U)
39633/*! LOCKDS - Lock Detector Select
39634 */
39635#define DDRPHY_DX8SL8PLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SL8PLLCR1_LOCKDS_MASK)
39636#define DDRPHY_DX8SL8PLLCR1_LOCKCS_MASK (0x2U)
39637#define DDRPHY_DX8SL8PLLCR1_LOCKCS_SHIFT (1U)
39638/*! LOCKCS - Lock Detector Counter Select
39639 */
39640#define DDRPHY_DX8SL8PLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SL8PLLCR1_LOCKCS_MASK)
39641#define DDRPHY_DX8SL8PLLCR1_LOCKPS_MASK (0x4U)
39642#define DDRPHY_DX8SL8PLLCR1_LOCKPS_SHIFT (2U)
39643/*! LOCKPS - Lock Detector Phase Select
39644 */
39645#define DDRPHY_DX8SL8PLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SL8PLLCR1_LOCKPS_MASK)
39646#define DDRPHY_DX8SL8PLLCR1_BYPVDD_MASK (0x8U)
39647#define DDRPHY_DX8SL8PLLCR1_BYPVDD_SHIFT (3U)
39648/*! BYPVDD - PLL VDD voltage level control
39649 */
39650#define DDRPHY_DX8SL8PLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SL8PLLCR1_BYPVDD_MASK)
39651#define DDRPHY_DX8SL8PLLCR1_BYPVREGDIG_MASK (0x10U)
39652#define DDRPHY_DX8SL8PLLCR1_BYPVREGDIG_SHIFT (4U)
39653/*! BYPVREGDIG - Bypass PLL vreg_dig
39654 */
39655#define DDRPHY_DX8SL8PLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SL8PLLCR1_BYPVREGDIG_MASK)
39656#define DDRPHY_DX8SL8PLLCR1_BYPVREGCP_MASK (0x20U)
39657#define DDRPHY_DX8SL8PLLCR1_BYPVREGCP_SHIFT (5U)
39658/*! BYPVREGCP - Bypass PLL vreg_cp
39659 */
39660#define DDRPHY_DX8SL8PLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SL8PLLCR1_BYPVREGCP_MASK)
39661#define DDRPHY_DX8SL8PLLCR1_PLLPROG_MASK (0x3FFFC0U)
39662#define DDRPHY_DX8SL8PLLCR1_PLLPROG_SHIFT (6U)
39663/*! PLLPROG - Connects to the PLL PLL_PROG bus.
39664 */
39665#define DDRPHY_DX8SL8PLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SL8PLLCR1_PLLPROG_MASK)
39666#define DDRPHY_DX8SL8PLLCR1_RESERVED_31_22_MASK (0xFFC00000U)
39667#define DDRPHY_DX8SL8PLLCR1_RESERVED_31_22_SHIFT (22U)
39668/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
39669 */
39670#define DDRPHY_DX8SL8PLLCR1_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SL8PLLCR1_RESERVED_31_22_MASK)
39671/*! @} */
39672
39673/*! @name DX8SL8PLLCR2 - DAXT8 0-1 PLL Control Register 2 (Type B PLL Only) */
39674/*! @{ */
39675#define DDRPHY_DX8SL8PLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU)
39676#define DDRPHY_DX8SL8PLLCR2_PLLCTRL_31_0_SHIFT (0U)
39677/*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
39678 */
39679#define DDRPHY_DX8SL8PLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SL8PLLCR2_PLLCTRL_31_0_MASK)
39680/*! @} */
39681
39682/*! @name DX8SL8PLLCR3 - DAXT8 0-1 PLL Control Register 3 (Type B PLL Only) */
39683/*! @{ */
39684#define DDRPHY_DX8SL8PLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU)
39685#define DDRPHY_DX8SL8PLLCR3_PLLCTRL_63_32_SHIFT (0U)
39686/*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
39687 */
39688#define DDRPHY_DX8SL8PLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SL8PLLCR3_PLLCTRL_63_32_MASK)
39689/*! @} */
39690
39691/*! @name DX8SL8PLLCR4 - DAXT8 0-1 PLL Control Register 4 (Type B PLL Only) */
39692/*! @{ */
39693#define DDRPHY_DX8SL8PLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU)
39694#define DDRPHY_DX8SL8PLLCR4_PLLCTRL_95_64_SHIFT (0U)
39695/*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
39696 */
39697#define DDRPHY_DX8SL8PLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SL8PLLCR4_PLLCTRL_95_64_MASK)
39698/*! @} */
39699
39700/*! @name DX8SL8PLLCR5 - DAXT8 0-1 PLL Control Register 5 (Type B PLL Only) */
39701/*! @{ */
39702#define DDRPHY_DX8SL8PLLCR5_PLLCTRL_103_96_MASK (0xFFU)
39703#define DDRPHY_DX8SL8PLLCR5_PLLCTRL_103_96_SHIFT (0U)
39704/*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
39705 */
39706#define DDRPHY_DX8SL8PLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SL8PLLCR5_PLLCTRL_103_96_MASK)
39707#define DDRPHY_DX8SL8PLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U)
39708#define DDRPHY_DX8SL8PLLCR5_RESERVED_31_8_SHIFT (8U)
39709/*! RESERVED_31_8 - Reserved. Return zeroes on reads.
39710 */
39711#define DDRPHY_DX8SL8PLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8PLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SL8PLLCR5_RESERVED_31_8_MASK)
39712/*! @} */
39713
39714/*! @name DX8SL8DQSCTL - DATX8 0-1 DQS Control Register */
39715/*! @{ */
39716#define DDRPHY_DX8SL8DQSCTL_DQSRES_MASK (0xFU)
39717#define DDRPHY_DX8SL8DQSCTL_DQSRES_SHIFT (0U)
39718/*! DQSRES - DQS Resistor
39719 */
39720#define DDRPHY_DX8SL8DQSCTL_DQSRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SL8DQSCTL_DQSRES_MASK)
39721#define DDRPHY_DX8SL8DQSCTL_DQSNRES_MASK (0xF0U)
39722#define DDRPHY_DX8SL8DQSCTL_DQSNRES_SHIFT (4U)
39723/*! DQSNRES - DQS_N Resistor
39724 */
39725#define DDRPHY_DX8SL8DQSCTL_DQSNRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SL8DQSCTL_DQSNRES_MASK)
39726#define DDRPHY_DX8SL8DQSCTL_DXSR_MASK (0x300U)
39727#define DDRPHY_DX8SL8DQSCTL_DXSR_SHIFT (8U)
39728/*! DXSR - Data Slew Rate
39729 */
39730#define DDRPHY_DX8SL8DQSCTL_DXSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SL8DQSCTL_DXSR_MASK)
39731#define DDRPHY_DX8SL8DQSCTL_RESERVED_12_10_MASK (0x1C00U)
39732#define DDRPHY_DX8SL8DQSCTL_RESERVED_12_10_SHIFT (10U)
39733/*! RESERVED_12_10 - Reserved. Return zeroes on reads.
39734 */
39735#define DDRPHY_DX8SL8DQSCTL_RESERVED_12_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SL8DQSCTL_RESERVED_12_10_MASK)
39736#define DDRPHY_DX8SL8DQSCTL_UDQIOM_MASK (0x2000U)
39737#define DDRPHY_DX8SL8DQSCTL_UDQIOM_SHIFT (13U)
39738/*! UDQIOM - Unused DQ I/O Mode
39739 */
39740#define DDRPHY_DX8SL8DQSCTL_UDQIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SL8DQSCTL_UDQIOM_MASK)
39741#define DDRPHY_DX8SL8DQSCTL_QSCNTEN_MASK (0x4000U)
39742#define DDRPHY_DX8SL8DQSCTL_QSCNTEN_SHIFT (14U)
39743/*! QSCNTEN - QS Counter Enable
39744 */
39745#define DDRPHY_DX8SL8DQSCTL_QSCNTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SL8DQSCTL_QSCNTEN_MASK)
39746#define DDRPHY_DX8SL8DQSCTL_RESERVED_16_15_MASK (0x18000U)
39747#define DDRPHY_DX8SL8DQSCTL_RESERVED_16_15_SHIFT (15U)
39748/*! RESERVED_16_15 - Reserved. Return zeroes on reads.
39749 */
39750#define DDRPHY_DX8SL8DQSCTL_RESERVED_16_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SL8DQSCTL_RESERVED_16_15_MASK)
39751#define DDRPHY_DX8SL8DQSCTL_LPIOPD_MASK (0x20000U)
39752#define DDRPHY_DX8SL8DQSCTL_LPIOPD_SHIFT (17U)
39753/*! LPIOPD - Low Power I/O Power Down
39754 */
39755#define DDRPHY_DX8SL8DQSCTL_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SL8DQSCTL_LPIOPD_MASK)
39756#define DDRPHY_DX8SL8DQSCTL_LPPLLPD_MASK (0x40000U)
39757#define DDRPHY_DX8SL8DQSCTL_LPPLLPD_SHIFT (18U)
39758/*! LPPLLPD - Low Power PLL Power Down
39759 */
39760#define DDRPHY_DX8SL8DQSCTL_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SL8DQSCTL_LPPLLPD_MASK)
39761#define DDRPHY_DX8SL8DQSCTL_DQSGX_MASK (0x180000U)
39762#define DDRPHY_DX8SL8DQSCTL_DQSGX_SHIFT (19U)
39763/*! DQSGX - DQS Gate Extension
39764 */
39765#define DDRPHY_DX8SL8DQSCTL_DQSGX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SL8DQSCTL_DQSGX_MASK)
39766#define DDRPHY_DX8SL8DQSCTL_WRRMODE_MASK (0x200000U)
39767#define DDRPHY_DX8SL8DQSCTL_WRRMODE_SHIFT (21U)
39768/*! WRRMODE - Write Path Rise-to-Rise Mode
39769 */
39770#define DDRPHY_DX8SL8DQSCTL_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SL8DQSCTL_WRRMODE_MASK)
39771#define DDRPHY_DX8SL8DQSCTL_RESERVED_23_22_MASK (0xC00000U)
39772#define DDRPHY_DX8SL8DQSCTL_RESERVED_23_22_SHIFT (22U)
39773/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
39774 */
39775#define DDRPHY_DX8SL8DQSCTL_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SL8DQSCTL_RESERVED_23_22_MASK)
39776#define DDRPHY_DX8SL8DQSCTL_RRRMODE_MASK (0x1000000U)
39777#define DDRPHY_DX8SL8DQSCTL_RRRMODE_SHIFT (24U)
39778/*! RRRMODE - Read Path Rise-to-Rise Mode
39779 */
39780#define DDRPHY_DX8SL8DQSCTL_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SL8DQSCTL_RRRMODE_MASK)
39781#define DDRPHY_DX8SL8DQSCTL_RESERVED_31_25_MASK (0xFE000000U)
39782#define DDRPHY_DX8SL8DQSCTL_RESERVED_31_25_SHIFT (25U)
39783/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
39784 */
39785#define DDRPHY_DX8SL8DQSCTL_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL8DQSCTL_RESERVED_31_25_MASK)
39786/*! @} */
39787
39788/*! @name DX8SL8TRNCTL - DATX8 0-1 Training Control Register */
39789/*! @{ */
39790#define DDRPHY_DX8SL8TRNCTL_RESERVED_31_0_MASK (0xFFFFFFFFU)
39791#define DDRPHY_DX8SL8TRNCTL_RESERVED_31_0_SHIFT (0U)
39792/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
39793 */
39794#define DDRPHY_DX8SL8TRNCTL_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8TRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SL8TRNCTL_RESERVED_31_0_MASK)
39795/*! @} */
39796
39797/*! @name DX8SL8DDLCTL - DATX8 0-1 DDL Control Register */
39798/*! @{ */
39799#define DDRPHY_DX8SL8DDLCTL_DDLBYPMODE_MASK (0x3U)
39800#define DDRPHY_DX8SL8DDLCTL_DDLBYPMODE_SHIFT (0U)
39801/*! DDLBYPMODE - Controls DDL Bypass Mode
39802 */
39803#define DDRPHY_DX8SL8DDLCTL_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SL8DDLCTL_DDLBYPMODE_MASK)
39804#define DDRPHY_DX8SL8DDLCTL_DXDDLBYP_MASK (0x3FFFCU)
39805#define DDRPHY_DX8SL8DDLCTL_DXDDLBYP_SHIFT (2U)
39806/*! DXDDLBYP - DATX8 DDL Bypass
39807 */
39808#define DDRPHY_DX8SL8DDLCTL_DXDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SL8DDLCTL_DXDDLBYP_MASK)
39809#define DDRPHY_DX8SL8DDLCTL_DXDDLLD_MASK (0x7C0000U)
39810#define DDRPHY_DX8SL8DDLCTL_DXDDLLD_SHIFT (18U)
39811/*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load
39812 */
39813#define DDRPHY_DX8SL8DDLCTL_DXDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SL8DDLCTL_DXDDLLD_MASK)
39814#define DDRPHY_DX8SL8DDLCTL_RESERVED_24_23_MASK (0x1800000U)
39815#define DDRPHY_DX8SL8DDLCTL_RESERVED_24_23_SHIFT (23U)
39816/*! RESERVED_24_23 - Reserved. Return zeroes on reads.
39817 */
39818#define DDRPHY_DX8SL8DDLCTL_RESERVED_24_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SL8DDLCTL_RESERVED_24_23_MASK)
39819#define DDRPHY_DX8SL8DDLCTL_DXDDLLDT_MASK (0x2000000U)
39820#define DDRPHY_DX8SL8DDLCTL_DXDDLLDT_SHIFT (25U)
39821/*! DXDDLLDT - DX DDL Load Type
39822 */
39823#define DDRPHY_DX8SL8DDLCTL_DXDDLLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SL8DDLCTL_DXDDLLDT_MASK)
39824#define DDRPHY_DX8SL8DDLCTL_DLYLDTM_MASK (0x4000000U)
39825#define DDRPHY_DX8SL8DDLCTL_DLYLDTM_SHIFT (26U)
39826/*! DLYLDTM - Delay Load Timing
39827 */
39828#define DDRPHY_DX8SL8DDLCTL_DLYLDTM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SL8DDLCTL_DLYLDTM_MASK)
39829#define DDRPHY_DX8SL8DDLCTL_RESERVED_31_27_MASK (0xF8000000U)
39830#define DDRPHY_DX8SL8DDLCTL_RESERVED_31_27_SHIFT (27U)
39831/*! RESERVED_31_27 - Reserved. Return zeroes on reads.
39832 */
39833#define DDRPHY_DX8SL8DDLCTL_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SL8DDLCTL_RESERVED_31_27_MASK)
39834/*! @} */
39835
39836/*! @name DX8SL8DXCTL1 - DATX8 0-1 DX Control Register 1 */
39837/*! @{ */
39838#define DDRPHY_DX8SL8DXCTL1_RESERVED_15_0_MASK (0xFFFFU)
39839#define DDRPHY_DX8SL8DXCTL1_RESERVED_15_0_SHIFT (0U)
39840/*! RESERVED_15_0 - Reserved. Return zeroes on reads.
39841 */
39842#define DDRPHY_DX8SL8DXCTL1_RESERVED_15_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SL8DXCTL1_RESERVED_15_0_MASK)
39843#define DDRPHY_DX8SL8DXCTL1_DXTMODE_MASK (0x10000U)
39844#define DDRPHY_DX8SL8DXCTL1_DXTMODE_SHIFT (16U)
39845/*! DXTMODE - DATX8 Test Mode
39846 */
39847#define DDRPHY_DX8SL8DXCTL1_DXTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXTMODE_MASK)
39848#define DDRPHY_DX8SL8DXCTL1_DXGDBYP_MASK (0x20000U)
39849#define DDRPHY_DX8SL8DXCTL1_DXGDBYP_SHIFT (17U)
39850/*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode
39851 */
39852#define DDRPHY_DX8SL8DXCTL1_DXGDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXGDBYP_MASK)
39853#define DDRPHY_DX8SL8DXCTL1_DXQSDBYP_MASK (0x40000U)
39854#define DDRPHY_DX8SL8DXCTL1_DXQSDBYP_SHIFT (18U)
39855/*! DXQSDBYP - Read DQS/DQS_N Delay Load Bypass Mode
39856 */
39857#define DDRPHY_DX8SL8DXCTL1_DXQSDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXQSDBYP_MASK)
39858#define DDRPHY_DX8SL8DXCTL1_DXGSMD_MASK (0x80000U)
39859#define DDRPHY_DX8SL8DXCTL1_DXGSMD_SHIFT (19U)
39860/*! DXGSMD - Read DQS Gating Status Mode
39861 */
39862#define DDRPHY_DX8SL8DXCTL1_DXGSMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXGSMD_MASK)
39863#define DDRPHY_DX8SL8DXCTL1_DXDTOSEL_MASK (0x300000U)
39864#define DDRPHY_DX8SL8DXCTL1_DXDTOSEL_SHIFT (20U)
39865/*! DXDTOSEL - DATX8 Digital Test Output Select
39866 */
39867#define DDRPHY_DX8SL8DXCTL1_DXDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXDTOSEL_MASK)
39868#define DDRPHY_DX8SL8DXCTL1_RESERVED_22_MASK (0x400000U)
39869#define DDRPHY_DX8SL8DXCTL1_RESERVED_22_SHIFT (22U)
39870/*! RESERVED_22 - Reserved. Return zeroes on reads.
39871 */
39872#define DDRPHY_DX8SL8DXCTL1_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SL8DXCTL1_RESERVED_22_MASK)
39873#define DDRPHY_DX8SL8DXCTL1_DXRCLKMD_MASK (0x800000U)
39874#define DDRPHY_DX8SL8DXCTL1_DXRCLKMD_SHIFT (23U)
39875/*! DXRCLKMD - DATX8 Read Clock Mode
39876 */
39877#define DDRPHY_DX8SL8DXCTL1_DXRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXRCLKMD_MASK)
39878#define DDRPHY_DX8SL8DXCTL1_DXCALCLK_MASK (0x1000000U)
39879#define DDRPHY_DX8SL8DXCTL1_DXCALCLK_SHIFT (24U)
39880/*! DXCALCLK - DATX Calibration Clock Select
39881 */
39882#define DDRPHY_DX8SL8DXCTL1_DXCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SL8DXCTL1_DXCALCLK_MASK)
39883#define DDRPHY_DX8SL8DXCTL1_RESERVED_31_25_MASK (0xFE000000U)
39884#define DDRPHY_DX8SL8DXCTL1_RESERVED_31_25_SHIFT (25U)
39885/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
39886 */
39887#define DDRPHY_DX8SL8DXCTL1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SL8DXCTL1_RESERVED_31_25_MASK)
39888/*! @} */
39889
39890/*! @name DX8SL8DXCTL2 - DATX8 0-1 DX Control Register 2 */
39891/*! @{ */
39892#define DDRPHY_DX8SL8DXCTL2_RESERVED_0_MASK (0x1U)
39893#define DDRPHY_DX8SL8DXCTL2_RESERVED_0_SHIFT (0U)
39894/*! RESERVED_0 - Reserved. Return zeroes on reads.
39895 */
39896#define DDRPHY_DX8SL8DXCTL2_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SL8DXCTL2_RESERVED_0_MASK)
39897#define DDRPHY_DX8SL8DXCTL2_DQSGLB_MASK (0x6U)
39898#define DDRPHY_DX8SL8DXCTL2_DQSGLB_SHIFT (1U)
39899/*! DQSGLB - Read DQS Gate I/O Loopback
39900 */
39901#define DDRPHY_DX8SL8DXCTL2_DQSGLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SL8DXCTL2_DQSGLB_MASK)
39902#define DDRPHY_DX8SL8DXCTL2_DISRST_MASK (0x8U)
39903#define DDRPHY_DX8SL8DXCTL2_DISRST_SHIFT (3U)
39904/*! DISRST - Disables the Read FIFO Reset
39905 */
39906#define DDRPHY_DX8SL8DXCTL2_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SL8DXCTL2_DISRST_MASK)
39907#define DDRPHY_DX8SL8DXCTL2_RDMODE_MASK (0x30U)
39908#define DDRPHY_DX8SL8DXCTL2_RDMODE_SHIFT (4U)
39909/*! RDMODE - DATX8 Receive FIFO Read Mode
39910 */
39911#define DDRPHY_DX8SL8DXCTL2_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SL8DXCTL2_RDMODE_MASK)
39912#define DDRPHY_DX8SL8DXCTL2_PRFBYP_MASK (0x40U)
39913#define DDRPHY_DX8SL8DXCTL2_PRFBYP_SHIFT (6U)
39914/*! PRFBYP - PUB Read FIFO Bypass
39915 */
39916#define DDRPHY_DX8SL8DXCTL2_PRFBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SL8DXCTL2_PRFBYP_MASK)
39917#define DDRPHY_DX8SL8DXCTL2_WDBI_MASK (0x80U)
39918#define DDRPHY_DX8SL8DXCTL2_WDBI_SHIFT (7U)
39919/*! WDBI - Write Data Bus Inversion Enable
39920 */
39921#define DDRPHY_DX8SL8DXCTL2_WDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SL8DXCTL2_WDBI_MASK)
39922#define DDRPHY_DX8SL8DXCTL2_RDBI_MASK (0x100U)
39923#define DDRPHY_DX8SL8DXCTL2_RDBI_SHIFT (8U)
39924/*! RDBI - Read Data Bus Inversion Enable
39925 */
39926#define DDRPHY_DX8SL8DXCTL2_RDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SL8DXCTL2_RDBI_MASK)
39927#define DDRPHY_DX8SL8DXCTL2_LPWAKEUP_THRSH_MASK (0x1E00U)
39928#define DDRPHY_DX8SL8DXCTL2_LPWAKEUP_THRSH_SHIFT (9U)
39929/*! LPWAKEUP_THRSH - Low Power Wakeup Threshold
39930 */
39931#define DDRPHY_DX8SL8DXCTL2_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SL8DXCTL2_LPWAKEUP_THRSH_MASK)
39932#define DDRPHY_DX8SL8DXCTL2_RESERVED_14_13_MASK (0x6000U)
39933#define DDRPHY_DX8SL8DXCTL2_RESERVED_14_13_SHIFT (13U)
39934/*! RESERVED_14_13 - Reserved. Return zeroes on reads.
39935 */
39936#define DDRPHY_DX8SL8DXCTL2_RESERVED_14_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SL8DXCTL2_RESERVED_14_13_MASK)
39937#define DDRPHY_DX8SL8DXCTL2_IOLB_MASK (0x8000U)
39938#define DDRPHY_DX8SL8DXCTL2_IOLB_SHIFT (15U)
39939/*! IOLB - I/O Loopback Select
39940 */
39941#define DDRPHY_DX8SL8DXCTL2_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SL8DXCTL2_IOLB_MASK)
39942#define DDRPHY_DX8SL8DXCTL2_IOAG_MASK (0x10000U)
39943#define DDRPHY_DX8SL8DXCTL2_IOAG_SHIFT (16U)
39944/*! IOAG - I/O Assisted Gate Select
39945 */
39946#define DDRPHY_DX8SL8DXCTL2_IOAG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SL8DXCTL2_IOAG_MASK)
39947#define DDRPHY_DX8SL8DXCTL2_RESERVED_17_MASK (0x20000U)
39948#define DDRPHY_DX8SL8DXCTL2_RESERVED_17_SHIFT (17U)
39949/*! RESERVED_17 - Reserved. Return zeroes on reads.
39950 */
39951#define DDRPHY_DX8SL8DXCTL2_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SL8DXCTL2_RESERVED_17_MASK)
39952#define DDRPHY_DX8SL8DXCTL2_PREOEX_MASK (0xC0000U)
39953#define DDRPHY_DX8SL8DXCTL2_PREOEX_SHIFT (18U)
39954/*! PREOEX - OE Extension during Pre-amble
39955 */
39956#define DDRPHY_DX8SL8DXCTL2_PREOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SL8DXCTL2_PREOEX_MASK)
39957#define DDRPHY_DX8SL8DXCTL2_POSOEX_MASK (0x700000U)
39958#define DDRPHY_DX8SL8DXCTL2_POSOEX_SHIFT (20U)
39959/*! POSOEX - OX Extension during Post-amble
39960 */
39961#define DDRPHY_DX8SL8DXCTL2_POSOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SL8DXCTL2_POSOEX_MASK)
39962#define DDRPHY_DX8SL8DXCTL2_CRDEN_MASK (0x800000U)
39963#define DDRPHY_DX8SL8DXCTL2_CRDEN_SHIFT (23U)
39964/*! CRDEN - Configurable Read Data Enable
39965 */
39966#define DDRPHY_DX8SL8DXCTL2_CRDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SL8DXCTL2_CRDEN_MASK)
39967#define DDRPHY_DX8SL8DXCTL2_RESERVED_31_24_MASK (0xFF000000U)
39968#define DDRPHY_DX8SL8DXCTL2_RESERVED_31_24_SHIFT (24U)
39969/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
39970 */
39971#define DDRPHY_DX8SL8DXCTL2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8DXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SL8DXCTL2_RESERVED_31_24_MASK)
39972/*! @} */
39973
39974/*! @name DX8SL8IOCR - DATX8 0-1 I/O Configuration Register */
39975/*! @{ */
39976#define DDRPHY_DX8SL8IOCR_DXRXM_MASK (0x7FFU)
39977#define DDRPHY_DX8SL8IOCR_DXRXM_SHIFT (0U)
39978/*! DXRXM - DX IO Receiver Mode
39979 */
39980#define DDRPHY_DX8SL8IOCR_DXRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8IOCR_DXRXM_SHIFT)) & DDRPHY_DX8SL8IOCR_DXRXM_MASK)
39981#define DDRPHY_DX8SL8IOCR_DXTXM_MASK (0x3FF800U)
39982#define DDRPHY_DX8SL8IOCR_DXTXM_SHIFT (11U)
39983/*! DXTXM - DX IO Transmitter Mode
39984 */
39985#define DDRPHY_DX8SL8IOCR_DXTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8IOCR_DXTXM_SHIFT)) & DDRPHY_DX8SL8IOCR_DXTXM_MASK)
39986#define DDRPHY_DX8SL8IOCR_DXIOM_MASK (0x1C00000U)
39987#define DDRPHY_DX8SL8IOCR_DXIOM_SHIFT (22U)
39988/*! DXIOM - DX IO Mode
39989 */
39990#define DDRPHY_DX8SL8IOCR_DXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8IOCR_DXIOM_SHIFT)) & DDRPHY_DX8SL8IOCR_DXIOM_MASK)
39991#define DDRPHY_DX8SL8IOCR_DXVREFIOM_MASK (0xE000000U)
39992#define DDRPHY_DX8SL8IOCR_DXVREFIOM_SHIFT (25U)
39993/*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
39994 */
39995#define DDRPHY_DX8SL8IOCR_DXVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8IOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SL8IOCR_DXVREFIOM_MASK)
39996#define DDRPHY_DX8SL8IOCR_DXDACRANGE_MASK (0x70000000U)
39997#define DDRPHY_DX8SL8IOCR_DXDACRANGE_SHIFT (28U)
39998/*! DXDACRANGE - PVREF_DAC REFSEL range select
39999 */
40000#define DDRPHY_DX8SL8IOCR_DXDACRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8IOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SL8IOCR_DXDACRANGE_MASK)
40001#define DDRPHY_DX8SL8IOCR_RESERVED_31_MASK (0x80000000U)
40002#define DDRPHY_DX8SL8IOCR_RESERVED_31_SHIFT (31U)
40003/*! RESERVED_31 - Reserved. Return zeroes on reads.
40004 */
40005#define DDRPHY_DX8SL8IOCR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SL8IOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SL8IOCR_RESERVED_31_MASK)
40006/*! @} */
40007
40008/*! @name DX4SL8IOCR - DATX4 Slice 0-1 I/O Configuration Register */
40009/*! @{ */
40010#define DDRPHY_DX4SL8IOCR_RESERVED_31_0_MASK (0xFFFFFFFFU)
40011#define DDRPHY_DX4SL8IOCR_RESERVED_31_0_SHIFT (0U)
40012/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
40013 */
40014#define DDRPHY_DX4SL8IOCR_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SL8IOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SL8IOCR_RESERVED_31_0_MASK)
40015/*! @} */
40016
40017/*! @name DX8SLBOSC - DATX8 0-8 Oscillator, Delay Line Test, PHY FIFO and High Speed Reset, Loopback, and Gated Clock Control Register */
40018/*! @{ */
40019#define DDRPHY_DX8SLBOSC_OSCEN_MASK (0x1U)
40020#define DDRPHY_DX8SLBOSC_OSCEN_SHIFT (0U)
40021/*! OSCEN - Oscillator Enable
40022 */
40023#define DDRPHY_DX8SLBOSC_OSCEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_OSCEN_SHIFT)) & DDRPHY_DX8SLBOSC_OSCEN_MASK)
40024#define DDRPHY_DX8SLBOSC_OSCDIV_MASK (0x1EU)
40025#define DDRPHY_DX8SLBOSC_OSCDIV_SHIFT (1U)
40026/*! OSCDIV - Oscillator Mode Division
40027 */
40028#define DDRPHY_DX8SLBOSC_OSCDIV(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_OSCDIV_SHIFT)) & DDRPHY_DX8SLBOSC_OSCDIV_MASK)
40029#define DDRPHY_DX8SLBOSC_OSCWDL_MASK (0x60U)
40030#define DDRPHY_DX8SLBOSC_OSCWDL_SHIFT (5U)
40031/*! OSCWDL - Oscillator Mode Write-Leveling Delay Line Select
40032 */
40033#define DDRPHY_DX8SLBOSC_OSCWDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_OSCWDL_SHIFT)) & DDRPHY_DX8SLBOSC_OSCWDL_MASK)
40034#define DDRPHY_DX8SLBOSC_RESERVED_8_7_MASK (0x180U)
40035#define DDRPHY_DX8SLBOSC_RESERVED_8_7_SHIFT (7U)
40036/*! RESERVED_8_7 - Reserved. Caution, do not write to this register field.
40037 */
40038#define DDRPHY_DX8SLBOSC_RESERVED_8_7(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_RESERVED_8_7_SHIFT)) & DDRPHY_DX8SLBOSC_RESERVED_8_7_MASK)
40039#define DDRPHY_DX8SLBOSC_OSCWDDL_MASK (0x600U)
40040#define DDRPHY_DX8SLBOSC_OSCWDDL_SHIFT (9U)
40041/*! OSCWDDL - Oscillator Mode Write-Data Delay Line Select
40042 */
40043#define DDRPHY_DX8SLBOSC_OSCWDDL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_OSCWDDL_SHIFT)) & DDRPHY_DX8SLBOSC_OSCWDDL_MASK)
40044#define DDRPHY_DX8SLBOSC_RESERVED_12_11_MASK (0x1800U)
40045#define DDRPHY_DX8SLBOSC_RESERVED_12_11_SHIFT (11U)
40046/*! RESERVED_12_11 - Reserved. Caution, do not write to this register field.
40047 */
40048#define DDRPHY_DX8SLBOSC_RESERVED_12_11(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_RESERVED_12_11_SHIFT)) & DDRPHY_DX8SLBOSC_RESERVED_12_11_MASK)
40049#define DDRPHY_DX8SLBOSC_DLTMODE_MASK (0x2000U)
40050#define DDRPHY_DX8SLBOSC_DLTMODE_SHIFT (13U)
40051/*! DLTMODE - Delay Line Test Mode
40052 */
40053#define DDRPHY_DX8SLBOSC_DLTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_DLTMODE_SHIFT)) & DDRPHY_DX8SLBOSC_DLTMODE_MASK)
40054#define DDRPHY_DX8SLBOSC_DLTST_MASK (0x4000U)
40055#define DDRPHY_DX8SLBOSC_DLTST_SHIFT (14U)
40056/*! DLTST - Delay Line Test Start
40057 */
40058#define DDRPHY_DX8SLBOSC_DLTST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_DLTST_SHIFT)) & DDRPHY_DX8SLBOSC_DLTST_MASK)
40059#define DDRPHY_DX8SLBOSC_PHYFRST_MASK (0x8000U)
40060#define DDRPHY_DX8SLBOSC_PHYFRST_SHIFT (15U)
40061/*! PHYFRST - PHY FIFO Reset
40062 */
40063#define DDRPHY_DX8SLBOSC_PHYFRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_PHYFRST_SHIFT)) & DDRPHY_DX8SLBOSC_PHYFRST_MASK)
40064#define DDRPHY_DX8SLBOSC_PHYHRST_MASK (0x10000U)
40065#define DDRPHY_DX8SLBOSC_PHYHRST_SHIFT (16U)
40066/*! PHYHRST - PHY High-Speed Reset
40067 */
40068#define DDRPHY_DX8SLBOSC_PHYHRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_PHYHRST_SHIFT)) & DDRPHY_DX8SLBOSC_PHYHRST_MASK)
40069#define DDRPHY_DX8SLBOSC_LBDQSS_MASK (0x20000U)
40070#define DDRPHY_DX8SLBOSC_LBDQSS_SHIFT (17U)
40071/*! LBDQSS - Loopback DQS Shift
40072 */
40073#define DDRPHY_DX8SLBOSC_LBDQSS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_LBDQSS_SHIFT)) & DDRPHY_DX8SLBOSC_LBDQSS_MASK)
40074#define DDRPHY_DX8SLBOSC_LBGDQS_MASK (0xC0000U)
40075#define DDRPHY_DX8SLBOSC_LBGDQS_SHIFT (18U)
40076/*! LBGDQS - Loopback DQS Gating
40077 */
40078#define DDRPHY_DX8SLBOSC_LBGDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_LBGDQS_SHIFT)) & DDRPHY_DX8SLBOSC_LBGDQS_MASK)
40079#define DDRPHY_DX8SLBOSC_LBGSDQS_MASK (0x100000U)
40080#define DDRPHY_DX8SLBOSC_LBGSDQS_SHIFT (20U)
40081/*! LBGSDQS - Load GSDQS LCDL with 2x the calibrated GSDQSPRD value
40082 */
40083#define DDRPHY_DX8SLBOSC_LBGSDQS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_LBGSDQS_SHIFT)) & DDRPHY_DX8SLBOSC_LBGSDQS_MASK)
40084#define DDRPHY_DX8SLBOSC_LBMODE_MASK (0x200000U)
40085#define DDRPHY_DX8SLBOSC_LBMODE_SHIFT (21U)
40086/*! LBMODE - Loopback Mode
40087 */
40088#define DDRPHY_DX8SLBOSC_LBMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_LBMODE_SHIFT)) & DDRPHY_DX8SLBOSC_LBMODE_MASK)
40089#define DDRPHY_DX8SLBOSC_CLKLEVEL_MASK (0xC00000U)
40090#define DDRPHY_DX8SLBOSC_CLKLEVEL_SHIFT (22U)
40091/*! CLKLEVEL - Selects the level to which clocks will be stalled when clock gating is enabled.
40092 */
40093#define DDRPHY_DX8SLBOSC_CLKLEVEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_CLKLEVEL_SHIFT)) & DDRPHY_DX8SLBOSC_CLKLEVEL_MASK)
40094#define DDRPHY_DX8SLBOSC_GATEDXCTLCLK_MASK (0x3000000U)
40095#define DDRPHY_DX8SLBOSC_GATEDXCTLCLK_SHIFT (24U)
40096/*! GATEDXCTLCLK - Enable Clock Gating for DX ctl_clk
40097 */
40098#define DDRPHY_DX8SLBOSC_GATEDXCTLCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_GATEDXCTLCLK_SHIFT)) & DDRPHY_DX8SLBOSC_GATEDXCTLCLK_MASK)
40099#define DDRPHY_DX8SLBOSC_GATEDXDDRCLK_MASK (0xC000000U)
40100#define DDRPHY_DX8SLBOSC_GATEDXDDRCLK_SHIFT (26U)
40101/*! GATEDXDDRCLK - Enable Clock Gating for DX ctl_rd_clk
40102 */
40103#define DDRPHY_DX8SLBOSC_GATEDXDDRCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_GATEDXDDRCLK_SHIFT)) & DDRPHY_DX8SLBOSC_GATEDXDDRCLK_MASK)
40104#define DDRPHY_DX8SLBOSC_GATEDXRDCLK_MASK (0x30000000U)
40105#define DDRPHY_DX8SLBOSC_GATEDXRDCLK_SHIFT (28U)
40106/*! GATEDXRDCLK - Enable Clock Gating for DX ddr_clk
40107 */
40108#define DDRPHY_DX8SLBOSC_GATEDXRDCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_GATEDXRDCLK_SHIFT)) & DDRPHY_DX8SLBOSC_GATEDXRDCLK_MASK)
40109#define DDRPHY_DX8SLBOSC_RESERVED_31_30_MASK (0xC0000000U)
40110#define DDRPHY_DX8SLBOSC_RESERVED_31_30_SHIFT (30U)
40111/*! RESERVED_31_30 - Reserved. Return zeroes on reads.
40112 */
40113#define DDRPHY_DX8SLBOSC_RESERVED_31_30(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBOSC_RESERVED_31_30_SHIFT)) & DDRPHY_DX8SLBOSC_RESERVED_31_30_MASK)
40114/*! @} */
40115
40116/*! @name DX8SLBPLLCR0 - DAXT8 0-8 PLL Control Register 0 */
40117/*! @{ */
40118#define DDRPHY_DX8SLBPLLCR0_DTC_MASK (0xFU)
40119#define DDRPHY_DX8SLBPLLCR0_DTC_SHIFT (0U)
40120/*! DTC - Digital Test Control
40121 */
40122#define DDRPHY_DX8SLBPLLCR0_DTC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_DTC_SHIFT)) & DDRPHY_DX8SLBPLLCR0_DTC_MASK)
40123#define DDRPHY_DX8SLBPLLCR0_ATC_MASK (0xF0U)
40124#define DDRPHY_DX8SLBPLLCR0_ATC_SHIFT (4U)
40125/*! ATC - Analog Test Control
40126 */
40127#define DDRPHY_DX8SLBPLLCR0_ATC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_ATC_SHIFT)) & DDRPHY_DX8SLBPLLCR0_ATC_MASK)
40128#define DDRPHY_DX8SLBPLLCR0_ATOEN_MASK (0x100U)
40129#define DDRPHY_DX8SLBPLLCR0_ATOEN_SHIFT (8U)
40130/*! ATOEN - Analog Test Enable (ATOEN)
40131 */
40132#define DDRPHY_DX8SLBPLLCR0_ATOEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_ATOEN_SHIFT)) & DDRPHY_DX8SLBPLLCR0_ATOEN_MASK)
40133#define DDRPHY_DX8SLBPLLCR0_RESERVED_11_9_MASK (0xE00U)
40134#define DDRPHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT (9U)
40135/*! RESERVED_11_9 - Reserved. Return zeroes on reads.
40136 */
40137#define DDRPHY_DX8SLBPLLCR0_RESERVED_11_9(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_RESERVED_11_9_SHIFT)) & DDRPHY_DX8SLBPLLCR0_RESERVED_11_9_MASK)
40138#define DDRPHY_DX8SLBPLLCR0_GSHIFT_MASK (0x1000U)
40139#define DDRPHY_DX8SLBPLLCR0_GSHIFT_SHIFT (12U)
40140/*! GSHIFT - Gear Shift
40141 */
40142#define DDRPHY_DX8SLBPLLCR0_GSHIFT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_GSHIFT_SHIFT)) & DDRPHY_DX8SLBPLLCR0_GSHIFT_MASK)
40143#define DDRPHY_DX8SLBPLLCR0_CPIC_MASK (0x1E000U)
40144#define DDRPHY_DX8SLBPLLCR0_CPIC_SHIFT (13U)
40145/*! CPIC - Charge Pump Integrating Current Control
40146 */
40147#define DDRPHY_DX8SLBPLLCR0_CPIC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_CPIC_SHIFT)) & DDRPHY_DX8SLBPLLCR0_CPIC_MASK)
40148#define DDRPHY_DX8SLBPLLCR0_CPPC_MASK (0x7E0000U)
40149#define DDRPHY_DX8SLBPLLCR0_CPPC_SHIFT (17U)
40150/*! CPPC - Charge Pump Proportional Current Control
40151 */
40152#define DDRPHY_DX8SLBPLLCR0_CPPC(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_CPPC_SHIFT)) & DDRPHY_DX8SLBPLLCR0_CPPC_MASK)
40153#define DDRPHY_DX8SLBPLLCR0_RLOCKM_MASK (0x800000U)
40154#define DDRPHY_DX8SLBPLLCR0_RLOCKM_SHIFT (23U)
40155/*! RLOCKM - Relock Mode
40156 */
40157#define DDRPHY_DX8SLBPLLCR0_RLOCKM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_RLOCKM_SHIFT)) & DDRPHY_DX8SLBPLLCR0_RLOCKM_MASK)
40158#define DDRPHY_DX8SLBPLLCR0_FRQSEL_MASK (0xF000000U)
40159#define DDRPHY_DX8SLBPLLCR0_FRQSEL_SHIFT (24U)
40160/*! FRQSEL - PLL Frequency Select
40161 */
40162#define DDRPHY_DX8SLBPLLCR0_FRQSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_FRQSEL_SHIFT)) & DDRPHY_DX8SLBPLLCR0_FRQSEL_MASK)
40163#define DDRPHY_DX8SLBPLLCR0_RSTOPM_MASK (0x10000000U)
40164#define DDRPHY_DX8SLBPLLCR0_RSTOPM_SHIFT (28U)
40165/*! RSTOPM - Reference Stop Mode
40166 */
40167#define DDRPHY_DX8SLBPLLCR0_RSTOPM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_RSTOPM_SHIFT)) & DDRPHY_DX8SLBPLLCR0_RSTOPM_MASK)
40168#define DDRPHY_DX8SLBPLLCR0_PLLPD_MASK (0x20000000U)
40169#define DDRPHY_DX8SLBPLLCR0_PLLPD_SHIFT (29U)
40170/*! PLLPD - PLL Power Down
40171 */
40172#define DDRPHY_DX8SLBPLLCR0_PLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_PLLPD_SHIFT)) & DDRPHY_DX8SLBPLLCR0_PLLPD_MASK)
40173#define DDRPHY_DX8SLBPLLCR0_PLLRST_MASK (0x40000000U)
40174#define DDRPHY_DX8SLBPLLCR0_PLLRST_SHIFT (30U)
40175/*! PLLRST - PLL Reset
40176 */
40177#define DDRPHY_DX8SLBPLLCR0_PLLRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_PLLRST_SHIFT)) & DDRPHY_DX8SLBPLLCR0_PLLRST_MASK)
40178#define DDRPHY_DX8SLBPLLCR0_PLLBYP_MASK (0x80000000U)
40179#define DDRPHY_DX8SLBPLLCR0_PLLBYP_SHIFT (31U)
40180/*! PLLBYP - PLL Bypass
40181 */
40182#define DDRPHY_DX8SLBPLLCR0_PLLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR0_PLLBYP_SHIFT)) & DDRPHY_DX8SLBPLLCR0_PLLBYP_MASK)
40183/*! @} */
40184
40185/*! @name DX8SLBPLLCR1 - DAXT8 0-8 PLL Control Register 1 (Type B PLL Only) */
40186/*! @{ */
40187#define DDRPHY_DX8SLBPLLCR1_LOCKDS_MASK (0x1U)
40188#define DDRPHY_DX8SLBPLLCR1_LOCKDS_SHIFT (0U)
40189/*! LOCKDS - Lock Detector Select
40190 */
40191#define DDRPHY_DX8SLBPLLCR1_LOCKDS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_LOCKDS_SHIFT)) & DDRPHY_DX8SLBPLLCR1_LOCKDS_MASK)
40192#define DDRPHY_DX8SLBPLLCR1_LOCKCS_MASK (0x2U)
40193#define DDRPHY_DX8SLBPLLCR1_LOCKCS_SHIFT (1U)
40194/*! LOCKCS - Lock Detector Counter Select
40195 */
40196#define DDRPHY_DX8SLBPLLCR1_LOCKCS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_LOCKCS_SHIFT)) & DDRPHY_DX8SLBPLLCR1_LOCKCS_MASK)
40197#define DDRPHY_DX8SLBPLLCR1_LOCKPS_MASK (0x4U)
40198#define DDRPHY_DX8SLBPLLCR1_LOCKPS_SHIFT (2U)
40199/*! LOCKPS - Lock Detector Phase Select
40200 */
40201#define DDRPHY_DX8SLBPLLCR1_LOCKPS(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_LOCKPS_SHIFT)) & DDRPHY_DX8SLBPLLCR1_LOCKPS_MASK)
40202#define DDRPHY_DX8SLBPLLCR1_BYPVDD_MASK (0x8U)
40203#define DDRPHY_DX8SLBPLLCR1_BYPVDD_SHIFT (3U)
40204/*! BYPVDD - PLL VDD voltage level control
40205 */
40206#define DDRPHY_DX8SLBPLLCR1_BYPVDD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_BYPVDD_SHIFT)) & DDRPHY_DX8SLBPLLCR1_BYPVDD_MASK)
40207#define DDRPHY_DX8SLBPLLCR1_BYPVREGDIG_MASK (0x10U)
40208#define DDRPHY_DX8SLBPLLCR1_BYPVREGDIG_SHIFT (4U)
40209/*! BYPVREGDIG - Bypass PLL vreg_dig
40210 */
40211#define DDRPHY_DX8SLBPLLCR1_BYPVREGDIG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_BYPVREGDIG_SHIFT)) & DDRPHY_DX8SLBPLLCR1_BYPVREGDIG_MASK)
40212#define DDRPHY_DX8SLBPLLCR1_BYPVREGCP_MASK (0x20U)
40213#define DDRPHY_DX8SLBPLLCR1_BYPVREGCP_SHIFT (5U)
40214/*! BYPVREGCP - Bypass PLL vreg_cp
40215 */
40216#define DDRPHY_DX8SLBPLLCR1_BYPVREGCP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_BYPVREGCP_SHIFT)) & DDRPHY_DX8SLBPLLCR1_BYPVREGCP_MASK)
40217#define DDRPHY_DX8SLBPLLCR1_PLLPROG_MASK (0x3FFFC0U)
40218#define DDRPHY_DX8SLBPLLCR1_PLLPROG_SHIFT (6U)
40219/*! PLLPROG - Connects to the PLL PLL_PROG bus.
40220 */
40221#define DDRPHY_DX8SLBPLLCR1_PLLPROG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_PLLPROG_SHIFT)) & DDRPHY_DX8SLBPLLCR1_PLLPROG_MASK)
40222#define DDRPHY_DX8SLBPLLCR1_RESERVED_31_22_MASK (0xFFC00000U)
40223#define DDRPHY_DX8SLBPLLCR1_RESERVED_31_22_SHIFT (22U)
40224/*! RESERVED_31_22 - Reserved. Return zeroes on reads.
40225 */
40226#define DDRPHY_DX8SLBPLLCR1_RESERVED_31_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR1_RESERVED_31_22_SHIFT)) & DDRPHY_DX8SLBPLLCR1_RESERVED_31_22_MASK)
40227/*! @} */
40228
40229/*! @name DX8SLBPLLCR2 - DAXT8 0-8 PLL Control Register 2 (Type B PLL Only) */
40230/*! @{ */
40231#define DDRPHY_DX8SLBPLLCR2_PLLCTRL_31_0_MASK (0xFFFFFFFFU)
40232#define DDRPHY_DX8SLBPLLCR2_PLLCTRL_31_0_SHIFT (0U)
40233/*! PLLCTRL_31_0 - Connectes to bits [31:0] of the PLL generatl control bus PLL_CTRL
40234 */
40235#define DDRPHY_DX8SLBPLLCR2_PLLCTRL_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR2_PLLCTRL_31_0_SHIFT)) & DDRPHY_DX8SLBPLLCR2_PLLCTRL_31_0_MASK)
40236/*! @} */
40237
40238/*! @name DX8SLBPLLCR3 - DAXT8 0-8 PLL Control Register 3 (Type B PLL Only) */
40239/*! @{ */
40240#define DDRPHY_DX8SLBPLLCR3_PLLCTRL_63_32_MASK (0xFFFFFFFFU)
40241#define DDRPHY_DX8SLBPLLCR3_PLLCTRL_63_32_SHIFT (0U)
40242/*! PLLCTRL_63_32 - Connectes to bits [63:32] of the PLL generatl control bus PLL_CTRL
40243 */
40244#define DDRPHY_DX8SLBPLLCR3_PLLCTRL_63_32(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR3_PLLCTRL_63_32_SHIFT)) & DDRPHY_DX8SLBPLLCR3_PLLCTRL_63_32_MASK)
40245/*! @} */
40246
40247/*! @name DX8SLBPLLCR4 - DAXT8 0-8 PLL Control Register 4 (Type B PLL Only) */
40248/*! @{ */
40249#define DDRPHY_DX8SLBPLLCR4_PLLCTRL_95_64_MASK (0xFFFFFFFFU)
40250#define DDRPHY_DX8SLBPLLCR4_PLLCTRL_95_64_SHIFT (0U)
40251/*! PLLCTRL_95_64 - Connectes to bits [95:64] of the PLL generatl control bus PLL_CTRL
40252 */
40253#define DDRPHY_DX8SLBPLLCR4_PLLCTRL_95_64(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR4_PLLCTRL_95_64_SHIFT)) & DDRPHY_DX8SLBPLLCR4_PLLCTRL_95_64_MASK)
40254/*! @} */
40255
40256/*! @name DX8SLBPLLCR5 - DAXT8 0-8 PLL Control Register 5 (Type B PLL Only) */
40257/*! @{ */
40258#define DDRPHY_DX8SLBPLLCR5_PLLCTRL_103_96_MASK (0xFFU)
40259#define DDRPHY_DX8SLBPLLCR5_PLLCTRL_103_96_SHIFT (0U)
40260/*! PLLCTRL_103_96 - Connectes to bits [103:96] of the PLL generatl control bus PLL_CTRL
40261 */
40262#define DDRPHY_DX8SLBPLLCR5_PLLCTRL_103_96(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR5_PLLCTRL_103_96_SHIFT)) & DDRPHY_DX8SLBPLLCR5_PLLCTRL_103_96_MASK)
40263#define DDRPHY_DX8SLBPLLCR5_RESERVED_31_8_MASK (0xFFFFFF00U)
40264#define DDRPHY_DX8SLBPLLCR5_RESERVED_31_8_SHIFT (8U)
40265/*! RESERVED_31_8 - Reserved. Return zeroes on reads.
40266 */
40267#define DDRPHY_DX8SLBPLLCR5_RESERVED_31_8(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBPLLCR5_RESERVED_31_8_SHIFT)) & DDRPHY_DX8SLBPLLCR5_RESERVED_31_8_MASK)
40268/*! @} */
40269
40270/*! @name DX8SLBDQSCTL - DATX8 0-8 DQS Control Register */
40271/*! @{ */
40272#define DDRPHY_DX8SLBDQSCTL_DQSRES_MASK (0xFU)
40273#define DDRPHY_DX8SLBDQSCTL_DQSRES_SHIFT (0U)
40274/*! DQSRES - DQS Resistor
40275 */
40276#define DDRPHY_DX8SLBDQSCTL_DQSRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_DQSRES_SHIFT)) & DDRPHY_DX8SLBDQSCTL_DQSRES_MASK)
40277#define DDRPHY_DX8SLBDQSCTL_DQSNRES_MASK (0xF0U)
40278#define DDRPHY_DX8SLBDQSCTL_DQSNRES_SHIFT (4U)
40279/*! DQSNRES - DQS# Resistor
40280 */
40281#define DDRPHY_DX8SLBDQSCTL_DQSNRES(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_DQSNRES_SHIFT)) & DDRPHY_DX8SLBDQSCTL_DQSNRES_MASK)
40282#define DDRPHY_DX8SLBDQSCTL_DXSR_MASK (0x300U)
40283#define DDRPHY_DX8SLBDQSCTL_DXSR_SHIFT (8U)
40284/*! DXSR - Data Slew Rate
40285 */
40286#define DDRPHY_DX8SLBDQSCTL_DXSR(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_DXSR_SHIFT)) & DDRPHY_DX8SLBDQSCTL_DXSR_MASK)
40287#define DDRPHY_DX8SLBDQSCTL_RESERVED_12_10_MASK (0x1C00U)
40288#define DDRPHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT (10U)
40289/*! RESERVED_12_10 - Reserved. Return zeroes on reads.
40290 */
40291#define DDRPHY_DX8SLBDQSCTL_RESERVED_12_10(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT)) & DDRPHY_DX8SLBDQSCTL_RESERVED_12_10_MASK)
40292#define DDRPHY_DX8SLBDQSCTL_UDQIOM_MASK (0x2000U)
40293#define DDRPHY_DX8SLBDQSCTL_UDQIOM_SHIFT (13U)
40294/*! UDQIOM - Unused DQ I/O Mode
40295 */
40296#define DDRPHY_DX8SLBDQSCTL_UDQIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_UDQIOM_SHIFT)) & DDRPHY_DX8SLBDQSCTL_UDQIOM_MASK)
40297#define DDRPHY_DX8SLBDQSCTL_QSCNTEN_MASK (0x4000U)
40298#define DDRPHY_DX8SLBDQSCTL_QSCNTEN_SHIFT (14U)
40299/*! QSCNTEN - QS Counter Enable
40300 */
40301#define DDRPHY_DX8SLBDQSCTL_QSCNTEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_QSCNTEN_SHIFT)) & DDRPHY_DX8SLBDQSCTL_QSCNTEN_MASK)
40302#define DDRPHY_DX8SLBDQSCTL_RESERVED_16_15_MASK (0x18000U)
40303#define DDRPHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT (15U)
40304/*! RESERVED_16_15 - Reserved. Return zeroes on reads.
40305 */
40306#define DDRPHY_DX8SLBDQSCTL_RESERVED_16_15(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT)) & DDRPHY_DX8SLBDQSCTL_RESERVED_16_15_MASK)
40307#define DDRPHY_DX8SLBDQSCTL_LPIOPD_MASK (0x20000U)
40308#define DDRPHY_DX8SLBDQSCTL_LPIOPD_SHIFT (17U)
40309/*! LPIOPD - Low Power I/O Power Down
40310 */
40311#define DDRPHY_DX8SLBDQSCTL_LPIOPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_LPIOPD_SHIFT)) & DDRPHY_DX8SLBDQSCTL_LPIOPD_MASK)
40312#define DDRPHY_DX8SLBDQSCTL_LPPLLPD_MASK (0x40000U)
40313#define DDRPHY_DX8SLBDQSCTL_LPPLLPD_SHIFT (18U)
40314/*! LPPLLPD - Low Power PLL Power Down
40315 */
40316#define DDRPHY_DX8SLBDQSCTL_LPPLLPD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_LPPLLPD_SHIFT)) & DDRPHY_DX8SLBDQSCTL_LPPLLPD_MASK)
40317#define DDRPHY_DX8SLBDQSCTL_DQSGX_MASK (0x180000U)
40318#define DDRPHY_DX8SLBDQSCTL_DQSGX_SHIFT (19U)
40319/*! DQSGX - DQS Gate Extension
40320 */
40321#define DDRPHY_DX8SLBDQSCTL_DQSGX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_DQSGX_SHIFT)) & DDRPHY_DX8SLBDQSCTL_DQSGX_MASK)
40322#define DDRPHY_DX8SLBDQSCTL_WRRMODE_MASK (0x200000U)
40323#define DDRPHY_DX8SLBDQSCTL_WRRMODE_SHIFT (21U)
40324/*! WRRMODE - Write Path Rise-to-Rise Mode
40325 */
40326#define DDRPHY_DX8SLBDQSCTL_WRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_WRRMODE_SHIFT)) & DDRPHY_DX8SLBDQSCTL_WRRMODE_MASK)
40327#define DDRPHY_DX8SLBDQSCTL_RESERVED_23_22_MASK (0xC00000U)
40328#define DDRPHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT (22U)
40329/*! RESERVED_23_22 - Reserved. Return zeroes on reads.
40330 */
40331#define DDRPHY_DX8SLBDQSCTL_RESERVED_23_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT)) & DDRPHY_DX8SLBDQSCTL_RESERVED_23_22_MASK)
40332#define DDRPHY_DX8SLBDQSCTL_RRRMODE_MASK (0x1000000U)
40333#define DDRPHY_DX8SLBDQSCTL_RRRMODE_SHIFT (24U)
40334/*! RRRMODE - Read Path Rise-to-Rise Mode
40335 */
40336#define DDRPHY_DX8SLBDQSCTL_RRRMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_RRRMODE_SHIFT)) & DDRPHY_DX8SLBDQSCTL_RRRMODE_MASK)
40337#define DDRPHY_DX8SLBDQSCTL_RESERVED_31_25_MASK (0xFE000000U)
40338#define DDRPHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT (25U)
40339/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
40340 */
40341#define DDRPHY_DX8SLBDQSCTL_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SLBDQSCTL_RESERVED_31_25_MASK)
40342/*! @} */
40343
40344/*! @name DX8SLBTRNCTL - DATX8 0-8 Training Control Register */
40345/*! @{ */
40346#define DDRPHY_DX8SLBTRNCTL_RESERVED_31_0_MASK (0xFFFFFFFFU)
40347#define DDRPHY_DX8SLBTRNCTL_RESERVED_31_0_SHIFT (0U)
40348/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
40349 */
40350#define DDRPHY_DX8SLBTRNCTL_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBTRNCTL_RESERVED_31_0_SHIFT)) & DDRPHY_DX8SLBTRNCTL_RESERVED_31_0_MASK)
40351/*! @} */
40352
40353/*! @name DX8SLBDDLCTL - DATX8 0-8 DDL Control Register */
40354/*! @{ */
40355#define DDRPHY_DX8SLBDDLCTL_DDLBYPMODE_MASK (0x3U)
40356#define DDRPHY_DX8SLBDDLCTL_DDLBYPMODE_SHIFT (0U)
40357/*! DDLBYPMODE - Controls DDL Bypass Mode
40358 */
40359#define DDRPHY_DX8SLBDDLCTL_DDLBYPMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_DDLBYPMODE_SHIFT)) & DDRPHY_DX8SLBDDLCTL_DDLBYPMODE_MASK)
40360#define DDRPHY_DX8SLBDDLCTL_DXDDLBYP_MASK (0x3FFFCU)
40361#define DDRPHY_DX8SLBDDLCTL_DXDDLBYP_SHIFT (2U)
40362/*! DXDDLBYP - DATX8 DDL Bypass
40363 */
40364#define DDRPHY_DX8SLBDDLCTL_DXDDLBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_DXDDLBYP_SHIFT)) & DDRPHY_DX8SLBDDLCTL_DXDDLBYP_MASK)
40365#define DDRPHY_DX8SLBDDLCTL_DXDDLLD_MASK (0x7C0000U)
40366#define DDRPHY_DX8SLBDDLCTL_DXDDLLD_SHIFT (18U)
40367/*! DXDDLLD - DATX8 DDL Delay Select Dymainc Load
40368 */
40369#define DDRPHY_DX8SLBDDLCTL_DXDDLLD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_DXDDLLD_SHIFT)) & DDRPHY_DX8SLBDDLCTL_DXDDLLD_MASK)
40370#define DDRPHY_DX8SLBDDLCTL_RESERVED_24_23_MASK (0x1800000U)
40371#define DDRPHY_DX8SLBDDLCTL_RESERVED_24_23_SHIFT (23U)
40372/*! RESERVED_24_23 - Reserved. Return zeroes on reads.
40373 */
40374#define DDRPHY_DX8SLBDDLCTL_RESERVED_24_23(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_RESERVED_24_23_SHIFT)) & DDRPHY_DX8SLBDDLCTL_RESERVED_24_23_MASK)
40375#define DDRPHY_DX8SLBDDLCTL_DXDDLLDT_MASK (0x2000000U)
40376#define DDRPHY_DX8SLBDDLCTL_DXDDLLDT_SHIFT (25U)
40377/*! DXDDLLDT - DX DDL Load Type
40378 */
40379#define DDRPHY_DX8SLBDDLCTL_DXDDLLDT(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_DXDDLLDT_SHIFT)) & DDRPHY_DX8SLBDDLCTL_DXDDLLDT_MASK)
40380#define DDRPHY_DX8SLBDDLCTL_DLYLDTM_MASK (0x4000000U)
40381#define DDRPHY_DX8SLBDDLCTL_DLYLDTM_SHIFT (26U)
40382/*! DLYLDTM - Delay Load Timing
40383 */
40384#define DDRPHY_DX8SLBDDLCTL_DLYLDTM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_DLYLDTM_SHIFT)) & DDRPHY_DX8SLBDDLCTL_DLYLDTM_MASK)
40385#define DDRPHY_DX8SLBDDLCTL_RESERVED_31_27_MASK (0xF8000000U)
40386#define DDRPHY_DX8SLBDDLCTL_RESERVED_31_27_SHIFT (27U)
40387/*! RESERVED_31_27 - Reserved. Return zeroes on reads.
40388 */
40389#define DDRPHY_DX8SLBDDLCTL_RESERVED_31_27(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDDLCTL_RESERVED_31_27_SHIFT)) & DDRPHY_DX8SLBDDLCTL_RESERVED_31_27_MASK)
40390/*! @} */
40391
40392/*! @name DX8SLBDXCTL1 - DATX8 0-8 DX Control Register 1 */
40393/*! @{ */
40394#define DDRPHY_DX8SLBDXCTL1_RESERVED_15_0_MASK (0xFFFFU)
40395#define DDRPHY_DX8SLBDXCTL1_RESERVED_15_0_SHIFT (0U)
40396/*! RESERVED_15_0 - Reserved. Return zeroes on reads.
40397 */
40398#define DDRPHY_DX8SLBDXCTL1_RESERVED_15_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_RESERVED_15_0_SHIFT)) & DDRPHY_DX8SLBDXCTL1_RESERVED_15_0_MASK)
40399#define DDRPHY_DX8SLBDXCTL1_DXTMODE_MASK (0x10000U)
40400#define DDRPHY_DX8SLBDXCTL1_DXTMODE_SHIFT (16U)
40401/*! DXTMODE - DATX8 Test Mode
40402 */
40403#define DDRPHY_DX8SLBDXCTL1_DXTMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXTMODE_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXTMODE_MASK)
40404#define DDRPHY_DX8SLBDXCTL1_DXGDBYP_MASK (0x20000U)
40405#define DDRPHY_DX8SLBDXCTL1_DXGDBYP_SHIFT (17U)
40406/*! DXGDBYP - Read DQS Gate Delay Load Bypass Mode
40407 */
40408#define DDRPHY_DX8SLBDXCTL1_DXGDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXGDBYP_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXGDBYP_MASK)
40409#define DDRPHY_DX8SLBDXCTL1_DXQSDBYP_MASK (0x40000U)
40410#define DDRPHY_DX8SLBDXCTL1_DXQSDBYP_SHIFT (18U)
40411/*! DXQSDBYP - Read DQS/DQS# Delay Load Bypass Mode
40412 */
40413#define DDRPHY_DX8SLBDXCTL1_DXQSDBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXQSDBYP_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXQSDBYP_MASK)
40414#define DDRPHY_DX8SLBDXCTL1_DXGSMD_MASK (0x80000U)
40415#define DDRPHY_DX8SLBDXCTL1_DXGSMD_SHIFT (19U)
40416/*! DXGSMD - Read DQS Gating Status Mode
40417 */
40418#define DDRPHY_DX8SLBDXCTL1_DXGSMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXGSMD_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXGSMD_MASK)
40419#define DDRPHY_DX8SLBDXCTL1_DXDTOSEL_MASK (0x300000U)
40420#define DDRPHY_DX8SLBDXCTL1_DXDTOSEL_SHIFT (20U)
40421/*! DXDTOSEL - DATX8 Digital Test Output Select
40422 */
40423#define DDRPHY_DX8SLBDXCTL1_DXDTOSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXDTOSEL_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXDTOSEL_MASK)
40424#define DDRPHY_DX8SLBDXCTL1_RESERVED_22_MASK (0x400000U)
40425#define DDRPHY_DX8SLBDXCTL1_RESERVED_22_SHIFT (22U)
40426/*! RESERVED_22 - Reserved. Return zeroes on reads.
40427 */
40428#define DDRPHY_DX8SLBDXCTL1_RESERVED_22(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_RESERVED_22_SHIFT)) & DDRPHY_DX8SLBDXCTL1_RESERVED_22_MASK)
40429#define DDRPHY_DX8SLBDXCTL1_DXRCLKMD_MASK (0x800000U)
40430#define DDRPHY_DX8SLBDXCTL1_DXRCLKMD_SHIFT (23U)
40431/*! DXRCLKMD - DATX8 Read Clock Mode
40432 */
40433#define DDRPHY_DX8SLBDXCTL1_DXRCLKMD(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXRCLKMD_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXRCLKMD_MASK)
40434#define DDRPHY_DX8SLBDXCTL1_DXCALCLK_MASK (0x1000000U)
40435#define DDRPHY_DX8SLBDXCTL1_DXCALCLK_SHIFT (24U)
40436/*! DXCALCLK - DATX Calibration Clock Select
40437 */
40438#define DDRPHY_DX8SLBDXCTL1_DXCALCLK(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_DXCALCLK_SHIFT)) & DDRPHY_DX8SLBDXCTL1_DXCALCLK_MASK)
40439#define DDRPHY_DX8SLBDXCTL1_RESERVED_31_25_MASK (0xFE000000U)
40440#define DDRPHY_DX8SLBDXCTL1_RESERVED_31_25_SHIFT (25U)
40441/*! RESERVED_31_25 - Reserved. Return zeroes on reads.
40442 */
40443#define DDRPHY_DX8SLBDXCTL1_RESERVED_31_25(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL1_RESERVED_31_25_SHIFT)) & DDRPHY_DX8SLBDXCTL1_RESERVED_31_25_MASK)
40444/*! @} */
40445
40446/*! @name DX8SLBDXCTL2 - DATX8 0-8 DX Control Register 2 */
40447/*! @{ */
40448#define DDRPHY_DX8SLBDXCTL2_RESERVED_0_MASK (0x1U)
40449#define DDRPHY_DX8SLBDXCTL2_RESERVED_0_SHIFT (0U)
40450/*! RESERVED_0 - Reserved. Return zeroes on reads.
40451 */
40452#define DDRPHY_DX8SLBDXCTL2_RESERVED_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_RESERVED_0_SHIFT)) & DDRPHY_DX8SLBDXCTL2_RESERVED_0_MASK)
40453#define DDRPHY_DX8SLBDXCTL2_DQSGLB_MASK (0x6U)
40454#define DDRPHY_DX8SLBDXCTL2_DQSGLB_SHIFT (1U)
40455/*! DQSGLB - Read DQS Gate I/O Loopback
40456 */
40457#define DDRPHY_DX8SLBDXCTL2_DQSGLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_DQSGLB_SHIFT)) & DDRPHY_DX8SLBDXCTL2_DQSGLB_MASK)
40458#define DDRPHY_DX8SLBDXCTL2_DISRST_MASK (0x8U)
40459#define DDRPHY_DX8SLBDXCTL2_DISRST_SHIFT (3U)
40460/*! DISRST - Disables the Read FIFO Reset
40461 */
40462#define DDRPHY_DX8SLBDXCTL2_DISRST(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_DISRST_SHIFT)) & DDRPHY_DX8SLBDXCTL2_DISRST_MASK)
40463#define DDRPHY_DX8SLBDXCTL2_RDMODE_MASK (0x30U)
40464#define DDRPHY_DX8SLBDXCTL2_RDMODE_SHIFT (4U)
40465/*! RDMODE - DATX8 Receive FIFO Read Mode
40466 */
40467#define DDRPHY_DX8SLBDXCTL2_RDMODE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_RDMODE_SHIFT)) & DDRPHY_DX8SLBDXCTL2_RDMODE_MASK)
40468#define DDRPHY_DX8SLBDXCTL2_PRFBYP_MASK (0x40U)
40469#define DDRPHY_DX8SLBDXCTL2_PRFBYP_SHIFT (6U)
40470/*! PRFBYP - PUB Read FIFO Bypass
40471 */
40472#define DDRPHY_DX8SLBDXCTL2_PRFBYP(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_PRFBYP_SHIFT)) & DDRPHY_DX8SLBDXCTL2_PRFBYP_MASK)
40473#define DDRPHY_DX8SLBDXCTL2_WDBI_MASK (0x80U)
40474#define DDRPHY_DX8SLBDXCTL2_WDBI_SHIFT (7U)
40475/*! WDBI - Write Data Bus Inversion Enable
40476 */
40477#define DDRPHY_DX8SLBDXCTL2_WDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_WDBI_SHIFT)) & DDRPHY_DX8SLBDXCTL2_WDBI_MASK)
40478#define DDRPHY_DX8SLBDXCTL2_RDBI_MASK (0x100U)
40479#define DDRPHY_DX8SLBDXCTL2_RDBI_SHIFT (8U)
40480/*! RDBI - Read Data Bus Inversion Enable
40481 */
40482#define DDRPHY_DX8SLBDXCTL2_RDBI(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_RDBI_SHIFT)) & DDRPHY_DX8SLBDXCTL2_RDBI_MASK)
40483#define DDRPHY_DX8SLBDXCTL2_LPWAKEUP_THRSH_MASK (0x1E00U)
40484#define DDRPHY_DX8SLBDXCTL2_LPWAKEUP_THRSH_SHIFT (9U)
40485/*! LPWAKEUP_THRSH - Low Power Wakeup Threshold
40486 */
40487#define DDRPHY_DX8SLBDXCTL2_LPWAKEUP_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_LPWAKEUP_THRSH_SHIFT)) & DDRPHY_DX8SLBDXCTL2_LPWAKEUP_THRSH_MASK)
40488#define DDRPHY_DX8SLBDXCTL2_RESERVED_14_13_MASK (0x6000U)
40489#define DDRPHY_DX8SLBDXCTL2_RESERVED_14_13_SHIFT (13U)
40490/*! RESERVED_14_13 - Reserved. Return zeroes on reads.
40491 */
40492#define DDRPHY_DX8SLBDXCTL2_RESERVED_14_13(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_RESERVED_14_13_SHIFT)) & DDRPHY_DX8SLBDXCTL2_RESERVED_14_13_MASK)
40493#define DDRPHY_DX8SLBDXCTL2_IOLB_MASK (0x8000U)
40494#define DDRPHY_DX8SLBDXCTL2_IOLB_SHIFT (15U)
40495/*! IOLB - I/O Loopback Select
40496 */
40497#define DDRPHY_DX8SLBDXCTL2_IOLB(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_IOLB_SHIFT)) & DDRPHY_DX8SLBDXCTL2_IOLB_MASK)
40498#define DDRPHY_DX8SLBDXCTL2_IOAG_MASK (0x10000U)
40499#define DDRPHY_DX8SLBDXCTL2_IOAG_SHIFT (16U)
40500/*! IOAG - I/O Assisted Gate Select
40501 */
40502#define DDRPHY_DX8SLBDXCTL2_IOAG(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_IOAG_SHIFT)) & DDRPHY_DX8SLBDXCTL2_IOAG_MASK)
40503#define DDRPHY_DX8SLBDXCTL2_RESERVED_17_MASK (0x20000U)
40504#define DDRPHY_DX8SLBDXCTL2_RESERVED_17_SHIFT (17U)
40505/*! RESERVED_17 - Reserved. Return zeroes on reads.
40506 */
40507#define DDRPHY_DX8SLBDXCTL2_RESERVED_17(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_RESERVED_17_SHIFT)) & DDRPHY_DX8SLBDXCTL2_RESERVED_17_MASK)
40508#define DDRPHY_DX8SLBDXCTL2_PREOEX_MASK (0xC0000U)
40509#define DDRPHY_DX8SLBDXCTL2_PREOEX_SHIFT (18U)
40510/*! PREOEX - OE Extension during Pre-amble
40511 */
40512#define DDRPHY_DX8SLBDXCTL2_PREOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_PREOEX_SHIFT)) & DDRPHY_DX8SLBDXCTL2_PREOEX_MASK)
40513#define DDRPHY_DX8SLBDXCTL2_POSOEX_MASK (0x700000U)
40514#define DDRPHY_DX8SLBDXCTL2_POSOEX_SHIFT (20U)
40515/*! POSOEX - OX Extension during Post-amble
40516 */
40517#define DDRPHY_DX8SLBDXCTL2_POSOEX(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_POSOEX_SHIFT)) & DDRPHY_DX8SLBDXCTL2_POSOEX_MASK)
40518#define DDRPHY_DX8SLBDXCTL2_CRDEN_MASK (0x800000U)
40519#define DDRPHY_DX8SLBDXCTL2_CRDEN_SHIFT (23U)
40520/*! CRDEN - Configurable Read Data Enable
40521 */
40522#define DDRPHY_DX8SLBDXCTL2_CRDEN(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_CRDEN_SHIFT)) & DDRPHY_DX8SLBDXCTL2_CRDEN_MASK)
40523#define DDRPHY_DX8SLBDXCTL2_RESERVED_31_24_MASK (0xFF000000U)
40524#define DDRPHY_DX8SLBDXCTL2_RESERVED_31_24_SHIFT (24U)
40525/*! RESERVED_31_24 - Reserved. Return zeroes on reads.
40526 */
40527#define DDRPHY_DX8SLBDXCTL2_RESERVED_31_24(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBDXCTL2_RESERVED_31_24_SHIFT)) & DDRPHY_DX8SLBDXCTL2_RESERVED_31_24_MASK)
40528/*! @} */
40529
40530/*! @name DX8SLBIOCR - DATX8 0-8 I/O Configuration Register */
40531/*! @{ */
40532#define DDRPHY_DX8SLBIOCR_DXRXM_MASK (0x7FFU)
40533#define DDRPHY_DX8SLBIOCR_DXRXM_SHIFT (0U)
40534/*! DXRXM - DX IO Receiver Mode
40535 */
40536#define DDRPHY_DX8SLBIOCR_DXRXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBIOCR_DXRXM_SHIFT)) & DDRPHY_DX8SLBIOCR_DXRXM_MASK)
40537#define DDRPHY_DX8SLBIOCR_DXTXM_MASK (0x3FF800U)
40538#define DDRPHY_DX8SLBIOCR_DXTXM_SHIFT (11U)
40539/*! DXTXM - DX IO Transmitter Mode
40540 */
40541#define DDRPHY_DX8SLBIOCR_DXTXM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBIOCR_DXTXM_SHIFT)) & DDRPHY_DX8SLBIOCR_DXTXM_MASK)
40542#define DDRPHY_DX8SLBIOCR_DXIOM_MASK (0x1C00000U)
40543#define DDRPHY_DX8SLBIOCR_DXIOM_SHIFT (22U)
40544/*! DXIOM - DX IO Mode
40545 */
40546#define DDRPHY_DX8SLBIOCR_DXIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBIOCR_DXIOM_SHIFT)) & DDRPHY_DX8SLBIOCR_DXIOM_MASK)
40547#define DDRPHY_DX8SLBIOCR_DXVREFIOM_MASK (0xE000000U)
40548#define DDRPHY_DX8SLBIOCR_DXVREFIOM_SHIFT (25U)
40549/*! DXVREFIOM - IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
40550 */
40551#define DDRPHY_DX8SLBIOCR_DXVREFIOM(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBIOCR_DXVREFIOM_SHIFT)) & DDRPHY_DX8SLBIOCR_DXVREFIOM_MASK)
40552#define DDRPHY_DX8SLBIOCR_DXDACRANGE_MASK (0x70000000U)
40553#define DDRPHY_DX8SLBIOCR_DXDACRANGE_SHIFT (28U)
40554/*! DXDACRANGE - PVREF_DAC REFSEL range select
40555 */
40556#define DDRPHY_DX8SLBIOCR_DXDACRANGE(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBIOCR_DXDACRANGE_SHIFT)) & DDRPHY_DX8SLBIOCR_DXDACRANGE_MASK)
40557#define DDRPHY_DX8SLBIOCR_RESERVED_31_MASK (0x80000000U)
40558#define DDRPHY_DX8SLBIOCR_RESERVED_31_SHIFT (31U)
40559/*! RESERVED_31 - Reserved. Return zeroes on reads.
40560 */
40561#define DDRPHY_DX8SLBIOCR_RESERVED_31(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX8SLBIOCR_RESERVED_31_SHIFT)) & DDRPHY_DX8SLBIOCR_RESERVED_31_MASK)
40562/*! @} */
40563
40564/*! @name DX4SLBIOCR - DATX4 0-8 I/O Configuration Register */
40565/*! @{ */
40566#define DDRPHY_DX4SLBIOCR_RESERVED_31_0_MASK (0xFFFFFFFFU)
40567#define DDRPHY_DX4SLBIOCR_RESERVED_31_0_SHIFT (0U)
40568/*! RESERVED_31_0 - Reserved. Return zeroes on reads.
40569 */
40570#define DDRPHY_DX4SLBIOCR_RESERVED_31_0(x) (((uint32_t)(((uint32_t)(x)) << DDRPHY_DX4SLBIOCR_RESERVED_31_0_SHIFT)) & DDRPHY_DX4SLBIOCR_RESERVED_31_0_MASK)
40571/*! @} */
40572
40573
40574/*!
40575 * @}
40576 */ /* end of group DDRPHY_Register_Masks */
40577
40578
40579/* DDRPHY - Peripheral instance base addresses */
40580/** Peripheral DRC__DDR_PHY base address */
40581#define DRC__DDR_PHY_BASE (0x5C010000u)
40582/** Peripheral DRC__DDR_PHY base pointer */
40583#define DRC__DDR_PHY ((DDRPHY_Type *)DRC__DDR_PHY_BASE)
40584/** Array initializer of DDRPHY peripheral base addresses */
40585#define DDRPHY_BASE_ADDRS { DRC__DDR_PHY_BASE }
40586/** Array initializer of DDRPHY peripheral base pointers */
40587#define DDRPHY_BASE_PTRS { DRC__DDR_PHY }
40588
40589/*!
40590 * @}
40591 */ /* end of group DDRPHY_Peripheral_Access_Layer */
40592
40593
40594/* ----------------------------------------------------------------------------
40595 -- DMA Peripheral Access Layer
40596 ---------------------------------------------------------------------------- */
40597
40598/*!
40599 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
40600 * @{
40601 */
40602
40603/** DMA - Register Layout Typedef */
40604typedef struct {
40605 __IO uint32_t MP_CSR; /**< Management Page Control Register, offset: 0x0 */
40606 __I uint32_t MP_ES; /**< Management Page Error Status Register, offset: 0x4 */
40607 uint8_t RESERVED_0[4];
40608 __I uint32_t MP_HRS; /**< Management Page Hardware Request Status Register, offset: 0xC */
40609 uint8_t RESERVED_1[240];
40610 __IO uint32_t CH_GRPRI[32]; /**< Channel Arbitration Group Register, array offset: 0x100, array step: 0x4 */
40611 uint8_t RESERVED_2[65152];
40612 struct { /* offset: 0x10000, array step: 0x10000 */
40613 __IO uint32_t CH_CSR; /**< Channel Control and Status Register, array offset: 0x10000, array step: 0x10000 */
40614 __IO uint32_t CH_ES; /**< Channel Error Status Register, array offset: 0x10004, array step: 0x10000 */
40615 __IO uint32_t CH_INT; /**< Channel Interrupt Status Register, array offset: 0x10008, array step: 0x10000 */
40616 __IO uint32_t CH_SBR; /**< Channel System Bus Register, array offset: 0x1000C, array step: 0x10000 */
40617 __IO uint32_t CH_PRI; /**< Channel Priority Register, array offset: 0x10010, array step: 0x10000 */
40618 __IO uint32_t CH_MUX; /**< Channel Multiplexor Configuration, array offset: 0x10014, array step: 0x10000 */
40619 uint8_t RESERVED_0[8];
40620 __IO uint32_t TCD_SADDR; /**< TCD Source Address Register, array offset: 0x10020, array step: 0x10000 */
40621 __IO uint16_t TCD_SOFF; /**< TCD Signed Source Address Offset Register, array offset: 0x10024, array step: 0x10000 */
40622 __IO uint16_t TCD_ATTR; /**< TCD Transfer Attributes Register, array offset: 0x10026, array step: 0x10000 */
40623 union { /* offset: 0x10028, array step: 0x10000 */
40624 __IO uint32_t TCD_NBYTES_MLOFFNO; /**< TCD Transfer Size without Minor Loop Offsets Register, array offset: 0x10028, array step: 0x10000 */
40625 __IO uint32_t TCD_NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets Register, array offset: 0x10028, array step: 0x10000 */
40626 };
40627 __IO uint32_t TCD_SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address Register, array offset: 0x1002C, array step: 0x10000 */
40628 __IO uint32_t TCD_DADDR; /**< TCD Destination Address Register, array offset: 0x10030, array step: 0x10000 */
40629 __IO uint16_t TCD_DOFF; /**< TCD Signed Destination Address Offset Register, array offset: 0x10034, array step: 0x10000 */
40630 union { /* offset: 0x10036, array step: 0x10000 */
40631 __IO uint16_t TCD_CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) Register, array offset: 0x10036, array step: 0x10000 */
40632 __IO uint16_t TCD_CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) Register, array offset: 0x10036, array step: 0x10000 */
40633 };
40634 __IO uint32_t TCD_DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address Register, array offset: 0x10038, array step: 0x10000 */
40635 __IO uint16_t TCD_CSR; /**< TCD Control and Status Register, array offset: 0x1003C, array step: 0x10000 */
40636 union { /* offset: 0x1003E, array step: 0x10000 */
40637 __IO uint16_t TCD_BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) Register, array offset: 0x1003E, array step: 0x10000 */
40638 __IO uint16_t TCD_BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) Register, array offset: 0x1003E, array step: 0x10000 */
40639 };
40640 uint8_t RESERVED_1[65472];
40641 } CH[32];
40642} DMA_Type;
40643
40644/* ----------------------------------------------------------------------------
40645 -- DMA Register Masks
40646 ---------------------------------------------------------------------------- */
40647
40648/*!
40649 * @addtogroup DMA_Register_Masks DMA Register Masks
40650 * @{
40651 */
40652
40653/*! @name MP_CSR - Management Page Control Register */
40654/*! @{ */
40655#define DMA_MP_CSR_EBW_MASK (0x1U)
40656#define DMA_MP_CSR_EBW_SHIFT (0U)
40657/*! EBW - Enable Buffered Writes
40658 * 0b0..Buffered writes on the system bus are disabled.
40659 * 0b1..Buffered writes on the system bus are enabled.
40660 */
40661#define DMA_MP_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EBW_SHIFT)) & DMA_MP_CSR_EBW_MASK)
40662#define DMA_MP_CSR_EDBG_MASK (0x2U)
40663#define DMA_MP_CSR_EDBG_SHIFT (1U)
40664/*! EDBG - Enable Debug
40665 * 0b0..Debug mode is disabled.
40666 * 0b1..Debug mode is enabled.
40667 */
40668#define DMA_MP_CSR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_EDBG_SHIFT)) & DMA_MP_CSR_EDBG_MASK)
40669#define DMA_MP_CSR_ERCA_MASK (0x4U)
40670#define DMA_MP_CSR_ERCA_SHIFT (2U)
40671/*! ERCA - Enable Round Robin Channel Arbitration
40672 * 0b0..Round robin channel arbitration is disabled.
40673 * 0b1..Round robin channel arbitration is enabled.
40674 */
40675#define DMA_MP_CSR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ERCA_SHIFT)) & DMA_MP_CSR_ERCA_MASK)
40676#define DMA_MP_CSR_HAE_MASK (0x10U)
40677#define DMA_MP_CSR_HAE_SHIFT (4U)
40678/*! HAE - Halt After Error
40679 * 0b0..Normal operation
40680 * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
40681 */
40682#define DMA_MP_CSR_HAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HAE_SHIFT)) & DMA_MP_CSR_HAE_MASK)
40683#define DMA_MP_CSR_HALT_MASK (0x20U)
40684#define DMA_MP_CSR_HALT_SHIFT (5U)
40685/*! HALT - Halt DMA Operations
40686 * 0b0..Normal operation
40687 * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
40688 */
40689#define DMA_MP_CSR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_HALT_SHIFT)) & DMA_MP_CSR_HALT_MASK)
40690#define DMA_MP_CSR_GCLC_MASK (0x40U)
40691#define DMA_MP_CSR_GCLC_SHIFT (6U)
40692/*! GCLC - Global Channel Linking Control
40693 * 0b0..Channel linking is disabled for all channels.
40694 * 0b1..Channel linking is available and controlled by each channel's link settings.
40695 */
40696#define DMA_MP_CSR_GCLC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GCLC_SHIFT)) & DMA_MP_CSR_GCLC_MASK)
40697#define DMA_MP_CSR_GMRC_MASK (0x80U)
40698#define DMA_MP_CSR_GMRC_SHIFT (7U)
40699/*! GMRC - Global Master ID Replication Control
40700 * 0b0..Master ID replication is disabled for all channels.
40701 * 0b1..Master ID replication is available and is controlled by each channel's CHn_SBR[EMI] setting.
40702 */
40703#define DMA_MP_CSR_GMRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_GMRC_SHIFT)) & DMA_MP_CSR_GMRC_MASK)
40704#define DMA_MP_CSR_ECX_MASK (0x100U)
40705#define DMA_MP_CSR_ECX_SHIFT (8U)
40706/*! ECX - Cancel Transfer with Error
40707 * 0b0..Normal operation
40708 * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and
40709 * force the minor loop to finish. The cancel takes effect after the last write of the current read/write
40710 * sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX
40711 * treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an
40712 * optional error interrupt.
40713 */
40714#define DMA_MP_CSR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ECX_SHIFT)) & DMA_MP_CSR_ECX_MASK)
40715#define DMA_MP_CSR_CX_MASK (0x200U)
40716#define DMA_MP_CSR_CX_SHIFT (9U)
40717/*! CX - Cancel Transfer
40718 * 0b0..Normal operation
40719 * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The
40720 * cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after
40721 * the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
40722 */
40723#define DMA_MP_CSR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_CX_SHIFT)) & DMA_MP_CSR_CX_MASK)
40724#define DMA_MP_CSR_ACTIVE_ID_MASK (0x1F000000U) /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */
40725#define DMA_MP_CSR_ACTIVE_ID_SHIFT (24U)
40726/*! ACTIVE_ID - Active channel ID
40727 */
40728#define DMA_MP_CSR_ACTIVE_ID(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_ID_SHIFT)) & DMA_MP_CSR_ACTIVE_ID_MASK) /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */
40729#define DMA_MP_CSR_ACTIVE_MASK (0x80000000U)
40730#define DMA_MP_CSR_ACTIVE_SHIFT (31U)
40731/*! ACTIVE - DMA Active Status
40732 * 0b0..eDMA is idle.
40733 * 0b1..eDMA is executing a channel.
40734 */
40735#define DMA_MP_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_CSR_ACTIVE_SHIFT)) & DMA_MP_CSR_ACTIVE_MASK)
40736/*! @} */
40737
40738/*! @name MP_ES - Management Page Error Status Register */
40739/*! @{ */
40740#define DMA_MP_ES_DBE_MASK (0x1U)
40741#define DMA_MP_ES_DBE_SHIFT (0U)
40742/*! DBE - Destination Bus Error
40743 * 0b0..No destination bus error
40744 * 0b1..The last recorded error was a bus error on a destination write
40745 */
40746#define DMA_MP_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DBE_SHIFT)) & DMA_MP_ES_DBE_MASK)
40747#define DMA_MP_ES_SBE_MASK (0x2U)
40748#define DMA_MP_ES_SBE_SHIFT (1U)
40749/*! SBE - Source Bus Error
40750 * 0b0..No source bus error
40751 * 0b1..The last recorded error was a bus error on a source read
40752 */
40753#define DMA_MP_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SBE_SHIFT)) & DMA_MP_ES_SBE_MASK)
40754#define DMA_MP_ES_SGE_MASK (0x4U)
40755#define DMA_MP_ES_SGE_SHIFT (2U)
40756/*! SGE - Scatter/Gather Configuration Error
40757 * 0b0..No scatter/gather configuration error
40758 * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is
40759 * checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is
40760 * enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
40761 */
40762#define DMA_MP_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SGE_SHIFT)) & DMA_MP_ES_SGE_MASK)
40763#define DMA_MP_ES_NCE_MASK (0x8U)
40764#define DMA_MP_ES_NCE_SHIFT (3U)
40765/*! NCE - NBYTES/CITER Configuration Error
40766 * 0b0..No NBYTES/CITER configuration error
40767 * 0b1..The last recorded error was NBYTES equal to zero or a CITER not equal to BITER error
40768 */
40769#define DMA_MP_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_NCE_SHIFT)) & DMA_MP_ES_NCE_MASK)
40770#define DMA_MP_ES_DOE_MASK (0x10U)
40771#define DMA_MP_ES_DOE_SHIFT (4U)
40772/*! DOE - Destination Offset Error
40773 * 0b0..No destination offset configuration error
40774 * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
40775 */
40776#define DMA_MP_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DOE_SHIFT)) & DMA_MP_ES_DOE_MASK)
40777#define DMA_MP_ES_DAE_MASK (0x20U)
40778#define DMA_MP_ES_DAE_SHIFT (5U)
40779/*! DAE - Destination Address Error
40780 * 0b0..No destination address configuration error
40781 * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
40782 */
40783#define DMA_MP_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_DAE_SHIFT)) & DMA_MP_ES_DAE_MASK)
40784#define DMA_MP_ES_SOE_MASK (0x40U)
40785#define DMA_MP_ES_SOE_SHIFT (6U)
40786/*! SOE - Source Offset Error
40787 * 0b0..No source offset configuration error
40788 * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
40789 */
40790#define DMA_MP_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SOE_SHIFT)) & DMA_MP_ES_SOE_MASK)
40791#define DMA_MP_ES_SAE_MASK (0x80U)
40792#define DMA_MP_ES_SAE_SHIFT (7U)
40793/*! SAE - Source Address Error
40794 * 0b0..No source address configuration error.
40795 * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
40796 */
40797#define DMA_MP_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_SAE_SHIFT)) & DMA_MP_ES_SAE_MASK)
40798#define DMA_MP_ES_ECX_MASK (0x100U)
40799#define DMA_MP_ES_ECX_SHIFT (8U)
40800/*! ECX - Transfer Canceled
40801 * 0b0..No canceled transfers
40802 * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input.
40803 */
40804#define DMA_MP_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ECX_SHIFT)) & DMA_MP_ES_ECX_MASK)
40805#define DMA_MP_ES_ERRCHN_MASK (0x1F000000U) /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */
40806#define DMA_MP_ES_ERRCHN_SHIFT (24U)
40807/*! ERRCHN - Error Channel Number or Canceled Channel Number
40808 */
40809#define DMA_MP_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_ERRCHN_SHIFT)) & DMA_MP_ES_ERRCHN_MASK) /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */
40810#define DMA_MP_ES_VLD_MASK (0x80000000U)
40811#define DMA_MP_ES_VLD_SHIFT (31U)
40812/*! VLD - Valid
40813 * 0b0..No ERR bits are set.
40814 * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.
40815 */
40816#define DMA_MP_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_ES_VLD_SHIFT)) & DMA_MP_ES_VLD_MASK)
40817/*! @} */
40818
40819/*! @name MP_HRS - Management Page Hardware Request Status Register */
40820/*! @{ */
40821#define DMA_MP_HRS_HRS_MASK (0xFFFFFFFFU)
40822#define DMA_MP_HRS_HRS_SHIFT (0U)
40823/*! HRS - Hardware Request Status
40824 * 0b00000000000000000000000000000000..A hardware service request for the channel is not present
40825 * 0b00000000000000000000000000000001..A hardware service request for channel 0 is present
40826 */
40827#define DMA_MP_HRS_HRS(x) (((uint32_t)(((uint32_t)(x)) << DMA_MP_HRS_HRS_SHIFT)) & DMA_MP_HRS_HRS_MASK)
40828/*! @} */
40829
40830/*! @name CH_GRPRI - Channel Arbitration Group Register */
40831/*! @{ */
40832#define DMA_CH_GRPRI_GRPRI_MASK (0x1FU)
40833#define DMA_CH_GRPRI_GRPRI_SHIFT (0U)
40834/*! GRPRI - Arbitration Group for channel n.
40835 */
40836#define DMA_CH_GRPRI_GRPRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_GRPRI_GRPRI_SHIFT)) & DMA_CH_GRPRI_GRPRI_MASK)
40837/*! @} */
40838
40839/* The count of DMA_CH_GRPRI */
40840#define DMA_CH_GRPRI_COUNT (32U)
40841
40842/*! @name CH_CSR - Channel Control and Status Register */
40843/*! @{ */
40844#define DMA_CH_CSR_ERQ_MASK (0x1U)
40845#define DMA_CH_CSR_ERQ_SHIFT (0U)
40846/*! ERQ - Enable DMA Request
40847 * 0b0..The DMA hardware request signal for the corresponding channel is disabled.
40848 * 0b1..The DMA hardware request signal for the corresponding channel is enabled.
40849 */
40850#define DMA_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
40851#define DMA_CH_CSR_EARQ_MASK (0x2U)
40852#define DMA_CH_CSR_EARQ_SHIFT (1U)
40853/*! EARQ - Enable Asynchronous DMA Request in stop mode for channel
40854 * 0b0..Disable asynchronous DMA request for the channel.
40855 * 0b1..Enable asynchronous DMA request for the channel.
40856 */
40857#define DMA_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EARQ_SHIFT)) & DMA_CH_CSR_EARQ_MASK)
40858#define DMA_CH_CSR_EEI_MASK (0x4U)
40859#define DMA_CH_CSR_EEI_SHIFT (2U)
40860/*! EEI - Enable Error Interrupt
40861 * 0b0..The error signal for corresponding channel does not generate an error interrupt
40862 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
40863 */
40864#define DMA_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_EEI_SHIFT)) & DMA_CH_CSR_EEI_MASK)
40865#define DMA_CH_CSR_DONE_MASK (0x40000000U)
40866#define DMA_CH_CSR_DONE_SHIFT (30U)
40867/*! DONE - Channel Done
40868 */
40869#define DMA_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_DONE_SHIFT)) & DMA_CH_CSR_DONE_MASK)
40870#define DMA_CH_CSR_ACTIVE_MASK (0x80000000U)
40871#define DMA_CH_CSR_ACTIVE_SHIFT (31U)
40872/*! ACTIVE - Channel Active
40873 */
40874#define DMA_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ACTIVE_SHIFT)) & DMA_CH_CSR_ACTIVE_MASK)
40875/*! @} */
40876
40877/* The count of DMA_CH_CSR */
40878#define DMA_CH_CSR_COUNT (32U)
40879
40880/*! @name CH_ES - Channel Error Status Register */
40881/*! @{ */
40882#define DMA_CH_ES_DBE_MASK (0x1U)
40883#define DMA_CH_ES_DBE_SHIFT (0U)
40884/*! DBE - Destination Bus Error
40885 * 0b0..No destination bus error
40886 * 0b1..The last recorded error was a bus error on a destination write
40887 */
40888#define DMA_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DBE_SHIFT)) & DMA_CH_ES_DBE_MASK)
40889#define DMA_CH_ES_SBE_MASK (0x2U)
40890#define DMA_CH_ES_SBE_SHIFT (1U)
40891/*! SBE - Source Bus Error
40892 * 0b0..No source bus error
40893 * 0b1..The last recorded error was a bus error on a source read
40894 */
40895#define DMA_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SBE_SHIFT)) & DMA_CH_ES_SBE_MASK)
40896#define DMA_CH_ES_SGE_MASK (0x4U)
40897#define DMA_CH_ES_SGE_SHIFT (2U)
40898/*! SGE - Scatter/Gather Configuration Error
40899 * 0b0..No scatter/gather configuration error
40900 * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is
40901 * checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is
40902 * enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
40903 */
40904#define DMA_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SGE_SHIFT)) & DMA_CH_ES_SGE_MASK)
40905#define DMA_CH_ES_NCE_MASK (0x8U)
40906#define DMA_CH_ES_NCE_SHIFT (3U)
40907/*! NCE - NBYTES/CITER Configuration Error
40908 * 0b0..No NBYTES/CITER configuration error
40909 * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields.
40910 * TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero,
40911 * or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
40912 */
40913#define DMA_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_NCE_SHIFT)) & DMA_CH_ES_NCE_MASK)
40914#define DMA_CH_ES_DOE_MASK (0x10U)
40915#define DMA_CH_ES_DOE_SHIFT (4U)
40916/*! DOE - Destination Offset Error
40917 * 0b0..No destination offset configuration error
40918 * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
40919 */
40920#define DMA_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DOE_SHIFT)) & DMA_CH_ES_DOE_MASK)
40921#define DMA_CH_ES_DAE_MASK (0x20U)
40922#define DMA_CH_ES_DAE_SHIFT (5U)
40923/*! DAE - Destination Address Error
40924 * 0b0..No destination address configuration error
40925 * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
40926 */
40927#define DMA_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_DAE_SHIFT)) & DMA_CH_ES_DAE_MASK)
40928#define DMA_CH_ES_SOE_MASK (0x40U)
40929#define DMA_CH_ES_SOE_SHIFT (6U)
40930/*! SOE - Source Offset Error
40931 * 0b0..No source offset configuration error
40932 * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
40933 */
40934#define DMA_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SOE_SHIFT)) & DMA_CH_ES_SOE_MASK)
40935#define DMA_CH_ES_SAE_MASK (0x80U)
40936#define DMA_CH_ES_SAE_SHIFT (7U)
40937/*! SAE - Source Address Error
40938 * 0b0..No source address configuration error.
40939 * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
40940 */
40941#define DMA_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_SAE_SHIFT)) & DMA_CH_ES_SAE_MASK)
40942#define DMA_CH_ES_ERR_MASK (0x80000000U)
40943#define DMA_CH_ES_ERR_SHIFT (31U)
40944/*! ERR - Error In Channel
40945 * 0b0..An error in this channel has not occurred
40946 * 0b1..An error in this channel has occurred
40947 */
40948#define DMA_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_ES_ERR_SHIFT)) & DMA_CH_ES_ERR_MASK)
40949/*! @} */
40950
40951/* The count of DMA_CH_ES */
40952#define DMA_CH_ES_COUNT (32U)
40953
40954/*! @name CH_INT - Channel Interrupt Status Register */
40955/*! @{ */
40956#define DMA_CH_INT_INT_MASK (0x1U)
40957#define DMA_CH_INT_INT_SHIFT (0U)
40958/*! INT - Interrupt Request
40959 * 0b0..The interrupt request for corresponding channel is cleared
40960 * 0b1..The interrupt request for corresponding channel is active
40961 */
40962#define DMA_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_INT_INT_SHIFT)) & DMA_CH_INT_INT_MASK)
40963/*! @} */
40964
40965/* The count of DMA_CH_INT */
40966#define DMA_CH_INT_COUNT (32U)
40967
40968/*! @name CH_SBR - Channel System Bus Register */
40969/*! @{ */
40970#define DMA_CH_SBR_MID_MASK (0x1FU)
40971#define DMA_CH_SBR_MID_SHIFT (0U)
40972/*! MID - Master ID
40973 */
40974#define DMA_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_MID_SHIFT)) & DMA_CH_SBR_MID_MASK)
40975#define DMA_CH_SBR_PAL_MASK (0x8000U)
40976#define DMA_CH_SBR_PAL_SHIFT (15U)
40977/*! PAL - Privileged Access Level
40978 * 0b0..User protection level for DMA transfers
40979 * 0b1..Privileged protection level for DMA transfers
40980 */
40981#define DMA_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_PAL_SHIFT)) & DMA_CH_SBR_PAL_MASK)
40982#define DMA_CH_SBR_EMI_MASK (0x10000U)
40983#define DMA_CH_SBR_EMI_SHIFT (16U)
40984/*! EMI - Enable Master ID replication
40985 * 0b0..Master ID replication is disabled
40986 * 0b1..Master ID replication is enabled
40987 */
40988#define DMA_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_EMI_SHIFT)) & DMA_CH_SBR_EMI_MASK)
40989#define DMA_CH_SBR_ATTR_MASK (0x7E0000U)
40990#define DMA_CH_SBR_ATTR_SHIFT (17U)
40991/*! ATTR - Attribute Output
40992 */
40993#define DMA_CH_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_SBR_ATTR_SHIFT)) & DMA_CH_SBR_ATTR_MASK)
40994/*! @} */
40995
40996/* The count of DMA_CH_SBR */
40997#define DMA_CH_SBR_COUNT (32U)
40998
40999/*! @name CH_PRI - Channel Priority Register */
41000/*! @{ */
41001#define DMA_CH_PRI_APL_MASK (0x7U)
41002#define DMA_CH_PRI_APL_SHIFT (0U)
41003/*! APL - Arbitration Priority Level
41004 */
41005#define DMA_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_APL_SHIFT)) & DMA_CH_PRI_APL_MASK)
41006#define DMA_CH_PRI_DPA_MASK (0x40000000U)
41007#define DMA_CH_PRI_DPA_SHIFT (30U)
41008/*! DPA - Disable Preempt Ability.
41009 * 0b0..The channel can suspend a lower priority channel.
41010 * 0b1..The channel cannot suspend any other channel, regardless of channel priority.
41011 */
41012#define DMA_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_DPA_SHIFT)) & DMA_CH_PRI_DPA_MASK)
41013#define DMA_CH_PRI_ECP_MASK (0x80000000U)
41014#define DMA_CH_PRI_ECP_SHIFT (31U)
41015/*! ECP - Enable Channel Preemption.
41016 * 0b0..The channel cannot be suspended by a higher priority channel's service request.
41017 * 0b1..The channel can be temporarily suspended by the service request of a higher priority channel.
41018 */
41019#define DMA_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_PRI_ECP_SHIFT)) & DMA_CH_PRI_ECP_MASK)
41020/*! @} */
41021
41022/* The count of DMA_CH_PRI */
41023#define DMA_CH_PRI_COUNT (32U)
41024
41025/*! @name CH_MUX - Channel Multiplexor Configuration */
41026/*! @{ */
41027#define DMA_CH_MUX_SRC_MASK (0x1FU)
41028#define DMA_CH_MUX_SRC_SHIFT (0U)
41029/*! SRC - Service Request Source
41030 */
41031#define DMA_CH_MUX_SRC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CH_MUX_SRC_SHIFT)) & DMA_CH_MUX_SRC_MASK)
41032/*! @} */
41033
41034/* The count of DMA_CH_MUX */
41035#define DMA_CH_MUX_COUNT (32U)
41036
41037/*! @name TCD_SADDR - TCD Source Address Register */
41038/*! @{ */
41039#define DMA_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU)
41040#define DMA_TCD_SADDR_SADDR_SHIFT (0U)
41041/*! SADDR - Source Address
41042 */
41043#define DMA_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SADDR_SADDR_SHIFT)) & DMA_TCD_SADDR_SADDR_MASK)
41044/*! @} */
41045
41046/* The count of DMA_TCD_SADDR */
41047#define DMA_TCD_SADDR_COUNT (32U)
41048
41049/*! @name TCD_SOFF - TCD Signed Source Address Offset Register */
41050/*! @{ */
41051#define DMA_TCD_SOFF_SOFF_MASK (0xFFFFU)
41052#define DMA_TCD_SOFF_SOFF_SHIFT (0U)
41053/*! SOFF - Source address signed offset
41054 */
41055#define DMA_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_SOFF_SOFF_SHIFT)) & DMA_TCD_SOFF_SOFF_MASK)
41056/*! @} */
41057
41058/* The count of DMA_TCD_SOFF */
41059#define DMA_TCD_SOFF_COUNT (32U)
41060
41061/*! @name TCD_ATTR - TCD Transfer Attributes Register */
41062/*! @{ */
41063#define DMA_TCD_ATTR_DSIZE_MASK (0x7U)
41064#define DMA_TCD_ATTR_DSIZE_SHIFT (0U)
41065/*! DSIZE - Destination data transfer size
41066 */
41067#define DMA_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DSIZE_SHIFT)) & DMA_TCD_ATTR_DSIZE_MASK)
41068#define DMA_TCD_ATTR_DMOD_MASK (0xF8U)
41069#define DMA_TCD_ATTR_DMOD_SHIFT (3U)
41070/*! DMOD - Destination address modulo
41071 */
41072#define DMA_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_DMOD_SHIFT)) & DMA_TCD_ATTR_DMOD_MASK)
41073#define DMA_TCD_ATTR_SSIZE_MASK (0x700U)
41074#define DMA_TCD_ATTR_SSIZE_SHIFT (8U)
41075/*! SSIZE - Source data transfer size
41076 * 0b000..8-bit
41077 * 0b001..16-bit
41078 * 0b010..32-bit
41079 * 0b011..64-bit
41080 * 0b100..16-byte
41081 * 0b101..32-byte
41082 * 0b110..64-byte
41083 * 0b111..Reserved
41084 */
41085#define DMA_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SSIZE_SHIFT)) & DMA_TCD_ATTR_SSIZE_MASK)
41086#define DMA_TCD_ATTR_SMOD_MASK (0xF800U)
41087#define DMA_TCD_ATTR_SMOD_SHIFT (11U)
41088/*! SMOD - Source address modulo
41089 * 0b00000..Source address modulo feature is disabled
41090 * 0b00001..Source address modulo feature is enabled for any non-zero value [1-31]
41091 */
41092#define DMA_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_ATTR_SMOD_SHIFT)) & DMA_TCD_ATTR_SMOD_MASK)
41093/*! @} */
41094
41095/* The count of DMA_TCD_ATTR */
41096#define DMA_TCD_ATTR_COUNT (32U)
41097
41098/*! @name TCD_NBYTES_MLOFFNO - TCD Transfer Size without Minor Loop Offsets Register */
41099/*! @{ */
41100#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
41101#define DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
41102/*! NBYTES - Number of Bytes to transfer per service request
41103 */
41104#define DMA_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_NBYTES_MASK)
41105#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
41106#define DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
41107/*! DMLOE - Destination Minor Loop Offset Enable
41108 * 0b0..The minor loop offset is not applied to the DADDR
41109 * 0b1..The minor loop offset is applied to the DADDR
41110 */
41111#define DMA_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_DMLOE_MASK)
41112#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
41113#define DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
41114/*! SMLOE - Source Minor Loop Offset Enable
41115 * 0b0..The minor loop offset is not applied to the SADDR
41116 * 0b1..The minor loop offset is applied to the SADDR
41117 */
41118#define DMA_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFNO_SMLOE_MASK)
41119/*! @} */
41120
41121/* The count of DMA_TCD_NBYTES_MLOFFNO */
41122#define DMA_TCD_NBYTES_MLOFFNO_COUNT (32U)
41123
41124/*! @name TCD_NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets Register */
41125/*! @{ */
41126#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
41127#define DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
41128/*! NBYTES - Number of Bytes to transfer per service request
41129 */
41130#define DMA_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_NBYTES_MASK)
41131#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
41132#define DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
41133/*! MLOFF - Minor Loop Offset
41134 */
41135#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_MLOFF_MASK)
41136#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
41137#define DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
41138/*! DMLOE - Destination Minor Loop Offset Enable
41139 * 0b0..The minor loop offset is not applied to the DADDR
41140 * 0b1..The minor loop offset is applied to the DADDR
41141 */
41142#define DMA_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_DMLOE_MASK)
41143#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
41144#define DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
41145/*! SMLOE - Source Minor Loop Offset Enable
41146 * 0b0..The minor loop offset is not applied to the SADDR
41147 * 0b1..The minor loop offset is applied to the SADDR
41148 */
41149#define DMA_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_TCD_NBYTES_MLOFFYES_SMLOE_MASK)
41150/*! @} */
41151
41152/* The count of DMA_TCD_NBYTES_MLOFFYES */
41153#define DMA_TCD_NBYTES_MLOFFYES_COUNT (32U)
41154
41155/*! @name TCD_SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address Register */
41156/*! @{ */
41157#define DMA_TCD_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU)
41158#define DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT (0U)
41159/*! SLAST_SDA - Last Source Address Adjustment / Store DADDR Address
41160 */
41161#define DMA_TCD_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & DMA_TCD_SLAST_SDA_SLAST_SDA_MASK)
41162/*! @} */
41163
41164/* The count of DMA_TCD_SLAST_SDA */
41165#define DMA_TCD_SLAST_SDA_COUNT (32U)
41166
41167/*! @name TCD_DADDR - TCD Destination Address Register */
41168/*! @{ */
41169#define DMA_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU)
41170#define DMA_TCD_DADDR_DADDR_SHIFT (0U)
41171/*! DADDR - Destination Address
41172 */
41173#define DMA_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DADDR_DADDR_SHIFT)) & DMA_TCD_DADDR_DADDR_MASK)
41174/*! @} */
41175
41176/* The count of DMA_TCD_DADDR */
41177#define DMA_TCD_DADDR_COUNT (32U)
41178
41179/*! @name TCD_DOFF - TCD Signed Destination Address Offset Register */
41180/*! @{ */
41181#define DMA_TCD_DOFF_DOFF_MASK (0xFFFFU)
41182#define DMA_TCD_DOFF_DOFF_SHIFT (0U)
41183/*! DOFF - Destination Address Signed Offset
41184 */
41185#define DMA_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_DOFF_DOFF_SHIFT)) & DMA_TCD_DOFF_DOFF_MASK)
41186/*! @} */
41187
41188/* The count of DMA_TCD_DOFF */
41189#define DMA_TCD_DOFF_COUNT (32U)
41190
41191/*! @name TCD_CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) Register */
41192/*! @{ */
41193#define DMA_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU)
41194#define DMA_TCD_CITER_ELINKNO_CITER_SHIFT (0U)
41195/*! CITER - Current Major Iteration Count
41196 */
41197#define DMA_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_CITER_SHIFT)) & DMA_TCD_CITER_ELINKNO_CITER_MASK)
41198#define DMA_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U)
41199#define DMA_TCD_CITER_ELINKNO_ELINK_SHIFT (15U)
41200/*! ELINK - Enable channel-to-channel linking on minor-loop complete
41201 * 0b0..The channel-to-channel linking is disabled
41202 * 0b1..The channel-to-channel linking is enabled
41203 */
41204#define DMA_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKNO_ELINK_MASK)
41205/*! @} */
41206
41207/* The count of DMA_TCD_CITER_ELINKNO */
41208#define DMA_TCD_CITER_ELINKNO_COUNT (32U)
41209
41210/*! @name TCD_CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) Register */
41211/*! @{ */
41212#define DMA_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU)
41213#define DMA_TCD_CITER_ELINKYES_CITER_SHIFT (0U)
41214/*! CITER - Current Major Iteration Count
41215 */
41216#define DMA_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_CITER_SHIFT)) & DMA_TCD_CITER_ELINKYES_CITER_MASK)
41217#define DMA_TCD_CITER_ELINKYES_LINKCH_MASK (0x3E00U) /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */
41218#define DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U)
41219/*! LINKCH - Minor Loop Link Channel Number
41220 */
41221#define DMA_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_CITER_ELINKYES_LINKCH_MASK) /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */
41222#define DMA_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U)
41223#define DMA_TCD_CITER_ELINKYES_ELINK_SHIFT (15U)
41224/*! ELINK - Enable channel-to-channel linking on minor-loop complete
41225 * 0b0..The channel-to-channel linking is disabled
41226 * 0b1..The channel-to-channel linking is enabled
41227 */
41228#define DMA_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_CITER_ELINKYES_ELINK_MASK)
41229/*! @} */
41230
41231/* The count of DMA_TCD_CITER_ELINKYES */
41232#define DMA_TCD_CITER_ELINKYES_COUNT (32U)
41233
41234/*! @name TCD_DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address Register */
41235/*! @{ */
41236#define DMA_TCD_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU)
41237#define DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT (0U)
41238/*! DLAST_SGA - Last Destination Address Adjustment / Scatter Gather Address
41239 */
41240#define DMA_TCD_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & DMA_TCD_DLAST_SGA_DLAST_SGA_MASK)
41241/*! @} */
41242
41243/* The count of DMA_TCD_DLAST_SGA */
41244#define DMA_TCD_DLAST_SGA_COUNT (32U)
41245
41246/*! @name TCD_CSR - TCD Control and Status Register */
41247/*! @{ */
41248#define DMA_TCD_CSR_START_MASK (0x1U)
41249#define DMA_TCD_CSR_START_SHIFT (0U)
41250/*! START - Channel Start
41251 * 0b0..The channel is not explicitly started.
41252 * 0b1..The channel is explicitly started via a software initiated service request.
41253 */
41254#define DMA_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_START_SHIFT)) & DMA_TCD_CSR_START_MASK)
41255#define DMA_TCD_CSR_INTMAJOR_MASK (0x2U)
41256#define DMA_TCD_CSR_INTMAJOR_SHIFT (1U)
41257/*! INTMAJOR - Enable an interrupt when major iteration count completes.
41258 * 0b0..The end-of-major loop interrupt is disabled.
41259 * 0b1..The end-of-major loop interrupt is enabled.
41260 */
41261#define DMA_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTMAJOR_SHIFT)) & DMA_TCD_CSR_INTMAJOR_MASK)
41262#define DMA_TCD_CSR_INTHALF_MASK (0x4U)
41263#define DMA_TCD_CSR_INTHALF_SHIFT (2U)
41264/*! INTHALF - Enable an interrupt when major counter is half complete.
41265 * 0b0..The half-point interrupt is disabled.
41266 * 0b1..The half-point interrupt is enabled.
41267 */
41268#define DMA_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_INTHALF_SHIFT)) & DMA_TCD_CSR_INTHALF_MASK)
41269#define DMA_TCD_CSR_DREQ_MASK (0x8U)
41270#define DMA_TCD_CSR_DREQ_SHIFT (3U)
41271/*! DREQ - Disable request
41272 * 0b0..No operation
41273 * 0b1..Clear the ERQ bit upon major loop completion, thus disabling hardware service requests.
41274 */
41275#define DMA_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
41276#define DMA_TCD_CSR_ESG_MASK (0x10U)
41277#define DMA_TCD_CSR_ESG_SHIFT (4U)
41278/*! ESG - Enable Scatter/Gather processing
41279 * 0b0..The current channel's TCD is normal format.
41280 * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer
41281 * to the next TCD to be loaded into this channel after the major loop completes its execution.
41282 */
41283#define DMA_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESG_SHIFT)) & DMA_TCD_CSR_ESG_MASK)
41284#define DMA_TCD_CSR_MAJORELINK_MASK (0x20U)
41285#define DMA_TCD_CSR_MAJORELINK_SHIFT (5U)
41286/*! MAJORELINK - Enable channel-to-channel linking on major loop complete
41287 * 0b0..The channel-to-channel linking is disabled.
41288 * 0b1..The channel-to-channel linking is enabled.
41289 */
41290#define DMA_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORELINK_SHIFT)) & DMA_TCD_CSR_MAJORELINK_MASK)
41291#define DMA_TCD_CSR_EEOP_MASK (0x40U)
41292#define DMA_TCD_CSR_EEOP_SHIFT (6U)
41293/*! EEOP - Enable end-of-packet processing
41294 * 0b0..The end-of-packet operation is disabled.
41295 * 0b1..The end-of-packet hardware input signal is enabled.
41296 */
41297#define DMA_TCD_CSR_EEOP(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_EEOP_SHIFT)) & DMA_TCD_CSR_EEOP_MASK)
41298#define DMA_TCD_CSR_ESDA_MASK (0x80U)
41299#define DMA_TCD_CSR_ESDA_SHIFT (7U)
41300/*! ESDA - Enable store destination address
41301 * 0b0..The store destination address to system memory operation is disabled.
41302 * 0b1..The store destination address to system memory operation is enabled.
41303 */
41304#define DMA_TCD_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_ESDA_SHIFT)) & DMA_TCD_CSR_ESDA_MASK)
41305#define DMA_TCD_CSR_MAJORLINKCH_MASK (0x1F00U) /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */
41306#define DMA_TCD_CSR_MAJORLINKCH_SHIFT (8U)
41307/*! MAJORLINKCH - Major loop link channel number
41308 */
41309#define DMA_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_MAJORLINKCH_SHIFT)) & DMA_TCD_CSR_MAJORLINKCH_MASK) /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */
41310#define DMA_TCD_CSR_BWC_MASK (0xC000U)
41311#define DMA_TCD_CSR_BWC_SHIFT (14U)
41312/*! BWC - Bandwidth Control
41313 * 0b00..No eDMA engine stalls.
41314 * 0b01..Reserved
41315 * 0b10..eDMA engine stalls for 4 cycles after each R/W.
41316 * 0b11..eDMA engine stalls for 8 cycles after each R/W.
41317 */
41318#define DMA_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_BWC_SHIFT)) & DMA_TCD_CSR_BWC_MASK)
41319/*! @} */
41320
41321/* The count of DMA_TCD_CSR */
41322#define DMA_TCD_CSR_COUNT (32U)
41323
41324/*! @name TCD_BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) Register */
41325/*! @{ */
41326#define DMA_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU)
41327#define DMA_TCD_BITER_ELINKNO_BITER_SHIFT (0U)
41328/*! BITER - Starting Major Iteration Count
41329 */
41330#define DMA_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_BITER_SHIFT)) & DMA_TCD_BITER_ELINKNO_BITER_MASK)
41331#define DMA_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U)
41332#define DMA_TCD_BITER_ELINKNO_ELINK_SHIFT (15U)
41333/*! ELINK - Enables channel-to-channel linking on minor loop complete
41334 * 0b0..The channel-to-channel linking is disabled
41335 * 0b1..The channel-to-channel linking is enabled
41336 */
41337#define DMA_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKNO_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKNO_ELINK_MASK)
41338/*! @} */
41339
41340/* The count of DMA_TCD_BITER_ELINKNO */
41341#define DMA_TCD_BITER_ELINKNO_COUNT (32U)
41342
41343/*! @name TCD_BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) Register */
41344/*! @{ */
41345#define DMA_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU)
41346#define DMA_TCD_BITER_ELINKYES_BITER_SHIFT (0U)
41347/*! BITER - Starting major iteration count
41348 */
41349#define DMA_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_BITER_SHIFT)) & DMA_TCD_BITER_ELINKYES_BITER_MASK)
41350#define DMA_TCD_BITER_ELINKYES_LINKCH_MASK (0x3E00U) /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */
41351#define DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U)
41352/*! LINKCH - Link Channel Number
41353 */
41354#define DMA_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_TCD_BITER_ELINKYES_LINKCH_MASK) /* Merged from fields with different position or width, of widths (3, 4, 5), largest definition used */
41355#define DMA_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U)
41356#define DMA_TCD_BITER_ELINKYES_ELINK_SHIFT (15U)
41357/*! ELINK - Enables channel-to-channel linking on minor loop complete
41358 * 0b0..The channel-to-channel linking is disabled
41359 * 0b1..The channel-to-channel linking is enabled
41360 */
41361#define DMA_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_TCD_BITER_ELINKYES_ELINK_SHIFT)) & DMA_TCD_BITER_ELINKYES_ELINK_MASK)
41362/*! @} */
41363
41364/* The count of DMA_TCD_BITER_ELINKYES */
41365#define DMA_TCD_BITER_ELINKYES_COUNT (32U)
41366
41367
41368/*!
41369 * @}
41370 */ /* end of group DMA_Register_Masks */
41371
41372
41373/* DMA - Peripheral instance base addresses */
41374/** Peripheral ADMA__EDMA0 base address */
41375#define ADMA__EDMA0_BASE (0x591F0000u)
41376/** Peripheral ADMA__EDMA0 base pointer */
41377#define ADMA__EDMA0 ((DMA_Type *)ADMA__EDMA0_BASE)
41378/** Peripheral ADMA__EDMA1 base address */
41379#define ADMA__EDMA1_BASE (0x599F0000u)
41380/** Peripheral ADMA__EDMA1 base pointer */
41381#define ADMA__EDMA1 ((DMA_Type *)ADMA__EDMA1_BASE)
41382/** Peripheral ADMA__EDMA2 base address */
41383#define ADMA__EDMA2_BASE (0x5A1F0000u)
41384/** Peripheral ADMA__EDMA2 base pointer */
41385#define ADMA__EDMA2 ((DMA_Type *)ADMA__EDMA2_BASE)
41386/** Peripheral ADMA__EDMA3 base address */
41387#define ADMA__EDMA3_BASE (0x5A9F0000u)
41388/** Peripheral ADMA__EDMA3 base pointer */
41389#define ADMA__EDMA3 ((DMA_Type *)ADMA__EDMA3_BASE)
41390/** Peripheral CONNECTIVITY__EDMA base address */
41391#define CONNECTIVITY__EDMA_BASE (0x5B070000u)
41392/** Peripheral CONNECTIVITY__EDMA base pointer */
41393#define CONNECTIVITY__EDMA ((DMA_Type *)CONNECTIVITY__EDMA_BASE)
41394/** Array initializer of DMA peripheral base addresses */
41395#define DMA_BASE_ADDRS { ADMA__EDMA0_BASE, ADMA__EDMA1_BASE, ADMA__EDMA2_BASE, ADMA__EDMA3_BASE, CONNECTIVITY__EDMA_BASE }
41396/** Array initializer of DMA peripheral base pointers */
41397#define DMA_BASE_PTRS { ADMA__EDMA0, ADMA__EDMA1, ADMA__EDMA2, ADMA__EDMA3, CONNECTIVITY__EDMA }
41398/** Interrupt vectors for the DMA peripheral type */
41399#define DMA_IRQS { { ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn, ADMA_EDMA0_INT_IRQn }, \
41400 { ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn, ADMA_EDMA1_INT_IRQn }, \
41401 { ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn, ADMA_EDMA2_INT_IRQn }, \
41402 { ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn, ADMA_EDMA3_INT_IRQn }, \
41403 { CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn, CONNECTIVITY_DMA_INT_IRQn } }
41404#define DMA_ERROR_IRQS { ADMA_EDMA0_ERR_INT_IRQn, ADMA_EDMA1_ERR_INT_IRQn, ADMA_EDMA2_ERR_INT_IRQn, ADMA_EDMA3_ERR_INT_IRQn, CONNECTIVITY_DMA_ERR_INT_IRQn }
41405
41406/*!
41407 * @}
41408 */ /* end of group DMA_Peripheral_Access_Layer */
41409
41410
41411/* ----------------------------------------------------------------------------
41412 -- DPR Peripheral Access Layer
41413 ---------------------------------------------------------------------------- */
41414
41415/*!
41416 * @addtogroup DPR_Peripheral_Access_Layer DPR Peripheral Access Layer
41417 * @{
41418 */
41419
41420/** DPR - Register Layout Typedef */
41421typedef struct {
41422 struct { /* offset: 0x0 */
41423 __IO uint32_t RW; /**< System Control 0, offset: 0x0 */
41424 __IO uint32_t SET; /**< System Control 0, offset: 0x4 */
41425 __IO uint32_t CLR; /**< System Control 0, offset: 0x8 */
41426 __IO uint32_t TOG; /**< System Control 0, offset: 0xC */
41427 } SYSTEM_CTRL0;
41428 uint8_t RESERVED_0[16];
41429 struct { /* offset: 0x20 */
41430 __IO uint32_t RW; /**< Interrupt Mask, offset: 0x20 */
41431 __IO uint32_t SET; /**< Interrupt Mask, offset: 0x24 */
41432 __IO uint32_t CLR; /**< Interrupt Mask, offset: 0x28 */
41433 __IO uint32_t TOG; /**< Interrupt Mask, offset: 0x2C */
41434 } IRQ_MASK;
41435 struct { /* offset: 0x30 */
41436 __I uint32_t RW; /**< Status Register of Masked IRQ, offset: 0x30 */
41437 __I uint32_t SET; /**< Status Register of Masked IRQ, offset: 0x34 */
41438 __I uint32_t CLR; /**< Status Register of Masked IRQ, offset: 0x38 */
41439 __I uint32_t TOG; /**< Status Register of Masked IRQ, offset: 0x3C */
41440 } IRQ_MASK_STATUS;
41441 struct { /* offset: 0x40 */
41442 __IO uint32_t RW; /**< Status of Non-Masked IRQ, offset: 0x40 */
41443 __IO uint32_t SET; /**< Status of Non-Masked IRQ, offset: 0x44 */
41444 __IO uint32_t CLR; /**< Status of Non-Masked IRQ, offset: 0x48 */
41445 __IO uint32_t TOG; /**< Status of Non-Masked IRQ, offset: 0x4C */
41446 } IRQ_NONMASK_STATUS;
41447 struct { /* offset: 0x50 */
41448 __IO uint32_t RW; /**< Mode Control 0, offset: 0x50 */
41449 __IO uint32_t SET; /**< Mode Control 0, offset: 0x54 */
41450 __IO uint32_t CLR; /**< Mode Control 0, offset: 0x58 */
41451 __IO uint32_t TOG; /**< Mode Control 0, offset: 0x5C */
41452 } MODE_CTRL0;
41453 uint8_t RESERVED_1[16];
41454 struct { /* offset: 0x70 */
41455 __IO uint32_t RW; /**< Frame Control 0, offset: 0x70 */
41456 __IO uint32_t SET; /**< Frame Control 0, offset: 0x74 */
41457 __IO uint32_t CLR; /**< Frame Control 0, offset: 0x78 */
41458 __IO uint32_t TOG; /**< Frame Control 0, offset: 0x7C */
41459 } FRAME_CTRL0;
41460 uint8_t RESERVED_2[16];
41461 struct { /* offset: 0x90 */
41462 __IO uint32_t RW; /**< Frame 1-Plane Control 0, offset: 0x90 */
41463 __IO uint32_t SET; /**< Frame 1-Plane Control 0, offset: 0x94 */
41464 __IO uint32_t CLR; /**< Frame 1-Plane Control 0, offset: 0x98 */
41465 __IO uint32_t TOG; /**< Frame 1-Plane Control 0, offset: 0x9C */
41466 } FRAME_1P_CTRL0;
41467 struct { /* offset: 0xA0 */
41468 __IO uint32_t RW; /**< Frame 1-Plane Pix X Control, offset: 0xA0 */
41469 __IO uint32_t SET; /**< Frame 1-Plane Pix X Control, offset: 0xA4 */
41470 __IO uint32_t CLR; /**< Frame 1-Plane Pix X Control, offset: 0xA8 */
41471 __IO uint32_t TOG; /**< Frame 1-Plane Pix X Control, offset: 0xAC */
41472 } FRAME_1P_PIX_X_CTRL;
41473 struct { /* offset: 0xB0 */
41474 __IO uint32_t RW; /**< Frame 1-Plane Pix Y Control, offset: 0xB0 */
41475 __IO uint32_t SET; /**< Frame 1-Plane Pix Y Control, offset: 0xB4 */
41476 __IO uint32_t CLR; /**< Frame 1-Plane Pix Y Control, offset: 0xB8 */
41477 __IO uint32_t TOG; /**< Frame 1-Plane Pix Y Control, offset: 0xBC */
41478 } FRAME_1P_PIX_Y_CTRL;
41479 struct { /* offset: 0xC0 */
41480 __IO uint32_t RW; /**< Frame 1-Plane Base Address Control 0, offset: 0xC0 */
41481 __IO uint32_t SET; /**< Frame 1-Plane Base Address Control 0, offset: 0xC4 */
41482 __IO uint32_t CLR; /**< Frame 1-Plane Base Address Control 0, offset: 0xC8 */
41483 __IO uint32_t TOG; /**< Frame 1-Plane Base Address Control 0, offset: 0xCC */
41484 } FRAME_1P_BASE_ADDR_CTRL0;
41485 uint8_t RESERVED_3[16];
41486 struct { /* offset: 0xE0 */
41487 __IO uint32_t RW; /**< Frame 2-Plane Control 0, offset: 0xE0 */
41488 __IO uint32_t SET; /**< Frame 2-Plane Control 0, offset: 0xE4 */
41489 __IO uint32_t CLR; /**< Frame 2-Plane Control 0, offset: 0xE8 */
41490 __IO uint32_t TOG; /**< Frame 2-Plane Control 0, offset: 0xEC */
41491 } FRAME_2P_CTRL0;
41492 struct { /* offset: 0xF0 */
41493 __IO uint32_t RW; /**< Frame Pixel X Upper Left Coordinate Control, offset: 0xF0 */
41494 __IO uint32_t SET; /**< Frame Pixel X Upper Left Coordinate Control, offset: 0xF4 */
41495 __IO uint32_t CLR; /**< Frame Pixel X Upper Left Coordinate Control, offset: 0xF8 */
41496 __IO uint32_t TOG; /**< Frame Pixel X Upper Left Coordinate Control, offset: 0xFC */
41497 } FRAME_PIX_X_ULC_CTRL;
41498 struct { /* offset: 0x100 */
41499 __IO uint32_t RW; /**< Frame Pixel Y Upper Left Coordinate Control, offset: 0x100 */
41500 __IO uint32_t SET; /**< Frame Pixel Y Upper Left Coordinate Control, offset: 0x104 */
41501 __IO uint32_t CLR; /**< Frame Pixel Y Upper Left Coordinate Control, offset: 0x108 */
41502 __IO uint32_t TOG; /**< Frame Pixel Y Upper Left Coordinate Control, offset: 0x10C */
41503 } FRAME_PIX_Y_ULC_CTRL;
41504 struct { /* offset: 0x110 */
41505 __IO uint32_t RW; /**< Frame 2-Plane Base Address Control 0, offset: 0x110 */
41506 __IO uint32_t SET; /**< Frame 2-Plane Base Address Control 0, offset: 0x114 */
41507 __IO uint32_t CLR; /**< Frame 2-Plane Base Address Control 0, offset: 0x118 */
41508 __IO uint32_t TOG; /**< Frame 2-Plane Base Address Control 0, offset: 0x11C */
41509 } FRAME_2P_BASE_ADDR_CTRL0;
41510 uint8_t RESERVED_4[16];
41511 struct { /* offset: 0x130 */
41512 __IO uint32_t RW; /**< Status Control 0, offset: 0x130 */
41513 __IO uint32_t SET; /**< Status Control 0, offset: 0x134 */
41514 __IO uint32_t CLR; /**< Status Control 0, offset: 0x138 */
41515 __IO uint32_t TOG; /**< Status Control 0, offset: 0x13C */
41516 } STATUS_CTRL0;
41517 struct { /* offset: 0x140 */
41518 __I uint32_t RW; /**< Status Control 1, offset: 0x140 */
41519 __I uint32_t SET; /**< Status Control 1, offset: 0x144 */
41520 __I uint32_t CLR; /**< Status Control 1, offset: 0x148 */
41521 __I uint32_t TOG; /**< Status Control 1, offset: 0x14C */
41522 } STATUS_CTRL1;
41523 uint8_t RESERVED_5[176];
41524 struct { /* offset: 0x200 */
41525 __IO uint32_t RW; /**< RTRAM Control 0, offset: 0x200 */
41526 __IO uint32_t SET; /**< RTRAM Control 0, offset: 0x204 */
41527 __IO uint32_t CLR; /**< RTRAM Control 0, offset: 0x208 */
41528 __IO uint32_t TOG; /**< RTRAM Control 0, offset: 0x20C */
41529 } RTRAM_CTRL0;
41530} DPR_Type;
41531
41532/* ----------------------------------------------------------------------------
41533 -- DPR Register Masks
41534 ---------------------------------------------------------------------------- */
41535
41536/*!
41537 * @addtogroup DPR_Register_Masks DPR Register Masks
41538 * @{
41539 */
41540
41541/*! @name SYSTEM_CTRL0 - System Control 0 */
41542/*! @{ */
41543#define DPR_SYSTEM_CTRL0_RUN_EN_MASK (0x1U)
41544#define DPR_SYSTEM_CTRL0_RUN_EN_SHIFT (0U)
41545/*! RUN_EN - Run Enable
41546 */
41547#define DPR_SYSTEM_CTRL0_RUN_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_RUN_EN_SHIFT)) & DPR_SYSTEM_CTRL0_RUN_EN_MASK)
41548#define DPR_SYSTEM_CTRL0_SOFT_RESET_MASK (0x2U)
41549#define DPR_SYSTEM_CTRL0_SOFT_RESET_SHIFT (1U)
41550/*! SOFT_RESET - Soft Reset
41551 */
41552#define DPR_SYSTEM_CTRL0_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SOFT_RESET_SHIFT)) & DPR_SYSTEM_CTRL0_SOFT_RESET_MASK)
41553#define DPR_SYSTEM_CTRL0_REPEAT_EN_MASK (0x4U)
41554#define DPR_SYSTEM_CTRL0_REPEAT_EN_SHIFT (2U)
41555/*! REPEAT_EN - Repeat Enable
41556 */
41557#define DPR_SYSTEM_CTRL0_REPEAT_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_REPEAT_EN_SHIFT)) & DPR_SYSTEM_CTRL0_REPEAT_EN_MASK)
41558#define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_MASK (0x8U)
41559#define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_SHIFT (3U)
41560/*! SHADOW_LOAD_EN - Shadow Load Enable
41561 */
41562#define DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_SHIFT)) & DPR_SYSTEM_CTRL0_SHADOW_LOAD_EN_MASK)
41563#define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_MASK (0x10U)
41564#define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_SHIFT (4U)
41565/*! SW_SHADOW_LOAD_SEL - Software Shadow Load Select
41566 */
41567#define DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_SHIFT)) & DPR_SYSTEM_CTRL0_SW_SHADOW_LOAD_SEL_MASK)
41568#define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_MASK (0x10000U)
41569#define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_SHIFT (16U)
41570/*! BCMD2AXI_MSTR_ID_CTRL - Buscmd To AXI Master ID Control
41571 */
41572#define DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_SHIFT)) & DPR_SYSTEM_CTRL0_BCMD2AXI_MSTR_ID_CTRL_MASK)
41573/*! @} */
41574
41575/*! @name IRQ_MASK - Interrupt Mask */
41576/*! @{ */
41577#define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_MASK (0x1U)
41578#define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_SHIFT (0U)
41579/*! IRQ_DPR_CTRL_DONE - DPR Control Done IRQ Mask
41580 */
41581#define DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_CTRL_DONE_MASK)
41582#define DPR_IRQ_MASK_IRQ_DPR_RUN_MASK (0x2U)
41583#define DPR_IRQ_MASK_IRQ_DPR_RUN_SHIFT (1U)
41584/*! IRQ_DPR_RUN - DPR Run IRQ Mask
41585 */
41586#define DPR_IRQ_MASK_IRQ_DPR_RUN(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_RUN_MASK)
41587#define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_MASK (0x4U)
41588#define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_SHIFT (2U)
41589/*! IRQ_DPR_SHADOW_LOADED_MASK - DPR Shadow Loaded IRQ Mask
41590 */
41591#define DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_SHIFT)) & DPR_IRQ_MASK_IRQ_DPR_SHADOW_LOADED_MASK_MASK)
41592#define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_MASK (0x8U)
41593#define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_SHIFT (3U)
41594/*! IRQ_AXI_READ_ERROR - AXI Read Error IRQ Mask
41595 */
41596#define DPR_IRQ_MASK_IRQ_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_MASK_IRQ_AXI_READ_ERROR_MASK)
41597#define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U)
41598#define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U)
41599/*! DPR2RTR_YRGB_FIFO_OVFL - DPR to RTRAM YRGB Fifo Overflow IRQ Mask
41600 */
41601#define DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_YRGB_FIFO_OVFL_MASK)
41602#define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_MASK (0x20U)
41603#define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_SHIFT (5U)
41604/*! DPR2RTR_UV_FIFO_OVFL - DPR to RTRAM UV Fifo Overflow IRQ Mask
41605 */
41606#define DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_UV_FIFO_OVFL_MASK)
41607#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U)
41608#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U)
41609/*! DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR - DPR to RTRAM Fifo load YRGB buffer ready IRQ error Mask
41610 */
41611#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK)
41612#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U)
41613#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U)
41614/*! DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR - DPR to RTRAM Fifo load UV buffer ready IRQ error Mask
41615 */
41616#define DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_MASK_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK)
41617/*! @} */
41618
41619/*! @name IRQ_MASK_STATUS - Status Register of Masked IRQ */
41620/*! @{ */
41621#define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_MASK (0x1U)
41622#define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT (0U)
41623/*! IRQ_DPR_CTRL_DONE - DPR Control Done Masked IRQ
41624 */
41625#define DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_CTRL_DONE_MASK)
41626#define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_MASK (0x2U)
41627#define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_SHIFT (1U)
41628/*! IRQ_DPR_RUN - DPR Run Masked IRQ
41629 */
41630#define DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_RUN_MASK)
41631#define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_MASK (0x4U)
41632#define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_SHIFT (2U)
41633/*! IRQ_DPR_SHADOW_LOADED - DPR Shadow Loaded Masked IRQ
41634 */
41635#define DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_DPR_SHADOW_LOADED_MASK)
41636#define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_MASK (0x8U)
41637#define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT (3U)
41638/*! IRQ_AXI_READ_ERROR - AXI Read Error Masked IRQ
41639 */
41640#define DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_IRQ_AXI_READ_ERROR_MASK)
41641#define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U)
41642#define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U)
41643/*! DPR2RTR_YRGB_FIFO_OVFL - DPR to RTRAM YRGB Fifo Overflow Masked IRQ
41644 */
41645#define DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK)
41646#define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK (0x20U)
41647#define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT (5U)
41648/*! DPR2RTR_UV_FIFO_OVFL - DPR to RTRAM UV Fifo Overflow Masked IRQ
41649 */
41650#define DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK)
41651#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U)
41652#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U)
41653/*! DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR - DPR to RTRAM Fifo load YRGB buffer error Masked IRQ
41654 */
41655#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK)
41656#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U)
41657#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U)
41658/*! DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR - DPR to RTRAM Fifo load UV buffer error Masked IRQ
41659 */
41660#define DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_MASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK)
41661/*! @} */
41662
41663/*! @name IRQ_NONMASK_STATUS - Status of Non-Masked IRQ */
41664/*! @{ */
41665#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_MASK (0x1U)
41666#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT (0U)
41667/*! IRQ_DPR_CTRL_DONE - DPR Control Done Non-Masked IRQ
41668 */
41669#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_CTRL_DONE_MASK)
41670#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_MASK (0x2U)
41671#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_SHIFT (1U)
41672/*! IRQ_DPR_RUN - DPR Run Non-Masked IRQ
41673 */
41674#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_RUN_MASK)
41675#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_MASK (0x4U)
41676#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_SHIFT (2U)
41677/*! IRQ_DPR_SHADOW_LOADED_NMSTAT - DPR Shadow Loaded Non-Masked IRQ
41678 */
41679#define DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_DPR_SHADOW_LOADED_NMSTAT_MASK)
41680#define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_MASK (0x8U)
41681#define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT (3U)
41682/*! IRQ_AXI_READ_ERROR - AXI Read Error Non-Masked IRQ
41683 */
41684#define DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_IRQ_AXI_READ_ERROR_MASK)
41685#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK (0x10U)
41686#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT (4U)
41687/*! DPR2RTR_YRGB_FIFO_OVFL - DPR to RTRAM YRGB Fifo Overflow Non-Masked IRQ
41688 */
41689#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_YRGB_FIFO_OVFL_MASK)
41690#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK (0x20U)
41691#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT (5U)
41692/*! DPR2RTR_UV_FIFO_OVFL - DPR to RTRAM UV Fifo Overflow Non-Masked IRQ
41693 */
41694#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_UV_FIFO_OVFL_MASK)
41695#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK (0x40U)
41696#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT (6U)
41697/*! DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR - DPR to RTRAM Fifo load YRGB buffer ready error Non-Masked IRQ
41698 */
41699#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_YRGB_ERROR_MASK)
41700#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK (0x80U)
41701#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT (7U)
41702/*! DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR - DPR to RTRAM Fifo load UV buffer ready error Non-Masked IRQ
41703 */
41704#define DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_SHIFT)) & DPR_IRQ_NONMASK_STATUS_DPR2RTR_FIFO_LOAD_BUF_RDY_UV_ERROR_MASK)
41705/*! @} */
41706
41707/*! @name MODE_CTRL0 - Mode Control 0 */
41708/*! @{ */
41709#define DPR_MODE_CTRL0_RTR_3BUF_EN_MASK (0x1U)
41710#define DPR_MODE_CTRL0_RTR_3BUF_EN_SHIFT (0U)
41711/*! RTR_3BUF_EN - RTRAM Buffer Implementation
41712 */
41713#define DPR_MODE_CTRL0_RTR_3BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_RTR_3BUF_EN_SHIFT)) & DPR_MODE_CTRL0_RTR_3BUF_EN_MASK)
41714#define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_MASK (0x2U)
41715#define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_SHIFT (1U)
41716/*! RTR_4LINE_BUF_EN - RTRAM Lines Per Buffer
41717 */
41718#define DPR_MODE_CTRL0_RTR_4LINE_BUF_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_SHIFT)) & DPR_MODE_CTRL0_RTR_4LINE_BUF_EN_MASK)
41719#define DPR_MODE_CTRL0_TILE_TYPE_MASK (0xCU)
41720#define DPR_MODE_CTRL0_TILE_TYPE_SHIFT (2U)
41721/*! TILE_TYPE - Tile Type
41722 */
41723#define DPR_MODE_CTRL0_TILE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_TILE_TYPE_SHIFT)) & DPR_MODE_CTRL0_TILE_TYPE_MASK)
41724#define DPR_MODE_CTRL0_YUV_EN_MASK (0x10U)
41725#define DPR_MODE_CTRL0_YUV_EN_SHIFT (4U)
41726/*! YUV_EN - YUV Enable
41727 */
41728#define DPR_MODE_CTRL0_YUV_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_YUV_EN_SHIFT)) & DPR_MODE_CTRL0_YUV_EN_MASK)
41729#define DPR_MODE_CTRL0_COMP_2PLANE_EN_MASK (0x20U)
41730#define DPR_MODE_CTRL0_COMP_2PLANE_EN_SHIFT (5U)
41731/*! COMP_2PLANE_EN - Component 2-Plane Enable
41732 */
41733#define DPR_MODE_CTRL0_COMP_2PLANE_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_COMP_2PLANE_EN_SHIFT)) & DPR_MODE_CTRL0_COMP_2PLANE_EN_MASK)
41734#define DPR_MODE_CTRL0_PIX_SIZE_MASK (0xC0U)
41735#define DPR_MODE_CTRL0_PIX_SIZE_SHIFT (6U)
41736/*! PIX_SIZE - Pixel Size
41737 */
41738#define DPR_MODE_CTRL0_PIX_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_SIZE_SHIFT)) & DPR_MODE_CTRL0_PIX_SIZE_MASK)
41739#define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_MASK (0x100U)
41740#define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_SHIFT (8U)
41741/*! PIX_LUMA_UV_SWAP - Pixel luma/UV position Swap
41742 */
41743#define DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_SHIFT)) & DPR_MODE_CTRL0_PIX_LUMA_UV_SWAP_MASK)
41744#define DPR_MODE_CTRL0_PIX_UV_SWAP_MASK (0x200U)
41745#define DPR_MODE_CTRL0_PIX_UV_SWAP_SHIFT (9U)
41746/*! PIX_UV_SWAP - Pixel UV Swap
41747 */
41748#define DPR_MODE_CTRL0_PIX_UV_SWAP(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_PIX_UV_SWAP_SHIFT)) & DPR_MODE_CTRL0_PIX_UV_SWAP_MASK)
41749#define DPR_MODE_CTRL0_B_COMP_SEL_MASK (0xC00U)
41750#define DPR_MODE_CTRL0_B_COMP_SEL_SHIFT (10U)
41751/*! B_COMP_SEL - B Component Select
41752 */
41753#define DPR_MODE_CTRL0_B_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_B_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_B_COMP_SEL_MASK)
41754#define DPR_MODE_CTRL0_G_COMP_SEL_MASK (0x3000U)
41755#define DPR_MODE_CTRL0_G_COMP_SEL_SHIFT (12U)
41756/*! G_COMP_SEL - G Component Select
41757 */
41758#define DPR_MODE_CTRL0_G_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_G_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_G_COMP_SEL_MASK)
41759#define DPR_MODE_CTRL0_R_COMP_SEL_MASK (0xC000U)
41760#define DPR_MODE_CTRL0_R_COMP_SEL_SHIFT (14U)
41761/*! R_COMP_SEL - R Component Select
41762 */
41763#define DPR_MODE_CTRL0_R_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_R_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_R_COMP_SEL_MASK)
41764#define DPR_MODE_CTRL0_A_COMP_SEL_MASK (0x30000U)
41765#define DPR_MODE_CTRL0_A_COMP_SEL_SHIFT (16U)
41766/*! A_COMP_SEL - A Component Select
41767 */
41768#define DPR_MODE_CTRL0_A_COMP_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_MODE_CTRL0_A_COMP_SEL_SHIFT)) & DPR_MODE_CTRL0_A_COMP_SEL_MASK)
41769/*! @} */
41770
41771/*! @name FRAME_CTRL0 - Frame Control 0 */
41772/*! @{ */
41773#define DPR_FRAME_CTRL0_HFLIP_EN_MASK (0x1U)
41774#define DPR_FRAME_CTRL0_HFLIP_EN_SHIFT (0U)
41775/*! HFLIP_EN - Horizontal Flip Enable
41776 */
41777#define DPR_FRAME_CTRL0_HFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_HFLIP_EN_SHIFT)) & DPR_FRAME_CTRL0_HFLIP_EN_MASK)
41778#define DPR_FRAME_CTRL0_VFLIP_EN_MASK (0x2U)
41779#define DPR_FRAME_CTRL0_VFLIP_EN_SHIFT (1U)
41780/*! VFLIP_EN - Vertical Flip Enable
41781 */
41782#define DPR_FRAME_CTRL0_VFLIP_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_VFLIP_EN_SHIFT)) & DPR_FRAME_CTRL0_VFLIP_EN_MASK)
41783#define DPR_FRAME_CTRL0_ROT_ENC_MASK (0xCU)
41784#define DPR_FRAME_CTRL0_ROT_ENC_SHIFT (2U)
41785/*! ROT_ENC - Encoded Rotation
41786 */
41787#define DPR_FRAME_CTRL0_ROT_ENC(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_ROT_ENC_SHIFT)) & DPR_FRAME_CTRL0_ROT_ENC_MASK)
41788#define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_MASK (0x10U)
41789#define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_SHIFT (4U)
41790/*! ROT_FLIP_ORDER_EN - Rotation Flip Order
41791 */
41792#define DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_SHIFT)) & DPR_FRAME_CTRL0_ROT_FLIP_ORDER_EN_MASK)
41793#define DPR_FRAME_CTRL0_PITCH_MASK (0xFFFF0000U)
41794#define DPR_FRAME_CTRL0_PITCH_SHIFT (16U)
41795/*! PITCH - Image Pitch
41796 */
41797#define DPR_FRAME_CTRL0_PITCH(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_CTRL0_PITCH_SHIFT)) & DPR_FRAME_CTRL0_PITCH_MASK)
41798/*! @} */
41799
41800/*! @name FRAME_1P_CTRL0 - Frame 1-Plane Control 0 */
41801/*! @{ */
41802#define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_MASK (0x7U)
41803#define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_SHIFT (0U)
41804/*! MAX_BYTES_PREQ - Max Bytes Per Request
41805 */
41806#define DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_SHIFT)) & DPR_FRAME_1P_CTRL0_MAX_BYTES_PREQ_MASK)
41807/*! @} */
41808
41809/*! @name FRAME_1P_PIX_X_CTRL - Frame 1-Plane Pix X Control */
41810/*! @{ */
41811#define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_MASK (0xFFFFU)
41812#define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_SHIFT (0U)
41813/*! NUM_X_PIX_WIDE - Number of Pixels Wide in X-direction
41814 */
41815#define DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_SHIFT)) & DPR_FRAME_1P_PIX_X_CTRL_NUM_X_PIX_WIDE_MASK)
41816/*! @} */
41817
41818/*! @name FRAME_1P_PIX_Y_CTRL - Frame 1-Plane Pix Y Control */
41819/*! @{ */
41820#define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_MASK (0xFFFFU)
41821#define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_SHIFT (0U)
41822/*! NUM_Y_PIX_HIGH - Number of Pixels High in Y-direction
41823 */
41824#define DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_SHIFT)) & DPR_FRAME_1P_PIX_Y_CTRL_NUM_Y_PIX_HIGH_MASK)
41825/*! @} */
41826
41827/*! @name FRAME_1P_BASE_ADDR_CTRL0 - Frame 1-Plane Base Address Control 0 */
41828/*! @{ */
41829#define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_MASK (0xFFFFFFFFU)
41830#define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT (0U)
41831/*! BASE_ADDR - Base Address
41832 */
41833#define DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT)) & DPR_FRAME_1P_BASE_ADDR_CTRL0_BASE_ADDR_MASK)
41834/*! @} */
41835
41836/*! @name FRAME_2P_CTRL0 - Frame 2-Plane Control 0 */
41837/*! @{ */
41838#define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_MASK (0x7U)
41839#define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_SHIFT (0U)
41840/*! MAX_BYTES_PREQ - Max Bytes Per Request
41841 */
41842#define DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_SHIFT)) & DPR_FRAME_2P_CTRL0_MAX_BYTES_PREQ_MASK)
41843/*! @} */
41844
41845/*! @name FRAME_PIX_X_ULC_CTRL - Frame Pixel X Upper Left Coordinate Control */
41846/*! @{ */
41847#define DPR_FRAME_PIX_X_ULC_CTRL_CROP_ULC_X_MASK (0xFFFFU)
41848#define DPR_FRAME_PIX_X_ULC_CTRL_CROP_ULC_X_SHIFT (0U)
41849/*! CROP_ULC_X - Starting Coordinate of Cropped Image X (1-Plane or 2-Plane Luma)
41850 */
41851#define DPR_FRAME_PIX_X_ULC_CTRL_CROP_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_PIX_X_ULC_CTRL_CROP_ULC_X_SHIFT)) & DPR_FRAME_PIX_X_ULC_CTRL_CROP_ULC_X_MASK)
41852/*! @} */
41853
41854/*! @name FRAME_PIX_Y_ULC_CTRL - Frame Pixel Y Upper Left Coordinate Control */
41855/*! @{ */
41856#define DPR_FRAME_PIX_Y_ULC_CTRL_CROP_ULC_y_MASK (0xFFFFU)
41857#define DPR_FRAME_PIX_Y_ULC_CTRL_CROP_ULC_y_SHIFT (0U)
41858/*! CROP_ULC_y - Starting Coordinate of Cropped Image X (1-Plane or 2-Plane Luma)
41859 */
41860#define DPR_FRAME_PIX_Y_ULC_CTRL_CROP_ULC_y(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_PIX_Y_ULC_CTRL_CROP_ULC_y_SHIFT)) & DPR_FRAME_PIX_Y_ULC_CTRL_CROP_ULC_y_MASK)
41861/*! @} */
41862
41863/*! @name FRAME_2P_BASE_ADDR_CTRL0 - Frame 2-Plane Base Address Control 0 */
41864/*! @{ */
41865#define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_MASK (0xFFFFFFFFU)
41866#define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT (0U)
41867/*! BASE_ADDR - Base Address
41868 */
41869#define DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_SHIFT)) & DPR_FRAME_2P_BASE_ADDR_CTRL0_BASE_ADDR_MASK)
41870/*! @} */
41871
41872/*! @name STATUS_CTRL0 - Status Control 0 */
41873/*! @{ */
41874#define DPR_STATUS_CTRL0_STATUS_MUX_SEL_MASK (0x7U)
41875#define DPR_STATUS_CTRL0_STATUS_MUX_SEL_SHIFT (0U)
41876/*! STATUS_MUX_SEL - Status Mux Select
41877 */
41878#define DPR_STATUS_CTRL0_STATUS_MUX_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_STATUS_CTRL0_STATUS_MUX_SEL_SHIFT)) & DPR_STATUS_CTRL0_STATUS_MUX_SEL_MASK)
41879#define DPR_STATUS_CTRL0_STATUS_SRC_SEL_MASK (0x70000U)
41880#define DPR_STATUS_CTRL0_STATUS_SRC_SEL_SHIFT (16U)
41881/*! STATUS_SRC_SEL - Status Source Select
41882 */
41883#define DPR_STATUS_CTRL0_STATUS_SRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_STATUS_CTRL0_STATUS_SRC_SEL_SHIFT)) & DPR_STATUS_CTRL0_STATUS_SRC_SEL_MASK)
41884/*! @} */
41885
41886/*! @name STATUS_CTRL1 - Status Control 1 */
41887/*! @{ */
41888#define DPR_STATUS_CTRL1_STATUS_MASK (0xFFFFFFFFU)
41889#define DPR_STATUS_CTRL1_STATUS_SHIFT (0U)
41890/*! STATUS - Status Register
41891 */
41892#define DPR_STATUS_CTRL1_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DPR_STATUS_CTRL1_STATUS_SHIFT)) & DPR_STATUS_CTRL1_STATUS_MASK)
41893/*! @} */
41894
41895/*! @name RTRAM_CTRL0 - RTRAM Control 0 */
41896/*! @{ */
41897#define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_MASK (0x1U)
41898#define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_SHIFT (0U)
41899/*! NUM_ROWS_ACTIVE - Number of Rows Active
41900 */
41901#define DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_SHIFT)) & DPR_RTRAM_CTRL0_NUM_ROWS_ACTIVE_MASK)
41902#define DPR_RTRAM_CTRL0_THRES_HIGH_MASK (0xEU)
41903#define DPR_RTRAM_CTRL0_THRES_HIGH_SHIFT (1U)
41904/*! THRES_HIGH - Threshold High
41905 */
41906#define DPR_RTRAM_CTRL0_THRES_HIGH(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_THRES_HIGH_SHIFT)) & DPR_RTRAM_CTRL0_THRES_HIGH_MASK)
41907#define DPR_RTRAM_CTRL0_THRES_LOW_MASK (0x70U)
41908#define DPR_RTRAM_CTRL0_THRES_LOW_SHIFT (4U)
41909/*! THRES_LOW - Threshold Low
41910 */
41911#define DPR_RTRAM_CTRL0_THRES_LOW(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_THRES_LOW_SHIFT)) & DPR_RTRAM_CTRL0_THRES_LOW_MASK)
41912#define DPR_RTRAM_CTRL0_ABORT_SEL_MASK (0x80U)
41913#define DPR_RTRAM_CTRL0_ABORT_SEL_SHIFT (7U)
41914/*! ABORT_SEL - Abort Select
41915 */
41916#define DPR_RTRAM_CTRL0_ABORT_SEL(x) (((uint32_t)(((uint32_t)(x)) << DPR_RTRAM_CTRL0_ABORT_SEL_SHIFT)) & DPR_RTRAM_CTRL0_ABORT_SEL_MASK)
41917/*! @} */
41918
41919
41920/*!
41921 * @}
41922 */ /* end of group DPR_Register_Masks */
41923
41924
41925/* DPR - Peripheral instance base addresses */
41926/** Peripheral DC__DPR0 base address */
41927#define DC__DPR0_BASE (0x560D0000u)
41928/** Peripheral DC__DPR0 base pointer */
41929#define DC__DPR0 ((DPR_Type *)DC__DPR0_BASE)
41930/** Peripheral DC__DPR1 base address */
41931#define DC__DPR1_BASE (0x56100000u)
41932/** Peripheral DC__DPR1 base pointer */
41933#define DC__DPR1 ((DPR_Type *)DC__DPR1_BASE)
41934/** Array initializer of DPR peripheral base addresses */
41935#define DPR_BASE_ADDRS { DC__DPR0_BASE, DC__DPR1_BASE }
41936/** Array initializer of DPR peripheral base pointers */
41937#define DPR_BASE_PTRS { DC__DPR0, DC__DPR1 }
41938/* Backward compatibility */
41939/** Peripheral DC__DPR0_CH0 base address */
41940#define DC__DPR0_CH0_BASE DC__DPR0_BASE
41941/** Peripheral DC__DPR0_CH0 base pointer */
41942#define DC__DPR0_CH0 ((DPR_Type *)DC__DPR0_CH0_BASE)
41943/** Peripheral DC__DPR0_CH1 base address */
41944#define DC__DPR0_CH1_BASE (0x560E0000u)
41945/** Peripheral DC__DPR0_CH1 base pointer */
41946#define DC__DPR0_CH1 ((DPR_Type *)DC__DPR0_CH1_BASE)
41947/** Peripheral DC__DPR0_CH2 base address */
41948#define DC__DPR0_CH2_BASE (0x560F0000u)
41949/** Peripheral DC__DPR0_CH2 base pointer */
41950#define DC__DPR0_CH2 ((DPR_Type *)DC__DPR0_CH2_BASE)
41951/** Peripheral DC__DPR1_CH0 base address */
41952#define DC__DPR1_CH0_BASE DC__DPR1_BASE
41953/** Peripheral DC__DPR1_CH0 base pointer */
41954#define DC__DPR1_CH0 ((DPR_Type *)DC__DPR1_CH0_BASE)
41955/** Peripheral DC__DPR1_CH1 base address */
41956#define DC__DPR1_CH1_BASE (0x56110000u)
41957/** Peripheral DC__DPR1_CH1 base pointer */
41958#define DC__DPR1_CH1 ((DPR_Type *)DC__DPR1_CH1_BASE)
41959/** Peripheral DC__DPR1_CH2 base address */
41960#define DC__DPR1_CH2_BASE (0x56120000u)
41961/** Peripheral DC__DPR1_CH2 base pointer */
41962#define DC__DPR1_CH2 ((DPR_Type *)DC__DPR1_CH2_BASE)
41963/** Array initializer of DPR peripheral base addresses */
41964#define DPR_CH_BASE_ADDRS { DC__DPR0_CH0_BASE, DC__DPR0_CH1_BASE, DC__DPR0_CH2_BASE, DC__DPR1_CH0_BASE, DC__DPR1_CH1_BASE, DC__DPR1_CH2_BASE }
41965/** Array initializer of DPR peripheral base pointers */
41966#define DPR_CH_BASE_PTRS { DC__DPR0_CH0, DC__DPR0_CH1, DC__DPR0_CH2, DC__DPR1_CH0, DC__DPR1_CH1, DC__DPR1_CH2 }
41967
41968
41969/*!
41970 * @}
41971 */ /* end of group DPR_Peripheral_Access_Layer */
41972
41973
41974/* ----------------------------------------------------------------------------
41975 -- ENET Peripheral Access Layer
41976 ---------------------------------------------------------------------------- */
41977
41978/*!
41979 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
41980 * @{
41981 */
41982
41983/** ENET - Register Layout Typedef */
41984typedef struct {
41985 uint8_t RESERVED_0[4];
41986 __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
41987 __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
41988 uint8_t RESERVED_1[4];
41989 __IO uint32_t RDAR; /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */
41990 __IO uint32_t TDAR; /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */
41991 uint8_t RESERVED_2[12];
41992 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
41993 uint8_t RESERVED_3[24];
41994 __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
41995 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
41996 uint8_t RESERVED_4[28];
41997 __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
41998 uint8_t RESERVED_5[28];
41999 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
42000 uint8_t RESERVED_6[60];
42001 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
42002 uint8_t RESERVED_7[28];
42003 __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
42004 __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
42005 __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
42006 __IO uint32_t TXIC[3]; /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */
42007 uint8_t RESERVED_8[4];
42008 __IO uint32_t RXIC[3]; /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */
42009 uint8_t RESERVED_9[12];
42010 __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
42011 __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
42012 __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
42013 __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
42014 uint8_t RESERVED_10[28];
42015 __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
42016 uint8_t RESERVED_11[24];
42017 __IO uint32_t RDSR1; /**< Receive Descriptor Ring 1 Start Register, offset: 0x160 */
42018 __IO uint32_t TDSR1; /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164 */
42019 __IO uint32_t MRBR1; /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168 */
42020 __IO uint32_t RDSR2; /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C */
42021 __IO uint32_t TDSR2; /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */
42022 __IO uint32_t MRBR2; /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */
42023 uint8_t RESERVED_12[8];
42024 __IO uint32_t RDSR; /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */
42025 __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */
42026 __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */
42027 uint8_t RESERVED_13[4];
42028 __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
42029 __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
42030 __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
42031 __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
42032 __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
42033 __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
42034 __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
42035 __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
42036 __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
42037 uint8_t RESERVED_14[12];
42038 __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
42039 __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
42040 __IO uint32_t RCMR[2]; /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4 */
42041 uint8_t RESERVED_15[8];
42042 __IO uint32_t DMACFG[2]; /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4 */
42043 __IO uint32_t RDAR1; /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0 */
42044 __IO uint32_t TDAR1; /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4 */
42045 __IO uint32_t RDAR2; /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */
42046 __IO uint32_t TDAR2; /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */
42047 __IO uint32_t QOS; /**< QOS Scheme, offset: 0x1F0 */
42048 uint8_t RESERVED_16[12];
42049 uint32_t RMON_T_DROP; /**< Reserved Statistic Register, offset: 0x200 */
42050 __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
42051 __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
42052 __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
42053 __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
42054 __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
42055 __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
42056 __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
42057 __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
42058 __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
42059 __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
42060 __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
42061 __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
42062 __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
42063 __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
42064 __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
42065 __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
42066 __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
42067 uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */
42068 __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
42069 __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
42070 __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
42071 __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
42072 __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
42073 __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
42074 __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
42075 __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
42076 __I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */
42077 __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
42078 __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
42079 uint8_t RESERVED_17[12];
42080 __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
42081 __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
42082 __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
42083 __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
42084 __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
42085 __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
42086 __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
42087 __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
42088 uint32_t RMON_R_RESVD_0; /**< Reserved Statistic Register, offset: 0x2A4 */
42089 __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
42090 __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
42091 __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
42092 __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
42093 __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
42094 __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
42095 __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
42096 __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
42097 __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
42098 __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
42099 __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
42100 __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
42101 __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
42102 __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
42103 __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
42104 uint8_t RESERVED_18[284];
42105 __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
42106 __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
42107 __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
42108 __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
42109 __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
42110 __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
42111 __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
42112 uint8_t RESERVED_19[356];
42113 __IO uint32_t MDATA; /**< Pattern Match Data Register, offset: 0x580 */
42114 __IO uint32_t MMASK; /**< Match Entry Mask Register, offset: 0x584 */
42115 __IO uint32_t MCONFIG; /**< Match Entry Rules Configuration Register, offset: 0x588 */
42116 __IO uint32_t MENTRYRW; /**< Match Entry Read/Write Command Register, offset: 0x58C */
42117 __IO uint32_t RXPCTL; /**< Receive Parser Control Register, offset: 0x590 */
42118 __IO uint32_t MAXFRMOFF; /**< Maximum Frame Offset, offset: 0x594 */
42119 __I uint32_t RXPARST; /**< Receive Parser Status, offset: 0x598 */
42120 uint8_t RESERVED_20[4];
42121 __I uint32_t PARSDSCD; /**< Parser Discard Count, offset: 0x5A0 */
42122 __I uint32_t PRSACPT0; /**< Parser Accept Count 0, offset: 0x5A4 */
42123 __I uint32_t PRSRJCT0; /**< Parser Reject Count 0, offset: 0x5A8 */
42124 __I uint32_t PRSACPT1; /**< Parser Accept Count 1, offset: 0x5AC */
42125 __I uint32_t PRSRJCT1; /**< Parser Reject Count 1, offset: 0x5B0 */
42126 __I uint32_t PRSACPT2; /**< Parser Accept Count 2, offset: 0x5B4 */
42127 __I uint32_t PRSRJCT2; /**< Parser Reject Count 2, offset: 0x5B8 */
42128 uint8_t RESERVED_21[72];
42129 __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
42130 struct { /* offset: 0x608, array step: 0x8 */
42131 __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
42132 __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
42133 } CHANNEL[4];
42134} ENET_Type;
42135
42136/* ----------------------------------------------------------------------------
42137 -- ENET Register Masks
42138 ---------------------------------------------------------------------------- */
42139
42140/*!
42141 * @addtogroup ENET_Register_Masks ENET Register Masks
42142 * @{
42143 */
42144
42145/*! @name EIR - Interrupt Event Register */
42146/*! @{ */
42147#define ENET_EIR_RXB1_MASK (0x1U)
42148#define ENET_EIR_RXB1_SHIFT (0U)
42149/*! RXB1 - Receive buffer interrupt, class 1
42150 */
42151#define ENET_EIR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK)
42152#define ENET_EIR_RXF1_MASK (0x2U)
42153#define ENET_EIR_RXF1_SHIFT (1U)
42154/*! RXF1 - Receive frame interrupt, class 1
42155 */
42156#define ENET_EIR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK)
42157#define ENET_EIR_TXB1_MASK (0x4U)
42158#define ENET_EIR_TXB1_SHIFT (2U)
42159/*! TXB1 - Transmit buffer interrupt, class 1
42160 */
42161#define ENET_EIR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK)
42162#define ENET_EIR_TXF1_MASK (0x8U)
42163#define ENET_EIR_TXF1_SHIFT (3U)
42164/*! TXF1 - Transmit frame interrupt, class 1
42165 */
42166#define ENET_EIR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK)
42167#define ENET_EIR_RXB2_MASK (0x10U)
42168#define ENET_EIR_RXB2_SHIFT (4U)
42169/*! RXB2 - Receive buffer interrupt, class 2
42170 */
42171#define ENET_EIR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK)
42172#define ENET_EIR_RXF2_MASK (0x20U)
42173#define ENET_EIR_RXF2_SHIFT (5U)
42174/*! RXF2 - Receive frame interrupt, class 2
42175 */
42176#define ENET_EIR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK)
42177#define ENET_EIR_TXB2_MASK (0x40U)
42178#define ENET_EIR_TXB2_SHIFT (6U)
42179/*! TXB2 - Transmit buffer interrupt, class 2
42180 */
42181#define ENET_EIR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK)
42182#define ENET_EIR_TXF2_MASK (0x80U)
42183#define ENET_EIR_TXF2_SHIFT (7U)
42184/*! TXF2 - Transmit frame interrupt, class 2
42185 */
42186#define ENET_EIR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK)
42187#define ENET_EIR_PARSRF_MASK (0x200U)
42188#define ENET_EIR_PARSRF_SHIFT (9U)
42189#define ENET_EIR_PARSRF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PARSRF_SHIFT)) & ENET_EIR_PARSRF_MASK)
42190#define ENET_EIR_PARSERR_MASK (0x400U)
42191#define ENET_EIR_PARSERR_SHIFT (10U)
42192#define ENET_EIR_PARSERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PARSERR_SHIFT)) & ENET_EIR_PARSERR_MASK)
42193#define ENET_EIR_RXFLUSH_0_MASK (0x1000U)
42194#define ENET_EIR_RXFLUSH_0_SHIFT (12U)
42195#define ENET_EIR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK)
42196#define ENET_EIR_RXFLUSH_1_MASK (0x2000U)
42197#define ENET_EIR_RXFLUSH_1_SHIFT (13U)
42198#define ENET_EIR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK)
42199#define ENET_EIR_RXFLUSH_2_MASK (0x4000U)
42200#define ENET_EIR_RXFLUSH_2_SHIFT (14U)
42201#define ENET_EIR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK)
42202#define ENET_EIR_TS_TIMER_MASK (0x8000U)
42203#define ENET_EIR_TS_TIMER_SHIFT (15U)
42204/*! TS_TIMER - Timestamp Timer
42205 */
42206#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
42207#define ENET_EIR_TS_AVAIL_MASK (0x10000U)
42208#define ENET_EIR_TS_AVAIL_SHIFT (16U)
42209/*! TS_AVAIL - Transmit Timestamp Available
42210 */
42211#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
42212#define ENET_EIR_WAKEUP_MASK (0x20000U)
42213#define ENET_EIR_WAKEUP_SHIFT (17U)
42214/*! WAKEUP - Node Wakeup Request Indication
42215 */
42216#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
42217#define ENET_EIR_PLR_MASK (0x40000U)
42218#define ENET_EIR_PLR_SHIFT (18U)
42219/*! PLR - Payload Receive Error
42220 */
42221#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
42222#define ENET_EIR_UN_MASK (0x80000U)
42223#define ENET_EIR_UN_SHIFT (19U)
42224/*! UN - Transmit FIFO Underrun
42225 */
42226#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
42227#define ENET_EIR_RL_MASK (0x100000U)
42228#define ENET_EIR_RL_SHIFT (20U)
42229/*! RL - Collision Retry Limit
42230 */
42231#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
42232#define ENET_EIR_LC_MASK (0x200000U)
42233#define ENET_EIR_LC_SHIFT (21U)
42234/*! LC - Late Collision
42235 */
42236#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
42237#define ENET_EIR_EBERR_MASK (0x400000U)
42238#define ENET_EIR_EBERR_SHIFT (22U)
42239/*! EBERR - Ethernet Bus Error
42240 */
42241#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
42242#define ENET_EIR_MII_MASK (0x800000U)
42243#define ENET_EIR_MII_SHIFT (23U)
42244/*! MII - MII Interrupt.
42245 */
42246#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
42247#define ENET_EIR_RXB_MASK (0x1000000U)
42248#define ENET_EIR_RXB_SHIFT (24U)
42249/*! RXB - Receive Buffer Interrupt
42250 */
42251#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
42252#define ENET_EIR_RXF_MASK (0x2000000U)
42253#define ENET_EIR_RXF_SHIFT (25U)
42254/*! RXF - Receive Frame Interrupt
42255 */
42256#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
42257#define ENET_EIR_TXB_MASK (0x4000000U)
42258#define ENET_EIR_TXB_SHIFT (26U)
42259/*! TXB - Transmit Buffer Interrupt
42260 */
42261#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
42262#define ENET_EIR_TXF_MASK (0x8000000U)
42263#define ENET_EIR_TXF_SHIFT (27U)
42264/*! TXF - Transmit Frame Interrupt
42265 */
42266#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
42267#define ENET_EIR_GRA_MASK (0x10000000U)
42268#define ENET_EIR_GRA_SHIFT (28U)
42269/*! GRA - Graceful Stop Complete
42270 */
42271#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
42272#define ENET_EIR_BABT_MASK (0x20000000U)
42273#define ENET_EIR_BABT_SHIFT (29U)
42274/*! BABT - Babbling Transmit Error
42275 */
42276#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
42277#define ENET_EIR_BABR_MASK (0x40000000U)
42278#define ENET_EIR_BABR_SHIFT (30U)
42279/*! BABR - Babbling Receive Error
42280 */
42281#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
42282/*! @} */
42283
42284/*! @name EIMR - Interrupt Mask Register */
42285/*! @{ */
42286#define ENET_EIMR_RXB1_MASK (0x1U)
42287#define ENET_EIMR_RXB1_SHIFT (0U)
42288/*! RXB1 - Receive buffer interrupt, class 1
42289 */
42290#define ENET_EIMR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK)
42291#define ENET_EIMR_RXF1_MASK (0x2U)
42292#define ENET_EIMR_RXF1_SHIFT (1U)
42293/*! RXF1 - Receive frame interrupt, class 1
42294 */
42295#define ENET_EIMR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK)
42296#define ENET_EIMR_TXB1_MASK (0x4U)
42297#define ENET_EIMR_TXB1_SHIFT (2U)
42298/*! TXB1 - Transmit buffer interrupt, class 1
42299 */
42300#define ENET_EIMR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK)
42301#define ENET_EIMR_TXF1_MASK (0x8U)
42302#define ENET_EIMR_TXF1_SHIFT (3U)
42303/*! TXF1 - Transmit frame interrupt, class 1
42304 */
42305#define ENET_EIMR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK)
42306#define ENET_EIMR_RXB2_MASK (0x10U)
42307#define ENET_EIMR_RXB2_SHIFT (4U)
42308/*! RXB2 - Receive buffer interrupt, class 2
42309 */
42310#define ENET_EIMR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK)
42311#define ENET_EIMR_RXF2_MASK (0x20U)
42312#define ENET_EIMR_RXF2_SHIFT (5U)
42313/*! RXF2 - Receive frame interrupt, class 2
42314 */
42315#define ENET_EIMR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK)
42316#define ENET_EIMR_TXB2_MASK (0x40U)
42317#define ENET_EIMR_TXB2_SHIFT (6U)
42318/*! TXB2 - Transmit buffer interrupt, class 2
42319 */
42320#define ENET_EIMR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK)
42321#define ENET_EIMR_TXF2_MASK (0x80U)
42322#define ENET_EIMR_TXF2_SHIFT (7U)
42323/*! TXF2 - Transmit frame interrupt, class 2
42324 */
42325#define ENET_EIMR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK)
42326#define ENET_EIMR_PARSRF_MASK (0x200U)
42327#define ENET_EIMR_PARSRF_SHIFT (9U)
42328#define ENET_EIMR_PARSRF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PARSRF_SHIFT)) & ENET_EIMR_PARSRF_MASK)
42329#define ENET_EIMR_PARSERR_MASK (0x400U)
42330#define ENET_EIMR_PARSERR_SHIFT (10U)
42331#define ENET_EIMR_PARSERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PARSERR_SHIFT)) & ENET_EIMR_PARSERR_MASK)
42332#define ENET_EIMR_RXFLUSH_0_MASK (0x1000U)
42333#define ENET_EIMR_RXFLUSH_0_SHIFT (12U)
42334#define ENET_EIMR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK)
42335#define ENET_EIMR_RXFLUSH_1_MASK (0x2000U)
42336#define ENET_EIMR_RXFLUSH_1_SHIFT (13U)
42337#define ENET_EIMR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK)
42338#define ENET_EIMR_RXFLUSH_2_MASK (0x4000U)
42339#define ENET_EIMR_RXFLUSH_2_SHIFT (14U)
42340#define ENET_EIMR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK)
42341#define ENET_EIMR_TS_TIMER_MASK (0x8000U)
42342#define ENET_EIMR_TS_TIMER_SHIFT (15U)
42343/*! TS_TIMER - TS_TIMER Interrupt Mask
42344 */
42345#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
42346#define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
42347#define ENET_EIMR_TS_AVAIL_SHIFT (16U)
42348/*! TS_AVAIL - TS_AVAIL Interrupt Mask
42349 */
42350#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
42351#define ENET_EIMR_WAKEUP_MASK (0x20000U)
42352#define ENET_EIMR_WAKEUP_SHIFT (17U)
42353/*! WAKEUP - WAKEUP Interrupt Mask
42354 */
42355#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
42356#define ENET_EIMR_PLR_MASK (0x40000U)
42357#define ENET_EIMR_PLR_SHIFT (18U)
42358/*! PLR - PLR Interrupt Mask
42359 */
42360#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
42361#define ENET_EIMR_UN_MASK (0x80000U)
42362#define ENET_EIMR_UN_SHIFT (19U)
42363/*! UN - UN Interrupt Mask
42364 */
42365#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
42366#define ENET_EIMR_RL_MASK (0x100000U)
42367#define ENET_EIMR_RL_SHIFT (20U)
42368/*! RL - RL Interrupt Mask
42369 */
42370#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
42371#define ENET_EIMR_LC_MASK (0x200000U)
42372#define ENET_EIMR_LC_SHIFT (21U)
42373/*! LC - LC Interrupt Mask
42374 */
42375#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
42376#define ENET_EIMR_EBERR_MASK (0x400000U)
42377#define ENET_EIMR_EBERR_SHIFT (22U)
42378/*! EBERR - EBERR Interrupt Mask
42379 */
42380#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
42381#define ENET_EIMR_MII_MASK (0x800000U)
42382#define ENET_EIMR_MII_SHIFT (23U)
42383/*! MII - MII Interrupt Mask
42384 */
42385#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
42386#define ENET_EIMR_RXB_MASK (0x1000000U)
42387#define ENET_EIMR_RXB_SHIFT (24U)
42388/*! RXB - RXB Interrupt Mask
42389 */
42390#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
42391#define ENET_EIMR_RXF_MASK (0x2000000U)
42392#define ENET_EIMR_RXF_SHIFT (25U)
42393/*! RXF - RXF Interrupt Mask
42394 */
42395#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
42396#define ENET_EIMR_TXB_MASK (0x4000000U)
42397#define ENET_EIMR_TXB_SHIFT (26U)
42398/*! TXB - TXB Interrupt Mask
42399 * 0b0..The corresponding interrupt source is masked.
42400 * 0b1..The corresponding interrupt source is not masked.
42401 */
42402#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
42403#define ENET_EIMR_TXF_MASK (0x8000000U)
42404#define ENET_EIMR_TXF_SHIFT (27U)
42405/*! TXF - TXF Interrupt Mask
42406 * 0b0..The corresponding interrupt source is masked.
42407 * 0b1..The corresponding interrupt source is not masked.
42408 */
42409#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
42410#define ENET_EIMR_GRA_MASK (0x10000000U)
42411#define ENET_EIMR_GRA_SHIFT (28U)
42412/*! GRA - GRA Interrupt Mask
42413 * 0b0..The corresponding interrupt source is masked.
42414 * 0b1..The corresponding interrupt source is not masked.
42415 */
42416#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
42417#define ENET_EIMR_BABT_MASK (0x20000000U)
42418#define ENET_EIMR_BABT_SHIFT (29U)
42419/*! BABT - BABT Interrupt Mask
42420 * 0b0..The corresponding interrupt source is masked.
42421 * 0b1..The corresponding interrupt source is not masked.
42422 */
42423#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
42424#define ENET_EIMR_BABR_MASK (0x40000000U)
42425#define ENET_EIMR_BABR_SHIFT (30U)
42426/*! BABR - BABR Interrupt Mask
42427 * 0b0..The corresponding interrupt source is masked.
42428 * 0b1..The corresponding interrupt source is not masked.
42429 */
42430#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
42431/*! @} */
42432
42433/*! @name RDAR - Receive Descriptor Active Register - Ring 0 */
42434/*! @{ */
42435#define ENET_RDAR_RDAR_MASK (0x1000000U)
42436#define ENET_RDAR_RDAR_SHIFT (24U)
42437/*! RDAR - Receive Descriptor Active
42438 */
42439#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
42440/*! @} */
42441
42442/*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */
42443/*! @{ */
42444#define ENET_TDAR_TDAR_MASK (0x1000000U)
42445#define ENET_TDAR_TDAR_SHIFT (24U)
42446/*! TDAR - Transmit Descriptor Active
42447 */
42448#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
42449/*! @} */
42450
42451/*! @name ECR - Ethernet Control Register */
42452/*! @{ */
42453#define ENET_ECR_RESET_MASK (0x1U)
42454#define ENET_ECR_RESET_SHIFT (0U)
42455/*! RESET - Ethernet MAC Reset
42456 */
42457#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
42458#define ENET_ECR_ETHEREN_MASK (0x2U)
42459#define ENET_ECR_ETHEREN_SHIFT (1U)
42460/*! ETHEREN - Ethernet Enable
42461 * 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame.
42462 * 0b1..MAC is enabled, and reception and transmission are possible.
42463 */
42464#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
42465#define ENET_ECR_MAGICEN_MASK (0x4U)
42466#define ENET_ECR_MAGICEN_SHIFT (2U)
42467/*! MAGICEN - Magic Packet Detection Enable
42468 * 0b0..Magic detection logic disabled.
42469 * 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
42470 */
42471#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
42472#define ENET_ECR_SLEEP_MASK (0x8U)
42473#define ENET_ECR_SLEEP_SHIFT (3U)
42474/*! SLEEP - Sleep Mode Enable
42475 * 0b0..Normal operating mode.
42476 * 0b1..Sleep mode.
42477 */
42478#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
42479#define ENET_ECR_EN1588_MASK (0x10U)
42480#define ENET_ECR_EN1588_SHIFT (4U)
42481/*! EN1588 - EN1588 Enable
42482 * 0b0..Legacy FEC buffer descriptors and functions enabled.
42483 * 0b1..Enhanced frame time-stamping functions enabled. Has no effect within the MAC besides controlling the DMA control bit ena_1588.
42484 */
42485#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
42486#define ENET_ECR_SPEED_MASK (0x20U)
42487#define ENET_ECR_SPEED_SHIFT (5U)
42488/*! SPEED
42489 * 0b0..10/100-Mbit/s mode
42490 * 0b1..1000-Mbit/s mode
42491 */
42492#define ENET_ECR_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK)
42493#define ENET_ECR_DBGEN_MASK (0x40U)
42494#define ENET_ECR_DBGEN_SHIFT (6U)
42495/*! DBGEN - Debug Enable
42496 * 0b0..MAC continues operation in debug mode.
42497 * 0b1..MAC enters hardware freeze mode when the processor is in debug mode.
42498 */
42499#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
42500#define ENET_ECR_DBSWP_MASK (0x100U)
42501#define ENET_ECR_DBSWP_SHIFT (8U)
42502/*! DBSWP - Descriptor Byte Swapping Enable
42503 * 0b0..The buffer descriptor bytes are not swapped to support big-endian devices.
42504 * 0b1..The buffer descriptor bytes are swapped to support little-endian devices.
42505 */
42506#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
42507#define ENET_ECR_SVLANEN_MASK (0x200U)
42508#define ENET_ECR_SVLANEN_SHIFT (9U)
42509/*! SVLANEN - S-VLAN enable
42510 * 0b0..Only the EtherType 0x8100 will be considered for VLAN detection.
42511 * 0b1..The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in
42512 * receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the
42513 * classification match comparators, RCMRn.
42514 */
42515#define ENET_ECR_SVLANEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK)
42516#define ENET_ECR_VLANUSE2ND_MASK (0x400U)
42517#define ENET_ECR_VLANUSE2ND_SHIFT (10U)
42518/*! VLANUSE2ND - VLAN use second tag
42519 * 0b0..Always extract data from the first VLAN tag if it exists.
42520 * 0b1..When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A
42521 * double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The
42522 * second tag must be a C-VLAN
42523 */
42524#define ENET_ECR_VLANUSE2ND(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK)
42525#define ENET_ECR_SVLANDBL_MASK (0x800U)
42526#define ENET_ECR_SVLANDBL_SHIFT (11U)
42527/*! SVLANDBL - S-VLAN double tag
42528 */
42529#define ENET_ECR_SVLANDBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK)
42530#define ENET_ECR_TXC_DLY_MASK (0x10000U)
42531#define ENET_ECR_TXC_DLY_SHIFT (16U)
42532/*! TXC_DLY - Transmit clock delay
42533 * 0b0..RGMII_TXC is not delayed.
42534 * 0b1..Generate delayed version of RGMII_TXC.
42535 */
42536#define ENET_ECR_TXC_DLY(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_TXC_DLY_SHIFT)) & ENET_ECR_TXC_DLY_MASK)
42537#define ENET_ECR_RXC_DLY_MASK (0x20000U)
42538#define ENET_ECR_RXC_DLY_SHIFT (17U)
42539/*! RXC_DLY - Receive clock delay
42540 * 0b0..Use non-delayed version of RGMII_RXC.
42541 * 0b1..Use delayed version of RGMII_RXC.
42542 */
42543#define ENET_ECR_RXC_DLY(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RXC_DLY_SHIFT)) & ENET_ECR_RXC_DLY_MASK)
42544/*! @} */
42545
42546/*! @name MMFR - MII Management Frame Register */
42547/*! @{ */
42548#define ENET_MMFR_DATA_MASK (0xFFFFU)
42549#define ENET_MMFR_DATA_SHIFT (0U)
42550/*! DATA - Management Frame Data
42551 */
42552#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
42553#define ENET_MMFR_TA_MASK (0x30000U)
42554#define ENET_MMFR_TA_SHIFT (16U)
42555/*! TA - Turn Around
42556 */
42557#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
42558#define ENET_MMFR_RA_MASK (0x7C0000U)
42559#define ENET_MMFR_RA_SHIFT (18U)
42560/*! RA - Register Address
42561 */
42562#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
42563#define ENET_MMFR_PA_MASK (0xF800000U)
42564#define ENET_MMFR_PA_SHIFT (23U)
42565/*! PA - PHY Address
42566 */
42567#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
42568#define ENET_MMFR_OP_MASK (0x30000000U)
42569#define ENET_MMFR_OP_SHIFT (28U)
42570/*! OP - Operation Code
42571 */
42572#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
42573#define ENET_MMFR_ST_MASK (0xC0000000U)
42574#define ENET_MMFR_ST_SHIFT (30U)
42575/*! ST - Start Of Frame Delimiter
42576 */
42577#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
42578/*! @} */
42579
42580/*! @name MSCR - MII Speed Control Register */
42581/*! @{ */
42582#define ENET_MSCR_MII_SPEED_MASK (0x7EU)
42583#define ENET_MSCR_MII_SPEED_SHIFT (1U)
42584/*! MII_SPEED - MII Speed
42585 */
42586#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
42587#define ENET_MSCR_DIS_PRE_MASK (0x80U)
42588#define ENET_MSCR_DIS_PRE_SHIFT (7U)
42589/*! DIS_PRE - Disable Preamble
42590 * 0b0..Preamble enabled.
42591 * 0b1..Preamble (32 ones) is not prepended to the MII management frame.
42592 */
42593#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
42594#define ENET_MSCR_HOLDTIME_MASK (0x700U)
42595#define ENET_MSCR_HOLDTIME_SHIFT (8U)
42596/*! HOLDTIME - Hold time On MDIO Output
42597 * 0b000..1 internal module clock cycle
42598 * 0b001..2 internal module clock cycles
42599 * 0b010..3 internal module clock cycles
42600 * 0b111..8 internal module clock cycles
42601 */
42602#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
42603/*! @} */
42604
42605/*! @name MIBC - MIB Control Register */
42606/*! @{ */
42607#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
42608#define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
42609/*! MIB_CLEAR - MIB Clear
42610 * 0b0..See note above.
42611 * 0b1..All statistics counters are reset to 0.
42612 */
42613#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
42614#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
42615#define ENET_MIBC_MIB_IDLE_SHIFT (30U)
42616/*! MIB_IDLE - MIB Idle
42617 * 0b0..The MIB block is updating MIB counters.
42618 * 0b1..The MIB block is not currently updating any MIB counters.
42619 */
42620#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
42621#define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
42622#define ENET_MIBC_MIB_DIS_SHIFT (31U)
42623/*! MIB_DIS - Disable MIB Logic
42624 * 0b0..MIB logic is enabled.
42625 * 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
42626 */
42627#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
42628/*! @} */
42629
42630/*! @name RCR - Receive Control Register */
42631/*! @{ */
42632#define ENET_RCR_LOOP_MASK (0x1U)
42633#define ENET_RCR_LOOP_SHIFT (0U)
42634/*! LOOP - Internal Loopback
42635 * 0b0..Loopback disabled.
42636 * 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
42637 */
42638#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
42639#define ENET_RCR_DRT_MASK (0x2U)
42640#define ENET_RCR_DRT_SHIFT (1U)
42641/*! DRT - Disable Receive On Transmit
42642 * 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode.
42643 * 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
42644 */
42645#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
42646#define ENET_RCR_MII_MODE_MASK (0x4U)
42647#define ENET_RCR_MII_MODE_SHIFT (2U)
42648/*! MII_MODE - Media Independent Interface Mode
42649 * 0b0..Reserved.
42650 * 0b1..MII or RMII mode, as indicated by the RMII_MODE field.
42651 */
42652#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
42653#define ENET_RCR_PROM_MASK (0x8U)
42654#define ENET_RCR_PROM_SHIFT (3U)
42655/*! PROM - Promiscuous Mode
42656 * 0b0..Disabled.
42657 * 0b1..Enabled.
42658 */
42659#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
42660#define ENET_RCR_BC_REJ_MASK (0x10U)
42661#define ENET_RCR_BC_REJ_SHIFT (4U)
42662/*! BC_REJ - Broadcast Frame Reject
42663 */
42664#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
42665#define ENET_RCR_FCE_MASK (0x20U)
42666#define ENET_RCR_FCE_SHIFT (5U)
42667/*! FCE - Flow Control Enable
42668 */
42669#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
42670#define ENET_RCR_RGMII_EN_MASK (0x40U)
42671#define ENET_RCR_RGMII_EN_SHIFT (6U)
42672/*! RGMII_EN - RGMII Mode Enable
42673 * 0b0..MAC configured for non-RGMII operation
42674 * 0b1..MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If
42675 * ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode.
42676 */
42677#define ENET_RCR_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK)
42678#define ENET_RCR_RMII_MODE_MASK (0x100U)
42679#define ENET_RCR_RMII_MODE_SHIFT (8U)
42680/*! RMII_MODE - RMII Mode Enable
42681 * 0b0..MAC configured for MII mode.
42682 * 0b1..MAC configured for RMII operation.
42683 */
42684#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
42685#define ENET_RCR_RMII_10T_MASK (0x200U)
42686#define ENET_RCR_RMII_10T_SHIFT (9U)
42687/*! RMII_10T
42688 * 0b0..100-Mbit/s operation.
42689 * 0b1..10-Mbit/s operation.
42690 */
42691#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
42692#define ENET_RCR_PADEN_MASK (0x1000U)
42693#define ENET_RCR_PADEN_SHIFT (12U)
42694/*! PADEN - Enable Frame Padding Remove On Receive
42695 * 0b0..No padding is removed on receive by the MAC.
42696 * 0b1..Padding is removed from received frames.
42697 */
42698#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
42699#define ENET_RCR_PAUFWD_MASK (0x2000U)
42700#define ENET_RCR_PAUFWD_SHIFT (13U)
42701/*! PAUFWD - Terminate/Forward Pause Frames
42702 * 0b0..Pause frames are terminated and discarded in the MAC.
42703 * 0b1..Pause frames are forwarded to the user application.
42704 */
42705#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
42706#define ENET_RCR_CRCFWD_MASK (0x4000U)
42707#define ENET_RCR_CRCFWD_SHIFT (14U)
42708/*! CRCFWD - Terminate/Forward Received CRC
42709 * 0b0..The CRC field of received frames is transmitted to the user application.
42710 * 0b1..The CRC field is stripped from the frame.
42711 */
42712#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
42713#define ENET_RCR_CFEN_MASK (0x8000U)
42714#define ENET_RCR_CFEN_SHIFT (15U)
42715/*! CFEN - MAC Control Frame Enable
42716 * 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface.
42717 * 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
42718 */
42719#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
42720#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
42721#define ENET_RCR_MAX_FL_SHIFT (16U)
42722/*! MAX_FL - Maximum Frame Length
42723 */
42724#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
42725#define ENET_RCR_NLC_MASK (0x40000000U)
42726#define ENET_RCR_NLC_SHIFT (30U)
42727/*! NLC - Payload Length Check Disable
42728 * 0b0..The payload length check is disabled.
42729 * 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.
42730 */
42731#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
42732#define ENET_RCR_GRS_MASK (0x80000000U)
42733#define ENET_RCR_GRS_SHIFT (31U)
42734/*! GRS - Graceful Receive Stopped
42735 */
42736#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
42737/*! @} */
42738
42739/*! @name TCR - Transmit Control Register */
42740/*! @{ */
42741#define ENET_TCR_GTS_MASK (0x1U)
42742#define ENET_TCR_GTS_SHIFT (0U)
42743/*! GTS - Graceful Transmit Stop
42744 */
42745#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
42746#define ENET_TCR_FDEN_MASK (0x4U)
42747#define ENET_TCR_FDEN_SHIFT (2U)
42748/*! FDEN - Full-Duplex Enable
42749 */
42750#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
42751#define ENET_TCR_TFC_PAUSE_MASK (0x8U)
42752#define ENET_TCR_TFC_PAUSE_SHIFT (3U)
42753/*! TFC_PAUSE - Transmit Frame Control Pause
42754 * 0b0..No PAUSE frame transmitted.
42755 * 0b1..The MAC stops transmission of data frames after the current transmission is complete.
42756 */
42757#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
42758#define ENET_TCR_RFC_PAUSE_MASK (0x10U)
42759#define ENET_TCR_RFC_PAUSE_SHIFT (4U)
42760/*! RFC_PAUSE - Receive Frame Control Pause
42761 */
42762#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
42763#define ENET_TCR_ADDSEL_MASK (0xE0U)
42764#define ENET_TCR_ADDSEL_SHIFT (5U)
42765/*! ADDSEL - Source MAC Address Select On Transmit
42766 * 0b000..Node MAC address programmed on PADDR1/2 registers.
42767 * 0b100..Reserved.
42768 * 0b101..Reserved.
42769 * 0b110..Reserved.
42770 */
42771#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
42772#define ENET_TCR_ADDINS_MASK (0x100U)
42773#define ENET_TCR_ADDINS_SHIFT (8U)
42774/*! ADDINS - Set MAC Address On Transmit
42775 * 0b0..The source MAC address is not modified by the MAC.
42776 * 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
42777 */
42778#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
42779#define ENET_TCR_CRCFWD_MASK (0x200U)
42780#define ENET_TCR_CRCFWD_SHIFT (9U)
42781/*! CRCFWD - Forward Frame From Application With CRC
42782 * 0b0..TxBD[TC] controls whether the frame has a CRC from the application.
42783 * 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
42784 */
42785#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
42786/*! @} */
42787
42788/*! @name PALR - Physical Address Lower Register */
42789/*! @{ */
42790#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
42791#define ENET_PALR_PADDR1_SHIFT (0U)
42792/*! PADDR1 - Pause Address
42793 */
42794#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
42795/*! @} */
42796
42797/*! @name PAUR - Physical Address Upper Register */
42798/*! @{ */
42799#define ENET_PAUR_TYPE_MASK (0xFFFFU)
42800#define ENET_PAUR_TYPE_SHIFT (0U)
42801/*! TYPE - Type Field In PAUSE Frames
42802 */
42803#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
42804#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
42805#define ENET_PAUR_PADDR2_SHIFT (16U)
42806#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
42807/*! @} */
42808
42809/*! @name OPD - Opcode/Pause Duration Register */
42810/*! @{ */
42811#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
42812#define ENET_OPD_PAUSE_DUR_SHIFT (0U)
42813/*! PAUSE_DUR - Pause Duration
42814 */
42815#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
42816#define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
42817#define ENET_OPD_OPCODE_SHIFT (16U)
42818/*! OPCODE - Opcode Field In PAUSE Frames
42819 */
42820#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
42821/*! @} */
42822
42823/*! @name TXIC - Transmit Interrupt Coalescing Register */
42824/*! @{ */
42825#define ENET_TXIC_ICTT_MASK (0xFFFFU)
42826#define ENET_TXIC_ICTT_SHIFT (0U)
42827/*! ICTT - Interrupt coalescing timer threshold
42828 */
42829#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
42830#define ENET_TXIC_ICFT_MASK (0xFF00000U)
42831#define ENET_TXIC_ICFT_SHIFT (20U)
42832/*! ICFT - Interrupt coalescing frame count threshold
42833 */
42834#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
42835#define ENET_TXIC_ICCS_MASK (0x40000000U)
42836#define ENET_TXIC_ICCS_SHIFT (30U)
42837/*! ICCS - Interrupt Coalescing Timer Clock Source Select
42838 * 0b0..Use MII/GMII TX clocks.
42839 * 0b1..Use ENET system clock.
42840 */
42841#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
42842#define ENET_TXIC_ICEN_MASK (0x80000000U)
42843#define ENET_TXIC_ICEN_SHIFT (31U)
42844/*! ICEN - Interrupt Coalescing Enable
42845 * 0b0..Disable Interrupt coalescing.
42846 * 0b1..Enable Interrupt coalescing.
42847 */
42848#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
42849/*! @} */
42850
42851/* The count of ENET_TXIC */
42852#define ENET_TXIC_COUNT (3U)
42853
42854/*! @name RXIC - Receive Interrupt Coalescing Register */
42855/*! @{ */
42856#define ENET_RXIC_ICTT_MASK (0xFFFFU)
42857#define ENET_RXIC_ICTT_SHIFT (0U)
42858/*! ICTT - Interrupt coalescing timer threshold
42859 */
42860#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
42861#define ENET_RXIC_ICFT_MASK (0xFF00000U)
42862#define ENET_RXIC_ICFT_SHIFT (20U)
42863/*! ICFT - Interrupt coalescing frame count threshold
42864 */
42865#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
42866#define ENET_RXIC_ICCS_MASK (0x40000000U)
42867#define ENET_RXIC_ICCS_SHIFT (30U)
42868/*! ICCS - Interrupt Coalescing Timer Clock Source Select
42869 * 0b0..Use MII/GMII TX clocks.
42870 * 0b1..Use ENET system clock.
42871 */
42872#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
42873#define ENET_RXIC_ICEN_MASK (0x80000000U)
42874#define ENET_RXIC_ICEN_SHIFT (31U)
42875/*! ICEN - Interrupt Coalescing Enable
42876 * 0b0..Disable Interrupt coalescing.
42877 * 0b1..Enable Interrupt coalescing.
42878 */
42879#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
42880/*! @} */
42881
42882/* The count of ENET_RXIC */
42883#define ENET_RXIC_COUNT (3U)
42884
42885/*! @name IAUR - Descriptor Individual Upper Address Register */
42886/*! @{ */
42887#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
42888#define ENET_IAUR_IADDR1_SHIFT (0U)
42889#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
42890/*! @} */
42891
42892/*! @name IALR - Descriptor Individual Lower Address Register */
42893/*! @{ */
42894#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
42895#define ENET_IALR_IADDR2_SHIFT (0U)
42896#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
42897/*! @} */
42898
42899/*! @name GAUR - Descriptor Group Upper Address Register */
42900/*! @{ */
42901#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
42902#define ENET_GAUR_GADDR1_SHIFT (0U)
42903#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
42904/*! @} */
42905
42906/*! @name GALR - Descriptor Group Lower Address Register */
42907/*! @{ */
42908#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
42909#define ENET_GALR_GADDR2_SHIFT (0U)
42910#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
42911/*! @} */
42912
42913/*! @name TFWR - Transmit FIFO Watermark Register */
42914/*! @{ */
42915#define ENET_TFWR_TFWR_MASK (0x3FU)
42916#define ENET_TFWR_TFWR_SHIFT (0U)
42917/*! TFWR - Transmit FIFO Write
42918 * 0b000000..64 bytes written.
42919 * 0b000001..64 bytes written.
42920 * 0b000010..128 bytes written.
42921 * 0b000011..192 bytes written.
42922 * 0b111111..4032 bytes written.
42923 */
42924#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
42925#define ENET_TFWR_STRFWD_MASK (0x100U)
42926#define ENET_TFWR_STRFWD_SHIFT (8U)
42927/*! STRFWD - Store And Forward Enable
42928 * 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR].
42929 * 0b1..Enabled.
42930 */
42931#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
42932/*! @} */
42933
42934/*! @name RDSR1 - Receive Descriptor Ring 1 Start Register */
42935/*! @{ */
42936#define ENET_RDSR1_R_DES_START_MASK (0xFFFFFFF8U)
42937#define ENET_RDSR1_R_DES_START_SHIFT (3U)
42938#define ENET_RDSR1_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK)
42939/*! @} */
42940
42941/*! @name TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register */
42942/*! @{ */
42943#define ENET_TDSR1_X_DES_START_MASK (0xFFFFFFF8U)
42944#define ENET_TDSR1_X_DES_START_SHIFT (3U)
42945#define ENET_TDSR1_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK)
42946/*! @} */
42947
42948/*! @name MRBR1 - Maximum Receive Buffer Size Register - Ring 1 */
42949/*! @{ */
42950#define ENET_MRBR1_R_BUF_SIZE_MASK (0x3FF0U)
42951#define ENET_MRBR1_R_BUF_SIZE_SHIFT (4U)
42952#define ENET_MRBR1_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK)
42953/*! @} */
42954
42955/*! @name RDSR2 - Receive Descriptor Ring 2 Start Register */
42956/*! @{ */
42957#define ENET_RDSR2_R_DES_START_MASK (0xFFFFFFF8U)
42958#define ENET_RDSR2_R_DES_START_SHIFT (3U)
42959#define ENET_RDSR2_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK)
42960/*! @} */
42961
42962/*! @name TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register */
42963/*! @{ */
42964#define ENET_TDSR2_X_DES_START_MASK (0xFFFFFFF8U)
42965#define ENET_TDSR2_X_DES_START_SHIFT (3U)
42966#define ENET_TDSR2_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK)
42967/*! @} */
42968
42969/*! @name MRBR2 - Maximum Receive Buffer Size Register - Ring 2 */
42970/*! @{ */
42971#define ENET_MRBR2_R_BUF_SIZE_MASK (0x3FF0U)
42972#define ENET_MRBR2_R_BUF_SIZE_SHIFT (4U)
42973#define ENET_MRBR2_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK)
42974/*! @} */
42975
42976/*! @name RDSR - Receive Descriptor Ring 0 Start Register */
42977/*! @{ */
42978#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
42979#define ENET_RDSR_R_DES_START_SHIFT (3U)
42980#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
42981/*! @} */
42982
42983/*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */
42984/*! @{ */
42985#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
42986#define ENET_TDSR_X_DES_START_SHIFT (3U)
42987#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
42988/*! @} */
42989
42990/*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */
42991/*! @{ */
42992#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U)
42993#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
42994#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
42995/*! @} */
42996
42997/*! @name RSFL - Receive FIFO Section Full Threshold */
42998/*! @{ */
42999#define ENET_RSFL_RX_SECTION_FULL_MASK (0x3FFU)
43000#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
43001/*! RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold
43002 */
43003#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
43004/*! @} */
43005
43006/*! @name RSEM - Receive FIFO Section Empty Threshold */
43007/*! @{ */
43008#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0x3FFU)
43009#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
43010/*! RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold
43011 */
43012#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
43013#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
43014#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
43015/*! STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold
43016 */
43017#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
43018/*! @} */
43019
43020/*! @name RAEM - Receive FIFO Almost Empty Threshold */
43021/*! @{ */
43022#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0x3FFU)
43023#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
43024/*! RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold
43025 */
43026#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
43027/*! @} */
43028
43029/*! @name RAFL - Receive FIFO Almost Full Threshold */
43030/*! @{ */
43031#define ENET_RAFL_RX_ALMOST_FULL_MASK (0x3FFU)
43032#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
43033/*! RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold
43034 */
43035#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
43036/*! @} */
43037
43038/*! @name TSEM - Transmit FIFO Section Empty Threshold */
43039/*! @{ */
43040#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0x3FFU)
43041#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
43042/*! TX_SECTION_EMPTY - Value Of The Transmit FIFO Section Empty Threshold
43043 */
43044#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
43045/*! @} */
43046
43047/*! @name TAEM - Transmit FIFO Almost Empty Threshold */
43048/*! @{ */
43049#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0x3FFU)
43050#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
43051/*! TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold
43052 */
43053#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
43054/*! @} */
43055
43056/*! @name TAFL - Transmit FIFO Almost Full Threshold */
43057/*! @{ */
43058#define ENET_TAFL_TX_ALMOST_FULL_MASK (0x3FFU)
43059#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
43060/*! TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold
43061 */
43062#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
43063/*! @} */
43064
43065/*! @name TIPG - Transmit Inter-Packet Gap */
43066/*! @{ */
43067#define ENET_TIPG_IPG_MASK (0x1FU)
43068#define ENET_TIPG_IPG_SHIFT (0U)
43069/*! IPG - Transmit Inter-Packet Gap
43070 */
43071#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
43072/*! @} */
43073
43074/*! @name FTRL - Frame Truncation Length */
43075/*! @{ */
43076#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
43077#define ENET_FTRL_TRUNC_FL_SHIFT (0U)
43078/*! TRUNC_FL - Frame Truncation Length
43079 */
43080#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
43081/*! @} */
43082
43083/*! @name TACC - Transmit Accelerator Function Configuration */
43084/*! @{ */
43085#define ENET_TACC_SHIFT16_MASK (0x1U)
43086#define ENET_TACC_SHIFT16_SHIFT (0U)
43087/*! SHIFT16 - TX FIFO Shift-16
43088 * 0b0..Disabled.
43089 * 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the
43090 * frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This
43091 * function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is
43092 * extended to a 16-byte header.
43093 */
43094#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
43095#define ENET_TACC_IPCHK_MASK (0x8U)
43096#define ENET_TACC_IPCHK_SHIFT (3U)
43097/*! IPCHK
43098 * 0b0..Checksum is not inserted.
43099 * 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must
43100 * be cleared. If a non-IP frame is transmitted the frame is not modified.
43101 */
43102#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
43103#define ENET_TACC_PROCHK_MASK (0x10U)
43104#define ENET_TACC_PROCHK_SHIFT (4U)
43105/*! PROCHK
43106 * 0b0..Checksum not inserted.
43107 * 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the
43108 * frame. The checksum field must be cleared. The other frames are not modified.
43109 */
43110#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
43111/*! @} */
43112
43113/*! @name RACC - Receive Accelerator Function Configuration */
43114/*! @{ */
43115#define ENET_RACC_PADREM_MASK (0x1U)
43116#define ENET_RACC_PADREM_SHIFT (0U)
43117/*! PADREM - Enable Padding Removal For Short IP Frames
43118 * 0b0..Padding not removed.
43119 * 0b1..Any bytes following the IP payload section of the frame are removed from the frame.
43120 */
43121#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
43122#define ENET_RACC_IPDIS_MASK (0x2U)
43123#define ENET_RACC_IPDIS_SHIFT (1U)
43124/*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum
43125 * 0b0..Frames with wrong IPv4 header checksum are not discarded.
43126 * 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no
43127 * header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in
43128 * store and forward mode (RSFL cleared).
43129 */
43130#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
43131#define ENET_RACC_PRODIS_MASK (0x4U)
43132#define ENET_RACC_PRODIS_SHIFT (2U)
43133/*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum
43134 * 0b0..Frames with wrong checksum are not discarded.
43135 * 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame
43136 * is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL
43137 * cleared).
43138 */
43139#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
43140#define ENET_RACC_LINEDIS_MASK (0x40U)
43141#define ENET_RACC_LINEDIS_SHIFT (6U)
43142/*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors
43143 * 0b0..Frames with errors are not discarded.
43144 * 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
43145 */
43146#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
43147#define ENET_RACC_SHIFT16_MASK (0x80U)
43148#define ENET_RACC_SHIFT16_SHIFT (7U)
43149/*! SHIFT16 - RX FIFO Shift-16
43150 * 0b0..Disabled.
43151 * 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
43152 */
43153#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
43154/*! @} */
43155
43156/*! @name RCMR - Receive Classification Match Register for Class n */
43157/*! @{ */
43158#define ENET_RCMR_CMP0_MASK (0x7U)
43159#define ENET_RCMR_CMP0_SHIFT (0U)
43160/*! CMP0 - Compare 0
43161 */
43162#define ENET_RCMR_CMP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK)
43163#define ENET_RCMR_CMP1_MASK (0x70U)
43164#define ENET_RCMR_CMP1_SHIFT (4U)
43165/*! CMP1 - Compare 1
43166 */
43167#define ENET_RCMR_CMP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK)
43168#define ENET_RCMR_CMP2_MASK (0x700U)
43169#define ENET_RCMR_CMP2_SHIFT (8U)
43170/*! CMP2 - Compare 2
43171 */
43172#define ENET_RCMR_CMP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK)
43173#define ENET_RCMR_CMP3_MASK (0x7000U)
43174#define ENET_RCMR_CMP3_SHIFT (12U)
43175/*! CMP3 - Compare 3
43176 */
43177#define ENET_RCMR_CMP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK)
43178#define ENET_RCMR_MATCHEN_MASK (0x10000U)
43179#define ENET_RCMR_MATCHEN_SHIFT (16U)
43180/*! MATCHEN - Match Enable
43181 * 0b0..Disabled (default): no compares will occur and the classification indicator for this class will never assert.
43182 * 0b1..The register contents are valid and a comparison with all compare values is done when a VLAN frame is received.
43183 */
43184#define ENET_RCMR_MATCHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK)
43185/*! @} */
43186
43187/* The count of ENET_RCMR */
43188#define ENET_RCMR_COUNT (2U)
43189
43190/*! @name DMACFG - DMA Class Based Configuration */
43191/*! @{ */
43192#define ENET_DMACFG_IDLE_SLOPE_MASK (0xFFFFU)
43193#define ENET_DMACFG_IDLE_SLOPE_SHIFT (0U)
43194/*! IDLE_SLOPE - Idle slope
43195 */
43196#define ENET_DMACFG_IDLE_SLOPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK)
43197#define ENET_DMACFG_DMA_CLASS_EN_MASK (0x10000U)
43198#define ENET_DMACFG_DMA_CLASS_EN_SHIFT (16U)
43199/*! DMA_CLASS_EN - DMA class enable
43200 * 0b0..The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also
43201 * requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2
43202 * queues are disabled then their frames will be placed in queue 0.
43203 * 0b1..Enable the DMA controller to support the corresponding descriptor ring for this class of traffic.
43204 */
43205#define ENET_DMACFG_DMA_CLASS_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK)
43206#define ENET_DMACFG_CALC_NOIPG_MASK (0x20000U)
43207#define ENET_DMACFG_CALC_NOIPG_SHIFT (17U)
43208/*! CALC_NOIPG - Calculate no IPG
43209 * 0b0..The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred
43210 * for a frame when doing bandwidth calculations. This is the default.
43211 * 0b1..Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping,
43212 * when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every
43213 * frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames
43214 * will become more bandwidth than large frames due to the relation of data to IPG overhead).
43215 */
43216#define ENET_DMACFG_CALC_NOIPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK)
43217/*! @} */
43218
43219/* The count of ENET_DMACFG */
43220#define ENET_DMACFG_COUNT (2U)
43221
43222/*! @name RDAR1 - Receive Descriptor Active Register - Ring 1 */
43223/*! @{ */
43224#define ENET_RDAR1_RDAR_MASK (0x1000000U)
43225#define ENET_RDAR1_RDAR_SHIFT (24U)
43226/*! RDAR - Receive Descriptor Active
43227 */
43228#define ENET_RDAR1_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK)
43229/*! @} */
43230
43231/*! @name TDAR1 - Transmit Descriptor Active Register - Ring 1 */
43232/*! @{ */
43233#define ENET_TDAR1_TDAR_MASK (0x1000000U)
43234#define ENET_TDAR1_TDAR_SHIFT (24U)
43235/*! TDAR - Transmit Descriptor Active
43236 */
43237#define ENET_TDAR1_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK)
43238/*! @} */
43239
43240/*! @name RDAR2 - Receive Descriptor Active Register - Ring 2 */
43241/*! @{ */
43242#define ENET_RDAR2_RDAR_MASK (0x1000000U)
43243#define ENET_RDAR2_RDAR_SHIFT (24U)
43244/*! RDAR - Receive Descriptor Active
43245 */
43246#define ENET_RDAR2_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK)
43247/*! @} */
43248
43249/*! @name TDAR2 - Transmit Descriptor Active Register - Ring 2 */
43250/*! @{ */
43251#define ENET_TDAR2_TDAR_MASK (0x1000000U)
43252#define ENET_TDAR2_TDAR_SHIFT (24U)
43253/*! TDAR - Transmit Descriptor Active
43254 */
43255#define ENET_TDAR2_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK)
43256/*! @} */
43257
43258/*! @name QOS - QOS Scheme */
43259/*! @{ */
43260#define ENET_QOS_TX_SCHEME_MASK (0x7U)
43261#define ENET_QOS_TX_SCHEME_SHIFT (0U)
43262/*! TX_SCHEME - TX scheme configuration
43263 * 0b000..Credit-based scheme
43264 * 0b001..Round-robin scheme
43265 * 0b010-0b111..Reserved
43266 */
43267#define ENET_QOS_TX_SCHEME(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK)
43268#define ENET_QOS_RX_FLUSH0_MASK (0x8U)
43269#define ENET_QOS_RX_FLUSH0_SHIFT (3U)
43270/*! RX_FLUSH0 - RX Flush Ring 0
43271 * 0b0..Disable
43272 * 0b1..Enable
43273 */
43274#define ENET_QOS_RX_FLUSH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK)
43275#define ENET_QOS_RX_FLUSH1_MASK (0x10U)
43276#define ENET_QOS_RX_FLUSH1_SHIFT (4U)
43277/*! RX_FLUSH1 - RX Flush Ring 1
43278 * 0b0..Disable
43279 * 0b1..Enable
43280 */
43281#define ENET_QOS_RX_FLUSH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK)
43282#define ENET_QOS_RX_FLUSH2_MASK (0x20U)
43283#define ENET_QOS_RX_FLUSH2_SHIFT (5U)
43284/*! RX_FLUSH2 - RX Flush Ring 2
43285 * 0b0..Disable
43286 * 0b1..Enable
43287 */
43288#define ENET_QOS_RX_FLUSH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK)
43289/*! @} */
43290
43291/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
43292/*! @{ */
43293#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
43294#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
43295/*! TXPKTS - Packet count
43296 */
43297#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
43298/*! @} */
43299
43300/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
43301/*! @{ */
43302#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
43303#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
43304/*! TXPKTS - Broadcast packets
43305 */
43306#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
43307/*! @} */
43308
43309/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
43310/*! @{ */
43311#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
43312#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
43313/*! TXPKTS - Multicast packets
43314 */
43315#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
43316/*! @} */
43317
43318/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
43319/*! @{ */
43320#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
43321#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
43322/*! TXPKTS - Packets with CRC/align error
43323 */
43324#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
43325/*! @} */
43326
43327/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
43328/*! @{ */
43329#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
43330#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
43331/*! TXPKTS - Number of transmit packets less than 64 bytes with good CRC
43332 */
43333#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
43334/*! @} */
43335
43336/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
43337/*! @{ */
43338#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
43339#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
43340/*! TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC
43341 */
43342#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
43343/*! @} */
43344
43345/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
43346/*! @{ */
43347#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
43348#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
43349/*! TXPKTS - Number of packets less than 64 bytes with bad CRC
43350 */
43351#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
43352/*! @} */
43353
43354/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
43355/*! @{ */
43356#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
43357#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
43358/*! TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC
43359 */
43360#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
43361/*! @} */
43362
43363/*! @name RMON_T_COL - Tx Collision Count Statistic Register */
43364/*! @{ */
43365#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
43366#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
43367/*! TXPKTS - Number of transmit collisions
43368 */
43369#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
43370/*! @} */
43371
43372/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
43373/*! @{ */
43374#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
43375#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
43376/*! TXPKTS - Number of 64-byte transmit packets
43377 */
43378#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
43379/*! @} */
43380
43381/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
43382/*! @{ */
43383#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
43384#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
43385/*! TXPKTS - Number of 65- to 127-byte transmit packets
43386 */
43387#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
43388/*! @} */
43389
43390/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
43391/*! @{ */
43392#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
43393#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
43394/*! TXPKTS - Number of 128- to 255-byte transmit packets
43395 */
43396#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
43397/*! @} */
43398
43399/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
43400/*! @{ */
43401#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
43402#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
43403/*! TXPKTS - Number of 256- to 511-byte transmit packets
43404 */
43405#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
43406/*! @} */
43407
43408/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
43409/*! @{ */
43410#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
43411#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
43412/*! TXPKTS - Number of 512- to 1023-byte transmit packets
43413 */
43414#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
43415/*! @} */
43416
43417/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
43418/*! @{ */
43419#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
43420#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
43421/*! TXPKTS - Number of 1024- to 2047-byte transmit packets
43422 */
43423#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
43424/*! @} */
43425
43426/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
43427/*! @{ */
43428#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
43429#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
43430/*! TXPKTS - Number of transmit packets greater than 2048 bytes
43431 */
43432#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
43433/*! @} */
43434
43435/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
43436/*! @{ */
43437#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
43438#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
43439/*! TXOCTS - Number of transmit octets
43440 */
43441#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
43442/*! @} */
43443
43444/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
43445/*! @{ */
43446#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
43447#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
43448/*! COUNT - Number of frames transmitted OK
43449 */
43450#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
43451/*! @} */
43452
43453/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
43454/*! @{ */
43455#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
43456#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
43457/*! COUNT - Number of frames transmitted with one collision
43458 */
43459#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
43460/*! @} */
43461
43462/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
43463/*! @{ */
43464#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
43465#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
43466/*! COUNT - Number of frames transmitted with multiple collisions
43467 */
43468#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
43469/*! @} */
43470
43471/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
43472/*! @{ */
43473#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
43474#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
43475/*! COUNT - Number of frames transmitted with deferral delay
43476 */
43477#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
43478/*! @} */
43479
43480/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
43481/*! @{ */
43482#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
43483#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
43484/*! COUNT - Number of frames transmitted with late collision
43485 */
43486#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
43487/*! @} */
43488
43489/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
43490/*! @{ */
43491#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
43492#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
43493/*! COUNT - Number of frames transmitted with excessive collisions
43494 */
43495#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
43496/*! @} */
43497
43498/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
43499/*! @{ */
43500#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
43501#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
43502/*! COUNT - Number of frames transmitted with transmit FIFO underrun
43503 */
43504#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
43505/*! @} */
43506
43507/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
43508/*! @{ */
43509#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
43510#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
43511/*! COUNT - Number of frames transmitted with carrier sense error
43512 */
43513#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
43514/*! @} */
43515
43516/*! @name IEEE_T_SQE - Reserved Statistic Register */
43517/*! @{ */
43518#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)
43519#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U)
43520/*! COUNT - This read-only field is reserved and always has the value 0
43521 */
43522#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
43523/*! @} */
43524
43525/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
43526/*! @{ */
43527#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
43528#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
43529/*! COUNT - Number of flow-control pause frames transmitted
43530 */
43531#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
43532/*! @} */
43533
43534/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
43535/*! @{ */
43536#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
43537#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
43538/*! COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields).
43539 */
43540#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
43541/*! @} */
43542
43543/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
43544/*! @{ */
43545#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
43546#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
43547/*! COUNT - Number of packets received
43548 */
43549#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
43550/*! @} */
43551
43552/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
43553/*! @{ */
43554#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
43555#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
43556/*! COUNT - Number of receive broadcast packets
43557 */
43558#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
43559/*! @} */
43560
43561/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
43562/*! @{ */
43563#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
43564#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
43565/*! COUNT - Number of receive multicast packets
43566 */
43567#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
43568/*! @} */
43569
43570/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
43571/*! @{ */
43572#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
43573#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
43574/*! COUNT - Number of receive packets with CRC or align error
43575 */
43576#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
43577/*! @} */
43578
43579/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
43580/*! @{ */
43581#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
43582#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
43583/*! COUNT - Number of receive packets with less than 64 bytes and good CRC
43584 */
43585#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
43586/*! @} */
43587
43588/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
43589/*! @{ */
43590#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
43591#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
43592/*! COUNT - Number of receive packets greater than MAX_FL and good CRC
43593 */
43594#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
43595/*! @} */
43596
43597/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
43598/*! @{ */
43599#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
43600#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
43601/*! COUNT - Number of receive packets with less than 64 bytes and bad CRC
43602 */
43603#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
43604/*! @} */
43605
43606/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
43607/*! @{ */
43608#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
43609#define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
43610/*! COUNT - Number of receive packets greater than MAX_FL and bad CRC
43611 */
43612#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
43613/*! @} */
43614
43615/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
43616/*! @{ */
43617#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
43618#define ENET_RMON_R_P64_COUNT_SHIFT (0U)
43619/*! COUNT - Number of 64-byte receive packets
43620 */
43621#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
43622/*! @} */
43623
43624/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
43625/*! @{ */
43626#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
43627#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
43628/*! COUNT - Number of 65- to 127-byte recieve packets
43629 */
43630#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
43631/*! @} */
43632
43633/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
43634/*! @{ */
43635#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
43636#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
43637/*! COUNT - Number of 128- to 255-byte recieve packets
43638 */
43639#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
43640/*! @} */
43641
43642/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
43643/*! @{ */
43644#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
43645#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
43646/*! COUNT - Number of 256- to 511-byte recieve packets
43647 */
43648#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
43649/*! @} */
43650
43651/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
43652/*! @{ */
43653#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
43654#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
43655/*! COUNT - Number of 512- to 1023-byte recieve packets
43656 */
43657#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
43658/*! @} */
43659
43660/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
43661/*! @{ */
43662#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
43663#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
43664/*! COUNT - Number of 1024- to 2047-byte recieve packets
43665 */
43666#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
43667/*! @} */
43668
43669/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
43670/*! @{ */
43671#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
43672#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
43673/*! COUNT - Number of greater-than-2048-byte recieve packets
43674 */
43675#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
43676/*! @} */
43677
43678/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
43679/*! @{ */
43680#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
43681#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
43682/*! COUNT - Number of receive octets
43683 */
43684#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
43685/*! @} */
43686
43687/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
43688/*! @{ */
43689#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
43690#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
43691/*! COUNT - Frame count
43692 */
43693#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
43694/*! @} */
43695
43696/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
43697/*! @{ */
43698#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
43699#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
43700/*! COUNT - Number of frames received OK
43701 */
43702#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
43703/*! @} */
43704
43705/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
43706/*! @{ */
43707#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
43708#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
43709/*! COUNT - Number of frames received with CRC error
43710 */
43711#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
43712/*! @} */
43713
43714/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
43715/*! @{ */
43716#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
43717#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
43718/*! COUNT - Number of frames received with alignment error
43719 */
43720#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
43721/*! @} */
43722
43723/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
43724/*! @{ */
43725#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
43726#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
43727/*! COUNT - Receive FIFO overflow count
43728 */
43729#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
43730/*! @} */
43731
43732/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
43733/*! @{ */
43734#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
43735#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
43736/*! COUNT - Number of flow-control pause frames received
43737 */
43738#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
43739/*! @} */
43740
43741/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
43742/*! @{ */
43743#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
43744#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
43745/*! COUNT - Number of octets for frames received without error
43746 */
43747#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
43748/*! @} */
43749
43750/*! @name ATCR - Adjustable Timer Control Register */
43751/*! @{ */
43752#define ENET_ATCR_EN_MASK (0x1U)
43753#define ENET_ATCR_EN_SHIFT (0U)
43754/*! EN - Enable Timer
43755 * 0b0..The timer stops at the current value.
43756 * 0b1..The timer starts incrementing.
43757 */
43758#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
43759#define ENET_ATCR_OFFEN_MASK (0x4U)
43760#define ENET_ATCR_OFFEN_SHIFT (2U)
43761/*! OFFEN - Enable One-Shot Offset Event
43762 * 0b0..Disable.
43763 * 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared
43764 * when the offset event is reached, so no further event occurs until the field is set again. The timer
43765 * offset value must be set before setting this field.
43766 */
43767#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
43768#define ENET_ATCR_OFFRST_MASK (0x8U)
43769#define ENET_ATCR_OFFRST_SHIFT (3U)
43770/*! OFFRST - Reset Timer On Offset Event
43771 * 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached.
43772 * 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
43773 */
43774#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
43775#define ENET_ATCR_PEREN_MASK (0x10U)
43776#define ENET_ATCR_PEREN_SHIFT (4U)
43777/*! PEREN - Enable Periodical Event
43778 * 0b0..Disable.
43779 * 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when
43780 * the timer wraps around according to the periodic setting ATPER. The timer period value must be set before
43781 * setting this bit. Not all devices contain the event signal output. See the chip configuration details.
43782 */
43783#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
43784#define ENET_ATCR_PINPER_MASK (0x80U)
43785#define ENET_ATCR_PINPER_SHIFT (7U)
43786/*! PINPER - Enables event signal output external pin frc_evt_period assertion on period event
43787 * 0b0..Disable.
43788 * 0b1..Enable.
43789 */
43790#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
43791#define ENET_ATCR_RESTART_MASK (0x200U)
43792#define ENET_ATCR_RESTART_SHIFT (9U)
43793/*! RESTART - Reset Timer
43794 */
43795#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
43796#define ENET_ATCR_CAPTURE_MASK (0x800U)
43797#define ENET_ATCR_CAPTURE_SHIFT (11U)
43798/*! CAPTURE - Capture Timer Value
43799 * 0b0..No effect.
43800 * 0b1..The current time is captured and can be read from the ATVR register.
43801 */
43802#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
43803#define ENET_ATCR_SLAVE_MASK (0x2000U)
43804#define ENET_ATCR_SLAVE_SHIFT (13U)
43805/*! SLAVE - Enable Timer Slave Mode
43806 * 0b0..The timer is active and all configuration fields in this register are relevant.
43807 * 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except
43808 * CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
43809 */
43810#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
43811/*! @} */
43812
43813/*! @name ATVR - Timer Value Register */
43814/*! @{ */
43815#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
43816#define ENET_ATVR_ATIME_SHIFT (0U)
43817#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
43818/*! @} */
43819
43820/*! @name ATOFF - Timer Offset Register */
43821/*! @{ */
43822#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
43823#define ENET_ATOFF_OFFSET_SHIFT (0U)
43824#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
43825/*! @} */
43826
43827/*! @name ATPER - Timer Period Register */
43828/*! @{ */
43829#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
43830#define ENET_ATPER_PERIOD_SHIFT (0U)
43831/*! PERIOD - Value for generating periodic events
43832 */
43833#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
43834/*! @} */
43835
43836/*! @name ATCOR - Timer Correction Register */
43837/*! @{ */
43838#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
43839#define ENET_ATCOR_COR_SHIFT (0U)
43840/*! COR - Correction Counter Wrap-Around Value
43841 */
43842#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
43843/*! @} */
43844
43845/*! @name ATINC - Time-Stamping Clock Period Register */
43846/*! @{ */
43847#define ENET_ATINC_INC_MASK (0x7FU)
43848#define ENET_ATINC_INC_SHIFT (0U)
43849/*! INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds
43850 */
43851#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
43852#define ENET_ATINC_INC_CORR_MASK (0x7F00U)
43853#define ENET_ATINC_INC_CORR_SHIFT (8U)
43854/*! INC_CORR - Correction Increment Value
43855 */
43856#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
43857/*! @} */
43858
43859/*! @name ATSTMP - Timestamp of Last Transmitted Frame */
43860/*! @{ */
43861#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
43862#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
43863/*! TIMESTAMP - Timestamp of the last frame transmitted by the core that had TxBD[TS] set the
43864 * ff_tx_ts_frm signal asserted from the user application
43865 */
43866#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
43867/*! @} */
43868
43869/*! @name MDATA - Pattern Match Data Register */
43870/*! @{ */
43871#define ENET_MDATA_MATCHDATA_MASK (0xFFFFFFFFU)
43872#define ENET_MDATA_MATCHDATA_SHIFT (0U)
43873/*! MATCHDATA - Match Data
43874 */
43875#define ENET_MDATA_MATCHDATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MDATA_MATCHDATA_SHIFT)) & ENET_MDATA_MATCHDATA_MASK)
43876/*! @} */
43877
43878/*! @name MMASK - Match Entry Mask Register */
43879/*! @{ */
43880#define ENET_MMASK_MATCHMASK_MASK (0xFFFFFFFFU)
43881#define ENET_MMASK_MATCHMASK_SHIFT (0U)
43882/*! MATCHMASK - Match Mask
43883 */
43884#define ENET_MMASK_MATCHMASK(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMASK_MATCHMASK_SHIFT)) & ENET_MMASK_MATCHMASK_MASK)
43885/*! @} */
43886
43887/*! @name MCONFIG - Match Entry Rules Configuration Register */
43888/*! @{ */
43889#define ENET_MCONFIG_FRMOFF_MASK (0xFCU)
43890#define ENET_MCONFIG_FRMOFF_SHIFT (2U)
43891/*! FRMOFF - Frame Offset
43892 */
43893#define ENET_MCONFIG_FRMOFF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MCONFIG_FRMOFF_SHIFT)) & ENET_MCONFIG_FRMOFF_MASK)
43894#define ENET_MCONFIG_OK_INDEX_MASK (0xFF0000U)
43895#define ENET_MCONFIG_OK_INDEX_SHIFT (16U)
43896/*! OK_INDEX - When AF = 0 and RF = 0, this value shows the next entry of the matching table to be
43897 * used for comparison instead of using the next entry sequentially
43898 */
43899#define ENET_MCONFIG_OK_INDEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MCONFIG_OK_INDEX_SHIFT)) & ENET_MCONFIG_OK_INDEX_MASK)
43900#define ENET_MCONFIG_IM_MASK (0x20000000U)
43901#define ENET_MCONFIG_IM_SHIFT (29U)
43902/*! IM - Invert Match
43903 */
43904#define ENET_MCONFIG_IM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MCONFIG_IM_SHIFT)) & ENET_MCONFIG_IM_MASK)
43905#define ENET_MCONFIG_RF_MASK (0x40000000U)
43906#define ENET_MCONFIG_RF_SHIFT (30U)
43907/*! RF - Reject Frame
43908 */
43909#define ENET_MCONFIG_RF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MCONFIG_RF_SHIFT)) & ENET_MCONFIG_RF_MASK)
43910#define ENET_MCONFIG_AF_MASK (0x80000000U)
43911#define ENET_MCONFIG_AF_SHIFT (31U)
43912/*! AF - Accept Frame
43913 */
43914#define ENET_MCONFIG_AF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MCONFIG_AF_SHIFT)) & ENET_MCONFIG_AF_MASK)
43915/*! @} */
43916
43917/*! @name MENTRYRW - Match Entry Read/Write Command Register */
43918/*! @{ */
43919#define ENET_MENTRYRW_ENTRYADD_MASK (0xFFU)
43920#define ENET_MENTRYRW_ENTRYADD_SHIFT (0U)
43921/*! ENTRYADD - Entry Address
43922 */
43923#define ENET_MENTRYRW_ENTRYADD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MENTRYRW_ENTRYADD_SHIFT)) & ENET_MENTRYRW_ENTRYADD_MASK)
43924#define ENET_MENTRYRW_WR_MASK (0x100U)
43925#define ENET_MENTRYRW_WR_SHIFT (8U)
43926/*! WR - Entry write command
43927 */
43928#define ENET_MENTRYRW_WR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MENTRYRW_WR_SHIFT)) & ENET_MENTRYRW_WR_MASK)
43929#define ENET_MENTRYRW_RD_MASK (0x200U)
43930#define ENET_MENTRYRW_RD_SHIFT (9U)
43931/*! RD - Entry Read Command
43932 */
43933#define ENET_MENTRYRW_RD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MENTRYRW_RD_SHIFT)) & ENET_MENTRYRW_RD_MASK)
43934/*! @} */
43935
43936/*! @name RXPCTL - Receive Parser Control Register */
43937/*! @{ */
43938#define ENET_RXPCTL_ENPARSER_MASK (0x1U)
43939#define ENET_RXPCTL_ENPARSER_SHIFT (0U)
43940/*! ENPARSER - Enable Receive Parser
43941 * 0b0..Parser is disabled.
43942 * 0b1..Parser is enabled.
43943 */
43944#define ENET_RXPCTL_ENPARSER(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPCTL_ENPARSER_SHIFT)) & ENET_RXPCTL_ENPARSER_MASK)
43945#define ENET_RXPCTL_INVBYTORD_MASK (0x2U)
43946#define ENET_RXPCTL_INVBYTORD_SHIFT (1U)
43947/*! INVBYTORD - Inverse Frame Byte Order
43948 */
43949#define ENET_RXPCTL_INVBYTORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPCTL_INVBYTORD_SHIFT)) & ENET_RXPCTL_INVBYTORD_MASK)
43950#define ENET_RXPCTL_PRSRSCLR_MASK (0x10U)
43951#define ENET_RXPCTL_PRSRSCLR_SHIFT (4U)
43952/*! PRSRSCLR - Clear Parser Statistics Counter
43953 */
43954#define ENET_RXPCTL_PRSRSCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPCTL_PRSRSCLR_SHIFT)) & ENET_RXPCTL_PRSRSCLR_MASK)
43955#define ENET_RXPCTL_MAXINDEX_MASK (0xFF00U)
43956#define ENET_RXPCTL_MAXINDEX_SHIFT (8U)
43957/*! MAXINDEX - Maximum Index
43958 */
43959#define ENET_RXPCTL_MAXINDEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPCTL_MAXINDEX_SHIFT)) & ENET_RXPCTL_MAXINDEX_MASK)
43960#define ENET_RXPCTL_ENDERRQ_MASK (0xFF0000U)
43961#define ENET_RXPCTL_ENDERRQ_SHIFT (16U)
43962/*! ENDERRQ - End Error Queue
43963 * 0b00000001..Place the frame in Queue 0
43964 * 0b00000010..Place the frame in Queue 1
43965 * 0b00000100..Place the frame in Queue 2
43966 */
43967#define ENET_RXPCTL_ENDERRQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPCTL_ENDERRQ_SHIFT)) & ENET_RXPCTL_ENDERRQ_MASK)
43968#define ENET_RXPCTL_ACPTEERR_MASK (0x1000000U)
43969#define ENET_RXPCTL_ACPTEERR_SHIFT (24U)
43970/*! ACPTEERR - Accept End Error
43971 */
43972#define ENET_RXPCTL_ACPTEERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPCTL_ACPTEERR_SHIFT)) & ENET_RXPCTL_ACPTEERR_MASK)
43973/*! @} */
43974
43975/*! @name MAXFRMOFF - Maximum Frame Offset */
43976/*! @{ */
43977#define ENET_MAXFRMOFF_MXFRMOFF_MASK (0x3FU)
43978#define ENET_MAXFRMOFF_MXFRMOFF_SHIFT (0U)
43979/*! MXFRMOFF - Max. Frame Offset
43980 */
43981#define ENET_MAXFRMOFF_MXFRMOFF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAXFRMOFF_MXFRMOFF_SHIFT)) & ENET_MAXFRMOFF_MXFRMOFF_MASK)
43982/*! @} */
43983
43984/*! @name RXPARST - Receive Parser Status */
43985/*! @{ */
43986#define ENET_RXPARST_MXINDERR_MASK (0x1U)
43987#define ENET_RXPARST_MXINDERR_SHIFT (0U)
43988/*! MXINDERR - Maximum Index Error
43989 */
43990#define ENET_RXPARST_MXINDERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_MXINDERR_SHIFT)) & ENET_RXPARST_MXINDERR_MASK)
43991#define ENET_RXPARST_TBLDPTERR_MASK (0x2U)
43992#define ENET_RXPARST_TBLDPTERR_SHIFT (1U)
43993/*! TBLDPTERR - Table Depth Error
43994 */
43995#define ENET_RXPARST_TBLDPTERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_TBLDPTERR_SHIFT)) & ENET_RXPARST_TBLDPTERR_MASK)
43996#define ENET_RXPARST_NOMTCERR_MASK (0x4U)
43997#define ENET_RXPARST_NOMTCERR_SHIFT (2U)
43998/*! NOMTCERR - No Match Error
43999 */
44000#define ENET_RXPARST_NOMTCERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_NOMTCERR_SHIFT)) & ENET_RXPARST_NOMTCERR_MASK)
44001#define ENET_RXPARST_FMOFFERR_MASK (0x8U)
44002#define ENET_RXPARST_FMOFFERR_SHIFT (3U)
44003/*! FMOFFERR - Maximum Frame Offset Error
44004 */
44005#define ENET_RXPARST_FMOFFERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_FMOFFERR_SHIFT)) & ENET_RXPARST_FMOFFERR_MASK)
44006#define ENET_RXPARST_PRSENDERR_MASK (0x10U)
44007#define ENET_RXPARST_PRSENDERR_SHIFT (4U)
44008/*! PRSENDERR - Parser End Error
44009 */
44010#define ENET_RXPARST_PRSENDERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_PRSENDERR_SHIFT)) & ENET_RXPARST_PRSENDERR_MASK)
44011#define ENET_RXPARST_INVMAXIDX_MASK (0x20U)
44012#define ENET_RXPARST_INVMAXIDX_SHIFT (5U)
44013/*! INVMAXIDX - Invalid Value of MAXINDEX
44014 */
44015#define ENET_RXPARST_INVMAXIDX(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_INVMAXIDX_SHIFT)) & ENET_RXPARST_INVMAXIDX_MASK)
44016#define ENET_RXPARST_RXPRSDN_MASK (0x100U)
44017#define ENET_RXPARST_RXPRSDN_SHIFT (8U)
44018/*! RXPRSDN - Receive Parser Done
44019 */
44020#define ENET_RXPARST_RXPRSDN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXPARST_RXPRSDN_SHIFT)) & ENET_RXPARST_RXPRSDN_MASK)
44021/*! @} */
44022
44023/*! @name PARSDSCD - Parser Discard Count */
44024/*! @{ */
44025#define ENET_PARSDSCD_COUNT_MASK (0xFFFFFFFFU)
44026#define ENET_PARSDSCD_COUNT_SHIFT (0U)
44027/*! COUNT - Count
44028 */
44029#define ENET_PARSDSCD_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_PARSDSCD_COUNT_SHIFT)) & ENET_PARSDSCD_COUNT_MASK)
44030/*! @} */
44031
44032/*! @name PRSACPT0 - Parser Accept Count 0 */
44033/*! @{ */
44034#define ENET_PRSACPT0_COUNT_MASK (0xFFFFFFFFU)
44035#define ENET_PRSACPT0_COUNT_SHIFT (0U)
44036/*! COUNT - Count
44037 */
44038#define ENET_PRSACPT0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_PRSACPT0_COUNT_SHIFT)) & ENET_PRSACPT0_COUNT_MASK)
44039/*! @} */
44040
44041/*! @name PRSRJCT0 - Parser Reject Count 0 */
44042/*! @{ */
44043#define ENET_PRSRJCT0_COUNT_MASK (0xFFFFFFFFU)
44044#define ENET_PRSRJCT0_COUNT_SHIFT (0U)
44045/*! COUNT - Count
44046 */
44047#define ENET_PRSRJCT0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_PRSRJCT0_COUNT_SHIFT)) & ENET_PRSRJCT0_COUNT_MASK)
44048/*! @} */
44049
44050/*! @name PRSACPT1 - Parser Accept Count 1 */
44051/*! @{ */
44052#define ENET_PRSACPT1_COUNT_MASK (0xFFFFFFFFU)
44053#define ENET_PRSACPT1_COUNT_SHIFT (0U)
44054/*! COUNT - Count
44055 */
44056#define ENET_PRSACPT1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_PRSACPT1_COUNT_SHIFT)) & ENET_PRSACPT1_COUNT_MASK)
44057/*! @} */
44058
44059/*! @name PRSRJCT1 - Parser Reject Count 1 */
44060/*! @{ */
44061#define ENET_PRSRJCT1_COUNT_MASK (0xFFFFFFFFU)
44062#define ENET_PRSRJCT1_COUNT_SHIFT (0U)
44063/*! COUNT - Count
44064 */
44065#define ENET_PRSRJCT1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_PRSRJCT1_COUNT_SHIFT)) & ENET_PRSRJCT1_COUNT_MASK)
44066/*! @} */
44067
44068/*! @name PRSACPT2 - Parser Accept Count 2 */
44069/*! @{ */
44070#define ENET_PRSACPT2_COUNT_MASK (0xFFFFFFFFU)
44071#define ENET_PRSACPT2_COUNT_SHIFT (0U)
44072/*! COUNT - Count
44073 */
44074#define ENET_PRSACPT2_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_PRSACPT2_COUNT_SHIFT)) & ENET_PRSACPT2_COUNT_MASK)
44075/*! @} */
44076
44077/*! @name PRSRJCT2 - Parser Reject Count 2 */
44078/*! @{ */
44079#define ENET_PRSRJCT2_COUNT_MASK (0xFFFFFFFFU)
44080#define ENET_PRSRJCT2_COUNT_SHIFT (0U)
44081/*! COUNT - Count
44082 */
44083#define ENET_PRSRJCT2_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_PRSRJCT2_COUNT_SHIFT)) & ENET_PRSRJCT2_COUNT_MASK)
44084/*! @} */
44085
44086/*! @name TGSR - Timer Global Status Register */
44087/*! @{ */
44088#define ENET_TGSR_TF0_MASK (0x1U)
44089#define ENET_TGSR_TF0_SHIFT (0U)
44090/*! TF0 - Copy Of Timer Flag For Channel 0
44091 * 0b0..Timer Flag for Channel 0 is clear
44092 * 0b1..Timer Flag for Channel 0 is set
44093 */
44094#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
44095#define ENET_TGSR_TF1_MASK (0x2U)
44096#define ENET_TGSR_TF1_SHIFT (1U)
44097/*! TF1 - Copy Of Timer Flag For Channel 1
44098 * 0b0..Timer Flag for Channel 1 is clear
44099 * 0b1..Timer Flag for Channel 1 is set
44100 */
44101#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
44102#define ENET_TGSR_TF2_MASK (0x4U)
44103#define ENET_TGSR_TF2_SHIFT (2U)
44104/*! TF2 - Copy Of Timer Flag For Channel 2
44105 * 0b0..Timer Flag for Channel 2 is clear
44106 * 0b1..Timer Flag for Channel 2 is set
44107 */
44108#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
44109#define ENET_TGSR_TF3_MASK (0x8U)
44110#define ENET_TGSR_TF3_SHIFT (3U)
44111/*! TF3 - Copy Of Timer Flag For Channel 3
44112 * 0b0..Timer Flag for Channel 3 is clear
44113 * 0b1..Timer Flag for Channel 3 is set
44114 */
44115#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
44116/*! @} */
44117
44118/*! @name TCSR - Timer Control Status Register */
44119/*! @{ */
44120#define ENET_TCSR_TDRE_MASK (0x1U)
44121#define ENET_TCSR_TDRE_SHIFT (0U)
44122/*! TDRE - Timer DMA Request Enable
44123 * 0b0..DMA request is disabled
44124 * 0b1..DMA request is enabled
44125 */
44126#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
44127#define ENET_TCSR_TMODE_MASK (0x3CU)
44128#define ENET_TCSR_TMODE_SHIFT (2U)
44129/*! TMODE - Timer Mode
44130 * 0b0000..Timer Channel is disabled.
44131 * 0b0001..Timer Channel is configured for Input Capture on rising edge.
44132 * 0b0010..Timer Channel is configured for Input Capture on falling edge.
44133 * 0b0011..Timer Channel is configured for Input Capture on both edges.
44134 * 0b0100..Timer Channel is configured for Output Compare - software only.
44135 * 0b0101..Timer Channel is configured for Output Compare - toggle output on compare.
44136 * 0b0110..Timer Channel is configured for Output Compare - clear output on compare.
44137 * 0b0111..Timer Channel is configured for Output Compare - set output on compare.
44138 * 0b1000..Reserved
44139 * 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
44140 * 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
44141 * 0b110x..Reserved
44142 * 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC.
44143 * 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.
44144 */
44145#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
44146#define ENET_TCSR_TIE_MASK (0x40U)
44147#define ENET_TCSR_TIE_SHIFT (6U)
44148/*! TIE - Timer Interrupt Enable
44149 * 0b0..Interrupt is disabled
44150 * 0b1..Interrupt is enabled
44151 */
44152#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
44153#define ENET_TCSR_TF_MASK (0x80U)
44154#define ENET_TCSR_TF_SHIFT (7U)
44155/*! TF - Timer Flag
44156 * 0b0..Input Capture or Output Compare has not occurred.
44157 * 0b1..Input Capture or Output Compare has occurred.
44158 */
44159#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
44160#define ENET_TCSR_TPWC_MASK (0xF800U)
44161#define ENET_TCSR_TPWC_SHIFT (11U)
44162/*! TPWC - Timer PulseWidth Control
44163 * 0b00000..Pulse width is one 1588-clock cycle.
44164 * 0b00001..Pulse width is two 1588-clock cycles.
44165 * 0b00010..Pulse width is three 1588-clock cycles.
44166 * 0b00011..Pulse width is four 1588-clock cycles.
44167 * 0b11111..Pulse width is 32 1588-clock cycles.
44168 */
44169#define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)
44170/*! @} */
44171
44172/* The count of ENET_TCSR */
44173#define ENET_TCSR_COUNT (4U)
44174
44175/*! @name TCCR - Timer Compare Capture Register */
44176/*! @{ */
44177#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
44178#define ENET_TCCR_TCC_SHIFT (0U)
44179/*! TCC - Timer Capture Compare
44180 */
44181#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
44182/*! @} */
44183
44184/* The count of ENET_TCCR */
44185#define ENET_TCCR_COUNT (4U)
44186
44187
44188/*!
44189 * @}
44190 */ /* end of group ENET_Register_Masks */
44191
44192
44193/* ENET - Peripheral instance base addresses */
44194/** Peripheral CONNECTIVITY__ENET0 base address */
44195#define CONNECTIVITY__ENET0_BASE (0x5B040000u)
44196/** Peripheral CONNECTIVITY__ENET0 base pointer */
44197#define CONNECTIVITY__ENET0 ((ENET_Type *)CONNECTIVITY__ENET0_BASE)
44198/** Peripheral CONNECTIVITY__ENET1 base address */
44199#define CONNECTIVITY__ENET1_BASE (0x5B050000u)
44200/** Peripheral CONNECTIVITY__ENET1 base pointer */
44201#define CONNECTIVITY__ENET1 ((ENET_Type *)CONNECTIVITY__ENET1_BASE)
44202/** Array initializer of ENET peripheral base addresses */
44203#define ENET_BASE_ADDRS { CONNECTIVITY__ENET0_BASE, CONNECTIVITY__ENET1_BASE }
44204/** Array initializer of ENET peripheral base pointers */
44205#define ENET_BASE_PTRS { CONNECTIVITY__ENET0, CONNECTIVITY__ENET1 }
44206/* ENET Buffer Descriptor and Buffer Address Alignment. */
44207#define ENET_BUFF_ALIGNMENT (64U)
44208
44209/* Interrupt vectors for the ENET peripheral type */
44210#define ENET_Transmit_IRQS { NotAvail_IRQn, NotAvail_IRQn }
44211#define ENET_Receive_IRQS { NotAvail_IRQn, NotAvail_IRQn }
44212#define ENET_Error_IRQS { NotAvail_IRQn, NotAvail_IRQn }
44213#define ENET_1588_Timer_IRQS { NotAvail_IRQn, NotAvail_IRQn }
44214
44215
44216/*!
44217 * @}
44218 */ /* end of group ENET_Peripheral_Access_Layer */
44219
44220
44221/* ----------------------------------------------------------------------------
44222 -- ESAI Peripheral Access Layer
44223 ---------------------------------------------------------------------------- */
44224
44225/*!
44226 * @addtogroup ESAI_Peripheral_Access_Layer ESAI Peripheral Access Layer
44227 * @{
44228 */
44229
44230/** ESAI - Register Layout Typedef */
44231typedef struct {
44232 __O uint32_t ETDR; /**< ESAI Transmit Data Register, offset: 0x0 */
44233 __I uint32_t ERDR; /**< ESAI Receive Data Register, offset: 0x4 */
44234 __IO uint32_t ECR; /**< ESAI Control Register, offset: 0x8 */
44235 __I uint32_t ESR; /**< ESAI Status Register, offset: 0xC */
44236 __IO uint32_t TFCR; /**< Transmit FIFO Configuration Register, offset: 0x10 */
44237 __I uint32_t TFSR; /**< Transmit FIFO Status Register, offset: 0x14 */
44238 __IO uint32_t RFCR; /**< Receive FIFO Configuration Register, offset: 0x18 */
44239 __I uint32_t RFSR; /**< Receive FIFO Status Register, offset: 0x1C */
44240 uint8_t RESERVED_0[96];
44241 __O uint32_t TX[6]; /**< Transmit Data Register n, array offset: 0x80, array step: 0x4 */
44242 __O uint32_t TSR; /**< ESAI Transmit Slot Register, offset: 0x98 */
44243 uint8_t RESERVED_1[4];
44244 __I uint32_t RX[4]; /**< Receive Data Register n, array offset: 0xA0, array step: 0x4 */
44245 uint8_t RESERVED_2[28];
44246 __I uint32_t SAISR; /**< Serial Audio Interface Status Register, offset: 0xCC */
44247 __IO uint32_t SAICR; /**< Serial Audio Interface Control Register, offset: 0xD0 */
44248 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xD4 */
44249 __IO uint32_t TCCR; /**< Transmit Clock Control Register, offset: 0xD8 */
44250 __IO uint32_t RCR; /**< Receive Control Register, offset: 0xDC */
44251 __IO uint32_t RCCR; /**< Receive Clock Control Register, offset: 0xE0 */
44252 __IO uint32_t TSMA; /**< Transmit Slot Mask Register A, offset: 0xE4 */
44253 __IO uint32_t TSMB; /**< Transmit Slot Mask Register B, offset: 0xE8 */
44254 __IO uint32_t RSMA; /**< Receive Slot Mask Register A, offset: 0xEC */
44255 __IO uint32_t RSMB; /**< Receive Slot Mask Register B, offset: 0xF0 */
44256 uint8_t RESERVED_3[4];
44257 __IO uint32_t PRRC; /**< Port C Direction Register, offset: 0xF8 */
44258 __IO uint32_t PCRC; /**< Port C Control Register, offset: 0xFC */
44259} ESAI_Type;
44260
44261/* ----------------------------------------------------------------------------
44262 -- ESAI Register Masks
44263 ---------------------------------------------------------------------------- */
44264
44265/*!
44266 * @addtogroup ESAI_Register_Masks ESAI Register Masks
44267 * @{
44268 */
44269
44270/*! @name ETDR - ESAI Transmit Data Register */
44271/*! @{ */
44272#define ESAI_ETDR_ETDR_MASK (0xFFFFFFFFU)
44273#define ESAI_ETDR_ETDR_SHIFT (0U)
44274/*! ETDR - ETDR
44275 */
44276#define ESAI_ETDR_ETDR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ETDR_ETDR_SHIFT)) & ESAI_ETDR_ETDR_MASK)
44277/*! @} */
44278
44279/*! @name ERDR - ESAI Receive Data Register */
44280/*! @{ */
44281#define ESAI_ERDR_ERDR_MASK (0xFFFFFFFFU)
44282#define ESAI_ERDR_ERDR_SHIFT (0U)
44283/*! ERDR - ERDR
44284 */
44285#define ESAI_ERDR_ERDR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ERDR_ERDR_SHIFT)) & ESAI_ERDR_ERDR_MASK)
44286/*! @} */
44287
44288/*! @name ECR - ESAI Control Register */
44289/*! @{ */
44290#define ESAI_ECR_ESAIEN_MASK (0x1U)
44291#define ESAI_ECR_ESAIEN_SHIFT (0U)
44292/*! ESAIEN - ESAIEN
44293 * 0b0..ESAI disabled.
44294 * 0b1..ESAI enabled.
44295 */
44296#define ESAI_ECR_ESAIEN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ESAIEN_SHIFT)) & ESAI_ECR_ESAIEN_MASK)
44297#define ESAI_ECR_ERST_MASK (0x2U)
44298#define ESAI_ECR_ERST_SHIFT (1U)
44299/*! ERST - ERST
44300 * 0b0..ESAI not reset.
44301 * 0b1..ESAI reset.
44302 */
44303#define ESAI_ECR_ERST(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERST_SHIFT)) & ESAI_ECR_ERST_MASK)
44304#define ESAI_ECR_ERO_MASK (0x10000U)
44305#define ESAI_ECR_ERO_SHIFT (16U)
44306/*! ERO - ERO
44307 * 0b0..HCKR pin has normal function.
44308 * 0b1..EXTAL driven onto HCKR pin.
44309 */
44310#define ESAI_ECR_ERO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERO_SHIFT)) & ESAI_ECR_ERO_MASK)
44311#define ESAI_ECR_ERI_MASK (0x20000U)
44312#define ESAI_ECR_ERI_SHIFT (17U)
44313/*! ERI - ERI
44314 * 0b0..HCKR pin has normal function.
44315 * 0b1..EXTAL muxed into HCKR input.
44316 */
44317#define ESAI_ECR_ERI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ERI_SHIFT)) & ESAI_ECR_ERI_MASK)
44318#define ESAI_ECR_ETO_MASK (0x40000U)
44319#define ESAI_ECR_ETO_SHIFT (18U)
44320/*! ETO - ETO
44321 * 0b0..HCKT pin has normal function.
44322 * 0b1..EXTAL driven onto HCKT pin.
44323 */
44324#define ESAI_ECR_ETO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ETO_SHIFT)) & ESAI_ECR_ETO_MASK)
44325#define ESAI_ECR_ETI_MASK (0x80000U)
44326#define ESAI_ECR_ETI_SHIFT (19U)
44327/*! ETI - ETI
44328 * 0b0..HCKT pin has normal function.
44329 * 0b1..EXTAL muxed into HCKT input.
44330 */
44331#define ESAI_ECR_ETI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ECR_ETI_SHIFT)) & ESAI_ECR_ETI_MASK)
44332/*! @} */
44333
44334/*! @name ESR - ESAI Status Register */
44335/*! @{ */
44336#define ESAI_ESR_RD_MASK (0x1U)
44337#define ESAI_ESR_RD_SHIFT (0U)
44338/*! RD - RD
44339 * 0b0..RD is not the highest priority active interrupt.
44340 * 0b1..RD is the highest priority active interrupt.
44341 */
44342#define ESAI_ESR_RD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RD_SHIFT)) & ESAI_ESR_RD_MASK)
44343#define ESAI_ESR_RED_MASK (0x2U)
44344#define ESAI_ESR_RED_SHIFT (1U)
44345/*! RED - RED
44346 * 0b0..RED is not the highest priority active interrupt.
44347 * 0b1..RED is the highest priority active interrupt.
44348 */
44349#define ESAI_ESR_RED(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RED_SHIFT)) & ESAI_ESR_RED_MASK)
44350#define ESAI_ESR_RDE_MASK (0x4U)
44351#define ESAI_ESR_RDE_SHIFT (2U)
44352/*! RDE - RDE
44353 * 0b0..RDE is not the highest priority active interrupt.
44354 * 0b1..RDE is the highest priority active interrupt.
44355 */
44356#define ESAI_ESR_RDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RDE_SHIFT)) & ESAI_ESR_RDE_MASK)
44357#define ESAI_ESR_RLS_MASK (0x8U)
44358#define ESAI_ESR_RLS_SHIFT (3U)
44359/*! RLS - RLS
44360 * 0b0..RLS is not the highest priority active interrupt.
44361 * 0b1..RLS is the highest priority active interrupt.
44362 */
44363#define ESAI_ESR_RLS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RLS_SHIFT)) & ESAI_ESR_RLS_MASK)
44364#define ESAI_ESR_TD_MASK (0x10U)
44365#define ESAI_ESR_TD_SHIFT (4U)
44366/*! TD - TD
44367 * 0b0..TD is not the highest priority active interrupt.
44368 * 0b1..TD is the highest priority active interrupt.
44369 */
44370#define ESAI_ESR_TD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TD_SHIFT)) & ESAI_ESR_TD_MASK)
44371#define ESAI_ESR_TED_MASK (0x20U)
44372#define ESAI_ESR_TED_SHIFT (5U)
44373/*! TED - TED
44374 * 0b0..TED is not the highest priority active interrupt.
44375 * 0b1..TED is the highest priority active interrupt.
44376 */
44377#define ESAI_ESR_TED(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TED_SHIFT)) & ESAI_ESR_TED_MASK)
44378#define ESAI_ESR_TDE_MASK (0x40U)
44379#define ESAI_ESR_TDE_SHIFT (6U)
44380/*! TDE - TDE
44381 * 0b0..TDE is not the highest priority active interrupt.
44382 * 0b1..TDE is the highest priority active interrupt.
44383 */
44384#define ESAI_ESR_TDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TDE_SHIFT)) & ESAI_ESR_TDE_MASK)
44385#define ESAI_ESR_TLS_MASK (0x80U)
44386#define ESAI_ESR_TLS_SHIFT (7U)
44387/*! TLS - TLS
44388 * 0b0..TLS is not the highest priority active interrupt.
44389 * 0b1..TLS is the highest priority active interrupt.
44390 */
44391#define ESAI_ESR_TLS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TLS_SHIFT)) & ESAI_ESR_TLS_MASK)
44392#define ESAI_ESR_TFE_MASK (0x100U)
44393#define ESAI_ESR_TFE_SHIFT (8U)
44394/*! TFE - TFE
44395 * 0b0..Number of empty slots in Transmit FIFO less than Transmit FIFO watermark.
44396 * 0b1..Number of empty slots in Transmit FIFO is equal to or greater than Transmit FIFO watermark.
44397 */
44398#define ESAI_ESR_TFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TFE_SHIFT)) & ESAI_ESR_TFE_MASK)
44399#define ESAI_ESR_RFF_MASK (0x200U)
44400#define ESAI_ESR_RFF_SHIFT (9U)
44401/*! RFF - RFF
44402 * 0b0..Number of words in Receive FIFO less than Receive FIFO watermark.
44403 * 0b1..Number of words in Receive FIFO is equal to or greater than Receive FIFO watermark.
44404 */
44405#define ESAI_ESR_RFF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_RFF_SHIFT)) & ESAI_ESR_RFF_MASK)
44406#define ESAI_ESR_TINIT_MASK (0x400U)
44407#define ESAI_ESR_TINIT_SHIFT (10U)
44408/*! TINIT - TINIT
44409 * 0b0..Transmitter has finished initializing the Transmit Data Registers (or Transmit FIFO is not enabled or
44410 * Transmit Initialization is not enabled).
44411 * 0b1..Transmitter has not finished initializing the Transmit Data Registers.
44412 */
44413#define ESAI_ESR_TINIT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_ESR_TINIT_SHIFT)) & ESAI_ESR_TINIT_MASK)
44414/*! @} */
44415
44416/*! @name TFCR - Transmit FIFO Configuration Register */
44417/*! @{ */
44418#define ESAI_TFCR_TFE_MASK (0x1U)
44419#define ESAI_TFCR_TFE_SHIFT (0U)
44420/*! TFE - TFE
44421 * 0b0..Transmit FIFO disabled.
44422 * 0b1..Transmit FIFO enabled.
44423 */
44424#define ESAI_TFCR_TFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFE_SHIFT)) & ESAI_TFCR_TFE_MASK)
44425#define ESAI_TFCR_TFR_MASK (0x2U)
44426#define ESAI_TFCR_TFR_SHIFT (1U)
44427/*! TFR - TFR
44428 * 0b0..Transmit FIFO not reset.
44429 * 0b1..Transmit FIFO reset.
44430 */
44431#define ESAI_TFCR_TFR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFR_SHIFT)) & ESAI_TFCR_TFR_MASK)
44432#define ESAI_TFCR_TE0_MASK (0x4U)
44433#define ESAI_TFCR_TE0_SHIFT (2U)
44434/*! TE0 - TE0
44435 * 0b0..Transmitter #0 is not using the Transmit FIFO.
44436 * 0b1..Transmitter #0 is using the Transmit FIFO.
44437 */
44438#define ESAI_TFCR_TE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE0_SHIFT)) & ESAI_TFCR_TE0_MASK)
44439#define ESAI_TFCR_TE1_MASK (0x8U)
44440#define ESAI_TFCR_TE1_SHIFT (3U)
44441/*! TE1 - TE1
44442 * 0b0..Transmitter #1 is not using the Transmit FIFO.
44443 * 0b1..Transmitter #1 is using the Transmit FIFO.
44444 */
44445#define ESAI_TFCR_TE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE1_SHIFT)) & ESAI_TFCR_TE1_MASK)
44446#define ESAI_TFCR_TE2_MASK (0x10U)
44447#define ESAI_TFCR_TE2_SHIFT (4U)
44448/*! TE2 - TE2
44449 * 0b0..Transmitter #2 is not using the Transmit FIFO.
44450 * 0b1..Transmitter #2 is using the Transmit FIFO.
44451 */
44452#define ESAI_TFCR_TE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE2_SHIFT)) & ESAI_TFCR_TE2_MASK)
44453#define ESAI_TFCR_TE3_MASK (0x20U)
44454#define ESAI_TFCR_TE3_SHIFT (5U)
44455/*! TE3 - TE3
44456 * 0b0..Transmitter #3 is not using the Transmit FIFO.
44457 * 0b1..Transmitter #3 is using the Transmit FIFO.
44458 */
44459#define ESAI_TFCR_TE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE3_SHIFT)) & ESAI_TFCR_TE3_MASK)
44460#define ESAI_TFCR_TE4_MASK (0x40U)
44461#define ESAI_TFCR_TE4_SHIFT (6U)
44462/*! TE4 - TE4
44463 * 0b0..Transmitter #4 is not using the Transmit FIFO.
44464 * 0b1..Transmitter #4 is using the Transmit FIFO.
44465 */
44466#define ESAI_TFCR_TE4(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE4_SHIFT)) & ESAI_TFCR_TE4_MASK)
44467#define ESAI_TFCR_TE5_MASK (0x80U)
44468#define ESAI_TFCR_TE5_SHIFT (7U)
44469/*! TE5 - TE5
44470 * 0b0..Transmitter #5 is not using the Transmit FIFO.
44471 * 0b1..Transmitter #5 is using the Transmit FIFO.
44472 */
44473#define ESAI_TFCR_TE5(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TE5_SHIFT)) & ESAI_TFCR_TE5_MASK)
44474#define ESAI_TFCR_TFWM_MASK (0xFF00U)
44475#define ESAI_TFCR_TFWM_SHIFT (8U)
44476/*! TFWM - TFWM
44477 */
44478#define ESAI_TFCR_TFWM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TFWM_SHIFT)) & ESAI_TFCR_TFWM_MASK)
44479#define ESAI_TFCR_TWA_MASK (0x70000U)
44480#define ESAI_TFCR_TWA_SHIFT (16U)
44481/*! TWA - TWA
44482 * 0b000..MSB of data is bit 31. Data bits 7-0 are ignored when passed to transmit shift register.
44483 * 0b001..MSB of data is bit 27. Data bits 3-0 are ignored when passed to transmit shift register.
44484 * 0b010..MSB of data is bit 23.
44485 * 0b011..MSB of data is bit 19. Bottom 4 bits of transmit shift register are zeroed.
44486 * 0b100..MSB of data is bit 15. Bottom 8 bits of transmit shift register are zeroed.
44487 * 0b101..MSB of data is bit 11. Bottom 12 bits of transmit shift register are zeroed.
44488 * 0b110..MSB of data is bit 7. Bottom 16 bits of transmit shift register are zeroed.
44489 * 0b111..MSB of data is bit 3. Bottom 20 bits of transmit shift register are zeroed.
44490 */
44491#define ESAI_TFCR_TWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TWA_SHIFT)) & ESAI_TFCR_TWA_MASK)
44492#define ESAI_TFCR_TIEN_MASK (0x80000U)
44493#define ESAI_TFCR_TIEN_SHIFT (19U)
44494/*! TIEN - TIEN
44495 * 0b0..Transmit Data Registers are not initialized from the FIFO once the Transmit FIFO is enabled. Software
44496 * must manually initialize the Transmit Data Registers separately.
44497 * 0b1..Transmit Data Registers are initialized from the FIFO once the Transmit FIFO is enabled.
44498 */
44499#define ESAI_TFCR_TIEN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFCR_TIEN_SHIFT)) & ESAI_TFCR_TIEN_MASK)
44500/*! @} */
44501
44502/*! @name TFSR - Transmit FIFO Status Register */
44503/*! @{ */
44504#define ESAI_TFSR_TFCNT_MASK (0xFFU)
44505#define ESAI_TFSR_TFCNT_SHIFT (0U)
44506/*! TFCNT - TFCNT
44507 */
44508#define ESAI_TFSR_TFCNT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_TFCNT_SHIFT)) & ESAI_TFSR_TFCNT_MASK)
44509#define ESAI_TFSR_NTFI_MASK (0x700U)
44510#define ESAI_TFSR_NTFI_SHIFT (8U)
44511/*! NTFI - NTFI
44512 * 0b000..Transmitter #0 receives next word written to the Transmit FIFO.
44513 * 0b001..Transmitter #1 receives next word written to the Transmit FIFO.
44514 * 0b010..Transmitter #2 receives next word written to the Transmit FIFO.
44515 * 0b011..Transmitter #3 receives next word written to the Transmit FIFO.
44516 * 0b100..Transmitter #4 receives next word written to the Transmit FIFO.
44517 * 0b101..Transmitter #5 receives next word written to the Transmit FIFO.
44518 * 0b110..Reserved.
44519 * 0b111..Reserved.
44520 */
44521#define ESAI_TFSR_NTFI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_NTFI_SHIFT)) & ESAI_TFSR_NTFI_MASK)
44522#define ESAI_TFSR_NTFO_MASK (0x7000U)
44523#define ESAI_TFSR_NTFO_SHIFT (12U)
44524/*! NTFO - NTFO
44525 * 0b000..Transmitter #0 receives next word from the Transmit FIFO.
44526 * 0b001..Transmitter #1 receives next word from the Transmit FIFO.
44527 * 0b010..Transmitter #2 receives next word from the Transmit FIFO.
44528 * 0b011..Transmitter #3 receives next word from the Transmit FIFO.
44529 * 0b100..Transmitter #4 receives next word from the Transmit FIFO.
44530 * 0b101..Transmitter #5 receives next word from the Transmit FIFO.
44531 * 0b110..Reserved.
44532 * 0b111..Reserved.
44533 */
44534#define ESAI_TFSR_NTFO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TFSR_NTFO_SHIFT)) & ESAI_TFSR_NTFO_MASK)
44535/*! @} */
44536
44537/*! @name RFCR - Receive FIFO Configuration Register */
44538/*! @{ */
44539#define ESAI_RFCR_RFE_MASK (0x1U)
44540#define ESAI_RFCR_RFE_SHIFT (0U)
44541/*! RFE - RFE
44542 * 0b0..Receive FIFO disabled.
44543 * 0b1..Receive FIFO enabled.
44544 */
44545#define ESAI_RFCR_RFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFE_SHIFT)) & ESAI_RFCR_RFE_MASK)
44546#define ESAI_RFCR_RFR_MASK (0x2U)
44547#define ESAI_RFCR_RFR_SHIFT (1U)
44548/*! RFR - RFR
44549 * 0b0..Receive FIFO not reset.
44550 * 0b1..Receive FIFO reset.
44551 */
44552#define ESAI_RFCR_RFR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFR_SHIFT)) & ESAI_RFCR_RFR_MASK)
44553#define ESAI_RFCR_RE0_MASK (0x4U)
44554#define ESAI_RFCR_RE0_SHIFT (2U)
44555/*! RE0 - RE0
44556 * 0b0..Receiver #0 is not using the Receive FIFO.
44557 * 0b1..Receiver #0 is using the Receive FIFO.
44558 */
44559#define ESAI_RFCR_RE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE0_SHIFT)) & ESAI_RFCR_RE0_MASK)
44560#define ESAI_RFCR_RE1_MASK (0x8U)
44561#define ESAI_RFCR_RE1_SHIFT (3U)
44562/*! RE1 - RE1
44563 * 0b0..Receiver #1 is not using the Receive FIFO.
44564 * 0b1..Receiver #1 is using the Receive FIFO.
44565 */
44566#define ESAI_RFCR_RE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE1_SHIFT)) & ESAI_RFCR_RE1_MASK)
44567#define ESAI_RFCR_RE2_MASK (0x10U)
44568#define ESAI_RFCR_RE2_SHIFT (4U)
44569/*! RE2 - RE2
44570 * 0b0..Receiver #2 is not using the Receive FIFO.
44571 * 0b1..Receiver #2 is using the Receive FIFO.
44572 */
44573#define ESAI_RFCR_RE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE2_SHIFT)) & ESAI_RFCR_RE2_MASK)
44574#define ESAI_RFCR_RE3_MASK (0x20U)
44575#define ESAI_RFCR_RE3_SHIFT (5U)
44576/*! RE3 - RE3
44577 * 0b0..Receiver #3 is not using the Receive FIFO.
44578 * 0b1..Receiver #3 is using the Receive FIFO.
44579 */
44580#define ESAI_RFCR_RE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RE3_SHIFT)) & ESAI_RFCR_RE3_MASK)
44581#define ESAI_RFCR_RFWM_MASK (0xFF00U)
44582#define ESAI_RFCR_RFWM_SHIFT (8U)
44583/*! RFWM - RFWM
44584 */
44585#define ESAI_RFCR_RFWM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RFWM_SHIFT)) & ESAI_RFCR_RFWM_MASK)
44586#define ESAI_RFCR_RWA_MASK (0x70000U)
44587#define ESAI_RFCR_RWA_SHIFT (16U)
44588/*! RWA - RWA
44589 * 0b000..MSB of data is at bit 31. Data bits 7-0 are zeroed.
44590 * 0b001..MSB of data is at bit 27. Data bits 3-0 are zeroed.
44591 * 0b010..MSB of data is at bit 23.
44592 * 0b011..MSB of data is at bit 19. Data bits 3-0 from receive shift register are ignored.
44593 * 0b100..MSB of data is at bit 15. Data bits 7-0 from receive shift register are ignored.
44594 * 0b101..MSB of data is at bit 11. Data bits 11-0 from receive shift register are ignored.
44595 * 0b110..MSB of data is at bit 7. Data bits 15-0 from receive shift register are ignored.
44596 * 0b111..MSB of data is at bit 3. Data bits 19-0 from receive shift register are ignored.
44597 */
44598#define ESAI_RFCR_RWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_RWA_SHIFT)) & ESAI_RFCR_RWA_MASK)
44599#define ESAI_RFCR_REXT_MASK (0x80000U)
44600#define ESAI_RFCR_REXT_SHIFT (19U)
44601/*! REXT - REXT
44602 * 0b0..Receive data is zero extended.
44603 * 0b1..Receive data is sign extended.
44604 */
44605#define ESAI_RFCR_REXT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFCR_REXT_SHIFT)) & ESAI_RFCR_REXT_MASK)
44606/*! @} */
44607
44608/*! @name RFSR - Receive FIFO Status Register */
44609/*! @{ */
44610#define ESAI_RFSR_RFCNT_MASK (0xFFU)
44611#define ESAI_RFSR_RFCNT_SHIFT (0U)
44612/*! RFCNT - RFCNT
44613 */
44614#define ESAI_RFSR_RFCNT(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_RFCNT_SHIFT)) & ESAI_RFSR_RFCNT_MASK)
44615#define ESAI_RFSR_NRFO_MASK (0x300U)
44616#define ESAI_RFSR_NRFO_SHIFT (8U)
44617/*! NRFO - NRFO
44618 * 0b00..Receiver #0 returns next word from the Receive FIFO.
44619 * 0b01..Receiver #1 returns next word from the Receive FIFO.
44620 * 0b10..Receiver #2 returns next word from the Receive FIFO.
44621 * 0b11..Receiver #3 returns next word from the Receive FIFO.
44622 */
44623#define ESAI_RFSR_NRFO(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_NRFO_SHIFT)) & ESAI_RFSR_NRFO_MASK)
44624#define ESAI_RFSR_NRFI_MASK (0x3000U)
44625#define ESAI_RFSR_NRFI_SHIFT (12U)
44626/*! NRFI - NRFI
44627 * 0b00..Receiver #0 returns next word to the Receive FIFO.
44628 * 0b01..Receiver #1 returns next word to the Receive FIFO.
44629 * 0b10..Receiver #2 returns next word to the Receive FIFO.
44630 * 0b11..Receiver #3 returns next word to the Receive FIFO.
44631 */
44632#define ESAI_RFSR_NRFI(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RFSR_NRFI_SHIFT)) & ESAI_RFSR_NRFI_MASK)
44633/*! @} */
44634
44635/*! @name TX - Transmit Data Register n */
44636/*! @{ */
44637#define ESAI_TX_TXn_MASK (0xFFFFFFU)
44638#define ESAI_TX_TXn_SHIFT (0U)
44639/*! TXn - TXn
44640 */
44641#define ESAI_TX_TXn(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TX_TXn_SHIFT)) & ESAI_TX_TXn_MASK)
44642/*! @} */
44643
44644/* The count of ESAI_TX */
44645#define ESAI_TX_COUNT (6U)
44646
44647/*! @name TSR - ESAI Transmit Slot Register */
44648/*! @{ */
44649#define ESAI_TSR_TSR_MASK (0xFFFFFFU)
44650#define ESAI_TSR_TSR_SHIFT (0U)
44651/*! TSR - TSR
44652 */
44653#define ESAI_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TSR_TSR_SHIFT)) & ESAI_TSR_TSR_MASK)
44654/*! @} */
44655
44656/*! @name RX - Receive Data Register n */
44657/*! @{ */
44658#define ESAI_RX_RXn_MASK (0xFFFFFFU)
44659#define ESAI_RX_RXn_SHIFT (0U)
44660/*! RXn - RXn
44661 */
44662#define ESAI_RX_RXn(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RX_RXn_SHIFT)) & ESAI_RX_RXn_MASK)
44663/*! @} */
44664
44665/* The count of ESAI_RX */
44666#define ESAI_RX_COUNT (4U)
44667
44668/*! @name SAISR - Serial Audio Interface Status Register */
44669/*! @{ */
44670#define ESAI_SAISR_IF0_MASK (0x1U)
44671#define ESAI_SAISR_IF0_SHIFT (0U)
44672/*! IF0 - IF0
44673 */
44674#define ESAI_SAISR_IF0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF0_SHIFT)) & ESAI_SAISR_IF0_MASK)
44675#define ESAI_SAISR_IF1_MASK (0x2U)
44676#define ESAI_SAISR_IF1_SHIFT (1U)
44677/*! IF1 - IF1
44678 */
44679#define ESAI_SAISR_IF1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF1_SHIFT)) & ESAI_SAISR_IF1_MASK)
44680#define ESAI_SAISR_IF2_MASK (0x4U)
44681#define ESAI_SAISR_IF2_SHIFT (2U)
44682/*! IF2 - IF2
44683 */
44684#define ESAI_SAISR_IF2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_IF2_SHIFT)) & ESAI_SAISR_IF2_MASK)
44685#define ESAI_SAISR_RFS_MASK (0x40U)
44686#define ESAI_SAISR_RFS_SHIFT (6U)
44687/*! RFS - RFS
44688 */
44689#define ESAI_SAISR_RFS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RFS_SHIFT)) & ESAI_SAISR_RFS_MASK)
44690#define ESAI_SAISR_ROE_MASK (0x80U)
44691#define ESAI_SAISR_ROE_SHIFT (7U)
44692/*! ROE - ROE
44693 */
44694#define ESAI_SAISR_ROE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_ROE_SHIFT)) & ESAI_SAISR_ROE_MASK)
44695#define ESAI_SAISR_RDF_MASK (0x100U)
44696#define ESAI_SAISR_RDF_SHIFT (8U)
44697/*! RDF - RDF
44698 */
44699#define ESAI_SAISR_RDF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RDF_SHIFT)) & ESAI_SAISR_RDF_MASK)
44700#define ESAI_SAISR_REDF_MASK (0x200U)
44701#define ESAI_SAISR_REDF_SHIFT (9U)
44702/*! REDF - REDF
44703 */
44704#define ESAI_SAISR_REDF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_REDF_SHIFT)) & ESAI_SAISR_REDF_MASK)
44705#define ESAI_SAISR_RODF_MASK (0x400U)
44706#define ESAI_SAISR_RODF_SHIFT (10U)
44707/*! RODF - RODF
44708 */
44709#define ESAI_SAISR_RODF(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_RODF_SHIFT)) & ESAI_SAISR_RODF_MASK)
44710#define ESAI_SAISR_TFS_MASK (0x2000U)
44711#define ESAI_SAISR_TFS_SHIFT (13U)
44712/*! TFS - TFS
44713 */
44714#define ESAI_SAISR_TFS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TFS_SHIFT)) & ESAI_SAISR_TFS_MASK)
44715#define ESAI_SAISR_TUE_MASK (0x4000U)
44716#define ESAI_SAISR_TUE_SHIFT (14U)
44717/*! TUE - TUE
44718 */
44719#define ESAI_SAISR_TUE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TUE_SHIFT)) & ESAI_SAISR_TUE_MASK)
44720#define ESAI_SAISR_TDE_MASK (0x8000U)
44721#define ESAI_SAISR_TDE_SHIFT (15U)
44722/*! TDE - TDE
44723 */
44724#define ESAI_SAISR_TDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TDE_SHIFT)) & ESAI_SAISR_TDE_MASK)
44725#define ESAI_SAISR_TEDE_MASK (0x10000U)
44726#define ESAI_SAISR_TEDE_SHIFT (16U)
44727/*! TEDE - TEDE
44728 */
44729#define ESAI_SAISR_TEDE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TEDE_SHIFT)) & ESAI_SAISR_TEDE_MASK)
44730#define ESAI_SAISR_TODFE_MASK (0x20000U)
44731#define ESAI_SAISR_TODFE_SHIFT (17U)
44732/*! TODFE - TODFE
44733 */
44734#define ESAI_SAISR_TODFE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAISR_TODFE_SHIFT)) & ESAI_SAISR_TODFE_MASK)
44735/*! @} */
44736
44737/*! @name SAICR - Serial Audio Interface Control Register */
44738/*! @{ */
44739#define ESAI_SAICR_OF0_MASK (0x1U)
44740#define ESAI_SAICR_OF0_SHIFT (0U)
44741/*! OF0 - OF0
44742 */
44743#define ESAI_SAICR_OF0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF0_SHIFT)) & ESAI_SAICR_OF0_MASK)
44744#define ESAI_SAICR_OF1_MASK (0x2U)
44745#define ESAI_SAICR_OF1_SHIFT (1U)
44746/*! OF1 - OF1
44747 */
44748#define ESAI_SAICR_OF1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF1_SHIFT)) & ESAI_SAICR_OF1_MASK)
44749#define ESAI_SAICR_OF2_MASK (0x4U)
44750#define ESAI_SAICR_OF2_SHIFT (2U)
44751/*! OF2 - OF2
44752 */
44753#define ESAI_SAICR_OF2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_OF2_SHIFT)) & ESAI_SAICR_OF2_MASK)
44754#define ESAI_SAICR_SYN_MASK (0x40U)
44755#define ESAI_SAICR_SYN_SHIFT (6U)
44756/*! SYN - SYN
44757 */
44758#define ESAI_SAICR_SYN(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_SYN_SHIFT)) & ESAI_SAICR_SYN_MASK)
44759#define ESAI_SAICR_TEBE_MASK (0x80U)
44760#define ESAI_SAICR_TEBE_SHIFT (7U)
44761/*! TEBE - TEBE
44762 */
44763#define ESAI_SAICR_TEBE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_TEBE_SHIFT)) & ESAI_SAICR_TEBE_MASK)
44764#define ESAI_SAICR_ALC_MASK (0x100U)
44765#define ESAI_SAICR_ALC_SHIFT (8U)
44766/*! ALC - ALC
44767 */
44768#define ESAI_SAICR_ALC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_SAICR_ALC_SHIFT)) & ESAI_SAICR_ALC_MASK)
44769/*! @} */
44770
44771/*! @name TCR - Transmit Control Register */
44772/*! @{ */
44773#define ESAI_TCR_TE0_MASK (0x1U)
44774#define ESAI_TCR_TE0_SHIFT (0U)
44775/*! TE0 - TE0
44776 */
44777#define ESAI_TCR_TE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE0_SHIFT)) & ESAI_TCR_TE0_MASK)
44778#define ESAI_TCR_TE1_MASK (0x2U)
44779#define ESAI_TCR_TE1_SHIFT (1U)
44780/*! TE1 - TE1
44781 */
44782#define ESAI_TCR_TE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE1_SHIFT)) & ESAI_TCR_TE1_MASK)
44783#define ESAI_TCR_TE2_MASK (0x4U)
44784#define ESAI_TCR_TE2_SHIFT (2U)
44785/*! TE2 - TE2
44786 */
44787#define ESAI_TCR_TE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE2_SHIFT)) & ESAI_TCR_TE2_MASK)
44788#define ESAI_TCR_TE3_MASK (0x8U)
44789#define ESAI_TCR_TE3_SHIFT (3U)
44790/*! TE3 - TE3
44791 */
44792#define ESAI_TCR_TE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE3_SHIFT)) & ESAI_TCR_TE3_MASK)
44793#define ESAI_TCR_TE4_MASK (0x10U)
44794#define ESAI_TCR_TE4_SHIFT (4U)
44795/*! TE4 - TE4
44796 */
44797#define ESAI_TCR_TE4(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE4_SHIFT)) & ESAI_TCR_TE4_MASK)
44798#define ESAI_TCR_TE5_MASK (0x20U)
44799#define ESAI_TCR_TE5_SHIFT (5U)
44800/*! TE5 - TE5
44801 */
44802#define ESAI_TCR_TE5(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TE5_SHIFT)) & ESAI_TCR_TE5_MASK)
44803#define ESAI_TCR_TSHFD_MASK (0x40U)
44804#define ESAI_TCR_TSHFD_SHIFT (6U)
44805/*! TSHFD - TSHFD
44806 */
44807#define ESAI_TCR_TSHFD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TSHFD_SHIFT)) & ESAI_TCR_TSHFD_MASK)
44808#define ESAI_TCR_TWA_MASK (0x80U)
44809#define ESAI_TCR_TWA_SHIFT (7U)
44810/*! TWA - TWA
44811 */
44812#define ESAI_TCR_TWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TWA_SHIFT)) & ESAI_TCR_TWA_MASK)
44813#define ESAI_TCR_TMOD_MASK (0x300U)
44814#define ESAI_TCR_TMOD_SHIFT (8U)
44815/*! TMOD - TMOD
44816 */
44817#define ESAI_TCR_TMOD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TMOD_SHIFT)) & ESAI_TCR_TMOD_MASK)
44818#define ESAI_TCR_TSWS_MASK (0x7C00U)
44819#define ESAI_TCR_TSWS_SHIFT (10U)
44820/*! TSWS - TSWS
44821 */
44822#define ESAI_TCR_TSWS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TSWS_SHIFT)) & ESAI_TCR_TSWS_MASK)
44823#define ESAI_TCR_TFSL_MASK (0x8000U)
44824#define ESAI_TCR_TFSL_SHIFT (15U)
44825/*! TFSL - TFSL
44826 */
44827#define ESAI_TCR_TFSL(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TFSL_SHIFT)) & ESAI_TCR_TFSL_MASK)
44828#define ESAI_TCR_TFSR_MASK (0x10000U)
44829#define ESAI_TCR_TFSR_SHIFT (16U)
44830/*! TFSR - TFSR
44831 */
44832#define ESAI_TCR_TFSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TFSR_SHIFT)) & ESAI_TCR_TFSR_MASK)
44833#define ESAI_TCR_PADC_MASK (0x20000U)
44834#define ESAI_TCR_PADC_SHIFT (17U)
44835/*! PADC - PADC
44836 */
44837#define ESAI_TCR_PADC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_PADC_SHIFT)) & ESAI_TCR_PADC_MASK)
44838#define ESAI_TCR_TPR_MASK (0x80000U)
44839#define ESAI_TCR_TPR_SHIFT (19U)
44840/*! TPR - TPR
44841 */
44842#define ESAI_TCR_TPR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TPR_SHIFT)) & ESAI_TCR_TPR_MASK)
44843#define ESAI_TCR_TEIE_MASK (0x100000U)
44844#define ESAI_TCR_TEIE_SHIFT (20U)
44845/*! TEIE - TEIE
44846 */
44847#define ESAI_TCR_TEIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TEIE_SHIFT)) & ESAI_TCR_TEIE_MASK)
44848#define ESAI_TCR_TEDIE_MASK (0x200000U)
44849#define ESAI_TCR_TEDIE_SHIFT (21U)
44850/*! TEDIE - TEDIE
44851 */
44852#define ESAI_TCR_TEDIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TEDIE_SHIFT)) & ESAI_TCR_TEDIE_MASK)
44853#define ESAI_TCR_TIE_MASK (0x400000U)
44854#define ESAI_TCR_TIE_SHIFT (22U)
44855/*! TIE - TIE
44856 */
44857#define ESAI_TCR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TIE_SHIFT)) & ESAI_TCR_TIE_MASK)
44858#define ESAI_TCR_TLIE_MASK (0x800000U)
44859#define ESAI_TCR_TLIE_SHIFT (23U)
44860/*! TLIE - TLIE
44861 */
44862#define ESAI_TCR_TLIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCR_TLIE_SHIFT)) & ESAI_TCR_TLIE_MASK)
44863/*! @} */
44864
44865/*! @name TCCR - Transmit Clock Control Register */
44866/*! @{ */
44867#define ESAI_TCCR_TPM_MASK (0xFFU)
44868#define ESAI_TCCR_TPM_SHIFT (0U)
44869/*! TPM - TPM
44870 */
44871#define ESAI_TCCR_TPM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TPM_SHIFT)) & ESAI_TCCR_TPM_MASK)
44872#define ESAI_TCCR_TPSR_MASK (0x100U)
44873#define ESAI_TCCR_TPSR_SHIFT (8U)
44874/*! TPSR - TPSR
44875 */
44876#define ESAI_TCCR_TPSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TPSR_SHIFT)) & ESAI_TCCR_TPSR_MASK)
44877#define ESAI_TCCR_TDC_MASK (0x3E00U)
44878#define ESAI_TCCR_TDC_SHIFT (9U)
44879/*! TDC - TDC
44880 */
44881#define ESAI_TCCR_TDC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TDC_SHIFT)) & ESAI_TCCR_TDC_MASK)
44882#define ESAI_TCCR_TFP_MASK (0x3C000U)
44883#define ESAI_TCCR_TFP_SHIFT (14U)
44884/*! TFP - TFP
44885 */
44886#define ESAI_TCCR_TFP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFP_SHIFT)) & ESAI_TCCR_TFP_MASK)
44887#define ESAI_TCCR_TCKP_MASK (0x40000U)
44888#define ESAI_TCCR_TCKP_SHIFT (18U)
44889/*! TCKP - TCKP
44890 */
44891#define ESAI_TCCR_TCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TCKP_SHIFT)) & ESAI_TCCR_TCKP_MASK)
44892#define ESAI_TCCR_TFSP_MASK (0x80000U)
44893#define ESAI_TCCR_TFSP_SHIFT (19U)
44894/*! TFSP - TFSP
44895 */
44896#define ESAI_TCCR_TFSP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFSP_SHIFT)) & ESAI_TCCR_TFSP_MASK)
44897#define ESAI_TCCR_THCKP_MASK (0x100000U)
44898#define ESAI_TCCR_THCKP_SHIFT (20U)
44899/*! THCKP - THCKP
44900 */
44901#define ESAI_TCCR_THCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_THCKP_SHIFT)) & ESAI_TCCR_THCKP_MASK)
44902#define ESAI_TCCR_TCKD_MASK (0x200000U)
44903#define ESAI_TCCR_TCKD_SHIFT (21U)
44904/*! TCKD - TCKD
44905 */
44906#define ESAI_TCCR_TCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TCKD_SHIFT)) & ESAI_TCCR_TCKD_MASK)
44907#define ESAI_TCCR_TFSD_MASK (0x400000U)
44908#define ESAI_TCCR_TFSD_SHIFT (22U)
44909/*! TFSD - TFSD
44910 */
44911#define ESAI_TCCR_TFSD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_TFSD_SHIFT)) & ESAI_TCCR_TFSD_MASK)
44912#define ESAI_TCCR_THCKD_MASK (0x800000U)
44913#define ESAI_TCCR_THCKD_SHIFT (23U)
44914/*! THCKD - THCKD
44915 */
44916#define ESAI_TCCR_THCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TCCR_THCKD_SHIFT)) & ESAI_TCCR_THCKD_MASK)
44917/*! @} */
44918
44919/*! @name RCR - Receive Control Register */
44920/*! @{ */
44921#define ESAI_RCR_RE0_MASK (0x1U)
44922#define ESAI_RCR_RE0_SHIFT (0U)
44923/*! RE0 - RE0
44924 */
44925#define ESAI_RCR_RE0(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE0_SHIFT)) & ESAI_RCR_RE0_MASK)
44926#define ESAI_RCR_RE1_MASK (0x2U)
44927#define ESAI_RCR_RE1_SHIFT (1U)
44928/*! RE1 - RE1
44929 */
44930#define ESAI_RCR_RE1(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE1_SHIFT)) & ESAI_RCR_RE1_MASK)
44931#define ESAI_RCR_RE2_MASK (0x4U)
44932#define ESAI_RCR_RE2_SHIFT (2U)
44933/*! RE2 - RE2
44934 */
44935#define ESAI_RCR_RE2(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE2_SHIFT)) & ESAI_RCR_RE2_MASK)
44936#define ESAI_RCR_RE3_MASK (0x8U)
44937#define ESAI_RCR_RE3_SHIFT (3U)
44938/*! RE3 - RE3
44939 */
44940#define ESAI_RCR_RE3(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RE3_SHIFT)) & ESAI_RCR_RE3_MASK)
44941#define ESAI_RCR_RSHFD_MASK (0x40U)
44942#define ESAI_RCR_RSHFD_SHIFT (6U)
44943/*! RSHFD - RSHFD
44944 */
44945#define ESAI_RCR_RSHFD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RSHFD_SHIFT)) & ESAI_RCR_RSHFD_MASK)
44946#define ESAI_RCR_RWA_MASK (0x80U)
44947#define ESAI_RCR_RWA_SHIFT (7U)
44948/*! RWA - RWA
44949 */
44950#define ESAI_RCR_RWA(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RWA_SHIFT)) & ESAI_RCR_RWA_MASK)
44951#define ESAI_RCR_RMOD_MASK (0x300U)
44952#define ESAI_RCR_RMOD_SHIFT (8U)
44953/*! RMOD - RMOD
44954 */
44955#define ESAI_RCR_RMOD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RMOD_SHIFT)) & ESAI_RCR_RMOD_MASK)
44956#define ESAI_RCR_RSWS_MASK (0x7C00U)
44957#define ESAI_RCR_RSWS_SHIFT (10U)
44958/*! RSWS - RSWS
44959 */
44960#define ESAI_RCR_RSWS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RSWS_SHIFT)) & ESAI_RCR_RSWS_MASK)
44961#define ESAI_RCR_RFSL_MASK (0x8000U)
44962#define ESAI_RCR_RFSL_SHIFT (15U)
44963/*! RFSL - RFSL
44964 */
44965#define ESAI_RCR_RFSL(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RFSL_SHIFT)) & ESAI_RCR_RFSL_MASK)
44966#define ESAI_RCR_RFSR_MASK (0x10000U)
44967#define ESAI_RCR_RFSR_SHIFT (16U)
44968/*! RFSR - RFSR
44969 */
44970#define ESAI_RCR_RFSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RFSR_SHIFT)) & ESAI_RCR_RFSR_MASK)
44971#define ESAI_RCR_RPR_MASK (0x80000U)
44972#define ESAI_RCR_RPR_SHIFT (19U)
44973/*! RPR - RPR
44974 */
44975#define ESAI_RCR_RPR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RPR_SHIFT)) & ESAI_RCR_RPR_MASK)
44976#define ESAI_RCR_REIE_MASK (0x100000U)
44977#define ESAI_RCR_REIE_SHIFT (20U)
44978/*! REIE - REIE
44979 */
44980#define ESAI_RCR_REIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_REIE_SHIFT)) & ESAI_RCR_REIE_MASK)
44981#define ESAI_RCR_REDIE_MASK (0x200000U)
44982#define ESAI_RCR_REDIE_SHIFT (21U)
44983/*! REDIE - REDIE
44984 */
44985#define ESAI_RCR_REDIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_REDIE_SHIFT)) & ESAI_RCR_REDIE_MASK)
44986#define ESAI_RCR_RIE_MASK (0x400000U)
44987#define ESAI_RCR_RIE_SHIFT (22U)
44988/*! RIE - RIE
44989 */
44990#define ESAI_RCR_RIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RIE_SHIFT)) & ESAI_RCR_RIE_MASK)
44991#define ESAI_RCR_RLIE_MASK (0x800000U)
44992#define ESAI_RCR_RLIE_SHIFT (23U)
44993/*! RLIE - RLIE
44994 */
44995#define ESAI_RCR_RLIE(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCR_RLIE_SHIFT)) & ESAI_RCR_RLIE_MASK)
44996/*! @} */
44997
44998/*! @name RCCR - Receive Clock Control Register */
44999/*! @{ */
45000#define ESAI_RCCR_RPM_MASK (0xFFU)
45001#define ESAI_RCCR_RPM_SHIFT (0U)
45002/*! RPM - RPM
45003 */
45004#define ESAI_RCCR_RPM(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RPM_SHIFT)) & ESAI_RCCR_RPM_MASK)
45005#define ESAI_RCCR_RPSR_MASK (0x100U)
45006#define ESAI_RCCR_RPSR_SHIFT (8U)
45007/*! RPSR - RPSR
45008 */
45009#define ESAI_RCCR_RPSR(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RPSR_SHIFT)) & ESAI_RCCR_RPSR_MASK)
45010#define ESAI_RCCR_RDC_MASK (0x3E00U)
45011#define ESAI_RCCR_RDC_SHIFT (9U)
45012/*! RDC - RDC
45013 */
45014#define ESAI_RCCR_RDC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RDC_SHIFT)) & ESAI_RCCR_RDC_MASK)
45015#define ESAI_RCCR_RFP_MASK (0x3C000U)
45016#define ESAI_RCCR_RFP_SHIFT (14U)
45017/*! RFP - RFP
45018 */
45019#define ESAI_RCCR_RFP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFP_SHIFT)) & ESAI_RCCR_RFP_MASK)
45020#define ESAI_RCCR_RCKP_MASK (0x40000U)
45021#define ESAI_RCCR_RCKP_SHIFT (18U)
45022/*! RCKP - RCKP
45023 */
45024#define ESAI_RCCR_RCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RCKP_SHIFT)) & ESAI_RCCR_RCKP_MASK)
45025#define ESAI_RCCR_RFSP_MASK (0x80000U)
45026#define ESAI_RCCR_RFSP_SHIFT (19U)
45027/*! RFSP - RFSP
45028 */
45029#define ESAI_RCCR_RFSP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFSP_SHIFT)) & ESAI_RCCR_RFSP_MASK)
45030#define ESAI_RCCR_RHCKP_MASK (0x100000U)
45031#define ESAI_RCCR_RHCKP_SHIFT (20U)
45032/*! RHCKP - RHCKP
45033 */
45034#define ESAI_RCCR_RHCKP(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RHCKP_SHIFT)) & ESAI_RCCR_RHCKP_MASK)
45035#define ESAI_RCCR_RCKD_MASK (0x200000U)
45036#define ESAI_RCCR_RCKD_SHIFT (21U)
45037/*! RCKD - RCKD
45038 */
45039#define ESAI_RCCR_RCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RCKD_SHIFT)) & ESAI_RCCR_RCKD_MASK)
45040#define ESAI_RCCR_RFSD_MASK (0x400000U)
45041#define ESAI_RCCR_RFSD_SHIFT (22U)
45042/*! RFSD - RFSD
45043 */
45044#define ESAI_RCCR_RFSD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RFSD_SHIFT)) & ESAI_RCCR_RFSD_MASK)
45045#define ESAI_RCCR_RHCKD_MASK (0x800000U)
45046#define ESAI_RCCR_RHCKD_SHIFT (23U)
45047/*! RHCKD - RHCKD
45048 */
45049#define ESAI_RCCR_RHCKD(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RCCR_RHCKD_SHIFT)) & ESAI_RCCR_RHCKD_MASK)
45050/*! @} */
45051
45052/*! @name TSMA - Transmit Slot Mask Register A */
45053/*! @{ */
45054#define ESAI_TSMA_TS_MASK (0xFFFFU)
45055#define ESAI_TSMA_TS_SHIFT (0U)
45056/*! TS - Lower 16 bits of TS
45057 */
45058#define ESAI_TSMA_TS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TSMA_TS_SHIFT)) & ESAI_TSMA_TS_MASK)
45059/*! @} */
45060
45061/*! @name TSMB - Transmit Slot Mask Register B */
45062/*! @{ */
45063#define ESAI_TSMB_TS_MASK (0xFFFFU)
45064#define ESAI_TSMB_TS_SHIFT (0U)
45065/*! TS - TS
45066 */
45067#define ESAI_TSMB_TS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_TSMB_TS_SHIFT)) & ESAI_TSMB_TS_MASK)
45068/*! @} */
45069
45070/*! @name RSMA - Receive Slot Mask Register A */
45071/*! @{ */
45072#define ESAI_RSMA_RS_MASK (0xFFFFU)
45073#define ESAI_RSMA_RS_SHIFT (0U)
45074/*! RS - RS
45075 */
45076#define ESAI_RSMA_RS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RSMA_RS_SHIFT)) & ESAI_RSMA_RS_MASK)
45077/*! @} */
45078
45079/*! @name RSMB - Receive Slot Mask Register B */
45080/*! @{ */
45081#define ESAI_RSMB_RS_MASK (0xFFFFU)
45082#define ESAI_RSMB_RS_SHIFT (0U)
45083/*! RS - RS
45084 */
45085#define ESAI_RSMB_RS(x) (((uint32_t)(((uint32_t)(x)) << ESAI_RSMB_RS_SHIFT)) & ESAI_RSMB_RS_MASK)
45086/*! @} */
45087
45088/*! @name PRRC - Port C Direction Register */
45089/*! @{ */
45090#define ESAI_PRRC_PDC_MASK (0xFFFU)
45091#define ESAI_PRRC_PDC_SHIFT (0U)
45092/*! PDC - PDC
45093 */
45094#define ESAI_PRRC_PDC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_PRRC_PDC_SHIFT)) & ESAI_PRRC_PDC_MASK)
45095/*! @} */
45096
45097/*! @name PCRC - Port C Control Register */
45098/*! @{ */
45099#define ESAI_PCRC_PC_MASK (0xFFFU)
45100#define ESAI_PCRC_PC_SHIFT (0U)
45101/*! PC - PC
45102 */
45103#define ESAI_PCRC_PC(x) (((uint32_t)(((uint32_t)(x)) << ESAI_PCRC_PC_SHIFT)) & ESAI_PCRC_PC_MASK)
45104/*! @} */
45105
45106
45107/*!
45108 * @}
45109 */ /* end of group ESAI_Register_Masks */
45110
45111
45112/* ESAI - Peripheral instance base addresses */
45113/** Peripheral ADMA__ESAI0 base address */
45114#define ADMA__ESAI0_BASE (0x59010000u)
45115/** Peripheral ADMA__ESAI0 base pointer */
45116#define ADMA__ESAI0 ((ESAI_Type *)ADMA__ESAI0_BASE)
45117/** Array initializer of ESAI peripheral base addresses */
45118#define ESAI_BASE_ADDRS { ADMA__ESAI0_BASE }
45119/** Array initializer of ESAI peripheral base pointers */
45120#define ESAI_BASE_PTRS { ADMA__ESAI0 }
45121/** Interrupt vectors for the ESAI peripheral type */
45122#define ESAI_IRQS { ADMA_ESAI0_INT_IRQn }
45123
45124/*!
45125 * @}
45126 */ /* end of group ESAI_Peripheral_Access_Layer */
45127
45128
45129/* ----------------------------------------------------------------------------
45130 -- FLEXSPI Peripheral Access Layer
45131 ---------------------------------------------------------------------------- */
45132
45133/*!
45134 * @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer
45135 * @{
45136 */
45137
45138/** FLEXSPI - Register Layout Typedef */
45139typedef struct {
45140 __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */
45141 __IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */
45142 __IO uint32_t MCR2; /**< Module Control Register 2, offset: 0x8 */
45143 __IO uint32_t AHBCR; /**< AHB Bus Control Register, offset: 0xC */
45144 __IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x10 */
45145 __IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */
45146 __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */
45147 __IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */
45148 __IO uint32_t AHBRXBUFCR0[8]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */
45149 uint8_t RESERVED_0[32];
45150 __IO uint32_t FLSHCR0[4]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */
45151 __IO uint32_t FLSHCR1[4]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */
45152 __IO uint32_t FLSHCR2[4]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */
45153 uint8_t RESERVED_1[4];
45154 __IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */
45155 uint8_t RESERVED_2[8];
45156 __IO uint32_t IPCR0; /**< IP Control Register 0, offset: 0xA0 */
45157 __IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */
45158 uint8_t RESERVED_3[8];
45159 __IO uint32_t IPCMD; /**< IP Command Register, offset: 0xB0 */
45160 __IO uint32_t DLPR; /**< Data Learn Pattern Register, offset: 0xB4 */
45161 __IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */
45162 __IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */
45163 __IO uint32_t DLLCR[2]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */
45164 uint8_t RESERVED_4[24];
45165 __I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */
45166 __I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */
45167 __I uint32_t STS2; /**< Status Register 2, offset: 0xE8 */
45168 __I uint32_t AHBSPNDSTS; /**< AHB Suspend Status Register, offset: 0xEC */
45169 __I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */
45170 __I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */
45171 uint8_t RESERVED_5[8];
45172 __I uint32_t RFDR[32]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */
45173 __O uint32_t TFDR[32]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */
45174 __IO uint32_t LUT[128]; /**< LUT 0..LUT 127, array offset: 0x200, array step: 0x4 */
45175} FLEXSPI_Type;
45176
45177/* ----------------------------------------------------------------------------
45178 -- FLEXSPI Register Masks
45179 ---------------------------------------------------------------------------- */
45180
45181/*!
45182 * @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks
45183 * @{
45184 */
45185
45186/*! @name MCR0 - Module Control Register 0 */
45187/*! @{ */
45188#define FLEXSPI_MCR0_SWRESET_MASK (0x1U)
45189#define FLEXSPI_MCR0_SWRESET_SHIFT (0U)
45190/*! SWRESET - Software Reset
45191 */
45192#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
45193#define FLEXSPI_MCR0_MDIS_MASK (0x2U)
45194#define FLEXSPI_MCR0_MDIS_SHIFT (1U)
45195/*! MDIS - Module Disable
45196 */
45197#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
45198#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U)
45199#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U)
45200/*! RXCLKSRC - Sample Clock source selection for Flash Reading
45201 * 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally.
45202 * 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
45203 * 0b10..Reserved
45204 * 0b11..Flash provided Read strobe and input from DQS pad
45205 */
45206#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
45207#define FLEXSPI_MCR0_ARDFEN_MASK (0x40U)
45208#define FLEXSPI_MCR0_ARDFEN_SHIFT (6U)
45209/*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO.
45210 * 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response.
45211 * 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.
45212 */
45213#define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
45214#define FLEXSPI_MCR0_ATDFEN_MASK (0x80U)
45215#define FLEXSPI_MCR0_ATDFEN_SHIFT (7U)
45216/*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO.
45217 * 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response.
45218 * 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.
45219 */
45220#define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
45221#define FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U)
45222#define FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U)
45223/*! SERCLKDIV - The serial root clock could be divided inside FlexSPI wrapper. Refer Clocks chapter for more details on clocking.
45224 * 0b000..Divided by 1
45225 * 0b001..Divided by 2
45226 * 0b010..Divided by 3
45227 * 0b011..Divided by 4
45228 * 0b100..Divided by 5
45229 * 0b101..Divided by 6
45230 * 0b110..Divided by 7
45231 * 0b111..Divided by 8
45232 */
45233#define FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK)
45234#define FLEXSPI_MCR0_HSEN_MASK (0x800U)
45235#define FLEXSPI_MCR0_HSEN_SHIFT (11U)
45236/*! HSEN - Half Speed Serial Flash access Enable.
45237 * 0b0..Disable divide by 2 of serial flash clock for half speed commands.
45238 * 0b1..Enable divide by 2 of serial flash clock for half speed commands.
45239 */
45240#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
45241#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U)
45242#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U)
45243/*! DOZEEN - Doze mode enable bit
45244 * 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.
45245 * 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
45246 */
45247#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
45248#define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U)
45249#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U)
45250/*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]).
45251 * 0b0..Disable.
45252 * 0b1..Enable.
45253 */
45254#define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
45255#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U)
45256#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U)
45257/*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications,
45258 * external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is
45259 * enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2).
45260 * 0b0..Disable.
45261 * 0b1..Enable.
45262 */
45263#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
45264#define FLEXSPI_MCR0_LEARNEN_MASK (0x8000U)
45265#define FLEXSPI_MCR0_LEARNEN_SHIFT (15U)
45266/*! LEARNEN - This bit is used to enable/disable data learning feature. When data learning is
45267 * disabled, the sampling clock phase 0 is always used for RX data sampling even if LEARN instruction
45268 * is correctly executed.
45269 * 0b0..Disable.
45270 * 0b1..Enable.
45271 */
45272#define FLEXSPI_MCR0_LEARNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_LEARNEN_SHIFT)) & FLEXSPI_MCR0_LEARNEN_MASK)
45273#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U)
45274#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U)
45275/*! IPGRANTWAIT - Time out wait cycle for IP command grant.
45276 */
45277#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
45278#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U)
45279#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U)
45280/*! AHBGRANTWAIT - Timeout wait cycle for AHB command grant.
45281 */
45282#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
45283/*! @} */
45284
45285/*! @name MCR1 - Module Control Register 1 */
45286/*! @{ */
45287#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU)
45288#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U)
45289#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
45290#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U)
45291#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U)
45292#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
45293/*! @} */
45294
45295/*! @name MCR2 - Module Control Register 2 */
45296/*! @{ */
45297#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U)
45298#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U)
45299/*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned
45300 * automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or
45301 * AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP
45302 * mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.
45303 * 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.
45304 * 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
45305 */
45306#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
45307#define FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U)
45308#define FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U)
45309/*! CLRLEARNPHASE - The sampling clock phase selection will be reset to phase 0 when this bit is
45310 * written with 0x1. This bit will be auto-cleared immediately.
45311 */
45312#define FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK)
45313#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U)
45314#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U)
45315/*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2.
45316 * 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash
45317 * A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1,
45318 * FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be
45319 * ignored.
45320 * 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
45321 */
45322#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
45323#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U)
45324#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U)
45325/*! SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to
45326 * A_SCLK). In this case, port B flash access is not available. After changing the value of this
45327 * field, MCR0[SWRESET] should be set.
45328 * 0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available.
45329 * 0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available.
45330 */
45331#define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
45332#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U)
45333#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U)
45334/*! RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.
45335 */
45336#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
45337/*! @} */
45338
45339/*! @name AHBCR - AHB Bus Control Register */
45340/*! @{ */
45341#define FLEXSPI_AHBCR_APAREN_MASK (0x1U)
45342#define FLEXSPI_AHBCR_APAREN_SHIFT (0U)
45343/*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) .
45344 * 0b0..Flash will be accessed in Individual mode.
45345 * 0b1..Flash will be accessed in Parallel mode.
45346 */
45347#define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
45348#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U)
45349#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U)
45350/*! CACHABLEEN - Enable AHB bus cachable read access support.
45351 * 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.
45352 * 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
45353 */
45354#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
45355#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U)
45356#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U)
45357/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat
45358 * of AHB write access, refer for more details about AHB bufferable write.
45359 * 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus
45360 * ready after all data is transmitted to External device and AHB command finished.
45361 * 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is
45362 * granted by arbitrator and will not wait for AHB command finished.
45363 */
45364#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
45365#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U)
45366#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U)
45367/*! PREFETCHEN - AHB Read Prefetch Enable.
45368 */
45369#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
45370#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U)
45371#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U)
45372/*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.
45373 * 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable.
45374 * 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB
45375 * burst required to meet the alignment requirement.
45376 */
45377#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
45378/*! @} */
45379
45380/*! @name INTEN - Interrupt Enable Register */
45381/*! @{ */
45382#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U)
45383#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U)
45384/*! IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable.
45385 */
45386#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
45387#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U)
45388#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U)
45389/*! IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable.
45390 */
45391#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
45392#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U)
45393#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U)
45394/*! AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable.
45395 */
45396#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
45397#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U)
45398#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U)
45399/*! IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable.
45400 */
45401#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
45402#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U)
45403#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U)
45404/*! AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable.
45405 */
45406#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
45407#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U)
45408#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U)
45409/*! IPRXWAEN - IP RX FIFO WaterMark available interrupt enable.
45410 */
45411#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
45412#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U)
45413#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U)
45414/*! IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable.
45415 */
45416#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
45417#define FLEXSPI_INTEN_DATALEARNFAILEN_MASK (0x80U)
45418#define FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT (7U)
45419/*! DATALEARNFAILEN - Data Learning failed interrupt enable.
45420 */
45421#define FLEXSPI_INTEN_DATALEARNFAILEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_DATALEARNFAILEN_SHIFT)) & FLEXSPI_INTEN_DATALEARNFAILEN_MASK)
45422#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U)
45423#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U)
45424/*! SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable.
45425 */
45426#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
45427#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U)
45428#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U)
45429/*! SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable.
45430 */
45431#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
45432#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U)
45433#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U)
45434/*! AHBBUSTIMEOUTEN - AHB Bus timeout interrupt.Refer Interrupts chapter for more details.
45435 */
45436#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK)
45437#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U)
45438#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U)
45439/*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details.
45440 */
45441#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
45442/*! @} */
45443
45444/*! @name INTR - Interrupt Register */
45445/*! @{ */
45446#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U)
45447#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U)
45448/*! IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also
45449 * generated when there is IPCMDGE or IPCMDERR interrupt generated.
45450 */
45451#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
45452#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U)
45453#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U)
45454/*! IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt.
45455 */
45456#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
45457#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U)
45458#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U)
45459/*! AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt.
45460 */
45461#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
45462#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U)
45463#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U)
45464/*! IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for
45465 * IP command, this command will be ignored and not executed at all.
45466 */
45467#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
45468#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U)
45469#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U)
45470/*! AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for
45471 * AHB command, this command will be ignored and not executed at all.
45472 */
45473#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
45474#define FLEXSPI_INTR_IPRXWA_MASK (0x20U)
45475#define FLEXSPI_INTR_IPRXWA_SHIFT (5U)
45476/*! IPRXWA - IP RX FIFO watermark available interrupt.
45477 */
45478#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
45479#define FLEXSPI_INTR_IPTXWE_MASK (0x40U)
45480#define FLEXSPI_INTR_IPTXWE_SHIFT (6U)
45481/*! IPTXWE - IP TX FIFO watermark empty interrupt.
45482 */
45483#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
45484#define FLEXSPI_INTR_DATALEARNFAIL_MASK (0x80U)
45485#define FLEXSPI_INTR_DATALEARNFAIL_SHIFT (7U)
45486/*! DATALEARNFAIL - Data Learning failed interrupt.
45487 */
45488#define FLEXSPI_INTR_DATALEARNFAIL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_DATALEARNFAIL_SHIFT)) & FLEXSPI_INTR_DATALEARNFAIL_MASK)
45489#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U)
45490#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U)
45491/*! SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt.
45492 */
45493#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
45494#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U)
45495#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U)
45496/*! SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt.
45497 */
45498#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
45499#define FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U)
45500#define FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U)
45501/*! AHBBUSTIMEOUT - AHB Bus timeout interrupt.Refer Interrupts chapter for more details.
45502 */
45503#define FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK)
45504#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U)
45505#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U)
45506/*! SEQTIMEOUT - Sequence execution timeout interrupt.
45507 */
45508#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
45509/*! @} */
45510
45511/*! @name LUTKEY - LUT Key Register */
45512/*! @{ */
45513#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)
45514#define FLEXSPI_LUTKEY_KEY_SHIFT (0U)
45515/*! KEY - The Key to lock or unlock LUT.
45516 */
45517#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
45518/*! @} */
45519
45520/*! @name LUTCR - LUT Control Register */
45521/*! @{ */
45522#define FLEXSPI_LUTCR_LOCK_MASK (0x1U)
45523#define FLEXSPI_LUTCR_LOCK_SHIFT (0U)
45524/*! LOCK - Lock LUT
45525 */
45526#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
45527#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U)
45528#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U)
45529/*! UNLOCK - Unlock LUT
45530 */
45531#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
45532/*! @} */
45533
45534/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */
45535/*! @{ */
45536#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0x1FFU)
45537#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U)
45538/*! BUFSZ - AHB RX Buffer Size in 64 bits.
45539 */
45540#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
45541#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U)
45542#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U)
45543/*! MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).
45544 */
45545#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
45546#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U)
45547#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U)
45548/*! PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned.
45549 */
45550#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
45551#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U)
45552#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U)
45553/*! PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.
45554 */
45555#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
45556/*! @} */
45557
45558/* The count of FLEXSPI_AHBRXBUFCR0 */
45559#define FLEXSPI_AHBRXBUFCR0_COUNT (8U)
45560
45561/*! @name FLSHCR0 - Flash Control Register 0 */
45562/*! @{ */
45563#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU)
45564#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U)
45565/*! FLSHSZ - Flash Size in KByte.
45566 */
45567#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
45568/*! @} */
45569
45570/* The count of FLEXSPI_FLSHCR0 */
45571#define FLEXSPI_FLSHCR0_COUNT (4U)
45572
45573/*! @name FLSHCR1 - Flash Control Register 1 */
45574/*! @{ */
45575#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU)
45576#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U)
45577/*! TCSS - Serial Flash CS setup time.
45578 */
45579#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
45580#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U)
45581#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U)
45582/*! TCSH - Serial Flash CS Hold time.
45583 */
45584#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
45585#define FLEXSPI_FLSHCR1_WA_MASK (0x400U)
45586#define FLEXSPI_FLSHCR1_WA_SHIFT (10U)
45587/*! WA - Word Addressable.
45588 */
45589#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
45590#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U)
45591#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U)
45592/*! CAS - Column Address Size.
45593 */
45594#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
45595#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U)
45596#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U)
45597/*! CSINTERVALUNIT - CS interval unit
45598 * 0b0..The CS interval unit is 1 serial clock cycle
45599 * 0b1..The CS interval unit is 256 serial clock cycle
45600 */
45601#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
45602#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U)
45603#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U)
45604/*! CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection
45605 * deassertion and flash device Chip selection assertion. If external flash has a limitation on
45606 * the interval between command sequences, this field should be set accordingly. If there is no
45607 * limitation, set this field with value 0x0.
45608 */
45609#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
45610/*! @} */
45611
45612/* The count of FLEXSPI_FLSHCR1 */
45613#define FLEXSPI_FLSHCR1_COUNT (4U)
45614
45615/*! @name FLSHCR2 - Flash Control Register 2 */
45616/*! @{ */
45617#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0x1FU)
45618#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U)
45619/*! ARDSEQID - Sequence Index for AHB Read triggered Command in LUT.
45620 */
45621#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
45622#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U)
45623#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U)
45624/*! ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT.
45625 */
45626#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
45627#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0x1F00U)
45628#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U)
45629/*! AWRSEQID - Sequence Index for AHB Write triggered Command.
45630 */
45631#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
45632#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U)
45633#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U)
45634/*! AWRSEQNUM - Sequence Number for AHB Write triggered Command.
45635 */
45636#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
45637#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U)
45638#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U)
45639#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
45640#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U)
45641#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U)
45642/*! AWRWAITUNIT - AWRWAIT unit
45643 * 0b000..The AWRWAIT unit is 2 ahb clock cycle
45644 * 0b001..The AWRWAIT unit is 8 ahb clock cycle
45645 * 0b010..The AWRWAIT unit is 32 ahb clock cycle
45646 * 0b011..The AWRWAIT unit is 128 ahb clock cycle
45647 * 0b100..The AWRWAIT unit is 512 ahb clock cycle
45648 * 0b101..The AWRWAIT unit is 2048 ahb clock cycle
45649 * 0b110..The AWRWAIT unit is 8192 ahb clock cycle
45650 * 0b111..The AWRWAIT unit is 32768 ahb clock cycle
45651 */
45652#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
45653#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U)
45654#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U)
45655/*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS.
45656 * Refer Programmable Sequence Engine for details.
45657 */
45658#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
45659/*! @} */
45660
45661/* The count of FLEXSPI_FLSHCR2 */
45662#define FLEXSPI_FLSHCR2_COUNT (4U)
45663
45664/*! @name FLSHCR4 - Flash Control Register 4 */
45665/*! @{ */
45666#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U)
45667#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U)
45668/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.
45669 * 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write
45670 * burst start address alignment when flash is accessed in individual mode.
45671 * 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write
45672 * burst start address alignment when flash is accessed in individual mode.
45673 */
45674#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
45675#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U)
45676#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U)
45677/*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for
45678 * memory device on port A, this bit must be set.
45679 * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
45680 * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
45681 */
45682#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
45683#define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U)
45684#define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U)
45685/*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for
45686 * memory device on port B, this bit must be set.
45687 * 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
45688 * 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
45689 */
45690#define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
45691/*! @} */
45692
45693/*! @name IPCR0 - IP Control Register 0 */
45694/*! @{ */
45695#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU)
45696#define FLEXSPI_IPCR0_SFAR_SHIFT (0U)
45697/*! SFAR - Serial Flash Address for IP command.
45698 */
45699#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
45700/*! @} */
45701
45702/*! @name IPCR1 - IP Control Register 1 */
45703/*! @{ */
45704#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU)
45705#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U)
45706/*! IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command.
45707 */
45708#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
45709#define FLEXSPI_IPCR1_ISEQID_MASK (0x1F0000U)
45710#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U)
45711/*! ISEQID - Sequence Index in LUT for IP command.
45712 */
45713#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
45714#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U)
45715#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U)
45716/*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1.
45717 */
45718#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
45719#define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U)
45720#define FLEXSPI_IPCR1_IPAREN_SHIFT (31U)
45721/*! IPAREN - Parallel mode Enabled for IP command.
45722 * 0b0..Flash will be accessed in Individual mode.
45723 * 0b1..Flash will be accessed in Parallel mode.
45724 */
45725#define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
45726/*! @} */
45727
45728/*! @name IPCMD - IP Command Register */
45729/*! @{ */
45730#define FLEXSPI_IPCMD_TRG_MASK (0x1U)
45731#define FLEXSPI_IPCMD_TRG_SHIFT (0U)
45732/*! TRG - Setting this bit will trigger an IP Command.
45733 */
45734#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
45735/*! @} */
45736
45737/*! @name DLPR - Data Learn Pattern Register */
45738/*! @{ */
45739#define FLEXSPI_DLPR_DLP_MASK (0xFFFFFFFFU)
45740#define FLEXSPI_DLPR_DLP_SHIFT (0U)
45741/*! DLP - Data Learning Pattern.
45742 */
45743#define FLEXSPI_DLPR_DLP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLPR_DLP_SHIFT)) & FLEXSPI_DLPR_DLP_MASK)
45744/*! @} */
45745
45746/*! @name IPRXFCR - IP RX FIFO Control Register */
45747/*! @{ */
45748#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U)
45749#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U)
45750/*! CLRIPRXF - Clear all valid data entries in IP RX FIFO.
45751 */
45752#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
45753#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U)
45754#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U)
45755/*! RXDMAEN - IP RX FIFO reading by DMA enabled.
45756 * 0b0..IP RX FIFO would be read by processor.
45757 * 0b1..IP RX FIFO would be read by DMA.
45758 */
45759#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
45760#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0xFCU)
45761#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U)
45762/*! RXWMRK - Watermark level is (RXWMRK+1)*64 Bits.
45763 */
45764#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
45765/*! @} */
45766
45767/*! @name IPTXFCR - IP TX FIFO Control Register */
45768/*! @{ */
45769#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U)
45770#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U)
45771/*! CLRIPTXF - Clear all valid data entries in IP TX FIFO.
45772 */
45773#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
45774#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U)
45775#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U)
45776/*! TXDMAEN - IP TX FIFO filling by DMA enabled.
45777 * 0b0..IP TX FIFO would be filled by processor.
45778 * 0b1..IP TX FIFO would be filled by DMA.
45779 */
45780#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
45781#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x1FCU)
45782#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U)
45783/*! TXWMRK - Watermark level is (TXWMRK+1)*64 Bits.
45784 */
45785#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
45786/*! @} */
45787
45788/*! @name DLLCR - DLL Control Register 0 */
45789/*! @{ */
45790#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U)
45791#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U)
45792/*! DLLEN - DLL calibration enable.
45793 */
45794#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
45795#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U)
45796#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U)
45797/*! DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the
45798 * DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset
45799 * action is edge triggered, so software need to clear this bit after set this bit (no delay
45800 * limitation).
45801 */
45802#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
45803#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U)
45804#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U)
45805/*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock).
45806 */
45807#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
45808#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U)
45809#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U)
45810/*! OVRDEN - Slave clock delay line delay cell number selection override enable.
45811 */
45812#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
45813#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U)
45814#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U)
45815/*! OVRDVAL - Slave clock delay line delay cell number selection override value.
45816 */
45817#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
45818/*! @} */
45819
45820/* The count of FLEXSPI_DLLCR */
45821#define FLEXSPI_DLLCR_COUNT (2U)
45822
45823/*! @name STS0 - Status Register 0 */
45824/*! @{ */
45825#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U)
45826#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U)
45827/*! SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command
45828 * sequence executing on FlexSPI interface.
45829 */
45830#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
45831#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U)
45832#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U)
45833/*! ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command
45834 * sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state
45835 * (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So
45836 * this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.
45837 */
45838#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
45839#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU)
45840#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U)
45841/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted
45842 * by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).
45843 * 0b00..Triggered by AHB read command (triggered by AHB read).
45844 * 0b01..Triggered by AHB write command (triggered by AHB Write).
45845 * 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG).
45846 * 0b11..Triggered by suspended command (resumed).
45847 */
45848#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
45849#define FLEXSPI_STS0_DATALEARNPHASEA_MASK (0xF0U)
45850#define FLEXSPI_STS0_DATALEARNPHASEA_SHIFT (4U)
45851/*! DATALEARNPHASEA - Indicate the sampling clock phase selection on Port A after Data Learning.
45852 */
45853#define FLEXSPI_STS0_DATALEARNPHASEA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEA_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEA_MASK)
45854#define FLEXSPI_STS0_DATALEARNPHASEB_MASK (0xF00U)
45855#define FLEXSPI_STS0_DATALEARNPHASEB_SHIFT (8U)
45856/*! DATALEARNPHASEB - Indicate the sampling clock phase selection on Port B after Data Learning.
45857 */
45858#define FLEXSPI_STS0_DATALEARNPHASEB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_DATALEARNPHASEB_SHIFT)) & FLEXSPI_STS0_DATALEARNPHASEB_MASK)
45859/*! @} */
45860
45861/*! @name STS1 - Status Register 1 */
45862/*! @{ */
45863#define FLEXSPI_STS1_AHBCMDERRID_MASK (0x1FU)
45864#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U)
45865/*! AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field
45866 * will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
45867 */
45868#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
45869#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U)
45870#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U)
45871/*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be
45872 * cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
45873 * 0b0000..No error.
45874 * 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence.
45875 * 0b0011..There is unknown instruction opcode in the sequence.
45876 * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
45877 * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
45878 * 0b1110..Sequence execution timeout.
45879 */
45880#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
45881#define FLEXSPI_STS1_IPCMDERRID_MASK (0x1F0000U)
45882#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U)
45883/*! IPCMDERRID - Indicates the sequence Index when IP command error detected. This field will be
45884 * cleared when INTR[IPCMDERR] is write-1-clear(w1c).
45885 */
45886#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
45887#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U)
45888#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U)
45889/*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be
45890 * cleared when INTR[IPCMDERR] is write-1-clear(w1c).
45891 * 0b0000..No error.
45892 * 0b0010..IP command with JMP_ON_CS instruction used in the sequence.
45893 * 0b0011..There is unknown instruction opcode in the sequence.
45894 * 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
45895 * 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
45896 * 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2).
45897 * 0b1110..Sequence execution timeout.
45898 * 0b1111..Flash boundary crossed.
45899 */
45900#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
45901/*! @} */
45902
45903/*! @name STS2 - Status Register 2 */
45904/*! @{ */
45905#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U)
45906#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U)
45907/*! ASLVLOCK - Flash A sample clock slave delay line locked.
45908 */
45909#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
45910#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U)
45911#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U)
45912/*! AREFLOCK - Flash A sample clock reference delay line locked.
45913 */
45914#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
45915#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU)
45916#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U)
45917/*! ASLVSEL - Flash A sample clock slave delay line delay cell number selection .
45918 */
45919#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
45920#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U)
45921#define FLEXSPI_STS2_AREFSEL_SHIFT (8U)
45922/*! AREFSEL - Flash A sample clock reference delay line delay cell number selection.
45923 */
45924#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
45925#define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U)
45926#define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U)
45927/*! BSLVLOCK - Flash B sample clock slave delay line locked.
45928 */
45929#define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
45930#define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U)
45931#define FLEXSPI_STS2_BREFLOCK_SHIFT (17U)
45932/*! BREFLOCK - Flash B sample clock reference delay line locked.
45933 */
45934#define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
45935#define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U)
45936#define FLEXSPI_STS2_BSLVSEL_SHIFT (18U)
45937/*! BSLVSEL - Flash B sample clock slave delay line delay cell number selection.
45938 */
45939#define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
45940#define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U)
45941#define FLEXSPI_STS2_BREFSEL_SHIFT (24U)
45942/*! BREFSEL - Flash B sample clock reference delay line delay cell number selection.
45943 */
45944#define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
45945/*! @} */
45946
45947/*! @name AHBSPNDSTS - AHB Suspend Status Register */
45948/*! @{ */
45949#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U)
45950#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U)
45951/*! ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended.
45952 */
45953#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
45954#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU)
45955#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U)
45956/*! BUFID - AHB RX BUF ID for suspended command sequence.
45957 */
45958#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
45959#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U)
45960#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U)
45961/*! DATLFT - Left Data size for suspended command sequence (in byte).
45962 */
45963#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
45964/*! @} */
45965
45966/*! @name IPRXFSTS - IP RX FIFO Status Register */
45967/*! @{ */
45968#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU)
45969#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U)
45970/*! FILL - Fill level of IP RX FIFO.
45971 */
45972#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
45973#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U)
45974#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U)
45975/*! RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits.
45976 */
45977#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
45978/*! @} */
45979
45980/*! @name IPTXFSTS - IP TX FIFO Status Register */
45981/*! @{ */
45982#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU)
45983#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U)
45984/*! FILL - Fill level of IP TX FIFO.
45985 */
45986#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
45987#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U)
45988#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U)
45989/*! WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits.
45990 */
45991#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
45992/*! @} */
45993
45994/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */
45995/*! @{ */
45996#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU)
45997#define FLEXSPI_RFDR_RXDATA_SHIFT (0U)
45998/*! RXDATA - RX Data
45999 */
46000#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
46001/*! @} */
46002
46003/* The count of FLEXSPI_RFDR */
46004#define FLEXSPI_RFDR_COUNT (32U)
46005
46006/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */
46007/*! @{ */
46008#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU)
46009#define FLEXSPI_TFDR_TXDATA_SHIFT (0U)
46010/*! TXDATA - TX Data
46011 */
46012#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
46013/*! @} */
46014
46015/* The count of FLEXSPI_TFDR */
46016#define FLEXSPI_TFDR_COUNT (32U)
46017
46018/*! @name LUT - LUT 0..LUT 127 */
46019/*! @{ */
46020#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU)
46021#define FLEXSPI_LUT_OPERAND0_SHIFT (0U)
46022/*! OPERAND0 - OPERAND0
46023 */
46024#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
46025#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U)
46026#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U)
46027/*! NUM_PADS0 - NUM_PADS0
46028 */
46029#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
46030#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U)
46031#define FLEXSPI_LUT_OPCODE0_SHIFT (10U)
46032/*! OPCODE0 - OPCODE
46033 */
46034#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
46035#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)
46036#define FLEXSPI_LUT_OPERAND1_SHIFT (16U)
46037/*! OPERAND1 - OPERAND1
46038 */
46039#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
46040#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)
46041#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U)
46042/*! NUM_PADS1 - NUM_PADS1
46043 */
46044#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
46045#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)
46046#define FLEXSPI_LUT_OPCODE1_SHIFT (26U)
46047/*! OPCODE1 - OPCODE1
46048 */
46049#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
46050/*! @} */
46051
46052/* The count of FLEXSPI_LUT */
46053#define FLEXSPI_LUT_COUNT (128U)
46054
46055
46056/*!
46057 * @}
46058 */ /* end of group FLEXSPI_Register_Masks */
46059
46060
46061/* FLEXSPI - Peripheral instance base addresses */
46062/** Peripheral LSIO__FLEXSPI0 base address */
46063#define LSIO__FLEXSPI0_BASE (0x5D120000u)
46064/** Peripheral LSIO__FLEXSPI0 base pointer */
46065#define LSIO__FLEXSPI0 ((FLEXSPI_Type *)LSIO__FLEXSPI0_BASE)
46066/** Peripheral LSIO__FLEXSPI1 base address */
46067#define LSIO__FLEXSPI1_BASE (0x5D130000u)
46068/** Peripheral LSIO__FLEXSPI1 base pointer */
46069#define LSIO__FLEXSPI1 ((FLEXSPI_Type *)LSIO__FLEXSPI1_BASE)
46070/** Array initializer of FLEXSPI peripheral base addresses */
46071#define FLEXSPI_BASE_ADDRS { LSIO__FLEXSPI0_BASE, LSIO__FLEXSPI1_BASE }
46072/** Array initializer of FLEXSPI peripheral base pointers */
46073#define FLEXSPI_BASE_PTRS { LSIO__FLEXSPI0, LSIO__FLEXSPI1 }
46074/** Interrupt vectors for the FLEXSPI peripheral type */
46075#define FLEXSPI_IRQS { LSIO_OCTASPI0_INT_IRQn, LSIO_OCTASPI1_INT_IRQn }
46076/* FlexSPI0 AMBA address. */
46077#define FlexSPI0_AMBA_BASE (0x08000000U)
46078
46079
46080/*!
46081 * @}
46082 */ /* end of group FLEXSPI_Peripheral_Access_Layer */
46083
46084
46085/* ----------------------------------------------------------------------------
46086 -- FTM Peripheral Access Layer
46087 ---------------------------------------------------------------------------- */
46088
46089/*!
46090 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
46091 * @{
46092 */
46093
46094/** FTM - Register Layout Typedef */
46095typedef struct {
46096 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
46097 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
46098 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
46099 struct { /* offset: 0xC, array step: 0x8 */
46100 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
46101 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
46102 } CONTROLS[8];
46103 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
46104 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
46105 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
46106 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
46107 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
46108 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
46109 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
46110 __IO uint32_t DEADTIME; /**< Deadtime Configuration, offset: 0x68 */
46111 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
46112 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
46113 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
46114 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
46115 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
46116 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
46117 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
46118 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
46119 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
46120 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
46121 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
46122 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
46123 __IO uint32_t HCR; /**< Half Cycle Register, offset: 0x9C */
46124 uint8_t RESERVED_0[352];
46125 __IO uint32_t MOD_MIRROR; /**< Mirror of Modulo Value, offset: 0x200 */
46126 __IO uint32_t CV_MIRROR[8]; /**< Mirror of Channel (n) Match Value, array offset: 0x204, array step: 0x4 */
46127} FTM_Type;
46128
46129/* ----------------------------------------------------------------------------
46130 -- FTM Register Masks
46131 ---------------------------------------------------------------------------- */
46132
46133/*!
46134 * @addtogroup FTM_Register_Masks FTM Register Masks
46135 * @{
46136 */
46137
46138/*! @name SC - Status And Control */
46139/*! @{ */
46140#define FTM_SC_PS_MASK (0x7U)
46141#define FTM_SC_PS_SHIFT (0U)
46142/*! PS - Prescale Factor Selection
46143 * 0b000..Divide by 1
46144 * 0b001..Divide by 2
46145 * 0b010..Divide by 4
46146 * 0b011..Divide by 8
46147 * 0b100..Divide by 16
46148 * 0b101..Divide by 32
46149 * 0b110..Divide by 64
46150 * 0b111..Divide by 128
46151 */
46152#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
46153#define FTM_SC_CLKS_MASK (0x18U)
46154#define FTM_SC_CLKS_SHIFT (3U)
46155/*! CLKS - Clock Source Selection
46156 * 0b00..No clock selected. This in effect disables the FTM counter.
46157 * 0b01..FTM input clock
46158 * 0b10..Fixed frequency clock
46159 * 0b11..External clock
46160 */
46161#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
46162#define FTM_SC_CPWMS_MASK (0x20U)
46163#define FTM_SC_CPWMS_SHIFT (5U)
46164/*! CPWMS - Center-Aligned PWM Select
46165 * 0b0..FTM counter operates in Up Counting mode.
46166 * 0b1..FTM counter operates in Up-Down Counting mode.
46167 */
46168#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
46169#define FTM_SC_RIE_MASK (0x40U)
46170#define FTM_SC_RIE_SHIFT (6U)
46171/*! RIE - Reload Point Interrupt Enable
46172 * 0b0..Reload point interrupt is disabled.
46173 * 0b1..Reload point interrupt is enabled.
46174 */
46175#define FTM_SC_RIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_RIE_SHIFT)) & FTM_SC_RIE_MASK)
46176#define FTM_SC_RF_MASK (0x80U)
46177#define FTM_SC_RF_SHIFT (7U)
46178/*! RF - Reload Flag
46179 * 0b0..A selected reload point did not happen.
46180 * 0b1..A selected reload point happened.
46181 */
46182#define FTM_SC_RF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_RF_SHIFT)) & FTM_SC_RF_MASK)
46183#define FTM_SC_TOIE_MASK (0x100U)
46184#define FTM_SC_TOIE_SHIFT (8U)
46185/*! TOIE - Timer Overflow Interrupt Enable
46186 * 0b0..Disable TOF interrupts. Use software polling.
46187 * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.
46188 */
46189#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
46190#define FTM_SC_TOF_MASK (0x200U)
46191#define FTM_SC_TOF_SHIFT (9U)
46192/*! TOF - Timer Overflow Flag
46193 * 0b0..FTM counter has not overflowed.
46194 * 0b1..FTM counter has overflowed.
46195 */
46196#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
46197#define FTM_SC_PWMEN0_MASK (0x10000U)
46198#define FTM_SC_PWMEN0_SHIFT (16U)
46199/*! PWMEN0 - Channel 0 PWM enable bit
46200 * 0b0..Channel output port is disabled.
46201 * 0b1..Channel output port is enabled.
46202 */
46203#define FTM_SC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN0_SHIFT)) & FTM_SC_PWMEN0_MASK)
46204#define FTM_SC_PWMEN1_MASK (0x20000U)
46205#define FTM_SC_PWMEN1_SHIFT (17U)
46206/*! PWMEN1 - Channel 1 PWM enable bit
46207 * 0b0..Channel output port is disabled.
46208 * 0b1..Channel output port is enabled.
46209 */
46210#define FTM_SC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN1_SHIFT)) & FTM_SC_PWMEN1_MASK)
46211#define FTM_SC_PWMEN2_MASK (0x40000U)
46212#define FTM_SC_PWMEN2_SHIFT (18U)
46213/*! PWMEN2 - Channel 2 PWM enable bit
46214 * 0b0..Channel output port is disabled.
46215 * 0b1..Channel output port is enabled.
46216 */
46217#define FTM_SC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN2_SHIFT)) & FTM_SC_PWMEN2_MASK)
46218#define FTM_SC_PWMEN3_MASK (0x80000U)
46219#define FTM_SC_PWMEN3_SHIFT (19U)
46220/*! PWMEN3 - Channel 3 PWM enable bit
46221 * 0b0..Channel output port is disabled.
46222 * 0b1..Channel output port is enabled.
46223 */
46224#define FTM_SC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN3_SHIFT)) & FTM_SC_PWMEN3_MASK)
46225#define FTM_SC_PWMEN4_MASK (0x100000U)
46226#define FTM_SC_PWMEN4_SHIFT (20U)
46227/*! PWMEN4 - Channel 4 PWM enable bit
46228 * 0b0..Channel output port is disabled.
46229 * 0b1..Channel output port is enabled.
46230 */
46231#define FTM_SC_PWMEN4(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN4_SHIFT)) & FTM_SC_PWMEN4_MASK)
46232#define FTM_SC_PWMEN5_MASK (0x200000U)
46233#define FTM_SC_PWMEN5_SHIFT (21U)
46234/*! PWMEN5 - Channel 5 PWM enable bit
46235 * 0b0..Channel output port is disabled.
46236 * 0b1..Channel output port is enabled.
46237 */
46238#define FTM_SC_PWMEN5(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN5_SHIFT)) & FTM_SC_PWMEN5_MASK)
46239#define FTM_SC_PWMEN6_MASK (0x400000U)
46240#define FTM_SC_PWMEN6_SHIFT (22U)
46241/*! PWMEN6 - Channel 6 PWM enable bit
46242 * 0b0..Channel output port is disabled.
46243 * 0b1..Channel output port is enabled.
46244 */
46245#define FTM_SC_PWMEN6(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN6_SHIFT)) & FTM_SC_PWMEN6_MASK)
46246#define FTM_SC_PWMEN7_MASK (0x800000U)
46247#define FTM_SC_PWMEN7_SHIFT (23U)
46248/*! PWMEN7 - Channel 7 PWM enable bit
46249 * 0b0..Channel output port is disabled.
46250 * 0b1..Channel output port is enabled.
46251 */
46252#define FTM_SC_PWMEN7(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PWMEN7_SHIFT)) & FTM_SC_PWMEN7_MASK)
46253#define FTM_SC_FLTPS_MASK (0xF000000U)
46254#define FTM_SC_FLTPS_SHIFT (24U)
46255/*! FLTPS - Filter Prescaler
46256 * 0b0000..Divide by 1
46257 * 0b0001..Divide by 2
46258 * 0b0010..Divide by 3
46259 * 0b0011..Divide by 4
46260 * 0b0100..Divide by 5
46261 * 0b0101..Divide by 6
46262 * 0b0110..Divide by 7
46263 * 0b0111..Divide by 8
46264 * 0b1000..Divide by 9
46265 * 0b1001..Divide by 10
46266 * 0b1010..Divide by 11
46267 * 0b1011..Divide by 12
46268 * 0b1100..Divide by 13
46269 * 0b1101..Divide by 14
46270 * 0b1110..Divide by 15
46271 * 0b1111..Divide by 16
46272 */
46273#define FTM_SC_FLTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_FLTPS_SHIFT)) & FTM_SC_FLTPS_MASK)
46274/*! @} */
46275
46276/*! @name CNT - Counter */
46277/*! @{ */
46278#define FTM_CNT_COUNT_MASK (0xFFFFU)
46279#define FTM_CNT_COUNT_SHIFT (0U)
46280/*! COUNT - Counter Value
46281 */
46282#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
46283/*! @} */
46284
46285/*! @name MOD - Modulo */
46286/*! @{ */
46287#define FTM_MOD_MOD_MASK (0xFFFFU)
46288#define FTM_MOD_MOD_SHIFT (0U)
46289/*! MOD - MOD
46290 */
46291#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
46292/*! @} */
46293
46294/*! @name CnSC - Channel (n) Status And Control */
46295/*! @{ */
46296#define FTM_CnSC_DMA_MASK (0x1U)
46297#define FTM_CnSC_DMA_SHIFT (0U)
46298/*! DMA - DMA Enable
46299 * 0b0..Disable DMA transfers.
46300 * 0b1..Enable DMA transfers.
46301 */
46302#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
46303#define FTM_CnSC_ICRST_MASK (0x2U)
46304#define FTM_CnSC_ICRST_SHIFT (1U)
46305/*! ICRST - FTM counter reset by the selected input capture event.
46306 * 0b0..FTM counter is not reset when the selected channel (n) input event is detected.
46307 * 0b1..FTM counter is reset when the selected channel (n) input event is detected.
46308 */
46309#define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK)
46310#define FTM_CnSC_ELSA_MASK (0x4U)
46311#define FTM_CnSC_ELSA_SHIFT (2U)
46312/*! ELSA - Channel (n) Edge or Level Select
46313 */
46314#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
46315#define FTM_CnSC_ELSB_MASK (0x8U)
46316#define FTM_CnSC_ELSB_SHIFT (3U)
46317/*! ELSB - Channel (n) Edge or Level Select
46318 */
46319#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
46320#define FTM_CnSC_MSA_MASK (0x10U)
46321#define FTM_CnSC_MSA_SHIFT (4U)
46322/*! MSA - Channel (n) Mode Select
46323 */
46324#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
46325#define FTM_CnSC_MSB_MASK (0x20U)
46326#define FTM_CnSC_MSB_SHIFT (5U)
46327/*! MSB - Channel (n) Mode Select
46328 */
46329#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
46330#define FTM_CnSC_CHIE_MASK (0x40U)
46331#define FTM_CnSC_CHIE_SHIFT (6U)
46332/*! CHIE - Channel (n) Interrupt Enable
46333 * 0b0..Disable channel (n) interrupt. Use software polling.
46334 * 0b1..Enable channel (n) interrupt.
46335 */
46336#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
46337#define FTM_CnSC_CHF_MASK (0x80U)
46338#define FTM_CnSC_CHF_SHIFT (7U)
46339/*! CHF - Channel (n) Flag
46340 * 0b0..No channel (n) event has occurred.
46341 * 0b1..A channel (n) event has occurred.
46342 */
46343#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
46344#define FTM_CnSC_TRIGMODE_MASK (0x100U)
46345#define FTM_CnSC_TRIGMODE_SHIFT (8U)
46346/*! TRIGMODE - Trigger mode control
46347 * 0b0..Channel outputs will generate the normal PWM outputs without generating a pulse.
46348 * 0b1..If a match in the channel occurs, a trigger generation on channel output will happen. The trigger pulse width has one FTM clock cycle.
46349 */
46350#define FTM_CnSC_TRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_TRIGMODE_SHIFT)) & FTM_CnSC_TRIGMODE_MASK)
46351#define FTM_CnSC_CHIS_MASK (0x200U)
46352#define FTM_CnSC_CHIS_SHIFT (9U)
46353/*! CHIS - Channel (n) Input State
46354 * 0b0..The channel (n) input is zero.
46355 * 0b1..The channel (n) input is one.
46356 */
46357#define FTM_CnSC_CHIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIS_SHIFT)) & FTM_CnSC_CHIS_MASK)
46358#define FTM_CnSC_CHOV_MASK (0x400U)
46359#define FTM_CnSC_CHOV_SHIFT (10U)
46360/*! CHOV - Channel (n) Output Value
46361 * 0b0..The channel (n) output is zero.
46362 * 0b1..The channel (n) output is one.
46363 */
46364#define FTM_CnSC_CHOV(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHOV_SHIFT)) & FTM_CnSC_CHOV_MASK)
46365/*! @} */
46366
46367/* The count of FTM_CnSC */
46368#define FTM_CnSC_COUNT (8U)
46369
46370/*! @name CnV - Channel (n) Value */
46371/*! @{ */
46372#define FTM_CnV_VAL_MASK (0xFFFFU)
46373#define FTM_CnV_VAL_SHIFT (0U)
46374/*! VAL - Channel Value
46375 */
46376#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
46377/*! @} */
46378
46379/* The count of FTM_CnV */
46380#define FTM_CnV_COUNT (8U)
46381
46382/*! @name CNTIN - Counter Initial Value */
46383/*! @{ */
46384#define FTM_CNTIN_INIT_MASK (0xFFFFU)
46385#define FTM_CNTIN_INIT_SHIFT (0U)
46386/*! INIT - INIT
46387 */
46388#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
46389/*! @} */
46390
46391/*! @name STATUS - Capture And Compare Status */
46392/*! @{ */
46393#define FTM_STATUS_CH0F_MASK (0x1U)
46394#define FTM_STATUS_CH0F_SHIFT (0U)
46395/*! CH0F - Channel 0 Flag
46396 * 0b0..No channel event has occurred.
46397 * 0b1..A channel event has occurred.
46398 */
46399#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
46400#define FTM_STATUS_CH1F_MASK (0x2U)
46401#define FTM_STATUS_CH1F_SHIFT (1U)
46402/*! CH1F - Channel 1 Flag
46403 * 0b0..No channel event has occurred.
46404 * 0b1..A channel event has occurred.
46405 */
46406#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
46407#define FTM_STATUS_CH2F_MASK (0x4U)
46408#define FTM_STATUS_CH2F_SHIFT (2U)
46409/*! CH2F - Channel 2 Flag
46410 * 0b0..No channel event has occurred.
46411 * 0b1..A channel event has occurred.
46412 */
46413#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
46414#define FTM_STATUS_CH3F_MASK (0x8U)
46415#define FTM_STATUS_CH3F_SHIFT (3U)
46416/*! CH3F - Channel 3 Flag
46417 * 0b0..No channel event has occurred.
46418 * 0b1..A channel event has occurred.
46419 */
46420#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
46421#define FTM_STATUS_CH4F_MASK (0x10U)
46422#define FTM_STATUS_CH4F_SHIFT (4U)
46423/*! CH4F - Channel 4 Flag
46424 * 0b0..No channel event has occurred.
46425 * 0b1..A channel event has occurred.
46426 */
46427#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
46428#define FTM_STATUS_CH5F_MASK (0x20U)
46429#define FTM_STATUS_CH5F_SHIFT (5U)
46430/*! CH5F - Channel 5 Flag
46431 * 0b0..No channel event has occurred.
46432 * 0b1..A channel event has occurred.
46433 */
46434#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
46435#define FTM_STATUS_CH6F_MASK (0x40U)
46436#define FTM_STATUS_CH6F_SHIFT (6U)
46437/*! CH6F - Channel 6 Flag
46438 * 0b0..No channel event has occurred.
46439 * 0b1..A channel event has occurred.
46440 */
46441#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
46442#define FTM_STATUS_CH7F_MASK (0x80U)
46443#define FTM_STATUS_CH7F_SHIFT (7U)
46444/*! CH7F - Channel 7 Flag
46445 * 0b0..No channel event has occurred.
46446 * 0b1..A channel event has occurred.
46447 */
46448#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
46449/*! @} */
46450
46451/*! @name MODE - Features Mode Selection */
46452/*! @{ */
46453#define FTM_MODE_FTMEN_MASK (0x1U)
46454#define FTM_MODE_FTMEN_SHIFT (0U)
46455/*! FTMEN - FTM Enable
46456 * 0b0..TPM compatibility. Free running counter and synchronization compatible with TPM.
46457 * 0b1..Free running counter and synchronization are different from TPM behavior.
46458 */
46459#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
46460#define FTM_MODE_INIT_MASK (0x2U)
46461#define FTM_MODE_INIT_SHIFT (1U)
46462/*! INIT - Initialize The Channels Output
46463 */
46464#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
46465#define FTM_MODE_WPDIS_MASK (0x4U)
46466#define FTM_MODE_WPDIS_SHIFT (2U)
46467/*! WPDIS - Write Protection Disable
46468 * 0b0..Write protection is enabled.
46469 * 0b1..Write protection is disabled.
46470 */
46471#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
46472#define FTM_MODE_PWMSYNC_MASK (0x8U)
46473#define FTM_MODE_PWMSYNC_SHIFT (3U)
46474/*! PWMSYNC - PWM Synchronization Mode
46475 * 0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
46476 * 0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used
46477 * by OUTMASK and FTM counter synchronization.
46478 */
46479#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
46480#define FTM_MODE_CAPTEST_MASK (0x10U)
46481#define FTM_MODE_CAPTEST_SHIFT (4U)
46482/*! CAPTEST - Capture Test Mode Enable
46483 * 0b0..Capture test mode is disabled.
46484 * 0b1..Capture test mode is enabled.
46485 */
46486#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
46487#define FTM_MODE_FAULTM_MASK (0x60U)
46488#define FTM_MODE_FAULTM_SHIFT (5U)
46489/*! FAULTM - Fault Control Mode
46490 * 0b00..Fault control is disabled for all channels.
46491 * 0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
46492 * 0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
46493 * 0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
46494 */
46495#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
46496#define FTM_MODE_FAULTIE_MASK (0x80U)
46497#define FTM_MODE_FAULTIE_SHIFT (7U)
46498/*! FAULTIE - Fault Interrupt Enable
46499 * 0b0..Fault control interrupt is disabled.
46500 * 0b1..Fault control interrupt is enabled.
46501 */
46502#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
46503/*! @} */
46504
46505/*! @name SYNC - Synchronization */
46506/*! @{ */
46507#define FTM_SYNC_CNTMIN_MASK (0x1U)
46508#define FTM_SYNC_CNTMIN_SHIFT (0U)
46509/*! CNTMIN - Minimum Loading Point Enable
46510 * 0b0..The minimum loading point is disabled.
46511 * 0b1..The minimum loading point is enabled.
46512 */
46513#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
46514#define FTM_SYNC_CNTMAX_MASK (0x2U)
46515#define FTM_SYNC_CNTMAX_SHIFT (1U)
46516/*! CNTMAX - Maximum Loading Point Enable
46517 * 0b0..The maximum loading point is disabled.
46518 * 0b1..The maximum loading point is enabled.
46519 */
46520#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
46521#define FTM_SYNC_REINIT_MASK (0x4U)
46522#define FTM_SYNC_REINIT_SHIFT (2U)
46523/*! REINIT - FTM Counter Reinitialization by Synchronization
46524 * 0b0..FTM counter continues to count normally.
46525 * 0b1..FTM counter is updated with its initial value when the selected trigger is detected.
46526 */
46527#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
46528#define FTM_SYNC_SYNCHOM_MASK (0x8U)
46529#define FTM_SYNC_SYNCHOM_SHIFT (3U)
46530/*! SYNCHOM - Output Mask Synchronization
46531 * 0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the FTM input clock.
46532 * 0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
46533 */
46534#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
46535#define FTM_SYNC_TRIG0_MASK (0x10U)
46536#define FTM_SYNC_TRIG0_SHIFT (4U)
46537/*! TRIG0 - PWM Synchronization Hardware Trigger 0
46538 * 0b0..Trigger is disabled.
46539 * 0b1..Trigger is enabled.
46540 */
46541#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
46542#define FTM_SYNC_TRIG1_MASK (0x20U)
46543#define FTM_SYNC_TRIG1_SHIFT (5U)
46544/*! TRIG1 - PWM Synchronization Hardware Trigger 1
46545 * 0b0..Trigger is disabled.
46546 * 0b1..Trigger is enabled.
46547 */
46548#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
46549#define FTM_SYNC_TRIG2_MASK (0x40U)
46550#define FTM_SYNC_TRIG2_SHIFT (6U)
46551/*! TRIG2 - PWM Synchronization Hardware Trigger 2
46552 * 0b0..Trigger is disabled.
46553 * 0b1..Trigger is enabled.
46554 */
46555#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
46556#define FTM_SYNC_SWSYNC_MASK (0x80U)
46557#define FTM_SYNC_SWSYNC_SHIFT (7U)
46558/*! SWSYNC - PWM Synchronization Software Trigger
46559 * 0b0..Software trigger is not selected.
46560 * 0b1..Software trigger is selected.
46561 */
46562#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
46563/*! @} */
46564
46565/*! @name OUTINIT - Initial State For Channels Output */
46566/*! @{ */
46567#define FTM_OUTINIT_CH0OI_MASK (0x1U)
46568#define FTM_OUTINIT_CH0OI_SHIFT (0U)
46569/*! CH0OI - Channel 0 Output Initialization Value
46570 * 0b0..The initialization value is 0.
46571 * 0b1..The initialization value is 1.
46572 */
46573#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
46574#define FTM_OUTINIT_CH1OI_MASK (0x2U)
46575#define FTM_OUTINIT_CH1OI_SHIFT (1U)
46576/*! CH1OI - Channel 1 Output Initialization Value
46577 * 0b0..The initialization value is 0.
46578 * 0b1..The initialization value is 1.
46579 */
46580#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
46581#define FTM_OUTINIT_CH2OI_MASK (0x4U)
46582#define FTM_OUTINIT_CH2OI_SHIFT (2U)
46583/*! CH2OI - Channel 2 Output Initialization Value
46584 * 0b0..The initialization value is 0.
46585 * 0b1..The initialization value is 1.
46586 */
46587#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
46588#define FTM_OUTINIT_CH3OI_MASK (0x8U)
46589#define FTM_OUTINIT_CH3OI_SHIFT (3U)
46590/*! CH3OI - Channel 3 Output Initialization Value
46591 * 0b0..The initialization value is 0.
46592 * 0b1..The initialization value is 1.
46593 */
46594#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
46595#define FTM_OUTINIT_CH4OI_MASK (0x10U)
46596#define FTM_OUTINIT_CH4OI_SHIFT (4U)
46597/*! CH4OI - Channel 4 Output Initialization Value
46598 * 0b0..The initialization value is 0.
46599 * 0b1..The initialization value is 1.
46600 */
46601#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
46602#define FTM_OUTINIT_CH5OI_MASK (0x20U)
46603#define FTM_OUTINIT_CH5OI_SHIFT (5U)
46604/*! CH5OI - Channel 5 Output Initialization Value
46605 * 0b0..The initialization value is 0.
46606 * 0b1..The initialization value is 1.
46607 */
46608#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
46609#define FTM_OUTINIT_CH6OI_MASK (0x40U)
46610#define FTM_OUTINIT_CH6OI_SHIFT (6U)
46611/*! CH6OI - Channel 6 Output Initialization Value
46612 * 0b0..The initialization value is 0.
46613 * 0b1..The initialization value is 1.
46614 */
46615#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
46616#define FTM_OUTINIT_CH7OI_MASK (0x80U)
46617#define FTM_OUTINIT_CH7OI_SHIFT (7U)
46618/*! CH7OI - Channel 7 Output Initialization Value
46619 * 0b0..The initialization value is 0.
46620 * 0b1..The initialization value is 1.
46621 */
46622#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
46623/*! @} */
46624
46625/*! @name OUTMASK - Output Mask */
46626/*! @{ */
46627#define FTM_OUTMASK_CH0OM_MASK (0x1U)
46628#define FTM_OUTMASK_CH0OM_SHIFT (0U)
46629/*! CH0OM - Channel 0 Output Mask
46630 * 0b0..Channel output is not masked. It continues to operate normally.
46631 * 0b1..Channel output is masked. It is forced to its inactive state.
46632 */
46633#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
46634#define FTM_OUTMASK_CH1OM_MASK (0x2U)
46635#define FTM_OUTMASK_CH1OM_SHIFT (1U)
46636/*! CH1OM - Channel 1 Output Mask
46637 * 0b0..Channel output is not masked. It continues to operate normally.
46638 * 0b1..Channel output is masked. It is forced to its inactive state.
46639 */
46640#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
46641#define FTM_OUTMASK_CH2OM_MASK (0x4U)
46642#define FTM_OUTMASK_CH2OM_SHIFT (2U)
46643/*! CH2OM - Channel 2 Output Mask
46644 * 0b0..Channel output is not masked. It continues to operate normally.
46645 * 0b1..Channel output is masked. It is forced to its inactive state.
46646 */
46647#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
46648#define FTM_OUTMASK_CH3OM_MASK (0x8U)
46649#define FTM_OUTMASK_CH3OM_SHIFT (3U)
46650/*! CH3OM - Channel 3 Output Mask
46651 * 0b0..Channel output is not masked. It continues to operate normally.
46652 * 0b1..Channel output is masked. It is forced to its inactive state.
46653 */
46654#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
46655#define FTM_OUTMASK_CH4OM_MASK (0x10U)
46656#define FTM_OUTMASK_CH4OM_SHIFT (4U)
46657/*! CH4OM - Channel 4 Output Mask
46658 * 0b0..Channel output is not masked. It continues to operate normally.
46659 * 0b1..Channel output is masked. It is forced to its inactive state.
46660 */
46661#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
46662#define FTM_OUTMASK_CH5OM_MASK (0x20U)
46663#define FTM_OUTMASK_CH5OM_SHIFT (5U)
46664/*! CH5OM - Channel 5 Output Mask
46665 * 0b0..Channel output is not masked. It continues to operate normally.
46666 * 0b1..Channel output is masked. It is forced to its inactive state.
46667 */
46668#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
46669#define FTM_OUTMASK_CH6OM_MASK (0x40U)
46670#define FTM_OUTMASK_CH6OM_SHIFT (6U)
46671/*! CH6OM - Channel 6 Output Mask
46672 * 0b0..Channel output is not masked. It continues to operate normally.
46673 * 0b1..Channel output is masked. It is forced to its inactive state.
46674 */
46675#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
46676#define FTM_OUTMASK_CH7OM_MASK (0x80U)
46677#define FTM_OUTMASK_CH7OM_SHIFT (7U)
46678/*! CH7OM - Channel 7 Output Mask
46679 * 0b0..Channel output is not masked. It continues to operate normally.
46680 * 0b1..Channel output is masked. It is forced to its inactive state.
46681 */
46682#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
46683/*! @} */
46684
46685/*! @name COMBINE - Function For Linked Channels */
46686/*! @{ */
46687#define FTM_COMBINE_COMBINE0_MASK (0x1U)
46688#define FTM_COMBINE_COMBINE0_SHIFT (0U)
46689/*! COMBINE0 - Combine Channels For n = 0
46690 */
46691#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
46692#define FTM_COMBINE_COMP0_MASK (0x2U)
46693#define FTM_COMBINE_COMP0_SHIFT (1U)
46694/*! COMP0 - Complement Of Channel (n) For n = 0
46695 * 0b0..If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the channel (n+1) output
46696 * is the same as the channel (n) output. If the channel (n+1) is in Output Compare Mode, EPWM or CPWM, the
46697 * channel (n+1) output is independent from channel (n) output.
46698 * 0b1..The channel (n+1) output is the complement of the channel (n) output.
46699 */
46700#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
46701#define FTM_COMBINE_DECAPEN0_MASK (0x4U)
46702#define FTM_COMBINE_DECAPEN0_SHIFT (2U)
46703/*! DECAPEN0 - Dual Edge Capture Mode Enable For n = 0
46704 */
46705#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
46706#define FTM_COMBINE_DECAP0_MASK (0x8U)
46707#define FTM_COMBINE_DECAP0_SHIFT (3U)
46708/*! DECAP0 - Dual Edge Capture Mode Captures For n = 0
46709 * 0b0..The dual edge captures are inactive.
46710 * 0b1..The dual edge captures are active.
46711 */
46712#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
46713#define FTM_COMBINE_DTEN0_MASK (0x10U)
46714#define FTM_COMBINE_DTEN0_SHIFT (4U)
46715/*! DTEN0 - Deadtime Enable For n = 0
46716 * 0b0..The deadtime insertion in this pair of channels is disabled.
46717 * 0b1..The deadtime insertion in this pair of channels is enabled.
46718 */
46719#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
46720#define FTM_COMBINE_SYNCEN0_MASK (0x20U)
46721#define FTM_COMBINE_SYNCEN0_SHIFT (5U)
46722/*! SYNCEN0 - Synchronization Enable For n = 0
46723 * 0b0..The PWM synchronization in this pair of channels is disabled.
46724 * 0b1..The PWM synchronization in this pair of channels is enabled.
46725 */
46726#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
46727#define FTM_COMBINE_FAULTEN0_MASK (0x40U)
46728#define FTM_COMBINE_FAULTEN0_SHIFT (6U)
46729/*! FAULTEN0 - Fault Control Enable For n = 0
46730 * 0b0..The fault control in this pair of channels is disabled.
46731 * 0b1..The fault control in this pair of channels is enabled.
46732 */
46733#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
46734#define FTM_COMBINE_MCOMBINE0_MASK (0x80U)
46735#define FTM_COMBINE_MCOMBINE0_SHIFT (7U)
46736/*! MCOMBINE0 - Modified Combine Mode For n = 0
46737 */
46738#define FTM_COMBINE_MCOMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE0_SHIFT)) & FTM_COMBINE_MCOMBINE0_MASK)
46739#define FTM_COMBINE_COMBINE1_MASK (0x100U)
46740#define FTM_COMBINE_COMBINE1_SHIFT (8U)
46741/*! COMBINE1 - Combine Channels For n = 2
46742 */
46743#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
46744#define FTM_COMBINE_COMP1_MASK (0x200U)
46745#define FTM_COMBINE_COMP1_SHIFT (9U)
46746/*! COMP1 - Complement Of Channel (n) For n = 2
46747 * 0b0..If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the channel (n+1) output
46748 * is the same as the channel (n) output. If the channel (n+1) is in Output Compare Mode, EPWM or CPWM, the
46749 * channel (n+1) output is independent from channel (n) output.
46750 * 0b1..The channel (n+1) output is the complement of the channel (n) output.
46751 */
46752#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
46753#define FTM_COMBINE_DECAPEN1_MASK (0x400U)
46754#define FTM_COMBINE_DECAPEN1_SHIFT (10U)
46755/*! DECAPEN1 - Dual Edge Capture Mode Enable For n = 2
46756 */
46757#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
46758#define FTM_COMBINE_DECAP1_MASK (0x800U)
46759#define FTM_COMBINE_DECAP1_SHIFT (11U)
46760/*! DECAP1 - Dual Edge Capture Mode Captures For n = 2
46761 * 0b0..The dual edge captures are inactive.
46762 * 0b1..The dual edge captures are active.
46763 */
46764#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
46765#define FTM_COMBINE_DTEN1_MASK (0x1000U)
46766#define FTM_COMBINE_DTEN1_SHIFT (12U)
46767/*! DTEN1 - Deadtime Enable For n = 2
46768 * 0b0..The deadtime insertion in this pair of channels is disabled.
46769 * 0b1..The deadtime insertion in this pair of channels is enabled.
46770 */
46771#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
46772#define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
46773#define FTM_COMBINE_SYNCEN1_SHIFT (13U)
46774/*! SYNCEN1 - Synchronization Enable For n = 2
46775 * 0b0..The PWM synchronization in this pair of channels is disabled.
46776 * 0b1..The PWM synchronization in this pair of channels is enabled.
46777 */
46778#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
46779#define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
46780#define FTM_COMBINE_FAULTEN1_SHIFT (14U)
46781/*! FAULTEN1 - Fault Control Enable For n = 2
46782 * 0b0..The fault control in this pair of channels is disabled.
46783 * 0b1..The fault control in this pair of channels is enabled.
46784 */
46785#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
46786#define FTM_COMBINE_MCOMBINE1_MASK (0x8000U)
46787#define FTM_COMBINE_MCOMBINE1_SHIFT (15U)
46788/*! MCOMBINE1 - Modified Combine Mode For n = 2
46789 */
46790#define FTM_COMBINE_MCOMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE1_SHIFT)) & FTM_COMBINE_MCOMBINE1_MASK)
46791#define FTM_COMBINE_COMBINE2_MASK (0x10000U)
46792#define FTM_COMBINE_COMBINE2_SHIFT (16U)
46793/*! COMBINE2 - Combine Channels For n = 4
46794 */
46795#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
46796#define FTM_COMBINE_COMP2_MASK (0x20000U)
46797#define FTM_COMBINE_COMP2_SHIFT (17U)
46798/*! COMP2 - Complement Of Channel (n) For n = 4
46799 * 0b0..If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the channel (n+1) output
46800 * is the same as the channel (n) output. If the channel (n+1) is in Output Compare Mode, EPWM or CPWM, the
46801 * channel (n+1) output is independent from channel (n) output.
46802 * 0b1..The channel (n+1) output is the complement of the channel (n) output.
46803 */
46804#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
46805#define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
46806#define FTM_COMBINE_DECAPEN2_SHIFT (18U)
46807/*! DECAPEN2 - Dual Edge Capture Mode Enable For n = 4
46808 */
46809#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
46810#define FTM_COMBINE_DECAP2_MASK (0x80000U)
46811#define FTM_COMBINE_DECAP2_SHIFT (19U)
46812/*! DECAP2 - Dual Edge Capture Mode Captures For n = 4
46813 * 0b0..The dual edge captures are inactive.
46814 * 0b1..The dual edge captures are active.
46815 */
46816#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
46817#define FTM_COMBINE_DTEN2_MASK (0x100000U)
46818#define FTM_COMBINE_DTEN2_SHIFT (20U)
46819/*! DTEN2 - Deadtime Enable For n = 4
46820 * 0b0..The deadtime insertion in this pair of channels is disabled.
46821 * 0b1..The deadtime insertion in this pair of channels is enabled.
46822 */
46823#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
46824#define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
46825#define FTM_COMBINE_SYNCEN2_SHIFT (21U)
46826/*! SYNCEN2 - Synchronization Enable For n = 4
46827 * 0b0..The PWM synchronization in this pair of channels is disabled.
46828 * 0b1..The PWM synchronization in this pair of channels is enabled.
46829 */
46830#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
46831#define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
46832#define FTM_COMBINE_FAULTEN2_SHIFT (22U)
46833/*! FAULTEN2 - Fault Control Enable For n = 4
46834 * 0b0..The fault control in this pair of channels is disabled.
46835 * 0b1..The fault control in this pair of channels is enabled.
46836 */
46837#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
46838#define FTM_COMBINE_MCOMBINE2_MASK (0x800000U)
46839#define FTM_COMBINE_MCOMBINE2_SHIFT (23U)
46840/*! MCOMBINE2 - Modified Combine Mode For n = 4
46841 */
46842#define FTM_COMBINE_MCOMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE2_SHIFT)) & FTM_COMBINE_MCOMBINE2_MASK)
46843#define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
46844#define FTM_COMBINE_COMBINE3_SHIFT (24U)
46845/*! COMBINE3 - Combine Channels For n = 6
46846 */
46847#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
46848#define FTM_COMBINE_COMP3_MASK (0x2000000U)
46849#define FTM_COMBINE_COMP3_SHIFT (25U)
46850/*! COMP3 - Complement Of Channel (n) for n = 6
46851 * 0b0..If the channels (n) and (n+1) are in Combine Mode or Modified Combine PWM Mode, the channel (n+1) output
46852 * is the same as the channel (n) output. If the channel (n+1) is in Output Compare Mode, EPWM or CPWM, the
46853 * channel (n+1) output is independent from channel (n) output.
46854 * 0b1..The channel (n+1) output is the complement of the channel (n) output.
46855 */
46856#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
46857#define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
46858#define FTM_COMBINE_DECAPEN3_SHIFT (26U)
46859/*! DECAPEN3 - Dual Edge Capture Mode Enable For n = 6
46860 */
46861#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
46862#define FTM_COMBINE_DECAP3_MASK (0x8000000U)
46863#define FTM_COMBINE_DECAP3_SHIFT (27U)
46864/*! DECAP3 - Dual Edge Capture Mode Captures For n = 6
46865 * 0b0..The dual edge captures are inactive.
46866 * 0b1..The dual edge captures are active.
46867 */
46868#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
46869#define FTM_COMBINE_DTEN3_MASK (0x10000000U)
46870#define FTM_COMBINE_DTEN3_SHIFT (28U)
46871/*! DTEN3 - Deadtime Enable For n = 6
46872 * 0b0..The deadtime insertion in this pair of channels is disabled.
46873 * 0b1..The deadtime insertion in this pair of channels is enabled.
46874 */
46875#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
46876#define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
46877#define FTM_COMBINE_SYNCEN3_SHIFT (29U)
46878/*! SYNCEN3 - Synchronization Enable For n = 6
46879 * 0b0..The PWM synchronization in this pair of channels is disabled.
46880 * 0b1..The PWM synchronization in this pair of channels is enabled.
46881 */
46882#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
46883#define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
46884#define FTM_COMBINE_FAULTEN3_SHIFT (30U)
46885/*! FAULTEN3 - Fault Control Enable For n = 6
46886 * 0b0..The fault control in this pair of channels is disabled.
46887 * 0b1..The fault control in this pair of channels is enabled.
46888 */
46889#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
46890#define FTM_COMBINE_MCOMBINE3_MASK (0x80000000U)
46891#define FTM_COMBINE_MCOMBINE3_SHIFT (31U)
46892/*! MCOMBINE3 - Modified Combine Mode For n = 6
46893 */
46894#define FTM_COMBINE_MCOMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_MCOMBINE3_SHIFT)) & FTM_COMBINE_MCOMBINE3_MASK)
46895/*! @} */
46896
46897/*! @name DEADTIME - Deadtime Configuration */
46898/*! @{ */
46899#define FTM_DEADTIME_DTVAL_MASK (0x3FU)
46900#define FTM_DEADTIME_DTVAL_SHIFT (0U)
46901/*! DTVAL - Deadtime Value
46902 */
46903#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
46904#define FTM_DEADTIME_DTPS_MASK (0xC0U)
46905#define FTM_DEADTIME_DTPS_SHIFT (6U)
46906/*! DTPS - Deadtime Prescaler Value
46907 * 0b0x..Divide the FTM input clock by 1.
46908 * 0b10..Divide the FTM input clock by 4.
46909 * 0b11..Divide the FTM input clock by 16.
46910 */
46911#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
46912#define FTM_DEADTIME_DTVALEX_MASK (0xF0000U)
46913#define FTM_DEADTIME_DTVALEX_SHIFT (16U)
46914/*! DTVALEX - Extended Deadtime Value
46915 */
46916#define FTM_DEADTIME_DTVALEX(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVALEX_SHIFT)) & FTM_DEADTIME_DTVALEX_MASK)
46917/*! @} */
46918
46919/*! @name EXTTRIG - FTM External Trigger */
46920/*! @{ */
46921#define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
46922#define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
46923/*! CH2TRIG - Channel 2 External Trigger Enable
46924 * 0b0..The generation of this external trigger is disabled.
46925 * 0b1..The generation of this external trigger is enabled.
46926 */
46927#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
46928#define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
46929#define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
46930/*! CH3TRIG - Channel 3 External Trigger Enable
46931 * 0b0..The generation of this external trigger is disabled.
46932 * 0b1..The generation of this external trigger is enabled.
46933 */
46934#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
46935#define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
46936#define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
46937/*! CH4TRIG - Channel 4 External Trigger Enable
46938 * 0b0..The generation of this external trigger is disabled.
46939 * 0b1..The generation of this external trigger is enabled.
46940 */
46941#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
46942#define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
46943#define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
46944/*! CH5TRIG - Channel 5 External Trigger Enable
46945 * 0b0..The generation of this external trigger is disabled.
46946 * 0b1..The generation of this external trigger is enabled.
46947 */
46948#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
46949#define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
46950#define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
46951/*! CH0TRIG - Channel 0 External Trigger Enable
46952 * 0b0..The generation of this external trigger is disabled.
46953 * 0b1..The generation of this external trigger is enabled.
46954 */
46955#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
46956#define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
46957#define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
46958/*! CH1TRIG - Channel 1 External Trigger Enable
46959 * 0b0..The generation of this external trigger is disabled.
46960 * 0b1..The generation of this external trigger is enabled.
46961 */
46962#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
46963#define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
46964#define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
46965/*! INITTRIGEN - Initialization Trigger Enable
46966 * 0b0..The generation of initialization trigger is disabled.
46967 * 0b1..The generation of initialization trigger is enabled.
46968 */
46969#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
46970#define FTM_EXTTRIG_TRIGF_MASK (0x80U)
46971#define FTM_EXTTRIG_TRIGF_SHIFT (7U)
46972/*! TRIGF - Channel Trigger Flag
46973 * 0b0..No channel trigger was generated.
46974 * 0b1..A channel trigger was generated.
46975 */
46976#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
46977#define FTM_EXTTRIG_CH6TRIG_MASK (0x100U)
46978#define FTM_EXTTRIG_CH6TRIG_SHIFT (8U)
46979/*! CH6TRIG - Channel 6 External Trigger Enable
46980 * 0b0..The generation of this external trigger is disabled.
46981 * 0b1..The generation of this external trigger is enabled.
46982 */
46983#define FTM_EXTTRIG_CH6TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH6TRIG_SHIFT)) & FTM_EXTTRIG_CH6TRIG_MASK)
46984#define FTM_EXTTRIG_CH7TRIG_MASK (0x200U)
46985#define FTM_EXTTRIG_CH7TRIG_SHIFT (9U)
46986/*! CH7TRIG - Channel 7 External Trigger Enable
46987 * 0b0..The generation of this external trigger is disabled.
46988 * 0b1..The generation of this external trigger is enabled.
46989 */
46990#define FTM_EXTTRIG_CH7TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH7TRIG_SHIFT)) & FTM_EXTTRIG_CH7TRIG_MASK)
46991/*! @} */
46992
46993/*! @name POL - Channels Polarity */
46994/*! @{ */
46995#define FTM_POL_POL0_MASK (0x1U)
46996#define FTM_POL_POL0_SHIFT (0U)
46997/*! POL0 - Channel 0 Polarity
46998 * 0b0..The channel polarity is active high.
46999 * 0b1..The channel polarity is active low.
47000 */
47001#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
47002#define FTM_POL_POL1_MASK (0x2U)
47003#define FTM_POL_POL1_SHIFT (1U)
47004/*! POL1 - Channel 1 Polarity
47005 * 0b0..The channel polarity is active high.
47006 * 0b1..The channel polarity is active low.
47007 */
47008#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
47009#define FTM_POL_POL2_MASK (0x4U)
47010#define FTM_POL_POL2_SHIFT (2U)
47011/*! POL2 - Channel 2 Polarity
47012 * 0b0..The channel polarity is active high.
47013 * 0b1..The channel polarity is active low.
47014 */
47015#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
47016#define FTM_POL_POL3_MASK (0x8U)
47017#define FTM_POL_POL3_SHIFT (3U)
47018/*! POL3 - Channel 3 Polarity
47019 * 0b0..The channel polarity is active high.
47020 * 0b1..The channel polarity is active low.
47021 */
47022#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
47023#define FTM_POL_POL4_MASK (0x10U)
47024#define FTM_POL_POL4_SHIFT (4U)
47025/*! POL4 - Channel 4 Polarity
47026 * 0b0..The channel polarity is active high.
47027 * 0b1..The channel polarity is active low.
47028 */
47029#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
47030#define FTM_POL_POL5_MASK (0x20U)
47031#define FTM_POL_POL5_SHIFT (5U)
47032/*! POL5 - Channel 5 Polarity
47033 * 0b0..The channel polarity is active high.
47034 * 0b1..The channel polarity is active low.
47035 */
47036#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
47037#define FTM_POL_POL6_MASK (0x40U)
47038#define FTM_POL_POL6_SHIFT (6U)
47039/*! POL6 - Channel 6 Polarity
47040 * 0b0..The channel polarity is active high.
47041 * 0b1..The channel polarity is active low.
47042 */
47043#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
47044#define FTM_POL_POL7_MASK (0x80U)
47045#define FTM_POL_POL7_SHIFT (7U)
47046/*! POL7 - Channel 7 Polarity
47047 * 0b0..The channel polarity is active high.
47048 * 0b1..The channel polarity is active low.
47049 */
47050#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
47051/*! @} */
47052
47053/*! @name FMS - Fault Mode Status */
47054/*! @{ */
47055#define FTM_FMS_FAULTF0_MASK (0x1U)
47056#define FTM_FMS_FAULTF0_SHIFT (0U)
47057/*! FAULTF0 - Fault Detection Flag 0
47058 * 0b0..No fault condition was detected at the fault input.
47059 * 0b1..A fault condition was detected at the fault input.
47060 */
47061#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
47062#define FTM_FMS_FAULTF1_MASK (0x2U)
47063#define FTM_FMS_FAULTF1_SHIFT (1U)
47064/*! FAULTF1 - Fault Detection Flag 1
47065 * 0b0..No fault condition was detected at the fault input.
47066 * 0b1..A fault condition was detected at the fault input.
47067 */
47068#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
47069#define FTM_FMS_FAULTF2_MASK (0x4U)
47070#define FTM_FMS_FAULTF2_SHIFT (2U)
47071/*! FAULTF2 - Fault Detection Flag 2
47072 * 0b0..No fault condition was detected at the fault input.
47073 * 0b1..A fault condition was detected at the fault input.
47074 */
47075#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
47076#define FTM_FMS_FAULTF3_MASK (0x8U)
47077#define FTM_FMS_FAULTF3_SHIFT (3U)
47078/*! FAULTF3 - Fault Detection Flag 3
47079 * 0b0..No fault condition was detected at the fault input.
47080 * 0b1..A fault condition was detected at the fault input.
47081 */
47082#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
47083#define FTM_FMS_FAULTIN_MASK (0x20U)
47084#define FTM_FMS_FAULTIN_SHIFT (5U)
47085/*! FAULTIN - Fault Inputs
47086 * 0b0..The logic OR of the enabled fault inputs is 0.
47087 * 0b1..The logic OR of the enabled fault inputs is 1.
47088 */
47089#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
47090#define FTM_FMS_WPEN_MASK (0x40U)
47091#define FTM_FMS_WPEN_SHIFT (6U)
47092/*! WPEN - Write Protection Enable
47093 * 0b0..Write protection is disabled. Write protected bits can be written.
47094 * 0b1..Write protection is enabled. Write protected bits cannot be written.
47095 */
47096#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
47097#define FTM_FMS_FAULTF_MASK (0x80U)
47098#define FTM_FMS_FAULTF_SHIFT (7U)
47099/*! FAULTF - Fault Detection Flag
47100 * 0b0..No fault condition was detected.
47101 * 0b1..A fault condition was detected.
47102 */
47103#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
47104/*! @} */
47105
47106/*! @name FILTER - Input Capture Filter Control */
47107/*! @{ */
47108#define FTM_FILTER_CH0FVAL_MASK (0xFU)
47109#define FTM_FILTER_CH0FVAL_SHIFT (0U)
47110/*! CH0FVAL - Channel 0 Input Filter
47111 */
47112#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
47113#define FTM_FILTER_CH1FVAL_MASK (0xF0U)
47114#define FTM_FILTER_CH1FVAL_SHIFT (4U)
47115/*! CH1FVAL - Channel 1 Input Filter
47116 */
47117#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
47118#define FTM_FILTER_CH2FVAL_MASK (0xF00U)
47119#define FTM_FILTER_CH2FVAL_SHIFT (8U)
47120/*! CH2FVAL - Channel 2 Input Filter
47121 */
47122#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
47123#define FTM_FILTER_CH3FVAL_MASK (0xF000U)
47124#define FTM_FILTER_CH3FVAL_SHIFT (12U)
47125/*! CH3FVAL - Channel 3 Input Filter
47126 */
47127#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
47128/*! @} */
47129
47130/*! @name FLTCTRL - Fault Control */
47131/*! @{ */
47132#define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
47133#define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
47134/*! FAULT0EN - Fault Input 0 Enable
47135 * 0b0..Fault input is disabled.
47136 * 0b1..Fault input is enabled.
47137 */
47138#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
47139#define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
47140#define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
47141/*! FAULT1EN - Fault Input 1 Enable
47142 * 0b0..Fault input is disabled.
47143 * 0b1..Fault input is enabled.
47144 */
47145#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
47146#define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
47147#define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
47148/*! FAULT2EN - Fault Input 2 Enable
47149 * 0b0..Fault input is disabled.
47150 * 0b1..Fault input is enabled.
47151 */
47152#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
47153#define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
47154#define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
47155/*! FAULT3EN - Fault Input 3 Enable
47156 * 0b0..Fault input is disabled.
47157 * 0b1..Fault input is enabled.
47158 */
47159#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
47160#define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
47161#define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
47162/*! FFLTR0EN - Fault Input 0 Filter Enable
47163 * 0b0..Fault input filter is disabled.
47164 * 0b1..Fault input filter is enabled.
47165 */
47166#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
47167#define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
47168#define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
47169/*! FFLTR1EN - Fault Input 1 Filter Enable
47170 * 0b0..Fault input filter is disabled.
47171 * 0b1..Fault input filter is enabled.
47172 */
47173#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
47174#define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
47175#define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
47176/*! FFLTR2EN - Fault Input 2 Filter Enable
47177 * 0b0..Fault input filter is disabled.
47178 * 0b1..Fault input filter is enabled.
47179 */
47180#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
47181#define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
47182#define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
47183/*! FFLTR3EN - Fault Input 3 Filter Enable
47184 * 0b0..Fault input filter is disabled.
47185 * 0b1..Fault input filter is enabled.
47186 */
47187#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
47188#define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
47189#define FTM_FLTCTRL_FFVAL_SHIFT (8U)
47190/*! FFVAL - Fault Input Filter
47191 */
47192#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
47193#define FTM_FLTCTRL_FSTATE_MASK (0x8000U)
47194#define FTM_FLTCTRL_FSTATE_SHIFT (15U)
47195/*! FSTATE - Fault output state
47196 * 0b0..FTM outputs will be placed into safe values when fault events in ongoing (defined by POL bits).
47197 * 0b1..FTM outputs will be tri-stated when fault event is ongoing
47198 */
47199#define FTM_FLTCTRL_FSTATE(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FSTATE_SHIFT)) & FTM_FLTCTRL_FSTATE_MASK)
47200/*! @} */
47201
47202/*! @name QDCTRL - Quadrature Decoder Control And Status */
47203/*! @{ */
47204#define FTM_QDCTRL_QUADEN_MASK (0x1U)
47205#define FTM_QDCTRL_QUADEN_SHIFT (0U)
47206/*! QUADEN - Quadrature Decoder Mode Enable
47207 * 0b0..Quadrature Decoder mode is disabled.
47208 * 0b1..Quadrature Decoder mode is enabled.
47209 */
47210#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
47211#define FTM_QDCTRL_TOFDIR_MASK (0x2U)
47212#define FTM_QDCTRL_TOFDIR_SHIFT (1U)
47213/*! TOFDIR - Timer Overflow Direction In Quadrature Decoder Mode
47214 * 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes
47215 * from its minimum value (CNTIN register) to its maximum value (MOD register).
47216 * 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from
47217 * its maximum value (MOD register) to its minimum value (CNTIN register).
47218 */
47219#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
47220#define FTM_QDCTRL_QUADIR_MASK (0x4U)
47221#define FTM_QDCTRL_QUADIR_SHIFT (2U)
47222/*! QUADIR - FTM Counter Direction In Quadrature Decoder Mode
47223 * 0b0..Counting direction is decreasing (FTM counter decrement).
47224 * 0b1..Counting direction is increasing (FTM counter increment).
47225 */
47226#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
47227#define FTM_QDCTRL_QUADMODE_MASK (0x8U)
47228#define FTM_QDCTRL_QUADMODE_SHIFT (3U)
47229/*! QUADMODE - Quadrature Decoder Mode
47230 * 0b0..Phase A and phase B encoding mode.
47231 * 0b1..Count and direction encoding mode.
47232 */
47233#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
47234#define FTM_QDCTRL_PHBPOL_MASK (0x10U)
47235#define FTM_QDCTRL_PHBPOL_SHIFT (4U)
47236/*! PHBPOL - Phase B Input Polarity
47237 * 0b0..Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.
47238 * 0b1..Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.
47239 */
47240#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
47241#define FTM_QDCTRL_PHAPOL_MASK (0x20U)
47242#define FTM_QDCTRL_PHAPOL_SHIFT (5U)
47243/*! PHAPOL - Phase A Input Polarity
47244 * 0b0..Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.
47245 * 0b1..Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.
47246 */
47247#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
47248#define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
47249#define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
47250/*! PHBFLTREN - Phase B Input Filter Enable
47251 * 0b0..Phase B input filter is disabled.
47252 * 0b1..Phase B input filter is enabled.
47253 */
47254#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
47255#define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
47256#define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
47257/*! PHAFLTREN - Phase A Input Filter Enable
47258 * 0b0..Phase A input filter is disabled.
47259 * 0b1..Phase A input filter is enabled.
47260 */
47261#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
47262/*! @} */
47263
47264/*! @name CONF - Configuration */
47265/*! @{ */
47266#define FTM_CONF_LDFQ_MASK (0x1FU)
47267#define FTM_CONF_LDFQ_SHIFT (0U)
47268/*! LDFQ - Frequency of the Reload Opportunities
47269 */
47270#define FTM_CONF_LDFQ(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_LDFQ_SHIFT)) & FTM_CONF_LDFQ_MASK)
47271#define FTM_CONF_BDMMODE_MASK (0xC0U)
47272#define FTM_CONF_BDMMODE_SHIFT (6U)
47273/*! BDMMODE - BDM Mode
47274 */
47275#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
47276#define FTM_CONF_GTBEEN_MASK (0x200U)
47277#define FTM_CONF_GTBEEN_SHIFT (9U)
47278/*! GTBEEN - Global Time Base Enable
47279 * 0b0..Use of an external global time base is disabled.
47280 * 0b1..Use of an external global time base is enabled.
47281 */
47282#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
47283#define FTM_CONF_GTBEOUT_MASK (0x400U)
47284#define FTM_CONF_GTBEOUT_SHIFT (10U)
47285/*! GTBEOUT - Global Time Base Output
47286 * 0b0..A global time base signal generation is disabled.
47287 * 0b1..A global time base signal generation is enabled.
47288 */
47289#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
47290#define FTM_CONF_ITRIGR_MASK (0x800U)
47291#define FTM_CONF_ITRIGR_SHIFT (11U)
47292/*! ITRIGR - Initialization trigger on Reload Point
47293 * 0b0..Initialization trigger is generated on counter wrap events.
47294 * 0b1..Initialization trigger is generated when a reload point is reached.
47295 */
47296#define FTM_CONF_ITRIGR(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_ITRIGR_SHIFT)) & FTM_CONF_ITRIGR_MASK)
47297/*! @} */
47298
47299/*! @name FLTPOL - FTM Fault Input Polarity */
47300/*! @{ */
47301#define FTM_FLTPOL_FLT0POL_MASK (0x1U)
47302#define FTM_FLTPOL_FLT0POL_SHIFT (0U)
47303/*! FLT0POL - Fault Input 0 Polarity
47304 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
47305 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
47306 */
47307#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
47308#define FTM_FLTPOL_FLT1POL_MASK (0x2U)
47309#define FTM_FLTPOL_FLT1POL_SHIFT (1U)
47310/*! FLT1POL - Fault Input 1 Polarity
47311 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
47312 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
47313 */
47314#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
47315#define FTM_FLTPOL_FLT2POL_MASK (0x4U)
47316#define FTM_FLTPOL_FLT2POL_SHIFT (2U)
47317/*! FLT2POL - Fault Input 2 Polarity
47318 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
47319 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
47320 */
47321#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
47322#define FTM_FLTPOL_FLT3POL_MASK (0x8U)
47323#define FTM_FLTPOL_FLT3POL_SHIFT (3U)
47324/*! FLT3POL - Fault Input 3 Polarity
47325 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
47326 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
47327 */
47328#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
47329/*! @} */
47330
47331/*! @name SYNCONF - Synchronization Configuration */
47332/*! @{ */
47333#define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
47334#define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
47335/*! HWTRIGMODE - Hardware Trigger Mode
47336 * 0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
47337 * 0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
47338 */
47339#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
47340#define FTM_SYNCONF_CNTINC_MASK (0x4U)
47341#define FTM_SYNCONF_CNTINC_SHIFT (2U)
47342/*! CNTINC - CNTIN Register Synchronization
47343 * 0b0..CNTIN register is updated with its buffer value at all rising edges of FTM input clock.
47344 * 0b1..CNTIN register is updated with its buffer value by the PWM synchronization.
47345 */
47346#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
47347#define FTM_SYNCONF_INVC_MASK (0x10U)
47348#define FTM_SYNCONF_INVC_SHIFT (4U)
47349/*! INVC - INVCTRL Register Synchronization
47350 * 0b0..INVCTRL register is updated with its buffer value at all rising edges of FTM input clock.
47351 * 0b1..INVCTRL register is updated with its buffer value by the PWM synchronization.
47352 */
47353#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
47354#define FTM_SYNCONF_SWOC_MASK (0x20U)
47355#define FTM_SYNCONF_SWOC_SHIFT (5U)
47356/*! SWOC - SWOCTRL Register Synchronization
47357 * 0b0..SWOCTRL register is updated with its buffer value at all rising edges of FTM input clock.
47358 * 0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization.
47359 */
47360#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
47361#define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
47362#define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
47363/*! SYNCMODE - Synchronization Mode
47364 * 0b0..Legacy PWM synchronization is selected.
47365 * 0b1..Enhanced PWM synchronization is selected.
47366 */
47367#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
47368#define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
47369#define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
47370/*! SWRSTCNT - FTM counter synchronization is activated by the software trigger
47371 * 0b0..The software trigger does not activate the FTM counter synchronization.
47372 * 0b1..The software trigger activates the FTM counter synchronization.
47373 */
47374#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
47375#define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
47376#define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
47377/*! SWWRBUF - MOD, HCR, CNTIN, and CV registers synchronization is activated by the software trigger
47378 * 0b0..The software trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization.
47379 * 0b1..The software trigger activates MOD, HCR, CNTIN, and CV registers synchronization.
47380 */
47381#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
47382#define FTM_SYNCONF_SWOM_MASK (0x400U)
47383#define FTM_SYNCONF_SWOM_SHIFT (10U)
47384/*! SWOM - Output mask synchronization is activated by the software trigger
47385 * 0b0..The software trigger does not activate the OUTMASK register synchronization.
47386 * 0b1..The software trigger activates the OUTMASK register synchronization.
47387 */
47388#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
47389#define FTM_SYNCONF_SWINVC_MASK (0x800U)
47390#define FTM_SYNCONF_SWINVC_SHIFT (11U)
47391/*! SWINVC - Inverting control synchronization is activated by the software trigger
47392 * 0b0..The software trigger does not activate the INVCTRL register synchronization.
47393 * 0b1..The software trigger activates the INVCTRL register synchronization.
47394 */
47395#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
47396#define FTM_SYNCONF_SWSOC_MASK (0x1000U)
47397#define FTM_SYNCONF_SWSOC_SHIFT (12U)
47398/*! SWSOC - Software output control synchronization is activated by the software trigger
47399 * 0b0..The software trigger does not activate the SWOCTRL register synchronization.
47400 * 0b1..The software trigger activates the SWOCTRL register synchronization.
47401 */
47402#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
47403#define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
47404#define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
47405/*! HWRSTCNT - FTM counter synchronization is activated by a hardware trigger
47406 * 0b0..A hardware trigger does not activate the FTM counter synchronization.
47407 * 0b1..A hardware trigger activates the FTM counter synchronization.
47408 */
47409#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
47410#define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
47411#define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
47412/*! HWWRBUF - MOD, HCR, CNTIN, and CV registers synchronization is activated by a hardware trigger
47413 * 0b0..A hardware trigger does not activate MOD, HCR, CNTIN, and CV registers synchronization.
47414 * 0b1..A hardware trigger activates MOD, HCR, CNTIN, and CV registers synchronization.
47415 */
47416#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
47417#define FTM_SYNCONF_HWOM_MASK (0x40000U)
47418#define FTM_SYNCONF_HWOM_SHIFT (18U)
47419/*! HWOM - Output mask synchronization is activated by a hardware trigger
47420 * 0b0..A hardware trigger does not activate the OUTMASK register synchronization.
47421 * 0b1..A hardware trigger activates the OUTMASK register synchronization.
47422 */
47423#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
47424#define FTM_SYNCONF_HWINVC_MASK (0x80000U)
47425#define FTM_SYNCONF_HWINVC_SHIFT (19U)
47426/*! HWINVC - Inverting control synchronization is activated by a hardware trigger
47427 * 0b0..A hardware trigger does not activate the INVCTRL register synchronization.
47428 * 0b1..A hardware trigger activates the INVCTRL register synchronization.
47429 */
47430#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
47431#define FTM_SYNCONF_HWSOC_MASK (0x100000U)
47432#define FTM_SYNCONF_HWSOC_SHIFT (20U)
47433/*! HWSOC - Software output control synchronization is activated by a hardware trigger
47434 * 0b0..A hardware trigger does not activate the SWOCTRL register synchronization.
47435 * 0b1..A hardware trigger activates the SWOCTRL register synchronization.
47436 */
47437#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
47438/*! @} */
47439
47440/*! @name INVCTRL - FTM Inverting Control */
47441/*! @{ */
47442#define FTM_INVCTRL_INV0EN_MASK (0x1U)
47443#define FTM_INVCTRL_INV0EN_SHIFT (0U)
47444/*! INV0EN - Pair Channels 0 Inverting Enable
47445 * 0b0..Inverting is disabled.
47446 * 0b1..Inverting is enabled.
47447 */
47448#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
47449#define FTM_INVCTRL_INV1EN_MASK (0x2U)
47450#define FTM_INVCTRL_INV1EN_SHIFT (1U)
47451/*! INV1EN - Pair Channels 1 Inverting Enable
47452 * 0b0..Inverting is disabled.
47453 * 0b1..Inverting is enabled.
47454 */
47455#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
47456#define FTM_INVCTRL_INV2EN_MASK (0x4U)
47457#define FTM_INVCTRL_INV2EN_SHIFT (2U)
47458/*! INV2EN - Pair Channels 2 Inverting Enable
47459 * 0b0..Inverting is disabled.
47460 * 0b1..Inverting is enabled.
47461 */
47462#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
47463#define FTM_INVCTRL_INV3EN_MASK (0x8U)
47464#define FTM_INVCTRL_INV3EN_SHIFT (3U)
47465/*! INV3EN - Pair Channels 3 Inverting Enable
47466 * 0b0..Inverting is disabled.
47467 * 0b1..Inverting is enabled.
47468 */
47469#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
47470/*! @} */
47471
47472/*! @name SWOCTRL - FTM Software Output Control */
47473/*! @{ */
47474#define FTM_SWOCTRL_CH0OC_MASK (0x1U)
47475#define FTM_SWOCTRL_CH0OC_SHIFT (0U)
47476/*! CH0OC - Channel 0 Software Output Control Enable
47477 * 0b0..The channel output is not affected by software output control.
47478 * 0b1..The channel output is affected by software output control.
47479 */
47480#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
47481#define FTM_SWOCTRL_CH1OC_MASK (0x2U)
47482#define FTM_SWOCTRL_CH1OC_SHIFT (1U)
47483/*! CH1OC - Channel 1 Software Output Control Enable
47484 * 0b0..The channel output is not affected by software output control.
47485 * 0b1..The channel output is affected by software output control.
47486 */
47487#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
47488#define FTM_SWOCTRL_CH2OC_MASK (0x4U)
47489#define FTM_SWOCTRL_CH2OC_SHIFT (2U)
47490/*! CH2OC - Channel 2 Software Output Control Enable
47491 * 0b0..The channel output is not affected by software output control.
47492 * 0b1..The channel output is affected by software output control.
47493 */
47494#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
47495#define FTM_SWOCTRL_CH3OC_MASK (0x8U)
47496#define FTM_SWOCTRL_CH3OC_SHIFT (3U)
47497/*! CH3OC - Channel 3 Software Output Control Enable
47498 * 0b0..The channel output is not affected by software output control.
47499 * 0b1..The channel output is affected by software output control.
47500 */
47501#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
47502#define FTM_SWOCTRL_CH4OC_MASK (0x10U)
47503#define FTM_SWOCTRL_CH4OC_SHIFT (4U)
47504/*! CH4OC - Channel 4 Software Output Control Enable
47505 * 0b0..The channel output is not affected by software output control.
47506 * 0b1..The channel output is affected by software output control.
47507 */
47508#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
47509#define FTM_SWOCTRL_CH5OC_MASK (0x20U)
47510#define FTM_SWOCTRL_CH5OC_SHIFT (5U)
47511/*! CH5OC - Channel 5 Software Output Control Enable
47512 * 0b0..The channel output is not affected by software output control.
47513 * 0b1..The channel output is affected by software output control.
47514 */
47515#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
47516#define FTM_SWOCTRL_CH6OC_MASK (0x40U)
47517#define FTM_SWOCTRL_CH6OC_SHIFT (6U)
47518/*! CH6OC - Channel 6 Software Output Control Enable
47519 * 0b0..The channel output is not affected by software output control.
47520 * 0b1..The channel output is affected by software output control.
47521 */
47522#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
47523#define FTM_SWOCTRL_CH7OC_MASK (0x80U)
47524#define FTM_SWOCTRL_CH7OC_SHIFT (7U)
47525/*! CH7OC - Channel 7 Software Output Control Enable
47526 * 0b0..The channel output is not affected by software output control.
47527 * 0b1..The channel output is affected by software output control.
47528 */
47529#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
47530#define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
47531#define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
47532/*! CH0OCV - Channel 0 Software Output Control Value
47533 * 0b0..The software output control forces 0 to the channel output.
47534 * 0b1..The software output control forces 1 to the channel output.
47535 */
47536#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
47537#define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
47538#define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
47539/*! CH1OCV - Channel 1 Software Output Control Value
47540 * 0b0..The software output control forces 0 to the channel output.
47541 * 0b1..The software output control forces 1 to the channel output.
47542 */
47543#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
47544#define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
47545#define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
47546/*! CH2OCV - Channel 2 Software Output Control Value
47547 * 0b0..The software output control forces 0 to the channel output.
47548 * 0b1..The software output control forces 1 to the channel output.
47549 */
47550#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
47551#define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
47552#define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
47553/*! CH3OCV - Channel 3 Software Output Control Value
47554 * 0b0..The software output control forces 0 to the channel output.
47555 * 0b1..The software output control forces 1 to the channel output.
47556 */
47557#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
47558#define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
47559#define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
47560/*! CH4OCV - Channel 4 Software Output Control Value
47561 * 0b0..The software output control forces 0 to the channel output.
47562 * 0b1..The software output control forces 1 to the channel output.
47563 */
47564#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
47565#define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
47566#define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
47567/*! CH5OCV - Channel 5 Software Output Control Value
47568 * 0b0..The software output control forces 0 to the channel output.
47569 * 0b1..The software output control forces 1 to the channel output.
47570 */
47571#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
47572#define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
47573#define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
47574/*! CH6OCV - Channel 6 Software Output Control Value
47575 * 0b0..The software output control forces 0 to the channel output.
47576 * 0b1..The software output control forces 1 to the channel output.
47577 */
47578#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
47579#define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
47580#define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
47581/*! CH7OCV - Channel 7 Software Output Control Value
47582 * 0b0..The software output control forces 0 to the channel output.
47583 * 0b1..The software output control forces 1 to the channel output.
47584 */
47585#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
47586/*! @} */
47587
47588/*! @name PWMLOAD - FTM PWM Load */
47589/*! @{ */
47590#define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
47591#define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
47592/*! CH0SEL - Channel 0 Select
47593 * 0b0..Channel match is not included as a reload opportunity.
47594 * 0b1..Channel match is included as a reload opportunity.
47595 */
47596#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
47597#define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
47598#define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
47599/*! CH1SEL - Channel 1 Select
47600 * 0b0..Channel match is not included as a reload opportunity.
47601 * 0b1..Channel match is included as a reload opportunity.
47602 */
47603#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
47604#define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
47605#define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
47606/*! CH2SEL - Channel 2 Select
47607 * 0b0..Channel match is not included as a reload opportunity.
47608 * 0b1..Channel match is included as a reload opportunity.
47609 */
47610#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
47611#define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
47612#define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
47613/*! CH3SEL - Channel 3 Select
47614 * 0b0..Channel match is not included as a reload opportunity.
47615 * 0b1..Channel match is included as a reload opportunity.
47616 */
47617#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
47618#define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
47619#define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
47620/*! CH4SEL - Channel 4 Select
47621 * 0b0..Channel match is not included as a reload opportunity.
47622 * 0b1..Channel match is included as a reload opportunity.
47623 */
47624#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
47625#define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
47626#define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
47627/*! CH5SEL - Channel 5 Select
47628 * 0b0..Channel match is not included as a reload opportunity.
47629 * 0b1..Channel match is included as a reload opportunity.
47630 */
47631#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
47632#define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
47633#define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
47634/*! CH6SEL - Channel 6 Select
47635 * 0b0..Channel match is not included as a reload opportunity.
47636 * 0b1..Channel match is included as a reload opportunity.
47637 */
47638#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
47639#define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
47640#define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
47641/*! CH7SEL - Channel 7 Select
47642 * 0b0..Channel match is not included as a reload opportunity.
47643 * 0b1..Channel match is included as a reload opportunity.
47644 */
47645#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
47646#define FTM_PWMLOAD_HCSEL_MASK (0x100U)
47647#define FTM_PWMLOAD_HCSEL_SHIFT (8U)
47648/*! HCSEL - Half Cycle Select
47649 * 0b0..Half cycle reload is disabled and it is not considered as a reload opportunity.
47650 * 0b1..Half cycle reload is enabled and it is considered as a reload opportunity.
47651 */
47652#define FTM_PWMLOAD_HCSEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_HCSEL_SHIFT)) & FTM_PWMLOAD_HCSEL_MASK)
47653#define FTM_PWMLOAD_LDOK_MASK (0x200U)
47654#define FTM_PWMLOAD_LDOK_SHIFT (9U)
47655/*! LDOK - Load Enable
47656 * 0b0..Loading updated values is disabled.
47657 * 0b1..Loading updated values is enabled.
47658 */
47659#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
47660#define FTM_PWMLOAD_GLEN_MASK (0x400U)
47661#define FTM_PWMLOAD_GLEN_SHIFT (10U)
47662/*! GLEN - Global Load Enable
47663 * 0b0..Global Load Ok disabled.
47664 * 0b1..Global Load OK enabled. A pulse event on the module global load input sets the LDOK bit.
47665 */
47666#define FTM_PWMLOAD_GLEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_GLEN_SHIFT)) & FTM_PWMLOAD_GLEN_MASK)
47667#define FTM_PWMLOAD_GLDOK_MASK (0x800U)
47668#define FTM_PWMLOAD_GLDOK_SHIFT (11U)
47669/*! GLDOK - Global Load OK
47670 * 0b0..No action.
47671 * 0b1..LDOK bit is set.
47672 */
47673#define FTM_PWMLOAD_GLDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_GLDOK_SHIFT)) & FTM_PWMLOAD_GLDOK_MASK)
47674/*! @} */
47675
47676/*! @name HCR - Half Cycle Register */
47677/*! @{ */
47678#define FTM_HCR_HCVAL_MASK (0xFFFFU)
47679#define FTM_HCR_HCVAL_SHIFT (0U)
47680/*! HCVAL - Half Cycle Value
47681 */
47682#define FTM_HCR_HCVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_HCR_HCVAL_SHIFT)) & FTM_HCR_HCVAL_MASK)
47683/*! @} */
47684
47685/*! @name MOD_MIRROR - Mirror of Modulo Value */
47686/*! @{ */
47687#define FTM_MOD_MIRROR_FRACMOD_MASK (0xF800U)
47688#define FTM_MOD_MIRROR_FRACMOD_SHIFT (11U)
47689/*! FRACMOD - Modulo Fractional Value
47690 */
47691#define FTM_MOD_MIRROR_FRACMOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MIRROR_FRACMOD_SHIFT)) & FTM_MOD_MIRROR_FRACMOD_MASK)
47692#define FTM_MOD_MIRROR_MOD_MASK (0xFFFF0000U)
47693#define FTM_MOD_MIRROR_MOD_SHIFT (16U)
47694/*! MOD - Mirror of the Modulo Integer Value
47695 */
47696#define FTM_MOD_MIRROR_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MIRROR_MOD_SHIFT)) & FTM_MOD_MIRROR_MOD_MASK)
47697/*! @} */
47698
47699/*! @name CV_MIRROR - Mirror of Channel (n) Match Value */
47700/*! @{ */
47701#define FTM_CV_MIRROR_FRACVAL_MASK (0xF800U)
47702#define FTM_CV_MIRROR_FRACVAL_SHIFT (11U)
47703/*! FRACVAL - Channel (n) Match Fractional Value
47704 */
47705#define FTM_CV_MIRROR_FRACVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CV_MIRROR_FRACVAL_SHIFT)) & FTM_CV_MIRROR_FRACVAL_MASK)
47706#define FTM_CV_MIRROR_VAL_MASK (0xFFFF0000U)
47707#define FTM_CV_MIRROR_VAL_SHIFT (16U)
47708/*! VAL - Mirror of the Channel (n) Match Integer Value
47709 */
47710#define FTM_CV_MIRROR_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CV_MIRROR_VAL_SHIFT)) & FTM_CV_MIRROR_VAL_MASK)
47711/*! @} */
47712
47713/* The count of FTM_CV_MIRROR */
47714#define FTM_CV_MIRROR_COUNT (8U)
47715
47716
47717/*!
47718 * @}
47719 */ /* end of group FTM_Register_Masks */
47720
47721
47722/* FTM - Peripheral instance base addresses */
47723/** Peripheral ADMA__FTM0 base address */
47724#define ADMA__FTM0_BASE (0x5A8A0000u)
47725/** Peripheral ADMA__FTM0 base pointer */
47726#define ADMA__FTM0 ((FTM_Type *)ADMA__FTM0_BASE)
47727/** Peripheral ADMA__FTM1 base address */
47728#define ADMA__FTM1_BASE (0x5A8B0000u)
47729/** Peripheral ADMA__FTM1 base pointer */
47730#define ADMA__FTM1 ((FTM_Type *)ADMA__FTM1_BASE)
47731/** Array initializer of FTM peripheral base addresses */
47732#define FTM_BASE_ADDRS { ADMA__FTM0_BASE, ADMA__FTM1_BASE }
47733/** Array initializer of FTM peripheral base pointers */
47734#define FTM_BASE_PTRS { ADMA__FTM0, ADMA__FTM1 }
47735/** Interrupt vectors for the FTM peripheral type */
47736#define FTM_IRQS { ADMA_FTM0_INT_IRQn, ADMA_FTM1_INT_IRQn }
47737
47738/*!
47739 * @}
47740 */ /* end of group FTM_Peripheral_Access_Layer */
47741
47742
47743/* ----------------------------------------------------------------------------
47744 -- GPIO Peripheral Access Layer
47745 ---------------------------------------------------------------------------- */
47746
47747/*!
47748 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
47749 * @{
47750 */
47751
47752/** GPIO - Register Layout Typedef */
47753typedef struct {
47754 __IO uint32_t DR; /**< GPIO data register, offset: 0x0 */
47755 __IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */
47756 __I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */
47757 __IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */
47758 __IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */
47759 __IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */
47760 __IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */
47761 __IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */
47762 uint8_t RESERVED_0[100];
47763 __O uint32_t DR_SET; /**< GPIO data register SET, offset: 0x84 */
47764 __O uint32_t DR_CLEAR; /**< GPIO data register CLEAR, offset: 0x88 */
47765 __O uint32_t DR_TOGGLE; /**< GPIO data register TOGGLE, offset: 0x8C */
47766} GPIO_Type;
47767
47768/* ----------------------------------------------------------------------------
47769 -- GPIO Register Masks
47770 ---------------------------------------------------------------------------- */
47771
47772/*!
47773 * @addtogroup GPIO_Register_Masks GPIO Register Masks
47774 * @{
47775 */
47776
47777/*! @name DR - GPIO data register */
47778/*! @{ */
47779#define GPIO_DR_DR_MASK (0xFFFFFFFFU)
47780#define GPIO_DR_DR_SHIFT (0U)
47781/*! DR - DR
47782 */
47783#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
47784/*! @} */
47785
47786/*! @name GDIR - GPIO direction register */
47787/*! @{ */
47788#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU)
47789#define GPIO_GDIR_GDIR_SHIFT (0U)
47790/*! GDIR - GDIR
47791 */
47792#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
47793/*! @} */
47794
47795/*! @name PSR - GPIO pad status register */
47796/*! @{ */
47797#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU)
47798#define GPIO_PSR_PSR_SHIFT (0U)
47799/*! PSR - PSR
47800 */
47801#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
47802/*! @} */
47803
47804/*! @name ICR1 - GPIO interrupt configuration register1 */
47805/*! @{ */
47806#define GPIO_ICR1_ICR0_MASK (0x3U)
47807#define GPIO_ICR1_ICR0_SHIFT (0U)
47808/*! ICR0 - ICR0
47809 * 0b00..Interrupt n is low-level sensitive.
47810 * 0b01..Interrupt n is high-level sensitive.
47811 * 0b10..Interrupt n is rising-edge sensitive.
47812 * 0b11..Interrupt n is falling-edge sensitive.
47813 */
47814#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
47815#define GPIO_ICR1_ICR1_MASK (0xCU)
47816#define GPIO_ICR1_ICR1_SHIFT (2U)
47817/*! ICR1 - ICR1
47818 * 0b00..Interrupt n is low-level sensitive.
47819 * 0b01..Interrupt n is high-level sensitive.
47820 * 0b10..Interrupt n is rising-edge sensitive.
47821 * 0b11..Interrupt n is falling-edge sensitive.
47822 */
47823#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
47824#define GPIO_ICR1_ICR2_MASK (0x30U)
47825#define GPIO_ICR1_ICR2_SHIFT (4U)
47826/*! ICR2 - ICR2
47827 * 0b00..Interrupt n is low-level sensitive.
47828 * 0b01..Interrupt n is high-level sensitive.
47829 * 0b10..Interrupt n is rising-edge sensitive.
47830 * 0b11..Interrupt n is falling-edge sensitive.
47831 */
47832#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
47833#define GPIO_ICR1_ICR3_MASK (0xC0U)
47834#define GPIO_ICR1_ICR3_SHIFT (6U)
47835/*! ICR3 - ICR3
47836 * 0b00..Interrupt n is low-level sensitive.
47837 * 0b01..Interrupt n is high-level sensitive.
47838 * 0b10..Interrupt n is rising-edge sensitive.
47839 * 0b11..Interrupt n is falling-edge sensitive.
47840 */
47841#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
47842#define GPIO_ICR1_ICR4_MASK (0x300U)
47843#define GPIO_ICR1_ICR4_SHIFT (8U)
47844/*! ICR4 - ICR4
47845 * 0b00..Interrupt n is low-level sensitive.
47846 * 0b01..Interrupt n is high-level sensitive.
47847 * 0b10..Interrupt n is rising-edge sensitive.
47848 * 0b11..Interrupt n is falling-edge sensitive.
47849 */
47850#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
47851#define GPIO_ICR1_ICR5_MASK (0xC00U)
47852#define GPIO_ICR1_ICR5_SHIFT (10U)
47853/*! ICR5 - ICR5
47854 * 0b00..Interrupt n is low-level sensitive.
47855 * 0b01..Interrupt n is high-level sensitive.
47856 * 0b10..Interrupt n is rising-edge sensitive.
47857 * 0b11..Interrupt n is falling-edge sensitive.
47858 */
47859#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
47860#define GPIO_ICR1_ICR6_MASK (0x3000U)
47861#define GPIO_ICR1_ICR6_SHIFT (12U)
47862/*! ICR6 - ICR6
47863 * 0b00..Interrupt n is low-level sensitive.
47864 * 0b01..Interrupt n is high-level sensitive.
47865 * 0b10..Interrupt n is rising-edge sensitive.
47866 * 0b11..Interrupt n is falling-edge sensitive.
47867 */
47868#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
47869#define GPIO_ICR1_ICR7_MASK (0xC000U)
47870#define GPIO_ICR1_ICR7_SHIFT (14U)
47871/*! ICR7 - ICR7
47872 * 0b00..Interrupt n is low-level sensitive.
47873 * 0b01..Interrupt n is high-level sensitive.
47874 * 0b10..Interrupt n is rising-edge sensitive.
47875 * 0b11..Interrupt n is falling-edge sensitive.
47876 */
47877#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
47878#define GPIO_ICR1_ICR8_MASK (0x30000U)
47879#define GPIO_ICR1_ICR8_SHIFT (16U)
47880/*! ICR8 - ICR8
47881 * 0b00..Interrupt n is low-level sensitive.
47882 * 0b01..Interrupt n is high-level sensitive.
47883 * 0b10..Interrupt n is rising-edge sensitive.
47884 * 0b11..Interrupt n is falling-edge sensitive.
47885 */
47886#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
47887#define GPIO_ICR1_ICR9_MASK (0xC0000U)
47888#define GPIO_ICR1_ICR9_SHIFT (18U)
47889/*! ICR9 - ICR9
47890 * 0b00..Interrupt n is low-level sensitive.
47891 * 0b01..Interrupt n is high-level sensitive.
47892 * 0b10..Interrupt n is rising-edge sensitive.
47893 * 0b11..Interrupt n is falling-edge sensitive.
47894 */
47895#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
47896#define GPIO_ICR1_ICR10_MASK (0x300000U)
47897#define GPIO_ICR1_ICR10_SHIFT (20U)
47898/*! ICR10 - ICR10
47899 * 0b00..Interrupt n is low-level sensitive.
47900 * 0b01..Interrupt n is high-level sensitive.
47901 * 0b10..Interrupt n is rising-edge sensitive.
47902 * 0b11..Interrupt n is falling-edge sensitive.
47903 */
47904#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
47905#define GPIO_ICR1_ICR11_MASK (0xC00000U)
47906#define GPIO_ICR1_ICR11_SHIFT (22U)
47907/*! ICR11 - ICR11
47908 * 0b00..Interrupt n is low-level sensitive.
47909 * 0b01..Interrupt n is high-level sensitive.
47910 * 0b10..Interrupt n is rising-edge sensitive.
47911 * 0b11..Interrupt n is falling-edge sensitive.
47912 */
47913#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
47914#define GPIO_ICR1_ICR12_MASK (0x3000000U)
47915#define GPIO_ICR1_ICR12_SHIFT (24U)
47916/*! ICR12 - ICR12
47917 * 0b00..Interrupt n is low-level sensitive.
47918 * 0b01..Interrupt n is high-level sensitive.
47919 * 0b10..Interrupt n is rising-edge sensitive.
47920 * 0b11..Interrupt n is falling-edge sensitive.
47921 */
47922#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
47923#define GPIO_ICR1_ICR13_MASK (0xC000000U)
47924#define GPIO_ICR1_ICR13_SHIFT (26U)
47925/*! ICR13 - ICR13
47926 * 0b00..Interrupt n is low-level sensitive.
47927 * 0b01..Interrupt n is high-level sensitive.
47928 * 0b10..Interrupt n is rising-edge sensitive.
47929 * 0b11..Interrupt n is falling-edge sensitive.
47930 */
47931#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
47932#define GPIO_ICR1_ICR14_MASK (0x30000000U)
47933#define GPIO_ICR1_ICR14_SHIFT (28U)
47934/*! ICR14 - ICR14
47935 * 0b00..Interrupt n is low-level sensitive.
47936 * 0b01..Interrupt n is high-level sensitive.
47937 * 0b10..Interrupt n is rising-edge sensitive.
47938 * 0b11..Interrupt n is falling-edge sensitive.
47939 */
47940#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
47941#define GPIO_ICR1_ICR15_MASK (0xC0000000U)
47942#define GPIO_ICR1_ICR15_SHIFT (30U)
47943/*! ICR15 - ICR15
47944 * 0b00..Interrupt n is low-level sensitive.
47945 * 0b01..Interrupt n is high-level sensitive.
47946 * 0b10..Interrupt n is rising-edge sensitive.
47947 * 0b11..Interrupt n is falling-edge sensitive.
47948 */
47949#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
47950/*! @} */
47951
47952/*! @name ICR2 - GPIO interrupt configuration register2 */
47953/*! @{ */
47954#define GPIO_ICR2_ICR16_MASK (0x3U)
47955#define GPIO_ICR2_ICR16_SHIFT (0U)
47956/*! ICR16 - ICR16
47957 * 0b00..Interrupt n is low-level sensitive.
47958 * 0b01..Interrupt n is high-level sensitive.
47959 * 0b10..Interrupt n is rising-edge sensitive.
47960 * 0b11..Interrupt n is falling-edge sensitive.
47961 */
47962#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
47963#define GPIO_ICR2_ICR17_MASK (0xCU)
47964#define GPIO_ICR2_ICR17_SHIFT (2U)
47965/*! ICR17 - ICR17
47966 * 0b00..Interrupt n is low-level sensitive.
47967 * 0b01..Interrupt n is high-level sensitive.
47968 * 0b10..Interrupt n is rising-edge sensitive.
47969 * 0b11..Interrupt n is falling-edge sensitive.
47970 */
47971#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
47972#define GPIO_ICR2_ICR18_MASK (0x30U)
47973#define GPIO_ICR2_ICR18_SHIFT (4U)
47974/*! ICR18 - ICR18
47975 * 0b00..Interrupt n is low-level sensitive.
47976 * 0b01..Interrupt n is high-level sensitive.
47977 * 0b10..Interrupt n is rising-edge sensitive.
47978 * 0b11..Interrupt n is falling-edge sensitive.
47979 */
47980#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
47981#define GPIO_ICR2_ICR19_MASK (0xC0U)
47982#define GPIO_ICR2_ICR19_SHIFT (6U)
47983/*! ICR19 - ICR19
47984 * 0b00..Interrupt n is low-level sensitive.
47985 * 0b01..Interrupt n is high-level sensitive.
47986 * 0b10..Interrupt n is rising-edge sensitive.
47987 * 0b11..Interrupt n is falling-edge sensitive.
47988 */
47989#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
47990#define GPIO_ICR2_ICR20_MASK (0x300U)
47991#define GPIO_ICR2_ICR20_SHIFT (8U)
47992/*! ICR20 - ICR20
47993 * 0b00..Interrupt n is low-level sensitive.
47994 * 0b01..Interrupt n is high-level sensitive.
47995 * 0b10..Interrupt n is rising-edge sensitive.
47996 * 0b11..Interrupt n is falling-edge sensitive.
47997 */
47998#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
47999#define GPIO_ICR2_ICR21_MASK (0xC00U)
48000#define GPIO_ICR2_ICR21_SHIFT (10U)
48001/*! ICR21 - ICR21
48002 * 0b00..Interrupt n is low-level sensitive.
48003 * 0b01..Interrupt n is high-level sensitive.
48004 * 0b10..Interrupt n is rising-edge sensitive.
48005 * 0b11..Interrupt n is falling-edge sensitive.
48006 */
48007#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
48008#define GPIO_ICR2_ICR22_MASK (0x3000U)
48009#define GPIO_ICR2_ICR22_SHIFT (12U)
48010/*! ICR22 - ICR22
48011 * 0b00..Interrupt n is low-level sensitive.
48012 * 0b01..Interrupt n is high-level sensitive.
48013 * 0b10..Interrupt n is rising-edge sensitive.
48014 * 0b11..Interrupt n is falling-edge sensitive.
48015 */
48016#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
48017#define GPIO_ICR2_ICR23_MASK (0xC000U)
48018#define GPIO_ICR2_ICR23_SHIFT (14U)
48019/*! ICR23 - ICR23
48020 * 0b00..Interrupt n is low-level sensitive.
48021 * 0b01..Interrupt n is high-level sensitive.
48022 * 0b10..Interrupt n is rising-edge sensitive.
48023 * 0b11..Interrupt n is falling-edge sensitive.
48024 */
48025#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
48026#define GPIO_ICR2_ICR24_MASK (0x30000U)
48027#define GPIO_ICR2_ICR24_SHIFT (16U)
48028/*! ICR24 - ICR24
48029 * 0b00..Interrupt n is low-level sensitive.
48030 * 0b01..Interrupt n is high-level sensitive.
48031 * 0b10..Interrupt n is rising-edge sensitive.
48032 * 0b11..Interrupt n is falling-edge sensitive.
48033 */
48034#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
48035#define GPIO_ICR2_ICR25_MASK (0xC0000U)
48036#define GPIO_ICR2_ICR25_SHIFT (18U)
48037/*! ICR25 - ICR25
48038 * 0b00..Interrupt n is low-level sensitive.
48039 * 0b01..Interrupt n is high-level sensitive.
48040 * 0b10..Interrupt n is rising-edge sensitive.
48041 * 0b11..Interrupt n is falling-edge sensitive.
48042 */
48043#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
48044#define GPIO_ICR2_ICR26_MASK (0x300000U)
48045#define GPIO_ICR2_ICR26_SHIFT (20U)
48046/*! ICR26 - ICR26
48047 * 0b00..Interrupt n is low-level sensitive.
48048 * 0b01..Interrupt n is high-level sensitive.
48049 * 0b10..Interrupt n is rising-edge sensitive.
48050 * 0b11..Interrupt n is falling-edge sensitive.
48051 */
48052#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
48053#define GPIO_ICR2_ICR27_MASK (0xC00000U)
48054#define GPIO_ICR2_ICR27_SHIFT (22U)
48055/*! ICR27 - ICR27
48056 * 0b00..Interrupt n is low-level sensitive.
48057 * 0b01..Interrupt n is high-level sensitive.
48058 * 0b10..Interrupt n is rising-edge sensitive.
48059 * 0b11..Interrupt n is falling-edge sensitive.
48060 */
48061#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
48062#define GPIO_ICR2_ICR28_MASK (0x3000000U)
48063#define GPIO_ICR2_ICR28_SHIFT (24U)
48064/*! ICR28 - ICR28
48065 * 0b00..Interrupt n is low-level sensitive.
48066 * 0b01..Interrupt n is high-level sensitive.
48067 * 0b10..Interrupt n is rising-edge sensitive.
48068 * 0b11..Interrupt n is falling-edge sensitive.
48069 */
48070#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
48071#define GPIO_ICR2_ICR29_MASK (0xC000000U)
48072#define GPIO_ICR2_ICR29_SHIFT (26U)
48073/*! ICR29 - ICR29
48074 * 0b00..Interrupt n is low-level sensitive.
48075 * 0b01..Interrupt n is high-level sensitive.
48076 * 0b10..Interrupt n is rising-edge sensitive.
48077 * 0b11..Interrupt n is falling-edge sensitive.
48078 */
48079#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
48080#define GPIO_ICR2_ICR30_MASK (0x30000000U)
48081#define GPIO_ICR2_ICR30_SHIFT (28U)
48082/*! ICR30 - ICR30
48083 * 0b00..Interrupt n is low-level sensitive.
48084 * 0b01..Interrupt n is high-level sensitive.
48085 * 0b10..Interrupt n is rising-edge sensitive.
48086 * 0b11..Interrupt n is falling-edge sensitive.
48087 */
48088#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
48089#define GPIO_ICR2_ICR31_MASK (0xC0000000U)
48090#define GPIO_ICR2_ICR31_SHIFT (30U)
48091/*! ICR31 - ICR31
48092 * 0b00..Interrupt n is low-level sensitive.
48093 * 0b01..Interrupt n is high-level sensitive.
48094 * 0b10..Interrupt n is rising-edge sensitive.
48095 * 0b11..Interrupt n is falling-edge sensitive.
48096 */
48097#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
48098/*! @} */
48099
48100/*! @name IMR - GPIO interrupt mask register */
48101/*! @{ */
48102#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU)
48103#define GPIO_IMR_IMR_SHIFT (0U)
48104/*! IMR - IMR
48105 */
48106#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
48107/*! @} */
48108
48109/*! @name ISR - GPIO interrupt status register */
48110/*! @{ */
48111#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU)
48112#define GPIO_ISR_ISR_SHIFT (0U)
48113/*! ISR - ISR
48114 */
48115#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
48116/*! @} */
48117
48118/*! @name EDGE_SEL - GPIO edge select register */
48119/*! @{ */
48120#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU)
48121#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U)
48122/*! GPIO_EDGE_SEL - GPIO_EDGE_SEL
48123 */
48124#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
48125/*! @} */
48126
48127/*! @name DR_SET - GPIO data register SET */
48128/*! @{ */
48129#define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU)
48130#define GPIO_DR_SET_DR_SET_SHIFT (0U)
48131/*! DR_SET - DR_SET
48132 */
48133#define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK)
48134/*! @} */
48135
48136/*! @name DR_CLEAR - GPIO data register CLEAR */
48137/*! @{ */
48138#define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU)
48139#define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U)
48140/*! DR_CLEAR - DR_CLEAR
48141 */
48142#define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK)
48143/*! @} */
48144
48145/*! @name DR_TOGGLE - GPIO data register TOGGLE */
48146/*! @{ */
48147#define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU)
48148#define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U)
48149/*! DR_TOGGLE - DR_TOGGLE
48150 */
48151#define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK)
48152/*! @} */
48153
48154
48155/*!
48156 * @}
48157 */ /* end of group GPIO_Register_Masks */
48158
48159
48160/* GPIO - Peripheral instance base addresses */
48161/** Peripheral CI_PI__GPIO base address */
48162#define CI_PI__GPIO_BASE (0x58262000u)
48163/** Peripheral CI_PI__GPIO base pointer */
48164#define CI_PI__GPIO ((GPIO_Type *)CI_PI__GPIO_BASE)
48165/** Peripheral DI_MIPI_DSI_LVDS_0__GPIO base address */
48166#define DI_MIPI_DSI_LVDS_0__GPIO_BASE (0x56222000u)
48167/** Peripheral DI_MIPI_DSI_LVDS_0__GPIO base pointer */
48168#define DI_MIPI_DSI_LVDS_0__GPIO ((GPIO_Type *)DI_MIPI_DSI_LVDS_0__GPIO_BASE)
48169/** Peripheral DI_MIPI_DSI_LVDS_1__GPIO base address */
48170#define DI_MIPI_DSI_LVDS_1__GPIO_BASE (0x56242000u)
48171/** Peripheral DI_MIPI_DSI_LVDS_1__GPIO base pointer */
48172#define DI_MIPI_DSI_LVDS_1__GPIO ((GPIO_Type *)DI_MIPI_DSI_LVDS_1__GPIO_BASE)
48173/** Peripheral HSIO__GPIO base address */
48174#define HSIO__GPIO_BASE (0x5F170000u)
48175/** Peripheral HSIO__GPIO base pointer */
48176#define HSIO__GPIO ((GPIO_Type *)HSIO__GPIO_BASE)
48177/** Peripheral LSIO__GPIO0 base address */
48178#define LSIO__GPIO0_BASE (0x5D080000u)
48179/** Peripheral LSIO__GPIO0 base pointer */
48180#define LSIO__GPIO0 ((GPIO_Type *)LSIO__GPIO0_BASE)
48181/** Peripheral LSIO__GPIO1 base address */
48182#define LSIO__GPIO1_BASE (0x5D090000u)
48183/** Peripheral LSIO__GPIO1 base pointer */
48184#define LSIO__GPIO1 ((GPIO_Type *)LSIO__GPIO1_BASE)
48185/** Peripheral LSIO__GPIO2 base address */
48186#define LSIO__GPIO2_BASE (0x5D0A0000u)
48187/** Peripheral LSIO__GPIO2 base pointer */
48188#define LSIO__GPIO2 ((GPIO_Type *)LSIO__GPIO2_BASE)
48189/** Peripheral LSIO__GPIO3 base address */
48190#define LSIO__GPIO3_BASE (0x5D0B0000u)
48191/** Peripheral LSIO__GPIO3 base pointer */
48192#define LSIO__GPIO3 ((GPIO_Type *)LSIO__GPIO3_BASE)
48193/** Peripheral LSIO__GPIO4 base address */
48194#define LSIO__GPIO4_BASE (0x5D0C0000u)
48195/** Peripheral LSIO__GPIO4 base pointer */
48196#define LSIO__GPIO4 ((GPIO_Type *)LSIO__GPIO4_BASE)
48197/** Peripheral LSIO__GPIO5 base address */
48198#define LSIO__GPIO5_BASE (0x5D0D0000u)
48199/** Peripheral LSIO__GPIO5 base pointer */
48200#define LSIO__GPIO5 ((GPIO_Type *)LSIO__GPIO5_BASE)
48201/** Peripheral LSIO__GPIO6 base address */
48202#define LSIO__GPIO6_BASE (0x5D0E0000u)
48203/** Peripheral LSIO__GPIO6 base pointer */
48204#define LSIO__GPIO6 ((GPIO_Type *)LSIO__GPIO6_BASE)
48205/** Peripheral LSIO__GPIO7 base address */
48206#define LSIO__GPIO7_BASE (0x5D0F0000u)
48207/** Peripheral LSIO__GPIO7 base pointer */
48208#define LSIO__GPIO7 ((GPIO_Type *)LSIO__GPIO7_BASE)
48209/** Peripheral MIPI_CSI__GPIO base address */
48210#define MIPI_CSI__GPIO_BASE (0x58222000u)
48211/** Peripheral MIPI_CSI__GPIO base pointer */
48212#define MIPI_CSI__GPIO ((GPIO_Type *)MIPI_CSI__GPIO_BASE)
48213/** Array initializer of GPIO peripheral base addresses */
48214#define GPIO_BASE_ADDRS { CI_PI__GPIO_BASE, DI_MIPI_DSI_LVDS_0__GPIO_BASE, DI_MIPI_DSI_LVDS_1__GPIO_BASE, HSIO__GPIO_BASE, LSIO__GPIO0_BASE, LSIO__GPIO1_BASE, LSIO__GPIO2_BASE, LSIO__GPIO3_BASE, LSIO__GPIO4_BASE, LSIO__GPIO5_BASE, LSIO__GPIO6_BASE, LSIO__GPIO7_BASE, MIPI_CSI__GPIO_BASE }
48215/** Array initializer of GPIO peripheral base pointers */
48216#define GPIO_BASE_PTRS { CI_PI__GPIO, DI_MIPI_DSI_LVDS_0__GPIO, DI_MIPI_DSI_LVDS_1__GPIO, HSIO__GPIO, LSIO__GPIO0, LSIO__GPIO1, LSIO__GPIO2, LSIO__GPIO3, LSIO__GPIO4, LSIO__GPIO5, LSIO__GPIO6, LSIO__GPIO7, MIPI_CSI__GPIO }
48217/** Interrupt vectors for the GPIO peripheral type */
48218#define GPIO_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, LSIO_GPIO_INT0_IRQn, LSIO_GPIO_INT1_IRQn, LSIO_GPIO_INT2_IRQn, LSIO_GPIO_INT3_IRQn, LSIO_GPIO_INT4_IRQn, LSIO_GPIO_INT5_IRQn, LSIO_GPIO_INT6_IRQn, LSIO_GPIO_INT7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
48219
48220/*!
48221 * @}
48222 */ /* end of group GPIO_Peripheral_Access_Layer */
48223
48224
48225/* ----------------------------------------------------------------------------
48226 -- GPMI Peripheral Access Layer
48227 ---------------------------------------------------------------------------- */
48228
48229/*!
48230 * @addtogroup GPMI_Peripheral_Access_Layer GPMI Peripheral Access Layer
48231 * @{
48232 */
48233
48234/** GPMI - Register Layout Typedef */
48235typedef struct {
48236 struct { /* offset: 0x0 */
48237 __IO uint32_t RW; /**< GPMI Control Register 0 Description, offset: 0x0 */
48238 __IO uint32_t SET; /**< GPMI Control Register 0 Description, offset: 0x4 */
48239 __IO uint32_t CLR; /**< GPMI Control Register 0 Description, offset: 0x8 */
48240 __IO uint32_t TOG; /**< GPMI Control Register 0 Description, offset: 0xC */
48241 } CTRL0;
48242 __IO uint32_t COMPARE; /**< GPMI Compare Register Description, offset: 0x10 */
48243 uint8_t RESERVED_0[12];
48244 struct { /* offset: 0x20 */
48245 __IO uint32_t RW; /**< GPMI Integrated ECC Control Register Description, offset: 0x20 */
48246 __IO uint32_t SET; /**< GPMI Integrated ECC Control Register Description, offset: 0x24 */
48247 __IO uint32_t CLR; /**< GPMI Integrated ECC Control Register Description, offset: 0x28 */
48248 __IO uint32_t TOG; /**< GPMI Integrated ECC Control Register Description, offset: 0x2C */
48249 } ECCCTRL;
48250 __IO uint32_t ECCCOUNT; /**< GPMI Integrated ECC Transfer Count Register Description, offset: 0x30 */
48251 uint8_t RESERVED_1[12];
48252 __IO uint32_t PAYLOAD; /**< GPMI Payload Address Register Description, offset: 0x40 */
48253 uint8_t RESERVED_2[12];
48254 __IO uint32_t AUXILIARY; /**< GPMI Auxiliary Address Register Description, offset: 0x50 */
48255 uint8_t RESERVED_3[12];
48256 struct { /* offset: 0x60 */
48257 __IO uint32_t RW; /**< GPMI Control Register 1 Description, offset: 0x60 */
48258 __IO uint32_t SET; /**< GPMI Control Register 1 Description, offset: 0x64 */
48259 __IO uint32_t CLR; /**< GPMI Control Register 1 Description, offset: 0x68 */
48260 __IO uint32_t TOG; /**< GPMI Control Register 1 Description, offset: 0x6C */
48261 } CTRL1;
48262 __IO uint32_t TIMING0; /**< GPMI Timing Register 0 Description, offset: 0x70 */
48263 uint8_t RESERVED_4[12];
48264 __IO uint32_t TIMING1; /**< GPMI Timing Register 1 Description, offset: 0x80 */
48265 uint8_t RESERVED_5[12];
48266 __IO uint32_t TIMING2; /**< GPMI Timing Register 2 Description, offset: 0x90 */
48267 uint8_t RESERVED_6[12];
48268 __IO uint32_t DATA; /**< GPMI DMA Data Transfer Register Description, offset: 0xA0 */
48269 uint8_t RESERVED_7[12];
48270 __I uint32_t STAT; /**< GPMI Status Register Description, offset: 0xB0 */
48271 uint8_t RESERVED_8[12];
48272 __I uint32_t DEBUGr; /**< GPMI Debug Information Register Description, offset: 0xC0 */
48273 uint8_t RESERVED_9[12];
48274 __I uint32_t VERSION; /**< GPMI Version Register Description, offset: 0xD0 */
48275 uint8_t RESERVED_10[12];
48276 __IO uint32_t DEBUG2; /**< GPMI Debug2 Information Register Description, offset: 0xE0 */
48277 uint8_t RESERVED_11[12];
48278 __I uint32_t DEBUG3; /**< GPMI Debug3 Information Register Description, offset: 0xF0 */
48279 uint8_t RESERVED_12[12];
48280 __IO uint32_t READ_DDR_DLL_CTRL; /**< GPMI Double Rate Read DLL Control Register Description, offset: 0x100 */
48281 uint8_t RESERVED_13[12];
48282 __IO uint32_t WRITE_DDR_DLL_CTRL; /**< GPMI Double Rate Write DLL Control Register Description, offset: 0x110 */
48283 uint8_t RESERVED_14[12];
48284 __I uint32_t READ_DDR_DLL_STS; /**< GPMI Double Rate Read DLL Status Register Description, offset: 0x120 */
48285 uint8_t RESERVED_15[12];
48286 __I uint32_t WRITE_DDR_DLL_STS; /**< GPMI Double Rate Write DLL Status Register Description, offset: 0x130 */
48287 uint8_t RESERVED_16[12];
48288 __IO uint32_t TIMING3; /**< GPMI Timing Register 3 Description, offset: 0x140 */
48289 uint8_t RESERVED_17[12];
48290 __IO uint32_t CTRL2; /**< GPMI Control Register 2 Description, offset: 0x150 */
48291} GPMI_Type;
48292
48293/* ----------------------------------------------------------------------------
48294 -- GPMI Register Masks
48295 ---------------------------------------------------------------------------- */
48296
48297/*!
48298 * @addtogroup GPMI_Register_Masks GPMI Register Masks
48299 * @{
48300 */
48301
48302/*! @name CTRL0 - GPMI Control Register 0 Description */
48303/*! @{ */
48304#define GPMI_CTRL0_XFER_COUNT_MASK (0xFFFFU)
48305#define GPMI_CTRL0_XFER_COUNT_SHIFT (0U)
48306/*! XFER_COUNT - XFER_COUNT
48307 */
48308#define GPMI_CTRL0_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_XFER_COUNT_SHIFT)) & GPMI_CTRL0_XFER_COUNT_MASK)
48309#define GPMI_CTRL0_ADDRESS_INCREMENT_MASK (0x10000U)
48310#define GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT (16U)
48311/*! ADDRESS_INCREMENT - ADDRESS_INCREMENT
48312 */
48313#define GPMI_CTRL0_ADDRESS_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_INCREMENT_SHIFT)) & GPMI_CTRL0_ADDRESS_INCREMENT_MASK)
48314#define GPMI_CTRL0_ADDRESS_MASK (0xE0000U)
48315#define GPMI_CTRL0_ADDRESS_SHIFT (17U)
48316/*! ADDRESS - ADDRESS
48317 */
48318#define GPMI_CTRL0_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_ADDRESS_SHIFT)) & GPMI_CTRL0_ADDRESS_MASK)
48319#define GPMI_CTRL0_CS_MASK (0x700000U)
48320#define GPMI_CTRL0_CS_SHIFT (20U)
48321/*! CS - CS
48322 */
48323#define GPMI_CTRL0_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CS_SHIFT)) & GPMI_CTRL0_CS_MASK)
48324#define GPMI_CTRL0_WORD_LENGTH_MASK (0x800000U)
48325#define GPMI_CTRL0_WORD_LENGTH_SHIFT (23U)
48326/*! WORD_LENGTH - WORD_LENGTH
48327 * 0b0..Reserved.
48328 * 0b1..8-bit Data Bus mode.
48329 */
48330#define GPMI_CTRL0_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_WORD_LENGTH_SHIFT)) & GPMI_CTRL0_WORD_LENGTH_MASK)
48331#define GPMI_CTRL0_COMMAND_MODE_MASK (0x3000000U)
48332#define GPMI_CTRL0_COMMAND_MODE_SHIFT (24U)
48333/*! COMMAND_MODE - COMMAND_MODE
48334 * 0b00..Write mode.
48335 * 0b01..Read Mode.
48336 * 0b10..Read and Compare Mode (setting sense flop).
48337 * 0b11..Wait for Ready.
48338 */
48339#define GPMI_CTRL0_COMMAND_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_COMMAND_MODE_SHIFT)) & GPMI_CTRL0_COMMAND_MODE_MASK)
48340#define GPMI_CTRL0_UDMA_MASK (0x4000000U)
48341#define GPMI_CTRL0_UDMA_SHIFT (26U)
48342/*! UDMA - UDMA
48343 * 0b0..Use ATA-PIO mode on the external bus.
48344 * 0b1..Use ATA-Ultra DMA mode on the external bus.
48345 */
48346#define GPMI_CTRL0_UDMA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_UDMA_SHIFT)) & GPMI_CTRL0_UDMA_MASK)
48347#define GPMI_CTRL0_LOCK_CS_MASK (0x8000000U)
48348#define GPMI_CTRL0_LOCK_CS_SHIFT (27U)
48349/*! LOCK_CS - LOCK_CS
48350 */
48351#define GPMI_CTRL0_LOCK_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_LOCK_CS_SHIFT)) & GPMI_CTRL0_LOCK_CS_MASK)
48352#define GPMI_CTRL0_WR_DATA_EN_MASK (0x10000000U)
48353#define GPMI_CTRL0_WR_DATA_EN_SHIFT (28U)
48354/*! WR_DATA_EN - WR_DATA_EN
48355 */
48356#define GPMI_CTRL0_WR_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_WR_DATA_EN_SHIFT)) & GPMI_CTRL0_WR_DATA_EN_MASK)
48357#define GPMI_CTRL0_RUN_MASK (0x20000000U)
48358#define GPMI_CTRL0_RUN_SHIFT (29U)
48359/*! RUN - RUN
48360 */
48361#define GPMI_CTRL0_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_RUN_SHIFT)) & GPMI_CTRL0_RUN_MASK)
48362#define GPMI_CTRL0_CLKGATE_MASK (0x40000000U)
48363#define GPMI_CTRL0_CLKGATE_SHIFT (30U)
48364/*! CLKGATE - CLKGATE
48365 */
48366#define GPMI_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_CLKGATE_SHIFT)) & GPMI_CTRL0_CLKGATE_MASK)
48367#define GPMI_CTRL0_SFTRST_MASK (0x80000000U)
48368#define GPMI_CTRL0_SFTRST_SHIFT (31U)
48369/*! SFTRST - SFTRST
48370 */
48371#define GPMI_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL0_SFTRST_SHIFT)) & GPMI_CTRL0_SFTRST_MASK)
48372/*! @} */
48373
48374/*! @name COMPARE - GPMI Compare Register Description */
48375/*! @{ */
48376#define GPMI_COMPARE_REFERENCE_MASK (0xFFFFU)
48377#define GPMI_COMPARE_REFERENCE_SHIFT (0U)
48378/*! REFERENCE - REFERENCE
48379 */
48380#define GPMI_COMPARE_REFERENCE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_REFERENCE_SHIFT)) & GPMI_COMPARE_REFERENCE_MASK)
48381#define GPMI_COMPARE_MASK_MASK (0xFFFF0000U)
48382#define GPMI_COMPARE_MASK_SHIFT (16U)
48383/*! MASK - MASK
48384 */
48385#define GPMI_COMPARE_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_COMPARE_MASK_SHIFT)) & GPMI_COMPARE_MASK_MASK)
48386/*! @} */
48387
48388/*! @name ECCCTRL - GPMI Integrated ECC Control Register Description */
48389/*! @{ */
48390#define GPMI_ECCCTRL_BUFFER_MASK_MASK (0x1FFU)
48391#define GPMI_ECCCTRL_BUFFER_MASK_SHIFT (0U)
48392/*! BUFFER_MASK - BUFFER_MASK
48393 */
48394#define GPMI_ECCCTRL_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_BUFFER_MASK_SHIFT)) & GPMI_ECCCTRL_BUFFER_MASK_MASK)
48395#define GPMI_ECCCTRL_RANDOMIZER_TYPE_MASK (0x600U)
48396#define GPMI_ECCCTRL_RANDOMIZER_TYPE_SHIFT (9U)
48397/*! RANDOMIZER_TYPE - RANDOMIZER_TYPE
48398 * 0b00..Type 0
48399 * 0b01..Type 1
48400 * 0b10..Type 2
48401 */
48402#define GPMI_ECCCTRL_RANDOMIZER_TYPE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RANDOMIZER_TYPE_SHIFT)) & GPMI_ECCCTRL_RANDOMIZER_TYPE_MASK)
48403#define GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK (0x800U)
48404#define GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT (11U)
48405/*! RANDOMIZER_ENABLE - RANDOMIZER_ENABLE
48406 * 0b0..disable
48407 * 0b1..enable
48408 */
48409#define GPMI_ECCCTRL_RANDOMIZER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RANDOMIZER_ENABLE_SHIFT)) & GPMI_ECCCTRL_RANDOMIZER_ENABLE_MASK)
48410#define GPMI_ECCCTRL_ENABLE_ECC_MASK (0x1000U)
48411#define GPMI_ECCCTRL_ENABLE_ECC_SHIFT (12U)
48412/*! ENABLE_ECC - ENABLE_ECC
48413 */
48414#define GPMI_ECCCTRL_ENABLE_ECC(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ENABLE_ECC_SHIFT)) & GPMI_ECCCTRL_ENABLE_ECC_MASK)
48415#define GPMI_ECCCTRL_ECC_CMD_MASK (0x6000U)
48416#define GPMI_ECCCTRL_ECC_CMD_SHIFT (13U)
48417/*! ECC_CMD - ECC_CMD
48418 */
48419#define GPMI_ECCCTRL_ECC_CMD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_ECC_CMD_SHIFT)) & GPMI_ECCCTRL_ECC_CMD_MASK)
48420#define GPMI_ECCCTRL_RSVD2_MASK (0x8000U)
48421#define GPMI_ECCCTRL_RSVD2_SHIFT (15U)
48422/*! RSVD2 - RSVD2
48423 */
48424#define GPMI_ECCCTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_RSVD2_SHIFT)) & GPMI_ECCCTRL_RSVD2_MASK)
48425#define GPMI_ECCCTRL_HANDLE_MASK (0xFFFF0000U)
48426#define GPMI_ECCCTRL_HANDLE_SHIFT (16U)
48427/*! HANDLE - HANDLE
48428 */
48429#define GPMI_ECCCTRL_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCTRL_HANDLE_SHIFT)) & GPMI_ECCCTRL_HANDLE_MASK)
48430/*! @} */
48431
48432/*! @name ECCCOUNT - GPMI Integrated ECC Transfer Count Register Description */
48433/*! @{ */
48434#define GPMI_ECCCOUNT_COUNT_MASK (0xFFFFU)
48435#define GPMI_ECCCOUNT_COUNT_SHIFT (0U)
48436/*! COUNT - COUNT
48437 */
48438#define GPMI_ECCCOUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_COUNT_SHIFT)) & GPMI_ECCCOUNT_COUNT_MASK)
48439#define GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK (0xFF0000U)
48440#define GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT (16U)
48441/*! RANDOMIZER_PAGE - RANDOMIZER_PAGE
48442 */
48443#define GPMI_ECCCOUNT_RANDOMIZER_PAGE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_ECCCOUNT_RANDOMIZER_PAGE_SHIFT)) & GPMI_ECCCOUNT_RANDOMIZER_PAGE_MASK)
48444/*! @} */
48445
48446/*! @name PAYLOAD - GPMI Payload Address Register Description */
48447/*! @{ */
48448#define GPMI_PAYLOAD_RSVD0_MASK (0x3U)
48449#define GPMI_PAYLOAD_RSVD0_SHIFT (0U)
48450/*! RSVD0 - RSVD0
48451 */
48452#define GPMI_PAYLOAD_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_RSVD0_SHIFT)) & GPMI_PAYLOAD_RSVD0_MASK)
48453#define GPMI_PAYLOAD_ADDRESS_MASK (0xFFFFFFFCU)
48454#define GPMI_PAYLOAD_ADDRESS_SHIFT (2U)
48455/*! ADDRESS - ADDRESS
48456 */
48457#define GPMI_PAYLOAD_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_PAYLOAD_ADDRESS_SHIFT)) & GPMI_PAYLOAD_ADDRESS_MASK)
48458/*! @} */
48459
48460/*! @name AUXILIARY - GPMI Auxiliary Address Register Description */
48461/*! @{ */
48462#define GPMI_AUXILIARY_RSVD0_MASK (0x3U)
48463#define GPMI_AUXILIARY_RSVD0_SHIFT (0U)
48464/*! RSVD0 - RSVD0
48465 */
48466#define GPMI_AUXILIARY_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_RSVD0_SHIFT)) & GPMI_AUXILIARY_RSVD0_MASK)
48467#define GPMI_AUXILIARY_ADDRESS_MASK (0xFFFFFFFCU)
48468#define GPMI_AUXILIARY_ADDRESS_SHIFT (2U)
48469/*! ADDRESS - ADDRESS
48470 */
48471#define GPMI_AUXILIARY_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_AUXILIARY_ADDRESS_SHIFT)) & GPMI_AUXILIARY_ADDRESS_MASK)
48472/*! @} */
48473
48474/*! @name CTRL1 - GPMI Control Register 1 Description */
48475/*! @{ */
48476#define GPMI_CTRL1_GPMI_MODE_MASK (0x1U)
48477#define GPMI_CTRL1_GPMI_MODE_SHIFT (0U)
48478/*! GPMI_MODE - GPMI_MODE
48479 * 0b0..NAND mode.
48480 * 0b1..ATA mode.
48481 */
48482#define GPMI_CTRL1_GPMI_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_MODE_SHIFT)) & GPMI_CTRL1_GPMI_MODE_MASK)
48483#define GPMI_CTRL1_CAMERA_MODE_MASK (0x2U)
48484#define GPMI_CTRL1_CAMERA_MODE_SHIFT (1U)
48485/*! CAMERA_MODE - CAMERA_MODE
48486 */
48487#define GPMI_CTRL1_CAMERA_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_CAMERA_MODE_SHIFT)) & GPMI_CTRL1_CAMERA_MODE_MASK)
48488#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK (0x4U)
48489#define GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT (2U)
48490/*! ATA_IRQRDY_POLARITY - ATA_IRQRDY_POLARITY
48491 * 0b0..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when low and busy when high.
48492 * 0b1..External RDY_BUSY[1] and RDY_BUSY[0] pins are ready when high and busy when low.
48493 */
48494#define GPMI_CTRL1_ATA_IRQRDY_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ATA_IRQRDY_POLARITY_SHIFT)) & GPMI_CTRL1_ATA_IRQRDY_POLARITY_MASK)
48495#define GPMI_CTRL1_DEV_RESET_MASK (0x8U)
48496#define GPMI_CTRL1_DEV_RESET_SHIFT (3U)
48497/*! DEV_RESET - DEV_RESET
48498 * 0b0..NANDF_WP_B pin is held low (asserted).
48499 * 0b1..NANDF_WP_B pin is held high (de-asserted).
48500 */
48501#define GPMI_CTRL1_DEV_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_RESET_SHIFT)) & GPMI_CTRL1_DEV_RESET_MASK)
48502#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK (0x70U)
48503#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT (4U)
48504/*! ABORT_WAIT_FOR_READY_CHANNEL - ABORT_WAIT_FOR_READY_CHANNEL
48505 */
48506#define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK)
48507#define GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK (0x80U)
48508#define GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT (7U)
48509/*! ABORT_WAIT_REQUEST - ABORT_WAIT_REQUEST
48510 */
48511#define GPMI_CTRL1_ABORT_WAIT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_ABORT_WAIT_REQUEST_SHIFT)) & GPMI_CTRL1_ABORT_WAIT_REQUEST_MASK)
48512#define GPMI_CTRL1_BURST_EN_MASK (0x100U)
48513#define GPMI_CTRL1_BURST_EN_SHIFT (8U)
48514/*! BURST_EN - BURST_EN
48515 */
48516#define GPMI_CTRL1_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BURST_EN_SHIFT)) & GPMI_CTRL1_BURST_EN_MASK)
48517#define GPMI_CTRL1_TIMEOUT_IRQ_MASK (0x200U)
48518#define GPMI_CTRL1_TIMEOUT_IRQ_SHIFT (9U)
48519/*! TIMEOUT_IRQ - TIMEOUT_IRQ
48520 */
48521#define GPMI_CTRL1_TIMEOUT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_MASK)
48522#define GPMI_CTRL1_DEV_IRQ_MASK (0x400U)
48523#define GPMI_CTRL1_DEV_IRQ_SHIFT (10U)
48524/*! DEV_IRQ - DEV_IRQ
48525 */
48526#define GPMI_CTRL1_DEV_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_IRQ_SHIFT)) & GPMI_CTRL1_DEV_IRQ_MASK)
48527#define GPMI_CTRL1_DMA2ECC_MODE_MASK (0x800U)
48528#define GPMI_CTRL1_DMA2ECC_MODE_SHIFT (11U)
48529/*! DMA2ECC_MODE - DMA2ECC_MODE
48530 */
48531#define GPMI_CTRL1_DMA2ECC_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DMA2ECC_MODE_SHIFT)) & GPMI_CTRL1_DMA2ECC_MODE_MASK)
48532#define GPMI_CTRL1_RDN_DELAY_MASK (0xF000U)
48533#define GPMI_CTRL1_RDN_DELAY_SHIFT (12U)
48534/*! RDN_DELAY - RDN_DELAY
48535 */
48536#define GPMI_CTRL1_RDN_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_RDN_DELAY_SHIFT)) & GPMI_CTRL1_RDN_DELAY_MASK)
48537#define GPMI_CTRL1_HALF_PERIOD_MASK (0x10000U)
48538#define GPMI_CTRL1_HALF_PERIOD_SHIFT (16U)
48539/*! HALF_PERIOD - HALF_PERIOD
48540 */
48541#define GPMI_CTRL1_HALF_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_HALF_PERIOD_SHIFT)) & GPMI_CTRL1_HALF_PERIOD_MASK)
48542#define GPMI_CTRL1_DLL_ENABLE_MASK (0x20000U)
48543#define GPMI_CTRL1_DLL_ENABLE_SHIFT (17U)
48544/*! DLL_ENABLE - DLL_ENABLE
48545 */
48546#define GPMI_CTRL1_DLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DLL_ENABLE_SHIFT)) & GPMI_CTRL1_DLL_ENABLE_MASK)
48547#define GPMI_CTRL1_BCH_MODE_MASK (0x40000U)
48548#define GPMI_CTRL1_BCH_MODE_SHIFT (18U)
48549/*! BCH_MODE - BCH_MODE
48550 */
48551#define GPMI_CTRL1_BCH_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_BCH_MODE_SHIFT)) & GPMI_CTRL1_BCH_MODE_MASK)
48552#define GPMI_CTRL1_GANGED_RDYBUSY_MASK (0x80000U)
48553#define GPMI_CTRL1_GANGED_RDYBUSY_SHIFT (19U)
48554/*! GANGED_RDYBUSY - GANGED_RDYBUSY
48555 */
48556#define GPMI_CTRL1_GANGED_RDYBUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GANGED_RDYBUSY_SHIFT)) & GPMI_CTRL1_GANGED_RDYBUSY_MASK)
48557#define GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK (0x100000U)
48558#define GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT (20U)
48559/*! TIMEOUT_IRQ_EN - TIMEOUT_IRQ_EN
48560 */
48561#define GPMI_CTRL1_TIMEOUT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TIMEOUT_IRQ_EN_SHIFT)) & GPMI_CTRL1_TIMEOUT_IRQ_EN_MASK)
48562#define GPMI_CTRL1_RSVD1_MASK (0x200000U)
48563#define GPMI_CTRL1_RSVD1_SHIFT (21U)
48564/*! RSVD1 - RSVD1
48565 */
48566#define GPMI_CTRL1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_RSVD1_SHIFT)) & GPMI_CTRL1_RSVD1_MASK)
48567#define GPMI_CTRL1_WRN_DLY_SEL_MASK (0xC00000U)
48568#define GPMI_CTRL1_WRN_DLY_SEL_SHIFT (22U)
48569/*! WRN_DLY_SEL - WRN_DLY_SEL
48570 */
48571#define GPMI_CTRL1_WRN_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRN_DLY_SEL_SHIFT)) & GPMI_CTRL1_WRN_DLY_SEL_MASK)
48572#define GPMI_CTRL1_DECOUPLE_CS_MASK (0x1000000U)
48573#define GPMI_CTRL1_DECOUPLE_CS_SHIFT (24U)
48574/*! DECOUPLE_CS - DECOUPLE_CS
48575 */
48576#define GPMI_CTRL1_DECOUPLE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DECOUPLE_CS_SHIFT)) & GPMI_CTRL1_DECOUPLE_CS_MASK)
48577#define GPMI_CTRL1_SSYNCMODE_MASK (0x2000000U)
48578#define GPMI_CTRL1_SSYNCMODE_SHIFT (25U)
48579/*! SSYNCMODE - SSYNCMODE
48580 */
48581#define GPMI_CTRL1_SSYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNCMODE_SHIFT)) & GPMI_CTRL1_SSYNCMODE_MASK)
48582#define GPMI_CTRL1_UPDATE_CS_MASK (0x4000000U)
48583#define GPMI_CTRL1_UPDATE_CS_SHIFT (26U)
48584/*! UPDATE_CS - UPDATE_CS
48585 */
48586#define GPMI_CTRL1_UPDATE_CS(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_UPDATE_CS_SHIFT)) & GPMI_CTRL1_UPDATE_CS_MASK)
48587#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK (0x8000000U)
48588#define GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT (27U)
48589/*! GPMI_CLK_DIV2_EN - GPMI_CLK_DIV2_EN
48590 * 0b0..internal factor-2 clock divider is disabled
48591 * 0b1..internal factor-2 clock divider is enabled.
48592 */
48593#define GPMI_CTRL1_GPMI_CLK_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_GPMI_CLK_DIV2_EN_SHIFT)) & GPMI_CTRL1_GPMI_CLK_DIV2_EN_MASK)
48594#define GPMI_CTRL1_TOGGLE_MODE_MASK (0x10000000U)
48595#define GPMI_CTRL1_TOGGLE_MODE_SHIFT (28U)
48596/*! TOGGLE_MODE - TOGGLE_MODE
48597 */
48598#define GPMI_CTRL1_TOGGLE_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_TOGGLE_MODE_SHIFT)) & GPMI_CTRL1_TOGGLE_MODE_MASK)
48599#define GPMI_CTRL1_WRITE_CLK_STOP_MASK (0x20000000U)
48600#define GPMI_CTRL1_WRITE_CLK_STOP_SHIFT (29U)
48601/*! WRITE_CLK_STOP - WRITE_CLK_STOP
48602 */
48603#define GPMI_CTRL1_WRITE_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_WRITE_CLK_STOP_SHIFT)) & GPMI_CTRL1_WRITE_CLK_STOP_MASK)
48604#define GPMI_CTRL1_SSYNC_CLK_STOP_MASK (0x40000000U)
48605#define GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT (30U)
48606/*! SSYNC_CLK_STOP - SSYNC_CLK_STOP
48607 */
48608#define GPMI_CTRL1_SSYNC_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_SSYNC_CLK_STOP_SHIFT)) & GPMI_CTRL1_SSYNC_CLK_STOP_MASK)
48609#define GPMI_CTRL1_DEV_CLK_STOP_MASK (0x80000000U)
48610#define GPMI_CTRL1_DEV_CLK_STOP_SHIFT (31U)
48611/*! DEV_CLK_STOP - DEV_CLK_STOP
48612 */
48613#define GPMI_CTRL1_DEV_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL1_DEV_CLK_STOP_SHIFT)) & GPMI_CTRL1_DEV_CLK_STOP_MASK)
48614/*! @} */
48615
48616/*! @name TIMING0 - GPMI Timing Register 0 Description */
48617/*! @{ */
48618#define GPMI_TIMING0_DATA_SETUP_MASK (0xFFU)
48619#define GPMI_TIMING0_DATA_SETUP_SHIFT (0U)
48620/*! DATA_SETUP - DATA_SETUP
48621 */
48622#define GPMI_TIMING0_DATA_SETUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_SETUP_SHIFT)) & GPMI_TIMING0_DATA_SETUP_MASK)
48623#define GPMI_TIMING0_DATA_HOLD_MASK (0xFF00U)
48624#define GPMI_TIMING0_DATA_HOLD_SHIFT (8U)
48625/*! DATA_HOLD - DATA_HOLD
48626 */
48627#define GPMI_TIMING0_DATA_HOLD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_DATA_HOLD_SHIFT)) & GPMI_TIMING0_DATA_HOLD_MASK)
48628#define GPMI_TIMING0_ADDRESS_SETUP_MASK (0xFF0000U)
48629#define GPMI_TIMING0_ADDRESS_SETUP_SHIFT (16U)
48630/*! ADDRESS_SETUP - ADDRESS_SETUP
48631 */
48632#define GPMI_TIMING0_ADDRESS_SETUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_ADDRESS_SETUP_SHIFT)) & GPMI_TIMING0_ADDRESS_SETUP_MASK)
48633#define GPMI_TIMING0_RSVD1_MASK (0xFF000000U)
48634#define GPMI_TIMING0_RSVD1_SHIFT (24U)
48635/*! RSVD1 - RSVD1
48636 */
48637#define GPMI_TIMING0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING0_RSVD1_SHIFT)) & GPMI_TIMING0_RSVD1_MASK)
48638/*! @} */
48639
48640/*! @name TIMING1 - GPMI Timing Register 1 Description */
48641/*! @{ */
48642#define GPMI_TIMING1_RSVD1_MASK (0xFFFFU)
48643#define GPMI_TIMING1_RSVD1_SHIFT (0U)
48644/*! RSVD1 - RSVD1
48645 */
48646#define GPMI_TIMING1_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_RSVD1_SHIFT)) & GPMI_TIMING1_RSVD1_MASK)
48647#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK (0xFFFF0000U)
48648#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT (16U)
48649/*! DEVICE_BUSY_TIMEOUT - DEVICE_BUSY_TIMEOUT
48650 */
48651#define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_SHIFT)) & GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK)
48652/*! @} */
48653
48654/*! @name TIMING2 - GPMI Timing Register 2 Description */
48655/*! @{ */
48656#define GPMI_TIMING2_DATA_PAUSE_MASK (0xFU)
48657#define GPMI_TIMING2_DATA_PAUSE_SHIFT (0U)
48658/*! DATA_PAUSE - DATA_PAUSE
48659 */
48660#define GPMI_TIMING2_DATA_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_DATA_PAUSE_SHIFT)) & GPMI_TIMING2_DATA_PAUSE_MASK)
48661#define GPMI_TIMING2_CMDADD_PAUSE_MASK (0xF0U)
48662#define GPMI_TIMING2_CMDADD_PAUSE_SHIFT (4U)
48663/*! CMDADD_PAUSE - CMDADD_PAUSE
48664 */
48665#define GPMI_TIMING2_CMDADD_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CMDADD_PAUSE_SHIFT)) & GPMI_TIMING2_CMDADD_PAUSE_MASK)
48666#define GPMI_TIMING2_POSTAMBLE_DELAY_MASK (0xF00U)
48667#define GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT (8U)
48668/*! POSTAMBLE_DELAY - POSTAMBLE_DELAY
48669 */
48670#define GPMI_TIMING2_POSTAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_POSTAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_POSTAMBLE_DELAY_MASK)
48671#define GPMI_TIMING2_PREAMBLE_DELAY_MASK (0xF000U)
48672#define GPMI_TIMING2_PREAMBLE_DELAY_SHIFT (12U)
48673/*! PREAMBLE_DELAY - PREAMBLE_DELAY
48674 */
48675#define GPMI_TIMING2_PREAMBLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_PREAMBLE_DELAY_SHIFT)) & GPMI_TIMING2_PREAMBLE_DELAY_MASK)
48676#define GPMI_TIMING2_CE_DELAY_MASK (0x1F0000U)
48677#define GPMI_TIMING2_CE_DELAY_SHIFT (16U)
48678/*! CE_DELAY - CE_DELAY
48679 */
48680#define GPMI_TIMING2_CE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_CE_DELAY_SHIFT)) & GPMI_TIMING2_CE_DELAY_MASK)
48681#define GPMI_TIMING2_RSVD0_MASK (0xE00000U)
48682#define GPMI_TIMING2_RSVD0_SHIFT (21U)
48683/*! RSVD0 - RSVD0
48684 */
48685#define GPMI_TIMING2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_RSVD0_SHIFT)) & GPMI_TIMING2_RSVD0_MASK)
48686#define GPMI_TIMING2_READ_LATENCY_MASK (0x7000000U)
48687#define GPMI_TIMING2_READ_LATENCY_SHIFT (24U)
48688/*! READ_LATENCY - READ_LATENCY
48689 * 0b000..READ LATENCY is 0
48690 * 0b001..READ LATENCY is 1
48691 * 0b010..READ LATENCY is 2
48692 * 0b011..READ LATENCY is 3
48693 * 0b100..READ LATENCY is 4
48694 * 0b101..READ LATENCY is 5
48695 */
48696#define GPMI_TIMING2_READ_LATENCY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_READ_LATENCY_SHIFT)) & GPMI_TIMING2_READ_LATENCY_MASK)
48697#define GPMI_TIMING2_TCR_MASK (0x18000000U)
48698#define GPMI_TIMING2_TCR_SHIFT (27U)
48699/*! TCR - TCR
48700 */
48701#define GPMI_TIMING2_TCR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TCR_SHIFT)) & GPMI_TIMING2_TCR_MASK)
48702#define GPMI_TIMING2_TRPSTH_MASK (0xE0000000U)
48703#define GPMI_TIMING2_TRPSTH_SHIFT (29U)
48704/*! TRPSTH - TRPSTH
48705 */
48706#define GPMI_TIMING2_TRPSTH(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING2_TRPSTH_SHIFT)) & GPMI_TIMING2_TRPSTH_MASK)
48707/*! @} */
48708
48709/*! @name DATA - GPMI DMA Data Transfer Register Description */
48710/*! @{ */
48711#define GPMI_DATA_DATA_MASK (0xFFFFFFFFU)
48712#define GPMI_DATA_DATA_SHIFT (0U)
48713/*! DATA - DATA
48714 */
48715#define GPMI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DATA_DATA_SHIFT)) & GPMI_DATA_DATA_MASK)
48716/*! @} */
48717
48718/*! @name STAT - GPMI Status Register Description */
48719/*! @{ */
48720#define GPMI_STAT_PRESENT_MASK (0x1U)
48721#define GPMI_STAT_PRESENT_SHIFT (0U)
48722/*! PRESENT - PRESENT
48723 * 0b0..GPMI is not present in this product.
48724 * 0b1..GPMI is present is in this product.
48725 */
48726#define GPMI_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_PRESENT_SHIFT)) & GPMI_STAT_PRESENT_MASK)
48727#define GPMI_STAT_FIFO_FULL_MASK (0x2U)
48728#define GPMI_STAT_FIFO_FULL_SHIFT (1U)
48729/*! FIFO_FULL - FIFO_FULL
48730 * 0b0..FIFO is not full.
48731 * 0b1..FIFO is full.
48732 */
48733#define GPMI_STAT_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_FULL_SHIFT)) & GPMI_STAT_FIFO_FULL_MASK)
48734#define GPMI_STAT_FIFO_EMPTY_MASK (0x4U)
48735#define GPMI_STAT_FIFO_EMPTY_SHIFT (2U)
48736/*! FIFO_EMPTY - FIFO_EMPTY
48737 * 0b0..FIFO is not empty.
48738 * 0b1..FIFO is empty.
48739 */
48740#define GPMI_STAT_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_FIFO_EMPTY_SHIFT)) & GPMI_STAT_FIFO_EMPTY_MASK)
48741#define GPMI_STAT_INVALID_BUFFER_MASK_MASK (0x8U)
48742#define GPMI_STAT_INVALID_BUFFER_MASK_SHIFT (3U)
48743/*! INVALID_BUFFER_MASK - INVALID_BUFFER_MASK
48744 * 0b0..ECC Buffer Mask is not invalid.
48745 * 0b1..ECC Buffer Mask is invalid.
48746 */
48747#define GPMI_STAT_INVALID_BUFFER_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_INVALID_BUFFER_MASK_SHIFT)) & GPMI_STAT_INVALID_BUFFER_MASK_MASK)
48748#define GPMI_STAT_ATA_IRQ_MASK (0x10U)
48749#define GPMI_STAT_ATA_IRQ_SHIFT (4U)
48750/*! ATA_IRQ - ATA_IRQ
48751 */
48752#define GPMI_STAT_ATA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_ATA_IRQ_SHIFT)) & GPMI_STAT_ATA_IRQ_MASK)
48753#define GPMI_STAT_RSVD1_MASK (0xE0U)
48754#define GPMI_STAT_RSVD1_SHIFT (5U)
48755/*! RSVD1 - RSVD1
48756 */
48757#define GPMI_STAT_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RSVD1_SHIFT)) & GPMI_STAT_RSVD1_MASK)
48758#define GPMI_STAT_DEV0_ERROR_MASK (0x100U)
48759#define GPMI_STAT_DEV0_ERROR_SHIFT (8U)
48760/*! DEV0_ERROR - DEV0_ERROR
48761 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 0.
48762 * 0b1..An Error has occurred on ATA/NAND Device accessed by
48763 */
48764#define GPMI_STAT_DEV0_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV0_ERROR_SHIFT)) & GPMI_STAT_DEV0_ERROR_MASK)
48765#define GPMI_STAT_DEV1_ERROR_MASK (0x200U)
48766#define GPMI_STAT_DEV1_ERROR_SHIFT (9U)
48767/*! DEV1_ERROR - DEV1_ERROR
48768 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 1.
48769 * 0b1..An Error has occurred on ATA/NAND Device accessed by
48770 */
48771#define GPMI_STAT_DEV1_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV1_ERROR_SHIFT)) & GPMI_STAT_DEV1_ERROR_MASK)
48772#define GPMI_STAT_DEV2_ERROR_MASK (0x400U)
48773#define GPMI_STAT_DEV2_ERROR_SHIFT (10U)
48774/*! DEV2_ERROR - DEV2_ERROR
48775 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 2.
48776 * 0b1..An Error has occurred on ATA/NAND Device accessed by
48777 */
48778#define GPMI_STAT_DEV2_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV2_ERROR_SHIFT)) & GPMI_STAT_DEV2_ERROR_MASK)
48779#define GPMI_STAT_DEV3_ERROR_MASK (0x800U)
48780#define GPMI_STAT_DEV3_ERROR_SHIFT (11U)
48781/*! DEV3_ERROR - DEV3_ERROR
48782 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 3.
48783 * 0b1..An Error has occurred on ATA/NAND Device accessed by
48784 */
48785#define GPMI_STAT_DEV3_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV3_ERROR_SHIFT)) & GPMI_STAT_DEV3_ERROR_MASK)
48786#define GPMI_STAT_DEV4_ERROR_MASK (0x1000U)
48787#define GPMI_STAT_DEV4_ERROR_SHIFT (12U)
48788/*! DEV4_ERROR - DEV4_ERROR
48789 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 4.
48790 * 0b1..An Error has occurred on ATA/NAND Device accessed by
48791 */
48792#define GPMI_STAT_DEV4_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV4_ERROR_SHIFT)) & GPMI_STAT_DEV4_ERROR_MASK)
48793#define GPMI_STAT_DEV5_ERROR_MASK (0x2000U)
48794#define GPMI_STAT_DEV5_ERROR_SHIFT (13U)
48795/*! DEV5_ERROR - DEV5_ERROR
48796 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 5.
48797 * 0b1..An Error has occurred on ATA/NAND Device accessed by
48798 */
48799#define GPMI_STAT_DEV5_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV5_ERROR_SHIFT)) & GPMI_STAT_DEV5_ERROR_MASK)
48800#define GPMI_STAT_DEV6_ERROR_MASK (0x4000U)
48801#define GPMI_STAT_DEV6_ERROR_SHIFT (14U)
48802/*! DEV6_ERROR - DEV6_ERROR
48803 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 6.
48804 * 0b1..An Error has occurred on ATA/NAND Device accessed by
48805 */
48806#define GPMI_STAT_DEV6_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV6_ERROR_SHIFT)) & GPMI_STAT_DEV6_ERROR_MASK)
48807#define GPMI_STAT_DEV7_ERROR_MASK (0x8000U)
48808#define GPMI_STAT_DEV7_ERROR_SHIFT (15U)
48809/*! DEV7_ERROR - DEV7_ERROR
48810 * 0b0..No error condition present on ATA/NAND Device accessed by DMA channel 7.
48811 * 0b1..An Error has occurred on ATA/NAND Device accessed by
48812 */
48813#define GPMI_STAT_DEV7_ERROR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_DEV7_ERROR_SHIFT)) & GPMI_STAT_DEV7_ERROR_MASK)
48814#define GPMI_STAT_RDY_TIMEOUT_MASK (0xFF0000U)
48815#define GPMI_STAT_RDY_TIMEOUT_SHIFT (16U)
48816/*! RDY_TIMEOUT - RDY_TIMEOUT
48817 */
48818#define GPMI_STAT_RDY_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_RDY_TIMEOUT_SHIFT)) & GPMI_STAT_RDY_TIMEOUT_MASK)
48819#define GPMI_STAT_READY_BUSY_MASK (0xFF000000U)
48820#define GPMI_STAT_READY_BUSY_SHIFT (24U)
48821/*! READY_BUSY - READY_BUSY
48822 */
48823#define GPMI_STAT_READY_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_STAT_READY_BUSY_SHIFT)) & GPMI_STAT_READY_BUSY_MASK)
48824/*! @} */
48825
48826/*! @name DEBUG - GPMI Debug Information Register Description */
48827/*! @{ */
48828#define GPMI_DEBUG_CMD_END_MASK (0xFFU)
48829#define GPMI_DEBUG_CMD_END_SHIFT (0U)
48830/*! CMD_END - CMD_END
48831 */
48832#define GPMI_DEBUG_CMD_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_CMD_END_SHIFT)) & GPMI_DEBUG_CMD_END_MASK)
48833#define GPMI_DEBUG_DMAREQ_MASK (0xFF00U)
48834#define GPMI_DEBUG_DMAREQ_SHIFT (8U)
48835/*! DMAREQ - DMAREQ
48836 */
48837#define GPMI_DEBUG_DMAREQ(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMAREQ_SHIFT)) & GPMI_DEBUG_DMAREQ_MASK)
48838#define GPMI_DEBUG_DMA_SENSE_MASK (0xFF0000U)
48839#define GPMI_DEBUG_DMA_SENSE_SHIFT (16U)
48840/*! DMA_SENSE - DMA_SENSE
48841 */
48842#define GPMI_DEBUG_DMA_SENSE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_DMA_SENSE_SHIFT)) & GPMI_DEBUG_DMA_SENSE_MASK)
48843#define GPMI_DEBUG_WAIT_FOR_READY_END_MASK (0xFF000000U)
48844#define GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT (24U)
48845/*! WAIT_FOR_READY_END - WAIT_FOR_READY_END
48846 */
48847#define GPMI_DEBUG_WAIT_FOR_READY_END(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG_WAIT_FOR_READY_END_SHIFT)) & GPMI_DEBUG_WAIT_FOR_READY_END_MASK)
48848/*! @} */
48849
48850/*! @name VERSION - GPMI Version Register Description */
48851/*! @{ */
48852#define GPMI_VERSION_STEP_MASK (0xFFFFU)
48853#define GPMI_VERSION_STEP_SHIFT (0U)
48854/*! STEP - STEP
48855 */
48856#define GPMI_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_STEP_SHIFT)) & GPMI_VERSION_STEP_MASK)
48857#define GPMI_VERSION_MINOR_MASK (0xFF0000U)
48858#define GPMI_VERSION_MINOR_SHIFT (16U)
48859/*! MINOR - MINOR
48860 */
48861#define GPMI_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MINOR_SHIFT)) & GPMI_VERSION_MINOR_MASK)
48862#define GPMI_VERSION_MAJOR_MASK (0xFF000000U)
48863#define GPMI_VERSION_MAJOR_SHIFT (24U)
48864/*! MAJOR - MAJOR
48865 */
48866#define GPMI_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_VERSION_MAJOR_SHIFT)) & GPMI_VERSION_MAJOR_MASK)
48867/*! @} */
48868
48869/*! @name DEBUG2 - GPMI Debug2 Information Register Description */
48870/*! @{ */
48871#define GPMI_DEBUG2_RDN_TAP_MASK (0x3FU)
48872#define GPMI_DEBUG2_RDN_TAP_SHIFT (0U)
48873/*! RDN_TAP - RDN_TAP
48874 */
48875#define GPMI_DEBUG2_RDN_TAP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RDN_TAP_SHIFT)) & GPMI_DEBUG2_RDN_TAP_MASK)
48876#define GPMI_DEBUG2_UPDATE_WINDOW_MASK (0x40U)
48877#define GPMI_DEBUG2_UPDATE_WINDOW_SHIFT (6U)
48878/*! UPDATE_WINDOW - UPDATE_WINDOW
48879 */
48880#define GPMI_DEBUG2_UPDATE_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UPDATE_WINDOW_SHIFT)) & GPMI_DEBUG2_UPDATE_WINDOW_MASK)
48881#define GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK (0x80U)
48882#define GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT (7U)
48883/*! VIEW_DELAYED_RDN - VIEW_DELAYED_RDN
48884 */
48885#define GPMI_DEBUG2_VIEW_DELAYED_RDN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_VIEW_DELAYED_RDN_SHIFT)) & GPMI_DEBUG2_VIEW_DELAYED_RDN_MASK)
48886#define GPMI_DEBUG2_SYND2GPMI_READY_MASK (0x100U)
48887#define GPMI_DEBUG2_SYND2GPMI_READY_SHIFT (8U)
48888/*! SYND2GPMI_READY - SYND2GPMI_READY
48889 */
48890#define GPMI_DEBUG2_SYND2GPMI_READY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_READY_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_READY_MASK)
48891#define GPMI_DEBUG2_SYND2GPMI_VALID_MASK (0x200U)
48892#define GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT (9U)
48893/*! SYND2GPMI_VALID - SYND2GPMI_VALID
48894 */
48895#define GPMI_DEBUG2_SYND2GPMI_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_VALID_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_VALID_MASK)
48896#define GPMI_DEBUG2_GPMI2SYND_READY_MASK (0x400U)
48897#define GPMI_DEBUG2_GPMI2SYND_READY_SHIFT (10U)
48898/*! GPMI2SYND_READY - GPMI2SYND_READY
48899 */
48900#define GPMI_DEBUG2_GPMI2SYND_READY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_READY_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_READY_MASK)
48901#define GPMI_DEBUG2_GPMI2SYND_VALID_MASK (0x800U)
48902#define GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT (11U)
48903/*! GPMI2SYND_VALID - GPMI2SYND_VALID
48904 */
48905#define GPMI_DEBUG2_GPMI2SYND_VALID(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_GPMI2SYND_VALID_SHIFT)) & GPMI_DEBUG2_GPMI2SYND_VALID_MASK)
48906#define GPMI_DEBUG2_SYND2GPMI_BE_MASK (0xF000U)
48907#define GPMI_DEBUG2_SYND2GPMI_BE_SHIFT (12U)
48908/*! SYND2GPMI_BE - SYND2GPMI_BE
48909 */
48910#define GPMI_DEBUG2_SYND2GPMI_BE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_SYND2GPMI_BE_SHIFT)) & GPMI_DEBUG2_SYND2GPMI_BE_MASK)
48911#define GPMI_DEBUG2_MAIN_STATE_MASK (0xF0000U)
48912#define GPMI_DEBUG2_MAIN_STATE_SHIFT (16U)
48913/*! MAIN_STATE - MAIN_STATE
48914 */
48915#define GPMI_DEBUG2_MAIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_MAIN_STATE_SHIFT)) & GPMI_DEBUG2_MAIN_STATE_MASK)
48916#define GPMI_DEBUG2_PIN_STATE_MASK (0x700000U)
48917#define GPMI_DEBUG2_PIN_STATE_SHIFT (20U)
48918/*! PIN_STATE - PIN_STATE
48919 */
48920#define GPMI_DEBUG2_PIN_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_PIN_STATE_SHIFT)) & GPMI_DEBUG2_PIN_STATE_MASK)
48921#define GPMI_DEBUG2_BUSY_MASK (0x800000U)
48922#define GPMI_DEBUG2_BUSY_SHIFT (23U)
48923/*! BUSY - BUSY
48924 */
48925#define GPMI_DEBUG2_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_BUSY_SHIFT)) & GPMI_DEBUG2_BUSY_MASK)
48926#define GPMI_DEBUG2_UDMA_STATE_MASK (0xF000000U)
48927#define GPMI_DEBUG2_UDMA_STATE_SHIFT (24U)
48928/*! UDMA_STATE - UDMA_STATE
48929 */
48930#define GPMI_DEBUG2_UDMA_STATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_UDMA_STATE_SHIFT)) & GPMI_DEBUG2_UDMA_STATE_MASK)
48931#define GPMI_DEBUG2_RSVD1_MASK (0xF0000000U)
48932#define GPMI_DEBUG2_RSVD1_SHIFT (28U)
48933/*! RSVD1 - RSVD1
48934 */
48935#define GPMI_DEBUG2_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG2_RSVD1_SHIFT)) & GPMI_DEBUG2_RSVD1_MASK)
48936/*! @} */
48937
48938/*! @name DEBUG3 - GPMI Debug3 Information Register Description */
48939/*! @{ */
48940#define GPMI_DEBUG3_DEV_WORD_CNTR_MASK (0xFFFFU)
48941#define GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT (0U)
48942/*! DEV_WORD_CNTR - DEV_WORD_CNTR
48943 */
48944#define GPMI_DEBUG3_DEV_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_DEV_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_DEV_WORD_CNTR_MASK)
48945#define GPMI_DEBUG3_APB_WORD_CNTR_MASK (0xFFFF0000U)
48946#define GPMI_DEBUG3_APB_WORD_CNTR_SHIFT (16U)
48947/*! APB_WORD_CNTR - APB_WORD_CNTR
48948 */
48949#define GPMI_DEBUG3_APB_WORD_CNTR(x) (((uint32_t)(((uint32_t)(x)) << GPMI_DEBUG3_APB_WORD_CNTR_SHIFT)) & GPMI_DEBUG3_APB_WORD_CNTR_MASK)
48950/*! @} */
48951
48952/*! @name READ_DDR_DLL_CTRL - GPMI Double Rate Read DLL Control Register Description */
48953/*! @{ */
48954#define GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK (0x1U)
48955#define GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT (0U)
48956/*! ENABLE - ENABLE
48957 */
48958#define GPMI_READ_DDR_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_ENABLE_MASK)
48959#define GPMI_READ_DDR_DLL_CTRL_RESET_MASK (0x2U)
48960#define GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT (1U)
48961/*! RESET - RESET
48962 */
48963#define GPMI_READ_DDR_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RESET_MASK)
48964#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
48965#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
48966/*! SLV_FORCE_UPD - SLV_FORCE_UPD
48967 */
48968#define GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK)
48969#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
48970#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
48971/*! SLV_DLY_TARGET - SLV_DLY_TARGET
48972 */
48973#define GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK)
48974#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
48975#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
48976/*! GATE_UPDATE - GATE_UPDATE
48977 */
48978#define GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_GATE_UPDATE_MASK)
48979#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U)
48980#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U)
48981/*! REFCLK_ON - REFCLK_ON
48982 */
48983#define GPMI_READ_DDR_DLL_CTRL_REFCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REFCLK_ON_MASK)
48984#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U)
48985#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U)
48986/*! SLV_OVERRIDE - SLV_OVERRIDE
48987 */
48988#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_MASK)
48989#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U)
48990#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U)
48991/*! SLV_OVERRIDE_VAL - SLV_OVERRIDE_VAL
48992 */
48993#define GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
48994#define GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U)
48995#define GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT (18U)
48996/*! RSVD1 - RSVD1
48997 */
48998#define GPMI_READ_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_RSVD1_MASK)
48999#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
49000#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
49001/*! SLV_UPDATE_INT - SLV_UPDATE_INT
49002 */
49003#define GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK)
49004#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
49005#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
49006/*! REF_UPDATE_INT - REF_UPDATE_INT
49007 */
49008#define GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_READ_DDR_DLL_CTRL_REF_UPDATE_INT_MASK)
49009/*! @} */
49010
49011/*! @name WRITE_DDR_DLL_CTRL - GPMI Double Rate Write DLL Control Register Description */
49012/*! @{ */
49013#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK (0x1U)
49014#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT (0U)
49015/*! ENABLE - ENABLE
49016 */
49017#define GPMI_WRITE_DDR_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_ENABLE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_ENABLE_MASK)
49018#define GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK (0x2U)
49019#define GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT (1U)
49020/*! RESET - RESET
49021 */
49022#define GPMI_WRITE_DDR_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RESET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RESET_MASK)
49023#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
49024#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
49025/*! SLV_FORCE_UPD - SLV_FORCE_UPD
49026 */
49027#define GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_FORCE_UPD_MASK)
49028#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
49029#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
49030/*! SLV_DLY_TARGET - SLV_DLY_TARGET
49031 */
49032#define GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_DLY_TARGET_MASK)
49033#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
49034#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
49035/*! GATE_UPDATE - GATE_UPDATE
49036 */
49037#define GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_GATE_UPDATE_MASK)
49038#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK (0x100U)
49039#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT (8U)
49040/*! REFCLK_ON - REFCLK_ON
49041 */
49042#define GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REFCLK_ON_MASK)
49043#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK (0x200U)
49044#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT (9U)
49045/*! SLV_OVERRIDE - SLV_OVERRIDE
49046 */
49047#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_MASK)
49048#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0x3FC00U)
49049#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (10U)
49050/*! SLV_OVERRIDE_VAL - SLV_OVERRIDE_VAL
49051 */
49052#define GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
49053#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK (0xC0000U)
49054#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT (18U)
49055/*! RSVD1 - RSVD1
49056 */
49057#define GPMI_WRITE_DDR_DLL_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_RSVD1_MASK)
49058#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
49059#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
49060/*! SLV_UPDATE_INT - SLV_UPDATE_INT
49061 */
49062#define GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_SLV_UPDATE_INT_MASK)
49063#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
49064#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
49065/*! REF_UPDATE_INT - REF_UPDATE_INT
49066 */
49067#define GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & GPMI_WRITE_DDR_DLL_CTRL_REF_UPDATE_INT_MASK)
49068/*! @} */
49069
49070/*! @name READ_DDR_DLL_STS - GPMI Double Rate Read DLL Status Register Description */
49071/*! @{ */
49072#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK (0x1U)
49073#define GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT (0U)
49074/*! SLV_LOCK - SLV_LOCK
49075 */
49076#define GPMI_READ_DDR_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_LOCK_MASK)
49077#define GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU)
49078#define GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT (1U)
49079/*! SLV_SEL - SLV_SEL
49080 */
49081#define GPMI_READ_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_SLV_SEL_MASK)
49082#define GPMI_READ_DDR_DLL_STS_RSVD0_MASK (0xFE00U)
49083#define GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT (9U)
49084/*! RSVD0 - RSVD0
49085 */
49086#define GPMI_READ_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD0_MASK)
49087#define GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK (0x10000U)
49088#define GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT (16U)
49089/*! REF_LOCK - REF_LOCK
49090 */
49091#define GPMI_READ_DDR_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_LOCK_MASK)
49092#define GPMI_READ_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U)
49093#define GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT (17U)
49094/*! REF_SEL - REF_SEL
49095 */
49096#define GPMI_READ_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_READ_DDR_DLL_STS_REF_SEL_MASK)
49097#define GPMI_READ_DDR_DLL_STS_RSVD1_MASK (0xFE000000U)
49098#define GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT (25U)
49099/*! RSVD1 - RSVD1
49100 */
49101#define GPMI_READ_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_READ_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_READ_DDR_DLL_STS_RSVD1_MASK)
49102/*! @} */
49103
49104/*! @name WRITE_DDR_DLL_STS - GPMI Double Rate Write DLL Status Register Description */
49105/*! @{ */
49106#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK (0x1U)
49107#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT (0U)
49108/*! SLV_LOCK - SLV_LOCK
49109 */
49110#define GPMI_WRITE_DDR_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_LOCK_MASK)
49111#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK (0x1FEU)
49112#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT (1U)
49113/*! SLV_SEL - SLV_SEL
49114 */
49115#define GPMI_WRITE_DDR_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_SLV_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_SLV_SEL_MASK)
49116#define GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK (0xFE00U)
49117#define GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT (9U)
49118/*! RSVD0 - RSVD0
49119 */
49120#define GPMI_WRITE_DDR_DLL_STS_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD0_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD0_MASK)
49121#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK (0x10000U)
49122#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT (16U)
49123/*! REF_LOCK - REF_LOCK
49124 */
49125#define GPMI_WRITE_DDR_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_LOCK_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_LOCK_MASK)
49126#define GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK (0x1FE0000U)
49127#define GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT (17U)
49128/*! REF_SEL - REF_SEL
49129 */
49130#define GPMI_WRITE_DDR_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_REF_SEL_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_REF_SEL_MASK)
49131#define GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK (0xFE000000U)
49132#define GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT (25U)
49133/*! RSVD1 - RSVD1
49134 */
49135#define GPMI_WRITE_DDR_DLL_STS_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_WRITE_DDR_DLL_STS_RSVD1_SHIFT)) & GPMI_WRITE_DDR_DLL_STS_RSVD1_MASK)
49136/*! @} */
49137
49138/*! @name TIMING3 - GPMI Timing Register 3 Description */
49139/*! @{ */
49140#define GPMI_TIMING3_TWWARMUP_MASK (0x1FU)
49141#define GPMI_TIMING3_TWWARMUP_SHIFT (0U)
49142/*! TWWARMUP - TWWARMUP
49143 */
49144#define GPMI_TIMING3_TWWARMUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING3_TWWARMUP_SHIFT)) & GPMI_TIMING3_TWWARMUP_MASK)
49145#define GPMI_TIMING3_RSVD0_MASK (0xE0U)
49146#define GPMI_TIMING3_RSVD0_SHIFT (5U)
49147/*! RSVD0 - RSVD0
49148 */
49149#define GPMI_TIMING3_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING3_RSVD0_SHIFT)) & GPMI_TIMING3_RSVD0_MASK)
49150#define GPMI_TIMING3_TRWARMUP_MASK (0x1F00U)
49151#define GPMI_TIMING3_TRWARMUP_SHIFT (8U)
49152/*! TRWARMUP - TRWARMUP
49153 */
49154#define GPMI_TIMING3_TRWARMUP(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING3_TRWARMUP_SHIFT)) & GPMI_TIMING3_TRWARMUP_MASK)
49155#define GPMI_TIMING3_RSVD1_MASK (0xFFFFE000U)
49156#define GPMI_TIMING3_RSVD1_SHIFT (13U)
49157/*! RSVD1 - RSVD1
49158 */
49159#define GPMI_TIMING3_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << GPMI_TIMING3_RSVD1_SHIFT)) & GPMI_TIMING3_RSVD1_MASK)
49160/*! @} */
49161
49162/*! @name CTRL2 - GPMI Control Register 2 Description */
49163/*! @{ */
49164#define GPMI_CTRL2_NVDDR2_MODE_MASK (0x1U)
49165#define GPMI_CTRL2_NVDDR2_MODE_SHIFT (0U)
49166/*! NVDDR2_MODE - NVDDR2_MODE
49167 */
49168#define GPMI_CTRL2_NVDDR2_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL2_NVDDR2_MODE_SHIFT)) & GPMI_CTRL2_NVDDR2_MODE_MASK)
49169#define GPMI_CTRL2_TOGGLE20_MODE_MASK (0x2U)
49170#define GPMI_CTRL2_TOGGLE20_MODE_SHIFT (1U)
49171/*! TOGGLE20_MODE - TOGGLE20_MODE
49172 */
49173#define GPMI_CTRL2_TOGGLE20_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL2_TOGGLE20_MODE_SHIFT)) & GPMI_CTRL2_TOGGLE20_MODE_MASK)
49174#define GPMI_CTRL2_WARMUP_EN_MASK (0x4U)
49175#define GPMI_CTRL2_WARMUP_EN_SHIFT (2U)
49176/*! WARMUP_EN - WARMUP_EN
49177 */
49178#define GPMI_CTRL2_WARMUP_EN(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL2_WARMUP_EN_SHIFT)) & GPMI_CTRL2_WARMUP_EN_MASK)
49179#define GPMI_CTRL2_CEN_REDUCTION_MASK (0x8U)
49180#define GPMI_CTRL2_CEN_REDUCTION_SHIFT (3U)
49181/*! CEN_REDUCTION - CEN_REDUCTION
49182 */
49183#define GPMI_CTRL2_CEN_REDUCTION(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL2_CEN_REDUCTION_SHIFT)) & GPMI_CTRL2_CEN_REDUCTION_MASK)
49184#define GPMI_CTRL2_RSVD0_MASK (0xFFFFFFF0U)
49185#define GPMI_CTRL2_RSVD0_SHIFT (4U)
49186/*! RSVD0 - RSVD0
49187 */
49188#define GPMI_CTRL2_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << GPMI_CTRL2_RSVD0_SHIFT)) & GPMI_CTRL2_RSVD0_MASK)
49189/*! @} */
49190
49191
49192/*!
49193 * @}
49194 */ /* end of group GPMI_Register_Masks */
49195
49196
49197/* GPMI - Peripheral instance base addresses */
49198/** Peripheral CONNECTIVITY__GPMI base address */
49199#define CONNECTIVITY__GPMI_BASE (0x5B812000u)
49200/** Peripheral CONNECTIVITY__GPMI base pointer */
49201#define CONNECTIVITY__GPMI ((GPMI_Type *)CONNECTIVITY__GPMI_BASE)
49202/** Array initializer of GPMI peripheral base addresses */
49203#define GPMI_BASE_ADDRS { CONNECTIVITY__GPMI_BASE }
49204/** Array initializer of GPMI peripheral base pointers */
49205#define GPMI_BASE_PTRS { CONNECTIVITY__GPMI }
49206
49207/*!
49208 * @}
49209 */ /* end of group GPMI_Peripheral_Access_Layer */
49210
49211
49212/* ----------------------------------------------------------------------------
49213 -- GPT Peripheral Access Layer
49214 ---------------------------------------------------------------------------- */
49215
49216/*!
49217 * @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer
49218 * @{
49219 */
49220
49221/** GPT - Register Layout Typedef */
49222typedef struct {
49223 __IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */
49224 __IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */
49225 __IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */
49226 __IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */
49227 __IO uint32_t OCR[3]; /**< GPT Output Compare Register 1..GPT Output Compare Register 3, array offset: 0x10, array step: 0x4 */
49228 __I uint32_t ICR[2]; /**< GPT Input Capture Register 1..GPT Input Capture Register 2, array offset: 0x1C, array step: 0x4 */
49229 __I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */
49230} GPT_Type;
49231
49232/* ----------------------------------------------------------------------------
49233 -- GPT Register Masks
49234 ---------------------------------------------------------------------------- */
49235
49236/*!
49237 * @addtogroup GPT_Register_Masks GPT Register Masks
49238 * @{
49239 */
49240
49241/*! @name CR - GPT Control Register */
49242/*! @{ */
49243#define GPT_CR_EN_MASK (0x1U)
49244#define GPT_CR_EN_SHIFT (0U)
49245/*! EN - EN
49246 * 0b0..GPT is disabled.
49247 * 0b1..GPT is enabled.
49248 */
49249#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
49250#define GPT_CR_ENMOD_MASK (0x2U)
49251#define GPT_CR_ENMOD_SHIFT (1U)
49252/*! ENMOD - ENMOD
49253 * 0b0..GPT counter will retain its value when it is disabled.
49254 * 0b1..GPT counter value is reset to 0 when it is disabled.
49255 */
49256#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
49257#define GPT_CR_DBGEN_MASK (0x4U)
49258#define GPT_CR_DBGEN_SHIFT (2U)
49259/*! DBGEN - DBGEN
49260 * 0b0..GPT is disabled in debug mode.
49261 * 0b1..GPT is enabled in debug mode.
49262 */
49263#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
49264#define GPT_CR_WAITEN_MASK (0x8U)
49265#define GPT_CR_WAITEN_SHIFT (3U)
49266/*! WAITEN - WAITEN
49267 * 0b0..GPT is disabled in wait mode.
49268 * 0b1..GPT is enabled in wait mode.
49269 */
49270#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
49271#define GPT_CR_DOZEEN_MASK (0x10U)
49272#define GPT_CR_DOZEEN_SHIFT (4U)
49273/*! DOZEEN - DOZEEN
49274 * 0b0..GPT is disabled in doze mode.
49275 * 0b1..GPT is enabled in doze mode.
49276 */
49277#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
49278#define GPT_CR_STOPEN_MASK (0x20U)
49279#define GPT_CR_STOPEN_SHIFT (5U)
49280/*! STOPEN - STOPEN
49281 * 0b0..GPT is disabled in Stop mode.
49282 * 0b1..GPT is enabled in Stop mode.
49283 */
49284#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
49285#define GPT_CR_CLKSRC_MASK (0x1C0U)
49286#define GPT_CR_CLKSRC_SHIFT (6U)
49287/*! CLKSRC - CLKSRC
49288 * 0b000..No clock
49289 * 0b001..Peripheral Clock (ipg_clk)
49290 * 0b010..High Frequency Reference Clock (ipg_clk_highfreq)
49291 * 0b011..External Clock
49292 * 0b100..Low Frequency Reference Clock (ipg_clk_32k)
49293 * 0b101..Crystal oscillator as Reference Clock (ipg_clk_24M)
49294 */
49295#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
49296#define GPT_CR_FRR_MASK (0x200U)
49297#define GPT_CR_FRR_SHIFT (9U)
49298/*! FRR - FRR
49299 * 0b0..Restart mode
49300 * 0b1..Free-Run mode
49301 */
49302#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
49303#define GPT_CR_EN_24M_MASK (0x400U)
49304#define GPT_CR_EN_24M_SHIFT (10U)
49305/*! EN_24M - EN_24M
49306 * 0b0..24M clock disabled
49307 * 0b1..24M clock enabled
49308 */
49309#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
49310#define GPT_CR_SWR_MASK (0x8000U)
49311#define GPT_CR_SWR_SHIFT (15U)
49312/*! SWR - SWR
49313 * 0b0..GPT is not in reset state
49314 * 0b1..GPT is in reset state
49315 */
49316#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
49317#define GPT_CR_IM1_MASK (0x30000U)
49318#define GPT_CR_IM1_SHIFT (16U)
49319/*! IM1 - IM1
49320 */
49321#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
49322#define GPT_CR_IM2_MASK (0xC0000U)
49323#define GPT_CR_IM2_SHIFT (18U)
49324/*! IM2 - IM2
49325 * 0b00..capture disabled
49326 * 0b01..capture on rising edge only
49327 * 0b10..capture on falling edge only
49328 * 0b11..capture on both edges
49329 */
49330#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
49331#define GPT_CR_OM1_MASK (0x700000U)
49332#define GPT_CR_OM1_SHIFT (20U)
49333/*! OM1 - OM1
49334 */
49335#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
49336#define GPT_CR_OM2_MASK (0x3800000U)
49337#define GPT_CR_OM2_SHIFT (23U)
49338/*! OM2 - OM2
49339 */
49340#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
49341#define GPT_CR_OM3_MASK (0x1C000000U)
49342#define GPT_CR_OM3_SHIFT (26U)
49343/*! OM3 - OM3
49344 * 0b000..Output disconnected. No response on pin.
49345 * 0b001..Toggle output pin
49346 * 0b010..Clear output pin
49347 * 0b011..Set output pin
49348 * 0b1xx..Generate an active low pulse (that is one input clock wide) on the output pin.
49349 */
49350#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
49351#define GPT_CR_FO1_MASK (0x20000000U)
49352#define GPT_CR_FO1_SHIFT (29U)
49353/*! FO1 - FO1
49354 */
49355#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
49356#define GPT_CR_FO2_MASK (0x40000000U)
49357#define GPT_CR_FO2_SHIFT (30U)
49358/*! FO2 - FO2
49359 */
49360#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
49361#define GPT_CR_FO3_MASK (0x80000000U)
49362#define GPT_CR_FO3_SHIFT (31U)
49363/*! FO3 - FO3
49364 * 0b0..Writing a 0 has no effect.
49365 * 0b1..Causes the programmed pin action on the timer Output Compare n pin; the OFn flag is not set.
49366 */
49367#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
49368/*! @} */
49369
49370/*! @name PR - GPT Prescaler Register */
49371/*! @{ */
49372#define GPT_PR_PRESCALER_MASK (0xFFFU)
49373#define GPT_PR_PRESCALER_SHIFT (0U)
49374/*! PRESCALER - PRESCALER
49375 * 0b000000000000..Divide by 1
49376 * 0b000000000001..Divide by 2
49377 * 0b111111111111..Divide by 4096
49378 */
49379#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
49380#define GPT_PR_PRESCALER24M_MASK (0xF000U)
49381#define GPT_PR_PRESCALER24M_SHIFT (12U)
49382/*! PRESCALER24M - PRESCALER24M
49383 * 0b0000..Divide by 1
49384 * 0b0001..Divide by 2
49385 * 0b1111..Divide by 16
49386 */
49387#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
49388/*! @} */
49389
49390/*! @name SR - GPT Status Register */
49391/*! @{ */
49392#define GPT_SR_OF1_MASK (0x1U)
49393#define GPT_SR_OF1_SHIFT (0U)
49394/*! OF1 - OF1
49395 */
49396#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
49397#define GPT_SR_OF2_MASK (0x2U)
49398#define GPT_SR_OF2_SHIFT (1U)
49399/*! OF2 - OF2
49400 */
49401#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
49402#define GPT_SR_OF3_MASK (0x4U)
49403#define GPT_SR_OF3_SHIFT (2U)
49404/*! OF3 - OF3
49405 * 0b0..Compare event has not occurred.
49406 * 0b1..Compare event has occurred.
49407 */
49408#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
49409#define GPT_SR_IF1_MASK (0x8U)
49410#define GPT_SR_IF1_SHIFT (3U)
49411/*! IF1 - IF1
49412 */
49413#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
49414#define GPT_SR_IF2_MASK (0x10U)
49415#define GPT_SR_IF2_SHIFT (4U)
49416/*! IF2 - IF2
49417 * 0b0..Capture event has not occurred.
49418 * 0b1..Capture event has occurred.
49419 */
49420#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
49421#define GPT_SR_ROV_MASK (0x20U)
49422#define GPT_SR_ROV_SHIFT (5U)
49423/*! ROV - ROV
49424 * 0b0..Rollover has not occurred.
49425 * 0b1..Rollover has occurred.
49426 */
49427#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
49428/*! @} */
49429
49430/*! @name IR - GPT Interrupt Register */
49431/*! @{ */
49432#define GPT_IR_OF1IE_MASK (0x1U)
49433#define GPT_IR_OF1IE_SHIFT (0U)
49434/*! OF1IE - OF1IE
49435 */
49436#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
49437#define GPT_IR_OF2IE_MASK (0x2U)
49438#define GPT_IR_OF2IE_SHIFT (1U)
49439/*! OF2IE - OF2IE
49440 */
49441#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
49442#define GPT_IR_OF3IE_MASK (0x4U)
49443#define GPT_IR_OF3IE_SHIFT (2U)
49444/*! OF3IE - OF3IE
49445 * 0b0..Output Compare Channel n interrupt is disabled.
49446 * 0b1..Output Compare Channel n interrupt is enabled.
49447 */
49448#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
49449#define GPT_IR_IF1IE_MASK (0x8U)
49450#define GPT_IR_IF1IE_SHIFT (3U)
49451/*! IF1IE - IF1IE
49452 */
49453#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
49454#define GPT_IR_IF2IE_MASK (0x10U)
49455#define GPT_IR_IF2IE_SHIFT (4U)
49456/*! IF2IE - IF2IE
49457 * 0b0..IF2IE Input Capture n Interrupt Enable is disabled.
49458 * 0b1..IF2IE Input Capture n Interrupt Enable is enabled.
49459 */
49460#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
49461#define GPT_IR_ROVIE_MASK (0x20U)
49462#define GPT_IR_ROVIE_SHIFT (5U)
49463/*! ROVIE - ROVIE
49464 * 0b0..Rollover interrupt is disabled.
49465 * 0b1..Rollover interrupt enabled.
49466 */
49467#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
49468/*! @} */
49469
49470/*! @name OCR - GPT Output Compare Register 1..GPT Output Compare Register 3 */
49471/*! @{ */
49472#define GPT_OCR_COMP_MASK (0xFFFFFFFFU)
49473#define GPT_OCR_COMP_SHIFT (0U)
49474/*! COMP - COMP
49475 */
49476#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
49477/*! @} */
49478
49479/* The count of GPT_OCR */
49480#define GPT_OCR_COUNT (3U)
49481
49482/*! @name ICR - GPT Input Capture Register 1..GPT Input Capture Register 2 */
49483/*! @{ */
49484#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU)
49485#define GPT_ICR_CAPT_SHIFT (0U)
49486/*! CAPT - CAPT
49487 */
49488#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
49489/*! @} */
49490
49491/* The count of GPT_ICR */
49492#define GPT_ICR_COUNT (2U)
49493
49494/*! @name CNT - GPT Counter Register */
49495/*! @{ */
49496#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU)
49497#define GPT_CNT_COUNT_SHIFT (0U)
49498/*! COUNT - COUNT
49499 */
49500#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)
49501/*! @} */
49502
49503
49504/*!
49505 * @}
49506 */ /* end of group GPT_Register_Masks */
49507
49508
49509/* GPT - Peripheral instance base addresses */
49510/** Peripheral ADMA__GPT0 base address */
49511#define ADMA__GPT0_BASE (0x590B0000u)
49512/** Peripheral ADMA__GPT0 base pointer */
49513#define ADMA__GPT0 ((GPT_Type *)ADMA__GPT0_BASE)
49514/** Peripheral ADMA__GPT1 base address */
49515#define ADMA__GPT1_BASE (0x590C0000u)
49516/** Peripheral ADMA__GPT1 base pointer */
49517#define ADMA__GPT1 ((GPT_Type *)ADMA__GPT1_BASE)
49518/** Peripheral ADMA__GPT2 base address */
49519#define ADMA__GPT2_BASE (0x590D0000u)
49520/** Peripheral ADMA__GPT2 base pointer */
49521#define ADMA__GPT2 ((GPT_Type *)ADMA__GPT2_BASE)
49522/** Peripheral ADMA__GPT3 base address */
49523#define ADMA__GPT3_BASE (0x590E0000u)
49524/** Peripheral ADMA__GPT3 base pointer */
49525#define ADMA__GPT3 ((GPT_Type *)ADMA__GPT3_BASE)
49526/** Peripheral ADMA__GPT4 base address */
49527#define ADMA__GPT4_BASE (0x590F0000u)
49528/** Peripheral ADMA__GPT4 base pointer */
49529#define ADMA__GPT4 ((GPT_Type *)ADMA__GPT4_BASE)
49530/** Peripheral ADMA__GPT5 base address */
49531#define ADMA__GPT5_BASE (0x59100000u)
49532/** Peripheral ADMA__GPT5 base pointer */
49533#define ADMA__GPT5 ((GPT_Type *)ADMA__GPT5_BASE)
49534/** Peripheral LSIO__GPT0 base address */
49535#define LSIO__GPT0_BASE (0x5D140000u)
49536/** Peripheral LSIO__GPT0 base pointer */
49537#define LSIO__GPT0 ((GPT_Type *)LSIO__GPT0_BASE)
49538/** Peripheral LSIO__GPT1 base address */
49539#define LSIO__GPT1_BASE (0x5D150000u)
49540/** Peripheral LSIO__GPT1 base pointer */
49541#define LSIO__GPT1 ((GPT_Type *)LSIO__GPT1_BASE)
49542/** Peripheral LSIO__GPT2 base address */
49543#define LSIO__GPT2_BASE (0x5D160000u)
49544/** Peripheral LSIO__GPT2 base pointer */
49545#define LSIO__GPT2 ((GPT_Type *)LSIO__GPT2_BASE)
49546/** Peripheral LSIO__GPT3 base address */
49547#define LSIO__GPT3_BASE (0x5D170000u)
49548/** Peripheral LSIO__GPT3 base pointer */
49549#define LSIO__GPT3 ((GPT_Type *)LSIO__GPT3_BASE)
49550/** Peripheral LSIO__GPT4 base address */
49551#define LSIO__GPT4_BASE (0x5D180000u)
49552/** Peripheral LSIO__GPT4 base pointer */
49553#define LSIO__GPT4 ((GPT_Type *)LSIO__GPT4_BASE)
49554/** Array initializer of GPT peripheral base addresses */
49555#define GPT_BASE_ADDRS { ADMA__GPT0_BASE, ADMA__GPT1_BASE, ADMA__GPT2_BASE, ADMA__GPT3_BASE, ADMA__GPT4_BASE, ADMA__GPT5_BASE, LSIO__GPT0_BASE, LSIO__GPT1_BASE, LSIO__GPT2_BASE, LSIO__GPT3_BASE, LSIO__GPT4_BASE }
49556/** Array initializer of GPT peripheral base pointers */
49557#define GPT_BASE_PTRS { ADMA__GPT0, ADMA__GPT1, ADMA__GPT2, ADMA__GPT3, ADMA__GPT4, ADMA__GPT5, LSIO__GPT0, LSIO__GPT1, LSIO__GPT2, LSIO__GPT3, LSIO__GPT4 }
49558/** Interrupt vectors for the GPT peripheral type */
49559#define GPT_IRQS { ADMA_GPT0_INT_IRQn, ADMA_GPT1_INT_IRQn, ADMA_GPT2_INT_IRQn, ADMA_GPT3_INT_IRQn, ADMA_GPT4_INT_IRQn, ADMA_GPT5_INT_IRQn, LSIO_GPT0_INT_IRQn, LSIO_GPT1_INT_IRQn, LSIO_GPT2_INT_IRQn, LSIO_GPT3_INT_IRQn, LSIO_GPT4_INT_IRQn }
49560
49561/*!
49562 * @}
49563 */ /* end of group GPT_Peripheral_Access_Layer */
49564
49565
49566/* ----------------------------------------------------------------------------
49567 -- HSIO_CSR Peripheral Access Layer
49568 ---------------------------------------------------------------------------- */
49569
49570/*!
49571 * @addtogroup HSIO_CSR_Peripheral_Access_Layer HSIO_CSR Peripheral Access Layer
49572 * @{
49573 */
49574
49575/** HSIO_CSR - Register Layout Typedef */
49576typedef struct {
49577 __IO uint32_t PHYX1_CTRL0; /**< , offset: 0x0 */
49578 __I uint32_t PHYX1_STTS0; /**< , offset: 0x4 */
49579 uint8_t RESERVED_0[131064];
49580 __IO uint32_t PCIEX1_CTRL0; /**< , offset: 0x20000 */
49581 __IO uint32_t PCIEX1_CTRL1; /**< , offset: 0x20004 */
49582 __IO uint32_t PCIEX1_CTRL2; /**< , offset: 0x20008 */
49583 __I uint32_t PCIEX1_STTS0; /**< , offset: 0x2000C */
49584 __I uint32_t PCIEX1_STTS1; /**< , offset: 0x20010 */
49585 __I uint32_t PCIEX1_STTS2; /**< , offset: 0x20014 */
49586 uint8_t RESERVED_1[131048];
49587 __IO uint32_t MISC_CTRL0; /**< , offset: 0x40000 */
49588 uint32_t MISC_STTS0; /**< , offset: 0x40004 */
49589} HSIO_CSR_Type;
49590
49591/* ----------------------------------------------------------------------------
49592 -- HSIO_CSR Register Masks
49593 ---------------------------------------------------------------------------- */
49594
49595/*!
49596 * @addtogroup HSIO_CSR_Register_Masks HSIO_CSR Register Masks
49597 * @{
49598 */
49599
49600/*! @name PHYX1_CTRL0 - */
49601/*! @{ */
49602#define HSIO_CSR_PHYX1_CTRL0_APB_RSTN_MASK (0x1U)
49603#define HSIO_CSR_PHYX1_CTRL0_APB_RSTN_SHIFT (0U)
49604#define HSIO_CSR_PHYX1_CTRL0_APB_RSTN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_CTRL0_APB_RSTN_SHIFT)) & HSIO_CSR_PHYX1_CTRL0_APB_RSTN_MASK)
49605#define HSIO_CSR_PHYX1_CTRL0_AIDDQ_0_MASK (0x400U)
49606#define HSIO_CSR_PHYX1_CTRL0_AIDDQ_0_SHIFT (10U)
49607#define HSIO_CSR_PHYX1_CTRL0_AIDDQ_0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_CTRL0_AIDDQ_0_SHIFT)) & HSIO_CSR_PHYX1_CTRL0_AIDDQ_0_MASK)
49608#define HSIO_CSR_PHYX1_CTRL0_PHY_MODE_MASK (0x1E0000U)
49609#define HSIO_CSR_PHYX1_CTRL0_PHY_MODE_SHIFT (17U)
49610#define HSIO_CSR_PHYX1_CTRL0_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_CTRL0_PHY_MODE_SHIFT)) & HSIO_CSR_PHYX1_CTRL0_PHY_MODE_MASK)
49611#define HSIO_CSR_PHYX1_CTRL0_EI4_CHANGE_REQ_0_MASK (0x200000U)
49612#define HSIO_CSR_PHYX1_CTRL0_EI4_CHANGE_REQ_0_SHIFT (21U)
49613#define HSIO_CSR_PHYX1_CTRL0_EI4_CHANGE_REQ_0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_CTRL0_EI4_CHANGE_REQ_0_SHIFT)) & HSIO_CSR_PHYX1_CTRL0_EI4_CHANGE_REQ_0_MASK)
49614#define HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_0_MASK (0x1000000U)
49615#define HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_0_SHIFT (24U)
49616#define HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_0_SHIFT)) & HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_0_MASK)
49617#define HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_OVERRIDE_0_MASK (0x2000000U)
49618#define HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_OVERRIDE_0_SHIFT (25U)
49619#define HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_OVERRIDE_0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_OVERRIDE_0_SHIFT)) & HSIO_CSR_PHYX1_CTRL0_PIPE_RSTN_OVERRIDE_0_MASK)
49620/*! @} */
49621
49622/*! @name PHYX1_STTS0 - */
49623/*! @{ */
49624#define HSIO_CSR_PHYX1_STTS0_TEST_OUT_MASK (0xFFU)
49625#define HSIO_CSR_PHYX1_STTS0_TEST_OUT_SHIFT (0U)
49626/*! TEST_OUT - TEST_OUT[7:0]
49627 */
49628#define HSIO_CSR_PHYX1_STTS0_TEST_OUT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_STTS0_TEST_OUT_SHIFT)) & HSIO_CSR_PHYX1_STTS0_TEST_OUT_MASK)
49629#define HSIO_CSR_PHYX1_STTS0_EI4_CHANGE_ACK_MASK (0x10000U)
49630#define HSIO_CSR_PHYX1_STTS0_EI4_CHANGE_ACK_SHIFT (16U)
49631#define HSIO_CSR_PHYX1_STTS0_EI4_CHANGE_ACK(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_STTS0_EI4_CHANGE_ACK_SHIFT)) & HSIO_CSR_PHYX1_STTS0_EI4_CHANGE_ACK_MASK)
49632#define HSIO_CSR_PHYX1_STTS0_EPCS_READY_MASK (0x40000U)
49633#define HSIO_CSR_PHYX1_STTS0_EPCS_READY_SHIFT (18U)
49634#define HSIO_CSR_PHYX1_STTS0_EPCS_READY(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PHYX1_STTS0_EPCS_READY_SHIFT)) & HSIO_CSR_PHYX1_STTS0_EPCS_READY_MASK)
49635/*! @} */
49636
49637/*! @name PCIEX1_CTRL0 - */
49638/*! @{ */
49639#define HSIO_CSR_PCIEX1_CTRL0_PS_DEVICE_ID_MASK (0xFFFFU)
49640#define HSIO_CSR_PCIEX1_CTRL0_PS_DEVICE_ID_SHIFT (0U)
49641#define HSIO_CSR_PCIEX1_CTRL0_PS_DEVICE_ID(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL0_PS_DEVICE_ID_SHIFT)) & HSIO_CSR_PCIEX1_CTRL0_PS_DEVICE_ID_MASK)
49642#define HSIO_CSR_PCIEX1_CTRL0_PS_REVISION_ID_MASK (0xFF0000U)
49643#define HSIO_CSR_PCIEX1_CTRL0_PS_REVISION_ID_SHIFT (16U)
49644#define HSIO_CSR_PCIEX1_CTRL0_PS_REVISION_ID(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL0_PS_REVISION_ID_SHIFT)) & HSIO_CSR_PCIEX1_CTRL0_PS_REVISION_ID_MASK)
49645#define HSIO_CSR_PCIEX1_CTRL0_DEVICE_TYPE_MASK (0xF000000U)
49646#define HSIO_CSR_PCIEX1_CTRL0_DEVICE_TYPE_SHIFT (24U)
49647#define HSIO_CSR_PCIEX1_CTRL0_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL0_DEVICE_TYPE_SHIFT)) & HSIO_CSR_PCIEX1_CTRL0_DEVICE_TYPE_MASK)
49648/*! @} */
49649
49650/*! @name PCIEX1_CTRL1 - */
49651/*! @{ */
49652#define HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_WIDTH_MASK (0x3FU)
49653#define HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_WIDTH_SHIFT (0U)
49654#define HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_WIDTH_SHIFT)) & HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_WIDTH_MASK)
49655#define HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_SPEED_MASK (0x3C0U)
49656#define HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_SPEED_SHIFT (6U)
49657#define HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_SPEED_SHIFT)) & HSIO_CSR_PCIEX1_CTRL1_PS_CFG_PCIE_MAX_LINK_SPEED_MASK)
49658#define HSIO_CSR_PCIEX1_CTRL1_POR_SAMPLING_VALID_MASK (0x400U)
49659#define HSIO_CSR_PCIEX1_CTRL1_POR_SAMPLING_VALID_SHIFT (10U)
49660#define HSIO_CSR_PCIEX1_CTRL1_POR_SAMPLING_VALID(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL1_POR_SAMPLING_VALID_SHIFT)) & HSIO_CSR_PCIEX1_CTRL1_POR_SAMPLING_VALID_MASK)
49661#define HSIO_CSR_PCIEX1_CTRL1_PS_SAMPLING_VALID_MASK (0x800U)
49662#define HSIO_CSR_PCIEX1_CTRL1_PS_SAMPLING_VALID_SHIFT (11U)
49663#define HSIO_CSR_PCIEX1_CTRL1_PS_SAMPLING_VALID(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL1_PS_SAMPLING_VALID_SHIFT)) & HSIO_CSR_PCIEX1_CTRL1_PS_SAMPLING_VALID_MASK)
49664#define HSIO_CSR_PCIEX1_CTRL1_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN_MASK (0x4000U)
49665#define HSIO_CSR_PCIEX1_CTRL1_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN_SHIFT (14U)
49666#define HSIO_CSR_PCIEX1_CTRL1_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL1_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN_SHIFT)) & HSIO_CSR_PCIEX1_CTRL1_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN_MASK)
49667/*! @} */
49668
49669/*! @name PCIEX1_CTRL2 - */
49670/*! @{ */
49671#define HSIO_CSR_PCIEX1_CTRL2_SYS_INT_MASK (0x3U)
49672#define HSIO_CSR_PCIEX1_CTRL2_SYS_INT_SHIFT (0U)
49673#define HSIO_CSR_PCIEX1_CTRL2_SYS_INT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_SYS_INT_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_SYS_INT_MASK)
49674#define HSIO_CSR_PCIEX1_CTRL2_APP_CLK_REQ_N_MASK (0x4U)
49675#define HSIO_CSR_PCIEX1_CTRL2_APP_CLK_REQ_N_SHIFT (2U)
49676#define HSIO_CSR_PCIEX1_CTRL2_APP_CLK_REQ_N(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_CLK_REQ_N_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_CLK_REQ_N_MASK)
49677#define HSIO_CSR_PCIEX1_CTRL2_APP_INIT_RST_MASK (0x8U)
49678#define HSIO_CSR_PCIEX1_CTRL2_APP_INIT_RST_SHIFT (3U)
49679#define HSIO_CSR_PCIEX1_CTRL2_APP_INIT_RST(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_INIT_RST_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_INIT_RST_MASK)
49680#define HSIO_CSR_PCIEX1_CTRL2_APP_LTSSM_ENABLE_MASK (0x10U)
49681#define HSIO_CSR_PCIEX1_CTRL2_APP_LTSSM_ENABLE_SHIFT (4U)
49682#define HSIO_CSR_PCIEX1_CTRL2_APP_LTSSM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_LTSSM_ENABLE_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_LTSSM_ENABLE_MASK)
49683#define HSIO_CSR_PCIEX1_CTRL2_APP_READY_ENTR_L23_MASK (0x20U)
49684#define HSIO_CSR_PCIEX1_CTRL2_APP_READY_ENTR_L23_SHIFT (5U)
49685#define HSIO_CSR_PCIEX1_CTRL2_APP_READY_ENTR_L23(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_READY_ENTR_L23_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_READY_ENTR_L23_MASK)
49686#define HSIO_CSR_PCIEX1_CTRL2_APP_REQ_ENTR_L1_MASK (0x40U)
49687#define HSIO_CSR_PCIEX1_CTRL2_APP_REQ_ENTR_L1_SHIFT (6U)
49688#define HSIO_CSR_PCIEX1_CTRL2_APP_REQ_ENTR_L1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_REQ_ENTR_L1_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_REQ_ENTR_L1_MASK)
49689#define HSIO_CSR_PCIEX1_CTRL2_APP_REQ_EXIT_L1_MASK (0x80U)
49690#define HSIO_CSR_PCIEX1_CTRL2_APP_REQ_EXIT_L1_SHIFT (7U)
49691#define HSIO_CSR_PCIEX1_CTRL2_APP_REQ_EXIT_L1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_REQ_EXIT_L1_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_REQ_EXIT_L1_MASK)
49692#define HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_PME_MASK (0x100U)
49693#define HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_PME_SHIFT (8U)
49694#define HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_PME(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_PME_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_PME_MASK)
49695#define HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_TURNOFF_MASK (0x200U)
49696#define HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_TURNOFF_SHIFT (9U)
49697#define HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_TURNOFF(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_TURNOFF_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APPS_PM_XMT_TURNOFF_MASK)
49698#define HSIO_CSR_PCIEX1_CTRL2_APP_CLK_PM_EN_MASK (0x400U)
49699#define HSIO_CSR_PCIEX1_CTRL2_APP_CLK_PM_EN_SHIFT (10U)
49700#define HSIO_CSR_PCIEX1_CTRL2_APP_CLK_PM_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_CLK_PM_EN_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_CLK_PM_EN_MASK)
49701#define HSIO_CSR_PCIEX1_CTRL2_APP_XFER_PENDING_MASK (0x800U)
49702#define HSIO_CSR_PCIEX1_CTRL2_APP_XFER_PENDING_SHIFT (11U)
49703#define HSIO_CSR_PCIEX1_CTRL2_APP_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_APP_XFER_PENDING_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_APP_XFER_PENDING_MASK)
49704#define HSIO_CSR_PCIEX1_CTRL2_DIAG_STATUS_BUS_SELECT_MASK (0x1E000U)
49705#define HSIO_CSR_PCIEX1_CTRL2_DIAG_STATUS_BUS_SELECT_SHIFT (13U)
49706#define HSIO_CSR_PCIEX1_CTRL2_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_DIAG_STATUS_BUS_SELECT_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_DIAG_STATUS_BUS_SELECT_MASK)
49707#define HSIO_CSR_PCIEX1_CTRL2_DIAG_CTRL_BUS_MASK (0xE0000U)
49708#define HSIO_CSR_PCIEX1_CTRL2_DIAG_CTRL_BUS_SHIFT (17U)
49709#define HSIO_CSR_PCIEX1_CTRL2_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_DIAG_CTRL_BUS_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_DIAG_CTRL_BUS_MASK)
49710#define HSIO_CSR_PCIEX1_CTRL2_BUTTON_RST_N_MASK (0x200000U)
49711#define HSIO_CSR_PCIEX1_CTRL2_BUTTON_RST_N_SHIFT (21U)
49712#define HSIO_CSR_PCIEX1_CTRL2_BUTTON_RST_N(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_BUTTON_RST_N_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_BUTTON_RST_N_MASK)
49713#define HSIO_CSR_PCIEX1_CTRL2_PERST_N_MASK (0x400000U)
49714#define HSIO_CSR_PCIEX1_CTRL2_PERST_N_SHIFT (22U)
49715#define HSIO_CSR_PCIEX1_CTRL2_PERST_N(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_PERST_N_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_PERST_N_MASK)
49716#define HSIO_CSR_PCIEX1_CTRL2_POWER_UP_RST_N__MASK (0x800000U)
49717#define HSIO_CSR_PCIEX1_CTRL2_POWER_UP_RST_N__SHIFT (23U)
49718#define HSIO_CSR_PCIEX1_CTRL2_POWER_UP_RST_N_(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_POWER_UP_RST_N__SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_POWER_UP_RST_N__MASK)
49719#define HSIO_CSR_PCIEX1_CTRL2_GPR_CRS_CLEAR_MASK (0x4000000U)
49720#define HSIO_CSR_PCIEX1_CTRL2_GPR_CRS_CLEAR_SHIFT (26U)
49721#define HSIO_CSR_PCIEX1_CTRL2_GPR_CRS_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_CTRL2_GPR_CRS_CLEAR_SHIFT)) & HSIO_CSR_PCIEX1_CTRL2_GPR_CRS_CLEAR_MASK)
49722/*! @} */
49723
49724/*! @name PCIEX1_STTS0 - */
49725/*! @{ */
49726#define HSIO_CSR_PCIEX1_STTS0_SMLH_LTSSM_STATE_MASK (0x3FU)
49727#define HSIO_CSR_PCIEX1_STTS0_SMLH_LTSSM_STATE_SHIFT (0U)
49728#define HSIO_CSR_PCIEX1_STTS0_SMLH_LTSSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_SMLH_LTSSM_STATE_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_SMLH_LTSSM_STATE_MASK)
49729#define HSIO_CSR_PCIEX1_STTS0_CFG_L1SUB_EN_MASK (0x40U)
49730#define HSIO_CSR_PCIEX1_STTS0_CFG_L1SUB_EN_SHIFT (6U)
49731#define HSIO_CSR_PCIEX1_STTS0_CFG_L1SUB_EN(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_CFG_L1SUB_EN_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_CFG_L1SUB_EN_MASK)
49732#define HSIO_CSR_PCIEX1_STTS0_PM_DSTATE_MASK (0x380U)
49733#define HSIO_CSR_PCIEX1_STTS0_PM_DSTATE_SHIFT (7U)
49734#define HSIO_CSR_PCIEX1_STTS0_PM_DSTATE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_DSTATE_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_DSTATE_MASK)
49735#define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L0S_MASK (0x400U)
49736#define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L0S_SHIFT (10U)
49737#define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L0S(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L0S_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L0S_MASK)
49738#define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1SUB_MASK (0x800U)
49739#define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1SUB_SHIFT (11U)
49740#define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1SUB(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1SUB_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1SUB_MASK)
49741#define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1_MASK (0x1000U)
49742#define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1_SHIFT (12U)
49743#define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L1_MASK)
49744#define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L2_MASK (0x2000U)
49745#define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L2_SHIFT (13U)
49746#define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L2(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L2_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_LINKST_IN_L2_MASK)
49747#define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_L2_EXIT_MASK (0x4000U)
49748#define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_L2_EXIT_SHIFT (14U)
49749#define HSIO_CSR_PCIEX1_STTS0_PM_LINKST_L2_EXIT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_LINKST_L2_EXIT_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_LINKST_L2_EXIT_MASK)
49750#define HSIO_CSR_PCIEX1_STTS0_BRDG_SLV_XFER_PENDING_MASK (0x8000U)
49751#define HSIO_CSR_PCIEX1_STTS0_BRDG_SLV_XFER_PENDING_SHIFT (15U)
49752#define HSIO_CSR_PCIEX1_STTS0_BRDG_SLV_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_BRDG_SLV_XFER_PENDING_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_BRDG_SLV_XFER_PENDING_MASK)
49753#define HSIO_CSR_PCIEX1_STTS0_EDMA_XFER_PENDING_MASK (0x10000U)
49754#define HSIO_CSR_PCIEX1_STTS0_EDMA_XFER_PENDING_SHIFT (16U)
49755#define HSIO_CSR_PCIEX1_STTS0_EDMA_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_EDMA_XFER_PENDING_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_EDMA_XFER_PENDING_MASK)
49756#define HSIO_CSR_PCIEX1_STTS0_RADM_XFER_PENDING_MASK (0x20000U)
49757#define HSIO_CSR_PCIEX1_STTS0_RADM_XFER_PENDING_SHIFT (17U)
49758#define HSIO_CSR_PCIEX1_STTS0_RADM_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_RADM_XFER_PENDING_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_RADM_XFER_PENDING_MASK)
49759#define HSIO_CSR_PCIEX1_STTS0_DBI_XFER_PENDING_MASK (0x40000U)
49760#define HSIO_CSR_PCIEX1_STTS0_DBI_XFER_PENDING_SHIFT (18U)
49761#define HSIO_CSR_PCIEX1_STTS0_DBI_XFER_PENDING(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_DBI_XFER_PENDING_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_DBI_XFER_PENDING_MASK)
49762#define HSIO_CSR_PCIEX1_STTS0_PM_REQ_CORE_RST_MASK (0x80000U)
49763#define HSIO_CSR_PCIEX1_STTS0_PM_REQ_CORE_RST_SHIFT (19U)
49764#define HSIO_CSR_PCIEX1_STTS0_PM_REQ_CORE_RST(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_PM_REQ_CORE_RST_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_PM_REQ_CORE_RST_MASK)
49765#define HSIO_CSR_PCIEX1_STTS0_CPL_CRS_RCVD_MASK (0x400000U)
49766#define HSIO_CSR_PCIEX1_STTS0_CPL_CRS_RCVD_SHIFT (22U)
49767#define HSIO_CSR_PCIEX1_STTS0_CPL_CRS_RCVD(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS0_CPL_CRS_RCVD_SHIFT)) & HSIO_CSR_PCIEX1_STTS0_CPL_CRS_RCVD_MASK)
49768/*! @} */
49769
49770/*! @name PCIEX1_STTS1 - */
49771/*! @{ */
49772#define HSIO_CSR_PCIEX1_STTS1_CXPL_DEBUG_INFO_EI_MASK (0xFFFFU)
49773#define HSIO_CSR_PCIEX1_STTS1_CXPL_DEBUG_INFO_EI_SHIFT (0U)
49774#define HSIO_CSR_PCIEX1_STTS1_CXPL_DEBUG_INFO_EI(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS1_CXPL_DEBUG_INFO_EI_SHIFT)) & HSIO_CSR_PCIEX1_STTS1_CXPL_DEBUG_INFO_EI_MASK)
49775/*! @} */
49776
49777/*! @name PCIEX1_STTS2 - */
49778/*! @{ */
49779#define HSIO_CSR_PCIEX1_STTS2_DIAG_STATUS_BUS_MUX_MASK (0xFFFFFFFFU)
49780#define HSIO_CSR_PCIEX1_STTS2_DIAG_STATUS_BUS_MUX_SHIFT (0U)
49781#define HSIO_CSR_PCIEX1_STTS2_DIAG_STATUS_BUS_MUX(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_PCIEX1_STTS2_DIAG_STATUS_BUS_MUX_SHIFT)) & HSIO_CSR_PCIEX1_STTS2_DIAG_STATUS_BUS_MUX_MASK)
49782/*! @} */
49783
49784/*! @name MISC_CTRL0 - */
49785/*! @{ */
49786#define HSIO_CSR_MISC_CTRL0_IOB_RXENA_MASK (0x1U)
49787#define HSIO_CSR_MISC_CTRL0_IOB_RXENA_SHIFT (0U)
49788#define HSIO_CSR_MISC_CTRL0_IOB_RXENA(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_IOB_RXENA_SHIFT)) & HSIO_CSR_MISC_CTRL0_IOB_RXENA_MASK)
49789#define HSIO_CSR_MISC_CTRL0_IOB_TXENA_MASK (0x2U)
49790#define HSIO_CSR_MISC_CTRL0_IOB_TXENA_SHIFT (1U)
49791#define HSIO_CSR_MISC_CTRL0_IOB_TXENA(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_IOB_TXENA_SHIFT)) & HSIO_CSR_MISC_CTRL0_IOB_TXENA_MASK)
49792#define HSIO_CSR_MISC_CTRL0_IOB_A_0_TXOE_MASK (0x4U)
49793#define HSIO_CSR_MISC_CTRL0_IOB_A_0_TXOE_SHIFT (2U)
49794#define HSIO_CSR_MISC_CTRL0_IOB_A_0_TXOE(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_IOB_A_0_TXOE_SHIFT)) & HSIO_CSR_MISC_CTRL0_IOB_A_0_TXOE_MASK)
49795#define HSIO_CSR_MISC_CTRL0_IOB_A_0_M1M0_MASK (0x18U)
49796#define HSIO_CSR_MISC_CTRL0_IOB_A_0_M1M0_SHIFT (3U)
49797#define HSIO_CSR_MISC_CTRL0_IOB_A_0_M1M0(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_IOB_A_0_M1M0_SHIFT)) & HSIO_CSR_MISC_CTRL0_IOB_A_0_M1M0_MASK)
49798#define HSIO_CSR_MISC_CTRL0_FAST_INIT_MASK (0x800U)
49799#define HSIO_CSR_MISC_CTRL0_FAST_INIT_SHIFT (11U)
49800#define HSIO_CSR_MISC_CTRL0_FAST_INIT(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_FAST_INIT_SHIFT)) & HSIO_CSR_MISC_CTRL0_FAST_INIT_MASK)
49801#define HSIO_CSR_MISC_CTRL0_PHY_X1_EPCS_SEL_MASK (0x1000U)
49802#define HSIO_CSR_MISC_CTRL0_PHY_X1_EPCS_SEL_SHIFT (12U)
49803/*! PHY_X1_EPCS_SEL - PHY_X1_EPCS_SEL will be used for ECO for PCIe controller bug fix.
49804 */
49805#define HSIO_CSR_MISC_CTRL0_PHY_X1_EPCS_SEL(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_PHY_X1_EPCS_SEL_SHIFT)) & HSIO_CSR_MISC_CTRL0_PHY_X1_EPCS_SEL_MASK)
49806#define HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_1_MASK (0x400000U)
49807#define HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_1_SHIFT (22U)
49808#define HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_1_SHIFT)) & HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_1_MASK)
49809#define HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_OVERRIDE_1_MASK (0x1000000U)
49810#define HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_OVERRIDE_1_SHIFT (24U)
49811#define HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_OVERRIDE_1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_OVERRIDE_1_SHIFT)) & HSIO_CSR_MISC_CTRL0_CLKREQN_OUT_OVERRIDE_1_MASK)
49812#define HSIO_CSR_MISC_CTRL0_CLKREQN_IN_1_MASK (0x4000000U)
49813#define HSIO_CSR_MISC_CTRL0_CLKREQN_IN_1_SHIFT (26U)
49814#define HSIO_CSR_MISC_CTRL0_CLKREQN_IN_1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_CLKREQN_IN_1_SHIFT)) & HSIO_CSR_MISC_CTRL0_CLKREQN_IN_1_MASK)
49815#define HSIO_CSR_MISC_CTRL0_CLKREQN_IN_OVERRIDE_1_MASK (0x10000000U)
49816#define HSIO_CSR_MISC_CTRL0_CLKREQN_IN_OVERRIDE_1_SHIFT (28U)
49817#define HSIO_CSR_MISC_CTRL0_CLKREQN_IN_OVERRIDE_1(x) (((uint32_t)(((uint32_t)(x)) << HSIO_CSR_MISC_CTRL0_CLKREQN_IN_OVERRIDE_1_SHIFT)) & HSIO_CSR_MISC_CTRL0_CLKREQN_IN_OVERRIDE_1_MASK)
49818/*! @} */
49819
49820
49821/*!
49822 * @}
49823 */ /* end of group HSIO_CSR_Register_Masks */
49824
49825
49826/* HSIO_CSR - Peripheral instance base addresses */
49827/** Peripheral HSIO_CSR base address */
49828#define HSIO_CSR_BASE (0x5F120000u)
49829/** Peripheral HSIO_CSR base pointer */
49830#define HSIO_CSR ((HSIO_CSR_Type *)HSIO_CSR_BASE)
49831/** Array initializer of HSIO_CSR peripheral base addresses */
49832#define HSIO_CSR_BASE_ADDRS { HSIO_CSR_BASE }
49833/** Array initializer of HSIO_CSR peripheral base pointers */
49834#define HSIO_CSR_BASE_PTRS { HSIO_CSR }
49835
49836/*!
49837 * @}
49838 */ /* end of group HSIO_CSR_Peripheral_Access_Layer */
49839
49840
49841/* ----------------------------------------------------------------------------
49842 -- I2S Peripheral Access Layer
49843 ---------------------------------------------------------------------------- */
49844
49845/*!
49846 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
49847 * @{
49848 */
49849
49850/** I2S - Register Layout Typedef */
49851typedef struct {
49852 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
49853 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
49854 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
49855 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
49856 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
49857 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
49858 uint8_t RESERVED_0[8];
49859 __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
49860 uint8_t RESERVED_1[28];
49861 __I uint32_t TFR[1]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
49862 uint8_t RESERVED_2[28];
49863 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
49864 uint8_t RESERVED_3[28];
49865 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
49866 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
49867 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
49868 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
49869 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
49870 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
49871 uint8_t RESERVED_4[8];
49872 __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
49873 uint8_t RESERVED_5[28];
49874 __I uint32_t RFR[1]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
49875 uint8_t RESERVED_6[28];
49876 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
49877} I2S_Type;
49878
49879/* ----------------------------------------------------------------------------
49880 -- I2S Register Masks
49881 ---------------------------------------------------------------------------- */
49882
49883/*!
49884 * @addtogroup I2S_Register_Masks I2S Register Masks
49885 * @{
49886 */
49887
49888/*! @name TCSR - SAI Transmit Control Register */
49889/*! @{ */
49890#define I2S_TCSR_FRDE_MASK (0x1U)
49891#define I2S_TCSR_FRDE_SHIFT (0U)
49892/*! FRDE - FIFO Request DMA Enable
49893 * 0b0..Disables the DMA request.
49894 * 0b1..Enables the DMA request.
49895 */
49896#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
49897#define I2S_TCSR_FWDE_MASK (0x2U)
49898#define I2S_TCSR_FWDE_SHIFT (1U)
49899/*! FWDE - FIFO Warning DMA Enable
49900 * 0b0..Disables the DMA request.
49901 * 0b1..Enables the DMA request.
49902 */
49903#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
49904#define I2S_TCSR_FRIE_MASK (0x100U)
49905#define I2S_TCSR_FRIE_SHIFT (8U)
49906/*! FRIE - FIFO Request Interrupt Enable
49907 * 0b0..Disables the interrupt.
49908 * 0b1..Enables the interrupt.
49909 */
49910#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
49911#define I2S_TCSR_FWIE_MASK (0x200U)
49912#define I2S_TCSR_FWIE_SHIFT (9U)
49913/*! FWIE - FIFO Warning Interrupt Enable
49914 * 0b0..Disables the interrupt.
49915 * 0b1..Enables the interrupt.
49916 */
49917#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
49918#define I2S_TCSR_FEIE_MASK (0x400U)
49919#define I2S_TCSR_FEIE_SHIFT (10U)
49920/*! FEIE - FIFO Error Interrupt Enable
49921 * 0b0..Disables the interrupt.
49922 * 0b1..Enables the interrupt.
49923 */
49924#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
49925#define I2S_TCSR_SEIE_MASK (0x800U)
49926#define I2S_TCSR_SEIE_SHIFT (11U)
49927/*! SEIE - Sync Error Interrupt Enable
49928 * 0b0..Disables interrupt.
49929 * 0b1..Enables interrupt.
49930 */
49931#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
49932#define I2S_TCSR_WSIE_MASK (0x1000U)
49933#define I2S_TCSR_WSIE_SHIFT (12U)
49934/*! WSIE - Word Start Interrupt Enable
49935 * 0b0..Disables interrupt.
49936 * 0b1..Enables interrupt.
49937 */
49938#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
49939#define I2S_TCSR_FRF_MASK (0x10000U)
49940#define I2S_TCSR_FRF_SHIFT (16U)
49941/*! FRF - FIFO Request Flag
49942 * 0b0..Transmit FIFO watermark has not been reached.
49943 * 0b1..Transmit FIFO watermark has been reached.
49944 */
49945#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
49946#define I2S_TCSR_FWF_MASK (0x20000U)
49947#define I2S_TCSR_FWF_SHIFT (17U)
49948/*! FWF - FIFO Warning Flag
49949 * 0b0..No enabled transmit FIFO is empty.
49950 * 0b1..Enabled transmit FIFO is empty.
49951 */
49952#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
49953#define I2S_TCSR_FEF_MASK (0x40000U)
49954#define I2S_TCSR_FEF_SHIFT (18U)
49955/*! FEF - FIFO Error Flag
49956 * 0b0..Transmit underrun not detected.
49957 * 0b1..Transmit underrun detected.
49958 */
49959#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
49960#define I2S_TCSR_SEF_MASK (0x80000U)
49961#define I2S_TCSR_SEF_SHIFT (19U)
49962/*! SEF - Sync Error Flag
49963 * 0b0..Sync error not detected.
49964 * 0b1..Frame sync error detected.
49965 */
49966#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
49967#define I2S_TCSR_WSF_MASK (0x100000U)
49968#define I2S_TCSR_WSF_SHIFT (20U)
49969/*! WSF - Word Start Flag
49970 * 0b0..Start of word not detected.
49971 * 0b1..Start of word detected.
49972 */
49973#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
49974#define I2S_TCSR_SR_MASK (0x1000000U)
49975#define I2S_TCSR_SR_SHIFT (24U)
49976/*! SR - Software Reset
49977 * 0b0..No effect.
49978 * 0b1..Software reset.
49979 */
49980#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
49981#define I2S_TCSR_FR_MASK (0x2000000U)
49982#define I2S_TCSR_FR_SHIFT (25U)
49983/*! FR - FIFO Reset
49984 * 0b0..No effect.
49985 * 0b1..FIFO reset.
49986 */
49987#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
49988#define I2S_TCSR_BCE_MASK (0x10000000U)
49989#define I2S_TCSR_BCE_SHIFT (28U)
49990/*! BCE - Bit Clock Enable
49991 * 0b0..Transmit bit clock is disabled.
49992 * 0b1..Transmit bit clock is enabled.
49993 */
49994#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
49995#define I2S_TCSR_DBGE_MASK (0x20000000U)
49996#define I2S_TCSR_DBGE_SHIFT (29U)
49997/*! DBGE - Debug Enable
49998 * 0b0..Transmitter is disabled in Debug mode, after completing the current frame.
49999 * 0b1..Transmitter is enabled in Debug mode.
50000 */
50001#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
50002#define I2S_TCSR_STOPE_MASK (0x40000000U)
50003#define I2S_TCSR_STOPE_SHIFT (30U)
50004/*! STOPE - Stop Enable
50005 * 0b0..Transmitter disabled in Stop mode.
50006 * 0b1..Transmitter enabled in Stop mode.
50007 */
50008#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
50009#define I2S_TCSR_TE_MASK (0x80000000U)
50010#define I2S_TCSR_TE_SHIFT (31U)
50011/*! TE - Transmitter Enable
50012 * 0b0..Transmitter is disabled.
50013 * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
50014 */
50015#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
50016/*! @} */
50017
50018/*! @name TCR1 - SAI Transmit Configuration 1 Register */
50019/*! @{ */
50020#define I2S_TCR1_TFW_MASK (0x3FU)
50021#define I2S_TCR1_TFW_SHIFT (0U)
50022/*! TFW - Transmit FIFO Watermark
50023 */
50024#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
50025/*! @} */
50026
50027/*! @name TCR2 - SAI Transmit Configuration 2 Register */
50028/*! @{ */
50029#define I2S_TCR2_DIV_MASK (0xFFU)
50030#define I2S_TCR2_DIV_SHIFT (0U)
50031/*! DIV - Bit Clock Divide
50032 */
50033#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
50034#define I2S_TCR2_BCD_MASK (0x1000000U)
50035#define I2S_TCR2_BCD_SHIFT (24U)
50036/*! BCD - Bit Clock Direction
50037 * 0b0..Bit clock is generated externally in Slave mode.
50038 * 0b1..Bit clock is generated internally in Master mode.
50039 */
50040#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
50041#define I2S_TCR2_BCP_MASK (0x2000000U)
50042#define I2S_TCR2_BCP_SHIFT (25U)
50043/*! BCP - Bit Clock Polarity
50044 * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
50045 * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
50046 */
50047#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
50048#define I2S_TCR2_MSEL_MASK (0xC000000U)
50049#define I2S_TCR2_MSEL_SHIFT (26U)
50050/*! MSEL - MCLK Select
50051 * 0b00..Bus Clock selected.
50052 * 0b01..Master Clock (MCLK) 1 option selected.
50053 * 0b10..Master Clock (MCLK) 2 option selected.
50054 * 0b11..Master Clock (MCLK) 3 option selected.
50055 */
50056#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
50057#define I2S_TCR2_BCI_MASK (0x10000000U)
50058#define I2S_TCR2_BCI_SHIFT (28U)
50059/*! BCI - Bit Clock Input
50060 * 0b0..No effect.
50061 * 0b1..Internal logic is clocked as if bit clock was externally generated.
50062 */
50063#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
50064#define I2S_TCR2_BCS_MASK (0x20000000U)
50065#define I2S_TCR2_BCS_SHIFT (29U)
50066/*! BCS - Bit Clock Swap
50067 * 0b0..Use the normal bit clock source.
50068 * 0b1..Swap the bit clock source.
50069 */
50070#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
50071#define I2S_TCR2_SYNC_MASK (0xC0000000U)
50072#define I2S_TCR2_SYNC_SHIFT (30U)
50073/*! SYNC - Synchronous Mode
50074 * 0b00..Asynchronous mode.
50075 * 0b01..Synchronous with receiver.
50076 * 0b10..Synchronous with another SAI transmitter.
50077 * 0b11..Synchronous with another SAI receiver.
50078 */
50079#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
50080/*! @} */
50081
50082/*! @name TCR3 - SAI Transmit Configuration 3 Register */
50083/*! @{ */
50084#define I2S_TCR3_WDFL_MASK (0x1FU) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
50085#define I2S_TCR3_WDFL_SHIFT (0U)
50086/*! WDFL - Word Flag Configuration
50087 */
50088#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
50089#define I2S_TCR3_TCE_MASK (0x10000U)
50090#define I2S_TCR3_TCE_SHIFT (16U)
50091/*! TCE - Transmit Channel Enable
50092 */
50093#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
50094/*! @} */
50095
50096/*! @name TCR4 - SAI Transmit Configuration 4 Register */
50097/*! @{ */
50098#define I2S_TCR4_FSD_MASK (0x1U)
50099#define I2S_TCR4_FSD_SHIFT (0U)
50100/*! FSD - Frame Sync Direction
50101 * 0b0..Frame sync is generated externally in Slave mode.
50102 * 0b1..Frame sync is generated internally in Master mode.
50103 */
50104#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
50105#define I2S_TCR4_FSP_MASK (0x2U)
50106#define I2S_TCR4_FSP_SHIFT (1U)
50107/*! FSP - Frame Sync Polarity
50108 * 0b0..Frame sync is active high.
50109 * 0b1..Frame sync is active low.
50110 */
50111#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
50112#define I2S_TCR4_ONDEM_MASK (0x4U)
50113#define I2S_TCR4_ONDEM_SHIFT (2U)
50114/*! ONDEM - On Demand Mode
50115 * 0b0..Internal frame sync is generated continuously.
50116 * 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
50117 */
50118#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
50119#define I2S_TCR4_FSE_MASK (0x8U)
50120#define I2S_TCR4_FSE_SHIFT (3U)
50121/*! FSE - Frame Sync Early
50122 * 0b0..Frame sync asserts with the first bit of the frame.
50123 * 0b1..Frame sync asserts one bit before the first bit of the frame.
50124 */
50125#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
50126#define I2S_TCR4_MF_MASK (0x10U)
50127#define I2S_TCR4_MF_SHIFT (4U)
50128/*! MF - MSB First
50129 * 0b0..LSB is transmitted first.
50130 * 0b1..MSB is transmitted first.
50131 */
50132#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
50133#define I2S_TCR4_SYWD_MASK (0x1F00U)
50134#define I2S_TCR4_SYWD_SHIFT (8U)
50135/*! SYWD - Sync Width
50136 */
50137#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
50138#define I2S_TCR4_FRSZ_MASK (0x1F0000U) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
50139#define I2S_TCR4_FRSZ_SHIFT (16U)
50140/*! FRSZ - Frame size
50141 */
50142#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
50143#define I2S_TCR4_FPACK_MASK (0x3000000U)
50144#define I2S_TCR4_FPACK_SHIFT (24U)
50145/*! FPACK - FIFO Packing Mode
50146 * 0b00..FIFO packing is disabled
50147 * 0b01..Reserved
50148 * 0b10..8-bit FIFO packing is enabled
50149 * 0b11..16-bit FIFO packing is enabled
50150 */
50151#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
50152#define I2S_TCR4_FCONT_MASK (0x10000000U)
50153#define I2S_TCR4_FCONT_SHIFT (28U)
50154/*! FCONT - FIFO Continue on Error
50155 * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
50156 * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
50157 */
50158#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
50159/*! @} */
50160
50161/*! @name TCR5 - SAI Transmit Configuration 5 Register */
50162/*! @{ */
50163#define I2S_TCR5_FBT_MASK (0x1F00U)
50164#define I2S_TCR5_FBT_SHIFT (8U)
50165/*! FBT - First Bit Shifted
50166 */
50167#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
50168#define I2S_TCR5_W0W_MASK (0x1F0000U)
50169#define I2S_TCR5_W0W_SHIFT (16U)
50170/*! W0W - Word 0 Width
50171 */
50172#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
50173#define I2S_TCR5_WNW_MASK (0x1F000000U)
50174#define I2S_TCR5_WNW_SHIFT (24U)
50175/*! WNW - Word N Width
50176 */
50177#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
50178/*! @} */
50179
50180/*! @name TDR - SAI Transmit Data Register */
50181/*! @{ */
50182#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
50183#define I2S_TDR_TDR_SHIFT (0U)
50184/*! TDR - Transmit Data Register
50185 */
50186#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
50187/*! @} */
50188
50189/* The count of I2S_TDR */
50190#define I2S_TDR_COUNT (1U)
50191
50192/*! @name TFR - SAI Transmit FIFO Register */
50193/*! @{ */
50194#define I2S_TFR_RFP_MASK (0x7FU)
50195#define I2S_TFR_RFP_SHIFT (0U)
50196/*! RFP - Read FIFO Pointer
50197 */
50198#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
50199#define I2S_TFR_WFP_MASK (0x7F0000U)
50200#define I2S_TFR_WFP_SHIFT (16U)
50201/*! WFP - Write FIFO Pointer
50202 */
50203#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
50204/*! @} */
50205
50206/* The count of I2S_TFR */
50207#define I2S_TFR_COUNT (1U)
50208
50209/*! @name TMR - SAI Transmit Mask Register */
50210/*! @{ */
50211#define I2S_TMR_TWM_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (8, 32), largest definition used */
50212#define I2S_TMR_TWM_SHIFT (0U)
50213/*! TWM - Transmit Word Mask
50214 * 0b00000000000000000000000000000000..Word N is enabled.
50215 * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated when masked.
50216 */
50217#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK) /* Merged from fields with different position or width, of widths (8, 32), largest definition used */
50218/*! @} */
50219
50220/*! @name RCSR - SAI Receive Control Register */
50221/*! @{ */
50222#define I2S_RCSR_FRDE_MASK (0x1U)
50223#define I2S_RCSR_FRDE_SHIFT (0U)
50224/*! FRDE - FIFO Request DMA Enable
50225 * 0b0..Disables the DMA request.
50226 * 0b1..Enables the DMA request.
50227 */
50228#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
50229#define I2S_RCSR_FWDE_MASK (0x2U)
50230#define I2S_RCSR_FWDE_SHIFT (1U)
50231/*! FWDE - FIFO Warning DMA Enable
50232 * 0b0..Disables the DMA request.
50233 * 0b1..Enables the DMA request.
50234 */
50235#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
50236#define I2S_RCSR_FRIE_MASK (0x100U)
50237#define I2S_RCSR_FRIE_SHIFT (8U)
50238/*! FRIE - FIFO Request Interrupt Enable
50239 * 0b0..Disables the interrupt.
50240 * 0b1..Enables the interrupt.
50241 */
50242#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
50243#define I2S_RCSR_FWIE_MASK (0x200U)
50244#define I2S_RCSR_FWIE_SHIFT (9U)
50245/*! FWIE - FIFO Warning Interrupt Enable
50246 * 0b0..Disables the interrupt.
50247 * 0b1..Enables the interrupt.
50248 */
50249#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
50250#define I2S_RCSR_FEIE_MASK (0x400U)
50251#define I2S_RCSR_FEIE_SHIFT (10U)
50252/*! FEIE - FIFO Error Interrupt Enable
50253 * 0b0..Disables the interrupt.
50254 * 0b1..Enables the interrupt.
50255 */
50256#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
50257#define I2S_RCSR_SEIE_MASK (0x800U)
50258#define I2S_RCSR_SEIE_SHIFT (11U)
50259/*! SEIE - Sync Error Interrupt Enable
50260 * 0b0..Disables interrupt.
50261 * 0b1..Enables interrupt.
50262 */
50263#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
50264#define I2S_RCSR_WSIE_MASK (0x1000U)
50265#define I2S_RCSR_WSIE_SHIFT (12U)
50266/*! WSIE - Word Start Interrupt Enable
50267 * 0b0..Disables interrupt.
50268 * 0b1..Enables interrupt.
50269 */
50270#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
50271#define I2S_RCSR_FRF_MASK (0x10000U)
50272#define I2S_RCSR_FRF_SHIFT (16U)
50273/*! FRF - FIFO Request Flag
50274 * 0b0..Receive FIFO watermark not reached.
50275 * 0b1..Receive FIFO watermark has been reached.
50276 */
50277#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
50278#define I2S_RCSR_FWF_MASK (0x20000U)
50279#define I2S_RCSR_FWF_SHIFT (17U)
50280/*! FWF - FIFO Warning Flag
50281 * 0b0..No enabled receive FIFO is full.
50282 * 0b1..Enabled receive FIFO is full.
50283 */
50284#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
50285#define I2S_RCSR_FEF_MASK (0x40000U)
50286#define I2S_RCSR_FEF_SHIFT (18U)
50287/*! FEF - FIFO Error Flag
50288 * 0b0..Receive overflow not detected.
50289 * 0b1..Receive overflow detected.
50290 */
50291#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
50292#define I2S_RCSR_SEF_MASK (0x80000U)
50293#define I2S_RCSR_SEF_SHIFT (19U)
50294/*! SEF - Sync Error Flag
50295 * 0b0..Sync error not detected.
50296 * 0b1..Frame sync error detected.
50297 */
50298#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
50299#define I2S_RCSR_WSF_MASK (0x100000U)
50300#define I2S_RCSR_WSF_SHIFT (20U)
50301/*! WSF - Word Start Flag
50302 * 0b0..Start of word not detected.
50303 * 0b1..Start of word detected.
50304 */
50305#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
50306#define I2S_RCSR_SR_MASK (0x1000000U)
50307#define I2S_RCSR_SR_SHIFT (24U)
50308/*! SR - Software Reset
50309 * 0b0..No effect.
50310 * 0b1..Software reset.
50311 */
50312#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
50313#define I2S_RCSR_FR_MASK (0x2000000U)
50314#define I2S_RCSR_FR_SHIFT (25U)
50315/*! FR - FIFO Reset
50316 * 0b0..No effect.
50317 * 0b1..FIFO reset.
50318 */
50319#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
50320#define I2S_RCSR_BCE_MASK (0x10000000U)
50321#define I2S_RCSR_BCE_SHIFT (28U)
50322/*! BCE - Bit Clock Enable
50323 * 0b0..Receive bit clock is disabled.
50324 * 0b1..Receive bit clock is enabled.
50325 */
50326#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
50327#define I2S_RCSR_DBGE_MASK (0x20000000U)
50328#define I2S_RCSR_DBGE_SHIFT (29U)
50329/*! DBGE - Debug Enable
50330 * 0b0..Receiver is disabled in Debug mode, after completing the current frame.
50331 * 0b1..Receiver is enabled in Debug mode.
50332 */
50333#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
50334#define I2S_RCSR_STOPE_MASK (0x40000000U)
50335#define I2S_RCSR_STOPE_SHIFT (30U)
50336/*! STOPE - Stop Enable
50337 * 0b0..Receiver disabled in Stop mode.
50338 * 0b1..Receiver enabled in Stop mode.
50339 */
50340#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
50341#define I2S_RCSR_RE_MASK (0x80000000U)
50342#define I2S_RCSR_RE_SHIFT (31U)
50343/*! RE - Receiver Enable
50344 * 0b0..Receiver is disabled.
50345 * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
50346 */
50347#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
50348/*! @} */
50349
50350/*! @name RCR1 - SAI Receive Configuration 1 Register */
50351/*! @{ */
50352#define I2S_RCR1_RFW_MASK (0x3FU)
50353#define I2S_RCR1_RFW_SHIFT (0U)
50354/*! RFW - Receive FIFO Watermark
50355 */
50356#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
50357/*! @} */
50358
50359/*! @name RCR2 - SAI Receive Configuration 2 Register */
50360/*! @{ */
50361#define I2S_RCR2_DIV_MASK (0xFFU)
50362#define I2S_RCR2_DIV_SHIFT (0U)
50363/*! DIV - Bit Clock Divide
50364 */
50365#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
50366#define I2S_RCR2_BCD_MASK (0x1000000U)
50367#define I2S_RCR2_BCD_SHIFT (24U)
50368/*! BCD - Bit Clock Direction
50369 * 0b0..Bit clock is generated externally in Slave mode.
50370 * 0b1..Bit clock is generated internally in Master mode.
50371 */
50372#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
50373#define I2S_RCR2_BCP_MASK (0x2000000U)
50374#define I2S_RCR2_BCP_SHIFT (25U)
50375/*! BCP - Bit Clock Polarity
50376 * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
50377 * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
50378 */
50379#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
50380#define I2S_RCR2_MSEL_MASK (0xC000000U)
50381#define I2S_RCR2_MSEL_SHIFT (26U)
50382/*! MSEL - MCLK Select
50383 * 0b00..Bus Clock selected.
50384 * 0b01..Master Clock (MCLK) 1 option selected.
50385 * 0b10..Master Clock (MCLK) 2 option selected.
50386 * 0b11..Master Clock (MCLK) 3 option selected.
50387 */
50388#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
50389#define I2S_RCR2_BCI_MASK (0x10000000U)
50390#define I2S_RCR2_BCI_SHIFT (28U)
50391/*! BCI - Bit Clock Input
50392 * 0b0..No effect.
50393 * 0b1..Internal logic is clocked as if bit clock was externally generated.
50394 */
50395#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
50396#define I2S_RCR2_BCS_MASK (0x20000000U)
50397#define I2S_RCR2_BCS_SHIFT (29U)
50398/*! BCS - Bit Clock Swap
50399 * 0b0..Use the normal bit clock source.
50400 * 0b1..Swap the bit clock source.
50401 */
50402#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
50403#define I2S_RCR2_SYNC_MASK (0xC0000000U)
50404#define I2S_RCR2_SYNC_SHIFT (30U)
50405/*! SYNC - Synchronous Mode
50406 * 0b00..Asynchronous mode.
50407 * 0b01..Synchronous with transmitter.
50408 * 0b10..Synchronous with another SAI receiver.
50409 * 0b11..Synchronous with another SAI transmitter.
50410 */
50411#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
50412/*! @} */
50413
50414/*! @name RCR3 - SAI Receive Configuration 3 Register */
50415/*! @{ */
50416#define I2S_RCR3_WDFL_MASK (0x1FU) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
50417#define I2S_RCR3_WDFL_SHIFT (0U)
50418/*! WDFL - Word Flag Configuration
50419 */
50420#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
50421#define I2S_RCR3_RCE_MASK (0x10000U)
50422#define I2S_RCR3_RCE_SHIFT (16U)
50423/*! RCE - Receive Channel Enable
50424 */
50425#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
50426/*! @} */
50427
50428/*! @name RCR4 - SAI Receive Configuration 4 Register */
50429/*! @{ */
50430#define I2S_RCR4_FSD_MASK (0x1U)
50431#define I2S_RCR4_FSD_SHIFT (0U)
50432/*! FSD - Frame Sync Direction
50433 * 0b0..Frame Sync is generated externally in Slave mode.
50434 * 0b1..Frame Sync is generated internally in Master mode.
50435 */
50436#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
50437#define I2S_RCR4_FSP_MASK (0x2U)
50438#define I2S_RCR4_FSP_SHIFT (1U)
50439/*! FSP - Frame Sync Polarity
50440 * 0b0..Frame sync is active high.
50441 * 0b1..Frame sync is active low.
50442 */
50443#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
50444#define I2S_RCR4_ONDEM_MASK (0x4U)
50445#define I2S_RCR4_ONDEM_SHIFT (2U)
50446/*! ONDEM - On Demand Mode
50447 * 0b0..Internal frame sync is generated continuously.
50448 * 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
50449 */
50450#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
50451#define I2S_RCR4_FSE_MASK (0x8U)
50452#define I2S_RCR4_FSE_SHIFT (3U)
50453/*! FSE - Frame Sync Early
50454 * 0b0..Frame sync asserts with the first bit of the frame.
50455 * 0b1..Frame sync asserts one bit before the first bit of the frame.
50456 */
50457#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
50458#define I2S_RCR4_MF_MASK (0x10U)
50459#define I2S_RCR4_MF_SHIFT (4U)
50460/*! MF - MSB First
50461 * 0b0..LSB is received first.
50462 * 0b1..MSB is received first.
50463 */
50464#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
50465#define I2S_RCR4_SYWD_MASK (0x1F00U)
50466#define I2S_RCR4_SYWD_SHIFT (8U)
50467/*! SYWD - Sync Width
50468 */
50469#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
50470#define I2S_RCR4_FRSZ_MASK (0x1F0000U) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
50471#define I2S_RCR4_FRSZ_SHIFT (16U)
50472/*! FRSZ - Frame Size
50473 */
50474#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
50475#define I2S_RCR4_FPACK_MASK (0x3000000U)
50476#define I2S_RCR4_FPACK_SHIFT (24U)
50477/*! FPACK - FIFO Packing Mode
50478 * 0b00..FIFO packing is disabled
50479 * 0b01..Reserved.
50480 * 0b10..8-bit FIFO packing is enabled
50481 * 0b11..16-bit FIFO packing is enabled
50482 */
50483#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
50484#define I2S_RCR4_FCONT_MASK (0x10000000U)
50485#define I2S_RCR4_FCONT_SHIFT (28U)
50486/*! FCONT - FIFO Continue on Error
50487 * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
50488 * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
50489 */
50490#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
50491/*! @} */
50492
50493/*! @name RCR5 - SAI Receive Configuration 5 Register */
50494/*! @{ */
50495#define I2S_RCR5_FBT_MASK (0x1F00U)
50496#define I2S_RCR5_FBT_SHIFT (8U)
50497/*! FBT - First Bit Shifted
50498 */
50499#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
50500#define I2S_RCR5_W0W_MASK (0x1F0000U)
50501#define I2S_RCR5_W0W_SHIFT (16U)
50502/*! W0W - Word 0 Width
50503 */
50504#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
50505#define I2S_RCR5_WNW_MASK (0x1F000000U)
50506#define I2S_RCR5_WNW_SHIFT (24U)
50507/*! WNW - Word N Width
50508 */
50509#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
50510/*! @} */
50511
50512/*! @name RDR - SAI Receive Data Register */
50513/*! @{ */
50514#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
50515#define I2S_RDR_RDR_SHIFT (0U)
50516/*! RDR - Receive Data Register
50517 */
50518#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
50519/*! @} */
50520
50521/* The count of I2S_RDR */
50522#define I2S_RDR_COUNT (1U)
50523
50524/*! @name RFR - SAI Receive FIFO Register */
50525/*! @{ */
50526#define I2S_RFR_RFP_MASK (0x7FU)
50527#define I2S_RFR_RFP_SHIFT (0U)
50528/*! RFP - Read FIFO Pointer
50529 */
50530#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
50531#define I2S_RFR_WFP_MASK (0x7F0000U)
50532#define I2S_RFR_WFP_SHIFT (16U)
50533/*! WFP - Write FIFO Pointer
50534 */
50535#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
50536/*! @} */
50537
50538/* The count of I2S_RFR */
50539#define I2S_RFR_COUNT (1U)
50540
50541/*! @name RMR - SAI Receive Mask Register */
50542/*! @{ */
50543#define I2S_RMR_RWM_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (8, 32), largest definition used */
50544#define I2S_RMR_RWM_SHIFT (0U)
50545/*! RWM - Receive Word Mask
50546 * 0b00000000000000000000000000000000..Word N is enabled.
50547 * 0b00000000000000000000000000000001..Word N is masked.
50548 */
50549#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK) /* Merged from fields with different position or width, of widths (8, 32), largest definition used */
50550/*! @} */
50551
50552
50553/*!
50554 * @}
50555 */ /* end of group I2S_Register_Masks */
50556
50557
50558/* I2S - Peripheral instance base addresses */
50559/** Peripheral ADMA__SAI0 base address */
50560#define ADMA__SAI0_BASE (0x59040000u)
50561/** Peripheral ADMA__SAI0 base pointer */
50562#define ADMA__SAI0 ((I2S_Type *)ADMA__SAI0_BASE)
50563/** Peripheral ADMA__SAI1 base address */
50564#define ADMA__SAI1_BASE (0x59050000u)
50565/** Peripheral ADMA__SAI1 base pointer */
50566#define ADMA__SAI1 ((I2S_Type *)ADMA__SAI1_BASE)
50567/** Peripheral ADMA__SAI2 base address */
50568#define ADMA__SAI2_BASE (0x59060000u)
50569/** Peripheral ADMA__SAI2 base pointer */
50570#define ADMA__SAI2 ((I2S_Type *)ADMA__SAI2_BASE)
50571/** Peripheral ADMA__SAI3 base address */
50572#define ADMA__SAI3_BASE (0x59070000u)
50573/** Peripheral ADMA__SAI3 base pointer */
50574#define ADMA__SAI3 ((I2S_Type *)ADMA__SAI3_BASE)
50575/** Peripheral ADMA__SAI4 base address */
50576#define ADMA__SAI4_BASE (0x59820000u)
50577/** Peripheral ADMA__SAI4 base pointer */
50578#define ADMA__SAI4 ((I2S_Type *)ADMA__SAI4_BASE)
50579/** Peripheral ADMA__SAI5 base address */
50580#define ADMA__SAI5_BASE (0x59830000u)
50581/** Peripheral ADMA__SAI5 base pointer */
50582#define ADMA__SAI5 ((I2S_Type *)ADMA__SAI5_BASE)
50583/** Array initializer of I2S peripheral base addresses */
50584#define I2S_BASE_ADDRS { ADMA__SAI0_BASE, ADMA__SAI1_BASE, ADMA__SAI2_BASE, ADMA__SAI3_BASE, ADMA__SAI4_BASE, ADMA__SAI5_BASE }
50585/** Array initializer of I2S peripheral base pointers */
50586#define I2S_BASE_PTRS { ADMA__SAI0, ADMA__SAI1, ADMA__SAI2, ADMA__SAI3, ADMA__SAI4, ADMA__SAI5 }
50587/** Interrupt vectors for the I2S peripheral type */
50588#define I2S_RX_IRQS { ADMA_SAI0_INT_IRQn, ADMA_SAI1_INT_IRQn, ADMA_SAI2_INT_IRQn, ADMA_SAI3_INT_IRQn, ADMA_SAI4_INT_IRQn, ADMA_SAI5_INT_IRQn }
50589#define I2S_TX_IRQS { ADMA_SAI0_INT_IRQn, ADMA_SAI1_INT_IRQn, ADMA_SAI2_INT_IRQn, ADMA_SAI3_INT_IRQn, ADMA_SAI4_INT_IRQn, ADMA_SAI5_INT_IRQn }
50590
50591/*!
50592 * @}
50593 */ /* end of group I2S_Peripheral_Access_Layer */
50594
50595
50596/* ----------------------------------------------------------------------------
50597 -- IMAGING_LPCG_MJPEG_COMMON_DEC Peripheral Access Layer
50598 ---------------------------------------------------------------------------- */
50599
50600/*!
50601 * @addtogroup IMAGING_LPCG_MJPEG_COMMON_DEC_Peripheral_Access_Layer IMAGING_LPCG_MJPEG_COMMON_DEC Peripheral Access Layer
50602 * @{
50603 */
50604
50605/** IMAGING_LPCG_MJPEG_COMMON_DEC - Register Layout Typedef */
50606typedef struct {
50607 __IO uint32_t LPCG_MJPEG_COMMON_DEC_0; /**< na, offset: 0x0 */
50608} IMAGING_LPCG_MJPEG_COMMON_DEC_Type;
50609
50610/* ----------------------------------------------------------------------------
50611 -- IMAGING_LPCG_MJPEG_COMMON_DEC Register Masks
50612 ---------------------------------------------------------------------------- */
50613
50614/*!
50615 * @addtogroup IMAGING_LPCG_MJPEG_COMMON_DEC_Register_Masks IMAGING_LPCG_MJPEG_COMMON_DEC Register Masks
50616 * @{
50617 */
50618
50619/*! @name LPCG_MJPEG_COMMON_DEC_0 - na */
50620/*! @{ */
50621#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_HWEN_MASK (0x1U)
50622#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_HWEN_SHIFT (0U)
50623/*! decode_jpeg_clk_HWEN - Hardware Enable
50624 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
50625 * 0b1..Enable HW automatic gating
50626 */
50627#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_HWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_HWEN_MASK)
50628#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_SWEN_MASK (0x2U)
50629#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_SWEN_SHIFT (1U)
50630/*! decode_jpeg_clk_SWEN - Software Enable
50631 * 0b0..Disable SW clock regardless of HWEN
50632 * 0b1..Enable SW clock gating
50633 */
50634#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_SWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_SWEN_MASK)
50635#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_2_2_MASK (0x4U)
50636#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_2_2_SHIFT (2U)
50637/*! LPCG_MJPEG_Common_Dec_0_reserved_2_2 - reserved
50638 */
50639#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_2_2_MASK)
50640#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_STOP_MASK (0x8U)
50641#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_STOP_SHIFT (3U)
50642/*! decode_jpeg_clk_STOP - show clock root status, 1 means clock stopped
50643 */
50644#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_STOP_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_jpeg_clk_STOP_MASK)
50645#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_4_16_MASK (0x1FFF0U)
50646#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_4_16_SHIFT (4U)
50647/*! LPCG_MJPEG_Common_Dec_0_reserved_4_16 - reserved
50648 */
50649#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_4_16_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_4_16_MASK)
50650#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_SWEN_MASK (0x20000U)
50651#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_SWEN_SHIFT (17U)
50652/*! decode_ips_clk_SWEN - Software Enable
50653 * 0b0..Disable SW clock regardless of HWEN
50654 * 0b1..Enable SW clock gating
50655 */
50656#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_SWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_SWEN_MASK)
50657#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_18_18_MASK (0x40000U)
50658#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_18_18_SHIFT (18U)
50659/*! LPCG_MJPEG_Common_Dec_0_reserved_18_18 - reserved
50660 */
50661#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_18_18_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_18_18_MASK)
50662#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_STOP_MASK (0x80000U)
50663#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_STOP_SHIFT (19U)
50664/*! decode_ips_clk_STOP - show clock root status, 1 means clock stopped
50665 */
50666#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_STOP_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_decode_ips_clk_STOP_MASK)
50667#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_20_31_MASK (0xFFF00000U)
50668#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_20_31_SHIFT (20U)
50669/*! LPCG_MJPEG_Common_Dec_0_reserved_20_31 - reserved
50670 */
50671#define IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_20_31_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_DEC_LPCG_MJPEG_COMMON_DEC_0_LPCG_MJPEG_Common_Dec_0_reserved_20_31_MASK)
50672/*! @} */
50673
50674
50675/*!
50676 * @}
50677 */ /* end of group IMAGING_LPCG_MJPEG_COMMON_DEC_Register_Masks */
50678
50679
50680/* IMAGING_LPCG_MJPEG_COMMON_DEC - Peripheral instance base addresses */
50681/** Peripheral IMAGING__LPCG_DECODE_IPS_CLK base address */
50682#define IMAGING__LPCG_DECODE_IPS_CLK_BASE (0x585D0000u)
50683/** Peripheral IMAGING__LPCG_DECODE_IPS_CLK base pointer */
50684#define IMAGING__LPCG_DECODE_IPS_CLK ((IMAGING_LPCG_MJPEG_COMMON_DEC_Type *)IMAGING__LPCG_DECODE_IPS_CLK_BASE)
50685/** Peripheral IMAGING__LPCG_DECODE_JPEG_CLK base address */
50686#define IMAGING__LPCG_DECODE_JPEG_CLK_BASE (0x585D0000u)
50687/** Peripheral IMAGING__LPCG_DECODE_JPEG_CLK base pointer */
50688#define IMAGING__LPCG_DECODE_JPEG_CLK ((IMAGING_LPCG_MJPEG_COMMON_DEC_Type *)IMAGING__LPCG_DECODE_JPEG_CLK_BASE)
50689/** Array initializer of IMAGING_LPCG_MJPEG_COMMON_DEC peripheral base addresses
50690 * */
50691#define IMAGING_LPCG_MJPEG_COMMON_DEC_BASE_ADDRS { IMAGING__LPCG_DECODE_IPS_CLK_BASE, IMAGING__LPCG_DECODE_JPEG_CLK_BASE }
50692/** Array initializer of IMAGING_LPCG_MJPEG_COMMON_DEC peripheral base pointers
50693 * */
50694#define IMAGING_LPCG_MJPEG_COMMON_DEC_BASE_PTRS { IMAGING__LPCG_DECODE_IPS_CLK, IMAGING__LPCG_DECODE_JPEG_CLK }
50695
50696/*!
50697 * @}
50698 */ /* end of group IMAGING_LPCG_MJPEG_COMMON_DEC_Peripheral_Access_Layer */
50699
50700
50701/* ----------------------------------------------------------------------------
50702 -- IMAGING_LPCG_MJPEG_COMMON_ENC Peripheral Access Layer
50703 ---------------------------------------------------------------------------- */
50704
50705/*!
50706 * @addtogroup IMAGING_LPCG_MJPEG_COMMON_ENC_Peripheral_Access_Layer IMAGING_LPCG_MJPEG_COMMON_ENC Peripheral Access Layer
50707 * @{
50708 */
50709
50710/** IMAGING_LPCG_MJPEG_COMMON_ENC - Register Layout Typedef */
50711typedef struct {
50712 __IO uint32_t LPCG_MJPEG_COMMON_ENC_0; /**< na, offset: 0x0 */
50713} IMAGING_LPCG_MJPEG_COMMON_ENC_Type;
50714
50715/* ----------------------------------------------------------------------------
50716 -- IMAGING_LPCG_MJPEG_COMMON_ENC Register Masks
50717 ---------------------------------------------------------------------------- */
50718
50719/*!
50720 * @addtogroup IMAGING_LPCG_MJPEG_COMMON_ENC_Register_Masks IMAGING_LPCG_MJPEG_COMMON_ENC Register Masks
50721 * @{
50722 */
50723
50724/*! @name LPCG_MJPEG_COMMON_ENC_0 - na */
50725/*! @{ */
50726#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_HWEN_MASK (0x1U)
50727#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_HWEN_SHIFT (0U)
50728/*! encode_jpeg_clk_HWEN - Hardware Enable
50729 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
50730 * 0b1..Enable HW automatic gating
50731 */
50732#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_HWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_HWEN_MASK)
50733#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_SWEN_MASK (0x2U)
50734#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_SWEN_SHIFT (1U)
50735/*! encode_jpeg_clk_SWEN - Software Enable
50736 * 0b0..Disable SW clock regardless of HWEN
50737 * 0b1..Enable SW clock gating
50738 */
50739#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_SWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_SWEN_MASK)
50740#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_2_2_MASK (0x4U)
50741#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_2_2_SHIFT (2U)
50742/*! LPCG_MJPEG_Common_Enc_0_reserved_2_2 - reserved
50743 */
50744#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_2_2_MASK)
50745#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_STOP_MASK (0x8U)
50746#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_STOP_SHIFT (3U)
50747/*! encode_jpeg_clk_STOP - show clock root status, 1 means clock stopped
50748 */
50749#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_STOP_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_jpeg_clk_STOP_MASK)
50750#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_4_16_MASK (0x1FFF0U)
50751#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_4_16_SHIFT (4U)
50752/*! LPCG_MJPEG_Common_Enc_0_reserved_4_16 - reserved
50753 */
50754#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_4_16_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_4_16_MASK)
50755#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_SWEN_MASK (0x20000U)
50756#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_SWEN_SHIFT (17U)
50757/*! encode_ips_clk_SWEN - Software Enable
50758 * 0b0..Disable SW clock regardless of HWEN
50759 * 0b1..Enable SW clock gating
50760 */
50761#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_SWEN_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_SWEN_MASK)
50762#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_18_18_MASK (0x40000U)
50763#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_18_18_SHIFT (18U)
50764/*! LPCG_MJPEG_Common_Enc_0_reserved_18_18 - reserved
50765 */
50766#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_18_18_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_18_18_MASK)
50767#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_STOP_MASK (0x80000U)
50768#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_STOP_SHIFT (19U)
50769/*! encode_ips_clk_STOP - show clock root status, 1 means clock stopped
50770 */
50771#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_STOP_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_encode_ips_clk_STOP_MASK)
50772#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_20_31_MASK (0xFFF00000U)
50773#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_20_31_SHIFT (20U)
50774/*! LPCG_MJPEG_Common_Enc_0_reserved_20_31 - reserved
50775 */
50776#define IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_20_31_SHIFT)) & IMAGING_LPCG_MJPEG_COMMON_ENC_LPCG_MJPEG_COMMON_ENC_0_LPCG_MJPEG_Common_Enc_0_reserved_20_31_MASK)
50777/*! @} */
50778
50779
50780/*!
50781 * @}
50782 */ /* end of group IMAGING_LPCG_MJPEG_COMMON_ENC_Register_Masks */
50783
50784
50785/* IMAGING_LPCG_MJPEG_COMMON_ENC - Peripheral instance base addresses */
50786/** Peripheral IMAGING__LPCG_ENCODE_IPS_CLK base address */
50787#define IMAGING__LPCG_ENCODE_IPS_CLK_BASE (0x585F0000u)
50788/** Peripheral IMAGING__LPCG_ENCODE_IPS_CLK base pointer */
50789#define IMAGING__LPCG_ENCODE_IPS_CLK ((IMAGING_LPCG_MJPEG_COMMON_ENC_Type *)IMAGING__LPCG_ENCODE_IPS_CLK_BASE)
50790/** Peripheral IMAGING__LPCG_ENCODE_JPEG_CLK base address */
50791#define IMAGING__LPCG_ENCODE_JPEG_CLK_BASE (0x585F0000u)
50792/** Peripheral IMAGING__LPCG_ENCODE_JPEG_CLK base pointer */
50793#define IMAGING__LPCG_ENCODE_JPEG_CLK ((IMAGING_LPCG_MJPEG_COMMON_ENC_Type *)IMAGING__LPCG_ENCODE_JPEG_CLK_BASE)
50794/** Array initializer of IMAGING_LPCG_MJPEG_COMMON_ENC peripheral base addresses
50795 * */
50796#define IMAGING_LPCG_MJPEG_COMMON_ENC_BASE_ADDRS { IMAGING__LPCG_ENCODE_IPS_CLK_BASE, IMAGING__LPCG_ENCODE_JPEG_CLK_BASE }
50797/** Array initializer of IMAGING_LPCG_MJPEG_COMMON_ENC peripheral base pointers
50798 * */
50799#define IMAGING_LPCG_MJPEG_COMMON_ENC_BASE_PTRS { IMAGING__LPCG_ENCODE_IPS_CLK, IMAGING__LPCG_ENCODE_JPEG_CLK }
50800
50801/*!
50802 * @}
50803 */ /* end of group IMAGING_LPCG_MJPEG_COMMON_ENC_Peripheral_Access_Layer */
50804
50805
50806/* ----------------------------------------------------------------------------
50807 -- IMAGING_LPCG_PDMA0 Peripheral Access Layer
50808 ---------------------------------------------------------------------------- */
50809
50810/*!
50811 * @addtogroup IMAGING_LPCG_PDMA0_Peripheral_Access_Layer IMAGING_LPCG_PDMA0 Peripheral Access Layer
50812 * @{
50813 */
50814
50815/** IMAGING_LPCG_PDMA0 - Register Layout Typedef */
50816typedef struct {
50817 __IO uint32_t LPCG_PDMA0_0; /**< na, offset: 0x0 */
50818} IMAGING_LPCG_PDMA0_Type;
50819
50820/* ----------------------------------------------------------------------------
50821 -- IMAGING_LPCG_PDMA0 Register Masks
50822 ---------------------------------------------------------------------------- */
50823
50824/*!
50825 * @addtogroup IMAGING_LPCG_PDMA0_Register_Masks IMAGING_LPCG_PDMA0 Register Masks
50826 * @{
50827 */
50828
50829/*! @name LPCG_PDMA0_0 - na */
50830/*! @{ */
50831#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_HWEN_MASK (0x1U)
50832#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_HWEN_SHIFT (0U)
50833/*! isi_ipg_proc_clk_0_HWEN - Hardware Enable
50834 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
50835 * 0b1..Enable HW automatic gating
50836 */
50837#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_HWEN_SHIFT)) & IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_HWEN_MASK)
50838#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_SWEN_MASK (0x2U)
50839#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_SWEN_SHIFT (1U)
50840/*! isi_ipg_proc_clk_0_SWEN - Software Enable
50841 * 0b0..Disable SW clock regardless of HWEN
50842 * 0b1..Enable SW clock gating
50843 */
50844#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_SWEN_SHIFT)) & IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_SWEN_MASK)
50845#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_2_2_MASK (0x4U)
50846#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_2_2_SHIFT (2U)
50847/*! LPCG_PDMA0_0_reserved_2_2 - reserved
50848 */
50849#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_2_2_MASK)
50850#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_STOP_MASK (0x8U)
50851#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_STOP_SHIFT (3U)
50852/*! isi_ipg_proc_clk_0_STOP - show clock root status, 1 means clock stopped
50853 */
50854#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_STOP_SHIFT)) & IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_isi_ipg_proc_clk_0_STOP_MASK)
50855#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_4_31_MASK (0xFFFFFFF0U)
50856#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_4_31_SHIFT (4U)
50857/*! LPCG_PDMA0_0_reserved_4_31 - reserved
50858 */
50859#define IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA0_LPCG_PDMA0_0_LPCG_PDMA0_0_reserved_4_31_MASK)
50860/*! @} */
50861
50862
50863/*!
50864 * @}
50865 */ /* end of group IMAGING_LPCG_PDMA0_Register_Masks */
50866
50867
50868/* IMAGING_LPCG_PDMA0 - Peripheral instance base addresses */
50869/** Peripheral IMAGING__LPCG_PROC_CLK_0 base address */
50870#define IMAGING__LPCG_PROC_CLK_0_BASE (0x58500000u)
50871/** Peripheral IMAGING__LPCG_PROC_CLK_0 base pointer */
50872#define IMAGING__LPCG_PROC_CLK_0 ((IMAGING_LPCG_PDMA0_Type *)IMAGING__LPCG_PROC_CLK_0_BASE)
50873/** Array initializer of IMAGING_LPCG_PDMA0 peripheral base addresses */
50874#define IMAGING_LPCG_PDMA0_BASE_ADDRS { IMAGING__LPCG_PROC_CLK_0_BASE }
50875/** Array initializer of IMAGING_LPCG_PDMA0 peripheral base pointers */
50876#define IMAGING_LPCG_PDMA0_BASE_PTRS { IMAGING__LPCG_PROC_CLK_0 }
50877
50878/*!
50879 * @}
50880 */ /* end of group IMAGING_LPCG_PDMA0_Peripheral_Access_Layer */
50881
50882
50883/* ----------------------------------------------------------------------------
50884 -- IMAGING_LPCG_PDMA1 Peripheral Access Layer
50885 ---------------------------------------------------------------------------- */
50886
50887/*!
50888 * @addtogroup IMAGING_LPCG_PDMA1_Peripheral_Access_Layer IMAGING_LPCG_PDMA1 Peripheral Access Layer
50889 * @{
50890 */
50891
50892/** IMAGING_LPCG_PDMA1 - Register Layout Typedef */
50893typedef struct {
50894 __IO uint32_t LPCG_PDMA1_0; /**< na, offset: 0x0 */
50895} IMAGING_LPCG_PDMA1_Type;
50896
50897/* ----------------------------------------------------------------------------
50898 -- IMAGING_LPCG_PDMA1 Register Masks
50899 ---------------------------------------------------------------------------- */
50900
50901/*!
50902 * @addtogroup IMAGING_LPCG_PDMA1_Register_Masks IMAGING_LPCG_PDMA1 Register Masks
50903 * @{
50904 */
50905
50906/*! @name LPCG_PDMA1_0 - na */
50907/*! @{ */
50908#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_HWEN_MASK (0x1U)
50909#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_HWEN_SHIFT (0U)
50910/*! isi_ipg_proc_clk_1_HWEN - Hardware Enable
50911 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
50912 * 0b1..Enable HW automatic gating
50913 */
50914#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_HWEN_SHIFT)) & IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_HWEN_MASK)
50915#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_SWEN_MASK (0x2U)
50916#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_SWEN_SHIFT (1U)
50917/*! isi_ipg_proc_clk_1_SWEN - Software Enable
50918 * 0b0..Disable SW clock regardless of HWEN
50919 * 0b1..Enable SW clock gating
50920 */
50921#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_SWEN_SHIFT)) & IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_SWEN_MASK)
50922#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_2_2_MASK (0x4U)
50923#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_2_2_SHIFT (2U)
50924/*! LPCG_PDMA1_0_reserved_2_2 - reserved
50925 */
50926#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_2_2_MASK)
50927#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_STOP_MASK (0x8U)
50928#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_STOP_SHIFT (3U)
50929/*! isi_ipg_proc_clk_1_STOP - show clock root status, 1 means clock stopped
50930 */
50931#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_STOP_SHIFT)) & IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_isi_ipg_proc_clk_1_STOP_MASK)
50932#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_4_31_MASK (0xFFFFFFF0U)
50933#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_4_31_SHIFT (4U)
50934/*! LPCG_PDMA1_0_reserved_4_31 - reserved
50935 */
50936#define IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA1_LPCG_PDMA1_0_LPCG_PDMA1_0_reserved_4_31_MASK)
50937/*! @} */
50938
50939
50940/*!
50941 * @}
50942 */ /* end of group IMAGING_LPCG_PDMA1_Register_Masks */
50943
50944
50945/* IMAGING_LPCG_PDMA1 - Peripheral instance base addresses */
50946/** Peripheral IMAGING__LPCG_PROC_CLK_1 base address */
50947#define IMAGING__LPCG_PROC_CLK_1_BASE (0x58510000u)
50948/** Peripheral IMAGING__LPCG_PROC_CLK_1 base pointer */
50949#define IMAGING__LPCG_PROC_CLK_1 ((IMAGING_LPCG_PDMA1_Type *)IMAGING__LPCG_PROC_CLK_1_BASE)
50950/** Array initializer of IMAGING_LPCG_PDMA1 peripheral base addresses */
50951#define IMAGING_LPCG_PDMA1_BASE_ADDRS { IMAGING__LPCG_PROC_CLK_1_BASE }
50952/** Array initializer of IMAGING_LPCG_PDMA1 peripheral base pointers */
50953#define IMAGING_LPCG_PDMA1_BASE_PTRS { IMAGING__LPCG_PROC_CLK_1 }
50954
50955/*!
50956 * @}
50957 */ /* end of group IMAGING_LPCG_PDMA1_Peripheral_Access_Layer */
50958
50959
50960/* ----------------------------------------------------------------------------
50961 -- IMAGING_LPCG_PDMA2 Peripheral Access Layer
50962 ---------------------------------------------------------------------------- */
50963
50964/*!
50965 * @addtogroup IMAGING_LPCG_PDMA2_Peripheral_Access_Layer IMAGING_LPCG_PDMA2 Peripheral Access Layer
50966 * @{
50967 */
50968
50969/** IMAGING_LPCG_PDMA2 - Register Layout Typedef */
50970typedef struct {
50971 __IO uint32_t LPCG_PDMA2_0; /**< na, offset: 0x0 */
50972} IMAGING_LPCG_PDMA2_Type;
50973
50974/* ----------------------------------------------------------------------------
50975 -- IMAGING_LPCG_PDMA2 Register Masks
50976 ---------------------------------------------------------------------------- */
50977
50978/*!
50979 * @addtogroup IMAGING_LPCG_PDMA2_Register_Masks IMAGING_LPCG_PDMA2 Register Masks
50980 * @{
50981 */
50982
50983/*! @name LPCG_PDMA2_0 - na */
50984/*! @{ */
50985#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_HWEN_MASK (0x1U)
50986#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_HWEN_SHIFT (0U)
50987/*! isi_ipg_proc_clk_2_HWEN - Hardware Enable
50988 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
50989 * 0b1..Enable HW automatic gating
50990 */
50991#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_HWEN_SHIFT)) & IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_HWEN_MASK)
50992#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_SWEN_MASK (0x2U)
50993#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_SWEN_SHIFT (1U)
50994/*! isi_ipg_proc_clk_2_SWEN - Software Enable
50995 * 0b0..Disable SW clock regardless of HWEN
50996 * 0b1..Enable SW clock gating
50997 */
50998#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_SWEN_SHIFT)) & IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_SWEN_MASK)
50999#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_2_2_MASK (0x4U)
51000#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_2_2_SHIFT (2U)
51001/*! LPCG_PDMA2_0_reserved_2_2 - reserved
51002 */
51003#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_2_2_MASK)
51004#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_STOP_MASK (0x8U)
51005#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_STOP_SHIFT (3U)
51006/*! isi_ipg_proc_clk_2_STOP - show clock root status, 1 means clock stopped
51007 */
51008#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_STOP_SHIFT)) & IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_isi_ipg_proc_clk_2_STOP_MASK)
51009#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_4_31_MASK (0xFFFFFFF0U)
51010#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_4_31_SHIFT (4U)
51011/*! LPCG_PDMA2_0_reserved_4_31 - reserved
51012 */
51013#define IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA2_LPCG_PDMA2_0_LPCG_PDMA2_0_reserved_4_31_MASK)
51014/*! @} */
51015
51016
51017/*!
51018 * @}
51019 */ /* end of group IMAGING_LPCG_PDMA2_Register_Masks */
51020
51021
51022/* IMAGING_LPCG_PDMA2 - Peripheral instance base addresses */
51023/** Peripheral IMAGING__LPCG_PROC_CLK_2 base address */
51024#define IMAGING__LPCG_PROC_CLK_2_BASE (0x58520000u)
51025/** Peripheral IMAGING__LPCG_PROC_CLK_2 base pointer */
51026#define IMAGING__LPCG_PROC_CLK_2 ((IMAGING_LPCG_PDMA2_Type *)IMAGING__LPCG_PROC_CLK_2_BASE)
51027/** Array initializer of IMAGING_LPCG_PDMA2 peripheral base addresses */
51028#define IMAGING_LPCG_PDMA2_BASE_ADDRS { IMAGING__LPCG_PROC_CLK_2_BASE }
51029/** Array initializer of IMAGING_LPCG_PDMA2 peripheral base pointers */
51030#define IMAGING_LPCG_PDMA2_BASE_PTRS { IMAGING__LPCG_PROC_CLK_2 }
51031
51032/*!
51033 * @}
51034 */ /* end of group IMAGING_LPCG_PDMA2_Peripheral_Access_Layer */
51035
51036
51037/* ----------------------------------------------------------------------------
51038 -- IMAGING_LPCG_PDMA3 Peripheral Access Layer
51039 ---------------------------------------------------------------------------- */
51040
51041/*!
51042 * @addtogroup IMAGING_LPCG_PDMA3_Peripheral_Access_Layer IMAGING_LPCG_PDMA3 Peripheral Access Layer
51043 * @{
51044 */
51045
51046/** IMAGING_LPCG_PDMA3 - Register Layout Typedef */
51047typedef struct {
51048 __IO uint32_t LPCG_PDMA3_0; /**< na, offset: 0x0 */
51049} IMAGING_LPCG_PDMA3_Type;
51050
51051/* ----------------------------------------------------------------------------
51052 -- IMAGING_LPCG_PDMA3 Register Masks
51053 ---------------------------------------------------------------------------- */
51054
51055/*!
51056 * @addtogroup IMAGING_LPCG_PDMA3_Register_Masks IMAGING_LPCG_PDMA3 Register Masks
51057 * @{
51058 */
51059
51060/*! @name LPCG_PDMA3_0 - na */
51061/*! @{ */
51062#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_HWEN_MASK (0x1U)
51063#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_HWEN_SHIFT (0U)
51064/*! isi_ipg_proc_clk_3_HWEN - Hardware Enable
51065 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
51066 * 0b1..Enable HW automatic gating
51067 */
51068#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_HWEN_SHIFT)) & IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_HWEN_MASK)
51069#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_SWEN_MASK (0x2U)
51070#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_SWEN_SHIFT (1U)
51071/*! isi_ipg_proc_clk_3_SWEN - Software Enable
51072 * 0b0..Disable SW clock regardless of HWEN
51073 * 0b1..Enable SW clock gating
51074 */
51075#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_SWEN_SHIFT)) & IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_SWEN_MASK)
51076#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_2_2_MASK (0x4U)
51077#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_2_2_SHIFT (2U)
51078/*! LPCG_PDMA3_0_reserved_2_2 - reserved
51079 */
51080#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_2_2_MASK)
51081#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_STOP_MASK (0x8U)
51082#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_STOP_SHIFT (3U)
51083/*! isi_ipg_proc_clk_3_STOP - show clock root status, 1 means clock stopped
51084 */
51085#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_STOP_SHIFT)) & IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_isi_ipg_proc_clk_3_STOP_MASK)
51086#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_4_31_MASK (0xFFFFFFF0U)
51087#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_4_31_SHIFT (4U)
51088/*! LPCG_PDMA3_0_reserved_4_31 - reserved
51089 */
51090#define IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA3_LPCG_PDMA3_0_LPCG_PDMA3_0_reserved_4_31_MASK)
51091/*! @} */
51092
51093
51094/*!
51095 * @}
51096 */ /* end of group IMAGING_LPCG_PDMA3_Register_Masks */
51097
51098
51099/* IMAGING_LPCG_PDMA3 - Peripheral instance base addresses */
51100/** Peripheral IMAGING__LPCG_PROC_CLK_3 base address */
51101#define IMAGING__LPCG_PROC_CLK_3_BASE (0x58530000u)
51102/** Peripheral IMAGING__LPCG_PROC_CLK_3 base pointer */
51103#define IMAGING__LPCG_PROC_CLK_3 ((IMAGING_LPCG_PDMA3_Type *)IMAGING__LPCG_PROC_CLK_3_BASE)
51104/** Array initializer of IMAGING_LPCG_PDMA3 peripheral base addresses */
51105#define IMAGING_LPCG_PDMA3_BASE_ADDRS { IMAGING__LPCG_PROC_CLK_3_BASE }
51106/** Array initializer of IMAGING_LPCG_PDMA3 peripheral base pointers */
51107#define IMAGING_LPCG_PDMA3_BASE_PTRS { IMAGING__LPCG_PROC_CLK_3 }
51108
51109/*!
51110 * @}
51111 */ /* end of group IMAGING_LPCG_PDMA3_Peripheral_Access_Layer */
51112
51113
51114/* ----------------------------------------------------------------------------
51115 -- IMAGING_LPCG_PDMA4 Peripheral Access Layer
51116 ---------------------------------------------------------------------------- */
51117
51118/*!
51119 * @addtogroup IMAGING_LPCG_PDMA4_Peripheral_Access_Layer IMAGING_LPCG_PDMA4 Peripheral Access Layer
51120 * @{
51121 */
51122
51123/** IMAGING_LPCG_PDMA4 - Register Layout Typedef */
51124typedef struct {
51125 __IO uint32_t LPCG_PDMA4_0; /**< na, offset: 0x0 */
51126} IMAGING_LPCG_PDMA4_Type;
51127
51128/* ----------------------------------------------------------------------------
51129 -- IMAGING_LPCG_PDMA4 Register Masks
51130 ---------------------------------------------------------------------------- */
51131
51132/*!
51133 * @addtogroup IMAGING_LPCG_PDMA4_Register_Masks IMAGING_LPCG_PDMA4 Register Masks
51134 * @{
51135 */
51136
51137/*! @name LPCG_PDMA4_0 - na */
51138/*! @{ */
51139#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_HWEN_MASK (0x1U)
51140#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_HWEN_SHIFT (0U)
51141/*! isi_ipg_proc_clk_4_HWEN - Hardware Enable
51142 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
51143 * 0b1..Enable HW automatic gating
51144 */
51145#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_HWEN_SHIFT)) & IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_HWEN_MASK)
51146#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_SWEN_MASK (0x2U)
51147#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_SWEN_SHIFT (1U)
51148/*! isi_ipg_proc_clk_4_SWEN - Software Enable
51149 * 0b0..Disable SW clock regardless of HWEN
51150 * 0b1..Enable SW clock gating
51151 */
51152#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_SWEN_SHIFT)) & IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_SWEN_MASK)
51153#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_2_2_MASK (0x4U)
51154#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_2_2_SHIFT (2U)
51155/*! LPCG_PDMA4_0_reserved_2_2 - reserved
51156 */
51157#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_2_2_MASK)
51158#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_STOP_MASK (0x8U)
51159#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_STOP_SHIFT (3U)
51160/*! isi_ipg_proc_clk_4_STOP - show clock root status, 1 means clock stopped
51161 */
51162#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_STOP_SHIFT)) & IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_isi_ipg_proc_clk_4_STOP_MASK)
51163#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_4_31_MASK (0xFFFFFFF0U)
51164#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_4_31_SHIFT (4U)
51165/*! LPCG_PDMA4_0_reserved_4_31 - reserved
51166 */
51167#define IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA4_LPCG_PDMA4_0_LPCG_PDMA4_0_reserved_4_31_MASK)
51168/*! @} */
51169
51170
51171/*!
51172 * @}
51173 */ /* end of group IMAGING_LPCG_PDMA4_Register_Masks */
51174
51175
51176/* IMAGING_LPCG_PDMA4 - Peripheral instance base addresses */
51177/** Peripheral IMAGING__LPCG_PROC_CLK_4 base address */
51178#define IMAGING__LPCG_PROC_CLK_4_BASE (0x58540000u)
51179/** Peripheral IMAGING__LPCG_PROC_CLK_4 base pointer */
51180#define IMAGING__LPCG_PROC_CLK_4 ((IMAGING_LPCG_PDMA4_Type *)IMAGING__LPCG_PROC_CLK_4_BASE)
51181/** Array initializer of IMAGING_LPCG_PDMA4 peripheral base addresses */
51182#define IMAGING_LPCG_PDMA4_BASE_ADDRS { IMAGING__LPCG_PROC_CLK_4_BASE }
51183/** Array initializer of IMAGING_LPCG_PDMA4 peripheral base pointers */
51184#define IMAGING_LPCG_PDMA4_BASE_PTRS { IMAGING__LPCG_PROC_CLK_4 }
51185
51186/*!
51187 * @}
51188 */ /* end of group IMAGING_LPCG_PDMA4_Peripheral_Access_Layer */
51189
51190
51191/* ----------------------------------------------------------------------------
51192 -- IMAGING_LPCG_PDMA5 Peripheral Access Layer
51193 ---------------------------------------------------------------------------- */
51194
51195/*!
51196 * @addtogroup IMAGING_LPCG_PDMA5_Peripheral_Access_Layer IMAGING_LPCG_PDMA5 Peripheral Access Layer
51197 * @{
51198 */
51199
51200/** IMAGING_LPCG_PDMA5 - Register Layout Typedef */
51201typedef struct {
51202 __IO uint32_t LPCG_PDMA5_0; /**< na, offset: 0x0 */
51203} IMAGING_LPCG_PDMA5_Type;
51204
51205/* ----------------------------------------------------------------------------
51206 -- IMAGING_LPCG_PDMA5 Register Masks
51207 ---------------------------------------------------------------------------- */
51208
51209/*!
51210 * @addtogroup IMAGING_LPCG_PDMA5_Register_Masks IMAGING_LPCG_PDMA5 Register Masks
51211 * @{
51212 */
51213
51214/*! @name LPCG_PDMA5_0 - na */
51215/*! @{ */
51216#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_HWEN_MASK (0x1U)
51217#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_HWEN_SHIFT (0U)
51218/*! isi_ipg_proc_clk_5_HWEN - Hardware Enable
51219 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
51220 * 0b1..Enable HW automatic gating
51221 */
51222#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_HWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_HWEN_SHIFT)) & IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_HWEN_MASK)
51223#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_SWEN_MASK (0x2U)
51224#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_SWEN_SHIFT (1U)
51225/*! isi_ipg_proc_clk_5_SWEN - Software Enable
51226 * 0b0..Disable SW clock regardless of HWEN
51227 * 0b1..Enable SW clock gating
51228 */
51229#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_SWEN_SHIFT)) & IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_SWEN_MASK)
51230#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_2_2_MASK (0x4U)
51231#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_2_2_SHIFT (2U)
51232/*! LPCG_PDMA5_0_reserved_2_2 - reserved
51233 */
51234#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_2_2_MASK)
51235#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_STOP_MASK (0x8U)
51236#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_STOP_SHIFT (3U)
51237/*! isi_ipg_proc_clk_5_STOP - show clock root status, 1 means clock stopped
51238 */
51239#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_STOP_SHIFT)) & IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_isi_ipg_proc_clk_5_STOP_MASK)
51240#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_4_31_MASK (0xFFFFFFF0U)
51241#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_4_31_SHIFT (4U)
51242/*! LPCG_PDMA5_0_reserved_4_31 - reserved
51243 */
51244#define IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PDMA5_LPCG_PDMA5_0_LPCG_PDMA5_0_reserved_4_31_MASK)
51245/*! @} */
51246
51247
51248/*!
51249 * @}
51250 */ /* end of group IMAGING_LPCG_PDMA5_Register_Masks */
51251
51252
51253/* IMAGING_LPCG_PDMA5 - Peripheral instance base addresses */
51254/** Peripheral IMAGING__LPCG_PROC_CLK_5 base address */
51255#define IMAGING__LPCG_PROC_CLK_5_BASE (0x58550000u)
51256/** Peripheral IMAGING__LPCG_PROC_CLK_5 base pointer */
51257#define IMAGING__LPCG_PROC_CLK_5 ((IMAGING_LPCG_PDMA5_Type *)IMAGING__LPCG_PROC_CLK_5_BASE)
51258/** Array initializer of IMAGING_LPCG_PDMA5 peripheral base addresses */
51259#define IMAGING_LPCG_PDMA5_BASE_ADDRS { IMAGING__LPCG_PROC_CLK_5_BASE }
51260/** Array initializer of IMAGING_LPCG_PDMA5 peripheral base pointers */
51261#define IMAGING_LPCG_PDMA5_BASE_PTRS { IMAGING__LPCG_PROC_CLK_5 }
51262
51263/*!
51264 * @}
51265 */ /* end of group IMAGING_LPCG_PDMA5_Peripheral_Access_Layer */
51266
51267
51268/* ----------------------------------------------------------------------------
51269 -- IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 Peripheral Access Layer
51270 ---------------------------------------------------------------------------- */
51271
51272/*!
51273 * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Peripheral_Access_Layer IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 Peripheral Access Layer
51274 * @{
51275 */
51276
51277/** IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 - Register Layout Typedef */
51278typedef struct {
51279 __IO uint32_t LPCG_PIXEL_LINK_SLAVE_CSI1_0; /**< na, offset: 0x0 */
51280} IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Type;
51281
51282/* ----------------------------------------------------------------------------
51283 -- IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 Register Masks
51284 ---------------------------------------------------------------------------- */
51285
51286/*!
51287 * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Register_Masks IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 Register Masks
51288 * @{
51289 */
51290
51291/*! @name LPCG_PIXEL_LINK_SLAVE_CSI1_0 - na */
51292/*! @{ */
51293#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0_MASK (0x1U)
51294#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0_SHIFT (0U)
51295/*! LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0 - reserved
51296 */
51297#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_0_0_MASK)
51298#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_SWEN_MASK (0x2U)
51299#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_SWEN_SHIFT (1U)
51300/*! pixel_link_slv_csi1_ingress_clk_SWEN - Software Enable
51301 * 0b0..Disable SW clock regardless of HWEN
51302 * 0b1..Enable SW clock gating
51303 */
51304#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_SWEN_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_SWEN_MASK)
51305#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2_MASK (0x4U)
51306#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2_SHIFT (2U)
51307/*! LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2 - reserved
51308 */
51309#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_2_2_MASK)
51310#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_STOP_MASK (0x8U)
51311#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_STOP_SHIFT (3U)
51312/*! pixel_link_slv_csi1_ingress_clk_STOP - show clock root status, 1 means clock stopped
51313 */
51314#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_STOP_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_pixel_link_slv_csi1_ingress_clk_STOP_MASK)
51315#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31_MASK (0xFFFFFFF0U)
51316#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31_SHIFT (4U)
51317/*! LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31 - reserved
51318 */
51319#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_LPCG_PIXEL_LINK_SLAVE_CSI1_0_LPCG_Pixel_Link_Slave_csi1_0_reserved_4_31_MASK)
51320/*! @} */
51321
51322
51323/*!
51324 * @}
51325 */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Register_Masks */
51326
51327
51328/* IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 - Peripheral instance base addresses */
51329/** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_CSI0 base address */
51330#define IMAGING__LPCG_PIXEL_LINK_SLV_CSI0_BASE (0x58580000u)
51331/** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_CSI0 base pointer */
51332#define IMAGING__LPCG_PIXEL_LINK_SLV_CSI0 ((IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Type *)IMAGING__LPCG_PIXEL_LINK_SLV_CSI0_BASE)
51333/** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 peripheral base
51334 * addresses */
51335#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_BASE_ADDRS { IMAGING__LPCG_PIXEL_LINK_SLV_CSI0_BASE }
51336/** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0 peripheral base
51337 * pointers */
51338#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_BASE_PTRS { IMAGING__LPCG_PIXEL_LINK_SLV_CSI0 }
51339
51340/*!
51341 * @}
51342 */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI0_Peripheral_Access_Layer */
51343
51344
51345/* ----------------------------------------------------------------------------
51346 -- IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 Peripheral Access Layer
51347 ---------------------------------------------------------------------------- */
51348
51349/*!
51350 * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Peripheral_Access_Layer IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 Peripheral Access Layer
51351 * @{
51352 */
51353
51354/** IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 - Register Layout Typedef */
51355typedef struct {
51356 __IO uint32_t LPCG_PIXEL_LINK_SLAVE_CSI2_0; /**< na, offset: 0x0 */
51357} IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Type;
51358
51359/* ----------------------------------------------------------------------------
51360 -- IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 Register Masks
51361 ---------------------------------------------------------------------------- */
51362
51363/*!
51364 * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Register_Masks IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 Register Masks
51365 * @{
51366 */
51367
51368/*! @name LPCG_PIXEL_LINK_SLAVE_CSI2_0 - na */
51369/*! @{ */
51370#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0_MASK (0x1U)
51371#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0_SHIFT (0U)
51372/*! LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0 - reserved
51373 */
51374#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_0_0_MASK)
51375#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_SWEN_MASK (0x2U)
51376#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_SWEN_SHIFT (1U)
51377/*! pixel_link_slv_csi2_ingress_clk_SWEN - Software Enable
51378 * 0b0..Disable SW clock regardless of HWEN
51379 * 0b1..Enable SW clock gating
51380 */
51381#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_SWEN_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_SWEN_MASK)
51382#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2_MASK (0x4U)
51383#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2_SHIFT (2U)
51384/*! LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2 - reserved
51385 */
51386#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_2_2_MASK)
51387#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_STOP_MASK (0x8U)
51388#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_STOP_SHIFT (3U)
51389/*! pixel_link_slv_csi2_ingress_clk_STOP - show clock root status, 1 means clock stopped
51390 */
51391#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_STOP_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_pixel_link_slv_csi2_ingress_clk_STOP_MASK)
51392#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31_MASK (0xFFFFFFF0U)
51393#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31_SHIFT (4U)
51394/*! LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31 - reserved
51395 */
51396#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_LPCG_PIXEL_LINK_SLAVE_CSI2_0_LPCG_Pixel_Link_Slave_csi2_0_reserved_4_31_MASK)
51397/*! @} */
51398
51399
51400/*!
51401 * @}
51402 */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Register_Masks */
51403
51404
51405/* IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 - Peripheral instance base addresses */
51406/** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_CSI1 base address */
51407#define IMAGING__LPCG_PIXEL_LINK_SLV_CSI1_BASE (0x58590000u)
51408/** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_CSI1 base pointer */
51409#define IMAGING__LPCG_PIXEL_LINK_SLV_CSI1 ((IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Type *)IMAGING__LPCG_PIXEL_LINK_SLV_CSI1_BASE)
51410/** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 peripheral base
51411 * addresses */
51412#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_BASE_ADDRS { IMAGING__LPCG_PIXEL_LINK_SLV_CSI1_BASE }
51413/** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1 peripheral base
51414 * pointers */
51415#define IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_BASE_PTRS { IMAGING__LPCG_PIXEL_LINK_SLV_CSI1 }
51416
51417/*!
51418 * @}
51419 */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_CSI1_Peripheral_Access_Layer */
51420
51421
51422/* ----------------------------------------------------------------------------
51423 -- IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 Peripheral Access Layer
51424 ---------------------------------------------------------------------------- */
51425
51426/*!
51427 * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Peripheral_Access_Layer IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 Peripheral Access Layer
51428 * @{
51429 */
51430
51431/** IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 - Register Layout Typedef */
51432typedef struct {
51433 __IO uint32_t LPCG_PIXEL_LINK_SLAVE_DC0_0; /**< na, offset: 0x0 */
51434} IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Type;
51435
51436/* ----------------------------------------------------------------------------
51437 -- IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 Register Masks
51438 ---------------------------------------------------------------------------- */
51439
51440/*!
51441 * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Register_Masks IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 Register Masks
51442 * @{
51443 */
51444
51445/*! @name LPCG_PIXEL_LINK_SLAVE_DC0_0 - na */
51446/*! @{ */
51447#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0_MASK (0x1U)
51448#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0_SHIFT (0U)
51449/*! LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0 - reserved
51450 */
51451#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_0_0_MASK)
51452#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_SWEN_MASK (0x2U)
51453#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_SWEN_SHIFT (1U)
51454/*! pixel_link_slv_dc0_ingress_clk_SWEN - Software Enable
51455 * 0b0..Disable SW clock regardless of HWEN
51456 * 0b1..Enable SW clock gating
51457 */
51458#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_SWEN_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_SWEN_MASK)
51459#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2_MASK (0x4U)
51460#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2_SHIFT (2U)
51461/*! LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2 - reserved
51462 */
51463#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_2_2_MASK)
51464#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_STOP_MASK (0x8U)
51465#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_STOP_SHIFT (3U)
51466/*! pixel_link_slv_dc0_ingress_clk_STOP - show clock root status, 1 means clock stopped
51467 */
51468#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_STOP_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_pixel_link_slv_dc0_ingress_clk_STOP_MASK)
51469#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31_MASK (0xFFFFFFF0U)
51470#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31_SHIFT (4U)
51471/*! LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31 - reserved
51472 */
51473#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_LPCG_PIXEL_LINK_SLAVE_DC0_0_LPCG_Pixel_Link_Slave_dc0_0_reserved_4_31_MASK)
51474/*! @} */
51475
51476
51477/*!
51478 * @}
51479 */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Register_Masks */
51480
51481
51482/* IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 - Peripheral instance base addresses */
51483/** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK base address */
51484#define IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK_BASE (0x585C0000u)
51485/** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK base pointer */
51486#define IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK ((IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Type *)IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK_BASE)
51487/** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 peripheral base
51488 * addresses */
51489#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_BASE_ADDRS { IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK_BASE }
51490/** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0 peripheral base
51491 * pointers */
51492#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_BASE_PTRS { IMAGING__LPCG_PIXEL_LINK_SLV_DC0_INGRESS_CLK }
51493
51494/*!
51495 * @}
51496 */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_DC0_Peripheral_Access_Layer */
51497
51498
51499/* ----------------------------------------------------------------------------
51500 -- IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 Peripheral Access Layer
51501 ---------------------------------------------------------------------------- */
51502
51503/*!
51504 * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Peripheral_Access_Layer IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 Peripheral Access Layer
51505 * @{
51506 */
51507
51508/** IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 - Register Layout Typedef */
51509typedef struct {
51510 __IO uint32_t LPCG_PIXEL_LINK_SLAVE_DC1_0; /**< na, offset: 0x0 */
51511} IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Type;
51512
51513/* ----------------------------------------------------------------------------
51514 -- IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 Register Masks
51515 ---------------------------------------------------------------------------- */
51516
51517/*!
51518 * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Register_Masks IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 Register Masks
51519 * @{
51520 */
51521
51522/*! @name LPCG_PIXEL_LINK_SLAVE_DC1_0 - na */
51523/*! @{ */
51524#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0_MASK (0x1U)
51525#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0_SHIFT (0U)
51526/*! LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0 - reserved
51527 */
51528#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_0_0_MASK)
51529#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_SWEN_MASK (0x2U)
51530#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_SWEN_SHIFT (1U)
51531/*! pixel_link_slv_dc1_ingress_clk_SWEN - Software Enable
51532 * 0b0..Disable SW clock regardless of HWEN
51533 * 0b1..Enable SW clock gating
51534 */
51535#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_SWEN_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_SWEN_MASK)
51536#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2_MASK (0x4U)
51537#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2_SHIFT (2U)
51538/*! LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2 - reserved
51539 */
51540#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_2_2_MASK)
51541#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_STOP_MASK (0x8U)
51542#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_STOP_SHIFT (3U)
51543/*! pixel_link_slv_dc1_ingress_clk_STOP - show clock root status, 1 means clock stopped
51544 */
51545#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_STOP_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_pixel_link_slv_dc1_ingress_clk_STOP_MASK)
51546#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31_MASK (0xFFFFFFF0U)
51547#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31_SHIFT (4U)
51548/*! LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31 - reserved
51549 */
51550#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_LPCG_PIXEL_LINK_SLAVE_DC1_0_LPCG_Pixel_Link_Slave_dc1_0_reserved_4_31_MASK)
51551/*! @} */
51552
51553
51554/*!
51555 * @}
51556 */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Register_Masks */
51557
51558
51559/* IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 - Peripheral instance base addresses */
51560/** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK base address */
51561#define IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK_BASE (0x585E0000u)
51562/** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK base pointer */
51563#define IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK ((IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Type *)IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK_BASE)
51564/** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 peripheral base
51565 * addresses */
51566#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_BASE_ADDRS { IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK_BASE }
51567/** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1 peripheral base
51568 * pointers */
51569#define IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_BASE_PTRS { IMAGING__LPCG_PIXEL_LINK_SLV_DC1_INGRESS_CLK }
51570
51571/*!
51572 * @}
51573 */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_DC1_Peripheral_Access_Layer */
51574
51575
51576/* ----------------------------------------------------------------------------
51577 -- IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN Peripheral Access Layer
51578 ---------------------------------------------------------------------------- */
51579
51580/*!
51581 * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Peripheral_Access_Layer IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN Peripheral Access Layer
51582 * @{
51583 */
51584
51585/** IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN - Register Layout Typedef */
51586typedef struct {
51587 __IO uint32_t LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0; /**< na, offset: 0x0 */
51588} IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Type;
51589
51590/* ----------------------------------------------------------------------------
51591 -- IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN Register Masks
51592 ---------------------------------------------------------------------------- */
51593
51594/*!
51595 * @addtogroup IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Register_Masks IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN Register Masks
51596 * @{
51597 */
51598
51599/*! @name LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0 - na */
51600/*! @{ */
51601#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0_MASK (0x1U)
51602#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0_SHIFT (0U)
51603/*! LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0 - reserved
51604 */
51605#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_0_0_MASK)
51606#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_SWEN_MASK (0x2U)
51607#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_SWEN_SHIFT (1U)
51608/*! pixel_link_slv_hdmi_in_ingress_clk_SWEN - Software Enable
51609 * 0b0..Disable SW clock regardless of HWEN
51610 * 0b1..Enable SW clock gating
51611 */
51612#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_SWEN_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_SWEN_MASK)
51613#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2_MASK (0x4U)
51614#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2_SHIFT (2U)
51615/*! LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2 - reserved
51616 */
51617#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_2_2_MASK)
51618#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_STOP_MASK (0x8U)
51619#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_STOP_SHIFT (3U)
51620/*! pixel_link_slv_hdmi_in_ingress_clk_STOP - show clock root status, 1 means clock stopped
51621 */
51622#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_STOP_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_pixel_link_slv_hdmi_in_ingress_clk_STOP_MASK)
51623#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31_MASK (0xFFFFFFF0U)
51624#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31_SHIFT (4U)
51625/*! LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31 - reserved
51626 */
51627#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31_SHIFT)) & IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_0_LPCG_Pixel_Link_Slave_hdmi_in_0_reserved_4_31_MASK)
51628/*! @} */
51629
51630
51631/*!
51632 * @}
51633 */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Register_Masks */
51634
51635
51636/* IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN - Peripheral instance base addresses */
51637/** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK base address */
51638#define IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK_BASE (0x585A0000u)
51639/** Peripheral IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK base pointer */
51640#define IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK ((IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Type *)IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK_BASE)
51641/** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN peripheral base
51642 * addresses */
51643#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_BASE_ADDRS { IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK_BASE }
51644/** Array initializer of IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN peripheral base
51645 * pointers */
51646#define IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_BASE_PTRS { IMAGING__LPCG_PIXEL_LINK_SLV_HDMI_IN_INGRESS_CLK }
51647
51648/*!
51649 * @}
51650 */ /* end of group IMAGING_LPCG_PIXEL_LINK_SLAVE_HDMI_IN_Peripheral_Access_Layer */
51651
51652
51653/* ----------------------------------------------------------------------------
51654 -- INTMUX Peripheral Access Layer
51655 ---------------------------------------------------------------------------- */
51656
51657/*!
51658 * @addtogroup INTMUX_Peripheral_Access_Layer INTMUX Peripheral Access Layer
51659 * @{
51660 */
51661
51662/** INTMUX - Register Layout Typedef */
51663typedef struct {
51664 struct { /* offset: 0x0, array step: 0x40 */
51665 __IO uint32_t CHn_CSR; /**< Channel n Control Status Register, array offset: 0x0, array step: 0x40 */
51666 __I uint32_t CHn_VEC; /**< Channel n Vector Number Register, array offset: 0x4, array step: 0x40 */
51667 uint8_t RESERVED_0[8];
51668 __IO uint32_t CHn_IER_31_0; /**< Channel n Interrupt Enable Register, array offset: 0x10, array step: 0x40 */
51669 uint8_t RESERVED_1[12];
51670 __I uint32_t CHn_IPR_31_0; /**< Channel n Interrupt Pending Register, array offset: 0x20, array step: 0x40 */
51671 uint8_t RESERVED_2[28];
51672 } CHANNEL[8];
51673} INTMUX_Type;
51674
51675/* ----------------------------------------------------------------------------
51676 -- INTMUX Register Masks
51677 ---------------------------------------------------------------------------- */
51678
51679/*!
51680 * @addtogroup INTMUX_Register_Masks INTMUX Register Masks
51681 * @{
51682 */
51683
51684/*! @name CHn_CSR - Channel n Control Status Register */
51685/*! @{ */
51686#define INTMUX_CHn_CSR_RST_MASK (0x1U)
51687#define INTMUX_CHn_CSR_RST_SHIFT (0U)
51688/*! RST - Software Reset
51689 * 0b0..No operation.
51690 * 0b1..Perform a software reset on this channel.
51691 */
51692#define INTMUX_CHn_CSR_RST(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_RST_SHIFT)) & INTMUX_CHn_CSR_RST_MASK)
51693#define INTMUX_CHn_CSR_AND_MASK (0x2U)
51694#define INTMUX_CHn_CSR_AND_SHIFT (1U)
51695/*! AND - Logic AND
51696 * 0b0..Logic OR all enabled interrupt inputs.
51697 * 0b1..Logic AND all enabled interrupt inputs.
51698 */
51699#define INTMUX_CHn_CSR_AND(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_AND_SHIFT)) & INTMUX_CHn_CSR_AND_MASK)
51700#define INTMUX_CHn_CSR_IRQN_MASK (0x30U)
51701#define INTMUX_CHn_CSR_IRQN_SHIFT (4U)
51702/*! IRQN - Channel Input Number
51703 * 0b00..32 interrupt inputs
51704 * 0b01..Reserved
51705 * 0b10..Reserved
51706 * 0b11..Reserved
51707 */
51708#define INTMUX_CHn_CSR_IRQN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQN_SHIFT)) & INTMUX_CHn_CSR_IRQN_MASK)
51709#define INTMUX_CHn_CSR_CHIN_MASK (0xF00U)
51710#define INTMUX_CHn_CSR_CHIN_SHIFT (8U)
51711/*! CHIN - Channel Instance Number
51712 */
51713#define INTMUX_CHn_CSR_CHIN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_CHIN_SHIFT)) & INTMUX_CHn_CSR_CHIN_MASK)
51714#define INTMUX_CHn_CSR_IRQP_MASK (0x80000000U)
51715#define INTMUX_CHn_CSR_IRQP_SHIFT (31U)
51716/*! IRQP - Channel Interrupt Request Pending
51717 * 0b0..No interrupt is pending.
51718 * 0b1..The interrupt output of this channel is pending.
51719 */
51720#define INTMUX_CHn_CSR_IRQP(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQP_SHIFT)) & INTMUX_CHn_CSR_IRQP_MASK)
51721/*! @} */
51722
51723/* The count of INTMUX_CHn_CSR */
51724#define INTMUX_CHn_CSR_COUNT (8U)
51725
51726/*! @name CHn_VEC - Channel n Vector Number Register */
51727/*! @{ */
51728#define INTMUX_CHn_VEC_VECN_MASK (0x3FFCU)
51729#define INTMUX_CHn_VEC_VECN_SHIFT (2U)
51730/*! VECN - Vector Number
51731 */
51732#define INTMUX_CHn_VEC_VECN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_VEC_VECN_SHIFT)) & INTMUX_CHn_VEC_VECN_MASK)
51733/*! @} */
51734
51735/* The count of INTMUX_CHn_VEC */
51736#define INTMUX_CHn_VEC_COUNT (8U)
51737
51738/*! @name CHn_IER_31_0 - Channel n Interrupt Enable Register */
51739/*! @{ */
51740#define INTMUX_CHn_IER_31_0_INTE_MASK (0xFFFFFFFFU)
51741#define INTMUX_CHn_IER_31_0_INTE_SHIFT (0U)
51742/*! INTE - Interrupt Enable
51743 */
51744#define INTMUX_CHn_IER_31_0_INTE(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IER_31_0_INTE_SHIFT)) & INTMUX_CHn_IER_31_0_INTE_MASK)
51745/*! @} */
51746
51747/* The count of INTMUX_CHn_IER_31_0 */
51748#define INTMUX_CHn_IER_31_0_COUNT (8U)
51749
51750/*! @name CHn_IPR_31_0 - Channel n Interrupt Pending Register */
51751/*! @{ */
51752#define INTMUX_CHn_IPR_31_0_INTP_MASK (0xFFFFFFFFU)
51753#define INTMUX_CHn_IPR_31_0_INTP_SHIFT (0U)
51754/*! INTP - Interrupt Pending
51755 */
51756#define INTMUX_CHn_IPR_31_0_INTP(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IPR_31_0_INTP_SHIFT)) & INTMUX_CHn_IPR_31_0_INTP_MASK)
51757/*! @} */
51758
51759/* The count of INTMUX_CHn_IPR_31_0 */
51760#define INTMUX_CHn_IPR_31_0_COUNT (8U)
51761
51762
51763/*!
51764 * @}
51765 */ /* end of group INTMUX_Register_Masks */
51766
51767
51768/* INTMUX - Peripheral instance base addresses */
51769/** Peripheral CM4__INTMUX base address */
51770#define CM4__INTMUX_BASE (0x41400000u)
51771/** Peripheral CM4__INTMUX base pointer */
51772#define CM4__INTMUX ((INTMUX_Type *)CM4__INTMUX_BASE)
51773/** Peripheral SCU__INTMUX base address */
51774#define SCU__INTMUX_BASE (0x33400000u)
51775/** Peripheral SCU__INTMUX base pointer */
51776#define SCU__INTMUX ((INTMUX_Type *)SCU__INTMUX_BASE)
51777/** Array initializer of INTMUX peripheral base addresses */
51778#define INTMUX_BASE_ADDRS { CM4__INTMUX_BASE, SCU__INTMUX_BASE }
51779/** Array initializer of INTMUX peripheral base pointers */
51780#define INTMUX_BASE_PTRS { CM4__INTMUX, SCU__INTMUX }
51781
51782/*!
51783 * @}
51784 */ /* end of group INTMUX_Peripheral_Access_Layer */
51785
51786
51787/* ----------------------------------------------------------------------------
51788 -- IOMUXD Peripheral Access Layer
51789 ---------------------------------------------------------------------------- */
51790
51791/*!
51792 * @addtogroup IOMUXD_Peripheral_Access_Layer IOMUXD Peripheral Access Layer
51793 * @{
51794 */
51795
51796/** IOMUXD - Register Layout Typedef */
51797typedef struct {
51798 __IO uint32_t PCIE_CTRL0_PERST_B; /**< PCIE_CTRL0_PERST_B, offset: 0x0 */
51799 uint8_t RESERVED_0[60];
51800 __IO uint32_t PCIE_CTRL0_CLKREQ_B; /**< PCIE_CTRL0_CLKREQ_B, offset: 0x40 */
51801 uint8_t RESERVED_1[60];
51802 __IO uint32_t PCIE_CTRL0_WAKE_B; /**< PCIE_CTRL0_WAKE_B, offset: 0x80 */
51803 uint8_t RESERVED_2[60];
51804 __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP, offset: 0xC0 */
51805 uint8_t RESERVED_3[60];
51806 __IO uint32_t USB_SS3_TC0; /**< USB_SS3_TC0, offset: 0x100 */
51807 uint8_t RESERVED_4[60];
51808 __IO uint32_t USB_SS3_TC1; /**< USB_SS3_TC1, offset: 0x140 */
51809 uint8_t RESERVED_5[60];
51810 __IO uint32_t USB_SS3_TC2; /**< USB_SS3_TC2, offset: 0x180 */
51811 uint8_t RESERVED_6[60];
51812 __IO uint32_t USB_SS3_TC3; /**< USB_SS3_TC3, offset: 0x1C0 */
51813 uint8_t RESERVED_7[60];
51814 __IO uint32_t IOMUXD_COMP_CTL_GPIO_3V3_USB3IO; /**< IOMUXD_COMP_CTL_GPIO_3V3_USB3IO, offset: 0x200 */
51815 uint8_t RESERVED_8[508];
51816 __I uint32_t IOMUXD_GROUP_0_0; /**< na, offset: 0x400 */
51817 uint8_t RESERVED_9[130044];
51818 __IO uint32_t EMMC0_CLK; /**< EMMC0_CLK, offset: 0x20000 */
51819 uint8_t RESERVED_10[60];
51820 __IO uint32_t EMMC0_CMD; /**< EMMC0_CMD, offset: 0x20040 */
51821 uint8_t RESERVED_11[60];
51822 __IO uint32_t EMMC0_DATA0; /**< EMMC0_DATA0, offset: 0x20080 */
51823 uint8_t RESERVED_12[60];
51824 __IO uint32_t EMMC0_DATA1; /**< EMMC0_DATA1, offset: 0x200C0 */
51825 uint8_t RESERVED_13[60];
51826 __IO uint32_t EMMC0_DATA2; /**< EMMC0_DATA2, offset: 0x20100 */
51827 uint8_t RESERVED_14[60];
51828 __IO uint32_t EMMC0_DATA3; /**< EMMC0_DATA3, offset: 0x20140 */
51829 uint8_t RESERVED_15[60];
51830 __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0, offset: 0x20180 */
51831 uint8_t RESERVED_16[60];
51832 __IO uint32_t EMMC0_DATA4; /**< EMMC0_DATA4, offset: 0x201C0 */
51833 uint8_t RESERVED_17[60];
51834 __IO uint32_t EMMC0_DATA5; /**< EMMC0_DATA5, offset: 0x20200 */
51835 uint8_t RESERVED_18[60];
51836 __IO uint32_t EMMC0_DATA6; /**< EMMC0_DATA6, offset: 0x20240 */
51837 uint8_t RESERVED_19[60];
51838 __IO uint32_t EMMC0_DATA7; /**< EMMC0_DATA7, offset: 0x20280 */
51839 uint8_t RESERVED_20[60];
51840 __IO uint32_t EMMC0_STROBE; /**< EMMC0_STROBE, offset: 0x202C0 */
51841 uint8_t RESERVED_21[60];
51842 __IO uint32_t EMMC0_RESET_B; /**< EMMC0_RESET_B, offset: 0x20300 */
51843 uint8_t RESERVED_22[60];
51844 __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1, offset: 0x20340 */
51845 uint8_t RESERVED_23[60];
51846 __IO uint32_t USDHC1_RESET_B; /**< USDHC1_RESET_B, offset: 0x20380 */
51847 uint8_t RESERVED_24[124];
51848 __I uint32_t IOMUXD_GROUP_1_0; /**< na, offset: 0x20400 */
51849 uint8_t RESERVED_25[3068];
51850 __IO uint32_t USDHC1_VSELECT; /**< USDHC1_VSELECT, offset: 0x21000 */
51851 uint8_t RESERVED_26[60];
51852 __IO uint32_t IOMUXD_CTL_NAND_RE_P_N; /**< IOMUXD_CTL_NAND_RE_P_N, offset: 0x21040 */
51853 uint8_t RESERVED_27[60];
51854 __IO uint32_t USDHC1_WP; /**< USDHC1_WP, offset: 0x21080 */
51855 uint8_t RESERVED_28[60];
51856 __IO uint32_t USDHC1_CD_B; /**< USDHC1_CD_B, offset: 0x210C0 */
51857 uint8_t RESERVED_29[60];
51858 __IO uint32_t IOMUXD_CTL_NAND_DQS_P_N; /**< IOMUXD_CTL_NAND_DQS_P_N, offset: 0x21100 */
51859 uint8_t RESERVED_30[60];
51860 __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP, offset: 0x21140 */
51861 uint8_t RESERVED_31[60];
51862 __IO uint32_t USDHC1_CLK; /**< USDHC1_CLK, offset: 0x21180 */
51863 uint8_t RESERVED_32[60];
51864 __IO uint32_t USDHC1_CMD; /**< USDHC1_CMD, offset: 0x211C0 */
51865 uint8_t RESERVED_33[60];
51866 __IO uint32_t USDHC1_DATA0; /**< USDHC1_DATA0, offset: 0x21200 */
51867 uint8_t RESERVED_34[60];
51868 __IO uint32_t USDHC1_DATA1; /**< USDHC1_DATA1, offset: 0x21240 */
51869 uint8_t RESERVED_35[60];
51870 __IO uint32_t USDHC1_DATA2; /**< USDHC1_DATA2, offset: 0x21280 */
51871 uint8_t RESERVED_36[60];
51872 __IO uint32_t USDHC1_DATA3; /**< USDHC1_DATA3, offset: 0x212C0 */
51873 uint8_t RESERVED_37[60];
51874 __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3, offset: 0x21300 */
51875 uint8_t RESERVED_38[60];
51876 __IO uint32_t ENET0_RGMII_TXC; /**< ENET0_RGMII_TXC, offset: 0x21340 */
51877 uint8_t RESERVED_39[60];
51878 __IO uint32_t ENET0_RGMII_TX_CTL; /**< ENET0_RGMII_TX_CTL, offset: 0x21380 */
51879 uint8_t RESERVED_40[124];
51880 __I uint32_t IOMUXD_GROUP_1_1; /**< na, offset: 0x21400 */
51881 uint8_t RESERVED_41[3068];
51882 __IO uint32_t ENET0_RGMII_TXD0; /**< ENET0_RGMII_TXD0, offset: 0x22000 */
51883 uint8_t RESERVED_42[60];
51884 __IO uint32_t ENET0_RGMII_TXD1; /**< ENET0_RGMII_TXD1, offset: 0x22040 */
51885 uint8_t RESERVED_43[60];
51886 __IO uint32_t ENET0_RGMII_TXD2; /**< ENET0_RGMII_TXD2, offset: 0x22080 */
51887 uint8_t RESERVED_44[60];
51888 __IO uint32_t ENET0_RGMII_TXD3; /**< ENET0_RGMII_TXD3, offset: 0x220C0 */
51889 uint8_t RESERVED_45[60];
51890 __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0, offset: 0x22100 */
51891 uint8_t RESERVED_46[60];
51892 __IO uint32_t ENET0_RGMII_RXC; /**< ENET0_RGMII_RXC, offset: 0x22140 */
51893 uint8_t RESERVED_47[60];
51894 __IO uint32_t ENET0_RGMII_RX_CTL; /**< ENET0_RGMII_RX_CTL, offset: 0x22180 */
51895 uint8_t RESERVED_48[60];
51896 __IO uint32_t ENET0_RGMII_RXD0; /**< ENET0_RGMII_RXD0, offset: 0x221C0 */
51897 uint8_t RESERVED_49[60];
51898 __IO uint32_t ENET0_RGMII_RXD1; /**< ENET0_RGMII_RXD1, offset: 0x22200 */
51899 uint8_t RESERVED_50[60];
51900 __IO uint32_t ENET0_RGMII_RXD2; /**< ENET0_RGMII_RXD2, offset: 0x22240 */
51901 uint8_t RESERVED_51[60];
51902 __IO uint32_t ENET0_RGMII_RXD3; /**< ENET0_RGMII_RXD3, offset: 0x22280 */
51903 uint8_t RESERVED_52[60];
51904 __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1, offset: 0x222C0 */
51905 uint8_t RESERVED_53[60];
51906 __IO uint32_t ENET0_REFCLK_125M_25M; /**< ENET0_REFCLK_125M_25M, offset: 0x22300 */
51907 uint8_t RESERVED_54[252];
51908 __I uint32_t IOMUXD_GROUP_1_2; /**< na, offset: 0x22400 */
51909 uint8_t RESERVED_55[3068];
51910 __IO uint32_t ENET0_MDIO; /**< ENET0_MDIO, offset: 0x23000 */
51911 uint8_t RESERVED_56[60];
51912 __IO uint32_t ENET0_MDC; /**< ENET0_MDC, offset: 0x23040 */
51913 uint8_t RESERVED_57[60];
51914 __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT, offset: 0x23080 */
51915 uint8_t RESERVED_58[60];
51916 __IO uint32_t ESAI0_FSR; /**< ESAI0_FSR, offset: 0x230C0 */
51917 uint8_t RESERVED_59[60];
51918 __IO uint32_t ESAI0_FST; /**< ESAI0_FST, offset: 0x23100 */
51919 uint8_t RESERVED_60[60];
51920 __IO uint32_t ESAI0_SCKR; /**< ESAI0_SCKR, offset: 0x23140 */
51921 uint8_t RESERVED_61[60];
51922 __IO uint32_t ESAI0_SCKT; /**< ESAI0_SCKT, offset: 0x23180 */
51923 uint8_t RESERVED_62[60];
51924 __IO uint32_t ESAI0_TX0; /**< ESAI0_TX0, offset: 0x231C0 */
51925 uint8_t RESERVED_63[60];
51926 __IO uint32_t ESAI0_TX1; /**< ESAI0_TX1, offset: 0x23200 */
51927 uint8_t RESERVED_64[60];
51928 __IO uint32_t ESAI0_TX2_RX3; /**< ESAI0_TX2_RX3, offset: 0x23240 */
51929 uint8_t RESERVED_65[60];
51930 __IO uint32_t ESAI0_TX3_RX2; /**< ESAI0_TX3_RX2, offset: 0x23280 */
51931 uint8_t RESERVED_66[60];
51932 __IO uint32_t ESAI0_TX4_RX1; /**< ESAI0_TX4_RX1, offset: 0x232C0 */
51933 uint8_t RESERVED_67[60];
51934 __IO uint32_t ESAI0_TX5_RX0; /**< ESAI0_TX5_RX0, offset: 0x23300 */
51935 uint8_t RESERVED_68[60];
51936 __IO uint32_t SPDIF0_RX; /**< SPDIF0_RX, offset: 0x23340 */
51937 uint8_t RESERVED_69[60];
51938 __IO uint32_t SPDIF0_TX; /**< SPDIF0_TX, offset: 0x23380 */
51939 uint8_t RESERVED_70[124];
51940 __I uint32_t IOMUXD_GROUP_1_3; /**< na, offset: 0x23400 */
51941 uint8_t RESERVED_71[3068];
51942 __IO uint32_t SPDIF0_EXT_CLK; /**< SPDIF0_EXT_CLK, offset: 0x24000 */
51943 uint8_t RESERVED_72[60];
51944 __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB, offset: 0x24040 */
51945 uint8_t RESERVED_73[60];
51946 __IO uint32_t SPI3_SCK; /**< SPI3_SCK, offset: 0x24080 */
51947 uint8_t RESERVED_74[60];
51948 __IO uint32_t SPI3_SDO; /**< SPI3_SDO, offset: 0x240C0 */
51949 uint8_t RESERVED_75[60];
51950 __IO uint32_t SPI3_SDI; /**< SPI3_SDI, offset: 0x24100 */
51951 uint8_t RESERVED_76[60];
51952 __IO uint32_t SPI3_CS0; /**< SPI3_CS0, offset: 0x24140 */
51953 uint8_t RESERVED_77[60];
51954 __IO uint32_t SPI3_CS1; /**< SPI3_CS1, offset: 0x24180 */
51955 uint8_t RESERVED_78[60];
51956 __IO uint32_t MCLK_IN1; /**< MCLK_IN1, offset: 0x241C0 */
51957 uint8_t RESERVED_79[60];
51958 __IO uint32_t MCLK_IN0; /**< MCLK_IN0, offset: 0x24200 */
51959 uint8_t RESERVED_80[60];
51960 __IO uint32_t MCLK_OUT0; /**< MCLK_OUT0, offset: 0x24240 */
51961 uint8_t RESERVED_81[60];
51962 __IO uint32_t UART1_TX; /**< UART1_TX, offset: 0x24280 */
51963 uint8_t RESERVED_82[60];
51964 __IO uint32_t UART1_RX; /**< UART1_RX, offset: 0x242C0 */
51965 uint8_t RESERVED_83[60];
51966 __IO uint32_t UART1_RTS_B; /**< UART1_RTS_B, offset: 0x24300 */
51967 uint8_t RESERVED_84[60];
51968 __IO uint32_t UART1_CTS_B; /**< UART1_CTS_B, offset: 0x24340 */
51969 uint8_t RESERVED_85[60];
51970 __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK, offset: 0x24380 */
51971 uint8_t RESERVED_86[124];
51972 __I uint32_t IOMUXD_GROUP_1_4; /**< na, offset: 0x24400 */
51973 uint8_t RESERVED_87[113660];
51974 __IO uint32_t SAI0_TXD; /**< SAI0_TXD, offset: 0x40000 */
51975 uint8_t RESERVED_88[60];
51976 __IO uint32_t SAI0_TXC; /**< SAI0_TXC, offset: 0x40040 */
51977 uint8_t RESERVED_89[60];
51978 __IO uint32_t SAI0_RXD; /**< SAI0_RXD, offset: 0x40080 */
51979 uint8_t RESERVED_90[60];
51980 __IO uint32_t SAI0_TXFS; /**< SAI0_TXFS, offset: 0x400C0 */
51981 uint8_t RESERVED_91[60];
51982 __IO uint32_t SAI1_RXD; /**< SAI1_RXD, offset: 0x40100 */
51983 uint8_t RESERVED_92[60];
51984 __IO uint32_t SAI1_RXC; /**< SAI1_RXC, offset: 0x40140 */
51985 uint8_t RESERVED_93[60];
51986 __IO uint32_t SAI1_RXFS; /**< SAI1_RXFS, offset: 0x40180 */
51987 uint8_t RESERVED_94[60];
51988 __IO uint32_t SPI2_CS0; /**< SPI2_CS0, offset: 0x401C0 */
51989 uint8_t RESERVED_95[60];
51990 __IO uint32_t SPI2_SDO; /**< SPI2_SDO, offset: 0x40200 */
51991 uint8_t RESERVED_96[60];
51992 __IO uint32_t SPI2_SDI; /**< SPI2_SDI, offset: 0x40240 */
51993 uint8_t RESERVED_97[60];
51994 __IO uint32_t SPI2_SCK; /**< SPI2_SCK, offset: 0x40280 */
51995 uint8_t RESERVED_98[60];
51996 __IO uint32_t SPI0_SCK; /**< SPI0_SCK, offset: 0x402C0 */
51997 uint8_t RESERVED_99[60];
51998 __IO uint32_t SPI0_SDI; /**< SPI0_SDI, offset: 0x40300 */
51999 uint8_t RESERVED_100[60];
52000 __IO uint32_t SPI0_SDO; /**< SPI0_SDO, offset: 0x40340 */
52001 uint8_t RESERVED_101[60];
52002 __IO uint32_t SPI0_CS1; /**< SPI0_CS1, offset: 0x40380 */
52003 uint8_t RESERVED_102[124];
52004 __I uint32_t IOMUXD_GROUP_2_0; /**< na, offset: 0x40400 */
52005 uint8_t RESERVED_103[3068];
52006 __IO uint32_t SPI0_CS0; /**< SPI0_CS0, offset: 0x41000 */
52007 uint8_t RESERVED_104[60];
52008 __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT, offset: 0x41040 */
52009 uint8_t RESERVED_105[60];
52010 __IO uint32_t ADC_IN1; /**< ADC_IN1, offset: 0x41080 */
52011 uint8_t RESERVED_106[60];
52012 __IO uint32_t ADC_IN0; /**< ADC_IN0, offset: 0x410C0 */
52013 uint8_t RESERVED_107[60];
52014 __IO uint32_t ADC_IN3; /**< ADC_IN3, offset: 0x41100 */
52015 uint8_t RESERVED_108[60];
52016 __IO uint32_t ADC_IN2; /**< ADC_IN2, offset: 0x41140 */
52017 uint8_t RESERVED_109[60];
52018 __IO uint32_t ADC_IN5; /**< ADC_IN5, offset: 0x41180 */
52019 uint8_t RESERVED_110[60];
52020 __IO uint32_t ADC_IN4; /**< ADC_IN4, offset: 0x411C0 */
52021 uint8_t RESERVED_111[60];
52022 __IO uint32_t FLEXCAN0_RX; /**< FLEXCAN0_RX, offset: 0x41200 */
52023 uint8_t RESERVED_112[60];
52024 __IO uint32_t FLEXCAN0_TX; /**< FLEXCAN0_TX, offset: 0x41240 */
52025 uint8_t RESERVED_113[60];
52026 __IO uint32_t FLEXCAN1_RX; /**< FLEXCAN1_RX, offset: 0x41280 */
52027 uint8_t RESERVED_114[60];
52028 __IO uint32_t FLEXCAN1_TX; /**< FLEXCAN1_TX, offset: 0x412C0 */
52029 uint8_t RESERVED_115[60];
52030 __IO uint32_t FLEXCAN2_RX; /**< FLEXCAN2_RX, offset: 0x41300 */
52031 uint8_t RESERVED_116[60];
52032 __IO uint32_t FLEXCAN2_TX; /**< FLEXCAN2_TX, offset: 0x41340 */
52033 uint8_t RESERVED_117[60];
52034 __IO uint32_t UART0_RX; /**< UART0_RX, offset: 0x41380 */
52035 uint8_t RESERVED_118[124];
52036 __I uint32_t IOMUXD_GROUP_2_1; /**< na, offset: 0x41400 */
52037 uint8_t RESERVED_119[3068];
52038 __IO uint32_t UART0_TX; /**< UART0_TX, offset: 0x42000 */
52039 uint8_t RESERVED_120[60];
52040 __IO uint32_t UART2_TX; /**< UART2_TX, offset: 0x42040 */
52041 uint8_t RESERVED_121[60];
52042 __IO uint32_t UART2_RX; /**< UART2_RX, offset: 0x42080 */
52043 uint8_t RESERVED_122[60];
52044 __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH, offset: 0x420C0 */
52045 uint8_t RESERVED_123[60];
52046 __IO uint32_t MIPI_DSI0_I2C0_SCL; /**< MIPI_DSI0_I2C0_SCL, offset: 0x42100 */
52047 uint8_t RESERVED_124[60];
52048 __IO uint32_t MIPI_DSI0_I2C0_SDA; /**< MIPI_DSI0_I2C0_SDA, offset: 0x42140 */
52049 uint8_t RESERVED_125[60];
52050 __IO uint32_t MIPI_DSI0_GPIO0_00; /**< MIPI_DSI0_GPIO0_00, offset: 0x42180 */
52051 uint8_t RESERVED_126[60];
52052 __IO uint32_t MIPI_DSI0_GPIO0_01; /**< MIPI_DSI0_GPIO0_01, offset: 0x421C0 */
52053 uint8_t RESERVED_127[60];
52054 __IO uint32_t MIPI_DSI1_I2C0_SCL; /**< MIPI_DSI1_I2C0_SCL, offset: 0x42200 */
52055 uint8_t RESERVED_128[60];
52056 __IO uint32_t MIPI_DSI1_I2C0_SDA; /**< MIPI_DSI1_I2C0_SDA, offset: 0x42240 */
52057 uint8_t RESERVED_129[60];
52058 __IO uint32_t MIPI_DSI1_GPIO0_00; /**< MIPI_DSI1_GPIO0_00, offset: 0x42280 */
52059 uint8_t RESERVED_130[60];
52060 __IO uint32_t MIPI_DSI1_GPIO0_01; /**< MIPI_DSI1_GPIO0_01, offset: 0x422C0 */
52061 uint8_t RESERVED_131[60];
52062 __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO, offset: 0x42300 */
52063 uint8_t RESERVED_132[60];
52064 __IO uint32_t SCU_WDOG_OUT; /**< SCU_WDOG_OUT, offset: 0x42340 */
52065 uint8_t RESERVED_133[60];
52066 __IO uint32_t PMIC_I2C_SCL; /**< PMIC_I2C_SCL, offset: 0x42380 */
52067 uint8_t RESERVED_134[124];
52068 __I uint32_t IOMUXD_GROUP_2_2; /**< na, offset: 0x42400 */
52069 uint8_t RESERVED_135[3068];
52070 __IO uint32_t PMIC_I2C_SDA; /**< PMIC_I2C_SDA, offset: 0x43000 */
52071 uint8_t RESERVED_136[60];
52072 __IO uint32_t PMIC_INT_B; /**< PMIC_INT_B, offset: 0x43040 */
52073 uint8_t RESERVED_137[60];
52074 __IO uint32_t SCU_GPIO0_00; /**< SCU_GPIO0_00, offset: 0x43080 */
52075 uint8_t RESERVED_138[60];
52076 __IO uint32_t SCU_GPIO0_01; /**< SCU_GPIO0_01, offset: 0x430C0 */
52077 uint8_t RESERVED_139[60];
52078 __IO uint32_t SCU_PMIC_STANDBY; /**< SCU_PMIC_STANDBY, offset: 0x43100 */
52079 uint8_t RESERVED_140[60];
52080 __IO uint32_t SCU_BOOT_MODE0; /**< SCU_BOOT_MODE0, offset: 0x43140 */
52081 uint8_t RESERVED_141[60];
52082 __IO uint32_t SCU_BOOT_MODE1; /**< SCU_BOOT_MODE1, offset: 0x43180 */
52083 uint8_t RESERVED_142[60];
52084 __IO uint32_t SCU_BOOT_MODE2; /**< SCU_BOOT_MODE2, offset: 0x431C0 */
52085 uint8_t RESERVED_143[60];
52086 __IO uint32_t SCU_BOOT_MODE3; /**< SCU_BOOT_MODE3, offset: 0x43200 */
52087 uint8_t RESERVED_144[60];
52088 __IO uint32_t CSI_DIG_D00; /**< CSI_DIG_D00, offset: 0x43240 */
52089 uint8_t RESERVED_145[60];
52090 __IO uint32_t CSI_DIG_D01; /**< CSI_DIG_D01, offset: 0x43280 */
52091 uint8_t RESERVED_146[60];
52092 __IO uint32_t CSI_DIG_D02; /**< CSI_DIG_D02, offset: 0x432C0 */
52093 uint8_t RESERVED_147[60];
52094 __IO uint32_t CSI_DIG_D03; /**< CSI_DIG_D03, offset: 0x43300 */
52095 uint8_t RESERVED_148[60];
52096 __IO uint32_t CSI_DIG_D04; /**< CSI_DIG_D04, offset: 0x43340 */
52097 uint8_t RESERVED_149[60];
52098 __IO uint32_t CSI_DIG_D05; /**< CSI_DIG_D05, offset: 0x43380 */
52099 uint8_t RESERVED_150[124];
52100 __I uint32_t IOMUXD_GROUP_2_3; /**< na, offset: 0x43400 */
52101 uint8_t RESERVED_151[3068];
52102 __IO uint32_t CSI_DIG_D06; /**< CSI_DIG_D06, offset: 0x44000 */
52103 uint8_t RESERVED_152[60];
52104 __IO uint32_t CSI_DIG_D07; /**< CSI_DIG_D07, offset: 0x44040 */
52105 uint8_t RESERVED_153[60];
52106 __IO uint32_t CSI_DIG_HSYNC; /**< CSI_DIG_HSYNC, offset: 0x44080 */
52107 uint8_t RESERVED_154[60];
52108 __IO uint32_t CSI_DIG_VSYNC; /**< CSI_DIG_VSYNC, offset: 0x440C0 */
52109 uint8_t RESERVED_155[60];
52110 __IO uint32_t CSI_PCLK; /**< CSI_PCLK, offset: 0x44100 */
52111 uint8_t RESERVED_156[60];
52112 __IO uint32_t CSI_MCLK; /**< CSI_MCLK, offset: 0x44140 */
52113 uint8_t RESERVED_157[60];
52114 __IO uint32_t CSI_EN; /**< CSI_EN, offset: 0x44180 */
52115 uint8_t RESERVED_158[60];
52116 __IO uint32_t CSI_RESET; /**< CSI_RESET, offset: 0x441C0 */
52117 uint8_t RESERVED_159[60];
52118 __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD, offset: 0x44200 */
52119 uint8_t RESERVED_160[60];
52120 __IO uint32_t MIPI_CSI0_MCLK_OUT; /**< MIPI_CSI0_MCLK_OUT, offset: 0x44240 */
52121 uint8_t RESERVED_161[60];
52122 __IO uint32_t MIPI_CSI0_I2C0_SCL; /**< MIPI_CSI0_I2C0_SCL, offset: 0x44280 */
52123 uint8_t RESERVED_162[60];
52124 __IO uint32_t MIPI_CSI0_I2C0_SDA; /**< MIPI_CSI0_I2C0_SDA, offset: 0x442C0 */
52125 uint8_t RESERVED_163[60];
52126 __IO uint32_t MIPI_CSI0_GPIO0_01; /**< MIPI_CSI0_GPIO0_01, offset: 0x44300 */
52127 uint8_t RESERVED_164[60];
52128 __IO uint32_t MIPI_CSI0_GPIO0_00; /**< MIPI_CSI0_GPIO0_00, offset: 0x44340 */
52129 uint8_t RESERVED_165[188];
52130 __I uint32_t IOMUXD_GROUP_2_4; /**< na, offset: 0x44400 */
52131 uint8_t RESERVED_166[113660];
52132 __IO uint32_t QSPI0A_DATA0; /**< QSPI0A_DATA0, offset: 0x60000 */
52133 uint8_t RESERVED_167[60];
52134 __IO uint32_t QSPI0A_DATA1; /**< QSPI0A_DATA1, offset: 0x60040 */
52135 uint8_t RESERVED_168[60];
52136 __IO uint32_t QSPI0A_DATA2; /**< QSPI0A_DATA2, offset: 0x60080 */
52137 uint8_t RESERVED_169[60];
52138 __IO uint32_t QSPI0A_DATA3; /**< QSPI0A_DATA3, offset: 0x600C0 */
52139 uint8_t RESERVED_170[60];
52140 __IO uint32_t QSPI0A_DQS; /**< QSPI0A_DQS, offset: 0x60100 */
52141 uint8_t RESERVED_171[60];
52142 __IO uint32_t QSPI0A_SS0_B; /**< QSPI0A_SS0_B, offset: 0x60140 */
52143 uint8_t RESERVED_172[60];
52144 __IO uint32_t QSPI0A_SS1_B; /**< QSPI0A_SS1_B, offset: 0x60180 */
52145 uint8_t RESERVED_173[60];
52146 __IO uint32_t QSPI0A_SCLK; /**< QSPI0A_SCLK, offset: 0x601C0 */
52147 uint8_t RESERVED_174[60];
52148 __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A, offset: 0x60200 */
52149 uint8_t RESERVED_175[60];
52150 __IO uint32_t QSPI0B_SCLK; /**< QSPI0B_SCLK, offset: 0x60240 */
52151 uint8_t RESERVED_176[60];
52152 __IO uint32_t QSPI0B_DATA0; /**< QSPI0B_DATA0, offset: 0x60280 */
52153 uint8_t RESERVED_177[60];
52154 __IO uint32_t QSPI0B_DATA1; /**< QSPI0B_DATA1, offset: 0x602C0 */
52155 uint8_t RESERVED_178[60];
52156 __IO uint32_t QSPI0B_DATA2; /**< QSPI0B_DATA2, offset: 0x60300 */
52157 uint8_t RESERVED_179[60];
52158 __IO uint32_t QSPI0B_DATA3; /**< QSPI0B_DATA3, offset: 0x60340 */
52159 uint8_t RESERVED_180[60];
52160 __IO uint32_t QSPI0B_DQS; /**< QSPI0B_DQS, offset: 0x60380 */
52161 uint8_t RESERVED_181[124];
52162 __I uint32_t IOMUXD_GROUP_3_0; /**< na, offset: 0x60400 */
52163 uint8_t RESERVED_182[3068];
52164 __IO uint32_t QSPI0B_SS0_B; /**< QSPI0B_SS0_B, offset: 0x61000 */
52165 uint8_t RESERVED_183[60];
52166 __IO uint32_t QSPI0B_SS1_B; /**< QSPI0B_SS1_B, offset: 0x61040 */
52167 uint8_t RESERVED_184[60];
52168 __IO uint32_t IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B; /**< IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B, offset: 0x61080 */
52169 uint8_t RESERVED_185[892];
52170 __I uint32_t IOMUXD_GROUP_3_1; /**< na, offset: 0x61400 */
52171} IOMUXD_Type;
52172
52173/* ----------------------------------------------------------------------------
52174 -- IOMUXD Register Masks
52175 ---------------------------------------------------------------------------- */
52176
52177/*!
52178 * @addtogroup IOMUXD_Register_Masks IOMUXD Register Masks
52179 * @{
52180 */
52181
52182/*! @name PCIE_CTRL0_PERST_B - PCIE_CTRL0_PERST_B */
52183/*! @{ */
52184#define IOMUXD_PCIE_CTRL0_PERST_B_PDRV_MASK (0x1U)
52185#define IOMUXD_PCIE_CTRL0_PERST_B_PDRV_SHIFT (0U)
52186/*! PDRV - Drive
52187 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
52188 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
52189 */
52190#define IOMUXD_PCIE_CTRL0_PERST_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_PDRV_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_PDRV_MASK)
52191#define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_1_4_MASK (0x1EU)
52192#define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_1_4_SHIFT (1U)
52193/*! PCIE_CTRL0_PERST_B_reserved_1_4 - reserved
52194 */
52195#define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_1_4_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_1_4_MASK)
52196#define IOMUXD_PCIE_CTRL0_PERST_B_PULL_MASK (0x60U)
52197#define IOMUXD_PCIE_CTRL0_PERST_B_PULL_SHIFT (5U)
52198/*! PULL - Pull Down Pull Up
52199 * 0b10..pull down
52200 * 0b01..pull up
52201 * 0b00..Prohibited
52202 * 0b11..pull disabled
52203 */
52204#define IOMUXD_PCIE_CTRL0_PERST_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_PULL_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_PULL_MASK)
52205#define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_7_18_MASK (0x7FF80U)
52206#define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_7_18_SHIFT (7U)
52207/*! PCIE_CTRL0_PERST_B_reserved_7_18 - reserved
52208 */
52209#define IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_7_18_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_PCIE_CTRL0_PERST_B_reserved_7_18_MASK)
52210#define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_CTRL_MASK (0x380000U)
52211#define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_CTRL_SHIFT (19U)
52212/*! WAKEUP_CTRL - wakeup control
52213 * 0b000..OFF
52214 * 0b001..RESAMPLE
52215 * 0b100..LOW
52216 * 0b111..HIGH
52217 * 0b110..RISE
52218 * 0b101..FALL
52219 */
52220#define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_CTRL_MASK)
52221#define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_MASK_MASK (0x400000U)
52222#define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_MASK_SHIFT (22U)
52223/*! WAKEUP_MASK - wakeup mask
52224 */
52225#define IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_MASK_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_WAKEUP_MASK_MASK)
52226#define IOMUXD_PCIE_CTRL0_PERST_B_lp_config_MASK (0x1800000U)
52227#define IOMUXD_PCIE_CTRL0_PERST_B_lp_config_SHIFT (23U)
52228/*! lp_config - lower power configuration
52229 * 0b01..EARLY_ISO
52230 * 0b10..LATE_ISO
52231 * 0b11..LATCH
52232 * 0b00..PASS
52233 */
52234#define IOMUXD_PCIE_CTRL0_PERST_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_lp_config_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_lp_config_MASK)
52235#define IOMUXD_PCIE_CTRL0_PERST_B_sw_config_MASK (0x6000000U)
52236#define IOMUXD_PCIE_CTRL0_PERST_B_sw_config_SHIFT (25U)
52237/*! sw_config - output and input configuration
52238 * 0b01..OPEN_DRAIN
52239 * 0b10..OPEN_DRAIN_INPUT
52240 * 0b11..INOUT
52241 * 0b00..DEFAULT
52242 */
52243#define IOMUXD_PCIE_CTRL0_PERST_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_sw_config_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_sw_config_MASK)
52244#define IOMUXD_PCIE_CTRL0_PERST_B_mux_mode_MASK (0x38000000U)
52245#define IOMUXD_PCIE_CTRL0_PERST_B_mux_mode_SHIFT (27U)
52246/*! mux_mode - mux_mode
52247 * 0b000..HSIO.PCIE0.PERST_B
52248 * 0b100..LSIO.GPIO4.IO00
52249 */
52250#define IOMUXD_PCIE_CTRL0_PERST_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_mux_mode_MASK)
52251#define IOMUXD_PCIE_CTRL0_PERST_B_update_pad_ctl_MASK (0x40000000U)
52252#define IOMUXD_PCIE_CTRL0_PERST_B_update_pad_ctl_SHIFT (30U)
52253/*! update_pad_ctl - update lock for pad control
52254 */
52255#define IOMUXD_PCIE_CTRL0_PERST_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_update_pad_ctl_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_update_pad_ctl_MASK)
52256#define IOMUXD_PCIE_CTRL0_PERST_B_update_mux_mode_MASK (0x80000000U)
52257#define IOMUXD_PCIE_CTRL0_PERST_B_update_mux_mode_SHIFT (31U)
52258/*! update_mux_mode - update lock for mux control
52259 */
52260#define IOMUXD_PCIE_CTRL0_PERST_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_PERST_B_update_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_PERST_B_update_mux_mode_MASK)
52261/*! @} */
52262
52263/*! @name PCIE_CTRL0_CLKREQ_B - PCIE_CTRL0_CLKREQ_B */
52264/*! @{ */
52265#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PDRV_MASK (0x1U)
52266#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PDRV_SHIFT (0U)
52267/*! PDRV - Drive
52268 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
52269 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
52270 */
52271#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_PDRV_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_PDRV_MASK)
52272#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_1_4_MASK (0x1EU)
52273#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_1_4_SHIFT (1U)
52274/*! PCIE_CTRL0_CLKREQ_B_reserved_1_4 - reserved
52275 */
52276#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_1_4_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_1_4_MASK)
52277#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PULL_MASK (0x60U)
52278#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PULL_SHIFT (5U)
52279/*! PULL - Pull Down Pull Up
52280 * 0b10..pull down
52281 * 0b01..pull up
52282 * 0b00..Prohibited
52283 * 0b11..pull disabled
52284 */
52285#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_PULL_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_PULL_MASK)
52286#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_7_18_MASK (0x7FF80U)
52287#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_7_18_SHIFT (7U)
52288/*! PCIE_CTRL0_CLKREQ_B_reserved_7_18 - reserved
52289 */
52290#define IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_7_18_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_PCIE_CTRL0_CLKREQ_B_reserved_7_18_MASK)
52291#define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_CTRL_MASK (0x380000U)
52292#define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_CTRL_SHIFT (19U)
52293/*! WAKEUP_CTRL - wakeup control
52294 * 0b000..OFF
52295 * 0b001..RESAMPLE
52296 * 0b100..LOW
52297 * 0b111..HIGH
52298 * 0b110..RISE
52299 * 0b101..FALL
52300 */
52301#define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_CTRL_MASK)
52302#define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_MASK_MASK (0x400000U)
52303#define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_MASK_SHIFT (22U)
52304/*! WAKEUP_MASK - wakeup mask
52305 */
52306#define IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_MASK_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_WAKEUP_MASK_MASK)
52307#define IOMUXD_PCIE_CTRL0_CLKREQ_B_lp_config_MASK (0x1800000U)
52308#define IOMUXD_PCIE_CTRL0_CLKREQ_B_lp_config_SHIFT (23U)
52309/*! lp_config - lower power configuration
52310 * 0b01..EARLY_ISO
52311 * 0b10..LATE_ISO
52312 * 0b11..LATCH
52313 * 0b00..PASS
52314 */
52315#define IOMUXD_PCIE_CTRL0_CLKREQ_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_lp_config_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_lp_config_MASK)
52316#define IOMUXD_PCIE_CTRL0_CLKREQ_B_sw_config_MASK (0x6000000U)
52317#define IOMUXD_PCIE_CTRL0_CLKREQ_B_sw_config_SHIFT (25U)
52318/*! sw_config - output and input configuration
52319 * 0b01..OPEN_DRAIN
52320 * 0b10..OPEN_DRAIN_INPUT
52321 * 0b11..INOUT
52322 * 0b00..DEFAULT
52323 */
52324#define IOMUXD_PCIE_CTRL0_CLKREQ_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_sw_config_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_sw_config_MASK)
52325#define IOMUXD_PCIE_CTRL0_CLKREQ_B_mux_mode_MASK (0x38000000U)
52326#define IOMUXD_PCIE_CTRL0_CLKREQ_B_mux_mode_SHIFT (27U)
52327/*! mux_mode - mux_mode
52328 * 0b000..HSIO.PCIE0.CLKREQ_B
52329 * 0b100..LSIO.GPIO4.IO01
52330 */
52331#define IOMUXD_PCIE_CTRL0_CLKREQ_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_mux_mode_MASK)
52332#define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_pad_ctl_MASK (0x40000000U)
52333#define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_pad_ctl_SHIFT (30U)
52334/*! update_pad_ctl - update lock for pad control
52335 */
52336#define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_update_pad_ctl_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_update_pad_ctl_MASK)
52337#define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_mux_mode_MASK (0x80000000U)
52338#define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_mux_mode_SHIFT (31U)
52339/*! update_mux_mode - update lock for mux control
52340 */
52341#define IOMUXD_PCIE_CTRL0_CLKREQ_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_CLKREQ_B_update_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_CLKREQ_B_update_mux_mode_MASK)
52342/*! @} */
52343
52344/*! @name PCIE_CTRL0_WAKE_B - PCIE_CTRL0_WAKE_B */
52345/*! @{ */
52346#define IOMUXD_PCIE_CTRL0_WAKE_B_PDRV_MASK (0x1U)
52347#define IOMUXD_PCIE_CTRL0_WAKE_B_PDRV_SHIFT (0U)
52348/*! PDRV - Drive
52349 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
52350 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
52351 */
52352#define IOMUXD_PCIE_CTRL0_WAKE_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_PDRV_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_PDRV_MASK)
52353#define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_1_4_MASK (0x1EU)
52354#define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_1_4_SHIFT (1U)
52355/*! PCIE_CTRL0_WAKE_B_reserved_1_4 - reserved
52356 */
52357#define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_1_4_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_1_4_MASK)
52358#define IOMUXD_PCIE_CTRL0_WAKE_B_PULL_MASK (0x60U)
52359#define IOMUXD_PCIE_CTRL0_WAKE_B_PULL_SHIFT (5U)
52360/*! PULL - Pull Down Pull Up
52361 * 0b10..pull down
52362 * 0b01..pull up
52363 * 0b00..Prohibited
52364 * 0b11..pull disabled
52365 */
52366#define IOMUXD_PCIE_CTRL0_WAKE_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_PULL_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_PULL_MASK)
52367#define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_7_18_MASK (0x7FF80U)
52368#define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_7_18_SHIFT (7U)
52369/*! PCIE_CTRL0_WAKE_B_reserved_7_18 - reserved
52370 */
52371#define IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_7_18_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_PCIE_CTRL0_WAKE_B_reserved_7_18_MASK)
52372#define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_CTRL_MASK (0x380000U)
52373#define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_CTRL_SHIFT (19U)
52374/*! WAKEUP_CTRL - wakeup control
52375 * 0b000..OFF
52376 * 0b001..RESAMPLE
52377 * 0b100..LOW
52378 * 0b111..HIGH
52379 * 0b110..RISE
52380 * 0b101..FALL
52381 */
52382#define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_CTRL_MASK)
52383#define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_MASK_MASK (0x400000U)
52384#define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_MASK_SHIFT (22U)
52385/*! WAKEUP_MASK - wakeup mask
52386 */
52387#define IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_MASK_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_WAKEUP_MASK_MASK)
52388#define IOMUXD_PCIE_CTRL0_WAKE_B_lp_config_MASK (0x1800000U)
52389#define IOMUXD_PCIE_CTRL0_WAKE_B_lp_config_SHIFT (23U)
52390/*! lp_config - lower power configuration
52391 * 0b01..EARLY_ISO
52392 * 0b10..LATE_ISO
52393 * 0b11..LATCH
52394 * 0b00..PASS
52395 */
52396#define IOMUXD_PCIE_CTRL0_WAKE_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_lp_config_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_lp_config_MASK)
52397#define IOMUXD_PCIE_CTRL0_WAKE_B_sw_config_MASK (0x6000000U)
52398#define IOMUXD_PCIE_CTRL0_WAKE_B_sw_config_SHIFT (25U)
52399/*! sw_config - output and input configuration
52400 * 0b01..OPEN_DRAIN
52401 * 0b10..OPEN_DRAIN_INPUT
52402 * 0b11..INOUT
52403 * 0b00..DEFAULT
52404 */
52405#define IOMUXD_PCIE_CTRL0_WAKE_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_sw_config_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_sw_config_MASK)
52406#define IOMUXD_PCIE_CTRL0_WAKE_B_mux_mode_MASK (0x38000000U)
52407#define IOMUXD_PCIE_CTRL0_WAKE_B_mux_mode_SHIFT (27U)
52408/*! mux_mode - mux_mode
52409 * 0b000..HSIO.PCIE0.WAKE_B
52410 * 0b100..LSIO.GPIO4.IO02
52411 */
52412#define IOMUXD_PCIE_CTRL0_WAKE_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_mux_mode_MASK)
52413#define IOMUXD_PCIE_CTRL0_WAKE_B_update_pad_ctl_MASK (0x40000000U)
52414#define IOMUXD_PCIE_CTRL0_WAKE_B_update_pad_ctl_SHIFT (30U)
52415/*! update_pad_ctl - update lock for pad control
52416 */
52417#define IOMUXD_PCIE_CTRL0_WAKE_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_update_pad_ctl_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_update_pad_ctl_MASK)
52418#define IOMUXD_PCIE_CTRL0_WAKE_B_update_mux_mode_MASK (0x80000000U)
52419#define IOMUXD_PCIE_CTRL0_WAKE_B_update_mux_mode_SHIFT (31U)
52420/*! update_mux_mode - update lock for mux control
52421 */
52422#define IOMUXD_PCIE_CTRL0_WAKE_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PCIE_CTRL0_WAKE_B_update_mux_mode_SHIFT)) & IOMUXD_PCIE_CTRL0_WAKE_B_update_mux_mode_MASK)
52423/*! @} */
52424
52425/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP - IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP */
52426/*! @{ */
52427#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMP_MASK (0x7U)
52428#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMP_SHIFT (0U)
52429/*! COMP - COMP
52430 * 0b010..Fixed code mode
52431 * 0b100..High impedance mode
52432 * 0b110..Read mode
52433 * 0b000..Normal Mode
52434 * 0b001..Freeze Mode
52435 */
52436#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMP_MASK)
52437#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_FASTFRZ_EN_MASK (0x8U)
52438#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_FASTFRZ_EN_SHIFT (3U)
52439/*! FASTFRZ_EN - FASTFRZ_EN
52440 * 0b1..FASTFRZ signal is driven by output of subsystem
52441 * 0b0..FASTFRZ signal is gated to 0
52442 */
52443#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_FASTFRZ_EN_MASK)
52444#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4_MASK (0x10U)
52445#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4_SHIFT (4U)
52446/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4 - reserved
52447 */
52448#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_4_4_MASK)
52449#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCP_MASK (0x1E0U)
52450#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCP_SHIFT (5U)
52451/*! RASRCP - RASRCP
52452 * 0b0101..Reset Value
52453 */
52454#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCP_MASK)
52455#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCN_MASK (0x1E00U)
52456#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCN_SHIFT (9U)
52457/*! RASRCN - RASRCN
52458 * 0b1010..Reset Value
52459 */
52460#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_RASRCN_MASK)
52461#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SELECT_NASRC_MASK (0x2000U)
52462#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SELECT_NASRC_SHIFT (13U)
52463/*! SELECT_NASRC - SELECT_NASRC
52464 * 0b1..NASRCN value
52465 * 0b0..NASRCP value
52466 */
52467#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SELECT_NASRC_MASK)
52468#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMPOK_MASK (0x4000U)
52469#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMPOK_SHIFT (14U)
52470/*! COMPOK - COMPOK
52471 * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
52472 * 0b1..compensation cell in Normal mode and tracking PVT
52473 */
52474#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_COMPOK_MASK)
52475#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_READ_NASRC_MASK (0x78000U)
52476#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_READ_NASRC_SHIFT (15U)
52477/*! READ_NASRC - READ_NASRC
52478 * 0b0000..READ Only
52479 */
52480#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_READ_NASRC_MASK)
52481#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22_MASK (0x780000U)
52482#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22_SHIFT (19U)
52483/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22 - reserved
52484 */
52485#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_19_22_MASK)
52486#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SLEEP_MASK (0x1800000U)
52487#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SLEEP_SHIFT (23U)
52488/*! SLEEP - SLEEP
52489 * 0b11..Force into sleep mode
52490 * 0b00..NO
52491 * 0b01..EARLY
52492 * 0b10..LATE
52493 */
52494#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_SLEEP_MASK)
52495#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29_MASK (0x3E000000U)
52496#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29_SHIFT (25U)
52497/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29 - reserved
52498 */
52499#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_reserved_25_29_MASK)
52500#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_pad_ctl_MASK (0x40000000U)
52501#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_pad_ctl_SHIFT (30U)
52502/*! update_pad_ctl - update lock for pad control
52503 */
52504#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_pad_ctl_MASK)
52505#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_mux_mode_MASK (0x80000000U)
52506#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_mux_mode_SHIFT (31U)
52507/*! update_mux_mode - update lock for mux control
52508 */
52509#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_PCIESEP_update_mux_mode_MASK)
52510/*! @} */
52511
52512/*! @name USB_SS3_TC0 - USB_SS3_TC0 */
52513/*! @{ */
52514#define IOMUXD_USB_SS3_TC0_DSE_MASK (0x3U)
52515#define IOMUXD_USB_SS3_TC0_DSE_SHIFT (0U)
52516/*! DSE - Drive
52517 * 0b00..Drive select 2mA
52518 * 0b11..Drive select 12mA
52519 * 0b01..Drive select 4mA
52520 * 0b10..Drive select 8mA
52521 */
52522#define IOMUXD_USB_SS3_TC0_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_DSE_SHIFT)) & IOMUXD_USB_SS3_TC0_DSE_MASK)
52523#define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_2_4_MASK (0x1CU)
52524#define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_2_4_SHIFT (2U)
52525/*! USB_SS3_TC0_reserved_2_4 - reserved
52526 */
52527#define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_2_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_2_4_SHIFT)) & IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_2_4_MASK)
52528#define IOMUXD_USB_SS3_TC0_PULL_MASK (0x60U)
52529#define IOMUXD_USB_SS3_TC0_PULL_SHIFT (5U)
52530/*! PULL - Pull Down Pull Up
52531 * 0b00..Bus-Keeper
52532 * 0b10..pull down
52533 * 0b01..pull up
52534 * 0b11..No Pull
52535 */
52536#define IOMUXD_USB_SS3_TC0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_PULL_SHIFT)) & IOMUXD_USB_SS3_TC0_PULL_MASK)
52537#define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_7_18_MASK (0x7FF80U)
52538#define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_7_18_SHIFT (7U)
52539/*! USB_SS3_TC0_reserved_7_18 - reserved
52540 */
52541#define IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_7_18_SHIFT)) & IOMUXD_USB_SS3_TC0_USB_SS3_TC0_reserved_7_18_MASK)
52542#define IOMUXD_USB_SS3_TC0_WAKEUP_CTRL_MASK (0x380000U)
52543#define IOMUXD_USB_SS3_TC0_WAKEUP_CTRL_SHIFT (19U)
52544/*! WAKEUP_CTRL - wakeup control
52545 * 0b000..OFF
52546 * 0b001..RESAMPLE
52547 * 0b100..LOW
52548 * 0b111..HIGH
52549 * 0b110..RISE
52550 * 0b101..FALL
52551 */
52552#define IOMUXD_USB_SS3_TC0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_WAKEUP_CTRL_SHIFT)) & IOMUXD_USB_SS3_TC0_WAKEUP_CTRL_MASK)
52553#define IOMUXD_USB_SS3_TC0_WAKEUP_MASK_MASK (0x400000U)
52554#define IOMUXD_USB_SS3_TC0_WAKEUP_MASK_SHIFT (22U)
52555/*! WAKEUP_MASK - wakeup mask
52556 */
52557#define IOMUXD_USB_SS3_TC0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_WAKEUP_MASK_SHIFT)) & IOMUXD_USB_SS3_TC0_WAKEUP_MASK_MASK)
52558#define IOMUXD_USB_SS3_TC0_lp_config_MASK (0x1800000U)
52559#define IOMUXD_USB_SS3_TC0_lp_config_SHIFT (23U)
52560/*! lp_config - lower power configuration
52561 * 0b01..EARLY_ISO
52562 * 0b10..LATE_ISO
52563 * 0b11..LATCH
52564 * 0b00..PASS
52565 */
52566#define IOMUXD_USB_SS3_TC0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_lp_config_SHIFT)) & IOMUXD_USB_SS3_TC0_lp_config_MASK)
52567#define IOMUXD_USB_SS3_TC0_sw_config_MASK (0x6000000U)
52568#define IOMUXD_USB_SS3_TC0_sw_config_SHIFT (25U)
52569/*! sw_config - output and input configuration
52570 * 0b01..OPEN_DRAIN
52571 * 0b10..OPEN_DRAIN_INPUT
52572 * 0b11..INOUT
52573 * 0b00..DEFAULT
52574 */
52575#define IOMUXD_USB_SS3_TC0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_sw_config_SHIFT)) & IOMUXD_USB_SS3_TC0_sw_config_MASK)
52576#define IOMUXD_USB_SS3_TC0_mux_mode_MASK (0x38000000U)
52577#define IOMUXD_USB_SS3_TC0_mux_mode_SHIFT (27U)
52578/*! mux_mode - mux_mode
52579 * 0b000..ADMA.I2C1.SCL
52580 * 0b001..CONN.USB_OTG1.PWR
52581 * 0b010..CONN.USB_OTG2.PWR
52582 * 0b100..LSIO.GPIO4.IO03
52583 */
52584#define IOMUXD_USB_SS3_TC0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC0_mux_mode_MASK)
52585#define IOMUXD_USB_SS3_TC0_update_pad_ctl_MASK (0x40000000U)
52586#define IOMUXD_USB_SS3_TC0_update_pad_ctl_SHIFT (30U)
52587/*! update_pad_ctl - update lock for pad control
52588 */
52589#define IOMUXD_USB_SS3_TC0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_update_pad_ctl_SHIFT)) & IOMUXD_USB_SS3_TC0_update_pad_ctl_MASK)
52590#define IOMUXD_USB_SS3_TC0_update_mux_mode_MASK (0x80000000U)
52591#define IOMUXD_USB_SS3_TC0_update_mux_mode_SHIFT (31U)
52592/*! update_mux_mode - update lock for mux control
52593 */
52594#define IOMUXD_USB_SS3_TC0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC0_update_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC0_update_mux_mode_MASK)
52595/*! @} */
52596
52597/*! @name USB_SS3_TC1 - USB_SS3_TC1 */
52598/*! @{ */
52599#define IOMUXD_USB_SS3_TC1_DSE_MASK (0x3U)
52600#define IOMUXD_USB_SS3_TC1_DSE_SHIFT (0U)
52601/*! DSE - Drive
52602 * 0b00..Drive select 2mA
52603 * 0b11..Drive select 12mA
52604 * 0b01..Drive select 4mA
52605 * 0b10..Drive select 8mA
52606 */
52607#define IOMUXD_USB_SS3_TC1_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_DSE_SHIFT)) & IOMUXD_USB_SS3_TC1_DSE_MASK)
52608#define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_2_4_MASK (0x1CU)
52609#define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_2_4_SHIFT (2U)
52610/*! USB_SS3_TC1_reserved_2_4 - reserved
52611 */
52612#define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_2_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_2_4_SHIFT)) & IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_2_4_MASK)
52613#define IOMUXD_USB_SS3_TC1_PULL_MASK (0x60U)
52614#define IOMUXD_USB_SS3_TC1_PULL_SHIFT (5U)
52615/*! PULL - Pull Down Pull Up
52616 * 0b00..Bus-Keeper
52617 * 0b10..pull down
52618 * 0b01..pull up
52619 * 0b11..No Pull
52620 */
52621#define IOMUXD_USB_SS3_TC1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_PULL_SHIFT)) & IOMUXD_USB_SS3_TC1_PULL_MASK)
52622#define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_7_18_MASK (0x7FF80U)
52623#define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_7_18_SHIFT (7U)
52624/*! USB_SS3_TC1_reserved_7_18 - reserved
52625 */
52626#define IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_7_18_SHIFT)) & IOMUXD_USB_SS3_TC1_USB_SS3_TC1_reserved_7_18_MASK)
52627#define IOMUXD_USB_SS3_TC1_WAKEUP_CTRL_MASK (0x380000U)
52628#define IOMUXD_USB_SS3_TC1_WAKEUP_CTRL_SHIFT (19U)
52629/*! WAKEUP_CTRL - wakeup control
52630 * 0b000..OFF
52631 * 0b001..RESAMPLE
52632 * 0b100..LOW
52633 * 0b111..HIGH
52634 * 0b110..RISE
52635 * 0b101..FALL
52636 */
52637#define IOMUXD_USB_SS3_TC1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_WAKEUP_CTRL_SHIFT)) & IOMUXD_USB_SS3_TC1_WAKEUP_CTRL_MASK)
52638#define IOMUXD_USB_SS3_TC1_WAKEUP_MASK_MASK (0x400000U)
52639#define IOMUXD_USB_SS3_TC1_WAKEUP_MASK_SHIFT (22U)
52640/*! WAKEUP_MASK - wakeup mask
52641 */
52642#define IOMUXD_USB_SS3_TC1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_WAKEUP_MASK_SHIFT)) & IOMUXD_USB_SS3_TC1_WAKEUP_MASK_MASK)
52643#define IOMUXD_USB_SS3_TC1_lp_config_MASK (0x1800000U)
52644#define IOMUXD_USB_SS3_TC1_lp_config_SHIFT (23U)
52645/*! lp_config - lower power configuration
52646 * 0b01..EARLY_ISO
52647 * 0b10..LATE_ISO
52648 * 0b11..LATCH
52649 * 0b00..PASS
52650 */
52651#define IOMUXD_USB_SS3_TC1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_lp_config_SHIFT)) & IOMUXD_USB_SS3_TC1_lp_config_MASK)
52652#define IOMUXD_USB_SS3_TC1_sw_config_MASK (0x6000000U)
52653#define IOMUXD_USB_SS3_TC1_sw_config_SHIFT (25U)
52654/*! sw_config - output and input configuration
52655 * 0b01..OPEN_DRAIN
52656 * 0b10..OPEN_DRAIN_INPUT
52657 * 0b11..INOUT
52658 * 0b00..DEFAULT
52659 */
52660#define IOMUXD_USB_SS3_TC1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_sw_config_SHIFT)) & IOMUXD_USB_SS3_TC1_sw_config_MASK)
52661#define IOMUXD_USB_SS3_TC1_mux_mode_MASK (0x38000000U)
52662#define IOMUXD_USB_SS3_TC1_mux_mode_SHIFT (27U)
52663/*! mux_mode - mux_mode
52664 * 0b000..ADMA.I2C1.SCL
52665 * 0b001..CONN.USB_OTG2.PWR
52666 * 0b100..LSIO.GPIO4.IO04
52667 */
52668#define IOMUXD_USB_SS3_TC1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC1_mux_mode_MASK)
52669#define IOMUXD_USB_SS3_TC1_update_pad_ctl_MASK (0x40000000U)
52670#define IOMUXD_USB_SS3_TC1_update_pad_ctl_SHIFT (30U)
52671/*! update_pad_ctl - update lock for pad control
52672 */
52673#define IOMUXD_USB_SS3_TC1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_update_pad_ctl_SHIFT)) & IOMUXD_USB_SS3_TC1_update_pad_ctl_MASK)
52674#define IOMUXD_USB_SS3_TC1_update_mux_mode_MASK (0x80000000U)
52675#define IOMUXD_USB_SS3_TC1_update_mux_mode_SHIFT (31U)
52676/*! update_mux_mode - update lock for mux control
52677 */
52678#define IOMUXD_USB_SS3_TC1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC1_update_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC1_update_mux_mode_MASK)
52679/*! @} */
52680
52681/*! @name USB_SS3_TC2 - USB_SS3_TC2 */
52682/*! @{ */
52683#define IOMUXD_USB_SS3_TC2_DSE_MASK (0x3U)
52684#define IOMUXD_USB_SS3_TC2_DSE_SHIFT (0U)
52685/*! DSE - Drive
52686 * 0b00..Drive select 2mA
52687 * 0b11..Drive select 12mA
52688 * 0b01..Drive select 4mA
52689 * 0b10..Drive select 8mA
52690 */
52691#define IOMUXD_USB_SS3_TC2_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_DSE_SHIFT)) & IOMUXD_USB_SS3_TC2_DSE_MASK)
52692#define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_2_4_MASK (0x1CU)
52693#define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_2_4_SHIFT (2U)
52694/*! USB_SS3_TC2_reserved_2_4 - reserved
52695 */
52696#define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_2_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_2_4_SHIFT)) & IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_2_4_MASK)
52697#define IOMUXD_USB_SS3_TC2_PULL_MASK (0x60U)
52698#define IOMUXD_USB_SS3_TC2_PULL_SHIFT (5U)
52699/*! PULL - Pull Down Pull Up
52700 * 0b00..Bus-Keeper
52701 * 0b10..pull down
52702 * 0b01..pull up
52703 * 0b11..No Pull
52704 */
52705#define IOMUXD_USB_SS3_TC2_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_PULL_SHIFT)) & IOMUXD_USB_SS3_TC2_PULL_MASK)
52706#define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_7_18_MASK (0x7FF80U)
52707#define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_7_18_SHIFT (7U)
52708/*! USB_SS3_TC2_reserved_7_18 - reserved
52709 */
52710#define IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_7_18_SHIFT)) & IOMUXD_USB_SS3_TC2_USB_SS3_TC2_reserved_7_18_MASK)
52711#define IOMUXD_USB_SS3_TC2_WAKEUP_CTRL_MASK (0x380000U)
52712#define IOMUXD_USB_SS3_TC2_WAKEUP_CTRL_SHIFT (19U)
52713/*! WAKEUP_CTRL - wakeup control
52714 * 0b000..OFF
52715 * 0b001..RESAMPLE
52716 * 0b100..LOW
52717 * 0b111..HIGH
52718 * 0b110..RISE
52719 * 0b101..FALL
52720 */
52721#define IOMUXD_USB_SS3_TC2_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_WAKEUP_CTRL_SHIFT)) & IOMUXD_USB_SS3_TC2_WAKEUP_CTRL_MASK)
52722#define IOMUXD_USB_SS3_TC2_WAKEUP_MASK_MASK (0x400000U)
52723#define IOMUXD_USB_SS3_TC2_WAKEUP_MASK_SHIFT (22U)
52724/*! WAKEUP_MASK - wakeup mask
52725 */
52726#define IOMUXD_USB_SS3_TC2_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_WAKEUP_MASK_SHIFT)) & IOMUXD_USB_SS3_TC2_WAKEUP_MASK_MASK)
52727#define IOMUXD_USB_SS3_TC2_lp_config_MASK (0x1800000U)
52728#define IOMUXD_USB_SS3_TC2_lp_config_SHIFT (23U)
52729/*! lp_config - lower power configuration
52730 * 0b01..EARLY_ISO
52731 * 0b10..LATE_ISO
52732 * 0b11..LATCH
52733 * 0b00..PASS
52734 */
52735#define IOMUXD_USB_SS3_TC2_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_lp_config_SHIFT)) & IOMUXD_USB_SS3_TC2_lp_config_MASK)
52736#define IOMUXD_USB_SS3_TC2_sw_config_MASK (0x6000000U)
52737#define IOMUXD_USB_SS3_TC2_sw_config_SHIFT (25U)
52738/*! sw_config - output and input configuration
52739 * 0b01..OPEN_DRAIN
52740 * 0b10..OPEN_DRAIN_INPUT
52741 * 0b11..INOUT
52742 * 0b00..DEFAULT
52743 */
52744#define IOMUXD_USB_SS3_TC2_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_sw_config_SHIFT)) & IOMUXD_USB_SS3_TC2_sw_config_MASK)
52745#define IOMUXD_USB_SS3_TC2_mux_mode_MASK (0x38000000U)
52746#define IOMUXD_USB_SS3_TC2_mux_mode_SHIFT (27U)
52747/*! mux_mode - mux_mode
52748 * 0b000..ADMA.I2C1.SDA
52749 * 0b001..CONN.USB_OTG1.OC
52750 * 0b010..CONN.USB_OTG2.OC
52751 * 0b100..LSIO.GPIO4.IO05
52752 */
52753#define IOMUXD_USB_SS3_TC2_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC2_mux_mode_MASK)
52754#define IOMUXD_USB_SS3_TC2_update_pad_ctl_MASK (0x40000000U)
52755#define IOMUXD_USB_SS3_TC2_update_pad_ctl_SHIFT (30U)
52756/*! update_pad_ctl - update lock for pad control
52757 */
52758#define IOMUXD_USB_SS3_TC2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_update_pad_ctl_SHIFT)) & IOMUXD_USB_SS3_TC2_update_pad_ctl_MASK)
52759#define IOMUXD_USB_SS3_TC2_update_mux_mode_MASK (0x80000000U)
52760#define IOMUXD_USB_SS3_TC2_update_mux_mode_SHIFT (31U)
52761/*! update_mux_mode - update lock for mux control
52762 */
52763#define IOMUXD_USB_SS3_TC2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC2_update_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC2_update_mux_mode_MASK)
52764/*! @} */
52765
52766/*! @name USB_SS3_TC3 - USB_SS3_TC3 */
52767/*! @{ */
52768#define IOMUXD_USB_SS3_TC3_DSE_MASK (0x3U)
52769#define IOMUXD_USB_SS3_TC3_DSE_SHIFT (0U)
52770/*! DSE - Drive
52771 * 0b00..Drive select 2mA
52772 * 0b11..Drive select 12mA
52773 * 0b01..Drive select 4mA
52774 * 0b10..Drive select 8mA
52775 */
52776#define IOMUXD_USB_SS3_TC3_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_DSE_SHIFT)) & IOMUXD_USB_SS3_TC3_DSE_MASK)
52777#define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_2_4_MASK (0x1CU)
52778#define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_2_4_SHIFT (2U)
52779/*! USB_SS3_TC3_reserved_2_4 - reserved
52780 */
52781#define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_2_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_2_4_SHIFT)) & IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_2_4_MASK)
52782#define IOMUXD_USB_SS3_TC3_PULL_MASK (0x60U)
52783#define IOMUXD_USB_SS3_TC3_PULL_SHIFT (5U)
52784/*! PULL - Pull Down Pull Up
52785 * 0b00..Bus-Keeper
52786 * 0b10..pull down
52787 * 0b01..pull up
52788 * 0b11..No Pull
52789 */
52790#define IOMUXD_USB_SS3_TC3_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_PULL_SHIFT)) & IOMUXD_USB_SS3_TC3_PULL_MASK)
52791#define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_7_18_MASK (0x7FF80U)
52792#define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_7_18_SHIFT (7U)
52793/*! USB_SS3_TC3_reserved_7_18 - reserved
52794 */
52795#define IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_7_18_SHIFT)) & IOMUXD_USB_SS3_TC3_USB_SS3_TC3_reserved_7_18_MASK)
52796#define IOMUXD_USB_SS3_TC3_WAKEUP_CTRL_MASK (0x380000U)
52797#define IOMUXD_USB_SS3_TC3_WAKEUP_CTRL_SHIFT (19U)
52798/*! WAKEUP_CTRL - wakeup control
52799 * 0b000..OFF
52800 * 0b001..RESAMPLE
52801 * 0b100..LOW
52802 * 0b111..HIGH
52803 * 0b110..RISE
52804 * 0b101..FALL
52805 */
52806#define IOMUXD_USB_SS3_TC3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_WAKEUP_CTRL_SHIFT)) & IOMUXD_USB_SS3_TC3_WAKEUP_CTRL_MASK)
52807#define IOMUXD_USB_SS3_TC3_WAKEUP_MASK_MASK (0x400000U)
52808#define IOMUXD_USB_SS3_TC3_WAKEUP_MASK_SHIFT (22U)
52809/*! WAKEUP_MASK - wakeup mask
52810 */
52811#define IOMUXD_USB_SS3_TC3_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_WAKEUP_MASK_SHIFT)) & IOMUXD_USB_SS3_TC3_WAKEUP_MASK_MASK)
52812#define IOMUXD_USB_SS3_TC3_lp_config_MASK (0x1800000U)
52813#define IOMUXD_USB_SS3_TC3_lp_config_SHIFT (23U)
52814/*! lp_config - lower power configuration
52815 * 0b01..EARLY_ISO
52816 * 0b10..LATE_ISO
52817 * 0b11..LATCH
52818 * 0b00..PASS
52819 */
52820#define IOMUXD_USB_SS3_TC3_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_lp_config_SHIFT)) & IOMUXD_USB_SS3_TC3_lp_config_MASK)
52821#define IOMUXD_USB_SS3_TC3_sw_config_MASK (0x6000000U)
52822#define IOMUXD_USB_SS3_TC3_sw_config_SHIFT (25U)
52823/*! sw_config - output and input configuration
52824 * 0b01..OPEN_DRAIN
52825 * 0b10..OPEN_DRAIN_INPUT
52826 * 0b11..INOUT
52827 * 0b00..DEFAULT
52828 */
52829#define IOMUXD_USB_SS3_TC3_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_sw_config_SHIFT)) & IOMUXD_USB_SS3_TC3_sw_config_MASK)
52830#define IOMUXD_USB_SS3_TC3_mux_mode_MASK (0x38000000U)
52831#define IOMUXD_USB_SS3_TC3_mux_mode_SHIFT (27U)
52832/*! mux_mode - mux_mode
52833 * 0b000..ADMA.I2C1.SDA
52834 * 0b001..CONN.USB_OTG2.OC
52835 * 0b100..LSIO.GPIO4.IO06
52836 */
52837#define IOMUXD_USB_SS3_TC3_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC3_mux_mode_MASK)
52838#define IOMUXD_USB_SS3_TC3_update_pad_ctl_MASK (0x40000000U)
52839#define IOMUXD_USB_SS3_TC3_update_pad_ctl_SHIFT (30U)
52840/*! update_pad_ctl - update lock for pad control
52841 */
52842#define IOMUXD_USB_SS3_TC3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_update_pad_ctl_SHIFT)) & IOMUXD_USB_SS3_TC3_update_pad_ctl_MASK)
52843#define IOMUXD_USB_SS3_TC3_update_mux_mode_MASK (0x80000000U)
52844#define IOMUXD_USB_SS3_TC3_update_mux_mode_SHIFT (31U)
52845/*! update_mux_mode - update lock for mux control
52846 */
52847#define IOMUXD_USB_SS3_TC3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USB_SS3_TC3_update_mux_mode_SHIFT)) & IOMUXD_USB_SS3_TC3_update_mux_mode_MASK)
52848/*! @} */
52849
52850/*! @name IOMUXD_COMP_CTL_GPIO_3V3_USB3IO - IOMUXD_COMP_CTL_GPIO_3V3_USB3IO */
52851/*! @{ */
52852#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22_MASK (0x7FFFFFU)
52853#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22_SHIFT (0U)
52854/*! IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22 - reserved
52855 */
52856#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_0_22_MASK)
52857#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_SLEEP_MASK (0x1800000U)
52858#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_SLEEP_SHIFT (23U)
52859/*! SLEEP - SLEEP
52860 * 0b11..LAST
52861 * 0b00..NO
52862 * 0b01..EARLY
52863 * 0b10..LATE
52864 */
52865#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_SLEEP_MASK)
52866#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29_MASK (0x3E000000U)
52867#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29_SHIFT (25U)
52868/*! IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29 - reserved
52869 */
52870#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_reserved_25_29_MASK)
52871#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_pad_ctl_MASK (0x40000000U)
52872#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_pad_ctl_SHIFT (30U)
52873/*! update_pad_ctl - update lock for pad control
52874 */
52875#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_pad_ctl_MASK)
52876#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_mux_mode_MASK (0x80000000U)
52877#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_mux_mode_SHIFT (31U)
52878/*! update_mux_mode - update lock for mux control
52879 */
52880#define IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_3V3_USB3IO_update_mux_mode_MASK)
52881/*! @} */
52882
52883/*! @name IOMUXD_GROUP_0_0 - na */
52884/*! @{ */
52885#define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_PERST_B_MASK (0x1U)
52886#define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_PERST_B_SHIFT (0U)
52887/*! PCIE_CTRL0_PERST_B - wakeup from PCIE_CTRL0_PERST_B
52888 */
52889#define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_PERST_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_PERST_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_PERST_B_MASK)
52890#define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_CLKREQ_B_MASK (0x2U)
52891#define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_CLKREQ_B_SHIFT (1U)
52892/*! PCIE_CTRL0_CLKREQ_B - wakeup from PCIE_CTRL0_CLKREQ_B
52893 */
52894#define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_CLKREQ_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_CLKREQ_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_CLKREQ_B_MASK)
52895#define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_WAKE_B_MASK (0x4U)
52896#define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_WAKE_B_SHIFT (2U)
52897/*! PCIE_CTRL0_WAKE_B - wakeup from PCIE_CTRL0_WAKE_B
52898 */
52899#define IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_WAKE_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_WAKE_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_PCIE_CTRL0_WAKE_B_MASK)
52900#define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_3_3_MASK (0x8U)
52901#define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_3_3_SHIFT (3U)
52902/*! iomuxd_group_0_0_reserved_3_3 - reserved
52903 */
52904#define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_3_3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_3_3_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_3_3_MASK)
52905#define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC0_MASK (0x10U)
52906#define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC0_SHIFT (4U)
52907/*! USB_SS3_TC0 - wakeup from USB_SS3_TC0
52908 */
52909#define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC0_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC0_MASK)
52910#define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC1_MASK (0x20U)
52911#define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC1_SHIFT (5U)
52912/*! USB_SS3_TC1 - wakeup from USB_SS3_TC1
52913 */
52914#define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC1_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC1_MASK)
52915#define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC2_MASK (0x40U)
52916#define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC2_SHIFT (6U)
52917/*! USB_SS3_TC2 - wakeup from USB_SS3_TC2
52918 */
52919#define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC2_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC2_MASK)
52920#define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC3_MASK (0x80U)
52921#define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC3_SHIFT (7U)
52922/*! USB_SS3_TC3 - wakeup from USB_SS3_TC3
52923 */
52924#define IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC3_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_USB_SS3_TC3_MASK)
52925#define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_8_31_MASK (0xFFFFFF00U)
52926#define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_8_31_SHIFT (8U)
52927/*! iomuxd_group_0_0_reserved_8_31 - reserved
52928 */
52929#define IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_8_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_0_0_iomuxd_group_0_0_reserved_8_31_MASK)
52930/*! @} */
52931
52932/*! @name EMMC0_CLK - EMMC0_CLK */
52933/*! @{ */
52934#define IOMUXD_EMMC0_CLK_PDRV_MASK (0x1U)
52935#define IOMUXD_EMMC0_CLK_PDRV_SHIFT (0U)
52936/*! PDRV - Drive
52937 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
52938 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
52939 */
52940#define IOMUXD_EMMC0_CLK_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_PDRV_SHIFT)) & IOMUXD_EMMC0_CLK_PDRV_MASK)
52941#define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_1_4_MASK (0x1EU)
52942#define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_1_4_SHIFT (1U)
52943/*! EMMC0_CLK_reserved_1_4 - reserved
52944 */
52945#define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_1_4_MASK)
52946#define IOMUXD_EMMC0_CLK_PULL_MASK (0x60U)
52947#define IOMUXD_EMMC0_CLK_PULL_SHIFT (5U)
52948/*! PULL - Pull Down Pull Up
52949 * 0b10..pull down
52950 * 0b01..pull up
52951 * 0b00..Prohibited
52952 * 0b11..pull disabled
52953 */
52954#define IOMUXD_EMMC0_CLK_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_PULL_SHIFT)) & IOMUXD_EMMC0_CLK_PULL_MASK)
52955#define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_7_18_MASK (0x7FF80U)
52956#define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_7_18_SHIFT (7U)
52957/*! EMMC0_CLK_reserved_7_18 - reserved
52958 */
52959#define IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_CLK_EMMC0_CLK_reserved_7_18_MASK)
52960#define IOMUXD_EMMC0_CLK_WAKEUP_CTRL_MASK (0x380000U)
52961#define IOMUXD_EMMC0_CLK_WAKEUP_CTRL_SHIFT (19U)
52962/*! WAKEUP_CTRL - wakeup control
52963 * 0b000..OFF
52964 * 0b001..RESAMPLE
52965 * 0b100..LOW
52966 * 0b111..HIGH
52967 * 0b110..RISE
52968 * 0b101..FALL
52969 */
52970#define IOMUXD_EMMC0_CLK_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_CLK_WAKEUP_CTRL_MASK)
52971#define IOMUXD_EMMC0_CLK_WAKEUP_MASK_MASK (0x400000U)
52972#define IOMUXD_EMMC0_CLK_WAKEUP_MASK_SHIFT (22U)
52973/*! WAKEUP_MASK - wakeup mask
52974 */
52975#define IOMUXD_EMMC0_CLK_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_CLK_WAKEUP_MASK_MASK)
52976#define IOMUXD_EMMC0_CLK_lp_config_MASK (0x1800000U)
52977#define IOMUXD_EMMC0_CLK_lp_config_SHIFT (23U)
52978/*! lp_config - lower power configuration
52979 * 0b01..EARLY_ISO
52980 * 0b10..LATE_ISO
52981 * 0b11..LATCH
52982 * 0b00..PASS
52983 */
52984#define IOMUXD_EMMC0_CLK_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_lp_config_SHIFT)) & IOMUXD_EMMC0_CLK_lp_config_MASK)
52985#define IOMUXD_EMMC0_CLK_sw_config_MASK (0x6000000U)
52986#define IOMUXD_EMMC0_CLK_sw_config_SHIFT (25U)
52987/*! sw_config - output and input configuration
52988 * 0b01..OPEN_DRAIN
52989 * 0b10..OPEN_DRAIN_INPUT
52990 * 0b11..INOUT
52991 * 0b00..DEFAULT
52992 */
52993#define IOMUXD_EMMC0_CLK_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_sw_config_SHIFT)) & IOMUXD_EMMC0_CLK_sw_config_MASK)
52994#define IOMUXD_EMMC0_CLK_mux_mode_MASK (0x38000000U)
52995#define IOMUXD_EMMC0_CLK_mux_mode_SHIFT (27U)
52996/*! mux_mode - mux_mode
52997 * 0b000..CONN.EMMC0.CLK
52998 * 0b001..CONN.NAND.READY_B
52999 * 0b100..LSIO.GPIO4.IO07
53000 */
53001#define IOMUXD_EMMC0_CLK_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_mux_mode_SHIFT)) & IOMUXD_EMMC0_CLK_mux_mode_MASK)
53002#define IOMUXD_EMMC0_CLK_update_pad_ctl_MASK (0x40000000U)
53003#define IOMUXD_EMMC0_CLK_update_pad_ctl_SHIFT (30U)
53004/*! update_pad_ctl - update lock for pad control
53005 */
53006#define IOMUXD_EMMC0_CLK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_CLK_update_pad_ctl_MASK)
53007#define IOMUXD_EMMC0_CLK_update_mux_mode_MASK (0x80000000U)
53008#define IOMUXD_EMMC0_CLK_update_mux_mode_SHIFT (31U)
53009/*! update_mux_mode - update lock for mux control
53010 */
53011#define IOMUXD_EMMC0_CLK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CLK_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_CLK_update_mux_mode_MASK)
53012/*! @} */
53013
53014/*! @name EMMC0_CMD - EMMC0_CMD */
53015/*! @{ */
53016#define IOMUXD_EMMC0_CMD_PDRV_MASK (0x1U)
53017#define IOMUXD_EMMC0_CMD_PDRV_SHIFT (0U)
53018/*! PDRV - Drive
53019 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
53020 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
53021 */
53022#define IOMUXD_EMMC0_CMD_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_PDRV_SHIFT)) & IOMUXD_EMMC0_CMD_PDRV_MASK)
53023#define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_1_4_MASK (0x1EU)
53024#define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_1_4_SHIFT (1U)
53025/*! EMMC0_CMD_reserved_1_4 - reserved
53026 */
53027#define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_1_4_MASK)
53028#define IOMUXD_EMMC0_CMD_PULL_MASK (0x60U)
53029#define IOMUXD_EMMC0_CMD_PULL_SHIFT (5U)
53030/*! PULL - Pull Down Pull Up
53031 * 0b10..pull down
53032 * 0b01..pull up
53033 * 0b00..Prohibited
53034 * 0b11..pull disabled
53035 */
53036#define IOMUXD_EMMC0_CMD_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_PULL_SHIFT)) & IOMUXD_EMMC0_CMD_PULL_MASK)
53037#define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_7_18_MASK (0x7FF80U)
53038#define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_7_18_SHIFT (7U)
53039/*! EMMC0_CMD_reserved_7_18 - reserved
53040 */
53041#define IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_CMD_EMMC0_CMD_reserved_7_18_MASK)
53042#define IOMUXD_EMMC0_CMD_WAKEUP_CTRL_MASK (0x380000U)
53043#define IOMUXD_EMMC0_CMD_WAKEUP_CTRL_SHIFT (19U)
53044/*! WAKEUP_CTRL - wakeup control
53045 * 0b000..OFF
53046 * 0b001..RESAMPLE
53047 * 0b100..LOW
53048 * 0b111..HIGH
53049 * 0b110..RISE
53050 * 0b101..FALL
53051 */
53052#define IOMUXD_EMMC0_CMD_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_CMD_WAKEUP_CTRL_MASK)
53053#define IOMUXD_EMMC0_CMD_WAKEUP_MASK_MASK (0x400000U)
53054#define IOMUXD_EMMC0_CMD_WAKEUP_MASK_SHIFT (22U)
53055/*! WAKEUP_MASK - wakeup mask
53056 */
53057#define IOMUXD_EMMC0_CMD_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_CMD_WAKEUP_MASK_MASK)
53058#define IOMUXD_EMMC0_CMD_lp_config_MASK (0x1800000U)
53059#define IOMUXD_EMMC0_CMD_lp_config_SHIFT (23U)
53060/*! lp_config - lower power configuration
53061 * 0b01..EARLY_ISO
53062 * 0b10..LATE_ISO
53063 * 0b11..LATCH
53064 * 0b00..PASS
53065 */
53066#define IOMUXD_EMMC0_CMD_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_lp_config_SHIFT)) & IOMUXD_EMMC0_CMD_lp_config_MASK)
53067#define IOMUXD_EMMC0_CMD_sw_config_MASK (0x6000000U)
53068#define IOMUXD_EMMC0_CMD_sw_config_SHIFT (25U)
53069/*! sw_config - output and input configuration
53070 * 0b01..OPEN_DRAIN
53071 * 0b10..OPEN_DRAIN_INPUT
53072 * 0b11..INOUT
53073 * 0b00..DEFAULT
53074 */
53075#define IOMUXD_EMMC0_CMD_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_sw_config_SHIFT)) & IOMUXD_EMMC0_CMD_sw_config_MASK)
53076#define IOMUXD_EMMC0_CMD_mux_mode_MASK (0x38000000U)
53077#define IOMUXD_EMMC0_CMD_mux_mode_SHIFT (27U)
53078/*! mux_mode - mux_mode
53079 * 0b000..CONN.EMMC0.CMD
53080 * 0b001..CONN.NAND.DQS
53081 * 0b100..LSIO.GPIO4.IO08
53082 */
53083#define IOMUXD_EMMC0_CMD_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_mux_mode_SHIFT)) & IOMUXD_EMMC0_CMD_mux_mode_MASK)
53084#define IOMUXD_EMMC0_CMD_update_pad_ctl_MASK (0x40000000U)
53085#define IOMUXD_EMMC0_CMD_update_pad_ctl_SHIFT (30U)
53086/*! update_pad_ctl - update lock for pad control
53087 */
53088#define IOMUXD_EMMC0_CMD_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_CMD_update_pad_ctl_MASK)
53089#define IOMUXD_EMMC0_CMD_update_mux_mode_MASK (0x80000000U)
53090#define IOMUXD_EMMC0_CMD_update_mux_mode_SHIFT (31U)
53091/*! update_mux_mode - update lock for mux control
53092 */
53093#define IOMUXD_EMMC0_CMD_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_CMD_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_CMD_update_mux_mode_MASK)
53094/*! @} */
53095
53096/*! @name EMMC0_DATA0 - EMMC0_DATA0 */
53097/*! @{ */
53098#define IOMUXD_EMMC0_DATA0_PDRV_MASK (0x1U)
53099#define IOMUXD_EMMC0_DATA0_PDRV_SHIFT (0U)
53100/*! PDRV - Drive
53101 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
53102 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
53103 */
53104#define IOMUXD_EMMC0_DATA0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA0_PDRV_MASK)
53105#define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_1_4_MASK (0x1EU)
53106#define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_1_4_SHIFT (1U)
53107/*! EMMC0_DATA0_reserved_1_4 - reserved
53108 */
53109#define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_1_4_MASK)
53110#define IOMUXD_EMMC0_DATA0_PULL_MASK (0x60U)
53111#define IOMUXD_EMMC0_DATA0_PULL_SHIFT (5U)
53112/*! PULL - Pull Down Pull Up
53113 * 0b10..pull down
53114 * 0b01..pull up
53115 * 0b00..Prohibited
53116 * 0b11..pull disabled
53117 */
53118#define IOMUXD_EMMC0_DATA0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_PULL_SHIFT)) & IOMUXD_EMMC0_DATA0_PULL_MASK)
53119#define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_7_18_MASK (0x7FF80U)
53120#define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_7_18_SHIFT (7U)
53121/*! EMMC0_DATA0_reserved_7_18 - reserved
53122 */
53123#define IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA0_EMMC0_DATA0_reserved_7_18_MASK)
53124#define IOMUXD_EMMC0_DATA0_WAKEUP_CTRL_MASK (0x380000U)
53125#define IOMUXD_EMMC0_DATA0_WAKEUP_CTRL_SHIFT (19U)
53126/*! WAKEUP_CTRL - wakeup control
53127 * 0b000..OFF
53128 * 0b001..RESAMPLE
53129 * 0b100..LOW
53130 * 0b111..HIGH
53131 * 0b110..RISE
53132 * 0b101..FALL
53133 */
53134#define IOMUXD_EMMC0_DATA0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA0_WAKEUP_CTRL_MASK)
53135#define IOMUXD_EMMC0_DATA0_WAKEUP_MASK_MASK (0x400000U)
53136#define IOMUXD_EMMC0_DATA0_WAKEUP_MASK_SHIFT (22U)
53137/*! WAKEUP_MASK - wakeup mask
53138 */
53139#define IOMUXD_EMMC0_DATA0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA0_WAKEUP_MASK_MASK)
53140#define IOMUXD_EMMC0_DATA0_lp_config_MASK (0x1800000U)
53141#define IOMUXD_EMMC0_DATA0_lp_config_SHIFT (23U)
53142/*! lp_config - lower power configuration
53143 * 0b01..EARLY_ISO
53144 * 0b10..LATE_ISO
53145 * 0b11..LATCH
53146 * 0b00..PASS
53147 */
53148#define IOMUXD_EMMC0_DATA0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA0_lp_config_MASK)
53149#define IOMUXD_EMMC0_DATA0_sw_config_MASK (0x6000000U)
53150#define IOMUXD_EMMC0_DATA0_sw_config_SHIFT (25U)
53151/*! sw_config - output and input configuration
53152 * 0b01..OPEN_DRAIN
53153 * 0b10..OPEN_DRAIN_INPUT
53154 * 0b11..INOUT
53155 * 0b00..DEFAULT
53156 */
53157#define IOMUXD_EMMC0_DATA0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA0_sw_config_MASK)
53158#define IOMUXD_EMMC0_DATA0_mux_mode_MASK (0x38000000U)
53159#define IOMUXD_EMMC0_DATA0_mux_mode_SHIFT (27U)
53160/*! mux_mode - mux_mode
53161 * 0b000..CONN.EMMC0.DATA0
53162 * 0b001..CONN.NAND.DATA00
53163 * 0b100..LSIO.GPIO4.IO09
53164 */
53165#define IOMUXD_EMMC0_DATA0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA0_mux_mode_MASK)
53166#define IOMUXD_EMMC0_DATA0_update_pad_ctl_MASK (0x40000000U)
53167#define IOMUXD_EMMC0_DATA0_update_pad_ctl_SHIFT (30U)
53168/*! update_pad_ctl - update lock for pad control
53169 */
53170#define IOMUXD_EMMC0_DATA0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA0_update_pad_ctl_MASK)
53171#define IOMUXD_EMMC0_DATA0_update_mux_mode_MASK (0x80000000U)
53172#define IOMUXD_EMMC0_DATA0_update_mux_mode_SHIFT (31U)
53173/*! update_mux_mode - update lock for mux control
53174 */
53175#define IOMUXD_EMMC0_DATA0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA0_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA0_update_mux_mode_MASK)
53176/*! @} */
53177
53178/*! @name EMMC0_DATA1 - EMMC0_DATA1 */
53179/*! @{ */
53180#define IOMUXD_EMMC0_DATA1_PDRV_MASK (0x1U)
53181#define IOMUXD_EMMC0_DATA1_PDRV_SHIFT (0U)
53182/*! PDRV - Drive
53183 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
53184 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
53185 */
53186#define IOMUXD_EMMC0_DATA1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA1_PDRV_MASK)
53187#define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_1_4_MASK (0x1EU)
53188#define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_1_4_SHIFT (1U)
53189/*! EMMC0_DATA1_reserved_1_4 - reserved
53190 */
53191#define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_1_4_MASK)
53192#define IOMUXD_EMMC0_DATA1_PULL_MASK (0x60U)
53193#define IOMUXD_EMMC0_DATA1_PULL_SHIFT (5U)
53194/*! PULL - Pull Down Pull Up
53195 * 0b10..pull down
53196 * 0b01..pull up
53197 * 0b00..Prohibited
53198 * 0b11..pull disabled
53199 */
53200#define IOMUXD_EMMC0_DATA1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_PULL_SHIFT)) & IOMUXD_EMMC0_DATA1_PULL_MASK)
53201#define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_7_18_MASK (0x7FF80U)
53202#define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_7_18_SHIFT (7U)
53203/*! EMMC0_DATA1_reserved_7_18 - reserved
53204 */
53205#define IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA1_EMMC0_DATA1_reserved_7_18_MASK)
53206#define IOMUXD_EMMC0_DATA1_WAKEUP_CTRL_MASK (0x380000U)
53207#define IOMUXD_EMMC0_DATA1_WAKEUP_CTRL_SHIFT (19U)
53208/*! WAKEUP_CTRL - wakeup control
53209 * 0b000..OFF
53210 * 0b001..RESAMPLE
53211 * 0b100..LOW
53212 * 0b111..HIGH
53213 * 0b110..RISE
53214 * 0b101..FALL
53215 */
53216#define IOMUXD_EMMC0_DATA1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA1_WAKEUP_CTRL_MASK)
53217#define IOMUXD_EMMC0_DATA1_WAKEUP_MASK_MASK (0x400000U)
53218#define IOMUXD_EMMC0_DATA1_WAKEUP_MASK_SHIFT (22U)
53219/*! WAKEUP_MASK - wakeup mask
53220 */
53221#define IOMUXD_EMMC0_DATA1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA1_WAKEUP_MASK_MASK)
53222#define IOMUXD_EMMC0_DATA1_lp_config_MASK (0x1800000U)
53223#define IOMUXD_EMMC0_DATA1_lp_config_SHIFT (23U)
53224/*! lp_config - lower power configuration
53225 * 0b01..EARLY_ISO
53226 * 0b10..LATE_ISO
53227 * 0b11..LATCH
53228 * 0b00..PASS
53229 */
53230#define IOMUXD_EMMC0_DATA1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA1_lp_config_MASK)
53231#define IOMUXD_EMMC0_DATA1_sw_config_MASK (0x6000000U)
53232#define IOMUXD_EMMC0_DATA1_sw_config_SHIFT (25U)
53233/*! sw_config - output and input configuration
53234 * 0b01..OPEN_DRAIN
53235 * 0b10..OPEN_DRAIN_INPUT
53236 * 0b11..INOUT
53237 * 0b00..DEFAULT
53238 */
53239#define IOMUXD_EMMC0_DATA1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA1_sw_config_MASK)
53240#define IOMUXD_EMMC0_DATA1_mux_mode_MASK (0x38000000U)
53241#define IOMUXD_EMMC0_DATA1_mux_mode_SHIFT (27U)
53242/*! mux_mode - mux_mode
53243 * 0b000..CONN.EMMC0.DATA1
53244 * 0b001..CONN.NAND.DATA01
53245 * 0b100..LSIO.GPIO4.IO10
53246 */
53247#define IOMUXD_EMMC0_DATA1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA1_mux_mode_MASK)
53248#define IOMUXD_EMMC0_DATA1_update_pad_ctl_MASK (0x40000000U)
53249#define IOMUXD_EMMC0_DATA1_update_pad_ctl_SHIFT (30U)
53250/*! update_pad_ctl - update lock for pad control
53251 */
53252#define IOMUXD_EMMC0_DATA1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA1_update_pad_ctl_MASK)
53253#define IOMUXD_EMMC0_DATA1_update_mux_mode_MASK (0x80000000U)
53254#define IOMUXD_EMMC0_DATA1_update_mux_mode_SHIFT (31U)
53255/*! update_mux_mode - update lock for mux control
53256 */
53257#define IOMUXD_EMMC0_DATA1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA1_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA1_update_mux_mode_MASK)
53258/*! @} */
53259
53260/*! @name EMMC0_DATA2 - EMMC0_DATA2 */
53261/*! @{ */
53262#define IOMUXD_EMMC0_DATA2_PDRV_MASK (0x1U)
53263#define IOMUXD_EMMC0_DATA2_PDRV_SHIFT (0U)
53264/*! PDRV - Drive
53265 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
53266 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
53267 */
53268#define IOMUXD_EMMC0_DATA2_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA2_PDRV_MASK)
53269#define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_1_4_MASK (0x1EU)
53270#define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_1_4_SHIFT (1U)
53271/*! EMMC0_DATA2_reserved_1_4 - reserved
53272 */
53273#define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_1_4_MASK)
53274#define IOMUXD_EMMC0_DATA2_PULL_MASK (0x60U)
53275#define IOMUXD_EMMC0_DATA2_PULL_SHIFT (5U)
53276/*! PULL - Pull Down Pull Up
53277 * 0b10..pull down
53278 * 0b01..pull up
53279 * 0b00..Prohibited
53280 * 0b11..pull disabled
53281 */
53282#define IOMUXD_EMMC0_DATA2_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_PULL_SHIFT)) & IOMUXD_EMMC0_DATA2_PULL_MASK)
53283#define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_7_18_MASK (0x7FF80U)
53284#define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_7_18_SHIFT (7U)
53285/*! EMMC0_DATA2_reserved_7_18 - reserved
53286 */
53287#define IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA2_EMMC0_DATA2_reserved_7_18_MASK)
53288#define IOMUXD_EMMC0_DATA2_WAKEUP_CTRL_MASK (0x380000U)
53289#define IOMUXD_EMMC0_DATA2_WAKEUP_CTRL_SHIFT (19U)
53290/*! WAKEUP_CTRL - wakeup control
53291 * 0b000..OFF
53292 * 0b001..RESAMPLE
53293 * 0b100..LOW
53294 * 0b111..HIGH
53295 * 0b110..RISE
53296 * 0b101..FALL
53297 */
53298#define IOMUXD_EMMC0_DATA2_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA2_WAKEUP_CTRL_MASK)
53299#define IOMUXD_EMMC0_DATA2_WAKEUP_MASK_MASK (0x400000U)
53300#define IOMUXD_EMMC0_DATA2_WAKEUP_MASK_SHIFT (22U)
53301/*! WAKEUP_MASK - wakeup mask
53302 */
53303#define IOMUXD_EMMC0_DATA2_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA2_WAKEUP_MASK_MASK)
53304#define IOMUXD_EMMC0_DATA2_lp_config_MASK (0x1800000U)
53305#define IOMUXD_EMMC0_DATA2_lp_config_SHIFT (23U)
53306/*! lp_config - lower power configuration
53307 * 0b01..EARLY_ISO
53308 * 0b10..LATE_ISO
53309 * 0b11..LATCH
53310 * 0b00..PASS
53311 */
53312#define IOMUXD_EMMC0_DATA2_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA2_lp_config_MASK)
53313#define IOMUXD_EMMC0_DATA2_sw_config_MASK (0x6000000U)
53314#define IOMUXD_EMMC0_DATA2_sw_config_SHIFT (25U)
53315/*! sw_config - output and input configuration
53316 * 0b01..OPEN_DRAIN
53317 * 0b10..OPEN_DRAIN_INPUT
53318 * 0b11..INOUT
53319 * 0b00..DEFAULT
53320 */
53321#define IOMUXD_EMMC0_DATA2_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA2_sw_config_MASK)
53322#define IOMUXD_EMMC0_DATA2_mux_mode_MASK (0x38000000U)
53323#define IOMUXD_EMMC0_DATA2_mux_mode_SHIFT (27U)
53324/*! mux_mode - mux_mode
53325 * 0b000..CONN.EMMC0.DATA2
53326 * 0b001..CONN.NAND.DATA02
53327 * 0b100..LSIO.GPIO4.IO11
53328 */
53329#define IOMUXD_EMMC0_DATA2_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA2_mux_mode_MASK)
53330#define IOMUXD_EMMC0_DATA2_update_pad_ctl_MASK (0x40000000U)
53331#define IOMUXD_EMMC0_DATA2_update_pad_ctl_SHIFT (30U)
53332/*! update_pad_ctl - update lock for pad control
53333 */
53334#define IOMUXD_EMMC0_DATA2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA2_update_pad_ctl_MASK)
53335#define IOMUXD_EMMC0_DATA2_update_mux_mode_MASK (0x80000000U)
53336#define IOMUXD_EMMC0_DATA2_update_mux_mode_SHIFT (31U)
53337/*! update_mux_mode - update lock for mux control
53338 */
53339#define IOMUXD_EMMC0_DATA2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA2_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA2_update_mux_mode_MASK)
53340/*! @} */
53341
53342/*! @name EMMC0_DATA3 - EMMC0_DATA3 */
53343/*! @{ */
53344#define IOMUXD_EMMC0_DATA3_PDRV_MASK (0x1U)
53345#define IOMUXD_EMMC0_DATA3_PDRV_SHIFT (0U)
53346/*! PDRV - Drive
53347 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
53348 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
53349 */
53350#define IOMUXD_EMMC0_DATA3_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA3_PDRV_MASK)
53351#define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_1_4_MASK (0x1EU)
53352#define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_1_4_SHIFT (1U)
53353/*! EMMC0_DATA3_reserved_1_4 - reserved
53354 */
53355#define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_1_4_MASK)
53356#define IOMUXD_EMMC0_DATA3_PULL_MASK (0x60U)
53357#define IOMUXD_EMMC0_DATA3_PULL_SHIFT (5U)
53358/*! PULL - Pull Down Pull Up
53359 * 0b10..pull down
53360 * 0b01..pull up
53361 * 0b00..Prohibited
53362 * 0b11..pull disabled
53363 */
53364#define IOMUXD_EMMC0_DATA3_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_PULL_SHIFT)) & IOMUXD_EMMC0_DATA3_PULL_MASK)
53365#define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_7_18_MASK (0x7FF80U)
53366#define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_7_18_SHIFT (7U)
53367/*! EMMC0_DATA3_reserved_7_18 - reserved
53368 */
53369#define IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA3_EMMC0_DATA3_reserved_7_18_MASK)
53370#define IOMUXD_EMMC0_DATA3_WAKEUP_CTRL_MASK (0x380000U)
53371#define IOMUXD_EMMC0_DATA3_WAKEUP_CTRL_SHIFT (19U)
53372/*! WAKEUP_CTRL - wakeup control
53373 * 0b000..OFF
53374 * 0b001..RESAMPLE
53375 * 0b100..LOW
53376 * 0b111..HIGH
53377 * 0b110..RISE
53378 * 0b101..FALL
53379 */
53380#define IOMUXD_EMMC0_DATA3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA3_WAKEUP_CTRL_MASK)
53381#define IOMUXD_EMMC0_DATA3_WAKEUP_MASK_MASK (0x400000U)
53382#define IOMUXD_EMMC0_DATA3_WAKEUP_MASK_SHIFT (22U)
53383/*! WAKEUP_MASK - wakeup mask
53384 */
53385#define IOMUXD_EMMC0_DATA3_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA3_WAKEUP_MASK_MASK)
53386#define IOMUXD_EMMC0_DATA3_lp_config_MASK (0x1800000U)
53387#define IOMUXD_EMMC0_DATA3_lp_config_SHIFT (23U)
53388/*! lp_config - lower power configuration
53389 * 0b01..EARLY_ISO
53390 * 0b10..LATE_ISO
53391 * 0b11..LATCH
53392 * 0b00..PASS
53393 */
53394#define IOMUXD_EMMC0_DATA3_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA3_lp_config_MASK)
53395#define IOMUXD_EMMC0_DATA3_sw_config_MASK (0x6000000U)
53396#define IOMUXD_EMMC0_DATA3_sw_config_SHIFT (25U)
53397/*! sw_config - output and input configuration
53398 * 0b01..OPEN_DRAIN
53399 * 0b10..OPEN_DRAIN_INPUT
53400 * 0b11..INOUT
53401 * 0b00..DEFAULT
53402 */
53403#define IOMUXD_EMMC0_DATA3_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA3_sw_config_MASK)
53404#define IOMUXD_EMMC0_DATA3_mux_mode_MASK (0x38000000U)
53405#define IOMUXD_EMMC0_DATA3_mux_mode_SHIFT (27U)
53406/*! mux_mode - mux_mode
53407 * 0b000..CONN.EMMC0.DATA3
53408 * 0b001..CONN.NAND.DATA03
53409 * 0b100..LSIO.GPIO4.IO12
53410 */
53411#define IOMUXD_EMMC0_DATA3_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA3_mux_mode_MASK)
53412#define IOMUXD_EMMC0_DATA3_update_pad_ctl_MASK (0x40000000U)
53413#define IOMUXD_EMMC0_DATA3_update_pad_ctl_SHIFT (30U)
53414/*! update_pad_ctl - update lock for pad control
53415 */
53416#define IOMUXD_EMMC0_DATA3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA3_update_pad_ctl_MASK)
53417#define IOMUXD_EMMC0_DATA3_update_mux_mode_MASK (0x80000000U)
53418#define IOMUXD_EMMC0_DATA3_update_mux_mode_SHIFT (31U)
53419/*! update_mux_mode - update lock for mux control
53420 */
53421#define IOMUXD_EMMC0_DATA3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA3_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA3_update_mux_mode_MASK)
53422/*! @} */
53423
53424/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 - IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 */
53425/*! @{ */
53426#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMP_MASK (0x7U)
53427#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMP_SHIFT (0U)
53428/*! COMP - COMP
53429 * 0b010..Fixed code mode
53430 * 0b100..High impedance mode
53431 * 0b110..Read mode
53432 * 0b000..Normal Mode
53433 * 0b001..Freeze Mode
53434 */
53435#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMP_MASK)
53436#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_FASTFRZ_EN_MASK (0x8U)
53437#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_FASTFRZ_EN_SHIFT (3U)
53438/*! FASTFRZ_EN - FASTFRZ_EN
53439 * 0b1..FASTFRZ signal is driven by output of subsystem
53440 * 0b0..FASTFRZ signal is gated to 0
53441 */
53442#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_FASTFRZ_EN_MASK)
53443#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_4_4_MASK (0x10U)
53444#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_4_4_SHIFT (4U)
53445/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_4_4 - reserved
53446 */
53447#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_4_4_MASK)
53448#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCP_MASK (0x1E0U)
53449#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCP_SHIFT (5U)
53450/*! RASRCP - RASRCP
53451 * 0b0101..Reset Value
53452 */
53453#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCP_MASK)
53454#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCN_MASK (0x1E00U)
53455#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCN_SHIFT (9U)
53456/*! RASRCN - RASRCN
53457 * 0b1010..Reset Value
53458 */
53459#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_RASRCN_MASK)
53460#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SELECT_NASRC_MASK (0x2000U)
53461#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SELECT_NASRC_SHIFT (13U)
53462/*! SELECT_NASRC - SELECT_NASRC
53463 * 0b1..NASRCN value
53464 * 0b0..NASRCP value
53465 */
53466#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SELECT_NASRC_MASK)
53467#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMPOK_MASK (0x4000U)
53468#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMPOK_SHIFT (14U)
53469/*! COMPOK - COMPOK
53470 * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
53471 * 0b1..compensation cell in Normal mode and tracking PVT
53472 */
53473#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_COMPOK_MASK)
53474#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_READ_NASRC_MASK (0x78000U)
53475#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_READ_NASRC_SHIFT (15U)
53476/*! READ_NASRC - READ_NASRC
53477 * 0b0000..READ Only
53478 */
53479#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_READ_NASRC_MASK)
53480#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_19_22_MASK (0x780000U)
53481#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_19_22_SHIFT (19U)
53482/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_19_22 - reserved
53483 */
53484#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_19_22_MASK)
53485#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SLEEP_MASK (0x1800000U)
53486#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SLEEP_SHIFT (23U)
53487/*! SLEEP - SLEEP
53488 * 0b11..Force into sleep mode
53489 * 0b00..NO
53490 * 0b01..EARLY
53491 * 0b10..LATE
53492 */
53493#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_SLEEP_MASK)
53494#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_25_29_MASK (0x3E000000U)
53495#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_25_29_SHIFT (25U)
53496/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_25_29 - reserved
53497 */
53498#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_reserved_25_29_MASK)
53499#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_pad_ctl_MASK (0x40000000U)
53500#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_pad_ctl_SHIFT (30U)
53501/*! update_pad_ctl - update lock for pad control
53502 */
53503#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_pad_ctl_MASK)
53504#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_mux_mode_MASK (0x80000000U)
53505#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_mux_mode_SHIFT (31U)
53506/*! update_mux_mode - update lock for mux control
53507 */
53508#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_update_mux_mode_MASK)
53509/*! @} */
53510
53511/*! @name EMMC0_DATA4 - EMMC0_DATA4 */
53512/*! @{ */
53513#define IOMUXD_EMMC0_DATA4_PDRV_MASK (0x1U)
53514#define IOMUXD_EMMC0_DATA4_PDRV_SHIFT (0U)
53515/*! PDRV - Drive
53516 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
53517 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
53518 */
53519#define IOMUXD_EMMC0_DATA4_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA4_PDRV_MASK)
53520#define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_1_4_MASK (0x1EU)
53521#define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_1_4_SHIFT (1U)
53522/*! EMMC0_DATA4_reserved_1_4 - reserved
53523 */
53524#define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_1_4_MASK)
53525#define IOMUXD_EMMC0_DATA4_PULL_MASK (0x60U)
53526#define IOMUXD_EMMC0_DATA4_PULL_SHIFT (5U)
53527/*! PULL - Pull Down Pull Up
53528 * 0b10..pull down
53529 * 0b01..pull up
53530 * 0b00..Prohibited
53531 * 0b11..pull disabled
53532 */
53533#define IOMUXD_EMMC0_DATA4_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_PULL_SHIFT)) & IOMUXD_EMMC0_DATA4_PULL_MASK)
53534#define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_7_18_MASK (0x7FF80U)
53535#define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_7_18_SHIFT (7U)
53536/*! EMMC0_DATA4_reserved_7_18 - reserved
53537 */
53538#define IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA4_EMMC0_DATA4_reserved_7_18_MASK)
53539#define IOMUXD_EMMC0_DATA4_WAKEUP_CTRL_MASK (0x380000U)
53540#define IOMUXD_EMMC0_DATA4_WAKEUP_CTRL_SHIFT (19U)
53541/*! WAKEUP_CTRL - wakeup control
53542 * 0b000..OFF
53543 * 0b001..RESAMPLE
53544 * 0b100..LOW
53545 * 0b111..HIGH
53546 * 0b110..RISE
53547 * 0b101..FALL
53548 */
53549#define IOMUXD_EMMC0_DATA4_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA4_WAKEUP_CTRL_MASK)
53550#define IOMUXD_EMMC0_DATA4_WAKEUP_MASK_MASK (0x400000U)
53551#define IOMUXD_EMMC0_DATA4_WAKEUP_MASK_SHIFT (22U)
53552/*! WAKEUP_MASK - wakeup mask
53553 */
53554#define IOMUXD_EMMC0_DATA4_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA4_WAKEUP_MASK_MASK)
53555#define IOMUXD_EMMC0_DATA4_lp_config_MASK (0x1800000U)
53556#define IOMUXD_EMMC0_DATA4_lp_config_SHIFT (23U)
53557/*! lp_config - lower power configuration
53558 * 0b01..EARLY_ISO
53559 * 0b10..LATE_ISO
53560 * 0b11..LATCH
53561 * 0b00..PASS
53562 */
53563#define IOMUXD_EMMC0_DATA4_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA4_lp_config_MASK)
53564#define IOMUXD_EMMC0_DATA4_sw_config_MASK (0x6000000U)
53565#define IOMUXD_EMMC0_DATA4_sw_config_SHIFT (25U)
53566/*! sw_config - output and input configuration
53567 * 0b01..OPEN_DRAIN
53568 * 0b10..OPEN_DRAIN_INPUT
53569 * 0b11..INOUT
53570 * 0b00..DEFAULT
53571 */
53572#define IOMUXD_EMMC0_DATA4_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA4_sw_config_MASK)
53573#define IOMUXD_EMMC0_DATA4_mux_mode_MASK (0x38000000U)
53574#define IOMUXD_EMMC0_DATA4_mux_mode_SHIFT (27U)
53575/*! mux_mode - mux_mode
53576 * 0b000..CONN.EMMC0.DATA4
53577 * 0b001..CONN.NAND.DATA04
53578 * 0b011..CONN.EMMC0.WP
53579 * 0b100..LSIO.GPIO4.IO13
53580 */
53581#define IOMUXD_EMMC0_DATA4_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA4_mux_mode_MASK)
53582#define IOMUXD_EMMC0_DATA4_update_pad_ctl_MASK (0x40000000U)
53583#define IOMUXD_EMMC0_DATA4_update_pad_ctl_SHIFT (30U)
53584/*! update_pad_ctl - update lock for pad control
53585 */
53586#define IOMUXD_EMMC0_DATA4_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA4_update_pad_ctl_MASK)
53587#define IOMUXD_EMMC0_DATA4_update_mux_mode_MASK (0x80000000U)
53588#define IOMUXD_EMMC0_DATA4_update_mux_mode_SHIFT (31U)
53589/*! update_mux_mode - update lock for mux control
53590 */
53591#define IOMUXD_EMMC0_DATA4_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA4_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA4_update_mux_mode_MASK)
53592/*! @} */
53593
53594/*! @name EMMC0_DATA5 - EMMC0_DATA5 */
53595/*! @{ */
53596#define IOMUXD_EMMC0_DATA5_PDRV_MASK (0x1U)
53597#define IOMUXD_EMMC0_DATA5_PDRV_SHIFT (0U)
53598/*! PDRV - Drive
53599 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
53600 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
53601 */
53602#define IOMUXD_EMMC0_DATA5_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA5_PDRV_MASK)
53603#define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_1_4_MASK (0x1EU)
53604#define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_1_4_SHIFT (1U)
53605/*! EMMC0_DATA5_reserved_1_4 - reserved
53606 */
53607#define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_1_4_MASK)
53608#define IOMUXD_EMMC0_DATA5_PULL_MASK (0x60U)
53609#define IOMUXD_EMMC0_DATA5_PULL_SHIFT (5U)
53610/*! PULL - Pull Down Pull Up
53611 * 0b10..pull down
53612 * 0b01..pull up
53613 * 0b00..Prohibited
53614 * 0b11..pull disabled
53615 */
53616#define IOMUXD_EMMC0_DATA5_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_PULL_SHIFT)) & IOMUXD_EMMC0_DATA5_PULL_MASK)
53617#define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_7_18_MASK (0x7FF80U)
53618#define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_7_18_SHIFT (7U)
53619/*! EMMC0_DATA5_reserved_7_18 - reserved
53620 */
53621#define IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA5_EMMC0_DATA5_reserved_7_18_MASK)
53622#define IOMUXD_EMMC0_DATA5_WAKEUP_CTRL_MASK (0x380000U)
53623#define IOMUXD_EMMC0_DATA5_WAKEUP_CTRL_SHIFT (19U)
53624/*! WAKEUP_CTRL - wakeup control
53625 * 0b000..OFF
53626 * 0b001..RESAMPLE
53627 * 0b100..LOW
53628 * 0b111..HIGH
53629 * 0b110..RISE
53630 * 0b101..FALL
53631 */
53632#define IOMUXD_EMMC0_DATA5_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA5_WAKEUP_CTRL_MASK)
53633#define IOMUXD_EMMC0_DATA5_WAKEUP_MASK_MASK (0x400000U)
53634#define IOMUXD_EMMC0_DATA5_WAKEUP_MASK_SHIFT (22U)
53635/*! WAKEUP_MASK - wakeup mask
53636 */
53637#define IOMUXD_EMMC0_DATA5_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA5_WAKEUP_MASK_MASK)
53638#define IOMUXD_EMMC0_DATA5_lp_config_MASK (0x1800000U)
53639#define IOMUXD_EMMC0_DATA5_lp_config_SHIFT (23U)
53640/*! lp_config - lower power configuration
53641 * 0b01..EARLY_ISO
53642 * 0b10..LATE_ISO
53643 * 0b11..LATCH
53644 * 0b00..PASS
53645 */
53646#define IOMUXD_EMMC0_DATA5_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA5_lp_config_MASK)
53647#define IOMUXD_EMMC0_DATA5_sw_config_MASK (0x6000000U)
53648#define IOMUXD_EMMC0_DATA5_sw_config_SHIFT (25U)
53649/*! sw_config - output and input configuration
53650 * 0b01..OPEN_DRAIN
53651 * 0b10..OPEN_DRAIN_INPUT
53652 * 0b11..INOUT
53653 * 0b00..DEFAULT
53654 */
53655#define IOMUXD_EMMC0_DATA5_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA5_sw_config_MASK)
53656#define IOMUXD_EMMC0_DATA5_mux_mode_MASK (0x38000000U)
53657#define IOMUXD_EMMC0_DATA5_mux_mode_SHIFT (27U)
53658/*! mux_mode - mux_mode
53659 * 0b000..CONN.EMMC0.DATA5
53660 * 0b001..CONN.NAND.DATA05
53661 * 0b011..CONN.EMMC0.VSELECT
53662 * 0b100..LSIO.GPIO4.IO14
53663 */
53664#define IOMUXD_EMMC0_DATA5_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA5_mux_mode_MASK)
53665#define IOMUXD_EMMC0_DATA5_update_pad_ctl_MASK (0x40000000U)
53666#define IOMUXD_EMMC0_DATA5_update_pad_ctl_SHIFT (30U)
53667/*! update_pad_ctl - update lock for pad control
53668 */
53669#define IOMUXD_EMMC0_DATA5_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA5_update_pad_ctl_MASK)
53670#define IOMUXD_EMMC0_DATA5_update_mux_mode_MASK (0x80000000U)
53671#define IOMUXD_EMMC0_DATA5_update_mux_mode_SHIFT (31U)
53672/*! update_mux_mode - update lock for mux control
53673 */
53674#define IOMUXD_EMMC0_DATA5_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA5_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA5_update_mux_mode_MASK)
53675/*! @} */
53676
53677/*! @name EMMC0_DATA6 - EMMC0_DATA6 */
53678/*! @{ */
53679#define IOMUXD_EMMC0_DATA6_PDRV_MASK (0x1U)
53680#define IOMUXD_EMMC0_DATA6_PDRV_SHIFT (0U)
53681/*! PDRV - Drive
53682 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
53683 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
53684 */
53685#define IOMUXD_EMMC0_DATA6_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA6_PDRV_MASK)
53686#define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_1_4_MASK (0x1EU)
53687#define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_1_4_SHIFT (1U)
53688/*! EMMC0_DATA6_reserved_1_4 - reserved
53689 */
53690#define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_1_4_MASK)
53691#define IOMUXD_EMMC0_DATA6_PULL_MASK (0x60U)
53692#define IOMUXD_EMMC0_DATA6_PULL_SHIFT (5U)
53693/*! PULL - Pull Down Pull Up
53694 * 0b10..pull down
53695 * 0b01..pull up
53696 * 0b00..Prohibited
53697 * 0b11..pull disabled
53698 */
53699#define IOMUXD_EMMC0_DATA6_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_PULL_SHIFT)) & IOMUXD_EMMC0_DATA6_PULL_MASK)
53700#define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_7_18_MASK (0x7FF80U)
53701#define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_7_18_SHIFT (7U)
53702/*! EMMC0_DATA6_reserved_7_18 - reserved
53703 */
53704#define IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA6_EMMC0_DATA6_reserved_7_18_MASK)
53705#define IOMUXD_EMMC0_DATA6_WAKEUP_CTRL_MASK (0x380000U)
53706#define IOMUXD_EMMC0_DATA6_WAKEUP_CTRL_SHIFT (19U)
53707/*! WAKEUP_CTRL - wakeup control
53708 * 0b000..OFF
53709 * 0b001..RESAMPLE
53710 * 0b100..LOW
53711 * 0b111..HIGH
53712 * 0b110..RISE
53713 * 0b101..FALL
53714 */
53715#define IOMUXD_EMMC0_DATA6_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA6_WAKEUP_CTRL_MASK)
53716#define IOMUXD_EMMC0_DATA6_WAKEUP_MASK_MASK (0x400000U)
53717#define IOMUXD_EMMC0_DATA6_WAKEUP_MASK_SHIFT (22U)
53718/*! WAKEUP_MASK - wakeup mask
53719 */
53720#define IOMUXD_EMMC0_DATA6_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA6_WAKEUP_MASK_MASK)
53721#define IOMUXD_EMMC0_DATA6_lp_config_MASK (0x1800000U)
53722#define IOMUXD_EMMC0_DATA6_lp_config_SHIFT (23U)
53723/*! lp_config - lower power configuration
53724 * 0b01..EARLY_ISO
53725 * 0b10..LATE_ISO
53726 * 0b11..LATCH
53727 * 0b00..PASS
53728 */
53729#define IOMUXD_EMMC0_DATA6_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA6_lp_config_MASK)
53730#define IOMUXD_EMMC0_DATA6_sw_config_MASK (0x6000000U)
53731#define IOMUXD_EMMC0_DATA6_sw_config_SHIFT (25U)
53732/*! sw_config - output and input configuration
53733 * 0b01..OPEN_DRAIN
53734 * 0b10..OPEN_DRAIN_INPUT
53735 * 0b11..INOUT
53736 * 0b00..DEFAULT
53737 */
53738#define IOMUXD_EMMC0_DATA6_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA6_sw_config_MASK)
53739#define IOMUXD_EMMC0_DATA6_mux_mode_MASK (0x38000000U)
53740#define IOMUXD_EMMC0_DATA6_mux_mode_SHIFT (27U)
53741/*! mux_mode - mux_mode
53742 * 0b000..CONN.EMMC0.DATA6
53743 * 0b001..CONN.NAND.DATA06
53744 * 0b011..CONN.MLB.CLK
53745 * 0b100..LSIO.GPIO4.IO15
53746 */
53747#define IOMUXD_EMMC0_DATA6_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA6_mux_mode_MASK)
53748#define IOMUXD_EMMC0_DATA6_update_pad_ctl_MASK (0x40000000U)
53749#define IOMUXD_EMMC0_DATA6_update_pad_ctl_SHIFT (30U)
53750/*! update_pad_ctl - update lock for pad control
53751 */
53752#define IOMUXD_EMMC0_DATA6_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA6_update_pad_ctl_MASK)
53753#define IOMUXD_EMMC0_DATA6_update_mux_mode_MASK (0x80000000U)
53754#define IOMUXD_EMMC0_DATA6_update_mux_mode_SHIFT (31U)
53755/*! update_mux_mode - update lock for mux control
53756 */
53757#define IOMUXD_EMMC0_DATA6_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA6_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA6_update_mux_mode_MASK)
53758/*! @} */
53759
53760/*! @name EMMC0_DATA7 - EMMC0_DATA7 */
53761/*! @{ */
53762#define IOMUXD_EMMC0_DATA7_PDRV_MASK (0x1U)
53763#define IOMUXD_EMMC0_DATA7_PDRV_SHIFT (0U)
53764/*! PDRV - Drive
53765 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
53766 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
53767 */
53768#define IOMUXD_EMMC0_DATA7_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_PDRV_SHIFT)) & IOMUXD_EMMC0_DATA7_PDRV_MASK)
53769#define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_1_4_MASK (0x1EU)
53770#define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_1_4_SHIFT (1U)
53771/*! EMMC0_DATA7_reserved_1_4 - reserved
53772 */
53773#define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_1_4_MASK)
53774#define IOMUXD_EMMC0_DATA7_PULL_MASK (0x60U)
53775#define IOMUXD_EMMC0_DATA7_PULL_SHIFT (5U)
53776/*! PULL - Pull Down Pull Up
53777 * 0b10..pull down
53778 * 0b01..pull up
53779 * 0b00..Prohibited
53780 * 0b11..pull disabled
53781 */
53782#define IOMUXD_EMMC0_DATA7_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_PULL_SHIFT)) & IOMUXD_EMMC0_DATA7_PULL_MASK)
53783#define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_7_18_MASK (0x7FF80U)
53784#define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_7_18_SHIFT (7U)
53785/*! EMMC0_DATA7_reserved_7_18 - reserved
53786 */
53787#define IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_DATA7_EMMC0_DATA7_reserved_7_18_MASK)
53788#define IOMUXD_EMMC0_DATA7_WAKEUP_CTRL_MASK (0x380000U)
53789#define IOMUXD_EMMC0_DATA7_WAKEUP_CTRL_SHIFT (19U)
53790/*! WAKEUP_CTRL - wakeup control
53791 * 0b000..OFF
53792 * 0b001..RESAMPLE
53793 * 0b100..LOW
53794 * 0b111..HIGH
53795 * 0b110..RISE
53796 * 0b101..FALL
53797 */
53798#define IOMUXD_EMMC0_DATA7_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_DATA7_WAKEUP_CTRL_MASK)
53799#define IOMUXD_EMMC0_DATA7_WAKEUP_MASK_MASK (0x400000U)
53800#define IOMUXD_EMMC0_DATA7_WAKEUP_MASK_SHIFT (22U)
53801/*! WAKEUP_MASK - wakeup mask
53802 */
53803#define IOMUXD_EMMC0_DATA7_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_DATA7_WAKEUP_MASK_MASK)
53804#define IOMUXD_EMMC0_DATA7_lp_config_MASK (0x1800000U)
53805#define IOMUXD_EMMC0_DATA7_lp_config_SHIFT (23U)
53806/*! lp_config - lower power configuration
53807 * 0b01..EARLY_ISO
53808 * 0b10..LATE_ISO
53809 * 0b11..LATCH
53810 * 0b00..PASS
53811 */
53812#define IOMUXD_EMMC0_DATA7_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_lp_config_SHIFT)) & IOMUXD_EMMC0_DATA7_lp_config_MASK)
53813#define IOMUXD_EMMC0_DATA7_sw_config_MASK (0x6000000U)
53814#define IOMUXD_EMMC0_DATA7_sw_config_SHIFT (25U)
53815/*! sw_config - output and input configuration
53816 * 0b01..OPEN_DRAIN
53817 * 0b10..OPEN_DRAIN_INPUT
53818 * 0b11..INOUT
53819 * 0b00..DEFAULT
53820 */
53821#define IOMUXD_EMMC0_DATA7_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_sw_config_SHIFT)) & IOMUXD_EMMC0_DATA7_sw_config_MASK)
53822#define IOMUXD_EMMC0_DATA7_mux_mode_MASK (0x38000000U)
53823#define IOMUXD_EMMC0_DATA7_mux_mode_SHIFT (27U)
53824/*! mux_mode - mux_mode
53825 * 0b000..CONN.EMMC0.DATA7
53826 * 0b001..CONN.NAND.DATA07
53827 * 0b011..CONN.MLB.SIG
53828 * 0b100..LSIO.GPIO4.IO16
53829 */
53830#define IOMUXD_EMMC0_DATA7_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA7_mux_mode_MASK)
53831#define IOMUXD_EMMC0_DATA7_update_pad_ctl_MASK (0x40000000U)
53832#define IOMUXD_EMMC0_DATA7_update_pad_ctl_SHIFT (30U)
53833/*! update_pad_ctl - update lock for pad control
53834 */
53835#define IOMUXD_EMMC0_DATA7_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_DATA7_update_pad_ctl_MASK)
53836#define IOMUXD_EMMC0_DATA7_update_mux_mode_MASK (0x80000000U)
53837#define IOMUXD_EMMC0_DATA7_update_mux_mode_SHIFT (31U)
53838/*! update_mux_mode - update lock for mux control
53839 */
53840#define IOMUXD_EMMC0_DATA7_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_DATA7_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_DATA7_update_mux_mode_MASK)
53841/*! @} */
53842
53843/*! @name EMMC0_STROBE - EMMC0_STROBE */
53844/*! @{ */
53845#define IOMUXD_EMMC0_STROBE_PDRV_MASK (0x1U)
53846#define IOMUXD_EMMC0_STROBE_PDRV_SHIFT (0U)
53847/*! PDRV - Drive
53848 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
53849 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
53850 */
53851#define IOMUXD_EMMC0_STROBE_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_PDRV_SHIFT)) & IOMUXD_EMMC0_STROBE_PDRV_MASK)
53852#define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_1_4_MASK (0x1EU)
53853#define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_1_4_SHIFT (1U)
53854/*! EMMC0_STROBE_reserved_1_4 - reserved
53855 */
53856#define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_1_4_MASK)
53857#define IOMUXD_EMMC0_STROBE_PULL_MASK (0x60U)
53858#define IOMUXD_EMMC0_STROBE_PULL_SHIFT (5U)
53859/*! PULL - Pull Down Pull Up
53860 * 0b10..pull down
53861 * 0b01..pull up
53862 * 0b00..Prohibited
53863 * 0b11..pull disabled
53864 */
53865#define IOMUXD_EMMC0_STROBE_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_PULL_SHIFT)) & IOMUXD_EMMC0_STROBE_PULL_MASK)
53866#define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_7_18_MASK (0x7FF80U)
53867#define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_7_18_SHIFT (7U)
53868/*! EMMC0_STROBE_reserved_7_18 - reserved
53869 */
53870#define IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_STROBE_EMMC0_STROBE_reserved_7_18_MASK)
53871#define IOMUXD_EMMC0_STROBE_WAKEUP_CTRL_MASK (0x380000U)
53872#define IOMUXD_EMMC0_STROBE_WAKEUP_CTRL_SHIFT (19U)
53873/*! WAKEUP_CTRL - wakeup control
53874 * 0b000..OFF
53875 * 0b001..RESAMPLE
53876 * 0b100..LOW
53877 * 0b111..HIGH
53878 * 0b110..RISE
53879 * 0b101..FALL
53880 */
53881#define IOMUXD_EMMC0_STROBE_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_STROBE_WAKEUP_CTRL_MASK)
53882#define IOMUXD_EMMC0_STROBE_WAKEUP_MASK_MASK (0x400000U)
53883#define IOMUXD_EMMC0_STROBE_WAKEUP_MASK_SHIFT (22U)
53884/*! WAKEUP_MASK - wakeup mask
53885 */
53886#define IOMUXD_EMMC0_STROBE_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_STROBE_WAKEUP_MASK_MASK)
53887#define IOMUXD_EMMC0_STROBE_lp_config_MASK (0x1800000U)
53888#define IOMUXD_EMMC0_STROBE_lp_config_SHIFT (23U)
53889/*! lp_config - lower power configuration
53890 * 0b01..EARLY_ISO
53891 * 0b10..LATE_ISO
53892 * 0b11..LATCH
53893 * 0b00..PASS
53894 */
53895#define IOMUXD_EMMC0_STROBE_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_lp_config_SHIFT)) & IOMUXD_EMMC0_STROBE_lp_config_MASK)
53896#define IOMUXD_EMMC0_STROBE_sw_config_MASK (0x6000000U)
53897#define IOMUXD_EMMC0_STROBE_sw_config_SHIFT (25U)
53898/*! sw_config - output and input configuration
53899 * 0b01..OPEN_DRAIN
53900 * 0b10..OPEN_DRAIN_INPUT
53901 * 0b11..INOUT
53902 * 0b00..DEFAULT
53903 */
53904#define IOMUXD_EMMC0_STROBE_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_sw_config_SHIFT)) & IOMUXD_EMMC0_STROBE_sw_config_MASK)
53905#define IOMUXD_EMMC0_STROBE_mux_mode_MASK (0x38000000U)
53906#define IOMUXD_EMMC0_STROBE_mux_mode_SHIFT (27U)
53907/*! mux_mode - mux_mode
53908 * 0b000..CONN.EMMC0.STROBE
53909 * 0b001..CONN.NAND.CLE
53910 * 0b011..CONN.MLB.DATA
53911 * 0b100..LSIO.GPIO4.IO17
53912 */
53913#define IOMUXD_EMMC0_STROBE_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_mux_mode_SHIFT)) & IOMUXD_EMMC0_STROBE_mux_mode_MASK)
53914#define IOMUXD_EMMC0_STROBE_update_pad_ctl_MASK (0x40000000U)
53915#define IOMUXD_EMMC0_STROBE_update_pad_ctl_SHIFT (30U)
53916/*! update_pad_ctl - update lock for pad control
53917 */
53918#define IOMUXD_EMMC0_STROBE_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_STROBE_update_pad_ctl_MASK)
53919#define IOMUXD_EMMC0_STROBE_update_mux_mode_MASK (0x80000000U)
53920#define IOMUXD_EMMC0_STROBE_update_mux_mode_SHIFT (31U)
53921/*! update_mux_mode - update lock for mux control
53922 */
53923#define IOMUXD_EMMC0_STROBE_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_STROBE_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_STROBE_update_mux_mode_MASK)
53924/*! @} */
53925
53926/*! @name EMMC0_RESET_B - EMMC0_RESET_B */
53927/*! @{ */
53928#define IOMUXD_EMMC0_RESET_B_PDRV_MASK (0x1U)
53929#define IOMUXD_EMMC0_RESET_B_PDRV_SHIFT (0U)
53930/*! PDRV - Drive
53931 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
53932 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
53933 */
53934#define IOMUXD_EMMC0_RESET_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_PDRV_SHIFT)) & IOMUXD_EMMC0_RESET_B_PDRV_MASK)
53935#define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_1_4_MASK (0x1EU)
53936#define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_1_4_SHIFT (1U)
53937/*! EMMC0_RESET_B_reserved_1_4 - reserved
53938 */
53939#define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_1_4_SHIFT)) & IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_1_4_MASK)
53940#define IOMUXD_EMMC0_RESET_B_PULL_MASK (0x60U)
53941#define IOMUXD_EMMC0_RESET_B_PULL_SHIFT (5U)
53942/*! PULL - Pull Down Pull Up
53943 * 0b10..pull down
53944 * 0b01..pull up
53945 * 0b00..Prohibited
53946 * 0b11..pull disabled
53947 */
53948#define IOMUXD_EMMC0_RESET_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_PULL_SHIFT)) & IOMUXD_EMMC0_RESET_B_PULL_MASK)
53949#define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_7_18_MASK (0x7FF80U)
53950#define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_7_18_SHIFT (7U)
53951/*! EMMC0_RESET_B_reserved_7_18 - reserved
53952 */
53953#define IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_7_18_SHIFT)) & IOMUXD_EMMC0_RESET_B_EMMC0_RESET_B_reserved_7_18_MASK)
53954#define IOMUXD_EMMC0_RESET_B_WAKEUP_CTRL_MASK (0x380000U)
53955#define IOMUXD_EMMC0_RESET_B_WAKEUP_CTRL_SHIFT (19U)
53956/*! WAKEUP_CTRL - wakeup control
53957 * 0b000..OFF
53958 * 0b001..RESAMPLE
53959 * 0b100..LOW
53960 * 0b111..HIGH
53961 * 0b110..RISE
53962 * 0b101..FALL
53963 */
53964#define IOMUXD_EMMC0_RESET_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_EMMC0_RESET_B_WAKEUP_CTRL_MASK)
53965#define IOMUXD_EMMC0_RESET_B_WAKEUP_MASK_MASK (0x400000U)
53966#define IOMUXD_EMMC0_RESET_B_WAKEUP_MASK_SHIFT (22U)
53967/*! WAKEUP_MASK - wakeup mask
53968 */
53969#define IOMUXD_EMMC0_RESET_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_WAKEUP_MASK_SHIFT)) & IOMUXD_EMMC0_RESET_B_WAKEUP_MASK_MASK)
53970#define IOMUXD_EMMC0_RESET_B_lp_config_MASK (0x1800000U)
53971#define IOMUXD_EMMC0_RESET_B_lp_config_SHIFT (23U)
53972/*! lp_config - lower power configuration
53973 * 0b01..EARLY_ISO
53974 * 0b10..LATE_ISO
53975 * 0b11..LATCH
53976 * 0b00..PASS
53977 */
53978#define IOMUXD_EMMC0_RESET_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_lp_config_SHIFT)) & IOMUXD_EMMC0_RESET_B_lp_config_MASK)
53979#define IOMUXD_EMMC0_RESET_B_sw_config_MASK (0x6000000U)
53980#define IOMUXD_EMMC0_RESET_B_sw_config_SHIFT (25U)
53981/*! sw_config - output and input configuration
53982 * 0b01..OPEN_DRAIN
53983 * 0b10..OPEN_DRAIN_INPUT
53984 * 0b11..INOUT
53985 * 0b00..DEFAULT
53986 */
53987#define IOMUXD_EMMC0_RESET_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_sw_config_SHIFT)) & IOMUXD_EMMC0_RESET_B_sw_config_MASK)
53988#define IOMUXD_EMMC0_RESET_B_mux_mode_MASK (0x38000000U)
53989#define IOMUXD_EMMC0_RESET_B_mux_mode_SHIFT (27U)
53990/*! mux_mode - mux_mode
53991 * 0b000..CONN.EMMC0.RESET_B
53992 * 0b001..CONN.NAND.WP_B
53993 * 0b100..LSIO.GPIO4.IO18
53994 */
53995#define IOMUXD_EMMC0_RESET_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_mux_mode_SHIFT)) & IOMUXD_EMMC0_RESET_B_mux_mode_MASK)
53996#define IOMUXD_EMMC0_RESET_B_update_pad_ctl_MASK (0x40000000U)
53997#define IOMUXD_EMMC0_RESET_B_update_pad_ctl_SHIFT (30U)
53998/*! update_pad_ctl - update lock for pad control
53999 */
54000#define IOMUXD_EMMC0_RESET_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_update_pad_ctl_SHIFT)) & IOMUXD_EMMC0_RESET_B_update_pad_ctl_MASK)
54001#define IOMUXD_EMMC0_RESET_B_update_mux_mode_MASK (0x80000000U)
54002#define IOMUXD_EMMC0_RESET_B_update_mux_mode_SHIFT (31U)
54003/*! update_mux_mode - update lock for mux control
54004 */
54005#define IOMUXD_EMMC0_RESET_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_EMMC0_RESET_B_update_mux_mode_SHIFT)) & IOMUXD_EMMC0_RESET_B_update_mux_mode_MASK)
54006/*! @} */
54007
54008/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 - IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 */
54009/*! @{ */
54010#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMP_MASK (0x7U)
54011#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMP_SHIFT (0U)
54012/*! COMP - COMP
54013 * 0b010..Fixed code mode
54014 * 0b100..High impedance mode
54015 * 0b110..Read mode
54016 * 0b000..Normal Mode
54017 * 0b001..Freeze Mode
54018 */
54019#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMP_MASK)
54020#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_FASTFRZ_EN_MASK (0x8U)
54021#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_FASTFRZ_EN_SHIFT (3U)
54022/*! FASTFRZ_EN - FASTFRZ_EN
54023 * 0b1..FASTFRZ signal is driven by output of subsystem
54024 * 0b0..FASTFRZ signal is gated to 0
54025 */
54026#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_FASTFRZ_EN_MASK)
54027#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_4_4_MASK (0x10U)
54028#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_4_4_SHIFT (4U)
54029/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_4_4 - reserved
54030 */
54031#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_4_4_MASK)
54032#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCP_MASK (0x1E0U)
54033#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCP_SHIFT (5U)
54034/*! RASRCP - RASRCP
54035 * 0b0101..Reset Value
54036 */
54037#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCP_MASK)
54038#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCN_MASK (0x1E00U)
54039#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCN_SHIFT (9U)
54040/*! RASRCN - RASRCN
54041 * 0b1010..Reset Value
54042 */
54043#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_RASRCN_MASK)
54044#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SELECT_NASRC_MASK (0x2000U)
54045#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SELECT_NASRC_SHIFT (13U)
54046/*! SELECT_NASRC - SELECT_NASRC
54047 * 0b1..NASRCN value
54048 * 0b0..NASRCP value
54049 */
54050#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SELECT_NASRC_MASK)
54051#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMPOK_MASK (0x4000U)
54052#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMPOK_SHIFT (14U)
54053/*! COMPOK - COMPOK
54054 * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
54055 * 0b1..compensation cell in Normal mode and tracking PVT
54056 */
54057#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_COMPOK_MASK)
54058#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_READ_NASRC_MASK (0x78000U)
54059#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_READ_NASRC_SHIFT (15U)
54060/*! READ_NASRC - READ_NASRC
54061 * 0b0000..READ Only
54062 */
54063#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_READ_NASRC_MASK)
54064#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_19_22_MASK (0x780000U)
54065#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_19_22_SHIFT (19U)
54066/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_19_22 - reserved
54067 */
54068#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_19_22_MASK)
54069#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SLEEP_MASK (0x1800000U)
54070#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SLEEP_SHIFT (23U)
54071/*! SLEEP - SLEEP
54072 * 0b11..Force into sleep mode
54073 * 0b00..NO
54074 * 0b01..EARLY
54075 * 0b10..LATE
54076 */
54077#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_SLEEP_MASK)
54078#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_25_29_MASK (0x3E000000U)
54079#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_25_29_SHIFT (25U)
54080/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_25_29 - reserved
54081 */
54082#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_reserved_25_29_MASK)
54083#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_pad_ctl_MASK (0x40000000U)
54084#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_pad_ctl_SHIFT (30U)
54085/*! update_pad_ctl - update lock for pad control
54086 */
54087#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_pad_ctl_MASK)
54088#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_mux_mode_MASK (0x80000000U)
54089#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_mux_mode_SHIFT (31U)
54090/*! update_mux_mode - update lock for mux control
54091 */
54092#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_update_mux_mode_MASK)
54093/*! @} */
54094
54095/*! @name USDHC1_RESET_B - USDHC1_RESET_B */
54096/*! @{ */
54097#define IOMUXD_USDHC1_RESET_B_PDRV_MASK (0x1U)
54098#define IOMUXD_USDHC1_RESET_B_PDRV_SHIFT (0U)
54099/*! PDRV - Drive
54100 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
54101 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
54102 */
54103#define IOMUXD_USDHC1_RESET_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_PDRV_SHIFT)) & IOMUXD_USDHC1_RESET_B_PDRV_MASK)
54104#define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_1_4_MASK (0x1EU)
54105#define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_1_4_SHIFT (1U)
54106/*! USDHC1_RESET_B_reserved_1_4 - reserved
54107 */
54108#define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_1_4_MASK)
54109#define IOMUXD_USDHC1_RESET_B_PULL_MASK (0x60U)
54110#define IOMUXD_USDHC1_RESET_B_PULL_SHIFT (5U)
54111/*! PULL - Pull Down Pull Up
54112 * 0b10..pull down
54113 * 0b01..pull up
54114 * 0b00..Prohibited
54115 * 0b11..pull disabled
54116 */
54117#define IOMUXD_USDHC1_RESET_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_PULL_SHIFT)) & IOMUXD_USDHC1_RESET_B_PULL_MASK)
54118#define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_7_18_MASK (0x7FF80U)
54119#define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_7_18_SHIFT (7U)
54120/*! USDHC1_RESET_B_reserved_7_18 - reserved
54121 */
54122#define IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_RESET_B_USDHC1_RESET_B_reserved_7_18_MASK)
54123#define IOMUXD_USDHC1_RESET_B_WAKEUP_CTRL_MASK (0x380000U)
54124#define IOMUXD_USDHC1_RESET_B_WAKEUP_CTRL_SHIFT (19U)
54125/*! WAKEUP_CTRL - wakeup control
54126 * 0b000..OFF
54127 * 0b001..RESAMPLE
54128 * 0b100..LOW
54129 * 0b111..HIGH
54130 * 0b110..RISE
54131 * 0b101..FALL
54132 */
54133#define IOMUXD_USDHC1_RESET_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_RESET_B_WAKEUP_CTRL_MASK)
54134#define IOMUXD_USDHC1_RESET_B_WAKEUP_MASK_MASK (0x400000U)
54135#define IOMUXD_USDHC1_RESET_B_WAKEUP_MASK_SHIFT (22U)
54136/*! WAKEUP_MASK - wakeup mask
54137 */
54138#define IOMUXD_USDHC1_RESET_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_RESET_B_WAKEUP_MASK_MASK)
54139#define IOMUXD_USDHC1_RESET_B_lp_config_MASK (0x1800000U)
54140#define IOMUXD_USDHC1_RESET_B_lp_config_SHIFT (23U)
54141/*! lp_config - lower power configuration
54142 * 0b01..EARLY_ISO
54143 * 0b10..LATE_ISO
54144 * 0b11..LATCH
54145 * 0b00..PASS
54146 */
54147#define IOMUXD_USDHC1_RESET_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_lp_config_SHIFT)) & IOMUXD_USDHC1_RESET_B_lp_config_MASK)
54148#define IOMUXD_USDHC1_RESET_B_sw_config_MASK (0x6000000U)
54149#define IOMUXD_USDHC1_RESET_B_sw_config_SHIFT (25U)
54150/*! sw_config - output and input configuration
54151 * 0b01..OPEN_DRAIN
54152 * 0b10..OPEN_DRAIN_INPUT
54153 * 0b11..INOUT
54154 * 0b00..DEFAULT
54155 */
54156#define IOMUXD_USDHC1_RESET_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_sw_config_SHIFT)) & IOMUXD_USDHC1_RESET_B_sw_config_MASK)
54157#define IOMUXD_USDHC1_RESET_B_mux_mode_MASK (0x38000000U)
54158#define IOMUXD_USDHC1_RESET_B_mux_mode_SHIFT (27U)
54159/*! mux_mode - mux_mode
54160 * 0b000..CONN.USDHC1.RESET_B
54161 * 0b001..CONN.NAND.RE_N
54162 * 0b010..ADMA.SPI2.SCK
54163 * 0b100..LSIO.GPIO4.IO19
54164 */
54165#define IOMUXD_USDHC1_RESET_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_mux_mode_SHIFT)) & IOMUXD_USDHC1_RESET_B_mux_mode_MASK)
54166#define IOMUXD_USDHC1_RESET_B_update_pad_ctl_MASK (0x40000000U)
54167#define IOMUXD_USDHC1_RESET_B_update_pad_ctl_SHIFT (30U)
54168/*! update_pad_ctl - update lock for pad control
54169 */
54170#define IOMUXD_USDHC1_RESET_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_RESET_B_update_pad_ctl_MASK)
54171#define IOMUXD_USDHC1_RESET_B_update_mux_mode_MASK (0x80000000U)
54172#define IOMUXD_USDHC1_RESET_B_update_mux_mode_SHIFT (31U)
54173/*! update_mux_mode - update lock for mux control
54174 */
54175#define IOMUXD_USDHC1_RESET_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_RESET_B_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_RESET_B_update_mux_mode_MASK)
54176/*! @} */
54177
54178/*! @name IOMUXD_GROUP_1_0 - na */
54179/*! @{ */
54180#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CLK_MASK (0x1U)
54181#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CLK_SHIFT (0U)
54182/*! EMMC0_CLK - wakeup from EMMC0_CLK
54183 */
54184#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CLK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CLK_MASK)
54185#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CMD_MASK (0x2U)
54186#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CMD_SHIFT (1U)
54187/*! EMMC0_CMD - wakeup from EMMC0_CMD
54188 */
54189#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CMD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CMD_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_CMD_MASK)
54190#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA0_MASK (0x4U)
54191#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA0_SHIFT (2U)
54192/*! EMMC0_DATA0 - wakeup from EMMC0_DATA0
54193 */
54194#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA0_MASK)
54195#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA1_MASK (0x8U)
54196#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA1_SHIFT (3U)
54197/*! EMMC0_DATA1 - wakeup from EMMC0_DATA1
54198 */
54199#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA1_MASK)
54200#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA2_MASK (0x10U)
54201#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA2_SHIFT (4U)
54202/*! EMMC0_DATA2 - wakeup from EMMC0_DATA2
54203 */
54204#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA2_MASK)
54205#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA3_MASK (0x20U)
54206#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA3_SHIFT (5U)
54207/*! EMMC0_DATA3 - wakeup from EMMC0_DATA3
54208 */
54209#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA3_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA3_MASK)
54210#define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_6_6_MASK (0x40U)
54211#define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_6_6_SHIFT (6U)
54212/*! iomuxd_group_1_0_reserved_6_6 - reserved
54213 */
54214#define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_6_6_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_6_6_MASK)
54215#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA4_MASK (0x80U)
54216#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA4_SHIFT (7U)
54217/*! EMMC0_DATA4 - wakeup from EMMC0_DATA4
54218 */
54219#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA4_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA4_MASK)
54220#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA5_MASK (0x100U)
54221#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA5_SHIFT (8U)
54222/*! EMMC0_DATA5 - wakeup from EMMC0_DATA5
54223 */
54224#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA5_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA5_MASK)
54225#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA6_MASK (0x200U)
54226#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA6_SHIFT (9U)
54227/*! EMMC0_DATA6 - wakeup from EMMC0_DATA6
54228 */
54229#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA6_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA6_MASK)
54230#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA7_MASK (0x400U)
54231#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA7_SHIFT (10U)
54232/*! EMMC0_DATA7 - wakeup from EMMC0_DATA7
54233 */
54234#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA7_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_DATA7_MASK)
54235#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_STROBE_MASK (0x800U)
54236#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_STROBE_SHIFT (11U)
54237/*! EMMC0_STROBE - wakeup from EMMC0_STROBE
54238 */
54239#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_STROBE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_STROBE_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_STROBE_MASK)
54240#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_RESET_B_MASK (0x1000U)
54241#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_RESET_B_SHIFT (12U)
54242/*! EMMC0_RESET_B - wakeup from EMMC0_RESET_B
54243 */
54244#define IOMUXD_IOMUXD_GROUP_1_0_EMMC0_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_EMMC0_RESET_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_EMMC0_RESET_B_MASK)
54245#define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_13_13_MASK (0x2000U)
54246#define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_13_13_SHIFT (13U)
54247/*! iomuxd_group_1_0_reserved_13_13 - reserved
54248 */
54249#define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_13_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_13_13_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_13_13_MASK)
54250#define IOMUXD_IOMUXD_GROUP_1_0_USDHC1_RESET_B_MASK (0x4000U)
54251#define IOMUXD_IOMUXD_GROUP_1_0_USDHC1_RESET_B_SHIFT (14U)
54252/*! USDHC1_RESET_B - wakeup from USDHC1_RESET_B
54253 */
54254#define IOMUXD_IOMUXD_GROUP_1_0_USDHC1_RESET_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_USDHC1_RESET_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_USDHC1_RESET_B_MASK)
54255#define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_15_31_MASK (0xFFFF8000U)
54256#define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_15_31_SHIFT (15U)
54257/*! iomuxd_group_1_0_reserved_15_31 - reserved
54258 */
54259#define IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_0_iomuxd_group_1_0_reserved_15_31_MASK)
54260/*! @} */
54261
54262/*! @name USDHC1_VSELECT - USDHC1_VSELECT */
54263/*! @{ */
54264#define IOMUXD_USDHC1_VSELECT_PDRV_MASK (0x1U)
54265#define IOMUXD_USDHC1_VSELECT_PDRV_SHIFT (0U)
54266/*! PDRV - Drive
54267 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
54268 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
54269 */
54270#define IOMUXD_USDHC1_VSELECT_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_PDRV_SHIFT)) & IOMUXD_USDHC1_VSELECT_PDRV_MASK)
54271#define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_1_4_MASK (0x1EU)
54272#define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_1_4_SHIFT (1U)
54273/*! USDHC1_VSELECT_reserved_1_4 - reserved
54274 */
54275#define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_1_4_MASK)
54276#define IOMUXD_USDHC1_VSELECT_PULL_MASK (0x60U)
54277#define IOMUXD_USDHC1_VSELECT_PULL_SHIFT (5U)
54278/*! PULL - Pull Down Pull Up
54279 * 0b10..pull down
54280 * 0b01..pull up
54281 * 0b00..Prohibited
54282 * 0b11..pull disabled
54283 */
54284#define IOMUXD_USDHC1_VSELECT_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_PULL_SHIFT)) & IOMUXD_USDHC1_VSELECT_PULL_MASK)
54285#define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_7_18_MASK (0x7FF80U)
54286#define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_7_18_SHIFT (7U)
54287/*! USDHC1_VSELECT_reserved_7_18 - reserved
54288 */
54289#define IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_VSELECT_USDHC1_VSELECT_reserved_7_18_MASK)
54290#define IOMUXD_USDHC1_VSELECT_WAKEUP_CTRL_MASK (0x380000U)
54291#define IOMUXD_USDHC1_VSELECT_WAKEUP_CTRL_SHIFT (19U)
54292/*! WAKEUP_CTRL - wakeup control
54293 * 0b000..OFF
54294 * 0b001..RESAMPLE
54295 * 0b100..LOW
54296 * 0b111..HIGH
54297 * 0b110..RISE
54298 * 0b101..FALL
54299 */
54300#define IOMUXD_USDHC1_VSELECT_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_VSELECT_WAKEUP_CTRL_MASK)
54301#define IOMUXD_USDHC1_VSELECT_WAKEUP_MASK_MASK (0x400000U)
54302#define IOMUXD_USDHC1_VSELECT_WAKEUP_MASK_SHIFT (22U)
54303/*! WAKEUP_MASK - wakeup mask
54304 */
54305#define IOMUXD_USDHC1_VSELECT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_VSELECT_WAKEUP_MASK_MASK)
54306#define IOMUXD_USDHC1_VSELECT_lp_config_MASK (0x1800000U)
54307#define IOMUXD_USDHC1_VSELECT_lp_config_SHIFT (23U)
54308/*! lp_config - lower power configuration
54309 * 0b01..EARLY_ISO
54310 * 0b10..LATE_ISO
54311 * 0b11..LATCH
54312 * 0b00..PASS
54313 */
54314#define IOMUXD_USDHC1_VSELECT_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_lp_config_SHIFT)) & IOMUXD_USDHC1_VSELECT_lp_config_MASK)
54315#define IOMUXD_USDHC1_VSELECT_sw_config_MASK (0x6000000U)
54316#define IOMUXD_USDHC1_VSELECT_sw_config_SHIFT (25U)
54317/*! sw_config - output and input configuration
54318 * 0b01..OPEN_DRAIN
54319 * 0b10..OPEN_DRAIN_INPUT
54320 * 0b11..INOUT
54321 * 0b00..DEFAULT
54322 */
54323#define IOMUXD_USDHC1_VSELECT_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_sw_config_SHIFT)) & IOMUXD_USDHC1_VSELECT_sw_config_MASK)
54324#define IOMUXD_USDHC1_VSELECT_mux_mode_MASK (0x38000000U)
54325#define IOMUXD_USDHC1_VSELECT_mux_mode_SHIFT (27U)
54326/*! mux_mode - mux_mode
54327 * 0b000..CONN.USDHC1.VSELECT
54328 * 0b001..CONN.NAND.RE_P
54329 * 0b010..ADMA.SPI2.SDO
54330 * 0b011..CONN.NAND.RE_B
54331 * 0b100..LSIO.GPIO4.IO20
54332 */
54333#define IOMUXD_USDHC1_VSELECT_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_mux_mode_SHIFT)) & IOMUXD_USDHC1_VSELECT_mux_mode_MASK)
54334#define IOMUXD_USDHC1_VSELECT_update_pad_ctl_MASK (0x40000000U)
54335#define IOMUXD_USDHC1_VSELECT_update_pad_ctl_SHIFT (30U)
54336/*! update_pad_ctl - update lock for pad control
54337 */
54338#define IOMUXD_USDHC1_VSELECT_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_VSELECT_update_pad_ctl_MASK)
54339#define IOMUXD_USDHC1_VSELECT_update_mux_mode_MASK (0x80000000U)
54340#define IOMUXD_USDHC1_VSELECT_update_mux_mode_SHIFT (31U)
54341/*! update_mux_mode - update lock for mux control
54342 */
54343#define IOMUXD_USDHC1_VSELECT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_VSELECT_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_VSELECT_update_mux_mode_MASK)
54344/*! @} */
54345
54346/*! @name IOMUXD_CTL_NAND_RE_P_N - IOMUXD_CTL_NAND_RE_P_N */
54347/*! @{ */
54348#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_P_N_SELECT_MASK (0x1U)
54349#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_P_N_SELECT_SHIFT (0U)
54350/*! P_N_SELECT - P_N_SELECT
54351 * 0b0..
54352 * 0b1..
54353 */
54354#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_P_N_SELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_RE_P_N_P_N_SELECT_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_RE_P_N_P_N_SELECT_MASK)
54355#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_IOMUXD_CTL_NAND_RE_P_N_reserved_1_29_MASK (0x3FFFFFFEU)
54356#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_IOMUXD_CTL_NAND_RE_P_N_reserved_1_29_SHIFT (1U)
54357/*! IOMUXD_CTL_NAND_RE_P_N_reserved_1_29 - reserved
54358 */
54359#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_IOMUXD_CTL_NAND_RE_P_N_reserved_1_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_RE_P_N_IOMUXD_CTL_NAND_RE_P_N_reserved_1_29_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_RE_P_N_IOMUXD_CTL_NAND_RE_P_N_reserved_1_29_MASK)
54360#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_pad_ctl_MASK (0x40000000U)
54361#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_pad_ctl_SHIFT (30U)
54362/*! update_pad_ctl - update lock for pad control
54363 */
54364#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_pad_ctl_MASK)
54365#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_mux_mode_MASK (0x80000000U)
54366#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_mux_mode_SHIFT (31U)
54367/*! update_mux_mode - update lock for mux control
54368 */
54369#define IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_RE_P_N_update_mux_mode_MASK)
54370/*! @} */
54371
54372/*! @name USDHC1_WP - USDHC1_WP */
54373/*! @{ */
54374#define IOMUXD_USDHC1_WP_PDRV_MASK (0x1U)
54375#define IOMUXD_USDHC1_WP_PDRV_SHIFT (0U)
54376/*! PDRV - Drive
54377 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
54378 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
54379 */
54380#define IOMUXD_USDHC1_WP_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_PDRV_SHIFT)) & IOMUXD_USDHC1_WP_PDRV_MASK)
54381#define IOMUXD_USDHC1_WP_USDHC1_WP_reserved_1_4_MASK (0x1EU)
54382#define IOMUXD_USDHC1_WP_USDHC1_WP_reserved_1_4_SHIFT (1U)
54383/*! USDHC1_WP_reserved_1_4 - reserved
54384 */
54385#define IOMUXD_USDHC1_WP_USDHC1_WP_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_USDHC1_WP_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_WP_USDHC1_WP_reserved_1_4_MASK)
54386#define IOMUXD_USDHC1_WP_PULL_MASK (0x60U)
54387#define IOMUXD_USDHC1_WP_PULL_SHIFT (5U)
54388/*! PULL - Pull Down Pull Up
54389 * 0b10..pull down
54390 * 0b01..pull up
54391 * 0b00..Prohibited
54392 * 0b11..pull disabled
54393 */
54394#define IOMUXD_USDHC1_WP_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_PULL_SHIFT)) & IOMUXD_USDHC1_WP_PULL_MASK)
54395#define IOMUXD_USDHC1_WP_USDHC1_WP_reserved_7_18_MASK (0x7FF80U)
54396#define IOMUXD_USDHC1_WP_USDHC1_WP_reserved_7_18_SHIFT (7U)
54397/*! USDHC1_WP_reserved_7_18 - reserved
54398 */
54399#define IOMUXD_USDHC1_WP_USDHC1_WP_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_USDHC1_WP_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_WP_USDHC1_WP_reserved_7_18_MASK)
54400#define IOMUXD_USDHC1_WP_WAKEUP_CTRL_MASK (0x380000U)
54401#define IOMUXD_USDHC1_WP_WAKEUP_CTRL_SHIFT (19U)
54402/*! WAKEUP_CTRL - wakeup control
54403 * 0b000..OFF
54404 * 0b001..RESAMPLE
54405 * 0b100..LOW
54406 * 0b111..HIGH
54407 * 0b110..RISE
54408 * 0b101..FALL
54409 */
54410#define IOMUXD_USDHC1_WP_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_WP_WAKEUP_CTRL_MASK)
54411#define IOMUXD_USDHC1_WP_WAKEUP_MASK_MASK (0x400000U)
54412#define IOMUXD_USDHC1_WP_WAKEUP_MASK_SHIFT (22U)
54413/*! WAKEUP_MASK - wakeup mask
54414 */
54415#define IOMUXD_USDHC1_WP_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_WP_WAKEUP_MASK_MASK)
54416#define IOMUXD_USDHC1_WP_lp_config_MASK (0x1800000U)
54417#define IOMUXD_USDHC1_WP_lp_config_SHIFT (23U)
54418/*! lp_config - lower power configuration
54419 * 0b01..EARLY_ISO
54420 * 0b10..LATE_ISO
54421 * 0b11..LATCH
54422 * 0b00..PASS
54423 */
54424#define IOMUXD_USDHC1_WP_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_lp_config_SHIFT)) & IOMUXD_USDHC1_WP_lp_config_MASK)
54425#define IOMUXD_USDHC1_WP_sw_config_MASK (0x6000000U)
54426#define IOMUXD_USDHC1_WP_sw_config_SHIFT (25U)
54427/*! sw_config - output and input configuration
54428 * 0b01..OPEN_DRAIN
54429 * 0b10..OPEN_DRAIN_INPUT
54430 * 0b11..INOUT
54431 * 0b00..DEFAULT
54432 */
54433#define IOMUXD_USDHC1_WP_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_sw_config_SHIFT)) & IOMUXD_USDHC1_WP_sw_config_MASK)
54434#define IOMUXD_USDHC1_WP_mux_mode_MASK (0x38000000U)
54435#define IOMUXD_USDHC1_WP_mux_mode_SHIFT (27U)
54436/*! mux_mode - mux_mode
54437 * 0b000..CONN.USDHC1.WP
54438 * 0b001..CONN.NAND.DQS_N
54439 * 0b010..ADMA.SPI2.SDI
54440 * 0b100..LSIO.GPIO4.IO21
54441 */
54442#define IOMUXD_USDHC1_WP_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_mux_mode_SHIFT)) & IOMUXD_USDHC1_WP_mux_mode_MASK)
54443#define IOMUXD_USDHC1_WP_update_pad_ctl_MASK (0x40000000U)
54444#define IOMUXD_USDHC1_WP_update_pad_ctl_SHIFT (30U)
54445/*! update_pad_ctl - update lock for pad control
54446 */
54447#define IOMUXD_USDHC1_WP_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_WP_update_pad_ctl_MASK)
54448#define IOMUXD_USDHC1_WP_update_mux_mode_MASK (0x80000000U)
54449#define IOMUXD_USDHC1_WP_update_mux_mode_SHIFT (31U)
54450/*! update_mux_mode - update lock for mux control
54451 */
54452#define IOMUXD_USDHC1_WP_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_WP_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_WP_update_mux_mode_MASK)
54453/*! @} */
54454
54455/*! @name USDHC1_CD_B - USDHC1_CD_B */
54456/*! @{ */
54457#define IOMUXD_USDHC1_CD_B_PDRV_MASK (0x1U)
54458#define IOMUXD_USDHC1_CD_B_PDRV_SHIFT (0U)
54459/*! PDRV - Drive
54460 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
54461 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
54462 */
54463#define IOMUXD_USDHC1_CD_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_PDRV_SHIFT)) & IOMUXD_USDHC1_CD_B_PDRV_MASK)
54464#define IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_1_4_MASK (0x1EU)
54465#define IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_1_4_SHIFT (1U)
54466/*! USDHC1_CD_B_reserved_1_4 - reserved
54467 */
54468#define IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_1_4_MASK)
54469#define IOMUXD_USDHC1_CD_B_PULL_MASK (0x60U)
54470#define IOMUXD_USDHC1_CD_B_PULL_SHIFT (5U)
54471/*! PULL - Pull Down Pull Up
54472 * 0b10..pull down
54473 * 0b01..pull up
54474 * 0b00..Prohibited
54475 * 0b11..pull disabled
54476 */
54477#define IOMUXD_USDHC1_CD_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_PULL_SHIFT)) & IOMUXD_USDHC1_CD_B_PULL_MASK)
54478#define IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_7_18_MASK (0x7FF80U)
54479#define IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_7_18_SHIFT (7U)
54480/*! USDHC1_CD_B_reserved_7_18 - reserved
54481 */
54482#define IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_CD_B_USDHC1_CD_B_reserved_7_18_MASK)
54483#define IOMUXD_USDHC1_CD_B_WAKEUP_CTRL_MASK (0x380000U)
54484#define IOMUXD_USDHC1_CD_B_WAKEUP_CTRL_SHIFT (19U)
54485/*! WAKEUP_CTRL - wakeup control
54486 * 0b000..OFF
54487 * 0b001..RESAMPLE
54488 * 0b100..LOW
54489 * 0b111..HIGH
54490 * 0b110..RISE
54491 * 0b101..FALL
54492 */
54493#define IOMUXD_USDHC1_CD_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_CD_B_WAKEUP_CTRL_MASK)
54494#define IOMUXD_USDHC1_CD_B_WAKEUP_MASK_MASK (0x400000U)
54495#define IOMUXD_USDHC1_CD_B_WAKEUP_MASK_SHIFT (22U)
54496/*! WAKEUP_MASK - wakeup mask
54497 */
54498#define IOMUXD_USDHC1_CD_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_CD_B_WAKEUP_MASK_MASK)
54499#define IOMUXD_USDHC1_CD_B_lp_config_MASK (0x1800000U)
54500#define IOMUXD_USDHC1_CD_B_lp_config_SHIFT (23U)
54501/*! lp_config - lower power configuration
54502 * 0b01..EARLY_ISO
54503 * 0b10..LATE_ISO
54504 * 0b11..LATCH
54505 * 0b00..PASS
54506 */
54507#define IOMUXD_USDHC1_CD_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_lp_config_SHIFT)) & IOMUXD_USDHC1_CD_B_lp_config_MASK)
54508#define IOMUXD_USDHC1_CD_B_sw_config_MASK (0x6000000U)
54509#define IOMUXD_USDHC1_CD_B_sw_config_SHIFT (25U)
54510/*! sw_config - output and input configuration
54511 * 0b01..OPEN_DRAIN
54512 * 0b10..OPEN_DRAIN_INPUT
54513 * 0b11..INOUT
54514 * 0b00..DEFAULT
54515 */
54516#define IOMUXD_USDHC1_CD_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_sw_config_SHIFT)) & IOMUXD_USDHC1_CD_B_sw_config_MASK)
54517#define IOMUXD_USDHC1_CD_B_mux_mode_MASK (0x38000000U)
54518#define IOMUXD_USDHC1_CD_B_mux_mode_SHIFT (27U)
54519/*! mux_mode - mux_mode
54520 * 0b000..CONN.USDHC1.CD_B
54521 * 0b001..CONN.NAND.DQS_P
54522 * 0b010..ADMA.SPI2.CS0
54523 * 0b011..CONN.NAND.DQS
54524 * 0b100..LSIO.GPIO4.IO22
54525 */
54526#define IOMUXD_USDHC1_CD_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_mux_mode_SHIFT)) & IOMUXD_USDHC1_CD_B_mux_mode_MASK)
54527#define IOMUXD_USDHC1_CD_B_update_pad_ctl_MASK (0x40000000U)
54528#define IOMUXD_USDHC1_CD_B_update_pad_ctl_SHIFT (30U)
54529/*! update_pad_ctl - update lock for pad control
54530 */
54531#define IOMUXD_USDHC1_CD_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_CD_B_update_pad_ctl_MASK)
54532#define IOMUXD_USDHC1_CD_B_update_mux_mode_MASK (0x80000000U)
54533#define IOMUXD_USDHC1_CD_B_update_mux_mode_SHIFT (31U)
54534/*! update_mux_mode - update lock for mux control
54535 */
54536#define IOMUXD_USDHC1_CD_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CD_B_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_CD_B_update_mux_mode_MASK)
54537/*! @} */
54538
54539/*! @name IOMUXD_CTL_NAND_DQS_P_N - IOMUXD_CTL_NAND_DQS_P_N */
54540/*! @{ */
54541#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_P_N_SELECT_MASK (0x1U)
54542#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_P_N_SELECT_SHIFT (0U)
54543/*! P_N_SELECT - P_N_SELECT
54544 * 0b0..
54545 * 0b1..
54546 */
54547#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_P_N_SELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_P_N_SELECT_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_P_N_SELECT_MASK)
54548#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29_MASK (0x3FFFFFFEU)
54549#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29_SHIFT (1U)
54550/*! IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29 - reserved
54551 */
54552#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_IOMUXD_CTL_NAND_DQS_P_N_reserved_1_29_MASK)
54553#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_pad_ctl_MASK (0x40000000U)
54554#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_pad_ctl_SHIFT (30U)
54555/*! update_pad_ctl - update lock for pad control
54556 */
54557#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_pad_ctl_MASK)
54558#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_mux_mode_MASK (0x80000000U)
54559#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_mux_mode_SHIFT (31U)
54560/*! update_mux_mode - update lock for mux control
54561 */
54562#define IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_CTL_NAND_DQS_P_N_update_mux_mode_MASK)
54563/*! @} */
54564
54565/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP - IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP */
54566/*! @{ */
54567#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMP_MASK (0x7U)
54568#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMP_SHIFT (0U)
54569/*! COMP - COMP
54570 * 0b010..Fixed code mode
54571 * 0b100..High impedance mode
54572 * 0b110..Read mode
54573 * 0b000..Normal Mode
54574 * 0b001..Freeze Mode
54575 */
54576#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMP_MASK)
54577#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_FASTFRZ_EN_MASK (0x8U)
54578#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_FASTFRZ_EN_SHIFT (3U)
54579/*! FASTFRZ_EN - FASTFRZ_EN
54580 * 0b1..FASTFRZ signal is driven by output of subsystem
54581 * 0b0..FASTFRZ signal is gated to 0
54582 */
54583#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_FASTFRZ_EN_MASK)
54584#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4_MASK (0x10U)
54585#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4_SHIFT (4U)
54586/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4 - reserved
54587 */
54588#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_4_4_MASK)
54589#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCP_MASK (0x1E0U)
54590#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCP_SHIFT (5U)
54591/*! RASRCP - RASRCP
54592 * 0b0101..Reset Value
54593 */
54594#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCP_MASK)
54595#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCN_MASK (0x1E00U)
54596#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCN_SHIFT (9U)
54597/*! RASRCN - RASRCN
54598 * 0b1010..Reset Value
54599 */
54600#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_RASRCN_MASK)
54601#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SELECT_NASRC_MASK (0x2000U)
54602#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SELECT_NASRC_SHIFT (13U)
54603/*! SELECT_NASRC - SELECT_NASRC
54604 * 0b1..NASRCN value
54605 * 0b0..NASRCP value
54606 */
54607#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SELECT_NASRC_MASK)
54608#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMPOK_MASK (0x4000U)
54609#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMPOK_SHIFT (14U)
54610/*! COMPOK - COMPOK
54611 * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
54612 * 0b1..compensation cell in Normal mode and tracking PVT
54613 */
54614#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_COMPOK_MASK)
54615#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_READ_NASRC_MASK (0x78000U)
54616#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_READ_NASRC_SHIFT (15U)
54617/*! READ_NASRC - READ_NASRC
54618 * 0b0000..READ Only
54619 */
54620#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_READ_NASRC_MASK)
54621#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22_MASK (0x780000U)
54622#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22_SHIFT (19U)
54623/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22 - reserved
54624 */
54625#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_19_22_MASK)
54626#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SLEEP_MASK (0x1800000U)
54627#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SLEEP_SHIFT (23U)
54628/*! SLEEP - SLEEP
54629 * 0b11..Force into sleep mode
54630 * 0b00..NO
54631 * 0b01..EARLY
54632 * 0b10..LATE
54633 */
54634#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_SLEEP_MASK)
54635#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29_MASK (0x3E000000U)
54636#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29_SHIFT (25U)
54637/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29 - reserved
54638 */
54639#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_reserved_25_29_MASK)
54640#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_pad_ctl_MASK (0x40000000U)
54641#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_pad_ctl_SHIFT (30U)
54642/*! update_pad_ctl - update lock for pad control
54643 */
54644#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_pad_ctl_MASK)
54645#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_mux_mode_MASK (0x80000000U)
54646#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_mux_mode_SHIFT (31U)
54647/*! update_mux_mode - update lock for mux control
54648 */
54649#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSELSEP_update_mux_mode_MASK)
54650/*! @} */
54651
54652/*! @name USDHC1_CLK - USDHC1_CLK */
54653/*! @{ */
54654#define IOMUXD_USDHC1_CLK_PDRV_MASK (0x1U)
54655#define IOMUXD_USDHC1_CLK_PDRV_SHIFT (0U)
54656/*! PDRV - Drive
54657 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
54658 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
54659 */
54660#define IOMUXD_USDHC1_CLK_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_PDRV_SHIFT)) & IOMUXD_USDHC1_CLK_PDRV_MASK)
54661#define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_1_4_MASK (0x1EU)
54662#define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_1_4_SHIFT (1U)
54663/*! USDHC1_CLK_reserved_1_4 - reserved
54664 */
54665#define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_1_4_MASK)
54666#define IOMUXD_USDHC1_CLK_PULL_MASK (0x60U)
54667#define IOMUXD_USDHC1_CLK_PULL_SHIFT (5U)
54668/*! PULL - Pull Down Pull Up
54669 * 0b10..pull down
54670 * 0b01..pull up
54671 * 0b00..Prohibited
54672 * 0b11..pull disabled
54673 */
54674#define IOMUXD_USDHC1_CLK_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_PULL_SHIFT)) & IOMUXD_USDHC1_CLK_PULL_MASK)
54675#define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_7_18_MASK (0x7FF80U)
54676#define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_7_18_SHIFT (7U)
54677/*! USDHC1_CLK_reserved_7_18 - reserved
54678 */
54679#define IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_CLK_USDHC1_CLK_reserved_7_18_MASK)
54680#define IOMUXD_USDHC1_CLK_WAKEUP_CTRL_MASK (0x380000U)
54681#define IOMUXD_USDHC1_CLK_WAKEUP_CTRL_SHIFT (19U)
54682/*! WAKEUP_CTRL - wakeup control
54683 * 0b000..OFF
54684 * 0b001..RESAMPLE
54685 * 0b100..LOW
54686 * 0b111..HIGH
54687 * 0b110..RISE
54688 * 0b101..FALL
54689 */
54690#define IOMUXD_USDHC1_CLK_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_CLK_WAKEUP_CTRL_MASK)
54691#define IOMUXD_USDHC1_CLK_WAKEUP_MASK_MASK (0x400000U)
54692#define IOMUXD_USDHC1_CLK_WAKEUP_MASK_SHIFT (22U)
54693/*! WAKEUP_MASK - wakeup mask
54694 */
54695#define IOMUXD_USDHC1_CLK_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_CLK_WAKEUP_MASK_MASK)
54696#define IOMUXD_USDHC1_CLK_lp_config_MASK (0x1800000U)
54697#define IOMUXD_USDHC1_CLK_lp_config_SHIFT (23U)
54698/*! lp_config - lower power configuration
54699 * 0b01..EARLY_ISO
54700 * 0b10..LATE_ISO
54701 * 0b11..LATCH
54702 * 0b00..PASS
54703 */
54704#define IOMUXD_USDHC1_CLK_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_lp_config_SHIFT)) & IOMUXD_USDHC1_CLK_lp_config_MASK)
54705#define IOMUXD_USDHC1_CLK_sw_config_MASK (0x6000000U)
54706#define IOMUXD_USDHC1_CLK_sw_config_SHIFT (25U)
54707/*! sw_config - output and input configuration
54708 * 0b01..OPEN_DRAIN
54709 * 0b10..OPEN_DRAIN_INPUT
54710 * 0b11..INOUT
54711 * 0b00..DEFAULT
54712 */
54713#define IOMUXD_USDHC1_CLK_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_sw_config_SHIFT)) & IOMUXD_USDHC1_CLK_sw_config_MASK)
54714#define IOMUXD_USDHC1_CLK_mux_mode_MASK (0x38000000U)
54715#define IOMUXD_USDHC1_CLK_mux_mode_SHIFT (27U)
54716/*! mux_mode - mux_mode
54717 * 0b000..CONN.USDHC1.CLK
54718 * 0b010..ADMA.UART3.RX
54719 * 0b100..LSIO.GPIO4.IO23
54720 */
54721#define IOMUXD_USDHC1_CLK_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_mux_mode_SHIFT)) & IOMUXD_USDHC1_CLK_mux_mode_MASK)
54722#define IOMUXD_USDHC1_CLK_update_pad_ctl_MASK (0x40000000U)
54723#define IOMUXD_USDHC1_CLK_update_pad_ctl_SHIFT (30U)
54724/*! update_pad_ctl - update lock for pad control
54725 */
54726#define IOMUXD_USDHC1_CLK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_CLK_update_pad_ctl_MASK)
54727#define IOMUXD_USDHC1_CLK_update_mux_mode_MASK (0x80000000U)
54728#define IOMUXD_USDHC1_CLK_update_mux_mode_SHIFT (31U)
54729/*! update_mux_mode - update lock for mux control
54730 */
54731#define IOMUXD_USDHC1_CLK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CLK_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_CLK_update_mux_mode_MASK)
54732/*! @} */
54733
54734/*! @name USDHC1_CMD - USDHC1_CMD */
54735/*! @{ */
54736#define IOMUXD_USDHC1_CMD_PDRV_MASK (0x1U)
54737#define IOMUXD_USDHC1_CMD_PDRV_SHIFT (0U)
54738/*! PDRV - Drive
54739 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
54740 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
54741 */
54742#define IOMUXD_USDHC1_CMD_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_PDRV_SHIFT)) & IOMUXD_USDHC1_CMD_PDRV_MASK)
54743#define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_1_4_MASK (0x1EU)
54744#define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_1_4_SHIFT (1U)
54745/*! USDHC1_CMD_reserved_1_4 - reserved
54746 */
54747#define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_1_4_MASK)
54748#define IOMUXD_USDHC1_CMD_PULL_MASK (0x60U)
54749#define IOMUXD_USDHC1_CMD_PULL_SHIFT (5U)
54750/*! PULL - Pull Down Pull Up
54751 * 0b10..pull down
54752 * 0b01..pull up
54753 * 0b00..Prohibited
54754 * 0b11..pull disabled
54755 */
54756#define IOMUXD_USDHC1_CMD_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_PULL_SHIFT)) & IOMUXD_USDHC1_CMD_PULL_MASK)
54757#define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_7_18_MASK (0x7FF80U)
54758#define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_7_18_SHIFT (7U)
54759/*! USDHC1_CMD_reserved_7_18 - reserved
54760 */
54761#define IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_CMD_USDHC1_CMD_reserved_7_18_MASK)
54762#define IOMUXD_USDHC1_CMD_WAKEUP_CTRL_MASK (0x380000U)
54763#define IOMUXD_USDHC1_CMD_WAKEUP_CTRL_SHIFT (19U)
54764/*! WAKEUP_CTRL - wakeup control
54765 * 0b000..OFF
54766 * 0b001..RESAMPLE
54767 * 0b100..LOW
54768 * 0b111..HIGH
54769 * 0b110..RISE
54770 * 0b101..FALL
54771 */
54772#define IOMUXD_USDHC1_CMD_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_CMD_WAKEUP_CTRL_MASK)
54773#define IOMUXD_USDHC1_CMD_WAKEUP_MASK_MASK (0x400000U)
54774#define IOMUXD_USDHC1_CMD_WAKEUP_MASK_SHIFT (22U)
54775/*! WAKEUP_MASK - wakeup mask
54776 */
54777#define IOMUXD_USDHC1_CMD_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_CMD_WAKEUP_MASK_MASK)
54778#define IOMUXD_USDHC1_CMD_lp_config_MASK (0x1800000U)
54779#define IOMUXD_USDHC1_CMD_lp_config_SHIFT (23U)
54780/*! lp_config - lower power configuration
54781 * 0b01..EARLY_ISO
54782 * 0b10..LATE_ISO
54783 * 0b11..LATCH
54784 * 0b00..PASS
54785 */
54786#define IOMUXD_USDHC1_CMD_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_lp_config_SHIFT)) & IOMUXD_USDHC1_CMD_lp_config_MASK)
54787#define IOMUXD_USDHC1_CMD_sw_config_MASK (0x6000000U)
54788#define IOMUXD_USDHC1_CMD_sw_config_SHIFT (25U)
54789/*! sw_config - output and input configuration
54790 * 0b01..OPEN_DRAIN
54791 * 0b10..OPEN_DRAIN_INPUT
54792 * 0b11..INOUT
54793 * 0b00..DEFAULT
54794 */
54795#define IOMUXD_USDHC1_CMD_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_sw_config_SHIFT)) & IOMUXD_USDHC1_CMD_sw_config_MASK)
54796#define IOMUXD_USDHC1_CMD_mux_mode_MASK (0x38000000U)
54797#define IOMUXD_USDHC1_CMD_mux_mode_SHIFT (27U)
54798/*! mux_mode - mux_mode
54799 * 0b000..CONN.USDHC1.CMD
54800 * 0b001..CONN.NAND.CE0_B
54801 * 0b010..ADMA.MQS.R
54802 * 0b100..LSIO.GPIO4.IO24
54803 */
54804#define IOMUXD_USDHC1_CMD_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_mux_mode_SHIFT)) & IOMUXD_USDHC1_CMD_mux_mode_MASK)
54805#define IOMUXD_USDHC1_CMD_update_pad_ctl_MASK (0x40000000U)
54806#define IOMUXD_USDHC1_CMD_update_pad_ctl_SHIFT (30U)
54807/*! update_pad_ctl - update lock for pad control
54808 */
54809#define IOMUXD_USDHC1_CMD_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_CMD_update_pad_ctl_MASK)
54810#define IOMUXD_USDHC1_CMD_update_mux_mode_MASK (0x80000000U)
54811#define IOMUXD_USDHC1_CMD_update_mux_mode_SHIFT (31U)
54812/*! update_mux_mode - update lock for mux control
54813 */
54814#define IOMUXD_USDHC1_CMD_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_CMD_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_CMD_update_mux_mode_MASK)
54815/*! @} */
54816
54817/*! @name USDHC1_DATA0 - USDHC1_DATA0 */
54818/*! @{ */
54819#define IOMUXD_USDHC1_DATA0_PDRV_MASK (0x1U)
54820#define IOMUXD_USDHC1_DATA0_PDRV_SHIFT (0U)
54821/*! PDRV - Drive
54822 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
54823 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
54824 */
54825#define IOMUXD_USDHC1_DATA0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_PDRV_SHIFT)) & IOMUXD_USDHC1_DATA0_PDRV_MASK)
54826#define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_1_4_MASK (0x1EU)
54827#define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_1_4_SHIFT (1U)
54828/*! USDHC1_DATA0_reserved_1_4 - reserved
54829 */
54830#define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_1_4_MASK)
54831#define IOMUXD_USDHC1_DATA0_PULL_MASK (0x60U)
54832#define IOMUXD_USDHC1_DATA0_PULL_SHIFT (5U)
54833/*! PULL - Pull Down Pull Up
54834 * 0b10..pull down
54835 * 0b01..pull up
54836 * 0b00..Prohibited
54837 * 0b11..pull disabled
54838 */
54839#define IOMUXD_USDHC1_DATA0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_PULL_SHIFT)) & IOMUXD_USDHC1_DATA0_PULL_MASK)
54840#define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_7_18_MASK (0x7FF80U)
54841#define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_7_18_SHIFT (7U)
54842/*! USDHC1_DATA0_reserved_7_18 - reserved
54843 */
54844#define IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_DATA0_USDHC1_DATA0_reserved_7_18_MASK)
54845#define IOMUXD_USDHC1_DATA0_WAKEUP_CTRL_MASK (0x380000U)
54846#define IOMUXD_USDHC1_DATA0_WAKEUP_CTRL_SHIFT (19U)
54847/*! WAKEUP_CTRL - wakeup control
54848 * 0b000..OFF
54849 * 0b001..RESAMPLE
54850 * 0b100..LOW
54851 * 0b111..HIGH
54852 * 0b110..RISE
54853 * 0b101..FALL
54854 */
54855#define IOMUXD_USDHC1_DATA0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_DATA0_WAKEUP_CTRL_MASK)
54856#define IOMUXD_USDHC1_DATA0_WAKEUP_MASK_MASK (0x400000U)
54857#define IOMUXD_USDHC1_DATA0_WAKEUP_MASK_SHIFT (22U)
54858/*! WAKEUP_MASK - wakeup mask
54859 */
54860#define IOMUXD_USDHC1_DATA0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_DATA0_WAKEUP_MASK_MASK)
54861#define IOMUXD_USDHC1_DATA0_lp_config_MASK (0x1800000U)
54862#define IOMUXD_USDHC1_DATA0_lp_config_SHIFT (23U)
54863/*! lp_config - lower power configuration
54864 * 0b01..EARLY_ISO
54865 * 0b10..LATE_ISO
54866 * 0b11..LATCH
54867 * 0b00..PASS
54868 */
54869#define IOMUXD_USDHC1_DATA0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_lp_config_SHIFT)) & IOMUXD_USDHC1_DATA0_lp_config_MASK)
54870#define IOMUXD_USDHC1_DATA0_sw_config_MASK (0x6000000U)
54871#define IOMUXD_USDHC1_DATA0_sw_config_SHIFT (25U)
54872/*! sw_config - output and input configuration
54873 * 0b01..OPEN_DRAIN
54874 * 0b10..OPEN_DRAIN_INPUT
54875 * 0b11..INOUT
54876 * 0b00..DEFAULT
54877 */
54878#define IOMUXD_USDHC1_DATA0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_sw_config_SHIFT)) & IOMUXD_USDHC1_DATA0_sw_config_MASK)
54879#define IOMUXD_USDHC1_DATA0_mux_mode_MASK (0x38000000U)
54880#define IOMUXD_USDHC1_DATA0_mux_mode_SHIFT (27U)
54881/*! mux_mode - mux_mode
54882 * 0b000..CONN.USDHC1.DATA0
54883 * 0b001..CONN.NAND.CE1_B
54884 * 0b010..ADMA.MQS.L
54885 * 0b100..LSIO.GPIO4.IO25
54886 */
54887#define IOMUXD_USDHC1_DATA0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA0_mux_mode_MASK)
54888#define IOMUXD_USDHC1_DATA0_update_pad_ctl_MASK (0x40000000U)
54889#define IOMUXD_USDHC1_DATA0_update_pad_ctl_SHIFT (30U)
54890/*! update_pad_ctl - update lock for pad control
54891 */
54892#define IOMUXD_USDHC1_DATA0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_DATA0_update_pad_ctl_MASK)
54893#define IOMUXD_USDHC1_DATA0_update_mux_mode_MASK (0x80000000U)
54894#define IOMUXD_USDHC1_DATA0_update_mux_mode_SHIFT (31U)
54895/*! update_mux_mode - update lock for mux control
54896 */
54897#define IOMUXD_USDHC1_DATA0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA0_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA0_update_mux_mode_MASK)
54898/*! @} */
54899
54900/*! @name USDHC1_DATA1 - USDHC1_DATA1 */
54901/*! @{ */
54902#define IOMUXD_USDHC1_DATA1_PDRV_MASK (0x1U)
54903#define IOMUXD_USDHC1_DATA1_PDRV_SHIFT (0U)
54904/*! PDRV - Drive
54905 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
54906 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
54907 */
54908#define IOMUXD_USDHC1_DATA1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_PDRV_SHIFT)) & IOMUXD_USDHC1_DATA1_PDRV_MASK)
54909#define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_1_4_MASK (0x1EU)
54910#define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_1_4_SHIFT (1U)
54911/*! USDHC1_DATA1_reserved_1_4 - reserved
54912 */
54913#define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_1_4_MASK)
54914#define IOMUXD_USDHC1_DATA1_PULL_MASK (0x60U)
54915#define IOMUXD_USDHC1_DATA1_PULL_SHIFT (5U)
54916/*! PULL - Pull Down Pull Up
54917 * 0b10..pull down
54918 * 0b01..pull up
54919 * 0b00..Prohibited
54920 * 0b11..pull disabled
54921 */
54922#define IOMUXD_USDHC1_DATA1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_PULL_SHIFT)) & IOMUXD_USDHC1_DATA1_PULL_MASK)
54923#define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_7_18_MASK (0x7FF80U)
54924#define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_7_18_SHIFT (7U)
54925/*! USDHC1_DATA1_reserved_7_18 - reserved
54926 */
54927#define IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_DATA1_USDHC1_DATA1_reserved_7_18_MASK)
54928#define IOMUXD_USDHC1_DATA1_WAKEUP_CTRL_MASK (0x380000U)
54929#define IOMUXD_USDHC1_DATA1_WAKEUP_CTRL_SHIFT (19U)
54930/*! WAKEUP_CTRL - wakeup control
54931 * 0b000..OFF
54932 * 0b001..RESAMPLE
54933 * 0b100..LOW
54934 * 0b111..HIGH
54935 * 0b110..RISE
54936 * 0b101..FALL
54937 */
54938#define IOMUXD_USDHC1_DATA1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_DATA1_WAKEUP_CTRL_MASK)
54939#define IOMUXD_USDHC1_DATA1_WAKEUP_MASK_MASK (0x400000U)
54940#define IOMUXD_USDHC1_DATA1_WAKEUP_MASK_SHIFT (22U)
54941/*! WAKEUP_MASK - wakeup mask
54942 */
54943#define IOMUXD_USDHC1_DATA1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_DATA1_WAKEUP_MASK_MASK)
54944#define IOMUXD_USDHC1_DATA1_lp_config_MASK (0x1800000U)
54945#define IOMUXD_USDHC1_DATA1_lp_config_SHIFT (23U)
54946/*! lp_config - lower power configuration
54947 * 0b01..EARLY_ISO
54948 * 0b10..LATE_ISO
54949 * 0b11..LATCH
54950 * 0b00..PASS
54951 */
54952#define IOMUXD_USDHC1_DATA1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_lp_config_SHIFT)) & IOMUXD_USDHC1_DATA1_lp_config_MASK)
54953#define IOMUXD_USDHC1_DATA1_sw_config_MASK (0x6000000U)
54954#define IOMUXD_USDHC1_DATA1_sw_config_SHIFT (25U)
54955/*! sw_config - output and input configuration
54956 * 0b01..OPEN_DRAIN
54957 * 0b10..OPEN_DRAIN_INPUT
54958 * 0b11..INOUT
54959 * 0b00..DEFAULT
54960 */
54961#define IOMUXD_USDHC1_DATA1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_sw_config_SHIFT)) & IOMUXD_USDHC1_DATA1_sw_config_MASK)
54962#define IOMUXD_USDHC1_DATA1_mux_mode_MASK (0x38000000U)
54963#define IOMUXD_USDHC1_DATA1_mux_mode_SHIFT (27U)
54964/*! mux_mode - mux_mode
54965 * 0b000..CONN.USDHC1.DATA1
54966 * 0b001..CONN.NAND.RE_B
54967 * 0b010..ADMA.UART3.TX
54968 * 0b100..LSIO.GPIO4.IO26
54969 */
54970#define IOMUXD_USDHC1_DATA1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA1_mux_mode_MASK)
54971#define IOMUXD_USDHC1_DATA1_update_pad_ctl_MASK (0x40000000U)
54972#define IOMUXD_USDHC1_DATA1_update_pad_ctl_SHIFT (30U)
54973/*! update_pad_ctl - update lock for pad control
54974 */
54975#define IOMUXD_USDHC1_DATA1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_DATA1_update_pad_ctl_MASK)
54976#define IOMUXD_USDHC1_DATA1_update_mux_mode_MASK (0x80000000U)
54977#define IOMUXD_USDHC1_DATA1_update_mux_mode_SHIFT (31U)
54978/*! update_mux_mode - update lock for mux control
54979 */
54980#define IOMUXD_USDHC1_DATA1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA1_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA1_update_mux_mode_MASK)
54981/*! @} */
54982
54983/*! @name USDHC1_DATA2 - USDHC1_DATA2 */
54984/*! @{ */
54985#define IOMUXD_USDHC1_DATA2_PDRV_MASK (0x1U)
54986#define IOMUXD_USDHC1_DATA2_PDRV_SHIFT (0U)
54987/*! PDRV - Drive
54988 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
54989 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
54990 */
54991#define IOMUXD_USDHC1_DATA2_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_PDRV_SHIFT)) & IOMUXD_USDHC1_DATA2_PDRV_MASK)
54992#define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_1_4_MASK (0x1EU)
54993#define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_1_4_SHIFT (1U)
54994/*! USDHC1_DATA2_reserved_1_4 - reserved
54995 */
54996#define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_1_4_MASK)
54997#define IOMUXD_USDHC1_DATA2_PULL_MASK (0x60U)
54998#define IOMUXD_USDHC1_DATA2_PULL_SHIFT (5U)
54999/*! PULL - Pull Down Pull Up
55000 * 0b10..pull down
55001 * 0b01..pull up
55002 * 0b00..Prohibited
55003 * 0b11..pull disabled
55004 */
55005#define IOMUXD_USDHC1_DATA2_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_PULL_SHIFT)) & IOMUXD_USDHC1_DATA2_PULL_MASK)
55006#define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_7_18_MASK (0x7FF80U)
55007#define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_7_18_SHIFT (7U)
55008/*! USDHC1_DATA2_reserved_7_18 - reserved
55009 */
55010#define IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_DATA2_USDHC1_DATA2_reserved_7_18_MASK)
55011#define IOMUXD_USDHC1_DATA2_WAKEUP_CTRL_MASK (0x380000U)
55012#define IOMUXD_USDHC1_DATA2_WAKEUP_CTRL_SHIFT (19U)
55013/*! WAKEUP_CTRL - wakeup control
55014 * 0b000..OFF
55015 * 0b001..RESAMPLE
55016 * 0b100..LOW
55017 * 0b111..HIGH
55018 * 0b110..RISE
55019 * 0b101..FALL
55020 */
55021#define IOMUXD_USDHC1_DATA2_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_DATA2_WAKEUP_CTRL_MASK)
55022#define IOMUXD_USDHC1_DATA2_WAKEUP_MASK_MASK (0x400000U)
55023#define IOMUXD_USDHC1_DATA2_WAKEUP_MASK_SHIFT (22U)
55024/*! WAKEUP_MASK - wakeup mask
55025 */
55026#define IOMUXD_USDHC1_DATA2_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_DATA2_WAKEUP_MASK_MASK)
55027#define IOMUXD_USDHC1_DATA2_lp_config_MASK (0x1800000U)
55028#define IOMUXD_USDHC1_DATA2_lp_config_SHIFT (23U)
55029/*! lp_config - lower power configuration
55030 * 0b01..EARLY_ISO
55031 * 0b10..LATE_ISO
55032 * 0b11..LATCH
55033 * 0b00..PASS
55034 */
55035#define IOMUXD_USDHC1_DATA2_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_lp_config_SHIFT)) & IOMUXD_USDHC1_DATA2_lp_config_MASK)
55036#define IOMUXD_USDHC1_DATA2_sw_config_MASK (0x6000000U)
55037#define IOMUXD_USDHC1_DATA2_sw_config_SHIFT (25U)
55038/*! sw_config - output and input configuration
55039 * 0b01..OPEN_DRAIN
55040 * 0b10..OPEN_DRAIN_INPUT
55041 * 0b11..INOUT
55042 * 0b00..DEFAULT
55043 */
55044#define IOMUXD_USDHC1_DATA2_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_sw_config_SHIFT)) & IOMUXD_USDHC1_DATA2_sw_config_MASK)
55045#define IOMUXD_USDHC1_DATA2_mux_mode_MASK (0x38000000U)
55046#define IOMUXD_USDHC1_DATA2_mux_mode_SHIFT (27U)
55047/*! mux_mode - mux_mode
55048 * 0b000..CONN.USDHC1.DATA2
55049 * 0b001..CONN.NAND.WE_B
55050 * 0b010..ADMA.UART3.CTS_B
55051 * 0b100..LSIO.GPIO4.IO27
55052 */
55053#define IOMUXD_USDHC1_DATA2_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA2_mux_mode_MASK)
55054#define IOMUXD_USDHC1_DATA2_update_pad_ctl_MASK (0x40000000U)
55055#define IOMUXD_USDHC1_DATA2_update_pad_ctl_SHIFT (30U)
55056/*! update_pad_ctl - update lock for pad control
55057 */
55058#define IOMUXD_USDHC1_DATA2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_DATA2_update_pad_ctl_MASK)
55059#define IOMUXD_USDHC1_DATA2_update_mux_mode_MASK (0x80000000U)
55060#define IOMUXD_USDHC1_DATA2_update_mux_mode_SHIFT (31U)
55061/*! update_mux_mode - update lock for mux control
55062 */
55063#define IOMUXD_USDHC1_DATA2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA2_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA2_update_mux_mode_MASK)
55064/*! @} */
55065
55066/*! @name USDHC1_DATA3 - USDHC1_DATA3 */
55067/*! @{ */
55068#define IOMUXD_USDHC1_DATA3_PDRV_MASK (0x1U)
55069#define IOMUXD_USDHC1_DATA3_PDRV_SHIFT (0U)
55070/*! PDRV - Drive
55071 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
55072 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
55073 */
55074#define IOMUXD_USDHC1_DATA3_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_PDRV_SHIFT)) & IOMUXD_USDHC1_DATA3_PDRV_MASK)
55075#define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_1_4_MASK (0x1EU)
55076#define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_1_4_SHIFT (1U)
55077/*! USDHC1_DATA3_reserved_1_4 - reserved
55078 */
55079#define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_1_4_SHIFT)) & IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_1_4_MASK)
55080#define IOMUXD_USDHC1_DATA3_PULL_MASK (0x60U)
55081#define IOMUXD_USDHC1_DATA3_PULL_SHIFT (5U)
55082/*! PULL - Pull Down Pull Up
55083 * 0b10..pull down
55084 * 0b01..pull up
55085 * 0b00..Prohibited
55086 * 0b11..pull disabled
55087 */
55088#define IOMUXD_USDHC1_DATA3_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_PULL_SHIFT)) & IOMUXD_USDHC1_DATA3_PULL_MASK)
55089#define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_7_18_MASK (0x7FF80U)
55090#define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_7_18_SHIFT (7U)
55091/*! USDHC1_DATA3_reserved_7_18 - reserved
55092 */
55093#define IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_7_18_SHIFT)) & IOMUXD_USDHC1_DATA3_USDHC1_DATA3_reserved_7_18_MASK)
55094#define IOMUXD_USDHC1_DATA3_WAKEUP_CTRL_MASK (0x380000U)
55095#define IOMUXD_USDHC1_DATA3_WAKEUP_CTRL_SHIFT (19U)
55096/*! WAKEUP_CTRL - wakeup control
55097 * 0b000..OFF
55098 * 0b001..RESAMPLE
55099 * 0b100..LOW
55100 * 0b111..HIGH
55101 * 0b110..RISE
55102 * 0b101..FALL
55103 */
55104#define IOMUXD_USDHC1_DATA3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_WAKEUP_CTRL_SHIFT)) & IOMUXD_USDHC1_DATA3_WAKEUP_CTRL_MASK)
55105#define IOMUXD_USDHC1_DATA3_WAKEUP_MASK_MASK (0x400000U)
55106#define IOMUXD_USDHC1_DATA3_WAKEUP_MASK_SHIFT (22U)
55107/*! WAKEUP_MASK - wakeup mask
55108 */
55109#define IOMUXD_USDHC1_DATA3_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_WAKEUP_MASK_SHIFT)) & IOMUXD_USDHC1_DATA3_WAKEUP_MASK_MASK)
55110#define IOMUXD_USDHC1_DATA3_lp_config_MASK (0x1800000U)
55111#define IOMUXD_USDHC1_DATA3_lp_config_SHIFT (23U)
55112/*! lp_config - lower power configuration
55113 * 0b01..EARLY_ISO
55114 * 0b10..LATE_ISO
55115 * 0b11..LATCH
55116 * 0b00..PASS
55117 */
55118#define IOMUXD_USDHC1_DATA3_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_lp_config_SHIFT)) & IOMUXD_USDHC1_DATA3_lp_config_MASK)
55119#define IOMUXD_USDHC1_DATA3_sw_config_MASK (0x6000000U)
55120#define IOMUXD_USDHC1_DATA3_sw_config_SHIFT (25U)
55121/*! sw_config - output and input configuration
55122 * 0b01..OPEN_DRAIN
55123 * 0b10..OPEN_DRAIN_INPUT
55124 * 0b11..INOUT
55125 * 0b00..DEFAULT
55126 */
55127#define IOMUXD_USDHC1_DATA3_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_sw_config_SHIFT)) & IOMUXD_USDHC1_DATA3_sw_config_MASK)
55128#define IOMUXD_USDHC1_DATA3_mux_mode_MASK (0x38000000U)
55129#define IOMUXD_USDHC1_DATA3_mux_mode_SHIFT (27U)
55130/*! mux_mode - mux_mode
55131 * 0b000..CONN.USDHC1.DATA3
55132 * 0b001..CONN.NAND.ALE
55133 * 0b010..ADMA.UART3.RTS_B
55134 * 0b100..LSIO.GPIO4.IO28
55135 */
55136#define IOMUXD_USDHC1_DATA3_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA3_mux_mode_MASK)
55137#define IOMUXD_USDHC1_DATA3_update_pad_ctl_MASK (0x40000000U)
55138#define IOMUXD_USDHC1_DATA3_update_pad_ctl_SHIFT (30U)
55139/*! update_pad_ctl - update lock for pad control
55140 */
55141#define IOMUXD_USDHC1_DATA3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_update_pad_ctl_SHIFT)) & IOMUXD_USDHC1_DATA3_update_pad_ctl_MASK)
55142#define IOMUXD_USDHC1_DATA3_update_mux_mode_MASK (0x80000000U)
55143#define IOMUXD_USDHC1_DATA3_update_mux_mode_SHIFT (31U)
55144/*! update_mux_mode - update lock for mux control
55145 */
55146#define IOMUXD_USDHC1_DATA3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_USDHC1_DATA3_update_mux_mode_SHIFT)) & IOMUXD_USDHC1_DATA3_update_mux_mode_MASK)
55147/*! @} */
55148
55149/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3 - IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3 */
55150/*! @{ */
55151#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMP_MASK (0x7U)
55152#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMP_SHIFT (0U)
55153/*! COMP - COMP
55154 * 0b010..Fixed code mode
55155 * 0b100..High impedance mode
55156 * 0b110..Read mode
55157 * 0b000..Normal Mode
55158 * 0b001..Freeze Mode
55159 */
55160#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMP_MASK)
55161#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_FASTFRZ_EN_MASK (0x8U)
55162#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_FASTFRZ_EN_SHIFT (3U)
55163/*! FASTFRZ_EN - FASTFRZ_EN
55164 * 0b1..FASTFRZ signal is driven by output of subsystem
55165 * 0b0..FASTFRZ signal is gated to 0
55166 */
55167#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_FASTFRZ_EN_MASK)
55168#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4_MASK (0x10U)
55169#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4_SHIFT (4U)
55170/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4 - reserved
55171 */
55172#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_4_4_MASK)
55173#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCP_MASK (0x1E0U)
55174#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCP_SHIFT (5U)
55175/*! RASRCP - RASRCP
55176 * 0b0101..Reset Value
55177 */
55178#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCP_MASK)
55179#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCN_MASK (0x1E00U)
55180#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCN_SHIFT (9U)
55181/*! RASRCN - RASRCN
55182 * 0b1010..Reset Value
55183 */
55184#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_RASRCN_MASK)
55185#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SELECT_NASRC_MASK (0x2000U)
55186#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SELECT_NASRC_SHIFT (13U)
55187/*! SELECT_NASRC - SELECT_NASRC
55188 * 0b1..NASRCN value
55189 * 0b0..NASRCP value
55190 */
55191#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SELECT_NASRC_MASK)
55192#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMPOK_MASK (0x4000U)
55193#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMPOK_SHIFT (14U)
55194/*! COMPOK - COMPOK
55195 * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
55196 * 0b1..compensation cell in Normal mode and tracking PVT
55197 */
55198#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_COMPOK_MASK)
55199#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_READ_NASRC_MASK (0x78000U)
55200#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_READ_NASRC_SHIFT (15U)
55201/*! READ_NASRC - READ_NASRC
55202 * 0b0000..READ Only
55203 */
55204#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_READ_NASRC_MASK)
55205#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22_MASK (0x780000U)
55206#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22_SHIFT (19U)
55207/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22 - reserved
55208 */
55209#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_19_22_MASK)
55210#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SLEEP_MASK (0x1800000U)
55211#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SLEEP_SHIFT (23U)
55212/*! SLEEP - SLEEP
55213 * 0b11..Force into sleep mode
55214 * 0b00..NO
55215 * 0b01..EARLY
55216 * 0b10..LATE
55217 */
55218#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_SLEEP_MASK)
55219#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29_MASK (0x3E000000U)
55220#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29_SHIFT (25U)
55221/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29 - reserved
55222 */
55223#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_reserved_25_29_MASK)
55224#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_pad_ctl_MASK (0x40000000U)
55225#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_pad_ctl_SHIFT (30U)
55226/*! update_pad_ctl - update lock for pad control
55227 */
55228#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_pad_ctl_MASK)
55229#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_mux_mode_MASK (0x80000000U)
55230#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_mux_mode_SHIFT (31U)
55231/*! update_mux_mode - update lock for mux control
55232 */
55233#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_VSEL3_update_mux_mode_MASK)
55234/*! @} */
55235
55236/*! @name ENET0_RGMII_TXC - ENET0_RGMII_TXC */
55237/*! @{ */
55238#define IOMUXD_ENET0_RGMII_TXC_PDRV_MASK (0x1U)
55239#define IOMUXD_ENET0_RGMII_TXC_PDRV_SHIFT (0U)
55240/*! PDRV - Drive
55241 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
55242 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
55243 */
55244#define IOMUXD_ENET0_RGMII_TXC_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_PDRV_MASK)
55245#define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_1_4_MASK (0x1EU)
55246#define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_1_4_SHIFT (1U)
55247/*! ENET0_RGMII_TXC_reserved_1_4 - reserved
55248 */
55249#define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_1_4_MASK)
55250#define IOMUXD_ENET0_RGMII_TXC_PULL_MASK (0x60U)
55251#define IOMUXD_ENET0_RGMII_TXC_PULL_SHIFT (5U)
55252/*! PULL - Pull Down Pull Up
55253 * 0b10..pull down
55254 * 0b01..pull up
55255 * 0b00..Prohibited
55256 * 0b11..pull disabled
55257 */
55258#define IOMUXD_ENET0_RGMII_TXC_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_PULL_MASK)
55259#define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_7_18_MASK (0x7FF80U)
55260#define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_7_18_SHIFT (7U)
55261/*! ENET0_RGMII_TXC_reserved_7_18 - reserved
55262 */
55263#define IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_ENET0_RGMII_TXC_reserved_7_18_MASK)
55264#define IOMUXD_ENET0_RGMII_TXC_WAKEUP_CTRL_MASK (0x380000U)
55265#define IOMUXD_ENET0_RGMII_TXC_WAKEUP_CTRL_SHIFT (19U)
55266/*! WAKEUP_CTRL - wakeup control
55267 * 0b000..OFF
55268 * 0b001..RESAMPLE
55269 * 0b100..LOW
55270 * 0b111..HIGH
55271 * 0b110..RISE
55272 * 0b101..FALL
55273 */
55274#define IOMUXD_ENET0_RGMII_TXC_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_WAKEUP_CTRL_MASK)
55275#define IOMUXD_ENET0_RGMII_TXC_WAKEUP_MASK_MASK (0x400000U)
55276#define IOMUXD_ENET0_RGMII_TXC_WAKEUP_MASK_SHIFT (22U)
55277/*! WAKEUP_MASK - wakeup mask
55278 */
55279#define IOMUXD_ENET0_RGMII_TXC_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_WAKEUP_MASK_MASK)
55280#define IOMUXD_ENET0_RGMII_TXC_lp_config_MASK (0x1800000U)
55281#define IOMUXD_ENET0_RGMII_TXC_lp_config_SHIFT (23U)
55282/*! lp_config - lower power configuration
55283 * 0b01..EARLY_ISO
55284 * 0b10..LATE_ISO
55285 * 0b11..LATCH
55286 * 0b00..PASS
55287 */
55288#define IOMUXD_ENET0_RGMII_TXC_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_lp_config_MASK)
55289#define IOMUXD_ENET0_RGMII_TXC_sw_config_MASK (0x6000000U)
55290#define IOMUXD_ENET0_RGMII_TXC_sw_config_SHIFT (25U)
55291/*! sw_config - output and input configuration
55292 * 0b01..OPEN_DRAIN
55293 * 0b10..OPEN_DRAIN_INPUT
55294 * 0b11..INOUT
55295 * 0b00..DEFAULT
55296 */
55297#define IOMUXD_ENET0_RGMII_TXC_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_sw_config_MASK)
55298#define IOMUXD_ENET0_RGMII_TXC_mux_mode_MASK (0x38000000U)
55299#define IOMUXD_ENET0_RGMII_TXC_mux_mode_SHIFT (27U)
55300/*! mux_mode - mux_mode
55301 * 0b000..CONN.ENET0.RGMII_TXC
55302 * 0b001..CONN.ENET0.RCLK50M_OUT
55303 * 0b010..CONN.ENET0.RCLK50M_IN
55304 * 0b011..CONN.NAND.CE1_B
55305 * 0b100..LSIO.GPIO4.IO29
55306 */
55307#define IOMUXD_ENET0_RGMII_TXC_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_mux_mode_MASK)
55308#define IOMUXD_ENET0_RGMII_TXC_update_pad_ctl_MASK (0x40000000U)
55309#define IOMUXD_ENET0_RGMII_TXC_update_pad_ctl_SHIFT (30U)
55310/*! update_pad_ctl - update lock for pad control
55311 */
55312#define IOMUXD_ENET0_RGMII_TXC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_update_pad_ctl_MASK)
55313#define IOMUXD_ENET0_RGMII_TXC_update_mux_mode_MASK (0x80000000U)
55314#define IOMUXD_ENET0_RGMII_TXC_update_mux_mode_SHIFT (31U)
55315/*! update_mux_mode - update lock for mux control
55316 */
55317#define IOMUXD_ENET0_RGMII_TXC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXC_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXC_update_mux_mode_MASK)
55318/*! @} */
55319
55320/*! @name ENET0_RGMII_TX_CTL - ENET0_RGMII_TX_CTL */
55321/*! @{ */
55322#define IOMUXD_ENET0_RGMII_TX_CTL_PDRV_MASK (0x1U)
55323#define IOMUXD_ENET0_RGMII_TX_CTL_PDRV_SHIFT (0U)
55324/*! PDRV - Drive
55325 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
55326 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
55327 */
55328#define IOMUXD_ENET0_RGMII_TX_CTL_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_PDRV_MASK)
55329#define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_1_4_MASK (0x1EU)
55330#define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_1_4_SHIFT (1U)
55331/*! ENET0_RGMII_TX_CTL_reserved_1_4 - reserved
55332 */
55333#define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_1_4_MASK)
55334#define IOMUXD_ENET0_RGMII_TX_CTL_PULL_MASK (0x60U)
55335#define IOMUXD_ENET0_RGMII_TX_CTL_PULL_SHIFT (5U)
55336/*! PULL - Pull Down Pull Up
55337 * 0b10..pull down
55338 * 0b01..pull up
55339 * 0b00..Prohibited
55340 * 0b11..pull disabled
55341 */
55342#define IOMUXD_ENET0_RGMII_TX_CTL_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_PULL_MASK)
55343#define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_7_18_MASK (0x7FF80U)
55344#define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_7_18_SHIFT (7U)
55345/*! ENET0_RGMII_TX_CTL_reserved_7_18 - reserved
55346 */
55347#define IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_ENET0_RGMII_TX_CTL_reserved_7_18_MASK)
55348#define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_CTRL_MASK (0x380000U)
55349#define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_CTRL_SHIFT (19U)
55350/*! WAKEUP_CTRL - wakeup control
55351 * 0b000..OFF
55352 * 0b001..RESAMPLE
55353 * 0b100..LOW
55354 * 0b111..HIGH
55355 * 0b110..RISE
55356 * 0b101..FALL
55357 */
55358#define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_CTRL_MASK)
55359#define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_MASK_MASK (0x400000U)
55360#define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_MASK_SHIFT (22U)
55361/*! WAKEUP_MASK - wakeup mask
55362 */
55363#define IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_WAKEUP_MASK_MASK)
55364#define IOMUXD_ENET0_RGMII_TX_CTL_lp_config_MASK (0x1800000U)
55365#define IOMUXD_ENET0_RGMII_TX_CTL_lp_config_SHIFT (23U)
55366/*! lp_config - lower power configuration
55367 * 0b01..EARLY_ISO
55368 * 0b10..LATE_ISO
55369 * 0b11..LATCH
55370 * 0b00..PASS
55371 */
55372#define IOMUXD_ENET0_RGMII_TX_CTL_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_lp_config_MASK)
55373#define IOMUXD_ENET0_RGMII_TX_CTL_sw_config_MASK (0x6000000U)
55374#define IOMUXD_ENET0_RGMII_TX_CTL_sw_config_SHIFT (25U)
55375/*! sw_config - output and input configuration
55376 * 0b01..OPEN_DRAIN
55377 * 0b10..OPEN_DRAIN_INPUT
55378 * 0b11..INOUT
55379 * 0b00..DEFAULT
55380 */
55381#define IOMUXD_ENET0_RGMII_TX_CTL_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_sw_config_MASK)
55382#define IOMUXD_ENET0_RGMII_TX_CTL_mux_mode_MASK (0x38000000U)
55383#define IOMUXD_ENET0_RGMII_TX_CTL_mux_mode_SHIFT (27U)
55384/*! mux_mode - mux_mode
55385 * 0b000..CONN.ENET0.RGMII_TX_CTL
55386 * 0b011..CONN.USDHC1.RESET_B
55387 * 0b100..LSIO.GPIO4.IO30
55388 */
55389#define IOMUXD_ENET0_RGMII_TX_CTL_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_mux_mode_MASK)
55390#define IOMUXD_ENET0_RGMII_TX_CTL_update_pad_ctl_MASK (0x40000000U)
55391#define IOMUXD_ENET0_RGMII_TX_CTL_update_pad_ctl_SHIFT (30U)
55392/*! update_pad_ctl - update lock for pad control
55393 */
55394#define IOMUXD_ENET0_RGMII_TX_CTL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_update_pad_ctl_MASK)
55395#define IOMUXD_ENET0_RGMII_TX_CTL_update_mux_mode_MASK (0x80000000U)
55396#define IOMUXD_ENET0_RGMII_TX_CTL_update_mux_mode_SHIFT (31U)
55397/*! update_mux_mode - update lock for mux control
55398 */
55399#define IOMUXD_ENET0_RGMII_TX_CTL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TX_CTL_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TX_CTL_update_mux_mode_MASK)
55400/*! @} */
55401
55402/*! @name IOMUXD_GROUP_1_1 - na */
55403/*! @{ */
55404#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_VSELECT_MASK (0x1U)
55405#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_VSELECT_SHIFT (0U)
55406/*! USDHC1_VSELECT - wakeup from USDHC1_VSELECT
55407 */
55408#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_VSELECT_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_VSELECT_MASK)
55409#define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_1_1_MASK (0x2U)
55410#define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_1_1_SHIFT (1U)
55411/*! iomuxd_group_1_1_reserved_1_1 - reserved
55412 */
55413#define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_1_1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_1_1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_1_1_MASK)
55414#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_WP_MASK (0x4U)
55415#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_WP_SHIFT (2U)
55416/*! USDHC1_WP - wakeup from USDHC1_WP
55417 */
55418#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_WP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_WP_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_WP_MASK)
55419#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CD_B_MASK (0x8U)
55420#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CD_B_SHIFT (3U)
55421/*! USDHC1_CD_B - wakeup from USDHC1_CD_B
55422 */
55423#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CD_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CD_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CD_B_MASK)
55424#define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_4_5_MASK (0x30U)
55425#define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_4_5_SHIFT (4U)
55426/*! iomuxd_group_1_1_reserved_4_5 - reserved
55427 */
55428#define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_4_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_4_5_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_4_5_MASK)
55429#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CLK_MASK (0x40U)
55430#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CLK_SHIFT (6U)
55431/*! USDHC1_CLK - wakeup from USDHC1_CLK
55432 */
55433#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CLK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CLK_MASK)
55434#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CMD_MASK (0x80U)
55435#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CMD_SHIFT (7U)
55436/*! USDHC1_CMD - wakeup from USDHC1_CMD
55437 */
55438#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CMD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CMD_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_CMD_MASK)
55439#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA0_MASK (0x100U)
55440#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA0_SHIFT (8U)
55441/*! USDHC1_DATA0 - wakeup from USDHC1_DATA0
55442 */
55443#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA0_MASK)
55444#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA1_MASK (0x200U)
55445#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA1_SHIFT (9U)
55446/*! USDHC1_DATA1 - wakeup from USDHC1_DATA1
55447 */
55448#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA1_MASK)
55449#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA2_MASK (0x400U)
55450#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA2_SHIFT (10U)
55451/*! USDHC1_DATA2 - wakeup from USDHC1_DATA2
55452 */
55453#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA2_MASK)
55454#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA3_MASK (0x800U)
55455#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA3_SHIFT (11U)
55456/*! USDHC1_DATA3 - wakeup from USDHC1_DATA3
55457 */
55458#define IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA3_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_USDHC1_DATA3_MASK)
55459#define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_12_12_MASK (0x1000U)
55460#define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_12_12_SHIFT (12U)
55461/*! iomuxd_group_1_1_reserved_12_12 - reserved
55462 */
55463#define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_12_12_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_12_12_MASK)
55464#define IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TXC_MASK (0x2000U)
55465#define IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TXC_SHIFT (13U)
55466/*! ENET0_RGMII_TXC - wakeup from ENET0_RGMII_TXC
55467 */
55468#define IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TXC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TXC_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TXC_MASK)
55469#define IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TX_CTL_MASK (0x4000U)
55470#define IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TX_CTL_SHIFT (14U)
55471/*! ENET0_RGMII_TX_CTL - wakeup from ENET0_RGMII_TX_CTL
55472 */
55473#define IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TX_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TX_CTL_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_ENET0_RGMII_TX_CTL_MASK)
55474#define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_15_31_MASK (0xFFFF8000U)
55475#define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_15_31_SHIFT (15U)
55476/*! iomuxd_group_1_1_reserved_15_31 - reserved
55477 */
55478#define IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_1_iomuxd_group_1_1_reserved_15_31_MASK)
55479/*! @} */
55480
55481/*! @name ENET0_RGMII_TXD0 - ENET0_RGMII_TXD0 */
55482/*! @{ */
55483#define IOMUXD_ENET0_RGMII_TXD0_PDRV_MASK (0x1U)
55484#define IOMUXD_ENET0_RGMII_TXD0_PDRV_SHIFT (0U)
55485/*! PDRV - Drive
55486 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
55487 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
55488 */
55489#define IOMUXD_ENET0_RGMII_TXD0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_PDRV_MASK)
55490#define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_1_4_MASK (0x1EU)
55491#define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_1_4_SHIFT (1U)
55492/*! ENET0_RGMII_TXD0_reserved_1_4 - reserved
55493 */
55494#define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_1_4_MASK)
55495#define IOMUXD_ENET0_RGMII_TXD0_PULL_MASK (0x60U)
55496#define IOMUXD_ENET0_RGMII_TXD0_PULL_SHIFT (5U)
55497/*! PULL - Pull Down Pull Up
55498 * 0b10..pull down
55499 * 0b01..pull up
55500 * 0b00..Prohibited
55501 * 0b11..pull disabled
55502 */
55503#define IOMUXD_ENET0_RGMII_TXD0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_PULL_MASK)
55504#define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_7_18_MASK (0x7FF80U)
55505#define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_7_18_SHIFT (7U)
55506/*! ENET0_RGMII_TXD0_reserved_7_18 - reserved
55507 */
55508#define IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_ENET0_RGMII_TXD0_reserved_7_18_MASK)
55509#define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_CTRL_MASK (0x380000U)
55510#define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_CTRL_SHIFT (19U)
55511/*! WAKEUP_CTRL - wakeup control
55512 * 0b000..OFF
55513 * 0b001..RESAMPLE
55514 * 0b100..LOW
55515 * 0b111..HIGH
55516 * 0b110..RISE
55517 * 0b101..FALL
55518 */
55519#define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_WAKEUP_CTRL_MASK)
55520#define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_MASK_MASK (0x400000U)
55521#define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_MASK_SHIFT (22U)
55522/*! WAKEUP_MASK - wakeup mask
55523 */
55524#define IOMUXD_ENET0_RGMII_TXD0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_WAKEUP_MASK_MASK)
55525#define IOMUXD_ENET0_RGMII_TXD0_lp_config_MASK (0x1800000U)
55526#define IOMUXD_ENET0_RGMII_TXD0_lp_config_SHIFT (23U)
55527/*! lp_config - lower power configuration
55528 * 0b01..EARLY_ISO
55529 * 0b10..LATE_ISO
55530 * 0b11..LATCH
55531 * 0b00..PASS
55532 */
55533#define IOMUXD_ENET0_RGMII_TXD0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_lp_config_MASK)
55534#define IOMUXD_ENET0_RGMII_TXD0_sw_config_MASK (0x6000000U)
55535#define IOMUXD_ENET0_RGMII_TXD0_sw_config_SHIFT (25U)
55536/*! sw_config - output and input configuration
55537 * 0b01..OPEN_DRAIN
55538 * 0b10..OPEN_DRAIN_INPUT
55539 * 0b11..INOUT
55540 * 0b00..DEFAULT
55541 */
55542#define IOMUXD_ENET0_RGMII_TXD0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_sw_config_MASK)
55543#define IOMUXD_ENET0_RGMII_TXD0_mux_mode_MASK (0x38000000U)
55544#define IOMUXD_ENET0_RGMII_TXD0_mux_mode_SHIFT (27U)
55545/*! mux_mode - mux_mode
55546 * 0b000..CONN.ENET0.RGMII_TXD0
55547 * 0b011..CONN.USDHC1.VSELECT
55548 * 0b100..LSIO.GPIO4.IO31
55549 */
55550#define IOMUXD_ENET0_RGMII_TXD0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_mux_mode_MASK)
55551#define IOMUXD_ENET0_RGMII_TXD0_update_pad_ctl_MASK (0x40000000U)
55552#define IOMUXD_ENET0_RGMII_TXD0_update_pad_ctl_SHIFT (30U)
55553/*! update_pad_ctl - update lock for pad control
55554 */
55555#define IOMUXD_ENET0_RGMII_TXD0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_update_pad_ctl_MASK)
55556#define IOMUXD_ENET0_RGMII_TXD0_update_mux_mode_MASK (0x80000000U)
55557#define IOMUXD_ENET0_RGMII_TXD0_update_mux_mode_SHIFT (31U)
55558/*! update_mux_mode - update lock for mux control
55559 */
55560#define IOMUXD_ENET0_RGMII_TXD0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD0_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD0_update_mux_mode_MASK)
55561/*! @} */
55562
55563/*! @name ENET0_RGMII_TXD1 - ENET0_RGMII_TXD1 */
55564/*! @{ */
55565#define IOMUXD_ENET0_RGMII_TXD1_PDRV_MASK (0x1U)
55566#define IOMUXD_ENET0_RGMII_TXD1_PDRV_SHIFT (0U)
55567/*! PDRV - Drive
55568 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
55569 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
55570 */
55571#define IOMUXD_ENET0_RGMII_TXD1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_PDRV_MASK)
55572#define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_1_4_MASK (0x1EU)
55573#define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_1_4_SHIFT (1U)
55574/*! ENET0_RGMII_TXD1_reserved_1_4 - reserved
55575 */
55576#define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_1_4_MASK)
55577#define IOMUXD_ENET0_RGMII_TXD1_PULL_MASK (0x60U)
55578#define IOMUXD_ENET0_RGMII_TXD1_PULL_SHIFT (5U)
55579/*! PULL - Pull Down Pull Up
55580 * 0b10..pull down
55581 * 0b01..pull up
55582 * 0b00..Prohibited
55583 * 0b11..pull disabled
55584 */
55585#define IOMUXD_ENET0_RGMII_TXD1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_PULL_MASK)
55586#define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_7_18_MASK (0x7FF80U)
55587#define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_7_18_SHIFT (7U)
55588/*! ENET0_RGMII_TXD1_reserved_7_18 - reserved
55589 */
55590#define IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_ENET0_RGMII_TXD1_reserved_7_18_MASK)
55591#define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_CTRL_MASK (0x380000U)
55592#define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_CTRL_SHIFT (19U)
55593/*! WAKEUP_CTRL - wakeup control
55594 * 0b000..OFF
55595 * 0b001..RESAMPLE
55596 * 0b100..LOW
55597 * 0b111..HIGH
55598 * 0b110..RISE
55599 * 0b101..FALL
55600 */
55601#define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_WAKEUP_CTRL_MASK)
55602#define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_MASK_MASK (0x400000U)
55603#define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_MASK_SHIFT (22U)
55604/*! WAKEUP_MASK - wakeup mask
55605 */
55606#define IOMUXD_ENET0_RGMII_TXD1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_WAKEUP_MASK_MASK)
55607#define IOMUXD_ENET0_RGMII_TXD1_lp_config_MASK (0x1800000U)
55608#define IOMUXD_ENET0_RGMII_TXD1_lp_config_SHIFT (23U)
55609/*! lp_config - lower power configuration
55610 * 0b01..EARLY_ISO
55611 * 0b10..LATE_ISO
55612 * 0b11..LATCH
55613 * 0b00..PASS
55614 */
55615#define IOMUXD_ENET0_RGMII_TXD1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_lp_config_MASK)
55616#define IOMUXD_ENET0_RGMII_TXD1_sw_config_MASK (0x6000000U)
55617#define IOMUXD_ENET0_RGMII_TXD1_sw_config_SHIFT (25U)
55618/*! sw_config - output and input configuration
55619 * 0b01..OPEN_DRAIN
55620 * 0b10..OPEN_DRAIN_INPUT
55621 * 0b11..INOUT
55622 * 0b00..DEFAULT
55623 */
55624#define IOMUXD_ENET0_RGMII_TXD1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_sw_config_MASK)
55625#define IOMUXD_ENET0_RGMII_TXD1_mux_mode_MASK (0x38000000U)
55626#define IOMUXD_ENET0_RGMII_TXD1_mux_mode_SHIFT (27U)
55627/*! mux_mode - mux_mode
55628 * 0b000..CONN.ENET0.RGMII_TXD1
55629 * 0b011..CONN.USDHC1.WP
55630 * 0b100..LSIO.GPIO5.IO00
55631 */
55632#define IOMUXD_ENET0_RGMII_TXD1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_mux_mode_MASK)
55633#define IOMUXD_ENET0_RGMII_TXD1_update_pad_ctl_MASK (0x40000000U)
55634#define IOMUXD_ENET0_RGMII_TXD1_update_pad_ctl_SHIFT (30U)
55635/*! update_pad_ctl - update lock for pad control
55636 */
55637#define IOMUXD_ENET0_RGMII_TXD1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_update_pad_ctl_MASK)
55638#define IOMUXD_ENET0_RGMII_TXD1_update_mux_mode_MASK (0x80000000U)
55639#define IOMUXD_ENET0_RGMII_TXD1_update_mux_mode_SHIFT (31U)
55640/*! update_mux_mode - update lock for mux control
55641 */
55642#define IOMUXD_ENET0_RGMII_TXD1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD1_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD1_update_mux_mode_MASK)
55643/*! @} */
55644
55645/*! @name ENET0_RGMII_TXD2 - ENET0_RGMII_TXD2 */
55646/*! @{ */
55647#define IOMUXD_ENET0_RGMII_TXD2_PDRV_MASK (0x1U)
55648#define IOMUXD_ENET0_RGMII_TXD2_PDRV_SHIFT (0U)
55649/*! PDRV - Drive
55650 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
55651 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
55652 */
55653#define IOMUXD_ENET0_RGMII_TXD2_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_PDRV_MASK)
55654#define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_1_4_MASK (0x1EU)
55655#define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_1_4_SHIFT (1U)
55656/*! ENET0_RGMII_TXD2_reserved_1_4 - reserved
55657 */
55658#define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_1_4_MASK)
55659#define IOMUXD_ENET0_RGMII_TXD2_PULL_MASK (0x60U)
55660#define IOMUXD_ENET0_RGMII_TXD2_PULL_SHIFT (5U)
55661/*! PULL - Pull Down Pull Up
55662 * 0b10..pull down
55663 * 0b01..pull up
55664 * 0b00..Prohibited
55665 * 0b11..pull disabled
55666 */
55667#define IOMUXD_ENET0_RGMII_TXD2_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_PULL_MASK)
55668#define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_7_18_MASK (0x7FF80U)
55669#define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_7_18_SHIFT (7U)
55670/*! ENET0_RGMII_TXD2_reserved_7_18 - reserved
55671 */
55672#define IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_ENET0_RGMII_TXD2_reserved_7_18_MASK)
55673#define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_CTRL_MASK (0x380000U)
55674#define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_CTRL_SHIFT (19U)
55675/*! WAKEUP_CTRL - wakeup control
55676 * 0b000..OFF
55677 * 0b001..RESAMPLE
55678 * 0b100..LOW
55679 * 0b111..HIGH
55680 * 0b110..RISE
55681 * 0b101..FALL
55682 */
55683#define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_WAKEUP_CTRL_MASK)
55684#define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_MASK_MASK (0x400000U)
55685#define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_MASK_SHIFT (22U)
55686/*! WAKEUP_MASK - wakeup mask
55687 */
55688#define IOMUXD_ENET0_RGMII_TXD2_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_WAKEUP_MASK_MASK)
55689#define IOMUXD_ENET0_RGMII_TXD2_lp_config_MASK (0x1800000U)
55690#define IOMUXD_ENET0_RGMII_TXD2_lp_config_SHIFT (23U)
55691/*! lp_config - lower power configuration
55692 * 0b01..EARLY_ISO
55693 * 0b10..LATE_ISO
55694 * 0b11..LATCH
55695 * 0b00..PASS
55696 */
55697#define IOMUXD_ENET0_RGMII_TXD2_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_lp_config_MASK)
55698#define IOMUXD_ENET0_RGMII_TXD2_sw_config_MASK (0x6000000U)
55699#define IOMUXD_ENET0_RGMII_TXD2_sw_config_SHIFT (25U)
55700/*! sw_config - output and input configuration
55701 * 0b01..OPEN_DRAIN
55702 * 0b10..OPEN_DRAIN_INPUT
55703 * 0b11..INOUT
55704 * 0b00..DEFAULT
55705 */
55706#define IOMUXD_ENET0_RGMII_TXD2_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_sw_config_MASK)
55707#define IOMUXD_ENET0_RGMII_TXD2_mux_mode_MASK (0x38000000U)
55708#define IOMUXD_ENET0_RGMII_TXD2_mux_mode_SHIFT (27U)
55709/*! mux_mode - mux_mode
55710 * 0b000..CONN.ENET0.RGMII_TXD2
55711 * 0b001..CONN.MLB.CLK
55712 * 0b010..CONN.NAND.CE0_B
55713 * 0b011..CONN.USDHC1.CD_B
55714 * 0b100..LSIO.GPIO5.IO01
55715 */
55716#define IOMUXD_ENET0_RGMII_TXD2_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_mux_mode_MASK)
55717#define IOMUXD_ENET0_RGMII_TXD2_update_pad_ctl_MASK (0x40000000U)
55718#define IOMUXD_ENET0_RGMII_TXD2_update_pad_ctl_SHIFT (30U)
55719/*! update_pad_ctl - update lock for pad control
55720 */
55721#define IOMUXD_ENET0_RGMII_TXD2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_update_pad_ctl_MASK)
55722#define IOMUXD_ENET0_RGMII_TXD2_update_mux_mode_MASK (0x80000000U)
55723#define IOMUXD_ENET0_RGMII_TXD2_update_mux_mode_SHIFT (31U)
55724/*! update_mux_mode - update lock for mux control
55725 */
55726#define IOMUXD_ENET0_RGMII_TXD2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD2_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD2_update_mux_mode_MASK)
55727/*! @} */
55728
55729/*! @name ENET0_RGMII_TXD3 - ENET0_RGMII_TXD3 */
55730/*! @{ */
55731#define IOMUXD_ENET0_RGMII_TXD3_PDRV_MASK (0x1U)
55732#define IOMUXD_ENET0_RGMII_TXD3_PDRV_SHIFT (0U)
55733/*! PDRV - Drive
55734 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
55735 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
55736 */
55737#define IOMUXD_ENET0_RGMII_TXD3_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_PDRV_MASK)
55738#define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_1_4_MASK (0x1EU)
55739#define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_1_4_SHIFT (1U)
55740/*! ENET0_RGMII_TXD3_reserved_1_4 - reserved
55741 */
55742#define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_1_4_MASK)
55743#define IOMUXD_ENET0_RGMII_TXD3_PULL_MASK (0x60U)
55744#define IOMUXD_ENET0_RGMII_TXD3_PULL_SHIFT (5U)
55745/*! PULL - Pull Down Pull Up
55746 * 0b10..pull down
55747 * 0b01..pull up
55748 * 0b00..Prohibited
55749 * 0b11..pull disabled
55750 */
55751#define IOMUXD_ENET0_RGMII_TXD3_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_PULL_MASK)
55752#define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_7_18_MASK (0x7FF80U)
55753#define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_7_18_SHIFT (7U)
55754/*! ENET0_RGMII_TXD3_reserved_7_18 - reserved
55755 */
55756#define IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_ENET0_RGMII_TXD3_reserved_7_18_MASK)
55757#define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_CTRL_MASK (0x380000U)
55758#define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_CTRL_SHIFT (19U)
55759/*! WAKEUP_CTRL - wakeup control
55760 * 0b000..OFF
55761 * 0b001..RESAMPLE
55762 * 0b100..LOW
55763 * 0b111..HIGH
55764 * 0b110..RISE
55765 * 0b101..FALL
55766 */
55767#define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_WAKEUP_CTRL_MASK)
55768#define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_MASK_MASK (0x400000U)
55769#define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_MASK_SHIFT (22U)
55770/*! WAKEUP_MASK - wakeup mask
55771 */
55772#define IOMUXD_ENET0_RGMII_TXD3_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_WAKEUP_MASK_MASK)
55773#define IOMUXD_ENET0_RGMII_TXD3_lp_config_MASK (0x1800000U)
55774#define IOMUXD_ENET0_RGMII_TXD3_lp_config_SHIFT (23U)
55775/*! lp_config - lower power configuration
55776 * 0b01..EARLY_ISO
55777 * 0b10..LATE_ISO
55778 * 0b11..LATCH
55779 * 0b00..PASS
55780 */
55781#define IOMUXD_ENET0_RGMII_TXD3_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_lp_config_MASK)
55782#define IOMUXD_ENET0_RGMII_TXD3_sw_config_MASK (0x6000000U)
55783#define IOMUXD_ENET0_RGMII_TXD3_sw_config_SHIFT (25U)
55784/*! sw_config - output and input configuration
55785 * 0b01..OPEN_DRAIN
55786 * 0b10..OPEN_DRAIN_INPUT
55787 * 0b11..INOUT
55788 * 0b00..DEFAULT
55789 */
55790#define IOMUXD_ENET0_RGMII_TXD3_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_sw_config_MASK)
55791#define IOMUXD_ENET0_RGMII_TXD3_mux_mode_MASK (0x38000000U)
55792#define IOMUXD_ENET0_RGMII_TXD3_mux_mode_SHIFT (27U)
55793/*! mux_mode - mux_mode
55794 * 0b000..CONN.ENET0.RGMII_TXD3
55795 * 0b001..CONN.MLB.SIG
55796 * 0b010..CONN.NAND.RE_B
55797 * 0b100..LSIO.GPIO5.IO02
55798 */
55799#define IOMUXD_ENET0_RGMII_TXD3_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_mux_mode_MASK)
55800#define IOMUXD_ENET0_RGMII_TXD3_update_pad_ctl_MASK (0x40000000U)
55801#define IOMUXD_ENET0_RGMII_TXD3_update_pad_ctl_SHIFT (30U)
55802/*! update_pad_ctl - update lock for pad control
55803 */
55804#define IOMUXD_ENET0_RGMII_TXD3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_update_pad_ctl_MASK)
55805#define IOMUXD_ENET0_RGMII_TXD3_update_mux_mode_MASK (0x80000000U)
55806#define IOMUXD_ENET0_RGMII_TXD3_update_mux_mode_SHIFT (31U)
55807/*! update_mux_mode - update lock for mux control
55808 */
55809#define IOMUXD_ENET0_RGMII_TXD3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_TXD3_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_TXD3_update_mux_mode_MASK)
55810/*! @} */
55811
55812/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 - IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 */
55813/*! @{ */
55814#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMP_MASK (0x7U)
55815#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMP_SHIFT (0U)
55816/*! COMP - COMP
55817 * 0b010..Fixed code mode
55818 * 0b100..High impedance mode
55819 * 0b110..Read mode
55820 * 0b000..Normal Mode
55821 * 0b001..Freeze Mode
55822 */
55823#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMP_MASK)
55824#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_FASTFRZ_EN_MASK (0x8U)
55825#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_FASTFRZ_EN_SHIFT (3U)
55826/*! FASTFRZ_EN - FASTFRZ_EN
55827 * 0b1..FASTFRZ signal is driven by output of subsystem
55828 * 0b0..FASTFRZ signal is gated to 0
55829 */
55830#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_FASTFRZ_EN_MASK)
55831#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PSW_OVR_MASK (0x10U)
55832#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PSW_OVR_SHIFT (4U)
55833/*! PSW_OVR - PSW_OVR
55834 * 0b1..override output of voltage detector when using 2.5V IO operation
55835 * 0b0..selection coming from voltage detector cell for 1.8V or 3.3V IO operation
55836 */
55837#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PSW_OVR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PSW_OVR_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PSW_OVR_MASK)
55838#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCP_MASK (0x1E0U)
55839#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCP_SHIFT (5U)
55840/*! RASRCP - RASRCP
55841 * 0b0101..Reset Value
55842 */
55843#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCP_MASK)
55844#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCN_MASK (0x1E00U)
55845#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCN_SHIFT (9U)
55846/*! RASRCN - RASRCN
55847 * 0b1010..Reset Value
55848 */
55849#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_RASRCN_MASK)
55850#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SELECT_NASRC_MASK (0x2000U)
55851#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SELECT_NASRC_SHIFT (13U)
55852/*! SELECT_NASRC - SELECT_NASRC
55853 * 0b1..NASRCN value
55854 * 0b0..NASRCP value
55855 */
55856#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SELECT_NASRC_MASK)
55857#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMPOK_MASK (0x4000U)
55858#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMPOK_SHIFT (14U)
55859/*! COMPOK - COMPOK
55860 * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
55861 * 0b1..compensation cell in Normal mode and tracking PVT
55862 */
55863#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_COMPOK_MASK)
55864#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_READ_NASRC_MASK (0x78000U)
55865#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_READ_NASRC_SHIFT (15U)
55866/*! READ_NASRC - READ_NASRC
55867 * 0b0000..READ Only
55868 */
55869#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_READ_NASRC_MASK)
55870#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_19_22_MASK (0x780000U)
55871#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_19_22_SHIFT (19U)
55872/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_19_22 - reserved
55873 */
55874#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_19_22_MASK)
55875#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SLEEP_MASK (0x1800000U)
55876#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SLEEP_SHIFT (23U)
55877/*! SLEEP - SLEEP
55878 * 0b11..LAST
55879 * 0b00..NO
55880 * 0b01..EARLY
55881 * 0b10..LATE
55882 */
55883#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_SLEEP_MASK)
55884#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_25_29_MASK (0x3E000000U)
55885#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_25_29_SHIFT (25U)
55886/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_25_29 - reserved
55887 */
55888#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_reserved_25_29_MASK)
55889#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_pad_ctl_MASK (0x40000000U)
55890#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_pad_ctl_SHIFT (30U)
55891/*! update_pad_ctl - update lock for pad control
55892 */
55893#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_pad_ctl_MASK)
55894#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_mux_mode_MASK (0x80000000U)
55895#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_mux_mode_SHIFT (31U)
55896/*! update_mux_mode - update lock for mux control
55897 */
55898#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_update_mux_mode_MASK)
55899/*! @} */
55900
55901/*! @name ENET0_RGMII_RXC - ENET0_RGMII_RXC */
55902/*! @{ */
55903#define IOMUXD_ENET0_RGMII_RXC_PDRV_MASK (0x1U)
55904#define IOMUXD_ENET0_RGMII_RXC_PDRV_SHIFT (0U)
55905/*! PDRV - Drive
55906 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
55907 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
55908 */
55909#define IOMUXD_ENET0_RGMII_RXC_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_PDRV_MASK)
55910#define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_1_4_MASK (0x1EU)
55911#define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_1_4_SHIFT (1U)
55912/*! ENET0_RGMII_RXC_reserved_1_4 - reserved
55913 */
55914#define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_1_4_MASK)
55915#define IOMUXD_ENET0_RGMII_RXC_PULL_MASK (0x60U)
55916#define IOMUXD_ENET0_RGMII_RXC_PULL_SHIFT (5U)
55917/*! PULL - Pull Down Pull Up
55918 * 0b10..pull down
55919 * 0b01..pull up
55920 * 0b00..Prohibited
55921 * 0b11..pull disabled
55922 */
55923#define IOMUXD_ENET0_RGMII_RXC_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_PULL_MASK)
55924#define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_7_18_MASK (0x7FF80U)
55925#define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_7_18_SHIFT (7U)
55926/*! ENET0_RGMII_RXC_reserved_7_18 - reserved
55927 */
55928#define IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_ENET0_RGMII_RXC_reserved_7_18_MASK)
55929#define IOMUXD_ENET0_RGMII_RXC_WAKEUP_CTRL_MASK (0x380000U)
55930#define IOMUXD_ENET0_RGMII_RXC_WAKEUP_CTRL_SHIFT (19U)
55931/*! WAKEUP_CTRL - wakeup control
55932 * 0b000..OFF
55933 * 0b001..RESAMPLE
55934 * 0b100..LOW
55935 * 0b111..HIGH
55936 * 0b110..RISE
55937 * 0b101..FALL
55938 */
55939#define IOMUXD_ENET0_RGMII_RXC_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_WAKEUP_CTRL_MASK)
55940#define IOMUXD_ENET0_RGMII_RXC_WAKEUP_MASK_MASK (0x400000U)
55941#define IOMUXD_ENET0_RGMII_RXC_WAKEUP_MASK_SHIFT (22U)
55942/*! WAKEUP_MASK - wakeup mask
55943 */
55944#define IOMUXD_ENET0_RGMII_RXC_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_WAKEUP_MASK_MASK)
55945#define IOMUXD_ENET0_RGMII_RXC_lp_config_MASK (0x1800000U)
55946#define IOMUXD_ENET0_RGMII_RXC_lp_config_SHIFT (23U)
55947/*! lp_config - lower power configuration
55948 * 0b01..EARLY_ISO
55949 * 0b10..LATE_ISO
55950 * 0b11..LATCH
55951 * 0b00..PASS
55952 */
55953#define IOMUXD_ENET0_RGMII_RXC_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_lp_config_MASK)
55954#define IOMUXD_ENET0_RGMII_RXC_sw_config_MASK (0x6000000U)
55955#define IOMUXD_ENET0_RGMII_RXC_sw_config_SHIFT (25U)
55956/*! sw_config - output and input configuration
55957 * 0b01..OPEN_DRAIN
55958 * 0b10..OPEN_DRAIN_INPUT
55959 * 0b11..INOUT
55960 * 0b00..DEFAULT
55961 */
55962#define IOMUXD_ENET0_RGMII_RXC_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_sw_config_MASK)
55963#define IOMUXD_ENET0_RGMII_RXC_mux_mode_MASK (0x38000000U)
55964#define IOMUXD_ENET0_RGMII_RXC_mux_mode_SHIFT (27U)
55965/*! mux_mode - mux_mode
55966 * 0b000..CONN.ENET0.RGMII_RXC
55967 * 0b001..CONN.MLB.DATA
55968 * 0b010..CONN.NAND.WE_B
55969 * 0b011..CONN.USDHC1.CLK
55970 * 0b100..LSIO.GPIO5.IO03
55971 */
55972#define IOMUXD_ENET0_RGMII_RXC_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_mux_mode_MASK)
55973#define IOMUXD_ENET0_RGMII_RXC_update_pad_ctl_MASK (0x40000000U)
55974#define IOMUXD_ENET0_RGMII_RXC_update_pad_ctl_SHIFT (30U)
55975/*! update_pad_ctl - update lock for pad control
55976 */
55977#define IOMUXD_ENET0_RGMII_RXC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_update_pad_ctl_MASK)
55978#define IOMUXD_ENET0_RGMII_RXC_update_mux_mode_MASK (0x80000000U)
55979#define IOMUXD_ENET0_RGMII_RXC_update_mux_mode_SHIFT (31U)
55980/*! update_mux_mode - update lock for mux control
55981 */
55982#define IOMUXD_ENET0_RGMII_RXC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXC_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXC_update_mux_mode_MASK)
55983/*! @} */
55984
55985/*! @name ENET0_RGMII_RX_CTL - ENET0_RGMII_RX_CTL */
55986/*! @{ */
55987#define IOMUXD_ENET0_RGMII_RX_CTL_PDRV_MASK (0x1U)
55988#define IOMUXD_ENET0_RGMII_RX_CTL_PDRV_SHIFT (0U)
55989/*! PDRV - Drive
55990 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
55991 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
55992 */
55993#define IOMUXD_ENET0_RGMII_RX_CTL_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_PDRV_MASK)
55994#define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_1_4_MASK (0x1EU)
55995#define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_1_4_SHIFT (1U)
55996/*! ENET0_RGMII_RX_CTL_reserved_1_4 - reserved
55997 */
55998#define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_1_4_MASK)
55999#define IOMUXD_ENET0_RGMII_RX_CTL_PULL_MASK (0x60U)
56000#define IOMUXD_ENET0_RGMII_RX_CTL_PULL_SHIFT (5U)
56001/*! PULL - Pull Down Pull Up
56002 * 0b10..pull down
56003 * 0b01..pull up
56004 * 0b00..Prohibited
56005 * 0b11..pull disabled
56006 */
56007#define IOMUXD_ENET0_RGMII_RX_CTL_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_PULL_MASK)
56008#define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_7_18_MASK (0x7FF80U)
56009#define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_7_18_SHIFT (7U)
56010/*! ENET0_RGMII_RX_CTL_reserved_7_18 - reserved
56011 */
56012#define IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_ENET0_RGMII_RX_CTL_reserved_7_18_MASK)
56013#define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_CTRL_MASK (0x380000U)
56014#define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_CTRL_SHIFT (19U)
56015/*! WAKEUP_CTRL - wakeup control
56016 * 0b000..OFF
56017 * 0b001..RESAMPLE
56018 * 0b100..LOW
56019 * 0b111..HIGH
56020 * 0b110..RISE
56021 * 0b101..FALL
56022 */
56023#define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_CTRL_MASK)
56024#define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_MASK_MASK (0x400000U)
56025#define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_MASK_SHIFT (22U)
56026/*! WAKEUP_MASK - wakeup mask
56027 */
56028#define IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_WAKEUP_MASK_MASK)
56029#define IOMUXD_ENET0_RGMII_RX_CTL_lp_config_MASK (0x1800000U)
56030#define IOMUXD_ENET0_RGMII_RX_CTL_lp_config_SHIFT (23U)
56031/*! lp_config - lower power configuration
56032 * 0b01..EARLY_ISO
56033 * 0b10..LATE_ISO
56034 * 0b11..LATCH
56035 * 0b00..PASS
56036 */
56037#define IOMUXD_ENET0_RGMII_RX_CTL_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_lp_config_MASK)
56038#define IOMUXD_ENET0_RGMII_RX_CTL_sw_config_MASK (0x6000000U)
56039#define IOMUXD_ENET0_RGMII_RX_CTL_sw_config_SHIFT (25U)
56040/*! sw_config - output and input configuration
56041 * 0b01..OPEN_DRAIN
56042 * 0b10..OPEN_DRAIN_INPUT
56043 * 0b11..INOUT
56044 * 0b00..DEFAULT
56045 */
56046#define IOMUXD_ENET0_RGMII_RX_CTL_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_sw_config_MASK)
56047#define IOMUXD_ENET0_RGMII_RX_CTL_mux_mode_MASK (0x38000000U)
56048#define IOMUXD_ENET0_RGMII_RX_CTL_mux_mode_SHIFT (27U)
56049/*! mux_mode - mux_mode
56050 * 0b000..CONN.ENET0.RGMII_RX_CTL
56051 * 0b011..CONN.USDHC1.CMD
56052 * 0b100..LSIO.GPIO5.IO04
56053 */
56054#define IOMUXD_ENET0_RGMII_RX_CTL_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_mux_mode_MASK)
56055#define IOMUXD_ENET0_RGMII_RX_CTL_update_pad_ctl_MASK (0x40000000U)
56056#define IOMUXD_ENET0_RGMII_RX_CTL_update_pad_ctl_SHIFT (30U)
56057/*! update_pad_ctl - update lock for pad control
56058 */
56059#define IOMUXD_ENET0_RGMII_RX_CTL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_update_pad_ctl_MASK)
56060#define IOMUXD_ENET0_RGMII_RX_CTL_update_mux_mode_MASK (0x80000000U)
56061#define IOMUXD_ENET0_RGMII_RX_CTL_update_mux_mode_SHIFT (31U)
56062/*! update_mux_mode - update lock for mux control
56063 */
56064#define IOMUXD_ENET0_RGMII_RX_CTL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RX_CTL_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RX_CTL_update_mux_mode_MASK)
56065/*! @} */
56066
56067/*! @name ENET0_RGMII_RXD0 - ENET0_RGMII_RXD0 */
56068/*! @{ */
56069#define IOMUXD_ENET0_RGMII_RXD0_PDRV_MASK (0x1U)
56070#define IOMUXD_ENET0_RGMII_RXD0_PDRV_SHIFT (0U)
56071/*! PDRV - Drive
56072 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
56073 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
56074 */
56075#define IOMUXD_ENET0_RGMII_RXD0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_PDRV_MASK)
56076#define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_1_4_MASK (0x1EU)
56077#define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_1_4_SHIFT (1U)
56078/*! ENET0_RGMII_RXD0_reserved_1_4 - reserved
56079 */
56080#define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_1_4_MASK)
56081#define IOMUXD_ENET0_RGMII_RXD0_PULL_MASK (0x60U)
56082#define IOMUXD_ENET0_RGMII_RXD0_PULL_SHIFT (5U)
56083/*! PULL - Pull Down Pull Up
56084 * 0b10..pull down
56085 * 0b01..pull up
56086 * 0b00..Prohibited
56087 * 0b11..pull disabled
56088 */
56089#define IOMUXD_ENET0_RGMII_RXD0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_PULL_MASK)
56090#define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_7_18_MASK (0x7FF80U)
56091#define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_7_18_SHIFT (7U)
56092/*! ENET0_RGMII_RXD0_reserved_7_18 - reserved
56093 */
56094#define IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_ENET0_RGMII_RXD0_reserved_7_18_MASK)
56095#define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_CTRL_MASK (0x380000U)
56096#define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_CTRL_SHIFT (19U)
56097/*! WAKEUP_CTRL - wakeup control
56098 * 0b000..OFF
56099 * 0b001..RESAMPLE
56100 * 0b100..LOW
56101 * 0b111..HIGH
56102 * 0b110..RISE
56103 * 0b101..FALL
56104 */
56105#define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_WAKEUP_CTRL_MASK)
56106#define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_MASK_MASK (0x400000U)
56107#define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_MASK_SHIFT (22U)
56108/*! WAKEUP_MASK - wakeup mask
56109 */
56110#define IOMUXD_ENET0_RGMII_RXD0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_WAKEUP_MASK_MASK)
56111#define IOMUXD_ENET0_RGMII_RXD0_lp_config_MASK (0x1800000U)
56112#define IOMUXD_ENET0_RGMII_RXD0_lp_config_SHIFT (23U)
56113/*! lp_config - lower power configuration
56114 * 0b01..EARLY_ISO
56115 * 0b10..LATE_ISO
56116 * 0b11..LATCH
56117 * 0b00..PASS
56118 */
56119#define IOMUXD_ENET0_RGMII_RXD0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_lp_config_MASK)
56120#define IOMUXD_ENET0_RGMII_RXD0_sw_config_MASK (0x6000000U)
56121#define IOMUXD_ENET0_RGMII_RXD0_sw_config_SHIFT (25U)
56122/*! sw_config - output and input configuration
56123 * 0b01..OPEN_DRAIN
56124 * 0b10..OPEN_DRAIN_INPUT
56125 * 0b11..INOUT
56126 * 0b00..DEFAULT
56127 */
56128#define IOMUXD_ENET0_RGMII_RXD0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_sw_config_MASK)
56129#define IOMUXD_ENET0_RGMII_RXD0_mux_mode_MASK (0x38000000U)
56130#define IOMUXD_ENET0_RGMII_RXD0_mux_mode_SHIFT (27U)
56131/*! mux_mode - mux_mode
56132 * 0b000..CONN.ENET0.RGMII_RXD0
56133 * 0b011..CONN.USDHC1.DATA0
56134 * 0b100..LSIO.GPIO5.IO05
56135 */
56136#define IOMUXD_ENET0_RGMII_RXD0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_mux_mode_MASK)
56137#define IOMUXD_ENET0_RGMII_RXD0_update_pad_ctl_MASK (0x40000000U)
56138#define IOMUXD_ENET0_RGMII_RXD0_update_pad_ctl_SHIFT (30U)
56139/*! update_pad_ctl - update lock for pad control
56140 */
56141#define IOMUXD_ENET0_RGMII_RXD0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_update_pad_ctl_MASK)
56142#define IOMUXD_ENET0_RGMII_RXD0_update_mux_mode_MASK (0x80000000U)
56143#define IOMUXD_ENET0_RGMII_RXD0_update_mux_mode_SHIFT (31U)
56144/*! update_mux_mode - update lock for mux control
56145 */
56146#define IOMUXD_ENET0_RGMII_RXD0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD0_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD0_update_mux_mode_MASK)
56147/*! @} */
56148
56149/*! @name ENET0_RGMII_RXD1 - ENET0_RGMII_RXD1 */
56150/*! @{ */
56151#define IOMUXD_ENET0_RGMII_RXD1_PDRV_MASK (0x1U)
56152#define IOMUXD_ENET0_RGMII_RXD1_PDRV_SHIFT (0U)
56153/*! PDRV - Drive
56154 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
56155 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
56156 */
56157#define IOMUXD_ENET0_RGMII_RXD1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_PDRV_MASK)
56158#define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_1_4_MASK (0x1EU)
56159#define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_1_4_SHIFT (1U)
56160/*! ENET0_RGMII_RXD1_reserved_1_4 - reserved
56161 */
56162#define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_1_4_MASK)
56163#define IOMUXD_ENET0_RGMII_RXD1_PULL_MASK (0x60U)
56164#define IOMUXD_ENET0_RGMII_RXD1_PULL_SHIFT (5U)
56165/*! PULL - Pull Down Pull Up
56166 * 0b10..pull down
56167 * 0b01..pull up
56168 * 0b00..Prohibited
56169 * 0b11..pull disabled
56170 */
56171#define IOMUXD_ENET0_RGMII_RXD1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_PULL_MASK)
56172#define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_7_18_MASK (0x7FF80U)
56173#define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_7_18_SHIFT (7U)
56174/*! ENET0_RGMII_RXD1_reserved_7_18 - reserved
56175 */
56176#define IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_ENET0_RGMII_RXD1_reserved_7_18_MASK)
56177#define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_CTRL_MASK (0x380000U)
56178#define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_CTRL_SHIFT (19U)
56179/*! WAKEUP_CTRL - wakeup control
56180 * 0b000..OFF
56181 * 0b001..RESAMPLE
56182 * 0b100..LOW
56183 * 0b111..HIGH
56184 * 0b110..RISE
56185 * 0b101..FALL
56186 */
56187#define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_WAKEUP_CTRL_MASK)
56188#define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_MASK_MASK (0x400000U)
56189#define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_MASK_SHIFT (22U)
56190/*! WAKEUP_MASK - wakeup mask
56191 */
56192#define IOMUXD_ENET0_RGMII_RXD1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_WAKEUP_MASK_MASK)
56193#define IOMUXD_ENET0_RGMII_RXD1_lp_config_MASK (0x1800000U)
56194#define IOMUXD_ENET0_RGMII_RXD1_lp_config_SHIFT (23U)
56195/*! lp_config - lower power configuration
56196 * 0b01..EARLY_ISO
56197 * 0b10..LATE_ISO
56198 * 0b11..LATCH
56199 * 0b00..PASS
56200 */
56201#define IOMUXD_ENET0_RGMII_RXD1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_lp_config_MASK)
56202#define IOMUXD_ENET0_RGMII_RXD1_sw_config_MASK (0x6000000U)
56203#define IOMUXD_ENET0_RGMII_RXD1_sw_config_SHIFT (25U)
56204/*! sw_config - output and input configuration
56205 * 0b01..OPEN_DRAIN
56206 * 0b10..OPEN_DRAIN_INPUT
56207 * 0b11..INOUT
56208 * 0b00..DEFAULT
56209 */
56210#define IOMUXD_ENET0_RGMII_RXD1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_sw_config_MASK)
56211#define IOMUXD_ENET0_RGMII_RXD1_mux_mode_MASK (0x38000000U)
56212#define IOMUXD_ENET0_RGMII_RXD1_mux_mode_SHIFT (27U)
56213/*! mux_mode - mux_mode
56214 * 0b000..CONN.ENET0.RGMII_RXD1
56215 * 0b011..CONN.USDHC1.DATA1
56216 * 0b100..LSIO.GPIO5.IO06
56217 */
56218#define IOMUXD_ENET0_RGMII_RXD1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_mux_mode_MASK)
56219#define IOMUXD_ENET0_RGMII_RXD1_update_pad_ctl_MASK (0x40000000U)
56220#define IOMUXD_ENET0_RGMII_RXD1_update_pad_ctl_SHIFT (30U)
56221/*! update_pad_ctl - update lock for pad control
56222 */
56223#define IOMUXD_ENET0_RGMII_RXD1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_update_pad_ctl_MASK)
56224#define IOMUXD_ENET0_RGMII_RXD1_update_mux_mode_MASK (0x80000000U)
56225#define IOMUXD_ENET0_RGMII_RXD1_update_mux_mode_SHIFT (31U)
56226/*! update_mux_mode - update lock for mux control
56227 */
56228#define IOMUXD_ENET0_RGMII_RXD1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD1_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD1_update_mux_mode_MASK)
56229/*! @} */
56230
56231/*! @name ENET0_RGMII_RXD2 - ENET0_RGMII_RXD2 */
56232/*! @{ */
56233#define IOMUXD_ENET0_RGMII_RXD2_PDRV_MASK (0x1U)
56234#define IOMUXD_ENET0_RGMII_RXD2_PDRV_SHIFT (0U)
56235/*! PDRV - Drive
56236 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
56237 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
56238 */
56239#define IOMUXD_ENET0_RGMII_RXD2_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_PDRV_MASK)
56240#define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_1_4_MASK (0x1EU)
56241#define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_1_4_SHIFT (1U)
56242/*! ENET0_RGMII_RXD2_reserved_1_4 - reserved
56243 */
56244#define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_1_4_MASK)
56245#define IOMUXD_ENET0_RGMII_RXD2_PULL_MASK (0x60U)
56246#define IOMUXD_ENET0_RGMII_RXD2_PULL_SHIFT (5U)
56247/*! PULL - Pull Down Pull Up
56248 * 0b10..pull down
56249 * 0b01..pull up
56250 * 0b00..Prohibited
56251 * 0b11..pull disabled
56252 */
56253#define IOMUXD_ENET0_RGMII_RXD2_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_PULL_MASK)
56254#define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_7_18_MASK (0x7FF80U)
56255#define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_7_18_SHIFT (7U)
56256/*! ENET0_RGMII_RXD2_reserved_7_18 - reserved
56257 */
56258#define IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_ENET0_RGMII_RXD2_reserved_7_18_MASK)
56259#define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_CTRL_MASK (0x380000U)
56260#define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_CTRL_SHIFT (19U)
56261/*! WAKEUP_CTRL - wakeup control
56262 * 0b000..OFF
56263 * 0b001..RESAMPLE
56264 * 0b100..LOW
56265 * 0b111..HIGH
56266 * 0b110..RISE
56267 * 0b101..FALL
56268 */
56269#define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_WAKEUP_CTRL_MASK)
56270#define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_MASK_MASK (0x400000U)
56271#define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_MASK_SHIFT (22U)
56272/*! WAKEUP_MASK - wakeup mask
56273 */
56274#define IOMUXD_ENET0_RGMII_RXD2_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_WAKEUP_MASK_MASK)
56275#define IOMUXD_ENET0_RGMII_RXD2_lp_config_MASK (0x1800000U)
56276#define IOMUXD_ENET0_RGMII_RXD2_lp_config_SHIFT (23U)
56277/*! lp_config - lower power configuration
56278 * 0b01..EARLY_ISO
56279 * 0b10..LATE_ISO
56280 * 0b11..LATCH
56281 * 0b00..PASS
56282 */
56283#define IOMUXD_ENET0_RGMII_RXD2_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_lp_config_MASK)
56284#define IOMUXD_ENET0_RGMII_RXD2_sw_config_MASK (0x6000000U)
56285#define IOMUXD_ENET0_RGMII_RXD2_sw_config_SHIFT (25U)
56286/*! sw_config - output and input configuration
56287 * 0b01..OPEN_DRAIN
56288 * 0b10..OPEN_DRAIN_INPUT
56289 * 0b11..INOUT
56290 * 0b00..DEFAULT
56291 */
56292#define IOMUXD_ENET0_RGMII_RXD2_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_sw_config_MASK)
56293#define IOMUXD_ENET0_RGMII_RXD2_mux_mode_MASK (0x38000000U)
56294#define IOMUXD_ENET0_RGMII_RXD2_mux_mode_SHIFT (27U)
56295/*! mux_mode - mux_mode
56296 * 0b000..CONN.ENET0.RGMII_RXD2
56297 * 0b001..CONN.ENET0.RMII_RX_ER
56298 * 0b011..CONN.USDHC1.DATA2
56299 * 0b100..LSIO.GPIO5.IO07
56300 */
56301#define IOMUXD_ENET0_RGMII_RXD2_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_mux_mode_MASK)
56302#define IOMUXD_ENET0_RGMII_RXD2_update_pad_ctl_MASK (0x40000000U)
56303#define IOMUXD_ENET0_RGMII_RXD2_update_pad_ctl_SHIFT (30U)
56304/*! update_pad_ctl - update lock for pad control
56305 */
56306#define IOMUXD_ENET0_RGMII_RXD2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_update_pad_ctl_MASK)
56307#define IOMUXD_ENET0_RGMII_RXD2_update_mux_mode_MASK (0x80000000U)
56308#define IOMUXD_ENET0_RGMII_RXD2_update_mux_mode_SHIFT (31U)
56309/*! update_mux_mode - update lock for mux control
56310 */
56311#define IOMUXD_ENET0_RGMII_RXD2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD2_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD2_update_mux_mode_MASK)
56312/*! @} */
56313
56314/*! @name ENET0_RGMII_RXD3 - ENET0_RGMII_RXD3 */
56315/*! @{ */
56316#define IOMUXD_ENET0_RGMII_RXD3_PDRV_MASK (0x1U)
56317#define IOMUXD_ENET0_RGMII_RXD3_PDRV_SHIFT (0U)
56318/*! PDRV - Drive
56319 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
56320 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
56321 */
56322#define IOMUXD_ENET0_RGMII_RXD3_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_PDRV_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_PDRV_MASK)
56323#define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_1_4_MASK (0x1EU)
56324#define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_1_4_SHIFT (1U)
56325/*! ENET0_RGMII_RXD3_reserved_1_4 - reserved
56326 */
56327#define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_1_4_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_1_4_MASK)
56328#define IOMUXD_ENET0_RGMII_RXD3_PULL_MASK (0x60U)
56329#define IOMUXD_ENET0_RGMII_RXD3_PULL_SHIFT (5U)
56330/*! PULL - Pull Down Pull Up
56331 * 0b10..pull down
56332 * 0b01..pull up
56333 * 0b00..Prohibited
56334 * 0b11..pull disabled
56335 */
56336#define IOMUXD_ENET0_RGMII_RXD3_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_PULL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_PULL_MASK)
56337#define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_7_18_MASK (0x7FF80U)
56338#define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_7_18_SHIFT (7U)
56339/*! ENET0_RGMII_RXD3_reserved_7_18 - reserved
56340 */
56341#define IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_7_18_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_ENET0_RGMII_RXD3_reserved_7_18_MASK)
56342#define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_CTRL_MASK (0x380000U)
56343#define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_CTRL_SHIFT (19U)
56344/*! WAKEUP_CTRL - wakeup control
56345 * 0b000..OFF
56346 * 0b001..RESAMPLE
56347 * 0b100..LOW
56348 * 0b111..HIGH
56349 * 0b110..RISE
56350 * 0b101..FALL
56351 */
56352#define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_WAKEUP_CTRL_MASK)
56353#define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_MASK_MASK (0x400000U)
56354#define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_MASK_SHIFT (22U)
56355/*! WAKEUP_MASK - wakeup mask
56356 */
56357#define IOMUXD_ENET0_RGMII_RXD3_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_WAKEUP_MASK_MASK)
56358#define IOMUXD_ENET0_RGMII_RXD3_lp_config_MASK (0x1800000U)
56359#define IOMUXD_ENET0_RGMII_RXD3_lp_config_SHIFT (23U)
56360/*! lp_config - lower power configuration
56361 * 0b01..EARLY_ISO
56362 * 0b10..LATE_ISO
56363 * 0b11..LATCH
56364 * 0b00..PASS
56365 */
56366#define IOMUXD_ENET0_RGMII_RXD3_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_lp_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_lp_config_MASK)
56367#define IOMUXD_ENET0_RGMII_RXD3_sw_config_MASK (0x6000000U)
56368#define IOMUXD_ENET0_RGMII_RXD3_sw_config_SHIFT (25U)
56369/*! sw_config - output and input configuration
56370 * 0b01..OPEN_DRAIN
56371 * 0b10..OPEN_DRAIN_INPUT
56372 * 0b11..INOUT
56373 * 0b00..DEFAULT
56374 */
56375#define IOMUXD_ENET0_RGMII_RXD3_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_sw_config_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_sw_config_MASK)
56376#define IOMUXD_ENET0_RGMII_RXD3_mux_mode_MASK (0x38000000U)
56377#define IOMUXD_ENET0_RGMII_RXD3_mux_mode_SHIFT (27U)
56378/*! mux_mode - mux_mode
56379 * 0b000..CONN.ENET0.RGMII_RXD3
56380 * 0b010..CONN.NAND.ALE
56381 * 0b011..CONN.USDHC1.DATA3
56382 * 0b100..LSIO.GPIO5.IO08
56383 */
56384#define IOMUXD_ENET0_RGMII_RXD3_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_mux_mode_MASK)
56385#define IOMUXD_ENET0_RGMII_RXD3_update_pad_ctl_MASK (0x40000000U)
56386#define IOMUXD_ENET0_RGMII_RXD3_update_pad_ctl_SHIFT (30U)
56387/*! update_pad_ctl - update lock for pad control
56388 */
56389#define IOMUXD_ENET0_RGMII_RXD3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_update_pad_ctl_MASK)
56390#define IOMUXD_ENET0_RGMII_RXD3_update_mux_mode_MASK (0x80000000U)
56391#define IOMUXD_ENET0_RGMII_RXD3_update_mux_mode_SHIFT (31U)
56392/*! update_mux_mode - update lock for mux control
56393 */
56394#define IOMUXD_ENET0_RGMII_RXD3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_RGMII_RXD3_update_mux_mode_SHIFT)) & IOMUXD_ENET0_RGMII_RXD3_update_mux_mode_MASK)
56395/*! @} */
56396
56397/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 - IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 */
56398/*! @{ */
56399#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMP_MASK (0x7U)
56400#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMP_SHIFT (0U)
56401/*! COMP - COMP
56402 * 0b010..Fixed code mode
56403 * 0b100..High impedance mode
56404 * 0b110..Read mode
56405 * 0b000..Normal Mode
56406 * 0b001..Freeze Mode
56407 */
56408#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMP_MASK)
56409#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_FASTFRZ_EN_MASK (0x8U)
56410#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_FASTFRZ_EN_SHIFT (3U)
56411/*! FASTFRZ_EN - FASTFRZ_EN
56412 * 0b1..FASTFRZ signal is driven by output of subsystem
56413 * 0b0..FASTFRZ signal is gated to 0
56414 */
56415#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_FASTFRZ_EN_MASK)
56416#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PSW_OVR_MASK (0x10U)
56417#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PSW_OVR_SHIFT (4U)
56418/*! PSW_OVR - PSW_OVR
56419 * 0b1..override output of voltage detector when using 2.5V IO operation
56420 * 0b0..selection coming from voltage detector cell for 1.8V or 3.3V IO operation
56421 */
56422#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PSW_OVR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PSW_OVR_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PSW_OVR_MASK)
56423#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCP_MASK (0x1E0U)
56424#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCP_SHIFT (5U)
56425/*! RASRCP - RASRCP
56426 * 0b0101..Reset Value
56427 */
56428#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCP_MASK)
56429#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCN_MASK (0x1E00U)
56430#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCN_SHIFT (9U)
56431/*! RASRCN - RASRCN
56432 * 0b1010..Reset Value
56433 */
56434#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_RASRCN_MASK)
56435#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SELECT_NASRC_MASK (0x2000U)
56436#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SELECT_NASRC_SHIFT (13U)
56437/*! SELECT_NASRC - SELECT_NASRC
56438 * 0b1..NASRCN value
56439 * 0b0..NASRCP value
56440 */
56441#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SELECT_NASRC_MASK)
56442#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMPOK_MASK (0x4000U)
56443#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMPOK_SHIFT (14U)
56444/*! COMPOK - COMPOK
56445 * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
56446 * 0b1..compensation cell in Normal mode and tracking PVT
56447 */
56448#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_COMPOK_MASK)
56449#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_READ_NASRC_MASK (0x78000U)
56450#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_READ_NASRC_SHIFT (15U)
56451/*! READ_NASRC - READ_NASRC
56452 * 0b0000..READ Only
56453 */
56454#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_READ_NASRC_MASK)
56455#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_19_22_MASK (0x780000U)
56456#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_19_22_SHIFT (19U)
56457/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_19_22 - reserved
56458 */
56459#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_19_22_MASK)
56460#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SLEEP_MASK (0x1800000U)
56461#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SLEEP_SHIFT (23U)
56462/*! SLEEP - SLEEP
56463 * 0b11..LAST
56464 * 0b00..NO
56465 * 0b01..EARLY
56466 * 0b10..LATE
56467 */
56468#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_SLEEP_MASK)
56469#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_25_29_MASK (0x3E000000U)
56470#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_25_29_SHIFT (25U)
56471/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_25_29 - reserved
56472 */
56473#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_reserved_25_29_MASK)
56474#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_pad_ctl_MASK (0x40000000U)
56475#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_pad_ctl_SHIFT (30U)
56476/*! update_pad_ctl - update lock for pad control
56477 */
56478#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_pad_ctl_MASK)
56479#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_mux_mode_MASK (0x80000000U)
56480#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_mux_mode_SHIFT (31U)
56481/*! update_mux_mode - update lock for mux control
56482 */
56483#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_update_mux_mode_MASK)
56484/*! @} */
56485
56486/*! @name ENET0_REFCLK_125M_25M - ENET0_REFCLK_125M_25M */
56487/*! @{ */
56488#define IOMUXD_ENET0_REFCLK_125M_25M_PDRV_MASK (0x1U)
56489#define IOMUXD_ENET0_REFCLK_125M_25M_PDRV_SHIFT (0U)
56490/*! PDRV - Drive
56491 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
56492 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
56493 */
56494#define IOMUXD_ENET0_REFCLK_125M_25M_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_PDRV_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_PDRV_MASK)
56495#define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_1_4_MASK (0x1EU)
56496#define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_1_4_SHIFT (1U)
56497/*! ENET0_REFCLK_125M_25M_reserved_1_4 - reserved
56498 */
56499#define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_1_4_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_1_4_MASK)
56500#define IOMUXD_ENET0_REFCLK_125M_25M_PULL_MASK (0x60U)
56501#define IOMUXD_ENET0_REFCLK_125M_25M_PULL_SHIFT (5U)
56502/*! PULL - Pull Down Pull Up
56503 * 0b10..pull down
56504 * 0b01..pull up
56505 * 0b00..Prohibited
56506 * 0b11..pull disabled
56507 */
56508#define IOMUXD_ENET0_REFCLK_125M_25M_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_PULL_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_PULL_MASK)
56509#define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_7_18_MASK (0x7FF80U)
56510#define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_7_18_SHIFT (7U)
56511/*! ENET0_REFCLK_125M_25M_reserved_7_18 - reserved
56512 */
56513#define IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_7_18_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_ENET0_REFCLK_125M_25M_reserved_7_18_MASK)
56514#define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_CTRL_MASK (0x380000U)
56515#define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_CTRL_SHIFT (19U)
56516/*! WAKEUP_CTRL - wakeup control
56517 * 0b000..OFF
56518 * 0b001..RESAMPLE
56519 * 0b100..LOW
56520 * 0b111..HIGH
56521 * 0b110..RISE
56522 * 0b101..FALL
56523 */
56524#define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_CTRL_MASK)
56525#define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_MASK_MASK (0x400000U)
56526#define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_MASK_SHIFT (22U)
56527/*! WAKEUP_MASK - wakeup mask
56528 */
56529#define IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_WAKEUP_MASK_MASK)
56530#define IOMUXD_ENET0_REFCLK_125M_25M_lp_config_MASK (0x1800000U)
56531#define IOMUXD_ENET0_REFCLK_125M_25M_lp_config_SHIFT (23U)
56532/*! lp_config - lower power configuration
56533 * 0b01..EARLY_ISO
56534 * 0b10..LATE_ISO
56535 * 0b11..LATCH
56536 * 0b00..PASS
56537 */
56538#define IOMUXD_ENET0_REFCLK_125M_25M_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_lp_config_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_lp_config_MASK)
56539#define IOMUXD_ENET0_REFCLK_125M_25M_sw_config_MASK (0x6000000U)
56540#define IOMUXD_ENET0_REFCLK_125M_25M_sw_config_SHIFT (25U)
56541/*! sw_config - output and input configuration
56542 * 0b01..OPEN_DRAIN
56543 * 0b10..OPEN_DRAIN_INPUT
56544 * 0b11..INOUT
56545 * 0b00..DEFAULT
56546 */
56547#define IOMUXD_ENET0_REFCLK_125M_25M_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_sw_config_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_sw_config_MASK)
56548#define IOMUXD_ENET0_REFCLK_125M_25M_mux_mode_MASK (0x38000000U)
56549#define IOMUXD_ENET0_REFCLK_125M_25M_mux_mode_SHIFT (27U)
56550/*! mux_mode - mux_mode
56551 * 0b000..CONN.ENET0.REFCLK_125M_25M
56552 * 0b001..CONN.ENET0.PPS
56553 * 0b010..CONN.ENET1.PPS
56554 * 0b100..LSIO.GPIO5.IO09
56555 */
56556#define IOMUXD_ENET0_REFCLK_125M_25M_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_mux_mode_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_mux_mode_MASK)
56557#define IOMUXD_ENET0_REFCLK_125M_25M_update_pad_ctl_MASK (0x40000000U)
56558#define IOMUXD_ENET0_REFCLK_125M_25M_update_pad_ctl_SHIFT (30U)
56559/*! update_pad_ctl - update lock for pad control
56560 */
56561#define IOMUXD_ENET0_REFCLK_125M_25M_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_update_pad_ctl_MASK)
56562#define IOMUXD_ENET0_REFCLK_125M_25M_update_mux_mode_MASK (0x80000000U)
56563#define IOMUXD_ENET0_REFCLK_125M_25M_update_mux_mode_SHIFT (31U)
56564/*! update_mux_mode - update lock for mux control
56565 */
56566#define IOMUXD_ENET0_REFCLK_125M_25M_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_REFCLK_125M_25M_update_mux_mode_SHIFT)) & IOMUXD_ENET0_REFCLK_125M_25M_update_mux_mode_MASK)
56567/*! @} */
56568
56569/*! @name IOMUXD_GROUP_1_2 - na */
56570/*! @{ */
56571#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD0_MASK (0x1U)
56572#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD0_SHIFT (0U)
56573/*! ENET0_RGMII_TXD0 - wakeup from ENET0_RGMII_TXD0
56574 */
56575#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD0_MASK)
56576#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD1_MASK (0x2U)
56577#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD1_SHIFT (1U)
56578/*! ENET0_RGMII_TXD1 - wakeup from ENET0_RGMII_TXD1
56579 */
56580#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD1_MASK)
56581#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD2_MASK (0x4U)
56582#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD2_SHIFT (2U)
56583/*! ENET0_RGMII_TXD2 - wakeup from ENET0_RGMII_TXD2
56584 */
56585#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD2_MASK)
56586#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD3_MASK (0x8U)
56587#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD3_SHIFT (3U)
56588/*! ENET0_RGMII_TXD3 - wakeup from ENET0_RGMII_TXD3
56589 */
56590#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD3_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_TXD3_MASK)
56591#define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_4_4_MASK (0x10U)
56592#define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_4_4_SHIFT (4U)
56593/*! iomuxd_group_1_2_reserved_4_4 - reserved
56594 */
56595#define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_4_4_MASK)
56596#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXC_MASK (0x20U)
56597#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXC_SHIFT (5U)
56598/*! ENET0_RGMII_RXC - wakeup from ENET0_RGMII_RXC
56599 */
56600#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXC_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXC_MASK)
56601#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RX_CTL_MASK (0x40U)
56602#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RX_CTL_SHIFT (6U)
56603/*! ENET0_RGMII_RX_CTL - wakeup from ENET0_RGMII_RX_CTL
56604 */
56605#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RX_CTL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RX_CTL_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RX_CTL_MASK)
56606#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD0_MASK (0x80U)
56607#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD0_SHIFT (7U)
56608/*! ENET0_RGMII_RXD0 - wakeup from ENET0_RGMII_RXD0
56609 */
56610#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD0_MASK)
56611#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD1_MASK (0x100U)
56612#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD1_SHIFT (8U)
56613/*! ENET0_RGMII_RXD1 - wakeup from ENET0_RGMII_RXD1
56614 */
56615#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD1_MASK)
56616#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD2_MASK (0x200U)
56617#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD2_SHIFT (9U)
56618/*! ENET0_RGMII_RXD2 - wakeup from ENET0_RGMII_RXD2
56619 */
56620#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD2_MASK)
56621#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD3_MASK (0x400U)
56622#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD3_SHIFT (10U)
56623/*! ENET0_RGMII_RXD3 - wakeup from ENET0_RGMII_RXD3
56624 */
56625#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD3_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_RGMII_RXD3_MASK)
56626#define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_11_11_MASK (0x800U)
56627#define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_11_11_SHIFT (11U)
56628/*! iomuxd_group_1_2_reserved_11_11 - reserved
56629 */
56630#define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_11_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_11_11_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_11_11_MASK)
56631#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_REFCLK_125M_25M_MASK (0x1000U)
56632#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_REFCLK_125M_25M_SHIFT (12U)
56633/*! ENET0_REFCLK_125M_25M - wakeup from ENET0_REFCLK_125M_25M
56634 */
56635#define IOMUXD_IOMUXD_GROUP_1_2_ENET0_REFCLK_125M_25M(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_ENET0_REFCLK_125M_25M_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_ENET0_REFCLK_125M_25M_MASK)
56636#define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_13_31_MASK (0xFFFFE000U)
56637#define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_13_31_SHIFT (13U)
56638/*! iomuxd_group_1_2_reserved_13_31 - reserved
56639 */
56640#define IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_13_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_13_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_2_iomuxd_group_1_2_reserved_13_31_MASK)
56641/*! @} */
56642
56643/*! @name ENET0_MDIO - ENET0_MDIO */
56644/*! @{ */
56645#define IOMUXD_ENET0_MDIO_PDRV_MASK (0x1U)
56646#define IOMUXD_ENET0_MDIO_PDRV_SHIFT (0U)
56647/*! PDRV - Drive
56648 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
56649 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
56650 */
56651#define IOMUXD_ENET0_MDIO_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_PDRV_SHIFT)) & IOMUXD_ENET0_MDIO_PDRV_MASK)
56652#define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_1_4_MASK (0x1EU)
56653#define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_1_4_SHIFT (1U)
56654/*! ENET0_MDIO_reserved_1_4 - reserved
56655 */
56656#define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_1_4_SHIFT)) & IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_1_4_MASK)
56657#define IOMUXD_ENET0_MDIO_PULL_MASK (0x60U)
56658#define IOMUXD_ENET0_MDIO_PULL_SHIFT (5U)
56659/*! PULL - Pull Down Pull Up
56660 * 0b10..pull down
56661 * 0b01..pull up
56662 * 0b00..Prohibited
56663 * 0b11..pull disabled
56664 */
56665#define IOMUXD_ENET0_MDIO_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_PULL_SHIFT)) & IOMUXD_ENET0_MDIO_PULL_MASK)
56666#define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_7_18_MASK (0x7FF80U)
56667#define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_7_18_SHIFT (7U)
56668/*! ENET0_MDIO_reserved_7_18 - reserved
56669 */
56670#define IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_7_18_SHIFT)) & IOMUXD_ENET0_MDIO_ENET0_MDIO_reserved_7_18_MASK)
56671#define IOMUXD_ENET0_MDIO_WAKEUP_CTRL_MASK (0x380000U)
56672#define IOMUXD_ENET0_MDIO_WAKEUP_CTRL_SHIFT (19U)
56673/*! WAKEUP_CTRL - wakeup control
56674 * 0b000..OFF
56675 * 0b001..RESAMPLE
56676 * 0b100..LOW
56677 * 0b111..HIGH
56678 * 0b110..RISE
56679 * 0b101..FALL
56680 */
56681#define IOMUXD_ENET0_MDIO_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_MDIO_WAKEUP_CTRL_MASK)
56682#define IOMUXD_ENET0_MDIO_WAKEUP_MASK_MASK (0x400000U)
56683#define IOMUXD_ENET0_MDIO_WAKEUP_MASK_SHIFT (22U)
56684/*! WAKEUP_MASK - wakeup mask
56685 */
56686#define IOMUXD_ENET0_MDIO_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_MDIO_WAKEUP_MASK_MASK)
56687#define IOMUXD_ENET0_MDIO_lp_config_MASK (0x1800000U)
56688#define IOMUXD_ENET0_MDIO_lp_config_SHIFT (23U)
56689/*! lp_config - lower power configuration
56690 * 0b01..EARLY_ISO
56691 * 0b10..LATE_ISO
56692 * 0b11..LATCH
56693 * 0b00..PASS
56694 */
56695#define IOMUXD_ENET0_MDIO_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_lp_config_SHIFT)) & IOMUXD_ENET0_MDIO_lp_config_MASK)
56696#define IOMUXD_ENET0_MDIO_sw_config_MASK (0x6000000U)
56697#define IOMUXD_ENET0_MDIO_sw_config_SHIFT (25U)
56698/*! sw_config - output and input configuration
56699 * 0b01..OPEN_DRAIN
56700 * 0b10..OPEN_DRAIN_INPUT
56701 * 0b11..INOUT
56702 * 0b00..DEFAULT
56703 */
56704#define IOMUXD_ENET0_MDIO_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_sw_config_SHIFT)) & IOMUXD_ENET0_MDIO_sw_config_MASK)
56705#define IOMUXD_ENET0_MDIO_mux_mode_MASK (0x38000000U)
56706#define IOMUXD_ENET0_MDIO_mux_mode_SHIFT (27U)
56707/*! mux_mode - mux_mode
56708 * 0b000..CONN.ENET0.MDIO
56709 * 0b001..ADMA.I2C3.SDA
56710 * 0b010..CONN.ENET1.MDIO
56711 * 0b100..LSIO.GPIO5.IO10
56712 */
56713#define IOMUXD_ENET0_MDIO_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_mux_mode_SHIFT)) & IOMUXD_ENET0_MDIO_mux_mode_MASK)
56714#define IOMUXD_ENET0_MDIO_update_pad_ctl_MASK (0x40000000U)
56715#define IOMUXD_ENET0_MDIO_update_pad_ctl_SHIFT (30U)
56716/*! update_pad_ctl - update lock for pad control
56717 */
56718#define IOMUXD_ENET0_MDIO_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_MDIO_update_pad_ctl_MASK)
56719#define IOMUXD_ENET0_MDIO_update_mux_mode_MASK (0x80000000U)
56720#define IOMUXD_ENET0_MDIO_update_mux_mode_SHIFT (31U)
56721/*! update_mux_mode - update lock for mux control
56722 */
56723#define IOMUXD_ENET0_MDIO_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDIO_update_mux_mode_SHIFT)) & IOMUXD_ENET0_MDIO_update_mux_mode_MASK)
56724/*! @} */
56725
56726/*! @name ENET0_MDC - ENET0_MDC */
56727/*! @{ */
56728#define IOMUXD_ENET0_MDC_PDRV_MASK (0x1U)
56729#define IOMUXD_ENET0_MDC_PDRV_SHIFT (0U)
56730/*! PDRV - Drive
56731 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
56732 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
56733 */
56734#define IOMUXD_ENET0_MDC_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_PDRV_SHIFT)) & IOMUXD_ENET0_MDC_PDRV_MASK)
56735#define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_1_4_MASK (0x1EU)
56736#define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_1_4_SHIFT (1U)
56737/*! ENET0_MDC_reserved_1_4 - reserved
56738 */
56739#define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_ENET0_MDC_reserved_1_4_SHIFT)) & IOMUXD_ENET0_MDC_ENET0_MDC_reserved_1_4_MASK)
56740#define IOMUXD_ENET0_MDC_PULL_MASK (0x60U)
56741#define IOMUXD_ENET0_MDC_PULL_SHIFT (5U)
56742/*! PULL - Pull Down Pull Up
56743 * 0b10..pull down
56744 * 0b01..pull up
56745 * 0b00..Prohibited
56746 * 0b11..pull disabled
56747 */
56748#define IOMUXD_ENET0_MDC_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_PULL_SHIFT)) & IOMUXD_ENET0_MDC_PULL_MASK)
56749#define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_7_18_MASK (0x7FF80U)
56750#define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_7_18_SHIFT (7U)
56751/*! ENET0_MDC_reserved_7_18 - reserved
56752 */
56753#define IOMUXD_ENET0_MDC_ENET0_MDC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_ENET0_MDC_reserved_7_18_SHIFT)) & IOMUXD_ENET0_MDC_ENET0_MDC_reserved_7_18_MASK)
56754#define IOMUXD_ENET0_MDC_WAKEUP_CTRL_MASK (0x380000U)
56755#define IOMUXD_ENET0_MDC_WAKEUP_CTRL_SHIFT (19U)
56756/*! WAKEUP_CTRL - wakeup control
56757 * 0b000..OFF
56758 * 0b001..RESAMPLE
56759 * 0b100..LOW
56760 * 0b111..HIGH
56761 * 0b110..RISE
56762 * 0b101..FALL
56763 */
56764#define IOMUXD_ENET0_MDC_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_WAKEUP_CTRL_SHIFT)) & IOMUXD_ENET0_MDC_WAKEUP_CTRL_MASK)
56765#define IOMUXD_ENET0_MDC_WAKEUP_MASK_MASK (0x400000U)
56766#define IOMUXD_ENET0_MDC_WAKEUP_MASK_SHIFT (22U)
56767/*! WAKEUP_MASK - wakeup mask
56768 */
56769#define IOMUXD_ENET0_MDC_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_WAKEUP_MASK_SHIFT)) & IOMUXD_ENET0_MDC_WAKEUP_MASK_MASK)
56770#define IOMUXD_ENET0_MDC_lp_config_MASK (0x1800000U)
56771#define IOMUXD_ENET0_MDC_lp_config_SHIFT (23U)
56772/*! lp_config - lower power configuration
56773 * 0b01..EARLY_ISO
56774 * 0b10..LATE_ISO
56775 * 0b11..LATCH
56776 * 0b00..PASS
56777 */
56778#define IOMUXD_ENET0_MDC_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_lp_config_SHIFT)) & IOMUXD_ENET0_MDC_lp_config_MASK)
56779#define IOMUXD_ENET0_MDC_sw_config_MASK (0x6000000U)
56780#define IOMUXD_ENET0_MDC_sw_config_SHIFT (25U)
56781/*! sw_config - output and input configuration
56782 * 0b01..OPEN_DRAIN
56783 * 0b10..OPEN_DRAIN_INPUT
56784 * 0b11..INOUT
56785 * 0b00..DEFAULT
56786 */
56787#define IOMUXD_ENET0_MDC_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_sw_config_SHIFT)) & IOMUXD_ENET0_MDC_sw_config_MASK)
56788#define IOMUXD_ENET0_MDC_mux_mode_MASK (0x38000000U)
56789#define IOMUXD_ENET0_MDC_mux_mode_SHIFT (27U)
56790/*! mux_mode - mux_mode
56791 * 0b000..CONN.ENET0.MDC
56792 * 0b001..ADMA.I2C3.SCL
56793 * 0b010..CONN.ENET1.MDC
56794 * 0b100..LSIO.GPIO5.IO11
56795 */
56796#define IOMUXD_ENET0_MDC_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_mux_mode_SHIFT)) & IOMUXD_ENET0_MDC_mux_mode_MASK)
56797#define IOMUXD_ENET0_MDC_update_pad_ctl_MASK (0x40000000U)
56798#define IOMUXD_ENET0_MDC_update_pad_ctl_SHIFT (30U)
56799/*! update_pad_ctl - update lock for pad control
56800 */
56801#define IOMUXD_ENET0_MDC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_update_pad_ctl_SHIFT)) & IOMUXD_ENET0_MDC_update_pad_ctl_MASK)
56802#define IOMUXD_ENET0_MDC_update_mux_mode_MASK (0x80000000U)
56803#define IOMUXD_ENET0_MDC_update_mux_mode_SHIFT (31U)
56804/*! update_mux_mode - update lock for mux control
56805 */
56806#define IOMUXD_ENET0_MDC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ENET0_MDC_update_mux_mode_SHIFT)) & IOMUXD_ENET0_MDC_update_mux_mode_MASK)
56807/*! @} */
56808
56809/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT */
56810/*! @{ */
56811#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMP_MASK (0x7U)
56812#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMP_SHIFT (0U)
56813/*! COMP - COMP
56814 * 0b010..Fixed code mode
56815 * 0b100..High impedance mode
56816 * 0b110..Read mode
56817 * 0b000..Normal Mode
56818 * 0b001..Freeze Mode
56819 */
56820#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMP_MASK)
56821#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_FASTFRZ_EN_MASK (0x8U)
56822#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_FASTFRZ_EN_SHIFT (3U)
56823/*! FASTFRZ_EN - FASTFRZ_EN
56824 * 0b1..FASTFRZ signal is driven by output of subsystem
56825 * 0b0..FASTFRZ signal is gated to 0
56826 */
56827#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_FASTFRZ_EN_MASK)
56828#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4_MASK (0x10U)
56829#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4_SHIFT (4U)
56830/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4 - reserved
56831 */
56832#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_4_4_MASK)
56833#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCP_MASK (0x1E0U)
56834#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCP_SHIFT (5U)
56835/*! RASRCP - RASRCP
56836 * 0b0101..Reset Value
56837 */
56838#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCP_MASK)
56839#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCN_MASK (0x1E00U)
56840#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCN_SHIFT (9U)
56841/*! RASRCN - RASRCN
56842 * 0b1010..Reset Value
56843 */
56844#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_RASRCN_MASK)
56845#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SELECT_NASRC_MASK (0x2000U)
56846#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SELECT_NASRC_SHIFT (13U)
56847/*! SELECT_NASRC - SELECT_NASRC
56848 * 0b1..NASRCN value
56849 * 0b0..NASRCP value
56850 */
56851#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SELECT_NASRC_MASK)
56852#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMPOK_MASK (0x4000U)
56853#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMPOK_SHIFT (14U)
56854/*! COMPOK - COMPOK
56855 * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
56856 * 0b1..compensation cell in Normal mode and tracking PVT
56857 */
56858#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_COMPOK_MASK)
56859#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_READ_NASRC_MASK (0x78000U)
56860#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_READ_NASRC_SHIFT (15U)
56861/*! READ_NASRC - READ_NASRC
56862 * 0b0000..READ Only
56863 */
56864#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_READ_NASRC_MASK)
56865#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22_MASK (0x780000U)
56866#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22_SHIFT (19U)
56867/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22 - reserved
56868 */
56869#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_19_22_MASK)
56870#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SLEEP_MASK (0x1800000U)
56871#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SLEEP_SHIFT (23U)
56872/*! SLEEP - SLEEP
56873 * 0b11..Force into sleep mode
56874 * 0b00..NO
56875 * 0b01..EARLY
56876 * 0b10..LATE
56877 */
56878#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_SLEEP_MASK)
56879#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29_MASK (0x3E000000U)
56880#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29_SHIFT (25U)
56881/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29 - reserved
56882 */
56883#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_reserved_25_29_MASK)
56884#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_pad_ctl_MASK (0x40000000U)
56885#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_pad_ctl_SHIFT (30U)
56886/*! update_pad_ctl - update lock for pad control
56887 */
56888#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_pad_ctl_MASK)
56889#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_mux_mode_MASK (0x80000000U)
56890#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_mux_mode_SHIFT (31U)
56891/*! update_mux_mode - update lock for mux control
56892 */
56893#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOCT_update_mux_mode_MASK)
56894/*! @} */
56895
56896/*! @name ESAI0_FSR - ESAI0_FSR */
56897/*! @{ */
56898#define IOMUXD_ESAI0_FSR_PDRV_MASK (0x1U)
56899#define IOMUXD_ESAI0_FSR_PDRV_SHIFT (0U)
56900/*! PDRV - Drive
56901 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
56902 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
56903 */
56904#define IOMUXD_ESAI0_FSR_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_PDRV_SHIFT)) & IOMUXD_ESAI0_FSR_PDRV_MASK)
56905#define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_1_4_MASK (0x1EU)
56906#define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_1_4_SHIFT (1U)
56907/*! ESAI0_FSR_reserved_1_4 - reserved
56908 */
56909#define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_1_4_MASK)
56910#define IOMUXD_ESAI0_FSR_PULL_MASK (0x60U)
56911#define IOMUXD_ESAI0_FSR_PULL_SHIFT (5U)
56912/*! PULL - Pull Down Pull Up
56913 * 0b10..pull down
56914 * 0b01..pull up
56915 * 0b00..Prohibited
56916 * 0b11..pull disabled
56917 */
56918#define IOMUXD_ESAI0_FSR_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_PULL_SHIFT)) & IOMUXD_ESAI0_FSR_PULL_MASK)
56919#define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_7_18_MASK (0x7FF80U)
56920#define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_7_18_SHIFT (7U)
56921/*! ESAI0_FSR_reserved_7_18 - reserved
56922 */
56923#define IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_FSR_ESAI0_FSR_reserved_7_18_MASK)
56924#define IOMUXD_ESAI0_FSR_WAKEUP_CTRL_MASK (0x380000U)
56925#define IOMUXD_ESAI0_FSR_WAKEUP_CTRL_SHIFT (19U)
56926/*! WAKEUP_CTRL - wakeup control
56927 * 0b000..OFF
56928 * 0b001..RESAMPLE
56929 * 0b100..LOW
56930 * 0b111..HIGH
56931 * 0b110..RISE
56932 * 0b101..FALL
56933 */
56934#define IOMUXD_ESAI0_FSR_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_FSR_WAKEUP_CTRL_MASK)
56935#define IOMUXD_ESAI0_FSR_WAKEUP_MASK_MASK (0x400000U)
56936#define IOMUXD_ESAI0_FSR_WAKEUP_MASK_SHIFT (22U)
56937/*! WAKEUP_MASK - wakeup mask
56938 */
56939#define IOMUXD_ESAI0_FSR_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_FSR_WAKEUP_MASK_MASK)
56940#define IOMUXD_ESAI0_FSR_lp_config_MASK (0x1800000U)
56941#define IOMUXD_ESAI0_FSR_lp_config_SHIFT (23U)
56942/*! lp_config - lower power configuration
56943 * 0b01..EARLY_ISO
56944 * 0b10..LATE_ISO
56945 * 0b11..LATCH
56946 * 0b00..PASS
56947 */
56948#define IOMUXD_ESAI0_FSR_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_lp_config_SHIFT)) & IOMUXD_ESAI0_FSR_lp_config_MASK)
56949#define IOMUXD_ESAI0_FSR_sw_config_MASK (0x6000000U)
56950#define IOMUXD_ESAI0_FSR_sw_config_SHIFT (25U)
56951/*! sw_config - output and input configuration
56952 * 0b01..OPEN_DRAIN
56953 * 0b10..OPEN_DRAIN_INPUT
56954 * 0b11..INOUT
56955 * 0b00..DEFAULT
56956 */
56957#define IOMUXD_ESAI0_FSR_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_sw_config_SHIFT)) & IOMUXD_ESAI0_FSR_sw_config_MASK)
56958#define IOMUXD_ESAI0_FSR_mux_mode_MASK (0x38000000U)
56959#define IOMUXD_ESAI0_FSR_mux_mode_SHIFT (27U)
56960/*! mux_mode - mux_mode
56961 * 0b000..ADMA.ESAI0.FSR
56962 * 0b001..CONN.ENET1.RCLK50M_OUT
56963 * 0b010..ADMA.LCDIF.D00
56964 * 0b011..CONN.ENET1.RGMII_TXC
56965 * 0b100..CONN.ENET1.RCLK50M_IN
56966 */
56967#define IOMUXD_ESAI0_FSR_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_mux_mode_SHIFT)) & IOMUXD_ESAI0_FSR_mux_mode_MASK)
56968#define IOMUXD_ESAI0_FSR_update_pad_ctl_MASK (0x40000000U)
56969#define IOMUXD_ESAI0_FSR_update_pad_ctl_SHIFT (30U)
56970/*! update_pad_ctl - update lock for pad control
56971 */
56972#define IOMUXD_ESAI0_FSR_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_FSR_update_pad_ctl_MASK)
56973#define IOMUXD_ESAI0_FSR_update_mux_mode_MASK (0x80000000U)
56974#define IOMUXD_ESAI0_FSR_update_mux_mode_SHIFT (31U)
56975/*! update_mux_mode - update lock for mux control
56976 */
56977#define IOMUXD_ESAI0_FSR_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FSR_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_FSR_update_mux_mode_MASK)
56978/*! @} */
56979
56980/*! @name ESAI0_FST - ESAI0_FST */
56981/*! @{ */
56982#define IOMUXD_ESAI0_FST_PDRV_MASK (0x1U)
56983#define IOMUXD_ESAI0_FST_PDRV_SHIFT (0U)
56984/*! PDRV - Drive
56985 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
56986 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
56987 */
56988#define IOMUXD_ESAI0_FST_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_PDRV_SHIFT)) & IOMUXD_ESAI0_FST_PDRV_MASK)
56989#define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_1_4_MASK (0x1EU)
56990#define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_1_4_SHIFT (1U)
56991/*! ESAI0_FST_reserved_1_4 - reserved
56992 */
56993#define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_ESAI0_FST_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_FST_ESAI0_FST_reserved_1_4_MASK)
56994#define IOMUXD_ESAI0_FST_PULL_MASK (0x60U)
56995#define IOMUXD_ESAI0_FST_PULL_SHIFT (5U)
56996/*! PULL - Pull Down Pull Up
56997 * 0b10..pull down
56998 * 0b01..pull up
56999 * 0b00..Prohibited
57000 * 0b11..pull disabled
57001 */
57002#define IOMUXD_ESAI0_FST_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_PULL_SHIFT)) & IOMUXD_ESAI0_FST_PULL_MASK)
57003#define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_7_18_MASK (0x7FF80U)
57004#define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_7_18_SHIFT (7U)
57005/*! ESAI0_FST_reserved_7_18 - reserved
57006 */
57007#define IOMUXD_ESAI0_FST_ESAI0_FST_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_ESAI0_FST_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_FST_ESAI0_FST_reserved_7_18_MASK)
57008#define IOMUXD_ESAI0_FST_WAKEUP_CTRL_MASK (0x380000U)
57009#define IOMUXD_ESAI0_FST_WAKEUP_CTRL_SHIFT (19U)
57010/*! WAKEUP_CTRL - wakeup control
57011 * 0b000..OFF
57012 * 0b001..RESAMPLE
57013 * 0b100..LOW
57014 * 0b111..HIGH
57015 * 0b110..RISE
57016 * 0b101..FALL
57017 */
57018#define IOMUXD_ESAI0_FST_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_FST_WAKEUP_CTRL_MASK)
57019#define IOMUXD_ESAI0_FST_WAKEUP_MASK_MASK (0x400000U)
57020#define IOMUXD_ESAI0_FST_WAKEUP_MASK_SHIFT (22U)
57021/*! WAKEUP_MASK - wakeup mask
57022 */
57023#define IOMUXD_ESAI0_FST_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_FST_WAKEUP_MASK_MASK)
57024#define IOMUXD_ESAI0_FST_lp_config_MASK (0x1800000U)
57025#define IOMUXD_ESAI0_FST_lp_config_SHIFT (23U)
57026/*! lp_config - lower power configuration
57027 * 0b01..EARLY_ISO
57028 * 0b10..LATE_ISO
57029 * 0b11..LATCH
57030 * 0b00..PASS
57031 */
57032#define IOMUXD_ESAI0_FST_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_lp_config_SHIFT)) & IOMUXD_ESAI0_FST_lp_config_MASK)
57033#define IOMUXD_ESAI0_FST_sw_config_MASK (0x6000000U)
57034#define IOMUXD_ESAI0_FST_sw_config_SHIFT (25U)
57035/*! sw_config - output and input configuration
57036 * 0b01..OPEN_DRAIN
57037 * 0b10..OPEN_DRAIN_INPUT
57038 * 0b11..INOUT
57039 * 0b00..DEFAULT
57040 */
57041#define IOMUXD_ESAI0_FST_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_sw_config_SHIFT)) & IOMUXD_ESAI0_FST_sw_config_MASK)
57042#define IOMUXD_ESAI0_FST_mux_mode_MASK (0x38000000U)
57043#define IOMUXD_ESAI0_FST_mux_mode_SHIFT (27U)
57044/*! mux_mode - mux_mode
57045 * 0b000..ADMA.ESAI0.FST
57046 * 0b001..CONN.MLB.CLK
57047 * 0b010..ADMA.LCDIF.D01
57048 * 0b011..CONN.ENET1.RGMII_TXD2
57049 * 0b100..LSIO.GPIO0.IO01
57050 */
57051#define IOMUXD_ESAI0_FST_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_mux_mode_SHIFT)) & IOMUXD_ESAI0_FST_mux_mode_MASK)
57052#define IOMUXD_ESAI0_FST_update_pad_ctl_MASK (0x40000000U)
57053#define IOMUXD_ESAI0_FST_update_pad_ctl_SHIFT (30U)
57054/*! update_pad_ctl - update lock for pad control
57055 */
57056#define IOMUXD_ESAI0_FST_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_FST_update_pad_ctl_MASK)
57057#define IOMUXD_ESAI0_FST_update_mux_mode_MASK (0x80000000U)
57058#define IOMUXD_ESAI0_FST_update_mux_mode_SHIFT (31U)
57059/*! update_mux_mode - update lock for mux control
57060 */
57061#define IOMUXD_ESAI0_FST_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_FST_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_FST_update_mux_mode_MASK)
57062/*! @} */
57063
57064/*! @name ESAI0_SCKR - ESAI0_SCKR */
57065/*! @{ */
57066#define IOMUXD_ESAI0_SCKR_PDRV_MASK (0x1U)
57067#define IOMUXD_ESAI0_SCKR_PDRV_SHIFT (0U)
57068/*! PDRV - Drive
57069 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57070 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57071 */
57072#define IOMUXD_ESAI0_SCKR_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_PDRV_SHIFT)) & IOMUXD_ESAI0_SCKR_PDRV_MASK)
57073#define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_1_4_MASK (0x1EU)
57074#define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_1_4_SHIFT (1U)
57075/*! ESAI0_SCKR_reserved_1_4 - reserved
57076 */
57077#define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_1_4_MASK)
57078#define IOMUXD_ESAI0_SCKR_PULL_MASK (0x60U)
57079#define IOMUXD_ESAI0_SCKR_PULL_SHIFT (5U)
57080/*! PULL - Pull Down Pull Up
57081 * 0b10..pull down
57082 * 0b01..pull up
57083 * 0b00..Prohibited
57084 * 0b11..pull disabled
57085 */
57086#define IOMUXD_ESAI0_SCKR_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_PULL_SHIFT)) & IOMUXD_ESAI0_SCKR_PULL_MASK)
57087#define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_7_18_MASK (0x7FF80U)
57088#define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_7_18_SHIFT (7U)
57089/*! ESAI0_SCKR_reserved_7_18 - reserved
57090 */
57091#define IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_SCKR_ESAI0_SCKR_reserved_7_18_MASK)
57092#define IOMUXD_ESAI0_SCKR_WAKEUP_CTRL_MASK (0x380000U)
57093#define IOMUXD_ESAI0_SCKR_WAKEUP_CTRL_SHIFT (19U)
57094/*! WAKEUP_CTRL - wakeup control
57095 * 0b000..OFF
57096 * 0b001..RESAMPLE
57097 * 0b100..LOW
57098 * 0b111..HIGH
57099 * 0b110..RISE
57100 * 0b101..FALL
57101 */
57102#define IOMUXD_ESAI0_SCKR_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_SCKR_WAKEUP_CTRL_MASK)
57103#define IOMUXD_ESAI0_SCKR_WAKEUP_MASK_MASK (0x400000U)
57104#define IOMUXD_ESAI0_SCKR_WAKEUP_MASK_SHIFT (22U)
57105/*! WAKEUP_MASK - wakeup mask
57106 */
57107#define IOMUXD_ESAI0_SCKR_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_SCKR_WAKEUP_MASK_MASK)
57108#define IOMUXD_ESAI0_SCKR_lp_config_MASK (0x1800000U)
57109#define IOMUXD_ESAI0_SCKR_lp_config_SHIFT (23U)
57110/*! lp_config - lower power configuration
57111 * 0b01..EARLY_ISO
57112 * 0b10..LATE_ISO
57113 * 0b11..LATCH
57114 * 0b00..PASS
57115 */
57116#define IOMUXD_ESAI0_SCKR_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_lp_config_SHIFT)) & IOMUXD_ESAI0_SCKR_lp_config_MASK)
57117#define IOMUXD_ESAI0_SCKR_sw_config_MASK (0x6000000U)
57118#define IOMUXD_ESAI0_SCKR_sw_config_SHIFT (25U)
57119/*! sw_config - output and input configuration
57120 * 0b01..OPEN_DRAIN
57121 * 0b10..OPEN_DRAIN_INPUT
57122 * 0b11..INOUT
57123 * 0b00..DEFAULT
57124 */
57125#define IOMUXD_ESAI0_SCKR_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_sw_config_SHIFT)) & IOMUXD_ESAI0_SCKR_sw_config_MASK)
57126#define IOMUXD_ESAI0_SCKR_mux_mode_MASK (0x38000000U)
57127#define IOMUXD_ESAI0_SCKR_mux_mode_SHIFT (27U)
57128/*! mux_mode - mux_mode
57129 * 0b000..ADMA.ESAI0.SCKR
57130 * 0b010..ADMA.LCDIF.D02
57131 * 0b011..CONN.ENET1.RGMII_TX_CTL
57132 * 0b100..LSIO.GPIO0.IO02
57133 */
57134#define IOMUXD_ESAI0_SCKR_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_mux_mode_SHIFT)) & IOMUXD_ESAI0_SCKR_mux_mode_MASK)
57135#define IOMUXD_ESAI0_SCKR_update_pad_ctl_MASK (0x40000000U)
57136#define IOMUXD_ESAI0_SCKR_update_pad_ctl_SHIFT (30U)
57137/*! update_pad_ctl - update lock for pad control
57138 */
57139#define IOMUXD_ESAI0_SCKR_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_SCKR_update_pad_ctl_MASK)
57140#define IOMUXD_ESAI0_SCKR_update_mux_mode_MASK (0x80000000U)
57141#define IOMUXD_ESAI0_SCKR_update_mux_mode_SHIFT (31U)
57142/*! update_mux_mode - update lock for mux control
57143 */
57144#define IOMUXD_ESAI0_SCKR_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKR_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_SCKR_update_mux_mode_MASK)
57145/*! @} */
57146
57147/*! @name ESAI0_SCKT - ESAI0_SCKT */
57148/*! @{ */
57149#define IOMUXD_ESAI0_SCKT_PDRV_MASK (0x1U)
57150#define IOMUXD_ESAI0_SCKT_PDRV_SHIFT (0U)
57151/*! PDRV - Drive
57152 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57153 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57154 */
57155#define IOMUXD_ESAI0_SCKT_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_PDRV_SHIFT)) & IOMUXD_ESAI0_SCKT_PDRV_MASK)
57156#define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_1_4_MASK (0x1EU)
57157#define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_1_4_SHIFT (1U)
57158/*! ESAI0_SCKT_reserved_1_4 - reserved
57159 */
57160#define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_1_4_MASK)
57161#define IOMUXD_ESAI0_SCKT_PULL_MASK (0x60U)
57162#define IOMUXD_ESAI0_SCKT_PULL_SHIFT (5U)
57163/*! PULL - Pull Down Pull Up
57164 * 0b10..pull down
57165 * 0b01..pull up
57166 * 0b00..Prohibited
57167 * 0b11..pull disabled
57168 */
57169#define IOMUXD_ESAI0_SCKT_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_PULL_SHIFT)) & IOMUXD_ESAI0_SCKT_PULL_MASK)
57170#define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_7_18_MASK (0x7FF80U)
57171#define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_7_18_SHIFT (7U)
57172/*! ESAI0_SCKT_reserved_7_18 - reserved
57173 */
57174#define IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_SCKT_ESAI0_SCKT_reserved_7_18_MASK)
57175#define IOMUXD_ESAI0_SCKT_WAKEUP_CTRL_MASK (0x380000U)
57176#define IOMUXD_ESAI0_SCKT_WAKEUP_CTRL_SHIFT (19U)
57177/*! WAKEUP_CTRL - wakeup control
57178 * 0b000..OFF
57179 * 0b001..RESAMPLE
57180 * 0b100..LOW
57181 * 0b111..HIGH
57182 * 0b110..RISE
57183 * 0b101..FALL
57184 */
57185#define IOMUXD_ESAI0_SCKT_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_SCKT_WAKEUP_CTRL_MASK)
57186#define IOMUXD_ESAI0_SCKT_WAKEUP_MASK_MASK (0x400000U)
57187#define IOMUXD_ESAI0_SCKT_WAKEUP_MASK_SHIFT (22U)
57188/*! WAKEUP_MASK - wakeup mask
57189 */
57190#define IOMUXD_ESAI0_SCKT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_SCKT_WAKEUP_MASK_MASK)
57191#define IOMUXD_ESAI0_SCKT_lp_config_MASK (0x1800000U)
57192#define IOMUXD_ESAI0_SCKT_lp_config_SHIFT (23U)
57193/*! lp_config - lower power configuration
57194 * 0b01..EARLY_ISO
57195 * 0b10..LATE_ISO
57196 * 0b11..LATCH
57197 * 0b00..PASS
57198 */
57199#define IOMUXD_ESAI0_SCKT_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_lp_config_SHIFT)) & IOMUXD_ESAI0_SCKT_lp_config_MASK)
57200#define IOMUXD_ESAI0_SCKT_sw_config_MASK (0x6000000U)
57201#define IOMUXD_ESAI0_SCKT_sw_config_SHIFT (25U)
57202/*! sw_config - output and input configuration
57203 * 0b01..OPEN_DRAIN
57204 * 0b10..OPEN_DRAIN_INPUT
57205 * 0b11..INOUT
57206 * 0b00..DEFAULT
57207 */
57208#define IOMUXD_ESAI0_SCKT_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_sw_config_SHIFT)) & IOMUXD_ESAI0_SCKT_sw_config_MASK)
57209#define IOMUXD_ESAI0_SCKT_mux_mode_MASK (0x38000000U)
57210#define IOMUXD_ESAI0_SCKT_mux_mode_SHIFT (27U)
57211/*! mux_mode - mux_mode
57212 * 0b000..ADMA.ESAI0.SCKT
57213 * 0b001..CONN.MLB.SIG
57214 * 0b010..ADMA.LCDIF.D03
57215 * 0b011..CONN.ENET1.RGMII_TXD3
57216 * 0b100..LSIO.GPIO0.IO03
57217 */
57218#define IOMUXD_ESAI0_SCKT_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_mux_mode_SHIFT)) & IOMUXD_ESAI0_SCKT_mux_mode_MASK)
57219#define IOMUXD_ESAI0_SCKT_update_pad_ctl_MASK (0x40000000U)
57220#define IOMUXD_ESAI0_SCKT_update_pad_ctl_SHIFT (30U)
57221/*! update_pad_ctl - update lock for pad control
57222 */
57223#define IOMUXD_ESAI0_SCKT_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_SCKT_update_pad_ctl_MASK)
57224#define IOMUXD_ESAI0_SCKT_update_mux_mode_MASK (0x80000000U)
57225#define IOMUXD_ESAI0_SCKT_update_mux_mode_SHIFT (31U)
57226/*! update_mux_mode - update lock for mux control
57227 */
57228#define IOMUXD_ESAI0_SCKT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_SCKT_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_SCKT_update_mux_mode_MASK)
57229/*! @} */
57230
57231/*! @name ESAI0_TX0 - ESAI0_TX0 */
57232/*! @{ */
57233#define IOMUXD_ESAI0_TX0_PDRV_MASK (0x1U)
57234#define IOMUXD_ESAI0_TX0_PDRV_SHIFT (0U)
57235/*! PDRV - Drive
57236 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57237 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57238 */
57239#define IOMUXD_ESAI0_TX0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_PDRV_SHIFT)) & IOMUXD_ESAI0_TX0_PDRV_MASK)
57240#define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_1_4_MASK (0x1EU)
57241#define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_1_4_SHIFT (1U)
57242/*! ESAI0_TX0_reserved_1_4 - reserved
57243 */
57244#define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_1_4_MASK)
57245#define IOMUXD_ESAI0_TX0_PULL_MASK (0x60U)
57246#define IOMUXD_ESAI0_TX0_PULL_SHIFT (5U)
57247/*! PULL - Pull Down Pull Up
57248 * 0b10..pull down
57249 * 0b01..pull up
57250 * 0b00..Prohibited
57251 * 0b11..pull disabled
57252 */
57253#define IOMUXD_ESAI0_TX0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_PULL_SHIFT)) & IOMUXD_ESAI0_TX0_PULL_MASK)
57254#define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_7_18_MASK (0x7FF80U)
57255#define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_7_18_SHIFT (7U)
57256/*! ESAI0_TX0_reserved_7_18 - reserved
57257 */
57258#define IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX0_ESAI0_TX0_reserved_7_18_MASK)
57259#define IOMUXD_ESAI0_TX0_WAKEUP_CTRL_MASK (0x380000U)
57260#define IOMUXD_ESAI0_TX0_WAKEUP_CTRL_SHIFT (19U)
57261/*! WAKEUP_CTRL - wakeup control
57262 * 0b000..OFF
57263 * 0b001..RESAMPLE
57264 * 0b100..LOW
57265 * 0b111..HIGH
57266 * 0b110..RISE
57267 * 0b101..FALL
57268 */
57269#define IOMUXD_ESAI0_TX0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX0_WAKEUP_CTRL_MASK)
57270#define IOMUXD_ESAI0_TX0_WAKEUP_MASK_MASK (0x400000U)
57271#define IOMUXD_ESAI0_TX0_WAKEUP_MASK_SHIFT (22U)
57272/*! WAKEUP_MASK - wakeup mask
57273 */
57274#define IOMUXD_ESAI0_TX0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX0_WAKEUP_MASK_MASK)
57275#define IOMUXD_ESAI0_TX0_lp_config_MASK (0x1800000U)
57276#define IOMUXD_ESAI0_TX0_lp_config_SHIFT (23U)
57277/*! lp_config - lower power configuration
57278 * 0b01..EARLY_ISO
57279 * 0b10..LATE_ISO
57280 * 0b11..LATCH
57281 * 0b00..PASS
57282 */
57283#define IOMUXD_ESAI0_TX0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_lp_config_SHIFT)) & IOMUXD_ESAI0_TX0_lp_config_MASK)
57284#define IOMUXD_ESAI0_TX0_sw_config_MASK (0x6000000U)
57285#define IOMUXD_ESAI0_TX0_sw_config_SHIFT (25U)
57286/*! sw_config - output and input configuration
57287 * 0b01..OPEN_DRAIN
57288 * 0b10..OPEN_DRAIN_INPUT
57289 * 0b11..INOUT
57290 * 0b00..DEFAULT
57291 */
57292#define IOMUXD_ESAI0_TX0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_sw_config_SHIFT)) & IOMUXD_ESAI0_TX0_sw_config_MASK)
57293#define IOMUXD_ESAI0_TX0_mux_mode_MASK (0x38000000U)
57294#define IOMUXD_ESAI0_TX0_mux_mode_SHIFT (27U)
57295/*! mux_mode - mux_mode
57296 * 0b000..ADMA.ESAI0.TX0
57297 * 0b001..CONN.MLB.DATA
57298 * 0b010..ADMA.LCDIF.D04
57299 * 0b011..CONN.ENET1.RGMII_RXC
57300 * 0b100..LSIO.GPIO0.IO04
57301 */
57302#define IOMUXD_ESAI0_TX0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX0_mux_mode_MASK)
57303#define IOMUXD_ESAI0_TX0_update_pad_ctl_MASK (0x40000000U)
57304#define IOMUXD_ESAI0_TX0_update_pad_ctl_SHIFT (30U)
57305/*! update_pad_ctl - update lock for pad control
57306 */
57307#define IOMUXD_ESAI0_TX0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX0_update_pad_ctl_MASK)
57308#define IOMUXD_ESAI0_TX0_update_mux_mode_MASK (0x80000000U)
57309#define IOMUXD_ESAI0_TX0_update_mux_mode_SHIFT (31U)
57310/*! update_mux_mode - update lock for mux control
57311 */
57312#define IOMUXD_ESAI0_TX0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX0_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX0_update_mux_mode_MASK)
57313/*! @} */
57314
57315/*! @name ESAI0_TX1 - ESAI0_TX1 */
57316/*! @{ */
57317#define IOMUXD_ESAI0_TX1_PDRV_MASK (0x1U)
57318#define IOMUXD_ESAI0_TX1_PDRV_SHIFT (0U)
57319/*! PDRV - Drive
57320 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57321 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57322 */
57323#define IOMUXD_ESAI0_TX1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_PDRV_SHIFT)) & IOMUXD_ESAI0_TX1_PDRV_MASK)
57324#define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_1_4_MASK (0x1EU)
57325#define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_1_4_SHIFT (1U)
57326/*! ESAI0_TX1_reserved_1_4 - reserved
57327 */
57328#define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_1_4_MASK)
57329#define IOMUXD_ESAI0_TX1_PULL_MASK (0x60U)
57330#define IOMUXD_ESAI0_TX1_PULL_SHIFT (5U)
57331/*! PULL - Pull Down Pull Up
57332 * 0b10..pull down
57333 * 0b01..pull up
57334 * 0b00..Prohibited
57335 * 0b11..pull disabled
57336 */
57337#define IOMUXD_ESAI0_TX1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_PULL_SHIFT)) & IOMUXD_ESAI0_TX1_PULL_MASK)
57338#define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_7_18_MASK (0x7FF80U)
57339#define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_7_18_SHIFT (7U)
57340/*! ESAI0_TX1_reserved_7_18 - reserved
57341 */
57342#define IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX1_ESAI0_TX1_reserved_7_18_MASK)
57343#define IOMUXD_ESAI0_TX1_WAKEUP_CTRL_MASK (0x380000U)
57344#define IOMUXD_ESAI0_TX1_WAKEUP_CTRL_SHIFT (19U)
57345/*! WAKEUP_CTRL - wakeup control
57346 * 0b000..OFF
57347 * 0b001..RESAMPLE
57348 * 0b100..LOW
57349 * 0b111..HIGH
57350 * 0b110..RISE
57351 * 0b101..FALL
57352 */
57353#define IOMUXD_ESAI0_TX1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX1_WAKEUP_CTRL_MASK)
57354#define IOMUXD_ESAI0_TX1_WAKEUP_MASK_MASK (0x400000U)
57355#define IOMUXD_ESAI0_TX1_WAKEUP_MASK_SHIFT (22U)
57356/*! WAKEUP_MASK - wakeup mask
57357 */
57358#define IOMUXD_ESAI0_TX1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX1_WAKEUP_MASK_MASK)
57359#define IOMUXD_ESAI0_TX1_lp_config_MASK (0x1800000U)
57360#define IOMUXD_ESAI0_TX1_lp_config_SHIFT (23U)
57361/*! lp_config - lower power configuration
57362 * 0b01..EARLY_ISO
57363 * 0b10..LATE_ISO
57364 * 0b11..LATCH
57365 * 0b00..PASS
57366 */
57367#define IOMUXD_ESAI0_TX1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_lp_config_SHIFT)) & IOMUXD_ESAI0_TX1_lp_config_MASK)
57368#define IOMUXD_ESAI0_TX1_sw_config_MASK (0x6000000U)
57369#define IOMUXD_ESAI0_TX1_sw_config_SHIFT (25U)
57370/*! sw_config - output and input configuration
57371 * 0b01..OPEN_DRAIN
57372 * 0b10..OPEN_DRAIN_INPUT
57373 * 0b11..INOUT
57374 * 0b00..DEFAULT
57375 */
57376#define IOMUXD_ESAI0_TX1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_sw_config_SHIFT)) & IOMUXD_ESAI0_TX1_sw_config_MASK)
57377#define IOMUXD_ESAI0_TX1_mux_mode_MASK (0x38000000U)
57378#define IOMUXD_ESAI0_TX1_mux_mode_SHIFT (27U)
57379/*! mux_mode - mux_mode
57380 * 0b000..ADMA.ESAI0.TX1
57381 * 0b010..ADMA.LCDIF.D05
57382 * 0b011..CONN.ENET1.RGMII_RXD3
57383 * 0b100..LSIO.GPIO0.IO05
57384 */
57385#define IOMUXD_ESAI0_TX1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX1_mux_mode_MASK)
57386#define IOMUXD_ESAI0_TX1_update_pad_ctl_MASK (0x40000000U)
57387#define IOMUXD_ESAI0_TX1_update_pad_ctl_SHIFT (30U)
57388/*! update_pad_ctl - update lock for pad control
57389 */
57390#define IOMUXD_ESAI0_TX1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX1_update_pad_ctl_MASK)
57391#define IOMUXD_ESAI0_TX1_update_mux_mode_MASK (0x80000000U)
57392#define IOMUXD_ESAI0_TX1_update_mux_mode_SHIFT (31U)
57393/*! update_mux_mode - update lock for mux control
57394 */
57395#define IOMUXD_ESAI0_TX1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX1_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX1_update_mux_mode_MASK)
57396/*! @} */
57397
57398/*! @name ESAI0_TX2_RX3 - ESAI0_TX2_RX3 */
57399/*! @{ */
57400#define IOMUXD_ESAI0_TX2_RX3_PDRV_MASK (0x1U)
57401#define IOMUXD_ESAI0_TX2_RX3_PDRV_SHIFT (0U)
57402/*! PDRV - Drive
57403 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57404 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57405 */
57406#define IOMUXD_ESAI0_TX2_RX3_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_PDRV_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_PDRV_MASK)
57407#define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_1_4_MASK (0x1EU)
57408#define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_1_4_SHIFT (1U)
57409/*! ESAI0_TX2_RX3_reserved_1_4 - reserved
57410 */
57411#define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_1_4_MASK)
57412#define IOMUXD_ESAI0_TX2_RX3_PULL_MASK (0x60U)
57413#define IOMUXD_ESAI0_TX2_RX3_PULL_SHIFT (5U)
57414/*! PULL - Pull Down Pull Up
57415 * 0b10..pull down
57416 * 0b01..pull up
57417 * 0b00..Prohibited
57418 * 0b11..pull disabled
57419 */
57420#define IOMUXD_ESAI0_TX2_RX3_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_PULL_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_PULL_MASK)
57421#define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_7_18_MASK (0x7FF80U)
57422#define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_7_18_SHIFT (7U)
57423/*! ESAI0_TX2_RX3_reserved_7_18 - reserved
57424 */
57425#define IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_ESAI0_TX2_RX3_reserved_7_18_MASK)
57426#define IOMUXD_ESAI0_TX2_RX3_WAKEUP_CTRL_MASK (0x380000U)
57427#define IOMUXD_ESAI0_TX2_RX3_WAKEUP_CTRL_SHIFT (19U)
57428/*! WAKEUP_CTRL - wakeup control
57429 * 0b000..OFF
57430 * 0b001..RESAMPLE
57431 * 0b100..LOW
57432 * 0b111..HIGH
57433 * 0b110..RISE
57434 * 0b101..FALL
57435 */
57436#define IOMUXD_ESAI0_TX2_RX3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_WAKEUP_CTRL_MASK)
57437#define IOMUXD_ESAI0_TX2_RX3_WAKEUP_MASK_MASK (0x400000U)
57438#define IOMUXD_ESAI0_TX2_RX3_WAKEUP_MASK_SHIFT (22U)
57439/*! WAKEUP_MASK - wakeup mask
57440 */
57441#define IOMUXD_ESAI0_TX2_RX3_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_WAKEUP_MASK_MASK)
57442#define IOMUXD_ESAI0_TX2_RX3_lp_config_MASK (0x1800000U)
57443#define IOMUXD_ESAI0_TX2_RX3_lp_config_SHIFT (23U)
57444/*! lp_config - lower power configuration
57445 * 0b01..EARLY_ISO
57446 * 0b10..LATE_ISO
57447 * 0b11..LATCH
57448 * 0b00..PASS
57449 */
57450#define IOMUXD_ESAI0_TX2_RX3_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_lp_config_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_lp_config_MASK)
57451#define IOMUXD_ESAI0_TX2_RX3_sw_config_MASK (0x6000000U)
57452#define IOMUXD_ESAI0_TX2_RX3_sw_config_SHIFT (25U)
57453/*! sw_config - output and input configuration
57454 * 0b01..OPEN_DRAIN
57455 * 0b10..OPEN_DRAIN_INPUT
57456 * 0b11..INOUT
57457 * 0b00..DEFAULT
57458 */
57459#define IOMUXD_ESAI0_TX2_RX3_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_sw_config_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_sw_config_MASK)
57460#define IOMUXD_ESAI0_TX2_RX3_mux_mode_MASK (0x38000000U)
57461#define IOMUXD_ESAI0_TX2_RX3_mux_mode_SHIFT (27U)
57462/*! mux_mode - mux_mode
57463 * 0b000..ADMA.ESAI0.TX2_RX3
57464 * 0b001..CONN.ENET1.RMII_RX_ER
57465 * 0b010..ADMA.LCDIF.D06
57466 * 0b011..CONN.ENET1.RGMII_RXD2
57467 * 0b100..LSIO.GPIO0.IO06
57468 */
57469#define IOMUXD_ESAI0_TX2_RX3_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_mux_mode_MASK)
57470#define IOMUXD_ESAI0_TX2_RX3_update_pad_ctl_MASK (0x40000000U)
57471#define IOMUXD_ESAI0_TX2_RX3_update_pad_ctl_SHIFT (30U)
57472/*! update_pad_ctl - update lock for pad control
57473 */
57474#define IOMUXD_ESAI0_TX2_RX3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_update_pad_ctl_MASK)
57475#define IOMUXD_ESAI0_TX2_RX3_update_mux_mode_MASK (0x80000000U)
57476#define IOMUXD_ESAI0_TX2_RX3_update_mux_mode_SHIFT (31U)
57477/*! update_mux_mode - update lock for mux control
57478 */
57479#define IOMUXD_ESAI0_TX2_RX3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX2_RX3_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX2_RX3_update_mux_mode_MASK)
57480/*! @} */
57481
57482/*! @name ESAI0_TX3_RX2 - ESAI0_TX3_RX2 */
57483/*! @{ */
57484#define IOMUXD_ESAI0_TX3_RX2_PDRV_MASK (0x1U)
57485#define IOMUXD_ESAI0_TX3_RX2_PDRV_SHIFT (0U)
57486/*! PDRV - Drive
57487 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57488 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57489 */
57490#define IOMUXD_ESAI0_TX3_RX2_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_PDRV_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_PDRV_MASK)
57491#define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_1_4_MASK (0x1EU)
57492#define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_1_4_SHIFT (1U)
57493/*! ESAI0_TX3_RX2_reserved_1_4 - reserved
57494 */
57495#define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_1_4_MASK)
57496#define IOMUXD_ESAI0_TX3_RX2_PULL_MASK (0x60U)
57497#define IOMUXD_ESAI0_TX3_RX2_PULL_SHIFT (5U)
57498/*! PULL - Pull Down Pull Up
57499 * 0b10..pull down
57500 * 0b01..pull up
57501 * 0b00..Prohibited
57502 * 0b11..pull disabled
57503 */
57504#define IOMUXD_ESAI0_TX3_RX2_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_PULL_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_PULL_MASK)
57505#define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_7_18_MASK (0x7FF80U)
57506#define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_7_18_SHIFT (7U)
57507/*! ESAI0_TX3_RX2_reserved_7_18 - reserved
57508 */
57509#define IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_ESAI0_TX3_RX2_reserved_7_18_MASK)
57510#define IOMUXD_ESAI0_TX3_RX2_WAKEUP_CTRL_MASK (0x380000U)
57511#define IOMUXD_ESAI0_TX3_RX2_WAKEUP_CTRL_SHIFT (19U)
57512/*! WAKEUP_CTRL - wakeup control
57513 * 0b000..OFF
57514 * 0b001..RESAMPLE
57515 * 0b100..LOW
57516 * 0b111..HIGH
57517 * 0b110..RISE
57518 * 0b101..FALL
57519 */
57520#define IOMUXD_ESAI0_TX3_RX2_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_WAKEUP_CTRL_MASK)
57521#define IOMUXD_ESAI0_TX3_RX2_WAKEUP_MASK_MASK (0x400000U)
57522#define IOMUXD_ESAI0_TX3_RX2_WAKEUP_MASK_SHIFT (22U)
57523/*! WAKEUP_MASK - wakeup mask
57524 */
57525#define IOMUXD_ESAI0_TX3_RX2_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_WAKEUP_MASK_MASK)
57526#define IOMUXD_ESAI0_TX3_RX2_lp_config_MASK (0x1800000U)
57527#define IOMUXD_ESAI0_TX3_RX2_lp_config_SHIFT (23U)
57528/*! lp_config - lower power configuration
57529 * 0b01..EARLY_ISO
57530 * 0b10..LATE_ISO
57531 * 0b11..LATCH
57532 * 0b00..PASS
57533 */
57534#define IOMUXD_ESAI0_TX3_RX2_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_lp_config_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_lp_config_MASK)
57535#define IOMUXD_ESAI0_TX3_RX2_sw_config_MASK (0x6000000U)
57536#define IOMUXD_ESAI0_TX3_RX2_sw_config_SHIFT (25U)
57537/*! sw_config - output and input configuration
57538 * 0b01..OPEN_DRAIN
57539 * 0b10..OPEN_DRAIN_INPUT
57540 * 0b11..INOUT
57541 * 0b00..DEFAULT
57542 */
57543#define IOMUXD_ESAI0_TX3_RX2_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_sw_config_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_sw_config_MASK)
57544#define IOMUXD_ESAI0_TX3_RX2_mux_mode_MASK (0x38000000U)
57545#define IOMUXD_ESAI0_TX3_RX2_mux_mode_SHIFT (27U)
57546/*! mux_mode - mux_mode
57547 * 0b000..ADMA.ESAI0.TX3_RX2
57548 * 0b010..ADMA.LCDIF.D07
57549 * 0b011..CONN.ENET1.RGMII_RXD1
57550 * 0b100..LSIO.GPIO0.IO07
57551 */
57552#define IOMUXD_ESAI0_TX3_RX2_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_mux_mode_MASK)
57553#define IOMUXD_ESAI0_TX3_RX2_update_pad_ctl_MASK (0x40000000U)
57554#define IOMUXD_ESAI0_TX3_RX2_update_pad_ctl_SHIFT (30U)
57555/*! update_pad_ctl - update lock for pad control
57556 */
57557#define IOMUXD_ESAI0_TX3_RX2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_update_pad_ctl_MASK)
57558#define IOMUXD_ESAI0_TX3_RX2_update_mux_mode_MASK (0x80000000U)
57559#define IOMUXD_ESAI0_TX3_RX2_update_mux_mode_SHIFT (31U)
57560/*! update_mux_mode - update lock for mux control
57561 */
57562#define IOMUXD_ESAI0_TX3_RX2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX3_RX2_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX3_RX2_update_mux_mode_MASK)
57563/*! @} */
57564
57565/*! @name ESAI0_TX4_RX1 - ESAI0_TX4_RX1 */
57566/*! @{ */
57567#define IOMUXD_ESAI0_TX4_RX1_PDRV_MASK (0x1U)
57568#define IOMUXD_ESAI0_TX4_RX1_PDRV_SHIFT (0U)
57569/*! PDRV - Drive
57570 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57571 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57572 */
57573#define IOMUXD_ESAI0_TX4_RX1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_PDRV_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_PDRV_MASK)
57574#define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_1_4_MASK (0x1EU)
57575#define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_1_4_SHIFT (1U)
57576/*! ESAI0_TX4_RX1_reserved_1_4 - reserved
57577 */
57578#define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_1_4_MASK)
57579#define IOMUXD_ESAI0_TX4_RX1_PULL_MASK (0x60U)
57580#define IOMUXD_ESAI0_TX4_RX1_PULL_SHIFT (5U)
57581/*! PULL - Pull Down Pull Up
57582 * 0b10..pull down
57583 * 0b01..pull up
57584 * 0b00..Prohibited
57585 * 0b11..pull disabled
57586 */
57587#define IOMUXD_ESAI0_TX4_RX1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_PULL_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_PULL_MASK)
57588#define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_7_18_MASK (0x7FF80U)
57589#define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_7_18_SHIFT (7U)
57590/*! ESAI0_TX4_RX1_reserved_7_18 - reserved
57591 */
57592#define IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_ESAI0_TX4_RX1_reserved_7_18_MASK)
57593#define IOMUXD_ESAI0_TX4_RX1_WAKEUP_CTRL_MASK (0x380000U)
57594#define IOMUXD_ESAI0_TX4_RX1_WAKEUP_CTRL_SHIFT (19U)
57595/*! WAKEUP_CTRL - wakeup control
57596 * 0b000..OFF
57597 * 0b001..RESAMPLE
57598 * 0b100..LOW
57599 * 0b111..HIGH
57600 * 0b110..RISE
57601 * 0b101..FALL
57602 */
57603#define IOMUXD_ESAI0_TX4_RX1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_WAKEUP_CTRL_MASK)
57604#define IOMUXD_ESAI0_TX4_RX1_WAKEUP_MASK_MASK (0x400000U)
57605#define IOMUXD_ESAI0_TX4_RX1_WAKEUP_MASK_SHIFT (22U)
57606/*! WAKEUP_MASK - wakeup mask
57607 */
57608#define IOMUXD_ESAI0_TX4_RX1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_WAKEUP_MASK_MASK)
57609#define IOMUXD_ESAI0_TX4_RX1_lp_config_MASK (0x1800000U)
57610#define IOMUXD_ESAI0_TX4_RX1_lp_config_SHIFT (23U)
57611/*! lp_config - lower power configuration
57612 * 0b01..EARLY_ISO
57613 * 0b10..LATE_ISO
57614 * 0b11..LATCH
57615 * 0b00..PASS
57616 */
57617#define IOMUXD_ESAI0_TX4_RX1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_lp_config_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_lp_config_MASK)
57618#define IOMUXD_ESAI0_TX4_RX1_sw_config_MASK (0x6000000U)
57619#define IOMUXD_ESAI0_TX4_RX1_sw_config_SHIFT (25U)
57620/*! sw_config - output and input configuration
57621 * 0b01..OPEN_DRAIN
57622 * 0b10..OPEN_DRAIN_INPUT
57623 * 0b11..INOUT
57624 * 0b00..DEFAULT
57625 */
57626#define IOMUXD_ESAI0_TX4_RX1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_sw_config_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_sw_config_MASK)
57627#define IOMUXD_ESAI0_TX4_RX1_mux_mode_MASK (0x38000000U)
57628#define IOMUXD_ESAI0_TX4_RX1_mux_mode_SHIFT (27U)
57629/*! mux_mode - mux_mode
57630 * 0b000..ADMA.ESAI0.TX4_RX1
57631 * 0b010..ADMA.LCDIF.D08
57632 * 0b011..CONN.ENET1.RGMII_TXD0
57633 * 0b100..LSIO.GPIO0.IO08
57634 */
57635#define IOMUXD_ESAI0_TX4_RX1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_mux_mode_MASK)
57636#define IOMUXD_ESAI0_TX4_RX1_update_pad_ctl_MASK (0x40000000U)
57637#define IOMUXD_ESAI0_TX4_RX1_update_pad_ctl_SHIFT (30U)
57638/*! update_pad_ctl - update lock for pad control
57639 */
57640#define IOMUXD_ESAI0_TX4_RX1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_update_pad_ctl_MASK)
57641#define IOMUXD_ESAI0_TX4_RX1_update_mux_mode_MASK (0x80000000U)
57642#define IOMUXD_ESAI0_TX4_RX1_update_mux_mode_SHIFT (31U)
57643/*! update_mux_mode - update lock for mux control
57644 */
57645#define IOMUXD_ESAI0_TX4_RX1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX4_RX1_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX4_RX1_update_mux_mode_MASK)
57646/*! @} */
57647
57648/*! @name ESAI0_TX5_RX0 - ESAI0_TX5_RX0 */
57649/*! @{ */
57650#define IOMUXD_ESAI0_TX5_RX0_PDRV_MASK (0x1U)
57651#define IOMUXD_ESAI0_TX5_RX0_PDRV_SHIFT (0U)
57652/*! PDRV - Drive
57653 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57654 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57655 */
57656#define IOMUXD_ESAI0_TX5_RX0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_PDRV_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_PDRV_MASK)
57657#define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_1_4_MASK (0x1EU)
57658#define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_1_4_SHIFT (1U)
57659/*! ESAI0_TX5_RX0_reserved_1_4 - reserved
57660 */
57661#define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_1_4_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_1_4_MASK)
57662#define IOMUXD_ESAI0_TX5_RX0_PULL_MASK (0x60U)
57663#define IOMUXD_ESAI0_TX5_RX0_PULL_SHIFT (5U)
57664/*! PULL - Pull Down Pull Up
57665 * 0b10..pull down
57666 * 0b01..pull up
57667 * 0b00..Prohibited
57668 * 0b11..pull disabled
57669 */
57670#define IOMUXD_ESAI0_TX5_RX0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_PULL_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_PULL_MASK)
57671#define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_7_18_MASK (0x7FF80U)
57672#define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_7_18_SHIFT (7U)
57673/*! ESAI0_TX5_RX0_reserved_7_18 - reserved
57674 */
57675#define IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_7_18_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_ESAI0_TX5_RX0_reserved_7_18_MASK)
57676#define IOMUXD_ESAI0_TX5_RX0_WAKEUP_CTRL_MASK (0x380000U)
57677#define IOMUXD_ESAI0_TX5_RX0_WAKEUP_CTRL_SHIFT (19U)
57678/*! WAKEUP_CTRL - wakeup control
57679 * 0b000..OFF
57680 * 0b001..RESAMPLE
57681 * 0b100..LOW
57682 * 0b111..HIGH
57683 * 0b110..RISE
57684 * 0b101..FALL
57685 */
57686#define IOMUXD_ESAI0_TX5_RX0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_WAKEUP_CTRL_MASK)
57687#define IOMUXD_ESAI0_TX5_RX0_WAKEUP_MASK_MASK (0x400000U)
57688#define IOMUXD_ESAI0_TX5_RX0_WAKEUP_MASK_SHIFT (22U)
57689/*! WAKEUP_MASK - wakeup mask
57690 */
57691#define IOMUXD_ESAI0_TX5_RX0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_WAKEUP_MASK_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_WAKEUP_MASK_MASK)
57692#define IOMUXD_ESAI0_TX5_RX0_lp_config_MASK (0x1800000U)
57693#define IOMUXD_ESAI0_TX5_RX0_lp_config_SHIFT (23U)
57694/*! lp_config - lower power configuration
57695 * 0b01..EARLY_ISO
57696 * 0b10..LATE_ISO
57697 * 0b11..LATCH
57698 * 0b00..PASS
57699 */
57700#define IOMUXD_ESAI0_TX5_RX0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_lp_config_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_lp_config_MASK)
57701#define IOMUXD_ESAI0_TX5_RX0_sw_config_MASK (0x6000000U)
57702#define IOMUXD_ESAI0_TX5_RX0_sw_config_SHIFT (25U)
57703/*! sw_config - output and input configuration
57704 * 0b01..OPEN_DRAIN
57705 * 0b10..OPEN_DRAIN_INPUT
57706 * 0b11..INOUT
57707 * 0b00..DEFAULT
57708 */
57709#define IOMUXD_ESAI0_TX5_RX0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_sw_config_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_sw_config_MASK)
57710#define IOMUXD_ESAI0_TX5_RX0_mux_mode_MASK (0x38000000U)
57711#define IOMUXD_ESAI0_TX5_RX0_mux_mode_SHIFT (27U)
57712/*! mux_mode - mux_mode
57713 * 0b000..ADMA.ESAI0.TX5_RX0
57714 * 0b010..ADMA.LCDIF.D09
57715 * 0b011..CONN.ENET1.RGMII_TXD1
57716 * 0b100..LSIO.GPIO0.IO09
57717 */
57718#define IOMUXD_ESAI0_TX5_RX0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_mux_mode_MASK)
57719#define IOMUXD_ESAI0_TX5_RX0_update_pad_ctl_MASK (0x40000000U)
57720#define IOMUXD_ESAI0_TX5_RX0_update_pad_ctl_SHIFT (30U)
57721/*! update_pad_ctl - update lock for pad control
57722 */
57723#define IOMUXD_ESAI0_TX5_RX0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_update_pad_ctl_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_update_pad_ctl_MASK)
57724#define IOMUXD_ESAI0_TX5_RX0_update_mux_mode_MASK (0x80000000U)
57725#define IOMUXD_ESAI0_TX5_RX0_update_mux_mode_SHIFT (31U)
57726/*! update_mux_mode - update lock for mux control
57727 */
57728#define IOMUXD_ESAI0_TX5_RX0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ESAI0_TX5_RX0_update_mux_mode_SHIFT)) & IOMUXD_ESAI0_TX5_RX0_update_mux_mode_MASK)
57729/*! @} */
57730
57731/*! @name SPDIF0_RX - SPDIF0_RX */
57732/*! @{ */
57733#define IOMUXD_SPDIF0_RX_PDRV_MASK (0x1U)
57734#define IOMUXD_SPDIF0_RX_PDRV_SHIFT (0U)
57735/*! PDRV - Drive
57736 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57737 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57738 */
57739#define IOMUXD_SPDIF0_RX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_PDRV_SHIFT)) & IOMUXD_SPDIF0_RX_PDRV_MASK)
57740#define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_1_4_MASK (0x1EU)
57741#define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_1_4_SHIFT (1U)
57742/*! SPDIF0_RX_reserved_1_4 - reserved
57743 */
57744#define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_1_4_SHIFT)) & IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_1_4_MASK)
57745#define IOMUXD_SPDIF0_RX_PULL_MASK (0x60U)
57746#define IOMUXD_SPDIF0_RX_PULL_SHIFT (5U)
57747/*! PULL - Pull Down Pull Up
57748 * 0b10..pull down
57749 * 0b01..pull up
57750 * 0b00..Prohibited
57751 * 0b11..pull disabled
57752 */
57753#define IOMUXD_SPDIF0_RX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_PULL_SHIFT)) & IOMUXD_SPDIF0_RX_PULL_MASK)
57754#define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_7_18_MASK (0x7FF80U)
57755#define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_7_18_SHIFT (7U)
57756/*! SPDIF0_RX_reserved_7_18 - reserved
57757 */
57758#define IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_7_18_SHIFT)) & IOMUXD_SPDIF0_RX_SPDIF0_RX_reserved_7_18_MASK)
57759#define IOMUXD_SPDIF0_RX_WAKEUP_CTRL_MASK (0x380000U)
57760#define IOMUXD_SPDIF0_RX_WAKEUP_CTRL_SHIFT (19U)
57761/*! WAKEUP_CTRL - wakeup control
57762 * 0b000..OFF
57763 * 0b001..RESAMPLE
57764 * 0b100..LOW
57765 * 0b111..HIGH
57766 * 0b110..RISE
57767 * 0b101..FALL
57768 */
57769#define IOMUXD_SPDIF0_RX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPDIF0_RX_WAKEUP_CTRL_MASK)
57770#define IOMUXD_SPDIF0_RX_WAKEUP_MASK_MASK (0x400000U)
57771#define IOMUXD_SPDIF0_RX_WAKEUP_MASK_SHIFT (22U)
57772/*! WAKEUP_MASK - wakeup mask
57773 */
57774#define IOMUXD_SPDIF0_RX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_SPDIF0_RX_WAKEUP_MASK_MASK)
57775#define IOMUXD_SPDIF0_RX_lp_config_MASK (0x1800000U)
57776#define IOMUXD_SPDIF0_RX_lp_config_SHIFT (23U)
57777/*! lp_config - lower power configuration
57778 * 0b01..EARLY_ISO
57779 * 0b10..LATE_ISO
57780 * 0b11..LATCH
57781 * 0b00..PASS
57782 */
57783#define IOMUXD_SPDIF0_RX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_lp_config_SHIFT)) & IOMUXD_SPDIF0_RX_lp_config_MASK)
57784#define IOMUXD_SPDIF0_RX_sw_config_MASK (0x6000000U)
57785#define IOMUXD_SPDIF0_RX_sw_config_SHIFT (25U)
57786/*! sw_config - output and input configuration
57787 * 0b01..OPEN_DRAIN
57788 * 0b10..OPEN_DRAIN_INPUT
57789 * 0b11..INOUT
57790 * 0b00..DEFAULT
57791 */
57792#define IOMUXD_SPDIF0_RX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_sw_config_SHIFT)) & IOMUXD_SPDIF0_RX_sw_config_MASK)
57793#define IOMUXD_SPDIF0_RX_mux_mode_MASK (0x38000000U)
57794#define IOMUXD_SPDIF0_RX_mux_mode_SHIFT (27U)
57795/*! mux_mode - mux_mode
57796 * 0b000..ADMA.SPDIF0.RX
57797 * 0b001..ADMA.MQS.R
57798 * 0b010..ADMA.LCDIF.D10
57799 * 0b011..CONN.ENET1.RGMII_RXD0
57800 * 0b100..LSIO.GPIO0.IO10
57801 */
57802#define IOMUXD_SPDIF0_RX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_mux_mode_SHIFT)) & IOMUXD_SPDIF0_RX_mux_mode_MASK)
57803#define IOMUXD_SPDIF0_RX_update_pad_ctl_MASK (0x40000000U)
57804#define IOMUXD_SPDIF0_RX_update_pad_ctl_SHIFT (30U)
57805/*! update_pad_ctl - update lock for pad control
57806 */
57807#define IOMUXD_SPDIF0_RX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_update_pad_ctl_SHIFT)) & IOMUXD_SPDIF0_RX_update_pad_ctl_MASK)
57808#define IOMUXD_SPDIF0_RX_update_mux_mode_MASK (0x80000000U)
57809#define IOMUXD_SPDIF0_RX_update_mux_mode_SHIFT (31U)
57810/*! update_mux_mode - update lock for mux control
57811 */
57812#define IOMUXD_SPDIF0_RX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_RX_update_mux_mode_SHIFT)) & IOMUXD_SPDIF0_RX_update_mux_mode_MASK)
57813/*! @} */
57814
57815/*! @name SPDIF0_TX - SPDIF0_TX */
57816/*! @{ */
57817#define IOMUXD_SPDIF0_TX_PDRV_MASK (0x1U)
57818#define IOMUXD_SPDIF0_TX_PDRV_SHIFT (0U)
57819/*! PDRV - Drive
57820 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57821 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57822 */
57823#define IOMUXD_SPDIF0_TX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_PDRV_SHIFT)) & IOMUXD_SPDIF0_TX_PDRV_MASK)
57824#define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_1_4_MASK (0x1EU)
57825#define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_1_4_SHIFT (1U)
57826/*! SPDIF0_TX_reserved_1_4 - reserved
57827 */
57828#define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_1_4_SHIFT)) & IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_1_4_MASK)
57829#define IOMUXD_SPDIF0_TX_PULL_MASK (0x60U)
57830#define IOMUXD_SPDIF0_TX_PULL_SHIFT (5U)
57831/*! PULL - Pull Down Pull Up
57832 * 0b10..pull down
57833 * 0b01..pull up
57834 * 0b00..Prohibited
57835 * 0b11..pull disabled
57836 */
57837#define IOMUXD_SPDIF0_TX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_PULL_SHIFT)) & IOMUXD_SPDIF0_TX_PULL_MASK)
57838#define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_7_18_MASK (0x7FF80U)
57839#define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_7_18_SHIFT (7U)
57840/*! SPDIF0_TX_reserved_7_18 - reserved
57841 */
57842#define IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_7_18_SHIFT)) & IOMUXD_SPDIF0_TX_SPDIF0_TX_reserved_7_18_MASK)
57843#define IOMUXD_SPDIF0_TX_WAKEUP_CTRL_MASK (0x380000U)
57844#define IOMUXD_SPDIF0_TX_WAKEUP_CTRL_SHIFT (19U)
57845/*! WAKEUP_CTRL - wakeup control
57846 * 0b000..OFF
57847 * 0b001..RESAMPLE
57848 * 0b100..LOW
57849 * 0b111..HIGH
57850 * 0b110..RISE
57851 * 0b101..FALL
57852 */
57853#define IOMUXD_SPDIF0_TX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPDIF0_TX_WAKEUP_CTRL_MASK)
57854#define IOMUXD_SPDIF0_TX_WAKEUP_MASK_MASK (0x400000U)
57855#define IOMUXD_SPDIF0_TX_WAKEUP_MASK_SHIFT (22U)
57856/*! WAKEUP_MASK - wakeup mask
57857 */
57858#define IOMUXD_SPDIF0_TX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_SPDIF0_TX_WAKEUP_MASK_MASK)
57859#define IOMUXD_SPDIF0_TX_lp_config_MASK (0x1800000U)
57860#define IOMUXD_SPDIF0_TX_lp_config_SHIFT (23U)
57861/*! lp_config - lower power configuration
57862 * 0b01..EARLY_ISO
57863 * 0b10..LATE_ISO
57864 * 0b11..LATCH
57865 * 0b00..PASS
57866 */
57867#define IOMUXD_SPDIF0_TX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_lp_config_SHIFT)) & IOMUXD_SPDIF0_TX_lp_config_MASK)
57868#define IOMUXD_SPDIF0_TX_sw_config_MASK (0x6000000U)
57869#define IOMUXD_SPDIF0_TX_sw_config_SHIFT (25U)
57870/*! sw_config - output and input configuration
57871 * 0b01..OPEN_DRAIN
57872 * 0b10..OPEN_DRAIN_INPUT
57873 * 0b11..INOUT
57874 * 0b00..DEFAULT
57875 */
57876#define IOMUXD_SPDIF0_TX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_sw_config_SHIFT)) & IOMUXD_SPDIF0_TX_sw_config_MASK)
57877#define IOMUXD_SPDIF0_TX_mux_mode_MASK (0x38000000U)
57878#define IOMUXD_SPDIF0_TX_mux_mode_SHIFT (27U)
57879/*! mux_mode - mux_mode
57880 * 0b000..ADMA.SPDIF0.TX
57881 * 0b001..ADMA.MQS.L
57882 * 0b010..ADMA.LCDIF.D11
57883 * 0b011..CONN.ENET1.RGMII_RX_CTL
57884 * 0b100..LSIO.GPIO0.IO11
57885 */
57886#define IOMUXD_SPDIF0_TX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_mux_mode_SHIFT)) & IOMUXD_SPDIF0_TX_mux_mode_MASK)
57887#define IOMUXD_SPDIF0_TX_update_pad_ctl_MASK (0x40000000U)
57888#define IOMUXD_SPDIF0_TX_update_pad_ctl_SHIFT (30U)
57889/*! update_pad_ctl - update lock for pad control
57890 */
57891#define IOMUXD_SPDIF0_TX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_update_pad_ctl_SHIFT)) & IOMUXD_SPDIF0_TX_update_pad_ctl_MASK)
57892#define IOMUXD_SPDIF0_TX_update_mux_mode_MASK (0x80000000U)
57893#define IOMUXD_SPDIF0_TX_update_mux_mode_SHIFT (31U)
57894/*! update_mux_mode - update lock for mux control
57895 */
57896#define IOMUXD_SPDIF0_TX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_TX_update_mux_mode_SHIFT)) & IOMUXD_SPDIF0_TX_update_mux_mode_MASK)
57897/*! @} */
57898
57899/*! @name IOMUXD_GROUP_1_3 - na */
57900/*! @{ */
57901#define IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDIO_MASK (0x1U)
57902#define IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDIO_SHIFT (0U)
57903/*! ENET0_MDIO - wakeup from ENET0_MDIO
57904 */
57905#define IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDIO(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDIO_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDIO_MASK)
57906#define IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDC_MASK (0x2U)
57907#define IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDC_SHIFT (1U)
57908/*! ENET0_MDC - wakeup from ENET0_MDC
57909 */
57910#define IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDC_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ENET0_MDC_MASK)
57911#define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_2_2_MASK (0x4U)
57912#define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_2_2_SHIFT (2U)
57913/*! iomuxd_group_1_3_reserved_2_2 - reserved
57914 */
57915#define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_2_2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_2_2_MASK)
57916#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FSR_MASK (0x8U)
57917#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FSR_SHIFT (3U)
57918/*! ESAI0_FSR - wakeup from ESAI0_FSR
57919 */
57920#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FSR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FSR_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FSR_MASK)
57921#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FST_MASK (0x10U)
57922#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FST_SHIFT (4U)
57923/*! ESAI0_FST - wakeup from ESAI0_FST
57924 */
57925#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FST_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_FST_MASK)
57926#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKR_MASK (0x20U)
57927#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKR_SHIFT (5U)
57928/*! ESAI0_SCKR - wakeup from ESAI0_SCKR
57929 */
57930#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKR_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKR_MASK)
57931#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKT_MASK (0x40U)
57932#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKT_SHIFT (6U)
57933/*! ESAI0_SCKT - wakeup from ESAI0_SCKT
57934 */
57935#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKT_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_SCKT_MASK)
57936#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX0_MASK (0x80U)
57937#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX0_SHIFT (7U)
57938/*! ESAI0_TX0 - wakeup from ESAI0_TX0
57939 */
57940#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX0_MASK)
57941#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX1_MASK (0x100U)
57942#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX1_SHIFT (8U)
57943/*! ESAI0_TX1 - wakeup from ESAI0_TX1
57944 */
57945#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX1_MASK)
57946#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX2_RX3_MASK (0x200U)
57947#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX2_RX3_SHIFT (9U)
57948/*! ESAI0_TX2_RX3 - wakeup from ESAI0_TX2_RX3
57949 */
57950#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX2_RX3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX2_RX3_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX2_RX3_MASK)
57951#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX3_RX2_MASK (0x400U)
57952#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX3_RX2_SHIFT (10U)
57953/*! ESAI0_TX3_RX2 - wakeup from ESAI0_TX3_RX2
57954 */
57955#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX3_RX2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX3_RX2_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX3_RX2_MASK)
57956#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX4_RX1_MASK (0x800U)
57957#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX4_RX1_SHIFT (11U)
57958/*! ESAI0_TX4_RX1 - wakeup from ESAI0_TX4_RX1
57959 */
57960#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX4_RX1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX4_RX1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX4_RX1_MASK)
57961#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX5_RX0_MASK (0x1000U)
57962#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX5_RX0_SHIFT (12U)
57963/*! ESAI0_TX5_RX0 - wakeup from ESAI0_TX5_RX0
57964 */
57965#define IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX5_RX0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX5_RX0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_ESAI0_TX5_RX0_MASK)
57966#define IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_RX_MASK (0x2000U)
57967#define IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_RX_SHIFT (13U)
57968/*! SPDIF0_RX - wakeup from SPDIF0_RX
57969 */
57970#define IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_RX_MASK)
57971#define IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_TX_MASK (0x4000U)
57972#define IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_TX_SHIFT (14U)
57973/*! SPDIF0_TX - wakeup from SPDIF0_TX
57974 */
57975#define IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_TX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_SPDIF0_TX_MASK)
57976#define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_15_31_MASK (0xFFFF8000U)
57977#define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_15_31_SHIFT (15U)
57978/*! iomuxd_group_1_3_reserved_15_31 - reserved
57979 */
57980#define IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_3_iomuxd_group_1_3_reserved_15_31_MASK)
57981/*! @} */
57982
57983/*! @name SPDIF0_EXT_CLK - SPDIF0_EXT_CLK */
57984/*! @{ */
57985#define IOMUXD_SPDIF0_EXT_CLK_PDRV_MASK (0x1U)
57986#define IOMUXD_SPDIF0_EXT_CLK_PDRV_SHIFT (0U)
57987/*! PDRV - Drive
57988 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
57989 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
57990 */
57991#define IOMUXD_SPDIF0_EXT_CLK_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_PDRV_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_PDRV_MASK)
57992#define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_1_4_MASK (0x1EU)
57993#define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_1_4_SHIFT (1U)
57994/*! SPDIF0_EXT_CLK_reserved_1_4 - reserved
57995 */
57996#define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_1_4_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_1_4_MASK)
57997#define IOMUXD_SPDIF0_EXT_CLK_PULL_MASK (0x60U)
57998#define IOMUXD_SPDIF0_EXT_CLK_PULL_SHIFT (5U)
57999/*! PULL - Pull Down Pull Up
58000 * 0b10..pull down
58001 * 0b01..pull up
58002 * 0b00..Prohibited
58003 * 0b11..pull disabled
58004 */
58005#define IOMUXD_SPDIF0_EXT_CLK_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_PULL_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_PULL_MASK)
58006#define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_7_18_MASK (0x7FF80U)
58007#define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_7_18_SHIFT (7U)
58008/*! SPDIF0_EXT_CLK_reserved_7_18 - reserved
58009 */
58010#define IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_7_18_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_SPDIF0_EXT_CLK_reserved_7_18_MASK)
58011#define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_CTRL_MASK (0x380000U)
58012#define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_CTRL_SHIFT (19U)
58013/*! WAKEUP_CTRL - wakeup control
58014 * 0b000..OFF
58015 * 0b001..RESAMPLE
58016 * 0b100..LOW
58017 * 0b111..HIGH
58018 * 0b110..RISE
58019 * 0b101..FALL
58020 */
58021#define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_WAKEUP_CTRL_MASK)
58022#define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_MASK_MASK (0x400000U)
58023#define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_MASK_SHIFT (22U)
58024/*! WAKEUP_MASK - wakeup mask
58025 */
58026#define IOMUXD_SPDIF0_EXT_CLK_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_WAKEUP_MASK_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_WAKEUP_MASK_MASK)
58027#define IOMUXD_SPDIF0_EXT_CLK_lp_config_MASK (0x1800000U)
58028#define IOMUXD_SPDIF0_EXT_CLK_lp_config_SHIFT (23U)
58029/*! lp_config - lower power configuration
58030 * 0b01..EARLY_ISO
58031 * 0b10..LATE_ISO
58032 * 0b11..LATCH
58033 * 0b00..PASS
58034 */
58035#define IOMUXD_SPDIF0_EXT_CLK_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_lp_config_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_lp_config_MASK)
58036#define IOMUXD_SPDIF0_EXT_CLK_sw_config_MASK (0x6000000U)
58037#define IOMUXD_SPDIF0_EXT_CLK_sw_config_SHIFT (25U)
58038/*! sw_config - output and input configuration
58039 * 0b01..OPEN_DRAIN
58040 * 0b10..OPEN_DRAIN_INPUT
58041 * 0b11..INOUT
58042 * 0b00..DEFAULT
58043 */
58044#define IOMUXD_SPDIF0_EXT_CLK_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_sw_config_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_sw_config_MASK)
58045#define IOMUXD_SPDIF0_EXT_CLK_mux_mode_MASK (0x38000000U)
58046#define IOMUXD_SPDIF0_EXT_CLK_mux_mode_SHIFT (27U)
58047/*! mux_mode - mux_mode
58048 * 0b000..ADMA.SPDIF0.EXT_CLK
58049 * 0b010..ADMA.LCDIF.D12
58050 * 0b011..CONN.ENET1.REFCLK_125M_25M
58051 * 0b100..LSIO.GPIO0.IO12
58052 */
58053#define IOMUXD_SPDIF0_EXT_CLK_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_mux_mode_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_mux_mode_MASK)
58054#define IOMUXD_SPDIF0_EXT_CLK_update_pad_ctl_MASK (0x40000000U)
58055#define IOMUXD_SPDIF0_EXT_CLK_update_pad_ctl_SHIFT (30U)
58056/*! update_pad_ctl - update lock for pad control
58057 */
58058#define IOMUXD_SPDIF0_EXT_CLK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_update_pad_ctl_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_update_pad_ctl_MASK)
58059#define IOMUXD_SPDIF0_EXT_CLK_update_mux_mode_MASK (0x80000000U)
58060#define IOMUXD_SPDIF0_EXT_CLK_update_mux_mode_SHIFT (31U)
58061/*! update_mux_mode - update lock for mux control
58062 */
58063#define IOMUXD_SPDIF0_EXT_CLK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPDIF0_EXT_CLK_update_mux_mode_SHIFT)) & IOMUXD_SPDIF0_EXT_CLK_update_mux_mode_MASK)
58064/*! @} */
58065
58066/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB */
58067/*! @{ */
58068#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMP_MASK (0x7U)
58069#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMP_SHIFT (0U)
58070/*! COMP - COMP
58071 * 0b010..Fixed code mode
58072 * 0b100..High impedance mode
58073 * 0b110..Read mode
58074 * 0b000..Normal Mode
58075 * 0b001..Freeze Mode
58076 */
58077#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMP_MASK)
58078#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_FASTFRZ_EN_MASK (0x8U)
58079#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_FASTFRZ_EN_SHIFT (3U)
58080/*! FASTFRZ_EN - FASTFRZ_EN
58081 * 0b1..FASTFRZ signal is driven by output of subsystem
58082 * 0b0..FASTFRZ signal is gated to 0
58083 */
58084#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_FASTFRZ_EN_MASK)
58085#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PSW_OVR_MASK (0x10U)
58086#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PSW_OVR_SHIFT (4U)
58087/*! PSW_OVR - PSW_OVR
58088 * 0b1..override output of voltage detector when using 2.5V IO operation
58089 * 0b0..selection coming from voltage detector cell for 1.8V or 3.3V IO operation
58090 */
58091#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PSW_OVR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PSW_OVR_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PSW_OVR_MASK)
58092#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCP_MASK (0x1E0U)
58093#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCP_SHIFT (5U)
58094/*! RASRCP - RASRCP
58095 * 0b0101..Reset Value
58096 */
58097#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCP_MASK)
58098#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCN_MASK (0x1E00U)
58099#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCN_SHIFT (9U)
58100/*! RASRCN - RASRCN
58101 * 0b1010..Reset Value
58102 */
58103#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_RASRCN_MASK)
58104#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SELECT_NASRC_MASK (0x2000U)
58105#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SELECT_NASRC_SHIFT (13U)
58106/*! SELECT_NASRC - SELECT_NASRC
58107 * 0b1..NASRCN value
58108 * 0b0..NASRCP value
58109 */
58110#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SELECT_NASRC_MASK)
58111#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMPOK_MASK (0x4000U)
58112#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMPOK_SHIFT (14U)
58113/*! COMPOK - COMPOK
58114 * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
58115 * 0b1..compensation cell in Normal mode and tracking PVT
58116 */
58117#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_COMPOK_MASK)
58118#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_READ_NASRC_MASK (0x78000U)
58119#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_READ_NASRC_SHIFT (15U)
58120/*! READ_NASRC - READ_NASRC
58121 * 0b0000..READ Only
58122 */
58123#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_READ_NASRC_MASK)
58124#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22_MASK (0x780000U)
58125#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22_SHIFT (19U)
58126/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22 - reserved
58127 */
58128#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_19_22_MASK)
58129#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SLEEP_MASK (0x1800000U)
58130#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SLEEP_SHIFT (23U)
58131/*! SLEEP - SLEEP
58132 * 0b11..LAST
58133 * 0b00..NO
58134 * 0b01..EARLY
58135 * 0b10..LATE
58136 */
58137#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_SLEEP_MASK)
58138#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29_MASK (0x3E000000U)
58139#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29_SHIFT (25U)
58140/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29 - reserved
58141 */
58142#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_reserved_25_29_MASK)
58143#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_pad_ctl_MASK (0x40000000U)
58144#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_pad_ctl_SHIFT (30U)
58145/*! update_pad_ctl - update lock for pad control
58146 */
58147#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_pad_ctl_MASK)
58148#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_mux_mode_MASK (0x80000000U)
58149#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_mux_mode_SHIFT (31U)
58150/*! update_mux_mode - update lock for mux control
58151 */
58152#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHB_update_mux_mode_MASK)
58153/*! @} */
58154
58155/*! @name SPI3_SCK - SPI3_SCK */
58156/*! @{ */
58157#define IOMUXD_SPI3_SCK_PDRV_MASK (0x1U)
58158#define IOMUXD_SPI3_SCK_PDRV_SHIFT (0U)
58159/*! PDRV - Drive
58160 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58161 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58162 */
58163#define IOMUXD_SPI3_SCK_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_PDRV_SHIFT)) & IOMUXD_SPI3_SCK_PDRV_MASK)
58164#define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_1_4_MASK (0x1EU)
58165#define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_1_4_SHIFT (1U)
58166/*! SPI3_SCK_reserved_1_4 - reserved
58167 */
58168#define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_SPI3_SCK_reserved_1_4_SHIFT)) & IOMUXD_SPI3_SCK_SPI3_SCK_reserved_1_4_MASK)
58169#define IOMUXD_SPI3_SCK_PULL_MASK (0x60U)
58170#define IOMUXD_SPI3_SCK_PULL_SHIFT (5U)
58171/*! PULL - Pull Down Pull Up
58172 * 0b10..pull down
58173 * 0b01..pull up
58174 * 0b00..Prohibited
58175 * 0b11..pull disabled
58176 */
58177#define IOMUXD_SPI3_SCK_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_PULL_SHIFT)) & IOMUXD_SPI3_SCK_PULL_MASK)
58178#define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_7_18_MASK (0x7FF80U)
58179#define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_7_18_SHIFT (7U)
58180/*! SPI3_SCK_reserved_7_18 - reserved
58181 */
58182#define IOMUXD_SPI3_SCK_SPI3_SCK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_SPI3_SCK_reserved_7_18_SHIFT)) & IOMUXD_SPI3_SCK_SPI3_SCK_reserved_7_18_MASK)
58183#define IOMUXD_SPI3_SCK_WAKEUP_CTRL_MASK (0x380000U)
58184#define IOMUXD_SPI3_SCK_WAKEUP_CTRL_SHIFT (19U)
58185/*! WAKEUP_CTRL - wakeup control
58186 * 0b000..OFF
58187 * 0b001..RESAMPLE
58188 * 0b100..LOW
58189 * 0b111..HIGH
58190 * 0b110..RISE
58191 * 0b101..FALL
58192 */
58193#define IOMUXD_SPI3_SCK_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI3_SCK_WAKEUP_CTRL_MASK)
58194#define IOMUXD_SPI3_SCK_WAKEUP_MASK_MASK (0x400000U)
58195#define IOMUXD_SPI3_SCK_WAKEUP_MASK_SHIFT (22U)
58196/*! WAKEUP_MASK - wakeup mask
58197 */
58198#define IOMUXD_SPI3_SCK_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI3_SCK_WAKEUP_MASK_MASK)
58199#define IOMUXD_SPI3_SCK_lp_config_MASK (0x1800000U)
58200#define IOMUXD_SPI3_SCK_lp_config_SHIFT (23U)
58201/*! lp_config - lower power configuration
58202 * 0b01..EARLY_ISO
58203 * 0b10..LATE_ISO
58204 * 0b11..LATCH
58205 * 0b00..PASS
58206 */
58207#define IOMUXD_SPI3_SCK_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_lp_config_SHIFT)) & IOMUXD_SPI3_SCK_lp_config_MASK)
58208#define IOMUXD_SPI3_SCK_sw_config_MASK (0x6000000U)
58209#define IOMUXD_SPI3_SCK_sw_config_SHIFT (25U)
58210/*! sw_config - output and input configuration
58211 * 0b01..OPEN_DRAIN
58212 * 0b10..OPEN_DRAIN_INPUT
58213 * 0b11..INOUT
58214 * 0b00..DEFAULT
58215 */
58216#define IOMUXD_SPI3_SCK_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_sw_config_SHIFT)) & IOMUXD_SPI3_SCK_sw_config_MASK)
58217#define IOMUXD_SPI3_SCK_mux_mode_MASK (0x38000000U)
58218#define IOMUXD_SPI3_SCK_mux_mode_SHIFT (27U)
58219/*! mux_mode - mux_mode
58220 * 0b000..ADMA.SPI3.SCK
58221 * 0b010..ADMA.LCDIF.D13
58222 * 0b100..LSIO.GPIO0.IO13
58223 */
58224#define IOMUXD_SPI3_SCK_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_mux_mode_SHIFT)) & IOMUXD_SPI3_SCK_mux_mode_MASK)
58225#define IOMUXD_SPI3_SCK_update_pad_ctl_MASK (0x40000000U)
58226#define IOMUXD_SPI3_SCK_update_pad_ctl_SHIFT (30U)
58227/*! update_pad_ctl - update lock for pad control
58228 */
58229#define IOMUXD_SPI3_SCK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_update_pad_ctl_SHIFT)) & IOMUXD_SPI3_SCK_update_pad_ctl_MASK)
58230#define IOMUXD_SPI3_SCK_update_mux_mode_MASK (0x80000000U)
58231#define IOMUXD_SPI3_SCK_update_mux_mode_SHIFT (31U)
58232/*! update_mux_mode - update lock for mux control
58233 */
58234#define IOMUXD_SPI3_SCK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SCK_update_mux_mode_SHIFT)) & IOMUXD_SPI3_SCK_update_mux_mode_MASK)
58235/*! @} */
58236
58237/*! @name SPI3_SDO - SPI3_SDO */
58238/*! @{ */
58239#define IOMUXD_SPI3_SDO_PDRV_MASK (0x1U)
58240#define IOMUXD_SPI3_SDO_PDRV_SHIFT (0U)
58241/*! PDRV - Drive
58242 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58243 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58244 */
58245#define IOMUXD_SPI3_SDO_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_PDRV_SHIFT)) & IOMUXD_SPI3_SDO_PDRV_MASK)
58246#define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_1_4_MASK (0x1EU)
58247#define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_1_4_SHIFT (1U)
58248/*! SPI3_SDO_reserved_1_4 - reserved
58249 */
58250#define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_SPI3_SDO_reserved_1_4_SHIFT)) & IOMUXD_SPI3_SDO_SPI3_SDO_reserved_1_4_MASK)
58251#define IOMUXD_SPI3_SDO_PULL_MASK (0x60U)
58252#define IOMUXD_SPI3_SDO_PULL_SHIFT (5U)
58253/*! PULL - Pull Down Pull Up
58254 * 0b10..pull down
58255 * 0b01..pull up
58256 * 0b00..Prohibited
58257 * 0b11..pull disabled
58258 */
58259#define IOMUXD_SPI3_SDO_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_PULL_SHIFT)) & IOMUXD_SPI3_SDO_PULL_MASK)
58260#define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_7_18_MASK (0x7FF80U)
58261#define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_7_18_SHIFT (7U)
58262/*! SPI3_SDO_reserved_7_18 - reserved
58263 */
58264#define IOMUXD_SPI3_SDO_SPI3_SDO_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_SPI3_SDO_reserved_7_18_SHIFT)) & IOMUXD_SPI3_SDO_SPI3_SDO_reserved_7_18_MASK)
58265#define IOMUXD_SPI3_SDO_WAKEUP_CTRL_MASK (0x380000U)
58266#define IOMUXD_SPI3_SDO_WAKEUP_CTRL_SHIFT (19U)
58267/*! WAKEUP_CTRL - wakeup control
58268 * 0b000..OFF
58269 * 0b001..RESAMPLE
58270 * 0b100..LOW
58271 * 0b111..HIGH
58272 * 0b110..RISE
58273 * 0b101..FALL
58274 */
58275#define IOMUXD_SPI3_SDO_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI3_SDO_WAKEUP_CTRL_MASK)
58276#define IOMUXD_SPI3_SDO_WAKEUP_MASK_MASK (0x400000U)
58277#define IOMUXD_SPI3_SDO_WAKEUP_MASK_SHIFT (22U)
58278/*! WAKEUP_MASK - wakeup mask
58279 */
58280#define IOMUXD_SPI3_SDO_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI3_SDO_WAKEUP_MASK_MASK)
58281#define IOMUXD_SPI3_SDO_lp_config_MASK (0x1800000U)
58282#define IOMUXD_SPI3_SDO_lp_config_SHIFT (23U)
58283/*! lp_config - lower power configuration
58284 * 0b01..EARLY_ISO
58285 * 0b10..LATE_ISO
58286 * 0b11..LATCH
58287 * 0b00..PASS
58288 */
58289#define IOMUXD_SPI3_SDO_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_lp_config_SHIFT)) & IOMUXD_SPI3_SDO_lp_config_MASK)
58290#define IOMUXD_SPI3_SDO_sw_config_MASK (0x6000000U)
58291#define IOMUXD_SPI3_SDO_sw_config_SHIFT (25U)
58292/*! sw_config - output and input configuration
58293 * 0b01..OPEN_DRAIN
58294 * 0b10..OPEN_DRAIN_INPUT
58295 * 0b11..INOUT
58296 * 0b00..DEFAULT
58297 */
58298#define IOMUXD_SPI3_SDO_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_sw_config_SHIFT)) & IOMUXD_SPI3_SDO_sw_config_MASK)
58299#define IOMUXD_SPI3_SDO_mux_mode_MASK (0x38000000U)
58300#define IOMUXD_SPI3_SDO_mux_mode_SHIFT (27U)
58301/*! mux_mode - mux_mode
58302 * 0b000..ADMA.SPI3.SDO
58303 * 0b010..ADMA.LCDIF.D14
58304 * 0b100..LSIO.GPIO0.IO14
58305 */
58306#define IOMUXD_SPI3_SDO_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_mux_mode_SHIFT)) & IOMUXD_SPI3_SDO_mux_mode_MASK)
58307#define IOMUXD_SPI3_SDO_update_pad_ctl_MASK (0x40000000U)
58308#define IOMUXD_SPI3_SDO_update_pad_ctl_SHIFT (30U)
58309/*! update_pad_ctl - update lock for pad control
58310 */
58311#define IOMUXD_SPI3_SDO_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_update_pad_ctl_SHIFT)) & IOMUXD_SPI3_SDO_update_pad_ctl_MASK)
58312#define IOMUXD_SPI3_SDO_update_mux_mode_MASK (0x80000000U)
58313#define IOMUXD_SPI3_SDO_update_mux_mode_SHIFT (31U)
58314/*! update_mux_mode - update lock for mux control
58315 */
58316#define IOMUXD_SPI3_SDO_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDO_update_mux_mode_SHIFT)) & IOMUXD_SPI3_SDO_update_mux_mode_MASK)
58317/*! @} */
58318
58319/*! @name SPI3_SDI - SPI3_SDI */
58320/*! @{ */
58321#define IOMUXD_SPI3_SDI_PDRV_MASK (0x1U)
58322#define IOMUXD_SPI3_SDI_PDRV_SHIFT (0U)
58323/*! PDRV - Drive
58324 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58325 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58326 */
58327#define IOMUXD_SPI3_SDI_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_PDRV_SHIFT)) & IOMUXD_SPI3_SDI_PDRV_MASK)
58328#define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_1_4_MASK (0x1EU)
58329#define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_1_4_SHIFT (1U)
58330/*! SPI3_SDI_reserved_1_4 - reserved
58331 */
58332#define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_SPI3_SDI_reserved_1_4_SHIFT)) & IOMUXD_SPI3_SDI_SPI3_SDI_reserved_1_4_MASK)
58333#define IOMUXD_SPI3_SDI_PULL_MASK (0x60U)
58334#define IOMUXD_SPI3_SDI_PULL_SHIFT (5U)
58335/*! PULL - Pull Down Pull Up
58336 * 0b10..pull down
58337 * 0b01..pull up
58338 * 0b00..Prohibited
58339 * 0b11..pull disabled
58340 */
58341#define IOMUXD_SPI3_SDI_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_PULL_SHIFT)) & IOMUXD_SPI3_SDI_PULL_MASK)
58342#define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_7_18_MASK (0x7FF80U)
58343#define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_7_18_SHIFT (7U)
58344/*! SPI3_SDI_reserved_7_18 - reserved
58345 */
58346#define IOMUXD_SPI3_SDI_SPI3_SDI_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_SPI3_SDI_reserved_7_18_SHIFT)) & IOMUXD_SPI3_SDI_SPI3_SDI_reserved_7_18_MASK)
58347#define IOMUXD_SPI3_SDI_WAKEUP_CTRL_MASK (0x380000U)
58348#define IOMUXD_SPI3_SDI_WAKEUP_CTRL_SHIFT (19U)
58349/*! WAKEUP_CTRL - wakeup control
58350 * 0b000..OFF
58351 * 0b001..RESAMPLE
58352 * 0b100..LOW
58353 * 0b111..HIGH
58354 * 0b110..RISE
58355 * 0b101..FALL
58356 */
58357#define IOMUXD_SPI3_SDI_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI3_SDI_WAKEUP_CTRL_MASK)
58358#define IOMUXD_SPI3_SDI_WAKEUP_MASK_MASK (0x400000U)
58359#define IOMUXD_SPI3_SDI_WAKEUP_MASK_SHIFT (22U)
58360/*! WAKEUP_MASK - wakeup mask
58361 */
58362#define IOMUXD_SPI3_SDI_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI3_SDI_WAKEUP_MASK_MASK)
58363#define IOMUXD_SPI3_SDI_lp_config_MASK (0x1800000U)
58364#define IOMUXD_SPI3_SDI_lp_config_SHIFT (23U)
58365/*! lp_config - lower power configuration
58366 * 0b01..EARLY_ISO
58367 * 0b10..LATE_ISO
58368 * 0b11..LATCH
58369 * 0b00..PASS
58370 */
58371#define IOMUXD_SPI3_SDI_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_lp_config_SHIFT)) & IOMUXD_SPI3_SDI_lp_config_MASK)
58372#define IOMUXD_SPI3_SDI_sw_config_MASK (0x6000000U)
58373#define IOMUXD_SPI3_SDI_sw_config_SHIFT (25U)
58374/*! sw_config - output and input configuration
58375 * 0b01..OPEN_DRAIN
58376 * 0b10..OPEN_DRAIN_INPUT
58377 * 0b11..INOUT
58378 * 0b00..DEFAULT
58379 */
58380#define IOMUXD_SPI3_SDI_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_sw_config_SHIFT)) & IOMUXD_SPI3_SDI_sw_config_MASK)
58381#define IOMUXD_SPI3_SDI_mux_mode_MASK (0x38000000U)
58382#define IOMUXD_SPI3_SDI_mux_mode_SHIFT (27U)
58383/*! mux_mode - mux_mode
58384 * 0b000..ADMA.SPI3.SDI
58385 * 0b010..ADMA.LCDIF.D15
58386 * 0b100..LSIO.GPIO0.IO15
58387 */
58388#define IOMUXD_SPI3_SDI_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_mux_mode_SHIFT)) & IOMUXD_SPI3_SDI_mux_mode_MASK)
58389#define IOMUXD_SPI3_SDI_update_pad_ctl_MASK (0x40000000U)
58390#define IOMUXD_SPI3_SDI_update_pad_ctl_SHIFT (30U)
58391/*! update_pad_ctl - update lock for pad control
58392 */
58393#define IOMUXD_SPI3_SDI_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_update_pad_ctl_SHIFT)) & IOMUXD_SPI3_SDI_update_pad_ctl_MASK)
58394#define IOMUXD_SPI3_SDI_update_mux_mode_MASK (0x80000000U)
58395#define IOMUXD_SPI3_SDI_update_mux_mode_SHIFT (31U)
58396/*! update_mux_mode - update lock for mux control
58397 */
58398#define IOMUXD_SPI3_SDI_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_SDI_update_mux_mode_SHIFT)) & IOMUXD_SPI3_SDI_update_mux_mode_MASK)
58399/*! @} */
58400
58401/*! @name SPI3_CS0 - SPI3_CS0 */
58402/*! @{ */
58403#define IOMUXD_SPI3_CS0_PDRV_MASK (0x1U)
58404#define IOMUXD_SPI3_CS0_PDRV_SHIFT (0U)
58405/*! PDRV - Drive
58406 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58407 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58408 */
58409#define IOMUXD_SPI3_CS0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_PDRV_SHIFT)) & IOMUXD_SPI3_CS0_PDRV_MASK)
58410#define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_1_4_MASK (0x1EU)
58411#define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_1_4_SHIFT (1U)
58412/*! SPI3_CS0_reserved_1_4 - reserved
58413 */
58414#define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_SPI3_CS0_reserved_1_4_SHIFT)) & IOMUXD_SPI3_CS0_SPI3_CS0_reserved_1_4_MASK)
58415#define IOMUXD_SPI3_CS0_PULL_MASK (0x60U)
58416#define IOMUXD_SPI3_CS0_PULL_SHIFT (5U)
58417/*! PULL - Pull Down Pull Up
58418 * 0b10..pull down
58419 * 0b01..pull up
58420 * 0b00..Prohibited
58421 * 0b11..pull disabled
58422 */
58423#define IOMUXD_SPI3_CS0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_PULL_SHIFT)) & IOMUXD_SPI3_CS0_PULL_MASK)
58424#define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_7_18_MASK (0x7FF80U)
58425#define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_7_18_SHIFT (7U)
58426/*! SPI3_CS0_reserved_7_18 - reserved
58427 */
58428#define IOMUXD_SPI3_CS0_SPI3_CS0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_SPI3_CS0_reserved_7_18_SHIFT)) & IOMUXD_SPI3_CS0_SPI3_CS0_reserved_7_18_MASK)
58429#define IOMUXD_SPI3_CS0_WAKEUP_CTRL_MASK (0x380000U)
58430#define IOMUXD_SPI3_CS0_WAKEUP_CTRL_SHIFT (19U)
58431/*! WAKEUP_CTRL - wakeup control
58432 * 0b000..OFF
58433 * 0b001..RESAMPLE
58434 * 0b100..LOW
58435 * 0b111..HIGH
58436 * 0b110..RISE
58437 * 0b101..FALL
58438 */
58439#define IOMUXD_SPI3_CS0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI3_CS0_WAKEUP_CTRL_MASK)
58440#define IOMUXD_SPI3_CS0_WAKEUP_MASK_MASK (0x400000U)
58441#define IOMUXD_SPI3_CS0_WAKEUP_MASK_SHIFT (22U)
58442/*! WAKEUP_MASK - wakeup mask
58443 */
58444#define IOMUXD_SPI3_CS0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI3_CS0_WAKEUP_MASK_MASK)
58445#define IOMUXD_SPI3_CS0_lp_config_MASK (0x1800000U)
58446#define IOMUXD_SPI3_CS0_lp_config_SHIFT (23U)
58447/*! lp_config - lower power configuration
58448 * 0b01..EARLY_ISO
58449 * 0b10..LATE_ISO
58450 * 0b11..LATCH
58451 * 0b00..PASS
58452 */
58453#define IOMUXD_SPI3_CS0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_lp_config_SHIFT)) & IOMUXD_SPI3_CS0_lp_config_MASK)
58454#define IOMUXD_SPI3_CS0_sw_config_MASK (0x6000000U)
58455#define IOMUXD_SPI3_CS0_sw_config_SHIFT (25U)
58456/*! sw_config - output and input configuration
58457 * 0b01..OPEN_DRAIN
58458 * 0b10..OPEN_DRAIN_INPUT
58459 * 0b11..INOUT
58460 * 0b00..DEFAULT
58461 */
58462#define IOMUXD_SPI3_CS0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_sw_config_SHIFT)) & IOMUXD_SPI3_CS0_sw_config_MASK)
58463#define IOMUXD_SPI3_CS0_mux_mode_MASK (0x38000000U)
58464#define IOMUXD_SPI3_CS0_mux_mode_SHIFT (27U)
58465/*! mux_mode - mux_mode
58466 * 0b000..ADMA.SPI3.CS0
58467 * 0b001..ADMA.ACM.MCLK_OUT1
58468 * 0b010..ADMA.LCDIF.HSYNC
58469 * 0b100..LSIO.GPIO0.IO16
58470 */
58471#define IOMUXD_SPI3_CS0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_mux_mode_SHIFT)) & IOMUXD_SPI3_CS0_mux_mode_MASK)
58472#define IOMUXD_SPI3_CS0_update_pad_ctl_MASK (0x40000000U)
58473#define IOMUXD_SPI3_CS0_update_pad_ctl_SHIFT (30U)
58474/*! update_pad_ctl - update lock for pad control
58475 */
58476#define IOMUXD_SPI3_CS0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_update_pad_ctl_SHIFT)) & IOMUXD_SPI3_CS0_update_pad_ctl_MASK)
58477#define IOMUXD_SPI3_CS0_update_mux_mode_MASK (0x80000000U)
58478#define IOMUXD_SPI3_CS0_update_mux_mode_SHIFT (31U)
58479/*! update_mux_mode - update lock for mux control
58480 */
58481#define IOMUXD_SPI3_CS0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS0_update_mux_mode_SHIFT)) & IOMUXD_SPI3_CS0_update_mux_mode_MASK)
58482/*! @} */
58483
58484/*! @name SPI3_CS1 - SPI3_CS1 */
58485/*! @{ */
58486#define IOMUXD_SPI3_CS1_PDRV_MASK (0x1U)
58487#define IOMUXD_SPI3_CS1_PDRV_SHIFT (0U)
58488/*! PDRV - Drive
58489 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58490 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58491 */
58492#define IOMUXD_SPI3_CS1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_PDRV_SHIFT)) & IOMUXD_SPI3_CS1_PDRV_MASK)
58493#define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_1_4_MASK (0x1EU)
58494#define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_1_4_SHIFT (1U)
58495/*! SPI3_CS1_reserved_1_4 - reserved
58496 */
58497#define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_SPI3_CS1_reserved_1_4_SHIFT)) & IOMUXD_SPI3_CS1_SPI3_CS1_reserved_1_4_MASK)
58498#define IOMUXD_SPI3_CS1_PULL_MASK (0x60U)
58499#define IOMUXD_SPI3_CS1_PULL_SHIFT (5U)
58500/*! PULL - Pull Down Pull Up
58501 * 0b10..pull down
58502 * 0b01..pull up
58503 * 0b00..Prohibited
58504 * 0b11..pull disabled
58505 */
58506#define IOMUXD_SPI3_CS1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_PULL_SHIFT)) & IOMUXD_SPI3_CS1_PULL_MASK)
58507#define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_7_18_MASK (0x7FF80U)
58508#define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_7_18_SHIFT (7U)
58509/*! SPI3_CS1_reserved_7_18 - reserved
58510 */
58511#define IOMUXD_SPI3_CS1_SPI3_CS1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_SPI3_CS1_reserved_7_18_SHIFT)) & IOMUXD_SPI3_CS1_SPI3_CS1_reserved_7_18_MASK)
58512#define IOMUXD_SPI3_CS1_WAKEUP_CTRL_MASK (0x380000U)
58513#define IOMUXD_SPI3_CS1_WAKEUP_CTRL_SHIFT (19U)
58514/*! WAKEUP_CTRL - wakeup control
58515 * 0b000..OFF
58516 * 0b001..RESAMPLE
58517 * 0b100..LOW
58518 * 0b111..HIGH
58519 * 0b110..RISE
58520 * 0b101..FALL
58521 */
58522#define IOMUXD_SPI3_CS1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI3_CS1_WAKEUP_CTRL_MASK)
58523#define IOMUXD_SPI3_CS1_WAKEUP_MASK_MASK (0x400000U)
58524#define IOMUXD_SPI3_CS1_WAKEUP_MASK_SHIFT (22U)
58525/*! WAKEUP_MASK - wakeup mask
58526 */
58527#define IOMUXD_SPI3_CS1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI3_CS1_WAKEUP_MASK_MASK)
58528#define IOMUXD_SPI3_CS1_lp_config_MASK (0x1800000U)
58529#define IOMUXD_SPI3_CS1_lp_config_SHIFT (23U)
58530/*! lp_config - lower power configuration
58531 * 0b01..EARLY_ISO
58532 * 0b10..LATE_ISO
58533 * 0b11..LATCH
58534 * 0b00..PASS
58535 */
58536#define IOMUXD_SPI3_CS1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_lp_config_SHIFT)) & IOMUXD_SPI3_CS1_lp_config_MASK)
58537#define IOMUXD_SPI3_CS1_sw_config_MASK (0x6000000U)
58538#define IOMUXD_SPI3_CS1_sw_config_SHIFT (25U)
58539/*! sw_config - output and input configuration
58540 * 0b01..OPEN_DRAIN
58541 * 0b10..OPEN_DRAIN_INPUT
58542 * 0b11..INOUT
58543 * 0b00..DEFAULT
58544 */
58545#define IOMUXD_SPI3_CS1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_sw_config_SHIFT)) & IOMUXD_SPI3_CS1_sw_config_MASK)
58546#define IOMUXD_SPI3_CS1_mux_mode_MASK (0x38000000U)
58547#define IOMUXD_SPI3_CS1_mux_mode_SHIFT (27U)
58548/*! mux_mode - mux_mode
58549 * 0b000..ADMA.SPI3.CS1
58550 * 0b001..ADMA.I2C3.SCL
58551 * 0b010..ADMA.LCDIF.RESET
58552 * 0b011..ADMA.SPI2.CS0
58553 * 0b100..ADMA.LCDIF.D16
58554 */
58555#define IOMUXD_SPI3_CS1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_mux_mode_SHIFT)) & IOMUXD_SPI3_CS1_mux_mode_MASK)
58556#define IOMUXD_SPI3_CS1_update_pad_ctl_MASK (0x40000000U)
58557#define IOMUXD_SPI3_CS1_update_pad_ctl_SHIFT (30U)
58558/*! update_pad_ctl - update lock for pad control
58559 */
58560#define IOMUXD_SPI3_CS1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_update_pad_ctl_SHIFT)) & IOMUXD_SPI3_CS1_update_pad_ctl_MASK)
58561#define IOMUXD_SPI3_CS1_update_mux_mode_MASK (0x80000000U)
58562#define IOMUXD_SPI3_CS1_update_mux_mode_SHIFT (31U)
58563/*! update_mux_mode - update lock for mux control
58564 */
58565#define IOMUXD_SPI3_CS1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI3_CS1_update_mux_mode_SHIFT)) & IOMUXD_SPI3_CS1_update_mux_mode_MASK)
58566/*! @} */
58567
58568/*! @name MCLK_IN1 - MCLK_IN1 */
58569/*! @{ */
58570#define IOMUXD_MCLK_IN1_PDRV_MASK (0x1U)
58571#define IOMUXD_MCLK_IN1_PDRV_SHIFT (0U)
58572/*! PDRV - Drive
58573 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58574 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58575 */
58576#define IOMUXD_MCLK_IN1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_PDRV_SHIFT)) & IOMUXD_MCLK_IN1_PDRV_MASK)
58577#define IOMUXD_MCLK_IN1_MCLK_IN1_reserved_1_4_MASK (0x1EU)
58578#define IOMUXD_MCLK_IN1_MCLK_IN1_reserved_1_4_SHIFT (1U)
58579/*! MCLK_IN1_reserved_1_4 - reserved
58580 */
58581#define IOMUXD_MCLK_IN1_MCLK_IN1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_MCLK_IN1_reserved_1_4_SHIFT)) & IOMUXD_MCLK_IN1_MCLK_IN1_reserved_1_4_MASK)
58582#define IOMUXD_MCLK_IN1_PULL_MASK (0x60U)
58583#define IOMUXD_MCLK_IN1_PULL_SHIFT (5U)
58584/*! PULL - Pull Down Pull Up
58585 * 0b10..pull down
58586 * 0b01..pull up
58587 * 0b00..Prohibited
58588 * 0b11..pull disabled
58589 */
58590#define IOMUXD_MCLK_IN1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_PULL_SHIFT)) & IOMUXD_MCLK_IN1_PULL_MASK)
58591#define IOMUXD_MCLK_IN1_MCLK_IN1_reserved_7_18_MASK (0x7FF80U)
58592#define IOMUXD_MCLK_IN1_MCLK_IN1_reserved_7_18_SHIFT (7U)
58593/*! MCLK_IN1_reserved_7_18 - reserved
58594 */
58595#define IOMUXD_MCLK_IN1_MCLK_IN1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_MCLK_IN1_reserved_7_18_SHIFT)) & IOMUXD_MCLK_IN1_MCLK_IN1_reserved_7_18_MASK)
58596#define IOMUXD_MCLK_IN1_WAKEUP_CTRL_MASK (0x380000U)
58597#define IOMUXD_MCLK_IN1_WAKEUP_CTRL_SHIFT (19U)
58598/*! WAKEUP_CTRL - wakeup control
58599 * 0b000..OFF
58600 * 0b001..RESAMPLE
58601 * 0b100..LOW
58602 * 0b111..HIGH
58603 * 0b110..RISE
58604 * 0b101..FALL
58605 */
58606#define IOMUXD_MCLK_IN1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_WAKEUP_CTRL_SHIFT)) & IOMUXD_MCLK_IN1_WAKEUP_CTRL_MASK)
58607#define IOMUXD_MCLK_IN1_WAKEUP_MASK_MASK (0x400000U)
58608#define IOMUXD_MCLK_IN1_WAKEUP_MASK_SHIFT (22U)
58609/*! WAKEUP_MASK - wakeup mask
58610 */
58611#define IOMUXD_MCLK_IN1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_WAKEUP_MASK_SHIFT)) & IOMUXD_MCLK_IN1_WAKEUP_MASK_MASK)
58612#define IOMUXD_MCLK_IN1_lp_config_MASK (0x1800000U)
58613#define IOMUXD_MCLK_IN1_lp_config_SHIFT (23U)
58614/*! lp_config - lower power configuration
58615 * 0b01..EARLY_ISO
58616 * 0b10..LATE_ISO
58617 * 0b11..LATCH
58618 * 0b00..PASS
58619 */
58620#define IOMUXD_MCLK_IN1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_lp_config_SHIFT)) & IOMUXD_MCLK_IN1_lp_config_MASK)
58621#define IOMUXD_MCLK_IN1_sw_config_MASK (0x6000000U)
58622#define IOMUXD_MCLK_IN1_sw_config_SHIFT (25U)
58623/*! sw_config - output and input configuration
58624 * 0b01..OPEN_DRAIN
58625 * 0b10..OPEN_DRAIN_INPUT
58626 * 0b11..INOUT
58627 * 0b00..DEFAULT
58628 */
58629#define IOMUXD_MCLK_IN1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_sw_config_SHIFT)) & IOMUXD_MCLK_IN1_sw_config_MASK)
58630#define IOMUXD_MCLK_IN1_mux_mode_MASK (0x38000000U)
58631#define IOMUXD_MCLK_IN1_mux_mode_SHIFT (27U)
58632/*! mux_mode - mux_mode
58633 * 0b000..ADMA.ACM.MCLK_IN1
58634 * 0b001..ADMA.I2C3.SDA
58635 * 0b010..ADMA.LCDIF.EN
58636 * 0b011..ADMA.SPI2.SCK
58637 * 0b100..ADMA.LCDIF.D17
58638 */
58639#define IOMUXD_MCLK_IN1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_mux_mode_SHIFT)) & IOMUXD_MCLK_IN1_mux_mode_MASK)
58640#define IOMUXD_MCLK_IN1_update_pad_ctl_MASK (0x40000000U)
58641#define IOMUXD_MCLK_IN1_update_pad_ctl_SHIFT (30U)
58642/*! update_pad_ctl - update lock for pad control
58643 */
58644#define IOMUXD_MCLK_IN1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_update_pad_ctl_SHIFT)) & IOMUXD_MCLK_IN1_update_pad_ctl_MASK)
58645#define IOMUXD_MCLK_IN1_update_mux_mode_MASK (0x80000000U)
58646#define IOMUXD_MCLK_IN1_update_mux_mode_SHIFT (31U)
58647/*! update_mux_mode - update lock for mux control
58648 */
58649#define IOMUXD_MCLK_IN1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN1_update_mux_mode_SHIFT)) & IOMUXD_MCLK_IN1_update_mux_mode_MASK)
58650/*! @} */
58651
58652/*! @name MCLK_IN0 - MCLK_IN0 */
58653/*! @{ */
58654#define IOMUXD_MCLK_IN0_PDRV_MASK (0x1U)
58655#define IOMUXD_MCLK_IN0_PDRV_SHIFT (0U)
58656/*! PDRV - Drive
58657 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58658 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58659 */
58660#define IOMUXD_MCLK_IN0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_PDRV_SHIFT)) & IOMUXD_MCLK_IN0_PDRV_MASK)
58661#define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_1_4_MASK (0x1EU)
58662#define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_1_4_SHIFT (1U)
58663/*! MCLK_IN0_reserved_1_4 - reserved
58664 */
58665#define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_MCLK_IN0_reserved_1_4_SHIFT)) & IOMUXD_MCLK_IN0_MCLK_IN0_reserved_1_4_MASK)
58666#define IOMUXD_MCLK_IN0_PULL_MASK (0x60U)
58667#define IOMUXD_MCLK_IN0_PULL_SHIFT (5U)
58668/*! PULL - Pull Down Pull Up
58669 * 0b10..pull down
58670 * 0b01..pull up
58671 * 0b00..Prohibited
58672 * 0b11..pull disabled
58673 */
58674#define IOMUXD_MCLK_IN0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_PULL_SHIFT)) & IOMUXD_MCLK_IN0_PULL_MASK)
58675#define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_7_18_MASK (0x7FF80U)
58676#define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_7_18_SHIFT (7U)
58677/*! MCLK_IN0_reserved_7_18 - reserved
58678 */
58679#define IOMUXD_MCLK_IN0_MCLK_IN0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_MCLK_IN0_reserved_7_18_SHIFT)) & IOMUXD_MCLK_IN0_MCLK_IN0_reserved_7_18_MASK)
58680#define IOMUXD_MCLK_IN0_WAKEUP_CTRL_MASK (0x380000U)
58681#define IOMUXD_MCLK_IN0_WAKEUP_CTRL_SHIFT (19U)
58682/*! WAKEUP_CTRL - wakeup control
58683 * 0b000..OFF
58684 * 0b001..RESAMPLE
58685 * 0b100..LOW
58686 * 0b111..HIGH
58687 * 0b110..RISE
58688 * 0b101..FALL
58689 */
58690#define IOMUXD_MCLK_IN0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_WAKEUP_CTRL_SHIFT)) & IOMUXD_MCLK_IN0_WAKEUP_CTRL_MASK)
58691#define IOMUXD_MCLK_IN0_WAKEUP_MASK_MASK (0x400000U)
58692#define IOMUXD_MCLK_IN0_WAKEUP_MASK_SHIFT (22U)
58693/*! WAKEUP_MASK - wakeup mask
58694 */
58695#define IOMUXD_MCLK_IN0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_WAKEUP_MASK_SHIFT)) & IOMUXD_MCLK_IN0_WAKEUP_MASK_MASK)
58696#define IOMUXD_MCLK_IN0_lp_config_MASK (0x1800000U)
58697#define IOMUXD_MCLK_IN0_lp_config_SHIFT (23U)
58698/*! lp_config - lower power configuration
58699 * 0b01..EARLY_ISO
58700 * 0b10..LATE_ISO
58701 * 0b11..LATCH
58702 * 0b00..PASS
58703 */
58704#define IOMUXD_MCLK_IN0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_lp_config_SHIFT)) & IOMUXD_MCLK_IN0_lp_config_MASK)
58705#define IOMUXD_MCLK_IN0_sw_config_MASK (0x6000000U)
58706#define IOMUXD_MCLK_IN0_sw_config_SHIFT (25U)
58707/*! sw_config - output and input configuration
58708 * 0b01..OPEN_DRAIN
58709 * 0b10..OPEN_DRAIN_INPUT
58710 * 0b11..INOUT
58711 * 0b00..DEFAULT
58712 */
58713#define IOMUXD_MCLK_IN0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_sw_config_SHIFT)) & IOMUXD_MCLK_IN0_sw_config_MASK)
58714#define IOMUXD_MCLK_IN0_mux_mode_MASK (0x38000000U)
58715#define IOMUXD_MCLK_IN0_mux_mode_SHIFT (27U)
58716/*! mux_mode - mux_mode
58717 * 0b000..ADMA.ACM.MCLK_IN0
58718 * 0b001..ADMA.ESAI0.RX_HF_CLK
58719 * 0b010..ADMA.LCDIF.VSYNC
58720 * 0b011..ADMA.SPI2.SDI
58721 * 0b100..LSIO.GPIO0.IO19
58722 */
58723#define IOMUXD_MCLK_IN0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_mux_mode_SHIFT)) & IOMUXD_MCLK_IN0_mux_mode_MASK)
58724#define IOMUXD_MCLK_IN0_update_pad_ctl_MASK (0x40000000U)
58725#define IOMUXD_MCLK_IN0_update_pad_ctl_SHIFT (30U)
58726/*! update_pad_ctl - update lock for pad control
58727 */
58728#define IOMUXD_MCLK_IN0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_update_pad_ctl_SHIFT)) & IOMUXD_MCLK_IN0_update_pad_ctl_MASK)
58729#define IOMUXD_MCLK_IN0_update_mux_mode_MASK (0x80000000U)
58730#define IOMUXD_MCLK_IN0_update_mux_mode_SHIFT (31U)
58731/*! update_mux_mode - update lock for mux control
58732 */
58733#define IOMUXD_MCLK_IN0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_IN0_update_mux_mode_SHIFT)) & IOMUXD_MCLK_IN0_update_mux_mode_MASK)
58734/*! @} */
58735
58736/*! @name MCLK_OUT0 - MCLK_OUT0 */
58737/*! @{ */
58738#define IOMUXD_MCLK_OUT0_PDRV_MASK (0x1U)
58739#define IOMUXD_MCLK_OUT0_PDRV_SHIFT (0U)
58740/*! PDRV - Drive
58741 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58742 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58743 */
58744#define IOMUXD_MCLK_OUT0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_PDRV_SHIFT)) & IOMUXD_MCLK_OUT0_PDRV_MASK)
58745#define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_1_4_MASK (0x1EU)
58746#define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_1_4_SHIFT (1U)
58747/*! MCLK_OUT0_reserved_1_4 - reserved
58748 */
58749#define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_1_4_SHIFT)) & IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_1_4_MASK)
58750#define IOMUXD_MCLK_OUT0_PULL_MASK (0x60U)
58751#define IOMUXD_MCLK_OUT0_PULL_SHIFT (5U)
58752/*! PULL - Pull Down Pull Up
58753 * 0b10..pull down
58754 * 0b01..pull up
58755 * 0b00..Prohibited
58756 * 0b11..pull disabled
58757 */
58758#define IOMUXD_MCLK_OUT0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_PULL_SHIFT)) & IOMUXD_MCLK_OUT0_PULL_MASK)
58759#define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_7_18_MASK (0x7FF80U)
58760#define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_7_18_SHIFT (7U)
58761/*! MCLK_OUT0_reserved_7_18 - reserved
58762 */
58763#define IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_7_18_SHIFT)) & IOMUXD_MCLK_OUT0_MCLK_OUT0_reserved_7_18_MASK)
58764#define IOMUXD_MCLK_OUT0_WAKEUP_CTRL_MASK (0x380000U)
58765#define IOMUXD_MCLK_OUT0_WAKEUP_CTRL_SHIFT (19U)
58766/*! WAKEUP_CTRL - wakeup control
58767 * 0b000..OFF
58768 * 0b001..RESAMPLE
58769 * 0b100..LOW
58770 * 0b111..HIGH
58771 * 0b110..RISE
58772 * 0b101..FALL
58773 */
58774#define IOMUXD_MCLK_OUT0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_WAKEUP_CTRL_SHIFT)) & IOMUXD_MCLK_OUT0_WAKEUP_CTRL_MASK)
58775#define IOMUXD_MCLK_OUT0_WAKEUP_MASK_MASK (0x400000U)
58776#define IOMUXD_MCLK_OUT0_WAKEUP_MASK_SHIFT (22U)
58777/*! WAKEUP_MASK - wakeup mask
58778 */
58779#define IOMUXD_MCLK_OUT0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_WAKEUP_MASK_SHIFT)) & IOMUXD_MCLK_OUT0_WAKEUP_MASK_MASK)
58780#define IOMUXD_MCLK_OUT0_lp_config_MASK (0x1800000U)
58781#define IOMUXD_MCLK_OUT0_lp_config_SHIFT (23U)
58782/*! lp_config - lower power configuration
58783 * 0b01..EARLY_ISO
58784 * 0b10..LATE_ISO
58785 * 0b11..LATCH
58786 * 0b00..PASS
58787 */
58788#define IOMUXD_MCLK_OUT0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_lp_config_SHIFT)) & IOMUXD_MCLK_OUT0_lp_config_MASK)
58789#define IOMUXD_MCLK_OUT0_sw_config_MASK (0x6000000U)
58790#define IOMUXD_MCLK_OUT0_sw_config_SHIFT (25U)
58791/*! sw_config - output and input configuration
58792 * 0b01..OPEN_DRAIN
58793 * 0b10..OPEN_DRAIN_INPUT
58794 * 0b11..INOUT
58795 * 0b00..DEFAULT
58796 */
58797#define IOMUXD_MCLK_OUT0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_sw_config_SHIFT)) & IOMUXD_MCLK_OUT0_sw_config_MASK)
58798#define IOMUXD_MCLK_OUT0_mux_mode_MASK (0x38000000U)
58799#define IOMUXD_MCLK_OUT0_mux_mode_SHIFT (27U)
58800/*! mux_mode - mux_mode
58801 * 0b000..ADMA.ACM.MCLK_OUT0
58802 * 0b001..ADMA.ESAI0.TX_HF_CLK
58803 * 0b010..ADMA.LCDIF.CLK
58804 * 0b011..ADMA.SPI2.SDO
58805 * 0b100..LSIO.GPIO0.IO20
58806 */
58807#define IOMUXD_MCLK_OUT0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_mux_mode_SHIFT)) & IOMUXD_MCLK_OUT0_mux_mode_MASK)
58808#define IOMUXD_MCLK_OUT0_update_pad_ctl_MASK (0x40000000U)
58809#define IOMUXD_MCLK_OUT0_update_pad_ctl_SHIFT (30U)
58810/*! update_pad_ctl - update lock for pad control
58811 */
58812#define IOMUXD_MCLK_OUT0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_update_pad_ctl_SHIFT)) & IOMUXD_MCLK_OUT0_update_pad_ctl_MASK)
58813#define IOMUXD_MCLK_OUT0_update_mux_mode_MASK (0x80000000U)
58814#define IOMUXD_MCLK_OUT0_update_mux_mode_SHIFT (31U)
58815/*! update_mux_mode - update lock for mux control
58816 */
58817#define IOMUXD_MCLK_OUT0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MCLK_OUT0_update_mux_mode_SHIFT)) & IOMUXD_MCLK_OUT0_update_mux_mode_MASK)
58818/*! @} */
58819
58820/*! @name UART1_TX - UART1_TX */
58821/*! @{ */
58822#define IOMUXD_UART1_TX_PDRV_MASK (0x1U)
58823#define IOMUXD_UART1_TX_PDRV_SHIFT (0U)
58824/*! PDRV - Drive
58825 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58826 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58827 */
58828#define IOMUXD_UART1_TX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_PDRV_SHIFT)) & IOMUXD_UART1_TX_PDRV_MASK)
58829#define IOMUXD_UART1_TX_UART1_TX_reserved_1_4_MASK (0x1EU)
58830#define IOMUXD_UART1_TX_UART1_TX_reserved_1_4_SHIFT (1U)
58831/*! UART1_TX_reserved_1_4 - reserved
58832 */
58833#define IOMUXD_UART1_TX_UART1_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_UART1_TX_reserved_1_4_SHIFT)) & IOMUXD_UART1_TX_UART1_TX_reserved_1_4_MASK)
58834#define IOMUXD_UART1_TX_PULL_MASK (0x60U)
58835#define IOMUXD_UART1_TX_PULL_SHIFT (5U)
58836/*! PULL - Pull Down Pull Up
58837 * 0b10..pull down
58838 * 0b01..pull up
58839 * 0b00..Prohibited
58840 * 0b11..pull disabled
58841 */
58842#define IOMUXD_UART1_TX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_PULL_SHIFT)) & IOMUXD_UART1_TX_PULL_MASK)
58843#define IOMUXD_UART1_TX_UART1_TX_reserved_7_18_MASK (0x7FF80U)
58844#define IOMUXD_UART1_TX_UART1_TX_reserved_7_18_SHIFT (7U)
58845/*! UART1_TX_reserved_7_18 - reserved
58846 */
58847#define IOMUXD_UART1_TX_UART1_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_UART1_TX_reserved_7_18_SHIFT)) & IOMUXD_UART1_TX_UART1_TX_reserved_7_18_MASK)
58848#define IOMUXD_UART1_TX_WAKEUP_CTRL_MASK (0x380000U)
58849#define IOMUXD_UART1_TX_WAKEUP_CTRL_SHIFT (19U)
58850/*! WAKEUP_CTRL - wakeup control
58851 * 0b000..OFF
58852 * 0b001..RESAMPLE
58853 * 0b100..LOW
58854 * 0b111..HIGH
58855 * 0b110..RISE
58856 * 0b101..FALL
58857 */
58858#define IOMUXD_UART1_TX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART1_TX_WAKEUP_CTRL_MASK)
58859#define IOMUXD_UART1_TX_WAKEUP_MASK_MASK (0x400000U)
58860#define IOMUXD_UART1_TX_WAKEUP_MASK_SHIFT (22U)
58861/*! WAKEUP_MASK - wakeup mask
58862 */
58863#define IOMUXD_UART1_TX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART1_TX_WAKEUP_MASK_MASK)
58864#define IOMUXD_UART1_TX_lp_config_MASK (0x1800000U)
58865#define IOMUXD_UART1_TX_lp_config_SHIFT (23U)
58866/*! lp_config - lower power configuration
58867 * 0b01..EARLY_ISO
58868 * 0b10..LATE_ISO
58869 * 0b11..LATCH
58870 * 0b00..PASS
58871 */
58872#define IOMUXD_UART1_TX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_lp_config_SHIFT)) & IOMUXD_UART1_TX_lp_config_MASK)
58873#define IOMUXD_UART1_TX_sw_config_MASK (0x6000000U)
58874#define IOMUXD_UART1_TX_sw_config_SHIFT (25U)
58875/*! sw_config - output and input configuration
58876 * 0b01..OPEN_DRAIN
58877 * 0b10..OPEN_DRAIN_INPUT
58878 * 0b11..INOUT
58879 * 0b00..DEFAULT
58880 */
58881#define IOMUXD_UART1_TX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_sw_config_SHIFT)) & IOMUXD_UART1_TX_sw_config_MASK)
58882#define IOMUXD_UART1_TX_mux_mode_MASK (0x38000000U)
58883#define IOMUXD_UART1_TX_mux_mode_SHIFT (27U)
58884/*! mux_mode - mux_mode
58885 * 0b000..ADMA.UART1.TX
58886 * 0b001..LSIO.PWM0.OUT
58887 * 0b010..LSIO.GPT0.CAPTURE
58888 * 0b100..LSIO.GPIO0.IO21
58889 */
58890#define IOMUXD_UART1_TX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_mux_mode_SHIFT)) & IOMUXD_UART1_TX_mux_mode_MASK)
58891#define IOMUXD_UART1_TX_update_pad_ctl_MASK (0x40000000U)
58892#define IOMUXD_UART1_TX_update_pad_ctl_SHIFT (30U)
58893/*! update_pad_ctl - update lock for pad control
58894 */
58895#define IOMUXD_UART1_TX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_update_pad_ctl_SHIFT)) & IOMUXD_UART1_TX_update_pad_ctl_MASK)
58896#define IOMUXD_UART1_TX_update_mux_mode_MASK (0x80000000U)
58897#define IOMUXD_UART1_TX_update_mux_mode_SHIFT (31U)
58898/*! update_mux_mode - update lock for mux control
58899 */
58900#define IOMUXD_UART1_TX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_TX_update_mux_mode_SHIFT)) & IOMUXD_UART1_TX_update_mux_mode_MASK)
58901/*! @} */
58902
58903/*! @name UART1_RX - UART1_RX */
58904/*! @{ */
58905#define IOMUXD_UART1_RX_PDRV_MASK (0x1U)
58906#define IOMUXD_UART1_RX_PDRV_SHIFT (0U)
58907/*! PDRV - Drive
58908 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58909 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58910 */
58911#define IOMUXD_UART1_RX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_PDRV_SHIFT)) & IOMUXD_UART1_RX_PDRV_MASK)
58912#define IOMUXD_UART1_RX_UART1_RX_reserved_1_4_MASK (0x1EU)
58913#define IOMUXD_UART1_RX_UART1_RX_reserved_1_4_SHIFT (1U)
58914/*! UART1_RX_reserved_1_4 - reserved
58915 */
58916#define IOMUXD_UART1_RX_UART1_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_UART1_RX_reserved_1_4_SHIFT)) & IOMUXD_UART1_RX_UART1_RX_reserved_1_4_MASK)
58917#define IOMUXD_UART1_RX_PULL_MASK (0x60U)
58918#define IOMUXD_UART1_RX_PULL_SHIFT (5U)
58919/*! PULL - Pull Down Pull Up
58920 * 0b10..pull down
58921 * 0b01..pull up
58922 * 0b00..Prohibited
58923 * 0b11..pull disabled
58924 */
58925#define IOMUXD_UART1_RX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_PULL_SHIFT)) & IOMUXD_UART1_RX_PULL_MASK)
58926#define IOMUXD_UART1_RX_UART1_RX_reserved_7_18_MASK (0x7FF80U)
58927#define IOMUXD_UART1_RX_UART1_RX_reserved_7_18_SHIFT (7U)
58928/*! UART1_RX_reserved_7_18 - reserved
58929 */
58930#define IOMUXD_UART1_RX_UART1_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_UART1_RX_reserved_7_18_SHIFT)) & IOMUXD_UART1_RX_UART1_RX_reserved_7_18_MASK)
58931#define IOMUXD_UART1_RX_WAKEUP_CTRL_MASK (0x380000U)
58932#define IOMUXD_UART1_RX_WAKEUP_CTRL_SHIFT (19U)
58933/*! WAKEUP_CTRL - wakeup control
58934 * 0b000..OFF
58935 * 0b001..RESAMPLE
58936 * 0b100..LOW
58937 * 0b111..HIGH
58938 * 0b110..RISE
58939 * 0b101..FALL
58940 */
58941#define IOMUXD_UART1_RX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART1_RX_WAKEUP_CTRL_MASK)
58942#define IOMUXD_UART1_RX_WAKEUP_MASK_MASK (0x400000U)
58943#define IOMUXD_UART1_RX_WAKEUP_MASK_SHIFT (22U)
58944/*! WAKEUP_MASK - wakeup mask
58945 */
58946#define IOMUXD_UART1_RX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART1_RX_WAKEUP_MASK_MASK)
58947#define IOMUXD_UART1_RX_lp_config_MASK (0x1800000U)
58948#define IOMUXD_UART1_RX_lp_config_SHIFT (23U)
58949/*! lp_config - lower power configuration
58950 * 0b01..EARLY_ISO
58951 * 0b10..LATE_ISO
58952 * 0b11..LATCH
58953 * 0b00..PASS
58954 */
58955#define IOMUXD_UART1_RX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_lp_config_SHIFT)) & IOMUXD_UART1_RX_lp_config_MASK)
58956#define IOMUXD_UART1_RX_sw_config_MASK (0x6000000U)
58957#define IOMUXD_UART1_RX_sw_config_SHIFT (25U)
58958/*! sw_config - output and input configuration
58959 * 0b01..OPEN_DRAIN
58960 * 0b10..OPEN_DRAIN_INPUT
58961 * 0b11..INOUT
58962 * 0b00..DEFAULT
58963 */
58964#define IOMUXD_UART1_RX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_sw_config_SHIFT)) & IOMUXD_UART1_RX_sw_config_MASK)
58965#define IOMUXD_UART1_RX_mux_mode_MASK (0x38000000U)
58966#define IOMUXD_UART1_RX_mux_mode_SHIFT (27U)
58967/*! mux_mode - mux_mode
58968 * 0b000..ADMA.UART1.RX
58969 * 0b001..LSIO.PWM1.OUT
58970 * 0b010..LSIO.GPT0.COMPARE
58971 * 0b011..LSIO.GPT1.CLK
58972 * 0b100..LSIO.GPIO0.IO22
58973 */
58974#define IOMUXD_UART1_RX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_mux_mode_SHIFT)) & IOMUXD_UART1_RX_mux_mode_MASK)
58975#define IOMUXD_UART1_RX_update_pad_ctl_MASK (0x40000000U)
58976#define IOMUXD_UART1_RX_update_pad_ctl_SHIFT (30U)
58977/*! update_pad_ctl - update lock for pad control
58978 */
58979#define IOMUXD_UART1_RX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_update_pad_ctl_SHIFT)) & IOMUXD_UART1_RX_update_pad_ctl_MASK)
58980#define IOMUXD_UART1_RX_update_mux_mode_MASK (0x80000000U)
58981#define IOMUXD_UART1_RX_update_mux_mode_SHIFT (31U)
58982/*! update_mux_mode - update lock for mux control
58983 */
58984#define IOMUXD_UART1_RX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RX_update_mux_mode_SHIFT)) & IOMUXD_UART1_RX_update_mux_mode_MASK)
58985/*! @} */
58986
58987/*! @name UART1_RTS_B - UART1_RTS_B */
58988/*! @{ */
58989#define IOMUXD_UART1_RTS_B_PDRV_MASK (0x1U)
58990#define IOMUXD_UART1_RTS_B_PDRV_SHIFT (0U)
58991/*! PDRV - Drive
58992 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
58993 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
58994 */
58995#define IOMUXD_UART1_RTS_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_PDRV_SHIFT)) & IOMUXD_UART1_RTS_B_PDRV_MASK)
58996#define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_1_4_MASK (0x1EU)
58997#define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_1_4_SHIFT (1U)
58998/*! UART1_RTS_B_reserved_1_4 - reserved
58999 */
59000#define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_1_4_SHIFT)) & IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_1_4_MASK)
59001#define IOMUXD_UART1_RTS_B_PULL_MASK (0x60U)
59002#define IOMUXD_UART1_RTS_B_PULL_SHIFT (5U)
59003/*! PULL - Pull Down Pull Up
59004 * 0b10..pull down
59005 * 0b01..pull up
59006 * 0b00..Prohibited
59007 * 0b11..pull disabled
59008 */
59009#define IOMUXD_UART1_RTS_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_PULL_SHIFT)) & IOMUXD_UART1_RTS_B_PULL_MASK)
59010#define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_7_18_MASK (0x7FF80U)
59011#define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_7_18_SHIFT (7U)
59012/*! UART1_RTS_B_reserved_7_18 - reserved
59013 */
59014#define IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_7_18_SHIFT)) & IOMUXD_UART1_RTS_B_UART1_RTS_B_reserved_7_18_MASK)
59015#define IOMUXD_UART1_RTS_B_WAKEUP_CTRL_MASK (0x380000U)
59016#define IOMUXD_UART1_RTS_B_WAKEUP_CTRL_SHIFT (19U)
59017/*! WAKEUP_CTRL - wakeup control
59018 * 0b000..OFF
59019 * 0b001..RESAMPLE
59020 * 0b100..LOW
59021 * 0b111..HIGH
59022 * 0b110..RISE
59023 * 0b101..FALL
59024 */
59025#define IOMUXD_UART1_RTS_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART1_RTS_B_WAKEUP_CTRL_MASK)
59026#define IOMUXD_UART1_RTS_B_WAKEUP_MASK_MASK (0x400000U)
59027#define IOMUXD_UART1_RTS_B_WAKEUP_MASK_SHIFT (22U)
59028/*! WAKEUP_MASK - wakeup mask
59029 */
59030#define IOMUXD_UART1_RTS_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_WAKEUP_MASK_SHIFT)) & IOMUXD_UART1_RTS_B_WAKEUP_MASK_MASK)
59031#define IOMUXD_UART1_RTS_B_lp_config_MASK (0x1800000U)
59032#define IOMUXD_UART1_RTS_B_lp_config_SHIFT (23U)
59033/*! lp_config - lower power configuration
59034 * 0b01..EARLY_ISO
59035 * 0b10..LATE_ISO
59036 * 0b11..LATCH
59037 * 0b00..PASS
59038 */
59039#define IOMUXD_UART1_RTS_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_lp_config_SHIFT)) & IOMUXD_UART1_RTS_B_lp_config_MASK)
59040#define IOMUXD_UART1_RTS_B_sw_config_MASK (0x6000000U)
59041#define IOMUXD_UART1_RTS_B_sw_config_SHIFT (25U)
59042/*! sw_config - output and input configuration
59043 * 0b01..OPEN_DRAIN
59044 * 0b10..OPEN_DRAIN_INPUT
59045 * 0b11..INOUT
59046 * 0b00..DEFAULT
59047 */
59048#define IOMUXD_UART1_RTS_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_sw_config_SHIFT)) & IOMUXD_UART1_RTS_B_sw_config_MASK)
59049#define IOMUXD_UART1_RTS_B_mux_mode_MASK (0x38000000U)
59050#define IOMUXD_UART1_RTS_B_mux_mode_SHIFT (27U)
59051/*! mux_mode - mux_mode
59052 * 0b000..ADMA.UART1.RTS_B
59053 * 0b001..LSIO.PWM2.OUT
59054 * 0b010..ADMA.LCDIF.D16
59055 * 0b011..LSIO.GPT1.CAPTURE
59056 * 0b100..LSIO.GPT0.CLK
59057 */
59058#define IOMUXD_UART1_RTS_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_mux_mode_SHIFT)) & IOMUXD_UART1_RTS_B_mux_mode_MASK)
59059#define IOMUXD_UART1_RTS_B_update_pad_ctl_MASK (0x40000000U)
59060#define IOMUXD_UART1_RTS_B_update_pad_ctl_SHIFT (30U)
59061/*! update_pad_ctl - update lock for pad control
59062 */
59063#define IOMUXD_UART1_RTS_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_update_pad_ctl_SHIFT)) & IOMUXD_UART1_RTS_B_update_pad_ctl_MASK)
59064#define IOMUXD_UART1_RTS_B_update_mux_mode_MASK (0x80000000U)
59065#define IOMUXD_UART1_RTS_B_update_mux_mode_SHIFT (31U)
59066/*! update_mux_mode - update lock for mux control
59067 */
59068#define IOMUXD_UART1_RTS_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_RTS_B_update_mux_mode_SHIFT)) & IOMUXD_UART1_RTS_B_update_mux_mode_MASK)
59069/*! @} */
59070
59071/*! @name UART1_CTS_B - UART1_CTS_B */
59072/*! @{ */
59073#define IOMUXD_UART1_CTS_B_PDRV_MASK (0x1U)
59074#define IOMUXD_UART1_CTS_B_PDRV_SHIFT (0U)
59075/*! PDRV - Drive
59076 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59077 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59078 */
59079#define IOMUXD_UART1_CTS_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_PDRV_SHIFT)) & IOMUXD_UART1_CTS_B_PDRV_MASK)
59080#define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_1_4_MASK (0x1EU)
59081#define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_1_4_SHIFT (1U)
59082/*! UART1_CTS_B_reserved_1_4 - reserved
59083 */
59084#define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_1_4_SHIFT)) & IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_1_4_MASK)
59085#define IOMUXD_UART1_CTS_B_PULL_MASK (0x60U)
59086#define IOMUXD_UART1_CTS_B_PULL_SHIFT (5U)
59087/*! PULL - Pull Down Pull Up
59088 * 0b10..pull down
59089 * 0b01..pull up
59090 * 0b00..Prohibited
59091 * 0b11..pull disabled
59092 */
59093#define IOMUXD_UART1_CTS_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_PULL_SHIFT)) & IOMUXD_UART1_CTS_B_PULL_MASK)
59094#define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_7_18_MASK (0x7FF80U)
59095#define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_7_18_SHIFT (7U)
59096/*! UART1_CTS_B_reserved_7_18 - reserved
59097 */
59098#define IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_7_18_SHIFT)) & IOMUXD_UART1_CTS_B_UART1_CTS_B_reserved_7_18_MASK)
59099#define IOMUXD_UART1_CTS_B_WAKEUP_CTRL_MASK (0x380000U)
59100#define IOMUXD_UART1_CTS_B_WAKEUP_CTRL_SHIFT (19U)
59101/*! WAKEUP_CTRL - wakeup control
59102 * 0b000..OFF
59103 * 0b001..RESAMPLE
59104 * 0b100..LOW
59105 * 0b111..HIGH
59106 * 0b110..RISE
59107 * 0b101..FALL
59108 */
59109#define IOMUXD_UART1_CTS_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART1_CTS_B_WAKEUP_CTRL_MASK)
59110#define IOMUXD_UART1_CTS_B_WAKEUP_MASK_MASK (0x400000U)
59111#define IOMUXD_UART1_CTS_B_WAKEUP_MASK_SHIFT (22U)
59112/*! WAKEUP_MASK - wakeup mask
59113 */
59114#define IOMUXD_UART1_CTS_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_WAKEUP_MASK_SHIFT)) & IOMUXD_UART1_CTS_B_WAKEUP_MASK_MASK)
59115#define IOMUXD_UART1_CTS_B_lp_config_MASK (0x1800000U)
59116#define IOMUXD_UART1_CTS_B_lp_config_SHIFT (23U)
59117/*! lp_config - lower power configuration
59118 * 0b01..EARLY_ISO
59119 * 0b10..LATE_ISO
59120 * 0b11..LATCH
59121 * 0b00..PASS
59122 */
59123#define IOMUXD_UART1_CTS_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_lp_config_SHIFT)) & IOMUXD_UART1_CTS_B_lp_config_MASK)
59124#define IOMUXD_UART1_CTS_B_sw_config_MASK (0x6000000U)
59125#define IOMUXD_UART1_CTS_B_sw_config_SHIFT (25U)
59126/*! sw_config - output and input configuration
59127 * 0b01..OPEN_DRAIN
59128 * 0b10..OPEN_DRAIN_INPUT
59129 * 0b11..INOUT
59130 * 0b00..DEFAULT
59131 */
59132#define IOMUXD_UART1_CTS_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_sw_config_SHIFT)) & IOMUXD_UART1_CTS_B_sw_config_MASK)
59133#define IOMUXD_UART1_CTS_B_mux_mode_MASK (0x38000000U)
59134#define IOMUXD_UART1_CTS_B_mux_mode_SHIFT (27U)
59135/*! mux_mode - mux_mode
59136 * 0b000..ADMA.UART1.CTS_B
59137 * 0b001..LSIO.PWM3.OUT
59138 * 0b010..ADMA.LCDIF.D17
59139 * 0b011..LSIO.GPT1.COMPARE
59140 * 0b100..LSIO.GPIO0.IO24
59141 */
59142#define IOMUXD_UART1_CTS_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_mux_mode_SHIFT)) & IOMUXD_UART1_CTS_B_mux_mode_MASK)
59143#define IOMUXD_UART1_CTS_B_update_pad_ctl_MASK (0x40000000U)
59144#define IOMUXD_UART1_CTS_B_update_pad_ctl_SHIFT (30U)
59145/*! update_pad_ctl - update lock for pad control
59146 */
59147#define IOMUXD_UART1_CTS_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_update_pad_ctl_SHIFT)) & IOMUXD_UART1_CTS_B_update_pad_ctl_MASK)
59148#define IOMUXD_UART1_CTS_B_update_mux_mode_MASK (0x80000000U)
59149#define IOMUXD_UART1_CTS_B_update_mux_mode_SHIFT (31U)
59150/*! update_mux_mode - update lock for mux control
59151 */
59152#define IOMUXD_UART1_CTS_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART1_CTS_B_update_mux_mode_SHIFT)) & IOMUXD_UART1_CTS_B_update_mux_mode_MASK)
59153/*! @} */
59154
59155/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK */
59156/*! @{ */
59157#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMP_MASK (0x7U)
59158#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMP_SHIFT (0U)
59159/*! COMP - COMP
59160 * 0b010..Fixed code mode
59161 * 0b100..High impedance mode
59162 * 0b110..Read mode
59163 * 0b000..Normal Mode
59164 * 0b001..Freeze Mode
59165 */
59166#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMP_MASK)
59167#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_FASTFRZ_EN_MASK (0x8U)
59168#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_FASTFRZ_EN_SHIFT (3U)
59169/*! FASTFRZ_EN - FASTFRZ_EN
59170 * 0b1..FASTFRZ signal is driven by output of subsystem
59171 * 0b0..FASTFRZ signal is gated to 0
59172 */
59173#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_FASTFRZ_EN_MASK)
59174#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_4_4_MASK (0x10U)
59175#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_4_4_SHIFT (4U)
59176/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_4_4 - reserved
59177 */
59178#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_4_4_MASK)
59179#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCP_MASK (0x1E0U)
59180#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCP_SHIFT (5U)
59181/*! RASRCP - RASRCP
59182 * 0b0101..Reset Value
59183 */
59184#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCP_MASK)
59185#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCN_MASK (0x1E00U)
59186#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCN_SHIFT (9U)
59187/*! RASRCN - RASRCN
59188 * 0b1010..Reset Value
59189 */
59190#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_RASRCN_MASK)
59191#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SELECT_NASRC_MASK (0x2000U)
59192#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SELECT_NASRC_SHIFT (13U)
59193/*! SELECT_NASRC - SELECT_NASRC
59194 * 0b1..NASRCN value
59195 * 0b0..NASRCP value
59196 */
59197#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SELECT_NASRC_MASK)
59198#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMPOK_MASK (0x4000U)
59199#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMPOK_SHIFT (14U)
59200/*! COMPOK - COMPOK
59201 * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
59202 * 0b1..compensation cell in Normal mode and tracking PVT
59203 */
59204#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_COMPOK_MASK)
59205#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_READ_NASRC_MASK (0x78000U)
59206#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_READ_NASRC_SHIFT (15U)
59207/*! READ_NASRC - READ_NASRC
59208 * 0b0000..READ Only
59209 */
59210#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_READ_NASRC_MASK)
59211#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_19_22_MASK (0x780000U)
59212#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_19_22_SHIFT (19U)
59213/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_19_22 - reserved
59214 */
59215#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_19_22_MASK)
59216#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SLEEP_MASK (0x1800000U)
59217#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SLEEP_SHIFT (23U)
59218/*! SLEEP - SLEEP
59219 * 0b11..Force into sleep mode
59220 * 0b00..NO
59221 * 0b01..EARLY
59222 * 0b10..LATE
59223 */
59224#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_SLEEP_MASK)
59225#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_25_29_MASK (0x3E000000U)
59226#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_25_29_SHIFT (25U)
59227/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_25_29 - reserved
59228 */
59229#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_reserved_25_29_MASK)
59230#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_pad_ctl_MASK (0x40000000U)
59231#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_pad_ctl_SHIFT (30U)
59232/*! update_pad_ctl - update lock for pad control
59233 */
59234#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_pad_ctl_MASK)
59235#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_mux_mode_MASK (0x80000000U)
59236#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_mux_mode_SHIFT (31U)
59237/*! update_mux_mode - update lock for mux control
59238 */
59239#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHK_update_mux_mode_MASK)
59240/*! @} */
59241
59242/*! @name IOMUXD_GROUP_1_4 - na */
59243/*! @{ */
59244#define IOMUXD_IOMUXD_GROUP_1_4_SPDIF0_EXT_CLK_MASK (0x1U)
59245#define IOMUXD_IOMUXD_GROUP_1_4_SPDIF0_EXT_CLK_SHIFT (0U)
59246/*! SPDIF0_EXT_CLK - wakeup from SPDIF0_EXT_CLK
59247 */
59248#define IOMUXD_IOMUXD_GROUP_1_4_SPDIF0_EXT_CLK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPDIF0_EXT_CLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPDIF0_EXT_CLK_MASK)
59249#define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_1_1_MASK (0x2U)
59250#define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_1_1_SHIFT (1U)
59251/*! iomuxd_group_1_4_reserved_1_1 - reserved
59252 */
59253#define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_1_1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_1_1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_1_1_MASK)
59254#define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SCK_MASK (0x4U)
59255#define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SCK_SHIFT (2U)
59256/*! SPI3_SCK - wakeup from SPI3_SCK
59257 */
59258#define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI3_SCK_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI3_SCK_MASK)
59259#define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDO_MASK (0x8U)
59260#define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDO_SHIFT (3U)
59261/*! SPI3_SDO - wakeup from SPI3_SDO
59262 */
59263#define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDO(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDO_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDO_MASK)
59264#define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDI_MASK (0x10U)
59265#define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDI_SHIFT (4U)
59266/*! SPI3_SDI - wakeup from SPI3_SDI
59267 */
59268#define IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDI(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDI_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI3_SDI_MASK)
59269#define IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS0_MASK (0x20U)
59270#define IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS0_SHIFT (5U)
59271/*! SPI3_CS0 - wakeup from SPI3_CS0
59272 */
59273#define IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS0_MASK)
59274#define IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS1_MASK (0x40U)
59275#define IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS1_SHIFT (6U)
59276/*! SPI3_CS1 - wakeup from SPI3_CS1
59277 */
59278#define IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_SPI3_CS1_MASK)
59279#define IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN1_MASK (0x80U)
59280#define IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN1_SHIFT (7U)
59281/*! MCLK_IN1 - wakeup from MCLK_IN1
59282 */
59283#define IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN1_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN1_MASK)
59284#define IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN0_MASK (0x100U)
59285#define IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN0_SHIFT (8U)
59286/*! MCLK_IN0 - wakeup from MCLK_IN0
59287 */
59288#define IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_MCLK_IN0_MASK)
59289#define IOMUXD_IOMUXD_GROUP_1_4_MCLK_OUT0_MASK (0x200U)
59290#define IOMUXD_IOMUXD_GROUP_1_4_MCLK_OUT0_SHIFT (9U)
59291/*! MCLK_OUT0 - wakeup from MCLK_OUT0
59292 */
59293#define IOMUXD_IOMUXD_GROUP_1_4_MCLK_OUT0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_MCLK_OUT0_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_MCLK_OUT0_MASK)
59294#define IOMUXD_IOMUXD_GROUP_1_4_UART1_TX_MASK (0x400U)
59295#define IOMUXD_IOMUXD_GROUP_1_4_UART1_TX_SHIFT (10U)
59296/*! UART1_TX - wakeup from UART1_TX
59297 */
59298#define IOMUXD_IOMUXD_GROUP_1_4_UART1_TX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_UART1_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_UART1_TX_MASK)
59299#define IOMUXD_IOMUXD_GROUP_1_4_UART1_RX_MASK (0x800U)
59300#define IOMUXD_IOMUXD_GROUP_1_4_UART1_RX_SHIFT (11U)
59301/*! UART1_RX - wakeup from UART1_RX
59302 */
59303#define IOMUXD_IOMUXD_GROUP_1_4_UART1_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_UART1_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_UART1_RX_MASK)
59304#define IOMUXD_IOMUXD_GROUP_1_4_UART1_RTS_B_MASK (0x1000U)
59305#define IOMUXD_IOMUXD_GROUP_1_4_UART1_RTS_B_SHIFT (12U)
59306/*! UART1_RTS_B - wakeup from UART1_RTS_B
59307 */
59308#define IOMUXD_IOMUXD_GROUP_1_4_UART1_RTS_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_UART1_RTS_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_UART1_RTS_B_MASK)
59309#define IOMUXD_IOMUXD_GROUP_1_4_UART1_CTS_B_MASK (0x2000U)
59310#define IOMUXD_IOMUXD_GROUP_1_4_UART1_CTS_B_SHIFT (13U)
59311/*! UART1_CTS_B - wakeup from UART1_CTS_B
59312 */
59313#define IOMUXD_IOMUXD_GROUP_1_4_UART1_CTS_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_UART1_CTS_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_UART1_CTS_B_MASK)
59314#define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_14_31_MASK (0xFFFFC000U)
59315#define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_14_31_SHIFT (14U)
59316/*! iomuxd_group_1_4_reserved_14_31 - reserved
59317 */
59318#define IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_14_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_14_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_1_4_iomuxd_group_1_4_reserved_14_31_MASK)
59319/*! @} */
59320
59321/*! @name SAI0_TXD - SAI0_TXD */
59322/*! @{ */
59323#define IOMUXD_SAI0_TXD_PDRV_MASK (0x1U)
59324#define IOMUXD_SAI0_TXD_PDRV_SHIFT (0U)
59325/*! PDRV - Drive
59326 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59327 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59328 */
59329#define IOMUXD_SAI0_TXD_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_PDRV_SHIFT)) & IOMUXD_SAI0_TXD_PDRV_MASK)
59330#define IOMUXD_SAI0_TXD_SAI0_TXD_reserved_1_4_MASK (0x1EU)
59331#define IOMUXD_SAI0_TXD_SAI0_TXD_reserved_1_4_SHIFT (1U)
59332/*! SAI0_TXD_reserved_1_4 - reserved
59333 */
59334#define IOMUXD_SAI0_TXD_SAI0_TXD_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_SAI0_TXD_reserved_1_4_SHIFT)) & IOMUXD_SAI0_TXD_SAI0_TXD_reserved_1_4_MASK)
59335#define IOMUXD_SAI0_TXD_PULL_MASK (0x60U)
59336#define IOMUXD_SAI0_TXD_PULL_SHIFT (5U)
59337/*! PULL - Pull Down Pull Up
59338 * 0b10..pull down
59339 * 0b01..pull up
59340 * 0b00..Prohibited
59341 * 0b11..pull disabled
59342 */
59343#define IOMUXD_SAI0_TXD_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_PULL_SHIFT)) & IOMUXD_SAI0_TXD_PULL_MASK)
59344#define IOMUXD_SAI0_TXD_SAI0_TXD_reserved_7_18_MASK (0x7FF80U)
59345#define IOMUXD_SAI0_TXD_SAI0_TXD_reserved_7_18_SHIFT (7U)
59346/*! SAI0_TXD_reserved_7_18 - reserved
59347 */
59348#define IOMUXD_SAI0_TXD_SAI0_TXD_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_SAI0_TXD_reserved_7_18_SHIFT)) & IOMUXD_SAI0_TXD_SAI0_TXD_reserved_7_18_MASK)
59349#define IOMUXD_SAI0_TXD_WAKEUP_CTRL_MASK (0x380000U)
59350#define IOMUXD_SAI0_TXD_WAKEUP_CTRL_SHIFT (19U)
59351/*! WAKEUP_CTRL - wakeup control
59352 * 0b000..OFF
59353 * 0b001..RESAMPLE
59354 * 0b100..LOW
59355 * 0b111..HIGH
59356 * 0b110..RISE
59357 * 0b101..FALL
59358 */
59359#define IOMUXD_SAI0_TXD_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI0_TXD_WAKEUP_CTRL_MASK)
59360#define IOMUXD_SAI0_TXD_WAKEUP_MASK_MASK (0x400000U)
59361#define IOMUXD_SAI0_TXD_WAKEUP_MASK_SHIFT (22U)
59362/*! WAKEUP_MASK - wakeup mask
59363 */
59364#define IOMUXD_SAI0_TXD_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI0_TXD_WAKEUP_MASK_MASK)
59365#define IOMUXD_SAI0_TXD_lp_config_MASK (0x1800000U)
59366#define IOMUXD_SAI0_TXD_lp_config_SHIFT (23U)
59367/*! lp_config - lower power configuration
59368 * 0b01..EARLY_ISO
59369 * 0b10..LATE_ISO
59370 * 0b11..LATCH
59371 * 0b00..PASS
59372 */
59373#define IOMUXD_SAI0_TXD_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_lp_config_SHIFT)) & IOMUXD_SAI0_TXD_lp_config_MASK)
59374#define IOMUXD_SAI0_TXD_sw_config_MASK (0x6000000U)
59375#define IOMUXD_SAI0_TXD_sw_config_SHIFT (25U)
59376/*! sw_config - output and input configuration
59377 * 0b01..OPEN_DRAIN
59378 * 0b10..OPEN_DRAIN_INPUT
59379 * 0b11..INOUT
59380 * 0b00..DEFAULT
59381 */
59382#define IOMUXD_SAI0_TXD_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_sw_config_SHIFT)) & IOMUXD_SAI0_TXD_sw_config_MASK)
59383#define IOMUXD_SAI0_TXD_mux_mode_MASK (0x38000000U)
59384#define IOMUXD_SAI0_TXD_mux_mode_SHIFT (27U)
59385/*! mux_mode - mux_mode
59386 * 0b000..ADMA.SAI0.TXD
59387 * 0b001..ADMA.SAI1.RXC
59388 * 0b010..ADMA.SPI1.SDO
59389 * 0b011..ADMA.LCDIF.D18
59390 * 0b100..LSIO.GPIO0.IO25
59391 */
59392#define IOMUXD_SAI0_TXD_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_mux_mode_SHIFT)) & IOMUXD_SAI0_TXD_mux_mode_MASK)
59393#define IOMUXD_SAI0_TXD_update_pad_ctl_MASK (0x40000000U)
59394#define IOMUXD_SAI0_TXD_update_pad_ctl_SHIFT (30U)
59395/*! update_pad_ctl - update lock for pad control
59396 */
59397#define IOMUXD_SAI0_TXD_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_update_pad_ctl_SHIFT)) & IOMUXD_SAI0_TXD_update_pad_ctl_MASK)
59398#define IOMUXD_SAI0_TXD_update_mux_mode_MASK (0x80000000U)
59399#define IOMUXD_SAI0_TXD_update_mux_mode_SHIFT (31U)
59400/*! update_mux_mode - update lock for mux control
59401 */
59402#define IOMUXD_SAI0_TXD_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXD_update_mux_mode_SHIFT)) & IOMUXD_SAI0_TXD_update_mux_mode_MASK)
59403/*! @} */
59404
59405/*! @name SAI0_TXC - SAI0_TXC */
59406/*! @{ */
59407#define IOMUXD_SAI0_TXC_PDRV_MASK (0x1U)
59408#define IOMUXD_SAI0_TXC_PDRV_SHIFT (0U)
59409/*! PDRV - Drive
59410 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59411 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59412 */
59413#define IOMUXD_SAI0_TXC_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_PDRV_SHIFT)) & IOMUXD_SAI0_TXC_PDRV_MASK)
59414#define IOMUXD_SAI0_TXC_SAI0_TXC_reserved_1_4_MASK (0x1EU)
59415#define IOMUXD_SAI0_TXC_SAI0_TXC_reserved_1_4_SHIFT (1U)
59416/*! SAI0_TXC_reserved_1_4 - reserved
59417 */
59418#define IOMUXD_SAI0_TXC_SAI0_TXC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_SAI0_TXC_reserved_1_4_SHIFT)) & IOMUXD_SAI0_TXC_SAI0_TXC_reserved_1_4_MASK)
59419#define IOMUXD_SAI0_TXC_PULL_MASK (0x60U)
59420#define IOMUXD_SAI0_TXC_PULL_SHIFT (5U)
59421/*! PULL - Pull Down Pull Up
59422 * 0b10..pull down
59423 * 0b01..pull up
59424 * 0b00..Prohibited
59425 * 0b11..pull disabled
59426 */
59427#define IOMUXD_SAI0_TXC_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_PULL_SHIFT)) & IOMUXD_SAI0_TXC_PULL_MASK)
59428#define IOMUXD_SAI0_TXC_SAI0_TXC_reserved_7_18_MASK (0x7FF80U)
59429#define IOMUXD_SAI0_TXC_SAI0_TXC_reserved_7_18_SHIFT (7U)
59430/*! SAI0_TXC_reserved_7_18 - reserved
59431 */
59432#define IOMUXD_SAI0_TXC_SAI0_TXC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_SAI0_TXC_reserved_7_18_SHIFT)) & IOMUXD_SAI0_TXC_SAI0_TXC_reserved_7_18_MASK)
59433#define IOMUXD_SAI0_TXC_WAKEUP_CTRL_MASK (0x380000U)
59434#define IOMUXD_SAI0_TXC_WAKEUP_CTRL_SHIFT (19U)
59435/*! WAKEUP_CTRL - wakeup control
59436 * 0b000..OFF
59437 * 0b001..RESAMPLE
59438 * 0b100..LOW
59439 * 0b111..HIGH
59440 * 0b110..RISE
59441 * 0b101..FALL
59442 */
59443#define IOMUXD_SAI0_TXC_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI0_TXC_WAKEUP_CTRL_MASK)
59444#define IOMUXD_SAI0_TXC_WAKEUP_MASK_MASK (0x400000U)
59445#define IOMUXD_SAI0_TXC_WAKEUP_MASK_SHIFT (22U)
59446/*! WAKEUP_MASK - wakeup mask
59447 */
59448#define IOMUXD_SAI0_TXC_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI0_TXC_WAKEUP_MASK_MASK)
59449#define IOMUXD_SAI0_TXC_lp_config_MASK (0x1800000U)
59450#define IOMUXD_SAI0_TXC_lp_config_SHIFT (23U)
59451/*! lp_config - lower power configuration
59452 * 0b01..EARLY_ISO
59453 * 0b10..LATE_ISO
59454 * 0b11..LATCH
59455 * 0b00..PASS
59456 */
59457#define IOMUXD_SAI0_TXC_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_lp_config_SHIFT)) & IOMUXD_SAI0_TXC_lp_config_MASK)
59458#define IOMUXD_SAI0_TXC_sw_config_MASK (0x6000000U)
59459#define IOMUXD_SAI0_TXC_sw_config_SHIFT (25U)
59460/*! sw_config - output and input configuration
59461 * 0b01..OPEN_DRAIN
59462 * 0b10..OPEN_DRAIN_INPUT
59463 * 0b11..INOUT
59464 * 0b00..DEFAULT
59465 */
59466#define IOMUXD_SAI0_TXC_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_sw_config_SHIFT)) & IOMUXD_SAI0_TXC_sw_config_MASK)
59467#define IOMUXD_SAI0_TXC_mux_mode_MASK (0x38000000U)
59468#define IOMUXD_SAI0_TXC_mux_mode_SHIFT (27U)
59469/*! mux_mode - mux_mode
59470 * 0b000..ADMA.SAI0.TXC
59471 * 0b001..ADMA.SAI1.TXD
59472 * 0b010..ADMA.SPI1.SDI
59473 * 0b011..ADMA.LCDIF.D19
59474 * 0b100..LSIO.GPIO0.IO26
59475 */
59476#define IOMUXD_SAI0_TXC_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_mux_mode_SHIFT)) & IOMUXD_SAI0_TXC_mux_mode_MASK)
59477#define IOMUXD_SAI0_TXC_update_pad_ctl_MASK (0x40000000U)
59478#define IOMUXD_SAI0_TXC_update_pad_ctl_SHIFT (30U)
59479/*! update_pad_ctl - update lock for pad control
59480 */
59481#define IOMUXD_SAI0_TXC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_update_pad_ctl_SHIFT)) & IOMUXD_SAI0_TXC_update_pad_ctl_MASK)
59482#define IOMUXD_SAI0_TXC_update_mux_mode_MASK (0x80000000U)
59483#define IOMUXD_SAI0_TXC_update_mux_mode_SHIFT (31U)
59484/*! update_mux_mode - update lock for mux control
59485 */
59486#define IOMUXD_SAI0_TXC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXC_update_mux_mode_SHIFT)) & IOMUXD_SAI0_TXC_update_mux_mode_MASK)
59487/*! @} */
59488
59489/*! @name SAI0_RXD - SAI0_RXD */
59490/*! @{ */
59491#define IOMUXD_SAI0_RXD_PDRV_MASK (0x1U)
59492#define IOMUXD_SAI0_RXD_PDRV_SHIFT (0U)
59493/*! PDRV - Drive
59494 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59495 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59496 */
59497#define IOMUXD_SAI0_RXD_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_PDRV_SHIFT)) & IOMUXD_SAI0_RXD_PDRV_MASK)
59498#define IOMUXD_SAI0_RXD_SAI0_RXD_reserved_1_4_MASK (0x1EU)
59499#define IOMUXD_SAI0_RXD_SAI0_RXD_reserved_1_4_SHIFT (1U)
59500/*! SAI0_RXD_reserved_1_4 - reserved
59501 */
59502#define IOMUXD_SAI0_RXD_SAI0_RXD_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_SAI0_RXD_reserved_1_4_SHIFT)) & IOMUXD_SAI0_RXD_SAI0_RXD_reserved_1_4_MASK)
59503#define IOMUXD_SAI0_RXD_PULL_MASK (0x60U)
59504#define IOMUXD_SAI0_RXD_PULL_SHIFT (5U)
59505/*! PULL - Pull Down Pull Up
59506 * 0b10..pull down
59507 * 0b01..pull up
59508 * 0b00..Prohibited
59509 * 0b11..pull disabled
59510 */
59511#define IOMUXD_SAI0_RXD_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_PULL_SHIFT)) & IOMUXD_SAI0_RXD_PULL_MASK)
59512#define IOMUXD_SAI0_RXD_SAI0_RXD_reserved_7_18_MASK (0x7FF80U)
59513#define IOMUXD_SAI0_RXD_SAI0_RXD_reserved_7_18_SHIFT (7U)
59514/*! SAI0_RXD_reserved_7_18 - reserved
59515 */
59516#define IOMUXD_SAI0_RXD_SAI0_RXD_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_SAI0_RXD_reserved_7_18_SHIFT)) & IOMUXD_SAI0_RXD_SAI0_RXD_reserved_7_18_MASK)
59517#define IOMUXD_SAI0_RXD_WAKEUP_CTRL_MASK (0x380000U)
59518#define IOMUXD_SAI0_RXD_WAKEUP_CTRL_SHIFT (19U)
59519/*! WAKEUP_CTRL - wakeup control
59520 * 0b000..OFF
59521 * 0b001..RESAMPLE
59522 * 0b100..LOW
59523 * 0b111..HIGH
59524 * 0b110..RISE
59525 * 0b101..FALL
59526 */
59527#define IOMUXD_SAI0_RXD_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI0_RXD_WAKEUP_CTRL_MASK)
59528#define IOMUXD_SAI0_RXD_WAKEUP_MASK_MASK (0x400000U)
59529#define IOMUXD_SAI0_RXD_WAKEUP_MASK_SHIFT (22U)
59530/*! WAKEUP_MASK - wakeup mask
59531 */
59532#define IOMUXD_SAI0_RXD_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI0_RXD_WAKEUP_MASK_MASK)
59533#define IOMUXD_SAI0_RXD_lp_config_MASK (0x1800000U)
59534#define IOMUXD_SAI0_RXD_lp_config_SHIFT (23U)
59535/*! lp_config - lower power configuration
59536 * 0b01..EARLY_ISO
59537 * 0b10..LATE_ISO
59538 * 0b11..LATCH
59539 * 0b00..PASS
59540 */
59541#define IOMUXD_SAI0_RXD_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_lp_config_SHIFT)) & IOMUXD_SAI0_RXD_lp_config_MASK)
59542#define IOMUXD_SAI0_RXD_sw_config_MASK (0x6000000U)
59543#define IOMUXD_SAI0_RXD_sw_config_SHIFT (25U)
59544/*! sw_config - output and input configuration
59545 * 0b01..OPEN_DRAIN
59546 * 0b10..OPEN_DRAIN_INPUT
59547 * 0b11..INOUT
59548 * 0b00..DEFAULT
59549 */
59550#define IOMUXD_SAI0_RXD_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_sw_config_SHIFT)) & IOMUXD_SAI0_RXD_sw_config_MASK)
59551#define IOMUXD_SAI0_RXD_mux_mode_MASK (0x38000000U)
59552#define IOMUXD_SAI0_RXD_mux_mode_SHIFT (27U)
59553/*! mux_mode - mux_mode
59554 * 0b000..ADMA.SAI0.RXD
59555 * 0b001..ADMA.SAI1.RXFS
59556 * 0b010..ADMA.SPI1.CS0
59557 * 0b011..ADMA.LCDIF.D20
59558 * 0b100..LSIO.GPIO0.IO27
59559 */
59560#define IOMUXD_SAI0_RXD_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_mux_mode_SHIFT)) & IOMUXD_SAI0_RXD_mux_mode_MASK)
59561#define IOMUXD_SAI0_RXD_update_pad_ctl_MASK (0x40000000U)
59562#define IOMUXD_SAI0_RXD_update_pad_ctl_SHIFT (30U)
59563/*! update_pad_ctl - update lock for pad control
59564 */
59565#define IOMUXD_SAI0_RXD_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_update_pad_ctl_SHIFT)) & IOMUXD_SAI0_RXD_update_pad_ctl_MASK)
59566#define IOMUXD_SAI0_RXD_update_mux_mode_MASK (0x80000000U)
59567#define IOMUXD_SAI0_RXD_update_mux_mode_SHIFT (31U)
59568/*! update_mux_mode - update lock for mux control
59569 */
59570#define IOMUXD_SAI0_RXD_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_RXD_update_mux_mode_SHIFT)) & IOMUXD_SAI0_RXD_update_mux_mode_MASK)
59571/*! @} */
59572
59573/*! @name SAI0_TXFS - SAI0_TXFS */
59574/*! @{ */
59575#define IOMUXD_SAI0_TXFS_PDRV_MASK (0x1U)
59576#define IOMUXD_SAI0_TXFS_PDRV_SHIFT (0U)
59577/*! PDRV - Drive
59578 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59579 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59580 */
59581#define IOMUXD_SAI0_TXFS_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_PDRV_SHIFT)) & IOMUXD_SAI0_TXFS_PDRV_MASK)
59582#define IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_1_4_MASK (0x1EU)
59583#define IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_1_4_SHIFT (1U)
59584/*! SAI0_TXFS_reserved_1_4 - reserved
59585 */
59586#define IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_1_4_SHIFT)) & IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_1_4_MASK)
59587#define IOMUXD_SAI0_TXFS_PULL_MASK (0x60U)
59588#define IOMUXD_SAI0_TXFS_PULL_SHIFT (5U)
59589/*! PULL - Pull Down Pull Up
59590 * 0b10..pull down
59591 * 0b01..pull up
59592 * 0b00..Prohibited
59593 * 0b11..pull disabled
59594 */
59595#define IOMUXD_SAI0_TXFS_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_PULL_SHIFT)) & IOMUXD_SAI0_TXFS_PULL_MASK)
59596#define IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_7_18_MASK (0x7FF80U)
59597#define IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_7_18_SHIFT (7U)
59598/*! SAI0_TXFS_reserved_7_18 - reserved
59599 */
59600#define IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_7_18_SHIFT)) & IOMUXD_SAI0_TXFS_SAI0_TXFS_reserved_7_18_MASK)
59601#define IOMUXD_SAI0_TXFS_WAKEUP_CTRL_MASK (0x380000U)
59602#define IOMUXD_SAI0_TXFS_WAKEUP_CTRL_SHIFT (19U)
59603/*! WAKEUP_CTRL - wakeup control
59604 * 0b000..OFF
59605 * 0b001..RESAMPLE
59606 * 0b100..LOW
59607 * 0b111..HIGH
59608 * 0b110..RISE
59609 * 0b101..FALL
59610 */
59611#define IOMUXD_SAI0_TXFS_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI0_TXFS_WAKEUP_CTRL_MASK)
59612#define IOMUXD_SAI0_TXFS_WAKEUP_MASK_MASK (0x400000U)
59613#define IOMUXD_SAI0_TXFS_WAKEUP_MASK_SHIFT (22U)
59614/*! WAKEUP_MASK - wakeup mask
59615 */
59616#define IOMUXD_SAI0_TXFS_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI0_TXFS_WAKEUP_MASK_MASK)
59617#define IOMUXD_SAI0_TXFS_lp_config_MASK (0x1800000U)
59618#define IOMUXD_SAI0_TXFS_lp_config_SHIFT (23U)
59619/*! lp_config - lower power configuration
59620 * 0b01..EARLY_ISO
59621 * 0b10..LATE_ISO
59622 * 0b11..LATCH
59623 * 0b00..PASS
59624 */
59625#define IOMUXD_SAI0_TXFS_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_lp_config_SHIFT)) & IOMUXD_SAI0_TXFS_lp_config_MASK)
59626#define IOMUXD_SAI0_TXFS_sw_config_MASK (0x6000000U)
59627#define IOMUXD_SAI0_TXFS_sw_config_SHIFT (25U)
59628/*! sw_config - output and input configuration
59629 * 0b01..OPEN_DRAIN
59630 * 0b10..OPEN_DRAIN_INPUT
59631 * 0b11..INOUT
59632 * 0b00..DEFAULT
59633 */
59634#define IOMUXD_SAI0_TXFS_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_sw_config_SHIFT)) & IOMUXD_SAI0_TXFS_sw_config_MASK)
59635#define IOMUXD_SAI0_TXFS_mux_mode_MASK (0x38000000U)
59636#define IOMUXD_SAI0_TXFS_mux_mode_SHIFT (27U)
59637/*! mux_mode - mux_mode
59638 * 0b000..ADMA.SAI0.TXFS
59639 * 0b001..ADMA.SPI2.CS1
59640 * 0b010..ADMA.SPI1.SCK
59641 * 0b100..LSIO.GPIO0.IO28
59642 */
59643#define IOMUXD_SAI0_TXFS_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_mux_mode_SHIFT)) & IOMUXD_SAI0_TXFS_mux_mode_MASK)
59644#define IOMUXD_SAI0_TXFS_update_pad_ctl_MASK (0x40000000U)
59645#define IOMUXD_SAI0_TXFS_update_pad_ctl_SHIFT (30U)
59646/*! update_pad_ctl - update lock for pad control
59647 */
59648#define IOMUXD_SAI0_TXFS_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_update_pad_ctl_SHIFT)) & IOMUXD_SAI0_TXFS_update_pad_ctl_MASK)
59649#define IOMUXD_SAI0_TXFS_update_mux_mode_MASK (0x80000000U)
59650#define IOMUXD_SAI0_TXFS_update_mux_mode_SHIFT (31U)
59651/*! update_mux_mode - update lock for mux control
59652 */
59653#define IOMUXD_SAI0_TXFS_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI0_TXFS_update_mux_mode_SHIFT)) & IOMUXD_SAI0_TXFS_update_mux_mode_MASK)
59654/*! @} */
59655
59656/*! @name SAI1_RXD - SAI1_RXD */
59657/*! @{ */
59658#define IOMUXD_SAI1_RXD_PDRV_MASK (0x1U)
59659#define IOMUXD_SAI1_RXD_PDRV_SHIFT (0U)
59660/*! PDRV - Drive
59661 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59662 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59663 */
59664#define IOMUXD_SAI1_RXD_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_PDRV_SHIFT)) & IOMUXD_SAI1_RXD_PDRV_MASK)
59665#define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_1_4_MASK (0x1EU)
59666#define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_1_4_SHIFT (1U)
59667/*! SAI1_RXD_reserved_1_4 - reserved
59668 */
59669#define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_SAI1_RXD_reserved_1_4_SHIFT)) & IOMUXD_SAI1_RXD_SAI1_RXD_reserved_1_4_MASK)
59670#define IOMUXD_SAI1_RXD_PULL_MASK (0x60U)
59671#define IOMUXD_SAI1_RXD_PULL_SHIFT (5U)
59672/*! PULL - Pull Down Pull Up
59673 * 0b10..pull down
59674 * 0b01..pull up
59675 * 0b00..Prohibited
59676 * 0b11..pull disabled
59677 */
59678#define IOMUXD_SAI1_RXD_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_PULL_SHIFT)) & IOMUXD_SAI1_RXD_PULL_MASK)
59679#define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_7_18_MASK (0x7FF80U)
59680#define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_7_18_SHIFT (7U)
59681/*! SAI1_RXD_reserved_7_18 - reserved
59682 */
59683#define IOMUXD_SAI1_RXD_SAI1_RXD_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_SAI1_RXD_reserved_7_18_SHIFT)) & IOMUXD_SAI1_RXD_SAI1_RXD_reserved_7_18_MASK)
59684#define IOMUXD_SAI1_RXD_WAKEUP_CTRL_MASK (0x380000U)
59685#define IOMUXD_SAI1_RXD_WAKEUP_CTRL_SHIFT (19U)
59686/*! WAKEUP_CTRL - wakeup control
59687 * 0b000..OFF
59688 * 0b001..RESAMPLE
59689 * 0b100..LOW
59690 * 0b111..HIGH
59691 * 0b110..RISE
59692 * 0b101..FALL
59693 */
59694#define IOMUXD_SAI1_RXD_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI1_RXD_WAKEUP_CTRL_MASK)
59695#define IOMUXD_SAI1_RXD_WAKEUP_MASK_MASK (0x400000U)
59696#define IOMUXD_SAI1_RXD_WAKEUP_MASK_SHIFT (22U)
59697/*! WAKEUP_MASK - wakeup mask
59698 */
59699#define IOMUXD_SAI1_RXD_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI1_RXD_WAKEUP_MASK_MASK)
59700#define IOMUXD_SAI1_RXD_lp_config_MASK (0x1800000U)
59701#define IOMUXD_SAI1_RXD_lp_config_SHIFT (23U)
59702/*! lp_config - lower power configuration
59703 * 0b01..EARLY_ISO
59704 * 0b10..LATE_ISO
59705 * 0b11..LATCH
59706 * 0b00..PASS
59707 */
59708#define IOMUXD_SAI1_RXD_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_lp_config_SHIFT)) & IOMUXD_SAI1_RXD_lp_config_MASK)
59709#define IOMUXD_SAI1_RXD_sw_config_MASK (0x6000000U)
59710#define IOMUXD_SAI1_RXD_sw_config_SHIFT (25U)
59711/*! sw_config - output and input configuration
59712 * 0b01..OPEN_DRAIN
59713 * 0b10..OPEN_DRAIN_INPUT
59714 * 0b11..INOUT
59715 * 0b00..DEFAULT
59716 */
59717#define IOMUXD_SAI1_RXD_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_sw_config_SHIFT)) & IOMUXD_SAI1_RXD_sw_config_MASK)
59718#define IOMUXD_SAI1_RXD_mux_mode_MASK (0x38000000U)
59719#define IOMUXD_SAI1_RXD_mux_mode_SHIFT (27U)
59720/*! mux_mode - mux_mode
59721 * 0b000..ADMA.SAI1.RXD
59722 * 0b001..ADMA.SAI0.RXFS
59723 * 0b010..ADMA.SPI1.CS1
59724 * 0b011..ADMA.LCDIF.D21
59725 * 0b100..LSIO.GPIO0.IO29
59726 */
59727#define IOMUXD_SAI1_RXD_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_mux_mode_SHIFT)) & IOMUXD_SAI1_RXD_mux_mode_MASK)
59728#define IOMUXD_SAI1_RXD_update_pad_ctl_MASK (0x40000000U)
59729#define IOMUXD_SAI1_RXD_update_pad_ctl_SHIFT (30U)
59730/*! update_pad_ctl - update lock for pad control
59731 */
59732#define IOMUXD_SAI1_RXD_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_update_pad_ctl_SHIFT)) & IOMUXD_SAI1_RXD_update_pad_ctl_MASK)
59733#define IOMUXD_SAI1_RXD_update_mux_mode_MASK (0x80000000U)
59734#define IOMUXD_SAI1_RXD_update_mux_mode_SHIFT (31U)
59735/*! update_mux_mode - update lock for mux control
59736 */
59737#define IOMUXD_SAI1_RXD_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXD_update_mux_mode_SHIFT)) & IOMUXD_SAI1_RXD_update_mux_mode_MASK)
59738/*! @} */
59739
59740/*! @name SAI1_RXC - SAI1_RXC */
59741/*! @{ */
59742#define IOMUXD_SAI1_RXC_PDRV_MASK (0x1U)
59743#define IOMUXD_SAI1_RXC_PDRV_SHIFT (0U)
59744/*! PDRV - Drive
59745 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59746 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59747 */
59748#define IOMUXD_SAI1_RXC_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_PDRV_SHIFT)) & IOMUXD_SAI1_RXC_PDRV_MASK)
59749#define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_1_4_MASK (0x1EU)
59750#define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_1_4_SHIFT (1U)
59751/*! SAI1_RXC_reserved_1_4 - reserved
59752 */
59753#define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_SAI1_RXC_reserved_1_4_SHIFT)) & IOMUXD_SAI1_RXC_SAI1_RXC_reserved_1_4_MASK)
59754#define IOMUXD_SAI1_RXC_PULL_MASK (0x60U)
59755#define IOMUXD_SAI1_RXC_PULL_SHIFT (5U)
59756/*! PULL - Pull Down Pull Up
59757 * 0b10..pull down
59758 * 0b01..pull up
59759 * 0b00..Prohibited
59760 * 0b11..pull disabled
59761 */
59762#define IOMUXD_SAI1_RXC_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_PULL_SHIFT)) & IOMUXD_SAI1_RXC_PULL_MASK)
59763#define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_7_18_MASK (0x7FF80U)
59764#define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_7_18_SHIFT (7U)
59765/*! SAI1_RXC_reserved_7_18 - reserved
59766 */
59767#define IOMUXD_SAI1_RXC_SAI1_RXC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_SAI1_RXC_reserved_7_18_SHIFT)) & IOMUXD_SAI1_RXC_SAI1_RXC_reserved_7_18_MASK)
59768#define IOMUXD_SAI1_RXC_WAKEUP_CTRL_MASK (0x380000U)
59769#define IOMUXD_SAI1_RXC_WAKEUP_CTRL_SHIFT (19U)
59770/*! WAKEUP_CTRL - wakeup control
59771 * 0b000..OFF
59772 * 0b001..RESAMPLE
59773 * 0b100..LOW
59774 * 0b111..HIGH
59775 * 0b110..RISE
59776 * 0b101..FALL
59777 */
59778#define IOMUXD_SAI1_RXC_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI1_RXC_WAKEUP_CTRL_MASK)
59779#define IOMUXD_SAI1_RXC_WAKEUP_MASK_MASK (0x400000U)
59780#define IOMUXD_SAI1_RXC_WAKEUP_MASK_SHIFT (22U)
59781/*! WAKEUP_MASK - wakeup mask
59782 */
59783#define IOMUXD_SAI1_RXC_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI1_RXC_WAKEUP_MASK_MASK)
59784#define IOMUXD_SAI1_RXC_lp_config_MASK (0x1800000U)
59785#define IOMUXD_SAI1_RXC_lp_config_SHIFT (23U)
59786/*! lp_config - lower power configuration
59787 * 0b01..EARLY_ISO
59788 * 0b10..LATE_ISO
59789 * 0b11..LATCH
59790 * 0b00..PASS
59791 */
59792#define IOMUXD_SAI1_RXC_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_lp_config_SHIFT)) & IOMUXD_SAI1_RXC_lp_config_MASK)
59793#define IOMUXD_SAI1_RXC_sw_config_MASK (0x6000000U)
59794#define IOMUXD_SAI1_RXC_sw_config_SHIFT (25U)
59795/*! sw_config - output and input configuration
59796 * 0b01..OPEN_DRAIN
59797 * 0b10..OPEN_DRAIN_INPUT
59798 * 0b11..INOUT
59799 * 0b00..DEFAULT
59800 */
59801#define IOMUXD_SAI1_RXC_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_sw_config_SHIFT)) & IOMUXD_SAI1_RXC_sw_config_MASK)
59802#define IOMUXD_SAI1_RXC_mux_mode_MASK (0x38000000U)
59803#define IOMUXD_SAI1_RXC_mux_mode_SHIFT (27U)
59804/*! mux_mode - mux_mode
59805 * 0b000..ADMA.SAI1.RXC
59806 * 0b001..ADMA.SAI1.TXC
59807 * 0b011..ADMA.LCDIF.D22
59808 * 0b100..LSIO.GPIO0.IO30
59809 */
59810#define IOMUXD_SAI1_RXC_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_mux_mode_SHIFT)) & IOMUXD_SAI1_RXC_mux_mode_MASK)
59811#define IOMUXD_SAI1_RXC_update_pad_ctl_MASK (0x40000000U)
59812#define IOMUXD_SAI1_RXC_update_pad_ctl_SHIFT (30U)
59813/*! update_pad_ctl - update lock for pad control
59814 */
59815#define IOMUXD_SAI1_RXC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_update_pad_ctl_SHIFT)) & IOMUXD_SAI1_RXC_update_pad_ctl_MASK)
59816#define IOMUXD_SAI1_RXC_update_mux_mode_MASK (0x80000000U)
59817#define IOMUXD_SAI1_RXC_update_mux_mode_SHIFT (31U)
59818/*! update_mux_mode - update lock for mux control
59819 */
59820#define IOMUXD_SAI1_RXC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXC_update_mux_mode_SHIFT)) & IOMUXD_SAI1_RXC_update_mux_mode_MASK)
59821/*! @} */
59822
59823/*! @name SAI1_RXFS - SAI1_RXFS */
59824/*! @{ */
59825#define IOMUXD_SAI1_RXFS_PDRV_MASK (0x1U)
59826#define IOMUXD_SAI1_RXFS_PDRV_SHIFT (0U)
59827/*! PDRV - Drive
59828 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59829 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59830 */
59831#define IOMUXD_SAI1_RXFS_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_PDRV_SHIFT)) & IOMUXD_SAI1_RXFS_PDRV_MASK)
59832#define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_1_4_MASK (0x1EU)
59833#define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_1_4_SHIFT (1U)
59834/*! SAI1_RXFS_reserved_1_4 - reserved
59835 */
59836#define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_1_4_SHIFT)) & IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_1_4_MASK)
59837#define IOMUXD_SAI1_RXFS_PULL_MASK (0x60U)
59838#define IOMUXD_SAI1_RXFS_PULL_SHIFT (5U)
59839/*! PULL - Pull Down Pull Up
59840 * 0b10..pull down
59841 * 0b01..pull up
59842 * 0b00..Prohibited
59843 * 0b11..pull disabled
59844 */
59845#define IOMUXD_SAI1_RXFS_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_PULL_SHIFT)) & IOMUXD_SAI1_RXFS_PULL_MASK)
59846#define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_7_18_MASK (0x7FF80U)
59847#define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_7_18_SHIFT (7U)
59848/*! SAI1_RXFS_reserved_7_18 - reserved
59849 */
59850#define IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_7_18_SHIFT)) & IOMUXD_SAI1_RXFS_SAI1_RXFS_reserved_7_18_MASK)
59851#define IOMUXD_SAI1_RXFS_WAKEUP_CTRL_MASK (0x380000U)
59852#define IOMUXD_SAI1_RXFS_WAKEUP_CTRL_SHIFT (19U)
59853/*! WAKEUP_CTRL - wakeup control
59854 * 0b000..OFF
59855 * 0b001..RESAMPLE
59856 * 0b100..LOW
59857 * 0b111..HIGH
59858 * 0b110..RISE
59859 * 0b101..FALL
59860 */
59861#define IOMUXD_SAI1_RXFS_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_WAKEUP_CTRL_SHIFT)) & IOMUXD_SAI1_RXFS_WAKEUP_CTRL_MASK)
59862#define IOMUXD_SAI1_RXFS_WAKEUP_MASK_MASK (0x400000U)
59863#define IOMUXD_SAI1_RXFS_WAKEUP_MASK_SHIFT (22U)
59864/*! WAKEUP_MASK - wakeup mask
59865 */
59866#define IOMUXD_SAI1_RXFS_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_WAKEUP_MASK_SHIFT)) & IOMUXD_SAI1_RXFS_WAKEUP_MASK_MASK)
59867#define IOMUXD_SAI1_RXFS_lp_config_MASK (0x1800000U)
59868#define IOMUXD_SAI1_RXFS_lp_config_SHIFT (23U)
59869/*! lp_config - lower power configuration
59870 * 0b01..EARLY_ISO
59871 * 0b10..LATE_ISO
59872 * 0b11..LATCH
59873 * 0b00..PASS
59874 */
59875#define IOMUXD_SAI1_RXFS_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_lp_config_SHIFT)) & IOMUXD_SAI1_RXFS_lp_config_MASK)
59876#define IOMUXD_SAI1_RXFS_sw_config_MASK (0x6000000U)
59877#define IOMUXD_SAI1_RXFS_sw_config_SHIFT (25U)
59878/*! sw_config - output and input configuration
59879 * 0b01..OPEN_DRAIN
59880 * 0b10..OPEN_DRAIN_INPUT
59881 * 0b11..INOUT
59882 * 0b00..DEFAULT
59883 */
59884#define IOMUXD_SAI1_RXFS_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_sw_config_SHIFT)) & IOMUXD_SAI1_RXFS_sw_config_MASK)
59885#define IOMUXD_SAI1_RXFS_mux_mode_MASK (0x38000000U)
59886#define IOMUXD_SAI1_RXFS_mux_mode_SHIFT (27U)
59887/*! mux_mode - mux_mode
59888 * 0b000..ADMA.SAI1.RXFS
59889 * 0b001..ADMA.SAI1.TXFS
59890 * 0b011..ADMA.LCDIF.D23
59891 * 0b100..LSIO.GPIO0.IO31
59892 */
59893#define IOMUXD_SAI1_RXFS_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_mux_mode_SHIFT)) & IOMUXD_SAI1_RXFS_mux_mode_MASK)
59894#define IOMUXD_SAI1_RXFS_update_pad_ctl_MASK (0x40000000U)
59895#define IOMUXD_SAI1_RXFS_update_pad_ctl_SHIFT (30U)
59896/*! update_pad_ctl - update lock for pad control
59897 */
59898#define IOMUXD_SAI1_RXFS_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_update_pad_ctl_SHIFT)) & IOMUXD_SAI1_RXFS_update_pad_ctl_MASK)
59899#define IOMUXD_SAI1_RXFS_update_mux_mode_MASK (0x80000000U)
59900#define IOMUXD_SAI1_RXFS_update_mux_mode_SHIFT (31U)
59901/*! update_mux_mode - update lock for mux control
59902 */
59903#define IOMUXD_SAI1_RXFS_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SAI1_RXFS_update_mux_mode_SHIFT)) & IOMUXD_SAI1_RXFS_update_mux_mode_MASK)
59904/*! @} */
59905
59906/*! @name SPI2_CS0 - SPI2_CS0 */
59907/*! @{ */
59908#define IOMUXD_SPI2_CS0_PDRV_MASK (0x1U)
59909#define IOMUXD_SPI2_CS0_PDRV_SHIFT (0U)
59910/*! PDRV - Drive
59911 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59912 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59913 */
59914#define IOMUXD_SPI2_CS0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_PDRV_SHIFT)) & IOMUXD_SPI2_CS0_PDRV_MASK)
59915#define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_1_4_MASK (0x1EU)
59916#define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_1_4_SHIFT (1U)
59917/*! SPI2_CS0_reserved_1_4 - reserved
59918 */
59919#define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_SPI2_CS0_reserved_1_4_SHIFT)) & IOMUXD_SPI2_CS0_SPI2_CS0_reserved_1_4_MASK)
59920#define IOMUXD_SPI2_CS0_PULL_MASK (0x60U)
59921#define IOMUXD_SPI2_CS0_PULL_SHIFT (5U)
59922/*! PULL - Pull Down Pull Up
59923 * 0b10..pull down
59924 * 0b01..pull up
59925 * 0b00..Prohibited
59926 * 0b11..pull disabled
59927 */
59928#define IOMUXD_SPI2_CS0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_PULL_SHIFT)) & IOMUXD_SPI2_CS0_PULL_MASK)
59929#define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_7_18_MASK (0x7FF80U)
59930#define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_7_18_SHIFT (7U)
59931/*! SPI2_CS0_reserved_7_18 - reserved
59932 */
59933#define IOMUXD_SPI2_CS0_SPI2_CS0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_SPI2_CS0_reserved_7_18_SHIFT)) & IOMUXD_SPI2_CS0_SPI2_CS0_reserved_7_18_MASK)
59934#define IOMUXD_SPI2_CS0_WAKEUP_CTRL_MASK (0x380000U)
59935#define IOMUXD_SPI2_CS0_WAKEUP_CTRL_SHIFT (19U)
59936/*! WAKEUP_CTRL - wakeup control
59937 * 0b000..OFF
59938 * 0b001..RESAMPLE
59939 * 0b100..LOW
59940 * 0b111..HIGH
59941 * 0b110..RISE
59942 * 0b101..FALL
59943 */
59944#define IOMUXD_SPI2_CS0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI2_CS0_WAKEUP_CTRL_MASK)
59945#define IOMUXD_SPI2_CS0_WAKEUP_MASK_MASK (0x400000U)
59946#define IOMUXD_SPI2_CS0_WAKEUP_MASK_SHIFT (22U)
59947/*! WAKEUP_MASK - wakeup mask
59948 */
59949#define IOMUXD_SPI2_CS0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI2_CS0_WAKEUP_MASK_MASK)
59950#define IOMUXD_SPI2_CS0_lp_config_MASK (0x1800000U)
59951#define IOMUXD_SPI2_CS0_lp_config_SHIFT (23U)
59952/*! lp_config - lower power configuration
59953 * 0b01..EARLY_ISO
59954 * 0b10..LATE_ISO
59955 * 0b11..LATCH
59956 * 0b00..PASS
59957 */
59958#define IOMUXD_SPI2_CS0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_lp_config_SHIFT)) & IOMUXD_SPI2_CS0_lp_config_MASK)
59959#define IOMUXD_SPI2_CS0_sw_config_MASK (0x6000000U)
59960#define IOMUXD_SPI2_CS0_sw_config_SHIFT (25U)
59961/*! sw_config - output and input configuration
59962 * 0b01..OPEN_DRAIN
59963 * 0b10..OPEN_DRAIN_INPUT
59964 * 0b11..INOUT
59965 * 0b00..DEFAULT
59966 */
59967#define IOMUXD_SPI2_CS0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_sw_config_SHIFT)) & IOMUXD_SPI2_CS0_sw_config_MASK)
59968#define IOMUXD_SPI2_CS0_mux_mode_MASK (0x38000000U)
59969#define IOMUXD_SPI2_CS0_mux_mode_SHIFT (27U)
59970/*! mux_mode - mux_mode
59971 * 0b000..ADMA.SPI2.CS0
59972 * 0b100..LSIO.GPIO1.IO00
59973 */
59974#define IOMUXD_SPI2_CS0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_mux_mode_SHIFT)) & IOMUXD_SPI2_CS0_mux_mode_MASK)
59975#define IOMUXD_SPI2_CS0_update_pad_ctl_MASK (0x40000000U)
59976#define IOMUXD_SPI2_CS0_update_pad_ctl_SHIFT (30U)
59977/*! update_pad_ctl - update lock for pad control
59978 */
59979#define IOMUXD_SPI2_CS0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_update_pad_ctl_SHIFT)) & IOMUXD_SPI2_CS0_update_pad_ctl_MASK)
59980#define IOMUXD_SPI2_CS0_update_mux_mode_MASK (0x80000000U)
59981#define IOMUXD_SPI2_CS0_update_mux_mode_SHIFT (31U)
59982/*! update_mux_mode - update lock for mux control
59983 */
59984#define IOMUXD_SPI2_CS0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_CS0_update_mux_mode_SHIFT)) & IOMUXD_SPI2_CS0_update_mux_mode_MASK)
59985/*! @} */
59986
59987/*! @name SPI2_SDO - SPI2_SDO */
59988/*! @{ */
59989#define IOMUXD_SPI2_SDO_PDRV_MASK (0x1U)
59990#define IOMUXD_SPI2_SDO_PDRV_SHIFT (0U)
59991/*! PDRV - Drive
59992 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
59993 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
59994 */
59995#define IOMUXD_SPI2_SDO_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_PDRV_SHIFT)) & IOMUXD_SPI2_SDO_PDRV_MASK)
59996#define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_1_4_MASK (0x1EU)
59997#define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_1_4_SHIFT (1U)
59998/*! SPI2_SDO_reserved_1_4 - reserved
59999 */
60000#define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_SPI2_SDO_reserved_1_4_SHIFT)) & IOMUXD_SPI2_SDO_SPI2_SDO_reserved_1_4_MASK)
60001#define IOMUXD_SPI2_SDO_PULL_MASK (0x60U)
60002#define IOMUXD_SPI2_SDO_PULL_SHIFT (5U)
60003/*! PULL - Pull Down Pull Up
60004 * 0b10..pull down
60005 * 0b01..pull up
60006 * 0b00..Prohibited
60007 * 0b11..pull disabled
60008 */
60009#define IOMUXD_SPI2_SDO_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_PULL_SHIFT)) & IOMUXD_SPI2_SDO_PULL_MASK)
60010#define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_7_18_MASK (0x7FF80U)
60011#define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_7_18_SHIFT (7U)
60012/*! SPI2_SDO_reserved_7_18 - reserved
60013 */
60014#define IOMUXD_SPI2_SDO_SPI2_SDO_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_SPI2_SDO_reserved_7_18_SHIFT)) & IOMUXD_SPI2_SDO_SPI2_SDO_reserved_7_18_MASK)
60015#define IOMUXD_SPI2_SDO_WAKEUP_CTRL_MASK (0x380000U)
60016#define IOMUXD_SPI2_SDO_WAKEUP_CTRL_SHIFT (19U)
60017/*! WAKEUP_CTRL - wakeup control
60018 * 0b000..OFF
60019 * 0b001..RESAMPLE
60020 * 0b100..LOW
60021 * 0b111..HIGH
60022 * 0b110..RISE
60023 * 0b101..FALL
60024 */
60025#define IOMUXD_SPI2_SDO_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI2_SDO_WAKEUP_CTRL_MASK)
60026#define IOMUXD_SPI2_SDO_WAKEUP_MASK_MASK (0x400000U)
60027#define IOMUXD_SPI2_SDO_WAKEUP_MASK_SHIFT (22U)
60028/*! WAKEUP_MASK - wakeup mask
60029 */
60030#define IOMUXD_SPI2_SDO_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI2_SDO_WAKEUP_MASK_MASK)
60031#define IOMUXD_SPI2_SDO_lp_config_MASK (0x1800000U)
60032#define IOMUXD_SPI2_SDO_lp_config_SHIFT (23U)
60033/*! lp_config - lower power configuration
60034 * 0b01..EARLY_ISO
60035 * 0b10..LATE_ISO
60036 * 0b11..LATCH
60037 * 0b00..PASS
60038 */
60039#define IOMUXD_SPI2_SDO_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_lp_config_SHIFT)) & IOMUXD_SPI2_SDO_lp_config_MASK)
60040#define IOMUXD_SPI2_SDO_sw_config_MASK (0x6000000U)
60041#define IOMUXD_SPI2_SDO_sw_config_SHIFT (25U)
60042/*! sw_config - output and input configuration
60043 * 0b01..OPEN_DRAIN
60044 * 0b10..OPEN_DRAIN_INPUT
60045 * 0b11..INOUT
60046 * 0b00..DEFAULT
60047 */
60048#define IOMUXD_SPI2_SDO_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_sw_config_SHIFT)) & IOMUXD_SPI2_SDO_sw_config_MASK)
60049#define IOMUXD_SPI2_SDO_mux_mode_MASK (0x38000000U)
60050#define IOMUXD_SPI2_SDO_mux_mode_SHIFT (27U)
60051/*! mux_mode - mux_mode
60052 * 0b000..ADMA.SPI2.SDO
60053 * 0b100..LSIO.GPIO1.IO01
60054 */
60055#define IOMUXD_SPI2_SDO_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_mux_mode_SHIFT)) & IOMUXD_SPI2_SDO_mux_mode_MASK)
60056#define IOMUXD_SPI2_SDO_update_pad_ctl_MASK (0x40000000U)
60057#define IOMUXD_SPI2_SDO_update_pad_ctl_SHIFT (30U)
60058/*! update_pad_ctl - update lock for pad control
60059 */
60060#define IOMUXD_SPI2_SDO_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_update_pad_ctl_SHIFT)) & IOMUXD_SPI2_SDO_update_pad_ctl_MASK)
60061#define IOMUXD_SPI2_SDO_update_mux_mode_MASK (0x80000000U)
60062#define IOMUXD_SPI2_SDO_update_mux_mode_SHIFT (31U)
60063/*! update_mux_mode - update lock for mux control
60064 */
60065#define IOMUXD_SPI2_SDO_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDO_update_mux_mode_SHIFT)) & IOMUXD_SPI2_SDO_update_mux_mode_MASK)
60066/*! @} */
60067
60068/*! @name SPI2_SDI - SPI2_SDI */
60069/*! @{ */
60070#define IOMUXD_SPI2_SDI_PDRV_MASK (0x1U)
60071#define IOMUXD_SPI2_SDI_PDRV_SHIFT (0U)
60072/*! PDRV - Drive
60073 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
60074 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
60075 */
60076#define IOMUXD_SPI2_SDI_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_PDRV_SHIFT)) & IOMUXD_SPI2_SDI_PDRV_MASK)
60077#define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_1_4_MASK (0x1EU)
60078#define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_1_4_SHIFT (1U)
60079/*! SPI2_SDI_reserved_1_4 - reserved
60080 */
60081#define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_SPI2_SDI_reserved_1_4_SHIFT)) & IOMUXD_SPI2_SDI_SPI2_SDI_reserved_1_4_MASK)
60082#define IOMUXD_SPI2_SDI_PULL_MASK (0x60U)
60083#define IOMUXD_SPI2_SDI_PULL_SHIFT (5U)
60084/*! PULL - Pull Down Pull Up
60085 * 0b10..pull down
60086 * 0b01..pull up
60087 * 0b00..Prohibited
60088 * 0b11..pull disabled
60089 */
60090#define IOMUXD_SPI2_SDI_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_PULL_SHIFT)) & IOMUXD_SPI2_SDI_PULL_MASK)
60091#define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_7_18_MASK (0x7FF80U)
60092#define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_7_18_SHIFT (7U)
60093/*! SPI2_SDI_reserved_7_18 - reserved
60094 */
60095#define IOMUXD_SPI2_SDI_SPI2_SDI_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_SPI2_SDI_reserved_7_18_SHIFT)) & IOMUXD_SPI2_SDI_SPI2_SDI_reserved_7_18_MASK)
60096#define IOMUXD_SPI2_SDI_WAKEUP_CTRL_MASK (0x380000U)
60097#define IOMUXD_SPI2_SDI_WAKEUP_CTRL_SHIFT (19U)
60098/*! WAKEUP_CTRL - wakeup control
60099 * 0b000..OFF
60100 * 0b001..RESAMPLE
60101 * 0b100..LOW
60102 * 0b111..HIGH
60103 * 0b110..RISE
60104 * 0b101..FALL
60105 */
60106#define IOMUXD_SPI2_SDI_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI2_SDI_WAKEUP_CTRL_MASK)
60107#define IOMUXD_SPI2_SDI_WAKEUP_MASK_MASK (0x400000U)
60108#define IOMUXD_SPI2_SDI_WAKEUP_MASK_SHIFT (22U)
60109/*! WAKEUP_MASK - wakeup mask
60110 */
60111#define IOMUXD_SPI2_SDI_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI2_SDI_WAKEUP_MASK_MASK)
60112#define IOMUXD_SPI2_SDI_lp_config_MASK (0x1800000U)
60113#define IOMUXD_SPI2_SDI_lp_config_SHIFT (23U)
60114/*! lp_config - lower power configuration
60115 * 0b01..EARLY_ISO
60116 * 0b10..LATE_ISO
60117 * 0b11..LATCH
60118 * 0b00..PASS
60119 */
60120#define IOMUXD_SPI2_SDI_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_lp_config_SHIFT)) & IOMUXD_SPI2_SDI_lp_config_MASK)
60121#define IOMUXD_SPI2_SDI_sw_config_MASK (0x6000000U)
60122#define IOMUXD_SPI2_SDI_sw_config_SHIFT (25U)
60123/*! sw_config - output and input configuration
60124 * 0b01..OPEN_DRAIN
60125 * 0b10..OPEN_DRAIN_INPUT
60126 * 0b11..INOUT
60127 * 0b00..DEFAULT
60128 */
60129#define IOMUXD_SPI2_SDI_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_sw_config_SHIFT)) & IOMUXD_SPI2_SDI_sw_config_MASK)
60130#define IOMUXD_SPI2_SDI_mux_mode_MASK (0x38000000U)
60131#define IOMUXD_SPI2_SDI_mux_mode_SHIFT (27U)
60132/*! mux_mode - mux_mode
60133 * 0b000..ADMA.SPI2.SDI
60134 * 0b100..LSIO.GPIO1.IO02
60135 */
60136#define IOMUXD_SPI2_SDI_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_mux_mode_SHIFT)) & IOMUXD_SPI2_SDI_mux_mode_MASK)
60137#define IOMUXD_SPI2_SDI_update_pad_ctl_MASK (0x40000000U)
60138#define IOMUXD_SPI2_SDI_update_pad_ctl_SHIFT (30U)
60139/*! update_pad_ctl - update lock for pad control
60140 */
60141#define IOMUXD_SPI2_SDI_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_update_pad_ctl_SHIFT)) & IOMUXD_SPI2_SDI_update_pad_ctl_MASK)
60142#define IOMUXD_SPI2_SDI_update_mux_mode_MASK (0x80000000U)
60143#define IOMUXD_SPI2_SDI_update_mux_mode_SHIFT (31U)
60144/*! update_mux_mode - update lock for mux control
60145 */
60146#define IOMUXD_SPI2_SDI_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SDI_update_mux_mode_SHIFT)) & IOMUXD_SPI2_SDI_update_mux_mode_MASK)
60147/*! @} */
60148
60149/*! @name SPI2_SCK - SPI2_SCK */
60150/*! @{ */
60151#define IOMUXD_SPI2_SCK_PDRV_MASK (0x1U)
60152#define IOMUXD_SPI2_SCK_PDRV_SHIFT (0U)
60153/*! PDRV - Drive
60154 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
60155 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
60156 */
60157#define IOMUXD_SPI2_SCK_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_PDRV_SHIFT)) & IOMUXD_SPI2_SCK_PDRV_MASK)
60158#define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_1_4_MASK (0x1EU)
60159#define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_1_4_SHIFT (1U)
60160/*! SPI2_SCK_reserved_1_4 - reserved
60161 */
60162#define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_SPI2_SCK_reserved_1_4_SHIFT)) & IOMUXD_SPI2_SCK_SPI2_SCK_reserved_1_4_MASK)
60163#define IOMUXD_SPI2_SCK_PULL_MASK (0x60U)
60164#define IOMUXD_SPI2_SCK_PULL_SHIFT (5U)
60165/*! PULL - Pull Down Pull Up
60166 * 0b10..pull down
60167 * 0b01..pull up
60168 * 0b00..Prohibited
60169 * 0b11..pull disabled
60170 */
60171#define IOMUXD_SPI2_SCK_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_PULL_SHIFT)) & IOMUXD_SPI2_SCK_PULL_MASK)
60172#define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_7_18_MASK (0x7FF80U)
60173#define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_7_18_SHIFT (7U)
60174/*! SPI2_SCK_reserved_7_18 - reserved
60175 */
60176#define IOMUXD_SPI2_SCK_SPI2_SCK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_SPI2_SCK_reserved_7_18_SHIFT)) & IOMUXD_SPI2_SCK_SPI2_SCK_reserved_7_18_MASK)
60177#define IOMUXD_SPI2_SCK_WAKEUP_CTRL_MASK (0x380000U)
60178#define IOMUXD_SPI2_SCK_WAKEUP_CTRL_SHIFT (19U)
60179/*! WAKEUP_CTRL - wakeup control
60180 * 0b000..OFF
60181 * 0b001..RESAMPLE
60182 * 0b100..LOW
60183 * 0b111..HIGH
60184 * 0b110..RISE
60185 * 0b101..FALL
60186 */
60187#define IOMUXD_SPI2_SCK_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI2_SCK_WAKEUP_CTRL_MASK)
60188#define IOMUXD_SPI2_SCK_WAKEUP_MASK_MASK (0x400000U)
60189#define IOMUXD_SPI2_SCK_WAKEUP_MASK_SHIFT (22U)
60190/*! WAKEUP_MASK - wakeup mask
60191 */
60192#define IOMUXD_SPI2_SCK_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI2_SCK_WAKEUP_MASK_MASK)
60193#define IOMUXD_SPI2_SCK_lp_config_MASK (0x1800000U)
60194#define IOMUXD_SPI2_SCK_lp_config_SHIFT (23U)
60195/*! lp_config - lower power configuration
60196 * 0b01..EARLY_ISO
60197 * 0b10..LATE_ISO
60198 * 0b11..LATCH
60199 * 0b00..PASS
60200 */
60201#define IOMUXD_SPI2_SCK_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_lp_config_SHIFT)) & IOMUXD_SPI2_SCK_lp_config_MASK)
60202#define IOMUXD_SPI2_SCK_sw_config_MASK (0x6000000U)
60203#define IOMUXD_SPI2_SCK_sw_config_SHIFT (25U)
60204/*! sw_config - output and input configuration
60205 * 0b01..OPEN_DRAIN
60206 * 0b10..OPEN_DRAIN_INPUT
60207 * 0b11..INOUT
60208 * 0b00..DEFAULT
60209 */
60210#define IOMUXD_SPI2_SCK_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_sw_config_SHIFT)) & IOMUXD_SPI2_SCK_sw_config_MASK)
60211#define IOMUXD_SPI2_SCK_mux_mode_MASK (0x38000000U)
60212#define IOMUXD_SPI2_SCK_mux_mode_SHIFT (27U)
60213/*! mux_mode - mux_mode
60214 * 0b000..ADMA.SPI2.SCK
60215 * 0b100..LSIO.GPIO1.IO03
60216 */
60217#define IOMUXD_SPI2_SCK_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_mux_mode_SHIFT)) & IOMUXD_SPI2_SCK_mux_mode_MASK)
60218#define IOMUXD_SPI2_SCK_update_pad_ctl_MASK (0x40000000U)
60219#define IOMUXD_SPI2_SCK_update_pad_ctl_SHIFT (30U)
60220/*! update_pad_ctl - update lock for pad control
60221 */
60222#define IOMUXD_SPI2_SCK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_update_pad_ctl_SHIFT)) & IOMUXD_SPI2_SCK_update_pad_ctl_MASK)
60223#define IOMUXD_SPI2_SCK_update_mux_mode_MASK (0x80000000U)
60224#define IOMUXD_SPI2_SCK_update_mux_mode_SHIFT (31U)
60225/*! update_mux_mode - update lock for mux control
60226 */
60227#define IOMUXD_SPI2_SCK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI2_SCK_update_mux_mode_SHIFT)) & IOMUXD_SPI2_SCK_update_mux_mode_MASK)
60228/*! @} */
60229
60230/*! @name SPI0_SCK - SPI0_SCK */
60231/*! @{ */
60232#define IOMUXD_SPI0_SCK_PDRV_MASK (0x1U)
60233#define IOMUXD_SPI0_SCK_PDRV_SHIFT (0U)
60234/*! PDRV - Drive
60235 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
60236 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
60237 */
60238#define IOMUXD_SPI0_SCK_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_PDRV_SHIFT)) & IOMUXD_SPI0_SCK_PDRV_MASK)
60239#define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_1_4_MASK (0x1EU)
60240#define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_1_4_SHIFT (1U)
60241/*! SPI0_SCK_reserved_1_4 - reserved
60242 */
60243#define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_SPI0_SCK_reserved_1_4_SHIFT)) & IOMUXD_SPI0_SCK_SPI0_SCK_reserved_1_4_MASK)
60244#define IOMUXD_SPI0_SCK_PULL_MASK (0x60U)
60245#define IOMUXD_SPI0_SCK_PULL_SHIFT (5U)
60246/*! PULL - Pull Down Pull Up
60247 * 0b10..pull down
60248 * 0b01..pull up
60249 * 0b00..Prohibited
60250 * 0b11..pull disabled
60251 */
60252#define IOMUXD_SPI0_SCK_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_PULL_SHIFT)) & IOMUXD_SPI0_SCK_PULL_MASK)
60253#define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_7_18_MASK (0x7FF80U)
60254#define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_7_18_SHIFT (7U)
60255/*! SPI0_SCK_reserved_7_18 - reserved
60256 */
60257#define IOMUXD_SPI0_SCK_SPI0_SCK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_SPI0_SCK_reserved_7_18_SHIFT)) & IOMUXD_SPI0_SCK_SPI0_SCK_reserved_7_18_MASK)
60258#define IOMUXD_SPI0_SCK_WAKEUP_CTRL_MASK (0x380000U)
60259#define IOMUXD_SPI0_SCK_WAKEUP_CTRL_SHIFT (19U)
60260/*! WAKEUP_CTRL - wakeup control
60261 * 0b000..OFF
60262 * 0b001..RESAMPLE
60263 * 0b100..LOW
60264 * 0b111..HIGH
60265 * 0b110..RISE
60266 * 0b101..FALL
60267 */
60268#define IOMUXD_SPI0_SCK_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI0_SCK_WAKEUP_CTRL_MASK)
60269#define IOMUXD_SPI0_SCK_WAKEUP_MASK_MASK (0x400000U)
60270#define IOMUXD_SPI0_SCK_WAKEUP_MASK_SHIFT (22U)
60271/*! WAKEUP_MASK - wakeup mask
60272 */
60273#define IOMUXD_SPI0_SCK_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI0_SCK_WAKEUP_MASK_MASK)
60274#define IOMUXD_SPI0_SCK_lp_config_MASK (0x1800000U)
60275#define IOMUXD_SPI0_SCK_lp_config_SHIFT (23U)
60276/*! lp_config - lower power configuration
60277 * 0b01..EARLY_ISO
60278 * 0b10..LATE_ISO
60279 * 0b11..LATCH
60280 * 0b00..PASS
60281 */
60282#define IOMUXD_SPI0_SCK_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_lp_config_SHIFT)) & IOMUXD_SPI0_SCK_lp_config_MASK)
60283#define IOMUXD_SPI0_SCK_sw_config_MASK (0x6000000U)
60284#define IOMUXD_SPI0_SCK_sw_config_SHIFT (25U)
60285/*! sw_config - output and input configuration
60286 * 0b01..OPEN_DRAIN
60287 * 0b10..OPEN_DRAIN_INPUT
60288 * 0b11..INOUT
60289 * 0b00..DEFAULT
60290 */
60291#define IOMUXD_SPI0_SCK_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_sw_config_SHIFT)) & IOMUXD_SPI0_SCK_sw_config_MASK)
60292#define IOMUXD_SPI0_SCK_mux_mode_MASK (0x38000000U)
60293#define IOMUXD_SPI0_SCK_mux_mode_SHIFT (27U)
60294/*! mux_mode - mux_mode
60295 * 0b000..ADMA.SPI0.SCK
60296 * 0b001..ADMA.SAI0.TXC
60297 * 0b010..M40.I2C0.SCL
60298 * 0b011..M40.GPIO0.IO00
60299 * 0b100..LSIO.GPIO1.IO04
60300 */
60301#define IOMUXD_SPI0_SCK_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_mux_mode_SHIFT)) & IOMUXD_SPI0_SCK_mux_mode_MASK)
60302#define IOMUXD_SPI0_SCK_update_pad_ctl_MASK (0x40000000U)
60303#define IOMUXD_SPI0_SCK_update_pad_ctl_SHIFT (30U)
60304/*! update_pad_ctl - update lock for pad control
60305 */
60306#define IOMUXD_SPI0_SCK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_update_pad_ctl_SHIFT)) & IOMUXD_SPI0_SCK_update_pad_ctl_MASK)
60307#define IOMUXD_SPI0_SCK_update_mux_mode_MASK (0x80000000U)
60308#define IOMUXD_SPI0_SCK_update_mux_mode_SHIFT (31U)
60309/*! update_mux_mode - update lock for mux control
60310 */
60311#define IOMUXD_SPI0_SCK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SCK_update_mux_mode_SHIFT)) & IOMUXD_SPI0_SCK_update_mux_mode_MASK)
60312/*! @} */
60313
60314/*! @name SPI0_SDI - SPI0_SDI */
60315/*! @{ */
60316#define IOMUXD_SPI0_SDI_PDRV_MASK (0x1U)
60317#define IOMUXD_SPI0_SDI_PDRV_SHIFT (0U)
60318/*! PDRV - Drive
60319 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
60320 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
60321 */
60322#define IOMUXD_SPI0_SDI_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_PDRV_SHIFT)) & IOMUXD_SPI0_SDI_PDRV_MASK)
60323#define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_1_4_MASK (0x1EU)
60324#define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_1_4_SHIFT (1U)
60325/*! SPI0_SDI_reserved_1_4 - reserved
60326 */
60327#define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_SPI0_SDI_reserved_1_4_SHIFT)) & IOMUXD_SPI0_SDI_SPI0_SDI_reserved_1_4_MASK)
60328#define IOMUXD_SPI0_SDI_PULL_MASK (0x60U)
60329#define IOMUXD_SPI0_SDI_PULL_SHIFT (5U)
60330/*! PULL - Pull Down Pull Up
60331 * 0b10..pull down
60332 * 0b01..pull up
60333 * 0b00..Prohibited
60334 * 0b11..pull disabled
60335 */
60336#define IOMUXD_SPI0_SDI_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_PULL_SHIFT)) & IOMUXD_SPI0_SDI_PULL_MASK)
60337#define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_7_18_MASK (0x7FF80U)
60338#define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_7_18_SHIFT (7U)
60339/*! SPI0_SDI_reserved_7_18 - reserved
60340 */
60341#define IOMUXD_SPI0_SDI_SPI0_SDI_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_SPI0_SDI_reserved_7_18_SHIFT)) & IOMUXD_SPI0_SDI_SPI0_SDI_reserved_7_18_MASK)
60342#define IOMUXD_SPI0_SDI_WAKEUP_CTRL_MASK (0x380000U)
60343#define IOMUXD_SPI0_SDI_WAKEUP_CTRL_SHIFT (19U)
60344/*! WAKEUP_CTRL - wakeup control
60345 * 0b000..OFF
60346 * 0b001..RESAMPLE
60347 * 0b100..LOW
60348 * 0b111..HIGH
60349 * 0b110..RISE
60350 * 0b101..FALL
60351 */
60352#define IOMUXD_SPI0_SDI_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI0_SDI_WAKEUP_CTRL_MASK)
60353#define IOMUXD_SPI0_SDI_WAKEUP_MASK_MASK (0x400000U)
60354#define IOMUXD_SPI0_SDI_WAKEUP_MASK_SHIFT (22U)
60355/*! WAKEUP_MASK - wakeup mask
60356 */
60357#define IOMUXD_SPI0_SDI_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI0_SDI_WAKEUP_MASK_MASK)
60358#define IOMUXD_SPI0_SDI_lp_config_MASK (0x1800000U)
60359#define IOMUXD_SPI0_SDI_lp_config_SHIFT (23U)
60360/*! lp_config - lower power configuration
60361 * 0b01..EARLY_ISO
60362 * 0b10..LATE_ISO
60363 * 0b11..LATCH
60364 * 0b00..PASS
60365 */
60366#define IOMUXD_SPI0_SDI_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_lp_config_SHIFT)) & IOMUXD_SPI0_SDI_lp_config_MASK)
60367#define IOMUXD_SPI0_SDI_sw_config_MASK (0x6000000U)
60368#define IOMUXD_SPI0_SDI_sw_config_SHIFT (25U)
60369/*! sw_config - output and input configuration
60370 * 0b01..OPEN_DRAIN
60371 * 0b10..OPEN_DRAIN_INPUT
60372 * 0b11..INOUT
60373 * 0b00..DEFAULT
60374 */
60375#define IOMUXD_SPI0_SDI_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_sw_config_SHIFT)) & IOMUXD_SPI0_SDI_sw_config_MASK)
60376#define IOMUXD_SPI0_SDI_mux_mode_MASK (0x38000000U)
60377#define IOMUXD_SPI0_SDI_mux_mode_SHIFT (27U)
60378/*! mux_mode - mux_mode
60379 * 0b000..ADMA.SPI0.SDI
60380 * 0b001..ADMA.SAI0.TXD
60381 * 0b010..M40.TPM0.CH0
60382 * 0b011..M40.GPIO0.IO02
60383 * 0b100..LSIO.GPIO1.IO05
60384 */
60385#define IOMUXD_SPI0_SDI_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_mux_mode_SHIFT)) & IOMUXD_SPI0_SDI_mux_mode_MASK)
60386#define IOMUXD_SPI0_SDI_update_pad_ctl_MASK (0x40000000U)
60387#define IOMUXD_SPI0_SDI_update_pad_ctl_SHIFT (30U)
60388/*! update_pad_ctl - update lock for pad control
60389 */
60390#define IOMUXD_SPI0_SDI_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_update_pad_ctl_SHIFT)) & IOMUXD_SPI0_SDI_update_pad_ctl_MASK)
60391#define IOMUXD_SPI0_SDI_update_mux_mode_MASK (0x80000000U)
60392#define IOMUXD_SPI0_SDI_update_mux_mode_SHIFT (31U)
60393/*! update_mux_mode - update lock for mux control
60394 */
60395#define IOMUXD_SPI0_SDI_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDI_update_mux_mode_SHIFT)) & IOMUXD_SPI0_SDI_update_mux_mode_MASK)
60396/*! @} */
60397
60398/*! @name SPI0_SDO - SPI0_SDO */
60399/*! @{ */
60400#define IOMUXD_SPI0_SDO_PDRV_MASK (0x1U)
60401#define IOMUXD_SPI0_SDO_PDRV_SHIFT (0U)
60402/*! PDRV - Drive
60403 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
60404 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
60405 */
60406#define IOMUXD_SPI0_SDO_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_PDRV_SHIFT)) & IOMUXD_SPI0_SDO_PDRV_MASK)
60407#define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_1_4_MASK (0x1EU)
60408#define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_1_4_SHIFT (1U)
60409/*! SPI0_SDO_reserved_1_4 - reserved
60410 */
60411#define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_SPI0_SDO_reserved_1_4_SHIFT)) & IOMUXD_SPI0_SDO_SPI0_SDO_reserved_1_4_MASK)
60412#define IOMUXD_SPI0_SDO_PULL_MASK (0x60U)
60413#define IOMUXD_SPI0_SDO_PULL_SHIFT (5U)
60414/*! PULL - Pull Down Pull Up
60415 * 0b10..pull down
60416 * 0b01..pull up
60417 * 0b00..Prohibited
60418 * 0b11..pull disabled
60419 */
60420#define IOMUXD_SPI0_SDO_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_PULL_SHIFT)) & IOMUXD_SPI0_SDO_PULL_MASK)
60421#define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_7_18_MASK (0x7FF80U)
60422#define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_7_18_SHIFT (7U)
60423/*! SPI0_SDO_reserved_7_18 - reserved
60424 */
60425#define IOMUXD_SPI0_SDO_SPI0_SDO_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_SPI0_SDO_reserved_7_18_SHIFT)) & IOMUXD_SPI0_SDO_SPI0_SDO_reserved_7_18_MASK)
60426#define IOMUXD_SPI0_SDO_WAKEUP_CTRL_MASK (0x380000U)
60427#define IOMUXD_SPI0_SDO_WAKEUP_CTRL_SHIFT (19U)
60428/*! WAKEUP_CTRL - wakeup control
60429 * 0b000..OFF
60430 * 0b001..RESAMPLE
60431 * 0b100..LOW
60432 * 0b111..HIGH
60433 * 0b110..RISE
60434 * 0b101..FALL
60435 */
60436#define IOMUXD_SPI0_SDO_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI0_SDO_WAKEUP_CTRL_MASK)
60437#define IOMUXD_SPI0_SDO_WAKEUP_MASK_MASK (0x400000U)
60438#define IOMUXD_SPI0_SDO_WAKEUP_MASK_SHIFT (22U)
60439/*! WAKEUP_MASK - wakeup mask
60440 */
60441#define IOMUXD_SPI0_SDO_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI0_SDO_WAKEUP_MASK_MASK)
60442#define IOMUXD_SPI0_SDO_lp_config_MASK (0x1800000U)
60443#define IOMUXD_SPI0_SDO_lp_config_SHIFT (23U)
60444/*! lp_config - lower power configuration
60445 * 0b01..EARLY_ISO
60446 * 0b10..LATE_ISO
60447 * 0b11..LATCH
60448 * 0b00..PASS
60449 */
60450#define IOMUXD_SPI0_SDO_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_lp_config_SHIFT)) & IOMUXD_SPI0_SDO_lp_config_MASK)
60451#define IOMUXD_SPI0_SDO_sw_config_MASK (0x6000000U)
60452#define IOMUXD_SPI0_SDO_sw_config_SHIFT (25U)
60453/*! sw_config - output and input configuration
60454 * 0b01..OPEN_DRAIN
60455 * 0b10..OPEN_DRAIN_INPUT
60456 * 0b11..INOUT
60457 * 0b00..DEFAULT
60458 */
60459#define IOMUXD_SPI0_SDO_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_sw_config_SHIFT)) & IOMUXD_SPI0_SDO_sw_config_MASK)
60460#define IOMUXD_SPI0_SDO_mux_mode_MASK (0x38000000U)
60461#define IOMUXD_SPI0_SDO_mux_mode_SHIFT (27U)
60462/*! mux_mode - mux_mode
60463 * 0b000..ADMA.SPI0.SDO
60464 * 0b001..ADMA.SAI0.TXFS
60465 * 0b010..M40.I2C0.SDA
60466 * 0b011..M40.GPIO0.IO01
60467 * 0b100..LSIO.GPIO1.IO06
60468 */
60469#define IOMUXD_SPI0_SDO_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_mux_mode_SHIFT)) & IOMUXD_SPI0_SDO_mux_mode_MASK)
60470#define IOMUXD_SPI0_SDO_update_pad_ctl_MASK (0x40000000U)
60471#define IOMUXD_SPI0_SDO_update_pad_ctl_SHIFT (30U)
60472/*! update_pad_ctl - update lock for pad control
60473 */
60474#define IOMUXD_SPI0_SDO_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_update_pad_ctl_SHIFT)) & IOMUXD_SPI0_SDO_update_pad_ctl_MASK)
60475#define IOMUXD_SPI0_SDO_update_mux_mode_MASK (0x80000000U)
60476#define IOMUXD_SPI0_SDO_update_mux_mode_SHIFT (31U)
60477/*! update_mux_mode - update lock for mux control
60478 */
60479#define IOMUXD_SPI0_SDO_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_SDO_update_mux_mode_SHIFT)) & IOMUXD_SPI0_SDO_update_mux_mode_MASK)
60480/*! @} */
60481
60482/*! @name SPI0_CS1 - SPI0_CS1 */
60483/*! @{ */
60484#define IOMUXD_SPI0_CS1_PDRV_MASK (0x1U)
60485#define IOMUXD_SPI0_CS1_PDRV_SHIFT (0U)
60486/*! PDRV - Drive
60487 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
60488 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
60489 */
60490#define IOMUXD_SPI0_CS1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_PDRV_SHIFT)) & IOMUXD_SPI0_CS1_PDRV_MASK)
60491#define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_1_4_MASK (0x1EU)
60492#define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_1_4_SHIFT (1U)
60493/*! SPI0_CS1_reserved_1_4 - reserved
60494 */
60495#define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_SPI0_CS1_reserved_1_4_SHIFT)) & IOMUXD_SPI0_CS1_SPI0_CS1_reserved_1_4_MASK)
60496#define IOMUXD_SPI0_CS1_PULL_MASK (0x60U)
60497#define IOMUXD_SPI0_CS1_PULL_SHIFT (5U)
60498/*! PULL - Pull Down Pull Up
60499 * 0b10..pull down
60500 * 0b01..pull up
60501 * 0b00..Prohibited
60502 * 0b11..pull disabled
60503 */
60504#define IOMUXD_SPI0_CS1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_PULL_SHIFT)) & IOMUXD_SPI0_CS1_PULL_MASK)
60505#define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_7_18_MASK (0x7FF80U)
60506#define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_7_18_SHIFT (7U)
60507/*! SPI0_CS1_reserved_7_18 - reserved
60508 */
60509#define IOMUXD_SPI0_CS1_SPI0_CS1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_SPI0_CS1_reserved_7_18_SHIFT)) & IOMUXD_SPI0_CS1_SPI0_CS1_reserved_7_18_MASK)
60510#define IOMUXD_SPI0_CS1_WAKEUP_CTRL_MASK (0x380000U)
60511#define IOMUXD_SPI0_CS1_WAKEUP_CTRL_SHIFT (19U)
60512/*! WAKEUP_CTRL - wakeup control
60513 * 0b000..OFF
60514 * 0b001..RESAMPLE
60515 * 0b100..LOW
60516 * 0b111..HIGH
60517 * 0b110..RISE
60518 * 0b101..FALL
60519 */
60520#define IOMUXD_SPI0_CS1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI0_CS1_WAKEUP_CTRL_MASK)
60521#define IOMUXD_SPI0_CS1_WAKEUP_MASK_MASK (0x400000U)
60522#define IOMUXD_SPI0_CS1_WAKEUP_MASK_SHIFT (22U)
60523/*! WAKEUP_MASK - wakeup mask
60524 */
60525#define IOMUXD_SPI0_CS1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI0_CS1_WAKEUP_MASK_MASK)
60526#define IOMUXD_SPI0_CS1_lp_config_MASK (0x1800000U)
60527#define IOMUXD_SPI0_CS1_lp_config_SHIFT (23U)
60528/*! lp_config - lower power configuration
60529 * 0b01..EARLY_ISO
60530 * 0b10..LATE_ISO
60531 * 0b11..LATCH
60532 * 0b00..PASS
60533 */
60534#define IOMUXD_SPI0_CS1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_lp_config_SHIFT)) & IOMUXD_SPI0_CS1_lp_config_MASK)
60535#define IOMUXD_SPI0_CS1_sw_config_MASK (0x6000000U)
60536#define IOMUXD_SPI0_CS1_sw_config_SHIFT (25U)
60537/*! sw_config - output and input configuration
60538 * 0b01..OPEN_DRAIN
60539 * 0b10..OPEN_DRAIN_INPUT
60540 * 0b11..INOUT
60541 * 0b00..DEFAULT
60542 */
60543#define IOMUXD_SPI0_CS1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_sw_config_SHIFT)) & IOMUXD_SPI0_CS1_sw_config_MASK)
60544#define IOMUXD_SPI0_CS1_mux_mode_MASK (0x38000000U)
60545#define IOMUXD_SPI0_CS1_mux_mode_SHIFT (27U)
60546/*! mux_mode - mux_mode
60547 * 0b000..ADMA.SPI0.CS1
60548 * 0b001..ADMA.SAI0.RXC
60549 * 0b010..ADMA.SAI1.TXD
60550 * 0b011..ADMA.LCD_PWM0.OUT
60551 * 0b100..LSIO.GPIO1.IO07
60552 */
60553#define IOMUXD_SPI0_CS1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_mux_mode_SHIFT)) & IOMUXD_SPI0_CS1_mux_mode_MASK)
60554#define IOMUXD_SPI0_CS1_update_pad_ctl_MASK (0x40000000U)
60555#define IOMUXD_SPI0_CS1_update_pad_ctl_SHIFT (30U)
60556/*! update_pad_ctl - update lock for pad control
60557 */
60558#define IOMUXD_SPI0_CS1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_update_pad_ctl_SHIFT)) & IOMUXD_SPI0_CS1_update_pad_ctl_MASK)
60559#define IOMUXD_SPI0_CS1_update_mux_mode_MASK (0x80000000U)
60560#define IOMUXD_SPI0_CS1_update_mux_mode_SHIFT (31U)
60561/*! update_mux_mode - update lock for mux control
60562 */
60563#define IOMUXD_SPI0_CS1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS1_update_mux_mode_SHIFT)) & IOMUXD_SPI0_CS1_update_mux_mode_MASK)
60564/*! @} */
60565
60566/*! @name IOMUXD_GROUP_2_0 - na */
60567/*! @{ */
60568#define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXD_MASK (0x1U)
60569#define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXD_SHIFT (0U)
60570/*! SAI0_TXD - wakeup from SAI0_TXD
60571 */
60572#define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXD_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXD_MASK)
60573#define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXC_MASK (0x2U)
60574#define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXC_SHIFT (1U)
60575/*! SAI0_TXC - wakeup from SAI0_TXC
60576 */
60577#define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXC_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXC_MASK)
60578#define IOMUXD_IOMUXD_GROUP_2_0_SAI0_RXD_MASK (0x4U)
60579#define IOMUXD_IOMUXD_GROUP_2_0_SAI0_RXD_SHIFT (2U)
60580/*! SAI0_RXD - wakeup from SAI0_RXD
60581 */
60582#define IOMUXD_IOMUXD_GROUP_2_0_SAI0_RXD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI0_RXD_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI0_RXD_MASK)
60583#define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXFS_MASK (0x8U)
60584#define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXFS_SHIFT (3U)
60585/*! SAI0_TXFS - wakeup from SAI0_TXFS
60586 */
60587#define IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXFS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXFS_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI0_TXFS_MASK)
60588#define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXD_MASK (0x10U)
60589#define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXD_SHIFT (4U)
60590/*! SAI1_RXD - wakeup from SAI1_RXD
60591 */
60592#define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXD(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXD_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXD_MASK)
60593#define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXC_MASK (0x20U)
60594#define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXC_SHIFT (5U)
60595/*! SAI1_RXC - wakeup from SAI1_RXC
60596 */
60597#define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXC_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXC_MASK)
60598#define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXFS_MASK (0x40U)
60599#define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXFS_SHIFT (6U)
60600/*! SAI1_RXFS - wakeup from SAI1_RXFS
60601 */
60602#define IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXFS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXFS_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SAI1_RXFS_MASK)
60603#define IOMUXD_IOMUXD_GROUP_2_0_SPI2_CS0_MASK (0x80U)
60604#define IOMUXD_IOMUXD_GROUP_2_0_SPI2_CS0_SHIFT (7U)
60605/*! SPI2_CS0 - wakeup from SPI2_CS0
60606 */
60607#define IOMUXD_IOMUXD_GROUP_2_0_SPI2_CS0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI2_CS0_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI2_CS0_MASK)
60608#define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDO_MASK (0x100U)
60609#define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDO_SHIFT (8U)
60610/*! SPI2_SDO - wakeup from SPI2_SDO
60611 */
60612#define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDO(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDO_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDO_MASK)
60613#define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDI_MASK (0x200U)
60614#define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDI_SHIFT (9U)
60615/*! SPI2_SDI - wakeup from SPI2_SDI
60616 */
60617#define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDI(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDI_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI2_SDI_MASK)
60618#define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SCK_MASK (0x400U)
60619#define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SCK_SHIFT (10U)
60620/*! SPI2_SCK - wakeup from SPI2_SCK
60621 */
60622#define IOMUXD_IOMUXD_GROUP_2_0_SPI2_SCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI2_SCK_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI2_SCK_MASK)
60623#define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SCK_MASK (0x800U)
60624#define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SCK_SHIFT (11U)
60625/*! SPI0_SCK - wakeup from SPI0_SCK
60626 */
60627#define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI0_SCK_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI0_SCK_MASK)
60628#define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDI_MASK (0x1000U)
60629#define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDI_SHIFT (12U)
60630/*! SPI0_SDI - wakeup from SPI0_SDI
60631 */
60632#define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDI(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDI_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDI_MASK)
60633#define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDO_MASK (0x2000U)
60634#define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDO_SHIFT (13U)
60635/*! SPI0_SDO - wakeup from SPI0_SDO
60636 */
60637#define IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDO(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDO_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI0_SDO_MASK)
60638#define IOMUXD_IOMUXD_GROUP_2_0_SPI0_CS1_MASK (0x4000U)
60639#define IOMUXD_IOMUXD_GROUP_2_0_SPI0_CS1_SHIFT (14U)
60640/*! SPI0_CS1 - wakeup from SPI0_CS1
60641 */
60642#define IOMUXD_IOMUXD_GROUP_2_0_SPI0_CS1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_SPI0_CS1_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_SPI0_CS1_MASK)
60643#define IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_15_31_MASK (0xFFFF8000U)
60644#define IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_15_31_SHIFT (15U)
60645/*! iomuxd_group_2_0_reserved_15_31 - reserved
60646 */
60647#define IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_0_iomuxd_group_2_0_reserved_15_31_MASK)
60648/*! @} */
60649
60650/*! @name SPI0_CS0 - SPI0_CS0 */
60651/*! @{ */
60652#define IOMUXD_SPI0_CS0_PDRV_MASK (0x1U)
60653#define IOMUXD_SPI0_CS0_PDRV_SHIFT (0U)
60654/*! PDRV - Drive
60655 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
60656 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
60657 */
60658#define IOMUXD_SPI0_CS0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_PDRV_SHIFT)) & IOMUXD_SPI0_CS0_PDRV_MASK)
60659#define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_1_4_MASK (0x1EU)
60660#define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_1_4_SHIFT (1U)
60661/*! SPI0_CS0_reserved_1_4 - reserved
60662 */
60663#define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_SPI0_CS0_reserved_1_4_SHIFT)) & IOMUXD_SPI0_CS0_SPI0_CS0_reserved_1_4_MASK)
60664#define IOMUXD_SPI0_CS0_PULL_MASK (0x60U)
60665#define IOMUXD_SPI0_CS0_PULL_SHIFT (5U)
60666/*! PULL - Pull Down Pull Up
60667 * 0b10..pull down
60668 * 0b01..pull up
60669 * 0b00..Prohibited
60670 * 0b11..pull disabled
60671 */
60672#define IOMUXD_SPI0_CS0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_PULL_SHIFT)) & IOMUXD_SPI0_CS0_PULL_MASK)
60673#define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_7_18_MASK (0x7FF80U)
60674#define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_7_18_SHIFT (7U)
60675/*! SPI0_CS0_reserved_7_18 - reserved
60676 */
60677#define IOMUXD_SPI0_CS0_SPI0_CS0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_SPI0_CS0_reserved_7_18_SHIFT)) & IOMUXD_SPI0_CS0_SPI0_CS0_reserved_7_18_MASK)
60678#define IOMUXD_SPI0_CS0_WAKEUP_CTRL_MASK (0x380000U)
60679#define IOMUXD_SPI0_CS0_WAKEUP_CTRL_SHIFT (19U)
60680/*! WAKEUP_CTRL - wakeup control
60681 * 0b000..OFF
60682 * 0b001..RESAMPLE
60683 * 0b100..LOW
60684 * 0b111..HIGH
60685 * 0b110..RISE
60686 * 0b101..FALL
60687 */
60688#define IOMUXD_SPI0_CS0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_WAKEUP_CTRL_SHIFT)) & IOMUXD_SPI0_CS0_WAKEUP_CTRL_MASK)
60689#define IOMUXD_SPI0_CS0_WAKEUP_MASK_MASK (0x400000U)
60690#define IOMUXD_SPI0_CS0_WAKEUP_MASK_SHIFT (22U)
60691/*! WAKEUP_MASK - wakeup mask
60692 */
60693#define IOMUXD_SPI0_CS0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_WAKEUP_MASK_SHIFT)) & IOMUXD_SPI0_CS0_WAKEUP_MASK_MASK)
60694#define IOMUXD_SPI0_CS0_lp_config_MASK (0x1800000U)
60695#define IOMUXD_SPI0_CS0_lp_config_SHIFT (23U)
60696/*! lp_config - lower power configuration
60697 * 0b01..EARLY_ISO
60698 * 0b10..LATE_ISO
60699 * 0b11..LATCH
60700 * 0b00..PASS
60701 */
60702#define IOMUXD_SPI0_CS0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_lp_config_SHIFT)) & IOMUXD_SPI0_CS0_lp_config_MASK)
60703#define IOMUXD_SPI0_CS0_sw_config_MASK (0x6000000U)
60704#define IOMUXD_SPI0_CS0_sw_config_SHIFT (25U)
60705/*! sw_config - output and input configuration
60706 * 0b01..OPEN_DRAIN
60707 * 0b10..OPEN_DRAIN_INPUT
60708 * 0b11..INOUT
60709 * 0b00..DEFAULT
60710 */
60711#define IOMUXD_SPI0_CS0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_sw_config_SHIFT)) & IOMUXD_SPI0_CS0_sw_config_MASK)
60712#define IOMUXD_SPI0_CS0_mux_mode_MASK (0x38000000U)
60713#define IOMUXD_SPI0_CS0_mux_mode_SHIFT (27U)
60714/*! mux_mode - mux_mode
60715 * 0b000..ADMA.SPI0.CS0
60716 * 0b001..ADMA.SAI0.RXD
60717 * 0b010..M40.TPM0.CH1
60718 * 0b011..M40.GPIO0.IO03
60719 * 0b100..LSIO.GPIO1.IO08
60720 */
60721#define IOMUXD_SPI0_CS0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_mux_mode_SHIFT)) & IOMUXD_SPI0_CS0_mux_mode_MASK)
60722#define IOMUXD_SPI0_CS0_update_pad_ctl_MASK (0x40000000U)
60723#define IOMUXD_SPI0_CS0_update_pad_ctl_SHIFT (30U)
60724/*! update_pad_ctl - update lock for pad control
60725 */
60726#define IOMUXD_SPI0_CS0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_update_pad_ctl_SHIFT)) & IOMUXD_SPI0_CS0_update_pad_ctl_MASK)
60727#define IOMUXD_SPI0_CS0_update_mux_mode_MASK (0x80000000U)
60728#define IOMUXD_SPI0_CS0_update_mux_mode_SHIFT (31U)
60729/*! update_mux_mode - update lock for mux control
60730 */
60731#define IOMUXD_SPI0_CS0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SPI0_CS0_update_mux_mode_SHIFT)) & IOMUXD_SPI0_CS0_update_mux_mode_MASK)
60732/*! @} */
60733
60734/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT */
60735/*! @{ */
60736#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMP_MASK (0x7U)
60737#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMP_SHIFT (0U)
60738/*! COMP - COMP
60739 * 0b010..Fixed code mode
60740 * 0b100..High impedance mode
60741 * 0b110..Read mode
60742 * 0b000..Normal Mode
60743 * 0b001..Freeze Mode
60744 */
60745#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMP_MASK)
60746#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_FASTFRZ_EN_MASK (0x8U)
60747#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_FASTFRZ_EN_SHIFT (3U)
60748/*! FASTFRZ_EN - FASTFRZ_EN
60749 * 0b1..FASTFRZ signal is driven by output of subsystem
60750 * 0b0..FASTFRZ signal is gated to 0
60751 */
60752#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_FASTFRZ_EN_MASK)
60753#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4_MASK (0x10U)
60754#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4_SHIFT (4U)
60755/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4 - reserved
60756 */
60757#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_4_4_MASK)
60758#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCP_MASK (0x1E0U)
60759#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCP_SHIFT (5U)
60760/*! RASRCP - RASRCP
60761 * 0b0101..Reset Value
60762 */
60763#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCP_MASK)
60764#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCN_MASK (0x1E00U)
60765#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCN_SHIFT (9U)
60766/*! RASRCN - RASRCN
60767 * 0b1010..Reset Value
60768 */
60769#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_RASRCN_MASK)
60770#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SELECT_NASRC_MASK (0x2000U)
60771#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SELECT_NASRC_SHIFT (13U)
60772/*! SELECT_NASRC - SELECT_NASRC
60773 * 0b1..NASRCN value
60774 * 0b0..NASRCP value
60775 */
60776#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SELECT_NASRC_MASK)
60777#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMPOK_MASK (0x4000U)
60778#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMPOK_SHIFT (14U)
60779/*! COMPOK - COMPOK
60780 * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
60781 * 0b1..compensation cell in Normal mode and tracking PVT
60782 */
60783#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_COMPOK_MASK)
60784#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_READ_NASRC_MASK (0x78000U)
60785#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_READ_NASRC_SHIFT (15U)
60786/*! READ_NASRC - READ_NASRC
60787 * 0b0000..READ Only
60788 */
60789#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_READ_NASRC_MASK)
60790#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22_MASK (0x780000U)
60791#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22_SHIFT (19U)
60792/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22 - reserved
60793 */
60794#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_19_22_MASK)
60795#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SLEEP_MASK (0x1800000U)
60796#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SLEEP_SHIFT (23U)
60797/*! SLEEP - SLEEP
60798 * 0b11..Force into sleep mode
60799 * 0b00..NO
60800 * 0b01..EARLY
60801 * 0b10..LATE
60802 */
60803#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_SLEEP_MASK)
60804#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29_MASK (0x3E000000U)
60805#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29_SHIFT (25U)
60806/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29 - reserved
60807 */
60808#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_reserved_25_29_MASK)
60809#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_pad_ctl_MASK (0x40000000U)
60810#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_pad_ctl_SHIFT (30U)
60811/*! update_pad_ctl - update lock for pad control
60812 */
60813#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_pad_ctl_MASK)
60814#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_mux_mode_MASK (0x80000000U)
60815#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_mux_mode_SHIFT (31U)
60816/*! update_mux_mode - update lock for mux control
60817 */
60818#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHT_update_mux_mode_MASK)
60819/*! @} */
60820
60821/*! @name ADC_IN1 - ADC_IN1 */
60822/*! @{ */
60823#define IOMUXD_ADC_IN1_DSE_MASK (0x7U)
60824#define IOMUXD_ADC_IN1_DSE_SHIFT (0U)
60825/*! DSE - Drive
60826 * 0b001..Drive select 2mA
60827 * 0b011..Drive select 6mA
60828 * 0b111..High Speed
60829 * 0b110..Drive select 12mA
60830 * 0b010..Drive select 4mA
60831 * 0b100..Drive select 8mA
60832 * 0b000..Drive select 1mA
60833 * 0b101..Drive select 10mA
60834 */
60835#define IOMUXD_ADC_IN1_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_DSE_SHIFT)) & IOMUXD_ADC_IN1_DSE_MASK)
60836#define IOMUXD_ADC_IN1_ADC_IN1_reserved_3_4_MASK (0x18U)
60837#define IOMUXD_ADC_IN1_ADC_IN1_reserved_3_4_SHIFT (3U)
60838/*! ADC_IN1_reserved_3_4 - reserved
60839 */
60840#define IOMUXD_ADC_IN1_ADC_IN1_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_ADC_IN1_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN1_ADC_IN1_reserved_3_4_MASK)
60841#define IOMUXD_ADC_IN1_PULL_MASK (0x60U)
60842#define IOMUXD_ADC_IN1_PULL_SHIFT (5U)
60843/*! PULL - Pull Down Pull Up
60844 * 0b00..Bus-Keeper
60845 * 0b10..pull down
60846 * 0b01..pull up
60847 * 0b11..No Pull
60848 */
60849#define IOMUXD_ADC_IN1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_PULL_SHIFT)) & IOMUXD_ADC_IN1_PULL_MASK)
60850#define IOMUXD_ADC_IN1_ADC_IN1_reserved_7_18_MASK (0x7FF80U)
60851#define IOMUXD_ADC_IN1_ADC_IN1_reserved_7_18_SHIFT (7U)
60852/*! ADC_IN1_reserved_7_18 - reserved
60853 */
60854#define IOMUXD_ADC_IN1_ADC_IN1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_ADC_IN1_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN1_ADC_IN1_reserved_7_18_MASK)
60855#define IOMUXD_ADC_IN1_WAKEUP_CTRL_MASK (0x380000U)
60856#define IOMUXD_ADC_IN1_WAKEUP_CTRL_SHIFT (19U)
60857/*! WAKEUP_CTRL - wakeup control
60858 * 0b000..OFF
60859 * 0b001..RESAMPLE
60860 * 0b100..LOW
60861 * 0b111..HIGH
60862 * 0b110..RISE
60863 * 0b101..FALL
60864 */
60865#define IOMUXD_ADC_IN1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN1_WAKEUP_CTRL_MASK)
60866#define IOMUXD_ADC_IN1_WAKEUP_MASK_MASK (0x400000U)
60867#define IOMUXD_ADC_IN1_WAKEUP_MASK_SHIFT (22U)
60868/*! WAKEUP_MASK - wakeup mask
60869 */
60870#define IOMUXD_ADC_IN1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN1_WAKEUP_MASK_MASK)
60871#define IOMUXD_ADC_IN1_lp_config_MASK (0x1800000U)
60872#define IOMUXD_ADC_IN1_lp_config_SHIFT (23U)
60873/*! lp_config - lower power configuration
60874 * 0b01..EARLY_ISO
60875 * 0b10..LATE_ISO
60876 * 0b11..LATCH
60877 * 0b00..PASS
60878 */
60879#define IOMUXD_ADC_IN1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_lp_config_SHIFT)) & IOMUXD_ADC_IN1_lp_config_MASK)
60880#define IOMUXD_ADC_IN1_sw_config_MASK (0x6000000U)
60881#define IOMUXD_ADC_IN1_sw_config_SHIFT (25U)
60882/*! sw_config - output and input configuration
60883 * 0b01..OPEN_DRAIN
60884 * 0b10..OPEN_DRAIN_INPUT
60885 * 0b11..INOUT
60886 * 0b00..DEFAULT
60887 */
60888#define IOMUXD_ADC_IN1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_sw_config_SHIFT)) & IOMUXD_ADC_IN1_sw_config_MASK)
60889#define IOMUXD_ADC_IN1_mux_mode_MASK (0x38000000U)
60890#define IOMUXD_ADC_IN1_mux_mode_SHIFT (27U)
60891/*! mux_mode - mux_mode
60892 * 0b000..ADMA.ADC.IN1
60893 * 0b001..M40.I2C0.SDA
60894 * 0b010..M40.GPIO0.IO01
60895 * 0b100..LSIO.GPIO1.IO09
60896 */
60897#define IOMUXD_ADC_IN1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_mux_mode_SHIFT)) & IOMUXD_ADC_IN1_mux_mode_MASK)
60898#define IOMUXD_ADC_IN1_update_pad_ctl_MASK (0x40000000U)
60899#define IOMUXD_ADC_IN1_update_pad_ctl_SHIFT (30U)
60900/*! update_pad_ctl - update lock for pad control
60901 */
60902#define IOMUXD_ADC_IN1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN1_update_pad_ctl_MASK)
60903#define IOMUXD_ADC_IN1_update_mux_mode_MASK (0x80000000U)
60904#define IOMUXD_ADC_IN1_update_mux_mode_SHIFT (31U)
60905/*! update_mux_mode - update lock for mux control
60906 */
60907#define IOMUXD_ADC_IN1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN1_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN1_update_mux_mode_MASK)
60908/*! @} */
60909
60910/*! @name ADC_IN0 - ADC_IN0 */
60911/*! @{ */
60912#define IOMUXD_ADC_IN0_DSE_MASK (0x7U)
60913#define IOMUXD_ADC_IN0_DSE_SHIFT (0U)
60914/*! DSE - Drive
60915 * 0b001..Drive select 2mA
60916 * 0b011..Drive select 6mA
60917 * 0b111..High Speed
60918 * 0b110..Drive select 12mA
60919 * 0b010..Drive select 4mA
60920 * 0b100..Drive select 8mA
60921 * 0b000..Drive select 1mA
60922 * 0b101..Drive select 10mA
60923 */
60924#define IOMUXD_ADC_IN0_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_DSE_SHIFT)) & IOMUXD_ADC_IN0_DSE_MASK)
60925#define IOMUXD_ADC_IN0_ADC_IN0_reserved_3_4_MASK (0x18U)
60926#define IOMUXD_ADC_IN0_ADC_IN0_reserved_3_4_SHIFT (3U)
60927/*! ADC_IN0_reserved_3_4 - reserved
60928 */
60929#define IOMUXD_ADC_IN0_ADC_IN0_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_ADC_IN0_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN0_ADC_IN0_reserved_3_4_MASK)
60930#define IOMUXD_ADC_IN0_PULL_MASK (0x60U)
60931#define IOMUXD_ADC_IN0_PULL_SHIFT (5U)
60932/*! PULL - Pull Down Pull Up
60933 * 0b00..Bus-Keeper
60934 * 0b10..pull down
60935 * 0b01..pull up
60936 * 0b11..No Pull
60937 */
60938#define IOMUXD_ADC_IN0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_PULL_SHIFT)) & IOMUXD_ADC_IN0_PULL_MASK)
60939#define IOMUXD_ADC_IN0_ADC_IN0_reserved_7_18_MASK (0x7FF80U)
60940#define IOMUXD_ADC_IN0_ADC_IN0_reserved_7_18_SHIFT (7U)
60941/*! ADC_IN0_reserved_7_18 - reserved
60942 */
60943#define IOMUXD_ADC_IN0_ADC_IN0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_ADC_IN0_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN0_ADC_IN0_reserved_7_18_MASK)
60944#define IOMUXD_ADC_IN0_WAKEUP_CTRL_MASK (0x380000U)
60945#define IOMUXD_ADC_IN0_WAKEUP_CTRL_SHIFT (19U)
60946/*! WAKEUP_CTRL - wakeup control
60947 * 0b000..OFF
60948 * 0b001..RESAMPLE
60949 * 0b100..LOW
60950 * 0b111..HIGH
60951 * 0b110..RISE
60952 * 0b101..FALL
60953 */
60954#define IOMUXD_ADC_IN0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN0_WAKEUP_CTRL_MASK)
60955#define IOMUXD_ADC_IN0_WAKEUP_MASK_MASK (0x400000U)
60956#define IOMUXD_ADC_IN0_WAKEUP_MASK_SHIFT (22U)
60957/*! WAKEUP_MASK - wakeup mask
60958 */
60959#define IOMUXD_ADC_IN0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN0_WAKEUP_MASK_MASK)
60960#define IOMUXD_ADC_IN0_lp_config_MASK (0x1800000U)
60961#define IOMUXD_ADC_IN0_lp_config_SHIFT (23U)
60962/*! lp_config - lower power configuration
60963 * 0b01..EARLY_ISO
60964 * 0b10..LATE_ISO
60965 * 0b11..LATCH
60966 * 0b00..PASS
60967 */
60968#define IOMUXD_ADC_IN0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_lp_config_SHIFT)) & IOMUXD_ADC_IN0_lp_config_MASK)
60969#define IOMUXD_ADC_IN0_sw_config_MASK (0x6000000U)
60970#define IOMUXD_ADC_IN0_sw_config_SHIFT (25U)
60971/*! sw_config - output and input configuration
60972 * 0b01..OPEN_DRAIN
60973 * 0b10..OPEN_DRAIN_INPUT
60974 * 0b11..INOUT
60975 * 0b00..DEFAULT
60976 */
60977#define IOMUXD_ADC_IN0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_sw_config_SHIFT)) & IOMUXD_ADC_IN0_sw_config_MASK)
60978#define IOMUXD_ADC_IN0_mux_mode_MASK (0x38000000U)
60979#define IOMUXD_ADC_IN0_mux_mode_SHIFT (27U)
60980/*! mux_mode - mux_mode
60981 * 0b000..ADMA.ADC.IN0
60982 * 0b001..M40.I2C0.SCL
60983 * 0b010..M40.GPIO0.IO00
60984 * 0b100..LSIO.GPIO1.IO10
60985 */
60986#define IOMUXD_ADC_IN0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_mux_mode_SHIFT)) & IOMUXD_ADC_IN0_mux_mode_MASK)
60987#define IOMUXD_ADC_IN0_update_pad_ctl_MASK (0x40000000U)
60988#define IOMUXD_ADC_IN0_update_pad_ctl_SHIFT (30U)
60989/*! update_pad_ctl - update lock for pad control
60990 */
60991#define IOMUXD_ADC_IN0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN0_update_pad_ctl_MASK)
60992#define IOMUXD_ADC_IN0_update_mux_mode_MASK (0x80000000U)
60993#define IOMUXD_ADC_IN0_update_mux_mode_SHIFT (31U)
60994/*! update_mux_mode - update lock for mux control
60995 */
60996#define IOMUXD_ADC_IN0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN0_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN0_update_mux_mode_MASK)
60997/*! @} */
60998
60999/*! @name ADC_IN3 - ADC_IN3 */
61000/*! @{ */
61001#define IOMUXD_ADC_IN3_DSE_MASK (0x7U)
61002#define IOMUXD_ADC_IN3_DSE_SHIFT (0U)
61003/*! DSE - Drive
61004 * 0b001..Drive select 2mA
61005 * 0b011..Drive select 6mA
61006 * 0b111..High Speed
61007 * 0b110..Drive select 12mA
61008 * 0b010..Drive select 4mA
61009 * 0b100..Drive select 8mA
61010 * 0b000..Drive select 1mA
61011 * 0b101..Drive select 10mA
61012 */
61013#define IOMUXD_ADC_IN3_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_DSE_SHIFT)) & IOMUXD_ADC_IN3_DSE_MASK)
61014#define IOMUXD_ADC_IN3_ADC_IN3_reserved_3_4_MASK (0x18U)
61015#define IOMUXD_ADC_IN3_ADC_IN3_reserved_3_4_SHIFT (3U)
61016/*! ADC_IN3_reserved_3_4 - reserved
61017 */
61018#define IOMUXD_ADC_IN3_ADC_IN3_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_ADC_IN3_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN3_ADC_IN3_reserved_3_4_MASK)
61019#define IOMUXD_ADC_IN3_PULL_MASK (0x60U)
61020#define IOMUXD_ADC_IN3_PULL_SHIFT (5U)
61021/*! PULL - Pull Down Pull Up
61022 * 0b00..Bus-Keeper
61023 * 0b10..pull down
61024 * 0b01..pull up
61025 * 0b11..No Pull
61026 */
61027#define IOMUXD_ADC_IN3_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_PULL_SHIFT)) & IOMUXD_ADC_IN3_PULL_MASK)
61028#define IOMUXD_ADC_IN3_ADC_IN3_reserved_7_18_MASK (0x7FF80U)
61029#define IOMUXD_ADC_IN3_ADC_IN3_reserved_7_18_SHIFT (7U)
61030/*! ADC_IN3_reserved_7_18 - reserved
61031 */
61032#define IOMUXD_ADC_IN3_ADC_IN3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_ADC_IN3_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN3_ADC_IN3_reserved_7_18_MASK)
61033#define IOMUXD_ADC_IN3_WAKEUP_CTRL_MASK (0x380000U)
61034#define IOMUXD_ADC_IN3_WAKEUP_CTRL_SHIFT (19U)
61035/*! WAKEUP_CTRL - wakeup control
61036 * 0b000..OFF
61037 * 0b001..RESAMPLE
61038 * 0b100..LOW
61039 * 0b111..HIGH
61040 * 0b110..RISE
61041 * 0b101..FALL
61042 */
61043#define IOMUXD_ADC_IN3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN3_WAKEUP_CTRL_MASK)
61044#define IOMUXD_ADC_IN3_WAKEUP_MASK_MASK (0x400000U)
61045#define IOMUXD_ADC_IN3_WAKEUP_MASK_SHIFT (22U)
61046/*! WAKEUP_MASK - wakeup mask
61047 */
61048#define IOMUXD_ADC_IN3_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN3_WAKEUP_MASK_MASK)
61049#define IOMUXD_ADC_IN3_lp_config_MASK (0x1800000U)
61050#define IOMUXD_ADC_IN3_lp_config_SHIFT (23U)
61051/*! lp_config - lower power configuration
61052 * 0b01..EARLY_ISO
61053 * 0b10..LATE_ISO
61054 * 0b11..LATCH
61055 * 0b00..PASS
61056 */
61057#define IOMUXD_ADC_IN3_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_lp_config_SHIFT)) & IOMUXD_ADC_IN3_lp_config_MASK)
61058#define IOMUXD_ADC_IN3_sw_config_MASK (0x6000000U)
61059#define IOMUXD_ADC_IN3_sw_config_SHIFT (25U)
61060/*! sw_config - output and input configuration
61061 * 0b01..OPEN_DRAIN
61062 * 0b10..OPEN_DRAIN_INPUT
61063 * 0b11..INOUT
61064 * 0b00..DEFAULT
61065 */
61066#define IOMUXD_ADC_IN3_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_sw_config_SHIFT)) & IOMUXD_ADC_IN3_sw_config_MASK)
61067#define IOMUXD_ADC_IN3_mux_mode_MASK (0x38000000U)
61068#define IOMUXD_ADC_IN3_mux_mode_SHIFT (27U)
61069/*! mux_mode - mux_mode
61070 * 0b000..ADMA.ADC.IN3
61071 * 0b001..M40.UART0.TX
61072 * 0b010..M40.GPIO0.IO03
61073 * 0b011..ADMA.ACM.MCLK_OUT0
61074 * 0b100..LSIO.GPIO1.IO11
61075 */
61076#define IOMUXD_ADC_IN3_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_mux_mode_SHIFT)) & IOMUXD_ADC_IN3_mux_mode_MASK)
61077#define IOMUXD_ADC_IN3_update_pad_ctl_MASK (0x40000000U)
61078#define IOMUXD_ADC_IN3_update_pad_ctl_SHIFT (30U)
61079/*! update_pad_ctl - update lock for pad control
61080 */
61081#define IOMUXD_ADC_IN3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN3_update_pad_ctl_MASK)
61082#define IOMUXD_ADC_IN3_update_mux_mode_MASK (0x80000000U)
61083#define IOMUXD_ADC_IN3_update_mux_mode_SHIFT (31U)
61084/*! update_mux_mode - update lock for mux control
61085 */
61086#define IOMUXD_ADC_IN3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN3_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN3_update_mux_mode_MASK)
61087/*! @} */
61088
61089/*! @name ADC_IN2 - ADC_IN2 */
61090/*! @{ */
61091#define IOMUXD_ADC_IN2_DSE_MASK (0x7U)
61092#define IOMUXD_ADC_IN2_DSE_SHIFT (0U)
61093/*! DSE - Drive
61094 * 0b001..Drive select 2mA
61095 * 0b011..Drive select 6mA
61096 * 0b111..High Speed
61097 * 0b110..Drive select 12mA
61098 * 0b010..Drive select 4mA
61099 * 0b100..Drive select 8mA
61100 * 0b000..Drive select 1mA
61101 * 0b101..Drive select 10mA
61102 */
61103#define IOMUXD_ADC_IN2_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_DSE_SHIFT)) & IOMUXD_ADC_IN2_DSE_MASK)
61104#define IOMUXD_ADC_IN2_ADC_IN2_reserved_3_4_MASK (0x18U)
61105#define IOMUXD_ADC_IN2_ADC_IN2_reserved_3_4_SHIFT (3U)
61106/*! ADC_IN2_reserved_3_4 - reserved
61107 */
61108#define IOMUXD_ADC_IN2_ADC_IN2_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_ADC_IN2_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN2_ADC_IN2_reserved_3_4_MASK)
61109#define IOMUXD_ADC_IN2_PULL_MASK (0x60U)
61110#define IOMUXD_ADC_IN2_PULL_SHIFT (5U)
61111/*! PULL - Pull Down Pull Up
61112 * 0b00..Bus-Keeper
61113 * 0b10..pull down
61114 * 0b01..pull up
61115 * 0b11..No Pull
61116 */
61117#define IOMUXD_ADC_IN2_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_PULL_SHIFT)) & IOMUXD_ADC_IN2_PULL_MASK)
61118#define IOMUXD_ADC_IN2_ADC_IN2_reserved_7_18_MASK (0x7FF80U)
61119#define IOMUXD_ADC_IN2_ADC_IN2_reserved_7_18_SHIFT (7U)
61120/*! ADC_IN2_reserved_7_18 - reserved
61121 */
61122#define IOMUXD_ADC_IN2_ADC_IN2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_ADC_IN2_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN2_ADC_IN2_reserved_7_18_MASK)
61123#define IOMUXD_ADC_IN2_WAKEUP_CTRL_MASK (0x380000U)
61124#define IOMUXD_ADC_IN2_WAKEUP_CTRL_SHIFT (19U)
61125/*! WAKEUP_CTRL - wakeup control
61126 * 0b000..OFF
61127 * 0b001..RESAMPLE
61128 * 0b100..LOW
61129 * 0b111..HIGH
61130 * 0b110..RISE
61131 * 0b101..FALL
61132 */
61133#define IOMUXD_ADC_IN2_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN2_WAKEUP_CTRL_MASK)
61134#define IOMUXD_ADC_IN2_WAKEUP_MASK_MASK (0x400000U)
61135#define IOMUXD_ADC_IN2_WAKEUP_MASK_SHIFT (22U)
61136/*! WAKEUP_MASK - wakeup mask
61137 */
61138#define IOMUXD_ADC_IN2_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN2_WAKEUP_MASK_MASK)
61139#define IOMUXD_ADC_IN2_lp_config_MASK (0x1800000U)
61140#define IOMUXD_ADC_IN2_lp_config_SHIFT (23U)
61141/*! lp_config - lower power configuration
61142 * 0b01..EARLY_ISO
61143 * 0b10..LATE_ISO
61144 * 0b11..LATCH
61145 * 0b00..PASS
61146 */
61147#define IOMUXD_ADC_IN2_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_lp_config_SHIFT)) & IOMUXD_ADC_IN2_lp_config_MASK)
61148#define IOMUXD_ADC_IN2_sw_config_MASK (0x6000000U)
61149#define IOMUXD_ADC_IN2_sw_config_SHIFT (25U)
61150/*! sw_config - output and input configuration
61151 * 0b01..OPEN_DRAIN
61152 * 0b10..OPEN_DRAIN_INPUT
61153 * 0b11..INOUT
61154 * 0b00..DEFAULT
61155 */
61156#define IOMUXD_ADC_IN2_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_sw_config_SHIFT)) & IOMUXD_ADC_IN2_sw_config_MASK)
61157#define IOMUXD_ADC_IN2_mux_mode_MASK (0x38000000U)
61158#define IOMUXD_ADC_IN2_mux_mode_SHIFT (27U)
61159/*! mux_mode - mux_mode
61160 * 0b000..ADMA.ADC.IN2
61161 * 0b001..M40.UART0.RX
61162 * 0b010..M40.GPIO0.IO02
61163 * 0b011..ADMA.ACM.MCLK_IN0
61164 * 0b100..LSIO.GPIO1.IO12
61165 */
61166#define IOMUXD_ADC_IN2_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_mux_mode_SHIFT)) & IOMUXD_ADC_IN2_mux_mode_MASK)
61167#define IOMUXD_ADC_IN2_update_pad_ctl_MASK (0x40000000U)
61168#define IOMUXD_ADC_IN2_update_pad_ctl_SHIFT (30U)
61169/*! update_pad_ctl - update lock for pad control
61170 */
61171#define IOMUXD_ADC_IN2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN2_update_pad_ctl_MASK)
61172#define IOMUXD_ADC_IN2_update_mux_mode_MASK (0x80000000U)
61173#define IOMUXD_ADC_IN2_update_mux_mode_SHIFT (31U)
61174/*! update_mux_mode - update lock for mux control
61175 */
61176#define IOMUXD_ADC_IN2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN2_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN2_update_mux_mode_MASK)
61177/*! @} */
61178
61179/*! @name ADC_IN5 - ADC_IN5 */
61180/*! @{ */
61181#define IOMUXD_ADC_IN5_DSE_MASK (0x7U)
61182#define IOMUXD_ADC_IN5_DSE_SHIFT (0U)
61183/*! DSE - Drive
61184 * 0b001..Drive select 2mA
61185 * 0b011..Drive select 6mA
61186 * 0b111..High Speed
61187 * 0b110..Drive select 12mA
61188 * 0b010..Drive select 4mA
61189 * 0b100..Drive select 8mA
61190 * 0b000..Drive select 1mA
61191 * 0b101..Drive select 10mA
61192 */
61193#define IOMUXD_ADC_IN5_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_DSE_SHIFT)) & IOMUXD_ADC_IN5_DSE_MASK)
61194#define IOMUXD_ADC_IN5_ADC_IN5_reserved_3_4_MASK (0x18U)
61195#define IOMUXD_ADC_IN5_ADC_IN5_reserved_3_4_SHIFT (3U)
61196/*! ADC_IN5_reserved_3_4 - reserved
61197 */
61198#define IOMUXD_ADC_IN5_ADC_IN5_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_ADC_IN5_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN5_ADC_IN5_reserved_3_4_MASK)
61199#define IOMUXD_ADC_IN5_PULL_MASK (0x60U)
61200#define IOMUXD_ADC_IN5_PULL_SHIFT (5U)
61201/*! PULL - Pull Down Pull Up
61202 * 0b00..Bus-Keeper
61203 * 0b10..pull down
61204 * 0b01..pull up
61205 * 0b11..No Pull
61206 */
61207#define IOMUXD_ADC_IN5_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_PULL_SHIFT)) & IOMUXD_ADC_IN5_PULL_MASK)
61208#define IOMUXD_ADC_IN5_ADC_IN5_reserved_7_18_MASK (0x7FF80U)
61209#define IOMUXD_ADC_IN5_ADC_IN5_reserved_7_18_SHIFT (7U)
61210/*! ADC_IN5_reserved_7_18 - reserved
61211 */
61212#define IOMUXD_ADC_IN5_ADC_IN5_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_ADC_IN5_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN5_ADC_IN5_reserved_7_18_MASK)
61213#define IOMUXD_ADC_IN5_WAKEUP_CTRL_MASK (0x380000U)
61214#define IOMUXD_ADC_IN5_WAKEUP_CTRL_SHIFT (19U)
61215/*! WAKEUP_CTRL - wakeup control
61216 * 0b000..OFF
61217 * 0b001..RESAMPLE
61218 * 0b100..LOW
61219 * 0b111..HIGH
61220 * 0b110..RISE
61221 * 0b101..FALL
61222 */
61223#define IOMUXD_ADC_IN5_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN5_WAKEUP_CTRL_MASK)
61224#define IOMUXD_ADC_IN5_WAKEUP_MASK_MASK (0x400000U)
61225#define IOMUXD_ADC_IN5_WAKEUP_MASK_SHIFT (22U)
61226/*! WAKEUP_MASK - wakeup mask
61227 */
61228#define IOMUXD_ADC_IN5_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN5_WAKEUP_MASK_MASK)
61229#define IOMUXD_ADC_IN5_lp_config_MASK (0x1800000U)
61230#define IOMUXD_ADC_IN5_lp_config_SHIFT (23U)
61231/*! lp_config - lower power configuration
61232 * 0b01..EARLY_ISO
61233 * 0b10..LATE_ISO
61234 * 0b11..LATCH
61235 * 0b00..PASS
61236 */
61237#define IOMUXD_ADC_IN5_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_lp_config_SHIFT)) & IOMUXD_ADC_IN5_lp_config_MASK)
61238#define IOMUXD_ADC_IN5_sw_config_MASK (0x6000000U)
61239#define IOMUXD_ADC_IN5_sw_config_SHIFT (25U)
61240/*! sw_config - output and input configuration
61241 * 0b01..OPEN_DRAIN
61242 * 0b10..OPEN_DRAIN_INPUT
61243 * 0b11..INOUT
61244 * 0b00..DEFAULT
61245 */
61246#define IOMUXD_ADC_IN5_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_sw_config_SHIFT)) & IOMUXD_ADC_IN5_sw_config_MASK)
61247#define IOMUXD_ADC_IN5_mux_mode_MASK (0x38000000U)
61248#define IOMUXD_ADC_IN5_mux_mode_SHIFT (27U)
61249/*! mux_mode - mux_mode
61250 * 0b000..ADMA.ADC.IN5
61251 * 0b001..M40.TPM0.CH1
61252 * 0b010..M40.GPIO0.IO05
61253 * 0b100..LSIO.GPIO1.IO13
61254 */
61255#define IOMUXD_ADC_IN5_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_mux_mode_SHIFT)) & IOMUXD_ADC_IN5_mux_mode_MASK)
61256#define IOMUXD_ADC_IN5_update_pad_ctl_MASK (0x40000000U)
61257#define IOMUXD_ADC_IN5_update_pad_ctl_SHIFT (30U)
61258/*! update_pad_ctl - update lock for pad control
61259 */
61260#define IOMUXD_ADC_IN5_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN5_update_pad_ctl_MASK)
61261#define IOMUXD_ADC_IN5_update_mux_mode_MASK (0x80000000U)
61262#define IOMUXD_ADC_IN5_update_mux_mode_SHIFT (31U)
61263/*! update_mux_mode - update lock for mux control
61264 */
61265#define IOMUXD_ADC_IN5_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN5_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN5_update_mux_mode_MASK)
61266/*! @} */
61267
61268/*! @name ADC_IN4 - ADC_IN4 */
61269/*! @{ */
61270#define IOMUXD_ADC_IN4_DSE_MASK (0x7U)
61271#define IOMUXD_ADC_IN4_DSE_SHIFT (0U)
61272/*! DSE - Drive
61273 * 0b001..Drive select 2mA
61274 * 0b011..Drive select 6mA
61275 * 0b111..High Speed
61276 * 0b110..Drive select 12mA
61277 * 0b010..Drive select 4mA
61278 * 0b100..Drive select 8mA
61279 * 0b000..Drive select 1mA
61280 * 0b101..Drive select 10mA
61281 */
61282#define IOMUXD_ADC_IN4_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_DSE_SHIFT)) & IOMUXD_ADC_IN4_DSE_MASK)
61283#define IOMUXD_ADC_IN4_ADC_IN4_reserved_3_4_MASK (0x18U)
61284#define IOMUXD_ADC_IN4_ADC_IN4_reserved_3_4_SHIFT (3U)
61285/*! ADC_IN4_reserved_3_4 - reserved
61286 */
61287#define IOMUXD_ADC_IN4_ADC_IN4_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_ADC_IN4_reserved_3_4_SHIFT)) & IOMUXD_ADC_IN4_ADC_IN4_reserved_3_4_MASK)
61288#define IOMUXD_ADC_IN4_PULL_MASK (0x60U)
61289#define IOMUXD_ADC_IN4_PULL_SHIFT (5U)
61290/*! PULL - Pull Down Pull Up
61291 * 0b00..Bus-Keeper
61292 * 0b10..pull down
61293 * 0b01..pull up
61294 * 0b11..No Pull
61295 */
61296#define IOMUXD_ADC_IN4_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_PULL_SHIFT)) & IOMUXD_ADC_IN4_PULL_MASK)
61297#define IOMUXD_ADC_IN4_ADC_IN4_reserved_7_18_MASK (0x7FF80U)
61298#define IOMUXD_ADC_IN4_ADC_IN4_reserved_7_18_SHIFT (7U)
61299/*! ADC_IN4_reserved_7_18 - reserved
61300 */
61301#define IOMUXD_ADC_IN4_ADC_IN4_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_ADC_IN4_reserved_7_18_SHIFT)) & IOMUXD_ADC_IN4_ADC_IN4_reserved_7_18_MASK)
61302#define IOMUXD_ADC_IN4_WAKEUP_CTRL_MASK (0x380000U)
61303#define IOMUXD_ADC_IN4_WAKEUP_CTRL_SHIFT (19U)
61304/*! WAKEUP_CTRL - wakeup control
61305 * 0b000..OFF
61306 * 0b001..RESAMPLE
61307 * 0b100..LOW
61308 * 0b111..HIGH
61309 * 0b110..RISE
61310 * 0b101..FALL
61311 */
61312#define IOMUXD_ADC_IN4_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_WAKEUP_CTRL_SHIFT)) & IOMUXD_ADC_IN4_WAKEUP_CTRL_MASK)
61313#define IOMUXD_ADC_IN4_WAKEUP_MASK_MASK (0x400000U)
61314#define IOMUXD_ADC_IN4_WAKEUP_MASK_SHIFT (22U)
61315/*! WAKEUP_MASK - wakeup mask
61316 */
61317#define IOMUXD_ADC_IN4_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_WAKEUP_MASK_SHIFT)) & IOMUXD_ADC_IN4_WAKEUP_MASK_MASK)
61318#define IOMUXD_ADC_IN4_lp_config_MASK (0x1800000U)
61319#define IOMUXD_ADC_IN4_lp_config_SHIFT (23U)
61320/*! lp_config - lower power configuration
61321 * 0b01..EARLY_ISO
61322 * 0b10..LATE_ISO
61323 * 0b11..LATCH
61324 * 0b00..PASS
61325 */
61326#define IOMUXD_ADC_IN4_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_lp_config_SHIFT)) & IOMUXD_ADC_IN4_lp_config_MASK)
61327#define IOMUXD_ADC_IN4_sw_config_MASK (0x6000000U)
61328#define IOMUXD_ADC_IN4_sw_config_SHIFT (25U)
61329/*! sw_config - output and input configuration
61330 * 0b01..OPEN_DRAIN
61331 * 0b10..OPEN_DRAIN_INPUT
61332 * 0b11..INOUT
61333 * 0b00..DEFAULT
61334 */
61335#define IOMUXD_ADC_IN4_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_sw_config_SHIFT)) & IOMUXD_ADC_IN4_sw_config_MASK)
61336#define IOMUXD_ADC_IN4_mux_mode_MASK (0x38000000U)
61337#define IOMUXD_ADC_IN4_mux_mode_SHIFT (27U)
61338/*! mux_mode - mux_mode
61339 * 0b000..ADMA.ADC.IN4
61340 * 0b001..M40.TPM0.CH0
61341 * 0b010..M40.GPIO0.IO04
61342 * 0b100..LSIO.GPIO1.IO14
61343 */
61344#define IOMUXD_ADC_IN4_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_mux_mode_SHIFT)) & IOMUXD_ADC_IN4_mux_mode_MASK)
61345#define IOMUXD_ADC_IN4_update_pad_ctl_MASK (0x40000000U)
61346#define IOMUXD_ADC_IN4_update_pad_ctl_SHIFT (30U)
61347/*! update_pad_ctl - update lock for pad control
61348 */
61349#define IOMUXD_ADC_IN4_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_update_pad_ctl_SHIFT)) & IOMUXD_ADC_IN4_update_pad_ctl_MASK)
61350#define IOMUXD_ADC_IN4_update_mux_mode_MASK (0x80000000U)
61351#define IOMUXD_ADC_IN4_update_mux_mode_SHIFT (31U)
61352/*! update_mux_mode - update lock for mux control
61353 */
61354#define IOMUXD_ADC_IN4_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_ADC_IN4_update_mux_mode_SHIFT)) & IOMUXD_ADC_IN4_update_mux_mode_MASK)
61355/*! @} */
61356
61357/*! @name FLEXCAN0_RX - FLEXCAN0_RX */
61358/*! @{ */
61359#define IOMUXD_FLEXCAN0_RX_PDRV_MASK (0x1U)
61360#define IOMUXD_FLEXCAN0_RX_PDRV_SHIFT (0U)
61361/*! PDRV - Drive
61362 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
61363 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
61364 */
61365#define IOMUXD_FLEXCAN0_RX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_PDRV_SHIFT)) & IOMUXD_FLEXCAN0_RX_PDRV_MASK)
61366#define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_1_4_MASK (0x1EU)
61367#define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_1_4_SHIFT (1U)
61368/*! FLEXCAN0_RX_reserved_1_4 - reserved
61369 */
61370#define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_1_4_MASK)
61371#define IOMUXD_FLEXCAN0_RX_PULL_MASK (0x60U)
61372#define IOMUXD_FLEXCAN0_RX_PULL_SHIFT (5U)
61373/*! PULL - Pull Down Pull Up
61374 * 0b10..pull down
61375 * 0b01..pull up
61376 * 0b00..Prohibited
61377 * 0b11..pull disabled
61378 */
61379#define IOMUXD_FLEXCAN0_RX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_PULL_SHIFT)) & IOMUXD_FLEXCAN0_RX_PULL_MASK)
61380#define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_7_18_MASK (0x7FF80U)
61381#define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_7_18_SHIFT (7U)
61382/*! FLEXCAN0_RX_reserved_7_18 - reserved
61383 */
61384#define IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN0_RX_FLEXCAN0_RX_reserved_7_18_MASK)
61385#define IOMUXD_FLEXCAN0_RX_WAKEUP_CTRL_MASK (0x380000U)
61386#define IOMUXD_FLEXCAN0_RX_WAKEUP_CTRL_SHIFT (19U)
61387/*! WAKEUP_CTRL - wakeup control
61388 * 0b000..OFF
61389 * 0b001..RESAMPLE
61390 * 0b100..LOW
61391 * 0b111..HIGH
61392 * 0b110..RISE
61393 * 0b101..FALL
61394 */
61395#define IOMUXD_FLEXCAN0_RX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN0_RX_WAKEUP_CTRL_MASK)
61396#define IOMUXD_FLEXCAN0_RX_WAKEUP_MASK_MASK (0x400000U)
61397#define IOMUXD_FLEXCAN0_RX_WAKEUP_MASK_SHIFT (22U)
61398/*! WAKEUP_MASK - wakeup mask
61399 */
61400#define IOMUXD_FLEXCAN0_RX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN0_RX_WAKEUP_MASK_MASK)
61401#define IOMUXD_FLEXCAN0_RX_lp_config_MASK (0x1800000U)
61402#define IOMUXD_FLEXCAN0_RX_lp_config_SHIFT (23U)
61403/*! lp_config - lower power configuration
61404 * 0b01..EARLY_ISO
61405 * 0b10..LATE_ISO
61406 * 0b11..LATCH
61407 * 0b00..PASS
61408 */
61409#define IOMUXD_FLEXCAN0_RX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_lp_config_SHIFT)) & IOMUXD_FLEXCAN0_RX_lp_config_MASK)
61410#define IOMUXD_FLEXCAN0_RX_sw_config_MASK (0x6000000U)
61411#define IOMUXD_FLEXCAN0_RX_sw_config_SHIFT (25U)
61412/*! sw_config - output and input configuration
61413 * 0b01..OPEN_DRAIN
61414 * 0b10..OPEN_DRAIN_INPUT
61415 * 0b11..INOUT
61416 * 0b00..DEFAULT
61417 */
61418#define IOMUXD_FLEXCAN0_RX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_sw_config_SHIFT)) & IOMUXD_FLEXCAN0_RX_sw_config_MASK)
61419#define IOMUXD_FLEXCAN0_RX_mux_mode_MASK (0x38000000U)
61420#define IOMUXD_FLEXCAN0_RX_mux_mode_SHIFT (27U)
61421/*! mux_mode - mux_mode
61422 * 0b000..ADMA.FLEXCAN0.RX
61423 * 0b001..ADMA.SAI2.RXC
61424 * 0b010..ADMA.UART0.RTS_B
61425 * 0b011..ADMA.SAI1.TXC
61426 * 0b100..LSIO.GPIO1.IO15
61427 */
61428#define IOMUXD_FLEXCAN0_RX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN0_RX_mux_mode_MASK)
61429#define IOMUXD_FLEXCAN0_RX_update_pad_ctl_MASK (0x40000000U)
61430#define IOMUXD_FLEXCAN0_RX_update_pad_ctl_SHIFT (30U)
61431/*! update_pad_ctl - update lock for pad control
61432 */
61433#define IOMUXD_FLEXCAN0_RX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN0_RX_update_pad_ctl_MASK)
61434#define IOMUXD_FLEXCAN0_RX_update_mux_mode_MASK (0x80000000U)
61435#define IOMUXD_FLEXCAN0_RX_update_mux_mode_SHIFT (31U)
61436/*! update_mux_mode - update lock for mux control
61437 */
61438#define IOMUXD_FLEXCAN0_RX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_RX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN0_RX_update_mux_mode_MASK)
61439/*! @} */
61440
61441/*! @name FLEXCAN0_TX - FLEXCAN0_TX */
61442/*! @{ */
61443#define IOMUXD_FLEXCAN0_TX_PDRV_MASK (0x1U)
61444#define IOMUXD_FLEXCAN0_TX_PDRV_SHIFT (0U)
61445/*! PDRV - Drive
61446 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
61447 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
61448 */
61449#define IOMUXD_FLEXCAN0_TX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_PDRV_SHIFT)) & IOMUXD_FLEXCAN0_TX_PDRV_MASK)
61450#define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_1_4_MASK (0x1EU)
61451#define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_1_4_SHIFT (1U)
61452/*! FLEXCAN0_TX_reserved_1_4 - reserved
61453 */
61454#define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_1_4_MASK)
61455#define IOMUXD_FLEXCAN0_TX_PULL_MASK (0x60U)
61456#define IOMUXD_FLEXCAN0_TX_PULL_SHIFT (5U)
61457/*! PULL - Pull Down Pull Up
61458 * 0b10..pull down
61459 * 0b01..pull up
61460 * 0b00..Prohibited
61461 * 0b11..pull disabled
61462 */
61463#define IOMUXD_FLEXCAN0_TX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_PULL_SHIFT)) & IOMUXD_FLEXCAN0_TX_PULL_MASK)
61464#define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_7_18_MASK (0x7FF80U)
61465#define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_7_18_SHIFT (7U)
61466/*! FLEXCAN0_TX_reserved_7_18 - reserved
61467 */
61468#define IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN0_TX_FLEXCAN0_TX_reserved_7_18_MASK)
61469#define IOMUXD_FLEXCAN0_TX_WAKEUP_CTRL_MASK (0x380000U)
61470#define IOMUXD_FLEXCAN0_TX_WAKEUP_CTRL_SHIFT (19U)
61471/*! WAKEUP_CTRL - wakeup control
61472 * 0b000..OFF
61473 * 0b001..RESAMPLE
61474 * 0b100..LOW
61475 * 0b111..HIGH
61476 * 0b110..RISE
61477 * 0b101..FALL
61478 */
61479#define IOMUXD_FLEXCAN0_TX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN0_TX_WAKEUP_CTRL_MASK)
61480#define IOMUXD_FLEXCAN0_TX_WAKEUP_MASK_MASK (0x400000U)
61481#define IOMUXD_FLEXCAN0_TX_WAKEUP_MASK_SHIFT (22U)
61482/*! WAKEUP_MASK - wakeup mask
61483 */
61484#define IOMUXD_FLEXCAN0_TX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN0_TX_WAKEUP_MASK_MASK)
61485#define IOMUXD_FLEXCAN0_TX_lp_config_MASK (0x1800000U)
61486#define IOMUXD_FLEXCAN0_TX_lp_config_SHIFT (23U)
61487/*! lp_config - lower power configuration
61488 * 0b01..EARLY_ISO
61489 * 0b10..LATE_ISO
61490 * 0b11..LATCH
61491 * 0b00..PASS
61492 */
61493#define IOMUXD_FLEXCAN0_TX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_lp_config_SHIFT)) & IOMUXD_FLEXCAN0_TX_lp_config_MASK)
61494#define IOMUXD_FLEXCAN0_TX_sw_config_MASK (0x6000000U)
61495#define IOMUXD_FLEXCAN0_TX_sw_config_SHIFT (25U)
61496/*! sw_config - output and input configuration
61497 * 0b01..OPEN_DRAIN
61498 * 0b10..OPEN_DRAIN_INPUT
61499 * 0b11..INOUT
61500 * 0b00..DEFAULT
61501 */
61502#define IOMUXD_FLEXCAN0_TX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_sw_config_SHIFT)) & IOMUXD_FLEXCAN0_TX_sw_config_MASK)
61503#define IOMUXD_FLEXCAN0_TX_mux_mode_MASK (0x38000000U)
61504#define IOMUXD_FLEXCAN0_TX_mux_mode_SHIFT (27U)
61505/*! mux_mode - mux_mode
61506 * 0b000..ADMA.FLEXCAN0.TX
61507 * 0b001..ADMA.SAI2.RXD
61508 * 0b010..ADMA.UART0.CTS_B
61509 * 0b011..ADMA.SAI1.TXFS
61510 * 0b100..LSIO.GPIO1.IO16
61511 */
61512#define IOMUXD_FLEXCAN0_TX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN0_TX_mux_mode_MASK)
61513#define IOMUXD_FLEXCAN0_TX_update_pad_ctl_MASK (0x40000000U)
61514#define IOMUXD_FLEXCAN0_TX_update_pad_ctl_SHIFT (30U)
61515/*! update_pad_ctl - update lock for pad control
61516 */
61517#define IOMUXD_FLEXCAN0_TX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN0_TX_update_pad_ctl_MASK)
61518#define IOMUXD_FLEXCAN0_TX_update_mux_mode_MASK (0x80000000U)
61519#define IOMUXD_FLEXCAN0_TX_update_mux_mode_SHIFT (31U)
61520/*! update_mux_mode - update lock for mux control
61521 */
61522#define IOMUXD_FLEXCAN0_TX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN0_TX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN0_TX_update_mux_mode_MASK)
61523/*! @} */
61524
61525/*! @name FLEXCAN1_RX - FLEXCAN1_RX */
61526/*! @{ */
61527#define IOMUXD_FLEXCAN1_RX_PDRV_MASK (0x1U)
61528#define IOMUXD_FLEXCAN1_RX_PDRV_SHIFT (0U)
61529/*! PDRV - Drive
61530 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
61531 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
61532 */
61533#define IOMUXD_FLEXCAN1_RX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_PDRV_SHIFT)) & IOMUXD_FLEXCAN1_RX_PDRV_MASK)
61534#define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_1_4_MASK (0x1EU)
61535#define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_1_4_SHIFT (1U)
61536/*! FLEXCAN1_RX_reserved_1_4 - reserved
61537 */
61538#define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_1_4_MASK)
61539#define IOMUXD_FLEXCAN1_RX_PULL_MASK (0x60U)
61540#define IOMUXD_FLEXCAN1_RX_PULL_SHIFT (5U)
61541/*! PULL - Pull Down Pull Up
61542 * 0b10..pull down
61543 * 0b01..pull up
61544 * 0b00..Prohibited
61545 * 0b11..pull disabled
61546 */
61547#define IOMUXD_FLEXCAN1_RX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_PULL_SHIFT)) & IOMUXD_FLEXCAN1_RX_PULL_MASK)
61548#define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_7_18_MASK (0x7FF80U)
61549#define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_7_18_SHIFT (7U)
61550/*! FLEXCAN1_RX_reserved_7_18 - reserved
61551 */
61552#define IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN1_RX_FLEXCAN1_RX_reserved_7_18_MASK)
61553#define IOMUXD_FLEXCAN1_RX_WAKEUP_CTRL_MASK (0x380000U)
61554#define IOMUXD_FLEXCAN1_RX_WAKEUP_CTRL_SHIFT (19U)
61555/*! WAKEUP_CTRL - wakeup control
61556 * 0b000..OFF
61557 * 0b001..RESAMPLE
61558 * 0b100..LOW
61559 * 0b111..HIGH
61560 * 0b110..RISE
61561 * 0b101..FALL
61562 */
61563#define IOMUXD_FLEXCAN1_RX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN1_RX_WAKEUP_CTRL_MASK)
61564#define IOMUXD_FLEXCAN1_RX_WAKEUP_MASK_MASK (0x400000U)
61565#define IOMUXD_FLEXCAN1_RX_WAKEUP_MASK_SHIFT (22U)
61566/*! WAKEUP_MASK - wakeup mask
61567 */
61568#define IOMUXD_FLEXCAN1_RX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN1_RX_WAKEUP_MASK_MASK)
61569#define IOMUXD_FLEXCAN1_RX_lp_config_MASK (0x1800000U)
61570#define IOMUXD_FLEXCAN1_RX_lp_config_SHIFT (23U)
61571/*! lp_config - lower power configuration
61572 * 0b01..EARLY_ISO
61573 * 0b10..LATE_ISO
61574 * 0b11..LATCH
61575 * 0b00..PASS
61576 */
61577#define IOMUXD_FLEXCAN1_RX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_lp_config_SHIFT)) & IOMUXD_FLEXCAN1_RX_lp_config_MASK)
61578#define IOMUXD_FLEXCAN1_RX_sw_config_MASK (0x6000000U)
61579#define IOMUXD_FLEXCAN1_RX_sw_config_SHIFT (25U)
61580/*! sw_config - output and input configuration
61581 * 0b01..OPEN_DRAIN
61582 * 0b10..OPEN_DRAIN_INPUT
61583 * 0b11..INOUT
61584 * 0b00..DEFAULT
61585 */
61586#define IOMUXD_FLEXCAN1_RX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_sw_config_SHIFT)) & IOMUXD_FLEXCAN1_RX_sw_config_MASK)
61587#define IOMUXD_FLEXCAN1_RX_mux_mode_MASK (0x38000000U)
61588#define IOMUXD_FLEXCAN1_RX_mux_mode_SHIFT (27U)
61589/*! mux_mode - mux_mode
61590 * 0b000..ADMA.FLEXCAN1.RX
61591 * 0b001..ADMA.SAI2.RXFS
61592 * 0b010..ADMA.FTM.CH2
61593 * 0b011..ADMA.SAI1.TXD
61594 * 0b100..LSIO.GPIO1.IO17
61595 */
61596#define IOMUXD_FLEXCAN1_RX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN1_RX_mux_mode_MASK)
61597#define IOMUXD_FLEXCAN1_RX_update_pad_ctl_MASK (0x40000000U)
61598#define IOMUXD_FLEXCAN1_RX_update_pad_ctl_SHIFT (30U)
61599/*! update_pad_ctl - update lock for pad control
61600 */
61601#define IOMUXD_FLEXCAN1_RX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN1_RX_update_pad_ctl_MASK)
61602#define IOMUXD_FLEXCAN1_RX_update_mux_mode_MASK (0x80000000U)
61603#define IOMUXD_FLEXCAN1_RX_update_mux_mode_SHIFT (31U)
61604/*! update_mux_mode - update lock for mux control
61605 */
61606#define IOMUXD_FLEXCAN1_RX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_RX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN1_RX_update_mux_mode_MASK)
61607/*! @} */
61608
61609/*! @name FLEXCAN1_TX - FLEXCAN1_TX */
61610/*! @{ */
61611#define IOMUXD_FLEXCAN1_TX_PDRV_MASK (0x1U)
61612#define IOMUXD_FLEXCAN1_TX_PDRV_SHIFT (0U)
61613/*! PDRV - Drive
61614 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
61615 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
61616 */
61617#define IOMUXD_FLEXCAN1_TX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_PDRV_SHIFT)) & IOMUXD_FLEXCAN1_TX_PDRV_MASK)
61618#define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_1_4_MASK (0x1EU)
61619#define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_1_4_SHIFT (1U)
61620/*! FLEXCAN1_TX_reserved_1_4 - reserved
61621 */
61622#define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_1_4_MASK)
61623#define IOMUXD_FLEXCAN1_TX_PULL_MASK (0x60U)
61624#define IOMUXD_FLEXCAN1_TX_PULL_SHIFT (5U)
61625/*! PULL - Pull Down Pull Up
61626 * 0b10..pull down
61627 * 0b01..pull up
61628 * 0b00..Prohibited
61629 * 0b11..pull disabled
61630 */
61631#define IOMUXD_FLEXCAN1_TX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_PULL_SHIFT)) & IOMUXD_FLEXCAN1_TX_PULL_MASK)
61632#define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_7_18_MASK (0x7FF80U)
61633#define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_7_18_SHIFT (7U)
61634/*! FLEXCAN1_TX_reserved_7_18 - reserved
61635 */
61636#define IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN1_TX_FLEXCAN1_TX_reserved_7_18_MASK)
61637#define IOMUXD_FLEXCAN1_TX_WAKEUP_CTRL_MASK (0x380000U)
61638#define IOMUXD_FLEXCAN1_TX_WAKEUP_CTRL_SHIFT (19U)
61639/*! WAKEUP_CTRL - wakeup control
61640 * 0b000..OFF
61641 * 0b001..RESAMPLE
61642 * 0b100..LOW
61643 * 0b111..HIGH
61644 * 0b110..RISE
61645 * 0b101..FALL
61646 */
61647#define IOMUXD_FLEXCAN1_TX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN1_TX_WAKEUP_CTRL_MASK)
61648#define IOMUXD_FLEXCAN1_TX_WAKEUP_MASK_MASK (0x400000U)
61649#define IOMUXD_FLEXCAN1_TX_WAKEUP_MASK_SHIFT (22U)
61650/*! WAKEUP_MASK - wakeup mask
61651 */
61652#define IOMUXD_FLEXCAN1_TX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN1_TX_WAKEUP_MASK_MASK)
61653#define IOMUXD_FLEXCAN1_TX_lp_config_MASK (0x1800000U)
61654#define IOMUXD_FLEXCAN1_TX_lp_config_SHIFT (23U)
61655/*! lp_config - lower power configuration
61656 * 0b01..EARLY_ISO
61657 * 0b10..LATE_ISO
61658 * 0b11..LATCH
61659 * 0b00..PASS
61660 */
61661#define IOMUXD_FLEXCAN1_TX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_lp_config_SHIFT)) & IOMUXD_FLEXCAN1_TX_lp_config_MASK)
61662#define IOMUXD_FLEXCAN1_TX_sw_config_MASK (0x6000000U)
61663#define IOMUXD_FLEXCAN1_TX_sw_config_SHIFT (25U)
61664/*! sw_config - output and input configuration
61665 * 0b01..OPEN_DRAIN
61666 * 0b10..OPEN_DRAIN_INPUT
61667 * 0b11..INOUT
61668 * 0b00..DEFAULT
61669 */
61670#define IOMUXD_FLEXCAN1_TX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_sw_config_SHIFT)) & IOMUXD_FLEXCAN1_TX_sw_config_MASK)
61671#define IOMUXD_FLEXCAN1_TX_mux_mode_MASK (0x38000000U)
61672#define IOMUXD_FLEXCAN1_TX_mux_mode_SHIFT (27U)
61673/*! mux_mode - mux_mode
61674 * 0b000..ADMA.FLEXCAN1.TX
61675 * 0b001..ADMA.SAI3.RXC
61676 * 0b010..ADMA.DMA0.REQ_IN0
61677 * 0b011..ADMA.SAI1.RXD
61678 * 0b100..LSIO.GPIO1.IO18
61679 */
61680#define IOMUXD_FLEXCAN1_TX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN1_TX_mux_mode_MASK)
61681#define IOMUXD_FLEXCAN1_TX_update_pad_ctl_MASK (0x40000000U)
61682#define IOMUXD_FLEXCAN1_TX_update_pad_ctl_SHIFT (30U)
61683/*! update_pad_ctl - update lock for pad control
61684 */
61685#define IOMUXD_FLEXCAN1_TX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN1_TX_update_pad_ctl_MASK)
61686#define IOMUXD_FLEXCAN1_TX_update_mux_mode_MASK (0x80000000U)
61687#define IOMUXD_FLEXCAN1_TX_update_mux_mode_SHIFT (31U)
61688/*! update_mux_mode - update lock for mux control
61689 */
61690#define IOMUXD_FLEXCAN1_TX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN1_TX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN1_TX_update_mux_mode_MASK)
61691/*! @} */
61692
61693/*! @name FLEXCAN2_RX - FLEXCAN2_RX */
61694/*! @{ */
61695#define IOMUXD_FLEXCAN2_RX_PDRV_MASK (0x1U)
61696#define IOMUXD_FLEXCAN2_RX_PDRV_SHIFT (0U)
61697/*! PDRV - Drive
61698 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
61699 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
61700 */
61701#define IOMUXD_FLEXCAN2_RX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_PDRV_SHIFT)) & IOMUXD_FLEXCAN2_RX_PDRV_MASK)
61702#define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_1_4_MASK (0x1EU)
61703#define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_1_4_SHIFT (1U)
61704/*! FLEXCAN2_RX_reserved_1_4 - reserved
61705 */
61706#define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_1_4_MASK)
61707#define IOMUXD_FLEXCAN2_RX_PULL_MASK (0x60U)
61708#define IOMUXD_FLEXCAN2_RX_PULL_SHIFT (5U)
61709/*! PULL - Pull Down Pull Up
61710 * 0b10..pull down
61711 * 0b01..pull up
61712 * 0b00..Prohibited
61713 * 0b11..pull disabled
61714 */
61715#define IOMUXD_FLEXCAN2_RX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_PULL_SHIFT)) & IOMUXD_FLEXCAN2_RX_PULL_MASK)
61716#define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_7_18_MASK (0x7FF80U)
61717#define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_7_18_SHIFT (7U)
61718/*! FLEXCAN2_RX_reserved_7_18 - reserved
61719 */
61720#define IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN2_RX_FLEXCAN2_RX_reserved_7_18_MASK)
61721#define IOMUXD_FLEXCAN2_RX_WAKEUP_CTRL_MASK (0x380000U)
61722#define IOMUXD_FLEXCAN2_RX_WAKEUP_CTRL_SHIFT (19U)
61723/*! WAKEUP_CTRL - wakeup control
61724 * 0b000..OFF
61725 * 0b001..RESAMPLE
61726 * 0b100..LOW
61727 * 0b111..HIGH
61728 * 0b110..RISE
61729 * 0b101..FALL
61730 */
61731#define IOMUXD_FLEXCAN2_RX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN2_RX_WAKEUP_CTRL_MASK)
61732#define IOMUXD_FLEXCAN2_RX_WAKEUP_MASK_MASK (0x400000U)
61733#define IOMUXD_FLEXCAN2_RX_WAKEUP_MASK_SHIFT (22U)
61734/*! WAKEUP_MASK - wakeup mask
61735 */
61736#define IOMUXD_FLEXCAN2_RX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN2_RX_WAKEUP_MASK_MASK)
61737#define IOMUXD_FLEXCAN2_RX_lp_config_MASK (0x1800000U)
61738#define IOMUXD_FLEXCAN2_RX_lp_config_SHIFT (23U)
61739/*! lp_config - lower power configuration
61740 * 0b01..EARLY_ISO
61741 * 0b10..LATE_ISO
61742 * 0b11..LATCH
61743 * 0b00..PASS
61744 */
61745#define IOMUXD_FLEXCAN2_RX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_lp_config_SHIFT)) & IOMUXD_FLEXCAN2_RX_lp_config_MASK)
61746#define IOMUXD_FLEXCAN2_RX_sw_config_MASK (0x6000000U)
61747#define IOMUXD_FLEXCAN2_RX_sw_config_SHIFT (25U)
61748/*! sw_config - output and input configuration
61749 * 0b01..OPEN_DRAIN
61750 * 0b10..OPEN_DRAIN_INPUT
61751 * 0b11..INOUT
61752 * 0b00..DEFAULT
61753 */
61754#define IOMUXD_FLEXCAN2_RX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_sw_config_SHIFT)) & IOMUXD_FLEXCAN2_RX_sw_config_MASK)
61755#define IOMUXD_FLEXCAN2_RX_mux_mode_MASK (0x38000000U)
61756#define IOMUXD_FLEXCAN2_RX_mux_mode_SHIFT (27U)
61757/*! mux_mode - mux_mode
61758 * 0b000..ADMA.FLEXCAN2.RX
61759 * 0b001..ADMA.SAI3.RXD
61760 * 0b010..ADMA.UART3.RX
61761 * 0b011..ADMA.SAI1.RXFS
61762 * 0b100..LSIO.GPIO1.IO19
61763 */
61764#define IOMUXD_FLEXCAN2_RX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN2_RX_mux_mode_MASK)
61765#define IOMUXD_FLEXCAN2_RX_update_pad_ctl_MASK (0x40000000U)
61766#define IOMUXD_FLEXCAN2_RX_update_pad_ctl_SHIFT (30U)
61767/*! update_pad_ctl - update lock for pad control
61768 */
61769#define IOMUXD_FLEXCAN2_RX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN2_RX_update_pad_ctl_MASK)
61770#define IOMUXD_FLEXCAN2_RX_update_mux_mode_MASK (0x80000000U)
61771#define IOMUXD_FLEXCAN2_RX_update_mux_mode_SHIFT (31U)
61772/*! update_mux_mode - update lock for mux control
61773 */
61774#define IOMUXD_FLEXCAN2_RX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_RX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN2_RX_update_mux_mode_MASK)
61775/*! @} */
61776
61777/*! @name FLEXCAN2_TX - FLEXCAN2_TX */
61778/*! @{ */
61779#define IOMUXD_FLEXCAN2_TX_PDRV_MASK (0x1U)
61780#define IOMUXD_FLEXCAN2_TX_PDRV_SHIFT (0U)
61781/*! PDRV - Drive
61782 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
61783 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
61784 */
61785#define IOMUXD_FLEXCAN2_TX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_PDRV_SHIFT)) & IOMUXD_FLEXCAN2_TX_PDRV_MASK)
61786#define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_1_4_MASK (0x1EU)
61787#define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_1_4_SHIFT (1U)
61788/*! FLEXCAN2_TX_reserved_1_4 - reserved
61789 */
61790#define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_1_4_SHIFT)) & IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_1_4_MASK)
61791#define IOMUXD_FLEXCAN2_TX_PULL_MASK (0x60U)
61792#define IOMUXD_FLEXCAN2_TX_PULL_SHIFT (5U)
61793/*! PULL - Pull Down Pull Up
61794 * 0b10..pull down
61795 * 0b01..pull up
61796 * 0b00..Prohibited
61797 * 0b11..pull disabled
61798 */
61799#define IOMUXD_FLEXCAN2_TX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_PULL_SHIFT)) & IOMUXD_FLEXCAN2_TX_PULL_MASK)
61800#define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_7_18_MASK (0x7FF80U)
61801#define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_7_18_SHIFT (7U)
61802/*! FLEXCAN2_TX_reserved_7_18 - reserved
61803 */
61804#define IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_7_18_SHIFT)) & IOMUXD_FLEXCAN2_TX_FLEXCAN2_TX_reserved_7_18_MASK)
61805#define IOMUXD_FLEXCAN2_TX_WAKEUP_CTRL_MASK (0x380000U)
61806#define IOMUXD_FLEXCAN2_TX_WAKEUP_CTRL_SHIFT (19U)
61807/*! WAKEUP_CTRL - wakeup control
61808 * 0b000..OFF
61809 * 0b001..RESAMPLE
61810 * 0b100..LOW
61811 * 0b111..HIGH
61812 * 0b110..RISE
61813 * 0b101..FALL
61814 */
61815#define IOMUXD_FLEXCAN2_TX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_FLEXCAN2_TX_WAKEUP_CTRL_MASK)
61816#define IOMUXD_FLEXCAN2_TX_WAKEUP_MASK_MASK (0x400000U)
61817#define IOMUXD_FLEXCAN2_TX_WAKEUP_MASK_SHIFT (22U)
61818/*! WAKEUP_MASK - wakeup mask
61819 */
61820#define IOMUXD_FLEXCAN2_TX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_FLEXCAN2_TX_WAKEUP_MASK_MASK)
61821#define IOMUXD_FLEXCAN2_TX_lp_config_MASK (0x1800000U)
61822#define IOMUXD_FLEXCAN2_TX_lp_config_SHIFT (23U)
61823/*! lp_config - lower power configuration
61824 * 0b01..EARLY_ISO
61825 * 0b10..LATE_ISO
61826 * 0b11..LATCH
61827 * 0b00..PASS
61828 */
61829#define IOMUXD_FLEXCAN2_TX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_lp_config_SHIFT)) & IOMUXD_FLEXCAN2_TX_lp_config_MASK)
61830#define IOMUXD_FLEXCAN2_TX_sw_config_MASK (0x6000000U)
61831#define IOMUXD_FLEXCAN2_TX_sw_config_SHIFT (25U)
61832/*! sw_config - output and input configuration
61833 * 0b01..OPEN_DRAIN
61834 * 0b10..OPEN_DRAIN_INPUT
61835 * 0b11..INOUT
61836 * 0b00..DEFAULT
61837 */
61838#define IOMUXD_FLEXCAN2_TX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_sw_config_SHIFT)) & IOMUXD_FLEXCAN2_TX_sw_config_MASK)
61839#define IOMUXD_FLEXCAN2_TX_mux_mode_MASK (0x38000000U)
61840#define IOMUXD_FLEXCAN2_TX_mux_mode_SHIFT (27U)
61841/*! mux_mode - mux_mode
61842 * 0b000..ADMA.FLEXCAN2.TX
61843 * 0b001..ADMA.SAI3.RXFS
61844 * 0b010..ADMA.UART3.TX
61845 * 0b011..ADMA.SAI1.RXC
61846 * 0b100..LSIO.GPIO1.IO20
61847 */
61848#define IOMUXD_FLEXCAN2_TX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_mux_mode_SHIFT)) & IOMUXD_FLEXCAN2_TX_mux_mode_MASK)
61849#define IOMUXD_FLEXCAN2_TX_update_pad_ctl_MASK (0x40000000U)
61850#define IOMUXD_FLEXCAN2_TX_update_pad_ctl_SHIFT (30U)
61851/*! update_pad_ctl - update lock for pad control
61852 */
61853#define IOMUXD_FLEXCAN2_TX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_update_pad_ctl_SHIFT)) & IOMUXD_FLEXCAN2_TX_update_pad_ctl_MASK)
61854#define IOMUXD_FLEXCAN2_TX_update_mux_mode_MASK (0x80000000U)
61855#define IOMUXD_FLEXCAN2_TX_update_mux_mode_SHIFT (31U)
61856/*! update_mux_mode - update lock for mux control
61857 */
61858#define IOMUXD_FLEXCAN2_TX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_FLEXCAN2_TX_update_mux_mode_SHIFT)) & IOMUXD_FLEXCAN2_TX_update_mux_mode_MASK)
61859/*! @} */
61860
61861/*! @name UART0_RX - UART0_RX */
61862/*! @{ */
61863#define IOMUXD_UART0_RX_PDRV_MASK (0x1U)
61864#define IOMUXD_UART0_RX_PDRV_SHIFT (0U)
61865/*! PDRV - Drive
61866 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
61867 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
61868 */
61869#define IOMUXD_UART0_RX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_PDRV_SHIFT)) & IOMUXD_UART0_RX_PDRV_MASK)
61870#define IOMUXD_UART0_RX_UART0_RX_reserved_1_4_MASK (0x1EU)
61871#define IOMUXD_UART0_RX_UART0_RX_reserved_1_4_SHIFT (1U)
61872/*! UART0_RX_reserved_1_4 - reserved
61873 */
61874#define IOMUXD_UART0_RX_UART0_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_UART0_RX_reserved_1_4_SHIFT)) & IOMUXD_UART0_RX_UART0_RX_reserved_1_4_MASK)
61875#define IOMUXD_UART0_RX_PULL_MASK (0x60U)
61876#define IOMUXD_UART0_RX_PULL_SHIFT (5U)
61877/*! PULL - Pull Down Pull Up
61878 * 0b10..pull down
61879 * 0b01..pull up
61880 * 0b00..Prohibited
61881 * 0b11..pull disabled
61882 */
61883#define IOMUXD_UART0_RX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_PULL_SHIFT)) & IOMUXD_UART0_RX_PULL_MASK)
61884#define IOMUXD_UART0_RX_UART0_RX_reserved_7_18_MASK (0x7FF80U)
61885#define IOMUXD_UART0_RX_UART0_RX_reserved_7_18_SHIFT (7U)
61886/*! UART0_RX_reserved_7_18 - reserved
61887 */
61888#define IOMUXD_UART0_RX_UART0_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_UART0_RX_reserved_7_18_SHIFT)) & IOMUXD_UART0_RX_UART0_RX_reserved_7_18_MASK)
61889#define IOMUXD_UART0_RX_WAKEUP_CTRL_MASK (0x380000U)
61890#define IOMUXD_UART0_RX_WAKEUP_CTRL_SHIFT (19U)
61891/*! WAKEUP_CTRL - wakeup control
61892 * 0b000..OFF
61893 * 0b001..RESAMPLE
61894 * 0b100..LOW
61895 * 0b111..HIGH
61896 * 0b110..RISE
61897 * 0b101..FALL
61898 */
61899#define IOMUXD_UART0_RX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART0_RX_WAKEUP_CTRL_MASK)
61900#define IOMUXD_UART0_RX_WAKEUP_MASK_MASK (0x400000U)
61901#define IOMUXD_UART0_RX_WAKEUP_MASK_SHIFT (22U)
61902/*! WAKEUP_MASK - wakeup mask
61903 */
61904#define IOMUXD_UART0_RX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART0_RX_WAKEUP_MASK_MASK)
61905#define IOMUXD_UART0_RX_lp_config_MASK (0x1800000U)
61906#define IOMUXD_UART0_RX_lp_config_SHIFT (23U)
61907/*! lp_config - lower power configuration
61908 * 0b01..EARLY_ISO
61909 * 0b10..LATE_ISO
61910 * 0b11..LATCH
61911 * 0b00..PASS
61912 */
61913#define IOMUXD_UART0_RX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_lp_config_SHIFT)) & IOMUXD_UART0_RX_lp_config_MASK)
61914#define IOMUXD_UART0_RX_sw_config_MASK (0x6000000U)
61915#define IOMUXD_UART0_RX_sw_config_SHIFT (25U)
61916/*! sw_config - output and input configuration
61917 * 0b01..OPEN_DRAIN
61918 * 0b10..OPEN_DRAIN_INPUT
61919 * 0b11..INOUT
61920 * 0b00..DEFAULT
61921 */
61922#define IOMUXD_UART0_RX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_sw_config_SHIFT)) & IOMUXD_UART0_RX_sw_config_MASK)
61923#define IOMUXD_UART0_RX_mux_mode_MASK (0x38000000U)
61924#define IOMUXD_UART0_RX_mux_mode_SHIFT (27U)
61925/*! mux_mode - mux_mode
61926 * 0b000..ADMA.UART0.RX
61927 * 0b001..ADMA.MQS.R
61928 * 0b010..ADMA.FLEXCAN0.RX
61929 * 0b011..SCU.UART0.RX
61930 * 0b100..LSIO.GPIO1.IO21
61931 */
61932#define IOMUXD_UART0_RX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_mux_mode_SHIFT)) & IOMUXD_UART0_RX_mux_mode_MASK)
61933#define IOMUXD_UART0_RX_update_pad_ctl_MASK (0x40000000U)
61934#define IOMUXD_UART0_RX_update_pad_ctl_SHIFT (30U)
61935/*! update_pad_ctl - update lock for pad control
61936 */
61937#define IOMUXD_UART0_RX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_update_pad_ctl_SHIFT)) & IOMUXD_UART0_RX_update_pad_ctl_MASK)
61938#define IOMUXD_UART0_RX_update_mux_mode_MASK (0x80000000U)
61939#define IOMUXD_UART0_RX_update_mux_mode_SHIFT (31U)
61940/*! update_mux_mode - update lock for mux control
61941 */
61942#define IOMUXD_UART0_RX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_RX_update_mux_mode_SHIFT)) & IOMUXD_UART0_RX_update_mux_mode_MASK)
61943/*! @} */
61944
61945/*! @name IOMUXD_GROUP_2_1 - na */
61946/*! @{ */
61947#define IOMUXD_IOMUXD_GROUP_2_1_SPI0_CS0_MASK (0x1U)
61948#define IOMUXD_IOMUXD_GROUP_2_1_SPI0_CS0_SHIFT (0U)
61949/*! SPI0_CS0 - wakeup from SPI0_CS0
61950 */
61951#define IOMUXD_IOMUXD_GROUP_2_1_SPI0_CS0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_SPI0_CS0_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_SPI0_CS0_MASK)
61952#define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_1_1_MASK (0x2U)
61953#define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_1_1_SHIFT (1U)
61954/*! iomuxd_group_2_1_reserved_1_1 - reserved
61955 */
61956#define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_1_1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_1_1_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_1_1_MASK)
61957#define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN1_MASK (0x4U)
61958#define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN1_SHIFT (2U)
61959/*! ADC_IN1 - wakeup from ADC_IN1
61960 */
61961#define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ADC_IN1_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ADC_IN1_MASK)
61962#define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN0_MASK (0x8U)
61963#define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN0_SHIFT (3U)
61964/*! ADC_IN0 - wakeup from ADC_IN0
61965 */
61966#define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ADC_IN0_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ADC_IN0_MASK)
61967#define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN3_MASK (0x10U)
61968#define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN3_SHIFT (4U)
61969/*! ADC_IN3 - wakeup from ADC_IN3
61970 */
61971#define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ADC_IN3_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ADC_IN3_MASK)
61972#define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN2_MASK (0x20U)
61973#define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN2_SHIFT (5U)
61974/*! ADC_IN2 - wakeup from ADC_IN2
61975 */
61976#define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ADC_IN2_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ADC_IN2_MASK)
61977#define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN5_MASK (0x40U)
61978#define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN5_SHIFT (6U)
61979/*! ADC_IN5 - wakeup from ADC_IN5
61980 */
61981#define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ADC_IN5_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ADC_IN5_MASK)
61982#define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN4_MASK (0x80U)
61983#define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN4_SHIFT (7U)
61984/*! ADC_IN4 - wakeup from ADC_IN4
61985 */
61986#define IOMUXD_IOMUXD_GROUP_2_1_ADC_IN4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_ADC_IN4_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_ADC_IN4_MASK)
61987#define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_RX_MASK (0x100U)
61988#define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_RX_SHIFT (8U)
61989/*! FLEXCAN0_RX - wakeup from FLEXCAN0_RX
61990 */
61991#define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_RX_MASK)
61992#define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_TX_MASK (0x200U)
61993#define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_TX_SHIFT (9U)
61994/*! FLEXCAN0_TX - wakeup from FLEXCAN0_TX
61995 */
61996#define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_TX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN0_TX_MASK)
61997#define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_RX_MASK (0x400U)
61998#define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_RX_SHIFT (10U)
61999/*! FLEXCAN1_RX - wakeup from FLEXCAN1_RX
62000 */
62001#define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_RX_MASK)
62002#define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_TX_MASK (0x800U)
62003#define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_TX_SHIFT (11U)
62004/*! FLEXCAN1_TX - wakeup from FLEXCAN1_TX
62005 */
62006#define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_TX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN1_TX_MASK)
62007#define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_RX_MASK (0x1000U)
62008#define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_RX_SHIFT (12U)
62009/*! FLEXCAN2_RX - wakeup from FLEXCAN2_RX
62010 */
62011#define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_RX_MASK)
62012#define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_TX_MASK (0x2000U)
62013#define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_TX_SHIFT (13U)
62014/*! FLEXCAN2_TX - wakeup from FLEXCAN2_TX
62015 */
62016#define IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_TX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_FLEXCAN2_TX_MASK)
62017#define IOMUXD_IOMUXD_GROUP_2_1_UART0_RX_MASK (0x4000U)
62018#define IOMUXD_IOMUXD_GROUP_2_1_UART0_RX_SHIFT (14U)
62019/*! UART0_RX - wakeup from UART0_RX
62020 */
62021#define IOMUXD_IOMUXD_GROUP_2_1_UART0_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_UART0_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_UART0_RX_MASK)
62022#define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_15_31_MASK (0xFFFF8000U)
62023#define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_15_31_SHIFT (15U)
62024/*! iomuxd_group_2_1_reserved_15_31 - reserved
62025 */
62026#define IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_1_iomuxd_group_2_1_reserved_15_31_MASK)
62027/*! @} */
62028
62029/*! @name UART0_TX - UART0_TX */
62030/*! @{ */
62031#define IOMUXD_UART0_TX_PDRV_MASK (0x1U)
62032#define IOMUXD_UART0_TX_PDRV_SHIFT (0U)
62033/*! PDRV - Drive
62034 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
62035 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
62036 */
62037#define IOMUXD_UART0_TX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_PDRV_SHIFT)) & IOMUXD_UART0_TX_PDRV_MASK)
62038#define IOMUXD_UART0_TX_UART0_TX_reserved_1_4_MASK (0x1EU)
62039#define IOMUXD_UART0_TX_UART0_TX_reserved_1_4_SHIFT (1U)
62040/*! UART0_TX_reserved_1_4 - reserved
62041 */
62042#define IOMUXD_UART0_TX_UART0_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_UART0_TX_reserved_1_4_SHIFT)) & IOMUXD_UART0_TX_UART0_TX_reserved_1_4_MASK)
62043#define IOMUXD_UART0_TX_PULL_MASK (0x60U)
62044#define IOMUXD_UART0_TX_PULL_SHIFT (5U)
62045/*! PULL - Pull Down Pull Up
62046 * 0b10..pull down
62047 * 0b01..pull up
62048 * 0b00..Prohibited
62049 * 0b11..pull disabled
62050 */
62051#define IOMUXD_UART0_TX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_PULL_SHIFT)) & IOMUXD_UART0_TX_PULL_MASK)
62052#define IOMUXD_UART0_TX_UART0_TX_reserved_7_18_MASK (0x7FF80U)
62053#define IOMUXD_UART0_TX_UART0_TX_reserved_7_18_SHIFT (7U)
62054/*! UART0_TX_reserved_7_18 - reserved
62055 */
62056#define IOMUXD_UART0_TX_UART0_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_UART0_TX_reserved_7_18_SHIFT)) & IOMUXD_UART0_TX_UART0_TX_reserved_7_18_MASK)
62057#define IOMUXD_UART0_TX_WAKEUP_CTRL_MASK (0x380000U)
62058#define IOMUXD_UART0_TX_WAKEUP_CTRL_SHIFT (19U)
62059/*! WAKEUP_CTRL - wakeup control
62060 * 0b000..OFF
62061 * 0b001..RESAMPLE
62062 * 0b100..LOW
62063 * 0b111..HIGH
62064 * 0b110..RISE
62065 * 0b101..FALL
62066 */
62067#define IOMUXD_UART0_TX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART0_TX_WAKEUP_CTRL_MASK)
62068#define IOMUXD_UART0_TX_WAKEUP_MASK_MASK (0x400000U)
62069#define IOMUXD_UART0_TX_WAKEUP_MASK_SHIFT (22U)
62070/*! WAKEUP_MASK - wakeup mask
62071 */
62072#define IOMUXD_UART0_TX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART0_TX_WAKEUP_MASK_MASK)
62073#define IOMUXD_UART0_TX_lp_config_MASK (0x1800000U)
62074#define IOMUXD_UART0_TX_lp_config_SHIFT (23U)
62075/*! lp_config - lower power configuration
62076 * 0b01..EARLY_ISO
62077 * 0b10..LATE_ISO
62078 * 0b11..LATCH
62079 * 0b00..PASS
62080 */
62081#define IOMUXD_UART0_TX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_lp_config_SHIFT)) & IOMUXD_UART0_TX_lp_config_MASK)
62082#define IOMUXD_UART0_TX_sw_config_MASK (0x6000000U)
62083#define IOMUXD_UART0_TX_sw_config_SHIFT (25U)
62084/*! sw_config - output and input configuration
62085 * 0b01..OPEN_DRAIN
62086 * 0b10..OPEN_DRAIN_INPUT
62087 * 0b11..INOUT
62088 * 0b00..DEFAULT
62089 */
62090#define IOMUXD_UART0_TX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_sw_config_SHIFT)) & IOMUXD_UART0_TX_sw_config_MASK)
62091#define IOMUXD_UART0_TX_mux_mode_MASK (0x38000000U)
62092#define IOMUXD_UART0_TX_mux_mode_SHIFT (27U)
62093/*! mux_mode - mux_mode
62094 * 0b000..ADMA.UART0.TX
62095 * 0b001..ADMA.MQS.L
62096 * 0b010..ADMA.FLEXCAN0.TX
62097 * 0b011..SCU.UART0.TX
62098 * 0b100..LSIO.GPIO1.IO22
62099 */
62100#define IOMUXD_UART0_TX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_mux_mode_SHIFT)) & IOMUXD_UART0_TX_mux_mode_MASK)
62101#define IOMUXD_UART0_TX_update_pad_ctl_MASK (0x40000000U)
62102#define IOMUXD_UART0_TX_update_pad_ctl_SHIFT (30U)
62103/*! update_pad_ctl - update lock for pad control
62104 */
62105#define IOMUXD_UART0_TX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_update_pad_ctl_SHIFT)) & IOMUXD_UART0_TX_update_pad_ctl_MASK)
62106#define IOMUXD_UART0_TX_update_mux_mode_MASK (0x80000000U)
62107#define IOMUXD_UART0_TX_update_mux_mode_SHIFT (31U)
62108/*! update_mux_mode - update lock for mux control
62109 */
62110#define IOMUXD_UART0_TX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART0_TX_update_mux_mode_SHIFT)) & IOMUXD_UART0_TX_update_mux_mode_MASK)
62111/*! @} */
62112
62113/*! @name UART2_TX - UART2_TX */
62114/*! @{ */
62115#define IOMUXD_UART2_TX_PDRV_MASK (0x1U)
62116#define IOMUXD_UART2_TX_PDRV_SHIFT (0U)
62117/*! PDRV - Drive
62118 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
62119 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
62120 */
62121#define IOMUXD_UART2_TX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_PDRV_SHIFT)) & IOMUXD_UART2_TX_PDRV_MASK)
62122#define IOMUXD_UART2_TX_UART2_TX_reserved_1_4_MASK (0x1EU)
62123#define IOMUXD_UART2_TX_UART2_TX_reserved_1_4_SHIFT (1U)
62124/*! UART2_TX_reserved_1_4 - reserved
62125 */
62126#define IOMUXD_UART2_TX_UART2_TX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_UART2_TX_reserved_1_4_SHIFT)) & IOMUXD_UART2_TX_UART2_TX_reserved_1_4_MASK)
62127#define IOMUXD_UART2_TX_PULL_MASK (0x60U)
62128#define IOMUXD_UART2_TX_PULL_SHIFT (5U)
62129/*! PULL - Pull Down Pull Up
62130 * 0b10..pull down
62131 * 0b01..pull up
62132 * 0b00..Prohibited
62133 * 0b11..pull disabled
62134 */
62135#define IOMUXD_UART2_TX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_PULL_SHIFT)) & IOMUXD_UART2_TX_PULL_MASK)
62136#define IOMUXD_UART2_TX_UART2_TX_reserved_7_18_MASK (0x7FF80U)
62137#define IOMUXD_UART2_TX_UART2_TX_reserved_7_18_SHIFT (7U)
62138/*! UART2_TX_reserved_7_18 - reserved
62139 */
62140#define IOMUXD_UART2_TX_UART2_TX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_UART2_TX_reserved_7_18_SHIFT)) & IOMUXD_UART2_TX_UART2_TX_reserved_7_18_MASK)
62141#define IOMUXD_UART2_TX_WAKEUP_CTRL_MASK (0x380000U)
62142#define IOMUXD_UART2_TX_WAKEUP_CTRL_SHIFT (19U)
62143/*! WAKEUP_CTRL - wakeup control
62144 * 0b000..OFF
62145 * 0b001..RESAMPLE
62146 * 0b100..LOW
62147 * 0b111..HIGH
62148 * 0b110..RISE
62149 * 0b101..FALL
62150 */
62151#define IOMUXD_UART2_TX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART2_TX_WAKEUP_CTRL_MASK)
62152#define IOMUXD_UART2_TX_WAKEUP_MASK_MASK (0x400000U)
62153#define IOMUXD_UART2_TX_WAKEUP_MASK_SHIFT (22U)
62154/*! WAKEUP_MASK - wakeup mask
62155 */
62156#define IOMUXD_UART2_TX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART2_TX_WAKEUP_MASK_MASK)
62157#define IOMUXD_UART2_TX_lp_config_MASK (0x1800000U)
62158#define IOMUXD_UART2_TX_lp_config_SHIFT (23U)
62159/*! lp_config - lower power configuration
62160 * 0b01..EARLY_ISO
62161 * 0b10..LATE_ISO
62162 * 0b11..LATCH
62163 * 0b00..PASS
62164 */
62165#define IOMUXD_UART2_TX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_lp_config_SHIFT)) & IOMUXD_UART2_TX_lp_config_MASK)
62166#define IOMUXD_UART2_TX_sw_config_MASK (0x6000000U)
62167#define IOMUXD_UART2_TX_sw_config_SHIFT (25U)
62168/*! sw_config - output and input configuration
62169 * 0b01..OPEN_DRAIN
62170 * 0b10..OPEN_DRAIN_INPUT
62171 * 0b11..INOUT
62172 * 0b00..DEFAULT
62173 */
62174#define IOMUXD_UART2_TX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_sw_config_SHIFT)) & IOMUXD_UART2_TX_sw_config_MASK)
62175#define IOMUXD_UART2_TX_mux_mode_MASK (0x38000000U)
62176#define IOMUXD_UART2_TX_mux_mode_SHIFT (27U)
62177/*! mux_mode - mux_mode
62178 * 0b000..ADMA.UART2.TX
62179 * 0b001..ADMA.FTM.CH1
62180 * 0b010..ADMA.FLEXCAN1.TX
62181 * 0b100..LSIO.GPIO1.IO23
62182 */
62183#define IOMUXD_UART2_TX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_mux_mode_SHIFT)) & IOMUXD_UART2_TX_mux_mode_MASK)
62184#define IOMUXD_UART2_TX_update_pad_ctl_MASK (0x40000000U)
62185#define IOMUXD_UART2_TX_update_pad_ctl_SHIFT (30U)
62186/*! update_pad_ctl - update lock for pad control
62187 */
62188#define IOMUXD_UART2_TX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_update_pad_ctl_SHIFT)) & IOMUXD_UART2_TX_update_pad_ctl_MASK)
62189#define IOMUXD_UART2_TX_update_mux_mode_MASK (0x80000000U)
62190#define IOMUXD_UART2_TX_update_mux_mode_SHIFT (31U)
62191/*! update_mux_mode - update lock for mux control
62192 */
62193#define IOMUXD_UART2_TX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_TX_update_mux_mode_SHIFT)) & IOMUXD_UART2_TX_update_mux_mode_MASK)
62194/*! @} */
62195
62196/*! @name UART2_RX - UART2_RX */
62197/*! @{ */
62198#define IOMUXD_UART2_RX_PDRV_MASK (0x1U)
62199#define IOMUXD_UART2_RX_PDRV_SHIFT (0U)
62200/*! PDRV - Drive
62201 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
62202 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
62203 */
62204#define IOMUXD_UART2_RX_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_PDRV_SHIFT)) & IOMUXD_UART2_RX_PDRV_MASK)
62205#define IOMUXD_UART2_RX_UART2_RX_reserved_1_4_MASK (0x1EU)
62206#define IOMUXD_UART2_RX_UART2_RX_reserved_1_4_SHIFT (1U)
62207/*! UART2_RX_reserved_1_4 - reserved
62208 */
62209#define IOMUXD_UART2_RX_UART2_RX_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_UART2_RX_reserved_1_4_SHIFT)) & IOMUXD_UART2_RX_UART2_RX_reserved_1_4_MASK)
62210#define IOMUXD_UART2_RX_PULL_MASK (0x60U)
62211#define IOMUXD_UART2_RX_PULL_SHIFT (5U)
62212/*! PULL - Pull Down Pull Up
62213 * 0b10..pull down
62214 * 0b01..pull up
62215 * 0b00..Prohibited
62216 * 0b11..pull disabled
62217 */
62218#define IOMUXD_UART2_RX_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_PULL_SHIFT)) & IOMUXD_UART2_RX_PULL_MASK)
62219#define IOMUXD_UART2_RX_UART2_RX_reserved_7_18_MASK (0x7FF80U)
62220#define IOMUXD_UART2_RX_UART2_RX_reserved_7_18_SHIFT (7U)
62221/*! UART2_RX_reserved_7_18 - reserved
62222 */
62223#define IOMUXD_UART2_RX_UART2_RX_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_UART2_RX_reserved_7_18_SHIFT)) & IOMUXD_UART2_RX_UART2_RX_reserved_7_18_MASK)
62224#define IOMUXD_UART2_RX_WAKEUP_CTRL_MASK (0x380000U)
62225#define IOMUXD_UART2_RX_WAKEUP_CTRL_SHIFT (19U)
62226/*! WAKEUP_CTRL - wakeup control
62227 * 0b000..OFF
62228 * 0b001..RESAMPLE
62229 * 0b100..LOW
62230 * 0b111..HIGH
62231 * 0b110..RISE
62232 * 0b101..FALL
62233 */
62234#define IOMUXD_UART2_RX_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_WAKEUP_CTRL_SHIFT)) & IOMUXD_UART2_RX_WAKEUP_CTRL_MASK)
62235#define IOMUXD_UART2_RX_WAKEUP_MASK_MASK (0x400000U)
62236#define IOMUXD_UART2_RX_WAKEUP_MASK_SHIFT (22U)
62237/*! WAKEUP_MASK - wakeup mask
62238 */
62239#define IOMUXD_UART2_RX_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_WAKEUP_MASK_SHIFT)) & IOMUXD_UART2_RX_WAKEUP_MASK_MASK)
62240#define IOMUXD_UART2_RX_lp_config_MASK (0x1800000U)
62241#define IOMUXD_UART2_RX_lp_config_SHIFT (23U)
62242/*! lp_config - lower power configuration
62243 * 0b01..EARLY_ISO
62244 * 0b10..LATE_ISO
62245 * 0b11..LATCH
62246 * 0b00..PASS
62247 */
62248#define IOMUXD_UART2_RX_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_lp_config_SHIFT)) & IOMUXD_UART2_RX_lp_config_MASK)
62249#define IOMUXD_UART2_RX_sw_config_MASK (0x6000000U)
62250#define IOMUXD_UART2_RX_sw_config_SHIFT (25U)
62251/*! sw_config - output and input configuration
62252 * 0b01..OPEN_DRAIN
62253 * 0b10..OPEN_DRAIN_INPUT
62254 * 0b11..INOUT
62255 * 0b00..DEFAULT
62256 */
62257#define IOMUXD_UART2_RX_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_sw_config_SHIFT)) & IOMUXD_UART2_RX_sw_config_MASK)
62258#define IOMUXD_UART2_RX_mux_mode_MASK (0x38000000U)
62259#define IOMUXD_UART2_RX_mux_mode_SHIFT (27U)
62260/*! mux_mode - mux_mode
62261 * 0b000..ADMA.UART2.RX
62262 * 0b001..ADMA.FTM.CH0
62263 * 0b010..ADMA.FLEXCAN1.RX
62264 * 0b100..LSIO.GPIO1.IO24
62265 */
62266#define IOMUXD_UART2_RX_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_mux_mode_SHIFT)) & IOMUXD_UART2_RX_mux_mode_MASK)
62267#define IOMUXD_UART2_RX_update_pad_ctl_MASK (0x40000000U)
62268#define IOMUXD_UART2_RX_update_pad_ctl_SHIFT (30U)
62269/*! update_pad_ctl - update lock for pad control
62270 */
62271#define IOMUXD_UART2_RX_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_update_pad_ctl_SHIFT)) & IOMUXD_UART2_RX_update_pad_ctl_MASK)
62272#define IOMUXD_UART2_RX_update_mux_mode_MASK (0x80000000U)
62273#define IOMUXD_UART2_RX_update_mux_mode_SHIFT (31U)
62274/*! update_mux_mode - update lock for mux control
62275 */
62276#define IOMUXD_UART2_RX_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_UART2_RX_update_mux_mode_SHIFT)) & IOMUXD_UART2_RX_update_mux_mode_MASK)
62277/*! @} */
62278
62279/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH */
62280/*! @{ */
62281#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMP_MASK (0x7U)
62282#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMP_SHIFT (0U)
62283/*! COMP - COMP
62284 * 0b010..Fixed code mode
62285 * 0b100..High impedance mode
62286 * 0b110..Read mode
62287 * 0b000..Normal Mode
62288 * 0b001..Freeze Mode
62289 */
62290#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMP_MASK)
62291#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_FASTFRZ_EN_MASK (0x8U)
62292#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_FASTFRZ_EN_SHIFT (3U)
62293/*! FASTFRZ_EN - FASTFRZ_EN
62294 * 0b1..FASTFRZ signal is driven by output of subsystem
62295 * 0b0..FASTFRZ signal is gated to 0
62296 */
62297#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_FASTFRZ_EN_MASK)
62298#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4_MASK (0x10U)
62299#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4_SHIFT (4U)
62300/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4 - reserved
62301 */
62302#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_4_4_MASK)
62303#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCP_MASK (0x1E0U)
62304#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCP_SHIFT (5U)
62305/*! RASRCP - RASRCP
62306 * 0b0101..Reset Value
62307 */
62308#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCP_MASK)
62309#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCN_MASK (0x1E00U)
62310#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCN_SHIFT (9U)
62311/*! RASRCN - RASRCN
62312 * 0b1010..Reset Value
62313 */
62314#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_RASRCN_MASK)
62315#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SELECT_NASRC_MASK (0x2000U)
62316#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SELECT_NASRC_SHIFT (13U)
62317/*! SELECT_NASRC - SELECT_NASRC
62318 * 0b1..NASRCN value
62319 * 0b0..NASRCP value
62320 */
62321#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SELECT_NASRC_MASK)
62322#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMPOK_MASK (0x4000U)
62323#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMPOK_SHIFT (14U)
62324/*! COMPOK - COMPOK
62325 * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
62326 * 0b1..compensation cell in Normal mode and tracking PVT
62327 */
62328#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_COMPOK_MASK)
62329#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_READ_NASRC_MASK (0x78000U)
62330#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_READ_NASRC_SHIFT (15U)
62331/*! READ_NASRC - READ_NASRC
62332 * 0b0000..READ Only
62333 */
62334#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_READ_NASRC_MASK)
62335#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22_MASK (0x780000U)
62336#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22_SHIFT (19U)
62337/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22 - reserved
62338 */
62339#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_19_22_MASK)
62340#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SLEEP_MASK (0x1800000U)
62341#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SLEEP_SHIFT (23U)
62342/*! SLEEP - SLEEP
62343 * 0b11..Force into sleep mode
62344 * 0b00..NO
62345 * 0b01..EARLY
62346 * 0b10..LATE
62347 */
62348#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_SLEEP_MASK)
62349#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29_MASK (0x3E000000U)
62350#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29_SHIFT (25U)
62351/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29 - reserved
62352 */
62353#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_reserved_25_29_MASK)
62354#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_pad_ctl_MASK (0x40000000U)
62355#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_pad_ctl_SHIFT (30U)
62356/*! update_pad_ctl - update lock for pad control
62357 */
62358#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_pad_ctl_MASK)
62359#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_mux_mode_MASK (0x80000000U)
62360#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_mux_mode_SHIFT (31U)
62361/*! update_mux_mode - update lock for mux control
62362 */
62363#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIOLH_update_mux_mode_MASK)
62364/*! @} */
62365
62366/*! @name MIPI_DSI0_I2C0_SCL - MIPI_DSI0_I2C0_SCL */
62367/*! @{ */
62368#define IOMUXD_MIPI_DSI0_I2C0_SCL_PDRV_MASK (0x1U)
62369#define IOMUXD_MIPI_DSI0_I2C0_SCL_PDRV_SHIFT (0U)
62370/*! PDRV - Drive
62371 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
62372 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
62373 */
62374#define IOMUXD_MIPI_DSI0_I2C0_SCL_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_PDRV_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_PDRV_MASK)
62375#define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_1_4_MASK (0x1EU)
62376#define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_1_4_SHIFT (1U)
62377/*! MIPI_DSI0_I2C0_SCL_reserved_1_4 - reserved
62378 */
62379#define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_1_4_MASK)
62380#define IOMUXD_MIPI_DSI0_I2C0_SCL_PULL_MASK (0x60U)
62381#define IOMUXD_MIPI_DSI0_I2C0_SCL_PULL_SHIFT (5U)
62382/*! PULL - Pull Down Pull Up
62383 * 0b10..pull down
62384 * 0b01..pull up
62385 * 0b00..Prohibited
62386 * 0b11..pull disabled
62387 */
62388#define IOMUXD_MIPI_DSI0_I2C0_SCL_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_PULL_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_PULL_MASK)
62389#define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_7_18_MASK (0x7FF80U)
62390#define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_7_18_SHIFT (7U)
62391/*! MIPI_DSI0_I2C0_SCL_reserved_7_18 - reserved
62392 */
62393#define IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL_reserved_7_18_MASK)
62394#define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_CTRL_MASK (0x380000U)
62395#define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_CTRL_SHIFT (19U)
62396/*! WAKEUP_CTRL - wakeup control
62397 * 0b000..OFF
62398 * 0b001..RESAMPLE
62399 * 0b100..LOW
62400 * 0b111..HIGH
62401 * 0b110..RISE
62402 * 0b101..FALL
62403 */
62404#define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_CTRL_MASK)
62405#define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_MASK_MASK (0x400000U)
62406#define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_MASK_SHIFT (22U)
62407/*! WAKEUP_MASK - wakeup mask
62408 */
62409#define IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_WAKEUP_MASK_MASK)
62410#define IOMUXD_MIPI_DSI0_I2C0_SCL_lp_config_MASK (0x1800000U)
62411#define IOMUXD_MIPI_DSI0_I2C0_SCL_lp_config_SHIFT (23U)
62412/*! lp_config - lower power configuration
62413 * 0b01..EARLY_ISO
62414 * 0b10..LATE_ISO
62415 * 0b11..LATCH
62416 * 0b00..PASS
62417 */
62418#define IOMUXD_MIPI_DSI0_I2C0_SCL_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_lp_config_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_lp_config_MASK)
62419#define IOMUXD_MIPI_DSI0_I2C0_SCL_sw_config_MASK (0x6000000U)
62420#define IOMUXD_MIPI_DSI0_I2C0_SCL_sw_config_SHIFT (25U)
62421/*! sw_config - output and input configuration
62422 * 0b01..OPEN_DRAIN
62423 * 0b10..OPEN_DRAIN_INPUT
62424 * 0b11..INOUT
62425 * 0b00..DEFAULT
62426 */
62427#define IOMUXD_MIPI_DSI0_I2C0_SCL_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_sw_config_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_sw_config_MASK)
62428#define IOMUXD_MIPI_DSI0_I2C0_SCL_mux_mode_MASK (0x38000000U)
62429#define IOMUXD_MIPI_DSI0_I2C0_SCL_mux_mode_SHIFT (27U)
62430/*! mux_mode - mux_mode
62431 * 0b000..MIPI_DSI0.I2C0.SCL
62432 * 0b001..MIPI_DSI1.GPIO0.IO02
62433 * 0b100..LSIO.GPIO1.IO25
62434 */
62435#define IOMUXD_MIPI_DSI0_I2C0_SCL_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_mux_mode_MASK)
62436#define IOMUXD_MIPI_DSI0_I2C0_SCL_update_pad_ctl_MASK (0x40000000U)
62437#define IOMUXD_MIPI_DSI0_I2C0_SCL_update_pad_ctl_SHIFT (30U)
62438/*! update_pad_ctl - update lock for pad control
62439 */
62440#define IOMUXD_MIPI_DSI0_I2C0_SCL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_update_pad_ctl_MASK)
62441#define IOMUXD_MIPI_DSI0_I2C0_SCL_update_mux_mode_MASK (0x80000000U)
62442#define IOMUXD_MIPI_DSI0_I2C0_SCL_update_mux_mode_SHIFT (31U)
62443/*! update_mux_mode - update lock for mux control
62444 */
62445#define IOMUXD_MIPI_DSI0_I2C0_SCL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SCL_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SCL_update_mux_mode_MASK)
62446/*! @} */
62447
62448/*! @name MIPI_DSI0_I2C0_SDA - MIPI_DSI0_I2C0_SDA */
62449/*! @{ */
62450#define IOMUXD_MIPI_DSI0_I2C0_SDA_PDRV_MASK (0x1U)
62451#define IOMUXD_MIPI_DSI0_I2C0_SDA_PDRV_SHIFT (0U)
62452/*! PDRV - Drive
62453 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
62454 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
62455 */
62456#define IOMUXD_MIPI_DSI0_I2C0_SDA_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_PDRV_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_PDRV_MASK)
62457#define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_1_4_MASK (0x1EU)
62458#define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_1_4_SHIFT (1U)
62459/*! MIPI_DSI0_I2C0_SDA_reserved_1_4 - reserved
62460 */
62461#define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_1_4_MASK)
62462#define IOMUXD_MIPI_DSI0_I2C0_SDA_PULL_MASK (0x60U)
62463#define IOMUXD_MIPI_DSI0_I2C0_SDA_PULL_SHIFT (5U)
62464/*! PULL - Pull Down Pull Up
62465 * 0b10..pull down
62466 * 0b01..pull up
62467 * 0b00..Prohibited
62468 * 0b11..pull disabled
62469 */
62470#define IOMUXD_MIPI_DSI0_I2C0_SDA_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_PULL_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_PULL_MASK)
62471#define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_7_18_MASK (0x7FF80U)
62472#define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_7_18_SHIFT (7U)
62473/*! MIPI_DSI0_I2C0_SDA_reserved_7_18 - reserved
62474 */
62475#define IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA_reserved_7_18_MASK)
62476#define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_CTRL_MASK (0x380000U)
62477#define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_CTRL_SHIFT (19U)
62478/*! WAKEUP_CTRL - wakeup control
62479 * 0b000..OFF
62480 * 0b001..RESAMPLE
62481 * 0b100..LOW
62482 * 0b111..HIGH
62483 * 0b110..RISE
62484 * 0b101..FALL
62485 */
62486#define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_CTRL_MASK)
62487#define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_MASK_MASK (0x400000U)
62488#define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_MASK_SHIFT (22U)
62489/*! WAKEUP_MASK - wakeup mask
62490 */
62491#define IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_WAKEUP_MASK_MASK)
62492#define IOMUXD_MIPI_DSI0_I2C0_SDA_lp_config_MASK (0x1800000U)
62493#define IOMUXD_MIPI_DSI0_I2C0_SDA_lp_config_SHIFT (23U)
62494/*! lp_config - lower power configuration
62495 * 0b01..EARLY_ISO
62496 * 0b10..LATE_ISO
62497 * 0b11..LATCH
62498 * 0b00..PASS
62499 */
62500#define IOMUXD_MIPI_DSI0_I2C0_SDA_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_lp_config_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_lp_config_MASK)
62501#define IOMUXD_MIPI_DSI0_I2C0_SDA_sw_config_MASK (0x6000000U)
62502#define IOMUXD_MIPI_DSI0_I2C0_SDA_sw_config_SHIFT (25U)
62503/*! sw_config - output and input configuration
62504 * 0b01..OPEN_DRAIN
62505 * 0b10..OPEN_DRAIN_INPUT
62506 * 0b11..INOUT
62507 * 0b00..DEFAULT
62508 */
62509#define IOMUXD_MIPI_DSI0_I2C0_SDA_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_sw_config_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_sw_config_MASK)
62510#define IOMUXD_MIPI_DSI0_I2C0_SDA_mux_mode_MASK (0x38000000U)
62511#define IOMUXD_MIPI_DSI0_I2C0_SDA_mux_mode_SHIFT (27U)
62512/*! mux_mode - mux_mode
62513 * 0b000..MIPI_DSI0.I2C0.SDA
62514 * 0b001..MIPI_DSI1.GPIO0.IO03
62515 * 0b100..LSIO.GPIO1.IO26
62516 */
62517#define IOMUXD_MIPI_DSI0_I2C0_SDA_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_mux_mode_MASK)
62518#define IOMUXD_MIPI_DSI0_I2C0_SDA_update_pad_ctl_MASK (0x40000000U)
62519#define IOMUXD_MIPI_DSI0_I2C0_SDA_update_pad_ctl_SHIFT (30U)
62520/*! update_pad_ctl - update lock for pad control
62521 */
62522#define IOMUXD_MIPI_DSI0_I2C0_SDA_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_update_pad_ctl_MASK)
62523#define IOMUXD_MIPI_DSI0_I2C0_SDA_update_mux_mode_MASK (0x80000000U)
62524#define IOMUXD_MIPI_DSI0_I2C0_SDA_update_mux_mode_SHIFT (31U)
62525/*! update_mux_mode - update lock for mux control
62526 */
62527#define IOMUXD_MIPI_DSI0_I2C0_SDA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_I2C0_SDA_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_I2C0_SDA_update_mux_mode_MASK)
62528/*! @} */
62529
62530/*! @name MIPI_DSI0_GPIO0_00 - MIPI_DSI0_GPIO0_00 */
62531/*! @{ */
62532#define IOMUXD_MIPI_DSI0_GPIO0_00_PDRV_MASK (0x1U)
62533#define IOMUXD_MIPI_DSI0_GPIO0_00_PDRV_SHIFT (0U)
62534/*! PDRV - Drive
62535 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
62536 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
62537 */
62538#define IOMUXD_MIPI_DSI0_GPIO0_00_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_PDRV_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_PDRV_MASK)
62539#define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_1_4_MASK (0x1EU)
62540#define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_1_4_SHIFT (1U)
62541/*! MIPI_DSI0_GPIO0_00_reserved_1_4 - reserved
62542 */
62543#define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_1_4_MASK)
62544#define IOMUXD_MIPI_DSI0_GPIO0_00_PULL_MASK (0x60U)
62545#define IOMUXD_MIPI_DSI0_GPIO0_00_PULL_SHIFT (5U)
62546/*! PULL - Pull Down Pull Up
62547 * 0b10..pull down
62548 * 0b01..pull up
62549 * 0b00..Prohibited
62550 * 0b11..pull disabled
62551 */
62552#define IOMUXD_MIPI_DSI0_GPIO0_00_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_PULL_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_PULL_MASK)
62553#define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_7_18_MASK (0x7FF80U)
62554#define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_7_18_SHIFT (7U)
62555/*! MIPI_DSI0_GPIO0_00_reserved_7_18 - reserved
62556 */
62557#define IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_MIPI_DSI0_GPIO0_00_reserved_7_18_MASK)
62558#define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_CTRL_MASK (0x380000U)
62559#define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_CTRL_SHIFT (19U)
62560/*! WAKEUP_CTRL - wakeup control
62561 * 0b000..OFF
62562 * 0b001..RESAMPLE
62563 * 0b100..LOW
62564 * 0b111..HIGH
62565 * 0b110..RISE
62566 * 0b101..FALL
62567 */
62568#define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_CTRL_MASK)
62569#define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_MASK_MASK (0x400000U)
62570#define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_MASK_SHIFT (22U)
62571/*! WAKEUP_MASK - wakeup mask
62572 */
62573#define IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_WAKEUP_MASK_MASK)
62574#define IOMUXD_MIPI_DSI0_GPIO0_00_lp_config_MASK (0x1800000U)
62575#define IOMUXD_MIPI_DSI0_GPIO0_00_lp_config_SHIFT (23U)
62576/*! lp_config - lower power configuration
62577 * 0b01..EARLY_ISO
62578 * 0b10..LATE_ISO
62579 * 0b11..LATCH
62580 * 0b00..PASS
62581 */
62582#define IOMUXD_MIPI_DSI0_GPIO0_00_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_lp_config_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_lp_config_MASK)
62583#define IOMUXD_MIPI_DSI0_GPIO0_00_sw_config_MASK (0x6000000U)
62584#define IOMUXD_MIPI_DSI0_GPIO0_00_sw_config_SHIFT (25U)
62585/*! sw_config - output and input configuration
62586 * 0b01..OPEN_DRAIN
62587 * 0b10..OPEN_DRAIN_INPUT
62588 * 0b11..INOUT
62589 * 0b00..DEFAULT
62590 */
62591#define IOMUXD_MIPI_DSI0_GPIO0_00_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_sw_config_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_sw_config_MASK)
62592#define IOMUXD_MIPI_DSI0_GPIO0_00_mux_mode_MASK (0x38000000U)
62593#define IOMUXD_MIPI_DSI0_GPIO0_00_mux_mode_SHIFT (27U)
62594/*! mux_mode - mux_mode
62595 * 0b000..MIPI_DSI0.GPIO0.IO00
62596 * 0b001..ADMA.I2C1.SCL
62597 * 0b010..MIPI_DSI0.PWM0.OUT
62598 * 0b100..LSIO.GPIO1.IO27
62599 */
62600#define IOMUXD_MIPI_DSI0_GPIO0_00_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_mux_mode_MASK)
62601#define IOMUXD_MIPI_DSI0_GPIO0_00_update_pad_ctl_MASK (0x40000000U)
62602#define IOMUXD_MIPI_DSI0_GPIO0_00_update_pad_ctl_SHIFT (30U)
62603/*! update_pad_ctl - update lock for pad control
62604 */
62605#define IOMUXD_MIPI_DSI0_GPIO0_00_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_update_pad_ctl_MASK)
62606#define IOMUXD_MIPI_DSI0_GPIO0_00_update_mux_mode_MASK (0x80000000U)
62607#define IOMUXD_MIPI_DSI0_GPIO0_00_update_mux_mode_SHIFT (31U)
62608/*! update_mux_mode - update lock for mux control
62609 */
62610#define IOMUXD_MIPI_DSI0_GPIO0_00_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_00_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_00_update_mux_mode_MASK)
62611/*! @} */
62612
62613/*! @name MIPI_DSI0_GPIO0_01 - MIPI_DSI0_GPIO0_01 */
62614/*! @{ */
62615#define IOMUXD_MIPI_DSI0_GPIO0_01_PDRV_MASK (0x1U)
62616#define IOMUXD_MIPI_DSI0_GPIO0_01_PDRV_SHIFT (0U)
62617/*! PDRV - Drive
62618 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
62619 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
62620 */
62621#define IOMUXD_MIPI_DSI0_GPIO0_01_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_PDRV_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_PDRV_MASK)
62622#define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_1_4_MASK (0x1EU)
62623#define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_1_4_SHIFT (1U)
62624/*! MIPI_DSI0_GPIO0_01_reserved_1_4 - reserved
62625 */
62626#define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_1_4_MASK)
62627#define IOMUXD_MIPI_DSI0_GPIO0_01_PULL_MASK (0x60U)
62628#define IOMUXD_MIPI_DSI0_GPIO0_01_PULL_SHIFT (5U)
62629/*! PULL - Pull Down Pull Up
62630 * 0b10..pull down
62631 * 0b01..pull up
62632 * 0b00..Prohibited
62633 * 0b11..pull disabled
62634 */
62635#define IOMUXD_MIPI_DSI0_GPIO0_01_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_PULL_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_PULL_MASK)
62636#define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_7_18_MASK (0x7FF80U)
62637#define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_7_18_SHIFT (7U)
62638/*! MIPI_DSI0_GPIO0_01_reserved_7_18 - reserved
62639 */
62640#define IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_MIPI_DSI0_GPIO0_01_reserved_7_18_MASK)
62641#define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_CTRL_MASK (0x380000U)
62642#define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_CTRL_SHIFT (19U)
62643/*! WAKEUP_CTRL - wakeup control
62644 * 0b000..OFF
62645 * 0b001..RESAMPLE
62646 * 0b100..LOW
62647 * 0b111..HIGH
62648 * 0b110..RISE
62649 * 0b101..FALL
62650 */
62651#define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_CTRL_MASK)
62652#define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_MASK_MASK (0x400000U)
62653#define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_MASK_SHIFT (22U)
62654/*! WAKEUP_MASK - wakeup mask
62655 */
62656#define IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_WAKEUP_MASK_MASK)
62657#define IOMUXD_MIPI_DSI0_GPIO0_01_lp_config_MASK (0x1800000U)
62658#define IOMUXD_MIPI_DSI0_GPIO0_01_lp_config_SHIFT (23U)
62659/*! lp_config - lower power configuration
62660 * 0b01..EARLY_ISO
62661 * 0b10..LATE_ISO
62662 * 0b11..LATCH
62663 * 0b00..PASS
62664 */
62665#define IOMUXD_MIPI_DSI0_GPIO0_01_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_lp_config_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_lp_config_MASK)
62666#define IOMUXD_MIPI_DSI0_GPIO0_01_sw_config_MASK (0x6000000U)
62667#define IOMUXD_MIPI_DSI0_GPIO0_01_sw_config_SHIFT (25U)
62668/*! sw_config - output and input configuration
62669 * 0b01..OPEN_DRAIN
62670 * 0b10..OPEN_DRAIN_INPUT
62671 * 0b11..INOUT
62672 * 0b00..DEFAULT
62673 */
62674#define IOMUXD_MIPI_DSI0_GPIO0_01_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_sw_config_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_sw_config_MASK)
62675#define IOMUXD_MIPI_DSI0_GPIO0_01_mux_mode_MASK (0x38000000U)
62676#define IOMUXD_MIPI_DSI0_GPIO0_01_mux_mode_SHIFT (27U)
62677/*! mux_mode - mux_mode
62678 * 0b000..MIPI_DSI0.GPIO0.IO01
62679 * 0b001..ADMA.I2C1.SDA
62680 * 0b100..LSIO.GPIO1.IO28
62681 */
62682#define IOMUXD_MIPI_DSI0_GPIO0_01_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_mux_mode_MASK)
62683#define IOMUXD_MIPI_DSI0_GPIO0_01_update_pad_ctl_MASK (0x40000000U)
62684#define IOMUXD_MIPI_DSI0_GPIO0_01_update_pad_ctl_SHIFT (30U)
62685/*! update_pad_ctl - update lock for pad control
62686 */
62687#define IOMUXD_MIPI_DSI0_GPIO0_01_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_update_pad_ctl_MASK)
62688#define IOMUXD_MIPI_DSI0_GPIO0_01_update_mux_mode_MASK (0x80000000U)
62689#define IOMUXD_MIPI_DSI0_GPIO0_01_update_mux_mode_SHIFT (31U)
62690/*! update_mux_mode - update lock for mux control
62691 */
62692#define IOMUXD_MIPI_DSI0_GPIO0_01_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI0_GPIO0_01_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI0_GPIO0_01_update_mux_mode_MASK)
62693/*! @} */
62694
62695/*! @name MIPI_DSI1_I2C0_SCL - MIPI_DSI1_I2C0_SCL */
62696/*! @{ */
62697#define IOMUXD_MIPI_DSI1_I2C0_SCL_PDRV_MASK (0x1U)
62698#define IOMUXD_MIPI_DSI1_I2C0_SCL_PDRV_SHIFT (0U)
62699/*! PDRV - Drive
62700 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
62701 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
62702 */
62703#define IOMUXD_MIPI_DSI1_I2C0_SCL_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_PDRV_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_PDRV_MASK)
62704#define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_1_4_MASK (0x1EU)
62705#define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_1_4_SHIFT (1U)
62706/*! MIPI_DSI1_I2C0_SCL_reserved_1_4 - reserved
62707 */
62708#define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_1_4_MASK)
62709#define IOMUXD_MIPI_DSI1_I2C0_SCL_PULL_MASK (0x60U)
62710#define IOMUXD_MIPI_DSI1_I2C0_SCL_PULL_SHIFT (5U)
62711/*! PULL - Pull Down Pull Up
62712 * 0b10..pull down
62713 * 0b01..pull up
62714 * 0b00..Prohibited
62715 * 0b11..pull disabled
62716 */
62717#define IOMUXD_MIPI_DSI1_I2C0_SCL_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_PULL_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_PULL_MASK)
62718#define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_7_18_MASK (0x7FF80U)
62719#define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_7_18_SHIFT (7U)
62720/*! MIPI_DSI1_I2C0_SCL_reserved_7_18 - reserved
62721 */
62722#define IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL_reserved_7_18_MASK)
62723#define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_CTRL_MASK (0x380000U)
62724#define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_CTRL_SHIFT (19U)
62725/*! WAKEUP_CTRL - wakeup control
62726 * 0b000..OFF
62727 * 0b001..RESAMPLE
62728 * 0b100..LOW
62729 * 0b111..HIGH
62730 * 0b110..RISE
62731 * 0b101..FALL
62732 */
62733#define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_CTRL_MASK)
62734#define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_MASK_MASK (0x400000U)
62735#define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_MASK_SHIFT (22U)
62736/*! WAKEUP_MASK - wakeup mask
62737 */
62738#define IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_WAKEUP_MASK_MASK)
62739#define IOMUXD_MIPI_DSI1_I2C0_SCL_lp_config_MASK (0x1800000U)
62740#define IOMUXD_MIPI_DSI1_I2C0_SCL_lp_config_SHIFT (23U)
62741/*! lp_config - lower power configuration
62742 * 0b01..EARLY_ISO
62743 * 0b10..LATE_ISO
62744 * 0b11..LATCH
62745 * 0b00..PASS
62746 */
62747#define IOMUXD_MIPI_DSI1_I2C0_SCL_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_lp_config_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_lp_config_MASK)
62748#define IOMUXD_MIPI_DSI1_I2C0_SCL_sw_config_MASK (0x6000000U)
62749#define IOMUXD_MIPI_DSI1_I2C0_SCL_sw_config_SHIFT (25U)
62750/*! sw_config - output and input configuration
62751 * 0b01..OPEN_DRAIN
62752 * 0b10..OPEN_DRAIN_INPUT
62753 * 0b11..INOUT
62754 * 0b00..DEFAULT
62755 */
62756#define IOMUXD_MIPI_DSI1_I2C0_SCL_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_sw_config_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_sw_config_MASK)
62757#define IOMUXD_MIPI_DSI1_I2C0_SCL_mux_mode_MASK (0x38000000U)
62758#define IOMUXD_MIPI_DSI1_I2C0_SCL_mux_mode_SHIFT (27U)
62759/*! mux_mode - mux_mode
62760 * 0b000..MIPI_DSI1.I2C0.SCL
62761 * 0b001..MIPI_DSI0.GPIO0.IO02
62762 * 0b100..LSIO.GPIO1.IO29
62763 */
62764#define IOMUXD_MIPI_DSI1_I2C0_SCL_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_mux_mode_MASK)
62765#define IOMUXD_MIPI_DSI1_I2C0_SCL_update_pad_ctl_MASK (0x40000000U)
62766#define IOMUXD_MIPI_DSI1_I2C0_SCL_update_pad_ctl_SHIFT (30U)
62767/*! update_pad_ctl - update lock for pad control
62768 */
62769#define IOMUXD_MIPI_DSI1_I2C0_SCL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_update_pad_ctl_MASK)
62770#define IOMUXD_MIPI_DSI1_I2C0_SCL_update_mux_mode_MASK (0x80000000U)
62771#define IOMUXD_MIPI_DSI1_I2C0_SCL_update_mux_mode_SHIFT (31U)
62772/*! update_mux_mode - update lock for mux control
62773 */
62774#define IOMUXD_MIPI_DSI1_I2C0_SCL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SCL_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SCL_update_mux_mode_MASK)
62775/*! @} */
62776
62777/*! @name MIPI_DSI1_I2C0_SDA - MIPI_DSI1_I2C0_SDA */
62778/*! @{ */
62779#define IOMUXD_MIPI_DSI1_I2C0_SDA_PDRV_MASK (0x1U)
62780#define IOMUXD_MIPI_DSI1_I2C0_SDA_PDRV_SHIFT (0U)
62781/*! PDRV - Drive
62782 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
62783 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
62784 */
62785#define IOMUXD_MIPI_DSI1_I2C0_SDA_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_PDRV_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_PDRV_MASK)
62786#define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_1_4_MASK (0x1EU)
62787#define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_1_4_SHIFT (1U)
62788/*! MIPI_DSI1_I2C0_SDA_reserved_1_4 - reserved
62789 */
62790#define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_1_4_MASK)
62791#define IOMUXD_MIPI_DSI1_I2C0_SDA_PULL_MASK (0x60U)
62792#define IOMUXD_MIPI_DSI1_I2C0_SDA_PULL_SHIFT (5U)
62793/*! PULL - Pull Down Pull Up
62794 * 0b10..pull down
62795 * 0b01..pull up
62796 * 0b00..Prohibited
62797 * 0b11..pull disabled
62798 */
62799#define IOMUXD_MIPI_DSI1_I2C0_SDA_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_PULL_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_PULL_MASK)
62800#define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_7_18_MASK (0x7FF80U)
62801#define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_7_18_SHIFT (7U)
62802/*! MIPI_DSI1_I2C0_SDA_reserved_7_18 - reserved
62803 */
62804#define IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA_reserved_7_18_MASK)
62805#define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_CTRL_MASK (0x380000U)
62806#define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_CTRL_SHIFT (19U)
62807/*! WAKEUP_CTRL - wakeup control
62808 * 0b000..OFF
62809 * 0b001..RESAMPLE
62810 * 0b100..LOW
62811 * 0b111..HIGH
62812 * 0b110..RISE
62813 * 0b101..FALL
62814 */
62815#define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_CTRL_MASK)
62816#define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_MASK_MASK (0x400000U)
62817#define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_MASK_SHIFT (22U)
62818/*! WAKEUP_MASK - wakeup mask
62819 */
62820#define IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_WAKEUP_MASK_MASK)
62821#define IOMUXD_MIPI_DSI1_I2C0_SDA_lp_config_MASK (0x1800000U)
62822#define IOMUXD_MIPI_DSI1_I2C0_SDA_lp_config_SHIFT (23U)
62823/*! lp_config - lower power configuration
62824 * 0b01..EARLY_ISO
62825 * 0b10..LATE_ISO
62826 * 0b11..LATCH
62827 * 0b00..PASS
62828 */
62829#define IOMUXD_MIPI_DSI1_I2C0_SDA_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_lp_config_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_lp_config_MASK)
62830#define IOMUXD_MIPI_DSI1_I2C0_SDA_sw_config_MASK (0x6000000U)
62831#define IOMUXD_MIPI_DSI1_I2C0_SDA_sw_config_SHIFT (25U)
62832/*! sw_config - output and input configuration
62833 * 0b01..OPEN_DRAIN
62834 * 0b10..OPEN_DRAIN_INPUT
62835 * 0b11..INOUT
62836 * 0b00..DEFAULT
62837 */
62838#define IOMUXD_MIPI_DSI1_I2C0_SDA_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_sw_config_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_sw_config_MASK)
62839#define IOMUXD_MIPI_DSI1_I2C0_SDA_mux_mode_MASK (0x38000000U)
62840#define IOMUXD_MIPI_DSI1_I2C0_SDA_mux_mode_SHIFT (27U)
62841/*! mux_mode - mux_mode
62842 * 0b000..MIPI_DSI1.I2C0.SDA
62843 * 0b001..MIPI_DSI0.GPIO0.IO03
62844 * 0b100..LSIO.GPIO1.IO30
62845 */
62846#define IOMUXD_MIPI_DSI1_I2C0_SDA_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_mux_mode_MASK)
62847#define IOMUXD_MIPI_DSI1_I2C0_SDA_update_pad_ctl_MASK (0x40000000U)
62848#define IOMUXD_MIPI_DSI1_I2C0_SDA_update_pad_ctl_SHIFT (30U)
62849/*! update_pad_ctl - update lock for pad control
62850 */
62851#define IOMUXD_MIPI_DSI1_I2C0_SDA_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_update_pad_ctl_MASK)
62852#define IOMUXD_MIPI_DSI1_I2C0_SDA_update_mux_mode_MASK (0x80000000U)
62853#define IOMUXD_MIPI_DSI1_I2C0_SDA_update_mux_mode_SHIFT (31U)
62854/*! update_mux_mode - update lock for mux control
62855 */
62856#define IOMUXD_MIPI_DSI1_I2C0_SDA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_I2C0_SDA_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_I2C0_SDA_update_mux_mode_MASK)
62857/*! @} */
62858
62859/*! @name MIPI_DSI1_GPIO0_00 - MIPI_DSI1_GPIO0_00 */
62860/*! @{ */
62861#define IOMUXD_MIPI_DSI1_GPIO0_00_PDRV_MASK (0x1U)
62862#define IOMUXD_MIPI_DSI1_GPIO0_00_PDRV_SHIFT (0U)
62863/*! PDRV - Drive
62864 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
62865 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
62866 */
62867#define IOMUXD_MIPI_DSI1_GPIO0_00_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_PDRV_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_PDRV_MASK)
62868#define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_1_4_MASK (0x1EU)
62869#define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_1_4_SHIFT (1U)
62870/*! MIPI_DSI1_GPIO0_00_reserved_1_4 - reserved
62871 */
62872#define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_1_4_MASK)
62873#define IOMUXD_MIPI_DSI1_GPIO0_00_PULL_MASK (0x60U)
62874#define IOMUXD_MIPI_DSI1_GPIO0_00_PULL_SHIFT (5U)
62875/*! PULL - Pull Down Pull Up
62876 * 0b10..pull down
62877 * 0b01..pull up
62878 * 0b00..Prohibited
62879 * 0b11..pull disabled
62880 */
62881#define IOMUXD_MIPI_DSI1_GPIO0_00_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_PULL_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_PULL_MASK)
62882#define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_7_18_MASK (0x7FF80U)
62883#define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_7_18_SHIFT (7U)
62884/*! MIPI_DSI1_GPIO0_00_reserved_7_18 - reserved
62885 */
62886#define IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_MIPI_DSI1_GPIO0_00_reserved_7_18_MASK)
62887#define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_CTRL_MASK (0x380000U)
62888#define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_CTRL_SHIFT (19U)
62889/*! WAKEUP_CTRL - wakeup control
62890 * 0b000..OFF
62891 * 0b001..RESAMPLE
62892 * 0b100..LOW
62893 * 0b111..HIGH
62894 * 0b110..RISE
62895 * 0b101..FALL
62896 */
62897#define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_CTRL_MASK)
62898#define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_MASK_MASK (0x400000U)
62899#define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_MASK_SHIFT (22U)
62900/*! WAKEUP_MASK - wakeup mask
62901 */
62902#define IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_WAKEUP_MASK_MASK)
62903#define IOMUXD_MIPI_DSI1_GPIO0_00_lp_config_MASK (0x1800000U)
62904#define IOMUXD_MIPI_DSI1_GPIO0_00_lp_config_SHIFT (23U)
62905/*! lp_config - lower power configuration
62906 * 0b01..EARLY_ISO
62907 * 0b10..LATE_ISO
62908 * 0b11..LATCH
62909 * 0b00..PASS
62910 */
62911#define IOMUXD_MIPI_DSI1_GPIO0_00_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_lp_config_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_lp_config_MASK)
62912#define IOMUXD_MIPI_DSI1_GPIO0_00_sw_config_MASK (0x6000000U)
62913#define IOMUXD_MIPI_DSI1_GPIO0_00_sw_config_SHIFT (25U)
62914/*! sw_config - output and input configuration
62915 * 0b01..OPEN_DRAIN
62916 * 0b10..OPEN_DRAIN_INPUT
62917 * 0b11..INOUT
62918 * 0b00..DEFAULT
62919 */
62920#define IOMUXD_MIPI_DSI1_GPIO0_00_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_sw_config_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_sw_config_MASK)
62921#define IOMUXD_MIPI_DSI1_GPIO0_00_mux_mode_MASK (0x38000000U)
62922#define IOMUXD_MIPI_DSI1_GPIO0_00_mux_mode_SHIFT (27U)
62923/*! mux_mode - mux_mode
62924 * 0b000..MIPI_DSI1.GPIO0.IO00
62925 * 0b001..ADMA.I2C2.SCL
62926 * 0b010..MIPI_DSI1.PWM0.OUT
62927 * 0b100..LSIO.GPIO1.IO31
62928 */
62929#define IOMUXD_MIPI_DSI1_GPIO0_00_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_mux_mode_MASK)
62930#define IOMUXD_MIPI_DSI1_GPIO0_00_update_pad_ctl_MASK (0x40000000U)
62931#define IOMUXD_MIPI_DSI1_GPIO0_00_update_pad_ctl_SHIFT (30U)
62932/*! update_pad_ctl - update lock for pad control
62933 */
62934#define IOMUXD_MIPI_DSI1_GPIO0_00_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_update_pad_ctl_MASK)
62935#define IOMUXD_MIPI_DSI1_GPIO0_00_update_mux_mode_MASK (0x80000000U)
62936#define IOMUXD_MIPI_DSI1_GPIO0_00_update_mux_mode_SHIFT (31U)
62937/*! update_mux_mode - update lock for mux control
62938 */
62939#define IOMUXD_MIPI_DSI1_GPIO0_00_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_00_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_00_update_mux_mode_MASK)
62940/*! @} */
62941
62942/*! @name MIPI_DSI1_GPIO0_01 - MIPI_DSI1_GPIO0_01 */
62943/*! @{ */
62944#define IOMUXD_MIPI_DSI1_GPIO0_01_PDRV_MASK (0x1U)
62945#define IOMUXD_MIPI_DSI1_GPIO0_01_PDRV_SHIFT (0U)
62946/*! PDRV - Drive
62947 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
62948 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
62949 */
62950#define IOMUXD_MIPI_DSI1_GPIO0_01_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_PDRV_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_PDRV_MASK)
62951#define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_1_4_MASK (0x1EU)
62952#define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_1_4_SHIFT (1U)
62953/*! MIPI_DSI1_GPIO0_01_reserved_1_4 - reserved
62954 */
62955#define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_1_4_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_1_4_MASK)
62956#define IOMUXD_MIPI_DSI1_GPIO0_01_PULL_MASK (0x60U)
62957#define IOMUXD_MIPI_DSI1_GPIO0_01_PULL_SHIFT (5U)
62958/*! PULL - Pull Down Pull Up
62959 * 0b10..pull down
62960 * 0b01..pull up
62961 * 0b00..Prohibited
62962 * 0b11..pull disabled
62963 */
62964#define IOMUXD_MIPI_DSI1_GPIO0_01_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_PULL_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_PULL_MASK)
62965#define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_7_18_MASK (0x7FF80U)
62966#define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_7_18_SHIFT (7U)
62967/*! MIPI_DSI1_GPIO0_01_reserved_7_18 - reserved
62968 */
62969#define IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_7_18_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_MIPI_DSI1_GPIO0_01_reserved_7_18_MASK)
62970#define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_CTRL_MASK (0x380000U)
62971#define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_CTRL_SHIFT (19U)
62972/*! WAKEUP_CTRL - wakeup control
62973 * 0b000..OFF
62974 * 0b001..RESAMPLE
62975 * 0b100..LOW
62976 * 0b111..HIGH
62977 * 0b110..RISE
62978 * 0b101..FALL
62979 */
62980#define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_CTRL_MASK)
62981#define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_MASK_MASK (0x400000U)
62982#define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_MASK_SHIFT (22U)
62983/*! WAKEUP_MASK - wakeup mask
62984 */
62985#define IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_WAKEUP_MASK_MASK)
62986#define IOMUXD_MIPI_DSI1_GPIO0_01_lp_config_MASK (0x1800000U)
62987#define IOMUXD_MIPI_DSI1_GPIO0_01_lp_config_SHIFT (23U)
62988/*! lp_config - lower power configuration
62989 * 0b01..EARLY_ISO
62990 * 0b10..LATE_ISO
62991 * 0b11..LATCH
62992 * 0b00..PASS
62993 */
62994#define IOMUXD_MIPI_DSI1_GPIO0_01_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_lp_config_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_lp_config_MASK)
62995#define IOMUXD_MIPI_DSI1_GPIO0_01_sw_config_MASK (0x6000000U)
62996#define IOMUXD_MIPI_DSI1_GPIO0_01_sw_config_SHIFT (25U)
62997/*! sw_config - output and input configuration
62998 * 0b01..OPEN_DRAIN
62999 * 0b10..OPEN_DRAIN_INPUT
63000 * 0b11..INOUT
63001 * 0b00..DEFAULT
63002 */
63003#define IOMUXD_MIPI_DSI1_GPIO0_01_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_sw_config_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_sw_config_MASK)
63004#define IOMUXD_MIPI_DSI1_GPIO0_01_mux_mode_MASK (0x38000000U)
63005#define IOMUXD_MIPI_DSI1_GPIO0_01_mux_mode_SHIFT (27U)
63006/*! mux_mode - mux_mode
63007 * 0b000..MIPI_DSI1.GPIO0.IO01
63008 * 0b001..ADMA.I2C2.SDA
63009 * 0b100..LSIO.GPIO2.IO00
63010 */
63011#define IOMUXD_MIPI_DSI1_GPIO0_01_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_mux_mode_MASK)
63012#define IOMUXD_MIPI_DSI1_GPIO0_01_update_pad_ctl_MASK (0x40000000U)
63013#define IOMUXD_MIPI_DSI1_GPIO0_01_update_pad_ctl_SHIFT (30U)
63014/*! update_pad_ctl - update lock for pad control
63015 */
63016#define IOMUXD_MIPI_DSI1_GPIO0_01_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_update_pad_ctl_MASK)
63017#define IOMUXD_MIPI_DSI1_GPIO0_01_update_mux_mode_MASK (0x80000000U)
63018#define IOMUXD_MIPI_DSI1_GPIO0_01_update_mux_mode_SHIFT (31U)
63019/*! update_mux_mode - update lock for mux control
63020 */
63021#define IOMUXD_MIPI_DSI1_GPIO0_01_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_DSI1_GPIO0_01_update_mux_mode_SHIFT)) & IOMUXD_MIPI_DSI1_GPIO0_01_update_mux_mode_MASK)
63022/*! @} */
63023
63024/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO - IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO */
63025/*! @{ */
63026#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMP_MASK (0x7U)
63027#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMP_SHIFT (0U)
63028/*! COMP - COMP
63029 * 0b010..Fixed code mode
63030 * 0b100..High impedance mode
63031 * 0b110..Read mode
63032 * 0b000..Normal Mode
63033 * 0b001..Freeze Mode
63034 */
63035#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMP_MASK)
63036#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_FASTFRZ_EN_MASK (0x8U)
63037#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_FASTFRZ_EN_SHIFT (3U)
63038/*! FASTFRZ_EN - FASTFRZ_EN
63039 * 0b1..FASTFRZ signal is driven by output of subsystem
63040 * 0b0..FASTFRZ signal is gated to 0
63041 */
63042#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_FASTFRZ_EN_MASK)
63043#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4_MASK (0x10U)
63044#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4_SHIFT (4U)
63045/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4 - reserved
63046 */
63047#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_4_4_MASK)
63048#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCP_MASK (0x1E0U)
63049#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCP_SHIFT (5U)
63050/*! RASRCP - RASRCP
63051 * 0b0101..Reset Value
63052 */
63053#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCP_MASK)
63054#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCN_MASK (0x1E00U)
63055#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCN_SHIFT (9U)
63056/*! RASRCN - RASRCN
63057 * 0b1010..Reset Value
63058 */
63059#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_RASRCN_MASK)
63060#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SELECT_NASRC_MASK (0x2000U)
63061#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SELECT_NASRC_SHIFT (13U)
63062/*! SELECT_NASRC - SELECT_NASRC
63063 * 0b1..NASRCN value
63064 * 0b0..NASRCP value
63065 */
63066#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SELECT_NASRC_MASK)
63067#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMPOK_MASK (0x4000U)
63068#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMPOK_SHIFT (14U)
63069/*! COMPOK - COMPOK
63070 * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
63071 * 0b1..compensation cell in Normal mode and tracking PVT
63072 */
63073#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_COMPOK_MASK)
63074#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_READ_NASRC_MASK (0x78000U)
63075#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_READ_NASRC_SHIFT (15U)
63076/*! READ_NASRC - READ_NASRC
63077 * 0b0000..READ Only
63078 */
63079#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_READ_NASRC_MASK)
63080#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22_MASK (0x780000U)
63081#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22_SHIFT (19U)
63082/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22 - reserved
63083 */
63084#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_19_22_MASK)
63085#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SLEEP_MASK (0x1800000U)
63086#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SLEEP_SHIFT (23U)
63087/*! SLEEP - SLEEP
63088 * 0b11..Force into sleep mode
63089 * 0b00..NO
63090 * 0b01..EARLY
63091 * 0b10..LATE
63092 */
63093#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_SLEEP_MASK)
63094#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29_MASK (0x3E000000U)
63095#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29_SHIFT (25U)
63096/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29 - reserved
63097 */
63098#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_reserved_25_29_MASK)
63099#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_pad_ctl_MASK (0x40000000U)
63100#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_pad_ctl_SHIFT (30U)
63101/*! update_pad_ctl - update lock for pad control
63102 */
63103#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_pad_ctl_MASK)
63104#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_mux_mode_MASK (0x80000000U)
63105#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_mux_mode_SHIFT (31U)
63106/*! update_mux_mode - update lock for mux control
63107 */
63108#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_update_mux_mode_MASK)
63109/*! @} */
63110
63111/*! @name SCU_WDOG_OUT - SCU_WDOG_OUT */
63112/*! @{ */
63113#define IOMUXD_SCU_WDOG_OUT_DSE_MASK (0x7U)
63114#define IOMUXD_SCU_WDOG_OUT_DSE_SHIFT (0U)
63115/*! DSE - Drive
63116 * 0b001..Drive select 2mA
63117 * 0b011..Drive select 6mA
63118 * 0b111..High Speed
63119 * 0b110..Drive select 12mA
63120 * 0b010..Drive select 4mA
63121 * 0b100..Drive select 8mA
63122 * 0b000..Drive select 1mA
63123 * 0b101..Drive select 10mA
63124 */
63125#define IOMUXD_SCU_WDOG_OUT_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_DSE_SHIFT)) & IOMUXD_SCU_WDOG_OUT_DSE_MASK)
63126#define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_3_4_MASK (0x18U)
63127#define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_3_4_SHIFT (3U)
63128/*! SCU_WDOG_OUT_reserved_3_4 - reserved
63129 */
63130#define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_3_4_SHIFT)) & IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_3_4_MASK)
63131#define IOMUXD_SCU_WDOG_OUT_PULL_MASK (0x60U)
63132#define IOMUXD_SCU_WDOG_OUT_PULL_SHIFT (5U)
63133/*! PULL - Pull Down Pull Up
63134 * 0b00..Bus-Keeper
63135 * 0b10..pull down
63136 * 0b01..pull up
63137 * 0b11..No Pull
63138 */
63139#define IOMUXD_SCU_WDOG_OUT_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_PULL_SHIFT)) & IOMUXD_SCU_WDOG_OUT_PULL_MASK)
63140#define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_7_18_MASK (0x7FF80U)
63141#define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_7_18_SHIFT (7U)
63142/*! SCU_WDOG_OUT_reserved_7_18 - reserved
63143 */
63144#define IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_7_18_SHIFT)) & IOMUXD_SCU_WDOG_OUT_SCU_WDOG_OUT_reserved_7_18_MASK)
63145#define IOMUXD_SCU_WDOG_OUT_WAKEUP_CTRL_MASK (0x380000U)
63146#define IOMUXD_SCU_WDOG_OUT_WAKEUP_CTRL_SHIFT (19U)
63147/*! WAKEUP_CTRL - wakeup control
63148 * 0b000..OFF
63149 * 0b001..RESAMPLE
63150 * 0b100..LOW
63151 * 0b111..HIGH
63152 * 0b110..RISE
63153 * 0b101..FALL
63154 */
63155#define IOMUXD_SCU_WDOG_OUT_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_WDOG_OUT_WAKEUP_CTRL_MASK)
63156#define IOMUXD_SCU_WDOG_OUT_WAKEUP_MASK_MASK (0x400000U)
63157#define IOMUXD_SCU_WDOG_OUT_WAKEUP_MASK_SHIFT (22U)
63158/*! WAKEUP_MASK - wakeup mask
63159 */
63160#define IOMUXD_SCU_WDOG_OUT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_WDOG_OUT_WAKEUP_MASK_MASK)
63161#define IOMUXD_SCU_WDOG_OUT_lp_config_MASK (0x1800000U)
63162#define IOMUXD_SCU_WDOG_OUT_lp_config_SHIFT (23U)
63163/*! lp_config - lower power configuration
63164 * 0b01..EARLY_ISO
63165 * 0b10..LATE_ISO
63166 * 0b11..LATCH
63167 * 0b00..PASS
63168 */
63169#define IOMUXD_SCU_WDOG_OUT_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_lp_config_SHIFT)) & IOMUXD_SCU_WDOG_OUT_lp_config_MASK)
63170#define IOMUXD_SCU_WDOG_OUT_sw_config_MASK (0x6000000U)
63171#define IOMUXD_SCU_WDOG_OUT_sw_config_SHIFT (25U)
63172/*! sw_config - output and input configuration
63173 * 0b01..OPEN_DRAIN
63174 * 0b10..OPEN_DRAIN_INPUT
63175 * 0b11..INOUT
63176 * 0b00..DEFAULT
63177 */
63178#define IOMUXD_SCU_WDOG_OUT_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_sw_config_SHIFT)) & IOMUXD_SCU_WDOG_OUT_sw_config_MASK)
63179#define IOMUXD_SCU_WDOG_OUT_mux_mode_MASK (0x38000000U)
63180#define IOMUXD_SCU_WDOG_OUT_mux_mode_SHIFT (27U)
63181/*! mux_mode - mux_mode
63182 * 0b001..SCU.WDOG0.WDOG_OUT
63183 */
63184#define IOMUXD_SCU_WDOG_OUT_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_mux_mode_SHIFT)) & IOMUXD_SCU_WDOG_OUT_mux_mode_MASK)
63185#define IOMUXD_SCU_WDOG_OUT_update_pad_ctl_MASK (0x40000000U)
63186#define IOMUXD_SCU_WDOG_OUT_update_pad_ctl_SHIFT (30U)
63187/*! update_pad_ctl - update lock for pad control
63188 */
63189#define IOMUXD_SCU_WDOG_OUT_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_update_pad_ctl_SHIFT)) & IOMUXD_SCU_WDOG_OUT_update_pad_ctl_MASK)
63190#define IOMUXD_SCU_WDOG_OUT_update_mux_mode_MASK (0x80000000U)
63191#define IOMUXD_SCU_WDOG_OUT_update_mux_mode_SHIFT (31U)
63192/*! update_mux_mode - update lock for mux control
63193 */
63194#define IOMUXD_SCU_WDOG_OUT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_WDOG_OUT_update_mux_mode_SHIFT)) & IOMUXD_SCU_WDOG_OUT_update_mux_mode_MASK)
63195/*! @} */
63196
63197/*! @name PMIC_I2C_SCL - PMIC_I2C_SCL */
63198/*! @{ */
63199#define IOMUXD_PMIC_I2C_SCL_DSE_MASK (0x7U)
63200#define IOMUXD_PMIC_I2C_SCL_DSE_SHIFT (0U)
63201/*! DSE - Drive
63202 * 0b001..Drive select 2mA
63203 * 0b011..Drive select 6mA
63204 * 0b111..High Speed
63205 * 0b110..Drive select 12mA
63206 * 0b010..Drive select 4mA
63207 * 0b100..Drive select 8mA
63208 * 0b000..Drive select 1mA
63209 * 0b101..Drive select 10mA
63210 */
63211#define IOMUXD_PMIC_I2C_SCL_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_DSE_SHIFT)) & IOMUXD_PMIC_I2C_SCL_DSE_MASK)
63212#define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_3_4_MASK (0x18U)
63213#define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_3_4_SHIFT (3U)
63214/*! PMIC_I2C_SCL_reserved_3_4 - reserved
63215 */
63216#define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_3_4_SHIFT)) & IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_3_4_MASK)
63217#define IOMUXD_PMIC_I2C_SCL_PULL_MASK (0x60U)
63218#define IOMUXD_PMIC_I2C_SCL_PULL_SHIFT (5U)
63219/*! PULL - Pull Down Pull Up
63220 * 0b00..Bus-Keeper
63221 * 0b10..pull down
63222 * 0b01..pull up
63223 * 0b11..No Pull
63224 */
63225#define IOMUXD_PMIC_I2C_SCL_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_PULL_SHIFT)) & IOMUXD_PMIC_I2C_SCL_PULL_MASK)
63226#define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_7_18_MASK (0x7FF80U)
63227#define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_7_18_SHIFT (7U)
63228/*! PMIC_I2C_SCL_reserved_7_18 - reserved
63229 */
63230#define IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_7_18_SHIFT)) & IOMUXD_PMIC_I2C_SCL_PMIC_I2C_SCL_reserved_7_18_MASK)
63231#define IOMUXD_PMIC_I2C_SCL_WAKEUP_CTRL_MASK (0x380000U)
63232#define IOMUXD_PMIC_I2C_SCL_WAKEUP_CTRL_SHIFT (19U)
63233/*! WAKEUP_CTRL - wakeup control
63234 * 0b000..OFF
63235 * 0b001..RESAMPLE
63236 * 0b100..LOW
63237 * 0b111..HIGH
63238 * 0b110..RISE
63239 * 0b101..FALL
63240 */
63241#define IOMUXD_PMIC_I2C_SCL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_PMIC_I2C_SCL_WAKEUP_CTRL_MASK)
63242#define IOMUXD_PMIC_I2C_SCL_WAKEUP_MASK_MASK (0x400000U)
63243#define IOMUXD_PMIC_I2C_SCL_WAKEUP_MASK_SHIFT (22U)
63244/*! WAKEUP_MASK - wakeup mask
63245 */
63246#define IOMUXD_PMIC_I2C_SCL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_PMIC_I2C_SCL_WAKEUP_MASK_MASK)
63247#define IOMUXD_PMIC_I2C_SCL_lp_config_MASK (0x1800000U)
63248#define IOMUXD_PMIC_I2C_SCL_lp_config_SHIFT (23U)
63249/*! lp_config - lower power configuration
63250 * 0b01..EARLY_ISO
63251 * 0b10..LATE_ISO
63252 * 0b11..LATCH
63253 * 0b00..PASS
63254 */
63255#define IOMUXD_PMIC_I2C_SCL_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_lp_config_SHIFT)) & IOMUXD_PMIC_I2C_SCL_lp_config_MASK)
63256#define IOMUXD_PMIC_I2C_SCL_sw_config_MASK (0x6000000U)
63257#define IOMUXD_PMIC_I2C_SCL_sw_config_SHIFT (25U)
63258/*! sw_config - output and input configuration
63259 * 0b01..OPEN_DRAIN
63260 * 0b10..OPEN_DRAIN_INPUT
63261 * 0b11..INOUT
63262 * 0b00..DEFAULT
63263 */
63264#define IOMUXD_PMIC_I2C_SCL_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_sw_config_SHIFT)) & IOMUXD_PMIC_I2C_SCL_sw_config_MASK)
63265#define IOMUXD_PMIC_I2C_SCL_mux_mode_MASK (0x38000000U)
63266#define IOMUXD_PMIC_I2C_SCL_mux_mode_SHIFT (27U)
63267/*! mux_mode - mux_mode
63268 * 0b000..SCU.PMIC_I2C.SCL
63269 * 0b001..SCU.GPIO0.IOXX_PMIC_A35_ON
63270 * 0b100..LSIO.GPIO2.IO01
63271 */
63272#define IOMUXD_PMIC_I2C_SCL_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_mux_mode_SHIFT)) & IOMUXD_PMIC_I2C_SCL_mux_mode_MASK)
63273#define IOMUXD_PMIC_I2C_SCL_update_pad_ctl_MASK (0x40000000U)
63274#define IOMUXD_PMIC_I2C_SCL_update_pad_ctl_SHIFT (30U)
63275/*! update_pad_ctl - update lock for pad control
63276 */
63277#define IOMUXD_PMIC_I2C_SCL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_update_pad_ctl_SHIFT)) & IOMUXD_PMIC_I2C_SCL_update_pad_ctl_MASK)
63278#define IOMUXD_PMIC_I2C_SCL_update_mux_mode_MASK (0x80000000U)
63279#define IOMUXD_PMIC_I2C_SCL_update_mux_mode_SHIFT (31U)
63280/*! update_mux_mode - update lock for mux control
63281 */
63282#define IOMUXD_PMIC_I2C_SCL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SCL_update_mux_mode_SHIFT)) & IOMUXD_PMIC_I2C_SCL_update_mux_mode_MASK)
63283/*! @} */
63284
63285/*! @name IOMUXD_GROUP_2_2 - na */
63286/*! @{ */
63287#define IOMUXD_IOMUXD_GROUP_2_2_UART0_TX_MASK (0x1U)
63288#define IOMUXD_IOMUXD_GROUP_2_2_UART0_TX_SHIFT (0U)
63289/*! UART0_TX - wakeup from UART0_TX
63290 */
63291#define IOMUXD_IOMUXD_GROUP_2_2_UART0_TX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_UART0_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_UART0_TX_MASK)
63292#define IOMUXD_IOMUXD_GROUP_2_2_UART2_TX_MASK (0x2U)
63293#define IOMUXD_IOMUXD_GROUP_2_2_UART2_TX_SHIFT (1U)
63294/*! UART2_TX - wakeup from UART2_TX
63295 */
63296#define IOMUXD_IOMUXD_GROUP_2_2_UART2_TX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_UART2_TX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_UART2_TX_MASK)
63297#define IOMUXD_IOMUXD_GROUP_2_2_UART2_RX_MASK (0x4U)
63298#define IOMUXD_IOMUXD_GROUP_2_2_UART2_RX_SHIFT (2U)
63299/*! UART2_RX - wakeup from UART2_RX
63300 */
63301#define IOMUXD_IOMUXD_GROUP_2_2_UART2_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_UART2_RX_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_UART2_RX_MASK)
63302#define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_3_3_MASK (0x8U)
63303#define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_3_3_SHIFT (3U)
63304/*! iomuxd_group_2_2_reserved_3_3 - reserved
63305 */
63306#define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_3_3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_3_3_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_3_3_MASK)
63307#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SCL_MASK (0x10U)
63308#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SCL_SHIFT (4U)
63309/*! MIPI_DSI0_I2C0_SCL - wakeup from MIPI_DSI0_I2C0_SCL
63310 */
63311#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SCL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SCL_MASK)
63312#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SDA_MASK (0x20U)
63313#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SDA_SHIFT (5U)
63314/*! MIPI_DSI0_I2C0_SDA - wakeup from MIPI_DSI0_I2C0_SDA
63315 */
63316#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SDA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_I2C0_SDA_MASK)
63317#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_00_MASK (0x40U)
63318#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_00_SHIFT (6U)
63319/*! MIPI_DSI0_GPIO0_00 - wakeup from MIPI_DSI0_GPIO0_00
63320 */
63321#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_00(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_00_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_00_MASK)
63322#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_01_MASK (0x80U)
63323#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_01_SHIFT (7U)
63324/*! MIPI_DSI0_GPIO0_01 - wakeup from MIPI_DSI0_GPIO0_01
63325 */
63326#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_01(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_01_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI0_GPIO0_01_MASK)
63327#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SCL_MASK (0x100U)
63328#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SCL_SHIFT (8U)
63329/*! MIPI_DSI1_I2C0_SCL - wakeup from MIPI_DSI1_I2C0_SCL
63330 */
63331#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SCL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SCL_MASK)
63332#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SDA_MASK (0x200U)
63333#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SDA_SHIFT (9U)
63334/*! MIPI_DSI1_I2C0_SDA - wakeup from MIPI_DSI1_I2C0_SDA
63335 */
63336#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SDA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_I2C0_SDA_MASK)
63337#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_00_MASK (0x400U)
63338#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_00_SHIFT (10U)
63339/*! MIPI_DSI1_GPIO0_00 - wakeup from MIPI_DSI1_GPIO0_00
63340 */
63341#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_00(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_00_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_00_MASK)
63342#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_01_MASK (0x800U)
63343#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_01_SHIFT (11U)
63344/*! MIPI_DSI1_GPIO0_01 - wakeup from MIPI_DSI1_GPIO0_01
63345 */
63346#define IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_01(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_01_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_MIPI_DSI1_GPIO0_01_MASK)
63347#define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_12_12_MASK (0x1000U)
63348#define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_12_12_SHIFT (12U)
63349/*! iomuxd_group_2_2_reserved_12_12 - reserved
63350 */
63351#define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_12_12_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_12_12_MASK)
63352#define IOMUXD_IOMUXD_GROUP_2_2_SCU_WDOG_OUT_MASK (0x2000U)
63353#define IOMUXD_IOMUXD_GROUP_2_2_SCU_WDOG_OUT_SHIFT (13U)
63354/*! SCU_WDOG_OUT - wakeup from SCU_WDOG_OUT
63355 */
63356#define IOMUXD_IOMUXD_GROUP_2_2_SCU_WDOG_OUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_SCU_WDOG_OUT_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_SCU_WDOG_OUT_MASK)
63357#define IOMUXD_IOMUXD_GROUP_2_2_PMIC_I2C_SCL_MASK (0x4000U)
63358#define IOMUXD_IOMUXD_GROUP_2_2_PMIC_I2C_SCL_SHIFT (14U)
63359/*! PMIC_I2C_SCL - wakeup from PMIC_I2C_SCL
63360 */
63361#define IOMUXD_IOMUXD_GROUP_2_2_PMIC_I2C_SCL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_PMIC_I2C_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_PMIC_I2C_SCL_MASK)
63362#define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_15_31_MASK (0xFFFF8000U)
63363#define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_15_31_SHIFT (15U)
63364/*! iomuxd_group_2_2_reserved_15_31 - reserved
63365 */
63366#define IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_2_iomuxd_group_2_2_reserved_15_31_MASK)
63367/*! @} */
63368
63369/*! @name PMIC_I2C_SDA - PMIC_I2C_SDA */
63370/*! @{ */
63371#define IOMUXD_PMIC_I2C_SDA_DSE_MASK (0x7U)
63372#define IOMUXD_PMIC_I2C_SDA_DSE_SHIFT (0U)
63373/*! DSE - Drive
63374 * 0b001..Drive select 2mA
63375 * 0b011..Drive select 6mA
63376 * 0b111..High Speed
63377 * 0b110..Drive select 12mA
63378 * 0b010..Drive select 4mA
63379 * 0b100..Drive select 8mA
63380 * 0b000..Drive select 1mA
63381 * 0b101..Drive select 10mA
63382 */
63383#define IOMUXD_PMIC_I2C_SDA_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_DSE_SHIFT)) & IOMUXD_PMIC_I2C_SDA_DSE_MASK)
63384#define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_3_4_MASK (0x18U)
63385#define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_3_4_SHIFT (3U)
63386/*! PMIC_I2C_SDA_reserved_3_4 - reserved
63387 */
63388#define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_3_4_SHIFT)) & IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_3_4_MASK)
63389#define IOMUXD_PMIC_I2C_SDA_PULL_MASK (0x60U)
63390#define IOMUXD_PMIC_I2C_SDA_PULL_SHIFT (5U)
63391/*! PULL - Pull Down Pull Up
63392 * 0b00..Bus-Keeper
63393 * 0b10..pull down
63394 * 0b01..pull up
63395 * 0b11..No Pull
63396 */
63397#define IOMUXD_PMIC_I2C_SDA_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_PULL_SHIFT)) & IOMUXD_PMIC_I2C_SDA_PULL_MASK)
63398#define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_7_18_MASK (0x7FF80U)
63399#define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_7_18_SHIFT (7U)
63400/*! PMIC_I2C_SDA_reserved_7_18 - reserved
63401 */
63402#define IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_7_18_SHIFT)) & IOMUXD_PMIC_I2C_SDA_PMIC_I2C_SDA_reserved_7_18_MASK)
63403#define IOMUXD_PMIC_I2C_SDA_WAKEUP_CTRL_MASK (0x380000U)
63404#define IOMUXD_PMIC_I2C_SDA_WAKEUP_CTRL_SHIFT (19U)
63405/*! WAKEUP_CTRL - wakeup control
63406 * 0b000..OFF
63407 * 0b001..RESAMPLE
63408 * 0b100..LOW
63409 * 0b111..HIGH
63410 * 0b110..RISE
63411 * 0b101..FALL
63412 */
63413#define IOMUXD_PMIC_I2C_SDA_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_PMIC_I2C_SDA_WAKEUP_CTRL_MASK)
63414#define IOMUXD_PMIC_I2C_SDA_WAKEUP_MASK_MASK (0x400000U)
63415#define IOMUXD_PMIC_I2C_SDA_WAKEUP_MASK_SHIFT (22U)
63416/*! WAKEUP_MASK - wakeup mask
63417 */
63418#define IOMUXD_PMIC_I2C_SDA_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_PMIC_I2C_SDA_WAKEUP_MASK_MASK)
63419#define IOMUXD_PMIC_I2C_SDA_lp_config_MASK (0x1800000U)
63420#define IOMUXD_PMIC_I2C_SDA_lp_config_SHIFT (23U)
63421/*! lp_config - lower power configuration
63422 * 0b01..EARLY_ISO
63423 * 0b10..LATE_ISO
63424 * 0b11..LATCH
63425 * 0b00..PASS
63426 */
63427#define IOMUXD_PMIC_I2C_SDA_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_lp_config_SHIFT)) & IOMUXD_PMIC_I2C_SDA_lp_config_MASK)
63428#define IOMUXD_PMIC_I2C_SDA_sw_config_MASK (0x6000000U)
63429#define IOMUXD_PMIC_I2C_SDA_sw_config_SHIFT (25U)
63430/*! sw_config - output and input configuration
63431 * 0b01..OPEN_DRAIN
63432 * 0b10..OPEN_DRAIN_INPUT
63433 * 0b11..INOUT
63434 * 0b00..DEFAULT
63435 */
63436#define IOMUXD_PMIC_I2C_SDA_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_sw_config_SHIFT)) & IOMUXD_PMIC_I2C_SDA_sw_config_MASK)
63437#define IOMUXD_PMIC_I2C_SDA_mux_mode_MASK (0x38000000U)
63438#define IOMUXD_PMIC_I2C_SDA_mux_mode_SHIFT (27U)
63439/*! mux_mode - mux_mode
63440 * 0b000..SCU.PMIC_I2C.SDA
63441 * 0b001..SCU.GPIO0.IOXX_PMIC_GPU_ON
63442 * 0b100..LSIO.GPIO2.IO02
63443 */
63444#define IOMUXD_PMIC_I2C_SDA_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_mux_mode_SHIFT)) & IOMUXD_PMIC_I2C_SDA_mux_mode_MASK)
63445#define IOMUXD_PMIC_I2C_SDA_update_pad_ctl_MASK (0x40000000U)
63446#define IOMUXD_PMIC_I2C_SDA_update_pad_ctl_SHIFT (30U)
63447/*! update_pad_ctl - update lock for pad control
63448 */
63449#define IOMUXD_PMIC_I2C_SDA_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_update_pad_ctl_SHIFT)) & IOMUXD_PMIC_I2C_SDA_update_pad_ctl_MASK)
63450#define IOMUXD_PMIC_I2C_SDA_update_mux_mode_MASK (0x80000000U)
63451#define IOMUXD_PMIC_I2C_SDA_update_mux_mode_SHIFT (31U)
63452/*! update_mux_mode - update lock for mux control
63453 */
63454#define IOMUXD_PMIC_I2C_SDA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_I2C_SDA_update_mux_mode_SHIFT)) & IOMUXD_PMIC_I2C_SDA_update_mux_mode_MASK)
63455/*! @} */
63456
63457/*! @name PMIC_INT_B - PMIC_INT_B */
63458/*! @{ */
63459#define IOMUXD_PMIC_INT_B_DSE_MASK (0x7U)
63460#define IOMUXD_PMIC_INT_B_DSE_SHIFT (0U)
63461/*! DSE - Drive
63462 * 0b001..Drive select 2mA
63463 * 0b011..Drive select 6mA
63464 * 0b111..High Speed
63465 * 0b110..Drive select 12mA
63466 * 0b010..Drive select 4mA
63467 * 0b100..Drive select 8mA
63468 * 0b000..Drive select 1mA
63469 * 0b101..Drive select 10mA
63470 */
63471#define IOMUXD_PMIC_INT_B_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_DSE_SHIFT)) & IOMUXD_PMIC_INT_B_DSE_MASK)
63472#define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_3_4_MASK (0x18U)
63473#define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_3_4_SHIFT (3U)
63474/*! PMIC_INT_B_reserved_3_4 - reserved
63475 */
63476#define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_3_4_SHIFT)) & IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_3_4_MASK)
63477#define IOMUXD_PMIC_INT_B_PULL_MASK (0x60U)
63478#define IOMUXD_PMIC_INT_B_PULL_SHIFT (5U)
63479/*! PULL - Pull Down Pull Up
63480 * 0b00..Bus-Keeper
63481 * 0b10..pull down
63482 * 0b01..pull up
63483 * 0b11..No Pull
63484 */
63485#define IOMUXD_PMIC_INT_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_PULL_SHIFT)) & IOMUXD_PMIC_INT_B_PULL_MASK)
63486#define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_7_18_MASK (0x7FF80U)
63487#define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_7_18_SHIFT (7U)
63488/*! PMIC_INT_B_reserved_7_18 - reserved
63489 */
63490#define IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_7_18_SHIFT)) & IOMUXD_PMIC_INT_B_PMIC_INT_B_reserved_7_18_MASK)
63491#define IOMUXD_PMIC_INT_B_WAKEUP_CTRL_MASK (0x380000U)
63492#define IOMUXD_PMIC_INT_B_WAKEUP_CTRL_SHIFT (19U)
63493/*! WAKEUP_CTRL - wakeup control
63494 * 0b000..OFF
63495 * 0b001..RESAMPLE
63496 * 0b100..LOW
63497 * 0b111..HIGH
63498 * 0b110..RISE
63499 * 0b101..FALL
63500 */
63501#define IOMUXD_PMIC_INT_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_PMIC_INT_B_WAKEUP_CTRL_MASK)
63502#define IOMUXD_PMIC_INT_B_WAKEUP_MASK_MASK (0x400000U)
63503#define IOMUXD_PMIC_INT_B_WAKEUP_MASK_SHIFT (22U)
63504/*! WAKEUP_MASK - wakeup mask
63505 */
63506#define IOMUXD_PMIC_INT_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_WAKEUP_MASK_SHIFT)) & IOMUXD_PMIC_INT_B_WAKEUP_MASK_MASK)
63507#define IOMUXD_PMIC_INT_B_lp_config_MASK (0x1800000U)
63508#define IOMUXD_PMIC_INT_B_lp_config_SHIFT (23U)
63509/*! lp_config - lower power configuration
63510 * 0b01..EARLY_ISO
63511 * 0b10..LATE_ISO
63512 * 0b11..LATCH
63513 * 0b00..PASS
63514 */
63515#define IOMUXD_PMIC_INT_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_lp_config_SHIFT)) & IOMUXD_PMIC_INT_B_lp_config_MASK)
63516#define IOMUXD_PMIC_INT_B_sw_config_MASK (0x6000000U)
63517#define IOMUXD_PMIC_INT_B_sw_config_SHIFT (25U)
63518/*! sw_config - output and input configuration
63519 * 0b01..OPEN_DRAIN
63520 * 0b10..OPEN_DRAIN_INPUT
63521 * 0b11..INOUT
63522 * 0b00..DEFAULT
63523 */
63524#define IOMUXD_PMIC_INT_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_sw_config_SHIFT)) & IOMUXD_PMIC_INT_B_sw_config_MASK)
63525#define IOMUXD_PMIC_INT_B_mux_mode_MASK (0x38000000U)
63526#define IOMUXD_PMIC_INT_B_mux_mode_SHIFT (27U)
63527/*! mux_mode - mux_mode
63528 * 0b000..SCU.DSC.PMIC_INT_B
63529 */
63530#define IOMUXD_PMIC_INT_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_mux_mode_SHIFT)) & IOMUXD_PMIC_INT_B_mux_mode_MASK)
63531#define IOMUXD_PMIC_INT_B_update_pad_ctl_MASK (0x40000000U)
63532#define IOMUXD_PMIC_INT_B_update_pad_ctl_SHIFT (30U)
63533/*! update_pad_ctl - update lock for pad control
63534 */
63535#define IOMUXD_PMIC_INT_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_update_pad_ctl_SHIFT)) & IOMUXD_PMIC_INT_B_update_pad_ctl_MASK)
63536#define IOMUXD_PMIC_INT_B_update_mux_mode_MASK (0x80000000U)
63537#define IOMUXD_PMIC_INT_B_update_mux_mode_SHIFT (31U)
63538/*! update_mux_mode - update lock for mux control
63539 */
63540#define IOMUXD_PMIC_INT_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_PMIC_INT_B_update_mux_mode_SHIFT)) & IOMUXD_PMIC_INT_B_update_mux_mode_MASK)
63541/*! @} */
63542
63543/*! @name SCU_GPIO0_00 - SCU_GPIO0_00 */
63544/*! @{ */
63545#define IOMUXD_SCU_GPIO0_00_DSE_MASK (0x7U)
63546#define IOMUXD_SCU_GPIO0_00_DSE_SHIFT (0U)
63547/*! DSE - Drive
63548 * 0b001..Drive select 2mA
63549 * 0b011..Drive select 6mA
63550 * 0b111..High Speed
63551 * 0b110..Drive select 12mA
63552 * 0b010..Drive select 4mA
63553 * 0b100..Drive select 8mA
63554 * 0b000..Drive select 1mA
63555 * 0b101..Drive select 10mA
63556 */
63557#define IOMUXD_SCU_GPIO0_00_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_DSE_SHIFT)) & IOMUXD_SCU_GPIO0_00_DSE_MASK)
63558#define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_3_4_MASK (0x18U)
63559#define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_3_4_SHIFT (3U)
63560/*! SCU_GPIO0_00_reserved_3_4 - reserved
63561 */
63562#define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_3_4_SHIFT)) & IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_3_4_MASK)
63563#define IOMUXD_SCU_GPIO0_00_PULL_MASK (0x60U)
63564#define IOMUXD_SCU_GPIO0_00_PULL_SHIFT (5U)
63565/*! PULL - Pull Down Pull Up
63566 * 0b00..Bus-Keeper
63567 * 0b10..pull down
63568 * 0b01..pull up
63569 * 0b11..No Pull
63570 */
63571#define IOMUXD_SCU_GPIO0_00_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_PULL_SHIFT)) & IOMUXD_SCU_GPIO0_00_PULL_MASK)
63572#define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_7_18_MASK (0x7FF80U)
63573#define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_7_18_SHIFT (7U)
63574/*! SCU_GPIO0_00_reserved_7_18 - reserved
63575 */
63576#define IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_7_18_SHIFT)) & IOMUXD_SCU_GPIO0_00_SCU_GPIO0_00_reserved_7_18_MASK)
63577#define IOMUXD_SCU_GPIO0_00_WAKEUP_CTRL_MASK (0x380000U)
63578#define IOMUXD_SCU_GPIO0_00_WAKEUP_CTRL_SHIFT (19U)
63579/*! WAKEUP_CTRL - wakeup control
63580 * 0b000..OFF
63581 * 0b001..RESAMPLE
63582 * 0b100..LOW
63583 * 0b111..HIGH
63584 * 0b110..RISE
63585 * 0b101..FALL
63586 */
63587#define IOMUXD_SCU_GPIO0_00_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_GPIO0_00_WAKEUP_CTRL_MASK)
63588#define IOMUXD_SCU_GPIO0_00_WAKEUP_MASK_MASK (0x400000U)
63589#define IOMUXD_SCU_GPIO0_00_WAKEUP_MASK_SHIFT (22U)
63590/*! WAKEUP_MASK - wakeup mask
63591 */
63592#define IOMUXD_SCU_GPIO0_00_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_GPIO0_00_WAKEUP_MASK_MASK)
63593#define IOMUXD_SCU_GPIO0_00_lp_config_MASK (0x1800000U)
63594#define IOMUXD_SCU_GPIO0_00_lp_config_SHIFT (23U)
63595/*! lp_config - lower power configuration
63596 * 0b01..EARLY_ISO
63597 * 0b10..LATE_ISO
63598 * 0b11..LATCH
63599 * 0b00..PASS
63600 */
63601#define IOMUXD_SCU_GPIO0_00_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_lp_config_SHIFT)) & IOMUXD_SCU_GPIO0_00_lp_config_MASK)
63602#define IOMUXD_SCU_GPIO0_00_sw_config_MASK (0x6000000U)
63603#define IOMUXD_SCU_GPIO0_00_sw_config_SHIFT (25U)
63604/*! sw_config - output and input configuration
63605 * 0b01..OPEN_DRAIN
63606 * 0b10..OPEN_DRAIN_INPUT
63607 * 0b11..INOUT
63608 * 0b00..DEFAULT
63609 */
63610#define IOMUXD_SCU_GPIO0_00_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_sw_config_SHIFT)) & IOMUXD_SCU_GPIO0_00_sw_config_MASK)
63611#define IOMUXD_SCU_GPIO0_00_mux_mode_MASK (0x38000000U)
63612#define IOMUXD_SCU_GPIO0_00_mux_mode_SHIFT (27U)
63613/*! mux_mode - mux_mode
63614 * 0b000..SCU.GPIO0.IO00
63615 * 0b001..SCU.UART0.RX
63616 * 0b010..M40.UART0.RX
63617 * 0b011..ADMA.UART3.RX
63618 * 0b100..LSIO.GPIO2.IO03
63619 */
63620#define IOMUXD_SCU_GPIO0_00_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_00_mux_mode_MASK)
63621#define IOMUXD_SCU_GPIO0_00_update_pad_ctl_MASK (0x40000000U)
63622#define IOMUXD_SCU_GPIO0_00_update_pad_ctl_SHIFT (30U)
63623/*! update_pad_ctl - update lock for pad control
63624 */
63625#define IOMUXD_SCU_GPIO0_00_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_update_pad_ctl_SHIFT)) & IOMUXD_SCU_GPIO0_00_update_pad_ctl_MASK)
63626#define IOMUXD_SCU_GPIO0_00_update_mux_mode_MASK (0x80000000U)
63627#define IOMUXD_SCU_GPIO0_00_update_mux_mode_SHIFT (31U)
63628/*! update_mux_mode - update lock for mux control
63629 */
63630#define IOMUXD_SCU_GPIO0_00_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_00_update_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_00_update_mux_mode_MASK)
63631/*! @} */
63632
63633/*! @name SCU_GPIO0_01 - SCU_GPIO0_01 */
63634/*! @{ */
63635#define IOMUXD_SCU_GPIO0_01_DSE_MASK (0x7U)
63636#define IOMUXD_SCU_GPIO0_01_DSE_SHIFT (0U)
63637/*! DSE - Drive
63638 * 0b001..Drive select 2mA
63639 * 0b011..Drive select 6mA
63640 * 0b111..High Speed
63641 * 0b110..Drive select 12mA
63642 * 0b010..Drive select 4mA
63643 * 0b100..Drive select 8mA
63644 * 0b000..Drive select 1mA
63645 * 0b101..Drive select 10mA
63646 */
63647#define IOMUXD_SCU_GPIO0_01_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_DSE_SHIFT)) & IOMUXD_SCU_GPIO0_01_DSE_MASK)
63648#define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_3_4_MASK (0x18U)
63649#define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_3_4_SHIFT (3U)
63650/*! SCU_GPIO0_01_reserved_3_4 - reserved
63651 */
63652#define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_3_4_SHIFT)) & IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_3_4_MASK)
63653#define IOMUXD_SCU_GPIO0_01_PULL_MASK (0x60U)
63654#define IOMUXD_SCU_GPIO0_01_PULL_SHIFT (5U)
63655/*! PULL - Pull Down Pull Up
63656 * 0b00..Bus-Keeper
63657 * 0b10..pull down
63658 * 0b01..pull up
63659 * 0b11..No Pull
63660 */
63661#define IOMUXD_SCU_GPIO0_01_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_PULL_SHIFT)) & IOMUXD_SCU_GPIO0_01_PULL_MASK)
63662#define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_7_18_MASK (0x7FF80U)
63663#define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_7_18_SHIFT (7U)
63664/*! SCU_GPIO0_01_reserved_7_18 - reserved
63665 */
63666#define IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_7_18_SHIFT)) & IOMUXD_SCU_GPIO0_01_SCU_GPIO0_01_reserved_7_18_MASK)
63667#define IOMUXD_SCU_GPIO0_01_WAKEUP_CTRL_MASK (0x380000U)
63668#define IOMUXD_SCU_GPIO0_01_WAKEUP_CTRL_SHIFT (19U)
63669/*! WAKEUP_CTRL - wakeup control
63670 * 0b000..OFF
63671 * 0b001..RESAMPLE
63672 * 0b100..LOW
63673 * 0b111..HIGH
63674 * 0b110..RISE
63675 * 0b101..FALL
63676 */
63677#define IOMUXD_SCU_GPIO0_01_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_GPIO0_01_WAKEUP_CTRL_MASK)
63678#define IOMUXD_SCU_GPIO0_01_WAKEUP_MASK_MASK (0x400000U)
63679#define IOMUXD_SCU_GPIO0_01_WAKEUP_MASK_SHIFT (22U)
63680/*! WAKEUP_MASK - wakeup mask
63681 */
63682#define IOMUXD_SCU_GPIO0_01_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_GPIO0_01_WAKEUP_MASK_MASK)
63683#define IOMUXD_SCU_GPIO0_01_lp_config_MASK (0x1800000U)
63684#define IOMUXD_SCU_GPIO0_01_lp_config_SHIFT (23U)
63685/*! lp_config - lower power configuration
63686 * 0b01..EARLY_ISO
63687 * 0b10..LATE_ISO
63688 * 0b11..LATCH
63689 * 0b00..PASS
63690 */
63691#define IOMUXD_SCU_GPIO0_01_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_lp_config_SHIFT)) & IOMUXD_SCU_GPIO0_01_lp_config_MASK)
63692#define IOMUXD_SCU_GPIO0_01_sw_config_MASK (0x6000000U)
63693#define IOMUXD_SCU_GPIO0_01_sw_config_SHIFT (25U)
63694/*! sw_config - output and input configuration
63695 * 0b01..OPEN_DRAIN
63696 * 0b10..OPEN_DRAIN_INPUT
63697 * 0b11..INOUT
63698 * 0b00..DEFAULT
63699 */
63700#define IOMUXD_SCU_GPIO0_01_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_sw_config_SHIFT)) & IOMUXD_SCU_GPIO0_01_sw_config_MASK)
63701#define IOMUXD_SCU_GPIO0_01_mux_mode_MASK (0x38000000U)
63702#define IOMUXD_SCU_GPIO0_01_mux_mode_SHIFT (27U)
63703/*! mux_mode - mux_mode
63704 * 0b000..SCU.GPIO0.IO01
63705 * 0b001..SCU.UART0.TX
63706 * 0b010..M40.UART0.TX
63707 * 0b011..ADMA.UART3.TX
63708 * 0b100..SCU.WDOG0.WDOG_OUT
63709 */
63710#define IOMUXD_SCU_GPIO0_01_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_01_mux_mode_MASK)
63711#define IOMUXD_SCU_GPIO0_01_update_pad_ctl_MASK (0x40000000U)
63712#define IOMUXD_SCU_GPIO0_01_update_pad_ctl_SHIFT (30U)
63713/*! update_pad_ctl - update lock for pad control
63714 */
63715#define IOMUXD_SCU_GPIO0_01_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_update_pad_ctl_SHIFT)) & IOMUXD_SCU_GPIO0_01_update_pad_ctl_MASK)
63716#define IOMUXD_SCU_GPIO0_01_update_mux_mode_MASK (0x80000000U)
63717#define IOMUXD_SCU_GPIO0_01_update_mux_mode_SHIFT (31U)
63718/*! update_mux_mode - update lock for mux control
63719 */
63720#define IOMUXD_SCU_GPIO0_01_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_GPIO0_01_update_mux_mode_SHIFT)) & IOMUXD_SCU_GPIO0_01_update_mux_mode_MASK)
63721/*! @} */
63722
63723/*! @name SCU_PMIC_STANDBY - SCU_PMIC_STANDBY */
63724/*! @{ */
63725#define IOMUXD_SCU_PMIC_STANDBY_DSE_MASK (0x7U)
63726#define IOMUXD_SCU_PMIC_STANDBY_DSE_SHIFT (0U)
63727/*! DSE - Drive
63728 * 0b001..Drive select 2mA
63729 * 0b011..Drive select 6mA
63730 * 0b111..High Speed
63731 * 0b110..Drive select 12mA
63732 * 0b010..Drive select 4mA
63733 * 0b100..Drive select 8mA
63734 * 0b000..Drive select 1mA
63735 * 0b101..Drive select 10mA
63736 */
63737#define IOMUXD_SCU_PMIC_STANDBY_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_DSE_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_DSE_MASK)
63738#define IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_3_4_MASK (0x18U)
63739#define IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_3_4_SHIFT (3U)
63740/*! SCU_PMIC_STANDBY_reserved_3_4 - reserved
63741 */
63742#define IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_3_4_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_3_4_MASK)
63743#define IOMUXD_SCU_PMIC_STANDBY_PULL_MASK (0x60U)
63744#define IOMUXD_SCU_PMIC_STANDBY_PULL_SHIFT (5U)
63745/*! PULL - Pull Down Pull Up
63746 * 0b00..Bus-Keeper
63747 * 0b10..pull down
63748 * 0b01..pull up
63749 * 0b11..No Pull
63750 */
63751#define IOMUXD_SCU_PMIC_STANDBY_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_PULL_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_PULL_MASK)
63752#define IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_7_18_MASK (0x7FF80U)
63753#define IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_7_18_SHIFT (7U)
63754/*! SCU_PMIC_STANDBY_reserved_7_18 - reserved
63755 */
63756#define IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_7_18_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_SCU_PMIC_STANDBY_reserved_7_18_MASK)
63757#define IOMUXD_SCU_PMIC_STANDBY_WAKEUP_CTRL_MASK (0x380000U)
63758#define IOMUXD_SCU_PMIC_STANDBY_WAKEUP_CTRL_SHIFT (19U)
63759/*! WAKEUP_CTRL - wakeup control
63760 * 0b000..OFF
63761 * 0b001..RESAMPLE
63762 * 0b100..LOW
63763 * 0b111..HIGH
63764 * 0b110..RISE
63765 * 0b101..FALL
63766 */
63767#define IOMUXD_SCU_PMIC_STANDBY_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_WAKEUP_CTRL_MASK)
63768#define IOMUXD_SCU_PMIC_STANDBY_WAKEUP_MASK_MASK (0x400000U)
63769#define IOMUXD_SCU_PMIC_STANDBY_WAKEUP_MASK_SHIFT (22U)
63770/*! WAKEUP_MASK - wakeup mask
63771 */
63772#define IOMUXD_SCU_PMIC_STANDBY_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_WAKEUP_MASK_MASK)
63773#define IOMUXD_SCU_PMIC_STANDBY_lp_config_MASK (0x1800000U)
63774#define IOMUXD_SCU_PMIC_STANDBY_lp_config_SHIFT (23U)
63775/*! lp_config - lower power configuration
63776 * 0b01..EARLY_ISO
63777 * 0b10..LATE_ISO
63778 * 0b11..LATCH
63779 * 0b00..PASS
63780 */
63781#define IOMUXD_SCU_PMIC_STANDBY_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_lp_config_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_lp_config_MASK)
63782#define IOMUXD_SCU_PMIC_STANDBY_sw_config_MASK (0x6000000U)
63783#define IOMUXD_SCU_PMIC_STANDBY_sw_config_SHIFT (25U)
63784/*! sw_config - output and input configuration
63785 * 0b01..OPEN_DRAIN
63786 * 0b10..OPEN_DRAIN_INPUT
63787 * 0b11..INOUT
63788 * 0b00..DEFAULT
63789 */
63790#define IOMUXD_SCU_PMIC_STANDBY_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_sw_config_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_sw_config_MASK)
63791#define IOMUXD_SCU_PMIC_STANDBY_mux_mode_MASK (0x38000000U)
63792#define IOMUXD_SCU_PMIC_STANDBY_mux_mode_SHIFT (27U)
63793/*! mux_mode - mux_mode
63794 * 0b000..SCU.DSC.PMIC_STANDBY
63795 */
63796#define IOMUXD_SCU_PMIC_STANDBY_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_mux_mode_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_mux_mode_MASK)
63797#define IOMUXD_SCU_PMIC_STANDBY_update_pad_ctl_MASK (0x40000000U)
63798#define IOMUXD_SCU_PMIC_STANDBY_update_pad_ctl_SHIFT (30U)
63799/*! update_pad_ctl - update lock for pad control
63800 */
63801#define IOMUXD_SCU_PMIC_STANDBY_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_update_pad_ctl_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_update_pad_ctl_MASK)
63802#define IOMUXD_SCU_PMIC_STANDBY_update_mux_mode_MASK (0x80000000U)
63803#define IOMUXD_SCU_PMIC_STANDBY_update_mux_mode_SHIFT (31U)
63804/*! update_mux_mode - update lock for mux control
63805 */
63806#define IOMUXD_SCU_PMIC_STANDBY_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_PMIC_STANDBY_update_mux_mode_SHIFT)) & IOMUXD_SCU_PMIC_STANDBY_update_mux_mode_MASK)
63807/*! @} */
63808
63809/*! @name SCU_BOOT_MODE0 - SCU_BOOT_MODE0 */
63810/*! @{ */
63811#define IOMUXD_SCU_BOOT_MODE0_DSE_MASK (0x7U)
63812#define IOMUXD_SCU_BOOT_MODE0_DSE_SHIFT (0U)
63813/*! DSE - Drive
63814 * 0b001..Drive select 2mA
63815 * 0b011..Drive select 6mA
63816 * 0b111..High Speed
63817 * 0b110..Drive select 12mA
63818 * 0b010..Drive select 4mA
63819 * 0b100..Drive select 8mA
63820 * 0b000..Drive select 1mA
63821 * 0b101..Drive select 10mA
63822 */
63823#define IOMUXD_SCU_BOOT_MODE0_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_DSE_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_DSE_MASK)
63824#define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_3_4_MASK (0x18U)
63825#define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_3_4_SHIFT (3U)
63826/*! SCU_BOOT_MODE0_reserved_3_4 - reserved
63827 */
63828#define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_3_4_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_3_4_MASK)
63829#define IOMUXD_SCU_BOOT_MODE0_PULL_MASK (0x60U)
63830#define IOMUXD_SCU_BOOT_MODE0_PULL_SHIFT (5U)
63831/*! PULL - Pull Down Pull Up
63832 * 0b00..Bus-Keeper
63833 * 0b10..pull down
63834 * 0b01..pull up
63835 * 0b11..No Pull
63836 */
63837#define IOMUXD_SCU_BOOT_MODE0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_PULL_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_PULL_MASK)
63838#define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_7_18_MASK (0x7FF80U)
63839#define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_7_18_SHIFT (7U)
63840/*! SCU_BOOT_MODE0_reserved_7_18 - reserved
63841 */
63842#define IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_7_18_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_SCU_BOOT_MODE0_reserved_7_18_MASK)
63843#define IOMUXD_SCU_BOOT_MODE0_WAKEUP_CTRL_MASK (0x380000U)
63844#define IOMUXD_SCU_BOOT_MODE0_WAKEUP_CTRL_SHIFT (19U)
63845/*! WAKEUP_CTRL - wakeup control
63846 * 0b000..OFF
63847 * 0b001..RESAMPLE
63848 * 0b100..LOW
63849 * 0b111..HIGH
63850 * 0b110..RISE
63851 * 0b101..FALL
63852 */
63853#define IOMUXD_SCU_BOOT_MODE0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_WAKEUP_CTRL_MASK)
63854#define IOMUXD_SCU_BOOT_MODE0_WAKEUP_MASK_MASK (0x400000U)
63855#define IOMUXD_SCU_BOOT_MODE0_WAKEUP_MASK_SHIFT (22U)
63856/*! WAKEUP_MASK - wakeup mask
63857 */
63858#define IOMUXD_SCU_BOOT_MODE0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_WAKEUP_MASK_MASK)
63859#define IOMUXD_SCU_BOOT_MODE0_lp_config_MASK (0x1800000U)
63860#define IOMUXD_SCU_BOOT_MODE0_lp_config_SHIFT (23U)
63861/*! lp_config - lower power configuration
63862 * 0b01..EARLY_ISO
63863 * 0b10..LATE_ISO
63864 * 0b11..LATCH
63865 * 0b00..PASS
63866 */
63867#define IOMUXD_SCU_BOOT_MODE0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_lp_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_lp_config_MASK)
63868#define IOMUXD_SCU_BOOT_MODE0_sw_config_MASK (0x6000000U)
63869#define IOMUXD_SCU_BOOT_MODE0_sw_config_SHIFT (25U)
63870/*! sw_config - output and input configuration
63871 * 0b01..OPEN_DRAIN
63872 * 0b10..OPEN_DRAIN_INPUT
63873 * 0b11..INOUT
63874 * 0b00..DEFAULT
63875 */
63876#define IOMUXD_SCU_BOOT_MODE0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_sw_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_sw_config_MASK)
63877#define IOMUXD_SCU_BOOT_MODE0_mux_mode_MASK (0x38000000U)
63878#define IOMUXD_SCU_BOOT_MODE0_mux_mode_SHIFT (27U)
63879/*! mux_mode - mux_mode
63880 * 0b000..SCU.DSC.BOOT_MODE0
63881 */
63882#define IOMUXD_SCU_BOOT_MODE0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_mux_mode_MASK)
63883#define IOMUXD_SCU_BOOT_MODE0_update_pad_ctl_MASK (0x40000000U)
63884#define IOMUXD_SCU_BOOT_MODE0_update_pad_ctl_SHIFT (30U)
63885/*! update_pad_ctl - update lock for pad control
63886 */
63887#define IOMUXD_SCU_BOOT_MODE0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_update_pad_ctl_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_update_pad_ctl_MASK)
63888#define IOMUXD_SCU_BOOT_MODE0_update_mux_mode_MASK (0x80000000U)
63889#define IOMUXD_SCU_BOOT_MODE0_update_mux_mode_SHIFT (31U)
63890/*! update_mux_mode - update lock for mux control
63891 */
63892#define IOMUXD_SCU_BOOT_MODE0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE0_update_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE0_update_mux_mode_MASK)
63893/*! @} */
63894
63895/*! @name SCU_BOOT_MODE1 - SCU_BOOT_MODE1 */
63896/*! @{ */
63897#define IOMUXD_SCU_BOOT_MODE1_DSE_MASK (0x7U)
63898#define IOMUXD_SCU_BOOT_MODE1_DSE_SHIFT (0U)
63899/*! DSE - Drive
63900 * 0b001..Drive select 2mA
63901 * 0b011..Drive select 6mA
63902 * 0b111..High Speed
63903 * 0b110..Drive select 12mA
63904 * 0b010..Drive select 4mA
63905 * 0b100..Drive select 8mA
63906 * 0b000..Drive select 1mA
63907 * 0b101..Drive select 10mA
63908 */
63909#define IOMUXD_SCU_BOOT_MODE1_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_DSE_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_DSE_MASK)
63910#define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_3_4_MASK (0x18U)
63911#define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_3_4_SHIFT (3U)
63912/*! SCU_BOOT_MODE1_reserved_3_4 - reserved
63913 */
63914#define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_3_4_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_3_4_MASK)
63915#define IOMUXD_SCU_BOOT_MODE1_PULL_MASK (0x60U)
63916#define IOMUXD_SCU_BOOT_MODE1_PULL_SHIFT (5U)
63917/*! PULL - Pull Down Pull Up
63918 * 0b00..Bus-Keeper
63919 * 0b10..pull down
63920 * 0b01..pull up
63921 * 0b11..No Pull
63922 */
63923#define IOMUXD_SCU_BOOT_MODE1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_PULL_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_PULL_MASK)
63924#define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_7_18_MASK (0x7FF80U)
63925#define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_7_18_SHIFT (7U)
63926/*! SCU_BOOT_MODE1_reserved_7_18 - reserved
63927 */
63928#define IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_7_18_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_SCU_BOOT_MODE1_reserved_7_18_MASK)
63929#define IOMUXD_SCU_BOOT_MODE1_WAKEUP_CTRL_MASK (0x380000U)
63930#define IOMUXD_SCU_BOOT_MODE1_WAKEUP_CTRL_SHIFT (19U)
63931/*! WAKEUP_CTRL - wakeup control
63932 * 0b000..OFF
63933 * 0b001..RESAMPLE
63934 * 0b100..LOW
63935 * 0b111..HIGH
63936 * 0b110..RISE
63937 * 0b101..FALL
63938 */
63939#define IOMUXD_SCU_BOOT_MODE1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_WAKEUP_CTRL_MASK)
63940#define IOMUXD_SCU_BOOT_MODE1_WAKEUP_MASK_MASK (0x400000U)
63941#define IOMUXD_SCU_BOOT_MODE1_WAKEUP_MASK_SHIFT (22U)
63942/*! WAKEUP_MASK - wakeup mask
63943 */
63944#define IOMUXD_SCU_BOOT_MODE1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_WAKEUP_MASK_MASK)
63945#define IOMUXD_SCU_BOOT_MODE1_lp_config_MASK (0x1800000U)
63946#define IOMUXD_SCU_BOOT_MODE1_lp_config_SHIFT (23U)
63947/*! lp_config - lower power configuration
63948 * 0b01..EARLY_ISO
63949 * 0b10..LATE_ISO
63950 * 0b11..LATCH
63951 * 0b00..PASS
63952 */
63953#define IOMUXD_SCU_BOOT_MODE1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_lp_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_lp_config_MASK)
63954#define IOMUXD_SCU_BOOT_MODE1_sw_config_MASK (0x6000000U)
63955#define IOMUXD_SCU_BOOT_MODE1_sw_config_SHIFT (25U)
63956/*! sw_config - output and input configuration
63957 * 0b01..OPEN_DRAIN
63958 * 0b10..OPEN_DRAIN_INPUT
63959 * 0b11..INOUT
63960 * 0b00..DEFAULT
63961 */
63962#define IOMUXD_SCU_BOOT_MODE1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_sw_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_sw_config_MASK)
63963#define IOMUXD_SCU_BOOT_MODE1_mux_mode_MASK (0x38000000U)
63964#define IOMUXD_SCU_BOOT_MODE1_mux_mode_SHIFT (27U)
63965/*! mux_mode - mux_mode
63966 * 0b000..SCU.DSC.BOOT_MODE1
63967 */
63968#define IOMUXD_SCU_BOOT_MODE1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_mux_mode_MASK)
63969#define IOMUXD_SCU_BOOT_MODE1_update_pad_ctl_MASK (0x40000000U)
63970#define IOMUXD_SCU_BOOT_MODE1_update_pad_ctl_SHIFT (30U)
63971/*! update_pad_ctl - update lock for pad control
63972 */
63973#define IOMUXD_SCU_BOOT_MODE1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_update_pad_ctl_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_update_pad_ctl_MASK)
63974#define IOMUXD_SCU_BOOT_MODE1_update_mux_mode_MASK (0x80000000U)
63975#define IOMUXD_SCU_BOOT_MODE1_update_mux_mode_SHIFT (31U)
63976/*! update_mux_mode - update lock for mux control
63977 */
63978#define IOMUXD_SCU_BOOT_MODE1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE1_update_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE1_update_mux_mode_MASK)
63979/*! @} */
63980
63981/*! @name SCU_BOOT_MODE2 - SCU_BOOT_MODE2 */
63982/*! @{ */
63983#define IOMUXD_SCU_BOOT_MODE2_DSE_MASK (0x7U)
63984#define IOMUXD_SCU_BOOT_MODE2_DSE_SHIFT (0U)
63985/*! DSE - Drive
63986 * 0b001..Drive select 2mA
63987 * 0b011..Drive select 6mA
63988 * 0b111..High Speed
63989 * 0b110..Drive select 12mA
63990 * 0b010..Drive select 4mA
63991 * 0b100..Drive select 8mA
63992 * 0b000..Drive select 1mA
63993 * 0b101..Drive select 10mA
63994 */
63995#define IOMUXD_SCU_BOOT_MODE2_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_DSE_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_DSE_MASK)
63996#define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_3_4_MASK (0x18U)
63997#define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_3_4_SHIFT (3U)
63998/*! SCU_BOOT_MODE2_reserved_3_4 - reserved
63999 */
64000#define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_3_4_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_3_4_MASK)
64001#define IOMUXD_SCU_BOOT_MODE2_PULL_MASK (0x60U)
64002#define IOMUXD_SCU_BOOT_MODE2_PULL_SHIFT (5U)
64003/*! PULL - Pull Down Pull Up
64004 * 0b00..Bus-Keeper
64005 * 0b10..pull down
64006 * 0b01..pull up
64007 * 0b11..No Pull
64008 */
64009#define IOMUXD_SCU_BOOT_MODE2_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_PULL_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_PULL_MASK)
64010#define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_7_18_MASK (0x7FF80U)
64011#define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_7_18_SHIFT (7U)
64012/*! SCU_BOOT_MODE2_reserved_7_18 - reserved
64013 */
64014#define IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_7_18_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_SCU_BOOT_MODE2_reserved_7_18_MASK)
64015#define IOMUXD_SCU_BOOT_MODE2_WAKEUP_CTRL_MASK (0x380000U)
64016#define IOMUXD_SCU_BOOT_MODE2_WAKEUP_CTRL_SHIFT (19U)
64017/*! WAKEUP_CTRL - wakeup control
64018 * 0b000..OFF
64019 * 0b001..RESAMPLE
64020 * 0b100..LOW
64021 * 0b111..HIGH
64022 * 0b110..RISE
64023 * 0b101..FALL
64024 */
64025#define IOMUXD_SCU_BOOT_MODE2_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_WAKEUP_CTRL_MASK)
64026#define IOMUXD_SCU_BOOT_MODE2_WAKEUP_MASK_MASK (0x400000U)
64027#define IOMUXD_SCU_BOOT_MODE2_WAKEUP_MASK_SHIFT (22U)
64028/*! WAKEUP_MASK - wakeup mask
64029 */
64030#define IOMUXD_SCU_BOOT_MODE2_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_WAKEUP_MASK_MASK)
64031#define IOMUXD_SCU_BOOT_MODE2_lp_config_MASK (0x1800000U)
64032#define IOMUXD_SCU_BOOT_MODE2_lp_config_SHIFT (23U)
64033/*! lp_config - lower power configuration
64034 * 0b01..EARLY_ISO
64035 * 0b10..LATE_ISO
64036 * 0b11..LATCH
64037 * 0b00..PASS
64038 */
64039#define IOMUXD_SCU_BOOT_MODE2_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_lp_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_lp_config_MASK)
64040#define IOMUXD_SCU_BOOT_MODE2_sw_config_MASK (0x6000000U)
64041#define IOMUXD_SCU_BOOT_MODE2_sw_config_SHIFT (25U)
64042/*! sw_config - output and input configuration
64043 * 0b01..OPEN_DRAIN
64044 * 0b10..OPEN_DRAIN_INPUT
64045 * 0b11..INOUT
64046 * 0b00..DEFAULT
64047 */
64048#define IOMUXD_SCU_BOOT_MODE2_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_sw_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_sw_config_MASK)
64049#define IOMUXD_SCU_BOOT_MODE2_mux_mode_MASK (0x38000000U)
64050#define IOMUXD_SCU_BOOT_MODE2_mux_mode_SHIFT (27U)
64051/*! mux_mode - mux_mode
64052 * 0b000..SCU.DSC.BOOT_MODE2
64053 * 0b001..SCU.PMIC_I2C.SDA
64054 */
64055#define IOMUXD_SCU_BOOT_MODE2_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_mux_mode_MASK)
64056#define IOMUXD_SCU_BOOT_MODE2_update_pad_ctl_MASK (0x40000000U)
64057#define IOMUXD_SCU_BOOT_MODE2_update_pad_ctl_SHIFT (30U)
64058/*! update_pad_ctl - update lock for pad control
64059 */
64060#define IOMUXD_SCU_BOOT_MODE2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_update_pad_ctl_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_update_pad_ctl_MASK)
64061#define IOMUXD_SCU_BOOT_MODE2_update_mux_mode_MASK (0x80000000U)
64062#define IOMUXD_SCU_BOOT_MODE2_update_mux_mode_SHIFT (31U)
64063/*! update_mux_mode - update lock for mux control
64064 */
64065#define IOMUXD_SCU_BOOT_MODE2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE2_update_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE2_update_mux_mode_MASK)
64066/*! @} */
64067
64068/*! @name SCU_BOOT_MODE3 - SCU_BOOT_MODE3 */
64069/*! @{ */
64070#define IOMUXD_SCU_BOOT_MODE3_DSE_MASK (0x7U)
64071#define IOMUXD_SCU_BOOT_MODE3_DSE_SHIFT (0U)
64072/*! DSE - Drive
64073 * 0b001..Drive select 2mA
64074 * 0b011..Drive select 6mA
64075 * 0b111..High Speed
64076 * 0b110..Drive select 12mA
64077 * 0b010..Drive select 4mA
64078 * 0b100..Drive select 8mA
64079 * 0b000..Drive select 1mA
64080 * 0b101..Drive select 10mA
64081 */
64082#define IOMUXD_SCU_BOOT_MODE3_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_DSE_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_DSE_MASK)
64083#define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_3_4_MASK (0x18U)
64084#define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_3_4_SHIFT (3U)
64085/*! SCU_BOOT_MODE3_reserved_3_4 - reserved
64086 */
64087#define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_3_4_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_3_4_MASK)
64088#define IOMUXD_SCU_BOOT_MODE3_PULL_MASK (0x60U)
64089#define IOMUXD_SCU_BOOT_MODE3_PULL_SHIFT (5U)
64090/*! PULL - Pull Down Pull Up
64091 * 0b00..Bus-Keeper
64092 * 0b10..pull down
64093 * 0b01..pull up
64094 * 0b11..No Pull
64095 */
64096#define IOMUXD_SCU_BOOT_MODE3_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_PULL_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_PULL_MASK)
64097#define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_7_18_MASK (0x7FF80U)
64098#define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_7_18_SHIFT (7U)
64099/*! SCU_BOOT_MODE3_reserved_7_18 - reserved
64100 */
64101#define IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_7_18_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_SCU_BOOT_MODE3_reserved_7_18_MASK)
64102#define IOMUXD_SCU_BOOT_MODE3_WAKEUP_CTRL_MASK (0x380000U)
64103#define IOMUXD_SCU_BOOT_MODE3_WAKEUP_CTRL_SHIFT (19U)
64104/*! WAKEUP_CTRL - wakeup control
64105 * 0b000..OFF
64106 * 0b001..RESAMPLE
64107 * 0b100..LOW
64108 * 0b111..HIGH
64109 * 0b110..RISE
64110 * 0b101..FALL
64111 */
64112#define IOMUXD_SCU_BOOT_MODE3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_WAKEUP_CTRL_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_WAKEUP_CTRL_MASK)
64113#define IOMUXD_SCU_BOOT_MODE3_WAKEUP_MASK_MASK (0x400000U)
64114#define IOMUXD_SCU_BOOT_MODE3_WAKEUP_MASK_SHIFT (22U)
64115/*! WAKEUP_MASK - wakeup mask
64116 */
64117#define IOMUXD_SCU_BOOT_MODE3_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_WAKEUP_MASK_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_WAKEUP_MASK_MASK)
64118#define IOMUXD_SCU_BOOT_MODE3_lp_config_MASK (0x1800000U)
64119#define IOMUXD_SCU_BOOT_MODE3_lp_config_SHIFT (23U)
64120/*! lp_config - lower power configuration
64121 * 0b01..EARLY_ISO
64122 * 0b10..LATE_ISO
64123 * 0b11..LATCH
64124 * 0b00..PASS
64125 */
64126#define IOMUXD_SCU_BOOT_MODE3_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_lp_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_lp_config_MASK)
64127#define IOMUXD_SCU_BOOT_MODE3_sw_config_MASK (0x6000000U)
64128#define IOMUXD_SCU_BOOT_MODE3_sw_config_SHIFT (25U)
64129/*! sw_config - output and input configuration
64130 * 0b01..OPEN_DRAIN
64131 * 0b10..OPEN_DRAIN_INPUT
64132 * 0b11..INOUT
64133 * 0b00..DEFAULT
64134 */
64135#define IOMUXD_SCU_BOOT_MODE3_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_sw_config_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_sw_config_MASK)
64136#define IOMUXD_SCU_BOOT_MODE3_mux_mode_MASK (0x38000000U)
64137#define IOMUXD_SCU_BOOT_MODE3_mux_mode_SHIFT (27U)
64138/*! mux_mode - mux_mode
64139 * 0b000..SCU.DSC.BOOT_MODE3
64140 * 0b001..SCU.PMIC_I2C.SCL
64141 * 0b011..SCU.DSC.RTC_CLOCK_OUTPUT_32K
64142 */
64143#define IOMUXD_SCU_BOOT_MODE3_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_mux_mode_MASK)
64144#define IOMUXD_SCU_BOOT_MODE3_update_pad_ctl_MASK (0x40000000U)
64145#define IOMUXD_SCU_BOOT_MODE3_update_pad_ctl_SHIFT (30U)
64146/*! update_pad_ctl - update lock for pad control
64147 */
64148#define IOMUXD_SCU_BOOT_MODE3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_update_pad_ctl_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_update_pad_ctl_MASK)
64149#define IOMUXD_SCU_BOOT_MODE3_update_mux_mode_MASK (0x80000000U)
64150#define IOMUXD_SCU_BOOT_MODE3_update_mux_mode_SHIFT (31U)
64151/*! update_mux_mode - update lock for mux control
64152 */
64153#define IOMUXD_SCU_BOOT_MODE3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_SCU_BOOT_MODE3_update_mux_mode_SHIFT)) & IOMUXD_SCU_BOOT_MODE3_update_mux_mode_MASK)
64154/*! @} */
64155
64156/*! @name CSI_DIG_D00 - CSI_DIG_D00 */
64157/*! @{ */
64158#define IOMUXD_CSI_DIG_D00_PDRV_MASK (0x1U)
64159#define IOMUXD_CSI_DIG_D00_PDRV_SHIFT (0U)
64160/*! PDRV - Drive
64161 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
64162 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
64163 */
64164#define IOMUXD_CSI_DIG_D00_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D00_PDRV_MASK)
64165#define IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_1_4_MASK (0x1EU)
64166#define IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_1_4_SHIFT (1U)
64167/*! CSI_DIG_D00_reserved_1_4 - reserved
64168 */
64169#define IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_1_4_MASK)
64170#define IOMUXD_CSI_DIG_D00_PULL_MASK (0x60U)
64171#define IOMUXD_CSI_DIG_D00_PULL_SHIFT (5U)
64172/*! PULL - Pull Down Pull Up
64173 * 0b10..pull down
64174 * 0b01..pull up
64175 * 0b00..Prohibited
64176 * 0b11..pull disabled
64177 */
64178#define IOMUXD_CSI_DIG_D00_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_PULL_SHIFT)) & IOMUXD_CSI_DIG_D00_PULL_MASK)
64179#define IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_7_18_MASK (0x7FF80U)
64180#define IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_7_18_SHIFT (7U)
64181/*! CSI_DIG_D00_reserved_7_18 - reserved
64182 */
64183#define IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D00_CSI_DIG_D00_reserved_7_18_MASK)
64184#define IOMUXD_CSI_DIG_D00_WAKEUP_CTRL_MASK (0x380000U)
64185#define IOMUXD_CSI_DIG_D00_WAKEUP_CTRL_SHIFT (19U)
64186/*! WAKEUP_CTRL - wakeup control
64187 * 0b000..OFF
64188 * 0b001..RESAMPLE
64189 * 0b100..LOW
64190 * 0b111..HIGH
64191 * 0b110..RISE
64192 * 0b101..FALL
64193 */
64194#define IOMUXD_CSI_DIG_D00_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D00_WAKEUP_CTRL_MASK)
64195#define IOMUXD_CSI_DIG_D00_WAKEUP_MASK_MASK (0x400000U)
64196#define IOMUXD_CSI_DIG_D00_WAKEUP_MASK_SHIFT (22U)
64197/*! WAKEUP_MASK - wakeup mask
64198 */
64199#define IOMUXD_CSI_DIG_D00_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D00_WAKEUP_MASK_MASK)
64200#define IOMUXD_CSI_DIG_D00_lp_config_MASK (0x1800000U)
64201#define IOMUXD_CSI_DIG_D00_lp_config_SHIFT (23U)
64202/*! lp_config - lower power configuration
64203 * 0b01..EARLY_ISO
64204 * 0b10..LATE_ISO
64205 * 0b11..LATCH
64206 * 0b00..PASS
64207 */
64208#define IOMUXD_CSI_DIG_D00_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D00_lp_config_MASK)
64209#define IOMUXD_CSI_DIG_D00_sw_config_MASK (0x6000000U)
64210#define IOMUXD_CSI_DIG_D00_sw_config_SHIFT (25U)
64211/*! sw_config - output and input configuration
64212 * 0b01..OPEN_DRAIN
64213 * 0b10..OPEN_DRAIN_INPUT
64214 * 0b11..INOUT
64215 * 0b00..DEFAULT
64216 */
64217#define IOMUXD_CSI_DIG_D00_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D00_sw_config_MASK)
64218#define IOMUXD_CSI_DIG_D00_mux_mode_MASK (0x38000000U)
64219#define IOMUXD_CSI_DIG_D00_mux_mode_SHIFT (27U)
64220/*! mux_mode - mux_mode
64221 * 0b000..CI_PI.D02
64222 * 0b010..ADMA.SAI0.RXC
64223 */
64224#define IOMUXD_CSI_DIG_D00_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D00_mux_mode_MASK)
64225#define IOMUXD_CSI_DIG_D00_update_pad_ctl_MASK (0x40000000U)
64226#define IOMUXD_CSI_DIG_D00_update_pad_ctl_SHIFT (30U)
64227/*! update_pad_ctl - update lock for pad control
64228 */
64229#define IOMUXD_CSI_DIG_D00_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D00_update_pad_ctl_MASK)
64230#define IOMUXD_CSI_DIG_D00_update_mux_mode_MASK (0x80000000U)
64231#define IOMUXD_CSI_DIG_D00_update_mux_mode_SHIFT (31U)
64232/*! update_mux_mode - update lock for mux control
64233 */
64234#define IOMUXD_CSI_DIG_D00_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D00_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D00_update_mux_mode_MASK)
64235/*! @} */
64236
64237/*! @name CSI_DIG_D01 - CSI_DIG_D01 */
64238/*! @{ */
64239#define IOMUXD_CSI_DIG_D01_PDRV_MASK (0x1U)
64240#define IOMUXD_CSI_DIG_D01_PDRV_SHIFT (0U)
64241/*! PDRV - Drive
64242 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
64243 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
64244 */
64245#define IOMUXD_CSI_DIG_D01_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D01_PDRV_MASK)
64246#define IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_1_4_MASK (0x1EU)
64247#define IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_1_4_SHIFT (1U)
64248/*! CSI_DIG_D01_reserved_1_4 - reserved
64249 */
64250#define IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_1_4_MASK)
64251#define IOMUXD_CSI_DIG_D01_PULL_MASK (0x60U)
64252#define IOMUXD_CSI_DIG_D01_PULL_SHIFT (5U)
64253/*! PULL - Pull Down Pull Up
64254 * 0b10..pull down
64255 * 0b01..pull up
64256 * 0b00..Prohibited
64257 * 0b11..pull disabled
64258 */
64259#define IOMUXD_CSI_DIG_D01_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_PULL_SHIFT)) & IOMUXD_CSI_DIG_D01_PULL_MASK)
64260#define IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_7_18_MASK (0x7FF80U)
64261#define IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_7_18_SHIFT (7U)
64262/*! CSI_DIG_D01_reserved_7_18 - reserved
64263 */
64264#define IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D01_CSI_DIG_D01_reserved_7_18_MASK)
64265#define IOMUXD_CSI_DIG_D01_WAKEUP_CTRL_MASK (0x380000U)
64266#define IOMUXD_CSI_DIG_D01_WAKEUP_CTRL_SHIFT (19U)
64267/*! WAKEUP_CTRL - wakeup control
64268 * 0b000..OFF
64269 * 0b001..RESAMPLE
64270 * 0b100..LOW
64271 * 0b111..HIGH
64272 * 0b110..RISE
64273 * 0b101..FALL
64274 */
64275#define IOMUXD_CSI_DIG_D01_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D01_WAKEUP_CTRL_MASK)
64276#define IOMUXD_CSI_DIG_D01_WAKEUP_MASK_MASK (0x400000U)
64277#define IOMUXD_CSI_DIG_D01_WAKEUP_MASK_SHIFT (22U)
64278/*! WAKEUP_MASK - wakeup mask
64279 */
64280#define IOMUXD_CSI_DIG_D01_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D01_WAKEUP_MASK_MASK)
64281#define IOMUXD_CSI_DIG_D01_lp_config_MASK (0x1800000U)
64282#define IOMUXD_CSI_DIG_D01_lp_config_SHIFT (23U)
64283/*! lp_config - lower power configuration
64284 * 0b01..EARLY_ISO
64285 * 0b10..LATE_ISO
64286 * 0b11..LATCH
64287 * 0b00..PASS
64288 */
64289#define IOMUXD_CSI_DIG_D01_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D01_lp_config_MASK)
64290#define IOMUXD_CSI_DIG_D01_sw_config_MASK (0x6000000U)
64291#define IOMUXD_CSI_DIG_D01_sw_config_SHIFT (25U)
64292/*! sw_config - output and input configuration
64293 * 0b01..OPEN_DRAIN
64294 * 0b10..OPEN_DRAIN_INPUT
64295 * 0b11..INOUT
64296 * 0b00..DEFAULT
64297 */
64298#define IOMUXD_CSI_DIG_D01_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D01_sw_config_MASK)
64299#define IOMUXD_CSI_DIG_D01_mux_mode_MASK (0x38000000U)
64300#define IOMUXD_CSI_DIG_D01_mux_mode_SHIFT (27U)
64301/*! mux_mode - mux_mode
64302 * 0b000..CI_PI.D03
64303 * 0b010..ADMA.SAI0.RXD
64304 */
64305#define IOMUXD_CSI_DIG_D01_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D01_mux_mode_MASK)
64306#define IOMUXD_CSI_DIG_D01_update_pad_ctl_MASK (0x40000000U)
64307#define IOMUXD_CSI_DIG_D01_update_pad_ctl_SHIFT (30U)
64308/*! update_pad_ctl - update lock for pad control
64309 */
64310#define IOMUXD_CSI_DIG_D01_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D01_update_pad_ctl_MASK)
64311#define IOMUXD_CSI_DIG_D01_update_mux_mode_MASK (0x80000000U)
64312#define IOMUXD_CSI_DIG_D01_update_mux_mode_SHIFT (31U)
64313/*! update_mux_mode - update lock for mux control
64314 */
64315#define IOMUXD_CSI_DIG_D01_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D01_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D01_update_mux_mode_MASK)
64316/*! @} */
64317
64318/*! @name CSI_DIG_D02 - CSI_DIG_D02 */
64319/*! @{ */
64320#define IOMUXD_CSI_DIG_D02_PDRV_MASK (0x1U)
64321#define IOMUXD_CSI_DIG_D02_PDRV_SHIFT (0U)
64322/*! PDRV - Drive
64323 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
64324 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
64325 */
64326#define IOMUXD_CSI_DIG_D02_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D02_PDRV_MASK)
64327#define IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_1_4_MASK (0x1EU)
64328#define IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_1_4_SHIFT (1U)
64329/*! CSI_DIG_D02_reserved_1_4 - reserved
64330 */
64331#define IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_1_4_MASK)
64332#define IOMUXD_CSI_DIG_D02_PULL_MASK (0x60U)
64333#define IOMUXD_CSI_DIG_D02_PULL_SHIFT (5U)
64334/*! PULL - Pull Down Pull Up
64335 * 0b10..pull down
64336 * 0b01..pull up
64337 * 0b00..Prohibited
64338 * 0b11..pull disabled
64339 */
64340#define IOMUXD_CSI_DIG_D02_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_PULL_SHIFT)) & IOMUXD_CSI_DIG_D02_PULL_MASK)
64341#define IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_7_18_MASK (0x7FF80U)
64342#define IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_7_18_SHIFT (7U)
64343/*! CSI_DIG_D02_reserved_7_18 - reserved
64344 */
64345#define IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D02_CSI_DIG_D02_reserved_7_18_MASK)
64346#define IOMUXD_CSI_DIG_D02_WAKEUP_CTRL_MASK (0x380000U)
64347#define IOMUXD_CSI_DIG_D02_WAKEUP_CTRL_SHIFT (19U)
64348/*! WAKEUP_CTRL - wakeup control
64349 * 0b000..OFF
64350 * 0b001..RESAMPLE
64351 * 0b100..LOW
64352 * 0b111..HIGH
64353 * 0b110..RISE
64354 * 0b101..FALL
64355 */
64356#define IOMUXD_CSI_DIG_D02_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D02_WAKEUP_CTRL_MASK)
64357#define IOMUXD_CSI_DIG_D02_WAKEUP_MASK_MASK (0x400000U)
64358#define IOMUXD_CSI_DIG_D02_WAKEUP_MASK_SHIFT (22U)
64359/*! WAKEUP_MASK - wakeup mask
64360 */
64361#define IOMUXD_CSI_DIG_D02_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D02_WAKEUP_MASK_MASK)
64362#define IOMUXD_CSI_DIG_D02_lp_config_MASK (0x1800000U)
64363#define IOMUXD_CSI_DIG_D02_lp_config_SHIFT (23U)
64364/*! lp_config - lower power configuration
64365 * 0b01..EARLY_ISO
64366 * 0b10..LATE_ISO
64367 * 0b11..LATCH
64368 * 0b00..PASS
64369 */
64370#define IOMUXD_CSI_DIG_D02_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D02_lp_config_MASK)
64371#define IOMUXD_CSI_DIG_D02_sw_config_MASK (0x6000000U)
64372#define IOMUXD_CSI_DIG_D02_sw_config_SHIFT (25U)
64373/*! sw_config - output and input configuration
64374 * 0b01..OPEN_DRAIN
64375 * 0b10..OPEN_DRAIN_INPUT
64376 * 0b11..INOUT
64377 * 0b00..DEFAULT
64378 */
64379#define IOMUXD_CSI_DIG_D02_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D02_sw_config_MASK)
64380#define IOMUXD_CSI_DIG_D02_mux_mode_MASK (0x38000000U)
64381#define IOMUXD_CSI_DIG_D02_mux_mode_SHIFT (27U)
64382/*! mux_mode - mux_mode
64383 * 0b000..CI_PI.D04
64384 * 0b010..ADMA.SAI0.RXFS
64385 */
64386#define IOMUXD_CSI_DIG_D02_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D02_mux_mode_MASK)
64387#define IOMUXD_CSI_DIG_D02_update_pad_ctl_MASK (0x40000000U)
64388#define IOMUXD_CSI_DIG_D02_update_pad_ctl_SHIFT (30U)
64389/*! update_pad_ctl - update lock for pad control
64390 */
64391#define IOMUXD_CSI_DIG_D02_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D02_update_pad_ctl_MASK)
64392#define IOMUXD_CSI_DIG_D02_update_mux_mode_MASK (0x80000000U)
64393#define IOMUXD_CSI_DIG_D02_update_mux_mode_SHIFT (31U)
64394/*! update_mux_mode - update lock for mux control
64395 */
64396#define IOMUXD_CSI_DIG_D02_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D02_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D02_update_mux_mode_MASK)
64397/*! @} */
64398
64399/*! @name CSI_DIG_D03 - CSI_DIG_D03 */
64400/*! @{ */
64401#define IOMUXD_CSI_DIG_D03_PDRV_MASK (0x1U)
64402#define IOMUXD_CSI_DIG_D03_PDRV_SHIFT (0U)
64403/*! PDRV - Drive
64404 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
64405 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
64406 */
64407#define IOMUXD_CSI_DIG_D03_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D03_PDRV_MASK)
64408#define IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_1_4_MASK (0x1EU)
64409#define IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_1_4_SHIFT (1U)
64410/*! CSI_DIG_D03_reserved_1_4 - reserved
64411 */
64412#define IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_1_4_MASK)
64413#define IOMUXD_CSI_DIG_D03_PULL_MASK (0x60U)
64414#define IOMUXD_CSI_DIG_D03_PULL_SHIFT (5U)
64415/*! PULL - Pull Down Pull Up
64416 * 0b10..pull down
64417 * 0b01..pull up
64418 * 0b00..Prohibited
64419 * 0b11..pull disabled
64420 */
64421#define IOMUXD_CSI_DIG_D03_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_PULL_SHIFT)) & IOMUXD_CSI_DIG_D03_PULL_MASK)
64422#define IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_7_18_MASK (0x7FF80U)
64423#define IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_7_18_SHIFT (7U)
64424/*! CSI_DIG_D03_reserved_7_18 - reserved
64425 */
64426#define IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D03_CSI_DIG_D03_reserved_7_18_MASK)
64427#define IOMUXD_CSI_DIG_D03_WAKEUP_CTRL_MASK (0x380000U)
64428#define IOMUXD_CSI_DIG_D03_WAKEUP_CTRL_SHIFT (19U)
64429/*! WAKEUP_CTRL - wakeup control
64430 * 0b000..OFF
64431 * 0b001..RESAMPLE
64432 * 0b100..LOW
64433 * 0b111..HIGH
64434 * 0b110..RISE
64435 * 0b101..FALL
64436 */
64437#define IOMUXD_CSI_DIG_D03_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D03_WAKEUP_CTRL_MASK)
64438#define IOMUXD_CSI_DIG_D03_WAKEUP_MASK_MASK (0x400000U)
64439#define IOMUXD_CSI_DIG_D03_WAKEUP_MASK_SHIFT (22U)
64440/*! WAKEUP_MASK - wakeup mask
64441 */
64442#define IOMUXD_CSI_DIG_D03_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D03_WAKEUP_MASK_MASK)
64443#define IOMUXD_CSI_DIG_D03_lp_config_MASK (0x1800000U)
64444#define IOMUXD_CSI_DIG_D03_lp_config_SHIFT (23U)
64445/*! lp_config - lower power configuration
64446 * 0b01..EARLY_ISO
64447 * 0b10..LATE_ISO
64448 * 0b11..LATCH
64449 * 0b00..PASS
64450 */
64451#define IOMUXD_CSI_DIG_D03_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D03_lp_config_MASK)
64452#define IOMUXD_CSI_DIG_D03_sw_config_MASK (0x6000000U)
64453#define IOMUXD_CSI_DIG_D03_sw_config_SHIFT (25U)
64454/*! sw_config - output and input configuration
64455 * 0b01..OPEN_DRAIN
64456 * 0b10..OPEN_DRAIN_INPUT
64457 * 0b11..INOUT
64458 * 0b00..DEFAULT
64459 */
64460#define IOMUXD_CSI_DIG_D03_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D03_sw_config_MASK)
64461#define IOMUXD_CSI_DIG_D03_mux_mode_MASK (0x38000000U)
64462#define IOMUXD_CSI_DIG_D03_mux_mode_SHIFT (27U)
64463/*! mux_mode - mux_mode
64464 * 0b000..CI_PI.D05
64465 * 0b010..ADMA.SAI2.RXC
64466 */
64467#define IOMUXD_CSI_DIG_D03_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D03_mux_mode_MASK)
64468#define IOMUXD_CSI_DIG_D03_update_pad_ctl_MASK (0x40000000U)
64469#define IOMUXD_CSI_DIG_D03_update_pad_ctl_SHIFT (30U)
64470/*! update_pad_ctl - update lock for pad control
64471 */
64472#define IOMUXD_CSI_DIG_D03_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D03_update_pad_ctl_MASK)
64473#define IOMUXD_CSI_DIG_D03_update_mux_mode_MASK (0x80000000U)
64474#define IOMUXD_CSI_DIG_D03_update_mux_mode_SHIFT (31U)
64475/*! update_mux_mode - update lock for mux control
64476 */
64477#define IOMUXD_CSI_DIG_D03_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D03_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D03_update_mux_mode_MASK)
64478/*! @} */
64479
64480/*! @name CSI_DIG_D04 - CSI_DIG_D04 */
64481/*! @{ */
64482#define IOMUXD_CSI_DIG_D04_PDRV_MASK (0x1U)
64483#define IOMUXD_CSI_DIG_D04_PDRV_SHIFT (0U)
64484/*! PDRV - Drive
64485 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
64486 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
64487 */
64488#define IOMUXD_CSI_DIG_D04_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D04_PDRV_MASK)
64489#define IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_1_4_MASK (0x1EU)
64490#define IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_1_4_SHIFT (1U)
64491/*! CSI_DIG_D04_reserved_1_4 - reserved
64492 */
64493#define IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_1_4_MASK)
64494#define IOMUXD_CSI_DIG_D04_PULL_MASK (0x60U)
64495#define IOMUXD_CSI_DIG_D04_PULL_SHIFT (5U)
64496/*! PULL - Pull Down Pull Up
64497 * 0b10..pull down
64498 * 0b01..pull up
64499 * 0b00..Prohibited
64500 * 0b11..pull disabled
64501 */
64502#define IOMUXD_CSI_DIG_D04_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_PULL_SHIFT)) & IOMUXD_CSI_DIG_D04_PULL_MASK)
64503#define IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_7_18_MASK (0x7FF80U)
64504#define IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_7_18_SHIFT (7U)
64505/*! CSI_DIG_D04_reserved_7_18 - reserved
64506 */
64507#define IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D04_CSI_DIG_D04_reserved_7_18_MASK)
64508#define IOMUXD_CSI_DIG_D04_WAKEUP_CTRL_MASK (0x380000U)
64509#define IOMUXD_CSI_DIG_D04_WAKEUP_CTRL_SHIFT (19U)
64510/*! WAKEUP_CTRL - wakeup control
64511 * 0b000..OFF
64512 * 0b001..RESAMPLE
64513 * 0b100..LOW
64514 * 0b111..HIGH
64515 * 0b110..RISE
64516 * 0b101..FALL
64517 */
64518#define IOMUXD_CSI_DIG_D04_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D04_WAKEUP_CTRL_MASK)
64519#define IOMUXD_CSI_DIG_D04_WAKEUP_MASK_MASK (0x400000U)
64520#define IOMUXD_CSI_DIG_D04_WAKEUP_MASK_SHIFT (22U)
64521/*! WAKEUP_MASK - wakeup mask
64522 */
64523#define IOMUXD_CSI_DIG_D04_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D04_WAKEUP_MASK_MASK)
64524#define IOMUXD_CSI_DIG_D04_lp_config_MASK (0x1800000U)
64525#define IOMUXD_CSI_DIG_D04_lp_config_SHIFT (23U)
64526/*! lp_config - lower power configuration
64527 * 0b01..EARLY_ISO
64528 * 0b10..LATE_ISO
64529 * 0b11..LATCH
64530 * 0b00..PASS
64531 */
64532#define IOMUXD_CSI_DIG_D04_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D04_lp_config_MASK)
64533#define IOMUXD_CSI_DIG_D04_sw_config_MASK (0x6000000U)
64534#define IOMUXD_CSI_DIG_D04_sw_config_SHIFT (25U)
64535/*! sw_config - output and input configuration
64536 * 0b01..OPEN_DRAIN
64537 * 0b10..OPEN_DRAIN_INPUT
64538 * 0b11..INOUT
64539 * 0b00..DEFAULT
64540 */
64541#define IOMUXD_CSI_DIG_D04_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D04_sw_config_MASK)
64542#define IOMUXD_CSI_DIG_D04_mux_mode_MASK (0x38000000U)
64543#define IOMUXD_CSI_DIG_D04_mux_mode_SHIFT (27U)
64544/*! mux_mode - mux_mode
64545 * 0b000..CI_PI.D06
64546 * 0b010..ADMA.SAI2.RXD
64547 */
64548#define IOMUXD_CSI_DIG_D04_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D04_mux_mode_MASK)
64549#define IOMUXD_CSI_DIG_D04_update_pad_ctl_MASK (0x40000000U)
64550#define IOMUXD_CSI_DIG_D04_update_pad_ctl_SHIFT (30U)
64551/*! update_pad_ctl - update lock for pad control
64552 */
64553#define IOMUXD_CSI_DIG_D04_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D04_update_pad_ctl_MASK)
64554#define IOMUXD_CSI_DIG_D04_update_mux_mode_MASK (0x80000000U)
64555#define IOMUXD_CSI_DIG_D04_update_mux_mode_SHIFT (31U)
64556/*! update_mux_mode - update lock for mux control
64557 */
64558#define IOMUXD_CSI_DIG_D04_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D04_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D04_update_mux_mode_MASK)
64559/*! @} */
64560
64561/*! @name CSI_DIG_D05 - CSI_DIG_D05 */
64562/*! @{ */
64563#define IOMUXD_CSI_DIG_D05_PDRV_MASK (0x1U)
64564#define IOMUXD_CSI_DIG_D05_PDRV_SHIFT (0U)
64565/*! PDRV - Drive
64566 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
64567 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
64568 */
64569#define IOMUXD_CSI_DIG_D05_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D05_PDRV_MASK)
64570#define IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_1_4_MASK (0x1EU)
64571#define IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_1_4_SHIFT (1U)
64572/*! CSI_DIG_D05_reserved_1_4 - reserved
64573 */
64574#define IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_1_4_MASK)
64575#define IOMUXD_CSI_DIG_D05_PULL_MASK (0x60U)
64576#define IOMUXD_CSI_DIG_D05_PULL_SHIFT (5U)
64577/*! PULL - Pull Down Pull Up
64578 * 0b10..pull down
64579 * 0b01..pull up
64580 * 0b00..Prohibited
64581 * 0b11..pull disabled
64582 */
64583#define IOMUXD_CSI_DIG_D05_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_PULL_SHIFT)) & IOMUXD_CSI_DIG_D05_PULL_MASK)
64584#define IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_7_18_MASK (0x7FF80U)
64585#define IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_7_18_SHIFT (7U)
64586/*! CSI_DIG_D05_reserved_7_18 - reserved
64587 */
64588#define IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D05_CSI_DIG_D05_reserved_7_18_MASK)
64589#define IOMUXD_CSI_DIG_D05_WAKEUP_CTRL_MASK (0x380000U)
64590#define IOMUXD_CSI_DIG_D05_WAKEUP_CTRL_SHIFT (19U)
64591/*! WAKEUP_CTRL - wakeup control
64592 * 0b000..OFF
64593 * 0b001..RESAMPLE
64594 * 0b100..LOW
64595 * 0b111..HIGH
64596 * 0b110..RISE
64597 * 0b101..FALL
64598 */
64599#define IOMUXD_CSI_DIG_D05_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D05_WAKEUP_CTRL_MASK)
64600#define IOMUXD_CSI_DIG_D05_WAKEUP_MASK_MASK (0x400000U)
64601#define IOMUXD_CSI_DIG_D05_WAKEUP_MASK_SHIFT (22U)
64602/*! WAKEUP_MASK - wakeup mask
64603 */
64604#define IOMUXD_CSI_DIG_D05_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D05_WAKEUP_MASK_MASK)
64605#define IOMUXD_CSI_DIG_D05_lp_config_MASK (0x1800000U)
64606#define IOMUXD_CSI_DIG_D05_lp_config_SHIFT (23U)
64607/*! lp_config - lower power configuration
64608 * 0b01..EARLY_ISO
64609 * 0b10..LATE_ISO
64610 * 0b11..LATCH
64611 * 0b00..PASS
64612 */
64613#define IOMUXD_CSI_DIG_D05_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D05_lp_config_MASK)
64614#define IOMUXD_CSI_DIG_D05_sw_config_MASK (0x6000000U)
64615#define IOMUXD_CSI_DIG_D05_sw_config_SHIFT (25U)
64616/*! sw_config - output and input configuration
64617 * 0b01..OPEN_DRAIN
64618 * 0b10..OPEN_DRAIN_INPUT
64619 * 0b11..INOUT
64620 * 0b00..DEFAULT
64621 */
64622#define IOMUXD_CSI_DIG_D05_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D05_sw_config_MASK)
64623#define IOMUXD_CSI_DIG_D05_mux_mode_MASK (0x38000000U)
64624#define IOMUXD_CSI_DIG_D05_mux_mode_SHIFT (27U)
64625/*! mux_mode - mux_mode
64626 * 0b000..CI_PI.D07
64627 * 0b010..ADMA.SAI2.RXFS
64628 */
64629#define IOMUXD_CSI_DIG_D05_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D05_mux_mode_MASK)
64630#define IOMUXD_CSI_DIG_D05_update_pad_ctl_MASK (0x40000000U)
64631#define IOMUXD_CSI_DIG_D05_update_pad_ctl_SHIFT (30U)
64632/*! update_pad_ctl - update lock for pad control
64633 */
64634#define IOMUXD_CSI_DIG_D05_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D05_update_pad_ctl_MASK)
64635#define IOMUXD_CSI_DIG_D05_update_mux_mode_MASK (0x80000000U)
64636#define IOMUXD_CSI_DIG_D05_update_mux_mode_SHIFT (31U)
64637/*! update_mux_mode - update lock for mux control
64638 */
64639#define IOMUXD_CSI_DIG_D05_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D05_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D05_update_mux_mode_MASK)
64640/*! @} */
64641
64642/*! @name IOMUXD_GROUP_2_3 - na */
64643/*! @{ */
64644#define IOMUXD_IOMUXD_GROUP_2_3_PMIC_I2C_SDA_MASK (0x1U)
64645#define IOMUXD_IOMUXD_GROUP_2_3_PMIC_I2C_SDA_SHIFT (0U)
64646/*! PMIC_I2C_SDA - wakeup from PMIC_I2C_SDA
64647 */
64648#define IOMUXD_IOMUXD_GROUP_2_3_PMIC_I2C_SDA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_PMIC_I2C_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_PMIC_I2C_SDA_MASK)
64649#define IOMUXD_IOMUXD_GROUP_2_3_PMIC_INT_B_MASK (0x2U)
64650#define IOMUXD_IOMUXD_GROUP_2_3_PMIC_INT_B_SHIFT (1U)
64651/*! PMIC_INT_B - wakeup from PMIC_INT_B
64652 */
64653#define IOMUXD_IOMUXD_GROUP_2_3_PMIC_INT_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_PMIC_INT_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_PMIC_INT_B_MASK)
64654#define IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_00_MASK (0x4U)
64655#define IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_00_SHIFT (2U)
64656/*! SCU_GPIO0_00 - wakeup from SCU_GPIO0_00
64657 */
64658#define IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_00(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_00_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_00_MASK)
64659#define IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_01_MASK (0x8U)
64660#define IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_01_SHIFT (3U)
64661/*! SCU_GPIO0_01 - wakeup from SCU_GPIO0_01
64662 */
64663#define IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_01(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_01_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_GPIO0_01_MASK)
64664#define IOMUXD_IOMUXD_GROUP_2_3_SCU_PMIC_STANDBY_MASK (0x10U)
64665#define IOMUXD_IOMUXD_GROUP_2_3_SCU_PMIC_STANDBY_SHIFT (4U)
64666/*! SCU_PMIC_STANDBY - wakeup from SCU_PMIC_STANDBY
64667 */
64668#define IOMUXD_IOMUXD_GROUP_2_3_SCU_PMIC_STANDBY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_PMIC_STANDBY_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_PMIC_STANDBY_MASK)
64669#define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE0_MASK (0x20U)
64670#define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE0_SHIFT (5U)
64671/*! SCU_BOOT_MODE0 - wakeup from SCU_BOOT_MODE0
64672 */
64673#define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE0_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE0_MASK)
64674#define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE1_MASK (0x40U)
64675#define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE1_SHIFT (6U)
64676/*! SCU_BOOT_MODE1 - wakeup from SCU_BOOT_MODE1
64677 */
64678#define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE1_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE1_MASK)
64679#define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE2_MASK (0x80U)
64680#define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE2_SHIFT (7U)
64681/*! SCU_BOOT_MODE2 - wakeup from SCU_BOOT_MODE2
64682 */
64683#define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE2_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE2_MASK)
64684#define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE3_MASK (0x100U)
64685#define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE3_SHIFT (8U)
64686/*! SCU_BOOT_MODE3 - wakeup from SCU_BOOT_MODE3
64687 */
64688#define IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE3_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_SCU_BOOT_MODE3_MASK)
64689#define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D00_MASK (0x200U)
64690#define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D00_SHIFT (9U)
64691/*! CSI_DIG_D00 - wakeup from CSI_DIG_D00
64692 */
64693#define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D00(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D00_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D00_MASK)
64694#define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D01_MASK (0x400U)
64695#define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D01_SHIFT (10U)
64696/*! CSI_DIG_D01 - wakeup from CSI_DIG_D01
64697 */
64698#define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D01(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D01_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D01_MASK)
64699#define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D02_MASK (0x800U)
64700#define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D02_SHIFT (11U)
64701/*! CSI_DIG_D02 - wakeup from CSI_DIG_D02
64702 */
64703#define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D02(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D02_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D02_MASK)
64704#define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D03_MASK (0x1000U)
64705#define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D03_SHIFT (12U)
64706/*! CSI_DIG_D03 - wakeup from CSI_DIG_D03
64707 */
64708#define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D03(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D03_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D03_MASK)
64709#define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D04_MASK (0x2000U)
64710#define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D04_SHIFT (13U)
64711/*! CSI_DIG_D04 - wakeup from CSI_DIG_D04
64712 */
64713#define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D04(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D04_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D04_MASK)
64714#define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D05_MASK (0x4000U)
64715#define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D05_SHIFT (14U)
64716/*! CSI_DIG_D05 - wakeup from CSI_DIG_D05
64717 */
64718#define IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D05(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D05_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_CSI_DIG_D05_MASK)
64719#define IOMUXD_IOMUXD_GROUP_2_3_iomuxd_group_2_3_reserved_15_31_MASK (0xFFFF8000U)
64720#define IOMUXD_IOMUXD_GROUP_2_3_iomuxd_group_2_3_reserved_15_31_SHIFT (15U)
64721/*! iomuxd_group_2_3_reserved_15_31 - reserved
64722 */
64723#define IOMUXD_IOMUXD_GROUP_2_3_iomuxd_group_2_3_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_3_iomuxd_group_2_3_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_3_iomuxd_group_2_3_reserved_15_31_MASK)
64724/*! @} */
64725
64726/*! @name CSI_DIG_D06 - CSI_DIG_D06 */
64727/*! @{ */
64728#define IOMUXD_CSI_DIG_D06_PDRV_MASK (0x1U)
64729#define IOMUXD_CSI_DIG_D06_PDRV_SHIFT (0U)
64730/*! PDRV - Drive
64731 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
64732 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
64733 */
64734#define IOMUXD_CSI_DIG_D06_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D06_PDRV_MASK)
64735#define IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_1_4_MASK (0x1EU)
64736#define IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_1_4_SHIFT (1U)
64737/*! CSI_DIG_D06_reserved_1_4 - reserved
64738 */
64739#define IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_1_4_MASK)
64740#define IOMUXD_CSI_DIG_D06_PULL_MASK (0x60U)
64741#define IOMUXD_CSI_DIG_D06_PULL_SHIFT (5U)
64742/*! PULL - Pull Down Pull Up
64743 * 0b10..pull down
64744 * 0b01..pull up
64745 * 0b00..Prohibited
64746 * 0b11..pull disabled
64747 */
64748#define IOMUXD_CSI_DIG_D06_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_PULL_SHIFT)) & IOMUXD_CSI_DIG_D06_PULL_MASK)
64749#define IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_7_18_MASK (0x7FF80U)
64750#define IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_7_18_SHIFT (7U)
64751/*! CSI_DIG_D06_reserved_7_18 - reserved
64752 */
64753#define IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D06_CSI_DIG_D06_reserved_7_18_MASK)
64754#define IOMUXD_CSI_DIG_D06_WAKEUP_CTRL_MASK (0x380000U)
64755#define IOMUXD_CSI_DIG_D06_WAKEUP_CTRL_SHIFT (19U)
64756/*! WAKEUP_CTRL - wakeup control
64757 * 0b000..OFF
64758 * 0b001..RESAMPLE
64759 * 0b100..LOW
64760 * 0b111..HIGH
64761 * 0b110..RISE
64762 * 0b101..FALL
64763 */
64764#define IOMUXD_CSI_DIG_D06_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D06_WAKEUP_CTRL_MASK)
64765#define IOMUXD_CSI_DIG_D06_WAKEUP_MASK_MASK (0x400000U)
64766#define IOMUXD_CSI_DIG_D06_WAKEUP_MASK_SHIFT (22U)
64767/*! WAKEUP_MASK - wakeup mask
64768 */
64769#define IOMUXD_CSI_DIG_D06_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D06_WAKEUP_MASK_MASK)
64770#define IOMUXD_CSI_DIG_D06_lp_config_MASK (0x1800000U)
64771#define IOMUXD_CSI_DIG_D06_lp_config_SHIFT (23U)
64772/*! lp_config - lower power configuration
64773 * 0b01..EARLY_ISO
64774 * 0b10..LATE_ISO
64775 * 0b11..LATCH
64776 * 0b00..PASS
64777 */
64778#define IOMUXD_CSI_DIG_D06_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D06_lp_config_MASK)
64779#define IOMUXD_CSI_DIG_D06_sw_config_MASK (0x6000000U)
64780#define IOMUXD_CSI_DIG_D06_sw_config_SHIFT (25U)
64781/*! sw_config - output and input configuration
64782 * 0b01..OPEN_DRAIN
64783 * 0b10..OPEN_DRAIN_INPUT
64784 * 0b11..INOUT
64785 * 0b00..DEFAULT
64786 */
64787#define IOMUXD_CSI_DIG_D06_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D06_sw_config_MASK)
64788#define IOMUXD_CSI_DIG_D06_mux_mode_MASK (0x38000000U)
64789#define IOMUXD_CSI_DIG_D06_mux_mode_SHIFT (27U)
64790/*! mux_mode - mux_mode
64791 * 0b000..CI_PI.D08
64792 * 0b010..ADMA.SAI3.RXC
64793 */
64794#define IOMUXD_CSI_DIG_D06_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D06_mux_mode_MASK)
64795#define IOMUXD_CSI_DIG_D06_update_pad_ctl_MASK (0x40000000U)
64796#define IOMUXD_CSI_DIG_D06_update_pad_ctl_SHIFT (30U)
64797/*! update_pad_ctl - update lock for pad control
64798 */
64799#define IOMUXD_CSI_DIG_D06_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D06_update_pad_ctl_MASK)
64800#define IOMUXD_CSI_DIG_D06_update_mux_mode_MASK (0x80000000U)
64801#define IOMUXD_CSI_DIG_D06_update_mux_mode_SHIFT (31U)
64802/*! update_mux_mode - update lock for mux control
64803 */
64804#define IOMUXD_CSI_DIG_D06_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D06_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D06_update_mux_mode_MASK)
64805/*! @} */
64806
64807/*! @name CSI_DIG_D07 - CSI_DIG_D07 */
64808/*! @{ */
64809#define IOMUXD_CSI_DIG_D07_PDRV_MASK (0x1U)
64810#define IOMUXD_CSI_DIG_D07_PDRV_SHIFT (0U)
64811/*! PDRV - Drive
64812 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
64813 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
64814 */
64815#define IOMUXD_CSI_DIG_D07_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_PDRV_SHIFT)) & IOMUXD_CSI_DIG_D07_PDRV_MASK)
64816#define IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_1_4_MASK (0x1EU)
64817#define IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_1_4_SHIFT (1U)
64818/*! CSI_DIG_D07_reserved_1_4 - reserved
64819 */
64820#define IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_1_4_MASK)
64821#define IOMUXD_CSI_DIG_D07_PULL_MASK (0x60U)
64822#define IOMUXD_CSI_DIG_D07_PULL_SHIFT (5U)
64823/*! PULL - Pull Down Pull Up
64824 * 0b10..pull down
64825 * 0b01..pull up
64826 * 0b00..Prohibited
64827 * 0b11..pull disabled
64828 */
64829#define IOMUXD_CSI_DIG_D07_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_PULL_SHIFT)) & IOMUXD_CSI_DIG_D07_PULL_MASK)
64830#define IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_7_18_MASK (0x7FF80U)
64831#define IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_7_18_SHIFT (7U)
64832/*! CSI_DIG_D07_reserved_7_18 - reserved
64833 */
64834#define IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_D07_CSI_DIG_D07_reserved_7_18_MASK)
64835#define IOMUXD_CSI_DIG_D07_WAKEUP_CTRL_MASK (0x380000U)
64836#define IOMUXD_CSI_DIG_D07_WAKEUP_CTRL_SHIFT (19U)
64837/*! WAKEUP_CTRL - wakeup control
64838 * 0b000..OFF
64839 * 0b001..RESAMPLE
64840 * 0b100..LOW
64841 * 0b111..HIGH
64842 * 0b110..RISE
64843 * 0b101..FALL
64844 */
64845#define IOMUXD_CSI_DIG_D07_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_D07_WAKEUP_CTRL_MASK)
64846#define IOMUXD_CSI_DIG_D07_WAKEUP_MASK_MASK (0x400000U)
64847#define IOMUXD_CSI_DIG_D07_WAKEUP_MASK_SHIFT (22U)
64848/*! WAKEUP_MASK - wakeup mask
64849 */
64850#define IOMUXD_CSI_DIG_D07_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_D07_WAKEUP_MASK_MASK)
64851#define IOMUXD_CSI_DIG_D07_lp_config_MASK (0x1800000U)
64852#define IOMUXD_CSI_DIG_D07_lp_config_SHIFT (23U)
64853/*! lp_config - lower power configuration
64854 * 0b01..EARLY_ISO
64855 * 0b10..LATE_ISO
64856 * 0b11..LATCH
64857 * 0b00..PASS
64858 */
64859#define IOMUXD_CSI_DIG_D07_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_lp_config_SHIFT)) & IOMUXD_CSI_DIG_D07_lp_config_MASK)
64860#define IOMUXD_CSI_DIG_D07_sw_config_MASK (0x6000000U)
64861#define IOMUXD_CSI_DIG_D07_sw_config_SHIFT (25U)
64862/*! sw_config - output and input configuration
64863 * 0b01..OPEN_DRAIN
64864 * 0b10..OPEN_DRAIN_INPUT
64865 * 0b11..INOUT
64866 * 0b00..DEFAULT
64867 */
64868#define IOMUXD_CSI_DIG_D07_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_sw_config_SHIFT)) & IOMUXD_CSI_DIG_D07_sw_config_MASK)
64869#define IOMUXD_CSI_DIG_D07_mux_mode_MASK (0x38000000U)
64870#define IOMUXD_CSI_DIG_D07_mux_mode_SHIFT (27U)
64871/*! mux_mode - mux_mode
64872 * 0b000..CI_PI.D09
64873 * 0b010..ADMA.SAI3.RXD
64874 */
64875#define IOMUXD_CSI_DIG_D07_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D07_mux_mode_MASK)
64876#define IOMUXD_CSI_DIG_D07_update_pad_ctl_MASK (0x40000000U)
64877#define IOMUXD_CSI_DIG_D07_update_pad_ctl_SHIFT (30U)
64878/*! update_pad_ctl - update lock for pad control
64879 */
64880#define IOMUXD_CSI_DIG_D07_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_D07_update_pad_ctl_MASK)
64881#define IOMUXD_CSI_DIG_D07_update_mux_mode_MASK (0x80000000U)
64882#define IOMUXD_CSI_DIG_D07_update_mux_mode_SHIFT (31U)
64883/*! update_mux_mode - update lock for mux control
64884 */
64885#define IOMUXD_CSI_DIG_D07_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_D07_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_D07_update_mux_mode_MASK)
64886/*! @} */
64887
64888/*! @name CSI_DIG_HSYNC - CSI_DIG_HSYNC */
64889/*! @{ */
64890#define IOMUXD_CSI_DIG_HSYNC_PDRV_MASK (0x1U)
64891#define IOMUXD_CSI_DIG_HSYNC_PDRV_SHIFT (0U)
64892/*! PDRV - Drive
64893 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
64894 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
64895 */
64896#define IOMUXD_CSI_DIG_HSYNC_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_PDRV_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_PDRV_MASK)
64897#define IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_1_4_MASK (0x1EU)
64898#define IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_1_4_SHIFT (1U)
64899/*! CSI_DIG_HSYNC_reserved_1_4 - reserved
64900 */
64901#define IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_1_4_MASK)
64902#define IOMUXD_CSI_DIG_HSYNC_PULL_MASK (0x60U)
64903#define IOMUXD_CSI_DIG_HSYNC_PULL_SHIFT (5U)
64904/*! PULL - Pull Down Pull Up
64905 * 0b10..pull down
64906 * 0b01..pull up
64907 * 0b00..Prohibited
64908 * 0b11..pull disabled
64909 */
64910#define IOMUXD_CSI_DIG_HSYNC_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_PULL_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_PULL_MASK)
64911#define IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_7_18_MASK (0x7FF80U)
64912#define IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_7_18_SHIFT (7U)
64913/*! CSI_DIG_HSYNC_reserved_7_18 - reserved
64914 */
64915#define IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_CSI_DIG_HSYNC_reserved_7_18_MASK)
64916#define IOMUXD_CSI_DIG_HSYNC_WAKEUP_CTRL_MASK (0x380000U)
64917#define IOMUXD_CSI_DIG_HSYNC_WAKEUP_CTRL_SHIFT (19U)
64918/*! WAKEUP_CTRL - wakeup control
64919 * 0b000..OFF
64920 * 0b001..RESAMPLE
64921 * 0b100..LOW
64922 * 0b111..HIGH
64923 * 0b110..RISE
64924 * 0b101..FALL
64925 */
64926#define IOMUXD_CSI_DIG_HSYNC_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_WAKEUP_CTRL_MASK)
64927#define IOMUXD_CSI_DIG_HSYNC_WAKEUP_MASK_MASK (0x400000U)
64928#define IOMUXD_CSI_DIG_HSYNC_WAKEUP_MASK_SHIFT (22U)
64929/*! WAKEUP_MASK - wakeup mask
64930 */
64931#define IOMUXD_CSI_DIG_HSYNC_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_WAKEUP_MASK_MASK)
64932#define IOMUXD_CSI_DIG_HSYNC_lp_config_MASK (0x1800000U)
64933#define IOMUXD_CSI_DIG_HSYNC_lp_config_SHIFT (23U)
64934/*! lp_config - lower power configuration
64935 * 0b01..EARLY_ISO
64936 * 0b10..LATE_ISO
64937 * 0b11..LATCH
64938 * 0b00..PASS
64939 */
64940#define IOMUXD_CSI_DIG_HSYNC_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_lp_config_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_lp_config_MASK)
64941#define IOMUXD_CSI_DIG_HSYNC_sw_config_MASK (0x6000000U)
64942#define IOMUXD_CSI_DIG_HSYNC_sw_config_SHIFT (25U)
64943/*! sw_config - output and input configuration
64944 * 0b01..OPEN_DRAIN
64945 * 0b10..OPEN_DRAIN_INPUT
64946 * 0b11..INOUT
64947 * 0b00..DEFAULT
64948 */
64949#define IOMUXD_CSI_DIG_HSYNC_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_sw_config_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_sw_config_MASK)
64950#define IOMUXD_CSI_DIG_HSYNC_mux_mode_MASK (0x38000000U)
64951#define IOMUXD_CSI_DIG_HSYNC_mux_mode_SHIFT (27U)
64952/*! mux_mode - mux_mode
64953 * 0b000..CI_PI.HSYNC
64954 * 0b001..CI_PI.D00
64955 * 0b010..ADMA.SAI3.RXFS
64956 */
64957#define IOMUXD_CSI_DIG_HSYNC_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_mux_mode_MASK)
64958#define IOMUXD_CSI_DIG_HSYNC_update_pad_ctl_MASK (0x40000000U)
64959#define IOMUXD_CSI_DIG_HSYNC_update_pad_ctl_SHIFT (30U)
64960/*! update_pad_ctl - update lock for pad control
64961 */
64962#define IOMUXD_CSI_DIG_HSYNC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_update_pad_ctl_MASK)
64963#define IOMUXD_CSI_DIG_HSYNC_update_mux_mode_MASK (0x80000000U)
64964#define IOMUXD_CSI_DIG_HSYNC_update_mux_mode_SHIFT (31U)
64965/*! update_mux_mode - update lock for mux control
64966 */
64967#define IOMUXD_CSI_DIG_HSYNC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_HSYNC_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_HSYNC_update_mux_mode_MASK)
64968/*! @} */
64969
64970/*! @name CSI_DIG_VSYNC - CSI_DIG_VSYNC */
64971/*! @{ */
64972#define IOMUXD_CSI_DIG_VSYNC_PDRV_MASK (0x1U)
64973#define IOMUXD_CSI_DIG_VSYNC_PDRV_SHIFT (0U)
64974/*! PDRV - Drive
64975 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
64976 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
64977 */
64978#define IOMUXD_CSI_DIG_VSYNC_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_PDRV_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_PDRV_MASK)
64979#define IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_1_4_MASK (0x1EU)
64980#define IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_1_4_SHIFT (1U)
64981/*! CSI_DIG_VSYNC_reserved_1_4 - reserved
64982 */
64983#define IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_1_4_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_1_4_MASK)
64984#define IOMUXD_CSI_DIG_VSYNC_PULL_MASK (0x60U)
64985#define IOMUXD_CSI_DIG_VSYNC_PULL_SHIFT (5U)
64986/*! PULL - Pull Down Pull Up
64987 * 0b10..pull down
64988 * 0b01..pull up
64989 * 0b00..Prohibited
64990 * 0b11..pull disabled
64991 */
64992#define IOMUXD_CSI_DIG_VSYNC_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_PULL_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_PULL_MASK)
64993#define IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_7_18_MASK (0x7FF80U)
64994#define IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_7_18_SHIFT (7U)
64995/*! CSI_DIG_VSYNC_reserved_7_18 - reserved
64996 */
64997#define IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_7_18_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_CSI_DIG_VSYNC_reserved_7_18_MASK)
64998#define IOMUXD_CSI_DIG_VSYNC_WAKEUP_CTRL_MASK (0x380000U)
64999#define IOMUXD_CSI_DIG_VSYNC_WAKEUP_CTRL_SHIFT (19U)
65000/*! WAKEUP_CTRL - wakeup control
65001 * 0b000..OFF
65002 * 0b001..RESAMPLE
65003 * 0b100..LOW
65004 * 0b111..HIGH
65005 * 0b110..RISE
65006 * 0b101..FALL
65007 */
65008#define IOMUXD_CSI_DIG_VSYNC_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_WAKEUP_CTRL_MASK)
65009#define IOMUXD_CSI_DIG_VSYNC_WAKEUP_MASK_MASK (0x400000U)
65010#define IOMUXD_CSI_DIG_VSYNC_WAKEUP_MASK_SHIFT (22U)
65011/*! WAKEUP_MASK - wakeup mask
65012 */
65013#define IOMUXD_CSI_DIG_VSYNC_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_WAKEUP_MASK_MASK)
65014#define IOMUXD_CSI_DIG_VSYNC_lp_config_MASK (0x1800000U)
65015#define IOMUXD_CSI_DIG_VSYNC_lp_config_SHIFT (23U)
65016/*! lp_config - lower power configuration
65017 * 0b01..EARLY_ISO
65018 * 0b10..LATE_ISO
65019 * 0b11..LATCH
65020 * 0b00..PASS
65021 */
65022#define IOMUXD_CSI_DIG_VSYNC_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_lp_config_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_lp_config_MASK)
65023#define IOMUXD_CSI_DIG_VSYNC_sw_config_MASK (0x6000000U)
65024#define IOMUXD_CSI_DIG_VSYNC_sw_config_SHIFT (25U)
65025/*! sw_config - output and input configuration
65026 * 0b01..OPEN_DRAIN
65027 * 0b10..OPEN_DRAIN_INPUT
65028 * 0b11..INOUT
65029 * 0b00..DEFAULT
65030 */
65031#define IOMUXD_CSI_DIG_VSYNC_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_sw_config_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_sw_config_MASK)
65032#define IOMUXD_CSI_DIG_VSYNC_mux_mode_MASK (0x38000000U)
65033#define IOMUXD_CSI_DIG_VSYNC_mux_mode_SHIFT (27U)
65034/*! mux_mode - mux_mode
65035 * 0b000..CI_PI.VSYNC
65036 * 0b001..CI_PI.D01
65037 */
65038#define IOMUXD_CSI_DIG_VSYNC_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_mux_mode_MASK)
65039#define IOMUXD_CSI_DIG_VSYNC_update_pad_ctl_MASK (0x40000000U)
65040#define IOMUXD_CSI_DIG_VSYNC_update_pad_ctl_SHIFT (30U)
65041/*! update_pad_ctl - update lock for pad control
65042 */
65043#define IOMUXD_CSI_DIG_VSYNC_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_update_pad_ctl_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_update_pad_ctl_MASK)
65044#define IOMUXD_CSI_DIG_VSYNC_update_mux_mode_MASK (0x80000000U)
65045#define IOMUXD_CSI_DIG_VSYNC_update_mux_mode_SHIFT (31U)
65046/*! update_mux_mode - update lock for mux control
65047 */
65048#define IOMUXD_CSI_DIG_VSYNC_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_DIG_VSYNC_update_mux_mode_SHIFT)) & IOMUXD_CSI_DIG_VSYNC_update_mux_mode_MASK)
65049/*! @} */
65050
65051/*! @name CSI_PCLK - CSI_PCLK */
65052/*! @{ */
65053#define IOMUXD_CSI_PCLK_PDRV_MASK (0x1U)
65054#define IOMUXD_CSI_PCLK_PDRV_SHIFT (0U)
65055/*! PDRV - Drive
65056 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
65057 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
65058 */
65059#define IOMUXD_CSI_PCLK_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_PDRV_SHIFT)) & IOMUXD_CSI_PCLK_PDRV_MASK)
65060#define IOMUXD_CSI_PCLK_CSI_PCLK_reserved_1_4_MASK (0x1EU)
65061#define IOMUXD_CSI_PCLK_CSI_PCLK_reserved_1_4_SHIFT (1U)
65062/*! CSI_PCLK_reserved_1_4 - reserved
65063 */
65064#define IOMUXD_CSI_PCLK_CSI_PCLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_CSI_PCLK_reserved_1_4_SHIFT)) & IOMUXD_CSI_PCLK_CSI_PCLK_reserved_1_4_MASK)
65065#define IOMUXD_CSI_PCLK_PULL_MASK (0x60U)
65066#define IOMUXD_CSI_PCLK_PULL_SHIFT (5U)
65067/*! PULL - Pull Down Pull Up
65068 * 0b10..pull down
65069 * 0b01..pull up
65070 * 0b00..Prohibited
65071 * 0b11..pull disabled
65072 */
65073#define IOMUXD_CSI_PCLK_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_PULL_SHIFT)) & IOMUXD_CSI_PCLK_PULL_MASK)
65074#define IOMUXD_CSI_PCLK_CSI_PCLK_reserved_7_18_MASK (0x7FF80U)
65075#define IOMUXD_CSI_PCLK_CSI_PCLK_reserved_7_18_SHIFT (7U)
65076/*! CSI_PCLK_reserved_7_18 - reserved
65077 */
65078#define IOMUXD_CSI_PCLK_CSI_PCLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_CSI_PCLK_reserved_7_18_SHIFT)) & IOMUXD_CSI_PCLK_CSI_PCLK_reserved_7_18_MASK)
65079#define IOMUXD_CSI_PCLK_WAKEUP_CTRL_MASK (0x380000U)
65080#define IOMUXD_CSI_PCLK_WAKEUP_CTRL_SHIFT (19U)
65081/*! WAKEUP_CTRL - wakeup control
65082 * 0b000..OFF
65083 * 0b001..RESAMPLE
65084 * 0b100..LOW
65085 * 0b111..HIGH
65086 * 0b110..RISE
65087 * 0b101..FALL
65088 */
65089#define IOMUXD_CSI_PCLK_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_PCLK_WAKEUP_CTRL_MASK)
65090#define IOMUXD_CSI_PCLK_WAKEUP_MASK_MASK (0x400000U)
65091#define IOMUXD_CSI_PCLK_WAKEUP_MASK_SHIFT (22U)
65092/*! WAKEUP_MASK - wakeup mask
65093 */
65094#define IOMUXD_CSI_PCLK_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_PCLK_WAKEUP_MASK_MASK)
65095#define IOMUXD_CSI_PCLK_lp_config_MASK (0x1800000U)
65096#define IOMUXD_CSI_PCLK_lp_config_SHIFT (23U)
65097/*! lp_config - lower power configuration
65098 * 0b01..EARLY_ISO
65099 * 0b10..LATE_ISO
65100 * 0b11..LATCH
65101 * 0b00..PASS
65102 */
65103#define IOMUXD_CSI_PCLK_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_lp_config_SHIFT)) & IOMUXD_CSI_PCLK_lp_config_MASK)
65104#define IOMUXD_CSI_PCLK_sw_config_MASK (0x6000000U)
65105#define IOMUXD_CSI_PCLK_sw_config_SHIFT (25U)
65106/*! sw_config - output and input configuration
65107 * 0b01..OPEN_DRAIN
65108 * 0b10..OPEN_DRAIN_INPUT
65109 * 0b11..INOUT
65110 * 0b00..DEFAULT
65111 */
65112#define IOMUXD_CSI_PCLK_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_sw_config_SHIFT)) & IOMUXD_CSI_PCLK_sw_config_MASK)
65113#define IOMUXD_CSI_PCLK_mux_mode_MASK (0x38000000U)
65114#define IOMUXD_CSI_PCLK_mux_mode_SHIFT (27U)
65115/*! mux_mode - mux_mode
65116 * 0b000..CI_PI.PCLK
65117 * 0b001..MIPI_CSI0.I2C0.SCL
65118 * 0b011..ADMA.SPI1.SCK
65119 * 0b100..LSIO.GPIO3.IO00
65120 */
65121#define IOMUXD_CSI_PCLK_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_mux_mode_SHIFT)) & IOMUXD_CSI_PCLK_mux_mode_MASK)
65122#define IOMUXD_CSI_PCLK_update_pad_ctl_MASK (0x40000000U)
65123#define IOMUXD_CSI_PCLK_update_pad_ctl_SHIFT (30U)
65124/*! update_pad_ctl - update lock for pad control
65125 */
65126#define IOMUXD_CSI_PCLK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_update_pad_ctl_SHIFT)) & IOMUXD_CSI_PCLK_update_pad_ctl_MASK)
65127#define IOMUXD_CSI_PCLK_update_mux_mode_MASK (0x80000000U)
65128#define IOMUXD_CSI_PCLK_update_mux_mode_SHIFT (31U)
65129/*! update_mux_mode - update lock for mux control
65130 */
65131#define IOMUXD_CSI_PCLK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_PCLK_update_mux_mode_SHIFT)) & IOMUXD_CSI_PCLK_update_mux_mode_MASK)
65132/*! @} */
65133
65134/*! @name CSI_MCLK - CSI_MCLK */
65135/*! @{ */
65136#define IOMUXD_CSI_MCLK_PDRV_MASK (0x1U)
65137#define IOMUXD_CSI_MCLK_PDRV_SHIFT (0U)
65138/*! PDRV - Drive
65139 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
65140 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
65141 */
65142#define IOMUXD_CSI_MCLK_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_PDRV_SHIFT)) & IOMUXD_CSI_MCLK_PDRV_MASK)
65143#define IOMUXD_CSI_MCLK_CSI_MCLK_reserved_1_4_MASK (0x1EU)
65144#define IOMUXD_CSI_MCLK_CSI_MCLK_reserved_1_4_SHIFT (1U)
65145/*! CSI_MCLK_reserved_1_4 - reserved
65146 */
65147#define IOMUXD_CSI_MCLK_CSI_MCLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_CSI_MCLK_reserved_1_4_SHIFT)) & IOMUXD_CSI_MCLK_CSI_MCLK_reserved_1_4_MASK)
65148#define IOMUXD_CSI_MCLK_PULL_MASK (0x60U)
65149#define IOMUXD_CSI_MCLK_PULL_SHIFT (5U)
65150/*! PULL - Pull Down Pull Up
65151 * 0b10..pull down
65152 * 0b01..pull up
65153 * 0b00..Prohibited
65154 * 0b11..pull disabled
65155 */
65156#define IOMUXD_CSI_MCLK_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_PULL_SHIFT)) & IOMUXD_CSI_MCLK_PULL_MASK)
65157#define IOMUXD_CSI_MCLK_CSI_MCLK_reserved_7_18_MASK (0x7FF80U)
65158#define IOMUXD_CSI_MCLK_CSI_MCLK_reserved_7_18_SHIFT (7U)
65159/*! CSI_MCLK_reserved_7_18 - reserved
65160 */
65161#define IOMUXD_CSI_MCLK_CSI_MCLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_CSI_MCLK_reserved_7_18_SHIFT)) & IOMUXD_CSI_MCLK_CSI_MCLK_reserved_7_18_MASK)
65162#define IOMUXD_CSI_MCLK_WAKEUP_CTRL_MASK (0x380000U)
65163#define IOMUXD_CSI_MCLK_WAKEUP_CTRL_SHIFT (19U)
65164/*! WAKEUP_CTRL - wakeup control
65165 * 0b000..OFF
65166 * 0b001..RESAMPLE
65167 * 0b100..LOW
65168 * 0b111..HIGH
65169 * 0b110..RISE
65170 * 0b101..FALL
65171 */
65172#define IOMUXD_CSI_MCLK_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_MCLK_WAKEUP_CTRL_MASK)
65173#define IOMUXD_CSI_MCLK_WAKEUP_MASK_MASK (0x400000U)
65174#define IOMUXD_CSI_MCLK_WAKEUP_MASK_SHIFT (22U)
65175/*! WAKEUP_MASK - wakeup mask
65176 */
65177#define IOMUXD_CSI_MCLK_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_MCLK_WAKEUP_MASK_MASK)
65178#define IOMUXD_CSI_MCLK_lp_config_MASK (0x1800000U)
65179#define IOMUXD_CSI_MCLK_lp_config_SHIFT (23U)
65180/*! lp_config - lower power configuration
65181 * 0b01..EARLY_ISO
65182 * 0b10..LATE_ISO
65183 * 0b11..LATCH
65184 * 0b00..PASS
65185 */
65186#define IOMUXD_CSI_MCLK_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_lp_config_SHIFT)) & IOMUXD_CSI_MCLK_lp_config_MASK)
65187#define IOMUXD_CSI_MCLK_sw_config_MASK (0x6000000U)
65188#define IOMUXD_CSI_MCLK_sw_config_SHIFT (25U)
65189/*! sw_config - output and input configuration
65190 * 0b01..OPEN_DRAIN
65191 * 0b10..OPEN_DRAIN_INPUT
65192 * 0b11..INOUT
65193 * 0b00..DEFAULT
65194 */
65195#define IOMUXD_CSI_MCLK_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_sw_config_SHIFT)) & IOMUXD_CSI_MCLK_sw_config_MASK)
65196#define IOMUXD_CSI_MCLK_mux_mode_MASK (0x38000000U)
65197#define IOMUXD_CSI_MCLK_mux_mode_SHIFT (27U)
65198/*! mux_mode - mux_mode
65199 * 0b000..CI_PI.MCLK
65200 * 0b001..MIPI_CSI0.I2C0.SDA
65201 * 0b011..ADMA.SPI1.SDO
65202 * 0b100..LSIO.GPIO3.IO01
65203 */
65204#define IOMUXD_CSI_MCLK_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_mux_mode_SHIFT)) & IOMUXD_CSI_MCLK_mux_mode_MASK)
65205#define IOMUXD_CSI_MCLK_update_pad_ctl_MASK (0x40000000U)
65206#define IOMUXD_CSI_MCLK_update_pad_ctl_SHIFT (30U)
65207/*! update_pad_ctl - update lock for pad control
65208 */
65209#define IOMUXD_CSI_MCLK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_update_pad_ctl_SHIFT)) & IOMUXD_CSI_MCLK_update_pad_ctl_MASK)
65210#define IOMUXD_CSI_MCLK_update_mux_mode_MASK (0x80000000U)
65211#define IOMUXD_CSI_MCLK_update_mux_mode_SHIFT (31U)
65212/*! update_mux_mode - update lock for mux control
65213 */
65214#define IOMUXD_CSI_MCLK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_MCLK_update_mux_mode_SHIFT)) & IOMUXD_CSI_MCLK_update_mux_mode_MASK)
65215/*! @} */
65216
65217/*! @name CSI_EN - CSI_EN */
65218/*! @{ */
65219#define IOMUXD_CSI_EN_PDRV_MASK (0x1U)
65220#define IOMUXD_CSI_EN_PDRV_SHIFT (0U)
65221/*! PDRV - Drive
65222 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
65223 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
65224 */
65225#define IOMUXD_CSI_EN_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_PDRV_SHIFT)) & IOMUXD_CSI_EN_PDRV_MASK)
65226#define IOMUXD_CSI_EN_CSI_EN_reserved_1_4_MASK (0x1EU)
65227#define IOMUXD_CSI_EN_CSI_EN_reserved_1_4_SHIFT (1U)
65228/*! CSI_EN_reserved_1_4 - reserved
65229 */
65230#define IOMUXD_CSI_EN_CSI_EN_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_CSI_EN_reserved_1_4_SHIFT)) & IOMUXD_CSI_EN_CSI_EN_reserved_1_4_MASK)
65231#define IOMUXD_CSI_EN_PULL_MASK (0x60U)
65232#define IOMUXD_CSI_EN_PULL_SHIFT (5U)
65233/*! PULL - Pull Down Pull Up
65234 * 0b10..pull down
65235 * 0b01..pull up
65236 * 0b00..Prohibited
65237 * 0b11..pull disabled
65238 */
65239#define IOMUXD_CSI_EN_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_PULL_SHIFT)) & IOMUXD_CSI_EN_PULL_MASK)
65240#define IOMUXD_CSI_EN_CSI_EN_reserved_7_18_MASK (0x7FF80U)
65241#define IOMUXD_CSI_EN_CSI_EN_reserved_7_18_SHIFT (7U)
65242/*! CSI_EN_reserved_7_18 - reserved
65243 */
65244#define IOMUXD_CSI_EN_CSI_EN_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_CSI_EN_reserved_7_18_SHIFT)) & IOMUXD_CSI_EN_CSI_EN_reserved_7_18_MASK)
65245#define IOMUXD_CSI_EN_WAKEUP_CTRL_MASK (0x380000U)
65246#define IOMUXD_CSI_EN_WAKEUP_CTRL_SHIFT (19U)
65247/*! WAKEUP_CTRL - wakeup control
65248 * 0b000..OFF
65249 * 0b001..RESAMPLE
65250 * 0b100..LOW
65251 * 0b111..HIGH
65252 * 0b110..RISE
65253 * 0b101..FALL
65254 */
65255#define IOMUXD_CSI_EN_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_EN_WAKEUP_CTRL_MASK)
65256#define IOMUXD_CSI_EN_WAKEUP_MASK_MASK (0x400000U)
65257#define IOMUXD_CSI_EN_WAKEUP_MASK_SHIFT (22U)
65258/*! WAKEUP_MASK - wakeup mask
65259 */
65260#define IOMUXD_CSI_EN_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_EN_WAKEUP_MASK_MASK)
65261#define IOMUXD_CSI_EN_lp_config_MASK (0x1800000U)
65262#define IOMUXD_CSI_EN_lp_config_SHIFT (23U)
65263/*! lp_config - lower power configuration
65264 * 0b01..EARLY_ISO
65265 * 0b10..LATE_ISO
65266 * 0b11..LATCH
65267 * 0b00..PASS
65268 */
65269#define IOMUXD_CSI_EN_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_lp_config_SHIFT)) & IOMUXD_CSI_EN_lp_config_MASK)
65270#define IOMUXD_CSI_EN_sw_config_MASK (0x6000000U)
65271#define IOMUXD_CSI_EN_sw_config_SHIFT (25U)
65272/*! sw_config - output and input configuration
65273 * 0b01..OPEN_DRAIN
65274 * 0b10..OPEN_DRAIN_INPUT
65275 * 0b11..INOUT
65276 * 0b00..DEFAULT
65277 */
65278#define IOMUXD_CSI_EN_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_sw_config_SHIFT)) & IOMUXD_CSI_EN_sw_config_MASK)
65279#define IOMUXD_CSI_EN_mux_mode_MASK (0x38000000U)
65280#define IOMUXD_CSI_EN_mux_mode_SHIFT (27U)
65281/*! mux_mode - mux_mode
65282 * 0b000..CI_PI.EN
65283 * 0b001..CI_PI.I2C.SCL
65284 * 0b010..ADMA.I2C3.SCL
65285 * 0b011..ADMA.SPI1.SDI
65286 * 0b100..LSIO.GPIO3.IO02
65287 */
65288#define IOMUXD_CSI_EN_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_mux_mode_SHIFT)) & IOMUXD_CSI_EN_mux_mode_MASK)
65289#define IOMUXD_CSI_EN_update_pad_ctl_MASK (0x40000000U)
65290#define IOMUXD_CSI_EN_update_pad_ctl_SHIFT (30U)
65291/*! update_pad_ctl - update lock for pad control
65292 */
65293#define IOMUXD_CSI_EN_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_update_pad_ctl_SHIFT)) & IOMUXD_CSI_EN_update_pad_ctl_MASK)
65294#define IOMUXD_CSI_EN_update_mux_mode_MASK (0x80000000U)
65295#define IOMUXD_CSI_EN_update_mux_mode_SHIFT (31U)
65296/*! update_mux_mode - update lock for mux control
65297 */
65298#define IOMUXD_CSI_EN_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_EN_update_mux_mode_SHIFT)) & IOMUXD_CSI_EN_update_mux_mode_MASK)
65299/*! @} */
65300
65301/*! @name CSI_RESET - CSI_RESET */
65302/*! @{ */
65303#define IOMUXD_CSI_RESET_PDRV_MASK (0x1U)
65304#define IOMUXD_CSI_RESET_PDRV_SHIFT (0U)
65305/*! PDRV - Drive
65306 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
65307 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
65308 */
65309#define IOMUXD_CSI_RESET_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_PDRV_SHIFT)) & IOMUXD_CSI_RESET_PDRV_MASK)
65310#define IOMUXD_CSI_RESET_CSI_RESET_reserved_1_4_MASK (0x1EU)
65311#define IOMUXD_CSI_RESET_CSI_RESET_reserved_1_4_SHIFT (1U)
65312/*! CSI_RESET_reserved_1_4 - reserved
65313 */
65314#define IOMUXD_CSI_RESET_CSI_RESET_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_CSI_RESET_reserved_1_4_SHIFT)) & IOMUXD_CSI_RESET_CSI_RESET_reserved_1_4_MASK)
65315#define IOMUXD_CSI_RESET_PULL_MASK (0x60U)
65316#define IOMUXD_CSI_RESET_PULL_SHIFT (5U)
65317/*! PULL - Pull Down Pull Up
65318 * 0b10..pull down
65319 * 0b01..pull up
65320 * 0b00..Prohibited
65321 * 0b11..pull disabled
65322 */
65323#define IOMUXD_CSI_RESET_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_PULL_SHIFT)) & IOMUXD_CSI_RESET_PULL_MASK)
65324#define IOMUXD_CSI_RESET_CSI_RESET_reserved_7_18_MASK (0x7FF80U)
65325#define IOMUXD_CSI_RESET_CSI_RESET_reserved_7_18_SHIFT (7U)
65326/*! CSI_RESET_reserved_7_18 - reserved
65327 */
65328#define IOMUXD_CSI_RESET_CSI_RESET_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_CSI_RESET_reserved_7_18_SHIFT)) & IOMUXD_CSI_RESET_CSI_RESET_reserved_7_18_MASK)
65329#define IOMUXD_CSI_RESET_WAKEUP_CTRL_MASK (0x380000U)
65330#define IOMUXD_CSI_RESET_WAKEUP_CTRL_SHIFT (19U)
65331/*! WAKEUP_CTRL - wakeup control
65332 * 0b000..OFF
65333 * 0b001..RESAMPLE
65334 * 0b100..LOW
65335 * 0b111..HIGH
65336 * 0b110..RISE
65337 * 0b101..FALL
65338 */
65339#define IOMUXD_CSI_RESET_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_WAKEUP_CTRL_SHIFT)) & IOMUXD_CSI_RESET_WAKEUP_CTRL_MASK)
65340#define IOMUXD_CSI_RESET_WAKEUP_MASK_MASK (0x400000U)
65341#define IOMUXD_CSI_RESET_WAKEUP_MASK_SHIFT (22U)
65342/*! WAKEUP_MASK - wakeup mask
65343 */
65344#define IOMUXD_CSI_RESET_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_WAKEUP_MASK_SHIFT)) & IOMUXD_CSI_RESET_WAKEUP_MASK_MASK)
65345#define IOMUXD_CSI_RESET_lp_config_MASK (0x1800000U)
65346#define IOMUXD_CSI_RESET_lp_config_SHIFT (23U)
65347/*! lp_config - lower power configuration
65348 * 0b01..EARLY_ISO
65349 * 0b10..LATE_ISO
65350 * 0b11..LATCH
65351 * 0b00..PASS
65352 */
65353#define IOMUXD_CSI_RESET_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_lp_config_SHIFT)) & IOMUXD_CSI_RESET_lp_config_MASK)
65354#define IOMUXD_CSI_RESET_sw_config_MASK (0x6000000U)
65355#define IOMUXD_CSI_RESET_sw_config_SHIFT (25U)
65356/*! sw_config - output and input configuration
65357 * 0b01..OPEN_DRAIN
65358 * 0b10..OPEN_DRAIN_INPUT
65359 * 0b11..INOUT
65360 * 0b00..DEFAULT
65361 */
65362#define IOMUXD_CSI_RESET_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_sw_config_SHIFT)) & IOMUXD_CSI_RESET_sw_config_MASK)
65363#define IOMUXD_CSI_RESET_mux_mode_MASK (0x38000000U)
65364#define IOMUXD_CSI_RESET_mux_mode_SHIFT (27U)
65365/*! mux_mode - mux_mode
65366 * 0b000..CI_PI.RESET
65367 * 0b001..CI_PI.I2C.SDA
65368 * 0b010..ADMA.I2C3.SDA
65369 * 0b011..ADMA.SPI1.CS0
65370 * 0b100..LSIO.GPIO3.IO03
65371 */
65372#define IOMUXD_CSI_RESET_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_mux_mode_SHIFT)) & IOMUXD_CSI_RESET_mux_mode_MASK)
65373#define IOMUXD_CSI_RESET_update_pad_ctl_MASK (0x40000000U)
65374#define IOMUXD_CSI_RESET_update_pad_ctl_SHIFT (30U)
65375/*! update_pad_ctl - update lock for pad control
65376 */
65377#define IOMUXD_CSI_RESET_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_update_pad_ctl_SHIFT)) & IOMUXD_CSI_RESET_update_pad_ctl_MASK)
65378#define IOMUXD_CSI_RESET_update_mux_mode_MASK (0x80000000U)
65379#define IOMUXD_CSI_RESET_update_mux_mode_SHIFT (31U)
65380/*! update_mux_mode - update lock for mux control
65381 */
65382#define IOMUXD_CSI_RESET_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_CSI_RESET_update_mux_mode_SHIFT)) & IOMUXD_CSI_RESET_update_mux_mode_MASK)
65383/*! @} */
65384
65385/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD - IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD */
65386/*! @{ */
65387#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMP_MASK (0x7U)
65388#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMP_SHIFT (0U)
65389/*! COMP - COMP
65390 * 0b010..Fixed code mode
65391 * 0b100..High impedance mode
65392 * 0b110..Read mode
65393 * 0b000..Normal Mode
65394 * 0b001..Freeze Mode
65395 */
65396#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMP_MASK)
65397#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_FASTFRZ_EN_MASK (0x8U)
65398#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_FASTFRZ_EN_SHIFT (3U)
65399/*! FASTFRZ_EN - FASTFRZ_EN
65400 * 0b1..FASTFRZ signal is driven by output of subsystem
65401 * 0b0..FASTFRZ signal is gated to 0
65402 */
65403#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_FASTFRZ_EN_MASK)
65404#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_4_4_MASK (0x10U)
65405#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_4_4_SHIFT (4U)
65406/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_4_4 - reserved
65407 */
65408#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_4_4_MASK)
65409#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCP_MASK (0x1E0U)
65410#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCP_SHIFT (5U)
65411/*! RASRCP - RASRCP
65412 * 0b0101..Reset Value
65413 */
65414#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCP_MASK)
65415#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCN_MASK (0x1E00U)
65416#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCN_SHIFT (9U)
65417/*! RASRCN - RASRCN
65418 * 0b1010..Reset Value
65419 */
65420#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_RASRCN_MASK)
65421#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SELECT_NASRC_MASK (0x2000U)
65422#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SELECT_NASRC_SHIFT (13U)
65423/*! SELECT_NASRC - SELECT_NASRC
65424 * 0b1..NASRCN value
65425 * 0b0..NASRCP value
65426 */
65427#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SELECT_NASRC_MASK)
65428#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMPOK_MASK (0x4000U)
65429#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMPOK_SHIFT (14U)
65430/*! COMPOK - COMPOK
65431 * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
65432 * 0b1..compensation cell in Normal mode and tracking PVT
65433 */
65434#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_COMPOK_MASK)
65435#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_READ_NASRC_MASK (0x78000U)
65436#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_READ_NASRC_SHIFT (15U)
65437/*! READ_NASRC - READ_NASRC
65438 * 0b0000..READ Only
65439 */
65440#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_READ_NASRC_MASK)
65441#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_19_22_MASK (0x780000U)
65442#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_19_22_SHIFT (19U)
65443/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_19_22 - reserved
65444 */
65445#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_19_22_MASK)
65446#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SLEEP_MASK (0x1800000U)
65447#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SLEEP_SHIFT (23U)
65448/*! SLEEP - SLEEP
65449 * 0b11..Force into sleep mode
65450 * 0b00..NO
65451 * 0b01..EARLY
65452 * 0b10..LATE
65453 */
65454#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_SLEEP_MASK)
65455#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_25_29_MASK (0x3E000000U)
65456#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_25_29_SHIFT (25U)
65457/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_25_29 - reserved
65458 */
65459#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_reserved_25_29_MASK)
65460#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_pad_ctl_MASK (0x40000000U)
65461#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_pad_ctl_SHIFT (30U)
65462/*! update_pad_ctl - update lock for pad control
65463 */
65464#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_pad_ctl_MASK)
65465#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_mux_mode_MASK (0x80000000U)
65466#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_mux_mode_SHIFT (31U)
65467/*! update_mux_mode - update lock for mux control
65468 */
65469#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_GPIORHD_update_mux_mode_MASK)
65470/*! @} */
65471
65472/*! @name MIPI_CSI0_MCLK_OUT - MIPI_CSI0_MCLK_OUT */
65473/*! @{ */
65474#define IOMUXD_MIPI_CSI0_MCLK_OUT_DSE_MASK (0x7U)
65475#define IOMUXD_MIPI_CSI0_MCLK_OUT_DSE_SHIFT (0U)
65476/*! DSE - Drive
65477 * 0b001..Drive select 2mA
65478 * 0b011..Drive select 6mA
65479 * 0b111..High Speed
65480 * 0b110..Drive select 12mA
65481 * 0b010..Drive select 4mA
65482 * 0b100..Drive select 8mA
65483 * 0b000..Drive select 1mA
65484 * 0b101..Drive select 10mA
65485 */
65486#define IOMUXD_MIPI_CSI0_MCLK_OUT_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_DSE_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_DSE_MASK)
65487#define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_3_4_MASK (0x18U)
65488#define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_3_4_SHIFT (3U)
65489/*! MIPI_CSI0_MCLK_OUT_reserved_3_4 - reserved
65490 */
65491#define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_3_4_MASK)
65492#define IOMUXD_MIPI_CSI0_MCLK_OUT_PULL_MASK (0x60U)
65493#define IOMUXD_MIPI_CSI0_MCLK_OUT_PULL_SHIFT (5U)
65494/*! PULL - Pull Down Pull Up
65495 * 0b00..Bus-Keeper
65496 * 0b10..pull down
65497 * 0b01..pull up
65498 * 0b11..No Pull
65499 */
65500#define IOMUXD_MIPI_CSI0_MCLK_OUT_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_PULL_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_PULL_MASK)
65501#define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_7_18_MASK (0x7FF80U)
65502#define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_7_18_SHIFT (7U)
65503/*! MIPI_CSI0_MCLK_OUT_reserved_7_18 - reserved
65504 */
65505#define IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_MCLK_OUT_reserved_7_18_MASK)
65506#define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_CTRL_MASK (0x380000U)
65507#define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_CTRL_SHIFT (19U)
65508/*! WAKEUP_CTRL - wakeup control
65509 * 0b000..OFF
65510 * 0b001..RESAMPLE
65511 * 0b100..LOW
65512 * 0b111..HIGH
65513 * 0b110..RISE
65514 * 0b101..FALL
65515 */
65516#define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_CTRL_MASK)
65517#define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_MASK_MASK (0x400000U)
65518#define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_MASK_SHIFT (22U)
65519/*! WAKEUP_MASK - wakeup mask
65520 */
65521#define IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_WAKEUP_MASK_MASK)
65522#define IOMUXD_MIPI_CSI0_MCLK_OUT_lp_config_MASK (0x1800000U)
65523#define IOMUXD_MIPI_CSI0_MCLK_OUT_lp_config_SHIFT (23U)
65524/*! lp_config - lower power configuration
65525 * 0b01..EARLY_ISO
65526 * 0b10..LATE_ISO
65527 * 0b11..LATCH
65528 * 0b00..PASS
65529 */
65530#define IOMUXD_MIPI_CSI0_MCLK_OUT_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_lp_config_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_lp_config_MASK)
65531#define IOMUXD_MIPI_CSI0_MCLK_OUT_sw_config_MASK (0x6000000U)
65532#define IOMUXD_MIPI_CSI0_MCLK_OUT_sw_config_SHIFT (25U)
65533/*! sw_config - output and input configuration
65534 * 0b01..OPEN_DRAIN
65535 * 0b10..OPEN_DRAIN_INPUT
65536 * 0b11..INOUT
65537 * 0b00..DEFAULT
65538 */
65539#define IOMUXD_MIPI_CSI0_MCLK_OUT_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_sw_config_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_sw_config_MASK)
65540#define IOMUXD_MIPI_CSI0_MCLK_OUT_mux_mode_MASK (0x38000000U)
65541#define IOMUXD_MIPI_CSI0_MCLK_OUT_mux_mode_SHIFT (27U)
65542/*! mux_mode - mux_mode
65543 * 0b000..MIPI_CSI0.ACM.MCLK_OUT
65544 * 0b100..LSIO.GPIO3.IO04
65545 */
65546#define IOMUXD_MIPI_CSI0_MCLK_OUT_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_mux_mode_MASK)
65547#define IOMUXD_MIPI_CSI0_MCLK_OUT_update_pad_ctl_MASK (0x40000000U)
65548#define IOMUXD_MIPI_CSI0_MCLK_OUT_update_pad_ctl_SHIFT (30U)
65549/*! update_pad_ctl - update lock for pad control
65550 */
65551#define IOMUXD_MIPI_CSI0_MCLK_OUT_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_update_pad_ctl_MASK)
65552#define IOMUXD_MIPI_CSI0_MCLK_OUT_update_mux_mode_MASK (0x80000000U)
65553#define IOMUXD_MIPI_CSI0_MCLK_OUT_update_mux_mode_SHIFT (31U)
65554/*! update_mux_mode - update lock for mux control
65555 */
65556#define IOMUXD_MIPI_CSI0_MCLK_OUT_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_MCLK_OUT_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_MCLK_OUT_update_mux_mode_MASK)
65557/*! @} */
65558
65559/*! @name MIPI_CSI0_I2C0_SCL - MIPI_CSI0_I2C0_SCL */
65560/*! @{ */
65561#define IOMUXD_MIPI_CSI0_I2C0_SCL_DSE_MASK (0x7U)
65562#define IOMUXD_MIPI_CSI0_I2C0_SCL_DSE_SHIFT (0U)
65563/*! DSE - Drive
65564 * 0b001..Drive select 2mA
65565 * 0b011..Drive select 6mA
65566 * 0b111..High Speed
65567 * 0b110..Drive select 12mA
65568 * 0b010..Drive select 4mA
65569 * 0b100..Drive select 8mA
65570 * 0b000..Drive select 1mA
65571 * 0b101..Drive select 10mA
65572 */
65573#define IOMUXD_MIPI_CSI0_I2C0_SCL_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_DSE_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_DSE_MASK)
65574#define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_3_4_MASK (0x18U)
65575#define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_3_4_SHIFT (3U)
65576/*! MIPI_CSI0_I2C0_SCL_reserved_3_4 - reserved
65577 */
65578#define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_3_4_MASK)
65579#define IOMUXD_MIPI_CSI0_I2C0_SCL_PULL_MASK (0x60U)
65580#define IOMUXD_MIPI_CSI0_I2C0_SCL_PULL_SHIFT (5U)
65581/*! PULL - Pull Down Pull Up
65582 * 0b00..Bus-Keeper
65583 * 0b10..pull down
65584 * 0b01..pull up
65585 * 0b11..No Pull
65586 */
65587#define IOMUXD_MIPI_CSI0_I2C0_SCL_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_PULL_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_PULL_MASK)
65588#define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_7_18_MASK (0x7FF80U)
65589#define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_7_18_SHIFT (7U)
65590/*! MIPI_CSI0_I2C0_SCL_reserved_7_18 - reserved
65591 */
65592#define IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL_reserved_7_18_MASK)
65593#define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_CTRL_MASK (0x380000U)
65594#define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_CTRL_SHIFT (19U)
65595/*! WAKEUP_CTRL - wakeup control
65596 * 0b000..OFF
65597 * 0b001..RESAMPLE
65598 * 0b100..LOW
65599 * 0b111..HIGH
65600 * 0b110..RISE
65601 * 0b101..FALL
65602 */
65603#define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_CTRL_MASK)
65604#define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_MASK_MASK (0x400000U)
65605#define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_MASK_SHIFT (22U)
65606/*! WAKEUP_MASK - wakeup mask
65607 */
65608#define IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_WAKEUP_MASK_MASK)
65609#define IOMUXD_MIPI_CSI0_I2C0_SCL_lp_config_MASK (0x1800000U)
65610#define IOMUXD_MIPI_CSI0_I2C0_SCL_lp_config_SHIFT (23U)
65611/*! lp_config - lower power configuration
65612 * 0b01..EARLY_ISO
65613 * 0b10..LATE_ISO
65614 * 0b11..LATCH
65615 * 0b00..PASS
65616 */
65617#define IOMUXD_MIPI_CSI0_I2C0_SCL_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_lp_config_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_lp_config_MASK)
65618#define IOMUXD_MIPI_CSI0_I2C0_SCL_sw_config_MASK (0x6000000U)
65619#define IOMUXD_MIPI_CSI0_I2C0_SCL_sw_config_SHIFT (25U)
65620/*! sw_config - output and input configuration
65621 * 0b01..OPEN_DRAIN
65622 * 0b10..OPEN_DRAIN_INPUT
65623 * 0b11..INOUT
65624 * 0b00..DEFAULT
65625 */
65626#define IOMUXD_MIPI_CSI0_I2C0_SCL_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_sw_config_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_sw_config_MASK)
65627#define IOMUXD_MIPI_CSI0_I2C0_SCL_mux_mode_MASK (0x38000000U)
65628#define IOMUXD_MIPI_CSI0_I2C0_SCL_mux_mode_SHIFT (27U)
65629/*! mux_mode - mux_mode
65630 * 0b000..MIPI_CSI0.I2C0.SCL
65631 * 0b001..MIPI_CSI0.GPIO0.IO02
65632 * 0b100..LSIO.GPIO3.IO05
65633 */
65634#define IOMUXD_MIPI_CSI0_I2C0_SCL_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_mux_mode_MASK)
65635#define IOMUXD_MIPI_CSI0_I2C0_SCL_update_pad_ctl_MASK (0x40000000U)
65636#define IOMUXD_MIPI_CSI0_I2C0_SCL_update_pad_ctl_SHIFT (30U)
65637/*! update_pad_ctl - update lock for pad control
65638 */
65639#define IOMUXD_MIPI_CSI0_I2C0_SCL_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_update_pad_ctl_MASK)
65640#define IOMUXD_MIPI_CSI0_I2C0_SCL_update_mux_mode_MASK (0x80000000U)
65641#define IOMUXD_MIPI_CSI0_I2C0_SCL_update_mux_mode_SHIFT (31U)
65642/*! update_mux_mode - update lock for mux control
65643 */
65644#define IOMUXD_MIPI_CSI0_I2C0_SCL_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SCL_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SCL_update_mux_mode_MASK)
65645/*! @} */
65646
65647/*! @name MIPI_CSI0_I2C0_SDA - MIPI_CSI0_I2C0_SDA */
65648/*! @{ */
65649#define IOMUXD_MIPI_CSI0_I2C0_SDA_DSE_MASK (0x7U)
65650#define IOMUXD_MIPI_CSI0_I2C0_SDA_DSE_SHIFT (0U)
65651/*! DSE - Drive
65652 * 0b001..Drive select 2mA
65653 * 0b011..Drive select 6mA
65654 * 0b111..High Speed
65655 * 0b110..Drive select 12mA
65656 * 0b010..Drive select 4mA
65657 * 0b100..Drive select 8mA
65658 * 0b000..Drive select 1mA
65659 * 0b101..Drive select 10mA
65660 */
65661#define IOMUXD_MIPI_CSI0_I2C0_SDA_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_DSE_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_DSE_MASK)
65662#define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_3_4_MASK (0x18U)
65663#define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_3_4_SHIFT (3U)
65664/*! MIPI_CSI0_I2C0_SDA_reserved_3_4 - reserved
65665 */
65666#define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_3_4_MASK)
65667#define IOMUXD_MIPI_CSI0_I2C0_SDA_PULL_MASK (0x60U)
65668#define IOMUXD_MIPI_CSI0_I2C0_SDA_PULL_SHIFT (5U)
65669/*! PULL - Pull Down Pull Up
65670 * 0b00..Bus-Keeper
65671 * 0b10..pull down
65672 * 0b01..pull up
65673 * 0b11..No Pull
65674 */
65675#define IOMUXD_MIPI_CSI0_I2C0_SDA_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_PULL_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_PULL_MASK)
65676#define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_7_18_MASK (0x7FF80U)
65677#define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_7_18_SHIFT (7U)
65678/*! MIPI_CSI0_I2C0_SDA_reserved_7_18 - reserved
65679 */
65680#define IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA_reserved_7_18_MASK)
65681#define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_CTRL_MASK (0x380000U)
65682#define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_CTRL_SHIFT (19U)
65683/*! WAKEUP_CTRL - wakeup control
65684 * 0b000..OFF
65685 * 0b001..RESAMPLE
65686 * 0b100..LOW
65687 * 0b111..HIGH
65688 * 0b110..RISE
65689 * 0b101..FALL
65690 */
65691#define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_CTRL_MASK)
65692#define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_MASK_MASK (0x400000U)
65693#define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_MASK_SHIFT (22U)
65694/*! WAKEUP_MASK - wakeup mask
65695 */
65696#define IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_WAKEUP_MASK_MASK)
65697#define IOMUXD_MIPI_CSI0_I2C0_SDA_lp_config_MASK (0x1800000U)
65698#define IOMUXD_MIPI_CSI0_I2C0_SDA_lp_config_SHIFT (23U)
65699/*! lp_config - lower power configuration
65700 * 0b01..EARLY_ISO
65701 * 0b10..LATE_ISO
65702 * 0b11..LATCH
65703 * 0b00..PASS
65704 */
65705#define IOMUXD_MIPI_CSI0_I2C0_SDA_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_lp_config_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_lp_config_MASK)
65706#define IOMUXD_MIPI_CSI0_I2C0_SDA_sw_config_MASK (0x6000000U)
65707#define IOMUXD_MIPI_CSI0_I2C0_SDA_sw_config_SHIFT (25U)
65708/*! sw_config - output and input configuration
65709 * 0b01..OPEN_DRAIN
65710 * 0b10..OPEN_DRAIN_INPUT
65711 * 0b11..INOUT
65712 * 0b00..DEFAULT
65713 */
65714#define IOMUXD_MIPI_CSI0_I2C0_SDA_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_sw_config_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_sw_config_MASK)
65715#define IOMUXD_MIPI_CSI0_I2C0_SDA_mux_mode_MASK (0x38000000U)
65716#define IOMUXD_MIPI_CSI0_I2C0_SDA_mux_mode_SHIFT (27U)
65717/*! mux_mode - mux_mode
65718 * 0b000..MIPI_CSI0.I2C0.SDA
65719 * 0b001..MIPI_CSI0.GPIO0.IO03
65720 * 0b100..LSIO.GPIO3.IO06
65721 */
65722#define IOMUXD_MIPI_CSI0_I2C0_SDA_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_mux_mode_MASK)
65723#define IOMUXD_MIPI_CSI0_I2C0_SDA_update_pad_ctl_MASK (0x40000000U)
65724#define IOMUXD_MIPI_CSI0_I2C0_SDA_update_pad_ctl_SHIFT (30U)
65725/*! update_pad_ctl - update lock for pad control
65726 */
65727#define IOMUXD_MIPI_CSI0_I2C0_SDA_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_update_pad_ctl_MASK)
65728#define IOMUXD_MIPI_CSI0_I2C0_SDA_update_mux_mode_MASK (0x80000000U)
65729#define IOMUXD_MIPI_CSI0_I2C0_SDA_update_mux_mode_SHIFT (31U)
65730/*! update_mux_mode - update lock for mux control
65731 */
65732#define IOMUXD_MIPI_CSI0_I2C0_SDA_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_I2C0_SDA_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_I2C0_SDA_update_mux_mode_MASK)
65733/*! @} */
65734
65735/*! @name MIPI_CSI0_GPIO0_01 - MIPI_CSI0_GPIO0_01 */
65736/*! @{ */
65737#define IOMUXD_MIPI_CSI0_GPIO0_01_DSE_MASK (0x7U)
65738#define IOMUXD_MIPI_CSI0_GPIO0_01_DSE_SHIFT (0U)
65739/*! DSE - Drive
65740 * 0b001..Drive select 2mA
65741 * 0b011..Drive select 6mA
65742 * 0b111..High Speed
65743 * 0b110..Drive select 12mA
65744 * 0b010..Drive select 4mA
65745 * 0b100..Drive select 8mA
65746 * 0b000..Drive select 1mA
65747 * 0b101..Drive select 10mA
65748 */
65749#define IOMUXD_MIPI_CSI0_GPIO0_01_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_DSE_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_DSE_MASK)
65750#define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_3_4_MASK (0x18U)
65751#define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_3_4_SHIFT (3U)
65752/*! MIPI_CSI0_GPIO0_01_reserved_3_4 - reserved
65753 */
65754#define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_3_4_MASK)
65755#define IOMUXD_MIPI_CSI0_GPIO0_01_PULL_MASK (0x60U)
65756#define IOMUXD_MIPI_CSI0_GPIO0_01_PULL_SHIFT (5U)
65757/*! PULL - Pull Down Pull Up
65758 * 0b00..Bus-Keeper
65759 * 0b10..pull down
65760 * 0b01..pull up
65761 * 0b11..No Pull
65762 */
65763#define IOMUXD_MIPI_CSI0_GPIO0_01_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_PULL_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_PULL_MASK)
65764#define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_7_18_MASK (0x7FF80U)
65765#define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_7_18_SHIFT (7U)
65766/*! MIPI_CSI0_GPIO0_01_reserved_7_18 - reserved
65767 */
65768#define IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_01_reserved_7_18_MASK)
65769#define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_CTRL_MASK (0x380000U)
65770#define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_CTRL_SHIFT (19U)
65771/*! WAKEUP_CTRL - wakeup control
65772 * 0b000..OFF
65773 * 0b001..RESAMPLE
65774 * 0b100..LOW
65775 * 0b111..HIGH
65776 * 0b110..RISE
65777 * 0b101..FALL
65778 */
65779#define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_CTRL_MASK)
65780#define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_MASK_MASK (0x400000U)
65781#define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_MASK_SHIFT (22U)
65782/*! WAKEUP_MASK - wakeup mask
65783 */
65784#define IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_WAKEUP_MASK_MASK)
65785#define IOMUXD_MIPI_CSI0_GPIO0_01_lp_config_MASK (0x1800000U)
65786#define IOMUXD_MIPI_CSI0_GPIO0_01_lp_config_SHIFT (23U)
65787/*! lp_config - lower power configuration
65788 * 0b01..EARLY_ISO
65789 * 0b10..LATE_ISO
65790 * 0b11..LATCH
65791 * 0b00..PASS
65792 */
65793#define IOMUXD_MIPI_CSI0_GPIO0_01_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_lp_config_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_lp_config_MASK)
65794#define IOMUXD_MIPI_CSI0_GPIO0_01_sw_config_MASK (0x6000000U)
65795#define IOMUXD_MIPI_CSI0_GPIO0_01_sw_config_SHIFT (25U)
65796/*! sw_config - output and input configuration
65797 * 0b01..OPEN_DRAIN
65798 * 0b10..OPEN_DRAIN_INPUT
65799 * 0b11..INOUT
65800 * 0b00..DEFAULT
65801 */
65802#define IOMUXD_MIPI_CSI0_GPIO0_01_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_sw_config_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_sw_config_MASK)
65803#define IOMUXD_MIPI_CSI0_GPIO0_01_mux_mode_MASK (0x38000000U)
65804#define IOMUXD_MIPI_CSI0_GPIO0_01_mux_mode_SHIFT (27U)
65805/*! mux_mode - mux_mode
65806 * 0b000..MIPI_CSI0.GPIO0.IO01
65807 * 0b001..ADMA.I2C0.SDA
65808 * 0b100..LSIO.GPIO3.IO07
65809 */
65810#define IOMUXD_MIPI_CSI0_GPIO0_01_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_mux_mode_MASK)
65811#define IOMUXD_MIPI_CSI0_GPIO0_01_update_pad_ctl_MASK (0x40000000U)
65812#define IOMUXD_MIPI_CSI0_GPIO0_01_update_pad_ctl_SHIFT (30U)
65813/*! update_pad_ctl - update lock for pad control
65814 */
65815#define IOMUXD_MIPI_CSI0_GPIO0_01_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_update_pad_ctl_MASK)
65816#define IOMUXD_MIPI_CSI0_GPIO0_01_update_mux_mode_MASK (0x80000000U)
65817#define IOMUXD_MIPI_CSI0_GPIO0_01_update_mux_mode_SHIFT (31U)
65818/*! update_mux_mode - update lock for mux control
65819 */
65820#define IOMUXD_MIPI_CSI0_GPIO0_01_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_01_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_01_update_mux_mode_MASK)
65821/*! @} */
65822
65823/*! @name MIPI_CSI0_GPIO0_00 - MIPI_CSI0_GPIO0_00 */
65824/*! @{ */
65825#define IOMUXD_MIPI_CSI0_GPIO0_00_DSE_MASK (0x7U)
65826#define IOMUXD_MIPI_CSI0_GPIO0_00_DSE_SHIFT (0U)
65827/*! DSE - Drive
65828 * 0b001..Drive select 2mA
65829 * 0b011..Drive select 6mA
65830 * 0b111..High Speed
65831 * 0b110..Drive select 12mA
65832 * 0b010..Drive select 4mA
65833 * 0b100..Drive select 8mA
65834 * 0b000..Drive select 1mA
65835 * 0b101..Drive select 10mA
65836 */
65837#define IOMUXD_MIPI_CSI0_GPIO0_00_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_DSE_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_DSE_MASK)
65838#define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_3_4_MASK (0x18U)
65839#define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_3_4_SHIFT (3U)
65840/*! MIPI_CSI0_GPIO0_00_reserved_3_4 - reserved
65841 */
65842#define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_3_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_3_4_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_3_4_MASK)
65843#define IOMUXD_MIPI_CSI0_GPIO0_00_PULL_MASK (0x60U)
65844#define IOMUXD_MIPI_CSI0_GPIO0_00_PULL_SHIFT (5U)
65845/*! PULL - Pull Down Pull Up
65846 * 0b00..Bus-Keeper
65847 * 0b10..pull down
65848 * 0b01..pull up
65849 * 0b11..No Pull
65850 */
65851#define IOMUXD_MIPI_CSI0_GPIO0_00_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_PULL_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_PULL_MASK)
65852#define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_7_18_MASK (0x7FF80U)
65853#define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_7_18_SHIFT (7U)
65854/*! MIPI_CSI0_GPIO0_00_reserved_7_18 - reserved
65855 */
65856#define IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_7_18_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_00_reserved_7_18_MASK)
65857#define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_CTRL_MASK (0x380000U)
65858#define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_CTRL_SHIFT (19U)
65859/*! WAKEUP_CTRL - wakeup control
65860 * 0b000..OFF
65861 * 0b001..RESAMPLE
65862 * 0b100..LOW
65863 * 0b111..HIGH
65864 * 0b110..RISE
65865 * 0b101..FALL
65866 */
65867#define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_CTRL_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_CTRL_MASK)
65868#define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_MASK_MASK (0x400000U)
65869#define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_MASK_SHIFT (22U)
65870/*! WAKEUP_MASK - wakeup mask
65871 */
65872#define IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_MASK_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_WAKEUP_MASK_MASK)
65873#define IOMUXD_MIPI_CSI0_GPIO0_00_lp_config_MASK (0x1800000U)
65874#define IOMUXD_MIPI_CSI0_GPIO0_00_lp_config_SHIFT (23U)
65875/*! lp_config - lower power configuration
65876 * 0b01..EARLY_ISO
65877 * 0b10..LATE_ISO
65878 * 0b11..LATCH
65879 * 0b00..PASS
65880 */
65881#define IOMUXD_MIPI_CSI0_GPIO0_00_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_lp_config_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_lp_config_MASK)
65882#define IOMUXD_MIPI_CSI0_GPIO0_00_sw_config_MASK (0x6000000U)
65883#define IOMUXD_MIPI_CSI0_GPIO0_00_sw_config_SHIFT (25U)
65884/*! sw_config - output and input configuration
65885 * 0b01..OPEN_DRAIN
65886 * 0b10..OPEN_DRAIN_INPUT
65887 * 0b11..INOUT
65888 * 0b00..DEFAULT
65889 */
65890#define IOMUXD_MIPI_CSI0_GPIO0_00_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_sw_config_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_sw_config_MASK)
65891#define IOMUXD_MIPI_CSI0_GPIO0_00_mux_mode_MASK (0x38000000U)
65892#define IOMUXD_MIPI_CSI0_GPIO0_00_mux_mode_SHIFT (27U)
65893/*! mux_mode - mux_mode
65894 * 0b000..MIPI_CSI0.GPIO0.IO00
65895 * 0b001..ADMA.I2C0.SCL
65896 * 0b100..LSIO.GPIO3.IO08
65897 */
65898#define IOMUXD_MIPI_CSI0_GPIO0_00_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_mux_mode_MASK)
65899#define IOMUXD_MIPI_CSI0_GPIO0_00_update_pad_ctl_MASK (0x40000000U)
65900#define IOMUXD_MIPI_CSI0_GPIO0_00_update_pad_ctl_SHIFT (30U)
65901/*! update_pad_ctl - update lock for pad control
65902 */
65903#define IOMUXD_MIPI_CSI0_GPIO0_00_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_update_pad_ctl_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_update_pad_ctl_MASK)
65904#define IOMUXD_MIPI_CSI0_GPIO0_00_update_mux_mode_MASK (0x80000000U)
65905#define IOMUXD_MIPI_CSI0_GPIO0_00_update_mux_mode_SHIFT (31U)
65906/*! update_mux_mode - update lock for mux control
65907 */
65908#define IOMUXD_MIPI_CSI0_GPIO0_00_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_MIPI_CSI0_GPIO0_00_update_mux_mode_SHIFT)) & IOMUXD_MIPI_CSI0_GPIO0_00_update_mux_mode_MASK)
65909/*! @} */
65910
65911/*! @name IOMUXD_GROUP_2_4 - na */
65912/*! @{ */
65913#define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D06_MASK (0x1U)
65914#define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D06_SHIFT (0U)
65915/*! CSI_DIG_D06 - wakeup from CSI_DIG_D06
65916 */
65917#define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D06(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D06_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D06_MASK)
65918#define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D07_MASK (0x2U)
65919#define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D07_SHIFT (1U)
65920/*! CSI_DIG_D07 - wakeup from CSI_DIG_D07
65921 */
65922#define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D07(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D07_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_D07_MASK)
65923#define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_HSYNC_MASK (0x4U)
65924#define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_HSYNC_SHIFT (2U)
65925/*! CSI_DIG_HSYNC - wakeup from CSI_DIG_HSYNC
65926 */
65927#define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_HSYNC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_HSYNC_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_HSYNC_MASK)
65928#define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_VSYNC_MASK (0x8U)
65929#define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_VSYNC_SHIFT (3U)
65930/*! CSI_DIG_VSYNC - wakeup from CSI_DIG_VSYNC
65931 */
65932#define IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_VSYNC_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_DIG_VSYNC_MASK)
65933#define IOMUXD_IOMUXD_GROUP_2_4_CSI_PCLK_MASK (0x10U)
65934#define IOMUXD_IOMUXD_GROUP_2_4_CSI_PCLK_SHIFT (4U)
65935/*! CSI_PCLK - wakeup from CSI_PCLK
65936 */
65937#define IOMUXD_IOMUXD_GROUP_2_4_CSI_PCLK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_PCLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_PCLK_MASK)
65938#define IOMUXD_IOMUXD_GROUP_2_4_CSI_MCLK_MASK (0x20U)
65939#define IOMUXD_IOMUXD_GROUP_2_4_CSI_MCLK_SHIFT (5U)
65940/*! CSI_MCLK - wakeup from CSI_MCLK
65941 */
65942#define IOMUXD_IOMUXD_GROUP_2_4_CSI_MCLK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_MCLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_MCLK_MASK)
65943#define IOMUXD_IOMUXD_GROUP_2_4_CSI_EN_MASK (0x40U)
65944#define IOMUXD_IOMUXD_GROUP_2_4_CSI_EN_SHIFT (6U)
65945/*! CSI_EN - wakeup from CSI_EN
65946 */
65947#define IOMUXD_IOMUXD_GROUP_2_4_CSI_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_EN_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_EN_MASK)
65948#define IOMUXD_IOMUXD_GROUP_2_4_CSI_RESET_MASK (0x80U)
65949#define IOMUXD_IOMUXD_GROUP_2_4_CSI_RESET_SHIFT (7U)
65950/*! CSI_RESET - wakeup from CSI_RESET
65951 */
65952#define IOMUXD_IOMUXD_GROUP_2_4_CSI_RESET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_CSI_RESET_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_CSI_RESET_MASK)
65953#define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_8_8_MASK (0x100U)
65954#define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_8_8_SHIFT (8U)
65955/*! iomuxd_group_2_4_reserved_8_8 - reserved
65956 */
65957#define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_8_8_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_8_8_MASK)
65958#define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_MCLK_OUT_MASK (0x200U)
65959#define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_MCLK_OUT_SHIFT (9U)
65960/*! MIPI_CSI0_MCLK_OUT - wakeup from MIPI_CSI0_MCLK_OUT
65961 */
65962#define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_MCLK_OUT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_MCLK_OUT_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_MCLK_OUT_MASK)
65963#define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SCL_MASK (0x400U)
65964#define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SCL_SHIFT (10U)
65965/*! MIPI_CSI0_I2C0_SCL - wakeup from MIPI_CSI0_I2C0_SCL
65966 */
65967#define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SCL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SCL_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SCL_MASK)
65968#define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SDA_MASK (0x800U)
65969#define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SDA_SHIFT (11U)
65970/*! MIPI_CSI0_I2C0_SDA - wakeup from MIPI_CSI0_I2C0_SDA
65971 */
65972#define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SDA(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SDA_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_I2C0_SDA_MASK)
65973#define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_01_MASK (0x1000U)
65974#define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_01_SHIFT (12U)
65975/*! MIPI_CSI0_GPIO0_01 - wakeup from MIPI_CSI0_GPIO0_01
65976 */
65977#define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_01(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_01_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_01_MASK)
65978#define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_00_MASK (0x2000U)
65979#define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_00_SHIFT (13U)
65980/*! MIPI_CSI0_GPIO0_00 - wakeup from MIPI_CSI0_GPIO0_00
65981 */
65982#define IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_00(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_00_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_MIPI_CSI0_GPIO0_00_MASK)
65983#define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_14_31_MASK (0xFFFFC000U)
65984#define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_14_31_SHIFT (14U)
65985/*! iomuxd_group_2_4_reserved_14_31 - reserved
65986 */
65987#define IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_14_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_14_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_2_4_iomuxd_group_2_4_reserved_14_31_MASK)
65988/*! @} */
65989
65990/*! @name QSPI0A_DATA0 - QSPI0A_DATA0 */
65991/*! @{ */
65992#define IOMUXD_QSPI0A_DATA0_PDRV_MASK (0x1U)
65993#define IOMUXD_QSPI0A_DATA0_PDRV_SHIFT (0U)
65994/*! PDRV - Drive
65995 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
65996 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
65997 */
65998#define IOMUXD_QSPI0A_DATA0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_PDRV_SHIFT)) & IOMUXD_QSPI0A_DATA0_PDRV_MASK)
65999#define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_1_4_MASK (0x1EU)
66000#define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_1_4_SHIFT (1U)
66001/*! QSPI0A_DATA0_reserved_1_4 - reserved
66002 */
66003#define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_1_4_MASK)
66004#define IOMUXD_QSPI0A_DATA0_PULL_MASK (0x60U)
66005#define IOMUXD_QSPI0A_DATA0_PULL_SHIFT (5U)
66006/*! PULL - Pull Down Pull Up
66007 * 0b10..pull down
66008 * 0b01..pull up
66009 * 0b00..Prohibited
66010 * 0b11..pull disabled
66011 */
66012#define IOMUXD_QSPI0A_DATA0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_PULL_SHIFT)) & IOMUXD_QSPI0A_DATA0_PULL_MASK)
66013#define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_7_18_MASK (0x7FF80U)
66014#define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_7_18_SHIFT (7U)
66015/*! QSPI0A_DATA0_reserved_7_18 - reserved
66016 */
66017#define IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_DATA0_QSPI0A_DATA0_reserved_7_18_MASK)
66018#define IOMUXD_QSPI0A_DATA0_WAKEUP_CTRL_MASK (0x380000U)
66019#define IOMUXD_QSPI0A_DATA0_WAKEUP_CTRL_SHIFT (19U)
66020/*! WAKEUP_CTRL - wakeup control
66021 * 0b000..OFF
66022 * 0b001..RESAMPLE
66023 * 0b100..LOW
66024 * 0b111..HIGH
66025 * 0b110..RISE
66026 * 0b101..FALL
66027 */
66028#define IOMUXD_QSPI0A_DATA0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_DATA0_WAKEUP_CTRL_MASK)
66029#define IOMUXD_QSPI0A_DATA0_WAKEUP_MASK_MASK (0x400000U)
66030#define IOMUXD_QSPI0A_DATA0_WAKEUP_MASK_SHIFT (22U)
66031/*! WAKEUP_MASK - wakeup mask
66032 */
66033#define IOMUXD_QSPI0A_DATA0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_DATA0_WAKEUP_MASK_MASK)
66034#define IOMUXD_QSPI0A_DATA0_lp_config_MASK (0x1800000U)
66035#define IOMUXD_QSPI0A_DATA0_lp_config_SHIFT (23U)
66036/*! lp_config - lower power configuration
66037 * 0b01..EARLY_ISO
66038 * 0b10..LATE_ISO
66039 * 0b11..LATCH
66040 * 0b00..PASS
66041 */
66042#define IOMUXD_QSPI0A_DATA0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_lp_config_SHIFT)) & IOMUXD_QSPI0A_DATA0_lp_config_MASK)
66043#define IOMUXD_QSPI0A_DATA0_sw_config_MASK (0x6000000U)
66044#define IOMUXD_QSPI0A_DATA0_sw_config_SHIFT (25U)
66045/*! sw_config - output and input configuration
66046 * 0b01..OPEN_DRAIN
66047 * 0b10..OPEN_DRAIN_INPUT
66048 * 0b11..INOUT
66049 * 0b00..DEFAULT
66050 */
66051#define IOMUXD_QSPI0A_DATA0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_sw_config_SHIFT)) & IOMUXD_QSPI0A_DATA0_sw_config_MASK)
66052#define IOMUXD_QSPI0A_DATA0_mux_mode_MASK (0x38000000U)
66053#define IOMUXD_QSPI0A_DATA0_mux_mode_SHIFT (27U)
66054/*! mux_mode - mux_mode
66055 * 0b000..LSIO.QSPI0A.DATA0
66056 * 0b100..LSIO.GPIO3.IO09
66057 */
66058#define IOMUXD_QSPI0A_DATA0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA0_mux_mode_MASK)
66059#define IOMUXD_QSPI0A_DATA0_update_pad_ctl_MASK (0x40000000U)
66060#define IOMUXD_QSPI0A_DATA0_update_pad_ctl_SHIFT (30U)
66061/*! update_pad_ctl - update lock for pad control
66062 */
66063#define IOMUXD_QSPI0A_DATA0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_DATA0_update_pad_ctl_MASK)
66064#define IOMUXD_QSPI0A_DATA0_update_mux_mode_MASK (0x80000000U)
66065#define IOMUXD_QSPI0A_DATA0_update_mux_mode_SHIFT (31U)
66066/*! update_mux_mode - update lock for mux control
66067 */
66068#define IOMUXD_QSPI0A_DATA0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA0_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA0_update_mux_mode_MASK)
66069/*! @} */
66070
66071/*! @name QSPI0A_DATA1 - QSPI0A_DATA1 */
66072/*! @{ */
66073#define IOMUXD_QSPI0A_DATA1_PDRV_MASK (0x1U)
66074#define IOMUXD_QSPI0A_DATA1_PDRV_SHIFT (0U)
66075/*! PDRV - Drive
66076 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
66077 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
66078 */
66079#define IOMUXD_QSPI0A_DATA1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_PDRV_SHIFT)) & IOMUXD_QSPI0A_DATA1_PDRV_MASK)
66080#define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_1_4_MASK (0x1EU)
66081#define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_1_4_SHIFT (1U)
66082/*! QSPI0A_DATA1_reserved_1_4 - reserved
66083 */
66084#define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_1_4_MASK)
66085#define IOMUXD_QSPI0A_DATA1_PULL_MASK (0x60U)
66086#define IOMUXD_QSPI0A_DATA1_PULL_SHIFT (5U)
66087/*! PULL - Pull Down Pull Up
66088 * 0b10..pull down
66089 * 0b01..pull up
66090 * 0b00..Prohibited
66091 * 0b11..pull disabled
66092 */
66093#define IOMUXD_QSPI0A_DATA1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_PULL_SHIFT)) & IOMUXD_QSPI0A_DATA1_PULL_MASK)
66094#define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_7_18_MASK (0x7FF80U)
66095#define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_7_18_SHIFT (7U)
66096/*! QSPI0A_DATA1_reserved_7_18 - reserved
66097 */
66098#define IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_DATA1_QSPI0A_DATA1_reserved_7_18_MASK)
66099#define IOMUXD_QSPI0A_DATA1_WAKEUP_CTRL_MASK (0x380000U)
66100#define IOMUXD_QSPI0A_DATA1_WAKEUP_CTRL_SHIFT (19U)
66101/*! WAKEUP_CTRL - wakeup control
66102 * 0b000..OFF
66103 * 0b001..RESAMPLE
66104 * 0b100..LOW
66105 * 0b111..HIGH
66106 * 0b110..RISE
66107 * 0b101..FALL
66108 */
66109#define IOMUXD_QSPI0A_DATA1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_DATA1_WAKEUP_CTRL_MASK)
66110#define IOMUXD_QSPI0A_DATA1_WAKEUP_MASK_MASK (0x400000U)
66111#define IOMUXD_QSPI0A_DATA1_WAKEUP_MASK_SHIFT (22U)
66112/*! WAKEUP_MASK - wakeup mask
66113 */
66114#define IOMUXD_QSPI0A_DATA1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_DATA1_WAKEUP_MASK_MASK)
66115#define IOMUXD_QSPI0A_DATA1_lp_config_MASK (0x1800000U)
66116#define IOMUXD_QSPI0A_DATA1_lp_config_SHIFT (23U)
66117/*! lp_config - lower power configuration
66118 * 0b01..EARLY_ISO
66119 * 0b10..LATE_ISO
66120 * 0b11..LATCH
66121 * 0b00..PASS
66122 */
66123#define IOMUXD_QSPI0A_DATA1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_lp_config_SHIFT)) & IOMUXD_QSPI0A_DATA1_lp_config_MASK)
66124#define IOMUXD_QSPI0A_DATA1_sw_config_MASK (0x6000000U)
66125#define IOMUXD_QSPI0A_DATA1_sw_config_SHIFT (25U)
66126/*! sw_config - output and input configuration
66127 * 0b01..OPEN_DRAIN
66128 * 0b10..OPEN_DRAIN_INPUT
66129 * 0b11..INOUT
66130 * 0b00..DEFAULT
66131 */
66132#define IOMUXD_QSPI0A_DATA1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_sw_config_SHIFT)) & IOMUXD_QSPI0A_DATA1_sw_config_MASK)
66133#define IOMUXD_QSPI0A_DATA1_mux_mode_MASK (0x38000000U)
66134#define IOMUXD_QSPI0A_DATA1_mux_mode_SHIFT (27U)
66135/*! mux_mode - mux_mode
66136 * 0b000..LSIO.QSPI0A.DATA1
66137 * 0b100..LSIO.GPIO3.IO10
66138 */
66139#define IOMUXD_QSPI0A_DATA1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA1_mux_mode_MASK)
66140#define IOMUXD_QSPI0A_DATA1_update_pad_ctl_MASK (0x40000000U)
66141#define IOMUXD_QSPI0A_DATA1_update_pad_ctl_SHIFT (30U)
66142/*! update_pad_ctl - update lock for pad control
66143 */
66144#define IOMUXD_QSPI0A_DATA1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_DATA1_update_pad_ctl_MASK)
66145#define IOMUXD_QSPI0A_DATA1_update_mux_mode_MASK (0x80000000U)
66146#define IOMUXD_QSPI0A_DATA1_update_mux_mode_SHIFT (31U)
66147/*! update_mux_mode - update lock for mux control
66148 */
66149#define IOMUXD_QSPI0A_DATA1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA1_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA1_update_mux_mode_MASK)
66150/*! @} */
66151
66152/*! @name QSPI0A_DATA2 - QSPI0A_DATA2 */
66153/*! @{ */
66154#define IOMUXD_QSPI0A_DATA2_PDRV_MASK (0x1U)
66155#define IOMUXD_QSPI0A_DATA2_PDRV_SHIFT (0U)
66156/*! PDRV - Drive
66157 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
66158 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
66159 */
66160#define IOMUXD_QSPI0A_DATA2_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_PDRV_SHIFT)) & IOMUXD_QSPI0A_DATA2_PDRV_MASK)
66161#define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_1_4_MASK (0x1EU)
66162#define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_1_4_SHIFT (1U)
66163/*! QSPI0A_DATA2_reserved_1_4 - reserved
66164 */
66165#define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_1_4_MASK)
66166#define IOMUXD_QSPI0A_DATA2_PULL_MASK (0x60U)
66167#define IOMUXD_QSPI0A_DATA2_PULL_SHIFT (5U)
66168/*! PULL - Pull Down Pull Up
66169 * 0b10..pull down
66170 * 0b01..pull up
66171 * 0b00..Prohibited
66172 * 0b11..pull disabled
66173 */
66174#define IOMUXD_QSPI0A_DATA2_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_PULL_SHIFT)) & IOMUXD_QSPI0A_DATA2_PULL_MASK)
66175#define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_7_18_MASK (0x7FF80U)
66176#define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_7_18_SHIFT (7U)
66177/*! QSPI0A_DATA2_reserved_7_18 - reserved
66178 */
66179#define IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_DATA2_QSPI0A_DATA2_reserved_7_18_MASK)
66180#define IOMUXD_QSPI0A_DATA2_WAKEUP_CTRL_MASK (0x380000U)
66181#define IOMUXD_QSPI0A_DATA2_WAKEUP_CTRL_SHIFT (19U)
66182/*! WAKEUP_CTRL - wakeup control
66183 * 0b000..OFF
66184 * 0b001..RESAMPLE
66185 * 0b100..LOW
66186 * 0b111..HIGH
66187 * 0b110..RISE
66188 * 0b101..FALL
66189 */
66190#define IOMUXD_QSPI0A_DATA2_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_DATA2_WAKEUP_CTRL_MASK)
66191#define IOMUXD_QSPI0A_DATA2_WAKEUP_MASK_MASK (0x400000U)
66192#define IOMUXD_QSPI0A_DATA2_WAKEUP_MASK_SHIFT (22U)
66193/*! WAKEUP_MASK - wakeup mask
66194 */
66195#define IOMUXD_QSPI0A_DATA2_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_DATA2_WAKEUP_MASK_MASK)
66196#define IOMUXD_QSPI0A_DATA2_lp_config_MASK (0x1800000U)
66197#define IOMUXD_QSPI0A_DATA2_lp_config_SHIFT (23U)
66198/*! lp_config - lower power configuration
66199 * 0b01..EARLY_ISO
66200 * 0b10..LATE_ISO
66201 * 0b11..LATCH
66202 * 0b00..PASS
66203 */
66204#define IOMUXD_QSPI0A_DATA2_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_lp_config_SHIFT)) & IOMUXD_QSPI0A_DATA2_lp_config_MASK)
66205#define IOMUXD_QSPI0A_DATA2_sw_config_MASK (0x6000000U)
66206#define IOMUXD_QSPI0A_DATA2_sw_config_SHIFT (25U)
66207/*! sw_config - output and input configuration
66208 * 0b01..OPEN_DRAIN
66209 * 0b10..OPEN_DRAIN_INPUT
66210 * 0b11..INOUT
66211 * 0b00..DEFAULT
66212 */
66213#define IOMUXD_QSPI0A_DATA2_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_sw_config_SHIFT)) & IOMUXD_QSPI0A_DATA2_sw_config_MASK)
66214#define IOMUXD_QSPI0A_DATA2_mux_mode_MASK (0x38000000U)
66215#define IOMUXD_QSPI0A_DATA2_mux_mode_SHIFT (27U)
66216/*! mux_mode - mux_mode
66217 * 0b000..LSIO.QSPI0A.DATA2
66218 * 0b100..LSIO.GPIO3.IO11
66219 */
66220#define IOMUXD_QSPI0A_DATA2_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA2_mux_mode_MASK)
66221#define IOMUXD_QSPI0A_DATA2_update_pad_ctl_MASK (0x40000000U)
66222#define IOMUXD_QSPI0A_DATA2_update_pad_ctl_SHIFT (30U)
66223/*! update_pad_ctl - update lock for pad control
66224 */
66225#define IOMUXD_QSPI0A_DATA2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_DATA2_update_pad_ctl_MASK)
66226#define IOMUXD_QSPI0A_DATA2_update_mux_mode_MASK (0x80000000U)
66227#define IOMUXD_QSPI0A_DATA2_update_mux_mode_SHIFT (31U)
66228/*! update_mux_mode - update lock for mux control
66229 */
66230#define IOMUXD_QSPI0A_DATA2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA2_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA2_update_mux_mode_MASK)
66231/*! @} */
66232
66233/*! @name QSPI0A_DATA3 - QSPI0A_DATA3 */
66234/*! @{ */
66235#define IOMUXD_QSPI0A_DATA3_PDRV_MASK (0x1U)
66236#define IOMUXD_QSPI0A_DATA3_PDRV_SHIFT (0U)
66237/*! PDRV - Drive
66238 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
66239 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
66240 */
66241#define IOMUXD_QSPI0A_DATA3_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_PDRV_SHIFT)) & IOMUXD_QSPI0A_DATA3_PDRV_MASK)
66242#define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_1_4_MASK (0x1EU)
66243#define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_1_4_SHIFT (1U)
66244/*! QSPI0A_DATA3_reserved_1_4 - reserved
66245 */
66246#define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_1_4_MASK)
66247#define IOMUXD_QSPI0A_DATA3_PULL_MASK (0x60U)
66248#define IOMUXD_QSPI0A_DATA3_PULL_SHIFT (5U)
66249/*! PULL - Pull Down Pull Up
66250 * 0b10..pull down
66251 * 0b01..pull up
66252 * 0b00..Prohibited
66253 * 0b11..pull disabled
66254 */
66255#define IOMUXD_QSPI0A_DATA3_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_PULL_SHIFT)) & IOMUXD_QSPI0A_DATA3_PULL_MASK)
66256#define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_7_18_MASK (0x7FF80U)
66257#define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_7_18_SHIFT (7U)
66258/*! QSPI0A_DATA3_reserved_7_18 - reserved
66259 */
66260#define IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_DATA3_QSPI0A_DATA3_reserved_7_18_MASK)
66261#define IOMUXD_QSPI0A_DATA3_WAKEUP_CTRL_MASK (0x380000U)
66262#define IOMUXD_QSPI0A_DATA3_WAKEUP_CTRL_SHIFT (19U)
66263/*! WAKEUP_CTRL - wakeup control
66264 * 0b000..OFF
66265 * 0b001..RESAMPLE
66266 * 0b100..LOW
66267 * 0b111..HIGH
66268 * 0b110..RISE
66269 * 0b101..FALL
66270 */
66271#define IOMUXD_QSPI0A_DATA3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_DATA3_WAKEUP_CTRL_MASK)
66272#define IOMUXD_QSPI0A_DATA3_WAKEUP_MASK_MASK (0x400000U)
66273#define IOMUXD_QSPI0A_DATA3_WAKEUP_MASK_SHIFT (22U)
66274/*! WAKEUP_MASK - wakeup mask
66275 */
66276#define IOMUXD_QSPI0A_DATA3_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_DATA3_WAKEUP_MASK_MASK)
66277#define IOMUXD_QSPI0A_DATA3_lp_config_MASK (0x1800000U)
66278#define IOMUXD_QSPI0A_DATA3_lp_config_SHIFT (23U)
66279/*! lp_config - lower power configuration
66280 * 0b01..EARLY_ISO
66281 * 0b10..LATE_ISO
66282 * 0b11..LATCH
66283 * 0b00..PASS
66284 */
66285#define IOMUXD_QSPI0A_DATA3_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_lp_config_SHIFT)) & IOMUXD_QSPI0A_DATA3_lp_config_MASK)
66286#define IOMUXD_QSPI0A_DATA3_sw_config_MASK (0x6000000U)
66287#define IOMUXD_QSPI0A_DATA3_sw_config_SHIFT (25U)
66288/*! sw_config - output and input configuration
66289 * 0b01..OPEN_DRAIN
66290 * 0b10..OPEN_DRAIN_INPUT
66291 * 0b11..INOUT
66292 * 0b00..DEFAULT
66293 */
66294#define IOMUXD_QSPI0A_DATA3_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_sw_config_SHIFT)) & IOMUXD_QSPI0A_DATA3_sw_config_MASK)
66295#define IOMUXD_QSPI0A_DATA3_mux_mode_MASK (0x38000000U)
66296#define IOMUXD_QSPI0A_DATA3_mux_mode_SHIFT (27U)
66297/*! mux_mode - mux_mode
66298 * 0b000..LSIO.QSPI0A.DATA3
66299 * 0b100..LSIO.GPIO3.IO12
66300 */
66301#define IOMUXD_QSPI0A_DATA3_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA3_mux_mode_MASK)
66302#define IOMUXD_QSPI0A_DATA3_update_pad_ctl_MASK (0x40000000U)
66303#define IOMUXD_QSPI0A_DATA3_update_pad_ctl_SHIFT (30U)
66304/*! update_pad_ctl - update lock for pad control
66305 */
66306#define IOMUXD_QSPI0A_DATA3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_DATA3_update_pad_ctl_MASK)
66307#define IOMUXD_QSPI0A_DATA3_update_mux_mode_MASK (0x80000000U)
66308#define IOMUXD_QSPI0A_DATA3_update_mux_mode_SHIFT (31U)
66309/*! update_mux_mode - update lock for mux control
66310 */
66311#define IOMUXD_QSPI0A_DATA3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DATA3_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DATA3_update_mux_mode_MASK)
66312/*! @} */
66313
66314/*! @name QSPI0A_DQS - QSPI0A_DQS */
66315/*! @{ */
66316#define IOMUXD_QSPI0A_DQS_PDRV_MASK (0x1U)
66317#define IOMUXD_QSPI0A_DQS_PDRV_SHIFT (0U)
66318/*! PDRV - Drive
66319 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
66320 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
66321 */
66322#define IOMUXD_QSPI0A_DQS_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_PDRV_SHIFT)) & IOMUXD_QSPI0A_DQS_PDRV_MASK)
66323#define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_1_4_MASK (0x1EU)
66324#define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_1_4_SHIFT (1U)
66325/*! QSPI0A_DQS_reserved_1_4 - reserved
66326 */
66327#define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_1_4_MASK)
66328#define IOMUXD_QSPI0A_DQS_PULL_MASK (0x60U)
66329#define IOMUXD_QSPI0A_DQS_PULL_SHIFT (5U)
66330/*! PULL - Pull Down Pull Up
66331 * 0b10..pull down
66332 * 0b01..pull up
66333 * 0b00..Prohibited
66334 * 0b11..pull disabled
66335 */
66336#define IOMUXD_QSPI0A_DQS_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_PULL_SHIFT)) & IOMUXD_QSPI0A_DQS_PULL_MASK)
66337#define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_7_18_MASK (0x7FF80U)
66338#define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_7_18_SHIFT (7U)
66339/*! QSPI0A_DQS_reserved_7_18 - reserved
66340 */
66341#define IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_DQS_QSPI0A_DQS_reserved_7_18_MASK)
66342#define IOMUXD_QSPI0A_DQS_WAKEUP_CTRL_MASK (0x380000U)
66343#define IOMUXD_QSPI0A_DQS_WAKEUP_CTRL_SHIFT (19U)
66344/*! WAKEUP_CTRL - wakeup control
66345 * 0b000..OFF
66346 * 0b001..RESAMPLE
66347 * 0b100..LOW
66348 * 0b111..HIGH
66349 * 0b110..RISE
66350 * 0b101..FALL
66351 */
66352#define IOMUXD_QSPI0A_DQS_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_DQS_WAKEUP_CTRL_MASK)
66353#define IOMUXD_QSPI0A_DQS_WAKEUP_MASK_MASK (0x400000U)
66354#define IOMUXD_QSPI0A_DQS_WAKEUP_MASK_SHIFT (22U)
66355/*! WAKEUP_MASK - wakeup mask
66356 */
66357#define IOMUXD_QSPI0A_DQS_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_DQS_WAKEUP_MASK_MASK)
66358#define IOMUXD_QSPI0A_DQS_lp_config_MASK (0x1800000U)
66359#define IOMUXD_QSPI0A_DQS_lp_config_SHIFT (23U)
66360/*! lp_config - lower power configuration
66361 * 0b01..EARLY_ISO
66362 * 0b10..LATE_ISO
66363 * 0b11..LATCH
66364 * 0b00..PASS
66365 */
66366#define IOMUXD_QSPI0A_DQS_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_lp_config_SHIFT)) & IOMUXD_QSPI0A_DQS_lp_config_MASK)
66367#define IOMUXD_QSPI0A_DQS_sw_config_MASK (0x6000000U)
66368#define IOMUXD_QSPI0A_DQS_sw_config_SHIFT (25U)
66369/*! sw_config - output and input configuration
66370 * 0b01..OPEN_DRAIN
66371 * 0b10..OPEN_DRAIN_INPUT
66372 * 0b11..INOUT
66373 * 0b00..DEFAULT
66374 */
66375#define IOMUXD_QSPI0A_DQS_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_sw_config_SHIFT)) & IOMUXD_QSPI0A_DQS_sw_config_MASK)
66376#define IOMUXD_QSPI0A_DQS_mux_mode_MASK (0x38000000U)
66377#define IOMUXD_QSPI0A_DQS_mux_mode_SHIFT (27U)
66378/*! mux_mode - mux_mode
66379 * 0b000..LSIO.QSPI0A.DQS
66380 * 0b100..LSIO.GPIO3.IO13
66381 */
66382#define IOMUXD_QSPI0A_DQS_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DQS_mux_mode_MASK)
66383#define IOMUXD_QSPI0A_DQS_update_pad_ctl_MASK (0x40000000U)
66384#define IOMUXD_QSPI0A_DQS_update_pad_ctl_SHIFT (30U)
66385/*! update_pad_ctl - update lock for pad control
66386 */
66387#define IOMUXD_QSPI0A_DQS_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_DQS_update_pad_ctl_MASK)
66388#define IOMUXD_QSPI0A_DQS_update_mux_mode_MASK (0x80000000U)
66389#define IOMUXD_QSPI0A_DQS_update_mux_mode_SHIFT (31U)
66390/*! update_mux_mode - update lock for mux control
66391 */
66392#define IOMUXD_QSPI0A_DQS_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_DQS_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_DQS_update_mux_mode_MASK)
66393/*! @} */
66394
66395/*! @name QSPI0A_SS0_B - QSPI0A_SS0_B */
66396/*! @{ */
66397#define IOMUXD_QSPI0A_SS0_B_PDRV_MASK (0x1U)
66398#define IOMUXD_QSPI0A_SS0_B_PDRV_SHIFT (0U)
66399/*! PDRV - Drive
66400 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
66401 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
66402 */
66403#define IOMUXD_QSPI0A_SS0_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_PDRV_SHIFT)) & IOMUXD_QSPI0A_SS0_B_PDRV_MASK)
66404#define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_1_4_MASK (0x1EU)
66405#define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_1_4_SHIFT (1U)
66406/*! QSPI0A_SS0_B_reserved_1_4 - reserved
66407 */
66408#define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_1_4_MASK)
66409#define IOMUXD_QSPI0A_SS0_B_PULL_MASK (0x60U)
66410#define IOMUXD_QSPI0A_SS0_B_PULL_SHIFT (5U)
66411/*! PULL - Pull Down Pull Up
66412 * 0b10..pull down
66413 * 0b01..pull up
66414 * 0b00..Prohibited
66415 * 0b11..pull disabled
66416 */
66417#define IOMUXD_QSPI0A_SS0_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_PULL_SHIFT)) & IOMUXD_QSPI0A_SS0_B_PULL_MASK)
66418#define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_7_18_MASK (0x7FF80U)
66419#define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_7_18_SHIFT (7U)
66420/*! QSPI0A_SS0_B_reserved_7_18 - reserved
66421 */
66422#define IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_SS0_B_QSPI0A_SS0_B_reserved_7_18_MASK)
66423#define IOMUXD_QSPI0A_SS0_B_WAKEUP_CTRL_MASK (0x380000U)
66424#define IOMUXD_QSPI0A_SS0_B_WAKEUP_CTRL_SHIFT (19U)
66425/*! WAKEUP_CTRL - wakeup control
66426 * 0b000..OFF
66427 * 0b001..RESAMPLE
66428 * 0b100..LOW
66429 * 0b111..HIGH
66430 * 0b110..RISE
66431 * 0b101..FALL
66432 */
66433#define IOMUXD_QSPI0A_SS0_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_SS0_B_WAKEUP_CTRL_MASK)
66434#define IOMUXD_QSPI0A_SS0_B_WAKEUP_MASK_MASK (0x400000U)
66435#define IOMUXD_QSPI0A_SS0_B_WAKEUP_MASK_SHIFT (22U)
66436/*! WAKEUP_MASK - wakeup mask
66437 */
66438#define IOMUXD_QSPI0A_SS0_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_SS0_B_WAKEUP_MASK_MASK)
66439#define IOMUXD_QSPI0A_SS0_B_lp_config_MASK (0x1800000U)
66440#define IOMUXD_QSPI0A_SS0_B_lp_config_SHIFT (23U)
66441/*! lp_config - lower power configuration
66442 * 0b01..EARLY_ISO
66443 * 0b10..LATE_ISO
66444 * 0b11..LATCH
66445 * 0b00..PASS
66446 */
66447#define IOMUXD_QSPI0A_SS0_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_lp_config_SHIFT)) & IOMUXD_QSPI0A_SS0_B_lp_config_MASK)
66448#define IOMUXD_QSPI0A_SS0_B_sw_config_MASK (0x6000000U)
66449#define IOMUXD_QSPI0A_SS0_B_sw_config_SHIFT (25U)
66450/*! sw_config - output and input configuration
66451 * 0b01..OPEN_DRAIN
66452 * 0b10..OPEN_DRAIN_INPUT
66453 * 0b11..INOUT
66454 * 0b00..DEFAULT
66455 */
66456#define IOMUXD_QSPI0A_SS0_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_sw_config_SHIFT)) & IOMUXD_QSPI0A_SS0_B_sw_config_MASK)
66457#define IOMUXD_QSPI0A_SS0_B_mux_mode_MASK (0x38000000U)
66458#define IOMUXD_QSPI0A_SS0_B_mux_mode_SHIFT (27U)
66459/*! mux_mode - mux_mode
66460 * 0b000..LSIO.QSPI0A.SS0_B
66461 * 0b100..LSIO.GPIO3.IO14
66462 */
66463#define IOMUXD_QSPI0A_SS0_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SS0_B_mux_mode_MASK)
66464#define IOMUXD_QSPI0A_SS0_B_update_pad_ctl_MASK (0x40000000U)
66465#define IOMUXD_QSPI0A_SS0_B_update_pad_ctl_SHIFT (30U)
66466/*! update_pad_ctl - update lock for pad control
66467 */
66468#define IOMUXD_QSPI0A_SS0_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_SS0_B_update_pad_ctl_MASK)
66469#define IOMUXD_QSPI0A_SS0_B_update_mux_mode_MASK (0x80000000U)
66470#define IOMUXD_QSPI0A_SS0_B_update_mux_mode_SHIFT (31U)
66471/*! update_mux_mode - update lock for mux control
66472 */
66473#define IOMUXD_QSPI0A_SS0_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS0_B_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SS0_B_update_mux_mode_MASK)
66474/*! @} */
66475
66476/*! @name QSPI0A_SS1_B - QSPI0A_SS1_B */
66477/*! @{ */
66478#define IOMUXD_QSPI0A_SS1_B_PDRV_MASK (0x1U)
66479#define IOMUXD_QSPI0A_SS1_B_PDRV_SHIFT (0U)
66480/*! PDRV - Drive
66481 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
66482 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
66483 */
66484#define IOMUXD_QSPI0A_SS1_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_PDRV_SHIFT)) & IOMUXD_QSPI0A_SS1_B_PDRV_MASK)
66485#define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_1_4_MASK (0x1EU)
66486#define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_1_4_SHIFT (1U)
66487/*! QSPI0A_SS1_B_reserved_1_4 - reserved
66488 */
66489#define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_1_4_MASK)
66490#define IOMUXD_QSPI0A_SS1_B_PULL_MASK (0x60U)
66491#define IOMUXD_QSPI0A_SS1_B_PULL_SHIFT (5U)
66492/*! PULL - Pull Down Pull Up
66493 * 0b10..pull down
66494 * 0b01..pull up
66495 * 0b00..Prohibited
66496 * 0b11..pull disabled
66497 */
66498#define IOMUXD_QSPI0A_SS1_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_PULL_SHIFT)) & IOMUXD_QSPI0A_SS1_B_PULL_MASK)
66499#define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_7_18_MASK (0x7FF80U)
66500#define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_7_18_SHIFT (7U)
66501/*! QSPI0A_SS1_B_reserved_7_18 - reserved
66502 */
66503#define IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_SS1_B_QSPI0A_SS1_B_reserved_7_18_MASK)
66504#define IOMUXD_QSPI0A_SS1_B_WAKEUP_CTRL_MASK (0x380000U)
66505#define IOMUXD_QSPI0A_SS1_B_WAKEUP_CTRL_SHIFT (19U)
66506/*! WAKEUP_CTRL - wakeup control
66507 * 0b000..OFF
66508 * 0b001..RESAMPLE
66509 * 0b100..LOW
66510 * 0b111..HIGH
66511 * 0b110..RISE
66512 * 0b101..FALL
66513 */
66514#define IOMUXD_QSPI0A_SS1_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_SS1_B_WAKEUP_CTRL_MASK)
66515#define IOMUXD_QSPI0A_SS1_B_WAKEUP_MASK_MASK (0x400000U)
66516#define IOMUXD_QSPI0A_SS1_B_WAKEUP_MASK_SHIFT (22U)
66517/*! WAKEUP_MASK - wakeup mask
66518 */
66519#define IOMUXD_QSPI0A_SS1_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_SS1_B_WAKEUP_MASK_MASK)
66520#define IOMUXD_QSPI0A_SS1_B_lp_config_MASK (0x1800000U)
66521#define IOMUXD_QSPI0A_SS1_B_lp_config_SHIFT (23U)
66522/*! lp_config - lower power configuration
66523 * 0b01..EARLY_ISO
66524 * 0b10..LATE_ISO
66525 * 0b11..LATCH
66526 * 0b00..PASS
66527 */
66528#define IOMUXD_QSPI0A_SS1_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_lp_config_SHIFT)) & IOMUXD_QSPI0A_SS1_B_lp_config_MASK)
66529#define IOMUXD_QSPI0A_SS1_B_sw_config_MASK (0x6000000U)
66530#define IOMUXD_QSPI0A_SS1_B_sw_config_SHIFT (25U)
66531/*! sw_config - output and input configuration
66532 * 0b01..OPEN_DRAIN
66533 * 0b10..OPEN_DRAIN_INPUT
66534 * 0b11..INOUT
66535 * 0b00..DEFAULT
66536 */
66537#define IOMUXD_QSPI0A_SS1_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_sw_config_SHIFT)) & IOMUXD_QSPI0A_SS1_B_sw_config_MASK)
66538#define IOMUXD_QSPI0A_SS1_B_mux_mode_MASK (0x38000000U)
66539#define IOMUXD_QSPI0A_SS1_B_mux_mode_SHIFT (27U)
66540/*! mux_mode - mux_mode
66541 * 0b000..LSIO.QSPI0A.SS1_B
66542 * 0b100..LSIO.GPIO3.IO15
66543 */
66544#define IOMUXD_QSPI0A_SS1_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SS1_B_mux_mode_MASK)
66545#define IOMUXD_QSPI0A_SS1_B_update_pad_ctl_MASK (0x40000000U)
66546#define IOMUXD_QSPI0A_SS1_B_update_pad_ctl_SHIFT (30U)
66547/*! update_pad_ctl - update lock for pad control
66548 */
66549#define IOMUXD_QSPI0A_SS1_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_SS1_B_update_pad_ctl_MASK)
66550#define IOMUXD_QSPI0A_SS1_B_update_mux_mode_MASK (0x80000000U)
66551#define IOMUXD_QSPI0A_SS1_B_update_mux_mode_SHIFT (31U)
66552/*! update_mux_mode - update lock for mux control
66553 */
66554#define IOMUXD_QSPI0A_SS1_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SS1_B_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SS1_B_update_mux_mode_MASK)
66555/*! @} */
66556
66557/*! @name QSPI0A_SCLK - QSPI0A_SCLK */
66558/*! @{ */
66559#define IOMUXD_QSPI0A_SCLK_PDRV_MASK (0x1U)
66560#define IOMUXD_QSPI0A_SCLK_PDRV_SHIFT (0U)
66561/*! PDRV - Drive
66562 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
66563 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
66564 */
66565#define IOMUXD_QSPI0A_SCLK_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_PDRV_SHIFT)) & IOMUXD_QSPI0A_SCLK_PDRV_MASK)
66566#define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_1_4_MASK (0x1EU)
66567#define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_1_4_SHIFT (1U)
66568/*! QSPI0A_SCLK_reserved_1_4 - reserved
66569 */
66570#define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_1_4_SHIFT)) & IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_1_4_MASK)
66571#define IOMUXD_QSPI0A_SCLK_PULL_MASK (0x60U)
66572#define IOMUXD_QSPI0A_SCLK_PULL_SHIFT (5U)
66573/*! PULL - Pull Down Pull Up
66574 * 0b10..pull down
66575 * 0b01..pull up
66576 * 0b00..Prohibited
66577 * 0b11..pull disabled
66578 */
66579#define IOMUXD_QSPI0A_SCLK_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_PULL_SHIFT)) & IOMUXD_QSPI0A_SCLK_PULL_MASK)
66580#define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_7_18_MASK (0x7FF80U)
66581#define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_7_18_SHIFT (7U)
66582/*! QSPI0A_SCLK_reserved_7_18 - reserved
66583 */
66584#define IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_7_18_SHIFT)) & IOMUXD_QSPI0A_SCLK_QSPI0A_SCLK_reserved_7_18_MASK)
66585#define IOMUXD_QSPI0A_SCLK_WAKEUP_CTRL_MASK (0x380000U)
66586#define IOMUXD_QSPI0A_SCLK_WAKEUP_CTRL_SHIFT (19U)
66587/*! WAKEUP_CTRL - wakeup control
66588 * 0b000..OFF
66589 * 0b001..RESAMPLE
66590 * 0b100..LOW
66591 * 0b111..HIGH
66592 * 0b110..RISE
66593 * 0b101..FALL
66594 */
66595#define IOMUXD_QSPI0A_SCLK_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0A_SCLK_WAKEUP_CTRL_MASK)
66596#define IOMUXD_QSPI0A_SCLK_WAKEUP_MASK_MASK (0x400000U)
66597#define IOMUXD_QSPI0A_SCLK_WAKEUP_MASK_SHIFT (22U)
66598/*! WAKEUP_MASK - wakeup mask
66599 */
66600#define IOMUXD_QSPI0A_SCLK_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0A_SCLK_WAKEUP_MASK_MASK)
66601#define IOMUXD_QSPI0A_SCLK_lp_config_MASK (0x1800000U)
66602#define IOMUXD_QSPI0A_SCLK_lp_config_SHIFT (23U)
66603/*! lp_config - lower power configuration
66604 * 0b01..EARLY_ISO
66605 * 0b10..LATE_ISO
66606 * 0b11..LATCH
66607 * 0b00..PASS
66608 */
66609#define IOMUXD_QSPI0A_SCLK_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_lp_config_SHIFT)) & IOMUXD_QSPI0A_SCLK_lp_config_MASK)
66610#define IOMUXD_QSPI0A_SCLK_sw_config_MASK (0x6000000U)
66611#define IOMUXD_QSPI0A_SCLK_sw_config_SHIFT (25U)
66612/*! sw_config - output and input configuration
66613 * 0b01..OPEN_DRAIN
66614 * 0b10..OPEN_DRAIN_INPUT
66615 * 0b11..INOUT
66616 * 0b00..DEFAULT
66617 */
66618#define IOMUXD_QSPI0A_SCLK_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_sw_config_SHIFT)) & IOMUXD_QSPI0A_SCLK_sw_config_MASK)
66619#define IOMUXD_QSPI0A_SCLK_mux_mode_MASK (0x38000000U)
66620#define IOMUXD_QSPI0A_SCLK_mux_mode_SHIFT (27U)
66621/*! mux_mode - mux_mode
66622 * 0b000..LSIO.QSPI0A.SCLK
66623 * 0b100..LSIO.GPIO3.IO16
66624 */
66625#define IOMUXD_QSPI0A_SCLK_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SCLK_mux_mode_MASK)
66626#define IOMUXD_QSPI0A_SCLK_update_pad_ctl_MASK (0x40000000U)
66627#define IOMUXD_QSPI0A_SCLK_update_pad_ctl_SHIFT (30U)
66628/*! update_pad_ctl - update lock for pad control
66629 */
66630#define IOMUXD_QSPI0A_SCLK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0A_SCLK_update_pad_ctl_MASK)
66631#define IOMUXD_QSPI0A_SCLK_update_mux_mode_MASK (0x80000000U)
66632#define IOMUXD_QSPI0A_SCLK_update_mux_mode_SHIFT (31U)
66633/*! update_mux_mode - update lock for mux control
66634 */
66635#define IOMUXD_QSPI0A_SCLK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0A_SCLK_update_mux_mode_SHIFT)) & IOMUXD_QSPI0A_SCLK_update_mux_mode_MASK)
66636/*! @} */
66637
66638/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A - IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A */
66639/*! @{ */
66640#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMP_MASK (0x7U)
66641#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMP_SHIFT (0U)
66642/*! COMP - COMP
66643 * 0b010..Fixed code mode
66644 * 0b100..High impedance mode
66645 * 0b110..Read mode
66646 * 0b000..Normal Mode
66647 * 0b001..Freeze Mode
66648 */
66649#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMP_MASK)
66650#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_FASTFRZ_EN_MASK (0x8U)
66651#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_FASTFRZ_EN_SHIFT (3U)
66652/*! FASTFRZ_EN - FASTFRZ_EN
66653 * 0b1..FASTFRZ signal is driven by output of subsystem
66654 * 0b0..FASTFRZ signal is gated to 0
66655 */
66656#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_FASTFRZ_EN_MASK)
66657#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_4_4_MASK (0x10U)
66658#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_4_4_SHIFT (4U)
66659/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_4_4 - reserved
66660 */
66661#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_4_4_MASK)
66662#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCP_MASK (0x1E0U)
66663#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCP_SHIFT (5U)
66664/*! RASRCP - RASRCP
66665 * 0b0101..Reset Value
66666 */
66667#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCP_MASK)
66668#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCN_MASK (0x1E00U)
66669#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCN_SHIFT (9U)
66670/*! RASRCN - RASRCN
66671 * 0b1010..Reset Value
66672 */
66673#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_RASRCN_MASK)
66674#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SELECT_NASRC_MASK (0x2000U)
66675#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SELECT_NASRC_SHIFT (13U)
66676/*! SELECT_NASRC - SELECT_NASRC
66677 * 0b1..NASRCN value
66678 * 0b0..NASRCP value
66679 */
66680#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SELECT_NASRC_MASK)
66681#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMPOK_MASK (0x4000U)
66682#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMPOK_SHIFT (14U)
66683/*! COMPOK - COMPOK
66684 * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
66685 * 0b1..compensation cell in Normal mode and tracking PVT
66686 */
66687#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_COMPOK_MASK)
66688#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_READ_NASRC_MASK (0x78000U)
66689#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_READ_NASRC_SHIFT (15U)
66690/*! READ_NASRC - READ_NASRC
66691 * 0b0000..READ Only
66692 */
66693#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_READ_NASRC_MASK)
66694#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_19_22_MASK (0x780000U)
66695#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_19_22_SHIFT (19U)
66696/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_19_22 - reserved
66697 */
66698#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_19_22_MASK)
66699#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SLEEP_MASK (0x1800000U)
66700#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SLEEP_SHIFT (23U)
66701/*! SLEEP - SLEEP
66702 * 0b11..Force into sleep mode
66703 * 0b00..NO
66704 * 0b01..EARLY
66705 * 0b10..LATE
66706 */
66707#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_SLEEP_MASK)
66708#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_25_29_MASK (0x3E000000U)
66709#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_25_29_SHIFT (25U)
66710/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_25_29 - reserved
66711 */
66712#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_reserved_25_29_MASK)
66713#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_pad_ctl_MASK (0x40000000U)
66714#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_pad_ctl_SHIFT (30U)
66715/*! update_pad_ctl - update lock for pad control
66716 */
66717#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_pad_ctl_MASK)
66718#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_mux_mode_MASK (0x80000000U)
66719#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_mux_mode_SHIFT (31U)
66720/*! update_mux_mode - update lock for mux control
66721 */
66722#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0A_update_mux_mode_MASK)
66723/*! @} */
66724
66725/*! @name QSPI0B_SCLK - QSPI0B_SCLK */
66726/*! @{ */
66727#define IOMUXD_QSPI0B_SCLK_PDRV_MASK (0x1U)
66728#define IOMUXD_QSPI0B_SCLK_PDRV_SHIFT (0U)
66729/*! PDRV - Drive
66730 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
66731 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
66732 */
66733#define IOMUXD_QSPI0B_SCLK_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_PDRV_SHIFT)) & IOMUXD_QSPI0B_SCLK_PDRV_MASK)
66734#define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_1_4_MASK (0x1EU)
66735#define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_1_4_SHIFT (1U)
66736/*! QSPI0B_SCLK_reserved_1_4 - reserved
66737 */
66738#define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_1_4_MASK)
66739#define IOMUXD_QSPI0B_SCLK_PULL_MASK (0x60U)
66740#define IOMUXD_QSPI0B_SCLK_PULL_SHIFT (5U)
66741/*! PULL - Pull Down Pull Up
66742 * 0b10..pull down
66743 * 0b01..pull up
66744 * 0b00..Prohibited
66745 * 0b11..pull disabled
66746 */
66747#define IOMUXD_QSPI0B_SCLK_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_PULL_SHIFT)) & IOMUXD_QSPI0B_SCLK_PULL_MASK)
66748#define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_7_18_MASK (0x7FF80U)
66749#define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_7_18_SHIFT (7U)
66750/*! QSPI0B_SCLK_reserved_7_18 - reserved
66751 */
66752#define IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_SCLK_QSPI0B_SCLK_reserved_7_18_MASK)
66753#define IOMUXD_QSPI0B_SCLK_WAKEUP_CTRL_MASK (0x380000U)
66754#define IOMUXD_QSPI0B_SCLK_WAKEUP_CTRL_SHIFT (19U)
66755/*! WAKEUP_CTRL - wakeup control
66756 * 0b000..OFF
66757 * 0b001..RESAMPLE
66758 * 0b100..LOW
66759 * 0b111..HIGH
66760 * 0b110..RISE
66761 * 0b101..FALL
66762 */
66763#define IOMUXD_QSPI0B_SCLK_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_SCLK_WAKEUP_CTRL_MASK)
66764#define IOMUXD_QSPI0B_SCLK_WAKEUP_MASK_MASK (0x400000U)
66765#define IOMUXD_QSPI0B_SCLK_WAKEUP_MASK_SHIFT (22U)
66766/*! WAKEUP_MASK - wakeup mask
66767 */
66768#define IOMUXD_QSPI0B_SCLK_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_SCLK_WAKEUP_MASK_MASK)
66769#define IOMUXD_QSPI0B_SCLK_lp_config_MASK (0x1800000U)
66770#define IOMUXD_QSPI0B_SCLK_lp_config_SHIFT (23U)
66771/*! lp_config - lower power configuration
66772 * 0b01..EARLY_ISO
66773 * 0b10..LATE_ISO
66774 * 0b11..LATCH
66775 * 0b00..PASS
66776 */
66777#define IOMUXD_QSPI0B_SCLK_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_lp_config_SHIFT)) & IOMUXD_QSPI0B_SCLK_lp_config_MASK)
66778#define IOMUXD_QSPI0B_SCLK_sw_config_MASK (0x6000000U)
66779#define IOMUXD_QSPI0B_SCLK_sw_config_SHIFT (25U)
66780/*! sw_config - output and input configuration
66781 * 0b01..OPEN_DRAIN
66782 * 0b10..OPEN_DRAIN_INPUT
66783 * 0b11..INOUT
66784 * 0b00..DEFAULT
66785 */
66786#define IOMUXD_QSPI0B_SCLK_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_sw_config_SHIFT)) & IOMUXD_QSPI0B_SCLK_sw_config_MASK)
66787#define IOMUXD_QSPI0B_SCLK_mux_mode_MASK (0x38000000U)
66788#define IOMUXD_QSPI0B_SCLK_mux_mode_SHIFT (27U)
66789/*! mux_mode - mux_mode
66790 * 0b000..LSIO.QSPI0B.SCLK
66791 * 0b001..LSIO.QSPI1A.SCLK
66792 * 0b010..LSIO.KPP0.COL0
66793 * 0b100..LSIO.GPIO3.IO17
66794 */
66795#define IOMUXD_QSPI0B_SCLK_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SCLK_mux_mode_MASK)
66796#define IOMUXD_QSPI0B_SCLK_update_pad_ctl_MASK (0x40000000U)
66797#define IOMUXD_QSPI0B_SCLK_update_pad_ctl_SHIFT (30U)
66798/*! update_pad_ctl - update lock for pad control
66799 */
66800#define IOMUXD_QSPI0B_SCLK_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_SCLK_update_pad_ctl_MASK)
66801#define IOMUXD_QSPI0B_SCLK_update_mux_mode_MASK (0x80000000U)
66802#define IOMUXD_QSPI0B_SCLK_update_mux_mode_SHIFT (31U)
66803/*! update_mux_mode - update lock for mux control
66804 */
66805#define IOMUXD_QSPI0B_SCLK_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SCLK_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SCLK_update_mux_mode_MASK)
66806/*! @} */
66807
66808/*! @name QSPI0B_DATA0 - QSPI0B_DATA0 */
66809/*! @{ */
66810#define IOMUXD_QSPI0B_DATA0_PDRV_MASK (0x1U)
66811#define IOMUXD_QSPI0B_DATA0_PDRV_SHIFT (0U)
66812/*! PDRV - Drive
66813 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
66814 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
66815 */
66816#define IOMUXD_QSPI0B_DATA0_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_PDRV_SHIFT)) & IOMUXD_QSPI0B_DATA0_PDRV_MASK)
66817#define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_1_4_MASK (0x1EU)
66818#define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_1_4_SHIFT (1U)
66819/*! QSPI0B_DATA0_reserved_1_4 - reserved
66820 */
66821#define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_1_4_MASK)
66822#define IOMUXD_QSPI0B_DATA0_PULL_MASK (0x60U)
66823#define IOMUXD_QSPI0B_DATA0_PULL_SHIFT (5U)
66824/*! PULL - Pull Down Pull Up
66825 * 0b10..pull down
66826 * 0b01..pull up
66827 * 0b00..Prohibited
66828 * 0b11..pull disabled
66829 */
66830#define IOMUXD_QSPI0B_DATA0_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_PULL_SHIFT)) & IOMUXD_QSPI0B_DATA0_PULL_MASK)
66831#define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_7_18_MASK (0x7FF80U)
66832#define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_7_18_SHIFT (7U)
66833/*! QSPI0B_DATA0_reserved_7_18 - reserved
66834 */
66835#define IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_DATA0_QSPI0B_DATA0_reserved_7_18_MASK)
66836#define IOMUXD_QSPI0B_DATA0_WAKEUP_CTRL_MASK (0x380000U)
66837#define IOMUXD_QSPI0B_DATA0_WAKEUP_CTRL_SHIFT (19U)
66838/*! WAKEUP_CTRL - wakeup control
66839 * 0b000..OFF
66840 * 0b001..RESAMPLE
66841 * 0b100..LOW
66842 * 0b111..HIGH
66843 * 0b110..RISE
66844 * 0b101..FALL
66845 */
66846#define IOMUXD_QSPI0B_DATA0_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_DATA0_WAKEUP_CTRL_MASK)
66847#define IOMUXD_QSPI0B_DATA0_WAKEUP_MASK_MASK (0x400000U)
66848#define IOMUXD_QSPI0B_DATA0_WAKEUP_MASK_SHIFT (22U)
66849/*! WAKEUP_MASK - wakeup mask
66850 */
66851#define IOMUXD_QSPI0B_DATA0_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_DATA0_WAKEUP_MASK_MASK)
66852#define IOMUXD_QSPI0B_DATA0_lp_config_MASK (0x1800000U)
66853#define IOMUXD_QSPI0B_DATA0_lp_config_SHIFT (23U)
66854/*! lp_config - lower power configuration
66855 * 0b01..EARLY_ISO
66856 * 0b10..LATE_ISO
66857 * 0b11..LATCH
66858 * 0b00..PASS
66859 */
66860#define IOMUXD_QSPI0B_DATA0_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_lp_config_SHIFT)) & IOMUXD_QSPI0B_DATA0_lp_config_MASK)
66861#define IOMUXD_QSPI0B_DATA0_sw_config_MASK (0x6000000U)
66862#define IOMUXD_QSPI0B_DATA0_sw_config_SHIFT (25U)
66863/*! sw_config - output and input configuration
66864 * 0b01..OPEN_DRAIN
66865 * 0b10..OPEN_DRAIN_INPUT
66866 * 0b11..INOUT
66867 * 0b00..DEFAULT
66868 */
66869#define IOMUXD_QSPI0B_DATA0_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_sw_config_SHIFT)) & IOMUXD_QSPI0B_DATA0_sw_config_MASK)
66870#define IOMUXD_QSPI0B_DATA0_mux_mode_MASK (0x38000000U)
66871#define IOMUXD_QSPI0B_DATA0_mux_mode_SHIFT (27U)
66872/*! mux_mode - mux_mode
66873 * 0b000..LSIO.QSPI0B.DATA0
66874 * 0b001..LSIO.QSPI1A.DATA0
66875 * 0b010..LSIO.KPP0.COL1
66876 * 0b100..LSIO.GPIO3.IO18
66877 */
66878#define IOMUXD_QSPI0B_DATA0_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA0_mux_mode_MASK)
66879#define IOMUXD_QSPI0B_DATA0_update_pad_ctl_MASK (0x40000000U)
66880#define IOMUXD_QSPI0B_DATA0_update_pad_ctl_SHIFT (30U)
66881/*! update_pad_ctl - update lock for pad control
66882 */
66883#define IOMUXD_QSPI0B_DATA0_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_DATA0_update_pad_ctl_MASK)
66884#define IOMUXD_QSPI0B_DATA0_update_mux_mode_MASK (0x80000000U)
66885#define IOMUXD_QSPI0B_DATA0_update_mux_mode_SHIFT (31U)
66886/*! update_mux_mode - update lock for mux control
66887 */
66888#define IOMUXD_QSPI0B_DATA0_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA0_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA0_update_mux_mode_MASK)
66889/*! @} */
66890
66891/*! @name QSPI0B_DATA1 - QSPI0B_DATA1 */
66892/*! @{ */
66893#define IOMUXD_QSPI0B_DATA1_PDRV_MASK (0x1U)
66894#define IOMUXD_QSPI0B_DATA1_PDRV_SHIFT (0U)
66895/*! PDRV - Drive
66896 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
66897 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
66898 */
66899#define IOMUXD_QSPI0B_DATA1_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_PDRV_SHIFT)) & IOMUXD_QSPI0B_DATA1_PDRV_MASK)
66900#define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_1_4_MASK (0x1EU)
66901#define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_1_4_SHIFT (1U)
66902/*! QSPI0B_DATA1_reserved_1_4 - reserved
66903 */
66904#define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_1_4_MASK)
66905#define IOMUXD_QSPI0B_DATA1_PULL_MASK (0x60U)
66906#define IOMUXD_QSPI0B_DATA1_PULL_SHIFT (5U)
66907/*! PULL - Pull Down Pull Up
66908 * 0b10..pull down
66909 * 0b01..pull up
66910 * 0b00..Prohibited
66911 * 0b11..pull disabled
66912 */
66913#define IOMUXD_QSPI0B_DATA1_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_PULL_SHIFT)) & IOMUXD_QSPI0B_DATA1_PULL_MASK)
66914#define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_7_18_MASK (0x7FF80U)
66915#define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_7_18_SHIFT (7U)
66916/*! QSPI0B_DATA1_reserved_7_18 - reserved
66917 */
66918#define IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_DATA1_QSPI0B_DATA1_reserved_7_18_MASK)
66919#define IOMUXD_QSPI0B_DATA1_WAKEUP_CTRL_MASK (0x380000U)
66920#define IOMUXD_QSPI0B_DATA1_WAKEUP_CTRL_SHIFT (19U)
66921/*! WAKEUP_CTRL - wakeup control
66922 * 0b000..OFF
66923 * 0b001..RESAMPLE
66924 * 0b100..LOW
66925 * 0b111..HIGH
66926 * 0b110..RISE
66927 * 0b101..FALL
66928 */
66929#define IOMUXD_QSPI0B_DATA1_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_DATA1_WAKEUP_CTRL_MASK)
66930#define IOMUXD_QSPI0B_DATA1_WAKEUP_MASK_MASK (0x400000U)
66931#define IOMUXD_QSPI0B_DATA1_WAKEUP_MASK_SHIFT (22U)
66932/*! WAKEUP_MASK - wakeup mask
66933 */
66934#define IOMUXD_QSPI0B_DATA1_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_DATA1_WAKEUP_MASK_MASK)
66935#define IOMUXD_QSPI0B_DATA1_lp_config_MASK (0x1800000U)
66936#define IOMUXD_QSPI0B_DATA1_lp_config_SHIFT (23U)
66937/*! lp_config - lower power configuration
66938 * 0b01..EARLY_ISO
66939 * 0b10..LATE_ISO
66940 * 0b11..LATCH
66941 * 0b00..PASS
66942 */
66943#define IOMUXD_QSPI0B_DATA1_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_lp_config_SHIFT)) & IOMUXD_QSPI0B_DATA1_lp_config_MASK)
66944#define IOMUXD_QSPI0B_DATA1_sw_config_MASK (0x6000000U)
66945#define IOMUXD_QSPI0B_DATA1_sw_config_SHIFT (25U)
66946/*! sw_config - output and input configuration
66947 * 0b01..OPEN_DRAIN
66948 * 0b10..OPEN_DRAIN_INPUT
66949 * 0b11..INOUT
66950 * 0b00..DEFAULT
66951 */
66952#define IOMUXD_QSPI0B_DATA1_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_sw_config_SHIFT)) & IOMUXD_QSPI0B_DATA1_sw_config_MASK)
66953#define IOMUXD_QSPI0B_DATA1_mux_mode_MASK (0x38000000U)
66954#define IOMUXD_QSPI0B_DATA1_mux_mode_SHIFT (27U)
66955/*! mux_mode - mux_mode
66956 * 0b000..LSIO.QSPI0B.DATA1
66957 * 0b001..LSIO.QSPI1A.DATA1
66958 * 0b010..LSIO.KPP0.COL2
66959 * 0b100..LSIO.GPIO3.IO19
66960 */
66961#define IOMUXD_QSPI0B_DATA1_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA1_mux_mode_MASK)
66962#define IOMUXD_QSPI0B_DATA1_update_pad_ctl_MASK (0x40000000U)
66963#define IOMUXD_QSPI0B_DATA1_update_pad_ctl_SHIFT (30U)
66964/*! update_pad_ctl - update lock for pad control
66965 */
66966#define IOMUXD_QSPI0B_DATA1_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_DATA1_update_pad_ctl_MASK)
66967#define IOMUXD_QSPI0B_DATA1_update_mux_mode_MASK (0x80000000U)
66968#define IOMUXD_QSPI0B_DATA1_update_mux_mode_SHIFT (31U)
66969/*! update_mux_mode - update lock for mux control
66970 */
66971#define IOMUXD_QSPI0B_DATA1_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA1_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA1_update_mux_mode_MASK)
66972/*! @} */
66973
66974/*! @name QSPI0B_DATA2 - QSPI0B_DATA2 */
66975/*! @{ */
66976#define IOMUXD_QSPI0B_DATA2_PDRV_MASK (0x1U)
66977#define IOMUXD_QSPI0B_DATA2_PDRV_SHIFT (0U)
66978/*! PDRV - Drive
66979 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
66980 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
66981 */
66982#define IOMUXD_QSPI0B_DATA2_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_PDRV_SHIFT)) & IOMUXD_QSPI0B_DATA2_PDRV_MASK)
66983#define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_1_4_MASK (0x1EU)
66984#define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_1_4_SHIFT (1U)
66985/*! QSPI0B_DATA2_reserved_1_4 - reserved
66986 */
66987#define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_1_4_MASK)
66988#define IOMUXD_QSPI0B_DATA2_PULL_MASK (0x60U)
66989#define IOMUXD_QSPI0B_DATA2_PULL_SHIFT (5U)
66990/*! PULL - Pull Down Pull Up
66991 * 0b10..pull down
66992 * 0b01..pull up
66993 * 0b00..Prohibited
66994 * 0b11..pull disabled
66995 */
66996#define IOMUXD_QSPI0B_DATA2_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_PULL_SHIFT)) & IOMUXD_QSPI0B_DATA2_PULL_MASK)
66997#define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_7_18_MASK (0x7FF80U)
66998#define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_7_18_SHIFT (7U)
66999/*! QSPI0B_DATA2_reserved_7_18 - reserved
67000 */
67001#define IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_DATA2_QSPI0B_DATA2_reserved_7_18_MASK)
67002#define IOMUXD_QSPI0B_DATA2_WAKEUP_CTRL_MASK (0x380000U)
67003#define IOMUXD_QSPI0B_DATA2_WAKEUP_CTRL_SHIFT (19U)
67004/*! WAKEUP_CTRL - wakeup control
67005 * 0b000..OFF
67006 * 0b001..RESAMPLE
67007 * 0b100..LOW
67008 * 0b111..HIGH
67009 * 0b110..RISE
67010 * 0b101..FALL
67011 */
67012#define IOMUXD_QSPI0B_DATA2_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_DATA2_WAKEUP_CTRL_MASK)
67013#define IOMUXD_QSPI0B_DATA2_WAKEUP_MASK_MASK (0x400000U)
67014#define IOMUXD_QSPI0B_DATA2_WAKEUP_MASK_SHIFT (22U)
67015/*! WAKEUP_MASK - wakeup mask
67016 */
67017#define IOMUXD_QSPI0B_DATA2_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_DATA2_WAKEUP_MASK_MASK)
67018#define IOMUXD_QSPI0B_DATA2_lp_config_MASK (0x1800000U)
67019#define IOMUXD_QSPI0B_DATA2_lp_config_SHIFT (23U)
67020/*! lp_config - lower power configuration
67021 * 0b01..EARLY_ISO
67022 * 0b10..LATE_ISO
67023 * 0b11..LATCH
67024 * 0b00..PASS
67025 */
67026#define IOMUXD_QSPI0B_DATA2_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_lp_config_SHIFT)) & IOMUXD_QSPI0B_DATA2_lp_config_MASK)
67027#define IOMUXD_QSPI0B_DATA2_sw_config_MASK (0x6000000U)
67028#define IOMUXD_QSPI0B_DATA2_sw_config_SHIFT (25U)
67029/*! sw_config - output and input configuration
67030 * 0b01..OPEN_DRAIN
67031 * 0b10..OPEN_DRAIN_INPUT
67032 * 0b11..INOUT
67033 * 0b00..DEFAULT
67034 */
67035#define IOMUXD_QSPI0B_DATA2_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_sw_config_SHIFT)) & IOMUXD_QSPI0B_DATA2_sw_config_MASK)
67036#define IOMUXD_QSPI0B_DATA2_mux_mode_MASK (0x38000000U)
67037#define IOMUXD_QSPI0B_DATA2_mux_mode_SHIFT (27U)
67038/*! mux_mode - mux_mode
67039 * 0b000..LSIO.QSPI0B.DATA2
67040 * 0b001..LSIO.QSPI1A.DATA2
67041 * 0b010..LSIO.KPP0.COL3
67042 * 0b100..LSIO.GPIO3.IO20
67043 */
67044#define IOMUXD_QSPI0B_DATA2_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA2_mux_mode_MASK)
67045#define IOMUXD_QSPI0B_DATA2_update_pad_ctl_MASK (0x40000000U)
67046#define IOMUXD_QSPI0B_DATA2_update_pad_ctl_SHIFT (30U)
67047/*! update_pad_ctl - update lock for pad control
67048 */
67049#define IOMUXD_QSPI0B_DATA2_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_DATA2_update_pad_ctl_MASK)
67050#define IOMUXD_QSPI0B_DATA2_update_mux_mode_MASK (0x80000000U)
67051#define IOMUXD_QSPI0B_DATA2_update_mux_mode_SHIFT (31U)
67052/*! update_mux_mode - update lock for mux control
67053 */
67054#define IOMUXD_QSPI0B_DATA2_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA2_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA2_update_mux_mode_MASK)
67055/*! @} */
67056
67057/*! @name QSPI0B_DATA3 - QSPI0B_DATA3 */
67058/*! @{ */
67059#define IOMUXD_QSPI0B_DATA3_PDRV_MASK (0x1U)
67060#define IOMUXD_QSPI0B_DATA3_PDRV_SHIFT (0U)
67061/*! PDRV - Drive
67062 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
67063 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
67064 */
67065#define IOMUXD_QSPI0B_DATA3_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_PDRV_SHIFT)) & IOMUXD_QSPI0B_DATA3_PDRV_MASK)
67066#define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_1_4_MASK (0x1EU)
67067#define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_1_4_SHIFT (1U)
67068/*! QSPI0B_DATA3_reserved_1_4 - reserved
67069 */
67070#define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_1_4_MASK)
67071#define IOMUXD_QSPI0B_DATA3_PULL_MASK (0x60U)
67072#define IOMUXD_QSPI0B_DATA3_PULL_SHIFT (5U)
67073/*! PULL - Pull Down Pull Up
67074 * 0b10..pull down
67075 * 0b01..pull up
67076 * 0b00..Prohibited
67077 * 0b11..pull disabled
67078 */
67079#define IOMUXD_QSPI0B_DATA3_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_PULL_SHIFT)) & IOMUXD_QSPI0B_DATA3_PULL_MASK)
67080#define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_7_18_MASK (0x7FF80U)
67081#define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_7_18_SHIFT (7U)
67082/*! QSPI0B_DATA3_reserved_7_18 - reserved
67083 */
67084#define IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_DATA3_QSPI0B_DATA3_reserved_7_18_MASK)
67085#define IOMUXD_QSPI0B_DATA3_WAKEUP_CTRL_MASK (0x380000U)
67086#define IOMUXD_QSPI0B_DATA3_WAKEUP_CTRL_SHIFT (19U)
67087/*! WAKEUP_CTRL - wakeup control
67088 * 0b000..OFF
67089 * 0b001..RESAMPLE
67090 * 0b100..LOW
67091 * 0b111..HIGH
67092 * 0b110..RISE
67093 * 0b101..FALL
67094 */
67095#define IOMUXD_QSPI0B_DATA3_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_DATA3_WAKEUP_CTRL_MASK)
67096#define IOMUXD_QSPI0B_DATA3_WAKEUP_MASK_MASK (0x400000U)
67097#define IOMUXD_QSPI0B_DATA3_WAKEUP_MASK_SHIFT (22U)
67098/*! WAKEUP_MASK - wakeup mask
67099 */
67100#define IOMUXD_QSPI0B_DATA3_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_DATA3_WAKEUP_MASK_MASK)
67101#define IOMUXD_QSPI0B_DATA3_lp_config_MASK (0x1800000U)
67102#define IOMUXD_QSPI0B_DATA3_lp_config_SHIFT (23U)
67103/*! lp_config - lower power configuration
67104 * 0b01..EARLY_ISO
67105 * 0b10..LATE_ISO
67106 * 0b11..LATCH
67107 * 0b00..PASS
67108 */
67109#define IOMUXD_QSPI0B_DATA3_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_lp_config_SHIFT)) & IOMUXD_QSPI0B_DATA3_lp_config_MASK)
67110#define IOMUXD_QSPI0B_DATA3_sw_config_MASK (0x6000000U)
67111#define IOMUXD_QSPI0B_DATA3_sw_config_SHIFT (25U)
67112/*! sw_config - output and input configuration
67113 * 0b01..OPEN_DRAIN
67114 * 0b10..OPEN_DRAIN_INPUT
67115 * 0b11..INOUT
67116 * 0b00..DEFAULT
67117 */
67118#define IOMUXD_QSPI0B_DATA3_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_sw_config_SHIFT)) & IOMUXD_QSPI0B_DATA3_sw_config_MASK)
67119#define IOMUXD_QSPI0B_DATA3_mux_mode_MASK (0x38000000U)
67120#define IOMUXD_QSPI0B_DATA3_mux_mode_SHIFT (27U)
67121/*! mux_mode - mux_mode
67122 * 0b000..LSIO.QSPI0B.DATA3
67123 * 0b001..LSIO.QSPI1A.DATA3
67124 * 0b010..LSIO.KPP0.ROW0
67125 * 0b100..LSIO.GPIO3.IO21
67126 */
67127#define IOMUXD_QSPI0B_DATA3_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA3_mux_mode_MASK)
67128#define IOMUXD_QSPI0B_DATA3_update_pad_ctl_MASK (0x40000000U)
67129#define IOMUXD_QSPI0B_DATA3_update_pad_ctl_SHIFT (30U)
67130/*! update_pad_ctl - update lock for pad control
67131 */
67132#define IOMUXD_QSPI0B_DATA3_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_DATA3_update_pad_ctl_MASK)
67133#define IOMUXD_QSPI0B_DATA3_update_mux_mode_MASK (0x80000000U)
67134#define IOMUXD_QSPI0B_DATA3_update_mux_mode_SHIFT (31U)
67135/*! update_mux_mode - update lock for mux control
67136 */
67137#define IOMUXD_QSPI0B_DATA3_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DATA3_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DATA3_update_mux_mode_MASK)
67138/*! @} */
67139
67140/*! @name QSPI0B_DQS - QSPI0B_DQS */
67141/*! @{ */
67142#define IOMUXD_QSPI0B_DQS_PDRV_MASK (0x1U)
67143#define IOMUXD_QSPI0B_DQS_PDRV_SHIFT (0U)
67144/*! PDRV - Drive
67145 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
67146 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
67147 */
67148#define IOMUXD_QSPI0B_DQS_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_PDRV_SHIFT)) & IOMUXD_QSPI0B_DQS_PDRV_MASK)
67149#define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_1_4_MASK (0x1EU)
67150#define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_1_4_SHIFT (1U)
67151/*! QSPI0B_DQS_reserved_1_4 - reserved
67152 */
67153#define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_1_4_MASK)
67154#define IOMUXD_QSPI0B_DQS_PULL_MASK (0x60U)
67155#define IOMUXD_QSPI0B_DQS_PULL_SHIFT (5U)
67156/*! PULL - Pull Down Pull Up
67157 * 0b10..pull down
67158 * 0b01..pull up
67159 * 0b00..Prohibited
67160 * 0b11..pull disabled
67161 */
67162#define IOMUXD_QSPI0B_DQS_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_PULL_SHIFT)) & IOMUXD_QSPI0B_DQS_PULL_MASK)
67163#define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_7_18_MASK (0x7FF80U)
67164#define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_7_18_SHIFT (7U)
67165/*! QSPI0B_DQS_reserved_7_18 - reserved
67166 */
67167#define IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_DQS_QSPI0B_DQS_reserved_7_18_MASK)
67168#define IOMUXD_QSPI0B_DQS_WAKEUP_CTRL_MASK (0x380000U)
67169#define IOMUXD_QSPI0B_DQS_WAKEUP_CTRL_SHIFT (19U)
67170/*! WAKEUP_CTRL - wakeup control
67171 * 0b000..OFF
67172 * 0b001..RESAMPLE
67173 * 0b100..LOW
67174 * 0b111..HIGH
67175 * 0b110..RISE
67176 * 0b101..FALL
67177 */
67178#define IOMUXD_QSPI0B_DQS_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_DQS_WAKEUP_CTRL_MASK)
67179#define IOMUXD_QSPI0B_DQS_WAKEUP_MASK_MASK (0x400000U)
67180#define IOMUXD_QSPI0B_DQS_WAKEUP_MASK_SHIFT (22U)
67181/*! WAKEUP_MASK - wakeup mask
67182 */
67183#define IOMUXD_QSPI0B_DQS_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_DQS_WAKEUP_MASK_MASK)
67184#define IOMUXD_QSPI0B_DQS_lp_config_MASK (0x1800000U)
67185#define IOMUXD_QSPI0B_DQS_lp_config_SHIFT (23U)
67186/*! lp_config - lower power configuration
67187 * 0b01..EARLY_ISO
67188 * 0b10..LATE_ISO
67189 * 0b11..LATCH
67190 * 0b00..PASS
67191 */
67192#define IOMUXD_QSPI0B_DQS_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_lp_config_SHIFT)) & IOMUXD_QSPI0B_DQS_lp_config_MASK)
67193#define IOMUXD_QSPI0B_DQS_sw_config_MASK (0x6000000U)
67194#define IOMUXD_QSPI0B_DQS_sw_config_SHIFT (25U)
67195/*! sw_config - output and input configuration
67196 * 0b01..OPEN_DRAIN
67197 * 0b10..OPEN_DRAIN_INPUT
67198 * 0b11..INOUT
67199 * 0b00..DEFAULT
67200 */
67201#define IOMUXD_QSPI0B_DQS_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_sw_config_SHIFT)) & IOMUXD_QSPI0B_DQS_sw_config_MASK)
67202#define IOMUXD_QSPI0B_DQS_mux_mode_MASK (0x38000000U)
67203#define IOMUXD_QSPI0B_DQS_mux_mode_SHIFT (27U)
67204/*! mux_mode - mux_mode
67205 * 0b000..LSIO.QSPI0B.DQS
67206 * 0b001..LSIO.QSPI1A.DQS
67207 * 0b010..LSIO.KPP0.ROW1
67208 * 0b100..LSIO.GPIO3.IO22
67209 */
67210#define IOMUXD_QSPI0B_DQS_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DQS_mux_mode_MASK)
67211#define IOMUXD_QSPI0B_DQS_update_pad_ctl_MASK (0x40000000U)
67212#define IOMUXD_QSPI0B_DQS_update_pad_ctl_SHIFT (30U)
67213/*! update_pad_ctl - update lock for pad control
67214 */
67215#define IOMUXD_QSPI0B_DQS_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_DQS_update_pad_ctl_MASK)
67216#define IOMUXD_QSPI0B_DQS_update_mux_mode_MASK (0x80000000U)
67217#define IOMUXD_QSPI0B_DQS_update_mux_mode_SHIFT (31U)
67218/*! update_mux_mode - update lock for mux control
67219 */
67220#define IOMUXD_QSPI0B_DQS_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_DQS_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_DQS_update_mux_mode_MASK)
67221/*! @} */
67222
67223/*! @name IOMUXD_GROUP_3_0 - na */
67224/*! @{ */
67225#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA0_MASK (0x1U)
67226#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA0_SHIFT (0U)
67227/*! QSPI0A_DATA0 - wakeup from QSPI0A_DATA0
67228 */
67229#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA0_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA0_MASK)
67230#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA1_MASK (0x2U)
67231#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA1_SHIFT (1U)
67232/*! QSPI0A_DATA1 - wakeup from QSPI0A_DATA1
67233 */
67234#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA1_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA1_MASK)
67235#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA2_MASK (0x4U)
67236#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA2_SHIFT (2U)
67237/*! QSPI0A_DATA2 - wakeup from QSPI0A_DATA2
67238 */
67239#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA2_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA2_MASK)
67240#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA3_MASK (0x8U)
67241#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA3_SHIFT (3U)
67242/*! QSPI0A_DATA3 - wakeup from QSPI0A_DATA3
67243 */
67244#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA3_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DATA3_MASK)
67245#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DQS_MASK (0x10U)
67246#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DQS_SHIFT (4U)
67247/*! QSPI0A_DQS - wakeup from QSPI0A_DQS
67248 */
67249#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DQS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DQS_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_DQS_MASK)
67250#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS0_B_MASK (0x20U)
67251#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS0_B_SHIFT (5U)
67252/*! QSPI0A_SS0_B - wakeup from QSPI0A_SS0_B
67253 */
67254#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS0_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS0_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS0_B_MASK)
67255#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS1_B_MASK (0x40U)
67256#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS1_B_SHIFT (6U)
67257/*! QSPI0A_SS1_B - wakeup from QSPI0A_SS1_B
67258 */
67259#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS1_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS1_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SS1_B_MASK)
67260#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SCLK_MASK (0x80U)
67261#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SCLK_SHIFT (7U)
67262/*! QSPI0A_SCLK - wakeup from QSPI0A_SCLK
67263 */
67264#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SCLK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SCLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0A_SCLK_MASK)
67265#define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_8_8_MASK (0x100U)
67266#define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_8_8_SHIFT (8U)
67267/*! iomuxd_group_3_0_reserved_8_8 - reserved
67268 */
67269#define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_8_8_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_8_8_MASK)
67270#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_SCLK_MASK (0x200U)
67271#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_SCLK_SHIFT (9U)
67272/*! QSPI0B_SCLK - wakeup from QSPI0B_SCLK
67273 */
67274#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_SCLK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_SCLK_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_SCLK_MASK)
67275#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA0_MASK (0x400U)
67276#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA0_SHIFT (10U)
67277/*! QSPI0B_DATA0 - wakeup from QSPI0B_DATA0
67278 */
67279#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA0_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA0_MASK)
67280#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA1_MASK (0x800U)
67281#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA1_SHIFT (11U)
67282/*! QSPI0B_DATA1 - wakeup from QSPI0B_DATA1
67283 */
67284#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA1_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA1_MASK)
67285#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA2_MASK (0x1000U)
67286#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA2_SHIFT (12U)
67287/*! QSPI0B_DATA2 - wakeup from QSPI0B_DATA2
67288 */
67289#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA2_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA2_MASK)
67290#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA3_MASK (0x2000U)
67291#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA3_SHIFT (13U)
67292/*! QSPI0B_DATA3 - wakeup from QSPI0B_DATA3
67293 */
67294#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA3_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DATA3_MASK)
67295#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DQS_MASK (0x4000U)
67296#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DQS_SHIFT (14U)
67297/*! QSPI0B_DQS - wakeup from QSPI0B_DQS
67298 */
67299#define IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DQS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DQS_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_QSPI0B_DQS_MASK)
67300#define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_15_31_MASK (0xFFFF8000U)
67301#define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_15_31_SHIFT (15U)
67302/*! iomuxd_group_3_0_reserved_15_31 - reserved
67303 */
67304#define IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_15_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_15_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_0_iomuxd_group_3_0_reserved_15_31_MASK)
67305/*! @} */
67306
67307/*! @name QSPI0B_SS0_B - QSPI0B_SS0_B */
67308/*! @{ */
67309#define IOMUXD_QSPI0B_SS0_B_PDRV_MASK (0x1U)
67310#define IOMUXD_QSPI0B_SS0_B_PDRV_SHIFT (0U)
67311/*! PDRV - Drive
67312 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
67313 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
67314 */
67315#define IOMUXD_QSPI0B_SS0_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_PDRV_SHIFT)) & IOMUXD_QSPI0B_SS0_B_PDRV_MASK)
67316#define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_1_4_MASK (0x1EU)
67317#define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_1_4_SHIFT (1U)
67318/*! QSPI0B_SS0_B_reserved_1_4 - reserved
67319 */
67320#define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_1_4_MASK)
67321#define IOMUXD_QSPI0B_SS0_B_PULL_MASK (0x60U)
67322#define IOMUXD_QSPI0B_SS0_B_PULL_SHIFT (5U)
67323/*! PULL - Pull Down Pull Up
67324 * 0b10..pull down
67325 * 0b01..pull up
67326 * 0b00..Prohibited
67327 * 0b11..pull disabled
67328 */
67329#define IOMUXD_QSPI0B_SS0_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_PULL_SHIFT)) & IOMUXD_QSPI0B_SS0_B_PULL_MASK)
67330#define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_7_18_MASK (0x7FF80U)
67331#define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_7_18_SHIFT (7U)
67332/*! QSPI0B_SS0_B_reserved_7_18 - reserved
67333 */
67334#define IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_SS0_B_QSPI0B_SS0_B_reserved_7_18_MASK)
67335#define IOMUXD_QSPI0B_SS0_B_WAKEUP_CTRL_MASK (0x380000U)
67336#define IOMUXD_QSPI0B_SS0_B_WAKEUP_CTRL_SHIFT (19U)
67337/*! WAKEUP_CTRL - wakeup control
67338 * 0b000..OFF
67339 * 0b001..RESAMPLE
67340 * 0b100..LOW
67341 * 0b111..HIGH
67342 * 0b110..RISE
67343 * 0b101..FALL
67344 */
67345#define IOMUXD_QSPI0B_SS0_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_SS0_B_WAKEUP_CTRL_MASK)
67346#define IOMUXD_QSPI0B_SS0_B_WAKEUP_MASK_MASK (0x400000U)
67347#define IOMUXD_QSPI0B_SS0_B_WAKEUP_MASK_SHIFT (22U)
67348/*! WAKEUP_MASK - wakeup mask
67349 */
67350#define IOMUXD_QSPI0B_SS0_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_SS0_B_WAKEUP_MASK_MASK)
67351#define IOMUXD_QSPI0B_SS0_B_lp_config_MASK (0x1800000U)
67352#define IOMUXD_QSPI0B_SS0_B_lp_config_SHIFT (23U)
67353/*! lp_config - lower power configuration
67354 * 0b01..EARLY_ISO
67355 * 0b10..LATE_ISO
67356 * 0b11..LATCH
67357 * 0b00..PASS
67358 */
67359#define IOMUXD_QSPI0B_SS0_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_lp_config_SHIFT)) & IOMUXD_QSPI0B_SS0_B_lp_config_MASK)
67360#define IOMUXD_QSPI0B_SS0_B_sw_config_MASK (0x6000000U)
67361#define IOMUXD_QSPI0B_SS0_B_sw_config_SHIFT (25U)
67362/*! sw_config - output and input configuration
67363 * 0b01..OPEN_DRAIN
67364 * 0b10..OPEN_DRAIN_INPUT
67365 * 0b11..INOUT
67366 * 0b00..DEFAULT
67367 */
67368#define IOMUXD_QSPI0B_SS0_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_sw_config_SHIFT)) & IOMUXD_QSPI0B_SS0_B_sw_config_MASK)
67369#define IOMUXD_QSPI0B_SS0_B_mux_mode_MASK (0x38000000U)
67370#define IOMUXD_QSPI0B_SS0_B_mux_mode_SHIFT (27U)
67371/*! mux_mode - mux_mode
67372 * 0b000..LSIO.QSPI0B.SS0_B
67373 * 0b001..LSIO.QSPI1A.SS0_B
67374 * 0b010..LSIO.KPP0.ROW2
67375 * 0b100..LSIO.GPIO3.IO23
67376 */
67377#define IOMUXD_QSPI0B_SS0_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SS0_B_mux_mode_MASK)
67378#define IOMUXD_QSPI0B_SS0_B_update_pad_ctl_MASK (0x40000000U)
67379#define IOMUXD_QSPI0B_SS0_B_update_pad_ctl_SHIFT (30U)
67380/*! update_pad_ctl - update lock for pad control
67381 */
67382#define IOMUXD_QSPI0B_SS0_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_SS0_B_update_pad_ctl_MASK)
67383#define IOMUXD_QSPI0B_SS0_B_update_mux_mode_MASK (0x80000000U)
67384#define IOMUXD_QSPI0B_SS0_B_update_mux_mode_SHIFT (31U)
67385/*! update_mux_mode - update lock for mux control
67386 */
67387#define IOMUXD_QSPI0B_SS0_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS0_B_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SS0_B_update_mux_mode_MASK)
67388/*! @} */
67389
67390/*! @name QSPI0B_SS1_B - QSPI0B_SS1_B */
67391/*! @{ */
67392#define IOMUXD_QSPI0B_SS1_B_PDRV_MASK (0x1U)
67393#define IOMUXD_QSPI0B_SS1_B_PDRV_SHIFT (0U)
67394/*! PDRV - Drive
67395 * 0b0..Output is configured in High Drive mode both in 1.8 V and 3.3 V applications
67396 * 0b1..Output is configured in Low Drive mode both in 1.8 V and 3.3 V applications
67397 */
67398#define IOMUXD_QSPI0B_SS1_B_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_PDRV_SHIFT)) & IOMUXD_QSPI0B_SS1_B_PDRV_MASK)
67399#define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_1_4_MASK (0x1EU)
67400#define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_1_4_SHIFT (1U)
67401/*! QSPI0B_SS1_B_reserved_1_4 - reserved
67402 */
67403#define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_1_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_1_4_SHIFT)) & IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_1_4_MASK)
67404#define IOMUXD_QSPI0B_SS1_B_PULL_MASK (0x60U)
67405#define IOMUXD_QSPI0B_SS1_B_PULL_SHIFT (5U)
67406/*! PULL - Pull Down Pull Up
67407 * 0b10..pull down
67408 * 0b01..pull up
67409 * 0b00..Prohibited
67410 * 0b11..pull disabled
67411 */
67412#define IOMUXD_QSPI0B_SS1_B_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_PULL_SHIFT)) & IOMUXD_QSPI0B_SS1_B_PULL_MASK)
67413#define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_7_18_MASK (0x7FF80U)
67414#define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_7_18_SHIFT (7U)
67415/*! QSPI0B_SS1_B_reserved_7_18 - reserved
67416 */
67417#define IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_7_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_7_18_SHIFT)) & IOMUXD_QSPI0B_SS1_B_QSPI0B_SS1_B_reserved_7_18_MASK)
67418#define IOMUXD_QSPI0B_SS1_B_WAKEUP_CTRL_MASK (0x380000U)
67419#define IOMUXD_QSPI0B_SS1_B_WAKEUP_CTRL_SHIFT (19U)
67420/*! WAKEUP_CTRL - wakeup control
67421 * 0b000..OFF
67422 * 0b001..RESAMPLE
67423 * 0b100..LOW
67424 * 0b111..HIGH
67425 * 0b110..RISE
67426 * 0b101..FALL
67427 */
67428#define IOMUXD_QSPI0B_SS1_B_WAKEUP_CTRL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_WAKEUP_CTRL_SHIFT)) & IOMUXD_QSPI0B_SS1_B_WAKEUP_CTRL_MASK)
67429#define IOMUXD_QSPI0B_SS1_B_WAKEUP_MASK_MASK (0x400000U)
67430#define IOMUXD_QSPI0B_SS1_B_WAKEUP_MASK_SHIFT (22U)
67431/*! WAKEUP_MASK - wakeup mask
67432 */
67433#define IOMUXD_QSPI0B_SS1_B_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_WAKEUP_MASK_SHIFT)) & IOMUXD_QSPI0B_SS1_B_WAKEUP_MASK_MASK)
67434#define IOMUXD_QSPI0B_SS1_B_lp_config_MASK (0x1800000U)
67435#define IOMUXD_QSPI0B_SS1_B_lp_config_SHIFT (23U)
67436/*! lp_config - lower power configuration
67437 * 0b01..EARLY_ISO
67438 * 0b10..LATE_ISO
67439 * 0b11..LATCH
67440 * 0b00..PASS
67441 */
67442#define IOMUXD_QSPI0B_SS1_B_lp_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_lp_config_SHIFT)) & IOMUXD_QSPI0B_SS1_B_lp_config_MASK)
67443#define IOMUXD_QSPI0B_SS1_B_sw_config_MASK (0x6000000U)
67444#define IOMUXD_QSPI0B_SS1_B_sw_config_SHIFT (25U)
67445/*! sw_config - output and input configuration
67446 * 0b01..OPEN_DRAIN
67447 * 0b10..OPEN_DRAIN_INPUT
67448 * 0b11..INOUT
67449 * 0b00..DEFAULT
67450 */
67451#define IOMUXD_QSPI0B_SS1_B_sw_config(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_sw_config_SHIFT)) & IOMUXD_QSPI0B_SS1_B_sw_config_MASK)
67452#define IOMUXD_QSPI0B_SS1_B_mux_mode_MASK (0x38000000U)
67453#define IOMUXD_QSPI0B_SS1_B_mux_mode_SHIFT (27U)
67454/*! mux_mode - mux_mode
67455 * 0b000..LSIO.QSPI0B.SS1_B
67456 * 0b001..LSIO.QSPI1A.SS1_B
67457 * 0b010..LSIO.KPP0.ROW3
67458 * 0b100..LSIO.GPIO3.IO24
67459 */
67460#define IOMUXD_QSPI0B_SS1_B_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SS1_B_mux_mode_MASK)
67461#define IOMUXD_QSPI0B_SS1_B_update_pad_ctl_MASK (0x40000000U)
67462#define IOMUXD_QSPI0B_SS1_B_update_pad_ctl_SHIFT (30U)
67463/*! update_pad_ctl - update lock for pad control
67464 */
67465#define IOMUXD_QSPI0B_SS1_B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_update_pad_ctl_SHIFT)) & IOMUXD_QSPI0B_SS1_B_update_pad_ctl_MASK)
67466#define IOMUXD_QSPI0B_SS1_B_update_mux_mode_MASK (0x80000000U)
67467#define IOMUXD_QSPI0B_SS1_B_update_mux_mode_SHIFT (31U)
67468/*! update_mux_mode - update lock for mux control
67469 */
67470#define IOMUXD_QSPI0B_SS1_B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_QSPI0B_SS1_B_update_mux_mode_SHIFT)) & IOMUXD_QSPI0B_SS1_B_update_mux_mode_MASK)
67471/*! @} */
67472
67473/*! @name IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B - IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B */
67474/*! @{ */
67475#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMP_MASK (0x7U)
67476#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMP_SHIFT (0U)
67477/*! COMP - COMP
67478 * 0b010..Fixed code mode
67479 * 0b100..High impedance mode
67480 * 0b110..Read mode
67481 * 0b000..Normal Mode
67482 * 0b001..Freeze Mode
67483 */
67484#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMP_MASK)
67485#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_FASTFRZ_EN_MASK (0x8U)
67486#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_FASTFRZ_EN_SHIFT (3U)
67487/*! FASTFRZ_EN - FASTFRZ_EN
67488 * 0b1..FASTFRZ signal is driven by output of subsystem
67489 * 0b0..FASTFRZ signal is gated to 0
67490 */
67491#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_FASTFRZ_EN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_FASTFRZ_EN_MASK)
67492#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_4_4_MASK (0x10U)
67493#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_4_4_SHIFT (4U)
67494/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_4_4 - reserved
67495 */
67496#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_4_4_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_4_4_MASK)
67497#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCP_MASK (0x1E0U)
67498#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCP_SHIFT (5U)
67499/*! RASRCP - RASRCP
67500 * 0b0101..Reset Value
67501 */
67502#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCP_MASK)
67503#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCN_MASK (0x1E00U)
67504#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCN_SHIFT (9U)
67505/*! RASRCN - RASRCN
67506 * 0b1010..Reset Value
67507 */
67508#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCN_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_RASRCN_MASK)
67509#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SELECT_NASRC_MASK (0x2000U)
67510#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SELECT_NASRC_SHIFT (13U)
67511/*! SELECT_NASRC - SELECT_NASRC
67512 * 0b1..NASRCN value
67513 * 0b0..NASRCP value
67514 */
67515#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SELECT_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SELECT_NASRC_MASK)
67516#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMPOK_MASK (0x4000U)
67517#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMPOK_SHIFT (14U)
67518/*! COMPOK - COMPOK
67519 * 0b0..compensation cell in another mode than Normal mode or generating compensation code when in Normal mode
67520 * 0b1..compensation cell in Normal mode and tracking PVT
67521 */
67522#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMPOK_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_COMPOK_MASK)
67523#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_READ_NASRC_MASK (0x78000U)
67524#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_READ_NASRC_SHIFT (15U)
67525/*! READ_NASRC - READ_NASRC
67526 * 0b0000..READ Only
67527 */
67528#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_READ_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_READ_NASRC_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_READ_NASRC_MASK)
67529#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_19_22_MASK (0x780000U)
67530#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_19_22_SHIFT (19U)
67531/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_19_22 - reserved
67532 */
67533#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_19_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_19_22_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_19_22_MASK)
67534#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SLEEP_MASK (0x1800000U)
67535#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SLEEP_SHIFT (23U)
67536/*! SLEEP - SLEEP
67537 * 0b11..Force into sleep mode
67538 * 0b00..NO
67539 * 0b01..EARLY
67540 * 0b10..LATE
67541 */
67542#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SLEEP_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_SLEEP_MASK)
67543#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_25_29_MASK (0x3E000000U)
67544#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_25_29_SHIFT (25U)
67545/*! IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_25_29 - reserved
67546 */
67547#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_25_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_25_29_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_reserved_25_29_MASK)
67548#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_pad_ctl_MASK (0x40000000U)
67549#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_pad_ctl_SHIFT (30U)
67550/*! update_pad_ctl - update lock for pad control
67551 */
67552#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_pad_ctl(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_pad_ctl_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_pad_ctl_MASK)
67553#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_mux_mode_MASK (0x80000000U)
67554#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_mux_mode_SHIFT (31U)
67555/*! update_mux_mode - update lock for mux control
67556 */
67557#define IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_mux_mode(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_mux_mode_SHIFT)) & IOMUXD_IOMUXD_COMP_CTL_GPIO_1V8_3V3_QSPI0B_update_mux_mode_MASK)
67558/*! @} */
67559
67560/*! @name IOMUXD_GROUP_3_1 - na */
67561/*! @{ */
67562#define IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS0_B_MASK (0x1U)
67563#define IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS0_B_SHIFT (0U)
67564/*! QSPI0B_SS0_B - wakeup from QSPI0B_SS0_B
67565 */
67566#define IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS0_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS0_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS0_B_MASK)
67567#define IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS1_B_MASK (0x2U)
67568#define IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS1_B_SHIFT (1U)
67569/*! QSPI0B_SS1_B - wakeup from QSPI0B_SS1_B
67570 */
67571#define IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS1_B(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS1_B_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_QSPI0B_SS1_B_MASK)
67572#define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_2_31_MASK (0xFFFFFFFCU)
67573#define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_2_31_SHIFT (2U)
67574/*! iomuxd_group_3_1_reserved_2_31 - reserved
67575 */
67576#define IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_2_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_2_31_SHIFT)) & IOMUXD_IOMUXD_GROUP_3_1_iomuxd_group_3_1_reserved_2_31_MASK)
67577/*! @} */
67578
67579
67580/*!
67581 * @}
67582 */ /* end of group IOMUXD_Register_Masks */
67583
67584
67585/* IOMUXD - Peripheral instance base addresses */
67586/** Peripheral IOMUXD base address */
67587#define IOMUXD_BASE (0x33F80000u)
67588/** Peripheral IOMUXD base pointer */
67589#define IOMUXD ((IOMUXD_Type *)IOMUXD_BASE)
67590/** Array initializer of IOMUXD peripheral base addresses */
67591#define IOMUXD_BASE_ADDRS { IOMUXD_BASE }
67592/** Array initializer of IOMUXD peripheral base pointers */
67593#define IOMUXD_BASE_PTRS { IOMUXD }
67594
67595/*!
67596 * @}
67597 */ /* end of group IOMUXD_Peripheral_Access_Layer */
67598
67599
67600/* ----------------------------------------------------------------------------
67601 -- IRIS_MVPL Peripheral Access Layer
67602 ---------------------------------------------------------------------------- */
67603
67604/*!
67605 * @addtogroup IRIS_MVPL_Peripheral_Access_Layer IRIS_MVPL Peripheral Access Layer
67606 * @{
67607 */
67608
67609/** IRIS_MVPL - Register Layout Typedef */
67610typedef struct {
67611 __IO uint32_t IPIDENTIFIER; /**< IP Identifier for this SEERIS derivate., offset: 0x0 */
67612 uint8_t RESERVED_0[60];
67613 __I uint32_t COMCTRL_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x40 */
67614 __I uint32_t COMCTRL_LOCKSTATUS; /**< Protection status of this address block., offset: 0x44 */
67615 __IO uint32_t COMCTRL_USERINTERRUPTMASK0; /**< Interrupt UserMask register 0, offset: 0x48 */
67616 __IO uint32_t COMCTRL_USERINTERRUPTMASK1; /**< Interrupt UserMask register 1, offset: 0x4C */
67617 __I uint32_t COMCTRL_INTERRUPTENABLE0; /**< Interrupt Enable register 0, offset: 0x50 */
67618 __I uint32_t COMCTRL_INTERRUPTENABLE1; /**< Interrupt Enable register 1, offset: 0x54 */
67619 __O uint32_t COMCTRL_INTERRUPTPRESET0; /**< Interrupt Preset register 0, offset: 0x58 */
67620 __O uint32_t COMCTRL_INTERRUPTPRESET1; /**< Interrupt Preset register 1, offset: 0x5C */
67621 __O uint32_t COMCTRL_INTERRUPTCLEAR0; /**< Interrupt Clear register 0, offset: 0x60 */
67622 __O uint32_t COMCTRL_INTERRUPTCLEAR1; /**< Interrupt Clear register 1, offset: 0x64 */
67623 __I uint32_t COMCTRL_INTERRUPTSTATUS0; /**< Interrupt Status register 0, offset: 0x68 */
67624 __I uint32_t COMCTRL_INTERRUPTSTATUS1; /**< Interrupt Status register 1, offset: 0x6C */
67625 uint8_t RESERVED_1[16];
67626 __I uint32_t USERINTERRUPTENABLE0; /**< Interrupt Enable register 0 for user mode access, offset: 0x80 */
67627 __I uint32_t USERINTERRUPTENABLE1; /**< Interrupt Enable register 1 for user mode access, offset: 0x84 */
67628 __O uint32_t USERINTERRUPTPRESET0; /**< Interrupt Preset register 0, offset: 0x88 */
67629 __O uint32_t USERINTERRUPTPRESET1; /**< Interrupt Preset register 1, offset: 0x8C */
67630 __O uint32_t USERINTERRUPTCLEAR0; /**< Interrupt Clear register 0, offset: 0x90 */
67631 __O uint32_t USERINTERRUPTCLEAR1; /**< Interrupt Clear register 1, offset: 0x94 */
67632 __I uint32_t USERINTERRUPTSTATUS0; /**< Interrupt Status register 0, offset: 0x98 */
67633 __I uint32_t USERINTERRUPTSTATUS1; /**< Interrupt Status register 1, offset: 0x9C */
67634 uint8_t RESERVED_2[96];
67635 __IO uint32_t GENERALPURPOSE; /**< General purpose config memory, offset: 0x100 */
67636 uint8_t RESERVED_3[764];
67637 __I uint32_t CMDSEQ_HIF; /**< Command input buffer, offset: 0x400 */
67638 uint8_t RESERVED_4[252];
67639 __I uint32_t CMDSEQ_LOCKUNLOCKHIF; /**< Register to change the protection status of this address block., offset: 0x500 */
67640 __I uint32_t CMDSEQ_LOCKSTATUSHIF; /**< Protection status of this address block., offset: 0x504 */
67641 uint8_t RESERVED_5[120];
67642 __I uint32_t CMDSEQ_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x580 */
67643 __I uint32_t CMDSEQ_LOCKSTATUS; /**< Protection status of this address block., offset: 0x584 */
67644 __IO uint32_t CMDSEQ_BUFFERADDRESS; /**< Command buffer address register, offset: 0x588 */
67645 __IO uint32_t CMDSEQ_BUFFERSIZE; /**< Command buffer size register, offset: 0x58C */
67646 __IO uint32_t CMDSEQ_WATERMARKCONTROL; /**< Watermark Control register, offset: 0x590 */
67647 __O uint32_t CMDSEQ_CONTROL; /**< Control register, offset: 0x594 */
67648 __I uint32_t CMDSEQ_STATUS; /**< Status register, offset: 0x598 */
67649 __IO uint32_t CMDSEQ_PREFETCHWINDOWSTART; /**< PrefetchWindowStart register, offset: 0x59C */
67650 __IO uint32_t CMDSEQ_PREFETCHWINDOWEND; /**< PrefetchWindowEnd register, offset: 0x5A0 */
67651 uint8_t RESERVED_6[604];
67652 __I uint32_t SAFETYLOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x800 */
67653 __I uint32_t SAFETYLOCKSTATUS; /**< Protection status of this address block., offset: 0x804 */
67654 __IO uint32_t STORE9_SAFETYMASK; /**< Safety mask for store9, offset: 0x808 */
67655 __IO uint32_t EXTDST0_SAFETYMASK; /**< Safety mask for extdst0, offset: 0x80C */
67656 __IO uint32_t EXTDST4_SAFETYMASK; /**< Safety mask for extdst4, offset: 0x810 */
67657 __IO uint32_t EXTDST1_SAFETYMASK; /**< Safety mask for extdst1, offset: 0x814 */
67658 __IO uint32_t EXTDST5_SAFETYMASK; /**< Safety mask for extdst5, offset: 0x818 */
67659 uint8_t RESERVED_7[4];
67660 __I uint32_t FETCHDECODE32_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x820 */
67661 __I uint32_t FETCHDECODE32_LOCKSTATUS; /**< Protection status of this address block., offset: 0x824 */
67662 __IO uint32_t FETCHDECODE_DYNAMIC; /**< Dynamic pixel engine configuration for fetchdecode9, offset: 0x828 */
67663 __I uint32_t FETCHDECODE_STATUS; /**< Status information for pixel engine configuration of fetchdecode9, offset: 0x82C */
67664 uint8_t RESERVED_8[16];
67665 __I uint32_t FETCHWARP64_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x840 */
67666 __I uint32_t FETCHWARP64_LOCKSTATUS; /**< Protection status of this address block., offset: 0x844 */
67667 __IO uint32_t FETCHWARP64_DYNAMIC; /**< Dynamic pixel engine configuration for fetchwarp9, offset: 0x848 */
67668 __I uint32_t FETCHWARP64_STATUS; /**< Status information for pixel engine configuration of fetchwarp9, offset: 0x84C */
67669 __I uint32_t FETCHECO80_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x850 */
67670 __I uint32_t FETCHECO80_LOCKSTATUS; /**< Protection status of this address block., offset: 0x854 */
67671 __I uint32_t FETCHECO_STATUS; /**< Status information for pixel engine configuration of fetcheco9, offset: 0x858 */
67672 uint8_t RESERVED_9[4];
67673 __I uint32_t ROP_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x860 */
67674 __I uint32_t ROP_LOCKSTATUS; /**< Protection status of this address block., offset: 0x864 */
67675 __IO uint32_t ROP_DYNAMIC; /**< Dynamic pixel engine configuration for rop9, offset: 0x868 */
67676 __I uint32_t ROP_STATUS; /**< Status information for pixel engine configuration of rop9, offset: 0x86C */
67677 uint8_t RESERVED_10[16];
67678 __I uint32_t CLUT_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x880 */
67679 __I uint32_t CLUT_LOCKSTATUS; /**< Protection status of this address block., offset: 0x884 */
67680 __IO uint32_t CLUT_DYNAMIC; /**< Dynamic pixel engine configuration for clut9, offset: 0x888 */
67681 __I uint32_t CLUT_STATUS; /**< Status information for pixel engine configuration of clut9, offset: 0x88C */
67682 uint8_t RESERVED_11[16];
67683 __I uint32_t MATRIX160_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x8A0 */
67684 __I uint32_t MATRIX160_LOCKSTATUS; /**< Protection status of this address block., offset: 0x8A4 */
67685 __IO uint32_t MATRIX_DYNAMIC; /**< Dynamic pixel engine configuration for matrix9, offset: 0x8A8 */
67686 __I uint32_t MATRIX_STATUS; /**< Status information for pixel engine configuration of matrix9, offset: 0x8AC */
67687 uint8_t RESERVED_12[16];
67688 __I uint32_t HSCALER192_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x8C0 */
67689 __I uint32_t HSCALER192_LOCKSTATUS; /**< Protection status of this address block., offset: 0x8C4 */
67690 __IO uint32_t HSCALER_DYNAMIC; /**< Dynamic pixel engine configuration for hscaler9, offset: 0x8C8 */
67691 __I uint32_t HSCALER_STATUS; /**< Status information for pixel engine configuration of hscaler9, offset: 0x8CC */
67692 uint8_t RESERVED_13[16];
67693 __I uint32_t VSCALER224_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x8E0 */
67694 __I uint32_t VSCALER224_LOCKSTATUS; /**< Protection status of this address block., offset: 0x8E4 */
67695 __IO uint32_t VSCALER_DYNAMIC; /**< Dynamic pixel engine configuration for vscaler9, offset: 0x8E8 */
67696 __I uint32_t VSCALER_STATUS; /**< Status information for pixel engine configuration of vscaler9, offset: 0x8EC */
67697 uint8_t RESERVED_14[16];
67698 __I uint32_t FILTER_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x900 */
67699 __I uint32_t FILTER_LOCKSTATUS; /**< Protection status of this address block., offset: 0x904 */
67700 __IO uint32_t FILTER_DYNAMIC; /**< Dynamic pixel engine configuration for filter9, offset: 0x908 */
67701 __I uint32_t FILTER_STATUS; /**< Status information for pixel engine configuration of filter9, offset: 0x90C */
67702 uint8_t RESERVED_15[16];
67703 __I uint32_t BLITBLEND_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x920 */
67704 __I uint32_t BLITBLEND_LOCKSTATUS; /**< Protection status of this address block., offset: 0x924 */
67705 __IO uint32_t BLITBLEND_DYNAMIC; /**< Dynamic pixel engine configuration for blitblend9, offset: 0x928 */
67706 __I uint32_t BLITBLEND_STATUS; /**< Status information for pixel engine configuration of blitblend9, offset: 0x92C */
67707 uint8_t RESERVED_16[16];
67708 __I uint32_t STORE_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x940 */
67709 __I uint32_t STORE_LOCKSTATUS; /**< Protection status of this address block., offset: 0x944 */
67710 __IO uint32_t STORE9_STATIC; /**< Static pixel engine configuration for store9, offset: 0x948 */
67711 __IO uint32_t STORE_DYNAMIC; /**< Dynamic pixel engine configuration for store9, offset: 0x94C */
67712 __I uint32_t STORE9_REQUEST; /**< ShadowLoadRequest register for endpoint store9, offset: 0x950 */
67713 __O uint32_t STORE9_TRIGGER; /**< Trigger bits for pixel engine configuration of store9, offset: 0x954 */
67714 __I uint32_t STORE_STATUS; /**< Status information for pixel engine configuration of store9, offset: 0x958 */
67715 uint8_t RESERVED_17[4];
67716 __I uint32_t CONSTFRAME352_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x960 */
67717 __I uint32_t CONSTFRAME352_LOCKSTATUS; /**< Protection status of this address block., offset: 0x964 */
67718 __I uint32_t CONSTFRAME352_STATUS; /**< Status information for pixel engine configuration of constframe0, offset: 0x968 */
67719 uint8_t RESERVED_18[20];
67720 __I uint32_t EXTDST384_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x980 */
67721 __I uint32_t EXTDST384_LOCKSTATUS; /**< Protection status of this address block., offset: 0x984 */
67722 __IO uint32_t EXTDST384_STATIC; /**< Static pixel engine configuration for extdst0, offset: 0x988 */
67723 __IO uint32_t EXTDST384_DYNAMIC; /**< Dynamic pixel engine configuration for extdst0, offset: 0x98C */
67724 __I uint32_t EXTDST384_REQUEST; /**< ShadowLoadRequest register for endpoint extdst0, offset: 0x990 */
67725 __O uint32_t EXTDST384_TRIGGER; /**< Trigger bits for pixel engine configuration of extdst0, offset: 0x994 */
67726 __I uint32_t EXTDST384_STATUS; /**< Status information for pixel engine configuration of extdst0, offset: 0x998 */
67727 uint8_t RESERVED_19[4];
67728 __I uint32_t CONSTFRAME416_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x9A0 */
67729 __I uint32_t CONSTFRAME416_LOCKSTATUS; /**< Protection status of this address block., offset: 0x9A4 */
67730 __I uint32_t CONSTFRAME416_STATUS; /**< Status information for pixel engine configuration of constframe4, offset: 0x9A8 */
67731 uint8_t RESERVED_20[20];
67732 __I uint32_t EXTDST448_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x9C0 */
67733 __I uint32_t EXTDST448_LOCKSTATUS; /**< Protection status of this address block., offset: 0x9C4 */
67734 __IO uint32_t EXTDST448_STATIC; /**< Static pixel engine configuration for extdst4, offset: 0x9C8 */
67735 __IO uint32_t EXTDST448_DYNAMIC; /**< Dynamic pixel engine configuration for extdst4, offset: 0x9CC */
67736 __I uint32_t EXTDST448_REQUEST; /**< ShadowLoadRequest register for endpoint extdst4, offset: 0x9D0 */
67737 __O uint32_t EXTDST448_TRIGGER; /**< Trigger bits for pixel engine configuration of extdst4, offset: 0x9D4 */
67738 __I uint32_t EXTDST448_STATUS; /**< Status information for pixel engine configuration of extdst4, offset: 0x9D8 */
67739 uint8_t RESERVED_21[4];
67740 __I uint32_t CONSTFRAME480_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x9E0 */
67741 __I uint32_t CONSTFRAME480_LOCKSTATUS; /**< Protection status of this address block., offset: 0x9E4 */
67742 __I uint32_t CONSTFRAME480_STATUS; /**< Status information for pixel engine configuration of constframe1, offset: 0x9E8 */
67743 uint8_t RESERVED_22[20];
67744 __I uint32_t EXTDST512_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA00 */
67745 __I uint32_t EXTDST512_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA04 */
67746 __IO uint32_t EXTDST1_STATIC; /**< Static pixel engine configuration for extdst1, offset: 0xA08 */
67747 __IO uint32_t EXTDST1_DYNAMIC; /**< Dynamic pixel engine configuration for extdst1, offset: 0xA0C */
67748 __I uint32_t EXTDST1_REQUEST; /**< ShadowLoadRequest register for endpoint extdst1, offset: 0xA10 */
67749 __O uint32_t EXTDST1_TRIGGER; /**< Trigger bits for pixel engine configuration of extdst1, offset: 0xA14 */
67750 __I uint32_t EXTDST512_STATUS; /**< Status information for pixel engine configuration of extdst1, offset: 0xA18 */
67751 uint8_t RESERVED_23[4];
67752 __I uint32_t CONSTFRAME_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA20 */
67753 __I uint32_t CONSTFRAME_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA24 */
67754 __I uint32_t CONSTFRAME_STATUS; /**< Status information for pixel engine configuration of constframe5, offset: 0xA28 */
67755 uint8_t RESERVED_24[20];
67756 __I uint32_t EXTDST544_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA40 */
67757 __I uint32_t EXTDST544_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA44 */
67758 __IO uint32_t EXTDST5_STATIC; /**< Static pixel engine configuration for extdst5, offset: 0xA48 */
67759 __IO uint32_t EXTDST5_DYNAMIC; /**< Dynamic pixel engine configuration for extdst5, offset: 0xA4C */
67760 __I uint32_t EXTDST5_REQUEST; /**< ShadowLoadRequest register for endpoint extdst5, offset: 0xA50 */
67761 __O uint32_t EXTDST5_TRIGGER; /**< Trigger bits for pixel engine configuration of extdst5, offset: 0xA54 */
67762 __I uint32_t EXTDST544_STATUS; /**< Status information for pixel engine configuration of extdst5, offset: 0xA58 */
67763 uint8_t RESERVED_25[4];
67764 __I uint32_t FETCHWARP608_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA60 */
67765 __I uint32_t FETCHWARP608_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA64 */
67766 __IO uint32_t FETCHWARP608_DYNAMIC; /**< Dynamic pixel engine configuration for fetchwarp2, offset: 0xA68 */
67767 __I uint32_t FETCHWARP608_STATUS; /**< Status information for pixel engine configuration of fetchwarp2, offset: 0xA6C */
67768 __I uint32_t FETCHECO624_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA70 */
67769 __I uint32_t FETCHECO624_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA74 */
67770 __I uint32_t FETCHECO2_STATUS; /**< Status information for pixel engine configuration of fetcheco2, offset: 0xA78 */
67771 uint8_t RESERVED_26[4];
67772 __I uint32_t FETCHDECODE0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA80 */
67773 __I uint32_t FETCHDECODE0_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA84 */
67774 __IO uint32_t FETCHDECODE0_DYNAMIC; /**< Dynamic pixel engine configuration for fetchdecode0, offset: 0xA88 */
67775 __I uint32_t FETCHDECODE0_STATUS; /**< Status information for pixel engine configuration of fetchdecode0, offset: 0xA8C */
67776 __I uint32_t FETCHECO656_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA90 */
67777 __I uint32_t FETCHECO656_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA94 */
67778 __I uint32_t FETCHECO0_STATUS; /**< Status information for pixel engine configuration of fetcheco0, offset: 0xA98 */
67779 uint8_t RESERVED_27[4];
67780 __I uint32_t FETCHDECODE672_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xAA0 */
67781 __I uint32_t FETCHDECODE672_LOCKSTATUS; /**< Protection status of this address block., offset: 0xAA4 */
67782 __IO uint32_t FETCHDECODE1_DYNAMIC; /**< Dynamic pixel engine configuration for fetchdecode1, offset: 0xAA8 */
67783 __I uint32_t FETCHDECODE1_STATUS; /**< Status information for pixel engine configuration of fetchdecode1, offset: 0xAAC */
67784 __I uint32_t FETCHECO688_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xAB0 */
67785 __I uint32_t FETCHECO688_LOCKSTATUS; /**< Protection status of this address block., offset: 0xAB4 */
67786 __I uint32_t FETCHECO1_STATUS; /**< Status information for pixel engine configuration of fetcheco1, offset: 0xAB8 */
67787 uint8_t RESERVED_28[4];
67788 __I uint32_t FETCHLAYER704_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xAC0 */
67789 __I uint32_t FETCHLAYER704_LOCKSTATUS; /**< Protection status of this address block., offset: 0xAC4 */
67790 __I uint32_t FETCHLAYER704_STATUS; /**< Status information for pixel engine configuration of fetchlayer0, offset: 0xAC8 */
67791 uint8_t RESERVED_29[20];
67792 __I uint32_t MATRIX736_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xAE0 */
67793 __I uint32_t MATRIX736_LOCKSTATUS; /**< Protection status of this address block., offset: 0xAE4 */
67794 __IO uint32_t MATRIX4_DYNAMIC; /**< Dynamic pixel engine configuration for matrix4, offset: 0xAE8 */
67795 __I uint32_t MATRIX4_STATUS; /**< Status information for pixel engine configuration of matrix4, offset: 0xAEC */
67796 uint8_t RESERVED_30[16];
67797 __I uint32_t HSCALER768_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xB00 */
67798 __I uint32_t HSCALER768_LOCKSTATUS; /**< Protection status of this address block., offset: 0xB04 */
67799 __IO uint32_t HSCALER4_DYNAMIC; /**< Dynamic pixel engine configuration for hscaler4, offset: 0xB08 */
67800 __I uint32_t HSCALER4_STATUS; /**< Status information for pixel engine configuration of hscaler4, offset: 0xB0C */
67801 uint8_t RESERVED_31[16];
67802 __I uint32_t VSCALER800_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xB20 */
67803 __I uint32_t VSCALER800_LOCKSTATUS; /**< Protection status of this address block., offset: 0xB24 */
67804 __IO uint32_t VSCALER4_DYNAMIC; /**< Dynamic pixel engine configuration for vscaler4, offset: 0xB28 */
67805 __I uint32_t VSCALER4_STATUS; /**< Status information for pixel engine configuration of vscaler4, offset: 0xB2C */
67806 uint8_t RESERVED_32[16];
67807 __I uint32_t MATRIX832_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xB40 */
67808 __I uint32_t MATRIX832_LOCKSTATUS; /**< Protection status of this address block., offset: 0xB44 */
67809 __IO uint32_t MATRIX5_DYNAMIC; /**< Dynamic pixel engine configuration for matrix5, offset: 0xB48 */
67810 __I uint32_t MATRIX5_STATUS; /**< Status information for pixel engine configuration of matrix5, offset: 0xB4C */
67811 uint8_t RESERVED_33[16];
67812 __I uint32_t HSCALER864_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xB60 */
67813 __I uint32_t HSCALER864_LOCKSTATUS; /**< Protection status of this address block., offset: 0xB64 */
67814 __IO uint32_t HSCALER5_DYNAMIC; /**< Dynamic pixel engine configuration for hscaler5, offset: 0xB68 */
67815 __I uint32_t HSCALER5_STATUS; /**< Status information for pixel engine configuration of hscaler5, offset: 0xB6C */
67816 uint8_t RESERVED_34[16];
67817 __I uint32_t VSCALER896_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xB80 */
67818 __I uint32_t VSCALER896_LOCKSTATUS; /**< Protection status of this address block., offset: 0xB84 */
67819 __IO uint32_t VSCALER5_DYNAMIC; /**< Dynamic pixel engine configuration for vscaler5, offset: 0xB88 */
67820 __I uint32_t VSCALER5_STATUS; /**< Status information for pixel engine configuration of vscaler5, offset: 0xB8C */
67821 uint8_t RESERVED_35[16];
67822 __I uint32_t LAYERBLEND928_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xBA0 */
67823 __I uint32_t LAYERBLEND928_LOCKSTATUS; /**< Protection status of this address block., offset: 0xBA4 */
67824 __IO uint32_t LAYERBLEND0_DYNAMIC; /**< Dynamic pixel engine configuration for layerblend0, offset: 0xBA8 */
67825 __I uint32_t LAYERBLEND0_STATUS; /**< Status information for pixel engine configuration of layerblend0, offset: 0xBAC */
67826 uint8_t RESERVED_36[16];
67827 __I uint32_t LAYERBLEND960_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xBC0 */
67828 __I uint32_t LAYERBLEND960_LOCKSTATUS; /**< Protection status of this address block., offset: 0xBC4 */
67829 __IO uint32_t LAYERBLEND1_DYNAMIC; /**< Dynamic pixel engine configuration for layerblend1, offset: 0xBC8 */
67830 __I uint32_t LAYERBLEND1_STATUS; /**< Status information for pixel engine configuration of layerblend1, offset: 0xBCC */
67831 uint8_t RESERVED_37[16];
67832 __I uint32_t LAYERBLEND992_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xBE0 */
67833 __I uint32_t LAYERBLEND99_LOCKSTATUS; /**< Protection status of this address block., offset: 0xBE4 */
67834 __IO uint32_t LAYERBLEND2_DYNAMIC; /**< Dynamic pixel engine configuration for layerblend2, offset: 0xBE8 */
67835 __I uint32_t LAYERBLEND2_STATUS; /**< Status information for pixel engine configuration of layerblend2, offset: 0xBEC */
67836 uint8_t RESERVED_38[16];
67837 __I uint32_t LAYERBLEND1024_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xC00 */
67838 __I uint32_t LAYERBLEND1024_LOCKSTATUS; /**< Protection status of this address block., offset: 0xC04 */
67839 __IO uint32_t LAYERBLEND3_DYNAMIC; /**< Dynamic pixel engine configuration for layerblend3, offset: 0xC08 */
67840 __I uint32_t LAYERBLEND3_STATUS; /**< Status information for pixel engine configuration of layerblend3, offset: 0xC0C */
67841 uint8_t RESERVED_39[1008];
67842 __I uint32_t FETCHDECODE_LOCKUNLOCK_1; /**< Register to change the protection status of this address block., offset: 0x1000 */
67843 __I uint32_t FETCHDECODE_LOCKSTATUS_1; /**< Protection status of this address block., offset: 0x1004 */
67844 __IO uint32_t FETCHDECODE_STATICCONTRO_1L; /**< Common static control options., offset: 0x1008 */
67845 __IO uint32_t FETCHDECODE_BURSTBUFFERMANAGEMENT_1; /**< AXI interface buffer management register, offset: 0x100C */
67846 __IO uint32_t FETCHDECODE_RINGBUFSTARTADDR0_1; /**< Ring buffer setup for layer 0., offset: 0x1010 */
67847 __IO uint32_t FETCHDECODE_RINGBUFWRAPADDR0_1; /**< Ring buffer setup for layer 0., offset: 0x1014 */
67848 __IO uint32_t FETCHDECODE_FRAMEPROPERTIES0_1; /**< Frame property setup for layer 0., offset: 0x1018 */
67849 __IO uint32_t FETCHDECODE_BASEADDRESS0_1; /**< Source buffer base address of layer 0., offset: 0x101C */
67850 __IO uint32_t FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1; /**< Source buffer attributes for layer 0., offset: 0x1020 */
67851 __IO uint32_t FETCHDECODE_SOURCEBUFFERDIMENSION0_1; /**< Source buffer dimension of layer 0., offset: 0x1024 */
67852 __IO uint32_t FETCHDECODE_COLORCOMPONENTBITS0_1; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x1028 */
67853 __IO uint32_t FETCHDECODE_COLORCOMPONENTSHIFT0_1; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x102C */
67854 __IO uint32_t FETCHDECODE_LAYEROFFSET0_1; /**< Position of layer 0 within the destination frame., offset: 0x1030 */
67855 __IO uint32_t FETCHDECODE_CLIPWINDOWOFFSET0_1; /**< Clip window position for layer 0., offset: 0x1034 */
67856 __IO uint32_t FETCHDECODE_CLIPWINDOWDIMENSIONS0_1; /**< Clip window size for layer 0., offset: 0x1038 */
67857 __IO uint32_t FETCHDECODE_CONSTANTCOLOR0_1; /**< Constant color for layer 0., offset: 0x103C */
67858 __IO uint32_t FETCHDECODE_LAYERPROPERTY0_1; /**< Common properties of layer 0., offset: 0x1040 */
67859 __IO uint32_t FETCHDECODE_FRAMEDIMENSIONS_1; /**< Output frame dimension., offset: 0x1044 */
67860 __IO uint32_t FETCHDECODE_FRAMERESAMPLING_1; /**< Resampling options for output frame., offset: 0x1048 */
67861 __IO uint32_t FETCHDECODE_DECODECONTROL_1; /**< Control options for RLAD decompression., offset: 0x104C */
67862 __IO uint32_t FETCHDECODE_SOURCEBUFFERLENGTH_1; /**< Source buffer length for compressed data., offset: 0x1050 */
67863 __IO uint32_t FETCHDECODE_CONTROL_1; /**< Shared common control settings for all layers., offset: 0x1054 */
67864 __O uint32_t FETCHDECODE_CONTROLTRIGGER_1; /**< Shadow load trigger., offset: 0x1058 */
67865 __O uint32_t FETCHDECODE_START_1; /**< Frame start trigger., offset: 0x105C */
67866 __I uint32_t FETCHDECODE_FETCHTYPE_1; /**< Fetch unit type., offset: 0x1060 */
67867 __IO uint32_t FETCHDECODE_DECODERSTATUS_1; /**< Status information of the RLAD decoder., offset: 0x1064 */
67868 __I uint32_t FETCHDECODE_READADDRESS0_1; /**< Ring buffer synchronization for layer 0., offset: 0x1068 */
67869 __I uint32_t FETCHDECODE_BURSTBUFFERPROPERTIES_1; /**< Burst buffer properties., offset: 0x106C */
67870 __IO uint32_t FETCHDECODE_STATUS_1; /**< Status informations., offset: 0x1070 */
67871 __I uint32_t FETCHDECODE_HIDDENSTATUS_1; /**< Hidden status informations., offset: 0x1074 */
67872 uint8_t RESERVED_40[904];
67873 __IO uint32_t COLORPALETTE_1; /**< Color palette look up table., offset: 0x1400 */
67874 uint8_t RESERVED_41[1020];
67875 __I uint32_t FETCHWARP9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x1800 */
67876 __I uint32_t FETCHWARP9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x1804 */
67877 __IO uint32_t FETCHWARP9_STATICCONTROL; /**< Common static control options., offset: 0x1808 */
67878 __IO uint32_t FETCHWARP9_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x180C */
67879 __IO uint32_t FETCHWARP9_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x1810 */
67880 __IO uint32_t FETCHWARP9_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x1814 */
67881 __IO uint32_t FETCHWARP9_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x1818 */
67882 __IO uint32_t FETCHWARP9_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x181C */
67883 __IO uint32_t FETCHWARP9_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x1820 */
67884 __IO uint32_t FETCHWARP9_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x1824 */
67885 __IO uint32_t FETCHWARP9_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x1828 */
67886 __IO uint32_t FETCHWARP9_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x182C */
67887 __IO uint32_t FETCHWARP9_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x1830 */
67888 __IO uint32_t FETCHWARP9_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x1834 */
67889 __IO uint32_t FETCHWARP9_BASEADDRESS1; /**< Source buffer base address of layer 1., offset: 0x1838 */
67890 __IO uint32_t FETCHWARP9_SOURCEBUFFERATTRIBUTES1; /**< Source buffer attributes for layer 1., offset: 0x183C */
67891 __IO uint32_t FETCHWARP9_SOURCEBUFFERDIMENSION1; /**< Source buffer dimensions of layer 1,, offset: 0x1840 */
67892 __IO uint32_t FETCHWARP9_COLORCOMPONENTBITS1; /**< Size of color components for RGB, YUV and index formats (layer 1)., offset: 0x1844 */
67893 __IO uint32_t FETCHWARP9_COLORCOMPONENTSHIFT1; /**< Bit position of color components for RGB, YUV and index formats (layer 1)., offset: 0x1848 */
67894 __IO uint32_t FETCHWARP9_LAYEROFFSET1; /**< Position of layer 1 within the destination frame., offset: 0x184C */
67895 __IO uint32_t FETCHWARP9_CLIPWINDOWOFFSET1; /**< Clip window position for layer 1., offset: 0x1850 */
67896 __IO uint32_t FETCHWARP9_CLIPWINDOWDIMENSIONS1; /**< Clip window size for layer 1., offset: 0x1854 */
67897 __IO uint32_t FETCHWARP9_CONSTANTCOLOR1; /**< Constant color for layer 1., offset: 0x1858 */
67898 __IO uint32_t FETCHWARP9_LAYERPROPERTY1; /**< Common properties of layer 1., offset: 0x185C */
67899 __IO uint32_t FETCHWARP9_BASEADDRESS2; /**< Source buffer base address of layer 2., offset: 0x1860 */
67900 __IO uint32_t FETCHWARP9_SOURCEBUFFERATTRIBUTES2; /**< Source buffer attributes for layer 2., offset: 0x1864 */
67901 __IO uint32_t FETCHWARP9_SOURCEBUFFERDIMENSION2; /**< Source buffer dimension of layer 2., offset: 0x1868 */
67902 __IO uint32_t FETCHWARP9_COLORCOMPONENTBITS2; /**< Size of color components for RGB, YUV and index formats (layer 2)., offset: 0x186C */
67903 __IO uint32_t FETCHWARP9_COLORCOMPONENTSHIFT2; /**< Bit position of color components for RGB, YUV and index formats (layer 2)., offset: 0x1870 */
67904 __IO uint32_t FETCHWARP9_LAYEROFFSET2; /**< Position of layer 2 within the destination frame., offset: 0x1874 */
67905 __IO uint32_t FETCHWARP9_CLIPWINDOWOFFSET2; /**< Clip window position for layer 2., offset: 0x1878 */
67906 __IO uint32_t FETCHWARP9_CLIPWINDOWDIMENSIONS2; /**< Clip window size for layer 2., offset: 0x187C */
67907 __IO uint32_t FETCHWARP9_CONSTANTCOLOR2; /**< Constant color for layer 2., offset: 0x1880 */
67908 __IO uint32_t FETCHWARP9_LAYERPROPERTY2; /**< Common properties of layer 2., offset: 0x1884 */
67909 __IO uint32_t FETCHWARP9_BASEADDRESS3; /**< Source buffer base address of layer 3., offset: 0x1888 */
67910 __IO uint32_t FETCHWARP9_SOURCEBUFFERATTRIBUTES3; /**< Source buffer attributes for layer 3., offset: 0x188C */
67911 __IO uint32_t FETCHWARP9_SOURCEBUFFERDIMENSION3; /**< Source buffer dimension of layer 3., offset: 0x1890 */
67912 __IO uint32_t FETCHWARP9_COLORCOMPONENTBITS3; /**< Size of color components for RGB, YUV and index formats (layer 3)., offset: 0x1894 */
67913 __IO uint32_t FETCHWARP9_COLORCOMPONENTSHIFT3; /**< Bit position of color components for RGB, YUV and index formats (layer 3)., offset: 0x1898 */
67914 __IO uint32_t FETCHWARP9_LAYEROFFSET3; /**< Position of layer 3 within the destination frame., offset: 0x189C */
67915 __IO uint32_t FETCHWARP9_CLIPWINDOWOFFSET3; /**< Clip window position for layer 3., offset: 0x18A0 */
67916 __IO uint32_t FETCHWARP9_CLIPWINDOWDIMENSIONS3; /**< Clip window size for layer 3., offset: 0x18A4 */
67917 __IO uint32_t FETCHWARP9_CONSTANTCOLOR3; /**< Constant color for layer 3., offset: 0x18A8 */
67918 __IO uint32_t FETCHWARP9_LAYERPROPERTY3; /**< Common properties of layer 3., offset: 0x18AC */
67919 __IO uint32_t FETCHWARP9_BASEADDRESS4; /**< Source buffer base address of layer 4., offset: 0x18B0 */
67920 __IO uint32_t FETCHWARP9_SOURCEBUFFERATTRIBUTES4; /**< Source buffer attributes for layer 4., offset: 0x18B4 */
67921 __IO uint32_t FETCHWARP9_SOURCEBUFFERDIMENSION4; /**< Source buffer dimension of layer 4., offset: 0x18B8 */
67922 __IO uint32_t FETCHWARP9_COLORCOMPONENTBITS4; /**< Size of color components for RGB, YUV and index formats (layer 4)., offset: 0x18BC */
67923 __IO uint32_t FETCHWARP9_COLORCOMPONENTSHIFT4; /**< Bit position of color components for RGB, YUV and index formats (layer 4)., offset: 0x18C0 */
67924 __IO uint32_t FETCHWARP9_LAYEROFFSET4; /**< Position of layer 4 within the destination frame., offset: 0x18C4 */
67925 __IO uint32_t FETCHWARP9_CLIPWINDOWOFFSET4; /**< Clip window position for layer 4., offset: 0x18C8 */
67926 __IO uint32_t FETCHWARP9_CLIPWINDOWDIMENSIONS4; /**< Clip window size for layer 4., offset: 0x18CC */
67927 __IO uint32_t FETCHWARP9_CONSTANTCOLOR4; /**< Constant color for layer 4., offset: 0x18D0 */
67928 __IO uint32_t FETCHWARP9_LAYERPROPERTY4; /**< Common properties of layer 4., offset: 0x18D4 */
67929 __IO uint32_t FETCHWARP9_BASEADDRESS5; /**< Source buffer base address of layer 5., offset: 0x18D8 */
67930 __IO uint32_t FETCHWARP9_SOURCEBUFFERATTRIBUTES5; /**< Source buffer attributes for layer 5., offset: 0x18DC */
67931 __IO uint32_t FETCHWARP9_SOURCEBUFFERDIMENSION5; /**< Source buffer dimension of layer 5., offset: 0x18E0 */
67932 __IO uint32_t FETCHWARP9_COLORCOMPONENTBITS5; /**< Size of color components for RGB, YUV and index formats (layer 5)., offset: 0x18E4 */
67933 __IO uint32_t FETCHWARP9_COLORCOMPONENTSHIFT5; /**< Bit position of color components for RGB, YUV and index formats (layer 5)., offset: 0x18E8 */
67934 __IO uint32_t FETCHWARP9_LAYEROFFSET5; /**< Position of layer 5 within the destination frame., offset: 0x18EC */
67935 __IO uint32_t FETCHWARP9_CLIPWINDOWOFFSET5; /**< Clip window position for layer 5., offset: 0x18F0 */
67936 __IO uint32_t FETCHWARP9_CLIPWINDOWDIMENSIONS5; /**< Clip window size for layer 5., offset: 0x18F4 */
67937 __IO uint32_t FETCHWARP9_CONSTANTCOLOR5; /**< Constant color for layer 5., offset: 0x18F8 */
67938 __IO uint32_t FETCHWARP9_LAYERPROPERTY5; /**< Common properties of layer 5., offset: 0x18FC */
67939 __IO uint32_t FETCHWARP9_BASEADDRESS6; /**< Source buffer base address of layer 6., offset: 0x1900 */
67940 __IO uint32_t FETCHWARP9_SOURCEBUFFERATTRIBUTES6; /**< Source buffer attributes for layer 6., offset: 0x1904 */
67941 __IO uint32_t FETCHWARP9_SOURCEBUFFERDIMENSION6; /**< Source buffer dimension of layer 6., offset: 0x1908 */
67942 __IO uint32_t FETCHWARP9_COLORCOMPONENTBITS6; /**< Size of color components for RGB, YUV and index formats (layer 6)., offset: 0x190C */
67943 __IO uint32_t FETCHWARP9_COLORCOMPONENTSHIFT6; /**< Bit position of color components for RGB, YUV and index formats (layer 6)., offset: 0x1910 */
67944 __IO uint32_t FETCHWARP9_LAYEROFFSET6; /**< Position of layer 1 within the destination frame., offset: 0x1914 */
67945 __IO uint32_t FETCHWARP9_CLIPWINDOWOFFSET6; /**< Clip window position for layer 6., offset: 0x1918 */
67946 __IO uint32_t FETCHWARP9_CLIPWINDOWDIMENSIONS6; /**< Clip window size for layer 6., offset: 0x191C */
67947 __IO uint32_t FETCHWARP9_CONSTANTCOLOR6; /**< Constant color for layer 6., offset: 0x1920 */
67948 __IO uint32_t FETCHWARP9_LAYERPROPERTY6; /**< Common properties of layer 6., offset: 0x1924 */
67949 __IO uint32_t FETCHWARP9_BASEADDRESS7; /**< Source buffer base address of layer 7., offset: 0x1928 */
67950 __IO uint32_t FETCHWARP9_SOURCEBUFFERATTRIBUTES7; /**< Source buffer stride for layer 7., offset: 0x192C */
67951 __IO uint32_t FETCHWARP9_SOURCEBUFFERDIMENSION7; /**< Source buffer dimension of layer 7., offset: 0x1930 */
67952 __IO uint32_t FETCHWARP9_COLORCOMPONENTBITS7; /**< Size of color components for RGB, YUV and index formats (layer 7)., offset: 0x1934 */
67953 __IO uint32_t FETCHWARP9_COLORCOMPONENTSHIFT7; /**< Bit position of color components for RGB, YUV and index formats (layer 7)., offset: 0x1938 */
67954 __IO uint32_t FETCHWARP9_LAYEROFFSET7; /**< Position of layer 7 within the destination frame., offset: 0x193C */
67955 __IO uint32_t FETCHWARP9_CLIPWINDOWOFFSET7; /**< Clip window position for layer 7., offset: 0x1940 */
67956 __IO uint32_t FETCHWARP9_CLIPWINDOWDIMENSIONS7; /**< Clip window size for layer 7., offset: 0x1944 */
67957 __IO uint32_t FETCHWARP9_CONSTANTCOLOR7; /**< Constant color for layer 7., offset: 0x1948 */
67958 __IO uint32_t FETCHWARP9_LAYERPROPERTY7; /**< Common properties of layer 7., offset: 0x194C */
67959 __IO uint32_t FETCHWARP9_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x1950 */
67960 __IO uint32_t FETCHWARP9_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x1954 */
67961 __IO uint32_t FETCHWARP9_WARPCONTROL; /**< Warping control options., offset: 0x1958 */
67962 __IO uint32_t FETCHWARP9_ARBSTARTX; /**< Start value X for arbitrary warping., offset: 0x195C */
67963 __IO uint32_t FETCHWARP9_ARBSTARTY; /**< Start value Y for arbitrary warping., offset: 0x1960 */
67964 __IO uint32_t FETCHWARP9_ARBDELTA; /**< Start values for delta incrementation of arbitrary warping., offset: 0x1964 */
67965 __IO uint32_t FETCHWARP9_FIRPOSITIONS; /**< FIR sequence control register., offset: 0x1968 */
67966 __IO uint32_t FETCHWARP9_FIRCOEFFICIENTS; /**< FIR coefficients register., offset: 0x196C */
67967 __IO uint32_t FETCHWARP9_CONTROL; /**< Shared common control settings for all layers., offset: 0x1970 */
67968 __I uint32_t FETCHWARP9_TRIGGERENABLE; /**< Shadow load enable flags for all layers., offset: 0x1974 */
67969 __O uint32_t FETCHWARP9_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x1978 */
67970 __O uint32_t FETCHWARP9_START; /**< Frame start trigger., offset: 0x197C */
67971 __I uint32_t FETCHWARP9_FETCHTYPE; /**< Fetch unit type., offset: 0x1980 */
67972 __I uint32_t FETCHWARP9_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x1984 */
67973 __IO uint32_t FETCHWARP9_STATUS; /**< Status informations., offset: 0x1988 */
67974 __I uint32_t FETCHWARP9_HIDDENSTATUS; /**< Hidden status informations., offset: 0x198C */
67975 uint8_t RESERVED_42[624];
67976 __I uint32_t FETCHECO9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x1C00 */
67977 __I uint32_t FETCHECO9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x1C04 */
67978 __IO uint32_t FETCHECO9_STATICCONTROL; /**< Common static control options., offset: 0x1C08 */
67979 __IO uint32_t FETCHECO9_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x1C0C */
67980 __IO uint32_t FETCHECO9_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x1C10 */
67981 __IO uint32_t FETCHECO9_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x1C14 */
67982 __IO uint32_t FETCHECO9_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x1C18 */
67983 __IO uint32_t FETCHECO9_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x1C1C */
67984 __IO uint32_t FETCHECO9_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x1C20 */
67985 __IO uint32_t FETCHECO9_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x1C24 */
67986 __IO uint32_t FETCHECO9_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x1C28 */
67987 __IO uint32_t FETCHECO9_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x1C2C */
67988 __IO uint32_t FETCHECO9_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x1C30 */
67989 __IO uint32_t FETCHECO9_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x1C34 */
67990 __IO uint32_t FETCHECO9_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x1C38 */
67991 __IO uint32_t FETCHECO9_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x1C3C */
67992 __IO uint32_t FETCHECO9_CONTROL; /**< Shared common control settings for all layers., offset: 0x1C40 */
67993 __O uint32_t FETCHECO9_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x1C44 */
67994 __O uint32_t FETCHECO9_START; /**< Frame start trigger., offset: 0x1C48 */
67995 __I uint32_t FETCHECO9_FETCHTYPE; /**< Fetch unit type., offset: 0x1C4C */
67996 __I uint32_t FETCHECO9_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x1C50 */
67997 __I uint32_t FETCHECO9_HIDDENSTATUS; /**< Hidden status informations., offset: 0x1C54 */
67998 uint8_t RESERVED_43[936];
67999 __I uint32_t ROP9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x2000 */
68000 __I uint32_t ROP9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x2004 */
68001 __IO uint32_t ROP9_STATICCONTROL; /**< Raster Operation static control register, offset: 0x2008 */
68002 __IO uint32_t ROP9_CONTROL; /**< Raster Operation control register, offset: 0x200C */
68003 __IO uint32_t ROP9_RASTEROPERATIONINDICES; /**< ROP operation indices, offset: 0x2010 */
68004 __I uint32_t ROP9_PRIMCONTROLWORD; /**< Value of last received primary control word, offset: 0x2014 */
68005 __I uint32_t ROP9_SECCONTROLWORD; /**< Value of last received secondary control word, offset: 0x2018 */
68006 __I uint32_t ROP9_TERTCONTROLWORD; /**< Value of last received tertiary control word, offset: 0x201C */
68007 uint8_t RESERVED_44[992];
68008 __I uint32_t CLUT9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x2400 */
68009 __I uint32_t CLUT9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x2404 */
68010 __IO uint32_t CLUT9_STATICCONTROL; /**< CLUT static control register, offset: 0x2408 */
68011 __IO uint32_t CLUT9_UNSHADOWEDCONTROL; /**< CLUT unshadowed control register, offset: 0x240C */
68012 __IO uint32_t CLUT9_CONTROL; /**< CLUT control register, offset: 0x2410 */
68013 __IO uint32_t CLUT9_STATUS; /**< CLUT status register, offset: 0x2414 */
68014 __I uint32_t CLUT9_LASTCONTROLWORD; /**< Value of last received control word, for debugging, offset: 0x2418 */
68015 uint8_t RESERVED_45[996];
68016 __IO uint32_t CLUT9_LUT; /**< Look Up Table, offset: 0x2800 */
68017 uint8_t RESERVED_46[1020];
68018 __I uint32_t MATRIX9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x2C00 */
68019 __I uint32_t MATRIX9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x2C04 */
68020 __IO uint32_t MATRIX9_STATICCONTROL; /**< Color Matrix static control register, offset: 0x2C08 */
68021 __IO uint32_t MATRIX9_CONTROL; /**< Color Matrix control register, offset: 0x2C0C */
68022 __IO uint32_t MATRIX9_RED0; /**< Matrix values for calculation of the red output value., offset: 0x2C10 */
68023 __IO uint32_t MATRIX9_RED1; /**< Matrix values for calculation of the red output value., offset: 0x2C14 */
68024 __IO uint32_t MATRIX9_GREEN0; /**< Matrix values for calculation of the green output value., offset: 0x2C18 */
68025 __IO uint32_t MATRIX9_GREEN1; /**< Matrix values for calculation of the green output value., offset: 0x2C1C */
68026 __IO uint32_t MATRIX9_BLUE0; /**< Matrix values for calculation of the blue output value., offset: 0x2C20 */
68027 __IO uint32_t MATRIX9_BLUE1; /**< Matrix values for calculation of the blue output value., offset: 0x2C24 */
68028 __IO uint32_t MATRIX9_ALPHA0; /**< Matrix values for calculation of the alpha output value., offset: 0x2C28 */
68029 __IO uint32_t MATRIX9_ALPHA1; /**< Matrix values for calculation of the alpha output value., offset: 0x2C2C */
68030 __IO uint32_t MATRIX9_OFFSETVECTOR0; /**< Offset vectors for red and green output., offset: 0x2C30 */
68031 __IO uint32_t MATRIX9_OFFSETVECTOR1; /**< Offset vectors for blue and alpha output., offset: 0x2C34 */
68032 __I uint32_t MATRIX9_LASTCONTROLWORD; /**< Value of last received control word, for debugging., offset: 0x2C38 */
68033 uint8_t RESERVED_47[964];
68034 __I uint32_t HSCALER9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x3000 */
68035 __I uint32_t HSCALER9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x3004 */
68036 __IO uint32_t HSCALER9_STATICCONTROL; /**< Static control settings that must typically be setup once only., offset: 0x3008 */
68037 __IO uint32_t HSCALER9_SETUP1; /**< Phase interpolator setup., offset: 0x300C */
68038 __IO uint32_t HSCALER9_SETUP2; /**< Phase interpolator setup., offset: 0x3010 */
68039 __IO uint32_t HSCALER9_CONTROL; /**< Scaler operation control., offset: 0x3014 */
68040 uint8_t RESERVED_48[1000];
68041 __I uint32_t VSCALER9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x3400 */
68042 __I uint32_t VSCALER9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x3404 */
68043 __IO uint32_t VSCALER9_STATICCONTROL; /**< Static control settings that must typically be setup once only., offset: 0x3408 */
68044 __IO uint32_t VSCALER9_SETUP1; /**< Phase interpolator setup., offset: 0x340C */
68045 __IO uint32_t VSCALER9_SETUP2; /**< Phase interpolator setup, selected if input and output field polarity is 0., offset: 0x3410 */
68046 __IO uint32_t VSCALER9_SETUP3; /**< Phase interpolator setup, selected if input field polarity is 1 and output field polarity is 0., offset: 0x3414 */
68047 __IO uint32_t VSCALER9_SETUP4; /**< Phase interpolator setup, selected if input field polarity is 0 and output field polarity is 1., offset: 0x3418 */
68048 __IO uint32_t VSCALER9_SETUP5; /**< Phase interpolator setup, selected if input and output field polarity is 1., offset: 0x341C */
68049 __IO uint32_t VSCALER9_CONTROL; /**< Scaler operation control., offset: 0x3420 */
68050 uint8_t RESERVED_49[988];
68051 __I uint32_t FILTER9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x3800 */
68052 __I uint32_t FILTER9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x3804 */
68053 __IO uint32_t FILTER9_STATICCONTROL; /**< Static control settings that must typically be setup once only., offset: 0x3808 */
68054 __IO uint32_t FILTER9_CONTROL; /**< Filter operation main control., offset: 0x380C */
68055 __IO uint32_t FILTER9_FIR_CONTROL; /**< FIR filter operation control., offset: 0x3810 */
68056 __IO uint32_t FILTER9_COEFFICIENTS0; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x3814 */
68057 __IO uint32_t FILTER9_COEFFICIENTS1; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x3818 */
68058 __IO uint32_t FILTER9_COEFFICIENTS2; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x381C */
68059 __IO uint32_t FILTER9_COEFFICIENTS3; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x3820 */
68060 __IO uint32_t FILTER9_COEFFICIENTS4; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x3824 */
68061 __IO uint32_t FILTER9_COEFFICIENTS5; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x3828 */
68062 __IO uint32_t FILTER9_COEFFICIENTS6; /**< FIR coefficients[column][row] for 5x5 window for filter_mode FIR., offset: 0x382C */
68063 uint8_t RESERVED_50[976];
68064 __I uint32_t BLITBLEND9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x3C00 */
68065 __I uint32_t BLITBLEND9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x3C04 */
68066 __IO uint32_t BLITBLEND9_STATICCONTROL; /**< BlitBlend static control register, offset: 0x3C08 */
68067 __IO uint32_t BLITBLEND9_CONTROL; /**< BlitBlend control register, offset: 0x3C0C */
68068 __IO uint32_t BLITBLEND9_NEUTRALBORDER; /**< Neutral border setup register, offset: 0x3C10 */
68069 __IO uint32_t BLITBLEND9_CONSTANTCOLOR; /**< Constant color register, offset: 0x3C14 */
68070 __IO uint32_t BLITBLEND9_COLORREDBLENDFUNCTION; /**< Open GL RGB blending factors, offset: 0x3C18 */
68071 __IO uint32_t BLITBLEND9_COLORGREENBLENDFUNCTION; /**< Open GL RGB blending factors, offset: 0x3C1C */
68072 __IO uint32_t BLITBLEND9_COLORBLUEBLENDFUNCTION; /**< Open GL RGB blending factors, offset: 0x3C20 */
68073 __IO uint32_t BLITBLEND9_ALPHABLENDFUNCTION; /**< Open GL alpha blending factors, offset: 0x3C24 */
68074 __IO uint32_t BLITBLEND9_BLENDMODE1; /**< Open GL and Open VG blending modes for colors red and green, offset: 0x3C28 */
68075 __IO uint32_t BLITBLEND9_BLENDMODE2; /**< Open GL and Open VG blending modes for color blue and alpha, offset: 0x3C2C */
68076 __IO uint32_t BLITBLEND9_DIRECTSETUP; /**< Direct Control of the BlitBlend Datapath multiplexers, do not change, offset: 0x3C30 */
68077 __I uint32_t BLITBLEND9_PRIMCONTROLWORD; /**< Value of last received primary control word, offset: 0x3C34 */
68078 __I uint32_t BLITBLEND9_SECCONTROLWORD; /**< Value of last received secondary control word, offset: 0x3C38 */
68079 uint8_t RESERVED_51[964];
68080 __I uint32_t STORE9_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x4000 */
68081 __I uint32_t STORE9_LOCKSTATUS; /**< Protection status of this address block., offset: 0x4004 */
68082 __IO uint32_t STORE9_STATICCONTROL; /**< Store unit static control register., offset: 0x4008 */
68083 __IO uint32_t STORE9_BURSTBUFFERMANAGEMENT; /**< Burst Buffer setup register., offset: 0x400C */
68084 __IO uint32_t STORE9_RINGBUFSTARTADDR; /**< Ring buffer setup for destination., offset: 0x4010 */
68085 __IO uint32_t STORE9_RINGBUFWRAPADDR; /**< Ring buffer setup for destination., offset: 0x4014 */
68086 __IO uint32_t STORE9_BASEADDRESS; /**< Destination buffer base address., offset: 0x4018 */
68087 __IO uint32_t STORE9_DESTINATIONBUFFERATTRIBUTES; /**< Destination buffer attributes., offset: 0x401C */
68088 __IO uint32_t STORE9_DESTINATIONBUFFERDIMENSION; /**< Destination buffer dimension., offset: 0x4020 */
68089 __IO uint32_t STORE9_FRAMEOFFSET; /**< Offset between destination frame and buffer., offset: 0x4024 */
68090 __IO uint32_t STORE9_COLORCOMPONENTBITS; /**< Color component size of destination buffer, offset: 0x4028 */
68091 __IO uint32_t STORE9_COLORCOMPONENTSHIFT; /**< Color component offset of destination buffer., offset: 0x402C */
68092 __IO uint32_t STORE9_CONTROL; /**< Store unit dynamic control register, offset: 0x4030 */
68093 __IO uint32_t STORE9_ENCODECONTROL; /**< Control options for RLAD compression., offset: 0x4034 */
68094 __IO uint32_t STORE9_DESTINATIONBUFFERLENGTH; /**< Destination buffer length for compressed data., offset: 0x4038 */
68095 __O uint32_t STORE9_START; /**< Store unit start register, offset: 0x403C */
68096 __IO uint32_t STORE9_ENCODERSTATUS; /**< Status information of the RLAD encoder., offset: 0x4040 */
68097 __I uint32_t STORE9_WRITEADDRESS; /**< Ring buffer synchronization., offset: 0x4044 */
68098 __I uint32_t STORE9_FRAMEPROPERTIES; /**< Ring buffer synchronization., offset: 0x4048 */
68099 __I uint32_t STORE9_BURSTBUFFERPROPERTIES; /**< Burst Buffer Property register, offset: 0x404C */
68100 __I uint32_t STORE9_LASTCONTROLWORD; /**< Shows the last control word received, offset: 0x4050 */
68101 __I uint32_t STORE9_PERFCOUNTER; /**< Performance counter result, offset: 0x4054 */
68102 __IO uint32_t STORE9_STATUS; /**< Shows status information, offset: 0x4058 */
68103 uint8_t RESERVED_52[932];
68104 __I uint32_t CONSTFRAME0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x4400 */
68105 __I uint32_t CONSTFRAME0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x4404 */
68106 __IO uint32_t CONSTFRAME0_STATICCONTROL; /**< ConstFrame unit static control register, offset: 0x4408 */
68107 __IO uint32_t CONSTFRAME0_FRAMEDIMENSIONS; /**< Output frame dimensions., offset: 0x440C */
68108 __IO uint32_t CONSTFRAME0_CONSTANTCOLOR; /**< Color of output frame., offset: 0x4410 */
68109 __O uint32_t CONSTFRAME0_CONTROLTRIGGER; /**< ConstFrame unit trigger register, offset: 0x4414 */
68110 __O uint32_t CONSTFRAME0_START; /**< ConstFrame unit start register, offset: 0x4418 */
68111 __I uint32_t CONSTFRAME0_STATUS; /**< Shows status information, offset: 0x441C */
68112 uint8_t RESERVED_53[992];
68113 __I uint32_t EXTDST0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x4800 */
68114 __I uint32_t EXTDST0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x4804 */
68115 __IO uint32_t EXTDST0_STATICCONTROL; /**< External Destination static control register, offset: 0x4808 */
68116 __IO uint32_t EXTDST0_CONTROL; /**< External Destination shadowed control register, offset: 0x480C */
68117 __O uint32_t EXTDST0_SOFTWAREKICK; /**< External Destination software kick, offset: 0x4810 */
68118 __IO uint32_t EXTDST0_STATUS; /**< External Destination Unit current status, offset: 0x4814 */
68119 __I uint32_t EXTDST0_CONTROLWORD; /**< Value of last received control word, offset: 0x4818 */
68120 __I uint32_t EXTDST0_CURPIXELCNT; /**< pixel count of currently running frame, offset: 0x481C */
68121 __I uint32_t EXTDST0_LASTPIXELCNT; /**< pixel count between last two control words, offset: 0x4820 */
68122 __I uint32_t EXTDST0_PERFCOUNTER; /**< Performance counter result, offset: 0x4824 */
68123 uint8_t RESERVED_54[984];
68124 __I uint32_t CONSTFRAME4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x4C00 */
68125 __I uint32_t CONSTFRAME4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x4C04 */
68126 __IO uint32_t CONSTFRAME4_STATICCONTROL; /**< ConstFrame unit static control register, offset: 0x4C08 */
68127 __IO uint32_t CONSTFRAME4_FRAMEDIMENSIONS; /**< Output frame dimensions., offset: 0x4C0C */
68128 __IO uint32_t CONSTFRAME4_CONSTANTCOLOR; /**< Color of output frame., offset: 0x4C10 */
68129 __O uint32_t CONSTFRAME4_CONTROLTRIGGER; /**< ConstFrame unit trigger register, offset: 0x4C14 */
68130 __O uint32_t CONSTFRAME4_START; /**< ConstFrame unit start register, offset: 0x4C18 */
68131 __I uint32_t CONSTFRAME4_STATUS; /**< Shows status information, offset: 0x4C1C */
68132 uint8_t RESERVED_55[992];
68133 __I uint32_t EXTDST4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x5000 */
68134 __I uint32_t EXTDST4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x5004 */
68135 __IO uint32_t EXTDST4_STATICCONTROL; /**< External Destination static control register, offset: 0x5008 */
68136 __IO uint32_t EXTDST4_CONTROL; /**< External Destination shadowed control register, offset: 0x500C */
68137 __O uint32_t EXTDST4_SOFTWAREKICK; /**< External Destination software kick, offset: 0x5010 */
68138 __IO uint32_t EXTDST4_STATUS; /**< External Destination Unit current status, offset: 0x5014 */
68139 __I uint32_t EXTDST4_CONTROLWORD; /**< Value of last received control word, offset: 0x5018 */
68140 __I uint32_t EXTDST4_CURPIXELCNT; /**< pixel count of currently running frame, offset: 0x501C */
68141 __I uint32_t EXTDST4_LASTPIXELCNT; /**< pixel count between last two control words, offset: 0x5020 */
68142 __I uint32_t EXTDST4_PERFCOUNTER; /**< Performance counter result, offset: 0x5024 */
68143 uint8_t RESERVED_56[984];
68144 __I uint32_t CONSTFRAME1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x5400 */
68145 __I uint32_t CONSTFRAME1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x5404 */
68146 __IO uint32_t CONSTFRAME1_STATICCONTROL; /**< ConstFrame unit static control register, offset: 0x5408 */
68147 __IO uint32_t CONSTFRAME1_FRAMEDIMENSIONS; /**< Output frame dimensions., offset: 0x540C */
68148 __IO uint32_t CONSTFRAME1_CONSTANTCOLOR; /**< Color of output frame., offset: 0x5410 */
68149 __O uint32_t CONSTFRAME1_CONTROLTRIGGER; /**< ConstFrame unit trigger register, offset: 0x5414 */
68150 __O uint32_t CONSTFRAME1_START; /**< ConstFrame unit start register, offset: 0x5418 */
68151 __I uint32_t CONSTFRAME1_STATUS; /**< Shows status information, offset: 0x541C */
68152 uint8_t RESERVED_57[992];
68153 __I uint32_t EXTDST1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x5800 */
68154 __I uint32_t EXTDST1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x5804 */
68155 __IO uint32_t EXTDST1_STATICCONTROL; /**< External Destination static control register, offset: 0x5808 */
68156 __IO uint32_t EXTDST1_CONTROL; /**< External Destination shadowed control register, offset: 0x580C */
68157 __O uint32_t EXTDST1_SOFTWAREKICK; /**< External Destination software kick, offset: 0x5810 */
68158 __IO uint32_t EXTDST1_STATUS; /**< External Destination Unit current status, offset: 0x5814 */
68159 __I uint32_t EXTDST1_CONTROLWORD; /**< Value of last received control word, offset: 0x5818 */
68160 __I uint32_t EXTDST1_CURPIXELCNT; /**< pixel count of currently running frame, offset: 0x581C */
68161 __I uint32_t EXTDST1_LASTPIXELCNT; /**< pixel count between last two control words, offset: 0x5820 */
68162 __I uint32_t EXTDST1_PERFCOUNTER; /**< Performance counter result, offset: 0x5824 */
68163 uint8_t RESERVED_58[984];
68164 __I uint32_t CONSTFRAME5_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x5C00 */
68165 __I uint32_t CONSTFRAME5_LOCKSTATUS; /**< Protection status of this address block., offset: 0x5C04 */
68166 __IO uint32_t CONSTFRAME5_STATICCONTROL; /**< ConstFrame unit static control register, offset: 0x5C08 */
68167 __IO uint32_t CONSTFRAME5_FRAMEDIMENSIONS; /**< Output frame dimensions., offset: 0x5C0C */
68168 __IO uint32_t CONSTFRAME5_CONSTANTCOLOR; /**< Color of output frame., offset: 0x5C10 */
68169 __O uint32_t CONSTFRAME5_CONTROLTRIGGER; /**< ConstFrame unit trigger register, offset: 0x5C14 */
68170 __O uint32_t CONSTFRAME5_START; /**< ConstFrame unit start register, offset: 0x5C18 */
68171 __I uint32_t CONSTFRAME5_STATUS; /**< Shows status information, offset: 0x5C1C */
68172 uint8_t RESERVED_59[992];
68173 __I uint32_t EXTDST5_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x6000 */
68174 __I uint32_t EXTDST5_LOCKSTATUS; /**< Protection status of this address block., offset: 0x6004 */
68175 __IO uint32_t EXTDST5_STATICCONTROL; /**< External Destination static control register, offset: 0x6008 */
68176 __IO uint32_t EXTDST5_CONTROL; /**< External Destination shadowed control register, offset: 0x600C */
68177 __O uint32_t EXTDST5_SOFTWAREKICK; /**< External Destination software kick, offset: 0x6010 */
68178 __IO uint32_t EXTDST5_STATUS; /**< External Destination Unit current status, offset: 0x6014 */
68179 __I uint32_t EXTDST5_CONTROLWORD; /**< Value of last received control word, offset: 0x6018 */
68180 __I uint32_t EXTDST5_CURPIXELCNT; /**< pixel count of currently running frame, offset: 0x601C */
68181 __I uint32_t EXTDST5_LASTPIXELCNT; /**< pixel count between last two control words, offset: 0x6020 */
68182 __I uint32_t EXTDST5_PERFCOUNTER; /**< Performance counter result, offset: 0x6024 */
68183 uint8_t RESERVED_60[984];
68184 __I uint32_t FETCHWARP2_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x6400 */
68185 __I uint32_t FETCHWARP2_LOCKSTATUS; /**< Protection status of this address block., offset: 0x6404 */
68186 __IO uint32_t FETCHWARP2_STATICCONTROL; /**< Common static control options., offset: 0x6408 */
68187 __IO uint32_t FETCHWARP2_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x640C */
68188 __IO uint32_t FETCHWARP2_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x6410 */
68189 __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x6414 */
68190 __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x6418 */
68191 __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x641C */
68192 __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x6420 */
68193 __IO uint32_t FETCHWARP2_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x6424 */
68194 __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x6428 */
68195 __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x642C */
68196 __IO uint32_t FETCHWARP2_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x6430 */
68197 __IO uint32_t FETCHWARP2_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x6434 */
68198 __IO uint32_t FETCHWARP2_BASEADDRESS1; /**< Source buffer base address of layer 1., offset: 0x6438 */
68199 __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES1; /**< Source buffer attributes for layer 1., offset: 0x643C */
68200 __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION1; /**< Source buffer dimensions of layer 1,, offset: 0x6440 */
68201 __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS1; /**< Size of color components for RGB, YUV and index formats (layer 1)., offset: 0x6444 */
68202 __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT1; /**< Bit position of color components for RGB, YUV and index formats (layer 1)., offset: 0x6448 */
68203 __IO uint32_t FETCHWARP2_LAYEROFFSET1; /**< Position of layer 1 within the destination frame., offset: 0x644C */
68204 __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET1; /**< Clip window position for layer 1., offset: 0x6450 */
68205 __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS1; /**< Clip window size for layer 1., offset: 0x6454 */
68206 __IO uint32_t FETCHWARP2_CONSTANTCOLOR1; /**< Constant color for layer 1., offset: 0x6458 */
68207 __IO uint32_t FETCHWARP2_LAYERPROPERTY1; /**< Common properties of layer 1., offset: 0x645C */
68208 __IO uint32_t FETCHWARP2_BASEADDRESS2; /**< Source buffer base address of layer 2., offset: 0x6460 */
68209 __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES2; /**< Source buffer attributes for layer 2., offset: 0x6464 */
68210 __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION2; /**< Source buffer dimension of layer 2., offset: 0x6468 */
68211 __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS2; /**< Size of color components for RGB, YUV and index formats (layer 2)., offset: 0x646C */
68212 __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT2; /**< Bit position of color components for RGB, YUV and index formats (layer 2)., offset: 0x6470 */
68213 __IO uint32_t FETCHWARP2_LAYEROFFSET2; /**< Position of layer 2 within the destination frame., offset: 0x6474 */
68214 __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET2; /**< Clip window position for layer 2., offset: 0x6478 */
68215 __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS2; /**< Clip window size for layer 2., offset: 0x647C */
68216 __IO uint32_t FETCHWARP2_CONSTANTCOLOR2; /**< Constant color for layer 2., offset: 0x6480 */
68217 __IO uint32_t FETCHWARP2_LAYERPROPERTY2; /**< Common properties of layer 2., offset: 0x6484 */
68218 __IO uint32_t FETCHWARP2_BASEADDRESS3; /**< Source buffer base address of layer 3., offset: 0x6488 */
68219 __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES3; /**< Source buffer attributes for layer 3., offset: 0x648C */
68220 __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION3; /**< Source buffer dimension of layer 3., offset: 0x6490 */
68221 __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS3; /**< Size of color components for RGB, YUV and index formats (layer 3)., offset: 0x6494 */
68222 __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT3; /**< Bit position of color components for RGB, YUV and index formats (layer 3)., offset: 0x6498 */
68223 __IO uint32_t FETCHWARP2_LAYEROFFSET3; /**< Position of layer 3 within the destination frame., offset: 0x649C */
68224 __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET3; /**< Clip window position for layer 3., offset: 0x64A0 */
68225 __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS3; /**< Clip window size for layer 3., offset: 0x64A4 */
68226 __IO uint32_t FETCHWARP2_CONSTANTCOLOR3; /**< Constant color for layer 3., offset: 0x64A8 */
68227 __IO uint32_t FETCHWARP2_LAYERPROPERTY3; /**< Common properties of layer 3., offset: 0x64AC */
68228 __IO uint32_t FETCHWARP2_BASEADDRESS4; /**< Source buffer base address of layer 4., offset: 0x64B0 */
68229 __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES4; /**< Source buffer attributes for layer 4., offset: 0x64B4 */
68230 __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION4; /**< Source buffer dimension of layer 4., offset: 0x64B8 */
68231 __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS4; /**< Size of color components for RGB, YUV and index formats (layer 4)., offset: 0x64BC */
68232 __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT4; /**< Bit position of color components for RGB, YUV and index formats (layer 4)., offset: 0x64C0 */
68233 __IO uint32_t FETCHWARP2_LAYEROFFSET4; /**< Position of layer 4 within the destination frame., offset: 0x64C4 */
68234 __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET4; /**< Clip window position for layer 4., offset: 0x64C8 */
68235 __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS4; /**< Clip window size for layer 4., offset: 0x64CC */
68236 __IO uint32_t FETCHWARP2_CONSTANTCOLOR4; /**< Constant color for layer 4., offset: 0x64D0 */
68237 __IO uint32_t FETCHWARP2_LAYERPROPERTY4; /**< Common properties of layer 4., offset: 0x64D4 */
68238 __IO uint32_t FETCHWARP2_BASEADDRESS5; /**< Source buffer base address of layer 5., offset: 0x64D8 */
68239 __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES5; /**< Source buffer attributes for layer 5., offset: 0x64DC */
68240 __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION5; /**< Source buffer dimension of layer 5., offset: 0x64E0 */
68241 __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS5; /**< Size of color components for RGB, YUV and index formats (layer 5)., offset: 0x64E4 */
68242 __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT5; /**< Bit position of color components for RGB, YUV and index formats (layer 5)., offset: 0x64E8 */
68243 __IO uint32_t FETCHWARP2_LAYEROFFSET5; /**< Position of layer 5 within the destination frame., offset: 0x64EC */
68244 __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET5; /**< Clip window position for layer 5., offset: 0x64F0 */
68245 __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS5; /**< Clip window size for layer 5., offset: 0x64F4 */
68246 __IO uint32_t FETCHWARP2_CONSTANTCOLOR5; /**< Constant color for layer 5., offset: 0x64F8 */
68247 __IO uint32_t FETCHWARP2_LAYERPROPERTY5; /**< Common properties of layer 5., offset: 0x64FC */
68248 __IO uint32_t FETCHWARP2_BASEADDRESS6; /**< Source buffer base address of layer 6., offset: 0x6500 */
68249 __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES6; /**< Source buffer attributes for layer 6., offset: 0x6504 */
68250 __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION6; /**< Source buffer dimension of layer 6., offset: 0x6508 */
68251 __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS6; /**< Size of color components for RGB, YUV and index formats (layer 6)., offset: 0x650C */
68252 __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT6; /**< Bit position of color components for RGB, YUV and index formats (layer 6)., offset: 0x6510 */
68253 __IO uint32_t FETCHWARP2_LAYEROFFSET6; /**< Position of layer 1 within the destination frame., offset: 0x6514 */
68254 __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET6; /**< Clip window position for layer 6., offset: 0x6518 */
68255 __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS6; /**< Clip window size for layer 6., offset: 0x651C */
68256 __IO uint32_t FETCHWARP2_CONSTANTCOLOR6; /**< Constant color for layer 6., offset: 0x6520 */
68257 __IO uint32_t FETCHWARP2_LAYERPROPERTY6; /**< Common properties of layer 6., offset: 0x6524 */
68258 __IO uint32_t FETCHWARP2_BASEADDRESS7; /**< Source buffer base address of layer 7., offset: 0x6528 */
68259 __IO uint32_t FETCHWARP2_SOURCEBUFFERATTRIBUTES7; /**< Source buffer stride for layer 7., offset: 0x652C */
68260 __IO uint32_t FETCHWARP2_SOURCEBUFFERDIMENSION7; /**< Source buffer dimension of layer 7., offset: 0x6530 */
68261 __IO uint32_t FETCHWARP2_COLORCOMPONENTBITS7; /**< Size of color components for RGB, YUV and index formats (layer 7)., offset: 0x6534 */
68262 __IO uint32_t FETCHWARP2_COLORCOMPONENTSHIFT7; /**< Bit position of color components for RGB, YUV and index formats (layer 7)., offset: 0x6538 */
68263 __IO uint32_t FETCHWARP2_LAYEROFFSET7; /**< Position of layer 7 within the destination frame., offset: 0x653C */
68264 __IO uint32_t FETCHWARP2_CLIPWINDOWOFFSET7; /**< Clip window position for layer 7., offset: 0x6540 */
68265 __IO uint32_t FETCHWARP2_CLIPWINDOWDIMENSIONS7; /**< Clip window size for layer 7., offset: 0x6544 */
68266 __IO uint32_t FETCHWARP2_CONSTANTCOLOR7; /**< Constant color for layer 7., offset: 0x6548 */
68267 __IO uint32_t FETCHWARP2_LAYERPROPERTY7; /**< Common properties of layer 7., offset: 0x654C */
68268 __IO uint32_t FETCHWARP2_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x6550 */
68269 __IO uint32_t FETCHWARP2_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x6554 */
68270 __IO uint32_t FETCHWARP2_WARPCONTROL; /**< Warping control options., offset: 0x6558 */
68271 __IO uint32_t FETCHWARP2_ARBSTARTX; /**< Start value X for arbitrary warping., offset: 0x655C */
68272 __IO uint32_t FETCHWARP2_ARBSTARTY; /**< Start value Y for arbitrary warping., offset: 0x6560 */
68273 __IO uint32_t FETCHWARP2_ARBDELTA; /**< Start values for delta incrementation of arbitrary warping., offset: 0x6564 */
68274 __IO uint32_t FETCHWARP2_FIRPOSITIONS; /**< FIR sequence control register., offset: 0x6568 */
68275 __IO uint32_t FETCHWARP2_FIRCOEFFICIENTS; /**< FIR coefficients register., offset: 0x656C */
68276 __IO uint32_t FETCHWARP2_CONTROL; /**< Shared common control settings for all layers., offset: 0x6570 */
68277 __I uint32_t FETCHWARP2_TRIGGERENABLE; /**< Shadow load enable flags for all layers., offset: 0x6574 */
68278 __O uint32_t FETCHWARP2_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x6578 */
68279 __O uint32_t FETCHWARP2_START; /**< Frame start trigger., offset: 0x657C */
68280 __I uint32_t FETCHWARP2_FETCHTYPE; /**< Fetch unit type., offset: 0x6580 */
68281 __I uint32_t FETCHWARP2_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x6584 */
68282 __IO uint32_t FETCHWARP2_STATUS; /**< Status informations., offset: 0x6588 */
68283 __I uint32_t FETCHWARP2_HIDDENSTATUS; /**< Hidden status informations., offset: 0x658C */
68284 uint8_t RESERVED_61[624];
68285 __I uint32_t FETCHECO2_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x6800 */
68286 __I uint32_t FETCHECO2_LOCKSTATUS; /**< Protection status of this address block., offset: 0x6804 */
68287 __IO uint32_t FETCHECO2_STATICCONTROL; /**< Common static control options., offset: 0x6808 */
68288 __IO uint32_t FETCHECO2_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x680C */
68289 __IO uint32_t FETCHECO2_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x6810 */
68290 __IO uint32_t FETCHECO2_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x6814 */
68291 __IO uint32_t FETCHECO2_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x6818 */
68292 __IO uint32_t FETCHECO2_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x681C */
68293 __IO uint32_t FETCHECO2_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x6820 */
68294 __IO uint32_t FETCHECO2_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x6824 */
68295 __IO uint32_t FETCHECO2_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x6828 */
68296 __IO uint32_t FETCHECO2_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x682C */
68297 __IO uint32_t FETCHECO2_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x6830 */
68298 __IO uint32_t FETCHECO2_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x6834 */
68299 __IO uint32_t FETCHECO2_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x6838 */
68300 __IO uint32_t FETCHECO2_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x683C */
68301 __IO uint32_t FETCHECO2_CONTROL; /**< Shared common control settings for all layers., offset: 0x6840 */
68302 __O uint32_t FETCHECO2_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x6844 */
68303 __O uint32_t FETCHECO2_START; /**< Frame start trigger., offset: 0x6848 */
68304 __I uint32_t FETCHECO2_FETCHTYPE; /**< Fetch unit type., offset: 0x684C */
68305 __I uint32_t FETCHECO2_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x6850 */
68306 __I uint32_t FETCHECO2_HIDDENSTATUS; /**< Hidden status informations., offset: 0x6854 */
68307 uint8_t RESERVED_62[936];
68308 __I uint32_t FETCHDECODE_LOCKUNLOCK_4; /**< Register to change the protection status of this address block., offset: 0x6C00 */
68309 __I uint32_t FETCHDECODE_LOCKSTATUS_4; /**< Protection status of this address block., offset: 0x6C04 */
68310 __IO uint32_t FETCHDECODE_STATICCONTRO_4L; /**< Common static control options., offset: 0x6C08 */
68311 __IO uint32_t FETCHDECODE_BURSTBUFFERMANAGEMENT_4; /**< AXI interface buffer management register, offset: 0x6C0C */
68312 __IO uint32_t FETCHDECODE_RINGBUFSTARTADDR0_4; /**< Ring buffer setup for layer 0., offset: 0x6C10 */
68313 __IO uint32_t FETCHDECODE_RINGBUFWRAPADDR0_4; /**< Ring buffer setup for layer 0., offset: 0x6C14 */
68314 __IO uint32_t FETCHDECODE_FRAMEPROPERTIES0_4; /**< Frame property setup for layer 0., offset: 0x6C18 */
68315 __IO uint32_t FETCHDECODE_BASEADDRESS0_4; /**< Source buffer base address of layer 0., offset: 0x6C1C */
68316 __IO uint32_t FETCHDECODE_SOURCEBUFFERATTRIBUTES0_4; /**< Source buffer attributes for layer 0., offset: 0x6C20 */
68317 __IO uint32_t FETCHDECODE_SOURCEBUFFERDIMENSION0_4; /**< Source buffer dimension of layer 0., offset: 0x6C24 */
68318 __IO uint32_t FETCHDECODE_COLORCOMPONENTBITS0_4; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x6C28 */
68319 __IO uint32_t FETCHDECODE_COLORCOMPONENTSHIFT0_4; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x6C2C */
68320 __IO uint32_t FETCHDECODE_LAYEROFFSET0_4; /**< Position of layer 0 within the destination frame., offset: 0x6C30 */
68321 __IO uint32_t FETCHDECODE_CLIPWINDOWOFFSET0_4; /**< Clip window position for layer 0., offset: 0x6C34 */
68322 __IO uint32_t FETCHDECODE_CLIPWINDOWDIMENSIONS0_4; /**< Clip window size for layer 0., offset: 0x6C38 */
68323 __IO uint32_t FETCHDECODE_CONSTANTCOLOR0_4; /**< Constant color for layer 0., offset: 0x6C3C */
68324 __IO uint32_t FETCHDECODE_LAYERPROPERTY0_4; /**< Common properties of layer 0., offset: 0x6C40 */
68325 __IO uint32_t FETCHDECODE_FRAMEDIMENSIONS_4; /**< Output frame dimension., offset: 0x6C44 */
68326 __IO uint32_t FETCHDECODE_FRAMERESAMPLING_4; /**< Resampling options for output frame., offset: 0x6C48 */
68327 __IO uint32_t FETCHDECODE_DECODECONTROL_4; /**< Control options for RLAD decompression., offset: 0x6C4C */
68328 __IO uint32_t FETCHDECODE_SOURCEBUFFERLENGTH_4; /**< Source buffer length for compressed data., offset: 0x6C50 */
68329 __IO uint32_t FETCHDECODE_CONTROL_4; /**< Shared common control settings for all layers., offset: 0x6C54 */
68330 __O uint32_t FETCHDECODE_CONTROLTRIGGER_4; /**< Shadow load trigger., offset: 0x6C58 */
68331 __O uint32_t FETCHDECODE_START_4; /**< Frame start trigger., offset: 0x6C5C */
68332 __I uint32_t FETCHDECODE_FETCHTYPE_4; /**< Fetch unit type., offset: 0x6C60 */
68333 __IO uint32_t FETCHDECODE_DECODERSTATUS_4; /**< Status information of the RLAD decoder., offset: 0x6C64 */
68334 __I uint32_t FETCHDECODE_READADDRESS0_4; /**< Ring buffer synchronization for layer 0., offset: 0x6C68 */
68335 __I uint32_t FETCHDECODE_BURSTBUFFERPROPERTIES_4; /**< Burst buffer properties., offset: 0x6C6C */
68336 __IO uint32_t FETCHDECODE_STATUS_4; /**< Status informations., offset: 0x6C70 */
68337 __I uint32_t FETCHDECODE_HIDDENSTATUS_4; /**< Hidden status informations., offset: 0x6C74 */
68338 uint8_t RESERVED_63[904];
68339 __IO uint32_t COLORPALETTE_4; /**< Color palette look up table., offset: 0x7000 */
68340 uint8_t RESERVED_64[1020];
68341 __I uint32_t FETCHECO0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x7400 */
68342 __I uint32_t FETCHECO0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x7404 */
68343 __IO uint32_t FETCHECO0_STATICCONTROL; /**< Common static control options., offset: 0x7408 */
68344 __IO uint32_t FETCHECO0_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x740C */
68345 __IO uint32_t FETCHECO0_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x7410 */
68346 __IO uint32_t FETCHECO0_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x7414 */
68347 __IO uint32_t FETCHECO0_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x7418 */
68348 __IO uint32_t FETCHECO0_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x741C */
68349 __IO uint32_t FETCHECO0_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x7420 */
68350 __IO uint32_t FETCHECO0_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x7424 */
68351 __IO uint32_t FETCHECO0_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x7428 */
68352 __IO uint32_t FETCHECO0_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x742C */
68353 __IO uint32_t FETCHECO0_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x7430 */
68354 __IO uint32_t FETCHECO0_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x7434 */
68355 __IO uint32_t FETCHECO0_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x7438 */
68356 __IO uint32_t FETCHECO0_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x743C */
68357 __IO uint32_t FETCHECO0_CONTROL; /**< Shared common control settings for all layers., offset: 0x7440 */
68358 __O uint32_t FETCHECO0_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x7444 */
68359 __O uint32_t FETCHECO0_START; /**< Frame start trigger., offset: 0x7448 */
68360 __I uint32_t FETCHECO0_FETCHTYPE; /**< Fetch unit type., offset: 0x744C */
68361 __I uint32_t FETCHECO0_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x7450 */
68362 __I uint32_t FETCHECO0_HIDDENSTATUS; /**< Hidden status informations., offset: 0x7454 */
68363 uint8_t RESERVED_65[936];
68364 __I uint32_t FETCHDECODE_LOCKUNLOCK_7; /**< Register to change the protection status of this address block., offset: 0x7800 */
68365 __I uint32_t FETCHDECODE_LOCKSTATUS_7; /**< Protection status of this address block., offset: 0x7804 */
68366 __IO uint32_t FETCHDECODE_STATICCONTRO_7L; /**< Common static control options., offset: 0x7808 */
68367 __IO uint32_t FETCHDECODE_BURSTBUFFERMANAGEMENT_7; /**< AXI interface buffer management register, offset: 0x780C */
68368 __IO uint32_t FETCHDECODE_RINGBUFSTARTADDR0_7; /**< Ring buffer setup for layer 0., offset: 0x7810 */
68369 __IO uint32_t FETCHDECODE_RINGBUFWRAPADDR0_7; /**< Ring buffer setup for layer 0., offset: 0x7814 */
68370 __IO uint32_t FETCHDECODE_FRAMEPROPERTIES0_7; /**< Frame property setup for layer 0., offset: 0x7818 */
68371 __IO uint32_t FETCHDECODE_BASEADDRESS0_7; /**< Source buffer base address of layer 0., offset: 0x781C */
68372 __IO uint32_t FETCHDECODE_SOURCEBUFFERATTRIBUTES0_7; /**< Source buffer attributes for layer 0., offset: 0x7820 */
68373 __IO uint32_t FETCHDECODE_SOURCEBUFFERDIMENSION0_7; /**< Source buffer dimension of layer 0., offset: 0x7824 */
68374 __IO uint32_t FETCHDECODE_COLORCOMPONENTBITS0_7; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x7828 */
68375 __IO uint32_t FETCHDECODE_COLORCOMPONENTSHIFT0_7; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x782C */
68376 __IO uint32_t FETCHDECODE_LAYEROFFSET0_7; /**< Position of layer 0 within the destination frame., offset: 0x7830 */
68377 __IO uint32_t FETCHDECODE_CLIPWINDOWOFFSET0_7; /**< Clip window position for layer 0., offset: 0x7834 */
68378 __IO uint32_t FETCHDECODE_CLIPWINDOWDIMENSIONS0_7; /**< Clip window size for layer 0., offset: 0x7838 */
68379 __IO uint32_t FETCHDECODE_CONSTANTCOLOR0_7; /**< Constant color for layer 0., offset: 0x783C */
68380 __IO uint32_t FETCHDECODE_LAYERPROPERTY0_7; /**< Common properties of layer 0., offset: 0x7840 */
68381 __IO uint32_t FETCHDECODE_FRAMEDIMENSIONS_7; /**< Output frame dimension., offset: 0x7844 */
68382 __IO uint32_t FETCHDECODE_FRAMERESAMPLING_7; /**< Resampling options for output frame., offset: 0x7848 */
68383 __IO uint32_t FETCHDECODE_DECODECONTROL_7; /**< Control options for RLAD decompression., offset: 0x784C */
68384 __IO uint32_t FETCHDECODE_SOURCEBUFFERLENGTH_7; /**< Source buffer length for compressed data., offset: 0x7850 */
68385 __IO uint32_t FETCHDECODE_CONTROL_7; /**< Shared common control settings for all layers., offset: 0x7854 */
68386 __O uint32_t FETCHDECODE_CONTROLTRIGGER_7; /**< Shadow load trigger., offset: 0x7858 */
68387 __O uint32_t FETCHDECODE_START_7; /**< Frame start trigger., offset: 0x785C */
68388 __I uint32_t FETCHDECODE_FETCHTYPE_7; /**< Fetch unit type., offset: 0x7860 */
68389 __IO uint32_t FETCHDECODE_DECODERSTATUS_7; /**< Status information of the RLAD decoder., offset: 0x7864 */
68390 __I uint32_t FETCHDECODE_READADDRESS0_7; /**< Ring buffer synchronization for layer 0., offset: 0x7868 */
68391 __I uint32_t FETCHDECODE_BURSTBUFFERPROPERTIES_7; /**< Burst buffer properties., offset: 0x786C */
68392 __IO uint32_t FETCHDECODE_STATUS_7; /**< Status informations., offset: 0x7870 */
68393 __I uint32_t FETCHDECODE_HIDDENSTATUS_7; /**< Hidden status informations., offset: 0x7874 */
68394 uint8_t RESERVED_66[904];
68395 __IO uint32_t COLORPALETTE_7; /**< Color palette look up table., offset: 0x7C00 */
68396 uint8_t RESERVED_67[1020];
68397 __I uint32_t FETCHECO1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x8000 */
68398 __I uint32_t FETCHECO1_LOCKSTATUS; /**< Protection status of this address block., offset: 0x8004 */
68399 __IO uint32_t FETCHECO1_STATICCONTROL; /**< Common static control options., offset: 0x8008 */
68400 __IO uint32_t FETCHECO1_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x800C */
68401 __IO uint32_t FETCHECO1_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x8010 */
68402 __IO uint32_t FETCHECO1_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x8014 */
68403 __IO uint32_t FETCHECO1_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x8018 */
68404 __IO uint32_t FETCHECO1_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x801C */
68405 __IO uint32_t FETCHECO1_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x8020 */
68406 __IO uint32_t FETCHECO1_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x8024 */
68407 __IO uint32_t FETCHECO1_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x8028 */
68408 __IO uint32_t FETCHECO1_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x802C */
68409 __IO uint32_t FETCHECO1_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x8030 */
68410 __IO uint32_t FETCHECO1_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x8034 */
68411 __IO uint32_t FETCHECO1_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x8038 */
68412 __IO uint32_t FETCHECO1_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x803C */
68413 __IO uint32_t FETCHECO1_CONTROL; /**< Shared common control settings for all layers., offset: 0x8040 */
68414 __O uint32_t FETCHECO1_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x8044 */
68415 __O uint32_t FETCHECO1_START; /**< Frame start trigger., offset: 0x8048 */
68416 __I uint32_t FETCHECO1_FETCHTYPE; /**< Fetch unit type., offset: 0x804C */
68417 __I uint32_t FETCHECO1_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x8050 */
68418 __I uint32_t FETCHECO1_HIDDENSTATUS; /**< Hidden status informations., offset: 0x8054 */
68419 uint8_t RESERVED_68[936];
68420 __I uint32_t FETCHLAYER0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x8400 */
68421 __I uint32_t FETCHLAYER0_LOCKSTATUS; /**< Protection status of this address block., offset: 0x8404 */
68422 __IO uint32_t FETCHLAYER0_STATICCONTROL; /**< Common static control options., offset: 0x8408 */
68423 __IO uint32_t FETCHLAYER0_BURSTBUFFERMANAGEMENT; /**< AXI interface buffer management register, offset: 0x840C */
68424 __IO uint32_t FETCHLAYER0_BASEADDRESS0; /**< Source buffer base address of layer 0., offset: 0x8410 */
68425 __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES0; /**< Source buffer attributes for layer 0., offset: 0x8414 */
68426 __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION0; /**< Source buffer dimension of layer 0., offset: 0x8418 */
68427 __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS0; /**< Size of color components for RGB, YUV and index formats (layer 0)., offset: 0x841C */
68428 __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT0; /**< Bit position of color components for RGB, YUV and index formats (layer 0)., offset: 0x8420 */
68429 __IO uint32_t FETCHLAYER0_LAYEROFFSET0; /**< Position of layer 0 within the destination frame., offset: 0x8424 */
68430 __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET0; /**< Clip window position for layer 0., offset: 0x8428 */
68431 __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS0; /**< Clip window size for layer 0., offset: 0x842C */
68432 __IO uint32_t FETCHLAYER0_CONSTANTCOLOR0; /**< Constant color for layer 0., offset: 0x8430 */
68433 __IO uint32_t FETCHLAYER0_LAYERPROPERTY0; /**< Common properties of layer 0., offset: 0x8434 */
68434 __IO uint32_t FETCHLAYER0_BASEADDRESS1; /**< Source buffer base address of layer 1., offset: 0x8438 */
68435 __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES1; /**< Source buffer attributes for layer 1., offset: 0x843C */
68436 __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION1; /**< Source buffer dimensions of layer 1,, offset: 0x8440 */
68437 __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS1; /**< Size of color components for RGB, YUV and index formats (layer 1)., offset: 0x8444 */
68438 __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT1; /**< Bit position of color components for RGB, YUV and index formats (layer 1)., offset: 0x8448 */
68439 __IO uint32_t FETCHLAYER0_LAYEROFFSET1; /**< Position of layer 1 within the destination frame., offset: 0x844C */
68440 __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET1; /**< Clip window position for layer 1., offset: 0x8450 */
68441 __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS1; /**< Clip window size for layer 1., offset: 0x8454 */
68442 __IO uint32_t FETCHLAYER0_CONSTANTCOLOR1; /**< Constant color for layer 1., offset: 0x8458 */
68443 __IO uint32_t FETCHLAYER0_LAYERPROPERTY1; /**< Common properties of layer 1., offset: 0x845C */
68444 __IO uint32_t FETCHLAYER0_BASEADDRESS2; /**< Source buffer base address of layer 2., offset: 0x8460 */
68445 __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES2; /**< Source buffer attributes for layer 2., offset: 0x8464 */
68446 __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION2; /**< Source buffer dimension of layer 2., offset: 0x8468 */
68447 __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS2; /**< Size of color components for RGB, YUV and index formats (layer 2)., offset: 0x846C */
68448 __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT2; /**< Bit position of color components for RGB, YUV and index formats (layer 2)., offset: 0x8470 */
68449 __IO uint32_t FETCHLAYER0_LAYEROFFSET2; /**< Position of layer 2 within the destination frame., offset: 0x8474 */
68450 __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET2; /**< Clip window position for layer 2., offset: 0x8478 */
68451 __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS2; /**< Clip window size for layer 2., offset: 0x847C */
68452 __IO uint32_t FETCHLAYER0_CONSTANTCOLOR2; /**< Constant color for layer 2., offset: 0x8480 */
68453 __IO uint32_t FETCHLAYER0_LAYERPROPERTY2; /**< Common properties of layer 2., offset: 0x8484 */
68454 __IO uint32_t FETCHLAYER0_BASEADDRESS3; /**< Source buffer base address of layer 3., offset: 0x8488 */
68455 __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES3; /**< Source buffer attributes for layer 3., offset: 0x848C */
68456 __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION3; /**< Source buffer dimension of layer 3., offset: 0x8490 */
68457 __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS3; /**< Size of color components for RGB, YUV and index formats (layer 3)., offset: 0x8494 */
68458 __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT3; /**< Bit position of color components for RGB, YUV and index formats (layer 3)., offset: 0x8498 */
68459 __IO uint32_t FETCHLAYER0_LAYEROFFSET3; /**< Position of layer 3 within the destination frame., offset: 0x849C */
68460 __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET3; /**< Clip window position for layer 3., offset: 0x84A0 */
68461 __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS3; /**< Clip window size for layer 3., offset: 0x84A4 */
68462 __IO uint32_t FETCHLAYER0_CONSTANTCOLOR3; /**< Constant color for layer 3., offset: 0x84A8 */
68463 __IO uint32_t FETCHLAYER0_LAYERPROPERTY3; /**< Common properties of layer 3., offset: 0x84AC */
68464 __IO uint32_t FETCHLAYER0_BASEADDRESS4; /**< Source buffer base address of layer 4., offset: 0x84B0 */
68465 __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES4; /**< Source buffer attributes for layer 4., offset: 0x84B4 */
68466 __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION4; /**< Source buffer dimension of layer 4., offset: 0x84B8 */
68467 __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS4; /**< Size of color components for RGB, YUV and index formats (layer 4)., offset: 0x84BC */
68468 __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT4; /**< Bit position of color components for RGB, YUV and index formats (layer 4)., offset: 0x84C0 */
68469 __IO uint32_t FETCHLAYER0_LAYEROFFSET4; /**< Position of layer 4 within the destination frame., offset: 0x84C4 */
68470 __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET4; /**< Clip window position for layer 4., offset: 0x84C8 */
68471 __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS4; /**< Clip window size for layer 4., offset: 0x84CC */
68472 __IO uint32_t FETCHLAYER0_CONSTANTCOLOR4; /**< Constant color for layer 4., offset: 0x84D0 */
68473 __IO uint32_t FETCHLAYER0_LAYERPROPERTY4; /**< Common properties of layer 4., offset: 0x84D4 */
68474 __IO uint32_t FETCHLAYER0_BASEADDRESS5; /**< Source buffer base address of layer 5., offset: 0x84D8 */
68475 __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES5; /**< Source buffer attributes for layer 5., offset: 0x84DC */
68476 __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION5; /**< Source buffer dimension of layer 5., offset: 0x84E0 */
68477 __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS5; /**< Size of color components for RGB, YUV and index formats (layer 5)., offset: 0x84E4 */
68478 __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT5; /**< Bit position of color components for RGB, YUV and index formats (layer 5)., offset: 0x84E8 */
68479 __IO uint32_t FETCHLAYER0_LAYEROFFSET5; /**< Position of layer 5 within the destination frame., offset: 0x84EC */
68480 __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET5; /**< Clip window position for layer 5., offset: 0x84F0 */
68481 __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS5; /**< Clip window size for layer 5., offset: 0x84F4 */
68482 __IO uint32_t FETCHLAYER0_CONSTANTCOLOR5; /**< Constant color for layer 5., offset: 0x84F8 */
68483 __IO uint32_t FETCHLAYER0_LAYERPROPERTY5; /**< Common properties of layer 5., offset: 0x84FC */
68484 __IO uint32_t FETCHLAYER0_BASEADDRESS6; /**< Source buffer base address of layer 6., offset: 0x8500 */
68485 __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES6; /**< Source buffer attributes for layer 6., offset: 0x8504 */
68486 __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION6; /**< Source buffer dimension of layer 6., offset: 0x8508 */
68487 __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS6; /**< Size of color components for RGB, YUV and index formats (layer 6)., offset: 0x850C */
68488 __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT6; /**< Bit position of color components for RGB, YUV and index formats (layer 6)., offset: 0x8510 */
68489 __IO uint32_t FETCHLAYER0_LAYEROFFSET6; /**< Position of layer 1 within the destination frame., offset: 0x8514 */
68490 __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET6; /**< Clip window position for layer 6., offset: 0x8518 */
68491 __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS6; /**< Clip window size for layer 6., offset: 0x851C */
68492 __IO uint32_t FETCHLAYER0_CONSTANTCOLOR6; /**< Constant color for layer 6., offset: 0x8520 */
68493 __IO uint32_t FETCHLAYER0_LAYERPROPERTY6; /**< Common properties of layer 6., offset: 0x8524 */
68494 __IO uint32_t FETCHLAYER0_BASEADDRESS7; /**< Source buffer base address of layer 7., offset: 0x8528 */
68495 __IO uint32_t FETCHLAYER0_SOURCEBUFFERATTRIBUTES7; /**< Source buffer stride for layer 7., offset: 0x852C */
68496 __IO uint32_t FETCHLAYER0_SOURCEBUFFERDIMENSION7; /**< Source buffer dimension of layer 7., offset: 0x8530 */
68497 __IO uint32_t FETCHLAYER0_COLORCOMPONENTBITS7; /**< Size of color components for RGB, YUV and index formats (layer 7)., offset: 0x8534 */
68498 __IO uint32_t FETCHLAYER0_COLORCOMPONENTSHIFT7; /**< Bit position of color components for RGB, YUV and index formats (layer 7)., offset: 0x8538 */
68499 __IO uint32_t FETCHLAYER0_LAYEROFFSET7; /**< Position of layer 7 within the destination frame., offset: 0x853C */
68500 __IO uint32_t FETCHLAYER0_CLIPWINDOWOFFSET7; /**< Clip window position for layer 7., offset: 0x8540 */
68501 __IO uint32_t FETCHLAYER0_CLIPWINDOWDIMENSIONS7; /**< Clip window size for layer 7., offset: 0x8544 */
68502 __IO uint32_t FETCHLAYER0_CONSTANTCOLOR7; /**< Constant color for layer 7., offset: 0x8548 */
68503 __IO uint32_t FETCHLAYER0_LAYERPROPERTY7; /**< Common properties of layer 7., offset: 0x854C */
68504 __IO uint32_t FETCHLAYER0_FRAMEDIMENSIONS; /**< Output frame dimension., offset: 0x8550 */
68505 __IO uint32_t FETCHLAYER0_FRAMERESAMPLING; /**< Resampling options for output frame., offset: 0x8554 */
68506 __IO uint32_t FETCHLAYER0_CONTROL; /**< Shared common control settings for all layers., offset: 0x8558 */
68507 __I uint32_t FETCHLAYER0_TRIGGERENABLE; /**< Shadow load enable flags for all layers., offset: 0x855C */
68508 __O uint32_t FETCHLAYER0_CONTROLTRIGGER; /**< Shadow load trigger., offset: 0x8560 */
68509 __O uint32_t FETCHLAYER0_START; /**< Frame start trigger., offset: 0x8564 */
68510 __I uint32_t FETCHLAYER0_FETCHTYPE; /**< Fetch unit type., offset: 0x8568 */
68511 __I uint32_t FETCHLAYER0_BURSTBUFFERPROPERTIES; /**< Burst buffer properties., offset: 0x856C */
68512 __IO uint32_t FETCHLAYER0_STATUS; /**< Status informations., offset: 0x8570 */
68513 __I uint32_t FETCHLAYER0_HIDDENSTATUS; /**< Hidden status informations., offset: 0x8574 */
68514 uint8_t RESERVED_69[648];
68515 __IO uint32_t FETCHLAYER0_COLORPALETTE; /**< Color palette look up table., offset: 0x8800 */
68516 uint8_t RESERVED_70[1020];
68517 __I uint32_t MATRIX4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x8C00 */
68518 __I uint32_t MATRIX4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x8C04 */
68519 __IO uint32_t MATRIX4_STATICCONTROL; /**< Color Matrix static control register, offset: 0x8C08 */
68520 __IO uint32_t MATRIX4_CONTROL; /**< Color Matrix control register, offset: 0x8C0C */
68521 __IO uint32_t MATRIX4_RED0; /**< Matrix values for calculation of the red output value., offset: 0x8C10 */
68522 __IO uint32_t MATRIX4_RED1; /**< Matrix values for calculation of the red output value., offset: 0x8C14 */
68523 __IO uint32_t MATRIX4_GREEN0; /**< Matrix values for calculation of the green output value., offset: 0x8C18 */
68524 __IO uint32_t MATRIX4_GREEN1; /**< Matrix values for calculation of the green output value., offset: 0x8C1C */
68525 __IO uint32_t MATRIX4_BLUE0; /**< Matrix values for calculation of the blue output value., offset: 0x8C20 */
68526 __IO uint32_t MATRIX4_BLUE1; /**< Matrix values for calculation of the blue output value., offset: 0x8C24 */
68527 __IO uint32_t MATRIX4_ALPHA0; /**< Matrix values for calculation of the alpha output value., offset: 0x8C28 */
68528 __IO uint32_t MATRIX4_ALPHA1; /**< Matrix values for calculation of the alpha output value., offset: 0x8C2C */
68529 __IO uint32_t MATRIX4_OFFSETVECTOR0; /**< Offset vectors for red and green output., offset: 0x8C30 */
68530 __IO uint32_t MATRIX4_OFFSETVECTOR1; /**< Offset vectors for blue and alpha output., offset: 0x8C34 */
68531 __I uint32_t MATRIX4_LASTCONTROLWORD; /**< Value of last received control word, for debugging., offset: 0x8C38 */
68532 uint8_t RESERVED_71[964];
68533 __I uint32_t HSCALER4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x9000 */
68534 __I uint32_t HSCALER4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x9004 */
68535 __IO uint32_t HSCALER4_STATICCONTROL; /**< Static control settings that must typically be setup once only., offset: 0x9008 */
68536 __IO uint32_t HSCALER4_SETUP1; /**< Phase interpolator setup., offset: 0x900C */
68537 __IO uint32_t HSCALER4_SETUP2; /**< Phase interpolator setup., offset: 0x9010 */
68538 __IO uint32_t HSCALER4_CONTROL; /**< Scaler operation control., offset: 0x9014 */
68539 uint8_t RESERVED_72[1000];
68540 __I uint32_t VSCALER4_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x9400 */
68541 __I uint32_t VSCALER4_LOCKSTATUS; /**< Protection status of this address block., offset: 0x9404 */
68542 __IO uint32_t VSCALER4_STATICCONTROL; /**< Static control settings that must typically be setup once only., offset: 0x9408 */
68543 __IO uint32_t VSCALER4_SETUP1; /**< Phase interpolator setup., offset: 0x940C */
68544 __IO uint32_t VSCALER4_SETUP2; /**< Phase interpolator setup, selected if input and output field polarity is 0., offset: 0x9410 */
68545 __IO uint32_t VSCALER4_SETUP3; /**< Phase interpolator setup, selected if input field polarity is 1 and output field polarity is 0., offset: 0x9414 */
68546 __IO uint32_t VSCALER4_SETUP4; /**< Phase interpolator setup, selected if input field polarity is 0 and output field polarity is 1., offset: 0x9418 */
68547 __IO uint32_t VSCALER4_SETUP5; /**< Phase interpolator setup, selected if input and output field polarity is 1., offset: 0x941C */
68548 __IO uint32_t VSCALER4_CONTROL; /**< Scaler operation control., offset: 0x9420 */
68549 uint8_t RESERVED_73[988];
68550 __I uint32_t MATRIX5_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x9800 */
68551 __I uint32_t MATRIX5_LOCKSTATUS; /**< Protection status of this address block., offset: 0x9804 */
68552 __IO uint32_t MATRIX5_STATICCONTROL; /**< Color Matrix static control register, offset: 0x9808 */
68553 __IO uint32_t MATRIX5_CONTROL; /**< Color Matrix control register, offset: 0x980C */
68554 __IO uint32_t MATRIX5_RED0; /**< Matrix values for calculation of the red output value., offset: 0x9810 */
68555 __IO uint32_t MATRIX5_RED1; /**< Matrix values for calculation of the red output value., offset: 0x9814 */
68556 __IO uint32_t MATRIX5_GREEN0; /**< Matrix values for calculation of the green output value., offset: 0x9818 */
68557 __IO uint32_t MATRIX5_GREEN1; /**< Matrix values for calculation of the green output value., offset: 0x981C */
68558 __IO uint32_t MATRIX5_BLUE0; /**< Matrix values for calculation of the blue output value., offset: 0x9820 */
68559 __IO uint32_t MATRIX5_BLUE1; /**< Matrix values for calculation of the blue output value., offset: 0x9824 */
68560 __IO uint32_t MATRIX5_ALPHA0; /**< Matrix values for calculation of the alpha output value., offset: 0x9828 */
68561 __IO uint32_t MATRIX5_ALPHA1; /**< Matrix values for calculation of the alpha output value., offset: 0x982C */
68562 __IO uint32_t MATRIX5_OFFSETVECTOR0; /**< Offset vectors for red and green output., offset: 0x9830 */
68563 __IO uint32_t MATRIX5_OFFSETVECTOR1; /**< Offset vectors for blue and alpha output., offset: 0x9834 */
68564 __I uint32_t MATRIX5_LASTCONTROLWORD; /**< Value of last received control word, for debugging., offset: 0x9838 */
68565 uint8_t RESERVED_74[964];
68566 __I uint32_t HSCALER5_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0x9C00 */
68567 __I uint32_t HSCALER5_LOCKSTATUS; /**< Protection status of this address block., offset: 0x9C04 */
68568 __IO uint32_t HSCALER5_STATICCONTROL; /**< Static control settings that must typically be setup once only., offset: 0x9C08 */
68569 __IO uint32_t HSCALER5_SETUP1; /**< Phase interpolator setup., offset: 0x9C0C */
68570 __IO uint32_t HSCALER5_SETUP2; /**< Phase interpolator setup., offset: 0x9C10 */
68571 __IO uint32_t HSCALER5_CONTROL; /**< Scaler operation control., offset: 0x9C14 */
68572 uint8_t RESERVED_75[1000];
68573 __I uint32_t VSCALER5_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA000 */
68574 __I uint32_t VSCALER5_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA004 */
68575 __IO uint32_t VSCALER5_STATICCONTROL; /**< Static control settings that must typically be setup once only., offset: 0xA008 */
68576 __IO uint32_t VSCALER5_SETUP1; /**< Phase interpolator setup., offset: 0xA00C */
68577 __IO uint32_t VSCALER5_SETUP2; /**< Phase interpolator setup, selected if input and output field polarity is 0., offset: 0xA010 */
68578 __IO uint32_t VSCALER5_SETUP3; /**< Phase interpolator setup, selected if input field polarity is 1 and output field polarity is 0., offset: 0xA014 */
68579 __IO uint32_t VSCALER5_SETUP4; /**< Phase interpolator setup, selected if input field polarity is 0 and output field polarity is 1., offset: 0xA018 */
68580 __IO uint32_t VSCALER5_SETUP5; /**< Phase interpolator setup, selected if input and output field polarity is 1., offset: 0xA01C */
68581 __IO uint32_t VSCALER5_CONTROL; /**< Scaler operation control., offset: 0xA020 */
68582 uint8_t RESERVED_76[988];
68583 __I uint32_t LAYERBLEND0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA400 */
68584 __I uint32_t LAYERBLEND0_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA404 */
68585 __IO uint32_t LAYERBLEND0_STATICCONTROL; /**< Static control settings., offset: 0xA408 */
68586 __IO uint32_t LAYERBLEND0_CONTROL; /**< Common control settings., offset: 0xA40C */
68587 __IO uint32_t LAYERBLEND0_BLENDCONTROL; /**< Options for blend operations, offset: 0xA410 */
68588 __IO uint32_t LAYERBLEND0_POSITION; /**< Position of secondary (overlay) input frame, offset: 0xA414 */
68589 __I uint32_t LAYERBLEND0_PRIMCONTROLWORD; /**< Value of last received primary (background) control word, for debugging, offset: 0xA418 */
68590 __I uint32_t LAYERBLEND0_SECCONTROLWORD; /**< Value of last received secondary (overlay) control word, for debugging, offset: 0xA41C */
68591 uint8_t RESERVED_77[992];
68592 __I uint32_t LAYERBLEND1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xA800 */
68593 __I uint32_t LAYERBLEND1_LOCKSTATUS; /**< Protection status of this address block., offset: 0xA804 */
68594 __IO uint32_t LAYERBLEND1_STATICCONTROL; /**< Static control settings., offset: 0xA808 */
68595 __IO uint32_t LAYERBLEND1_CONTROL; /**< Common control settings., offset: 0xA80C */
68596 __IO uint32_t LAYERBLEND1_BLENDCONTROL; /**< Options for blend operations, offset: 0xA810 */
68597 __IO uint32_t LAYERBLEND1_POSITION; /**< Position of secondary (overlay) input frame, offset: 0xA814 */
68598 __I uint32_t LAYERBLEND1_PRIMCONTROLWORD; /**< Value of last received primary (background) control word, for debugging, offset: 0xA818 */
68599 __I uint32_t LAYERBLEND1_SECCONTROLWORD; /**< Value of last received secondary (overlay) control word, for debugging, offset: 0xA81C */
68600 uint8_t RESERVED_78[992];
68601 __I uint32_t LAYERBLEND2_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xAC00 */
68602 __I uint32_t LAYERBLEND2_LOCKSTATUS; /**< Protection status of this address block., offset: 0xAC04 */
68603 __IO uint32_t LAYERBLEND2_STATICCONTROL; /**< Static control settings., offset: 0xAC08 */
68604 __IO uint32_t LAYERBLEND2_CONTROL; /**< Common control settings., offset: 0xAC0C */
68605 __IO uint32_t LAYERBLEND2_BLENDCONTROL; /**< Options for blend operations, offset: 0xAC10 */
68606 __IO uint32_t LAYERBLEND2_POSITION; /**< Position of secondary (overlay) input frame, offset: 0xAC14 */
68607 __I uint32_t LAYERBLEND2_PRIMCONTROLWORD; /**< Value of last received primary (background) control word, for debugging, offset: 0xAC18 */
68608 __I uint32_t LAYERBLEND2_SECCONTROLWORD; /**< Value of last received secondary (overlay) control word, for debugging, offset: 0xAC1C */
68609 uint8_t RESERVED_79[992];
68610 __I uint32_t LAYERBLEND3_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xB000 */
68611 __I uint32_t LAYERBLEND3_LOCKSTATUS; /**< Protection status of this address block., offset: 0xB004 */
68612 __IO uint32_t LAYERBLEND3_STATICCONTROL; /**< Static control settings., offset: 0xB008 */
68613 __IO uint32_t LAYERBLEND3_CONTROL; /**< Common control settings., offset: 0xB00C */
68614 __IO uint32_t LAYERBLEND3_BLENDCONTROL; /**< Options for blend operations, offset: 0xB010 */
68615 __IO uint32_t LAYERBLEND3_POSITION; /**< Position of secondary (overlay) input frame, offset: 0xB014 */
68616 __I uint32_t LAYERBLEND3_PRIMCONTROLWORD; /**< Value of last received primary (background) control word, for debugging, offset: 0xB018 */
68617 __I uint32_t LAYERBLEND3_SECCONTROLWORD; /**< Value of last received secondary (overlay) control word, for debugging, offset: 0xB01C */
68618 uint8_t RESERVED_80[992];
68619 __I uint32_t LOCKUNLOCK0; /**< Register to change the protection status of this address block., offset: 0xB400 */
68620 __I uint32_t LOCKSTATUS0; /**< Protection status of this address block., offset: 0xB404 */
68621 __IO uint32_t CLOCKCTRL0; /**< No function in SEERIS-MVPL, internally hardwired to DIV1., offset: 0xB408 */
68622 __IO uint32_t POLARITYCTRL0; /**< Polarity control for TCon#0 input and corresponding top-level output (TCon by-pass port)., offset: 0xB40C */
68623 __IO uint32_t SRCSELECT0; /**< Tap selection for Signature (display stream 0). Disable framegen#0 for reprogramming., offset: 0xB410 */
68624 uint8_t RESERVED_81[12];
68625 __I uint32_t LOCKUNLOCK1; /**< Register to change the protection status of this address block., offset: 0xB420 */
68626 __I uint32_t LOCKSTATUS1; /**< Protection status of this address block., offset: 0xB424 */
68627 __IO uint32_t CLOCKCTRL1; /**< No function in SEERIS-MVPL, internally hardwired to DIV1., offset: 0xB428 */
68628 __IO uint32_t POLARITYCTRL1; /**< Polarity control for TCon#1 input and corresponding top-level output (TCon by-pass port)., offset: 0xB42C */
68629 __IO uint32_t SRCSELECT1; /**< Tap selection for Signature (display stream 1). Disable framegen#1 for reprogramming., offset: 0xB430 */
68630 uint8_t RESERVED_82[972];
68631 __I uint32_t FRAMEGEN0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xB800 */
68632 __I uint32_t FRAMEGEN0_LOCKSTATUS; /**< Protection status of this address block., offset: 0xB804 */
68633 __IO uint32_t FRAMEGEN0_FGSTCTRL; /**< FrameGen Static Control Register, offset: 0xB808 */
68634 __IO uint32_t FRAMEGEN0_HTCFG1; /**< FrameGen Horizontal Timing Config Register 1, offset: 0xB80C */
68635 __IO uint32_t FRAMEGEN0_HTCFG2; /**< FrameGen Horizontal Timing Config Register 2, offset: 0xB810 */
68636 __IO uint32_t FRAMEGEN0_VTCFG1; /**< FrameGen Vertical Timing Config Register 1, offset: 0xB814 */
68637 __IO uint32_t FRAMEGEN0_VTCFG2; /**< FrameGen Vertical Timing Config Register 2, offset: 0xB818 */
68638 __I uint32_t FRAMEGEN0_INT0CONFIG; /**< Coordinates of the trigger point for generation of the Int0 interrupt signal, offset: 0xB81C */
68639 __I uint32_t FRAMEGEN0_INT1CONFIG; /**< Coordinates of the trigger point for generation of the Int1 interrupt signal, offset: 0xB820 */
68640 __I uint32_t FRAMEGEN0_INT2CONFIG; /**< Coordinates of the trigger point for generation of the Int2 interrupt signal, offset: 0xB824 */
68641 __I uint32_t FRAMEGEN0_INT3CONFIG; /**< Coordinates of the trigger point for generation of the Int3 interrupt signal, offset: 0xB828 */
68642 __IO uint32_t FRAMEGEN0_PKICKCONFIG; /**< Coordinates of the trigger point for generation of the primary kick signal, offset: 0xB82C */
68643 __IO uint32_t FRAMEGEN0_SKICKCONFIG; /**< Coordinates of the trigger point for generation of the secondary kick signal, offset: 0xB830 */
68644 __IO uint32_t FRAMEGEN0_SECSTATCONFIG; /**< Configuration register for controlling the behaviour of the SecSyncStat field in the FgSecChStat register., offset: 0xB834 */
68645 __IO uint32_t FRAMEGEN0_FGSRCR1; /**< FrameGen Skew Regulation Control Register 1., offset: 0xB838 */
68646 __IO uint32_t FRAMEGEN0_FGSRCR2; /**< FrameGen Skew Regulation Control Register 2, offset: 0xB83C */
68647 __IO uint32_t FRAMEGEN0_FGSRCR3; /**< FrameGen Skew Regulation Control Register 3, offset: 0xB840 */
68648 __IO uint32_t FRAMEGEN0_FGSRCR4; /**< FrameGen Skew Regulation Control Register 4, offset: 0xB844 */
68649 __IO uint32_t FRAMEGEN0_FGSRCR5; /**< FrameGen Skew Regulation Control Register 5, offset: 0xB848 */
68650 __IO uint32_t FRAMEGEN0_FGSRCR6; /**< FrameGen Skew Regulation Control Register 6, offset: 0xB84C */
68651 __IO uint32_t FRAMEGEN0_FGKSDR; /**< FrameGen Kick System Debug Register, offset: 0xB850 */
68652 __IO uint32_t FRAMEGEN0_PACFG; /**< FrameGen Primary Area Config Register 1 (shadowed), offset: 0xB854 */
68653 __IO uint32_t FRAMEGEN0_SACFG; /**< FrameGen Secondary Area Config Register 1 (shadowed), offset: 0xB858 */
68654 __IO uint32_t FRAMEGEN0_FGINCTRL; /**< FrameGen Input Control Register (shadowed), offset: 0xB85C */
68655 __IO uint32_t FRAMEGEN0_FGINCTRLPANIC; /**< FrameGen Input Control Panic Register (shadowed), offset: 0xB860 */
68656 __IO uint32_t FRAMEGEN0_FGCCR; /**< FrameGen Constant Color Register (shadowed), offset: 0xB864 */
68657 __IO uint32_t FRAMEGEN0_FGENABLE; /**< FrameGen Enable Register, offset: 0xB868 */
68658 __O uint32_t FRAMEGEN0_FGSLR; /**< FrameGen Shadow Load Register, offset: 0xB86C */
68659 __I uint32_t FRAMEGEN0_FGENSTS; /**< FrameGen Enable Status Register, offset: 0xB870 */
68660 __I uint32_t FRAMEGEN0_FGTIMESTAMP; /**< Time stamp status., offset: 0xB874 */
68661 __I uint32_t FRAMEGEN0_FGCHSTAT; /**< FrameGen Channel Status Register, offset: 0xB878 */
68662 __O uint32_t FRAMEGEN0_FGCHSTATCLR; /**< FrameGen Channel Status Clear Register, offset: 0xB87C */
68663 __I uint32_t FRAMEGEN0_FGSKEWMON; /**< FrameGen Skew Monitor Register for Secondary Channel Skew Control, offset: 0xB880 */
68664 __I uint32_t FRAMEGEN0_FGSFIFOMIN; /**< FrameGen Secondary FIFO Min Fill Register, offset: 0xB884 */
68665 __I uint32_t FRAMEGEN0_FGSFIFOMAX; /**< FrameGen Secondary FIFO Max Fill Register, offset: 0xB888 */
68666 __O uint32_t FRAMEGEN0_FGSFIFOFILLCLR; /**< FrameGen Secondary FIFO Fill Clear Register, offset: 0xB88C */
68667 __I uint32_t FRAMEGEN0_FGSREPD; /**< FrameGen Skew Regulation ExtraPolation Debug Register, offset: 0xB890 */
68668 __I uint32_t FRAMEGEN0_FGSRFTD; /**< FrameGen Skew Regulation Frame Total Debug Register, offset: 0xB894 */
68669 uint8_t RESERVED_83[872];
68670 __I uint32_t MATRIX0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xBC00 */
68671 __I uint32_t MATRIX0_LOCKSTATUS; /**< Protection status of this address block., offset: 0xBC04 */
68672 __IO uint32_t MATRIX0_STATICCONTROL; /**< Color Matrix static control register, offset: 0xBC08 */
68673 __IO uint32_t MATRIX0_CONTROL; /**< Color Matrix control register, offset: 0xBC0C */
68674 __IO uint32_t MATRIX0_RED0; /**< Matrix values for calculation of the red output value., offset: 0xBC10 */
68675 __IO uint32_t MATRIX0_RED1; /**< Matrix values for calculation of the red output value., offset: 0xBC14 */
68676 __IO uint32_t MATRIX0_GREEN0; /**< Matrix values for calculation of the green output value., offset: 0xBC18 */
68677 __IO uint32_t MATRIX0_GREEN1; /**< Matrix values for calculation of the green output value., offset: 0xBC1C */
68678 __IO uint32_t MATRIX0_BLUE0; /**< Matrix values for calculation of the blue output value., offset: 0xBC20 */
68679 __IO uint32_t MATRIX0_BLUE1; /**< Matrix values for calculation of the blue output value., offset: 0xBC24 */
68680 __IO uint32_t MATRIX0_ALPHA0; /**< Matrix values for calculation of the alpha output value., offset: 0xBC28 */
68681 __IO uint32_t MATRIX0_ALPHA1; /**< Matrix values for calculation of the alpha output value., offset: 0xBC2C */
68682 __IO uint32_t MATRIX0_OFFSETVECTOR0; /**< Offset vectors for red and green output., offset: 0xBC30 */
68683 __IO uint32_t MATRIX0_OFFSETVECTOR1; /**< Offset vectors for blue and alpha output., offset: 0xBC34 */
68684 __I uint32_t MATRIX0_LASTCONTROLWORD; /**< Value of last received control word, for debugging., offset: 0xBC38 */
68685 uint8_t RESERVED_84[964];
68686 __I uint32_t GAMMACOR0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xC000 */
68687 __I uint32_t GAMMACOR0_LOCKSTATUS; /**< Protection status of this address block., offset: 0xC004 */
68688 __IO uint32_t GAMMACOR0_STATICCONTROL; /**< Static control settings., offset: 0xC008 */
68689 __I uint32_t GAMMACOR0_LUTSTART; /**< Start values for look-up table programming., offset: 0xC00C */
68690 __I uint32_t GAMMACOR0_LUTDELTAS; /**< Delta values for look-up table programming., offset: 0xC010 */
68691 __IO uint32_t GAMMACOR0_CONTROL; /**< Dynamic control settings., offset: 0xC014 */
68692 __IO uint32_t GAMMACOR0_STATUS; /**< Internal status bits., offset: 0xC018 */
68693 __I uint32_t GAMMACOR0_LASTCONTROLWORD; /**< Value of last received control word., offset: 0xC01C */
68694 uint8_t RESERVED_85[992];
68695 __I uint32_t DITHER0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xC400 */
68696 __I uint32_t DITHER0_LOCKSTATUS; /**< Protection status of this address block., offset: 0xC404 */
68697 __IO uint32_t DITHER0_CONTROL; /**< Dither Unit common control., offset: 0xC408 */
68698 __IO uint32_t DITHER0_DITHERCONTROL; /**< Dither Unit processing control., offset: 0xC40C */
68699 __I uint32_t DITHER0_RELEASE; /**< Dither Unit release., offset: 0xC410 */
68700 uint8_t RESERVED_86[1004];
68701 __I uint32_t TCON0_SSQCNTS; /**< The 64 Sequencer Position Definitions registers define the X/Y scan positions of the sequencers, hold their output value and assign the sequencer to an odd/even field, offset: 0xC800 */
68702 uint8_t RESERVED_87[1020];
68703 __I uint32_t TCON0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xCC00 */
68704 __I uint32_t TCON0_LOCKSTATUS; /**< Protection status of this address block., offset: 0xCC04 */
68705 __IO uint32_t TCON0_SSQCYCLE; /**< This bitfield sets the sequencer cycle length. The value set here -1 is the number of sequencer cycles, offset: 0xCC08 */
68706 __IO uint32_t TCON0_SWRESET; /**< TCON Software Reset - Reset all tcon registers except configuration registers. Detailed description in specification document Note: 1/ if tsig[11] pulse=n*pixel_period, (n-1)*0xFF will be blent between ResetWordStart and ResetWordEnd into miniLVDS stream Note: 2/ if( EnResetWord=0) Reset-Pulse (ResetWordStart,ResetWordEnd) won't be blent into miniLVDS stream. Pixels will be transfered unchanged, offset: 0xCC0C */
68707 __IO uint32_t TCON0_CTRL; /**< TCON Control register, offset: 0xCC10 */
68708 __IO uint32_t RSDSINVCTRL; /**< Controls inversion of output polarity when connected IO cells operate in RSDS mode, offset: 0xCC14 */
68709 __IO uint32_t TCON0_MAPBIT3_0; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 0..3, offset: 0xCC18 */
68710 __IO uint32_t TCON0_MAPBIT7_4; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 4..7, offset: 0xCC1C */
68711 __IO uint32_t TCON0_MAPBIT11_8; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 8..11, offset: 0xCC20 */
68712 __IO uint32_t TCON0_MAPBIT15_12; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 12..15, offset: 0xCC24 */
68713 __IO uint32_t TCON0_MAPBIT19_16; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 16..19, offset: 0xCC28 */
68714 __IO uint32_t TCON0_MAPBIT23_20; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 20..23, offset: 0xCC2C */
68715 __IO uint32_t TCON0_MAPBIT27_24; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 24..27, offset: 0xCC30 */
68716 __IO uint32_t TCON0_MAPBIT31_28; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 28..31, offset: 0xCC34 */
68717 __IO uint32_t TCON0_MAPBIT34_32; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 32..34, offset: 0xCC38 */
68718 __IO uint32_t TCON0_MAPBIT3_0_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 0..3 2nd channel, offset: 0xCC3C */
68719 __IO uint32_t TCON0_MAPBIT7_4_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 4..7 2nd channel, offset: 0xCC40 */
68720 __IO uint32_t TCON0_MAPBIT11_8_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 8..11 2nd channel, offset: 0xCC44 */
68721 __IO uint32_t TCON0_MAPBIT15_12_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 12..15 2nd channel, offset: 0xCC48 */
68722 __IO uint32_t TCON0_MAPBIT19_16_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 16..19 2nd channel, offset: 0xCC4C */
68723 __IO uint32_t TCON0_MAPBIT23_20_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 20..23 2nd channel, offset: 0xCC50 */
68724 __IO uint32_t TCON0_MAPBIT27_24_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 24..27 2nd channel, offset: 0xCC54 */
68725 __IO uint32_t TCON0_MAPBIT31_28_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 28..31 2nd channel, offset: 0xCC58 */
68726 __IO uint32_t TCON0_MAPBIT34_32_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 32..34 2nd channel, offset: 0xCC5C */
68727 __IO uint32_t TCON0_SPG0POSON; /**< Sync pulse generator 0, 'Switch on' position, offset: 0xCC60 */
68728 __IO uint32_t TCON0_SPG0MASKON; /**< The Sequencer Pulse Generator 0 Mask Enable register is used to mask the enable of SPG 0, offset: 0xCC64 */
68729 __IO uint32_t TCON0_SPG0POSOFF; /**< Sync pulse generator 0, 'Switch off' position, offset: 0xCC68 */
68730 __IO uint32_t TCON0_SPG0MASKOFF; /**< The Sequencer Pulse Generator 0 Mask Enable register is used to mask the disable of SPG 0, offset: 0xCC6C */
68731 __IO uint32_t TCON0_SPG1POSON; /**< Sync pulse generator 1, 'Switch on' position, offset: 0xCC70 */
68732 __IO uint32_t TCON0_SPG1MASKON; /**< The Sequencer Pulse Generator 1 Mask Enable register is used to mask the enable of SPG 1, offset: 0xCC74 */
68733 __IO uint32_t TCON0_SPG1POSOFF; /**< Sync pulse generator 1, 'Switch off' position, offset: 0xCC78 */
68734 __IO uint32_t TCON0_SPG1MASKOFF; /**< The Sequencer Pulse Generator 1 Mask Enable register is used to mask the disable of SPG 1, offset: 0xCC7C */
68735 __IO uint32_t TCON0_SPG2POSON; /**< Sync pulse generator 2, 'Switch on' position, offset: 0xCC80 */
68736 __IO uint32_t TCON0_SPG2MASKON; /**< The Sequencer Pulse Generator 2 Mask Enable register is used to mask the enable of SPG 2, offset: 0xCC84 */
68737 __IO uint32_t TCON0_SPG2POSOFF; /**< Sync pulse generator 2, 'Switch off' position, offset: 0xCC88 */
68738 __IO uint32_t TCON0_SPG2MASKOFF; /**< The Sequencer Pulse Generator 2 Mask Enable register is used to mask the disable of SPG 2, offset: 0xCC8C */
68739 __IO uint32_t TCON0_SPG3POSON; /**< Sync pulse generator 3, 'Switch on' position, offset: 0xCC90 */
68740 __IO uint32_t TCON0_SPG3MASKON; /**< The Sequencer Pulse Generator 3 Mask Enable register is used to mask the enable of SPG 3, offset: 0xCC94 */
68741 __IO uint32_t TCON0_SPG3POSOFF; /**< Sync pulse generator 3, 'Switch off' position, offset: 0xCC98 */
68742 __IO uint32_t TCON0_SPG3MASKOFF; /**< The Sequencer Pulse Generator 3 Mask Enable register is used to mask the disable of SPG 3, offset: 0xCC9C */
68743 __IO uint32_t TCON0_SPG4POSON; /**< Sync pulse generator 4, 'Switch on' position, offset: 0xCCA0 */
68744 __IO uint32_t TCON0_SPG4MASKON; /**< The Sequencer Pulse Generator 4 Mask Enable register is used to mask the enable of SPG 4, offset: 0xCCA4 */
68745 __IO uint32_t TCON0_SPG4POSOFF; /**< Sync pulse generator 4, 'Switch off' position, offset: 0xCCA8 */
68746 __IO uint32_t TCON0_SPG4MASKOFF; /**< The Sequencer Pulse Generator 4 Mask Enable register is used to mask the disable of SPG 4, offset: 0xCCAC */
68747 __IO uint32_t TCON0_SPG5POSON; /**< Sync pulse generator 5, 'Switch on' position, offset: 0xCCB0 */
68748 __IO uint32_t TCON0_SPG5MASKON; /**< The Sequencer Pulse Generator 5 Mask Enable register is used to mask the enable of SPG 5, offset: 0xCCB4 */
68749 __IO uint32_t TCON0_SPG5POSOFF; /**< Sync pulse generator 5, 'Switch off' position, offset: 0xCCB8 */
68750 __IO uint32_t TCON0_SPG5MASKOFF; /**< The Sequencer Pulse Generator 5 Mask Enable register is used to mask the disable of SPG 5, offset: 0xCCBC */
68751 __IO uint32_t TCON0_SPG6POSON; /**< Sync pulse generator 6, 'Switch on' position, offset: 0xCCC0 */
68752 __IO uint32_t TCON0_SPG6MASKON; /**< The Sequencer Pulse Generator 6 Mask Enable register is used to mask the enable of SPG 6, offset: 0xCCC4 */
68753 __IO uint32_t TCON0_SPG6POSOFF; /**< Sync pulse generator 6, 'Switch off' position, offset: 0xCCC8 */
68754 __IO uint32_t TCON0_SPG6MASKOFF; /**< The Sequencer Pulse Generator 6 Mask Enable register is used to mask the disable of SPG 6, offset: 0xCCCC */
68755 __IO uint32_t TCON0_SPG7POSON; /**< Sync pulse generator 7, 'Switch on' position, offset: 0xCCD0 */
68756 __IO uint32_t TCON0_SPG7MASKON; /**< The Sequencer Pulse Generator 7 Mask Enable register is used to mask the enable of SPG 7, offset: 0xCCD4 */
68757 __IO uint32_t TCON0_SPG7POSOFF; /**< Sync pulse generator 7, 'Switch off' position, offset: 0xCCD8 */
68758 __IO uint32_t TCON0_SPG7MASKOFF; /**< The Sequencer Pulse Generator 7 Mask Enable register is used to mask the disable of SPG 7, offset: 0xCCDC */
68759 __IO uint32_t TCON0_SPG8POSON; /**< Sync pulse generator 8, 'Switch on' position, offset: 0xCCE0 */
68760 __IO uint32_t TCON0_SPG8MASKON; /**< The Sequencer Pulse Generator 8 Mask Enable register is used to mask the enable of SPG 8, offset: 0xCCE4 */
68761 __IO uint32_t TCON0_SPG8POSOFF; /**< Sync pulse generator 8, 'Switch off' position, offset: 0xCCE8 */
68762 __IO uint32_t TCON0_SPG8MASKOFF; /**< The Sequencer Pulse Generator 8 Mask Enable register is used to mask the disable of SPG 8, offset: 0xCCEC */
68763 __IO uint32_t TCON0_SPG9POSON; /**< Sync pulse generator 9, 'Switch on' position, offset: 0xCCF0 */
68764 __IO uint32_t TCON0_SPG9MASKON; /**< The Sequencer Pulse Generator 9 Mask Enable register is used to mask the enable of SPG 9, offset: 0xCCF4 */
68765 __IO uint32_t TCON0_SPG9POSOFF; /**< Sync pulse generator 9, 'Switch off' position, offset: 0xCCF8 */
68766 __IO uint32_t TCON0_SPG9MASKOFF; /**< The Sequencer Pulse Generator 9 Mask Enable register is used to mask the disable of SPG 9, offset: 0xCCFC */
68767 __IO uint32_t TCON0_SPG10POSON; /**< Sync pulse generator 10, 'Switch on' position, offset: 0xCD00 */
68768 __IO uint32_t TCON0_SPG10MASKON; /**< The Sequencer Pulse Generator 10 Mask Enable register is used to mask the enable of SPG 10, offset: 0xCD04 */
68769 __IO uint32_t TCON0_SPG10POSOFF; /**< Sync pulse generator 10, 'Switch off' position, offset: 0xCD08 */
68770 __IO uint32_t TCON0_SPG10MASKOFF; /**< The Sequencer Pulse Generator 10 Mask Enable register is used to mask the disable of SPG 10, offset: 0xCD0C */
68771 __IO uint32_t TCON0_SPG11POSON; /**< Sync pulse generator 11, 'Switch on' position, offset: 0xCD10 */
68772 __IO uint32_t TCON0_SPG11MASKON; /**< The Sequencer Pulse Generator 11 Mask Enable register is used to mask the enable of SPG 11, offset: 0xCD14 */
68773 __IO uint32_t TCON0_SPG11POSOFF; /**< Sync pulse generator 11, 'Switch off' position, offset: 0xCD18 */
68774 __IO uint32_t TCON0_SPG11MASKOFF; /**< The Sequencer Pulse Generator 11 Mask Enable register is used to mask the disable of SPG 11, offset: 0xCD1C */
68775 __IO uint32_t TCON0_SMX0SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD20 */
68776 __IO uint32_t TCON0_SMX0FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD24 */
68777 __IO uint32_t TCON0_SMX1SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD28 */
68778 __IO uint32_t TCON0_SMX1FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD2C */
68779 __IO uint32_t TCON0_SMX2SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD30 */
68780 __IO uint32_t TCON0_SMX2FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s**3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD34 */
68781 __IO uint32_t TCON0_SMX3SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD38 */
68782 __IO uint32_t TCON0_SMX3FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD3C */
68783 __IO uint32_t TCON0_SMX4SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD40 */
68784 __IO uint32_t TCON0_SMX4FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD44 */
68785 __IO uint32_t TCON0_SMX5SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD48 */
68786 __IO uint32_t TCON0_SMX5FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD4C */
68787 __IO uint32_t TCON0_SMX6SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD50 */
68788 __IO uint32_t TCON0_SMX6FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD54 */
68789 __IO uint32_t TCON0_SMX7SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD58 */
68790 __IO uint32_t TCON0_SMX7FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD5C */
68791 __IO uint32_t TCON0_SMX8SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD60 */
68792 __IO uint32_t TCON0_SMX8FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD64 */
68793 __IO uint32_t TCON0_SMX9SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD68 */
68794 __IO uint32_t TCON0_SMX9FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD6C */
68795 __IO uint32_t TCON0_SMX10SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD70 */
68796 __IO uint32_t TCON0_SMX10FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD74 */
68797 __IO uint32_t TCON0_SMX11SIGS; /**< Selection of input signals of sync mixer, offset: 0xCD78 */
68798 __IO uint32_t TCON0_SMX11FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xCD7C */
68799 __O uint32_t TCON0_RESET_OVER_UNFERFLOW; /**< reset status overflow and underflow of both dual channel fifos, offset: 0xCD80 */
68800 __I uint32_t TCON0_DUAL_DEBUG; /**< Status of fifo during dual channel operation. They are only available in Split Mode For Debug only, offset: 0xCD84 */
68801 uint8_t RESERVED_88[632];
68802 __I uint32_t SIG0_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xD000 */
68803 __I uint32_t SIG0_LOCKSTATUS; /**< Protection status of this address block., offset: 0xD004 */
68804 __IO uint32_t SIG0_STATICCONTROL; /**< Global configuration shared by all evaluation windows., offset: 0xD008 */
68805 __IO uint32_t SIG0_PANICCOLOR; /**< Overlay color for evaluation windows in panic mode., offset: 0xD00C */
68806 __IO uint32_t SIG0_EVALCONTROL0; /**< Control settings for evaluation window 0., offset: 0xD010 */
68807 __IO uint32_t SIG0_EVALUPPERLEFT0; /**< Upper left corner of evaluation window 0., offset: 0xD014 */
68808 __IO uint32_t SIG0_EVALLOWERRIGHT0; /**< Lower right corner of evaluation window 0., offset: 0xD018 */
68809 __IO uint32_t SIG0_SIGCRCREDREF0; /**< Reference signature of red channel for evaluation window 0., offset: 0xD01C */
68810 __IO uint32_t SIG0_SIGCRCGREENREF0; /**< Reference signature of green channel for evaluation window 0., offset: 0xD020 */
68811 __IO uint32_t SIG0_SIGCRCBLUEREF0; /**< Reference signature of blue channel for evaluation window 0., offset: 0xD024 */
68812 __I uint32_t SIG0_SIGCRCRED0; /**< Measured signature of red channel for evaluation window 0., offset: 0xD028 */
68813 __I uint32_t SIG0_SIGCRCGREEN0; /**< Measured signature of green channel for evaluation window 0., offset: 0xD02C */
68814 __I uint32_t SIG0_SIGCRCBLUE0; /**< Measured signature of blue channel for evaluation window 0., offset: 0xD030 */
68815 __IO uint32_t SIG0_EVALCONTROL1; /**< Control settings for evaluation window 1., offset: 0xD034 */
68816 __IO uint32_t SIG0_EVALUPPERLEFT1; /**< Upper left corner of evaluation window 1., offset: 0xD038 */
68817 __IO uint32_t SIG0_EVALLOWERRIGHT1; /**< Lower right corner of evaluation window 1., offset: 0xD03C */
68818 __IO uint32_t SIG0_SIGCRCREDREF1; /**< Reference signature of red channel for evaluation window 1., offset: 0xD040 */
68819 __IO uint32_t SIG0_SIGCRCGREENREF1; /**< Reference signature of green channel for evaluation window 1., offset: 0xD044 */
68820 __IO uint32_t SIG0_SIGCRCBLUEREF1; /**< Reference signature of blue channel for evaluation window 1., offset: 0xD048 */
68821 __I uint32_t SIG0_SIGCRCRED1; /**< Measured signature of red channel for evaluation window 1., offset: 0xD04C */
68822 __I uint32_t SIG0_SIGCRCGREEN1; /**< Measured signature of green channel for evaluation window 1., offset: 0xD050 */
68823 __I uint32_t SIG0_SIGCRCBLUE1; /**< Measured signature of blue channel for evaluation window 1., offset: 0xD054 */
68824 __IO uint32_t SIG0_EVALCONTROL2; /**< Control settings for evaluation window 2., offset: 0xD058 */
68825 __IO uint32_t SIG0_EVALUPPERLEFT2; /**< Upper left corner of evaluation window 2., offset: 0xD05C */
68826 __IO uint32_t SIG0_EVALLOWERRIGHT2; /**< Lower right corner of evaluation window 2., offset: 0xD060 */
68827 __IO uint32_t SIG0_SIGCRCREDREF2; /**< Reference signature of red channel for evaluation window 2., offset: 0xD064 */
68828 __IO uint32_t SIG0_SIGCRCGREENREF2; /**< Reference signature of green channel for evaluation window 2., offset: 0xD068 */
68829 __IO uint32_t SIG0_SIGCRCBLUEREF2; /**< Reference signature of blue channel for evaluation window 2., offset: 0xD06C */
68830 __I uint32_t SIG0_SIGCRCRED2; /**< Measured signature of red channel for evaluation window 2., offset: 0xD070 */
68831 __I uint32_t SIG0_SIGCRCGREEN2; /**< Measured signature of green channel for evaluation window 2., offset: 0xD074 */
68832 __I uint32_t SIG0_SIGCRCBLUE2; /**< Measured signature of blue channel for evaluation window 2., offset: 0xD078 */
68833 __IO uint32_t SIG0_EVALCONTROL3; /**< Control settings for evaluation window 3., offset: 0xD07C */
68834 __IO uint32_t SIG0_EVALUPPERLEFT3; /**< Upper left corner of evaluation window 3., offset: 0xD080 */
68835 __IO uint32_t SIG0_EVALLOWERRIGHT3; /**< Lower right corner of evaluation window 3., offset: 0xD084 */
68836 __IO uint32_t SIG0_SIGCRCREDREF3; /**< Reference signature of red channel for evaluation window 3., offset: 0xD088 */
68837 __IO uint32_t SIG0_SIGCRCGREENREF3; /**< Reference signature of green channel for evaluation window 3., offset: 0xD08C */
68838 __IO uint32_t SIG0_SIGCRCBLUEREF3; /**< Reference signature of blue channel for evaluation window 3., offset: 0xD090 */
68839 __I uint32_t SIG0_SIGCRCRED3; /**< Measured signature of red channel for evaluation window 3., offset: 0xD094 */
68840 __I uint32_t SIG0_SIGCRCGREEN3; /**< Measured signature of green channel for evaluation window 3., offset: 0xD098 */
68841 __I uint32_t SIG0_SIGCRCBLUE3; /**< Measured signature of blue channel for evaluation window 3., offset: 0xD09C */
68842 __IO uint32_t SIG0_EVALCONTROL4; /**< Control settings for evaluation window 4., offset: 0xD0A0 */
68843 __IO uint32_t SIG0_EVALUPPERLEFT4; /**< Upper left corner of evaluation window 4., offset: 0xD0A4 */
68844 __IO uint32_t SIG0_EVALLOWERRIGHT4; /**< Lower right corner of evaluation window 4., offset: 0xD0A8 */
68845 __IO uint32_t SIG0_SIGCRCREDREF4; /**< Reference signature of red channel for evaluation window 4., offset: 0xD0AC */
68846 __IO uint32_t SIG0_SIGCRCGREENREF4; /**< Reference signature of green channel for evaluation window 4., offset: 0xD0B0 */
68847 __IO uint32_t SIG0_SIGCRCBLUEREF4; /**< Reference signature of blue channel for evaluation window 4., offset: 0xD0B4 */
68848 __I uint32_t SIG0_SIGCRCRED4; /**< Measured signature of red channel for evaluation window 4., offset: 0xD0B8 */
68849 __I uint32_t SIG0_SIGCRCGREEN4; /**< Measured signature of green channel for evaluation window 4., offset: 0xD0BC */
68850 __I uint32_t SIG0_SIGCRCBLUE4; /**< Measured signature of blue channel for evaluation window 4., offset: 0xD0C0 */
68851 __IO uint32_t SIG0_EVALCONTROL5; /**< Control settings for evaluation window 5., offset: 0xD0C4 */
68852 __IO uint32_t SIG0_EVALUPPERLEFT5; /**< Upper left corner of evaluation window 5., offset: 0xD0C8 */
68853 __IO uint32_t SIG0_EVALLOWERRIGHT5; /**< Lower right corner of evaluation window 5., offset: 0xD0CC */
68854 __IO uint32_t SIG0_SIGCRCREDREF5; /**< Reference signature of red channel for evaluation window 5., offset: 0xD0D0 */
68855 __IO uint32_t SIG0_SIGCRCGREENREF5; /**< Reference signature of green channel for evaluation window 5., offset: 0xD0D4 */
68856 __IO uint32_t SIG0_SIGCRCBLUEREF5; /**< Reference signature of blue channel for evaluation window 5., offset: 0xD0D8 */
68857 __I uint32_t SIG0_SIGCRCRED5; /**< Measured signature of red channel for evaluation window 5., offset: 0xD0DC */
68858 __I uint32_t SIG0_SIGCRCGREEN5; /**< Measured signature of green channel for evaluation window 5., offset: 0xD0E0 */
68859 __I uint32_t SIG0_SIGCRCBLUE5; /**< Measured signature of blue channel for evaluation window 5., offset: 0xD0E4 */
68860 __IO uint32_t SIG0_EVALCONTROL6; /**< Control settings for evaluation window 6., offset: 0xD0E8 */
68861 __IO uint32_t SIG0_EVALUPPERLEFT6; /**< Upper left corner of evaluation window 6., offset: 0xD0EC */
68862 __IO uint32_t SIG0_EVALLOWERRIGHT6; /**< Lower right corner of evaluation window 6., offset: 0xD0F0 */
68863 __IO uint32_t SIG0_SIGCRCREDREF6; /**< Reference signature of red channel for evaluation window 6., offset: 0xD0F4 */
68864 __IO uint32_t SIG0_SIGCRCGREENREF6; /**< Reference signature of green channel for evaluation window 6., offset: 0xD0F8 */
68865 __IO uint32_t SIG0_SIGCRCBLUEREF6; /**< Reference signature of blue channel for evaluation window 6., offset: 0xD0FC */
68866 __I uint32_t SIG0_SIGCRCRED6; /**< Measured signature of red channel for evaluation window 6., offset: 0xD100 */
68867 __I uint32_t SIG0_SIGCRCGREEN6; /**< Measured signature of green channel for evaluation window 6., offset: 0xD104 */
68868 __I uint32_t SIG0_SIGCRCBLUE6; /**< Measured signature of blue channel for evaluation window 6., offset: 0xD108 */
68869 __IO uint32_t SIG0_EVALCONTROL7; /**< Control settings for evaluation window 7., offset: 0xD10C */
68870 __IO uint32_t SIG0_EVALUPPERLEFT7; /**< Upper left corner of evaluation window 7., offset: 0xD110 */
68871 __IO uint32_t SIG0_EVALLOWERRIGHT7; /**< Lower right corner of evaluation window 7., offset: 0xD114 */
68872 __IO uint32_t SIG0_SIGCRCREDREF7; /**< Reference signature of red channel for evaluation window 7., offset: 0xD118 */
68873 __IO uint32_t SIG0_SIGCRCGREENREF7; /**< Reference signature of green channel for evaluation window 7., offset: 0xD11C */
68874 __IO uint32_t SIG0_SIGCRCBLUEREF7; /**< Reference signature of blue channel for evaluation window 7., offset: 0xD120 */
68875 __I uint32_t SIG0_SIGCRCRED7; /**< Measured signature of red channel for evaluation window 7., offset: 0xD124 */
68876 __I uint32_t SIG0_SIGCRCGREEN7; /**< Measured signature of green channel for evaluation window 7., offset: 0xD128 */
68877 __I uint32_t SIG0_SIGCRCBLUE7; /**< Measured signature of blue channel for evaluation window 7., offset: 0xD12C */
68878 __I uint32_t SIG0_SHADOWLOAD; /**< Shadow load control register., offset: 0xD130 */
68879 __IO uint32_t SIG0_CONTINUOUSMODE; /**< Signature operation mode control., offset: 0xD134 */
68880 __O uint32_t SIG0_SOFTWAREKICK; /**< Signature measurement trigger., offset: 0xD138 */
68881 __I uint32_t SIG0_STATUS; /**< Module status., offset: 0xD13C */
68882 uint8_t RESERVED_89[704];
68883 __I uint32_t FRAMEGEN1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xD400 */
68884 __I uint32_t FRAMEGEN1_LOCKSTATUS; /**< Protection status of this address block., offset: 0xD404 */
68885 __IO uint32_t FRAMEGEN1_FGSTCTRL; /**< FrameGen Static Control Register, offset: 0xD408 */
68886 __IO uint32_t FRAMEGEN1_HTCFG1; /**< FrameGen Horizontal Timing Config Register 1, offset: 0xD40C */
68887 __IO uint32_t FRAMEGEN1_HTCFG2; /**< FrameGen Horizontal Timing Config Register 2, offset: 0xD410 */
68888 __IO uint32_t FRAMEGEN1_VTCFG1; /**< FrameGen Vertical Timing Config Register 1, offset: 0xD414 */
68889 __IO uint32_t FRAMEGEN1_VTCFG2; /**< FrameGen Vertical Timing Config Register 2, offset: 0xD418 */
68890 __I uint32_t FRAMEGEN1_INT0CONFIG; /**< Coordinates of the trigger point for generation of the Int0 interrupt signal, offset: 0xD41C */
68891 __I uint32_t FRAMEGEN1_INT1CONFIG; /**< Coordinates of the trigger point for generation of the Int1 interrupt signal, offset: 0xD420 */
68892 __I uint32_t FRAMEGEN1_INT2CONFIG; /**< Coordinates of the trigger point for generation of the Int2 interrupt signal, offset: 0xD424 */
68893 __I uint32_t FRAMEGEN1_INT3CONFIG; /**< Coordinates of the trigger point for generation of the Int3 interrupt signal, offset: 0xD428 */
68894 __IO uint32_t FRAMEGEN1_PKICKCONFIG; /**< Coordinates of the trigger point for generation of the primary kick signal, offset: 0xD42C */
68895 __IO uint32_t FRAMEGEN1_SKICKCONFIG; /**< Coordinates of the trigger point for generation of the secondary kick signal, offset: 0xD430 */
68896 __IO uint32_t FRAMEGEN1_SECSTATCONFIG; /**< Configuration register for controlling the behaviour of the SecSyncStat field in the FgSecChStat register., offset: 0xD434 */
68897 __IO uint32_t FRAMEGEN1_FGSRCR1; /**< FrameGen Skew Regulation Control Register 1., offset: 0xD438 */
68898 __IO uint32_t FRAMEGEN1_FGSRCR2; /**< FrameGen Skew Regulation Control Register 2, offset: 0xD43C */
68899 __IO uint32_t FRAMEGEN1_FGSRCR3; /**< FrameGen Skew Regulation Control Register 3, offset: 0xD440 */
68900 __IO uint32_t FRAMEGEN1_FGSRCR4; /**< FrameGen Skew Regulation Control Register 4, offset: 0xD444 */
68901 __IO uint32_t FRAMEGEN1_FGSRCR5; /**< FrameGen Skew Regulation Control Register 5, offset: 0xD448 */
68902 __IO uint32_t FRAMEGEN1_FGSRCR6; /**< FrameGen Skew Regulation Control Register 6, offset: 0xD44C */
68903 __IO uint32_t FRAMEGEN1_FGKSDR; /**< FrameGen Kick System Debug Register, offset: 0xD450 */
68904 __IO uint32_t FRAMEGEN1_PACFG; /**< FrameGen Primary Area Config Register 1 (shadowed), offset: 0xD454 */
68905 __IO uint32_t FRAMEGEN1_SACFG; /**< FrameGen Secondary Area Config Register 1 (shadowed), offset: 0xD458 */
68906 __IO uint32_t FRAMEGEN1_FGINCTRL; /**< FrameGen Input Control Register (shadowed), offset: 0xD45C */
68907 __IO uint32_t FRAMEGEN1_FGINCTRLPANIC; /**< FrameGen Input Control Panic Register (shadowed), offset: 0xD460 */
68908 __IO uint32_t FRAMEGEN1_FGCCR; /**< FrameGen Constant Color Register (shadowed), offset: 0xD464 */
68909 __IO uint32_t FRAMEGEN1_FGENABLE; /**< FrameGen Enable Register, offset: 0xD468 */
68910 __O uint32_t FRAMEGEN1_FGSLR; /**< FrameGen Shadow Load Register, offset: 0xD46C */
68911 __I uint32_t FRAMEGEN1_FGENSTS; /**< FrameGen Enable Status Register, offset: 0xD470 */
68912 __I uint32_t FRAMEGEN1_FGTIMESTAMP; /**< Time stamp status., offset: 0xD474 */
68913 __I uint32_t FRAMEGEN1_FGCHSTAT; /**< FrameGen Channel Status Register, offset: 0xD478 */
68914 __O uint32_t FRAMEGEN1_FGCHSTATCLR; /**< FrameGen Channel Status Clear Register, offset: 0xD47C */
68915 __I uint32_t FRAMEGEN1_FGSKEWMON; /**< FrameGen Skew Monitor Register for Secondary Channel Skew Control, offset: 0xD480 */
68916 __I uint32_t FRAMEGEN1_FGSFIFOMIN; /**< FrameGen Secondary FIFO Min Fill Register, offset: 0xD484 */
68917 __I uint32_t FRAMEGEN1_FGSFIFOMAX; /**< FrameGen Secondary FIFO Max Fill Register, offset: 0xD488 */
68918 __O uint32_t FRAMEGEN1_FGSFIFOFILLCLR; /**< FrameGen Secondary FIFO Fill Clear Register, offset: 0xD48C */
68919 __I uint32_t FRAMEGEN1_FGSREPD; /**< FrameGen Skew Regulation ExtraPolation Debug Register, offset: 0xD490 */
68920 __I uint32_t FRAMEGEN1_FGSRFTD; /**< FrameGen Skew Regulation Frame Total Debug Register, offset: 0xD494 */
68921 uint8_t RESERVED_90[872];
68922 __I uint32_t MATRIX1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xD800 */
68923 __I uint32_t MATRIX1_LOCKSTATUS; /**< Protection status of this address block., offset: 0xD804 */
68924 __IO uint32_t MATRIX1_STATICCONTROL; /**< Color Matrix static control register, offset: 0xD808 */
68925 __IO uint32_t MATRIX1_CONTROL; /**< Color Matrix control register, offset: 0xD80C */
68926 __IO uint32_t MATRIX1_RED0; /**< Matrix values for calculation of the red output value., offset: 0xD810 */
68927 __IO uint32_t MATRIX1_RED1; /**< Matrix values for calculation of the red output value., offset: 0xD814 */
68928 __IO uint32_t MATRIX1_GREEN0; /**< Matrix values for calculation of the green output value., offset: 0xD818 */
68929 __IO uint32_t MATRIX1_GREEN1; /**< Matrix values for calculation of the green output value., offset: 0xD81C */
68930 __IO uint32_t MATRIX1_BLUE0; /**< Matrix values for calculation of the blue output value., offset: 0xD820 */
68931 __IO uint32_t MATRIX1_BLUE1; /**< Matrix values for calculation of the blue output value., offset: 0xD824 */
68932 __IO uint32_t MATRIX1_ALPHA0; /**< Matrix values for calculation of the alpha output value., offset: 0xD828 */
68933 __IO uint32_t MATRIX1_ALPHA1; /**< Matrix values for calculation of the alpha output value., offset: 0xD82C */
68934 __IO uint32_t MATRIX1_OFFSETVECTOR0; /**< Offset vectors for red and green output., offset: 0xD830 */
68935 __IO uint32_t MATRIX1_OFFSETVECTOR1; /**< Offset vectors for blue and alpha output., offset: 0xD834 */
68936 __I uint32_t MATRIX1_LASTCONTROLWORD; /**< Value of last received control word, for debugging., offset: 0xD838 */
68937 uint8_t RESERVED_91[964];
68938 __I uint32_t GAMMACOR1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xDC00 */
68939 __I uint32_t GAMMACOR1_LOCKSTATUS; /**< Protection status of this address block., offset: 0xDC04 */
68940 __IO uint32_t GAMMACOR1_STATICCONTROL; /**< Static control settings., offset: 0xDC08 */
68941 __I uint32_t GAMMACOR1_LUTSTART; /**< Start values for look-up table programming., offset: 0xDC0C */
68942 __I uint32_t GAMMACOR1_LUTDELTAS; /**< Delta values for look-up table programming., offset: 0xDC10 */
68943 __IO uint32_t GAMMACOR1_CONTROL; /**< Dynamic control settings., offset: 0xDC14 */
68944 __IO uint32_t GAMMACOR1_STATUS; /**< Internal status bits., offset: 0xDC18 */
68945 __I uint32_t GAMMACOR1_LASTCONTROLWORD; /**< Value of last received control word., offset: 0xDC1C */
68946 uint8_t RESERVED_92[992];
68947 __I uint32_t DITHER1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xE000 */
68948 __I uint32_t DITHER1_LOCKSTATUS; /**< Protection status of this address block., offset: 0xE004 */
68949 __IO uint32_t DITHER1_CONTROL; /**< Dither Unit common control., offset: 0xE008 */
68950 __IO uint32_t DITHER1_DITHERCONTROL; /**< Dither Unit processing control., offset: 0xE00C */
68951 __I uint32_t DITHER1_RELEASE; /**< Dither Unit release., offset: 0xE010 */
68952 uint8_t RESERVED_93[2028];
68953 __I uint32_t TCON1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xE800 */
68954 __I uint32_t TCON1_LOCKSTATUS; /**< Protection status of this address block., offset: 0xE804 */
68955 __IO uint32_t TCON1_SSQCYCLE; /**< This bitfield sets the sequencer cycle length. The value set here -1 is the number of sequencer cycles, offset: 0xE808 */
68956 __IO uint32_t TCON1_SWRESET; /**< TCON Software Reset - Reset all tcon registers except configuration registers. Detailed description in specification document Note: 1/ if tsig[11] pulse=n*pixel_period, (n-1)*0xFF will be blent between ResetWordStart and ResetWordEnd into miniLVDS stream Note: 2/ if( EnResetWord=0) Reset-Pulse (ResetWordStart,ResetWordEnd) won't be blent into miniLVDS stream. Pixels will be transfered unchanged, offset: 0xE80C */
68957 __IO uint32_t TCON1_CTRL; /**< TCON Control register, offset: 0xE810 */
68958 __IO uint32_t TCON1_RSDSINVCTRL; /**< Controls inversion of output polarity when connected IO cells operate in RSDS mode, offset: 0xE814 */
68959 __IO uint32_t TCON1_MAPBIT3_0; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 0..3, offset: 0xE818 */
68960 __IO uint32_t TCON1_MAPBIT7_4; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 4..7, offset: 0xE81C */
68961 __IO uint32_t TCON1_MAPBIT11_8; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 8..11, offset: 0xE820 */
68962 __IO uint32_t TCON1_MAPBIT15_12; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 12..15, offset: 0xE824 */
68963 __IO uint32_t TCON1_MAPBIT19_16; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 16..19, offset: 0xE828 */
68964 __IO uint32_t TCON1_MAPBIT23_20; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 20..23, offset: 0xE82C */
68965 __IO uint32_t TCON1_MAPBIT27_24; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 24..27, offset: 0xE830 */
68966 __IO uint32_t TCON1_MAPBIT31_28; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 28..31, offset: 0xE834 */
68967 __IO uint32_t TCON1_MAPBIT34_32; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 32..34, offset: 0xE838 */
68968 __IO uint32_t TCON1_MAPBIT3_0_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 0..3 2nd channel, offset: 0xE83C */
68969 __IO uint32_t TCON1_MAPBIT7_4_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 4..7 2nd channel, offset: 0xE840 */
68970 __IO uint32_t TCON1_MAPBIT11_8_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 8..11 2nd channel, offset: 0xE844 */
68971 __IO uint32_t TCON1_MAPBIT15_12_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 12..15 2nd channel, offset: 0xE848 */
68972 __IO uint32_t TCON1_MAPBIT19_16_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 16..19 2nd channel, offset: 0xE84C */
68973 __IO uint32_t TCON1_MAPBIT23_20_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 20..23 2nd channel, offset: 0xE850 */
68974 __IO uint32_t TCON1_MAPBIT27_24_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 24..27 2nd channel, offset: 0xE854 */
68975 __IO uint32_t TCON1_MAPBIT31_28_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 28..31 2nd channel, offset: 0xE858 */
68976 __IO uint32_t TCON1_MAPBIT34_32_DUAL; /**< Mapping of 30 bit RGB or Timing Generator TSig[11:0] to bit 32..34 2nd channel, offset: 0xE85C */
68977 __IO uint32_t TCON1_SPG0POSON; /**< Sync pulse generator 0, 'Switch on' position, offset: 0xE860 */
68978 __IO uint32_t TCON1_SPG0MASKON; /**< The Sequencer Pulse Generator 0 Mask Enable register is used to mask the enable of SPG 0, offset: 0xE864 */
68979 __IO uint32_t TCON1_SPG0POSOFF; /**< Sync pulse generator 0, 'Switch off' position, offset: 0xE868 */
68980 __IO uint32_t TCON1_SPG0MASKOFF; /**< The Sequencer Pulse Generator 0 Mask Enable register is used to mask the disable of SPG 0, offset: 0xE86C */
68981 __IO uint32_t TCON1_SPG1POSON; /**< Sync pulse generator 1, 'Switch on' position, offset: 0xE870 */
68982 __IO uint32_t TCON1_SPG1MASKON; /**< The Sequencer Pulse Generator 1 Mask Enable register is used to mask the enable of SPG 1, offset: 0xE874 */
68983 __IO uint32_t TCON1_SPG1POSOFF; /**< Sync pulse generator 1, 'Switch off' position, offset: 0xE878 */
68984 __IO uint32_t TCON1_SPG1MASKOFF; /**< The Sequencer Pulse Generator 1 Mask Enable register is used to mask the disable of SPG 1, offset: 0xE87C */
68985 __IO uint32_t TCON1_SPG2POSON; /**< Sync pulse generator 2, 'Switch on' position, offset: 0xE880 */
68986 __IO uint32_t TCON1_SPG2MASKON; /**< The Sequencer Pulse Generator 2 Mask Enable register is used to mask the enable of SPG 2, offset: 0xE884 */
68987 __IO uint32_t TCON1_SPG2POSOFF; /**< Sync pulse generator 2, 'Switch off' position, offset: 0xE888 */
68988 __IO uint32_t TCON1_SPG2MASKOFF; /**< The Sequencer Pulse Generator 2 Mask Enable register is used to mask the disable of SPG 2, offset: 0xE88C */
68989 __IO uint32_t TCON1_SPG3POSON; /**< Sync pulse generator 3, 'Switch on' position, offset: 0xE890 */
68990 __IO uint32_t TCON1_SPG3MASKON; /**< The Sequencer Pulse Generator 3 Mask Enable register is used to mask the enable of SPG 3, offset: 0xE894 */
68991 __IO uint32_t TCON1_SPG3POSOFF; /**< Sync pulse generator 3, 'Switch off' position, offset: 0xE898 */
68992 __IO uint32_t TCON1_SPG3MASKOFF; /**< The Sequencer Pulse Generator 3 Mask Enable register is used to mask the disable of SPG 3, offset: 0xE89C */
68993 __IO uint32_t TCON1_SPG4POSON; /**< Sync pulse generator 4, 'Switch on' position, offset: 0xE8A0 */
68994 __IO uint32_t TCON1_SPG4MASKON; /**< The Sequencer Pulse Generator 4 Mask Enable register is used to mask the enable of SPG 4, offset: 0xE8A4 */
68995 __IO uint32_t TCON1_SPG4POSOFF; /**< Sync pulse generator 4, 'Switch off' position, offset: 0xE8A8 */
68996 __IO uint32_t TCON1_SPG4MASKOFF; /**< The Sequencer Pulse Generator 4 Mask Enable register is used to mask the disable of SPG 4, offset: 0xE8AC */
68997 __IO uint32_t TCON1_SPG5POSON; /**< Sync pulse generator 5, 'Switch on' position, offset: 0xE8B0 */
68998 __IO uint32_t TCON1_SPG5MASKON; /**< The Sequencer Pulse Generator 5 Mask Enable register is used to mask the enable of SPG 5, offset: 0xE8B4 */
68999 __IO uint32_t TCON1_SPG5POSOFF; /**< Sync pulse generator 5, 'Switch off' position, offset: 0xE8B8 */
69000 __IO uint32_t TCON1_SPG5MASKOFF; /**< The Sequencer Pulse Generator 5 Mask Enable register is used to mask the disable of SPG 5, offset: 0xE8BC */
69001 __IO uint32_t TCON1_SPG6POSON; /**< Sync pulse generator 6, 'Switch on' position, offset: 0xE8C0 */
69002 __IO uint32_t TCON1_SPG6MASKON; /**< The Sequencer Pulse Generator 6 Mask Enable register is used to mask the enable of SPG 6, offset: 0xE8C4 */
69003 __IO uint32_t TCON1_SPG6POSOFF; /**< Sync pulse generator 6, 'Switch off' position, offset: 0xE8C8 */
69004 __IO uint32_t TCON1_SPG6MASKOFF; /**< The Sequencer Pulse Generator 6 Mask Enable register is used to mask the disable of SPG 6, offset: 0xE8CC */
69005 __IO uint32_t TCON1_SPG7POSON; /**< Sync pulse generator 7, 'Switch on' position, offset: 0xE8D0 */
69006 __IO uint32_t TCON1_SPG7MASKON; /**< The Sequencer Pulse Generator 7 Mask Enable register is used to mask the enable of SPG 7, offset: 0xE8D4 */
69007 __IO uint32_t TCON1_SPG7POSOFF; /**< Sync pulse generator 7, 'Switch off' position, offset: 0xE8D8 */
69008 __IO uint32_t TCON1_SPG7MASKOFF; /**< The Sequencer Pulse Generator 7 Mask Enable register is used to mask the disable of SPG 7, offset: 0xE8DC */
69009 __IO uint32_t TCON1_SPG8POSON; /**< Sync pulse generator 8, 'Switch on' position, offset: 0xE8E0 */
69010 __IO uint32_t TCON1_SPG8MASKON; /**< The Sequencer Pulse Generator 8 Mask Enable register is used to mask the enable of SPG 8, offset: 0xE8E4 */
69011 __IO uint32_t TCON1_SPG8POSOFF; /**< Sync pulse generator 8, 'Switch off' position, offset: 0xE8E8 */
69012 __IO uint32_t TCON1_SPG8MASKOFF; /**< The Sequencer Pulse Generator 8 Mask Enable register is used to mask the disable of SPG 8, offset: 0xE8EC */
69013 __IO uint32_t TCON1_SPG9POSON; /**< Sync pulse generator 9, 'Switch on' position, offset: 0xE8F0 */
69014 __IO uint32_t TCON1_SPG9MASKON; /**< The Sequencer Pulse Generator 9 Mask Enable register is used to mask the enable of SPG 9, offset: 0xE8F4 */
69015 __IO uint32_t TCON1_SPG9POSOFF; /**< Sync pulse generator 9, 'Switch off' position, offset: 0xE8F8 */
69016 __IO uint32_t TCON1_SPG9MASKOFF; /**< The Sequencer Pulse Generator 9 Mask Enable register is used to mask the disable of SPG 9, offset: 0xE8FC */
69017 __IO uint32_t TCON1_SPG10POSON; /**< Sync pulse generator 10, 'Switch on' position, offset: 0xE900 */
69018 __IO uint32_t TCON1_SPG10MASKON; /**< The Sequencer Pulse Generator 10 Mask Enable register is used to mask the enable of SPG 10, offset: 0xE904 */
69019 __IO uint32_t TCON1_SPG10POSOFF; /**< Sync pulse generator 10, 'Switch off' position, offset: 0xE908 */
69020 __IO uint32_t TCON1_SPG10MASKOFF; /**< The Sequencer Pulse Generator 10 Mask Enable register is used to mask the disable of SPG 10, offset: 0xE90C */
69021 __IO uint32_t TCON1_SPG11POSON; /**< Sync pulse generator 11, 'Switch on' position, offset: 0xE910 */
69022 __IO uint32_t TCON1_SPG11MASKON; /**< The Sequencer Pulse Generator 11 Mask Enable register is used to mask the enable of SPG 11, offset: 0xE914 */
69023 __IO uint32_t TCON1_SPG11POSOFF; /**< Sync pulse generator 11, 'Switch off' position, offset: 0xE918 */
69024 __IO uint32_t TCON1_SPG11MASKOFF; /**< The Sequencer Pulse Generator 11 Mask Enable register is used to mask the disable of SPG 11, offset: 0xE91C */
69025 __IO uint32_t TCON1_SMX0SIGS; /**< Selection of input signals of sync mixer, offset: 0xE920 */
69026 __IO uint32_t TCON1_SMX0FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE924 */
69027 __IO uint32_t TCON1_SMX1SIGS; /**< Selection of input signals of sync mixer, offset: 0xE928 */
69028 __IO uint32_t TCON1_SMX1FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE92C */
69029 __IO uint32_t TCON1_SMX2SIGS; /**< Selection of input signals of sync mixer, offset: 0xE930 */
69030 __IO uint32_t TCON1_SMX2FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s**3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE934 */
69031 __IO uint32_t TCON1_SMX3SIGS; /**< Selection of input signals of sync mixer, offset: 0xE938 */
69032 __IO uint32_t TCON1_SMX3FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE93C */
69033 __IO uint32_t TCON1_SMX4SIGS; /**< Selection of input signals of sync mixer, offset: 0xE940 */
69034 __IO uint32_t TCON1_SMX4FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE944 */
69035 __IO uint32_t TCON1_SMX5SIGS; /**< Selection of input signals of sync mixer, offset: 0xE948 */
69036 __IO uint32_t TCON1_SMX5FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE94C */
69037 __IO uint32_t TCON1_SMX6SIGS; /**< Selection of input signals of sync mixer, offset: 0xE950 */
69038 __IO uint32_t TCON1_SMX6FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE954 */
69039 __IO uint32_t TCON1_SMX7SIGS; /**< Selection of input signals of sync mixer, offset: 0xE958 */
69040 __IO uint32_t TCON1_SMX7FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE95C */
69041 __IO uint32_t TCON1_SMX8SIGS; /**< Selection of input signals of sync mixer, offset: 0xE960 */
69042 __IO uint32_t TCON1_SMX8FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE964 */
69043 __IO uint32_t TCON1_SMX9SIGS; /**< Selection of input signals of sync mixer, offset: 0xE968 */
69044 __IO uint32_t TCON1_SMX9FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE96C */
69045 __IO uint32_t TCON1_SMX10SIGS; /**< Selection of input signals of sync mixer, offset: 0xE970 */
69046 __IO uint32_t TCON1_SMX10FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE974 */
69047 __IO uint32_t TCON1_SMX11SIGS; /**< Selection of input signals of sync mixer, offset: 0xE978 */
69048 __IO uint32_t TCON1_SMX11FCTTABLE; /**< The sync mixer output is the result of the function table a=s4*2**4+s3*2**3+s2*2**2+s1*2**1+s0*2**0 whereby a is bit number and s result of sync mixer input selection, offset: 0xE97C */
69049 __O uint32_t TCON1_RESET_OVER_UNFERFLOW; /**< reset status overflow and underflow of both dual channel fifos, offset: 0xE980 */
69050 __I uint32_t TCON1_DUAL_DEBUG; /**< Status of fifo during dual channel operation. They are only available in Split Mode For Debug only, offset: 0xE984 */
69051 uint8_t RESERVED_94[632];
69052 __I uint32_t SIG1_LOCKUNLOCK; /**< Register to change the protection status of this address block., offset: 0xEC00 */
69053 __I uint32_t SIG1_LOCKSTATUS; /**< Protection status of this address block., offset: 0xEC04 */
69054 __IO uint32_t SIG1_STATICCONTROL; /**< Global configuration shared by all evaluation windows., offset: 0xEC08 */
69055 __IO uint32_t SIG1_PANICCOLOR; /**< Overlay color for evaluation windows in panic mode., offset: 0xEC0C */
69056 __IO uint32_t SIG1_EVALCONTROL0; /**< Control settings for evaluation window 0., offset: 0xEC10 */
69057 __IO uint32_t SIG1_EVALUPPERLEFT0; /**< Upper left corner of evaluation window 0., offset: 0xEC14 */
69058 __IO uint32_t SIG1_EVALLOWERRIGHT0; /**< Lower right corner of evaluation window 0., offset: 0xEC18 */
69059 __IO uint32_t SIG1_SIGCRCREDREF0; /**< Reference signature of red channel for evaluation window 0., offset: 0xEC1C */
69060 __IO uint32_t SIG1_SIGCRCGREENREF0; /**< Reference signature of green channel for evaluation window 0., offset: 0xEC20 */
69061 __IO uint32_t SIG1_SIGCRCBLUEREF0; /**< Reference signature of blue channel for evaluation window 0., offset: 0xEC24 */
69062 __I uint32_t SIG1_SIGCRCRED0; /**< Measured signature of red channel for evaluation window 0., offset: 0xEC28 */
69063 __I uint32_t SIG1_SIGCRCGREEN0; /**< Measured signature of green channel for evaluation window 0., offset: 0xEC2C */
69064 __I uint32_t SIG1_SIGCRCBLUE0; /**< Measured signature of blue channel for evaluation window 0., offset: 0xEC30 */
69065 __IO uint32_t SIG1_EVALCONTROL1; /**< Control settings for evaluation window 1., offset: 0xEC34 */
69066 __IO uint32_t SIG1_EVALUPPERLEFT1; /**< Upper left corner of evaluation window 1., offset: 0xEC38 */
69067 __IO uint32_t SIG1_EVALLOWERRIGHT1; /**< Lower right corner of evaluation window 1., offset: 0xEC3C */
69068 __IO uint32_t SIG1_SIGCRCREDREF1; /**< Reference signature of red channel for evaluation window 1., offset: 0xEC40 */
69069 __IO uint32_t SIG1_SIGCRCGREENREF1; /**< Reference signature of green channel for evaluation window 1., offset: 0xEC44 */
69070 __IO uint32_t SIG1_SIGCRCBLUEREF1; /**< Reference signature of blue channel for evaluation window 1., offset: 0xEC48 */
69071 __I uint32_t SIG1_SIGCRCRED1; /**< Measured signature of red channel for evaluation window 1., offset: 0xEC4C */
69072 __I uint32_t SIG1_SIGCRCGREEN1; /**< Measured signature of green channel for evaluation window 1., offset: 0xEC50 */
69073 __I uint32_t SIG1_SIGCRCBLUE1; /**< Measured signature of blue channel for evaluation window 1., offset: 0xEC54 */
69074 __IO uint32_t SIG1_EVALCONTROL2; /**< Control settings for evaluation window 2., offset: 0xEC58 */
69075 __IO uint32_t SIG1_EVALUPPERLEFT2; /**< Upper left corner of evaluation window 2., offset: 0xEC5C */
69076 __IO uint32_t SIG1_EVALLOWERRIGHT2; /**< Lower right corner of evaluation window 2., offset: 0xEC60 */
69077 __IO uint32_t SIG1_SIGCRCREDREF2; /**< Reference signature of red channel for evaluation window 2., offset: 0xEC64 */
69078 __IO uint32_t SIG1_SIGCRCGREENREF2; /**< Reference signature of green channel for evaluation window 2., offset: 0xEC68 */
69079 __IO uint32_t SIG1_SIGCRCBLUEREF2; /**< Reference signature of blue channel for evaluation window 2., offset: 0xEC6C */
69080 __I uint32_t SIG1_SIGCRCRED2; /**< Measured signature of red channel for evaluation window 2., offset: 0xEC70 */
69081 __I uint32_t SIG1_SIGCRCGREEN2; /**< Measured signature of green channel for evaluation window 2., offset: 0xEC74 */
69082 __I uint32_t SIG1_SIGCRCBLUE2; /**< Measured signature of blue channel for evaluation window 2., offset: 0xEC78 */
69083 __IO uint32_t SIG1_EVALCONTROL3; /**< Control settings for evaluation window 3., offset: 0xEC7C */
69084 __IO uint32_t SIG1_EVALUPPERLEFT3; /**< Upper left corner of evaluation window 3., offset: 0xEC80 */
69085 __IO uint32_t SIG1_EVALLOWERRIGHT3; /**< Lower right corner of evaluation window 3., offset: 0xEC84 */
69086 __IO uint32_t SIG1_SIGCRCREDREF3; /**< Reference signature of red channel for evaluation window 3., offset: 0xEC88 */
69087 __IO uint32_t SIG1_SIGCRCGREENREF3; /**< Reference signature of green channel for evaluation window 3., offset: 0xEC8C */
69088 __IO uint32_t SIG1_SIGCRCBLUEREF3; /**< Reference signature of blue channel for evaluation window 3., offset: 0xEC90 */
69089 __I uint32_t SIG1_SIGCRCRED3; /**< Measured signature of red channel for evaluation window 3., offset: 0xEC94 */
69090 __I uint32_t SIG1_SIGCRCGREEN3; /**< Measured signature of green channel for evaluation window 3., offset: 0xEC98 */
69091 __I uint32_t SIG1_SIGCRCBLUE3; /**< Measured signature of blue channel for evaluation window 3., offset: 0xEC9C */
69092 __IO uint32_t SIG1_EVALCONTROL4; /**< Control settings for evaluation window 4., offset: 0xECA0 */
69093 __IO uint32_t SIG1_EVALUPPERLEFT4; /**< Upper left corner of evaluation window 4., offset: 0xECA4 */
69094 __IO uint32_t SIG1_EVALLOWERRIGHT4; /**< Lower right corner of evaluation window 4., offset: 0xECA8 */
69095 __IO uint32_t SIG1_SIGCRCREDREF4; /**< Reference signature of red channel for evaluation window 4., offset: 0xECAC */
69096 __IO uint32_t SIG1_SIGCRCGREENREF4; /**< Reference signature of green channel for evaluation window 4., offset: 0xECB0 */
69097 __IO uint32_t SIG1_SIGCRCBLUEREF4; /**< Reference signature of blue channel for evaluation window 4., offset: 0xECB4 */
69098 __I uint32_t SIG1_SIGCRCRED4; /**< Measured signature of red channel for evaluation window 4., offset: 0xECB8 */
69099 __I uint32_t SIG1_SIGCRCGREEN4; /**< Measured signature of green channel for evaluation window 4., offset: 0xECBC */
69100 __I uint32_t SIG1_SIGCRCBLUE4; /**< Measured signature of blue channel for evaluation window 4., offset: 0xECC0 */
69101 __IO uint32_t SIG1_EVALCONTROL5; /**< Control settings for evaluation window 5., offset: 0xECC4 */
69102 __IO uint32_t SIG1_EVALUPPERLEFT5; /**< Upper left corner of evaluation window 5., offset: 0xECC8 */
69103 __IO uint32_t SIG1_EVALLOWERRIGHT5; /**< Lower right corner of evaluation window 5., offset: 0xECCC */
69104 __IO uint32_t SIG1_SIGCRCREDREF5; /**< Reference signature of red channel for evaluation window 5., offset: 0xECD0 */
69105 __IO uint32_t SIG1_SIGCRCGREENREF5; /**< Reference signature of green channel for evaluation window 5., offset: 0xECD4 */
69106 __IO uint32_t SIG1_SIGCRCBLUEREF5; /**< Reference signature of blue channel for evaluation window 5., offset: 0xECD8 */
69107 __I uint32_t SIG1_SIGCRCRED5; /**< Measured signature of red channel for evaluation window 5., offset: 0xECDC */
69108 __I uint32_t SIG1_SIGCRCGREEN5; /**< Measured signature of green channel for evaluation window 5., offset: 0xECE0 */
69109 __I uint32_t SIG1_SIGCRCBLUE5; /**< Measured signature of blue channel for evaluation window 5., offset: 0xECE4 */
69110 __IO uint32_t SIG1_EVALCONTROL6; /**< Control settings for evaluation window 6., offset: 0xECE8 */
69111 __IO uint32_t SIG1_EVALUPPERLEFT6; /**< Upper left corner of evaluation window 6., offset: 0xECEC */
69112 __IO uint32_t SIG1_EVALLOWERRIGHT6; /**< Lower right corner of evaluation window 6., offset: 0xECF0 */
69113 __IO uint32_t SIG1_SIGCRCREDREF6; /**< Reference signature of red channel for evaluation window 6., offset: 0xECF4 */
69114 __IO uint32_t SIG1_SIGCRCGREENREF6; /**< Reference signature of green channel for evaluation window 6., offset: 0xECF8 */
69115 __IO uint32_t SIG1_SIGCRCBLUEREF6; /**< Reference signature of blue channel for evaluation window 6., offset: 0xECFC */
69116 __I uint32_t SIG1_SIGCRCRED6; /**< Measured signature of red channel for evaluation window 6., offset: 0xED00 */
69117 __I uint32_t SIG1_SIGCRCGREEN6; /**< Measured signature of green channel for evaluation window 6., offset: 0xED04 */
69118 __I uint32_t SIG1_SIGCRCBLUE6; /**< Measured signature of blue channel for evaluation window 6., offset: 0xED08 */
69119 __IO uint32_t SIG1_EVALCONTROL7; /**< Control settings for evaluation window 7., offset: 0xED0C */
69120 __IO uint32_t SIG1_EVALUPPERLEFT7; /**< Upper left corner of evaluation window 7., offset: 0xED10 */
69121 __IO uint32_t SIG1_EVALLOWERRIGHT7; /**< Lower right corner of evaluation window 7., offset: 0xED14 */
69122 __IO uint32_t SIG1_SIGCRCREDREF7; /**< Reference signature of red channel for evaluation window 7., offset: 0xED18 */
69123 __IO uint32_t SIG1_SIGCRCGREENREF7; /**< Reference signature of green channel for evaluation window 7., offset: 0xED1C */
69124 __IO uint32_t SIG1_SIGCRCBLUEREF7; /**< Reference signature of blue channel for evaluation window 7., offset: 0xED20 */
69125 __I uint32_t SIG1_SIGCRCRED7; /**< Measured signature of red channel for evaluation window 7., offset: 0xED24 */
69126 __I uint32_t SIG1_SIGCRCGREEN7; /**< Measured signature of green channel for evaluation window 7., offset: 0xED28 */
69127 __I uint32_t SIG1_SIGCRCBLUE7; /**< Measured signature of blue channel for evaluation window 7., offset: 0xED2C */
69128 __I uint32_t SIG1_SHADOWLOAD; /**< Shadow load control register., offset: 0xED30 */
69129 __IO uint32_t SIG1_CONTINUOUSMODE; /**< Signature operation mode control., offset: 0xED34 */
69130 __O uint32_t SIG1_SOFTWAREKICK; /**< Signature measurement trigger., offset: 0xED38 */
69131 __I uint32_t SIG1_STATUS; /**< Module status., offset: 0xED3C */
69132 uint8_t RESERVED_95[704];
69133 __IO uint32_t CONTROL; /**< Measurement Control Register, offset: 0xF000 */
69134 __IO uint32_t TIMER; /**< Timer Register, offset: 0xF004 */
69135 __IO uint32_t MEASUREMENTTIMECONTROL; /**< Timer Control Register, offset: 0xF008 */
69136 __I uint32_t SW_TAG; /**< Software Tag Register, offset: 0xF00C */
69137 __I uint32_t MEASUREMENTTIME; /**< Measurement Time Register, offset: 0xF010 */
69138 __I uint32_t GLOBAL_COUNTER; /**< Global Counter Register, offset: 0xF014 */
69139 __IO uint32_t MU00_SWITCH; /**< Measurement Unit 0 Source Select Register, offset: 0xF018 */
69140 __I uint32_t MU00_DATA_COUNTER; /**< Measurement Unit 0 Data Cycle Counter, offset: 0xF01C */
69141 __I uint32_t MU00_BUSY_COUNTER; /**< Measurement Unit 0 Busy Cycle Counter, offset: 0xF020 */
69142 __I uint32_t MU00_TRANSFER_COUNTER; /**< Measurement Unit 0 Transfer Counter, offset: 0xF024 */
69143 __I uint32_t MU00_ADDRBUSY_COUNTER; /**< Measurement Unit 0 Address Busy Cycle Counter, offset: 0xF028 */
69144 __I uint32_t MU00_LATENCY_COUNTER; /**< Measurement Unit 0 Latency Counter, offset: 0xF02C */
69145 __IO uint32_t MU01_SWITCH; /**< Measurement Unit 1 Source Select Register, offset: 0xF030 */
69146 __I uint32_t MU01_DATA_COUNTER; /**< Measurement Unit 1 Data Cycle Counter, offset: 0xF034 */
69147 __I uint32_t MU01_BUSY_COUNTER; /**< Measurement Unit 1 Busy Cycle Counter, offset: 0xF038 */
69148 __I uint32_t MU01_TRANSFER_COUNTER; /**< Measurement Unit 1 Transfer Counter, offset: 0xF03C */
69149 __I uint32_t MU01_ADDRBUSY_COUNTER; /**< Measurement Unit 1 Address Busy Cycle Counter, offset: 0xF040 */
69150 __I uint32_t MU01_LATENCY_COUNTER; /**< Measurement Unit 1 Latency Counter, offset: 0xF044 */
69151 __IO uint32_t MU02_SWITCH; /**< Measurement Unit 2 Source Select Register, offset: 0xF048 */
69152 __I uint32_t MU02_DATA_COUNTER; /**< Measurement Unit 2 Data Cycle Counter, offset: 0xF04C */
69153 __I uint32_t MU02_BUSY_COUNTER; /**< Measurement Unit 2 Busy Cycle Counter, offset: 0xF050 */
69154 __I uint32_t MU02_TRANSFER_COUNTER; /**< Measurement Unit 2 Transfer Counter, offset: 0xF054 */
69155 __I uint32_t MU02_ADDRBUSY_COUNTER; /**< Measurement Unit 2 Address Busy Cycle Counter, offset: 0xF058 */
69156 __I uint32_t MU02_LATENCY_COUNTER; /**< Measurement Unit 2 Latency Counter, offset: 0xF05C */
69157 __IO uint32_t MU03_SWITCH; /**< Measurement Unit 3 Source Select Register, offset: 0xF060 */
69158 __I uint32_t MU03_DATA_COUNTER; /**< Measurement Unit 3 Data Cycle Counter, offset: 0xF064 */
69159 __I uint32_t MU03_BUSY_COUNTER; /**< Measurement Unit 3 Busy Cycle Counter, offset: 0xF068 */
69160 __I uint32_t MU03_TRANSFER_COUNTER; /**< Measurement Unit 3 Transfer Counter, offset: 0xF06C */
69161 __I uint32_t MU03_ADDRBUSY_COUNTER; /**< Measurement Unit 3 Address Busy Cycle Counter, offset: 0xF070 */
69162 __I uint32_t MU03_LATENCY_COUNTER; /**< Measurement Unit 3 Latency Counter, offset: 0xF074 */
69163 __IO uint32_t MU04_SWITCH; /**< Measurement Unit 4 Source Select Register, offset: 0xF078 */
69164 __I uint32_t MU04_DATA_COUNTER; /**< Measurement Unit 4 Data Cycle Counter, offset: 0xF07C */
69165 __I uint32_t MU04_BUSY_COUNTER; /**< Measurement Unit 4 Busy Cycle Counter, offset: 0xF080 */
69166 __I uint32_t MU04_TRANSFER_COUNTER; /**< Measurement Unit 4 Transfer Counter, offset: 0xF084 */
69167 __I uint32_t MU04_ADDRBUSY_COUNTER; /**< Measurement Unit 4 Address Busy Cycle Counter, offset: 0xF088 */
69168 __I uint32_t MU04_LATENCY_COUNTER; /**< Measurement Unit 4 Latency Counter, offset: 0xF08C */
69169 uint8_t RESERVED_96[55152];
69170 __I uint32_t TCON1_SSQCNTS; /**< The 64 Sequencer Position Definitions registers define the X/Y scan positions of the sequencers, hold their output value and assign the sequencer to an odd/even field, offset: 0x1C800 */
69171} IRIS_MVPL_Type;
69172
69173/* ----------------------------------------------------------------------------
69174 -- IRIS_MVPL Register Masks
69175 ---------------------------------------------------------------------------- */
69176
69177/*!
69178 * @addtogroup IRIS_MVPL_Register_Masks IRIS_MVPL Register Masks
69179 * @{
69180 */
69181
69182/*! @name IPIDENTIFIER - IP Identifier for this SEERIS derivate. */
69183/*! @{ */
69184#define IRIS_MVPL_IPIDENTIFIER_DesignDeliveryID_MASK (0xF0U)
69185#define IRIS_MVPL_IPIDENTIFIER_DesignDeliveryID_SHIFT (4U)
69186/*! DesignDeliveryID - Design delivery ID (increased with each official delivery when maturity keeps the same).
69187 */
69188#define IRIS_MVPL_IPIDENTIFIER_DesignDeliveryID(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_IPIDENTIFIER_DesignDeliveryID_SHIFT)) & IRIS_MVPL_IPIDENTIFIER_DesignDeliveryID_MASK)
69189#define IRIS_MVPL_IPIDENTIFIER_DesignMaturityLevel_MASK (0xF00U)
69190#define IRIS_MVPL_IPIDENTIFIER_DesignMaturityLevel_SHIFT (8U)
69191/*! DesignMaturityLevel - Design maturity level (corresponds to status at time of IP delivery, Fujitsu internal development stages)
69192 * 0b0001..Pre feasibility study.
69193 * 0b0010..Feasibility study.
69194 * 0b0011..Functionality complete.
69195 * 0b0100..Verification complete.
69196 */
69197#define IRIS_MVPL_IPIDENTIFIER_DesignMaturityLevel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_IPIDENTIFIER_DesignMaturityLevel_SHIFT)) & IRIS_MVPL_IPIDENTIFIER_DesignMaturityLevel_MASK)
69198#define IRIS_MVPL_IPIDENTIFIER_IPEvolution_MASK (0xF000U)
69199#define IRIS_MVPL_IPIDENTIFIER_IPEvolution_SHIFT (12U)
69200/*! IPEvolution - IP evolution (increased for functional spec changes only when feature set keeps the same)
69201 */
69202#define IRIS_MVPL_IPIDENTIFIER_IPEvolution(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_IPIDENTIFIER_IPEvolution_SHIFT)) & IRIS_MVPL_IPIDENTIFIER_IPEvolution_MASK)
69203#define IRIS_MVPL_IPIDENTIFIER_IPFeatureSet_MASK (0xF0000U)
69204#define IRIS_MVPL_IPIDENTIFIER_IPFeatureSet_SHIFT (16U)
69205/*! IPFeatureSet - IP feature set (complexity of implemented features, e.g. availability of re-sampling filter etc)
69206 * 0b0001..Minimal functionality (Eco).
69207 * 0b0010..Reduced functionality (Light).
69208 * 0b0100..Advanced functionality (Plus).
69209 * 0b0101..Extensive functionality (eXtensive).
69210 */
69211#define IRIS_MVPL_IPIDENTIFIER_IPFeatureSet(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_IPIDENTIFIER_IPFeatureSet_SHIFT)) & IRIS_MVPL_IPIDENTIFIER_IPFeatureSet_MASK)
69212#define IRIS_MVPL_IPIDENTIFIER_IPApplication_MASK (0xF00000U)
69213#define IRIS_MVPL_IPIDENTIFIER_IPApplication_SHIFT (20U)
69214/*! IPApplication - IP application
69215 * 0b0001..Blit Engine only.
69216 * 0b0010..Blit Engine and Display Controller.
69217 * 0b0011..Display Controller only (with direct capture).
69218 * 0b0100..Blit Engine, Display Controller (with direct capture), Capture Controller (buffered capture) and Drawing Engine.
69219 * 0b0101..Display Controller only.
69220 */
69221#define IRIS_MVPL_IPIDENTIFIER_IPApplication(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_IPIDENTIFIER_IPApplication_SHIFT)) & IRIS_MVPL_IPIDENTIFIER_IPApplication_MASK)
69222#define IRIS_MVPL_IPIDENTIFIER_IPConfiguration_MASK (0xF000000U)
69223#define IRIS_MVPL_IPIDENTIFIER_IPConfiguration_SHIFT (24U)
69224/*! IPConfiguration - Ip configuration
69225 * 0b0001..Graphics core only (Module).
69226 * 0b0010..Subsystem including a graphics core (System).
69227 */
69228#define IRIS_MVPL_IPIDENTIFIER_IPConfiguration(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_IPIDENTIFIER_IPConfiguration_SHIFT)) & IRIS_MVPL_IPIDENTIFIER_IPConfiguration_MASK)
69229#define IRIS_MVPL_IPIDENTIFIER_IPFamily_MASK (0xF0000000U)
69230#define IRIS_MVPL_IPIDENTIFIER_IPFamily_SHIFT (28U)
69231/*! IPFamily - IP family
69232 * 0b0000..Iris building block generation 2010.
69233 * 0b0001..Iris building block generation 2012.
69234 * 0b0010..Iris building block generation 2013.
69235 */
69236#define IRIS_MVPL_IPIDENTIFIER_IPFamily(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_IPIDENTIFIER_IPFamily_SHIFT)) & IRIS_MVPL_IPIDENTIFIER_IPFamily_MASK)
69237/*! @} */
69238
69239/*! @name COMCTRL_LOCKUNLOCK - Register to change the protection status of this address block. */
69240/*! @{ */
69241#define IRIS_MVPL_COMCTRL_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
69242#define IRIS_MVPL_COMCTRL_LOCKUNLOCK_LockUnlock_SHIFT (0U)
69243/*! LockUnlock - The protection status is changed by writing one of the following key values to this field:
69244 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
69245 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
69246 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
69247 * 0b10110101111000100100011001101110..Disables privilege protection.
69248 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
69249 */
69250#define IRIS_MVPL_COMCTRL_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_COMCTRL_LOCKUNLOCK_LockUnlock_MASK)
69251/*! @} */
69252
69253/*! @name COMCTRL_LOCKSTATUS - Protection status of this address block. */
69254/*! @{ */
69255#define IRIS_MVPL_COMCTRL_LOCKSTATUS_LockStatus_MASK (0x1U)
69256#define IRIS_MVPL_COMCTRL_LOCKSTATUS_LockStatus_SHIFT (0U)
69257/*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
69258 */
69259#define IRIS_MVPL_COMCTRL_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_COMCTRL_LOCKSTATUS_LockStatus_MASK)
69260#define IRIS_MVPL_COMCTRL_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
69261#define IRIS_MVPL_COMCTRL_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
69262/*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
69263 */
69264#define IRIS_MVPL_COMCTRL_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_COMCTRL_LOCKSTATUS_PrivilegeStatus_MASK)
69265#define IRIS_MVPL_COMCTRL_LOCKSTATUS_FreezeStatus_MASK (0x100U)
69266#define IRIS_MVPL_COMCTRL_LOCKSTATUS_FreezeStatus_SHIFT (8U)
69267/*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
69268 */
69269#define IRIS_MVPL_COMCTRL_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_COMCTRL_LOCKSTATUS_FreezeStatus_MASK)
69270/*! @} */
69271
69272/*! @name COMCTRL_USERINTERRUPTMASK0 - Interrupt UserMask register 0 */
69273/*! @{ */
69274#define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK0_UserInterruptMask0_MASK (0xFFFFFFFFU)
69275#define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK0_UserInterruptMask0_SHIFT (0U)
69276/*! UserInterruptMask0 - UserMask vector for interrupts. Only interrupts that are set in this vector
69277 * can be accessed by the unprotected UserInterruptEnable0, UserInterruptPreset0 and
69278 * UserInterruptClear0 registers as well.
69279 */
69280#define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK0_UserInterruptMask0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_USERINTERRUPTMASK0_UserInterruptMask0_SHIFT)) & IRIS_MVPL_COMCTRL_USERINTERRUPTMASK0_UserInterruptMask0_MASK)
69281/*! @} */
69282
69283/*! @name COMCTRL_USERINTERRUPTMASK1 - Interrupt UserMask register 1 */
69284/*! @{ */
69285#define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK1_UserInterruptMask1_MASK (0x1FFFFU)
69286#define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK1_UserInterruptMask1_SHIFT (0U)
69287/*! UserInterruptMask1 - UserMask vector for interrupts. Only interrupts that are set in this vector
69288 * can be accessed by the unprotected UserInterruptEnable1, UserInterruptPreset1 and
69289 * UserInterruptClear1 registers as well.
69290 */
69291#define IRIS_MVPL_COMCTRL_USERINTERRUPTMASK1_UserInterruptMask1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_USERINTERRUPTMASK1_UserInterruptMask1_SHIFT)) & IRIS_MVPL_COMCTRL_USERINTERRUPTMASK1_UserInterruptMask1_MASK)
69292/*! @} */
69293
69294/*! @name COMCTRL_INTERRUPTENABLE0 - Interrupt Enable register 0 */
69295/*! @{ */
69296#define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_MASK (0xFFFFFFFFU)
69297#define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_SHIFT (0U)
69298/*! InterruptEnable0 - Enable vector for interrupts. InterruptEnable0[n] is mapped to Interrupt (n +
69299 * 0) (1=enable, 0=disable). Please note that this enable vector does not affect the
69300 * InterruptStatus register fields and the cmdseq sysstatus vector. It only affects the interrupt outputs
69301 * going to higher hierarchies than SEERIS.
69302 */
69303#define IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTENABLE0_InterruptEnable0_MASK)
69304/*! @} */
69305
69306/*! @name COMCTRL_INTERRUPTENABLE1 - Interrupt Enable register 1 */
69307/*! @{ */
69308#define IRIS_MVPL_COMCTRL_INTERRUPTENABLE1_InterruptEnable1_MASK (0x1FFFFU)
69309#define IRIS_MVPL_COMCTRL_INTERRUPTENABLE1_InterruptEnable1_SHIFT (0U)
69310/*! InterruptEnable1 - Enable vector for interrupts. InterruptEnable1[n] is mapped to Interrupt (n +
69311 * 32) (1=enable, 0=disable). Please note that this enable vector does not affect the
69312 * InterruptStatus register fields and the cmdseq sysstatus vector. It only affects the interrupt outputs
69313 * going to higher hierarchies than SEERIS.
69314 */
69315#define IRIS_MVPL_COMCTRL_INTERRUPTENABLE1_InterruptEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTENABLE1_InterruptEnable1_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTENABLE1_InterruptEnable1_MASK)
69316/*! @} */
69317
69318/*! @name COMCTRL_INTERRUPTPRESET0 - Interrupt Preset register 0 */
69319/*! @{ */
69320#define IRIS_MVPL_COMCTRL_INTERRUPTPRESET0_InterruptPreset0_MASK (0xFFFFFFFFU)
69321#define IRIS_MVPL_COMCTRL_INTERRUPTPRESET0_InterruptPreset0_SHIFT (0U)
69322/*! InterruptPreset0 - Preset vector for interrupts. InterruptPreset0[n] is mapped to Interrupt (n +
69323 * 0) (write 1 to bit [n] to set interrupt (n + 0)).
69324 */
69325#define IRIS_MVPL_COMCTRL_INTERRUPTPRESET0_InterruptPreset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTPRESET0_InterruptPreset0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTPRESET0_InterruptPreset0_MASK)
69326/*! @} */
69327
69328/*! @name COMCTRL_INTERRUPTPRESET1 - Interrupt Preset register 1 */
69329/*! @{ */
69330#define IRIS_MVPL_COMCTRL_INTERRUPTPRESET1_InterruptPreset1_MASK (0x1FFFFU)
69331#define IRIS_MVPL_COMCTRL_INTERRUPTPRESET1_InterruptPreset1_SHIFT (0U)
69332/*! InterruptPreset1 - Preset vector for interrupts. InterruptPreset1[n] is mapped to Interrupt (n +
69333 * 32) (write 1 to bit [n] to set interrupt (n + 32)).
69334 */
69335#define IRIS_MVPL_COMCTRL_INTERRUPTPRESET1_InterruptPreset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTPRESET1_InterruptPreset1_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTPRESET1_InterruptPreset1_MASK)
69336/*! @} */
69337
69338/*! @name COMCTRL_INTERRUPTCLEAR0 - Interrupt Clear register 0 */
69339/*! @{ */
69340#define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR0_InterruptClear0_MASK (0xFFFFFFFFU)
69341#define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR0_InterruptClear0_SHIFT (0U)
69342/*! InterruptClear0 - Clear vector for interrupts. InterruptClear0[n] is mapped to Interrupt (n + 0)
69343 * (write 1 to bit [n] to clear interrupt (n + 0)).
69344 */
69345#define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR0_InterruptClear0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTCLEAR0_InterruptClear0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTCLEAR0_InterruptClear0_MASK)
69346/*! @} */
69347
69348/*! @name COMCTRL_INTERRUPTCLEAR1 - Interrupt Clear register 1 */
69349/*! @{ */
69350#define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR1_InterruptClear1_MASK (0x1FFFFU)
69351#define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR1_InterruptClear1_SHIFT (0U)
69352/*! InterruptClear1 - Clear vector for interrupts. InterruptClear1[n] is mapped to Interrupt (n +
69353 * 32) (write 1 to bit [n] to clear interrupt (n + 32)).
69354 */
69355#define IRIS_MVPL_COMCTRL_INTERRUPTCLEAR1_InterruptClear1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTCLEAR1_InterruptClear1_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTCLEAR1_InterruptClear1_MASK)
69356/*! @} */
69357
69358/*! @name COMCTRL_INTERRUPTSTATUS0 - Interrupt Status register 0 */
69359/*! @{ */
69360#define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS0_InterruptStatus0_MASK (0xFFFFFFFFU)
69361#define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS0_InterruptStatus0_SHIFT (0U)
69362/*! InterruptStatus0 - Status vector of interrupts. InterruptStatus0[n] is mapped to Interrupt (n + 0) (1=set, 0=not set).
69363 */
69364#define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS0_InterruptStatus0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTSTATUS0_InterruptStatus0_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTSTATUS0_InterruptStatus0_MASK)
69365/*! @} */
69366
69367/*! @name COMCTRL_INTERRUPTSTATUS1 - Interrupt Status register 1 */
69368/*! @{ */
69369#define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS1_InterruptStatus1_MASK (0x1FFFFU)
69370#define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS1_InterruptStatus1_SHIFT (0U)
69371/*! InterruptStatus1 - Status vector of interrupts. InterruptStatus1[n] is mapped to Interrupt (n + 32) (1=set, 0=not set).
69372 */
69373#define IRIS_MVPL_COMCTRL_INTERRUPTSTATUS1_InterruptStatus1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COMCTRL_INTERRUPTSTATUS1_InterruptStatus1_SHIFT)) & IRIS_MVPL_COMCTRL_INTERRUPTSTATUS1_InterruptStatus1_MASK)
69374/*! @} */
69375
69376/*! @name USERINTERRUPTENABLE0 - Interrupt Enable register 0 for user mode access */
69377/*! @{ */
69378#define IRIS_MVPL_USERINTERRUPTENABLE0_UserInterruptEnable0_MASK (0xFFFFFFFFU)
69379#define IRIS_MVPL_USERINTERRUPTENABLE0_UserInterruptEnable0_SHIFT (0U)
69380/*! UserInterruptEnable0 - Same as InterruptEnable0, except only effective for bits which are set in UserInterruptMask0.
69381 */
69382#define IRIS_MVPL_USERINTERRUPTENABLE0_UserInterruptEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_USERINTERRUPTENABLE0_UserInterruptEnable0_SHIFT)) & IRIS_MVPL_USERINTERRUPTENABLE0_UserInterruptEnable0_MASK)
69383/*! @} */
69384
69385/*! @name USERINTERRUPTENABLE1 - Interrupt Enable register 1 for user mode access */
69386/*! @{ */
69387#define IRIS_MVPL_USERINTERRUPTENABLE1_UserInterruptEnable1_MASK (0x1FFFFU)
69388#define IRIS_MVPL_USERINTERRUPTENABLE1_UserInterruptEnable1_SHIFT (0U)
69389/*! UserInterruptEnable1 - Same as InterruptEnable1, except only effective for bits which are set in UserInterruptMask1.
69390 */
69391#define IRIS_MVPL_USERINTERRUPTENABLE1_UserInterruptEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_USERINTERRUPTENABLE1_UserInterruptEnable1_SHIFT)) & IRIS_MVPL_USERINTERRUPTENABLE1_UserInterruptEnable1_MASK)
69392/*! @} */
69393
69394/*! @name USERINTERRUPTPRESET0 - Interrupt Preset register 0 */
69395/*! @{ */
69396#define IRIS_MVPL_USERINTERRUPTPRESET0_UserInterruptPreset0_MASK (0xFFFFFFFFU)
69397#define IRIS_MVPL_USERINTERRUPTPRESET0_UserInterruptPreset0_SHIFT (0U)
69398/*! UserInterruptPreset0 - Same as InterruptPreset0, except only effective for bits which are set in UserInterruptMask0.
69399 */
69400#define IRIS_MVPL_USERINTERRUPTPRESET0_UserInterruptPreset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_USERINTERRUPTPRESET0_UserInterruptPreset0_SHIFT)) & IRIS_MVPL_USERINTERRUPTPRESET0_UserInterruptPreset0_MASK)
69401/*! @} */
69402
69403/*! @name USERINTERRUPTPRESET1 - Interrupt Preset register 1 */
69404/*! @{ */
69405#define IRIS_MVPL_USERINTERRUPTPRESET1_UserInterruptPreset1_MASK (0x1FFFFU)
69406#define IRIS_MVPL_USERINTERRUPTPRESET1_UserInterruptPreset1_SHIFT (0U)
69407/*! UserInterruptPreset1 - Same as InterruptPreset1, except only effective for bits which are set in UserInterruptMask1.
69408 */
69409#define IRIS_MVPL_USERINTERRUPTPRESET1_UserInterruptPreset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_USERINTERRUPTPRESET1_UserInterruptPreset1_SHIFT)) & IRIS_MVPL_USERINTERRUPTPRESET1_UserInterruptPreset1_MASK)
69410/*! @} */
69411
69412/*! @name USERINTERRUPTCLEAR0 - Interrupt Clear register 0 */
69413/*! @{ */
69414#define IRIS_MVPL_USERINTERRUPTCLEAR0_UserInterruptClear0_MASK (0xFFFFFFFFU)
69415#define IRIS_MVPL_USERINTERRUPTCLEAR0_UserInterruptClear0_SHIFT (0U)
69416/*! UserInterruptClear0 - Same as InterruptClear0, except only effective for bits which are set in UserInterruptMask0.
69417 */
69418#define IRIS_MVPL_USERINTERRUPTCLEAR0_UserInterruptClear0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_USERINTERRUPTCLEAR0_UserInterruptClear0_SHIFT)) & IRIS_MVPL_USERINTERRUPTCLEAR0_UserInterruptClear0_MASK)
69419/*! @} */
69420
69421/*! @name USERINTERRUPTCLEAR1 - Interrupt Clear register 1 */
69422/*! @{ */
69423#define IRIS_MVPL_USERINTERRUPTCLEAR1_UserInterruptClear1_MASK (0x1FFFFU)
69424#define IRIS_MVPL_USERINTERRUPTCLEAR1_UserInterruptClear1_SHIFT (0U)
69425/*! UserInterruptClear1 - Same as InterruptClear1, except only effective for bits which are set in UserInterruptMask1.
69426 */
69427#define IRIS_MVPL_USERINTERRUPTCLEAR1_UserInterruptClear1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_USERINTERRUPTCLEAR1_UserInterruptClear1_SHIFT)) & IRIS_MVPL_USERINTERRUPTCLEAR1_UserInterruptClear1_MASK)
69428/*! @} */
69429
69430/*! @name USERINTERRUPTSTATUS0 - Interrupt Status register 0 */
69431/*! @{ */
69432#define IRIS_MVPL_USERINTERRUPTSTATUS0_UserInterruptStatus0_MASK (0xFFFFFFFFU)
69433#define IRIS_MVPL_USERINTERRUPTSTATUS0_UserInterruptStatus0_SHIFT (0U)
69434/*! UserInterruptStatus0 - Same as InterruptStatus0.
69435 */
69436#define IRIS_MVPL_USERINTERRUPTSTATUS0_UserInterruptStatus0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_USERINTERRUPTSTATUS0_UserInterruptStatus0_SHIFT)) & IRIS_MVPL_USERINTERRUPTSTATUS0_UserInterruptStatus0_MASK)
69437/*! @} */
69438
69439/*! @name USERINTERRUPTSTATUS1 - Interrupt Status register 1 */
69440/*! @{ */
69441#define IRIS_MVPL_USERINTERRUPTSTATUS1_UserInterruptStatus1_MASK (0x1FFFFU)
69442#define IRIS_MVPL_USERINTERRUPTSTATUS1_UserInterruptStatus1_SHIFT (0U)
69443/*! UserInterruptStatus1 - Same as InterruptStatus1.
69444 */
69445#define IRIS_MVPL_USERINTERRUPTSTATUS1_UserInterruptStatus1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_USERINTERRUPTSTATUS1_UserInterruptStatus1_SHIFT)) & IRIS_MVPL_USERINTERRUPTSTATUS1_UserInterruptStatus1_MASK)
69446/*! @} */
69447
69448/*! @name GENERALPURPOSE - General purpose config memory */
69449/*! @{ */
69450#define IRIS_MVPL_GENERALPURPOSE_GeneralPurpose_MASK (0xFFFFFFFFU)
69451#define IRIS_MVPL_GENERALPURPOSE_GeneralPurpose_SHIFT (0U)
69452/*! GeneralPurpose - General purpose config memory entry, does not have any function.
69453 */
69454#define IRIS_MVPL_GENERALPURPOSE_GeneralPurpose(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_GENERALPURPOSE_GeneralPurpose_SHIFT)) & IRIS_MVPL_GENERALPURPOSE_GeneralPurpose_MASK)
69455/*! @} */
69456
69457/*! @name CMDSEQ_HIF - Command input buffer */
69458/*! @{ */
69459#define IRIS_MVPL_CMDSEQ_HIF_CommandFIFO_MASK (0xFFFFFFFFU)
69460#define IRIS_MVPL_CMDSEQ_HIF_CommandFIFO_SHIFT (0U)
69461/*! CommandFIFO - Writing an instruction to this field will add it to the command FIFO. Reading always returns 0.
69462 */
69463#define IRIS_MVPL_CMDSEQ_HIF_CommandFIFO(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_HIF_CommandFIFO_SHIFT)) & IRIS_MVPL_CMDSEQ_HIF_CommandFIFO_MASK)
69464/*! @} */
69465
69466/*! @name CMDSEQ_LOCKUNLOCKHIF - Register to change the protection status of this address block. */
69467/*! @{ */
69468#define IRIS_MVPL_CMDSEQ_LOCKUNLOCKHIF_LockUnlockHIF_MASK (0xFFFFFFFFU)
69469#define IRIS_MVPL_CMDSEQ_LOCKUNLOCKHIF_LockUnlockHIF_SHIFT (0U)
69470/*! LockUnlockHIF - The protection status is changed by writing one of the following key values to this field:
69471 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
69472 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
69473 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
69474 * 0b10110101111000100100011001101110..Disables privilege protection.
69475 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
69476 */
69477#define IRIS_MVPL_CMDSEQ_LOCKUNLOCKHIF_LockUnlockHIF(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKUNLOCKHIF_LockUnlockHIF_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKUNLOCKHIF_LockUnlockHIF_MASK)
69478/*! @} */
69479
69480/*! @name CMDSEQ_LOCKSTATUSHIF - Protection status of this address block. */
69481/*! @{ */
69482#define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_LockStatusHIF_MASK (0x1U)
69483#define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_LockStatusHIF_SHIFT (0U)
69484/*! LockStatusHIF - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
69485 */
69486#define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_LockStatusHIF(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_LockStatusHIF_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_LockStatusHIF_MASK)
69487#define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_PrivilegeStatusHIF_MASK (0x10U)
69488#define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_PrivilegeStatusHIF_SHIFT (4U)
69489/*! PrivilegeStatusHIF - Current status of privilege protection: 0 = inactive , 1 = active.
69490 */
69491#define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_PrivilegeStatusHIF(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_PrivilegeStatusHIF_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_PrivilegeStatusHIF_MASK)
69492#define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_FreezeStatusHIF_MASK (0x100U)
69493#define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_FreezeStatusHIF_SHIFT (8U)
69494/*! FreezeStatusHIF - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
69495 */
69496#define IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_FreezeStatusHIF(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_FreezeStatusHIF_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKSTATUSHIF_FreezeStatusHIF_MASK)
69497/*! @} */
69498
69499/*! @name CMDSEQ_LOCKUNLOCK - Register to change the protection status of this address block. */
69500/*! @{ */
69501#define IRIS_MVPL_CMDSEQ_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
69502#define IRIS_MVPL_CMDSEQ_LOCKUNLOCK_LockUnlock_SHIFT (0U)
69503/*! LockUnlock - The protection status is changed by writing one of the following key values to this field:
69504 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
69505 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
69506 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
69507 * 0b10110101111000100100011001101110..Disables privilege protection.
69508 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
69509 */
69510#define IRIS_MVPL_CMDSEQ_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKUNLOCK_LockUnlock_MASK)
69511/*! @} */
69512
69513/*! @name CMDSEQ_LOCKSTATUS - Protection status of this address block. */
69514/*! @{ */
69515#define IRIS_MVPL_CMDSEQ_LOCKSTATUS_LockStatus_MASK (0x1U)
69516#define IRIS_MVPL_CMDSEQ_LOCKSTATUS_LockStatus_SHIFT (0U)
69517/*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
69518 */
69519#define IRIS_MVPL_CMDSEQ_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKSTATUS_LockStatus_MASK)
69520#define IRIS_MVPL_CMDSEQ_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
69521#define IRIS_MVPL_CMDSEQ_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
69522/*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
69523 */
69524#define IRIS_MVPL_CMDSEQ_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKSTATUS_PrivilegeStatus_MASK)
69525#define IRIS_MVPL_CMDSEQ_LOCKSTATUS_FreezeStatus_MASK (0x100U)
69526#define IRIS_MVPL_CMDSEQ_LOCKSTATUS_FreezeStatus_SHIFT (8U)
69527/*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
69528 */
69529#define IRIS_MVPL_CMDSEQ_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_CMDSEQ_LOCKSTATUS_FreezeStatus_MASK)
69530/*! @} */
69531
69532/*! @name CMDSEQ_BUFFERADDRESS - Command buffer address register */
69533/*! @{ */
69534#define IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Local_MASK (0x1U)
69535#define IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Local_SHIFT (0U)
69536/*! Local - When enabled, a local buffer is used as command FIFO instead of the external one, which
69537 * is specified by 'Addr' and 'Size' fields. It has a size of 4 instructions only.
69538 */
69539#define IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Local(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Local_SHIFT)) & IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Local_MASK)
69540#define IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Addr_MASK (0xFFFFFFE0U)
69541#define IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Addr_SHIFT (5U)
69542/*! Addr - Command buffer base address. Must be 32 byte aligned.
69543 */
69544#define IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Addr(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Addr_SHIFT)) & IRIS_MVPL_CMDSEQ_BUFFERADDRESS_Addr_MASK)
69545/*! @} */
69546
69547/*! @name CMDSEQ_BUFFERSIZE - Command buffer size register */
69548/*! @{ */
69549#define IRIS_MVPL_CMDSEQ_BUFFERSIZE_Size_MASK (0xFFF8U)
69550#define IRIS_MVPL_CMDSEQ_BUFFERSIZE_Size_SHIFT (3U)
69551/*! Size - Size of command buffer in multiples of 32 byte; a value of 0 is equal to 0x10000
69552 */
69553#define IRIS_MVPL_CMDSEQ_BUFFERSIZE_Size(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_BUFFERSIZE_Size_SHIFT)) & IRIS_MVPL_CMDSEQ_BUFFERSIZE_Size_MASK)
69554/*! @} */
69555
69556/*! @name CMDSEQ_WATERMARKCONTROL - Watermark Control register */
69557/*! @{ */
69558#define IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_LowWM_MASK (0xFFFFU)
69559#define IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_LowWM_SHIFT (0U)
69560/*! LowWM - Low water mark
69561 */
69562#define IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_LowWM(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_LowWM_SHIFT)) & IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_LowWM_MASK)
69563#define IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_HighWM_MASK (0xFFFF0000U)
69564#define IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_HighWM_SHIFT (16U)
69565/*! HighWM - High water mark
69566 */
69567#define IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_HighWM(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_HighWM_SHIFT)) & IRIS_MVPL_CMDSEQ_WATERMARKCONTROL_HighWM_MASK)
69568/*! @} */
69569
69570/*! @name CMDSEQ_CONTROL - Control register */
69571/*! @{ */
69572#define IRIS_MVPL_CMDSEQ_CONTROL_ClrAxiw_MASK (0x1U)
69573#define IRIS_MVPL_CMDSEQ_CONTROL_ClrAxiw_SHIFT (0U)
69574/*! ClrAxiw - Clear axiwrite controller by writing a 1
69575 */
69576#define IRIS_MVPL_CMDSEQ_CONTROL_ClrAxiw(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_CONTROL_ClrAxiw_SHIFT)) & IRIS_MVPL_CMDSEQ_CONTROL_ClrAxiw_MASK)
69577#define IRIS_MVPL_CMDSEQ_CONTROL_ClrRbuf_MASK (0x4U)
69578#define IRIS_MVPL_CMDSEQ_CONTROL_ClrRbuf_SHIFT (2U)
69579/*! ClrRbuf - Clear read prefetch buffer by writing a 1
69580 */
69581#define IRIS_MVPL_CMDSEQ_CONTROL_ClrRbuf(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_CONTROL_ClrRbuf_SHIFT)) & IRIS_MVPL_CMDSEQ_CONTROL_ClrRbuf_MASK)
69582#define IRIS_MVPL_CMDSEQ_CONTROL_ClrCmdBuf_MASK (0x8U)
69583#define IRIS_MVPL_CMDSEQ_CONTROL_ClrCmdBuf_SHIFT (3U)
69584/*! ClrCmdBuf - Clear command buffer by writing a 1
69585 */
69586#define IRIS_MVPL_CMDSEQ_CONTROL_ClrCmdBuf(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_CONTROL_ClrCmdBuf_SHIFT)) & IRIS_MVPL_CMDSEQ_CONTROL_ClrCmdBuf_MASK)
69587#define IRIS_MVPL_CMDSEQ_CONTROL_Clear_MASK (0x80000000U)
69588#define IRIS_MVPL_CMDSEQ_CONTROL_Clear_SHIFT (31U)
69589/*! Clear - Clear internal data pipelines and core state by writing a 1
69590 */
69591#define IRIS_MVPL_CMDSEQ_CONTROL_Clear(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_CONTROL_Clear_SHIFT)) & IRIS_MVPL_CMDSEQ_CONTROL_Clear_MASK)
69592/*! @} */
69593
69594/*! @name CMDSEQ_STATUS - Status register */
69595/*! @{ */
69596#define IRIS_MVPL_CMDSEQ_STATUS_FIFOSpace_MASK (0x1FFFFU)
69597#define IRIS_MVPL_CMDSEQ_STATUS_FIFOSpace_SHIFT (0U)
69598/*! FIFOSpace - Available space in command FIFO in number of 32-bit words.
69599 */
69600#define IRIS_MVPL_CMDSEQ_STATUS_FIFOSpace(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_FIFOSpace_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_FIFOSpace_MASK)
69601#define IRIS_MVPL_CMDSEQ_STATUS_FIFOEmpty_MASK (0x1000000U)
69602#define IRIS_MVPL_CMDSEQ_STATUS_FIFOEmpty_SHIFT (24U)
69603/*! FIFOEmpty - Command FIFO empty flag
69604 */
69605#define IRIS_MVPL_CMDSEQ_STATUS_FIFOEmpty(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_FIFOEmpty_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_FIFOEmpty_MASK)
69606#define IRIS_MVPL_CMDSEQ_STATUS_FIFOFull_MASK (0x2000000U)
69607#define IRIS_MVPL_CMDSEQ_STATUS_FIFOFull_SHIFT (25U)
69608/*! FIFOFull - Command FIFO full flag
69609 */
69610#define IRIS_MVPL_CMDSEQ_STATUS_FIFOFull(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_FIFOFull_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_FIFOFull_MASK)
69611#define IRIS_MVPL_CMDSEQ_STATUS_FIFOWMState_MASK (0x4000000U)
69612#define IRIS_MVPL_CMDSEQ_STATUS_FIFOWMState_SHIFT (26U)
69613/*! FIFOWMState - Water mark state
69614 */
69615#define IRIS_MVPL_CMDSEQ_STATUS_FIFOWMState(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_FIFOWMState_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_FIFOWMState_MASK)
69616#define IRIS_MVPL_CMDSEQ_STATUS_Watchdog_MASK (0x8000000U)
69617#define IRIS_MVPL_CMDSEQ_STATUS_Watchdog_SHIFT (27U)
69618/*! Watchdog - Watchdog expired
69619 */
69620#define IRIS_MVPL_CMDSEQ_STATUS_Watchdog(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_Watchdog_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_Watchdog_MASK)
69621#define IRIS_MVPL_CMDSEQ_STATUS_ReadBusy_MASK (0x10000000U)
69622#define IRIS_MVPL_CMDSEQ_STATUS_ReadBusy_SHIFT (28U)
69623/*! ReadBusy - If this is 1 then the command sequencer AXI read path is not idle.
69624 */
69625#define IRIS_MVPL_CMDSEQ_STATUS_ReadBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_ReadBusy_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_ReadBusy_MASK)
69626#define IRIS_MVPL_CMDSEQ_STATUS_WriteBusy_MASK (0x20000000U)
69627#define IRIS_MVPL_CMDSEQ_STATUS_WriteBusy_SHIFT (29U)
69628/*! WriteBusy - If this is 1 then the command sequencer write paths are not idle.
69629 */
69630#define IRIS_MVPL_CMDSEQ_STATUS_WriteBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_WriteBusy_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_WriteBusy_MASK)
69631#define IRIS_MVPL_CMDSEQ_STATUS_Idle_MASK (0x40000000U)
69632#define IRIS_MVPL_CMDSEQ_STATUS_Idle_SHIFT (30U)
69633/*! Idle - Command sequencer is in IDLE state
69634 */
69635#define IRIS_MVPL_CMDSEQ_STATUS_Idle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_Idle_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_Idle_MASK)
69636#define IRIS_MVPL_CMDSEQ_STATUS_ErrorHalt_MASK (0x80000000U)
69637#define IRIS_MVPL_CMDSEQ_STATUS_ErrorHalt_SHIFT (31U)
69638/*! ErrorHalt - Execution stopped after illegal instruction
69639 */
69640#define IRIS_MVPL_CMDSEQ_STATUS_ErrorHalt(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_STATUS_ErrorHalt_SHIFT)) & IRIS_MVPL_CMDSEQ_STATUS_ErrorHalt_MASK)
69641/*! @} */
69642
69643/*! @name CMDSEQ_PREFETCHWINDOWSTART - PrefetchWindowStart register */
69644/*! @{ */
69645#define IRIS_MVPL_CMDSEQ_PREFETCHWINDOWSTART_PWStart_MASK (0xFFFFFFFCU)
69646#define IRIS_MVPL_CMDSEQ_PREFETCHWINDOWSTART_PWStart_SHIFT (2U)
69647/*! PWStart - Start address of prefetch window
69648 */
69649#define IRIS_MVPL_CMDSEQ_PREFETCHWINDOWSTART_PWStart(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_PREFETCHWINDOWSTART_PWStart_SHIFT)) & IRIS_MVPL_CMDSEQ_PREFETCHWINDOWSTART_PWStart_MASK)
69650/*! @} */
69651
69652/*! @name CMDSEQ_PREFETCHWINDOWEND - PrefetchWindowEnd register */
69653/*! @{ */
69654#define IRIS_MVPL_CMDSEQ_PREFETCHWINDOWEND_PWEnd_MASK (0xFFFFFFFCU)
69655#define IRIS_MVPL_CMDSEQ_PREFETCHWINDOWEND_PWEnd_SHIFT (2U)
69656/*! PWEnd - End address of prefetch window
69657 */
69658#define IRIS_MVPL_CMDSEQ_PREFETCHWINDOWEND_PWEnd(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CMDSEQ_PREFETCHWINDOWEND_PWEnd_SHIFT)) & IRIS_MVPL_CMDSEQ_PREFETCHWINDOWEND_PWEnd_MASK)
69659/*! @} */
69660
69661/*! @name SAFETYLOCKUNLOCK - Register to change the protection status of this address block. */
69662/*! @{ */
69663#define IRIS_MVPL_SAFETYLOCKUNLOCK_SafetyLockUnlock_MASK (0xFFFFFFFFU)
69664#define IRIS_MVPL_SAFETYLOCKUNLOCK_SafetyLockUnlock_SHIFT (0U)
69665/*! SafetyLockUnlock - The protection status is changed by writing one of the following key values to this field:
69666 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
69667 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
69668 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
69669 * 0b10110101111000100100011001101110..Disables privilege protection.
69670 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
69671 */
69672#define IRIS_MVPL_SAFETYLOCKUNLOCK_SafetyLockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SAFETYLOCKUNLOCK_SafetyLockUnlock_SHIFT)) & IRIS_MVPL_SAFETYLOCKUNLOCK_SafetyLockUnlock_MASK)
69673/*! @} */
69674
69675/*! @name SAFETYLOCKSTATUS - Protection status of this address block. */
69676/*! @{ */
69677#define IRIS_MVPL_SAFETYLOCKSTATUS_SafetyLockStatus_MASK (0x1U)
69678#define IRIS_MVPL_SAFETYLOCKSTATUS_SafetyLockStatus_SHIFT (0U)
69679/*! SafetyLockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
69680 */
69681#define IRIS_MVPL_SAFETYLOCKSTATUS_SafetyLockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SAFETYLOCKSTATUS_SafetyLockStatus_SHIFT)) & IRIS_MVPL_SAFETYLOCKSTATUS_SafetyLockStatus_MASK)
69682#define IRIS_MVPL_SAFETYLOCKSTATUS_SafetyPrivilegeStatus_MASK (0x10U)
69683#define IRIS_MVPL_SAFETYLOCKSTATUS_SafetyPrivilegeStatus_SHIFT (4U)
69684/*! SafetyPrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
69685 */
69686#define IRIS_MVPL_SAFETYLOCKSTATUS_SafetyPrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SAFETYLOCKSTATUS_SafetyPrivilegeStatus_SHIFT)) & IRIS_MVPL_SAFETYLOCKSTATUS_SafetyPrivilegeStatus_MASK)
69687#define IRIS_MVPL_SAFETYLOCKSTATUS_SafetyFreezeStatus_MASK (0x100U)
69688#define IRIS_MVPL_SAFETYLOCKSTATUS_SafetyFreezeStatus_SHIFT (8U)
69689/*! SafetyFreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
69690 */
69691#define IRIS_MVPL_SAFETYLOCKSTATUS_SafetyFreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_SAFETYLOCKSTATUS_SafetyFreezeStatus_SHIFT)) & IRIS_MVPL_SAFETYLOCKSTATUS_SafetyFreezeStatus_MASK)
69692/*! @} */
69693
69694/*! @name STORE9_SAFETYMASK - Safety mask for store9 */
69695/*! @{ */
69696#define IRIS_MVPL_STORE9_SAFETYMASK_store9_SafetyMask_MASK (0x7FFFFFFFU)
69697#define IRIS_MVPL_STORE9_SAFETYMASK_store9_SafetyMask_SHIFT (0U)
69698/*! store9_SafetyMask - Each bit in this field describes whether the corresponding processing unit
69699 * is allowed to be configured in a path leading to this endpoint (store9). 1 = allowed, 0 =
69700 * prohibited.
69701 */
69702#define IRIS_MVPL_STORE9_SAFETYMASK_store9_SafetyMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_SAFETYMASK_store9_SafetyMask_SHIFT)) & IRIS_MVPL_STORE9_SAFETYMASK_store9_SafetyMask_MASK)
69703/*! @} */
69704
69705/*! @name EXTDST0_SAFETYMASK - Safety mask for extdst0 */
69706/*! @{ */
69707#define IRIS_MVPL_EXTDST0_SAFETYMASK_extdst0_SafetyMask_MASK (0x7FFFFFFFU)
69708#define IRIS_MVPL_EXTDST0_SAFETYMASK_extdst0_SafetyMask_SHIFT (0U)
69709/*! extdst0_SafetyMask - Each bit in this field describes whether the corresponding processing unit
69710 * is allowed to be configured in a path leading to this endpoint (extdst0). 1 = allowed, 0 =
69711 * prohibited.
69712 */
69713#define IRIS_MVPL_EXTDST0_SAFETYMASK_extdst0_SafetyMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_SAFETYMASK_extdst0_SafetyMask_SHIFT)) & IRIS_MVPL_EXTDST0_SAFETYMASK_extdst0_SafetyMask_MASK)
69714/*! @} */
69715
69716/*! @name EXTDST4_SAFETYMASK - Safety mask for extdst4 */
69717/*! @{ */
69718#define IRIS_MVPL_EXTDST4_SAFETYMASK_extdst4_SafetyMask_MASK (0x7FFFFFFFU)
69719#define IRIS_MVPL_EXTDST4_SAFETYMASK_extdst4_SafetyMask_SHIFT (0U)
69720/*! extdst4_SafetyMask - Each bit in this field describes whether the corresponding processing unit
69721 * is allowed to be configured in a path leading to this endpoint (extdst4). 1 = allowed, 0 =
69722 * prohibited.
69723 */
69724#define IRIS_MVPL_EXTDST4_SAFETYMASK_extdst4_SafetyMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST4_SAFETYMASK_extdst4_SafetyMask_SHIFT)) & IRIS_MVPL_EXTDST4_SAFETYMASK_extdst4_SafetyMask_MASK)
69725/*! @} */
69726
69727/*! @name EXTDST1_SAFETYMASK - Safety mask for extdst1 */
69728/*! @{ */
69729#define IRIS_MVPL_EXTDST1_SAFETYMASK_extdst1_SafetyMask_MASK (0x7FFFFFFFU)
69730#define IRIS_MVPL_EXTDST1_SAFETYMASK_extdst1_SafetyMask_SHIFT (0U)
69731/*! extdst1_SafetyMask - Each bit in this field describes whether the corresponding processing unit
69732 * is allowed to be configured in a path leading to this endpoint (extdst1). 1 = allowed, 0 =
69733 * prohibited.
69734 */
69735#define IRIS_MVPL_EXTDST1_SAFETYMASK_extdst1_SafetyMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_SAFETYMASK_extdst1_SafetyMask_SHIFT)) & IRIS_MVPL_EXTDST1_SAFETYMASK_extdst1_SafetyMask_MASK)
69736/*! @} */
69737
69738/*! @name EXTDST5_SAFETYMASK - Safety mask for extdst5 */
69739/*! @{ */
69740#define IRIS_MVPL_EXTDST5_SAFETYMASK_extdst5_SafetyMask_MASK (0x7FFFFFFFU)
69741#define IRIS_MVPL_EXTDST5_SAFETYMASK_extdst5_SafetyMask_SHIFT (0U)
69742/*! extdst5_SafetyMask - Each bit in this field describes whether the corresponding processing unit
69743 * is allowed to be configured in a path leading to this endpoint (extdst5). 1 = allowed, 0 =
69744 * prohibited.
69745 */
69746#define IRIS_MVPL_EXTDST5_SAFETYMASK_extdst5_SafetyMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_SAFETYMASK_extdst5_SafetyMask_SHIFT)) & IRIS_MVPL_EXTDST5_SAFETYMASK_extdst5_SafetyMask_MASK)
69747/*! @} */
69748
69749/*! @name FETCHDECODE32_LOCKUNLOCK - Register to change the protection status of this address block. */
69750/*! @{ */
69751#define IRIS_MVPL_FETCHDECODE32_LOCKUNLOCK_fetchdecode_LockUnlock_MASK (0xFFFFFFFFU)
69752#define IRIS_MVPL_FETCHDECODE32_LOCKUNLOCK_fetchdecode_LockUnlock_SHIFT (0U)
69753/*! fetchdecode_LockUnlock - The protection status is changed by writing one of the following key values to this field:
69754 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
69755 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
69756 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
69757 * 0b10110101111000100100011001101110..Disables privilege protection.
69758 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
69759 */
69760#define IRIS_MVPL_FETCHDECODE32_LOCKUNLOCK_fetchdecode_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE32_LOCKUNLOCK_fetchdecode_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHDECODE32_LOCKUNLOCK_fetchdecode_LockUnlock_MASK)
69761/*! @} */
69762
69763/*! @name FETCHDECODE32_LOCKSTATUS - Protection status of this address block. */
69764/*! @{ */
69765#define IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode_LockStatus_MASK (0x1U)
69766#define IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode_LockStatus_SHIFT (0U)
69767/*! fetchdecode_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
69768 */
69769#define IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode_LockStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode_LockStatus_MASK)
69770#define IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode9_PrivilegeStatus_MASK (0x10U)
69771#define IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode9_PrivilegeStatus_SHIFT (4U)
69772/*! fetchdecode9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
69773 */
69774#define IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode9_PrivilegeStatus_MASK)
69775#define IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode9_FreezeStatus_MASK (0x100U)
69776#define IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode9_FreezeStatus_SHIFT (8U)
69777/*! fetchdecode9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
69778 */
69779#define IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode9_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE32_LOCKSTATUS_fetchdecode9_FreezeStatus_MASK)
69780/*! @} */
69781
69782/*! @name FETCHDECODE_DYNAMIC - Dynamic pixel engine configuration for fetchdecode9 */
69783/*! @{ */
69784#define IRIS_MVPL_FETCHDECODE_DYNAMIC_fetchdecode9_src_sel_MASK (0x3FU)
69785#define IRIS_MVPL_FETCHDECODE_DYNAMIC_fetchdecode9_src_sel_SHIFT (0U)
69786/*! fetchdecode9_src_sel - Selection of the source for the src input of the fetchdecode9 module
69787 * 0b000000..Unit fetchdecode9 input port src is disabled
69788 * 0b000010..Unit fetchdecode9 input port src is connected to output of unit fetchwarp9
69789 * 0b000011..Unit fetchdecode9 input port src is connected to output of unit fetcheco9
69790 */
69791#define IRIS_MVPL_FETCHDECODE_DYNAMIC_fetchdecode9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DYNAMIC_fetchdecode9_src_sel_SHIFT)) & IRIS_MVPL_FETCHDECODE_DYNAMIC_fetchdecode9_src_sel_MASK)
69792/*! @} */
69793
69794/*! @name FETCHDECODE_STATUS - Status information for pixel engine configuration of fetchdecode9 */
69795/*! @{ */
69796#define IRIS_MVPL_FETCHDECODE_STATUS_fetchdecode9_sel_MASK (0x70000U)
69797#define IRIS_MVPL_FETCHDECODE_STATUS_fetchdecode9_sel_SHIFT (16U)
69798/*! fetchdecode9_sel - Status of the connection of the fetchdecode9 module
69799 * 0b000..fetchdecode9 module is not used
69800 * 0b001..fetchdecode9 module is used from store9 processing path
69801 * 0b010..fetchdecode9 module is used from extdst0 processing path
69802 * 0b011..fetchdecode9 module is used from extdst4 processing path
69803 * 0b100..fetchdecode9 module is used from extdst1 processing path
69804 * 0b101..fetchdecode9 module is used from extdst5 processing path
69805 */
69806#define IRIS_MVPL_FETCHDECODE_STATUS_fetchdecode9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_STATUS_fetchdecode9_sel_SHIFT)) & IRIS_MVPL_FETCHDECODE_STATUS_fetchdecode9_sel_MASK)
69807/*! @} */
69808
69809/*! @name FETCHWARP64_LOCKUNLOCK - Register to change the protection status of this address block. */
69810/*! @{ */
69811#define IRIS_MVPL_FETCHWARP64_LOCKUNLOCK_fetchwarp_LockUnlock_MASK (0xFFFFFFFFU)
69812#define IRIS_MVPL_FETCHWARP64_LOCKUNLOCK_fetchwarp_LockUnlock_SHIFT (0U)
69813/*! fetchwarp_LockUnlock - The protection status is changed by writing one of the following key values to this field:
69814 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
69815 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
69816 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
69817 * 0b10110101111000100100011001101110..Disables privilege protection.
69818 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
69819 */
69820#define IRIS_MVPL_FETCHWARP64_LOCKUNLOCK_fetchwarp_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP64_LOCKUNLOCK_fetchwarp_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHWARP64_LOCKUNLOCK_fetchwarp_LockUnlock_MASK)
69821/*! @} */
69822
69823/*! @name FETCHWARP64_LOCKSTATUS - Protection status of this address block. */
69824/*! @{ */
69825#define IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp_LockStatus_MASK (0x1U)
69826#define IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp_LockStatus_SHIFT (0U)
69827/*! fetchwarp_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
69828 */
69829#define IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp_LockStatus_SHIFT)) & IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp_LockStatus_MASK)
69830#define IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp9_PrivilegeStatus_MASK (0x10U)
69831#define IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp9_PrivilegeStatus_SHIFT (4U)
69832/*! fetchwarp9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
69833 */
69834#define IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp9_PrivilegeStatus_MASK)
69835#define IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp9_FreezeStatus_MASK (0x100U)
69836#define IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp9_FreezeStatus_SHIFT (8U)
69837/*! fetchwarp9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
69838 */
69839#define IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp9_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHWARP64_LOCKSTATUS_fetchwarp9_FreezeStatus_MASK)
69840/*! @} */
69841
69842/*! @name FETCHWARP64_DYNAMIC - Dynamic pixel engine configuration for fetchwarp9 */
69843/*! @{ */
69844#define IRIS_MVPL_FETCHWARP64_DYNAMIC_fetchwarp9_src_sel_MASK (0x3FU)
69845#define IRIS_MVPL_FETCHWARP64_DYNAMIC_fetchwarp9_src_sel_SHIFT (0U)
69846/*! fetchwarp9_src_sel - Selection of the source for the src input of the fetchwarp9 module
69847 * 0b000000..Unit fetchwarp9 input port src is disabled
69848 * 0b000011..Unit fetchwarp9 input port src is connected to output of unit fetcheco9
69849 */
69850#define IRIS_MVPL_FETCHWARP64_DYNAMIC_fetchwarp9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP64_DYNAMIC_fetchwarp9_src_sel_SHIFT)) & IRIS_MVPL_FETCHWARP64_DYNAMIC_fetchwarp9_src_sel_MASK)
69851/*! @} */
69852
69853/*! @name FETCHWARP64_STATUS - Status information for pixel engine configuration of fetchwarp9 */
69854/*! @{ */
69855#define IRIS_MVPL_FETCHWARP64_STATUS_fetchwarp9_sel_MASK (0x70000U)
69856#define IRIS_MVPL_FETCHWARP64_STATUS_fetchwarp9_sel_SHIFT (16U)
69857/*! fetchwarp9_sel - Status of the connection of the fetchwarp9 module
69858 * 0b000..fetchwarp9 module is not used
69859 * 0b001..fetchwarp9 module is used from store9 processing path
69860 * 0b010..fetchwarp9 module is used from extdst0 processing path
69861 * 0b011..fetchwarp9 module is used from extdst4 processing path
69862 * 0b100..fetchwarp9 module is used from extdst1 processing path
69863 * 0b101..fetchwarp9 module is used from extdst5 processing path
69864 */
69865#define IRIS_MVPL_FETCHWARP64_STATUS_fetchwarp9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP64_STATUS_fetchwarp9_sel_SHIFT)) & IRIS_MVPL_FETCHWARP64_STATUS_fetchwarp9_sel_MASK)
69866/*! @} */
69867
69868/*! @name FETCHECO80_LOCKUNLOCK - Register to change the protection status of this address block. */
69869/*! @{ */
69870#define IRIS_MVPL_FETCHECO80_LOCKUNLOCK_fetcheco_LockUnlock_MASK (0xFFFFFFFFU)
69871#define IRIS_MVPL_FETCHECO80_LOCKUNLOCK_fetcheco_LockUnlock_SHIFT (0U)
69872/*! fetcheco_LockUnlock - The protection status is changed by writing one of the following key values to this field:
69873 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
69874 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
69875 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
69876 * 0b10110101111000100100011001101110..Disables privilege protection.
69877 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
69878 */
69879#define IRIS_MVPL_FETCHECO80_LOCKUNLOCK_fetcheco_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO80_LOCKUNLOCK_fetcheco_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHECO80_LOCKUNLOCK_fetcheco_LockUnlock_MASK)
69880/*! @} */
69881
69882/*! @name FETCHECO80_LOCKSTATUS - Protection status of this address block. */
69883/*! @{ */
69884#define IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco_LockStatus_MASK (0x1U)
69885#define IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco_LockStatus_SHIFT (0U)
69886/*! fetcheco_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
69887 */
69888#define IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco_LockStatus_SHIFT)) & IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco_LockStatus_MASK)
69889#define IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco9_PrivilegeStatus_MASK (0x10U)
69890#define IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco9_PrivilegeStatus_SHIFT (4U)
69891/*! fetcheco9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
69892 */
69893#define IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco9_PrivilegeStatus_MASK)
69894#define IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco9_FreezeStatus_MASK (0x100U)
69895#define IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco9_FreezeStatus_SHIFT (8U)
69896/*! fetcheco9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
69897 */
69898#define IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco9_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHECO80_LOCKSTATUS_fetcheco9_FreezeStatus_MASK)
69899/*! @} */
69900
69901/*! @name FETCHECO_STATUS - Status information for pixel engine configuration of fetcheco9 */
69902/*! @{ */
69903#define IRIS_MVPL_FETCHECO_STATUS_fetcheco9_sel_MASK (0x70000U)
69904#define IRIS_MVPL_FETCHECO_STATUS_fetcheco9_sel_SHIFT (16U)
69905/*! fetcheco9_sel - Status of the connection of the fetcheco9 module
69906 * 0b000..fetcheco9 module is not used
69907 * 0b001..fetcheco9 module is used from store9 processing path
69908 * 0b010..fetcheco9 module is used from extdst0 processing path
69909 * 0b011..fetcheco9 module is used from extdst4 processing path
69910 * 0b100..fetcheco9 module is used from extdst1 processing path
69911 * 0b101..fetcheco9 module is used from extdst5 processing path
69912 */
69913#define IRIS_MVPL_FETCHECO_STATUS_fetcheco9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO_STATUS_fetcheco9_sel_SHIFT)) & IRIS_MVPL_FETCHECO_STATUS_fetcheco9_sel_MASK)
69914/*! @} */
69915
69916/*! @name ROP_LOCKUNLOCK - Register to change the protection status of this address block. */
69917/*! @{ */
69918#define IRIS_MVPL_ROP_LOCKUNLOCK_rop_LockUnlock_MASK (0xFFFFFFFFU)
69919#define IRIS_MVPL_ROP_LOCKUNLOCK_rop_LockUnlock_SHIFT (0U)
69920/*! rop_LockUnlock - The protection status is changed by writing one of the following key values to this field:
69921 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
69922 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
69923 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
69924 * 0b10110101111000100100011001101110..Disables privilege protection.
69925 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
69926 */
69927#define IRIS_MVPL_ROP_LOCKUNLOCK_rop_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP_LOCKUNLOCK_rop_LockUnlock_SHIFT)) & IRIS_MVPL_ROP_LOCKUNLOCK_rop_LockUnlock_MASK)
69928/*! @} */
69929
69930/*! @name ROP_LOCKSTATUS - Protection status of this address block. */
69931/*! @{ */
69932#define IRIS_MVPL_ROP_LOCKSTATUS_rop_LockStatus_MASK (0x1U)
69933#define IRIS_MVPL_ROP_LOCKSTATUS_rop_LockStatus_SHIFT (0U)
69934/*! rop_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
69935 */
69936#define IRIS_MVPL_ROP_LOCKSTATUS_rop_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP_LOCKSTATUS_rop_LockStatus_SHIFT)) & IRIS_MVPL_ROP_LOCKSTATUS_rop_LockStatus_MASK)
69937#define IRIS_MVPL_ROP_LOCKSTATUS_rop9_PrivilegeStatus_MASK (0x10U)
69938#define IRIS_MVPL_ROP_LOCKSTATUS_rop9_PrivilegeStatus_SHIFT (4U)
69939/*! rop9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
69940 */
69941#define IRIS_MVPL_ROP_LOCKSTATUS_rop9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP_LOCKSTATUS_rop9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_ROP_LOCKSTATUS_rop9_PrivilegeStatus_MASK)
69942#define IRIS_MVPL_ROP_LOCKSTATUS_rop9_FreezeStatus_MASK (0x100U)
69943#define IRIS_MVPL_ROP_LOCKSTATUS_rop9_FreezeStatus_SHIFT (8U)
69944/*! rop9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
69945 */
69946#define IRIS_MVPL_ROP_LOCKSTATUS_rop9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP_LOCKSTATUS_rop9_FreezeStatus_SHIFT)) & IRIS_MVPL_ROP_LOCKSTATUS_rop9_FreezeStatus_MASK)
69947/*! @} */
69948
69949/*! @name ROP_DYNAMIC - Dynamic pixel engine configuration for rop9 */
69950/*! @{ */
69951#define IRIS_MVPL_ROP_DYNAMIC_rop9_prim_sel_MASK (0x3FU)
69952#define IRIS_MVPL_ROP_DYNAMIC_rop9_prim_sel_SHIFT (0U)
69953/*! rop9_prim_sel - Selection of the source for the prim input of the rop9 module
69954 * 0b000000..Unit rop9 input port prim is disabled
69955 * 0b000001..Unit rop9 input port prim is connected to output of unit fetchdecode9
69956 * 0b000010..Unit rop9 input port prim is connected to output of unit fetchwarp9
69957 */
69958#define IRIS_MVPL_ROP_DYNAMIC_rop9_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP_DYNAMIC_rop9_prim_sel_SHIFT)) & IRIS_MVPL_ROP_DYNAMIC_rop9_prim_sel_MASK)
69959#define IRIS_MVPL_ROP_DYNAMIC_rop9_sec_sel_MASK (0x3F00U)
69960#define IRIS_MVPL_ROP_DYNAMIC_rop9_sec_sel_SHIFT (8U)
69961/*! rop9_sec_sel - Selection of the source for the sec input of the rop9 module
69962 * 0b000000..Unit rop9 input port sec is disabled
69963 * 0b000011..Unit rop9 input port sec is connected to output of unit fetcheco9
69964 */
69965#define IRIS_MVPL_ROP_DYNAMIC_rop9_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP_DYNAMIC_rop9_sec_sel_SHIFT)) & IRIS_MVPL_ROP_DYNAMIC_rop9_sec_sel_MASK)
69966#define IRIS_MVPL_ROP_DYNAMIC_rop9_tert_sel_MASK (0x3F0000U)
69967#define IRIS_MVPL_ROP_DYNAMIC_rop9_tert_sel_SHIFT (16U)
69968/*! rop9_tert_sel - Selection of the source for the tert input of the rop9 module
69969 * 0b000000..Unit rop9 input port tert is disabled
69970 * 0b000001..Unit rop9 input port tert is connected to output of unit fetchdecode9
69971 * 0b000010..Unit rop9 input port tert is connected to output of unit fetchwarp9
69972 */
69973#define IRIS_MVPL_ROP_DYNAMIC_rop9_tert_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP_DYNAMIC_rop9_tert_sel_SHIFT)) & IRIS_MVPL_ROP_DYNAMIC_rop9_tert_sel_MASK)
69974#define IRIS_MVPL_ROP_DYNAMIC_rop9_clken_MASK (0x3000000U)
69975#define IRIS_MVPL_ROP_DYNAMIC_rop9_clken_SHIFT (24U)
69976/*! rop9_clken - Enable of rop9 clock (this setting has to be the same for all modules of one
69977 * processing pipeline). If a submodule is enabled and FULL is used, then the register
69978 * [endpoint_name]_clk must be set to 0x80.
69979 * 0b00..Clock for rop9 is disabled
69980 * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register)
69981 * 0b11..Clock for rop9 is without gating
69982 */
69983#define IRIS_MVPL_ROP_DYNAMIC_rop9_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP_DYNAMIC_rop9_clken_SHIFT)) & IRIS_MVPL_ROP_DYNAMIC_rop9_clken_MASK)
69984/*! @} */
69985
69986/*! @name ROP_STATUS - Status information for pixel engine configuration of rop9 */
69987/*! @{ */
69988#define IRIS_MVPL_ROP_STATUS_rop9_sel_MASK (0x70000U)
69989#define IRIS_MVPL_ROP_STATUS_rop9_sel_SHIFT (16U)
69990/*! rop9_sel - Status of the connection of the rop9 module
69991 * 0b000..rop9 module is not used
69992 * 0b001..rop9 module is used from store9 processing path
69993 * 0b010..rop9 module is used from extdst0 processing path
69994 * 0b011..rop9 module is used from extdst4 processing path
69995 * 0b100..rop9 module is used from extdst1 processing path
69996 * 0b101..rop9 module is used from extdst5 processing path
69997 */
69998#define IRIS_MVPL_ROP_STATUS_rop9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP_STATUS_rop9_sel_SHIFT)) & IRIS_MVPL_ROP_STATUS_rop9_sel_MASK)
69999/*! @} */
70000
70001/*! @name CLUT_LOCKUNLOCK - Register to change the protection status of this address block. */
70002/*! @{ */
70003#define IRIS_MVPL_CLUT_LOCKUNLOCK_clut_LockUnlock_MASK (0xFFFFFFFFU)
70004#define IRIS_MVPL_CLUT_LOCKUNLOCK_clut_LockUnlock_SHIFT (0U)
70005/*! clut_LockUnlock - The protection status is changed by writing one of the following key values to this field:
70006 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
70007 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
70008 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
70009 * 0b10110101111000100100011001101110..Disables privilege protection.
70010 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
70011 */
70012#define IRIS_MVPL_CLUT_LOCKUNLOCK_clut_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT_LOCKUNLOCK_clut_LockUnlock_SHIFT)) & IRIS_MVPL_CLUT_LOCKUNLOCK_clut_LockUnlock_MASK)
70013/*! @} */
70014
70015/*! @name CLUT_LOCKSTATUS - Protection status of this address block. */
70016/*! @{ */
70017#define IRIS_MVPL_CLUT_LOCKSTATUS_clut_LockStatus_MASK (0x1U)
70018#define IRIS_MVPL_CLUT_LOCKSTATUS_clut_LockStatus_SHIFT (0U)
70019/*! clut_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
70020 */
70021#define IRIS_MVPL_CLUT_LOCKSTATUS_clut_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT_LOCKSTATUS_clut_LockStatus_SHIFT)) & IRIS_MVPL_CLUT_LOCKSTATUS_clut_LockStatus_MASK)
70022#define IRIS_MVPL_CLUT_LOCKSTATUS_clut9_PrivilegeStatus_MASK (0x10U)
70023#define IRIS_MVPL_CLUT_LOCKSTATUS_clut9_PrivilegeStatus_SHIFT (4U)
70024/*! clut9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
70025 */
70026#define IRIS_MVPL_CLUT_LOCKSTATUS_clut9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT_LOCKSTATUS_clut9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CLUT_LOCKSTATUS_clut9_PrivilegeStatus_MASK)
70027#define IRIS_MVPL_CLUT_LOCKSTATUS_clut9_FreezeStatus_MASK (0x100U)
70028#define IRIS_MVPL_CLUT_LOCKSTATUS_clut9_FreezeStatus_SHIFT (8U)
70029/*! clut9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
70030 */
70031#define IRIS_MVPL_CLUT_LOCKSTATUS_clut9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT_LOCKSTATUS_clut9_FreezeStatus_SHIFT)) & IRIS_MVPL_CLUT_LOCKSTATUS_clut9_FreezeStatus_MASK)
70032/*! @} */
70033
70034/*! @name CLUT_DYNAMIC - Dynamic pixel engine configuration for clut9 */
70035/*! @{ */
70036#define IRIS_MVPL_CLUT_DYNAMIC_clut9_src_sel_MASK (0x3FU)
70037#define IRIS_MVPL_CLUT_DYNAMIC_clut9_src_sel_SHIFT (0U)
70038/*! clut9_src_sel - Selection of the source for the src input of the clut9 module
70039 * 0b000000..Unit clut9 input port src is disabled
70040 * 0b001010..Unit clut9 input port src is connected to output of unit blitblend9
70041 * 0b000100..Unit clut9 input port src is connected to output of unit rop9
70042 */
70043#define IRIS_MVPL_CLUT_DYNAMIC_clut9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT_DYNAMIC_clut9_src_sel_SHIFT)) & IRIS_MVPL_CLUT_DYNAMIC_clut9_src_sel_MASK)
70044/*! @} */
70045
70046/*! @name CLUT_STATUS - Status information for pixel engine configuration of clut9 */
70047/*! @{ */
70048#define IRIS_MVPL_CLUT_STATUS_clut9_sel_MASK (0x70000U)
70049#define IRIS_MVPL_CLUT_STATUS_clut9_sel_SHIFT (16U)
70050/*! clut9_sel - Status of the connection of the clut9 module
70051 * 0b000..clut9 module is not used
70052 * 0b001..clut9 module is used from store9 processing path
70053 * 0b010..clut9 module is used from extdst0 processing path
70054 * 0b011..clut9 module is used from extdst4 processing path
70055 * 0b100..clut9 module is used from extdst1 processing path
70056 * 0b101..clut9 module is used from extdst5 processing path
70057 */
70058#define IRIS_MVPL_CLUT_STATUS_clut9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT_STATUS_clut9_sel_SHIFT)) & IRIS_MVPL_CLUT_STATUS_clut9_sel_MASK)
70059/*! @} */
70060
70061/*! @name MATRIX160_LOCKUNLOCK - Register to change the protection status of this address block. */
70062/*! @{ */
70063#define IRIS_MVPL_MATRIX160_LOCKUNLOCK_matrix_LockUnlock_MASK (0xFFFFFFFFU)
70064#define IRIS_MVPL_MATRIX160_LOCKUNLOCK_matrix_LockUnlock_SHIFT (0U)
70065/*! matrix_LockUnlock - The protection status is changed by writing one of the following key values to this field:
70066 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
70067 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
70068 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
70069 * 0b10110101111000100100011001101110..Disables privilege protection.
70070 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
70071 */
70072#define IRIS_MVPL_MATRIX160_LOCKUNLOCK_matrix_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX160_LOCKUNLOCK_matrix_LockUnlock_SHIFT)) & IRIS_MVPL_MATRIX160_LOCKUNLOCK_matrix_LockUnlock_MASK)
70073/*! @} */
70074
70075/*! @name MATRIX160_LOCKSTATUS - Protection status of this address block. */
70076/*! @{ */
70077#define IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix_LockStatus_MASK (0x1U)
70078#define IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix_LockStatus_SHIFT (0U)
70079/*! matrix_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
70080 */
70081#define IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix_LockStatus_SHIFT)) & IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix_LockStatus_MASK)
70082#define IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix9_PrivilegeStatus_MASK (0x10U)
70083#define IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix9_PrivilegeStatus_SHIFT (4U)
70084/*! matrix9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
70085 */
70086#define IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix9_PrivilegeStatus_MASK)
70087#define IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix9_FreezeStatus_MASK (0x100U)
70088#define IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix9_FreezeStatus_SHIFT (8U)
70089/*! matrix9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
70090 */
70091#define IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix9_FreezeStatus_SHIFT)) & IRIS_MVPL_MATRIX160_LOCKSTATUS_matrix9_FreezeStatus_MASK)
70092/*! @} */
70093
70094/*! @name MATRIX_DYNAMIC - Dynamic pixel engine configuration for matrix9 */
70095/*! @{ */
70096#define IRIS_MVPL_MATRIX_DYNAMIC_matrix9_src_sel_MASK (0x3FU)
70097#define IRIS_MVPL_MATRIX_DYNAMIC_matrix9_src_sel_SHIFT (0U)
70098/*! matrix9_src_sel - Selection of the source for the src input of the matrix9 module
70099 * 0b000000..Unit matrix9 input port src is disabled
70100 * 0b001010..Unit matrix9 input port src is connected to output of unit blitblend9
70101 * 0b000100..Unit matrix9 input port src is connected to output of unit rop9
70102 * 0b000101..Unit matrix9 input port src is connected to output of unit clut9
70103 */
70104#define IRIS_MVPL_MATRIX_DYNAMIC_matrix9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX_DYNAMIC_matrix9_src_sel_SHIFT)) & IRIS_MVPL_MATRIX_DYNAMIC_matrix9_src_sel_MASK)
70105#define IRIS_MVPL_MATRIX_DYNAMIC_matrix9_clken_MASK (0x3000000U)
70106#define IRIS_MVPL_MATRIX_DYNAMIC_matrix9_clken_SHIFT (24U)
70107/*! matrix9_clken - Enable of matrix9 clock (this setting has to be the same for all modules of one
70108 * processing pipeline). If a submodule is enabled and FULL is used, then the register
70109 * [endpoint_name]_clk must be set to 0x80.
70110 * 0b00..Clock for matrix9 is disabled
70111 * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register)
70112 * 0b11..Clock for matrix9 is without gating
70113 */
70114#define IRIS_MVPL_MATRIX_DYNAMIC_matrix9_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX_DYNAMIC_matrix9_clken_SHIFT)) & IRIS_MVPL_MATRIX_DYNAMIC_matrix9_clken_MASK)
70115/*! @} */
70116
70117/*! @name MATRIX_STATUS - Status information for pixel engine configuration of matrix9 */
70118/*! @{ */
70119#define IRIS_MVPL_MATRIX_STATUS_matrix9_sel_MASK (0x70000U)
70120#define IRIS_MVPL_MATRIX_STATUS_matrix9_sel_SHIFT (16U)
70121/*! matrix9_sel - Status of the connection of the matrix9 module
70122 * 0b000..matrix9 module is not used
70123 * 0b001..matrix9 module is used from store9 processing path
70124 * 0b010..matrix9 module is used from extdst0 processing path
70125 * 0b011..matrix9 module is used from extdst4 processing path
70126 * 0b100..matrix9 module is used from extdst1 processing path
70127 * 0b101..matrix9 module is used from extdst5 processing path
70128 */
70129#define IRIS_MVPL_MATRIX_STATUS_matrix9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX_STATUS_matrix9_sel_SHIFT)) & IRIS_MVPL_MATRIX_STATUS_matrix9_sel_MASK)
70130/*! @} */
70131
70132/*! @name HSCALER192_LOCKUNLOCK - Register to change the protection status of this address block. */
70133/*! @{ */
70134#define IRIS_MVPL_HSCALER192_LOCKUNLOCK_hscaler_LockUnlock_MASK (0xFFFFFFFFU)
70135#define IRIS_MVPL_HSCALER192_LOCKUNLOCK_hscaler_LockUnlock_SHIFT (0U)
70136/*! hscaler_LockUnlock - The protection status is changed by writing one of the following key values to this field:
70137 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
70138 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
70139 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
70140 * 0b10110101111000100100011001101110..Disables privilege protection.
70141 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
70142 */
70143#define IRIS_MVPL_HSCALER192_LOCKUNLOCK_hscaler_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER192_LOCKUNLOCK_hscaler_LockUnlock_SHIFT)) & IRIS_MVPL_HSCALER192_LOCKUNLOCK_hscaler_LockUnlock_MASK)
70144/*! @} */
70145
70146/*! @name HSCALER192_LOCKSTATUS - Protection status of this address block. */
70147/*! @{ */
70148#define IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler_LockStatus_MASK (0x1U)
70149#define IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler_LockStatus_SHIFT (0U)
70150/*! hscaler_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
70151 */
70152#define IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler_LockStatus_SHIFT)) & IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler_LockStatus_MASK)
70153#define IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler9_PrivilegeStatus_MASK (0x10U)
70154#define IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler9_PrivilegeStatus_SHIFT (4U)
70155/*! hscaler9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
70156 */
70157#define IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler9_PrivilegeStatus_MASK)
70158#define IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler9_FreezeStatus_MASK (0x100U)
70159#define IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler9_FreezeStatus_SHIFT (8U)
70160/*! hscaler9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
70161 */
70162#define IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler9_FreezeStatus_SHIFT)) & IRIS_MVPL_HSCALER192_LOCKSTATUS_hscaler9_FreezeStatus_MASK)
70163/*! @} */
70164
70165/*! @name HSCALER_DYNAMIC - Dynamic pixel engine configuration for hscaler9 */
70166/*! @{ */
70167#define IRIS_MVPL_HSCALER_DYNAMIC_hscaler9_src_sel_MASK (0x3FU)
70168#define IRIS_MVPL_HSCALER_DYNAMIC_hscaler9_src_sel_SHIFT (0U)
70169/*! hscaler9_src_sel - Selection of the source for the src input of the hscaler9 module
70170 * 0b000000..Unit hscaler9 input port src is disabled
70171 * 0b000110..Unit hscaler9 input port src is connected to output of unit matrix9
70172 * 0b001000..Unit hscaler9 input port src is connected to output of unit vscaler9
70173 * 0b001001..Unit hscaler9 input port src is connected to output of unit filter9
70174 */
70175#define IRIS_MVPL_HSCALER_DYNAMIC_hscaler9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER_DYNAMIC_hscaler9_src_sel_SHIFT)) & IRIS_MVPL_HSCALER_DYNAMIC_hscaler9_src_sel_MASK)
70176#define IRIS_MVPL_HSCALER_DYNAMIC_hscaler9_clken_MASK (0x3000000U)
70177#define IRIS_MVPL_HSCALER_DYNAMIC_hscaler9_clken_SHIFT (24U)
70178/*! hscaler9_clken - Enable of hscaler9 clock (this setting has to be the same for all modules of
70179 * one processing pipeline). If a submodule is enabled and FULL is used, then the register
70180 * [endpoint_name]_clk must be set to 0x80.
70181 * 0b00..Clock for hscaler9 is disabled
70182 * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register)
70183 * 0b11..Clock for hscaler9 is without gating
70184 */
70185#define IRIS_MVPL_HSCALER_DYNAMIC_hscaler9_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER_DYNAMIC_hscaler9_clken_SHIFT)) & IRIS_MVPL_HSCALER_DYNAMIC_hscaler9_clken_MASK)
70186/*! @} */
70187
70188/*! @name HSCALER_STATUS - Status information for pixel engine configuration of hscaler9 */
70189/*! @{ */
70190#define IRIS_MVPL_HSCALER_STATUS_hscaler9_sel_MASK (0x70000U)
70191#define IRIS_MVPL_HSCALER_STATUS_hscaler9_sel_SHIFT (16U)
70192/*! hscaler9_sel - Status of the connection of the hscaler9 module
70193 * 0b000..hscaler9 module is not used
70194 * 0b001..hscaler9 module is used from store9 processing path
70195 * 0b010..hscaler9 module is used from extdst0 processing path
70196 * 0b011..hscaler9 module is used from extdst4 processing path
70197 * 0b100..hscaler9 module is used from extdst1 processing path
70198 * 0b101..hscaler9 module is used from extdst5 processing path
70199 */
70200#define IRIS_MVPL_HSCALER_STATUS_hscaler9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER_STATUS_hscaler9_sel_SHIFT)) & IRIS_MVPL_HSCALER_STATUS_hscaler9_sel_MASK)
70201/*! @} */
70202
70203/*! @name VSCALER224_LOCKUNLOCK - Register to change the protection status of this address block. */
70204/*! @{ */
70205#define IRIS_MVPL_VSCALER224_LOCKUNLOCK_vscaler_LockUnlock_MASK (0xFFFFFFFFU)
70206#define IRIS_MVPL_VSCALER224_LOCKUNLOCK_vscaler_LockUnlock_SHIFT (0U)
70207/*! vscaler_LockUnlock - The protection status is changed by writing one of the following key values to this field:
70208 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
70209 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
70210 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
70211 * 0b10110101111000100100011001101110..Disables privilege protection.
70212 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
70213 */
70214#define IRIS_MVPL_VSCALER224_LOCKUNLOCK_vscaler_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER224_LOCKUNLOCK_vscaler_LockUnlock_SHIFT)) & IRIS_MVPL_VSCALER224_LOCKUNLOCK_vscaler_LockUnlock_MASK)
70215/*! @} */
70216
70217/*! @name VSCALER224_LOCKSTATUS - Protection status of this address block. */
70218/*! @{ */
70219#define IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler_LockStatus_MASK (0x1U)
70220#define IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler_LockStatus_SHIFT (0U)
70221/*! vscaler_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
70222 */
70223#define IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler_LockStatus_SHIFT)) & IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler_LockStatus_MASK)
70224#define IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler9_PrivilegeStatus_MASK (0x10U)
70225#define IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler9_PrivilegeStatus_SHIFT (4U)
70226/*! vscaler9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
70227 */
70228#define IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler9_PrivilegeStatus_MASK)
70229#define IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler9_FreezeStatus_MASK (0x100U)
70230#define IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler9_FreezeStatus_SHIFT (8U)
70231/*! vscaler9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
70232 */
70233#define IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler9_FreezeStatus_SHIFT)) & IRIS_MVPL_VSCALER224_LOCKSTATUS_vscaler9_FreezeStatus_MASK)
70234/*! @} */
70235
70236/*! @name VSCALER_DYNAMIC - Dynamic pixel engine configuration for vscaler9 */
70237/*! @{ */
70238#define IRIS_MVPL_VSCALER_DYNAMIC_vscaler9_src_sel_MASK (0x3FU)
70239#define IRIS_MVPL_VSCALER_DYNAMIC_vscaler9_src_sel_SHIFT (0U)
70240/*! vscaler9_src_sel - Selection of the source for the src input of the vscaler9 module
70241 * 0b000000..Unit vscaler9 input port src is disabled
70242 * 0b000110..Unit vscaler9 input port src is connected to output of unit matrix9
70243 * 0b000111..Unit vscaler9 input port src is connected to output of unit hscaler9
70244 */
70245#define IRIS_MVPL_VSCALER_DYNAMIC_vscaler9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER_DYNAMIC_vscaler9_src_sel_SHIFT)) & IRIS_MVPL_VSCALER_DYNAMIC_vscaler9_src_sel_MASK)
70246#define IRIS_MVPL_VSCALER_DYNAMIC_vscaler9_clken_MASK (0x3000000U)
70247#define IRIS_MVPL_VSCALER_DYNAMIC_vscaler9_clken_SHIFT (24U)
70248/*! vscaler9_clken - Enable of vscaler9 clock (this setting has to be the same for all modules of
70249 * one processing pipeline). If a submodule is enabled and FULL is used, then the register
70250 * [endpoint_name]_clk must be set to 0x80.
70251 * 0b00..Clock for vscaler9 is disabled
70252 * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register)
70253 * 0b11..Clock for vscaler9 is without gating
70254 */
70255#define IRIS_MVPL_VSCALER_DYNAMIC_vscaler9_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER_DYNAMIC_vscaler9_clken_SHIFT)) & IRIS_MVPL_VSCALER_DYNAMIC_vscaler9_clken_MASK)
70256/*! @} */
70257
70258/*! @name VSCALER_STATUS - Status information for pixel engine configuration of vscaler9 */
70259/*! @{ */
70260#define IRIS_MVPL_VSCALER_STATUS_vscaler9_sel_MASK (0x70000U)
70261#define IRIS_MVPL_VSCALER_STATUS_vscaler9_sel_SHIFT (16U)
70262/*! vscaler9_sel - Status of the connection of the vscaler9 module
70263 * 0b000..vscaler9 module is not used
70264 * 0b001..vscaler9 module is used from store9 processing path
70265 * 0b010..vscaler9 module is used from extdst0 processing path
70266 * 0b011..vscaler9 module is used from extdst4 processing path
70267 * 0b100..vscaler9 module is used from extdst1 processing path
70268 * 0b101..vscaler9 module is used from extdst5 processing path
70269 */
70270#define IRIS_MVPL_VSCALER_STATUS_vscaler9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER_STATUS_vscaler9_sel_SHIFT)) & IRIS_MVPL_VSCALER_STATUS_vscaler9_sel_MASK)
70271/*! @} */
70272
70273/*! @name FILTER_LOCKUNLOCK - Register to change the protection status of this address block. */
70274/*! @{ */
70275#define IRIS_MVPL_FILTER_LOCKUNLOCK_filter_LockUnlock_MASK (0xFFFFFFFFU)
70276#define IRIS_MVPL_FILTER_LOCKUNLOCK_filter_LockUnlock_SHIFT (0U)
70277/*! filter_LockUnlock - The protection status is changed by writing one of the following key values to this field:
70278 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
70279 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
70280 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
70281 * 0b10110101111000100100011001101110..Disables privilege protection.
70282 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
70283 */
70284#define IRIS_MVPL_FILTER_LOCKUNLOCK_filter_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER_LOCKUNLOCK_filter_LockUnlock_SHIFT)) & IRIS_MVPL_FILTER_LOCKUNLOCK_filter_LockUnlock_MASK)
70285/*! @} */
70286
70287/*! @name FILTER_LOCKSTATUS - Protection status of this address block. */
70288/*! @{ */
70289#define IRIS_MVPL_FILTER_LOCKSTATUS_filter_LockStatus_MASK (0x1U)
70290#define IRIS_MVPL_FILTER_LOCKSTATUS_filter_LockStatus_SHIFT (0U)
70291/*! filter_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
70292 */
70293#define IRIS_MVPL_FILTER_LOCKSTATUS_filter_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER_LOCKSTATUS_filter_LockStatus_SHIFT)) & IRIS_MVPL_FILTER_LOCKSTATUS_filter_LockStatus_MASK)
70294#define IRIS_MVPL_FILTER_LOCKSTATUS_filter9_PrivilegeStatus_MASK (0x10U)
70295#define IRIS_MVPL_FILTER_LOCKSTATUS_filter9_PrivilegeStatus_SHIFT (4U)
70296/*! filter9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
70297 */
70298#define IRIS_MVPL_FILTER_LOCKSTATUS_filter9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER_LOCKSTATUS_filter9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FILTER_LOCKSTATUS_filter9_PrivilegeStatus_MASK)
70299#define IRIS_MVPL_FILTER_LOCKSTATUS_filter9_FreezeStatus_MASK (0x100U)
70300#define IRIS_MVPL_FILTER_LOCKSTATUS_filter9_FreezeStatus_SHIFT (8U)
70301/*! filter9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
70302 */
70303#define IRIS_MVPL_FILTER_LOCKSTATUS_filter9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER_LOCKSTATUS_filter9_FreezeStatus_SHIFT)) & IRIS_MVPL_FILTER_LOCKSTATUS_filter9_FreezeStatus_MASK)
70304/*! @} */
70305
70306/*! @name FILTER_DYNAMIC - Dynamic pixel engine configuration for filter9 */
70307/*! @{ */
70308#define IRIS_MVPL_FILTER_DYNAMIC_filter9_src_sel_MASK (0x3FU)
70309#define IRIS_MVPL_FILTER_DYNAMIC_filter9_src_sel_SHIFT (0U)
70310/*! filter9_src_sel - Selection of the source for the src input of the filter9 module
70311 * 0b000000..Unit filter9 input port src is disabled
70312 * 0b000110..Unit filter9 input port src is connected to output of unit matrix9
70313 * 0b000111..Unit filter9 input port src is connected to output of unit hscaler9
70314 */
70315#define IRIS_MVPL_FILTER_DYNAMIC_filter9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER_DYNAMIC_filter9_src_sel_SHIFT)) & IRIS_MVPL_FILTER_DYNAMIC_filter9_src_sel_MASK)
70316#define IRIS_MVPL_FILTER_DYNAMIC_filter9_clken_MASK (0x3000000U)
70317#define IRIS_MVPL_FILTER_DYNAMIC_filter9_clken_SHIFT (24U)
70318/*! filter9_clken - Enable of filter9 clock (this setting has to be the same for all modules of one
70319 * processing pipeline). If a submodule is enabled and FULL is used, then the register
70320 * [endpoint_name]_clk must be set to 0x80.
70321 * 0b00..Clock for filter9 is disabled
70322 * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register)
70323 * 0b11..Clock for filter9 is without gating
70324 */
70325#define IRIS_MVPL_FILTER_DYNAMIC_filter9_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER_DYNAMIC_filter9_clken_SHIFT)) & IRIS_MVPL_FILTER_DYNAMIC_filter9_clken_MASK)
70326/*! @} */
70327
70328/*! @name FILTER_STATUS - Status information for pixel engine configuration of filter9 */
70329/*! @{ */
70330#define IRIS_MVPL_FILTER_STATUS_filter9_sel_MASK (0x70000U)
70331#define IRIS_MVPL_FILTER_STATUS_filter9_sel_SHIFT (16U)
70332/*! filter9_sel - Status of the connection of the filter9 module
70333 * 0b000..filter9 module is not used
70334 * 0b001..filter9 module is used from store9 processing path
70335 * 0b010..filter9 module is used from extdst0 processing path
70336 * 0b011..filter9 module is used from extdst4 processing path
70337 * 0b100..filter9 module is used from extdst1 processing path
70338 * 0b101..filter9 module is used from extdst5 processing path
70339 */
70340#define IRIS_MVPL_FILTER_STATUS_filter9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER_STATUS_filter9_sel_SHIFT)) & IRIS_MVPL_FILTER_STATUS_filter9_sel_MASK)
70341/*! @} */
70342
70343/*! @name BLITBLEND_LOCKUNLOCK - Register to change the protection status of this address block. */
70344/*! @{ */
70345#define IRIS_MVPL_BLITBLEND_LOCKUNLOCK_blitblend_LockUnlock_MASK (0xFFFFFFFFU)
70346#define IRIS_MVPL_BLITBLEND_LOCKUNLOCK_blitblend_LockUnlock_SHIFT (0U)
70347/*! blitblend_LockUnlock - The protection status is changed by writing one of the following key values to this field:
70348 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
70349 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
70350 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
70351 * 0b10110101111000100100011001101110..Disables privilege protection.
70352 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
70353 */
70354#define IRIS_MVPL_BLITBLEND_LOCKUNLOCK_blitblend_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND_LOCKUNLOCK_blitblend_LockUnlock_SHIFT)) & IRIS_MVPL_BLITBLEND_LOCKUNLOCK_blitblend_LockUnlock_MASK)
70355/*! @} */
70356
70357/*! @name BLITBLEND_LOCKSTATUS - Protection status of this address block. */
70358/*! @{ */
70359#define IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend_LockStatus_MASK (0x1U)
70360#define IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend_LockStatus_SHIFT (0U)
70361/*! blitblend_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
70362 */
70363#define IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend_LockStatus_SHIFT)) & IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend_LockStatus_MASK)
70364#define IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend9_PrivilegeStatus_MASK (0x10U)
70365#define IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend9_PrivilegeStatus_SHIFT (4U)
70366/*! blitblend9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
70367 */
70368#define IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend9_PrivilegeStatus_MASK)
70369#define IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend9_FreezeStatus_MASK (0x100U)
70370#define IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend9_FreezeStatus_SHIFT (8U)
70371/*! blitblend9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
70372 */
70373#define IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend9_FreezeStatus_SHIFT)) & IRIS_MVPL_BLITBLEND_LOCKSTATUS_blitblend9_FreezeStatus_MASK)
70374/*! @} */
70375
70376/*! @name BLITBLEND_DYNAMIC - Dynamic pixel engine configuration for blitblend9 */
70377/*! @{ */
70378#define IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_prim_sel_MASK (0x3FU)
70379#define IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_prim_sel_SHIFT (0U)
70380/*! blitblend9_prim_sel - Selection of the source for the prim input of the blitblend9 module
70381 * 0b000000..Unit blitblend9 input port prim is disabled
70382 * 0b000100..Unit blitblend9 input port prim is connected to output of unit rop9
70383 * 0b000111..Unit blitblend9 input port prim is connected to output of unit hscaler9
70384 * 0b001000..Unit blitblend9 input port prim is connected to output of unit vscaler9
70385 * 0b001001..Unit blitblend9 input port prim is connected to output of unit filter9
70386 */
70387#define IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_prim_sel_SHIFT)) & IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_prim_sel_MASK)
70388#define IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_sec_sel_MASK (0x3F00U)
70389#define IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_sec_sel_SHIFT (8U)
70390/*! blitblend9_sec_sel - Selection of the source for the sec input of the blitblend9 module
70391 * 0b000000..Unit blitblend9 input port sec is disabled
70392 * 0b000001..Unit blitblend9 input port sec is connected to output of unit fetchdecode9
70393 * 0b000010..Unit blitblend9 input port sec is connected to output of unit fetchwarp9
70394 */
70395#define IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_sec_sel_SHIFT)) & IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_sec_sel_MASK)
70396#define IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_clken_MASK (0x3000000U)
70397#define IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_clken_SHIFT (24U)
70398/*! blitblend9_clken - Enable of blitblend9 clock (this setting has to be the same for all modules
70399 * of one processing pipeline). If a submodule is enabled and FULL is used, then the register
70400 * [endpoint_name]_clk must be set to 0x80.
70401 * 0b00..Clock for blitblend9 is disabled
70402 * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register)
70403 * 0b11..Clock for blitblend9 is without gating
70404 */
70405#define IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_clken_SHIFT)) & IRIS_MVPL_BLITBLEND_DYNAMIC_blitblend9_clken_MASK)
70406/*! @} */
70407
70408/*! @name BLITBLEND_STATUS - Status information for pixel engine configuration of blitblend9 */
70409/*! @{ */
70410#define IRIS_MVPL_BLITBLEND_STATUS_blitblend9_sel_MASK (0x70000U)
70411#define IRIS_MVPL_BLITBLEND_STATUS_blitblend9_sel_SHIFT (16U)
70412/*! blitblend9_sel - Status of the connection of the blitblend9 module
70413 * 0b000..blitblend9 module is not used
70414 * 0b001..blitblend9 module is used from store9 processing path
70415 * 0b010..blitblend9 module is used from extdst0 processing path
70416 * 0b011..blitblend9 module is used from extdst4 processing path
70417 * 0b100..blitblend9 module is used from extdst1 processing path
70418 * 0b101..blitblend9 module is used from extdst5 processing path
70419 */
70420#define IRIS_MVPL_BLITBLEND_STATUS_blitblend9_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND_STATUS_blitblend9_sel_SHIFT)) & IRIS_MVPL_BLITBLEND_STATUS_blitblend9_sel_MASK)
70421/*! @} */
70422
70423/*! @name STORE_LOCKUNLOCK - Register to change the protection status of this address block. */
70424/*! @{ */
70425#define IRIS_MVPL_STORE_LOCKUNLOCK_store_LockUnlock_MASK (0xFFFFFFFFU)
70426#define IRIS_MVPL_STORE_LOCKUNLOCK_store_LockUnlock_SHIFT (0U)
70427/*! store_LockUnlock - The protection status is changed by writing one of the following key values to this field:
70428 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
70429 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
70430 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
70431 * 0b10110101111000100100011001101110..Disables privilege protection.
70432 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
70433 */
70434#define IRIS_MVPL_STORE_LOCKUNLOCK_store_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE_LOCKUNLOCK_store_LockUnlock_SHIFT)) & IRIS_MVPL_STORE_LOCKUNLOCK_store_LockUnlock_MASK)
70435/*! @} */
70436
70437/*! @name STORE_LOCKSTATUS - Protection status of this address block. */
70438/*! @{ */
70439#define IRIS_MVPL_STORE_LOCKSTATUS_store_LockStatus_MASK (0x1U)
70440#define IRIS_MVPL_STORE_LOCKSTATUS_store_LockStatus_SHIFT (0U)
70441/*! store_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
70442 */
70443#define IRIS_MVPL_STORE_LOCKSTATUS_store_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE_LOCKSTATUS_store_LockStatus_SHIFT)) & IRIS_MVPL_STORE_LOCKSTATUS_store_LockStatus_MASK)
70444#define IRIS_MVPL_STORE_LOCKSTATUS_store9_PrivilegeStatus_MASK (0x10U)
70445#define IRIS_MVPL_STORE_LOCKSTATUS_store9_PrivilegeStatus_SHIFT (4U)
70446/*! store9_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
70447 */
70448#define IRIS_MVPL_STORE_LOCKSTATUS_store9_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE_LOCKSTATUS_store9_PrivilegeStatus_SHIFT)) & IRIS_MVPL_STORE_LOCKSTATUS_store9_PrivilegeStatus_MASK)
70449#define IRIS_MVPL_STORE_LOCKSTATUS_store9_FreezeStatus_MASK (0x100U)
70450#define IRIS_MVPL_STORE_LOCKSTATUS_store9_FreezeStatus_SHIFT (8U)
70451/*! store9_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
70452 */
70453#define IRIS_MVPL_STORE_LOCKSTATUS_store9_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE_LOCKSTATUS_store9_FreezeStatus_SHIFT)) & IRIS_MVPL_STORE_LOCKSTATUS_store9_FreezeStatus_MASK)
70454/*! @} */
70455
70456/*! @name STORE9_STATIC - Static pixel engine configuration for store9 */
70457/*! @{ */
70458#define IRIS_MVPL_STORE9_STATIC_store9_ShdEn_MASK (0x1U)
70459#define IRIS_MVPL_STORE9_STATIC_store9_ShdEn_SHIFT (0U)
70460/*! store9_ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed) for
70461 * pixelbus configuration of pipeline with endpoint store9.
70462 */
70463#define IRIS_MVPL_STORE9_STATIC_store9_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATIC_store9_ShdEn_SHIFT)) & IRIS_MVPL_STORE9_STATIC_store9_ShdEn_MASK)
70464#define IRIS_MVPL_STORE9_STATIC_store9_powerdown_MASK (0x10U)
70465#define IRIS_MVPL_STORE9_STATIC_store9_powerdown_SHIFT (4U)
70466/*! store9_powerdown - Set this to 1 to activate powerdown or to 0 to deactivate powerdown for the store9 endpoint.
70467 */
70468#define IRIS_MVPL_STORE9_STATIC_store9_powerdown(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATIC_store9_powerdown_SHIFT)) & IRIS_MVPL_STORE9_STATIC_store9_powerdown_MASK)
70469#define IRIS_MVPL_STORE9_STATIC_store9_Sync_Mode_MASK (0x100U)
70470#define IRIS_MVPL_STORE9_STATIC_store9_Sync_Mode_SHIFT (8U)
70471/*! store9_Sync_Mode - Synchronization mode for store9 pipeline endpoint synchronizer
70472 * 0b0..Reconfig pipeline after explicit trigger
70473 * 0b1..Reconfig pipeline after every kick when idle
70474 */
70475#define IRIS_MVPL_STORE9_STATIC_store9_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATIC_store9_Sync_Mode_SHIFT)) & IRIS_MVPL_STORE9_STATIC_store9_Sync_Mode_MASK)
70476#define IRIS_MVPL_STORE9_STATIC_store9_SW_Reset_MASK (0x800U)
70477#define IRIS_MVPL_STORE9_STATIC_store9_SW_Reset_SHIFT (11U)
70478/*! store9_SW_Reset - Software reset for store9 synchronizer, for debug purposes only
70479 * 0b0..Normal Operation
70480 * 0b1..Software Reset
70481 */
70482#define IRIS_MVPL_STORE9_STATIC_store9_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATIC_store9_SW_Reset_SHIFT)) & IRIS_MVPL_STORE9_STATIC_store9_SW_Reset_MASK)
70483#define IRIS_MVPL_STORE9_STATIC_store9_div_MASK (0xFF0000U)
70484#define IRIS_MVPL_STORE9_STATIC_store9_div_SHIFT (16U)
70485/*! store9_div - store9 clock dividing factor (ratio is register_value/128, values above 128 are
70486 * reserved). If a value smaller than 0x80 is used, than the *_clken registers of all enabled
70487 * submodules have to be set to AUTOMATIC. The value 0x0 disables the clock while the value 0x80 sets
70488 * the clock at full speed.
70489 */
70490#define IRIS_MVPL_STORE9_STATIC_store9_div(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATIC_store9_div_SHIFT)) & IRIS_MVPL_STORE9_STATIC_store9_div_MASK)
70491/*! @} */
70492
70493/*! @name STORE_DYNAMIC - Dynamic pixel engine configuration for store9 */
70494/*! @{ */
70495#define IRIS_MVPL_STORE_DYNAMIC_store9_src_sel_MASK (0x3FU)
70496#define IRIS_MVPL_STORE_DYNAMIC_store9_src_sel_SHIFT (0U)
70497/*! store9_src_sel - Selection of the source for the src input of the store9 module
70498 * 0b000000..Unit store9 input port src is disabled
70499 * 0b000001..Unit store9 input port src is connected to output of unit fetchdecode9
70500 * 0b001010..Unit store9 input port src is connected to output of unit blitblend9
70501 * 0b000010..Unit store9 input port src is connected to output of unit fetchwarp9
70502 * 0b000111..Unit store9 input port src is connected to output of unit hscaler9
70503 * 0b001000..Unit store9 input port src is connected to output of unit vscaler9
70504 * 0b001001..Unit store9 input port src is connected to output of unit filter9
70505 */
70506#define IRIS_MVPL_STORE_DYNAMIC_store9_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE_DYNAMIC_store9_src_sel_SHIFT)) & IRIS_MVPL_STORE_DYNAMIC_store9_src_sel_MASK)
70507/*! @} */
70508
70509/*! @name STORE9_REQUEST - ShadowLoadRequest register for endpoint store9 */
70510/*! @{ */
70511#define IRIS_MVPL_STORE9_REQUEST_store9_sel_ShdLdReq_MASK (0x1U)
70512#define IRIS_MVPL_STORE9_REQUEST_store9_sel_ShdLdReq_SHIFT (0U)
70513/*! store9_sel_ShdLdReq - Shadow load request flag for destination store9.
70514 */
70515#define IRIS_MVPL_STORE9_REQUEST_store9_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_REQUEST_store9_sel_ShdLdReq_SHIFT)) & IRIS_MVPL_STORE9_REQUEST_store9_sel_ShdLdReq_MASK)
70516#define IRIS_MVPL_STORE9_REQUEST_store9_ShdLdReq_MASK (0x7FFEU)
70517#define IRIS_MVPL_STORE9_REQUEST_store9_ShdLdReq_SHIFT (1U)
70518/*! store9_ShdLdReq - Vector of shadow load request flag of all sources for destination store9.
70519 * Setting a bit has no effect if the source is currently in a different pipeline than the one of
70520 * destination store9.
70521 */
70522#define IRIS_MVPL_STORE9_REQUEST_store9_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_REQUEST_store9_ShdLdReq_SHIFT)) & IRIS_MVPL_STORE9_REQUEST_store9_ShdLdReq_MASK)
70523/*! @} */
70524
70525/*! @name STORE9_TRIGGER - Trigger bits for pixel engine configuration of store9 */
70526/*! @{ */
70527#define IRIS_MVPL_STORE9_TRIGGER_store9_Sync_Trigger_MASK (0x1U)
70528#define IRIS_MVPL_STORE9_TRIGGER_store9_Sync_Trigger_SHIFT (0U)
70529/*! store9_Sync_Trigger - Writing a '1' to this field triggers reconfiguration of the pipeline with endpoint store9
70530 */
70531#define IRIS_MVPL_STORE9_TRIGGER_store9_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_TRIGGER_store9_Sync_Trigger_SHIFT)) & IRIS_MVPL_STORE9_TRIGGER_store9_Sync_Trigger_MASK)
70532#define IRIS_MVPL_STORE9_TRIGGER_store9_trigger_sequence_complete_MASK (0x10U)
70533#define IRIS_MVPL_STORE9_TRIGGER_store9_trigger_sequence_complete_SHIFT (4U)
70534/*! store9_trigger_sequence_complete - By writing a '1' to this register field, you can trigger the
70535 * store9 sequence complete interrupt that will occur as soon as the pipeline with the endpoint
70536 * store9 is empty. This interrupt will also occur if the pipeline is already empty when this
70537 * field is written. The interrupt will not occur if this field is not written. The interrupt will
70538 * occur exactly as often as this field is written, assuming that this field is not written again
70539 * until the interrupt has occured after a previous trigger.
70540 */
70541#define IRIS_MVPL_STORE9_TRIGGER_store9_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_TRIGGER_store9_trigger_sequence_complete_SHIFT)) & IRIS_MVPL_STORE9_TRIGGER_store9_trigger_sequence_complete_MASK)
70542/*! @} */
70543
70544/*! @name STORE_STATUS - Status information for pixel engine configuration of store9 */
70545/*! @{ */
70546#define IRIS_MVPL_STORE_STATUS_store9_pipeline_status_MASK (0x3U)
70547#define IRIS_MVPL_STORE_STATUS_store9_pipeline_status_SHIFT (0U)
70548/*! store9_pipeline_status - Status of pipeline with endpoint store9
70549 * 0b00..Pipeline with endpoint store9 is empty
70550 * 0b01..Pipeline with endpoint store9 is currently processing one operation
70551 * 0b10..Pipeline with endpoint store9 is currently processing one operation with a second one already kicked to be processed afterwards
70552 * 0b11..reserved
70553 */
70554#define IRIS_MVPL_STORE_STATUS_store9_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE_STATUS_store9_pipeline_status_SHIFT)) & IRIS_MVPL_STORE_STATUS_store9_pipeline_status_MASK)
70555#define IRIS_MVPL_STORE_STATUS_store9_sync_busy_MASK (0x100U)
70556#define IRIS_MVPL_STORE_STATUS_store9_sync_busy_SHIFT (8U)
70557/*! store9_sync_busy - Synchronization busy status of store9 endpoint
70558 * 0b0..store9 synchronizer is idle
70559 * 0b1..store9 synchronizer is busy
70560 */
70561#define IRIS_MVPL_STORE_STATUS_store9_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE_STATUS_store9_sync_busy_SHIFT)) & IRIS_MVPL_STORE_STATUS_store9_sync_busy_MASK)
70562/*! @} */
70563
70564/*! @name CONSTFRAME352_LOCKUNLOCK - Register to change the protection status of this address block. */
70565/*! @{ */
70566#define IRIS_MVPL_CONSTFRAME352_LOCKUNLOCK_constframe0_LockUnlock_MASK (0xFFFFFFFFU)
70567#define IRIS_MVPL_CONSTFRAME352_LOCKUNLOCK_constframe0_LockUnlock_SHIFT (0U)
70568/*! constframe0_LockUnlock - The protection status is changed by writing one of the following key values to this field:
70569 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
70570 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
70571 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
70572 * 0b10110101111000100100011001101110..Disables privilege protection.
70573 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
70574 */
70575#define IRIS_MVPL_CONSTFRAME352_LOCKUNLOCK_constframe0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME352_LOCKUNLOCK_constframe0_LockUnlock_SHIFT)) & IRIS_MVPL_CONSTFRAME352_LOCKUNLOCK_constframe0_LockUnlock_MASK)
70576/*! @} */
70577
70578/*! @name CONSTFRAME352_LOCKSTATUS - Protection status of this address block. */
70579/*! @{ */
70580#define IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_LockStatus_MASK (0x1U)
70581#define IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_LockStatus_SHIFT (0U)
70582/*! constframe0_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
70583 */
70584#define IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_LockStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_LockStatus_MASK)
70585#define IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_PrivilegeStatus_MASK (0x10U)
70586#define IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_PrivilegeStatus_SHIFT (4U)
70587/*! constframe0_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
70588 */
70589#define IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_PrivilegeStatus_MASK)
70590#define IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_FreezeStatus_MASK (0x100U)
70591#define IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_FreezeStatus_SHIFT (8U)
70592/*! constframe0_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
70593 */
70594#define IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_FreezeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME352_LOCKSTATUS_constframe0_FreezeStatus_MASK)
70595/*! @} */
70596
70597/*! @name CONSTFRAME352_STATUS - Status information for pixel engine configuration of constframe0 */
70598/*! @{ */
70599#define IRIS_MVPL_CONSTFRAME352_STATUS_constframe0_sel_MASK (0x70000U)
70600#define IRIS_MVPL_CONSTFRAME352_STATUS_constframe0_sel_SHIFT (16U)
70601/*! constframe0_sel - Status of the connection of the constframe0 module
70602 * 0b000..constframe0 module is not used
70603 * 0b001..constframe0 module is used from store9 processing path
70604 * 0b010..constframe0 module is used from extdst0 processing path
70605 * 0b011..constframe0 module is used from extdst4 processing path
70606 * 0b100..constframe0 module is used from extdst1 processing path
70607 * 0b101..constframe0 module is used from extdst5 processing path
70608 */
70609#define IRIS_MVPL_CONSTFRAME352_STATUS_constframe0_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME352_STATUS_constframe0_sel_SHIFT)) & IRIS_MVPL_CONSTFRAME352_STATUS_constframe0_sel_MASK)
70610/*! @} */
70611
70612/*! @name EXTDST384_LOCKUNLOCK - Register to change the protection status of this address block. */
70613/*! @{ */
70614#define IRIS_MVPL_EXTDST384_LOCKUNLOCK_extdst0_LockUnlock_MASK (0xFFFFFFFFU)
70615#define IRIS_MVPL_EXTDST384_LOCKUNLOCK_extdst0_LockUnlock_SHIFT (0U)
70616/*! extdst0_LockUnlock - The protection status is changed by writing one of the following key values to this field:
70617 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
70618 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
70619 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
70620 * 0b10110101111000100100011001101110..Disables privilege protection.
70621 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
70622 */
70623#define IRIS_MVPL_EXTDST384_LOCKUNLOCK_extdst0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_LOCKUNLOCK_extdst0_LockUnlock_SHIFT)) & IRIS_MVPL_EXTDST384_LOCKUNLOCK_extdst0_LockUnlock_MASK)
70624/*! @} */
70625
70626/*! @name EXTDST384_LOCKSTATUS - Protection status of this address block. */
70627/*! @{ */
70628#define IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_LockStatus_MASK (0x1U)
70629#define IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_LockStatus_SHIFT (0U)
70630/*! extdst0_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
70631 */
70632#define IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_LockStatus_SHIFT)) & IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_LockStatus_MASK)
70633#define IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_PrivilegeStatus_MASK (0x10U)
70634#define IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_PrivilegeStatus_SHIFT (4U)
70635/*! extdst0_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
70636 */
70637#define IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_PrivilegeStatus_MASK)
70638#define IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_FreezeStatus_MASK (0x100U)
70639#define IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_FreezeStatus_SHIFT (8U)
70640/*! extdst0_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
70641 */
70642#define IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTDST384_LOCKSTATUS_extdst0_FreezeStatus_MASK)
70643/*! @} */
70644
70645/*! @name EXTDST384_STATIC - Static pixel engine configuration for extdst0 */
70646/*! @{ */
70647#define IRIS_MVPL_EXTDST384_STATIC_extdst0_ShdEn_MASK (0x1U)
70648#define IRIS_MVPL_EXTDST384_STATIC_extdst0_ShdEn_SHIFT (0U)
70649/*! extdst0_ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed) for
70650 * pixelbus configuration of pipeline with endpoint extdst0.
70651 */
70652#define IRIS_MVPL_EXTDST384_STATIC_extdst0_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_STATIC_extdst0_ShdEn_SHIFT)) & IRIS_MVPL_EXTDST384_STATIC_extdst0_ShdEn_MASK)
70653#define IRIS_MVPL_EXTDST384_STATIC_extdst0_powerdown_MASK (0x10U)
70654#define IRIS_MVPL_EXTDST384_STATIC_extdst0_powerdown_SHIFT (4U)
70655/*! extdst0_powerdown - Set this to 1 to activate powerdown or to 0 to deactivate powerdown for the extdst0 endpoint.
70656 */
70657#define IRIS_MVPL_EXTDST384_STATIC_extdst0_powerdown(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_STATIC_extdst0_powerdown_SHIFT)) & IRIS_MVPL_EXTDST384_STATIC_extdst0_powerdown_MASK)
70658#define IRIS_MVPL_EXTDST384_STATIC_extdst0_Sync_Mode_MASK (0x100U)
70659#define IRIS_MVPL_EXTDST384_STATIC_extdst0_Sync_Mode_SHIFT (8U)
70660/*! extdst0_Sync_Mode - Synchronization mode for extdst0 pipeline endpoint synchronizer
70661 * 0b0..Reconfig pipeline after explicit trigger
70662 * 0b1..Reconfig pipeline after every kick when idle
70663 */
70664#define IRIS_MVPL_EXTDST384_STATIC_extdst0_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_STATIC_extdst0_Sync_Mode_SHIFT)) & IRIS_MVPL_EXTDST384_STATIC_extdst0_Sync_Mode_MASK)
70665#define IRIS_MVPL_EXTDST384_STATIC_extdst0_SW_Reset_MASK (0x800U)
70666#define IRIS_MVPL_EXTDST384_STATIC_extdst0_SW_Reset_SHIFT (11U)
70667/*! extdst0_SW_Reset - Software reset for extdst0 synchronizer, for debug purposes only
70668 * 0b0..Normal Operation
70669 * 0b1..Software Reset
70670 */
70671#define IRIS_MVPL_EXTDST384_STATIC_extdst0_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_STATIC_extdst0_SW_Reset_SHIFT)) & IRIS_MVPL_EXTDST384_STATIC_extdst0_SW_Reset_MASK)
70672#define IRIS_MVPL_EXTDST384_STATIC_extdst0_div_MASK (0xFF0000U)
70673#define IRIS_MVPL_EXTDST384_STATIC_extdst0_div_SHIFT (16U)
70674/*! extdst0_div - extdst0 clock dividing factor (ratio is register_value/128, values above 128 are
70675 * reserved). If a value smaller than 0x80 is used, than the *_clken registers of all enabled
70676 * submodules have to be set to AUTOMATIC. The value 0x0 disables the clock while the value 0x80 sets
70677 * the clock at full speed.
70678 */
70679#define IRIS_MVPL_EXTDST384_STATIC_extdst0_div(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_STATIC_extdst0_div_SHIFT)) & IRIS_MVPL_EXTDST384_STATIC_extdst0_div_MASK)
70680/*! @} */
70681
70682/*! @name EXTDST384_DYNAMIC - Dynamic pixel engine configuration for extdst0 */
70683/*! @{ */
70684#define IRIS_MVPL_EXTDST384_DYNAMIC_extdst0_src_sel_MASK (0x3FU)
70685#define IRIS_MVPL_EXTDST384_DYNAMIC_extdst0_src_sel_SHIFT (0U)
70686/*! extdst0_src_sel - Selection of the source for the src input of the extdst0 module
70687 * 0b000000..Unit extdst0 input port src is disabled
70688 * 0b001010..Unit extdst0 input port src is connected to output of unit blitblend9
70689 * 0b001100..Unit extdst0 input port src is connected to output of unit constframe0
70690 * 0b001110..Unit extdst0 input port src is connected to output of unit constframe4
70691 * 0b000000..Unit extdst0 input port src is connected to output of unit constframe1
70692 * 0b010010..Unit extdst0 input port src is connected to output of unit constframe5
70693 * 0b011011..Unit extdst0 input port src is connected to output of unit matrix4
70694 * 0b011100..Unit extdst0 input port src is connected to output of unit hscaler4
70695 * 0b011101..Unit extdst0 input port src is connected to output of unit vscaler4
70696 * 0b011110..Unit extdst0 input port src is connected to output of unit matrix5
70697 * 0b011111..Unit extdst0 input port src is connected to output of unit hscaler5
70698 * 0b100000..Unit extdst0 input port src is connected to output of unit vscaler5
70699 * 0b100001..Unit extdst0 input port src is connected to output of unit layerblend0
70700 * 0b100010..Unit extdst0 input port src is connected to output of unit layerblend1
70701 * 0b100011..Unit extdst0 input port src is connected to output of unit layerblend2
70702 * 0b100100..Unit extdst0 input port src is connected to output of unit layerblend3
70703 */
70704#define IRIS_MVPL_EXTDST384_DYNAMIC_extdst0_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_DYNAMIC_extdst0_src_sel_SHIFT)) & IRIS_MVPL_EXTDST384_DYNAMIC_extdst0_src_sel_MASK)
70705/*! @} */
70706
70707/*! @name EXTDST384_REQUEST - ShadowLoadRequest register for endpoint extdst0 */
70708/*! @{ */
70709#define IRIS_MVPL_EXTDST384_REQUEST_extdst0_sel_ShdLdReq_MASK (0x1U)
70710#define IRIS_MVPL_EXTDST384_REQUEST_extdst0_sel_ShdLdReq_SHIFT (0U)
70711/*! extdst0_sel_ShdLdReq - Shadow load request flag for destination extdst0.
70712 */
70713#define IRIS_MVPL_EXTDST384_REQUEST_extdst0_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_REQUEST_extdst0_sel_ShdLdReq_SHIFT)) & IRIS_MVPL_EXTDST384_REQUEST_extdst0_sel_ShdLdReq_MASK)
70714#define IRIS_MVPL_EXTDST384_REQUEST_extdst0_ShdLdReq_MASK (0x7FFEU)
70715#define IRIS_MVPL_EXTDST384_REQUEST_extdst0_ShdLdReq_SHIFT (1U)
70716/*! extdst0_ShdLdReq - Vector of shadow load request flag of all sources for destination extdst0.
70717 * Setting a bit has no effect if the source is currently in a different pipeline than the one of
70718 * destination extdst0.
70719 */
70720#define IRIS_MVPL_EXTDST384_REQUEST_extdst0_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_REQUEST_extdst0_ShdLdReq_SHIFT)) & IRIS_MVPL_EXTDST384_REQUEST_extdst0_ShdLdReq_MASK)
70721/*! @} */
70722
70723/*! @name EXTDST384_TRIGGER - Trigger bits for pixel engine configuration of extdst0 */
70724/*! @{ */
70725#define IRIS_MVPL_EXTDST384_TRIGGER_extdst0_Sync_Trigger_MASK (0x1U)
70726#define IRIS_MVPL_EXTDST384_TRIGGER_extdst0_Sync_Trigger_SHIFT (0U)
70727/*! extdst0_Sync_Trigger - Writing a '1' to this field triggers reconfiguration of the pipeline with endpoint extdst0
70728 */
70729#define IRIS_MVPL_EXTDST384_TRIGGER_extdst0_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_TRIGGER_extdst0_Sync_Trigger_SHIFT)) & IRIS_MVPL_EXTDST384_TRIGGER_extdst0_Sync_Trigger_MASK)
70730#define IRIS_MVPL_EXTDST384_TRIGGER_extdst0_trigger_sequence_complete_MASK (0x10U)
70731#define IRIS_MVPL_EXTDST384_TRIGGER_extdst0_trigger_sequence_complete_SHIFT (4U)
70732/*! extdst0_trigger_sequence_complete - By writing a '1' to this register field, you can trigger the
70733 * extdst0 sequence complete interrupt that will occur as soon as the pipeline with the endpoint
70734 * extdst0 is empty. This interrupt will also occur if the pipeline is already empty when this
70735 * field is written. The interrupt will not occur if this field is not written. The interrupt will
70736 * occur exactly as often as this field is written, assuming that this field is not written
70737 * again until the interrupt has occured after a previous trigger.
70738 */
70739#define IRIS_MVPL_EXTDST384_TRIGGER_extdst0_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_TRIGGER_extdst0_trigger_sequence_complete_SHIFT)) & IRIS_MVPL_EXTDST384_TRIGGER_extdst0_trigger_sequence_complete_MASK)
70740/*! @} */
70741
70742/*! @name EXTDST384_STATUS - Status information for pixel engine configuration of extdst0 */
70743/*! @{ */
70744#define IRIS_MVPL_EXTDST384_STATUS_extdst0_pipeline_status_MASK (0x3U)
70745#define IRIS_MVPL_EXTDST384_STATUS_extdst0_pipeline_status_SHIFT (0U)
70746/*! extdst0_pipeline_status - Status of pipeline with endpoint extdst0
70747 * 0b00..Pipeline with endpoint extdst0 is empty
70748 * 0b01..Pipeline with endpoint extdst0 is currently processing one operation
70749 * 0b10..Pipeline with endpoint extdst0 is currently processing one operation with a second one already kicked to be processed afterwards
70750 * 0b11..reserved
70751 */
70752#define IRIS_MVPL_EXTDST384_STATUS_extdst0_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_STATUS_extdst0_pipeline_status_SHIFT)) & IRIS_MVPL_EXTDST384_STATUS_extdst0_pipeline_status_MASK)
70753#define IRIS_MVPL_EXTDST384_STATUS_extdst0_sync_busy_MASK (0x100U)
70754#define IRIS_MVPL_EXTDST384_STATUS_extdst0_sync_busy_SHIFT (8U)
70755/*! extdst0_sync_busy - Synchronization busy status of extdst0 endpoint
70756 * 0b0..extdst0 synchronizer is idle
70757 * 0b1..extdst0 synchronizer is busy
70758 */
70759#define IRIS_MVPL_EXTDST384_STATUS_extdst0_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST384_STATUS_extdst0_sync_busy_SHIFT)) & IRIS_MVPL_EXTDST384_STATUS_extdst0_sync_busy_MASK)
70760/*! @} */
70761
70762/*! @name CONSTFRAME416_LOCKUNLOCK - Register to change the protection status of this address block. */
70763/*! @{ */
70764#define IRIS_MVPL_CONSTFRAME416_LOCKUNLOCK_constframe4_LockUnlock_MASK (0xFFFFFFFFU)
70765#define IRIS_MVPL_CONSTFRAME416_LOCKUNLOCK_constframe4_LockUnlock_SHIFT (0U)
70766/*! constframe4_LockUnlock - The protection status is changed by writing one of the following key values to this field:
70767 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
70768 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
70769 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
70770 * 0b10110101111000100100011001101110..Disables privilege protection.
70771 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
70772 */
70773#define IRIS_MVPL_CONSTFRAME416_LOCKUNLOCK_constframe4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME416_LOCKUNLOCK_constframe4_LockUnlock_SHIFT)) & IRIS_MVPL_CONSTFRAME416_LOCKUNLOCK_constframe4_LockUnlock_MASK)
70774/*! @} */
70775
70776/*! @name CONSTFRAME416_LOCKSTATUS - Protection status of this address block. */
70777/*! @{ */
70778#define IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_LockStatus_MASK (0x1U)
70779#define IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_LockStatus_SHIFT (0U)
70780/*! constframe4_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
70781 */
70782#define IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_LockStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_LockStatus_MASK)
70783#define IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_PrivilegeStatus_MASK (0x10U)
70784#define IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_PrivilegeStatus_SHIFT (4U)
70785/*! constframe4_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
70786 */
70787#define IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_PrivilegeStatus_MASK)
70788#define IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_FreezeStatus_MASK (0x100U)
70789#define IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_FreezeStatus_SHIFT (8U)
70790/*! constframe4_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
70791 */
70792#define IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_FreezeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME416_LOCKSTATUS_constframe4_FreezeStatus_MASK)
70793/*! @} */
70794
70795/*! @name CONSTFRAME416_STATUS - Status information for pixel engine configuration of constframe4 */
70796/*! @{ */
70797#define IRIS_MVPL_CONSTFRAME416_STATUS_constframe4_sel_MASK (0x70000U)
70798#define IRIS_MVPL_CONSTFRAME416_STATUS_constframe4_sel_SHIFT (16U)
70799/*! constframe4_sel - Status of the connection of the constframe4 module
70800 * 0b000..constframe4 module is not used
70801 * 0b001..constframe4 module is used from store9 processing path
70802 * 0b010..constframe4 module is used from extdst0 processing path
70803 * 0b011..constframe4 module is used from extdst4 processing path
70804 * 0b100..constframe4 module is used from extdst1 processing path
70805 * 0b101..constframe4 module is used from extdst5 processing path
70806 */
70807#define IRIS_MVPL_CONSTFRAME416_STATUS_constframe4_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME416_STATUS_constframe4_sel_SHIFT)) & IRIS_MVPL_CONSTFRAME416_STATUS_constframe4_sel_MASK)
70808/*! @} */
70809
70810/*! @name EXTDST448_LOCKUNLOCK - Register to change the protection status of this address block. */
70811/*! @{ */
70812#define IRIS_MVPL_EXTDST448_LOCKUNLOCK_extdst4_LockUnlock_MASK (0xFFFFFFFFU)
70813#define IRIS_MVPL_EXTDST448_LOCKUNLOCK_extdst4_LockUnlock_SHIFT (0U)
70814/*! extdst4_LockUnlock - The protection status is changed by writing one of the following key values to this field:
70815 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
70816 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
70817 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
70818 * 0b10110101111000100100011001101110..Disables privilege protection.
70819 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
70820 */
70821#define IRIS_MVPL_EXTDST448_LOCKUNLOCK_extdst4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_LOCKUNLOCK_extdst4_LockUnlock_SHIFT)) & IRIS_MVPL_EXTDST448_LOCKUNLOCK_extdst4_LockUnlock_MASK)
70822/*! @} */
70823
70824/*! @name EXTDST448_LOCKSTATUS - Protection status of this address block. */
70825/*! @{ */
70826#define IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_LockStatus_MASK (0x1U)
70827#define IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_LockStatus_SHIFT (0U)
70828/*! extdst4_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
70829 */
70830#define IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_LockStatus_SHIFT)) & IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_LockStatus_MASK)
70831#define IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_PrivilegeStatus_MASK (0x10U)
70832#define IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_PrivilegeStatus_SHIFT (4U)
70833/*! extdst4_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
70834 */
70835#define IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_PrivilegeStatus_MASK)
70836#define IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_FreezeStatus_MASK (0x100U)
70837#define IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_FreezeStatus_SHIFT (8U)
70838/*! extdst4_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
70839 */
70840#define IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTDST448_LOCKSTATUS_extdst4_FreezeStatus_MASK)
70841/*! @} */
70842
70843/*! @name EXTDST448_STATIC - Static pixel engine configuration for extdst4 */
70844/*! @{ */
70845#define IRIS_MVPL_EXTDST448_STATIC_extdst4_ShdEn_MASK (0x1U)
70846#define IRIS_MVPL_EXTDST448_STATIC_extdst4_ShdEn_SHIFT (0U)
70847/*! extdst4_ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed) for
70848 * pixelbus configuration of pipeline with endpoint extdst4.
70849 */
70850#define IRIS_MVPL_EXTDST448_STATIC_extdst4_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_STATIC_extdst4_ShdEn_SHIFT)) & IRIS_MVPL_EXTDST448_STATIC_extdst4_ShdEn_MASK)
70851#define IRIS_MVPL_EXTDST448_STATIC_extdst4_powerdown_MASK (0x10U)
70852#define IRIS_MVPL_EXTDST448_STATIC_extdst4_powerdown_SHIFT (4U)
70853/*! extdst4_powerdown - Set this to 1 to activate powerdown or to 0 to deactivate powerdown for the extdst4 endpoint.
70854 */
70855#define IRIS_MVPL_EXTDST448_STATIC_extdst4_powerdown(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_STATIC_extdst4_powerdown_SHIFT)) & IRIS_MVPL_EXTDST448_STATIC_extdst4_powerdown_MASK)
70856#define IRIS_MVPL_EXTDST448_STATIC_extdst4_Sync_Mode_MASK (0x100U)
70857#define IRIS_MVPL_EXTDST448_STATIC_extdst4_Sync_Mode_SHIFT (8U)
70858/*! extdst4_Sync_Mode - Synchronization mode for extdst4 pipeline endpoint synchronizer
70859 * 0b0..Reconfig pipeline after explicit trigger
70860 * 0b1..Reconfig pipeline after every kick when idle
70861 */
70862#define IRIS_MVPL_EXTDST448_STATIC_extdst4_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_STATIC_extdst4_Sync_Mode_SHIFT)) & IRIS_MVPL_EXTDST448_STATIC_extdst4_Sync_Mode_MASK)
70863#define IRIS_MVPL_EXTDST448_STATIC_extdst4_SW_Reset_MASK (0x800U)
70864#define IRIS_MVPL_EXTDST448_STATIC_extdst4_SW_Reset_SHIFT (11U)
70865/*! extdst4_SW_Reset - Software reset for extdst4 synchronizer, for debug purposes only
70866 * 0b0..Normal Operation
70867 * 0b1..Software Reset
70868 */
70869#define IRIS_MVPL_EXTDST448_STATIC_extdst4_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_STATIC_extdst4_SW_Reset_SHIFT)) & IRIS_MVPL_EXTDST448_STATIC_extdst4_SW_Reset_MASK)
70870#define IRIS_MVPL_EXTDST448_STATIC_extdst4_div_MASK (0xFF0000U)
70871#define IRIS_MVPL_EXTDST448_STATIC_extdst4_div_SHIFT (16U)
70872/*! extdst4_div - extdst4 clock dividing factor (ratio is register_value/128, values above 128 are
70873 * reserved). If a value smaller than 0x80 is used, than the *_clken registers of all enabled
70874 * submodules have to be set to AUTOMATIC. The value 0x0 disables the clock while the value 0x80 sets
70875 * the clock at full speed.
70876 */
70877#define IRIS_MVPL_EXTDST448_STATIC_extdst4_div(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_STATIC_extdst4_div_SHIFT)) & IRIS_MVPL_EXTDST448_STATIC_extdst4_div_MASK)
70878/*! @} */
70879
70880/*! @name EXTDST448_DYNAMIC - Dynamic pixel engine configuration for extdst4 */
70881/*! @{ */
70882#define IRIS_MVPL_EXTDST448_DYNAMIC_extdst4_src_sel_MASK (0x3FU)
70883#define IRIS_MVPL_EXTDST448_DYNAMIC_extdst4_src_sel_SHIFT (0U)
70884/*! extdst4_src_sel - Selection of the source for the src input of the extdst4 module
70885 * 0b000000..Unit extdst4 input port src is disabled
70886 * 0b001010..Unit extdst4 input port src is connected to output of unit blitblend9
70887 * 0b001100..Unit extdst4 input port src is connected to output of unit constframe0
70888 * 0b001110..Unit extdst4 input port src is connected to output of unit constframe4
70889 * 0b000000..Unit extdst4 input port src is connected to output of unit constframe1
70890 * 0b010010..Unit extdst4 input port src is connected to output of unit constframe5
70891 * 0b011011..Unit extdst4 input port src is connected to output of unit matrix4
70892 * 0b011100..Unit extdst4 input port src is connected to output of unit hscaler4
70893 * 0b011101..Unit extdst4 input port src is connected to output of unit vscaler4
70894 * 0b011110..Unit extdst4 input port src is connected to output of unit matrix5
70895 * 0b011111..Unit extdst4 input port src is connected to output of unit hscaler5
70896 * 0b100000..Unit extdst4 input port src is connected to output of unit vscaler5
70897 * 0b100001..Unit extdst4 input port src is connected to output of unit layerblend0
70898 * 0b100010..Unit extdst4 input port src is connected to output of unit layerblend1
70899 * 0b100011..Unit extdst4 input port src is connected to output of unit layerblend2
70900 * 0b100100..Unit extdst4 input port src is connected to output of unit layerblend3
70901 */
70902#define IRIS_MVPL_EXTDST448_DYNAMIC_extdst4_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_DYNAMIC_extdst4_src_sel_SHIFT)) & IRIS_MVPL_EXTDST448_DYNAMIC_extdst4_src_sel_MASK)
70903/*! @} */
70904
70905/*! @name EXTDST448_REQUEST - ShadowLoadRequest register for endpoint extdst4 */
70906/*! @{ */
70907#define IRIS_MVPL_EXTDST448_REQUEST_extdst4_sel_ShdLdReq_MASK (0x1U)
70908#define IRIS_MVPL_EXTDST448_REQUEST_extdst4_sel_ShdLdReq_SHIFT (0U)
70909/*! extdst4_sel_ShdLdReq - Shadow load request flag for destination extdst4.
70910 */
70911#define IRIS_MVPL_EXTDST448_REQUEST_extdst4_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_REQUEST_extdst4_sel_ShdLdReq_SHIFT)) & IRIS_MVPL_EXTDST448_REQUEST_extdst4_sel_ShdLdReq_MASK)
70912#define IRIS_MVPL_EXTDST448_REQUEST_extdst4_ShdLdReq_MASK (0x7FFEU)
70913#define IRIS_MVPL_EXTDST448_REQUEST_extdst4_ShdLdReq_SHIFT (1U)
70914/*! extdst4_ShdLdReq - Vector of shadow load request flag of all sources for destination extdst4.
70915 * Setting a bit has no effect if the source is currently in a different pipeline than the one of
70916 * destination extdst4.
70917 */
70918#define IRIS_MVPL_EXTDST448_REQUEST_extdst4_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_REQUEST_extdst4_ShdLdReq_SHIFT)) & IRIS_MVPL_EXTDST448_REQUEST_extdst4_ShdLdReq_MASK)
70919/*! @} */
70920
70921/*! @name EXTDST448_TRIGGER - Trigger bits for pixel engine configuration of extdst4 */
70922/*! @{ */
70923#define IRIS_MVPL_EXTDST448_TRIGGER_extdst4_Sync_Trigger_MASK (0x1U)
70924#define IRIS_MVPL_EXTDST448_TRIGGER_extdst4_Sync_Trigger_SHIFT (0U)
70925/*! extdst4_Sync_Trigger - Writing a '1' to this field triggers reconfiguration of the pipeline with endpoint extdst4
70926 */
70927#define IRIS_MVPL_EXTDST448_TRIGGER_extdst4_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_TRIGGER_extdst4_Sync_Trigger_SHIFT)) & IRIS_MVPL_EXTDST448_TRIGGER_extdst4_Sync_Trigger_MASK)
70928#define IRIS_MVPL_EXTDST448_TRIGGER_extdst4_trigger_sequence_complete_MASK (0x10U)
70929#define IRIS_MVPL_EXTDST448_TRIGGER_extdst4_trigger_sequence_complete_SHIFT (4U)
70930/*! extdst4_trigger_sequence_complete - By writing a '1' to this register field, you can trigger the
70931 * extdst4 sequence complete interrupt that will occur as soon as the pipeline with the endpoint
70932 * extdst4 is empty. This interrupt will also occur if the pipeline is already empty when this
70933 * field is written. The interrupt will not occur if this field is not written. The interrupt will
70934 * occur exactly as often as this field is written, assuming that this field is not written
70935 * again until the interrupt has occured after a previous trigger.
70936 */
70937#define IRIS_MVPL_EXTDST448_TRIGGER_extdst4_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_TRIGGER_extdst4_trigger_sequence_complete_SHIFT)) & IRIS_MVPL_EXTDST448_TRIGGER_extdst4_trigger_sequence_complete_MASK)
70938/*! @} */
70939
70940/*! @name EXTDST448_STATUS - Status information for pixel engine configuration of extdst4 */
70941/*! @{ */
70942#define IRIS_MVPL_EXTDST448_STATUS_extdst4_pipeline_status_MASK (0x3U)
70943#define IRIS_MVPL_EXTDST448_STATUS_extdst4_pipeline_status_SHIFT (0U)
70944/*! extdst4_pipeline_status - Status of pipeline with endpoint extdst4
70945 * 0b00..Pipeline with endpoint extdst4 is empty
70946 * 0b01..Pipeline with endpoint extdst4 is currently processing one operation
70947 * 0b10..Pipeline with endpoint extdst4 is currently processing one operation with a second one already kicked to be processed afterwards
70948 * 0b11..reserved
70949 */
70950#define IRIS_MVPL_EXTDST448_STATUS_extdst4_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_STATUS_extdst4_pipeline_status_SHIFT)) & IRIS_MVPL_EXTDST448_STATUS_extdst4_pipeline_status_MASK)
70951#define IRIS_MVPL_EXTDST448_STATUS_extdst4_sync_busy_MASK (0x100U)
70952#define IRIS_MVPL_EXTDST448_STATUS_extdst4_sync_busy_SHIFT (8U)
70953/*! extdst4_sync_busy - Synchronization busy status of extdst4 endpoint
70954 * 0b0..extdst4 synchronizer is idle
70955 * 0b1..extdst4 synchronizer is busy
70956 */
70957#define IRIS_MVPL_EXTDST448_STATUS_extdst4_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST448_STATUS_extdst4_sync_busy_SHIFT)) & IRIS_MVPL_EXTDST448_STATUS_extdst4_sync_busy_MASK)
70958/*! @} */
70959
70960/*! @name CONSTFRAME480_LOCKUNLOCK - Register to change the protection status of this address block. */
70961/*! @{ */
70962#define IRIS_MVPL_CONSTFRAME480_LOCKUNLOCK_constframe1_LockUnlock_MASK (0xFFFFFFFFU)
70963#define IRIS_MVPL_CONSTFRAME480_LOCKUNLOCK_constframe1_LockUnlock_SHIFT (0U)
70964/*! constframe1_LockUnlock - The protection status is changed by writing one of the following key values to this field:
70965 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
70966 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
70967 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
70968 * 0b10110101111000100100011001101110..Disables privilege protection.
70969 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
70970 */
70971#define IRIS_MVPL_CONSTFRAME480_LOCKUNLOCK_constframe1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME480_LOCKUNLOCK_constframe1_LockUnlock_SHIFT)) & IRIS_MVPL_CONSTFRAME480_LOCKUNLOCK_constframe1_LockUnlock_MASK)
70972/*! @} */
70973
70974/*! @name CONSTFRAME480_LOCKSTATUS - Protection status of this address block. */
70975/*! @{ */
70976#define IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_LockStatus_MASK (0x1U)
70977#define IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_LockStatus_SHIFT (0U)
70978/*! constframe1_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
70979 */
70980#define IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_LockStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_LockStatus_MASK)
70981#define IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_PrivilegeStatus_MASK (0x10U)
70982#define IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_PrivilegeStatus_SHIFT (4U)
70983/*! constframe1_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
70984 */
70985#define IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_PrivilegeStatus_MASK)
70986#define IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_FreezeStatus_MASK (0x100U)
70987#define IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_FreezeStatus_SHIFT (8U)
70988/*! constframe1_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
70989 */
70990#define IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_FreezeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME480_LOCKSTATUS_constframe1_FreezeStatus_MASK)
70991/*! @} */
70992
70993/*! @name CONSTFRAME480_STATUS - Status information for pixel engine configuration of constframe1 */
70994/*! @{ */
70995#define IRIS_MVPL_CONSTFRAME480_STATUS_constframe1_sel_MASK (0x70000U)
70996#define IRIS_MVPL_CONSTFRAME480_STATUS_constframe1_sel_SHIFT (16U)
70997/*! constframe1_sel - Status of the connection of the constframe1 module
70998 * 0b000..constframe1 module is not used
70999 * 0b001..constframe1 module is used from store9 processing path
71000 * 0b010..constframe1 module is used from extdst0 processing path
71001 * 0b011..constframe1 module is used from extdst4 processing path
71002 * 0b100..constframe1 module is used from extdst1 processing path
71003 * 0b101..constframe1 module is used from extdst5 processing path
71004 */
71005#define IRIS_MVPL_CONSTFRAME480_STATUS_constframe1_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME480_STATUS_constframe1_sel_SHIFT)) & IRIS_MVPL_CONSTFRAME480_STATUS_constframe1_sel_MASK)
71006/*! @} */
71007
71008/*! @name EXTDST512_LOCKUNLOCK - Register to change the protection status of this address block. */
71009/*! @{ */
71010#define IRIS_MVPL_EXTDST512_LOCKUNLOCK_extdst1_LockUnlock_MASK (0xFFFFFFFFU)
71011#define IRIS_MVPL_EXTDST512_LOCKUNLOCK_extdst1_LockUnlock_SHIFT (0U)
71012/*! extdst1_LockUnlock - The protection status is changed by writing one of the following key values to this field:
71013 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
71014 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
71015 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
71016 * 0b10110101111000100100011001101110..Disables privilege protection.
71017 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
71018 */
71019#define IRIS_MVPL_EXTDST512_LOCKUNLOCK_extdst1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST512_LOCKUNLOCK_extdst1_LockUnlock_SHIFT)) & IRIS_MVPL_EXTDST512_LOCKUNLOCK_extdst1_LockUnlock_MASK)
71020/*! @} */
71021
71022/*! @name EXTDST512_LOCKSTATUS - Protection status of this address block. */
71023/*! @{ */
71024#define IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_LockStatus_MASK (0x1U)
71025#define IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_LockStatus_SHIFT (0U)
71026/*! extdst1_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
71027 */
71028#define IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_LockStatus_SHIFT)) & IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_LockStatus_MASK)
71029#define IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_PrivilegeStatus_MASK (0x10U)
71030#define IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_PrivilegeStatus_SHIFT (4U)
71031/*! extdst1_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
71032 */
71033#define IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_PrivilegeStatus_MASK)
71034#define IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_FreezeStatus_MASK (0x100U)
71035#define IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_FreezeStatus_SHIFT (8U)
71036/*! extdst1_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
71037 */
71038#define IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTDST512_LOCKSTATUS_extdst1_FreezeStatus_MASK)
71039/*! @} */
71040
71041/*! @name EXTDST1_STATIC - Static pixel engine configuration for extdst1 */
71042/*! @{ */
71043#define IRIS_MVPL_EXTDST1_STATIC_extdst1_ShdEn_MASK (0x1U)
71044#define IRIS_MVPL_EXTDST1_STATIC_extdst1_ShdEn_SHIFT (0U)
71045/*! extdst1_ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed) for
71046 * pixelbus configuration of pipeline with endpoint extdst1.
71047 */
71048#define IRIS_MVPL_EXTDST1_STATIC_extdst1_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_STATIC_extdst1_ShdEn_SHIFT)) & IRIS_MVPL_EXTDST1_STATIC_extdst1_ShdEn_MASK)
71049#define IRIS_MVPL_EXTDST1_STATIC_extdst1_powerdown_MASK (0x10U)
71050#define IRIS_MVPL_EXTDST1_STATIC_extdst1_powerdown_SHIFT (4U)
71051/*! extdst1_powerdown - Set this to 1 to activate powerdown or to 0 to deactivate powerdown for the extdst1 endpoint.
71052 */
71053#define IRIS_MVPL_EXTDST1_STATIC_extdst1_powerdown(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_STATIC_extdst1_powerdown_SHIFT)) & IRIS_MVPL_EXTDST1_STATIC_extdst1_powerdown_MASK)
71054#define IRIS_MVPL_EXTDST1_STATIC_extdst1_Sync_Mode_MASK (0x100U)
71055#define IRIS_MVPL_EXTDST1_STATIC_extdst1_Sync_Mode_SHIFT (8U)
71056/*! extdst1_Sync_Mode - Synchronization mode for extdst1 pipeline endpoint synchronizer
71057 * 0b0..Reconfig pipeline after explicit trigger
71058 * 0b1..Reconfig pipeline after every kick when idle
71059 */
71060#define IRIS_MVPL_EXTDST1_STATIC_extdst1_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_STATIC_extdst1_Sync_Mode_SHIFT)) & IRIS_MVPL_EXTDST1_STATIC_extdst1_Sync_Mode_MASK)
71061#define IRIS_MVPL_EXTDST1_STATIC_extdst1_SW_Reset_MASK (0x800U)
71062#define IRIS_MVPL_EXTDST1_STATIC_extdst1_SW_Reset_SHIFT (11U)
71063/*! extdst1_SW_Reset - Software reset for extdst1 synchronizer, for debug purposes only
71064 * 0b0..Normal Operation
71065 * 0b1..Software Reset
71066 */
71067#define IRIS_MVPL_EXTDST1_STATIC_extdst1_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_STATIC_extdst1_SW_Reset_SHIFT)) & IRIS_MVPL_EXTDST1_STATIC_extdst1_SW_Reset_MASK)
71068#define IRIS_MVPL_EXTDST1_STATIC_extdst1_div_MASK (0xFF0000U)
71069#define IRIS_MVPL_EXTDST1_STATIC_extdst1_div_SHIFT (16U)
71070/*! extdst1_div - extdst1 clock dividing factor (ratio is register_value/128, values above 128 are
71071 * reserved). If a value smaller than 0x80 is used, than the *_clken registers of all enabled
71072 * submodules have to be set to AUTOMATIC. The value 0x0 disables the clock while the value 0x80 sets
71073 * the clock at full speed.
71074 */
71075#define IRIS_MVPL_EXTDST1_STATIC_extdst1_div(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_STATIC_extdst1_div_SHIFT)) & IRIS_MVPL_EXTDST1_STATIC_extdst1_div_MASK)
71076/*! @} */
71077
71078/*! @name EXTDST1_DYNAMIC - Dynamic pixel engine configuration for extdst1 */
71079/*! @{ */
71080#define IRIS_MVPL_EXTDST1_DYNAMIC_extdst1_src_sel_MASK (0x3FU)
71081#define IRIS_MVPL_EXTDST1_DYNAMIC_extdst1_src_sel_SHIFT (0U)
71082/*! extdst1_src_sel - Selection of the source for the src input of the extdst1 module
71083 * 0b000000..Unit extdst1 input port src is disabled
71084 * 0b001010..Unit extdst1 input port src is connected to output of unit blitblend9
71085 * 0b001100..Unit extdst1 input port src is connected to output of unit constframe0
71086 * 0b001110..Unit extdst1 input port src is connected to output of unit constframe4
71087 * 0b000000..Unit extdst1 input port src is connected to output of unit constframe1
71088 * 0b010010..Unit extdst1 input port src is connected to output of unit constframe5
71089 * 0b011011..Unit extdst1 input port src is connected to output of unit matrix4
71090 * 0b011100..Unit extdst1 input port src is connected to output of unit hscaler4
71091 * 0b011101..Unit extdst1 input port src is connected to output of unit vscaler4
71092 * 0b011110..Unit extdst1 input port src is connected to output of unit matrix5
71093 * 0b011111..Unit extdst1 input port src is connected to output of unit hscaler5
71094 * 0b100000..Unit extdst1 input port src is connected to output of unit vscaler5
71095 * 0b100001..Unit extdst1 input port src is connected to output of unit layerblend0
71096 * 0b100010..Unit extdst1 input port src is connected to output of unit layerblend1
71097 * 0b100011..Unit extdst1 input port src is connected to output of unit layerblend2
71098 * 0b100100..Unit extdst1 input port src is connected to output of unit layerblend3
71099 */
71100#define IRIS_MVPL_EXTDST1_DYNAMIC_extdst1_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_DYNAMIC_extdst1_src_sel_SHIFT)) & IRIS_MVPL_EXTDST1_DYNAMIC_extdst1_src_sel_MASK)
71101/*! @} */
71102
71103/*! @name EXTDST1_REQUEST - ShadowLoadRequest register for endpoint extdst1 */
71104/*! @{ */
71105#define IRIS_MVPL_EXTDST1_REQUEST_extdst1_sel_ShdLdReq_MASK (0x1U)
71106#define IRIS_MVPL_EXTDST1_REQUEST_extdst1_sel_ShdLdReq_SHIFT (0U)
71107/*! extdst1_sel_ShdLdReq - Shadow load request flag for destination extdst1.
71108 */
71109#define IRIS_MVPL_EXTDST1_REQUEST_extdst1_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_REQUEST_extdst1_sel_ShdLdReq_SHIFT)) & IRIS_MVPL_EXTDST1_REQUEST_extdst1_sel_ShdLdReq_MASK)
71110#define IRIS_MVPL_EXTDST1_REQUEST_extdst1_ShdLdReq_MASK (0x7FFEU)
71111#define IRIS_MVPL_EXTDST1_REQUEST_extdst1_ShdLdReq_SHIFT (1U)
71112/*! extdst1_ShdLdReq - Vector of shadow load request flag of all sources for destination extdst1.
71113 * Setting a bit has no effect if the source is currently in a different pipeline than the one of
71114 * destination extdst1.
71115 */
71116#define IRIS_MVPL_EXTDST1_REQUEST_extdst1_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_REQUEST_extdst1_ShdLdReq_SHIFT)) & IRIS_MVPL_EXTDST1_REQUEST_extdst1_ShdLdReq_MASK)
71117/*! @} */
71118
71119/*! @name EXTDST1_TRIGGER - Trigger bits for pixel engine configuration of extdst1 */
71120/*! @{ */
71121#define IRIS_MVPL_EXTDST1_TRIGGER_extdst1_Sync_Trigger_MASK (0x1U)
71122#define IRIS_MVPL_EXTDST1_TRIGGER_extdst1_Sync_Trigger_SHIFT (0U)
71123/*! extdst1_Sync_Trigger - Writing a '1' to this field triggers reconfiguration of the pipeline with endpoint extdst1
71124 */
71125#define IRIS_MVPL_EXTDST1_TRIGGER_extdst1_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_TRIGGER_extdst1_Sync_Trigger_SHIFT)) & IRIS_MVPL_EXTDST1_TRIGGER_extdst1_Sync_Trigger_MASK)
71126#define IRIS_MVPL_EXTDST1_TRIGGER_extdst1_trigger_sequence_complete_MASK (0x10U)
71127#define IRIS_MVPL_EXTDST1_TRIGGER_extdst1_trigger_sequence_complete_SHIFT (4U)
71128/*! extdst1_trigger_sequence_complete - By writing a '1' to this register field, you can trigger the
71129 * extdst1 sequence complete interrupt that will occur as soon as the pipeline with the endpoint
71130 * extdst1 is empty. This interrupt will also occur if the pipeline is already empty when this
71131 * field is written. The interrupt will not occur if this field is not written. The interrupt will
71132 * occur exactly as often as this field is written, assuming that this field is not written
71133 * again until the interrupt has occured after a previous trigger.
71134 */
71135#define IRIS_MVPL_EXTDST1_TRIGGER_extdst1_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST1_TRIGGER_extdst1_trigger_sequence_complete_SHIFT)) & IRIS_MVPL_EXTDST1_TRIGGER_extdst1_trigger_sequence_complete_MASK)
71136/*! @} */
71137
71138/*! @name EXTDST512_STATUS - Status information for pixel engine configuration of extdst1 */
71139/*! @{ */
71140#define IRIS_MVPL_EXTDST512_STATUS_extdst1_pipeline_status_MASK (0x3U)
71141#define IRIS_MVPL_EXTDST512_STATUS_extdst1_pipeline_status_SHIFT (0U)
71142/*! extdst1_pipeline_status - Status of pipeline with endpoint extdst1
71143 * 0b00..Pipeline with endpoint extdst1 is empty
71144 * 0b01..Pipeline with endpoint extdst1 is currently processing one operation
71145 * 0b10..Pipeline with endpoint extdst1 is currently processing one operation with a second one already kicked to be processed afterwards
71146 * 0b11..reserved
71147 */
71148#define IRIS_MVPL_EXTDST512_STATUS_extdst1_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST512_STATUS_extdst1_pipeline_status_SHIFT)) & IRIS_MVPL_EXTDST512_STATUS_extdst1_pipeline_status_MASK)
71149#define IRIS_MVPL_EXTDST512_STATUS_extdst1_sync_busy_MASK (0x100U)
71150#define IRIS_MVPL_EXTDST512_STATUS_extdst1_sync_busy_SHIFT (8U)
71151/*! extdst1_sync_busy - Synchronization busy status of extdst1 endpoint
71152 * 0b0..extdst1 synchronizer is idle
71153 * 0b1..extdst1 synchronizer is busy
71154 */
71155#define IRIS_MVPL_EXTDST512_STATUS_extdst1_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST512_STATUS_extdst1_sync_busy_SHIFT)) & IRIS_MVPL_EXTDST512_STATUS_extdst1_sync_busy_MASK)
71156/*! @} */
71157
71158/*! @name CONSTFRAME_LOCKUNLOCK - Register to change the protection status of this address block. */
71159/*! @{ */
71160#define IRIS_MVPL_CONSTFRAME_LOCKUNLOCK_constframe5_LockUnlock_MASK (0xFFFFFFFFU)
71161#define IRIS_MVPL_CONSTFRAME_LOCKUNLOCK_constframe5_LockUnlock_SHIFT (0U)
71162/*! constframe5_LockUnlock - The protection status is changed by writing one of the following key values to this field:
71163 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
71164 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
71165 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
71166 * 0b10110101111000100100011001101110..Disables privilege protection.
71167 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
71168 */
71169#define IRIS_MVPL_CONSTFRAME_LOCKUNLOCK_constframe5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME_LOCKUNLOCK_constframe5_LockUnlock_SHIFT)) & IRIS_MVPL_CONSTFRAME_LOCKUNLOCK_constframe5_LockUnlock_MASK)
71170/*! @} */
71171
71172/*! @name CONSTFRAME_LOCKSTATUS - Protection status of this address block. */
71173/*! @{ */
71174#define IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_LockStatus_MASK (0x1U)
71175#define IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_LockStatus_SHIFT (0U)
71176/*! constframe5_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
71177 */
71178#define IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_LockStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_LockStatus_MASK)
71179#define IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_PrivilegeStatus_MASK (0x10U)
71180#define IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_PrivilegeStatus_SHIFT (4U)
71181/*! constframe5_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
71182 */
71183#define IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_PrivilegeStatus_MASK)
71184#define IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_FreezeStatus_MASK (0x100U)
71185#define IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_FreezeStatus_SHIFT (8U)
71186/*! constframe5_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
71187 */
71188#define IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_FreezeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME_LOCKSTATUS_constframe5_FreezeStatus_MASK)
71189/*! @} */
71190
71191/*! @name CONSTFRAME_STATUS - Status information for pixel engine configuration of constframe5 */
71192/*! @{ */
71193#define IRIS_MVPL_CONSTFRAME_STATUS_constframe5_sel_MASK (0x70000U)
71194#define IRIS_MVPL_CONSTFRAME_STATUS_constframe5_sel_SHIFT (16U)
71195/*! constframe5_sel - Status of the connection of the constframe5 module
71196 * 0b000..constframe5 module is not used
71197 * 0b001..constframe5 module is used from store9 processing path
71198 * 0b010..constframe5 module is used from extdst0 processing path
71199 * 0b011..constframe5 module is used from extdst4 processing path
71200 * 0b100..constframe5 module is used from extdst1 processing path
71201 * 0b101..constframe5 module is used from extdst5 processing path
71202 */
71203#define IRIS_MVPL_CONSTFRAME_STATUS_constframe5_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME_STATUS_constframe5_sel_SHIFT)) & IRIS_MVPL_CONSTFRAME_STATUS_constframe5_sel_MASK)
71204/*! @} */
71205
71206/*! @name EXTDST544_LOCKUNLOCK - Register to change the protection status of this address block. */
71207/*! @{ */
71208#define IRIS_MVPL_EXTDST544_LOCKUNLOCK_extdst5_LockUnlock_MASK (0xFFFFFFFFU)
71209#define IRIS_MVPL_EXTDST544_LOCKUNLOCK_extdst5_LockUnlock_SHIFT (0U)
71210/*! extdst5_LockUnlock - The protection status is changed by writing one of the following key values to this field:
71211 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
71212 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
71213 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
71214 * 0b10110101111000100100011001101110..Disables privilege protection.
71215 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
71216 */
71217#define IRIS_MVPL_EXTDST544_LOCKUNLOCK_extdst5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST544_LOCKUNLOCK_extdst5_LockUnlock_SHIFT)) & IRIS_MVPL_EXTDST544_LOCKUNLOCK_extdst5_LockUnlock_MASK)
71218/*! @} */
71219
71220/*! @name EXTDST544_LOCKSTATUS - Protection status of this address block. */
71221/*! @{ */
71222#define IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_LockStatus_MASK (0x1U)
71223#define IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_LockStatus_SHIFT (0U)
71224/*! extdst5_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
71225 */
71226#define IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_LockStatus_SHIFT)) & IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_LockStatus_MASK)
71227#define IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_PrivilegeStatus_MASK (0x10U)
71228#define IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_PrivilegeStatus_SHIFT (4U)
71229/*! extdst5_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
71230 */
71231#define IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_PrivilegeStatus_MASK)
71232#define IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_FreezeStatus_MASK (0x100U)
71233#define IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_FreezeStatus_SHIFT (8U)
71234/*! extdst5_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
71235 */
71236#define IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTDST544_LOCKSTATUS_extdst5_FreezeStatus_MASK)
71237/*! @} */
71238
71239/*! @name EXTDST5_STATIC - Static pixel engine configuration for extdst5 */
71240/*! @{ */
71241#define IRIS_MVPL_EXTDST5_STATIC_extdst5_ShdEn_MASK (0x1U)
71242#define IRIS_MVPL_EXTDST5_STATIC_extdst5_ShdEn_SHIFT (0U)
71243/*! extdst5_ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed) for
71244 * pixelbus configuration of pipeline with endpoint extdst5.
71245 */
71246#define IRIS_MVPL_EXTDST5_STATIC_extdst5_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_STATIC_extdst5_ShdEn_SHIFT)) & IRIS_MVPL_EXTDST5_STATIC_extdst5_ShdEn_MASK)
71247#define IRIS_MVPL_EXTDST5_STATIC_extdst5_powerdown_MASK (0x10U)
71248#define IRIS_MVPL_EXTDST5_STATIC_extdst5_powerdown_SHIFT (4U)
71249/*! extdst5_powerdown - Set this to 1 to activate powerdown or to 0 to deactivate powerdown for the extdst5 endpoint.
71250 */
71251#define IRIS_MVPL_EXTDST5_STATIC_extdst5_powerdown(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_STATIC_extdst5_powerdown_SHIFT)) & IRIS_MVPL_EXTDST5_STATIC_extdst5_powerdown_MASK)
71252#define IRIS_MVPL_EXTDST5_STATIC_extdst5_Sync_Mode_MASK (0x100U)
71253#define IRIS_MVPL_EXTDST5_STATIC_extdst5_Sync_Mode_SHIFT (8U)
71254/*! extdst5_Sync_Mode - Synchronization mode for extdst5 pipeline endpoint synchronizer
71255 * 0b0..Reconfig pipeline after explicit trigger
71256 * 0b1..Reconfig pipeline after every kick when idle
71257 */
71258#define IRIS_MVPL_EXTDST5_STATIC_extdst5_Sync_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_STATIC_extdst5_Sync_Mode_SHIFT)) & IRIS_MVPL_EXTDST5_STATIC_extdst5_Sync_Mode_MASK)
71259#define IRIS_MVPL_EXTDST5_STATIC_extdst5_SW_Reset_MASK (0x800U)
71260#define IRIS_MVPL_EXTDST5_STATIC_extdst5_SW_Reset_SHIFT (11U)
71261/*! extdst5_SW_Reset - Software reset for extdst5 synchronizer, for debug purposes only
71262 * 0b0..Normal Operation
71263 * 0b1..Software Reset
71264 */
71265#define IRIS_MVPL_EXTDST5_STATIC_extdst5_SW_Reset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_STATIC_extdst5_SW_Reset_SHIFT)) & IRIS_MVPL_EXTDST5_STATIC_extdst5_SW_Reset_MASK)
71266#define IRIS_MVPL_EXTDST5_STATIC_extdst5_div_MASK (0xFF0000U)
71267#define IRIS_MVPL_EXTDST5_STATIC_extdst5_div_SHIFT (16U)
71268/*! extdst5_div - extdst5 clock dividing factor (ratio is register_value/128, values above 128 are
71269 * reserved). If a value smaller than 0x80 is used, than the *_clken registers of all enabled
71270 * submodules have to be set to AUTOMATIC. The value 0x0 disables the clock while the value 0x80 sets
71271 * the clock at full speed.
71272 */
71273#define IRIS_MVPL_EXTDST5_STATIC_extdst5_div(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_STATIC_extdst5_div_SHIFT)) & IRIS_MVPL_EXTDST5_STATIC_extdst5_div_MASK)
71274/*! @} */
71275
71276/*! @name EXTDST5_DYNAMIC - Dynamic pixel engine configuration for extdst5 */
71277/*! @{ */
71278#define IRIS_MVPL_EXTDST5_DYNAMIC_extdst5_src_sel_MASK (0x3FU)
71279#define IRIS_MVPL_EXTDST5_DYNAMIC_extdst5_src_sel_SHIFT (0U)
71280/*! extdst5_src_sel - Selection of the source for the src input of the extdst5 module
71281 * 0b000000..Unit extdst5 input port src is disabled
71282 * 0b001010..Unit extdst5 input port src is connected to output of unit blitblend9
71283 * 0b001100..Unit extdst5 input port src is connected to output of unit constframe0
71284 * 0b001110..Unit extdst5 input port src is connected to output of unit constframe4
71285 * 0b000000..Unit extdst5 input port src is connected to output of unit constframe1
71286 * 0b010010..Unit extdst5 input port src is connected to output of unit constframe5
71287 * 0b011011..Unit extdst5 input port src is connected to output of unit matrix4
71288 * 0b011100..Unit extdst5 input port src is connected to output of unit hscaler4
71289 * 0b011101..Unit extdst5 input port src is connected to output of unit vscaler4
71290 * 0b011110..Unit extdst5 input port src is connected to output of unit matrix5
71291 * 0b011111..Unit extdst5 input port src is connected to output of unit hscaler5
71292 * 0b100000..Unit extdst5 input port src is connected to output of unit vscaler5
71293 * 0b100001..Unit extdst5 input port src is connected to output of unit layerblend0
71294 * 0b100010..Unit extdst5 input port src is connected to output of unit layerblend1
71295 * 0b100011..Unit extdst5 input port src is connected to output of unit layerblend2
71296 * 0b100100..Unit extdst5 input port src is connected to output of unit layerblend3
71297 */
71298#define IRIS_MVPL_EXTDST5_DYNAMIC_extdst5_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_DYNAMIC_extdst5_src_sel_SHIFT)) & IRIS_MVPL_EXTDST5_DYNAMIC_extdst5_src_sel_MASK)
71299/*! @} */
71300
71301/*! @name EXTDST5_REQUEST - ShadowLoadRequest register for endpoint extdst5 */
71302/*! @{ */
71303#define IRIS_MVPL_EXTDST5_REQUEST_extdst5_sel_ShdLdReq_MASK (0x1U)
71304#define IRIS_MVPL_EXTDST5_REQUEST_extdst5_sel_ShdLdReq_SHIFT (0U)
71305/*! extdst5_sel_ShdLdReq - Shadow load request flag for destination extdst5.
71306 */
71307#define IRIS_MVPL_EXTDST5_REQUEST_extdst5_sel_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_REQUEST_extdst5_sel_ShdLdReq_SHIFT)) & IRIS_MVPL_EXTDST5_REQUEST_extdst5_sel_ShdLdReq_MASK)
71308#define IRIS_MVPL_EXTDST5_REQUEST_extdst5_ShdLdReq_MASK (0x7FFEU)
71309#define IRIS_MVPL_EXTDST5_REQUEST_extdst5_ShdLdReq_SHIFT (1U)
71310/*! extdst5_ShdLdReq - Vector of shadow load request flag of all sources for destination extdst5.
71311 * Setting a bit has no effect if the source is currently in a different pipeline than the one of
71312 * destination extdst5.
71313 */
71314#define IRIS_MVPL_EXTDST5_REQUEST_extdst5_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_REQUEST_extdst5_ShdLdReq_SHIFT)) & IRIS_MVPL_EXTDST5_REQUEST_extdst5_ShdLdReq_MASK)
71315/*! @} */
71316
71317/*! @name EXTDST5_TRIGGER - Trigger bits for pixel engine configuration of extdst5 */
71318/*! @{ */
71319#define IRIS_MVPL_EXTDST5_TRIGGER_extdst5_Sync_Trigger_MASK (0x1U)
71320#define IRIS_MVPL_EXTDST5_TRIGGER_extdst5_Sync_Trigger_SHIFT (0U)
71321/*! extdst5_Sync_Trigger - Writing a '1' to this field triggers reconfiguration of the pipeline with endpoint extdst5
71322 */
71323#define IRIS_MVPL_EXTDST5_TRIGGER_extdst5_Sync_Trigger(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_TRIGGER_extdst5_Sync_Trigger_SHIFT)) & IRIS_MVPL_EXTDST5_TRIGGER_extdst5_Sync_Trigger_MASK)
71324#define IRIS_MVPL_EXTDST5_TRIGGER_extdst5_trigger_sequence_complete_MASK (0x10U)
71325#define IRIS_MVPL_EXTDST5_TRIGGER_extdst5_trigger_sequence_complete_SHIFT (4U)
71326/*! extdst5_trigger_sequence_complete - By writing a '1' to this register field, you can trigger the
71327 * extdst5 sequence complete interrupt that will occur as soon as the pipeline with the endpoint
71328 * extdst5 is empty. This interrupt will also occur if the pipeline is already empty when this
71329 * field is written. The interrupt will not occur if this field is not written. The interrupt will
71330 * occur exactly as often as this field is written, assuming that this field is not written
71331 * again until the interrupt has occured after a previous trigger.
71332 */
71333#define IRIS_MVPL_EXTDST5_TRIGGER_extdst5_trigger_sequence_complete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST5_TRIGGER_extdst5_trigger_sequence_complete_SHIFT)) & IRIS_MVPL_EXTDST5_TRIGGER_extdst5_trigger_sequence_complete_MASK)
71334/*! @} */
71335
71336/*! @name EXTDST544_STATUS - Status information for pixel engine configuration of extdst5 */
71337/*! @{ */
71338#define IRIS_MVPL_EXTDST544_STATUS_extdst5_pipeline_status_MASK (0x3U)
71339#define IRIS_MVPL_EXTDST544_STATUS_extdst5_pipeline_status_SHIFT (0U)
71340/*! extdst5_pipeline_status - Status of pipeline with endpoint extdst5
71341 * 0b00..Pipeline with endpoint extdst5 is empty
71342 * 0b01..Pipeline with endpoint extdst5 is currently processing one operation
71343 * 0b10..Pipeline with endpoint extdst5 is currently processing one operation with a second one already kicked to be processed afterwards
71344 * 0b11..reserved
71345 */
71346#define IRIS_MVPL_EXTDST544_STATUS_extdst5_pipeline_status(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST544_STATUS_extdst5_pipeline_status_SHIFT)) & IRIS_MVPL_EXTDST544_STATUS_extdst5_pipeline_status_MASK)
71347#define IRIS_MVPL_EXTDST544_STATUS_extdst5_sync_busy_MASK (0x100U)
71348#define IRIS_MVPL_EXTDST544_STATUS_extdst5_sync_busy_SHIFT (8U)
71349/*! extdst5_sync_busy - Synchronization busy status of extdst5 endpoint
71350 * 0b0..extdst5 synchronizer is idle
71351 * 0b1..extdst5 synchronizer is busy
71352 */
71353#define IRIS_MVPL_EXTDST544_STATUS_extdst5_sync_busy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST544_STATUS_extdst5_sync_busy_SHIFT)) & IRIS_MVPL_EXTDST544_STATUS_extdst5_sync_busy_MASK)
71354/*! @} */
71355
71356/*! @name FETCHWARP608_LOCKUNLOCK - Register to change the protection status of this address block. */
71357/*! @{ */
71358#define IRIS_MVPL_FETCHWARP608_LOCKUNLOCK_fetchwarp2_LockUnlock_MASK (0xFFFFFFFFU)
71359#define IRIS_MVPL_FETCHWARP608_LOCKUNLOCK_fetchwarp2_LockUnlock_SHIFT (0U)
71360/*! fetchwarp2_LockUnlock - The protection status is changed by writing one of the following key values to this field:
71361 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
71362 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
71363 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
71364 * 0b10110101111000100100011001101110..Disables privilege protection.
71365 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
71366 */
71367#define IRIS_MVPL_FETCHWARP608_LOCKUNLOCK_fetchwarp2_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP608_LOCKUNLOCK_fetchwarp2_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHWARP608_LOCKUNLOCK_fetchwarp2_LockUnlock_MASK)
71368/*! @} */
71369
71370/*! @name FETCHWARP608_LOCKSTATUS - Protection status of this address block. */
71371/*! @{ */
71372#define IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_LockStatus_MASK (0x1U)
71373#define IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_LockStatus_SHIFT (0U)
71374/*! fetchwarp2_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
71375 */
71376#define IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_LockStatus_SHIFT)) & IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_LockStatus_MASK)
71377#define IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_PrivilegeStatus_MASK (0x10U)
71378#define IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_PrivilegeStatus_SHIFT (4U)
71379/*! fetchwarp2_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
71380 */
71381#define IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_PrivilegeStatus_MASK)
71382#define IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_FreezeStatus_MASK (0x100U)
71383#define IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_FreezeStatus_SHIFT (8U)
71384/*! fetchwarp2_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
71385 */
71386#define IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHWARP608_LOCKSTATUS_fetchwarp2_FreezeStatus_MASK)
71387/*! @} */
71388
71389/*! @name FETCHWARP608_DYNAMIC - Dynamic pixel engine configuration for fetchwarp2 */
71390/*! @{ */
71391#define IRIS_MVPL_FETCHWARP608_DYNAMIC_fetchwarp2_src_sel_MASK (0x3FU)
71392#define IRIS_MVPL_FETCHWARP608_DYNAMIC_fetchwarp2_src_sel_SHIFT (0U)
71393/*! fetchwarp2_src_sel - Selection of the source for the src input of the fetchwarp2 module
71394 * 0b000000..Unit fetchwarp2 input port src is disabled
71395 * 0b010101..Unit fetchwarp2 input port src is connected to output of unit fetcheco2
71396 */
71397#define IRIS_MVPL_FETCHWARP608_DYNAMIC_fetchwarp2_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP608_DYNAMIC_fetchwarp2_src_sel_SHIFT)) & IRIS_MVPL_FETCHWARP608_DYNAMIC_fetchwarp2_src_sel_MASK)
71398/*! @} */
71399
71400/*! @name FETCHWARP608_STATUS - Status information for pixel engine configuration of fetchwarp2 */
71401/*! @{ */
71402#define IRIS_MVPL_FETCHWARP608_STATUS_fetchwarp2_sel_MASK (0x70000U)
71403#define IRIS_MVPL_FETCHWARP608_STATUS_fetchwarp2_sel_SHIFT (16U)
71404/*! fetchwarp2_sel - Status of the connection of the fetchwarp2 module
71405 * 0b000..fetchwarp2 module is not used
71406 * 0b001..fetchwarp2 module is used from store9 processing path
71407 * 0b010..fetchwarp2 module is used from extdst0 processing path
71408 * 0b011..fetchwarp2 module is used from extdst4 processing path
71409 * 0b100..fetchwarp2 module is used from extdst1 processing path
71410 * 0b101..fetchwarp2 module is used from extdst5 processing path
71411 */
71412#define IRIS_MVPL_FETCHWARP608_STATUS_fetchwarp2_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP608_STATUS_fetchwarp2_sel_SHIFT)) & IRIS_MVPL_FETCHWARP608_STATUS_fetchwarp2_sel_MASK)
71413/*! @} */
71414
71415/*! @name FETCHECO624_LOCKUNLOCK - Register to change the protection status of this address block. */
71416/*! @{ */
71417#define IRIS_MVPL_FETCHECO624_LOCKUNLOCK_fetcheco2_LockUnlock_MASK (0xFFFFFFFFU)
71418#define IRIS_MVPL_FETCHECO624_LOCKUNLOCK_fetcheco2_LockUnlock_SHIFT (0U)
71419/*! fetcheco2_LockUnlock - The protection status is changed by writing one of the following key values to this field:
71420 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
71421 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
71422 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
71423 * 0b10110101111000100100011001101110..Disables privilege protection.
71424 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
71425 */
71426#define IRIS_MVPL_FETCHECO624_LOCKUNLOCK_fetcheco2_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO624_LOCKUNLOCK_fetcheco2_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHECO624_LOCKUNLOCK_fetcheco2_LockUnlock_MASK)
71427/*! @} */
71428
71429/*! @name FETCHECO624_LOCKSTATUS - Protection status of this address block. */
71430/*! @{ */
71431#define IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_LockStatus_MASK (0x1U)
71432#define IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_LockStatus_SHIFT (0U)
71433/*! fetcheco2_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
71434 */
71435#define IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_LockStatus_SHIFT)) & IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_LockStatus_MASK)
71436#define IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_PrivilegeStatus_MASK (0x10U)
71437#define IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_PrivilegeStatus_SHIFT (4U)
71438/*! fetcheco2_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
71439 */
71440#define IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_PrivilegeStatus_MASK)
71441#define IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_FreezeStatus_MASK (0x100U)
71442#define IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_FreezeStatus_SHIFT (8U)
71443/*! fetcheco2_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
71444 */
71445#define IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHECO624_LOCKSTATUS_fetcheco2_FreezeStatus_MASK)
71446/*! @} */
71447
71448/*! @name FETCHECO2_STATUS - Status information for pixel engine configuration of fetcheco2 */
71449/*! @{ */
71450#define IRIS_MVPL_FETCHECO2_STATUS_fetcheco2_sel_MASK (0x70000U)
71451#define IRIS_MVPL_FETCHECO2_STATUS_fetcheco2_sel_SHIFT (16U)
71452/*! fetcheco2_sel - Status of the connection of the fetcheco2 module
71453 * 0b000..fetcheco2 module is not used
71454 * 0b001..fetcheco2 module is used from store9 processing path
71455 * 0b010..fetcheco2 module is used from extdst0 processing path
71456 * 0b011..fetcheco2 module is used from extdst4 processing path
71457 * 0b100..fetcheco2 module is used from extdst1 processing path
71458 * 0b101..fetcheco2 module is used from extdst5 processing path
71459 */
71460#define IRIS_MVPL_FETCHECO2_STATUS_fetcheco2_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO2_STATUS_fetcheco2_sel_SHIFT)) & IRIS_MVPL_FETCHECO2_STATUS_fetcheco2_sel_MASK)
71461/*! @} */
71462
71463/*! @name FETCHDECODE0_LOCKUNLOCK - Register to change the protection status of this address block. */
71464/*! @{ */
71465#define IRIS_MVPL_FETCHDECODE0_LOCKUNLOCK_fetchdecode0_LockUnlock_MASK (0xFFFFFFFFU)
71466#define IRIS_MVPL_FETCHDECODE0_LOCKUNLOCK_fetchdecode0_LockUnlock_SHIFT (0U)
71467/*! fetchdecode0_LockUnlock - The protection status is changed by writing one of the following key values to this field:
71468 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
71469 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
71470 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
71471 * 0b10110101111000100100011001101110..Disables privilege protection.
71472 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
71473 */
71474#define IRIS_MVPL_FETCHDECODE0_LOCKUNLOCK_fetchdecode0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LOCKUNLOCK_fetchdecode0_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LOCKUNLOCK_fetchdecode0_LockUnlock_MASK)
71475/*! @} */
71476
71477/*! @name FETCHDECODE0_LOCKSTATUS - Protection status of this address block. */
71478/*! @{ */
71479#define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_LockStatus_MASK (0x1U)
71480#define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_LockStatus_SHIFT (0U)
71481/*! fetchdecode0_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
71482 */
71483#define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_LockStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_LockStatus_MASK)
71484#define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_PrivilegeStatus_MASK (0x10U)
71485#define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_PrivilegeStatus_SHIFT (4U)
71486/*! fetchdecode0_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
71487 */
71488#define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_PrivilegeStatus_MASK)
71489#define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_FreezeStatus_MASK (0x100U)
71490#define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_FreezeStatus_SHIFT (8U)
71491/*! fetchdecode0_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
71492 */
71493#define IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE0_LOCKSTATUS_fetchdecode0_FreezeStatus_MASK)
71494/*! @} */
71495
71496/*! @name FETCHDECODE0_DYNAMIC - Dynamic pixel engine configuration for fetchdecode0 */
71497/*! @{ */
71498#define IRIS_MVPL_FETCHDECODE0_DYNAMIC_fetchdecode0_src_sel_MASK (0x3FU)
71499#define IRIS_MVPL_FETCHDECODE0_DYNAMIC_fetchdecode0_src_sel_SHIFT (0U)
71500/*! fetchdecode0_src_sel - Selection of the source for the src input of the fetchdecode0 module
71501 * 0b000000..Unit fetchdecode0 input port src is disabled
71502 * 0b010100..Unit fetchdecode0 input port src is connected to output of unit fetchwarp2
71503 * 0b010111..Unit fetchdecode0 input port src is connected to output of unit fetcheco0
71504 * 0b011000..Unit fetchdecode0 input port src is connected to output of unit fetchdecode1
71505 */
71506#define IRIS_MVPL_FETCHDECODE0_DYNAMIC_fetchdecode0_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_DYNAMIC_fetchdecode0_src_sel_SHIFT)) & IRIS_MVPL_FETCHDECODE0_DYNAMIC_fetchdecode0_src_sel_MASK)
71507/*! @} */
71508
71509/*! @name FETCHDECODE0_STATUS - Status information for pixel engine configuration of fetchdecode0 */
71510/*! @{ */
71511#define IRIS_MVPL_FETCHDECODE0_STATUS_fetchdecode0_sel_MASK (0x70000U)
71512#define IRIS_MVPL_FETCHDECODE0_STATUS_fetchdecode0_sel_SHIFT (16U)
71513/*! fetchdecode0_sel - Status of the connection of the fetchdecode0 module
71514 * 0b000..fetchdecode0 module is not used
71515 * 0b001..fetchdecode0 module is used from store9 processing path
71516 * 0b010..fetchdecode0 module is used from extdst0 processing path
71517 * 0b011..fetchdecode0 module is used from extdst4 processing path
71518 * 0b100..fetchdecode0 module is used from extdst1 processing path
71519 * 0b101..fetchdecode0 module is used from extdst5 processing path
71520 */
71521#define IRIS_MVPL_FETCHDECODE0_STATUS_fetchdecode0_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE0_STATUS_fetchdecode0_sel_SHIFT)) & IRIS_MVPL_FETCHDECODE0_STATUS_fetchdecode0_sel_MASK)
71522/*! @} */
71523
71524/*! @name FETCHECO656_LOCKUNLOCK - Register to change the protection status of this address block. */
71525/*! @{ */
71526#define IRIS_MVPL_FETCHECO656_LOCKUNLOCK_fetcheco0_LockUnlock_MASK (0xFFFFFFFFU)
71527#define IRIS_MVPL_FETCHECO656_LOCKUNLOCK_fetcheco0_LockUnlock_SHIFT (0U)
71528/*! fetcheco0_LockUnlock - The protection status is changed by writing one of the following key values to this field:
71529 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
71530 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
71531 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
71532 * 0b10110101111000100100011001101110..Disables privilege protection.
71533 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
71534 */
71535#define IRIS_MVPL_FETCHECO656_LOCKUNLOCK_fetcheco0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO656_LOCKUNLOCK_fetcheco0_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHECO656_LOCKUNLOCK_fetcheco0_LockUnlock_MASK)
71536/*! @} */
71537
71538/*! @name FETCHECO656_LOCKSTATUS - Protection status of this address block. */
71539/*! @{ */
71540#define IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_LockStatus_MASK (0x1U)
71541#define IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_LockStatus_SHIFT (0U)
71542/*! fetcheco0_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
71543 */
71544#define IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_LockStatus_SHIFT)) & IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_LockStatus_MASK)
71545#define IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_PrivilegeStatus_MASK (0x10U)
71546#define IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_PrivilegeStatus_SHIFT (4U)
71547/*! fetcheco0_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
71548 */
71549#define IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_PrivilegeStatus_MASK)
71550#define IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_FreezeStatus_MASK (0x100U)
71551#define IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_FreezeStatus_SHIFT (8U)
71552/*! fetcheco0_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
71553 */
71554#define IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHECO656_LOCKSTATUS_fetcheco0_FreezeStatus_MASK)
71555/*! @} */
71556
71557/*! @name FETCHECO0_STATUS - Status information for pixel engine configuration of fetcheco0 */
71558/*! @{ */
71559#define IRIS_MVPL_FETCHECO0_STATUS_fetcheco0_sel_MASK (0x70000U)
71560#define IRIS_MVPL_FETCHECO0_STATUS_fetcheco0_sel_SHIFT (16U)
71561/*! fetcheco0_sel - Status of the connection of the fetcheco0 module
71562 * 0b000..fetcheco0 module is not used
71563 * 0b001..fetcheco0 module is used from store9 processing path
71564 * 0b010..fetcheco0 module is used from extdst0 processing path
71565 * 0b011..fetcheco0 module is used from extdst4 processing path
71566 * 0b100..fetcheco0 module is used from extdst1 processing path
71567 * 0b101..fetcheco0 module is used from extdst5 processing path
71568 */
71569#define IRIS_MVPL_FETCHECO0_STATUS_fetcheco0_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO0_STATUS_fetcheco0_sel_SHIFT)) & IRIS_MVPL_FETCHECO0_STATUS_fetcheco0_sel_MASK)
71570/*! @} */
71571
71572/*! @name FETCHDECODE672_LOCKUNLOCK - Register to change the protection status of this address block. */
71573/*! @{ */
71574#define IRIS_MVPL_FETCHDECODE672_LOCKUNLOCK_fetchdecode1_LockUnlock_MASK (0xFFFFFFFFU)
71575#define IRIS_MVPL_FETCHDECODE672_LOCKUNLOCK_fetchdecode1_LockUnlock_SHIFT (0U)
71576/*! fetchdecode1_LockUnlock - The protection status is changed by writing one of the following key values to this field:
71577 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
71578 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
71579 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
71580 * 0b10110101111000100100011001101110..Disables privilege protection.
71581 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
71582 */
71583#define IRIS_MVPL_FETCHDECODE672_LOCKUNLOCK_fetchdecode1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE672_LOCKUNLOCK_fetchdecode1_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHDECODE672_LOCKUNLOCK_fetchdecode1_LockUnlock_MASK)
71584/*! @} */
71585
71586/*! @name FETCHDECODE672_LOCKSTATUS - Protection status of this address block. */
71587/*! @{ */
71588#define IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_LockStatus_MASK (0x1U)
71589#define IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_LockStatus_SHIFT (0U)
71590/*! fetchdecode1_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
71591 */
71592#define IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_LockStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_LockStatus_MASK)
71593#define IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_PrivilegeStatus_MASK (0x10U)
71594#define IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_PrivilegeStatus_SHIFT (4U)
71595/*! fetchdecode1_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
71596 */
71597#define IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_PrivilegeStatus_MASK)
71598#define IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_FreezeStatus_MASK (0x100U)
71599#define IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_FreezeStatus_SHIFT (8U)
71600/*! fetchdecode1_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
71601 */
71602#define IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE672_LOCKSTATUS_fetchdecode1_FreezeStatus_MASK)
71603/*! @} */
71604
71605/*! @name FETCHDECODE1_DYNAMIC - Dynamic pixel engine configuration for fetchdecode1 */
71606/*! @{ */
71607#define IRIS_MVPL_FETCHDECODE1_DYNAMIC_fetchdecode1_src_sel_MASK (0x3FU)
71608#define IRIS_MVPL_FETCHDECODE1_DYNAMIC_fetchdecode1_src_sel_SHIFT (0U)
71609/*! fetchdecode1_src_sel - Selection of the source for the src input of the fetchdecode1 module
71610 * 0b000000..Unit fetchdecode1 input port src is disabled
71611 * 0b010100..Unit fetchdecode1 input port src is connected to output of unit fetchwarp2
71612 * 0b010110..Unit fetchdecode1 input port src is connected to output of unit fetchdecode0
71613 * 0b011001..Unit fetchdecode1 input port src is connected to output of unit fetcheco1
71614 */
71615#define IRIS_MVPL_FETCHDECODE1_DYNAMIC_fetchdecode1_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_DYNAMIC_fetchdecode1_src_sel_SHIFT)) & IRIS_MVPL_FETCHDECODE1_DYNAMIC_fetchdecode1_src_sel_MASK)
71616/*! @} */
71617
71618/*! @name FETCHDECODE1_STATUS - Status information for pixel engine configuration of fetchdecode1 */
71619/*! @{ */
71620#define IRIS_MVPL_FETCHDECODE1_STATUS_fetchdecode1_sel_MASK (0x70000U)
71621#define IRIS_MVPL_FETCHDECODE1_STATUS_fetchdecode1_sel_SHIFT (16U)
71622/*! fetchdecode1_sel - Status of the connection of the fetchdecode1 module
71623 * 0b000..fetchdecode1 module is not used
71624 * 0b001..fetchdecode1 module is used from store9 processing path
71625 * 0b010..fetchdecode1 module is used from extdst0 processing path
71626 * 0b011..fetchdecode1 module is used from extdst4 processing path
71627 * 0b100..fetchdecode1 module is used from extdst1 processing path
71628 * 0b101..fetchdecode1 module is used from extdst5 processing path
71629 */
71630#define IRIS_MVPL_FETCHDECODE1_STATUS_fetchdecode1_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE1_STATUS_fetchdecode1_sel_SHIFT)) & IRIS_MVPL_FETCHDECODE1_STATUS_fetchdecode1_sel_MASK)
71631/*! @} */
71632
71633/*! @name FETCHECO688_LOCKUNLOCK - Register to change the protection status of this address block. */
71634/*! @{ */
71635#define IRIS_MVPL_FETCHECO688_LOCKUNLOCK_fetcheco1_LockUnlock_MASK (0xFFFFFFFFU)
71636#define IRIS_MVPL_FETCHECO688_LOCKUNLOCK_fetcheco1_LockUnlock_SHIFT (0U)
71637/*! fetcheco1_LockUnlock - The protection status is changed by writing one of the following key values to this field:
71638 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
71639 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
71640 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
71641 * 0b10110101111000100100011001101110..Disables privilege protection.
71642 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
71643 */
71644#define IRIS_MVPL_FETCHECO688_LOCKUNLOCK_fetcheco1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO688_LOCKUNLOCK_fetcheco1_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHECO688_LOCKUNLOCK_fetcheco1_LockUnlock_MASK)
71645/*! @} */
71646
71647/*! @name FETCHECO688_LOCKSTATUS - Protection status of this address block. */
71648/*! @{ */
71649#define IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_LockStatus_MASK (0x1U)
71650#define IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_LockStatus_SHIFT (0U)
71651/*! fetcheco1_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
71652 */
71653#define IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_LockStatus_SHIFT)) & IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_LockStatus_MASK)
71654#define IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_PrivilegeStatus_MASK (0x10U)
71655#define IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_PrivilegeStatus_SHIFT (4U)
71656/*! fetcheco1_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
71657 */
71658#define IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_PrivilegeStatus_MASK)
71659#define IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_FreezeStatus_MASK (0x100U)
71660#define IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_FreezeStatus_SHIFT (8U)
71661/*! fetcheco1_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
71662 */
71663#define IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHECO688_LOCKSTATUS_fetcheco1_FreezeStatus_MASK)
71664/*! @} */
71665
71666/*! @name FETCHECO1_STATUS - Status information for pixel engine configuration of fetcheco1 */
71667/*! @{ */
71668#define IRIS_MVPL_FETCHECO1_STATUS_fetcheco1_sel_MASK (0x70000U)
71669#define IRIS_MVPL_FETCHECO1_STATUS_fetcheco1_sel_SHIFT (16U)
71670/*! fetcheco1_sel - Status of the connection of the fetcheco1 module
71671 * 0b000..fetcheco1 module is not used
71672 * 0b001..fetcheco1 module is used from store9 processing path
71673 * 0b010..fetcheco1 module is used from extdst0 processing path
71674 * 0b011..fetcheco1 module is used from extdst4 processing path
71675 * 0b100..fetcheco1 module is used from extdst1 processing path
71676 * 0b101..fetcheco1 module is used from extdst5 processing path
71677 */
71678#define IRIS_MVPL_FETCHECO1_STATUS_fetcheco1_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO1_STATUS_fetcheco1_sel_SHIFT)) & IRIS_MVPL_FETCHECO1_STATUS_fetcheco1_sel_MASK)
71679/*! @} */
71680
71681/*! @name FETCHLAYER704_LOCKUNLOCK - Register to change the protection status of this address block. */
71682/*! @{ */
71683#define IRIS_MVPL_FETCHLAYER704_LOCKUNLOCK_fetchlayer0_LockUnlock_MASK (0xFFFFFFFFU)
71684#define IRIS_MVPL_FETCHLAYER704_LOCKUNLOCK_fetchlayer0_LockUnlock_SHIFT (0U)
71685/*! fetchlayer0_LockUnlock - The protection status is changed by writing one of the following key values to this field:
71686 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
71687 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
71688 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
71689 * 0b10110101111000100100011001101110..Disables privilege protection.
71690 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
71691 */
71692#define IRIS_MVPL_FETCHLAYER704_LOCKUNLOCK_fetchlayer0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER704_LOCKUNLOCK_fetchlayer0_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHLAYER704_LOCKUNLOCK_fetchlayer0_LockUnlock_MASK)
71693/*! @} */
71694
71695/*! @name FETCHLAYER704_LOCKSTATUS - Protection status of this address block. */
71696/*! @{ */
71697#define IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_LockStatus_MASK (0x1U)
71698#define IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_LockStatus_SHIFT (0U)
71699/*! fetchlayer0_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
71700 */
71701#define IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_LockStatus_SHIFT)) & IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_LockStatus_MASK)
71702#define IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_PrivilegeStatus_MASK (0x10U)
71703#define IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_PrivilegeStatus_SHIFT (4U)
71704/*! fetchlayer0_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
71705 */
71706#define IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_PrivilegeStatus_MASK)
71707#define IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_FreezeStatus_MASK (0x100U)
71708#define IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_FreezeStatus_SHIFT (8U)
71709/*! fetchlayer0_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
71710 */
71711#define IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHLAYER704_LOCKSTATUS_fetchlayer0_FreezeStatus_MASK)
71712/*! @} */
71713
71714/*! @name FETCHLAYER704_STATUS - Status information for pixel engine configuration of fetchlayer0 */
71715/*! @{ */
71716#define IRIS_MVPL_FETCHLAYER704_STATUS_fetchlayer0_sel_MASK (0x70000U)
71717#define IRIS_MVPL_FETCHLAYER704_STATUS_fetchlayer0_sel_SHIFT (16U)
71718/*! fetchlayer0_sel - Status of the connection of the fetchlayer0 module
71719 * 0b000..fetchlayer0 module is not used
71720 * 0b001..fetchlayer0 module is used from store9 processing path
71721 * 0b010..fetchlayer0 module is used from extdst0 processing path
71722 * 0b011..fetchlayer0 module is used from extdst4 processing path
71723 * 0b100..fetchlayer0 module is used from extdst1 processing path
71724 * 0b101..fetchlayer0 module is used from extdst5 processing path
71725 */
71726#define IRIS_MVPL_FETCHLAYER704_STATUS_fetchlayer0_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHLAYER704_STATUS_fetchlayer0_sel_SHIFT)) & IRIS_MVPL_FETCHLAYER704_STATUS_fetchlayer0_sel_MASK)
71727/*! @} */
71728
71729/*! @name MATRIX736_LOCKUNLOCK - Register to change the protection status of this address block. */
71730/*! @{ */
71731#define IRIS_MVPL_MATRIX736_LOCKUNLOCK_matrix4_LockUnlock_MASK (0xFFFFFFFFU)
71732#define IRIS_MVPL_MATRIX736_LOCKUNLOCK_matrix4_LockUnlock_SHIFT (0U)
71733/*! matrix4_LockUnlock - The protection status is changed by writing one of the following key values to this field:
71734 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
71735 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
71736 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
71737 * 0b10110101111000100100011001101110..Disables privilege protection.
71738 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
71739 */
71740#define IRIS_MVPL_MATRIX736_LOCKUNLOCK_matrix4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX736_LOCKUNLOCK_matrix4_LockUnlock_SHIFT)) & IRIS_MVPL_MATRIX736_LOCKUNLOCK_matrix4_LockUnlock_MASK)
71741/*! @} */
71742
71743/*! @name MATRIX736_LOCKSTATUS - Protection status of this address block. */
71744/*! @{ */
71745#define IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_LockStatus_MASK (0x1U)
71746#define IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_LockStatus_SHIFT (0U)
71747/*! matrix4_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
71748 */
71749#define IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_LockStatus_SHIFT)) & IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_LockStatus_MASK)
71750#define IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_PrivilegeStatus_MASK (0x10U)
71751#define IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_PrivilegeStatus_SHIFT (4U)
71752/*! matrix4_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
71753 */
71754#define IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_PrivilegeStatus_MASK)
71755#define IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_FreezeStatus_MASK (0x100U)
71756#define IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_FreezeStatus_SHIFT (8U)
71757/*! matrix4_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
71758 */
71759#define IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_FreezeStatus_SHIFT)) & IRIS_MVPL_MATRIX736_LOCKSTATUS_matrix4_FreezeStatus_MASK)
71760/*! @} */
71761
71762/*! @name MATRIX4_DYNAMIC - Dynamic pixel engine configuration for matrix4 */
71763/*! @{ */
71764#define IRIS_MVPL_MATRIX4_DYNAMIC_matrix4_src_sel_MASK (0x3FU)
71765#define IRIS_MVPL_MATRIX4_DYNAMIC_matrix4_src_sel_SHIFT (0U)
71766/*! matrix4_src_sel - Selection of the source for the src input of the matrix4 module
71767 * 0b000000..Unit matrix4 input port src is disabled
71768 * 0b001010..Unit matrix4 input port src is connected to output of unit blitblend9
71769 * 0b010110..Unit matrix4 input port src is connected to output of unit fetchdecode0
71770 */
71771#define IRIS_MVPL_MATRIX4_DYNAMIC_matrix4_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_DYNAMIC_matrix4_src_sel_SHIFT)) & IRIS_MVPL_MATRIX4_DYNAMIC_matrix4_src_sel_MASK)
71772#define IRIS_MVPL_MATRIX4_DYNAMIC_matrix4_clken_MASK (0x3000000U)
71773#define IRIS_MVPL_MATRIX4_DYNAMIC_matrix4_clken_SHIFT (24U)
71774/*! matrix4_clken - Enable of matrix4 clock (this setting has to be the same for all modules of one
71775 * processing pipeline). If a submodule is enabled and FULL is used, then the register
71776 * [endpoint_name]_clk must be set to 0x80.
71777 * 0b00..Clock for matrix4 is disabled
71778 * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register)
71779 * 0b11..Clock for matrix4 is without gating
71780 */
71781#define IRIS_MVPL_MATRIX4_DYNAMIC_matrix4_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_DYNAMIC_matrix4_clken_SHIFT)) & IRIS_MVPL_MATRIX4_DYNAMIC_matrix4_clken_MASK)
71782/*! @} */
71783
71784/*! @name MATRIX4_STATUS - Status information for pixel engine configuration of matrix4 */
71785/*! @{ */
71786#define IRIS_MVPL_MATRIX4_STATUS_matrix4_sel_MASK (0x70000U)
71787#define IRIS_MVPL_MATRIX4_STATUS_matrix4_sel_SHIFT (16U)
71788/*! matrix4_sel - Status of the connection of the matrix4 module
71789 * 0b000..matrix4 module is not used
71790 * 0b001..matrix4 module is used from store9 processing path
71791 * 0b010..matrix4 module is used from extdst0 processing path
71792 * 0b011..matrix4 module is used from extdst4 processing path
71793 * 0b100..matrix4 module is used from extdst1 processing path
71794 * 0b101..matrix4 module is used from extdst5 processing path
71795 */
71796#define IRIS_MVPL_MATRIX4_STATUS_matrix4_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX4_STATUS_matrix4_sel_SHIFT)) & IRIS_MVPL_MATRIX4_STATUS_matrix4_sel_MASK)
71797/*! @} */
71798
71799/*! @name HSCALER768_LOCKUNLOCK - Register to change the protection status of this address block. */
71800/*! @{ */
71801#define IRIS_MVPL_HSCALER768_LOCKUNLOCK_hscaler4_LockUnlock_MASK (0xFFFFFFFFU)
71802#define IRIS_MVPL_HSCALER768_LOCKUNLOCK_hscaler4_LockUnlock_SHIFT (0U)
71803/*! hscaler4_LockUnlock - The protection status is changed by writing one of the following key values to this field:
71804 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
71805 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
71806 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
71807 * 0b10110101111000100100011001101110..Disables privilege protection.
71808 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
71809 */
71810#define IRIS_MVPL_HSCALER768_LOCKUNLOCK_hscaler4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER768_LOCKUNLOCK_hscaler4_LockUnlock_SHIFT)) & IRIS_MVPL_HSCALER768_LOCKUNLOCK_hscaler4_LockUnlock_MASK)
71811/*! @} */
71812
71813/*! @name HSCALER768_LOCKSTATUS - Protection status of this address block. */
71814/*! @{ */
71815#define IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_LockStatus_MASK (0x1U)
71816#define IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_LockStatus_SHIFT (0U)
71817/*! hscaler4_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
71818 */
71819#define IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_LockStatus_SHIFT)) & IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_LockStatus_MASK)
71820#define IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_PrivilegeStatus_MASK (0x10U)
71821#define IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_PrivilegeStatus_SHIFT (4U)
71822/*! hscaler4_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
71823 */
71824#define IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_PrivilegeStatus_MASK)
71825#define IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_FreezeStatus_MASK (0x100U)
71826#define IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_FreezeStatus_SHIFT (8U)
71827/*! hscaler4_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
71828 */
71829#define IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_FreezeStatus_SHIFT)) & IRIS_MVPL_HSCALER768_LOCKSTATUS_hscaler4_FreezeStatus_MASK)
71830/*! @} */
71831
71832/*! @name HSCALER4_DYNAMIC - Dynamic pixel engine configuration for hscaler4 */
71833/*! @{ */
71834#define IRIS_MVPL_HSCALER4_DYNAMIC_hscaler4_src_sel_MASK (0x3FU)
71835#define IRIS_MVPL_HSCALER4_DYNAMIC_hscaler4_src_sel_SHIFT (0U)
71836/*! hscaler4_src_sel - Selection of the source for the src input of the hscaler4 module
71837 * 0b000000..Unit hscaler4 input port src is disabled
71838 * 0b010110..Unit hscaler4 input port src is connected to output of unit fetchdecode0
71839 * 0b011011..Unit hscaler4 input port src is connected to output of unit matrix4
71840 * 0b011101..Unit hscaler4 input port src is connected to output of unit vscaler4
71841 */
71842#define IRIS_MVPL_HSCALER4_DYNAMIC_hscaler4_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_DYNAMIC_hscaler4_src_sel_SHIFT)) & IRIS_MVPL_HSCALER4_DYNAMIC_hscaler4_src_sel_MASK)
71843#define IRIS_MVPL_HSCALER4_DYNAMIC_hscaler4_clken_MASK (0x3000000U)
71844#define IRIS_MVPL_HSCALER4_DYNAMIC_hscaler4_clken_SHIFT (24U)
71845/*! hscaler4_clken - Enable of hscaler4 clock (this setting has to be the same for all modules of
71846 * one processing pipeline). If a submodule is enabled and FULL is used, then the register
71847 * [endpoint_name]_clk must be set to 0x80.
71848 * 0b00..Clock for hscaler4 is disabled
71849 * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register)
71850 * 0b11..Clock for hscaler4 is without gating
71851 */
71852#define IRIS_MVPL_HSCALER4_DYNAMIC_hscaler4_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_DYNAMIC_hscaler4_clken_SHIFT)) & IRIS_MVPL_HSCALER4_DYNAMIC_hscaler4_clken_MASK)
71853/*! @} */
71854
71855/*! @name HSCALER4_STATUS - Status information for pixel engine configuration of hscaler4 */
71856/*! @{ */
71857#define IRIS_MVPL_HSCALER4_STATUS_hscaler4_sel_MASK (0x70000U)
71858#define IRIS_MVPL_HSCALER4_STATUS_hscaler4_sel_SHIFT (16U)
71859/*! hscaler4_sel - Status of the connection of the hscaler4 module
71860 * 0b000..hscaler4 module is not used
71861 * 0b001..hscaler4 module is used from store9 processing path
71862 * 0b010..hscaler4 module is used from extdst0 processing path
71863 * 0b011..hscaler4 module is used from extdst4 processing path
71864 * 0b100..hscaler4 module is used from extdst1 processing path
71865 * 0b101..hscaler4 module is used from extdst5 processing path
71866 */
71867#define IRIS_MVPL_HSCALER4_STATUS_hscaler4_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER4_STATUS_hscaler4_sel_SHIFT)) & IRIS_MVPL_HSCALER4_STATUS_hscaler4_sel_MASK)
71868/*! @} */
71869
71870/*! @name VSCALER800_LOCKUNLOCK - Register to change the protection status of this address block. */
71871/*! @{ */
71872#define IRIS_MVPL_VSCALER800_LOCKUNLOCK_vscaler4_LockUnlock_MASK (0xFFFFFFFFU)
71873#define IRIS_MVPL_VSCALER800_LOCKUNLOCK_vscaler4_LockUnlock_SHIFT (0U)
71874/*! vscaler4_LockUnlock - The protection status is changed by writing one of the following key values to this field:
71875 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
71876 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
71877 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
71878 * 0b10110101111000100100011001101110..Disables privilege protection.
71879 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
71880 */
71881#define IRIS_MVPL_VSCALER800_LOCKUNLOCK_vscaler4_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER800_LOCKUNLOCK_vscaler4_LockUnlock_SHIFT)) & IRIS_MVPL_VSCALER800_LOCKUNLOCK_vscaler4_LockUnlock_MASK)
71882/*! @} */
71883
71884/*! @name VSCALER800_LOCKSTATUS - Protection status of this address block. */
71885/*! @{ */
71886#define IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_LockStatus_MASK (0x1U)
71887#define IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_LockStatus_SHIFT (0U)
71888/*! vscaler4_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
71889 */
71890#define IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_LockStatus_SHIFT)) & IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_LockStatus_MASK)
71891#define IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_PrivilegeStatus_MASK (0x10U)
71892#define IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_PrivilegeStatus_SHIFT (4U)
71893/*! vscaler4_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
71894 */
71895#define IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_PrivilegeStatus_SHIFT)) & IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_PrivilegeStatus_MASK)
71896#define IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_FreezeStatus_MASK (0x100U)
71897#define IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_FreezeStatus_SHIFT (8U)
71898/*! vscaler4_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
71899 */
71900#define IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_FreezeStatus_SHIFT)) & IRIS_MVPL_VSCALER800_LOCKSTATUS_vscaler4_FreezeStatus_MASK)
71901/*! @} */
71902
71903/*! @name VSCALER4_DYNAMIC - Dynamic pixel engine configuration for vscaler4 */
71904/*! @{ */
71905#define IRIS_MVPL_VSCALER4_DYNAMIC_vscaler4_src_sel_MASK (0x3FU)
71906#define IRIS_MVPL_VSCALER4_DYNAMIC_vscaler4_src_sel_SHIFT (0U)
71907/*! vscaler4_src_sel - Selection of the source for the src input of the vscaler4 module
71908 * 0b000000..Unit vscaler4 input port src is disabled
71909 * 0b010110..Unit vscaler4 input port src is connected to output of unit fetchdecode0
71910 * 0b011011..Unit vscaler4 input port src is connected to output of unit matrix4
71911 * 0b011100..Unit vscaler4 input port src is connected to output of unit hscaler4
71912 */
71913#define IRIS_MVPL_VSCALER4_DYNAMIC_vscaler4_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_DYNAMIC_vscaler4_src_sel_SHIFT)) & IRIS_MVPL_VSCALER4_DYNAMIC_vscaler4_src_sel_MASK)
71914#define IRIS_MVPL_VSCALER4_DYNAMIC_vscaler4_clken_MASK (0x3000000U)
71915#define IRIS_MVPL_VSCALER4_DYNAMIC_vscaler4_clken_SHIFT (24U)
71916/*! vscaler4_clken - Enable of vscaler4 clock (this setting has to be the same for all modules of
71917 * one processing pipeline). If a submodule is enabled and FULL is used, then the register
71918 * [endpoint_name]_clk must be set to 0x80.
71919 * 0b00..Clock for vscaler4 is disabled
71920 * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register)
71921 * 0b11..Clock for vscaler4 is without gating
71922 */
71923#define IRIS_MVPL_VSCALER4_DYNAMIC_vscaler4_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_DYNAMIC_vscaler4_clken_SHIFT)) & IRIS_MVPL_VSCALER4_DYNAMIC_vscaler4_clken_MASK)
71924/*! @} */
71925
71926/*! @name VSCALER4_STATUS - Status information for pixel engine configuration of vscaler4 */
71927/*! @{ */
71928#define IRIS_MVPL_VSCALER4_STATUS_vscaler4_sel_MASK (0x70000U)
71929#define IRIS_MVPL_VSCALER4_STATUS_vscaler4_sel_SHIFT (16U)
71930/*! vscaler4_sel - Status of the connection of the vscaler4 module
71931 * 0b000..vscaler4 module is not used
71932 * 0b001..vscaler4 module is used from store9 processing path
71933 * 0b010..vscaler4 module is used from extdst0 processing path
71934 * 0b011..vscaler4 module is used from extdst4 processing path
71935 * 0b100..vscaler4 module is used from extdst1 processing path
71936 * 0b101..vscaler4 module is used from extdst5 processing path
71937 */
71938#define IRIS_MVPL_VSCALER4_STATUS_vscaler4_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER4_STATUS_vscaler4_sel_SHIFT)) & IRIS_MVPL_VSCALER4_STATUS_vscaler4_sel_MASK)
71939/*! @} */
71940
71941/*! @name MATRIX832_LOCKUNLOCK - Register to change the protection status of this address block. */
71942/*! @{ */
71943#define IRIS_MVPL_MATRIX832_LOCKUNLOCK_matrix5_LockUnlock_MASK (0xFFFFFFFFU)
71944#define IRIS_MVPL_MATRIX832_LOCKUNLOCK_matrix5_LockUnlock_SHIFT (0U)
71945/*! matrix5_LockUnlock - The protection status is changed by writing one of the following key values to this field:
71946 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
71947 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
71948 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
71949 * 0b10110101111000100100011001101110..Disables privilege protection.
71950 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
71951 */
71952#define IRIS_MVPL_MATRIX832_LOCKUNLOCK_matrix5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX832_LOCKUNLOCK_matrix5_LockUnlock_SHIFT)) & IRIS_MVPL_MATRIX832_LOCKUNLOCK_matrix5_LockUnlock_MASK)
71953/*! @} */
71954
71955/*! @name MATRIX832_LOCKSTATUS - Protection status of this address block. */
71956/*! @{ */
71957#define IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_LockStatus_MASK (0x1U)
71958#define IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_LockStatus_SHIFT (0U)
71959/*! matrix5_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
71960 */
71961#define IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_LockStatus_SHIFT)) & IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_LockStatus_MASK)
71962#define IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_PrivilegeStatus_MASK (0x10U)
71963#define IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_PrivilegeStatus_SHIFT (4U)
71964/*! matrix5_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
71965 */
71966#define IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_PrivilegeStatus_SHIFT)) & IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_PrivilegeStatus_MASK)
71967#define IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_FreezeStatus_MASK (0x100U)
71968#define IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_FreezeStatus_SHIFT (8U)
71969/*! matrix5_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
71970 */
71971#define IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_FreezeStatus_SHIFT)) & IRIS_MVPL_MATRIX832_LOCKSTATUS_matrix5_FreezeStatus_MASK)
71972/*! @} */
71973
71974/*! @name MATRIX5_DYNAMIC - Dynamic pixel engine configuration for matrix5 */
71975/*! @{ */
71976#define IRIS_MVPL_MATRIX5_DYNAMIC_matrix5_src_sel_MASK (0x3FU)
71977#define IRIS_MVPL_MATRIX5_DYNAMIC_matrix5_src_sel_SHIFT (0U)
71978/*! matrix5_src_sel - Selection of the source for the src input of the matrix5 module
71979 * 0b000000..Unit matrix5 input port src is disabled
71980 * 0b001010..Unit matrix5 input port src is connected to output of unit blitblend9
71981 * 0b011000..Unit matrix5 input port src is connected to output of unit fetchdecode1
71982 */
71983#define IRIS_MVPL_MATRIX5_DYNAMIC_matrix5_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_DYNAMIC_matrix5_src_sel_SHIFT)) & IRIS_MVPL_MATRIX5_DYNAMIC_matrix5_src_sel_MASK)
71984#define IRIS_MVPL_MATRIX5_DYNAMIC_matrix5_clken_MASK (0x3000000U)
71985#define IRIS_MVPL_MATRIX5_DYNAMIC_matrix5_clken_SHIFT (24U)
71986/*! matrix5_clken - Enable of matrix5 clock (this setting has to be the same for all modules of one
71987 * processing pipeline). If a submodule is enabled and FULL is used, then the register
71988 * [endpoint_name]_clk must be set to 0x80.
71989 * 0b00..Clock for matrix5 is disabled
71990 * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register)
71991 * 0b11..Clock for matrix5 is without gating
71992 */
71993#define IRIS_MVPL_MATRIX5_DYNAMIC_matrix5_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_DYNAMIC_matrix5_clken_SHIFT)) & IRIS_MVPL_MATRIX5_DYNAMIC_matrix5_clken_MASK)
71994/*! @} */
71995
71996/*! @name MATRIX5_STATUS - Status information for pixel engine configuration of matrix5 */
71997/*! @{ */
71998#define IRIS_MVPL_MATRIX5_STATUS_matrix5_sel_MASK (0x70000U)
71999#define IRIS_MVPL_MATRIX5_STATUS_matrix5_sel_SHIFT (16U)
72000/*! matrix5_sel - Status of the connection of the matrix5 module
72001 * 0b000..matrix5 module is not used
72002 * 0b001..matrix5 module is used from store9 processing path
72003 * 0b010..matrix5 module is used from extdst0 processing path
72004 * 0b011..matrix5 module is used from extdst4 processing path
72005 * 0b100..matrix5 module is used from extdst1 processing path
72006 * 0b101..matrix5 module is used from extdst5 processing path
72007 */
72008#define IRIS_MVPL_MATRIX5_STATUS_matrix5_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX5_STATUS_matrix5_sel_SHIFT)) & IRIS_MVPL_MATRIX5_STATUS_matrix5_sel_MASK)
72009/*! @} */
72010
72011/*! @name HSCALER864_LOCKUNLOCK - Register to change the protection status of this address block. */
72012/*! @{ */
72013#define IRIS_MVPL_HSCALER864_LOCKUNLOCK_hscaler5_LockUnlock_MASK (0xFFFFFFFFU)
72014#define IRIS_MVPL_HSCALER864_LOCKUNLOCK_hscaler5_LockUnlock_SHIFT (0U)
72015/*! hscaler5_LockUnlock - The protection status is changed by writing one of the following key values to this field:
72016 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
72017 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
72018 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
72019 * 0b10110101111000100100011001101110..Disables privilege protection.
72020 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
72021 */
72022#define IRIS_MVPL_HSCALER864_LOCKUNLOCK_hscaler5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER864_LOCKUNLOCK_hscaler5_LockUnlock_SHIFT)) & IRIS_MVPL_HSCALER864_LOCKUNLOCK_hscaler5_LockUnlock_MASK)
72023/*! @} */
72024
72025/*! @name HSCALER864_LOCKSTATUS - Protection status of this address block. */
72026/*! @{ */
72027#define IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_LockStatus_MASK (0x1U)
72028#define IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_LockStatus_SHIFT (0U)
72029/*! hscaler5_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
72030 */
72031#define IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_LockStatus_SHIFT)) & IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_LockStatus_MASK)
72032#define IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_PrivilegeStatus_MASK (0x10U)
72033#define IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_PrivilegeStatus_SHIFT (4U)
72034/*! hscaler5_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
72035 */
72036#define IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_PrivilegeStatus_SHIFT)) & IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_PrivilegeStatus_MASK)
72037#define IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_FreezeStatus_MASK (0x100U)
72038#define IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_FreezeStatus_SHIFT (8U)
72039/*! hscaler5_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
72040 */
72041#define IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_FreezeStatus_SHIFT)) & IRIS_MVPL_HSCALER864_LOCKSTATUS_hscaler5_FreezeStatus_MASK)
72042/*! @} */
72043
72044/*! @name HSCALER5_DYNAMIC - Dynamic pixel engine configuration for hscaler5 */
72045/*! @{ */
72046#define IRIS_MVPL_HSCALER5_DYNAMIC_hscaler5_src_sel_MASK (0x3FU)
72047#define IRIS_MVPL_HSCALER5_DYNAMIC_hscaler5_src_sel_SHIFT (0U)
72048/*! hscaler5_src_sel - Selection of the source for the src input of the hscaler5 module
72049 * 0b000000..Unit hscaler5 input port src is disabled
72050 * 0b011000..Unit hscaler5 input port src is connected to output of unit fetchdecode1
72051 * 0b011110..Unit hscaler5 input port src is connected to output of unit matrix5
72052 * 0b100000..Unit hscaler5 input port src is connected to output of unit vscaler5
72053 */
72054#define IRIS_MVPL_HSCALER5_DYNAMIC_hscaler5_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_DYNAMIC_hscaler5_src_sel_SHIFT)) & IRIS_MVPL_HSCALER5_DYNAMIC_hscaler5_src_sel_MASK)
72055#define IRIS_MVPL_HSCALER5_DYNAMIC_hscaler5_clken_MASK (0x3000000U)
72056#define IRIS_MVPL_HSCALER5_DYNAMIC_hscaler5_clken_SHIFT (24U)
72057/*! hscaler5_clken - Enable of hscaler5 clock (this setting has to be the same for all modules of
72058 * one processing pipeline). If a submodule is enabled and FULL is used, then the register
72059 * [endpoint_name]_clk must be set to 0x80.
72060 * 0b00..Clock for hscaler5 is disabled
72061 * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register)
72062 * 0b11..Clock for hscaler5 is without gating
72063 */
72064#define IRIS_MVPL_HSCALER5_DYNAMIC_hscaler5_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_DYNAMIC_hscaler5_clken_SHIFT)) & IRIS_MVPL_HSCALER5_DYNAMIC_hscaler5_clken_MASK)
72065/*! @} */
72066
72067/*! @name HSCALER5_STATUS - Status information for pixel engine configuration of hscaler5 */
72068/*! @{ */
72069#define IRIS_MVPL_HSCALER5_STATUS_hscaler5_sel_MASK (0x70000U)
72070#define IRIS_MVPL_HSCALER5_STATUS_hscaler5_sel_SHIFT (16U)
72071/*! hscaler5_sel - Status of the connection of the hscaler5 module
72072 * 0b000..hscaler5 module is not used
72073 * 0b001..hscaler5 module is used from store9 processing path
72074 * 0b010..hscaler5 module is used from extdst0 processing path
72075 * 0b011..hscaler5 module is used from extdst4 processing path
72076 * 0b100..hscaler5 module is used from extdst1 processing path
72077 * 0b101..hscaler5 module is used from extdst5 processing path
72078 */
72079#define IRIS_MVPL_HSCALER5_STATUS_hscaler5_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER5_STATUS_hscaler5_sel_SHIFT)) & IRIS_MVPL_HSCALER5_STATUS_hscaler5_sel_MASK)
72080/*! @} */
72081
72082/*! @name VSCALER896_LOCKUNLOCK - Register to change the protection status of this address block. */
72083/*! @{ */
72084#define IRIS_MVPL_VSCALER896_LOCKUNLOCK_vscaler5_LockUnlock_MASK (0xFFFFFFFFU)
72085#define IRIS_MVPL_VSCALER896_LOCKUNLOCK_vscaler5_LockUnlock_SHIFT (0U)
72086/*! vscaler5_LockUnlock - The protection status is changed by writing one of the following key values to this field:
72087 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
72088 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
72089 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
72090 * 0b10110101111000100100011001101110..Disables privilege protection.
72091 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
72092 */
72093#define IRIS_MVPL_VSCALER896_LOCKUNLOCK_vscaler5_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER896_LOCKUNLOCK_vscaler5_LockUnlock_SHIFT)) & IRIS_MVPL_VSCALER896_LOCKUNLOCK_vscaler5_LockUnlock_MASK)
72094/*! @} */
72095
72096/*! @name VSCALER896_LOCKSTATUS - Protection status of this address block. */
72097/*! @{ */
72098#define IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_LockStatus_MASK (0x1U)
72099#define IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_LockStatus_SHIFT (0U)
72100/*! vscaler5_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
72101 */
72102#define IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_LockStatus_SHIFT)) & IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_LockStatus_MASK)
72103#define IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_PrivilegeStatus_MASK (0x10U)
72104#define IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_PrivilegeStatus_SHIFT (4U)
72105/*! vscaler5_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
72106 */
72107#define IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_PrivilegeStatus_SHIFT)) & IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_PrivilegeStatus_MASK)
72108#define IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_FreezeStatus_MASK (0x100U)
72109#define IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_FreezeStatus_SHIFT (8U)
72110/*! vscaler5_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
72111 */
72112#define IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_FreezeStatus_SHIFT)) & IRIS_MVPL_VSCALER896_LOCKSTATUS_vscaler5_FreezeStatus_MASK)
72113/*! @} */
72114
72115/*! @name VSCALER5_DYNAMIC - Dynamic pixel engine configuration for vscaler5 */
72116/*! @{ */
72117#define IRIS_MVPL_VSCALER5_DYNAMIC_vscaler5_src_sel_MASK (0x3FU)
72118#define IRIS_MVPL_VSCALER5_DYNAMIC_vscaler5_src_sel_SHIFT (0U)
72119/*! vscaler5_src_sel - Selection of the source for the src input of the vscaler5 module
72120 * 0b000000..Unit vscaler5 input port src is disabled
72121 * 0b011000..Unit vscaler5 input port src is connected to output of unit fetchdecode1
72122 * 0b011110..Unit vscaler5 input port src is connected to output of unit matrix5
72123 * 0b011111..Unit vscaler5 input port src is connected to output of unit hscaler5
72124 */
72125#define IRIS_MVPL_VSCALER5_DYNAMIC_vscaler5_src_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_DYNAMIC_vscaler5_src_sel_SHIFT)) & IRIS_MVPL_VSCALER5_DYNAMIC_vscaler5_src_sel_MASK)
72126#define IRIS_MVPL_VSCALER5_DYNAMIC_vscaler5_clken_MASK (0x3000000U)
72127#define IRIS_MVPL_VSCALER5_DYNAMIC_vscaler5_clken_SHIFT (24U)
72128/*! vscaler5_clken - Enable of vscaler5 clock (this setting has to be the same for all modules of
72129 * one processing pipeline). If a submodule is enabled and FULL is used, then the register
72130 * [endpoint_name]_clk must be set to 0x80.
72131 * 0b00..Clock for vscaler5 is disabled
72132 * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register)
72133 * 0b11..Clock for vscaler5 is without gating
72134 */
72135#define IRIS_MVPL_VSCALER5_DYNAMIC_vscaler5_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_DYNAMIC_vscaler5_clken_SHIFT)) & IRIS_MVPL_VSCALER5_DYNAMIC_vscaler5_clken_MASK)
72136/*! @} */
72137
72138/*! @name VSCALER5_STATUS - Status information for pixel engine configuration of vscaler5 */
72139/*! @{ */
72140#define IRIS_MVPL_VSCALER5_STATUS_vscaler5_sel_MASK (0x70000U)
72141#define IRIS_MVPL_VSCALER5_STATUS_vscaler5_sel_SHIFT (16U)
72142/*! vscaler5_sel - Status of the connection of the vscaler5 module
72143 * 0b000..vscaler5 module is not used
72144 * 0b001..vscaler5 module is used from store9 processing path
72145 * 0b010..vscaler5 module is used from extdst0 processing path
72146 * 0b011..vscaler5 module is used from extdst4 processing path
72147 * 0b100..vscaler5 module is used from extdst1 processing path
72148 * 0b101..vscaler5 module is used from extdst5 processing path
72149 */
72150#define IRIS_MVPL_VSCALER5_STATUS_vscaler5_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER5_STATUS_vscaler5_sel_SHIFT)) & IRIS_MVPL_VSCALER5_STATUS_vscaler5_sel_MASK)
72151/*! @} */
72152
72153/*! @name LAYERBLEND928_LOCKUNLOCK - Register to change the protection status of this address block. */
72154/*! @{ */
72155#define IRIS_MVPL_LAYERBLEND928_LOCKUNLOCK_layerblend0_LockUnlock_MASK (0xFFFFFFFFU)
72156#define IRIS_MVPL_LAYERBLEND928_LOCKUNLOCK_layerblend0_LockUnlock_SHIFT (0U)
72157/*! layerblend0_LockUnlock - The protection status is changed by writing one of the following key values to this field:
72158 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
72159 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
72160 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
72161 * 0b10110101111000100100011001101110..Disables privilege protection.
72162 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
72163 */
72164#define IRIS_MVPL_LAYERBLEND928_LOCKUNLOCK_layerblend0_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND928_LOCKUNLOCK_layerblend0_LockUnlock_SHIFT)) & IRIS_MVPL_LAYERBLEND928_LOCKUNLOCK_layerblend0_LockUnlock_MASK)
72165/*! @} */
72166
72167/*! @name LAYERBLEND928_LOCKSTATUS - Protection status of this address block. */
72168/*! @{ */
72169#define IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_LockStatus_MASK (0x1U)
72170#define IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_LockStatus_SHIFT (0U)
72171/*! layerblend0_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
72172 */
72173#define IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_LockStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_LockStatus_MASK)
72174#define IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_PrivilegeStatus_MASK (0x10U)
72175#define IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_PrivilegeStatus_SHIFT (4U)
72176/*! layerblend0_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
72177 */
72178#define IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_PrivilegeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_PrivilegeStatus_MASK)
72179#define IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_FreezeStatus_MASK (0x100U)
72180#define IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_FreezeStatus_SHIFT (8U)
72181/*! layerblend0_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
72182 */
72183#define IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_FreezeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND928_LOCKSTATUS_layerblend0_FreezeStatus_MASK)
72184/*! @} */
72185
72186/*! @name LAYERBLEND0_DYNAMIC - Dynamic pixel engine configuration for layerblend0 */
72187/*! @{ */
72188#define IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_prim_sel_MASK (0x3FU)
72189#define IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_prim_sel_SHIFT (0U)
72190/*! layerblend0_prim_sel - Selection of the source for the prim input of the layerblend0 module
72191 * 0b000000..Unit layerblend0 input port prim is disabled
72192 * 0b001010..Unit layerblend0 input port prim is connected to output of unit blitblend9
72193 * 0b001100..Unit layerblend0 input port prim is connected to output of unit constframe0
72194 * 0b001110..Unit layerblend0 input port prim is connected to output of unit constframe4
72195 * 0b000000..Unit layerblend0 input port prim is connected to output of unit constframe1
72196 * 0b010010..Unit layerblend0 input port prim is connected to output of unit constframe5
72197 * 0b011011..Unit layerblend0 input port prim is connected to output of unit matrix4
72198 * 0b011100..Unit layerblend0 input port prim is connected to output of unit hscaler4
72199 * 0b011101..Unit layerblend0 input port prim is connected to output of unit vscaler4
72200 * 0b011110..Unit layerblend0 input port prim is connected to output of unit matrix5
72201 * 0b011111..Unit layerblend0 input port prim is connected to output of unit hscaler5
72202 * 0b100000..Unit layerblend0 input port prim is connected to output of unit vscaler5
72203 */
72204#define IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_prim_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_prim_sel_MASK)
72205#define IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_sec_sel_MASK (0x3F00U)
72206#define IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_sec_sel_SHIFT (8U)
72207/*! layerblend0_sec_sel - Selection of the source for the sec input of the layerblend0 module
72208 * 0b000000..Unit layerblend0 input port sec is disabled
72209 * 0b010100..Unit layerblend0 input port sec is connected to output of unit fetchwarp2
72210 * 0b010110..Unit layerblend0 input port sec is connected to output of unit fetchdecode0
72211 * 0b011000..Unit layerblend0 input port sec is connected to output of unit fetchdecode1
72212 * 0b011010..Unit layerblend0 input port sec is connected to output of unit fetchlayer0
72213 * 0b011011..Unit layerblend0 input port sec is connected to output of unit matrix4
72214 * 0b011100..Unit layerblend0 input port sec is connected to output of unit hscaler4
72215 * 0b011101..Unit layerblend0 input port sec is connected to output of unit vscaler4
72216 * 0b011110..Unit layerblend0 input port sec is connected to output of unit matrix5
72217 * 0b011111..Unit layerblend0 input port sec is connected to output of unit hscaler5
72218 * 0b100000..Unit layerblend0 input port sec is connected to output of unit vscaler5
72219 */
72220#define IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_sec_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_sec_sel_MASK)
72221#define IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_clken_MASK (0x3000000U)
72222#define IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_clken_SHIFT (24U)
72223/*! layerblend0_clken - Enable of layerblend0 clock (this setting has to be the same for all modules
72224 * of one processing pipeline). If a submodule is enabled and FULL is used, then the register
72225 * [endpoint_name]_clk must be set to 0x80.
72226 * 0b00..Clock for layerblend0 is disabled
72227 * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register)
72228 * 0b11..Clock for layerblend0 is without gating
72229 */
72230#define IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_clken_SHIFT)) & IRIS_MVPL_LAYERBLEND0_DYNAMIC_layerblend0_clken_MASK)
72231/*! @} */
72232
72233/*! @name LAYERBLEND0_STATUS - Status information for pixel engine configuration of layerblend0 */
72234/*! @{ */
72235#define IRIS_MVPL_LAYERBLEND0_STATUS_layerblend0_sel_MASK (0x70000U)
72236#define IRIS_MVPL_LAYERBLEND0_STATUS_layerblend0_sel_SHIFT (16U)
72237/*! layerblend0_sel - Status of the connection of the layerblend0 module
72238 * 0b000..layerblend0 module is not used
72239 * 0b001..layerblend0 module is used from store9 processing path
72240 * 0b010..layerblend0 module is used from extdst0 processing path
72241 * 0b011..layerblend0 module is used from extdst4 processing path
72242 * 0b100..layerblend0 module is used from extdst1 processing path
72243 * 0b101..layerblend0 module is used from extdst5 processing path
72244 */
72245#define IRIS_MVPL_LAYERBLEND0_STATUS_layerblend0_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND0_STATUS_layerblend0_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND0_STATUS_layerblend0_sel_MASK)
72246/*! @} */
72247
72248/*! @name LAYERBLEND960_LOCKUNLOCK - Register to change the protection status of this address block. */
72249/*! @{ */
72250#define IRIS_MVPL_LAYERBLEND960_LOCKUNLOCK_layerblend1_LockUnlock_MASK (0xFFFFFFFFU)
72251#define IRIS_MVPL_LAYERBLEND960_LOCKUNLOCK_layerblend1_LockUnlock_SHIFT (0U)
72252/*! layerblend1_LockUnlock - The protection status is changed by writing one of the following key values to this field:
72253 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
72254 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
72255 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
72256 * 0b10110101111000100100011001101110..Disables privilege protection.
72257 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
72258 */
72259#define IRIS_MVPL_LAYERBLEND960_LOCKUNLOCK_layerblend1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND960_LOCKUNLOCK_layerblend1_LockUnlock_SHIFT)) & IRIS_MVPL_LAYERBLEND960_LOCKUNLOCK_layerblend1_LockUnlock_MASK)
72260/*! @} */
72261
72262/*! @name LAYERBLEND960_LOCKSTATUS - Protection status of this address block. */
72263/*! @{ */
72264#define IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_LockStatus_MASK (0x1U)
72265#define IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_LockStatus_SHIFT (0U)
72266/*! layerblend1_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
72267 */
72268#define IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_LockStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_LockStatus_MASK)
72269#define IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_PrivilegeStatus_MASK (0x10U)
72270#define IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_PrivilegeStatus_SHIFT (4U)
72271/*! layerblend1_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
72272 */
72273#define IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_PrivilegeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_PrivilegeStatus_MASK)
72274#define IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_FreezeStatus_MASK (0x100U)
72275#define IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_FreezeStatus_SHIFT (8U)
72276/*! layerblend1_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
72277 */
72278#define IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_FreezeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND960_LOCKSTATUS_layerblend1_FreezeStatus_MASK)
72279/*! @} */
72280
72281/*! @name LAYERBLEND1_DYNAMIC - Dynamic pixel engine configuration for layerblend1 */
72282/*! @{ */
72283#define IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_prim_sel_MASK (0x3FU)
72284#define IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_prim_sel_SHIFT (0U)
72285/*! layerblend1_prim_sel - Selection of the source for the prim input of the layerblend1 module
72286 * 0b000000..Unit layerblend1 input port prim is disabled
72287 * 0b001010..Unit layerblend1 input port prim is connected to output of unit blitblend9
72288 * 0b001100..Unit layerblend1 input port prim is connected to output of unit constframe0
72289 * 0b001110..Unit layerblend1 input port prim is connected to output of unit constframe4
72290 * 0b000000..Unit layerblend1 input port prim is connected to output of unit constframe1
72291 * 0b010010..Unit layerblend1 input port prim is connected to output of unit constframe5
72292 * 0b011011..Unit layerblend1 input port prim is connected to output of unit matrix4
72293 * 0b011100..Unit layerblend1 input port prim is connected to output of unit hscaler4
72294 * 0b011101..Unit layerblend1 input port prim is connected to output of unit vscaler4
72295 * 0b011110..Unit layerblend1 input port prim is connected to output of unit matrix5
72296 * 0b011111..Unit layerblend1 input port prim is connected to output of unit hscaler5
72297 * 0b100000..Unit layerblend1 input port prim is connected to output of unit vscaler5
72298 * 0b100001..Unit layerblend1 input port prim is connected to output of unit layerblend0
72299 */
72300#define IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_prim_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_prim_sel_MASK)
72301#define IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_sec_sel_MASK (0x3F00U)
72302#define IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_sec_sel_SHIFT (8U)
72303/*! layerblend1_sec_sel - Selection of the source for the sec input of the layerblend1 module
72304 * 0b000000..Unit layerblend1 input port sec is disabled
72305 * 0b010100..Unit layerblend1 input port sec is connected to output of unit fetchwarp2
72306 * 0b010110..Unit layerblend1 input port sec is connected to output of unit fetchdecode0
72307 * 0b011000..Unit layerblend1 input port sec is connected to output of unit fetchdecode1
72308 * 0b011010..Unit layerblend1 input port sec is connected to output of unit fetchlayer0
72309 * 0b011011..Unit layerblend1 input port sec is connected to output of unit matrix4
72310 * 0b011100..Unit layerblend1 input port sec is connected to output of unit hscaler4
72311 * 0b011101..Unit layerblend1 input port sec is connected to output of unit vscaler4
72312 * 0b011110..Unit layerblend1 input port sec is connected to output of unit matrix5
72313 * 0b011111..Unit layerblend1 input port sec is connected to output of unit hscaler5
72314 * 0b100000..Unit layerblend1 input port sec is connected to output of unit vscaler5
72315 */
72316#define IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_sec_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_sec_sel_MASK)
72317#define IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_clken_MASK (0x3000000U)
72318#define IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_clken_SHIFT (24U)
72319/*! layerblend1_clken - Enable of layerblend1 clock (this setting has to be the same for all modules
72320 * of one processing pipeline). If a submodule is enabled and FULL is used, then the register
72321 * [endpoint_name]_clk must be set to 0x80.
72322 * 0b00..Clock for layerblend1 is disabled
72323 * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register)
72324 * 0b11..Clock for layerblend1 is without gating
72325 */
72326#define IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_clken_SHIFT)) & IRIS_MVPL_LAYERBLEND1_DYNAMIC_layerblend1_clken_MASK)
72327/*! @} */
72328
72329/*! @name LAYERBLEND1_STATUS - Status information for pixel engine configuration of layerblend1 */
72330/*! @{ */
72331#define IRIS_MVPL_LAYERBLEND1_STATUS_layerblend1_sel_MASK (0x70000U)
72332#define IRIS_MVPL_LAYERBLEND1_STATUS_layerblend1_sel_SHIFT (16U)
72333/*! layerblend1_sel - Status of the connection of the layerblend1 module
72334 * 0b000..layerblend1 module is not used
72335 * 0b001..layerblend1 module is used from store9 processing path
72336 * 0b010..layerblend1 module is used from extdst0 processing path
72337 * 0b011..layerblend1 module is used from extdst4 processing path
72338 * 0b100..layerblend1 module is used from extdst1 processing path
72339 * 0b101..layerblend1 module is used from extdst5 processing path
72340 */
72341#define IRIS_MVPL_LAYERBLEND1_STATUS_layerblend1_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1_STATUS_layerblend1_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND1_STATUS_layerblend1_sel_MASK)
72342/*! @} */
72343
72344/*! @name LAYERBLEND992_LOCKUNLOCK - Register to change the protection status of this address block. */
72345/*! @{ */
72346#define IRIS_MVPL_LAYERBLEND992_LOCKUNLOCK_layerblend2_LockUnlock_MASK (0xFFFFFFFFU)
72347#define IRIS_MVPL_LAYERBLEND992_LOCKUNLOCK_layerblend2_LockUnlock_SHIFT (0U)
72348/*! layerblend2_LockUnlock - The protection status is changed by writing one of the following key values to this field:
72349 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
72350 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
72351 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
72352 * 0b10110101111000100100011001101110..Disables privilege protection.
72353 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
72354 */
72355#define IRIS_MVPL_LAYERBLEND992_LOCKUNLOCK_layerblend2_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND992_LOCKUNLOCK_layerblend2_LockUnlock_SHIFT)) & IRIS_MVPL_LAYERBLEND992_LOCKUNLOCK_layerblend2_LockUnlock_MASK)
72356/*! @} */
72357
72358/*! @name LAYERBLEND99_LOCKSTATUS - Protection status of this address block. */
72359/*! @{ */
72360#define IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_LockStatus_MASK (0x1U)
72361#define IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_LockStatus_SHIFT (0U)
72362/*! layerblend2_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
72363 */
72364#define IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_LockStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_LockStatus_MASK)
72365#define IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_PrivilegeStatus_MASK (0x10U)
72366#define IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_PrivilegeStatus_SHIFT (4U)
72367/*! layerblend2_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
72368 */
72369#define IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_PrivilegeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_PrivilegeStatus_MASK)
72370#define IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_FreezeStatus_MASK (0x100U)
72371#define IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_FreezeStatus_SHIFT (8U)
72372/*! layerblend2_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
72373 */
72374#define IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_FreezeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND99_LOCKSTATUS_layerblend2_FreezeStatus_MASK)
72375/*! @} */
72376
72377/*! @name LAYERBLEND2_DYNAMIC - Dynamic pixel engine configuration for layerblend2 */
72378/*! @{ */
72379#define IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_prim_sel_MASK (0x3FU)
72380#define IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_prim_sel_SHIFT (0U)
72381/*! layerblend2_prim_sel - Selection of the source for the prim input of the layerblend2 module
72382 * 0b000000..Unit layerblend2 input port prim is disabled
72383 * 0b001010..Unit layerblend2 input port prim is connected to output of unit blitblend9
72384 * 0b001100..Unit layerblend2 input port prim is connected to output of unit constframe0
72385 * 0b001110..Unit layerblend2 input port prim is connected to output of unit constframe4
72386 * 0b000000..Unit layerblend2 input port prim is connected to output of unit constframe1
72387 * 0b010010..Unit layerblend2 input port prim is connected to output of unit constframe5
72388 * 0b011011..Unit layerblend2 input port prim is connected to output of unit matrix4
72389 * 0b011100..Unit layerblend2 input port prim is connected to output of unit hscaler4
72390 * 0b011101..Unit layerblend2 input port prim is connected to output of unit vscaler4
72391 * 0b011110..Unit layerblend2 input port prim is connected to output of unit matrix5
72392 * 0b011111..Unit layerblend2 input port prim is connected to output of unit hscaler5
72393 * 0b100000..Unit layerblend2 input port prim is connected to output of unit vscaler5
72394 * 0b100001..Unit layerblend2 input port prim is connected to output of unit layerblend0
72395 * 0b100010..Unit layerblend2 input port prim is connected to output of unit layerblend1
72396 */
72397#define IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_prim_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_prim_sel_MASK)
72398#define IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_sec_sel_MASK (0x3F00U)
72399#define IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_sec_sel_SHIFT (8U)
72400/*! layerblend2_sec_sel - Selection of the source for the sec input of the layerblend2 module
72401 * 0b000000..Unit layerblend2 input port sec is disabled
72402 * 0b010100..Unit layerblend2 input port sec is connected to output of unit fetchwarp2
72403 * 0b010110..Unit layerblend2 input port sec is connected to output of unit fetchdecode0
72404 * 0b011000..Unit layerblend2 input port sec is connected to output of unit fetchdecode1
72405 * 0b011010..Unit layerblend2 input port sec is connected to output of unit fetchlayer0
72406 * 0b011011..Unit layerblend2 input port sec is connected to output of unit matrix4
72407 * 0b011100..Unit layerblend2 input port sec is connected to output of unit hscaler4
72408 * 0b011101..Unit layerblend2 input port sec is connected to output of unit vscaler4
72409 * 0b011110..Unit layerblend2 input port sec is connected to output of unit matrix5
72410 * 0b011111..Unit layerblend2 input port sec is connected to output of unit hscaler5
72411 * 0b100000..Unit layerblend2 input port sec is connected to output of unit vscaler5
72412 */
72413#define IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_sec_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_sec_sel_MASK)
72414#define IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_clken_MASK (0x3000000U)
72415#define IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_clken_SHIFT (24U)
72416/*! layerblend2_clken - Enable of layerblend2 clock (this setting has to be the same for all modules
72417 * of one processing pipeline). If a submodule is enabled and FULL is used, then the register
72418 * [endpoint_name]_clk must be set to 0x80.
72419 * 0b00..Clock for layerblend2 is disabled
72420 * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register)
72421 * 0b11..Clock for layerblend2 is without gating
72422 */
72423#define IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_clken_SHIFT)) & IRIS_MVPL_LAYERBLEND2_DYNAMIC_layerblend2_clken_MASK)
72424/*! @} */
72425
72426/*! @name LAYERBLEND2_STATUS - Status information for pixel engine configuration of layerblend2 */
72427/*! @{ */
72428#define IRIS_MVPL_LAYERBLEND2_STATUS_layerblend2_sel_MASK (0x70000U)
72429#define IRIS_MVPL_LAYERBLEND2_STATUS_layerblend2_sel_SHIFT (16U)
72430/*! layerblend2_sel - Status of the connection of the layerblend2 module
72431 * 0b000..layerblend2 module is not used
72432 * 0b001..layerblend2 module is used from store9 processing path
72433 * 0b010..layerblend2 module is used from extdst0 processing path
72434 * 0b011..layerblend2 module is used from extdst4 processing path
72435 * 0b100..layerblend2 module is used from extdst1 processing path
72436 * 0b101..layerblend2 module is used from extdst5 processing path
72437 */
72438#define IRIS_MVPL_LAYERBLEND2_STATUS_layerblend2_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND2_STATUS_layerblend2_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND2_STATUS_layerblend2_sel_MASK)
72439/*! @} */
72440
72441/*! @name LAYERBLEND1024_LOCKUNLOCK - Register to change the protection status of this address block. */
72442/*! @{ */
72443#define IRIS_MVPL_LAYERBLEND1024_LOCKUNLOCK_layerblend3_LockUnlock_MASK (0xFFFFFFFFU)
72444#define IRIS_MVPL_LAYERBLEND1024_LOCKUNLOCK_layerblend3_LockUnlock_SHIFT (0U)
72445/*! layerblend3_LockUnlock - The protection status is changed by writing one of the following key values to this field:
72446 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
72447 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
72448 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
72449 * 0b10110101111000100100011001101110..Disables privilege protection.
72450 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
72451 */
72452#define IRIS_MVPL_LAYERBLEND1024_LOCKUNLOCK_layerblend3_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1024_LOCKUNLOCK_layerblend3_LockUnlock_SHIFT)) & IRIS_MVPL_LAYERBLEND1024_LOCKUNLOCK_layerblend3_LockUnlock_MASK)
72453/*! @} */
72454
72455/*! @name LAYERBLEND1024_LOCKSTATUS - Protection status of this address block. */
72456/*! @{ */
72457#define IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_LockStatus_MASK (0x1U)
72458#define IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_LockStatus_SHIFT (0U)
72459/*! layerblend3_LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
72460 */
72461#define IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_LockStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_LockStatus_MASK)
72462#define IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_PrivilegeStatus_MASK (0x10U)
72463#define IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_PrivilegeStatus_SHIFT (4U)
72464/*! layerblend3_PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
72465 */
72466#define IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_PrivilegeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_PrivilegeStatus_MASK)
72467#define IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_FreezeStatus_MASK (0x100U)
72468#define IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_FreezeStatus_SHIFT (8U)
72469/*! layerblend3_FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
72470 */
72471#define IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_FreezeStatus_SHIFT)) & IRIS_MVPL_LAYERBLEND1024_LOCKSTATUS_layerblend3_FreezeStatus_MASK)
72472/*! @} */
72473
72474/*! @name LAYERBLEND3_DYNAMIC - Dynamic pixel engine configuration for layerblend3 */
72475/*! @{ */
72476#define IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_prim_sel_MASK (0x3FU)
72477#define IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_prim_sel_SHIFT (0U)
72478/*! layerblend3_prim_sel - Selection of the source for the prim input of the layerblend3 module
72479 * 0b000000..Unit layerblend3 input port prim is disabled
72480 * 0b001010..Unit layerblend3 input port prim is connected to output of unit blitblend9
72481 * 0b001100..Unit layerblend3 input port prim is connected to output of unit constframe0
72482 * 0b001110..Unit layerblend3 input port prim is connected to output of unit constframe4
72483 * 0b000000..Unit layerblend3 input port prim is connected to output of unit constframe1
72484 * 0b010010..Unit layerblend3 input port prim is connected to output of unit constframe5
72485 * 0b011011..Unit layerblend3 input port prim is connected to output of unit matrix4
72486 * 0b011100..Unit layerblend3 input port prim is connected to output of unit hscaler4
72487 * 0b011101..Unit layerblend3 input port prim is connected to output of unit vscaler4
72488 * 0b011110..Unit layerblend3 input port prim is connected to output of unit matrix5
72489 * 0b011111..Unit layerblend3 input port prim is connected to output of unit hscaler5
72490 * 0b100000..Unit layerblend3 input port prim is connected to output of unit vscaler5
72491 * 0b100001..Unit layerblend3 input port prim is connected to output of unit layerblend0
72492 * 0b100010..Unit layerblend3 input port prim is connected to output of unit layerblend1
72493 * 0b100011..Unit layerblend3 input port prim is connected to output of unit layerblend2
72494 */
72495#define IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_prim_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_prim_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_prim_sel_MASK)
72496#define IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_sec_sel_MASK (0x3F00U)
72497#define IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_sec_sel_SHIFT (8U)
72498/*! layerblend3_sec_sel - Selection of the source for the sec input of the layerblend3 module
72499 * 0b000000..Unit layerblend3 input port sec is disabled
72500 * 0b010100..Unit layerblend3 input port sec is connected to output of unit fetchwarp2
72501 * 0b010110..Unit layerblend3 input port sec is connected to output of unit fetchdecode0
72502 * 0b011000..Unit layerblend3 input port sec is connected to output of unit fetchdecode1
72503 * 0b011010..Unit layerblend3 input port sec is connected to output of unit fetchlayer0
72504 * 0b011011..Unit layerblend3 input port sec is connected to output of unit matrix4
72505 * 0b011100..Unit layerblend3 input port sec is connected to output of unit hscaler4
72506 * 0b011101..Unit layerblend3 input port sec is connected to output of unit vscaler4
72507 * 0b011110..Unit layerblend3 input port sec is connected to output of unit matrix5
72508 * 0b011111..Unit layerblend3 input port sec is connected to output of unit hscaler5
72509 * 0b100000..Unit layerblend3 input port sec is connected to output of unit vscaler5
72510 */
72511#define IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_sec_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_sec_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_sec_sel_MASK)
72512#define IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_clken_MASK (0x3000000U)
72513#define IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_clken_SHIFT (24U)
72514/*! layerblend3_clken - Enable of layerblend3 clock (this setting has to be the same for all modules
72515 * of one processing pipeline). If a submodule is enabled and FULL is used, then the register
72516 * [endpoint_name]_clk must be set to 0x80.
72517 * 0b00..Clock for layerblend3 is disabled
72518 * 0b01..Clock is enabled if unit is used, frequency is defined by the register setting for this pipeline (see [endpoint_name]_Static register)
72519 * 0b11..Clock for layerblend3 is without gating
72520 */
72521#define IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_clken(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_clken_SHIFT)) & IRIS_MVPL_LAYERBLEND3_DYNAMIC_layerblend3_clken_MASK)
72522/*! @} */
72523
72524/*! @name LAYERBLEND3_STATUS - Status information for pixel engine configuration of layerblend3 */
72525/*! @{ */
72526#define IRIS_MVPL_LAYERBLEND3_STATUS_layerblend3_sel_MASK (0x70000U)
72527#define IRIS_MVPL_LAYERBLEND3_STATUS_layerblend3_sel_SHIFT (16U)
72528/*! layerblend3_sel - Status of the connection of the layerblend3 module
72529 * 0b000..layerblend3 module is not used
72530 * 0b001..layerblend3 module is used from store9 processing path
72531 * 0b010..layerblend3 module is used from extdst0 processing path
72532 * 0b011..layerblend3 module is used from extdst4 processing path
72533 * 0b100..layerblend3 module is used from extdst1 processing path
72534 * 0b101..layerblend3 module is used from extdst5 processing path
72535 */
72536#define IRIS_MVPL_LAYERBLEND3_STATUS_layerblend3_sel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_LAYERBLEND3_STATUS_layerblend3_sel_SHIFT)) & IRIS_MVPL_LAYERBLEND3_STATUS_layerblend3_sel_MASK)
72537/*! @} */
72538
72539/*! @name FETCHDECODE_LOCKUNLOCK_1 - Register to change the protection status of this address block. */
72540/*! @{ */
72541#define IRIS_MVPL_FETCHDECODE_LOCKUNLOCK_1_LockUnlock_MASK (0xFFFFFFFFU)
72542#define IRIS_MVPL_FETCHDECODE_LOCKUNLOCK_1_LockUnlock_SHIFT (0U)
72543/*! LockUnlock - The protection status is changed by writing one of the following key values to this field:
72544 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
72545 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
72546 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
72547 * 0b10110101111000100100011001101110..Disables privilege protection.
72548 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
72549 */
72550#define IRIS_MVPL_FETCHDECODE_LOCKUNLOCK_1_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LOCKUNLOCK_1_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHDECODE_LOCKUNLOCK_1_LockUnlock_MASK)
72551/*! @} */
72552
72553/*! @name FETCHDECODE_LOCKSTATUS_1 - Protection status of this address block. */
72554/*! @{ */
72555#define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_LockStatus_MASK (0x1U)
72556#define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_LockStatus_SHIFT (0U)
72557/*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
72558 */
72559#define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_LockStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_LockStatus_MASK)
72560#define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_PrivilegeStatus_MASK (0x10U)
72561#define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_PrivilegeStatus_SHIFT (4U)
72562/*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
72563 */
72564#define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_PrivilegeStatus_MASK)
72565#define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_FreezeStatus_MASK (0x100U)
72566#define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_FreezeStatus_SHIFT (8U)
72567/*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
72568 */
72569#define IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE_LOCKSTATUS_1_FreezeStatus_MASK)
72570/*! @} */
72571
72572/*! @name FETCHDECODE_STATICCONTRO_1L - Common static control options. */
72573/*! @{ */
72574#define IRIS_MVPL_FETCHDECODE_STATICCONTRO_1L_ShdEn_MASK (0x1U)
72575#define IRIS_MVPL_FETCHDECODE_STATICCONTRO_1L_ShdEn_SHIFT (0U)
72576/*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed).
72577 */
72578#define IRIS_MVPL_FETCHDECODE_STATICCONTRO_1L_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_STATICCONTRO_1L_ShdEn_SHIFT)) & IRIS_MVPL_FETCHDECODE_STATICCONTRO_1L_ShdEn_MASK)
72579#define IRIS_MVPL_FETCHDECODE_STATICCONTRO_1L_BaseAddressAutoUpdate_MASK (0xFF0000U)
72580#define IRIS_MVPL_FETCHDECODE_STATICCONTRO_1L_BaseAddressAutoUpdate_SHIFT (16U)
72581/*! BaseAddressAutoUpdate - Enable flag for continuous shadow load of BaseAddress field for each
72582 * layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded
72583 * from shadow at start of each frame. This update is then executed independently from other RWS
72584 * type fields. ShdEn must be enabled for this mode.
72585 */
72586#define IRIS_MVPL_FETCHDECODE_STATICCONTRO_1L_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_STATICCONTRO_1L_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHDECODE_STATICCONTRO_1L_BaseAddressAutoUpdate_MASK)
72587/*! @} */
72588
72589/*! @name FETCHDECODE_BURSTBUFFERMANAGEMENT_1 - AXI interface buffer management register */
72590/*! @{ */
72591#define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetNumBuffers_MASK (0xFFU)
72592#define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetNumBuffers_SHIFT (0U)
72593/*! SetNumBuffers - Set this to the number of bursts that should be buffered. SetNumBuffers has to
72594 * be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller
72595 * or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum
72596 * allowed settings is 4 except for the fetcheco derivate which has a minimum allowed setting of
72597 * 2.
72598 */
72599#define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetNumBuffers_MASK)
72600#define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_MASK (0x1F00U)
72601#define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_SHIFT (8U)
72602/*! SetBurstLength - Set this to the burst length that should be used on the AXI interface.
72603 * SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers *
72604 * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of
72605 * two may be specified as burst length.
72606 */
72607#define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_SetBurstLength_MASK)
72608#define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_LineMode_MASK (0x80000000U)
72609#define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_LineMode_SHIFT (31U)
72610/*! LineMode - Fetch buffer cache control.
72611 * 0b0..Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact.
72612 * 0b1..Recommended setting for operation in the Blit Engine.
72613 */
72614#define IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_LineMode_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERMANAGEMENT_1_LineMode_MASK)
72615/*! @} */
72616
72617/*! @name FETCHDECODE_RINGBUFSTARTADDR0_1 - Ring buffer setup for layer 0. */
72618/*! @{ */
72619#define IRIS_MVPL_FETCHDECODE_RINGBUFSTARTADDR0_1_RingBufStartAddr0_MASK (0xFFFFFFFFU)
72620#define IRIS_MVPL_FETCHDECODE_RINGBUFSTARTADDR0_1_RingBufStartAddr0_SHIFT (0U)
72621/*! RingBufStartAddr0 - Start address of the ring buffer. Must be aligned to SetBurstLength x 8 bytes.
72622 */
72623#define IRIS_MVPL_FETCHDECODE_RINGBUFSTARTADDR0_1_RingBufStartAddr0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_RINGBUFSTARTADDR0_1_RingBufStartAddr0_SHIFT)) & IRIS_MVPL_FETCHDECODE_RINGBUFSTARTADDR0_1_RingBufStartAddr0_MASK)
72624/*! @} */
72625
72626/*! @name FETCHDECODE_RINGBUFWRAPADDR0_1 - Ring buffer setup for layer 0. */
72627/*! @{ */
72628#define IRIS_MVPL_FETCHDECODE_RINGBUFWRAPADDR0_1_RingBufWrapAddr0_MASK (0xFFFFFFFFU)
72629#define IRIS_MVPL_FETCHDECODE_RINGBUFWRAPADDR0_1_RingBufWrapAddr0_SHIFT (0U)
72630/*! RingBufWrapAddr0 - End address of the ring buffer (last byte of the buffer plus one).
72631 */
72632#define IRIS_MVPL_FETCHDECODE_RINGBUFWRAPADDR0_1_RingBufWrapAddr0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_RINGBUFWRAPADDR0_1_RingBufWrapAddr0_SHIFT)) & IRIS_MVPL_FETCHDECODE_RINGBUFWRAPADDR0_1_RingBufWrapAddr0_MASK)
72633/*! @} */
72634
72635/*! @name FETCHDECODE_FRAMEPROPERTIES0_1 - Frame property setup for layer 0. */
72636/*! @{ */
72637#define IRIS_MVPL_FETCHDECODE_FRAMEPROPERTIES0_1_FieldId0_MASK (0x1U)
72638#define IRIS_MVPL_FETCHDECODE_FRAMEPROPERTIES0_1_FieldId0_SHIFT (0U)
72639/*! FieldId0 - Field identifier that is generated for subsequent units (0 = progressive frame or
72640 * interlaced field with even line indices, 1 = odd field).
72641 */
72642#define IRIS_MVPL_FETCHDECODE_FRAMEPROPERTIES0_1_FieldId0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMEPROPERTIES0_1_FieldId0_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMEPROPERTIES0_1_FieldId0_MASK)
72643/*! @} */
72644
72645/*! @name FETCHDECODE_BASEADDRESS0_1 - Source buffer base address of layer 0. */
72646/*! @{ */
72647#define IRIS_MVPL_FETCHDECODE_BASEADDRESS0_1_BaseAddress0_MASK (0xFFFFFFFFU)
72648#define IRIS_MVPL_FETCHDECODE_BASEADDRESS0_1_BaseAddress0_SHIFT (0U)
72649/*! BaseAddress0 - Byte aligned start address of the layer source buffer. For a pixel width of 32
72650 * bits or DECODE operations BaseAddress[1:0] has to be 0 and for a pixel width of 16 bit
72651 * BaseAddress[0] has to be 0.
72652 */
72653#define IRIS_MVPL_FETCHDECODE_BASEADDRESS0_1_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BASEADDRESS0_1_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHDECODE_BASEADDRESS0_1_BaseAddress0_MASK)
72654/*! @} */
72655
72656/*! @name FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1 - Source buffer attributes for layer 0. */
72657/*! @{ */
72658#define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1_Stride0_MASK (0xFFFFU)
72659#define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1_Stride0_SHIFT (0U)
72660/*! Stride0 - Source buffer stride of the layer in bytes minus one, used for address generation. For
72661 * a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel
72662 * width of 16 bit Stride has to be dividable by two and given minus one.
72663 */
72664#define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1_Stride0_SHIFT)) & IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1_Stride0_MASK)
72665#define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1_BitsPerPixel0_MASK (0x3F0000U)
72666#define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1_BitsPerPixel0_SHIFT (16U)
72667/*! BitsPerPixel0 - Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or
72668 * 32. Exception: FetchEco does not support 18 and 24.
72669 */
72670#define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHDECODE_SOURCEBUFFERATTRIBUTES0_1_BitsPerPixel0_MASK)
72671/*! @} */
72672
72673/*! @name FETCHDECODE_SOURCEBUFFERDIMENSION0_1 - Source buffer dimension of layer 0. */
72674/*! @{ */
72675#define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_1_LineWidth0_MASK (0x3FFFU)
72676#define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_1_LineWidth0_SHIFT (0U)
72677/*! LineWidth0 - Width of the source buffer of the layer in pixels minus one.
72678 */
72679#define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_1_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_1_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_1_LineWidth0_MASK)
72680#define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_1_LineCount0_MASK (0x3FFF0000U)
72681#define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_1_LineCount0_SHIFT (16U)
72682/*! LineCount0 - Number of lines of the source buffer of the layer minus one.
72683 */
72684#define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_1_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_1_LineCount0_SHIFT)) & IRIS_MVPL_FETCHDECODE_SOURCEBUFFERDIMENSION0_1_LineCount0_MASK)
72685/*! @} */
72686
72687/*! @name FETCHDECODE_COLORCOMPONENTBITS0_1 - Size of color components for RGB, YUV and index formats (layer 0). */
72688/*! @{ */
72689#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsAlpha0_MASK (0xFU)
72690#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsAlpha0_SHIFT (0U)
72691/*! ComponentBitsAlpha0 - Alpha.
72692 */
72693#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsAlpha0_MASK)
72694#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsBlue0_MASK (0xF00U)
72695#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsBlue0_SHIFT (8U)
72696/*! ComponentBitsBlue0 - Blue and V (chroma).
72697 */
72698#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsBlue0_MASK)
72699#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsGreen0_MASK (0xF0000U)
72700#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsGreen0_SHIFT (16U)
72701/*! ComponentBitsGreen0 - Green and U (chroma).
72702 */
72703#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsGreen0_MASK)
72704#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsRed0_MASK (0xF000000U)
72705#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsRed0_SHIFT (24U)
72706/*! ComponentBitsRed0 - Red, Y (luma) and palette index.
72707 */
72708#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ComponentBitsRed0_MASK)
72709#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ITUFormat0_MASK (0x80000000U)
72710#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ITUFormat0_SHIFT (31U)
72711/*! ITUFormat0 - When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then
72712 * input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This
72713 * is compliant to ITU 656 standard.
72714 */
72715#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTBITS0_1_ITUFormat0_MASK)
72716/*! @} */
72717
72718/*! @name FETCHDECODE_COLORCOMPONENTSHIFT0_1 - Bit position of color components for RGB, YUV and index formats (layer 0). */
72719/*! @{ */
72720#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftAlpha0_MASK (0x1FU)
72721#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftAlpha0_SHIFT (0U)
72722/*! ComponentShiftAlpha0 - Alpha.
72723 */
72724#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftAlpha0_MASK)
72725#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftBlue0_MASK (0x1F00U)
72726#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftBlue0_SHIFT (8U)
72727/*! ComponentShiftBlue0 - Blue and V (chroma).
72728 */
72729#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftBlue0_MASK)
72730#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftGreen0_MASK (0x1F0000U)
72731#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftGreen0_SHIFT (16U)
72732/*! ComponentShiftGreen0 - Green and U (chroma).
72733 */
72734#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftGreen0_MASK)
72735#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftRed0_MASK (0x1F000000U)
72736#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftRed0_SHIFT (24U)
72737/*! ComponentShiftRed0 - Red, Y (luma) and palette index.
72738 */
72739#define IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE_COLORCOMPONENTSHIFT0_1_ComponentShiftRed0_MASK)
72740/*! @} */
72741
72742/*! @name FETCHDECODE_LAYEROFFSET0_1 - Position of layer 0 within the destination frame. */
72743/*! @{ */
72744#define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_1_LayerXOffset0_MASK (0x7FFFU)
72745#define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_1_LayerXOffset0_SHIFT (0U)
72746/*! LayerXOffset0 - Horizontal offset (X).
72747 */
72748#define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_1_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_1_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_1_LayerXOffset0_MASK)
72749#define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_1_LayerYOffset0_MASK (0x7FFF0000U)
72750#define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_1_LayerYOffset0_SHIFT (16U)
72751/*! LayerYOffset0 - Vertical offset (Y).
72752 */
72753#define IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_1_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_1_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYEROFFSET0_1_LayerYOffset0_MASK)
72754/*! @} */
72755
72756/*! @name FETCHDECODE_CLIPWINDOWOFFSET0_1 - Clip window position for layer 0. */
72757/*! @{ */
72758#define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_1_ClipWindowXOffset0_MASK (0x7FFFU)
72759#define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_1_ClipWindowXOffset0_SHIFT (0U)
72760/*! ClipWindowXOffset0 - Horizontal position (X).
72761 */
72762#define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_1_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_1_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_1_ClipWindowXOffset0_MASK)
72763#define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_1_ClipWindowYOffset0_MASK (0x7FFF0000U)
72764#define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_1_ClipWindowYOffset0_SHIFT (16U)
72765/*! ClipWindowYOffset0 - Vertical position (Y).
72766 */
72767#define IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_1_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_1_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CLIPWINDOWOFFSET0_1_ClipWindowYOffset0_MASK)
72768/*! @} */
72769
72770/*! @name FETCHDECODE_CLIPWINDOWDIMENSIONS0_1 - Clip window size for layer 0. */
72771/*! @{ */
72772#define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_1_ClipWindowWidth0_MASK (0x3FFFU)
72773#define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_1_ClipWindowWidth0_SHIFT (0U)
72774/*! ClipWindowWidth0 - Width.
72775 */
72776#define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_1_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_1_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_1_ClipWindowWidth0_MASK)
72777#define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_1_ClipWindowHeight0_MASK (0x3FFF0000U)
72778#define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_1_ClipWindowHeight0_SHIFT (16U)
72779/*! ClipWindowHeight0 - Height.
72780 */
72781#define IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_1_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_1_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CLIPWINDOWDIMENSIONS0_1_ClipWindowHeight0_MASK)
72782/*! @} */
72783
72784/*! @name FETCHDECODE_CONSTANTCOLOR0_1 - Constant color for layer 0. */
72785/*! @{ */
72786#define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantAlpha0_MASK (0xFFU)
72787#define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantAlpha0_SHIFT (0U)
72788/*! ConstantAlpha0 - Alpha.
72789 */
72790#define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantAlpha0_MASK)
72791#define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantBlue0_MASK (0xFF00U)
72792#define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantBlue0_SHIFT (8U)
72793/*! ConstantBlue0 - Blue and V (chroma).
72794 */
72795#define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantBlue0_MASK)
72796#define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantGreen0_MASK (0xFF0000U)
72797#define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantGreen0_SHIFT (16U)
72798/*! ConstantGreen0 - Green and U (chroma).
72799 */
72800#define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantGreen0_MASK)
72801#define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantRed0_MASK (0xFF000000U)
72802#define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantRed0_SHIFT (24U)
72803/*! ConstantRed0 - Red and Y (luma).
72804 */
72805#define IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONSTANTCOLOR0_1_ConstantRed0_MASK)
72806/*! @} */
72807
72808/*! @name FETCHDECODE_LAYERPROPERTY0_1 - Common properties of layer 0. */
72809/*! @{ */
72810#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_PaletteEnable0_MASK (0x1U)
72811#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_PaletteEnable0_SHIFT (0U)
72812/*! PaletteEnable0 - Enables (value = 1) a color palette with 8 bits input and 24 bits output. Lower
72813 * bits of the lookup index are read from memory (PaletteIdxWidth), upper bits are set to index
72814 * of this layer. Palette output is extended by upper bits of index word read from memory (e.g.
72815 * to store alpha together with index). Result is mapped to color channels according to
72816 * ColorComponentBits/Shift settings.
72817 */
72818#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_PaletteEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_PaletteEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_PaletteEnable0_MASK)
72819#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_TileMode0_MASK (0x30U)
72820#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_TileMode0_SHIFT (4U)
72821/*! TileMode0 - Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0)
72822 * takes precedence if a pixel becomes subject to both tiling and clipping.
72823 * 0b00..Use zero value
72824 * 0b01..Use constant color register value
72825 * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0.
72826 * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422
72827 * operations or when SourceBufferEnable is 0.
72828 */
72829#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_TileMode0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_TileMode0_MASK)
72830#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaSrcEnable0_MASK (0x100U)
72831#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaSrcEnable0_SHIFT (8U)
72832/*! AlphaSrcEnable0 - Value 1 enables source alpha for computing the output alpha. When disabled source alpha is set to 1.
72833 */
72834#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaSrcEnable0_MASK)
72835#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaConstEnable0_MASK (0x200U)
72836#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaConstEnable0_SHIFT (9U)
72837/*! AlphaConstEnable0 - Value 1 enables constant alpha for computing the output alpha. When disabled constant alpha is set to 1.
72838 */
72839#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaConstEnable0_MASK)
72840#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaMaskEnable0_MASK (0x400U)
72841#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaMaskEnable0_SHIFT (10U)
72842/*! AlphaMaskEnable0 - Value 1 enables mask alpha for computing the output alpha. When disabled mask alpha is set to 1.
72843 */
72844#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaMaskEnable0_MASK)
72845#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaTransEnable0_MASK (0x800U)
72846#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaTransEnable0_SHIFT (11U)
72847/*! AlphaTransEnable0 - Value 1 enables transparent alpha for computing the output alpha. When disabled transparent alpha is set to 1.
72848 */
72849#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_AlphaTransEnable0_MASK)
72850#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaSrcEnable0_MASK (0x1000U)
72851#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaSrcEnable0_SHIFT (12U)
72852/*! RGBAlphaSrcEnable0 - Value 1 enables source alpha (stored together with color component in the
72853 * source buffer) for RGB pre-multiply. When disabled source alpha is set to 1.
72854 */
72855#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaSrcEnable0_MASK)
72856#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaConstEnable0_MASK (0x2000U)
72857#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaConstEnable0_SHIFT (13U)
72858/*! RGBAlphaConstEnable0 - Value 1 enables constant alpha (ConstAlpha fields) for RGB pre-multiply. When disabled constant alpha is set to 1.
72859 */
72860#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaConstEnable0_MASK)
72861#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaMaskEnable0_MASK (0x4000U)
72862#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaMaskEnable0_SHIFT (14U)
72863/*! RGBAlphaMaskEnable0 - Value 1 enables mask alpha (read by another Fetch unit from a separate
72864 * alpha layer) for RGB pre-multiply. When disabled mask alpha is set to 1. Alpha mask input must be
72865 * enabled for this field to have effect.
72866 */
72867#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaMaskEnable0_MASK)
72868#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaTransEnable0_MASK (0x8000U)
72869#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaTransEnable0_SHIFT (15U)
72870/*! RGBAlphaTransEnable0 - Value 1 enables transparent alpha (0 or 1 depending on RGB matching
72871 * ConstantColor setting) for RGB pre-multiply. When disabled transparent alpha is set to 1.
72872 */
72873#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_RGBAlphaTransEnable0_MASK)
72874#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_PremulConstRGB0_MASK (0x10000U)
72875#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_PremulConstRGB0_SHIFT (16U)
72876/*! PremulConstRGB0 - When enabled (value 1) the values given by ConstantRed/Green/Blue are used
72877 * instead of alpha for source RGB pre-multiply. Settings RGBAlphaSrc/Const/Mask/TransEnable have no
72878 * effect then.
72879 */
72880#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_PremulConstRGB0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_PremulConstRGB0_MASK)
72881#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_YUVConversionMode0_MASK (0x60000U)
72882#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_YUVConversionMode0_SHIFT (17U)
72883/*! YUVConversionMode0 - Enables different kind of YUV to RGB conversions.
72884 * 0b00..No conversion.
72885 * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV).
72886 * Input range is 16..235 for Y and 16..240 for U/V.
72887 * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV
72888 * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding).
72889 * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV).
72890 * Input range is 16..235 for Y and 16..240 for U/V.
72891 */
72892#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_YUVConversionMode0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_YUVConversionMode0_MASK)
72893#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_GammaRemoveEnable0_MASK (0x100000U)
72894#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_GammaRemoveEnable0_SHIFT (20U)
72895/*! GammaRemoveEnable0 - Value 1 enables the stage to remove a gamma from RGB components.
72896 */
72897#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_GammaRemoveEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_GammaRemoveEnable0_MASK)
72898#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_ClipWindowEnable0_MASK (0x40000000U)
72899#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_ClipWindowEnable0_SHIFT (30U)
72900/*! ClipWindowEnable0 - Value 1 enables the clip window for this layer. Pixels outside the clip
72901 * window get the clip color, pixels inside the source or tiling color.
72902 */
72903#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_ClipWindowEnable0_MASK)
72904#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_SourceBufferEnable0_MASK (0x80000000U)
72905#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_SourceBufferEnable0_SHIFT (31U)
72906/*! SourceBufferEnable0 - Value 1 enables the source buffer for this layer. When disabled the tiling
72907 * color is used only (TileMode TILE_PAD not allowed).
72908 */
72909#define IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHDECODE_LAYERPROPERTY0_1_SourceBufferEnable0_MASK)
72910/*! @} */
72911
72912/*! @name FETCHDECODE_FRAMEDIMENSIONS_1 - Output frame dimension. */
72913/*! @{ */
72914#define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_FrameWidth_MASK (0x3FFFU)
72915#define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_FrameWidth_SHIFT (0U)
72916/*! FrameWidth - Frame width minus one.
72917 */
72918#define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_FrameWidth_MASK)
72919#define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_FrameHeight_MASK (0x3FFF0000U)
72920#define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_FrameHeight_SHIFT (16U)
72921/*! FrameHeight - Frame height minus one.
72922 */
72923#define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_FrameHeight_MASK)
72924#define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_EmptyFrame_MASK (0x80000000U)
72925#define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_EmptyFrame_SHIFT (31U)
72926/*! EmptyFrame - When enabled output frame is empty. FrameWidth/Height settings have no effect then.
72927 * Can be used to load shadows or to generate synchronization signals only (frame/sequence
72928 * complete). If enabled, InputSelect must be set to INACTIVE.
72929 */
72930#define IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMEDIMENSIONS_1_EmptyFrame_MASK)
72931/*! @} */
72932
72933/*! @name FETCHDECODE_FRAMERESAMPLING_1 - Resampling options for output frame. */
72934/*! @{ */
72935#define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_StartX_MASK (0x3FU)
72936#define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_StartX_SHIFT (0U)
72937/*! StartX - X coordinate of first sample point relative to origin.
72938 */
72939#define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_StartX_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_StartX_MASK)
72940#define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_StartY_MASK (0xFC0U)
72941#define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_StartY_SHIFT (6U)
72942/*! StartY - Y coordinate of first sample point relative to origin.
72943 */
72944#define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_StartY_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_StartY_MASK)
72945#define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_DeltaX_MASK (0x3F000U)
72946#define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_DeltaX_SHIFT (12U)
72947/*! DeltaX - Increment of X coordinate for horizontal step in destination frame.
72948 */
72949#define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_DeltaX_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_DeltaX_MASK)
72950#define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_DeltaY_MASK (0xFC0000U)
72951#define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_DeltaY_SHIFT (18U)
72952/*! DeltaY - Increment of Y coordinate for vertical step in destination frame.
72953 */
72954#define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_DeltaY_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_DeltaY_MASK)
72955#define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_SwapDirection_MASK (0x1000000U)
72956#define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_SwapDirection_SHIFT (24U)
72957/*! SwapDirection - Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied
72958 * for horizontal and DeltaX for vertical step on destination frame.
72959 */
72960#define IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHDECODE_FRAMERESAMPLING_1_SwapDirection_MASK)
72961/*! @} */
72962
72963/*! @name FETCHDECODE_DECODECONTROL_1 - Control options for RLAD decompression. */
72964/*! @{ */
72965#define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_CompressionMode_MASK (0x3U)
72966#define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_CompressionMode_SHIFT (0U)
72967/*! CompressionMode - Algorithm that the encoder used for compression.
72968 * 0b00..Run-Length Adaptive Dithering (lossy compression).
72969 * 0b01..Run-Length Adaptive Dithering (lossy compression; uniform package size).
72970 * 0b10..Run-Length Adaptive (lossless compression).
72971 * 0b11..Standard Run-Length.
72972 */
72973#define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_CompressionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_CompressionMode_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_CompressionMode_MASK)
72974#define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADEndianness_MASK (0x8000U)
72975#define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADEndianness_SHIFT (15U)
72976/*! RLADEndianness - Changes endianness of decoder for RL mode, does not affect any other CompressionModes
72977 * 0b0..Big endian format
72978 * 0b1..Little endian format
72979 */
72980#define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADEndianness(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADEndianness_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADEndianness_MASK)
72981#define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsRed_MASK (0xF0000U)
72982#define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsRed_SHIFT (16U)
72983/*! RLADCompBitsRed - Maximum for average number of bits per compressed pixel for Red or Y (luma)
72984 * channel. This must match the corresponding encoder setting.
72985 */
72986#define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsRed_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsRed_MASK)
72987#define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsGreen_MASK (0xF00000U)
72988#define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsGreen_SHIFT (20U)
72989/*! RLADCompBitsGreen - Maximum for average number of bits per compressed pixel for Green or U
72990 * (chroma) channel. This must match the corresponding encoder setting.
72991 */
72992#define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsGreen_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsGreen_MASK)
72993#define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsBlue_MASK (0xF000000U)
72994#define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsBlue_SHIFT (24U)
72995/*! RLADCompBitsBlue - Maximum for average number of bits per compressed pixel for Blue or V
72996 * (chroma) channel. This must match the corresponding encoder setting.
72997 */
72998#define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsBlue_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsBlue_MASK)
72999#define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsAlpha_MASK (0xF0000000U)
73000#define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsAlpha_SHIFT (28U)
73001/*! RLADCompBitsAlpha - Maximum for average number of bits per compressed pixel for Alpha channel.
73002 * This must match the corresponding encoder setting.
73003 */
73004#define IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsAlpha_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODECONTROL_1_RLADCompBitsAlpha_MASK)
73005/*! @} */
73006
73007/*! @name FETCHDECODE_SOURCEBUFFERLENGTH_1 - Source buffer length for compressed data. */
73008/*! @{ */
73009#define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERLENGTH_1_RLEWords_MASK (0x1FFFFFFFU)
73010#define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERLENGTH_1_RLEWords_SHIFT (0U)
73011/*! RLEWords - Number of 32-bit words minus one that are required to decode the run length encoded source buffer.
73012 */
73013#define IRIS_MVPL_FETCHDECODE_SOURCEBUFFERLENGTH_1_RLEWords(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_SOURCEBUFFERLENGTH_1_RLEWords_SHIFT)) & IRIS_MVPL_FETCHDECODE_SOURCEBUFFERLENGTH_1_RLEWords_MASK)
73014/*! @} */
73015
73016/*! @name FETCHDECODE_CONTROL_1 - Shared common control settings for all layers. */
73017/*! @{ */
73018#define IRIS_MVPL_FETCHDECODE_CONTROL_1_RasterMode_MASK (0x7U)
73019#define IRIS_MVPL_FETCHDECODE_CONTROL_1_RasterMode_SHIFT (0U)
73020/*! RasterMode - Selects a method how to generate source buffer sample points.
73021 * 0b000..First sample at StartX/Y relative to origin. Hor/ver increments using DeltaX/Y and DeltaSwap setup.
73022 * 0b001..[FetchDecode/FetchDecodeL only] Source buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1).
73023 * 0b010..[FetchPersp/Warp/Rot/RotL only] Arbitrary warping (filter is active). Coordinates are read from frame
73024 * input port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY must be setup.
73025 * 0b011..[FetchPersp only] Affine/Perspective warping (filter is active). First sample at PerspStartX/Y/W.
73026 * Hor/ver increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates.
73027 * 0b100..[FetchPersp/Decode only] Source buffer is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver
73028 * increments = (1,0)/(0,1). All corellated window widths and horizontal offsets must be even.
73029 * 0b101..[FetchRot/RotL only] Affine warping (filter is active). First sample at AffineStartX/Y. Hor/ver
73030 * increments using AffineDeltaXX/XY/YX/YY. Cartesian coordinates.
73031 */
73032#define IRIS_MVPL_FETCHDECODE_CONTROL_1_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_1_RasterMode_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_1_RasterMode_MASK)
73033#define IRIS_MVPL_FETCHDECODE_CONTROL_1_InputSelect_MASK (0x18U)
73034#define IRIS_MVPL_FETCHDECODE_CONTROL_1_InputSelect_SHIFT (3U)
73035/*! InputSelect - Selects function for the frame input port.
73036 * 0b00..Not used.
73037 * 0b01..Used for component packing (e.g. UV or source alpha buffer).
73038 * 0b10..Used for RGB and alpha pre-multiply stage (mask alpha buffer).
73039 * 0b11..Used for arbitrary warping (coordinate buffer).
73040 */
73041#define IRIS_MVPL_FETCHDECODE_CONTROL_1_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_1_InputSelect_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_1_InputSelect_MASK)
73042#define IRIS_MVPL_FETCHDECODE_CONTROL_1_YUV422UpsamplingMode_MASK (0x20U)
73043#define IRIS_MVPL_FETCHDECODE_CONTROL_1_YUV422UpsamplingMode_SHIFT (5U)
73044/*! YUV422UpsamplingMode - Selects a method for horizontal up-sampling of YUV 4:2:2/4:2:0 input data.
73045 * 0b0..Replicate mode for interspersed samples (UV samples between Y samples).
73046 * 0b1..Interpolate mode for coaligned samples (UV samples at Y sample positions).
73047 */
73048#define IRIS_MVPL_FETCHDECODE_CONTROL_1_YUV422UpsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_1_YUV422UpsamplingMode_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_1_YUV422UpsamplingMode_MASK)
73049#define IRIS_MVPL_FETCHDECODE_CONTROL_1_RawPixel_MASK (0x80U)
73050#define IRIS_MVPL_FETCHDECODE_CONTROL_1_RawPixel_SHIFT (7U)
73051/*! RawPixel - Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced
73052 * for all layers by fixed values that allow passing the pixel data read from memory unchanged
73053 * to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color
73054 * are deactived. Skip and Tile pixels are not affected by this setting.
73055 */
73056#define IRIS_MVPL_FETCHDECODE_CONTROL_1_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_1_RawPixel_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_1_RawPixel_MASK)
73057#define IRIS_MVPL_FETCHDECODE_CONTROL_1_PaletteIdxWidth_MASK (0x700U)
73058#define IRIS_MVPL_FETCHDECODE_CONTROL_1_PaletteIdxWidth_SHIFT (8U)
73059/*! PaletteIdxWidth - Number minus one of least significant bits of pixel data read from the source
73060 * buffer that are used as index value for color palette look-up.
73061 */
73062#define IRIS_MVPL_FETCHDECODE_CONTROL_1_PaletteIdxWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_1_PaletteIdxWidth_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_1_PaletteIdxWidth_MASK)
73063#define IRIS_MVPL_FETCHDECODE_CONTROL_1_ClipColor_MASK (0x10000U)
73064#define IRIS_MVPL_FETCHDECODE_CONTROL_1_ClipColor_SHIFT (16U)
73065/*! ClipColor - Selects which color to take for pixels that do not lie inside the clip window of any layer.
73066 * 0b0..Null color.
73067 * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is
73068 * then the layer's source or tiling color.
73069 */
73070#define IRIS_MVPL_FETCHDECODE_CONTROL_1_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROL_1_ClipColor_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROL_1_ClipColor_MASK)
73071/*! @} */
73072
73073/*! @name FETCHDECODE_CONTROLTRIGGER_1 - Shadow load trigger. */
73074/*! @{ */
73075#define IRIS_MVPL_FETCHDECODE_CONTROLTRIGGER_1_ShdTokGen_MASK (0x1U)
73076#define IRIS_MVPL_FETCHDECODE_CONTROLTRIGGER_1_ShdTokGen_SHIFT (0U)
73077/*! ShdTokGen - Writing a 1 to this will load shadow registers into the active configuration with
73078 * the next start of frame and send a shadow load token to subsequent units.
73079 */
73080#define IRIS_MVPL_FETCHDECODE_CONTROLTRIGGER_1_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_CONTROLTRIGGER_1_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHDECODE_CONTROLTRIGGER_1_ShdTokGen_MASK)
73081/*! @} */
73082
73083/*! @name FETCHDECODE_START_1 - Frame start trigger. */
73084/*! @{ */
73085#define IRIS_MVPL_FETCHDECODE_START_1_Start_MASK (0x1U)
73086#define IRIS_MVPL_FETCHDECODE_START_1_Start_SHIFT (0U)
73087/*! Start - Writing a 1 to this field will start generating one frame (for debugging purposes only).
73088 */
73089#define IRIS_MVPL_FETCHDECODE_START_1_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_START_1_Start_SHIFT)) & IRIS_MVPL_FETCHDECODE_START_1_Start_MASK)
73090/*! @} */
73091
73092/*! @name FETCHDECODE_FETCHTYPE_1 - Fetch unit type. */
73093/*! @{ */
73094#define IRIS_MVPL_FETCHDECODE_FETCHTYPE_1_FetchType_MASK (0xFU)
73095#define IRIS_MVPL_FETCHDECODE_FETCHTYPE_1_FetchType_SHIFT (0U)
73096/*! FetchType - This field can be used to determine what kind of fetch unit this is.
73097 * 0b0000..Fetch unit with RL and RLAD decoder.
73098 * 0b0001..Fetch unit with fractional plane (8 layers).
73099 * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers).
73100 * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes.
73101 * 0b0100..Fetch unit with affine, perspective and arbitrary warping.
73102 * 0b0101..Fetch unit with affine and arbitrary warping.
73103 * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set.
73104 * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set.
73105 * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set.
73106 */
73107#define IRIS_MVPL_FETCHDECODE_FETCHTYPE_1_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_FETCHTYPE_1_FetchType_SHIFT)) & IRIS_MVPL_FETCHDECODE_FETCHTYPE_1_FetchType_MASK)
73108/*! @} */
73109
73110/*! @name FETCHDECODE_DECODERSTATUS_1 - Status information of the RLAD decoder. */
73111/*! @{ */
73112#define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_1_BufferTooSmall_MASK (0x1U)
73113#define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_1_BufferTooSmall_SHIFT (0U)
73114/*! BufferTooSmall - The buffer size given by RLEWords is too small. No complete output frame could be decoded.
73115 */
73116#define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_1_BufferTooSmall(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODERSTATUS_1_BufferTooSmall_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODERSTATUS_1_BufferTooSmall_MASK)
73117#define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_1_BufferTooLarge_MASK (0x2U)
73118#define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_1_BufferTooLarge_SHIFT (1U)
73119/*! BufferTooLarge - The buffer size given by RLEWords is too large. A complete output frame could
73120 * be decoded, but more data was read than necessary.
73121 */
73122#define IRIS_MVPL_FETCHDECODE_DECODERSTATUS_1_BufferTooLarge(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_DECODERSTATUS_1_BufferTooLarge_SHIFT)) & IRIS_MVPL_FETCHDECODE_DECODERSTATUS_1_BufferTooLarge_MASK)
73123/*! @} */
73124
73125/*! @name FETCHDECODE_READADDRESS0_1 - Ring buffer synchronization for layer 0. */
73126/*! @{ */
73127#define IRIS_MVPL_FETCHDECODE_READADDRESS0_1_ReadAddress0_MASK (0xFFFFFFFFU)
73128#define IRIS_MVPL_FETCHDECODE_READADDRESS0_1_ReadAddress0_SHIFT (0U)
73129/*! ReadAddress0 - Last burst address that was read from the layer's source buffer.
73130 */
73131#define IRIS_MVPL_FETCHDECODE_READADDRESS0_1_ReadAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_READADDRESS0_1_ReadAddress0_SHIFT)) & IRIS_MVPL_FETCHDECODE_READADDRESS0_1_ReadAddress0_MASK)
73132/*! @} */
73133
73134/*! @name FETCHDECODE_BURSTBUFFERPROPERTIES_1 - Burst buffer properties. */
73135/*! @{ */
73136#define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_1_ManagedBurstBuffers_MASK (0xFFU)
73137#define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_1_ManagedBurstBuffers_SHIFT (0U)
73138/*! ManagedBurstBuffers - Maximum number of burst buffers that can be administrated in the AXI interface.
73139 */
73140#define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_1_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_1_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_1_ManagedBurstBuffers_MASK)
73141#define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_1_BurstLengthForMaxBuffers_MASK (0x1F00U)
73142#define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_1_BurstLengthForMaxBuffers_SHIFT (8U)
73143/*! BurstLengthForMaxBuffers - Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used.
73144 */
73145#define IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_1_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_1_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHDECODE_BURSTBUFFERPROPERTIES_1_BurstLengthForMaxBuffers_MASK)
73146/*! @} */
73147
73148/*! @name FETCHDECODE_STATUS_1 - Status informations. */
73149/*! @{ */
73150#define IRIS_MVPL_FETCHDECODE_STATUS_1_WriteTimeout_MASK (0x1U)
73151#define IRIS_MVPL_FETCHDECODE_STATUS_1_WriteTimeout_SHIFT (0U)
73152/*! WriteTimeout - Timeout detected when writing to the palette entries or shadow token trigger
73153 * enables in fetchlayer derivate. Write 1 to clear.
73154 */
73155#define IRIS_MVPL_FETCHDECODE_STATUS_1_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_STATUS_1_WriteTimeout_SHIFT)) & IRIS_MVPL_FETCHDECODE_STATUS_1_WriteTimeout_MASK)
73156#define IRIS_MVPL_FETCHDECODE_STATUS_1_ReadTimeout_MASK (0x10U)
73157#define IRIS_MVPL_FETCHDECODE_STATUS_1_ReadTimeout_SHIFT (4U)
73158/*! ReadTimeout - Timeout detected when reading from the palette entries or shadow token trigger
73159 * enables in fetchlayer derivate. Write 1 to clear.
73160 */
73161#define IRIS_MVPL_FETCHDECODE_STATUS_1_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_STATUS_1_ReadTimeout_SHIFT)) & IRIS_MVPL_FETCHDECODE_STATUS_1_ReadTimeout_MASK)
73162/*! @} */
73163
73164/*! @name FETCHDECODE_HIDDENSTATUS_1 - Hidden status informations. */
73165/*! @{ */
73166#define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusBusy_MASK (0x1U)
73167#define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusBusy_SHIFT (0U)
73168/*! StatusBusy - Fetch unit is busy.
73169 */
73170#define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusBusy_MASK)
73171#define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusBuffersIdle_MASK (0x10U)
73172#define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusBuffersIdle_SHIFT (4U)
73173/*! StatusBuffersIdle - AXI interface buffers are idle.
73174 */
73175#define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusBuffersIdle_MASK)
73176#define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusRequest_MASK (0x20U)
73177#define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusRequest_SHIFT (5U)
73178/*! StatusRequest - Fetch unit requesting on the AXI interface, waiting for acknowledge.
73179 */
73180#define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusRequest_MASK)
73181#define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusComplete_MASK (0x40U)
73182#define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusComplete_SHIFT (6U)
73183/*! StatusComplete - Fetch unit completed all requested AXI transfers.
73184 */
73185#define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_StatusComplete_MASK)
73186#define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_ShadowStatus_MASK (0xFF00U)
73187#define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_ShadowStatus_SHIFT (8U)
73188/*! ShadowStatus - Shadow load status for all layers (layer index = bit index).
73189 */
73190#define IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHDECODE_HIDDENSTATUS_1_ShadowStatus_MASK)
73191/*! @} */
73192
73193/*! @name COLORPALETTE_1 - Color palette look up table. */
73194/*! @{ */
73195#define IRIS_MVPL_COLORPALETTE_1_ColorPalette_MASK (0xFFFFFFU)
73196#define IRIS_MVPL_COLORPALETTE_1_ColorPalette_SHIFT (0U)
73197/*! ColorPalette - Entry of the color palette look-up table
73198 */
73199#define IRIS_MVPL_COLORPALETTE_1_ColorPalette(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_COLORPALETTE_1_ColorPalette_SHIFT)) & IRIS_MVPL_COLORPALETTE_1_ColorPalette_MASK)
73200/*! @} */
73201
73202/*! @name FETCHWARP9_LOCKUNLOCK - Register to change the protection status of this address block. */
73203/*! @{ */
73204#define IRIS_MVPL_FETCHWARP9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
73205#define IRIS_MVPL_FETCHWARP9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
73206/*! LockUnlock - The protection status is changed by writing one of the following key values to this field:
73207 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
73208 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
73209 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
73210 * 0b10110101111000100100011001101110..Disables privilege protection.
73211 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
73212 */
73213#define IRIS_MVPL_FETCHWARP9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHWARP9_LOCKUNLOCK_LockUnlock_MASK)
73214/*! @} */
73215
73216/*! @name FETCHWARP9_LOCKSTATUS - Protection status of this address block. */
73217/*! @{ */
73218#define IRIS_MVPL_FETCHWARP9_LOCKSTATUS_LockStatus_MASK (0x1U)
73219#define IRIS_MVPL_FETCHWARP9_LOCKSTATUS_LockStatus_SHIFT (0U)
73220/*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
73221 */
73222#define IRIS_MVPL_FETCHWARP9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHWARP9_LOCKSTATUS_LockStatus_MASK)
73223#define IRIS_MVPL_FETCHWARP9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
73224#define IRIS_MVPL_FETCHWARP9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
73225/*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
73226 */
73227#define IRIS_MVPL_FETCHWARP9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHWARP9_LOCKSTATUS_PrivilegeStatus_MASK)
73228#define IRIS_MVPL_FETCHWARP9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
73229#define IRIS_MVPL_FETCHWARP9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
73230/*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
73231 */
73232#define IRIS_MVPL_FETCHWARP9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHWARP9_LOCKSTATUS_FreezeStatus_MASK)
73233/*! @} */
73234
73235/*! @name FETCHWARP9_STATICCONTROL - Common static control options. */
73236/*! @{ */
73237#define IRIS_MVPL_FETCHWARP9_STATICCONTROL_ShdEn_MASK (0x1U)
73238#define IRIS_MVPL_FETCHWARP9_STATICCONTROL_ShdEn_SHIFT (0U)
73239/*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed).
73240 */
73241#define IRIS_MVPL_FETCHWARP9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHWARP9_STATICCONTROL_ShdEn_MASK)
73242#define IRIS_MVPL_FETCHWARP9_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U)
73243#define IRIS_MVPL_FETCHWARP9_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U)
73244/*! BaseAddressAutoUpdate - Enable flag for continuous shadow load of BaseAddress field for each
73245 * layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded
73246 * from shadow at start of each frame. This update is then executed independently from other RWS
73247 * type fields. ShdEn must be enabled for this mode.
73248 */
73249#define IRIS_MVPL_FETCHWARP9_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHWARP9_STATICCONTROL_BaseAddressAutoUpdate_MASK)
73250#define IRIS_MVPL_FETCHWARP9_STATICCONTROL_ShdLdReqSticky_MASK (0xFF000000U)
73251#define IRIS_MVPL_FETCHWARP9_STATICCONTROL_ShdLdReqSticky_SHIFT (24U)
73252/*! ShdLdReqSticky - Shadow load request flags for each layer (always load). See description of
73253 * register TriggerEnable for further information.
73254 */
73255#define IRIS_MVPL_FETCHWARP9_STATICCONTROL_ShdLdReqSticky(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_STATICCONTROL_ShdLdReqSticky_SHIFT)) & IRIS_MVPL_FETCHWARP9_STATICCONTROL_ShdLdReqSticky_MASK)
73256/*! @} */
73257
73258/*! @name FETCHWARP9_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */
73259/*! @{ */
73260#define IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU)
73261#define IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U)
73262/*! SetNumBuffers - Set this to the number of bursts that should be buffered. SetNumBuffers has to
73263 * be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller
73264 * or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum
73265 * allowed settings is 4 except for the fetcheco derivate which has a minimum allowed setting of
73266 * 2.
73267 */
73268#define IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK)
73269#define IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U)
73270#define IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U)
73271/*! SetBurstLength - Set this to the burst length that should be used on the AXI interface.
73272 * SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers *
73273 * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of
73274 * two may be specified as burst length.
73275 */
73276#define IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK)
73277#define IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U)
73278#define IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U)
73279/*! LineMode - Fetch buffer cache control.
73280 * 0b0..Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact.
73281 * 0b1..Recommended setting for operation in the Blit Engine.
73282 */
73283#define IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHWARP9_BURSTBUFFERMANAGEMENT_LineMode_MASK)
73284/*! @} */
73285
73286/*! @name FETCHWARP9_BASEADDRESS0 - Source buffer base address of layer 0. */
73287/*! @{ */
73288#define IRIS_MVPL_FETCHWARP9_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU)
73289#define IRIS_MVPL_FETCHWARP9_BASEADDRESS0_BaseAddress0_SHIFT (0U)
73290/*! BaseAddress0 - Byte aligned start address of the layer source buffer. For a pixel width of 32
73291 * bits or DECODE operations BaseAddress[1:0] has to be 0 and for a pixel width of 16 bit
73292 * BaseAddress[0] has to be 0.
73293 */
73294#define IRIS_MVPL_FETCHWARP9_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHWARP9_BASEADDRESS0_BaseAddress0_MASK)
73295/*! @} */
73296
73297/*! @name FETCHWARP9_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */
73298/*! @{ */
73299#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU)
73300#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U)
73301/*! Stride0 - Source buffer stride of the layer in bytes minus one, used for address generation. For
73302 * a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel
73303 * width of 16 bit Stride has to be dividable by two and given minus one.
73304 */
73305#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_Stride0_MASK)
73306#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U)
73307#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U)
73308/*! BitsPerPixel0 - Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or
73309 * 32. Exception: FetchEco does not support 18 and 24.
73310 */
73311#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK)
73312/*! @} */
73313
73314/*! @name FETCHWARP9_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */
73315/*! @{ */
73316#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU)
73317#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U)
73318/*! LineWidth0 - Width of the source buffer of the layer in pixels minus one.
73319 */
73320#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION0_LineWidth0_MASK)
73321#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U)
73322#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U)
73323/*! LineCount0 - Number of lines of the source buffer of the layer minus one.
73324 */
73325#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION0_LineCount0_MASK)
73326/*! @} */
73327
73328/*! @name FETCHWARP9_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */
73329/*! @{ */
73330#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU)
73331#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U)
73332/*! ComponentBitsAlpha0 - Alpha.
73333 */
73334#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK)
73335#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U)
73336#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U)
73337/*! ComponentBitsBlue0 - Blue and V (chroma).
73338 */
73339#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK)
73340#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U)
73341#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U)
73342/*! ComponentBitsGreen0 - Green and U (chroma).
73343 */
73344#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK)
73345#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U)
73346#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U)
73347/*! ComponentBitsRed0 - Red, Y (luma) and palette index.
73348 */
73349#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK)
73350#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U)
73351#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U)
73352/*! ITUFormat0 - When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then
73353 * input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This
73354 * is compliant to ITU 656 standard.
73355 */
73356#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS0_ITUFormat0_MASK)
73357/*! @} */
73358
73359/*! @name FETCHWARP9_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */
73360/*! @{ */
73361#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU)
73362#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U)
73363/*! ComponentShiftAlpha0 - Alpha.
73364 */
73365#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK)
73366#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U)
73367#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U)
73368/*! ComponentShiftBlue0 - Blue and V (chroma).
73369 */
73370#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK)
73371#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U)
73372#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U)
73373/*! ComponentShiftGreen0 - Green and U (chroma).
73374 */
73375#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK)
73376#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U)
73377#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U)
73378/*! ComponentShiftRed0 - Red, Y (luma) and palette index.
73379 */
73380#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK)
73381/*! @} */
73382
73383/*! @name FETCHWARP9_LAYEROFFSET0 - Position of layer 0 within the destination frame. */
73384/*! @{ */
73385#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU)
73386#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET0_LayerXOffset0_SHIFT (0U)
73387/*! LayerXOffset0 - Horizontal offset (X).
73388 */
73389#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET0_LayerXOffset0_MASK)
73390#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U)
73391#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET0_LayerYOffset0_SHIFT (16U)
73392/*! LayerYOffset0 - Vertical offset (Y).
73393 */
73394#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET0_LayerYOffset0_MASK)
73395/*! @} */
73396
73397/*! @name FETCHWARP9_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */
73398/*! @{ */
73399#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU)
73400#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U)
73401/*! ClipWindowXOffset0 - Horizontal position (X).
73402 */
73403#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK)
73404#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U)
73405#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U)
73406/*! ClipWindowYOffset0 - Vertical position (Y).
73407 */
73408#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK)
73409/*! @} */
73410
73411/*! @name FETCHWARP9_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */
73412/*! @{ */
73413#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU)
73414#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U)
73415/*! ClipWindowWidth0 - Width.
73416 */
73417#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK)
73418#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U)
73419#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U)
73420/*! ClipWindowHeight0 - Height.
73421 */
73422#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK)
73423/*! @} */
73424
73425/*! @name FETCHWARP9_CONSTANTCOLOR0 - Constant color for layer 0. */
73426/*! @{ */
73427#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU)
73428#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U)
73429/*! ConstantAlpha0 - Alpha.
73430 */
73431#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantAlpha0_MASK)
73432#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U)
73433#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U)
73434/*! ConstantBlue0 - Blue and V (chroma).
73435 */
73436#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantBlue0_MASK)
73437#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U)
73438#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U)
73439/*! ConstantGreen0 - Green and U (chroma).
73440 */
73441#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantGreen0_MASK)
73442#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U)
73443#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U)
73444/*! ConstantRed0 - Red and Y (luma).
73445 */
73446#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR0_ConstantRed0_MASK)
73447/*! @} */
73448
73449/*! @name FETCHWARP9_LAYERPROPERTY0 - Common properties of layer 0. */
73450/*! @{ */
73451#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_TileMode0_MASK (0x30U)
73452#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_TileMode0_SHIFT (4U)
73453/*! TileMode0 - Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0)
73454 * takes precedence if a pixel becomes subject to both tiling and clipping.
73455 * 0b00..Use zero value
73456 * 0b01..Use constant color register value
73457 * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0.
73458 * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422
73459 * operations or when SourceBufferEnable is 0.
73460 */
73461#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_TileMode0_MASK)
73462#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaSrcEnable0_MASK (0x100U)
73463#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT (8U)
73464/*! AlphaSrcEnable0 - Value 1 enables source alpha for computing the output alpha. When disabled source alpha is set to 1.
73465 */
73466#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaSrcEnable0_MASK)
73467#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaConstEnable0_MASK (0x200U)
73468#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaConstEnable0_SHIFT (9U)
73469/*! AlphaConstEnable0 - Value 1 enables constant alpha for computing the output alpha. When disabled constant alpha is set to 1.
73470 */
73471#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaConstEnable0_MASK)
73472#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaMaskEnable0_MASK (0x400U)
73473#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaMaskEnable0_SHIFT (10U)
73474/*! AlphaMaskEnable0 - Value 1 enables mask alpha for computing the output alpha. When disabled mask alpha is set to 1.
73475 */
73476#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaMaskEnable0_MASK)
73477#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaTransEnable0_MASK (0x800U)
73478#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaTransEnable0_SHIFT (11U)
73479/*! AlphaTransEnable0 - Value 1 enables transparent alpha for computing the output alpha. When disabled transparent alpha is set to 1.
73480 */
73481#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_AlphaTransEnable0_MASK)
73482#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK (0x1000U)
73483#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT (12U)
73484/*! RGBAlphaSrcEnable0 - Value 1 enables source alpha (stored together with color component in the
73485 * source buffer) for RGB pre-multiply. When disabled source alpha is set to 1.
73486 */
73487#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaSrcEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaSrcEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaSrcEnable0_MASK)
73488#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK (0x2000U)
73489#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT (13U)
73490/*! RGBAlphaConstEnable0 - Value 1 enables constant alpha (ConstAlpha fields) for RGB pre-multiply. When disabled constant alpha is set to 1.
73491 */
73492#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaConstEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaConstEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaConstEnable0_MASK)
73493#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaMaskEnable0_MASK (0x4000U)
73494#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaMaskEnable0_SHIFT (14U)
73495/*! RGBAlphaMaskEnable0 - Value 1 enables mask alpha (read by another Fetch unit from a separate
73496 * alpha layer) for RGB pre-multiply. When disabled mask alpha is set to 1. Alpha mask input must be
73497 * enabled for this field to have effect.
73498 */
73499#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaMaskEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaMaskEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaMaskEnable0_MASK)
73500#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK (0x8000U)
73501#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT (15U)
73502/*! RGBAlphaTransEnable0 - Value 1 enables transparent alpha (0 or 1 depending on RGB matching
73503 * ConstantColor setting) for RGB pre-multiply. When disabled transparent alpha is set to 1.
73504 */
73505#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaTransEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaTransEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_RGBAlphaTransEnable0_MASK)
73506#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_PremulConstRGB0_MASK (0x10000U)
73507#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_PremulConstRGB0_SHIFT (16U)
73508/*! PremulConstRGB0 - When enabled (value 1) the values given by ConstantRed/Green/Blue are used
73509 * instead of alpha for source RGB pre-multiply. Settings RGBAlphaSrc/Const/Mask/TransEnable have no
73510 * effect then.
73511 */
73512#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_PremulConstRGB0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_PremulConstRGB0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_PremulConstRGB0_MASK)
73513#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_YUVConversionMode0_MASK (0x60000U)
73514#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_YUVConversionMode0_SHIFT (17U)
73515/*! YUVConversionMode0 - Enables different kind of YUV to RGB conversions.
73516 * 0b00..No conversion.
73517 * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV).
73518 * Input range is 16..235 for Y and 16..240 for U/V.
73519 * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV
73520 * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding).
73521 * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV).
73522 * Input range is 16..235 for Y and 16..240 for U/V.
73523 */
73524#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_YUVConversionMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_YUVConversionMode0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_YUVConversionMode0_MASK)
73525#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_GammaRemoveEnable0_MASK (0x100000U)
73526#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT (20U)
73527/*! GammaRemoveEnable0 - Value 1 enables the stage to remove a gamma from RGB components.
73528 */
73529#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_GammaRemoveEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_GammaRemoveEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_GammaRemoveEnable0_MASK)
73530#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U)
73531#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U)
73532/*! ClipWindowEnable0 - Value 1 enables the clip window for this layer. Pixels outside the clip
73533 * window get the clip color, pixels inside the source or tiling color.
73534 */
73535#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_ClipWindowEnable0_MASK)
73536#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U)
73537#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U)
73538/*! SourceBufferEnable0 - Value 1 enables the source buffer for this layer. When disabled the tiling
73539 * color is used only (TileMode TILE_PAD not allowed).
73540 */
73541#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY0_SourceBufferEnable0_MASK)
73542/*! @} */
73543
73544/*! @name FETCHWARP9_BASEADDRESS1 - Source buffer base address of layer 1. */
73545/*! @{ */
73546#define IRIS_MVPL_FETCHWARP9_BASEADDRESS1_BaseAddress1_MASK (0xFFFFFFFFU)
73547#define IRIS_MVPL_FETCHWARP9_BASEADDRESS1_BaseAddress1_SHIFT (0U)
73548/*! BaseAddress1 - See BaseAddress0.
73549 */
73550#define IRIS_MVPL_FETCHWARP9_BASEADDRESS1_BaseAddress1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BASEADDRESS1_BaseAddress1_SHIFT)) & IRIS_MVPL_FETCHWARP9_BASEADDRESS1_BaseAddress1_MASK)
73551/*! @} */
73552
73553/*! @name FETCHWARP9_SOURCEBUFFERATTRIBUTES1 - Source buffer attributes for layer 1. */
73554/*! @{ */
73555#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_Stride1_MASK (0xFFFFU)
73556#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_Stride1_SHIFT (0U)
73557/*! Stride1 - See Stride0.
73558 */
73559#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_Stride1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_Stride1_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_Stride1_MASK)
73560#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_MASK (0x3F0000U)
73561#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_SHIFT (16U)
73562/*! BitsPerPixel1 - See BitsPerPixel0.
73563 */
73564#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES1_BitsPerPixel1_MASK)
73565/*! @} */
73566
73567/*! @name FETCHWARP9_SOURCEBUFFERDIMENSION1 - Source buffer dimensions of layer 1, */
73568/*! @{ */
73569#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION1_LineWidth1_MASK (0x3FFFU)
73570#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION1_LineWidth1_SHIFT (0U)
73571/*! LineWidth1 - See LineWidth0.
73572 */
73573#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION1_LineWidth1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION1_LineWidth1_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION1_LineWidth1_MASK)
73574#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION1_LineCount1_MASK (0x3FFF0000U)
73575#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION1_LineCount1_SHIFT (16U)
73576/*! LineCount1 - See LineCount0.
73577 */
73578#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION1_LineCount1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION1_LineCount1_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION1_LineCount1_MASK)
73579/*! @} */
73580
73581/*! @name FETCHWARP9_COLORCOMPONENTBITS1 - Size of color components for RGB, YUV and index formats (layer 1). */
73582/*! @{ */
73583#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsAlpha1_MASK (0xFU)
73584#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsAlpha1_SHIFT (0U)
73585/*! ComponentBitsAlpha1 - Alpha.
73586 */
73587#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsAlpha1_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsAlpha1_MASK)
73588#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsBlue1_MASK (0xF00U)
73589#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsBlue1_SHIFT (8U)
73590/*! ComponentBitsBlue1 - Blue and V (chroma).
73591 */
73592#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsBlue1_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsBlue1_MASK)
73593#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsGreen1_MASK (0xF0000U)
73594#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsGreen1_SHIFT (16U)
73595/*! ComponentBitsGreen1 - Green and U (chroma).
73596 */
73597#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsGreen1_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsGreen1_MASK)
73598#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsRed1_MASK (0xF000000U)
73599#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsRed1_SHIFT (24U)
73600/*! ComponentBitsRed1 - Red, Y (luma) and palette index.
73601 */
73602#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsRed1_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ComponentBitsRed1_MASK)
73603#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ITUFormat1_MASK (0x80000000U)
73604#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ITUFormat1_SHIFT (31U)
73605/*! ITUFormat1 - See ITUFormat0.
73606 */
73607#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ITUFormat1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ITUFormat1_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS1_ITUFormat1_MASK)
73608/*! @} */
73609
73610/*! @name FETCHWARP9_COLORCOMPONENTSHIFT1 - Bit position of color components for RGB, YUV and index formats (layer 1). */
73611/*! @{ */
73612#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_MASK (0x1FU)
73613#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_SHIFT (0U)
73614/*! ComponentShiftAlpha1 - Alpha.
73615 */
73616#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftAlpha1_MASK)
73617#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_MASK (0x1F00U)
73618#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_SHIFT (8U)
73619/*! ComponentShiftBlue1 - Blue and V (chroma).
73620 */
73621#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftBlue1_MASK)
73622#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_MASK (0x1F0000U)
73623#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_SHIFT (16U)
73624/*! ComponentShiftGreen1 - Green and U (chroma).
73625 */
73626#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftGreen1_MASK)
73627#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftRed1_MASK (0x1F000000U)
73628#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftRed1_SHIFT (24U)
73629/*! ComponentShiftRed1 - Red, Y (luma) and palette index.
73630 */
73631#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftRed1_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT1_ComponentShiftRed1_MASK)
73632/*! @} */
73633
73634/*! @name FETCHWARP9_LAYEROFFSET1 - Position of layer 1 within the destination frame. */
73635/*! @{ */
73636#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET1_LayerXOffset1_MASK (0x7FFFU)
73637#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET1_LayerXOffset1_SHIFT (0U)
73638/*! LayerXOffset1 - Horizontal offset (X).
73639 */
73640#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET1_LayerXOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET1_LayerXOffset1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET1_LayerXOffset1_MASK)
73641#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET1_LayerYOffset1_MASK (0x7FFF0000U)
73642#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET1_LayerYOffset1_SHIFT (16U)
73643/*! LayerYOffset1 - Vertical offset (Y).
73644 */
73645#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET1_LayerYOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET1_LayerYOffset1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET1_LayerYOffset1_MASK)
73646/*! @} */
73647
73648/*! @name FETCHWARP9_CLIPWINDOWOFFSET1 - Clip window position for layer 1. */
73649/*! @{ */
73650#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET1_ClipWindowXOffset1_MASK (0x7FFFU)
73651#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET1_ClipWindowXOffset1_SHIFT (0U)
73652/*! ClipWindowXOffset1 - Horizontal position (X).
73653 */
73654#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET1_ClipWindowXOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET1_ClipWindowXOffset1_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET1_ClipWindowXOffset1_MASK)
73655#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET1_ClipWindowYOffset1_MASK (0x7FFF0000U)
73656#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET1_ClipWindowYOffset1_SHIFT (16U)
73657/*! ClipWindowYOffset1 - Vertical position (Y).
73658 */
73659#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET1_ClipWindowYOffset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET1_ClipWindowYOffset1_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET1_ClipWindowYOffset1_MASK)
73660/*! @} */
73661
73662/*! @name FETCHWARP9_CLIPWINDOWDIMENSIONS1 - Clip window size for layer 1. */
73663/*! @{ */
73664#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_MASK (0x3FFFU)
73665#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_SHIFT (0U)
73666/*! ClipWindowWidth1 - Width.
73667 */
73668#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS1_ClipWindowWidth1_MASK)
73669#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_MASK (0x3FFF0000U)
73670#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_SHIFT (16U)
73671/*! ClipWindowHeight1 - Height.
73672 */
73673#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS1_ClipWindowHeight1_MASK)
73674/*! @} */
73675
73676/*! @name FETCHWARP9_CONSTANTCOLOR1 - Constant color for layer 1. */
73677/*! @{ */
73678#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantAlpha1_MASK (0xFFU)
73679#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantAlpha1_SHIFT (0U)
73680/*! ConstantAlpha1 - Alpha.
73681 */
73682#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantAlpha1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantAlpha1_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantAlpha1_MASK)
73683#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantBlue1_MASK (0xFF00U)
73684#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantBlue1_SHIFT (8U)
73685/*! ConstantBlue1 - Blue and V (chroma).
73686 */
73687#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantBlue1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantBlue1_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantBlue1_MASK)
73688#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantGreen1_MASK (0xFF0000U)
73689#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantGreen1_SHIFT (16U)
73690/*! ConstantGreen1 - Green and U (chroma).
73691 */
73692#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantGreen1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantGreen1_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantGreen1_MASK)
73693#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantRed1_MASK (0xFF000000U)
73694#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantRed1_SHIFT (24U)
73695/*! ConstantRed1 - Red and Y (luma).
73696 */
73697#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantRed1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantRed1_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR1_ConstantRed1_MASK)
73698/*! @} */
73699
73700/*! @name FETCHWARP9_LAYERPROPERTY1 - Common properties of layer 1. */
73701/*! @{ */
73702#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_TileMode1_MASK (0x30U)
73703#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_TileMode1_SHIFT (4U)
73704/*! TileMode1 - See TileMode0.
73705 * 0b00..Use zero value
73706 * 0b01..Use constant color register value
73707 * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0.
73708 * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422
73709 * operations or when SourceBufferEnable is 0.
73710 */
73711#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_TileMode1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_TileMode1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_TileMode1_MASK)
73712#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaSrcEnable1_MASK (0x100U)
73713#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaSrcEnable1_SHIFT (8U)
73714/*! AlphaSrcEnable1 - See AlphaSrcSelect0.
73715 */
73716#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaSrcEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaSrcEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaSrcEnable1_MASK)
73717#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaConstEnable1_MASK (0x200U)
73718#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaConstEnable1_SHIFT (9U)
73719/*! AlphaConstEnable1 - See AlphaConstSelect0.
73720 */
73721#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaConstEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaConstEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaConstEnable1_MASK)
73722#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaMaskEnable1_MASK (0x400U)
73723#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaMaskEnable1_SHIFT (10U)
73724/*! AlphaMaskEnable1 - See AlphaMaskSelect0.
73725 */
73726#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaMaskEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaMaskEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaMaskEnable1_MASK)
73727#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaTransEnable1_MASK (0x800U)
73728#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaTransEnable1_SHIFT (11U)
73729/*! AlphaTransEnable1 - See AlphaTransSelect0.
73730 */
73731#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaTransEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaTransEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_AlphaTransEnable1_MASK)
73732#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaSrcEnable1_MASK (0x1000U)
73733#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaSrcEnable1_SHIFT (12U)
73734/*! RGBAlphaSrcEnable1 - See RGBAlphaSrcSelect0.
73735 */
73736#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaSrcEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaSrcEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaSrcEnable1_MASK)
73737#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaConstEnable1_MASK (0x2000U)
73738#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaConstEnable1_SHIFT (13U)
73739/*! RGBAlphaConstEnable1 - See RGBAlphaConstSelect0.
73740 */
73741#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaConstEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaConstEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaConstEnable1_MASK)
73742#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaMaskEnable1_MASK (0x4000U)
73743#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaMaskEnable1_SHIFT (14U)
73744/*! RGBAlphaMaskEnable1 - See RGBAlphaMaskSelect0.
73745 */
73746#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaMaskEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaMaskEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaMaskEnable1_MASK)
73747#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaTransEnable1_MASK (0x8000U)
73748#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaTransEnable1_SHIFT (15U)
73749/*! RGBAlphaTransEnable1 - See RGBAlphaTransSelect0.
73750 */
73751#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaTransEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaTransEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_RGBAlphaTransEnable1_MASK)
73752#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_PremulConstRGB1_MASK (0x10000U)
73753#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_PremulConstRGB1_SHIFT (16U)
73754/*! PremulConstRGB1 - See PremulConstRGB0.
73755 */
73756#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_PremulConstRGB1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_PremulConstRGB1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_PremulConstRGB1_MASK)
73757#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_YUVConversionMode1_MASK (0x60000U)
73758#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_YUVConversionMode1_SHIFT (17U)
73759/*! YUVConversionMode1 - See YUVConversionMode0.
73760 * 0b00..No conversion.
73761 * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV).
73762 * Input range is 16..235 for Y and 16..240 for U/V.
73763 * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV
73764 * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding).
73765 * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV).
73766 * Input range is 16..235 for Y and 16..240 for U/V.
73767 */
73768#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_YUVConversionMode1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_YUVConversionMode1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_YUVConversionMode1_MASK)
73769#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_GammaRemoveEnable1_MASK (0x100000U)
73770#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_GammaRemoveEnable1_SHIFT (20U)
73771/*! GammaRemoveEnable1 - See GammaRemoveEnable0.
73772 */
73773#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_GammaRemoveEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_GammaRemoveEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_GammaRemoveEnable1_MASK)
73774#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_ClipWindowEnable1_MASK (0x40000000U)
73775#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_ClipWindowEnable1_SHIFT (30U)
73776/*! ClipWindowEnable1 - See ClipWindowEnable0.
73777 */
73778#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_ClipWindowEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_ClipWindowEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_ClipWindowEnable1_MASK)
73779#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_SourceBufferEnable1_MASK (0x80000000U)
73780#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_SourceBufferEnable1_SHIFT (31U)
73781/*! SourceBufferEnable1 - See SourceBufferEnable0.
73782 */
73783#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_SourceBufferEnable1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_SourceBufferEnable1_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY1_SourceBufferEnable1_MASK)
73784/*! @} */
73785
73786/*! @name FETCHWARP9_BASEADDRESS2 - Source buffer base address of layer 2. */
73787/*! @{ */
73788#define IRIS_MVPL_FETCHWARP9_BASEADDRESS2_BaseAddress2_MASK (0xFFFFFFFFU)
73789#define IRIS_MVPL_FETCHWARP9_BASEADDRESS2_BaseAddress2_SHIFT (0U)
73790/*! BaseAddress2 - See BaseAddress0.
73791 */
73792#define IRIS_MVPL_FETCHWARP9_BASEADDRESS2_BaseAddress2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BASEADDRESS2_BaseAddress2_SHIFT)) & IRIS_MVPL_FETCHWARP9_BASEADDRESS2_BaseAddress2_MASK)
73793/*! @} */
73794
73795/*! @name FETCHWARP9_SOURCEBUFFERATTRIBUTES2 - Source buffer attributes for layer 2. */
73796/*! @{ */
73797#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_Stride2_MASK (0xFFFFU)
73798#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_Stride2_SHIFT (0U)
73799/*! Stride2 - See Stride0.
73800 */
73801#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_Stride2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_Stride2_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_Stride2_MASK)
73802#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_MASK (0x3F0000U)
73803#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_SHIFT (16U)
73804/*! BitsPerPixel2 - See BitsPerPixel0.
73805 */
73806#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES2_BitsPerPixel2_MASK)
73807/*! @} */
73808
73809/*! @name FETCHWARP9_SOURCEBUFFERDIMENSION2 - Source buffer dimension of layer 2. */
73810/*! @{ */
73811#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION2_LineWidth2_MASK (0x3FFFU)
73812#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION2_LineWidth2_SHIFT (0U)
73813/*! LineWidth2 - See LineWidth0.
73814 */
73815#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION2_LineWidth2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION2_LineWidth2_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION2_LineWidth2_MASK)
73816#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION2_LineCount2_MASK (0x3FFF0000U)
73817#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION2_LineCount2_SHIFT (16U)
73818/*! LineCount2 - See LineCount0.
73819 */
73820#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION2_LineCount2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION2_LineCount2_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION2_LineCount2_MASK)
73821/*! @} */
73822
73823/*! @name FETCHWARP9_COLORCOMPONENTBITS2 - Size of color components for RGB, YUV and index formats (layer 2). */
73824/*! @{ */
73825#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsAlpha2_MASK (0xFU)
73826#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsAlpha2_SHIFT (0U)
73827/*! ComponentBitsAlpha2 - Alpha.
73828 */
73829#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsAlpha2_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsAlpha2_MASK)
73830#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsBlue2_MASK (0xF00U)
73831#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsBlue2_SHIFT (8U)
73832/*! ComponentBitsBlue2 - Blue and V (chroma).
73833 */
73834#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsBlue2_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsBlue2_MASK)
73835#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsGreen2_MASK (0xF0000U)
73836#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsGreen2_SHIFT (16U)
73837/*! ComponentBitsGreen2 - Green and U (chroma).
73838 */
73839#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsGreen2_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsGreen2_MASK)
73840#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsRed2_MASK (0xF000000U)
73841#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsRed2_SHIFT (24U)
73842/*! ComponentBitsRed2 - Red, Y (luma) and palette index.
73843 */
73844#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsRed2_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ComponentBitsRed2_MASK)
73845#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ITUFormat2_MASK (0x80000000U)
73846#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ITUFormat2_SHIFT (31U)
73847/*! ITUFormat2 - See ITUFormat0.
73848 */
73849#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ITUFormat2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ITUFormat2_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS2_ITUFormat2_MASK)
73850/*! @} */
73851
73852/*! @name FETCHWARP9_COLORCOMPONENTSHIFT2 - Bit position of color components for RGB, YUV and index formats (layer 2). */
73853/*! @{ */
73854#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_MASK (0x1FU)
73855#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_SHIFT (0U)
73856/*! ComponentShiftAlpha2 - Alpha.
73857 */
73858#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftAlpha2_MASK)
73859#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_MASK (0x1F00U)
73860#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_SHIFT (8U)
73861/*! ComponentShiftBlue2 - Blue and V (chroma).
73862 */
73863#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftBlue2_MASK)
73864#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_MASK (0x1F0000U)
73865#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_SHIFT (16U)
73866/*! ComponentShiftGreen2 - Green and U (chroma).
73867 */
73868#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftGreen2_MASK)
73869#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftRed2_MASK (0x1F000000U)
73870#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftRed2_SHIFT (24U)
73871/*! ComponentShiftRed2 - Red, Y (luma) and palette index.
73872 */
73873#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftRed2_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT2_ComponentShiftRed2_MASK)
73874/*! @} */
73875
73876/*! @name FETCHWARP9_LAYEROFFSET2 - Position of layer 2 within the destination frame. */
73877/*! @{ */
73878#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET2_LayerXOffset2_MASK (0x7FFFU)
73879#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET2_LayerXOffset2_SHIFT (0U)
73880/*! LayerXOffset2 - Horizontal offset (X).
73881 */
73882#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET2_LayerXOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET2_LayerXOffset2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET2_LayerXOffset2_MASK)
73883#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET2_LayerYOffset2_MASK (0x7FFF0000U)
73884#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET2_LayerYOffset2_SHIFT (16U)
73885/*! LayerYOffset2 - Vertical offset (Y).
73886 */
73887#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET2_LayerYOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET2_LayerYOffset2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET2_LayerYOffset2_MASK)
73888/*! @} */
73889
73890/*! @name FETCHWARP9_CLIPWINDOWOFFSET2 - Clip window position for layer 2. */
73891/*! @{ */
73892#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET2_ClipWindowXOffset2_MASK (0x7FFFU)
73893#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET2_ClipWindowXOffset2_SHIFT (0U)
73894/*! ClipWindowXOffset2 - Horizontal position (X).
73895 */
73896#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET2_ClipWindowXOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET2_ClipWindowXOffset2_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET2_ClipWindowXOffset2_MASK)
73897#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET2_ClipWindowYOffset2_MASK (0x7FFF0000U)
73898#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET2_ClipWindowYOffset2_SHIFT (16U)
73899/*! ClipWindowYOffset2 - Vertical position (Y).
73900 */
73901#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET2_ClipWindowYOffset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET2_ClipWindowYOffset2_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET2_ClipWindowYOffset2_MASK)
73902/*! @} */
73903
73904/*! @name FETCHWARP9_CLIPWINDOWDIMENSIONS2 - Clip window size for layer 2. */
73905/*! @{ */
73906#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_MASK (0x3FFFU)
73907#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_SHIFT (0U)
73908/*! ClipWindowWidth2 - Width.
73909 */
73910#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS2_ClipWindowWidth2_MASK)
73911#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_MASK (0x3FFF0000U)
73912#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_SHIFT (16U)
73913/*! ClipWindowHeight2 - Height.
73914 */
73915#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS2_ClipWindowHeight2_MASK)
73916/*! @} */
73917
73918/*! @name FETCHWARP9_CONSTANTCOLOR2 - Constant color for layer 2. */
73919/*! @{ */
73920#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantAlpha2_MASK (0xFFU)
73921#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantAlpha2_SHIFT (0U)
73922/*! ConstantAlpha2 - Alpha.
73923 */
73924#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantAlpha2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantAlpha2_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantAlpha2_MASK)
73925#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantBlue2_MASK (0xFF00U)
73926#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantBlue2_SHIFT (8U)
73927/*! ConstantBlue2 - Blue and V (chroma).
73928 */
73929#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantBlue2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantBlue2_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantBlue2_MASK)
73930#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantGreen2_MASK (0xFF0000U)
73931#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantGreen2_SHIFT (16U)
73932/*! ConstantGreen2 - Green and U (chroma).
73933 */
73934#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantGreen2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantGreen2_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantGreen2_MASK)
73935#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantRed2_MASK (0xFF000000U)
73936#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantRed2_SHIFT (24U)
73937/*! ConstantRed2 - Red and Y (luma).
73938 */
73939#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantRed2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantRed2_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR2_ConstantRed2_MASK)
73940/*! @} */
73941
73942/*! @name FETCHWARP9_LAYERPROPERTY2 - Common properties of layer 2. */
73943/*! @{ */
73944#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_TileMode2_MASK (0x30U)
73945#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_TileMode2_SHIFT (4U)
73946/*! TileMode2 - See TileMode0.
73947 * 0b00..Use zero value
73948 * 0b01..Use constant color register value
73949 * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0.
73950 * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422
73951 * operations or when SourceBufferEnable is 0.
73952 */
73953#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_TileMode2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_TileMode2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_TileMode2_MASK)
73954#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaSrcEnable2_MASK (0x100U)
73955#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaSrcEnable2_SHIFT (8U)
73956/*! AlphaSrcEnable2 - See AlphaSrcSelect0.
73957 */
73958#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaSrcEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaSrcEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaSrcEnable2_MASK)
73959#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaConstEnable2_MASK (0x200U)
73960#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaConstEnable2_SHIFT (9U)
73961/*! AlphaConstEnable2 - See AlphaConstSelect0.
73962 */
73963#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaConstEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaConstEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaConstEnable2_MASK)
73964#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaMaskEnable2_MASK (0x400U)
73965#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaMaskEnable2_SHIFT (10U)
73966/*! AlphaMaskEnable2 - See AlphaMaskSelect0.
73967 */
73968#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaMaskEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaMaskEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaMaskEnable2_MASK)
73969#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaTransEnable2_MASK (0x800U)
73970#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaTransEnable2_SHIFT (11U)
73971/*! AlphaTransEnable2 - See AlphaTransSelect0.
73972 */
73973#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaTransEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaTransEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_AlphaTransEnable2_MASK)
73974#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaSrcEnable2_MASK (0x1000U)
73975#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaSrcEnable2_SHIFT (12U)
73976/*! RGBAlphaSrcEnable2 - See RGBAlphaSrcSelect0.
73977 */
73978#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaSrcEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaSrcEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaSrcEnable2_MASK)
73979#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaConstEnable2_MASK (0x2000U)
73980#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaConstEnable2_SHIFT (13U)
73981/*! RGBAlphaConstEnable2 - See RGBAlphaConstSelect0.
73982 */
73983#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaConstEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaConstEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaConstEnable2_MASK)
73984#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaMaskEnable2_MASK (0x4000U)
73985#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaMaskEnable2_SHIFT (14U)
73986/*! RGBAlphaMaskEnable2 - See RGBAlphaMaskSelect0.
73987 */
73988#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaMaskEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaMaskEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaMaskEnable2_MASK)
73989#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaTransEnable2_MASK (0x8000U)
73990#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaTransEnable2_SHIFT (15U)
73991/*! RGBAlphaTransEnable2 - See RGBAlphaTransSelect0.
73992 */
73993#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaTransEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaTransEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_RGBAlphaTransEnable2_MASK)
73994#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_PremulConstRGB2_MASK (0x10000U)
73995#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_PremulConstRGB2_SHIFT (16U)
73996/*! PremulConstRGB2 - See PremulConstRGB0.
73997 */
73998#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_PremulConstRGB2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_PremulConstRGB2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_PremulConstRGB2_MASK)
73999#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_YUVConversionMode2_MASK (0x60000U)
74000#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_YUVConversionMode2_SHIFT (17U)
74001/*! YUVConversionMode2 - See YUVConversionMode0.
74002 * 0b00..No conversion.
74003 * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV).
74004 * Input range is 16..235 for Y and 16..240 for U/V.
74005 * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV
74006 * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding).
74007 * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV).
74008 * Input range is 16..235 for Y and 16..240 for U/V.
74009 */
74010#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_YUVConversionMode2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_YUVConversionMode2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_YUVConversionMode2_MASK)
74011#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_GammaRemoveEnable2_MASK (0x100000U)
74012#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_GammaRemoveEnable2_SHIFT (20U)
74013/*! GammaRemoveEnable2 - See GammaRemoveEnable0.
74014 */
74015#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_GammaRemoveEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_GammaRemoveEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_GammaRemoveEnable2_MASK)
74016#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_ClipWindowEnable2_MASK (0x40000000U)
74017#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_ClipWindowEnable2_SHIFT (30U)
74018/*! ClipWindowEnable2 - See ClipWindowEnable0.
74019 */
74020#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_ClipWindowEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_ClipWindowEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_ClipWindowEnable2_MASK)
74021#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_SourceBufferEnable2_MASK (0x80000000U)
74022#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_SourceBufferEnable2_SHIFT (31U)
74023/*! SourceBufferEnable2 - See SourceBufferEnable0.
74024 */
74025#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_SourceBufferEnable2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_SourceBufferEnable2_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY2_SourceBufferEnable2_MASK)
74026/*! @} */
74027
74028/*! @name FETCHWARP9_BASEADDRESS3 - Source buffer base address of layer 3. */
74029/*! @{ */
74030#define IRIS_MVPL_FETCHWARP9_BASEADDRESS3_BaseAddress3_MASK (0xFFFFFFFFU)
74031#define IRIS_MVPL_FETCHWARP9_BASEADDRESS3_BaseAddress3_SHIFT (0U)
74032/*! BaseAddress3 - See BaseAddress0.
74033 */
74034#define IRIS_MVPL_FETCHWARP9_BASEADDRESS3_BaseAddress3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BASEADDRESS3_BaseAddress3_SHIFT)) & IRIS_MVPL_FETCHWARP9_BASEADDRESS3_BaseAddress3_MASK)
74035/*! @} */
74036
74037/*! @name FETCHWARP9_SOURCEBUFFERATTRIBUTES3 - Source buffer attributes for layer 3. */
74038/*! @{ */
74039#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_Stride3_MASK (0xFFFFU)
74040#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_Stride3_SHIFT (0U)
74041/*! Stride3 - See Stride0.
74042 */
74043#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_Stride3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_Stride3_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_Stride3_MASK)
74044#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_MASK (0x3F0000U)
74045#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_SHIFT (16U)
74046/*! BitsPerPixel3 - See BitsPerPixel0.
74047 */
74048#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES3_BitsPerPixel3_MASK)
74049/*! @} */
74050
74051/*! @name FETCHWARP9_SOURCEBUFFERDIMENSION3 - Source buffer dimension of layer 3. */
74052/*! @{ */
74053#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION3_LineWidth3_MASK (0x3FFFU)
74054#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION3_LineWidth3_SHIFT (0U)
74055/*! LineWidth3 - See LineWidth0.
74056 */
74057#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION3_LineWidth3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION3_LineWidth3_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION3_LineWidth3_MASK)
74058#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION3_LineCount3_MASK (0x3FFF0000U)
74059#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION3_LineCount3_SHIFT (16U)
74060/*! LineCount3 - See LineCount0.
74061 */
74062#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION3_LineCount3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION3_LineCount3_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION3_LineCount3_MASK)
74063/*! @} */
74064
74065/*! @name FETCHWARP9_COLORCOMPONENTBITS3 - Size of color components for RGB, YUV and index formats (layer 3). */
74066/*! @{ */
74067#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsAlpha3_MASK (0xFU)
74068#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsAlpha3_SHIFT (0U)
74069/*! ComponentBitsAlpha3 - Alpha.
74070 */
74071#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsAlpha3_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsAlpha3_MASK)
74072#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsBlue3_MASK (0xF00U)
74073#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsBlue3_SHIFT (8U)
74074/*! ComponentBitsBlue3 - Blue and V (chroma).
74075 */
74076#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsBlue3_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsBlue3_MASK)
74077#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsGreen3_MASK (0xF0000U)
74078#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsGreen3_SHIFT (16U)
74079/*! ComponentBitsGreen3 - Green and U (chroma).
74080 */
74081#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsGreen3_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsGreen3_MASK)
74082#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsRed3_MASK (0xF000000U)
74083#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsRed3_SHIFT (24U)
74084/*! ComponentBitsRed3 - Red, Y (luma) and palette index.
74085 */
74086#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsRed3_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ComponentBitsRed3_MASK)
74087#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ITUFormat3_MASK (0x80000000U)
74088#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ITUFormat3_SHIFT (31U)
74089/*! ITUFormat3 - See ITUFormat0.
74090 */
74091#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ITUFormat3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ITUFormat3_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS3_ITUFormat3_MASK)
74092/*! @} */
74093
74094/*! @name FETCHWARP9_COLORCOMPONENTSHIFT3 - Bit position of color components for RGB, YUV and index formats (layer 3). */
74095/*! @{ */
74096#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_MASK (0x1FU)
74097#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_SHIFT (0U)
74098/*! ComponentShiftAlpha3 - Alpha.
74099 */
74100#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftAlpha3_MASK)
74101#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_MASK (0x1F00U)
74102#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_SHIFT (8U)
74103/*! ComponentShiftBlue3 - Blue and V (chroma).
74104 */
74105#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftBlue3_MASK)
74106#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_MASK (0x1F0000U)
74107#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_SHIFT (16U)
74108/*! ComponentShiftGreen3 - Green and U (chroma).
74109 */
74110#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftGreen3_MASK)
74111#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftRed3_MASK (0x1F000000U)
74112#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftRed3_SHIFT (24U)
74113/*! ComponentShiftRed3 - Red, Y (luma) and palette index.
74114 */
74115#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftRed3_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT3_ComponentShiftRed3_MASK)
74116/*! @} */
74117
74118/*! @name FETCHWARP9_LAYEROFFSET3 - Position of layer 3 within the destination frame. */
74119/*! @{ */
74120#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET3_LayerXOffset3_MASK (0x7FFFU)
74121#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET3_LayerXOffset3_SHIFT (0U)
74122/*! LayerXOffset3 - Horizontal offset (X).
74123 */
74124#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET3_LayerXOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET3_LayerXOffset3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET3_LayerXOffset3_MASK)
74125#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET3_LayerYOffset3_MASK (0x7FFF0000U)
74126#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET3_LayerYOffset3_SHIFT (16U)
74127/*! LayerYOffset3 - Vertical offset (Y).
74128 */
74129#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET3_LayerYOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET3_LayerYOffset3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET3_LayerYOffset3_MASK)
74130/*! @} */
74131
74132/*! @name FETCHWARP9_CLIPWINDOWOFFSET3 - Clip window position for layer 3. */
74133/*! @{ */
74134#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET3_ClipWindowXOffset3_MASK (0x7FFFU)
74135#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET3_ClipWindowXOffset3_SHIFT (0U)
74136/*! ClipWindowXOffset3 - Horizontal position (X).
74137 */
74138#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET3_ClipWindowXOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET3_ClipWindowXOffset3_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET3_ClipWindowXOffset3_MASK)
74139#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET3_ClipWindowYOffset3_MASK (0x7FFF0000U)
74140#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET3_ClipWindowYOffset3_SHIFT (16U)
74141/*! ClipWindowYOffset3 - Vertical position (Y).
74142 */
74143#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET3_ClipWindowYOffset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET3_ClipWindowYOffset3_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET3_ClipWindowYOffset3_MASK)
74144/*! @} */
74145
74146/*! @name FETCHWARP9_CLIPWINDOWDIMENSIONS3 - Clip window size for layer 3. */
74147/*! @{ */
74148#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_MASK (0x3FFFU)
74149#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_SHIFT (0U)
74150/*! ClipWindowWidth3 - Width.
74151 */
74152#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS3_ClipWindowWidth3_MASK)
74153#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_MASK (0x3FFF0000U)
74154#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_SHIFT (16U)
74155/*! ClipWindowHeight3 - Height.
74156 */
74157#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS3_ClipWindowHeight3_MASK)
74158/*! @} */
74159
74160/*! @name FETCHWARP9_CONSTANTCOLOR3 - Constant color for layer 3. */
74161/*! @{ */
74162#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantAlpha3_MASK (0xFFU)
74163#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantAlpha3_SHIFT (0U)
74164/*! ConstantAlpha3 - Alpha.
74165 */
74166#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantAlpha3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantAlpha3_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantAlpha3_MASK)
74167#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantBlue3_MASK (0xFF00U)
74168#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantBlue3_SHIFT (8U)
74169/*! ConstantBlue3 - Blue and V (chroma).
74170 */
74171#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantBlue3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantBlue3_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantBlue3_MASK)
74172#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantGreen3_MASK (0xFF0000U)
74173#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantGreen3_SHIFT (16U)
74174/*! ConstantGreen3 - Green and U (chroma).
74175 */
74176#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantGreen3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantGreen3_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantGreen3_MASK)
74177#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantRed3_MASK (0xFF000000U)
74178#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantRed3_SHIFT (24U)
74179/*! ConstantRed3 - Red and Y (luma).
74180 */
74181#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantRed3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantRed3_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR3_ConstantRed3_MASK)
74182/*! @} */
74183
74184/*! @name FETCHWARP9_LAYERPROPERTY3 - Common properties of layer 3. */
74185/*! @{ */
74186#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_TileMode3_MASK (0x30U)
74187#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_TileMode3_SHIFT (4U)
74188/*! TileMode3 - See TileMode0.
74189 * 0b00..Use zero value
74190 * 0b01..Use constant color register value
74191 * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0.
74192 * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422
74193 * operations or when SourceBufferEnable is 0.
74194 */
74195#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_TileMode3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_TileMode3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_TileMode3_MASK)
74196#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaSrcEnable3_MASK (0x100U)
74197#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaSrcEnable3_SHIFT (8U)
74198/*! AlphaSrcEnable3 - See AlphaSrcSelect0.
74199 */
74200#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaSrcEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaSrcEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaSrcEnable3_MASK)
74201#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaConstEnable3_MASK (0x200U)
74202#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaConstEnable3_SHIFT (9U)
74203/*! AlphaConstEnable3 - See AlphaConstSelect0.
74204 */
74205#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaConstEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaConstEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaConstEnable3_MASK)
74206#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaMaskEnable3_MASK (0x400U)
74207#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaMaskEnable3_SHIFT (10U)
74208/*! AlphaMaskEnable3 - See AlphaMaskSelect0.
74209 */
74210#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaMaskEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaMaskEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaMaskEnable3_MASK)
74211#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaTransEnable3_MASK (0x800U)
74212#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaTransEnable3_SHIFT (11U)
74213/*! AlphaTransEnable3 - See AlphaTransSelect0.
74214 */
74215#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaTransEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaTransEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_AlphaTransEnable3_MASK)
74216#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaSrcEnable3_MASK (0x1000U)
74217#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaSrcEnable3_SHIFT (12U)
74218/*! RGBAlphaSrcEnable3 - See RGBAlphaSrcSelect0.
74219 */
74220#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaSrcEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaSrcEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaSrcEnable3_MASK)
74221#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaConstEnable3_MASK (0x2000U)
74222#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaConstEnable3_SHIFT (13U)
74223/*! RGBAlphaConstEnable3 - See RGBAlphaConstSelect0.
74224 */
74225#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaConstEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaConstEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaConstEnable3_MASK)
74226#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaMaskEnable3_MASK (0x4000U)
74227#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaMaskEnable3_SHIFT (14U)
74228/*! RGBAlphaMaskEnable3 - See RGBAlphaMaskSelect0.
74229 */
74230#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaMaskEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaMaskEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaMaskEnable3_MASK)
74231#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaTransEnable3_MASK (0x8000U)
74232#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaTransEnable3_SHIFT (15U)
74233/*! RGBAlphaTransEnable3 - See RGBAlphaTransSelect0.
74234 */
74235#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaTransEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaTransEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_RGBAlphaTransEnable3_MASK)
74236#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_PremulConstRGB3_MASK (0x10000U)
74237#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_PremulConstRGB3_SHIFT (16U)
74238/*! PremulConstRGB3 - See PremulConstRGB0.
74239 */
74240#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_PremulConstRGB3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_PremulConstRGB3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_PremulConstRGB3_MASK)
74241#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_YUVConversionMode3_MASK (0x60000U)
74242#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_YUVConversionMode3_SHIFT (17U)
74243/*! YUVConversionMode3 - See YUVConversionMode0.
74244 * 0b00..No conversion.
74245 * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV).
74246 * Input range is 16..235 for Y and 16..240 for U/V.
74247 * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV
74248 * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding).
74249 * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV).
74250 * Input range is 16..235 for Y and 16..240 for U/V.
74251 */
74252#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_YUVConversionMode3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_YUVConversionMode3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_YUVConversionMode3_MASK)
74253#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_GammaRemoveEnable3_MASK (0x100000U)
74254#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_GammaRemoveEnable3_SHIFT (20U)
74255/*! GammaRemoveEnable3 - See GammaRemoveEnable0.
74256 */
74257#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_GammaRemoveEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_GammaRemoveEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_GammaRemoveEnable3_MASK)
74258#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_ClipWindowEnable3_MASK (0x40000000U)
74259#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_ClipWindowEnable3_SHIFT (30U)
74260/*! ClipWindowEnable3 - See ClipWindowEnable0.
74261 */
74262#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_ClipWindowEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_ClipWindowEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_ClipWindowEnable3_MASK)
74263#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_SourceBufferEnable3_MASK (0x80000000U)
74264#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_SourceBufferEnable3_SHIFT (31U)
74265/*! SourceBufferEnable3 - See SourceBufferEnable0.
74266 */
74267#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_SourceBufferEnable3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_SourceBufferEnable3_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY3_SourceBufferEnable3_MASK)
74268/*! @} */
74269
74270/*! @name FETCHWARP9_BASEADDRESS4 - Source buffer base address of layer 4. */
74271/*! @{ */
74272#define IRIS_MVPL_FETCHWARP9_BASEADDRESS4_BaseAddress4_MASK (0xFFFFFFFFU)
74273#define IRIS_MVPL_FETCHWARP9_BASEADDRESS4_BaseAddress4_SHIFT (0U)
74274/*! BaseAddress4 - See BaseAddress0.
74275 */
74276#define IRIS_MVPL_FETCHWARP9_BASEADDRESS4_BaseAddress4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BASEADDRESS4_BaseAddress4_SHIFT)) & IRIS_MVPL_FETCHWARP9_BASEADDRESS4_BaseAddress4_MASK)
74277/*! @} */
74278
74279/*! @name FETCHWARP9_SOURCEBUFFERATTRIBUTES4 - Source buffer attributes for layer 4. */
74280/*! @{ */
74281#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_Stride4_MASK (0xFFFFU)
74282#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_Stride4_SHIFT (0U)
74283/*! Stride4 - See Stride0.
74284 */
74285#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_Stride4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_Stride4_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_Stride4_MASK)
74286#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_MASK (0x3F0000U)
74287#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_SHIFT (16U)
74288/*! BitsPerPixel4 - See BitsPerPixel0.
74289 */
74290#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES4_BitsPerPixel4_MASK)
74291/*! @} */
74292
74293/*! @name FETCHWARP9_SOURCEBUFFERDIMENSION4 - Source buffer dimension of layer 4. */
74294/*! @{ */
74295#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION4_LineWidth4_MASK (0x3FFFU)
74296#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION4_LineWidth4_SHIFT (0U)
74297/*! LineWidth4 - See LineWidth0.
74298 */
74299#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION4_LineWidth4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION4_LineWidth4_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION4_LineWidth4_MASK)
74300#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION4_LineCount4_MASK (0x3FFF0000U)
74301#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION4_LineCount4_SHIFT (16U)
74302/*! LineCount4 - See LineCount0.
74303 */
74304#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION4_LineCount4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION4_LineCount4_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION4_LineCount4_MASK)
74305/*! @} */
74306
74307/*! @name FETCHWARP9_COLORCOMPONENTBITS4 - Size of color components for RGB, YUV and index formats (layer 4). */
74308/*! @{ */
74309#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsAlpha4_MASK (0xFU)
74310#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsAlpha4_SHIFT (0U)
74311/*! ComponentBitsAlpha4 - Alpha.
74312 */
74313#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsAlpha4_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsAlpha4_MASK)
74314#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsBlue4_MASK (0xF00U)
74315#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsBlue4_SHIFT (8U)
74316/*! ComponentBitsBlue4 - Blue and V (chroma).
74317 */
74318#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsBlue4_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsBlue4_MASK)
74319#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsGreen4_MASK (0xF0000U)
74320#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsGreen4_SHIFT (16U)
74321/*! ComponentBitsGreen4 - Green and U (chroma).
74322 */
74323#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsGreen4_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsGreen4_MASK)
74324#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsRed4_MASK (0xF000000U)
74325#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsRed4_SHIFT (24U)
74326/*! ComponentBitsRed4 - Red, Y (luma) and palette index.
74327 */
74328#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsRed4_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ComponentBitsRed4_MASK)
74329#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ITUFormat4_MASK (0x80000000U)
74330#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ITUFormat4_SHIFT (31U)
74331/*! ITUFormat4 - See ITUFormat0.
74332 */
74333#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ITUFormat4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ITUFormat4_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS4_ITUFormat4_MASK)
74334/*! @} */
74335
74336/*! @name FETCHWARP9_COLORCOMPONENTSHIFT4 - Bit position of color components for RGB, YUV and index formats (layer 4). */
74337/*! @{ */
74338#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_MASK (0x1FU)
74339#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_SHIFT (0U)
74340/*! ComponentShiftAlpha4 - Alpha.
74341 */
74342#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftAlpha4_MASK)
74343#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_MASK (0x1F00U)
74344#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_SHIFT (8U)
74345/*! ComponentShiftBlue4 - Blue and V (chroma).
74346 */
74347#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftBlue4_MASK)
74348#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_MASK (0x1F0000U)
74349#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_SHIFT (16U)
74350/*! ComponentShiftGreen4 - Green and U (chroma).
74351 */
74352#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftGreen4_MASK)
74353#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftRed4_MASK (0x1F000000U)
74354#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftRed4_SHIFT (24U)
74355/*! ComponentShiftRed4 - Red, Y (luma) and palette index.
74356 */
74357#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftRed4_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT4_ComponentShiftRed4_MASK)
74358/*! @} */
74359
74360/*! @name FETCHWARP9_LAYEROFFSET4 - Position of layer 4 within the destination frame. */
74361/*! @{ */
74362#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET4_LayerXOffset4_MASK (0x7FFFU)
74363#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET4_LayerXOffset4_SHIFT (0U)
74364/*! LayerXOffset4 - Horizontal offset (X).
74365 */
74366#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET4_LayerXOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET4_LayerXOffset4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET4_LayerXOffset4_MASK)
74367#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET4_LayerYOffset4_MASK (0x7FFF0000U)
74368#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET4_LayerYOffset4_SHIFT (16U)
74369/*! LayerYOffset4 - Vertical offset (Y).
74370 */
74371#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET4_LayerYOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET4_LayerYOffset4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET4_LayerYOffset4_MASK)
74372/*! @} */
74373
74374/*! @name FETCHWARP9_CLIPWINDOWOFFSET4 - Clip window position for layer 4. */
74375/*! @{ */
74376#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET4_ClipWindowXOffset4_MASK (0x7FFFU)
74377#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET4_ClipWindowXOffset4_SHIFT (0U)
74378/*! ClipWindowXOffset4 - Horizontal position (X).
74379 */
74380#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET4_ClipWindowXOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET4_ClipWindowXOffset4_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET4_ClipWindowXOffset4_MASK)
74381#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET4_ClipWindowYOffset4_MASK (0x7FFF0000U)
74382#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET4_ClipWindowYOffset4_SHIFT (16U)
74383/*! ClipWindowYOffset4 - Vertical position (Y).
74384 */
74385#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET4_ClipWindowYOffset4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET4_ClipWindowYOffset4_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET4_ClipWindowYOffset4_MASK)
74386/*! @} */
74387
74388/*! @name FETCHWARP9_CLIPWINDOWDIMENSIONS4 - Clip window size for layer 4. */
74389/*! @{ */
74390#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_MASK (0x3FFFU)
74391#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_SHIFT (0U)
74392/*! ClipWindowWidth4 - Width.
74393 */
74394#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS4_ClipWindowWidth4_MASK)
74395#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_MASK (0x3FFF0000U)
74396#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_SHIFT (16U)
74397/*! ClipWindowHeight4 - Height.
74398 */
74399#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS4_ClipWindowHeight4_MASK)
74400/*! @} */
74401
74402/*! @name FETCHWARP9_CONSTANTCOLOR4 - Constant color for layer 4. */
74403/*! @{ */
74404#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantAlpha4_MASK (0xFFU)
74405#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantAlpha4_SHIFT (0U)
74406/*! ConstantAlpha4 - Alpha.
74407 */
74408#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantAlpha4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantAlpha4_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantAlpha4_MASK)
74409#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantBlue4_MASK (0xFF00U)
74410#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantBlue4_SHIFT (8U)
74411/*! ConstantBlue4 - Blue and V (chroma).
74412 */
74413#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantBlue4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantBlue4_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantBlue4_MASK)
74414#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantGreen4_MASK (0xFF0000U)
74415#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantGreen4_SHIFT (16U)
74416/*! ConstantGreen4 - Green and U (chroma).
74417 */
74418#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantGreen4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantGreen4_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantGreen4_MASK)
74419#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantRed4_MASK (0xFF000000U)
74420#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantRed4_SHIFT (24U)
74421/*! ConstantRed4 - Red and Y (luma).
74422 */
74423#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantRed4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantRed4_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR4_ConstantRed4_MASK)
74424/*! @} */
74425
74426/*! @name FETCHWARP9_LAYERPROPERTY4 - Common properties of layer 4. */
74427/*! @{ */
74428#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_TileMode4_MASK (0x30U)
74429#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_TileMode4_SHIFT (4U)
74430/*! TileMode4 - See TileMode0.
74431 * 0b00..Use zero value
74432 * 0b01..Use constant color register value
74433 * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0.
74434 * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422
74435 * operations or when SourceBufferEnable is 0.
74436 */
74437#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_TileMode4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_TileMode4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_TileMode4_MASK)
74438#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaSrcEnable4_MASK (0x100U)
74439#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaSrcEnable4_SHIFT (8U)
74440/*! AlphaSrcEnable4 - See AlphaSrcSelect0.
74441 */
74442#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaSrcEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaSrcEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaSrcEnable4_MASK)
74443#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaConstEnable4_MASK (0x200U)
74444#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaConstEnable4_SHIFT (9U)
74445/*! AlphaConstEnable4 - See AlphaConstSelect0.
74446 */
74447#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaConstEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaConstEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaConstEnable4_MASK)
74448#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaMaskEnable4_MASK (0x400U)
74449#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaMaskEnable4_SHIFT (10U)
74450/*! AlphaMaskEnable4 - See AlphaMaskSelect0.
74451 */
74452#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaMaskEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaMaskEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaMaskEnable4_MASK)
74453#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaTransEnable4_MASK (0x800U)
74454#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaTransEnable4_SHIFT (11U)
74455/*! AlphaTransEnable4 - See AlphaTransSelect0.
74456 */
74457#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaTransEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaTransEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_AlphaTransEnable4_MASK)
74458#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaSrcEnable4_MASK (0x1000U)
74459#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaSrcEnable4_SHIFT (12U)
74460/*! RGBAlphaSrcEnable4 - See RGBAlphaSrcSelect0.
74461 */
74462#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaSrcEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaSrcEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaSrcEnable4_MASK)
74463#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaConstEnable4_MASK (0x2000U)
74464#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaConstEnable4_SHIFT (13U)
74465/*! RGBAlphaConstEnable4 - See RGBAlphaConstSelect0.
74466 */
74467#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaConstEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaConstEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaConstEnable4_MASK)
74468#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaMaskEnable4_MASK (0x4000U)
74469#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaMaskEnable4_SHIFT (14U)
74470/*! RGBAlphaMaskEnable4 - See RGBAlphaMaskSelect0.
74471 */
74472#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaMaskEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaMaskEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaMaskEnable4_MASK)
74473#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaTransEnable4_MASK (0x8000U)
74474#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaTransEnable4_SHIFT (15U)
74475/*! RGBAlphaTransEnable4 - See RGBAlphaTransSelect0.
74476 */
74477#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaTransEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaTransEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_RGBAlphaTransEnable4_MASK)
74478#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_PremulConstRGB4_MASK (0x10000U)
74479#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_PremulConstRGB4_SHIFT (16U)
74480/*! PremulConstRGB4 - See PremulConstRGB0.
74481 */
74482#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_PremulConstRGB4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_PremulConstRGB4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_PremulConstRGB4_MASK)
74483#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_YUVConversionMode4_MASK (0x60000U)
74484#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_YUVConversionMode4_SHIFT (17U)
74485/*! YUVConversionMode4 - See YUVConversionMode0.
74486 * 0b00..No conversion.
74487 * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV).
74488 * Input range is 16..235 for Y and 16..240 for U/V.
74489 * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV
74490 * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding).
74491 * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV).
74492 * Input range is 16..235 for Y and 16..240 for U/V.
74493 */
74494#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_YUVConversionMode4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_YUVConversionMode4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_YUVConversionMode4_MASK)
74495#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_GammaRemoveEnable4_MASK (0x100000U)
74496#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_GammaRemoveEnable4_SHIFT (20U)
74497/*! GammaRemoveEnable4 - See GammaRemoveEnable0.
74498 */
74499#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_GammaRemoveEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_GammaRemoveEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_GammaRemoveEnable4_MASK)
74500#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_ClipWindowEnable4_MASK (0x40000000U)
74501#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_ClipWindowEnable4_SHIFT (30U)
74502/*! ClipWindowEnable4 - See ClipWindowEnable0.
74503 */
74504#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_ClipWindowEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_ClipWindowEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_ClipWindowEnable4_MASK)
74505#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_SourceBufferEnable4_MASK (0x80000000U)
74506#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_SourceBufferEnable4_SHIFT (31U)
74507/*! SourceBufferEnable4 - See SourceBufferEnable0.
74508 */
74509#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_SourceBufferEnable4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_SourceBufferEnable4_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY4_SourceBufferEnable4_MASK)
74510/*! @} */
74511
74512/*! @name FETCHWARP9_BASEADDRESS5 - Source buffer base address of layer 5. */
74513/*! @{ */
74514#define IRIS_MVPL_FETCHWARP9_BASEADDRESS5_BaseAddress5_MASK (0xFFFFFFFFU)
74515#define IRIS_MVPL_FETCHWARP9_BASEADDRESS5_BaseAddress5_SHIFT (0U)
74516/*! BaseAddress5 - See BaseAddress0.
74517 */
74518#define IRIS_MVPL_FETCHWARP9_BASEADDRESS5_BaseAddress5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BASEADDRESS5_BaseAddress5_SHIFT)) & IRIS_MVPL_FETCHWARP9_BASEADDRESS5_BaseAddress5_MASK)
74519/*! @} */
74520
74521/*! @name FETCHWARP9_SOURCEBUFFERATTRIBUTES5 - Source buffer attributes for layer 5. */
74522/*! @{ */
74523#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_Stride5_MASK (0xFFFFU)
74524#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_Stride5_SHIFT (0U)
74525/*! Stride5 - See Stride0.
74526 */
74527#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_Stride5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_Stride5_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_Stride5_MASK)
74528#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_MASK (0x3F0000U)
74529#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_SHIFT (16U)
74530/*! BitsPerPixel5 - See BitsPerPixel0.
74531 */
74532#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES5_BitsPerPixel5_MASK)
74533/*! @} */
74534
74535/*! @name FETCHWARP9_SOURCEBUFFERDIMENSION5 - Source buffer dimension of layer 5. */
74536/*! @{ */
74537#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION5_LineWidth5_MASK (0x3FFFU)
74538#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION5_LineWidth5_SHIFT (0U)
74539/*! LineWidth5 - See LineWidth0.
74540 */
74541#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION5_LineWidth5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION5_LineWidth5_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION5_LineWidth5_MASK)
74542#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION5_LineCount5_MASK (0x3FFF0000U)
74543#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION5_LineCount5_SHIFT (16U)
74544/*! LineCount5 - See LineCount0.
74545 */
74546#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION5_LineCount5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION5_LineCount5_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION5_LineCount5_MASK)
74547/*! @} */
74548
74549/*! @name FETCHWARP9_COLORCOMPONENTBITS5 - Size of color components for RGB, YUV and index formats (layer 5). */
74550/*! @{ */
74551#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsAlpha5_MASK (0xFU)
74552#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsAlpha5_SHIFT (0U)
74553/*! ComponentBitsAlpha5 - Alpha.
74554 */
74555#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsAlpha5_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsAlpha5_MASK)
74556#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsBlue5_MASK (0xF00U)
74557#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsBlue5_SHIFT (8U)
74558/*! ComponentBitsBlue5 - Blue and V (chroma).
74559 */
74560#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsBlue5_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsBlue5_MASK)
74561#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsGreen5_MASK (0xF0000U)
74562#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsGreen5_SHIFT (16U)
74563/*! ComponentBitsGreen5 - Green and U (chroma).
74564 */
74565#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsGreen5_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsGreen5_MASK)
74566#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsRed5_MASK (0xF000000U)
74567#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsRed5_SHIFT (24U)
74568/*! ComponentBitsRed5 - Red, Y (luma) and palette index.
74569 */
74570#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsRed5_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ComponentBitsRed5_MASK)
74571#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ITUFormat5_MASK (0x80000000U)
74572#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ITUFormat5_SHIFT (31U)
74573/*! ITUFormat5 - See ITUFormat0.
74574 */
74575#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ITUFormat5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ITUFormat5_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS5_ITUFormat5_MASK)
74576/*! @} */
74577
74578/*! @name FETCHWARP9_COLORCOMPONENTSHIFT5 - Bit position of color components for RGB, YUV and index formats (layer 5). */
74579/*! @{ */
74580#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_MASK (0x1FU)
74581#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_SHIFT (0U)
74582/*! ComponentShiftAlpha5 - Alpha.
74583 */
74584#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftAlpha5_MASK)
74585#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_MASK (0x1F00U)
74586#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_SHIFT (8U)
74587/*! ComponentShiftBlue5 - Blue and V (chroma).
74588 */
74589#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftBlue5_MASK)
74590#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_MASK (0x1F0000U)
74591#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_SHIFT (16U)
74592/*! ComponentShiftGreen5 - Green and U (chroma).
74593 */
74594#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftGreen5_MASK)
74595#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftRed5_MASK (0x1F000000U)
74596#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftRed5_SHIFT (24U)
74597/*! ComponentShiftRed5 - Red, Y (luma) and palette index.
74598 */
74599#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftRed5_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT5_ComponentShiftRed5_MASK)
74600/*! @} */
74601
74602/*! @name FETCHWARP9_LAYEROFFSET5 - Position of layer 5 within the destination frame. */
74603/*! @{ */
74604#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET5_LayerXOffset5_MASK (0x7FFFU)
74605#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET5_LayerXOffset5_SHIFT (0U)
74606/*! LayerXOffset5 - Horizontal offset (X).
74607 */
74608#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET5_LayerXOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET5_LayerXOffset5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET5_LayerXOffset5_MASK)
74609#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET5_LayerYOffset5_MASK (0x7FFF0000U)
74610#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET5_LayerYOffset5_SHIFT (16U)
74611/*! LayerYOffset5 - Vertical offset (Y).
74612 */
74613#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET5_LayerYOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET5_LayerYOffset5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET5_LayerYOffset5_MASK)
74614/*! @} */
74615
74616/*! @name FETCHWARP9_CLIPWINDOWOFFSET5 - Clip window position for layer 5. */
74617/*! @{ */
74618#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET5_ClipWindowXOffset5_MASK (0x7FFFU)
74619#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET5_ClipWindowXOffset5_SHIFT (0U)
74620/*! ClipWindowXOffset5 - Horizontal position (X).
74621 */
74622#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET5_ClipWindowXOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET5_ClipWindowXOffset5_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET5_ClipWindowXOffset5_MASK)
74623#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET5_ClipWindowYOffset5_MASK (0x7FFF0000U)
74624#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET5_ClipWindowYOffset5_SHIFT (16U)
74625/*! ClipWindowYOffset5 - Vertical position (Y).
74626 */
74627#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET5_ClipWindowYOffset5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET5_ClipWindowYOffset5_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET5_ClipWindowYOffset5_MASK)
74628/*! @} */
74629
74630/*! @name FETCHWARP9_CLIPWINDOWDIMENSIONS5 - Clip window size for layer 5. */
74631/*! @{ */
74632#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_MASK (0x3FFFU)
74633#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_SHIFT (0U)
74634/*! ClipWindowWidth5 - Width.
74635 */
74636#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS5_ClipWindowWidth5_MASK)
74637#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_MASK (0x3FFF0000U)
74638#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_SHIFT (16U)
74639/*! ClipWindowHeight5 - Height.
74640 */
74641#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS5_ClipWindowHeight5_MASK)
74642/*! @} */
74643
74644/*! @name FETCHWARP9_CONSTANTCOLOR5 - Constant color for layer 5. */
74645/*! @{ */
74646#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantAlpha5_MASK (0xFFU)
74647#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantAlpha5_SHIFT (0U)
74648/*! ConstantAlpha5 - Alpha.
74649 */
74650#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantAlpha5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantAlpha5_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantAlpha5_MASK)
74651#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantBlue5_MASK (0xFF00U)
74652#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantBlue5_SHIFT (8U)
74653/*! ConstantBlue5 - Blue and V (chroma).
74654 */
74655#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantBlue5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantBlue5_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantBlue5_MASK)
74656#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantGreen5_MASK (0xFF0000U)
74657#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantGreen5_SHIFT (16U)
74658/*! ConstantGreen5 - Green and U (chroma).
74659 */
74660#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantGreen5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantGreen5_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantGreen5_MASK)
74661#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantRed5_MASK (0xFF000000U)
74662#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantRed5_SHIFT (24U)
74663/*! ConstantRed5 - Red and Y (luma).
74664 */
74665#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantRed5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantRed5_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR5_ConstantRed5_MASK)
74666/*! @} */
74667
74668/*! @name FETCHWARP9_LAYERPROPERTY5 - Common properties of layer 5. */
74669/*! @{ */
74670#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_TileMode5_MASK (0x30U)
74671#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_TileMode5_SHIFT (4U)
74672/*! TileMode5 - See TileMode0.
74673 * 0b00..Use zero value
74674 * 0b01..Use constant color register value
74675 * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0.
74676 * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422
74677 * operations or when SourceBufferEnable is 0.
74678 */
74679#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_TileMode5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_TileMode5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_TileMode5_MASK)
74680#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaSrcEnable5_MASK (0x100U)
74681#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaSrcEnable5_SHIFT (8U)
74682/*! AlphaSrcEnable5 - See AlphaSrcSelect0.
74683 */
74684#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaSrcEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaSrcEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaSrcEnable5_MASK)
74685#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaConstEnable5_MASK (0x200U)
74686#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaConstEnable5_SHIFT (9U)
74687/*! AlphaConstEnable5 - See AlphaConstSelect0.
74688 */
74689#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaConstEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaConstEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaConstEnable5_MASK)
74690#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaMaskEnable5_MASK (0x400U)
74691#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaMaskEnable5_SHIFT (10U)
74692/*! AlphaMaskEnable5 - See AlphaMaskSelect0.
74693 */
74694#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaMaskEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaMaskEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaMaskEnable5_MASK)
74695#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaTransEnable5_MASK (0x800U)
74696#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaTransEnable5_SHIFT (11U)
74697/*! AlphaTransEnable5 - See AlphaTransSelect0.
74698 */
74699#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaTransEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaTransEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_AlphaTransEnable5_MASK)
74700#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaSrcEnable5_MASK (0x1000U)
74701#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaSrcEnable5_SHIFT (12U)
74702/*! RGBAlphaSrcEnable5 - See RGBAlphaSrcSelect0.
74703 */
74704#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaSrcEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaSrcEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaSrcEnable5_MASK)
74705#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaConstEnable5_MASK (0x2000U)
74706#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaConstEnable5_SHIFT (13U)
74707/*! RGBAlphaConstEnable5 - See RGBAlphaConstSelect0.
74708 */
74709#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaConstEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaConstEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaConstEnable5_MASK)
74710#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaMaskEnable5_MASK (0x4000U)
74711#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaMaskEnable5_SHIFT (14U)
74712/*! RGBAlphaMaskEnable5 - See RGBAlphaMaskSelect0.
74713 */
74714#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaMaskEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaMaskEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaMaskEnable5_MASK)
74715#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaTransEnable5_MASK (0x8000U)
74716#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaTransEnable5_SHIFT (15U)
74717/*! RGBAlphaTransEnable5 - See RGBAlphaTransSelect0.
74718 */
74719#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaTransEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaTransEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_RGBAlphaTransEnable5_MASK)
74720#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_PremulConstRGB5_MASK (0x10000U)
74721#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_PremulConstRGB5_SHIFT (16U)
74722/*! PremulConstRGB5 - See PremulConstRGB0.
74723 */
74724#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_PremulConstRGB5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_PremulConstRGB5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_PremulConstRGB5_MASK)
74725#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_YUVConversionMode5_MASK (0x60000U)
74726#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_YUVConversionMode5_SHIFT (17U)
74727/*! YUVConversionMode5 - See YUVConversionMode0.
74728 * 0b00..No conversion.
74729 * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV).
74730 * Input range is 16..235 for Y and 16..240 for U/V.
74731 * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV
74732 * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding).
74733 * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV).
74734 * Input range is 16..235 for Y and 16..240 for U/V.
74735 */
74736#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_YUVConversionMode5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_YUVConversionMode5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_YUVConversionMode5_MASK)
74737#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_GammaRemoveEnable5_MASK (0x100000U)
74738#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_GammaRemoveEnable5_SHIFT (20U)
74739/*! GammaRemoveEnable5 - See GammaRemoveEnable0.
74740 */
74741#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_GammaRemoveEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_GammaRemoveEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_GammaRemoveEnable5_MASK)
74742#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_ClipWindowEnable5_MASK (0x40000000U)
74743#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_ClipWindowEnable5_SHIFT (30U)
74744/*! ClipWindowEnable5 - See ClipWindowEnable0.
74745 */
74746#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_ClipWindowEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_ClipWindowEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_ClipWindowEnable5_MASK)
74747#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_SourceBufferEnable5_MASK (0x80000000U)
74748#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_SourceBufferEnable5_SHIFT (31U)
74749/*! SourceBufferEnable5 - See SourceBufferEnable0.
74750 */
74751#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_SourceBufferEnable5(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_SourceBufferEnable5_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY5_SourceBufferEnable5_MASK)
74752/*! @} */
74753
74754/*! @name FETCHWARP9_BASEADDRESS6 - Source buffer base address of layer 6. */
74755/*! @{ */
74756#define IRIS_MVPL_FETCHWARP9_BASEADDRESS6_BaseAddress6_MASK (0xFFFFFFFFU)
74757#define IRIS_MVPL_FETCHWARP9_BASEADDRESS6_BaseAddress6_SHIFT (0U)
74758/*! BaseAddress6 - See BaseAddress0.
74759 */
74760#define IRIS_MVPL_FETCHWARP9_BASEADDRESS6_BaseAddress6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BASEADDRESS6_BaseAddress6_SHIFT)) & IRIS_MVPL_FETCHWARP9_BASEADDRESS6_BaseAddress6_MASK)
74761/*! @} */
74762
74763/*! @name FETCHWARP9_SOURCEBUFFERATTRIBUTES6 - Source buffer attributes for layer 6. */
74764/*! @{ */
74765#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_Stride6_MASK (0xFFFFU)
74766#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_Stride6_SHIFT (0U)
74767/*! Stride6 - See Stride0.
74768 */
74769#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_Stride6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_Stride6_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_Stride6_MASK)
74770#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_MASK (0x3F0000U)
74771#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_SHIFT (16U)
74772/*! BitsPerPixel6 - See BitsPerPixel0.
74773 */
74774#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES6_BitsPerPixel6_MASK)
74775/*! @} */
74776
74777/*! @name FETCHWARP9_SOURCEBUFFERDIMENSION6 - Source buffer dimension of layer 6. */
74778/*! @{ */
74779#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION6_LineWidth6_MASK (0x3FFFU)
74780#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION6_LineWidth6_SHIFT (0U)
74781/*! LineWidth6 - See LineWidth0.
74782 */
74783#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION6_LineWidth6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION6_LineWidth6_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION6_LineWidth6_MASK)
74784#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION6_LineCount6_MASK (0x3FFF0000U)
74785#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION6_LineCount6_SHIFT (16U)
74786/*! LineCount6 - See LineCount0.
74787 */
74788#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION6_LineCount6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION6_LineCount6_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION6_LineCount6_MASK)
74789/*! @} */
74790
74791/*! @name FETCHWARP9_COLORCOMPONENTBITS6 - Size of color components for RGB, YUV and index formats (layer 6). */
74792/*! @{ */
74793#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsAlpha6_MASK (0xFU)
74794#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsAlpha6_SHIFT (0U)
74795/*! ComponentBitsAlpha6 - Alpha.
74796 */
74797#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsAlpha6_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsAlpha6_MASK)
74798#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsBlue6_MASK (0xF00U)
74799#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsBlue6_SHIFT (8U)
74800/*! ComponentBitsBlue6 - Blue and V (chroma).
74801 */
74802#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsBlue6_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsBlue6_MASK)
74803#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsGreen6_MASK (0xF0000U)
74804#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsGreen6_SHIFT (16U)
74805/*! ComponentBitsGreen6 - Green and U (chroma).
74806 */
74807#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsGreen6_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsGreen6_MASK)
74808#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsRed6_MASK (0xF000000U)
74809#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsRed6_SHIFT (24U)
74810/*! ComponentBitsRed6 - Red, Y (luma) and palette index.
74811 */
74812#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsRed6_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ComponentBitsRed6_MASK)
74813#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ITUFormat6_MASK (0x80000000U)
74814#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ITUFormat6_SHIFT (31U)
74815/*! ITUFormat6 - See ITUFormat0.
74816 */
74817#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ITUFormat6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ITUFormat6_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS6_ITUFormat6_MASK)
74818/*! @} */
74819
74820/*! @name FETCHWARP9_COLORCOMPONENTSHIFT6 - Bit position of color components for RGB, YUV and index formats (layer 6). */
74821/*! @{ */
74822#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_MASK (0x1FU)
74823#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_SHIFT (0U)
74824/*! ComponentShiftAlpha6 - Alpha.
74825 */
74826#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftAlpha6_MASK)
74827#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_MASK (0x1F00U)
74828#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_SHIFT (8U)
74829/*! ComponentShiftBlue6 - Blue and V (chroma).
74830 */
74831#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftBlue6_MASK)
74832#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_MASK (0x1F0000U)
74833#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_SHIFT (16U)
74834/*! ComponentShiftGreen6 - Green and U (chroma).
74835 */
74836#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftGreen6_MASK)
74837#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftRed6_MASK (0x1F000000U)
74838#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftRed6_SHIFT (24U)
74839/*! ComponentShiftRed6 - Red, Y (luma) and palette index.
74840 */
74841#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftRed6_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT6_ComponentShiftRed6_MASK)
74842/*! @} */
74843
74844/*! @name FETCHWARP9_LAYEROFFSET6 - Position of layer 1 within the destination frame. */
74845/*! @{ */
74846#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET6_LayerXOffset6_MASK (0x7FFFU)
74847#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET6_LayerXOffset6_SHIFT (0U)
74848/*! LayerXOffset6 - Horizontal offset (X).
74849 */
74850#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET6_LayerXOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET6_LayerXOffset6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET6_LayerXOffset6_MASK)
74851#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET6_LayerYOffset6_MASK (0x7FFF0000U)
74852#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET6_LayerYOffset6_SHIFT (16U)
74853/*! LayerYOffset6 - Vertical offset (Y).
74854 */
74855#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET6_LayerYOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET6_LayerYOffset6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET6_LayerYOffset6_MASK)
74856/*! @} */
74857
74858/*! @name FETCHWARP9_CLIPWINDOWOFFSET6 - Clip window position for layer 6. */
74859/*! @{ */
74860#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET6_ClipWindowXOffset6_MASK (0x7FFFU)
74861#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET6_ClipWindowXOffset6_SHIFT (0U)
74862/*! ClipWindowXOffset6 - Horizontal position (X).
74863 */
74864#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET6_ClipWindowXOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET6_ClipWindowXOffset6_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET6_ClipWindowXOffset6_MASK)
74865#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET6_ClipWindowYOffset6_MASK (0x7FFF0000U)
74866#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET6_ClipWindowYOffset6_SHIFT (16U)
74867/*! ClipWindowYOffset6 - Vertical position (Y).
74868 */
74869#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET6_ClipWindowYOffset6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET6_ClipWindowYOffset6_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET6_ClipWindowYOffset6_MASK)
74870/*! @} */
74871
74872/*! @name FETCHWARP9_CLIPWINDOWDIMENSIONS6 - Clip window size for layer 6. */
74873/*! @{ */
74874#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_MASK (0x3FFFU)
74875#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_SHIFT (0U)
74876/*! ClipWindowWidth6 - Width.
74877 */
74878#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS6_ClipWindowWidth6_MASK)
74879#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_MASK (0x3FFF0000U)
74880#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_SHIFT (16U)
74881/*! ClipWindowHeight6 - Height.
74882 */
74883#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS6_ClipWindowHeight6_MASK)
74884/*! @} */
74885
74886/*! @name FETCHWARP9_CONSTANTCOLOR6 - Constant color for layer 6. */
74887/*! @{ */
74888#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantAlpha6_MASK (0xFFU)
74889#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantAlpha6_SHIFT (0U)
74890/*! ConstantAlpha6 - Alpha.
74891 */
74892#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantAlpha6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantAlpha6_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantAlpha6_MASK)
74893#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantBlue6_MASK (0xFF00U)
74894#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantBlue6_SHIFT (8U)
74895/*! ConstantBlue6 - Blue and V (chroma).
74896 */
74897#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantBlue6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantBlue6_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantBlue6_MASK)
74898#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantGreen6_MASK (0xFF0000U)
74899#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantGreen6_SHIFT (16U)
74900/*! ConstantGreen6 - Green and U (chroma).
74901 */
74902#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantGreen6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantGreen6_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantGreen6_MASK)
74903#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantRed6_MASK (0xFF000000U)
74904#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantRed6_SHIFT (24U)
74905/*! ConstantRed6 - Red and Y (luma).
74906 */
74907#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantRed6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantRed6_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR6_ConstantRed6_MASK)
74908/*! @} */
74909
74910/*! @name FETCHWARP9_LAYERPROPERTY6 - Common properties of layer 6. */
74911/*! @{ */
74912#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_TileMode6_MASK (0x30U)
74913#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_TileMode6_SHIFT (4U)
74914/*! TileMode6 - See TileMode0.
74915 * 0b00..Use zero value
74916 * 0b01..Use constant color register value
74917 * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0.
74918 * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422
74919 * operations or when SourceBufferEnable is 0.
74920 */
74921#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_TileMode6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_TileMode6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_TileMode6_MASK)
74922#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaSrcEnable6_MASK (0x100U)
74923#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaSrcEnable6_SHIFT (8U)
74924/*! AlphaSrcEnable6 - See AlphaSrcSelect0.
74925 */
74926#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaSrcEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaSrcEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaSrcEnable6_MASK)
74927#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaConstEnable6_MASK (0x200U)
74928#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaConstEnable6_SHIFT (9U)
74929/*! AlphaConstEnable6 - See AlphaConstSelect0.
74930 */
74931#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaConstEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaConstEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaConstEnable6_MASK)
74932#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaMaskEnable6_MASK (0x400U)
74933#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaMaskEnable6_SHIFT (10U)
74934/*! AlphaMaskEnable6 - See AlphaMaskSelect0.
74935 */
74936#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaMaskEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaMaskEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaMaskEnable6_MASK)
74937#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaTransEnable6_MASK (0x800U)
74938#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaTransEnable6_SHIFT (11U)
74939/*! AlphaTransEnable6 - See AlphaTransSelect0.
74940 */
74941#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaTransEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaTransEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_AlphaTransEnable6_MASK)
74942#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaSrcEnable6_MASK (0x1000U)
74943#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaSrcEnable6_SHIFT (12U)
74944/*! RGBAlphaSrcEnable6 - See RGBAlphaSrcSelect0.
74945 */
74946#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaSrcEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaSrcEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaSrcEnable6_MASK)
74947#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaConstEnable6_MASK (0x2000U)
74948#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaConstEnable6_SHIFT (13U)
74949/*! RGBAlphaConstEnable6 - See RGBAlphaConstSelect0.
74950 */
74951#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaConstEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaConstEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaConstEnable6_MASK)
74952#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaMaskEnable6_MASK (0x4000U)
74953#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaMaskEnable6_SHIFT (14U)
74954/*! RGBAlphaMaskEnable6 - See RGBAlphaMaskSelect0.
74955 */
74956#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaMaskEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaMaskEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaMaskEnable6_MASK)
74957#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaTransEnable6_MASK (0x8000U)
74958#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaTransEnable6_SHIFT (15U)
74959/*! RGBAlphaTransEnable6 - See RGBAlphaTransSelect0.
74960 */
74961#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaTransEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaTransEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_RGBAlphaTransEnable6_MASK)
74962#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_PremulConstRGB6_MASK (0x10000U)
74963#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_PremulConstRGB6_SHIFT (16U)
74964/*! PremulConstRGB6 - See PremulConstRGB0.
74965 */
74966#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_PremulConstRGB6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_PremulConstRGB6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_PremulConstRGB6_MASK)
74967#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_YUVConversionMode6_MASK (0x60000U)
74968#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_YUVConversionMode6_SHIFT (17U)
74969/*! YUVConversionMode6 - See YUVConversionMode0.
74970 * 0b00..No conversion.
74971 * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV).
74972 * Input range is 16..235 for Y and 16..240 for U/V.
74973 * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV
74974 * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding).
74975 * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV).
74976 * Input range is 16..235 for Y and 16..240 for U/V.
74977 */
74978#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_YUVConversionMode6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_YUVConversionMode6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_YUVConversionMode6_MASK)
74979#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_GammaRemoveEnable6_MASK (0x100000U)
74980#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_GammaRemoveEnable6_SHIFT (20U)
74981/*! GammaRemoveEnable6 - See GammaRemoveEnable0.
74982 */
74983#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_GammaRemoveEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_GammaRemoveEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_GammaRemoveEnable6_MASK)
74984#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_ClipWindowEnable6_MASK (0x40000000U)
74985#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_ClipWindowEnable6_SHIFT (30U)
74986/*! ClipWindowEnable6 - See ClipWindowEnable0.
74987 */
74988#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_ClipWindowEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_ClipWindowEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_ClipWindowEnable6_MASK)
74989#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_SourceBufferEnable6_MASK (0x80000000U)
74990#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_SourceBufferEnable6_SHIFT (31U)
74991/*! SourceBufferEnable6 - See SourceBufferEnable0.
74992 */
74993#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_SourceBufferEnable6(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_SourceBufferEnable6_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY6_SourceBufferEnable6_MASK)
74994/*! @} */
74995
74996/*! @name FETCHWARP9_BASEADDRESS7 - Source buffer base address of layer 7. */
74997/*! @{ */
74998#define IRIS_MVPL_FETCHWARP9_BASEADDRESS7_BaseAddress7_MASK (0xFFFFFFFFU)
74999#define IRIS_MVPL_FETCHWARP9_BASEADDRESS7_BaseAddress7_SHIFT (0U)
75000/*! BaseAddress7 - See BaseAddress0.
75001 */
75002#define IRIS_MVPL_FETCHWARP9_BASEADDRESS7_BaseAddress7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BASEADDRESS7_BaseAddress7_SHIFT)) & IRIS_MVPL_FETCHWARP9_BASEADDRESS7_BaseAddress7_MASK)
75003/*! @} */
75004
75005/*! @name FETCHWARP9_SOURCEBUFFERATTRIBUTES7 - Source buffer stride for layer 7. */
75006/*! @{ */
75007#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_Stride7_MASK (0xFFFFU)
75008#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_Stride7_SHIFT (0U)
75009/*! Stride7 - See Stride0.
75010 */
75011#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_Stride7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_Stride7_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_Stride7_MASK)
75012#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_MASK (0x3F0000U)
75013#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_SHIFT (16U)
75014/*! BitsPerPixel7 - See BitsPerPixel0.
75015 */
75016#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERATTRIBUTES7_BitsPerPixel7_MASK)
75017/*! @} */
75018
75019/*! @name FETCHWARP9_SOURCEBUFFERDIMENSION7 - Source buffer dimension of layer 7. */
75020/*! @{ */
75021#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION7_LineWidth7_MASK (0x3FFFU)
75022#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION7_LineWidth7_SHIFT (0U)
75023/*! LineWidth7 - See LineWidth0.
75024 */
75025#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION7_LineWidth7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION7_LineWidth7_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION7_LineWidth7_MASK)
75026#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION7_LineCount7_MASK (0x3FFF0000U)
75027#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION7_LineCount7_SHIFT (16U)
75028/*! LineCount7 - See LineCount0.
75029 */
75030#define IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION7_LineCount7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION7_LineCount7_SHIFT)) & IRIS_MVPL_FETCHWARP9_SOURCEBUFFERDIMENSION7_LineCount7_MASK)
75031/*! @} */
75032
75033/*! @name FETCHWARP9_COLORCOMPONENTBITS7 - Size of color components for RGB, YUV and index formats (layer 7). */
75034/*! @{ */
75035#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsAlpha7_MASK (0xFU)
75036#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsAlpha7_SHIFT (0U)
75037/*! ComponentBitsAlpha7 - Alpha.
75038 */
75039#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsAlpha7_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsAlpha7_MASK)
75040#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsBlue7_MASK (0xF00U)
75041#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsBlue7_SHIFT (8U)
75042/*! ComponentBitsBlue7 - Blue and V (chroma).
75043 */
75044#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsBlue7_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsBlue7_MASK)
75045#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsGreen7_MASK (0xF0000U)
75046#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsGreen7_SHIFT (16U)
75047/*! ComponentBitsGreen7 - Green and U (chroma).
75048 */
75049#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsGreen7_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsGreen7_MASK)
75050#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsRed7_MASK (0xF000000U)
75051#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsRed7_SHIFT (24U)
75052/*! ComponentBitsRed7 - Red, Y (luma) and palette index.
75053 */
75054#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsRed7_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ComponentBitsRed7_MASK)
75055#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ITUFormat7_MASK (0x80000000U)
75056#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ITUFormat7_SHIFT (31U)
75057/*! ITUFormat7 - See ITUFormat0.
75058 */
75059#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ITUFormat7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ITUFormat7_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTBITS7_ITUFormat7_MASK)
75060/*! @} */
75061
75062/*! @name FETCHWARP9_COLORCOMPONENTSHIFT7 - Bit position of color components for RGB, YUV and index formats (layer 7). */
75063/*! @{ */
75064#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_MASK (0x1FU)
75065#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_SHIFT (0U)
75066/*! ComponentShiftAlpha7 - Alpha.
75067 */
75068#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftAlpha7_MASK)
75069#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_MASK (0x1F00U)
75070#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_SHIFT (8U)
75071/*! ComponentShiftBlue7 - Blue and V (chroma).
75072 */
75073#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftBlue7_MASK)
75074#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_MASK (0x1F0000U)
75075#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_SHIFT (16U)
75076/*! ComponentShiftGreen7 - Green and U (chroma).
75077 */
75078#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftGreen7_MASK)
75079#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftRed7_MASK (0x1F000000U)
75080#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftRed7_SHIFT (24U)
75081/*! ComponentShiftRed7 - Red, Y (luma) and palette index.
75082 */
75083#define IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftRed7_SHIFT)) & IRIS_MVPL_FETCHWARP9_COLORCOMPONENTSHIFT7_ComponentShiftRed7_MASK)
75084/*! @} */
75085
75086/*! @name FETCHWARP9_LAYEROFFSET7 - Position of layer 7 within the destination frame. */
75087/*! @{ */
75088#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET7_LayerXOffset7_MASK (0x7FFFU)
75089#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET7_LayerXOffset7_SHIFT (0U)
75090/*! LayerXOffset7 - Horizontal offset (X).
75091 */
75092#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET7_LayerXOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET7_LayerXOffset7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET7_LayerXOffset7_MASK)
75093#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET7_LayerYOffset7_MASK (0x7FFF0000U)
75094#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET7_LayerYOffset7_SHIFT (16U)
75095/*! LayerYOffset7 - Vertical offset (Y).
75096 */
75097#define IRIS_MVPL_FETCHWARP9_LAYEROFFSET7_LayerYOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYEROFFSET7_LayerYOffset7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYEROFFSET7_LayerYOffset7_MASK)
75098/*! @} */
75099
75100/*! @name FETCHWARP9_CLIPWINDOWOFFSET7 - Clip window position for layer 7. */
75101/*! @{ */
75102#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET7_ClipWindowXOffset7_MASK (0x7FFFU)
75103#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET7_ClipWindowXOffset7_SHIFT (0U)
75104/*! ClipWindowXOffset7 - Horizontal position (X).
75105 */
75106#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET7_ClipWindowXOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET7_ClipWindowXOffset7_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET7_ClipWindowXOffset7_MASK)
75107#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET7_ClipWindowYOffset7_MASK (0x7FFF0000U)
75108#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET7_ClipWindowYOffset7_SHIFT (16U)
75109/*! ClipWindowYOffset7 - Vertical position (Y).
75110 */
75111#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET7_ClipWindowYOffset7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET7_ClipWindowYOffset7_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWOFFSET7_ClipWindowYOffset7_MASK)
75112/*! @} */
75113
75114/*! @name FETCHWARP9_CLIPWINDOWDIMENSIONS7 - Clip window size for layer 7. */
75115/*! @{ */
75116#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_MASK (0x3FFFU)
75117#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_SHIFT (0U)
75118/*! ClipWindowWidth7 - Width.
75119 */
75120#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS7_ClipWindowWidth7_MASK)
75121#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_MASK (0x3FFF0000U)
75122#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_SHIFT (16U)
75123/*! ClipWindowHeight7 - Height.
75124 */
75125#define IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_SHIFT)) & IRIS_MVPL_FETCHWARP9_CLIPWINDOWDIMENSIONS7_ClipWindowHeight7_MASK)
75126/*! @} */
75127
75128/*! @name FETCHWARP9_CONSTANTCOLOR7 - Constant color for layer 7. */
75129/*! @{ */
75130#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantAlpha7_MASK (0xFFU)
75131#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantAlpha7_SHIFT (0U)
75132/*! ConstantAlpha7 - Alpha.
75133 */
75134#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantAlpha7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantAlpha7_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantAlpha7_MASK)
75135#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantBlue7_MASK (0xFF00U)
75136#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantBlue7_SHIFT (8U)
75137/*! ConstantBlue7 - Blue and V (chroma).
75138 */
75139#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantBlue7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantBlue7_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantBlue7_MASK)
75140#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantGreen7_MASK (0xFF0000U)
75141#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantGreen7_SHIFT (16U)
75142/*! ConstantGreen7 - Green and U (chroma).
75143 */
75144#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantGreen7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantGreen7_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantGreen7_MASK)
75145#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantRed7_MASK (0xFF000000U)
75146#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantRed7_SHIFT (24U)
75147/*! ConstantRed7 - Red and Y (luma).
75148 */
75149#define IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantRed7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantRed7_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONSTANTCOLOR7_ConstantRed7_MASK)
75150/*! @} */
75151
75152/*! @name FETCHWARP9_LAYERPROPERTY7 - Common properties of layer 7. */
75153/*! @{ */
75154#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_TileMode7_MASK (0x30U)
75155#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_TileMode7_SHIFT (4U)
75156/*! TileMode7 - See TileMode0.
75157 * 0b00..Use zero value
75158 * 0b01..Use constant color register value
75159 * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0.
75160 * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422
75161 * operations or when SourceBufferEnable is 0.
75162 */
75163#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_TileMode7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_TileMode7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_TileMode7_MASK)
75164#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaSrcEnable7_MASK (0x100U)
75165#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaSrcEnable7_SHIFT (8U)
75166/*! AlphaSrcEnable7 - See AlphaSrcSelect0.
75167 */
75168#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaSrcEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaSrcEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaSrcEnable7_MASK)
75169#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaConstEnable7_MASK (0x200U)
75170#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaConstEnable7_SHIFT (9U)
75171/*! AlphaConstEnable7 - See AlphaConstSelect0.
75172 */
75173#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaConstEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaConstEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaConstEnable7_MASK)
75174#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaMaskEnable7_MASK (0x400U)
75175#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaMaskEnable7_SHIFT (10U)
75176/*! AlphaMaskEnable7 - See AlphaMaskSelect0.
75177 */
75178#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaMaskEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaMaskEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaMaskEnable7_MASK)
75179#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaTransEnable7_MASK (0x800U)
75180#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaTransEnable7_SHIFT (11U)
75181/*! AlphaTransEnable7 - See AlphaTransSelect0.
75182 */
75183#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaTransEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaTransEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_AlphaTransEnable7_MASK)
75184#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaSrcEnable7_MASK (0x1000U)
75185#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaSrcEnable7_SHIFT (12U)
75186/*! RGBAlphaSrcEnable7 - See RGBAlphaSrcSelect0.
75187 */
75188#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaSrcEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaSrcEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaSrcEnable7_MASK)
75189#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaConstEnable7_MASK (0x2000U)
75190#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaConstEnable7_SHIFT (13U)
75191/*! RGBAlphaConstEnable7 - See RGBAlphaConstSelect0.
75192 */
75193#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaConstEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaConstEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaConstEnable7_MASK)
75194#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaMaskEnable7_MASK (0x4000U)
75195#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaMaskEnable7_SHIFT (14U)
75196/*! RGBAlphaMaskEnable7 - See RGBAlphaMaskSelect0.
75197 */
75198#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaMaskEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaMaskEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaMaskEnable7_MASK)
75199#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaTransEnable7_MASK (0x8000U)
75200#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaTransEnable7_SHIFT (15U)
75201/*! RGBAlphaTransEnable7 - See RGBAlphaTransSelect0.
75202 */
75203#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaTransEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaTransEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_RGBAlphaTransEnable7_MASK)
75204#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_PremulConstRGB7_MASK (0x10000U)
75205#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_PremulConstRGB7_SHIFT (16U)
75206/*! PremulConstRGB7 - See PremulConstRGB0.
75207 */
75208#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_PremulConstRGB7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_PremulConstRGB7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_PremulConstRGB7_MASK)
75209#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_YUVConversionMode7_MASK (0x60000U)
75210#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_YUVConversionMode7_SHIFT (17U)
75211/*! YUVConversionMode7 - See YUVConversionMode0.
75212 * 0b00..No conversion.
75213 * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV).
75214 * Input range is 16..235 for Y and 16..240 for U/V.
75215 * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV
75216 * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding).
75217 * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV).
75218 * Input range is 16..235 for Y and 16..240 for U/V.
75219 */
75220#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_YUVConversionMode7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_YUVConversionMode7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_YUVConversionMode7_MASK)
75221#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_GammaRemoveEnable7_MASK (0x100000U)
75222#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_GammaRemoveEnable7_SHIFT (20U)
75223/*! GammaRemoveEnable7 - See GammaRemoveEnable0.
75224 */
75225#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_GammaRemoveEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_GammaRemoveEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_GammaRemoveEnable7_MASK)
75226#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_ClipWindowEnable7_MASK (0x40000000U)
75227#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_ClipWindowEnable7_SHIFT (30U)
75228/*! ClipWindowEnable7 - See ClipWindowEnable0.
75229 */
75230#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_ClipWindowEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_ClipWindowEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_ClipWindowEnable7_MASK)
75231#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_SourceBufferEnable7_MASK (0x80000000U)
75232#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_SourceBufferEnable7_SHIFT (31U)
75233/*! SourceBufferEnable7 - See SourceBufferEnable0.
75234 */
75235#define IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_SourceBufferEnable7(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_SourceBufferEnable7_SHIFT)) & IRIS_MVPL_FETCHWARP9_LAYERPROPERTY7_SourceBufferEnable7_MASK)
75236/*! @} */
75237
75238/*! @name FETCHWARP9_FRAMEDIMENSIONS - Output frame dimension. */
75239/*! @{ */
75240#define IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
75241#define IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
75242/*! FrameWidth - Frame width minus one.
75243 */
75244#define IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_FrameWidth_MASK)
75245#define IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
75246#define IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
75247/*! FrameHeight - Frame height minus one.
75248 */
75249#define IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_FrameHeight_MASK)
75250#define IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
75251#define IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
75252/*! EmptyFrame - When enabled output frame is empty. FrameWidth/Height settings have no effect then.
75253 * Can be used to load shadows or to generate synchronization signals only (frame/sequence
75254 * complete). If enabled, InputSelect must be set to INACTIVE.
75255 */
75256#define IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHWARP9_FRAMEDIMENSIONS_EmptyFrame_MASK)
75257/*! @} */
75258
75259/*! @name FETCHWARP9_FRAMERESAMPLING - Resampling options for output frame. */
75260/*! @{ */
75261#define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_StartX_MASK (0x3FU)
75262#define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_StartX_SHIFT (0U)
75263/*! StartX - X coordinate of first sample point relative to origin.
75264 */
75265#define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_StartX_MASK)
75266#define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_StartY_MASK (0xFC0U)
75267#define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_StartY_SHIFT (6U)
75268/*! StartY - Y coordinate of first sample point relative to origin.
75269 */
75270#define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_StartY_MASK)
75271#define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_DeltaX_MASK (0x3F000U)
75272#define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_DeltaX_SHIFT (12U)
75273/*! DeltaX - Increment of X coordinate for horizontal step in destination frame.
75274 */
75275#define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_DeltaX_MASK)
75276#define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U)
75277#define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_DeltaY_SHIFT (18U)
75278/*! DeltaY - Increment of Y coordinate for vertical step in destination frame.
75279 */
75280#define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_DeltaY_MASK)
75281#define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U)
75282#define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_SwapDirection_SHIFT (24U)
75283/*! SwapDirection - Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied
75284 * for horizontal and DeltaX for vertical step on destination frame.
75285 */
75286#define IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHWARP9_FRAMERESAMPLING_SwapDirection_MASK)
75287/*! @} */
75288
75289/*! @name FETCHWARP9_WARPCONTROL - Warping control options. */
75290/*! @{ */
75291#define IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpBitsPerPixel_MASK (0x3FU)
75292#define IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpBitsPerPixel_SHIFT (0U)
75293/*! WarpBitsPerPixel - Number of bits per pixel in the coordinate layer, which is read by another Fetch unit. Has to be 1, 2, 4, 8, 16 or 32.
75294 */
75295#define IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpBitsPerPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpBitsPerPixel_SHIFT)) & IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpBitsPerPixel_MASK)
75296#define IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpCoordinateMode_MASK (0x300U)
75297#define IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpCoordinateMode_SHIFT (8U)
75298/*! WarpCoordinateMode - Content of pixel data in the coordinate layer.
75299 * 0b00..x and y (sample points).
75300 * 0b01..dx and dy (vectors between adjacent sample points).
75301 * 0b10..ddx and ddy (deltas between adjacent vectors).
75302 */
75303#define IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpCoordinateMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpCoordinateMode_SHIFT)) & IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpCoordinateMode_MASK)
75304#define IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpSymmetricOffset_MASK (0x1000U)
75305#define IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpSymmetricOffset_SHIFT (12U)
75306/*! WarpSymmetricOffset - Value 1 enables symmetric range for negative and positive coordinate
75307 * values by adding an offset of +0.03125 internally to all coordinate input values. Recommended for
75308 * small coordinate formats in DD_PNT mode.
75309 */
75310#define IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpSymmetricOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpSymmetricOffset_SHIFT)) & IRIS_MVPL_FETCHWARP9_WARPCONTROL_WarpSymmetricOffset_MASK)
75311/*! @} */
75312
75313/*! @name FETCHWARP9_ARBSTARTX - Start value X for arbitrary warping. */
75314/*! @{ */
75315#define IRIS_MVPL_FETCHWARP9_ARBSTARTX_ArbStartX_MASK (0x1FFFFFU)
75316#define IRIS_MVPL_FETCHWARP9_ARBSTARTX_ArbStartX_SHIFT (0U)
75317/*! ArbStartX - Start point for sample-point interpolation (X coordinate). Given in signed 16.5 fix-point notation.
75318 */
75319#define IRIS_MVPL_FETCHWARP9_ARBSTARTX_ArbStartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_ARBSTARTX_ArbStartX_SHIFT)) & IRIS_MVPL_FETCHWARP9_ARBSTARTX_ArbStartX_MASK)
75320/*! @} */
75321
75322/*! @name FETCHWARP9_ARBSTARTY - Start value Y for arbitrary warping. */
75323/*! @{ */
75324#define IRIS_MVPL_FETCHWARP9_ARBSTARTY_ArbStartY_MASK (0x1FFFFFU)
75325#define IRIS_MVPL_FETCHWARP9_ARBSTARTY_ArbStartY_SHIFT (0U)
75326/*! ArbStartY - Start point for sample-point interpolation (Y coordinate). Given in signed 16.5 fix-point notation.
75327 */
75328#define IRIS_MVPL_FETCHWARP9_ARBSTARTY_ArbStartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_ARBSTARTY_ArbStartY_SHIFT)) & IRIS_MVPL_FETCHWARP9_ARBSTARTY_ArbStartY_MASK)
75329/*! @} */
75330
75331/*! @name FETCHWARP9_ARBDELTA - Start values for delta incrementation of arbitrary warping. */
75332/*! @{ */
75333#define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaXX_MASK (0xFFU)
75334#define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaXX_SHIFT (0U)
75335/*! ArbDeltaXX - X coordinate of vector between first and second sample point. Given in signed 3.5 fix-point notation.
75336 */
75337#define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaXX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaXX_SHIFT)) & IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaXX_MASK)
75338#define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaXY_MASK (0xFF00U)
75339#define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaXY_SHIFT (8U)
75340/*! ArbDeltaXY - Y coordinate of vector between first and second sample point. Given in signed 3.5 fix-point notation.
75341 */
75342#define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaXY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaXY_SHIFT)) & IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaXY_MASK)
75343#define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaYX_MASK (0xFF0000U)
75344#define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaYX_SHIFT (16U)
75345/*! ArbDeltaYX - X coordinate of vector between start and first sample point. Given in signed 3.5 fix-point notation.
75346 */
75347#define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaYX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaYX_SHIFT)) & IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaYX_MASK)
75348#define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaYY_MASK (0xFF000000U)
75349#define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaYY_SHIFT (24U)
75350/*! ArbDeltaYY - Y coordinate of vector between start and first sample point. Given in signed 3.5 fix-point notation.
75351 */
75352#define IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaYY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaYY_SHIFT)) & IRIS_MVPL_FETCHWARP9_ARBDELTA_ArbDeltaYY_MASK)
75353/*! @} */
75354
75355/*! @name FETCHWARP9_FIRPOSITIONS - FIR sequence control register. */
75356/*! @{ */
75357#define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR0Position_MASK (0xFU)
75358#define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR0Position_SHIFT (0U)
75359/*! FIR0Position - Position of first pixel.
75360 */
75361#define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR0Position(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR0Position_SHIFT)) & IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR0Position_MASK)
75362#define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR1Position_MASK (0xF0U)
75363#define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR1Position_SHIFT (4U)
75364/*! FIR1Position - Position of second pixel.
75365 */
75366#define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR1Position(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR1Position_SHIFT)) & IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR1Position_MASK)
75367#define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR2Position_MASK (0xF00U)
75368#define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR2Position_SHIFT (8U)
75369/*! FIR2Position - Position of third pixel.
75370 */
75371#define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR2Position(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR2Position_SHIFT)) & IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR2Position_MASK)
75372#define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR3Position_MASK (0xF000U)
75373#define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR3Position_SHIFT (12U)
75374/*! FIR3Position - Position of fourth pixel.
75375 */
75376#define IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR3Position(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR3Position_SHIFT)) & IRIS_MVPL_FETCHWARP9_FIRPOSITIONS_FIR3Position_MASK)
75377/*! @} */
75378
75379/*! @name FETCHWARP9_FIRCOEFFICIENTS - FIR coefficients register. */
75380/*! @{ */
75381#define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR0Coefficient_MASK (0xFFU)
75382#define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR0Coefficient_SHIFT (0U)
75383/*! FIR0Coefficient - First coefficient.
75384 */
75385#define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR0Coefficient(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR0Coefficient_SHIFT)) & IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR0Coefficient_MASK)
75386#define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR1Coefficient_MASK (0xFF00U)
75387#define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR1Coefficient_SHIFT (8U)
75388/*! FIR1Coefficient - Second coefficient.
75389 */
75390#define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR1Coefficient(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR1Coefficient_SHIFT)) & IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR1Coefficient_MASK)
75391#define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR2Coefficient_MASK (0xFF0000U)
75392#define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR2Coefficient_SHIFT (16U)
75393/*! FIR2Coefficient - Third coefficient.
75394 */
75395#define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR2Coefficient(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR2Coefficient_SHIFT)) & IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR2Coefficient_MASK)
75396#define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR3Coefficient_MASK (0xFF000000U)
75397#define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR3Coefficient_SHIFT (24U)
75398/*! FIR3Coefficient - Fourth coefficient.
75399 */
75400#define IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR3Coefficient(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR3Coefficient_SHIFT)) & IRIS_MVPL_FETCHWARP9_FIRCOEFFICIENTS_FIR3Coefficient_MASK)
75401/*! @} */
75402
75403/*! @name FETCHWARP9_CONTROL - Shared common control settings for all layers. */
75404/*! @{ */
75405#define IRIS_MVPL_FETCHWARP9_CONTROL_RasterMode_MASK (0x7U)
75406#define IRIS_MVPL_FETCHWARP9_CONTROL_RasterMode_SHIFT (0U)
75407/*! RasterMode - Selects a method how to generate source buffer sample points.
75408 * 0b000..First sample at StartX/Y relative to origin. Hor/ver increments using DeltaX/Y and DeltaSwap setup.
75409 * 0b001..[FetchDecode/FetchDecodeL only] Source buffer is an encoded bit stream. First sample at origin (0,0). Hor/ver increments = (1,0)/(0,1).
75410 * 0b010..[FetchPersp/Warp/Rot/RotL only] Arbitrary warping (filter is active). Coordinates are read from frame
75411 * input port. InputSelect must be set to COORDINATE. ArbStartX/Y and ArbDeltaXX/XY/YX/YY must be setup.
75412 * 0b011..[FetchPersp only] Affine/Perspective warping (filter is active). First sample at PerspStartX/Y/W.
75413 * Hor/ver increments using PerspDeltaXX/XY/YX/YY/WX/WY. Homogeneous coordinates.
75414 * 0b100..[FetchPersp/Decode only] Source buffer is packed YUV 4:2:2. First sample at origin (0,0). Hor/ver
75415 * increments = (1,0)/(0,1). All corellated window widths and horizontal offsets must be even.
75416 * 0b101..[FetchRot/RotL only] Affine warping (filter is active). First sample at AffineStartX/Y. Hor/ver
75417 * increments using AffineDeltaXX/XY/YX/YY. Cartesian coordinates.
75418 */
75419#define IRIS_MVPL_FETCHWARP9_CONTROL_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONTROL_RasterMode_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONTROL_RasterMode_MASK)
75420#define IRIS_MVPL_FETCHWARP9_CONTROL_InputSelect_MASK (0x18U)
75421#define IRIS_MVPL_FETCHWARP9_CONTROL_InputSelect_SHIFT (3U)
75422/*! InputSelect - Selects function for the frame input port.
75423 * 0b00..Not used.
75424 * 0b01..Used for component packing (e.g. UV or source alpha buffer).
75425 * 0b10..Used for RGB and alpha pre-multiply stage (mask alpha buffer).
75426 * 0b11..Used for arbitrary warping (coordinate buffer).
75427 */
75428#define IRIS_MVPL_FETCHWARP9_CONTROL_InputSelect(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONTROL_InputSelect_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONTROL_InputSelect_MASK)
75429#define IRIS_MVPL_FETCHWARP9_CONTROL_RawPixel_MASK (0x80U)
75430#define IRIS_MVPL_FETCHWARP9_CONTROL_RawPixel_SHIFT (7U)
75431/*! RawPixel - Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced
75432 * for all layers by fixed values that allow passing the pixel data read from memory unchanged
75433 * to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color
75434 * are deactived. Skip and Tile pixels are not affected by this setting.
75435 */
75436#define IRIS_MVPL_FETCHWARP9_CONTROL_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONTROL_RawPixel_MASK)
75437#define IRIS_MVPL_FETCHWARP9_CONTROL_ClipColor_MASK (0x10000U)
75438#define IRIS_MVPL_FETCHWARP9_CONTROL_ClipColor_SHIFT (16U)
75439/*! ClipColor - Selects which color to take for pixels that do not lie inside the clip window of any layer.
75440 * 0b0..Null color.
75441 * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is
75442 * then the layer's source or tiling color.
75443 */
75444#define IRIS_MVPL_FETCHWARP9_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONTROL_ClipColor_MASK)
75445#define IRIS_MVPL_FETCHWARP9_CONTROL_ClipLayer_MASK (0xE0000U)
75446#define IRIS_MVPL_FETCHWARP9_CONTROL_ClipLayer_SHIFT (17U)
75447/*! ClipLayer - Index of the layer which is used to fill the clipping area of the frame layout when
75448 * ClipColor is set to LAYER. The selected layer must be enabled (LayerEnable).
75449 */
75450#define IRIS_MVPL_FETCHWARP9_CONTROL_ClipLayer(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONTROL_ClipLayer_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONTROL_ClipLayer_MASK)
75451#define IRIS_MVPL_FETCHWARP9_CONTROL_FilterMode_MASK (0x700000U)
75452#define IRIS_MVPL_FETCHWARP9_CONTROL_FilterMode_SHIFT (20U)
75453/*! FilterMode - Use this to select between nearest and bilinear filtering. Only has an effect if
75454 * rastermode == ARBITRARY or rastermode == PERSPECTIVE or rastermode == AFFINE.
75455 * 0b000..Chooses pixel closest to sample point
75456 * 0b001..Calculates result from 4 pixels closest to sample point
75457 * 0b010..FIR mode with 2 programmable pixel positions and coefficients
75458 * 0b011..FIR mode with 4 programmable pixel positions and coefficients
75459 * 0b100..Calculates result from 2 pixels closest to the sample point and on the same line
75460 */
75461#define IRIS_MVPL_FETCHWARP9_CONTROL_FilterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONTROL_FilterMode_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONTROL_FilterMode_MASK)
75462/*! @} */
75463
75464/*! @name FETCHWARP9_TRIGGERENABLE - Shadow load enable flags for all layers. */
75465/*! @{ */
75466#define IRIS_MVPL_FETCHWARP9_TRIGGERENABLE_ShdLdReq_MASK (0xFFU)
75467#define IRIS_MVPL_FETCHWARP9_TRIGGERENABLE_ShdLdReq_SHIFT (0U)
75468/*! ShdLdReq - Shadow load request flags for each layer (one time load).
75469 */
75470#define IRIS_MVPL_FETCHWARP9_TRIGGERENABLE_ShdLdReq(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_TRIGGERENABLE_ShdLdReq_SHIFT)) & IRIS_MVPL_FETCHWARP9_TRIGGERENABLE_ShdLdReq_MASK)
75471/*! @} */
75472
75473/*! @name FETCHWARP9_CONTROLTRIGGER - Shadow load trigger. */
75474/*! @{ */
75475#define IRIS_MVPL_FETCHWARP9_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
75476#define IRIS_MVPL_FETCHWARP9_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
75477/*! ShdTokGen - Writing a 1 to this will load shadow registers into the active configuration with
75478 * the next start of frame and send a shadow load token to subsequent units.
75479 */
75480#define IRIS_MVPL_FETCHWARP9_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHWARP9_CONTROLTRIGGER_ShdTokGen_MASK)
75481/*! @} */
75482
75483/*! @name FETCHWARP9_START - Frame start trigger. */
75484/*! @{ */
75485#define IRIS_MVPL_FETCHWARP9_START_Start_MASK (0x1U)
75486#define IRIS_MVPL_FETCHWARP9_START_Start_SHIFT (0U)
75487/*! Start - Writing a 1 to this field will start generating one frame (for debugging purposes only).
75488 */
75489#define IRIS_MVPL_FETCHWARP9_START_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_START_Start_SHIFT)) & IRIS_MVPL_FETCHWARP9_START_Start_MASK)
75490/*! @} */
75491
75492/*! @name FETCHWARP9_FETCHTYPE - Fetch unit type. */
75493/*! @{ */
75494#define IRIS_MVPL_FETCHWARP9_FETCHTYPE_FetchType_MASK (0xFU)
75495#define IRIS_MVPL_FETCHWARP9_FETCHTYPE_FetchType_SHIFT (0U)
75496/*! FetchType - This field can be used to determine what kind of fetch unit this is.
75497 * 0b0000..Fetch unit with RL and RLAD decoder.
75498 * 0b0001..Fetch unit with fractional plane (8 layers).
75499 * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers).
75500 * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes.
75501 * 0b0100..Fetch unit with affine, perspective and arbitrary warping.
75502 * 0b0101..Fetch unit with affine and arbitrary warping.
75503 * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set.
75504 * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set.
75505 * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set.
75506 */
75507#define IRIS_MVPL_FETCHWARP9_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHWARP9_FETCHTYPE_FetchType_MASK)
75508/*! @} */
75509
75510/*! @name FETCHWARP9_BURSTBUFFERPROPERTIES - Burst buffer properties. */
75511/*! @{ */
75512#define IRIS_MVPL_FETCHWARP9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU)
75513#define IRIS_MVPL_FETCHWARP9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U)
75514/*! ManagedBurstBuffers - Maximum number of burst buffers that can be administrated in the AXI interface.
75515 */
75516#define IRIS_MVPL_FETCHWARP9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHWARP9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK)
75517#define IRIS_MVPL_FETCHWARP9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U)
75518#define IRIS_MVPL_FETCHWARP9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U)
75519/*! BurstLengthForMaxBuffers - Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used.
75520 */
75521#define IRIS_MVPL_FETCHWARP9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHWARP9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK)
75522/*! @} */
75523
75524/*! @name FETCHWARP9_STATUS - Status informations. */
75525/*! @{ */
75526#define IRIS_MVPL_FETCHWARP9_STATUS_WriteTimeout_MASK (0x1U)
75527#define IRIS_MVPL_FETCHWARP9_STATUS_WriteTimeout_SHIFT (0U)
75528/*! WriteTimeout - Timeout detected when writing to the palette entries or shadow token trigger
75529 * enables in fetchlayer derivate. Write 1 to clear.
75530 */
75531#define IRIS_MVPL_FETCHWARP9_STATUS_WriteTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_STATUS_WriteTimeout_SHIFT)) & IRIS_MVPL_FETCHWARP9_STATUS_WriteTimeout_MASK)
75532#define IRIS_MVPL_FETCHWARP9_STATUS_ReadTimeout_MASK (0x10U)
75533#define IRIS_MVPL_FETCHWARP9_STATUS_ReadTimeout_SHIFT (4U)
75534/*! ReadTimeout - Timeout detected when reading from the palette entries or shadow token trigger
75535 * enables in fetchlayer derivate. Write 1 to clear.
75536 */
75537#define IRIS_MVPL_FETCHWARP9_STATUS_ReadTimeout(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_STATUS_ReadTimeout_SHIFT)) & IRIS_MVPL_FETCHWARP9_STATUS_ReadTimeout_MASK)
75538/*! @} */
75539
75540/*! @name FETCHWARP9_HIDDENSTATUS - Hidden status informations. */
75541/*! @{ */
75542#define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusBusy_MASK (0x1U)
75543#define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusBusy_SHIFT (0U)
75544/*! StatusBusy - Fetch unit is busy.
75545 */
75546#define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusBusy_MASK)
75547#define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U)
75548#define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U)
75549/*! StatusBuffersIdle - AXI interface buffers are idle.
75550 */
75551#define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusBuffersIdle_MASK)
75552#define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusRequest_MASK (0x20U)
75553#define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusRequest_SHIFT (5U)
75554/*! StatusRequest - Fetch unit requesting on the AXI interface, waiting for acknowledge.
75555 */
75556#define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusRequest_MASK)
75557#define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusComplete_MASK (0x40U)
75558#define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusComplete_SHIFT (6U)
75559/*! StatusComplete - Fetch unit completed all requested AXI transfers.
75560 */
75561#define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_StatusComplete_MASK)
75562#define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U)
75563#define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_ShadowStatus_SHIFT (8U)
75564/*! ShadowStatus - Shadow load status for all layers (layer index = bit index).
75565 */
75566#define IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHWARP9_HIDDENSTATUS_ShadowStatus_MASK)
75567/*! @} */
75568
75569/*! @name FETCHECO9_LOCKUNLOCK - Register to change the protection status of this address block. */
75570/*! @{ */
75571#define IRIS_MVPL_FETCHECO9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
75572#define IRIS_MVPL_FETCHECO9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
75573/*! LockUnlock - The protection status is changed by writing one of the following key values to this field:
75574 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
75575 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
75576 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
75577 * 0b10110101111000100100011001101110..Disables privilege protection.
75578 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
75579 */
75580#define IRIS_MVPL_FETCHECO9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FETCHECO9_LOCKUNLOCK_LockUnlock_MASK)
75581/*! @} */
75582
75583/*! @name FETCHECO9_LOCKSTATUS - Protection status of this address block. */
75584/*! @{ */
75585#define IRIS_MVPL_FETCHECO9_LOCKSTATUS_LockStatus_MASK (0x1U)
75586#define IRIS_MVPL_FETCHECO9_LOCKSTATUS_LockStatus_SHIFT (0U)
75587/*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
75588 */
75589#define IRIS_MVPL_FETCHECO9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FETCHECO9_LOCKSTATUS_LockStatus_MASK)
75590#define IRIS_MVPL_FETCHECO9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
75591#define IRIS_MVPL_FETCHECO9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
75592/*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
75593 */
75594#define IRIS_MVPL_FETCHECO9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FETCHECO9_LOCKSTATUS_PrivilegeStatus_MASK)
75595#define IRIS_MVPL_FETCHECO9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
75596#define IRIS_MVPL_FETCHECO9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
75597/*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
75598 */
75599#define IRIS_MVPL_FETCHECO9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FETCHECO9_LOCKSTATUS_FreezeStatus_MASK)
75600/*! @} */
75601
75602/*! @name FETCHECO9_STATICCONTROL - Common static control options. */
75603/*! @{ */
75604#define IRIS_MVPL_FETCHECO9_STATICCONTROL_ShdEn_MASK (0x1U)
75605#define IRIS_MVPL_FETCHECO9_STATICCONTROL_ShdEn_SHIFT (0U)
75606/*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed).
75607 */
75608#define IRIS_MVPL_FETCHECO9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FETCHECO9_STATICCONTROL_ShdEn_MASK)
75609#define IRIS_MVPL_FETCHECO9_STATICCONTROL_BaseAddressAutoUpdate_MASK (0xFF0000U)
75610#define IRIS_MVPL_FETCHECO9_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (16U)
75611/*! BaseAddressAutoUpdate - Enable flag for continuous shadow load of BaseAddress field for each
75612 * layer (layer index = bit index). When set to 1 the active BaseAddress configuration is loaded
75613 * from shadow at start of each frame. This update is then executed independently from other RWS
75614 * type fields. ShdEn must be enabled for this mode.
75615 */
75616#define IRIS_MVPL_FETCHECO9_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_FETCHECO9_STATICCONTROL_BaseAddressAutoUpdate_MASK)
75617/*! @} */
75618
75619/*! @name FETCHECO9_BURSTBUFFERMANAGEMENT - AXI interface buffer management register */
75620/*! @{ */
75621#define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK (0xFFU)
75622#define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT (0U)
75623/*! SetNumBuffers - Set this to the number of bursts that should be buffered. SetNumBuffers has to
75624 * be smaller or equal to ManagedBurstBuffers and SetNumBuffers * SetBurstLength has to be smaller
75625 * or equal to ManagedBurstBuffers * BurstLengthForMaxBuffers. Must be a power of 2. The minimum
75626 * allowed settings is 4 except for the fetcheco derivate which has a minimum allowed setting of
75627 * 2.
75628 */
75629#define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetNumBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetNumBuffers_SHIFT)) & IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetNumBuffers_MASK)
75630#define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U)
75631#define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U)
75632/*! SetBurstLength - Set this to the burst length that should be used on the AXI interface.
75633 * SetNumBuffers * SetBurstLength has to be smaller or equal to ManagedBurstBuffers *
75634 * BurstLengthForMaxBuffers and that bursts larger than 16 are not possible on the axi interface. Only a power of
75635 * two may be specified as burst length.
75636 */
75637#define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK)
75638#define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_LineMode_MASK (0x80000000U)
75639#define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_LineMode_SHIFT (31U)
75640/*! LineMode - Fetch buffer cache control.
75641 * 0b0..Mandatory setting for operation in the Display Controller. Works also for Blit Engine with marginal performance impact.
75642 * 0b1..Recommended setting for operation in the Blit Engine.
75643 */
75644#define IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_LineMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_LineMode_SHIFT)) & IRIS_MVPL_FETCHECO9_BURSTBUFFERMANAGEMENT_LineMode_MASK)
75645/*! @} */
75646
75647/*! @name FETCHECO9_BASEADDRESS0 - Source buffer base address of layer 0. */
75648/*! @{ */
75649#define IRIS_MVPL_FETCHECO9_BASEADDRESS0_BaseAddress0_MASK (0xFFFFFFFFU)
75650#define IRIS_MVPL_FETCHECO9_BASEADDRESS0_BaseAddress0_SHIFT (0U)
75651/*! BaseAddress0 - Byte aligned start address of the layer source buffer. For a pixel width of 32
75652 * bits or DECODE operations BaseAddress[1:0] has to be 0 and for a pixel width of 16 bit
75653 * BaseAddress[0] has to be 0.
75654 */
75655#define IRIS_MVPL_FETCHECO9_BASEADDRESS0_BaseAddress0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_BASEADDRESS0_BaseAddress0_SHIFT)) & IRIS_MVPL_FETCHECO9_BASEADDRESS0_BaseAddress0_MASK)
75656/*! @} */
75657
75658/*! @name FETCHECO9_SOURCEBUFFERATTRIBUTES0 - Source buffer attributes for layer 0. */
75659/*! @{ */
75660#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_Stride0_MASK (0xFFFFU)
75661#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT (0U)
75662/*! Stride0 - Source buffer stride of the layer in bytes minus one, used for address generation. For
75663 * a pixel width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel
75664 * width of 16 bit Stride has to be dividable by two and given minus one.
75665 */
75666#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_Stride0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_Stride0_SHIFT)) & IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_Stride0_MASK)
75667#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK (0x3F0000U)
75668#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT (16U)
75669/*! BitsPerPixel0 - Number of bits per pixel in the source buffer. Must be 1, 2, 4, 8, 16, 18, 24 or
75670 * 32. Exception: FetchEco does not support 18 and 24.
75671 */
75672#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_SHIFT)) & IRIS_MVPL_FETCHECO9_SOURCEBUFFERATTRIBUTES0_BitsPerPixel0_MASK)
75673/*! @} */
75674
75675/*! @name FETCHECO9_SOURCEBUFFERDIMENSION0 - Source buffer dimension of layer 0. */
75676/*! @{ */
75677#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineWidth0_MASK (0x3FFFU)
75678#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT (0U)
75679/*! LineWidth0 - Width of the source buffer of the layer in pixels minus one.
75680 */
75681#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineWidth0_SHIFT)) & IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineWidth0_MASK)
75682#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineCount0_MASK (0x3FFF0000U)
75683#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT (16U)
75684/*! LineCount0 - Number of lines of the source buffer of the layer minus one.
75685 */
75686#define IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineCount0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineCount0_SHIFT)) & IRIS_MVPL_FETCHECO9_SOURCEBUFFERDIMENSION0_LineCount0_MASK)
75687/*! @} */
75688
75689/*! @name FETCHECO9_COLORCOMPONENTBITS0 - Size of color components for RGB, YUV and index formats (layer 0). */
75690/*! @{ */
75691#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK (0xFU)
75692#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT (0U)
75693/*! ComponentBitsAlpha0 - Alpha.
75694 */
75695#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsAlpha0_MASK)
75696#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK (0xF00U)
75697#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT (8U)
75698/*! ComponentBitsBlue0 - Blue and V (chroma).
75699 */
75700#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsBlue0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsBlue0_MASK)
75701#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK (0xF0000U)
75702#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT (16U)
75703/*! ComponentBitsGreen0 - Green and U (chroma).
75704 */
75705#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsGreen0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsGreen0_MASK)
75706#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK (0xF000000U)
75707#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT (24U)
75708/*! ComponentBitsRed0 - Red, Y (luma) and palette index.
75709 */
75710#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsRed0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ComponentBitsRed0_MASK)
75711#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ITUFormat0_MASK (0x80000000U)
75712#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ITUFormat0_SHIFT (31U)
75713/*! ITUFormat0 - When ComponentBitsRed/Green/Blue is set to 10 and this mode enabled (value 1), then
75714 * input format is considered 8.2 instead of 10.0 bits (max color is 1020 instead of 1023). This
75715 * is compliant to ITU 656 standard.
75716 */
75717#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ITUFormat0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ITUFormat0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTBITS0_ITUFormat0_MASK)
75718/*! @} */
75719
75720/*! @name FETCHECO9_COLORCOMPONENTSHIFT0 - Bit position of color components for RGB, YUV and index formats (layer 0). */
75721/*! @{ */
75722#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK (0x1FU)
75723#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT (0U)
75724/*! ComponentShiftAlpha0 - Alpha.
75725 */
75726#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftAlpha0_MASK)
75727#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK (0x1F00U)
75728#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT (8U)
75729/*! ComponentShiftBlue0 - Blue and V (chroma).
75730 */
75731#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftBlue0_MASK)
75732#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK (0x1F0000U)
75733#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT (16U)
75734/*! ComponentShiftGreen0 - Green and U (chroma).
75735 */
75736#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftGreen0_MASK)
75737#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK (0x1F000000U)
75738#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT (24U)
75739/*! ComponentShiftRed0 - Red, Y (luma) and palette index.
75740 */
75741#define IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_SHIFT)) & IRIS_MVPL_FETCHECO9_COLORCOMPONENTSHIFT0_ComponentShiftRed0_MASK)
75742/*! @} */
75743
75744/*! @name FETCHECO9_LAYEROFFSET0 - Position of layer 0 within the destination frame. */
75745/*! @{ */
75746#define IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerXOffset0_MASK (0x7FFFU)
75747#define IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerXOffset0_SHIFT (0U)
75748/*! LayerXOffset0 - Horizontal offset (X).
75749 */
75750#define IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerXOffset0_SHIFT)) & IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerXOffset0_MASK)
75751#define IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerYOffset0_MASK (0x7FFF0000U)
75752#define IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerYOffset0_SHIFT (16U)
75753/*! LayerYOffset0 - Vertical offset (Y).
75754 */
75755#define IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerYOffset0_SHIFT)) & IRIS_MVPL_FETCHECO9_LAYEROFFSET0_LayerYOffset0_MASK)
75756/*! @} */
75757
75758/*! @name FETCHECO9_CLIPWINDOWOFFSET0 - Clip window position for layer 0. */
75759/*! @{ */
75760#define IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK (0x7FFFU)
75761#define IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT (0U)
75762/*! ClipWindowXOffset0 - Horizontal position (X).
75763 */
75764#define IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowXOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_SHIFT)) & IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowXOffset0_MASK)
75765#define IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK (0x7FFF0000U)
75766#define IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT (16U)
75767/*! ClipWindowYOffset0 - Vertical position (Y).
75768 */
75769#define IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowYOffset0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_SHIFT)) & IRIS_MVPL_FETCHECO9_CLIPWINDOWOFFSET0_ClipWindowYOffset0_MASK)
75770/*! @} */
75771
75772/*! @name FETCHECO9_CLIPWINDOWDIMENSIONS0 - Clip window size for layer 0. */
75773/*! @{ */
75774#define IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK (0x3FFFU)
75775#define IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT (0U)
75776/*! ClipWindowWidth0 - Width.
75777 */
75778#define IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_SHIFT)) & IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowWidth0_MASK)
75779#define IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK (0x3FFF0000U)
75780#define IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT (16U)
75781/*! ClipWindowHeight0 - Height.
75782 */
75783#define IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_SHIFT)) & IRIS_MVPL_FETCHECO9_CLIPWINDOWDIMENSIONS0_ClipWindowHeight0_MASK)
75784/*! @} */
75785
75786/*! @name FETCHECO9_CONSTANTCOLOR0 - Constant color for layer 0. */
75787/*! @{ */
75788#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantAlpha0_MASK (0xFFU)
75789#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantAlpha0_SHIFT (0U)
75790/*! ConstantAlpha0 - Alpha.
75791 */
75792#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantAlpha0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantAlpha0_SHIFT)) & IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantAlpha0_MASK)
75793#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantBlue0_MASK (0xFF00U)
75794#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantBlue0_SHIFT (8U)
75795/*! ConstantBlue0 - Blue and V (chroma).
75796 */
75797#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantBlue0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantBlue0_SHIFT)) & IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantBlue0_MASK)
75798#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantGreen0_MASK (0xFF0000U)
75799#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantGreen0_SHIFT (16U)
75800/*! ConstantGreen0 - Green and U (chroma).
75801 */
75802#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantGreen0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantGreen0_SHIFT)) & IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantGreen0_MASK)
75803#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantRed0_MASK (0xFF000000U)
75804#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantRed0_SHIFT (24U)
75805/*! ConstantRed0 - Red and Y (luma).
75806 */
75807#define IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantRed0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantRed0_SHIFT)) & IRIS_MVPL_FETCHECO9_CONSTANTCOLOR0_ConstantRed0_MASK)
75808/*! @} */
75809
75810/*! @name FETCHECO9_LAYERPROPERTY0 - Common properties of layer 0. */
75811/*! @{ */
75812#define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_TileMode0_MASK (0x30U)
75813#define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_TileMode0_SHIFT (4U)
75814/*! TileMode0 - Select the tile mode for pixels outside the source buffer. Clip color (0,0,0,0)
75815 * takes precedence if a pixel becomes subject to both tiling and clipping.
75816 * 0b00..Use zero value
75817 * 0b01..Use constant color register value
75818 * 0b10..Use closest pixel from source buffer. Must not be used for DECODE or YUV422 operations or when SourceBufferEnable is 0.
75819 * 0b11..Use closest pixel from source buffer but zero for alpha component. Must not be used for DECODE or YUV422
75820 * operations or when SourceBufferEnable is 0.
75821 */
75822#define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_TileMode0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_TileMode0_SHIFT)) & IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_TileMode0_MASK)
75823#define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_ClipWindowEnable0_MASK (0x40000000U)
75824#define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_ClipWindowEnable0_SHIFT (30U)
75825/*! ClipWindowEnable0 - Value 1 enables the clip window for this layer. Pixels outside the clip
75826 * window get the clip color, pixels inside the source or tiling color.
75827 */
75828#define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_ClipWindowEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_ClipWindowEnable0_SHIFT)) & IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_ClipWindowEnable0_MASK)
75829#define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_SourceBufferEnable0_MASK (0x80000000U)
75830#define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_SourceBufferEnable0_SHIFT (31U)
75831/*! SourceBufferEnable0 - Value 1 enables the source buffer for this layer. When disabled the tiling
75832 * color is used only (TileMode TILE_PAD not allowed).
75833 */
75834#define IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_SourceBufferEnable0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_SourceBufferEnable0_SHIFT)) & IRIS_MVPL_FETCHECO9_LAYERPROPERTY0_SourceBufferEnable0_MASK)
75835/*! @} */
75836
75837/*! @name FETCHECO9_FRAMEDIMENSIONS - Output frame dimension. */
75838/*! @{ */
75839#define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
75840#define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
75841/*! FrameWidth - Frame width minus one.
75842 */
75843#define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameWidth_MASK)
75844#define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
75845#define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
75846/*! FrameHeight - Frame height minus one.
75847 */
75848#define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_FrameHeight_MASK)
75849#define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
75850#define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
75851/*! EmptyFrame - When enabled output frame is empty. FrameWidth/Height settings have no effect then.
75852 * Can be used to load shadows or to generate synchronization signals only (frame/sequence
75853 * complete). If enabled, InputSelect must be set to INACTIVE.
75854 */
75855#define IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMEDIMENSIONS_EmptyFrame_MASK)
75856/*! @} */
75857
75858/*! @name FETCHECO9_FRAMERESAMPLING - Resampling options for output frame. */
75859/*! @{ */
75860#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartX_MASK (0x3FU)
75861#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartX_SHIFT (0U)
75862/*! StartX - X coordinate of first sample point relative to origin.
75863 */
75864#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartX_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartX_MASK)
75865#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartY_MASK (0xFC0U)
75866#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartY_SHIFT (6U)
75867/*! StartY - Y coordinate of first sample point relative to origin.
75868 */
75869#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartY_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_StartY_MASK)
75870#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaX_MASK (0x3F000U)
75871#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaX_SHIFT (12U)
75872/*! DeltaX - Increment of X coordinate for horizontal step in destination frame.
75873 */
75874#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaX(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaX_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaX_MASK)
75875#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaY_MASK (0xFC0000U)
75876#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaY_SHIFT (18U)
75877/*! DeltaY - Increment of Y coordinate for vertical step in destination frame.
75878 */
75879#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaY(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaY_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_DeltaY_MASK)
75880#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_SwapDirection_MASK (0x1000000U)
75881#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_SwapDirection_SHIFT (24U)
75882/*! SwapDirection - Swaps X and Y directions for re-sampling. When enabled (= 1) DeltaY is applied
75883 * for horizontal and DeltaX for vertical step on destination frame.
75884 */
75885#define IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_SwapDirection(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_SwapDirection_SHIFT)) & IRIS_MVPL_FETCHECO9_FRAMERESAMPLING_SwapDirection_MASK)
75886/*! @} */
75887
75888/*! @name FETCHECO9_CONTROL - Shared common control settings for all layers. */
75889/*! @{ */
75890#define IRIS_MVPL_FETCHECO9_CONTROL_RawPixel_MASK (0x80U)
75891#define IRIS_MVPL_FETCHECO9_CONTROL_RawPixel_SHIFT (7U)
75892/*! RawPixel - Raw pixel mode. If enabled (value = 1), the ComponentBits/Shift settings are replaced
75893 * for all layers by fixed values that allow passing the pixel data read from memory unchanged
75894 * to subsequent units (e.g. for reading coordinate layers). Multiply stages and transparent color
75895 * are deactived. Skip and Tile pixels are not affected by this setting.
75896 */
75897#define IRIS_MVPL_FETCHECO9_CONTROL_RawPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONTROL_RawPixel_SHIFT)) & IRIS_MVPL_FETCHECO9_CONTROL_RawPixel_MASK)
75898#define IRIS_MVPL_FETCHECO9_CONTROL_ClipColor_MASK (0x10000U)
75899#define IRIS_MVPL_FETCHECO9_CONTROL_ClipColor_SHIFT (16U)
75900/*! ClipColor - Selects which color to take for pixels that do not lie inside the clip window of any layer.
75901 * 0b0..Null color.
75902 * 0b1..Color of layer number given by ClipLayer (or layer 0 when Fetch unit has one layer only). The color is
75903 * then the layer's source or tiling color.
75904 */
75905#define IRIS_MVPL_FETCHECO9_CONTROL_ClipColor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONTROL_ClipColor_SHIFT)) & IRIS_MVPL_FETCHECO9_CONTROL_ClipColor_MASK)
75906/*! @} */
75907
75908/*! @name FETCHECO9_CONTROLTRIGGER - Shadow load trigger. */
75909/*! @{ */
75910#define IRIS_MVPL_FETCHECO9_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
75911#define IRIS_MVPL_FETCHECO9_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
75912/*! ShdTokGen - Writing a 1 to this will load shadow registers into the active configuration with
75913 * the next start of frame and send a shadow load token to subsequent units.
75914 */
75915#define IRIS_MVPL_FETCHECO9_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_FETCHECO9_CONTROLTRIGGER_ShdTokGen_MASK)
75916/*! @} */
75917
75918/*! @name FETCHECO9_START - Frame start trigger. */
75919/*! @{ */
75920#define IRIS_MVPL_FETCHECO9_START_Start_MASK (0x1U)
75921#define IRIS_MVPL_FETCHECO9_START_Start_SHIFT (0U)
75922/*! Start - Writing a 1 to this field will start generating one frame (for debugging purposes only).
75923 */
75924#define IRIS_MVPL_FETCHECO9_START_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_START_Start_SHIFT)) & IRIS_MVPL_FETCHECO9_START_Start_MASK)
75925/*! @} */
75926
75927/*! @name FETCHECO9_FETCHTYPE - Fetch unit type. */
75928/*! @{ */
75929#define IRIS_MVPL_FETCHECO9_FETCHTYPE_FetchType_MASK (0xFU)
75930#define IRIS_MVPL_FETCHECO9_FETCHTYPE_FetchType_SHIFT (0U)
75931/*! FetchType - This field can be used to determine what kind of fetch unit this is.
75932 * 0b0000..Fetch unit with RL and RLAD decoder.
75933 * 0b0001..Fetch unit with fractional plane (8 layers).
75934 * 0b0010..Fetch unit with arbitrary warping and fractional plane (8 layers).
75935 * 0b0011..Fetch unit with minimum feature set for alpha, chroma and coordinate planes.
75936 * 0b0100..Fetch unit with affine, perspective and arbitrary warping.
75937 * 0b0101..Fetch unit with affine and arbitrary warping.
75938 * 0b0110..Fetch unit with RL and RLAD decoder, reduced feature set.
75939 * 0b0111..Fetch unit with fractional plane (8 layers), reduced feature set.
75940 * 0b1000..Fetch unit with affine and arbitrary warping, reduced feature set.
75941 */
75942#define IRIS_MVPL_FETCHECO9_FETCHTYPE_FetchType(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_FETCHTYPE_FetchType_SHIFT)) & IRIS_MVPL_FETCHECO9_FETCHTYPE_FetchType_MASK)
75943/*! @} */
75944
75945/*! @name FETCHECO9_BURSTBUFFERPROPERTIES - Burst buffer properties. */
75946/*! @{ */
75947#define IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK (0xFFU)
75948#define IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT (0U)
75949/*! ManagedBurstBuffers - Maximum number of burst buffers that can be administrated in the AXI interface.
75950 */
75951#define IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_SHIFT)) & IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_ManagedBurstBuffers_MASK)
75952#define IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK (0x1F00U)
75953#define IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT (8U)
75954/*! BurstLengthForMaxBuffers - Maximum Burst Length that can be used when ManagedBurstBuffers burst buffers are used.
75955 */
75956#define IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_SHIFT)) & IRIS_MVPL_FETCHECO9_BURSTBUFFERPROPERTIES_BurstLengthForMaxBuffers_MASK)
75957/*! @} */
75958
75959/*! @name FETCHECO9_HIDDENSTATUS - Hidden status informations. */
75960/*! @{ */
75961#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBusy_MASK (0x1U)
75962#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBusy_SHIFT (0U)
75963/*! StatusBusy - Fetch unit is busy.
75964 */
75965#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBusy_SHIFT)) & IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBusy_MASK)
75966#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBuffersIdle_MASK (0x10U)
75967#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBuffersIdle_SHIFT (4U)
75968/*! StatusBuffersIdle - AXI interface buffers are idle.
75969 */
75970#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusBuffersIdle_MASK)
75971#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusRequest_MASK (0x20U)
75972#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusRequest_SHIFT (5U)
75973/*! StatusRequest - Fetch unit requesting on the AXI interface, waiting for acknowledge.
75974 */
75975#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusRequest_SHIFT)) & IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusRequest_MASK)
75976#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusComplete_MASK (0x40U)
75977#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusComplete_SHIFT (6U)
75978/*! StatusComplete - Fetch unit completed all requested AXI transfers.
75979 */
75980#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusComplete_SHIFT)) & IRIS_MVPL_FETCHECO9_HIDDENSTATUS_StatusComplete_MASK)
75981#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_ShadowStatus_MASK (0xFF00U)
75982#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_ShadowStatus_SHIFT (8U)
75983/*! ShadowStatus - Shadow load status for all layers (layer index = bit index).
75984 */
75985#define IRIS_MVPL_FETCHECO9_HIDDENSTATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FETCHECO9_HIDDENSTATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_FETCHECO9_HIDDENSTATUS_ShadowStatus_MASK)
75986/*! @} */
75987
75988/*! @name ROP9_LOCKUNLOCK - Register to change the protection status of this address block. */
75989/*! @{ */
75990#define IRIS_MVPL_ROP9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
75991#define IRIS_MVPL_ROP9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
75992/*! LockUnlock - The protection status is changed by writing one of the following key values to this field:
75993 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
75994 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
75995 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
75996 * 0b10110101111000100100011001101110..Disables privilege protection.
75997 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
75998 */
75999#define IRIS_MVPL_ROP9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_ROP9_LOCKUNLOCK_LockUnlock_MASK)
76000/*! @} */
76001
76002/*! @name ROP9_LOCKSTATUS - Protection status of this address block. */
76003/*! @{ */
76004#define IRIS_MVPL_ROP9_LOCKSTATUS_LockStatus_MASK (0x1U)
76005#define IRIS_MVPL_ROP9_LOCKSTATUS_LockStatus_SHIFT (0U)
76006/*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
76007 */
76008#define IRIS_MVPL_ROP9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_ROP9_LOCKSTATUS_LockStatus_MASK)
76009#define IRIS_MVPL_ROP9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
76010#define IRIS_MVPL_ROP9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
76011/*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
76012 */
76013#define IRIS_MVPL_ROP9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_ROP9_LOCKSTATUS_PrivilegeStatus_MASK)
76014#define IRIS_MVPL_ROP9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
76015#define IRIS_MVPL_ROP9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
76016/*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
76017 */
76018#define IRIS_MVPL_ROP9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_ROP9_LOCKSTATUS_FreezeStatus_MASK)
76019/*! @} */
76020
76021/*! @name ROP9_STATICCONTROL - Raster Operation static control register */
76022/*! @{ */
76023#define IRIS_MVPL_ROP9_STATICCONTROL_ShdEn_MASK (0x1U)
76024#define IRIS_MVPL_ROP9_STATICCONTROL_ShdEn_SHIFT (0U)
76025/*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed).
76026 */
76027#define IRIS_MVPL_ROP9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_ROP9_STATICCONTROL_ShdEn_MASK)
76028/*! @} */
76029
76030/*! @name ROP9_CONTROL - Raster Operation control register */
76031/*! @{ */
76032#define IRIS_MVPL_ROP9_CONTROL_Mode_MASK (0x1U)
76033#define IRIS_MVPL_ROP9_CONTROL_Mode_SHIFT (0U)
76034/*! Mode - Operation mode for rop
76035 * 0b0..Neutral mode
76036 * 0b1..Normal Operation
76037 */
76038#define IRIS_MVPL_ROP9_CONTROL_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_Mode_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_Mode_MASK)
76039#define IRIS_MVPL_ROP9_CONTROL_AlphaMode_MASK (0x10U)
76040#define IRIS_MVPL_ROP9_CONTROL_AlphaMode_SHIFT (4U)
76041/*! AlphaMode - Selects the mode for the alpha component channel, has no effect in NEUTRAL mode
76042 * 0b0..Normal raster operation mode, using the operation index
76043 * 0b1..Add mode, adds this component from all enabled inputs, clamps to 1
76044 */
76045#define IRIS_MVPL_ROP9_CONTROL_AlphaMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_AlphaMode_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_AlphaMode_MASK)
76046#define IRIS_MVPL_ROP9_CONTROL_BlueMode_MASK (0x20U)
76047#define IRIS_MVPL_ROP9_CONTROL_BlueMode_SHIFT (5U)
76048/*! BlueMode - Selects the mode for the blue component channel, has no effect in NEUTRAL mode
76049 * 0b0..Normal raster operation mode, using the operation index
76050 * 0b1..Add mode, adds this component from all enabled inputs, clamps to 1
76051 */
76052#define IRIS_MVPL_ROP9_CONTROL_BlueMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_BlueMode_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_BlueMode_MASK)
76053#define IRIS_MVPL_ROP9_CONTROL_GreenMode_MASK (0x40U)
76054#define IRIS_MVPL_ROP9_CONTROL_GreenMode_SHIFT (6U)
76055/*! GreenMode - Selects the mode for the green component channel, has no effect in NEUTRAL mode
76056 * 0b0..Normal raster operation mode, using the operation index
76057 * 0b1..Add mode, adds this component from all enabled inputs, clamps to 1
76058 */
76059#define IRIS_MVPL_ROP9_CONTROL_GreenMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_GreenMode_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_GreenMode_MASK)
76060#define IRIS_MVPL_ROP9_CONTROL_RedMode_MASK (0x80U)
76061#define IRIS_MVPL_ROP9_CONTROL_RedMode_SHIFT (7U)
76062/*! RedMode - Selects the mode for the red component channel, has no effect in NEUTRAL mode
76063 * 0b0..Normal raster operation mode, using the operation index
76064 * 0b1..Add mode, adds this component from all enabled inputs, clamps to 1
76065 */
76066#define IRIS_MVPL_ROP9_CONTROL_RedMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_RedMode_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_RedMode_MASK)
76067#define IRIS_MVPL_ROP9_CONTROL_PrimDiv2_MASK (0x100U)
76068#define IRIS_MVPL_ROP9_CONTROL_PrimDiv2_SHIFT (8U)
76069/*! PrimDiv2 - Selects whether to divide the primary input color components by two or not for ADD
76070 * mode. This field has no effect on a color component in ROP mode.
76071 * 0b0..No change to input
76072 * 0b1..Input is divided by two/shift to the right by one
76073 */
76074#define IRIS_MVPL_ROP9_CONTROL_PrimDiv2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_PrimDiv2_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_PrimDiv2_MASK)
76075#define IRIS_MVPL_ROP9_CONTROL_SecDiv2_MASK (0x200U)
76076#define IRIS_MVPL_ROP9_CONTROL_SecDiv2_SHIFT (9U)
76077/*! SecDiv2 - Selects whether to divide the secondary input color components by two or not for ADD
76078 * mode. This field has no effect on a color component in ROP mode.
76079 * 0b0..No change to input
76080 * 0b1..Input is divided by two/shift to the right by one
76081 */
76082#define IRIS_MVPL_ROP9_CONTROL_SecDiv2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_SecDiv2_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_SecDiv2_MASK)
76083#define IRIS_MVPL_ROP9_CONTROL_TertDiv2_MASK (0x400U)
76084#define IRIS_MVPL_ROP9_CONTROL_TertDiv2_SHIFT (10U)
76085/*! TertDiv2 - Selects whether to divide the tertiary input color components by two or not for ADD
76086 * mode. This field has no effect on a color component in ROP mode.
76087 * 0b0..No change to input
76088 * 0b1..Input is divided by two/shift to the right by one
76089 */
76090#define IRIS_MVPL_ROP9_CONTROL_TertDiv2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_CONTROL_TertDiv2_SHIFT)) & IRIS_MVPL_ROP9_CONTROL_TertDiv2_MASK)
76091/*! @} */
76092
76093/*! @name ROP9_RASTEROPERATIONINDICES - ROP operation indices */
76094/*! @{ */
76095#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexAlpha_MASK (0xFFU)
76096#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexAlpha_SHIFT (0U)
76097/*! OpIndexAlpha - Alpha operation index
76098 */
76099#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexAlpha_SHIFT)) & IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexAlpha_MASK)
76100#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexBlue_MASK (0xFF00U)
76101#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexBlue_SHIFT (8U)
76102/*! OpIndexBlue - Blue operation index
76103 */
76104#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexBlue_SHIFT)) & IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexBlue_MASK)
76105#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexGreen_MASK (0xFF0000U)
76106#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexGreen_SHIFT (16U)
76107/*! OpIndexGreen - Green operation index
76108 */
76109#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexGreen_SHIFT)) & IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexGreen_MASK)
76110#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexRed_MASK (0xFF000000U)
76111#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexRed_SHIFT (24U)
76112/*! OpIndexRed - Red operation index
76113 */
76114#define IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexRed_SHIFT)) & IRIS_MVPL_ROP9_RASTEROPERATIONINDICES_OpIndexRed_MASK)
76115/*! @} */
76116
76117/*! @name ROP9_PRIMCONTROLWORD - Value of last received primary control word */
76118/*! @{ */
76119#define IRIS_MVPL_ROP9_PRIMCONTROLWORD_P_VAL_MASK (0xFFFFFFFFU)
76120#define IRIS_MVPL_ROP9_PRIMCONTROLWORD_P_VAL_SHIFT (0U)
76121/*! P_VAL - Value of last received control word on the primary input. If a 39 bit pixel channel is
76122 * connected, the mapping is as follows: p_val[31:0] = { data[37:22], data[19:12], data[9:2] }.
76123 * For debug purposes only, read when stable only, otherwise read data might be corrupted.
76124 */
76125#define IRIS_MVPL_ROP9_PRIMCONTROLWORD_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_PRIMCONTROLWORD_P_VAL_SHIFT)) & IRIS_MVPL_ROP9_PRIMCONTROLWORD_P_VAL_MASK)
76126/*! @} */
76127
76128/*! @name ROP9_SECCONTROLWORD - Value of last received secondary control word */
76129/*! @{ */
76130#define IRIS_MVPL_ROP9_SECCONTROLWORD_S_VAL_MASK (0xFFFFFFFFU)
76131#define IRIS_MVPL_ROP9_SECCONTROLWORD_S_VAL_SHIFT (0U)
76132/*! S_VAL - Value of last received control word on the secondary input. If a 39 bit pixel channel is
76133 * connected, the mapping is as follows: s_val[31:0] = { data[37:22], data[19:12], data[9:2] }.
76134 * For debug purposes only, read when stable only, otherwise read data might be corrupted.
76135 */
76136#define IRIS_MVPL_ROP9_SECCONTROLWORD_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_SECCONTROLWORD_S_VAL_SHIFT)) & IRIS_MVPL_ROP9_SECCONTROLWORD_S_VAL_MASK)
76137/*! @} */
76138
76139/*! @name ROP9_TERTCONTROLWORD - Value of last received tertiary control word */
76140/*! @{ */
76141#define IRIS_MVPL_ROP9_TERTCONTROLWORD_T_VAL_MASK (0xFFFFFFFFU)
76142#define IRIS_MVPL_ROP9_TERTCONTROLWORD_T_VAL_SHIFT (0U)
76143/*! T_VAL - Value of last received control word on the tertiary input. If a 39 bit pixel channel is
76144 * connected, the mapping is as follows: t_val[31:0] = { data[37:22], data[19:12], data[9:2] }.
76145 * For debug purposes only, read when stable only, otherwise read data might be corrupted.
76146 */
76147#define IRIS_MVPL_ROP9_TERTCONTROLWORD_T_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_ROP9_TERTCONTROLWORD_T_VAL_SHIFT)) & IRIS_MVPL_ROP9_TERTCONTROLWORD_T_VAL_MASK)
76148/*! @} */
76149
76150/*! @name CLUT9_LOCKUNLOCK - Register to change the protection status of this address block. */
76151/*! @{ */
76152#define IRIS_MVPL_CLUT9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
76153#define IRIS_MVPL_CLUT9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
76154/*! LockUnlock - The protection status is changed by writing one of the following key values to this field:
76155 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
76156 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
76157 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
76158 * 0b10110101111000100100011001101110..Disables privilege protection.
76159 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
76160 */
76161#define IRIS_MVPL_CLUT9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_CLUT9_LOCKUNLOCK_LockUnlock_MASK)
76162/*! @} */
76163
76164/*! @name CLUT9_LOCKSTATUS - Protection status of this address block. */
76165/*! @{ */
76166#define IRIS_MVPL_CLUT9_LOCKSTATUS_LockStatus_MASK (0x1U)
76167#define IRIS_MVPL_CLUT9_LOCKSTATUS_LockStatus_SHIFT (0U)
76168/*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
76169 */
76170#define IRIS_MVPL_CLUT9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_CLUT9_LOCKSTATUS_LockStatus_MASK)
76171#define IRIS_MVPL_CLUT9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
76172#define IRIS_MVPL_CLUT9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
76173/*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
76174 */
76175#define IRIS_MVPL_CLUT9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CLUT9_LOCKSTATUS_PrivilegeStatus_MASK)
76176#define IRIS_MVPL_CLUT9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
76177#define IRIS_MVPL_CLUT9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
76178/*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
76179 */
76180#define IRIS_MVPL_CLUT9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_CLUT9_LOCKSTATUS_FreezeStatus_MASK)
76181/*! @} */
76182
76183/*! @name CLUT9_STATICCONTROL - CLUT static control register */
76184/*! @{ */
76185#define IRIS_MVPL_CLUT9_STATICCONTROL_ShdEn_MASK (0x1U)
76186#define IRIS_MVPL_CLUT9_STATICCONTROL_ShdEn_SHIFT (0U)
76187/*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed).
76188 */
76189#define IRIS_MVPL_CLUT9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_CLUT9_STATICCONTROL_ShdEn_MASK)
76190/*! @} */
76191
76192/*! @name CLUT9_UNSHADOWEDCONTROL - CLUT unshadowed control register */
76193/*! @{ */
76194#define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_B_EN_MASK (0x1U)
76195#define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_B_EN_SHIFT (0U)
76196/*! B_EN - Write enable for writing the blue color LUT entry from the host (allows writing a single
76197 * color entry without a read-modify-write cycle)
76198 * 0b0..disable
76199 * 0b1..enable
76200 */
76201#define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_B_EN(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_B_EN_SHIFT)) & IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_B_EN_MASK)
76202#define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_G_EN_MASK (0x2U)
76203#define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_G_EN_SHIFT (1U)
76204/*! G_EN - Write enable for writing the green color LUT entry from the host (allows writing a single
76205 * color entry without a read-modify-write cycle)
76206 * 0b0..disable
76207 * 0b1..enable
76208 */
76209#define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_G_EN(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_G_EN_SHIFT)) & IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_G_EN_MASK)
76210#define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_R_EN_MASK (0x4U)
76211#define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_R_EN_SHIFT (2U)
76212/*! R_EN - Write enable for writing the red color LUT entry from the host (allows writing a single
76213 * color entry without a read-modify-write cycle)
76214 * 0b0..disable
76215 * 0b1..enable
76216 */
76217#define IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_R_EN(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_R_EN_SHIFT)) & IRIS_MVPL_CLUT9_UNSHADOWEDCONTROL_R_EN_MASK)
76218/*! @} */
76219
76220/*! @name CLUT9_CONTROL - CLUT control register */
76221/*! @{ */
76222#define IRIS_MVPL_CLUT9_CONTROL_MODE_MASK (0x3U)
76223#define IRIS_MVPL_CLUT9_CONTROL_MODE_SHIFT (0U)
76224/*! MODE - Operation mode for color lookup table
76225 * 0b00..module in neutral mode, input data is bypassed to the output
76226 * 0b01..module in color lookup mode (LUT holds a 10bit color value for CLut derivate and 8bit color value for CLutL derivate for each input color)
76227 * 0b10..module in 10bit color index table mode (LUT holds a 3x10bit color value for derivate CLut and 3x8bit
76228 * color value for CLUTL derivate, indexed with the red input color)
76229 * 0b11..module in RGBA color index table mode (LUT holds a 3x8bit color value and a 6bit alpha value for CLut
76230 * derivate and 3x6bit color value and 6bit alpha value for CLutL derivate, indexed with the red input color)
76231 */
76232#define IRIS_MVPL_CLUT9_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_CONTROL_MODE_SHIFT)) & IRIS_MVPL_CLUT9_CONTROL_MODE_MASK)
76233#define IRIS_MVPL_CLUT9_CONTROL_COL_8BIT_MASK (0x10U)
76234#define IRIS_MVPL_CLUT9_CONTROL_COL_8BIT_SHIFT (4U)
76235/*! COL_8BIT - Color (red, green, blue) output bitwidth select
76236 * 0b0..color is 10bit output
76237 * 0b1..color is 8bit output (dithering of internal 10bit value)
76238 */
76239#define IRIS_MVPL_CLUT9_CONTROL_COL_8BIT(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_CONTROL_COL_8BIT_SHIFT)) & IRIS_MVPL_CLUT9_CONTROL_COL_8BIT_MASK)
76240#define IRIS_MVPL_CLUT9_CONTROL_AlphaMask_MASK (0x20U)
76241#define IRIS_MVPL_CLUT9_CONTROL_AlphaMask_SHIFT (5U)
76242/*! AlphaMask - Enables the alpha mask mode. This mode disables lookup for all pixels with an alpha
76243 * component smaller or greater/equal than 128. They are bypassed unchanged.
76244 * 0b0..Alpha mask mode disabled
76245 * 0b1..Alpha mask mode enabled
76246 */
76247#define IRIS_MVPL_CLUT9_CONTROL_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_CLUT9_CONTROL_AlphaMask_MASK)
76248#define IRIS_MVPL_CLUT9_CONTROL_AlphaInvert_MASK (0x40U)
76249#define IRIS_MVPL_CLUT9_CONTROL_AlphaInvert_SHIFT (6U)
76250/*! AlphaInvert - Chooses whether to disable lookup for alpha components smaller or greater/equal
76251 * than 128. For this field to have an effect AlphaMask must be set to ENABLE.
76252 * 0b0..Disable computation for alpha smaller than 128
76253 * 0b1..Disable computation for alpha greater than or equal to 128
76254 */
76255#define IRIS_MVPL_CLUT9_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_CLUT9_CONTROL_AlphaInvert_MASK)
76256#define IRIS_MVPL_CLUT9_CONTROL_IDX_BITS_MASK (0xF00U)
76257#define IRIS_MVPL_CLUT9_CONTROL_IDX_BITS_SHIFT (8U)
76258/*! IDX_BITS - Number of msb bits of the red color input used for the LUT index input
76259 */
76260#define IRIS_MVPL_CLUT9_CONTROL_IDX_BITS(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_CONTROL_IDX_BITS_SHIFT)) & IRIS_MVPL_CLUT9_CONTROL_IDX_BITS_MASK)
76261/*! @} */
76262
76263/*! @name CLUT9_STATUS - CLUT status register */
76264/*! @{ */
76265#define IRIS_MVPL_CLUT9_STATUS_WRITE_TIMEOUT_MASK (0x1U)
76266#define IRIS_MVPL_CLUT9_STATUS_WRITE_TIMEOUT_SHIFT (0U)
76267/*! WRITE_TIMEOUT - Timeout detected when writing to the LUT
76268 */
76269#define IRIS_MVPL_CLUT9_STATUS_WRITE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_STATUS_WRITE_TIMEOUT_SHIFT)) & IRIS_MVPL_CLUT9_STATUS_WRITE_TIMEOUT_MASK)
76270#define IRIS_MVPL_CLUT9_STATUS_READ_TIMEOUT_MASK (0x10U)
76271#define IRIS_MVPL_CLUT9_STATUS_READ_TIMEOUT_SHIFT (4U)
76272/*! READ_TIMEOUT - Timeout detected when reading from the LUT
76273 */
76274#define IRIS_MVPL_CLUT9_STATUS_READ_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_STATUS_READ_TIMEOUT_SHIFT)) & IRIS_MVPL_CLUT9_STATUS_READ_TIMEOUT_MASK)
76275/*! @} */
76276
76277/*! @name CLUT9_LASTCONTROLWORD - Value of last received control word, for debugging */
76278/*! @{ */
76279#define IRIS_MVPL_CLUT9_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU)
76280#define IRIS_MVPL_CLUT9_LASTCONTROLWORD_L_VAL_SHIFT (0U)
76281/*! L_VAL - Value of last received control word. For debug purposes only, read when stable only,
76282 * otherwise read data might be corrupted.
76283 */
76284#define IRIS_MVPL_CLUT9_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_CLUT9_LASTCONTROLWORD_L_VAL_MASK)
76285/*! @} */
76286
76287/*! @name CLUT9_LUT - Look Up Table */
76288/*! @{ */
76289#define IRIS_MVPL_CLUT9_LUT_BLUE_MASK (0x3FFU)
76290#define IRIS_MVPL_CLUT9_LUT_BLUE_SHIFT (0U)
76291/*! BLUE - Blue component
76292 */
76293#define IRIS_MVPL_CLUT9_LUT_BLUE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LUT_BLUE_SHIFT)) & IRIS_MVPL_CLUT9_LUT_BLUE_MASK)
76294#define IRIS_MVPL_CLUT9_LUT_GREEN_MASK (0xFFC00U)
76295#define IRIS_MVPL_CLUT9_LUT_GREEN_SHIFT (10U)
76296/*! GREEN - Green component
76297 */
76298#define IRIS_MVPL_CLUT9_LUT_GREEN(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LUT_GREEN_SHIFT)) & IRIS_MVPL_CLUT9_LUT_GREEN_MASK)
76299#define IRIS_MVPL_CLUT9_LUT_RED_MASK (0x3FF00000U)
76300#define IRIS_MVPL_CLUT9_LUT_RED_SHIFT (20U)
76301/*! RED - Red component
76302 */
76303#define IRIS_MVPL_CLUT9_LUT_RED(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CLUT9_LUT_RED_SHIFT)) & IRIS_MVPL_CLUT9_LUT_RED_MASK)
76304/*! @} */
76305
76306/*! @name MATRIX9_LOCKUNLOCK - Register to change the protection status of this address block. */
76307/*! @{ */
76308#define IRIS_MVPL_MATRIX9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
76309#define IRIS_MVPL_MATRIX9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
76310/*! LockUnlock - The protection status is changed by writing one of the following key values to this field:
76311 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
76312 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
76313 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
76314 * 0b10110101111000100100011001101110..Disables privilege protection.
76315 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
76316 */
76317#define IRIS_MVPL_MATRIX9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_MATRIX9_LOCKUNLOCK_LockUnlock_MASK)
76318/*! @} */
76319
76320/*! @name MATRIX9_LOCKSTATUS - Protection status of this address block. */
76321/*! @{ */
76322#define IRIS_MVPL_MATRIX9_LOCKSTATUS_LockStatus_MASK (0x1U)
76323#define IRIS_MVPL_MATRIX9_LOCKSTATUS_LockStatus_SHIFT (0U)
76324/*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
76325 */
76326#define IRIS_MVPL_MATRIX9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_MATRIX9_LOCKSTATUS_LockStatus_MASK)
76327#define IRIS_MVPL_MATRIX9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
76328#define IRIS_MVPL_MATRIX9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
76329/*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
76330 */
76331#define IRIS_MVPL_MATRIX9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_MATRIX9_LOCKSTATUS_PrivilegeStatus_MASK)
76332#define IRIS_MVPL_MATRIX9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
76333#define IRIS_MVPL_MATRIX9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
76334/*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
76335 */
76336#define IRIS_MVPL_MATRIX9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_MATRIX9_LOCKSTATUS_FreezeStatus_MASK)
76337/*! @} */
76338
76339/*! @name MATRIX9_STATICCONTROL - Color Matrix static control register */
76340/*! @{ */
76341#define IRIS_MVPL_MATRIX9_STATICCONTROL_ShdEn_MASK (0x1U)
76342#define IRIS_MVPL_MATRIX9_STATICCONTROL_ShdEn_SHIFT (0U)
76343/*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed).
76344 */
76345#define IRIS_MVPL_MATRIX9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_MATRIX9_STATICCONTROL_ShdEn_MASK)
76346/*! @} */
76347
76348/*! @name MATRIX9_CONTROL - Color Matrix control register */
76349/*! @{ */
76350#define IRIS_MVPL_MATRIX9_CONTROL_MODE_MASK (0x3U)
76351#define IRIS_MVPL_MATRIX9_CONTROL_MODE_SHIFT (0U)
76352/*! MODE - Operation mode for color matrix
76353 * 0b00..Module in neutral mode, input data is bypassed
76354 * 0b01..Module in matrix mode, input data is multiplied with matrix values
76355 * 0b10..Module in alpha pre-multiplication mode, input color is multiplied with input alpha
76356 * 0b11..Reserved, do not use
76357 */
76358#define IRIS_MVPL_MATRIX9_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_CONTROL_MODE_SHIFT)) & IRIS_MVPL_MATRIX9_CONTROL_MODE_MASK)
76359#define IRIS_MVPL_MATRIX9_CONTROL_AlphaMask_MASK (0x10U)
76360#define IRIS_MVPL_MATRIX9_CONTROL_AlphaMask_SHIFT (4U)
76361/*! AlphaMask - Value 1 enables the alpha mask mode. In this mode all pixels with an alpha value
76362 * smaller than 0.5 are by-passed unchanged.
76363 */
76364#define IRIS_MVPL_MATRIX9_CONTROL_AlphaMask(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_CONTROL_AlphaMask_SHIFT)) & IRIS_MVPL_MATRIX9_CONTROL_AlphaMask_MASK)
76365#define IRIS_MVPL_MATRIX9_CONTROL_AlphaInvert_MASK (0x20U)
76366#define IRIS_MVPL_MATRIX9_CONTROL_AlphaInvert_SHIFT (5U)
76367/*! AlphaInvert - Value 1 inverts the effect of the alpha mask mode when enabled (pixels with alpha
76368 * value greater or equal 0.5 are by-passed).
76369 */
76370#define IRIS_MVPL_MATRIX9_CONTROL_AlphaInvert(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_CONTROL_AlphaInvert_SHIFT)) & IRIS_MVPL_MATRIX9_CONTROL_AlphaInvert_MASK)
76371/*! @} */
76372
76373/*! @name MATRIX9_RED0 - Matrix values for calculation of the red output value. */
76374/*! @{ */
76375#define IRIS_MVPL_MATRIX9_RED0_A11_MASK (0x1FFFU)
76376#define IRIS_MVPL_MATRIX9_RED0_A11_SHIFT (0U)
76377/*! A11 - Value for red input.
76378 */
76379#define IRIS_MVPL_MATRIX9_RED0_A11(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_RED0_A11_SHIFT)) & IRIS_MVPL_MATRIX9_RED0_A11_MASK)
76380#define IRIS_MVPL_MATRIX9_RED0_A12_MASK (0x1FFF0000U)
76381#define IRIS_MVPL_MATRIX9_RED0_A12_SHIFT (16U)
76382/*! A12 - Value for green input.
76383 */
76384#define IRIS_MVPL_MATRIX9_RED0_A12(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_RED0_A12_SHIFT)) & IRIS_MVPL_MATRIX9_RED0_A12_MASK)
76385/*! @} */
76386
76387/*! @name MATRIX9_RED1 - Matrix values for calculation of the red output value. */
76388/*! @{ */
76389#define IRIS_MVPL_MATRIX9_RED1_A13_MASK (0x1FFFU)
76390#define IRIS_MVPL_MATRIX9_RED1_A13_SHIFT (0U)
76391/*! A13 - Value for blue input.
76392 */
76393#define IRIS_MVPL_MATRIX9_RED1_A13(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_RED1_A13_SHIFT)) & IRIS_MVPL_MATRIX9_RED1_A13_MASK)
76394#define IRIS_MVPL_MATRIX9_RED1_A14_MASK (0x1FFF0000U)
76395#define IRIS_MVPL_MATRIX9_RED1_A14_SHIFT (16U)
76396/*! A14 - Value for alpha input.
76397 */
76398#define IRIS_MVPL_MATRIX9_RED1_A14(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_RED1_A14_SHIFT)) & IRIS_MVPL_MATRIX9_RED1_A14_MASK)
76399/*! @} */
76400
76401/*! @name MATRIX9_GREEN0 - Matrix values for calculation of the green output value. */
76402/*! @{ */
76403#define IRIS_MVPL_MATRIX9_GREEN0_A21_MASK (0x1FFFU)
76404#define IRIS_MVPL_MATRIX9_GREEN0_A21_SHIFT (0U)
76405/*! A21 - Value for red input.
76406 */
76407#define IRIS_MVPL_MATRIX9_GREEN0_A21(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_GREEN0_A21_SHIFT)) & IRIS_MVPL_MATRIX9_GREEN0_A21_MASK)
76408#define IRIS_MVPL_MATRIX9_GREEN0_A22_MASK (0x1FFF0000U)
76409#define IRIS_MVPL_MATRIX9_GREEN0_A22_SHIFT (16U)
76410/*! A22 - Value for green input.
76411 */
76412#define IRIS_MVPL_MATRIX9_GREEN0_A22(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_GREEN0_A22_SHIFT)) & IRIS_MVPL_MATRIX9_GREEN0_A22_MASK)
76413/*! @} */
76414
76415/*! @name MATRIX9_GREEN1 - Matrix values for calculation of the green output value. */
76416/*! @{ */
76417#define IRIS_MVPL_MATRIX9_GREEN1_A23_MASK (0x1FFFU)
76418#define IRIS_MVPL_MATRIX9_GREEN1_A23_SHIFT (0U)
76419/*! A23 - Value for blue input.
76420 */
76421#define IRIS_MVPL_MATRIX9_GREEN1_A23(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_GREEN1_A23_SHIFT)) & IRIS_MVPL_MATRIX9_GREEN1_A23_MASK)
76422#define IRIS_MVPL_MATRIX9_GREEN1_A24_MASK (0x1FFF0000U)
76423#define IRIS_MVPL_MATRIX9_GREEN1_A24_SHIFT (16U)
76424/*! A24 - Value for alpha input.
76425 */
76426#define IRIS_MVPL_MATRIX9_GREEN1_A24(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_GREEN1_A24_SHIFT)) & IRIS_MVPL_MATRIX9_GREEN1_A24_MASK)
76427/*! @} */
76428
76429/*! @name MATRIX9_BLUE0 - Matrix values for calculation of the blue output value. */
76430/*! @{ */
76431#define IRIS_MVPL_MATRIX9_BLUE0_A31_MASK (0x1FFFU)
76432#define IRIS_MVPL_MATRIX9_BLUE0_A31_SHIFT (0U)
76433/*! A31 - Value for red input.
76434 */
76435#define IRIS_MVPL_MATRIX9_BLUE0_A31(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_BLUE0_A31_SHIFT)) & IRIS_MVPL_MATRIX9_BLUE0_A31_MASK)
76436#define IRIS_MVPL_MATRIX9_BLUE0_A32_MASK (0x1FFF0000U)
76437#define IRIS_MVPL_MATRIX9_BLUE0_A32_SHIFT (16U)
76438/*! A32 - Value for green input.
76439 */
76440#define IRIS_MVPL_MATRIX9_BLUE0_A32(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_BLUE0_A32_SHIFT)) & IRIS_MVPL_MATRIX9_BLUE0_A32_MASK)
76441/*! @} */
76442
76443/*! @name MATRIX9_BLUE1 - Matrix values for calculation of the blue output value. */
76444/*! @{ */
76445#define IRIS_MVPL_MATRIX9_BLUE1_A33_MASK (0x1FFFU)
76446#define IRIS_MVPL_MATRIX9_BLUE1_A33_SHIFT (0U)
76447/*! A33 - Value for blue input.
76448 */
76449#define IRIS_MVPL_MATRIX9_BLUE1_A33(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_BLUE1_A33_SHIFT)) & IRIS_MVPL_MATRIX9_BLUE1_A33_MASK)
76450#define IRIS_MVPL_MATRIX9_BLUE1_A34_MASK (0x1FFF0000U)
76451#define IRIS_MVPL_MATRIX9_BLUE1_A34_SHIFT (16U)
76452/*! A34 - Value for alpha input.
76453 */
76454#define IRIS_MVPL_MATRIX9_BLUE1_A34(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_BLUE1_A34_SHIFT)) & IRIS_MVPL_MATRIX9_BLUE1_A34_MASK)
76455/*! @} */
76456
76457/*! @name MATRIX9_ALPHA0 - Matrix values for calculation of the alpha output value. */
76458/*! @{ */
76459#define IRIS_MVPL_MATRIX9_ALPHA0_A41_MASK (0x1FFFU)
76460#define IRIS_MVPL_MATRIX9_ALPHA0_A41_SHIFT (0U)
76461/*! A41 - Value for red input.
76462 */
76463#define IRIS_MVPL_MATRIX9_ALPHA0_A41(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_ALPHA0_A41_SHIFT)) & IRIS_MVPL_MATRIX9_ALPHA0_A41_MASK)
76464#define IRIS_MVPL_MATRIX9_ALPHA0_A42_MASK (0x1FFF0000U)
76465#define IRIS_MVPL_MATRIX9_ALPHA0_A42_SHIFT (16U)
76466/*! A42 - Value for green input.
76467 */
76468#define IRIS_MVPL_MATRIX9_ALPHA0_A42(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_ALPHA0_A42_SHIFT)) & IRIS_MVPL_MATRIX9_ALPHA0_A42_MASK)
76469/*! @} */
76470
76471/*! @name MATRIX9_ALPHA1 - Matrix values for calculation of the alpha output value. */
76472/*! @{ */
76473#define IRIS_MVPL_MATRIX9_ALPHA1_A43_MASK (0x1FFFU)
76474#define IRIS_MVPL_MATRIX9_ALPHA1_A43_SHIFT (0U)
76475/*! A43 - Value for blue input.
76476 */
76477#define IRIS_MVPL_MATRIX9_ALPHA1_A43(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_ALPHA1_A43_SHIFT)) & IRIS_MVPL_MATRIX9_ALPHA1_A43_MASK)
76478#define IRIS_MVPL_MATRIX9_ALPHA1_A44_MASK (0x1FFF0000U)
76479#define IRIS_MVPL_MATRIX9_ALPHA1_A44_SHIFT (16U)
76480/*! A44 - Value for alpha input.
76481 */
76482#define IRIS_MVPL_MATRIX9_ALPHA1_A44(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_ALPHA1_A44_SHIFT)) & IRIS_MVPL_MATRIX9_ALPHA1_A44_MASK)
76483/*! @} */
76484
76485/*! @name MATRIX9_OFFSETVECTOR0 - Offset vectors for red and green output. */
76486/*! @{ */
76487#define IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C1_MASK (0x1FFFU)
76488#define IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C1_SHIFT (0U)
76489/*! C1 - Red output offset.
76490 */
76491#define IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C1_SHIFT)) & IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C1_MASK)
76492#define IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C2_MASK (0x1FFF0000U)
76493#define IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C2_SHIFT (16U)
76494/*! C2 - Green output offset.
76495 */
76496#define IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C2_SHIFT)) & IRIS_MVPL_MATRIX9_OFFSETVECTOR0_C2_MASK)
76497/*! @} */
76498
76499/*! @name MATRIX9_OFFSETVECTOR1 - Offset vectors for blue and alpha output. */
76500/*! @{ */
76501#define IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C3_MASK (0x1FFFU)
76502#define IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C3_SHIFT (0U)
76503/*! C3 - Blue output offset.
76504 */
76505#define IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C3_SHIFT)) & IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C3_MASK)
76506#define IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C4_MASK (0x1FFF0000U)
76507#define IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C4_SHIFT (16U)
76508/*! C4 - Alpha output offset. Note that the 8-bit alpha input is up-scaled to 10-bit, before the
76509 * matrix and this offset is applied, and down-scaled to 8-bit for output afterwards.
76510 */
76511#define IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C4_SHIFT)) & IRIS_MVPL_MATRIX9_OFFSETVECTOR1_C4_MASK)
76512/*! @} */
76513
76514/*! @name MATRIX9_LASTCONTROLWORD - Value of last received control word, for debugging. */
76515/*! @{ */
76516#define IRIS_MVPL_MATRIX9_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU)
76517#define IRIS_MVPL_MATRIX9_LASTCONTROLWORD_L_VAL_SHIFT (0U)
76518/*! L_VAL - Value of last received control word. For debug purposes only, read when stable only,
76519 * otherwise read data might be corrupted.
76520 */
76521#define IRIS_MVPL_MATRIX9_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_MATRIX9_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_MATRIX9_LASTCONTROLWORD_L_VAL_MASK)
76522/*! @} */
76523
76524/*! @name HSCALER9_LOCKUNLOCK - Register to change the protection status of this address block. */
76525/*! @{ */
76526#define IRIS_MVPL_HSCALER9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
76527#define IRIS_MVPL_HSCALER9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
76528/*! LockUnlock - The protection status is changed by writing one of the following key values to this field:
76529 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
76530 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
76531 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
76532 * 0b10110101111000100100011001101110..Disables privilege protection.
76533 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
76534 */
76535#define IRIS_MVPL_HSCALER9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_HSCALER9_LOCKUNLOCK_LockUnlock_MASK)
76536/*! @} */
76537
76538/*! @name HSCALER9_LOCKSTATUS - Protection status of this address block. */
76539/*! @{ */
76540#define IRIS_MVPL_HSCALER9_LOCKSTATUS_LockStatus_MASK (0x1U)
76541#define IRIS_MVPL_HSCALER9_LOCKSTATUS_LockStatus_SHIFT (0U)
76542/*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
76543 */
76544#define IRIS_MVPL_HSCALER9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_HSCALER9_LOCKSTATUS_LockStatus_MASK)
76545#define IRIS_MVPL_HSCALER9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
76546#define IRIS_MVPL_HSCALER9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
76547/*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
76548 */
76549#define IRIS_MVPL_HSCALER9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_HSCALER9_LOCKSTATUS_PrivilegeStatus_MASK)
76550#define IRIS_MVPL_HSCALER9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
76551#define IRIS_MVPL_HSCALER9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
76552/*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
76553 */
76554#define IRIS_MVPL_HSCALER9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_HSCALER9_LOCKSTATUS_FreezeStatus_MASK)
76555/*! @} */
76556
76557/*! @name HSCALER9_STATICCONTROL - Static control settings that must typically be setup once only. */
76558/*! @{ */
76559#define IRIS_MVPL_HSCALER9_STATICCONTROL_ShdEn_MASK (0x1U)
76560#define IRIS_MVPL_HSCALER9_STATICCONTROL_ShdEn_SHIFT (0U)
76561/*! ShdEn - Shadow enable for RWS type configuration fields (0 = write-through, 1 = shadows enabled)
76562 */
76563#define IRIS_MVPL_HSCALER9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_HSCALER9_STATICCONTROL_ShdEn_MASK)
76564/*! @} */
76565
76566/*! @name HSCALER9_SETUP1 - Phase interpolator setup. */
76567/*! @{ */
76568#define IRIS_MVPL_HSCALER9_SETUP1_scale_factor_MASK (0xFFFFFU)
76569#define IRIS_MVPL_HSCALER9_SETUP1_scale_factor_SHIFT (0U)
76570/*! scale_factor - Scale factor (unsigned fix-point 1.19). Must be greater 0.0 and less or equal
76571 * 1.0. If scale_mode is UPSCALE then the inverse scale factor must be programmed.
76572 */
76573#define IRIS_MVPL_HSCALER9_SETUP1_scale_factor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_SETUP1_scale_factor_SHIFT)) & IRIS_MVPL_HSCALER9_SETUP1_scale_factor_MASK)
76574/*! @} */
76575
76576/*! @name HSCALER9_SETUP2 - Phase interpolator setup. */
76577/*! @{ */
76578#define IRIS_MVPL_HSCALER9_SETUP2_phase_offset_MASK (0x1FFFFFU)
76579#define IRIS_MVPL_HSCALER9_SETUP2_phase_offset_SHIFT (0U)
76580/*! phase_offset - Phase shift (signed fix-point 2.19). Value must be larger or equal to -1.5 and
76581 * smaller than +1.5. Value is relative to input or output pixel size depending on scale_mode is
76582 * UPSCALE or DOWNSCALE. A negative value shifts the image to the right, a positive one to the left.
76583 */
76584#define IRIS_MVPL_HSCALER9_SETUP2_phase_offset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_SETUP2_phase_offset_SHIFT)) & IRIS_MVPL_HSCALER9_SETUP2_phase_offset_MASK)
76585/*! @} */
76586
76587/*! @name HSCALER9_CONTROL - Scaler operation control. */
76588/*! @{ */
76589#define IRIS_MVPL_HSCALER9_CONTROL_mode_MASK (0x1U)
76590#define IRIS_MVPL_HSCALER9_CONTROL_mode_SHIFT (0U)
76591/*! mode - Switches scaler on/off in datapath.
76592 * 0b0..Neutral mode. Pixels by-pass the scaler, all other settings are ignored.
76593 * 0b1..Scaler is active.
76594 */
76595#define IRIS_MVPL_HSCALER9_CONTROL_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_CONTROL_mode_SHIFT)) & IRIS_MVPL_HSCALER9_CONTROL_mode_MASK)
76596#define IRIS_MVPL_HSCALER9_CONTROL_scale_mode_MASK (0x10U)
76597#define IRIS_MVPL_HSCALER9_CONTROL_scale_mode_SHIFT (4U)
76598/*! scale_mode - Scale mode.
76599 * 0b0..Down-scaling (output size less or equal input size).
76600 * 0b1..Up-scaling (output size greater or equal input size)
76601 */
76602#define IRIS_MVPL_HSCALER9_CONTROL_scale_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_CONTROL_scale_mode_SHIFT)) & IRIS_MVPL_HSCALER9_CONTROL_scale_mode_MASK)
76603#define IRIS_MVPL_HSCALER9_CONTROL_filter_mode_MASK (0x100U)
76604#define IRIS_MVPL_HSCALER9_CONTROL_filter_mode_SHIFT (8U)
76605/*! filter_mode - Selects scaling filter algorithm.
76606 * 0b0..Nearest filter (point-sampling)
76607 * 0b1..Box filter (linear)
76608 */
76609#define IRIS_MVPL_HSCALER9_CONTROL_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_CONTROL_filter_mode_SHIFT)) & IRIS_MVPL_HSCALER9_CONTROL_filter_mode_MASK)
76610#define IRIS_MVPL_HSCALER9_CONTROL_output_size_MASK (0x3FFF0000U)
76611#define IRIS_MVPL_HSCALER9_CONTROL_output_size_SHIFT (16U)
76612/*! output_size - Number of output pixel per input line. Value must be one less than actual number of pixels.
76613 */
76614#define IRIS_MVPL_HSCALER9_CONTROL_output_size(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_HSCALER9_CONTROL_output_size_SHIFT)) & IRIS_MVPL_HSCALER9_CONTROL_output_size_MASK)
76615/*! @} */
76616
76617/*! @name VSCALER9_LOCKUNLOCK - Register to change the protection status of this address block. */
76618/*! @{ */
76619#define IRIS_MVPL_VSCALER9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
76620#define IRIS_MVPL_VSCALER9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
76621/*! LockUnlock - The protection status is changed by writing one of the following key values to this field:
76622 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
76623 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
76624 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
76625 * 0b10110101111000100100011001101110..Disables privilege protection.
76626 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
76627 */
76628#define IRIS_MVPL_VSCALER9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_VSCALER9_LOCKUNLOCK_LockUnlock_MASK)
76629/*! @} */
76630
76631/*! @name VSCALER9_LOCKSTATUS - Protection status of this address block. */
76632/*! @{ */
76633#define IRIS_MVPL_VSCALER9_LOCKSTATUS_LockStatus_MASK (0x1U)
76634#define IRIS_MVPL_VSCALER9_LOCKSTATUS_LockStatus_SHIFT (0U)
76635/*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
76636 */
76637#define IRIS_MVPL_VSCALER9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_VSCALER9_LOCKSTATUS_LockStatus_MASK)
76638#define IRIS_MVPL_VSCALER9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
76639#define IRIS_MVPL_VSCALER9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
76640/*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
76641 */
76642#define IRIS_MVPL_VSCALER9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_VSCALER9_LOCKSTATUS_PrivilegeStatus_MASK)
76643#define IRIS_MVPL_VSCALER9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
76644#define IRIS_MVPL_VSCALER9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
76645/*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
76646 */
76647#define IRIS_MVPL_VSCALER9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_VSCALER9_LOCKSTATUS_FreezeStatus_MASK)
76648/*! @} */
76649
76650/*! @name VSCALER9_STATICCONTROL - Static control settings that must typically be setup once only. */
76651/*! @{ */
76652#define IRIS_MVPL_VSCALER9_STATICCONTROL_ShdEn_MASK (0x1U)
76653#define IRIS_MVPL_VSCALER9_STATICCONTROL_ShdEn_SHIFT (0U)
76654/*! ShdEn - Shadow enable for RWS type configuration fields (0 = write-through, 1 = shadows enabled)
76655 */
76656#define IRIS_MVPL_VSCALER9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_VSCALER9_STATICCONTROL_ShdEn_MASK)
76657/*! @} */
76658
76659/*! @name VSCALER9_SETUP1 - Phase interpolator setup. */
76660/*! @{ */
76661#define IRIS_MVPL_VSCALER9_SETUP1_scale_factor_MASK (0xFFFFFU)
76662#define IRIS_MVPL_VSCALER9_SETUP1_scale_factor_SHIFT (0U)
76663/*! scale_factor - Scale factor (unsigned fix-point 1.19). Must be greater 0.0 and less or equal
76664 * 1.0. If scale_mode is UPSCALE then the inverse scale factor must be programmed.
76665 */
76666#define IRIS_MVPL_VSCALER9_SETUP1_scale_factor(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_SETUP1_scale_factor_SHIFT)) & IRIS_MVPL_VSCALER9_SETUP1_scale_factor_MASK)
76667/*! @} */
76668
76669/*! @name VSCALER9_SETUP2 - Phase interpolator setup, selected if input and output field polarity is 0. */
76670/*! @{ */
76671#define IRIS_MVPL_VSCALER9_SETUP2_phase_offset_MASK (0x1FFFFFU)
76672#define IRIS_MVPL_VSCALER9_SETUP2_phase_offset_SHIFT (0U)
76673/*! phase_offset - Phase shift (signed fix-point 2.19). Value must be larger or equal to -1.5 and
76674 * smaller than +1.5. Value is relative to input or output pixel size depending on scale_mode is
76675 * UPSCALE or DOWNSCALE. A negative value shifts the image to the bottom, a positive one to the top.
76676 */
76677#define IRIS_MVPL_VSCALER9_SETUP2_phase_offset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_SETUP2_phase_offset_SHIFT)) & IRIS_MVPL_VSCALER9_SETUP2_phase_offset_MASK)
76678/*! @} */
76679
76680/*! @name VSCALER9_SETUP3 - Phase interpolator setup, selected if input field polarity is 1 and output field polarity is 0. */
76681/*! @{ */
76682#define IRIS_MVPL_VSCALER9_SETUP3_phase_offset1_MASK (0x1FFFFFU)
76683#define IRIS_MVPL_VSCALER9_SETUP3_phase_offset1_SHIFT (0U)
76684/*! phase_offset1 - Phase shift (signed fix-point 2.15). Value must be larger or equal to -1.5 and
76685 * smaller than +1.5. Value is relative to input or output pixel size depending on scale_mode is
76686 * UPSCALE or DOWNSCALE. A negative value shifts the image to the bottom, a positive one to the
76687 * top.
76688 */
76689#define IRIS_MVPL_VSCALER9_SETUP3_phase_offset1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_SETUP3_phase_offset1_SHIFT)) & IRIS_MVPL_VSCALER9_SETUP3_phase_offset1_MASK)
76690/*! @} */
76691
76692/*! @name VSCALER9_SETUP4 - Phase interpolator setup, selected if input field polarity is 0 and output field polarity is 1. */
76693/*! @{ */
76694#define IRIS_MVPL_VSCALER9_SETUP4_phase_offset2_MASK (0x1FFFFFU)
76695#define IRIS_MVPL_VSCALER9_SETUP4_phase_offset2_SHIFT (0U)
76696/*! phase_offset2 - Phase shift (signed fix-point 2.15). Value must be larger or equal to -1.5 and
76697 * smaller than +1.5. Value is relative to input or output pixel size depending on scale_mode is
76698 * UPSCALE or DOWNSCALE. A negative value shifts the image to the bottom, a positive one to the
76699 * top.
76700 */
76701#define IRIS_MVPL_VSCALER9_SETUP4_phase_offset2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_SETUP4_phase_offset2_SHIFT)) & IRIS_MVPL_VSCALER9_SETUP4_phase_offset2_MASK)
76702/*! @} */
76703
76704/*! @name VSCALER9_SETUP5 - Phase interpolator setup, selected if input and output field polarity is 1. */
76705/*! @{ */
76706#define IRIS_MVPL_VSCALER9_SETUP5_phase_offset3_MASK (0x1FFFFFU)
76707#define IRIS_MVPL_VSCALER9_SETUP5_phase_offset3_SHIFT (0U)
76708/*! phase_offset3 - Phase shift (signed fix-point 2.15). Value must be larger or equal to -1.5 and
76709 * smaller than +1.5. Value is relative to input or output pixel size depending on scale_mode is
76710 * UPSCALE or DOWNSCALE. A negative value shifts the image to the bottom, a positive one to the
76711 * top.
76712 */
76713#define IRIS_MVPL_VSCALER9_SETUP5_phase_offset3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_SETUP5_phase_offset3_SHIFT)) & IRIS_MVPL_VSCALER9_SETUP5_phase_offset3_MASK)
76714/*! @} */
76715
76716/*! @name VSCALER9_CONTROL - Scaler operation control. */
76717/*! @{ */
76718#define IRIS_MVPL_VSCALER9_CONTROL_mode_MASK (0x1U)
76719#define IRIS_MVPL_VSCALER9_CONTROL_mode_SHIFT (0U)
76720/*! mode - Operation mode.
76721 * 0b0..Neutral mode. Pixels by-pass the scaler, all other settings are ignored.
76722 * 0b1..Scaler is active.
76723 */
76724#define IRIS_MVPL_VSCALER9_CONTROL_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_CONTROL_mode_SHIFT)) & IRIS_MVPL_VSCALER9_CONTROL_mode_MASK)
76725#define IRIS_MVPL_VSCALER9_CONTROL_scale_mode_MASK (0x10U)
76726#define IRIS_MVPL_VSCALER9_CONTROL_scale_mode_SHIFT (4U)
76727/*! scale_mode - Operation mode.
76728 * 0b0..Down-scaling (output size less or equal input size).
76729 * 0b1..Up-scaling (output size greater or equal input size).
76730 */
76731#define IRIS_MVPL_VSCALER9_CONTROL_scale_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_CONTROL_scale_mode_SHIFT)) & IRIS_MVPL_VSCALER9_CONTROL_scale_mode_MASK)
76732#define IRIS_MVPL_VSCALER9_CONTROL_filter_mode_MASK (0x100U)
76733#define IRIS_MVPL_VSCALER9_CONTROL_filter_mode_SHIFT (8U)
76734/*! filter_mode - Scaling filter.
76735 * 0b0..Nearest filter (point-sampling)
76736 * 0b1..Box filter (linear)
76737 */
76738#define IRIS_MVPL_VSCALER9_CONTROL_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_CONTROL_filter_mode_SHIFT)) & IRIS_MVPL_VSCALER9_CONTROL_filter_mode_MASK)
76739#define IRIS_MVPL_VSCALER9_CONTROL_field_mode_MASK (0x3000U)
76740#define IRIS_MVPL_VSCALER9_CONTROL_field_mode_SHIFT (12U)
76741/*! field_mode - Controls generation of output field polarity. Has no effect in NEUTRAL mode.
76742 * 0b00..Constant 0 indicates frame or top field.
76743 * 0b01..Constant 1 indicates bottom field.
76744 * 0b10..Output field polarity is taken from input field polarity.
76745 * 0b11..Output field polarity toggles, starting with 0 after reset.
76746 */
76747#define IRIS_MVPL_VSCALER9_CONTROL_field_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_CONTROL_field_mode_SHIFT)) & IRIS_MVPL_VSCALER9_CONTROL_field_mode_MASK)
76748#define IRIS_MVPL_VSCALER9_CONTROL_output_size_MASK (0x3FFF0000U)
76749#define IRIS_MVPL_VSCALER9_CONTROL_output_size_SHIFT (16U)
76750/*! output_size - Number of output lines per input frame. Value must be one less than actual number of pixels.
76751 */
76752#define IRIS_MVPL_VSCALER9_CONTROL_output_size(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_VSCALER9_CONTROL_output_size_SHIFT)) & IRIS_MVPL_VSCALER9_CONTROL_output_size_MASK)
76753/*! @} */
76754
76755/*! @name FILTER9_LOCKUNLOCK - Register to change the protection status of this address block. */
76756/*! @{ */
76757#define IRIS_MVPL_FILTER9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
76758#define IRIS_MVPL_FILTER9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
76759/*! LockUnlock - The protection status is changed by writing one of the following key values to this field:
76760 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
76761 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
76762 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
76763 * 0b10110101111000100100011001101110..Disables privilege protection.
76764 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
76765 */
76766#define IRIS_MVPL_FILTER9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_FILTER9_LOCKUNLOCK_LockUnlock_MASK)
76767/*! @} */
76768
76769/*! @name FILTER9_LOCKSTATUS - Protection status of this address block. */
76770/*! @{ */
76771#define IRIS_MVPL_FILTER9_LOCKSTATUS_LockStatus_MASK (0x1U)
76772#define IRIS_MVPL_FILTER9_LOCKSTATUS_LockStatus_SHIFT (0U)
76773/*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
76774 */
76775#define IRIS_MVPL_FILTER9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_FILTER9_LOCKSTATUS_LockStatus_MASK)
76776#define IRIS_MVPL_FILTER9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
76777#define IRIS_MVPL_FILTER9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
76778/*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
76779 */
76780#define IRIS_MVPL_FILTER9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_FILTER9_LOCKSTATUS_PrivilegeStatus_MASK)
76781#define IRIS_MVPL_FILTER9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
76782#define IRIS_MVPL_FILTER9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
76783/*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
76784 */
76785#define IRIS_MVPL_FILTER9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_FILTER9_LOCKSTATUS_FreezeStatus_MASK)
76786/*! @} */
76787
76788/*! @name FILTER9_STATICCONTROL - Static control settings that must typically be setup once only. */
76789/*! @{ */
76790#define IRIS_MVPL_FILTER9_STATICCONTROL_ShdEn_MASK (0x1U)
76791#define IRIS_MVPL_FILTER9_STATICCONTROL_ShdEn_SHIFT (0U)
76792/*! ShdEn - If ShdEn==1 shadow registers are loaded when indicated by hardware signal ( a command
76793 * signal in the data stream at frame start ). If ShdEn==0 shadow registers are loaded each frame
76794 * start.
76795 */
76796#define IRIS_MVPL_FILTER9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_FILTER9_STATICCONTROL_ShdEn_MASK)
76797/*! @} */
76798
76799/*! @name FILTER9_CONTROL - Filter operation main control. */
76800/*! @{ */
76801#define IRIS_MVPL_FILTER9_CONTROL_mode_MASK (0x1U)
76802#define IRIS_MVPL_FILTER9_CONTROL_mode_SHIFT (0U)
76803/*! mode - The filter can be by-passed or switched by mode field.
76804 * 0b0..Neutral mode. Pixels by-pass the filter, all other settings are ignored.
76805 * 0b1..Filter is active.
76806 */
76807#define IRIS_MVPL_FILTER9_CONTROL_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_CONTROL_mode_SHIFT)) & IRIS_MVPL_FILTER9_CONTROL_mode_MASK)
76808#define IRIS_MVPL_FILTER9_CONTROL_tile_mode_MASK (0x30U)
76809#define IRIS_MVPL_FILTER9_CONTROL_tile_mode_SHIFT (4U)
76810/*! tile_mode - Selects how filter samples outside the input frame are treated.
76811 * 0b00..Samples outside the frame are padded with the last valid border pixels.
76812 * 0b01..Samples outside the frame are treated as zero pixel value.
76813 * 0b10..Applies tile mode PAD to RGB channels and tile mode ZERO to alpha channel.
76814 */
76815#define IRIS_MVPL_FILTER9_CONTROL_tile_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_CONTROL_tile_mode_SHIFT)) & IRIS_MVPL_FILTER9_CONTROL_tile_mode_MASK)
76816#define IRIS_MVPL_FILTER9_CONTROL_filter_mode_MASK (0xFFFF00U)
76817#define IRIS_MVPL_FILTER9_CONTROL_filter_mode_SHIFT (8U)
76818/*! filter_mode - Filter mode of operation is controlled by filter_mode field.
76819 * 0b0000000001010101..FIR filter 5x5 window.
76820 */
76821#define IRIS_MVPL_FILTER9_CONTROL_filter_mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_CONTROL_filter_mode_SHIFT)) & IRIS_MVPL_FILTER9_CONTROL_filter_mode_MASK)
76822#define IRIS_MVPL_FILTER9_CONTROL_buffer_format_MASK (0x30000000U)
76823#define IRIS_MVPL_FILTER9_CONTROL_buffer_format_SHIFT (28U)
76824/*! buffer_format - Selects the pixel storage format for the line buffers.
76825 * 0b00..RGB888 format. Alpha is not filtered but set to constant value 255.
76826 * 0b01..RGBA5658 format. Alpha is filtered.
76827 * 0b10..RGBA8888 format. Alpha is filtered. The filter window is limited to 5x4.
76828 * 0b11..RGBA10.10.10.8 format. Alpha is filtered. The filter window is limited to 5x3.
76829 */
76830#define IRIS_MVPL_FILTER9_CONTROL_buffer_format(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_CONTROL_buffer_format_SHIFT)) & IRIS_MVPL_FILTER9_CONTROL_buffer_format_MASK)
76831/*! @} */
76832
76833/*! @name FILTER9_FIR_CONTROL - FIR filter operation control. */
76834/*! @{ */
76835#define IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_component_select_MASK (0xFU)
76836#define IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_component_select_SHIFT (0U)
76837/*! FIR_component_select - Bit 3 enables R or Y component for filtering, bit 2 G or U, bit 1 B or V
76838 * and bit 0 alpha component. Disabled components are by-passed.
76839 */
76840#define IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_component_select(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_component_select_SHIFT)) & IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_component_select_MASK)
76841#define IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_exponent_MASK (0xF00U)
76842#define IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_exponent_SHIFT (8U)
76843/*! FIR_exponent - FIR product sum is divided by 2**FIR_exponent and rounded.
76844 */
76845#define IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_exponent(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_exponent_SHIFT)) & IRIS_MVPL_FILTER9_FIR_CONTROL_FIR_exponent_MASK)
76846/*! @} */
76847
76848/*! @name FILTER9_COEFFICIENTS0 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */
76849/*! @{ */
76850#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff0_0_MASK (0xFFU)
76851#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff0_0_SHIFT (0U)
76852/*! coeff0_0 - Coefficient[0][0].
76853 */
76854#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff0_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff0_0_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff0_0_MASK)
76855#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff1_0_MASK (0xFF00U)
76856#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff1_0_SHIFT (8U)
76857/*! coeff1_0 - Coefficient[1][0].
76858 */
76859#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff1_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff1_0_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff1_0_MASK)
76860#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff2_0_MASK (0xFF0000U)
76861#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff2_0_SHIFT (16U)
76862/*! coeff2_0 - Coefficient[2][0].
76863 */
76864#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff2_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff2_0_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff2_0_MASK)
76865#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff3_0_MASK (0xFF000000U)
76866#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff3_0_SHIFT (24U)
76867/*! coeff3_0 - Coefficient[3][0].
76868 */
76869#define IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff3_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff3_0_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS0_coeff3_0_MASK)
76870/*! @} */
76871
76872/*! @name FILTER9_COEFFICIENTS1 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */
76873/*! @{ */
76874#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff4_0_MASK (0xFFU)
76875#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff4_0_SHIFT (0U)
76876/*! coeff4_0 - Coefficient[4][0].
76877 */
76878#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff4_0(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff4_0_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff4_0_MASK)
76879#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff0_1_MASK (0xFF00U)
76880#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff0_1_SHIFT (8U)
76881/*! coeff0_1 - Coefficient[0][1].
76882 */
76883#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff0_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff0_1_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff0_1_MASK)
76884#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff1_1_MASK (0xFF0000U)
76885#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff1_1_SHIFT (16U)
76886/*! coeff1_1 - Coefficient[1][1].
76887 */
76888#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff1_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff1_1_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff1_1_MASK)
76889#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff2_1_MASK (0xFF000000U)
76890#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff2_1_SHIFT (24U)
76891/*! coeff2_1 - Coefficient[2][1].
76892 */
76893#define IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff2_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff2_1_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS1_coeff2_1_MASK)
76894/*! @} */
76895
76896/*! @name FILTER9_COEFFICIENTS2 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */
76897/*! @{ */
76898#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff3_1_MASK (0xFFU)
76899#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff3_1_SHIFT (0U)
76900/*! coeff3_1 - Coefficient[3][1].
76901 */
76902#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff3_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff3_1_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff3_1_MASK)
76903#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff4_1_MASK (0xFF00U)
76904#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff4_1_SHIFT (8U)
76905/*! coeff4_1 - Coefficient[4][1].
76906 */
76907#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff4_1(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff4_1_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff4_1_MASK)
76908#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff0_2_MASK (0xFF0000U)
76909#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff0_2_SHIFT (16U)
76910/*! coeff0_2 - Coefficient[0][2].
76911 */
76912#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff0_2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff0_2_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff0_2_MASK)
76913#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff1_2_MASK (0xFF000000U)
76914#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff1_2_SHIFT (24U)
76915/*! coeff1_2 - Coefficient[1][2].
76916 */
76917#define IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff1_2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff1_2_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS2_coeff1_2_MASK)
76918/*! @} */
76919
76920/*! @name FILTER9_COEFFICIENTS3 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */
76921/*! @{ */
76922#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff2_2_MASK (0xFFU)
76923#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff2_2_SHIFT (0U)
76924/*! coeff2_2 - Coefficient[2][2].
76925 */
76926#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff2_2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff2_2_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff2_2_MASK)
76927#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff3_2_MASK (0xFF00U)
76928#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff3_2_SHIFT (8U)
76929/*! coeff3_2 - Coefficient[3][2].
76930 */
76931#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff3_2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff3_2_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff3_2_MASK)
76932#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff4_2_MASK (0xFF0000U)
76933#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff4_2_SHIFT (16U)
76934/*! coeff4_2 - Coefficient[4][2].
76935 */
76936#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff4_2(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff4_2_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff4_2_MASK)
76937#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff0_3_MASK (0xFF000000U)
76938#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff0_3_SHIFT (24U)
76939/*! coeff0_3 - Coefficient[0][3].
76940 */
76941#define IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff0_3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff0_3_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS3_coeff0_3_MASK)
76942/*! @} */
76943
76944/*! @name FILTER9_COEFFICIENTS4 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */
76945/*! @{ */
76946#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff1_3_MASK (0xFFU)
76947#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff1_3_SHIFT (0U)
76948/*! coeff1_3 - Coefficient[1][3].
76949 */
76950#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff1_3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff1_3_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff1_3_MASK)
76951#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff2_3_MASK (0xFF00U)
76952#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff2_3_SHIFT (8U)
76953/*! coeff2_3 - Coefficient[2][3].
76954 */
76955#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff2_3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff2_3_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff2_3_MASK)
76956#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff3_3_MASK (0xFF0000U)
76957#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff3_3_SHIFT (16U)
76958/*! coeff3_3 - Coefficient[3][3].
76959 */
76960#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff3_3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff3_3_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff3_3_MASK)
76961#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff4_3_MASK (0xFF000000U)
76962#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff4_3_SHIFT (24U)
76963/*! coeff4_3 - Coefficient[4][3].
76964 */
76965#define IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff4_3(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff4_3_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS4_coeff4_3_MASK)
76966/*! @} */
76967
76968/*! @name FILTER9_COEFFICIENTS5 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */
76969/*! @{ */
76970#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff0_4_MASK (0xFFU)
76971#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff0_4_SHIFT (0U)
76972/*! coeff0_4 - Coefficient[0][4].
76973 */
76974#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff0_4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff0_4_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff0_4_MASK)
76975#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff1_4_MASK (0xFF00U)
76976#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff1_4_SHIFT (8U)
76977/*! coeff1_4 - Coefficient[1][4].
76978 */
76979#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff1_4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff1_4_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff1_4_MASK)
76980#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff2_4_MASK (0xFF0000U)
76981#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff2_4_SHIFT (16U)
76982/*! coeff2_4 - Coefficient[2][4].
76983 */
76984#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff2_4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff2_4_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff2_4_MASK)
76985#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff3_4_MASK (0xFF000000U)
76986#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff3_4_SHIFT (24U)
76987/*! coeff3_4 - Coefficient[3][4].
76988 */
76989#define IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff3_4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff3_4_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS5_coeff3_4_MASK)
76990/*! @} */
76991
76992/*! @name FILTER9_COEFFICIENTS6 - FIR coefficients[column][row] for 5x5 window for filter_mode FIR. */
76993/*! @{ */
76994#define IRIS_MVPL_FILTER9_COEFFICIENTS6_coeff4_4_MASK (0xFFU)
76995#define IRIS_MVPL_FILTER9_COEFFICIENTS6_coeff4_4_SHIFT (0U)
76996/*! coeff4_4 - Coefficient[4][4].
76997 */
76998#define IRIS_MVPL_FILTER9_COEFFICIENTS6_coeff4_4(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_FILTER9_COEFFICIENTS6_coeff4_4_SHIFT)) & IRIS_MVPL_FILTER9_COEFFICIENTS6_coeff4_4_MASK)
76999/*! @} */
77000
77001/*! @name BLITBLEND9_LOCKUNLOCK - Register to change the protection status of this address block. */
77002/*! @{ */
77003#define IRIS_MVPL_BLITBLEND9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
77004#define IRIS_MVPL_BLITBLEND9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
77005/*! LockUnlock - The protection status is changed by writing one of the following key values to this field:
77006 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
77007 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
77008 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
77009 * 0b10110101111000100100011001101110..Disables privilege protection.
77010 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
77011 */
77012#define IRIS_MVPL_BLITBLEND9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_BLITBLEND9_LOCKUNLOCK_LockUnlock_MASK)
77013/*! @} */
77014
77015/*! @name BLITBLEND9_LOCKSTATUS - Protection status of this address block. */
77016/*! @{ */
77017#define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_LockStatus_MASK (0x1U)
77018#define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_LockStatus_SHIFT (0U)
77019/*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
77020 */
77021#define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_BLITBLEND9_LOCKSTATUS_LockStatus_MASK)
77022#define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
77023#define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
77024/*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
77025 */
77026#define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_BLITBLEND9_LOCKSTATUS_PrivilegeStatus_MASK)
77027#define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
77028#define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
77029/*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
77030 */
77031#define IRIS_MVPL_BLITBLEND9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_BLITBLEND9_LOCKSTATUS_FreezeStatus_MASK)
77032/*! @} */
77033
77034/*! @name BLITBLEND9_STATICCONTROL - BlitBlend static control register */
77035/*! @{ */
77036#define IRIS_MVPL_BLITBLEND9_STATICCONTROL_ShdEn_MASK (0x1U)
77037#define IRIS_MVPL_BLITBLEND9_STATICCONTROL_ShdEn_SHIFT (0U)
77038/*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed).
77039 */
77040#define IRIS_MVPL_BLITBLEND9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_BLITBLEND9_STATICCONTROL_ShdEn_MASK)
77041/*! @} */
77042
77043/*! @name BLITBLEND9_CONTROL - BlitBlend control register */
77044/*! @{ */
77045#define IRIS_MVPL_BLITBLEND9_CONTROL_Mode_MASK (0x1U)
77046#define IRIS_MVPL_BLITBLEND9_CONTROL_Mode_SHIFT (0U)
77047/*! Mode - Operation mode for BlitBlend
77048 * 0b0..Neutral mode, only route pixels and commands from primary input to output
77049 * 0b1..Normal Operation
77050 */
77051#define IRIS_MVPL_BLITBLEND9_CONTROL_Mode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_CONTROL_Mode_SHIFT)) & IRIS_MVPL_BLITBLEND9_CONTROL_Mode_MASK)
77052/*! @} */
77053
77054/*! @name BLITBLEND9_NEUTRALBORDER - Neutral border setup register */
77055/*! @{ */
77056#define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderMode_MASK (0x1U)
77057#define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderMode_SHIFT (0U)
77058/*! NeutralBorderMode - Chooses whether to bypass primary or secondary input pixels
77059 * 0b0..Bypasses primary pixel
77060 * 0b1..Bypasses secondary pixel
77061 */
77062#define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderMode_SHIFT)) & IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderMode_MASK)
77063#define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderLeft_MASK (0x700U)
77064#define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderLeft_SHIFT (8U)
77065/*! NeutralBorderLeft - Number of neutral left border pixels
77066 */
77067#define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderLeft(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderLeft_SHIFT)) & IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderLeft_MASK)
77068#define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderRight_MASK (0x7000U)
77069#define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderRight_SHIFT (12U)
77070/*! NeutralBorderRight - Number of neutral right border pixels
77071 */
77072#define IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderRight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderRight_SHIFT)) & IRIS_MVPL_BLITBLEND9_NEUTRALBORDER_NeutralBorderRight_MASK)
77073/*! @} */
77074
77075/*! @name BLITBLEND9_CONSTANTCOLOR - Constant color register */
77076/*! @{ */
77077#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantAlpha_MASK (0xFFU)
77078#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantAlpha_SHIFT (0U)
77079/*! ConstantAlpha - Alpha.
77080 */
77081#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantAlpha_SHIFT)) & IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantAlpha_MASK)
77082#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantBlue_MASK (0xFF00U)
77083#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantBlue_SHIFT (8U)
77084/*! ConstantBlue - Blue and V (chroma).
77085 */
77086#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantBlue_SHIFT)) & IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantBlue_MASK)
77087#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantGreen_MASK (0xFF0000U)
77088#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantGreen_SHIFT (16U)
77089/*! ConstantGreen - Green and U (chroma).
77090 */
77091#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantGreen_SHIFT)) & IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantGreen_MASK)
77092#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantRed_MASK (0xFF000000U)
77093#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantRed_SHIFT (24U)
77094/*! ConstantRed - Red and Y (luma).
77095 */
77096#define IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantRed_SHIFT)) & IRIS_MVPL_BLITBLEND9_CONSTANTCOLOR_ConstantRed_MASK)
77097/*! @} */
77098
77099/*! @name BLITBLEND9_COLORREDBLENDFUNCTION - Open GL RGB blending factors */
77100/*! @{ */
77101#define IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedSrc_MASK (0xFFFFU)
77102#define IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedSrc_SHIFT (0U)
77103/*! BlendFuncColorRedSrc - Red component source blend function
77104 * 0b0000000000000000..
77105 * 0b0000000000000001..
77106 * 0b0000001100000000..
77107 * 0b0000001100000001..
77108 * 0b0000001100000010..
77109 * 0b0000001100000011..
77110 * 0b0000001100000100..
77111 * 0b0000001100000101..
77112 * 0b0000001100000110..
77113 * 0b0000001100000111..
77114 * 0b0000001100001000..
77115 * 0b1000000000000001..
77116 * 0b1000000000000010..
77117 * 0b1000000000000011..
77118 * 0b1000000000000100..
77119 */
77120#define IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedSrc(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedSrc_SHIFT)) & IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedSrc_MASK)
77121#define IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedDst_MASK (0xFFFF0000U)
77122#define IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedDst_SHIFT (16U)
77123/*! BlendFuncColorRedDst - Red component destination blend function
77124 * 0b0000000000000000..
77125 * 0b0000000000000001..
77126 * 0b0000001100000000..
77127 * 0b0000001100000001..
77128 * 0b0000001100000010..
77129 * 0b0000001100000011..
77130 * 0b0000001100000100..
77131 * 0b0000001100000101..
77132 * 0b0000001100000110..
77133 * 0b0000001100000111..
77134 * 0b0000001100001000..
77135 * 0b1000000000000001..
77136 * 0b1000000000000010..
77137 * 0b1000000000000011..
77138 * 0b1000000000000100..
77139 */
77140#define IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedDst(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedDst_SHIFT)) & IRIS_MVPL_BLITBLEND9_COLORREDBLENDFUNCTION_BlendFuncColorRedDst_MASK)
77141/*! @} */
77142
77143/*! @name BLITBLEND9_COLORGREENBLENDFUNCTION - Open GL RGB blending factors */
77144/*! @{ */
77145#define IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenSrc_MASK (0xFFFFU)
77146#define IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenSrc_SHIFT (0U)
77147/*! BlendFuncColorGreenSrc - Green component source blend function
77148 * 0b0000000000000000..
77149 * 0b0000000000000001..
77150 * 0b0000001100000000..
77151 * 0b0000001100000001..
77152 * 0b0000001100000010..
77153 * 0b0000001100000011..
77154 * 0b0000001100000100..
77155 * 0b0000001100000101..
77156 * 0b0000001100000110..
77157 * 0b0000001100000111..
77158 * 0b0000001100001000..
77159 * 0b1000000000000001..
77160 * 0b1000000000000010..
77161 * 0b1000000000000011..
77162 * 0b1000000000000100..
77163 */
77164#define IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenSrc(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenSrc_SHIFT)) & IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenSrc_MASK)
77165#define IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenDst_MASK (0xFFFF0000U)
77166#define IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenDst_SHIFT (16U)
77167/*! BlendFuncColorGreenDst - Green component destination blend function
77168 * 0b0000000000000000..
77169 * 0b0000000000000001..
77170 * 0b0000001100000000..
77171 * 0b0000001100000001..
77172 * 0b0000001100000010..
77173 * 0b0000001100000011..
77174 * 0b0000001100000100..
77175 * 0b0000001100000101..
77176 * 0b0000001100000110..
77177 * 0b0000001100000111..
77178 * 0b0000001100001000..
77179 * 0b1000000000000001..
77180 * 0b1000000000000010..
77181 * 0b1000000000000011..
77182 * 0b1000000000000100..
77183 */
77184#define IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenDst(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenDst_SHIFT)) & IRIS_MVPL_BLITBLEND9_COLORGREENBLENDFUNCTION_BlendFuncColorGreenDst_MASK)
77185/*! @} */
77186
77187/*! @name BLITBLEND9_COLORBLUEBLENDFUNCTION - Open GL RGB blending factors */
77188/*! @{ */
77189#define IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueSrc_MASK (0xFFFFU)
77190#define IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueSrc_SHIFT (0U)
77191/*! BlendFuncColorBlueSrc - Blue component source blend function
77192 * 0b0000000000000000..
77193 * 0b0000000000000001..
77194 * 0b0000001100000000..
77195 * 0b0000001100000001..
77196 * 0b0000001100000010..
77197 * 0b0000001100000011..
77198 * 0b0000001100000100..
77199 * 0b0000001100000101..
77200 * 0b0000001100000110..
77201 * 0b0000001100000111..
77202 * 0b0000001100001000..
77203 * 0b1000000000000001..
77204 * 0b1000000000000010..
77205 * 0b1000000000000011..
77206 * 0b1000000000000100..
77207 */
77208#define IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueSrc(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueSrc_SHIFT)) & IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueSrc_MASK)
77209#define IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueDst_MASK (0xFFFF0000U)
77210#define IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueDst_SHIFT (16U)
77211/*! BlendFuncColorBlueDst - Blue component destination blend function
77212 * 0b0000000000000000..
77213 * 0b0000000000000001..
77214 * 0b0000001100000000..
77215 * 0b0000001100000001..
77216 * 0b0000001100000010..
77217 * 0b0000001100000011..
77218 * 0b0000001100000100..
77219 * 0b0000001100000101..
77220 * 0b0000001100000110..
77221 * 0b0000001100000111..
77222 * 0b0000001100001000..
77223 * 0b1000000000000001..
77224 * 0b1000000000000010..
77225 * 0b1000000000000011..
77226 * 0b1000000000000100..
77227 */
77228#define IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueDst(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueDst_SHIFT)) & IRIS_MVPL_BLITBLEND9_COLORBLUEBLENDFUNCTION_BlendFuncColorBlueDst_MASK)
77229/*! @} */
77230
77231/*! @name BLITBLEND9_ALPHABLENDFUNCTION - Open GL alpha blending factors */
77232/*! @{ */
77233#define IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaSrc_MASK (0xFFFFU)
77234#define IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaSrc_SHIFT (0U)
77235/*! BlendFuncAlphaSrc - Alpha component source blend function
77236 * 0b0000000000000000..
77237 * 0b0000000000000001..
77238 * 0b0000001100000000..
77239 * 0b0000001100000001..
77240 * 0b0000001100000010..
77241 * 0b0000001100000011..
77242 * 0b0000001100000100..
77243 * 0b0000001100000101..
77244 * 0b0000001100000110..
77245 * 0b0000001100000111..
77246 * 0b0000001100001000..
77247 * 0b1000000000000001..
77248 * 0b1000000000000010..
77249 * 0b1000000000000011..
77250 * 0b1000000000000100..
77251 */
77252#define IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaSrc(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaSrc_SHIFT)) & IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaSrc_MASK)
77253#define IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaDst_MASK (0xFFFF0000U)
77254#define IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaDst_SHIFT (16U)
77255/*! BlendFuncAlphaDst - Alpha component destination blend function
77256 * 0b0000000000000000..
77257 * 0b0000000000000001..
77258 * 0b0000001100000000..
77259 * 0b0000001100000001..
77260 * 0b0000001100000010..
77261 * 0b0000001100000011..
77262 * 0b0000001100000100..
77263 * 0b0000001100000101..
77264 * 0b0000001100000110..
77265 * 0b0000001100000111..
77266 * 0b0000001100001000..
77267 * 0b1000000000000001..
77268 * 0b1000000000000010..
77269 * 0b1000000000000011..
77270 * 0b1000000000000100..
77271 */
77272#define IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaDst(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaDst_SHIFT)) & IRIS_MVPL_BLITBLEND9_ALPHABLENDFUNCTION_BlendFuncAlphaDst_MASK)
77273/*! @} */
77274
77275/*! @name BLITBLEND9_BLENDMODE1 - Open GL and Open VG blending modes for colors red and green */
77276/*! @{ */
77277#define IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorRed_MASK (0xFFFFU)
77278#define IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorRed_SHIFT (0U)
77279/*! BlendModeColorRed - Red component blend mode
77280 * 0b1000000000000110..
77281 * 0b1000000000000111..
77282 * 0b1000000000001000..
77283 * 0b1000000000001010..
77284 * 0b1000000000001011..
77285 * 0b0010000000000000..
77286 * 0b0010000000000001..
77287 * 0b0010000000000010..
77288 * 0b0010000000000011..
77289 * 0b0010000000000100..
77290 * 0b0010000000000101..
77291 * 0b0010000000000110..
77292 * 0b0010000000000111..
77293 * 0b0010000000001000..
77294 * 0b0010000000001001..
77295 */
77296#define IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorRed_SHIFT)) & IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorRed_MASK)
77297#define IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorGreen_MASK (0xFFFF0000U)
77298#define IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorGreen_SHIFT (16U)
77299/*! BlendModeColorGreen - Green component blend mode
77300 * 0b1000000000000110..
77301 * 0b1000000000000111..
77302 * 0b1000000000001000..
77303 * 0b1000000000001010..
77304 * 0b1000000000001011..
77305 * 0b0010000000000000..
77306 * 0b0010000000000001..
77307 * 0b0010000000000010..
77308 * 0b0010000000000011..
77309 * 0b0010000000000100..
77310 * 0b0010000000000101..
77311 * 0b0010000000000110..
77312 * 0b0010000000000111..
77313 * 0b0010000000001000..
77314 * 0b0010000000001001..
77315 */
77316#define IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorGreen_SHIFT)) & IRIS_MVPL_BLITBLEND9_BLENDMODE1_BlendModeColorGreen_MASK)
77317/*! @} */
77318
77319/*! @name BLITBLEND9_BLENDMODE2 - Open GL and Open VG blending modes for color blue and alpha */
77320/*! @{ */
77321#define IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeColorBlue_MASK (0xFFFFU)
77322#define IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeColorBlue_SHIFT (0U)
77323/*! BlendModeColorBlue - Blue component blend mode
77324 * 0b1000000000000110..
77325 * 0b1000000000000111..
77326 * 0b1000000000001000..
77327 * 0b1000000000001010..
77328 * 0b1000000000001011..
77329 * 0b0010000000000000..
77330 * 0b0010000000000001..
77331 * 0b0010000000000010..
77332 * 0b0010000000000011..
77333 * 0b0010000000000100..
77334 * 0b0010000000000101..
77335 * 0b0010000000000110..
77336 * 0b0010000000000111..
77337 * 0b0010000000001000..
77338 * 0b0010000000001001..
77339 */
77340#define IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeColorBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeColorBlue_SHIFT)) & IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeColorBlue_MASK)
77341#define IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeAlpha_MASK (0xFFFF0000U)
77342#define IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeAlpha_SHIFT (16U)
77343/*! BlendModeAlpha - Alpha component blend mode
77344 * 0b1000000000000110..
77345 * 0b1000000000000111..
77346 * 0b1000000000001000..
77347 * 0b1000000000001010..
77348 * 0b1000000000001011..
77349 * 0b0010000000000000..
77350 * 0b0010000000000001..
77351 * 0b0010000000000010..
77352 * 0b0010000000000011..
77353 * 0b0010000000000100..
77354 * 0b0010000000000101..
77355 * 0b0010000000000110..
77356 * 0b0010000000000111..
77357 * 0b0010000000001000..
77358 * 0b0010000000001001..
77359 */
77360#define IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeAlpha_SHIFT)) & IRIS_MVPL_BLITBLEND9_BLENDMODE2_BlendModeAlpha_MASK)
77361/*! @} */
77362
77363/*! @name BLITBLEND9_DIRECTSETUP - Direct Control of the BlitBlend Datapath multiplexers, do not change */
77364/*! @{ */
77365#define IRIS_MVPL_BLITBLEND9_DIRECTSETUP_ColorDebug_MASK (0x3FFU)
77366#define IRIS_MVPL_BLITBLEND9_DIRECTSETUP_ColorDebug_SHIFT (0U)
77367/*! ColorDebug - Sets the multiplexers of the color datapath directly, do not change
77368 */
77369#define IRIS_MVPL_BLITBLEND9_DIRECTSETUP_ColorDebug(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_DIRECTSETUP_ColorDebug_SHIFT)) & IRIS_MVPL_BLITBLEND9_DIRECTSETUP_ColorDebug_MASK)
77370#define IRIS_MVPL_BLITBLEND9_DIRECTSETUP_AlphaDebug_MASK (0x3FF0000U)
77371#define IRIS_MVPL_BLITBLEND9_DIRECTSETUP_AlphaDebug_SHIFT (16U)
77372/*! AlphaDebug - Sets the multiplexers of the alpha datapath directly, do not change
77373 */
77374#define IRIS_MVPL_BLITBLEND9_DIRECTSETUP_AlphaDebug(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_DIRECTSETUP_AlphaDebug_SHIFT)) & IRIS_MVPL_BLITBLEND9_DIRECTSETUP_AlphaDebug_MASK)
77375/*! @} */
77376
77377/*! @name BLITBLEND9_PRIMCONTROLWORD - Value of last received primary control word */
77378/*! @{ */
77379#define IRIS_MVPL_BLITBLEND9_PRIMCONTROLWORD_P_VAL_MASK (0xFFFFFFFFU)
77380#define IRIS_MVPL_BLITBLEND9_PRIMCONTROLWORD_P_VAL_SHIFT (0U)
77381/*! P_VAL - Value of last received control word on primary input. If a 39 bit pixel channel is
77382 * connected, the mapping is as follows: p_val[31:0] = { data[37:22], data[19:12], data[9:2] }. For
77383 * debug purposes only, read when stable only, otherwise read data might be corrupted.
77384 */
77385#define IRIS_MVPL_BLITBLEND9_PRIMCONTROLWORD_P_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_PRIMCONTROLWORD_P_VAL_SHIFT)) & IRIS_MVPL_BLITBLEND9_PRIMCONTROLWORD_P_VAL_MASK)
77386/*! @} */
77387
77388/*! @name BLITBLEND9_SECCONTROLWORD - Value of last received secondary control word */
77389/*! @{ */
77390#define IRIS_MVPL_BLITBLEND9_SECCONTROLWORD_S_VAL_MASK (0xFFFFFFFFU)
77391#define IRIS_MVPL_BLITBLEND9_SECCONTROLWORD_S_VAL_SHIFT (0U)
77392/*! S_VAL - Value of last received control word on secondary input. If a 39 bit pixel channel is
77393 * connected, the mapping is as follows: s_val[31:0] = { data[37:22], data[19:12], data[9:2] }. For
77394 * debug purposes only, read when stable only, otherwise read data might be corrupted.
77395 */
77396#define IRIS_MVPL_BLITBLEND9_SECCONTROLWORD_S_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_BLITBLEND9_SECCONTROLWORD_S_VAL_SHIFT)) & IRIS_MVPL_BLITBLEND9_SECCONTROLWORD_S_VAL_MASK)
77397/*! @} */
77398
77399/*! @name STORE9_LOCKUNLOCK - Register to change the protection status of this address block. */
77400/*! @{ */
77401#define IRIS_MVPL_STORE9_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
77402#define IRIS_MVPL_STORE9_LOCKUNLOCK_LockUnlock_SHIFT (0U)
77403/*! LockUnlock - The protection status is changed by writing one of the following key values to this field:
77404 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
77405 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
77406 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
77407 * 0b10110101111000100100011001101110..Disables privilege protection.
77408 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
77409 */
77410#define IRIS_MVPL_STORE9_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_STORE9_LOCKUNLOCK_LockUnlock_MASK)
77411/*! @} */
77412
77413/*! @name STORE9_LOCKSTATUS - Protection status of this address block. */
77414/*! @{ */
77415#define IRIS_MVPL_STORE9_LOCKSTATUS_LockStatus_MASK (0x1U)
77416#define IRIS_MVPL_STORE9_LOCKSTATUS_LockStatus_SHIFT (0U)
77417/*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
77418 */
77419#define IRIS_MVPL_STORE9_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_STORE9_LOCKSTATUS_LockStatus_MASK)
77420#define IRIS_MVPL_STORE9_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
77421#define IRIS_MVPL_STORE9_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
77422/*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
77423 */
77424#define IRIS_MVPL_STORE9_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_STORE9_LOCKSTATUS_PrivilegeStatus_MASK)
77425#define IRIS_MVPL_STORE9_LOCKSTATUS_FreezeStatus_MASK (0x100U)
77426#define IRIS_MVPL_STORE9_LOCKSTATUS_FreezeStatus_SHIFT (8U)
77427/*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
77428 */
77429#define IRIS_MVPL_STORE9_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_STORE9_LOCKSTATUS_FreezeStatus_MASK)
77430/*! @} */
77431
77432/*! @name STORE9_STATICCONTROL - Store unit static control register. */
77433/*! @{ */
77434#define IRIS_MVPL_STORE9_STATICCONTROL_ShdEn_MASK (0x1U)
77435#define IRIS_MVPL_STORE9_STATICCONTROL_ShdEn_SHIFT (0U)
77436/*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed).
77437 */
77438#define IRIS_MVPL_STORE9_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_STORE9_STATICCONTROL_ShdEn_MASK)
77439#define IRIS_MVPL_STORE9_STATICCONTROL_BaseAddressAutoUpdate_MASK (0x100U)
77440#define IRIS_MVPL_STORE9_STATICCONTROL_BaseAddressAutoUpdate_SHIFT (8U)
77441/*! BaseAddressAutoUpdate - If enabled (value 1) the base address is automatically updated at the
77442 * start of each frame. This update is then executed independently of the ShdEn setting. When
77443 * disabled ShdEn controls the update of the base address operation register.
77444 */
77445#define IRIS_MVPL_STORE9_STATICCONTROL_BaseAddressAutoUpdate(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATICCONTROL_BaseAddressAutoUpdate_SHIFT)) & IRIS_MVPL_STORE9_STATICCONTROL_BaseAddressAutoUpdate_MASK)
77446/*! @} */
77447
77448/*! @name STORE9_BURSTBUFFERMANAGEMENT - Burst Buffer setup register. */
77449/*! @{ */
77450#define IRIS_MVPL_STORE9_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK (0x1F00U)
77451#define IRIS_MVPL_STORE9_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT (8U)
77452/*! SetBurstLength - Set this to the burst length that should be used on the AXI interface. Please
77453 * note that SetBurstLength has to be smaller or equal to MaxBurstLength. Only a power of two may
77454 * be specified as burst length. Please set this to at least 2 for 64bit pixels, otherwise
77455 * performance will suffer.
77456 */
77457#define IRIS_MVPL_STORE9_BURSTBUFFERMANAGEMENT_SetBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_BURSTBUFFERMANAGEMENT_SetBurstLength_SHIFT)) & IRIS_MVPL_STORE9_BURSTBUFFERMANAGEMENT_SetBurstLength_MASK)
77458/*! @} */
77459
77460/*! @name STORE9_RINGBUFSTARTADDR - Ring buffer setup for destination. */
77461/*! @{ */
77462#define IRIS_MVPL_STORE9_RINGBUFSTARTADDR_RingBufStartAddr_MASK (0xFFFFFFFFU)
77463#define IRIS_MVPL_STORE9_RINGBUFSTARTADDR_RingBufStartAddr_SHIFT (0U)
77464/*! RingBufStartAddr - Start address of the ring buffer. Must be aligned to SetBurstLength x 8 bytes.
77465 */
77466#define IRIS_MVPL_STORE9_RINGBUFSTARTADDR_RingBufStartAddr(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_RINGBUFSTARTADDR_RingBufStartAddr_SHIFT)) & IRIS_MVPL_STORE9_RINGBUFSTARTADDR_RingBufStartAddr_MASK)
77467/*! @} */
77468
77469/*! @name STORE9_RINGBUFWRAPADDR - Ring buffer setup for destination. */
77470/*! @{ */
77471#define IRIS_MVPL_STORE9_RINGBUFWRAPADDR_RingBufWrapAddr_MASK (0xFFFFFFFFU)
77472#define IRIS_MVPL_STORE9_RINGBUFWRAPADDR_RingBufWrapAddr_SHIFT (0U)
77473/*! RingBufWrapAddr - End address of the ring buffer (last byte of the buffer plus one).
77474 */
77475#define IRIS_MVPL_STORE9_RINGBUFWRAPADDR_RingBufWrapAddr(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_RINGBUFWRAPADDR_RingBufWrapAddr_SHIFT)) & IRIS_MVPL_STORE9_RINGBUFWRAPADDR_RingBufWrapAddr_MASK)
77476/*! @} */
77477
77478/*! @name STORE9_BASEADDRESS - Destination buffer base address. */
77479/*! @{ */
77480#define IRIS_MVPL_STORE9_BASEADDRESS_BaseAddress_MASK (0xFFFFFFFFU)
77481#define IRIS_MVPL_STORE9_BASEADDRESS_BaseAddress_SHIFT (0U)
77482/*! BaseAddress - Byte aligned start address of the destination buffer. For 32 bit pixels
77483 * BaseAddress[1:0] must be set 0 and for 16 bit pixels BaseAddress[0] must be set 0.
77484 */
77485#define IRIS_MVPL_STORE9_BASEADDRESS_BaseAddress(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_BASEADDRESS_BaseAddress_SHIFT)) & IRIS_MVPL_STORE9_BASEADDRESS_BaseAddress_MASK)
77486/*! @} */
77487
77488/*! @name STORE9_DESTINATIONBUFFERATTRIBUTES - Destination buffer attributes. */
77489/*! @{ */
77490#define IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_Stride_MASK (0x1FFFFU)
77491#define IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_Stride_SHIFT (0U)
77492/*! Stride - Destination buffer stride in bytes minus one, used for address generation. For a pixel
77493 * width of 32 bits Stride has to be dividable by 4 and given minus one and for a pixel width of
77494 * 16 bit Stride has to be dividable by two and given minus one.
77495 */
77496#define IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_Stride(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_Stride_SHIFT)) & IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_Stride_MASK)
77497#define IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel_MASK (0x7F000000U)
77498#define IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel_SHIFT (24U)
77499/*! BitsPerPixel - Size of a pixel in the destination buffer in bits. Has to be a power of two, 18
77500 * or 24. When 64 bit is selected, input pixels are converted into a 32 bit value that is
77501 * replicated into low and high word of the 64 bit output. Set SetBurstLength at least to 2 in that case
77502 * to get best possible performance.
77503 */
77504#define IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel_SHIFT)) & IRIS_MVPL_STORE9_DESTINATIONBUFFERATTRIBUTES_BitsPerPixel_MASK)
77505/*! @} */
77506
77507/*! @name STORE9_DESTINATIONBUFFERDIMENSION - Destination buffer dimension. */
77508/*! @{ */
77509#define IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineWidth_MASK (0x3FFFU)
77510#define IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineWidth_SHIFT (0U)
77511/*! LineWidth - Width of the destination buffer in pixels minus one.
77512 */
77513#define IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineWidth_SHIFT)) & IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineWidth_MASK)
77514#define IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineCount_MASK (0x3FFF0000U)
77515#define IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineCount_SHIFT (16U)
77516/*! LineCount - Number of lines of the destination buffer in pixels minus one.
77517 */
77518#define IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineCount(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineCount_SHIFT)) & IRIS_MVPL_STORE9_DESTINATIONBUFFERDIMENSION_LineCount_MASK)
77519/*! @} */
77520
77521/*! @name STORE9_FRAMEOFFSET - Offset between destination frame and buffer. */
77522/*! @{ */
77523#define IRIS_MVPL_STORE9_FRAMEOFFSET_FrameXOffset_MASK (0x7FFFU)
77524#define IRIS_MVPL_STORE9_FRAMEOFFSET_FrameXOffset_SHIFT (0U)
77525/*! FrameXOffset - Horizontal offset (X).
77526 */
77527#define IRIS_MVPL_STORE9_FRAMEOFFSET_FrameXOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_FRAMEOFFSET_FrameXOffset_SHIFT)) & IRIS_MVPL_STORE9_FRAMEOFFSET_FrameXOffset_MASK)
77528#define IRIS_MVPL_STORE9_FRAMEOFFSET_FrameYOffset_MASK (0x7FFF0000U)
77529#define IRIS_MVPL_STORE9_FRAMEOFFSET_FrameYOffset_SHIFT (16U)
77530/*! FrameYOffset - Vertical offset (Y).
77531 */
77532#define IRIS_MVPL_STORE9_FRAMEOFFSET_FrameYOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_FRAMEOFFSET_FrameYOffset_SHIFT)) & IRIS_MVPL_STORE9_FRAMEOFFSET_FrameYOffset_MASK)
77533/*! @} */
77534
77535/*! @name STORE9_COLORCOMPONENTBITS - Color component size of destination buffer */
77536/*! @{ */
77537#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsAlpha_MASK (0xFU)
77538#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsAlpha_SHIFT (0U)
77539/*! ComponentBitsAlpha - Alpha component bits.
77540 */
77541#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsAlpha_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsAlpha_MASK)
77542#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsBlue_MASK (0xF00U)
77543#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsBlue_SHIFT (8U)
77544/*! ComponentBitsBlue - Blue/V component bits.
77545 */
77546#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsBlue_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsBlue_MASK)
77547#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsGreen_MASK (0xF0000U)
77548#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsGreen_SHIFT (16U)
77549/*! ComponentBitsGreen - Green/U component bits.
77550 */
77551#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsGreen_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsGreen_MASK)
77552#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsRed_MASK (0xF000000U)
77553#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsRed_SHIFT (24U)
77554/*! ComponentBitsRed - Red/Y component bits.
77555 */
77556#define IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsRed_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTBITS_ComponentBitsRed_MASK)
77557/*! @} */
77558
77559/*! @name STORE9_COLORCOMPONENTSHIFT - Color component offset of destination buffer. */
77560/*! @{ */
77561#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftAlpha_MASK (0x1FU)
77562#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftAlpha_SHIFT (0U)
77563/*! ComponentShiftAlpha - Alpha component shift.
77564 */
77565#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftAlpha_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftAlpha_MASK)
77566#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftBlue_MASK (0x1F00U)
77567#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftBlue_SHIFT (8U)
77568/*! ComponentShiftBlue - Blue/V component shift.
77569 */
77570#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftBlue_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftBlue_MASK)
77571#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftGreen_MASK (0x1F0000U)
77572#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftGreen_SHIFT (16U)
77573/*! ComponentShiftGreen - Green/U component shift.
77574 */
77575#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftGreen_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftGreen_MASK)
77576#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftRed_MASK (0x1F000000U)
77577#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftRed_SHIFT (24U)
77578/*! ComponentShiftRed - Red/Y component shift.
77579 */
77580#define IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftRed_SHIFT)) & IRIS_MVPL_STORE9_COLORCOMPONENTSHIFT_ComponentShiftRed_MASK)
77581/*! @} */
77582
77583/*! @name STORE9_CONTROL - Store unit dynamic control register */
77584/*! @{ */
77585#define IRIS_MVPL_STORE9_CONTROL_ColorDitherEnable_MASK (0x1U)
77586#define IRIS_MVPL_STORE9_CONTROL_ColorDitherEnable_SHIFT (0U)
77587/*! ColorDitherEnable - Controls whether spatial dithering (value 1) or LSB truncation (value 0) is
77588 * used when ComponentBitsRed/Green/Blue is smaller than 10 bits for Store derivate or 8 bit for
77589 * StoreL derivate.
77590 */
77591#define IRIS_MVPL_STORE9_CONTROL_ColorDitherEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_ColorDitherEnable_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_ColorDitherEnable_MASK)
77592#define IRIS_MVPL_STORE9_CONTROL_AlphaDitherEnable_MASK (0x2U)
77593#define IRIS_MVPL_STORE9_CONTROL_AlphaDitherEnable_SHIFT (1U)
77594/*! AlphaDitherEnable - Controls whether spatial dithering (value 1) or LSB truncation (value 0) is
77595 * used when ComponentBitsAlpha is smaller than 8 bits.
77596 */
77597#define IRIS_MVPL_STORE9_CONTROL_AlphaDitherEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_AlphaDitherEnable_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_AlphaDitherEnable_MASK)
77598#define IRIS_MVPL_STORE9_CONTROL_DitherOffset_MASK (0xF0U)
77599#define IRIS_MVPL_STORE9_CONTROL_DitherOffset_SHIFT (4U)
77600/*! DitherOffset - Dither offset that is additionally applied to the spatial offset, which is
77601 * internally generated from the pixel position. Can be used by SW to generate image sequences with
77602 * temporal dithering.
77603 */
77604#define IRIS_MVPL_STORE9_CONTROL_DitherOffset(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_DitherOffset_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_DitherOffset_MASK)
77605#define IRIS_MVPL_STORE9_CONTROL_GammaApplyEnable_MASK (0x1000U)
77606#define IRIS_MVPL_STORE9_CONTROL_GammaApplyEnable_SHIFT (12U)
77607/*! GammaApplyEnable - Enable gamma conversion stage to apply gamma function. This gamma function
77608 * converts the pixel data from linear color space to non-linear color space before writing it to
77609 * AXI.
77610 */
77611#define IRIS_MVPL_STORE9_CONTROL_GammaApplyEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_GammaApplyEnable_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_GammaApplyEnable_MASK)
77612#define IRIS_MVPL_STORE9_CONTROL_YUVConversionMode_MASK (0x30000U)
77613#define IRIS_MVPL_STORE9_CONTROL_YUVConversionMode_SHIFT (16U)
77614/*! YUVConversionMode - Enables different kind of RGB to YUV conversions.
77615 * 0b00..No conversion. Input data must be RGB.
77616 * 0b01..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6 (standard definition TV).
77617 * Input range is 16..235 for Y and 16..240 for U/V.
77618 * 0b10..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.601-6, but assuming full range YUV
77619 * inputs (0..255). Most typically used for computer graphics (e.g. for JPEG encoding).
77620 * 0b11..Conversion from YCbCr (YUV) to RGB according to ITU recommendation BT.709-5 part 2 (high definition TV).
77621 * Input range is 16..235 for Y and 16..240 for U/V.
77622 */
77623#define IRIS_MVPL_STORE9_CONTROL_YUVConversionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_YUVConversionMode_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_YUVConversionMode_MASK)
77624#define IRIS_MVPL_STORE9_CONTROL_RasterMode_MASK (0xC0000U)
77625#define IRIS_MVPL_STORE9_CONTROL_RasterMode_SHIFT (18U)
77626/*! RasterMode - Selects a method for destination buffer data from input pixels.
77627 * 0b00..RGBA or YUV 4:4:4 pixel buffer.
77628 * 0b01..[Store derivate only] Packed YUV 4:2:2 pixel buffer. Effect is that U samples are written for pixels
77629 * with even and V samples for odd column index only. So BitsPerPixel must be set to the size that a pair of YU
77630 * or YV has in memory (most typically 16 bits). All correlated widths and horizontal offsets must be even.
77631 * 0b10..[Store derivate only] RLAD compressed bit stream.
77632 */
77633#define IRIS_MVPL_STORE9_CONTROL_RasterMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_RasterMode_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_RasterMode_MASK)
77634#define IRIS_MVPL_STORE9_CONTROL_YUV422DownsamplingMode_MASK (0x300000U)
77635#define IRIS_MVPL_STORE9_CONTROL_YUV422DownsamplingMode_SHIFT (20U)
77636/*! YUV422DownsamplingMode - Selects a method for horizontal down-sampling when RasterMode is YUV422.
77637 * 0b00..Nearest mode. Discards all odd samples, outputs even samples.
77638 * 0b01..Linear coaligned mode. 3 nearest UV samples are combined in linear filter to get one output sample.
77639 * 0b10..Linear interspersed mode. 2 nearest UV samples are combined in linear filter to get one output sample.
77640 */
77641#define IRIS_MVPL_STORE9_CONTROL_YUV422DownsamplingMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_CONTROL_YUV422DownsamplingMode_SHIFT)) & IRIS_MVPL_STORE9_CONTROL_YUV422DownsamplingMode_MASK)
77642/*! @} */
77643
77644/*! @name STORE9_ENCODECONTROL - Control options for RLAD compression. */
77645/*! @{ */
77646#define IRIS_MVPL_STORE9_ENCODECONTROL_CompressionMode_MASK (0x1U)
77647#define IRIS_MVPL_STORE9_ENCODECONTROL_CompressionMode_SHIFT (0U)
77648/*! CompressionMode - Algorithm to use for compression.
77649 * 0b0..Run-Length Adaptive Dithering (lossy compression).
77650 * 0b1..Run-Length Adaptive Dithering (lossy compression; uniform package size).
77651 */
77652#define IRIS_MVPL_STORE9_ENCODECONTROL_CompressionMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODECONTROL_CompressionMode_SHIFT)) & IRIS_MVPL_STORE9_ENCODECONTROL_CompressionMode_MASK)
77653#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsRed_MASK (0xF0000U)
77654#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsRed_SHIFT (16U)
77655/*! RLADCompBitsRed - Maximum for average number of bits per compressed pixel for Red or Y (luma) channel.
77656 */
77657#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsRed_SHIFT)) & IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsRed_MASK)
77658#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsGreen_MASK (0xF00000U)
77659#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsGreen_SHIFT (20U)
77660/*! RLADCompBitsGreen - Maximum for average number of bits per compressed pixel for Green or U (chroma) channel.
77661 */
77662#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsGreen_SHIFT)) & IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsGreen_MASK)
77663#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsBlue_MASK (0xF000000U)
77664#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsBlue_SHIFT (24U)
77665/*! RLADCompBitsBlue - Maximum for average number of bits per compressed pixel for Blue or V (chroma) channel.
77666 */
77667#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsBlue_SHIFT)) & IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsBlue_MASK)
77668#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsAlpha_MASK (0xF0000000U)
77669#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsAlpha_SHIFT (28U)
77670/*! RLADCompBitsAlpha - Maximum for average number of bits per compressed pixel for Alpha channel.
77671 */
77672#define IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsAlpha_SHIFT)) & IRIS_MVPL_STORE9_ENCODECONTROL_RLADCompBitsAlpha_MASK)
77673/*! @} */
77674
77675/*! @name STORE9_DESTINATIONBUFFERLENGTH - Destination buffer length for compressed data. */
77676/*! @{ */
77677#define IRIS_MVPL_STORE9_DESTINATIONBUFFERLENGTH_RLEWordsMax_MASK (0x1FFFFFFFU)
77678#define IRIS_MVPL_STORE9_DESTINATIONBUFFERLENGTH_RLEWordsMax_SHIFT (0U)
77679/*! RLEWordsMax - Number of 32-bit words minus one that are reserved for the destination buffer in
77680 * case that RasterMode is ENCODE. The actual number used can be read from RLEWords field.
77681 */
77682#define IRIS_MVPL_STORE9_DESTINATIONBUFFERLENGTH_RLEWordsMax(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_DESTINATIONBUFFERLENGTH_RLEWordsMax_SHIFT)) & IRIS_MVPL_STORE9_DESTINATIONBUFFERLENGTH_RLEWordsMax_MASK)
77683/*! @} */
77684
77685/*! @name STORE9_START - Store unit start register */
77686/*! @{ */
77687#define IRIS_MVPL_STORE9_START_Start_MASK (0x1U)
77688#define IRIS_MVPL_STORE9_START_Start_SHIFT (0U)
77689/*! Start - Writing a one starts processing of the pixel engine.
77690 */
77691#define IRIS_MVPL_STORE9_START_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_START_Start_SHIFT)) & IRIS_MVPL_STORE9_START_Start_MASK)
77692/*! @} */
77693
77694/*! @name STORE9_ENCODERSTATUS - Status information of the RLAD encoder. */
77695/*! @{ */
77696#define IRIS_MVPL_STORE9_ENCODERSTATUS_RLEWords_MASK (0x1FFFFFFFU)
77697#define IRIS_MVPL_STORE9_ENCODERSTATUS_RLEWords_SHIFT (0U)
77698/*! RLEWords - Number of 32-bit words minus one that was used for the compressed buffer.
77699 */
77700#define IRIS_MVPL_STORE9_ENCODERSTATUS_RLEWords(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODERSTATUS_RLEWords_SHIFT)) & IRIS_MVPL_STORE9_ENCODERSTATUS_RLEWords_MASK)
77701#define IRIS_MVPL_STORE9_ENCODERSTATUS_BufferTooSmall_MASK (0x80000000U)
77702#define IRIS_MVPL_STORE9_ENCODERSTATUS_BufferTooSmall_SHIFT (31U)
77703/*! BufferTooSmall - The buffer size given by RLEWordsMax is too small. Not the complete input frame could be encoded.
77704 */
77705#define IRIS_MVPL_STORE9_ENCODERSTATUS_BufferTooSmall(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_ENCODERSTATUS_BufferTooSmall_SHIFT)) & IRIS_MVPL_STORE9_ENCODERSTATUS_BufferTooSmall_MASK)
77706/*! @} */
77707
77708/*! @name STORE9_WRITEADDRESS - Ring buffer synchronization. */
77709/*! @{ */
77710#define IRIS_MVPL_STORE9_WRITEADDRESS_WriteAddress_MASK (0xFFFFFFFFU)
77711#define IRIS_MVPL_STORE9_WRITEADDRESS_WriteAddress_SHIFT (0U)
77712/*! WriteAddress - Last burst address that was written to the destination buffer.
77713 */
77714#define IRIS_MVPL_STORE9_WRITEADDRESS_WriteAddress(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_WRITEADDRESS_WriteAddress_SHIFT)) & IRIS_MVPL_STORE9_WRITEADDRESS_WriteAddress_MASK)
77715/*! @} */
77716
77717/*! @name STORE9_FRAMEPROPERTIES - Ring buffer synchronization. */
77718/*! @{ */
77719#define IRIS_MVPL_STORE9_FRAMEPROPERTIES_FieldId_MASK (0x1U)
77720#define IRIS_MVPL_STORE9_FRAMEPROPERTIES_FieldId_SHIFT (0U)
77721/*! FieldId - Field identifier for interlaced video streams (0/1 = even/odd line indices of
77722 * progressive frame). Status is updated with begin of a new field.
77723 */
77724#define IRIS_MVPL_STORE9_FRAMEPROPERTIES_FieldId(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_FRAMEPROPERTIES_FieldId_SHIFT)) & IRIS_MVPL_STORE9_FRAMEPROPERTIES_FieldId_MASK)
77725/*! @} */
77726
77727/*! @name STORE9_BURSTBUFFERPROPERTIES - Burst Buffer Property register */
77728/*! @{ */
77729#define IRIS_MVPL_STORE9_BURSTBUFFERPROPERTIES_MaxBurstLength_MASK (0x1F00U)
77730#define IRIS_MVPL_STORE9_BURSTBUFFERPROPERTIES_MaxBurstLength_SHIFT (8U)
77731/*! MaxBurstLength - Maximum Burst Length that can be configured.
77732 */
77733#define IRIS_MVPL_STORE9_BURSTBUFFERPROPERTIES_MaxBurstLength(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_BURSTBUFFERPROPERTIES_MaxBurstLength_SHIFT)) & IRIS_MVPL_STORE9_BURSTBUFFERPROPERTIES_MaxBurstLength_MASK)
77734/*! @} */
77735
77736/*! @name STORE9_LASTCONTROLWORD - Shows the last control word received */
77737/*! @{ */
77738#define IRIS_MVPL_STORE9_LASTCONTROLWORD_L_VAL_MASK (0xFFFFFFFFU)
77739#define IRIS_MVPL_STORE9_LASTCONTROLWORD_L_VAL_SHIFT (0U)
77740/*! L_VAL - Shows the last control word received from the pixel engine. If a 39 bit pixel channel is
77741 * connected, the mapping is as follows: l_val[31:0] = { data[37:22], data[19:12], data[9:2] }.
77742 * For debug purposes only, read when stable only, otherwise read data might be corrupted.
77743 */
77744#define IRIS_MVPL_STORE9_LASTCONTROLWORD_L_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_LASTCONTROLWORD_L_VAL_SHIFT)) & IRIS_MVPL_STORE9_LASTCONTROLWORD_L_VAL_MASK)
77745/*! @} */
77746
77747/*! @name STORE9_PERFCOUNTER - Performance counter result */
77748/*! @{ */
77749#define IRIS_MVPL_STORE9_PERFCOUNTER_PerfResult_MASK (0xFFFFFFFFU)
77750#define IRIS_MVPL_STORE9_PERFCOUNTER_PerfResult_SHIFT (0U)
77751/*! PerfResult - Returns the performance counter value. Please note that a sw reset during a frame
77752 * can potentially produce invalid results in the first frame afterwards. For debug purposes only,
77753 * read when stable only, otherwise read data might be corrupted.
77754 */
77755#define IRIS_MVPL_STORE9_PERFCOUNTER_PerfResult(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_PERFCOUNTER_PerfResult_SHIFT)) & IRIS_MVPL_STORE9_PERFCOUNTER_PerfResult_MASK)
77756/*! @} */
77757
77758/*! @name STORE9_STATUS - Shows status information */
77759/*! @{ */
77760#define IRIS_MVPL_STORE9_STATUS_StatusBusy_MASK (0x1U)
77761#define IRIS_MVPL_STORE9_STATUS_StatusBusy_SHIFT (0U)
77762/*! StatusBusy - Store unit is busy
77763 */
77764#define IRIS_MVPL_STORE9_STATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_StatusBusy_SHIFT)) & IRIS_MVPL_STORE9_STATUS_StatusBusy_MASK)
77765#define IRIS_MVPL_STORE9_STATUS_StatusBuffersIdle_MASK (0x10U)
77766#define IRIS_MVPL_STORE9_STATUS_StatusBuffersIdle_SHIFT (4U)
77767/*! StatusBuffersIdle - AXI interface buffers are idle
77768 */
77769#define IRIS_MVPL_STORE9_STATUS_StatusBuffersIdle(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_StatusBuffersIdle_SHIFT)) & IRIS_MVPL_STORE9_STATUS_StatusBuffersIdle_MASK)
77770#define IRIS_MVPL_STORE9_STATUS_StatusRequest_MASK (0x20U)
77771#define IRIS_MVPL_STORE9_STATUS_StatusRequest_SHIFT (5U)
77772/*! StatusRequest - Store unit requesting on the AXI interface, waiting for acknowledge
77773 */
77774#define IRIS_MVPL_STORE9_STATUS_StatusRequest(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_StatusRequest_SHIFT)) & IRIS_MVPL_STORE9_STATUS_StatusRequest_MASK)
77775#define IRIS_MVPL_STORE9_STATUS_StatusComplete_MASK (0x40U)
77776#define IRIS_MVPL_STORE9_STATUS_StatusComplete_SHIFT (6U)
77777/*! StatusComplete - Store unit completed all requested AXI transfers
77778 */
77779#define IRIS_MVPL_STORE9_STATUS_StatusComplete(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_StatusComplete_SHIFT)) & IRIS_MVPL_STORE9_STATUS_StatusComplete_MASK)
77780#define IRIS_MVPL_STORE9_STATUS_PixelbusError_MASK (0x100U)
77781#define IRIS_MVPL_STORE9_STATUS_PixelbusError_SHIFT (8U)
77782/*! PixelbusError - A pixel bus error has occured. Write 1 to clear.
77783 */
77784#define IRIS_MVPL_STORE9_STATUS_PixelbusError(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_PixelbusError_SHIFT)) & IRIS_MVPL_STORE9_STATUS_PixelbusError_MASK)
77785#define IRIS_MVPL_STORE9_STATUS_EncoderOverflow_MASK (0x10000U)
77786#define IRIS_MVPL_STORE9_STATUS_EncoderOverflow_SHIFT (16U)
77787/*! EncoderOverflow - An overflow error has occured in encoder. Write 1 to clear.
77788 */
77789#define IRIS_MVPL_STORE9_STATUS_EncoderOverflow(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_EncoderOverflow_SHIFT)) & IRIS_MVPL_STORE9_STATUS_EncoderOverflow_MASK)
77790#define IRIS_MVPL_STORE9_STATUS_EncoderStallPixel_MASK (0x20000U)
77791#define IRIS_MVPL_STORE9_STATUS_EncoderStallPixel_SHIFT (17U)
77792/*! EncoderStallPixel - The encoder stalled input pixels during a frame. Write 1 to clear.
77793 */
77794#define IRIS_MVPL_STORE9_STATUS_EncoderStallPixel(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_STORE9_STATUS_EncoderStallPixel_SHIFT)) & IRIS_MVPL_STORE9_STATUS_EncoderStallPixel_MASK)
77795/*! @} */
77796
77797/*! @name CONSTFRAME0_LOCKUNLOCK - Register to change the protection status of this address block. */
77798/*! @{ */
77799#define IRIS_MVPL_CONSTFRAME0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
77800#define IRIS_MVPL_CONSTFRAME0_LOCKUNLOCK_LockUnlock_SHIFT (0U)
77801/*! LockUnlock - The protection status is changed by writing one of the following key values to this field:
77802 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
77803 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
77804 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
77805 * 0b10110101111000100100011001101110..Disables privilege protection.
77806 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
77807 */
77808#define IRIS_MVPL_CONSTFRAME0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_CONSTFRAME0_LOCKUNLOCK_LockUnlock_MASK)
77809/*! @} */
77810
77811/*! @name CONSTFRAME0_LOCKSTATUS - Protection status of this address block. */
77812/*! @{ */
77813#define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_LockStatus_MASK (0x1U)
77814#define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_LockStatus_SHIFT (0U)
77815/*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
77816 */
77817#define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_LockStatus_MASK)
77818#define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
77819#define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
77820/*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
77821 */
77822#define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_PrivilegeStatus_MASK)
77823#define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_FreezeStatus_MASK (0x100U)
77824#define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_FreezeStatus_SHIFT (8U)
77825/*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
77826 */
77827#define IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME0_LOCKSTATUS_FreezeStatus_MASK)
77828/*! @} */
77829
77830/*! @name CONSTFRAME0_STATICCONTROL - ConstFrame unit static control register */
77831/*! @{ */
77832#define IRIS_MVPL_CONSTFRAME0_STATICCONTROL_ShdEn_MASK (0x1U)
77833#define IRIS_MVPL_CONSTFRAME0_STATICCONTROL_ShdEn_SHIFT (0U)
77834/*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed).
77835 */
77836#define IRIS_MVPL_CONSTFRAME0_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_CONSTFRAME0_STATICCONTROL_ShdEn_MASK)
77837/*! @} */
77838
77839/*! @name CONSTFRAME0_FRAMEDIMENSIONS - Output frame dimensions. */
77840/*! @{ */
77841#define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
77842#define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
77843/*! FrameWidth - Frame width in pixels minus one.
77844 */
77845#define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameWidth_MASK)
77846#define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
77847#define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
77848/*! FrameHeight - Frame height in pixels minus one.
77849 */
77850#define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_FrameHeight_MASK)
77851#define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
77852#define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
77853/*! EmptyFrame - When enabled output frame is empty. FrameWidth/Height settings have no effect then.
77854 * Can be used to load shadows or to generate synchronization signals only (frame/sequence
77855 * complete).
77856 */
77857#define IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_CONSTFRAME0_FRAMEDIMENSIONS_EmptyFrame_MASK)
77858/*! @} */
77859
77860/*! @name CONSTFRAME0_CONSTANTCOLOR - Color of output frame. */
77861/*! @{ */
77862#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantAlpha_MASK (0xFFU)
77863#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantAlpha_SHIFT (0U)
77864/*! ConstantAlpha - Alpha component.
77865 */
77866#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantAlpha_SHIFT)) & IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantAlpha_MASK)
77867#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantBlue_MASK (0xFF00U)
77868#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantBlue_SHIFT (8U)
77869/*! ConstantBlue - Blue component.
77870 */
77871#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantBlue_SHIFT)) & IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantBlue_MASK)
77872#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantGreen_MASK (0xFF0000U)
77873#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantGreen_SHIFT (16U)
77874/*! ConstantGreen - Green component.
77875 */
77876#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantGreen_SHIFT)) & IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantGreen_MASK)
77877#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantRed_MASK (0xFF000000U)
77878#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantRed_SHIFT (24U)
77879/*! ConstantRed - Red component.
77880 */
77881#define IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantRed_SHIFT)) & IRIS_MVPL_CONSTFRAME0_CONSTANTCOLOR_ConstantRed_MASK)
77882/*! @} */
77883
77884/*! @name CONSTFRAME0_CONTROLTRIGGER - ConstFrame unit trigger register */
77885/*! @{ */
77886#define IRIS_MVPL_CONSTFRAME0_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
77887#define IRIS_MVPL_CONSTFRAME0_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
77888/*! ShdTokGen - Writing a 1 to this will load shadow registers into the active configuration with
77889 * the next start of frame and send a shadow load token to subsequent units.
77890 */
77891#define IRIS_MVPL_CONSTFRAME0_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_CONSTFRAME0_CONTROLTRIGGER_ShdTokGen_MASK)
77892/*! @} */
77893
77894/*! @name CONSTFRAME0_START - ConstFrame unit start register */
77895/*! @{ */
77896#define IRIS_MVPL_CONSTFRAME0_START_Start_MASK (0x1U)
77897#define IRIS_MVPL_CONSTFRAME0_START_Start_SHIFT (0U)
77898/*! Start - Writing a one starts processing, it is recommended to use this for debug purposes only.
77899 */
77900#define IRIS_MVPL_CONSTFRAME0_START_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_START_Start_SHIFT)) & IRIS_MVPL_CONSTFRAME0_START_Start_MASK)
77901/*! @} */
77902
77903/*! @name CONSTFRAME0_STATUS - Shows status information */
77904/*! @{ */
77905#define IRIS_MVPL_CONSTFRAME0_STATUS_StatusBusy_MASK (0x1U)
77906#define IRIS_MVPL_CONSTFRAME0_STATUS_StatusBusy_SHIFT (0U)
77907/*! StatusBusy - Unit is busy.
77908 */
77909#define IRIS_MVPL_CONSTFRAME0_STATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_STATUS_StatusBusy_SHIFT)) & IRIS_MVPL_CONSTFRAME0_STATUS_StatusBusy_MASK)
77910#define IRIS_MVPL_CONSTFRAME0_STATUS_ShadowStatus_MASK (0x2U)
77911#define IRIS_MVPL_CONSTFRAME0_STATUS_ShadowStatus_SHIFT (1U)
77912/*! ShadowStatus - Shadow load status. 1 if shadow load has been triggered and not yet consumed, 0
77913 * if shadow load is already consumed or has not yet been triggered.
77914 */
77915#define IRIS_MVPL_CONSTFRAME0_STATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME0_STATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME0_STATUS_ShadowStatus_MASK)
77916/*! @} */
77917
77918/*! @name EXTDST0_LOCKUNLOCK - Register to change the protection status of this address block. */
77919/*! @{ */
77920#define IRIS_MVPL_EXTDST0_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
77921#define IRIS_MVPL_EXTDST0_LOCKUNLOCK_LockUnlock_SHIFT (0U)
77922/*! LockUnlock - The protection status is changed by writing one of the following key values to this field:
77923 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
77924 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
77925 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
77926 * 0b10110101111000100100011001101110..Disables privilege protection.
77927 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
77928 */
77929#define IRIS_MVPL_EXTDST0_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_EXTDST0_LOCKUNLOCK_LockUnlock_MASK)
77930/*! @} */
77931
77932/*! @name EXTDST0_LOCKSTATUS - Protection status of this address block. */
77933/*! @{ */
77934#define IRIS_MVPL_EXTDST0_LOCKSTATUS_LockStatus_MASK (0x1U)
77935#define IRIS_MVPL_EXTDST0_LOCKSTATUS_LockStatus_SHIFT (0U)
77936/*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
77937 */
77938#define IRIS_MVPL_EXTDST0_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_EXTDST0_LOCKSTATUS_LockStatus_MASK)
77939#define IRIS_MVPL_EXTDST0_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
77940#define IRIS_MVPL_EXTDST0_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
77941/*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
77942 */
77943#define IRIS_MVPL_EXTDST0_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_EXTDST0_LOCKSTATUS_PrivilegeStatus_MASK)
77944#define IRIS_MVPL_EXTDST0_LOCKSTATUS_FreezeStatus_MASK (0x100U)
77945#define IRIS_MVPL_EXTDST0_LOCKSTATUS_FreezeStatus_SHIFT (8U)
77946/*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
77947 */
77948#define IRIS_MVPL_EXTDST0_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_EXTDST0_LOCKSTATUS_FreezeStatus_MASK)
77949/*! @} */
77950
77951/*! @name EXTDST0_STATICCONTROL - External Destination static control register */
77952/*! @{ */
77953#define IRIS_MVPL_EXTDST0_STATICCONTROL_ShdEn_MASK (0x1U)
77954#define IRIS_MVPL_EXTDST0_STATICCONTROL_ShdEn_SHIFT (0U)
77955/*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed).
77956 */
77957#define IRIS_MVPL_EXTDST0_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_EXTDST0_STATICCONTROL_ShdEn_MASK)
77958#define IRIS_MVPL_EXTDST0_STATICCONTROL_KICK_MODE_MASK (0x100U)
77959#define IRIS_MVPL_EXTDST0_STATICCONTROL_KICK_MODE_SHIFT (8U)
77960/*! KICK_MODE - Operation mode of generated kick signal
77961 * 0b0..kick generation by KICK field only
77962 * 0b1..kick signal from external allowed
77963 */
77964#define IRIS_MVPL_EXTDST0_STATICCONTROL_KICK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_STATICCONTROL_KICK_MODE_SHIFT)) & IRIS_MVPL_EXTDST0_STATICCONTROL_KICK_MODE_MASK)
77965#define IRIS_MVPL_EXTDST0_STATICCONTROL_PerfCountMode_MASK (0x1000U)
77966#define IRIS_MVPL_EXTDST0_STATICCONTROL_PerfCountMode_SHIFT (12U)
77967/*! PerfCountMode - Value 1 enables performance counter mode, which does not generate an output
77968 * frame but processes input data as fast as possible instead. Can be used to determine the maximum
77969 * possible read-out performance of display buffers.
77970 */
77971#define IRIS_MVPL_EXTDST0_STATICCONTROL_PerfCountMode(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_STATICCONTROL_PerfCountMode_SHIFT)) & IRIS_MVPL_EXTDST0_STATICCONTROL_PerfCountMode_MASK)
77972/*! @} */
77973
77974/*! @name EXTDST0_CONTROL - External Destination shadowed control register */
77975/*! @{ */
77976#define IRIS_MVPL_EXTDST0_CONTROL_GammaApplyEnable_MASK (0x1U)
77977#define IRIS_MVPL_EXTDST0_CONTROL_GammaApplyEnable_SHIFT (0U)
77978/*! GammaApplyEnable - Enable gamma conversion stage to apply gamma function. This gamma function
77979 * converts the pixel data from linear color space to non-linear color space before they are output.
77980 */
77981#define IRIS_MVPL_EXTDST0_CONTROL_GammaApplyEnable(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_CONTROL_GammaApplyEnable_SHIFT)) & IRIS_MVPL_EXTDST0_CONTROL_GammaApplyEnable_MASK)
77982/*! @} */
77983
77984/*! @name EXTDST0_SOFTWAREKICK - External Destination software kick */
77985/*! @{ */
77986#define IRIS_MVPL_EXTDST0_SOFTWAREKICK_KICK_MASK (0x1U)
77987#define IRIS_MVPL_EXTDST0_SOFTWAREKICK_KICK_SHIFT (0U)
77988/*! KICK - Software kick, forces a kick signal independent of KICK_MODE. Write 1 to send kick.
77989 */
77990#define IRIS_MVPL_EXTDST0_SOFTWAREKICK_KICK(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_SOFTWAREKICK_KICK_SHIFT)) & IRIS_MVPL_EXTDST0_SOFTWAREKICK_KICK_MASK)
77991/*! @} */
77992
77993/*! @name EXTDST0_STATUS - External Destination Unit current status */
77994/*! @{ */
77995#define IRIS_MVPL_EXTDST0_STATUS_CNT_ERR_STS_MASK (0x1U)
77996#define IRIS_MVPL_EXTDST0_STATUS_CNT_ERR_STS_SHIFT (0U)
77997/*! CNT_ERR_STS - Pixel count error
77998 */
77999#define IRIS_MVPL_EXTDST0_STATUS_CNT_ERR_STS(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_STATUS_CNT_ERR_STS_SHIFT)) & IRIS_MVPL_EXTDST0_STATUS_CNT_ERR_STS_MASK)
78000/*! @} */
78001
78002/*! @name EXTDST0_CONTROLWORD - Value of last received control word */
78003/*! @{ */
78004#define IRIS_MVPL_EXTDST0_CONTROLWORD_CW_VAL_MASK (0xFFFFFFFFU)
78005#define IRIS_MVPL_EXTDST0_CONTROLWORD_CW_VAL_SHIFT (0U)
78006/*! CW_VAL - Value of last received control word
78007 */
78008#define IRIS_MVPL_EXTDST0_CONTROLWORD_CW_VAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_CONTROLWORD_CW_VAL_SHIFT)) & IRIS_MVPL_EXTDST0_CONTROLWORD_CW_VAL_MASK)
78009/*! @} */
78010
78011/*! @name EXTDST0_CURPIXELCNT - pixel count of currently running frame */
78012/*! @{ */
78013#define IRIS_MVPL_EXTDST0_CURPIXELCNT_C_XVAL_MASK (0xFFFFU)
78014#define IRIS_MVPL_EXTDST0_CURPIXELCNT_C_XVAL_SHIFT (0U)
78015/*! C_XVAL - value of horizontal pixel counter, internal counter counting from max-1 to 0
78016 */
78017#define IRIS_MVPL_EXTDST0_CURPIXELCNT_C_XVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_CURPIXELCNT_C_XVAL_SHIFT)) & IRIS_MVPL_EXTDST0_CURPIXELCNT_C_XVAL_MASK)
78018#define IRIS_MVPL_EXTDST0_CURPIXELCNT_C_YVAL_MASK (0xFFFF0000U)
78019#define IRIS_MVPL_EXTDST0_CURPIXELCNT_C_YVAL_SHIFT (16U)
78020/*! C_YVAL - value of vertical line counter, internal counter counting from max-1 to 0
78021 */
78022#define IRIS_MVPL_EXTDST0_CURPIXELCNT_C_YVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_CURPIXELCNT_C_YVAL_SHIFT)) & IRIS_MVPL_EXTDST0_CURPIXELCNT_C_YVAL_MASK)
78023/*! @} */
78024
78025/*! @name EXTDST0_LASTPIXELCNT - pixel count between last two control words */
78026/*! @{ */
78027#define IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_XVAL_MASK (0xFFFFU)
78028#define IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_XVAL_SHIFT (0U)
78029/*! L_XVAL - value of horizontal pixel counter
78030 */
78031#define IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_XVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_XVAL_SHIFT)) & IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_XVAL_MASK)
78032#define IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_YVAL_MASK (0xFFFF0000U)
78033#define IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_YVAL_SHIFT (16U)
78034/*! L_YVAL - value of vertical line counter
78035 */
78036#define IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_YVAL(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_YVAL_SHIFT)) & IRIS_MVPL_EXTDST0_LASTPIXELCNT_L_YVAL_MASK)
78037/*! @} */
78038
78039/*! @name EXTDST0_PERFCOUNTER - Performance counter result */
78040/*! @{ */
78041#define IRIS_MVPL_EXTDST0_PERFCOUNTER_PerfResult_MASK (0xFFFFFFFFU)
78042#define IRIS_MVPL_EXTDST0_PERFCOUNTER_PerfResult_SHIFT (0U)
78043/*! PerfResult - Returns the performance counter value. Returns number of cycles of the last frame
78044 * on the input. To calculate the performance divide the known number of pixels of the frame by
78045 * this number. For debug purposes only, read when stable only, otherwise read data might be
78046 * corrupted.
78047 */
78048#define IRIS_MVPL_EXTDST0_PERFCOUNTER_PerfResult(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_EXTDST0_PERFCOUNTER_PerfResult_SHIFT)) & IRIS_MVPL_EXTDST0_PERFCOUNTER_PerfResult_MASK)
78049/*! @} */
78050
78051/*! @name CONSTFRAME4_LOCKUNLOCK - Register to change the protection status of this address block. */
78052/*! @{ */
78053#define IRIS_MVPL_CONSTFRAME4_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
78054#define IRIS_MVPL_CONSTFRAME4_LOCKUNLOCK_LockUnlock_SHIFT (0U)
78055/*! LockUnlock - The protection status is changed by writing one of the following key values to this field:
78056 * 0b01010110010100011111011101100011..Decrements the unlock counter. When the counter value is null, lock protection is active. Reset counter value is 1.
78057 * 0b01101001000111011011100100110110..Increments the unlock counter. Max allowed value is 15.
78058 * 0b10101110111010010101110011011100..Enables privilege protection. Disabled after reset.
78059 * 0b10110101111000100100011001101110..Disables privilege protection.
78060 * 0b11111011111010001011000111100110..Freezes current protection status. Writing keys to this register has no more effect until reset.
78061 */
78062#define IRIS_MVPL_CONSTFRAME4_LOCKUNLOCK_LockUnlock(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_LOCKUNLOCK_LockUnlock_SHIFT)) & IRIS_MVPL_CONSTFRAME4_LOCKUNLOCK_LockUnlock_MASK)
78063/*! @} */
78064
78065/*! @name CONSTFRAME4_LOCKSTATUS - Protection status of this address block. */
78066/*! @{ */
78067#define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_LockStatus_MASK (0x1U)
78068#define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_LockStatus_SHIFT (0U)
78069/*! LockStatus - Current status of lock protection: 0 = inactive (unlock counter > 0), 1 = active (unlock counter == 0).
78070 */
78071#define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_LockStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_LockStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_LockStatus_MASK)
78072#define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_PrivilegeStatus_MASK (0x10U)
78073#define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_PrivilegeStatus_SHIFT (4U)
78074/*! PrivilegeStatus - Current status of privilege protection: 0 = inactive , 1 = active.
78075 */
78076#define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_PrivilegeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_PrivilegeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_PrivilegeStatus_MASK)
78077#define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_FreezeStatus_MASK (0x100U)
78078#define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_FreezeStatus_SHIFT (8U)
78079/*! FreezeStatus - Current freeze status: 0 = protection status can be changed, 1 = cannot be changed.
78080 */
78081#define IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_FreezeStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_FreezeStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME4_LOCKSTATUS_FreezeStatus_MASK)
78082/*! @} */
78083
78084/*! @name CONSTFRAME4_STATICCONTROL - ConstFrame unit static control register */
78085/*! @{ */
78086#define IRIS_MVPL_CONSTFRAME4_STATICCONTROL_ShdEn_MASK (0x1U)
78087#define IRIS_MVPL_CONSTFRAME4_STATICCONTROL_ShdEn_SHIFT (0U)
78088/*! ShdEn - Enables shadowing of all RWS type registers (0=write_through, 1=shadowed).
78089 */
78090#define IRIS_MVPL_CONSTFRAME4_STATICCONTROL_ShdEn(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_STATICCONTROL_ShdEn_SHIFT)) & IRIS_MVPL_CONSTFRAME4_STATICCONTROL_ShdEn_MASK)
78091/*! @} */
78092
78093/*! @name CONSTFRAME4_FRAMEDIMENSIONS - Output frame dimensions. */
78094/*! @{ */
78095#define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameWidth_MASK (0x3FFFU)
78096#define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameWidth_SHIFT (0U)
78097/*! FrameWidth - Frame width in pixels minus one.
78098 */
78099#define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameWidth(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameWidth_SHIFT)) & IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameWidth_MASK)
78100#define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameHeight_MASK (0x3FFF0000U)
78101#define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameHeight_SHIFT (16U)
78102/*! FrameHeight - Frame height in pixels minus one.
78103 */
78104#define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameHeight(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameHeight_SHIFT)) & IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_FrameHeight_MASK)
78105#define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_EmptyFrame_MASK (0x80000000U)
78106#define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_EmptyFrame_SHIFT (31U)
78107/*! EmptyFrame - When enabled output frame is empty. FrameWidth/Height settings have no effect then.
78108 * Can be used to load shadows or to generate synchronization signals only (frame/sequence
78109 * complete).
78110 */
78111#define IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_EmptyFrame(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_EmptyFrame_SHIFT)) & IRIS_MVPL_CONSTFRAME4_FRAMEDIMENSIONS_EmptyFrame_MASK)
78112/*! @} */
78113
78114/*! @name CONSTFRAME4_CONSTANTCOLOR - Color of output frame. */
78115/*! @{ */
78116#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantAlpha_MASK (0xFFU)
78117#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantAlpha_SHIFT (0U)
78118/*! ConstantAlpha - Alpha component.
78119 */
78120#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantAlpha(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantAlpha_SHIFT)) & IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantAlpha_MASK)
78121#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantBlue_MASK (0xFF00U)
78122#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantBlue_SHIFT (8U)
78123/*! ConstantBlue - Blue component.
78124 */
78125#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantBlue(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantBlue_SHIFT)) & IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantBlue_MASK)
78126#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantGreen_MASK (0xFF0000U)
78127#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantGreen_SHIFT (16U)
78128/*! ConstantGreen - Green component.
78129 */
78130#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantGreen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantGreen_SHIFT)) & IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantGreen_MASK)
78131#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantRed_MASK (0xFF000000U)
78132#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantRed_SHIFT (24U)
78133/*! ConstantRed - Red component.
78134 */
78135#define IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantRed(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantRed_SHIFT)) & IRIS_MVPL_CONSTFRAME4_CONSTANTCOLOR_ConstantRed_MASK)
78136/*! @} */
78137
78138/*! @name CONSTFRAME4_CONTROLTRIGGER - ConstFrame unit trigger register */
78139/*! @{ */
78140#define IRIS_MVPL_CONSTFRAME4_CONTROLTRIGGER_ShdTokGen_MASK (0x1U)
78141#define IRIS_MVPL_CONSTFRAME4_CONTROLTRIGGER_ShdTokGen_SHIFT (0U)
78142/*! ShdTokGen - Writing a 1 to this will load shadow registers into the active configuration with
78143 * the next start of frame and send a shadow load token to subsequent units.
78144 */
78145#define IRIS_MVPL_CONSTFRAME4_CONTROLTRIGGER_ShdTokGen(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_CONTROLTRIGGER_ShdTokGen_SHIFT)) & IRIS_MVPL_CONSTFRAME4_CONTROLTRIGGER_ShdTokGen_MASK)
78146/*! @} */
78147
78148/*! @name CONSTFRAME4_START - ConstFrame unit start register */
78149/*! @{ */
78150#define IRIS_MVPL_CONSTFRAME4_START_Start_MASK (0x1U)
78151#define IRIS_MVPL_CONSTFRAME4_START_Start_SHIFT (0U)
78152/*! Start - Writing a one starts processing, it is recommended to use this for debug purposes only.
78153 */
78154#define IRIS_MVPL_CONSTFRAME4_START_Start(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_START_Start_SHIFT)) & IRIS_MVPL_CONSTFRAME4_START_Start_MASK)
78155/*! @} */
78156
78157/*! @name CONSTFRAME4_STATUS - Shows status information */
78158/*! @{ */
78159#define IRIS_MVPL_CONSTFRAME4_STATUS_StatusBusy_MASK (0x1U)
78160#define IRIS_MVPL_CONSTFRAME4_STATUS_StatusBusy_SHIFT (0U)
78161/*! StatusBusy - Unit is busy.
78162 */
78163#define IRIS_MVPL_CONSTFRAME4_STATUS_StatusBusy(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_STATUS_StatusBusy_SHIFT)) & IRIS_MVPL_CONSTFRAME4_STATUS_StatusBusy_MASK)
78164#define IRIS_MVPL_CONSTFRAME4_STATUS_ShadowStatus_MASK (0x2U)
78165#define IRIS_MVPL_CONSTFRAME4_STATUS_ShadowStatus_SHIFT (1U)
78166/*! ShadowStatus - Shadow load status. 1 if shadow load has been triggered and not yet consumed, 0
78167 * if shadow load is already consumed or has not yet been triggered.
78168 */
78169#define IRIS_MVPL_CONSTFRAME4_STATUS_ShadowStatus(x) (((uint32_t)(((uint32_t)(x)) << IRIS_MVPL_CONSTFRAME4_STATUS_ShadowStatus_SHIFT)) & IRIS_MVPL_CONSTFRAME4_STATUS_ShadowStatus_MASK)
78170/*! @} */
78171
78172/*! @name EXTDST4_LOCKUNLOCK - Register to change the protection status of this address block. */
78173/*! @{ */
78174#define IRIS_MVPL_EXTDST4_LOCKUNLOCK_LockUnlock_MASK (0xFFFFFFFFU)
78175#define IRIS_MVPL_EXTDST4_LOCKUNLOCK_LockUnlock_SHIFT (0U)
78176/*! LockUnlock - The protection status is changed by writing one of the fo